From 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 Mon Sep 17 00:00:00 2001 From: Chris Johns Date: Sat, 23 Dec 2017 18:18:56 +1100 Subject: Remove make preinstall A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254. --- bsps/arm/altera-cyclone-v/headers.am | 45 + bsps/arm/altera-cyclone-v/include/bsp.h | 50 + .../altera-cyclone-v/include/bsp/alt_16550_uart.h | 1555 ++ .../include/bsp/alt_address_space.h | 825 + bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h | 964 + .../altera-cyclone-v/include/bsp/alt_clock_group.h | 114 + .../include/bsp/alt_clock_manager.h | 1434 ++ bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h | 1007 + .../altera-cyclone-v/include/bsp/alt_dma_common.h | 162 + .../altera-cyclone-v/include/bsp/alt_dma_program.h | 951 + .../include/bsp/alt_generalpurpose_io.h | 1254 + .../altera-cyclone-v/include/bsp/alt_hwlibs_ver.h | 56 + bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h | 2024 ++ .../include/bsp/alt_interrupt_common.h | 533 + .../include/bsp/alt_mpu_registers.h | 156 + .../include/bsp/alt_qspi_private.h | 167 + .../include/bsp/alt_reset_manager.h | 291 + bsps/arm/altera-cyclone-v/include/bsp/hwlib.h | 189 + bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h | 76 + bsps/arm/altera-cyclone-v/include/bsp/irq.h | 41 + .../include/bsp/socal/alt_acpidmap.h | 3569 +++ .../include/bsp/socal/alt_clkmgr.h | 6464 +++++ .../include/bsp/socal/alt_dmanonsecure.h | 144 + .../include/bsp/socal/alt_dmasecure.h | 144 + .../altera-cyclone-v/include/bsp/socal/alt_gpio.h | 1991 ++ .../altera-cyclone-v/include/bsp/socal/alt_i2c.h | 5940 +++++ .../altera-cyclone-v/include/bsp/socal/alt_l3.h | 6299 +++++ .../altera-cyclone-v/include/bsp/socal/alt_qspi.h | 5951 +++++ .../include/bsp/socal/alt_qspidata.h | 52 + .../include/bsp/socal/alt_rstmgr.h | 3382 +++ .../altera-cyclone-v/include/bsp/socal/alt_sdr.h | 4149 ++++ .../include/bsp/socal/alt_sysmgr.h | 24810 +++++++++++++++++++ .../altera-cyclone-v/include/bsp/socal/alt_uart.h | 5158 ++++ bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h | 8026 ++++++ .../arm/altera-cyclone-v/include/bsp/socal/socal.h | 259 + bsps/arm/altera-cyclone-v/include/tm27.h | 24 + bsps/arm/atsam/headers.am | 269 + bsps/arm/atsam/include/bsp.h | 102 + bsps/arm/atsam/include/bsp/atsam-clock-config.h | 62 + bsps/arm/atsam/include/bsp/atsam-i2c.h | 74 + bsps/arm/atsam/include/bsp/atsam-spi.h | 36 + bsps/arm/atsam/include/bsp/i2c.h | 36 + bsps/arm/atsam/include/bsp/irq.h | 30 + bsps/arm/atsam/include/bsp/pin-config.h | 36 + bsps/arm/atsam/include/bsp/power.h | 245 + bsps/arm/atsam/include/bsp/sc16is752.h | 68 + bsps/arm/atsam/include/bsp/spi.h | 36 + bsps/arm/atsam/include/libchip/chip.h | 124 + bsps/arm/atsam/include/libchip/compiler.h | 476 + bsps/arm/atsam/include/libchip/include/acc.h | 152 + bsps/arm/atsam/include/libchip/include/adc.h | 179 + bsps/arm/atsam/include/libchip/include/aes.h | 68 + bsps/arm/atsam/include/libchip/include/afe_dma.h | 116 + bsps/arm/atsam/include/libchip/include/afec.h | 190 + bsps/arm/atsam/include/libchip/include/chip.h | 1 + bsps/arm/atsam/include/libchip/include/dac_dma.h | 150 + bsps/arm/atsam/include/libchip/include/efc.h | 128 + .../arm/atsam/include/libchip/include/exceptions.h | 52 + bsps/arm/atsam/include/libchip/include/flashd.h | 91 + bsps/arm/atsam/include/libchip/include/gmac.h | 349 + bsps/arm/atsam/include/libchip/include/gmacd.h | 283 + bsps/arm/atsam/include/libchip/include/hsmci.h | 155 + bsps/arm/atsam/include/libchip/include/icm.h | 112 + bsps/arm/atsam/include/libchip/include/isi.h | 200 + bsps/arm/atsam/include/libchip/include/iso7816_4.h | 110 + bsps/arm/atsam/include/libchip/include/mcan.h | 329 + bsps/arm/atsam/include/libchip/include/mcid.h | 170 + bsps/arm/atsam/include/libchip/include/mediaLB.h | 45 + bsps/arm/atsam/include/libchip/include/mpu.h | 222 + bsps/arm/atsam/include/libchip/include/pio.h | 217 + .../atsam/include/libchip/include/pio_capture.h | 79 + bsps/arm/atsam/include/libchip/include/pio_it.h | 117 + bsps/arm/atsam/include/libchip/include/pmc.h | 101 + bsps/arm/atsam/include/libchip/include/pwmc.h | 137 + bsps/arm/atsam/include/libchip/include/qspi.h | 236 + bsps/arm/atsam/include/libchip/include/qspi_dma.h | 115 + bsps/arm/atsam/include/libchip/include/rstc.h | 64 + bsps/arm/atsam/include/libchip/include/rtc.h | 102 + bsps/arm/atsam/include/libchip/include/rtt.h | 82 + .../include/same70/component/component_acc.h | 128 + .../include/same70/component/component_aes.h | 191 + .../include/same70/component/component_afec.h | 483 + .../include/same70/component/component_chipid.h | 123 + .../include/same70/component/component_dacc.h | 184 + .../include/same70/component/component_efc.h | 111 + .../include/same70/component/component_gmac.h | 1240 + .../include/same70/component/component_gpbr.h | 53 + .../include/same70/component/component_hsmci.h | 335 + .../include/same70/component/component_icm.h | 192 + .../include/same70/component/component_isi.h | 280 + .../include/same70/component/component_matrix.h | 301 + .../include/same70/component/component_mcan.h | 845 + .../include/same70/component/component_pio.h | 1711 ++ .../include/same70/component/component_pmc.h | 723 + .../include/same70/component/component_pwm.h | 644 + .../include/same70/component/component_qspi.h | 216 + .../include/same70/component/component_rstc.h | 79 + .../include/same70/component/component_rswdt.h | 72 + .../include/same70/component/component_rtc.h | 234 + .../include/same70/component/component_rtt.h | 71 + .../include/same70/component/component_sdramc.h | 173 + .../include/same70/component/component_smc.h | 144 + .../include/same70/component/component_spi.h | 161 + .../include/same70/component/component_ssc.h | 280 + .../include/same70/component/component_supc.h | 295 + .../include/same70/component/component_tc.h | 346 + .../include/same70/component/component_trng.h | 73 + .../include/same70/component/component_twihs.h | 250 + .../include/same70/component/component_uart.h | 151 + .../include/same70/component/component_usart.h | 478 + .../include/same70/component/component_usbhs.h | 909 + .../include/same70/component/component_utmi.h | 63 + .../include/same70/component/component_wdt.h | 72 + .../include/same70/component/component_xdmac.h | 616 + .../libchip/include/same70/pio/pio_same70j19.h | 431 + .../libchip/include/same70/pio/pio_same70j20.h | 437 + .../libchip/include/same70/pio/pio_same70j21.h | 437 + .../libchip/include/same70/pio/pio_same70n19.h | 495 + .../libchip/include/same70/pio/pio_same70n20.h | 495 + .../libchip/include/same70/pio/pio_same70n21.h | 495 + .../libchip/include/same70/pio/pio_same70q19.h | 668 + .../libchip/include/same70/pio/pio_same70q20.h | 668 + .../libchip/include/same70/pio/pio_same70q21.h | 668 + .../atsam/include/libchip/include/same70/same70.h | 55 + .../include/libchip/include/same70/same70j19.h | 623 + .../include/libchip/include/same70/same70j20.h | 630 + .../include/libchip/include/same70/same70j21.h | 630 + .../include/libchip/include/same70/same70n19.h | 636 + .../include/libchip/include/same70/same70n20.h | 636 + .../include/libchip/include/same70/same70n21.h | 636 + .../include/libchip/include/same70/same70q19.h | 684 + .../include/libchip/include/same70/same70q20.h | 684 + .../include/libchip/include/same70/same70q21.h | 689 + .../include/libchip/include/same70/system_same70.h | 80 + .../include/sams70/component/component_acc.h | 128 + .../include/sams70/component/component_aes.h | 191 + .../include/sams70/component/component_afec.h | 483 + .../include/sams70/component/component_chipid.h | 123 + .../include/sams70/component/component_dacc.h | 184 + .../include/sams70/component/component_efc.h | 111 + .../include/sams70/component/component_gpbr.h | 53 + .../include/sams70/component/component_hsmci.h | 335 + .../include/sams70/component/component_icm.h | 192 + .../include/sams70/component/component_isi.h | 280 + .../include/sams70/component/component_matrix.h | 461 + .../include/sams70/component/component_pio.h | 1711 ++ .../include/sams70/component/component_pmc.h | 786 + .../include/sams70/component/component_pwm.h | 667 + .../include/sams70/component/component_qspi.h | 216 + .../include/sams70/component/component_rstc.h | 79 + .../include/sams70/component/component_rswdt.h | 72 + .../include/sams70/component/component_rtc.h | 234 + .../include/sams70/component/component_rtt.h | 71 + .../include/sams70/component/component_sdramc.h | 173 + .../include/sams70/component/component_smc.h | 144 + .../include/sams70/component/component_spi.h | 161 + .../include/sams70/component/component_ssc.h | 280 + .../include/sams70/component/component_supc.h | 295 + .../include/sams70/component/component_tc.h | 346 + .../include/sams70/component/component_trng.h | 73 + .../include/sams70/component/component_twihs.h | 250 + .../include/sams70/component/component_uart.h | 151 + .../include/sams70/component/component_usart.h | 478 + .../include/sams70/component/component_usbhs.h | 905 + .../include/sams70/component/component_utmi.h | 63 + .../include/sams70/component/component_wdt.h | 72 + .../include/sams70/component/component_xdmac.h | 616 + .../libchip/include/sams70/pio/pio_sams70j19.h | 406 + .../libchip/include/sams70/pio/pio_sams70j20.h | 407 + .../libchip/include/sams70/pio/pio_sams70j21.h | 407 + .../libchip/include/sams70/pio/pio_sams70n19.h | 464 + .../libchip/include/sams70/pio/pio_sams70n20.h | 463 + .../libchip/include/sams70/pio/pio_sams70n21.h | 463 + .../libchip/include/sams70/pio/pio_sams70q19.h | 637 + .../libchip/include/sams70/pio/pio_sams70q20.h | 637 + .../libchip/include/sams70/pio/pio_sams70q21.h | 637 + .../atsam/include/libchip/include/sams70/sams70.h | 55 + .../include/libchip/include/sams70/sams70j19.h | 610 + .../include/libchip/include/sams70/sams70j20.h | 610 + .../include/libchip/include/sams70/sams70j21.h | 610 + .../include/libchip/include/sams70/sams70n19.h | 616 + .../include/libchip/include/sams70/sams70n20.h | 616 + .../include/libchip/include/sams70/sams70n21.h | 616 + .../include/libchip/include/sams70/sams70q19.h | 664 + .../include/libchip/include/sams70/sams70q20.h | 664 + .../include/libchip/include/sams70/sams70q21.h | 664 + .../include/libchip/include/sams70/system_sams70.h | 77 + .../include/samv71/component/component_acc.h | 135 + .../include/samv71/component/component_aes.h | 198 + .../include/samv71/component/component_afec.h | 490 + .../include/samv71/component/component_chipid.h | 123 + .../include/samv71/component/component_dacc.h | 191 + .../include/samv71/component/component_efc.h | 118 + .../include/samv71/component/component_gmac.h | 1246 + .../include/samv71/component/component_gpbr.h | 53 + .../include/samv71/component/component_hsmci.h | 342 + .../include/samv71/component/component_icm.h | 224 + .../include/samv71/component/component_isi.h | 287 + .../include/samv71/component/component_matrix.h | 181 + .../include/samv71/component/component_mcan.h | 868 + .../include/samv71/component/component_mlb.h | 192 + .../include/samv71/component/component_pio.h | 1717 ++ .../include/samv71/component/component_pmc.h | 729 + .../include/samv71/component/component_pwm.h | 651 + .../include/samv71/component/component_qspi.h | 223 + .../include/samv71/component/component_rstc.h | 79 + .../include/samv71/component/component_rswdt.h | 72 + .../include/samv71/component/component_rtc.h | 241 + .../include/samv71/component/component_rtt.h | 71 + .../include/samv71/component/component_sdramc.h | 180 + .../include/samv71/component/component_smc.h | 151 + .../include/samv71/component/component_spi.h | 168 + .../include/samv71/component/component_ssc.h | 287 + .../include/samv71/component/component_supc.h | 302 + .../include/samv71/component/component_tc.h | 353 + .../include/samv71/component/component_trng.h | 80 + .../include/samv71/component/component_twihs.h | 264 + .../include/samv71/component/component_uart.h | 162 + .../include/samv71/component/component_usart.h | 485 + .../include/samv71/component/component_usbhs.h | 961 + .../include/samv71/component/component_utmi.h | 63 + .../include/samv71/component/component_wdt.h | 72 + .../include/samv71/component/component_xdmac.h | 625 + .../libchip/include/samv71/pio/pio_samv71j19.h | 441 + .../libchip/include/samv71/pio/pio_samv71j20.h | 442 + .../libchip/include/samv71/pio/pio_samv71j21.h | 442 + .../libchip/include/samv71/pio/pio_samv71n19.h | 499 + .../libchip/include/samv71/pio/pio_samv71n20.h | 498 + .../libchip/include/samv71/pio/pio_samv71n21.h | 498 + .../libchip/include/samv71/pio/pio_samv71q19.h | 672 + .../libchip/include/samv71/pio/pio_samv71q20.h | 672 + .../libchip/include/samv71/pio/pio_samv71q21.h | 672 + .../atsam/include/libchip/include/samv71/samv71.h | 58 + .../include/libchip/include/samv71/samv71j19.h | 637 + .../include/libchip/include/samv71/samv71j20.h | 637 + .../include/libchip/include/samv71/samv71j21.h | 637 + .../include/libchip/include/samv71/samv71n19.h | 643 + .../include/libchip/include/samv71/samv71n20.h | 643 + .../include/libchip/include/samv71/samv71n21.h | 643 + .../include/libchip/include/samv71/samv71q19.h | 691 + .../include/libchip/include/samv71/samv71q20.h | 691 + .../include/libchip/include/samv71/samv71q21.h | 696 + .../include/libchip/include/samv71/system_samv71.h | 80 + bsps/arm/atsam/include/libchip/include/sdramc.h | 68 + bsps/arm/atsam/include/libchip/include/smc.h | 174 + bsps/arm/atsam/include/libchip/include/spi.h | 116 + bsps/arm/atsam/include/libchip/include/spi_dma.h | 146 + bsps/arm/atsam/include/libchip/include/ssc.h | 72 + bsps/arm/atsam/include/libchip/include/supc.h | 75 + bsps/arm/atsam/include/libchip/include/tc.h | 77 + bsps/arm/atsam/include/libchip/include/timetick.h | 101 + bsps/arm/atsam/include/libchip/include/trace.h | 231 + bsps/arm/atsam/include/libchip/include/trng.h | 50 + bsps/arm/atsam/include/libchip/include/twi.h | 114 + bsps/arm/atsam/include/libchip/include/twid.h | 140 + bsps/arm/atsam/include/libchip/include/uart.h | 68 + bsps/arm/atsam/include/libchip/include/uart_dma.h | 137 + bsps/arm/atsam/include/libchip/include/usart.h | 164 + bsps/arm/atsam/include/libchip/include/usart_dma.h | 137 + bsps/arm/atsam/include/libchip/include/usbhs.h | 1699 ++ bsps/arm/atsam/include/libchip/include/video.h | 79 + bsps/arm/atsam/include/libchip/include/wdt.h | 74 + .../libchip/include/xdma_hardware_interface.h | 58 + bsps/arm/atsam/include/libchip/include/xdmac.h | 640 + bsps/arm/atsam/include/libchip/include/xdmad.h | 253 + bsps/arm/atsam/include/tm27.h | 1 + bsps/arm/beagle/headers.am | 14 + bsps/arm/beagle/include/bsp.h | 364 + bsps/arm/beagle/include/bsp/bbb-gpio.h | 45 + bsps/arm/beagle/include/bsp/bbb-pwm.h | 178 + bsps/arm/beagle/include/bsp/beagleboneblack.h | 72 + bsps/arm/beagle/include/bsp/i2c.h | 211 + bsps/arm/beagle/include/bsp/irq.h | 23 + bsps/arm/beagle/include/tm27.h | 1 + bsps/arm/csb336/headers.am | 11 + bsps/arm/csb336/include/bsp.h | 68 + bsps/arm/csb336/include/bsp/irq.h | 95 + bsps/arm/csb336/include/mc9328mxl.h | 486 + bsps/arm/csb336/include/tm27.h | 1 + bsps/arm/csb337/headers.am | 21 + bsps/arm/csb337/include/at91rm9200.h | 344 + bsps/arm/csb337/include/at91rm9200_dbgu.h | 89 + bsps/arm/csb337/include/at91rm9200_emac.h | 160 + bsps/arm/csb337/include/at91rm9200_gpio.h | 401 + bsps/arm/csb337/include/at91rm9200_mem.h | 115 + bsps/arm/csb337/include/at91rm9200_pmc.h | 169 + bsps/arm/csb337/include/at91rm9200_usart.h | 146 + bsps/arm/csb337/include/bits.h | 48 + bsps/arm/csb337/include/bsp.h | 78 + bsps/arm/csb337/include/bsp/irq.h | 63 + bsps/arm/csb337/include/font8x16.h | 3615 +++ bsps/arm/csb337/include/sed1356.h | 52 + bsps/arm/csb337/include/sed1356_16bit.h | 566 + bsps/arm/csb337/include/tm27.h | 1 + bsps/arm/edb7312/headers.am | 11 + bsps/arm/edb7312/include/bsp.h | 72 + bsps/arm/edb7312/include/bsp/irq.h | 92 + bsps/arm/edb7312/include/ep7312.h | 218 + bsps/arm/edb7312/include/tm27.h | 1 + bsps/arm/gdbarmsim/headers.am | 11 + bsps/arm/gdbarmsim/include/bsp.h | 82 + bsps/arm/gdbarmsim/include/bsp/irq.h | 95 + bsps/arm/gdbarmsim/include/bsp/swi.h | 110 + bsps/arm/gdbarmsim/include/tm27.h | 1 + bsps/arm/gumstix/headers.am | 12 + bsps/arm/gumstix/include/bsp.h | 84 + bsps/arm/gumstix/include/bsp/irq.h | 29 + bsps/arm/gumstix/include/ffuart.h | 48 + bsps/arm/gumstix/include/pxa255.h | 128 + bsps/arm/gumstix/include/tm27.h | 1 + bsps/arm/headers.am | 45 + bsps/arm/imx/headers.am | 22 + .../arm/imx/include/arm/freescale/imx/imx_ccmvar.h | 64 + .../imx/include/arm/freescale/imx/imx_ecspireg.h | 111 + .../arm/imx/include/arm/freescale/imx/imx_gpcreg.h | 162 + .../arm/imx/include/arm/freescale/imx/imx_i2creg.h | 54 + .../imx/include/arm/freescale/imx/imx_iomuxreg.h | 61 + .../imx/include/arm/freescale/imx/imx_iomuxvar.h | 49 + .../arm/imx/include/arm/freescale/imx/imx_srcreg.h | 104 + .../imx/include/arm/freescale/imx/imx_uartreg.h | 174 + .../imx/include/arm/freescale/imx/imx_wdogreg.h | 62 + bsps/arm/imx/include/bsp.h | 84 + bsps/arm/imx/include/bsp/irq.h | 38 + bsps/arm/imx/include/tm27.h | 24 + bsps/arm/include/bsp/arm-a8core-start.h | 55 + bsps/arm/include/bsp/arm-a9mpcore-clock.h | 38 + bsps/arm/include/bsp/arm-a9mpcore-irq.h | 40 + bsps/arm/include/bsp/arm-a9mpcore-regs.h | 133 + bsps/arm/include/bsp/arm-a9mpcore-start.h | 172 + bsps/arm/include/bsp/arm-cp15-start.h | 187 + bsps/arm/include/bsp/arm-errata.h | 121 + bsps/arm/include/bsp/arm-gic-irq.h | 112 + bsps/arm/include/bsp/arm-gic-regs.h | 138 + bsps/arm/include/bsp/arm-gic-tm27.h | 103 + bsps/arm/include/bsp/arm-gic.h | 207 + bsps/arm/include/bsp/arm-pl011-regs.h | 130 + bsps/arm/include/bsp/arm-pl011.h | 51 + bsps/arm/include/bsp/arm-pl050-regs.h | 57 + bsps/arm/include/bsp/arm-pl050.h | 47 + bsps/arm/include/bsp/arm-pl111-fb.h | 44 + bsps/arm/include/bsp/arm-pl111-regs.h | 184 + bsps/arm/include/bsp/arm-release-id.h | 152 + bsps/arm/include/bsp/armv7m-irq.h | 36 + bsps/arm/include/bsp/linker-symbols.h | 167 + bsps/arm/include/bsp/lpc-dma.h | 221 + bsps/arm/include/bsp/lpc-emc.h | 170 + bsps/arm/include/bsp/lpc-i2s.h | 132 + bsps/arm/include/bsp/lpc-lcd.h | 213 + bsps/arm/include/bsp/lpc-timer.h | 159 + bsps/arm/include/bsp/start.h | 183 + bsps/arm/include/cmsis_gcc.h | 1373 + bsps/arm/include/core_cm7.h | 2512 ++ bsps/arm/include/core_cmFunc.h | 87 + bsps/arm/include/core_cmInstr.h | 87 + bsps/arm/include/core_cmSimd.h | 96 + bsps/arm/include/libcpu/am335x.h | 704 + bsps/arm/include/libcpu/mmu.h | 32 + bsps/arm/include/libcpu/omap3.h | 384 + bsps/arm/include/libcpu/omap_timer.h | 39 + bsps/arm/include/uart.h | 163 + bsps/arm/lm3s69xx/headers.am | 15 + bsps/arm/lm3s69xx/include/bsp.h | 52 + bsps/arm/lm3s69xx/include/bsp/io.h | 191 + bsps/arm/lm3s69xx/include/bsp/irq.h | 107 + bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h | 407 + bsps/arm/lm3s69xx/include/bsp/ssi.h | 43 + bsps/arm/lm3s69xx/include/bsp/syscon.h | 43 + bsps/arm/lm3s69xx/include/bsp/uart.h | 46 + bsps/arm/lm3s69xx/include/tm27.h | 1 + bsps/arm/lpc176x/headers.am | 30 + bsps/arm/lpc176x/include/bsp.h | 98 + bsps/arm/lpc176x/include/bsp/adc-defs.h | 96 + bsps/arm/lpc176x/include/bsp/adc.h | 60 + bsps/arm/lpc176x/include/bsp/can-defs.h | 183 + bsps/arm/lpc176x/include/bsp/can.h | 179 + bsps/arm/lpc176x/include/bsp/common-types.h | 118 + bsps/arm/lpc176x/include/bsp/dma.h | 98 + bsps/arm/lpc176x/include/bsp/gpio-defs.h | 218 + bsps/arm/lpc176x/include/bsp/io-defs.h | 142 + bsps/arm/lpc176x/include/bsp/io.h | 88 + bsps/arm/lpc176x/include/bsp/irq.h | 108 + bsps/arm/lpc176x/include/bsp/lpc-clock-config.h | 45 + bsps/arm/lpc176x/include/bsp/lpc-gpio.h | 100 + bsps/arm/lpc176x/include/bsp/lpc176x.h | 1585 ++ bsps/arm/lpc176x/include/bsp/mbed-pinmap.h | 50 + bsps/arm/lpc176x/include/bsp/pwmout-defs.h | 105 + bsps/arm/lpc176x/include/bsp/pwmout.h | 73 + bsps/arm/lpc176x/include/bsp/system-clocks.h | 91 + bsps/arm/lpc176x/include/bsp/timer-defs.h | 449 + bsps/arm/lpc176x/include/bsp/timer.h | 195 + bsps/arm/lpc176x/include/bsp/watchdog-defs.h | 65 + bsps/arm/lpc176x/include/bsp/watchdog.h | 70 + bsps/arm/lpc176x/include/tm27.h | 1 + bsps/arm/lpc24xx/headers.am | 21 + bsps/arm/lpc24xx/include/bsp.h | 128 + bsps/arm/lpc24xx/include/bsp/dma.h | 95 + bsps/arm/lpc24xx/include/bsp/i2c.h | 71 + bsps/arm/lpc24xx/include/bsp/io.h | 1154 + bsps/arm/lpc24xx/include/bsp/irq.h | 140 + bsps/arm/lpc24xx/include/bsp/lcd.h | 91 + bsps/arm/lpc24xx/include/bsp/lpc-clock-config.h | 49 + bsps/arm/lpc24xx/include/bsp/lpc-ethernet-config.h | 130 + bsps/arm/lpc24xx/include/bsp/lpc17xx.h | 207 + bsps/arm/lpc24xx/include/bsp/lpc24xx.h | 2206 ++ bsps/arm/lpc24xx/include/bsp/ssp.h | 47 + bsps/arm/lpc24xx/include/bsp/start-config.h | 121 + bsps/arm/lpc24xx/include/bsp/system-clocks.h | 89 + bsps/arm/lpc24xx/include/tm27.h | 1 + bsps/arm/lpc32xx/headers.am | 19 + bsps/arm/lpc32xx/include/bsp.h | 259 + bsps/arm/lpc32xx/include/bsp/boot.h | 114 + bsps/arm/lpc32xx/include/bsp/emc.h | 161 + bsps/arm/lpc32xx/include/bsp/hsu.h | 68 + bsps/arm/lpc32xx/include/bsp/i2c.h | 269 + bsps/arm/lpc32xx/include/bsp/irq.h | 179 + bsps/arm/lpc32xx/include/bsp/lpc-clock-config.h | 59 + bsps/arm/lpc32xx/include/bsp/lpc-ethernet-config.h | 98 + bsps/arm/lpc32xx/include/bsp/lpc32xx.h | 641 + bsps/arm/lpc32xx/include/bsp/mmu.h | 79 + bsps/arm/lpc32xx/include/bsp/nand-mlc.h | 422 + bsps/arm/lpc32xx/include/tm27.h | 72 + bsps/arm/raspberrypi/headers.am | 20 + bsps/arm/raspberrypi/include/bsp.h | 69 + bsps/arm/raspberrypi/include/bsp/fbcons.h | 47 + bsps/arm/raspberrypi/include/bsp/i2c.h | 95 + bsps/arm/raspberrypi/include/bsp/irq.h | 76 + bsps/arm/raspberrypi/include/bsp/mailbox.h | 32 + bsps/arm/raspberrypi/include/bsp/mmu.h | 68 + bsps/arm/raspberrypi/include/bsp/raspberrypi.h | 572 + bsps/arm/raspberrypi/include/bsp/rpi-fb.h | 55 + bsps/arm/raspberrypi/include/bsp/rpi-gpio.h | 70 + bsps/arm/raspberrypi/include/bsp/spi.h | 77 + bsps/arm/raspberrypi/include/bsp/usart.h | 43 + bsps/arm/raspberrypi/include/bsp/vc.h | 157 + bsps/arm/raspberrypi/include/tm27.h | 1 + bsps/arm/realview-pbx-a9/headers.am | 10 + bsps/arm/realview-pbx-a9/include/bsp.h | 67 + bsps/arm/realview-pbx-a9/include/bsp/irq.h | 102 + bsps/arm/realview-pbx-a9/include/tm27.h | 41 + bsps/arm/rtl22xx/headers.am | 11 + bsps/arm/rtl22xx/include/bsp.h | 226 + bsps/arm/rtl22xx/include/bsp/irq.h | 71 + bsps/arm/rtl22xx/include/lpc22xx.h | 475 + bsps/arm/rtl22xx/include/tm27.h | 1 + bsps/arm/smdk2410/headers.am | 14 + bsps/arm/smdk2410/include/bsp.h | 80 + bsps/arm/smdk2410/include/bsp/irq.h | 96 + bsps/arm/smdk2410/include/s3c2400.h | 676 + bsps/arm/smdk2410/include/s3c2410.h | 825 + bsps/arm/smdk2410/include/s3c24xx.h | 17 + bsps/arm/smdk2410/include/smc.h | 44 + bsps/arm/smdk2410/include/tm27.h | 1 + bsps/arm/stm32f4/headers.am | 29 + bsps/arm/stm32f4/include/bsp.h | 54 + bsps/arm/stm32f4/include/bsp/i2c.h | 96 + bsps/arm/stm32f4/include/bsp/io.h | 416 + bsps/arm/stm32f4/include/bsp/irq.h | 141 + bsps/arm/stm32f4/include/bsp/rcc.h | 196 + bsps/arm/stm32f4/include/bsp/stm32_i2c.h | 113 + bsps/arm/stm32f4/include/bsp/stm32_usart.h | 110 + bsps/arm/stm32f4/include/bsp/stm32f10xxx_exti.h | 50 + bsps/arm/stm32f4/include/bsp/stm32f10xxx_gpio.h | 51 + bsps/arm/stm32f4/include/bsp/stm32f10xxx_rcc.h | 48 + bsps/arm/stm32f4/include/bsp/stm32f4.h | 258 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h | 320 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_exti.h | 64 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h | 83 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_gpio.h | 39 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_otgfs.h | 445 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h | 47 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h | 289 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h | 108 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_tim.h | 206 + bsps/arm/stm32f4/include/bsp/usart.h | 45 + bsps/arm/stm32f4/include/tm27.h | 1 + bsps/arm/tms570/headers.am | 63 + bsps/arm/tms570/include/bsp.h | 42 + bsps/arm/tms570/include/bsp/irq.h | 160 + bsps/arm/tms570/include/bsp/system-clocks.h | 62 + bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h | 626 + bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h | 72 + bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h | 379 + bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h | 941 + bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h | 183 + bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h | 711 + bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h | 557 + bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h | 126 + bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h | 285 + bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h | 898 + bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h | 468 + bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h | 170 + bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h | 675 + bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h | 618 + bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h | 324 + bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h | 333 + bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h | 363 + bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h | 235 + bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h | 594 + bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h | 230 + bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h | 332 + bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h | 195 + bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h | 120 + bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h | 298 + bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h | 258 + bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h | 309 + bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h | 359 + bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h | 227 + bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h | 450 + bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h | 918 + bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h | 158 + bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h | 695 + bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h | 170 + bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h | 84 + bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h | 170 + bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h | 190 + bsps/arm/tms570/include/bsp/tms570-pinmux.h | 137 + bsps/arm/tms570/include/bsp/tms570-pins.h | 10 + bsps/arm/tms570/include/bsp/tms570-pom.h | 60 + bsps/arm/tms570/include/bsp/tms570-rti.h | 46 + bsps/arm/tms570/include/bsp/tms570-sci-driver.h | 65 + bsps/arm/tms570/include/bsp/tms570-sci.h | 45 + bsps/arm/tms570/include/bsp/tms570-vim.h | 48 + bsps/arm/tms570/include/bsp/tms570.h | 137 + bsps/arm/tms570/include/bsp/tms570_hwinit.h | 31 + bsps/arm/tms570/include/bsp/tms570_selftest.h | 214 + .../tms570/include/bsp/tms570_selftest_parity.h | 110 + bsps/arm/tms570/include/bsp/tms570lc4357-pins.h | 1114 + bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h | 690 + bsps/arm/tms570/include/tm27.h | 1 + bsps/arm/xilinx-zynq/headers.am | 15 + bsps/arm/xilinx-zynq/include/bsp.h | 80 + .../arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h | 73 + bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h | 35 + bsps/arm/xilinx-zynq/include/bsp/i2c.h | 50 + bsps/arm/xilinx-zynq/include/bsp/irq.h | 115 + bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h | 150 + bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h | 67 + bsps/arm/xilinx-zynq/include/tm27.h | 36 + bsps/bfin/TLL6527M/headers.am | 7 + bsps/bfin/TLL6527M/include/bsp.h | 129 + bsps/bfin/TLL6527M/include/cplb.h | 47 + bsps/bfin/TLL6527M/include/tm27.h | 50 + bsps/bfin/bf537Stamp/headers.am | 6 + bsps/bfin/bf537Stamp/include/bsp.h | 122 + bsps/bfin/bf537Stamp/include/tm27.h | 1 + bsps/bfin/eZKit533/headers.am | 7 + bsps/bfin/eZKit533/include/bsp.h | 166 + bsps/bfin/eZKit533/include/cplb.h | 47 + bsps/bfin/eZKit533/include/tm27.h | 48 + bsps/bfin/headers.am | 37 + bsps/bfin/include/bf52x.h | 131 + bsps/bfin/include/bsp/interrupt.h | 144 + bsps/bfin/include/libcpu/bf533.h | 135 + bsps/bfin/include/libcpu/bf537.h | 225 + bsps/bfin/include/libcpu/cecRegs.h | 46 + bsps/bfin/include/libcpu/coreTimerRegs.h | 29 + bsps/bfin/include/libcpu/dmaRegs.h | 97 + bsps/bfin/include/libcpu/ebiuRegs.h | 133 + bsps/bfin/include/libcpu/ethernet.h | 54 + bsps/bfin/include/libcpu/ethernetRegs.h | 419 + bsps/bfin/include/libcpu/gpioRegs.h | 36 + bsps/bfin/include/libcpu/interrupt.h | 80 + bsps/bfin/include/libcpu/memoryRegs.h | 58 + bsps/bfin/include/libcpu/mmu.h | 73 + bsps/bfin/include/libcpu/mmuRegs.h | 54 + bsps/bfin/include/libcpu/ppiRegs.h | 58 + bsps/bfin/include/libcpu/rtcRegs.h | 65 + bsps/bfin/include/libcpu/sicRegs.h | 43 + bsps/bfin/include/libcpu/spi.h | 53 + bsps/bfin/include/libcpu/spiRegs.h | 69 + bsps/bfin/include/libcpu/sport.h | 2 + bsps/bfin/include/libcpu/sportRegs.h | 111 + bsps/bfin/include/libcpu/timerRegs.h | 45 + bsps/bfin/include/libcpu/twi.h | 68 + bsps/bfin/include/libcpu/twiRegs.h | 118 + bsps/bfin/include/libcpu/uart.h | 135 + bsps/bfin/include/libcpu/uartRegs.h | 70 + bsps/bfin/include/libcpu/wdogRegs.h | 33 + bsps/epiphany/epiphany_sim/headers.am | 10 + bsps/epiphany/epiphany_sim/include/bsp.h | 65 + bsps/epiphany/epiphany_sim/include/bsp/irq.h | 49 + bsps/epiphany/epiphany_sim/include/tm27.h | 1 + bsps/epiphany/headers.am | 5 + bsps/epiphany/include/bsp/linker-symbols.h | 81 + bsps/headers.am | 83 + bsps/i386/headers.am | 20 + bsps/i386/include/bsp/apic.h | 125 + bsps/i386/include/bsp/irq.h | 96 + bsps/i386/include/bsp/irq_asm.h | 45 + bsps/i386/include/bsp/realmode_int.h | 97 + bsps/i386/include/bsp/smp-imps.h | 245 + bsps/i386/include/bsp/tty_drv.h | 104 + bsps/i386/include/i386_io.h | 73 + bsps/i386/include/libcpu/byteorder.h | 31 + bsps/i386/include/libcpu/cpuModel.h | 51 + bsps/i386/include/libcpu/page.h | 39 + bsps/i386/include/uart.h | 191 + bsps/i386/pc386/headers.am | 25 + bsps/i386/pc386/include/bsp.h | 264 + bsps/i386/pc386/include/bsp/bspimpl.h | 47 + bsps/i386/pc386/include/bsp/exar17d15x.h | 55 + bsps/i386/pc386/include/bsp/fb_default_mode.h | 25 + bsps/i386/pc386/include/bsp/fb_vesa.h | 132 + bsps/i386/pc386/include/bsp/rtd316.h | 77 + bsps/i386/pc386/include/bsp/tblsizes.h | 24 + bsps/i386/pc386/include/bsp/vbe3.h | 619 + bsps/i386/pc386/include/crt.h | 94 + bsps/i386/pc386/include/edid.h | 520 + bsps/i386/pc386/include/rtems/kd.h | 111 + bsps/i386/pc386/include/rtems/keyboard.h | 604 + bsps/i386/pc386/include/rtems/ps2_drv.h | 79 + bsps/i386/pc386/include/rtems/vgacons.h | 49 + bsps/i386/pc386/include/tm27.h | 38 + bsps/include/bsp/VME.h | 133 + bsps/include/bsp/VMEDMA.h | 309 + bsps/include/bsp/bootcard.h | 188 + bsps/include/bsp/bspVmeDmaList.h | 140 + bsps/include/bsp/console-polled.h | 43 + bsps/include/bsp/console-termios.h | 117 + bsps/include/bsp/default-initial-extension.h | 53 + bsps/include/bsp/fatal.h | 153 + bsps/include/bsp/fdt.h | 67 + bsps/include/bsp/gpio.h | 955 + bsps/include/bsp/irq-generic.h | 304 + bsps/include/bsp/irq-info.h | 56 + bsps/include/bsp/mm.h | 41 + bsps/include/bsp/stackalloc.h | 94 + bsps/include/bsp/u-boot.h | 66 + bsps/include/bsp/uart-output-char.h | 60 + bsps/include/bsp/utility.h | 156 + bsps/include/bsp/vmeTsi148.h | 662 + bsps/include/bsp/vmeTsi148DMA.h | 102 + bsps/include/bsp/vmeUniverse.h | 1045 + bsps/include/bsp/vmeUniverseDMA.h | 95 + bsps/include/bsp/vme_am_defs.h | 198 + bsps/include/libchip/am29lv160.h | 55 + bsps/include/libchip/ata.h | 50 + bsps/include/libchip/ata_internal.h | 323 + bsps/include/libchip/cs8900.h | 761 + bsps/include/libchip/disp_hcms29xx.h | 156 + bsps/include/libchip/ds1375-rtc.h | 99 + bsps/include/libchip/greth.h | 152 + bsps/include/libchip/i2c-2b-eeprom.h | 74 + bsps/include/libchip/i2c-ds1621.h | 81 + bsps/include/libchip/i2c-sc620.h | 40 + bsps/include/libchip/i82586var.h | 319 + bsps/include/libchip/icm7170.h | 97 + bsps/include/libchip/ide_ctrl.h | 35 + bsps/include/libchip/ide_ctrl_cfg.h | 123 + bsps/include/libchip/ide_ctrl_io.h | 186 + bsps/include/libchip/if_dcreg.h | 1120 + bsps/include/libchip/if_fxpvar.h | 203 + bsps/include/libchip/m48t08.h | 87 + bsps/include/libchip/mc146818a.h | 68 + bsps/include/libchip/mc68681.h | 122 + bsps/include/libchip/ns16550.h | 99 + bsps/include/libchip/ns16550_p.h | 142 + bsps/include/libchip/open_eth.h | 173 + bsps/include/libchip/rtc.h | 80 + bsps/include/libchip/serial.h | 235 + bsps/include/libchip/sersupp.h | 19 + bsps/include/libchip/smc91111.h | 558 + bsps/include/libchip/smc91111exp.h | 26 + bsps/include/libchip/sonic.h | 458 + bsps/include/libchip/spi-flash-m25p40.h | 44 + bsps/include/libchip/spi-fram-fm25l256.h | 44 + bsps/include/libchip/spi-memdrv.h | 90 + bsps/include/libchip/spi-sd-card.h | 86 + bsps/include/libchip/wd80x3.h | 139 + bsps/include/libchip/z85c30.h | 83 + bsps/include/mpci.h | 56 + bsps/include/rtems/umon.h | 68 + bsps/include/rtems/zilog/z8036.h | 106 + bsps/include/rtems/zilog/z8530.h | 97 + bsps/include/shm_driver.h | 542 + bsps/include/umon/cli.h | 147 + bsps/include/umon/monlib.h | 265 + bsps/include/umon/tfs.h | 214 + bsps/lm32/headers.am | 18 + bsps/lm32/include/bsp/irq.h | 47 + bsps/lm32/include/bsp/milkymist_ac97.h | 76 + bsps/lm32/include/bsp/milkymist_buttons.h | 59 + bsps/lm32/include/bsp/milkymist_dmx.h | 68 + bsps/lm32/include/bsp/milkymist_flash.h | 64 + bsps/lm32/include/bsp/milkymist_gpio.h | 59 + bsps/lm32/include/bsp/milkymist_ir.h | 59 + bsps/lm32/include/bsp/milkymist_memcard.h | 32 + bsps/lm32/include/bsp/milkymist_midi.h | 59 + bsps/lm32/include/bsp/milkymist_pfpu.h | 72 + bsps/lm32/include/bsp/milkymist_tmu.h | 98 + bsps/lm32/include/bsp/milkymist_usbinput.h | 71 + bsps/lm32/include/bsp/milkymist_versions.h | 53 + bsps/lm32/include/bsp/milkymist_video.h | 90 + bsps/lm32/lm32_evr/headers.am | 7 + bsps/lm32/lm32_evr/include/bsp.h | 87 + bsps/lm32/lm32_evr/include/system_conf.h | 180 + bsps/lm32/lm32_evr/include/tm27.h | 38 + bsps/lm32/milkymist/headers.am | 7 + bsps/lm32/milkymist/include/bsp.h | 62 + bsps/lm32/milkymist/include/system_conf.h | 329 + bsps/lm32/milkymist/include/tm27.h | 1 + bsps/m32c/m32cbsp/headers.am | 6 + bsps/m32c/m32cbsp/include/bsp.h | 49 + bsps/m32c/m32cbsp/include/tm27.h | 1 + bsps/m68k/av5282/headers.am | 6 + bsps/m68k/av5282/include/bsp.h | 97 + bsps/m68k/av5282/include/tm27.h | 37 + bsps/m68k/csb360/headers.am | 6 + bsps/m68k/csb360/include/bsp.h | 189 + bsps/m68k/csb360/include/tm27.h | 39 + bsps/m68k/gen68340/headers.am | 11 + bsps/m68k/gen68340/include/bsp.h | 81 + bsps/m68k/gen68340/include/m340timer.h | 85 + bsps/m68k/gen68340/include/m340uart.h | 162 + bsps/m68k/gen68340/include/m68340.h | 145 + bsps/m68k/gen68340/include/m68340.inc | 148 + bsps/m68k/gen68340/include/m68349.inc | 410 + bsps/m68k/gen68340/include/tm27.h | 1 + bsps/m68k/gen68360/headers.am | 6 + bsps/m68k/gen68360/include/bsp.h | 111 + bsps/m68k/gen68360/include/tm27.h | 40 + bsps/m68k/genmcf548x/headers.am | 10 + bsps/m68k/genmcf548x/include/bsp.h | 134 + bsps/m68k/genmcf548x/include/bsp/irq.h | 96 + bsps/m68k/genmcf548x/include/tm27.h | 37 + bsps/m68k/headers.am | 47 + bsps/m68k/include/bsp/linker-symbols.h | 84 + bsps/m68k/include/mcf5206/mcf5206e.h | 609 + bsps/m68k/include/mcf5206/mcfmbus.h | 129 + bsps/m68k/include/mcf5206/mcfuart.h | 109 + bsps/m68k/include/mcf5223x/mcf5223x.h | 3362 +++ bsps/m68k/include/mcf5225x/fec.h | 32 + bsps/m68k/include/mcf5225x/mcf5225x.h | 3552 +++ bsps/m68k/include/mcf5235/mcf5235.h | 2998 +++ bsps/m68k/include/mcf5272/mcf5272.h | 699 + bsps/m68k/include/mcf5282/mcf5282.h | 2407 ++ bsps/m68k/include/mcf532x/mcf532x.h | 4483 ++++ bsps/m68k/include/mcf548x/MCD_dma.h | 362 + bsps/m68k/include/mcf548x/MCD_progCheck.h | 5 + bsps/m68k/include/mcf548x/MCD_tasksInit.h | 44 + bsps/m68k/include/mcf548x/mcdma_glue.h | 106 + bsps/m68k/include/mcf548x/mcf548x.h | 4056 +++ bsps/m68k/include/mvme16x_hw.h | 274 + bsps/m68k/mcf5206elite/headers.am | 10 + bsps/m68k/mcf5206elite/include/bsp.h | 181 + bsps/m68k/mcf5206elite/include/ds1307.h | 41 + bsps/m68k/mcf5206elite/include/i2c.h | 243 + bsps/m68k/mcf5206elite/include/i2cdrv.h | 35 + bsps/m68k/mcf5206elite/include/nvram.h | 71 + bsps/m68k/mcf5206elite/include/tm27.h | 35 + bsps/m68k/mcf52235/headers.am | 6 + bsps/m68k/mcf52235/include/bsp.h | 87 + bsps/m68k/mcf52235/include/tm27.h | 35 + bsps/m68k/mcf5225x/headers.am | 6 + bsps/m68k/mcf5225x/include/bsp.h | 90 + bsps/m68k/mcf5225x/include/tm27.h | 35 + bsps/m68k/mcf5235/headers.am | 6 + bsps/m68k/mcf5235/include/bsp.h | 70 + bsps/m68k/mcf5235/include/tm27.h | 35 + bsps/m68k/mcf5329/headers.am | 6 + bsps/m68k/mcf5329/include/bsp.h | 70 + bsps/m68k/mcf5329/include/tm27.h | 35 + bsps/m68k/mrm332/headers.am | 7 + bsps/m68k/mrm332/include/bsp.h | 90 + bsps/m68k/mrm332/include/mrm332.h | 71 + bsps/m68k/mrm332/include/tm27.h | 1 + bsps/m68k/mvme147/headers.am | 6 + bsps/m68k/mvme147/include/bsp.h | 117 + bsps/m68k/mvme147/include/tm27.h | 38 + bsps/m68k/mvme147s/headers.am | 6 + bsps/m68k/mvme147s/include/bsp.h | 192 + bsps/m68k/mvme147s/include/tm27.h | 38 + bsps/m68k/mvme162/headers.am | 7 + bsps/m68k/mvme162/include/bsp.h | 204 + bsps/m68k/mvme162/include/page_table.h | 27 + bsps/m68k/mvme162/include/tm27.h | 39 + bsps/m68k/mvme167/headers.am | 7 + bsps/m68k/mvme167/include/bsp.h | 318 + bsps/m68k/mvme167/include/page_table.h | 43 + bsps/m68k/mvme167/include/tm27.h | 38 + bsps/m68k/uC5282/headers.am | 6 + bsps/m68k/uC5282/include/bsp.h | 175 + bsps/m68k/uC5282/include/tm27.h | 40 + bsps/mips/csb350/headers.am | 10 + bsps/mips/csb350/include/bsp.h | 47 + bsps/mips/csb350/include/bsp/irq.h | 123 + bsps/mips/csb350/include/tm27.h | 48 + bsps/mips/headers.am | 15 + bsps/mips/hurricane/headers.am | 11 + bsps/mips/hurricane/include/bsp.h | 79 + bsps/mips/hurricane/include/bsp/irq.h | 40 + bsps/mips/hurricane/include/tm27.h | 1 + bsps/mips/hurricane/include/usc.h | 32 + bsps/mips/include/bsp/i8259.h | 269 + bsps/mips/include/bsp/regs.h | 187 + bsps/mips/include/libcpu/au1x00.h | 445 + bsps/mips/include/libcpu/isr_entries.h | 39 + bsps/mips/include/libcpu/rm5231.h | 19 + bsps/mips/include/libcpu/tx3904.h | 45 + bsps/mips/include/libcpu/tx4925.h | 107 + bsps/mips/include/libcpu/tx4938.h | 191 + bsps/mips/jmr3904/headers.am | 10 + bsps/mips/jmr3904/include/bsp.h | 37 + bsps/mips/jmr3904/include/bsp/irq.h | 68 + bsps/mips/jmr3904/include/tm27.h | 52 + bsps/mips/malta/headers.am | 11 + bsps/mips/malta/include/bsp.h | 113 + bsps/mips/malta/include/bsp/irq.h | 131 + bsps/mips/malta/include/bsp/pci.h | 139 + bsps/mips/malta/include/tm27.h | 1 + bsps/mips/rbtx4925/headers.am | 10 + bsps/mips/rbtx4925/include/bsp.h | 46 + bsps/mips/rbtx4925/include/bsp/irq.h | 80 + bsps/mips/rbtx4925/include/tm27.h | 1 + bsps/mips/rbtx4938/headers.am | 10 + bsps/mips/rbtx4938/include/bsp.h | 46 + bsps/mips/rbtx4938/include/bsp/irq.h | 80 + bsps/mips/rbtx4938/include/tm27.h | 1 + bsps/moxie/moxiesim/headers.am | 6 + bsps/moxie/moxiesim/include/bsp.h | 35 + bsps/moxie/moxiesim/include/tm27.h | 1 + bsps/nios2/nios2_iss/headers.am | 6 + bsps/nios2/nios2_iss/include/bsp.h | 130 + bsps/nios2/nios2_iss/include/tm27.h | 1 + bsps/no_cpu/no_bsp/headers.am | 6 + bsps/no_cpu/no_bsp/include/bsp.h | 41 + bsps/no_cpu/no_bsp/include/tm27.h | 1 + bsps/or1k/generic_or1k/headers.am | 12 + bsps/or1k/generic_or1k/include/bsp.h | 45 + bsps/or1k/generic_or1k/include/bsp/generic_or1k.h | 118 + bsps/or1k/generic_or1k/include/bsp/irq.h | 45 + bsps/or1k/generic_or1k/include/bsp/uart.h | 42 + bsps/or1k/generic_or1k/include/tm27.h | 1 + bsps/or1k/headers.am | 6 + bsps/or1k/include/bsp/cache_.h | 43 + bsps/or1k/include/bsp/linker-symbols.h | 79 + bsps/powerpc/beatnik/headers.am | 22 + bsps/powerpc/beatnik/include/bsp.h | 297 + bsps/powerpc/beatnik/include/bsp/VMEConfig.h | 114 + .../beatnik/include/bsp/bsp_bsdnet_attach.h | 79 + .../beatnik/include/bsp/early_enet_link_status.h | 30 + bsps/powerpc/beatnik/include/bsp/gt_timer.h | 133 + bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h | 62 + bsps/powerpc/beatnik/include/bsp/gti2creg.h | 83 + bsps/powerpc/beatnik/include/bsp/gtintrreg.h | 257 + bsps/powerpc/beatnik/include/bsp/gtpcireg.h | 964 + bsps/powerpc/beatnik/include/bsp/gtreg.h | 854 + bsps/powerpc/beatnik/include/bsp/if_em_pub.h | 22 + bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h | 30 + bsps/powerpc/beatnik/include/bsp/if_mve_pub.h | 422 + bsps/powerpc/beatnik/include/bsp/irq.h | 133 + bsps/powerpc/beatnik/include/tm27.h | 1 + bsps/powerpc/gen5200/headers.am | 45 + bsps/powerpc/gen5200/include/bsp.h | 266 + bsps/powerpc/gen5200/include/bsp/ata.h | 338 + bsps/powerpc/gen5200/include/bsp/bestcomm.h | 370 + .../gen5200/include/bsp/bestcomm/bestcomm_api.h | 460 + .../gen5200/include/bsp/bestcomm/bestcomm_glue.h | 114 + .../gen5200/include/bsp/bestcomm/bestcomm_priv.h | 38 + .../gen5200/include/bsp/bestcomm/dma_image.capi.h | 84 + .../gen5200/include/bsp/bestcomm/dma_image.h | 472 + .../include/bsp/bestcomm/include/mgt5200/mgt5200.h | 61 + .../include/bsp/bestcomm/include/mgt5200/sdma.h | 153 + .../include/bsp/bestcomm/include/ppctypes.h | 43 + .../bsp/bestcomm/task_api/bestcomm_api_mem.h | 67 + .../include/bsp/bestcomm/task_api/bestcomm_cntrl.h | 282 + .../bsp/bestcomm/task_api/tasksetup_bdtable.h | 86 + .../bsp/bestcomm/task_api/tasksetup_general.h | 624 + bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h | 224 + bsps/powerpc/gen5200/include/bsp/i2c.h | 243 + bsps/powerpc/gen5200/include/bsp/i2cdrv.h | 35 + bsps/powerpc/gen5200/include/bsp/irq.h | 212 + bsps/powerpc/gen5200/include/bsp/mpc5200.h | 1369 + bsps/powerpc/gen5200/include/bsp/mscan-base.h | 284 + bsps/powerpc/gen5200/include/bsp/mscan.h | 127 + bsps/powerpc/gen5200/include/bsp/nvram.h | 141 + bsps/powerpc/gen5200/include/bsp/slicetimer.h | 69 + bsps/powerpc/gen5200/include/bsp/u-boot-config.h | 20 + bsps/powerpc/gen5200/include/tm27.h | 66 + bsps/powerpc/gen83xx/headers.am | 13 + bsps/powerpc/gen83xx/include/bsp.h | 163 + bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h | 381 + bsps/powerpc/gen83xx/include/bsp/irq.h | 184 + bsps/powerpc/gen83xx/include/bsp/tsec-config.h | 28 + bsps/powerpc/gen83xx/include/bsp/u-boot-config.h | 21 + bsps/powerpc/gen83xx/include/tm27.h | 62 + bsps/powerpc/haleakala/headers.am | 11 + bsps/powerpc/haleakala/include/bsp.h | 87 + bsps/powerpc/haleakala/include/bsp/irq.h | 166 + bsps/powerpc/haleakala/include/mmu_405.h | 77 + bsps/powerpc/haleakala/include/tm27.h | 1 + bsps/powerpc/headers.am | 101 + bsps/powerpc/include/bsp/consoleIo.h | 38 + bsps/powerpc/include/bsp/flashPgm.h | 209 + bsps/powerpc/include/bsp/flashPgmPvt.h | 274 + bsps/powerpc/include/bsp/irq_supp.h | 124 + bsps/powerpc/include/bsp/linker-symbols.h | 139 + bsps/powerpc/include/bsp/motorola.h | 69 + bsps/powerpc/include/bsp/openpic.h | 378 + bsps/powerpc/include/bsp/pci.h | 84 + bsps/powerpc/include/bsp/pnp.h | 644 + bsps/powerpc/include/bsp/residual.h | 356 + bsps/powerpc/include/bsp/start.h | 84 + bsps/powerpc/include/bsp/tictac.h | 78 + bsps/powerpc/include/bsp/tsec.h | 380 + bsps/powerpc/include/bsp/u-boot-board-info.h | 146 + bsps/powerpc/include/bsp/uart.h | 190 + bsps/powerpc/include/bsp/vectors.h | 493 + bsps/powerpc/include/bsp/vpd.h | 143 + bsps/powerpc/include/ictrl.h | 75 + bsps/powerpc/include/libcpu/bat.h | 85 + bsps/powerpc/include/libcpu/byteorder.h | 54 + bsps/powerpc/include/libcpu/c_clock.h | 56 + bsps/powerpc/include/libcpu/cpuIdent.h | 158 + bsps/powerpc/include/libcpu/e500_mmu.h | 230 + bsps/powerpc/include/libcpu/io.h | 139 + bsps/powerpc/include/libcpu/irq.h | 199 + bsps/powerpc/include/libcpu/mmu.h | 304 + bsps/powerpc/include/libcpu/page.h | 66 + bsps/powerpc/include/libcpu/pgtable.h | 144 + bsps/powerpc/include/libcpu/powerpc-utility.h | 985 + bsps/powerpc/include/libcpu/pte121.h | 265 + bsps/powerpc/include/libcpu/raw_exception.h | 161 + bsps/powerpc/include/libcpu/spr.h | 78 + bsps/powerpc/include/libcpu/stackTrace.h | 8 + bsps/powerpc/include/libcpu/vectors.h | 115 + bsps/powerpc/include/mpc55xx/dspi.h | 128 + bsps/powerpc/include/mpc55xx/edma.h | 329 + bsps/powerpc/include/mpc55xx/emios.h | 197 + bsps/powerpc/include/mpc55xx/fsl-mpc551x.h | 4005 +++ bsps/powerpc/include/mpc55xx/fsl-mpc555x.h | 3383 +++ bsps/powerpc/include/mpc55xx/fsl-mpc556x.h | 4563 ++++ bsps/powerpc/include/mpc55xx/fsl-mpc564xL.h | 20666 +++++++++++++++ bsps/powerpc/include/mpc55xx/fsl-mpc5668.h | 6721 +++++ bsps/powerpc/include/mpc55xx/fsl-mpc567x.h | 6630 +++++ bsps/powerpc/include/mpc55xx/mpc55xx.h | 155 + bsps/powerpc/include/mpc55xx/reg-defs.h | 100 + bsps/powerpc/include/mpc55xx/regs-edma.h | 710 + bsps/powerpc/include/mpc55xx/regs-mmu.h | 200 + bsps/powerpc/include/mpc55xx/regs.h | 88 + bsps/powerpc/include/mpc55xx/siu.h | 313 + bsps/powerpc/include/mpc55xx/watchdog.h | 68 + bsps/powerpc/include/mpc5xx.h | 626 + bsps/powerpc/include/mpc5xx/console.h | 34 + bsps/powerpc/include/mpc8260.h | 1510 ++ bsps/powerpc/include/mpc8260/console.h | 60 + bsps/powerpc/include/mpc8260/cpm.h | 123 + bsps/powerpc/include/mpc8260/mmu.h | 47 + bsps/powerpc/include/mpc83xx/gtm.h | 67 + bsps/powerpc/include/mpc83xx/mpc83xx.h | 1014 + bsps/powerpc/include/mpc83xx/mpc83xx_i2cdrv.h | 68 + bsps/powerpc/include/mpc83xx/mpc83xx_spidrv.h | 172 + bsps/powerpc/include/mpc8xx.h | 1499 ++ bsps/powerpc/include/mpc8xx/console.h | 32 + bsps/powerpc/include/mpc8xx/cpm.h | 36 + bsps/powerpc/include/mpc8xx/mmu.h | 47 + bsps/powerpc/include/nvram.h | 167 + bsps/powerpc/include/ppc4xx/ppc405ex.h | 191 + bsps/powerpc/include/ppc4xx/ppc405gp.h | 214 + bsps/powerpc/include/rtems/powerpc/cache.h | 38 + bsps/powerpc/include/rtems/powerpc/debugmod.h | 124 + bsps/powerpc/include/rtems/powerpc/powerpc.h | 644 + bsps/powerpc/include/tty_drv.h | 63 + bsps/powerpc/motorola_powerpc/headers.am | 11 + bsps/powerpc/motorola_powerpc/include/bsp.h | 248 + .../motorola_powerpc/include/bsp/VMEConfig.h | 233 + bsps/powerpc/motorola_powerpc/include/bsp/irq.h | 204 + bsps/powerpc/motorola_powerpc/include/tm27.h | 64 + bsps/powerpc/mpc55xxevb/headers.am | 15 + bsps/powerpc/mpc55xxevb/include/bsp.h | 104 + bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h | 57 + .../mpc55xxevb/include/bsp/console-generic.h | 81 + .../mpc55xxevb/include/bsp/console-linflex.h | 64 + bsps/powerpc/mpc55xxevb/include/bsp/irq.h | 499 + .../mpc55xxevb/include/bsp/mpc55xx-config.h | 170 + bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h | 704 + bsps/powerpc/mpc55xxevb/include/tm27.h | 1 + bsps/powerpc/mpc8260ads/headers.am | 10 + bsps/powerpc/mpc8260ads/include/bsp.h | 86 + bsps/powerpc/mpc8260ads/include/bsp/irq.h | 193 + bsps/powerpc/mpc8260ads/include/tm27.h | 46 + bsps/powerpc/mvme3100/headers.am | 13 + bsps/powerpc/mvme3100/include/bsp.h | 343 + bsps/powerpc/mvme3100/include/bsp/VMEConfig.h | 132 + bsps/powerpc/mvme3100/include/bsp/if_tsec_pub.h | 475 + bsps/powerpc/mvme3100/include/bsp/irq.h | 137 + .../mvme3100/include/bsp/mpc8540_i2c_busdrv.h | 72 + bsps/powerpc/mvme3100/include/tm27.h | 1 + bsps/powerpc/mvme5500/headers.am | 21 + bsps/powerpc/mvme5500/include/bsp.h | 206 + bsps/powerpc/mvme5500/include/bsp/GT64260TWSI.h | 20 + bsps/powerpc/mvme5500/include/bsp/GT64260eth.h | 140 + bsps/powerpc/mvme5500/include/bsp/GT64260ethreg.h | 879 + bsps/powerpc/mvme5500/include/bsp/VMEConfig.h | 67 + bsps/powerpc/mvme5500/include/bsp/VPD.h | 9 + bsps/powerpc/mvme5500/include/bsp/bspException.h | 99 + bsps/powerpc/mvme5500/include/bsp/bspMvme5500.h | 15 + bsps/powerpc/mvme5500/include/bsp/gtpcireg.h | 99 + bsps/powerpc/mvme5500/include/bsp/gtreg.h | 810 + bsps/powerpc/mvme5500/include/bsp/if_wmreg.h | 740 + bsps/powerpc/mvme5500/include/bsp/irq.h | 137 + bsps/powerpc/mvme5500/include/bsp/pcireg.h | 386 + bsps/powerpc/mvme5500/include/tm27.h | 66 + bsps/powerpc/psim/headers.am | 11 + bsps/powerpc/psim/include/bsp.h | 90 + bsps/powerpc/psim/include/bsp/irq.h | 74 + bsps/powerpc/psim/include/psim.h | 90 + bsps/powerpc/psim/include/tm27.h | 66 + bsps/powerpc/qemuppc/headers.am | 10 + bsps/powerpc/qemuppc/include/bsp.h | 47 + bsps/powerpc/qemuppc/include/bsp/irq.h | 76 + bsps/powerpc/qemuppc/include/tm27.h | 1 + bsps/powerpc/qoriq/headers.am | 24 + bsps/powerpc/qoriq/include/asm/epapr_hcalls.h | 573 + bsps/powerpc/qoriq/include/asm/fsl_hcalls.h | 653 + bsps/powerpc/qoriq/include/bsp.h | 128 + bsps/powerpc/qoriq/include/bsp/intercom.h | 125 + bsps/powerpc/qoriq/include/bsp/irq.h | 401 + bsps/powerpc/qoriq/include/bsp/mmu.h | 101 + bsps/powerpc/qoriq/include/bsp/qoriq.h | 559 + bsps/powerpc/qoriq/include/bsp/tsec-config.h | 36 + bsps/powerpc/qoriq/include/bsp/uart-bridge.h | 72 + bsps/powerpc/qoriq/include/tm27.h | 96 + bsps/powerpc/qoriq/include/uapi/asm/epapr_hcalls.h | 98 + bsps/powerpc/ss555/headers.am | 10 + bsps/powerpc/ss555/include/bsp.h | 91 + bsps/powerpc/ss555/include/bsp/irq.h | 66 + bsps/powerpc/ss555/include/tm27.h | 56 + bsps/powerpc/t32mppc/headers.am | 10 + bsps/powerpc/t32mppc/include/bsp.h | 42 + bsps/powerpc/t32mppc/include/bsp/irq.h | 52 + bsps/powerpc/t32mppc/include/tm27.h | 1 + bsps/powerpc/tqm8xx/headers.am | 13 + bsps/powerpc/tqm8xx/include/bsp.h | 169 + bsps/powerpc/tqm8xx/include/bsp/8xx_immap.h | 477 + bsps/powerpc/tqm8xx/include/bsp/irq.h | 160 + bsps/powerpc/tqm8xx/include/bsp/spi.h | 146 + bsps/powerpc/tqm8xx/include/bsp/tqm.h | 51 + bsps/powerpc/tqm8xx/include/tm27.h | 1 + bsps/powerpc/virtex/headers.am | 13 + bsps/powerpc/virtex/include/bsp.h | 84 + bsps/powerpc/virtex/include/bsp/irq.h | 94 + bsps/powerpc/virtex/include/bsp/opbintctrl.h | 75 + bsps/powerpc/virtex/include/tm27.h | 1 + bsps/powerpc/virtex/include/xiltemac.h | 375 + bsps/powerpc/virtex/include/xparameters_dflt.h | 192 + bsps/powerpc/virtex4/headers.am | 11 + bsps/powerpc/virtex4/include/bsp.h | 83 + bsps/powerpc/virtex4/include/bsp/irq.h | 79 + bsps/powerpc/virtex4/include/bsp/mmu.h | 269 + bsps/powerpc/virtex4/include/tm27.h | 1 + bsps/powerpc/virtex5/headers.am | 11 + bsps/powerpc/virtex5/include/bsp.h | 107 + bsps/powerpc/virtex5/include/bsp/irq.h | 82 + bsps/powerpc/virtex5/include/bsp/mmu.h | 287 + bsps/powerpc/virtex5/include/tm27.h | 1 + bsps/riscv/headers.am | 5 + bsps/riscv/include/bsp/linker-symbols.h | 81 + bsps/riscv/riscv_generic/headers.am | 10 + bsps/riscv/riscv_generic/include/bsp.h | 73 + bsps/riscv/riscv_generic/include/bsp/irq.h | 49 + bsps/riscv/riscv_generic/include/tm27.h | 1 + bsps/sh/gensh1/headers.am | 17 + bsps/sh/gensh1/include/bsp.h | 86 + bsps/sh/gensh1/include/rtems/score/iosh7032.h | 220 + bsps/sh/gensh1/include/rtems/score/ispsh7032.h | 162 + bsps/sh/gensh1/include/sh/sci.h | 82 + bsps/sh/gensh1/include/sh/sh7_pfc.h | 115 + bsps/sh/gensh1/include/sh/sh7_sci.h | 79 + bsps/sh/gensh1/include/tm27.h | 1 + bsps/sh/gensh2/headers.am | 19 + bsps/sh/gensh2/include/bsp.h | 85 + bsps/sh/gensh2/include/rtems/score/iosh7045.h | 322 + bsps/sh/gensh2/include/rtems/score/ispsh7045.h | 208 + bsps/sh/gensh2/include/sh/io_types.h | 84 + bsps/sh/gensh2/include/sh/sci.h | 89 + bsps/sh/gensh2/include/sh/sci_termios.h | 65 + bsps/sh/gensh2/include/sh/sh7_pfc.h | 202 + bsps/sh/gensh2/include/sh/sh7_sci.h | 88 + bsps/sh/gensh2/include/tm27.h | 1 + bsps/sh/gensh4/headers.am | 19 + bsps/sh/gensh4/include/bsp.h | 92 + bsps/sh/gensh4/include/rtems/score/iosh7750.h | 47 + bsps/sh/gensh4/include/rtems/score/ipl.h | 73 + bsps/sh/gensh4/include/rtems/score/ispsh7750.h | 62 + bsps/sh/gensh4/include/rtems/score/sh4_regs.h | 51 + bsps/sh/gensh4/include/rtems/score/sh7750_regs.h | 1613 ++ bsps/sh/gensh4/include/sdram.h | 40 + bsps/sh/gensh4/include/sh/sh4uart.h | 174 + bsps/sh/gensh4/include/tm27.h | 59 + bsps/sh/shsim/headers.am | 10 + bsps/sh/shsim/include/bsp.h | 65 + bsps/sh/shsim/include/bsp/syscall.h | 32 + bsps/sh/shsim/include/tm27.h | 1 + bsps/sparc/erc32/headers.am | 11 + bsps/sparc/erc32/include/bsp.h | 184 + bsps/sparc/erc32/include/bsp/irq.h | 48 + bsps/sparc/erc32/include/erc32.h | 549 + bsps/sparc/erc32/include/tm27.h | 85 + bsps/sparc/headers.am | 75 + bsps/sparc/include/ambapp.h | 376 + bsps/sparc/include/ambapp_ids.h | 317 + bsps/sparc/include/bsp/ahbstat.h | 76 + bsps/sparc/include/bsp/apbuart.h | 60 + bsps/sparc/include/bsp/apbuart_cons.h | 16 + bsps/sparc/include/bsp/apbuart_termios.h | 60 + bsps/sparc/include/bsp/b1553brm.h | 178 + bsps/sparc/include/bsp/b1553rt.h | 79 + bsps/sparc/include/bsp/canmux.h | 32 + bsps/sparc/include/bsp/cons.h | 42 + bsps/sparc/include/bsp/debug_defs.h | 45 + bsps/sparc/include/bsp/genirq.h | 132 + bsps/sparc/include/bsp/gnatcommon.h | 19 + bsps/sparc/include/bsp/gpiolib.h | 94 + bsps/sparc/include/bsp/gptimer.h | 30 + bsps/sparc/include/bsp/gr1553b.h | 369 + bsps/sparc/include/bsp/gr1553bc.h | 250 + bsps/sparc/include/bsp/gr1553bc_list.h | 707 + bsps/sparc/include/bsp/gr1553bm.h | 204 + bsps/sparc/include/bsp/gr1553rt.h | 434 + bsps/sparc/include/bsp/gr_701.h | 51 + bsps/sparc/include/bsp/gr_cpci_gr740.h | 61 + bsps/sparc/include/bsp/gr_leon4_n2x.h | 61 + bsps/sparc/include/bsp/gr_rasta_adcdac.h | 52 + bsps/sparc/include/bsp/gr_rasta_io.h | 52 + bsps/sparc/include/bsp/gr_rasta_spw_router.h | 48 + bsps/sparc/include/bsp/gr_rasta_tmtc.h | 103 + bsps/sparc/include/bsp/gr_tmtc_1553.h | 55 + bsps/sparc/include/bsp/gradcdac.h | 227 + bsps/sparc/include/bsp/grascs.h | 92 + bsps/sparc/include/bsp/grcan.h | 342 + bsps/sparc/include/bsp/grctm.h | 171 + bsps/sparc/include/bsp/greth.h | 157 + bsps/sparc/include/bsp/grgpio.h | 25 + bsps/sparc/include/bsp/griommu.h | 187 + bsps/sparc/include/bsp/grpci.h | 31 + bsps/sparc/include/bsp/grpci2.h | 65 + bsps/sparc/include/bsp/grpci2dma.h | 263 + bsps/sparc/include/bsp/grpwm.h | 127 + bsps/sparc/include/bsp/grslink.h | 148 + bsps/sparc/include/bsp/grspw.h | 168 + bsps/sparc/include/bsp/grspw_pkt.h | 845 + bsps/sparc/include/bsp/grspw_router.h | 505 + bsps/sparc/include/bsp/grtc.h | 155 + bsps/sparc/include/bsp/grtm.h | 245 + bsps/sparc/include/bsp/i2cmst.h | 65 + bsps/sparc/include/bsp/l2c.h | 201 + bsps/sparc/include/bsp/l4stat.h | 91 + bsps/sparc/include/bsp/mctrl.h | 26 + bsps/sparc/include/bsp/memscrub.h | 172 + bsps/sparc/include/bsp/network_interface_add.h | 47 + bsps/sparc/include/bsp/occan.h | 165 + bsps/sparc/include/bsp/pcif.h | 15 + bsps/sparc/include/bsp/satcan.h | 142 + bsps/sparc/include/bsp/spictrl.h | 126 + bsps/sparc/include/bsp/spwcuc.h | 188 + bsps/sparc/include/bsp/tlib.h | 202 + bsps/sparc/include/drvmgr/ambapp_bus.h | 142 + bsps/sparc/include/drvmgr/ambapp_bus_grlib.h | 36 + bsps/sparc/include/drvmgr/bspcommon.h | 28 + bsps/sparc/include/drvmgr/leon2_amba_bus.h | 95 + bsps/sparc/include/grlib.h | 164 + bsps/sparc/include/libcpu/access.h | 50 + bsps/sparc/leon2/headers.am | 12 + bsps/sparc/leon2/include/bsp.h | 220 + bsps/sparc/leon2/include/bsp/at697_pci.h | 26 + bsps/sparc/leon2/include/bsp/irq.h | 28 + bsps/sparc/leon2/include/leon.h | 423 + bsps/sparc/leon2/include/tm27.h | 84 + bsps/sparc/leon3/headers.am | 13 + bsps/sparc/leon3/include/amba.h | 48 + bsps/sparc/leon3/include/bsp.h | 250 + bsps/sparc/leon3/include/bsp/irq.h | 55 + bsps/sparc/leon3/include/bsp/watchdog.h | 49 + bsps/sparc/leon3/include/leon.h | 511 + bsps/sparc/leon3/include/tm27.h | 84 + bsps/sparc64/headers.am | 54 + bsps/sparc64/include/arch/arch.h | 61 + bsps/sparc64/include/arch/boot.h | 98 + bsps/sparc64/include/arch/mm/cache_spec.h | 58 + bsps/sparc64/include/arch/mm/frame.h | 47 + bsps/sparc64/include/arch/mm/mmu.h | 48 + bsps/sparc64/include/arch/mm/page.h | 84 + bsps/sparc64/include/arch/mm/sun4u/frame.h | 87 + bsps/sparc64/include/arch/mm/sun4u/mmu.h | 123 + bsps/sparc64/include/arch/mm/sun4u/page.h | 84 + bsps/sparc64/include/arch/mm/sun4u/tlb.h | 693 + bsps/sparc64/include/arch/mm/sun4u/tte.h | 104 + bsps/sparc64/include/arch/mm/tlb.h | 48 + bsps/sparc64/include/arch/mm/tte.h | 47 + bsps/sparc64/include/arch/regdef.h | 67 + bsps/sparc64/include/arch/stack.h | 72 + bsps/sparc64/include/arch/sun4u/arch.h | 47 + bsps/sparc64/include/asm.h | 13 + bsps/sparc64/include/boot/align.h | 48 + bsps/sparc64/include/boot/balloc.h | 52 + bsps/sparc64/include/boot/gentypes.h | 47 + bsps/sparc64/include/boot/main.h | 75 + bsps/sparc64/include/boot/ofw.h | 117 + bsps/sparc64/include/boot/ofw_tree.h | 61 + bsps/sparc64/include/boot/ofwarch.h | 41 + bsps/sparc64/include/boot/register.h | 39 + bsps/sparc64/include/boot/stack.h | 36 + bsps/sparc64/include/boot/types.h | 44 + bsps/sparc64/include/genarch/ofw/ofw_tree.h | 88 + bsps/sparc64/include/kernel/align.h | 59 + bsps/sparc64/include/traptable.h | 21 + bsps/sparc64/niagara/headers.am | 6 + bsps/sparc64/niagara/include/bsp.h | 41 + bsps/sparc64/niagara/include/tm27.h | 1 + bsps/sparc64/usiii/headers.am | 6 + bsps/sparc64/usiii/include/bsp.h | 42 + bsps/sparc64/usiii/include/tm27.h | 1 + bsps/v850/gdbv850sim/headers.am | 10 + bsps/v850/gdbv850sim/include/bsp.h | 35 + bsps/v850/gdbv850sim/include/bsp/syscall.h | 47 + bsps/v850/gdbv850sim/include/tm27.h | 1 + 1217 files changed, 381032 insertions(+) create mode 100644 bsps/arm/altera-cyclone-v/headers.am create mode 100644 bsps/arm/altera-cyclone-v/include/bsp.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/hwlib.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/irq.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h create mode 100644 bsps/arm/altera-cyclone-v/include/tm27.h create mode 100644 bsps/arm/atsam/headers.am create mode 100644 bsps/arm/atsam/include/bsp.h create mode 100644 bsps/arm/atsam/include/bsp/atsam-clock-config.h create mode 100644 bsps/arm/atsam/include/bsp/atsam-i2c.h create mode 100644 bsps/arm/atsam/include/bsp/atsam-spi.h create mode 100644 bsps/arm/atsam/include/bsp/i2c.h create mode 100644 bsps/arm/atsam/include/bsp/irq.h create mode 100644 bsps/arm/atsam/include/bsp/pin-config.h create mode 100644 bsps/arm/atsam/include/bsp/power.h create mode 100644 bsps/arm/atsam/include/bsp/sc16is752.h create mode 100644 bsps/arm/atsam/include/bsp/spi.h create mode 100644 bsps/arm/atsam/include/libchip/chip.h create mode 100644 bsps/arm/atsam/include/libchip/compiler.h create mode 100644 bsps/arm/atsam/include/libchip/include/acc.h create mode 100644 bsps/arm/atsam/include/libchip/include/adc.h create mode 100644 bsps/arm/atsam/include/libchip/include/aes.h create mode 100644 bsps/arm/atsam/include/libchip/include/afe_dma.h create mode 100644 bsps/arm/atsam/include/libchip/include/afec.h create mode 100644 bsps/arm/atsam/include/libchip/include/chip.h create mode 100644 bsps/arm/atsam/include/libchip/include/dac_dma.h create mode 100644 bsps/arm/atsam/include/libchip/include/efc.h create mode 100644 bsps/arm/atsam/include/libchip/include/exceptions.h create mode 100644 bsps/arm/atsam/include/libchip/include/flashd.h create mode 100644 bsps/arm/atsam/include/libchip/include/gmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/gmacd.h create mode 100644 bsps/arm/atsam/include/libchip/include/hsmci.h create mode 100644 bsps/arm/atsam/include/libchip/include/icm.h create mode 100644 bsps/arm/atsam/include/libchip/include/isi.h create mode 100644 bsps/arm/atsam/include/libchip/include/iso7816_4.h create mode 100644 bsps/arm/atsam/include/libchip/include/mcan.h create mode 100644 bsps/arm/atsam/include/libchip/include/mcid.h create mode 100644 bsps/arm/atsam/include/libchip/include/mediaLB.h create mode 100644 bsps/arm/atsam/include/libchip/include/mpu.h create mode 100644 bsps/arm/atsam/include/libchip/include/pio.h create mode 100644 bsps/arm/atsam/include/libchip/include/pio_capture.h create mode 100644 bsps/arm/atsam/include/libchip/include/pio_it.h create mode 100644 bsps/arm/atsam/include/libchip/include/pmc.h create mode 100644 bsps/arm/atsam/include/libchip/include/pwmc.h create mode 100644 bsps/arm/atsam/include/libchip/include/qspi.h create mode 100644 bsps/arm/atsam/include/libchip/include/qspi_dma.h create mode 100644 bsps/arm/atsam/include/libchip/include/rstc.h create mode 100644 bsps/arm/atsam/include/libchip/include/rtc.h create mode 100644 bsps/arm/atsam/include/libchip/include/rtt.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_acc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_aes.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_afec.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_chipid.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_dacc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_efc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_gmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_gpbr.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_hsmci.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_icm.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_isi.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_matrix.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_mcan.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_pwm.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_qspi.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_rstc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_rswdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_rtc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_rtt.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_sdramc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_smc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_spi.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_ssc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_supc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_tc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_trng.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_twihs.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_uart.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_usart.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_usbhs.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_utmi.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_wdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_xdmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j19.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j20.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j21.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n19.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n20.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n21.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q19.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q20.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q21.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70j19.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70j20.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70j21.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70n19.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70n20.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70n21.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70q19.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70q20.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70q21.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/system_same70.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_acc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_aes.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_afec.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_chipid.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_dacc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_efc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_gpbr.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_hsmci.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_icm.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_isi.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_pio.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_pmc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_pwm.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_rstc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_rswdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_rtc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_rtt.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_sdramc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_smc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_spi.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_ssc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_supc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_tc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_trng.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_twihs.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_uart.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_usart.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_usbhs.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_utmi.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_wdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_xdmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j19.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j20.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j21.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n19.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n20.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n21.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q19.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q20.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q21.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70j19.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70j20.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70j21.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70n19.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70n20.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70n21.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70q19.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70q20.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70q21.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/system_sams70.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_acc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_aes.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_afec.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_chipid.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_dacc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_efc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_gmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_gpbr.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_hsmci.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_icm.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_isi.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_matrix.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_mlb.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_pio.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_pmc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_pwm.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_qspi.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_rstc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_rswdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_rtc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_rtt.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_sdramc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_smc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_spi.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_ssc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_supc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_tc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_trng.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_twihs.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_uart.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_usart.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_usbhs.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_utmi.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_wdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_xdmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j19.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j20.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j21.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n19.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n20.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n21.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q19.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q20.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q21.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71j19.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71j20.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71j21.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71n19.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71n20.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71n21.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71q19.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71q20.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71q21.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/system_samv71.h create mode 100644 bsps/arm/atsam/include/libchip/include/sdramc.h create mode 100644 bsps/arm/atsam/include/libchip/include/smc.h create mode 100644 bsps/arm/atsam/include/libchip/include/spi.h create mode 100644 bsps/arm/atsam/include/libchip/include/spi_dma.h create mode 100644 bsps/arm/atsam/include/libchip/include/ssc.h create mode 100644 bsps/arm/atsam/include/libchip/include/supc.h create mode 100644 bsps/arm/atsam/include/libchip/include/tc.h create mode 100644 bsps/arm/atsam/include/libchip/include/timetick.h create mode 100644 bsps/arm/atsam/include/libchip/include/trace.h create mode 100644 bsps/arm/atsam/include/libchip/include/trng.h create mode 100644 bsps/arm/atsam/include/libchip/include/twi.h create mode 100644 bsps/arm/atsam/include/libchip/include/twid.h create mode 100644 bsps/arm/atsam/include/libchip/include/uart.h create mode 100644 bsps/arm/atsam/include/libchip/include/uart_dma.h create mode 100644 bsps/arm/atsam/include/libchip/include/usart.h create mode 100644 bsps/arm/atsam/include/libchip/include/usart_dma.h create mode 100644 bsps/arm/atsam/include/libchip/include/usbhs.h create mode 100644 bsps/arm/atsam/include/libchip/include/video.h create mode 100644 bsps/arm/atsam/include/libchip/include/wdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/xdma_hardware_interface.h create mode 100644 bsps/arm/atsam/include/libchip/include/xdmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/xdmad.h create mode 100644 bsps/arm/atsam/include/tm27.h create mode 100644 bsps/arm/beagle/headers.am create mode 100644 bsps/arm/beagle/include/bsp.h create mode 100644 bsps/arm/beagle/include/bsp/bbb-gpio.h create mode 100644 bsps/arm/beagle/include/bsp/bbb-pwm.h create mode 100644 bsps/arm/beagle/include/bsp/beagleboneblack.h create mode 100644 bsps/arm/beagle/include/bsp/i2c.h create mode 100644 bsps/arm/beagle/include/bsp/irq.h create mode 100644 bsps/arm/beagle/include/tm27.h create mode 100644 bsps/arm/csb336/headers.am create mode 100644 bsps/arm/csb336/include/bsp.h create mode 100644 bsps/arm/csb336/include/bsp/irq.h create mode 100644 bsps/arm/csb336/include/mc9328mxl.h create mode 100644 bsps/arm/csb336/include/tm27.h create mode 100644 bsps/arm/csb337/headers.am create mode 100644 bsps/arm/csb337/include/at91rm9200.h create mode 100644 bsps/arm/csb337/include/at91rm9200_dbgu.h create mode 100644 bsps/arm/csb337/include/at91rm9200_emac.h create mode 100644 bsps/arm/csb337/include/at91rm9200_gpio.h create mode 100644 bsps/arm/csb337/include/at91rm9200_mem.h create mode 100644 bsps/arm/csb337/include/at91rm9200_pmc.h create mode 100644 bsps/arm/csb337/include/at91rm9200_usart.h create mode 100644 bsps/arm/csb337/include/bits.h create mode 100644 bsps/arm/csb337/include/bsp.h create mode 100644 bsps/arm/csb337/include/bsp/irq.h create mode 100644 bsps/arm/csb337/include/font8x16.h create mode 100644 bsps/arm/csb337/include/sed1356.h create mode 100644 bsps/arm/csb337/include/sed1356_16bit.h create mode 100644 bsps/arm/csb337/include/tm27.h create mode 100644 bsps/arm/edb7312/headers.am create mode 100644 bsps/arm/edb7312/include/bsp.h create mode 100644 bsps/arm/edb7312/include/bsp/irq.h create mode 100644 bsps/arm/edb7312/include/ep7312.h create mode 100644 bsps/arm/edb7312/include/tm27.h create mode 100644 bsps/arm/gdbarmsim/headers.am create mode 100644 bsps/arm/gdbarmsim/include/bsp.h create mode 100644 bsps/arm/gdbarmsim/include/bsp/irq.h create mode 100644 bsps/arm/gdbarmsim/include/bsp/swi.h create mode 100644 bsps/arm/gdbarmsim/include/tm27.h create mode 100644 bsps/arm/gumstix/headers.am create mode 100644 bsps/arm/gumstix/include/bsp.h create mode 100644 bsps/arm/gumstix/include/bsp/irq.h create mode 100644 bsps/arm/gumstix/include/ffuart.h create mode 100644 bsps/arm/gumstix/include/pxa255.h create mode 100644 bsps/arm/gumstix/include/tm27.h create mode 100644 bsps/arm/headers.am create mode 100644 bsps/arm/imx/headers.am create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h create mode 100644 bsps/arm/imx/include/bsp.h create mode 100644 bsps/arm/imx/include/bsp/irq.h create mode 100644 bsps/arm/imx/include/tm27.h create mode 100644 bsps/arm/include/bsp/arm-a8core-start.h create mode 100644 bsps/arm/include/bsp/arm-a9mpcore-clock.h create mode 100644 bsps/arm/include/bsp/arm-a9mpcore-irq.h create mode 100644 bsps/arm/include/bsp/arm-a9mpcore-regs.h create mode 100644 bsps/arm/include/bsp/arm-a9mpcore-start.h create mode 100644 bsps/arm/include/bsp/arm-cp15-start.h create mode 100644 bsps/arm/include/bsp/arm-errata.h create mode 100644 bsps/arm/include/bsp/arm-gic-irq.h create mode 100644 bsps/arm/include/bsp/arm-gic-regs.h create mode 100644 bsps/arm/include/bsp/arm-gic-tm27.h create mode 100644 bsps/arm/include/bsp/arm-gic.h create mode 100644 bsps/arm/include/bsp/arm-pl011-regs.h create mode 100644 bsps/arm/include/bsp/arm-pl011.h create mode 100644 bsps/arm/include/bsp/arm-pl050-regs.h create mode 100644 bsps/arm/include/bsp/arm-pl050.h create mode 100644 bsps/arm/include/bsp/arm-pl111-fb.h create mode 100644 bsps/arm/include/bsp/arm-pl111-regs.h create mode 100644 bsps/arm/include/bsp/arm-release-id.h create mode 100644 bsps/arm/include/bsp/armv7m-irq.h create mode 100644 bsps/arm/include/bsp/linker-symbols.h create mode 100644 bsps/arm/include/bsp/lpc-dma.h create mode 100644 bsps/arm/include/bsp/lpc-emc.h create mode 100644 bsps/arm/include/bsp/lpc-i2s.h create mode 100644 bsps/arm/include/bsp/lpc-lcd.h create mode 100644 bsps/arm/include/bsp/lpc-timer.h create mode 100644 bsps/arm/include/bsp/start.h create mode 100644 bsps/arm/include/cmsis_gcc.h create mode 100644 bsps/arm/include/core_cm7.h create mode 100644 bsps/arm/include/core_cmFunc.h create mode 100644 bsps/arm/include/core_cmInstr.h create mode 100644 bsps/arm/include/core_cmSimd.h create mode 100644 bsps/arm/include/libcpu/am335x.h create mode 100644 bsps/arm/include/libcpu/mmu.h create mode 100644 bsps/arm/include/libcpu/omap3.h create mode 100644 bsps/arm/include/libcpu/omap_timer.h create mode 100644 bsps/arm/include/uart.h create mode 100644 bsps/arm/lm3s69xx/headers.am create mode 100644 bsps/arm/lm3s69xx/include/bsp.h create mode 100644 bsps/arm/lm3s69xx/include/bsp/io.h create mode 100644 bsps/arm/lm3s69xx/include/bsp/irq.h create mode 100644 bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h create mode 100644 bsps/arm/lm3s69xx/include/bsp/ssi.h create mode 100644 bsps/arm/lm3s69xx/include/bsp/syscon.h create mode 100644 bsps/arm/lm3s69xx/include/bsp/uart.h create mode 100644 bsps/arm/lm3s69xx/include/tm27.h create mode 100644 bsps/arm/lpc176x/headers.am create mode 100644 bsps/arm/lpc176x/include/bsp.h create mode 100755 bsps/arm/lpc176x/include/bsp/adc-defs.h create mode 100755 bsps/arm/lpc176x/include/bsp/adc.h create mode 100755 bsps/arm/lpc176x/include/bsp/can-defs.h create mode 100755 bsps/arm/lpc176x/include/bsp/can.h create mode 100644 bsps/arm/lpc176x/include/bsp/common-types.h create mode 100644 bsps/arm/lpc176x/include/bsp/dma.h create mode 100644 bsps/arm/lpc176x/include/bsp/gpio-defs.h create mode 100644 bsps/arm/lpc176x/include/bsp/io-defs.h create mode 100644 bsps/arm/lpc176x/include/bsp/io.h create mode 100644 bsps/arm/lpc176x/include/bsp/irq.h create mode 100644 bsps/arm/lpc176x/include/bsp/lpc-clock-config.h create mode 100644 bsps/arm/lpc176x/include/bsp/lpc-gpio.h create mode 100644 bsps/arm/lpc176x/include/bsp/lpc176x.h create mode 100755 bsps/arm/lpc176x/include/bsp/mbed-pinmap.h create mode 100755 bsps/arm/lpc176x/include/bsp/pwmout-defs.h create mode 100755 bsps/arm/lpc176x/include/bsp/pwmout.h create mode 100644 bsps/arm/lpc176x/include/bsp/system-clocks.h create mode 100644 bsps/arm/lpc176x/include/bsp/timer-defs.h create mode 100644 bsps/arm/lpc176x/include/bsp/timer.h create mode 100644 bsps/arm/lpc176x/include/bsp/watchdog-defs.h create mode 100644 bsps/arm/lpc176x/include/bsp/watchdog.h create mode 100644 bsps/arm/lpc176x/include/tm27.h create mode 100644 bsps/arm/lpc24xx/headers.am create mode 100644 bsps/arm/lpc24xx/include/bsp.h create mode 100644 bsps/arm/lpc24xx/include/bsp/dma.h create mode 100644 bsps/arm/lpc24xx/include/bsp/i2c.h create mode 100644 bsps/arm/lpc24xx/include/bsp/io.h create mode 100644 bsps/arm/lpc24xx/include/bsp/irq.h create mode 100644 bsps/arm/lpc24xx/include/bsp/lcd.h create mode 100644 bsps/arm/lpc24xx/include/bsp/lpc-clock-config.h create mode 100644 bsps/arm/lpc24xx/include/bsp/lpc-ethernet-config.h create mode 100644 bsps/arm/lpc24xx/include/bsp/lpc17xx.h create mode 100644 bsps/arm/lpc24xx/include/bsp/lpc24xx.h create mode 100644 bsps/arm/lpc24xx/include/bsp/ssp.h create mode 100644 bsps/arm/lpc24xx/include/bsp/start-config.h create mode 100644 bsps/arm/lpc24xx/include/bsp/system-clocks.h create mode 100644 bsps/arm/lpc24xx/include/tm27.h create mode 100644 bsps/arm/lpc32xx/headers.am create mode 100644 bsps/arm/lpc32xx/include/bsp.h create mode 100644 bsps/arm/lpc32xx/include/bsp/boot.h create mode 100644 bsps/arm/lpc32xx/include/bsp/emc.h create mode 100644 bsps/arm/lpc32xx/include/bsp/hsu.h create mode 100644 bsps/arm/lpc32xx/include/bsp/i2c.h create mode 100644 bsps/arm/lpc32xx/include/bsp/irq.h create mode 100644 bsps/arm/lpc32xx/include/bsp/lpc-clock-config.h create mode 100644 bsps/arm/lpc32xx/include/bsp/lpc-ethernet-config.h create mode 100644 bsps/arm/lpc32xx/include/bsp/lpc32xx.h create mode 100644 bsps/arm/lpc32xx/include/bsp/mmu.h create mode 100644 bsps/arm/lpc32xx/include/bsp/nand-mlc.h create mode 100644 bsps/arm/lpc32xx/include/tm27.h create mode 100644 bsps/arm/raspberrypi/headers.am create mode 100644 bsps/arm/raspberrypi/include/bsp.h create mode 100644 bsps/arm/raspberrypi/include/bsp/fbcons.h create mode 100644 bsps/arm/raspberrypi/include/bsp/i2c.h create mode 100644 bsps/arm/raspberrypi/include/bsp/irq.h create mode 100644 bsps/arm/raspberrypi/include/bsp/mailbox.h create mode 100644 bsps/arm/raspberrypi/include/bsp/mmu.h create mode 100644 bsps/arm/raspberrypi/include/bsp/raspberrypi.h create mode 100644 bsps/arm/raspberrypi/include/bsp/rpi-fb.h create mode 100644 bsps/arm/raspberrypi/include/bsp/rpi-gpio.h create mode 100644 bsps/arm/raspberrypi/include/bsp/spi.h create mode 100644 bsps/arm/raspberrypi/include/bsp/usart.h create mode 100644 bsps/arm/raspberrypi/include/bsp/vc.h create mode 100644 bsps/arm/raspberrypi/include/tm27.h create mode 100644 bsps/arm/realview-pbx-a9/headers.am create mode 100644 bsps/arm/realview-pbx-a9/include/bsp.h create mode 100644 bsps/arm/realview-pbx-a9/include/bsp/irq.h create mode 100644 bsps/arm/realview-pbx-a9/include/tm27.h create mode 100644 bsps/arm/rtl22xx/headers.am create mode 100644 bsps/arm/rtl22xx/include/bsp.h create mode 100644 bsps/arm/rtl22xx/include/bsp/irq.h create mode 100644 bsps/arm/rtl22xx/include/lpc22xx.h create mode 100644 bsps/arm/rtl22xx/include/tm27.h create mode 100644 bsps/arm/smdk2410/headers.am create mode 100644 bsps/arm/smdk2410/include/bsp.h create mode 100644 bsps/arm/smdk2410/include/bsp/irq.h create mode 100644 bsps/arm/smdk2410/include/s3c2400.h create mode 100644 bsps/arm/smdk2410/include/s3c2410.h create mode 100644 bsps/arm/smdk2410/include/s3c24xx.h create mode 100644 bsps/arm/smdk2410/include/smc.h create mode 100644 bsps/arm/smdk2410/include/tm27.h create mode 100644 bsps/arm/stm32f4/headers.am create mode 100644 bsps/arm/stm32f4/include/bsp.h create mode 100644 bsps/arm/stm32f4/include/bsp/i2c.h create mode 100644 bsps/arm/stm32f4/include/bsp/io.h create mode 100644 bsps/arm/stm32f4/include/bsp/irq.h create mode 100644 bsps/arm/stm32f4/include/bsp/rcc.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32_i2c.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32_usart.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f10xxx_exti.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f10xxx_gpio.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f10xxx_rcc.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_exti.h create mode 100755 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_gpio.h create mode 100755 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_otgfs.h create mode 100755 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h create mode 100755 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h create mode 100755 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h create mode 100755 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_tim.h create mode 100644 bsps/arm/stm32f4/include/bsp/usart.h create mode 100644 bsps/arm/stm32f4/include/tm27.h create mode 100644 bsps/arm/tms570/headers.am create mode 100644 bsps/arm/tms570/include/bsp.h create mode 100644 bsps/arm/tms570/include/bsp/irq.h create mode 100644 bsps/arm/tms570/include/bsp/system-clocks.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-pinmux.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-pins.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-pom.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-rti.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-sci-driver.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-sci.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-vim.h create mode 100644 bsps/arm/tms570/include/bsp/tms570.h create mode 100644 bsps/arm/tms570/include/bsp/tms570_hwinit.h create mode 100644 bsps/arm/tms570/include/bsp/tms570_selftest.h create mode 100644 bsps/arm/tms570/include/bsp/tms570_selftest_parity.h create mode 100644 bsps/arm/tms570/include/bsp/tms570lc4357-pins.h create mode 100644 bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h create mode 100644 bsps/arm/tms570/include/tm27.h create mode 100644 bsps/arm/xilinx-zynq/headers.am create mode 100644 bsps/arm/xilinx-zynq/include/bsp.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/i2c.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/irq.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h create mode 100644 bsps/arm/xilinx-zynq/include/tm27.h create mode 100644 bsps/bfin/TLL6527M/headers.am create mode 100644 bsps/bfin/TLL6527M/include/bsp.h create mode 100644 bsps/bfin/TLL6527M/include/cplb.h create mode 100644 bsps/bfin/TLL6527M/include/tm27.h create mode 100644 bsps/bfin/bf537Stamp/headers.am create mode 100644 bsps/bfin/bf537Stamp/include/bsp.h create mode 100644 bsps/bfin/bf537Stamp/include/tm27.h create mode 100644 bsps/bfin/eZKit533/headers.am create mode 100644 bsps/bfin/eZKit533/include/bsp.h create mode 100644 bsps/bfin/eZKit533/include/cplb.h create mode 100644 bsps/bfin/eZKit533/include/tm27.h create mode 100644 bsps/bfin/headers.am create mode 100644 bsps/bfin/include/bf52x.h create mode 100644 bsps/bfin/include/bsp/interrupt.h create mode 100644 bsps/bfin/include/libcpu/bf533.h create mode 100644 bsps/bfin/include/libcpu/bf537.h create mode 100644 bsps/bfin/include/libcpu/cecRegs.h create mode 100644 bsps/bfin/include/libcpu/coreTimerRegs.h create mode 100644 bsps/bfin/include/libcpu/dmaRegs.h create mode 100644 bsps/bfin/include/libcpu/ebiuRegs.h create mode 100644 bsps/bfin/include/libcpu/ethernet.h create mode 100644 bsps/bfin/include/libcpu/ethernetRegs.h create mode 100644 bsps/bfin/include/libcpu/gpioRegs.h create mode 100644 bsps/bfin/include/libcpu/interrupt.h create mode 100644 bsps/bfin/include/libcpu/memoryRegs.h create mode 100644 bsps/bfin/include/libcpu/mmu.h create mode 100644 bsps/bfin/include/libcpu/mmuRegs.h create mode 100644 bsps/bfin/include/libcpu/ppiRegs.h create mode 100644 bsps/bfin/include/libcpu/rtcRegs.h create mode 100644 bsps/bfin/include/libcpu/sicRegs.h create mode 100644 bsps/bfin/include/libcpu/spi.h create mode 100644 bsps/bfin/include/libcpu/spiRegs.h create mode 100644 bsps/bfin/include/libcpu/sport.h create mode 100644 bsps/bfin/include/libcpu/sportRegs.h create mode 100644 bsps/bfin/include/libcpu/timerRegs.h create mode 100644 bsps/bfin/include/libcpu/twi.h create mode 100644 bsps/bfin/include/libcpu/twiRegs.h create mode 100644 bsps/bfin/include/libcpu/uart.h create mode 100644 bsps/bfin/include/libcpu/uartRegs.h create mode 100644 bsps/bfin/include/libcpu/wdogRegs.h create mode 100644 bsps/epiphany/epiphany_sim/headers.am create mode 100644 bsps/epiphany/epiphany_sim/include/bsp.h create mode 100644 bsps/epiphany/epiphany_sim/include/bsp/irq.h create mode 100644 bsps/epiphany/epiphany_sim/include/tm27.h create mode 100644 bsps/epiphany/headers.am create mode 100644 bsps/epiphany/include/bsp/linker-symbols.h create mode 100644 bsps/headers.am create mode 100644 bsps/i386/headers.am create mode 100644 bsps/i386/include/bsp/apic.h create mode 100644 bsps/i386/include/bsp/irq.h create mode 100644 bsps/i386/include/bsp/irq_asm.h create mode 100644 bsps/i386/include/bsp/realmode_int.h create mode 100644 bsps/i386/include/bsp/smp-imps.h create mode 100644 bsps/i386/include/bsp/tty_drv.h create mode 100644 bsps/i386/include/i386_io.h create mode 100644 bsps/i386/include/libcpu/byteorder.h create mode 100644 bsps/i386/include/libcpu/cpuModel.h create mode 100644 bsps/i386/include/libcpu/page.h create mode 100644 bsps/i386/include/uart.h create mode 100644 bsps/i386/pc386/headers.am create mode 100644 bsps/i386/pc386/include/bsp.h create mode 100644 bsps/i386/pc386/include/bsp/bspimpl.h create mode 100644 bsps/i386/pc386/include/bsp/exar17d15x.h create mode 100644 bsps/i386/pc386/include/bsp/fb_default_mode.h create mode 100644 bsps/i386/pc386/include/bsp/fb_vesa.h create mode 100644 bsps/i386/pc386/include/bsp/rtd316.h create mode 100644 bsps/i386/pc386/include/bsp/tblsizes.h create mode 100644 bsps/i386/pc386/include/bsp/vbe3.h create mode 100644 bsps/i386/pc386/include/crt.h create mode 100644 bsps/i386/pc386/include/edid.h create mode 100644 bsps/i386/pc386/include/rtems/kd.h create mode 100644 bsps/i386/pc386/include/rtems/keyboard.h create mode 100644 bsps/i386/pc386/include/rtems/ps2_drv.h create mode 100644 bsps/i386/pc386/include/rtems/vgacons.h create mode 100644 bsps/i386/pc386/include/tm27.h create mode 100644 bsps/include/bsp/VME.h create mode 100644 bsps/include/bsp/VMEDMA.h create mode 100644 bsps/include/bsp/bootcard.h create mode 100644 bsps/include/bsp/bspVmeDmaList.h create mode 100644 bsps/include/bsp/console-polled.h create mode 100644 bsps/include/bsp/console-termios.h create mode 100644 bsps/include/bsp/default-initial-extension.h create mode 100644 bsps/include/bsp/fatal.h create mode 100644 bsps/include/bsp/fdt.h create mode 100644 bsps/include/bsp/gpio.h create mode 100644 bsps/include/bsp/irq-generic.h create mode 100644 bsps/include/bsp/irq-info.h create mode 100644 bsps/include/bsp/mm.h create mode 100644 bsps/include/bsp/stackalloc.h create mode 100644 bsps/include/bsp/u-boot.h create mode 100644 bsps/include/bsp/uart-output-char.h create mode 100644 bsps/include/bsp/utility.h create mode 100644 bsps/include/bsp/vmeTsi148.h create mode 100644 bsps/include/bsp/vmeTsi148DMA.h create mode 100644 bsps/include/bsp/vmeUniverse.h create mode 100644 bsps/include/bsp/vmeUniverseDMA.h create mode 100644 bsps/include/bsp/vme_am_defs.h create mode 100644 bsps/include/libchip/am29lv160.h create mode 100644 bsps/include/libchip/ata.h create mode 100644 bsps/include/libchip/ata_internal.h create mode 100644 bsps/include/libchip/cs8900.h create mode 100644 bsps/include/libchip/disp_hcms29xx.h create mode 100644 bsps/include/libchip/ds1375-rtc.h create mode 100644 bsps/include/libchip/greth.h create mode 100644 bsps/include/libchip/i2c-2b-eeprom.h create mode 100644 bsps/include/libchip/i2c-ds1621.h create mode 100644 bsps/include/libchip/i2c-sc620.h create mode 100644 bsps/include/libchip/i82586var.h create mode 100644 bsps/include/libchip/icm7170.h create mode 100644 bsps/include/libchip/ide_ctrl.h create mode 100644 bsps/include/libchip/ide_ctrl_cfg.h create mode 100644 bsps/include/libchip/ide_ctrl_io.h create mode 100644 bsps/include/libchip/if_dcreg.h create mode 100644 bsps/include/libchip/if_fxpvar.h create mode 100644 bsps/include/libchip/m48t08.h create mode 100644 bsps/include/libchip/mc146818a.h create mode 100644 bsps/include/libchip/mc68681.h create mode 100644 bsps/include/libchip/ns16550.h create mode 100755 bsps/include/libchip/ns16550_p.h create mode 100644 bsps/include/libchip/open_eth.h create mode 100644 bsps/include/libchip/rtc.h create mode 100644 bsps/include/libchip/serial.h create mode 100644 bsps/include/libchip/sersupp.h create mode 100644 bsps/include/libchip/smc91111.h create mode 100644 bsps/include/libchip/smc91111exp.h create mode 100644 bsps/include/libchip/sonic.h create mode 100644 bsps/include/libchip/spi-flash-m25p40.h create mode 100644 bsps/include/libchip/spi-fram-fm25l256.h create mode 100644 bsps/include/libchip/spi-memdrv.h create mode 100644 bsps/include/libchip/spi-sd-card.h create mode 100644 bsps/include/libchip/wd80x3.h create mode 100644 bsps/include/libchip/z85c30.h create mode 100644 bsps/include/mpci.h create mode 100644 bsps/include/rtems/umon.h create mode 100644 bsps/include/rtems/zilog/z8036.h create mode 100644 bsps/include/rtems/zilog/z8530.h create mode 100644 bsps/include/shm_driver.h create mode 100644 bsps/include/umon/cli.h create mode 100644 bsps/include/umon/monlib.h create mode 100644 bsps/include/umon/tfs.h create mode 100644 bsps/lm32/headers.am create mode 100644 bsps/lm32/include/bsp/irq.h create mode 100644 bsps/lm32/include/bsp/milkymist_ac97.h create mode 100644 bsps/lm32/include/bsp/milkymist_buttons.h create mode 100644 bsps/lm32/include/bsp/milkymist_dmx.h create mode 100644 bsps/lm32/include/bsp/milkymist_flash.h create mode 100644 bsps/lm32/include/bsp/milkymist_gpio.h create mode 100644 bsps/lm32/include/bsp/milkymist_ir.h create mode 100644 bsps/lm32/include/bsp/milkymist_memcard.h create mode 100644 bsps/lm32/include/bsp/milkymist_midi.h create mode 100644 bsps/lm32/include/bsp/milkymist_pfpu.h create mode 100644 bsps/lm32/include/bsp/milkymist_tmu.h create mode 100644 bsps/lm32/include/bsp/milkymist_usbinput.h create mode 100644 bsps/lm32/include/bsp/milkymist_versions.h create mode 100644 bsps/lm32/include/bsp/milkymist_video.h create mode 100644 bsps/lm32/lm32_evr/headers.am create mode 100644 bsps/lm32/lm32_evr/include/bsp.h create mode 100644 bsps/lm32/lm32_evr/include/system_conf.h create mode 100644 bsps/lm32/lm32_evr/include/tm27.h create mode 100644 bsps/lm32/milkymist/headers.am create mode 100644 bsps/lm32/milkymist/include/bsp.h create mode 100644 bsps/lm32/milkymist/include/system_conf.h create mode 100644 bsps/lm32/milkymist/include/tm27.h create mode 100644 bsps/m32c/m32cbsp/headers.am create mode 100644 bsps/m32c/m32cbsp/include/bsp.h create mode 100644 bsps/m32c/m32cbsp/include/tm27.h create mode 100644 bsps/m68k/av5282/headers.am create mode 100644 bsps/m68k/av5282/include/bsp.h create mode 100644 bsps/m68k/av5282/include/tm27.h create mode 100644 bsps/m68k/csb360/headers.am create mode 100644 bsps/m68k/csb360/include/bsp.h create mode 100644 bsps/m68k/csb360/include/tm27.h create mode 100644 bsps/m68k/gen68340/headers.am create mode 100644 bsps/m68k/gen68340/include/bsp.h create mode 100644 bsps/m68k/gen68340/include/m340timer.h create mode 100644 bsps/m68k/gen68340/include/m340uart.h create mode 100644 bsps/m68k/gen68340/include/m68340.h create mode 100644 bsps/m68k/gen68340/include/m68340.inc create mode 100644 bsps/m68k/gen68340/include/m68349.inc create mode 100644 bsps/m68k/gen68340/include/tm27.h create mode 100644 bsps/m68k/gen68360/headers.am create mode 100644 bsps/m68k/gen68360/include/bsp.h create mode 100644 bsps/m68k/gen68360/include/tm27.h create mode 100644 bsps/m68k/genmcf548x/headers.am create mode 100644 bsps/m68k/genmcf548x/include/bsp.h create mode 100644 bsps/m68k/genmcf548x/include/bsp/irq.h create mode 100644 bsps/m68k/genmcf548x/include/tm27.h create mode 100644 bsps/m68k/headers.am create mode 100644 bsps/m68k/include/bsp/linker-symbols.h create mode 100644 bsps/m68k/include/mcf5206/mcf5206e.h create mode 100644 bsps/m68k/include/mcf5206/mcfmbus.h create mode 100644 bsps/m68k/include/mcf5206/mcfuart.h create mode 100644 bsps/m68k/include/mcf5223x/mcf5223x.h create mode 100644 bsps/m68k/include/mcf5225x/fec.h create mode 100644 bsps/m68k/include/mcf5225x/mcf5225x.h create mode 100644 bsps/m68k/include/mcf5235/mcf5235.h create mode 100644 bsps/m68k/include/mcf5272/mcf5272.h create mode 100644 bsps/m68k/include/mcf5282/mcf5282.h create mode 100644 bsps/m68k/include/mcf532x/mcf532x.h create mode 100644 bsps/m68k/include/mcf548x/MCD_dma.h create mode 100644 bsps/m68k/include/mcf548x/MCD_progCheck.h create mode 100644 bsps/m68k/include/mcf548x/MCD_tasksInit.h create mode 100644 bsps/m68k/include/mcf548x/mcdma_glue.h create mode 100644 bsps/m68k/include/mcf548x/mcf548x.h create mode 100644 bsps/m68k/include/mvme16x_hw.h create mode 100644 bsps/m68k/mcf5206elite/headers.am create mode 100644 bsps/m68k/mcf5206elite/include/bsp.h create mode 100644 bsps/m68k/mcf5206elite/include/ds1307.h create mode 100644 bsps/m68k/mcf5206elite/include/i2c.h create mode 100644 bsps/m68k/mcf5206elite/include/i2cdrv.h create mode 100644 bsps/m68k/mcf5206elite/include/nvram.h create mode 100644 bsps/m68k/mcf5206elite/include/tm27.h create mode 100644 bsps/m68k/mcf52235/headers.am create mode 100644 bsps/m68k/mcf52235/include/bsp.h create mode 100644 bsps/m68k/mcf52235/include/tm27.h create mode 100644 bsps/m68k/mcf5225x/headers.am create mode 100644 bsps/m68k/mcf5225x/include/bsp.h create mode 100644 bsps/m68k/mcf5225x/include/tm27.h create mode 100644 bsps/m68k/mcf5235/headers.am create mode 100644 bsps/m68k/mcf5235/include/bsp.h create mode 100644 bsps/m68k/mcf5235/include/tm27.h create mode 100644 bsps/m68k/mcf5329/headers.am create mode 100644 bsps/m68k/mcf5329/include/bsp.h create mode 100644 bsps/m68k/mcf5329/include/tm27.h create mode 100644 bsps/m68k/mrm332/headers.am create mode 100644 bsps/m68k/mrm332/include/bsp.h create mode 100644 bsps/m68k/mrm332/include/mrm332.h create mode 100644 bsps/m68k/mrm332/include/tm27.h create mode 100644 bsps/m68k/mvme147/headers.am create mode 100644 bsps/m68k/mvme147/include/bsp.h create mode 100644 bsps/m68k/mvme147/include/tm27.h create mode 100644 bsps/m68k/mvme147s/headers.am create mode 100644 bsps/m68k/mvme147s/include/bsp.h create mode 100644 bsps/m68k/mvme147s/include/tm27.h create mode 100644 bsps/m68k/mvme162/headers.am create mode 100644 bsps/m68k/mvme162/include/bsp.h create mode 100644 bsps/m68k/mvme162/include/page_table.h create mode 100644 bsps/m68k/mvme162/include/tm27.h create mode 100644 bsps/m68k/mvme167/headers.am create mode 100644 bsps/m68k/mvme167/include/bsp.h create mode 100644 bsps/m68k/mvme167/include/page_table.h create mode 100644 bsps/m68k/mvme167/include/tm27.h create mode 100644 bsps/m68k/uC5282/headers.am create mode 100644 bsps/m68k/uC5282/include/bsp.h create mode 100644 bsps/m68k/uC5282/include/tm27.h create mode 100644 bsps/mips/csb350/headers.am create mode 100644 bsps/mips/csb350/include/bsp.h create mode 100644 bsps/mips/csb350/include/bsp/irq.h create mode 100644 bsps/mips/csb350/include/tm27.h create mode 100644 bsps/mips/headers.am create mode 100644 bsps/mips/hurricane/headers.am create mode 100644 bsps/mips/hurricane/include/bsp.h create mode 100644 bsps/mips/hurricane/include/bsp/irq.h create mode 100644 bsps/mips/hurricane/include/tm27.h create mode 100644 bsps/mips/hurricane/include/usc.h create mode 100644 bsps/mips/include/bsp/i8259.h create mode 100644 bsps/mips/include/bsp/regs.h create mode 100644 bsps/mips/include/libcpu/au1x00.h create mode 100644 bsps/mips/include/libcpu/isr_entries.h create mode 100644 bsps/mips/include/libcpu/rm5231.h create mode 100644 bsps/mips/include/libcpu/tx3904.h create mode 100644 bsps/mips/include/libcpu/tx4925.h create mode 100644 bsps/mips/include/libcpu/tx4938.h create mode 100644 bsps/mips/jmr3904/headers.am create mode 100644 bsps/mips/jmr3904/include/bsp.h create mode 100644 bsps/mips/jmr3904/include/bsp/irq.h create mode 100644 bsps/mips/jmr3904/include/tm27.h create mode 100644 bsps/mips/malta/headers.am create mode 100644 bsps/mips/malta/include/bsp.h create mode 100644 bsps/mips/malta/include/bsp/irq.h create mode 100644 bsps/mips/malta/include/bsp/pci.h create mode 100644 bsps/mips/malta/include/tm27.h create mode 100644 bsps/mips/rbtx4925/headers.am create mode 100644 bsps/mips/rbtx4925/include/bsp.h create mode 100644 bsps/mips/rbtx4925/include/bsp/irq.h create mode 100644 bsps/mips/rbtx4925/include/tm27.h create mode 100644 bsps/mips/rbtx4938/headers.am create mode 100644 bsps/mips/rbtx4938/include/bsp.h create mode 100644 bsps/mips/rbtx4938/include/bsp/irq.h create mode 100644 bsps/mips/rbtx4938/include/tm27.h create mode 100644 bsps/moxie/moxiesim/headers.am create mode 100644 bsps/moxie/moxiesim/include/bsp.h create mode 100644 bsps/moxie/moxiesim/include/tm27.h create mode 100644 bsps/nios2/nios2_iss/headers.am create mode 100644 bsps/nios2/nios2_iss/include/bsp.h create mode 100644 bsps/nios2/nios2_iss/include/tm27.h create mode 100644 bsps/no_cpu/no_bsp/headers.am create mode 100644 bsps/no_cpu/no_bsp/include/bsp.h create mode 100644 bsps/no_cpu/no_bsp/include/tm27.h create mode 100644 bsps/or1k/generic_or1k/headers.am create mode 100644 bsps/or1k/generic_or1k/include/bsp.h create mode 100644 bsps/or1k/generic_or1k/include/bsp/generic_or1k.h create mode 100644 bsps/or1k/generic_or1k/include/bsp/irq.h create mode 100644 bsps/or1k/generic_or1k/include/bsp/uart.h create mode 100644 bsps/or1k/generic_or1k/include/tm27.h create mode 100644 bsps/or1k/headers.am create mode 100644 bsps/or1k/include/bsp/cache_.h create mode 100644 bsps/or1k/include/bsp/linker-symbols.h create mode 100644 bsps/powerpc/beatnik/headers.am create mode 100644 bsps/powerpc/beatnik/include/bsp.h create mode 100644 bsps/powerpc/beatnik/include/bsp/VMEConfig.h create mode 100644 bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h create mode 100644 bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h create mode 100644 bsps/powerpc/beatnik/include/bsp/gt_timer.h create mode 100644 bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h create mode 100644 bsps/powerpc/beatnik/include/bsp/gti2creg.h create mode 100644 bsps/powerpc/beatnik/include/bsp/gtintrreg.h create mode 100644 bsps/powerpc/beatnik/include/bsp/gtpcireg.h create mode 100644 bsps/powerpc/beatnik/include/bsp/gtreg.h create mode 100644 bsps/powerpc/beatnik/include/bsp/if_em_pub.h create mode 100644 bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h create mode 100644 bsps/powerpc/beatnik/include/bsp/if_mve_pub.h create mode 100644 bsps/powerpc/beatnik/include/bsp/irq.h create mode 100644 bsps/powerpc/beatnik/include/tm27.h create mode 100644 bsps/powerpc/gen5200/headers.am create mode 100644 bsps/powerpc/gen5200/include/bsp.h create mode 100644 bsps/powerpc/gen5200/include/bsp/ata.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h create mode 100644 bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h create mode 100644 bsps/powerpc/gen5200/include/bsp/i2c.h create mode 100644 bsps/powerpc/gen5200/include/bsp/i2cdrv.h create mode 100644 bsps/powerpc/gen5200/include/bsp/irq.h create mode 100644 bsps/powerpc/gen5200/include/bsp/mpc5200.h create mode 100644 bsps/powerpc/gen5200/include/bsp/mscan-base.h create mode 100644 bsps/powerpc/gen5200/include/bsp/mscan.h create mode 100644 bsps/powerpc/gen5200/include/bsp/nvram.h create mode 100644 bsps/powerpc/gen5200/include/bsp/slicetimer.h create mode 100644 bsps/powerpc/gen5200/include/bsp/u-boot-config.h create mode 100644 bsps/powerpc/gen5200/include/tm27.h create mode 100644 bsps/powerpc/gen83xx/headers.am create mode 100644 bsps/powerpc/gen83xx/include/bsp.h create mode 100644 bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h create mode 100644 bsps/powerpc/gen83xx/include/bsp/irq.h create mode 100644 bsps/powerpc/gen83xx/include/bsp/tsec-config.h create mode 100644 bsps/powerpc/gen83xx/include/bsp/u-boot-config.h create mode 100644 bsps/powerpc/gen83xx/include/tm27.h create mode 100644 bsps/powerpc/haleakala/headers.am create mode 100644 bsps/powerpc/haleakala/include/bsp.h create mode 100644 bsps/powerpc/haleakala/include/bsp/irq.h create mode 100644 bsps/powerpc/haleakala/include/mmu_405.h create mode 100644 bsps/powerpc/haleakala/include/tm27.h create mode 100644 bsps/powerpc/headers.am create mode 100644 bsps/powerpc/include/bsp/consoleIo.h create mode 100644 bsps/powerpc/include/bsp/flashPgm.h create mode 100644 bsps/powerpc/include/bsp/flashPgmPvt.h create mode 100644 bsps/powerpc/include/bsp/irq_supp.h create mode 100644 bsps/powerpc/include/bsp/linker-symbols.h create mode 100644 bsps/powerpc/include/bsp/motorola.h create mode 100644 bsps/powerpc/include/bsp/openpic.h create mode 100644 bsps/powerpc/include/bsp/pci.h create mode 100644 bsps/powerpc/include/bsp/pnp.h create mode 100644 bsps/powerpc/include/bsp/residual.h create mode 100644 bsps/powerpc/include/bsp/start.h create mode 100644 bsps/powerpc/include/bsp/tictac.h create mode 100644 bsps/powerpc/include/bsp/tsec.h create mode 100644 bsps/powerpc/include/bsp/u-boot-board-info.h create mode 100644 bsps/powerpc/include/bsp/uart.h create mode 100644 bsps/powerpc/include/bsp/vectors.h create mode 100644 bsps/powerpc/include/bsp/vpd.h create mode 100644 bsps/powerpc/include/ictrl.h create mode 100644 bsps/powerpc/include/libcpu/bat.h create mode 100644 bsps/powerpc/include/libcpu/byteorder.h create mode 100644 bsps/powerpc/include/libcpu/c_clock.h create mode 100755 bsps/powerpc/include/libcpu/cpuIdent.h create mode 100644 bsps/powerpc/include/libcpu/e500_mmu.h create mode 100644 bsps/powerpc/include/libcpu/io.h create mode 100644 bsps/powerpc/include/libcpu/irq.h create mode 100644 bsps/powerpc/include/libcpu/mmu.h create mode 100644 bsps/powerpc/include/libcpu/page.h create mode 100644 bsps/powerpc/include/libcpu/pgtable.h create mode 100644 bsps/powerpc/include/libcpu/powerpc-utility.h create mode 100644 bsps/powerpc/include/libcpu/pte121.h create mode 100644 bsps/powerpc/include/libcpu/raw_exception.h create mode 100644 bsps/powerpc/include/libcpu/spr.h create mode 100644 bsps/powerpc/include/libcpu/stackTrace.h create mode 100644 bsps/powerpc/include/libcpu/vectors.h create mode 100644 bsps/powerpc/include/mpc55xx/dspi.h create mode 100644 bsps/powerpc/include/mpc55xx/edma.h create mode 100644 bsps/powerpc/include/mpc55xx/emios.h create mode 100644 bsps/powerpc/include/mpc55xx/fsl-mpc551x.h create mode 100644 bsps/powerpc/include/mpc55xx/fsl-mpc555x.h create mode 100644 bsps/powerpc/include/mpc55xx/fsl-mpc556x.h create mode 100644 bsps/powerpc/include/mpc55xx/fsl-mpc564xL.h create mode 100644 bsps/powerpc/include/mpc55xx/fsl-mpc5668.h create mode 100644 bsps/powerpc/include/mpc55xx/fsl-mpc567x.h create mode 100644 bsps/powerpc/include/mpc55xx/mpc55xx.h create mode 100644 bsps/powerpc/include/mpc55xx/reg-defs.h create mode 100644 bsps/powerpc/include/mpc55xx/regs-edma.h create mode 100644 bsps/powerpc/include/mpc55xx/regs-mmu.h create mode 100644 bsps/powerpc/include/mpc55xx/regs.h create mode 100644 bsps/powerpc/include/mpc55xx/siu.h create mode 100644 bsps/powerpc/include/mpc55xx/watchdog.h create mode 100644 bsps/powerpc/include/mpc5xx.h create mode 100644 bsps/powerpc/include/mpc5xx/console.h create mode 100644 bsps/powerpc/include/mpc8260.h create mode 100644 bsps/powerpc/include/mpc8260/console.h create mode 100644 bsps/powerpc/include/mpc8260/cpm.h create mode 100644 bsps/powerpc/include/mpc8260/mmu.h create mode 100644 bsps/powerpc/include/mpc83xx/gtm.h create mode 100644 bsps/powerpc/include/mpc83xx/mpc83xx.h create mode 100644 bsps/powerpc/include/mpc83xx/mpc83xx_i2cdrv.h create mode 100644 bsps/powerpc/include/mpc83xx/mpc83xx_spidrv.h create mode 100644 bsps/powerpc/include/mpc8xx.h create mode 100644 bsps/powerpc/include/mpc8xx/console.h create mode 100644 bsps/powerpc/include/mpc8xx/cpm.h create mode 100644 bsps/powerpc/include/mpc8xx/mmu.h create mode 100644 bsps/powerpc/include/nvram.h create mode 100644 bsps/powerpc/include/ppc4xx/ppc405ex.h create mode 100644 bsps/powerpc/include/ppc4xx/ppc405gp.h create mode 100644 bsps/powerpc/include/rtems/powerpc/cache.h create mode 100644 bsps/powerpc/include/rtems/powerpc/debugmod.h create mode 100644 bsps/powerpc/include/rtems/powerpc/powerpc.h create mode 100644 bsps/powerpc/include/tty_drv.h create mode 100644 bsps/powerpc/motorola_powerpc/headers.am create mode 100644 bsps/powerpc/motorola_powerpc/include/bsp.h create mode 100644 bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h create mode 100644 bsps/powerpc/motorola_powerpc/include/bsp/irq.h create mode 100644 bsps/powerpc/motorola_powerpc/include/tm27.h create mode 100644 bsps/powerpc/mpc55xxevb/headers.am create mode 100644 bsps/powerpc/mpc55xxevb/include/bsp.h create mode 100644 bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h create mode 100644 bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h create mode 100644 bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h create mode 100644 bsps/powerpc/mpc55xxevb/include/bsp/irq.h create mode 100644 bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h create mode 100644 bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h create mode 100644 bsps/powerpc/mpc55xxevb/include/tm27.h create mode 100644 bsps/powerpc/mpc8260ads/headers.am create mode 100644 bsps/powerpc/mpc8260ads/include/bsp.h create mode 100644 bsps/powerpc/mpc8260ads/include/bsp/irq.h create mode 100644 bsps/powerpc/mpc8260ads/include/tm27.h create mode 100644 bsps/powerpc/mvme3100/headers.am create mode 100644 bsps/powerpc/mvme3100/include/bsp.h create mode 100644 bsps/powerpc/mvme3100/include/bsp/VMEConfig.h create mode 100644 bsps/powerpc/mvme3100/include/bsp/if_tsec_pub.h create mode 100644 bsps/powerpc/mvme3100/include/bsp/irq.h create mode 100644 bsps/powerpc/mvme3100/include/bsp/mpc8540_i2c_busdrv.h create mode 100644 bsps/powerpc/mvme3100/include/tm27.h create mode 100644 bsps/powerpc/mvme5500/headers.am create mode 100644 bsps/powerpc/mvme5500/include/bsp.h create mode 100644 bsps/powerpc/mvme5500/include/bsp/GT64260TWSI.h create mode 100644 bsps/powerpc/mvme5500/include/bsp/GT64260eth.h create mode 100644 bsps/powerpc/mvme5500/include/bsp/GT64260ethreg.h create mode 100644 bsps/powerpc/mvme5500/include/bsp/VMEConfig.h create mode 100644 bsps/powerpc/mvme5500/include/bsp/VPD.h create mode 100644 bsps/powerpc/mvme5500/include/bsp/bspException.h create mode 100644 bsps/powerpc/mvme5500/include/bsp/bspMvme5500.h create mode 100644 bsps/powerpc/mvme5500/include/bsp/gtpcireg.h create mode 100644 bsps/powerpc/mvme5500/include/bsp/gtreg.h create mode 100644 bsps/powerpc/mvme5500/include/bsp/if_wmreg.h create mode 100644 bsps/powerpc/mvme5500/include/bsp/irq.h create mode 100644 bsps/powerpc/mvme5500/include/bsp/pcireg.h create mode 100644 bsps/powerpc/mvme5500/include/tm27.h create mode 100644 bsps/powerpc/psim/headers.am create mode 100644 bsps/powerpc/psim/include/bsp.h create mode 100644 bsps/powerpc/psim/include/bsp/irq.h create mode 100644 bsps/powerpc/psim/include/psim.h create mode 100644 bsps/powerpc/psim/include/tm27.h create mode 100644 bsps/powerpc/qemuppc/headers.am create mode 100644 bsps/powerpc/qemuppc/include/bsp.h create mode 100644 bsps/powerpc/qemuppc/include/bsp/irq.h create mode 100644 bsps/powerpc/qemuppc/include/tm27.h create mode 100644 bsps/powerpc/qoriq/headers.am create mode 100644 bsps/powerpc/qoriq/include/asm/epapr_hcalls.h create mode 100644 bsps/powerpc/qoriq/include/asm/fsl_hcalls.h create mode 100644 bsps/powerpc/qoriq/include/bsp.h create mode 100644 bsps/powerpc/qoriq/include/bsp/intercom.h create mode 100644 bsps/powerpc/qoriq/include/bsp/irq.h create mode 100644 bsps/powerpc/qoriq/include/bsp/mmu.h create mode 100644 bsps/powerpc/qoriq/include/bsp/qoriq.h create mode 100644 bsps/powerpc/qoriq/include/bsp/tsec-config.h create mode 100644 bsps/powerpc/qoriq/include/bsp/uart-bridge.h create mode 100644 bsps/powerpc/qoriq/include/tm27.h create mode 100644 bsps/powerpc/qoriq/include/uapi/asm/epapr_hcalls.h create mode 100644 bsps/powerpc/ss555/headers.am create mode 100644 bsps/powerpc/ss555/include/bsp.h create mode 100644 bsps/powerpc/ss555/include/bsp/irq.h create mode 100644 bsps/powerpc/ss555/include/tm27.h create mode 100644 bsps/powerpc/t32mppc/headers.am create mode 100644 bsps/powerpc/t32mppc/include/bsp.h create mode 100644 bsps/powerpc/t32mppc/include/bsp/irq.h create mode 100644 bsps/powerpc/t32mppc/include/tm27.h create mode 100644 bsps/powerpc/tqm8xx/headers.am create mode 100644 bsps/powerpc/tqm8xx/include/bsp.h create mode 100644 bsps/powerpc/tqm8xx/include/bsp/8xx_immap.h create mode 100644 bsps/powerpc/tqm8xx/include/bsp/irq.h create mode 100644 bsps/powerpc/tqm8xx/include/bsp/spi.h create mode 100644 bsps/powerpc/tqm8xx/include/bsp/tqm.h create mode 100644 bsps/powerpc/tqm8xx/include/tm27.h create mode 100644 bsps/powerpc/virtex/headers.am create mode 100644 bsps/powerpc/virtex/include/bsp.h create mode 100644 bsps/powerpc/virtex/include/bsp/irq.h create mode 100644 bsps/powerpc/virtex/include/bsp/opbintctrl.h create mode 100644 bsps/powerpc/virtex/include/tm27.h create mode 100644 bsps/powerpc/virtex/include/xiltemac.h create mode 100644 bsps/powerpc/virtex/include/xparameters_dflt.h create mode 100644 bsps/powerpc/virtex4/headers.am create mode 100644 bsps/powerpc/virtex4/include/bsp.h create mode 100644 bsps/powerpc/virtex4/include/bsp/irq.h create mode 100644 bsps/powerpc/virtex4/include/bsp/mmu.h create mode 100644 bsps/powerpc/virtex4/include/tm27.h create mode 100644 bsps/powerpc/virtex5/headers.am create mode 100644 bsps/powerpc/virtex5/include/bsp.h create mode 100644 bsps/powerpc/virtex5/include/bsp/irq.h create mode 100644 bsps/powerpc/virtex5/include/bsp/mmu.h create mode 100644 bsps/powerpc/virtex5/include/tm27.h create mode 100644 bsps/riscv/headers.am create mode 100644 bsps/riscv/include/bsp/linker-symbols.h create mode 100644 bsps/riscv/riscv_generic/headers.am create mode 100644 bsps/riscv/riscv_generic/include/bsp.h create mode 100644 bsps/riscv/riscv_generic/include/bsp/irq.h create mode 100644 bsps/riscv/riscv_generic/include/tm27.h create mode 100644 bsps/sh/gensh1/headers.am create mode 100644 bsps/sh/gensh1/include/bsp.h create mode 100644 bsps/sh/gensh1/include/rtems/score/iosh7032.h create mode 100644 bsps/sh/gensh1/include/rtems/score/ispsh7032.h create mode 100644 bsps/sh/gensh1/include/sh/sci.h create mode 100644 bsps/sh/gensh1/include/sh/sh7_pfc.h create mode 100644 bsps/sh/gensh1/include/sh/sh7_sci.h create mode 100644 bsps/sh/gensh1/include/tm27.h create mode 100644 bsps/sh/gensh2/headers.am create mode 100644 bsps/sh/gensh2/include/bsp.h create mode 100644 bsps/sh/gensh2/include/rtems/score/iosh7045.h create mode 100644 bsps/sh/gensh2/include/rtems/score/ispsh7045.h create mode 100644 bsps/sh/gensh2/include/sh/io_types.h create mode 100644 bsps/sh/gensh2/include/sh/sci.h create mode 100644 bsps/sh/gensh2/include/sh/sci_termios.h create mode 100644 bsps/sh/gensh2/include/sh/sh7_pfc.h create mode 100644 bsps/sh/gensh2/include/sh/sh7_sci.h create mode 100644 bsps/sh/gensh2/include/tm27.h create mode 100644 bsps/sh/gensh4/headers.am create mode 100644 bsps/sh/gensh4/include/bsp.h create mode 100644 bsps/sh/gensh4/include/rtems/score/iosh7750.h create mode 100644 bsps/sh/gensh4/include/rtems/score/ipl.h create mode 100644 bsps/sh/gensh4/include/rtems/score/ispsh7750.h create mode 100644 bsps/sh/gensh4/include/rtems/score/sh4_regs.h create mode 100644 bsps/sh/gensh4/include/rtems/score/sh7750_regs.h create mode 100644 bsps/sh/gensh4/include/sdram.h create mode 100644 bsps/sh/gensh4/include/sh/sh4uart.h create mode 100644 bsps/sh/gensh4/include/tm27.h create mode 100644 bsps/sh/shsim/headers.am create mode 100644 bsps/sh/shsim/include/bsp.h create mode 100644 bsps/sh/shsim/include/bsp/syscall.h create mode 100644 bsps/sh/shsim/include/tm27.h create mode 100644 bsps/sparc/erc32/headers.am create mode 100644 bsps/sparc/erc32/include/bsp.h create mode 100644 bsps/sparc/erc32/include/bsp/irq.h create mode 100644 bsps/sparc/erc32/include/erc32.h create mode 100644 bsps/sparc/erc32/include/tm27.h create mode 100644 bsps/sparc/headers.am create mode 100644 bsps/sparc/include/ambapp.h create mode 100644 bsps/sparc/include/ambapp_ids.h create mode 100644 bsps/sparc/include/bsp/ahbstat.h create mode 100644 bsps/sparc/include/bsp/apbuart.h create mode 100644 bsps/sparc/include/bsp/apbuart_cons.h create mode 100644 bsps/sparc/include/bsp/apbuart_termios.h create mode 100644 bsps/sparc/include/bsp/b1553brm.h create mode 100644 bsps/sparc/include/bsp/b1553rt.h create mode 100644 bsps/sparc/include/bsp/canmux.h create mode 100644 bsps/sparc/include/bsp/cons.h create mode 100644 bsps/sparc/include/bsp/debug_defs.h create mode 100644 bsps/sparc/include/bsp/genirq.h create mode 100644 bsps/sparc/include/bsp/gnatcommon.h create mode 100644 bsps/sparc/include/bsp/gpiolib.h create mode 100644 bsps/sparc/include/bsp/gptimer.h create mode 100644 bsps/sparc/include/bsp/gr1553b.h create mode 100644 bsps/sparc/include/bsp/gr1553bc.h create mode 100644 bsps/sparc/include/bsp/gr1553bc_list.h create mode 100644 bsps/sparc/include/bsp/gr1553bm.h create mode 100644 bsps/sparc/include/bsp/gr1553rt.h create mode 100644 bsps/sparc/include/bsp/gr_701.h create mode 100644 bsps/sparc/include/bsp/gr_cpci_gr740.h create mode 100644 bsps/sparc/include/bsp/gr_leon4_n2x.h create mode 100644 bsps/sparc/include/bsp/gr_rasta_adcdac.h create mode 100644 bsps/sparc/include/bsp/gr_rasta_io.h create mode 100644 bsps/sparc/include/bsp/gr_rasta_spw_router.h create mode 100644 bsps/sparc/include/bsp/gr_rasta_tmtc.h create mode 100644 bsps/sparc/include/bsp/gr_tmtc_1553.h create mode 100644 bsps/sparc/include/bsp/gradcdac.h create mode 100644 bsps/sparc/include/bsp/grascs.h create mode 100644 bsps/sparc/include/bsp/grcan.h create mode 100644 bsps/sparc/include/bsp/grctm.h create mode 100644 bsps/sparc/include/bsp/greth.h create mode 100644 bsps/sparc/include/bsp/grgpio.h create mode 100644 bsps/sparc/include/bsp/griommu.h create mode 100644 bsps/sparc/include/bsp/grpci.h create mode 100644 bsps/sparc/include/bsp/grpci2.h create mode 100644 bsps/sparc/include/bsp/grpci2dma.h create mode 100644 bsps/sparc/include/bsp/grpwm.h create mode 100644 bsps/sparc/include/bsp/grslink.h create mode 100644 bsps/sparc/include/bsp/grspw.h create mode 100644 bsps/sparc/include/bsp/grspw_pkt.h create mode 100644 bsps/sparc/include/bsp/grspw_router.h create mode 100644 bsps/sparc/include/bsp/grtc.h create mode 100644 bsps/sparc/include/bsp/grtm.h create mode 100644 bsps/sparc/include/bsp/i2cmst.h create mode 100644 bsps/sparc/include/bsp/l2c.h create mode 100644 bsps/sparc/include/bsp/l4stat.h create mode 100644 bsps/sparc/include/bsp/mctrl.h create mode 100644 bsps/sparc/include/bsp/memscrub.h create mode 100644 bsps/sparc/include/bsp/network_interface_add.h create mode 100644 bsps/sparc/include/bsp/occan.h create mode 100644 bsps/sparc/include/bsp/pcif.h create mode 100644 bsps/sparc/include/bsp/satcan.h create mode 100644 bsps/sparc/include/bsp/spictrl.h create mode 100644 bsps/sparc/include/bsp/spwcuc.h create mode 100644 bsps/sparc/include/bsp/tlib.h create mode 100644 bsps/sparc/include/drvmgr/ambapp_bus.h create mode 100644 bsps/sparc/include/drvmgr/ambapp_bus_grlib.h create mode 100644 bsps/sparc/include/drvmgr/bspcommon.h create mode 100644 bsps/sparc/include/drvmgr/leon2_amba_bus.h create mode 100644 bsps/sparc/include/grlib.h create mode 100644 bsps/sparc/include/libcpu/access.h create mode 100644 bsps/sparc/leon2/headers.am create mode 100644 bsps/sparc/leon2/include/bsp.h create mode 100644 bsps/sparc/leon2/include/bsp/at697_pci.h create mode 100644 bsps/sparc/leon2/include/bsp/irq.h create mode 100644 bsps/sparc/leon2/include/leon.h create mode 100644 bsps/sparc/leon2/include/tm27.h create mode 100644 bsps/sparc/leon3/headers.am create mode 100644 bsps/sparc/leon3/include/amba.h create mode 100644 bsps/sparc/leon3/include/bsp.h create mode 100644 bsps/sparc/leon3/include/bsp/irq.h create mode 100644 bsps/sparc/leon3/include/bsp/watchdog.h create mode 100644 bsps/sparc/leon3/include/leon.h create mode 100644 bsps/sparc/leon3/include/tm27.h create mode 100644 bsps/sparc64/headers.am create mode 100644 bsps/sparc64/include/arch/arch.h create mode 100644 bsps/sparc64/include/arch/boot.h create mode 100644 bsps/sparc64/include/arch/mm/cache_spec.h create mode 100644 bsps/sparc64/include/arch/mm/frame.h create mode 100644 bsps/sparc64/include/arch/mm/mmu.h create mode 100644 bsps/sparc64/include/arch/mm/page.h create mode 100644 bsps/sparc64/include/arch/mm/sun4u/frame.h create mode 100644 bsps/sparc64/include/arch/mm/sun4u/mmu.h create mode 100644 bsps/sparc64/include/arch/mm/sun4u/page.h create mode 100644 bsps/sparc64/include/arch/mm/sun4u/tlb.h create mode 100644 bsps/sparc64/include/arch/mm/sun4u/tte.h create mode 100644 bsps/sparc64/include/arch/mm/tlb.h create mode 100644 bsps/sparc64/include/arch/mm/tte.h create mode 100644 bsps/sparc64/include/arch/regdef.h create mode 100644 bsps/sparc64/include/arch/stack.h create mode 100644 bsps/sparc64/include/arch/sun4u/arch.h create mode 100644 bsps/sparc64/include/asm.h create mode 100644 bsps/sparc64/include/boot/align.h create mode 100644 bsps/sparc64/include/boot/balloc.h create mode 100644 bsps/sparc64/include/boot/gentypes.h create mode 100644 bsps/sparc64/include/boot/main.h create mode 100644 bsps/sparc64/include/boot/ofw.h create mode 100644 bsps/sparc64/include/boot/ofw_tree.h create mode 100644 bsps/sparc64/include/boot/ofwarch.h create mode 100644 bsps/sparc64/include/boot/register.h create mode 100644 bsps/sparc64/include/boot/stack.h create mode 100644 bsps/sparc64/include/boot/types.h create mode 100644 bsps/sparc64/include/genarch/ofw/ofw_tree.h create mode 100644 bsps/sparc64/include/kernel/align.h create mode 100644 bsps/sparc64/include/traptable.h create mode 100644 bsps/sparc64/niagara/headers.am create mode 100644 bsps/sparc64/niagara/include/bsp.h create mode 100644 bsps/sparc64/niagara/include/tm27.h create mode 100644 bsps/sparc64/usiii/headers.am create mode 100644 bsps/sparc64/usiii/include/bsp.h create mode 100644 bsps/sparc64/usiii/include/tm27.h create mode 100644 bsps/v850/gdbv850sim/headers.am create mode 100644 bsps/v850/gdbv850sim/include/bsp.h create mode 100644 bsps/v850/gdbv850sim/include/bsp/syscall.h create mode 100644 bsps/v850/gdbv850sim/include/tm27.h (limited to 'bsps') diff --git a/bsps/arm/altera-cyclone-v/headers.am b/bsps/arm/altera-cyclone-v/headers.am new file mode 100644 index 0000000000..f63ee38854 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/headers.am @@ -0,0 +1,45 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/hwlib.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/irq.h + +include_bsp_socaldir = $(includedir)/bsp/socal +include_bsp_socal_HEADERS = +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h diff --git a/bsps/arm/altera-cyclone-v/include/bsp.h b/bsps/arm/altera-cyclone-v/include/bsp.h new file mode 100644 index 0000000000..4118823958 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H +#define LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000 + +#define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 ) + +#define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 ) + +#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 ) + +#define BSP_ARM_L2C_310_BASE 0xfffef000 + +#define BSP_ARM_L2C_310_ID 0x410000c9 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h new file mode 100644 index 0000000000..bca6f63e00 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h @@ -0,0 +1,1555 @@ +/* + * Altera - SoC UART Manager + */ + +/***************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ALT_16550_UART_H__ +#define __ALT_16550_UART_H__ + +#include "hwlib.h" +#include "alt_clock_manager.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup UART UART Driver API + * + * This module defines the Universal Asynchronous Receiver/Transmitter (UART) + * API for accessing and using the UART resources. The API allows for general + * control of a 16550 compatible UART controller. + * + * This implementation can control the following UARTs: + * * SoCFPGA On-board UARTs + * * Altera 16550 Compatible Soft IP UART + * + * The following reference materials were used in the design of this API: + * * Synopsys® DesignWare DW_apb_uart Databook v3.10a + * + * @{ + */ + +/*! + * \addtogroup UART_BASIC UART Basic + * + * This group of APIs provides basic access to the UART to initialize, + * uninitialize, read, write, and reset the UART. + * + * @{ + */ + +/*! + * This type definition enumerates the list of UARTs available on the system. + */ +typedef enum ALT_16550_DEVICE_e +{ + /*! + * This option selects UART0 in the SoC FPGA. + */ + ALT_16550_DEVICE_SOCFPGA_UART0 = 0, + + /*! + * This option selects UART1 in the SoC FPGA. + */ + ALT_16550_DEVICE_SOCFPGA_UART1 = 1, + + /*! + * This option selects an Altera 16550 Compatible soft IP UART. The memory + * location of the device must be provided as part of the initialization. + */ + ALT_16550_DEVICE_ALTERA_16550_UART = 0x100 +} +ALT_16550_DEVICE_t; + +/*! + * This structure is used to represent a handle to a specific UART on the + * system. The internal members are undocumented and should be not altered + * outside of this API. + */ +typedef struct ALT_16550_HANDLE_s +{ + ALT_16550_DEVICE_t device; + void * location; + alt_freq_t clock_freq; + uint32_t data; + uint32_t fcr; +} +ALT_16550_HANDLE_t; + +/*! + * Performs the initialization steps needed by the UART. This should be the + * first API call made when accessing a particular UART + * + * The default UART setting is 8 databits, no parity, 1 stopbit, and 57600 + * baud. + * + * For the SoCFPGA UARTs, The ALT_CLK_L4_SP clock needs to be setup before + * initialization. + * + * \param device + * The UART device identifier. + * + * \param location + * The memory of the location for the given UART. For SoCFPGA + * UARTs, this parameter is ignored. + * + * \param clock_freq + * The clock frequency of the serial clock for the given UART. + * For SoCFPGA UARTs, this paramter is ignored. + * + * \param handle + * [out] A pointer to a handle that will represent the UART. This + * handle should subsequently be used when calling other UART + * APIs. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device identifier is invalid. + * \retval ALT_E_BAD_CLK The required clock is not yet setup. + */ +ALT_STATUS_CODE alt_16550_init(ALT_16550_DEVICE_t device, + void * location, + alt_freq_t clock_freq, + ALT_16550_HANDLE_t * handle); + +/*! + * Performs the uninitialization steps for the UART. This should be the last + * API call made to cleanup the UART. + * + * After calling this function, the handle will need to be initialized again + * before being used by calling alt_16550_init(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_uninit(ALT_16550_HANDLE_t * handle); + +/*! + * Resets the UART to the default configuration. The UART will be reset and + * reinitialized. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_reset(ALT_16550_HANDLE_t * handle); + +/*! + * Starts the UART after all configuration has been completed. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Stops the UART. While UART configuration can be done while enabled, it is + * not recommended. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads a single character from the UART receiver buffer. This API should + * only be used when FIFOs are disabled. + * + * \param handle + * The UART device handle. + * + * \param item + * [out] Pointer to an output parameter that contains the in + * receiver buffer of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_read(ALT_16550_HANDLE_t * handle, + char * item); + +/*! + * Writes a single character to the UART transmitter buffer. This API should + * only be used when FIFOs are disabled. + * + * \param handle + * The UART device handle. + * + * \param item + * The character to write to the transmitter buffer of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_write(ALT_16550_HANDLE_t * handle, + char item); + +/*! + * @} + */ + +/*! + * \addtogroup UART_FIFO UART FIFO Interface + * + * This group of APIs provides access, configuration, and control of the UART + * FIFO. The FIFO allows the UART to buffer received data and data to be + * transmitted. + * + * @{ + */ + +/*! + * This type definition enumerates the receiver FIFO level conditions that + * will trigger the receiver FIFO to issue a receiver FIFO full event. + */ +typedef enum ALT_16550_FIFO_TRIGGER_RX_e +{ + /*! + * 1 or more character(s) in the receiver FIFO will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_RX_ANY = 0, + + /*! + * 25% or higher capacity usage in the receiver FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL = 1, + + /*! + * 50% or higher capacity usage in the receiver FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_HALF_FULL = 2, + + /*! + * 2 characters less than the receiver FIFO capacity will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL = 3 +} +ALT_16550_FIFO_TRIGGER_RX_t; + +/*! + * This type definition enumerates the transmitter FIFO level conditions that + * will trigger the transmitter FIFO to issue a transmitter FIFO empty event. + */ +typedef enum ALT_16550_FIFO_TRIGGER_TX_e +{ + /*! + * Transmitter FIFO being completely empty will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_TX_EMPTY = 0, + + /*! + * 2 or less character(s) in the transmitter FIFO will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY = 1, + + /*! + * 25% or less capacity usage in the transmitter FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL = 2, + + /*! + * 50% or less capacity usage in the transmitter FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_TX_HALF_FULL = 3 +} +ALT_16550_FIFO_TRIGGER_TX_t; + +/*! + * Enables FIFO on the UART. This will enable both the receiver FIFO and + * transmitter FIFO. Both FIFOs will be cleared. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Disables FIFOs on the UART. This will disable both the receiver FIFO and + * transmitter FIFO. Any data left in the FIFOs will be lost. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the given buffer from the receiver FIFO in the UART. + * + * The available characters in the FIFO can be determined by a few ways. Users + * can determine the number of items by calling alt_16550_fifo_level_get_rx(). + * + * Another way is by using the RX trigger and RX interrupt. First determine the + * RX FIFO size by calling alt_16550_fifo_size_get_rx(). Then set the desired + * trigger level by calling alt_16550_fifo_trigger_set_rx(). Calculate the + * triggering point by applying trigger description on the FIFO size. Enable RX + * interrupts by calling alt_16550_int_enable_rx(). When the RX interrupt fires + * due to the ALT_16550_INT_STATUS_RX_DATA condition, the calculated triggering + * point value can be used to determine the RX FIFO level. If the interrupt + * fires due to the ALT_16550_INT_STATUS_RX_TIMEOUT, the RX FIFO can be + * completely emptied by repeatedly polling the Line Status + * ALT_16550_LINE_STATUS_DR condition by calling alt_16550_line_status_get(). + * These steps are necessary if the UART does not implement FIFO level query + * functionality. As of 13.0sp1, this applies to the Altera 16550 Compatible + * Soft UART. + * + * Reading more data than that which is available can result in invalid data + * appearing like valid data. + * + * The FIFO must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param buffer + * [out] Pointer to a buffer where the specified count of + * characters from the receiver FIFO will be copied to. + * + * \param count + * The count of characters from the receiver FIFO to be copied. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_read(ALT_16550_HANDLE_t * handle, + char * buffer, + size_t count); + +/*! + * Writes the given buffer to the transmitter FIFO in the UART. + * + * The available space in the FIFO can be determined by a few ways. Users can + * determine the number of items by calculating the FIFO capacity minus the + * FIFO level. This can be done by calling alt_16550_fifo_size_get_tx() and + * alt_16550_fifo_level_get_tx() respectively. + * + * Another way is by using the TX trigger and TX interrupt. First determine the + * TX FIFO size by calling alt_16550_fifo_size_get_tx(). The set the desired + * trigger level by calling alt_16550_fifo_trigger_set_tx(). Calculate the + * triggering point by applying the trigger description on the FIFO size. + * Enable TX interrupts by calling alt_16550_int_enable_tx(). When the TX + * interrupt fires, calculate the empty entries in the FIFO by subtracting the + * TX FIFO size and the calculated value. These steps are necessary if the UART + * does not implement FIFO level query functionality. As of 13.0sp1, this + * applies to the Altera 16550 Compatible Soft UART. + * + * Writing more data that there is space can result in data lost due to + * overflowing. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param buffer + * Pointer to a buffer from where the specified count of + * characters will be copied to the transmitter FIFO. + * + * \param count + * The count of characters from the given buffer to be copied. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_write(ALT_16550_HANDLE_t * handle, + const char * buffer, + size_t count); + +/*! + * Clears the contents of the receiver FIFO. Any characters which were + * previously contained in that FIFO will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Clears the contents of the transmitter FIFO. Any characters which were + * previously contained in that FIFO will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Clears the contents of the receiver and transmitter FIFO. Any characters + * which were previously contained on those FIFOs will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_all(ALT_16550_HANDLE_t * handle); + +/*! + * Queries the size of the receiver FIFO. + * + * \param handle + * The UART device handle. + * + * \param size + * [out] Pointer to an output parameter that contains the size of + * the receiver FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_size_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * size); + +/*! + * Queries the size of the transmitter FIFO. + * + * \param handle + * The UART device handle. + * + * \param size + * [out] Pointer to an output parameter that contains the size of + * the transmitter FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_size_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * size); + +/*! + * Queries the current level of the receiver FIFO. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * For the Altera 16550 Compatible UART, it may not be possible to read the + * FIFO level and this function may always report 0. For more information on + * interacting with the FIFO in this situation, see documentation for + * alt_16550_fifo_read(). + * + * \param handle + * The UART device handle. + * + * \param level + * [out] Pointer to an output parameter that contains the level + * or number of characters in the receiver FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_level_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * level); + +/*! + * Queries the current level of the transmitter FIFO. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * For the Altera 16550 Compatible UART, it may not be possible to read the + * FIFO level and this function may always report 0. For more information on + * interacting with the FIFO in this situation, see documentation for + * alt_16550_fifo_write(). + * + * \param handle + * The UART device handle. + * + * \param level + * [out] Pointer to an output parameter that contains the level + * or number of characters in the transmitter FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_level_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * level); + +/*! + * Sets the receiver FIFO level which will trigger the receiver FIFO to issue + * receiver FIFO full event. For the list of available receiver FIFO trigger + * levels, see the documentation for ALT_16550_FIFO_TRIGGER_RX_t. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param trigger + * The level of the receiver FIFO which is needed to trigger a + * receiver FIFO full event. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_trigger_set_rx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_RX_t trigger); + +/*! + * Sets the transmitter FIFO level which will trigger the transmitter FIFO to + * transmitter FIFO empty event. For the list of available transmitter FIFO + * trigger levels, see the documentation for ALT_16550_FIFO_TRIGGER_TX_t. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param trigger + * The level of the transmitter FIFO which is needed to trigger a + * transmitter FIFO empty event. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_trigger_set_tx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_TX_t trigger); + +/*! + * @} + */ + +/*! + * \addtogroup UART_BAUD UART Baudrate Interface + * + * This group of APIs allows for the configuration of the UART's baudrate + * generation related functions. + * + * The UART baudrate is determined by dividing the ALT_CLK_L4_SP clock with + * the configured divisor. + * + * @{ + */ + +/*! + * This enumeration lists out the common baudrates used with modem and serial + * ports. Not every baudrate is available for the UART due to the limits of + * the serial clock frequency and divisor value. + */ +typedef enum ALT_16550_BAUDRATE_e +{ + ALT_16550_BAUDRATE_50 = 50, /*!< 50 bps baudrate. */ + ALT_16550_BAUDRATE_75 = 75, /*!< 75 bps baudrate. */ + ALT_16550_BAUDRATE_150 = 150, /*!< 150 bps baudrate. */ + ALT_16550_BAUDRATE_300 = 300, /*!< 300 bps baudrate. */ + ALT_16550_BAUDRATE_600 = 600, /*!< 600 bps baudrate. */ + ALT_16550_BAUDRATE_900 = 900, /*!< 900 bps baudrate. */ + ALT_16550_BAUDRATE_1200 = 1200, /*!< 1200 bps baudrate. */ + ALT_16550_BAUDRATE_1800 = 1800, /*!< 1800 bps baudrate. */ + ALT_16550_BAUDRATE_2400 = 2400, /*!< 2400 bps baudrate. */ + ALT_16550_BAUDRATE_3600 = 3600, /*!< 3600 bps baudrate. */ + ALT_16550_BAUDRATE_4800 = 4800, /*!< 4800 bps baudrate. */ + ALT_16550_BAUDRATE_7200 = 7200, /*!< 7200 bps baudrate. */ + ALT_16550_BAUDRATE_9600 = 9600, /*!< 9600 bps baudrate. */ + ALT_16550_BAUDRATE_14400 = 14400, /*!< 14400 bps baudrate. */ + ALT_16550_BAUDRATE_19200 = 19200, /*!< 19200 bps baudrate. */ + ALT_16550_BAUDRATE_28800 = 28800, /*!< 28800 bps baudrate. */ + ALT_16550_BAUDRATE_38400 = 38400, /*!< 38400 bps baudrate. */ + ALT_16550_BAUDRATE_57600 = 57600, /*!< 57600 bps baudrate. */ + ALT_16550_BAUDRATE_115200 = 115200 /*!< 115200 bps baudrate. */ +} +ALT_16550_BAUDRATE_t; + +/*! + * Gets the baudrate for the UART. + * + * This is done by calculating the baudrate from the divisor and the serial + * clock. The reported baudrate may not correspond exactly to the request + * baudrate. + * + * \param handle + * The UART device handle. + * + * \param baudrate + * [out] Pointer to an output paramter that contains the current + * baudrate of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_baudrate_get(ALT_16550_HANDLE_t * handle, + uint32_t * baudrate); + +/*! + * Sets the baudrate for the UART. This change will take effect when the UART + * moves from disabled to enabled. + * + * This is done by calculating the correct divisor using the request baudrate + * and the known serial clock. + * + * \param handle + * The UART device handle. + * + * \param baudrate + * The requested baudrate for the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + * \retval ALT_E_ARG_RANGE The given baudrate is not possible due to + * limitations of the baudrate divisor and/or + * serial clock. + */ +ALT_STATUS_CODE alt_16550_baudrate_set(ALT_16550_HANDLE_t * handle, + uint32_t baudrate); + +/*! + * Gets the baudrate divisor for the UART. + * + * The baudrate is determined by the following formula: + * * Baudrate = (serial clock frequency) / (16 * divisor) + * + * \param handle + * The UART device handle. + * + * \param divisor + * [out] Pointer to an output parameter that contains the current + * divisor used for baudrate generation. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_divisor_get(ALT_16550_HANDLE_t * handle, + uint32_t * divisor); + +/*! + * Sets the baudrate divisor for the UART. This change will take effect when + * the UART moves from disabled to enabled. + * + * The baudrate is determined by the following formula: + * * Baudrate = (serial clock frequency) / (16 * divisor) + * + * \param handle + * The UART device handle. + * + * \param divisor + * The specified divisor value to use for baudrate generation. + * Valid values are 1 - 65535. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART identifier is invalid or the + * specified divisor is not supported by the + * UART. + */ +ALT_STATUS_CODE alt_16550_divisor_set(ALT_16550_HANDLE_t * handle, + uint32_t divisor); + +/*! + * @} + */ + +/*! + * \addtogroup UART_INT UART Interrupt Interface + * + * This group of APIs provides access, configuration, and control of the + * UART interrupts. + * + * @{ + */ + +/*! + * This type definition enumerates the different interrupt conditions that can + * be generated by the UART controller. + * + * Interrupts are listed in highest to lowest priority order. + */ +typedef enum ALT_16550_INT_STATUS_e +{ + /*! + * This interrupt signals that a overrun, parity, or framing error + * occurred, or a break event occured. The interrupt is cleared by reading + * the line status by calling alt_16550_line_status_get() or by disabling + * line status interrupts by calling alt_16550_int_disable_line(). + */ + ALT_16550_INT_STATUS_LINE = 0x6, + + /*! + * This interrupt signals that some data is available to be read from the + * UART. The definition of some depends on whether FIFOs are enabled or + * not. + * + * If FIFOs are disabled, this interrupt signals that the receiver + * contains data. In this case, the interrupt is cleared by reading the + * data from the UART by calling alt_16550_read(). + * + * If FIFOs are enabled, this interrupt signals that the receiver FIFO + * level is above the receiver trigger level specified. In this case, the + * interrupt is cleared by reading a sufficiently large buffer from the + * receiver FIFO such that the FIFO is filled below the receiver trigger + * level specified by calling alt_16550_fifo_read() or by adjusting the + * receiver trigger level appropriately by calling + * alt_16550_fifo_trigger_set_rx(). + * + * In either case, this interrupt can also be cleared by disabling + * receiver interrupts by calling alt_16550_int_disable_rx(). + */ + ALT_16550_INT_STATUS_RX_DATA = 0x4, + + /*! + * This interrupt signals that data is available in the receiver FIFO and + * that there has been no activity with the receiver FIFO for the last 4 + * character frames. In essence, the receiver FIFO has temporarily settled + * thus it may be a good time to empty the receiver FIFO. This interrupt + * is only available if FIFOs are enabled. The interrupt is cleared by + * reading from the receiver FIFO by calling alt_16550_fifo_read() or by + * disabling receiver interrupts by calling alt_16550_int_disable_rx(). + */ + ALT_16550_INT_STATUS_RX_TIMEOUT = 0xC, + + /*! + * This interrupt signals that the transmitter is idling. The definition + * of idling depends on whether FIFOs are enabled or not. + * + * If FIFOs are disabled, this interrupt signals that the transmitter + * shift register is empty. In this case, the interrupt is cleared by + * writing data to the UART by calling alt_16550_write(). + * + * If FIFO are enabled, this interrupt signals that the transmitter FIFO + * level is below the transmitter trigger level specified. In this case, + * the interrupt is cleared by writing a sufficiently large buffer to the + * transmitter FIFO such that the FIFO is filled above the transmitter + * trigger level specified by calling alt_16550_fifo_write() or by + * adjusting the transmitter trigger level appropriately by calling + * alt_16550_fifo_trigger_set_tx(). + * + * In either case, this interrupt can also be cleared by disabling + * transmitter interrupts by calling alt_16550_int_disable_tx(). + */ + ALT_16550_INT_STATUS_TX_IDLE = 0x2, + + /*! + * Modem status interrupt pending. The interrupt is cleared by reading the + * modem status by calling alt_16550_modem_status_get() or by disabling + * modem status interrupts by calling alt_16550_int_disable_modem(). + */ + ALT_16550_INT_STATUS_MODEM = 0x0, + + /*! + * No interrupts pending. + */ + ALT_16550_INT_STATUS_NONE = 0x1 +} +ALT_16550_INT_STATUS_t; + +/*! + * Enables the receiver FIFO to generate interrupts. Enabling this interrupt + * allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_RX_DATA + * * ALT_16550_INT_STATUS_RX_TIMEOUT + * + * This interrupt is disabled by default. + * + * The FIFOs must also be enabled for this interrupt to actually be generated. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the receiver FIFO from generating interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the transmitter FIFO to generate interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_TX_IDLE + * + * This interrupt is disabled by default. + * + * The FIFOs must also be enabled for this interrupt to actually be generated. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the transmitter FIFO from generating interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the receiver to generate line status interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_LINE + * + * This interrupt is disabled by default. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_line(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the receiver from generating line status interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_line(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the UART to generate modem status interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_MODEM + * + * This interrupt is disabled by default. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_modem(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the UART from generate modem status interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_modem(ALT_16550_HANDLE_t * handle); + +/*! + * Disables all interrupts on the UART. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_all(ALT_16550_HANDLE_t * handle); + +/*! + * Queries the interrupt status of the UART. This returns the highest priority + * interrupt pending. The appropriate interrupts must be enabled for them be + * generated in the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * interrupt status of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_status_get(ALT_16550_HANDLE_t * handle, + ALT_16550_INT_STATUS_t * status); + +/*! + * @} + */ + +/*! + * \addtogroup UART_MODEM UART Modem Interface + * + * This group of APIs provides access, configuration, and control of the UART + * Modem interface. + * + * @{ + */ + +/*! + * This type definition enumerates the set of UART modem status conditions as + * register mask values. + */ +typedef enum ALT_16550_MODEM_STATUS_e +{ + /*! + * Data Carrier Detect. This status indicates that the carrier has been + * detected by the modem. It corresponds to an inverted dcd_n input. DCD + * is unasserted when dcd_n is logic 1 and asserted when dcd_n is logic 0. + */ + ALT_16550_MODEM_STATUS_DCD = 1 << 7, + + /*! + * Ring Indicator. This status indicates that the telephone ringing signal + * has been redeived by the modem. It corresponds to an inverted ri_n + * input. RI is unasserted when ri_n is logic 1 and asserted when ri_n is + * logic 0. + */ + ALT_16550_MODEM_STATUS_RI = 1 << 6, + + /*! + * Data Set Ready. This status indicates that the modem is ready to + * establish communications with the UART. It corresponds to an inverted + * dsr_n input. DSR is unasserted when dsr_n is logic 1 and asserted when + * dsr_n is logic 0. + */ + ALT_16550_MODEM_STATUS_DSR = 1 << 5, + + /*! + * Clear To Send. This status indicates the current state of the modem + * cts_n line. It corresponds to an inverted cts_n input. CTS is + * unasserted when cts_n is logic 1 and asserted when cts_n is logic 0. + */ + ALT_16550_MODEM_STATUS_CTS = 1 << 4, + + /*! + * Delta Data Carrier Detect. This status condition indicates that the + * Data Carrier Detect has changed since the last time the modem status + * was read. Reading the modem status clears this status. For more + * information about the Data Carrier Detect status, see + * ALT_16550_MODEM_STATUS_DCD. + */ + ALT_16550_MODEM_STATUS_DDCD = 1 << 3, + + /*! + * Trailing Edge of Ring Indicator. This status indicates that the Ring + * Indicator has changed from asserted to unasserted. Reading the modem + * status will clear this status. For more information about the Ring + * Indicator status, reference ALT_16550_MODEM_STATUS_RI. + */ + ALT_16550_MODEM_STATUS_TERI = 1 << 2, + + /*! + * Delta Data Set Ready. This status condition indicates that the Data Set + * Ready has changed since the last time the modem status was read. + * Reading the modem status will clear this status. For more information + * about the Data Set Ready status, see ALT_16550_MODEM_STATUS_DSR. + */ + ALT_16550_MODEM_STATUS_DDSR = 1 << 1, + + /*! + * Delta Clear To Send. This status condition indicates that the Clear To + * Send has changed since the last time the modem status was read. Reading + * the modem status will clear this status. For more information about the + * Clear To Send status, see ALT_16550_MODEM_STATUS_CTS. + */ + ALT_16550_MODEM_STATUS_DCTS = 1 << 0 +} +ALT_16550_MODEM_STATUS_t; + +/*! + * Enables automatic flow control in the UART modem. When in this mode, the + * rts_n is gated with the threshold trigger condition of the receiver FIFO. + * + * The Altera 16550 Compatible Soft IP UART may not have this option enabled. + * + * The FIFOs must be enabled for flow control to be used. + * + * The recommended bring up for flow control is as follows: + * * Enable automatic flow control by calling alt_16550_flowcontrol_enable(). + * This will allow both the receiver FIFO and user RTS to control the rts_n + * output. Because the user RTS is not enabled, the rts_n will be inactive + * high. + * * Enable RTS by calling alt_16550_modem_enable_rts(). This will give the + * receiver FIFO to have full control of the rts_n output. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_flowcontrol_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Disables automatic flow control in the UART modem. + * + * The recommended bring down for flow control is as follows: + * * Disable RTS by calling alt_16550_modem_disable_rts(). This will disable + * generation of the rts_n ouput. + * * Disable automatic flow control by calling + * alt_16550_flowcontrol_disable(). + * + * The receiver FIFO will still be active after these steps. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_flowcontrol_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Puts the UART in loopback mode. This is used for diagnostic and test + * purposes. + * + * The SoCFPGA UARTs does not support automatic flow control when in loopback + * mode. + * + * The Altera 16550 Compatible Soft IP UART implements this in 13.0sp1 and + * later. Setting this has no effect with 13.0. + * + * When in this mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are + * disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) + * are held inactive high externally and internally looped back to the inputs. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_loopback_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Takes the UART out of loopback mode. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_loopback_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the OUT1 output. OUT1 is inverted then driven out to out1_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_out1(ALT_16550_HANDLE_t * handle); + +/*! + * Unasserts the OUT1 output. OUT1 is inverted then driven out to out1_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_out1(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the OUT2 output. OUT2 is inverted then driven out to out2_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_out2(ALT_16550_HANDLE_t * handle); + +/*! + * Unasserts the OUT2 output. OUT2 is inverted then driven out to out2_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_out2(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the RTS (Request To Send) output. RTS is inverted then driven out + * to rts_n. RTS is used to inform the modem that the UART is ready to receive + * data. + * + * There are special considerations when the UART is in automatic flow control + * mode. See alt_16550_flowcontrol_enable() for more information. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_rts(ALT_16550_HANDLE_t * handle); + +/*! + * Deaserts the RTS (Request To Send) output. RTS is inverted then driven out + * to rts_n. + * + * There are special considerations when the UART is in automatic flow control + * mode. See alt_16550_flowcontrol_enable() for more information. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_rts(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the DTR (Data Terminal Ready) output. DTR is inverted then driven + * out to dtr_n. DTR is used to inform the modem that UART is ready to + * establish communications. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_dtr(ALT_16550_HANDLE_t * handle); + +/*! + * Deasserts the DTR (Data Terminal Ready) output. DTR is inverted then driven + * out to dtr_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_dtr(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the modem status from the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * modem status of the UART as a register mask. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status); + +/*! + * @} + */ + +/*! + * \addtogroup UART_LINE UART Line Interface + * + * This group of APIs provides access, configuration, and control of the UART + * Line interface. + * + * @{ + */ + +/*! + * This type definition enumerates the supported databits per frame. + */ +typedef enum ALT_16550_DATABITS_e +{ + /*! + * This option selects 5 databits per frame. + */ + ALT_16550_DATABITS_5 = 0, + + /*! + * This option selects 6 databits per frame. + */ + ALT_16550_DATABITS_6 = 1, + + /*! + * This option selects 7 databits per frame. + */ + ALT_16550_DATABITS_7 = 2, + + /*! + * This option selects 8 databits per frame. + */ + ALT_16550_DATABITS_8 = 3 +} +ALT_16550_DATABITS_t; + +/*! + * This type definition enumerates the supported stopbits per frame. + */ +typedef enum ALT_16550_STOPBITS_e +{ + /*! + * This options specifies 1 stopbit per frame. + */ + ALT_16550_STOPBITS_1 = 0, + + /*! + * This options specifies 2 stopbits per frame. If the frame is + * configured with 5 databits, 1.5 stopbits is used instead. + */ + ALT_16550_STOPBITS_2 = 1 +} +ALT_16550_STOPBITS_t; + +/*! + * This type definition enumerates the possible parity to use per frame. + */ +typedef enum ALT_16550_PARITY_e +{ + /*! + * This option disables the parity error detection bit in the data frame. + */ + ALT_16550_PARITY_DISABLE = 0, + + /*! + * This option enables the odd parity error detection bit in the data + * frame. + */ + ALT_16550_PARITY_ODD = 1, + + /*! + * This option enables the even parity error detection bit in the data + * frame. + */ + ALT_16550_PARITY_EVEN = 2 +} +ALT_16550_PARITY_t; + +/*! + * This type definition enumerates the set of UART line status conditions as + * register mask values. + */ +typedef enum ALT_16550_LINE_STATUS_e +{ + /*! + * Receiver FIFO Error. This status indicates that one or more parity + * error, framing error, or break indication exists in the receiver FIFO. + * It is only set when FIFO is enabled. This status cleared when line + * status is read, the character with the issue is at the top of the FIFO, + * and when no other issues exist in the FIFO. + */ + ALT_16550_LINE_STATUS_RFE = 1 << 7, + + /*! + * Transmitter EMpTy (Empty). This status indicates that transmitter shift + * register is empty. If FIFOs are enabled, the status is set when the + * transmitter FIFO is also empty. This status is cleared when the + * transmitter shift registers is loaded by writing to the UART + * transmitter buffer or transmitter FIFO if FIFOs are enabled. This is + * done by calling alt_16550_write() and alt_16550_fifo_write() + * respectively. + */ + ALT_16550_LINE_STATUS_TEMT = 1 << 6, + + /*! + * Transmitter Holding Register Empty. This status indicates that the + * transmitter will run out of data soon. The definition of soon depends + * on whether the FIFOs are enabled. + * + * If FIFOs are disabled, this status indicates that the transmitter will + * run out of data to send after the current transmit shift register + * completes. In this case, this status is cleared when the data is + * written to the UART. This can be done by calling alt_16550_write(). + * + * If FIFOs are enabled, this status indicates that the transmitter FIFO + * level is below the transmitter trigger level specified. In this case, + * this status is cleared by writing a sufficiently large buffer to the + * transmitter FIFO such that the FIFO is filled above the transmitter + * trigger level specified by calling alt_16550_fifo_write() or by + * adjusting the transmitter trigger level appropriately by calling + * alt_16550_fifo_trigger_set_tx(). + * + * \internal + * The implementation of the UART driver always ensures that IER[7] is + * set. This means that the UART always has Programmable THRE (Transmitter + * Holding Register Empty) Interrupt Mode Enable (PTIME) enabled. + * \endinternal + */ + ALT_16550_LINE_STATUS_THRE = 1 << 5, + + /*! + * Break Interrupt. This status indicates that a break interrupt sequence + * is detected in the incoming serial data. This happens when the the data + * is 0 for longer than a frame would normally be transmitted. The break + * interrupt status is cleared by reading the line status by calling + * alt_16550_line_status_get(). + * + * If FIFOs are enabled, this status will be set when the character with + * the break interrupt status is at the top of the receiver FIFO. + */ + ALT_16550_LINE_STATUS_BI = 1 << 4, + + /*! + * Framing Error. This status indicates that a framing error occurred in + * the receiver. This happens when the receiver detects a missing or + * incorrect number of stopbit(s). + * + * If FIFOs are enabled, this status will be set when the character with + * the framing error is at the top of the FIFO. When a framing error + * occurs, the UART attempts to resynchronize with the transmitting UART. + * This status is also set if break interrupt occurred. + */ + ALT_16550_LINE_STATUS_FE = 1 << 3, + + /*! + * Parity Error. This status indicates that a parity error occurred in the + * receiver. + * + * If FIFOs are enabled, this status will be set when the character with + * the parity error is at the top of the receiver FIFO. This status is + * also set if a break interrupt occurred. + */ + ALT_16550_LINE_STATUS_PE = 1 << 2, + + /*! + * Overrun Error. This status indicates that an overrun occurred in the + * receiver. + * + * If FIFOs are disabled, the arriving character will overwrite the + * existing character in the receiver. Any previously existing + * character(s) will be lost. + * + * If FIFOs are disabled, the arriving character will be discarded. The + * buffer will continue to contain the preexisting characters. + */ + ALT_16550_LINE_STATUS_OE = 1 << 1, + + /*! + * Data Ready. This status indicates that the receiver or receiver FIFO + * contains at least one character. + */ + ALT_16550_LINE_STATUS_DR = 1 << 0 +} +ALT_16550_LINE_STATUS_t; + +/*! + * Sets the configuration for a given character frame. + * + * \param handle + * The UART device handle. + * + * \param databits + * The number of databits for each character frame. + * + * \param parity + * The parity to use for each character frame. + * + * \param stopbits + * The number of stopbits for each character frame. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_config_set(ALT_16550_HANDLE_t * handle, + ALT_16550_DATABITS_t databits, + ALT_16550_PARITY_t parity, + ALT_16550_STOPBITS_t stopbits); + +/*! + * Starts transmitting a break condition by transmitting a logic 0 state + * longer than a frame would normally be transmitted. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_break_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Stops transmitting a break condition. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_break_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the line status from the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * line status of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_16550_UART_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h new file mode 100644 index 0000000000..781cc49aa3 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h @@ -0,0 +1,825 @@ +/*! \file + * Altera - SoC FPGA Address Space Manager + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_ADDRESS_SPACE_H__ +#define __ALT_ADDRESS_SPACE_H__ + +#include +#include "hwlib.h" +#include "socal/hps.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +// ARM Level 2 Cache Controller L2C-310 Register Interface + +// Address Filtering Start Register +// The Address Filtering Start Register is a read and write register. +// Bits Field Description +// :-------|:--------------------------|:----------------------------------------- +// [31:20] | address_filtering_start | Address filtering start address for +// | | bits [31:20] of the filtering address. +// [19:1] | Reserved | SBZ/RAZ +// [0] | address_filtering_enable | 0 - address filtering disabled +// | | 1 - address filtering enabled. + +// Address Filtering Start Register Address +#define L2_CACHE_ADDR_FILTERING_START_OFST 0xC00 +#define L2_CACHE_ADDR_FILTERING_START_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_START_OFST) +// Address Filtering Start Register - Start Value Mask +#define L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000 +// Address Filtering Start Register - Reset Start Address Value (1 MB) +#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000 +// Address Filtering Start Register - Enable Flag Mask +#define L2_CACHE_ADDR_FILTERING_ENABLE_MASK 0x00000001 +// Address Filtering Start Register - Reset Enable Flag Value (Enabled) +#define L2_CACHE_ADDR_FILTERING_ENABLE_RESET 0x1 + +// Address Filtering End Register +// The Address Filtering End Register is a read and write register. +// Bits Field Description +// :-------|:--------------------------|:----------------------------------------- +// [31:20] | address_filtering_end | Address filtering end address for bits +// | | [31:20] of the filtering address. +// [19:0] | Reserved | SBZ/RAZ + +// Address Filtering End Register Address +#define L2_CACHE_ADDR_FILTERING_END_OFST 0xC04 +#define L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST) +// Address Filtering End Register - End Value Mask +#define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000 +// Address Filtering End Register - Reset End Address Value (3 GiB) +#define L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000 + +#ifndef __ASSEMBLY__ + +/******************************************************************************/ +/*! \addtogroup ADDR_SPACE_MGR The Address Space Manager + * + * This module contains group APIs for managing the HPS address space. This + * module contains group APIs to manage: + * * Memory Map Control + * * Memory Coherence + * * Cache Managment + * * MMU Managment + * + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup ADDR_SPACE_MGR_REMAP Address Space Mapping Control + * + * This group API provides functions to map and remap selected address ranges + * into the accessible (visible) views of the MPU and non MPU address spaces. + * + * \b Caveats + * + * \b NOTE: Caution should be observed when remapping address 0 to different + * memory. The code performing the remapping operation should not be executing + * in the address range being remapped to different memory. + * + * For example, if address 0 is presently mapped to OCRAM and the code is + * preparing to remap address 0 to SDRAM, then the code must not be executing in + * the range 0 to 64 KB as this address space is about to be remapped to + * different memory. If the code performing the remap operation is executing + * from OCRAM then it needs to be executing from its permanently mapped OCRAM + * address range in upper memory (i.e. ALT_OCRAM_LB_ADDR to ALT_OCRAM_UB_ADDR). + * + * \b NOTE: The MPU address space view is controlled by two disparate hardware + * control interfaces: the L3 remap register and the L2 cache address filtering + * registers. To complicate matters, the L3 remap register is write-only which + * means not only that current remap register state cannot be read but also that + * a read-modify-write operation cannot be performed on the register. + * + * This should not present a problem in most use case scenarios except for the + * case where a current MPU address space mapping of 0 to SDRAM is being changed + * to to a mapping of 0 to Boot ROM or OCRAM. + * + * In this case, a two step process whereby the L3 remap register is first set + * to the new desired MPU address 0 mapping and then the L2 cache address + * filtering registers have their address ranges adjusted accordingly must be + * followed. An example follows: +\verbatim +// 1 MB reset default value for address filtering start +#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000 +uint32_t addr_filt_start; +uint32_t addr_filt_end; + +// Perform L3 remap register programming first by setting the desired new MPU +// address space 0 mapping. Assume OCRAM for the example. +alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM, ...); + +// Next, adjust the L2 cache address filtering range. Set the start address to +// the default reset value and retain the existing end address configuration. +alt_l2_addr_filter_cfg_get(&addr_filt_start, &addr_filt_end); +if (addr_filt_start != L2_CACHE_ADDR_FILTERING_START_RESET) +{ + alt_l2_addr_filter_cfg_set(L2_CACHE_ADDR_FILTERING_START_RESET, addr_filt_end); +} +\endverbatim + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the MPU address space attributes. + * + * The MPU address space consists of the ARM Cortex A9 processors and associated + * processor peripherals (cache, MMU). + */ +typedef enum ALT_ADDR_SPACE_MPU_ATTR_e +{ + ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM, /*!< Maps the Boot ROM to address + * 0x0 for the MPU L3 master. Note + * that the Boot ROM is also + * always mapped to address + * 0xfffd_0000 for the MPU L3 + * master independent of + * attribute. + */ + + ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address + * 0x0 for the MPU L3 master. Note + * that the On-chip RAM is also + * always mapped to address + * 0xffff_0000 for the MPU L3 + * master independent of this + * attribute. + */ +} ALT_ADDR_SPACE_MPU_ATTR_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the non-MPU address space attributes. + * + * The non-MPU address space consists of the non-MPU L3 masters including the + * DMA controllers (standalone and those built into peripherals), the F2H AXI + * Bridge, and the DAP. + */ +typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e +{ + ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM, /*!< Maps the SDRAM to address 0x0 + * for the non-MPU L3 masters. + */ + ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address + * 0x0 for the non-MPU L3 + * masters. Note that the On-chip + * RAM is also always mapped to + * address 0xffff_0000 for the + * non-MPU L3 masters independent + * of this attribute. + */ +} ALT_ADDR_SPACE_NONMPU_ATTR_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the HPS to FPGA bridge accessiblity + * attributes. + */ +typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e +{ + ALT_ADDR_SPACE_H2F_INACCESSIBLE, /*!< The H2F AXI Bridge is not + * visible to L3 masters. Accesses + * to the associated address range + * return an AXI decode error to + * the master. + */ + ALT_ADDR_SPACE_H2F_ACCESSIBLE /*!< The H2F AXI Bridge is visible + * to L3 masters. + */ +} ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the Lightweight HPS to FPGA bridge + * accessiblity attributes. + */ +typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e +{ + ALT_ADDR_SPACE_LWH2F_INACCESSIBLE, /*!< The LWH2F AXI Bridge is not + * visible to L3 masters. Accesses + * to the associated address range + * return an AXI decode error to + * the master. + */ + ALT_ADDR_SPACE_LWH2F_ACCESSIBLE /*!< The LWH2F AXI Bridge is visible + * to L3 masters. + */ +} ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t; + +/******************************************************************************/ +/*! + * Configures the mapped and accessible (visible) address ranges for the HPS + * MPU, non-MPU, and Bridge address spaces. + * + * \param mpu_attr + * The MPU address space configuration attributes. + * + * \param nonmpu_attr + * The non-MPU address space configuration attributes. + * + * \param h2f_attr + * The H2F Bridge attribute mapping and accessibility attributes. + * + * \param lwh2f_attr + * The Lightweight H2F Bridge attribute mapping and accessibility + * attributes. + * + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_INV_OPTION One or more invalid attribute options were + * specified. + */ +ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, + ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr, + ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_attr, + ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_attr); + +/******************************************************************************/ +/*! + * Maps SDRAM to address 0x0 for the MPU address space view. + * + * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest + * 64KB of the boot region are accessible because the size of the Boot ROM and + * on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MiB) to + * 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to + * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not + * accessible to the MPU unless address 0 is remapped to SDRAM after reset. + * + * This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access + * SDRAM. + * + * \internal + * The remap to address 0x0 is achieved by configuring the L2 cache Address + * Filtering Registers to redirect address 0x0 to \e sdram_end_addr to the SDRAM + * AXI (M1) master port by calling: + * + * alt_l2_addr_filter_cfg_set(0x0, ); + * + * See: ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical + * Reference Manual, Section 3.3.12 Address Filtering . + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup L2_ADDR_FLTR L2 Cache Address Filter + * + * The L2 cache address filter controls where physical addresses within certain + * ranges of the MPU address space are directed. + * + * The L2 cache has master port connections to the L3 interconnect and the SDRAM + * controller. A programmable address filter controls which portions of the + * 32-bit physical address space use each master. + * + * When l2 address filtering is configured and enabled, a physical address will + * be redirected to one master or the other based upon the address filter + * configuration. + * + * If \b address_filter_start <= \e physical_address < \b address_filter_end: + * * then redirect \e physical_address to AXI Master Port M1 (SDRAM controller) + * * else redirect \e physical_address to AXI Master Port M0 (L3 interconnect) + * + * See: ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical + * Reference Manual, Section 3.3.12 Address Filtering for more information. + * @{ + */ + +/******************************************************************************/ +/*! + * Get the L2 cache address filtering configuration settings. + * + * \param addr_filt_start + * [out] An output parameter variable for the address filtering + * start address for the range of physical addresses redirected to + * the SDRAM AXI master port. The value returned is always a 1 MiB + * aligned address. + * + * \param addr_filt_end + * [out] An output parameter variable for the address filtering + * end address for the range of physical addresses redirected to + * the SDRAM AXI master port. The value returned is always a 1 MiB + * aligned address. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG An bad argument was passed. Either \e addr_filt_start + * or \e addr_filt_end or both are invalid addresses. + */ +ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start, + uint32_t* addr_filt_end); + +/******************************************************************************/ +/*! + * Set the L2 cache address filtering configuration settings. + * + * Address filtering start and end values must be 1 MiB aligned. + * + * \param addr_filt_start + * The address filtering start address for the range of physical + * addresses redirected to the SDRAM AXI master port. Only bits + * [31:20] of the address are valid. Any bits outside the range + * [31:20] are invalid and will cause an error status to be + * returned. + * + * \param addr_filt_end + * The address filtering end address for the range of physical + * addresses redirected to the SDRAM AXI master port. Only bits + * [31:20] of the address are valid. Any bits outside the range + * [31:20] are invalid and will cause an error status to be + * returned. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more address arguments do not satisfy the argument + * constraints. + */ +ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, + uint32_t addr_filt_end); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ADDR_SPACE_MGR_MEM_COHERENCE ACP Memory Coherence and ID Mapping + * + * This API provides management of the ACP ID Mapper that enables data coherent + * access to the MPU address space by external masters. The set of external + * masters include L3 master peripherals and FPGA soft IP. + * + * The Accelerator Coherency Port (ACP) allows peripherals - including FPGA + * based soft IP - to maintain data coherency with the Cortex-A9 MPCore + * processors and the Snoop Control Unit (SCU). + * + * The ACP supports up to six masters. However, soft IP implemented in the FPGA + * fabric can have a larger number of masters that need to access the ACP. The + * ACP ID Mapper expands the number of masters able to access the ACP. The ACP + * ID Mapper is situated between the interconnect and the ACP of the MPU + * subsystem. It has the following characteristics: + * * Support for up to six concurrent ID mappings. + * * 1 GiB coherent window into 4 GiB MPU address space + * * Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU) + * and L2 cache. + * + * The function of the ACP ID Mapper is to map 12-bit Advanced Microcontroller + * Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) IDs (input + * identifiers) from the Level 3 (L3) interconnect to 3-bit AXI IDs (output + * identifiers) required by the ACP slave port. + * + * The ACP ID Mapper supports the two ID mapping modes: + * * Dynamic Mapping - In this mode an input ID is automatically mapped to an + * available output ID. The dynamic mode is more flexible because the hardware + * handles the mapping. The hardware mapping allows an output ID to be used + * for more than one input ID. Output IDs are assigned to input IDs on a + * first-come, first-served basis. + * * Fixed Mapping - In this mode there is a one-to-one mapping from input IDs + * to output IDs. + * + * Out of the total of eight ACP output ID values, only six are available to the + * ACP ID Mapper for remapping. The first two output IDs (0 and 1) are + * dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the + * last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6 + * support fixed and dynamic modes of operation while output ID 7 supports + * dynamic mode only. + * + * The following table summarizes the usage of the 3-bit ouput ID values by the + * ACP ID Mapper and their settings at reset. + * + * Output ID | Usage | Reset State + * :-----------|:--------------------------------------------------|:------------ + * 0 | Reserved for Cortex-A9 cores. | - + * 1 | Reserved for Cortex-A9 cores. | - + * 2 | Assigned to Debug Access Port (DAP) input ID at | Fixed + * : | reset. After reset, can be reconfigured to either | DAP Master + * : | fixed or dynamic. |: + * 3 | Configurable fixed or dynamic mode. | Dynamic + * 4 | Configurable fixed or dynamic mode. | Dynamic + * 5 | Configurable fixed or dynamic mode. | Dynamic + * 6 | Configurable fixed or dynamic mode. | Dynamic + * 7 | Dynamic mode only. | Dynamic + * + * Where Output ID is the ACP ID Mapper output value that goes to the ACP. + * + * Additionally, for masters unable to drive the AXI user sideband signals of + * incoming transactions, the ACP ID Mapper allows control of the AXI user + * sideband signal values. Not all masters drive these signals, so the ACP ID + * Mapper makes it possible to drive the 5-bit user sideband signal with either + * a default value (in dynamic mode) or specific values (in fixed mode). + * + * The ACP ID Mapper can also control which 1 GiB coherent window into memory is + * accessed by masters of the L3 interconnect. Each fixed mapping can be + * assigned a different user sideband signal and memory window to allow specific + * settings for different masters. All dynamic mappings share a common user + * sideband signal and memory window setting. One important exception, however, + * is that the ACP ID mapper always allows user sideband signals from the + * FPGA-to-HPS bridge to pass through to the ACP regardless of the configured + * user sideband value associated with the ID. + * + * The ACP ID Mapper has a 1 GiB address window into the MPU address space, which + * is by default a view into the bottom 1 GiB of SDRAM. The ACP ID Mapper allows + * transactions to be routed to different 1 GiB-sized memory views, called pages, + * in both dynamic and fixed modes. + * + * See: Chapter 6: Cortex-A9 Microprocessor Unit Subsystem in + * Volume 3: Hard Processor System Technical Reference Manual of the + * Arria V or Cyclone V Device Handbook for a complete discussion of + * the operation and restrictions on the ACP and the ACP ID Mapper. + * + * @{ + */ + +/******************************************************************************/ +/*! + * \name External Master ID Macros + * + * These macros define the HPS external master identifiers that are 12-bit input + * IDs to the ACP ID Mapper. Some of the masters have a range of identifier + * values assigned to them and are distinguished by taking a (var)\ + * argument. + * @{ + */ + +/*! Bit mask for the relevant 12 bits of an external master ID */ +#define ALT_ACP_ID_MAP_MASTER_ID_MASK 0xfff + +/*! Master ID for L2M0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_L2M0(var) (0x00000002 | (0x000007f8 & (var))) +/*! Master ID for DMA */ +#define ALT_ACP_ID_MAP_MASTER_ID_DMA(var) (0x00000001 | (0x00000078 & (var))) +/*! Master ID for EMAC0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_EMAC0(var) (0x00000801 | (0x00000878 & (var))) +/*! Master ID for EMAC1 */ +#define ALT_ACP_ID_MAP_MASTER_ID_EMAC1(var) (0x00000802 | (0x00000878 & (var))) +/*! Master ID for USB0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_USB0 0x00000803 +/*! Master ID for USB1 */ +#define ALT_ACP_ID_MAP_MASTER_ID_USB1 0x00000806 +/*! Master ID for NAND controller */ +#define ALT_ACP_ID_MAP_MASTER_ID_NAND(var) (0x00000804 | (0x00000ff8 & (var))) +/*! Master ID for Embedded Trace Router (ETR) */ +#define ALT_ACP_ID_MAP_MASTER_ID_TMC 0x00000800 +/*! Master ID for Debug Access Port (DAP) */ +#define ALT_ACP_ID_MAP_MASTER_ID_DAP 0x00000004 +/*! Master ID for SD/MMC controller */ +#define ALT_ACP_ID_MAP_MASTER_ID_SDMMC 0x00000805 +/*! Master ID for FPGA to HPS (F2H) bridge - conduit for soft IP masters in FPGA fabric */ +#define ALT_ACP_ID_MAP_MASTER_ID_F2H(var) (0x00000000 | (0x000007f8 & (var))) +/*! @} */ + +/******************************************************************************/ +/*! + * This type defines the enumerations 3-bit output ids to ACP ID mapper. + */ +typedef enum ALT_ACP_ID_OUTPUT_ID_e +{ + ALT_ACP_ID_OUT_FIXED_ID_2 = 2, /*!< Assigned to the input ID of the DAP at reset. + * After reset, can be either fixed or dynamic, + * programmed by software. + */ + ALT_ACP_ID_OUT_DYNAM_ID_3 = 3, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_4 = 4, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_5 = 5, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_6 = 6, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_7 = 7 /*!< Dynamic mapping only */ +} ALT_ACP_ID_OUTPUT_ID_t; + +/*! + * This type defines the enumerations used to specify the 1 GiB page view of the + * MPU address space used by an ACP ID mapping configuration. + */ +typedef enum ALT_ACP_ID_MAP_PAGE_e +{ + ALT_ACP_ID_MAP_PAGE_0 = 0, /*!< Page 0 - MPU address range 0x00000000 - 0x3FFFFFFF */ + ALT_ACP_ID_MAP_PAGE_1 = 1, /*!< Page 1 - MPU address range 0x40000000 - 0x7FFFFFFF */ + ALT_ACP_ID_MAP_PAGE_2 = 2, /*!< Page 2 - MPU address range 0x80000000 - 0xBFFFFFFF */ + ALT_ACP_ID_MAP_PAGE_3 = 3 /*!< Page 3 - MPU address range 0xC0000000 - 0xFFFFFFFF */ +} ALT_ACP_ID_MAP_PAGE_t; + +/******************************************************************************/ +/*! + * Configure a fixed ACP ID mapping for read transactions originating from + * external masters identified by \e input_id. The \e input_id value is + * translated to the specified 3-bit \e output_id required by the ACP slave + * port. + * + * \param input_id + * The 12 bit external master ID originating read transactions + * targeted for ID translation. Valid argument range must be 0 <= + * \e output_id <= 4095. + * + * \param output_id + * The 3-bit output ID value the ACP ID Mapper translates read + * transactions identified by \e input_id to. This is the value + * propogated to the ACP slave port. Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the ID tranlation mapping. + * + * \param aruser + * The 5-bit AXI ARUSER read user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e input_id, and/or \e output_id + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e page argument is invalid. + */ +ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser); + +/******************************************************************************/ +/*! + * Configure a fixed ACP ID mapping for write transactions originating from + * external masters identified by \e input_id. The \e input_id value is + * translated to the specified 3-bit \e output_id required by the ACP slave + * port. + * + * \param input_id + * The 12 bit external master ID originating write transactions + * targeted for ID translation. Valid argument range must be 0 <= + * \e output_id <= 4095. + * + * \param output_id + * The 3-bit output ID value the ACP ID Mapper translates write + * transactions identified by \e input_id to. This is the value + * propogated to the ACP slave port. Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the ID tranlation mapping. + * + * \param awuser + * The 5-bit AXI AWUSER write user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e awuser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e input_id, and/or \e output_id + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e page argument is invalid. + */ +ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser); + +/******************************************************************************/ +/*! + * Configure the designated 3-bit output ID as an available identifier resource + * for use by the dynamic ID mapping function of the ACP ID Mapper for read + * transactions. The \e output_id value is available for dynamic assignment to + * external master read transaction IDs that do not have an explicit fixed ID + * mapping. + * + * \param output_id + * The 3-bit output ID value designated as an available ID for use + * by the dynamic mapping function of the ACP ID Mapper. The \e + * ouput_id value is used exclusively for dynamic ID mapping until + * reconfigured as a fixed ID mapping by a call to + * alt_acp_id_map_fixed_read_set(). Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id); + +/******************************************************************************/ +/*! + * Configure the designated 3-bit output ID as an available identifier resource + * for use by the dynamic ID mapping function of the ACP ID Mapper for write + * transactions. The \e output_id value is available for dynamic assignment to + * external master write transaction IDs that do not have an explicit fixed ID + * mapping. + * + * \param output_id + * The 3-bit output ID value designated as an available ID for use + * by the dynamic mapping function of the ACP ID Mapper. The \e + * ouput_id value is used exclusively for dynamic ID mapping until + * reconfigured as a fixed ID mapping by a call to + * alt_acp_id_map_fixed_write_set(). Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id); + +/******************************************************************************/ +/*! + * Configure the page and user read sideband signal options that are applied to + * all read transactions that have their input IDs dynamically mapped. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the dynamic ID tranlation mapping. + * + * \param aruser + * The 5-bit AXI ARUSER read user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e page and/or \e aruser + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master + * identifier. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser); + +/******************************************************************************/ +/*! + * Configure the page and user write sideband signal options that are applied to + * all write transactions that have their input IDs dynamically mapped. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the dynamic ID tranlation mapping. + * + * \param awuser + * The 5-bit AXI AWUSER write user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e page and/or \e awuser + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master + * identifier. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser); + +/******************************************************************************/ +/*! + * Return the current read transaction mapping configuration used by the ACP ID + * Mapper for the specified output ID. + * + * If \e output_id is configured as a fixed mapping then \b true is returned in + * the \e fixed output parameter and the translation mapping options configured + * for that \e output_id are returned in the other output parameters. + * + * If \e output_id is configured as a dynamic mapping then \b false is returned + * in the \e fixed output parameter and the translation mapping options + * configured for all dynamically remapped output IDs are returned in the other + * output parameters. + * + * \param output_id + * The output ID to return the mapping configuration for. 0 <= \e + * output_id <= 7. + * + * \param fixed + * [out] Set to \b true if the specified \e output_id is a fixed ID + * mapping configuration. Set to \b false if the mapping + * configuration is dynamic. + * + * \param input_id + * [out] The input ID of the external master that a fixed ID + * mapping is applied to for the \e output_id. If \e fixed is \b + * false then this output parameter is set to 0 and its value + * should be considered as not applicable. + * + * \param page + * [out] The MPU address space page view used by the mapping + * configuration. + * + * \param aruser + * [out] The 5-bit AXI ARUSER read user sideband signal value used + * by the mapping configuration when masters are unable to drive + * the AXI user sideband signals. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e + * output_id argument violates its range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id, + bool* fixed, + uint32_t* input_id, + ALT_ACP_ID_MAP_PAGE_t* page, + uint32_t* aruser); + +/******************************************************************************/ +/*! + * Return the current write transaction mapping configuration used by the ACP ID + * Mapper for the specified output ID. + * + * If \e output_id is configured as a fixed mapping then \b true is returned in + * the \e fixed output parameter and the translation mapping options configured + * for that \e output_id are returned in the other output parameters. + * + * If \e output_id is configured as a dynamic mapping then \b false is returned + * in the \e fixed output parameter and the translation mapping options + * configured for all dynamically remapped output IDs are returned in the other + * output parameters. + * + * \param output_id + * The output ID to return the mapping configuration for. 0 <= \e + * output_id <= 7. + * + * \param fixed + * [out] Set to \b true if the specified \e output_id is a fixed ID + * mapping configuration. Set to \b false if the mapping + * configuration is dynamic. + * + * \param input_id + * [out] The input ID of the external master that a fixed ID + * mapping is applied to for the \e output_id. If \e fixed is \b + * false then this output parameter is set to 0 and its value + * should be considered as not applicable. + * + * \param page + * [out] The MPU address space page view used by the mapping + * configuration. + * + * \param awuser + * [out] The 5-bit AXI AWUSER write user sideband signal value used + * by the mapping configuration when masters are unable to drive + * the AXI user sideband signals. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e + * output_id argument violates its range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id, + bool* fixed, + uint32_t* input_id, + ALT_ACP_ID_MAP_PAGE_t* page, + uint32_t* awuser); + +/*! @} */ + +/*! @} */ + +#endif /* __ASSEMBLY__ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_ADDRESS_SPACE_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h new file mode 100644 index 0000000000..8d088ab744 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h @@ -0,0 +1,964 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ALT_CACHE_H__ +#define __ALT_CACHE_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup CACHE_MGR Cache Management API + * + * This module defines the cache management API for enabling and disabling L1 + * data cache, L1 instruction cache, L1 dynamic branch prediction caches, L1 + * TLB cache, and L2 cache in the SoC. As well, many it allows users to perform + * cache maintenance operations on these caches. This includes the following + * operations: + * * Invalidate: Marks the cache line as being invalid, freeing up the space + * to cache other data. All APIs which enable caches invalidates the memory + * before being enabling the cache. + * * Clean: If the cache line is dirty, it synchronizes the cache line data + * with the upper level memory system and marks that line as clean. All APIs + * which disable caches cleans the memory before disabling the cache. + * * Purge: A term used in this API as a short form for clean and invalidate. + * This operation cleans and invalidates a cache line in that order, as a + * single command to the cache controller. + * + * The following reference materials were used in the design of this API: + * * ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition + * * Cortex™-A9 Technical Reference Manual + * * Cortex™-A9 MPCore Technical Reference Manual + * * CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference + * Manual + * + * @{ + */ + +/*! + * \addtogroup CACHE_SYS System Level Cache Management API + * + * This API group provides cache maintenance operations which affects multiple + * cache levels. + * + * The enable and disable functions enables and disables all caches in the + * system respectively. For caches shared by the CPU core(s), particularly the + * L2 cache, once that cache is enabled or disabled it will not be invalidated + * or cleaned again respectively. This allows the safe system-wide enable and + * disable to be used in single-core and multi-core scenarios. + * + * For cache maintenance operations, this API implements the procedures + * outlined in the L2C-310 Technical Reference Manual, section 3.3.10, + * subsection "System cache maintenance considerations". This allows for a + * convenient way to invalidate, clean, or clean and invalidate cache data from + * the L1 to L2 to L3 while avoiding any potential race conditions in + * mutli-core or multi-master scenarios. It assumes that the L1 and L2 cache is + * set in "non-exclusive" mode. This means a segment of data can reside in both + * the L1 and L2 simultaneously. This is the default mode for caches in the + * system. + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * @{ + */ + +/*! + * Enables support for a non-flat virtual memory. A flat virtual memory is + * where every virtual address matches exactly to the physical address, making + * the virtual to physical translation trivial. Adding support for non-flat + * adds some overhead for the VA to PA translation and error detection. + * + * To enable non-flat virtual memory support, defined + * ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY=1 in your Makefile when compiling + * HWLibs. + */ +#ifndef ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY +#define ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY (0) +#endif + +/*! + * This is the system wide cache line size, given in bytes. + */ +#define ALT_CACHE_LINE_SIZE 32 + +/*! + * Enables all caches and features which improve reliability and speed on all + * cache controllers visible to the current CPU core. This includes parity + * error detection. Cache controllers visible to multiple CPU cores, for + * example the L2, will first be checked to be disabled before being enabled. + * All necessary cache maintenance operations will be done automatically. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_system_enable(void); + +/*! + * Disables all cache controllers visible to the current CPU core. Cache + * controllers visible to multiple CPU cores, for example the L2, will first + * be checked to be enabled before being disabled. All necessary cache + * maintenance operations will be done automatically. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_system_disable(void); + +/*! + * Invalidates the specified contents of all cache levels visible to the + * current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L2 invalidate address(es) + * -# L2 cache sync + * -# L1 invalidate address(es) + * -# DSB instruction + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_invalidate(void * vaddress, size_t length); + +/*! + * Cleans the specified contents of all cache levels visible to the current + * CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L1 clean address(es) + * -# DSB instruction + * -# L2 clean address(es) + * -# L2 cache sync + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_clean(void * vaddress, size_t length); + +/*! + * Cleans and invalidates the specified contents of all cache levels visible + * to the current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L1 clean address(es) + * -# DSB instruction + * -# L2 clean and invalidate address(es) + * -# L2 cache sync + * -# L1 invalidate address(es) + * -# DSB instruction + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_purge(void * vaddress, size_t length); + +/*! + * @} + */ + +/*! + * \addtogroup CACHE_L1 L1 Cache Management API + * + * This API group provides functions to interact with various components of the + * L1 cache on the SoCFPGA. This includes the following cache components: + * * Instruction Cache + * * Data Cache + * * Parity error detection + * * Dynamic branch prediction + * * Data prefetching + * + * The API within this group only affects the L1 cache on the current CPU. To + * interact the L1 cache on another CPU, the API must be called from that other + * CPU. + * + * With respect to bring-up, the L1 and L2 cache controller setups are fully + * independent. The L2 can be setup at any time, before or after the L1 is setup. + * \internal + * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". + * \endinternal + * + * @{ + */ + +/*! + * Enables all L1 caches and features on the current CPU core. This includes + * the instruction cache, data cache, parity error detection, branch target + * address cache, global history buffer, and data prefetching. All necessary + * maintenance tasks will be taken care of. + * + * This function should not be mixed with other L1 cache related functions + * which enable or disable caches individually. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_enable_all(void); + +/*! + * Disables all L1 caches and features on the current CPU core. This includes + * the instruction cache, data cache, parity error detection, branch target + * address cache, global history buffer, and data prefetching. All necessary + * maintenance tasks will be taken care of. + * + * This function should not be mixed with other L1 cache related functions + * which enable or disable caches individually. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_disable_all(void); + +/*! + * Enables the L1 instruction cache on the current CPU core. If the cache is + * already enabled, nothing is done. Otherwise the instruction cache is first + * invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_enable(void); + +/*! + * Disables the L1 instruction cache on the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_disable(void); + +/*! + * Returns \b true when the L1 instruction cache is enabled and \b false when + * it is disabled on the current CPU core. + * + * \retval true The L1 instruction cache is enabled. + * \retval false The L1 instruction cache is disabled. + */ +bool alt_cache_l1_instruction_is_enabled(void); + +/*! + * Invalidates the contents of the L1 instruction cache on the current CPU + * core. + * + * Normally this is done automatically as part of + * alt_cache_l1_instruction_enable(), but in certain circumstances it may be + * necessary to invalidate it manually. An example of this situation is when + * the address space is remapped and the processor executes instructions from + * the new memory area. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_invalidate(void); + +/*! + * Enables the L1 data cache on the current CPU core. + * + * If the cache is already enabled nothing is done. Otherwise the data cache is + * first invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_enable(void); + +/*! + * Disables the L1 data cache on the current CPU core. + * + * If the cache is already disabled nothing is done. Otherwise the data cache + * is first cleaned before being disabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_disable(void); + +/*! + * Returns \b true when the L1 data cache is enabled and \b false when it is + * disabled on the current CPU core. + * + * \retval true The L1 data cache is enabled. + * \retval false The L1 data cache is disabled. + */ +bool alt_cache_l1_data_is_enabled(void); + +/*! + * Invalidates the specified contents of the L1 data cache on the current CPU + * core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param vaddress + * The virtual address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_invalidate(void * vaddress, size_t length); + +/*! + * Invalidates the entire contents of the L1 data cache on the current CPU + * core. + * + * Normally this is done automatically as part of alt_cache_l1_data_enable(), + * but in certain circumstances it may be necessary to invalidate it manually. + * An example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_invalidate_all(void); + +/*! + * Cleans the specified contents of the L1 data cache on the current CPU core + * for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param vaddress + * The virtual address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_clean(void * vaddress, size_t length); + +/*! + * Cleans the entire L1 data cache for the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_clean_all(void); + +/*! + * Cleans and invalidates the specified contents of the L1 data cache on the + * current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * Normally this is done automatically as part of alt_cache_l1_data_disable(), + * but in certain circumstances it may be necessary to purged it manually. + * An example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + * + * \param vaddress + * The virtual address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_purge(void * vaddress, size_t length); + +/*! + * Cleans and invalidates the entire L1 data cache for the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_purge_all(void); + +/*! + * Enables the parity error detection feature in the L1 caches on the current + * CPU core. + * + * Ideally parity should be enabled before any L1 caches are enabled. If the + * instruction, data, and / or dynamic branch predictor caches are already + * enabled, they will first be cleaned (if needed) and disabled before parity + * is enabled in hardware. Afterwards, the affected caches will be invalidated + * and enabled. + * + * Parity and TLB interaction deserves special attention. The TLB is considered + * to be a L1 cache but is enabled when the MMU, which is grouped in another + * API, is enabled. Due to the system-wide influence of the MMU, it cannot be + * disabled and enabled with impunity as the other L1 caches, which are + * designed to operate as transparently as possible. Thus parity error + * detection must be enabled before the L1 TLB cache, and by extension the MMU, + * is enabled. + * + * For a parity error to be reported, the appropriate CPU PARITYFAIL interrupt + * for the current CPU core must be enabled using the interrupt controller API. + * For CPU0, ALT_INT_INTERRUPT_CPU0_PARITYFAIL is asserted if any parity error + * is detected while the other PARITYFAIL interrupts are for parity errors in a + * specific memory. Refer to the interrupt controller API for more details + * about programming the interrupt controller. + * + * In the event of a parity error is detected, the appropriate CPU parity + * interrupt will be raised. CPU parity interrupts are all edge triggered and + * are cleared by acknowledging them in the interrupt controller API. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_parity_enable(void); + +/*! + * Disables parity error detection in the L1 caches. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_parity_disable(void); + +/*! + * Returns \b true when parity error detection is enabled and \b false when it + * is disabled on the current CPU core. + * + * \retval true Parity error detection for L1 caches is + * enabled. + * \retval false Parity error detection for L1 caches is + * disabled. + */ +bool alt_cache_l1_parity_is_enabled(void); + +/*! + * Enables the dynamic branch predictor features on the current CPU core. + * + * This operation enables both the Branch Target Address Cache (BTAC) and + * the Global History Buffer (GHB). Affected caches are automatically + * invalidated before use. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_enable(void); + +/*! + * Disables the dynamic branch predictor features on the current CPU core. + * + * This operation disables both the Branch Target Address Cache (BTAC) and + * the Global History Buffer (GHB). + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_disable(void); + +/*! + * Returns \b true when both the dynamic predictor features are enabled and + * \b false when they are disabled on the current CPU core. + * + * \retval true The L1 branch predictor caches are all enabled. + * \retval false Some or all L1 branch predictor caches are + * disabled. + */ +bool alt_cache_l1_branch_is_enabled(void); + +/*! + * Invalidates the dynamic branch predictor feature caches on the current CPU + * core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_invalidate(void); + +/*! + * Enables the L1 cache data prefetch feature on the current CPU core. + * + * This allows data to be prefetched into the data cache before it is to be + * used. For example in a loop the current iteration may want to preload the + * data which will be used in the next teration. This is done by using the PLD + * instructions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_prefetch_enable(void); + +/*! + * Disables the L1 cache data prefetch feature on the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_prefetch_disable(void); + +/*! + * Returns \b true if the L1 cache data prefetch feature is enabled and + * \b false if it is disabled on the current CPU core. + * + * \retval true The L1 data cache prefetch feature is enabled. + * \retval false The L1 data cache prefetch feature is disabled. + */ +bool alt_cache_l1_prefetch_is_enabled(void); + +/*! + * @} + */ + +/*! + * \addtogroup CACHE_L2 L2 Cache Management API + * + * This API group provides functions to interact with various features of the + * L2 cache on the SoCFPGA. This includes the following features: + * * L2 cache + * * Parity error detection + * * Data prefetching + * * Interrupt Management + * + * \internal + * Additional features that may be implemented in the future: + * * Lockdown + * * Event counter + * \endinternal + * + * The API within this group affects the L2 cache which is visible to all CPUs + * on the system. + * + * With respect to bring-up, the L1 and L2 cache controller setups are fully + * independent. The L2 can be setup at any time, before or after the L1 is setup. + * \internal + * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". + * \endinternal + * + * @{ + */ + +/*! + * Initializes the L2 cache controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_cache_l2_init(void); + +/*! + * Uninitializes the L2 cache controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_cache_l2_uninit(void); + +/*! + * Enables the L2 cache features for data and instruction prefetching. + * + * Prefetching can be enabled or disabled while the L2 cache is enabled. + * \internal + * Source: Use the Prefetch Control Register. + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_prefetch_enable(void); + +/*! + * Disables the L2 cache features for data and instruction prefetching. + * + * Prefetching can be enabled or disabled while the L2 cache is enabled. + * \internal + * Source: Use the Prefetch Control Register. + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_prefetch_disable(void); + +/*! + * Returns \b true if either L2 cache data or instruction prefetch features are + * enabled and \b false if no prefetching features are enabled. + * + * \retval true The L2 data and instruction prefetch features + * are enabled. + * \retval false Some L2 data and instruction prefetch features + * are disabled. + */ +bool alt_cache_l2_prefetch_is_enabled(void); + +/*! + * Enables parity error detection in the L2 cache. + * + * Ideally parity should be enabled before the L2 cache is enabled. If the + * cache is already enabled, it will first be cleaned and disabled before + * parity is enabled in hardware. Afterwards, the cache will be invalidated and + * enabled. + * + * For a parity error to be reported, the ALT_CACHE_L2_INTERRUPT_PARRD and / or + * ALT_CACHE_L2_INTERRUPT_PARRT interrupt condition(s) must be enabled. This is + * done by calling alt_cache_l2_int_enable(). As well, the L2 cache interrupt + * must be enabled using the interrupt controller API. Refer to the interrupt + * controller API for more details about programming the interrupt controller. + * + * In the event of a parity error is detected, the appropriate L2 cache parity + * interrupt will be raised. To clear the parity interrupt(s), the appropriate + * L2 cache parity interrupt must be cleared by calling + * alt_cache_l2_int_status_clear(). + * + * For ECC support, refer to the ECC related API documentation for more + * information. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_parity_enable(void); + +/*! + * Disables parity error detection in the L2 cache. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_parity_disable(void); + +/*! + * Returns \b true when parity error detection is enabled and \b false when it + * is disabled. + * + * \retval true The L2 cache parity error detection feature is + * enabled. + * \retval false The L2 cache parity error detection feature is + * disabled. + */ +bool alt_cache_l2_parity_is_enabled(void); + +/*! + * Enables the L2 cache. + * + * If the L2 cache is already enabled, nothing is done. Otherwise the entire + * contents of the cache is first invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_enable(void); + +/*! + * Disables the L2 cache. + * + * If the L2 cache is already disabled, nothing is done. Otherwise the entire + * contents of the cache is first cleaned before being disabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_disable(void); + +/*! + * Returns \b true when the L2 cache is enabled and \b false when it is + * disabled. + * + * \retval true The L2 cache is enabled. + * \retval false The L2 cache is disabled. + */ +bool alt_cache_l2_is_enabled(void); + +/*! + * Flushes the L2 cache controller hardware buffers. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_sync(void); + +/*! + * Invalidates the specified contents of the L2 cache for the given memory + * segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_invalidate(void * paddress, size_t length); + +/*! + * Invalidates th entire contents of the L2 cache. + * + * Normally this is done automatically as part of alt_cache_l2_enable(), but + * in certain circumstances it may be necessary to invalidate it manually. An + * example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_invalidate_all(void); + +/*! + * Cleans the specified contents of the L2 cache for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_clean(void * paddress, size_t length); + +/*! + * Cleans the entire L2 cache. All L2 cache controller interrupts will be + * temporarily disabled while the clean operation is in progress and restored + * once the it is finished. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_clean_all(void); + +/*! + * Cleans and invalidates the specified contents of the L2 cache for the + * given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l2_purge(void * paddress, size_t length); + +/*! + * Cleans and invalidates the entire L2 cache. All L2 cache controller + * interrupts will be temporarily disabled while the clean and invalidate + * operation is in progress and restored once the it is finished. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_purge_all(void); + +/*! + * This type definition enumerates all the interrupt conditions that can be + * generated by the L2 cache controller as register mask values. + */ +enum ALT_CACHE_L2_INTERRUPT_e +{ + /*! Decode error received on the master ports from L3. */ + ALT_CACHE_L2_INTERRUPT_DECERR = 1 << 8, + + /*! Slave error received on the master ports from L3. */ + ALT_CACHE_L2_INTERRUPT_SLVERR = 1 << 7, + + /*! Error on the L2 data RAM read. */ + ALT_CACHE_L2_INTERRUPT_ERRRD = 1 << 6, + + /*! Error on the L2 tag RAM read. */ + ALT_CACHE_L2_INTERRUPT_ERRRT = 1 << 5, + + /*! Error on the L2 data RAM write. */ + ALT_CACHE_L2_INTERRUPT_ERRWD = 1 << 4, + + /*! Error on the L2 tag RAM write. */ + ALT_CACHE_L2_INTERRUPT_ERRWT = 1 << 3, + + /*! Parity error on the L2 data RAM read. */ + ALT_CACHE_L2_INTERRUPT_PARRD = 1 << 2, + + /*! Parity error on the L2 tag RAM read. */ + ALT_CACHE_L2_INTERRUPT_PARRT = 1 << 1, + + /*! Event counter overflow or increment. */ + ALT_CACHE_L2_INTERRUPT_ECNTR = 1 << 0 +}; +typedef enum ALT_CACHE_L2_INTERRUPT_e ALT_CACHE_L2_INTERRUPT_t; + +/*! + * Enables the L2 cache controller interrupts for the specified set of + * condition(s). + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_enable(uint32_t interrupt); + +/*! + * Disables the L2 cache controller interrupts for the specified set of + * condition(s). + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_disable(uint32_t interrupt); + +/*! + * Gets the condition(s) causing the L2 cache controller to interrupt as a + * register mask. + * + * \returns A register mask of the currently asserted and enabled + * conditions resulting in an interrupt being generated. + */ +uint32_t alt_cache_l2_int_status_get(void); + +/*! + * Clears the specified conditon(s) causing the L2 cache controller to + * interrupt as a mask. Condition(s) specified which are not causing an + * interrupt or condition(s) specified which are not enabled are ignored. + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_status_clear(uint32_t interrupt); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_CACHE_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h new file mode 100644 index 0000000000..a43608e9f3 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h @@ -0,0 +1,114 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*! + * \file + * + * Contains the definition of an opaque data structure that contains raw + * configuration information for a clock group. + */ + +#ifndef __ALT_CLK_GRP_H__ +#define __ALT_CLK_GRP_H__ + +#include "hwlib.h" +#include "socal/alt_clkmgr.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * This type definition enumerates the clock groups + */ +typedef enum ALT_CLK_GRP_e +{ + ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */ + + ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */ + + ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */ + +} ALT_CLK_GRP_t; + +/*! + * This type definition defines an opaque data structure for holding the + * configuration settings for a complete clock group. + */ +typedef struct ALT_CLK_GROUP_RAW_CFG_s +{ + uint32_t verid; /*!< SoC FPGA version identifier. This field + * encapsulates the silicon identifier and + * version information associated with this + * clock group configuration. It is used to + * assert that this clock group configuration + * is valid for this device. */ + + uint32_t siliid2; /*!< Reserved register - reserved for future + * device IDs or capability flags. */ + + ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */ + + /*! + * This union holds the register values for configuration of the set of + * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator + * identifies the valid clock group union data member. + */ + union ALT_CLK_GROUP_RAW_CFG_u + { + /*! Clock group configuration for Main PLL group. */ + union + { + ALT_CLKMGR_MAINPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */ + } mainpllgrp; + + /*! Clock group configuration for Peripheral PLL group. */ + union + { + ALT_CLKMGR_PERPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */ + } perpllgrp; + + /*! Clock group configuration for SDRAM PLL group. */ + union + { + ALT_CLKMGR_SDRPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */ + } sdrpllgrp; + + } clkgrp; +} ALT_CLK_GROUP_RAW_CFG_t; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_CLK_GRP_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h new file mode 100644 index 0000000000..d6d96544f7 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h @@ -0,0 +1,1434 @@ +/*! \file + * Contains definitions for the Altera Hardware Libraries Clock Manager + * Application Programming Interface + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_CLK_MGR_H__ +#define __ALT_CLK_MGR_H__ + +#include "hwlib.h" +#include "alt_clock_group.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! \addtogroup CLK_MGR The Clock Manager API + * + * This module defines the Clock Manager API for accessing, configuring, and + * controlling the HPS clock resources. + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition is an opaque type definition for clock frequency values + * in Hz. + */ +typedef uint32_t alt_freq_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the names of the clock and PLL resources + * managed by the Clock Manager. + */ +typedef enum ALT_CLK_e +{ + /* Clock Input Pins */ + ALT_CLK_IN_PIN_OSC1, + /*!< \b OSC_CLK_1_HPS + * External oscillator input: + * * Input Pin + * * Clock source to Main PLL + * * Clock source to SDRAM PLL + * and Peripheral PLL if selected via + * register write + * * Clock source for clock in safe mode + */ + + ALT_CLK_IN_PIN_OSC2, + /*!< \b OSC_CLK_2_HPS + * External Oscillator input: + * * Input Pin + * * Optional clock source to SDRAM PLL + * and Peripheral PLL if selected + * * Typically used for Ethernet + * reference clock + */ + + + /* FPGA Clock Sources External to HPS */ + ALT_CLK_F2H_PERIPH_REF, + /*2C 0 TX */ + ALT_DMA_PERIPH_I2C0_RX = 9, /*!< I2C 0 RX */ + ALT_DMA_PERIPH_I2C1_TX = 10, /*!< I2C 1 TX */ + ALT_DMA_PERIPH_I2C1_RX = 11, /*!< I2C 1 RX */ + ALT_DMA_PERIPH_I2C2_TX = 12, /*!< I2C 2 TX */ + ALT_DMA_PERIPH_I2C2_RX = 13, /*!< I2C 2 RX */ + ALT_DMA_PERIPH_I2C3_TX = 14, /*!< I2C 3 TX */ + ALT_DMA_PERIPH_I2C3_RX = 15, /*!< I2C 3 RX */ + ALT_DMA_PERIPH_SPI0_MASTER_TX = 16, /*!< SPI 0 Master TX */ + ALT_DMA_PERIPH_SPI0_MASTER_RX = 17, /*!< SPI 0 Master RX */ + ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18, /*!< SPI 0 Slave TX */ + ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19, /*!< SPI 0 Slave RX */ + ALT_DMA_PERIPH_SPI1_MASTER_TX = 20, /*!< SPI 1 Master TX */ + ALT_DMA_PERIPH_SPI1_MASTER_RX = 21, /*!< SPI 1 Master RX */ + ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22, /*!< SPI 1 Slave TX */ + ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23, /*!< SPI 1 Slave RX */ + ALT_DMA_PERIPH_QSPI_FLASH_TX = 24, /*!< QSPI Flash TX */ + ALT_DMA_PERIPH_QSPI_FLASH_RX = 25, /*!< QSPI Flash RX */ + ALT_DMA_PERIPH_STM = 26, /*!< System Trace Macrocell */ + ALT_DMA_PERIPH_RESERVED = 27, /*!< Reserved */ + ALT_DMA_PERIPH_UART0_TX = 28, /*!< UART 0 TX */ + ALT_DMA_PERIPH_UART0_RX = 29, /*!< UART 0 RX */ + ALT_DMA_PERIPH_UART1_TX = 30, /*!< UART 1 TX */ + ALT_DMA_PERIPH_UART1_RX = 31 /*!< UART 1 RX */ +} +ALT_DMA_PERIPH_t; + +/*! + * This type enumerates the DMA security state options available. + */ +typedef enum ALT_DMA_SECURITY_e +{ + ALT_DMA_SECURITY_DEFAULT = 0, /*!< Use the default security value (e.g. reset default) */ + ALT_DMA_SECURITY_SECURE = 1, /*!< Secure */ + ALT_DMA_SECURITY_NONSECURE = 2 /*!< Non-secure */ +} +ALT_DMA_SECURITY_t; + +/*! + * This type definition enumerates the DMA event-interrupt resources. + */ +typedef enum ALT_DMA_EVENT_e +{ + ALT_DMA_EVENT_0 = 0, /*!< DMA Event 0 */ + ALT_DMA_EVENT_1 = 1, /*!< DMA Event 1 */ + ALT_DMA_EVENT_2 = 2, /*!< DMA Event 2 */ + ALT_DMA_EVENT_3 = 3, /*!< DMA Event 3 */ + ALT_DMA_EVENT_4 = 4, /*!< DMA Event 4 */ + ALT_DMA_EVENT_5 = 5, /*!< DMA Event 5 */ + ALT_DMA_EVENT_6 = 6, /*!< DMA Event 6 */ + ALT_DMA_EVENT_7 = 7, /*!< DMA Event 7 */ + ALT_DMA_EVENT_ABORT = 8 /*!< DMA Abort Event */ +} +ALT_DMA_EVENT_t; + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_COMMON_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h new file mode 100644 index 0000000000..5fa876f237 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h @@ -0,0 +1,951 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ALT_DMA_PROGRAM_H__ +#define __ALT_DMA_PROGRAM_H__ + +#include "hwlib.h" +#include "alt_dma_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup ALT_DMA_PRG DMA Controller Programming API + * + * This API provides functions for dynamically defining and assembling microcode + * programs for execution on the DMA controller. + * + * The microcode program assembly API provides users with the ability to develop + * highly optimized and tailored algorithms for data transfer between SoC FPGA + * IP blocks and/or system memory. + * + * The same microcode program assembly facilities are also used to implement the + * functions found in the HWLIB Common DMA Operations functional API. + * + * An ALT_DMA_PROGRAM_t structure is used to contain and assemble a DMA + * microcode program. The storage for an ALT_DMA_PROGRAM_t stucture is allocated + * from used specified system memory. Once a microcode program has been + * assembled in a ALT_DMA_PROGRAM_t it may be excecuted on a designated DMA + * channel thread. The microcode program may be rerun on any DMA channel thread + * whenever required as long as the integrity of the ALT_DMA_PROGRAM_t + * containing the program is maintained. + * + * @{ + */ + +/*! + * This preprocessor declares the DMA channel thread microcode instruction + * cache line width in bytes. It is recommended that the program buffers be + * sized to a multiple of the cache line size. This will allow for the most + * efficient microcode speed and space utilization. + */ +#define ALT_DMA_PROGRAM_CACHE_LINE_SIZE (32) + +/*! + * This preprocessor declares the DMA channel thread microcode instruction + * cache line count. Thus the total size of the cache is the cache line size + * multipled by the cache line count. Programs larger than the cache size risk + * having a cache miss while executing. + */ +#define ALT_DMA_PROGRAM_CACHE_LINE_COUNT (16) + +/*! + * This preprocessor definition determines the size of the program buffer + * within the ALT_DMA_PROGRAM_t structure. This size should provide adequate + * size for most DMA microcode programs. If calls within this API are + * reporting out of memory response codes, consider increasing the provisioned + * program buffersize. + * + * To specify another DMA microcode program buffer size, redefine the macro + * below by defining ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE to another size in + * your Makefile. It is recommended that the size be a multiple of the + * microcode engine cache line size. See ALT_DMA_PROGRAM_CACHE_LINE_SIZE for + * more information. The largest supported buffer size is 65536 bytes. + */ +#ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE +#define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT) +#endif + +/*! + * This type defines the structure used to assemble and contain a microcode + * program which can be executed by the DMA controller. The internal members + * are undocumented and should not be altered outside of this API. + */ +typedef struct ALT_DMA_PROGRAM_s +{ + uint32_t flag; + + uint16_t buffer_start; + uint16_t code_size; + + uint16_t loop0; + uint16_t loop1; + + uint16_t sar; + uint16_t dar; + + /* + * Add a little extra space so that regardless of where this structure + * sits in memory, a suitable start address can be aligned to the cache + * line stride while providing the requested buffer space. + */ + uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE + + ALT_DMA_PROGRAM_CACHE_LINE_SIZE]; +} +ALT_DMA_PROGRAM_t; + +/*! + * This type definition enumerates the DMA controller register names for use in + * microcode program definition. + */ +typedef enum ALT_DMA_PROGRAM_REG_e +{ + /*! Source Address Register */ + ALT_DMA_PROGRAM_REG_SAR = 0x0, + + /*! Destination Address Register */ + ALT_DMA_PROGRAM_REG_DAR = 0x2, + + /*! Channel Control Register */ + ALT_DMA_PROGRAM_REG_CCR = 0x1 +} +ALT_DMA_PROGRAM_REG_t; + +/*! + * This type definition enumerates the instruction modifier options available + * for use with selected DMA microcode instructions. + * + * The enumerations values are context dependent upon the instruction being + * modified. + * + * For the DMALD[S|B], DMALDP\, DMAST[S|B], and + * DMASTP\ microcode instructions, the enumeration + * ALT_DMA_PROGRAM_INST_MOD_SINGLE specifies the S option modifier + * while the enumeration ALT_DMA_PROGRAM_INST_MOD_BURST specifies the B + * option modifier. The enumeration ALT_DMA_PROGRAM_INST_MOD_NONE specifies + * that no modifier is present for instructions where use of [S|B] is + * optional. + * + * For the DMAWFP microcode instruction, the enumerations + * ALT_DMA_PROGRAM_INST_MOD_SINGLE, ALT_DMA_PROGRAM_INST_MOD_BURST, or + * ALT_DMA_PROGRAM_INST_MOD_PERIPH each specify one of the corresponding + * options \. + */ +typedef enum ALT_DMA_PROGRAM_INST_MOD_e +{ + /*! + * This DMA instruction modifier specifies that no special modifier is + * added to the instruction. + */ + ALT_DMA_PROGRAM_INST_MOD_NONE, + + /*! + * Depending on the DMA microcode instruction modified, this modifier + * specifies S case for a [S|B] or a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_SINGLE, + + /*! + * Depending on the DMA microcode instruction modified, this modifier + * specifies B case for a [S|B] or a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_BURST, + + /*! + * This DMA instruction modifier specifies a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_PERIPH +} +ALT_DMA_PROGRAM_INST_MOD_t; + +/*! + * This function initializes a system memory buffer for use as a DMA microcode + * program buffer. This should be the first API call made on the program + * buffer type. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function verifies that the DMA microcode program buffer is no longer + * in use and performs any needed uninitialization steps. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function clears the existing DMA microcode program in the given + * program buffer. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function validate that the given DMA microcode program buffer contains + * a well formed program. If caches are enabled, the program buffer contents + * will be cleaned to RAM. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The given program is well formed. + * \retval ALT_E_ERROR The given program is not well formed. + * \retval ALT_E_TMO The cache operation timed out. + */ +ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function reports the number bytes incremented for the register + * specified. The purpose is to determine the progress of an ongoing DMA + * transfer. + * + * It is implemented by calculating the difference of the programmed SAR or DAR + * with the current channel SAR or DAR register value. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \param channel + * The channel that the program is running on. + * + * \param reg + * Register to change the value for. Valid for only + * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. + * + * \param current + * The current snapshot value of the register read from the DMA + * channel. + * + * \param progress + * [out] A pointer to a memory location that will be used to store + * the number of bytes transfered. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + * \retval ALT_E_BAD_ARG The specified channel is invalid, the specified + * register is invalid, or the DMAMOV for the + * specified register has not yet been assembled + * in the current program buffer. + */ +ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, + uint32_t current, uint32_t * progress); + +/*! + * This function updates a pre-existing DMAMOV value affecting the SAR or DAR + * registers. This allows for pre-assembled programs that can be used on + * different source and destination addresses. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \param reg + * Register to change the value for. Valid for only + * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. + * + * \param val + * The value to update to. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + * \retval ALT_E_BAD_ARG The specified register is invalid or the DMAMOV + * for the specified register has not yet been + * assembled in the current program buffer. + */ +ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, uint32_t val); + +/*! + */ + +/*! + * Assembles a DMAADDH (Add Halfword) instruction into the microcode program + * buffer. This instruction uses 3 bytes of buffer space. + * + * \param pgm + * The DMA program buffer to contain the assembled instruction. + * + * \param addr_reg + * The channel address register (ALT_DMA_PROGRAM_REG_DAR or + * ALT_DMA_PROGRAM_REG_SAR) to add the value to. + * + * \param val + * The 16-bit unsigned value to add to the channel address + * register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAADDH , <16-bit immediate> +ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); + +/*! + * Assembles a DMAADNH (Add Negative Halfword) instruction into the microcode + * program buffer. This instruction uses 3 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param addr_reg + * The channel address register (ALT_DMA_PROGRAM_REG_DAR or + * ALT_DMA_PROGRAM_REG_SAR) to add the value to. + * + * \param val + * The 16-bit unsigned value to add to the channel address + * register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAADNH , <16-bit immediate> +ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); + +/*! + * Assembles a DMAEND (End) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAEND +ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAFLUSHP (Flush Peripheral) instruction into the microcode + * program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param periph + * The peripheral to flush. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid peripheral specified. + */ +// Assembler Syntax: DMAFLUSHP +ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMAGO (Go) instruction into the microcode program buffer. This + * instruction uses 6 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param channel + * The stopped channel to act upon. + * + * \param val + * The value to write to the channel program counter register. + * + * \param sec + * The security state for the operation. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel or security specified. + */ +// Assembler Syntax: DMAGO , <32-bit_immediate> [, ns] +ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_CHANNEL_t channel, uint32_t val, + ALT_DMA_SECURITY_t sec); + +/*! + * Assembles a DMAKILL (Kill) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAKILL +ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMALD (Load) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. + */ +// Assembler Syntax: DMALD[S|B] +ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMALDP (Load and notify Peripheral) instruction into the + * microcode program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \param periph + * The peripheral to notify. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral + * specified. + */ +// Assembler Syntax: DMALDP +ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMALP (Loop) instruction into the microcode program buffer. + * This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param iterations + * The number of iterations to run for. Valid values are 1 - 256. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid iterations specified. + * \retval ALT_E_BAD_OPERATION All loop registers are in use. + */ +// Assembler Syntax: DMALP [|] +ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm, + uint32_t iterations); + +/*! + * Assembles a DMALPEND (Loop End) instruction into the microcode program + * buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the loop terminator. Only + * ALT_DMA_PROGRAM_INST_MOD_NONE, ALT_DMA_PROGRAM_INST_MOD_SINGLE + * and ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. + * \retval ALT_E_ARG_RANGE Loop size is too large to be supported. + * \retval ALT_E_BAD_OPERATION A valid DMALP or DMALPFE was not added to + * the program buffer before adding this + * DMALPEND instruction. + */ +// Assembler Syntax: DMALPEND[S|B] +ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMALPFE (Loop Forever) instruction into the microcode program + * buffer. No instruction is added to the buffer but a previous DMALPEND to + * create an infinite loop. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMALPFE +ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAMOV (Move) instruction into the microcode program buffer. + * This instruction uses 6 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param chan_reg + * The channel non-looping register (ALT_DMA_PROGRAM_REG_SAR, + * ALT_DMA_PROGRAM_REG_DAR or ALT_DMA_PROGRAM_REG_CCR) to copy + * the value to. + * + * \param val + * The value to write to the specified register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAMOV , <32-bit_immediate> +ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val); + +/*! + * Assembles a DMANOP (No Operation) instruction into the microcode program + * buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMANOP +ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMARMB (Read Memory Barrier) instruction into the microcode + * program buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMARMB +ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMASEV (Send Event) instruction into the microcode program + * buffer. This instruction uses 2 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param evt + * The event to send. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid event specified. + */ +// Assembler Syntax: DMASEV +ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt); + +/*! + * Assembles a DMAST (Store) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAST[S|B] +ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMASTP (Store and notify Peripheral) instruction into the + * microcode program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \param periph + * The peripheral to notify. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral + * specified. + */ +// Assembler Syntax: DMASTP +ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMASTZ (Store Zero) instruction into the microcode program + * buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMASTZ +ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAWFE (Wait For Event) instruction into the microcode program + * buffer. This instruction uses 2 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param evt + * The event to wait for. + * + * \param invalid + * If invalid is set to true, the instruction will be configured + * to invalidate the instruction cache for the current DMA + * thread. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid event specified. + */ +// Assembler Syntax: DMAWFE [, invalid] +ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt, bool invalid); + +/*! + * Assembles a DMAWFP (Wait for Peripheral) instruction into the microcode + * program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param periph + * The peripheral to wait on. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE, + * ALT_DMA_PROGRAM_INST_MOD_BURST, or + * ALT_DMA_PROGRAM_INST_MOD_PERIPH are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid peripheral or instruction modifier + * specified. + */ +// Assembler Syntax: DMAWFP , +ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMAWMB (Write Memory Barrier) instruction into the microcode + * program buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAWMB +ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm); + +/*! + * \addtogroup DMA_CCR Support for DMAMOV CCR + * + * The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the + * dynamic microcode programming of the assembler directive: +\verbatim + +DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA] + [SP] [SC] + [DB<1-16>] [DS<8|16|32|64|128>] [DA] + [DP] [DC] + [ES<8|16|32|64|128>] + +\endverbatim +* with a DMAMOV instruction (see: alt_dma_program_DMAMOV()). +* +* For example the assembler directive: +\verbatim +DMAMOV CCR SB1 SS32 DB1 DS32 +\endverbatim +* would be dynamically programmed with the following API call: +\verbatim +alt_dma_program_DMAMOV( pgm, + ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES8 + ) + ); +\endverbatim +* +* Each CCR option category should be specified regardless of whether it +* specifies a custom value or the normal default value (i.e. an +* ALT_DMA_CCR_OPT_*_DEFAULT. +* +* @{ +*/ + +/* + * Source Address {Fixed,Incrementing} + */ +/*! Source Address Fixed address burst. */ +#define ALT_DMA_CCR_OPT_SAF (0 << 0) +/*! Source Address Incrementing address burst. */ +#define ALT_DMA_CCR_OPT_SAI (1 << 0) +/*! Source Address Default value. */ +#define ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI + +/* + * Source burst Size (in bits) + */ +/*! Source burst Size of 8 bits. */ +#define ALT_DMA_CCR_OPT_SS8 (0 << 1) +/*! Source burst Size of 16 bits. */ +#define ALT_DMA_CCR_OPT_SS16 (1 << 1) +/*! Source burst Size of 32 bits. */ +#define ALT_DMA_CCR_OPT_SS32 (2 << 1) +/*! Source burst Size of 64 bits. */ +#define ALT_DMA_CCR_OPT_SS64 (3 << 1) +/*! Source burst Size of 128 bits. */ +#define ALT_DMA_CCR_OPT_SS128 (4 << 1) +/*! Source burst Size default bits. */ +#define ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8 + +/* + * Source burst Length (in transfer(s)) + */ +/*! Source Burst length of 1 transfer. */ +#define ALT_DMA_CCR_OPT_SB1 (0x0 << 4) +/*! Source Burst length of 2 transfers. */ +#define ALT_DMA_CCR_OPT_SB2 (0x1 << 4) +/*! Source Burst length of 3 transfers. */ +#define ALT_DMA_CCR_OPT_SB3 (0x2 << 4) +/*! Source Burst length of 4 transfers. */ +#define ALT_DMA_CCR_OPT_SB4 (0x3 << 4) +/*! Source Burst length of 5 transfers. */ +#define ALT_DMA_CCR_OPT_SB5 (0x4 << 4) +/*! Source Burst length of 6 transfers. */ +#define ALT_DMA_CCR_OPT_SB6 (0x5 << 4) +/*! Source Burst length of 7 transfers. */ +#define ALT_DMA_CCR_OPT_SB7 (0x6 << 4) +/*! Source Burst length of 8 transfers. */ +#define ALT_DMA_CCR_OPT_SB8 (0x7 << 4) +/*! Source Burst length of 9 transfers. */ +#define ALT_DMA_CCR_OPT_SB9 (0x8 << 4) +/*! Source Burst length of 10 transfers. */ +#define ALT_DMA_CCR_OPT_SB10 (0x9 << 4) +/*! Source Burst length of 11 transfers. */ +#define ALT_DMA_CCR_OPT_SB11 (0xa << 4) +/*! Source Burst length of 12 transfers. */ +#define ALT_DMA_CCR_OPT_SB12 (0xb << 4) +/*! Source Burst length of 13 transfers. */ +#define ALT_DMA_CCR_OPT_SB13 (0xc << 4) +/*! Source Burst length of 14 transfers. */ +#define ALT_DMA_CCR_OPT_SB14 (0xd << 4) +/*! Source Burst length of 15 transfers. */ +#define ALT_DMA_CCR_OPT_SB15 (0xe << 4) +/*! Source Burst length of 16 transfers. */ +#define ALT_DMA_CCR_OPT_SB16 (0xf << 4) +/*! Source Burst length default transfers. */ +#define ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1 + +/* + * Source Protection + */ +/*! Source Protection bits for AXI bus ARPROT[2:0]. */ +#define ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8) +/*! Source Protection bits default value. */ +#define ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0) + +/* + * Source cache + */ +/*! Source Cache bits for AXI bus ARCACHE[2:0]. */ +#define ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11) +/*! Source Cache bits default value. */ +#define ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0) + +/* + * Destination Address {Fixed,Incrementing} + */ +/*! Destination Address Fixed address burst. */ +#define ALT_DMA_CCR_OPT_DAF (0 << 14) +/*! Destination Address Incrementing address burst. */ +#define ALT_DMA_CCR_OPT_DAI (1 << 14) +/*! Destination Address Default value. */ +#define ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI + +/* + * Destination burst Size (in bits) + */ +/*! Destination burst Size of 8 bits. */ +#define ALT_DMA_CCR_OPT_DS8 (0 << 15) +/*! Destination burst Size of 16 bits. */ +#define ALT_DMA_CCR_OPT_DS16 (1 << 15) +/*! Destination burst Size of 32 bits. */ +#define ALT_DMA_CCR_OPT_DS32 (2 << 15) +/*! Destination burst Size of 64 bits. */ +#define ALT_DMA_CCR_OPT_DS64 (3 << 15) +/*! Destination burst Size of 128 bits. */ +#define ALT_DMA_CCR_OPT_DS128 (4 << 15) +/*! Destination burst Size default bits. */ +#define ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8 + +/* + * Destination Burst length (in transfer(s)) + */ +/*! Destination Burst length of 1 transfer. */ +#define ALT_DMA_CCR_OPT_DB1 (0x0 << 18) +/*! Destination Burst length of 2 transfers. */ +#define ALT_DMA_CCR_OPT_DB2 (0x1 << 18) +/*! Destination Burst length of 3 transfers. */ +#define ALT_DMA_CCR_OPT_DB3 (0x2 << 18) +/*! Destination Burst length of 4 transfers. */ +#define ALT_DMA_CCR_OPT_DB4 (0x3 << 18) +/*! Destination Burst length of 5 transfers. */ +#define ALT_DMA_CCR_OPT_DB5 (0x4 << 18) +/*! Destination Burst length of 6 transfers. */ +#define ALT_DMA_CCR_OPT_DB6 (0x5 << 18) +/*! Destination Burst length of 7 transfers. */ +#define ALT_DMA_CCR_OPT_DB7 (0x6 << 18) +/*! Destination Burst length of 8 transfers. */ +#define ALT_DMA_CCR_OPT_DB8 (0x7 << 18) +/*! Destination Burst length of 9 transfers. */ +#define ALT_DMA_CCR_OPT_DB9 (0x8 << 18) +/*! Destination Burst length of 10 transfers. */ +#define ALT_DMA_CCR_OPT_DB10 (0x9 << 18) +/*! Destination Burst length of 11 transfers. */ +#define ALT_DMA_CCR_OPT_DB11 (0xa << 18) +/*! Destination Burst length of 12 transfers. */ +#define ALT_DMA_CCR_OPT_DB12 (0xb << 18) +/*! Destination Burst length of 13 transfers. */ +#define ALT_DMA_CCR_OPT_DB13 (0xc << 18) +/*! Destination Burst length of 14 transfers. */ +#define ALT_DMA_CCR_OPT_DB14 (0xd << 18) +/*! Destination Burst length of 15 transfers. */ +#define ALT_DMA_CCR_OPT_DB15 (0xe << 18) +/*! Destination Burst length of 16 transfers. */ +#define ALT_DMA_CCR_OPT_DB16 (0xf << 18) +/*! Destination Burst length default transfers. */ +#define ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1 + +/* + * Destination Protection + */ +/*! Destination Protection bits for AXI bus AWPROT[2:0]. */ +#define ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22) +/*! Destination Protection bits default value. */ +#define ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0) + +/* + * Destination Cache + */ +/*! Destination Cache bits for AXI bus AWCACHE[3,1:0]. */ +#define ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25) +/*! Destination Cache bits default value. */ +#define ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0) + +/* + * Endian Swap size (in bits) + */ +/*! Endian Swap: No swap, 8-bit data. */ +#define ALT_DMA_CCR_OPT_ES8 (0 << 28) +/*! Endian Swap: Swap bytes within 16-bit data. */ +#define ALT_DMA_CCR_OPT_ES16 (1 << 28) +/*! Endian Swap: Swap bytes within 32-bit data. */ +#define ALT_DMA_CCR_OPT_ES32 (2 << 28) +/*! Endian Swap: Swap bytes within 64-bit data. */ +#define ALT_DMA_CCR_OPT_ES64 (3 << 28) +/*! Endian Swap: Swap bytes within 128-bit data. */ +#define ALT_DMA_CCR_OPT_ES128 (4 << 28) +/*! Endian Swap: Default byte swap. */ +#define ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8 + +/*! Default CCR register options for a DMAMOV CCR assembler directive. */ +#define ALT_DMA_CCR_OPT_DEFAULT \ + (ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \ + ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \ + ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \ + ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \ + ALT_DMA_CCR_OPT_ES8) + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_PROGRAM_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h new file mode 100644 index 0000000000..0a7abaef8e --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h @@ -0,0 +1,1254 @@ +/*! \file + * Altera - GPIO Module + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_GPIO_H__ +#define __ALT_GPIO_H__ + +#include +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define ALT_GPIO_BITMASK 0x1FFFFFFF + +/* If the GPIO special test mode flag was not defined in the makefile, */ + /* set the ALT_GPIO_DATAREAD_TEST_MODE flag to false to specify that */ + /* the production code version of alt_gpio_port_data_read() is included. */ + /* If the flag is defined as true in the makefile, then the test version */ + /* located in the test code file is substituted instead of the version */ + /* in this file. */ +#ifndef ALT_GPIO_DATAREAD_TEST_MODE +#define ALT_GPIO_DATAREAD_TEST_MODE false +#endif + +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_API The General Purpose Input/Output Manager API + * + * This module defines the General Purpose Input/Output Manager API for + * accessing, configuring, and controlling the General Purpose Input/Output + * Manager resources. These include both the general-purpose GPIO signals and + * the input-only GPI signals that are shared with the DDR interface.\n \n + * The GPIO API presents two views or perspectives of the GPIO signals. The first + * is to view the GPIO signals in a traditional way, as separate GPIO ports + * each comprised of a number of GPIO bits. The second perspective is of a + * unified flat view that presents the GPIO and GPI signals as a set of indexed + * bits, a view that allows the programmer to mostly ignore the port and pin + * hardware configuration and read/write/configure the GPIO and GPI signals + * independently of the underlying hardware implementation. + * + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions + * + * This functional group contains functions to control, configure and manage + * the general-purpose IO signals as individual signals or as groups of signals. + * This group of functions can operate on multiple bits within the same GPIO + * port and accepts a bit mask to specify which bits an operation will operate on. + * Other bits within the same GPIO port are not changed. + * + * This example shows how multiple drivers or applications can use this feature + * to easily prevent conflict while accessing the same GPIO port: + * \verbatim + #define DRIVER_0_GPIO_MSK 0x0010FF03; + #define DRIVER_1_GPIO_MSK 0x002000F8; + #define DRIVER_2_GPIO_MSK 0x03C00004; + #define DRIVER_3_GPIO_MSK 0x000F0000; + + alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_0_GPIO_MSK, init_val0); + alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, init_val1); + alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_2_GPIO_MSK, init_val2); + alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_3_GPIO_MSK, init_val3); + alt_gpio_port_int_type_set(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, config_val1); + \endverbatim + * + * @{ + */ +/******************************************************************************/ +/*! + * This type definition enumerates the data direction (input or output) of + * the GPIO signals. + */ + +typedef enum ALT_GPIO_PIN_DIR_e +{ + /*! # */ + ALT_GPIO_PIN_INPUT, + /*! # */ + ALT_GPIO_PIN_OUTPUT +} ALT_GPIO_PIN_DIR_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the type of interrupt source + * (level-triggered or edge-triggered) of the GPIO signals. + */ + +typedef enum ALT_GPIO_PIN_TYPE_e +{ + /*! # */ + ALT_GPIO_PIN_LEVEL_TRIG_INT, + /*! # */ + ALT_GPIO_PIN_EDGE_TRIG_INT +} ALT_GPIO_PIN_TYPE_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the polarity of the interrupt sources + * (falling-edge or rising-edge for edge-triggered interrupts, active-low or + * active-high for level-triggered interrupts) of the GPIO signals. + */ + +typedef enum ALT_GPIO_PIN_POL_e +{ + /*! Indicates active-low for level-triggered interrupts and + * falling-edge for edge-triggered interrupts */ + ALT_GPIO_PIN_ACTIVE_LOW, + + /*! Indicates active-high for level-triggered interrupts and + * rising-edge for edge-triggered interrupt */ + ALT_GPIO_PIN_ACTIVE_HIGH +} ALT_GPIO_PIN_POL_t; + +/******************************************************************************/ +/*! + * This type definition enumerates whether or not the debounce metastability + * flip-flops are inserted or not. These are used to debounce signals presented + * to the GPIO inputs. A signal must be steady for two periods of the + * gpio_db_clk clock before it is considered valid. The frequency of the + * gpio_db_clk clock may be set using the Clock Manager API. + */ + +typedef enum ALT_GPIO_PIN_DEBOUNCE_e +{ + /*! # */ + ALT_GPIO_PIN_NODEBOUNCE, + /*! # */ + ALT_GPIO_PIN_DEBOUNCE +} ALT_GPIO_PIN_DEBOUNCE_t; + +/******************************************************************************/ +/*! + * This type definition enumerates whether or not level-sensitive interrupts + * are synchronized to the internal pclk_intr clock. It has no effect for GPIO + * signals that are selected as outputs, or if the interrupt is not enabled, + * or if the interrupt is set to be edge-triggered. This is a port-wide option. + */ + +typedef enum ALT_GPIO_PIN_SYNC_e +{ + /*! # */ + ALT_GPIO_PIN_NOSYNC, + /*! # */ + ALT_GPIO_PIN_SYNC +} ALT_GPIO_PIN_SYNC_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the possible data states of the GPIO bits. + */ + +typedef enum ALT_GPIO_PIN_DATA_e +{ + /*! # */ + ALT_GPIO_PIN_DATAZERO, + /*! # */ + ALT_GPIO_PIN_DATAONE +} ALT_GPIO_PIN_DATA_t; + + +/******************************************************************************/ +/*! + * This type definition enumerates the GPIO ports that the GPIO manager + * handles. + */ + +typedef enum ALT_GPIO_PORT_e +{ + /*! + * \b Port \b A - 29-bit GPIO port A. + */ + ALT_GPIO_PORTA, + + /*! + * \b Port \b B - 29-bit GPIO port B. + */ + ALT_GPIO_PORTB, + + /*! + * \b Port \b C - 29-bit GPIO port C. \n 13 bits are used for GPIO signals, + * 14 bits are used for GPI-only signals that are shared + * with the DDR interface, 2 bits are not used. Some signals + * may not be connected on some versions. See the relevant + * pin mux data. + */ + ALT_GPIO_PORTC, + + /*! + * \b Unknown \b Port - Used to indicate an error. + */ + ALT_GPIO_PORT_UNKNOWN +} ALT_GPIO_PORT_t; + + +/******************************************************************************/ +/*! + * This type definition enumerates the individual bits within the GPIO ports + * used by the GPIO manager. The bit-ordering must match the hardware + * bit-ordering. Since the ordering and packing of bitfields is not + * standardized in C/C++, the following are defined as masks. \n + * For example, to set bits 3 and 4 of GPIO port B outputs (assuming the bits + * had previously been set to outputs), the user could use the syntax: \par + * \b alt_gpio_port_data_write(\b ALT_GPIO_PORTB, \b ALT_GPIO_BIT3 \b | \b + * ALT_GPIO_BIT4); + */ + +typedef enum ALT_GPIO_PORTBIT_e +{ + /*! # */ + ALT_GPIO_BIT0 = ALT_TWO_TO_POW0, + /*! # */ + ALT_GPIO_BIT1 = ALT_TWO_TO_POW1, + /*! # */ + ALT_GPIO_BIT2 = ALT_TWO_TO_POW2, + /*! # */ + ALT_GPIO_BIT3 = ALT_TWO_TO_POW3, + /*! # */ + ALT_GPIO_BIT4 = ALT_TWO_TO_POW4, + /*! # */ + ALT_GPIO_BIT5 = ALT_TWO_TO_POW5, + /*! # */ + ALT_GPIO_BIT6 = ALT_TWO_TO_POW6, + /*! # */ + ALT_GPIO_BIT7 = ALT_TWO_TO_POW7, + /*! # */ + ALT_GPIO_BIT8 = ALT_TWO_TO_POW8, + /*! # */ + ALT_GPIO_BIT9 = ALT_TWO_TO_POW9, + /*! # */ + ALT_GPIO_BIT10 = ALT_TWO_TO_POW10, + /*! # */ + ALT_GPIO_BIT11 = ALT_TWO_TO_POW11, + /*! # */ + ALT_GPIO_BIT12 = ALT_TWO_TO_POW12, + /*! # */ + ALT_GPIO_BIT13 = ALT_TWO_TO_POW13, + /*! # */ + ALT_GPIO_BIT14 = ALT_TWO_TO_POW14, + /*! # */ + ALT_GPIO_BIT15 = ALT_TWO_TO_POW15, + /*! # */ + ALT_GPIO_BIT16 = ALT_TWO_TO_POW16, + /*! # */ + ALT_GPIO_BIT17 = ALT_TWO_TO_POW17, + /*! # */ + ALT_GPIO_BIT18 = ALT_TWO_TO_POW18, + /*! # */ + ALT_GPIO_BIT19 = ALT_TWO_TO_POW19, + /*! # */ + ALT_GPIO_BIT20 = ALT_TWO_TO_POW20, + /*! # */ + ALT_GPIO_BIT21 = ALT_TWO_TO_POW21, + /*! # */ + ALT_GPIO_BIT22 = ALT_TWO_TO_POW22, + /*! # */ + ALT_GPIO_BIT23 = ALT_TWO_TO_POW23, + /*! # */ + ALT_GPIO_BIT24 = ALT_TWO_TO_POW24, + /*! # */ + ALT_GPIO_BIT25 = ALT_TWO_TO_POW25, + /*! # */ + ALT_GPIO_BIT26 = ALT_TWO_TO_POW26, + /*! # */ + ALT_GPIO_BIT27 = ALT_TWO_TO_POW27, + /*! # */ + ALT_GPIO_BIT28 = ALT_TWO_TO_POW28, + ALT_GPIO_BIT29 = ALT_TWO_TO_POW29, /* Not currently used */ + ALT_GPIO_BIT30 = ALT_TWO_TO_POW30, /* Not currently used */ + ALT_GPIO_BIT31 = (int32_t) (1UL<<31), /* Not currently used */ + + ALT_GPIO_BITNUM_MAX = (28), + ALT_GPIO_BIT_MAX = (1 << ALT_GPIO_BITNUM_MAX), + ALT_END_OF_GPIO_PORT_SIGNALS = (32) +} ALT_GPIO_PORTBIT_t; + + + +/******************************************************************************/ +/*! + * Initialize the GPIO modules before use + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_gpio_init(void); + +/******************************************************************************/ +/*! + * Uninitialize the GPIO modules & return to reset state + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_gpio_uninit(void); + +/******************************************************************************/ +/*! + * Sets the specified GPIO data bits to use the data direction(s) + * specified. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are + * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to + * configure all data direction bits of the port. + * \param config + * The data-directions of the bits to be set in this operation. + * Individual bits are: \n \b 0 - Use as an input (default). \n + * \b 1 - Use as an output. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Bad input argument. + */ +ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the data direction configuration of selected bits of the + * specified GPIO module. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to read and + * return. Other bits (where mask bits equal zero) are returned + * as zero. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to + * return all data direction bits of the port. + * + * \retval uint32_t \n Individual bits are: \n \b 0 - The signal is + * configured as an input. + * \n \b 1 - The signal is configured as an output. + * + */ +uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask); + +/******************************************************************************/ +/*! + * Sets the GPIO data outputs of the specified GPIO module to a logic one or + * zero. Outputs are only set if the data direction for those bits is also + * set to configure them as outputs. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (mask bits equal one) to apply this + * operation to. Other bits (mask bits equal zero) are + * not changed. + * \param val + * The 32-bit word to write to the GPIO outputs. Only the 29 LSBs + * are used. Setting the three MSBs causes an error. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Bad input argument. + */ +ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t val); + +/******************************************************************************/ +/*! + * Returns the value of the data inputs of the specified GPIO module. This is + * the current logic value of the pin, whether set to be an input or an output. + * \n If a given signal is set to be an output, this input value can be read to + * determine if the pin is grounded, pulled high, or is floating. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify + * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all data bits of + * the port. + * + * \retval uint32_t The current value of the GPIO module input signals. + */ +uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask); + + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions + * + * This functional group contains functions to control and manage the + * interrupts of the General-Purpose IO modules. + * + * @{ + */ +/******************************************************************************/ +/*! + * Sets edge-triggered or level-triggered interrupt configuration for the + * specified signals of the specified GPIO module. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are + * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to + * configure all interrupt type bits of the port. + * \param config + * The interrupt configuration to write. Individual bits + * are: \n \b 0 - Set the + * interrupt for this bit to be level-sensitive (default). \n \b + * 1 - Set the interrupt for this bit to be edge-sensitive. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the interrupt configuration (edge-triggered or level-triggered) for + * the specified bits of the specified GPIO module. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify + * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all configuration + * bits of the port. + * \retval uint32_t + * The current interrupt source configuration. Individual bits + * are: \n \b 0 - The interrupt for this bit is set to be + * level-sensitive. \n \b 1 - + * The interrupt for this bit is set to be edge-sensitive. + * + */ +uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask); + +/******************************************************************************/ +/*! + * Sets the interrupt polarity of the signals of the specified GPIO register + * (when used as inputs) to active-high or active-low (for level-sensitive + * interrupts) or to rising-edge or falling-edge (for edge-sensitive interrupts). + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are + * not changed. + * \param config + * The interrupt polarity configuration to set. Individual bits + * are: \n \b 0 - Set the interrupt polarity for this bit to + * active-low or falling-edge mode (default). \n \b 1 - Set the + * interrupt polarity for this bit to active-high or rising-edge mode. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the active-high or active-low polarity configuration for the + * possible interrupt sources of the specified GPIO module. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify + * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all the + * configuration bits of the port. + * + * \retval uint32_t + * The current polarity configuration. Individual bits are: \n + * \b 0 = The interrupt polarity for this bit is set to + * active-low or falling-edge mode. \n \b 1 = The interrupt + * polarity for this bit is set to active-high or rising-edge mode. + * + */ +uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask); + + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions + * + * @{ + */ +/******************************************************************************/ +/*! + * Sets the debounce configuration for input signals of the specified GPIO + * module. If debounce is selected, metastability flip-flops are inserted to + * debounce signals presented to the GPIO inputs. A signal must be steady for + * two periods of the gpio_db_clk clock before it is considered valid. The + * frequency of the gpio_db_clk clock may be set using the Clock Manager API. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are + * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to + * configure the debounce setting for all bits of the port. + * \param config + * The debounce configuration to set. Individual bits are: \n + * \b 0 - Debounce is not selected for this signal (default). \n + * \b 1 - Debounce is selected for this signal. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the debounce configuration for the input signals of the specified + * GPIO register. If debounce is selected, metastability flip-flops are + * inserted to debounce signals presented to the GPIO inputs. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify + * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all debounce + * configuration bits of the port. + * + * \retval uint32_t + * The current debounce configuration.Individual bits are: \n + * \b 0 - Debounce is not selected for this signal. \n \b 1 - + * Debounce is selected for this signal. + * + */ +uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask); + +/******************************************************************************/ +/*! + * Sets the synchronization configuration for the signals of the specified + * GPIO register. This allows for synchronizing level-sensitive interrupts to + * an internal clock signal. This is a port-wide option that controls all + * level-sensitive interrupt signals of that GPIO port. + * + * \param gpio_pid + * The GPIO port identifier. + * \param config + * \n \b Any \b non-zero \b value - Synchronize to internal clock signal. + * \n \b Zero - Do not synchronize to internal clock signal. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t config); + +/******************************************************************************/ +/*! + * + * Returns the synchronization configuration for the signals of the + * specified GPIO register. This allows for synchronizing level-sensitive + * interrupts to the internal clock signal. This is a port-wide option that + * controls all level-sensitive interrupt signals of that GPIO port. + * + * \param gpio_pid + * The GPIO port identifier. + + + * \retval ALT_E_TRUE Synchronization to clock is enabled for + * level-sensitive interrupts. + * \retval ALT_E_FALSE Synchronization to clock is disabled for + * level-sensitive interrupts. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid); + +/******************************************************************************/ +/*! + * Configures a group of GPIO signals with identical setup parameters. Allows + * for configuring all parameters of a given port at one time. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits to apply this operation to. Other bits (mask + * set to zero) are not changed. + * \param dir + * Data direction. + * \param type + * Edge-triggered or level-triggered interrupts. + * \param pol + * Active-high or active-low polarity. + * \param debounc + * Debounce signals or not. + * \param data + * Set the data output to this value. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + + */ +ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, + ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounc, + uint32_t data); + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions + * + * @{ + */ +/******************************************************************************/ +/*! + * Enables the specified GPIO data input interrupts. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param config + * Individual bit interrupt enables \n + * \b 0 - Interrupt disabled. \n + * \b 1 - Interrupt enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Bad input argument. + */ +ALT_STATUS_CODE alt_gpio_port_int_enable(ALT_GPIO_PORT_t gpio_pid, uint32_t config); + +/******************************************************************************/ +/*! + * Disables the specified GPIO data module interrupt. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param config + * Individual bit interrupt enables \n + * \b 0 - Interrupt disabled. \n + * \b 1 - Interrupt enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Bad input argument. + */ +ALT_STATUS_CODE alt_gpio_port_int_disable(ALT_GPIO_PORT_t gpio_pid, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the current state of the specified GPIO port interrupts enables. + * + * \param gpio_pid + * The GPIO port identifier. + * + * \retval uint32_t + * The interrupt enable configuration that was read. Individual bits + * are: \n \b 0 = The interrupt for this bit is not enabled. \n \b + * 1 = The interrupt for this bit is enabled. + */ +uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid); + + +/******************************************************************************/ +/*! + * Masks or unmasks selected interrupt source bits of the data register of + * the specified GPIO module. Uses a second bit mask to determine which + * signals may be changed by this call. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * Which bits to change among the port \n \b 0 = + * Do not change this bit. \n \b 1 = Allow this bit to change. + * \param val + * The interrupt mask to write. Individual bits are: \n \b 0 = + * Do not mask the interrupt for this bit (default). \n \b 1 = + * Mask the interrupt for this bit. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t val); + +/******************************************************************************/ +/*! + * Returns the interrupt mask of the specified GPIO module. + * + * + * \param gpio_pid + * The GPIO port identifier. + * + * \retval uint32_t + * The interrupt mask that was read. Individual bits are: \n + * \b 0 = The interrupt for this bit is not masked. \n \b 1 = The + * interrupt for this bit is masked. + * + */ +uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid); + +/******************************************************************************/ +/*! + * Returns the interrupt pending status of all signals of the specified GPIO + * register. + * + * + * \param gpio_pid + * The GPIO port identifier. + + * \retval uint32_t + * The current interrupt pending status. Individual bits are: \n + * \b 0 - The interrupt for this bit is not pending. \n \b 1 - + * The interrupt for this bit is pending. + * + */ +uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid); + +/******************************************************************************/ +/*! + * Clear the interrupt pending status of selected signals of the + * specified GPIO register. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param clrmask + * The interrupt bits to clear. Individual bits are: \n \b 0 - + * The interrupt for this bit will not be changed. \n \b 1 - + * The interrupt for this bit will be cleared. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_int_status_clear(ALT_GPIO_PORT_t gpio_pid, + uint32_t clrmask); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index + * + * This functional group presents a perspective of the General-Purpose IO + * signals as individual GPIO and GPI bits spread across a number of signals + * across several GPIO ports. This allows the programmer the freedom to generally + * ignore the underlying port and signal structure of the GPIO hardware if + * desired. + * + * @{ + */ +/******************************************************************************/ +/*! + * This type definition enumerates the individual bits as one flat array spread + * across the multiple GPIO ports handled by the GPIO manager. The bit-ordering + * must match the hardware bit-ordering. + * + */ +typedef enum ALT_GPIO_1BIT_e +{ + /*! # */ + ALT_GPIO_1BIT_0, + /*! # */ + ALT_GPIO_1BIT_1, + /*! # */ + ALT_GPIO_1BIT_2, + /*! # */ + ALT_GPIO_1BIT_3, + /*! # */ + ALT_GPIO_1BIT_4, + /*! # */ + ALT_GPIO_1BIT_5, + /*! # */ + ALT_GPIO_1BIT_6, + /*! # */ + ALT_GPIO_1BIT_7, + /*! # */ + ALT_GPIO_1BIT_8, + /*! # */ + ALT_GPIO_1BIT_9, + /*! # */ + ALT_GPIO_1BIT_10, + /*! # */ + ALT_GPIO_1BIT_11, + /*! # */ + ALT_GPIO_1BIT_12, + /*! # */ + ALT_GPIO_1BIT_13, + /*! # */ + ALT_GPIO_1BIT_14, + /*! # */ + ALT_GPIO_1BIT_15, + /*! # */ + ALT_GPIO_1BIT_16, + /*! # */ + ALT_GPIO_1BIT_17, + /*! # */ + ALT_GPIO_1BIT_18, + /*! # */ + ALT_GPIO_1BIT_19, + /*! # */ + ALT_GPIO_1BIT_20, + /*! # */ + ALT_GPIO_1BIT_21, + /*! # */ + ALT_GPIO_1BIT_22, + /*! # */ + ALT_GPIO_1BIT_23, + /*! # */ + ALT_GPIO_1BIT_24, + /*! # */ + ALT_GPIO_1BIT_25, + /*! # */ + ALT_GPIO_1BIT_26, + /*! # */ + ALT_GPIO_1BIT_27, + /*! # */ + ALT_GPIO_1BIT_28, + /*! # */ + ALT_GPIO_1BIT_29, + /*! # */ + ALT_GPIO_1BIT_30, + /*! # */ + ALT_GPIO_1BIT_31, + /*! # */ + ALT_GPIO_1BIT_32, + /*! # */ + ALT_GPIO_1BIT_33, + /*! # */ + ALT_GPIO_1BIT_34, + /*! # */ + ALT_GPIO_1BIT_35, + /*! # */ + ALT_GPIO_1BIT_36, + /*! # */ + ALT_GPIO_1BIT_37, + /*! # */ + ALT_GPIO_1BIT_38, + /*! # */ + ALT_GPIO_1BIT_39, + /*! # */ + ALT_GPIO_1BIT_40, + /*! # */ + ALT_GPIO_1BIT_41, + /*! # */ + ALT_GPIO_1BIT_42, + /*! # */ + ALT_GPIO_1BIT_43, + /*! # */ + ALT_GPIO_1BIT_44, + /*! # */ + ALT_GPIO_1BIT_45, + /*! # */ + ALT_GPIO_1BIT_46, + /*! # */ + ALT_GPIO_1BIT_47, + /*! # */ + ALT_GPIO_1BIT_48, + /*! # */ + ALT_GPIO_1BIT_49, + /*! # */ + ALT_GPIO_1BIT_50, + /*! # */ + ALT_GPIO_1BIT_51, + /*! # */ + ALT_GPIO_1BIT_52, + /*! # */ + ALT_GPIO_1BIT_53, + /*! # */ + ALT_GPIO_1BIT_54, + /*! # */ + ALT_GPIO_1BIT_55, + /*! # */ + ALT_GPIO_1BIT_56, + /*! # */ + ALT_GPIO_1BIT_57, + /*! # */ + ALT_GPIO_1BIT_58, + /*! # */ + ALT_GPIO_1BIT_59, + /*! # */ + ALT_GPIO_1BIT_60, + /*! # */ + ALT_GPIO_1BIT_61, + /*! # */ + ALT_GPIO_1BIT_62, + /*! # */ + ALT_GPIO_1BIT_63, + /*! # */ + ALT_GPIO_1BIT_64, + /*! # */ + ALT_GPIO_1BIT_65, + /*! # */ + ALT_GPIO_1BIT_66, + /*! # */ + ALT_GPIO_1BIT_67, /* Not bonded out on some versions */ + /*! # */ + ALT_GPIO_1BIT_68, /* Not bonded out on some versions */ + /*! # */ + ALT_GPIO_1BIT_69, /* Not bonded out on some versions */ + + /*! The last of the input/output bits */ + ALT_GPIO_1BIT_70, /* Not bonded out on some versions */ + + + /*! This and the following signals are not present on all SoCs. \n + * If present, the selection between their use as 14 General-purpose inputs or + * use as 14 DDR interface signals is made in the IOCSR (IO Configuration Shift + * Register) and software to make this selection is in the IO Manager API. If + * they are present, they are restricted to using the same power supply voltage + * as the SDRAM module.*/ + ALT_HLGPI_0, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_1, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_2, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_3, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_4, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_5, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_6, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_7, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_8, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_9, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_10, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_11, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_12, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_13, /* Not bonded out on some versions */ + + ALT_HLGPI_14, /* Not bonded out */ + + ALT_HLGPI_15, /* Not bonded out */ + + ALT_GPIO_INVALID, + ALT_END_OF_GPIO_SIGNALS = -1, + ALT_LAST_VALID_GPIO_BIT = ALT_HLGPI_15 +} ALT_GPIO_1BIT_t; + + +/******************************************************************************/ +/*! + * This configuration record definition is used for configuring bits and + * groups of bits of the GPIO interface. + */ +typedef struct ALT_GPIO_CONFIG_RECORD_s +{ + /*! + * The index number of the signal to configure. */ + ALT_GPIO_1BIT_t signal_number; + /*! + * The data direction of the signal. */ + ALT_GPIO_PIN_DIR_t direction; + /*! + * Edge-triggered or level triggered interrupts. */ + ALT_GPIO_PIN_TYPE_t type; + /*! + * Active-high or active-low trigger for the interrupt. */ + ALT_GPIO_PIN_POL_t polarity; + /*! + * Enable or disable GPIO debounce capability. */ + ALT_GPIO_PIN_DEBOUNCE_t debounce; + /*! + * If the signal is an output, the data value to be output. */ + ALT_GPIO_PIN_DATA_t data; +} ALT_GPIO_CONFIG_RECORD_t; + +/******************************************************************************/ +/*! + * This pin record type definition is comprised of the signal index and + * associated input or output data. + */ +typedef struct ALT_GPIO_PIN_RECORD_s +{ + /*! + * The index number of the signal. */ + ALT_GPIO_1BIT_t signal_number; + /*! + * Data - zero or one. */ + ALT_GPIO_PIN_DATA_t val; +} ALT_GPIO_PIN_RECORD_t; + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index + * + * @{ + */ +/******************************************************************************/ +/*! + * Configures all parameters for one bit (signal) of the GPIO ports. + * + * \param signal_num + * The GPIO port signal index. + * \param dir + * The data direction for this signal. + * \param type + * Edge-triggered or Level-triggered interrupt for this signal. + * \param pol + * Active-high or active-low interrupt polarity for this signal. + * \param debounce + * Enable the debounce flip-flops for this signal or not. + * \param data + * If the GPIO signal is set to be an output, set it to + * this value + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num, + ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, + ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounce, + ALT_GPIO_PIN_DATA_t data); + +/******************************************************************************/ +/*! + * Returns the configuration parameters of a given GPIO bit. + * + * \param signal_num + * The GPIO port signal index. + * \param config + * Pointer to a single GPIO_CONFIG_RECORD_s configuration record. + * The fields of this configuration record are filled in + * by the function. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + + */ +ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num, + ALT_GPIO_CONFIG_RECORD_t *config); + +/******************************************************************************/ +/*! + * Configures a list of GPIO bits. The GPIO bits do not have to be + * configured the same, as was the case for the mask version of this function, + * alt_gpio_port_config(). Each bit may be configured differently and bits may + * be listed in any order. + * + * \param config_array + * Pointer to an array of GPIO_CONFIG_RECORD_s configuration + * records. These definitions contain all the parameters + * needed to set up the listed pins. All or + * any subset of the GPIO signals can be configured. Signals do + * not have to be listed in numerical order or be unique. If a + * signal number is listed multiple times, the last configuration + * listed is used. \n Configuration terminates either when \b len + * signals have been configured or if the next signal number index + * in the array is equal to \b ALT_END_OF_GPIO_SIGNALS (-1). + * + * \param len + * Length of array to configure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + + */ +ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array, + uint32_t len); + +/******************************************************************************/ +/*! + * Returns a list of the pin signal indices and the associated configuration + * settings (data direction, interrupt type, polarity, and debounce) of that + * list of signals. + * + * \param config_array + * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration + * records. Only the signal indices in the first field of each + * configuration record need be filled in. This function will + * fill in all the other fields of the configuration record, + * returning all configuration parameters in the array. + * Signals do not have to be listed in numerical order or be + * unique. If a signal number is listed multiple times, the + * configuration record will contain multiple entries for + * that signal. \n Configuration reading terminates either when + * \b len signal configurations have been read or if the next + * signal number index in the array is equal to + * \b ALT_END_OF_GPIO_SIGNALS (-1). + * \param len + * Length of configuration array to read and return. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + + */ +ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array, + uint32_t len); + +/******************************************************************************/ +/*! + * Returns a list of the pin signal indices and the associated configuration + * settings (data direction, interrupt type, polarity, and debounce) of that + * list of signals. The difference between this version and + * alt_gpio_group_config_get() is this version follows a separate list of + * signal indices instead of having the signal list provided in the first + * field of the configuration records in the array. + * + * \param pinid_array + * Pointer to a list of signal index numbers. These indices + * are copied to the first field of each configuration record + * in the returned array. + * \param config_array + * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration + * records. This function will fill in the fields of the + * configuration record, returning all configuration parameters + * in the array. Signals do not have to be listed in numerical + * order or be unique. If a signal number is listed multiple + * times, the configuration record array will contain multiple + * identical entries for that signal. \n Configuration reading + * terminates either when \b len signal configurations have been + * read or if the next signal number index in the array is equal + * to \b ALT_END_OF_GPIO_SIGNALS (-1). + * \param len + * Length of configuration array to read. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + * + */ +ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array, + ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len); + + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_UTILITY General-Purpose IO Utility Functions + * + * These are useful utility functions for the general-purpose input & output + * module. + * + * @{ */ +/******************************************************************************/ +/*! + * Returns the ID code of the specified GPIO module. + * + * \param gpio_pid + * The GPIO port identifier. + * + * + * \retval uint32_t The component code of the module, GPIO_MODULE_IDCODE. + */ +uint32_t alt_gpio_port_idcode_get(ALT_GPIO_PORT_t gpio_pid); + +/******************************************************************************/ +/*! + * Returns the version code of the specified GPIO module. + * + * \param gpio_pid + * The GPIO port identifier. + * + * + * \retval uint32_t The encoded revision number of the module. + */ +uint32_t alt_gpio_port_ver_get(ALT_GPIO_PORT_t gpio_pid); + + +/******************************************************************************/ +/*! + * Extracts the GPIO port ID from the supplied GPIO Signal Index Number. + */ +ALT_GPIO_PORT_t alt_gpio_bit_to_pid(ALT_GPIO_1BIT_t pin_num); + + +/******************************************************************************/ +/*! + * Extracts the GPIO signal (pin) offset from the supplied GPIO Signal Index + * Number. + * */ +ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num); + +/******************************************************************************/ +/*! + * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and + * signal mask. If passed a bitmask composed of more than one signal, the + * signal number of the lowest bit in the bitmask presented is returned. + * + */ +ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid, + uint32_t bitmask); + + +/*! @} */ +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_GPIO_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h new file mode 100644 index 0000000000..7596d50d66 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h @@ -0,0 +1,56 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_HWLIBS_VER_H__ + +/*********************************************************************** + * + * Set of macros to provide version information + * + ***********************************************************************/ + +/* This is the major revision of the Altera ACDS Release */ +#define ALTERA_ACDS_MAJOR_REV 13 + +/* This is the minor revision of the Altera ACDS Release */ +#define ALTERA_ACDS_MINOR_REV 1 + +/* This is an internal HwLibs revision/feature control code. */ +/* End-users should NOT depend upon the value of this field */ +#define ALTERA_HWLIBS_REV 0 + +/* This is a text string containing the current release and service pack IDs */ +#define ALTERA_ACDS_REV_STR "13.1" + +/* This is a text string containing the current SoC EDS ID */ +#define ALTERA_SOCEDS_REV_STR "Altera SoC Embedded Design Suite v13.1" + + +#endif /* __ALT_HWLIBS_VER_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h new file mode 100644 index 0000000000..7af55cf4ac --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h @@ -0,0 +1,2024 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/*! \file + * Altera - I2C Controller API + */ + +#ifndef __ALT_I2C_H__ +#define __ALT_I2C_H__ + +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "socal/alt_i2c.h" +#include "socal/alt_rstmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C I2C Controller API + * + * This module defines an API for configuring and managing the HPS I2C controllers. + * + * The I2C controller provides support for a communication link between integrated + * circuits on a board. It is a simple two-wire bus which consists of a serial + * data line (SDA) and a serial clock (SCL) for use in applications such as + * temperature sensors and voltage level translators to EEPROMs, A/D and D/A + * converters, CODECs, and many types of microprocessors. + * + * The Hard Processor System (HPS) provides four I2C controllers to enable system + * software to communicate serially with I2C buses. Each I2C controller can + * operate in master or slave mode, and support standard mode of up to 100 + * kilobits per second (Kbps) or fast mode of up to 400 Kbps. These I2C + * controllers are instances of the Synopsys DesignWare APB I2C (DW_apb_i2c) + * controller. + * + * NOTE: Each I2C controller must be programmed to operate in either master or + * slave mode only. Operating as a master and slave simultaneously is not + * supported. + * + * Features of the I2C Controller: + * * Support both 100 KBps and 400 KBps modes + * * One of the following I2C operations: master or slave + * * Support both 7-bit and 10-bit addressing modes + * * Mixed read and write combined-format transactions + * * Bulk transmit mode + * * DMA handshaking interface + * + * For a complete details on the configuration and operation of I2C controller, + * consult the following references: + * * Cyclone V Device Handbook Volume 3: Hard Processor System Technical + * Reference Manual, Chapter 20. I2C Controller (cv_54020-1.2) + * * Synopsys DesignWare DW_apb_i2c Databook DW_apb_i2c, Version 1.15a + * * The I2C-Bus Specification Version 2.1 + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the operational state of I2C by + * transfer operation. + */ +typedef enum ALT_I2C_TRANSFER_TYPE_e +{ + ALT_I2C_TRANSFER_NONE = 0, /*!< No transfer operation */ + ALT_I2C_TRANSFER_START = 1, /*!< Start detect */ + ALT_I2C_TRANSFER_COMPLETE = 2, /*!< All operations done */ + ALT_I2C_TRANSFER_READ = 3, /*!< Read operation is active */ + ALT_I2C_TRANSFER_WRITE = 4, /*!< Write operation is active */ +} +ALT_I2C_TRANSFER_TYPE_t; + + +/* + * A pointer or handle to the I2C controller device instance. The ALT_I2C_DEV_t is + * initialized by a call to alt_i2c_init() and subsequently used by the other I2C + * controller API functions as a reference to a specific device. + * + * \internal + * ALT_I2C_DEV_t may be a struct or reference to an opaque data + * structure. Whatever "internal" type is suited to the needs of the + * implementation. + * \endinternal + */ +typedef struct ALT_I2C_DEV_s +{ + void * location; /*!< HPS address of I2C instance. */ + alt_freq_t clock_freq; /*!< Input clock frequency. */ + uint32_t last_target; /*!< Last issued target address. */ +} +ALT_I2C_DEV_t; + +/*! + * This type enumerates the HPS I2C controller instances. + */ +typedef enum ALT_I2C_CTLR_e +{ + ALT_I2C_I2C0 = (int)ALT_I2C0_OFST, /*!< I2C0 instance. */ + ALT_I2C_I2C1 = (int)ALT_I2C1_OFST, /*!< I2C1 instance. */ + ALT_I2C_I2C2 = (int)ALT_I2C2_OFST, /*!< I2C2 instance. */ + ALT_I2C_I2C3 = (int)ALT_I2C3_OFST, /*!< I2C3 instance. */ +} ALT_I2C_CTLR_t; + +/*! + * This type enumerates the modes that the I2C controller may operate in. + * + * NOTE: Each I2C controller must be programmed to operate in either master or + * slave mode only. Operating as a master and slave simultaneously is not + * supported. + */ +typedef enum ALT_I2C_MODE_e +{ + ALT_I2C_MODE_SLAVE = ALT_I2C_CON_MST_MOD_E_DIS, /*!< Slave Mode */ + ALT_I2C_MODE_MASTER = ALT_I2C_CON_MST_MOD_E_EN /*!< Master Mode */ +} ALT_I2C_MODE_t; + +/*! + * This type enumerates the I2C controller operational speed modes. + * + * The I2C controller can operate in standard mode (with data rates 0 to 100 Kbps) + * or fast mode (with data rates less than or equal to 400 Kbps). Additionally, + * fast mode devices are downward compatible. For instance, fast mode devices can + * communicate with standard mode devices in 0 to 100 Kbps I2C bus + * system. However, standard mode devices are not upward compatible and should not + * be incorporated in a fast-mode I2C bus system as they cannot follow the higher + * transfer rate and therefore unpredictable states would occur. + * + * This setting is relevant only if one is operating the I2C in master mode. + */ +typedef enum ALT_I2C_SPEED_e +{ + ALT_I2C_SPEED_STANDARD = ALT_I2C_CON_SPEED_E_STANDARD, + /*!< Standard mode (0 to 100 Kbps) */ + ALT_I2C_SPEED_FAST = ALT_I2C_CON_SPEED_E_FAST + /*!< Fast mode (<= 400 Kbps) */ +} ALT_I2C_SPEED_t; + +/*! + * This type enumerates the two addressing modes formats supported by the I2C + * controller. + * + * The I2C controller does not support mixed address format - that is, a 7-bit + * address transaction followed by a 10-bit address transaction or vice versa - + * combined format transactions. + */ +typedef enum ALT_I2C_ADDR_MODE_e +{ + ALT_I2C_ADDR_MODE_7_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START7, + /*!< 7-Bit Address Format */ + ALT_I2C_ADDR_MODE_10_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 + /*!< 10-Bit Address Format */ +} ALT_I2C_ADDR_MODE_t; + +/*! + * This type enumerates interrupt status conditions for the I2C controller. + */ +typedef enum ALT_I2C_STATUS_e +{ + ALT_I2C_STATUS_RX_UNDER = 1UL << 0, + /*!< Set if the processor attempts to read the + * receive buffer when it is empty. If the I2C + * controller is disabled, this status keeps + * maintains its state until the master or slave + * state machines go into idle, then this + * interrupt is cleared. + */ + ALT_I2C_STATUS_RX_OVER = 1UL << 1, + /*!< Set if the receive buffer is completely + * filled to capacity and an additional byte is + * received from an external I2C device. The I2C + * controller acknowledges this, but any data + * bytes received after the FIFO is full are + * discarded. If the I2C controller is disabled, + * this status maintains its statue until the + * master or slave state machines go into idle, + * then this interrupt is cleared. + */ + ALT_I2C_STATUS_RX_FULL = 1UL << 2, + /*!< Set when the receive buffer reaches or goes + * above the RX_TL threshold. It is + * automatically cleared by hardware when buffer + * level goes below the threshold. If the I2C + * controller is disabled, the RX FIFO is + * flushed and held in reset; therefore the RX + * FIFO is not full. So this bit is cleared once + * the I2C controller is disabled, regardless of + * the activity that continues. + */ + ALT_I2C_STATUS_TX_OVER = 1UL << 3, + /*!< Set during transmit if the transmit buffer is + * filled to capacity and the processor attempts + * to issue another I2C command. When the I2C + * controller is disabled, this bit maintains + * its state until the master or slave state + * machines go into idle, then this interrupt is + * cleared. + */ + ALT_I2C_STATUS_TX_EMPTY = 1UL << 4, + /*!< This bit is set to 1 when the transmit buffer + * is at or below the configured threshold + * value. It is automatically cleared by + * hardware when the buffer level goes above the + * threshold. When the I2C controller is + * disabled, the TX FIFO is flushed and held in + * reset. The TX FIFO appears as if it has no + * data in it, so this bit is set to 1, provided + * there is activity in the master or slave + * state machines. When there is no longer + * activity, then this bit is set to 0. + * + */ + ALT_I2C_STATUS_RD_REQ = 1UL << 5, + /*!< This bit is set to 1 when I2C is acting as a + * slave and another I2C master is attempting to + * read data from the I2C. The I2C holds the bus + * in a wait state until this interrupt is + * serviced, which means that the slave has been + * addressed by a remote master that is asking + * for data to be transferred. The processor + * must respond to this interrupt and then write + * the requested data. This bit is set to 0 just + * after the processor by calling + * alt_i2c_int_clear() with + * ALT_I2C_STATUS_RD_REQ in the mask.. + */ + ALT_I2C_STATUS_TX_ABORT = 1UL << 6, + /*!< This bit indicates if I2C, as an I2C + * transmitter, is unable to complete the + * intended actions on the contents of the + * transmit FIFO. This situation can occur both + * as an I2C master or an I2C slave, and is + * referred to as a 'transmit abort'. When this + * bit is set to 1, the IC_TX_ABRT_SOURCE + * register indicates the reason why the + * transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX + * FIFO whenever this bit is set. The TX FIFO + * remains in this flushed state until the + * register alt_i2c_int_clear() with + * ALT_I2C_STATUS_TX_ABORT in the mask is + * called. Once this happens, the TX FIFO is + * then ready to accept more data bytes from the + * APB interface. + */ + ALT_I2C_STATUS_RX_DONE = 1UL << 7, + /*!< When the I2C is acting as a + * slave-transmitter, this bit is set to 1 if + * the master does not acknowledge a transmitted + * byte. This occurs on the last byte of the + * transmission, indicating that the + * transmission is done. + */ + ALT_I2C_STATUS_ACTIVITY = 1UL << 8, + /*!< This bit captures I2C activity and stays set + * until it is cleared. There are four ways to + * clear it: + * * Disabling the I2C controller + * * Calling alt_i2c_int_clear() with + * ALT_I2C_STATUS_ACTIVITY in the mask. + * * Calling alt_i2c_int_clear() with + * ALT_I2C_STATUS_ALL in the mask. + * * System reset + * + * Once this bit is set, it stays set unless one + * of the four methods is used to clear it. Even + * if the I2C module is idle, this bit remains + * set until cleared, indicating that there was + * activity on the bus. + */ + ALT_I2C_STATUS_STOP_DET = 1UL << 9, + /*!< Indicates whether a STOP condition has + * occurred on the I2C interface regardless of + * whether I2C is operating in slave or master + * mode. + */ + ALT_I2C_STATUS_START_DET = 1UL << 10, + /*!< Indicates whether a START or RESTART + * condition has occurred on the I2C interface + * regardless of whether I2C is operating in + * slave or master mode. + */ + ALT_I2C_STATUS_INT_CALL = 1UL << 11, + /*!< Set only when a General Call address is + * received and it is acknowledged. It stays set + * until it is cleared either by disabling I2C + * or when alt_i2c_int_clear() with + * ALT_I2C_STATUS_CALL in the mask is + * called. I2C stores the received data in the + * Rx buffer. + */ + ALT_I2C_STATUS_INT_ALL = 0xFFF, + /*!< All Combined and Individual Interrupts. This + * enumeration value can be used to clear, + * disable, and enable the combined interrupt + * and all individual interrupt status + * conditions. As a side effect, when passed to + * alt_i2c_int_clear(), clears the source causes + * (\ref ALT_I2C_TX_ABORT_CAUSE_t) of the + * ALT_I2C_STATUS_TX_ABORT condition. + */ +} ALT_I2C_STATUS_t; + +/*! + * This type enumerates the source causes of a ALT_I2C_STATUS_TX_ABORT condition. + * + * The active ALT_I2C_TX_ABORT_CAUSE_t source conditions are cleared when + * alt_i2c_int_clear() with is called ALT_I2C_STATUS_TX_ABORT in the mask or + * alt_i2c_int_clear() is called with ALT_I2C_STATUS_ALL in the mask. + * + * \internal + * Discuss special handling of abrt_sbyte_norstrt TX_ABRT source required in ???() function. + * \endinternal + */ +typedef enum ALT_I2C_TX_ABORT_CAUSE_e +{ + ALT_I2C_TX_ABORT_CAUSE_7B_ADDR_NOACK = 1UL << 0, + /*!< Master Abort 7 Bit Address - If set (1), + * Master is in 7-bit addressing mode and the + * address sent was not acknowledged by any + * slave. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_10ADDR1_NOACK = 1UL << 1, + /*!< Master Abort 10 Bit Address Byte 1 - If set + * (1), Master is in 10-bit address mode and the + * first 10-bit address byte was not + * acknowledged by any slave. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_10ADDR2_NOACK = 1UL << 2, + /*!< Master Abort 10 Bit Address Byte 2 - If set + * (1), Master is in 10-bit address mode and the + * second address byte of the 10-bit address was + * not acknowledged by any slave + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_TXDATA_NOACK = 1UL << 3, + /*!< Master Abort TX NOACK Bit - If set (1), + * Master has received an acknowledgement for + * the address, but when it sent data byte(s) + * following the address, it did not receive an + * acknowledge from the remote slave(s). This is + * a master-mode only bit. + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_GCALL_NOACK = 1UL << 4, + /*!< Master Abort GC Noack Bit - If set (1), I2C + * controller in master mode sent a General Call + * and no slave on the bus acknowledged the + * General Call. + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_GCALL_RD = 1UL << 5, + /*!< Master Abort GC Read Bit - If set (1), I2C + * controller in master mode sent a General Call + * but the user programmed the byte following + * the General Call to be a read from the bus + * (IC_DATA_CMD[9] is set to 1). + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_HS_ACKDET = 1UL << 6, + /*!< Master HS MC Ack - If set (1), Master is in + * High Speed mode and the High Speed Master + * code was acknowledged (wrong behavior). + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_SBYTE_ACKDET = 1UL << 7, + /*!< Master Abort START Byte - If set (1), Master + * has sent a START Byte and the START Byte was + * acknowledged (wrong behavior). + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_HS_NORSTRT = 1UL << 8, + /*!< Master HS Restart Disabled - If set (1), the + * restart is disabled (IC_RESTART_EN bit + * (IC_CON[5]) = 0) and the user is trying to + * use the master to transfer data in High Speed + * mode. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_SBYTE_NORSTRT = 1UL << 9, + /*!< Master Abort START No Restart - To clear, the + * source of the ABRT_SBYTE_NORSTRT must be + * fixed first; restart must be enabled + * (IC_CON[5]=1), the SPECIAL bit must be + * cleared (IC_TAR[11]), or the GC_OR_START bit + * must be cleared (IC_TAR[10]). Once the source + * of the ABRT_SBYTE_NORSTRT is fixed, then this + * bit can be cleared in the same manner as + * other bits in this register. If the source of + * the ABRT_SBYTE_NORSTRT is not fixed before + * attempting to clear this bit, bit 9 clears + * for one cycle and then gets re-asserted. + * + * If set (1), the restart is disabled + * (IC_RESTART_EN bit (IC_CON[5]) = 0) and the + * user is trying to send a START Byte. + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_10B_RD_NORSTRT = 1UL << 10, + /*!< Master Abort 10 Bit No Restart - If set (1), + * the restart is disabled (IC_RESTART_EN bit + * (IC_CON[5]) = 0) and the master sends a read + * command in 10-bit addressing mode. + * + * Role of I2C: Master Receiver. + */ + ALT_I2C_TX_ABORT_CAUSE_MST_DIS = 1UL << 11, + /*!< Master Operation with Master Disabled - If set + * (1), user tries to initiate a Master + * operation with the Master mode disabled. + * + * Role of I2C: Master or Slave-Receiver. + */ + ALT_I2C_TX_ABORT_CAUSE_ARB_LOST = 1UL << 12, + /*!< Master Abort Arbitration Lost - If set (1), + * master has lost arbitration, or if + * IC_TX_ABRT_SOURCE[14] is also set, then the + * slave transmitter has lost arbitration. Note: + * I2C can be both master and slave at the same + * time. + * + * Role of I2C: Master or Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLVFLUSH_TXFIFO = 1UL << 13, + /*!< Slave Abort Flush TXFIFO - If set (1), Slave + * has received a read command and some data + * exists in the TX FIFO so the slave issues a + * TX_ABRT interrupt to flush old data in TX + * FIFO. + * + * Role of I2C: Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLV_ARBLOST = 1UL << 14, + /*!< Slave Abort Arbitration Lost - If set (1), + * Slave lost the bus while transmitting data to + * a remote master. IC_TX_ABRT_SOURCE[12] is set + * at the same time. + * + * Note: Even though the slave never owns the + * bus, something could go wrong on the + * bus. This is a fail safe check. For instance, + * during a data transmission at the low-to-high + * transition of SCL, if what is on the data bus + * is not what is supposed to be transmitted, + * then DW_apb_i2c no longer own the bus. + * + * Role of I2C: Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLVRD_INTX = 1UL << 15 + /*!< Slave Abort Read TX - If set (1), + * when the processor side responds to a + * slave mode request for data to be transmitted + * to a remote master and user writes a 1 in CMD + * (bit 8) of IC_DATA_CMD register. + * + * Role of I2C: Slave-Transmitter. + */ +} ALT_I2C_TX_ABORT_CAUSE_t; + +/*! + * This type defines a structure for configuration of the SCL high and low counts + * to ensure proper I/O timing with the device interface. + * + * The SCL count values are only relevant if the I2C controller is enabled to as + * an I2C master. The SCL count values are ignored when the I2C controller is + * enabled as an I2C slave. + * + * See: Clock Frequency Configuration section of Chapter 20. I2C + * Controller in the Cyclone V Device Handbook Volume 3: Hard + * Processor System Technical Reference Manual for a complete discussion + * of calculation of the proper SCL clock high and low times. + */ +typedef struct ALT_I2C_MASTER_CONFIG_s +{ + ALT_I2C_ADDR_MODE_t addr_mode; + /*!< The address mode (7 or 10 bit) when + * acting as a master. + */ + bool restart_enable; + /*!< This setting determines whether RESTART + * conditions may be sent when acting as a + * master. When the \e restart_enable is + * false, the I2C controller master is + * incapable of performing the following + * functions: + * * Sending a START BYTE + * * Performing any high-speed mode + * operation + * * Performing direction changes in + * combined format mode + * * Performing a read operation with a + * 10-bit address + */ + ALT_I2C_SPEED_t speed_mode; + /*!< The speed mode of the I2C operation. + */ + uint16_t ss_scl_hcnt; + /*!< The SCL clock high-period count for + * standard speed. + */ + uint16_t ss_scl_lcnt; + /*!< The SCL clock low-period count for + * standard speed. + */ + uint16_t fs_scl_hcnt; + /*!< The SCL clock high-period count for fast + * speed. + */ + uint16_t fs_scl_lcnt; + /*!< The SCL clock low-period count for fast + * speed. + */ + uint8_t fs_spklen; + /*!< The duration, measured in ic_clk cycles, + * of the longest spike that is filtered out + * by the spike suppression logic when the + * component is operating in SS or FS modes. + */ +} ALT_I2C_MASTER_CONFIG_t; + +/*! + * This type defines a structure for configuration of the I2C controller when it + * is operating in slave mode. + */ +typedef struct ALT_I2C_SLAVE_CONFIG_s +{ + ALT_I2C_ADDR_MODE_t addr_mode; /*!< The address mode (7 or 10 bit) when + * acting as a slave. + */ + uint32_t addr; /*!< The slave address to which the I2C + * controller responds when acting as a + * slave. + */ + bool nack_enable; /*!< Enable generation of a NACK. when the + * I2C controller is a + * slave-receiver. If \b true, it can + * only generate a NACK after a data + * byte is received; hence, the data + * transfer is aborted and the data + * received is not pushed onto the + * receive buffer. When \b false, it + * generates NACK/ACK, depending on + * normal criteria. + * * \b true = generate NACK after data + * byte received + * * \b false = generate NACK/ACK normally + */ +} ALT_I2C_SLAVE_CONFIG_t; + +/*! + * Initialize the specified I2C controller instance for use and return a device + * handle referencing it. + * + * \param i2c + * The HPS I2C controller instance to initialize. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Initialization process: + * * Initialize internal driver state + * * Check clock setup (ALT_CLK_L4_SP) + * * Take I2C instance out of reset (System Manager) + * * Disable and clear all interrupts and status conditions + * * Setup and initialize any expected initial I2C controller state + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_init(const ALT_I2C_CTLR_t i2c, ALT_I2C_DEV_t *i2c_dev); + +/*! + * Reset the specified I2C controller instance for use. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Reset process: + * * Disable controller + * * Initialize internal driver state + * * Check clock setup (ALT_CLK_L4_SP) + * * Take I2C instance out of reset (System Manager) + * * Disable and clear all interrupts and status conditions + * * Setup and initialize any expected initial I2C controller state + * * Enable controller + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_reset(ALT_I2C_DEV_t * i2c_dev); + +/*! + * Uninitialize the I2C controller referenced by the \e i2c_dev handle. + * + * This function attempts to gracefully shutdown the I2C controller by waiting for + * any inpcomplete transactions to finish and then putting the I2C controller into + * reset. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_uninit(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Disables the I2C controller. + * + * When the I2C controller is disabled, the following occurs: + * * The TX FIFO and RX FIFO get flushed. + * * The I2C interrupt status conditions remain active until the I2C controller + * goes into IDLE state. + * + * If the controller is transmitting, it stops as well as deletes the contents of + * the transmit buffer after the current transfer is complete. If the module is + * receiving, the controller stops the current transfer at the end of the current + * byte and does not acknowledge the transfer. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE = 0 + * Follow the procedure in section 3.8.3 Disabling DW_apb_i2c of the DW Databook. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_disable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Enables the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_enable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE if the I2C controller is enabled. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_is_enabled(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Gets the current configuration of the I2C controller when operating in master + * mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * [out] Pointer to a ALT_I2C_MASTER_CONFIG_t structure for holding + * the returned I2C master mode configuration parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t* cfg); + +/*! + * Sets the configuration of the I2C controller with operational parameters for + * operating in master mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * Pointer to a ALT_I2C_MASTER_CONFIG_t structure holding the desired + * I2C master mode operational parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg); + +/*! + * This is a utility function that returns the speed based on parameters of the + * I2C master configuration. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * A pointer to the master confugurations. + * + * \param speed_in_hz + * [out] Speed (Hz) of the I2C bus currently configured at. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_master_config_speed_get(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg, + uint32_t * speed_in_hz); + +/*! + * This is a utility function that computes parameters for the I2C master + * configuration that best matches the speed requested. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * A pointer to the master confugurations. + * + * \param speed_in_hz + * Speed (Hz) of the I2C bus to configure. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_speed_set(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t * cfg, + uint32_t speed_in_hz); + +/*! + * Definition included for backwards compatibility. + */ +#define alt_i2c_cfg_to_speed(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_get((i2c_dev), (cfg), (speed_in_hz)) + +/*! + * Definition included for backwards compatibility. + */ +#define alt_i2c_speed_to_cfg(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_set((i2c_dev), (cfg), (speed_in_hz)) + +/*! + * Gets the current configuration of the I2C controller when operating in slave + * mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * [out] Pointer to a ALT_I2C_SLAVE_CONFIG_t structure for holding + * the returned I2C slave mode configuration parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_SLAVE_CONFIG_t* cfg); + +/*! + * Sets the configuration of the I2C controller with operational parameters for + * operating in slave mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * Pointer to a ALT_I2C_SLAVE_CONFIG_t structure holding the desired + * I2C slave mode operational parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_SLAVE_CONFIG_t* cfg); + +/*! \addtogroup ALT_I2C_SDA_HOLD SDA Hold Time Configuration + * + * The I2C protocol specification requires 300ns of hold time on the SDA signal in + * standard and fast speed modes. Board delays on the SCL and SDA signals can mean + * that the hold-time requirement is met at the I2C master, but not at the I2C + * slave (or vice-versa). Because each system may encounter differing board signal + * delays, the I2C controller provides the capability to adjust of the SDA + * hold-time. + * + * The functions in this section provide software configuration of SDA hold time + * for the I2C controller. + * + * @{ + */ + +/*! + * Gets the currently configured value for the SDA hold time in I2C controller + * clock (\ref ALT_CLK_L4_SP) clock ticks. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param hold_time + * [out] The configured SDA hold time in \ref ALT_CLK_L4_SP clock + * ticks. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_sda_hold_time_get(ALT_I2C_DEV_t *i2c_dev, + uint16_t *hold_time); + +/*! + * Sets the configured value for the SDA hold time in terms of I2C controller + * clock (\ref ALT_CLK_L4_SP) clock ticks. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param hold_time + * The SDA hold time in \ref ALT_CLK_L4_SP clock ticks. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_SDA_HOLD is 16 bits wide. hold_time must be in range 0..65535. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_sda_hold_time_set(ALT_I2C_DEV_t *i2c_dev, + const uint16_t hold_time); + +/*! @} */ + +/*! + * Gets the current operational mode of the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mode + * [out] The current operational mode enabled for the I2C + * controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_op_mode_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MODE_t* mode); + +/*! + * Sets the operational mode of the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mode + * The operational mode to enable for the I2C controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_op_mode_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MODE_t mode); + +/*! + * Returns ALT_E_TRUE if the I2C controller is busy. The I2C controller is busy if + * either the Slave Finite State Machine (FSM) is not in the IDLE state or the + * Master Finite State Machine (FSM) is not in the IDLE state. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.ACTIVITY == 1 + * NOTE: IC_STATUS[0] that is, the ACTIVITY bit is the OR of SLV_ACTIVITY and + * MST_ACTIVITY bits. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_is_busy(ALT_I2C_DEV_t *i2c_dev); + +/*! + * This function reads a single data byte from the receive FIFO. + * + * This function is used to perform low level access to the data bytes + * received by the I2C controller and buffered in the receive FIFO. It + * may be used by master-receivers or slave receivers. + * + * This function does not check for valid data in the receive FIFO + * beforehand and may cause an underflow if improperly used. It is + * meant to be called from a context where preconditions have been + * previously asserted such as in the implementation of the + * alt_i2c_slave_receive() or alt_i2c_master_receive() function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param val + * [out] The single data byte read from the receive FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_read(ALT_I2C_DEV_t *i2c_dev, uint8_t *val); + +/*! + * This function writes a single data byte to the transmit FIFO. + * + * This function is used to perform low level writes of data to the + * transmit FIFO for transmission by the I2C controller. It may be + * used by slave receivers. + * + * This function does not check whether the transmit FIFO is full or + * not beforehand and may cause an overflow if improperly used. It is + * meant to be called from a context where preconditions have been + * previously asserted such as in the implementation of the + * alt_i2c_slave_transmit() function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param val + * The data byte to write to the transmission FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_write(ALT_I2C_DEV_t *i2c_dev, const uint8_t val); + +/*! + * This function acts in the role of a slave-receiver by receiving a single data + * byte from the I2C bus in response to a write command from the master. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is data in the RX FIFO to + * accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * [out] A pointer to a buffer to contain the received data byte. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_receive(ALT_I2C_DEV_t *i2c_dev, + uint8_t *data); + +/*! + * This function acts in the role of a slave-transmitter by transmitting a single + * data byte to the I2C bus in response to a read request from the master. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough space in the TX + * FIFO to accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * The data byte to transmit. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_transmit(ALT_I2C_DEV_t *i2c_dev, + const uint8_t data); + +/*! + * This function acts in the role of a slave-transmitter by transmitting data in + * bulk to the I2C bus in response to a series of read requests from a master. + * + * In the standard I2C protocol, all transactions are single byte transactions and + * the slave responds to a remote master read request by writing one byte into the + * slave's TX FIFO. When a slave (slave-transmitter) is issued with a read request + * from the remote master (master-receiver), at a minimum there should be at least + * one entry placed into the slave-transmitter's TX FIFO. The I2C controller is + * capable of handling more data in the TX FIFO so that subsequent read requests + * can receive that data without raising an interrupt or software having to poll + * to request more data. This eliminates overhead latencies from being incurred by + * servicing the interrupt or polling for data requests each time had there been a + * restriction of having only one entry placed in the TX FIFO. + * + * If the remote master acknowledges the data sent by the slave-transmitter and + * there is no data in the slave's TX FIFO, the I2C controller raises the read + * request interrupt and waits for data to be written into the TX FIFO before it + * can be sent to the remote master. + * + * If the programmer knows in advance that the master is requesting a packet of \e + * n bytes, then when another master request for data is received, the TX FIFO + * could be written with \e n number bytes and the master receives it as a + * continuous stream of data. For example, the slave continues to send data to the + * master as long as the master is acknowledging the data sent and there is data + * available in the TX FIFO. There is no need to hold the SCL line low or to issue + * READ request again. + * + * If the remote master is to receive \e n bytes from the slave but the programmer + * wrote a number of bytes larger than \e n to the TX FIFO, then when the slave + * finishes sending the requested \e n bytes, it clears the TX FIFO and ignores + * any excess bytes. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough space in the TX + * FIFO to accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * A pointer to the data buffer to transmit. + * + * \param size + * The size of the data buffer in bytes to place in the TX FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * See: Section Slave-Transfer Operation for Bulk Transfers of the DW + * Databook for details of implementation and error conditions that may occur. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_bulk_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size); + +/*! + * This function returns the current target address. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param target_addr + * [out] The 7 or 10 bit slave target address. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_i2c_master_target_get(ALT_I2C_DEV_t * i2c_dev, uint32_t * target_addr); + +/*! + * This function updates the target slave address for any upcoming I2C bus IO. + * + * This API is not suitlabe for being called in an interrupt context as it + * will wait for the TX FIFO to flush before applying the changes. If the TX + * FIFO is known to be empty and the controller idle, then it can be safely + * called. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param target_addr + * The 7 or 10 bit slave target address. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_i2c_master_target_set(ALT_I2C_DEV_t * i2c_dev, uint32_t target_addr); + +/*! + * This function acts in the role of a master-transmitter by issuing a write + * command and transmitting data to the I2C bus. + * + * This API is not suitable for being called in an interrupt context as it may + * wait for certain controller states before completing. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * A pointer to a data buffer to transmit + * + * \param size + * The size of the data buffer in bytes to place in the TX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function acts in the role of a master-receiver by receiving one or more + * data bytes transmitted from a slave in response to read requests issued from + * this master. + * + * This function causes the master to issue the required number of read requests + * to the slave and read the received data bytes from the Rx FIFO. + * + * The \e issue_restart and \e issue_stop parameters apply to the final read + * request transaction in the \e num_data_entries sequence required to fulfill the + * aggregate receive request. + * + * This API is not suitable for being called in an interrupt context as it may + * wait for certain controller states before completing. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * [out] The data buffer to receive the requested \e size bytes. + * + * \param size + * The size of the data buffer to read from the RX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_receive(ALT_I2C_DEV_t *i2c_dev, + void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function causes the I2C controller master to issue a READ request on the + * bus. This function is typically used during master-receiver transfers. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Write IC_DATA_CMD.CMD = 1 (read request). IC_DATA_CMD.DAT is + * written with "don't care" values as these bits are ignored by the + * I2C controller . + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_issue_read(ALT_I2C_DEV_t *i2c_dev, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function causes the I2C controller master to issue a send byte on the + * bus. This function is typically used during master-transmitter/slave-transmitter + * transfers. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param value + * The data item to be transmitted. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Write IC_DATA_CMD.CMD = 0 (write request). + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_issue_write(ALT_I2C_DEV_t *i2c_dev, + const uint8_t value, + const bool issue_restart, + const bool issue_stop); + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_GEN_CALL General Call + * + * The functions in this group support General Call addresses. + * + * The general call address is for addressing every device connected to the I2C + * bus at the same time. However, if a device does not need any of the data + * supplied within the general call structure, it can ignore this address by not + * issuing an acknowledgment. If a device does require data from a general call + * address, it acknowledges this address and behaves as a slave-receiver. The + * master does not actually know how many devices acknowledged if one or more + * devices respond. The second and following bytes are acknowledged by every + * slave-receiver capable of handling this data. A slave who cannot process one of + * these bytes must ignore it by not-acknowledging. If one or more slaves + * acknowledge, the not-acknowledge will not be seen by the master. + * + * The functions in this group do not provide any general call functional command + * interpretation or implementation (e.g. software reset). + * + * @{ + */ + +/*! + * This function acts in the role of a master-transmitter by issuing a general + * call command to all devices connected to the I2C bus. + * + * The \e issue_restart and \e issue_stop parameters apply to the final write + * transaction in the \e num_data_entries byte transmission sequence. + * + * The I2C controller must be in master mode before calling this function. + * + * The target slave address will be modified by this function. Call + * alt_i2c_master_target_set() to reset the slave target address for + * subsequent IO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * An array of data byte(s) to transmit. + * + * \param num_data_entries + * The number of entries (bytes) in \e data to place in the TX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_general_call(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * Disables the I2C controller from responding to a General Call address. The + * controller will respond with a NACK and no General Call status conditions or + * interrupts are generated. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_disable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Enables the I2C controller to respond with an ACK when it receives a General + * Call address. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_enable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE if the I2C controller is enabled to respond to General Call + * addresses. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_is_enabled(ALT_I2C_DEV_t *i2c_dev); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_INT Interrupt and Status Conditions + * + * The functions in this group provide management for the I2C controller status + * conditions and interrupts. + * + * Each I2C controller has a single combined interrupt output (\b + * ALT_INT_INTERRUPT_I2Cn_IRQ). The following events can generate an + * interrupt: + * * General Call Address Received + * * Start or Restart Condition Occurred + * * Stop Condition Occurred + * * I2C Controller Activity + * * Receive Done + * * Transmit Abort + * * Read Request + * * Transmit Buffer Empty + * * Transmit Overflow + * * Receive Buffer Full + * * Receive Overflow + * * Receive Underflow + * + * These interrupt status conditions may be monitored either by polling their + * status or by configuring interrupt handlers using the HWLIB Interrupt + * Controller API. + * + * Functions to get the current status, enable or disable (i.e. mass or unmask), + * and clear interrupt status conditions for the I2C controller are defined in + * this section. + * + * @{ + */ + +/*! + * Returns the current I2C controller interrupt status conditions. + * + * This function returns the current value of the I2C controller interrupt status + * register value which reflects the current I2C controller status conditions that + * are not disabled (i.e. masked). + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param status + * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t + * interrupt and status conditions. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_INTR_STAT + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status); + +/*! + * Returns the I2C controller raw interrupt status conditions irrespective of + * the interrupt status condition enablement state. + * + * This function returns the current value of the I2C controller raw interrupt + * status register value which reflects the current I2C controller status + * conditions regardless of whether they are disabled (i.e. masked) or not. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param status + * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t + * interrupt and status conditions. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_INTR_STAT + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_raw_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status); + +/*! + * Clears the specified I2C controller interrupt status conditions identified + * in the mask. + * + * This function clears one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the QSPI interrupt status conditions to clear. \e mask + * is a mask of logically OR'ed \ref ALT_I2C_STATUS_t values that + * designate the status conditions to clear. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_clear(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Disable the specified I2C controller interrupt status conditions identified in + * the mask. + * + * This function disables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of enabling it as a contributor to the \b + * ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. The function + * alt_i2c_int_enable() is used to enable status source conditions. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the status conditions to disable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_I2C_STATUS_t values that designate the status conditions to + * disable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_disable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Enable the specified I2C controller interrupt status conditions identified in + * the mask. + * + * This function enables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of disabling it as a contributor to the \b + * ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. The function + * alt_i2c_int_disable() is used to disable status source conditions. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the status conditions to enable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_I2C_STATUS_t values that designate the status conditions to + * enable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_enable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Gets the cause of I2C transmission abort. A I2C transmission abort indicates + * that the I2C transmitter is unable to complete the intended actions on the + * contents of the transmit FIFO. This situation can occur both as an I2C master + * or an I2C slave, and is referred to as a "transmit abort". + * + * The returned value of this function is the value of the IC_TX_ABRT_SOURCE + * register which indicates the cause why the transmit abort occurred. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cause + * [out] A pointer to a bit mask of the \ref ALT_I2C_TX_ABORT_CAUSE_t + * causes of the transmission abort. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_ABRT_SOURCE + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_abort_cause_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_TX_ABORT_CAUSE_t *cause); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_RX_FIFO RX FIFO Management + * + * The receive FIFO has a configurable threshold value that controls the level of + * entries (or above) that sets the RX_FULL status condition and triggers an + * interrupt. The valid range is 0 - (ALT_I2C_RX_FIFO_NUM_ENTRIES-1), with the + * additional restriction that I2C controller does not allow this value to be set + * to a value larger than the depth of the buffer. If an attempt is made to do + * that, the actual value set will be the maximum depth of the buffer. A value of + * 0 sets the threshold for 1 entry, and a value of (ALT_I2C_RX_FIFO_NUM_ENTRIES-1) + * sets the threshold for ALT_I2C_RX_FIFO_NUM_ENTRIES entries. + * + * @{ + */ + +/*! + * The number of entries (depth) of the I2C controller receive FIFO. + */ +#define ALT_I2C_RX_FIFO_NUM_ENTRIES 64 + +/*! + * Returns ALT_E_TRUE when the receive FIFO is empty. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.RFNE == 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE when the receive FIFO is completely full. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.RFF == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns the number of valid entries in the receive FIFO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param num_entries + * [out] The number of entries in the receive FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RXFLR.RXFLR + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries); + +/*! + * Gets the current receive FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The current threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RX_TL.RX_TL + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold); + +/*! + * Sets the current receive FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RX_TL.RX_TL = threshold + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_TX_FIFO TX FIFO Management + * + * The transmit FIFO has a configurable threshold value that controls the level of + * entries (or below) that sets the TX_EMPTY status condition and triggers an + * interrupt. The valid range is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES-1), with the + * additional restriction that I2C controller does not allow this value to be set + * to a value larger than the depth of the buffer. If an attempt is made to do + * that, the actual value set will be the maximum depth of the buffer. A value of + * 0 sets the threshold for 0 entries, and a value of (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) + * sets the threshold for (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) entries. + * + * @{ + */ + +/*! + * The number of entries (depth) of the I2C controller transmit FIFO. + */ +#define ALT_I2C_TX_FIFO_NUM_ENTRIES 64 + +/*! + * Returns ALT_E_TRUE when the transmit FIFO is empty. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.TFE == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE when the transmit FIFO is completely full. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.TFNF == 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns the number of valid entries in the transmit FIFO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param num_entries + * [out] The number of entries in the transmit FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TXFLR.TXFLR + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries); + +/*! + * Gets the current transmit FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The current threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_TL.TX_TL + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold); + +/*! + * Sets the current transmit FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_TL.TX_TL = threshold + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_DMA DMA Interface + * + * The DMA interface has a configurable threshold value that controls the + * level of entries that triggers the burst handshaking request used for DMA + * integration. + * + * For the TX threshold, if the number of entries in the TX FIFO is at or + * below the set threshold, a DMA handshaking request will be made. The valid + * range for the TX threshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1). + * + * For the RX threshold, if the number of entries in the RX FIFO is above the + * set threshold, a DMA handshaking request will be made. The valid range for + * the RX treshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1). + * + * Having a higher threshold can improve the AXI bus utilization at the + * expense of the likelyhoold of overflow / underflow conditions. + * @{ + */ + +/*! + * Gets the current RX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold); + +/*! + * Sets the current RX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold); + +/*! + * Gets the current TX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold); + +/*! + * Sets the current TX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold); + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_I2C_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h new file mode 100644 index 0000000000..004fd3188c --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h @@ -0,0 +1,533 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_INT_COMMON_H__ +#define __ALT_INT_COMMON_H__ + +#include "hwlib.h" +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup INT_COMMON Interrupt Controller Common Definitions + * + * This module contains the definitions common to the Interrupt Controller + * Low-Level API and Interrupt Controller Manager Interface. + * + * @{ + */ + +/*! + * This type definition enumerates all the interrupt identification types. + */ +typedef enum ALT_INT_INTERRUPT_e +{ + ALT_INT_INTERRUPT_SGI0 = 0, /*!< # */ + ALT_INT_INTERRUPT_SGI1 = 1, /*!< # */ + ALT_INT_INTERRUPT_SGI2 = 2, /*!< # */ + ALT_INT_INTERRUPT_SGI3 = 3, /*!< # */ + ALT_INT_INTERRUPT_SGI4 = 4, /*!< # */ + ALT_INT_INTERRUPT_SGI5 = 5, /*!< # */ + ALT_INT_INTERRUPT_SGI6 = 6, /*!< # */ + ALT_INT_INTERRUPT_SGI7 = 7, /*!< # */ + ALT_INT_INTERRUPT_SGI8 = 8, /*!< # */ + ALT_INT_INTERRUPT_SGI9 = 9, /*!< # */ + ALT_INT_INTERRUPT_SGI10 = 10, /*!< # */ + ALT_INT_INTERRUPT_SGI11 = 11, /*!< # */ + ALT_INT_INTERRUPT_SGI12 = 12, /*!< # */ + ALT_INT_INTERRUPT_SGI13 = 13, /*!< # */ + ALT_INT_INTERRUPT_SGI14 = 14, /*!< # */ + ALT_INT_INTERRUPT_SGI15 = 15, + /*!< + * Software Generated Interrupts (SGI), 0 - 15. + * * All interrupts in this group are software triggered. + */ + + ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL = 27, /*!< # */ + ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE = 29, /*!< # */ + ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */ + /*!< + * Private Peripheral Interrupts (PPI) for the Global Timer, per CPU + * private timer, and watchdog timer. + * * All interrupts in this group are edge triggered. + */ + + ALT_INT_INTERRUPT_CPU0_PARITYFAIL = 32, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC = 33, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB = 34, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG = 35, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA = 36, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB = 37, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG = 39, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA = 40, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS0 = 41, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS1 = 42, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS2 = 43, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS3 = 44, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS4 = 45, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS5 = 46, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS6 = 47, + /*!< + * Interrupts sourced from CPU0. + * + * The ALT_INT_INTERRUPT_CPU0_PARITYFAIL interrupt combines the + * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts + * for CPU0. + * + * * PARITYFAIL interrupts in this group are edge triggered. + * * DEFFLAGS interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_CPU1_PARITYFAIL = 48, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC = 49, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB = 50, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG = 51, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA = 52, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB = 53, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG = 55, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA = 56, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS0 = 57, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS1 = 58, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS2 = 59, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS3 = 60, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS4 = 61, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS5 = 62, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS6 = 63, + /*!< + * Interrupts sourced from CPU1. + * + * The ALT_INT_INTERRUPT_CPU1_PARITYFAIL interrupt combines the + * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts + * for CPU1. + * + * * PARITYFAIL interrupts in this group are edge triggered. + * * DEFFLAGS interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_SCU_PARITYFAIL0 = 64, /*!< # */ + ALT_INT_INTERRUPT_SCU_PARITYFAIL1 = 65, /*!< # */ + ALT_INT_INTERRUPT_SCU_EV_ABORT = 66, + /*!< + * Interrupts sourced from the Snoop Control Unit (SCU). + * * All interrupts in this group are edge triggered. + */ + + ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ = 67, /*!< # */ + ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ = 68, /*!< # */ + ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */ + ALT_INT_INTERRUPT_L2_COMBINED_IRQ = 70, + /*!< + * Interrupts sourced from the L2 Cache Controller. + * + * The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache + * controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR, + * ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts. + * Consult the L2C documentation for information on these interrupts. + * + * * ECC interrupts in this group are edge triggered. + * * Other interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ = 71, + /*!< + * Interrupts sourced from the SDRAM Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_F2S_FPGA_IRQ0 = 72, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ1 = 73, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ2 = 74, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ3 = 75, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ4 = 76, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ5 = 77, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ6 = 78, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ7 = 79, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ8 = 80, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ9 = 81, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 = 82, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 = 83, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 = 84, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 = 85, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 = 86, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 = 87, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 = 88, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 = 89, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 = 90, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 = 91, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 = 92, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 = 93, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 = 94, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 = 95, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 = 96, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 = 97, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 = 98, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 = 99, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135, + /*!< + * Interrupt request from the FPGA logic, 0 - 63. + * * Trigger type depends on the implementation in the FPGA. + */ + + ALT_INT_INTERRUPT_DMA_IRQ0 = 136, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ1 = 137, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ2 = 138, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ3 = 139, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ4 = 140, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ5 = 141, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ6 = 142, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ7 = 143, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ_ABORT = 144, /*!< # */ + ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ = 145, /*!< # */ + ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146, + /*!< + * Interrupts sourced from the DMA Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_EMAC0_IRQ = 147, /*!< # */ + ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ = 148, /*!< # */ + ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */ + ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ = 150, /*!< # */ + ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151, + /*!< + * Interrupts sourced from the Ethernet MAC 0 (EMAC0). + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_EMAC1_IRQ = 152, /*!< # */ + ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ = 153, /*!< # */ + ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */ + ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ = 155, /*!< # */ + ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156, + /*!< + * Interrupts sourced from the Ethernet MAC 1 (EMAC1). + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_USB0_IRQ = 157, /*!< # */ + ALT_INT_INTERRUPT_USB0_ECC_CORRECTED = 158, /*!< # */ + ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159, + /*!< + * Interrupts sourced from the USB OTG 0. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_USB1_IRQ = 160, /*!< # */ + ALT_INT_INTERRUPT_USB1_ECC_CORRECTED = 161, /*!< # */ + ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162, + /*!< + * Interrupts sourced from the USB OTG 1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_CAN0_STS_IRQ = 163, /*!< # */ + ALT_INT_INTERRUPT_CAN0_MO_IRQ = 164, /*!< # */ + ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ = 165, /*!< # */ + ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166, + /*!< + * Interrupts sourced from the CAN Controller 0. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_CAN1_STS_IRQ = 167, /*!< # */ + ALT_INT_INTERRUPT_CAN1_MO_IRQ = 168, /*!< # */ + ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ = 169, /*!< # */ + ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170, + /*!< + * Interrupts sourced from the CAN Controller 1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_SDMMC_IRQ = 171, /*!< # */ + ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED = 172, /*!< # */ + ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */ + ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED = 174, /*!< # */ + ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175, + /*!< + * Interrupts sourced from the SDMMC Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_NAND_IRQ = 176, /*!< # */ + ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ = 177, /*!< # */ + ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */ + ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ = 179, /*!< # */ + ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */ + ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ = 181, /*!< # */ + ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182, + /*!< + * Interrupts sourced from the NAND Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_QSPI_IRQ = 183, /*!< # */ + ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ = 184, /*!< # */ + ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185, + /*!< + * Interrupts sourced from the QSPI Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */ + ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */ + ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */ + ALT_INT_INTERRUPT_SPI3_IRQ = 189, + /*!< + * Interrupts sourced from the SPI Controllers 0 - 3. + * SPI0_IRQ corresponds to SPIM0. SPI1_IRQ corresponds to SPIM1. + * SPI2_IRQ corresponds to SPIS0. SPI3_IRQ corresponds to SPIS1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */ + ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */ + ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */ + ALT_INT_INTERRUPT_I2C3_IRQ = 193, + /*!< + * Interrupts sourced from the I2C Controllers 0 - 3. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_UART0 = 194, /*!< # */ + ALT_INT_INTERRUPT_UART1 = 195, + /*!< + * Interrupts sourced from the UARTs 0 - 1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */ + ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */ + ALT_INT_INTERRUPT_GPIO2 = 198, + /*!< + * Interrupts sourced from the GPIO 0 - 2. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */ + ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */ + ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */ + ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202, + /*!< + * Interrupts sourced from the Timer controllers. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */ + ALT_INT_INTERRUPT_WDOG1_IRQ = 204, + /*!< + * Interrupts sourced from the Watchdog Timers 0 - 1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_CLKMGR_IRQ = 205, + /*!< + * Interrupts sourced from the Clock Manager. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206, + /*!< + * Interrupts sourced from the Clock Manager MPU Wakeup. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207, + /*!< + * Interrupts sourced from the FPGA Manager. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */ + ALT_INT_INTERRUPT_NCTIIRQ1 = 209, + /*!< + * Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ = 210, /*!< # */ + ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211 + /*!< + * Interrupts sourced from the On-chip RAM. + * * All interrupts in this group are level triggered. + */ + +} ALT_INT_INTERRUPT_t; + +/*! + * This is the CPU target type. It is used to specify a set of CPUs on the + * system. If only bit 0 is set then it specifies a set of CPUs containing + * only CPU 0. Multiple CPUs can be specified by setting the appropriate bit + * up to the number of CPUs on the system. + */ +typedef uint32_t alt_int_cpu_target_t; + +/*! + * This type definition enumerates all the interrupt trigger types. + */ +typedef enum ALT_INT_TRIGGER_e +{ + /*! + * Edge triggered interrupt. This applies to Private Peripheral Interrupts + * (PPI) and Shared Peripheral Interrupts (SPI) only, with interrupt IDs + * 16 - 1019. + */ + ALT_INT_TRIGGER_EDGE, + + /*! + * Level triggered interrupt. This applies to Private Peripheral + * Interrupts (PPI) and Shared Peripheral Interrupts (SPI) only, with + * interrupt IDs 16 - 1019. + */ + ALT_INT_TRIGGER_LEVEL, + + /*! + * Software triggered interrupt. This applies to Software Generated + * Interrupts (SGI) only, with interrupt IDs 0 - 15. + */ + ALT_INT_TRIGGER_SOFTWARE, + + /*! + * All triggering types except for those in the Shared Peripheral Interrupts + * (SPI) F2S FPGA family interrupts can be determined by the system + * automatically. In all functions which ask for the triggering type, the + * ALT_INT_TRIGGER_AUTODETECT can be used to select the correct trigger + * type for all non F2S interrupt types. + */ + ALT_INT_TRIGGER_AUTODETECT, + + /*! + * The interrupt triggering information is not applicable. This is possibly + * due to querying an invalid interrupt identifier. + */ + ALT_INT_TRIGGER_NA +} +ALT_INT_TRIGGER_t; + +/*! + * This type definition enumerates all the target list filter options. This is + * used by the trigger Software Generated Interrupt (SGI) feature to issue a + * SGI to the specified processor(s) in the system. Depending on the target + * list filter and the target list, interrupts can be routed to any + * combinations of CPUs. + */ +typedef enum ALT_INT_SGI_TARGET_e +{ + /*! + * This filter list uses the target list parameter to specify which CPUs + * to send the interrupt to. If target list is 0, no interrupts are sent. + */ + ALT_INT_SGI_TARGET_LIST, + + /*! + * This filter list sends the interrupt all CPUs except the current CPU. + * The target list parameter is ignored. + */ + ALT_INT_SGI_TARGET_ALL_EXCL_SENDER, + + /*! + * This filter list sends the interrupt to the current CPU only. The + * target list parameter is ignored. + */ + ALT_INT_SGI_TARGET_SENDER_ONLY +} +ALT_INT_SGI_TARGET_t; + +/*! + * Extracts the CPUID field from the ICCIAR register. + */ +#define ALT_INT_ICCIAR_CPUID_GET(icciar) ((icciar >> 10) & 0x7) + +/*! + * Extracts the ACKINTID field from the ICCIAR register. + */ +#define ALT_INT_ICCIAR_ACKINTID_GET(icciar) (icciar & 0x3FF) + +/*! + * The callback to use when an interrupt needs to be serviced. + * + * \param icciar The Interrupt Controller CPU Interrupt + * Acknowledgement Register value (ICCIAR) value + * corresponding to the current interrupt. + * + * \param context The user provided context. + */ +typedef void (*alt_int_callback_t)(uint32_t icciar, void * context); + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_INT_COMMON_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h new file mode 100644 index 0000000000..2ead15df86 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h @@ -0,0 +1,156 @@ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_MPUSCU_H__ +#define __ALT_MPUSCU_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +/************************************************************************************************************/ +/* alt_mpuscu.h */ +/* */ +/* Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog */ +/* Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor. */ +/* */ +/************************************************************************************************************/ + +#ifndef ALT_HPS_ADDR +#define ALT_HPS_ADDR 0x00 +#endif + + +/* ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h */ +/* and is the address of the base of the Snoop Control Unit (SCU) */ +#define GLOBALTMR_BASE (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET) +#define CPU_WDTGPT_TMR_BASE (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET) +#define CPU_PRIVATE_TMR_BASE (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET) +#define CPU_INT_CTRL_BASE (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET) +#define CPU_INT_DIST_BASE (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET) + + + /* offsets */ + /* Global Timer offsets */ +#define GLOBALTMR_MODULE_BASE_OFFSET 0x00000200 +#define GLOBALTMR_CNTR_LO_REG_OFFSET 0x00000000 +#define GLOBALTMR_CNTR_HI_REG_OFFSET 0x00000004 +#define GLOBALTMR_CTRL_REG_OFFSET 0x00000008 +#define GLOBALTMR_INT_STAT_REG_OFFSET 0x0000000C +#define GLOBALTMR_COMP_LO_REG_OFFSET 0x00000010 +#define GLOBALTMR_COMP_HI_REG_OFFSET 0x00000014 +#define GLOBALTMR_AUTOINC_REG_OFFSET 0x00000018 + +/* Global Timer bitmasks */ +#define GLOBALTMR_ENABLE_BIT 0x00000001 +#define GLOBALTMR_COMP_ENABLE_BIT 0x00000002 +#define GLOBALTMR_INT_ENABLE_BIT 0x00000004 +#define GLOBALTMR_AUTOINC_ENABLE_BIT 0x00000008 +#define GLOBALTMR_PS_MASK 0x0000FF00 +#define GLOBALTMR_PS_SHIFT 8 +#define GLOBALTMR_INT_STATUS_BIT 0x00000001 + +/* Global timer constants */ +#define GLOBALTMR_MAX 0xFFFFFFFF +#define GLOBALTMR_PS_MAX 0x000000FF + + +/* Private timer offsets */ +#define CPU_PRIV_TIMER_MODULE_BASE_OFFSET 0x00000600 +#define CPU_PRIV_TMR_LOAD_REG_OFFSET 0x00000000 +#define CPU_PRIV_TMR_CNTR_REG_OFFSET 0x00000004 +#define CPU_PRIV_TMR_CTRL_REG_OFFSET 0x00000008 +#define CPU_PRIV_TMR_INT_STATUS_REG_OFFSET 0x0000000C + +/* Private timer bitmasks */ +#define CPU_PRIV_TMR_ENABLE 0x00000001 +#define CPU_PRIV_TMR_AUTO_RELOAD 0x00000002 +#define CPU_PRIV_TMR_INT_EN 0x00000004 +#define CPU_PRIV_TMR_PS_MASK 0x0000FF00 +#define CPU_PRIV_TMR_PS_SHIFT 8 +#define CPU_PRIV_TMR_INT_STATUS 0x00000001 + +/* Private timer constants */ +#define CPU_PRIV_TMR_MAX 0xFFFFFFFF +#define CPU_PRIV_TMR_PS_MAX 0x000000FF + + + + /* Watchdog timer offsets */ +#define WDOG_TIMER_MODULE_BASE_OFFSET 0x00000620 +#define WDOG_LOAD_REG_OFFSET 0x00000000 +#define WDOG_CNTR_REG_OFFSET 0x00000004 +#define WDOG_CTRL_REG_OFFSET 0x00000008 +#define WDOG_INTSTAT_REG_OFFSET 0x0000000C +#define WDOG_RSTSTAT_REG_OFFSET 0x00000010 +#define WDOG_DISABLE_REG_OFFSET 0x00000014 + + /* Watchdog timer bitmasks : */ + /* Control Register bitmasks */ +#define WDOG_TMR_ENABLE 0x00000001 +#define WDOG_AUTO_RELOAD 0x00000002 +#define WDOG_INT_EN 0x00000004 +#define WDOG_WDT_MODE 0x00000008 +#define WDOG_PS_MASK 0x0000FF00 +#define WDOG_PS_SHIFT 8 + /* Interrupt Status Register bitmasks */ +#define WDOG_INT_STAT_BIT 0x00000001 + /* Reset Status Register bitmasks */ +#define WDOG_RST_STAT_BIT 0x00000001 + + /* Watchdog timer constants */ +#define WDOG_TMR_MAX UINT32_MAX +#define WDOG_PS_MAX UINT8_MAX +#define WDOG_DISABLE_VAL0 0x12345678 +#define WDOG_DISABLE_VAL1 0x87654321 + + + + /* Interrupt Manager offsets */ +/* */ +#define INT_CONTROLLER_MODULE_BASE_OFFSET 0x00000100 +#define INT_DISTRIBUTOR_MODULE_BASE_OFFSET 0x00001000 +#define INT_DIST_TYPE_REG 0x00000004 + + +/* Upper bound of the MPUSCU address space */ +#define MPUSCU_MAX 0x00001FFF + + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_MPUSCU_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h new file mode 100644 index 0000000000..21fd3a957d --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h @@ -0,0 +1,167 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*! \file + * Altera - QSPI Flash Controller Module + */ + +#ifndef __ALT_QSPI_PRIVATE_H__ +#define __ALT_QSPI_PRIVATE_H__ + +#include "socal/socal.h" + +// +// This section provisions support for various flash devices. +// + +#define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1 + +///// + +#define ALT_QSPI_PAGE_ADDR_MSK 0xFFFFFF00 +#define ALT_QSPI_PAGE_SIZE 0x00000100 // 256 B +#define ALT_QSPI_SUBSECTOR_ADDR_MSK 0xFFFFF000 +#define ALT_QSPI_SUBSECTOR_SIZE 0x00001000 // 4096 B +#define ALT_QSPI_SECTOR_ADDR_MSK 0xFFFF0000 +#define ALT_QSPI_SECTOR_SIZE 0x00010000 // 64 KiB +#define ALT_QSPI_BANK_ADDR_MSK 0xFF000000 +#define ALT_QSPI_BANK_SIZE 0x01000000 // 16 MiB + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +#define ALT_QSPI_N25Q_DIE_ADDR_MSK 0xFE000000 +#define ALT_QSPI_N25Q_DIE_SIZE 0x02000000 // 32 MiB +#endif + +///// + +// Default delay timing (in ns) for N25Q. +// These values are from the N25Q handbook. The timing correctness is difficult +// to test because the test setup does not feature mutliple chips. +#define ALT_QSPI_TSHSL_NS_DEF (50) +#define ALT_QSPI_TSD2D_NS_DEF (0) +#define ALT_QSPI_TCHSH_NS_DEF (4) +#define ALT_QSPI_TSLCH_NS_DEF (4) + +/* +// Default delay timing (in ns) +#define ALT_QSPI_TSHSL_NS_DEF (200) +#define ALT_QSPI_TSD2D_NS_DEF (255) +#define ALT_QSPI_TCHSH_NS_DEF (20) +#define ALT_QSPI_TSLCH_NS_DEF (20) +*/ + +// Flash commands +#define ALT_QSPI_STIG_OPCODE_READ (0x03) +#define ALT_QSPI_STIG_OPCODE_4BYTE_READ (0x13) +#define ALT_QSPI_STIG_OPCODE_FASTREAD (0x0B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO (0xBB) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO (0xEB) +#define ALT_QSPI_STIG_OPCODE_PP (0x02) +#define ALT_QSPI_STIG_OPCODE_DUAL_PP (0xA2) +#define ALT_QSPI_STIG_OPCODE_QUAD_PP (0x32) +#define ALT_QSPI_STIG_OPCODE_RDID (0x9F) +#define ALT_QSPI_STIG_OPCODE_WREN (0x06) +#define ALT_QSPI_STIG_OPCODE_WRDIS (0x04) +#define ALT_QSPI_STIG_OPCODE_RDSR (0x05) +#define ALT_QSPI_STIG_OPCODE_WRSR (0x01) +#define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE (0x20) +#define ALT_QSPI_STIG_OPCODE_SEC_ERASE (0xD8) +#define ALT_QSPI_STIG_OPCODE_BULK_ERASE (0xC7) +#define ALT_QSPI_STIG_OPCODE_DIE_ERASE (0xC4) +#define ALT_QSPI_STIG_OPCODE_CHIP_ERASE (0x60) +#define ALT_QSPI_STIG_OPCODE_RD_EXT_REG (0xC8) +#define ALT_QSPI_STIG_OPCODE_WR_EXT_REG (0xC5) +#define ALT_QSPI_STIG_OPCODE_RD_STAT_REG (0x05) +#define ALT_QSPI_STIG_OPCODE_WR_STAT_REG (0x01) +#define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE (0xB7) +#define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE (0xE9) + +// Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts. +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +#define ALT_QSPI_STIG_OPCODE_RESET_EN (0x66) +#define ALT_QSPI_STIG_OPCODE_RESET_MEM (0x99) +#define ALT_QSPI_STIG_OPCODE_RDFLGSR (0x70) +#define ALT_QSPI_STIG_OPCODE_CLRFLGSR (0x50) +#define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM (0x5A) +#endif + +// Spansion commands +// #define OPCODE_ECRM (0xFF) // Exit continuous read mode + +#define QSPI_READ_CLK_MHZ (50) +#define QSPI_FASTREAD_CLK_MHZ (100) + +// Manufacturer ID +#define ALT_QSPI_STIG_RDID_JEDECID_MICRON (0x20) +#define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX (0x20) // Same as Micron +#define ALT_QSPI_STIG_RDID_JEDECID_SPANSION (0xEF) +#define ALT_QSPI_STIG_RDID_JEDECID_WINBOND (0xEF) // Same as Spansion +#define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC (0xC2) +#define ALT_QSPI_STIG_RDID_JEDECID_ATMEL (0x1F) + +#define ALT_QSPI_STIG_RDID_JEDECID_GET(value) ((value >> 0) & 0xff) +#define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff) + +#define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value) ((value >> 5) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value) ((value >> 4) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value) ((value >> 1) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value) ((value >> 0) & 0x1) + +#define ALT_QSPI_STIG_SR_BUSY_GET(value) ((value >> 0) & 0x1) + +///// + +#define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff) + +ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size); + +ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy, + uint32_t num_bytes, uint32_t * output, + uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy, + uint32_t num_bytes, const uint32_t * input, + uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy, + uint32_t address, + uint32_t timeout); + +ALT_STATUS_CODE alt_qspi_device_wren(void); +ALT_STATUS_CODE alt_qspi_device_wrdis(void); +ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid); +ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param); +ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank); + +#endif // __ALT_PRIVATE_QSPI_H__ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h new file mode 100644 index 0000000000..d719e3f05e --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h @@ -0,0 +1,291 @@ +/*! \file + * Altera - SoC Reset Manager + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_RESET_MGR_H__ +#define __ALT_RESET_MGR_H__ + +#include "hwlib.h" +#include + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! \addtogroup RST_MGR The Reset Manager + * + * The Reset Manager API defines functions for accessing, configuring, and + * controlling the HPS reset behavior. + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup RST_MGR_STATUS Reset Status + * + * This functional group provides information on various aspects of SoC reset + * status and timeout events. + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the set of reset causes and timeout events as + * register mask values. + */ +typedef enum ALT_RESET_EVENT_e +{ + /*! Power-On Voltage Detector Cold Reset */ + ALT_RESET_EVENT_PORVOLTRST = 0x00000001, + + /*! nPOR Pin Cold Reset */ + ALT_RESET_EVENT_NPORPINRST = 0x00000002, + + /*! FPGA Core Cold Reset */ + ALT_RESET_EVENT_FPGACOLDRST = 0x00000004, + + /*! CONFIG_IO Cold Reset */ + ALT_RESET_EVENT_CONFIGIOCOLDRST = 0x00000008, + + /*! Software Cold Reset */ + ALT_RESET_EVENT_SWCOLDRST = 0x00000010, + + /*! nRST Pin Warm Reset */ + ALT_RESET_EVENT_NRSTPINRST = 0x00000100, + + /*! FPGA Core Warm Reset */ + ALT_RESET_EVENT_FPGAWARMRST = 0x00000200, + + /*! Software Warm Reset */ + ALT_RESET_EVENT_SWWARMRST = 0x00000400, + + /*! MPU Watchdog 0 Warm Reset */ + ALT_RESET_EVENT_MPUWD0RST = 0x00001000, + + /*! MPU Watchdog 1 Warm Reset */ + ALT_RESET_EVENT_MPUWD1RST = 0x00002000, + + /*! L4 Watchdog 0 Warm Reset */ + ALT_RESET_EVENT_L4WD0RST = 0x00004000, + + /*! L4 Watchdog 1 Warm Reset */ + ALT_RESET_EVENT_L4WD1RST = 0x00008000, + + /*! FPGA Core Debug Reset */ + ALT_RESET_EVENT_FPGADBGRST = 0x00040000, + + /*! DAP Debug Reset */ + ALT_RESET_EVENT_CDBGREQRST = 0x00080000, + + /*! SDRAM Self-Refresh Timeout */ + ALT_RESET_EVENT_SDRSELFREFTIMEOUT = 0x01000000, + + /*! FPGA manager handshake Timeout */ + ALT_RESET_EVENT_FPGAMGRHSTIMEOUT = 0x02000000, + + /*! SCAN manager handshake Timeout */ + ALT_RESET_EVENT_SCANHSTIMEOUT = 0x04000000, + + /*! FPGA handshake Timeout */ + ALT_RESET_EVENT_FPGAHSTIMEOUT = 0x08000000, + + /*! ETR Stall Timeout */ + ALT_RESET_EVENT_ETRSTALLTIMEOUT = 0x10000000 +} ALT_RESET_EVENT_t; + +/******************************************************************************/ +/*! + * Gets the reset and timeout events that caused the last reset. + * + * The ALT_RESET_EVENT_t enumeration values should be used to selectively + * examine the returned reset cause(s). + * + * \returns A mask of the reset and/or timeout events that caused the last + * reset. + */ +uint32_t alt_reset_event_get(void); + +/******************************************************************************/ +/*! + * Clears the reset and timeout events that caused the last reset. + * + * \param event_mask + * A mask of the selected reset and timeout events to clear in the + * Reset Manager \e stat register. The mask selection can be formed + * using the ALT_RESET_EVENT_t enumeration values. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup RST_MGR_CTRL Reset Control + * + * This functional group provides global and selective reset control for the SoC + * and its constituent modules. + * + * @{ + */ + +/******************************************************************************/ +/*! + * Initiate a cold reset of the SoC. + * + * If this function is successful, then it should never return. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_reset_cold_reset(void); + +/******************************************************************************/ +/*! + * Initiate a warm reset of the SoC. + * + * Perform a hardware sequenced warm reset of the SoC. A hardware sequenced + * reset handshake with certain modules can optionally be requested in an + * attempt to ensure an orderly reset transition. + * + * \param warm_reset_delay + * Specifies the number of cycles after the Reset Manager releases + * the Clock Manager reset before releasing any other hardware + * controlled resets. Value must be greater than 16 and less than + * 256. + * + * \param nRST_pin_clk_assertion + * Specifies that number of clock cycles (osc1_clk?) to externally + * assert the warm reset pin (nRST). 0 <= \e nRST_pin_clk_assertion <= + * (2**20 - 1). A value of 0 prevents any assertion of nRST. + * + * \param sdram_refresh + * Controls whether the contents of SDRAM survive a hardware + * sequenced warm reset. The reset manager requests the SDRAM + * controller to put SDRAM devices into self-refresh mode before + * asserting warm reset signals. An argument value of \b true + * enables the option, \b false disables the option. + * + * \param fpga_mgr_handshake + * Controls whether a handshake between the reset manager and FPGA + * manager occurs before a warm reset. The handshake is used to + * warn the FPGA manager that a warm reset is imminent so it can + * prepare for it by driving its output clock to a quiescent state + * to avoid glitches. An argument value of \b true enables the + * option, \b false disables the option. + * + * \param scan_mgr_handshake + * Controls whether a handshake between the reset manager and scan + * manager occurs before a warm reset. The handshake is used to + * warn the scan manager that a warm reset is imminent so it can + * prepare for it by driving its output clock to a quiescent state + * to avoid glitches. An argument value of \b true enables the + * option, \b false disables the option. + * + * \param fpga_handshake + * Controls whether a handshake between the reset manager and the + * FPGA occurs before a warm reset. The handshake is used to warn + * the FPGA that a warm reset is imminent so that the FPGA prepare + * for the reset event in soft IP. An argument value of \b true + * enables the option, \b false disables the option. + * + * \param etr_stall + * Controls whether the ETR is requested to idle its AXI master + * interface (i.e. finish outstanding transactions and not initiate + * any more) to the L3 Interconnect before a warm reset. An + * argument value of \b true enables the option, \b false disables + * the option. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay, + uint32_t nRST_pin_clk_assertion, + bool sdram_refresh, + bool fpga_mgr_handshake, + bool scan_mgr_handshake, + bool fpga_handshake, + bool etr_stall); + +#if 0 +/*! \addtogroup RST_MGR_MPU + * + * This functional group provides reset control for the Cortex-A9 MPU module. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_PERIPH + * + * This functional group provides inidividual reset control for the HPS + * peripheral modules. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_BRG + * + * This functional group provides inidividual reset control for the bridge + * interfaces between the HPS and FPGA. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_MISC + * + * This functional group provides inidividual reset control for miscellaneous + * HPS modules. + * + * @{ + */ + +/*! @} */ + +#endif + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_RESET_MGR_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/hwlib.h b/bsps/arm/altera-cyclone-v/include/bsp/hwlib.h new file mode 100644 index 0000000000..aba7e877c4 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/hwlib.h @@ -0,0 +1,189 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HWLIB_H__ +#define __HWLIB_H__ + +#ifdef __cplusplus +#include +#include +#include +#else /* __cplusplus */ +#include +#include +#include +#endif /* __cplusplus */ + +#include "alt_hwlibs_ver.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * The type definition for status codes returned by the HWLIB. + */ +typedef int32_t ALT_STATUS_CODE; + +/*! Definitions of status codes returned by the HWLIB. */ + +/*! The operation was successful. */ +#define ALT_E_SUCCESS 0 + +/*! The operation failed. */ +#define ALT_E_ERROR (-1) +/*! FPGA configuration error detected.*/ +#define ALT_E_FPGA_CFG (-2) +/*! FPGA CRC error detected. */ +#define ALT_E_FPGA_CRC (-3) +/*! An error occurred on the FPGA configuration bitstream input source. */ +#define ALT_E_FPGA_CFG_STM (-4) +/*! The FPGA is powered off. */ +#define ALT_E_FPGA_PWR_OFF (-5) +/*! The SoC does not currently control the FPGA. */ +#define ALT_E_FPGA_NO_SOC_CTRL (-6) +/*! The FPGA is not in USER mode. */ +#define ALT_E_FPGA_NOT_USER_MODE (-7) +/*! An argument violates a range constraint. */ +#define ALT_E_ARG_RANGE (-8) +/*! A bad argument value was passed. */ +#define ALT_E_BAD_ARG (-9) +/*! The operation is invalid or illegal. */ +#define ALT_E_BAD_OPERATION (-10) +/*! An invalid option was selected. */ +#define ALT_E_INV_OPTION (-11) +/*! An operation or response timeout period expired. */ +#define ALT_E_TMO (-12) +/*! The argument value is reserved or unavailable. */ +#define ALT_E_RESERVED (-13) +/*! A clock is not enabled or violates an operational constraint. */ +#define ALT_E_BAD_CLK (-14) +/*! The version ID is invalid. */ +#define ALT_E_BAD_VERSION (-15) +/*! The buffer does not contain enough free space for the operation. */ +#define ALT_E_BUF_OVF (-20) + +/*! + * Indicates a FALSE condition. + */ +#define ALT_E_FALSE (0) +/*! + * Indicates a TRUE condition. + */ +#define ALT_E_TRUE (1) + +/* Note, additional positive status codes may be defined to return + * a TRUE condition with additional information */ + + +/* Some other useful definitions */ + +/*! + * Specifies the current major and minor revision of the HWLibs. The + * MS four decimal digits specify the Altera ACDS release number, the + * LS two decimal digits specify minor revisions of the HWLibs, if any. + * + * A typical use is: + * \code + * #if ALTERA_HWLIBS_VERSION_CODE >= ALT_HWLIBS_VERSION(13, 1, 0) + * \endcode + * for a dependency on the major or minor ACDS revision + * or + * \code + * #if ALTERA_HWLIBS_VERSION_CODE == ALT_HWLIBS_VERSION(13, 0, 12) + * \endcode + * for a dependency on the hwlibs revision + * + */ +#define ALT_HWLIBS_VERSION(a,b,c) (((a)*10000)+((b)*100)+(c)) + +#define ALTERA_HWLIBS_VERSION_CODE ALT_HWLIBS_VERSION(ALTERA_ACDS_MAJOR_REV, \ + ALTERA_ACDS_MINOR_REV, ALTERA_HWLIBS_REV) + +/*! + * Allow some parts of the documentation to be hidden by setting to zero + */ +#define ALTERA_INTERNAL_ONLY_DOCS 1 + + +/*! + * Provide base address of MPU address space + */ + +#ifndef ALT_HPS_ADDR +#define ALT_HPS_ADDR 0 +#endif + +/*! + * These constants are sometimes useful: + */ +#define ALT_MILLISECS_IN_A_SEC 1000 +#define ALT_MICROSECS_IN_A_SEC 1000000 +#define ALT_NANOSECS_IN_A_SEC 1000000000 + +#define ALT_TWO_TO_POW0 (1) +#define ALT_TWO_TO_POW1 (1<<1) +#define ALT_TWO_TO_POW2 (1<<2) +#define ALT_TWO_TO_POW3 (1<<3) +#define ALT_TWO_TO_POW4 (1<<4) +#define ALT_TWO_TO_POW5 (1<<5) +#define ALT_TWO_TO_POW6 (1<<6) +#define ALT_TWO_TO_POW7 (1<<7) +#define ALT_TWO_TO_POW8 (1<<8) +#define ALT_TWO_TO_POW9 (1<<9) +#define ALT_TWO_TO_POW10 (1<<10) +#define ALT_TWO_TO_POW11 (1<<11) +#define ALT_TWO_TO_POW12 (1<<12) +#define ALT_TWO_TO_POW13 (1<<13) +#define ALT_TWO_TO_POW14 (1<<14) +#define ALT_TWO_TO_POW15 (1<<15) +#define ALT_TWO_TO_POW16 (1<<16) +#define ALT_TWO_TO_POW17 (1<<17) +#define ALT_TWO_TO_POW18 (1<<18) +#define ALT_TWO_TO_POW19 (1<<19) +#define ALT_TWO_TO_POW20 (1<<20) +#define ALT_TWO_TO_POW21 (1<<21) +#define ALT_TWO_TO_POW22 (1<<22) +#define ALT_TWO_TO_POW23 (1<<23) +#define ALT_TWO_TO_POW24 (1<<24) +#define ALT_TWO_TO_POW25 (1<<25) +#define ALT_TWO_TO_POW26 (1<<26) +#define ALT_TWO_TO_POW27 (1<<27) +#define ALT_TWO_TO_POW28 (1<<28) +#define ALT_TWO_TO_POW29 (1<<29) +#define ALT_TWO_TO_POW30 (1<<30) +#define ALT_TWO_TO_POW31 (1<<31) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __HWLIB_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h b/bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h new file mode 100644 index 0000000000..9a4411d637 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef I2CDRV_H +#define I2CDRV_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +rtems_device_driver i2cdrv_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_ioctl( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define I2C_DRIVER_TABLE_ENTRY \ + { \ + i2cdrv_initialize, \ + i2cdrv_open, \ + i2cdrv_close, \ + i2cdrv_read, \ + i2cdrv_write, \ + i2cdrv_ioctl \ + } + +#define I2C_IOC_SET_SLAVE_ADDRESS 1 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* I2CDRV_H */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/irq.h b/bsps/arm/altera-cyclone-v/include/bsp/irq.h new file mode 100644 index 0000000000..c136500415 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/irq.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H +#define LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H + +#ifndef ASM + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Use interrupt IDs as defined in alt_interrupt_common.h */ +#define BSP_INTERRUPT_VECTOR_MIN ALT_INT_INTERRUPT_SGI0 +#define BSP_INTERRUPT_VECTOR_MAX ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H */ \ No newline at end of file diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h new file mode 100644 index 0000000000..3a6bf0fffa --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h @@ -0,0 +1,3569 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_ACPIDMAP */ + +#ifndef __ALTERA_ALT_ACPIDMAP_H__ +#define __ALTERA_ALT_ACPIDMAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : ACP ID Mapper Registers - ALT_ACPIDMAP + * ACP ID Mapper Registers + * + * Registers in the ACP ID Mapper module + * + */ +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 2 - vid2rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x1 | ARUSER value to SCU for ID=2 + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x4 | Remap Master ID = DAP ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x1 | Force Mapping for ID=2 + * + */ +/* + * Field : ARUSER value to SCU for ID=2 - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2RD. + */ +struct ALT_ACPIDMAP_VID2RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU for ID=2 */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID = DAP ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping for ID=2 */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2RD. */ +typedef volatile struct ALT_ACPIDMAP_VID2RD_s ALT_ACPIDMAP_VID2RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2RD_OFST 0x0 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 2 - vid2wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x1 | AWUSER value to SCU for ID=2 + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x4 | Remap Master ID = DAP ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x1 | Force Mapping for ID=2 + * + */ +/* + * Field : AWUSER value to SCU for ID=2 - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2WR. + */ +struct ALT_ACPIDMAP_VID2WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU for ID=2 */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID = DAP ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping for ID=2 */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2WR. */ +typedef volatile struct ALT_ACPIDMAP_VID2WR_s ALT_ACPIDMAP_VID2WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2WR_OFST 0x4 + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 3 - vid3rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3RD. + */ +struct ALT_ACPIDMAP_VID3RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3RD. */ +typedef volatile struct ALT_ACPIDMAP_VID3RD_s ALT_ACPIDMAP_VID3RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3RD_OFST 0x8 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 3 - vid3wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3WR. + */ +struct ALT_ACPIDMAP_VID3WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3WR. */ +typedef volatile struct ALT_ACPIDMAP_VID3WR_s ALT_ACPIDMAP_VID3WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3WR_OFST 0xc + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 4 - vid4rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4RD. + */ +struct ALT_ACPIDMAP_VID4RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4RD. */ +typedef volatile struct ALT_ACPIDMAP_VID4RD_s ALT_ACPIDMAP_VID4RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4RD_OFST 0x10 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 4 - vid4wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4WR. + */ +struct ALT_ACPIDMAP_VID4WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4WR. */ +typedef volatile struct ALT_ACPIDMAP_VID4WR_s ALT_ACPIDMAP_VID4WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4WR_OFST 0x14 + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 5 - vid5rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5RD. + */ +struct ALT_ACPIDMAP_VID5RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5RD. */ +typedef volatile struct ALT_ACPIDMAP_VID5RD_s ALT_ACPIDMAP_VID5RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5RD_OFST 0x18 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 5 - vid5wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5WR. + */ +struct ALT_ACPIDMAP_VID5WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5WR. */ +typedef volatile struct ALT_ACPIDMAP_VID5WR_s ALT_ACPIDMAP_VID5WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5WR_OFST 0x1c + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 6 - vid6rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6RD. + */ +struct ALT_ACPIDMAP_VID6RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6RD. */ +typedef volatile struct ALT_ACPIDMAP_VID6RD_s ALT_ACPIDMAP_VID6RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6RD_OFST 0x20 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 6 - vid6wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6WR. + */ +struct ALT_ACPIDMAP_VID6WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6WR. */ +typedef volatile struct ALT_ACPIDMAP_VID6WR_s ALT_ACPIDMAP_VID6WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6WR_OFST 0x24 + +/* + * Register : Read AXI Master Mapping Register for Dynamic Virtual ID Remap - dynrd + * + * The Read AXI Master Mapping Register contains the USER, and ADDR page signals + * mapping values for transaction that dynamically remapped to one of the available + * 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNRD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNRD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNRD. + */ +struct ALT_ACPIDMAP_DYNRD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNRD. */ +typedef volatile struct ALT_ACPIDMAP_DYNRD_s ALT_ACPIDMAP_DYNRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNRD register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNRD_OFST 0x28 + +/* + * Register : Write AXI Master Mapping Register for Dynamic Virtual ID Remap - dynwr + * + * The Write AXI Master Mapping Register contains the USER, and ADDR page signals + * mapping values for transaction that dynamically remapped to one of the available + * 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNWR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNWR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNWR. + */ +struct ALT_ACPIDMAP_DYNWR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNWR. */ +typedef volatile struct ALT_ACPIDMAP_DYNWR_s ALT_ACPIDMAP_DYNWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNWR register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNWR_OFST 0x2c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | 0x1 | ARUSER value to SCU for ID=2 (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Force Mapping for ID=2 (Status) + * + */ +/* + * Field : ARUSER value to SCU for ID=2 (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2RD_S. + */ +struct ALT_ACPIDMAP_VID2RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU for ID=2 (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID2RD_S_s ALT_ACPIDMAP_VID2RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2RD_S_OFST 0x30 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | 0x1 | AWUSER value to SCU for ID=2 (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Force Mapping for ID=2 (Status) + * + */ +/* + * Field : AWUSER value to SCU for ID=2 (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2WR_S. + */ +struct ALT_ACPIDMAP_VID2WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU for ID=2 (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID2WR_S_s ALT_ACPIDMAP_VID2WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2WR_S_OFST 0x34 + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3RD_S. + */ +struct ALT_ACPIDMAP_VID3RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID3RD_S_s ALT_ACPIDMAP_VID3RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3RD_S_OFST 0x38 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3WR_S. + */ +struct ALT_ACPIDMAP_VID3WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID3WR_S_s ALT_ACPIDMAP_VID3WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3WR_S_OFST 0x3c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4RD_S. + */ +struct ALT_ACPIDMAP_VID4RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID4RD_S_s ALT_ACPIDMAP_VID4RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4RD_S_OFST 0x40 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4WR_S. + */ +struct ALT_ACPIDMAP_VID4WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID4WR_S_s ALT_ACPIDMAP_VID4WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4WR_S_OFST 0x44 + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5RD_S. + */ +struct ALT_ACPIDMAP_VID5RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID5RD_S_s ALT_ACPIDMAP_VID5RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5RD_S_OFST 0x48 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5WR_S. + */ +struct ALT_ACPIDMAP_VID5WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID5WR_S_s ALT_ACPIDMAP_VID5WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5WR_S_OFST 0x4c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6RD_S. + */ +struct ALT_ACPIDMAP_VID6RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID6RD_S_s ALT_ACPIDMAP_VID6RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6RD_S_OFST 0x50 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6WR_S. + */ +struct ALT_ACPIDMAP_VID6WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID6WR_S_s ALT_ACPIDMAP_VID6WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6WR_S_OFST 0x54 + +/* + * Register : Read AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynrd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, and + * ADDR page signals mapping values for transaction that dynamically remapped to + * one of the available 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNRD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNRD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNRD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNRD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNRD_S. + */ +struct ALT_ACPIDMAP_DYNRD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNRD_S. */ +typedef volatile struct ALT_ACPIDMAP_DYNRD_S_s ALT_ACPIDMAP_DYNRD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNRD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNRD_S_OFST 0x58 + +/* + * Register : Write AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynwr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, and + * ADDR page signals mapping values for transaction that dynamically remapped to + * one of the available 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNWR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNWR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNWR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNWR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNWR_S. + */ +struct ALT_ACPIDMAP_DYNWR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNWR_S. */ +typedef volatile struct ALT_ACPIDMAP_DYNWR_S_s ALT_ACPIDMAP_DYNWR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNWR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNWR_S_OFST 0x5c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_ACPIDMAP. + */ +struct ALT_ACPIDMAP_s +{ + volatile ALT_ACPIDMAP_VID2RD_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ + volatile ALT_ACPIDMAP_VID2WR_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ + volatile ALT_ACPIDMAP_VID3RD_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ + volatile ALT_ACPIDMAP_VID3WR_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ + volatile ALT_ACPIDMAP_VID4RD_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ + volatile ALT_ACPIDMAP_VID4WR_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ + volatile ALT_ACPIDMAP_VID5RD_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ + volatile ALT_ACPIDMAP_VID5WR_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ + volatile ALT_ACPIDMAP_VID6RD_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ + volatile ALT_ACPIDMAP_VID6WR_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ + volatile ALT_ACPIDMAP_DYNRD_t dynrd; /* ALT_ACPIDMAP_DYNRD */ + volatile ALT_ACPIDMAP_DYNWR_t dynwr; /* ALT_ACPIDMAP_DYNWR */ + volatile ALT_ACPIDMAP_VID2RD_S_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ + volatile ALT_ACPIDMAP_VID2WR_S_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ + volatile ALT_ACPIDMAP_VID3RD_S_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ + volatile ALT_ACPIDMAP_VID3WR_S_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ + volatile ALT_ACPIDMAP_VID4RD_S_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ + volatile ALT_ACPIDMAP_VID4WR_S_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ + volatile ALT_ACPIDMAP_VID5RD_S_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ + volatile ALT_ACPIDMAP_VID5WR_S_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ + volatile ALT_ACPIDMAP_VID6RD_S_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ + volatile ALT_ACPIDMAP_VID6WR_S_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ + volatile ALT_ACPIDMAP_DYNRD_S_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ + volatile ALT_ACPIDMAP_DYNWR_S_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ + volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_ACPIDMAP. */ +typedef volatile struct ALT_ACPIDMAP_s ALT_ACPIDMAP_t; +/* The struct declaration for the raw register contents of register group ALT_ACPIDMAP. */ +struct ALT_ACPIDMAP_raw_s +{ + volatile uint32_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ + volatile uint32_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ + volatile uint32_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ + volatile uint32_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ + volatile uint32_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ + volatile uint32_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ + volatile uint32_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ + volatile uint32_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ + volatile uint32_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ + volatile uint32_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ + volatile uint32_t dynrd; /* ALT_ACPIDMAP_DYNRD */ + volatile uint32_t dynwr; /* ALT_ACPIDMAP_DYNWR */ + volatile uint32_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ + volatile uint32_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ + volatile uint32_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ + volatile uint32_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ + volatile uint32_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ + volatile uint32_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ + volatile uint32_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ + volatile uint32_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ + volatile uint32_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ + volatile uint32_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ + volatile uint32_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ + volatile uint32_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ + volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_ACPIDMAP. */ +typedef volatile struct ALT_ACPIDMAP_raw_s ALT_ACPIDMAP_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_ACPIDMAP_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h new file mode 100644 index 0000000000..1875a84f10 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h @@ -0,0 +1,6464 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_CLKMGR */ + +#ifndef __ALTERA_ALT_CLKMGR_H__ +#define __ALTERA_ALT_CLKMGR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : Clock Manager Module - ALT_CLKMGR + * Clock Manager Module + * + * Registers in the Clock Manager module + * + */ +/* + * Register : Control Register - ctrl + * + * Contains fields that control the entire Clock Manager. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | RW | 0x1 | Safe Mode + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x1 | Enable SafeMode on Warm Reset + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Safe Mode - safemode + * + * When set the Clock Manager is in Safe Mode. + * + * In Safe Mode Clock Manager register settings defining clock behavior are ignored + * and clocks are set to a Safe Mode state.In Safe Mode all clocks with the + * optional exception of debug clocks, are directly generated from the EOSC1 clock + * input, all PLLs are bypassed, all programmable dividers are set to 1 and all + * clocks are enabled. + * + * This bit should only be cleared when clocks have been correctly configured + * + * This field is set on a cold reset and optionally on a warm reset and may not be + * set by SW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */ +#define ALT_CLKMGR_CTL_SAFEMOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */ +#define ALT_CLKMGR_CTL_SAFEMOD_MSB 0 +/* The width in bits of the ALT_CLKMGR_CTL_SAFEMOD register field. */ +#define ALT_CLKMGR_CTL_SAFEMOD_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_CTL_SAFEMOD register field value. */ +#define ALT_CLKMGR_CTL_SAFEMOD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_CTL_SAFEMOD register field value. */ +#define ALT_CLKMGR_CTL_SAFEMOD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_CTL_SAFEMOD register field. */ +#define ALT_CLKMGR_CTL_SAFEMOD_RESET 0x1 +/* Extracts the ALT_CLKMGR_CTL_SAFEMOD field value from a register. */ +#define ALT_CLKMGR_CTL_SAFEMOD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_CTL_SAFEMOD register field value suitable for setting the register. */ +#define ALT_CLKMGR_CTL_SAFEMOD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable SafeMode on Warm Reset - ensfmdwr + * + * When set the Clock Manager will respond to a Safe Mode request from the Reset + * Manager on a warm reset by setting the Safe Mode bit. When clear the clock + * manager will not set the the Safe Mode bit on a warm reset This bit is cleared + * on a cold reset. Warm reset has no affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_MSB 2 +/* The width in bits of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_CTL_ENSFMDWR register field value. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_CTL_ENSFMDWR register field value. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_RESET 0x1 +/* Extracts the ALT_CLKMGR_CTL_ENSFMDWR field value from a register. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_CTL_ENSFMDWR register field value suitable for setting the register. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_CTL. + */ +struct ALT_CLKMGR_CTL_s +{ + uint32_t safemode : 1; /* Safe Mode */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t ensfmdwr : 1; /* Enable SafeMode on Warm Reset */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_CTL. */ +typedef volatile struct ALT_CLKMGR_CTL_s ALT_CLKMGR_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_CTL register from the beginning of the component. */ +#define ALT_CLKMGR_CTL_OFST 0x0 + +/* + * Register : PLL Bypass Register - bypass + * + * Contains fields that control bypassing each PLL. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | RW | 0x1 | Main PLL Bypass + * [1] | RW | 0x1 | SDRAM PLL Bypass + * [2] | RW | 0x0 | SDRAM PLL Bypass Source + * [3] | RW | 0x1 | Peripheral PLL Bypass + * [4] | RW | 0x0 | Peripheral PLL Bypass Source + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Main PLL Bypass - mainpll + * + * When set, causes the Main PLL VCO and counters to be bypassed so that all clocks + * generated by the Main PLL are directly driven from the Main PLL input clock. The + * bypass source for Main PLL is the external eosc1_clk. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_MSB 0 +/* The width in bits of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_MAINPLL register field value. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_BYPASS_MAINPLL register field value. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_RESET 0x1 +/* Extracts the ALT_CLKMGR_BYPASS_MAINPLL field value from a register. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_BYPASS_MAINPLL register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SDRAM PLL Bypass - sdrpll + * + * When set, causes the SDRAM PLL VCO and counters to be bypassed so that all + * clocks generated by the SDRAM PLL are directly driven from either eosc1_clk or + * the SDRAM PLL input clock. + * + * The bypass clock source for SDRAM PLL is determined by the SDRAM PLL Bypass + * Source Register bit. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_MSB 1 +/* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLL register field value. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLL register field value. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_RESET 0x1 +/* Extracts the ALT_CLKMGR_BYPASS_SDRPLL field value from a register. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_BYPASS_SDRPLL register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDRAM PLL Bypass Source - sdrpllsrc + * + * This bit defines the bypass source forSDRAM PLL. + * + * When changing fields that affect VCO lock the PLL must be bypassed and this bit + * must be set to OSC1_CLK. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:--------------------- + * ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 | 0x0 | Select EOSC1 + * ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX | 0x1 | Select PLL Input Mux + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC + * + * Select EOSC1 + */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC + * + * Select PLL Input Mux + */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_MSB 2 +/* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_RESET 0x0 +/* Extracts the ALT_CLKMGR_BYPASS_SDRPLLSRC field value from a register. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_BYPASS_SDRPLLSRC register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Peripheral PLL Bypass - perpll + * + * When set, causes the Peripheral PLL VCO and counters to be bypassed so that all + * clocks generated by the Peripheral PLL are directly driven from either eosc1_clk + * or the Peripheral PLL input clock. + * + * The bypass clock source for Peripheral PLL is determined by the Peripheral PLL + * Bypass Source Register bit. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */ +#define ALT_CLKMGR_BYPASS_PERPLL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */ +#define ALT_CLKMGR_BYPASS_PERPLL_MSB 3 +/* The width in bits of the ALT_CLKMGR_BYPASS_PERPLL register field. */ +#define ALT_CLKMGR_BYPASS_PERPLL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_PERPLL register field value. */ +#define ALT_CLKMGR_BYPASS_PERPLL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLL register field value. */ +#define ALT_CLKMGR_BYPASS_PERPLL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_BYPASS_PERPLL register field. */ +#define ALT_CLKMGR_BYPASS_PERPLL_RESET 0x1 +/* Extracts the ALT_CLKMGR_BYPASS_PERPLL field value from a register. */ +#define ALT_CLKMGR_BYPASS_PERPLL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_BYPASS_PERPLL register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_PERPLL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Peripheral PLL Bypass Source - perpllsrc + * + * This bit defines the bypass source forPeripheral PLL. + * + * When changing fields that affect VCO lock the PLL must be bypassed and this bit + * must be set to OSC1_CLK. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:--------------------- + * ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 | 0x0 | Select EOSC1 + * ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX | 0x1 | Select PLL Input Mux + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC + * + * Select EOSC1 + */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC + * + * Select PLL Input Mux + */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_MSB 4 +/* The width in bits of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_RESET 0x0 +/* Extracts the ALT_CLKMGR_BYPASS_PERPLLSRC field value from a register. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_BYPASS_PERPLLSRC register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_BYPASS. + */ +struct ALT_CLKMGR_BYPASS_s +{ + uint32_t mainpll : 1; /* Main PLL Bypass */ + uint32_t sdrpll : 1; /* SDRAM PLL Bypass */ + uint32_t sdrpllsrc : 1; /* SDRAM PLL Bypass Source */ + uint32_t perpll : 1; /* Peripheral PLL Bypass */ + uint32_t perpllsrc : 1; /* Peripheral PLL Bypass Source */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_BYPASS. */ +typedef volatile struct ALT_CLKMGR_BYPASS_s ALT_CLKMGR_BYPASS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_BYPASS register from the beginning of the component. */ +#define ALT_CLKMGR_BYPASS_OFST 0x4 + +/* + * Register : Interrupt Status Register - inter + * + * Contains fields that indicate the PLL lock status. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------------------------- + * [0] | RW | 0x0 | Main PLL Achieved Lock + * [1] | RW | 0x0 | Peripheral PLL Achieved Lock + * [2] | RW | 0x0 | SDRAM PLL Achieved Lock + * [3] | RW | 0x0 | Main PLL Lost Lock + * [4] | RW | 0x0 | Peripheral PLL Lost Lock + * [5] | RW | 0x0 | SDRAM PLL Lost Lock + * [6] | R | Unknown | Main PLL Current Lock Status + * [7] | R | Unknown | Peripheral PLL Current Lock Status + * [8] | R | Unknown | SDRAM PLL Current Lock Status + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Main PLL Achieved Lock - mainpllachieved + * + * If 1, the Main PLL has achieved lock at least once since this bit was cleared. + * If 0, the Main PLL has not achieved lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_MSB 0 +/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_MAINPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Peripheral PLL Achieved Lock - perpllachieved + * + * If 1, the Peripheral PLL has achieved lock at least once since this bit was + * cleared. If 0, the Peripheral PLL has not achieved lock since this bit was + * cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_MSB 1 +/* The width in bits of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_PERPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_INTER_PERPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDRAM PLL Achieved Lock - sdrpllachieved + * + * If 1, the SDRAM PLL has achieved lock at least once since this bit was cleared. + * If 0, the SDRAM PLL has not achieved lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_MSB 2 +/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_SDRPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Main PLL Lost Lock - mainplllost + * + * If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0, + * the Main PLL has not lost lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_MSB 3 +/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_MAINPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_INTER_MAINPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Peripheral PLL Lost Lock - perplllost + * + * If 1, the Peripheral PLL has lost lock at least once since this bit was cleared. + * If 0, the Peripheral PLL has not lost lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_MSB 4 +/* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_PERPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_INTER_PERPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : SDRAM PLL Lost Lock - sdrplllost + * + * If 1, the SDRAM PLL has lost lock at least once since this bit was cleared. If + * 0, the SDRAM PLL has not lost lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_MSB 5 +/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_SDRPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CLKMGR_INTER_SDRPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Main PLL Current Lock Status - mainplllocked + * + * If 1, the Main PLL is currently locked. If 0, the Main PLL is currently not + * locked. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_MSB 6 +/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field is UNKNOWN. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_MAINPLLLOCKED field value from a register. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CLKMGR_INTER_MAINPLLLOCKED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Peripheral PLL Current Lock Status - perplllocked + * + * If 1, the Peripheral PLL is currently locked. If 0, the Peripheral PLL is + * currently not locked. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_MSB 7 +/* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CLKMGR_INTER_PERPLLLOCKED register field is UNKNOWN. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_PERPLLLOCKED field value from a register. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CLKMGR_INTER_PERPLLLOCKED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : SDRAM PLL Current Lock Status - sdrplllocked + * + * If 1, the SDRAM PLL is currently locked. If 0, the SDRAM PLL is currently not + * locked. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_MSB 8 +/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field is UNKNOWN. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_SDRPLLLOCKED field value from a register. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CLKMGR_INTER_SDRPLLLOCKED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_INTER. + */ +struct ALT_CLKMGR_INTER_s +{ + uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock */ + uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock */ + uint32_t sdrpllachieved : 1; /* SDRAM PLL Achieved Lock */ + uint32_t mainplllost : 1; /* Main PLL Lost Lock */ + uint32_t perplllost : 1; /* Peripheral PLL Lost Lock */ + uint32_t sdrplllost : 1; /* SDRAM PLL Lost Lock */ + const uint32_t mainplllocked : 1; /* Main PLL Current Lock Status */ + const uint32_t perplllocked : 1; /* Peripheral PLL Current Lock Status */ + const uint32_t sdrplllocked : 1; /* SDRAM PLL Current Lock Status */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_INTER. */ +typedef volatile struct ALT_CLKMGR_INTER_s ALT_CLKMGR_INTER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_INTER register from the beginning of the component. */ +#define ALT_CLKMGR_INTER_OFST 0x8 + +/* + * Register : Interrupt Enable Register - intren + * + * Contain fields that enable the interrupt. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable + * [1] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable + * [2] | RW | 0x0 | SDRAM PLL Achieved Lock Interrupt Enable + * [3] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable + * [4] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable + * [5] | RW | 0x0 | SDRAM PLL Achieved Lock Interrupt Enable + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Main PLL Achieved Lock Interrupt Enable - mainpllachieved + * + * When set to 1, the Main PLL achieved lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the Main PLL achieved lock bit is not ORed into + * the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_MSB 0 +/* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_MAINPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Peripheral PLL Achieved Lock Interrupt Enable - perpllachieved + * + * When set to 1, the Peripheral PLL achieved lock bit is ORed into the Clock + * Manager interrupt output. When set to 0 the Peripheral PLL achieved lock bit is + * not ORed into the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_MSB 1 +/* The width in bits of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_PERPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrpllachieved + * + * When set to 1, the SDRAM PLL achieved lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the SDRAM PLL achieved lock bit is not ORed + * into the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_MSB 2 +/* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_SDRPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Main PLL Achieved Lock Interrupt Enable - mainplllost + * + * When set to 1, the Main PLL lost lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the Main PLL lost lock bit is not ORed into the + * Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_MSB 3 +/* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_MAINPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_INTREN_MAINPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Peripheral PLL Achieved Lock Interrupt Enable - perplllost + * + * When set to 1, the Peripheral PLL lost lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the Peripheral PLL lost lock bit is not ORed + * into the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_MSB 4 +/* The width in bits of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_PERPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_INTREN_PERPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrplllost + * + * When set to 1, the SDRAM PLL lost lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the SDRAM PLL lost lock bit is not ORed into + * the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_MSB 5 +/* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_SDRPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CLKMGR_INTREN_SDRPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_INTREN. + */ +struct ALT_CLKMGR_INTREN_s +{ + uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock Interrupt Enable */ + uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */ + uint32_t sdrpllachieved : 1; /* SDRAM PLL Achieved Lock Interrupt Enable */ + uint32_t mainplllost : 1; /* Main PLL Achieved Lock Interrupt Enable */ + uint32_t perplllost : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */ + uint32_t sdrplllost : 1; /* SDRAM PLL Achieved Lock Interrupt Enable */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_INTREN. */ +typedef volatile struct ALT_CLKMGR_INTREN_s ALT_CLKMGR_INTREN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_INTREN register from the beginning of the component. */ +#define ALT_CLKMGR_INTREN_OFST 0xc + +/* + * Register : Debug clock Control Register - dbctrl + * + * Contains fields that control the debug clocks. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | RW | 0x1 | Debug Clocks Stay on EOSC1_CLK + * [1] | RW | 0x1 | Debug Clocks Enable Safe Mode + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debug Clocks Stay on EOSC1_CLK - stayosc1 + * + * When this bit is set the debug root clock (Main PLL C2 output) will always be + * bypassed to the EOSC1_clk independent of any other clock manager settings. + * When clear the debug source will be a function of register settings in the clock + * manager. Clocks affected by this bit are dbg_at_clk, dbg_clk, dbg_trace_clk, + * and dbg_timer_clk. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_MSB 0 +/* The width in bits of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_RESET 0x1 +/* Extracts the ALT_CLKMGR_DBCTL_STAYOSC1 field value from a register. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_DBCTL_STAYOSC1 register field value suitable for setting the register. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Debug Clocks Enable Safe Mode - ensfmdwr + * + * When this bit is set the debug clocks will be affected by the assertion of Safe + * Mode on a warm reset if Stay OSC1 is not set. + * + * When this bit is clear the debug clocks will not be affected by the assertion of + * Safe Mode on a warm reset. + * + * If Debug Clocks are in Safe Mode they are taken out of Safe Mode when the Safe + * Mode bit is cleared independent of this bit.The reset value of this bit is + * applied on a cold reset; warm reset has no affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_MSB 1 +/* The width in bits of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_RESET 0x1 +/* Extracts the ALT_CLKMGR_DBCTL_ENSFMDWR field value from a register. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_DBCTL_ENSFMDWR register field value suitable for setting the register. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_DBCTL. + */ +struct ALT_CLKMGR_DBCTL_s +{ + uint32_t stayosc1 : 1; /* Debug Clocks Stay on EOSC1_CLK */ + uint32_t ensfmdwr : 1; /* Debug Clocks Enable Safe Mode */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_DBCTL. */ +typedef volatile struct ALT_CLKMGR_DBCTL_s ALT_CLKMGR_DBCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_DBCTL register from the beginning of the component. */ +#define ALT_CLKMGR_DBCTL_OFST 0x10 + +/* + * Register : Status Register - stat + * + * Provides status of Hardware Managed Clock transition State Machine. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | HW Managed Clocks BUSY + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : HW Managed Clocks BUSY - busy + * + * This read only bit indicates that the Hardware Managed clock's state machine is + * active. If the state machine is active, then the clocks are in transition. + * Software should poll this bit after changing the source of internal clocks when + * writing to the BYPASS, CTRL or DBCTRL registers. Immediately following writes + * to any of these registers, SW should wait until this bit is IDLE before + * proceeding with any other register writes in the Clock Manager. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------- + * ALT_CLKMGR_STAT_BUSY_E_IDLE | 0x0 | Clocks stable + * ALT_CLKMGR_STAT_BUSY_E_BUSY | 0x1 | Clocks in transition + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_STAT_BUSY + * + * Clocks stable + */ +#define ALT_CLKMGR_STAT_BUSY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_STAT_BUSY + * + * Clocks in transition + */ +#define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_STAT_BUSY register field. */ +#define ALT_CLKMGR_STAT_BUSY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_STAT_BUSY register field. */ +#define ALT_CLKMGR_STAT_BUSY_MSB 0 +/* The width in bits of the ALT_CLKMGR_STAT_BUSY register field. */ +#define ALT_CLKMGR_STAT_BUSY_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_STAT_BUSY register field value. */ +#define ALT_CLKMGR_STAT_BUSY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_STAT_BUSY register field value. */ +#define ALT_CLKMGR_STAT_BUSY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_STAT_BUSY register field. */ +#define ALT_CLKMGR_STAT_BUSY_RESET 0x0 +/* Extracts the ALT_CLKMGR_STAT_BUSY field value from a register. */ +#define ALT_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_STAT_BUSY register field value suitable for setting the register. */ +#define ALT_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_STAT. + */ +struct ALT_CLKMGR_STAT_s +{ + const uint32_t busy : 1; /* HW Managed Clocks BUSY */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_STAT. */ +typedef volatile struct ALT_CLKMGR_STAT_s ALT_CLKMGR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_STAT register from the beginning of the component. */ +#define ALT_CLKMGR_STAT_OFST 0x14 + +/* + * Register Group : Main PLL Group - ALT_CLKMGR_MAINPLL + * Main PLL Group + * + * Contains registers with settings for the Main PLL. + * + */ +/* + * Register : Main PLL VCO Control Register - vco + * + * Contains settings that control the Main PLL VCO. The VCO output frequency is the + * input frequency multiplied by the numerator (M+1) and divided by the denominator + * (N+1). The VCO input clock source is always eosc1_clk. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [0] | RW | 0x1 | BG PWRDN + * [1] | RW | 0x0 | Enable + * [2] | RW | 0x1 | Power down + * [15:3] | RW | 0x1 | Numerator (M) + * [21:16] | RW | 0x1 | Denominator (N) + * [23:22] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | All Output Counter Reset + * [30:25] | RW | 0x0 | Output Counter Reset + * [31] | RW | 0x1 | External Regulator Input Select + * + */ +/* + * Field : BG PWRDN - bgpwrdn + * + * If '1', powers down bandgap. If '0', bandgap is not power down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_MSB 0 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable - en + * + * If '1', VCO is enabled. If '0', VCO is in reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_EN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_EN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Power down - pwrdn + * + * If '1', power down analog circuitry. If '0', analog circuitry not powered down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_MSB 2 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_PWRDN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Numerator (M) - numer + * + * Numerator in VCO output frequency equation. For incremental frequency change, if + * the new value lead to less than 20% of the frequency change, this value can be + * changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_MSB 15 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_WIDTH 13 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET_MSK 0x0000fff8 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK 0xffff0007 +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_NUMER field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_NUMER register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) + +/* + * Field : Denominator (N) - denom + * + * Denominator in VCO output frequency equation. For incremental frequency change, + * if the new value lead to less than 20% of the frequency change, this value can + * be changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_MSB 21 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_DENOM field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_DENOM register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : All Output Counter Reset - outresetall + * + * Before releasing Bypass, All Output Counter Reset must be set and cleared by + * software for correct clock operation. + * + * If '1', Reset phase multiplexer and all output counter state. So that after the + * assertion all the clocks output are start from rising edge align. + * + * If '0', phase multiplexer and output counter state not reset and no change to + * the phase of the clock outputs. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_MSB 24 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Output Counter Reset - outreset + * + * Resets the individual PLL output counter. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * LSB 'outreset[0]' corresponds to PLL output clock C0, etc. + * + * If set to '1', reset output divider, no clock output from counter. + * + * If set to '0', counter is not reset. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_MSB 30 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET_MSK 0x7e000000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK 0x81ffffff +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRST field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) + +/* + * Field : External Regulator Input Select - regextsel + * + * If set to '1', the external regulator is selected for the PLL. + * + * If set to '0', the internal regulator is slected. + * + * It is strongly recommended to select the external regulator while the PLL is not + * enabled (in reset), and then disable the external regulater once the PLL + * becomes enabled. Software should simulateously update the 'Enable' bit and the + * 'External Regulator Input Select' in the same write access to the VCO register. + * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be + * set, and vice versa. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_MSB 31 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_VCO. + */ +struct ALT_CLKMGR_MAINPLL_VCO_s +{ + uint32_t bgpwrdn : 1; /* BG PWRDN */ + uint32_t en : 1; /* Enable */ + uint32_t pwrdn : 1; /* Power down */ + uint32_t numer : 13; /* Numerator (M) */ + uint32_t denom : 6; /* Denominator (N) */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t outresetall : 1; /* All Output Counter Reset */ + uint32_t outreset : 6; /* Output Counter Reset */ + uint32_t regextsel : 1; /* External Regulator Input Select */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_VCO. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_VCO_s ALT_CLKMGR_MAINPLL_VCO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_VCO register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_VCO_OFST 0x0 + +/* + * Register : Main PLL VCO Advanced Control Register - misc + * + * Contains VCO control signals and other PLL control signals need to be + * controllable through register. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled + * [12:1] | RW | 0x1 | Loop Bandwidth Adjust + * [13] | RW | 0x0 | Fast Locking Enable + * [14] | RW | 0x1 | Saturation Enable + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Loop Bandwidth Adjust Enabled - bwadjen + * + * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth + * Adjust field. + * + * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 + * value of the VCO Control Register. The M divided by 2 is the upper 12 bits + * (12:1) of the M field in the VCO register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_MSB 0 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJEN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Loop Bandwidth Adjust - bwadj + * + * Provides Loop Bandwidth Adjust value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_MSB 12 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET_MSK 0x00001ffe +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_CLR_MSK 0xffffe001 +/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJ field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) +/* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) + +/* + * Field : Fast Locking Enable - fasten + * + * Enables fast locking circuit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_MSB 13 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MISC_FASTEN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Saturation Enable - saten + * + * Enables saturation behavior. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_MSB 14 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_MISC_SATEN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CLKMGR_MAINPLL_MISC_SATEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MISC. + */ +struct ALT_CLKMGR_MAINPLL_MISC_s +{ + uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */ + uint32_t bwadj : 12; /* Loop Bandwidth Adjust */ + uint32_t fasten : 1; /* Fast Locking Enable */ + uint32_t saten : 1; /* Saturation Enable */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MISC. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MISC_s ALT_CLKMGR_MAINPLL_MISC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MISC register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MISC_OFST 0x4 + +/* + * Register : Main PLL C0 Control Register for Clock mpu_clk - mpuclk + * + * Contains settings that control clock mpu_clk generated from the C0 output of the + * Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x0 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO/2 frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MPUCLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. + */ +struct ALT_CLKMGR_MAINPLL_MPUCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MPUCLK_s ALT_CLKMGR_MAINPLL_MPUCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MPUCLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_OFST 0x8 + +/* + * Register : Main PLL C1 Control Register for Clock main_clk - mainclk + * + * Contains settings that control clock main_clk generated from the C1 output of + * the Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x0 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO/4 frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINCLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINCLK. + */ +struct ALT_CLKMGR_MAINPLL_MAINCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINCLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MAINCLK_s ALT_CLKMGR_MAINPLL_MAINCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINCLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_OFST 0xc + +/* + * Register : Main PLL C2 Control Register for Clock dbg_base_clk - dbgatclk + * + * Contains settings that control clock dbg_base_clk generated from the C2 output + * of the Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x0 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO/4 frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK. + */ +struct ALT_CLKMGR_MAINPLL_DBGATCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_DBGATCLK_s ALT_CLKMGR_MAINPLL_DBGATCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_DBGATCLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_OFST 0x10 + +/* + * Register : Main PLL C3 Control Register for Clock main_qspi_clk - mainqspiclk + * + * Contains settings that control clock main_qspi_clk generated from the C3 output + * of the Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x3 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_RESET 0x3 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK. + */ +struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s ALT_CLKMGR_MAINPLL_MAINQSPICLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINQSPICLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST 0x14 + +/* + * Register : Main PLL C4 Control Register for Clock main_nand_sdmmc_clk - mainnandsdmmcclk + * + * Contains settings that control clock main_nand_sdmmc_clk generated from the C4 + * output of the Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x3 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_RESET 0x3 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK. + */ +struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST 0x18 + +/* + * Register : Main PLL C5 Control Register for Clock cfg_s2f_user0_clk - cfgs2fuser0clk + * + * Contains settings that control clock cfg_s2f_user0_clk generated from the C5 + * output of the Main PLL. + * + * Qsys and user documenation refer to cfg_s2f_user0_clk as cfg_h2f_user0_clk. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0xf | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_RESET 0xf +/* Extracts the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK. + */ +struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST 0x1c + +/* + * Register : Enable Register - en + * + * Contains fields that control clock enables for clocks derived from the Main PLL. + * + * 1: The clock is enabled. + * + * 0: The clock is disabled. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | l4_main_clk Enable + * [1] | RW | 0x1 | l3_mp_clk Enable + * [2] | RW | 0x1 | l4_mp_clk Enable + * [3] | RW | 0x1 | l4_sp_clk Enable + * [4] | RW | 0x1 | dbg_at_clk Enable + * [5] | RW | 0x1 | dbg_clk Enable + * [6] | RW | 0x1 | dbg_trace_clk Enable + * [7] | RW | 0x1 | dbg_timer_clk Enable + * [8] | RW | 0x1 | cfg_clk Enable + * [9] | RW | 0x1 | s2f_user0_clk Enable + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : l4_main_clk Enable - l4mainclk + * + * Enables clock l4_main_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_MSB 0 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : l3_mp_clk Enable - l3mpclk + * + * Enables clock l3_mp_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_L3MPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : l4_mp_clk Enable - l4mpclk + * + * Enables clock l4_mp_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : l4_sp_clk Enable - l4spclk + * + * Enables clock l4_sp_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4SPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : dbg_at_clk Enable - dbgatclk + * + * Enables clock dbg_at_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_MSB 4 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGATCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : dbg_clk Enable - dbgclk + * + * Enables clock dbg_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_MSB 5 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : dbg_trace_clk Enable - dbgtraceclk + * + * Enables clock dbg_trace_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_MSB 6 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : dbg_timer_clk Enable - dbgtimerclk + * + * Enables clock dbg_timer_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_MSB 7 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : cfg_clk Enable - cfgclk + * + * Enables clock cfg_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_CFGCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : s2f_user0_clk Enable - s2fuser0clk + * + * Enables clock s2f_user0_clk output. + * + * Qsys and user documenation refer to s2f_user0_clk as h2f_user0_clk. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_MSB 9 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET(value) (((value) << 9) & 0x00000200) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_EN. + */ +struct ALT_CLKMGR_MAINPLL_EN_s +{ + uint32_t l4mainclk : 1; /* l4_main_clk Enable */ + uint32_t l3mpclk : 1; /* l3_mp_clk Enable */ + uint32_t l4mpclk : 1; /* l4_mp_clk Enable */ + uint32_t l4spclk : 1; /* l4_sp_clk Enable */ + uint32_t dbgatclk : 1; /* dbg_at_clk Enable */ + uint32_t dbgclk : 1; /* dbg_clk Enable */ + uint32_t dbgtraceclk : 1; /* dbg_trace_clk Enable */ + uint32_t dbgtimerclk : 1; /* dbg_timer_clk Enable */ + uint32_t cfgclk : 1; /* cfg_clk Enable */ + uint32_t s2fuser0clk : 1; /* s2f_user0_clk Enable */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_EN. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_EN_s ALT_CLKMGR_MAINPLL_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_EN register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_EN_OFST 0x20 + +/* + * Register : Main Divide Register - maindiv + * + * Contains fields that control clock dividers for main clocks derived from the + * Main PLL + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [1:0] | RW | 0x0 | L3 MP Clock Divider + * [3:2] | RW | 0x0 | L3 SP Clock Divider + * [6:4] | RW | 0x0 | L4 MP Clock Divider + * [9:7] | RW | 0x0 | L4 SP Clock Divider + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : L3 MP Clock Divider - l3mpclk + * + * The l3_mp_clk is divided down from the l3_main_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 | 0x0 | Divide by 1 + * ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 | 0x1 | Divide by 2 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK + * + * Divide by 1 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK + * + * Divide by 2 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK 0x00000003 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_CLR_MSK 0xfffffffc +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : L3 SP Clock Divider - l3spclk + * + * The l3_sp_clk is divided down from the l3_mp_clk by the value specified in this + * field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 | 0x0 | Divide by 1 + * ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 | 0x1 | Divide by 2 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK + * + * Divide by 1 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK + * + * Divide by 2 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK 0x0000000c +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : L4 MP Clock Divider - l4mpclk + * + * The l4_mp_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_MSB 6 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK 0x00000070 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_CLR_MSK 0xffffff8f +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(value) (((value) & 0x00000070) >> 4) +/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET(value) (((value) << 4) & 0x00000070) + +/* + * Field : L4 SP Clock Divider - l4spclk + * + * The l4_sp_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_MSB 9 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK 0x00000380 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_CLR_MSK 0xfffffc7f +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(value) (((value) & 0x00000380) >> 7) +/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET(value) (((value) << 7) & 0x00000380) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINDIV. + */ +struct ALT_CLKMGR_MAINPLL_MAINDIV_s +{ + uint32_t l3mpclk : 2; /* L3 MP Clock Divider */ + uint32_t l3spclk : 2; /* L3 SP Clock Divider */ + uint32_t l4mpclk : 3; /* L4 MP Clock Divider */ + uint32_t l4spclk : 3; /* L4 SP Clock Divider */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINDIV. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MAINDIV_s ALT_CLKMGR_MAINPLL_MAINDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINDIV register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_OFST 0x24 + +/* + * Register : Debug Divide Register - dbgdiv + * + * Contains fields that control clock dividers for debug clocks derived from the + * Main PLL + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [1:0] | RW | 0x0 | Debug AT Clock Divider + * [3:2] | RW | 0x1 | Debug Clock Divider + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debug AT Clock Divider - dbgatclk + * + * The dbg_at_clk is divided down from the C2 output of the Main PLL by the value + * specified in this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 | 0x0 | Divide by 1 + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 | 0x1 | Divide by 2 + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 | 0x2 | Divide by 4 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK + * + * Divide by 1 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK + * + * Divide by 2 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK + * + * Divide by 4 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK 0x00000003 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_CLR_MSK 0xfffffffc +/* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Debug Clock Divider - dbgclk + * + * The dbg_clk is divided down from the dbg_at_clk by the value specified in this + * field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------ + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 | 0x1 | Divide by 2 + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 | 0x2 | Divide by 4 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK + * + * Divide by 2 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK + * + * Divide by 4 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK 0x0000000c +/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET(value) (((value) << 2) & 0x0000000c) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGDIV. + */ +struct ALT_CLKMGR_MAINPLL_DBGDIV_s +{ + uint32_t dbgatclk : 2; /* Debug AT Clock Divider */ + uint32_t dbgclk : 2; /* Debug Clock Divider */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGDIV. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_DBGDIV_s ALT_CLKMGR_MAINPLL_DBGDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_DBGDIV register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_OFST 0x28 + +/* + * Register : Debug Trace Divide Register - tracediv + * + * Contains a field that controls the clock divider for the debug trace clock + * derived from the Main PLL + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [2:0] | RW | 0x0 | Debug Trace Clock Divider + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debug Trace Clock Divider - traceclk + * + * The dbg_trace_clk is divided down from the C2 output of the Main PLL by the + * value specified in this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------- + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK 0x00000007 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET(value) (((value) << 0) & 0x00000007) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV. + */ +struct ALT_CLKMGR_MAINPLL_TRACEDIV_s +{ + uint32_t traceclk : 3; /* Debug Trace Clock Divider */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_TRACEDIV_s ALT_CLKMGR_MAINPLL_TRACEDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_TRACEDIV register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_OFST 0x2c + +/* + * Register : L4 MP SP APB Clock Source - l4src + * + * Contains fields that select the clock source for L4 MP and SP APB interconnect + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x0 | l4_mp_clk Source + * [1] | RW | 0x0 | l4_sp_clk Source + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : l4_mp_clk Source - l4mp + * + * Selects the source for l4_mp_clk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------- + * ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL | 0x0 | main_clk + * ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL | 0x1 | periph_base_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP + * + * main_clk + */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP + * + * periph_base_clk + */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_MSB 0 +/* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4MP field value from a register. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : l4_sp_clk Source - l4sp + * + * Selects the source for l4_sp_clk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------- + * ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL | 0x0 | main_clk + * ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL | 0x1 | periph_base_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP + * + * main_clk + */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP + * + * periph_base_clk + */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4SP field value from a register. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_L4SRC. + */ +struct ALT_CLKMGR_MAINPLL_L4SRC_s +{ + uint32_t l4mp : 1; /* l4_mp_clk Source */ + uint32_t l4sp : 1; /* l4_sp_clk Source */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_L4SRC. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_L4SRC_s ALT_CLKMGR_MAINPLL_L4SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_L4SRC register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_OFST 0x30 + +/* + * Register : Main PLL Output Counter Reset Ack Status Register - stat + * + * Contains Output Clock Counter Reset acknowledge status. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [5:0] | R | 0x0 | Output Counter Reset Acknowledge + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Output Counter Reset Acknowledge - outresetack + * + * These read only bits per PLL output indicate that the PLL has received the + * Output Reset Counter request and has gracefully stopped the respective PLL + * output clock. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------- + * ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle + * ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK + * + * Idle + */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK + * + * Output Counter Acknowledge received. + */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_MSB 5 +/* The width in bits of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f +/* The mask used to clear the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_STAT. + */ +struct ALT_CLKMGR_MAINPLL_STAT_s +{ + const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_STAT. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_STAT_s ALT_CLKMGR_MAINPLL_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_STAT register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_STAT_OFST 0x34 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CLKMGR_MAINPLL. + */ +struct ALT_CLKMGR_MAINPLL_s +{ + volatile ALT_CLKMGR_MAINPLL_VCO_t vco; /* ALT_CLKMGR_MAINPLL_VCO */ + volatile ALT_CLKMGR_MAINPLL_MISC_t misc; /* ALT_CLKMGR_MAINPLL_MISC */ + volatile ALT_CLKMGR_MAINPLL_MPUCLK_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */ + volatile ALT_CLKMGR_MAINPLL_MAINCLK_t mainclk; /* ALT_CLKMGR_MAINPLL_MAINCLK */ + volatile ALT_CLKMGR_MAINPLL_DBGATCLK_t dbgatclk; /* ALT_CLKMGR_MAINPLL_DBGATCLK */ + volatile ALT_CLKMGR_MAINPLL_MAINQSPICLK_t mainqspiclk; /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */ + volatile ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t mainnandsdmmcclk; /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */ + volatile ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t cfgs2fuser0clk; /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */ + volatile ALT_CLKMGR_MAINPLL_EN_t en; /* ALT_CLKMGR_MAINPLL_EN */ + volatile ALT_CLKMGR_MAINPLL_MAINDIV_t maindiv; /* ALT_CLKMGR_MAINPLL_MAINDIV */ + volatile ALT_CLKMGR_MAINPLL_DBGDIV_t dbgdiv; /* ALT_CLKMGR_MAINPLL_DBGDIV */ + volatile ALT_CLKMGR_MAINPLL_TRACEDIV_t tracediv; /* ALT_CLKMGR_MAINPLL_TRACEDIV */ + volatile ALT_CLKMGR_MAINPLL_L4SRC_t l4src; /* ALT_CLKMGR_MAINPLL_L4SRC */ + volatile ALT_CLKMGR_MAINPLL_STAT_t stat; /* ALT_CLKMGR_MAINPLL_STAT */ + volatile uint32_t _pad_0x38_0x40[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_CLKMGR_MAINPLL. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_s ALT_CLKMGR_MAINPLL_t; +/* The struct declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */ +struct ALT_CLKMGR_MAINPLL_raw_s +{ + volatile uint32_t vco; /* ALT_CLKMGR_MAINPLL_VCO */ + volatile uint32_t misc; /* ALT_CLKMGR_MAINPLL_MISC */ + volatile uint32_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */ + volatile uint32_t mainclk; /* ALT_CLKMGR_MAINPLL_MAINCLK */ + volatile uint32_t dbgatclk; /* ALT_CLKMGR_MAINPLL_DBGATCLK */ + volatile uint32_t mainqspiclk; /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */ + volatile uint32_t mainnandsdmmcclk; /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */ + volatile uint32_t cfgs2fuser0clk; /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */ + volatile uint32_t en; /* ALT_CLKMGR_MAINPLL_EN */ + volatile uint32_t maindiv; /* ALT_CLKMGR_MAINPLL_MAINDIV */ + volatile uint32_t dbgdiv; /* ALT_CLKMGR_MAINPLL_DBGDIV */ + volatile uint32_t tracediv; /* ALT_CLKMGR_MAINPLL_TRACEDIV */ + volatile uint32_t l4src; /* ALT_CLKMGR_MAINPLL_L4SRC */ + volatile uint32_t stat; /* ALT_CLKMGR_MAINPLL_STAT */ + volatile uint32_t _pad_0x38_0x40[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_raw_s ALT_CLKMGR_MAINPLL_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Peripheral PLL Group - ALT_CLKMGR_PERPLL + * Peripheral PLL Group + * + * Contains registers with settings for the Peripheral PLL. + * + */ +/* + * Register : Peripheral PLL VCO Control Register - vco + * + * Contains settings that control the Peripheral PLL VCO. The VCO output frequency + * is the input frequency multiplied by the numerator (M+1) and divided by the + * denominator (N+1). + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [0] | RW | 0x1 | BG PWRDN + * [1] | RW | 0x0 | Enable + * [2] | RW | 0x1 | Power down + * [15:3] | RW | 0x1 | Numerator (M) + * [21:16] | RW | 0x1 | Denominator (N) + * [23:22] | RW | 0x0 | Clock Source + * [24] | RW | 0x0 | All Output Counter Reset + * [30:25] | RW | 0x0 | Output Counter Reset + * [31] | RW | 0x1 | External Regulator Input Select + * + */ +/* + * Field : BG PWRDN - bgpwrdn + * + * If '1', powers down bandgap. If '0', bandgap is not power down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_MSB 0 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_BGPWRDN field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable - en + * + * If '1', VCO is enabled. If '0', VCO is in reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_MSB 1 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_EN field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_PERPLL_VCO_EN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Power down - pwrdn + * + * If '1', power down analog circuitry. If '0', analog circuitry not powered down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_MSB 2 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_PWRDN field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_PERPLL_VCO_PWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Numerator (M) - numer + * + * Numerator in VCO output frequency equation. For incremental frequency change, if + * the new value lead to less than 20% of the frequency change, this value can be + * changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_MSB 15 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_WIDTH 13 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_SET_MSK 0x0000fff8 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK 0xffff0007 +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_NUMER field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) +/* Produces a ALT_CLKMGR_PERPLL_VCO_NUMER register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) + +/* + * Field : Denominator (N) - denom + * + * Denominator in VCO output frequency equation. For incremental frequency change, + * if the new value lead to less than 20% of the frequency change, this value can + * be changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_MSB 21 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_DENOM field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_CLKMGR_PERPLL_VCO_DENOM register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : Clock Source - psrc + * + * Controls the VCO input clock source. + * + * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------- + * ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 | 0x0 | eosc1_clk + * ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 | 0x1 | eosc2_clk + * ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF | 0x2 | f2s_periph_ref_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC + * + * eosc1_clk + */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC + * + * eosc2_clk + */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC + * + * f2s_periph_ref_clk + */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_MSB 23 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_SET_MSK 0x00c00000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK 0xff3fffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_PSRC field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_GET(value) (((value) & 0x00c00000) >> 22) +/* Produces a ALT_CLKMGR_PERPLL_VCO_PSRC register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_SET(value) (((value) << 22) & 0x00c00000) + +/* + * Field : All Output Counter Reset - outresetall + * + * Before releasing Bypass, All Output Counter Reset must be set and cleared by + * software for correct clock operation. + * + * If '1', Reset phase multiplexer and all output counter state. So that after the + * assertion all the clocks output are start from rising edge align. + * + * If '0', phase multiplexer and output counter state not reset and no change to + * the phase of the clock outputs. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_MSB 24 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Output Counter Reset - outreset + * + * Resets the individual PLL output counter. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * LSB 'outreset[0]' corresponds to PLL output clock C0, etc. + * + * If set to '1', reset output divider, no clock output from counter. + * + * If set to '0', counter is not reset. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_MSB 30 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET_MSK 0x7e000000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK 0x81ffffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRST field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) +/* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRST register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) + +/* + * Field : External Regulator Input Select - regextsel + * + * If set to '1', the external regulator is selected for the PLL. + * + * If set to '0', the internal regulator is slected. + * + * It is strongly recommended to select the external regulator while the PLL is not + * enabled (in reset), and then disable the external regulater once the PLL + * becomes enabled. Software should simulateously update the 'Enable' bit and the + * 'External Regulator Input Select' in the same write access to the VCO register. + * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be + * set, and vice versa. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_MSB 31 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_VCO. + */ +struct ALT_CLKMGR_PERPLL_VCO_s +{ + uint32_t bgpwrdn : 1; /* BG PWRDN */ + uint32_t en : 1; /* Enable */ + uint32_t pwrdn : 1; /* Power down */ + uint32_t numer : 13; /* Numerator (M) */ + uint32_t denom : 6; /* Denominator (N) */ + uint32_t psrc : 2; /* Clock Source */ + uint32_t outresetall : 1; /* All Output Counter Reset */ + uint32_t outreset : 6; /* Output Counter Reset */ + uint32_t regextsel : 1; /* External Regulator Input Select */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_VCO. */ +typedef volatile struct ALT_CLKMGR_PERPLL_VCO_s ALT_CLKMGR_PERPLL_VCO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_VCO register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_VCO_OFST 0x0 + +/* + * Register : Peripheral PLL VCO Advanced Control Register - misc + * + * Contains VCO control signals and other PLL control signals need to be + * controllable through register. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled + * [12:1] | RW | 0x1 | Loop Bandwidth Adjust + * [13] | RW | 0x0 | Fast Locking Enable + * [14] | RW | 0x1 | Saturation Enable + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Loop Bandwidth Adjust Enabled - bwadjen + * + * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth + * Adjust field. + * + * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 + * value of the VCO Control Register. The M divided by 2 is the upper 12 bits + * (12:1) of the M field in the VCO register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_MSB 0 +/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJEN field value from a register. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Loop Bandwidth Adjust - bwadj + * + * Provides Loop Bandwidth Adjust value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_MSB 12 +/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET_MSK 0x00001ffe +/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_CLR_MSK 0xffffe001 +/* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJ field value from a register. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) +/* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJ register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) + +/* + * Field : Fast Locking Enable - fasten + * + * Enables fast locking circuit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_MSB 13 +/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_MISC_FASTEN field value from a register. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CLKMGR_PERPLL_MISC_FASTEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Saturation Enable - saten + * + * Enables saturation behavior. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_MSB 14 +/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_MISC_SATEN field value from a register. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CLKMGR_PERPLL_MISC_SATEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_MISC. + */ +struct ALT_CLKMGR_PERPLL_MISC_s +{ + uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */ + uint32_t bwadj : 12; /* Loop Bandwidth Adjust */ + uint32_t fasten : 1; /* Fast Locking Enable */ + uint32_t saten : 1; /* Saturation Enable */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_MISC. */ +typedef volatile struct ALT_CLKMGR_PERPLL_MISC_s ALT_CLKMGR_PERPLL_MISC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_MISC register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_MISC_OFST 0x4 + +/* + * Register : Peripheral PLL C0 Control Register for Clock emac0_clk - emac0clk + * + * Contains settings that control clock emac0_clk generated from the C0 output of + * the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK. + */ +struct ALT_CLKMGR_PERPLL_EMAC0CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_EMAC0CLK_s ALT_CLKMGR_PERPLL_EMAC0CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_EMAC0CLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_OFST 0x8 + +/* + * Register : Peripheral PLL C1 Control Register for Clock emac1_clk - emac1clk + * + * Contains settings that control clock emac1_clk generated from the C1 output of + * the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK. + */ +struct ALT_CLKMGR_PERPLL_EMAC1CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_EMAC1CLK_s ALT_CLKMGR_PERPLL_EMAC1CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_EMAC1CLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_OFST 0xc + +/* + * Register : Peripheral PLL C2 Control Register for Clock periph_qspi_clk - perqspiclk + * + * Contains settings that control clock periph_qspi_clk generated from the C2 + * output of the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK. + */ +struct ALT_CLKMGR_PERPLL_PERQSPICLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_PERQSPICLK_s ALT_CLKMGR_PERPLL_PERQSPICLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_PERQSPICLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_OFST 0x10 + +/* + * Register : Peripheral PLL C3 Control Register for Clock periph_nand_sdmmc_clk - pernandsdmmcclk + * + * Contains settings that control clock periph_nand_sdmmc_clk generated from the C3 + * output of the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK. + */ +struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST 0x14 + +/* + * Register : Peripheral PLL C4 Control Register for Clock periph_base_clk - perbaseclk + * + * Contains settings that control clock periph_base_clk generated from the C4 + * output of the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_PERBASECLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_PERBASECLK. + */ +struct ALT_CLKMGR_PERPLL_PERBASECLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERBASECLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_PERBASECLK_s ALT_CLKMGR_PERPLL_PERBASECLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_PERBASECLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_OFST 0x18 + +/* + * Register : Peripheral PLL C5 Control Register for Clock s2f_user1_clk - s2fuser1clk + * + * Contains settings that control clock s2f_user1_clk generated from the C5 output + * of the Peripheral PLL. + * + * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK. + */ +struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s ALT_CLKMGR_PERPLL_S2FUSER1CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_S2FUSER1CLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST 0x1c + +/* + * Register : Enable Register - en + * + * Contains fields that control clock enables for clocks derived from the + * Peripheral PLL + * + * 1: The clock is enabled. + * + * 0: The clock is disabled. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | emac0_clk Enable + * [1] | RW | 0x1 | emac1_clk Enable + * [2] | RW | 0x1 | usb_mp_clk Enable + * [3] | RW | 0x1 | spi_m_clk Enable + * [4] | RW | 0x1 | can0_clk Enable + * [5] | RW | 0x1 | can1_clk Enable + * [6] | RW | 0x1 | gpio_clk Enable + * [7] | RW | 0x1 | s2f_user1_clk Enable + * [8] | RW | 0x1 | sdmmc_clk Enable + * [9] | RW | 0x1 | nand_x_clk Enable + * [10] | RW | 0x1 | nand_clk Enable + * [11] | RW | 0x1 | qspi_clk Enable + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_clk Enable - emac0clk + * + * Enables clock emac0_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_MSB 0 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC0CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : emac1_clk Enable - emac1clk + * + * Enables clock emac1_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC1CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : usb_mp_clk Enable - usbclk + * + * Enables clock usb_mp_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_USBCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_PERPLL_EN_USBCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : spi_m_clk Enable - spimclk + * + * Enables clock spi_m_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_SPIMCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : can0_clk Enable - can0clk + * + * Enables clock can0_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_MSB 4 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_CAN0CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : can1_clk Enable - can1clk + * + * Enables clock can1_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_MSB 5 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_CAN1CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : gpio_clk Enable - gpioclk + * + * Enables clock gpio_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_MSB 6 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_GPIOCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : s2f_user1_clk Enable - s2fuser1clk + * + * Enables clock s2f_user1_clk output. + * + * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_MSB 7 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : sdmmc_clk Enable - sdmmcclk + * + * Enables clock sdmmc_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_SDMMCCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : nand_x_clk Enable - nandxclk + * + * Enables clock nand_x_clk output + * + * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and + * the nand_x_clk Enable should always be asserted before the nand_clk Enable is + * asserted. A brief delay is also required between switching the enables (8 * + * nand_clk period). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_MSB 9 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_NANDXCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : nand_clk Enable - nandclk + * + * Enables clock nand_clk output + * + * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and + * the nand_x_clk Enable should always be asserted before the nand_clk Enable is + * asserted. A brief delay is also required between switching the enables (8 * + * nand_clk period). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_MSB 10 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_NANDCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CLKMGR_PERPLL_EN_NANDCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : qspi_clk Enable - qspiclk + * + * Enables clock qspi_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_MSB 11 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_QSPICLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CLKMGR_PERPLL_EN_QSPICLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_EN. + */ +struct ALT_CLKMGR_PERPLL_EN_s +{ + uint32_t emac0clk : 1; /* emac0_clk Enable */ + uint32_t emac1clk : 1; /* emac1_clk Enable */ + uint32_t usbclk : 1; /* usb_mp_clk Enable */ + uint32_t spimclk : 1; /* spi_m_clk Enable */ + uint32_t can0clk : 1; /* can0_clk Enable */ + uint32_t can1clk : 1; /* can1_clk Enable */ + uint32_t gpioclk : 1; /* gpio_clk Enable */ + uint32_t s2fuser1clk : 1; /* s2f_user1_clk Enable */ + uint32_t sdmmcclk : 1; /* sdmmc_clk Enable */ + uint32_t nandxclk : 1; /* nand_x_clk Enable */ + uint32_t nandclk : 1; /* nand_clk Enable */ + uint32_t qspiclk : 1; /* qspi_clk Enable */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_EN. */ +typedef volatile struct ALT_CLKMGR_PERPLL_EN_s ALT_CLKMGR_PERPLL_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_EN register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_EN_OFST 0x20 + +/* + * Register : Divide Register - div + * + * Contains fields that control clock dividers for clocks derived from the + * Peripheral PLL + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [2:0] | RW | 0x0 | USB Clock Divider + * [5:3] | RW | 0x0 | SPI Master Clock Divider + * [8:6] | RW | 0x0 | CAN0 Clock Divider + * [11:9] | RW | 0x0 | CAN1 Clock Divider + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB Clock Divider - usbclk + * + * The usb_mp_clk is divided down from the periph_base_clk by the value specified + * in this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------- + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK 0x00000007 +/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_DIV_USBCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_DIV_USBCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : SPI Master Clock Divider - spimclk + * + * The spi_m_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------- + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_MSB 5 +/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK 0x00000038 +/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_CLR_MSK 0xffffffc7 +/* The reset value of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_DIV_SPIMCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(value) (((value) & 0x00000038) >> 3) +/* Produces a ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET(value) (((value) << 3) & 0x00000038) + +/* + * Field : CAN0 Clock Divider - can0clk + * + * The can0_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------- + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK 0x000001c0 +/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_CLR_MSK 0xfffffe3f +/* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN0CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(value) (((value) & 0x000001c0) >> 6) +/* Produces a ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET(value) (((value) << 6) & 0x000001c0) + +/* + * Field : CAN1 Clock Divider - can1clk + * + * The can1_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------- + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_MSB 11 +/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK 0x00000e00 +/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_CLR_MSK 0xfffff1ff +/* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN1CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(value) (((value) & 0x00000e00) >> 9) +/* Produces a ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET(value) (((value) << 9) & 0x00000e00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_DIV. + */ +struct ALT_CLKMGR_PERPLL_DIV_s +{ + uint32_t usbclk : 3; /* USB Clock Divider */ + uint32_t spimclk : 3; /* SPI Master Clock Divider */ + uint32_t can0clk : 3; /* CAN0 Clock Divider */ + uint32_t can1clk : 3; /* CAN1 Clock Divider */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_DIV. */ +typedef volatile struct ALT_CLKMGR_PERPLL_DIV_s ALT_CLKMGR_PERPLL_DIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_DIV register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_DIV_OFST 0x24 + +/* + * Register : GPIO Divide Register - gpiodiv + * + * Contains a field that controls the clock divider for the GPIO De-bounce clock. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [23:0] | RW | 0x1 | GPIO De-bounce Clock Divider + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO De-bounce Clock Divider - gpiodbclk + * + * The gpio_db_clk is divided down from the periph_base_clk by the value plus one + * specified in this field. The value 0 (divide by 1) is illegal. A value of 1 + * indicates divide by 2, 2 divide by 3, etc. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 23 +/* The width in bits of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 24 +/* The mask used to set the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x00ffffff +/* The mask used to clear the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xff000000 +/* The reset value of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x00ffffff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x00ffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_GPIODIV. + */ +struct ALT_CLKMGR_PERPLL_GPIODIV_s +{ + uint32_t gpiodbclk : 24; /* GPIO De-bounce Clock Divider */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_GPIODIV. */ +typedef volatile struct ALT_CLKMGR_PERPLL_GPIODIV_s ALT_CLKMGR_PERPLL_GPIODIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_GPIODIV register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x28 + +/* + * Register : Flash Clock Source Register - src + * + * Contains fields that select the source clocks for the flash controllers. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [1:0] | RW | 0x1 | SDMMC Clock Source + * [3:2] | RW | 0x1 | NAND Clock Source + * [5:4] | RW | 0x1 | QSPI Clock Source + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDMMC Clock Source - sdmmc + * + * Selects the source clock for the SDMMC. + * + * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:---------------------- + * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk + * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK | 0x1 | main_nand_sdmmc_clk + * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK | 0x2 | periph_nand_sdmmc_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC + * + * f2s_periph_ref_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC + * + * main_nand_sdmmc_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC + * + * periph_nand_sdmmc_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_MSB 1 +/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET_MSK 0x00000003 +/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK 0xfffffffc +/* The reset value of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_SRC_SDMMC field value from a register. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_SRC_SDMMC register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : NAND Clock Source - nand + * + * Selects the source clock for the NAND. + * + * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:---------------------- + * ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk + * ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK | 0x1 | main_nand_sdmmc_clk + * ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK | 0x2 | periph_nand_sdmmc_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND + * + * f2s_periph_ref_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND + * + * main_nand_sdmmc_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND + * + * periph_nand_sdmmc_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_MSB 3 +/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_SET_MSK 0x0000000c +/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_SRC_NAND field value from a register. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_CLKMGR_PERPLL_SRC_NAND register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : QSPI Clock Source - qspi + * + * Selects the source clock for the QSPI. + * + * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------- + * ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk + * ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK | 0x1 | main_qspi_clk + * ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK | 0x2 | periph_qspi_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI + * + * f2s_periph_ref_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI + * + * main_qspi_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI + * + * periph_qspi_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_MSB 5 +/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET_MSK 0x00000030 +/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK 0xffffffcf +/* The reset value of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_SRC_QSPI field value from a register. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_CLKMGR_PERPLL_SRC_QSPI register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET(value) (((value) << 4) & 0x00000030) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_SRC. + */ +struct ALT_CLKMGR_PERPLL_SRC_s +{ + uint32_t sdmmc : 2; /* SDMMC Clock Source */ + uint32_t nand : 2; /* NAND Clock Source */ + uint32_t qspi : 2; /* QSPI Clock Source */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_SRC. */ +typedef volatile struct ALT_CLKMGR_PERPLL_SRC_s ALT_CLKMGR_PERPLL_SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_SRC register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_SRC_OFST 0x2c + +/* + * Register : Peripheral PLL Output Counter Reset Ack Status Register - stat + * + * Contains Output Clock Counter Reset acknowledge status. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [5:0] | R | 0x0 | Output Counter Reset Acknowledge + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Output Counter Reset Acknowledge - outresetack + * + * These read only bits per PLL output indicate that the PLL has received the + * Output Reset Counter request and has gracefully stopped the respective PLL + * output clock. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------- + * ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle + * ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK + * + * Idle + */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK + * + * Output Counter Acknowledge received. + */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_MSB 5 +/* The width in bits of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f +/* The mask used to clear the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK field value from a register. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_STAT. + */ +struct ALT_CLKMGR_PERPLL_STAT_s +{ + const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_STAT. */ +typedef volatile struct ALT_CLKMGR_PERPLL_STAT_s ALT_CLKMGR_PERPLL_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_STAT register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_STAT_OFST 0x30 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CLKMGR_PERPLL. + */ +struct ALT_CLKMGR_PERPLL_s +{ + volatile ALT_CLKMGR_PERPLL_VCO_t vco; /* ALT_CLKMGR_PERPLL_VCO */ + volatile ALT_CLKMGR_PERPLL_MISC_t misc; /* ALT_CLKMGR_PERPLL_MISC */ + volatile ALT_CLKMGR_PERPLL_EMAC0CLK_t emac0clk; /* ALT_CLKMGR_PERPLL_EMAC0CLK */ + volatile ALT_CLKMGR_PERPLL_EMAC1CLK_t emac1clk; /* ALT_CLKMGR_PERPLL_EMAC1CLK */ + volatile ALT_CLKMGR_PERPLL_PERQSPICLK_t perqspiclk; /* ALT_CLKMGR_PERPLL_PERQSPICLK */ + volatile ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t pernandsdmmcclk; /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */ + volatile ALT_CLKMGR_PERPLL_PERBASECLK_t perbaseclk; /* ALT_CLKMGR_PERPLL_PERBASECLK */ + volatile ALT_CLKMGR_PERPLL_S2FUSER1CLK_t s2fuser1clk; /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */ + volatile ALT_CLKMGR_PERPLL_EN_t en; /* ALT_CLKMGR_PERPLL_EN */ + volatile ALT_CLKMGR_PERPLL_DIV_t div; /* ALT_CLKMGR_PERPLL_DIV */ + volatile ALT_CLKMGR_PERPLL_GPIODIV_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */ + volatile ALT_CLKMGR_PERPLL_SRC_t src; /* ALT_CLKMGR_PERPLL_SRC */ + volatile ALT_CLKMGR_PERPLL_STAT_t stat; /* ALT_CLKMGR_PERPLL_STAT */ + volatile uint32_t _pad_0x34_0x40[3]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_CLKMGR_PERPLL. */ +typedef volatile struct ALT_CLKMGR_PERPLL_s ALT_CLKMGR_PERPLL_t; +/* The struct declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */ +struct ALT_CLKMGR_PERPLL_raw_s +{ + volatile uint32_t vco; /* ALT_CLKMGR_PERPLL_VCO */ + volatile uint32_t misc; /* ALT_CLKMGR_PERPLL_MISC */ + volatile uint32_t emac0clk; /* ALT_CLKMGR_PERPLL_EMAC0CLK */ + volatile uint32_t emac1clk; /* ALT_CLKMGR_PERPLL_EMAC1CLK */ + volatile uint32_t perqspiclk; /* ALT_CLKMGR_PERPLL_PERQSPICLK */ + volatile uint32_t pernandsdmmcclk; /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */ + volatile uint32_t perbaseclk; /* ALT_CLKMGR_PERPLL_PERBASECLK */ + volatile uint32_t s2fuser1clk; /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */ + volatile uint32_t en; /* ALT_CLKMGR_PERPLL_EN */ + volatile uint32_t div; /* ALT_CLKMGR_PERPLL_DIV */ + volatile uint32_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */ + volatile uint32_t src; /* ALT_CLKMGR_PERPLL_SRC */ + volatile uint32_t stat; /* ALT_CLKMGR_PERPLL_STAT */ + volatile uint32_t _pad_0x34_0x40[3]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */ +typedef volatile struct ALT_CLKMGR_PERPLL_raw_s ALT_CLKMGR_PERPLL_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : SDRAM PLL Group - ALT_CLKMGR_SDRPLL + * SDRAM PLL Group + * + * Contains registers with settings for the SDRAM PLL. + * + */ +/* + * Register : SDRAM PLL VCO Control Register - vco + * + * Contains settings that control the SDRAM PLL VCO. The VCO output frequency is + * the input frequency multiplied by the numerator (M+1) and divided by the + * denominator (N+1). + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [0] | RW | 0x1 | BG PWRDN + * [1] | RW | 0x0 | Enable + * [2] | RW | 0x1 | Power down + * [15:3] | RW | 0x1 | Numerator (M) + * [21:16] | RW | 0x1 | Denominator (N) + * [23:22] | RW | 0x0 | Clock Source + * [24] | RW | 0x0 | SDRAM All Output Counter Reset + * [30:25] | RW | 0x0 | Output Counter Reset + * [31] | RW | 0x1 | External Regulator Input Select + * + */ +/* + * Field : BG PWRDN - bgpwrdn + * + * If '1', powers down bandgap. If '0', bandgap is not power down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_MSB 0 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable - en + * + * If '1', VCO is enabled. If '0', VCO is in reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_MSB 1 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_EN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_EN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Power down - pwrdn + * + * If '1', power down analog circuitry. If '0', analog circuitry not powered down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_MSB 2 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_PWRDN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Numerator (M) - numer + * + * Numerator in VCO output frequency equation. For incremental frequency change, if + * the new value lead to less than 20% of the frequency change, this value can be + * changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_MSB 15 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_WIDTH 13 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK 0x0000fff8 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK 0xffff0007 +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_NUMER field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_NUMER register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) + +/* + * Field : Denominator (N) - denom + * + * Denominator in VCO output frequency equation. For incremental frequency change, + * if the new value lead to less than 20% of the frequency change, this value can + * be changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_MSB 21 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_DENOM field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_DENOM register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : Clock Source - ssrc + * + * Controls the VCO input clock source. The PLL must by bypassed to eosc1_clk + * before changing this field. + * + * Qsys and user documenation refer to f2s_sdram_ref_clk as f2h_sdram_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------ + * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 | 0x0 | eosc1_clk + * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 | 0x1 | eosc2_clk + * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF | 0x2 | f2s_sdram_ref_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC + * + * eosc1_clk + */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC + * + * eosc2_clk + */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC + * + * f2s_sdram_ref_clk + */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_MSB 23 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET_MSK 0x00c00000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK 0xff3fffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_SSRC field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(value) (((value) & 0x00c00000) >> 22) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_SSRC register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(value) (((value) << 22) & 0x00c00000) + +/* + * Field : SDRAM All Output Counter Reset - outresetall + * + * Before releasing Bypass, All Output Counter Reset must be set and cleared by + * software for correct clock operation. + * + * If '1', Reset phase multiplexer and output counter state. So that after the + * assertion all the clocks output are start from rising edge align. + * + * If '0', phase multiplexer and output counter state not reset and no change to + * the phase of the clock outputs. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_MSB 24 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Output Counter Reset - outreset + * + * Resets the individual PLL output counter. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * LSB 'outreset[0]' corresponds to PLL output clock C0, etc. + * + * If set to '1', reset output divider, no clock output from counter. + * + * If set to '0', counter is not reset. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_MSB 30 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET_MSK 0x7e000000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK 0x81ffffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRST field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) + +/* + * Field : External Regulator Input Select - regextsel + * + * If set to '1', the external regulator is selected for the PLL. + * + * If set to '0', the internal regulator is slected. + * + * It is strongly recommended to select the external regulator while the PLL is not + * enabled (in reset), and then disable the external regulater once the PLL + * becomes enabled. Software should simulateously update the 'Enable' bit and the + * 'External Regulator Input Select' in the same write access to the VCO register. + * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be + * set, and vice versa. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_MSB 31 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_VCO. + */ +struct ALT_CLKMGR_SDRPLL_VCO_s +{ + uint32_t bgpwrdn : 1; /* BG PWRDN */ + uint32_t en : 1; /* Enable */ + uint32_t pwrdn : 1; /* Power down */ + uint32_t numer : 13; /* Numerator (M) */ + uint32_t denom : 6; /* Denominator (N) */ + uint32_t ssrc : 2; /* Clock Source */ + uint32_t outresetall : 1; /* SDRAM All Output Counter Reset */ + uint32_t outreset : 6; /* Output Counter Reset */ + uint32_t regextsel : 1; /* External Regulator Input Select */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_VCO. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_VCO_s ALT_CLKMGR_SDRPLL_VCO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_VCO register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_VCO_OFST 0x0 + +/* + * Register : SDRAM PLL VCO Advanced Control Register - ctrl + * + * Contains VCO control signals and other PLL control signals need to be + * controllable through register. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled + * [12:1] | RW | 0x1 | Loop Bandwidth Adjust + * [13] | RW | 0x0 | Fast Locking Enable + * [14] | RW | 0x1 | Saturation Enable + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Loop Bandwidth Adjust Enabled - bwadjen + * + * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth + * Adjust field. + * + * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 + * value of the VCO Control Register. The M divided by 2 is the upper 12 bits + * (12:1) of the M field in the VCO register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_MSB 0 +/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJEN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Loop Bandwidth Adjust - bwadj + * + * Provides Loop Bandwidth Adjust value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_MSB 12 +/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET_MSK 0x00001ffe +/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_CLR_MSK 0xffffe001 +/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJ field value from a register. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) +/* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) + +/* + * Field : Fast Locking Enable - fasten + * + * Enables fast locking circuit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_MSB 13 +/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_CTL_FASTEN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Saturation Enable - saten + * + * Enables saturation behavior. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_MSB 14 +/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_CTL_SATEN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CLKMGR_SDRPLL_CTL_SATEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_CTL. + */ +struct ALT_CLKMGR_SDRPLL_CTL_s +{ + uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */ + uint32_t bwadj : 12; /* Loop Bandwidth Adjust */ + uint32_t fasten : 1; /* Fast Locking Enable */ + uint32_t saten : 1; /* Saturation Enable */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_CTL. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_CTL_s ALT_CLKMGR_SDRPLL_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_CTL register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_CTL_OFST 0x4 + +/* + * Register : SDRAM PLL C0 Control Register for Clock ddr_dqs_clk - ddrdqsclk + * + * Contains settings that control clock ddr_dqs_clk generated from the C0 output of + * the SDRAM PLL. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [20:9] | RW | 0x0 | Phase Shift + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +/* + * Field : Phase Shift - phase + * + * Increment the phase of the VCO output by the value in this field multiplied by + * 45 degrees. The accumulated phase shift is the total shifted amount since the + * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco + * control register. In order to guarantee the phase shift to a known value, 'SDRAM + * clocks output phase align' bit should be asserted before programming this field. + * + * This field is only writeable by SW when it is zero. HW updates this field in + * real time as the phase adjustment is being made. SW may poll this field + * waiting for zero indicating the phase adjustment has completed by HW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_MSB 20 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK 0x001ffe00 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_CLR_MSK 0xffe001ff +/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) +/* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK. + */ +struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t phase : 12; /* Phase Shift */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s ALT_CLKMGR_SDRPLL_DDRDQSCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQSCLK register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST 0x8 + +/* + * Register : SDRAM PLL C1 Control Register for Clock ddr_2x_dqs_clk - ddr2xdqsclk + * + * Contains settings that control clock ddr_2x_dqs_clk generated from the C1 output + * of the SDRAM PLL. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [20:9] | RW | 0x0 | Phase Shift + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +/* + * Field : Phase Shift - phase + * + * Increment the phase of the VCO output by the value in this field multiplied by + * 45 degrees. The accumulated phase shift is the total shifted amount since the + * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco + * control register. In order to guarantee the phase shift to a known value, 'SDRAM + * clocks output phase align' bit should be asserted before programming this field. + * + * This field is only writeable by SW when it is zero. HW updates this field in + * real time as the phase adjustment is being made. SW may poll this field + * waiting for zero indicating the phase adjustment has completed by HW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_MSB 20 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK 0x001ffe00 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_CLR_MSK 0xffe001ff +/* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) +/* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK. + */ +struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t phase : 12; /* Phase Shift */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST 0xc + +/* + * Register : SDRAM PLL C2 Control Register for Clock ddr_dq_clk - ddrdqclk + * + * Contains settings that control clock ddr_dq_clk generated from the C2 output of + * the SDRAM PLL. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [20:9] | RW | 0x0 | Phase Shift + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +/* + * Field : Phase Shift - phase + * + * Increment the phase of the VCO output by the value in this field multiplied by + * 45 degrees. The accumulated phase shift is the total shifted amount since the + * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco + * control register. In order to guarantee the phase shift to a known value, 'SDRAM + * clocks output phase align' bit should be asserted before programming this field. + * + * This field is only writeable by SW when it is zero. HW updates this field in + * real time as the phase adjustment is being made. SW may poll this field + * waiting for zero indicating the phase adjustment has completed by HW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_MSB 20 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK 0x001ffe00 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_CLR_MSK 0xffe001ff +/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) +/* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK. + */ +struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t phase : 12; /* Phase Shift */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s ALT_CLKMGR_SDRPLL_DDRDQCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQCLK register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST 0x10 + +/* + * Register : SDRAM PLL C5 Control Register for Clock s2f_user2_clk - s2fuser2clk + * + * Contains settings that control clock s2f_user2_clk generated from the C5 output + * of the SDRAM PLL. + * + * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [20:9] | RW | 0x0 | Phase Shift + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT field value from a register. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +/* + * Field : Phase Shift - phase + * + * Increment the phase of the VCO output by the value in this field multiplied by + * 45 degrees. The accumulated phase shift is the total shifted amount since the + * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco + * control register. In order to guarantee the phase shift to a known value, 'SDRAM + * clocks output phase align' bit should be asserted before programming this field. + * + * This field is only writeable by SW when it is zero. HW updates this field in + * real time as the phase adjustment is being made. SW may poll this field + * waiting for zero indicating the phase adjustment has completed by HW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_MSB 20 +/* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK 0x001ffe00 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_CLR_MSK 0xffe001ff +/* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE field value from a register. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) +/* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK. + */ +struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t phase : 12; /* Phase Shift */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST 0x14 + +/* + * Register : Enable Register - en + * + * Contains fields that control the SDRAM Clock Group enables generated from the + * SDRAM PLL clock outputs. + * + * 1: The clock is enabled. + * + * 0: The clock is disabled. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | RW | 0x1 | ddr_dqs_clk Enable + * [1] | RW | 0x1 | ddr_2x_dqs_clk Enable + * [2] | RW | 0x1 | ddr_dq_clk Enable + * [3] | RW | 0x1 | s2f_user2_clk Enable + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ddr_dqs_clk Enable - ddrdqsclk + * + * Enables clock ddr_dqs_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_MSB 0 +/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : ddr_2x_dqs_clk Enable - ddr2xdqsclk + * + * Enables clock ddr_2x_dqs_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ddr_dq_clk Enable - ddrdqclk + * + * Enables clock ddr_dq_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : s2f_user2_clk Enable - s2fuser2clk + * + * Enables clock s2f_user2_clk output. + * + * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_EN. + */ +struct ALT_CLKMGR_SDRPLL_EN_s +{ + uint32_t ddrdqsclk : 1; /* ddr_dqs_clk Enable */ + uint32_t ddr2xdqsclk : 1; /* ddr_2x_dqs_clk Enable */ + uint32_t ddrdqclk : 1; /* ddr_dq_clk Enable */ + uint32_t s2fuser2clk : 1; /* s2f_user2_clk Enable */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_EN. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_EN_s ALT_CLKMGR_SDRPLL_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_EN register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_EN_OFST 0x18 + +/* + * Register : SDRAM PLL Output Counter Reset Ack Status Register - stat + * + * Contains Output Clock Counter Reset acknowledge status. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [5:0] | R | 0x0 | Output Counter Reset Acknowledge + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Output Counter Reset Acknowledge - outresetack + * + * These read only bits per PLL output indicate that the PLL has received the + * Output Reset Counter request and has gracefully stopped the respective PLL + * output clock. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------- + * ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle + * ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK + * + * Idle + */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK + * + * Output Counter Acknowledge received. + */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_MSB 5 +/* The width in bits of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f +/* The mask used to clear the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_STAT. + */ +struct ALT_CLKMGR_SDRPLL_STAT_s +{ + const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_STAT. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_STAT_s ALT_CLKMGR_SDRPLL_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_STAT register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_STAT_OFST 0x1c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CLKMGR_SDRPLL. + */ +struct ALT_CLKMGR_SDRPLL_s +{ + volatile ALT_CLKMGR_SDRPLL_VCO_t vco; /* ALT_CLKMGR_SDRPLL_VCO */ + volatile ALT_CLKMGR_SDRPLL_CTL_t ctrl; /* ALT_CLKMGR_SDRPLL_CTL */ + volatile ALT_CLKMGR_SDRPLL_DDRDQSCLK_t ddrdqsclk; /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */ + volatile ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t ddr2xdqsclk; /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */ + volatile ALT_CLKMGR_SDRPLL_DDRDQCLK_t ddrdqclk; /* ALT_CLKMGR_SDRPLL_DDRDQCLK */ + volatile ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t s2fuser2clk; /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */ + volatile ALT_CLKMGR_SDRPLL_EN_t en; /* ALT_CLKMGR_SDRPLL_EN */ + volatile ALT_CLKMGR_SDRPLL_STAT_t stat; /* ALT_CLKMGR_SDRPLL_STAT */ +}; + +/* The typedef declaration for register group ALT_CLKMGR_SDRPLL. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_s ALT_CLKMGR_SDRPLL_t; +/* The struct declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */ +struct ALT_CLKMGR_SDRPLL_raw_s +{ + volatile uint32_t vco; /* ALT_CLKMGR_SDRPLL_VCO */ + volatile uint32_t ctrl; /* ALT_CLKMGR_SDRPLL_CTL */ + volatile uint32_t ddrdqsclk; /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */ + volatile uint32_t ddr2xdqsclk; /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */ + volatile uint32_t ddrdqclk; /* ALT_CLKMGR_SDRPLL_DDRDQCLK */ + volatile uint32_t s2fuser2clk; /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */ + volatile uint32_t en; /* ALT_CLKMGR_SDRPLL_EN */ + volatile uint32_t stat; /* ALT_CLKMGR_SDRPLL_STAT */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_raw_s ALT_CLKMGR_SDRPLL_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CLKMGR. + */ +struct ALT_CLKMGR_s +{ + volatile ALT_CLKMGR_CTL_t ctrl; /* ALT_CLKMGR_CTL */ + volatile ALT_CLKMGR_BYPASS_t bypass; /* ALT_CLKMGR_BYPASS */ + volatile ALT_CLKMGR_INTER_t inter; /* ALT_CLKMGR_INTER */ + volatile ALT_CLKMGR_INTREN_t intren; /* ALT_CLKMGR_INTREN */ + volatile ALT_CLKMGR_DBCTL_t dbctrl; /* ALT_CLKMGR_DBCTL */ + volatile ALT_CLKMGR_STAT_t stat; /* ALT_CLKMGR_STAT */ + volatile uint32_t _pad_0x18_0x3f[10]; /* *UNDEFINED* */ + volatile ALT_CLKMGR_MAINPLL_t mainpllgrp; /* ALT_CLKMGR_MAINPLL */ + volatile ALT_CLKMGR_PERPLL_t perpllgrp; /* ALT_CLKMGR_PERPLL */ + volatile ALT_CLKMGR_SDRPLL_t sdrpllgrp; /* ALT_CLKMGR_SDRPLL */ + volatile uint32_t _pad_0xe0_0x200[72]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_CLKMGR. */ +typedef volatile struct ALT_CLKMGR_s ALT_CLKMGR_t; +/* The struct declaration for the raw register contents of register group ALT_CLKMGR. */ +struct ALT_CLKMGR_raw_s +{ + volatile uint32_t ctrl; /* ALT_CLKMGR_CTL */ + volatile uint32_t bypass; /* ALT_CLKMGR_BYPASS */ + volatile uint32_t inter; /* ALT_CLKMGR_INTER */ + volatile uint32_t intren; /* ALT_CLKMGR_INTREN */ + volatile uint32_t dbctrl; /* ALT_CLKMGR_DBCTL */ + volatile uint32_t stat; /* ALT_CLKMGR_STAT */ + volatile uint32_t _pad_0x18_0x3f[10]; /* *UNDEFINED* */ + volatile ALT_CLKMGR_MAINPLL_raw_t mainpllgrp; /* ALT_CLKMGR_MAINPLL */ + volatile ALT_CLKMGR_PERPLL_raw_t perpllgrp; /* ALT_CLKMGR_PERPLL */ + volatile ALT_CLKMGR_SDRPLL_raw_t sdrpllgrp; /* ALT_CLKMGR_SDRPLL */ + volatile uint32_t _pad_0xe0_0x200[72]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CLKMGR. */ +typedef volatile struct ALT_CLKMGR_raw_s ALT_CLKMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_CLKMGR_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h new file mode 100644 index 0000000000..1425708983 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_DMANONSECURE */ + +#ifndef __ALTERA_ALT_DMANONSECURE_H__ +#define __ALTERA_ALT_DMANONSECURE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : nonsecure DMA Module Address Space - ALT_DMANONSECURE + * nonsecure DMA Module Address Space + * + * Address space allocated to the nonsecure DMA. For detailed information about the + * use of this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click + * here[/url] to access the ARM documentation for the DMA-330. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_MSB 31 +/* The width in bits of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_DMANONSECURE_REG_FLD register field value. */ +#define ALT_DMANONSECURE_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_DMANONSECURE_REG_FLD register field value. */ +#define ALT_DMANONSECURE_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_DMANONSECURE_REG_FLD register field is UNKNOWN. */ +#define ALT_DMANONSECURE_REG_FLD_RESET 0x0 +/* Extracts the ALT_DMANONSECURE_REG_FLD field value from a register. */ +#define ALT_DMANONSECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_DMANONSECURE_REG_FLD register field value suitable for setting the register. */ +#define ALT_DMANONSECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_DMANONSECURE_REG. + */ +struct ALT_DMANONSECURE_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_DMANONSECURE_REG. */ +typedef volatile struct ALT_DMANONSECURE_REG_s ALT_DMANONSECURE_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_DMANONSECURE_REG register from the beginning of the component. */ +#define ALT_DMANONSECURE_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_DMANONSECURE. + */ +struct ALT_DMANONSECURE_s +{ + volatile ALT_DMANONSECURE_REG_t reg; /* ALT_DMANONSECURE_REG */ +}; + +/* The typedef declaration for register group ALT_DMANONSECURE. */ +typedef volatile struct ALT_DMANONSECURE_s ALT_DMANONSECURE_t; +/* The struct declaration for the raw register contents of register group ALT_DMANONSECURE. */ +struct ALT_DMANONSECURE_raw_s +{ + volatile uint32_t reg; /* ALT_DMANONSECURE_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_DMANONSECURE. */ +typedef volatile struct ALT_DMANONSECURE_raw_s ALT_DMANONSECURE_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_DMANONSECURE_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h new file mode 100644 index 0000000000..5941433268 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_DMASECURE */ + +#ifndef __ALTERA_ALT_DMASECURE_H__ +#define __ALTERA_ALT_DMASECURE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : secure DMA Module Address Space - ALT_DMASECURE + * secure DMA Module Address Space + * + * Address space allocated to the secure DMA. For detailed information about the + * use of this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click + * here[/url] to access the ARM documentation for the DMA-330. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_MSB 31 +/* The width in bits of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_DMASECURE_REG_FLD register field value. */ +#define ALT_DMASECURE_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_DMASECURE_REG_FLD register field value. */ +#define ALT_DMASECURE_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_DMASECURE_REG_FLD register field is UNKNOWN. */ +#define ALT_DMASECURE_REG_FLD_RESET 0x0 +/* Extracts the ALT_DMASECURE_REG_FLD field value from a register. */ +#define ALT_DMASECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_DMASECURE_REG_FLD register field value suitable for setting the register. */ +#define ALT_DMASECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_DMASECURE_REG. + */ +struct ALT_DMASECURE_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_DMASECURE_REG. */ +typedef volatile struct ALT_DMASECURE_REG_s ALT_DMASECURE_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_DMASECURE_REG register from the beginning of the component. */ +#define ALT_DMASECURE_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_DMASECURE. + */ +struct ALT_DMASECURE_s +{ + volatile ALT_DMASECURE_REG_t reg; /* ALT_DMASECURE_REG */ +}; + +/* The typedef declaration for register group ALT_DMASECURE. */ +typedef volatile struct ALT_DMASECURE_s ALT_DMASECURE_t; +/* The struct declaration for the raw register contents of register group ALT_DMASECURE. */ +struct ALT_DMASECURE_raw_s +{ + volatile uint32_t reg; /* ALT_DMASECURE_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_DMASECURE. */ +typedef volatile struct ALT_DMASECURE_raw_s ALT_DMASECURE_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_DMASECURE_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h new file mode 100644 index 0000000000..8bc4640161 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h @@ -0,0 +1,1991 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_GPIO */ + +#ifndef __ALTERA_ALT_GPIO_H__ +#define __ALTERA_ALT_GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : GPIO Module - ALT_GPIO + * GPIO Module + * + * Registers in the GPIO module + * + */ +/* + * Register : Port A Data Register - gpio_swporta_dr + * + * This GPIO Data register is used to input or output data + * + * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [28:0] | RW | 0x0 | Port A Data + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port A Data - gpio_swporta_dr + * + * Values written to this register are output on the I/O signals of the GPIO Data + * Register, if the corresponding data direction bits for GPIO Data Direction Field + * are set to Output mode. The value read back is equal to the last value written + * to this register. + * + * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_MSB 28 +/* The width in bits of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_WIDTH 29 +/* The mask used to set the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_RESET 0x0 +/* Extracts the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR field value from a register. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value suitable for setting the register. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_SWPORTA_DR. + */ +struct ALT_GPIO_SWPORTA_DR_s +{ + uint32_t gpio_swporta_dr : 29; /* Port A Data */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_SWPORTA_DR. */ +typedef volatile struct ALT_GPIO_SWPORTA_DR_s ALT_GPIO_SWPORTA_DR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_SWPORTA_DR register from the beginning of the component. */ +#define ALT_GPIO_SWPORTA_DR_OFST 0x0 +/* The address of the ALT_GPIO_SWPORTA_DR register. */ +#define ALT_GPIO_SWPORTA_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DR_OFST)) + +/* + * Register : Port A Data Direction Register - gpio_swporta_ddr + * + * This register establishes the direction of each corresponding GPIO Data Field + * Bit. + * + * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [28:0] | RW | 0x0 | Port A Data Direction Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port A Data Direction Field - gpio_swporta_ddr + * + * Values written to this register independently control the direction of the + * corresponding data bit in the Port A Data Register. + * + * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:----------------- + * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN | 0x0 | Input Direction + * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT | 0x1 | Output Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR + * + * Input Direction + */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN 0x0 +/* + * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR + * + * Output Direction + */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_MSB 28 +/* The width in bits of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_WIDTH 29 +/* The mask used to set the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_RESET 0x0 +/* Extracts the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR field value from a register. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value suitable for setting the register. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_SWPORTA_DDR. + */ +struct ALT_GPIO_SWPORTA_DDR_s +{ + uint32_t gpio_swporta_ddr : 29; /* Port A Data Direction Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_SWPORTA_DDR. */ +typedef volatile struct ALT_GPIO_SWPORTA_DDR_s ALT_GPIO_SWPORTA_DDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_SWPORTA_DDR register from the beginning of the component. */ +#define ALT_GPIO_SWPORTA_DDR_OFST 0x4 +/* The address of the ALT_GPIO_SWPORTA_DDR register. */ +#define ALT_GPIO_SWPORTA_DDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DDR_OFST)) + +/* + * Register : Interrupt Enable Register - gpio_inten + * + * The Interrupt enable register allows interrupts for each bit of the Port A data + * register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [28:0] | RW | 0x0 | Interrupt Enable Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Enable Field - gpio_inten + * + * Allows each bit of Port A Data Register to be configured for interrupt + * capability. Interrupts are disabled on the corresponding bits of Port A Data + * Register if the corresponding data direction register is set to Output. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------- + * ALT_GPIO_INTEN_GPIO_INTEN_E_DIS | 0x0 | Disable Interrupt on Port A + * ALT_GPIO_INTEN_GPIO_INTEN_E_EN | 0x1 | Enable Interrupt on Port A + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN + * + * Disable Interrupt on Port A + */ +#define ALT_GPIO_INTEN_GPIO_INTEN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN + * + * Enable Interrupt on Port A + */ +#define ALT_GPIO_INTEN_GPIO_INTEN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_MSB 28 +/* The width in bits of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_WIDTH 29 +/* The mask used to set the ALT_GPIO_INTEN_GPIO_INTEN register field value. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INTEN_GPIO_INTEN register field value. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_RESET 0x0 +/* Extracts the ALT_GPIO_INTEN_GPIO_INTEN field value from a register. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INTEN_GPIO_INTEN register field value suitable for setting the register. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INTEN. + */ +struct ALT_GPIO_INTEN_s +{ + uint32_t gpio_inten : 29; /* Interrupt Enable Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INTEN. */ +typedef volatile struct ALT_GPIO_INTEN_s ALT_GPIO_INTEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INTEN register from the beginning of the component. */ +#define ALT_GPIO_INTEN_OFST 0x30 +/* The address of the ALT_GPIO_INTEN register. */ +#define ALT_GPIO_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTEN_OFST)) + +/* + * Register : Interrupt Mask Register - gpio_intmask + * + * Controls which pins cause interrupts on Port A Data Register inputs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [28:0] | RW | 0x0 | Interrupt Mask Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Mask Field - gpio_intmask + * + * Controls whether an interrupt on Port A Data Register can generate an interrupt + * to the interrupt controller by not masking it. The unmasked status can be read + * as well as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------- + * ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS | 0x0 | Interrupt bits are unmasked + * ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK + * + * Interrupt bits are unmasked + */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS 0x0 +/* + * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK + * + * Mask Interrupt + */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_MSB 28 +/* The width in bits of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_WIDTH 29 +/* The mask used to set the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_RESET 0x0 +/* Extracts the ALT_GPIO_INTMSK_GPIO_INTMSK field value from a register. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INTMSK_GPIO_INTMSK register field value suitable for setting the register. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INTMSK. + */ +struct ALT_GPIO_INTMSK_s +{ + uint32_t gpio_intmask : 29; /* Interrupt Mask Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INTMSK. */ +typedef volatile struct ALT_GPIO_INTMSK_s ALT_GPIO_INTMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INTMSK register from the beginning of the component. */ +#define ALT_GPIO_INTMSK_OFST 0x34 +/* The address of the ALT_GPIO_INTMSK register. */ +#define ALT_GPIO_INTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTMSK_OFST)) + +/* + * Register : Interrupt Level Register - gpio_inttype_level + * + * The interrupt level register defines the type of interrupt (edge or level). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------- + * [28:0] | RW | 0x0 | Interrupt Level Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Level Field - gpio_inttype_level + * + * This field controls the type of interrupt that can occur on the Port A Data + * Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:---------------- + * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL | 0x0 | Level-sensitive + * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL + * + * Level-sensitive + */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL + * + * Edge-sensitive + */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_MSB 28 +/* The width in bits of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_WIDTH 29 +/* The mask used to set the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_RESET 0x0 +/* Extracts the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL field value from a register. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value suitable for setting the register. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INTTYPE_LEVEL. + */ +struct ALT_GPIO_INTTYPE_LEVEL_s +{ + uint32_t gpio_inttype_level : 29; /* Interrupt Level Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INTTYPE_LEVEL. */ +typedef volatile struct ALT_GPIO_INTTYPE_LEVEL_s ALT_GPIO_INTTYPE_LEVEL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INTTYPE_LEVEL register from the beginning of the component. */ +#define ALT_GPIO_INTTYPE_LEVEL_OFST 0x38 +/* The address of the ALT_GPIO_INTTYPE_LEVEL register. */ +#define ALT_GPIO_INTTYPE_LEVEL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTTYPE_LEVEL_OFST)) + +/* + * Register : Interrupt Polarity Register - gpio_int_polarity + * + * Controls the Polarity of Interrupts that can occur on inputs of Port A Data + * Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [28:0] | RW | 0x0 | Polarity Control Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Polarity Control Field - gpio_int_polarity + * + * Controls the polarity of edge or level sensitivity that can occur on input of + * Port A Data Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------ + * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW | 0x0 | Active low + * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL + * + * Active low + */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL + * + * Active high + */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_MSB 28 +/* The width in bits of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_WIDTH 29 +/* The mask used to set the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_RESET 0x0 +/* Extracts the ALT_GPIO_INT_POL_GPIO_INT_POL field value from a register. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INT_POL_GPIO_INT_POL register field value suitable for setting the register. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INT_POL. + */ +struct ALT_GPIO_INT_POL_s +{ + uint32_t gpio_int_polarity : 29; /* Polarity Control Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INT_POL. */ +typedef volatile struct ALT_GPIO_INT_POL_s ALT_GPIO_INT_POL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INT_POL register from the beginning of the component. */ +#define ALT_GPIO_INT_POL_OFST 0x3c +/* The address of the ALT_GPIO_INT_POL register. */ +#define ALT_GPIO_INT_POL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INT_POL_OFST)) + +/* + * Register : Interrupt Status Register - gpio_intstatus + * + * The Interrupt status is reported for all Port A Data Register Bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [28:0] | RW | 0x0 | Interrupt Status Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Status Field - gpio_intstatus + * + * Interrupt status of Port A Data Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------ + * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT | 0x0 | Inactive + * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT + * + * Inactive + */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT + * + * Active + */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_MSB 28 +/* The width in bits of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_WIDTH 29 +/* The mask used to set the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_RESET 0x0 +/* Extracts the ALT_GPIO_INTSTAT_GPIO_INTSTAT field value from a register. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value suitable for setting the register. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INTSTAT. + */ +struct ALT_GPIO_INTSTAT_s +{ + uint32_t gpio_intstatus : 29; /* Interrupt Status Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INTSTAT. */ +typedef volatile struct ALT_GPIO_INTSTAT_s ALT_GPIO_INTSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INTSTAT register from the beginning of the component. */ +#define ALT_GPIO_INTSTAT_OFST 0x40 +/* The address of the ALT_GPIO_INTSTAT register. */ +#define ALT_GPIO_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTSTAT_OFST)) + +/* + * Register : Raw Interrupt Status Register - gpio_raw_intstatus + * + * This is the Raw Interrupt Status Register for Port A Data Register. It is used + * with the Interrupt Mask Register to allow interrupts from the Port A Data + * Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [28:0] | RW | 0x0 | Raw Interrupt Status Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Raw Interrupt Status Field - gpio_raw_intstatus + * + * Raw interrupt of status of Port A Data Register (premasking bits) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------ + * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT | 0x0 | Inactive + * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT + * + * Inactive + */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT + * + * Active + */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_MSB 28 +/* The width in bits of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_WIDTH 29 +/* The mask used to set the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_RESET 0x0 +/* Extracts the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT field value from a register. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value suitable for setting the register. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_RAW_INTSTAT. + */ +struct ALT_GPIO_RAW_INTSTAT_s +{ + uint32_t gpio_raw_intstatus : 29; /* Raw Interrupt Status Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_RAW_INTSTAT. */ +typedef volatile struct ALT_GPIO_RAW_INTSTAT_s ALT_GPIO_RAW_INTSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_RAW_INTSTAT register from the beginning of the component. */ +#define ALT_GPIO_RAW_INTSTAT_OFST 0x44 +/* The address of the ALT_GPIO_RAW_INTSTAT register. */ +#define ALT_GPIO_RAW_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_RAW_INTSTAT_OFST)) + +/* + * Register : Debounce Enable Register - gpio_debounce + * + * Debounces each IO Pin + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [28:0] | RW | 0x0 | ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : gpio_debounce + * + * Controls whether an external signal that is the source of an interrupt needs to + * be debounced to remove any spurious glitches. A signal must be valid for two + * periods of an external clock (gpio_db_clk) before it is internally processed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------- + * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS | 0x0 | No debounce + * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN | 0x1 | Enable debounce + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE + * + * No debounce + */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE + * + * Enable debounce + */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_MSB 28 +/* The width in bits of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_WIDTH 29 +/* The mask used to set the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_RESET 0x0 +/* Extracts the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE field value from a register. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value suitable for setting the register. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_DEBOUNCE. + */ +struct ALT_GPIO_DEBOUNCE_s +{ + uint32_t gpio_debounce : 29; /* ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_DEBOUNCE. */ +typedef volatile struct ALT_GPIO_DEBOUNCE_s ALT_GPIO_DEBOUNCE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_DEBOUNCE register from the beginning of the component. */ +#define ALT_GPIO_DEBOUNCE_OFST 0x48 +/* The address of the ALT_GPIO_DEBOUNCE register. */ +#define ALT_GPIO_DEBOUNCE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_DEBOUNCE_OFST)) + +/* + * Register : Clear Interrupt Register - gpio_porta_eoi + * + * Port A Data Register interrupt handling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [28:0] | W | 0x0 | Clears Edge Interrupts Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clears Edge Interrupts Field - gpio_porta_eoi + * + * Controls the clearing of edge type interrupts from the Port A Data Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------- + * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR | 0x0 | No interrupt clear + * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI + * + * No interrupt clear + */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI + * + * Clear interrupt + */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_MSB 28 +/* The width in bits of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_WIDTH 29 +/* The mask used to set the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_RESET 0x0 +/* Extracts the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI field value from a register. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value suitable for setting the register. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_PORTA_EOI. + */ +struct ALT_GPIO_PORTA_EOI_s +{ + uint32_t gpio_porta_eoi : 29; /* Clears Edge Interrupts Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_PORTA_EOI. */ +typedef volatile struct ALT_GPIO_PORTA_EOI_s ALT_GPIO_PORTA_EOI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_PORTA_EOI register from the beginning of the component. */ +#define ALT_GPIO_PORTA_EOI_OFST 0x4c +/* The address of the ALT_GPIO_PORTA_EOI register. */ +#define ALT_GPIO_PORTA_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_PORTA_EOI_OFST)) + +/* + * Register : External Port A Register - gpio_ext_porta + * + * The external port register is used to input data to the metastability flops. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [28:0] | R | 0x0 | External Port Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : External Port Field - gpio_ext_porta + * + * When Port A Data Register is configured as Input, then reading this location + * reads the values on the signals. When the data direction of Port A Data Register + * is set as Output, reading this location reads Port A Data Register + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_MSB 28 +/* The width in bits of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_WIDTH 29 +/* The mask used to set the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_RESET 0x0 +/* Extracts the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA field value from a register. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value suitable for setting the register. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_EXT_PORTA. + */ +struct ALT_GPIO_EXT_PORTA_s +{ + const uint32_t gpio_ext_porta : 29; /* External Port Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_EXT_PORTA. */ +typedef volatile struct ALT_GPIO_EXT_PORTA_s ALT_GPIO_EXT_PORTA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_EXT_PORTA register from the beginning of the component. */ +#define ALT_GPIO_EXT_PORTA_OFST 0x50 +/* The address of the ALT_GPIO_EXT_PORTA register. */ +#define ALT_GPIO_EXT_PORTA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_EXT_PORTA_OFST)) + +/* + * Register : Synchronization Level Register - gpio_ls_sync + * + * The Synchronization level register is used to synchronize input with l4_mp_clk + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [0] | RW | 0x0 | Synchronization Level Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Synchronization Level Field - gpio_ls_sync + * + * The level-sensitive interrupts is synchronized to l4_mp_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------- + * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC | 0x0 | No synchronization to l4_mp_clk + * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC | 0x1 | Synchronize to l4_mp_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC + * + * No synchronization to l4_mp_clk + */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC 0x0 +/* + * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC + * + * Synchronize to l4_mp_clk + */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_MSB 0 +/* The width in bits of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_WIDTH 1 +/* The mask used to set the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET_MSK 0x00000001 +/* The mask used to clear the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_CLR_MSK 0xfffffffe +/* The reset value of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_RESET 0x0 +/* Extracts the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC field value from a register. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value suitable for setting the register. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_LS_SYNC. + */ +struct ALT_GPIO_LS_SYNC_s +{ + uint32_t gpio_ls_sync : 1; /* Synchronization Level Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_LS_SYNC. */ +typedef volatile struct ALT_GPIO_LS_SYNC_s ALT_GPIO_LS_SYNC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_LS_SYNC register from the beginning of the component. */ +#define ALT_GPIO_LS_SYNC_OFST 0x60 +/* The address of the ALT_GPIO_LS_SYNC register. */ +#define ALT_GPIO_LS_SYNC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_LS_SYNC_OFST)) + +/* + * Register : ID Code Register - gpio_id_code + * + * GPIO ID code. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [31:0] | R | 0x0 | ID Code Field + * + */ +/* + * Field : ID Code Field - gpio_id_code + * + * Chip identification + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_MSB 31 +/* The width in bits of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_WIDTH 32 +/* The mask used to set the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_CLR_MSK 0x00000000 +/* The reset value of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_RESET 0x0 +/* Extracts the ALT_GPIO_ID_CODE_GPIO_ID_CODE field value from a register. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value suitable for setting the register. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_ID_CODE. + */ +struct ALT_GPIO_ID_CODE_s +{ + const uint32_t gpio_id_code : 32; /* ID Code Field */ +}; + +/* The typedef declaration for register ALT_GPIO_ID_CODE. */ +typedef volatile struct ALT_GPIO_ID_CODE_s ALT_GPIO_ID_CODE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_ID_CODE register from the beginning of the component. */ +#define ALT_GPIO_ID_CODE_OFST 0x64 +/* The address of the ALT_GPIO_ID_CODE register. */ +#define ALT_GPIO_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_ID_CODE_OFST)) + +/* + * Register : GPIO Version Register - gpio_ver_id_code + * + * GPIO Component Version + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------------------------ + * [31:0] | R | 0x3230382a | ASCII Component Version Field + * + */ +/* + * Field : ASCII Component Version Field - gpio_ver_id_code + * + * ASCII value for each number in the version, followed by *. For example. + * 32_30_31_2A represents the version 2.01 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_MSB 31 +/* The width in bits of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_WIDTH 32 +/* The mask used to set the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_CLR_MSK 0x00000000 +/* The reset value of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_RESET 0x3230382a +/* Extracts the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE field value from a register. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value suitable for setting the register. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_VER_ID_CODE. + */ +struct ALT_GPIO_VER_ID_CODE_s +{ + const uint32_t gpio_ver_id_code : 32; /* ASCII Component Version Field */ +}; + +/* The typedef declaration for register ALT_GPIO_VER_ID_CODE. */ +typedef volatile struct ALT_GPIO_VER_ID_CODE_s ALT_GPIO_VER_ID_CODE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_VER_ID_CODE register from the beginning of the component. */ +#define ALT_GPIO_VER_ID_CODE_OFST 0x6c +/* The address of the ALT_GPIO_VER_ID_CODE register. */ +#define ALT_GPIO_VER_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_VER_ID_CODE_OFST)) + +/* + * Register : Configuration Register 2 - gpio_config_reg2 + * + * Specifies the bit width of port A. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------- + * [4:0] | R | 0x1c | Port A Width (less 1) + * [9:5] | R | 0x7 | Port B Width (less 1) + * [14:10] | R | 0x7 | Port C Width (less 1) + * [19:15] | R | 0x7 | Port D Width (less 1) + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port A Width (less 1) - encoded_id_pwidth_a + * + * Specifies the width of GPIO Port A. The value 28 represents the 29-bit width + * less one. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A + * + * Width (less 1) of 8 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A + * + * Width (less 1) of 29 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS 0x1c + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB 4 +/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK 0x0000001f +/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET 0x1c +/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A field value from a register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET(value) (((value) << 0) & 0x0000001f) + +/* + * Field : Port B Width (less 1) - encoded_id_pwidth_b + * + * Specifies the width of GPIO Port B. Ignored because there is no Port B in the + * GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B + * + * Width (less 1) of 8 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B + * + * Width (less 1) of 29 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS 0x1c + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB 9 +/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK 0x000003e0 +/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK 0xfffffc1f +/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET 0x7 +/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B field value from a register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET(value) (((value) & 0x000003e0) >> 5) +/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET(value) (((value) << 5) & 0x000003e0) + +/* + * Field : Port C Width (less 1) - encoded_id_pwidth_c + * + * Specifies the width of GPIO Port C. Ignored because there is no Port C in the + * GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C + * + * Width (less 1) of 8 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C + * + * Width (less 1) of 29 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS 0x1c + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB 14 +/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK 0x00007c00 +/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK 0xffff83ff +/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET 0x7 +/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C field value from a register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET(value) (((value) & 0x00007c00) >> 10) +/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET(value) (((value) << 10) & 0x00007c00) + +/* + * Field : Port D Width (less 1) - encoded_id_pwidth_d + * + * Specifies the width of GPIO Port D. Ignored because there is no Port D in the + * GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D + * + * Width (less 1) of 8 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D + * + * Width (less 1) of 29 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS 0x1c + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB 19 +/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK 0x000f8000 +/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK 0xfff07fff +/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET 0x7 +/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D field value from a register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET(value) (((value) & 0x000f8000) >> 15) +/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET(value) (((value) << 15) & 0x000f8000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_CFG_REG2. + */ +struct ALT_GPIO_CFG_REG2_s +{ + const uint32_t encoded_id_pwidth_a : 5; /* Port A Width (less 1) */ + const uint32_t encoded_id_pwidth_b : 5; /* Port B Width (less 1) */ + const uint32_t encoded_id_pwidth_c : 5; /* Port C Width (less 1) */ + const uint32_t encoded_id_pwidth_d : 5; /* Port D Width (less 1) */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_CFG_REG2. */ +typedef volatile struct ALT_GPIO_CFG_REG2_s ALT_GPIO_CFG_REG2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_CFG_REG2 register from the beginning of the component. */ +#define ALT_GPIO_CFG_REG2_OFST 0x70 +/* The address of the ALT_GPIO_CFG_REG2 register. */ +#define ALT_GPIO_CFG_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG2_OFST)) + +/* + * Register : Configuration Register 1 - gpio_config_reg1 + * + * Reports settings of various GPIO configuration parameters + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [1:0] | R | 0x2 | APB DATA WIDTH + * [3:2] | R | 0x0 | NUM PORTS + * [4] | R | 0x1 | PORT A SINGLE CTL + * [5] | R | 0x1 | PORT B SINGLE CTL + * [6] | R | 0x1 | PORT C SINGLE CTL + * [7] | R | 0x1 | PORT D SINGLE CTL + * [8] | R | 0x0 | HW PORTA + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [12] | R | 0x1 | Port A Interrupt Field + * [13] | R | 0x1 | Debounce Field + * [14] | R | 0x1 | Encoded GPIO Parameters Available + * [15] | R | 0x1 | ID Field + * [20:16] | R | 0x1f | Encoded ID Width Field + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : APB DATA WIDTH - apb_data_width + * + * Fixed to support an ABP data bus width of 32-bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------- + * ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_APB_DATA_WIDTH + * + * APB Data Width = 32-bits + */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB 1 +/* The width in bits of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH 2 +/* The mask used to set the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET 0x2 +/* Extracts the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH field value from a register. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : NUM PORTS - num_ports + * + * The value of this register is fixed at one port (Port A). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------- + * ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA | 0x0 | Number of GPIO Ports = 1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_NUM_PORTS + * + * Number of GPIO Ports = 1 + */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_MSB 3 +/* The width in bits of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_WIDTH 2 +/* The mask used to set the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET_MSK 0x0000000c +/* The mask used to clear the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_RESET 0x0 +/* Extracts the ALT_GPIO_CFG_REG1_NUM_PORTS field value from a register. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_GPIO_CFG_REG1_NUM_PORTS register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : PORT A SINGLE CTL - porta_single_ctl + * + * Indicates the mode of operation of Port A to be software controlled only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------------------- + * ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB 4 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef +/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : PORT B SINGLE CTL - portb_single_ctl + * + * Indicates the mode of operation of Port B to be software controlled only. + * Ignored because there is no Port B in the GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------------------- + * ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB 5 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : PORT C SINGLE CTL - portc_single_ctl + * + * Indicates the mode of operation of Port C to be software controlled only. + * Ignored because there is no Port C in the GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------------------- + * ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB 6 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : PORT D SINGLE CTL - portd_single_ctl + * + * Indicates the mode of operation of Port D to be software controlled only. + * Ignored because there is no Port D in the GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------------------- + * ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB 7 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f +/* The reset value of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : HW PORTA - hw_porta + * + * The value is fixed to enable Port A configuration to be controlled by software + * only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------- + * ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD | 0x0 | Software Configuration Control Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_HW_PORTA + * + * Software Configuration Control Enabled + */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_MSB 8 +/* The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_SET_MSK 0x00000100 +/* The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_CLR_MSK 0xfffffeff +/* The reset value of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_RESET 0x0 +/* Extracts the ALT_GPIO_CFG_REG1_HW_PORTA field value from a register. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_GPIO_CFG_REG1_HW_PORTA register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Port A Interrupt Field - porta_intr + * + * The value of this field is fixed to allow interrupts on Port A. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR | 0x1 | Port A Interrupts Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_INTR + * + * Port A Interrupts Enabled + */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_MSB 12 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK 0xffffefff +/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTA_INTR field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_GPIO_CFG_REG1_PORTA_INTR register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Debounce Field - debounce + * + * The value of this field is fixed to allow debouncing of the Port A signals. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA | 0x1 | Debounce is Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_DEBOUNCE + * + * Debounce is Enabled + */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_MSB 13 +/* The width in bits of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_DEBOUNCE field value from a register. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_GPIO_CFG_REG1_DEBOUNCE register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Encoded GPIO Parameters Available - add_encoded_params + * + * Fixed to allow the indentification of the Designware IP component. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Enable IP indentification + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS + * + * Enable IP indentification + */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB 14 +/* The width in bits of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK 0x00004000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK 0xffffbfff +/* The reset value of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS field value from a register. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : ID Field - gpio_id + * + * Provides an ID code value + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE | 0x1 | GPIO ID Code + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_GPIO_ID + * + * GPIO ID Code + */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_MSB 15 +/* The width in bits of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_SET_MSK 0x00008000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_CLR_MSK 0xffff7fff +/* The reset value of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_GPIO_ID field value from a register. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_GPIO_CFG_REG1_GPIO_ID register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Encoded ID Width Field - encoded_id_width + * + * This value is fixed at 32 bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH | 0x1f | Width of ID Field + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_ENC_ID_WIDTH + * + * Width of ID Field + */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB 20 +/* The width in bits of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK 0x001f0000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK 0xffe0ffff +/* The reset value of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET 0x1f +/* Extracts the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH field value from a register. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16) +/* Produces a ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_CFG_REG1. + */ +struct ALT_GPIO_CFG_REG1_s +{ + const uint32_t apb_data_width : 2; /* APB DATA WIDTH */ + const uint32_t num_ports : 2; /* NUM PORTS */ + const uint32_t porta_single_ctl : 1; /* PORT A SINGLE CTL */ + const uint32_t portb_single_ctl : 1; /* PORT B SINGLE CTL */ + const uint32_t portc_single_ctl : 1; /* PORT C SINGLE CTL */ + const uint32_t portd_single_ctl : 1; /* PORT D SINGLE CTL */ + const uint32_t hw_porta : 1; /* HW PORTA */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t porta_intr : 1; /* Port A Interrupt Field */ + const uint32_t debounce : 1; /* Debounce Field */ + const uint32_t add_encoded_params : 1; /* Encoded GPIO Parameters Available */ + const uint32_t gpio_id : 1; /* ID Field */ + const uint32_t encoded_id_width : 5; /* Encoded ID Width Field */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_CFG_REG1. */ +typedef volatile struct ALT_GPIO_CFG_REG1_s ALT_GPIO_CFG_REG1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_CFG_REG1 register from the beginning of the component. */ +#define ALT_GPIO_CFG_REG1_OFST 0x74 +/* The address of the ALT_GPIO_CFG_REG1 register. */ +#define ALT_GPIO_CFG_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG1_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_GPIO. + */ +struct ALT_GPIO_s +{ + volatile ALT_GPIO_SWPORTA_DR_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */ + volatile ALT_GPIO_SWPORTA_DDR_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */ + volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */ + volatile ALT_GPIO_INTEN_t gpio_inten; /* ALT_GPIO_INTEN */ + volatile ALT_GPIO_INTMSK_t gpio_intmask; /* ALT_GPIO_INTMSK */ + volatile ALT_GPIO_INTTYPE_LEVEL_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */ + volatile ALT_GPIO_INT_POL_t gpio_int_polarity; /* ALT_GPIO_INT_POL */ + volatile ALT_GPIO_INTSTAT_t gpio_intstatus; /* ALT_GPIO_INTSTAT */ + volatile ALT_GPIO_RAW_INTSTAT_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */ + volatile ALT_GPIO_DEBOUNCE_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */ + volatile ALT_GPIO_PORTA_EOI_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */ + volatile ALT_GPIO_EXT_PORTA_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile ALT_GPIO_LS_SYNC_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */ + volatile ALT_GPIO_ID_CODE_t gpio_id_code; /* ALT_GPIO_ID_CODE */ + volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */ + volatile ALT_GPIO_VER_ID_CODE_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */ + volatile ALT_GPIO_CFG_REG2_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */ + volatile ALT_GPIO_CFG_REG1_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */ + volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_GPIO. */ +typedef volatile struct ALT_GPIO_s ALT_GPIO_t; +/* The struct declaration for the raw register contents of register group ALT_GPIO. */ +struct ALT_GPIO_raw_s +{ + volatile uint32_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */ + volatile uint32_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */ + volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */ + volatile uint32_t gpio_inten; /* ALT_GPIO_INTEN */ + volatile uint32_t gpio_intmask; /* ALT_GPIO_INTMSK */ + volatile uint32_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */ + volatile uint32_t gpio_int_polarity; /* ALT_GPIO_INT_POL */ + volatile uint32_t gpio_intstatus; /* ALT_GPIO_INTSTAT */ + volatile uint32_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */ + volatile uint32_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */ + volatile uint32_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */ + volatile uint32_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile uint32_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */ + volatile uint32_t gpio_id_code; /* ALT_GPIO_ID_CODE */ + volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */ + volatile uint32_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */ + volatile uint32_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */ + volatile uint32_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */ + volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_GPIO. */ +typedef volatile struct ALT_GPIO_raw_s ALT_GPIO_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_GPIO_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h new file mode 100644 index 0000000000..b50543a884 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h @@ -0,0 +1,5940 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_I2C */ + +#ifndef __ALTERA_ALT_I2C_H__ +#define __ALTERA_ALT_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : I2C Module - ALT_I2C + * I2C Module + * + * Registers in the I2C module + * + */ +/* + * Register : Control Register - ic_con + * + * This register can be written only when the I2C is disabled, which corresponds to + * the Bit [0] of the Enable Register being set to 0. Writes at other times have no + * effect. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | Master Enable + * [2:1] | RW | 0x2 | Master Speed Control + * [3] | RW | 0x1 | Slave Address Size + * [4] | RW | 0x1 | Master Address Size + * [5] | RW | 0x1 | Restart Enable + * [6] | RW | 0x1 | Slave Disable + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Enable - master_mode + * + * This bit controls whether the i2c master is enabled. + * + * NOTE: Software should ensure that if this bit is written with '1', then bit 6 + * should also be written with a '1'. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:---------------- + * ALT_I2C_CON_MST_MOD_E_DIS | 0x0 | master disabled + * ALT_I2C_CON_MST_MOD_E_EN | 0x1 | master enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_MST_MOD + * + * master disabled + */ +#define ALT_I2C_CON_MST_MOD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_MST_MOD + * + * master enabled + */ +#define ALT_I2C_CON_MST_MOD_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_MSB 0 +/* The width in bits of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_MST_MOD register field value. */ +#define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CON_MST_MOD register field value. */ +#define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_RESET 0x1 +/* Extracts the ALT_I2C_CON_MST_MOD field value from a register. */ +#define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CON_MST_MOD register field value suitable for setting the register. */ +#define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Master Speed Control - speed + * + * These bits control at which speed the I2C operates, its setting is relevant only + * if one is operating the I2C in master mode. Hardware protects against illegal + * values being programmed by software. This field should be programmed only with + * standard or fast speed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:--------------------------- + * ALT_I2C_CON_SPEED_E_STANDARD | 0x1 | standard mode (100 kbit/s) + * ALT_I2C_CON_SPEED_E_FAST | 0x2 | fast mode (400 kbit/s) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_SPEED + * + * standard mode (100 kbit/s) + */ +#define ALT_I2C_CON_SPEED_E_STANDARD 0x1 +/* + * Enumerated value for register field ALT_I2C_CON_SPEED + * + * fast mode (400 kbit/s) + */ +#define ALT_I2C_CON_SPEED_E_FAST 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_MSB 2 +/* The width in bits of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_WIDTH 2 +/* The mask used to set the ALT_I2C_CON_SPEED register field value. */ +#define ALT_I2C_CON_SPEED_SET_MSK 0x00000006 +/* The mask used to clear the ALT_I2C_CON_SPEED register field value. */ +#define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_RESET 0x2 +/* Extracts the ALT_I2C_CON_SPEED field value from a register. */ +#define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_I2C_CON_SPEED register field value suitable for setting the register. */ +#define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006) + +/* + * Field : Slave Address Size - ic_10bitaddr_slave + * + * When acting as a slave, this bit controls whether the I2C responds to 7- or + * 10-bit addresses. In 7-bit addressing, only the lower 7 bits of the Slave + * Address Register are compared. The I2C responds will only respond to 10-bit + * addressing transfers that match the full 10 bits of the Slave Address register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT | 0x0 | 7-bit addressing + * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT | 0x1 | 10-bit addressing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV + * + * 7-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV + * + * 10-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3 +/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_10BITADDR_SLV field value from a register. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_CON_IC_10BITADDR_SLV register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Master Address Size - ic_10bitaddr_master + * + * This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing + * mode when acting as a master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT | 0x0 | 7-bit addressing + * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT | 0x1 | 10-bit addressing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST + * + * 7-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST + * + * 10-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4 +/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_10BITADDR_MST field value from a register. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_CON_IC_10BITADDR_MST register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Restart Enable - ic_restart_en + * + * Determines whether RESTART conditions may be sent when acting as a master. Some + * older slaves do not support handling RESTART conditions; however, RESTART + * conditions are used in several I2C operations. When RESTART is disabled, the + * master is prohibited from performing the following functions + * + * * Changing direction within a transfer (split), + * + * * Sending a START BYTE, + * + * * High-speed mode operation, + * + * * Combined format transfers in 7-bit addressing modes, + * + * * Read operation with a 10-bit address, + * + * * Sending multiple bytes per transfer, + * + * By replacing RESTART condition followed by a STOP and a subsequent START + * condition, split operations are broken down into multiple I2C transfers. If the + * above operations are performed, it will result in setting bit [6](tx_abort) of + * the Raw Interrupt Status Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------- + * ALT_I2C_CON_IC_RESTART_EN_E_DIS | 0x0 | restart master disable + * ALT_I2C_CON_IC_RESTART_EN_E_EN | 0x1 | restart master enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN + * + * restart master disable + */ +#define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN + * + * restart master enable + */ +#define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_MSB 5 +/* The width in bits of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_RESTART_EN register field value. */ +#define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_CON_IC_RESTART_EN register field value. */ +#define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_RESTART_EN field value from a register. */ +#define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_CON_IC_RESTART_EN register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Slave Disable - ic_slave_disable + * + * This bit controls whether I2C has its slave disabled. The slave will be + * disabled, after reset. + * + * NOTE: Software should ensure that if this bit is written with 0, then bit [0] of + * this register should also be written with a 0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------- + * ALT_I2C_CON_IC_SLV_DIS_E_DIS | 0x1 | slave disable + * ALT_I2C_CON_IC_SLV_DIS_E_EN | 0x0 | slave enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS + * + * slave disable + */ +#define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1 +/* + * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS + * + * slave enable + */ +#define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_MSB 6 +/* The width in bits of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_SLV_DIS register field value. */ +#define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_CON_IC_SLV_DIS register field value. */ +#define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_SLV_DIS field value from a register. */ +#define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_CON_IC_SLV_DIS register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CON. + */ +struct ALT_I2C_CON_s +{ + uint32_t master_mode : 1; /* Master Enable */ + uint32_t speed : 2; /* Master Speed Control */ + uint32_t ic_10bitaddr_slave : 1; /* Slave Address Size */ + uint32_t ic_10bitaddr_master : 1; /* Master Address Size */ + uint32_t ic_restart_en : 1; /* Restart Enable */ + uint32_t ic_slave_disable : 1; /* Slave Disable */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CON. */ +typedef volatile struct ALT_I2C_CON_s ALT_I2C_CON_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CON register from the beginning of the component. */ +#define ALT_I2C_CON_OFST 0x0 +/* The address of the ALT_I2C_CON register. */ +#define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST)) + +/* + * Register : Target Address Register - ic_tar + * + * This register can be written to only when the ic_enable register is set to 0. + * This register is 13 bits wide. All bits can be dynamically updated as long as + * any set of the following conditions are true, + * + * (Enable Register bit 0 is set to 0) or (Enable Register bit 0 is set to 1 AND + * (I2C is NOT engaged in any Master [tx, rx] operation [ic_status register + * mst_activity bit 5 is set to 0]) AND (I2C is enabled to operate in Master + * mode[ic_con bit[0] is set to one]) AND (there are NO entries in the TX FIFO + * Register [IC_STATUS bit [2] is set to 1]) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [9:0] | RW | 0x55 | Master Target Address + * [10] | RW | 0x0 | General Call OR Start + * [11] | RW | 0x0 | Special + * [12] | RW | 0x1 | Master Addressing Bit Control + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Target Address - ic_tar + * + * This is the target address for any master transaction. When transmitting a + * General Call, these bits are ignored. To generate a START BYTE, the CPU needs to + * write only once into these bits. If the ic_tar and ic_sar are the same, loopback + * exists but the FIFOs are shared between master and slave, so full loopback is + * not feasible. Only one direction loopback mode is supported (simplex), not + * duplex. A master cannot transmit to itself; it can transmit to only a slave. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_MSB 9 +/* The width in bits of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_WIDTH 10 +/* The mask used to set the ALT_I2C_TAR_IC_TAR register field value. */ +#define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff +/* The mask used to clear the ALT_I2C_TAR_IC_TAR register field value. */ +#define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_RESET 0x55 +/* Extracts the ALT_I2C_TAR_IC_TAR field value from a register. */ +#define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_I2C_TAR_IC_TAR register field value suitable for setting the register. */ +#define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff) + +/* + * Field : General Call OR Start - gc_or_start + * + * If bit 11 (SPECIAL) of this Register is set to 1, then this bit indicates + * whether a General Call or START byte command is to be performed by the I2C or + * General Call Address after issuing a General Call, only writes may be performed. + * Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the Raw + * Interrupt_Status register. The I2C remains in General Call mode until the + * special bit value (bit 11) is cleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------- + * ALT_I2C_TAR_GC_OR_START_E_GENCALL | 0x0 | General Call + * ALT_I2C_TAR_GC_OR_START_E_STARTBYTE | 0x1 | START Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_GC_OR_START + * + * General Call + */ +#define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_GC_OR_START + * + * START Byte + */ +#define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_MSB 10 +/* The width in bits of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_GC_OR_START register field value. */ +#define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_TAR_GC_OR_START register field value. */ +#define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_RESET 0x0 +/* Extracts the ALT_I2C_TAR_GC_OR_START field value from a register. */ +#define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_TAR_GC_OR_START register field value suitable for setting the register. */ +#define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Special - special + * + * This bit indicates whether software performs a General Call or START BYTE + * command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:-------------------------------------------- + * ALT_I2C_TAR_SPECIAL_E_GENCALL | 0x0 | Ignore bit 10 gc_or_start and use ic_tar + * : | | normally + * ALT_I2C_TAR_SPECIAL_E_STARTBYTE | 0x1 | Perform special I2C command as specified in + * : | | gc_or_start + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_SPECIAL + * + * Ignore bit 10 gc_or_start and use ic_tar normally + */ +#define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_SPECIAL + * + * Perform special I2C command as specified in gc_or_start + */ +#define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_MSB 11 +/* The width in bits of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_SPECIAL register field value. */ +#define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_TAR_SPECIAL register field value. */ +#define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_RESET 0x0 +/* Extracts the ALT_I2C_TAR_SPECIAL field value from a register. */ +#define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_TAR_SPECIAL register field value suitable for setting the register. */ +#define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Master Addressing Bit Control - ic_10bitaddr_master + * + * This bit controls whether the i2c starts its transfers in 7-bit or 10-bit + * addressing mode when acting as a master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------- + * ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 | 0x0 | Master Address, 7bit + * ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 | 0x1 | Master Address, 10bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST + * + * Master Address, 7bit + */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST + * + * Master Address, 10bit + */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12 +/* The width in bits of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff +/* The reset value of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1 +/* Extracts the ALT_I2C_TAR_IC_10BITADDR_MST field value from a register. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_I2C_TAR_IC_10BITADDR_MST register field value suitable for setting the register. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TAR. + */ +struct ALT_I2C_TAR_s +{ + uint32_t ic_tar : 10; /* Master Target Address */ + uint32_t gc_or_start : 1; /* General Call OR Start */ + uint32_t special : 1; /* Special */ + uint32_t ic_10bitaddr_master : 1; /* Master Addressing Bit Control */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TAR. */ +typedef volatile struct ALT_I2C_TAR_s ALT_I2C_TAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TAR register from the beginning of the component. */ +#define ALT_I2C_TAR_OFST 0x4 +/* The address of the ALT_I2C_TAR register. */ +#define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST)) + +/* + * Register : Slave Address Register - ic_sar + * + * Holds Address of Slave + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [9:0] | RW | 0x55 | Slave Address + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Slave Address - ic_sar + * + * The Slave Address register holds the slave address when the I2C is operating as + * a slave. For 7-bit addressing, only Field Bits [6:0] of the Slave Address + * Register are used. This register can be written only when the I2C interface is + * disabled, which corresponds to field bit 0 of the Enable Register being set to + * 0. Writes at other times have no effect. + * + * Note, the default values cannot be any of the reserved address locations: that + * is, + * + * 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not + * guaranteed if you program the Slave Address Register or Target Address Register + * to a reserved value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_MSB 9 +/* The width in bits of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_WIDTH 10 +/* The mask used to set the ALT_I2C_SAR_IC_SAR register field value. */ +#define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff +/* The mask used to clear the ALT_I2C_SAR_IC_SAR register field value. */ +#define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_RESET 0x55 +/* Extracts the ALT_I2C_SAR_IC_SAR field value from a register. */ +#define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_I2C_SAR_IC_SAR register field value suitable for setting the register. */ +#define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SAR. + */ +struct ALT_I2C_SAR_s +{ + uint32_t ic_sar : 10; /* Slave Address */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SAR. */ +typedef volatile struct ALT_I2C_SAR_s ALT_I2C_SAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SAR register from the beginning of the component. */ +#define ALT_I2C_SAR_OFST 0x8 +/* The address of the ALT_I2C_SAR register. */ +#define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST)) + +/* + * Register : Tx Rx Data and Command Register - ic_data_cmd + * + * This is the register the CPU writes to when filling the TX FIFO. Reading from + * this register returns bytes from RX FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------- + * [7:0] | RW | 0x0 | Tx Rx Data + * [8] | W | 0x0 | Master Read Write Control + * [9] | W | 0x0 | Generate Stop + * [10] | W | 0x0 | Generate Restart + * [31:11] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Tx Rx Data - dat + * + * This Field contains the data to be transmitted or received on the I2C bus. If + * you are writing to these bits and want to perform a read, bits 7:0 (dat) are + * ignored by the I2C. However, when you read from this register, these bits return + * the value of data received on the I2C interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_MSB 7 +/* The width in bits of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_WIDTH 8 +/* The mask used to set the ALT_I2C_DATA_CMD_DAT register field value. */ +#define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_DATA_CMD_DAT register field value. */ +#define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_DAT field value from a register. */ +#define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_DATA_CMD_DAT register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Master Read Write Control - cmd + * + * This bit controls whether a read or a write is performed. This bit does not + * control the direction when the I2C acts as a slave. It controls only the + * direction when it acts as a master. When a command is entered in the TX FIFO, + * this bit distinguishes the write and read commands. In slave-receiver mode, this + * bit is a 'don't care' because writes to this register are not required. In + * slave-transmitter mode, a '0' indicates that the CPU data is to be transmitted. + * When programming this bit, you should remember the following: attempting to + * perform a read operation after a General Call command has been sent results in a + * tx_abrt interrupt (bit 6 of the Raw Intr Status Register), unless bit 11 special + * in the Target Address Register has been cleared. If a '1' is written to this bit + * after receiving a RD_REQ interrupt, then a tx_abrt interrupt occurs. + * + * NOTE: It is possible that while attempting a master I2C read transfer on I2C, a + * RD_REQ interrupt may have occurred simultaneously due to a remote I2C master + * addressing I2C. In this type of scenario, I2C ignores the Data Cmd write, + * generates a tx_abrt interrupt, and waits to service the RD_REQ interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------- + * ALT_I2C_DATA_CMD_CMD_E_RD | 0x1 | Master Read + * ALT_I2C_DATA_CMD_CMD_E_WR | 0x0 | Master Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_CMD + * + * Master Read + */ +#define ALT_I2C_DATA_CMD_CMD_E_RD 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_CMD + * + * Master Write + */ +#define ALT_I2C_DATA_CMD_CMD_E_WR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_MSB 8 +/* The width in bits of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_CMD register field value. */ +#define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_DATA_CMD_CMD register field value. */ +#define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_CMD field value from a register. */ +#define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_DATA_CMD_CMD register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Generate Stop - stop + * + * This bit controls whether a STOP is issued after the byte is sent or received. + * + * 1 = STOP is issued after this byte, regardless of whether or not the Tx FIFO is + * empty. If the Tx FIFO is not empty, the master immediately tries to start a new + * transfer by issuing a START and arbitrating for the bus. + * + * 0 = STOP is not issued after this byte, regardless of whether or not the Tx FIFO + * is empty. If the Tx FIFO is not empty, the master continues the current transfer + * by sending/receiving data bytes according to the value of the CMD bit. If the Tx + * FIFO is empty, the master holds the SCL line low and stalls the bus until a new + * command is available in the Tx FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------ + * ALT_I2C_DATA_CMD_STOP_E_STOP | 0x1 | Issue Stop + * ALT_I2C_DATA_CMD_STOP_E_NO_STOP | 0x0 | Do Not Issue Stop + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_STOP + * + * Issue Stop + */ +#define ALT_I2C_DATA_CMD_STOP_E_STOP 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_STOP + * + * Do Not Issue Stop + */ +#define ALT_I2C_DATA_CMD_STOP_E_NO_STOP 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_MSB 9 +/* The width in bits of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_STOP register field value. */ +#define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_DATA_CMD_STOP register field value. */ +#define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_STOP field value from a register. */ +#define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_DATA_CMD_STOP register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Generate Restart - restart + * + * This bit controls whether a RESTART is issued before the byte is sent or + * received. + * + * 1 = A RESTART is issued before the data is sent/received (according to the value + * of CMD), regardless of whether or not the transfer direction is changing from + * the previous command. + * + * 0 = A RESTART is issued only if the transfer direction is changing from the + * previous command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:---------------------------------- + * ALT_I2C_DATA_CMD_RESTART_E_RESTART | 0x1 | Issue Restart + * ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE | 0x0 | Issue Restart On Direction Change + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART + * + * Issue Restart + */ +#define ALT_I2C_DATA_CMD_RESTART_E_RESTART 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART + * + * Issue Restart On Direction Change + */ +#define ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_MSB 10 +/* The width in bits of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_RESTART register field value. */ +#define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_DATA_CMD_RESTART register field value. */ +#define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_RESTART field value from a register. */ +#define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_DATA_CMD_RESTART register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DATA_CMD. + */ +struct ALT_I2C_DATA_CMD_s +{ + uint32_t dat : 8; /* Tx Rx Data */ + uint32_t cmd : 1; /* Master Read Write Control */ + uint32_t stop : 1; /* Generate Stop */ + uint32_t restart : 1; /* Generate Restart */ + uint32_t : 21; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DATA_CMD. */ +typedef volatile struct ALT_I2C_DATA_CMD_s ALT_I2C_DATA_CMD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DATA_CMD register from the beginning of the component. */ +#define ALT_I2C_DATA_CMD_OFST 0x10 +/* The address of the ALT_I2C_DATA_CMD register. */ +#define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST)) + +/* + * Register : Std Spd Clock SCL HCNT Register - ic_ss_scl_hcnt + * + * This register sets the SCL clock high-period count for standard speed. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [15:0] | RW | 0x190 | Std Spd SCL High Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Std Spd SCL High Period - ic_ss_scl_hcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock high-period count for + * standard speed. This register can be written only when the I2C interface is + * disabled which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect. The minimum valid value is 6; hardware prevents + * values less than this being written, and if attempted results in 6 being set. It + * is readable and writeable. + * + * NOTE: This register must not be programmed to a value higher than 65525, because + * I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter + * reaches a value of IC_SS_SCL_HCNT + 10. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15 +/* The width in bits of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190 +/* Extracts the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT field value from a register. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value suitable for setting the register. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SS_SCL_HCNT. + */ +struct ALT_I2C_SS_SCL_HCNT_s +{ + uint32_t ic_ss_scl_hcnt : 16; /* Std Spd SCL High Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SS_SCL_HCNT. */ +typedef volatile struct ALT_I2C_SS_SCL_HCNT_s ALT_I2C_SS_SCL_HCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SS_SCL_HCNT register from the beginning of the component. */ +#define ALT_I2C_SS_SCL_HCNT_OFST 0x14 +/* The address of the ALT_I2C_SS_SCL_HCNT register. */ +#define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST)) + +/* + * Register : Std Spd Clock SCL LCNT Register - ic_ss_scl_lcnt + * + * This register sets the SCL clock low-period count for standard speed + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [15:0] | RW | 0x1d6 | Std Spd SCL Low Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Std Spd SCL Low Period - ic_ss_scl_lcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock low period count for + * standard speed. This register can be written only when the I2C interface is + * disabled which corresponds to the Enable Register register being set to 0. + * Writes at other times have no effect. The minimum valid value is 8; hardware + * prevents values less than this from being written, and if attempted, results in + * 8 being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15 +/* The width in bits of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6 +/* Extracts the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT field value from a register. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value suitable for setting the register. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SS_SCL_LCNT. + */ +struct ALT_I2C_SS_SCL_LCNT_s +{ + uint32_t ic_ss_scl_lcnt : 16; /* Std Spd SCL Low Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SS_SCL_LCNT. */ +typedef volatile struct ALT_I2C_SS_SCL_LCNT_s ALT_I2C_SS_SCL_LCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SS_SCL_LCNT register from the beginning of the component. */ +#define ALT_I2C_SS_SCL_LCNT_OFST 0x18 +/* The address of the ALT_I2C_SS_SCL_LCNT register. */ +#define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST)) + +/* + * Register : Fast Spd Clock SCL HCNT Register - ic_fs_scl_hcnt + * + * This register sets the SCL clock high-period count for fast speed + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [15:0] | RW | 0x3c | Fast Spd SCL High Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Fast Spd SCL High Period - ic_fs_scl_hcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This register sets the SCL clock high-period count for + * fast speed. It is used in high-speed mode to send the Master Code and START BYTE + * or General CALL. This register goes away and becomes read-only returning 0s if + * in Standard Speed Mode. This register can be written only when the I2C interface + * is disabled, which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect. The minimum valid value is 6; hardware prevents + * values less than this from being written, and if attempted results in 6 being + * set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15 +/* The width in bits of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c +/* Extracts the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT field value from a register. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value suitable for setting the register. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SCL_HCNT. + */ +struct ALT_I2C_FS_SCL_HCNT_s +{ + uint32_t ic_fs_scl_hcnt : 16; /* Fast Spd SCL High Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SCL_HCNT. */ +typedef volatile struct ALT_I2C_FS_SCL_HCNT_s ALT_I2C_FS_SCL_HCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SCL_HCNT register from the beginning of the component. */ +#define ALT_I2C_FS_SCL_HCNT_OFST 0x1c +/* The address of the ALT_I2C_FS_SCL_HCNT register. */ +#define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST)) + +/* + * Register : Fast Spd Clock SCL LCNT Register - ic_fs_scl_lcnt + * + * This register sets the SCL clock low period count + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [15:0] | RW | 0x82 | Fast Spd SCL Low Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Fast Spd SCL Low Period - ic_fs_scl_lcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock low period count for + * fast speed. It is used in high-speed mode to send the Master Code and START BYTE + * or General CALL. This register can be written only when the I2C interface is + * disabled, which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect.The minimum valid value is 8; hardware prevents + * values less than this being written, and if attempted results in 8 being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15 +/* The width in bits of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82 +/* Extracts the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT field value from a register. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value suitable for setting the register. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SCL_LCNT. + */ +struct ALT_I2C_FS_SCL_LCNT_s +{ + uint32_t ic_fs_scl_lcnt : 16; /* Fast Spd SCL Low Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SCL_LCNT. */ +typedef volatile struct ALT_I2C_FS_SCL_LCNT_s ALT_I2C_FS_SCL_LCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SCL_LCNT register from the beginning of the component. */ +#define ALT_I2C_FS_SCL_LCNT_OFST 0x20 +/* The address of the ALT_I2C_FS_SCL_LCNT register. */ +#define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST)) + +/* + * Register : Interrupt Status Register - ic_intr_stat + * + * Each bit in this register has a corresponding mask bit in the Interrupt Mask + * Register. These bits are cleared by reading the matching Interrupt Clear + * Register. The unmasked raw versions of these bits are available in the Raw + * Interrupt Status Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [0] | R | 0x0 | Receiver Under + * [1] | R | 0x0 | Receiver Over + * [2] | R | 0x0 | Receive Full + * [3] | R | 0x0 | Interrupt Transmit Over + * [4] | R | 0x0 | Interrupt Transmit Empty + * [5] | R | 0x0 | Interrupt Read Request + * [6] | R | 0x0 | Interrupt TX Abort + * [7] | R | 0x0 | Interrupt RX Done + * [8] | R | 0x0 | Interrupt R_activity + * [9] | R | 0x0 | Interrupt Stop Detect + * [10] | R | 0x0 | Interrupt Start Detect + * [11] | R | 0x0 | Interrupt General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receiver Under - r_rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the Tx Rx Data and Command Register. If the module is disabled, + * Enable Register is set to 0, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_UNDER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_INTR_STAT_R_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Receiver Over - r_rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled, + * Enable Register bit[0] is set to 0 this bit keeps its level until the master or + * slave state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_OVER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_INTR_STAT_R_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive Full - r_rx_full + * + * Set when the receive buffer reaches or goes above the Receive FIFO Threshold + * Value(rx_tl). It is automatically cleared by hardware when buffer level goes + * below the threshold. If the module is disabled, Bit [0] of the Enable Register + * set to 0, the RX FIFO is flushed and held in reset; therefore the RX FIFO is not + * full. So this bit is cleared once the Enable Register Bit 0 is programmed with a + * 0, regardless of the activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_FULL field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_INTR_STAT_R_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Interrupt Transmit Over - r_tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the Data and Command + * Register. When the module is disabled, this bit keeps its level until the master + * or slave state machines goes into idle, then interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_OVER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_INTR_STAT_R_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Interrupt Transmit Empty - r_tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, this bit is set to 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_EMPTY field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_INTR_STAT_R_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Interrupt Read Request - r_rd_req + * + * This bit is set to 1 when i2c is acting as a slave and another I2C master is + * attempting to read data from I2C. The I2C holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the IC_DATA_CMD register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RD_REQ field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_INTR_STAT_R_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Interrupt TX Abort - r_tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit + * abort'.When this bit is set to 1, the ic_tx_abrt_source register indicates the + * reason why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_ABRT field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_INTR_STAT_R_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Interrupt RX Done - r_rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_DONE field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_INTR_STAT_R_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Interrupt R_activity - r_activity + * + * This bit captures I2C activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the I2C + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * I2C reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the I2C module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_ACTIVITY field value from a register. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_INTR_STAT_R_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Interrupt Stop Detect - r_stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_STOP_DET field value from a register. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_INTR_STAT_R_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Interrupt Start Detect - r_start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_START_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_START_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_START_DET field value from a register. */ +#define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_INTR_STAT_R_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Interrupt General Call - r_gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_GEN_CALL field value from a register. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_INTR_STAT_R_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_INTR_STAT. + */ +struct ALT_I2C_INTR_STAT_s +{ + const uint32_t r_rx_under : 1; /* Receiver Under */ + const uint32_t r_rx_over : 1; /* Receiver Over */ + const uint32_t r_rx_full : 1; /* Receive Full */ + const uint32_t r_tx_over : 1; /* Interrupt Transmit Over */ + const uint32_t r_tx_empty : 1; /* Interrupt Transmit Empty */ + const uint32_t r_rd_req : 1; /* Interrupt Read Request */ + const uint32_t r_tx_abrt : 1; /* Interrupt TX Abort */ + const uint32_t r_rx_done : 1; /* Interrupt RX Done */ + const uint32_t r_activity : 1; /* Interrupt R_activity */ + const uint32_t r_stop_det : 1; /* Interrupt Stop Detect */ + const uint32_t r_start_det : 1; /* Interrupt Start Detect */ + const uint32_t r_gen_call : 1; /* Interrupt General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_INTR_STAT. */ +typedef volatile struct ALT_I2C_INTR_STAT_s ALT_I2C_INTR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_INTR_STAT register from the beginning of the component. */ +#define ALT_I2C_INTR_STAT_OFST 0x2c +/* The address of the ALT_I2C_INTR_STAT register. */ +#define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST)) + +/* + * Register : Interrupt Mask Register - ic_intr_mask + * + * These bits mask their corresponding interrupt status bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------- + * [0] | RW | 0x1 | Mask RX Under + * [1] | RW | 0x1 | RX Buffer Over + * [2] | RW | 0x1 | RX Buffer Full + * [3] | RW | 0x1 | TX Buffer Over + * [4] | RW | 0x1 | TX Buffer Empty + * [5] | RW | 0x1 | Read Request + * [6] | RW | 0x1 | TX Abort + * [7] | RW | 0x1 | RX Done + * [8] | RW | 0x0 | Activity Bit + * [9] | RW | 0x0 | Stop Detect + * [10] | RW | 0x0 | Start Detect + * [11] | RW | 0x1 | General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Mask RX Under - m_rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, + * this bit keeps its level until the master or slave state machines go into idle, + * and then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_UNDER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_INTR_MSK_M_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : RX Buffer Over - m_rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled + * ic_enable[0]=0, this bit keeps its level until the master or slave state + * machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_OVER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_INTR_MSK_M_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : RX Buffer Full - m_rx_full + * + * Set when the receive buffer reaches or goes above the RX_TL threshold in the + * ic_rx_tl register. It is automatically cleared by hardware when buffer level + * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is + * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the + * activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_FULL field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_INTR_MSK_M_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : TX Buffer Over - m_tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the ic_data_cmd register. + * When the module is disabled, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_OVER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_INTR_MSK_M_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : TX Buffer Empty - m_tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, then this bit is set to + * 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_EMPTY field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_INTR_MSK_M_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Read Request - m_rd_req + * + * This bit is set to 1 when I2C is acting as a slave and another I2C master is + * attempting to read data from I2C. The I2C holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the ic_data_cmd register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RD_REQ field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_INTR_MSK_M_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : TX Abort - m_tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. + * When this bit is set to 1, the ic_tx_abrt_source register indicates the reason + * why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_ABRT field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_INTR_MSK_M_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : RX Done - m_rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_DONE field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_INTR_MSK_M_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Activity Bit - m_activity + * + * This bit captures i2c activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the i2c + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * System reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the I2C module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_ACTIVITY field value from a register. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_INTR_MSK_M_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Stop Detect - m_stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether i2c is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_STOP_DET field value from a register. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_INTR_MSK_M_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Start Detect - m_start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_START_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_START_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_START_DET field value from a register. */ +#define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_INTR_MSK_M_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : General Call - m_gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_GEN_CALL field value from a register. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_INTR_MSK_M_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_INTR_MSK. + */ +struct ALT_I2C_INTR_MSK_s +{ + uint32_t m_rx_under : 1; /* Mask RX Under */ + uint32_t m_rx_over : 1; /* RX Buffer Over */ + uint32_t m_rx_full : 1; /* RX Buffer Full */ + uint32_t m_tx_over : 1; /* TX Buffer Over */ + uint32_t m_tx_empty : 1; /* TX Buffer Empty */ + uint32_t m_rd_req : 1; /* Read Request */ + uint32_t m_tx_abrt : 1; /* TX Abort */ + uint32_t m_rx_done : 1; /* RX Done */ + uint32_t m_activity : 1; /* Activity Bit */ + uint32_t m_stop_det : 1; /* Stop Detect */ + uint32_t m_start_det : 1; /* Start Detect */ + uint32_t m_gen_call : 1; /* General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_INTR_MSK. */ +typedef volatile struct ALT_I2C_INTR_MSK_s ALT_I2C_INTR_MSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_INTR_MSK register from the beginning of the component. */ +#define ALT_I2C_INTR_MSK_OFST 0x30 +/* The address of the ALT_I2C_INTR_MSK register. */ +#define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST)) + +/* + * Register : Raw Interrupt Status Register - ic_raw_intr_stat + * + * Unlike the ic_intr_stat register, these bits are not masked so they always show + * the true status of the I2C. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | R | 0x0 | I2C Raw Interrupt RX Under + * [1] | R | 0x0 | Raw Interrupt RX Over + * [2] | R | 0x0 | Raw Interrupt RX Full + * [3] | R | 0x0 | Raw Interrupt TX Over + * [4] | R | 0x0 | Raw Interrupt TX Empty + * [5] | R | 0x0 | Raw Interrupt Read Request + * [6] | R | 0x0 | Raw Interrupt TX Abort + * [7] | R | 0x0 | Raw Interrupt RX Done + * [8] | R | 0x0 | Raw Interrupt Activity + * [9] | R | 0x0 | Raw Interrupt Stop Detect + * [10] | R | 0x0 | Raw Interrupt Start Detect + * [11] | R | 0x0 | Raw Interrupt General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : I2C Raw Interrupt RX Under - rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, + * this bit keeps its level until the master or slave state machines go into idle, + * then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_UNDER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Raw Interrupt RX Over - rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled + * ic_enable[0]=0), this bit keeps its level until the master or slave state + * machines go into then, this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_OVER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Raw Interrupt RX Full - rx_full + * + * Set when the receive buffer reaches or goes above the RX_TL threshold in the + * ic_rx_tl register. It is automatically cleared by hardware when buffer level + * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is + * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the + * activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_FULL field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Raw Interrupt TX Over - tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the ic_data_cmd register. + * When the module is disabled, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_OVER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Raw Interrupt TX Empty - tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, then this bit is set to + * 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_EMPTY field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Raw Interrupt Read Request - rd_req + * + * This bit is set to 1 when I2C is acting as a slave and another I2C master is + * attempting to read data from I2C. The i2c holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the ic_data_cmd register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RD_REQ field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_RAW_INTR_STAT_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Raw Interrupt TX Abort - tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. + * When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason + * why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_ABRT field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Raw Interrupt RX Done - rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1 if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_DONE field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Raw Interrupt Activity - activity + * + * This bit captures i2c activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the I2C + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * System reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the i2c module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_ACTIVITY field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Raw Interrupt Stop Detect - stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_STOP_DET field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_RAW_INTR_STAT_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Raw Interrupt Start Detect - start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_START_DET field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_RAW_INTR_STAT_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Raw Interrupt General Call - gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_GEN_CALL field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RAW_INTR_STAT. + */ +struct ALT_I2C_RAW_INTR_STAT_s +{ + const uint32_t rx_under : 1; /* I2C Raw Interrupt RX Under */ + const uint32_t rx_over : 1; /* Raw Interrupt RX Over */ + const uint32_t rx_full : 1; /* Raw Interrupt RX Full */ + const uint32_t tx_over : 1; /* Raw Interrupt TX Over */ + const uint32_t tx_empty : 1; /* Raw Interrupt TX Empty */ + const uint32_t rd_req : 1; /* Raw Interrupt Read Request */ + const uint32_t tx_abrt : 1; /* Raw Interrupt TX Abort */ + const uint32_t rx_done : 1; /* Raw Interrupt RX Done */ + const uint32_t activity : 1; /* Raw Interrupt Activity */ + const uint32_t stop_det : 1; /* Raw Interrupt Stop Detect */ + const uint32_t start_det : 1; /* Raw Interrupt Start Detect */ + const uint32_t gen_call : 1; /* Raw Interrupt General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RAW_INTR_STAT. */ +typedef volatile struct ALT_I2C_RAW_INTR_STAT_s ALT_I2C_RAW_INTR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RAW_INTR_STAT register from the beginning of the component. */ +#define ALT_I2C_RAW_INTR_STAT_OFST 0x34 +/* The address of the ALT_I2C_RAW_INTR_STAT register. */ +#define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST)) + +/* + * Register : Receive FIFO Threshold Register - ic_rx_tl + * + * I2C Receive FIFO Threshold Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [7:0] | RW | 0x0 | Receive FIFO Threshold Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Threshold Level - rx_tl + * + * Controls the level of entries (or above) that triggers the RX_FULL interrupt + * (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the + * additional restriction that hardware does not allow this value to be set to a + * value larger than the depth of the buffer. If an attempt is made to do that, the + * actual value set will be the maximum depth of the buffer. A value of 0 sets the + * threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_MSB 7 +/* The width in bits of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_WIDTH 8 +/* The mask used to set the ALT_I2C_RX_TL_RX_TL register field value. */ +#define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_RX_TL_RX_TL register field value. */ +#define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_RESET 0x0 +/* Extracts the ALT_I2C_RX_TL_RX_TL field value from a register. */ +#define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_RX_TL_RX_TL register field value suitable for setting the register. */ +#define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RX_TL. + */ +struct ALT_I2C_RX_TL_s +{ + uint32_t rx_tl : 8; /* Receive FIFO Threshold Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RX_TL. */ +typedef volatile struct ALT_I2C_RX_TL_s ALT_I2C_RX_TL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RX_TL register from the beginning of the component. */ +#define ALT_I2C_RX_TL_OFST 0x38 +/* The address of the ALT_I2C_RX_TL register. */ +#define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST)) + +/* + * Register : Transmit FIFO Threshold Level Register - ic_tx_tl + * + * Sets FIFO depth for Interrupt. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [7:0] | RW | 0x0 | Transmit FIFO Threshold Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Threshold Level - tx_tl + * + * Controls the level of entries (or below) that trigger the TX_EMPTY interrupt + * (bit 4 in ic_raw_intr_stat register). The valid range is 0-255, with the + * additional restriction that it may not be set to value larger than the depth of + * the buffer. If an attempt is made to do that, the actual value set will be the + * maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and + * a value of 255 sets the threshold for 255 entries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_MSB 7 +/* The width in bits of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_WIDTH 8 +/* The mask used to set the ALT_I2C_TX_TL_TX_TL register field value. */ +#define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_TX_TL_TX_TL register field value. */ +#define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_RESET 0x0 +/* Extracts the ALT_I2C_TX_TL_TX_TL field value from a register. */ +#define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_TX_TL_TX_TL register field value suitable for setting the register. */ +#define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TX_TL. + */ +struct ALT_I2C_TX_TL_s +{ + uint32_t tx_tl : 8; /* Transmit FIFO Threshold Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TX_TL. */ +typedef volatile struct ALT_I2C_TX_TL_s ALT_I2C_TX_TL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TX_TL register from the beginning of the component. */ +#define ALT_I2C_TX_TL_OFST 0x3c +/* The address of the ALT_I2C_TX_TL register. */ +#define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST)) + +/* + * Register : Combined and Individual Interrupt Register - ic_clr_intr + * + * Controls Interrupts + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Combined and Individual Interrupt Bits + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Combined and Individual Interrupt Bits - clr_intr + * + * Read this register to clear the combined interrupt, all individual interrupts, + * and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable + * interrupts but software clearable interrupts. Refer to Bit 9 of the + * ic_tx_abrt_source register for an exception to clearing ic_tx_abrt_source. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0 +/* The width in bits of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_INTR_CLR_INTR register field value. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_INTR_CLR_INTR register field value. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0 +/* Extracts the ALT_I2C_CLR_INTR_CLR_INTR field value from a register. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_INTR_CLR_INTR register field value suitable for setting the register. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_INTR. + */ +struct ALT_I2C_CLR_INTR_s +{ + const uint32_t clr_intr : 1; /* Combined and Individual Interrupt Bits */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_INTR. */ +typedef volatile struct ALT_I2C_CLR_INTR_s ALT_I2C_CLR_INTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_INTR register from the beginning of the component. */ +#define ALT_I2C_CLR_INTR_OFST 0x40 +/* The address of the ALT_I2C_CLR_INTR register. */ +#define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST)) + +/* + * Register : Rx Under Interrupt Register - ic_clr_rx_under + * + * Rx Under Interrupt Bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | R | 0x0 | Clear Rx Under Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Rx Under Interrupt Bit - clr_rx_under + * + * Read this register to clear the RX_UNDER interrupt bit 0 of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER field value from a register. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_UNDER. + */ +struct ALT_I2C_CLR_RX_UNDER_s +{ + const uint32_t clr_rx_under : 1; /* Clear Rx Under Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_UNDER. */ +typedef volatile struct ALT_I2C_CLR_RX_UNDER_s ALT_I2C_CLR_RX_UNDER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_UNDER register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_UNDER_OFST 0x44 +/* The address of the ALT_I2C_CLR_RX_UNDER register. */ +#define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST)) + +/* + * Register : RX Over Interrupt Register - ic_clr_rx_over + * + * Clears Rx over Interrupt Bit + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | RX Over Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RX Over Interrupt Bit - clr_rx_over + * + * Read this register to clear the RX_OVER interrupt bit 1 of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER field value from a register. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_OVER. + */ +struct ALT_I2C_CLR_RX_OVER_s +{ + const uint32_t clr_rx_over : 1; /* RX Over Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_OVER. */ +typedef volatile struct ALT_I2C_CLR_RX_OVER_s ALT_I2C_CLR_RX_OVER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_OVER register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_OVER_OFST 0x48 +/* The address of the ALT_I2C_CLR_RX_OVER register. */ +#define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST)) + +/* + * Register : TX Over Interrupt Register - ic_clr_tx_over + * + * Clears Over Interrupts + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | TX Over Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : TX Over Interrupt Bit - clr_tx_over + * + * Read this register to clear the TX_OVER interrupt (bit 3) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER field value from a register. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_TX_OVER. + */ +struct ALT_I2C_CLR_TX_OVER_s +{ + const uint32_t clr_tx_over : 1; /* TX Over Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_TX_OVER. */ +typedef volatile struct ALT_I2C_CLR_TX_OVER_s ALT_I2C_CLR_TX_OVER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_TX_OVER register from the beginning of the component. */ +#define ALT_I2C_CLR_TX_OVER_OFST 0x4c +/* The address of the ALT_I2C_CLR_TX_OVER register. */ +#define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST)) + +/* + * Register : Interrupt Read Request Register - ic_clr_rd_req + * + * Clear RD_REQ Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | R | 0x0 | Interrupt Register Read Request Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Register Read Request Bit - clr_rd_req + * + * Read this register to clear the RD_REQ interrupt (bit 5) of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ field value from a register. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RD_REQ. + */ +struct ALT_I2C_CLR_RD_REQ_s +{ + const uint32_t clr_rd_req : 1; /* Interrupt Register Read Request Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RD_REQ. */ +typedef volatile struct ALT_I2C_CLR_RD_REQ_s ALT_I2C_CLR_RD_REQ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RD_REQ register from the beginning of the component. */ +#define ALT_I2C_CLR_RD_REQ_OFST 0x50 +/* The address of the ALT_I2C_CLR_RD_REQ register. */ +#define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST)) + +/* + * Register : Tx Abort Interrupt Register - ic_clr_tx_abrt + * + * Clear TX_ABRT Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | Tx Abort Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Tx Abort Interrupt Bit - clr_tx_abort + * + * Read this register to clear the TX_ABRT interrupt (bit 6) of the + * ic_raw_intr_stat register, and the ic_tx_abrt_source register. This also + * releases the TX FIFO from the flushed/reset state, allowing more writes to the + * TX FIFO. Refer to Bit 9 of the ic_tx_abrt_source register for an exception to + * clearing ic_tx_abrt_source. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0 +/* The width in bits of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0 +/* Extracts the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT field value from a register. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value suitable for setting the register. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_TX_ABRT. + */ +struct ALT_I2C_CLR_TX_ABRT_s +{ + const uint32_t clr_tx_abort : 1; /* Tx Abort Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_TX_ABRT. */ +typedef volatile struct ALT_I2C_CLR_TX_ABRT_s ALT_I2C_CLR_TX_ABRT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_TX_ABRT register from the beginning of the component. */ +#define ALT_I2C_CLR_TX_ABRT_OFST 0x54 +/* The address of the ALT_I2C_CLR_TX_ABRT register. */ +#define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST)) + +/* + * Register : Rx Done Interrupt Register - ic_clr_rx_done + * + * Clear RX_DONE Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | RX_DONE Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RX_DONE Interrupt Bit - clr_rx_done + * + * Read this register to clear the RX_DONE interrupt (bit 7) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE field value from a register. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_DONE. + */ +struct ALT_I2C_CLR_RX_DONE_s +{ + const uint32_t clr_rx_done : 1; /* RX_DONE Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_DONE. */ +typedef volatile struct ALT_I2C_CLR_RX_DONE_s ALT_I2C_CLR_RX_DONE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_DONE register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_DONE_OFST 0x58 +/* The address of the ALT_I2C_CLR_RX_DONE register. */ +#define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST)) + +/* + * Register : Activity Interrupt Register - ic_clr_activity + * + * Clears ACTIVITY Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | Activity Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Activity Interrupt Bit - clr_activity + * + * Reading this register clears the ACTIVITY interrupt if the I2C is not active + * anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt + * bit continues to be set. It is automatically cleared by hardware if the module + * is disabled and if there is no further activity on the bus. The value read from + * this register to get status of the ACTIVITY interrupt (bit 8) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0 +/* The width in bits of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY field value from a register. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_ACTIVITY. + */ +struct ALT_I2C_CLR_ACTIVITY_s +{ + const uint32_t clr_activity : 1; /* Activity Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_ACTIVITY. */ +typedef volatile struct ALT_I2C_CLR_ACTIVITY_s ALT_I2C_CLR_ACTIVITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_ACTIVITY register from the beginning of the component. */ +#define ALT_I2C_CLR_ACTIVITY_OFST 0x5c +/* The address of the ALT_I2C_CLR_ACTIVITY register. */ +#define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST)) + +/* + * Register : Stop Detect Interrupt Register - ic_clr_stop_det + * + * Clear Interrupts. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [0] | R | 0x0 | Stop Detect Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Stop Detect Interrupt Bit - clr_stop_det + * + * Read this register to clear the clr_stop_det interrupt (bit 9) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0 +/* The width in bits of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET field value from a register. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_STOP_DET. + */ +struct ALT_I2C_CLR_STOP_DET_s +{ + const uint32_t clr_stop_det : 1; /* Stop Detect Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_STOP_DET. */ +typedef volatile struct ALT_I2C_CLR_STOP_DET_s ALT_I2C_CLR_STOP_DET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_STOP_DET register from the beginning of the component. */ +#define ALT_I2C_CLR_STOP_DET_OFST 0x60 +/* The address of the ALT_I2C_CLR_STOP_DET register. */ +#define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST)) + +/* + * Register : Start Detect Interrupt Register - ic_clr_start_det + * + * Clears START_DET Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | R | 0x0 | Start Detect Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Detect Interrupt Bit - clr_start_det + * + * Read this register to clear the start_det interrupt (bit 10) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0 +/* The width in bits of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_CLR_START_DET_CLR_START_DET field value from a register. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_START_DET_CLR_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_START_DET. + */ +struct ALT_I2C_CLR_START_DET_s +{ + const uint32_t clr_start_det : 1; /* Start Detect Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_START_DET. */ +typedef volatile struct ALT_I2C_CLR_START_DET_s ALT_I2C_CLR_START_DET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_START_DET register from the beginning of the component. */ +#define ALT_I2C_CLR_START_DET_OFST 0x64 +/* The address of the ALT_I2C_CLR_START_DET register. */ +#define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST)) + +/* + * Register : GEN CALL Interrupt Register - ic_clr_gen_call + * + * Clear GEN_CALL Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | GEN CALL Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GEN CALL Interrupt Bit - clr_gen_call + * + * Read this register to clear the GEN_CALL interrupt (bit 11) of ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0 +/* The width in bits of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL field value from a register. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_GEN_CALL. + */ +struct ALT_I2C_CLR_GEN_CALL_s +{ + const uint32_t clr_gen_call : 1; /* GEN CALL Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_GEN_CALL. */ +typedef volatile struct ALT_I2C_CLR_GEN_CALL_s ALT_I2C_CLR_GEN_CALL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_GEN_CALL register from the beginning of the component. */ +#define ALT_I2C_CLR_GEN_CALL_OFST 0x68 +/* The address of the ALT_I2C_CLR_GEN_CALL register. */ +#define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST)) + +/* + * Register : Enable Register - ic_enable + * + * Enable and disable i2c operation + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Enable Bit + * [1] | RW | 0x0 | TX abort Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable Bit - enable + * + * Controls whether the I2C is enabled. Software can disable I2C while it is + * active. However, it is important that care be taken to ensure that I2C is + * disabled properly. When the I2C is disabled, the following occurs: + * + * The TX FIFO and RX FIFO get flushed. Status bits in the IC_INTR_STAT register + * are still active until I2C goes into IDLE state. If the module is transmitting, + * it stops as well as deletes the contents of the transmit buffer after the + * current transfer is complete. If the module is receiving, the I2C stops the + * current transfer at the end of the current byte and does not acknowledge the + * transfer. The l4_sp_clk synchronizes pclk and ic_clk. The register + * ic_enable_status is added to allow software to determine when the hardware has + * completely shutdown in response to the IC_ENABLE register being set from 1 to 0. + * Only one register is required to be monitored. Procedure for Disabling I2C + * + * 1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling + * period for the highest I2C transfer speed used in the system and supported by + * I2C. For example, if the highest I2C transfer mode is 400 kb/s, then this + * ti2c_poll is 25us. + * + * 2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any + * repeated polling operation exceeds this maximum value, an error is reported. 3. + * Execute a blocking thread/process/function that prevents any further I2C master + * transactions to be started by software, but allows any pending transfers to be + * completed. + * + * 4. The variable POLL_COUNT is initialized to zero. 5. Set IC_ENABLE to 0. + * + * 6. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment + * POLL_COUNT by one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant + * error code. + * + * 7. If IC_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the + * previous step. Otherwise, exit with a relevant success code. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------|:------|:----------------------------------------------- + * ALT_I2C_EN_EN_E_DIS | 0x0 | Disables i2c. TX and RX FIFOs are held in an + * : | | erased state + * ALT_I2C_EN_EN_E_EN | 0x1 | Enables i2c. Software can disable i2c while it + * : | | is active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_EN_EN + * + * Disables i2c. TX and RX FIFOs are held in an erased state + */ +#define ALT_I2C_EN_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_EN_EN + * + * Enables i2c. Software can disable i2c while it is active + */ +#define ALT_I2C_EN_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_MSB 0 +/* The width in bits of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_EN register field value. */ +#define ALT_I2C_EN_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_EN_EN register field value. */ +#define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_RESET 0x0 +/* Extracts the ALT_I2C_EN_EN field value from a register. */ +#define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_EN_EN register field value suitable for setting the register. */ +#define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TX abort Bit - txabort + * + * Write 1 does a TX abort. Self cleared on abort completion + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_MSB 1 +/* The width in bits of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_TXABT register field value. */ +#define ALT_I2C_EN_TXABT_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_EN_TXABT register field value. */ +#define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_RESET 0x0 +/* Extracts the ALT_I2C_EN_TXABT field value from a register. */ +#define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_EN_TXABT register field value suitable for setting the register. */ +#define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_EN. + */ +struct ALT_I2C_EN_s +{ + uint32_t enable : 1; /* Enable Bit */ + uint32_t txabort : 1; /* TX abort Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_EN. */ +typedef volatile struct ALT_I2C_EN_s ALT_I2C_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_EN register from the beginning of the component. */ +#define ALT_I2C_EN_OFST 0x6c +/* The address of the ALT_I2C_EN register. */ +#define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST)) + +/* + * Register : Status Register - ic_status + * + * This is a read-only register used to indicate the current transfer status and + * FIFO status. The status register may be read at any time. None of the bits in + * this register request an interrupt.When the I2C is disabled by writing 0 in bit + * 0 of the ic_enable register: + * + * * Bits 1 and 2 are set to 1 + * + * * Bits 3 and 4 are set to 0 + * + * When the master or slave state machines goes to idle + * + * * Bits 5 and 6 are set to 0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | R | 0x0 | Activity Status Bit + * [1] | R | 0x1 | TX FIFO Not Full Bit + * [2] | R | 0x1 | TX FIFO Empty Bit + * [3] | R | 0x0 | RX FIFO Empty Bit + * [4] | R | 0x0 | RX FIFO Full Bit + * [5] | R | 0x0 | Master FSM Activity Status Bit + * [6] | R | 0x0 | Slave FSM Activity Status Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Activity Status Bit - activity + * + * I2C Activity. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_MSB 0 +/* The width in bits of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_ACTIVITY register field value. */ +#define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_STAT_ACTIVITY register field value. */ +#define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_STAT_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TX FIFO Not Full Bit - tfnf + * + * Transmit Fifo Full + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------------------- + * ALT_I2C_STAT_TFNF_E_FULL | 0x0 | Transmit FIFO is full + * ALT_I2C_STAT_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_TFNF + * + * Transmit FIFO is full + */ +#define ALT_I2C_STAT_TFNF_E_FULL 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_TFNF + * + * Transmit FIFO is not full + */ +#define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_MSB 1 +/* The width in bits of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_TFNF register field value. */ +#define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_STAT_TFNF register field value. */ +#define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_RESET 0x1 +/* Extracts the ALT_I2C_STAT_TFNF field value from a register. */ +#define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_STAT_TFNF register field value suitable for setting the register. */ +#define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : TX FIFO Empty Bit - tfe + * + * Transmit FIFO Empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_I2C_STAT_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty + * ALT_I2C_STAT_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_TFE + * + * Transmit FIFO is not empty + */ +#define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_TFE + * + * Transmit FIFO is empty + */ +#define ALT_I2C_STAT_TFE_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_MSB 2 +/* The width in bits of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_TFE register field value. */ +#define ALT_I2C_STAT_TFE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_STAT_TFE register field value. */ +#define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_RESET 0x1 +/* Extracts the ALT_I2C_STAT_TFE field value from a register. */ +#define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_STAT_TFE register field value suitable for setting the register. */ +#define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : RX FIFO Empty Bit - rfne + * + * Receive FIFO Not Empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------------- + * ALT_I2C_STAT_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty + * ALT_I2C_STAT_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_RFNE + * + * Receive FIFO is empty + */ +#define ALT_I2C_STAT_RFNE_E_EMPTY 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_RFNE + * + * Receive FIFO is not empty + */ +#define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_MSB 3 +/* The width in bits of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_RFNE register field value. */ +#define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_STAT_RFNE register field value. */ +#define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_RESET 0x0 +/* Extracts the ALT_I2C_STAT_RFNE field value from a register. */ +#define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_STAT_RFNE register field value suitable for setting the register. */ +#define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : RX FIFO Full Bit - rff + * + * Receive FIFO Completely Full. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:------------------------- + * ALT_I2C_STAT_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full + * ALT_I2C_STAT_RFF_E_FULL | 0x1 | Receive FIFO is full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_RFF + * + * Receive FIFO is not full + */ +#define ALT_I2C_STAT_RFF_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_RFF + * + * Receive FIFO is full + */ +#define ALT_I2C_STAT_RFF_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_MSB 4 +/* The width in bits of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_RFF register field value. */ +#define ALT_I2C_STAT_RFF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_STAT_RFF register field value. */ +#define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_RESET 0x0 +/* Extracts the ALT_I2C_STAT_RFF field value from a register. */ +#define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_STAT_RFF register field value suitable for setting the register. */ +#define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Master FSM Activity Status Bit - mst_activity + * + * When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is + * set. Note:IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and + * MST_ACTIVITY bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------ + * ALT_I2C_STAT_MST_ACTIVITY_E_IDLE | 0x0 | Master FSM is in IDLE state. Master part of i2c + * : | | is not Active + * ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE | 0x1 | Master FSM is not in IDLE state. Master part of + * : | | i2c is Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY + * + * Master FSM is in IDLE state. Master part of i2c is not Active + */ +#define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY + * + * Master FSM is not in IDLE state. Master part of i2c is Active + */ +#define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_MSB 5 +/* The width in bits of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_MST_ACTIVITY register field value. */ +#define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_STAT_MST_ACTIVITY register field value. */ +#define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_MST_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_STAT_MST_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Slave FSM Activity Status Bit - slv_activity + * + * Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in + * the IDLE state, this bit is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE | 0x0 | Slave FSM is in IDLE state so the Slave part of + * : | | i2c is not Active + * ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE | 0x1 | Slave FSM is not in IDLE state so the Slave part + * : | | of i2c is Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY + * + * Slave FSM is in IDLE state so the Slave part of i2c is not Active + */ +#define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY + * + * Slave FSM is not in IDLE state so the Slave part of i2c is Active + */ +#define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6 +/* The width in bits of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_SLV_ACTIVITY register field value. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_STAT_SLV_ACTIVITY register field value. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_SLV_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_STAT_SLV_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_STAT. + */ +struct ALT_I2C_STAT_s +{ + const uint32_t activity : 1; /* Activity Status Bit */ + const uint32_t tfnf : 1; /* TX FIFO Not Full Bit */ + const uint32_t tfe : 1; /* TX FIFO Empty Bit */ + const uint32_t rfne : 1; /* RX FIFO Empty Bit */ + const uint32_t rff : 1; /* RX FIFO Full Bit */ + const uint32_t mst_activity : 1; /* Master FSM Activity Status Bit */ + const uint32_t slv_activity : 1; /* Slave FSM Activity Status Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_STAT. */ +typedef volatile struct ALT_I2C_STAT_s ALT_I2C_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_STAT register from the beginning of the component. */ +#define ALT_I2C_STAT_OFST 0x70 +/* The address of the ALT_I2C_STAT register. */ +#define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST)) + +/* + * Register : Transmit FIFO Level Register - ic_txflr + * + * This register contains the number of valid data entries in the transmit FIFO + * buffer. It is cleared whenever: + * + * * The I2C is disabled + * + * * There is a transmit abort that is, TX_ABRT bit is set in the ic_raw_intr_stat + * register. The slave bulk transmit mode is aborted The register increments + * whenever data is placed into the transmit FIFO and decrements when data is + * taken from the transmit FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [6:0] | R | 0x0 | Transmit FIFO Level Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Level Bit - txflr + * + * Transmit FIFO Level.Contains the number of valid data entries in the transmit + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_MSB 6 +/* The width in bits of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_WIDTH 7 +/* The mask used to set the ALT_I2C_TXFLR_TXFLR register field value. */ +#define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_I2C_TXFLR_TXFLR register field value. */ +#define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_RESET 0x0 +/* Extracts the ALT_I2C_TXFLR_TXFLR field value from a register. */ +#define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_I2C_TXFLR_TXFLR register field value suitable for setting the register. */ +#define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TXFLR. + */ +struct ALT_I2C_TXFLR_s +{ + const uint32_t txflr : 7; /* Transmit FIFO Level Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TXFLR. */ +typedef volatile struct ALT_I2C_TXFLR_s ALT_I2C_TXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TXFLR register from the beginning of the component. */ +#define ALT_I2C_TXFLR_OFST 0x74 +/* The address of the ALT_I2C_TXFLR register. */ +#define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST)) + +/* + * Register : Receive FIFO Level Register - ic_rxflr + * + * This register contains the number of valid data entries in the receive FIFO + * buffer. It is cleared whenever: + * + * * The I2C is disabled + * + * * Whenever there is a transmit abort caused by any of the events tracked in + * ic_tx_abrt_source The register increments whenever data is placed into the + * receive FIFO and decrements when data is taken from the receive FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [6:0] | R | 0x0 | Receive FIFO Level Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Level Bit - rxflr + * + * Receive FIFO Level. Contains the number of valid data entries in the receive + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_MSB 6 +/* The width in bits of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_WIDTH 7 +/* The mask used to set the ALT_I2C_RXFLR_RXFLR register field value. */ +#define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_I2C_RXFLR_RXFLR register field value. */ +#define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_RESET 0x0 +/* Extracts the ALT_I2C_RXFLR_RXFLR field value from a register. */ +#define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_I2C_RXFLR_RXFLR register field value suitable for setting the register. */ +#define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RXFLR. + */ +struct ALT_I2C_RXFLR_s +{ + const uint32_t rxflr : 7; /* Receive FIFO Level Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RXFLR. */ +typedef volatile struct ALT_I2C_RXFLR_s ALT_I2C_RXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RXFLR register from the beginning of the component. */ +#define ALT_I2C_RXFLR_OFST 0x78 +/* The address of the ALT_I2C_RXFLR register. */ +#define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST)) + +/* + * Register : SDA Hold Register - ic_sda_hold + * + * This register controls the amount of time delay (in terms of number of l4_sp_clk + * clock periods) introduced in the falling edge of SCL, relative to SDA changing, + * when I2C services a read request in a slave-transmitter operation. The relevant + * I2C requirement is thd:DAT as detailed in the I2C Bus Specification. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------- + * [15:0] | RW | 0x1 | SDA Hold Bit + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDA Hold Bit - ic_sda_hold + * + * Program to a minimum 0f 300ns. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_MSB 15 +/* The width in bits of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_WIDTH 16 +/* The mask used to set the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_RESET 0x1 +/* Extracts the ALT_I2C_SDA_HOLD_IC_SDA_HOLD field value from a register. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value suitable for setting the register. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SDA_HOLD. + */ +struct ALT_I2C_SDA_HOLD_s +{ + uint32_t ic_sda_hold : 16; /* SDA Hold Bit */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SDA_HOLD. */ +typedef volatile struct ALT_I2C_SDA_HOLD_s ALT_I2C_SDA_HOLD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SDA_HOLD register from the beginning of the component. */ +#define ALT_I2C_SDA_HOLD_OFST 0x7c +/* The address of the ALT_I2C_SDA_HOLD register. */ +#define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST)) + +/* + * Register : Transmit Abort Source Register - ic_tx_abrt_source + * + * This register has 16 bits that indicate the source of the TX_ABRT bit. Except + * for Bit 9, this register is cleared whenever the ic_clr_tx_abrt register or the + * ic_clr_intr register is read. To clear Bit 9, the source of the + * abrt_sbyte_norstrt must be fixed first; RESTART must be enabled (ic_con[5]=1), + * the special bit must be cleared (ic_tar[11]), or the gc_or_start bit must be + * cleared (ic_tar[10]). Once the source of the abrt_sbyte_norstrt is fixed, then + * this bit can be cleared in the same manner as other bits in this register. If + * the source of the abrt_sbyte_norstrt is not fixed before attempting to clear + * this bit, Bit 9 clears for one cycle and is then re-asserted. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [0] | RW | 0x0 | Master Abort 7 Bit Address + * [1] | RW | 0x0 | Master Abort 10 Bit Address Byte 1 + * [2] | RW | 0x0 | Master Abort 10 Bit Address Byte 2 + * [3] | RW | 0x0 | Master Abort TX Noack Bit + * [4] | RW | 0x0 | Master Abort GC Noack Bit + * [5] | RW | 0x0 | Master Abort GC Read Bit + * [6] | RW | 0x0 | Master HS MC Ack + * [7] | RW | 0x0 | Master Abort START Byte + * [8] | RW | 0x0 | Master HS Restart Disabled + * [9] | RW | 0x0 | Master Abort START No Restart + * [10] | RW | 0x0 | Master Abort 10 Bit No Restart + * [11] | RW | 0x0 | Master Oper Master Dis + * [12] | RW | 0x0 | Master Abort Arbitration Lost + * [13] | RW | 0x0 | Slave Abort Flush TXFIFO + * [14] | RW | 0x0 | Slave Abort Arbitration Lost + * [15] | RW | 0x0 | Slave Abort Read TX + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Abort 7 Bit Address - abrt_7b_addr_noack + * + * Master is in 7-bit addressing mode and the address sent was not acknowledged by + * any slave. Role of i2c: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Master Abort 10 Bit Address Byte 1 - abrt_10addr1_noack + * + * Master is in 10-bit address mode and the first 10-bit address byte was not + * acknowledged by any slave. Role of i2c: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Master Abort 10 Bit Address Byte 2 - abrt_10addr2_noack + * + * Master is in 10-bit address mode and the second address byte of the 10-bit + * address was not acknowledged by any slave. Role of i2c: Master-Transmitter or + * Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Master Abort TX Noack Bit - abrt_txdata_noack + * + * This is a master-mode only bit. Master has received an acknowledgement for the + * address, but when it sent data byte(s) following the address, it did not receive + * an acknowledge from the remote slave(s). Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Master Abort GC Noack Bit - abrt_gcall_noack + * + * i2c in master mode sent a General Call and no slave on the bus acknowledged the + * General Call. Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Master Abort GC Read Bit - abrt_gcall_read + * + * i2c in master mode sent a General Call but the user programmed the byte + * following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to + * 1). Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Master HS MC Ack - abrt_hs_ackdet + * + * Master is in High Speed mode and the High Speed Master code was acknowledged + * (wrong behavior). Role of i2c: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Master Abort START Byte - abrt_sbyte_ackdet + * + * Master has sent a START Byte and the START Byte was acknowledged (wrong + * behavior). Role of i2c: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Master HS Restart Disabled - abrt_hs_norstrt + * + * The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is + * trying to use the master to transfer data in High Speed mode. Role of i2c: + * Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Master Abort START No Restart - abrt_sbyte_norstrt + * + * To clear Bit 9, the source of then abrt_sbyte_norstrt must be fixed first; + * restart must be enabled (ic_con[5]=1), the SPECIAL bit must be cleared + * (ic_tar[11]), or the GC_OR_START bit must be cleared (ic_tar[10]). Once the + * source of the abrt_sbyte_norstrt is fixed, then this bit can be cleared in the + * same manner as other bits in this register. If the source of the + * abrt_sbyte_norstrt is not fixed before attempting to clear this bit, bit 9 + * clears for one cycle and then gets reasserted. 1: The restart is disabled + * (IC_RESTART_EN bit (ic_con[5]) =0) and the user is trying to send a START Byte. + * Role of I2C: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Master Abort 10 Bit No Restart - abrt_10b_rd_norstrt + * + * The restart is disabled (ic_restart_en bit (ic_con[5]) =0) and the master sends + * a read command in 10-bit addressing mode. Role of I2C: Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Master Oper Master Dis - abrt_master_dis + * + * User tries to initiate a Master operation with the Master mode disabled. Role of + * I2C: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Master Abort Arbitration Lost - arb_lost + * + * Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the + * slave transmitter has lost arbitration. Note: I2C can be both master and slave + * at the same time. Role of i2c: Master-Transmitter or Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ARB_LOST field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Slave Abort Flush TXFIFO - abrt_slvflush_txfifo + * + * Slave has received a read command and some data exists in the TX FIFO so the + * slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Role of I2C: + * Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Slave Abort Arbitration Lost - abrt_slv_arblost + * + * Slave lost the bus while transmitting data to a remote master. + * IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never + * 'owns' the bus, something could go wrong on the bus. This is a fail safe check. + * For instance, during a data transmission at the low-to-high transition of SCL, + * if what is on the data bus is not what is supposed to be transmitted, then i2c + * no longer own the bus. Role of I2C: Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Slave Abort Read TX - abrt_slvrd_intx + * + * When the processor side responds to a slave mode request for data to be + * transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD + * register. Role of I2C: Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TX_ABRT_SRC. + */ +struct ALT_I2C_TX_ABRT_SRC_s +{ + uint32_t abrt_7b_addr_noack : 1; /* Master Abort 7 Bit Address */ + uint32_t abrt_10addr1_noack : 1; /* Master Abort 10 Bit Address Byte 1 */ + uint32_t abrt_10addr2_noack : 1; /* Master Abort 10 Bit Address Byte 2 */ + uint32_t abrt_txdata_noack : 1; /* Master Abort TX Noack Bit */ + uint32_t abrt_gcall_noack : 1; /* Master Abort GC Noack Bit */ + uint32_t abrt_gcall_read : 1; /* Master Abort GC Read Bit */ + uint32_t abrt_hs_ackdet : 1; /* Master HS MC Ack */ + uint32_t abrt_sbyte_ackdet : 1; /* Master Abort START Byte */ + uint32_t abrt_hs_norstrt : 1; /* Master HS Restart Disabled */ + uint32_t abrt_sbyte_norstrt : 1; /* Master Abort START No Restart */ + uint32_t abrt_10b_rd_norstrt : 1; /* Master Abort 10 Bit No Restart */ + uint32_t abrt_master_dis : 1; /* Master Oper Master Dis */ + uint32_t arb_lost : 1; /* Master Abort Arbitration Lost */ + uint32_t abrt_slvflush_txfifo : 1; /* Slave Abort Flush TXFIFO */ + uint32_t abrt_slv_arblost : 1; /* Slave Abort Arbitration Lost */ + uint32_t abrt_slvrd_intx : 1; /* Slave Abort Read TX */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TX_ABRT_SRC. */ +typedef volatile struct ALT_I2C_TX_ABRT_SRC_s ALT_I2C_TX_ABRT_SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TX_ABRT_SRC register from the beginning of the component. */ +#define ALT_I2C_TX_ABRT_SRC_OFST 0x80 +/* The address of the ALT_I2C_TX_ABRT_SRC register. */ +#define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST)) + +/* + * Register : Generate Slave Data NACK - ic_slv_data_nack_only + * + * The register is used to generate a NACK for the data part of a transfer when i2c + * is acting as a slave-receiver. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [0] | RW | 0x0 | Generate Nack Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Generate Nack Bit - nack + * + * This Bit control Nack generation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:-------------------------------------- + * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE | 0x1 | Generate NACK after data byte receive + * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM | 0x0 | Generate NACK/ACK normally + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK + * + * Generate NACK after data byte receive + */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1 +/* + * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK + * + * Generate NACK/ACK normally + */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0 +/* The width in bits of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1 +/* The mask used to set the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0 +/* Extracts the ALT_I2C_SLV_DATA_NACK_ONLY_NACK field value from a register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value suitable for setting the register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. + */ +struct ALT_I2C_SLV_DATA_NACK_ONLY_s +{ + uint32_t nack : 1; /* Generate Nack Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. */ +typedef volatile struct ALT_I2C_SLV_DATA_NACK_ONLY_s ALT_I2C_SLV_DATA_NACK_ONLY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SLV_DATA_NACK_ONLY register from the beginning of the component. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84 +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST)) + +/* + * Register : DMA Control - ic_dma_cr + * + * The register is used to enable the DMA Controller interface operation. There is + * a separate bit for transmit and receive. This can be programmed regardless of + * the state of IC_ENABLE. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | Receive DMA Enable Bit + * [1] | RW | 0x0 | Transmit DMA Enable Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive DMA Enable Bit - rdmae + * + * This bit enables/disables the receive FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------- + * ALT_I2C_DMA_CR_RDMAE_E_DIS | 0x0 | Receive DMA disable + * ALT_I2C_DMA_CR_RDMAE_E_EN | 0x1 | Receive DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE + * + * Receive DMA disable + */ +#define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE + * + * Receive DMA enabled + */ +#define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_MSB 0 +/* The width in bits of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_WIDTH 1 +/* The mask used to set the ALT_I2C_DMA_CR_RDMAE register field value. */ +#define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_DMA_CR_RDMAE register field value. */ +#define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_RESET 0x0 +/* Extracts the ALT_I2C_DMA_CR_RDMAE field value from a register. */ +#define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_DMA_CR_RDMAE register field value suitable for setting the register. */ +#define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit DMA Enable Bit - tdmae + * + * This bit enables/disables the transmit FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:--------------------- + * ALT_I2C_DMA_CR_TDMAE_E_DIS | 0x0 | Transmit DMA disable + * ALT_I2C_DMA_CR_TDMAE_E_EN | 0x1 | Transmit DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE + * + * Transmit DMA disable + */ +#define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE + * + * Transmit DMA enabled + */ +#define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_MSB 1 +/* The width in bits of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_WIDTH 1 +/* The mask used to set the ALT_I2C_DMA_CR_TDMAE register field value. */ +#define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_DMA_CR_TDMAE register field value. */ +#define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_RESET 0x0 +/* Extracts the ALT_I2C_DMA_CR_TDMAE field value from a register. */ +#define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_DMA_CR_TDMAE register field value suitable for setting the register. */ +#define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_CR. + */ +struct ALT_I2C_DMA_CR_s +{ + uint32_t rdmae : 1; /* Receive DMA Enable Bit */ + uint32_t tdmae : 1; /* Transmit DMA Enable Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_CR. */ +typedef volatile struct ALT_I2C_DMA_CR_s ALT_I2C_DMA_CR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_CR register from the beginning of the component. */ +#define ALT_I2C_DMA_CR_OFST 0x88 +/* The address of the ALT_I2C_DMA_CR register. */ +#define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST)) + +/* + * Register : DMA Transmit Data Level - ic_dma_tdlr + * + * This register supports DMA Transmit Operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [5:0] | RW | 0x0 | DMA Transmit Data Level Bit + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DMA Transmit Data Level Bit - dmatdl + * + * This bit field controls the level at which a DMA request is made by the transmit + * logic. It is equal to the watermark level; that is, the i2c_dma_tx_req signal is + * generated when the number of valid data entries in the transmit FIFO is equal to + * or below this field value, and TDMAE = 1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_MSB 5 +/* The width in bits of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6 +/* The mask used to set the ALT_I2C_DMA_TDLR_DMATDL register field value. */ +#define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f +/* The mask used to clear the ALT_I2C_DMA_TDLR_DMATDL register field value. */ +#define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0 +/* Extracts the ALT_I2C_DMA_TDLR_DMATDL field value from a register. */ +#define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_I2C_DMA_TDLR_DMATDL register field value suitable for setting the register. */ +#define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_TDLR. + */ +struct ALT_I2C_DMA_TDLR_s +{ + uint32_t dmatdl : 6; /* DMA Transmit Data Level Bit */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_TDLR. */ +typedef volatile struct ALT_I2C_DMA_TDLR_s ALT_I2C_DMA_TDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_TDLR register from the beginning of the component. */ +#define ALT_I2C_DMA_TDLR_OFST 0x8c +/* The address of the ALT_I2C_DMA_TDLR register. */ +#define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST)) + +/* + * Register : Receive Data Level - ic_dma_rdlr + * + * DMA Control Signals Interface. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [5:0] | RW | 0x0 | Receive Data Level Bits + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive Data Level Bits - dmardl + * + * This bit field controls the level at which a DMA request is made by the receive + * logic. The watermark level \= DMARDL+1; that is, dma_rx_req is generated when + * the number of valid data entries in the receive FIFO is equal to or more than + * this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then + * dma_rx_req is asserted when or more data entries are present in the receive + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_MSB 5 +/* The width in bits of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6 +/* The mask used to set the ALT_I2C_DMA_RDLR_DMARDL register field value. */ +#define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f +/* The mask used to clear the ALT_I2C_DMA_RDLR_DMARDL register field value. */ +#define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0 +/* Extracts the ALT_I2C_DMA_RDLR_DMARDL field value from a register. */ +#define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_I2C_DMA_RDLR_DMARDL register field value suitable for setting the register. */ +#define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_RDLR. + */ +struct ALT_I2C_DMA_RDLR_s +{ + uint32_t dmardl : 6; /* Receive Data Level Bits */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_RDLR. */ +typedef volatile struct ALT_I2C_DMA_RDLR_s ALT_I2C_DMA_RDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_RDLR register from the beginning of the component. */ +#define ALT_I2C_DMA_RDLR_OFST 0x90 +/* The address of the ALT_I2C_DMA_RDLR register. */ +#define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST)) + +/* + * Register : SDA Setup Register - ic_sda_setup + * + * This register controls the amount of time delay (in terms of number of l4_sp_clk + * clock periods) introduced in the rising edge of SCL relative to SDA changing by + * holding SCL low when I2C services a read request while operating as a slave- + * transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the + * I2C Bus Specification. This register must be programmed with a value equal to or + * greater than 2. + * + * Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * + * (l4_sp_clk)], so if the user requires 10 l4_sp_clk periods of setup time, they + * should program a value of 11. The IC_SDA_SETUP register is only used by the I2C + * when operating as a slave transmitter. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [7:0] | RW | 0x64 | SDA Setup Value + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDA Setup Value - sda_setup + * + * It is recommended that if the required delay is 1000ns, then for an l4_sp_clk + * frequency of 10 MHz, ic_sda_setup should be programmed to a value of 11. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7 +/* The width in bits of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8 +/* The mask used to set the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64 +/* Extracts the ALT_I2C_SDA_SETUP_SDA_SETUP field value from a register. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_SDA_SETUP_SDA_SETUP register field value suitable for setting the register. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SDA_SETUP. + */ +struct ALT_I2C_SDA_SETUP_s +{ + uint32_t sda_setup : 8; /* SDA Setup Value */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SDA_SETUP. */ +typedef volatile struct ALT_I2C_SDA_SETUP_s ALT_I2C_SDA_SETUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SDA_SETUP register from the beginning of the component. */ +#define ALT_I2C_SDA_SETUP_OFST 0x94 +/* The address of the ALT_I2C_SDA_SETUP register. */ +#define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST)) + +/* + * Register : ACK General Call - ic_ack_general_call + * + * The register controls whether i2c responds with a ACK or NACK when it receives + * an I2C General Call address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | ACK General Call Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ACK General Call Bit - ack_gen_call + * + * When an ACK is asserted, (by asserting i2c_out_data) when it receives a General + * call. Otherwise, i2c responds with a NACK (by negating i2c_out_data). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------- + * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK | 0x0 | I2C responds with a NACK + * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK | 0x1 | I2C responds with an ACK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL + * + * I2C responds with a NACK + */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0 +/* + * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL + * + * I2C responds with an ACK + */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0 +/* The width in bits of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1 +/* Extracts the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL field value from a register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_ACK_GENERAL_CALL. + */ +struct ALT_I2C_ACK_GENERAL_CALL_s +{ + uint32_t ack_gen_call : 1; /* ACK General Call Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_ACK_GENERAL_CALL. */ +typedef volatile struct ALT_I2C_ACK_GENERAL_CALL_s ALT_I2C_ACK_GENERAL_CALL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_ACK_GENERAL_CALL register from the beginning of the component. */ +#define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98 +/* The address of the ALT_I2C_ACK_GENERAL_CALL register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST)) + +/* + * Register : Enable Status Register - ic_enable_status + * + * This register is used to report the i2c hardware status when the IC_ENABLE + * register is set from 1 to 0; that is, when i2c is disabled. If IC_ENABLE has + * been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE + * has been set to 0, bits 2:1 are only valid as soon as bit 0 is read as '0'. + * + * Note: When ic_enable has been written with '0' a delay occurs for bit 0 to be + * read as '0' because disabling the i2c depends on I2C bus activities. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | R | 0x0 | Enable Status Bit + * [1] | R | 0x0 | Slave Disabled While Busy Bit + * [2] | R | 0x0 | Slave Received Data Lost Bit + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable Status Bit - ic_en + * + * This bit always reflects the value driven on the output port ic_en. Not used in + * current application. When read as 1, i2c is deemed to be in an enabled state. + * When read as 0, i2c is deemed completely inactive. NOTE: The CPU can safely read + * this bit anytime. When this bit is read as 0, the CPU can safely read + * slv_rx_data_lost (bit 2) and slv_disabled_while_busy (bit 1). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_MSB 0 +/* The width in bits of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_IC_EN register field value. */ +#define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_EN_STAT_IC_EN register field value. */ +#define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_IC_EN field value from a register. */ +#define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_EN_STAT_IC_EN register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Slave Disabled While Busy Bit - slv_disabled_while_busy + * + * This bit indicates if a potential or active Slave operation has been aborted due + * to the setting of the ic_enable register from 1 to 0. This bit is set when the + * CPU writes a 0 to the ic_enable register while: (a) I2C is receiving the address + * byte of the Slave-Transmitter operation from a remote master; OR, (b) address + * and data bytes of the Slave-Receiver operation from a remote master. When read + * as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer, + * irrespective of whether the I2C address matches the slave address set in i2c + * (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 + * but has not taken effect. NOTE: If the remote I2C master terminates the transfer + * with a STOP condition before the i2c has a chance to NACK a transfer, and + * IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as + * 0, i2c is deemed to have been disabled when there is master activity, or when + * the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) + * is read as 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1 +/* The width in bits of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY field value from a register. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Slave Received Data Lost Bit - slv_rx_data_lost + * + * This bit indicates if a Slave-Receiver operation has been aborted with at least + * one data byte received from an I2C transfer due to the setting of IC ENABLE from + * 1 to 0. When read as 1, i2c is deemed to have been actively engaged in an + * aborted I2C transfer (with matching address) and the data phase of the I2C + * transfer has been entered, even though a data byte has been responded with a + * NACK. NOTE: If the remote I2C master terminates the transfer with a STOP + * condition before the i2c has a chance to NACK a transfer, and ic_enable has been + * set to 0, then this bit is also set to 1. When read as 0, i2c is deemed to have + * been disabled without being actively involved in the data phase of a Slave- + * Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is + * read as 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2 +/* The width in bits of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST field value from a register. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_EN_STAT. + */ +struct ALT_I2C_EN_STAT_s +{ + const uint32_t ic_en : 1; /* Enable Status Bit */ + const uint32_t slv_disabled_while_busy : 1; /* Slave Disabled While Busy Bit */ + const uint32_t slv_rx_data_lost : 1; /* Slave Received Data Lost Bit */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_EN_STAT. */ +typedef volatile struct ALT_I2C_EN_STAT_s ALT_I2C_EN_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_EN_STAT register from the beginning of the component. */ +#define ALT_I2C_EN_STAT_OFST 0x9c +/* The address of the ALT_I2C_EN_STAT register. */ +#define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST)) + +/* + * Register : SS and FS Spike Suppression Limit Register - ic_fs_spklen + * + * This register is used to store the duration, measured in ic_clk cycles, of the + * longest spike that is filtered out by the spike suppression logic when the + * component is operating in SS or FS modes. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [7:0] | RW | 0x2 | Spike Suppression Limit Register + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Spike Suppression Limit Register - spklen + * + * This register must be set before any I2C bus transaction can take place to + * ensure stable operation. This register sets the duration, measured in ic_clk + * cycles, of the longest spike in the SCL or SDA lines that are filtered out by + * the spike suppression logic. This register can be written only when the I2C + * interface is disabled, which corresponds to the IC_ENABLE register being set to + * 0. Writes at other times have no effect. The minimum valid value is 1; hardware + * prevents values less than this being written, and if attempted results in 2 + * being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_MSB 7 +/* The width in bits of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_WIDTH 8 +/* The mask used to set the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_RESET 0x2 +/* Extracts the ALT_I2C_FS_SPKLEN_SPKLEN field value from a register. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_FS_SPKLEN_SPKLEN register field value suitable for setting the register. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SPKLEN. + */ +struct ALT_I2C_FS_SPKLEN_s +{ + uint32_t spklen : 8; /* Spike Suppression Limit Register */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SPKLEN. */ +typedef volatile struct ALT_I2C_FS_SPKLEN_s ALT_I2C_FS_SPKLEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SPKLEN register from the beginning of the component. */ +#define ALT_I2C_FS_SPKLEN_OFST 0xa0 +/* The address of the ALT_I2C_FS_SPKLEN register. */ +#define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST)) + +/* + * Register : Component Parameter Register 1 - ic_comp_param_1 + * + * This is a constant read-only register that contains encoded information about + * the component's parameter settings. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [1:0] | R | 0x2 | APB Data Width Register + * [3:2] | R | 0x2 | Max Speed Mode + * [4] | R | 0x0 | CNT Registers Access + * [5] | R | 0x1 | Intr IO + * [6] | R | 0x1 | Has DMA + * [7] | R | 0x1 | Add Encoded Params + * [15:8] | R | 0x3f | Rx Buffer Depth + * [23:16] | R | 0x3f | Tx Buffer Depth + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : APB Data Width Register - apb_data_width + * + * Sets the APB Data Width. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width is 32 Bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH + * + * APB Data Width is 32 Bits + */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2 +/* Extracts the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Max Speed Mode - max_speed_mode + * + * The value of this field determines the maximum i2c bus interface speed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------- + * ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST | 0x2 | Fast Mode (400 kbit/s) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD + * + * Fast Mode (400 kbit/s) + */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2 +/* Extracts the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : CNT Registers Access - hc_count_values + * + * This makes the *CNT registers readable and writable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR | 0x0 | *CNT registers read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES + * + * * CNT registers read/write + */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0 +/* Extracts the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Intr IO - intr_io + * + * All interrupt sources are combined in to a single output. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED | 0x1 | Combined Interrupt Output + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_INTR_IO + * + * Combined Interrupt Output + */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_INTR_IO field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_COMP_PARAM_1_INTR_IO register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Has DMA - has_dma + * + * This configures the inclusion of DMA handshaking interface signals. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------ + * ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT | 0x1 | Has DMA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HAS_DMA + * + * Has DMA + */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_HAS_DMA field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_COMP_PARAM_1_HAS_DMA register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Add Encoded Params - add_encoded_params + * + * By adding in the encoded parameters, this gives firmware an easy and quick way + * of identifying the DesignWare component within an I/O memory map. Some critical + * design-time options determine how a driver should interact with the peripheral. + * There is a minimal area overhead by including these parameters. Allows a single + * driver to be developed for each component which will be self-configurable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------------- + * ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Add Encoded Params + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS + * + * Add Encoded Params + */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Rx Buffer Depth - rx_buffer_depth + * + * Sets Rx FIFO Depth. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------------- + * ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Rx Fifo Depth 64 Entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH + * + * Rx Fifo Depth 64 Entries + */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff +/* The reset value of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f +/* Extracts the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Tx Buffer Depth - tx_buffer_depth + * + * Sets Tx FIFO Depth. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Tx Buffer Depth 64 Entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH + * + * Tx Buffer Depth 64 Entries + */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff +/* The reset value of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f +/* Extracts the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_PARAM_1. + */ +struct ALT_I2C_COMP_PARAM_1_s +{ + const uint32_t apb_data_width : 2; /* APB Data Width Register */ + const uint32_t max_speed_mode : 2; /* Max Speed Mode */ + const uint32_t hc_count_values : 1; /* CNT Registers Access */ + const uint32_t intr_io : 1; /* Intr IO */ + const uint32_t has_dma : 1; /* Has DMA */ + const uint32_t add_encoded_params : 1; /* Add Encoded Params */ + const uint32_t rx_buffer_depth : 8; /* Rx Buffer Depth */ + const uint32_t tx_buffer_depth : 8; /* Tx Buffer Depth */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_PARAM_1. */ +typedef volatile struct ALT_I2C_COMP_PARAM_1_s ALT_I2C_COMP_PARAM_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_PARAM_1 register from the beginning of the component. */ +#define ALT_I2C_COMP_PARAM_1_OFST 0xf4 +/* The address of the ALT_I2C_COMP_PARAM_1 register. */ +#define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST)) + +/* + * Register : Component Version Register - ic_comp_version + * + * Describes the version of the I2C + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------------- + * [31:0] | R | 0x3132302a | Component Parameter Value + * + */ +/* + * Field : Component Parameter Value - ic_comp_version + * + * Specifies I2C release number (encoded as 4 ASCII characters) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:-----------|:-------------- + * ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A | 0x3132302a | Version 1.20a + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_VER_IC_COMP_VER + * + * Version 1.20a + */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A 0x3132302a + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31 +/* The width in bits of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32 +/* The mask used to set the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff +/* The mask used to clear the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000 +/* The reset value of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132302a +/* Extracts the ALT_I2C_COMP_VER_IC_COMP_VER field value from a register. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_I2C_COMP_VER_IC_COMP_VER register field value suitable for setting the register. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_VER. + */ +struct ALT_I2C_COMP_VER_s +{ + const uint32_t ic_comp_version : 32; /* Component Parameter Value */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_VER. */ +typedef volatile struct ALT_I2C_COMP_VER_s ALT_I2C_COMP_VER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_VER register from the beginning of the component. */ +#define ALT_I2C_COMP_VER_OFST 0xf8 +/* The address of the ALT_I2C_COMP_VER register. */ +#define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST)) + +/* + * Register : Component Type Register - ic_comp_type + * + * Describes a unique ASCII value + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | R | 0x44570140 | Component Type Number + * + */ +/* + * Field : Component Type Number - ic_comp_type + * + * Designware Component Type number = 0x44_57_01_40. This assigned unique hex value + * is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit + * unsigned number. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31 +/* The width in bits of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32 +/* The mask used to set the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000 +/* The reset value of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140 +/* Extracts the ALT_I2C_COMP_TYPE_IC_COMP_TYPE field value from a register. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value suitable for setting the register. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_TYPE. + */ +struct ALT_I2C_COMP_TYPE_s +{ + const uint32_t ic_comp_type : 32; /* Component Type Number */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_TYPE. */ +typedef volatile struct ALT_I2C_COMP_TYPE_s ALT_I2C_COMP_TYPE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_TYPE register from the beginning of the component. */ +#define ALT_I2C_COMP_TYPE_OFST 0xfc +/* The address of the ALT_I2C_COMP_TYPE register. */ +#define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_I2C. + */ +struct ALT_I2C_s +{ + volatile ALT_I2C_CON_t ic_con; /* ALT_I2C_CON */ + volatile ALT_I2C_TAR_t ic_tar; /* ALT_I2C_TAR */ + volatile ALT_I2C_SAR_t ic_sar; /* ALT_I2C_SAR */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_I2C_DATA_CMD_t ic_data_cmd; /* ALT_I2C_DATA_CMD */ + volatile ALT_I2C_SS_SCL_HCNT_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */ + volatile ALT_I2C_SS_SCL_LCNT_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */ + volatile ALT_I2C_FS_SCL_HCNT_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */ + volatile ALT_I2C_FS_SCL_LCNT_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */ + volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */ + volatile ALT_I2C_INTR_STAT_t ic_intr_stat; /* ALT_I2C_INTR_STAT */ + volatile ALT_I2C_INTR_MSK_t ic_intr_mask; /* ALT_I2C_INTR_MSK */ + volatile ALT_I2C_RAW_INTR_STAT_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */ + volatile ALT_I2C_RX_TL_t ic_rx_tl; /* ALT_I2C_RX_TL */ + volatile ALT_I2C_TX_TL_t ic_tx_tl; /* ALT_I2C_TX_TL */ + volatile ALT_I2C_CLR_INTR_t ic_clr_intr; /* ALT_I2C_CLR_INTR */ + volatile ALT_I2C_CLR_RX_UNDER_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */ + volatile ALT_I2C_CLR_RX_OVER_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */ + volatile ALT_I2C_CLR_TX_OVER_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */ + volatile ALT_I2C_CLR_RD_REQ_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */ + volatile ALT_I2C_CLR_TX_ABRT_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */ + volatile ALT_I2C_CLR_RX_DONE_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */ + volatile ALT_I2C_CLR_ACTIVITY_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */ + volatile ALT_I2C_CLR_STOP_DET_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */ + volatile ALT_I2C_CLR_START_DET_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */ + volatile ALT_I2C_CLR_GEN_CALL_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */ + volatile ALT_I2C_EN_t ic_enable; /* ALT_I2C_EN */ + volatile ALT_I2C_STAT_t ic_status; /* ALT_I2C_STAT */ + volatile ALT_I2C_TXFLR_t ic_txflr; /* ALT_I2C_TXFLR */ + volatile ALT_I2C_RXFLR_t ic_rxflr; /* ALT_I2C_RXFLR */ + volatile ALT_I2C_SDA_HOLD_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */ + volatile ALT_I2C_TX_ABRT_SRC_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */ + volatile ALT_I2C_SLV_DATA_NACK_ONLY_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */ + volatile ALT_I2C_DMA_CR_t ic_dma_cr; /* ALT_I2C_DMA_CR */ + volatile ALT_I2C_DMA_TDLR_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */ + volatile ALT_I2C_DMA_RDLR_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */ + volatile ALT_I2C_SDA_SETUP_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */ + volatile ALT_I2C_ACK_GENERAL_CALL_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */ + volatile ALT_I2C_EN_STAT_t ic_enable_status; /* ALT_I2C_EN_STAT */ + volatile ALT_I2C_FS_SPKLEN_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */ + volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */ + volatile ALT_I2C_COMP_PARAM_1_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */ + volatile ALT_I2C_COMP_VER_t ic_comp_version; /* ALT_I2C_COMP_VER */ + volatile ALT_I2C_COMP_TYPE_t ic_comp_type; /* ALT_I2C_COMP_TYPE */ +}; + +/* The typedef declaration for register group ALT_I2C. */ +typedef volatile struct ALT_I2C_s ALT_I2C_t; +/* The struct declaration for the raw register contents of register group ALT_I2C. */ +struct ALT_I2C_raw_s +{ + volatile uint32_t ic_con; /* ALT_I2C_CON */ + volatile uint32_t ic_tar; /* ALT_I2C_TAR */ + volatile uint32_t ic_sar; /* ALT_I2C_SAR */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t ic_data_cmd; /* ALT_I2C_DATA_CMD */ + volatile uint32_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */ + volatile uint32_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */ + volatile uint32_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */ + volatile uint32_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */ + volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */ + volatile uint32_t ic_intr_stat; /* ALT_I2C_INTR_STAT */ + volatile uint32_t ic_intr_mask; /* ALT_I2C_INTR_MSK */ + volatile uint32_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */ + volatile uint32_t ic_rx_tl; /* ALT_I2C_RX_TL */ + volatile uint32_t ic_tx_tl; /* ALT_I2C_TX_TL */ + volatile uint32_t ic_clr_intr; /* ALT_I2C_CLR_INTR */ + volatile uint32_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */ + volatile uint32_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */ + volatile uint32_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */ + volatile uint32_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */ + volatile uint32_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */ + volatile uint32_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */ + volatile uint32_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */ + volatile uint32_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */ + volatile uint32_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */ + volatile uint32_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */ + volatile uint32_t ic_enable; /* ALT_I2C_EN */ + volatile uint32_t ic_status; /* ALT_I2C_STAT */ + volatile uint32_t ic_txflr; /* ALT_I2C_TXFLR */ + volatile uint32_t ic_rxflr; /* ALT_I2C_RXFLR */ + volatile uint32_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */ + volatile uint32_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */ + volatile uint32_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */ + volatile uint32_t ic_dma_cr; /* ALT_I2C_DMA_CR */ + volatile uint32_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */ + volatile uint32_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */ + volatile uint32_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */ + volatile uint32_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */ + volatile uint32_t ic_enable_status; /* ALT_I2C_EN_STAT */ + volatile uint32_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */ + volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */ + volatile uint32_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */ + volatile uint32_t ic_comp_version; /* ALT_I2C_COMP_VER */ + volatile uint32_t ic_comp_type; /* ALT_I2C_COMP_TYPE */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_I2C. */ +typedef volatile struct ALT_I2C_raw_s ALT_I2C_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_I2C_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h new file mode 100644 index 0000000000..12e6f21b89 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h @@ -0,0 +1,6299 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_L3 */ + +#ifndef __ALTERA_ALT_L3_H__ +#define __ALTERA_ALT_L3_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : L3 (NIC-301) GPV Registers - ALT_L3 + * L3 (NIC-301) GPV Registers + * + * Registers to control L3 interconnect settings + * + */ +/* + * Register : Remap - remap + * + * The L3 interconnect has separate address maps for the various L3 Masters. + * Generally, the addresses are the same for most masters. However, the sparse + * interconnect of the L3 switch causes some masters to have holes in their memory + * maps. The remap bits are not mutually exclusive. Each bit can be set + * independently and in combinations. Priority for the bits is determined by the + * bit offset: lower offset bits take precedence over higher offset bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [0] | W | 0x0 | MPU at 0x0 + * [1] | W | 0x0 | Non-MPU at 0x0 + * [2] | ??? | 0x0 | *UNDEFINED* + * [3] | W | 0x0 | HPS2FPGA AXI Bridge Visibility + * [4] | W | 0x0 | LWHPS2FPGA AXI Bridge Visibility + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MPU at 0x0 - mpuzero + * + * Controls whether address 0x0 for the MPU L3 master is mapped to the Boot ROM or + * On-chip RAM. This field only has an effect on the MPU L3 master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------------------------------- + * ALT_L3_REMAP_MPUZERO_E_BOOTROM | 0x0 | Maps the Boot ROM to address 0x0 for the MPU L3 + * : | | master. Note that the Boot ROM is also always + * : | | mapped to address 0xfffd_0000 for the MPU L3 + * : | | master independent of this field's value. + * ALT_L3_REMAP_MPUZERO_E_OCRAM | 0x1 | Maps the On-chip RAM to address 0x0 for the MPU + * : | | L3 master. Note that the On-chip RAM is also + * : | | always mapped to address 0xffff_0000 for the MPU + * : | | L3 master independent of this field's value. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_REMAP_MPUZERO + * + * Maps the Boot ROM to address 0x0 for the MPU L3 master. Note that the Boot ROM + * is also always mapped to address 0xfffd_0000 for the MPU L3 master independent + * of this field's value. + */ +#define ALT_L3_REMAP_MPUZERO_E_BOOTROM 0x0 +/* + * Enumerated value for register field ALT_L3_REMAP_MPUZERO + * + * Maps the On-chip RAM to address 0x0 for the MPU L3 master. Note that the On-chip + * RAM is also always mapped to address 0xffff_0000 for the MPU L3 master + * independent of this field's value. + */ +#define ALT_L3_REMAP_MPUZERO_E_OCRAM 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_MPUZERO register field. */ +#define ALT_L3_REMAP_MPUZERO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_MPUZERO register field. */ +#define ALT_L3_REMAP_MPUZERO_MSB 0 +/* The width in bits of the ALT_L3_REMAP_MPUZERO register field. */ +#define ALT_L3_REMAP_MPUZERO_WIDTH 1 +/* The mask used to set the ALT_L3_REMAP_MPUZERO register field value. */ +#define ALT_L3_REMAP_MPUZERO_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_REMAP_MPUZERO register field value. */ +#define ALT_L3_REMAP_MPUZERO_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_REMAP_MPUZERO register field. */ +#define ALT_L3_REMAP_MPUZERO_RESET 0x0 +/* Extracts the ALT_L3_REMAP_MPUZERO field value from a register. */ +#define ALT_L3_REMAP_MPUZERO_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_REMAP_MPUZERO register field value suitable for setting the register. */ +#define ALT_L3_REMAP_MPUZERO_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Non-MPU at 0x0 - nonmpuzero + * + * Controls whether address 0x0 for the non-MPU L3 masters is mapped to the SDRAM + * or On-chip RAM. This field only has an effect on the non-MPU L3 masters. The + * non-MPU L3 masters are the DMA controllers (standalone and those built-in to + * peripherals), the FPGA2HPS AXI Bridge, and the DAP. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------- + * ALT_L3_REMAP_NONMPUZERO_E_SDRAM | 0x0 | Maps the SDRAM to address 0x0 for the non-MPU L3 + * : | | masters. + * ALT_L3_REMAP_NONMPUZERO_E_OCRAM | 0x1 | Maps the On-chip RAM to address 0x0 for the non- + * : | | MPU L3 masters. Note that the On-chip RAM is + * : | | also always mapped to address 0xffff_0000 for + * : | | the non-MPU L3 masters independent of this + * : | | field's value. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO + * + * Maps the SDRAM to address 0x0 for the non-MPU L3 masters. + */ +#define ALT_L3_REMAP_NONMPUZERO_E_SDRAM 0x0 +/* + * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO + * + * Maps the On-chip RAM to address 0x0 for the non-MPU L3 masters. Note that the + * On-chip RAM is also always mapped to address 0xffff_0000 for the non-MPU L3 + * masters independent of this field's value. + */ +#define ALT_L3_REMAP_NONMPUZERO_E_OCRAM 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */ +#define ALT_L3_REMAP_NONMPUZERO_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */ +#define ALT_L3_REMAP_NONMPUZERO_MSB 1 +/* The width in bits of the ALT_L3_REMAP_NONMPUZERO register field. */ +#define ALT_L3_REMAP_NONMPUZERO_WIDTH 1 +/* The mask used to set the ALT_L3_REMAP_NONMPUZERO register field value. */ +#define ALT_L3_REMAP_NONMPUZERO_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_REMAP_NONMPUZERO register field value. */ +#define ALT_L3_REMAP_NONMPUZERO_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_REMAP_NONMPUZERO register field. */ +#define ALT_L3_REMAP_NONMPUZERO_RESET 0x0 +/* Extracts the ALT_L3_REMAP_NONMPUZERO field value from a register. */ +#define ALT_L3_REMAP_NONMPUZERO_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_REMAP_NONMPUZERO register field value suitable for setting the register. */ +#define ALT_L3_REMAP_NONMPUZERO_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : HPS2FPGA AXI Bridge Visibility - hps2fpga + * + * Controls whether the HPS2FPGA AXI Bridge is visible to L3 masters or not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------------------------------------ + * ALT_L3_REMAP_H2F_E_INVISIBLE | 0x0 | The HPS2FPGA AXI Bridge is not visible to L3 + * : | | masters. Accesses to the associated address + * : | | range return an AXI decode error to the master. + * ALT_L3_REMAP_H2F_E_VISIBLE | 0x1 | The HPS2FPGA AXI Bridge is visible to L3 + * : | | masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_REMAP_H2F + * + * The HPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the associated + * address range return an AXI decode error to the master. + */ +#define ALT_L3_REMAP_H2F_E_INVISIBLE 0x0 +/* + * Enumerated value for register field ALT_L3_REMAP_H2F + * + * The HPS2FPGA AXI Bridge is visible to L3 masters. + */ +#define ALT_L3_REMAP_H2F_E_VISIBLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_H2F register field. */ +#define ALT_L3_REMAP_H2F_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_H2F register field. */ +#define ALT_L3_REMAP_H2F_MSB 3 +/* The width in bits of the ALT_L3_REMAP_H2F register field. */ +#define ALT_L3_REMAP_H2F_WIDTH 1 +/* The mask used to set the ALT_L3_REMAP_H2F register field value. */ +#define ALT_L3_REMAP_H2F_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_REMAP_H2F register field value. */ +#define ALT_L3_REMAP_H2F_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_REMAP_H2F register field. */ +#define ALT_L3_REMAP_H2F_RESET 0x0 +/* Extracts the ALT_L3_REMAP_H2F field value from a register. */ +#define ALT_L3_REMAP_H2F_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_REMAP_H2F register field value suitable for setting the register. */ +#define ALT_L3_REMAP_H2F_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : LWHPS2FPGA AXI Bridge Visibility - lwhps2fpga + * + * Controls whether the Lightweight HPS2FPGA AXI Bridge is visible to L3 masters or + * not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------------------------------ + * ALT_L3_REMAP_LWH2F_E_INVISIBLE | 0x0 | The LWHPS2FPGA AXI Bridge is not visible to L3 + * : | | masters. Accesses to the associated address + * : | | range return an AXI decode error to the master. + * ALT_L3_REMAP_LWH2F_E_VISIBLE | 0x1 | The LWHPS2FPGA AXI Bridge is visible to L3 + * : | | masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_REMAP_LWH2F + * + * The LWHPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the + * associated address range return an AXI decode error to the master. + */ +#define ALT_L3_REMAP_LWH2F_E_INVISIBLE 0x0 +/* + * Enumerated value for register field ALT_L3_REMAP_LWH2F + * + * The LWHPS2FPGA AXI Bridge is visible to L3 masters. + */ +#define ALT_L3_REMAP_LWH2F_E_VISIBLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_LWH2F register field. */ +#define ALT_L3_REMAP_LWH2F_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_LWH2F register field. */ +#define ALT_L3_REMAP_LWH2F_MSB 4 +/* The width in bits of the ALT_L3_REMAP_LWH2F register field. */ +#define ALT_L3_REMAP_LWH2F_WIDTH 1 +/* The mask used to set the ALT_L3_REMAP_LWH2F register field value. */ +#define ALT_L3_REMAP_LWH2F_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L3_REMAP_LWH2F register field value. */ +#define ALT_L3_REMAP_LWH2F_CLR_MSK 0xffffffef +/* The reset value of the ALT_L3_REMAP_LWH2F register field. */ +#define ALT_L3_REMAP_LWH2F_RESET 0x0 +/* Extracts the ALT_L3_REMAP_LWH2F field value from a register. */ +#define ALT_L3_REMAP_LWH2F_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L3_REMAP_LWH2F register field value suitable for setting the register. */ +#define ALT_L3_REMAP_LWH2F_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_REMAP. + */ +struct ALT_L3_REMAP_s +{ + uint32_t mpuzero : 1; /* MPU at 0x0 */ + uint32_t nonmpuzero : 1; /* Non-MPU at 0x0 */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t hps2fpga : 1; /* HPS2FPGA AXI Bridge Visibility */ + uint32_t lwhps2fpga : 1; /* LWHPS2FPGA AXI Bridge Visibility */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_REMAP. */ +typedef volatile struct ALT_L3_REMAP_s ALT_L3_REMAP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_REMAP register from the beginning of the component. */ +#define ALT_L3_REMAP_OFST 0x0 + +/* + * Register Group : Security Register Group - ALT_L3_SECGRP + * Security Register Group + * + * Registers that control slave security. + * + */ +/* + * Register : L4 Main Peripherals Security - l4main + * + * Controls security settings for L4 Main peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | W | 0x0 | SPI Slave 0 Security + * [1] | W | 0x0 | SPI Slave 1 Security + * [2] | W | 0x0 | DMA Secure Security + * [3] | W | 0x0 | DMA Non-secure Security + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SPI Slave 0 Security - spis0 + * + * Controls whether secure or non-secure masters can access the SPI Slave 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MAIN_SPIS0 field value from a register. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4MAIN_SPIS0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SPI Slave 1 Security - spis1 + * + * Controls whether secure or non-secure masters can access the SPI Slave 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MAIN_SPIS1 field value from a register. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4MAIN_SPIS1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : DMA Secure Security - dmasecure + * + * Controls whether secure or non-secure masters can access the DMA Secure slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MAIN_DMASECURE field value from a register. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4MAIN_DMASECURE register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DMA Non-secure Security - dmanonsecure + * + * Controls whether secure or non-secure masters can access the DMA Non-secure + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_MSB 3 +/* The width in bits of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MAIN_DMANONSECURE field value from a register. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_SEC_L4MAIN_DMANONSECURE register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4MAIN. + */ +struct ALT_L3_SEC_L4MAIN_s +{ + uint32_t spis0 : 1; /* SPI Slave 0 Security */ + uint32_t spis1 : 1; /* SPI Slave 1 Security */ + uint32_t dmasecure : 1; /* DMA Secure Security */ + uint32_t dmanonsecure : 1; /* DMA Non-secure Security */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4MAIN. */ +typedef volatile struct ALT_L3_SEC_L4MAIN_s ALT_L3_SEC_L4MAIN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4MAIN register from the beginning of the component. */ +#define ALT_L3_SEC_L4MAIN_OFST 0x0 + +/* + * Register : L4 SP Peripherals Security - l4sp + * + * Controls security settings for L4 SP peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [0] | W | 0x0 | SDRAM Registers Security + * [1] | W | 0x0 | SP Timer 0 Security + * [2] | W | 0x0 | I2C0 Security + * [3] | W | 0x0 | I2C1 Security + * [4] | W | 0x0 | I2C2 (EMAC 0) Security + * [5] | W | 0x0 | I2C3 (EMAC 1) Security + * [6] | W | 0x0 | UART 0 Security + * [7] | W | 0x0 | UART 1 Security + * [8] | W | 0x0 | CAN 0 Security + * [9] | W | 0x0 | CAN 1 Security + * [10] | W | 0x0 | SP Timer 1 Security + * [31:11] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDRAM Registers Security - sdrregs + * + * Controls whether secure or non-secure masters can access the SDRAM Registers + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_SDRREGS_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_SDRREGS_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */ +#define ALT_L3_SEC_L4SP_SDRREGS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */ +#define ALT_L3_SEC_L4SP_SDRREGS_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4SP_SDRREGS register field. */ +#define ALT_L3_SEC_L4SP_SDRREGS_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_SDRREGS register field value. */ +#define ALT_L3_SEC_L4SP_SDRREGS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4SP_SDRREGS register field value. */ +#define ALT_L3_SEC_L4SP_SDRREGS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4SP_SDRREGS register field. */ +#define ALT_L3_SEC_L4SP_SDRREGS_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_SDRREGS field value from a register. */ +#define ALT_L3_SEC_L4SP_SDRREGS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4SP_SDRREGS register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_SDRREGS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SP Timer 0 Security - sptimer0 + * + * Controls whether secure or non-secure masters can access the SP Timer 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_SPTMR0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_SPTMR0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR0_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR0_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_SPTMR0 register field value. */ +#define ALT_L3_SEC_L4SP_SPTMR0_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR0 register field value. */ +#define ALT_L3_SEC_L4SP_SPTMR0_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_SPTMR0 field value from a register. */ +#define ALT_L3_SEC_L4SP_SPTMR0_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4SP_SPTMR0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_SPTMR0_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : I2C0 Security - i2c0 + * + * Controls whether secure or non-secure masters can access the I2C0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_I2C0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_I2C0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_I2C0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_I2C0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */ +#define ALT_L3_SEC_L4SP_I2C0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */ +#define ALT_L3_SEC_L4SP_I2C0_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4SP_I2C0 register field. */ +#define ALT_L3_SEC_L4SP_I2C0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_I2C0 register field value. */ +#define ALT_L3_SEC_L4SP_I2C0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4SP_I2C0 register field value. */ +#define ALT_L3_SEC_L4SP_I2C0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4SP_I2C0 register field. */ +#define ALT_L3_SEC_L4SP_I2C0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_I2C0 field value from a register. */ +#define ALT_L3_SEC_L4SP_I2C0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4SP_I2C0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_I2C0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : I2C1 Security - i2c1 + * + * Controls whether secure or non-secure masters can access the I2C1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_I2C1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_I2C1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_I2C1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_I2C1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */ +#define ALT_L3_SEC_L4SP_I2C1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */ +#define ALT_L3_SEC_L4SP_I2C1_MSB 3 +/* The width in bits of the ALT_L3_SEC_L4SP_I2C1 register field. */ +#define ALT_L3_SEC_L4SP_I2C1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_I2C1 register field value. */ +#define ALT_L3_SEC_L4SP_I2C1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_SEC_L4SP_I2C1 register field value. */ +#define ALT_L3_SEC_L4SP_I2C1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_SEC_L4SP_I2C1 register field. */ +#define ALT_L3_SEC_L4SP_I2C1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_I2C1 field value from a register. */ +#define ALT_L3_SEC_L4SP_I2C1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_SEC_L4SP_I2C1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_I2C1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : I2C2 (EMAC 0) Security - i2c2 + * + * Controls whether secure or non-secure masters can access the I2C2 (EMAC 0) + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_I2C2_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_I2C2_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_I2C2_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_I2C2_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */ +#define ALT_L3_SEC_L4SP_I2C2_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */ +#define ALT_L3_SEC_L4SP_I2C2_MSB 4 +/* The width in bits of the ALT_L3_SEC_L4SP_I2C2 register field. */ +#define ALT_L3_SEC_L4SP_I2C2_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_I2C2 register field value. */ +#define ALT_L3_SEC_L4SP_I2C2_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L3_SEC_L4SP_I2C2 register field value. */ +#define ALT_L3_SEC_L4SP_I2C2_CLR_MSK 0xffffffef +/* The reset value of the ALT_L3_SEC_L4SP_I2C2 register field. */ +#define ALT_L3_SEC_L4SP_I2C2_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_I2C2 field value from a register. */ +#define ALT_L3_SEC_L4SP_I2C2_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L3_SEC_L4SP_I2C2 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_I2C2_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : I2C3 (EMAC 1) Security - i2c3 + * + * Controls whether secure or non-secure masters can access the I2C3 (EMAC 1) + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_I2C3_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_I2C3_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_I2C3_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_I2C3_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */ +#define ALT_L3_SEC_L4SP_I2C3_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */ +#define ALT_L3_SEC_L4SP_I2C3_MSB 5 +/* The width in bits of the ALT_L3_SEC_L4SP_I2C3 register field. */ +#define ALT_L3_SEC_L4SP_I2C3_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_I2C3 register field value. */ +#define ALT_L3_SEC_L4SP_I2C3_SET_MSK 0x00000020 +/* The mask used to clear the ALT_L3_SEC_L4SP_I2C3 register field value. */ +#define ALT_L3_SEC_L4SP_I2C3_CLR_MSK 0xffffffdf +/* The reset value of the ALT_L3_SEC_L4SP_I2C3 register field. */ +#define ALT_L3_SEC_L4SP_I2C3_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_I2C3 field value from a register. */ +#define ALT_L3_SEC_L4SP_I2C3_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_L3_SEC_L4SP_I2C3 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_I2C3_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : UART 0 Security - uart0 + * + * Controls whether secure or non-secure masters can access the UART 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_UART0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_UART0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_UART0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_UART0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_UART0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_UART0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */ +#define ALT_L3_SEC_L4SP_UART0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */ +#define ALT_L3_SEC_L4SP_UART0_MSB 6 +/* The width in bits of the ALT_L3_SEC_L4SP_UART0 register field. */ +#define ALT_L3_SEC_L4SP_UART0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_UART0 register field value. */ +#define ALT_L3_SEC_L4SP_UART0_SET_MSK 0x00000040 +/* The mask used to clear the ALT_L3_SEC_L4SP_UART0 register field value. */ +#define ALT_L3_SEC_L4SP_UART0_CLR_MSK 0xffffffbf +/* The reset value of the ALT_L3_SEC_L4SP_UART0 register field. */ +#define ALT_L3_SEC_L4SP_UART0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_UART0 field value from a register. */ +#define ALT_L3_SEC_L4SP_UART0_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_L3_SEC_L4SP_UART0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_UART0_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : UART 1 Security - uart1 + * + * Controls whether secure or non-secure masters can access the UART 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_UART1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_UART1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_UART1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_UART1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_UART1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_UART1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */ +#define ALT_L3_SEC_L4SP_UART1_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */ +#define ALT_L3_SEC_L4SP_UART1_MSB 7 +/* The width in bits of the ALT_L3_SEC_L4SP_UART1 register field. */ +#define ALT_L3_SEC_L4SP_UART1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_UART1 register field value. */ +#define ALT_L3_SEC_L4SP_UART1_SET_MSK 0x00000080 +/* The mask used to clear the ALT_L3_SEC_L4SP_UART1 register field value. */ +#define ALT_L3_SEC_L4SP_UART1_CLR_MSK 0xffffff7f +/* The reset value of the ALT_L3_SEC_L4SP_UART1 register field. */ +#define ALT_L3_SEC_L4SP_UART1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_UART1 field value from a register. */ +#define ALT_L3_SEC_L4SP_UART1_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_L3_SEC_L4SP_UART1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_UART1_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : CAN 0 Security - can0 + * + * Controls whether secure or non-secure masters can access the CAN 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_CAN0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_CAN0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_CAN0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_CAN0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */ +#define ALT_L3_SEC_L4SP_CAN0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */ +#define ALT_L3_SEC_L4SP_CAN0_MSB 8 +/* The width in bits of the ALT_L3_SEC_L4SP_CAN0 register field. */ +#define ALT_L3_SEC_L4SP_CAN0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_CAN0 register field value. */ +#define ALT_L3_SEC_L4SP_CAN0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_L3_SEC_L4SP_CAN0 register field value. */ +#define ALT_L3_SEC_L4SP_CAN0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_L3_SEC_L4SP_CAN0 register field. */ +#define ALT_L3_SEC_L4SP_CAN0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_CAN0 field value from a register. */ +#define ALT_L3_SEC_L4SP_CAN0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_L3_SEC_L4SP_CAN0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_CAN0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : CAN 1 Security - can1 + * + * Controls whether secure or non-secure masters can access the CAN 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_CAN1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_CAN1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_CAN1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_CAN1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */ +#define ALT_L3_SEC_L4SP_CAN1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */ +#define ALT_L3_SEC_L4SP_CAN1_MSB 9 +/* The width in bits of the ALT_L3_SEC_L4SP_CAN1 register field. */ +#define ALT_L3_SEC_L4SP_CAN1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_CAN1 register field value. */ +#define ALT_L3_SEC_L4SP_CAN1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_L3_SEC_L4SP_CAN1 register field value. */ +#define ALT_L3_SEC_L4SP_CAN1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_L3_SEC_L4SP_CAN1 register field. */ +#define ALT_L3_SEC_L4SP_CAN1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_CAN1 field value from a register. */ +#define ALT_L3_SEC_L4SP_CAN1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_L3_SEC_L4SP_CAN1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_CAN1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : SP Timer 1 Security - sptimer1 + * + * Controls whether secure or non-secure masters can access the SP Timer 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_SPTMR1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_SPTMR1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR1_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR1_MSB 10 +/* The width in bits of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_SPTMR1 register field value. */ +#define ALT_L3_SEC_L4SP_SPTMR1_SET_MSK 0x00000400 +/* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR1 register field value. */ +#define ALT_L3_SEC_L4SP_SPTMR1_CLR_MSK 0xfffffbff +/* The reset value of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_SPTMR1 field value from a register. */ +#define ALT_L3_SEC_L4SP_SPTMR1_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_L3_SEC_L4SP_SPTMR1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_SPTMR1_SET(value) (((value) << 10) & 0x00000400) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4SP. + */ +struct ALT_L3_SEC_L4SP_s +{ + uint32_t sdrregs : 1; /* SDRAM Registers Security */ + uint32_t sptimer0 : 1; /* SP Timer 0 Security */ + uint32_t i2c0 : 1; /* I2C0 Security */ + uint32_t i2c1 : 1; /* I2C1 Security */ + uint32_t i2c2 : 1; /* I2C2 (EMAC 0) Security */ + uint32_t i2c3 : 1; /* I2C3 (EMAC 1) Security */ + uint32_t uart0 : 1; /* UART 0 Security */ + uint32_t uart1 : 1; /* UART 1 Security */ + uint32_t can0 : 1; /* CAN 0 Security */ + uint32_t can1 : 1; /* CAN 1 Security */ + uint32_t sptimer1 : 1; /* SP Timer 1 Security */ + uint32_t : 21; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4SP. */ +typedef volatile struct ALT_L3_SEC_L4SP_s ALT_L3_SEC_L4SP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4SP register from the beginning of the component. */ +#define ALT_L3_SEC_L4SP_OFST 0x4 + +/* + * Register : L4 MP Peripherals Security - l4mp + * + * Controls security settings for L4 MP peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------- + * [0] | W | 0x0 | FPGA Manager Register Security + * [1] | W | 0x0 | DAP Security + * [2] | W | 0x0 | QSPI Registers Security + * [3] | W | 0x0 | SDMMC Security + * [4] | W | 0x0 | EMAC 0 Security + * [5] | W | 0x0 | EMAC 1 Security + * [6] | W | 0x0 | ACP ID Mapper Security + * [7] | W | 0x0 | GPIO 0 Security + * [8] | W | 0x0 | GPIO 1 Security + * [9] | W | 0x0 | GPIO 2 Security + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FPGA Manager Register Security - fpgamgrregs + * + * Controls whether secure or non-secure masters can access the FPGA Manager + * Register slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_FPGAMGR register field value. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4MP_FPGAMGR register field value. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_FPGAMGR field value from a register. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4MP_FPGAMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : DAP Security - dap + * + * Controls whether secure or non-secure masters can access the DAP slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_DAP_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_DAP_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_DAP + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_DAP_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_DAP + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_DAP_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_DAP register field. */ +#define ALT_L3_SEC_L4MP_DAP_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_DAP register field. */ +#define ALT_L3_SEC_L4MP_DAP_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4MP_DAP register field. */ +#define ALT_L3_SEC_L4MP_DAP_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_DAP register field value. */ +#define ALT_L3_SEC_L4MP_DAP_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4MP_DAP register field value. */ +#define ALT_L3_SEC_L4MP_DAP_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4MP_DAP register field. */ +#define ALT_L3_SEC_L4MP_DAP_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_DAP field value from a register. */ +#define ALT_L3_SEC_L4MP_DAP_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4MP_DAP register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_DAP_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : QSPI Registers Security - qspiregs + * + * Controls whether secure or non-secure masters can access the QSPI Registers + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_QSPI_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_QSPI_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_QSPI_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_QSPI_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */ +#define ALT_L3_SEC_L4MP_QSPI_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */ +#define ALT_L3_SEC_L4MP_QSPI_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4MP_QSPI register field. */ +#define ALT_L3_SEC_L4MP_QSPI_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_QSPI register field value. */ +#define ALT_L3_SEC_L4MP_QSPI_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4MP_QSPI register field value. */ +#define ALT_L3_SEC_L4MP_QSPI_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4MP_QSPI register field. */ +#define ALT_L3_SEC_L4MP_QSPI_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_QSPI field value from a register. */ +#define ALT_L3_SEC_L4MP_QSPI_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4MP_QSPI register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_QSPI_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SDMMC Security - sdmmc + * + * Controls whether secure or non-secure masters can access the SDMMC slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_SDMMC_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_SDMMC_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */ +#define ALT_L3_SEC_L4MP_SDMMC_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */ +#define ALT_L3_SEC_L4MP_SDMMC_MSB 3 +/* The width in bits of the ALT_L3_SEC_L4MP_SDMMC register field. */ +#define ALT_L3_SEC_L4MP_SDMMC_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_SDMMC register field value. */ +#define ALT_L3_SEC_L4MP_SDMMC_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_SEC_L4MP_SDMMC register field value. */ +#define ALT_L3_SEC_L4MP_SDMMC_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_SEC_L4MP_SDMMC register field. */ +#define ALT_L3_SEC_L4MP_SDMMC_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_SDMMC field value from a register. */ +#define ALT_L3_SEC_L4MP_SDMMC_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_SEC_L4MP_SDMMC register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_SDMMC_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : EMAC 0 Security - emac0 + * + * Controls whether secure or non-secure masters can access the EMAC 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_EMAC0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_EMAC0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */ +#define ALT_L3_SEC_L4MP_EMAC0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */ +#define ALT_L3_SEC_L4MP_EMAC0_MSB 4 +/* The width in bits of the ALT_L3_SEC_L4MP_EMAC0 register field. */ +#define ALT_L3_SEC_L4MP_EMAC0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_EMAC0 register field value. */ +#define ALT_L3_SEC_L4MP_EMAC0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L3_SEC_L4MP_EMAC0 register field value. */ +#define ALT_L3_SEC_L4MP_EMAC0_CLR_MSK 0xffffffef +/* The reset value of the ALT_L3_SEC_L4MP_EMAC0 register field. */ +#define ALT_L3_SEC_L4MP_EMAC0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_EMAC0 field value from a register. */ +#define ALT_L3_SEC_L4MP_EMAC0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L3_SEC_L4MP_EMAC0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_EMAC0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : EMAC 1 Security - emac1 + * + * Controls whether secure or non-secure masters can access the EMAC 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_EMAC1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_EMAC1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */ +#define ALT_L3_SEC_L4MP_EMAC1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */ +#define ALT_L3_SEC_L4MP_EMAC1_MSB 5 +/* The width in bits of the ALT_L3_SEC_L4MP_EMAC1 register field. */ +#define ALT_L3_SEC_L4MP_EMAC1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_EMAC1 register field value. */ +#define ALT_L3_SEC_L4MP_EMAC1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_L3_SEC_L4MP_EMAC1 register field value. */ +#define ALT_L3_SEC_L4MP_EMAC1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_L3_SEC_L4MP_EMAC1 register field. */ +#define ALT_L3_SEC_L4MP_EMAC1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_EMAC1 field value from a register. */ +#define ALT_L3_SEC_L4MP_EMAC1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_L3_SEC_L4MP_EMAC1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_EMAC1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : ACP ID Mapper Security - acpidmap + * + * Controls whether secure or non-secure masters can access the ACP ID Mapper + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_MSB 6 +/* The width in bits of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_ACPIDMAP field value from a register. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_L3_SEC_L4MP_ACPIDMAP register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : GPIO 0 Security - gpio0 + * + * Controls whether secure or non-secure masters can access the GPIO 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_GPIO0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_GPIO0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */ +#define ALT_L3_SEC_L4MP_GPIO0_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */ +#define ALT_L3_SEC_L4MP_GPIO0_MSB 7 +/* The width in bits of the ALT_L3_SEC_L4MP_GPIO0 register field. */ +#define ALT_L3_SEC_L4MP_GPIO0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_GPIO0 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO0_SET_MSK 0x00000080 +/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO0 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO0_CLR_MSK 0xffffff7f +/* The reset value of the ALT_L3_SEC_L4MP_GPIO0 register field. */ +#define ALT_L3_SEC_L4MP_GPIO0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_GPIO0 field value from a register. */ +#define ALT_L3_SEC_L4MP_GPIO0_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_L3_SEC_L4MP_GPIO0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_GPIO0_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : GPIO 1 Security - gpio1 + * + * Controls whether secure or non-secure masters can access the GPIO 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_GPIO1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_GPIO1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */ +#define ALT_L3_SEC_L4MP_GPIO1_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */ +#define ALT_L3_SEC_L4MP_GPIO1_MSB 8 +/* The width in bits of the ALT_L3_SEC_L4MP_GPIO1 register field. */ +#define ALT_L3_SEC_L4MP_GPIO1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_GPIO1 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO1_SET_MSK 0x00000100 +/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO1 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO1_CLR_MSK 0xfffffeff +/* The reset value of the ALT_L3_SEC_L4MP_GPIO1 register field. */ +#define ALT_L3_SEC_L4MP_GPIO1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_GPIO1 field value from a register. */ +#define ALT_L3_SEC_L4MP_GPIO1_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_L3_SEC_L4MP_GPIO1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_GPIO1_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : GPIO 2 Security - gpio2 + * + * Controls whether secure or non-secure masters can access the GPIO 2 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_GPIO2_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_GPIO2_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */ +#define ALT_L3_SEC_L4MP_GPIO2_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */ +#define ALT_L3_SEC_L4MP_GPIO2_MSB 9 +/* The width in bits of the ALT_L3_SEC_L4MP_GPIO2 register field. */ +#define ALT_L3_SEC_L4MP_GPIO2_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_GPIO2 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO2_SET_MSK 0x00000200 +/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO2 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO2_CLR_MSK 0xfffffdff +/* The reset value of the ALT_L3_SEC_L4MP_GPIO2 register field. */ +#define ALT_L3_SEC_L4MP_GPIO2_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_GPIO2 field value from a register. */ +#define ALT_L3_SEC_L4MP_GPIO2_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_L3_SEC_L4MP_GPIO2 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_GPIO2_SET(value) (((value) << 9) & 0x00000200) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4MP. + */ +struct ALT_L3_SEC_L4MP_s +{ + uint32_t fpgamgrregs : 1; /* FPGA Manager Register Security */ + uint32_t dap : 1; /* DAP Security */ + uint32_t qspiregs : 1; /* QSPI Registers Security */ + uint32_t sdmmc : 1; /* SDMMC Security */ + uint32_t emac0 : 1; /* EMAC 0 Security */ + uint32_t emac1 : 1; /* EMAC 1 Security */ + uint32_t acpidmap : 1; /* ACP ID Mapper Security */ + uint32_t gpio0 : 1; /* GPIO 0 Security */ + uint32_t gpio1 : 1; /* GPIO 1 Security */ + uint32_t gpio2 : 1; /* GPIO 2 Security */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4MP. */ +typedef volatile struct ALT_L3_SEC_L4MP_s ALT_L3_SEC_L4MP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4MP register from the beginning of the component. */ +#define ALT_L3_SEC_L4MP_OFST 0x8 + +/* + * Register : L4 OSC1 Peripherals Security - l4osc1 + * + * Controls security settings for L4 OSC1 peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | W | 0x0 | L4 Watchdog Timer 0 Security + * [1] | W | 0x0 | L4 Watchdog Timer 0 Security + * [2] | W | 0x0 | Clock Manager Security + * [3] | W | 0x0 | Reset Manager Security + * [4] | W | 0x0 | System Manager Security + * [5] | W | 0x0 | OSC1 Timer 0 Security + * [6] | W | 0x0 | OSC1 Timer 1 Security + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : L4 Watchdog Timer 0 Security - l4wd0 + * + * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0 + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_L4WD0 field value from a register. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4OSC1_L4WD0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : L4 Watchdog Timer 0 Security - l4wd1 + * + * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0 + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_L4WD1 field value from a register. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4OSC1_L4WD1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Clock Manager Security - clkmgr + * + * Controls whether secure or non-secure masters can access the Clock Manager + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_CLKMGR field value from a register. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4OSC1_CLKMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Reset Manager Security - rstmgr + * + * Controls whether secure or non-secure masters can access the Reset Manager + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_MSB 3 +/* The width in bits of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_RSTMGR field value from a register. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_SEC_L4OSC1_RSTMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : System Manager Security - sysmgr + * + * Controls whether secure or non-secure masters can access the System Manager + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_MSB 4 +/* The width in bits of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_CLR_MSK 0xffffffef +/* The reset value of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_SYSMGR field value from a register. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L3_SEC_L4OSC1_SYSMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : OSC1 Timer 0 Security - osc1timer0 + * + * Controls whether secure or non-secure masters can access the OSC1 Timer 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_MSB 5 +/* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET_MSK 0x00000020 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_CLR_MSK 0xffffffdf +/* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR0 field value from a register. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : OSC1 Timer 1 Security - osc1timer1 + * + * Controls whether secure or non-secure masters can access the OSC1 Timer 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_MSB 6 +/* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET_MSK 0x00000040 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_CLR_MSK 0xffffffbf +/* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR1 field value from a register. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4OSC1. + */ +struct ALT_L3_SEC_L4OSC1_s +{ + uint32_t l4wd0 : 1; /* L4 Watchdog Timer 0 Security */ + uint32_t l4wd1 : 1; /* L4 Watchdog Timer 0 Security */ + uint32_t clkmgr : 1; /* Clock Manager Security */ + uint32_t rstmgr : 1; /* Reset Manager Security */ + uint32_t sysmgr : 1; /* System Manager Security */ + uint32_t osc1timer0 : 1; /* OSC1 Timer 0 Security */ + uint32_t osc1timer1 : 1; /* OSC1 Timer 1 Security */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4OSC1. */ +typedef volatile struct ALT_L3_SEC_L4OSC1_s ALT_L3_SEC_L4OSC1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4OSC1 register from the beginning of the component. */ +#define ALT_L3_SEC_L4OSC1_OFST 0xc + +/* + * Register : L4 SPIM Peripherals Security - l4spim + * + * Controls security settings for L4 SPIM peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | W | 0x0 | SPI Master 0 Security + * [1] | W | 0x0 | SPI Master 1 Security + * [2] | W | 0x0 | Scan Manager Security + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SPI Master 0 Security - spim0 + * + * Controls whether secure or non-secure masters can access the SPI Master 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SPIM_SPIM0 field value from a register. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4SPIM_SPIM0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SPI Master 1 Security - spim1 + * + * Controls whether secure or non-secure masters can access the SPI Master 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SPIM_SPIM1 field value from a register. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4SPIM_SPIM1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Scan Manager Security - scanmgr + * + * Controls whether secure or non-secure masters can access the Scan Manager slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SPIM_SCANMGR field value from a register. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4SPIM_SCANMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4SPIM. + */ +struct ALT_L3_SEC_L4SPIM_s +{ + uint32_t spim0 : 1; /* SPI Master 0 Security */ + uint32_t spim1 : 1; /* SPI Master 1 Security */ + uint32_t scanmgr : 1; /* Scan Manager Security */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4SPIM. */ +typedef volatile struct ALT_L3_SEC_L4SPIM_s ALT_L3_SEC_L4SPIM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4SPIM register from the beginning of the component. */ +#define ALT_L3_SEC_L4SPIM_OFST 0x10 + +/* + * Register : STM Peripheral Security - stm + * + * Controls security settings for STM peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | W | 0x0 | STM Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : STM Security - s + * + * Controls whether secure or non-secure masters can access the STM slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_STM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_STM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_STM_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_STM_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_STM_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_STM_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_STM_S register field. */ +#define ALT_L3_SEC_STM_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_STM_S register field. */ +#define ALT_L3_SEC_STM_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_STM_S register field. */ +#define ALT_L3_SEC_STM_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_STM_S register field value. */ +#define ALT_L3_SEC_STM_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_STM_S register field value. */ +#define ALT_L3_SEC_STM_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_STM_S register field. */ +#define ALT_L3_SEC_STM_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_STM_S field value from a register. */ +#define ALT_L3_SEC_STM_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_STM_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_STM_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_STM. + */ +struct ALT_L3_SEC_STM_s +{ + uint32_t s : 1; /* STM Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_STM. */ +typedef volatile struct ALT_L3_SEC_STM_s ALT_L3_SEC_STM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_STM register from the beginning of the component. */ +#define ALT_L3_SEC_STM_OFST 0x14 + +/* + * Register : LWHPS2FPGA AXI Bridge Registers Peripheral Security - lwhps2fpgaregs + * + * Controls security settings for LWHPS2FPGA AXI Bridge Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [0] | W | 0x0 | LWHPS2FPGA AXI Bridge Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : LWHPS2FPGA AXI Bridge Registers Security - s + * + * Controls whether secure or non-secure masters can access the LWHPS2FPGA AXI + * Bridge Registers slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_LWH2F_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_LWH2F_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_LWH2F_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_LWH2F_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_LWH2F_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_LWH2F_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_LWH2F_S register field. */ +#define ALT_L3_SEC_LWH2F_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_LWH2F_S register field. */ +#define ALT_L3_SEC_LWH2F_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_LWH2F_S register field. */ +#define ALT_L3_SEC_LWH2F_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_LWH2F_S register field value. */ +#define ALT_L3_SEC_LWH2F_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_LWH2F_S register field value. */ +#define ALT_L3_SEC_LWH2F_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_LWH2F_S register field. */ +#define ALT_L3_SEC_LWH2F_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_LWH2F_S field value from a register. */ +#define ALT_L3_SEC_LWH2F_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_LWH2F_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_LWH2F_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_LWH2F. + */ +struct ALT_L3_SEC_LWH2F_s +{ + uint32_t s : 1; /* LWHPS2FPGA AXI Bridge Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_LWH2F. */ +typedef volatile struct ALT_L3_SEC_LWH2F_s ALT_L3_SEC_LWH2F_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_LWH2F register from the beginning of the component. */ +#define ALT_L3_SEC_LWH2F_OFST 0x18 + +/* + * Register : USB1 Registers Peripheral Security - usb1 + * + * Controls security settings for USB1 Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | W | 0x0 | USB1 Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB1 Registers Security - s + * + * Controls whether secure or non-secure masters can access the USB1 Registers + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_USB1_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_USB1_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_USB1_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_USB1_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_USB1_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_USB1_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB1_S register field. */ +#define ALT_L3_SEC_USB1_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB1_S register field. */ +#define ALT_L3_SEC_USB1_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_USB1_S register field. */ +#define ALT_L3_SEC_USB1_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_USB1_S register field value. */ +#define ALT_L3_SEC_USB1_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_USB1_S register field value. */ +#define ALT_L3_SEC_USB1_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_USB1_S register field. */ +#define ALT_L3_SEC_USB1_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_USB1_S field value from a register. */ +#define ALT_L3_SEC_USB1_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_USB1_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_USB1_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_USB1. + */ +struct ALT_L3_SEC_USB1_s +{ + uint32_t s : 1; /* USB1 Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_USB1. */ +typedef volatile struct ALT_L3_SEC_USB1_s ALT_L3_SEC_USB1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_USB1 register from the beginning of the component. */ +#define ALT_L3_SEC_USB1_OFST 0x20 + +/* + * Register : NAND Flash Controller Data Peripheral Security - nanddata + * + * Controls security settings for NAND Flash Controller Data peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | W | 0x0 | NAND Flash Controller Data Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NAND Flash Controller Data Security - s + * + * Controls whether secure or non-secure masters can access the NAND Flash + * Controller Data slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_NANDDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_NANDDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_NANDDATA_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_NANDDATA_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_NANDDATA_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_NANDDATA_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NANDDATA_S register field. */ +#define ALT_L3_SEC_NANDDATA_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NANDDATA_S register field. */ +#define ALT_L3_SEC_NANDDATA_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_NANDDATA_S register field. */ +#define ALT_L3_SEC_NANDDATA_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_NANDDATA_S register field value. */ +#define ALT_L3_SEC_NANDDATA_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_NANDDATA_S register field value. */ +#define ALT_L3_SEC_NANDDATA_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_NANDDATA_S register field. */ +#define ALT_L3_SEC_NANDDATA_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_NANDDATA_S field value from a register. */ +#define ALT_L3_SEC_NANDDATA_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_NANDDATA_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_NANDDATA_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_NANDDATA. + */ +struct ALT_L3_SEC_NANDDATA_s +{ + uint32_t s : 1; /* NAND Flash Controller Data Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_NANDDATA. */ +typedef volatile struct ALT_L3_SEC_NANDDATA_s ALT_L3_SEC_NANDDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_NANDDATA register from the beginning of the component. */ +#define ALT_L3_SEC_NANDDATA_OFST 0x24 + +/* + * Register : USB0 Registers Peripheral Security - usb0 + * + * Controls security settings for USB0 Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | W | 0x0 | USB0 Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB0 Registers Security - s + * + * Controls whether secure or non-secure masters can access the USB0 Registers + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_USB0_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_USB0_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_USB0_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_USB0_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_USB0_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_USB0_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB0_S register field. */ +#define ALT_L3_SEC_USB0_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB0_S register field. */ +#define ALT_L3_SEC_USB0_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_USB0_S register field. */ +#define ALT_L3_SEC_USB0_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_USB0_S register field value. */ +#define ALT_L3_SEC_USB0_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_USB0_S register field value. */ +#define ALT_L3_SEC_USB0_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_USB0_S register field. */ +#define ALT_L3_SEC_USB0_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_USB0_S field value from a register. */ +#define ALT_L3_SEC_USB0_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_USB0_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_USB0_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_USB0. + */ +struct ALT_L3_SEC_USB0_s +{ + uint32_t s : 1; /* USB0 Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_USB0. */ +typedef volatile struct ALT_L3_SEC_USB0_s ALT_L3_SEC_USB0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_USB0 register from the beginning of the component. */ +#define ALT_L3_SEC_USB0_OFST 0x78 + +/* + * Register : NAND Flash Controller Registers Peripheral Security - nandregs + * + * Controls security settings for NAND Flash Controller Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [0] | W | 0x0 | NAND Flash Controller Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NAND Flash Controller Registers Security - s + * + * Controls whether secure or non-secure masters can access the NAND Flash + * Controller Registers slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_NAND_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_NAND_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_NAND_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_NAND_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_NAND_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_NAND_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NAND_S register field. */ +#define ALT_L3_SEC_NAND_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NAND_S register field. */ +#define ALT_L3_SEC_NAND_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_NAND_S register field. */ +#define ALT_L3_SEC_NAND_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_NAND_S register field value. */ +#define ALT_L3_SEC_NAND_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_NAND_S register field value. */ +#define ALT_L3_SEC_NAND_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_NAND_S register field. */ +#define ALT_L3_SEC_NAND_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_NAND_S field value from a register. */ +#define ALT_L3_SEC_NAND_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_NAND_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_NAND_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_NAND. + */ +struct ALT_L3_SEC_NAND_s +{ + uint32_t s : 1; /* NAND Flash Controller Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_NAND. */ +typedef volatile struct ALT_L3_SEC_NAND_s ALT_L3_SEC_NAND_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_NAND register from the beginning of the component. */ +#define ALT_L3_SEC_NAND_OFST 0x7c + +/* + * Register : QSPI Flash Controller Data Peripheral Security - qspidata + * + * Controls security settings for QSPI Flash Controller Data peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | W | 0x0 | QSPI Flash Controller Data Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : QSPI Flash Controller Data Security - s + * + * Controls whether secure or non-secure masters can access the QSPI Flash + * Controller Data slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_QSPIDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_QSPIDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_QSPIDATA_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_QSPIDATA_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */ +#define ALT_L3_SEC_QSPIDATA_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */ +#define ALT_L3_SEC_QSPIDATA_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_QSPIDATA_S register field. */ +#define ALT_L3_SEC_QSPIDATA_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_QSPIDATA_S register field value. */ +#define ALT_L3_SEC_QSPIDATA_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_QSPIDATA_S register field value. */ +#define ALT_L3_SEC_QSPIDATA_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_QSPIDATA_S register field. */ +#define ALT_L3_SEC_QSPIDATA_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_QSPIDATA_S field value from a register. */ +#define ALT_L3_SEC_QSPIDATA_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_QSPIDATA_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_QSPIDATA_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_QSPIDATA. + */ +struct ALT_L3_SEC_QSPIDATA_s +{ + uint32_t s : 1; /* QSPI Flash Controller Data Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_QSPIDATA. */ +typedef volatile struct ALT_L3_SEC_QSPIDATA_s ALT_L3_SEC_QSPIDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_QSPIDATA register from the beginning of the component. */ +#define ALT_L3_SEC_QSPIDATA_OFST 0x80 + +/* + * Register : FPGA Manager Data Peripheral Security - fpgamgrdata + * + * Controls security settings for FPGA Manager Data peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | W | 0x0 | FPGA Manager Data Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FPGA Manager Data Security - s + * + * Controls whether secure or non-secure masters can access the FPGA Manager Data + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_FPGAMGRDATA_S register field value. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_FPGAMGRDATA_S register field value. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_FPGAMGRDATA_S field value from a register. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_FPGAMGRDATA_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_FPGAMGRDATA. + */ +struct ALT_L3_SEC_FPGAMGRDATA_s +{ + uint32_t s : 1; /* FPGA Manager Data Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_FPGAMGRDATA. */ +typedef volatile struct ALT_L3_SEC_FPGAMGRDATA_s ALT_L3_SEC_FPGAMGRDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_FPGAMGRDATA register from the beginning of the component. */ +#define ALT_L3_SEC_FPGAMGRDATA_OFST 0x84 + +/* + * Register : HPS2FPGA AXI Bridge Registers Peripheral Security - hps2fpgaregs + * + * Controls security settings for HPS2FPGA AXI Bridge Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | W | 0x0 | HPS2FPGA AXI Bridge Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : HPS2FPGA AXI Bridge Registers Security - s + * + * Controls whether secure or non-secure masters can access the HPS2FPGA AXI Bridge + * Registers slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_H2F_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_H2F_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_H2F_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_H2F_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_H2F_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_H2F_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_H2F_S register field. */ +#define ALT_L3_SEC_H2F_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_H2F_S register field. */ +#define ALT_L3_SEC_H2F_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_H2F_S register field. */ +#define ALT_L3_SEC_H2F_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_H2F_S register field value. */ +#define ALT_L3_SEC_H2F_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_H2F_S register field value. */ +#define ALT_L3_SEC_H2F_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_H2F_S register field. */ +#define ALT_L3_SEC_H2F_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_H2F_S field value from a register. */ +#define ALT_L3_SEC_H2F_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_H2F_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_H2F_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_H2F. + */ +struct ALT_L3_SEC_H2F_s +{ + uint32_t s : 1; /* HPS2FPGA AXI Bridge Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_H2F. */ +typedef volatile struct ALT_L3_SEC_H2F_s ALT_L3_SEC_H2F_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_H2F register from the beginning of the component. */ +#define ALT_L3_SEC_H2F_OFST 0x88 + +/* + * Register : MPU ACP Peripheral Security - acp + * + * Controls security settings for MPU ACP peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | W | 0x0 | MPU ACP Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MPU ACP Security - s + * + * Controls whether secure or non-secure masters can access the MPU ACP slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_ACP_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_ACP_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_ACP_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_ACP_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_ACP_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_ACP_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ACP_S register field. */ +#define ALT_L3_SEC_ACP_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ACP_S register field. */ +#define ALT_L3_SEC_ACP_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_ACP_S register field. */ +#define ALT_L3_SEC_ACP_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_ACP_S register field value. */ +#define ALT_L3_SEC_ACP_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_ACP_S register field value. */ +#define ALT_L3_SEC_ACP_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_ACP_S register field. */ +#define ALT_L3_SEC_ACP_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_ACP_S field value from a register. */ +#define ALT_L3_SEC_ACP_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_ACP_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_ACP_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_ACP. + */ +struct ALT_L3_SEC_ACP_s +{ + uint32_t s : 1; /* MPU ACP Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_ACP. */ +typedef volatile struct ALT_L3_SEC_ACP_s ALT_L3_SEC_ACP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_ACP register from the beginning of the component. */ +#define ALT_L3_SEC_ACP_OFST 0x8c + +/* + * Register : ROM Peripheral Security - rom + * + * Controls security settings for ROM peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | W | 0x0 | ROM Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ROM Security - s + * + * Controls whether secure or non-secure masters can access the ROM slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_ROM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_ROM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_ROM_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_ROM_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_ROM_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_ROM_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ROM_S register field. */ +#define ALT_L3_SEC_ROM_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ROM_S register field. */ +#define ALT_L3_SEC_ROM_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_ROM_S register field. */ +#define ALT_L3_SEC_ROM_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_ROM_S register field value. */ +#define ALT_L3_SEC_ROM_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_ROM_S register field value. */ +#define ALT_L3_SEC_ROM_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_ROM_S register field. */ +#define ALT_L3_SEC_ROM_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_ROM_S field value from a register. */ +#define ALT_L3_SEC_ROM_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_ROM_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_ROM_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_ROM. + */ +struct ALT_L3_SEC_ROM_s +{ + uint32_t s : 1; /* ROM Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_ROM. */ +typedef volatile struct ALT_L3_SEC_ROM_s ALT_L3_SEC_ROM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_ROM register from the beginning of the component. */ +#define ALT_L3_SEC_ROM_OFST 0x90 + +/* + * Register : On-chip RAM Peripheral Security - ocram + * + * Controls security settings for On-chip RAM peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | W | 0x0 | On-chip RAM Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : On-chip RAM Security - s + * + * Controls whether secure or non-secure masters can access the On-chip RAM slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_OCRAM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_OCRAM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_OCRAM_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_OCRAM_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_OCRAM_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_OCRAM_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_OCRAM_S register field. */ +#define ALT_L3_SEC_OCRAM_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_OCRAM_S register field. */ +#define ALT_L3_SEC_OCRAM_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_OCRAM_S register field. */ +#define ALT_L3_SEC_OCRAM_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_OCRAM_S register field value. */ +#define ALT_L3_SEC_OCRAM_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_OCRAM_S register field value. */ +#define ALT_L3_SEC_OCRAM_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_OCRAM_S register field. */ +#define ALT_L3_SEC_OCRAM_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_OCRAM_S field value from a register. */ +#define ALT_L3_SEC_OCRAM_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_OCRAM_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_OCRAM_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_OCRAM. + */ +struct ALT_L3_SEC_OCRAM_s +{ + uint32_t s : 1; /* On-chip RAM Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_OCRAM. */ +typedef volatile struct ALT_L3_SEC_OCRAM_s ALT_L3_SEC_OCRAM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_OCRAM register from the beginning of the component. */ +#define ALT_L3_SEC_OCRAM_OFST 0x94 + +/* + * Register : SDRAM Data Peripheral Security - sdrdata + * + * Controls security settings for SDRAM Data peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [0] | W | 0x0 | SDRAM Data Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDRAM Data Security - s + * + * Controls whether secure or non-secure masters can access the SDRAM Data slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_SDRDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_SDRDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_SDRDATA_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_SDRDATA_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_SDRDATA_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_SDRDATA_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_SDRDATA_S register field. */ +#define ALT_L3_SEC_SDRDATA_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_SDRDATA_S register field. */ +#define ALT_L3_SEC_SDRDATA_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_SDRDATA_S register field. */ +#define ALT_L3_SEC_SDRDATA_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_SDRDATA_S register field value. */ +#define ALT_L3_SEC_SDRDATA_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_SDRDATA_S register field value. */ +#define ALT_L3_SEC_SDRDATA_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_SDRDATA_S register field. */ +#define ALT_L3_SEC_SDRDATA_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_SDRDATA_S field value from a register. */ +#define ALT_L3_SEC_SDRDATA_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_SDRDATA_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_SDRDATA_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_SDRDATA. + */ +struct ALT_L3_SEC_SDRDATA_s +{ + uint32_t s : 1; /* SDRAM Data Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_SDRDATA. */ +typedef volatile struct ALT_L3_SEC_SDRDATA_s ALT_L3_SEC_SDRDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_SDRDATA register from the beginning of the component. */ +#define ALT_L3_SEC_SDRDATA_OFST 0x98 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SECGRP. + */ +struct ALT_L3_SECGRP_s +{ + volatile ALT_L3_SEC_L4MAIN_t l4main; /* ALT_L3_SEC_L4MAIN */ + volatile ALT_L3_SEC_L4SP_t l4sp; /* ALT_L3_SEC_L4SP */ + volatile ALT_L3_SEC_L4MP_t l4mp; /* ALT_L3_SEC_L4MP */ + volatile ALT_L3_SEC_L4OSC1_t l4osc1; /* ALT_L3_SEC_L4OSC1 */ + volatile ALT_L3_SEC_L4SPIM_t l4spim; /* ALT_L3_SEC_L4SPIM */ + volatile ALT_L3_SEC_STM_t stm; /* ALT_L3_SEC_STM */ + volatile ALT_L3_SEC_LWH2F_t lwhps2fpgaregs; /* ALT_L3_SEC_LWH2F */ + volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */ + volatile ALT_L3_SEC_USB1_t usb1; /* ALT_L3_SEC_USB1 */ + volatile ALT_L3_SEC_NANDDATA_t nanddata; /* ALT_L3_SEC_NANDDATA */ + volatile uint32_t _pad_0x28_0x77[20]; /* *UNDEFINED* */ + volatile ALT_L3_SEC_USB0_t usb0; /* ALT_L3_SEC_USB0 */ + volatile ALT_L3_SEC_NAND_t nandregs; /* ALT_L3_SEC_NAND */ + volatile ALT_L3_SEC_QSPIDATA_t qspidata; /* ALT_L3_SEC_QSPIDATA */ + volatile ALT_L3_SEC_FPGAMGRDATA_t fpgamgrdata; /* ALT_L3_SEC_FPGAMGRDATA */ + volatile ALT_L3_SEC_H2F_t hps2fpgaregs; /* ALT_L3_SEC_H2F */ + volatile ALT_L3_SEC_ACP_t acp; /* ALT_L3_SEC_ACP */ + volatile ALT_L3_SEC_ROM_t rom; /* ALT_L3_SEC_ROM */ + volatile ALT_L3_SEC_OCRAM_t ocram; /* ALT_L3_SEC_OCRAM */ + volatile ALT_L3_SEC_SDRDATA_t sdrdata; /* ALT_L3_SEC_SDRDATA */ +}; + +/* The typedef declaration for register group ALT_L3_SECGRP. */ +typedef volatile struct ALT_L3_SECGRP_s ALT_L3_SECGRP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SECGRP. */ +struct ALT_L3_SECGRP_raw_s +{ + volatile uint32_t l4main; /* ALT_L3_SEC_L4MAIN */ + volatile uint32_t l4sp; /* ALT_L3_SEC_L4SP */ + volatile uint32_t l4mp; /* ALT_L3_SEC_L4MP */ + volatile uint32_t l4osc1; /* ALT_L3_SEC_L4OSC1 */ + volatile uint32_t l4spim; /* ALT_L3_SEC_L4SPIM */ + volatile uint32_t stm; /* ALT_L3_SEC_STM */ + volatile uint32_t lwhps2fpgaregs; /* ALT_L3_SEC_LWH2F */ + volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */ + volatile uint32_t usb1; /* ALT_L3_SEC_USB1 */ + volatile uint32_t nanddata; /* ALT_L3_SEC_NANDDATA */ + volatile uint32_t _pad_0x28_0x77[20]; /* *UNDEFINED* */ + volatile uint32_t usb0; /* ALT_L3_SEC_USB0 */ + volatile uint32_t nandregs; /* ALT_L3_SEC_NAND */ + volatile uint32_t qspidata; /* ALT_L3_SEC_QSPIDATA */ + volatile uint32_t fpgamgrdata; /* ALT_L3_SEC_FPGAMGRDATA */ + volatile uint32_t hps2fpgaregs; /* ALT_L3_SEC_H2F */ + volatile uint32_t acp; /* ALT_L3_SEC_ACP */ + volatile uint32_t rom; /* ALT_L3_SEC_ROM */ + volatile uint32_t ocram; /* ALT_L3_SEC_OCRAM */ + volatile uint32_t sdrdata; /* ALT_L3_SEC_SDRDATA */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SECGRP. */ +typedef volatile struct ALT_L3_SECGRP_raw_s ALT_L3_SECGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ID Register Group - ALT_L3_IDGRP + * ID Register Group + * + * Contains registers that identify the ARM NIC-301 IP Core. + * + */ +/* + * Register : Peripheral ID4 Register - periph_id_4 + * + * JEP106 continuation code + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [7:0] | R | 0x4 | Peripheral ID4 + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Peripheral ID4 - periph_id_4 + * + * JEP106 continuation code + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH 8 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_RESET 0x4 +/* Extracts the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_4. + */ +struct ALT_L3_ID_PERIPH_ID_4_s +{ + const uint32_t periph_id_4 : 8; /* Peripheral ID4 */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_4. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_4_s ALT_L3_ID_PERIPH_ID_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_4 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_4_OFST 0xfd0 + +/* + * Register : Peripheral ID0 Register - periph_id_0 + * + * Peripheral ID0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [7:0] | R | 0x1 | Part Number [7:0] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Part Number [7:0] - pn7to0 + * + * Part Number [7:0] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_WIDTH 8 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_RESET 0x1 +/* Extracts the ALT_L3_ID_PERIPH_ID_0_PN7TO0 field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_0. + */ +struct ALT_L3_ID_PERIPH_ID_0_s +{ + const uint32_t pn7to0 : 8; /* Part Number [7:0] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_0. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_0_s ALT_L3_ID_PERIPH_ID_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_0 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_0_OFST 0xfe0 + +/* + * Register : Peripheral ID1 Register - periph_id_1 + * + * Peripheral ID1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [7:0] | R | 0xb3 | JEP106[3:0], Part Number [11:8] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : JEP106[3:0], Part Number [11:8] - jep3to0_pn11to8 + * + * JEP106[3:0], Part Number [11:8] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH 8 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET 0xb3 +/* Extracts the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_1. + */ +struct ALT_L3_ID_PERIPH_ID_1_s +{ + const uint32_t jep3to0_pn11to8 : 8; /* JEP106[3:0], Part Number [11:8] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_1. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_1_s ALT_L3_ID_PERIPH_ID_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_1 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_1_OFST 0xfe4 + +/* + * Register : Peripheral ID2 Register - periph_id_2 + * + * Peripheral ID2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [7:0] | R | 0x6b | Revision, JEP106 code flag, JEP106[6:4] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Revision, JEP106 code flag, JEP106[6:4] - rev_jepcode_jep6to4 + * + * Revision, JEP106 code flag, JEP106[6:4] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH 8 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET 0x6b +/* Extracts the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_2. + */ +struct ALT_L3_ID_PERIPH_ID_2_s +{ + const uint32_t rev_jepcode_jep6to4 : 8; /* Revision, JEP106 code flag, JEP106[6:4] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_2. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_2_s ALT_L3_ID_PERIPH_ID_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_2 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_2_OFST 0xfe8 + +/* + * Register : Peripheral ID3 Register - periph_id_3 + * + * Peripheral ID3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [3:0] | R | 0x0 | Customer Model Number + * [7:4] | R | 0x0 | Revision + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Customer Model Number - cust_mod_num + * + * Customer Model Number + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB 3 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH 4 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET 0x0 +/* Extracts the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Revision - rev_and + * + * Revision + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_WIDTH 4 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_CLR_MSK 0xffffff0f +/* The reset value of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_RESET 0x0 +/* Extracts the ALT_L3_ID_PERIPH_ID_3_REV_AND field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_L3_ID_PERIPH_ID_3_REV_AND register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_3. + */ +struct ALT_L3_ID_PERIPH_ID_3_s +{ + const uint32_t cust_mod_num : 4; /* Customer Model Number */ + const uint32_t rev_and : 4; /* Revision */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_3. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_3_s ALT_L3_ID_PERIPH_ID_3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_3 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_3_OFST 0xfec + +/* + * Register : Component ID0 Register - comp_id_0 + * + * Component ID0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0xd | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_MSB 7 +/* The width in bits of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_RESET 0xd +/* Extracts the ALT_L3_ID_COMP_ID_0_PREAMBLE field value from a register. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_COMP_ID_0_PREAMBLE register field value suitable for setting the register. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_COMP_ID_0. + */ +struct ALT_L3_ID_COMP_ID_0_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_COMP_ID_0. */ +typedef volatile struct ALT_L3_ID_COMP_ID_0_s ALT_L3_ID_COMP_ID_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_COMP_ID_0 register from the beginning of the component. */ +#define ALT_L3_ID_COMP_ID_0_OFST 0xff0 + +/* + * Register : Component ID1 Register - comp_id_1 + * + * Component ID1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------- + * [7:0] | R | 0xf0 | Generic IP component class, Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Generic IP component class, Preamble - genipcompcls_preamble + * + * Generic IP component class, Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB 7 +/* The width in bits of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET 0xf0 +/* Extracts the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE field value from a register. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value suitable for setting the register. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_COMP_ID_1. + */ +struct ALT_L3_ID_COMP_ID_1_s +{ + const uint32_t genipcompcls_preamble : 8; /* Generic IP component class, Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_COMP_ID_1. */ +typedef volatile struct ALT_L3_ID_COMP_ID_1_s ALT_L3_ID_COMP_ID_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_COMP_ID_1 register from the beginning of the component. */ +#define ALT_L3_ID_COMP_ID_1_OFST 0xff4 + +/* + * Register : Component ID2 Register - comp_id_2 + * + * Component ID2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0x5 | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_MSB 7 +/* The width in bits of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_RESET 0x5 +/* Extracts the ALT_L3_ID_COMP_ID_2_PREAMBLE field value from a register. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_COMP_ID_2_PREAMBLE register field value suitable for setting the register. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_COMP_ID_2. + */ +struct ALT_L3_ID_COMP_ID_2_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_COMP_ID_2. */ +typedef volatile struct ALT_L3_ID_COMP_ID_2_s ALT_L3_ID_COMP_ID_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_COMP_ID_2 register from the beginning of the component. */ +#define ALT_L3_ID_COMP_ID_2_OFST 0xff8 + +/* + * Register : Component ID3 Register - comp_id_3 + * + * Component ID3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0xb1 | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_MSB 7 +/* The width in bits of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_RESET 0xb1 +/* Extracts the ALT_L3_ID_COMP_ID_3_PREAMBLE field value from a register. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_COMP_ID_3_PREAMBLE register field value suitable for setting the register. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_COMP_ID_3. + */ +struct ALT_L3_ID_COMP_ID_3_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_COMP_ID_3. */ +typedef volatile struct ALT_L3_ID_COMP_ID_3_s ALT_L3_ID_COMP_ID_3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_COMP_ID_3 register from the beginning of the component. */ +#define ALT_L3_ID_COMP_ID_3_OFST 0xffc + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_IDGRP. + */ +struct ALT_L3_IDGRP_s +{ + volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ + volatile ALT_L3_ID_PERIPH_ID_4_t periph_id_4; /* ALT_L3_ID_PERIPH_ID_4 */ + volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ + volatile ALT_L3_ID_PERIPH_ID_0_t periph_id_0; /* ALT_L3_ID_PERIPH_ID_0 */ + volatile ALT_L3_ID_PERIPH_ID_1_t periph_id_1; /* ALT_L3_ID_PERIPH_ID_1 */ + volatile ALT_L3_ID_PERIPH_ID_2_t periph_id_2; /* ALT_L3_ID_PERIPH_ID_2 */ + volatile ALT_L3_ID_PERIPH_ID_3_t periph_id_3; /* ALT_L3_ID_PERIPH_ID_3 */ + volatile ALT_L3_ID_COMP_ID_0_t comp_id_0; /* ALT_L3_ID_COMP_ID_0 */ + volatile ALT_L3_ID_COMP_ID_1_t comp_id_1; /* ALT_L3_ID_COMP_ID_1 */ + volatile ALT_L3_ID_COMP_ID_2_t comp_id_2; /* ALT_L3_ID_COMP_ID_2 */ + volatile ALT_L3_ID_COMP_ID_3_t comp_id_3; /* ALT_L3_ID_COMP_ID_3 */ +}; + +/* The typedef declaration for register group ALT_L3_IDGRP. */ +typedef volatile struct ALT_L3_IDGRP_s ALT_L3_IDGRP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_IDGRP. */ +struct ALT_L3_IDGRP_raw_s +{ + volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ + volatile uint32_t periph_id_4; /* ALT_L3_ID_PERIPH_ID_4 */ + volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ + volatile uint32_t periph_id_0; /* ALT_L3_ID_PERIPH_ID_0 */ + volatile uint32_t periph_id_1; /* ALT_L3_ID_PERIPH_ID_1 */ + volatile uint32_t periph_id_2; /* ALT_L3_ID_PERIPH_ID_2 */ + volatile uint32_t periph_id_3; /* ALT_L3_ID_PERIPH_ID_3 */ + volatile uint32_t comp_id_0; /* ALT_L3_ID_COMP_ID_0 */ + volatile uint32_t comp_id_1; /* ALT_L3_ID_COMP_ID_1 */ + volatile uint32_t comp_id_2; /* ALT_L3_ID_COMP_ID_2 */ + volatile uint32_t comp_id_3; /* ALT_L3_ID_COMP_ID_3 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_IDGRP. */ +typedef volatile struct ALT_L3_IDGRP_raw_s ALT_L3_IDGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Master Register Group - ALT_L3_MSTGRP + * Master Register Group + * + * Registers associated with master interfaces in the L3 Interconnect. Note that a + * master in the L3 Interconnect connects to a slave in a module. + * + */ +/* + * Register Group : L4 MAIN - ALT_L3_MST_L4MAIN + * L4 MAIN + * + * Registers associated with the L4 MAIN master. This master is used to access the + * APB slaves on the L4 MAIN bus. + * + */ +/* + * Register : Bus Matrix Issuing Functionality Modification Register - fn_mod_bm_iss + * + * Sets the issuing capability of the preceding switch arbitration scheme to + * multiple or single outstanding transactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | ALT_L3_FN_MOD_BM_ISS_RD + * [1] | RW | 0x0 | ALT_L3_FN_MOD_BM_ISS_WR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : rd + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------------- + * ALT_L3_FN_MOD_BM_ISS_RD_E_MULT | 0x0 | Multiple outstanding read transactions + * ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD + * + * Multiple outstanding read transactions + */ +#define ALT_L3_FN_MOD_BM_ISS_RD_E_MULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD + * + * Only a single outstanding read transaction + */ +#define ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_MSB 0 +/* The width in bits of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_BM_ISS_RD register field value. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_RD register field value. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_BM_ISS_RD field value from a register. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_FN_MOD_BM_ISS_RD register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : wr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------------------------------------- + * ALT_L3_FN_MOD_BM_ISS_WR_E_MULT | 0x0 | Multiple outstanding write transactions + * ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR + * + * Multiple outstanding write transactions + */ +#define ALT_L3_FN_MOD_BM_ISS_WR_E_MULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR + * + * Only a single outstanding write transaction + */ +#define ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_MSB 1 +/* The width in bits of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_BM_ISS_WR register field value. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_WR register field value. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_BM_ISS_WR field value from a register. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_FN_MOD_BM_ISS_WR register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_FN_MOD_BM_ISS. + */ +struct ALT_L3_FN_MOD_BM_ISS_s +{ + uint32_t rd : 1; /* ALT_L3_FN_MOD_BM_ISS_RD */ + uint32_t wr : 1; /* ALT_L3_FN_MOD_BM_ISS_WR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_FN_MOD_BM_ISS. */ +typedef volatile struct ALT_L3_FN_MOD_BM_ISS_s ALT_L3_FN_MOD_BM_ISS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_FN_MOD_BM_ISS register from the beginning of the component. */ +#define ALT_L3_FN_MOD_BM_ISS_OFST 0x8 +/* The address of the ALT_L3_FN_MOD_BM_ISS register. */ +#define ALT_L3_FN_MOD_BM_ISS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_BM_ISS_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4MAIN. + */ +struct ALT_L3_MST_L4MAIN_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4MAIN. */ +typedef volatile struct ALT_L3_MST_L4MAIN_s ALT_L3_MST_L4MAIN_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */ +struct ALT_L3_MST_L4MAIN_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */ +typedef volatile struct ALT_L3_MST_L4MAIN_raw_s ALT_L3_MST_L4MAIN_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : L4 SP - ALT_L3_MST_L4SP + * L4 SP + * + * Registers associated with the L4 SP master. This master is used to access the + * APB slaves on the L4 SP bus. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4SP. + */ +struct ALT_L3_MST_L4SP_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4SP. */ +typedef volatile struct ALT_L3_MST_L4SP_s ALT_L3_MST_L4SP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SP. */ +struct ALT_L3_MST_L4SP_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SP. */ +typedef volatile struct ALT_L3_MST_L4SP_raw_s ALT_L3_MST_L4SP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : L4 MP - ALT_L3_MST_L4MP + * L4 MP + * + * Registers associated with the L4 MP master. This master is used to access the + * APB slaves on the L4 MP bus. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4MP. + */ +struct ALT_L3_MST_L4MP_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4MP. */ +typedef volatile struct ALT_L3_MST_L4MP_s ALT_L3_MST_L4MP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MP. */ +struct ALT_L3_MST_L4MP_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MP. */ +typedef volatile struct ALT_L3_MST_L4MP_raw_s ALT_L3_MST_L4MP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : L4 OSC1 - ALT_L3_MST_L4OSC1 + * L4 OSC1 + * + * Registers associated with the L4 OSC1 master. This master is used to access the + * APB slaves on the L4 OSC1 bus. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4OSC1. + */ +struct ALT_L3_MST_L4OSC1_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4OSC1. */ +typedef volatile struct ALT_L3_MST_L4OSC1_s ALT_L3_MST_L4OSC1_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */ +struct ALT_L3_MST_L4OSC1_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */ +typedef volatile struct ALT_L3_MST_L4OSC1_raw_s ALT_L3_MST_L4OSC1_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : L4 SPIM - ALT_L3_MST_L4SPIM + * L4 SPIM + * + * Registers associated with the L4 SPIM master. This master is used to access the + * APB slaves on the L4 SPIM bus. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4SPIM. + */ +struct ALT_L3_MST_L4SPIM_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4SPIM. */ +typedef volatile struct ALT_L3_MST_L4SPIM_s ALT_L3_MST_L4SPIM_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */ +struct ALT_L3_MST_L4SPIM_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */ +typedef volatile struct ALT_L3_MST_L4SPIM_raw_s ALT_L3_MST_L4SPIM_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : STM - ALT_L3_MST_STM + * STM + * + * Registers associated with the STM master. This master is used to access the STM + * AXI slave. + * + */ +/* + * Register : Issuing Functionality Modification Register - fn_mod + * + * Sets the block issuing capability to multiple or single outstanding + * transactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x0 | ALT_L3_FN_MOD_RD + * [1] | RW | 0x0 | ALT_L3_FN_MOD_WR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : rd + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------------------------- + * ALT_L3_FN_MOD_RD_E_MULT | 0x0 | Multiple outstanding read transactions + * ALT_L3_FN_MOD_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_RD + * + * Multiple outstanding read transactions + */ +#define ALT_L3_FN_MOD_RD_E_MULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_RD + * + * Only a single outstanding read transaction + */ +#define ALT_L3_FN_MOD_RD_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_RD register field. */ +#define ALT_L3_FN_MOD_RD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_RD register field. */ +#define ALT_L3_FN_MOD_RD_MSB 0 +/* The width in bits of the ALT_L3_FN_MOD_RD register field. */ +#define ALT_L3_FN_MOD_RD_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_RD register field value. */ +#define ALT_L3_FN_MOD_RD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_FN_MOD_RD register field value. */ +#define ALT_L3_FN_MOD_RD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_FN_MOD_RD register field. */ +#define ALT_L3_FN_MOD_RD_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_RD field value from a register. */ +#define ALT_L3_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_FN_MOD_RD register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : wr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:-------------------------------------------- + * ALT_L3_FN_MOD_WR_E_MULT | 0x0 | Multiple outstanding write transactions + * ALT_L3_FN_MOD_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_WR + * + * Multiple outstanding write transactions + */ +#define ALT_L3_FN_MOD_WR_E_MULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_WR + * + * Only a single outstanding write transaction + */ +#define ALT_L3_FN_MOD_WR_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_WR register field. */ +#define ALT_L3_FN_MOD_WR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_WR register field. */ +#define ALT_L3_FN_MOD_WR_MSB 1 +/* The width in bits of the ALT_L3_FN_MOD_WR register field. */ +#define ALT_L3_FN_MOD_WR_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_WR register field value. */ +#define ALT_L3_FN_MOD_WR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_FN_MOD_WR register field value. */ +#define ALT_L3_FN_MOD_WR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_FN_MOD_WR register field. */ +#define ALT_L3_FN_MOD_WR_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_WR field value from a register. */ +#define ALT_L3_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_FN_MOD_WR register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_FN_MOD. + */ +struct ALT_L3_FN_MOD_s +{ + uint32_t rd : 1; /* ALT_L3_FN_MOD_RD */ + uint32_t wr : 1; /* ALT_L3_FN_MOD_WR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_FN_MOD. */ +typedef volatile struct ALT_L3_FN_MOD_s ALT_L3_FN_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_FN_MOD register from the beginning of the component. */ +#define ALT_L3_FN_MOD_OFST 0x108 +/* The address of the ALT_L3_FN_MOD register. */ +#define ALT_L3_FN_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_STM. + */ +struct ALT_L3_MST_STM_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_STM. */ +typedef volatile struct ALT_L3_MST_STM_s ALT_L3_MST_STM_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_STM. */ +struct ALT_L3_MST_STM_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_STM. */ +typedef volatile struct ALT_L3_MST_STM_raw_s ALT_L3_MST_STM_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : LWHPS2FPGA - ALT_L3_MST_LWH2F + * LWHPS2FPGA + * + * Registers associated with the LWHPS2FPGA AXI Bridge master. This master is used + * to access the LWHPS2FPGA AXI Bridge slave. This slave is used to access the + * registers for all 3 AXI bridges and to access slaves in the FPGA connected to + * the LWHPS2FPGA AXI Bridge. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_LWH2F. + */ +struct ALT_L3_MST_LWH2F_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_LWH2F. */ +typedef volatile struct ALT_L3_MST_LWH2F_s ALT_L3_MST_LWH2F_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */ +struct ALT_L3_MST_LWH2F_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */ +typedef volatile struct ALT_L3_MST_LWH2F_raw_s ALT_L3_MST_LWH2F_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB1 - ALT_L3_MST_USB1 + * USB1 + * + * Registers associated with the USB1 master. This master is used to access the + * registers in USB1. + * + */ +/* + * Register : AHB Control Register - ahb_cntl + * + * Sets the block issuing capability to one outstanding transaction. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | ALT_L3_AHB_CNTL_DECERR_EN + * [1] | RW | 0x0 | ALT_L3_AHB_CNTL_FORCE_INCR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : decerr_en + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------- + * ALT_L3_AHB_CNTL_DECERR_EN_E_DIS | 0x0 | No DECERR response. + * ALT_L3_AHB_CNTL_DECERR_EN_E_EN | 0x1 | If the AHB protocol conversion function receives + * : | | an unaligned address or a write data beat + * : | | without all the byte strobes set, creates a + * : | | DECERR response. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN + * + * No DECERR response. + */ +#define ALT_L3_AHB_CNTL_DECERR_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN + * + * If the AHB protocol conversion function receives an unaligned address or a write + * data beat without all the byte strobes set, creates a DECERR response. + */ +#define ALT_L3_AHB_CNTL_DECERR_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_MSB 0 +/* The width in bits of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_WIDTH 1 +/* The mask used to set the ALT_L3_AHB_CNTL_DECERR_EN register field value. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_AHB_CNTL_DECERR_EN register field value. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_RESET 0x0 +/* Extracts the ALT_L3_AHB_CNTL_DECERR_EN field value from a register. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_AHB_CNTL_DECERR_EN register field value suitable for setting the register. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : force_incr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------------------- + * ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS | 0x0 | Multiple outstanding write transactions + * ALT_L3_AHB_CNTL_FORCE_INCR_E_EN | 0x1 | If a beat is received that has no write data + * : | | strobes set, that write data beat is replaced + * : | | with an IDLE beat. Also, causes all transactions + * : | | that are to be output to the AHB domain to be an + * : | | undefined length INCR. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR + * + * Multiple outstanding write transactions + */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS 0x0 +/* + * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR + * + * If a beat is received that has no write data strobes set, that write data beat + * is replaced with an IDLE beat. Also, causes all transactions that are to be + * output to the AHB domain to be an undefined length INCR. + */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_MSB 1 +/* The width in bits of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_WIDTH 1 +/* The mask used to set the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_RESET 0x0 +/* Extracts the ALT_L3_AHB_CNTL_FORCE_INCR field value from a register. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_AHB_CNTL_FORCE_INCR register field value suitable for setting the register. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_AHB_CNTL. + */ +struct ALT_L3_AHB_CNTL_s +{ + uint32_t decerr_en : 1; /* ALT_L3_AHB_CNTL_DECERR_EN */ + uint32_t force_incr : 1; /* ALT_L3_AHB_CNTL_FORCE_INCR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_AHB_CNTL. */ +typedef volatile struct ALT_L3_AHB_CNTL_s ALT_L3_AHB_CNTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_AHB_CNTL register from the beginning of the component. */ +#define ALT_L3_AHB_CNTL_OFST 0x44 +/* The address of the ALT_L3_AHB_CNTL register. */ +#define ALT_L3_AHB_CNTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_AHB_CNTL_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_USB1. + */ +struct ALT_L3_MST_USB1_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for register group ALT_L3_MST_USB1. */ +typedef volatile struct ALT_L3_MST_USB1_s ALT_L3_MST_USB1_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_USB1. */ +struct ALT_L3_MST_USB1_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB1. */ +typedef volatile struct ALT_L3_MST_USB1_raw_s ALT_L3_MST_USB1_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : NANDDATA - ALT_L3_MST_NANDDATA + * NANDDATA + * + * Registers associated with the NANDDATA master. This master is used to access + * data in the NAND flash controller. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_NANDDATA. + */ +struct ALT_L3_MST_NANDDATA_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_NANDDATA. */ +typedef volatile struct ALT_L3_MST_NANDDATA_s ALT_L3_MST_NANDDATA_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */ +struct ALT_L3_MST_NANDDATA_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */ +typedef volatile struct ALT_L3_MST_NANDDATA_raw_s ALT_L3_MST_NANDDATA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB0 - ALT_L3_MST_USB0 + * USB0 + * + * Registers associated with the USB0 master. This master is used to access the + * registers in USB0. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_USB0. + */ +struct ALT_L3_MST_USB0_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for register group ALT_L3_MST_USB0. */ +typedef volatile struct ALT_L3_MST_USB0_s ALT_L3_MST_USB0_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_USB0. */ +struct ALT_L3_MST_USB0_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB0. */ +typedef volatile struct ALT_L3_MST_USB0_raw_s ALT_L3_MST_USB0_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : NANDREGS - ALT_L3_MST_NAND + * NANDREGS + * + * Registers associated with the NANDREGS master. This master is used to access the + * registers in the NAND flash controller. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_NAND. + */ +struct ALT_L3_MST_NAND_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_NAND. */ +typedef volatile struct ALT_L3_MST_NAND_s ALT_L3_MST_NAND_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_NAND. */ +struct ALT_L3_MST_NAND_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_NAND. */ +typedef volatile struct ALT_L3_MST_NAND_raw_s ALT_L3_MST_NAND_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : QSPIDATA - ALT_L3_MST_QSPIDATA + * QSPIDATA + * + * Registers associated with the QSPIDATA master. This master is used to access + * data in the QSPI flash controller. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_QSPIDATA. + */ +struct ALT_L3_MST_QSPIDATA_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for register group ALT_L3_MST_QSPIDATA. */ +typedef volatile struct ALT_L3_MST_QSPIDATA_s ALT_L3_MST_QSPIDATA_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */ +struct ALT_L3_MST_QSPIDATA_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */ +typedef volatile struct ALT_L3_MST_QSPIDATA_raw_s ALT_L3_MST_QSPIDATA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : FPGAMGRDATA - ALT_L3_MST_FPGAMGRDATA + * FPGAMGRDATA + * + * Registers associated with the FPGAMGRDATA master. This master is used to send + * FPGA configuration image data to the FPGA Manager. + * + */ +/* + * Register : Write Tidemark - wr_tidemark + * + * Controls the release of the transaction in the write data FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x4 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Stalls the transaction in the write data FIFO until the number of occupied slots + * in the write data FIFO exceeds the level. Note that the transaction is released + * before this level is achieved if the network receives the WLAST beat or the + * write FIFO becomes full. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_MSB 3 +/* The width in bits of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_WIDTH 4 +/* The mask used to set the ALT_L3_WR_TIDEMARK_LEVEL register field value. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L3_WR_TIDEMARK_LEVEL register field value. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_RESET 0x4 +/* Extracts the ALT_L3_WR_TIDEMARK_LEVEL field value from a register. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L3_WR_TIDEMARK_LEVEL register field value suitable for setting the register. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_WR_TIDEMARK. + */ +struct ALT_L3_WR_TIDEMARK_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_WR_TIDEMARK. */ +typedef volatile struct ALT_L3_WR_TIDEMARK_s ALT_L3_WR_TIDEMARK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_WR_TIDEMARK register from the beginning of the component. */ +#define ALT_L3_WR_TIDEMARK_OFST 0x40 +/* The address of the ALT_L3_WR_TIDEMARK register. */ +#define ALT_L3_WR_TIDEMARK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_TIDEMARK_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_FPGAMGRDATA. + */ +struct ALT_L3_MST_FPGAMGRDATA_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_FPGAMGRDATA. */ +typedef volatile struct ALT_L3_MST_FPGAMGRDATA_s ALT_L3_MST_FPGAMGRDATA_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */ +struct ALT_L3_MST_FPGAMGRDATA_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */ +typedef volatile struct ALT_L3_MST_FPGAMGRDATA_raw_s ALT_L3_MST_FPGAMGRDATA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : HPS2FPGA - ALT_L3_MST_H2F + * HPS2FPGA + * + * Registers associated with the HPS2FPGA AXI Bridge master. This master is used to + * access the HPS2FPGA AXI Bridge slave. This slave is used to access slaves in the + * FPGA connected to the HPS2FPGA AXI Bridge. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_H2F. + */ +struct ALT_L3_MST_H2F_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_H2F. */ +typedef volatile struct ALT_L3_MST_H2F_s ALT_L3_MST_H2F_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_H2F. */ +struct ALT_L3_MST_H2F_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_H2F. */ +typedef volatile struct ALT_L3_MST_H2F_raw_s ALT_L3_MST_H2F_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ACP - ALT_L3_MST_ACP + * ACP + * + * Registers associated with the ACP master. This master is used to access the MPU + * ACP slave via the ACP ID Mapper. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_ACP. + */ +struct ALT_L3_MST_ACP_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_ACP. */ +typedef volatile struct ALT_L3_MST_ACP_s ALT_L3_MST_ACP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_ACP. */ +struct ALT_L3_MST_ACP_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_ACP. */ +typedef volatile struct ALT_L3_MST_ACP_raw_s ALT_L3_MST_ACP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Boot ROM - ALT_L3_MST_ROM + * Boot ROM + * + * Registers associated with the Boot ROM master. This master is used to access the + * contents of the Boot ROM. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_ROM. + */ +struct ALT_L3_MST_ROM_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_ROM. */ +typedef volatile struct ALT_L3_MST_ROM_s ALT_L3_MST_ROM_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_ROM. */ +struct ALT_L3_MST_ROM_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_ROM. */ +typedef volatile struct ALT_L3_MST_ROM_raw_s ALT_L3_MST_ROM_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : On-chip RAM - ALT_L3_MST_OCRAM + * On-chip RAM + * + * Registers associated with the On-chip RAM master. This master is used to access + * the contents of the On-chip RAM. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_OCRAM. + */ +struct ALT_L3_MST_OCRAM_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_OCRAM. */ +typedef volatile struct ALT_L3_MST_OCRAM_s ALT_L3_MST_OCRAM_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */ +struct ALT_L3_MST_OCRAM_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */ +typedef volatile struct ALT_L3_MST_OCRAM_raw_s ALT_L3_MST_OCRAM_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MSTGRP. + */ +struct ALT_L3_MSTGRP_s +{ + volatile ALT_L3_MST_L4MAIN_t mastergrp_l4main; /* ALT_L3_MST_L4MAIN */ + volatile uint32_t _pad_0xc_0xfff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4SP_t mastergrp_l4sp; /* ALT_L3_MST_L4SP */ + volatile uint32_t _pad_0x100c_0x1fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4MP_t mastergrp_l4mp; /* ALT_L3_MST_L4MP */ + volatile uint32_t _pad_0x200c_0x2fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4OSC1_t mastergrp_l4osc1; /* ALT_L3_MST_L4OSC1 */ + volatile uint32_t _pad_0x300c_0x3fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4SPIM_t mastergrp_l4spim; /* ALT_L3_MST_L4SPIM */ + volatile uint32_t _pad_0x400c_0x4fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_STM_t mastergrp_stm; /* ALT_L3_MST_STM */ + volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_LWH2F_t mastergrp_lwhps2fpga; /* ALT_L3_MST_LWH2F */ + volatile uint32_t _pad_0x610c_0x7fff[1981]; /* *UNDEFINED* */ + volatile ALT_L3_MST_USB1_t mastergrp_usb1; /* ALT_L3_MST_USB1 */ + volatile uint32_t _pad_0x8048_0x8fff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_NANDDATA_t mastergrp_nanddata; /* ALT_L3_MST_NANDDATA */ + volatile uint32_t _pad_0x910c_0x1dfff[21437]; /* *UNDEFINED* */ + volatile ALT_L3_MST_USB0_t mastergrp_usb0; /* ALT_L3_MST_USB0 */ + volatile uint32_t _pad_0x1e048_0x1efff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_NAND_t mastergrp_nandregs; /* ALT_L3_MST_NAND */ + volatile uint32_t _pad_0x1f10c_0x1ffff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_QSPIDATA_t mastergrp_qspidata; /* ALT_L3_MST_QSPIDATA */ + volatile uint32_t _pad_0x20048_0x20fff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_FPGAMGRDATA_t mastergrp_fpgamgrdata; /* ALT_L3_MST_FPGAMGRDATA */ + volatile uint32_t _pad_0x2110c_0x21fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_H2F_t mastergrp_hps2fpga; /* ALT_L3_MST_H2F */ + volatile uint32_t _pad_0x2210c_0x22fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_ACP_t mastergrp_acp; /* ALT_L3_MST_ACP */ + volatile uint32_t _pad_0x2310c_0x23fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_ROM_t mastergrp_rom; /* ALT_L3_MST_ROM */ + volatile uint32_t _pad_0x2410c_0x24fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_OCRAM_t mastergrp_ocram; /* ALT_L3_MST_OCRAM */ +}; + +/* The typedef declaration for register group ALT_L3_MSTGRP. */ +typedef volatile struct ALT_L3_MSTGRP_s ALT_L3_MSTGRP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MSTGRP. */ +struct ALT_L3_MSTGRP_raw_s +{ + volatile ALT_L3_MST_L4MAIN_raw_t mastergrp_l4main; /* ALT_L3_MST_L4MAIN */ + volatile uint32_t _pad_0xc_0xfff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4SP_raw_t mastergrp_l4sp; /* ALT_L3_MST_L4SP */ + volatile uint32_t _pad_0x100c_0x1fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4MP_raw_t mastergrp_l4mp; /* ALT_L3_MST_L4MP */ + volatile uint32_t _pad_0x200c_0x2fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4OSC1_raw_t mastergrp_l4osc1; /* ALT_L3_MST_L4OSC1 */ + volatile uint32_t _pad_0x300c_0x3fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4SPIM_raw_t mastergrp_l4spim; /* ALT_L3_MST_L4SPIM */ + volatile uint32_t _pad_0x400c_0x4fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_STM_raw_t mastergrp_stm; /* ALT_L3_MST_STM */ + volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_LWH2F_raw_t mastergrp_lwhps2fpga; /* ALT_L3_MST_LWH2F */ + volatile uint32_t _pad_0x610c_0x7fff[1981]; /* *UNDEFINED* */ + volatile ALT_L3_MST_USB1_raw_t mastergrp_usb1; /* ALT_L3_MST_USB1 */ + volatile uint32_t _pad_0x8048_0x8fff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_NANDDATA_raw_t mastergrp_nanddata; /* ALT_L3_MST_NANDDATA */ + volatile uint32_t _pad_0x910c_0x1dfff[21437]; /* *UNDEFINED* */ + volatile ALT_L3_MST_USB0_raw_t mastergrp_usb0; /* ALT_L3_MST_USB0 */ + volatile uint32_t _pad_0x1e048_0x1efff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_NAND_raw_t mastergrp_nandregs; /* ALT_L3_MST_NAND */ + volatile uint32_t _pad_0x1f10c_0x1ffff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_QSPIDATA_raw_t mastergrp_qspidata; /* ALT_L3_MST_QSPIDATA */ + volatile uint32_t _pad_0x20048_0x20fff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_FPGAMGRDATA_raw_t mastergrp_fpgamgrdata; /* ALT_L3_MST_FPGAMGRDATA */ + volatile uint32_t _pad_0x2110c_0x21fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_H2F_raw_t mastergrp_hps2fpga; /* ALT_L3_MST_H2F */ + volatile uint32_t _pad_0x2210c_0x22fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_ACP_raw_t mastergrp_acp; /* ALT_L3_MST_ACP */ + volatile uint32_t _pad_0x2310c_0x23fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_ROM_raw_t mastergrp_rom; /* ALT_L3_MST_ROM */ + volatile uint32_t _pad_0x2410c_0x24fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_OCRAM_raw_t mastergrp_ocram; /* ALT_L3_MST_OCRAM */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MSTGRP. */ +typedef volatile struct ALT_L3_MSTGRP_raw_s ALT_L3_MSTGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Slave Register Group - ALT_L3_SLVGRP + * Slave Register Group + * + * Registers associated with slave interfaces. + * + */ +/* + * Register Group : DAP - ALT_L3_SLV_DAP + * DAP + * + * Registers associated with the DAP slave interface. This slave is used by the DAP + * to access slaves attached to the L3/L4 Interconnect. + * + */ +/* + * Register : Functionality Modification 2 Register - fn_mod2 + * + * Controls bypass merge of upsizing/downsizing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Bypass Merge + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bypass Merge - bypass_merge + * + * Controls bypass merge of upsizing/downsizing. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------- + * ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER | 0x0 | The network can alter transactions. + * ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER | 0x1 | The network does not alter any transactions that + * : | | could pass through the upsizer legally without + * : | | alteration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE + * + * The network can alter transactions. + */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE + * + * The network does not alter any transactions that could pass through the upsizer + * legally without alteration. + */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_MSB 0 +/* The width in bits of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD2_BYPASS_MERGE field value from a register. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_FN_MOD2_BYPASS_MERGE register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_FN_MOD2. + */ +struct ALT_L3_FN_MOD2_s +{ + uint32_t bypass_merge : 1; /* Bypass Merge */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_FN_MOD2. */ +typedef volatile struct ALT_L3_FN_MOD2_s ALT_L3_FN_MOD2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_FN_MOD2 register from the beginning of the component. */ +#define ALT_L3_FN_MOD2_OFST 0x24 +/* The address of the ALT_L3_FN_MOD2 register. */ +#define ALT_L3_FN_MOD2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD2_OFST)) + +/* + * Register : Functionality Modification AHB Register - fn_mod_ahb + * + * Controls how AHB-lite burst transactions are converted to AXI tranactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [0] | RW | 0x0 | Read Increment Override + * [1] | RW | 0x0 | Write Increment Override + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Read Increment Override - rd_incr_override + * + * Controls how AHB-lite read burst transactions are converted to AXI tranactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:---------------------------------------------- + * ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT | 0x0 | The L3 Interconnect converts AHB-lite read + * : | | bursts to AXI transactions in accordance with + * : | | the default behavior as specified in the ARM + * : | | NIC-301 documentation. + * ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES | 0x1 | The L3 Interconnect converts AHB-lite read + * : | | bursts to AXI single transactions. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE + * + * The L3 Interconnect converts AHB-lite read bursts to AXI transactions in + * accordance with the default behavior as specified in the ARM NIC-301 + * documentation. + */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE + * + * The L3 Interconnect converts AHB-lite read bursts to AXI single transactions. + */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_MSB 0 +/* The width in bits of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE field value from a register. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Write Increment Override - wr_incr_override + * + * Controls how AHB-lite write burst transactions are converted to AXI tranactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:---------------------------------------------- + * ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT | 0x0 | The L3 Interconnect converts AHB-lite write + * : | | bursts to AXI transactions in accordance with + * : | | the default behavior as specified in the ARM + * : | | NIC-301 documentation. + * ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES | 0x1 | The L3 Interconnect converts AHB-lite write + * : | | bursts to AXI single transactions. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE + * + * The L3 Interconnect converts AHB-lite write bursts to AXI transactions in + * accordance with the default behavior as specified in the ARM NIC-301 + * documentation. + */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE + * + * The L3 Interconnect converts AHB-lite write bursts to AXI single transactions. + */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_MSB 1 +/* The width in bits of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE field value from a register. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_FN_MOD_AHB. + */ +struct ALT_L3_FN_MOD_AHB_s +{ + uint32_t rd_incr_override : 1; /* Read Increment Override */ + uint32_t wr_incr_override : 1; /* Write Increment Override */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_FN_MOD_AHB. */ +typedef volatile struct ALT_L3_FN_MOD_AHB_s ALT_L3_FN_MOD_AHB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_FN_MOD_AHB register from the beginning of the component. */ +#define ALT_L3_FN_MOD_AHB_OFST 0x28 +/* The address of the ALT_L3_FN_MOD_AHB register. */ +#define ALT_L3_FN_MOD_AHB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_AHB_OFST)) + +/* + * Register : Read Channel QoS Value - read_qos + * + * QoS (Quality of Service) value for the read channel. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x0 | Priority + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Priority - pri + * + * QoS (Quality of Service) value for the read channel. A higher value has a higher + * priority. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_RD_QOS_PRI register field. */ +#define ALT_L3_RD_QOS_PRI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_RD_QOS_PRI register field. */ +#define ALT_L3_RD_QOS_PRI_MSB 3 +/* The width in bits of the ALT_L3_RD_QOS_PRI register field. */ +#define ALT_L3_RD_QOS_PRI_WIDTH 4 +/* The mask used to set the ALT_L3_RD_QOS_PRI register field value. */ +#define ALT_L3_RD_QOS_PRI_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L3_RD_QOS_PRI register field value. */ +#define ALT_L3_RD_QOS_PRI_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L3_RD_QOS_PRI register field. */ +#define ALT_L3_RD_QOS_PRI_RESET 0x0 +/* Extracts the ALT_L3_RD_QOS_PRI field value from a register. */ +#define ALT_L3_RD_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L3_RD_QOS_PRI register field value suitable for setting the register. */ +#define ALT_L3_RD_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_RD_QOS. + */ +struct ALT_L3_RD_QOS_s +{ + uint32_t pri : 4; /* Priority */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_RD_QOS. */ +typedef volatile struct ALT_L3_RD_QOS_s ALT_L3_RD_QOS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_RD_QOS register from the beginning of the component. */ +#define ALT_L3_RD_QOS_OFST 0x100 +/* The address of the ALT_L3_RD_QOS register. */ +#define ALT_L3_RD_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_RD_QOS_OFST)) + +/* + * Register : Write Channel QoS Value - write_qos + * + * QoS (Quality of Service) value for the write channel. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x0 | Priority + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Priority - pri + * + * QoS (Quality of Service) value for the write channel. A higher value has a + * higher priority. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_WR_QOS_PRI register field. */ +#define ALT_L3_WR_QOS_PRI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_WR_QOS_PRI register field. */ +#define ALT_L3_WR_QOS_PRI_MSB 3 +/* The width in bits of the ALT_L3_WR_QOS_PRI register field. */ +#define ALT_L3_WR_QOS_PRI_WIDTH 4 +/* The mask used to set the ALT_L3_WR_QOS_PRI register field value. */ +#define ALT_L3_WR_QOS_PRI_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L3_WR_QOS_PRI register field value. */ +#define ALT_L3_WR_QOS_PRI_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L3_WR_QOS_PRI register field. */ +#define ALT_L3_WR_QOS_PRI_RESET 0x0 +/* Extracts the ALT_L3_WR_QOS_PRI field value from a register. */ +#define ALT_L3_WR_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L3_WR_QOS_PRI register field value suitable for setting the register. */ +#define ALT_L3_WR_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_WR_QOS. + */ +struct ALT_L3_WR_QOS_s +{ + uint32_t pri : 4; /* Priority */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_WR_QOS. */ +typedef volatile struct ALT_L3_WR_QOS_s ALT_L3_WR_QOS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_WR_QOS register from the beginning of the component. */ +#define ALT_L3_WR_QOS_OFST 0x104 +/* The address of the ALT_L3_WR_QOS register. */ +#define ALT_L3_WR_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_QOS_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_DAP. + */ +struct ALT_L3_SLV_DAP_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD2_t fn_mod2; /* ALT_L3_FN_MOD2 */ + volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_DAP. */ +typedef volatile struct ALT_L3_SLV_DAP_s ALT_L3_SLV_DAP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_DAP. */ +struct ALT_L3_SLV_DAP_raw_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile uint32_t fn_mod2; /* ALT_L3_FN_MOD2 */ + volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DAP. */ +typedef volatile struct ALT_L3_SLV_DAP_raw_s ALT_L3_SLV_DAP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : MPU - ALT_L3_SLV_MPU + * MPU + * + * Registers associated with the MPU slave interface. This slave is used by the MPU + * to access slaves attached to the L3/L4 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_MPU. + */ +struct ALT_L3_SLV_MPU_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_MPU. */ +typedef volatile struct ALT_L3_SLV_MPU_s ALT_L3_SLV_MPU_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_MPU. */ +struct ALT_L3_SLV_MPU_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_MPU. */ +typedef volatile struct ALT_L3_SLV_MPU_raw_s ALT_L3_SLV_MPU_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : SDMMC - ALT_L3_SLV_SDMMC + * SDMMC + * + * Registers associated with the SDMMC slave interface. This slave is used by the + * DMA controller built into the SDMMC to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_SDMMC. + */ +struct ALT_L3_SLV_SDMMC_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_SDMMC. */ +typedef volatile struct ALT_L3_SLV_SDMMC_s ALT_L3_SLV_SDMMC_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */ +struct ALT_L3_SLV_SDMMC_raw_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */ +typedef volatile struct ALT_L3_SLV_SDMMC_raw_s ALT_L3_SLV_SDMMC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : DMA - ALT_L3_SLV_DMA + * DMA + * + * Registers associated with the DMA Controller slave interface. This slave is used + * by the DMA Controller to access slaves attached to the L3/L4 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_DMA. + */ +struct ALT_L3_SLV_DMA_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_DMA. */ +typedef volatile struct ALT_L3_SLV_DMA_s ALT_L3_SLV_DMA_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_DMA. */ +struct ALT_L3_SLV_DMA_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DMA. */ +typedef volatile struct ALT_L3_SLV_DMA_raw_s ALT_L3_SLV_DMA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : FPGA2HPS - ALT_L3_SLV_F2H + * FPGA2HPS + * + * Registers associated with the FPGA2HPS AXI Bridge slave interface. This slave is + * used by the FPGA2HPS AXI Bridge to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_F2H. + */ +struct ALT_L3_SLV_F2H_s +{ + volatile uint32_t _pad_0x0_0x3f[16]; /* *UNDEFINED* */ + volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_F2H. */ +typedef volatile struct ALT_L3_SLV_F2H_s ALT_L3_SLV_F2H_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_F2H. */ +struct ALT_L3_SLV_F2H_raw_s +{ + volatile uint32_t _pad_0x0_0x3f[16]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_F2H. */ +typedef volatile struct ALT_L3_SLV_F2H_raw_s ALT_L3_SLV_F2H_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ETR - ALT_L3_SLV_ETR + * ETR + * + * Registers associated with the ETR (TMC) slave interface. This slave is used by + * the ETR to access slaves attached to the L3/L4 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_ETR. + */ +struct ALT_L3_SLV_ETR_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_ETR. */ +typedef volatile struct ALT_L3_SLV_ETR_s ALT_L3_SLV_ETR_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_ETR. */ +struct ALT_L3_SLV_ETR_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_ETR. */ +typedef volatile struct ALT_L3_SLV_ETR_raw_s ALT_L3_SLV_ETR_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : EMAC0 - ALT_L3_SLV_EMAC0 + * EMAC0 + * + * Registers associated with the EMAC0 slave interface. This slave is used by the + * DMA controller built into the EMAC0 to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_EMAC0. + */ +struct ALT_L3_SLV_EMAC0_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_EMAC0. */ +typedef volatile struct ALT_L3_SLV_EMAC0_s ALT_L3_SLV_EMAC0_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */ +struct ALT_L3_SLV_EMAC0_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */ +typedef volatile struct ALT_L3_SLV_EMAC0_raw_s ALT_L3_SLV_EMAC0_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : EMAC1 - ALT_L3_SLV_EMAC1 + * EMAC1 + * + * Registers associated with the EMAC1 slave interface. This slave is used by the + * DMA controller built into the EMAC1 to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_EMAC1. + */ +struct ALT_L3_SLV_EMAC1_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_EMAC1. */ +typedef volatile struct ALT_L3_SLV_EMAC1_s ALT_L3_SLV_EMAC1_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */ +struct ALT_L3_SLV_EMAC1_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */ +typedef volatile struct ALT_L3_SLV_EMAC1_raw_s ALT_L3_SLV_EMAC1_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB0 - ALT_L3_SLV_USB0 + * USB0 + * + * Registers associated with the USB0 slave interface. This slave is used by the + * DMA controller built into the USB0 to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_USB0. + */ +struct ALT_L3_SLV_USB0_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_USB0. */ +typedef volatile struct ALT_L3_SLV_USB0_s ALT_L3_SLV_USB0_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB0. */ +struct ALT_L3_SLV_USB0_raw_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB0. */ +typedef volatile struct ALT_L3_SLV_USB0_raw_s ALT_L3_SLV_USB0_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : NAND - ALT_L3_SLV_NAND + * NAND + * + * Registers associated with the NAND slave interface. This slave is used by the + * DMA controller built into the NAND flash controller to access slaves attached to + * the L3/L4 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_NAND. + */ +struct ALT_L3_SLV_NAND_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_NAND. */ +typedef volatile struct ALT_L3_SLV_NAND_s ALT_L3_SLV_NAND_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_NAND. */ +struct ALT_L3_SLV_NAND_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_NAND. */ +typedef volatile struct ALT_L3_SLV_NAND_raw_s ALT_L3_SLV_NAND_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB1 - ALT_L3_SLV_USB1 + * USB1 + * + * Registers associated with the USB1 slave interface. This slave is used by the + * DMA controller built into the USB1 to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_USB1. + */ +struct ALT_L3_SLV_USB1_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_USB1. */ +typedef volatile struct ALT_L3_SLV_USB1_s ALT_L3_SLV_USB1_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB1. */ +struct ALT_L3_SLV_USB1_raw_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB1. */ +typedef volatile struct ALT_L3_SLV_USB1_raw_s ALT_L3_SLV_USB1_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLVGRP. + */ +struct ALT_L3_SLVGRP_s +{ + volatile ALT_L3_SLV_DAP_t slavegrp_dap; /* ALT_L3_SLV_DAP */ + volatile uint32_t _pad_0x10c_0xfff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_MPU_t slavegrp_mpu; /* ALT_L3_SLV_MPU */ + volatile uint32_t _pad_0x110c_0x1fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_SDMMC_t slavegrp_sdmmc; /* ALT_L3_SLV_SDMMC */ + volatile uint32_t _pad_0x210c_0x2fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_DMA_t slavegrp_dma; /* ALT_L3_SLV_DMA */ + volatile uint32_t _pad_0x310c_0x3fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_F2H_t slavegrp_fpga2hps; /* ALT_L3_SLV_F2H */ + volatile uint32_t _pad_0x410c_0x4fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_ETR_t slavegrp_etr; /* ALT_L3_SLV_ETR */ + volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_EMAC0_t slavegrp_emac0; /* ALT_L3_SLV_EMAC0 */ + volatile uint32_t _pad_0x610c_0x6fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_EMAC1_t slavegrp_emac1; /* ALT_L3_SLV_EMAC1 */ + volatile uint32_t _pad_0x710c_0x7fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_USB0_t slavegrp_usb0; /* ALT_L3_SLV_USB0 */ + volatile uint32_t _pad_0x810c_0x8fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_NAND_t slavegrp_nand; /* ALT_L3_SLV_NAND */ + volatile uint32_t _pad_0x910c_0x9fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_USB1_t slavegrp_usb1; /* ALT_L3_SLV_USB1 */ +}; + +/* The typedef declaration for register group ALT_L3_SLVGRP. */ +typedef volatile struct ALT_L3_SLVGRP_s ALT_L3_SLVGRP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLVGRP. */ +struct ALT_L3_SLVGRP_raw_s +{ + volatile ALT_L3_SLV_DAP_raw_t slavegrp_dap; /* ALT_L3_SLV_DAP */ + volatile uint32_t _pad_0x10c_0xfff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_MPU_raw_t slavegrp_mpu; /* ALT_L3_SLV_MPU */ + volatile uint32_t _pad_0x110c_0x1fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_SDMMC_raw_t slavegrp_sdmmc; /* ALT_L3_SLV_SDMMC */ + volatile uint32_t _pad_0x210c_0x2fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_DMA_raw_t slavegrp_dma; /* ALT_L3_SLV_DMA */ + volatile uint32_t _pad_0x310c_0x3fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_F2H_raw_t slavegrp_fpga2hps; /* ALT_L3_SLV_F2H */ + volatile uint32_t _pad_0x410c_0x4fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_ETR_raw_t slavegrp_etr; /* ALT_L3_SLV_ETR */ + volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_EMAC0_raw_t slavegrp_emac0; /* ALT_L3_SLV_EMAC0 */ + volatile uint32_t _pad_0x610c_0x6fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_EMAC1_raw_t slavegrp_emac1; /* ALT_L3_SLV_EMAC1 */ + volatile uint32_t _pad_0x710c_0x7fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_USB0_raw_t slavegrp_usb0; /* ALT_L3_SLV_USB0 */ + volatile uint32_t _pad_0x810c_0x8fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_NAND_raw_t slavegrp_nand; /* ALT_L3_SLV_NAND */ + volatile uint32_t _pad_0x910c_0x9fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_USB1_raw_t slavegrp_usb1; /* ALT_L3_SLV_USB1 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLVGRP. */ +typedef volatile struct ALT_L3_SLVGRP_raw_s ALT_L3_SLVGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3. + */ +struct ALT_L3_s +{ + volatile ALT_L3_REMAP_t remap; /* ALT_L3_REMAP */ + volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */ + volatile ALT_L3_SECGRP_t secgrp; /* ALT_L3_SECGRP */ + volatile uint32_t _pad_0xa4_0xfff[983]; /* *UNDEFINED* */ + volatile ALT_L3_IDGRP_t idgrp; /* ALT_L3_IDGRP */ + volatile ALT_L3_MSTGRP_t mastergrp; /* ALT_L3_MSTGRP */ + volatile uint32_t _pad_0x2710c_0x41fff[27581]; /* *UNDEFINED* */ + volatile ALT_L3_SLVGRP_t slavegrp; /* ALT_L3_SLVGRP */ + volatile uint32_t _pad_0x4c10c_0x80000[53181]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_L3. */ +typedef volatile struct ALT_L3_s ALT_L3_t; +/* The struct declaration for the raw register contents of register group ALT_L3. */ +struct ALT_L3_raw_s +{ + volatile uint32_t remap; /* ALT_L3_REMAP */ + volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */ + volatile ALT_L3_SECGRP_raw_t secgrp; /* ALT_L3_SECGRP */ + volatile uint32_t _pad_0xa4_0xfff[983]; /* *UNDEFINED* */ + volatile ALT_L3_IDGRP_raw_t idgrp; /* ALT_L3_IDGRP */ + volatile ALT_L3_MSTGRP_raw_t mastergrp; /* ALT_L3_MSTGRP */ + volatile uint32_t _pad_0x2710c_0x41fff[27581]; /* *UNDEFINED* */ + volatile ALT_L3_SLVGRP_raw_t slavegrp; /* ALT_L3_SLVGRP */ + volatile uint32_t _pad_0x4c10c_0x80000[53181]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3. */ +typedef volatile struct ALT_L3_raw_s ALT_L3_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_L3_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h new file mode 100644 index 0000000000..cbec31b76f --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h @@ -0,0 +1,5951 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_QSPI */ + +#ifndef __ALTERA_ALT_QSPI_H__ +#define __ALTERA_ALT_QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : QSPI Flash Controller Module Registers - ALT_QSPI + * QSPI Flash Controller Module Registers + * + * Registers in the QSPI Flash Controller module accessible via its APB slave + * + */ +/* + * Register : QSPI Configuration Register - cfg + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------- + * [0] | RW | 0x0 | QSPI Enable + * [1] | RW | 0x0 | Clock Polarity + * [2] | RW | 0x0 | Select Clock Phase + * [6:3] | ??? | 0x0 | *UNDEFINED* + * [7] | RW | 0x0 | Enable Direct Access Controller + * [8] | RW | 0x0 | Legacy IP Mode Enable + * [9] | RW | 0x0 | Peripheral select decode + * [13:10] | RW | 0x0 | Peripheral Chip Select Lines + * [14] | RW | 0x0 | Write Protect Flash Pin + * [15] | RW | 0x0 | Enable DMA Peripheral Interface + * [16] | RW | 0x0 | Enable AHB Address Re-mapping + * [17] | RW | 0x0 | Enter XIP Mode on next READ + * [18] | RW | 0x0 | Enter XIP Mode Immediately + * [22:19] | RW | 0xf | Master Mode Baud Rate Divisor + * [30:23] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x0 | Serial interface and QSPI pipeline is IDLE + * + */ +/* + * Field : QSPI Enable - en + * + * If this bit is disabled, the QSPI will finish the current transfer of the data + * word (FF_W) and stop sending. When Enabled, and qspi_n_mo_en = 0, all output + * enables are inactive and all pins are set to input mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------|:------|:----------------- + * ALT_QSPI_CFG_EN_E_DIS | 0x0 | Disable the QSPI + * ALT_QSPI_CFG_EN_E_EN | 0x1 | Enable the QSPI + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_EN + * + * Disable the QSPI + */ +#define ALT_QSPI_CFG_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_EN + * + * Enable the QSPI + */ +#define ALT_QSPI_CFG_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_MSB 0 +/* The width in bits of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_EN register field value. */ +#define ALT_QSPI_CFG_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_CFG_EN register field value. */ +#define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_EN field value from a register. */ +#define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Clock Polarity - selclkpol + * + * Controls spiclk modes of operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------- + * ALT_QSPI_CFG_SELCLKPOL_E_LOW | 0x1 | SPI clock is quiescent low + * ALT_QSPI_CFG_SELCLKPOL_E_HIGH | 0x0 | SPI clock is quiescent high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL + * + * SPI clock is quiescent low + */ +#define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL + * + * SPI clock is quiescent high + */ +#define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_MSB 1 +/* The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value. */ +#define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value. */ +#define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register. */ +#define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Select Clock Phase - selclkphase + * + * Selects whether the clock is in an active or inactive phase outside the SPI + * word. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:--------------------------- + * ALT_QSPI_CFG_SELCLKPHASE_E_ACT | 0x0 | SPI clock is quiescent low + * ALT_QSPI_CFG_SELCLKPHASE_E_INACT | 0x1 | Clock Inactive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE + * + * SPI clock is quiescent low + */ +#define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE + * + * Clock Inactive + */ +#define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_MSB 2 +/* The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value. */ +#define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value. */ +#define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register. */ +#define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Enable Direct Access Controller - endiracc + * + * If disabled, the Direct Access Controller becomes inactive once the current + * transfer of the data word (FF_W) is complete. When the Direct Access Controller + * and Indirect Access Controller are both disabled, all AHB requests are completed + * with an error response. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_QSPI_CFG_ENDIRACC_E_DIS | 0x0 | Disable Direct Access Ctrl + * ALT_QSPI_CFG_ENDIRACC_E_EN | 0x1 | Enable Direct Access Ctrl + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC + * + * Disable Direct Access Ctrl + */ +#define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC + * + * Enable Direct Access Ctrl + */ +#define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_MSB 7 +/* The width in bits of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value. */ +#define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value. */ +#define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register. */ +#define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Legacy IP Mode Enable - enlegacyip + * + * This bit can select the Direct Access Controller/Indirect Access Controller or + * legacy mode.If legacy mode is selected, any write to the controller via the AHB + * interface is serialized and sent to the FLASH device. Any valid AHB read will + * pop the internal RX-FIFO, retrieving data that was forwarded by the external + * FLASH device on the SPI lines, byte transfers of 4, 2 or 1 are permitted and + * controlled via the HSIZE input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------------------------------- + * ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD | 0x1 | Legacy Mode + * ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD | 0x0 | Use Direct/Indirect Access Controller + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP + * + * Legacy Mode + */ +#define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP + * + * Use Direct/Indirect Access Controller + */ +#define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_MSB 8 +/* The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value. */ +#define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value. */ +#define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register. */ +#define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Peripheral select decode - perseldec + * + * Select between '1 of 4 selects' or 'external 4-to-16 decode'. The + * qspi_n_ss_out[3:0] output signals are controlled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------- + * ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 | 0x1 | Select external 4-to-16 decode + * ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 | 0x0 | Selects 1 of 4 qspi_n_ss_out[3:0] + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC + * + * Select external 4-to-16 decode + */ +#define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC + * + * Selects 1 of 4 qspi_n_ss_out[3:0] + */ +#define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_MSB 9 +/* The width in bits of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value. */ +#define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value. */ +#define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register. */ +#define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Peripheral Chip Select Lines - percslines + * + * Peripheral chip select line output decode type. As per perseldec, if perseldec = + * 0, the decode is select 1 of 4 decoding on signals, qspi_n_ss_out[3:0], The + * asserted decode line goes to 0. If perseldec = 1, the signals qspi_n_ss_out[3:0] + * require an external 4 to 16 decoder. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_MSB 13 +/* The width in bits of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_WIDTH 4 +/* The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value. */ +#define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00 +/* The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value. */ +#define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff +/* The reset value of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register. */ +#define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10) +/* Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00) + +/* + * Field : Write Protect Flash Pin - wp + * + * This bit controls the write protect pin of the flash devices. The signal + * qspi_mo2_wpn needs to be resynchronized to the generated memory clock as + * necessary. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------- + * ALT_QSPI_CFG_WP_E_WRPROTON | 0x1 | Enable Write Protect + * ALT_QSPI_CFG_WP_E_WRTPROTOFF | 0x0 | Disable Write Protect + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_WP + * + * Enable Write Protect + */ +#define ALT_QSPI_CFG_WP_E_WRPROTON 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_WP + * + * Disable Write Protect + */ +#define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_MSB 14 +/* The width in bits of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_WP register field value. */ +#define ALT_QSPI_CFG_WP_SET_MSK 0x00004000 +/* The mask used to clear the ALT_QSPI_CFG_WP register field value. */ +#define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff +/* The reset value of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_WP field value from a register. */ +#define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Enable DMA Peripheral Interface - endma + * + * Allows DMA handshaking mode. When enabled the QSPI will trigger DMA transfer + * requests via the DMA peripheral interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------- + * ALT_QSPI_CFG_ENDMA_E_EN | 0x1 | Enable DMA Mode + * ALT_QSPI_CFG_ENDMA_E_DIS | 0x0 | Disable DMA Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDMA + * + * Enable DMA Mode + */ +#define ALT_QSPI_CFG_ENDMA_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDMA + * + * Disable DMA Mode + */ +#define ALT_QSPI_CFG_ENDMA_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_MSB 15 +/* The width in bits of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENDMA register field value. */ +#define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000 +/* The mask used to clear the ALT_QSPI_CFG_ENDMA register field value. */ +#define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff +/* The reset value of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENDMA field value from a register. */ +#define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Enable AHB Address Re-mapping - enahbremap + * + * (Direct Access Mode Only) When enabled, the incoming AHB address will be adapted + * and sent to the FLASH device as (address + N), where N is the value stored in + * the remap address register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------- + * ALT_QSPI_CFG_ENAHBREMAP_E_EN | 0x1 | Enable AHB Re-mapping + * ALT_QSPI_CFG_ENAHBREMAP_E_DIS | 0x0 | Disable AHB Re-mapping + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP + * + * Enable AHB Re-mapping + */ +#define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP + * + * Disable AHB Re-mapping + */ +#define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_MSB 16 +/* The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value. */ +#define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000 +/* The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value. */ +#define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff +/* The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register. */ +#define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Enter XIP Mode on next READ - enterxipnextrd + * + * If XIP is enabled, then setting to disabled will cause the controller to exit + * XIP mode on the next READ instruction. If XIP is disabled, then setting to + * enabled will inform the controller that the device is ready to enter XIP on the + * next READ instruction. The controller will therefore send the appropriate + * command sequence, including mode bits to cause the device to enter XIP mode. Use + * this register after the controller has ensured the FLASH device has been + * configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit + * should be set to 0. This will take effect in the attached device only AFTER the + * next READ instruction is executed. Software should therefore ensure that at + * least one READ instruction is requested after resetting this bit before it can + * be sure XIP mode in the device is exited. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------- + * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN | 0x1 | Enter XIP Mode on next READ instruction + * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS | 0x0 | Exit XIP Mode on next READ instruction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD + * + * Enter XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD + * + * Exit XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17 +/* The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000 +/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff +/* The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Enter XIP Mode Immediately - enterxipimm + * + * If XIP is enabled, then setting to disabled will cause the controller to exit + * XIP mode on the next READ instruction. If XIP is disabled, then setting enable + * will operate the device in XIP mode immediately. Use this register when the + * external device wakes up in XIP mode (as per the contents of its non- volatile + * configuration register). The controller will assume the next READ instruction + * will be passed to the device as an XIP instruction, and therefore will not + * require the READ opcode to be transferred. Note: To exit XIP mode, this bit + * should be set to 0. This will take effect in the attached device only after the + * next READ instruction is executed. Software therefore should ensure that at + * least one READ instruction is requested after resetting this bit in order to be + * sure that XIP mode is exited. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:--------------------------------------- + * ALT_QSPI_CFG_ENTERXIPIMM_E_EN | 0x1 | Enter XIP Mode immediately + * ALT_QSPI_CFG_ENTERXIPIMM_E_DIS | 0x0 | Exit XIP Mode on next READ instruction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM + * + * Enter XIP Mode immediately + */ +#define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM + * + * Exit XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18 +/* The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000 +/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff +/* The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Master Mode Baud Rate Divisor - bauddiv + * + * SPI baud rate = ref_clk / (2 * baud_rate_divisor) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_QSPI_CFG_BAUDDIV_E_BAUD2 | 0x0 | Baud Rate Div/2 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD4 | 0x1 | Baud Rate Div/4 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD6 | 0x2 | Baud Rate Div/6 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD8 | 0x3 | Baud Rate Div/8 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD10 | 0x4 | Baud Rate Div/10 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD12 | 0x5 | Baud Rate Div/12 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD14 | 0x6 | Baud Rate Div/14 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD16 | 0x7 | Baud Rate Div/16 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD18 | 0x8 | Baud Rate Div/18 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD20 | 0x9 | Baud Rate Div/20 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD22 | 0xa | Baud Rate Div/22 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD24 | 0xb | Baud Rate Div/24 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD26 | 0xc | Baud Rate Div/26 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD28 | 0xd | Baud Rate Div/28 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD30 | 0xe | Baud Rate Div/30 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD32 | 0xf | Baud Rate Div/32 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/2 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/4 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/6 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/8 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/10 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/12 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/14 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/16 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/18 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/20 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/22 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/24 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/26 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/28 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/30 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/32 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_MSB 22 +/* The width in bits of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_WIDTH 4 +/* The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value. */ +#define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000 +/* The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value. */ +#define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff +/* The reset value of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_RESET 0xf +/* Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register. */ +#define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19) +/* Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000) + +/* + * Field : Serial interface and QSPI pipeline is IDLE - idle + * + * This is a STATUS read-only bit. Note this is a retimed signal, so there will be + * some inherent delay on the generation of this status signal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------- + * ALT_QSPI_CFG_IDLE_E_SET | 0x1 | Idle Mode + * ALT_QSPI_CFG_IDLE_E_NOTSET | 0x0 | Non-Idle Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_IDLE + * + * Idle Mode + */ +#define ALT_QSPI_CFG_IDLE_E_SET 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_IDLE + * + * Non-Idle Mode + */ +#define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_MSB 31 +/* The width in bits of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_IDLE register field value. */ +#define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_QSPI_CFG_IDLE register field value. */ +#define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_IDLE field value from a register. */ +#define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_CFG. + */ +struct ALT_QSPI_CFG_s +{ + uint32_t en : 1; /* QSPI Enable */ + uint32_t selclkpol : 1; /* Clock Polarity */ + uint32_t selclkphase : 1; /* Select Clock Phase */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t endiracc : 1; /* Enable Direct Access Controller */ + uint32_t enlegacyip : 1; /* Legacy IP Mode Enable */ + uint32_t perseldec : 1; /* Peripheral select decode */ + uint32_t percslines : 4; /* Peripheral Chip Select Lines */ + uint32_t wp : 1; /* Write Protect Flash Pin */ + uint32_t endma : 1; /* Enable DMA Peripheral Interface */ + uint32_t enahbremap : 1; /* Enable AHB Address Re-mapping */ + uint32_t enterxipnextrd : 1; /* Enter XIP Mode on next READ */ + uint32_t enterxipimm : 1; /* Enter XIP Mode Immediately */ + uint32_t bauddiv : 4; /* Master Mode Baud Rate Divisor */ + uint32_t : 8; /* *UNDEFINED* */ + const uint32_t idle : 1; /* Serial interface and QSPI pipeline is IDLE */ +}; + +/* The typedef declaration for register ALT_QSPI_CFG. */ +typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_CFG register from the beginning of the component. */ +#define ALT_QSPI_CFG_OFST 0x0 + +/* + * Register : Device Read Instruction Register - devrd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [7:0] | RW | 0x3 | Read Opcode in non-XIP mode + * [9:8] | RW | 0x0 | Instruction Transfer Width + * [11:10] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | Address Transfer Width + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [17:16] | RW | 0x0 | Data Transfer Width + * [19:18] | ??? | 0x0 | *UNDEFINED* + * [20] | RW | 0x0 | Mode Bit Enable + * [23:21] | ??? | 0x0 | *UNDEFINED* + * [28:24] | RW | 0x0 | Dummy Read Clock Cycles + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Read Opcode in non-XIP mode - rdopcode + * + * Read Opcode to use when not in XIP mode + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------- + * ALT_QSPI_DEVRD_RDOPCODE_E_RD | 0x3 | Read Opcode in Non-XIP mode + * ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD | 0xb | Fast Read in Non-XIP mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE + * + * Read Opcode in Non-XIP mode + */ +#define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE + * + * Fast Read in Non-XIP mode + */ +#define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_MSB 7 +/* The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value. */ +#define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value. */ +#define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3 +/* Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register. */ +#define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Instruction Transfer Width - instwidth + * + * Sets instruction transfer width (1, 2, or 4 bits). Applies to all instructions + * sent to SPI flash device (not just read instructions). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE | 0x0 | Instruction transferred on DQ0. Supported by all + * : | | SPI flash devices. + * ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL | 0x1 | Instruction transferred on DQ0 and DQ1. + * : | | Supported by all SPI flash devices that support + * : | | the Dual SP (DIO-SPI) Protocol. + * ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD | 0x2 | Instruction transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by all SPI flash devices that + * : | | support the Quad SP (QIO-SPI) Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0. Supported by all SPI flash devices. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that + * support the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash + * devices that support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9 +/* The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300 +/* The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff +/* The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : Address Transfer Width - addrwidth + * + * Sets read address transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE | 0x0 | Read address transferred on DQ0. Supported by + * : | | all SPI flash devices + * ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by some SPI flash devices that + * : | | support the Extended SPI Protocol and by all SPI + * : | | flash devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices + * that support the Extended SPI Protocol and by all SPI flash devices that support + * the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13 +/* The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000 +/* The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff +/* The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Data Transfer Width - datawidth + * + * Sets read data transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE | 0x0 | Read data transferred on DQ0. Supported by all + * : | | SPI flash devices + * ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported + * : | | by some SPI flash devices that support the + * : | | Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that + * support the Extended SPI Protocol and by all SPI flash devices that support the + * Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17 +/* The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Mode Bit Enable - enmodebits + * + * If this bit is set, the mode bits as defined in the Mode Bit Configuration + * register are sent following the address bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------- + * ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER | 0x0 | No Order + * ALT_QSPI_DEVRD_ENMODBITS_E_ORDER | 0x1 | Mode Bits follow address bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS + * + * No Order + */ +#define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS + * + * Mode Bits follow address bytes + */ +#define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_MSB 20 +/* The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1 +/* The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value. */ +#define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000 +/* The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value. */ +#define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff +/* The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register. */ +#define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Dummy Read Clock Cycles - dummyrdclks + * + * Number of dummy clock cycles required by device for read instruction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28 +/* The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000 +/* The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff +/* The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24) +/* Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVRD. + */ +struct ALT_QSPI_DEVRD_s +{ + uint32_t rdopcode : 8; /* Read Opcode in non-XIP mode */ + uint32_t instwidth : 2; /* Instruction Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t addrwidth : 2; /* Address Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t datawidth : 2; /* Data Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t enmodebits : 1; /* Mode Bit Enable */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t dummyrdclks : 5; /* Dummy Read Clock Cycles */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVRD. */ +typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component. */ +#define ALT_QSPI_DEVRD_OFST 0x4 + +/* + * Register : Device Write Instruction Register - devwr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [7:0] | RW | 0x2 | Write Opcode + * [11:8] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | Address Transfer Width + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [17:16] | RW | 0x0 | Data Transfer Width + * [23:18] | ??? | 0x0 | *UNDEFINED* + * [28:24] | RW | 0x0 | Dummy Write Clock Cycles + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write Opcode - wropcode + * + * Write Opcode + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_MSB 7 +/* The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value. */ +#define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value. */ +#define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2 +/* Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register. */ +#define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Address Transfer Width - addrwidth + * + * Sets write address transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE | 0x0 | Write address transferred on DQ0. Supported by + * : | | all SPI flash devices + * ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by some SPI flash devices that + * : | | support the Extended SPI Protocol and by all SPI + * : | | flash devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Write address transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices + * that support the Extended SPI Protocol and by all SPI flash devices that support + * the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13 +/* The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000 +/* The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff +/* The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Data Transfer Width - datawidth + * + * Sets write data transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE | 0x0 | Write data transferred on DQ0. Supported by all + * : | | SPI flash devices + * ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported + * : | | by some SPI flash devices that support the + * : | | Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Write data transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that + * support the Extended SPI Protocol and by all SPI flash devices that support the + * Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17 +/* The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Dummy Write Clock Cycles - dummywrclks + * + * Number of dummy clock cycles required by device for write instruction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28 +/* The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000 +/* The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff +/* The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24) +/* Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVWR. + */ +struct ALT_QSPI_DEVWR_s +{ + uint32_t wropcode : 8; /* Write Opcode */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t addrwidth : 2; /* Address Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t datawidth : 2; /* Data Transfer Width */ + uint32_t : 6; /* *UNDEFINED* */ + uint32_t dummywrclks : 5; /* Dummy Write Clock Cycles */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVWR. */ +typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component. */ +#define ALT_QSPI_DEVWR_OFST 0x8 + +/* + * Register : QSPI Device Delay Register - delay + * + * This register is used to introduce relative delays into the generation of the + * master output signals. All timings are defined in cycles of the qspi_clk. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------- + * [7:0] | RW | 0x0 | Clock Delay with qspi_n_ss_out + * [15:8] | RW | 0x0 | Clock Delay for Last Transaction Bit + * [23:16] | RW | 0x0 | Clock Delay for Chip Select Deactivation + * [31:24] | RW | 0x0 | Clock Delay for Chip Select Deassert + * + */ +/* + * Field : Clock Delay with qspi_n_ss_out - init + * + * Delay in master reference clocks between setting qspi_n_ss_out low and first bit + * transfer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_MSB 7 +/* The width in bits of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_INIT register field value. */ +#define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DELAY_INIT register field value. */ +#define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_INIT field value from a register. */ +#define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Clock Delay for Last Transaction Bit - after + * + * Delay in master reference clocks between last bit of current transaction and + * deasserting the device chip select (qspi_n_ss_out). By default, the chip select + * will be deasserted on the cycle following the completion of the current + * transaction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_MSB 15 +/* The width in bits of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_AFTER register field value. */ +#define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_QSPI_DELAY_AFTER register field value. */ +#define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff +/* The reset value of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_AFTER field value from a register. */ +#define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Clock Delay for Chip Select Deactivation - btwn + * + * Delay in master reference clocks between one chip select being de-activated and + * the activation of another. This is used to ensure a quiet period between the + * selection of two different slaves and requires the transmit FIFO to be empty. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_MSB 23 +/* The width in bits of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_BTWN register field value. */ +#define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_QSPI_DELAY_BTWN register field value. */ +#define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff +/* The reset value of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_BTWN field value from a register. */ +#define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000) + +/* + * Field : Clock Delay for Chip Select Deassert - nss + * + * Delay in master reference clocks for the length that the master mode chip select + * outputs are de-asserted between transactions. The minimum delay is always + * qspi_sck_out period to ensure the chip select is never re-asserted within an + * qspi_sck_out period. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_MSB 31 +/* The width in bits of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_NSS register field value. */ +#define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000 +/* The mask used to clear the ALT_QSPI_DELAY_NSS register field value. */ +#define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff +/* The reset value of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_NSS field value from a register. */ +#define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DELAY. + */ +struct ALT_QSPI_DELAY_s +{ + uint32_t init : 8; /* Clock Delay with qspi_n_ss_out */ + uint32_t after : 8; /* Clock Delay for Last Transaction Bit */ + uint32_t btwn : 8; /* Clock Delay for Chip Select Deactivation */ + uint32_t nss : 8; /* Clock Delay for Chip Select Deassert */ +}; + +/* The typedef declaration for register ALT_QSPI_DELAY. */ +typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DELAY register from the beginning of the component. */ +#define ALT_QSPI_DELAY_OFST 0xc + +/* + * Register : Read Data Capture Register - rddatacap + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | RW | 0x1 | Bypass + * [4:1] | RW | 0x0 | Read Delay + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bypass - byp + * + * Controls bypass of the adapted loopback clock circuit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------ + * ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS | 0x0 | No Bypass + * ALT_QSPI_RDDATACAP_BYP_E_BYPASS | 0x1 | Bypass loopback clock circuit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP + * + * No Bypass + */ +#define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0 +/* + * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP + * + * Bypass loopback clock circuit + */ +#define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_MSB 0 +/* The width in bits of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_WIDTH 1 +/* The mask used to set the ALT_QSPI_RDDATACAP_BYP register field value. */ +#define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_RDDATACAP_BYP register field value. */ +#define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_RESET 0x1 +/* Extracts the ALT_QSPI_RDDATACAP_BYP field value from a register. */ +#define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_RDDATACAP_BYP register field value suitable for setting the register. */ +#define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Read Delay - delay + * + * Delay the read data capturing logic by the programmed number of qspi_clk cycles + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_MSB 4 +/* The width in bits of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4 +/* The mask used to set the ALT_QSPI_RDDATACAP_DELAY register field value. */ +#define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e +/* The mask used to clear the ALT_QSPI_RDDATACAP_DELAY register field value. */ +#define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1 +/* The reset value of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0 +/* Extracts the ALT_QSPI_RDDATACAP_DELAY field value from a register. */ +#define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1) +/* Produces a ALT_QSPI_RDDATACAP_DELAY register field value suitable for setting the register. */ +#define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_RDDATACAP. + */ +struct ALT_QSPI_RDDATACAP_s +{ + uint32_t byp : 1; /* Bypass */ + uint32_t delay : 4; /* Read Delay */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_RDDATACAP. */ +typedef volatile struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_RDDATACAP register from the beginning of the component. */ +#define ALT_QSPI_RDDATACAP_OFST 0x10 + +/* + * Register : Device Size Register - devsz + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [3:0] | RW | 0x2 | Number of address Bytes + * [15:4] | RW | 0x100 | Number of Bytes per Device Page + * [20:16] | RW | 0x10 | Number of Bytes per Block + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Number of address Bytes - numaddrbytes + * + * Number of address bytes. A value of 0 indicates 1 byte. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3 +/* The width in bits of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2 +/* Extracts the ALT_QSPI_DEVSZ_NUMADDRBYTES field value from a register. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_DEVSZ_NUMADDRBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Number of Bytes per Device Page - bytesperdevicepage + * + * Number of bytes per device page. This is required by the controller for + * performing FLASH writes up to and across page boundaries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15 +/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12 +/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0 +/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f +/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100 +/* Extracts the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE field value from a register. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4) +/* Produces a ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0) + +/* + * Field : Number of Bytes per Block - bytespersubsector + * + * Number of bytes per Block. This is required by the controller for performing the + * write protection logic. The number of bytes per block must be a power of 2 + * number. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20 +/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000 +/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff +/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10 +/* Extracts the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR field value from a register. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16) +/* Produces a ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVSZ. + */ +struct ALT_QSPI_DEVSZ_s +{ + uint32_t numaddrbytes : 4; /* Number of address Bytes */ + uint32_t bytesperdevicepage : 12; /* Number of Bytes per Device Page */ + uint32_t bytespersubsector : 5; /* Number of Bytes per Block */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVSZ. */ +typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVSZ register from the beginning of the component. */ +#define ALT_QSPI_DEVSZ_OFST 0x14 + +/* + * Register : SRAM Partition Register - srampart + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [6:0] | RW | 0x40 | Indirect Read Partition Size + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Indirect Read Partition Size - addr + * + * Defines the size of the indirect read partition in the SRAM, in units of SRAM + * locations. By default, half of the SRAM is reserved for indirect read operations + * and half for indirect write operations. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_MSB 6 +/* The width in bits of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_WIDTH 7 +/* The mask used to set the ALT_QSPI_SRAMPART_ADDR register field value. */ +#define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_QSPI_SRAMPART_ADDR register field value. */ +#define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_RESET 0x40 +/* Extracts the ALT_QSPI_SRAMPART_ADDR field value from a register. */ +#define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_QSPI_SRAMPART_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_SRAMPART. + */ +struct ALT_QSPI_SRAMPART_s +{ + uint32_t addr : 7; /* Indirect Read Partition Size */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_SRAMPART. */ +typedef volatile struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_SRAMPART register from the beginning of the component. */ +#define ALT_QSPI_SRAMPART_OFST 0x18 + +/* + * Register : Indirect AHB Address Trigger Register - indaddrtrig + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Trigger Address + * + */ +/* + * Field : Trigger Address - addr + * + * This is the base address that will be used by the AHB controller. When the + * incoming AHB read access address matches a range of addresses from this trigger + * address to the trigger address + 15, then the AHB request will be completed by + * fetching data from the Indirect Controllers SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDADDRTRIG_ADDR register field value. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDADDRTRIG_ADDR register field value. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDADDRTRIG_ADDR field value from a register. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDADDRTRIG_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDADDRTRIG. + */ +struct ALT_QSPI_INDADDRTRIG_s +{ + uint32_t addr : 32; /* Trigger Address */ +}; + +/* The typedef declaration for register ALT_QSPI_INDADDRTRIG. */ +typedef volatile struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDADDRTRIG register from the beginning of the component. */ +#define ALT_QSPI_INDADDRTRIG_OFST 0x1c + +/* + * Register : DMA Peripheral Register - dmaper + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [3:0] | RW | 0x0 | Number of Single Bytes + * [7:4] | ??? | 0x0 | *UNDEFINED* + * [11:8] | RW | 0x0 | Number of Burst Bytes + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Number of Single Bytes - numsglreqbytes + * + * Number of bytes in a single type request on the DMA peripheral request. A + * programmed value of 0 represents a single byte. This should be setup before + * starting the indirect read or write operation. The actual number of bytes used + * is 2**(value in this register) which will simplify implementation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3 +/* The width in bits of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_DMAPER_NUMSGLREQBYTES field value from a register. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Number of Burst Bytes - numburstreqbytes + * + * Number of bytes in a burst type request on the DMA peripheral request. A + * programmed value of 0 represents a single byte. This should be setup before + * starting the indirect read or write operation. The actual number of bytes used + * is 2**(value in this register) which will simplify implementation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11 +/* The width in bits of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00 +/* The mask used to clear the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff +/* The reset value of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_DMAPER_NUMBURSTREQBYTES field value from a register. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8) +/* Produces a ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DMAPER. + */ +struct ALT_QSPI_DMAPER_s +{ + uint32_t numsglreqbytes : 4; /* Number of Single Bytes */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t numburstreqbytes : 4; /* Number of Burst Bytes */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DMAPER. */ +typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DMAPER register from the beginning of the component. */ +#define ALT_QSPI_DMAPER_OFST 0x20 + +/* + * Register : Remap Address Register - remapaddr + * + * This register is used to remap an incoming AHB address to a different address + * used by the FLASH device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | RW | 0x0 | Remap Address Offset + * + */ +/* + * Field : Remap Address Offset - value + * + * This offset is added to the incoming AHB address to determine the address used + * by the FLASH device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_REMAPADDR_VALUE register field value. */ +#define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_REMAPADDR_VALUE register field value. */ +#define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_REMAPADDR_VALUE field value from a register. */ +#define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_REMAPADDR_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_REMAPADDR. + */ +struct ALT_QSPI_REMAPADDR_s +{ + uint32_t value : 32; /* Remap Address Offset */ +}; + +/* The typedef declaration for register ALT_QSPI_REMAPADDR. */ +typedef volatile struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_REMAPADDR register from the beginning of the component. */ +#define ALT_QSPI_REMAPADDR_OFST 0x24 + +/* + * Register : Mode Bit Register - modebit + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | RW | 0x0 | Mode + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Mode - mode + * + * These are the 8 mode bits that are sent to the device following the address + * bytes if mode bit transmission has been enabled. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_MSB 7 +/* The width in bits of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_WIDTH 8 +/* The mask used to set the ALT_QSPI_MODBIT_MOD register field value. */ +#define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_MODBIT_MOD register field value. */ +#define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_RESET 0x0 +/* Extracts the ALT_QSPI_MODBIT_MOD field value from a register. */ +#define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_MODBIT_MOD register field value suitable for setting the register. */ +#define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_MODBIT. + */ +struct ALT_QSPI_MODBIT_s +{ + uint32_t mode : 8; /* Mode */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_MODBIT. */ +typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_MODBIT register from the beginning of the component. */ +#define ALT_QSPI_MODBIT_OFST 0x28 + +/* + * Register : SRAM Fill Register - sramfill + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------------------------- + * [15:0] | R | 0x0 | SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS + * [31:16] | R | 0x0 | SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS + * + */ +/* + * Field : SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS - indrdpart + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15 +/* The width in bits of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16 +/* The mask used to set the ALT_QSPI_SRAMFILL_INDRDPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_QSPI_SRAMFILL_INDRDPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000 +/* The reset value of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0 +/* Extracts the ALT_QSPI_SRAMFILL_INDRDPART field value from a register. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_QSPI_SRAMFILL_INDRDPART register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS - indwrpart + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31 +/* The width in bits of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16 +/* The mask used to set the ALT_QSPI_SRAMFILL_INDWRPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_QSPI_SRAMFILL_INDWRPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff +/* The reset value of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0 +/* Extracts the ALT_QSPI_SRAMFILL_INDWRPART field value from a register. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_QSPI_SRAMFILL_INDWRPART register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_SRAMFILL. + */ +struct ALT_QSPI_SRAMFILL_s +{ + const uint32_t indrdpart : 16; /* SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS */ + const uint32_t indwrpart : 16; /* SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS */ +}; + +/* The typedef declaration for register ALT_QSPI_SRAMFILL. */ +typedef volatile struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_SRAMFILL register from the beginning of the component. */ +#define ALT_QSPI_SRAMFILL_OFST 0x2c + +/* + * Register : TX Threshold Register - txthresh + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x1 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Defines the level at which the transmit FIFO not full interrupt is generated + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_MSB 3 +/* The width in bits of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4 +/* The mask used to set the ALT_QSPI_TXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_TXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1 +/* Extracts the ALT_QSPI_TXTHRESH_LEVEL field value from a register. */ +#define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_TXTHRESH_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_TXTHRESH. + */ +struct ALT_QSPI_TXTHRESH_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_TXTHRESH. */ +typedef volatile struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_TXTHRESH register from the beginning of the component. */ +#define ALT_QSPI_TXTHRESH_OFST 0x30 + +/* + * Register : RX Threshold Register - rxthresh + * + * Device Instruction Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x1 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Defines the level at which the receive FIFO not empty interrupt is generated + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_MSB 3 +/* The width in bits of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4 +/* The mask used to set the ALT_QSPI_RXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_RXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1 +/* Extracts the ALT_QSPI_RXTHRESH_LEVEL field value from a register. */ +#define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_RXTHRESH_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_RXTHRESH. + */ +struct ALT_QSPI_RXTHRESH_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_RXTHRESH. */ +typedef volatile struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_RXTHRESH register from the beginning of the component. */ +#define ALT_QSPI_RXTHRESH_OFST 0x34 + +/* + * Register : Interrupt Status Register - irqstat + * + * The status fields in this register are set when the described event occurs and + * the interrupt is enabled in the mask register. When any of these bit fields are + * set, the interrupt output is asserted high. The fields are each cleared by + * writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when + * legacy SPI mode is active. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------ + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Underflow Detected + * [2] | RW | 0x0 | Indirect Operation Complete + * [3] | RW | 0x0 | Indirect Read Reject + * [4] | RW | 0x0 | Protected Area Write Attempt + * [5] | RW | 0x0 | Illegal AHB Access Detected + * [6] | RW | 0x0 | Transfer Watermark Reached + * [7] | RW | 0x0 | Receive Overflow + * [8] | RW | 0x1 | Transmit FIFO Compared to Threshold + * [9] | RW | 0x0 | Transmit FIFO Full + * [10] | RW | 0x0 | Receive FIFO Compared to Threshold + * [11] | RW | 0x0 | Receive FIFO Full + * [12] | RW | 0x0 | Indirect Read Partition overflow + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Underflow Detected - underflowdet + * + * An underflow is detected when an attempt to transfer data is made when the + * transmit FIFO is empty. This may occur when the AHB write data is being supplied + * too slowly to keep up with the requested write operation. This bit is reset only + * by a system reset and cleared only when the register is read. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW | 0x1 | Underflow + * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW | 0x0 | No Underflow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET + * + * Underflow + */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET + * + * No Underflow + */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1 +/* The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Operation Complete - indopdone + * + * Controller has completed last triggered indirect operation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP | 0x1 | Completed Indirect Operation + * ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP | 0x0 | No Indirect Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE + * + * Completed Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE + * + * No Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Indirect Read Reject - indrdreject + * + * Indirect operation was requested but could not be accepted. Two indirect + * operations already in storage. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ | 0x1 | Indirect Operation Requested + * ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ | 0x0 | No Indirect Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT + * + * Indirect Operation Requested + */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT + * + * No Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Protected Area Write Attempt - protwrattempt + * + * Write to protected area was attempted and rejected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------- + * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT | 0x1 | Write Attempt to protected area + * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT | 0x0 | No Write Attempt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT + * + * Write Attempt to protected area + */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT + * + * No Write Attempt + */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4 +/* The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Illegal AHB Access Detected - illegalacc + * + * Illegal AHB access has been detected. AHB wrapping bursts and the use of + * SPLIT/RETRY accesses will cause this error interrupt to trigger. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB | 0x1 | Illegal AHB attempt + * ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB | 0x0 | No Illegal AHB attempt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC + * + * Illegal AHB attempt + */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC + * + * No Illegal AHB attempt + */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5 +/* The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transfer Watermark Reached - indxfrlvl + * + * Indirect Transfer Watermark Level Reached + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL | 0x1 | Water level reached + * ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL | 0x0 | No water level reached + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL + * + * Water level reached + */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL + * + * No water level reached + */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receive Overflow - rxover + * + * This should only occur in Legacy SPI mode. Set if an attempt is made to push the + * RX FIFO when it is full. This bit is reset only by a system reset and cleared + * only when this register is read. If a new push to the RX FIFO occurs coincident + * with a register read this flag will remain set. 0 : no overflow has been + * detected. 1 : an overflow has occurred. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER | 0x1 | Receive Overflow + * ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER | 0x0 | No Receive Overflow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER + * + * Receive Overflow + */ +#define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER + * + * No Receive Overflow + */ +#define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_MSB 7 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value. */ +#define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value. */ +#define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transmit FIFO Compared to Threshold - txthreshcmp + * + * Indicates the number of entries in the transmit FIFO with respect to the + * threshold specified in the TXTHRESH register. Only relevant in SPI legacy mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT | 0x0 | FIFO has > TXTHRESH entries + * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE | 0x1 | FIFO has <= TXTHRESH entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP + * + * FIFO has > TXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP + * + * FIFO has <= TXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8 +/* The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1 +/* Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Transmit FIFO Full - txfull + * + * Indicates that the transmit FIFO is full or not. Only relevant in SPI legacy + * mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL | 0x0 | Transmit FIFO Not Full + * ALT_QSPI_IRQSTAT_TXFULL_E_FULL | 0x1 | Transmit FIFO Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL + * + * Transmit FIFO Not Full + */ +#define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL + * + * Transmit FIFO Full + */ +#define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_MSB 9 +/* The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Receive FIFO Compared to Threshold - rxthreshcmp + * + * Indicates the number of entries in the receive FIFO with respect to the + * threshold specified in the RXTHRESH register. Only relevant in SPI legacy mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE | 0x0 | FIFO has <= RXTHRESH entries + * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT | 0x1 | FIFO has > RXTHRESH entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP + * + * FIFO has <= RXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP + * + * FIFO has > RXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Receive FIFO Full - rxfull + * + * Indicates that the receive FIFO is full or not. Only relevant in SPI legacy + * mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------- + * ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL | 0x0 | Receive FIFO Not Full + * ALT_QSPI_IRQSTAT_RXFULL_E_FULL | 0x1 | Receive FIFO Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL + * + * Receive FIFO Not Full + */ +#define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL + * + * Receive FIFO Full + */ +#define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_MSB 11 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Indirect Read Partition overflow - indsramfull + * + * Indirect Read Partition of SRAM is full and unable to immediately complete + * indirect operation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------- + * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL | 0x1 | SRAM is full + * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL | 0x0 | SRAM is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL + * + * SRAM is full + */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL + * + * SRAM is not full + */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff +/* The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_IRQSTAT. + */ +struct ALT_QSPI_IRQSTAT_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t underflowdet : 1; /* Underflow Detected */ + uint32_t indopdone : 1; /* Indirect Operation Complete */ + uint32_t indrdreject : 1; /* Indirect Read Reject */ + uint32_t protwrattempt : 1; /* Protected Area Write Attempt */ + uint32_t illegalacc : 1; /* Illegal AHB Access Detected */ + uint32_t indxfrlvl : 1; /* Transfer Watermark Reached */ + uint32_t rxover : 1; /* Receive Overflow */ + uint32_t txthreshcmp : 1; /* Transmit FIFO Compared to Threshold */ + uint32_t txfull : 1; /* Transmit FIFO Full */ + uint32_t rxthreshcmp : 1; /* Receive FIFO Compared to Threshold */ + uint32_t rxfull : 1; /* Receive FIFO Full */ + uint32_t indsramfull : 1; /* Indirect Read Partition overflow */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_IRQSTAT. */ +typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component. */ +#define ALT_QSPI_IRQSTAT_OFST 0x40 + +/* + * Register : Interrupt Mask - irqmask + * + * If disabled, the interrupt for the corresponding interrupt status register bit + * is disabled. If enabled, the interrupt for the corresponding interrupt status + * register bit is enabled. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Underflow Detected Mask + * [2] | RW | 0x0 | Mask + * [3] | RW | 0x0 | Indirect Read Reject Mask + * [4] | RW | 0x0 | Protected Area Write Attempt Mask + * [5] | RW | 0x0 | Illegal Access Detected Mask + * [6] | RW | 0x0 | Transfer Watermark Breach Mask + * [7] | RW | 0x0 | Receive Overflow Mask + * [8] | RW | 0x0 | Transmit FIFO Threshold Compare Mask + * [9] | RW | 0x0 | Transmit FIFO Full Mask + * [10] | RW | 0x0 | Receive FIFO Threshold Compare Mask + * [11] | RW | 0x0 | Receive FIFO full Mask + * [12] | RW | 0x0 | Indirect Read Partition overflow mask + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Underflow Detected Mask - underflowdet + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1 +/* The width in bits of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_UNDERFLOWDET field value from a register. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_IRQMSK_UNDERFLOWDET register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Mask - indopdone + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDOPDONE_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDOPDONE_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2 +/* The width in bits of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDOPDONE register field value. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDOPDONE register field value. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDOPDONE field value from a register. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_IRQMSK_INDOPDONE register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Indirect Read Reject Mask - indrdreject + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDRDREJECT_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3 +/* The width in bits of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDRDREJECT field value from a register. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_IRQMSK_INDRDREJECT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Protected Area Write Attempt Mask - protwrattempt + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4 +/* The width in bits of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_PROTWRATTEMPT field value from a register. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Illegal Access Detected Mask - illegalacc + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_ILLEGALACC_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5 +/* The width in bits of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_ILLEGALACC field value from a register. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_IRQMSK_ILLEGALACC register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transfer Watermark Breach Mask - indxfrlvl + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDXFRLVL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6 +/* The width in bits of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDXFRLVL field value from a register. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_QSPI_IRQMSK_INDXFRLVL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receive Overflow Mask - rxover + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXOVER_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXOVER_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_MSB 7 +/* The width in bits of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXOVER register field value. */ +#define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXOVER register field value. */ +#define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXOVER field value from a register. */ +#define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_IRQMSK_RXOVER register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transmit FIFO Threshold Compare Mask - txthreshcmp + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8 +/* The width in bits of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_TXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_IRQMSK_TXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Transmit FIFO Full Mask - txfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_TXFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_TXFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_MSB 9 +/* The width in bits of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_TXFULL register field value. */ +#define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_IRQMSK_TXFULL register field value. */ +#define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_TXFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_IRQMSK_TXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Receive FIFO Threshold Compare Mask - rxthreshcmp + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10 +/* The width in bits of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_QSPI_IRQMSK_RXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Receive FIFO full Mask - rxfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_MSB 11 +/* The width in bits of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXFULL register field value. */ +#define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXFULL register field value. */ +#define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_QSPI_IRQMSK_RXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Indirect Read Partition overflow mask - indsramfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDSRAMFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12 +/* The width in bits of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff +/* The reset value of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDSRAMFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_QSPI_IRQMSK_INDSRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_IRQMSK. + */ +struct ALT_QSPI_IRQMSK_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t underflowdet : 1; /* Underflow Detected Mask */ + uint32_t indopdone : 1; /* Mask */ + uint32_t indrdreject : 1; /* Indirect Read Reject Mask */ + uint32_t protwrattempt : 1; /* Protected Area Write Attempt Mask */ + uint32_t illegalacc : 1; /* Illegal Access Detected Mask */ + uint32_t indxfrlvl : 1; /* Transfer Watermark Breach Mask */ + uint32_t rxover : 1; /* Receive Overflow Mask */ + uint32_t txthreshcmp : 1; /* Transmit FIFO Threshold Compare Mask */ + uint32_t txfull : 1; /* Transmit FIFO Full Mask */ + uint32_t rxthreshcmp : 1; /* Receive FIFO Threshold Compare Mask */ + uint32_t rxfull : 1; /* Receive FIFO full Mask */ + uint32_t indsramfull : 1; /* Indirect Read Partition overflow mask */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_IRQMSK. */ +typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_IRQMSK register from the beginning of the component. */ +#define ALT_QSPI_IRQMSK_OFST 0x44 + +/* + * Register : Lower Write Protection Register - lowwrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | RW | 0x0 | Block Number + * + */ +/* + * Field : Block Number - subsector + * + * The block number that defines the lower block in the range of blocks that is to + * be locked from writing. The definition of a block in terms of number of bytes is + * programmable via the Device Size Configuration register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31 +/* The width in bits of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32 +/* The mask used to set the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0 +/* Extracts the ALT_QSPI_LOWWRPROT_SUBSECTOR field value from a register. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_LOWWRPROT_SUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_LOWWRPROT. + */ +struct ALT_QSPI_LOWWRPROT_s +{ + uint32_t subsector : 32; /* Block Number */ +}; + +/* The typedef declaration for register ALT_QSPI_LOWWRPROT. */ +typedef volatile struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_LOWWRPROT register from the beginning of the component. */ +#define ALT_QSPI_LOWWRPROT_OFST 0x50 + +/* + * Register : Upper Write Protection Register - uppwrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | RW | 0x0 | Block Number + * + */ +/* + * Field : Block Number - subsector + * + * The block number that defines the upper block in the range of blocks that is to + * be locked from writing. The definition of a block in terms of number of bytes is + * programmable via the Device Size Configuration register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31 +/* The width in bits of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32 +/* The mask used to set the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0 +/* Extracts the ALT_QSPI_UPPWRPROT_SUBSECTOR field value from a register. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_UPPWRPROT_SUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_UPPWRPROT. + */ +struct ALT_QSPI_UPPWRPROT_s +{ + uint32_t subsector : 32; /* Block Number */ +}; + +/* The typedef declaration for register ALT_QSPI_UPPWRPROT. */ +typedef volatile struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_UPPWRPROT register from the beginning of the component. */ +#define ALT_QSPI_UPPWRPROT_OFST 0x54 + +/* + * Register : Write Protection Register - wrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | RW | 0x0 | Write Protection Inversion Bit + * [1] | RW | 0x0 | Write Protection Enable Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write Protection Inversion Bit - inv + * + * When enabled, the protection region defined in the lower and upper write + * protection registers is inverted meaning it is the region that the system is + * permitted to write to. When disabled, the protection region defined in the lower + * and upper write protection registers is the region that the system is not + * permitted to write to. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------- + * ALT_QSPI_WRPROT_INV_E_EN | 0x1 | Write Region allowed + * ALT_QSPI_WRPROT_INV_E_DIS | 0x0 | Write Region not allowed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_WRPROT_INV + * + * Write Region allowed + */ +#define ALT_QSPI_WRPROT_INV_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_WRPROT_INV + * + * Write Region not allowed + */ +#define ALT_QSPI_WRPROT_INV_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_MSB 0 +/* The width in bits of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_WIDTH 1 +/* The mask used to set the ALT_QSPI_WRPROT_INV register field value. */ +#define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_WRPROT_INV register field value. */ +#define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_RESET 0x0 +/* Extracts the ALT_QSPI_WRPROT_INV field value from a register. */ +#define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_WRPROT_INV register field value suitable for setting the register. */ +#define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Write Protection Enable Bit - en + * + * When enabled, any AHB write access with an address within the protection region + * defined in the lower and upper write protection registers is rejected. An AHB + * error response is generated and an interrupt source triggered. When disabled, + * the protection region is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:--------------------------- + * ALT_QSPI_WRPROT_EN_E_EN | 0x1 | AHB Write Access rejected + * ALT_QSPI_WRPROT_EN_E_DIS | 0x0 | Protection Region Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_WRPROT_EN + * + * AHB Write Access rejected + */ +#define ALT_QSPI_WRPROT_EN_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_WRPROT_EN + * + * Protection Region Disabled + */ +#define ALT_QSPI_WRPROT_EN_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_MSB 1 +/* The width in bits of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_WIDTH 1 +/* The mask used to set the ALT_QSPI_WRPROT_EN register field value. */ +#define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_WRPROT_EN register field value. */ +#define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_RESET 0x0 +/* Extracts the ALT_QSPI_WRPROT_EN field value from a register. */ +#define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_WRPROT_EN register field value suitable for setting the register. */ +#define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_WRPROT. + */ +struct ALT_QSPI_WRPROT_s +{ + uint32_t inv : 1; /* Write Protection Inversion Bit */ + uint32_t en : 1; /* Write Protection Enable Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_WRPROT. */ +typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_WRPROT register from the beginning of the component. */ +#define ALT_QSPI_WRPROT_OFST 0x58 + +/* + * Register : Indirect Read Transfer Register - indrd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------------- + * [0] | RW | 0x0 | Start Indirect Read + * [1] | RW | 0x0 | Cancel Indirect Read + * [2] | R | Unknown | Indirect Read Status + * [3] | RW | Unknown | SRAM Full + * [4] | R | Unknown | Queued Indirect Read Operations + * [5] | RW | Unknown | Indirect Completion Status + * [7:6] | R | Unknown | Completed Indirect Operations + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Indirect Read - start + * + * When this bit is enabled, it will trigger an indirect read operation. The + * assumption is that the indirect start address and the indirect number of bytes + * register is setup before triggering the indirect read operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------- + * ALT_QSPI_INDRD_START_E_END | 0x1 | Trigger Indirect Read + * ALT_QSPI_INDRD_START_E_DISD | 0x0 | No Indirect Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_START + * + * Trigger Indirect Read + */ +#define ALT_QSPI_INDRD_START_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_START + * + * No Indirect Read + */ +#define ALT_QSPI_INDRD_START_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_MSB 0 +/* The width in bits of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_START register field value. */ +#define ALT_QSPI_INDRD_START_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_INDRD_START register field value. */ +#define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_START field value from a register. */ +#define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Cancel Indirect Read - cancel + * + * This bit will cancel all ongoing indirect read operations. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------- + * ALT_QSPI_INDRD_CANCEL_E_CANCEL | 0x1 | Cancel Indirect Read + * ALT_QSPI_INDRD_CANCEL_E_NOACTION | 0x0 | Do Not Cancel Indirect Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_CANCEL + * + * Cancel Indirect Read + */ +#define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_CANCEL + * + * Do Not Cancel Indirect Read + */ +#define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_MSB 1 +/* The width in bits of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_CANCEL register field value. */ +#define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value. */ +#define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_CANCEL field value from a register. */ +#define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Read Status - rd_status + * + * Indirect read operation in progress (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------ + * ALT_QSPI_INDRD_RD_STAT_E_RDOP | 0x1 | Read Operation in progress + * ALT_QSPI_INDRD_RD_STAT_E_NOACTION | 0x0 | No read operation in progress + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT + * + * Read Operation in progress + */ +#define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT + * + * No read operation in progress + */ +#define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_MSB 2 +/* The width in bits of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_RD_STAT register field value. */ +#define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_INDRD_RD_STAT register field value. */ +#define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_INDRD_RD_STAT register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_RD_STAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_RD_STAT field value from a register. */ +#define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_INDRD_RD_STAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SRAM Full - sram_full + * + * SRAM full and unable to immediately complete an indirect operation. Write a 1 to + * this field to clear it. ; indirect operation (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------- + * ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL | 0x1 | Sram Full- Cant complete operation + * ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION | 0x0 | SRram Not Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL + * + * Sram Full- Cant complete operation + */ +#define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL + * + * SRram Not Full + */ +#define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_MSB 3 +/* The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value. */ +#define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value. */ +#define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register. */ +#define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Queued Indirect Read Operations - rd_queued + * + * Two indirect read operations have been queued + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD | 0x1 | Queued Indirect Read + * ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION | 0x0 | No Queued Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED + * + * Queued Indirect Read + */ +#define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED + * + * No Queued Read + */ +#define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_MSB 4 +/* The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value. */ +#define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value. */ +#define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register. */ +#define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Indirect Completion Status - ind_ops_done_status + * + * This field is set to 1 when an indirect operation has completed. Write a 1 to + * this field to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------- + * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP | 0x1 | Indirect Op Complete operation + * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION | 0x0 | Indirect Op Not Complete + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT + * + * Indirect Op Complete operation + */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT + * + * Indirect Op Not Complete + */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5 +/* The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STAT field value from a register. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Completed Indirect Operations - num_ind_ops_done + * + * This field contains the number of indirect operations which have been completed. + * This is used in conjunction with the indirect completion status field (bit 5). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7 +/* The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2 +/* The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f +/* The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRD. + */ +struct ALT_QSPI_INDRD_s +{ + uint32_t start : 1; /* Start Indirect Read */ + uint32_t cancel : 1; /* Cancel Indirect Read */ + const uint32_t rd_status : 1; /* Indirect Read Status */ + uint32_t sram_full : 1; /* SRAM Full */ + const uint32_t rd_queued : 1; /* Queued Indirect Read Operations */ + uint32_t ind_ops_done_status : 1; /* Indirect Completion Status */ + const uint32_t num_ind_ops_done : 2; /* Completed Indirect Operations */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRD. */ +typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRD register from the beginning of the component. */ +#define ALT_QSPI_INDRD_OFST 0x60 + +/* + * Register : Indirect Read Transfer Watermark Register - indrdwater + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Watermark Value + * + */ +/* + * Field : Watermark Value - level + * + * This represents the minimum fill level of the SRAM before a DMA peripheral + * access is permitted. When the SRAM fill level passes the watermark, an interrupt + * is also generated. This field can be disabled by writing a value of all zeroes. + * The units of this register are BYTES + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDWATER_LEVEL register field value. */ +#define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDWATER_LEVEL register field value. */ +#define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDWATER_LEVEL field value from a register. */ +#define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDWATER_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDWATER. + */ +struct ALT_QSPI_INDRDWATER_s +{ + uint32_t level : 32; /* Watermark Value */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDWATER. */ +typedef volatile struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDWATER register from the beginning of the component. */ +#define ALT_QSPI_INDRDWATER_OFST 0x64 + +/* + * Register : Indirect Read Transfer Start Address Register - indrdstaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [31:0] | RW | 0x0 | Start Address of Indirect Access + * + */ +/* + * Field : Start Address of Indirect Access - addr + * + * This is the start address from which the indirect access will commence its READ + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDSTADDR_ADDR field value from a register. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDSTADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDSTADDR. + */ +struct ALT_QSPI_INDRDSTADDR_s +{ + uint32_t addr : 32; /* Start Address of Indirect Access */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDSTADDR. */ +typedef volatile struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDSTADDR register from the beginning of the component. */ +#define ALT_QSPI_INDRDSTADDR_OFST 0x68 + +/* + * Register : Indirect Read Transfer Number Bytes Register - indrdcnt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | RW | 0x0 | Indirect Count + * + */ +/* + * Field : Indirect Count - value + * + * This is the number of bytes that the indirect access will consume. This can be + * bigger than the configured size of SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDCNT_VALUE register field value. */ +#define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDCNT_VALUE register field value. */ +#define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDCNT_VALUE field value from a register. */ +#define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDCNT_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDCNT. + */ +struct ALT_QSPI_INDRDCNT_s +{ + uint32_t value : 32; /* Indirect Count */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDCNT. */ +typedef volatile struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDCNT register from the beginning of the component. */ +#define ALT_QSPI_INDRDCNT_OFST 0x6c + +/* + * Register : Indirect Write Transfer Register - indwr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------------- + * [0] | RW | 0x0 | Start Indirect Write + * [1] | RW | 0x0 | Cancel Indirect Write + * [2] | R | Unknown | Indirect Write Status + * [3] | R | 0x0 | Reserved + * [4] | R | Unknown | Queued Indirect Write Operations + * [5] | RW | Unknown | Indirect Completion Status + * [7:6] | R | Unknown | Completed Indirect Operations + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Indirect Write - start + * + * Writing a 1 to this bit will trigger an indirect write operation. The assumption + * is that the indirect start address and the indirect number of bytes register is + * setup before triggering the indirect write operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------------- + * ALT_QSPI_INDWR_START_E_END | 0x1 | Trigger indirect write operation + * ALT_QSPI_INDWR_START_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_START + * + * Trigger indirect write operation + */ +#define ALT_QSPI_INDWR_START_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_START + * + * No Action + */ +#define ALT_QSPI_INDWR_START_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_MSB 0 +/* The width in bits of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_START register field value. */ +#define ALT_QSPI_INDWR_START_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_INDWR_START register field value. */ +#define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_START field value from a register. */ +#define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Cancel Indirect Write - cancel + * + * Writing a 1 to this bit will cancel all ongoing indirect write operations. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR | 0x1 | Cancel Indirect write operation + * ALT_QSPI_INDWR_CANCEL_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_CANCEL + * + * Cancel Indirect write operation + */ +#define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_CANCEL + * + * No Action + */ +#define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_MSB 1 +/* The width in bits of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_CANCEL register field value. */ +#define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value. */ +#define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_CANCEL field value from a register. */ +#define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Write Status - rdstat + * + * Indirect write operation in progress (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------- + * ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT | 0x1 | Indirect write operation + * ALT_QSPI_INDWR_RDSTAT_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT + * + * Indirect write operation + */ +#define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT + * + * No Action + */ +#define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_MSB 2 +/* The width in bits of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value. */ +#define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value. */ +#define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_INDWR_RDSTAT register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_RDSTAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register. */ +#define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Reserved - sramfull + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_MSB 3 +/* The width in bits of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_SRAMFULL register field value. */ +#define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_INDWR_SRAMFULL register field value. */ +#define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_SRAMFULL field value from a register. */ +#define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_INDWR_SRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Queued Indirect Write Operations - rdqueued + * + * Two indirect write operations have been queued + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_INDWR_RDQUEUED_E_INDWROP | 0x1 | Two Indirect write operation + * ALT_QSPI_INDWR_RDQUEUED_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED + * + * Two Indirect write operation + */ +#define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED + * + * No Action + */ +#define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_MSB 4 +/* The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value. */ +#define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value. */ +#define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_INDWR_RDQUEUED register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register. */ +#define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Indirect Completion Status - inddone + * + * This field is set to 1 when an indirect operation has completed. Write a 1 to + * this field to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_INDWR_INDDONE_E_INDCOMPST | 0x1 | Indirect operation completed + * ALT_QSPI_INDWR_INDDONE_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_INDDONE + * + * Indirect operation completed + */ +#define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_INDDONE + * + * No Action + */ +#define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_MSB 5 +/* The width in bits of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_INDDONE register field value. */ +#define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value. */ +#define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_INDWR_INDDONE register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_INDDONE_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_INDDONE field value from a register. */ +#define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Completed Indirect Operations - indcnt + * + * This field contains the count of indirect operations which have been completed. + * This is used in conjunction with the indirect completion status field (bit 5). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_MSB 7 +/* The width in bits of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_WIDTH 2 +/* The mask used to set the ALT_QSPI_INDWR_INDCNT register field value. */ +#define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value. */ +#define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f +/* The reset value of the ALT_QSPI_INDWR_INDCNT register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_INDCNT_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_INDCNT field value from a register. */ +#define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWR. + */ +struct ALT_QSPI_INDWR_s +{ + uint32_t start : 1; /* Start Indirect Write */ + uint32_t cancel : 1; /* Cancel Indirect Write */ + const uint32_t rdstat : 1; /* Indirect Write Status */ + const uint32_t sramfull : 1; /* Reserved */ + const uint32_t rdqueued : 1; /* Queued Indirect Write Operations */ + uint32_t inddone : 1; /* Indirect Completion Status */ + const uint32_t indcnt : 2; /* Completed Indirect Operations */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWR. */ +typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWR register from the beginning of the component. */ +#define ALT_QSPI_INDWR_OFST 0x70 + +/* + * Register : Indirect Write Transfer Watermark Register - indwrwater + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------- + * [31:0] | RW | 0xffffffff | Watermark Value + * + */ +/* + * Field : Watermark Value - level + * + * This represents the maximum fill level of the SRAM before a DMA peripheral + * access is permitted. When the SRAM fill level falls below the watermark, an + * interrupt is also generated. This field can be disabled by writing a value of + * all ones. The units of this register are bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRWATER_LEVEL register field value. */ +#define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRWATER_LEVEL register field value. */ +#define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff +/* Extracts the ALT_QSPI_INDWRWATER_LEVEL field value from a register. */ +#define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRWATER_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRWATER. + */ +struct ALT_QSPI_INDWRWATER_s +{ + uint32_t level : 32; /* Watermark Value */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRWATER. */ +typedef volatile struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRWATER register from the beginning of the component. */ +#define ALT_QSPI_INDWRWATER_OFST 0x74 + +/* + * Register : Indirect Write Transfer Start Address Register - indwrstaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [31:0] | RW | 0x0 | Start of Indirect Access + * + */ +/* + * Field : Start of Indirect Access - addr + * + * This is the start address from which the indirect access will commence its write + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDWRSTADDR_ADDR field value from a register. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRSTADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRSTADDR. + */ +struct ALT_QSPI_INDWRSTADDR_s +{ + uint32_t addr : 32; /* Start of Indirect Access */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRSTADDR. */ +typedef volatile struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRSTADDR register from the beginning of the component. */ +#define ALT_QSPI_INDWRSTADDR_OFST 0x78 + +/* + * Register : Indirect Write Transfer Count Register - indwrcnt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [31:0] | RW | 0x0 | Indirect Number of Bytes + * + */ +/* + * Field : Indirect Number of Bytes - value + * + * This is the number of bytes that the indirect access will consume. This can be + * bigger than the configured size of SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRCNT_VALUE register field value. */ +#define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRCNT_VALUE register field value. */ +#define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_INDWRCNT_VALUE field value from a register. */ +#define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRCNT_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRCNT. + */ +struct ALT_QSPI_INDWRCNT_s +{ + uint32_t value : 32; /* Indirect Number of Bytes */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRCNT. */ +typedef volatile struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRCNT register from the beginning of the component. */ +#define ALT_QSPI_INDWRCNT_OFST 0x7c + +/* + * Register : Flash Command Register - flashcmd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Execute Command + * [1] | R | 0x0 | Command Execution Status + * [6:2] | ??? | 0x0 | *UNDEFINED* + * [11:7] | RW | 0x0 | Number of Dummy Bytes + * [14:12] | RW | 0x0 | Number of Write Data Bytes + * [15] | RW | 0x0 | Write Data Enable + * [17:16] | RW | 0x0 | Number of Address Bytes + * [18] | RW | 0x0 | Mode Bit Enable + * [19] | RW | 0x0 | Command Address Enable + * [22:20] | RW | 0x0 | Number of Read Data Bytes + * [23] | RW | 0x0 | Read Data Enable + * [31:24] | RW | 0x0 | Command Opcode + * + */ +/* + * Field : Execute Command - execcmd + * + * Execute the command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE | 0x1 | Execute Command + * ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD + * + * Execute Command + */ +#define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0 +/* The width in bits of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_EXECCMD register field value. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_FLSHCMD_EXECCMD register field value. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_EXECCMD field value from a register. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_FLSHCMD_EXECCMD register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Command Execution Status - cmdexecstat + * + * Command execution in progress. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------- + * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT | 0x1 | Command Execution Status + * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT + * + * Command Execution Status + */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1 +/* The width in bits of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_CMDEXECSTAT field value from a register. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Number of Dummy Bytes - numdummybytes + * + * Set to the number of dummy bytes required This should be setup before triggering + * the command via the execute field of this register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f +/* The reset value of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7) +/* Produces a ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80) + +/* + * Field : Number of Write Data Bytes - numwrdatabytes + * + * Up to 8 Data bytes may be written using this command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------- + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 | 0x0 | Write 1 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 | 0x1 | Write 2 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 | 0x2 | Write 3 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 | 0x3 | Write 4 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 | 0x4 | Write 5 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 | 0x5 | Write 6 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 | 0x6 | Write 7 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 | 0x7 | Write 8 Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 1 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 2 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 3 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 4 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 5 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 6 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 7 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 8 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMWRDATABYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12) +/* Produces a ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000) + +/* + * Field : Write Data Enable - enwrdata + * + * Set to 1 if the command specified in the command opcode field requires write + * data bytes to be sent to the device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------- + * ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES | 0x1 | Command requires write data bytes + * ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA + * + * Command requires write data bytes + */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff +/* The reset value of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENWRDATA field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_QSPI_FLSHCMD_ENWRDATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Number of Address Bytes - numaddrbytes + * + * Set to the number of address bytes required (the address itself is programmed in + * the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the + * command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address + * bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------- + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 | 0x0 | Write 1 Address Byte + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 | 0x1 | Write 2 Address Bytes + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 | 0x2 | Write 3 Address Bytes + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 | 0x3 | Write 4 Address Bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 1 Address Byte + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 2 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 3 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 4 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMADDRBYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Mode Bit Enable - enmodebit + * + * Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration + * register are sent following the address bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------- + * ALT_QSPI_FLSHCMD_ENMODBIT_E_END | 0x1 | Mode Bit follows address bytes + * ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT + * + * Mode Bit follows address bytes + */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENMODBIT field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_QSPI_FLSHCMD_ENMODBIT register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Command Address Enable - encmdaddr + * + * If enabled, the command specified in bits 31:24 requires an address. This should + * be setup before triggering the command via writing a 1 to the execute field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:--------------------------------------- + * ALT_QSPI_FLSHCMD_ENCMDADDR_E_END | 0x1 | Command in bits 31:24 requires address + * ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR + * + * Command in bits 31:24 requires address + */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENCMDADDR field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_QSPI_FLSHCMD_ENCMDADDR register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Number of Read Data Bytes - numrddatabytes + * + * Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for + * 8 bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 | 0x0 | Read 1 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 | 0x1 | Read 2 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 | 0x2 | Read 3 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 | 0x3 | Read 4 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 | 0x4 | Read 5 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 | 0x5 | Read 6 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 | 0x6 | Read 7 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 | 0x7 | Read 8 Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 1 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 2 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 3 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 4 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 5 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 6 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 7 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 8 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMRDDATABYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20) +/* Produces a ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000) + +/* + * Field : Read Data Enable - enrddata + * + * If enabled, the command specified in the command opcode field (bits 31:24) + * requires read data bytes to be received from the device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------------- + * ALT_QSPI_FLSHCMD_ENRDDATA_E_EN | 0x1 | Command Requires read data + * ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA + * + * Command Requires read data + */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENRDDATA field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_QSPI_FLSHCMD_ENRDDATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Command Opcode - cmdopcode + * + * The command opcode field should be setup before triggering the command. For + * example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of + * this register launches the command. NOTE : Using this approach to issue commands + * to the device will make use of the instruction type of the device instruction + * configuration register. If this field is set to 2'b00, then the command opcode, + * command address, command dummy bytes and command data will all be transferred in + * a serial fashion. If this field is set to 2'b01, then the command opcode, + * command address, command dummy bytes and command data will all be transferred in + * parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command + * opcode, command address, command dummy bytes and command data will all be + * transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff +/* The reset value of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_CMDOPCODE field value from a register. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_QSPI_FLSHCMD_CMDOPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMD. + */ +struct ALT_QSPI_FLSHCMD_s +{ + uint32_t execcmd : 1; /* Execute Command */ + const uint32_t cmdexecstat : 1; /* Command Execution Status */ + uint32_t : 5; /* *UNDEFINED* */ + uint32_t numdummybytes : 5; /* Number of Dummy Bytes */ + uint32_t numwrdatabytes : 3; /* Number of Write Data Bytes */ + uint32_t enwrdata : 1; /* Write Data Enable */ + uint32_t numaddrbytes : 2; /* Number of Address Bytes */ + uint32_t enmodebit : 1; /* Mode Bit Enable */ + uint32_t encmdaddr : 1; /* Command Address Enable */ + uint32_t numrddatabytes : 3; /* Number of Read Data Bytes */ + uint32_t enrddata : 1; /* Read Data Enable */ + uint32_t cmdopcode : 8; /* Command Opcode */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMD. */ +typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMD register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMD_OFST 0x90 + +/* + * Register : Flash Command Address Registers - flashcmdaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Command Address + * + */ +/* + * Field : Command Address - addr + * + * This should be setup before triggering the command with execute field (bit 0) of + * the Flash Command Control register. It is the address used by the command + * specified in the opcode field (bits 31:24) of the Flash Command Control + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDADDR_ADDR field value from a register. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDADDR. + */ +struct ALT_QSPI_FLSHCMDADDR_s +{ + uint32_t addr : 32; /* Command Address */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDADDR. */ +typedef volatile struct ALT_QSPI_FLSHCMDADDR_s ALT_QSPI_FLSHCMDADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDADDR register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDADDR_OFST 0x94 + +/* + * Register : Flash Command Read Data Register (Lower) - flashcmdrddatalo + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [31:0] | RW | 0x0 | Command Read Data (Lower byte) + * + */ +/* + * Field : Command Read Data (Lower byte) - data + * + * This is the data that is returned by the flash device for any status or + * configuration read operation carried out by triggering the event in the control + * register. The register will be valid when the polling bit in the control + * register is low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDRDDATALO_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDRDDATALO_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDRDDATALO. + */ +struct ALT_QSPI_FLSHCMDRDDATALO_s +{ + uint32_t data : 32; /* Command Read Data (Lower byte) */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATALO. */ +typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s ALT_QSPI_FLSHCMDRDDATALO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDRDDATALO register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0 + +/* + * Register : Flash Command Read Data Register (Upper) - flashcmdrddataup + * + * Device Instruction Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [31:0] | RW | 0x0 | Command Read Data (Upper byte) + * + */ +/* + * Field : Command Read Data (Upper byte) - data + * + * This is the data that is returned by the FLASH device for any status or + * configuration read operation carried out by triggering the event in the control + * register. The register will be valid when the polling bit in the control + * register is low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDRDDATAUP_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDRDDATAUP. + */ +struct ALT_QSPI_FLSHCMDRDDATAUP_s +{ + uint32_t data : 32; /* Command Read Data (Upper byte) */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATAUP. */ +typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s ALT_QSPI_FLSHCMDRDDATAUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDRDDATAUP register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4 + +/* + * Register : Flash Command Write Data Register (Lower) - flashcmdwrdatalo + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | Command Write Data Lower Byte + * + */ +/* + * Field : Command Write Data Lower Byte - data + * + * This is the command write data lower byte. This should be setup before + * triggering the command with execute field (bit 0) of the Flash Command Control + * register. It is the data that is to be written to the flash for any status or + * configuration write operation carried out by triggering the event in the Flash + * Command Control register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDWRDATALO_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDWRDATALO_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDWRDATALO. + */ +struct ALT_QSPI_FLSHCMDWRDATALO_s +{ + uint32_t data : 32; /* Command Write Data Lower Byte */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATALO. */ +typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s ALT_QSPI_FLSHCMDWRDATALO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDWRDATALO register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8 + +/* + * Register : Flash Command Write Data Register (Upper) - flashcmdwrdataup + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | ALT_QSPI_FLSHCMDWRDATAUP_DATA + * + */ +/* + * Field : data + * + * This is the command write data upper byte. This should be setup before + * triggering the command with execute field (bit 0) of the Flash Command Control + * register. It is the data that is to be written to the flash for any status or + * configuration write operation carried out by triggering the event in the Flash + * Command Control register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDWRDATAUP_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDWRDATAUP. + */ +struct ALT_QSPI_FLSHCMDWRDATAUP_s +{ + uint32_t data : 32; /* ALT_QSPI_FLSHCMDWRDATAUP_DATA */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATAUP. */ +typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s ALT_QSPI_FLSHCMDWRDATAUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDWRDATAUP register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac + +/* + * Register : Module ID Register - moduleid + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------- + * [24:0] | R | 0x1001 | Module ID number + * [31:25] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Module ID number - value + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_MSB 24 +/* The width in bits of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_WIDTH 25 +/* The mask used to set the ALT_QSPI_MODULEID_VALUE register field value. */ +#define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff +/* The mask used to clear the ALT_QSPI_MODULEID_VALUE register field value. */ +#define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000 +/* The reset value of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_RESET 0x1001 +/* Extracts the ALT_QSPI_MODULEID_VALUE field value from a register. */ +#define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0) +/* Produces a ALT_QSPI_MODULEID_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_MODULEID. + */ +struct ALT_QSPI_MODULEID_s +{ + const uint32_t value : 25; /* Module ID number */ + uint32_t : 7; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_MODULEID. */ +typedef volatile struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_MODULEID register from the beginning of the component. */ +#define ALT_QSPI_MODULEID_OFST 0xfc + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_QSPI. + */ +struct ALT_QSPI_s +{ + volatile ALT_QSPI_CFG_t cfg; /* ALT_QSPI_CFG */ + volatile ALT_QSPI_DEVRD_t devrd; /* ALT_QSPI_DEVRD */ + volatile ALT_QSPI_DEVWR_t devwr; /* ALT_QSPI_DEVWR */ + volatile ALT_QSPI_DELAY_t delay; /* ALT_QSPI_DELAY */ + volatile ALT_QSPI_RDDATACAP_t rddatacap; /* ALT_QSPI_RDDATACAP */ + volatile ALT_QSPI_DEVSZ_t devsz; /* ALT_QSPI_DEVSZ */ + volatile ALT_QSPI_SRAMPART_t srampart; /* ALT_QSPI_SRAMPART */ + volatile ALT_QSPI_INDADDRTRIG_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */ + volatile ALT_QSPI_DMAPER_t dmaper; /* ALT_QSPI_DMAPER */ + volatile ALT_QSPI_REMAPADDR_t remapaddr; /* ALT_QSPI_REMAPADDR */ + volatile ALT_QSPI_MODBIT_t modebit; /* ALT_QSPI_MODBIT */ + volatile ALT_QSPI_SRAMFILL_t sramfill; /* ALT_QSPI_SRAMFILL */ + volatile ALT_QSPI_TXTHRESH_t txthresh; /* ALT_QSPI_TXTHRESH */ + volatile ALT_QSPI_RXTHRESH_t rxthresh; /* ALT_QSPI_RXTHRESH */ + volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_IRQSTAT_t irqstat; /* ALT_QSPI_IRQSTAT */ + volatile ALT_QSPI_IRQMSK_t irqmask; /* ALT_QSPI_IRQMSK */ + volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_LOWWRPROT_t lowwrprot; /* ALT_QSPI_LOWWRPROT */ + volatile ALT_QSPI_UPPWRPROT_t uppwrprot; /* ALT_QSPI_UPPWRPROT */ + volatile ALT_QSPI_WRPROT_t wrprot; /* ALT_QSPI_WRPROT */ + volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */ + volatile ALT_QSPI_INDRD_t indrd; /* ALT_QSPI_INDRD */ + volatile ALT_QSPI_INDRDWATER_t indrdwater; /* ALT_QSPI_INDRDWATER */ + volatile ALT_QSPI_INDRDSTADDR_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */ + volatile ALT_QSPI_INDRDCNT_t indrdcnt; /* ALT_QSPI_INDRDCNT */ + volatile ALT_QSPI_INDWR_t indwr; /* ALT_QSPI_INDWR */ + volatile ALT_QSPI_INDWRWATER_t indwrwater; /* ALT_QSPI_INDWRWATER */ + volatile ALT_QSPI_INDWRSTADDR_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */ + volatile ALT_QSPI_INDWRCNT_t indwrcnt; /* ALT_QSPI_INDWRCNT */ + volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */ + volatile ALT_QSPI_FLSHCMD_t flashcmd; /* ALT_QSPI_FLSHCMD */ + volatile ALT_QSPI_FLSHCMDADDR_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */ + volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */ + volatile ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */ + volatile ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */ + volatile ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */ + volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */ + volatile ALT_QSPI_MODULEID_t moduleid; /* ALT_QSPI_MODULEID */ +}; + +/* The typedef declaration for register group ALT_QSPI. */ +typedef volatile struct ALT_QSPI_s ALT_QSPI_t; +/* The struct declaration for the raw register contents of register group ALT_QSPI. */ +struct ALT_QSPI_raw_s +{ + volatile uint32_t cfg; /* ALT_QSPI_CFG */ + volatile uint32_t devrd; /* ALT_QSPI_DEVRD */ + volatile uint32_t devwr; /* ALT_QSPI_DEVWR */ + volatile uint32_t delay; /* ALT_QSPI_DELAY */ + volatile uint32_t rddatacap; /* ALT_QSPI_RDDATACAP */ + volatile uint32_t devsz; /* ALT_QSPI_DEVSZ */ + volatile uint32_t srampart; /* ALT_QSPI_SRAMPART */ + volatile uint32_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */ + volatile uint32_t dmaper; /* ALT_QSPI_DMAPER */ + volatile uint32_t remapaddr; /* ALT_QSPI_REMAPADDR */ + volatile uint32_t modebit; /* ALT_QSPI_MODBIT */ + volatile uint32_t sramfill; /* ALT_QSPI_SRAMFILL */ + volatile uint32_t txthresh; /* ALT_QSPI_TXTHRESH */ + volatile uint32_t rxthresh; /* ALT_QSPI_RXTHRESH */ + volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */ + volatile uint32_t irqstat; /* ALT_QSPI_IRQSTAT */ + volatile uint32_t irqmask; /* ALT_QSPI_IRQMSK */ + volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */ + volatile uint32_t lowwrprot; /* ALT_QSPI_LOWWRPROT */ + volatile uint32_t uppwrprot; /* ALT_QSPI_UPPWRPROT */ + volatile uint32_t wrprot; /* ALT_QSPI_WRPROT */ + volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */ + volatile uint32_t indrd; /* ALT_QSPI_INDRD */ + volatile uint32_t indrdwater; /* ALT_QSPI_INDRDWATER */ + volatile uint32_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */ + volatile uint32_t indrdcnt; /* ALT_QSPI_INDRDCNT */ + volatile uint32_t indwr; /* ALT_QSPI_INDWR */ + volatile uint32_t indwrwater; /* ALT_QSPI_INDWRWATER */ + volatile uint32_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */ + volatile uint32_t indwrcnt; /* ALT_QSPI_INDWRCNT */ + volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */ + volatile uint32_t flashcmd; /* ALT_QSPI_FLSHCMD */ + volatile uint32_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */ + volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */ + volatile uint32_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */ + volatile uint32_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */ + volatile uint32_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */ + volatile uint32_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */ + volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */ + volatile uint32_t moduleid; /* ALT_QSPI_MODULEID */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_QSPI. */ +typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_QSPI_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h new file mode 100644 index 0000000000..19383eefe5 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_QSPIDATA */ + +#ifndef __ALTERA_ALT_QSPIDATA_H__ +#define __ALTERA_ALT_QSPIDATA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : QSPI Flash Module Data (AHB Slave) - ALT_QSPIDATA + * QSPI Flash Module Data (AHB Slave) + * + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_QSPIDATA_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h new file mode 100644 index 0000000000..ab4ac65dcb --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h @@ -0,0 +1,3382 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_RSTMGR */ + +#ifndef __ALTERA_ALT_RSTMGR_H__ +#define __ALTERA_ALT_RSTMGR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : Reset Manager Module - ALT_RSTMGR + * Reset Manager Module + * + * Registers in the Reset Manager module + * + */ +/* + * Register : Status Register - stat + * + * The STAT register contains bits that indicate the reset source or a timeout + * event. For reset sources, a field is 1 if its associated reset requester caused + * the reset. For timeout events, a field is 1 if its associated timeout occured as + * part of a hardware sequenced warm/debug reset. + * + * Software clears bits by writing them with a value of 1. Writes to bits with a + * value of 0 are ignored. + * + * After a cold reset is complete, all bits are reset to their reset value except + * for the bit(s) that indicate the source of the cold reset. If multiple cold + * reset requests overlap with each other, the source de-asserts the request last + * will be logged. The other reset request source(s) de-assert the request in the + * same cycle will also be logged, the rest of the fields are reset to default + * value of 0. + * + * After a warm reset is complete, the bit(s) that indicate the source of the warm + * reset are set to 1. A warm reset doesn't clear any of the bits in the STAT + * register; these bits must be cleared by software writing the STAT register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------- + * [0] | RW | 0x0 | Power-On Voltage Detector Cold Reset + * [1] | RW | 0x0 | nPOR Pin Cold Reset + * [2] | RW | 0x0 | FPGA Core Cold Reset + * [3] | RW | 0x0 | CONFIG_IO Cold Reset + * [4] | RW | 0x0 | Software Cold Reset + * [7:5] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | nRST Pin Warm Reset + * [9] | RW | 0x0 | FPGA Core Warm Reset + * [10] | RW | 0x0 | Software Warm Reset + * [11] | ??? | 0x0 | *UNDEFINED* + * [12] | RW | 0x0 | MPU Watchdog 0 Warm Reset + * [13] | RW | 0x0 | MPU Watchdog 1 Warm Reset + * [14] | RW | 0x0 | L4 Watchdog 0 Warm Reset + * [15] | RW | 0x0 | L4 Watchdog 1 Warm Reset + * [17:16] | ??? | 0x0 | *UNDEFINED* + * [18] | RW | 0x0 | FPGA Core Debug Reset + * [19] | RW | 0x0 | DAP Debug Reset + * [23:20] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | SDRAM Self-Refresh Timeout + * [25] | RW | 0x0 | FPGA manager handshake Timeout + * [26] | RW | 0x0 | SCAN manager handshake Timeout + * [27] | RW | 0x0 | FPGA handshake Timeout + * [28] | RW | 0x0 | ETR Stall Timeout + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Power-On Voltage Detector Cold Reset - porvoltrst + * + * Built-in POR voltage detector triggered a cold reset (por_voltage_req = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_MSB 0 +/* The width in bits of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_PORVOLTRST register field value. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_STAT_PORVOLTRST register field value. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_PORVOLTRST field value from a register. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_STAT_PORVOLTRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : nPOR Pin Cold Reset - nporpinrst + * + * nPOR pin triggered a cold reset (por_pin_req = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */ +#define ALT_RSTMGR_STAT_NPORPINRST_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */ +#define ALT_RSTMGR_STAT_NPORPINRST_MSB 1 +/* The width in bits of the ALT_RSTMGR_STAT_NPORPINRST register field. */ +#define ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_NPORPINRST register field value. */ +#define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_STAT_NPORPINRST register field value. */ +#define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_STAT_NPORPINRST register field. */ +#define ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_NPORPINRST field value from a register. */ +#define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_STAT_NPORPINRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : FPGA Core Cold Reset - fpgacoldrst + * + * FPGA core triggered a cold reset (f2h_cold_rst_req_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_MSB 2 +/* The width in bits of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGACOLDRST field value from a register. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_STAT_FPGACOLDRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : CONFIG_IO Cold Reset - configiocoldrst + * + * FPGA entered CONFIG_IO mode and a triggered a cold reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 3 +/* The width in bits of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_CFGIOCOLDRST field value from a register. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_STAT_CFGIOCOLDRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Software Cold Reset - swcoldrst + * + * Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_MSB 4 +/* The width in bits of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_SWCOLDRST register field value. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_STAT_SWCOLDRST register field value. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_SWCOLDRST field value from a register. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_STAT_SWCOLDRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : nRST Pin Warm Reset - nrstpinrst + * + * nRST pin triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_MSB 8 +/* The width in bits of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_NRSTPINRST register field value. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100 +/* The mask used to clear the ALT_RSTMGR_STAT_NRSTPINRST register field value. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff +/* The reset value of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_NRSTPINRST field value from a register. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_RSTMGR_STAT_NRSTPINRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : FPGA Core Warm Reset - fpgawarmrst + * + * FPGA core triggered a hardware sequenced warm reset (f2h_warm_rst_req_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9 +/* The width in bits of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff +/* The reset value of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGAWARMRST field value from a register. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_RSTMGR_STAT_FPGAWARMRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Software Warm Reset - swwarmrst + * + * Software wrote CTRL.SWWARMRSTREQ to 1 and triggered a hardware sequenced warm + * reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */ +#define ALT_RSTMGR_STAT_SWWARMRST_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */ +#define ALT_RSTMGR_STAT_SWWARMRST_MSB 10 +/* The width in bits of the ALT_RSTMGR_STAT_SWWARMRST register field. */ +#define ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_SWWARMRST register field value. */ +#define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400 +/* The mask used to clear the ALT_RSTMGR_STAT_SWWARMRST register field value. */ +#define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff +/* The reset value of the ALT_RSTMGR_STAT_SWWARMRST register field. */ +#define ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_SWWARMRST field value from a register. */ +#define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_RSTMGR_STAT_SWWARMRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MPU Watchdog 0 Warm Reset - mpuwd0rst + * + * MPU Watchdog 0 triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_MSB 12 +/* The width in bits of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_MPUWD0RST register field value. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD0RST register field value. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xffffefff +/* The reset value of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_MPUWD0RST field value from a register. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_RSTMGR_STAT_MPUWD0RST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MPU Watchdog 1 Warm Reset - mpuwd1rst + * + * MPU Watchdog 1 triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_MSB 13 +/* The width in bits of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_MPUWD1RST register field value. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00002000 +/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD1RST register field value. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffdfff +/* The reset value of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_MPUWD1RST field value from a register. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_RSTMGR_STAT_MPUWD1RST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : L4 Watchdog 0 Warm Reset - l4wd0rst + * + * L4 Watchdog 0 triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */ +#define ALT_RSTMGR_STAT_L4WD0RST_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */ +#define ALT_RSTMGR_STAT_L4WD0RST_MSB 14 +/* The width in bits of the ALT_RSTMGR_STAT_L4WD0RST register field. */ +#define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_L4WD0RST register field value. */ +#define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00004000 +/* The mask used to clear the ALT_RSTMGR_STAT_L4WD0RST register field value. */ +#define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffbfff +/* The reset value of the ALT_RSTMGR_STAT_L4WD0RST register field. */ +#define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_L4WD0RST field value from a register. */ +#define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_RSTMGR_STAT_L4WD0RST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : L4 Watchdog 1 Warm Reset - l4wd1rst + * + * L4 Watchdog 1 triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */ +#define ALT_RSTMGR_STAT_L4WD1RST_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */ +#define ALT_RSTMGR_STAT_L4WD1RST_MSB 15 +/* The width in bits of the ALT_RSTMGR_STAT_L4WD1RST register field. */ +#define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_L4WD1RST register field value. */ +#define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00008000 +/* The mask used to clear the ALT_RSTMGR_STAT_L4WD1RST register field value. */ +#define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffff7fff +/* The reset value of the ALT_RSTMGR_STAT_L4WD1RST register field. */ +#define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_L4WD1RST field value from a register. */ +#define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_RSTMGR_STAT_L4WD1RST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : FPGA Core Debug Reset - fpgadbgrst + * + * FPGA triggered debug reset (f2h_dbg_rst_req_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_MSB 18 +/* The width in bits of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGADBGRST register field value. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00040000 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGADBGRST register field value. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffbffff +/* The reset value of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGADBGRST field value from a register. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_RSTMGR_STAT_FPGADBGRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : DAP Debug Reset - cdbgreqrst + * + * DAP triggered debug reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_MSB 19 +/* The width in bits of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_CDBGREQRST register field value. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00080000 +/* The mask used to clear the ALT_RSTMGR_STAT_CDBGREQRST register field value. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_CDBGREQRST field value from a register. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_RSTMGR_STAT_CDBGREQRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : SDRAM Self-Refresh Timeout - sdrselfreftimeout + * + * A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to + * put the SDRAM devices into self-refresh mode before starting a hardware + * sequenced warm reset timed-out and the Reset Manager had to proceed with the + * warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB 24 +/* The width in bits of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK 0x01000000 +/* The mask used to clear the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK 0xfeffffff +/* The reset value of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_SDRSELFREFTMO field value from a register. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_RSTMGR_STAT_SDRSELFREFTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : FPGA manager handshake Timeout - fpgamgrhstimeout + * + * A 1 indicates that Reset Manager's request to the FPGA manager to stop driving + * configuration clock to FPGA CB before starting a hardware sequenced warm reset + * timed-out and the Reset Manager had to proceed with the warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB 25 +/* The width in bits of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK 0x02000000 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK 0xfdffffff +/* The reset value of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGAMGRHSTMO field value from a register. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : SCAN manager handshake Timeout - scanhstimeout + * + * A 1 indicates that Reset Manager's request to the SCAN manager to stop driving + * JTAG clock to FPGA CB before starting a hardware sequenced warm reset timed-out + * and the Reset Manager had to proceed with the warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_MSB 26 +/* The width in bits of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_SCANHSTMO register field value. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK 0x04000000 +/* The mask used to clear the ALT_RSTMGR_STAT_SCANHSTMO register field value. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK 0xfbffffff +/* The reset value of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_SCANHSTMO field value from a register. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_RSTMGR_STAT_SCANHSTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : FPGA handshake Timeout - fpgahstimeout + * + * A 1 indicates that Reset Manager's handshake request to FPGA before starting a + * hardware sequenced warm reset timed-out and the Reset Manager had to proceed + * with the warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_MSB 27 +/* The width in bits of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK 0x08000000 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGAHSTMO field value from a register. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_RSTMGR_STAT_FPGAHSTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : ETR Stall Timeout - etrstalltimeout + * + * A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to + * stall its AXI master port before starting a hardware sequenced warm reset timed- + * out and the Reset Manager had to proceed with the warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_MSB 28 +/* The width in bits of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK 0x10000000 +/* The mask used to clear the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK 0xefffffff +/* The reset value of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_ETRSTALLTMO field value from a register. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_RSTMGR_STAT_ETRSTALLTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET(value) (((value) << 28) & 0x10000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_STAT. + */ +struct ALT_RSTMGR_STAT_s +{ + uint32_t porvoltrst : 1; /* Power-On Voltage Detector Cold Reset */ + uint32_t nporpinrst : 1; /* nPOR Pin Cold Reset */ + uint32_t fpgacoldrst : 1; /* FPGA Core Cold Reset */ + uint32_t configiocoldrst : 1; /* CONFIG_IO Cold Reset */ + uint32_t swcoldrst : 1; /* Software Cold Reset */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t nrstpinrst : 1; /* nRST Pin Warm Reset */ + uint32_t fpgawarmrst : 1; /* FPGA Core Warm Reset */ + uint32_t swwarmrst : 1; /* Software Warm Reset */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t mpuwd0rst : 1; /* MPU Watchdog 0 Warm Reset */ + uint32_t mpuwd1rst : 1; /* MPU Watchdog 1 Warm Reset */ + uint32_t l4wd0rst : 1; /* L4 Watchdog 0 Warm Reset */ + uint32_t l4wd1rst : 1; /* L4 Watchdog 1 Warm Reset */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t fpgadbgrst : 1; /* FPGA Core Debug Reset */ + uint32_t cdbgreqrst : 1; /* DAP Debug Reset */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t sdrselfreftimeout : 1; /* SDRAM Self-Refresh Timeout */ + uint32_t fpgamgrhstimeout : 1; /* FPGA manager handshake Timeout */ + uint32_t scanhstimeout : 1; /* SCAN manager handshake Timeout */ + uint32_t fpgahstimeout : 1; /* FPGA handshake Timeout */ + uint32_t etrstalltimeout : 1; /* ETR Stall Timeout */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_STAT. */ +typedef volatile struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_STAT register from the beginning of the component. */ +#define ALT_RSTMGR_STAT_OFST 0x0 + +/* + * Register : Control Register - ctrl + * + * The CTRL register is used by software to control reset behavior.It includes + * fields for software to initiate the cold and warm reset, enable hardware + * handshake with other modules before warm reset, and perform software handshake. + * The software handshake sequence must match the hardware sequence. Software + * mustde-assert the handshake request after asserting warm reset and before de- + * assert the warm reset. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------------------------- + * [0] | RW | 0x0 | Software Cold Reset Request + * [1] | RW | 0x0 | Software Warm Reset Request + * [3:2] | ??? | 0x0 | *UNDEFINED* + * [4] | RW | 0x0 | SDRAM Self-Refresh Enable + * [5] | RW | 0x0 | SDRAM Self-Refresh Request + * [6] | R | 0x0 | SDRAM Self-Refresh Acknowledge + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | FPGA Manager Handshake Enable + * [9] | RW | 0x0 | FPGA Manager Handshake Request + * [10] | R | Unknown | FPGA Manager Handshake Acknowledge + * [11] | ??? | 0x0 | *UNDEFINED* + * [12] | RW | 0x0 | SCAN Manager Handshake Enable + * [13] | RW | 0x0 | SCAN Manager Handshake Request + * [14] | R | Unknown | SCAN Manager Handshake Acknowledge + * [15] | ??? | 0x0 | *UNDEFINED* + * [16] | RW | 0x0 | FPGA Handshake Enable + * [17] | RW | 0x0 | FPGA Handshake Request + * [18] | R | Unknown | FPGA Handshake Acknowledge + * [19] | ??? | 0x0 | *UNDEFINED* + * [20] | RW | 0x1 | ETR (Embedded Trace Router) Stall Enable + * [21] | RW | 0x0 | ETR (Embedded Trace Router) Stall Request + * [22] | R | 0x0 | ETR (Embedded Trace Router) Stall Acknowledge + * [23] | RW | 0x0 | ETR (Embedded Trace Router) Stall After Warm Reset + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Software Cold Reset Request - swcoldrstreq + * + * This is a one-shot bit written by software to 1 to trigger a cold reset. It + * always reads the value 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0 +/* The width in bits of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SWCOLDRSTREQ field value from a register. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Software Warm Reset Request - swwarmrstreq + * + * This is a one-shot bit written by software to 1 to trigger a hardware sequenced + * warm reset. It always reads the value 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1 +/* The width in bits of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SWWARMRSTREQ field value from a register. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_CTL_SWWARMRSTREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDRAM Self-Refresh Enable - sdrselfrefen + * + * This field controls whether the contents of SDRAM devices survive a hardware + * sequenced warm reset. If set to 1, the Reset Manager makes a request to the + * SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode + * before asserting warm reset signals. However, if SDRAM is already in warm reset, + * Handshake with SDRAM is not performed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_MSB 4 +/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFEN field value from a register. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_CTL_SDRSELFREFEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : SDRAM Self-Refresh Request - sdrselfrefreq + * + * Software writes this field 1 to request to the SDRAM Controller Subsystem that + * it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM + * contents across a software warm reset. + * + * Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0. + * Note that it is possible for the SDRAM Controller Subsystem to never assert + * SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB 5 +/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFREQ field value from a register. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_RSTMGR_CTL_SDRSELFREFREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : SDRAM Self-Refresh Acknowledge - sdrselfreqack + * + * This is the acknowlege for a SDRAM self-refresh mode request initiated by the + * SDRSELFREFREQ field. A 1 indicates that the SDRAM Controller Subsystem has put + * the SDRAM devices into self-refresh mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_MSB 6 +/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SDRSELFREQACK field value from a register. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_RSTMGR_CTL_SDRSELFREQACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : FPGA Manager Handshake Enable - fpgamgrhsen + * + * Enables a handshake between the Reset Manager and FPGA Manager before a warm + * reset. The handshake is used to warn the FPGA Manager that a warm reset it + * coming so it can prepare for it. When the FPGA Manager receives a warm reset + * handshake, the FPGA Manager drives its output clock to a quiescent state to + * avoid glitches. + * + * If set to 1, the Manager makes a request to the FPGA Managerbefore asserting + * warm reset signals. However if the FPGA Manager is already in warm reset, the + * handshake is skipped. + * + * If set to 0, the handshake is skipped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB 8 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSEN field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : FPGA Manager Handshake Request - fpgamgrhsreq + * + * Software writes this field 1 to request to the FPGA Manager to idle its output + * clock. + * + * Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0. + * Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so + * software should timeout in this case. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB 9 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK 0x00000200 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK 0xfffffdff +/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSREQ field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : FPGA Manager Handshake Acknowledge - fpgamgrhsack + * + * This is the acknowlege (high active) that the FPGA manager has successfully + * idled its output clock. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB 10 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field is UNKNOWN. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSACK field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : SCAN Manager Handshake Enable - scanmgrhsen + * + * Enables a handshake between the Reset Manager and Scan Manager before a warm + * reset. The handshake is used to warn the Scan Manager that a warm reset it + * coming so it can prepare for it. When the Scan Manager receives a warm reset + * handshake, the Scan Manager drives its output clocks to a quiescent state to + * avoid glitches. + * + * If set to 1, the Reset Manager makes a request to the Scan Managerbefore + * asserting warm reset signals. However if the Scan Manager is already in warm + * reset, the handshake is skipped. + * + * If set to 0, the handshake is skipped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_MSB 12 +/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK 0x00001000 +/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK 0xffffefff +/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSEN field value from a register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_RSTMGR_CTL_SCANMGRHSEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : SCAN Manager Handshake Request - scanmgrhsreq + * + * Software writes this field 1 to request to the SCAN manager to idle its output + * clocks. + * + * Software waits for the SCANMGRHSACK to be 1 and then writes this field to 0. + * Note that it is possible for the Scan Manager to never assert SCANMGRHSACK (e.g. + * its input clock is disabled) so software should timeout in this case. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB 13 +/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK 0x00002000 +/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK 0xffffdfff +/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSREQ field value from a register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_RSTMGR_CTL_SCANMGRHSREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : SCAN Manager Handshake Acknowledge - scanmgrhsack + * + * This is the acknowlege (high active) that the SCAN manager has successfully + * idled its output clocks. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_MSB 14 +/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK 0x00004000 +/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK 0xffffbfff +/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSACK register field is UNKNOWN. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSACK field value from a register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_RSTMGR_CTL_SCANMGRHSACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : FPGA Handshake Enable - fpgahsen + * + * This field controls whether to perform handshake with FPGA before asserting warm + * reset. + * + * If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm + * reset signals. However if FPGA is already in warm reset state, the handshake is + * not performed. + * + * If set to 0, the handshake is not performed + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_MSB 16 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSEN register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK 0x00010000 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSEN register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK 0xfffeffff +/* The reset value of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAHSEN field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_RSTMGR_CTL_FPGAHSEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : FPGA Handshake Request - fpgahsreq + * + * Software writes this field 1 to initiate handshake request to FPGA . + * + * Software waits for the FPGAHSACK to be active and then writes this field to 0. + * Note that it is possible for the FPGA to never assert FPGAHSACK so software + * should timeout in this case. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_MSB 17 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK 0x00020000 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK 0xfffdffff +/* The reset value of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAHSREQ field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_RSTMGR_CTL_FPGAHSREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : FPGA Handshake Acknowledge - fpgahsack + * + * This is the acknowlege (high active) that the FPGA handshake acknowledge has + * been received by Reset Manager. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_MSB 18 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSACK register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK 0x00040000 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSACK register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK 0xfffbffff +/* The reset value of the ALT_RSTMGR_CTL_FPGAHSACK register field is UNKNOWN. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAHSACK field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_RSTMGR_CTL_FPGAHSACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : ETR (Embedded Trace Router) Stall Enable - etrstallen + * + * This field controls whether the ETR is requested to idle its AXI master + * interface (i.e. finish outstanding transactions and not initiate any more) to + * the L3 Interconnect before a warm or debug reset. If set to 1, the Reset Manager + * makes a request to the ETR to stall its AXI master and waits for it to finish + * any outstanding AXI transactions before a warm reset of the L3 Interconnect or a + * debug reset of the ETR. This stalling is required because the debug logic + * (including the ETR) is reset on a debug reset and the ETR AXI master is + * connected to the L3 Interconnect which is reset on a warm reset and these resets + * can happen independently. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_MSB 20 +/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK 0x00100000 +/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK 0xffefffff +/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_RESET 0x1 +/* Extracts the ALT_RSTMGR_CTL_ETRSTALLEN field value from a register. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_RSTMGR_CTL_ETRSTALLEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : ETR (Embedded Trace Router) Stall Request - etrstallreq + * + * Software writes this field 1 to request to the ETR that it stalls its AXI master + * to the L3 Interconnect. + * + * Software waits for the ETRSTALLACK to be 1 and then writes this field to 0. + * Note that it is possible for the ETR to never assert ETRSTALLACK so software + * should timeout if ETRSTALLACK is never asserted. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_MSB 21 +/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK 0x00200000 +/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK 0xffdfffff +/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_ETRSTALLREQ field value from a register. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_RSTMGR_CTL_ETRSTALLREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : ETR (Embedded Trace Router) Stall Acknowledge - etrstallack + * + * This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ + * field. A 1 indicates that the ETR has stalled its AXI master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_MSB 22 +/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK 0x00400000 +/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK 0xffbfffff +/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_ETRSTALLACK field value from a register. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_RSTMGR_CTL_ETRSTALLACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : ETR (Embedded Trace Router) Stall After Warm Reset - etrstallwarmrst + * + * If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to + * indicate that the stall of the ETR AXI master is pending. Hardware leaves the + * ETR stalled until software clears this field by writing it with 1. Software must + * only clear this field when it is ready to have the ETR AXI master start making + * AXI requests to write trace data. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB 23 +/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK 0x00800000 +/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK 0xff7fffff +/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_ETRSTALLWARMRST field value from a register. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET(value) (((value) << 23) & 0x00800000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_CTL. + */ +struct ALT_RSTMGR_CTL_s +{ + uint32_t swcoldrstreq : 1; /* Software Cold Reset Request */ + uint32_t swwarmrstreq : 1; /* Software Warm Reset Request */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t sdrselfrefen : 1; /* SDRAM Self-Refresh Enable */ + uint32_t sdrselfrefreq : 1; /* SDRAM Self-Refresh Request */ + const uint32_t sdrselfreqack : 1; /* SDRAM Self-Refresh Acknowledge */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t fpgamgrhsen : 1; /* FPGA Manager Handshake Enable */ + uint32_t fpgamgrhsreq : 1; /* FPGA Manager Handshake Request */ + const uint32_t fpgamgrhsack : 1; /* FPGA Manager Handshake Acknowledge */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t scanmgrhsen : 1; /* SCAN Manager Handshake Enable */ + uint32_t scanmgrhsreq : 1; /* SCAN Manager Handshake Request */ + const uint32_t scanmgrhsack : 1; /* SCAN Manager Handshake Acknowledge */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t fpgahsen : 1; /* FPGA Handshake Enable */ + uint32_t fpgahsreq : 1; /* FPGA Handshake Request */ + const uint32_t fpgahsack : 1; /* FPGA Handshake Acknowledge */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t etrstallen : 1; /* ETR (Embedded Trace Router) Stall Enable */ + uint32_t etrstallreq : 1; /* ETR (Embedded Trace Router) Stall Request */ + const uint32_t etrstallack : 1; /* ETR (Embedded Trace Router) Stall Acknowledge */ + uint32_t etrstallwarmrst : 1; /* ETR (Embedded Trace Router) Stall After Warm Reset */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_CTL. */ +typedef volatile struct ALT_RSTMGR_CTL_s ALT_RSTMGR_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_CTL register from the beginning of the component. */ +#define ALT_RSTMGR_CTL_OFST 0x4 + +/* + * Register : Reset Cycles Count Register - counts + * + * The COUNTS register is used by software to control reset behavior.It includes + * fields for software to control the behavior of the warm reset and nRST pin. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------- + * [7:0] | RW | 0x80 | Warm reset release delay count + * [27:8] | RW | 0x800 | nRST Pin Count + * [31:28] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Warm reset release delay count - warmrstcycles + * + * On a warm reset, the Reset Manager releases the reset to the Clock Manager, and + * then waits for the number of cycles specified in this register before releasing + * the rest of the hardware controlled resets. Value must be greater than 16. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 7 +/* The width in bits of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8 +/* The mask used to set the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0x000000ff +/* The mask used to clear the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0xffffff00 +/* The reset value of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80 +/* Extracts the ALT_RSTMGR_COUNTS_WARMRSTCYCLES field value from a register. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value suitable for setting the register. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : nRST Pin Count - nrstcnt + * + * The Reset Manager pulls down the nRST pin on a warm reset for the number of + * cycles specified in this register. A value of 0x0 prevents the Reset Manager + * from pulling down the nRST pin. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 27 +/* The width in bits of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20 +/* The mask used to set the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x0fffff00 +/* The mask used to clear the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xf00000ff +/* The reset value of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800 +/* Extracts the ALT_RSTMGR_COUNTS_NRSTCNT field value from a register. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x0fffff00) >> 8) +/* Produces a ALT_RSTMGR_COUNTS_NRSTCNT register field value suitable for setting the register. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 8) & 0x0fffff00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_COUNTS. + */ +struct ALT_RSTMGR_COUNTS_s +{ + uint32_t warmrstcycles : 8; /* Warm reset release delay count */ + uint32_t nrstcnt : 20; /* nRST Pin Count */ + uint32_t : 4; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_COUNTS. */ +typedef volatile struct ALT_RSTMGR_COUNTS_s ALT_RSTMGR_COUNTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_COUNTS register from the beginning of the component. */ +#define ALT_RSTMGR_COUNTS_OFST 0x8 + +/* + * Register : MPU Module Reset Register - mpumodrst + * + * The MPUMODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields except CPU1 are only reset by a cold reset. The CPU1 field is reset + * by a cold reset. The CPU1 field is also reset by a warm reset if not masked by + * the corresponding MPUWARMMASK field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [0] | RW | 0x0 | CPU0 + * [1] | RW | 0x1 | CPU1 + * [2] | RW | 0x0 | Watchdogs + * [3] | RW | 0x0 | SCU/Peripherals + * [4] | RW | 0x0 | L2 + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : CPU0 - cpu0 + * + * Resets Cortex-A9 CPU0 in MPU. Whe software changes this field from 0 to 1, + * ittriggers the following sequence: 1. CPU0 reset is asserted. cpu0 clkoff is + * de-asserted 2. after 32 osc1_clk cycles, cpu0 clkoff is asserted. + * + * When software changes this field from 1 to 0, it triggers the following + * sequence: 1.CPU0 reset is de-asserted. 2. after 32 cycles, cpu0 clkoff is de- + * asserted. + * + * Software needs to wait for at least 64 osc1_clk cycles between each change of + * this field to keep the proper reset/clkoff sequence. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_MSB 0 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0 +/* Extracts the ALT_RSTMGR_MPUMODRST_CPU0 field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_MPUMODRST_CPU0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : CPU1 - cpu1 + * + * Resets Cortex-A9 CPU1 in MPU. + * + * It is reset to 1 on a cold or warm reset. This holds CPU1 in reset until + * software is ready to release CPU1 from reset by writing 0 to this field. + * + * On single-core devices, writes to this field are ignored.On dual-core devices, + * writes to this field trigger the same sequence as writes to the CPU0 field + * (except the sequence is performed on CPU1). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_MSB 1 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1 +/* Extracts the ALT_RSTMGR_MPUMODRST_CPU1 field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_MPUMODRST_CPU1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Watchdogs - wds + * + * Resets both per-CPU Watchdog Reset Status registers in MPU. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */ +#define ALT_RSTMGR_MPUMODRST_WDS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */ +#define ALT_RSTMGR_MPUMODRST_WDS_MSB 2 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_WDS register field. */ +#define ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_WDS register field value. */ +#define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_WDS register field value. */ +#define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_MPUMODRST_WDS register field. */ +#define ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0 +/* Extracts the ALT_RSTMGR_MPUMODRST_WDS field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_MPUMODRST_WDS register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SCU/Peripherals - scuper + * + * Resets SCU and peripherals. Peripherals consist of the interrupt controller, + * global timer, both per-CPU private timers, and both per-CPU watchdogs (except + * for the Watchdog Reset Status registers). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0 +/* Extracts the ALT_RSTMGR_MPUMODRST_SCUPER field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_MPUMODRST_SCUPER register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : L2 - l2 + * + * Resets L2 cache controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */ +#define ALT_RSTMGR_MPUMODRST_L2_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */ +#define ALT_RSTMGR_MPUMODRST_L2_MSB 4 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_L2 register field. */ +#define ALT_RSTMGR_MPUMODRST_L2_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_L2 register field value. */ +#define ALT_RSTMGR_MPUMODRST_L2_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_L2 register field value. */ +#define ALT_RSTMGR_MPUMODRST_L2_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_MPUMODRST_L2 register field. */ +#define ALT_RSTMGR_MPUMODRST_L2_RESET 0x0 +/* Extracts the ALT_RSTMGR_MPUMODRST_L2 field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_L2_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_MPUMODRST_L2 register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_L2_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_MPUMODRST. + */ +struct ALT_RSTMGR_MPUMODRST_s +{ + uint32_t cpu0 : 1; /* CPU0 */ + uint32_t cpu1 : 1; /* CPU1 */ + uint32_t wds : 1; /* Watchdogs */ + uint32_t scuper : 1; /* SCU/Peripherals */ + uint32_t l2 : 1; /* L2 */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_MPUMODRST. */ +typedef volatile struct ALT_RSTMGR_MPUMODRST_s ALT_RSTMGR_MPUMODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_MPUMODRST register from the beginning of the component. */ +#define ALT_RSTMGR_MPUMODRST_OFST 0x10 + +/* + * Register : Peripheral Module Reset Register - permodrst + * + * The PERMODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields are reset by a cold reset.All fields are also reset by a warm reset + * if not masked by the corresponding PERWARMMASK field. + * + * The reset value of all fields is 1. This holds the corresponding module in reset + * until software is ready to release the module from reset by writing 0 to its + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | RW | 0x1 | EMAC0 + * [1] | RW | 0x1 | EMAC1 + * [2] | RW | 0x1 | USB0 + * [3] | RW | 0x1 | USB1 + * [4] | RW | 0x1 | NAND Flash + * [5] | RW | 0x1 | QSPI Flash + * [6] | RW | 0x1 | L4 Watchdog 0 + * [7] | RW | 0x1 | L4 Watchdog 1 + * [8] | RW | 0x1 | OSC1 Timer 0 + * [9] | RW | 0x1 | OSC1 Timer 1 + * [10] | RW | 0x1 | SP Timer 0 + * [11] | RW | 0x1 | SP Timer 1 + * [12] | RW | 0x1 | I2C0 + * [13] | RW | 0x1 | I2C1 + * [14] | RW | 0x1 | I2C2 + * [15] | RW | 0x1 | I2C3 + * [16] | RW | 0x1 | UART0 + * [17] | RW | 0x1 | UART1 + * [18] | RW | 0x1 | SPIM0 + * [19] | RW | 0x1 | SPIM1 + * [20] | RW | 0x1 | SPIS0 + * [21] | RW | 0x1 | SPIS1 + * [22] | RW | 0x1 | SD/MMC + * [23] | RW | 0x1 | CAN0 + * [24] | RW | 0x1 | CAN1 + * [25] | RW | 0x1 | GPIO0 + * [26] | RW | 0x1 | GPIO1 + * [27] | RW | 0x1 | GPIO2 + * [28] | RW | 0x1 | DMA Controller + * [29] | RW | 0x1 | SDRAM Controller Subsystem + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC0 - emac0 + * + * Resets EMAC0 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_MSB 0 +/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_EMAC0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_PERMODRST_EMAC0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : EMAC1 - emac1 + * + * Resets EMAC1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_MSB 1 +/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_EMAC1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_PERMODRST_EMAC1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : USB0 - usb0 + * + * Resets USB0 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */ +#define ALT_RSTMGR_PERMODRST_USB0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */ +#define ALT_RSTMGR_PERMODRST_USB0_MSB 2 +/* The width in bits of the ALT_RSTMGR_PERMODRST_USB0 register field. */ +#define ALT_RSTMGR_PERMODRST_USB0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_USB0 register field value. */ +#define ALT_RSTMGR_PERMODRST_USB0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB0 register field value. */ +#define ALT_RSTMGR_PERMODRST_USB0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_PERMODRST_USB0 register field. */ +#define ALT_RSTMGR_PERMODRST_USB0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_USB0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_USB0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_PERMODRST_USB0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_USB0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : USB1 - usb1 + * + * Resets USB1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */ +#define ALT_RSTMGR_PERMODRST_USB1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */ +#define ALT_RSTMGR_PERMODRST_USB1_MSB 3 +/* The width in bits of the ALT_RSTMGR_PERMODRST_USB1 register field. */ +#define ALT_RSTMGR_PERMODRST_USB1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_USB1 register field value. */ +#define ALT_RSTMGR_PERMODRST_USB1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB1 register field value. */ +#define ALT_RSTMGR_PERMODRST_USB1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_PERMODRST_USB1 register field. */ +#define ALT_RSTMGR_PERMODRST_USB1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_USB1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_USB1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_PERMODRST_USB1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_USB1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAND Flash - nand + * + * Resets NAND flash controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */ +#define ALT_RSTMGR_PERMODRST_NAND_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */ +#define ALT_RSTMGR_PERMODRST_NAND_MSB 4 +/* The width in bits of the ALT_RSTMGR_PERMODRST_NAND register field. */ +#define ALT_RSTMGR_PERMODRST_NAND_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_NAND register field value. */ +#define ALT_RSTMGR_PERMODRST_NAND_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_NAND register field value. */ +#define ALT_RSTMGR_PERMODRST_NAND_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_PERMODRST_NAND register field. */ +#define ALT_RSTMGR_PERMODRST_NAND_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_NAND field value from a register. */ +#define ALT_RSTMGR_PERMODRST_NAND_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_PERMODRST_NAND register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_NAND_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : QSPI Flash - qspi + * + * Resets QSPI flash controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */ +#define ALT_RSTMGR_PERMODRST_QSPI_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */ +#define ALT_RSTMGR_PERMODRST_QSPI_MSB 5 +/* The width in bits of the ALT_RSTMGR_PERMODRST_QSPI register field. */ +#define ALT_RSTMGR_PERMODRST_QSPI_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_QSPI register field value. */ +#define ALT_RSTMGR_PERMODRST_QSPI_SET_MSK 0x00000020 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_QSPI register field value. */ +#define ALT_RSTMGR_PERMODRST_QSPI_CLR_MSK 0xffffffdf +/* The reset value of the ALT_RSTMGR_PERMODRST_QSPI register field. */ +#define ALT_RSTMGR_PERMODRST_QSPI_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_QSPI field value from a register. */ +#define ALT_RSTMGR_PERMODRST_QSPI_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_RSTMGR_PERMODRST_QSPI register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_QSPI_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : L4 Watchdog 0 - l4wd0 + * + * Resets watchdog 0 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_MSB 6 +/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK 0x00000040 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_CLR_MSK 0xffffffbf +/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_L4WD0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_RSTMGR_PERMODRST_L4WD0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : L4 Watchdog 1 - l4wd1 + * + * Resets watchdog 1 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_MSB 7 +/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK 0x00000080 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_CLR_MSK 0xffffff7f +/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_L4WD1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_RSTMGR_PERMODRST_L4WD1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : OSC1 Timer 0 - osc1timer0 + * + * Resets OSC1 timer 0 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_MSB 8 +/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : OSC1 Timer 1 - osc1timer1 + * + * Resets OSC1 timer 1 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_MSB 9 +/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : SP Timer 0 - sptimer0 + * + * Resets SP timer 0 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_MSB 10 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK 0x00000400 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_CLR_MSK 0xfffffbff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_RSTMGR_PERMODRST_SPTMR0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : SP Timer 1 - sptimer1 + * + * Resets SP timer 1 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_MSB 11 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK 0x00000800 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_RSTMGR_PERMODRST_SPTMR1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : I2C0 - i2c0 + * + * Resets I2C0 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C0_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C0_MSB 12 +/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C0 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C0_SET_MSK 0x00001000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C0 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C0_CLR_MSK 0xffffefff +/* The reset value of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_I2C0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_I2C0_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_RSTMGR_PERMODRST_I2C0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_I2C0_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : I2C1 - i2c1 + * + * Resets I2C1 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C1_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C1_MSB 13 +/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C1 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C1_SET_MSK 0x00002000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C1 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C1_CLR_MSK 0xffffdfff +/* The reset value of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_I2C1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_I2C1_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_RSTMGR_PERMODRST_I2C1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_I2C1_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : I2C2 - i2c2 + * + * Resets I2C2 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C2_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C2_MSB 14 +/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C2_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C2 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C2_SET_MSK 0x00004000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C2 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C2_CLR_MSK 0xffffbfff +/* The reset value of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C2_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_I2C2 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_I2C2_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_RSTMGR_PERMODRST_I2C2 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_I2C2_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : I2C3 - i2c3 + * + * Resets I2C3 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C3_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C3_MSB 15 +/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C3_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C3 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C3_SET_MSK 0x00008000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C3 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C3_CLR_MSK 0xffff7fff +/* The reset value of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C3_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_I2C3 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_I2C3_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_RSTMGR_PERMODRST_I2C3 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_I2C3_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : UART0 - uart0 + * + * Resets UART0 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */ +#define ALT_RSTMGR_PERMODRST_UART0_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */ +#define ALT_RSTMGR_PERMODRST_UART0_MSB 16 +/* The width in bits of the ALT_RSTMGR_PERMODRST_UART0 register field. */ +#define ALT_RSTMGR_PERMODRST_UART0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_UART0 register field value. */ +#define ALT_RSTMGR_PERMODRST_UART0_SET_MSK 0x00010000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART0 register field value. */ +#define ALT_RSTMGR_PERMODRST_UART0_CLR_MSK 0xfffeffff +/* The reset value of the ALT_RSTMGR_PERMODRST_UART0 register field. */ +#define ALT_RSTMGR_PERMODRST_UART0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_UART0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_UART0_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_RSTMGR_PERMODRST_UART0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_UART0_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : UART1 - uart1 + * + * Resets UART1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */ +#define ALT_RSTMGR_PERMODRST_UART1_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */ +#define ALT_RSTMGR_PERMODRST_UART1_MSB 17 +/* The width in bits of the ALT_RSTMGR_PERMODRST_UART1 register field. */ +#define ALT_RSTMGR_PERMODRST_UART1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_UART1 register field value. */ +#define ALT_RSTMGR_PERMODRST_UART1_SET_MSK 0x00020000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART1 register field value. */ +#define ALT_RSTMGR_PERMODRST_UART1_CLR_MSK 0xfffdffff +/* The reset value of the ALT_RSTMGR_PERMODRST_UART1 register field. */ +#define ALT_RSTMGR_PERMODRST_UART1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_UART1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_UART1_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_RSTMGR_PERMODRST_UART1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_UART1_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : SPIM0 - spim0 + * + * Resets SPIM0 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_MSB 18 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK 0x00040000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_CLR_MSK 0xfffbffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPIM0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_RSTMGR_PERMODRST_SPIM0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : SPIM1 - spim1 + * + * Resets SPIM1 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_MSB 19 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK 0x00080000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPIM1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_RSTMGR_PERMODRST_SPIM1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : SPIS0 - spis0 + * + * Resets SPIS0 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_MSB 20 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK 0x00100000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_CLR_MSK 0xffefffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPIS0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_RSTMGR_PERMODRST_SPIS0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : SPIS1 - spis1 + * + * Resets SPIS1 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_MSB 21 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK 0x00200000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_CLR_MSK 0xffdfffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPIS1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_RSTMGR_PERMODRST_SPIS1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : SD/MMC - sdmmc + * + * Resets SD/MMC controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_MSB 22 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SDMMC register field value. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK 0x00400000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDMMC register field value. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_CLR_MSK 0xffbfffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SDMMC field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_RSTMGR_PERMODRST_SDMMC register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : CAN0 - can0 + * + * Resets CAN0 controller. + * + * Writes to this field on devices not containing CAN controllers will be ignored. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN0_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN0_MSB 23 +/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN0 register field value. */ +#define ALT_RSTMGR_PERMODRST_CAN0_SET_MSK 0x00800000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN0 register field value. */ +#define ALT_RSTMGR_PERMODRST_CAN0_CLR_MSK 0xff7fffff +/* The reset value of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_CAN0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_CAN0_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_RSTMGR_PERMODRST_CAN0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_CAN0_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : CAN1 - can1 + * + * Resets CAN1 controller. + * + * Writes to this field on devices not containing CAN controllers will be ignored. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN1_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN1_MSB 24 +/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN1 register field value. */ +#define ALT_RSTMGR_PERMODRST_CAN1_SET_MSK 0x01000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN1 register field value. */ +#define ALT_RSTMGR_PERMODRST_CAN1_CLR_MSK 0xfeffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_CAN1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_CAN1_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_RSTMGR_PERMODRST_CAN1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_CAN1_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : GPIO0 - gpio0 + * + * Resets GPIO0 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_MSB 25 +/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK 0x02000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_CLR_MSK 0xfdffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_GPIO0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_RSTMGR_PERMODRST_GPIO0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : GPIO1 - gpio1 + * + * Resets GPIO1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_MSB 26 +/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK 0x04000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_CLR_MSK 0xfbffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_GPIO1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_RSTMGR_PERMODRST_GPIO1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : GPIO2 - gpio2 + * + * Resets GPIO2 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_MSB 27 +/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK 0x08000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_GPIO2 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_RSTMGR_PERMODRST_GPIO2 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : DMA Controller - dma + * + * Resets DMA controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */ +#define ALT_RSTMGR_PERMODRST_DMA_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */ +#define ALT_RSTMGR_PERMODRST_DMA_MSB 28 +/* The width in bits of the ALT_RSTMGR_PERMODRST_DMA register field. */ +#define ALT_RSTMGR_PERMODRST_DMA_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_DMA register field value. */ +#define ALT_RSTMGR_PERMODRST_DMA_SET_MSK 0x10000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_DMA register field value. */ +#define ALT_RSTMGR_PERMODRST_DMA_CLR_MSK 0xefffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_DMA register field. */ +#define ALT_RSTMGR_PERMODRST_DMA_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_DMA field value from a register. */ +#define ALT_RSTMGR_PERMODRST_DMA_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_RSTMGR_PERMODRST_DMA register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_DMA_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : SDRAM Controller Subsystem - sdr + * + * Resets SDRAM Controller Subsystem affected by a warm or cold reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */ +#define ALT_RSTMGR_PERMODRST_SDR_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */ +#define ALT_RSTMGR_PERMODRST_SDR_MSB 29 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SDR register field. */ +#define ALT_RSTMGR_PERMODRST_SDR_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SDR register field value. */ +#define ALT_RSTMGR_PERMODRST_SDR_SET_MSK 0x20000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDR register field value. */ +#define ALT_RSTMGR_PERMODRST_SDR_CLR_MSK 0xdfffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SDR register field. */ +#define ALT_RSTMGR_PERMODRST_SDR_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SDR field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SDR_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_RSTMGR_PERMODRST_SDR register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SDR_SET(value) (((value) << 29) & 0x20000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_PERMODRST. + */ +struct ALT_RSTMGR_PERMODRST_s +{ + uint32_t emac0 : 1; /* EMAC0 */ + uint32_t emac1 : 1; /* EMAC1 */ + uint32_t usb0 : 1; /* USB0 */ + uint32_t usb1 : 1; /* USB1 */ + uint32_t nand : 1; /* NAND Flash */ + uint32_t qspi : 1; /* QSPI Flash */ + uint32_t l4wd0 : 1; /* L4 Watchdog 0 */ + uint32_t l4wd1 : 1; /* L4 Watchdog 1 */ + uint32_t osc1timer0 : 1; /* OSC1 Timer 0 */ + uint32_t osc1timer1 : 1; /* OSC1 Timer 1 */ + uint32_t sptimer0 : 1; /* SP Timer 0 */ + uint32_t sptimer1 : 1; /* SP Timer 1 */ + uint32_t i2c0 : 1; /* I2C0 */ + uint32_t i2c1 : 1; /* I2C1 */ + uint32_t i2c2 : 1; /* I2C2 */ + uint32_t i2c3 : 1; /* I2C3 */ + uint32_t uart0 : 1; /* UART0 */ + uint32_t uart1 : 1; /* UART1 */ + uint32_t spim0 : 1; /* SPIM0 */ + uint32_t spim1 : 1; /* SPIM1 */ + uint32_t spis0 : 1; /* SPIS0 */ + uint32_t spis1 : 1; /* SPIS1 */ + uint32_t sdmmc : 1; /* SD/MMC */ + uint32_t can0 : 1; /* CAN0 */ + uint32_t can1 : 1; /* CAN1 */ + uint32_t gpio0 : 1; /* GPIO0 */ + uint32_t gpio1 : 1; /* GPIO1 */ + uint32_t gpio2 : 1; /* GPIO2 */ + uint32_t dma : 1; /* DMA Controller */ + uint32_t sdr : 1; /* SDRAM Controller Subsystem */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_PERMODRST. */ +typedef volatile struct ALT_RSTMGR_PERMODRST_s ALT_RSTMGR_PERMODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_PERMODRST register from the beginning of the component. */ +#define ALT_RSTMGR_PERMODRST_OFST 0x14 + +/* + * Register : Peripheral 2 Module Reset Register - per2modrst + * + * The PER2MODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields are reset by a cold reset.All fields are also reset by a warm reset + * if not masked by the corresponding PERWARMMASK field. + * + * The reset value of all fields is 1. This holds the corresponding module in reset + * until software is ready to release the module from reset by writing 0 to its + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | RW | 0x1 | FPGA DMA0 + * [1] | RW | 0x1 | FPGA DMA1 + * [2] | RW | 0x1 | FPGA DMA2 + * [3] | RW | 0x1 | FPGA DMA3 + * [4] | RW | 0x1 | FPGA DMA4 + * [5] | RW | 0x1 | FPGA DMA5 + * [6] | RW | 0x1 | FPGA DMA6 + * [7] | RW | 0x1 | FPGA DMA7 + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FPGA DMA0 - dmaif0 + * + * Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_MSB 0 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF0 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : FPGA DMA1 - dmaif1 + * + * Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_MSB 1 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF1 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : FPGA DMA2 - dmaif2 + * + * Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_MSB 2 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF2 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF2 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : FPGA DMA3 - dmaif3 + * + * Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_MSB 3 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF3 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF3 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : FPGA DMA4 - dmaif4 + * + * Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_MSB 4 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF4 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF4 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : FPGA DMA5 - dmaif5 + * + * Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_MSB 5 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF5 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF5 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : FPGA DMA6 - dmaif6 + * + * Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_MSB 6 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF6 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF6 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : FPGA DMA7 - dmaif7 + * + * Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_MSB 7 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF7 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF7 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_PER2MODRST. + */ +struct ALT_RSTMGR_PER2MODRST_s +{ + uint32_t dmaif0 : 1; /* FPGA DMA0 */ + uint32_t dmaif1 : 1; /* FPGA DMA1 */ + uint32_t dmaif2 : 1; /* FPGA DMA2 */ + uint32_t dmaif3 : 1; /* FPGA DMA3 */ + uint32_t dmaif4 : 1; /* FPGA DMA4 */ + uint32_t dmaif5 : 1; /* FPGA DMA5 */ + uint32_t dmaif6 : 1; /* FPGA DMA6 */ + uint32_t dmaif7 : 1; /* FPGA DMA7 */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_PER2MODRST. */ +typedef volatile struct ALT_RSTMGR_PER2MODRST_s ALT_RSTMGR_PER2MODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_PER2MODRST register from the beginning of the component. */ +#define ALT_RSTMGR_PER2MODRST_OFST 0x18 + +/* + * Register : Bridge Module Reset Register - brgmodrst + * + * The BRGMODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields are reset by a cold reset.All fields are also reset by a warm reset + * if not masked by the corresponding BRGWARMMASK field. + * + * The reset value of all fields is 1. This holds the corresponding module in reset + * until software is ready to release the module from reset by writing 0 to its + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [0] | RW | 0x1 | HPS2FPGA Bridge + * [1] | RW | 0x1 | LWHPS2FPGA Bridge + * [2] | RW | 0x1 | FPGA2HPS Bridge + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : HPS2FPGA Bridge - hps2fpga + * + * Resets HPS2FPGA Bridge + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */ +#define ALT_RSTMGR_BRGMODRST_H2F_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */ +#define ALT_RSTMGR_BRGMODRST_H2F_MSB 0 +/* The width in bits of the ALT_RSTMGR_BRGMODRST_H2F register field. */ +#define ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_BRGMODRST_H2F register field value. */ +#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_BRGMODRST_H2F register field value. */ +#define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_BRGMODRST_H2F register field. */ +#define ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1 +/* Extracts the ALT_RSTMGR_BRGMODRST_H2F field value from a register. */ +#define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_BRGMODRST_H2F register field value suitable for setting the register. */ +#define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : LWHPS2FPGA Bridge - lwhps2fpga + * + * Resets LWHPS2FPGA Bridge + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1 +/* The width in bits of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1 +/* Extracts the ALT_RSTMGR_BRGMODRST_LWH2F field value from a register. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_BRGMODRST_LWH2F register field value suitable for setting the register. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : FPGA2HPS Bridge - fpga2hps + * + * Resets FPGA2HPS Bridge + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */ +#define ALT_RSTMGR_BRGMODRST_F2H_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */ +#define ALT_RSTMGR_BRGMODRST_F2H_MSB 2 +/* The width in bits of the ALT_RSTMGR_BRGMODRST_F2H register field. */ +#define ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_BRGMODRST_F2H register field value. */ +#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2H register field value. */ +#define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_BRGMODRST_F2H register field. */ +#define ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1 +/* Extracts the ALT_RSTMGR_BRGMODRST_F2H field value from a register. */ +#define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_BRGMODRST_F2H register field value suitable for setting the register. */ +#define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_BRGMODRST. + */ +struct ALT_RSTMGR_BRGMODRST_s +{ + uint32_t hps2fpga : 1; /* HPS2FPGA Bridge */ + uint32_t lwhps2fpga : 1; /* LWHPS2FPGA Bridge */ + uint32_t fpga2hps : 1; /* FPGA2HPS Bridge */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_BRGMODRST. */ +typedef volatile struct ALT_RSTMGR_BRGMODRST_s ALT_RSTMGR_BRGMODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_BRGMODRST register from the beginning of the component. */ +#define ALT_RSTMGR_BRGMODRST_OFST 0x1c + +/* + * Register : Miscellaneous Module Reset Register - miscmodrst + * + * The MISCMODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields are only reset by a cold reset + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [0] | RW | 0x0 | Boot ROM + * [1] | RW | 0x0 | On-chip RAM + * [2] | RW | 0x0 | System Manager (Cold or Warm) + * [3] | RW | 0x0 | System Manager (Cold-only) + * [4] | RW | 0x0 | FPGA Manager + * [5] | RW | 0x0 | ACP ID Mapper + * [6] | RW | 0x0 | HPS to FPGA Core (Cold or Warm) + * [7] | RW | 0x0 | HPS to FPGA Core (Cold-only) + * [8] | RW | 0x0 | nRST Pin + * [9] | RW | 0x0 | Timestamp + * [10] | RW | 0x0 | Clock Manager + * [11] | RW | 0x0 | Scan Manager + * [12] | RW | 0x0 | Freeze Controller + * [13] | RW | 0x0 | System/Debug + * [14] | RW | 0x0 | Debug + * [15] | RW | 0x0 | TAP Controller + * [16] | RW | 0x0 | SDRAM Controller Subsystem Cold Reset + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Boot ROM - rom + * + * Resets Boot ROM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */ +#define ALT_RSTMGR_MISCMODRST_ROM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */ +#define ALT_RSTMGR_MISCMODRST_ROM_MSB 0 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_ROM register field. */ +#define ALT_RSTMGR_MISCMODRST_ROM_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_ROM register field value. */ +#define ALT_RSTMGR_MISCMODRST_ROM_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ROM register field value. */ +#define ALT_RSTMGR_MISCMODRST_ROM_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_MISCMODRST_ROM register field. */ +#define ALT_RSTMGR_MISCMODRST_ROM_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_ROM field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_MISCMODRST_ROM register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_ROM_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : On-chip RAM - ocram + * + * Resets On-chip RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_MSB 1 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_OCRAM field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_MISCMODRST_OCRAM register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : System Manager (Cold or Warm) - sysmgr + * + * Resets logic in System Manager that doesn't differentiate between cold and warm + * resets + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_MSB 2 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGR field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGR register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : System Manager (Cold-only) - sysmgrcold + * + * Resets logic in System Manager that is only reset by a cold reset (ignores warm + * reset) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_MSB 3 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : FPGA Manager - fpgamgr + * + * Resets FPGA Manager + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_MSB 4 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_FPGAMGR field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_MISCMODRST_FPGAMGR register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACP ID Mapper - acpidmap + * + * Resets ACP ID Mapper + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_MSB 5 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET_MSK 0x00000020 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_CLR_MSK 0xffffffdf +/* The reset value of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_ACPIDMAP field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : HPS to FPGA Core (Cold or Warm) - s2f + * + * Resets logic in FPGA core that doesn't differentiate between HPS cold and warm + * resets (h2f_rst_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */ +#define ALT_RSTMGR_MISCMODRST_S2F_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */ +#define ALT_RSTMGR_MISCMODRST_S2F_MSB 6 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2F register field. */ +#define ALT_RSTMGR_MISCMODRST_S2F_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2F register field value. */ +#define ALT_RSTMGR_MISCMODRST_S2F_SET_MSK 0x00000040 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2F register field value. */ +#define ALT_RSTMGR_MISCMODRST_S2F_CLR_MSK 0xffffffbf +/* The reset value of the ALT_RSTMGR_MISCMODRST_S2F register field. */ +#define ALT_RSTMGR_MISCMODRST_S2F_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_S2F field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_S2F_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_RSTMGR_MISCMODRST_S2F register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_S2F_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : HPS to FPGA Core (Cold-only) - s2fcold + * + * Resets logic in FPGA core that is only reset by a cold reset (ignores warm + * reset) (h2f_cold_rst_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_MSB 7 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_S2FCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_RSTMGR_MISCMODRST_S2FCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : nRST Pin - nrstpin + * + * Pulls nRST pin low + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_MSB 8 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_NRSTPIN field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_RSTMGR_MISCMODRST_NRSTPIN register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Timestamp - timestampcold + * + * Resets debug timestamp to 0 (cold reset only) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_MSB 9 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET_MSK 0x00000200 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_CLR_MSK 0xfffffdff +/* The reset value of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_TSCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_RSTMGR_MISCMODRST_TSCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Clock Manager - clkmgrcold + * + * Resets Clock Manager (cold reset only) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_MSB 10 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET_MSK 0x00000400 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_CLR_MSK 0xfffffbff +/* The reset value of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Scan Manager - scanmgr + * + * Resets Scan Manager + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_MSB 11 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SCANMGR field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_RSTMGR_MISCMODRST_SCANMGR register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Freeze Controller - frzctrlcold + * + * Resets Freeze Controller in System Manager (cold reset only) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_MSB 12 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET_MSK 0x00001000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_CLR_MSK 0xffffefff +/* The reset value of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : System/Debug - sysdbg + * + * Resets logic that spans the system and debug domains. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_MSB 13 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_SET_MSK 0x00002000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_CLR_MSK 0xffffdfff +/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SYSDBG field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_RSTMGR_MISCMODRST_SYSDBG register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Debug - dbg + * + * Resets logic located only in the debug domain. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */ +#define ALT_RSTMGR_MISCMODRST_DBG_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */ +#define ALT_RSTMGR_MISCMODRST_DBG_MSB 14 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_DBG register field. */ +#define ALT_RSTMGR_MISCMODRST_DBG_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_DBG register field value. */ +#define ALT_RSTMGR_MISCMODRST_DBG_SET_MSK 0x00004000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_DBG register field value. */ +#define ALT_RSTMGR_MISCMODRST_DBG_CLR_MSK 0xffffbfff +/* The reset value of the ALT_RSTMGR_MISCMODRST_DBG register field. */ +#define ALT_RSTMGR_MISCMODRST_DBG_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_DBG field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_DBG_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_RSTMGR_MISCMODRST_DBG register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_DBG_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : TAP Controller - tapcold + * + * Resets portion of DAP JTAG TAP controller no reset by a debug probe reset (i.e. + * nTRST pin). Cold reset only. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_MSB 15 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET_MSK 0x00008000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_CLR_MSK 0xffff7fff +/* The reset value of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_TAPCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_RSTMGR_MISCMODRST_TAPCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : SDRAM Controller Subsystem Cold Reset - sdrcold + * + * Resets logic in SDRAM Controller Subsystem affected only by a cold reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_MSB 16 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET_MSK 0x00010000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_CLR_MSK 0xfffeffff +/* The reset value of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SDRCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_RSTMGR_MISCMODRST_SDRCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET(value) (((value) << 16) & 0x00010000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_MISCMODRST. + */ +struct ALT_RSTMGR_MISCMODRST_s +{ + uint32_t rom : 1; /* Boot ROM */ + uint32_t ocram : 1; /* On-chip RAM */ + uint32_t sysmgr : 1; /* System Manager (Cold or Warm) */ + uint32_t sysmgrcold : 1; /* System Manager (Cold-only) */ + uint32_t fpgamgr : 1; /* FPGA Manager */ + uint32_t acpidmap : 1; /* ACP ID Mapper */ + uint32_t s2f : 1; /* HPS to FPGA Core (Cold or Warm) */ + uint32_t s2fcold : 1; /* HPS to FPGA Core (Cold-only) */ + uint32_t nrstpin : 1; /* nRST Pin */ + uint32_t timestampcold : 1; /* Timestamp */ + uint32_t clkmgrcold : 1; /* Clock Manager */ + uint32_t scanmgr : 1; /* Scan Manager */ + uint32_t frzctrlcold : 1; /* Freeze Controller */ + uint32_t sysdbg : 1; /* System/Debug */ + uint32_t dbg : 1; /* Debug */ + uint32_t tapcold : 1; /* TAP Controller */ + uint32_t sdrcold : 1; /* SDRAM Controller Subsystem Cold Reset */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_MISCMODRST. */ +typedef volatile struct ALT_RSTMGR_MISCMODRST_s ALT_RSTMGR_MISCMODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_MISCMODRST register from the beginning of the component. */ +#define ALT_RSTMGR_MISCMODRST_OFST 0x20 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_RSTMGR. + */ +struct ALT_RSTMGR_s +{ + volatile ALT_RSTMGR_STAT_t stat; /* ALT_RSTMGR_STAT */ + volatile ALT_RSTMGR_CTL_t ctrl; /* ALT_RSTMGR_CTL */ + volatile ALT_RSTMGR_COUNTS_t counts; /* ALT_RSTMGR_COUNTS */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_RSTMGR_MPUMODRST_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */ + volatile ALT_RSTMGR_PERMODRST_t permodrst; /* ALT_RSTMGR_PERMODRST */ + volatile ALT_RSTMGR_PER2MODRST_t per2modrst; /* ALT_RSTMGR_PER2MODRST */ + volatile ALT_RSTMGR_BRGMODRST_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */ + volatile ALT_RSTMGR_MISCMODRST_t miscmodrst; /* ALT_RSTMGR_MISCMODRST */ + volatile uint32_t _pad_0x24_0x100[55]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_RSTMGR. */ +typedef volatile struct ALT_RSTMGR_s ALT_RSTMGR_t; +/* The struct declaration for the raw register contents of register group ALT_RSTMGR. */ +struct ALT_RSTMGR_raw_s +{ + volatile uint32_t stat; /* ALT_RSTMGR_STAT */ + volatile uint32_t ctrl; /* ALT_RSTMGR_CTL */ + volatile uint32_t counts; /* ALT_RSTMGR_COUNTS */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */ + volatile uint32_t permodrst; /* ALT_RSTMGR_PERMODRST */ + volatile uint32_t per2modrst; /* ALT_RSTMGR_PER2MODRST */ + volatile uint32_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */ + volatile uint32_t miscmodrst; /* ALT_RSTMGR_MISCMODRST */ + volatile uint32_t _pad_0x24_0x100[55]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_RSTMGR. */ +typedef volatile struct ALT_RSTMGR_raw_s ALT_RSTMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_RSTMGR_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h new file mode 100644 index 0000000000..785aa743cb --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h @@ -0,0 +1,4149 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_SDR */ + +#ifndef __ALTERA_ALT_SDR_H__ +#define __ALTERA_ALT_SDR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : SDRAM Controller - ALT_SDR + * SDRAM Controller + * + * Address map for the SDRAM Interface registers + * + */ +/* + * Register Group : SDRAM Controller Module - ALT_SDR_CTL + * SDRAM Controller Module + * + * Address map for the SDRAM controller and multi-port front-end. + * + * All registers in this group reset to zero. + * + */ +/* + * Register : Controller Configuration Register - ctrlcfg + * + * The Controller Configuration Register determines the behavior of the controller. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [2:0] | RW | Unknown | DRAM Memory Type + * [7:3] | RW | Unknown | DRAM Memory Burst Length + * [9:8] | RW | Unknown | Address Interleaving Order + * [10] | RW | Unknown | ECC Enable + * [11] | RW | Unknown | ECC Auto-Correction Enable + * [12] | RW | Unknown | TBD + * [13] | RW | Unknown | Generate Single Bit Errors + * [14] | RW | Unknown | Generate Double Bit Errors + * [15] | RW | Unknown | Command Reorder Enable + * [21:16] | RW | Unknown | Starvation Limit + * [22] | RW | Unknown | DQS Tracking Enable + * [23] | RW | Unknown | No DM Pins Present + * [24] | RW | Unknown | Burst Interrupt Enable + * [25] | RW | Unknown | Burst Terminate Enable + * [31:26] | ??? | Unknown | *UNDEFINED* + * + */ +/* + * Field : DRAM Memory Type - memtype + * + * Selects memory type. Program this field with one of the following binary values, + * "001" for DDR2 SDRAM, "010" for DDR3 SDRAM, "011" + * for LPDDR1 SDRAM or "100" for LPDDR2 SDRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_MSB 2 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_WIDTH 3 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET_MSK 0x00000007 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_MEMTYPE field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_SDR_CTL_CTLCFG_MEMTYPE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : DRAM Memory Burst Length - membl + * + * Configures burst length as a static decimal value. Legal values are valid for + * JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, this + * should be programmed with 8 (binary "01000"), for DDR2 it can be + * either 4 or 8 depending on the exact DRAM chip. LPDDR2 can be programmed with + * 4, 8, or 16 and LPDDR can be programmed with 2, 4, or 8. You must also program + * the membl field in the staticcfg register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_MSB 7 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_SET_MSK 0x000000f8 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_CLR_MSK 0xffffff07 +/* The reset value of the ALT_SDR_CTL_CTLCFG_MEMBL register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_MEMBL field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_GET(value) (((value) & 0x000000f8) >> 3) +/* Produces a ALT_SDR_CTL_CTLCFG_MEMBL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_SET(value) (((value) << 3) & 0x000000f8) + +/* + * Field : Address Interleaving Order - addrorder + * + * Selects the order for address interleaving. Programming this field with + * different values gives different mappings between the AXI or Avalon-MM address + * and the SDRAM address. Program this field with the following binary values to + * select the ordering. "00" - chip, row, bank, column, "01" - + * chip, bank, row, column, "10"-row, chip, bank, column + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_MSB 9 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET_MSK 0x00000300 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_CLR_MSK 0xfffffcff +/* The reset value of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_ADDRORDER field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_SDR_CTL_CTLCFG_ADDRORDER register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : ECC Enable - eccen + * + * Enable the generation and checking of ECC. This bit must only be set if the + * memory connected to the SDRAM interface is 24 or 40 bits wide. If you set this, + * you must clear the useeccasdata field in the staticcfg register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_MSB 10 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SDR_CTL_CTLCFG_ECCEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_ECCEN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SDR_CTL_CTLCFG_ECCEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : ECC Auto-Correction Enable - ecccorren + * + * Enable auto correction of the read data returned when single bit error is + * detected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_MSB 11 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_ECCCORREN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SDR_CTL_CTLCFG_ECCCORREN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : TBD - cfg_enable_ecc_code_overwrites + * + * Set to a one to enable ECC overwrites. ECC overwrites occur when a correctable + * ECC error is seen and cause a new read/modify/write to be scheduled for that + * location to clear the ECC error. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_MSB 12 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_CLR_MSK 0xffffefff +/* The reset value of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Generate Single Bit Errors - gensbe + * + * Enable the deliberate insertion of single bit errors in data written to memory. + * This should only be used for testing purposes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_MSB 13 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SDR_CTL_CTLCFG_GENSBE register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_GENSBE field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SDR_CTL_CTLCFG_GENSBE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Generate Double Bit Errors - gendbe + * + * Enable the deliberate insertion of double bit errors in data written to memory. + * This should only be used for testing purposes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_MSB 14 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_SET_MSK 0x00004000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_CLR_MSK 0xffffbfff +/* The reset value of the ALT_SDR_CTL_CTLCFG_GENDBE register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_GENDBE field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_SDR_CTL_CTLCFG_GENDBE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Command Reorder Enable - reorderen + * + * This bit controls whether the controller can re-order operations to optimize + * SDRAM bandwidth. It should generally be set to a one. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_MSB 15 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_SET_MSK 0x00008000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_CLR_MSK 0xffff7fff +/* The reset value of the ALT_SDR_CTL_CTLCFG_REORDEREN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_REORDEREN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_SDR_CTL_CTLCFG_REORDEREN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Starvation Limit - starvelimit + * + * Specifies the number of DRAM burst transactions an individual transaction will + * allow to reorder ahead of it before its priority is raised in the memory + * controller. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_MSB 21 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_WIDTH 6 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_STARVELIMIT field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : DQS Tracking Enable - dqstrken + * + * Enables DQS tracking in the PHY. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_MSB 22 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET_MSK 0x00400000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_CLR_MSK 0xffbfffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_DQSTRKEN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : No DM Pins Present - nodmpins + * + * Set to a one to enable DRAM operation if no DM pins are connected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_MSB 23 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_SET_MSK 0x00800000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_CLR_MSK 0xff7fffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_NODMPINS register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_NODMPINS field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_SDR_CTL_CTLCFG_NODMPINS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Burst Interrupt Enable - burstintren + * + * Set to a one to enable the controller to issue burst interrupt commands. This + * must only be set when the DRAM memory type is LPDDR2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_MSB 24 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET_MSK 0x01000000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_CLR_MSK 0xfeffffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_BURSTINTREN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Burst Terminate Enable - bursttermen + * + * Set to a one to enable the controller to issue burst terminate commands. This + * must only be set when the DRAM memory type is LPDDR2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_MSB 25 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET_MSK 0x02000000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_CLR_MSK 0xfdffffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_BURSTTERMEN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET(value) (((value) << 25) & 0x02000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_CTLCFG. + */ +struct ALT_SDR_CTL_CTLCFG_s +{ + uint32_t memtype : 3; /* DRAM Memory Type */ + uint32_t membl : 5; /* DRAM Memory Burst Length */ + uint32_t addrorder : 2; /* Address Interleaving Order */ + uint32_t eccen : 1; /* ECC Enable */ + uint32_t ecccorren : 1; /* ECC Auto-Correction Enable */ + uint32_t cfg_enable_ecc_code_overwrites : 1; /* TBD */ + uint32_t gensbe : 1; /* Generate Single Bit Errors */ + uint32_t gendbe : 1; /* Generate Double Bit Errors */ + uint32_t reorderen : 1; /* Command Reorder Enable */ + uint32_t starvelimit : 6; /* Starvation Limit */ + uint32_t dqstrken : 1; /* DQS Tracking Enable */ + uint32_t nodmpins : 1; /* No DM Pins Present */ + uint32_t burstintren : 1; /* Burst Interrupt Enable */ + uint32_t bursttermen : 1; /* Burst Terminate Enable */ + uint32_t : 6; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_CTLCFG. */ +typedef volatile struct ALT_SDR_CTL_CTLCFG_s ALT_SDR_CTL_CTLCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_CTLCFG register from the beginning of the component. */ +#define ALT_SDR_CTL_CTLCFG_OFST 0x0 + +/* + * Register : DRAM Timings 1 Register - dramtiming1 + * + * This register implements JEDEC standardized timing parameters. It should be + * programmed in clock cycles, for the value specified by the memory vendor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [3:0] | RW | Unknown | CAS Write Latency + * [8:4] | RW | Unknown | Additive Latency + * [13:9] | RW | Unknown | CAS Read Latency + * [17:14] | RW | Unknown | Activate to Activate Delay + * [23:18] | RW | Unknown | Four Activate Window Time + * [31:24] | RW | Unknown | Refresh Cycle Time + * + */ +/* + * Field : CAS Write Latency - tcwl + * + * Memory write latency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCWL field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TCWL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Additive Latency - tal + * + * Memory additive latency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_MSB 8 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TAL register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TAL field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TAL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : CAS Read Latency - tcl + * + * Memory read latency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_MSB 13 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_SET_MSK 0x00003e00 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_CLR_MSK 0xffffc1ff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCL register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCL field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_GET(value) (((value) & 0x00003e00) >> 9) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TCL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_SET(value) (((value) << 9) & 0x00003e00) + +/* + * Field : Activate to Activate Delay - trrd + * + * The activate to activate, different banks timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_MSB 17 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET_MSK 0x0003c000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_CLR_MSK 0xfffc3fff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRRD field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_GET(value) (((value) & 0x0003c000) >> 14) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TRRD register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET(value) (((value) << 14) & 0x0003c000) + +/* + * Field : Four Activate Window Time - tfaw + * + * The four-activate window timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_MSB 23 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_WIDTH 6 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET_MSK 0x00fc0000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_CLR_MSK 0xff03ffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TFAW field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_GET(value) (((value) & 0x00fc0000) >> 18) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TFAW register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET(value) (((value) << 18) & 0x00fc0000) + +/* + * Field : Refresh Cycle Time - trfc + * + * The refresh cycle timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_MSB 31 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET_MSK 0xff000000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_CLR_MSK 0x00ffffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRFC field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TRFC register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMTIMING1. + */ +struct ALT_SDR_CTL_DRAMTIMING1_s +{ + uint32_t tcwl : 4; /* CAS Write Latency */ + uint32_t tal : 5; /* Additive Latency */ + uint32_t tcl : 5; /* CAS Read Latency */ + uint32_t trrd : 4; /* Activate to Activate Delay */ + uint32_t tfaw : 6; /* Four Activate Window Time */ + uint32_t trfc : 8; /* Refresh Cycle Time */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING1. */ +typedef volatile struct ALT_SDR_CTL_DRAMTIMING1_s ALT_SDR_CTL_DRAMTIMING1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMTIMING1 register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMTIMING1_OFST 0x4 + +/* + * Register : DRAM Timings 2 Register - dramtiming2 + * + * This register implements JEDEC standardized timing parameters. It should be + * programmed in clock cycles, for the value specified by the memory vendor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------- + * [12:0] | RW | Unknown | Refresh Interval + * [16:13] | RW | Unknown | Activate to Read or Write Delay + * [20:17] | RW | Unknown | Row Precharge Time + * [24:21] | RW | Unknown | Write Recovery Time + * [28:25] | RW | Unknown | Write to Read Time + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Refresh Interval - trefi + * + * The refresh interval timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_MSB 12 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_WIDTH 13 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET_MSK 0x00001fff +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_CLR_MSK 0xffffe000 +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TREFI field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_GET(value) (((value) & 0x00001fff) >> 0) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TREFI register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET(value) (((value) << 0) & 0x00001fff) + +/* + * Field : Activate to Read or Write Delay - trcd + * + * The activate to read/write timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_MSB 16 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET_MSK 0x0001e000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_CLR_MSK 0xfffe1fff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRCD field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_GET(value) (((value) & 0x0001e000) >> 13) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TRCD register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET(value) (((value) << 13) & 0x0001e000) + +/* + * Field : Row Precharge Time - trp + * + * The precharge to activate timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_MSB 20 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_SET_MSK 0x001e0000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_CLR_MSK 0xffe1ffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRP field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_GET(value) (((value) & 0x001e0000) >> 17) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TRP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_SET(value) (((value) << 17) & 0x001e0000) + +/* + * Field : Write Recovery Time - twr + * + * The write recovery timing. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_MSB 24 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_SET_MSK 0x01e00000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_CLR_MSK 0xfe1fffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWR field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_GET(value) (((value) & 0x01e00000) >> 21) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TWR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_SET(value) (((value) << 21) & 0x01e00000) + +/* + * Field : Write to Read Time - twtr + * + * The write to read timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_MSB 28 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET_MSK 0x1e000000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_CLR_MSK 0xe1ffffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWTR field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_GET(value) (((value) & 0x1e000000) >> 25) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TWTR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET(value) (((value) << 25) & 0x1e000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMTIMING2. + */ +struct ALT_SDR_CTL_DRAMTIMING2_s +{ + uint32_t trefi : 13; /* Refresh Interval */ + uint32_t trcd : 4; /* Activate to Read or Write Delay */ + uint32_t trp : 4; /* Row Precharge Time */ + uint32_t twr : 4; /* Write Recovery Time */ + uint32_t twtr : 4; /* Write to Read Time */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING2. */ +typedef volatile struct ALT_SDR_CTL_DRAMTIMING2_s ALT_SDR_CTL_DRAMTIMING2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMTIMING2 register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMTIMING2_OFST 0x8 + +/* + * Register : DRAM Timings 3 Register - dramtiming3 + * + * This register implements JEDEC standardized timing parameters. It should be + * programmed in clock cycles, for the value specified by the memory vendor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------- + * [3:0] | RW | Unknown | Read to Precharge Time + * [8:4] | RW | Unknown | Activate to Precharge Time + * [14:9] | RW | Unknown | Row Cycle Time + * [18:15] | RW | Unknown | Mode Register Programming Delay + * [22:19] | RW | Unknown | CAS to CAS Delay + * [31:23] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Read to Precharge Time - trtp + * + * The read to precharge timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRTP field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRTP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Activate to Precharge Time - tras + * + * The activate to precharge timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_MSB 8 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRAS field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRAS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : Row Cycle Time - trc + * + * The activate to activate timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_MSB 14 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_WIDTH 6 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET_MSK 0x00007e00 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_CLR_MSK 0xffff81ff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRC register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRC field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_GET(value) (((value) & 0x00007e00) >> 9) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRC register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET(value) (((value) << 9) & 0x00007e00) + +/* + * Field : Mode Register Programming Delay - tmrd + * + * Mode register timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_MSB 18 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET_MSK 0x00078000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_CLR_MSK 0xfff87fff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TMRD field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_GET(value) (((value) & 0x00078000) >> 15) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TMRD register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET(value) (((value) << 15) & 0x00078000) + +/* + * Field : CAS to CAS Delay - tccd + * + * The CAS to CAS delay time. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_MSB 22 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET_MSK 0x00780000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_CLR_MSK 0xff87ffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TCCD field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_GET(value) (((value) & 0x00780000) >> 19) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TCCD register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET(value) (((value) << 19) & 0x00780000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMTIMING3. + */ +struct ALT_SDR_CTL_DRAMTIMING3_s +{ + uint32_t trtp : 4; /* Read to Precharge Time */ + uint32_t tras : 5; /* Activate to Precharge Time */ + uint32_t trc : 6; /* Row Cycle Time */ + uint32_t tmrd : 4; /* Mode Register Programming Delay */ + uint32_t tccd : 4; /* CAS to CAS Delay */ + uint32_t : 9; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING3. */ +typedef volatile struct ALT_SDR_CTL_DRAMTIMING3_s ALT_SDR_CTL_DRAMTIMING3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMTIMING3 register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMTIMING3_OFST 0xc + +/* + * Register : DRAM Timings 4 Register - dramtiming4 + * + * This register implements JEDEC standardized timing parameters. It should be + * programmed in clock cycles, for the value specified by the memory vendor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------------------- + * [9:0] | RW | Unknown | Self-refresh Exit + * [19:10] | RW | Unknown | Power Down Exit + * [23:20] | RW | Unknown | Minimum Low Power State Cycles + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Self-refresh Exit - selfrfshexit + * + * The self refresh exit cycles, tXS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_MSB 9 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET_MSK 0x000003ff +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET(value) (((value) << 0) & 0x000003ff) + +/* + * Field : Power Down Exit - pwrdownexit + * + * The power down exit cycles, tXPDLL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_MSB 19 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET_MSK 0x000ffc00 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_CLR_MSK 0xfff003ff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_GET(value) (((value) & 0x000ffc00) >> 10) +/* Produces a ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET(value) (((value) << 10) & 0x000ffc00) + +/* + * Field : Minimum Low Power State Cycles - minpwrsavecycles + * + * The minimum number of cycles to stay in a low power state. This applies to both + * power down and self-refresh and should be set to the greater of tPD and tCKESR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_MSB 23 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET_MSK 0x00f00000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_CLR_MSK 0xff0fffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_GET(value) (((value) & 0x00f00000) >> 20) +/* Produces a ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET(value) (((value) << 20) & 0x00f00000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMTIMING4. + */ +struct ALT_SDR_CTL_DRAMTIMING4_s +{ + uint32_t selfrfshexit : 10; /* Self-refresh Exit */ + uint32_t pwrdownexit : 10; /* Power Down Exit */ + uint32_t minpwrsavecycles : 4; /* Minimum Low Power State Cycles */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING4. */ +typedef volatile struct ALT_SDR_CTL_DRAMTIMING4_s ALT_SDR_CTL_DRAMTIMING4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMTIMING4 register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMTIMING4_OFST 0x10 + +/* + * Register : Lower Power Timing Register - lowpwrtiming + * + * This register controls the behavior of the low power logic in the controller. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [15:0] | RW | Unknown | Auto-power Down Cycles + * [19:16] | RW | Unknown | Clock Disable Delay Cycles + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Auto-power Down Cycles - autopdcycles + * + * The number of idle clock cycles after which the controller should place the + * memory into power-down mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_MSB 15 +/* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_WIDTH 16 +/* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES field value from a register. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Clock Disable Delay Cycles - clkdisablecycles + * + * Set to a the number of clocks after the execution of an self-refresh to stop the + * clock. This register is generally set based on PHY design latency and should + * generally not be changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_MSB 19 +/* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET_MSK 0x000f0000 +/* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_CLR_MSK 0xfff0ffff +/* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES field value from a register. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_GET(value) (((value) & 0x000f0000) >> 16) +/* Produces a ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET(value) (((value) << 16) & 0x000f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_LOWPWRTIMING. + */ +struct ALT_SDR_CTL_LOWPWRTIMING_s +{ + uint32_t autopdcycles : 16; /* Auto-power Down Cycles */ + uint32_t clkdisablecycles : 4; /* Clock Disable Delay Cycles */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_LOWPWRTIMING. */ +typedef volatile struct ALT_SDR_CTL_LOWPWRTIMING_s ALT_SDR_CTL_LOWPWRTIMING_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_LOWPWRTIMING register from the beginning of the component. */ +#define ALT_SDR_CTL_LOWPWRTIMING_OFST 0x14 + +/* + * Register : ODT Control Register - dramodt + * + * This register controls which ODT pin is asserted during reads or writes. Bits + * [1:0] control which ODT pin is asserted during to accesses to chip select 0, + * bits [3:2] which ODT pin is asserted during accesses to chip select 1. For + * example, a value of "1001" will cause ODT[0] to be asserted for + * accesses to CS[0], and ODT[1] to be asserted for access to CS[1] pin. Set this + * to "0001" if there is only one chip select available. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------ + * [3:0] | RW | Unknown | Write ODT Control + * [7:4] | RW | Unknown | Read ODT Control + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write ODT Control - cfg_write_odt_chip + * + * This register controls which ODT pin is asserted during writes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP field value from a register. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Read ODT Control - cfg_read_odt_chip + * + * This register controls which ODT pin is asserted during reads. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_MSB 7 +/* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_CLR_MSK 0xffffff0f +/* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP field value from a register. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMODT. + */ +struct ALT_SDR_CTL_DRAMODT_s +{ + uint32_t cfg_write_odt_chip : 4; /* Write ODT Control */ + uint32_t cfg_read_odt_chip : 4; /* Read ODT Control */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMODT. */ +typedef volatile struct ALT_SDR_CTL_DRAMODT_s ALT_SDR_CTL_DRAMODT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMODT register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMODT_OFST 0x18 + +/* + * Register : DRAM Address Widths Register - dramaddrw + * + * This register configures the width of the various address fields of the DRAM. + * The values specified in this register must match the memory devices being used. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------------- + * [4:0] | RW | Unknown | DRAM Column Address Bits + * [9:5] | RW | Unknown | DRAM Row Address Bits + * [12:10] | RW | Unknown | DRAM Bank Address Bits + * [15:13] | RW | Unknown | DRAM Chip Address Bits + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DRAM Column Address Bits - colbits + * + * The number of column address bits for the memory devices in your memory + * interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_MSB 4 +/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET_MSK 0x0000001f +/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMADDRW_COLBITS field value from a register. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMADDRW_COLBITS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET(value) (((value) << 0) & 0x0000001f) + +/* + * Field : DRAM Row Address Bits - rowbits + * + * The number of row address bits for the memory devices in your memory interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_MSB 9 +/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET_MSK 0x000003e0 +/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_CLR_MSK 0xfffffc1f +/* The reset value of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMADDRW_ROWBITS field value from a register. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_GET(value) (((value) & 0x000003e0) >> 5) +/* Produces a ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET(value) (((value) << 5) & 0x000003e0) + +/* + * Field : DRAM Bank Address Bits - bankbits + * + * The number of bank address bits for the memory devices in your memory interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_MSB 12 +/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_WIDTH 3 +/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET_MSK 0x00001c00 +/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_CLR_MSK 0xffffe3ff +/* The reset value of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMADDRW_BANKBITS field value from a register. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_GET(value) (((value) & 0x00001c00) >> 10) +/* Produces a ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET(value) (((value) << 10) & 0x00001c00) + +/* + * Field : DRAM Chip Address Bits - csbits + * + * The number of chip select address bits for the memory devices in your memory + * interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_MSB 15 +/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_WIDTH 3 +/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET_MSK 0x0000e000 +/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_CLR_MSK 0xffff1fff +/* The reset value of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMADDRW_CSBITS field value from a register. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_GET(value) (((value) & 0x0000e000) >> 13) +/* Produces a ALT_SDR_CTL_DRAMADDRW_CSBITS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET(value) (((value) << 13) & 0x0000e000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMADDRW. + */ +struct ALT_SDR_CTL_DRAMADDRW_s +{ + uint32_t colbits : 5; /* DRAM Column Address Bits */ + uint32_t rowbits : 5; /* DRAM Row Address Bits */ + uint32_t bankbits : 3; /* DRAM Bank Address Bits */ + uint32_t csbits : 3; /* DRAM Chip Address Bits */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMADDRW. */ +typedef volatile struct ALT_SDR_CTL_DRAMADDRW_s ALT_SDR_CTL_DRAMADDRW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMADDRW register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMADDRW_OFST 0x2c + +/* + * Register : DRAM Interface Data Width Register - dramifwidth + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------- + * [7:0] | RW | Unknown | DRAM Interface Data Width + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DRAM Interface Data Width - ifwidth + * + * This register controls the interface width of the SDRAM interface, including any + * bits used for ECC. For example, for a 32-bit interface with ECC, program this + * register with 0x28. You must also program the ctrlwidth register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_MSB 7 +/* The width in bits of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH field value from a register. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMIFWIDTH. + */ +struct ALT_SDR_CTL_DRAMIFWIDTH_s +{ + uint32_t ifwidth : 8; /* DRAM Interface Data Width */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMIFWIDTH. */ +typedef volatile struct ALT_SDR_CTL_DRAMIFWIDTH_s ALT_SDR_CTL_DRAMIFWIDTH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMIFWIDTH register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_OFST 0x30 + +/* + * Register : DRAM Devices Data Width Register - dramdevwidth + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------------ + * [3:0] | RW | Unknown | DRAM Devices Data Width + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DRAM Devices Data Width - devwidth + * + * This register specifies the width of the physical DRAM chips, for example 8 or + * 16. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH field value from a register. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMDEVWIDTH. + */ +struct ALT_SDR_CTL_DRAMDEVWIDTH_s +{ + uint32_t devwidth : 4; /* DRAM Devices Data Width */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMDEVWIDTH. */ +typedef volatile struct ALT_SDR_CTL_DRAMDEVWIDTH_s ALT_SDR_CTL_DRAMDEVWIDTH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMDEVWIDTH register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_OFST 0x34 + +/* + * Register : DRAM Status Register - dramsts + * + * This register provides the status of the calibration and ECC logic. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:---------------------------- + * [0] | RW | Unknown | PHY Calibration Successful + * [1] | RW | Unknown | PHY Calibration Failed + * [2] | RW | Unknown | Single Bit Error Seen + * [3] | RW | Unknown | Double Bit Error Seen + * [4] | RW | Unknown | ECC Auto-Correction Dropped + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : PHY Calibration Successful - calsuccess + * + * This bit will be set to 1 if the PHY was able to successfully calibrate. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_MSB 0 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_CALSUCCESS field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : PHY Calibration Failed - calfail + * + * This bit will be set to 1 if the PHY was unable to calibrate. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_MSB 1 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_CALFAIL field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDR_CTL_DRAMSTS_CALFAIL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Single Bit Error Seen - sbeerr + * + * This bit will be set to 1 if there have been any ECC single bit errors detected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_MSB 2 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDR_CTL_DRAMSTS_SBEERR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_SBEERR field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDR_CTL_DRAMSTS_SBEERR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Double Bit Error Seen - dbeerr + * + * This bit will be set to 1 if there have been any ECC double bit errors detected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDR_CTL_DRAMSTS_DBEERR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_DBEERR field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDR_CTL_DRAMSTS_DBEERR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : ECC Auto-Correction Dropped - corrdrop + * + * This bit will be set to 1 if there any auto-corrections have been dropped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_MSB 4 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_CLR_MSK 0xffffffef +/* The reset value of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_CORRDROP field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SDR_CTL_DRAMSTS_CORRDROP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMSTS. + */ +struct ALT_SDR_CTL_DRAMSTS_s +{ + uint32_t calsuccess : 1; /* PHY Calibration Successful */ + uint32_t calfail : 1; /* PHY Calibration Failed */ + uint32_t sbeerr : 1; /* Single Bit Error Seen */ + uint32_t dbeerr : 1; /* Double Bit Error Seen */ + uint32_t corrdrop : 1; /* ECC Auto-Correction Dropped */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMSTS. */ +typedef volatile struct ALT_SDR_CTL_DRAMSTS_s ALT_SDR_CTL_DRAMSTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMSTS register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMSTS_OFST 0x38 + +/* + * Register : ECC Interrupt Register - dramintr + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------------------- + * [0] | RW | Unknown | Interrupt Enable + * [1] | RW | Unknown | Mask Single Bit Error Interrupt + * [2] | RW | Unknown | Mask Double Bit Error Interrupt + * [3] | RW | Unknown | Mask Dropped Auto-correction Interrupt + * [4] | RW | Unknown | Clear Interrupt Signal + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Enable - intren + * + * Enable the interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_MSB 0 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDR_CTL_DRAMINTR_INTREN register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_INTREN field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDR_CTL_DRAMINTR_INTREN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Mask Single Bit Error Interrupt - sbemask + * + * Mask the single bit error interrupt. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_MSB 1 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_SBEMSK field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDR_CTL_DRAMINTR_SBEMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Mask Double Bit Error Interrupt - dbemask + * + * Mask the double bit error interrupt. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_MSB 2 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_DBEMSK field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDR_CTL_DRAMINTR_DBEMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Mask Dropped Auto-correction Interrupt - corrdropmask + * + * Set this bit to a one to mask interrupts for an ECC correction write back + * needing to be dropped. This indicates a burst of memory errors in a short + * period of time. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Clear Interrupt Signal - intrclr + * + * Writing to this self-clearing bit clears the interrupt signal. Writing to this + * bit also clears the error count and error address registers. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_MSB 4 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_INTRCLR field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SDR_CTL_DRAMINTR_INTRCLR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMINTR. + */ +struct ALT_SDR_CTL_DRAMINTR_s +{ + uint32_t intren : 1; /* Interrupt Enable */ + uint32_t sbemask : 1; /* Mask Single Bit Error Interrupt */ + uint32_t dbemask : 1; /* Mask Double Bit Error Interrupt */ + uint32_t corrdropmask : 1; /* Mask Dropped Auto-correction Interrupt */ + uint32_t intrclr : 1; /* Clear Interrupt Signal */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMINTR. */ +typedef volatile struct ALT_SDR_CTL_DRAMINTR_s ALT_SDR_CTL_DRAMINTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMINTR register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMINTR_OFST 0x3c + +/* + * Register : ECC Single Bit Error Count Register - sbecount + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------------- + * [7:0] | RW | Unknown | Single Bit Error Count + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Single Bit Error Count - count + * + * Reports the number of single bit errors that have occurred since the status + * register counters were last cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_MSB 7 +/* The width in bits of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_SBECOUNT_COUNT register field is UNKNOWN. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_SBECOUNT_COUNT field value from a register. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_SBECOUNT_COUNT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_SBECOUNT. + */ +struct ALT_SDR_CTL_SBECOUNT_s +{ + uint32_t count : 8; /* Single Bit Error Count */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_SBECOUNT. */ +typedef volatile struct ALT_SDR_CTL_SBECOUNT_s ALT_SDR_CTL_SBECOUNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_SBECOUNT register from the beginning of the component. */ +#define ALT_SDR_CTL_SBECOUNT_OFST 0x40 + +/* + * Register : ECC Double Bit Error Count Register - dbecount + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------------- + * [7:0] | RW | Unknown | Double Bit Error Count + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Double Bit Error Count - count + * + * Reports the number of double bit errors that have occurred since the status + * register counters were last cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_MSB 7 +/* The width in bits of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_DBECOUNT_COUNT register field is UNKNOWN. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DBECOUNT_COUNT field value from a register. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_DBECOUNT_COUNT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DBECOUNT. + */ +struct ALT_SDR_CTL_DBECOUNT_s +{ + uint32_t count : 8; /* Double Bit Error Count */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DBECOUNT. */ +typedef volatile struct ALT_SDR_CTL_DBECOUNT_s ALT_SDR_CTL_DBECOUNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DBECOUNT register from the beginning of the component. */ +#define ALT_SDR_CTL_DBECOUNT_OFST 0x44 + +/* + * Register : ECC Error Address Register - erraddr + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------ + * [31:0] | RW | Unknown | ECC Error Address + * + */ +/* + * Field : ECC Error Address - addr + * + * The address of the most recent ECC error. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_MSB 31 +/* The width in bits of the ALT_SDR_CTL_ERRADDR_ADDR register field. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_SDR_CTL_ERRADDR_ADDR register field value. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDR_CTL_ERRADDR_ADDR register field value. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDR_CTL_ERRADDR_ADDR register field is UNKNOWN. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_ERRADDR_ADDR field value from a register. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDR_CTL_ERRADDR_ADDR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_ERRADDR. + */ +struct ALT_SDR_CTL_ERRADDR_s +{ + uint32_t addr : 32; /* ECC Error Address */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_ERRADDR. */ +typedef volatile struct ALT_SDR_CTL_ERRADDR_s ALT_SDR_CTL_ERRADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_ERRADDR register from the beginning of the component. */ +#define ALT_SDR_CTL_ERRADDR_OFST 0x48 + +/* + * Register : ECC Auto-correction Dropped Count Register - dropcount + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------------------ + * [7:0] | RW | Unknown | Dropped Auto-correction Count + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Dropped Auto-correction Count - corrdropcount + * + * This gives the count of the number of ECC write back transactions dropped due to + * the internal FIFO overflowing. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_MSB 7 +/* The width in bits of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field is UNKNOWN. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT field value from a register. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DROPCOUNT. + */ +struct ALT_SDR_CTL_DROPCOUNT_s +{ + uint32_t corrdropcount : 8; /* Dropped Auto-correction Count */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DROPCOUNT. */ +typedef volatile struct ALT_SDR_CTL_DROPCOUNT_s ALT_SDR_CTL_DROPCOUNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DROPCOUNT register from the beginning of the component. */ +#define ALT_SDR_CTL_DROPCOUNT_OFST 0x4c + +/* + * Register : ECC Auto-correction Dropped Address Register - dropaddr + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------------- + * [31:0] | RW | Unknown | Dropped Auto-correction Address + * + */ +/* + * Field : Dropped Auto-correction Address - corrdropaddr + * + * This register gives the last address which was dropped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_MSB 31 +/* The width in bits of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_WIDTH 32 +/* The mask used to set the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DROPADDR_CORRDROPADDR field value from a register. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DROPADDR. + */ +struct ALT_SDR_CTL_DROPADDR_s +{ + uint32_t corrdropaddr : 32; /* Dropped Auto-correction Address */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DROPADDR. */ +typedef volatile struct ALT_SDR_CTL_DROPADDR_s ALT_SDR_CTL_DROPADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DROPADDR register from the beginning of the component. */ +#define ALT_SDR_CTL_DROPADDR_OFST 0x50 + +/* + * Register : Low Power Control Register - lowpwreq + * + * This register instructs the controller to put the DRAM into a power down state. + * Note that some commands are only valid for certain memory types. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------------- + * [0] | RW | Unknown | Deep Power Down Request + * [2:1] | RW | Unknown | Deep Power Down Chip Select Mask + * [3] | RW | Unknown | Self-refresh Request + * [5:4] | RW | Unknown | Self-refresh Chip Select Mask + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Deep Power Down Request - deeppwrdnreq + * + * Write a one to this bit to request a deep power down. This bit should only be + * written with LPDDR2 DRAMs, DDR3 DRAMs do not support deep power down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_MSB 0 +/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ field value from a register. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Deep Power Down Chip Select Mask - deeppwrdnmask + * + * Write ones to this register to select which DRAM chip selects will be powered + * down. Typical usage is to set both of these bits when deeppwrdnreq is set but + * the controller does support putting a single chip into deep power down and + * keeping the other chip running. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_MSB 2 +/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET_MSK 0x00000006 +/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK field value from a register. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET(value) (((value) << 1) & 0x00000006) + +/* + * Field : Self-refresh Request - selfrshreq + * + * Write a one to this bit to request the RAM be put into a self refresh state. + * This bit is treated as a static value so the RAM will remain in self-refresh as + * long as this register bit is set to a one. This power down mode can be selected + * for all DRAMs supported by the controller. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_MSB 3 +/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ field value from a register. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Self-refresh Chip Select Mask - selfrfshmask + * + * Write a one to each bit of this field to have a self refresh request apply to + * both chips. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_MSB 5 +/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET_MSK 0x00000030 +/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_CLR_MSK 0xffffffcf +/* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK field value from a register. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET(value) (((value) << 4) & 0x00000030) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_LOWPWREQ. + */ +struct ALT_SDR_CTL_LOWPWREQ_s +{ + uint32_t deeppwrdnreq : 1; /* Deep Power Down Request */ + uint32_t deeppwrdnmask : 2; /* Deep Power Down Chip Select Mask */ + uint32_t selfrshreq : 1; /* Self-refresh Request */ + uint32_t selfrfshmask : 2; /* Self-refresh Chip Select Mask */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_LOWPWREQ. */ +typedef volatile struct ALT_SDR_CTL_LOWPWREQ_s ALT_SDR_CTL_LOWPWREQ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_LOWPWREQ register from the beginning of the component. */ +#define ALT_SDR_CTL_LOWPWREQ_OFST 0x54 + +/* + * Register : Low Power Acknowledge Register - lowpwrack + * + * This register gives the status of the power down commands requested by the Low + * Power Control register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:---------------------------- + * [0] | RW | Unknown | Deep Power Down Acknowledge + * [1] | RW | Unknown | Self-refresh Acknowledge + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Deep Power Down Acknowledge - deeppwrdnack + * + * This bit is set to a one after a deep power down has been executed + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_MSB 0 +/* The width in bits of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK field value from a register. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Self-refresh Acknowledge - selfrfshack + * + * This bit is a one to indicate that the controller is in a self-refresh state. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_MSB 1 +/* The width in bits of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK field value from a register. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_LOWPWRACK. + */ +struct ALT_SDR_CTL_LOWPWRACK_s +{ + uint32_t deeppwrdnack : 1; /* Deep Power Down Acknowledge */ + uint32_t selfrfshack : 1; /* Self-refresh Acknowledge */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_LOWPWRACK. */ +typedef volatile struct ALT_SDR_CTL_LOWPWRACK_s ALT_SDR_CTL_LOWPWRACK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_LOWPWRACK register from the beginning of the component. */ +#define ALT_SDR_CTL_LOWPWRACK_OFST 0x58 + +/* + * Register : Static Configuration Register - staticcfg + * + * This register controls configuration values which cannot be updated while + * transactions are flowing. + * + * You should write once to this register with the membl and eccen fields set to + * your desired configuration, and then write to the register again with membl and + * eccen and the applycfg bit set. The applycfg bit is write only. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:---------------------------- + * [1:0] | RW | Unknown | Memory Burst Length + * [2] | RW | Unknown | Use ECC Bits As Data + * [3] | RW | Unknown | Apply Configuration Changes + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Memory Burst Length - membl + * + * This field specifies the DRAM burst length. Write the following values to set + * the a burst length appropriate for the specific DRAM being used. "00" + * for burst length 2, "01" for burst length 4, "10" for burst + * length 8. If you set this, you must also set the membl field in the ctrlcfg + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_MSB 1 +/* The width in bits of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SDR_CTL_STATICCFG_MEMBL register field is UNKNOWN. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_STATICCFG_MEMBL field value from a register. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SDR_CTL_STATICCFG_MEMBL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Use ECC Bits As Data - useeccasdata + * + * This field allows the FPGA ports to directly access the extra data bits that are + * normally used to hold the ECC code. The interface width must be set to 24 or 40 + * in the dramifwidth register. If you set this, you must clear the eccen field in + * the ctrlcfg register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_MSB 2 +/* The width in bits of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field is UNKNOWN. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_RESET 0x0 +/* Extracts the ALT_SDR_CTL_STATICCFG_USEECCASDATA field value from a register. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value suitable for setting the register. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Apply Configuration Changes - applycfg + * + * Write with this bit set to apply all the settings loaded in SDR registers to the + * memory interface. This bit is write-only and always returns 0 if read. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_MSB 3 +/* The width in bits of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field is UNKNOWN. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_RESET 0x0 +/* Extracts the ALT_SDR_CTL_STATICCFG_APPLYCFG field value from a register. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDR_CTL_STATICCFG_APPLYCFG register field value suitable for setting the register. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_STATICCFG. + */ +struct ALT_SDR_CTL_STATICCFG_s +{ + uint32_t membl : 2; /* Memory Burst Length */ + uint32_t useeccasdata : 1; /* Use ECC Bits As Data */ + uint32_t applycfg : 1; /* Apply Configuration Changes */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_STATICCFG. */ +typedef volatile struct ALT_SDR_CTL_STATICCFG_s ALT_SDR_CTL_STATICCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_STATICCFG register from the beginning of the component. */ +#define ALT_SDR_CTL_STATICCFG_OFST 0x5c + +/* + * Register : Memory Controller Width Register - ctrlwidth + * + * This register controls the width of the physical DRAM interface. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------- + * [1:0] | RW | Unknown | Controller Interface Width + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Controller Interface Width - ctrlwidth + * + * Specifies controller DRAM interface width, with the following encoding. + * "00" for 8-bit, "01" for 16-bit (no ECC) or 24-bit (ECC + * enabled), "10" for 32-bit (no ECC) or 40-bit (ECC enabled). You must + * also program the dramifwidth register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_MSB 1 +/* The width in bits of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH field value from a register. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_CTLWIDTH. + */ +struct ALT_SDR_CTL_CTLWIDTH_s +{ + uint32_t ctrlwidth : 2; /* Controller Interface Width */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_CTLWIDTH. */ +typedef volatile struct ALT_SDR_CTL_CTLWIDTH_s ALT_SDR_CTL_CTLWIDTH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_CTLWIDTH register from the beginning of the component. */ +#define ALT_SDR_CTL_CTLWIDTH_OFST 0x60 + +/* + * Register : Port Configuration Register - portcfg + * + * This register should be set to a zero in any bit which corresponds to a port + * which does mostly sequential memory accesses. For ports with highly random + * accesses, the bit should be set to a one. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:---------------------- + * [9:0] | ??? | Unknown | *UNDEFINED* + * [19:10] | RW | Unknown | Auto-precharge Enable + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Auto-precharge Enable - autopchen + * + * One bit per control port. Set bit N to a 1 to have the controller request an + * automatic precharge following bus command completion (close the row + * automatically). Set to a zero to request that the controller attempt to keep a + * row open. For random dominated operations this register should be set to a 1 + * for all active ports. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_MSB 19 +/* The width in bits of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET_MSK 0x000ffc00 +/* The mask used to clear the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_CLR_MSK 0xfff003ff +/* The reset value of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PORTCFG_AUTOPCHEN field value from a register. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_GET(value) (((value) & 0x000ffc00) >> 10) +/* Produces a ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET(value) (((value) << 10) & 0x000ffc00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PORTCFG. + */ +struct ALT_SDR_CTL_PORTCFG_s +{ + uint32_t : 10; /* *UNDEFINED* */ + uint32_t autopchen : 10; /* Auto-precharge Enable */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PORTCFG. */ +typedef volatile struct ALT_SDR_CTL_PORTCFG_s ALT_SDR_CTL_PORTCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PORTCFG register from the beginning of the component. */ +#define ALT_SDR_CTL_PORTCFG_OFST 0x7c + +/* + * Register : FPGA Ports Reset Control Register - fpgaportrst + * + * This register implements functionality to allow the CPU to control when the MPFE + * will enable the ports to the FPGA fabric. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------- + * [13:0] | RW | Unknown | Port Reset Control + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port Reset Control - portrstn + * + * This register should be written to with a 1 to enable the selected FPGA port to + * exit reset. Writing a bit to a zero will stretch the port reset until the + * register is written. Read data ports are connected to bits 3:0, with read data + * port 0 at bit 0 to read data port 3 at bit 3. Write data ports 0 to 3 are mapped + * to 4 to 7, with write data port 0 connected to bit 4 to write data port 3 at bit + * 7. Command ports are connected to bits 8 to 13, with command port 0 at bit 8 to + * command port 5 at bit 13. Expected usage would be to set all the bits at the + * same time but setting some bits to a zero and others to a one is supported. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSB 13 +/* The width in bits of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_WIDTH 14 +/* The mask used to set the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET_MSK 0x00003fff +/* The mask used to clear the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_CLR_MSK 0xffffc000 +/* The reset value of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field is UNKNOWN. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN field value from a register. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_GET(value) (((value) & 0x00003fff) >> 0) +/* Produces a ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET(value) (((value) << 0) & 0x00003fff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_FPGAPORTRST. + */ +struct ALT_SDR_CTL_FPGAPORTRST_s +{ + uint32_t portrstn : 14; /* Port Reset Control */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_FPGAPORTRST. */ +typedef volatile struct ALT_SDR_CTL_FPGAPORTRST_s ALT_SDR_CTL_FPGAPORTRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_FPGAPORTRST register from the beginning of the component. */ +#define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80 + +/* + * Register : Memory Protection Port Default Register - protportdefault + * + * This register controls the default protection assignment for a port. Ports + * which have explicit rules which define regions which are illegal to access + * should set the bits to pass by default. Ports which have explicit rules which + * define legal areas should set the bit to force all transactions to fail. + * Leaving this register to all zeros should be used for systems which do not + * desire any protection from the memory controller. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------- + * [9:0] | RW | Unknown | Port Default Action + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port Default Action - portdefault + * + * Determines the default action for a transactions from a port. Set a bit to a + * zero to indicate that all accesses from the port should pass by default, set a + * bit to a one if the default protection is to fail the access. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_MSB 9 +/* The width in bits of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET_MSK 0x000003ff +/* The mask used to clear the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT field value from a register. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET(value) (((value) << 0) & 0x000003ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTPORTDEFAULT. + */ +struct ALT_SDR_CTL_PROTPORTDEFAULT_s +{ + uint32_t portdefault : 10; /* Port Default Action */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTPORTDEFAULT. */ +typedef volatile struct ALT_SDR_CTL_PROTPORTDEFAULT_s ALT_SDR_CTL_PROTPORTDEFAULT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTPORTDEFAULT register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_OFST 0x8c + +/* + * Register : Memory Protection Address Register - protruleaddr + * + * This register is used to control the memory protection for port 0 transactions. + * Address ranges can either be used to allow access to memory regions or disallow + * access to memory regions. If trustzone is being used, access can be enabled for + * protected transactions or disabled for unprotected transactions. The default + * state of this register is to allow all access. Address values used for + * protection are only physical addresses. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------- + * [11:0] | RW | Unknown | Low Address + * [23:12] | RW | Unknown | High Address + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Low Address - lowaddr + * + * Lower 12 bits of the address for a check. Address is compared to be less than + * or equal to the address of a transaction. Note that since AXI transactions + * cannot cross a 4K byte boundary, the transaction start and transaction end + * address must also fall within the same 1MByte block pointed to by this address + * pointer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_MSB 11 +/* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_WIDTH 12 +/* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET_MSK 0x00000fff +/* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_CLR_MSK 0xfffff000 +/* The reset value of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEADDR_LOWADDR field value from a register. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_GET(value) (((value) & 0x00000fff) >> 0) +/* Produces a ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET(value) (((value) << 0) & 0x00000fff) + +/* + * Field : High Address - highaddr + * + * Upper 12 bits of the address for a check. Address is compared to be greater + * than or equal to the address of a transaction. Note that since AXI transactions + * cannot cross a 4K byte boundary, the transaction start and transaction end + * address must also fall within the same 1MByte block pointed to by this address + * pointer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_MSB 23 +/* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_WIDTH 12 +/* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET_MSK 0x00fff000 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_CLR_MSK 0xff000fff +/* The reset value of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR field value from a register. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_GET(value) (((value) & 0x00fff000) >> 12) +/* Produces a ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET(value) (((value) << 12) & 0x00fff000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTRULEADDR. + */ +struct ALT_SDR_CTL_PROTRULEADDR_s +{ + uint32_t lowaddr : 12; /* Low Address */ + uint32_t highaddr : 12; /* High Address */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTRULEADDR. */ +typedef volatile struct ALT_SDR_CTL_PROTRULEADDR_s ALT_SDR_CTL_PROTRULEADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTRULEADDR register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTRULEADDR_OFST 0x90 + +/* + * Register : Memory Protection ID Register - protruleid + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------ + * [11:0] | RW | Unknown | Low ID + * [23:12] | RW | Unknown | High ID + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Low ID - lowid + * + * AxID for the protection rule. Incoming AxID needs to be greater than or equal + * to this value. For all AxIDs from a port, AxID high should be programmed to all + * ones. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_MSB 11 +/* The width in bits of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_WIDTH 12 +/* The mask used to set the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_SET_MSK 0x00000fff +/* The mask used to clear the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_CLR_MSK 0xfffff000 +/* The reset value of the ALT_SDR_CTL_PROTRULEID_LOWID register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEID_LOWID field value from a register. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_GET(value) (((value) & 0x00000fff) >> 0) +/* Produces a ALT_SDR_CTL_PROTRULEID_LOWID register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_SET(value) (((value) << 0) & 0x00000fff) + +/* + * Field : High ID - highid + * + * AxID for the protection rule. Incoming AxID needs to be less than or equal to + * this value. For all AxIDs from a port, AxID high should be programmed to all + * ones. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_MSB 23 +/* The width in bits of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_WIDTH 12 +/* The mask used to set the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_SET_MSK 0x00fff000 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_CLR_MSK 0xff000fff +/* The reset value of the ALT_SDR_CTL_PROTRULEID_HIGHID register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEID_HIGHID field value from a register. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_GET(value) (((value) & 0x00fff000) >> 12) +/* Produces a ALT_SDR_CTL_PROTRULEID_HIGHID register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_SET(value) (((value) << 12) & 0x00fff000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTRULEID. + */ +struct ALT_SDR_CTL_PROTRULEID_s +{ + uint32_t lowid : 12; /* Low ID */ + uint32_t highid : 12; /* High ID */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTRULEID. */ +typedef volatile struct ALT_SDR_CTL_PROTRULEID_s ALT_SDR_CTL_PROTRULEID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTRULEID register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTRULEID_OFST 0x94 + +/* + * Register : Memory Protection Rule Data Register - protruledata + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:---------------------- + * [1:0] | RW | Unknown | Security Bit Behavior + * [2] | RW | Unknown | Valid Rule + * [12:3] | RW | Unknown | Port Mask + * [13] | RW | Unknown | Rule Results + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Security Bit Behavior - security + * + * A value of 2'b00 will make the rule apply to secure transactions. + * + * A value of 2'b01 will make the rule apply to non-secure transactions. + * + * A value of 2'b10 or 2'b11 will make the rule apply to secure and non-secure + * transactions. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_MSB 1 +/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEDATA_SECURITY field value from a register. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Valid Rule - validrule + * + * Set to bit to a one to make a rule valid, set to a zero to invalidate a rule. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_MSB 2 +/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE field value from a register. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Port Mask - portmask + * + * Set bit x to a one to have this rule apply to port x, set bit x to a zero to + * have the rule not apply to a port. Note that port 0-port 5 are the FPGA + * fabric ports, port 6 is L3 read, port 7 is CPU read, port 8 is L3 write, port 9 + * is CPU write. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_MSB 12 +/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET_MSK 0x00001ff8 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_CLR_MSK 0xffffe007 +/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEDATA_PORTMSK field value from a register. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_GET(value) (((value) & 0x00001ff8) >> 3) +/* Produces a ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET(value) (((value) << 3) & 0x00001ff8) + +/* + * Field : Rule Results - ruleresult + * + * Set this bit to a one to force a protection failure, zero to allow the access + * the succeed + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_MSB 13 +/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEDATA_RULERESULT field value from a register. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTRULEDATA. + */ +struct ALT_SDR_CTL_PROTRULEDATA_s +{ + uint32_t security : 2; /* Security Bit Behavior */ + uint32_t validrule : 1; /* Valid Rule */ + uint32_t portmask : 10; /* Port Mask */ + uint32_t ruleresult : 1; /* Rule Results */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTRULEDATA. */ +typedef volatile struct ALT_SDR_CTL_PROTRULEDATA_s ALT_SDR_CTL_PROTRULEDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTRULEDATA register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTRULEDATA_OFST 0x98 + +/* + * Register : Memory Protection Rule Read-Write Register - protrulerdwr + * + * This register is used to perform read and write operations to the internal + * protection table. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [4:0] | RW | Unknown | Rule Offset + * [5] | RW | Unknown | Rule Write + * [6] | RW | Unknown | Rule Read + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Rule Offset - ruleoffset + * + * This field defines which of the 20 rules in the protection table you want to + * read or write. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_MSB 4 +/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET_MSK 0x0000001f +/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET field value from a register. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET(value) (((value) << 0) & 0x0000001f) + +/* + * Field : Rule Write - writerule + * + * Write to this bit to have the memory_prot_data register to the table at the + * offset specified by port_offset. Bit automatically clears after a single cycle + * and the write operation is complete. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_MSB 5 +/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULERDWR_WRRULE field value from a register. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Rule Read - readrule + * + * Write to this bit to have the memory_prot_data register loaded with the value + * from the internal protection table at offset. Table value will be loaded before + * a rdy is returned so read data from the register will be correct for any follow- + * on reads to the memory_prot_data register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_MSB 6 +/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULERDWR_RDRULE field value from a register. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTRULERDWR. + */ +struct ALT_SDR_CTL_PROTRULERDWR_s +{ + uint32_t ruleoffset : 5; /* Rule Offset */ + uint32_t writerule : 1; /* Rule Write */ + uint32_t readrule : 1; /* Rule Read */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTRULERDWR. */ +typedef volatile struct ALT_SDR_CTL_PROTRULERDWR_s ALT_SDR_CTL_PROTRULERDWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTRULERDWR register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTRULERDWR_OFST 0x9c + +/* + * Register : QOS Control Register - qoslowpri + * + * This register controls the mapping of AXI4 QOS received from the FPGA fabric to + * the internal priority used for traffic prioritization. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:----------------------- + * [19:0] | RW | Unknown | Low Priority QoS Value + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Low Priority QoS Value - lowpriorityval + * + * This 20 bit field is a 2 bit field for each of the 10 ports. The field used for + * each port in this register controls the priority used for a port + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_MSB 19 +/* The width in bits of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_WIDTH 20 +/* The mask used to set the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET_MSK 0x000fffff +/* The mask used to clear the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_CLR_MSK 0xfff00000 +/* The reset value of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field is UNKNOWN. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL field value from a register. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0) +/* Produces a ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_QOSLOWPRI. + */ +struct ALT_SDR_CTL_QOSLOWPRI_s +{ + uint32_t lowpriorityval : 20; /* Low Priority QoS Value */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_QOSLOWPRI. */ +typedef volatile struct ALT_SDR_CTL_QOSLOWPRI_s ALT_SDR_CTL_QOSLOWPRI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_QOSLOWPRI register from the beginning of the component. */ +#define ALT_SDR_CTL_QOSLOWPRI_OFST 0xa0 + +/* + * Register : qoshighpri Register - qoshighpri + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------------ + * [19:0] | RW | Unknown | High Priority QoS Value + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : High Priority QoS Value - highpriorityval + * + * This 20 bit field is a 2 bit field for each of the 10 ports. The field used for + * each port in this register controls the priority used for a port + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_MSB 19 +/* The width in bits of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_WIDTH 20 +/* The mask used to set the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET_MSK 0x000fffff +/* The mask used to clear the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_CLR_MSK 0xfff00000 +/* The reset value of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field is UNKNOWN. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL field value from a register. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0) +/* Produces a ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_QOSHIGHPRI. + */ +struct ALT_SDR_CTL_QOSHIGHPRI_s +{ + uint32_t highpriorityval : 20; /* High Priority QoS Value */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_QOSHIGHPRI. */ +typedef volatile struct ALT_SDR_CTL_QOSHIGHPRI_s ALT_SDR_CTL_QOSHIGHPRI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_QOSHIGHPRI register from the beginning of the component. */ +#define ALT_SDR_CTL_QOSHIGHPRI_OFST 0xa4 + +/* + * Register : qospriorityen Register - qospriorityen + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------- + * [9:0] | RW | Unknown | Per-Port QoS Enable + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Per-Port QoS Enable - priorityen + * + * This 10 bit field is set to a one to enable QOS usage for a port. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_MSB 9 +/* The width in bits of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET_MSK 0x000003ff +/* The mask used to clear the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN field value from a register. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET(value) (((value) << 0) & 0x000003ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_QOSPRIORITYEN. + */ +struct ALT_SDR_CTL_QOSPRIORITYEN_s +{ + uint32_t priorityen : 10; /* Per-Port QoS Enable */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_QOSPRIORITYEN. */ +typedef volatile struct ALT_SDR_CTL_QOSPRIORITYEN_s ALT_SDR_CTL_QOSPRIORITYEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_QOSPRIORITYEN register from the beginning of the component. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_OFST 0xa8 + +/* + * Register : Scheduler priority Register - mppriority + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------- + * [29:0] | RW | Unknown | Port User Priorities + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port User Priorities - userpriority + * + * Set absolute user priority of the port. Each port is represented by a 3 bit + * value, 000=lowest priority, 111=highest priority. Port 0 is bits 2:0. Port + * number offset corresponds to the control port assignment. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_MSB 29 +/* The width in bits of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_WIDTH 30 +/* The mask used to set the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET_MSK 0x3fffffff +/* The mask used to clear the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_CLR_MSK 0xc0000000 +/* The reset value of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY field value from a register. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_GET(value) (((value) & 0x3fffffff) >> 0) +/* Produces a ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET(value) (((value) << 0) & 0x3fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPPRIORITY. + */ +struct ALT_SDR_CTL_MPPRIORITY_s +{ + uint32_t userpriority : 30; /* Port User Priorities */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPPRIORITY. */ +typedef volatile struct ALT_SDR_CTL_MPPRIORITY_s ALT_SDR_CTL_MPPRIORITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPPRIORITY register from the beginning of the component. */ +#define ALT_SDR_CTL_MPPRIORITY_OFST 0xac + +/* + * Register : Controller Command Pool Priority Remap Register - remappriority + * + * This register controls the priority for transactions in the controller command + * pool. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------- + * [7:0] | RW | Unknown | Priority Remap + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Priority Remap - priorityremap + * + * Set bit N of this register to the value to a one to enable the controller + * command pool priority bit of a transaction from MPFE priority N + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_MSB 7 +/* The width in bits of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field is UNKNOWN. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP field value from a register. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_REMAPPRIORITY. + */ +struct ALT_SDR_CTL_REMAPPRIORITY_s +{ + uint32_t priorityremap : 8; /* Priority Remap */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_REMAPPRIORITY. */ +typedef volatile struct ALT_SDR_CTL_REMAPPRIORITY_s ALT_SDR_CTL_REMAPPRIORITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_REMAPPRIORITY register from the beginning of the component. */ +#define ALT_SDR_CTL_REMAPPRIORITY_OFST 0xe0 + +/* + * Register Group : Port Sum of Weight Register - ALT_SDR_CTL_MPWT + * Port Sum of Weight Register + * + * This register is used to configure the DRAM burst operation scheduling. + * + */ +/* + * Register : Port Sum of Weight Register[1/4] - mpweight_0_4 + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------- + * [31:0] | RW | Unknown | Port Static Weights[31:0] + * + */ +/* + * Field : Port Static Weights[31:0] - staticweight_31_0 + * + * Set static weight of the port. Each port is programmed with a 5 bit value. + * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_MSB 31 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_WIDTH 32 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4. + */ +struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s +{ + uint32_t staticweight_31_0 : 32; /* Port Static Weights[31:0] */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4. */ +typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register from the beginning of the component. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST 0x0 +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST)) + +/* + * Register : Port Sum of Weight Register[2/4] - mpweight_1_4 + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [17:0] | RW | Unknown | Port Static Weights[49:32] + * [31:18] | RW | Unknown | Port Sum of Weights[13:0] + * + */ +/* + * Field : Port Static Weights[49:32] - staticweight_49_32 + * + * Set static weight of the port. Each port is programmed with a 5 bit value. + * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_MSB 17 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_WIDTH 18 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET_MSK 0x0003ffff +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_CLR_MSK 0xfffc0000 +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_GET(value) (((value) & 0x0003ffff) >> 0) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET(value) (((value) << 0) & 0x0003ffff) + +/* + * Field : Port Sum of Weights[13:0] - sumofweights_13_0 + * + * Set the sum of static weights for particular user priority. This register is + * used as part of the deficit round robin implementation. It should be set to the + * sum of the weights for the ports + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_MSB 31 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_WIDTH 14 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET_MSK 0xfffc0000 +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_CLR_MSK 0x0003ffff +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_GET(value) (((value) & 0xfffc0000) >> 18) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET(value) (((value) << 18) & 0xfffc0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4. + */ +struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s +{ + uint32_t staticweight_49_32 : 18; /* Port Static Weights[49:32] */ + uint32_t sumofweights_13_0 : 14; /* Port Sum of Weights[13:0] */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4. */ +typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register from the beginning of the component. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST 0x4 +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST)) + +/* + * Register : Port Sum of Weight Register[3/4] - mpweight_2_4 + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------- + * [31:0] | RW | Unknown | Port Sum of Weights[45:14] + * + */ +/* + * Field : Port Sum of Weights[45:14] - sumofweights_45_14 + * + * Set the sum of static weights for particular user priority. This register is + * used as part of the deficit round robin implementation. It should be set to the + * sum of the weights for the ports + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_MSB 31 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_WIDTH 32 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4. + */ +struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s +{ + uint32_t sumofweights_45_14 : 32; /* Port Sum of Weights[45:14] */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4. */ +typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register from the beginning of the component. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST 0x8 +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST)) + +/* + * Register : Port Sum of Weight Register[4/4] - mpweight_3_4 + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [17:0] | RW | Unknown | Port Sum of Weights[63:46] + * [31:18] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port Sum of Weights[63:46] - sumofweights_63_46 + * + * Set the sum of static weights for particular user priority. This register is + * used as part of the deficit round robin implementation. It should be set to the + * sum of the weights for the ports + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_MSB 17 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_WIDTH 18 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET_MSK 0x0003ffff +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_CLR_MSK 0xfffc0000 +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_GET(value) (((value) & 0x0003ffff) >> 0) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET(value) (((value) << 0) & 0x0003ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4. + */ +struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s +{ + uint32_t sumofweights_63_46 : 18; /* Port Sum of Weights[63:46] */ + uint32_t : 14; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4. */ +typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register from the beginning of the component. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST 0xc +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SDR_CTL_MPWT. + */ +struct ALT_SDR_CTL_MPWT_s +{ + volatile ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t mpweight_0_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */ + volatile ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t mpweight_1_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */ + volatile ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t mpweight_2_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */ + volatile ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t mpweight_3_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */ +}; + +/* The typedef declaration for register group ALT_SDR_CTL_MPWT. */ +typedef volatile struct ALT_SDR_CTL_MPWT_s ALT_SDR_CTL_MPWT_t; +/* The struct declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */ +struct ALT_SDR_CTL_MPWT_raw_s +{ + volatile uint32_t mpweight_0_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */ + volatile uint32_t mpweight_1_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */ + volatile uint32_t mpweight_2_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */ + volatile uint32_t mpweight_3_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */ +typedef volatile struct ALT_SDR_CTL_MPWT_raw_s ALT_SDR_CTL_MPWT_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SDR_CTL. + */ +struct ALT_SDR_CTL_s +{ + volatile ALT_SDR_CTL_CTLCFG_t ctrlcfg; /* ALT_SDR_CTL_CTLCFG */ + volatile ALT_SDR_CTL_DRAMTIMING1_t dramtiming1; /* ALT_SDR_CTL_DRAMTIMING1 */ + volatile ALT_SDR_CTL_DRAMTIMING2_t dramtiming2; /* ALT_SDR_CTL_DRAMTIMING2 */ + volatile ALT_SDR_CTL_DRAMTIMING3_t dramtiming3; /* ALT_SDR_CTL_DRAMTIMING3 */ + volatile ALT_SDR_CTL_DRAMTIMING4_t dramtiming4; /* ALT_SDR_CTL_DRAMTIMING4 */ + volatile ALT_SDR_CTL_LOWPWRTIMING_t lowpwrtiming; /* ALT_SDR_CTL_LOWPWRTIMING */ + volatile ALT_SDR_CTL_DRAMODT_t dramodt; /* ALT_SDR_CTL_DRAMODT */ + volatile uint32_t _pad_0x1c_0x2b[4]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_DRAMADDRW_t dramaddrw; /* ALT_SDR_CTL_DRAMADDRW */ + volatile ALT_SDR_CTL_DRAMIFWIDTH_t dramifwidth; /* ALT_SDR_CTL_DRAMIFWIDTH */ + volatile ALT_SDR_CTL_DRAMDEVWIDTH_t dramdevwidth; /* ALT_SDR_CTL_DRAMDEVWIDTH */ + volatile ALT_SDR_CTL_DRAMSTS_t dramsts; /* ALT_SDR_CTL_DRAMSTS */ + volatile ALT_SDR_CTL_DRAMINTR_t dramintr; /* ALT_SDR_CTL_DRAMINTR */ + volatile ALT_SDR_CTL_SBECOUNT_t sbecount; /* ALT_SDR_CTL_SBECOUNT */ + volatile ALT_SDR_CTL_DBECOUNT_t dbecount; /* ALT_SDR_CTL_DBECOUNT */ + volatile ALT_SDR_CTL_ERRADDR_t erraddr; /* ALT_SDR_CTL_ERRADDR */ + volatile ALT_SDR_CTL_DROPCOUNT_t dropcount; /* ALT_SDR_CTL_DROPCOUNT */ + volatile ALT_SDR_CTL_DROPADDR_t dropaddr; /* ALT_SDR_CTL_DROPADDR */ + volatile ALT_SDR_CTL_LOWPWREQ_t lowpwreq; /* ALT_SDR_CTL_LOWPWREQ */ + volatile ALT_SDR_CTL_LOWPWRACK_t lowpwrack; /* ALT_SDR_CTL_LOWPWRACK */ + volatile ALT_SDR_CTL_STATICCFG_t staticcfg; /* ALT_SDR_CTL_STATICCFG */ + volatile ALT_SDR_CTL_CTLWIDTH_t ctrlwidth; /* ALT_SDR_CTL_CTLWIDTH */ + volatile uint32_t _pad_0x64_0x7b[6]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_PORTCFG_t portcfg; /* ALT_SDR_CTL_PORTCFG */ + volatile ALT_SDR_CTL_FPGAPORTRST_t fpgaportrst; /* ALT_SDR_CTL_FPGAPORTRST */ + volatile uint32_t _pad_0x84_0x8b[2]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_PROTPORTDEFAULT_t protportdefault; /* ALT_SDR_CTL_PROTPORTDEFAULT */ + volatile ALT_SDR_CTL_PROTRULEADDR_t protruleaddr; /* ALT_SDR_CTL_PROTRULEADDR */ + volatile ALT_SDR_CTL_PROTRULEID_t protruleid; /* ALT_SDR_CTL_PROTRULEID */ + volatile ALT_SDR_CTL_PROTRULEDATA_t protruledata; /* ALT_SDR_CTL_PROTRULEDATA */ + volatile ALT_SDR_CTL_PROTRULERDWR_t protrulerdwr; /* ALT_SDR_CTL_PROTRULERDWR */ + volatile ALT_SDR_CTL_QOSLOWPRI_t qoslowpri; /* ALT_SDR_CTL_QOSLOWPRI */ + volatile ALT_SDR_CTL_QOSHIGHPRI_t qoshighpri; /* ALT_SDR_CTL_QOSHIGHPRI */ + volatile ALT_SDR_CTL_QOSPRIORITYEN_t qospriorityen; /* ALT_SDR_CTL_QOSPRIORITYEN */ + volatile ALT_SDR_CTL_MPPRIORITY_t mppriority; /* ALT_SDR_CTL_MPPRIORITY */ + volatile ALT_SDR_CTL_MPWT_t ctrlgrp_mpweight; /* ALT_SDR_CTL_MPWT */ + volatile uint32_t _pad_0xc0_0xdf[8]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_REMAPPRIORITY_t remappriority; /* ALT_SDR_CTL_REMAPPRIORITY */ + volatile uint32_t _pad_0xe4_0x1000[967]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SDR_CTL. */ +typedef volatile struct ALT_SDR_CTL_s ALT_SDR_CTL_t; +/* The struct declaration for the raw register contents of register group ALT_SDR_CTL. */ +struct ALT_SDR_CTL_raw_s +{ + volatile uint32_t ctrlcfg; /* ALT_SDR_CTL_CTLCFG */ + volatile uint32_t dramtiming1; /* ALT_SDR_CTL_DRAMTIMING1 */ + volatile uint32_t dramtiming2; /* ALT_SDR_CTL_DRAMTIMING2 */ + volatile uint32_t dramtiming3; /* ALT_SDR_CTL_DRAMTIMING3 */ + volatile uint32_t dramtiming4; /* ALT_SDR_CTL_DRAMTIMING4 */ + volatile uint32_t lowpwrtiming; /* ALT_SDR_CTL_LOWPWRTIMING */ + volatile uint32_t dramodt; /* ALT_SDR_CTL_DRAMODT */ + volatile uint32_t _pad_0x1c_0x2b[4]; /* *UNDEFINED* */ + volatile uint32_t dramaddrw; /* ALT_SDR_CTL_DRAMADDRW */ + volatile uint32_t dramifwidth; /* ALT_SDR_CTL_DRAMIFWIDTH */ + volatile uint32_t dramdevwidth; /* ALT_SDR_CTL_DRAMDEVWIDTH */ + volatile uint32_t dramsts; /* ALT_SDR_CTL_DRAMSTS */ + volatile uint32_t dramintr; /* ALT_SDR_CTL_DRAMINTR */ + volatile uint32_t sbecount; /* ALT_SDR_CTL_SBECOUNT */ + volatile uint32_t dbecount; /* ALT_SDR_CTL_DBECOUNT */ + volatile uint32_t erraddr; /* ALT_SDR_CTL_ERRADDR */ + volatile uint32_t dropcount; /* ALT_SDR_CTL_DROPCOUNT */ + volatile uint32_t dropaddr; /* ALT_SDR_CTL_DROPADDR */ + volatile uint32_t lowpwreq; /* ALT_SDR_CTL_LOWPWREQ */ + volatile uint32_t lowpwrack; /* ALT_SDR_CTL_LOWPWRACK */ + volatile uint32_t staticcfg; /* ALT_SDR_CTL_STATICCFG */ + volatile uint32_t ctrlwidth; /* ALT_SDR_CTL_CTLWIDTH */ + volatile uint32_t _pad_0x64_0x7b[6]; /* *UNDEFINED* */ + volatile uint32_t portcfg; /* ALT_SDR_CTL_PORTCFG */ + volatile uint32_t fpgaportrst; /* ALT_SDR_CTL_FPGAPORTRST */ + volatile uint32_t _pad_0x84_0x8b[2]; /* *UNDEFINED* */ + volatile uint32_t protportdefault; /* ALT_SDR_CTL_PROTPORTDEFAULT */ + volatile uint32_t protruleaddr; /* ALT_SDR_CTL_PROTRULEADDR */ + volatile uint32_t protruleid; /* ALT_SDR_CTL_PROTRULEID */ + volatile uint32_t protruledata; /* ALT_SDR_CTL_PROTRULEDATA */ + volatile uint32_t protrulerdwr; /* ALT_SDR_CTL_PROTRULERDWR */ + volatile uint32_t qoslowpri; /* ALT_SDR_CTL_QOSLOWPRI */ + volatile uint32_t qoshighpri; /* ALT_SDR_CTL_QOSHIGHPRI */ + volatile uint32_t qospriorityen; /* ALT_SDR_CTL_QOSPRIORITYEN */ + volatile uint32_t mppriority; /* ALT_SDR_CTL_MPPRIORITY */ + volatile ALT_SDR_CTL_MPWT_raw_t ctrlgrp_mpweight; /* ALT_SDR_CTL_MPWT */ + volatile uint32_t _pad_0xc0_0xdf[8]; /* *UNDEFINED* */ + volatile uint32_t remappriority; /* ALT_SDR_CTL_REMAPPRIORITY */ + volatile uint32_t _pad_0xe4_0x1000[967]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SDR_CTL. */ +typedef volatile struct ALT_SDR_CTL_raw_s ALT_SDR_CTL_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SDR. + */ +struct ALT_SDR_s +{ + volatile uint32_t _pad_0x0_0x4fff[5120]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_t ctrlgrp; /* ALT_SDR_CTL */ + volatile uint32_t _pad_0x6000_0x20000[26624]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SDR. */ +typedef volatile struct ALT_SDR_s ALT_SDR_t; +/* The struct declaration for the raw register contents of register group ALT_SDR. */ +struct ALT_SDR_raw_s +{ + volatile uint32_t _pad_0x0_0x4fff[5120]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_raw_t ctrlgrp; /* ALT_SDR_CTL */ + volatile uint32_t _pad_0x6000_0x20000[26624]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SDR. */ +typedef volatile struct ALT_SDR_raw_s ALT_SDR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_SDR_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h new file mode 100644 index 0000000000..fce6d6e11e --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h @@ -0,0 +1,24810 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_SYSMGR */ + +#ifndef __ALTERA_ALT_SYSMGR_H__ +#define __ALTERA_ALT_SYSMGR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : System Manager Module - ALT_SYSMGR + * System Manager Module + * + * Registers in the System Manager module + * + */ +/* + * Register : Silicon ID1 Register - siliconid1 + * + * Specifies Silicon ID and revision number. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------- + * [15:0] | R | 0x1 | Silicon Revision + * [31:16] | R | 0x0 | Silicon ID + * + */ +/* + * Field : Silicon Revision - rev + * + * Silicon revision number. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_SYSMGR_SILICONID1_REV_E_REV1 | 0x1 | Revision 1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SILICONID1_REV + * + * Revision 1 + */ +#define ALT_SYSMGR_SILICONID1_REV_E_REV1 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */ +#define ALT_SYSMGR_SILICONID1_REV_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */ +#define ALT_SYSMGR_SILICONID1_REV_MSB 15 +/* The width in bits of the ALT_SYSMGR_SILICONID1_REV register field. */ +#define ALT_SYSMGR_SILICONID1_REV_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_SILICONID1_REV register field value. */ +#define ALT_SYSMGR_SILICONID1_REV_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SYSMGR_SILICONID1_REV register field value. */ +#define ALT_SYSMGR_SILICONID1_REV_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SYSMGR_SILICONID1_REV register field. */ +#define ALT_SYSMGR_SILICONID1_REV_RESET 0x1 +/* Extracts the ALT_SYSMGR_SILICONID1_REV field value from a register. */ +#define ALT_SYSMGR_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SYSMGR_SILICONID1_REV register field value suitable for setting the register. */ +#define ALT_SYSMGR_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Silicon ID - id + * + * Silicon ID + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------------------------------------- + * ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV | 0x0 | HPS in Cyclone V and Arria V SoC FPGA devices + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SILICONID1_ID + * + * HPS in Cyclone V and Arria V SoC FPGA devices + */ +#define ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */ +#define ALT_SYSMGR_SILICONID1_ID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */ +#define ALT_SYSMGR_SILICONID1_ID_MSB 31 +/* The width in bits of the ALT_SYSMGR_SILICONID1_ID register field. */ +#define ALT_SYSMGR_SILICONID1_ID_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_SILICONID1_ID register field value. */ +#define ALT_SYSMGR_SILICONID1_ID_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_SYSMGR_SILICONID1_ID register field value. */ +#define ALT_SYSMGR_SILICONID1_ID_CLR_MSK 0x0000ffff +/* The reset value of the ALT_SYSMGR_SILICONID1_ID register field. */ +#define ALT_SYSMGR_SILICONID1_ID_RESET 0x0 +/* Extracts the ALT_SYSMGR_SILICONID1_ID field value from a register. */ +#define ALT_SYSMGR_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_SYSMGR_SILICONID1_ID register field value suitable for setting the register. */ +#define ALT_SYSMGR_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SILICONID1. + */ +struct ALT_SYSMGR_SILICONID1_s +{ + const uint32_t rev : 16; /* Silicon Revision */ + const uint32_t id : 16; /* Silicon ID */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SILICONID1. */ +typedef volatile struct ALT_SYSMGR_SILICONID1_s ALT_SYSMGR_SILICONID1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SILICONID1 register from the beginning of the component. */ +#define ALT_SYSMGR_SILICONID1_OFST 0x0 + +/* + * Register : Silicon ID2 Register - siliconid2 + * + * Reserved for future use. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | Reserved + * + */ +/* + * Field : Reserved - rsv + * + * Reserved for future use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */ +#define ALT_SYSMGR_SILICONID2_RSV_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */ +#define ALT_SYSMGR_SILICONID2_RSV_MSB 31 +/* The width in bits of the ALT_SYSMGR_SILICONID2_RSV register field. */ +#define ALT_SYSMGR_SILICONID2_RSV_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_SILICONID2_RSV register field value. */ +#define ALT_SYSMGR_SILICONID2_RSV_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_SILICONID2_RSV register field value. */ +#define ALT_SYSMGR_SILICONID2_RSV_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_SILICONID2_RSV register field. */ +#define ALT_SYSMGR_SILICONID2_RSV_RESET 0x0 +/* Extracts the ALT_SYSMGR_SILICONID2_RSV field value from a register. */ +#define ALT_SYSMGR_SILICONID2_RSV_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_SILICONID2_RSV register field value suitable for setting the register. */ +#define ALT_SYSMGR_SILICONID2_RSV_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SILICONID2. + */ +struct ALT_SYSMGR_SILICONID2_s +{ + const uint32_t rsv : 32; /* Reserved */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SILICONID2. */ +typedef volatile struct ALT_SYSMGR_SILICONID2_s ALT_SYSMGR_SILICONID2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SILICONID2 register from the beginning of the component. */ +#define ALT_SYSMGR_SILICONID2_OFST 0x4 + +/* + * Register : L4 Watchdog Debug Register - wddbg + * + * Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These + * control registers are used to drive the pause input signal of the L4 watchdogs. + * Note that the watchdogs built into the MPU automatically are paused when their + * associated CPU enters debug mode. Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [1:0] | RW | 0x3 | Debug Mode + * [3:2] | RW | 0x3 | Debug Mode + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debug Mode - mode_0 + * + * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index + * matches L4 watchdog index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE | 0x0 | Continue normal operation ignoring debug mode of + * : | | CPUs + * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 | 0x1 | Pause normal operation only if CPU0 is in debug + * : | | mode + * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 | 0x2 | Pause normal operation only if CPU1 is in debug + * : | | mode + * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER | 0x3 | Pause normal operation if CPU0 or CPU1 is in + * : | | debug mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 + * + * Continue normal operation ignoring debug mode of CPUs + */ +#define ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 + * + * Pause normal operation only if CPU0 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 + * + * Pause normal operation only if CPU1 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 + * + * Pause normal operation if CPU0 or CPU1 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_0_MSB 1 +/* The width in bits of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_0_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_WDDBG_MOD_0 register field value. */ +#define ALT_SYSMGR_WDDBG_MOD_0_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_0 register field value. */ +#define ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_0_RESET 0x3 +/* Extracts the ALT_SYSMGR_WDDBG_MOD_0 field value from a register. */ +#define ALT_SYSMGR_WDDBG_MOD_0_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_WDDBG_MOD_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_WDDBG_MOD_0_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Debug Mode - mode_1 + * + * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index + * matches L4 watchdog index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE | 0x0 | Continue normal operation ignoring debug mode of + * : | | CPUs + * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 | 0x1 | Pause normal operation only if CPU0 is in debug + * : | | mode + * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 | 0x2 | Pause normal operation only if CPU1 is in debug + * : | | mode + * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER | 0x3 | Pause normal operation if CPU0 or CPU1 is in + * : | | debug mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 + * + * Continue normal operation ignoring debug mode of CPUs + */ +#define ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 + * + * Pause normal operation only if CPU0 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 + * + * Pause normal operation only if CPU1 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 + * + * Pause normal operation if CPU0 or CPU1 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_1_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_1_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_WDDBG_MOD_1 register field value. */ +#define ALT_SYSMGR_WDDBG_MOD_1_SET_MSK 0x0000000c +/* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_1 register field value. */ +#define ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_1_RESET 0x3 +/* Extracts the ALT_SYSMGR_WDDBG_MOD_1 field value from a register. */ +#define ALT_SYSMGR_WDDBG_MOD_1_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_SYSMGR_WDDBG_MOD_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_WDDBG_MOD_1_SET(value) (((value) << 2) & 0x0000000c) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_WDDBG. + */ +struct ALT_SYSMGR_WDDBG_s +{ + uint32_t mode_0 : 2; /* Debug Mode */ + uint32_t mode_1 : 2; /* Debug Mode */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_WDDBG. */ +typedef volatile struct ALT_SYSMGR_WDDBG_s ALT_SYSMGR_WDDBG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_WDDBG register from the beginning of the component. */ +#define ALT_SYSMGR_WDDBG_OFST 0x10 + +/* + * Register : Boot Info Register - bootinfo + * + * Provides access to boot configuration information. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------- + * [2:0] | R | Unknown | Boot Select + * [4:3] | R | Unknown | Clock Select + * [7:5] | R | Unknown | HPS Pin Boot Select + * [9:8] | R | Unknown | HPS Pin Clock Select + * [31:10] | ??? | Unknown | *UNDEFINED* + * + */ +/* + * Field : Boot Select - bsel + * + * The boot select field specifies the boot source. It is read by the Boot ROM code + * on a cold or warm reset to determine the boot source. + * + * The HPS BSEL pins value are sampled upon deassertion of cold reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------------|:------|:----------------------------------- + * ALT_SYSMGR_BOOT_BSEL_E_RSVD | 0x0 | Reserved + * ALT_SYSMGR_BOOT_BSEL_E_FPGA | 0x1 | FPGA (HPS2FPGA Bridge) + * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V | 0x2 | NAND Flash (1.8v) + * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V | 0x3 | NAND Flash (3.0v) + * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V | 0x4 | SD/MMC External Transceiver (1.8v) + * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V | 0x5 | SD/MMC Internal Transceiver (3.0v) + * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V | 0x6 | QSPI Flash (1.8v) + * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V | 0x7 | QSPI Flash (3.0v) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * Reserved + */ +#define ALT_SYSMGR_BOOT_BSEL_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * FPGA (HPS2FPGA Bridge) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_FPGA 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * NAND Flash (1.8v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * NAND Flash (3.0v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * SD/MMC External Transceiver (1.8v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * SD/MMC Internal Transceiver (3.0v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * QSPI Flash (1.8v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * QSPI Flash (3.0v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */ +#define ALT_SYSMGR_BOOT_BSEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */ +#define ALT_SYSMGR_BOOT_BSEL_MSB 2 +/* The width in bits of the ALT_SYSMGR_BOOT_BSEL register field. */ +#define ALT_SYSMGR_BOOT_BSEL_WIDTH 3 +/* The mask used to set the ALT_SYSMGR_BOOT_BSEL register field value. */ +#define ALT_SYSMGR_BOOT_BSEL_SET_MSK 0x00000007 +/* The mask used to clear the ALT_SYSMGR_BOOT_BSEL register field value. */ +#define ALT_SYSMGR_BOOT_BSEL_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_SYSMGR_BOOT_BSEL register field is UNKNOWN. */ +#define ALT_SYSMGR_BOOT_BSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_BOOT_BSEL field value from a register. */ +#define ALT_SYSMGR_BOOT_BSEL_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_SYSMGR_BOOT_BSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_BOOT_BSEL_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : Clock Select - csel + * + * The clock select field specifies clock information for booting. The clock select + * encoding is a function of the CSEL value. The clock select field is read by the + * Boot ROM code on a cold or warm reset when booting from a flash device to get + * information about how to setup the HPS clocking to boot from the specified clock + * device. + * + * The encoding of the clock select field is specified by the enum associated with + * this field. + * + * The HPS CSEL pins value are sampled upon deassertion of cold reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------ + * ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 | 0x0 | QSPI device clock is osc1_clk divided by 4, + * : | | SD/MMC device clock is osc1_clk divided by 4, + * : | | NAND device operation is osc1_clk divided by 25 + * ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 | 0x1 | QSPI device clock is osc1_clk divided by 2, + * : | | SD/MMC device clock is osc1_clk divided by 1, + * : | | NAND device operation is osc1_clk multiplied by + * : | | 20/25 + * ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 | 0x2 | QSPI device clock is osc1_clk divided by 1, + * : | | SD/MMC device clock is osc1_clk divided by 2, + * : | | NAND device operation is osc1_clk multiplied by + * : | | 10/25 + * ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 | 0x3 | QSPI device clock is osc1_clk multiplied by 2, + * : | | SD/MMC device clock is osc1_clk divided by 4, + * : | | NAND device operation is osc1_clk multiplied by + * : | | 5/25 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL + * + * QSPI device clock is osc1_clk divided by 4, SD/MMC device clock is osc1_clk + * divided by 4, NAND device operation is osc1_clk divided by 25 + */ +#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL + * + * QSPI device clock is osc1_clk divided by 2, SD/MMC device clock is osc1_clk + * divided by 1, NAND device operation is osc1_clk multiplied by 20/25 + */ +#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL + * + * QSPI device clock is osc1_clk divided by 1, SD/MMC device clock is osc1_clk + * divided by 2, NAND device operation is osc1_clk multiplied by 10/25 + */ +#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL + * + * QSPI device clock is osc1_clk multiplied by 2, SD/MMC device clock is osc1_clk + * divided by 4, NAND device operation is osc1_clk multiplied by 5/25 + */ +#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_CSEL register field. */ +#define ALT_SYSMGR_BOOT_CSEL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_CSEL register field. */ +#define ALT_SYSMGR_BOOT_CSEL_MSB 4 +/* The width in bits of the ALT_SYSMGR_BOOT_CSEL register field. */ +#define ALT_SYSMGR_BOOT_CSEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_BOOT_CSEL register field value. */ +#define ALT_SYSMGR_BOOT_CSEL_SET_MSK 0x00000018 +/* The mask used to clear the ALT_SYSMGR_BOOT_CSEL register field value. */ +#define ALT_SYSMGR_BOOT_CSEL_CLR_MSK 0xffffffe7 +/* The reset value of the ALT_SYSMGR_BOOT_CSEL register field is UNKNOWN. */ +#define ALT_SYSMGR_BOOT_CSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_BOOT_CSEL field value from a register. */ +#define ALT_SYSMGR_BOOT_CSEL_GET(value) (((value) & 0x00000018) >> 3) +/* Produces a ALT_SYSMGR_BOOT_CSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_BOOT_CSEL_SET(value) (((value) << 3) & 0x00000018) + +/* + * Field : HPS Pin Boot Select - pinbsel + * + * Specifies the sampled value of the HPS BSEL pins. The value of HPS BSEL pins are + * sampled upon deassertion of cold reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field. */ +#define ALT_SYSMGR_BOOT_PINBSEL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field. */ +#define ALT_SYSMGR_BOOT_PINBSEL_MSB 7 +/* The width in bits of the ALT_SYSMGR_BOOT_PINBSEL register field. */ +#define ALT_SYSMGR_BOOT_PINBSEL_WIDTH 3 +/* The mask used to set the ALT_SYSMGR_BOOT_PINBSEL register field value. */ +#define ALT_SYSMGR_BOOT_PINBSEL_SET_MSK 0x000000e0 +/* The mask used to clear the ALT_SYSMGR_BOOT_PINBSEL register field value. */ +#define ALT_SYSMGR_BOOT_PINBSEL_CLR_MSK 0xffffff1f +/* The reset value of the ALT_SYSMGR_BOOT_PINBSEL register field is UNKNOWN. */ +#define ALT_SYSMGR_BOOT_PINBSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_BOOT_PINBSEL field value from a register. */ +#define ALT_SYSMGR_BOOT_PINBSEL_GET(value) (((value) & 0x000000e0) >> 5) +/* Produces a ALT_SYSMGR_BOOT_PINBSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_BOOT_PINBSEL_SET(value) (((value) << 5) & 0x000000e0) + +/* + * Field : HPS Pin Clock Select - pincsel + * + * Specifies the sampled value of the HPS CSEL pins. The value of HPS CSEL pins are + * sampled upon deassertion of cold reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field. */ +#define ALT_SYSMGR_BOOT_PINCSEL_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field. */ +#define ALT_SYSMGR_BOOT_PINCSEL_MSB 9 +/* The width in bits of the ALT_SYSMGR_BOOT_PINCSEL register field. */ +#define ALT_SYSMGR_BOOT_PINCSEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_BOOT_PINCSEL register field value. */ +#define ALT_SYSMGR_BOOT_PINCSEL_SET_MSK 0x00000300 +/* The mask used to clear the ALT_SYSMGR_BOOT_PINCSEL register field value. */ +#define ALT_SYSMGR_BOOT_PINCSEL_CLR_MSK 0xfffffcff +/* The reset value of the ALT_SYSMGR_BOOT_PINCSEL register field is UNKNOWN. */ +#define ALT_SYSMGR_BOOT_PINCSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_BOOT_PINCSEL field value from a register. */ +#define ALT_SYSMGR_BOOT_PINCSEL_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_SYSMGR_BOOT_PINCSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_BOOT_PINCSEL_SET(value) (((value) << 8) & 0x00000300) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_BOOT. + */ +struct ALT_SYSMGR_BOOT_s +{ + const uint32_t bsel : 3; /* Boot Select */ + const uint32_t csel : 2; /* Clock Select */ + const uint32_t pinbsel : 3; /* HPS Pin Boot Select */ + const uint32_t pincsel : 2; /* HPS Pin Clock Select */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_BOOT. */ +typedef volatile struct ALT_SYSMGR_BOOT_s ALT_SYSMGR_BOOT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_BOOT register from the beginning of the component. */ +#define ALT_SYSMGR_BOOT_OFST 0x14 + +/* + * Register : HPS Info Register - hpsinfo + * + * Provides information about the HPS capabilities. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [0] | R | Unknown | Dual Core + * [1] | R | Unknown | CAN + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Dual Core - dualcore + * + * Indicates if CPU1 is available in MPU or not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE | 0x0 | Not dual-core (only CPU0 available). + * ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE | 0x1 | Is dual-core (CPU0 and CPU1 both available). + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_HPSINFO_DUALCORE + * + * Not dual-core (only CPU0 available). + */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_HPSINFO_DUALCORE + * + * Is dual-core (CPU0 and CPU1 both available). + */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_MSB 0 +/* The width in bits of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_HPSINFO_DUALCORE register field value. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_HPSINFO_DUALCORE register field value. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_HPSINFO_DUALCORE register field is UNKNOWN. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_RESET 0x0 +/* Extracts the ALT_SYSMGR_HPSINFO_DUALCORE field value from a register. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_HPSINFO_DUALCORE register field value suitable for setting the register. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : CAN - can + * + * Indicates if CAN0 and CAN1 controllers are available or not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------- + * ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE | 0x0 | CAN0 and CAN1 are not available. + * ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE | 0x1 | CAN0 and CAN1 are available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_HPSINFO_CAN + * + * CAN0 and CAN1 are not available. + */ +#define ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_HPSINFO_CAN + * + * CAN0 and CAN1 are available. + */ +#define ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_HPSINFO_CAN register field. */ +#define ALT_SYSMGR_HPSINFO_CAN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_HPSINFO_CAN register field. */ +#define ALT_SYSMGR_HPSINFO_CAN_MSB 1 +/* The width in bits of the ALT_SYSMGR_HPSINFO_CAN register field. */ +#define ALT_SYSMGR_HPSINFO_CAN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_HPSINFO_CAN register field value. */ +#define ALT_SYSMGR_HPSINFO_CAN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_HPSINFO_CAN register field value. */ +#define ALT_SYSMGR_HPSINFO_CAN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_HPSINFO_CAN register field is UNKNOWN. */ +#define ALT_SYSMGR_HPSINFO_CAN_RESET 0x0 +/* Extracts the ALT_SYSMGR_HPSINFO_CAN field value from a register. */ +#define ALT_SYSMGR_HPSINFO_CAN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_HPSINFO_CAN register field value suitable for setting the register. */ +#define ALT_SYSMGR_HPSINFO_CAN_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_HPSINFO. + */ +struct ALT_SYSMGR_HPSINFO_s +{ + const uint32_t dualcore : 1; /* Dual Core */ + const uint32_t can : 1; /* CAN */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_HPSINFO. */ +typedef volatile struct ALT_SYSMGR_HPSINFO_s ALT_SYSMGR_HPSINFO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_HPSINFO register from the beginning of the component. */ +#define ALT_SYSMGR_HPSINFO_OFST 0x18 + +/* + * Register : Parity Fail Injection Register - parityinj + * + * Inject parity failures into the parity-protected RAMs in the MPU. Allows + * software to test the parity failure interrupt handler. The field array index + * corresponds to the CPU index. + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------------------- + * [0] | RW | 0x0 | Parity Fail Injection for Data Cache Data RAM + * [1] | RW | 0x0 | Parity Fail Injection for Data Cache Data RAM + * [2] | RW | 0x0 | Parity Fail Injection for Data Cache Tag RAM + * [3] | RW | 0x0 | Parity Fail Injection for Data Cache Tag RAM + * [4] | RW | 0x0 | Parity Fail Injection for Data Cache Outer RAM + * [5] | RW | 0x0 | Parity Fail Injection for Data Cache Outer RAM + * [6] | RW | 0x0 | Parity Fail Injection for Main TLB RAM + * [7] | RW | 0x0 | Parity Fail Injection for Main TLB RAM + * [8] | RW | 0x0 | Parity Fail Injection for Instruction Cache Data RAM + * [9] | RW | 0x0 | Parity Fail Injection for Instruction Cache Data RAM + * [10] | RW | 0x0 | Parity Fail Injection for Instruction Cache Tag RAM + * [11] | RW | 0x0 | Parity Fail Injection for Instruction Cache Tag RAM + * [12] | RW | 0x0 | Parity Fail Injection for GHB RAM + * [13] | RW | 0x0 | Parity Fail Injection for GHB RAM + * [14] | RW | 0x0 | Parity Fail Injection for BTAC RAM + * [15] | RW | 0x0 | Parity Fail Injection for BTAC RAM + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Parity Fail Injection for Data Cache Data RAM - dcdata_0 + * + * If 1, injecting parity error to Data Cache Data RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_MSB 0 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCDATA_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Parity Fail Injection for Data Cache Data RAM - dcdata_1 + * + * If 1, injecting parity error to Data Cache Data RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_MSB 1 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCDATA_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Parity Fail Injection for Data Cache Tag RAM - dctag_0 + * + * If 1, injecting parity error to Data Cache Tag RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_MSB 2 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCTAG_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Parity Fail Injection for Data Cache Tag RAM - dctag_1 + * + * If 1, injecting parity error to Data Cache Tag RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCTAG_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Parity Fail Injection for Data Cache Outer RAM - dcouter_0 + * + * If 1, injecting parity error to Data Cache Outer RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_MSB 4 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCOUTER_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Parity Fail Injection for Data Cache Outer RAM - dcouter_1 + * + * If 1, injecting parity error to Data Cache Outer RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_MSB 5 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCOUTER_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Parity Fail Injection for Main TLB RAM - maintlb_0 + * + * If 1, injecting parity error to Main TLB RAM.The field array index corresponds + * to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_MSB 6 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_MAINTLB_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Parity Fail Injection for Main TLB RAM - maintlb_1 + * + * If 1, injecting parity error to Main TLB RAM.The field array index corresponds + * to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_MSB 7 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_MAINTLB_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Parity Fail Injection for Instruction Cache Data RAM - icdata_0 + * + * If 1, injecting parity error to Instruction Cache Data RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_MSB 8 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_ICDATA_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Parity Fail Injection for Instruction Cache Data RAM - icdata_1 + * + * If 1, injecting parity error to Instruction Cache Data RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_MSB 9 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_ICDATA_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Parity Fail Injection for Instruction Cache Tag RAM - ictag_0 + * + * If 1, injecting parity error to Instruction Cache Tag RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_MSB 10 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_ICTAG_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Parity Fail Injection for Instruction Cache Tag RAM - ictag_1 + * + * If 1, injecting parity error to Instruction Cache Tag RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_MSB 11 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_ICTAG_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Parity Fail Injection for GHB RAM - ghb_0 + * + * If 1, injecting parity error to GHB RAM.The field array index corresponds to the + * CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_MSB 12 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_GHB_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_GHB_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_CLR_MSK 0xffffefff +/* The reset value of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_GHB_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SYSMGR_PARITYINJ_GHB_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Parity Fail Injection for GHB RAM - ghb_1 + * + * If 1, injecting parity error to GHB RAM.The field array index corresponds to the + * CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_MSB 13 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_GHB_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_GHB_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_GHB_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SYSMGR_PARITYINJ_GHB_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Parity Fail Injection for BTAC RAM - btac_0 + * + * If 1, injecting parity error to BTAC RAM.The field array index corresponds to + * the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_MSB 14 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_BTAC_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_SET_MSK 0x00004000 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_BTAC_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_CLR_MSK 0xffffbfff +/* The reset value of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_BTAC_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_SYSMGR_PARITYINJ_BTAC_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Parity Fail Injection for BTAC RAM - btac_1 + * + * If 1, injecting parity error to BTAC RAM.The field array index corresponds to + * the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_MSB 15 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_BTAC_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_SET_MSK 0x00008000 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_BTAC_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_CLR_MSK 0xffff7fff +/* The reset value of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_BTAC_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_SYSMGR_PARITYINJ_BTAC_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PARITYINJ. + */ +struct ALT_SYSMGR_PARITYINJ_s +{ + uint32_t dcdata_0 : 1; /* Parity Fail Injection for Data Cache Data RAM */ + uint32_t dcdata_1 : 1; /* Parity Fail Injection for Data Cache Data RAM */ + uint32_t dctag_0 : 1; /* Parity Fail Injection for Data Cache Tag RAM */ + uint32_t dctag_1 : 1; /* Parity Fail Injection for Data Cache Tag RAM */ + uint32_t dcouter_0 : 1; /* Parity Fail Injection for Data Cache Outer RAM */ + uint32_t dcouter_1 : 1; /* Parity Fail Injection for Data Cache Outer RAM */ + uint32_t maintlb_0 : 1; /* Parity Fail Injection for Main TLB RAM */ + uint32_t maintlb_1 : 1; /* Parity Fail Injection for Main TLB RAM */ + uint32_t icdata_0 : 1; /* Parity Fail Injection for Instruction Cache Data RAM */ + uint32_t icdata_1 : 1; /* Parity Fail Injection for Instruction Cache Data RAM */ + uint32_t ictag_0 : 1; /* Parity Fail Injection for Instruction Cache Tag RAM */ + uint32_t ictag_1 : 1; /* Parity Fail Injection for Instruction Cache Tag RAM */ + uint32_t ghb_0 : 1; /* Parity Fail Injection for GHB RAM */ + uint32_t ghb_1 : 1; /* Parity Fail Injection for GHB RAM */ + uint32_t btac_0 : 1; /* Parity Fail Injection for BTAC RAM */ + uint32_t btac_1 : 1; /* Parity Fail Injection for BTAC RAM */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PARITYINJ. */ +typedef volatile struct ALT_SYSMGR_PARITYINJ_s ALT_SYSMGR_PARITYINJ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PARITYINJ register from the beginning of the component. */ +#define ALT_SYSMGR_PARITYINJ_OFST 0x1c + +/* + * Register Group : FPGA Interface Group - ALT_SYSMGR_FPGAINTF + * FPGA Interface Group + * + * Registers used to enable/disable interfaces between the FPGA and HPS. Required + * for either of the following situations:[list][*]Interfaces that cannot be + * disabled by putting an HPS module associated with the interface into + * reset.[*]HPS modules that accept signals from the FPGA fabric and those signals + * might interfere with the normal operation of the module.[/list]. + * + * All registers are only reset by a cold reset (ignore warm reset). + * + */ +/* + * Register : Global Disable Register - gbl + * + * Used to disable all interfaces between the FPGA and HPS. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x1 | Global Interface + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Global Interface - intf + * + * Used to disable all interfaces between the FPGA and HPS. Software must ensure + * that all interfaces between the FPGA and HPS are inactive before disabling them. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS | 0x0 | All interfaces between FPGA and HPS are + * : | | disabled. + * ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN | 0x1 | Interfaces between FPGA and HPS are not all + * : | | disabled. Interfaces can be indivdually disabled + * : | | by putting the HPS module associated with the + * : | | interface in reset using registers in the Reset + * : | | Manager or by using registers in this register + * : | | group of the System Manager for interfaces + * : | | without an associated module. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF + * + * All interfaces between FPGA and HPS are disabled. + */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF + * + * Interfaces between FPGA and HPS are not all disabled. Interfaces can be + * indivdually disabled by putting the HPS module associated with the interface in + * reset using registers in the Reset Manager or by using registers in this + * register group of the System Manager for interfaces without an associated + * module. + */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_MSB 0 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_GBL_INTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FPGAINTF_GBL_INTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FPGAINTF_GBL. + */ +struct ALT_SYSMGR_FPGAINTF_GBL_s +{ + uint32_t intf : 1; /* Global Interface */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_GBL. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_GBL_s ALT_SYSMGR_FPGAINTF_GBL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FPGAINTF_GBL register from the beginning of the component. */ +#define ALT_SYSMGR_FPGAINTF_GBL_OFST 0x0 + +/* + * Register : Individual Disable Register - indiv + * + * Used to disable individual interfaces between the FPGA and HPS. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | RW | 0x1 | Reset Request Interface + * [1] | RW | 0x1 | JTAG Enable Interface + * [2] | RW | 0x1 | CONFIG_IO Interface + * [3] | RW | 0x1 | Boundary-Scan Interface + * [4] | RW | 0x1 | Trace Interface + * [5] | ??? | 0x1 | *UNDEFINED* + * [6] | RW | 0x1 | STM Event Interface + * [7] | RW | 0x1 | Cross Trigger Interface (CTI) + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Reset Request Interface - rstreqintf + * + * Used to disable the reset request interface. This interface allows logic in the + * FPGA fabric to request HPS resets. This field disables the following reset + * request signals from the FPGA fabric to HPS:[list][*]f2h_cold_rst_req_n - + * Triggers a cold reset of the HPS[*]f2h_warm_rst_req_n - Triggers a warm reset of + * the HPS[*]f2h_dbg_rst_req_n - Triggers a debug reset of the HPS[/list] + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS | 0x0 | Reset request interface is disabled. Logic in + * : | | the FPGA fabric cannot reset the HPS. + * ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN | 0x1 | Reset request interface is enabled. Logic in the + * : | | FPGA fabric can reset the HPS. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF + * + * Reset request interface is disabled. Logic in the FPGA fabric cannot reset the + * HPS. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF + * + * Reset request interface is enabled. Logic in the FPGA fabric can reset the HPS. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_MSB 0 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : JTAG Enable Interface - jtagenintf + * + * Used to disable the JTAG enable interface. This interface allows logic in the + * FPGA fabric to disable the HPS JTAG operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------ + * ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS | 0x0 | JTAG enable interface is disabled. Logic in the + * : | | FPGA fabric cannot disable the HPS JTAG. + * ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN | 0x1 | JTAG enable interface is enabled. Logic in the + * : | | FPGA fabric can disable the HPS JTAG. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF + * + * JTAG enable interface is disabled. Logic in the FPGA fabric cannot disable the + * HPS JTAG. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF + * + * JTAG enable interface is enabled. Logic in the FPGA fabric can disable the HPS + * JTAG. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_MSB 1 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : CONFIG_IO Interface - configiointf + * + * Used to disable the CONFIG_IO interface. This interface allows the FPGA JTAG TAP + * controller to execute the CONFIG_IO instruction and configure all device I/Os + * (FPGA and HPS). This is typically done before executing boundary-scan + * instructions. The CONFIG_IO interface must be enabled before attempting to send + * the CONFIG_IO instruction to the FPGA JTAG TAP controller. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS | 0x0 | CONFIG_IO interface is disabled. Execution of + * : | | the CONFIG_IO instruction in the FPGA JTAG TAP + * : | | controller is unsupported and produces undefined + * : | | results. + * ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN | 0x1 | CONFIG_IO interface is enabled. Execution of the + * : | | CONFIG_IO instruction in the FPGA JTAG TAP + * : | | controller is supported. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF + * + * CONFIG_IO interface is disabled. Execution of the CONFIG_IO instruction in the + * FPGA JTAG TAP controller is unsupported and produces undefined results. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF + * + * CONFIG_IO interface is enabled. Execution of the CONFIG_IO instruction in the + * FPGA JTAG TAP controller is supported. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_MSB 2 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Boundary-Scan Interface - bscanintf + * + * Used to disable the boundary-scan interface. This interface allows the FPGA JTAG + * TAP controller to execute boundary-scan instructions such as SAMPLE/PRELOAD, + * EXTEST, and HIGHZ. The boundary-scan interface must be enabled before attempting + * to send the boundary-scan instructions to the FPGA JTAG TAP controller. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS | 0x0 | Boundary-scan interface is disabled. Execution + * : | | of boundary-scan instructions in the FPGA JTAG + * : | | TAP controller is unsupported and produces + * : | | undefined results. + * ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN | 0x1 | Boundary-scan interface is enabled. Execution of + * : | | the boundary-scan instructions in the FPGA JTAG + * : | | TAP controller is supported. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF + * + * Boundary-scan interface is disabled. Execution of boundary-scan instructions in + * the FPGA JTAG TAP controller is unsupported and produces undefined results. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF + * + * Boundary-scan interface is enabled. Execution of the boundary-scan instructions + * in the FPGA JTAG TAP controller is supported. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_MSB 3 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Trace Interface - traceintf + * + * Used to disable the trace interface. This interface allows the HPS debug logic + * to send trace data to logic in the FPGA fabric. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS | 0x0 | Trace interface is disabled. HPS debug logic + * : | | cannot send trace data to the FPGA fabric. + * ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN | 0x1 | Trace interface is enabled. Other registers in + * : | | the HPS debug logic must be programmmed to + * : | | actually send trace data to the FPGA fabric. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF + * + * Trace interface is disabled. HPS debug logic cannot send trace data to the FPGA + * fabric. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF + * + * Trace interface is enabled. Other registers in the HPS debug logic must be + * programmmed to actually send trace data to the FPGA fabric. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_MSB 4 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : STM Event Interface - stmeventintf + * + * Used to disable the STM event interface. This interface allows logic in the FPGA + * fabric to trigger events to the STM debug module in the HPS. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS | 0x0 | STM event interface is disabled. Logic in the + * : | | FPGA fabric cannot trigger STM events. + * ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN | 0x1 | STM event interface is enabled. Logic in the + * : | | FPGA fabric can trigger STM events. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF + * + * STM event interface is disabled. Logic in the FPGA fabric cannot trigger STM + * events. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF + * + * STM event interface is enabled. Logic in the FPGA fabric can trigger STM + * events. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_MSB 6 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Cross Trigger Interface (CTI) - crosstrigintf + * + * Used to disable the FPGA Fabric from sending triggers to HPS debug logic. Note + * that this doesn't prevent the HPS debug logic from sending triggers to the FPGA + * Fabric. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:---------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS | 0x0 | FPGA Fabric cannot send triggers. + * ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN | 0x1 | FPGA Fabric can send triggers. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF + * + * FPGA Fabric cannot send triggers. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF + * + * FPGA Fabric can send triggers. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_MSB 7 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FPGAINTF_INDIV. + */ +struct ALT_SYSMGR_FPGAINTF_INDIV_s +{ + uint32_t rstreqintf : 1; /* Reset Request Interface */ + uint32_t jtagenintf : 1; /* JTAG Enable Interface */ + uint32_t configiointf : 1; /* CONFIG_IO Interface */ + uint32_t bscanintf : 1; /* Boundary-Scan Interface */ + uint32_t traceintf : 1; /* Trace Interface */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t stmeventintf : 1; /* STM Event Interface */ + uint32_t crosstrigintf : 1; /* Cross Trigger Interface (CTI) */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_INDIV. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_INDIV_s ALT_SYSMGR_FPGAINTF_INDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FPGAINTF_INDIV register from the beginning of the component. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_OFST 0x4 + +/* + * Register : Module Disable Register - module + * + * Used to disable signals from the FPGA fabric to individual HPS modules. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [1:0] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | EMAC Module + * [3] | RW | 0x0 | EMAC Module + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC Module - emac_0 + * + * Used to disable signals from the FPGA fabric to the EMAC modules that could + * potentially interfere with their normal operation. + * + * The array index corresponds to the EMAC module instance. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS | 0x0 | Signals from FPGA fabric cannot affect operation + * : | | of the EMAC module. + * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN | 0x1 | Signals from FPGA fabric can potentially affect + * : | | operation of the EMAC module. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 + * + * Signals from FPGA fabric cannot affect operation of the EMAC module. + */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 + * + * Signals from FPGA fabric can potentially affect operation of the EMAC module. + */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_MSB 2 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : EMAC Module - emac_1 + * + * Used to disable signals from the FPGA fabric to the EMAC modules that could + * potentially interfere with their normal operation. + * + * The array index corresponds to the EMAC module instance. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS | 0x0 | Signals from FPGA fabric cannot affect operation + * : | | of the EMAC module. + * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN | 0x1 | Signals from FPGA fabric can potentially affect + * : | | operation of the EMAC module. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 + * + * Signals from FPGA fabric cannot affect operation of the EMAC module. + */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 + * + * Signals from FPGA fabric can potentially affect operation of the EMAC module. + */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FPGAINTF_MODULE. + */ +struct ALT_SYSMGR_FPGAINTF_MODULE_s +{ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t emac_0 : 1; /* EMAC Module */ + uint32_t emac_1 : 1; /* EMAC Module */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_MODULE. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_MODULE_s ALT_SYSMGR_FPGAINTF_MODULE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FPGAINTF_MODULE register from the beginning of the component. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_OFST 0x8 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_FPGAINTF. + */ +struct ALT_SYSMGR_FPGAINTF_s +{ + volatile ALT_SYSMGR_FPGAINTF_GBL_t gbl; /* ALT_SYSMGR_FPGAINTF_GBL */ + volatile ALT_SYSMGR_FPGAINTF_INDIV_t indiv; /* ALT_SYSMGR_FPGAINTF_INDIV */ + volatile ALT_SYSMGR_FPGAINTF_MODULE_t module; /* ALT_SYSMGR_FPGAINTF_MODULE */ + volatile uint32_t _pad_0xc_0x10; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_FPGAINTF. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_s ALT_SYSMGR_FPGAINTF_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_FPGAINTF. */ +struct ALT_SYSMGR_FPGAINTF_raw_s +{ + volatile uint32_t gbl; /* ALT_SYSMGR_FPGAINTF_GBL */ + volatile uint32_t indiv; /* ALT_SYSMGR_FPGAINTF_INDIV */ + volatile uint32_t module; /* ALT_SYSMGR_FPGAINTF_MODULE */ + volatile uint32_t _pad_0xc_0x10; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_FPGAINTF. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_raw_s ALT_SYSMGR_FPGAINTF_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Scan Manager Group - ALT_SYSMGR_SCANMGR + * Scan Manager Group + * + * Registers related to the Scan Manager that aren't located inside the Scan + * Manager itself. + * + */ +/* + * Register : Scan Manager Control Register - ctrl + * + * Controls behaviors of Scan Manager not controlled by registers in the Scan + * Manager itself. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x0 | FPGA JTAG Enable + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FPGA JTAG Enable - fpgajtagen + * + * Controls whether FPGA JTAG pins or Scan Manager drives JTAG signals to the FPGA. + * + * Only reset by a cold reset (ignores warm reset). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------ + * ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS | 0x0 | FPGA JTAG pins drive JTAG signals to FPGA + * ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR | 0x1 | Scan Manager drives JTAG signals to FPGA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN + * + * FPGA JTAG pins drive JTAG signals to FPGA + */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN + * + * Scan Manager drives JTAG signals to FPGA + */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_MSB 0 +/* The width in bits of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_RESET 0x0 +/* Extracts the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN field value from a register. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value suitable for setting the register. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SCANMGR_CTL. + */ +struct ALT_SYSMGR_SCANMGR_CTL_s +{ + uint32_t fpgajtagen : 1; /* FPGA JTAG Enable */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SCANMGR_CTL. */ +typedef volatile struct ALT_SYSMGR_SCANMGR_CTL_s ALT_SYSMGR_SCANMGR_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SCANMGR_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_SCANMGR_CTL_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_SCANMGR. + */ +struct ALT_SYSMGR_SCANMGR_s +{ + volatile ALT_SYSMGR_SCANMGR_CTL_t ctrl; /* ALT_SYSMGR_SCANMGR_CTL */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_SCANMGR. */ +typedef volatile struct ALT_SYSMGR_SCANMGR_s ALT_SYSMGR_SCANMGR_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_SCANMGR. */ +struct ALT_SYSMGR_SCANMGR_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_SCANMGR_CTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_SCANMGR. */ +typedef volatile struct ALT_SYSMGR_SCANMGR_raw_s ALT_SYSMGR_SCANMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Freeze Control Group - ALT_SYSMGR_FRZCTL + * Freeze Control Group + * + * Registers used to generate HPS IO freeze signals. + * + * All registers are only reset by a cold reset (ignore warm reset). + * + */ +/* + * Register : VIO Control Register - vioctrl + * + * Used to drive freeze signals to HPS VIO banks. + * + * The register array index corresponds to the freeze channel. + * + * Freeze channel 0 provides freeze signals to VIO bank 0 and 1. + * + * Freeze channel 1 provides freeze signals to VIO bank 2 and 3. Only drives freeze + * signals when SRC.VIO1 is set to SW. + * + * Freeze channel 2 provides freeze signals to VIO bank 4. + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * The following equation determines when the weak pullup resistor is enabled: + * + * enabled = ~wkpullup | (CFF & cfg & tristate) + * + * where CFF is the value of weak pullup as set by IO configuration + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x0 | IO Configuration + * [1] | RW | 0x0 | IO Bus Hold + * [2] | RW | 0x0 | IO Tri-State + * [3] | RW | 0x0 | IO Weak Pullup + * [4] | RW | 0x0 | IO Slew-rate + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IO Configuration - cfg + * + * Controls IO configuration + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS | 0x0 | Disable IO configuration (forced to a safe + * : | | value). + * ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG | 0x1 | Enables IO configuration as previously + * : | | configured by software using the Scan Manager. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG + * + * Disable IO configuration (forced to a safe value). + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG + * + * Enables IO configuration as previously configured by software using the Scan + * Manager. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_MSB 0 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_CFG field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IO Bus Hold - bushold + * + * Controls bus hold circuit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS | 0x0 | Disable bus hold circuit. + * ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG | 0x1 | Bus hold circuit controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD + * + * Disable bus hold circuit. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD + * + * Bus hold circuit controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_MSB 1 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IO Tri-State - tristate + * + * Controls IO tri-state + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN | 0x0 | IO tri-state enabled. + * ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG | 0x1 | IO tri-state controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE + * + * IO tri-state enabled. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE + * + * IO tri-state controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_MSB 2 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IO Weak Pullup - wkpullup + * + * Controls weak pullup resistor + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN | 0x0 | Weak pullup resistor enabled. + * ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG | 0x1 | Weak pullup resistor enable controlled by IO + * : | | configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP + * + * Weak pullup resistor enabled. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP + * + * Weak pullup resistor enable controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_MSB 3 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IO Slew-rate - slew + * + * Controls IO slew-rate + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------ + * ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW | 0x0 | Slew-rate forced to slow. + * ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG | 0x1 | Slew-rate controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW + * + * Slew-rate forced to slow. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW + * + * Slew-rate controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_MSB 4 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FRZCTL_VIOCTL. + */ +struct ALT_SYSMGR_FRZCTL_VIOCTL_s +{ + uint32_t cfg : 1; /* IO Configuration */ + uint32_t bushold : 1; /* IO Bus Hold */ + uint32_t tristate : 1; /* IO Tri-State */ + uint32_t wkpullup : 1; /* IO Weak Pullup */ + uint32_t slew : 1; /* IO Slew-rate */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FRZCTL_VIOCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_VIOCTL_s ALT_SYSMGR_FRZCTL_VIOCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FRZCTL_VIOCTL register from the beginning of the component. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_OFST 0x0 + +/* + * Register : HIO Control Register - hioctrl + * + * Used to drive freeze signals to HPS HIO bank (DDR SDRAM). + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * The following equation determines when the weak pullup resistor is enabled: + * + * enabled = ~wkpullup | (CFF & cfg & tristate) + * + * where CFF is the value of weak pullup as set by IO configuration + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [0] | RW | 0x0 | IO Configuration + * [1] | RW | 0x0 | IO Bus Hold + * [2] | RW | 0x0 | IO Tri-State + * [3] | RW | 0x0 | IO Weak Pullup + * [4] | RW | 0x0 | IO Slew-rate + * [5] | RW | 0x1 | DLL Reset + * [6] | RW | 0x1 | OCT Reset + * [7] | RW | 0x1 | IO and DQS Reset + * [8] | RW | 0x0 | OCT Calibration and Configuration Enable + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IO Configuration - cfg + * + * Controls IO configuration + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS | 0x0 | Disable IO configuration (forced to a safe + * : | | value). + * ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG | 0x1 | Enables IO configuration as previously + * : | | configured by software using the Scan Manager. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG + * + * Disable IO configuration (forced to a safe value). + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG + * + * Enables IO configuration as previously configured by software using the Scan + * Manager. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_MSB 0 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_CFG field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IO Bus Hold - bushold + * + * Controls bus hold circuit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS | 0x0 | Disable bus hold circuit. + * ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG | 0x1 | Bus hold circuit controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD + * + * Disable bus hold circuit. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD + * + * Bus hold circuit controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_MSB 1 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IO Tri-State - tristate + * + * Controls IO tri-state + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN | 0x0 | IO tri-state enabled. + * ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG | 0x1 | IO tri-state controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE + * + * IO tri-state enabled. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE + * + * IO tri-state controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_MSB 2 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IO Weak Pullup - wkpullup + * + * Controls weak pullup resistor + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN | 0x0 | Weak pullup resistor enabled. + * ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG | 0x1 | Weak pullup resistor enable controlled by IO + * : | | configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP + * + * Weak pullup resistor enabled. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP + * + * Weak pullup resistor enable controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_MSB 3 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IO Slew-rate - slew + * + * Controls IO slew-rate + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------ + * ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW | 0x0 | Slew-rate forced to slow. + * ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG | 0x1 | Slew-rate controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW + * + * Slew-rate forced to slow. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW + * + * Slew-rate controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_MSB 4 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : DLL Reset - dllrst + * + * Controls DLL (Delay-Locked Loop) reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS | 0x0 | No reset or clock gating. + * ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN | 0x1 | Resets registers in the DLL and gates off DLL + * : | | clock. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST + * + * No reset or clock gating. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST + * + * Resets registers in the DLL and gates off DLL clock. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_MSB 5 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_RESET 0x1 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : OCT Reset - octrst + * + * Controls OCT reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS | 0x0 | No reset. + * ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN | 0x1 | Resets registers in the OCT. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST + * + * No reset. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST + * + * Resets registers in the OCT. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_MSB 6 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_RESET 0x1 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : IO and DQS Reset - regrst + * + * Controls IO and DQS reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS | 0x0 | No reset. + * ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN | 0x1 | Resets all IO registers and DQS registers. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST + * + * No reset. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST + * + * Resets all IO registers and DQS registers. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_MSB 7 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_RESET 0x1 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : OCT Calibration and Configuration Enable - oct_cfgen_calstart + * + * Controls OCT calibration and OCT IO configuration enable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS | 0x0 | Disables IO configuration (forced to a safe + * : | | value) in OCT calibration block. + * ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN | 0x1 | Starts OCT calibration state machine and enables + * : | | IO configuration in OCT calibration block. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART + * + * Disables IO configuration (forced to a safe value) in OCT calibration block. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART + * + * Starts OCT calibration state machine and enables IO configuration in OCT + * calibration block. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_MSB 8 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FRZCTL_HIOCTL. + */ +struct ALT_SYSMGR_FRZCTL_HIOCTL_s +{ + uint32_t cfg : 1; /* IO Configuration */ + uint32_t bushold : 1; /* IO Bus Hold */ + uint32_t tristate : 1; /* IO Tri-State */ + uint32_t wkpullup : 1; /* IO Weak Pullup */ + uint32_t slew : 1; /* IO Slew-rate */ + uint32_t dllrst : 1; /* DLL Reset */ + uint32_t octrst : 1; /* OCT Reset */ + uint32_t regrst : 1; /* IO and DQS Reset */ + uint32_t oct_cfgen_calstart : 1; /* OCT Calibration and Configuration Enable */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FRZCTL_HIOCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_HIOCTL_s ALT_SYSMGR_FRZCTL_HIOCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FRZCTL_HIOCTL register from the beginning of the component. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OFST 0x10 + +/* + * Register : Source Register - src + * + * Contains register field to choose between software state machine (vioctrl array + * index [1] register) or hardware state machine in the Freeze Controller as the + * freeze signal source for VIO channel 1. + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [0] | RW | 0x0 | VIO1 Freeze Signal Source + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : VIO1 Freeze Signal Source - vio1 + * + * The freeze signal source for VIO channel 1 (VIO bank 2 and bank 3). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW | 0x0 | VIO1 freeze signals are driven by software + * : | | writing to the VIOCTRL[1] register. The + * : | | VIO1-related fields in the hwctrl register are + * : | | active but don't effect the VIO1 freeze signals. + * ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW | 0x1 | VIO1 freeze signals are driven by the hardware + * : | | state machine in the Freeze Controller. The + * : | | VIO1-related fields in the hwctrl register are + * : | | active and effect the VIO1 freeze signals. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1 + * + * VIO1 freeze signals are driven by software writing to the VIOCTRL[1] register. + * The VIO1-related fields in the hwctrl register are active but don't effect the + * VIO1 freeze signals. + */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1 + * + * VIO1 freeze signals are driven by the hardware state machine in the Freeze + * Controller. The VIO1-related fields in the hwctrl register are active and effect + * the VIO1 freeze signals. + */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_MSB 0 +/* The width in bits of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_SRC_VIO1 field value from a register. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FRZCTL_SRC. + */ +struct ALT_SYSMGR_FRZCTL_SRC_s +{ + uint32_t vio1 : 1; /* VIO1 Freeze Signal Source */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FRZCTL_SRC. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_SRC_s ALT_SYSMGR_FRZCTL_SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FRZCTL_SRC register from the beginning of the component. */ +#define ALT_SYSMGR_FRZCTL_SRC_OFST 0x14 + +/* + * Register : Hardware Control Register - hwctrl + * + * Activate freeze or thaw operations on VIO channel 1 (HPS IO bank 2 and bank 3) + * and monitor for completeness and the current state. + * + * These fields interact with the hardware state machine in the Freeze Controller. + * These fields can be accessed independent of the value of SRC1.VIO1 although they + * only have an effect on the VIO channel 1 freeze signals when SRC1.VIO1 is setup + * to have the hardware state machine be the freeze signal source. + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [0] | RW | 0x1 | VIO channel 1 Freeze/Thaw request + * [2:1] | R | 0x2 | VIO channel 1 State + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : VIO channel 1 Freeze/Thaw request - vio1req + * + * Requests hardware state machine to generate freeze signal sequence to transition + * between frozen and thawed states. + * + * If this field is read by software, it contains the value previously written by + * software (i.e. this field is not written by hardware). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------------- + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW | 0x0 | Requests a thaw (unfreeze) operation. + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ | 0x1 | Requests a freeze operation. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ + * + * Requests a thaw (unfreeze) operation. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ + * + * Requests a freeze operation. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_MSB 0 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_RESET 0x1 +/* Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : VIO channel 1 State - vio1state + * + * Software reads this field to determine the current frozen/thawed state of the + * VIO channel 1 or to determine when a freeze/thaw request is made by writing the + * corresponding *REQ field in this register has completed. + * + * Reset by a cold reset (ignores warm reset). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN | 0x0 | Transitioning from thawed state to frozen state. + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED | 0x1 | Thawed state. I/Os behave as configured. I/Os + * : | | must be configured by the Scan Manager before + * : | | entering this state. + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN | 0x2 | Frozen state. I/O configuration is ignored. + * : | | Instead, I/Os are in tri-state mode with a weak + * : | | pull-up. Scan Manager can be used to configure + * : | | the I/Os while they are frozen. + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED | 0x3 | Transitioning from frozen state to thawed state. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE + * + * Transitioning from thawed state to frozen state. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE + * + * Thawed state. I/Os behave as configured. I/Os must be configured by the Scan + * Manager before entering this state. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE + * + * Frozen state. I/O configuration is ignored. Instead, I/Os are in tri-state mode + * with a weak pull-up. Scan Manager can be used to configure the I/Os while they + * are frozen. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE + * + * Transitioning from frozen state to thawed state. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_MSB 2 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET_MSK 0x00000006 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_RESET 0x2 +/* Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET(value) (((value) << 1) & 0x00000006) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FRZCTL_HWCTL. + */ +struct ALT_SYSMGR_FRZCTL_HWCTL_s +{ + uint32_t vio1req : 1; /* VIO channel 1 Freeze/Thaw request */ + const uint32_t vio1state : 2; /* VIO channel 1 State */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FRZCTL_HWCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_HWCTL_s ALT_SYSMGR_FRZCTL_HWCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FRZCTL_HWCTL register from the beginning of the component. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_OFST 0x18 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_FRZCTL. + */ +struct ALT_SYSMGR_FRZCTL_s +{ + volatile ALT_SYSMGR_FRZCTL_VIOCTL_t vioctrl[3]; /* ALT_SYSMGR_FRZCTL_VIOCTL */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_SYSMGR_FRZCTL_HIOCTL_t hioctrl; /* ALT_SYSMGR_FRZCTL_HIOCTL */ + volatile ALT_SYSMGR_FRZCTL_SRC_t src; /* ALT_SYSMGR_FRZCTL_SRC */ + volatile ALT_SYSMGR_FRZCTL_HWCTL_t hwctrl; /* ALT_SYSMGR_FRZCTL_HWCTL */ + volatile uint32_t _pad_0x1c_0x20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_FRZCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_s ALT_SYSMGR_FRZCTL_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_FRZCTL. */ +struct ALT_SYSMGR_FRZCTL_raw_s +{ + volatile uint32_t vioctrl[3]; /* ALT_SYSMGR_FRZCTL_VIOCTL */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t hioctrl; /* ALT_SYSMGR_FRZCTL_HIOCTL */ + volatile uint32_t src; /* ALT_SYSMGR_FRZCTL_SRC */ + volatile uint32_t hwctrl; /* ALT_SYSMGR_FRZCTL_HWCTL */ + volatile uint32_t _pad_0x1c_0x20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_FRZCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_raw_s ALT_SYSMGR_FRZCTL_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : EMAC Group - ALT_SYSMGR_EMAC + * EMAC Group + * + * External control registers for the EMACs + * + */ +/* + * Register : Control Register - ctrl + * + * Registers used by the EMACs. All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [1:0] | RW | 0x2 | PHY Interface Select + * [3:2] | RW | 0x2 | PHY Interface Select + * [4] | RW | 0x0 | PTP Clock Select + * [5] | RW | 0x0 | PTP Clock Select + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : PHY Interface Select - physel_0 + * + * Controls the PHY interface selection of the EMACs. This is sampled by an EMAC + * module when it exits from reset. The associated enum defines the allowed values. + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------ + * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII | 0x0 | Select GMII/MII PHY interface + * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII | 0x1 | Select RGMII PHY interface + * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII | 0x2 | Select RMII PHY interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0 + * + * Select GMII/MII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0 + * + * Select RGMII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0 + * + * Select RMII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_MSB 1 +/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_RESET 0x2 +/* Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 field value from a register. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : PHY Interface Select - physel_1 + * + * Controls the PHY interface selection of the EMACs. This is sampled by an EMAC + * module when it exits from reset. The associated enum defines the allowed values. + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------ + * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII | 0x0 | Select GMII/MII PHY interface + * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII | 0x1 | Select RGMII PHY interface + * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII | 0x2 | Select RMII PHY interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1 + * + * Select GMII/MII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1 + * + * Select RGMII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1 + * + * Select RMII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET_MSK 0x0000000c +/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_RESET 0x2 +/* Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 field value from a register. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : PTP Clock Select - ptpclksel_0 + * + * Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC + * module when it exits from reset. The field array index corresponds to the EMAC + * index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------------------- + * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK | 0x0 | Selects osc1_clk + * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK | 0x1 | Selects fpga_ptp_ref_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 + * + * Selects osc1_clk + */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 + * + * Selects fpga_ptp_ref_clk + */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_MSB 4 +/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 field value from a register. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : PTP Clock Select - ptpclksel_1 + * + * Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC + * module when it exits from reset. The field array index corresponds to the EMAC + * index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------------------- + * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK | 0x0 | Selects osc1_clk + * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK | 0x1 | Selects fpga_ptp_ref_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 + * + * Selects osc1_clk + */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 + * + * Selects fpga_ptp_ref_clk + */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_MSB 5 +/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 field value from a register. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET(value) (((value) << 5) & 0x00000020) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_EMAC_CTL. + */ +struct ALT_SYSMGR_EMAC_CTL_s +{ + uint32_t physel_0 : 2; /* PHY Interface Select */ + uint32_t physel_1 : 2; /* PHY Interface Select */ + uint32_t ptpclksel_0 : 1; /* PTP Clock Select */ + uint32_t ptpclksel_1 : 1; /* PTP Clock Select */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_EMAC_CTL. */ +typedef volatile struct ALT_SYSMGR_EMAC_CTL_s ALT_SYSMGR_EMAC_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_EMAC_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_EMAC_CTL_OFST 0x0 + +/* + * Register : EMAC L3 Master AxCACHE Register - l3master + * + * Controls the L3 master ARCACHE and AWCACHE AXI signals. + * + * These register bits should be updated only during system initialization prior to + * removing the peripheral from reset. They may not be changed dynamically during + * peripheral operation + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------- + * [3:0] | RW | 0x0 | EMAC ARCACHE + * [7:4] | RW | 0x0 | EMAC ARCACHE + * [11:8] | RW | 0x0 | EMAC AWCACHE + * [15:12] | RW | 0x0 | EMAC AWCACHE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC ARCACHE - arcache_0 + * + * Specifies the values of the 2 EMAC ARCACHE signals. + * + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Bufferable only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_MSB 3 +/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 field value from a register. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : EMAC ARCACHE - arcache_1 + * + * Specifies the values of the 2 EMAC ARCACHE signals. + * + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Bufferable only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_MSB 7 +/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_CLR_MSK 0xffffff0f +/* The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 field value from a register. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET(value) (((value) << 4) & 0x000000f0) + +/* + * Field : EMAC AWCACHE - awcache_0 + * + * Specifies the values of the 2 EMAC AWCACHE signals. + * + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Bufferable only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_MSB 11 +/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET_MSK 0x00000f00 +/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_CLR_MSK 0xfffff0ff +/* The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 field value from a register. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_GET(value) (((value) & 0x00000f00) >> 8) +/* Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET(value) (((value) << 8) & 0x00000f00) + +/* + * Field : EMAC AWCACHE - awcache_1 + * + * Specifies the values of the 2 EMAC AWCACHE signals. + * + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Bufferable only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_MSB 15 +/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET_MSK 0x0000f000 +/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_CLR_MSK 0xffff0fff +/* The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 field value from a register. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_GET(value) (((value) & 0x0000f000) >> 12) +/* Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET(value) (((value) << 12) & 0x0000f000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_EMAC_L3MST. + */ +struct ALT_SYSMGR_EMAC_L3MST_s +{ + uint32_t arcache_0 : 4; /* EMAC ARCACHE */ + uint32_t arcache_1 : 4; /* EMAC ARCACHE */ + uint32_t awcache_0 : 4; /* EMAC AWCACHE */ + uint32_t awcache_1 : 4; /* EMAC AWCACHE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_EMAC_L3MST. */ +typedef volatile struct ALT_SYSMGR_EMAC_L3MST_s ALT_SYSMGR_EMAC_L3MST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_EMAC_L3MST register from the beginning of the component. */ +#define ALT_SYSMGR_EMAC_L3MST_OFST 0x4 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_EMAC. + */ +struct ALT_SYSMGR_EMAC_s +{ + volatile ALT_SYSMGR_EMAC_CTL_t ctrl; /* ALT_SYSMGR_EMAC_CTL */ + volatile ALT_SYSMGR_EMAC_L3MST_t l3master; /* ALT_SYSMGR_EMAC_L3MST */ + volatile uint32_t _pad_0x8_0x10[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_EMAC. */ +typedef volatile struct ALT_SYSMGR_EMAC_s ALT_SYSMGR_EMAC_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_EMAC. */ +struct ALT_SYSMGR_EMAC_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_EMAC_CTL */ + volatile uint32_t l3master; /* ALT_SYSMGR_EMAC_L3MST */ + volatile uint32_t _pad_0x8_0x10[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_EMAC. */ +typedef volatile struct ALT_SYSMGR_EMAC_raw_s ALT_SYSMGR_EMAC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : DMA Controller Group - ALT_SYSMGR_DMA + * DMA Controller Group + * + * Registers used by the DMA Controller to enable secured system support and select + * DMA channels. + * + */ +/* + * Register : Control Register - ctrl + * + * Registers used by the DMA Controller. All fields are reset by a cold or warm + * reset. + * + * These register bits should be updated during system initialization prior to + * removing the DMA controller from reset. They may not be changed dynamically + * during DMA operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | Channel Select + * [1] | RW | 0x0 | Channel Select + * [2] | RW | 0x0 | Channel Select + * [3] | RW | 0x0 | Channel Select + * [4] | RW | 0x0 | Manager Thread Security + * [12:5] | RW | 0x0 | IRQ Security + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Channel Select - chansel_0 + * + * Controls mux that selects whether FPGA or CAN connects to one of the DMA + * peripheral request interfaces.The peripheral request interface index equals the + * array index + 4. For example, array index 0 is for peripheral request index 4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------- + * ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA | 0x0 | FPGA drives peripheral request interface + * ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN | 0x1 | CAN drives peripheral request interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0 + * + * FPGA drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0 + * + * CAN drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_MSB 0 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_0 field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Select - chansel_1 + * + * Controls mux that selects whether FPGA or CAN connects to one of the DMA + * peripheral request interfaces.The peripheral request interface index equals the + * array index + 4. For example, array index 0 is for peripheral request index 4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------- + * ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA | 0x0 | FPGA drives peripheral request interface + * ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN | 0x1 | CAN drives peripheral request interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1 + * + * FPGA drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1 + * + * CAN drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_MSB 1 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_1 field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Channel Select - chansel_2 + * + * Controls mux that selects whether FPGA or CAN connects to one of the DMA + * peripheral request interfaces.The peripheral request interface index equals the + * array index + 4. For example, array index 0 is for peripheral request index 4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------- + * ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA | 0x0 | FPGA drives peripheral request interface + * ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN | 0x1 | CAN drives peripheral request interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2 + * + * FPGA drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2 + * + * CAN drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_MSB 2 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_2 field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Channel Select - chansel_3 + * + * Controls mux that selects whether FPGA or CAN connects to one of the DMA + * peripheral request interfaces.The peripheral request interface index equals the + * array index + 4. For example, array index 0 is for peripheral request index 4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------- + * ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA | 0x0 | FPGA drives peripheral request interface + * ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN | 0x1 | CAN drives peripheral request interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3 + * + * FPGA drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3 + * + * CAN drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_MSB 3 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_3 field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Manager Thread Security - mgrnonsecure + * + * Specifies the security state of the DMA manager thread. + * + * 0 = assigns DMA manager to the Secure state. + * + * 1 = assigns DMA manager to the Non-secure state. + * + * Sampled by the DMA controller when it exits from reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_MSB 4 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_MGRNONSECURE field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IRQ Security - irqnonsecure + * + * Specifies the security state of an event-interrupt resource. + * + * If bit index [x] is 0, the DMAC assigns event or irq[x] to the Secure state. + * + * If bit index [x] is 1, the DMAC assigns event or irq[x] to the Non-secure + * state. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_MSB 12 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH 8 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET_MSK 0x00001fe0 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_CLR_MSK 0xffffe01f +/* The reset value of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_IRQNONSECURE field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_GET(value) (((value) & 0x00001fe0) >> 5) +/* Produces a ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET(value) (((value) << 5) & 0x00001fe0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_DMA_CTL. + */ +struct ALT_SYSMGR_DMA_CTL_s +{ + uint32_t chansel_0 : 1; /* Channel Select */ + uint32_t chansel_1 : 1; /* Channel Select */ + uint32_t chansel_2 : 1; /* Channel Select */ + uint32_t chansel_3 : 1; /* Channel Select */ + uint32_t mgrnonsecure : 1; /* Manager Thread Security */ + uint32_t irqnonsecure : 8; /* IRQ Security */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_DMA_CTL. */ +typedef volatile struct ALT_SYSMGR_DMA_CTL_s ALT_SYSMGR_DMA_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_DMA_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_DMA_CTL_OFST 0x0 + +/* + * Register : Peripheral Security Register - persecurity + * + * Controls the security state of a peripheral request interface. Sampled by the + * DMA controller when it exits from reset. + * + * These register bits should be updated during system initialization prior to + * removing the DMA controller from reset. They may not be changed dynamically + * during DMA operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [31:0] | RW | 0x0 | Peripheral Non-Secure + * + */ +/* + * Field : Peripheral Non-Secure - nonsecure + * + * If bit index [x] is 0, the DMA controller assigns peripheral request interface x + * to the Secure state. + * + * If bit index [x] is 1, the DMA controller assigns peripheral request interface x + * to the Non-secure state. + * + * Reset by a cold or warm reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_MSB 31 +/* The width in bits of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE field value from a register. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_DMA_PERSECURITY. + */ +struct ALT_SYSMGR_DMA_PERSECURITY_s +{ + uint32_t nonsecure : 32; /* Peripheral Non-Secure */ +}; + +/* The typedef declaration for register ALT_SYSMGR_DMA_PERSECURITY. */ +typedef volatile struct ALT_SYSMGR_DMA_PERSECURITY_s ALT_SYSMGR_DMA_PERSECURITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_DMA_PERSECURITY register from the beginning of the component. */ +#define ALT_SYSMGR_DMA_PERSECURITY_OFST 0x4 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_DMA. + */ +struct ALT_SYSMGR_DMA_s +{ + volatile ALT_SYSMGR_DMA_CTL_t ctrl; /* ALT_SYSMGR_DMA_CTL */ + volatile ALT_SYSMGR_DMA_PERSECURITY_t persecurity; /* ALT_SYSMGR_DMA_PERSECURITY */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_DMA. */ +typedef volatile struct ALT_SYSMGR_DMA_s ALT_SYSMGR_DMA_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_DMA. */ +struct ALT_SYSMGR_DMA_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_DMA_CTL */ + volatile uint32_t persecurity; /* ALT_SYSMGR_DMA_PERSECURITY */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_DMA. */ +typedef volatile struct ALT_SYSMGR_DMA_raw_s ALT_SYSMGR_DMA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Preloader (initial software) Group - ALT_SYSMGR_ISW + * Preloader (initial software) Group + * + * Registers used by preloader code and the OS. + * + * All registers are only reset by a cold reset (ignore warm reset). + * + */ +/* + * Register : Preloader to OS Handoff Information - handoff + * + * These registers are used to store handoff infomation between the preloader and + * the OS. These 8 registers can be used to store any information. The contents of + * these registers have no impact on the state of the HPS hardware. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | Preloader Handoff Information + * + */ +/* + * Field : Preloader Handoff Information - value + * + * Preloader Handoff Information. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_MSB 31 +/* The width in bits of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ISW_HANDOFF_VALUE register field value. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ISW_HANDOFF_VALUE register field value. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ISW_HANDOFF_VALUE field value from a register. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ISW_HANDOFF_VALUE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ISW_HANDOFF. + */ +struct ALT_SYSMGR_ISW_HANDOFF_s +{ + uint32_t value : 32; /* Preloader Handoff Information */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ISW_HANDOFF. */ +typedef volatile struct ALT_SYSMGR_ISW_HANDOFF_s ALT_SYSMGR_ISW_HANDOFF_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ISW_HANDOFF register from the beginning of the component. */ +#define ALT_SYSMGR_ISW_HANDOFF_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ISW. + */ +struct ALT_SYSMGR_ISW_s +{ + volatile ALT_SYSMGR_ISW_HANDOFF_t handoff[8]; /* ALT_SYSMGR_ISW_HANDOFF */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ISW. */ +typedef volatile struct ALT_SYSMGR_ISW_s ALT_SYSMGR_ISW_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ISW. */ +struct ALT_SYSMGR_ISW_raw_s +{ + volatile uint32_t handoff[8]; /* ALT_SYSMGR_ISW_HANDOFF */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ISW. */ +typedef volatile struct ALT_SYSMGR_ISW_raw_s ALT_SYSMGR_ISW_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Boot ROM Code Register Group - ALT_SYSMGR_ROMCODE + * Boot ROM Code Register Group + * + * Registers used by the Boot ROM code. All fields are only reset by a cold reset + * (ignore warm reset). + * + */ +/* + * Register : Control Register - ctrl + * + * Contains information used to control Boot ROM code. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------- + * [0] | RW | 0x0 | Warm Reset Configure Pin Mux for Boot Pins + * [1] | RW | 0x0 | Warm Reset Configure IOs for Boot Pins + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Warm Reset Configure Pin Mux for Boot Pins - warmrstcfgpinmux + * + * Specifies whether the Boot ROM code configures the pin mux for boot pins after a + * warm reset. Note that the Boot ROM code always configures the pin mux for boot + * pins after a cold reset. After the Boot ROM code configures the pin mux for boot + * pins, it always disables this field. It is up to user software to enable this + * field if it wants a different behavior. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:---------------------------------------------- + * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD | 0x0 | Boot ROM code will not configure pin mux for + * : | | boot pins after a warm reset + * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END | 0x1 | Boot ROM code will configure pin mux for boot + * : | | pins after a warm reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX + * + * Boot ROM code will not configure pin mux for boot pins after a warm reset + */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX + * + * Boot ROM code will configure pin mux for boot pins after a warm reset + */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0 +/* The width in bits of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX field value from a register. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Warm Reset Configure IOs for Boot Pins - warmrstcfgio + * + * Specifies whether the Boot ROM code configures the IOs used by boot after a warm + * reset. Note that the Boot ROM code always configures the IOs used by boot after + * a cold reset. After the Boot ROM code configures the IOs used by boot, it always + * disables this field. It is up to user software to enable this field if it wants + * a different behavior. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------------------------------------- + * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD | 0x0 | Boot ROM code will not configure IOs used by + * : | | boot after a warm reset + * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END | 0x1 | Boot ROM code will configure IOs used by boot + * : | | after a warm reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO + * + * Boot ROM code will not configure IOs used by boot after a warm reset + */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO + * + * Boot ROM code will configure IOs used by boot after a warm reset + */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_MSB 1 +/* The width in bits of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO field value from a register. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_CTL. + */ +struct ALT_SYSMGR_ROMCODE_CTL_s +{ + uint32_t warmrstcfgpinmux : 1; /* Warm Reset Configure Pin Mux for Boot Pins */ + uint32_t warmrstcfgio : 1; /* Warm Reset Configure IOs for Boot Pins */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_CTL. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_CTL_s ALT_SYSMGR_ROMCODE_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_CTL_OFST 0x0 + +/* + * Register : CPU1 Start Address Register - cpu1startaddr + * + * When CPU1 is released from reset and the Boot ROM is located at the CPU1 reset + * exception address (the typical case), the Boot ROM reset handler code reads the + * address stored in this register and jumps it to hand off execution to user + * software. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | Address + * + */ +/* + * Field : Address - value + * + * Address for CPU1 to start executing at after coming out of reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE field value from a register. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR. + */ +struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s +{ + uint32_t value : 32; /* Address */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST 0x4 + +/* + * Register : Preloader (initial software) State Register - initswstate + * + * The preloader software (loaded by the Boot ROM) writes the magic value + * 0x49535756 (ISWV in ASCII) to this register when it has reached a valid state. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | Value + * + */ +/* + * Field : Value - value + * + * Written with magic value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:-----------|:------------ + * ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID | 0x0 | + * ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID | 0x49535756 | + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE + * + */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE + * + */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID 0x49535756 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE field value from a register. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_INITSWSTATE. + */ +struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s +{ + uint32_t value : 32; /* Value */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_INITSWSTATE. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s ALT_SYSMGR_ROMCODE_INITSWSTATE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_INITSWSTATE register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_OFST 0x8 + +/* + * Register : Preloader (initial software) Last Image Loaded Register - initswlastld + * + * Contains the index of the last preloader software image loaded by the Boot ROM + * from the boot device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [1:0] | RW | 0x0 | Index + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Index - index + * + * Index of last image loaded. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_MSB 1 +/* The width in bits of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX field value from a register. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_INITSWLASTLD. + */ +struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s +{ + uint32_t index : 2; /* Index */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_INITSWLASTLD. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s ALT_SYSMGR_ROMCODE_INITSWLASTLD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_INITSWLASTLD register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_OFST 0xc + +/* + * Register : Boot ROM Software State Register - bootromswstate + * + * 32-bits general purpose register used by the Boot ROM code. Actual usage is + * defined in the Boot ROM source code. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Boot ROM Software State + * + */ +/* + * Field : Boot ROM Software State - value + * + * Reserved for Boot ROM use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE field value from a register. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE. + */ +struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s +{ + uint32_t value : 32; /* Boot ROM Software State */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_OFST 0x10 + +/* + * Register Group : Warm Boot from On-Chip RAM Group - ALT_SYSMGR_ROMCODE_WARMRAM + * Warm Boot from On-Chip RAM Group + * + * Registers used by the Boot ROM code to support booting from the On-chip RAM on a + * warm reset. All these registers must be written by user software before a warm + * reset occurs to make use of this feature. + * + */ +/* + * Register : Enable Register - enable + * + * Enables or disables the warm reset from On-chip RAM feature. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [31:0] | RW | 0x0 | Warm Reset from On-chip RAM + * + */ +/* + * Field : Warm Reset from On-chip RAM - magic + * + * Controls whether Boot ROM will attempt to boot from the contents of the On-chip + * RAM on a warm reset. When this feature is enabled, the Boot ROM code will not + * configure boot IOs, the pin mux, or clocks. + * + * Note that the enable value is a 32-bit magic value (provided by the enum). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:-----------|:------------------------------------------------ + * ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD | 0x0 | Boot ROM code will not attempt to boot from On- + * : | | chip RAM on a warm reset + * ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END | 0xae9efebc | Boot ROM code will attempt to boot from On-chip + * : | | RAM on a warm reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC + * + * Boot ROM code will not attempt to boot from On-chip RAM on a warm reset + */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC + * + * Boot ROM code will attempt to boot from On-chip RAM on a warm reset + */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END 0xae9efebc + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EN. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s +{ + uint32_t magic : 32; /* Warm Reset from On-chip RAM */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EN. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s ALT_SYSMGR_ROMCODE_WARMRAM_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST 0x0 +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST)) + +/* + * Register : Data Start Register - datastart + * + * Offset into On-chip RAM of the start of the region for CRC validation + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------ + * [15:0] | RW | 0x0 | Data Start Offset + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Start Offset - offset + * + * Contains the byte offset into the On-chip RAM of the start of the On-chip RAM + * region for the warm boot CRC validation. The offset must be an integer multiple + * of 4 (i.e. aligned to a word). The Boot ROM code will set the top 16 bits to + * 0xFFFF and clear the bottom 2 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_MSB 15 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s +{ + uint32_t offset : 16; /* Data Start Offset */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST 0x4 +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST)) + +/* + * Register : Length Register - length + * + * Length of region in On-chip RAM for CRC validation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [15:0] | RW | 0x0 | Size + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Size - size + * + * Contains the length (in bytes) of the region in the On-chip RAM for the warm + * boot CRC validation. + * + * If the length is 0, the Boot ROM won't perform CRC calculation and CRC check to + * avoid overhead caused by CRC validation. + * + * If the START + LENGTH exceeds the maximum offset into the On-chip RAM, the Boot + * ROM won't boot from the On-chip RAM. + * + * The length must be an integer multiple of 4. + * + * The Boot ROM code will clear the top 16 bits and the bottom 2 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_MSB 15 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_LEN. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s +{ + uint32_t size : 16; /* Size */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_LEN. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST 0x8 +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST)) + +/* + * Register : Execution Register - execution + * + * Offset into On-chip RAM to enter to on a warm boot. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------- + * [15:0] | RW | 0x0 | Execution Offset + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Execution Offset - offset + * + * Contains the byte offset into the On-chip RAM that the Boot ROM will jump to if + * the CRC validation succeeds. + * + * The Boot ROM code will set the top 16 bits to 0xFFFF. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_MSB 15 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s +{ + uint32_t offset : 16; /* Execution Offset */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST 0xc +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST)) + +/* + * Register : Expected CRC Register - crc + * + * Length of region in On-chip RAM for CRC validation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------- + * [31:0] | RW | 0xe763552a | Expected CRC + * + */ +/* + * Field : Expected CRC - expected + * + * Contains the expected CRC of the region in the On-chip RAM.The Boot ROM code + * calculates the actual CRC for all bytes in the region specified by the DATA + * START an LENGTH registers. The contents of the EXECUTION register (after it has + * been read and modified by the Boot ROM code) is also included in the CRC + * calculation. The contents of the EXECUTION register is added to the CRC + * accumulator a byte at a time starting with the least significant byte. If the + * actual CRC doesn't match the expected CRC value in this register, the Boot ROM + * won't boot from the On-chip RAM. + * + * The CRC is a standard CRC32 with the polynomial: + * + * x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + + * x^2 + x + 1 + * + * There is no reflection of the bits and the initial value of the remainder is + * 0xFFFFFFFF and the final value is exclusive ORed with 0xFFFFFFFF. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_RESET 0xe763552a +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_CRC. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s +{ + uint32_t expected : 32; /* Expected CRC */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_CRC. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST 0x10 +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ROMCODE_WARMRAM. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_s +{ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_EN_t enable; /* ALT_SYSMGR_ROMCODE_WARMRAM_EN */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t datastart; /* ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t length; /* ALT_SYSMGR_ROMCODE_WARMRAM_LEN */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t execution; /* ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t crc; /* ALT_SYSMGR_ROMCODE_WARMRAM_CRC */ + volatile uint32_t _pad_0x14_0x20[3]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ROMCODE_WARMRAM. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_s ALT_SYSMGR_ROMCODE_WARMRAM_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE_WARMRAM. */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s +{ + volatile uint32_t enable; /* ALT_SYSMGR_ROMCODE_WARMRAM_EN */ + volatile uint32_t datastart; /* ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART */ + volatile uint32_t length; /* ALT_SYSMGR_ROMCODE_WARMRAM_LEN */ + volatile uint32_t execution; /* ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION */ + volatile uint32_t crc; /* ALT_SYSMGR_ROMCODE_WARMRAM_CRC */ + volatile uint32_t _pad_0x14_0x20[3]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE_WARMRAM. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s ALT_SYSMGR_ROMCODE_WARMRAM_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ROMCODE. + */ +struct ALT_SYSMGR_ROMCODE_s +{ + volatile ALT_SYSMGR_ROMCODE_CTL_t ctrl; /* ALT_SYSMGR_ROMCODE_CTL */ + volatile ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t cpu1startaddr; /* ALT_SYSMGR_ROMCODE_CPU1STARTADDR */ + volatile ALT_SYSMGR_ROMCODE_INITSWSTATE_t initswstate; /* ALT_SYSMGR_ROMCODE_INITSWSTATE */ + volatile ALT_SYSMGR_ROMCODE_INITSWLASTLD_t initswlastld; /* ALT_SYSMGR_ROMCODE_INITSWLASTLD */ + volatile ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t bootromswstate; /* ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE */ + volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_t romcodegrp_warmramgrp; /* ALT_SYSMGR_ROMCODE_WARMRAM */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ROMCODE. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_s ALT_SYSMGR_ROMCODE_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE. */ +struct ALT_SYSMGR_ROMCODE_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_ROMCODE_CTL */ + volatile uint32_t cpu1startaddr; /* ALT_SYSMGR_ROMCODE_CPU1STARTADDR */ + volatile uint32_t initswstate; /* ALT_SYSMGR_ROMCODE_INITSWSTATE */ + volatile uint32_t initswlastld; /* ALT_SYSMGR_ROMCODE_INITSWLASTLD */ + volatile uint32_t bootromswstate; /* ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE */ + volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_raw_t romcodegrp_warmramgrp; /* ALT_SYSMGR_ROMCODE_WARMRAM */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_raw_s ALT_SYSMGR_ROMCODE_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Boot ROM Hardware Register Group - ALT_SYSMGR_ROMHW + * Boot ROM Hardware Register Group + * + * Registers used by the Boot ROM hardware, not the code within it. + * + */ +/* + * Register : Boot ROM Hardware Control Register - ctrl + * + * Controls behavior of Boot ROM hardware. + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------- + * [0] | RW | 0x0 | Wait State + * [1] | RW | 0x1 | Enable Safe Mode Warm Reset Update + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Wait State - waitstate + * + * Controls the number of wait states applied to the Boot ROM's read operation. + * + * This field is cleared on a cold reset and optionally updated by hardware upon + * deassertion of warm reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS | 0x0 | No wait states are applied to the Boom ROM's + * : | | read operation. + * ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN | 0x1 | A single wait state is applied to the Boot ROM's + * : | | read operation. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE + * + * No wait states are applied to the Boom ROM's read operation. + */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE + * + * A single wait state is applied to the Boot ROM's read operation. + */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_MSB 0 +/* The width in bits of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMHW_CTL_WAITSTATE field value from a register. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable Safe Mode Warm Reset Update - ensfmdwru + * + * Controls whether the wait state bit is updated upon deassertion of warm reset. + * + * This field is set on a cold reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS | 0x0 | Wait state bit is not updated upon deassertion + * : | | of warm reset. + * ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN | 0x1 | Wait state bit is updated upon deassertion of + * : | | warm reset. It's value is updated based on the + * : | | control bit from clock manager which specifies + * : | | whether clock manager will be in safe mode or + * : | | not after warm reset. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU + * + * Wait state bit is not updated upon deassertion of warm reset. + */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU + * + * Wait state bit is updated upon deassertion of warm reset. + * + * It's value is updated based on the control bit from clock manager which + * specifies whether clock manager will be in safe mode or not after warm reset. + */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_MSB 1 +/* The width in bits of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_RESET 0x1 +/* Extracts the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU field value from a register. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMHW_CTL. + */ +struct ALT_SYSMGR_ROMHW_CTL_s +{ + uint32_t waitstate : 1; /* Wait State */ + uint32_t ensfmdwru : 1; /* Enable Safe Mode Warm Reset Update */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMHW_CTL. */ +typedef volatile struct ALT_SYSMGR_ROMHW_CTL_s ALT_SYSMGR_ROMHW_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMHW_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_ROMHW_CTL_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ROMHW. + */ +struct ALT_SYSMGR_ROMHW_s +{ + volatile ALT_SYSMGR_ROMHW_CTL_t ctrl; /* ALT_SYSMGR_ROMHW_CTL */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ROMHW. */ +typedef volatile struct ALT_SYSMGR_ROMHW_s ALT_SYSMGR_ROMHW_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMHW. */ +struct ALT_SYSMGR_ROMHW_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_ROMHW_CTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMHW. */ +typedef volatile struct ALT_SYSMGR_ROMHW_raw_s ALT_SYSMGR_ROMHW_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : SDMMC Controller Group - ALT_SYSMGR_SDMMC + * SDMMC Controller Group + * + * Registers related to SDMMC Controller which aren't located inside the SDMMC + * itself. + * + */ +/* + * Register : Control Register - ctrl + * + * Registers used by the SDMMC Controller. All fields are reset by a cold or warm + * reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [2:0] | RW | 0x0 | Drive Clock Phase Shift Select + * [5:3] | RW | 0x0 | Sample Clock Phase Shift Select + * [6] | RW | 0x0 | Feedback Clock Select + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Drive Clock Phase Shift Select - drvsel + * + * Select which phase shift of the clock for cclk_in_drv. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------------- + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 | 0x0 | 0 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 | 0x1 | 45 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 | 0x2 | 90 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 | 0x3 | 135 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 | 0x4 | 180 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 | 0x5 | 225 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 | 0x6 | 270 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 | 0x7 | 315 degrees phase shifted clock is selected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 0 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 45 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 90 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 135 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 180 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 225 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 270 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 315 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_MSB 2 +/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_WIDTH 3 +/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET_MSK 0x00000007 +/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_CTL_DRVSEL field value from a register. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : Sample Clock Phase Shift Select - smplsel + * + * Select which phase shift of the clock for cclk_in_sample. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------------------- + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 | 0x0 | 0 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 | 0x1 | 45 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 | 0x2 | 90 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 | 0x3 | 135 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 | 0x4 | 180 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 | 0x5 | 225 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 | 0x6 | 270 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 | 0x7 | 315 degrees phase shifted clock is selected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 0 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 45 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 90 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 135 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 180 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 225 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 270 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 315 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_MSB 5 +/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_WIDTH 3 +/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET_MSK 0x00000038 +/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_CLR_MSK 0xffffffc7 +/* The reset value of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_CTL_SMPLSEL field value from a register. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_GET(value) (((value) & 0x00000038) >> 3) +/* Produces a ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET(value) (((value) << 3) & 0x00000038) + +/* + * Field : Feedback Clock Select - fbclksel + * + * Select which fb_clk to be used as cclk_in_sample. + * + * If 0, cclk_in_sample is driven by internal phase shifted cclk_in. + * + * If 1, cclk_in_sample is driven by fb_clk_in. No phase shifting is provided + * internally on cclk_in_sample. + * + * Note: Using the feedback clock (setting this bit to 1) is not a supported use + * model. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_MSB 6 +/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL field value from a register. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SDMMC_CTL. + */ +struct ALT_SYSMGR_SDMMC_CTL_s +{ + uint32_t drvsel : 3; /* Drive Clock Phase Shift Select */ + uint32_t smplsel : 3; /* Sample Clock Phase Shift Select */ + uint32_t fbclksel : 1; /* Feedback Clock Select */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SDMMC_CTL. */ +typedef volatile struct ALT_SYSMGR_SDMMC_CTL_s ALT_SYSMGR_SDMMC_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SDMMC_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_SDMMC_CTL_OFST 0x0 + +/* + * Register : SD/MMC L3 Master HPROT Register - l3master + * + * Controls the L3 master HPROT AHB-Lite signal. + * + * These register bits should be updated only during system initialization prior to + * removing the peripheral from reset. They may not be changed dynamically during + * peripheral operation + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [0] | RW | 0x1 | SD/MMC HPROT Data/Opcode + * [1] | RW | 0x1 | SD/MMC HPROT Privileged + * [2] | RW | 0x0 | SD/MMC HPROT Bufferable + * [3] | RW | 0x0 | SD/MMC HPROT Cacheable + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SD/MMC HPROT Data/Opcode - hprotdata_0 + * + * Specifies if the L3 master access is for data or opcode for the SD/MMC module. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE | 0x0 | Opcode fetch + * ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA | 0x1 | Data access + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 + * + * Opcode fetch + */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 + * + * Data access + */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_MSB 0 +/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_RESET 0x1 +/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 field value from a register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SD/MMC HPROT Privileged - hprotpriv_0 + * + * If 1, L3 master accesses for the SD/MMC module are privileged. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_MSB 1 +/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_RESET 0x1 +/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 field value from a register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SD/MMC HPROT Bufferable - hprotbuff_0 + * + * If 1, L3 master accesses for the SD/MMC module are bufferable. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_MSB 2 +/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 field value from a register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SD/MMC HPROT Cacheable - hprotcache_0 + * + * If 1, L3 master accesses for the SD/MMC module are cacheable. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_MSB 3 +/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 field value from a register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SDMMC_L3MST. + */ +struct ALT_SYSMGR_SDMMC_L3MST_s +{ + uint32_t hprotdata_0 : 1; /* SD/MMC HPROT Data/Opcode */ + uint32_t hprotpriv_0 : 1; /* SD/MMC HPROT Privileged */ + uint32_t hprotbuff_0 : 1; /* SD/MMC HPROT Bufferable */ + uint32_t hprotcache_0 : 1; /* SD/MMC HPROT Cacheable */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SDMMC_L3MST. */ +typedef volatile struct ALT_SYSMGR_SDMMC_L3MST_s ALT_SYSMGR_SDMMC_L3MST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SDMMC_L3MST register from the beginning of the component. */ +#define ALT_SYSMGR_SDMMC_L3MST_OFST 0x4 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_SDMMC. + */ +struct ALT_SYSMGR_SDMMC_s +{ + volatile ALT_SYSMGR_SDMMC_CTL_t ctrl; /* ALT_SYSMGR_SDMMC_CTL */ + volatile ALT_SYSMGR_SDMMC_L3MST_t l3master; /* ALT_SYSMGR_SDMMC_L3MST */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_SDMMC. */ +typedef volatile struct ALT_SYSMGR_SDMMC_s ALT_SYSMGR_SDMMC_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_SDMMC. */ +struct ALT_SYSMGR_SDMMC_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_SDMMC_CTL */ + volatile uint32_t l3master; /* ALT_SYSMGR_SDMMC_L3MST */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_SDMMC. */ +typedef volatile struct ALT_SYSMGR_SDMMC_raw_s ALT_SYSMGR_SDMMC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : NAND Flash Controller Register Group - ALT_SYSMGR_NAND + * NAND Flash Controller Register Group + * + * Registers related to NAND Flash Controller which aren't located in the NAND + * Flash Controller itself. + * + */ +/* + * Register : Bootstrap Control Register - bootstrap + * + * Bootstrap fields sampled by NAND Flash Controller when released from reset. + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------- + * [0] | RW | 0x0 | Bootstrap Inhibit Initialization + * [1] | RW | 0x0 | Bootstrap 512 Byte Device + * [2] | RW | 0x0 | Bootstrap Inhibit Load Block 0 Page 0 + * [3] | RW | 0x0 | Bootstrap Two Row Address Cycles + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bootstrap Inhibit Initialization - noinit + * + * If 1, inhibits NAND Flash Controller from performing initialization when coming + * out of reset. Instead, software must program all registers pertaining to device + * parameters like page size, width, etc. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_MSB 0 +/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT field value from a register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Bootstrap 512 Byte Device - page512 + * + * If 1, NAND device has a 512 byte page size. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_MSB 1 +/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 field value from a register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Bootstrap Inhibit Load Block 0 Page 0 - noloadb0p0 + * + * If 1, inhibits NAND Flash Controller from loading page 0 of block 0 of the NAND + * device as part of the initialization procedure. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_MSB 2 +/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 field value from a register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Bootstrap Two Row Address Cycles - tworowaddr + * + * If 1, NAND device requires only 2 row address cycles instead of the normal 3 row + * address cycles. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_MSB 3 +/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR field value from a register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_NAND_BOOTSTRAP. + */ +struct ALT_SYSMGR_NAND_BOOTSTRAP_s +{ + uint32_t noinit : 1; /* Bootstrap Inhibit Initialization */ + uint32_t page512 : 1; /* Bootstrap 512 Byte Device */ + uint32_t noloadb0p0 : 1; /* Bootstrap Inhibit Load Block 0 Page 0 */ + uint32_t tworowaddr : 1; /* Bootstrap Two Row Address Cycles */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_NAND_BOOTSTRAP. */ +typedef volatile struct ALT_SYSMGR_NAND_BOOTSTRAP_s ALT_SYSMGR_NAND_BOOTSTRAP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_NAND_BOOTSTRAP register from the beginning of the component. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_OFST 0x0 + +/* + * Register : NAND L3 Master AxCACHE Register - l3master + * + * Controls the L3 master ARCACHE and AWCACHE AXI signals. + * + * These register bits should be updated only during system initialization prior to + * removing the peripheral from reset. They may not be changed dynamically during + * peripheral operation + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [3:0] | RW | 0x0 | NAND ARCACHE + * [7:4] | RW | 0x0 | NAND AWCACHE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NAND ARCACHE - arcache_0 + * + * Specifies the value of the module ARCACHE signal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Bufferable only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_MSB 3 +/* The width in bits of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 field value from a register. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : NAND AWCACHE - awcache_0 + * + * Specifies the value of the module AWCACHE signal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Bufferable only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_MSB 7 +/* The width in bits of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_CLR_MSK 0xffffff0f +/* The reset value of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 field value from a register. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_NAND_L3MST. + */ +struct ALT_SYSMGR_NAND_L3MST_s +{ + uint32_t arcache_0 : 4; /* NAND ARCACHE */ + uint32_t awcache_0 : 4; /* NAND AWCACHE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_NAND_L3MST. */ +typedef volatile struct ALT_SYSMGR_NAND_L3MST_s ALT_SYSMGR_NAND_L3MST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_NAND_L3MST register from the beginning of the component. */ +#define ALT_SYSMGR_NAND_L3MST_OFST 0x4 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_NAND. + */ +struct ALT_SYSMGR_NAND_s +{ + volatile ALT_SYSMGR_NAND_BOOTSTRAP_t bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */ + volatile ALT_SYSMGR_NAND_L3MST_t l3master; /* ALT_SYSMGR_NAND_L3MST */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_NAND. */ +typedef volatile struct ALT_SYSMGR_NAND_s ALT_SYSMGR_NAND_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_NAND. */ +struct ALT_SYSMGR_NAND_raw_s +{ + volatile uint32_t bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */ + volatile uint32_t l3master; /* ALT_SYSMGR_NAND_L3MST */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_NAND. */ +typedef volatile struct ALT_SYSMGR_NAND_raw_s ALT_SYSMGR_NAND_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB Controller Group - ALT_SYSMGR_USB + * USB Controller Group + * + * Registers related to USB Controllers which aren't located inside the USB + * controllers themselves. + * + */ +/* + * Register : USB L3 Master HPROT Register - l3master + * + * Controls the L3 master HPROT AHB-Lite signal. + * + * These register bits should be updated only during system initialization prior to + * removing the peripheral from reset. They may not be changed dynamically during + * peripheral operation + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | RW | 0x1 | USB HPROT Data/Opcode + * [1] | RW | 0x1 | USB HPROT Data/Opcode + * [2] | RW | 0x1 | USB HPROT Privileged + * [3] | RW | 0x1 | USB HPROT Privileged + * [4] | RW | 0x0 | USB HPROT Bufferable + * [5] | RW | 0x0 | USB HPROT Bufferable + * [6] | RW | 0x0 | USB HPROT Cacheable + * [7] | RW | 0x0 | USB HPROT Cacheable + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB HPROT Data/Opcode - hprotdata_0 + * + * Specifies if the L3 master access is for data or opcode for the USB modules. + * + * The field array index corresponds to the USB index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------- + * ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE | 0x0 | Opcode fetch + * ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA | 0x1 | Data access + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_0 + * + * Opcode fetch + */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_0 + * + * Data access + */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_MSB 0 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_RESET 0x1 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : USB HPROT Data/Opcode - hprotdata_1 + * + * Specifies if the L3 master access is for data or opcode for the USB modules. + * + * The field array index corresponds to the USB index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------- + * ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE | 0x0 | Opcode fetch + * ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA | 0x1 | Data access + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_1 + * + * Opcode fetch + */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_1 + * + * Data access + */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_MSB 1 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_RESET 0x1 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : USB HPROT Privileged - hprotpriv_0 + * + * If 1, L3 master accesses for the USB modules are privileged. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_MSB 2 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_RESET 0x1 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : USB HPROT Privileged - hprotpriv_1 + * + * If 1, L3 master accesses for the USB modules are privileged. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_RESET 0x1 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : USB HPROT Bufferable - hprotbuff_0 + * + * If 1, L3 master accesses for the USB modules are bufferable. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_MSB 4 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : USB HPROT Bufferable - hprotbuff_1 + * + * If 1, L3 master accesses for the USB modules are bufferable. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_MSB 5 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : USB HPROT Cacheable - hprotcache_0 + * + * If 1, L3 master accesses for the USB modules are cacheable. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_MSB 6 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : USB HPROT Cacheable - hprotcache_1 + * + * If 1, L3 master accesses for the USB modules are cacheable. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_MSB 7 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_USB_L3MST. + */ +struct ALT_SYSMGR_USB_L3MST_s +{ + uint32_t hprotdata_0 : 1; /* USB HPROT Data/Opcode */ + uint32_t hprotdata_1 : 1; /* USB HPROT Data/Opcode */ + uint32_t hprotpriv_0 : 1; /* USB HPROT Privileged */ + uint32_t hprotpriv_1 : 1; /* USB HPROT Privileged */ + uint32_t hprotbuff_0 : 1; /* USB HPROT Bufferable */ + uint32_t hprotbuff_1 : 1; /* USB HPROT Bufferable */ + uint32_t hprotcache_0 : 1; /* USB HPROT Cacheable */ + uint32_t hprotcache_1 : 1; /* USB HPROT Cacheable */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_USB_L3MST. */ +typedef volatile struct ALT_SYSMGR_USB_L3MST_s ALT_SYSMGR_USB_L3MST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_USB_L3MST register from the beginning of the component. */ +#define ALT_SYSMGR_USB_L3MST_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_USB. + */ +struct ALT_SYSMGR_USB_s +{ + volatile ALT_SYSMGR_USB_L3MST_t l3master; /* ALT_SYSMGR_USB_L3MST */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_USB. */ +typedef volatile struct ALT_SYSMGR_USB_s ALT_SYSMGR_USB_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_USB. */ +struct ALT_SYSMGR_USB_raw_s +{ + volatile uint32_t l3master; /* ALT_SYSMGR_USB_L3MST */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_USB. */ +typedef volatile struct ALT_SYSMGR_USB_raw_s ALT_SYSMGR_USB_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ECC Management Register Group - ALT_SYSMGR_ECC + * ECC Management Register Group + * + * ECC error status and control for all ECC-protected HPS RAM blocks. + * + */ +/* + * Register : L2 Data RAM ECC Enable Register - l2 + * + * This register is used to enable ECC on the L2 Data RAM. ECC errors can be + * injected into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------------------------- + * [0] | RW | 0x0 | L2 Data RAM ECC Enable + * [1] | RW | 0x0 | L2 Data RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | L2 Data RAM ECC inject double bit, non-correctable error + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : L2 Data RAM ECC Enable - en + * + * Enable ECC for L2 Data RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_EN register field. */ +#define ALT_SYSMGR_ECC_L2_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_EN register field. */ +#define ALT_SYSMGR_ECC_L2_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_L2_EN register field. */ +#define ALT_SYSMGR_ECC_L2_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_L2_EN register field value. */ +#define ALT_SYSMGR_ECC_L2_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_L2_EN register field value. */ +#define ALT_SYSMGR_ECC_L2_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_L2_EN register field. */ +#define ALT_SYSMGR_ECC_L2_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_L2_EN field value from a register. */ +#define ALT_SYSMGR_ECC_L2_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_L2_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_L2_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : L2 Data RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * L2 Data RAM. This only injects one error into the L2 Data RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_INJS register field. */ +#define ALT_SYSMGR_ECC_L2_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_INJS register field. */ +#define ALT_SYSMGR_ECC_L2_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_L2_INJS register field. */ +#define ALT_SYSMGR_ECC_L2_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_L2_INJS register field value. */ +#define ALT_SYSMGR_ECC_L2_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_L2_INJS register field value. */ +#define ALT_SYSMGR_ECC_L2_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_L2_INJS register field. */ +#define ALT_SYSMGR_ECC_L2_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_L2_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_L2_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_L2_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_L2_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : L2 Data RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the L2 Data RAM. This only injects one double bit error into the L2 Data RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_INJD register field. */ +#define ALT_SYSMGR_ECC_L2_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_INJD register field. */ +#define ALT_SYSMGR_ECC_L2_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_L2_INJD register field. */ +#define ALT_SYSMGR_ECC_L2_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_L2_INJD register field value. */ +#define ALT_SYSMGR_ECC_L2_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_L2_INJD register field value. */ +#define ALT_SYSMGR_ECC_L2_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_L2_INJD register field. */ +#define ALT_SYSMGR_ECC_L2_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_L2_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_L2_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_L2_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_L2_INJD_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_L2. + */ +struct ALT_SYSMGR_ECC_L2_s +{ + uint32_t en : 1; /* L2 Data RAM ECC Enable */ + uint32_t injs : 1; /* L2 Data RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* L2 Data RAM ECC inject double bit, non-correctable error */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_L2. */ +typedef volatile struct ALT_SYSMGR_ECC_L2_s ALT_SYSMGR_ECC_L2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_L2 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_L2_OFST 0x0 + +/* + * Register : On-chip RAM ECC Enable Register - ocram + * + * This register is used to enable ECC on the On-chip RAM. ECC errors can be + * injected into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------------------------- + * [0] | RW | 0x0 | On-chip RAM ECC Enable + * [1] | RW | 0x0 | On-chip RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | On-chip RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | On-chip RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | On-chip RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : On-chip RAM ECC Enable - en + * + * Enable ECC for On-chip RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_EN register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_EN register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_EN field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_OCRAM_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : On-chip RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * On-chip RAM. This only injects one error into the On-chip RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_INJS register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_INJS register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_OCRAM_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : On-chip RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the On-chip RAM. This only injects one double bit error into the On-chip RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_INJD register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_INJD register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_OCRAM_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : On-chip RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for On-chip RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in On-chip + * RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_SERR register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_SERR register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_OCRAM_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : On-chip RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for On-chip RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in On-chip RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_DERR register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_DERR register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_OCRAM_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_OCRAM. + */ +struct ALT_SYSMGR_ECC_OCRAM_s +{ + uint32_t en : 1; /* On-chip RAM ECC Enable */ + uint32_t injs : 1; /* On-chip RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* On-chip RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* On-chip RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* On-chip RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_OCRAM. */ +typedef volatile struct ALT_SYSMGR_ECC_OCRAM_s ALT_SYSMGR_ECC_OCRAM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_OCRAM register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_OCRAM_OFST 0x4 + +/* + * Register : USB0 RAM ECC Enable Register - usb0 + * + * This register is used to enable ECC on the USB0 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | USB0 RAM ECC Enable + * [1] | RW | 0x0 | USB0 RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | USB0 RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | USB0 RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | USB0 RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB0 RAM ECC Enable - en + * + * Enable ECC for USB0 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_EN register field. */ +#define ALT_SYSMGR_ECC_USB0_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_EN register field. */ +#define ALT_SYSMGR_ECC_USB0_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_EN register field. */ +#define ALT_SYSMGR_ECC_USB0_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_EN register field value. */ +#define ALT_SYSMGR_ECC_USB0_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_EN register field value. */ +#define ALT_SYSMGR_ECC_USB0_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_USB0_EN register field. */ +#define ALT_SYSMGR_ECC_USB0_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_EN field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_USB0_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : USB0 RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * USB0 RAM. This only injects one error into the USB0 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_INJS register field. */ +#define ALT_SYSMGR_ECC_USB0_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_INJS register field. */ +#define ALT_SYSMGR_ECC_USB0_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_INJS register field. */ +#define ALT_SYSMGR_ECC_USB0_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_INJS register field value. */ +#define ALT_SYSMGR_ECC_USB0_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_INJS register field value. */ +#define ALT_SYSMGR_ECC_USB0_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_USB0_INJS register field. */ +#define ALT_SYSMGR_ECC_USB0_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_USB0_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : USB0 RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the USB0 RAM. This only injects one double bit error into the USB0 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_INJD register field. */ +#define ALT_SYSMGR_ECC_USB0_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_INJD register field. */ +#define ALT_SYSMGR_ECC_USB0_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_INJD register field. */ +#define ALT_SYSMGR_ECC_USB0_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_INJD register field value. */ +#define ALT_SYSMGR_ECC_USB0_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_INJD register field value. */ +#define ALT_SYSMGR_ECC_USB0_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_USB0_INJD register field. */ +#define ALT_SYSMGR_ECC_USB0_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_USB0_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : USB0 RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for USB0 RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in USB0 RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_SERR register field. */ +#define ALT_SYSMGR_ECC_USB0_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_SERR register field. */ +#define ALT_SYSMGR_ECC_USB0_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_SERR register field. */ +#define ALT_SYSMGR_ECC_USB0_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_SERR register field value. */ +#define ALT_SYSMGR_ECC_USB0_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_SERR register field value. */ +#define ALT_SYSMGR_ECC_USB0_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_USB0_SERR register field. */ +#define ALT_SYSMGR_ECC_USB0_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_USB0_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : USB0 RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for USB0 RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * USB0 RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_DERR register field. */ +#define ALT_SYSMGR_ECC_USB0_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_DERR register field. */ +#define ALT_SYSMGR_ECC_USB0_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_DERR register field. */ +#define ALT_SYSMGR_ECC_USB0_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_DERR register field value. */ +#define ALT_SYSMGR_ECC_USB0_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_DERR register field value. */ +#define ALT_SYSMGR_ECC_USB0_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_USB0_DERR register field. */ +#define ALT_SYSMGR_ECC_USB0_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_USB0_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_USB0. + */ +struct ALT_SYSMGR_ECC_USB0_s +{ + uint32_t en : 1; /* USB0 RAM ECC Enable */ + uint32_t injs : 1; /* USB0 RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* USB0 RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* USB0 RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* USB0 RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_USB0. */ +typedef volatile struct ALT_SYSMGR_ECC_USB0_s ALT_SYSMGR_ECC_USB0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_USB0 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_USB0_OFST 0x8 + +/* + * Register : USB1 RAM ECC Enable Register - usb1 + * + * This register is used to enable ECC on the USB1 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | USB1 RAM ECC Enable + * [1] | RW | 0x0 | USB1 RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | USB1 RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | USB1 RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | USB1 RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB1 RAM ECC Enable - en + * + * Enable ECC for USB1 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_EN register field. */ +#define ALT_SYSMGR_ECC_USB1_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_EN register field. */ +#define ALT_SYSMGR_ECC_USB1_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_EN register field. */ +#define ALT_SYSMGR_ECC_USB1_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_EN register field value. */ +#define ALT_SYSMGR_ECC_USB1_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_EN register field value. */ +#define ALT_SYSMGR_ECC_USB1_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_USB1_EN register field. */ +#define ALT_SYSMGR_ECC_USB1_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_EN field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_USB1_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : USB1 RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * USB1 RAM. This only injects one error into the USB1 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_INJS register field. */ +#define ALT_SYSMGR_ECC_USB1_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_INJS register field. */ +#define ALT_SYSMGR_ECC_USB1_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_INJS register field. */ +#define ALT_SYSMGR_ECC_USB1_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_INJS register field value. */ +#define ALT_SYSMGR_ECC_USB1_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_INJS register field value. */ +#define ALT_SYSMGR_ECC_USB1_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_USB1_INJS register field. */ +#define ALT_SYSMGR_ECC_USB1_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_USB1_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : USB1 RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the USB1 RAM. This only injects one double bit error into the USB1 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_INJD register field. */ +#define ALT_SYSMGR_ECC_USB1_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_INJD register field. */ +#define ALT_SYSMGR_ECC_USB1_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_INJD register field. */ +#define ALT_SYSMGR_ECC_USB1_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_INJD register field value. */ +#define ALT_SYSMGR_ECC_USB1_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_INJD register field value. */ +#define ALT_SYSMGR_ECC_USB1_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_USB1_INJD register field. */ +#define ALT_SYSMGR_ECC_USB1_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_USB1_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : USB1 RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for USB1 RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in USB1 RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_SERR register field. */ +#define ALT_SYSMGR_ECC_USB1_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_SERR register field. */ +#define ALT_SYSMGR_ECC_USB1_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_SERR register field. */ +#define ALT_SYSMGR_ECC_USB1_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_SERR register field value. */ +#define ALT_SYSMGR_ECC_USB1_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_SERR register field value. */ +#define ALT_SYSMGR_ECC_USB1_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_USB1_SERR register field. */ +#define ALT_SYSMGR_ECC_USB1_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_USB1_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : USB1 RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for USB1 RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * USB1 RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_DERR register field. */ +#define ALT_SYSMGR_ECC_USB1_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_DERR register field. */ +#define ALT_SYSMGR_ECC_USB1_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_DERR register field. */ +#define ALT_SYSMGR_ECC_USB1_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_DERR register field value. */ +#define ALT_SYSMGR_ECC_USB1_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_DERR register field value. */ +#define ALT_SYSMGR_ECC_USB1_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_USB1_DERR register field. */ +#define ALT_SYSMGR_ECC_USB1_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_USB1_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_USB1. + */ +struct ALT_SYSMGR_ECC_USB1_s +{ + uint32_t en : 1; /* USB1 RAM ECC Enable */ + uint32_t injs : 1; /* USB1 RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* USB1 RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* USB1 RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* USB1 RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_USB1. */ +typedef volatile struct ALT_SYSMGR_ECC_USB1_s ALT_SYSMGR_ECC_USB1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_USB1 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_USB1_OFST 0xc + +/* + * Register : EMAC0 RAM ECC Enable Register - emac0 + * + * This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------------------------------ + * [0] | RW | 0x0 | EMAC0 RAM ECC Enable + * [1] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject single, correctable Error + * [4] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error + * [5] | RW | 0x0 | EMAC0 TXFIFO RAM ECC single, correctable error interrupt status + * [6] | RW | 0x0 | EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status + * [7] | RW | 0x0 | EMAC0 RXFIFO RAM ECC single, correctable error interrupt status + * [8] | RW | 0x0 | EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC0 RAM ECC Enable - en + * + * Enable ECC for EMAC0 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_EN register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_EN register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_EN field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_EMAC0_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : EMAC0 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * EMAC0 TXFIFO RAM. This only injects one error into the EMAC0 TXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the EMAC0 TXFIFO RAM. This only injects one double bit error into the EMAC0 + * TXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : EMAC0 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * EMAC0 RXFIFO RAM. This only injects one error into the EMAC0 RXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the EMAC0 RXFIFO RAM. This only injects one double bit error into the EMAC0 + * RXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : EMAC0 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr + * + * This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in EMAC0 + * TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_MSB 5 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr + * + * This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in EMAC0 TXFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_MSB 6 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : EMAC0 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr + * + * This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in EMAC0 + * RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_MSB 7 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr + * + * This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in EMAC0 RXFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_MSB 8 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_EMAC0. + */ +struct ALT_SYSMGR_ECC_EMAC0_s +{ + uint32_t en : 1; /* EMAC0 RAM ECC Enable */ + uint32_t txfifoinjs : 1; /* EMAC0 TXFIFO RAM ECC inject single, correctable Error */ + uint32_t txfifoinjd : 1; /* EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t rxfifoinjs : 1; /* EMAC0 RXFIFO RAM ECC inject single, correctable Error */ + uint32_t rxfifoinjd : 1; /* EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t txfifoserr : 1; /* EMAC0 TXFIFO RAM ECC single, correctable error interrupt status */ + uint32_t txfifoderr : 1; /* EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t rxfifoserr : 1; /* EMAC0 RXFIFO RAM ECC single, correctable error interrupt status */ + uint32_t rxfifoderr : 1; /* EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_EMAC0. */ +typedef volatile struct ALT_SYSMGR_ECC_EMAC0_s ALT_SYSMGR_ECC_EMAC0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_EMAC0 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_EMAC0_OFST 0x10 + +/* + * Register : EMAC1 RAM ECC Enable Register - emac1 + * + * This register is used to enable ECC on the EMAC1 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------------------------------ + * [0] | RW | 0x0 | EMAC1 RAM ECC Enable + * [1] | RW | 0x0 | EMAC1 TXFIFO RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | EMAC1 RXFIFO RAM ECC inject single, correctable Error + * [4] | RW | 0x0 | EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error + * [5] | RW | 0x0 | EMAC1 TXFIFO RAM ECC single, correctable error interrupt status + * [6] | RW | 0x0 | EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status + * [7] | RW | 0x0 | EMAC1 RXFIFO RAM ECC single, correctable error interrupt status + * [8] | RW | 0x0 | EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC1 RAM ECC Enable - en + * + * Enable ECC for EMAC1 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_EN register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_EN register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_EN field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_EMAC1_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : EMAC1 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * EMAC1 TXFIFO RAM. This only injects one error into the EMAC1 TXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the EMAC1 TXFIFO RAM. This only injects one double bit error into the EMAC1 + * TXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : EMAC1 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * EMAC1 RXFIFO RAM. This only injects one error into the EMAC1 RXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the EMAC1 RXFIFO RAM. This only injects one double bit error into the EMAC1 + * RXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : EMAC1 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr + * + * This bit is an interrupt status bit for EMAC1 TXFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in EMAC1 + * TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_MSB 5 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr + * + * This bit is an interrupt status bit for EMAC1 TXFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in EMAC1 TXFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_MSB 6 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : EMAC1 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr + * + * This bit is an interrupt status bit for EMAC1 RXFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in EMAC1 + * RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_MSB 7 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr + * + * This bit is an interrupt status bit for EMAC1 RXFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in EMAC1 RXFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_MSB 8 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_EMAC1. + */ +struct ALT_SYSMGR_ECC_EMAC1_s +{ + uint32_t en : 1; /* EMAC1 RAM ECC Enable */ + uint32_t txfifoinjs : 1; /* EMAC1 TXFIFO RAM ECC inject single, correctable Error */ + uint32_t txfifoinjd : 1; /* EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t rxfifoinjs : 1; /* EMAC1 RXFIFO RAM ECC inject single, correctable Error */ + uint32_t rxfifoinjd : 1; /* EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t txfifoserr : 1; /* EMAC1 TXFIFO RAM ECC single, correctable error interrupt status */ + uint32_t txfifoderr : 1; /* EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t rxfifoserr : 1; /* EMAC1 RXFIFO RAM ECC single, correctable error interrupt status */ + uint32_t rxfifoderr : 1; /* EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_EMAC1. */ +typedef volatile struct ALT_SYSMGR_ECC_EMAC1_s ALT_SYSMGR_ECC_EMAC1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_EMAC1 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_EMAC1_OFST 0x14 + +/* + * Register : DMA RAM ECC Enable Register - dma + * + * This register is used to enable ECC on the DMA RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------------------------------- + * [0] | RW | 0x0 | DMA RAM ECC Enable + * [1] | RW | 0x0 | DMA RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | DMA RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | DMA RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | DMA RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DMA RAM ECC Enable - en + * + * Enable ECC for DMA RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_EN register field. */ +#define ALT_SYSMGR_ECC_DMA_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_EN register field. */ +#define ALT_SYSMGR_ECC_DMA_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_EN register field. */ +#define ALT_SYSMGR_ECC_DMA_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_EN register field value. */ +#define ALT_SYSMGR_ECC_DMA_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_EN register field value. */ +#define ALT_SYSMGR_ECC_DMA_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_DMA_EN register field. */ +#define ALT_SYSMGR_ECC_DMA_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_EN field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_DMA_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : DMA RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * DMA RAM. This only injects one error into the DMA RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_INJS register field. */ +#define ALT_SYSMGR_ECC_DMA_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_INJS register field. */ +#define ALT_SYSMGR_ECC_DMA_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_INJS register field. */ +#define ALT_SYSMGR_ECC_DMA_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_INJS register field value. */ +#define ALT_SYSMGR_ECC_DMA_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_INJS register field value. */ +#define ALT_SYSMGR_ECC_DMA_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_DMA_INJS register field. */ +#define ALT_SYSMGR_ECC_DMA_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_DMA_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : DMA RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the DMA RAM. This only injects one double bit error into the DMA RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_INJD register field. */ +#define ALT_SYSMGR_ECC_DMA_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_INJD register field. */ +#define ALT_SYSMGR_ECC_DMA_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_INJD register field. */ +#define ALT_SYSMGR_ECC_DMA_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_INJD register field value. */ +#define ALT_SYSMGR_ECC_DMA_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_INJD register field value. */ +#define ALT_SYSMGR_ECC_DMA_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_DMA_INJD register field. */ +#define ALT_SYSMGR_ECC_DMA_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_DMA_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DMA RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for DMA RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in DMA RAM. Software + * needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_SERR register field. */ +#define ALT_SYSMGR_ECC_DMA_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_SERR register field. */ +#define ALT_SYSMGR_ECC_DMA_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_SERR register field. */ +#define ALT_SYSMGR_ECC_DMA_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_SERR register field value. */ +#define ALT_SYSMGR_ECC_DMA_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_SERR register field value. */ +#define ALT_SYSMGR_ECC_DMA_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_DMA_SERR register field. */ +#define ALT_SYSMGR_ECC_DMA_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_DMA_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : DMA RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for DMA RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * DMA RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_DERR register field. */ +#define ALT_SYSMGR_ECC_DMA_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_DERR register field. */ +#define ALT_SYSMGR_ECC_DMA_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_DERR register field. */ +#define ALT_SYSMGR_ECC_DMA_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_DERR register field value. */ +#define ALT_SYSMGR_ECC_DMA_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_DERR register field value. */ +#define ALT_SYSMGR_ECC_DMA_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_DMA_DERR register field. */ +#define ALT_SYSMGR_ECC_DMA_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_DMA_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_DMA. + */ +struct ALT_SYSMGR_ECC_DMA_s +{ + uint32_t en : 1; /* DMA RAM ECC Enable */ + uint32_t injs : 1; /* DMA RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* DMA RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* DMA RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* DMA RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_DMA. */ +typedef volatile struct ALT_SYSMGR_ECC_DMA_s ALT_SYSMGR_ECC_DMA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_DMA register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_DMA_OFST 0x18 + +/* + * Register : CAN0 RAM ECC Enable Register - can0 + * + * This register is used to enable ECC on the CAN0 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | CAN0 RAM ECC Enable + * [1] | RW | 0x0 | CAN0 RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | CAN0 RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | CAN0 RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | CAN0 RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : CAN0 RAM ECC Enable - en + * + * Enable ECC for CAN0 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_EN register field. */ +#define ALT_SYSMGR_ECC_CAN0_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_EN register field. */ +#define ALT_SYSMGR_ECC_CAN0_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_EN register field. */ +#define ALT_SYSMGR_ECC_CAN0_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_EN register field value. */ +#define ALT_SYSMGR_ECC_CAN0_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_EN register field value. */ +#define ALT_SYSMGR_ECC_CAN0_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_CAN0_EN register field. */ +#define ALT_SYSMGR_ECC_CAN0_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_EN field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_CAN0_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : CAN0 RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * CAN0 RAM. This only injects one error into the CAN0 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_INJS register field value. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_INJS register field value. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_CAN0_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : CAN0 RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the CAN0 RAM. This only injects one double bit error into the CAN0 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_INJD register field value. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_INJD register field value. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_CAN0_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : CAN0 RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for CAN0 RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in CAN0 RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_SERR register field value. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_SERR register field value. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_CAN0_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : CAN0 RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for CAN0 RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * CAN0 RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_DERR register field value. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_DERR register field value. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_CAN0_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_CAN0. + */ +struct ALT_SYSMGR_ECC_CAN0_s +{ + uint32_t en : 1; /* CAN0 RAM ECC Enable */ + uint32_t injs : 1; /* CAN0 RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* CAN0 RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* CAN0 RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* CAN0 RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_CAN0. */ +typedef volatile struct ALT_SYSMGR_ECC_CAN0_s ALT_SYSMGR_ECC_CAN0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_CAN0 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_CAN0_OFST 0x1c + +/* + * Register : CAN1 RAM ECC Enable Register - can1 + * + * This register is used to enable ECC on the CAN1 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | CAN1 RAM ECC Enable + * [1] | RW | 0x0 | CAN1 RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | CAN1 RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | CAN1 RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | CAN1 RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : CAN1 RAM ECC Enable - en + * + * Enable ECC for CAN1 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_EN register field. */ +#define ALT_SYSMGR_ECC_CAN1_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_EN register field. */ +#define ALT_SYSMGR_ECC_CAN1_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_EN register field. */ +#define ALT_SYSMGR_ECC_CAN1_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_EN register field value. */ +#define ALT_SYSMGR_ECC_CAN1_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_EN register field value. */ +#define ALT_SYSMGR_ECC_CAN1_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_CAN1_EN register field. */ +#define ALT_SYSMGR_ECC_CAN1_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_EN field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_CAN1_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : CAN1 RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * CAN1 RAM. This only injects one error into the CAN1 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_INJS register field value. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_INJS register field value. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_CAN1_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : CAN1 RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the CAN1 RAM. This only injects one double bit error into the CAN1 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_INJD register field value. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_INJD register field value. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_CAN1_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : CAN1 RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for CAN1 RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in CAN1 RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_SERR register field value. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_SERR register field value. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_CAN1_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : CAN1 RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for CAN1 RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * CAN1 RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_DERR register field value. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_DERR register field value. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_CAN1_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_CAN1. + */ +struct ALT_SYSMGR_ECC_CAN1_s +{ + uint32_t en : 1; /* CAN1 RAM ECC Enable */ + uint32_t injs : 1; /* CAN1 RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* CAN1 RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* CAN1 RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* CAN1 RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_CAN1. */ +typedef volatile struct ALT_SYSMGR_ECC_CAN1_s ALT_SYSMGR_ECC_CAN1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_CAN1 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_CAN1_OFST 0x20 + +/* + * Register : NAND RAM ECC Enable Register - nand + * + * This register is used to enable ECC on the NAND RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------------------------------------- + * [0] | RW | 0x0 | NAND RAM ECC Enable + * [1] | RW | 0x0 | NAND ECCBUFFER RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | NAND ECCBUFFER RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | NAND WRFIFO RAM ECC inject single, correctable Error + * [4] | RW | 0x0 | NAND WRFIFO RAM ECC inject double bit, non-correctable error + * [5] | RW | 0x0 | NAND RDFIFO RAM ECC inject single, correctable Error + * [6] | RW | 0x0 | NAND RDFIFO RAM ECC inject double bit, non-correctable error + * [7] | RW | 0x0 | NAND ECCBUFFER RAM ECC single, correctable error interrupt status + * [8] | RW | 0x0 | NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status + * [9] | RW | 0x0 | NAND WRFIFO RAM ECC single, correctable error interrupt status + * [10] | RW | 0x0 | NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status + * [11] | RW | 0x0 | NAND RDFIFO RAM ECC single, correctable error interrupt status + * [12] | RW | 0x0 | NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NAND RAM ECC Enable - en + * + * Enable ECC for NAND RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_EN register field. */ +#define ALT_SYSMGR_ECC_NAND_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_EN register field. */ +#define ALT_SYSMGR_ECC_NAND_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_EN register field. */ +#define ALT_SYSMGR_ECC_NAND_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_EN register field value. */ +#define ALT_SYSMGR_ECC_NAND_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_EN register field value. */ +#define ALT_SYSMGR_ECC_NAND_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_NAND_EN register field. */ +#define ALT_SYSMGR_ECC_NAND_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_EN field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_NAND_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : NAND ECCBUFFER RAM ECC inject single, correctable Error - eccbufinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * NAND ECCBUFFER RAM. This only injects one error into the NAND ECCBUFFER RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJS field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : NAND ECCBUFFER RAM ECC inject double bit, non-correctable error - eccbufinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the NAND ECCBUFFER RAM. This only injects one double bit error into the NAND + * ECCBUFFER RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJD field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : NAND WRFIFO RAM ECC inject single, correctable Error - wrfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * NAND WRFIFO RAM. This only injects one error into the NAND WRFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAND WRFIFO RAM ECC inject double bit, non-correctable error - wrfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the NAND WRFIFO RAM. This only injects one double bit error into the NAND WRFIFO + * RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : NAND RDFIFO RAM ECC inject single, correctable Error - rdfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * NAND RDFIFO RAM. This only injects one error into the NAND RDFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_MSB 5 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NAND RDFIFO RAM ECC inject double bit, non-correctable error - rdfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the NAND RDFIFO RAM. This only injects one double bit error into the NAND RDFIFO + * RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_MSB 6 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : NAND ECCBUFFER RAM ECC single, correctable error interrupt status - eccbufserr + * + * This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC single, + * correctable error. It is set by hardware when single, correctable error occurs + * in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_MSB 7 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFSERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status - eccbufderr + * + * This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear + * the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_MSB 8 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFDERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : NAND WRFIFO RAM ECC single, correctable error interrupt status - wrfifoserr + * + * This bit is an interrupt status bit for NAND WRFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in NAND + * WRFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_MSB 9 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status - wrfifoderr + * + * This bit is an interrupt status bit for NAND WRFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in NAND WRFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_MSB 10 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : NAND RDFIFO RAM ECC single, correctable error interrupt status - rdfifoserr + * + * This bit is an interrupt status bit for NAND RDFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in NAND + * RDFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_MSB 11 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status - rdfifoderr + * + * This bit is an interrupt status bit for NAND RDFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in NAND RDFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_MSB 12 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_NAND. + */ +struct ALT_SYSMGR_ECC_NAND_s +{ + uint32_t en : 1; /* NAND RAM ECC Enable */ + uint32_t eccbufinjs : 1; /* NAND ECCBUFFER RAM ECC inject single, correctable Error */ + uint32_t eccbufinjd : 1; /* NAND ECCBUFFER RAM ECC inject double bit, non-correctable error */ + uint32_t wrfifoinjs : 1; /* NAND WRFIFO RAM ECC inject single, correctable Error */ + uint32_t wrfifoinjd : 1; /* NAND WRFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t rdfifoinjs : 1; /* NAND RDFIFO RAM ECC inject single, correctable Error */ + uint32_t rdfifoinjd : 1; /* NAND RDFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t eccbufserr : 1; /* NAND ECCBUFFER RAM ECC single, correctable error interrupt status */ + uint32_t eccbufderr : 1; /* NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status */ + uint32_t wrfifoserr : 1; /* NAND WRFIFO RAM ECC single, correctable error interrupt status */ + uint32_t wrfifoderr : 1; /* NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t rdfifoserr : 1; /* NAND RDFIFO RAM ECC single, correctable error interrupt status */ + uint32_t rdfifoderr : 1; /* NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_NAND. */ +typedef volatile struct ALT_SYSMGR_ECC_NAND_s ALT_SYSMGR_ECC_NAND_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_NAND register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_NAND_OFST 0x24 + +/* + * Register : QSPI RAM ECC Enable Register - qspi + * + * This register is used to enable ECC on the QSPI RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | QSPI RAM ECC Enable + * [1] | RW | 0x0 | QSPI RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | QSPI RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | QSPI RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | QSPI RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : QSPI RAM ECC Enable - en + * + * Enable ECC for QSPI RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_EN register field. */ +#define ALT_SYSMGR_ECC_QSPI_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_EN register field. */ +#define ALT_SYSMGR_ECC_QSPI_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_EN register field. */ +#define ALT_SYSMGR_ECC_QSPI_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_EN register field value. */ +#define ALT_SYSMGR_ECC_QSPI_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_EN register field value. */ +#define ALT_SYSMGR_ECC_QSPI_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_QSPI_EN register field. */ +#define ALT_SYSMGR_ECC_QSPI_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_EN field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_QSPI_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : QSPI RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * QSPI RAM. This only injects one error into the QSPI RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_INJS register field value. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_INJS register field value. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_QSPI_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : QSPI RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the QSPI RAM. This only injects one double bit error into the QSPI RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_INJD register field value. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_INJD register field value. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_QSPI_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : QSPI RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for QSPI RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in QSPI RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_SERR register field value. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_SERR register field value. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_QSPI_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : QSPI RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for QSPI RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * QSPI RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_DERR register field value. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_DERR register field value. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_QSPI_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_QSPI. + */ +struct ALT_SYSMGR_ECC_QSPI_s +{ + uint32_t en : 1; /* QSPI RAM ECC Enable */ + uint32_t injs : 1; /* QSPI RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* QSPI RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* QSPI RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* QSPI RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_QSPI. */ +typedef volatile struct ALT_SYSMGR_ECC_QSPI_s ALT_SYSMGR_ECC_QSPI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_QSPI register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_QSPI_OFST 0x28 + +/* + * Register : SDMMC RAM ECC Enable Register - sdmmc + * + * This register is used to enable ECC on the SDMMC RAM.ECC errors can be injected + * into the write path using bits in this register. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------------------------------ + * [0] | RW | 0x0 | SDMMC RAM ECC Enable + * [1] | RW | 0x0 | SDMMC Port A RAM ECC inject single, correctable Error at Port A + * [2] | RW | 0x0 | SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A + * [3] | RW | 0x0 | SDMMC Port B RAM ECC inject single, correctable Error at Port B + * [4] | RW | 0x0 | SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B + * [5] | RW | 0x0 | SDMMC Port A RAM ECC single, correctable error interrupt status + * [6] | RW | 0x0 | SDMMC Port A RAM ECC double bit, non-correctable error interrupt status + * [7] | RW | 0x0 | SDMMC Port B RAM ECC single, correctable error interrupt status + * [8] | RW | 0x0 | SDMMC Port B RAM ECC double bit, non-correctable error interrupt status + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDMMC RAM ECC Enable - en + * + * Enable ECC for SDMMC RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_EN register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_EN register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_EN field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_SDMMC_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SDMMC Port A RAM ECC inject single, correctable Error at Port A - injsporta + * + * Changing this bit from zero to one injects a single, correctable error into the + * SDMMC RAM at Port A. This only injects one error into the SDMMC RAM at Port A. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJSPORTA field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A - injdporta + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the SDMMC RAM at Port A. This only injects one double bit error into the SDMMC + * RAM at Port A. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJDPORTA field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SDMMC Port B RAM ECC inject single, correctable Error at Port B - injsportb + * + * Changing this bit from zero to one injects a single, correctable error into the + * SDMMC RAM at Port B. This only injects one error into the SDMMC RAM at Port B. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJSPORTB field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B - injdportb + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the SDMMC RAM at Port B. This only injects one double bit error into the SDMMC + * RAM at Port B. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJDPORTB field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : SDMMC Port A RAM ECC single, correctable error interrupt status - serrporta + * + * This bit is an interrupt status bit for SDMMC Port A RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in SDMMC Port + * A RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_MSB 5 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_SERRPORTA field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : SDMMC Port A RAM ECC double bit, non-correctable error interrupt status - derrporta + * + * This bit is an interrupt status bit for SDMMC Port A RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in SDMMC Port A RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_MSB 6 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_DERRPORTA field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : SDMMC Port B RAM ECC single, correctable error interrupt status - serrportb + * + * This bit is an interrupt status bit for SDMMC Port B RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in SDMMC Port + * B RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_MSB 7 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_SERRPORTB field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : SDMMC Port B RAM ECC double bit, non-correctable error interrupt status - derrportb + * + * This bit is an interrupt status bit for SDMMC Port B RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in SDMMC Port B RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_MSB 8 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_DERRPORTB field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_SDMMC. + */ +struct ALT_SYSMGR_ECC_SDMMC_s +{ + uint32_t en : 1; /* SDMMC RAM ECC Enable */ + uint32_t injsporta : 1; /* SDMMC Port A RAM ECC inject single, correctable Error at Port A */ + uint32_t injdporta : 1; /* SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A */ + uint32_t injsportb : 1; /* SDMMC Port B RAM ECC inject single, correctable Error at Port B */ + uint32_t injdportb : 1; /* SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B */ + uint32_t serrporta : 1; /* SDMMC Port A RAM ECC single, correctable error interrupt status */ + uint32_t derrporta : 1; /* SDMMC Port A RAM ECC double bit, non-correctable error interrupt status */ + uint32_t serrportb : 1; /* SDMMC Port B RAM ECC single, correctable error interrupt status */ + uint32_t derrportb : 1; /* SDMMC Port B RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_SDMMC. */ +typedef volatile struct ALT_SYSMGR_ECC_SDMMC_s ALT_SYSMGR_ECC_SDMMC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_SDMMC register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_SDMMC_OFST 0x2c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ECC. + */ +struct ALT_SYSMGR_ECC_s +{ + volatile ALT_SYSMGR_ECC_L2_t l2; /* ALT_SYSMGR_ECC_L2 */ + volatile ALT_SYSMGR_ECC_OCRAM_t ocram; /* ALT_SYSMGR_ECC_OCRAM */ + volatile ALT_SYSMGR_ECC_USB0_t usb0; /* ALT_SYSMGR_ECC_USB0 */ + volatile ALT_SYSMGR_ECC_USB1_t usb1; /* ALT_SYSMGR_ECC_USB1 */ + volatile ALT_SYSMGR_ECC_EMAC0_t emac0; /* ALT_SYSMGR_ECC_EMAC0 */ + volatile ALT_SYSMGR_ECC_EMAC1_t emac1; /* ALT_SYSMGR_ECC_EMAC1 */ + volatile ALT_SYSMGR_ECC_DMA_t dma; /* ALT_SYSMGR_ECC_DMA */ + volatile ALT_SYSMGR_ECC_CAN0_t can0; /* ALT_SYSMGR_ECC_CAN0 */ + volatile ALT_SYSMGR_ECC_CAN1_t can1; /* ALT_SYSMGR_ECC_CAN1 */ + volatile ALT_SYSMGR_ECC_NAND_t nand; /* ALT_SYSMGR_ECC_NAND */ + volatile ALT_SYSMGR_ECC_QSPI_t qspi; /* ALT_SYSMGR_ECC_QSPI */ + volatile ALT_SYSMGR_ECC_SDMMC_t sdmmc; /* ALT_SYSMGR_ECC_SDMMC */ + volatile uint32_t _pad_0x30_0x40[4]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ECC. */ +typedef volatile struct ALT_SYSMGR_ECC_s ALT_SYSMGR_ECC_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ECC. */ +struct ALT_SYSMGR_ECC_raw_s +{ + volatile uint32_t l2; /* ALT_SYSMGR_ECC_L2 */ + volatile uint32_t ocram; /* ALT_SYSMGR_ECC_OCRAM */ + volatile uint32_t usb0; /* ALT_SYSMGR_ECC_USB0 */ + volatile uint32_t usb1; /* ALT_SYSMGR_ECC_USB1 */ + volatile uint32_t emac0; /* ALT_SYSMGR_ECC_EMAC0 */ + volatile uint32_t emac1; /* ALT_SYSMGR_ECC_EMAC1 */ + volatile uint32_t dma; /* ALT_SYSMGR_ECC_DMA */ + volatile uint32_t can0; /* ALT_SYSMGR_ECC_CAN0 */ + volatile uint32_t can1; /* ALT_SYSMGR_ECC_CAN1 */ + volatile uint32_t nand; /* ALT_SYSMGR_ECC_NAND */ + volatile uint32_t qspi; /* ALT_SYSMGR_ECC_QSPI */ + volatile uint32_t sdmmc; /* ALT_SYSMGR_ECC_SDMMC */ + volatile uint32_t _pad_0x30_0x40[4]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ECC. */ +typedef volatile struct ALT_SYSMGR_ECC_raw_s ALT_SYSMGR_ECC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Pin Mux Control Group - ALT_SYSMGR_PINMUX + * Pin Mux Control Group + * + * Controls Pin Mux selections + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + */ +/* + * Register : emac0_tx_clk Mux Selection Register - EMACIO0 + * + * This register is used to control the peripherals connected to emac0_tx_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_clk Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 0. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TX_CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO0. + */ +struct ALT_SYSMGR_PINMUX_EMACIO0_s +{ + uint32_t sel : 2; /* emac0_tx_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO0_s ALT_SYSMGR_PINMUX_EMACIO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_OFST 0x0 + +/* + * Register : emac0_tx_d0 Mux Selection Register - EMACIO1 + * + * This register is used to control the peripherals connected to emac0_tx_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_d0 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 1. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D0. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TXD0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO1. + */ +struct ALT_SYSMGR_PINMUX_EMACIO1_s +{ + uint32_t sel : 2; /* emac0_tx_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO1_s ALT_SYSMGR_PINMUX_EMACIO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_OFST 0x4 + +/* + * Register : emac0_tx_d1 Mux Selection Register - EMACIO2 + * + * This register is used to control the peripherals connected to emac0_tx_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_d1 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 2. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D1. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TXD1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO2. + */ +struct ALT_SYSMGR_PINMUX_EMACIO2_s +{ + uint32_t sel : 2; /* emac0_tx_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO2_s ALT_SYSMGR_PINMUX_EMACIO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_OFST 0x8 + +/* + * Register : emac0_tx_d2 Mux Selection Register - EMACIO3 + * + * This register is used to control the peripherals connected to emac0_tx_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_d2 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 3. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D2. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TXD2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO3. + */ +struct ALT_SYSMGR_PINMUX_EMACIO3_s +{ + uint32_t sel : 2; /* emac0_tx_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO3_s ALT_SYSMGR_PINMUX_EMACIO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_OFST 0xc + +/* + * Register : emac0_tx_d3 Mux Selection Register - EMACIO4 + * + * This register is used to control the peripherals connected to emac0_tx_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_d3 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 4. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D3. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TXD3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO4. + */ +struct ALT_SYSMGR_PINMUX_EMACIO4_s +{ + uint32_t sel : 2; /* emac0_tx_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO4_s ALT_SYSMGR_PINMUX_EMACIO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_OFST 0x10 + +/* + * Register : emac0_rx_d0 Mux Selection Register - EMACIO5 + * + * This register is used to control the peripherals connected to emac0_rx_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_d0 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 5. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D4. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RXD0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO5. + */ +struct ALT_SYSMGR_PINMUX_EMACIO5_s +{ + uint32_t sel : 2; /* emac0_rx_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO5_s ALT_SYSMGR_PINMUX_EMACIO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_OFST 0x14 + +/* + * Register : emac0_mdio Mux Selection Register - EMACIO6 + * + * This register is used to control the peripherals connected to emac0_mdio + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | emac0_mdio Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_mdio Mux Selection Field - sel + * + * Select peripheral signals connected emac0_mdio. + * + * 0 : Pin is connected to GPIO/LoanIO number 6. + * + * 1 : Pin is connected to Peripheral signal I2C2.SDA. + * + * 2 : Pin is connected to Peripheral signal USB1.D5. + * + * 3 : Pin is connected to Peripheral signal RGMII0.MDIO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO6. + */ +struct ALT_SYSMGR_PINMUX_EMACIO6_s +{ + uint32_t sel : 2; /* emac0_mdio Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO6_s ALT_SYSMGR_PINMUX_EMACIO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_OFST 0x18 + +/* + * Register : emac0_mdc Mux Selection Register - EMACIO7 + * + * This register is used to control the peripherals connected to emac0_mdc + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | emac0_mdc Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_mdc Mux Selection Field - sel + * + * Select peripheral signals connected emac0_mdc. + * + * 0 : Pin is connected to GPIO/LoanIO number 7. + * + * 1 : Pin is connected to Peripheral signal I2C2.SCL. + * + * 2 : Pin is connected to Peripheral signal USB1.D6. + * + * 3 : Pin is connected to Peripheral signal RGMII0.MDC. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO7. + */ +struct ALT_SYSMGR_PINMUX_EMACIO7_s +{ + uint32_t sel : 2; /* emac0_mdc Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO7_s ALT_SYSMGR_PINMUX_EMACIO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_OFST 0x1c + +/* + * Register : emac0_rx_ctl Mux Selection Register - EMACIO8 + * + * This register is used to control the peripherals connected to emac0_rx_ctl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_ctl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_ctl Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_ctl. + * + * 0 : Pin is connected to GPIO/LoanIO number 8. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D7. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RX_CTL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO8. + */ +struct ALT_SYSMGR_PINMUX_EMACIO8_s +{ + uint32_t sel : 2; /* emac0_rx_ctl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO8_s ALT_SYSMGR_PINMUX_EMACIO8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_OFST 0x20 + +/* + * Register : emac0_tx_ctl Mux Selection Register - EMACIO9 + * + * This register is used to control the peripherals connected to emac0_tx_ctl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_ctl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_ctl Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_ctl. + * + * 0 : Pin is connected to GPIO/LoanIO number 9. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TX_CTL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO9. + */ +struct ALT_SYSMGR_PINMUX_EMACIO9_s +{ + uint32_t sel : 2; /* emac0_tx_ctl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO9_s ALT_SYSMGR_PINMUX_EMACIO9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_OFST 0x24 + +/* + * Register : emac0_rx_clk Mux Selection Register - EMACIO10 + * + * This register is used to control the peripherals connected to emac0_rx_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_clk Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 10. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.CLK. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RX_CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO10. + */ +struct ALT_SYSMGR_PINMUX_EMACIO10_s +{ + uint32_t sel : 2; /* emac0_rx_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO10_s ALT_SYSMGR_PINMUX_EMACIO10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_OFST 0x28 + +/* + * Register : emac0_rx_d1 Mux Selection Register - EMACIO11 + * + * This register is used to control the peripherals connected to emac0_rx_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_d1 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 11. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.STP. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RXD1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO11. + */ +struct ALT_SYSMGR_PINMUX_EMACIO11_s +{ + uint32_t sel : 2; /* emac0_rx_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO11_s ALT_SYSMGR_PINMUX_EMACIO11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_OFST 0x2c + +/* + * Register : emac0_rx_d2 Mux Selection Register - EMACIO12 + * + * This register is used to control the peripherals connected to emac0_rx_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_d2 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 12. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.DIR. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RXD2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO12_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO12. + */ +struct ALT_SYSMGR_PINMUX_EMACIO12_s +{ + uint32_t sel : 2; /* emac0_rx_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO12. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO12_s ALT_SYSMGR_PINMUX_EMACIO12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO12 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_OFST 0x30 + +/* + * Register : emac0_rx_d3 Mux Selection Register - EMACIO13 + * + * This register is used to control the peripherals connected to emac0_rx_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_d3 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 13. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.NXT. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RXD3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO13_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO13. + */ +struct ALT_SYSMGR_PINMUX_EMACIO13_s +{ + uint32_t sel : 2; /* emac0_rx_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO13. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO13_s ALT_SYSMGR_PINMUX_EMACIO13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO13 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_OFST 0x34 + +/* + * Register : emac1_tx_clk Mux Selection Register - EMACIO14 + * + * This register is used to control the peripherals connected to emac1_tx_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_clk Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 48. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TX_CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO14_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO14. + */ +struct ALT_SYSMGR_PINMUX_EMACIO14_s +{ + uint32_t sel : 2; /* emac1_tx_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO14. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO14_s ALT_SYSMGR_PINMUX_EMACIO14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO14 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_OFST 0x38 + +/* + * Register : emac1_tx_d0 Mux Selection Register - EMACIO15 + * + * This register is used to control the peripherals connected to emac1_tx_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_d0 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 49. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TXD0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO15_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO15. + */ +struct ALT_SYSMGR_PINMUX_EMACIO15_s +{ + uint32_t sel : 2; /* emac1_tx_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO15. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO15_s ALT_SYSMGR_PINMUX_EMACIO15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO15 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_OFST 0x3c + +/* + * Register : emac1_tx_d1 Mux Selection Register - EMACIO16 + * + * This register is used to control the peripherals connected to emac1_tx_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_d1 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 50. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TXD1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO16_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO16. + */ +struct ALT_SYSMGR_PINMUX_EMACIO16_s +{ + uint32_t sel : 2; /* emac1_tx_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO16. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO16_s ALT_SYSMGR_PINMUX_EMACIO16_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO16 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_OFST 0x40 + +/* + * Register : emac1_tx_ctl Mux Selection Register - EMACIO17 + * + * This register is used to control the peripherals connected to emac1_tx_ctl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_ctl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_ctl Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_ctl. + * + * 0 : Pin is connected to GPIO/LoanIO number 51. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TX_CTL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO17_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO17. + */ +struct ALT_SYSMGR_PINMUX_EMACIO17_s +{ + uint32_t sel : 2; /* emac1_tx_ctl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO17. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO17_s ALT_SYSMGR_PINMUX_EMACIO17_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO17 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_OFST 0x44 + +/* + * Register : emac1_rx_d0 Mux Selection Register - EMACIO18 + * + * This register is used to control the peripherals connected to emac1_rx_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_d0 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 52. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RXD0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO18_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO18. + */ +struct ALT_SYSMGR_PINMUX_EMACIO18_s +{ + uint32_t sel : 2; /* emac1_rx_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO18. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO18_s ALT_SYSMGR_PINMUX_EMACIO18_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO18 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_OFST 0x48 + +/* + * Register : emac1_rx_d1 Mux Selection Register - EMACIO19 + * + * This register is used to control the peripherals connected to emac1_rx_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_d1 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 53. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RXD1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO19_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO19. + */ +struct ALT_SYSMGR_PINMUX_EMACIO19_s +{ + uint32_t sel : 2; /* emac1_rx_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO19. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO19_s ALT_SYSMGR_PINMUX_EMACIO19_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO19 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_OFST 0x4c + +/* + * Register : sdmmc_cmd Mux Selection Register - FLASHIO0 + * + * This register is used to control the peripherals connected to sdmmc_cmd + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | sdmmc_cmd Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_cmd Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_cmd. + * + * 0 : Pin is connected to GPIO/LoanIO number 36. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D0. + * + * 3 : Pin is connected to Peripheral signal SDMMC.CMD. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO0. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO0_s +{ + uint32_t sel : 2; /* sdmmc_cmd Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO0_s ALT_SYSMGR_PINMUX_FLSHIO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_OFST 0x50 + +/* + * Register : sdmmc_pwren Mux Selection Register - FLASHIO1 + * + * This register is used to control the peripherals connected to sdmmc_pwren + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | sdmmc_pwren Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_pwren Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_pwren. + * + * 0 : Pin is connected to GPIO/LoanIO number 37. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D1. + * + * 3 : Pin is connected to Peripheral signal SDMMC.PWREN. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO1. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO1_s +{ + uint32_t sel : 2; /* sdmmc_pwren Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO1_s ALT_SYSMGR_PINMUX_FLSHIO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_OFST 0x54 + +/* + * Register : sdmmc_d0 Mux Selection Register - FLASHIO2 + * + * This register is used to control the peripherals connected to sdmmc_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d0 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 38. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D2. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO2. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO2_s +{ + uint32_t sel : 2; /* sdmmc_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO2_s ALT_SYSMGR_PINMUX_FLSHIO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_OFST 0x58 + +/* + * Register : sdmmc_d1 Mux Selection Register - FLASHIO3 + * + * This register is used to control the peripherals connected to sdmmc_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d1 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 39. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D3. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO3. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO3_s +{ + uint32_t sel : 2; /* sdmmc_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO3_s ALT_SYSMGR_PINMUX_FLSHIO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_OFST 0x5c + +/* + * Register : sdmmc_d4 Mux Selection Register - FLASHIO4 + * + * This register is used to control the peripherals connected to sdmmc_d4 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d4 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d4 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d4. + * + * 0 : Pin is connected to GPIO/LoanIO number 40. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D4. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO4. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO4_s +{ + uint32_t sel : 2; /* sdmmc_d4 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO4_s ALT_SYSMGR_PINMUX_FLSHIO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_OFST 0x60 + +/* + * Register : sdmmc_d5 Mux Selection Register - FLASHIO5 + * + * This register is used to control the peripherals connected to sdmmc_d5 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d5 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d5 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d5. + * + * 0 : Pin is connected to GPIO/LoanIO number 41. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D5. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO5. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO5_s +{ + uint32_t sel : 2; /* sdmmc_d5 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO5_s ALT_SYSMGR_PINMUX_FLSHIO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_OFST 0x64 + +/* + * Register : sdmmc_d6 Mux Selection Register - FLASHIO6 + * + * This register is used to control the peripherals connected to sdmmc_d6 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d6 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d6 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d6. + * + * 0 : Pin is connected to GPIO/LoanIO number 42. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D6. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO6. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO6_s +{ + uint32_t sel : 2; /* sdmmc_d6 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO6_s ALT_SYSMGR_PINMUX_FLSHIO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_OFST 0x68 + +/* + * Register : sdmmc_d7 Mux Selection Register - FLASHIO7 + * + * This register is used to control the peripherals connected to sdmmc_d7 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d7 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d7 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d7. + * + * 0 : Pin is connected to GPIO/LoanIO number 43. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D7. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO7. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO7_s +{ + uint32_t sel : 2; /* sdmmc_d7 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO7_s ALT_SYSMGR_PINMUX_FLSHIO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_OFST 0x6c + +/* + * Register : sdmmc_clk_in Mux Selection Register - FLASHIO8 + * + * This register is used to control the peripherals connected to sdmmc_clk_in + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | sdmmc_clk_in Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_clk_in Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_clk_in. + * + * 0 : Pin is connected to GPIO/LoanIO number 44. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.CLK. + * + * 3 : Pin is connected to Peripheral signal SDMMC.CLK_IN. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO8. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO8_s +{ + uint32_t sel : 2; /* sdmmc_clk_in Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO8_s ALT_SYSMGR_PINMUX_FLSHIO8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_OFST 0x70 + +/* + * Register : sdmmc_clk Mux Selection Register - FLASHIO9 + * + * This register is used to control the peripherals connected to sdmmc_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | sdmmc_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_clk Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 45. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.STP. + * + * 3 : Pin is connected to Peripheral signal SDMMC.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO9. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO9_s +{ + uint32_t sel : 2; /* sdmmc_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO9_s ALT_SYSMGR_PINMUX_FLSHIO9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_OFST 0x74 + +/* + * Register : sdmmc_d2 Mux Selection Register - FLASHIO10 + * + * This register is used to control the peripherals connected to sdmmc_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d2 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 46. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.DIR. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO10. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO10_s +{ + uint32_t sel : 2; /* sdmmc_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO10_s ALT_SYSMGR_PINMUX_FLSHIO10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_OFST 0x78 + +/* + * Register : sdmmc_d3 Mux Selection Register - FLASHIO11 + * + * This register is used to control the peripherals connected to sdmmc_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d3 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 47. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.NXT. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO11. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO11_s +{ + uint32_t sel : 2; /* sdmmc_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO11_s ALT_SYSMGR_PINMUX_FLSHIO11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_OFST 0x7c + +/* + * Register : trace_clk Mux Selection Register - GENERALIO0 + * + * This register is used to control the peripherals connected to trace_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | trace_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_clk Mux Selection Field - sel + * + * Select peripheral signals connected trace_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 48. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal TRACE.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO0. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO0_s +{ + uint32_t sel : 2; /* trace_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO0_s ALT_SYSMGR_PINMUX_GENERALIO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_OFST 0x80 + +/* + * Register : trace_d0 Mux Selection Register - GENERALIO1 + * + * This register is used to control the peripherals connected to trace_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d0 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 49. + * + * 1 : Pin is connected to Peripheral signal UART0.RX. + * + * 2 : Pin is connected to Peripheral signal SPIS0.CLK. + * + * 3 : Pin is connected to Peripheral signal TRACE.D0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO1. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO1_s +{ + uint32_t sel : 2; /* trace_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO1_s ALT_SYSMGR_PINMUX_GENERALIO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_OFST 0x84 + +/* + * Register : trace_d1 Mux Selection Register - GENERALIO2 + * + * This register is used to control the peripherals connected to trace_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d1 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 50. + * + * 1 : Pin is connected to Peripheral signal UART0.TX. + * + * 2 : Pin is connected to Peripheral signal SPIS0.MOSI. + * + * 3 : Pin is connected to Peripheral signal TRACE.D1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO2. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO2_s +{ + uint32_t sel : 2; /* trace_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO2_s ALT_SYSMGR_PINMUX_GENERALIO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_OFST 0x88 + +/* + * Register : trace_d2 Mux Selection Register - GENERALIO3 + * + * This register is used to control the peripherals connected to trace_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d2 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 51. + * + * 1 : Pin is connected to Peripheral signal I2C1.SDA. + * + * 2 : Pin is connected to Peripheral signal SPIS0.MISO. + * + * 3 : Pin is connected to Peripheral signal TRACE.D2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO3. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO3_s +{ + uint32_t sel : 2; /* trace_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO3_s ALT_SYSMGR_PINMUX_GENERALIO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_OFST 0x8c + +/* + * Register : trace_d3 Mux Selection Register - GENERALIO4 + * + * This register is used to control the peripherals connected to trace_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d3 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 52. + * + * 1 : Pin is connected to Peripheral signal I2C1.SCL. + * + * 2 : Pin is connected to Peripheral signal SPIS0.SS0. + * + * 3 : Pin is connected to Peripheral signal TRACE.D3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO4. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO4_s +{ + uint32_t sel : 2; /* trace_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO4_s ALT_SYSMGR_PINMUX_GENERALIO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_OFST 0x90 + +/* + * Register : trace_d4 Mux Selection Register - GENERALIO5 + * + * This register is used to control the peripherals connected to trace_d4 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d4 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d4 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d4. + * + * 0 : Pin is connected to GPIO/LoanIO number 53. + * + * 1 : Pin is connected to Peripheral signal CAN1.RX. + * + * 2 : Pin is connected to Peripheral signal SPIS1.CLK. + * + * 3 : Pin is connected to Peripheral signal TRACE.D4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO5. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO5_s +{ + uint32_t sel : 2; /* trace_d4 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO5_s ALT_SYSMGR_PINMUX_GENERALIO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_OFST 0x94 + +/* + * Register : trace_d5 Mux Selection Register - GENERALIO6 + * + * This register is used to control the peripherals connected to trace_d5 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d5 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d5 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d5. + * + * 0 : Pin is connected to GPIO/LoanIO number 54. + * + * 1 : Pin is connected to Peripheral signal CAN1.TX. + * + * 2 : Pin is connected to Peripheral signal SPIS1.MOSI. + * + * 3 : Pin is connected to Peripheral signal TRACE.D5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO6. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO6_s +{ + uint32_t sel : 2; /* trace_d5 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO6_s ALT_SYSMGR_PINMUX_GENERALIO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_OFST 0x98 + +/* + * Register : trace_d6 Mux Selection Register - GENERALIO7 + * + * This register is used to control the peripherals connected to trace_d6 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d6 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d6 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d6. + * + * 0 : Pin is connected to GPIO/LoanIO number 55. + * + * 1 : Pin is connected to Peripheral signal I2C0.SDA. + * + * 2 : Pin is connected to Peripheral signal SPIS1.SS0. + * + * 3 : Pin is connected to Peripheral signal TRACE.D6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO7. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO7_s +{ + uint32_t sel : 2; /* trace_d6 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO7_s ALT_SYSMGR_PINMUX_GENERALIO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_OFST 0x9c + +/* + * Register : trace_d7 Mux Selection Register - GENERALIO8 + * + * This register is used to control the peripherals connected to trace_d7 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d7 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d7 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d7. + * + * 0 : Pin is connected to GPIO/LoanIO number 56. + * + * 1 : Pin is connected to Peripheral signal I2C0.SCL. + * + * 2 : Pin is connected to Peripheral signal SPIS1.MISO. + * + * 3 : Pin is connected to Peripheral signal TRACE.D7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO8. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO8_s +{ + uint32_t sel : 2; /* trace_d7 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO8_s ALT_SYSMGR_PINMUX_GENERALIO8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_OFST 0xa0 + +/* + * Register : spim0_clk Mux Selection Register - GENERALIO9 + * + * This register is used to control the peripherals connected to spim0_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spim0_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_clk Mux Selection Field - sel + * + * Select peripheral signals connected spim0_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 57. + * + * 1 : Pin is connected to Peripheral signal UART0.CTS. + * + * 2 : Pin is connected to Peripheral signal I2C1.SDA. + * + * 3 : Pin is connected to Peripheral signal SPIM0.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO9. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO9_s +{ + uint32_t sel : 2; /* spim0_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO9_s ALT_SYSMGR_PINMUX_GENERALIO9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_OFST 0xa4 + +/* + * Register : spim0_mosi Mux Selection Register - GENERALIO10 + * + * This register is used to control the peripherals connected to spim0_mosi + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spim0_mosi Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_mosi Mux Selection Field - sel + * + * Select peripheral signals connected spim0_mosi. + * + * 0 : Pin is connected to GPIO/LoanIO number 58. + * + * 1 : Pin is connected to Peripheral signal UART0.RTS. + * + * 2 : Pin is connected to Peripheral signal I2C1.SCL. + * + * 3 : Pin is connected to Peripheral signal SPIM0.MOSI. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO10. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO10_s +{ + uint32_t sel : 2; /* spim0_mosi Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO10_s ALT_SYSMGR_PINMUX_GENERALIO10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_OFST 0xa8 + +/* + * Register : spim0_miso Mux Selection Register - GENERALIO11 + * + * This register is used to control the peripherals connected to spim0_miso + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spim0_miso Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_miso Mux Selection Field - sel + * + * Select peripheral signals connected spim0_miso. + * + * 0 : Pin is connected to GPIO/LoanIO number 59. + * + * 1 : Pin is connected to Peripheral signal UART1.CTS. + * + * 2 : Pin is connected to Peripheral signal CAN1.RX. + * + * 3 : Pin is connected to Peripheral signal SPIM0.MISO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO11. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO11_s +{ + uint32_t sel : 2; /* spim0_miso Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO11_s ALT_SYSMGR_PINMUX_GENERALIO11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_OFST 0xac + +/* + * Register : spim0_ss0 Mux Selection Register - GENERALIO12 + * + * This register is used to control the peripherals connected to spim0_ss0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spim0_ss0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_ss0 Mux Selection Field - sel + * + * Select peripheral signals connected spim0_ss0. + * + * 0 : Pin is connected to GPIO/LoanIO number 60. + * + * 1 : Pin is connected to Peripheral signal UART1.RTS. + * + * 2 : Pin is connected to Peripheral signal CAN1.TX. + * + * 3 : Pin is connected to Peripheral signal SPIM0.SS0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO12_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO12. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO12_s +{ + uint32_t sel : 2; /* spim0_ss0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO12. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO12_s ALT_SYSMGR_PINMUX_GENERALIO12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO12 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_OFST 0xb0 + +/* + * Register : uart0_rx Mux Selection Register - GENERALIO13 + * + * This register is used to control the peripherals connected to uart0_rx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | uart0_rx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : uart0_rx Mux Selection Field - sel + * + * Select peripheral signals connected uart0_rx. + * + * 0 : Pin is connected to GPIO/LoanIO number 61. + * + * 1 : Pin is connected to Peripheral signal SPIM0.SS1. + * + * 2 : Pin is connected to Peripheral signal CAN0.RX. + * + * 3 : Pin is connected to Peripheral signal UART0.RX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO13_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO13. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO13_s +{ + uint32_t sel : 2; /* uart0_rx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO13. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO13_s ALT_SYSMGR_PINMUX_GENERALIO13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO13 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_OFST 0xb4 + +/* + * Register : uart0_tx Mux Selection Register - GENERALIO14 + * + * This register is used to control the peripherals connected to uart0_tx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | uart0_tx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : uart0_tx Mux Selection Field - sel + * + * Select peripheral signals connected uart0_tx. + * + * 0 : Pin is connected to GPIO/LoanIO number 62. + * + * 1 : Pin is connected to Peripheral signal SPIM1.SS1. + * + * 2 : Pin is connected to Peripheral signal CAN0.TX. + * + * 3 : Pin is connected to Peripheral signal UART0.TX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO14_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO14. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO14_s +{ + uint32_t sel : 2; /* uart0_tx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO14. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO14_s ALT_SYSMGR_PINMUX_GENERALIO14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO14 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_OFST 0xb8 + +/* + * Register : i2c0_sda Mux Selection Register - GENERALIO15 + * + * This register is used to control the peripherals connected to i2c0_sda + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | i2c0_sda Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : i2c0_sda Mux Selection Field - sel + * + * Select peripheral signals connected i2c0_sda. + * + * 0 : Pin is connected to GPIO/LoanIO number 63. + * + * 1 : Pin is connected to Peripheral signal SPIM1.CLK. + * + * 2 : Pin is connected to Peripheral signal UART1.RX. + * + * 3 : Pin is connected to Peripheral signal I2C0.SDA. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO15_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO15. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO15_s +{ + uint32_t sel : 2; /* i2c0_sda Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO15. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO15_s ALT_SYSMGR_PINMUX_GENERALIO15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO15 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_OFST 0xbc + +/* + * Register : i2c0_scl Mux Selection Register - GENERALIO16 + * + * This register is used to control the peripherals connected to i2c0_scl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | i2c0_scl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : i2c0_scl Mux Selection Field - sel + * + * Select peripheral signals connected i2c0_scl. + * + * 0 : Pin is connected to GPIO/LoanIO number 64. + * + * 1 : Pin is connected to Peripheral signal SPIM1.MOSI. + * + * 2 : Pin is connected to Peripheral signal UART1.TX. + * + * 3 : Pin is connected to Peripheral signal I2C0.SCL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO16_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO16. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO16_s +{ + uint32_t sel : 2; /* i2c0_scl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO16. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO16_s ALT_SYSMGR_PINMUX_GENERALIO16_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO16 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_OFST 0xc0 + +/* + * Register : can0_rx Mux Selection Register - GENERALIO17 + * + * This register is used to control the peripherals connected to can0_rx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | can0_rx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : can0_rx Mux Selection Field - sel + * + * Select peripheral signals connected can0_rx. + * + * 0 : Pin is connected to GPIO/LoanIO number 65. + * + * 1 : Pin is connected to Peripheral signal SPIM1.MISO. + * + * 2 : Pin is connected to Peripheral signal UART0.RX. + * + * 3 : Pin is connected to Peripheral signal CAN0.RX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO17_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO17. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO17_s +{ + uint32_t sel : 2; /* can0_rx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO17. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO17_s ALT_SYSMGR_PINMUX_GENERALIO17_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO17 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_OFST 0xc4 + +/* + * Register : can0_tx Mux Selection Register - GENERALIO18 + * + * This register is used to control the peripherals connected to can0_tx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | can0_tx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : can0_tx Mux Selection Field - sel + * + * Select peripheral signals connected can0_tx. + * + * 0 : Pin is connected to GPIO/LoanIO number 66. + * + * 1 : Pin is connected to Peripheral signal SPIM1.SS0. + * + * 2 : Pin is connected to Peripheral signal UART0.TX. + * + * 3 : Pin is connected to Peripheral signal CAN0.TX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO18_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO18. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO18_s +{ + uint32_t sel : 2; /* can0_tx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO18. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO18_s ALT_SYSMGR_PINMUX_GENERALIO18_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO18 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_OFST 0xc8 + +/* + * Register : spis1_clk Mux Selection Register - GENERALIO19 + * + * This register is used to control the peripherals connected to spis1_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spis1_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis1_clk Mux Selection Field - sel + * + * Select peripheral signals connected spis1_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 67. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.CLK. + * + * 3 : Pin is connected to Peripheral signal SPIS1.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO19_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO19. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO19_s +{ + uint32_t sel : 2; /* spis1_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO19. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO19_s ALT_SYSMGR_PINMUX_GENERALIO19_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO19 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_OFST 0xcc + +/* + * Register : spis1_mosi Mux Selection Register - GENERALIO20 + * + * This register is used to control the peripherals connected to spis1_mosi + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spis1_mosi Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis1_mosi Mux Selection Field - sel + * + * Select peripheral signals connected spis1_mosi. + * + * 0 : Pin is connected to GPIO/LoanIO number 68. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.MOSI. + * + * 3 : Pin is connected to Peripheral signal SPIS1.MOSI. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO20_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO20. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO20_s +{ + uint32_t sel : 2; /* spis1_mosi Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO20. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO20_s ALT_SYSMGR_PINMUX_GENERALIO20_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO20 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_OFST 0xd0 + +/* + * Register : spis1_miso Mux Selection Register - GENERALIO21 + * + * This register is used to control the peripherals connected to spis1_miso + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spis1_miso Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis1_miso Mux Selection Field - sel + * + * Select peripheral signals connected spis1_miso. + * + * 0 : Pin is connected to GPIO/LoanIO number 69. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.MISO. + * + * 3 : Pin is connected to Peripheral signal SPIS1.MISO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO21_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO21. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO21_s +{ + uint32_t sel : 2; /* spis1_miso Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO21. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO21_s ALT_SYSMGR_PINMUX_GENERALIO21_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO21 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_OFST 0xd4 + +/* + * Register : spis1_ss0 Mux Selection Register - GENERALIO22 + * + * This register is used to control the peripherals connected to spis1_ss0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spis1_ss0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis1_ss0 Mux Selection Field - sel + * + * Select peripheral signals connected spis1_ss0. + * + * 0 : Pin is connected to GPIO/LoanIO number 70. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.SS0. + * + * 3 : Pin is connected to Peripheral signal SPIS1.SS0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO22_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO22. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO22_s +{ + uint32_t sel : 2; /* spis1_ss0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO22. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO22_s ALT_SYSMGR_PINMUX_GENERALIO22_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO22 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_OFST 0xd8 + +/* + * Register : uart1_rx Mux Selection Register - GENERALIO23 + * + * This register is used to control the peripherals connected to uart1_rx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | uart1_rx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : uart1_rx Mux Selection Field - sel + * + * Select peripheral signals connected uart1_rx. + * + * 0 : Pin is connected to GPIO/LoanIO number 62. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.SS1. + * + * 3 : Pin is connected to Peripheral signal UART1.RX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO23_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO23. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO23_s +{ + uint32_t sel : 2; /* uart1_rx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO23. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO23_s ALT_SYSMGR_PINMUX_GENERALIO23_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO23 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_OFST 0xdc + +/* + * Register : uart1_tx Mux Selection Register - GENERALIO24 + * + * This register is used to control the peripherals connected to uart1_tx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | uart1_tx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : uart1_tx Mux Selection Field - sel + * + * Select peripheral signals connected uart1_tx. + * + * 0 : Pin is connected to GPIO/LoanIO number 63. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.CLK. + * + * 3 : Pin is connected to Peripheral signal UART1.TX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO24_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO24. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO24_s +{ + uint32_t sel : 2; /* uart1_tx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO24. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO24_s ALT_SYSMGR_PINMUX_GENERALIO24_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO24 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_OFST 0xe0 + +/* + * Register : i2c1_sda Mux Selection Register - GENERALIO25 + * + * This register is used to control the peripherals connected to i2c1_sda + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | i2c1_sda Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : i2c1_sda Mux Selection Field - sel + * + * Select peripheral signals connected i2c1_sda. + * + * 0 : Pin is connected to GPIO/LoanIO number 64. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.MOSI. + * + * 3 : Pin is connected to Peripheral signal I2C1.SDA. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO25_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO25. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO25_s +{ + uint32_t sel : 2; /* i2c1_sda Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO25. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO25_s ALT_SYSMGR_PINMUX_GENERALIO25_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO25 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_OFST 0xe4 + +/* + * Register : i2c1_scl Mux Selection Register - GENERALIO26 + * + * This register is used to control the peripherals connected to i2c1_scl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | i2c1_scl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : i2c1_scl Mux Selection Field - sel + * + * Select peripheral signals connected i2c1_scl. + * + * 0 : Pin is connected to GPIO/LoanIO number 65. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.MISO. + * + * 3 : Pin is connected to Peripheral signal I2C1.SCL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO26_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO26. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO26_s +{ + uint32_t sel : 2; /* i2c1_scl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO26. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO26_s ALT_SYSMGR_PINMUX_GENERALIO26_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO26 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_OFST 0xe8 + +/* + * Register : spim0_ss0_alt Mux Selection Register - GENERALIO27 + * + * This register is used to control the peripherals connected to spim0_ss0_alt + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [1:0] | RW | 0x0 | spim0_ss0_alt Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_ss0_alt Mux Selection Field - sel + * + * Select peripheral signals connected spim0_ss0_alt. + * + * 0 : Pin is connected to GPIO/LoanIO number 66. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.SS0. + * + * 3 : Pin is connected to Peripheral signal not applicable. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO27_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO27. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO27_s +{ + uint32_t sel : 2; /* spim0_ss0_alt Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO27. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO27_s ALT_SYSMGR_PINMUX_GENERALIO27_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO27 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_OFST 0xec + +/* + * Register : spis0_clk Mux Selection Register - GENERALIO28 + * + * This register is used to control the peripherals connected to spis0_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spis0_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis0_clk Mux Selection Field - sel + * + * Select peripheral signals connected spis0_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 67. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.SS1. + * + * 3 : Pin is connected to Peripheral signal SPIS0.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO28_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO28. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO28_s +{ + uint32_t sel : 2; /* spis0_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO28. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO28_s ALT_SYSMGR_PINMUX_GENERALIO28_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO28 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_OFST 0xf0 + +/* + * Register : spis0_mosi Mux Selection Register - GENERALIO29 + * + * This register is used to control the peripherals connected to spis0_mosi + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spis0_mosi Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis0_mosi Mux Selection Field - sel + * + * Select peripheral signals connected spis0_mosi. + * + * 0 : Pin is connected to GPIO/LoanIO number 68. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal SPIS0.MOSI. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO29_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO29. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO29_s +{ + uint32_t sel : 2; /* spis0_mosi Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO29. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO29_s ALT_SYSMGR_PINMUX_GENERALIO29_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO29 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_OFST 0xf4 + +/* + * Register : spis0_miso Mux Selection Register - GENERALIO30 + * + * This register is used to control the peripherals connected to spis0_miso + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spis0_miso Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis0_miso Mux Selection Field - sel + * + * Select peripheral signals connected spis0_miso. + * + * 0 : Pin is connected to GPIO/LoanIO number 69. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal SPIS0.MISO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO30_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO30. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO30_s +{ + uint32_t sel : 2; /* spis0_miso Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO30. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO30_s ALT_SYSMGR_PINMUX_GENERALIO30_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO30 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_OFST 0xf8 + +/* + * Register : spis0_ss0 Mux Selection Register - GENERALIO31 + * + * This register is used to control the peripherals connected to spis0_ss0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spis0_ss0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis0_ss0 Mux Selection Field - sel + * + * Select peripheral signals connected spis0_ss0. + * + * 0 : Pin is connected to GPIO/LoanIO number 70. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal SPIS0.SS0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO31_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO31. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO31_s +{ + uint32_t sel : 2; /* spis0_ss0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO31. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO31_s ALT_SYSMGR_PINMUX_GENERALIO31_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO31 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_OFST 0xfc + +/* + * Register : nand_ale Mux Selection Register - MIXED1IO0 + * + * This register is used to control the peripherals connected to nand_ale + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_ale Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_ale Mux Selection Field - sel + * + * Select peripheral signals connected nand_ale. + * + * 0 : Pin is connected to GPIO/LoanIO number 14. + * + * 1 : Pin is connected to Peripheral signal QSPI.SS3. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TX_CLK. + * + * 3 : Pin is connected to Peripheral signal NAND.ale. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO0. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO0_s +{ + uint32_t sel : 2; /* nand_ale Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO0_s ALT_SYSMGR_PINMUX_MIXED1IO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_OFST 0x100 + +/* + * Register : nand_ce Mux Selection Register - MIXED1IO1 + * + * This register is used to control the peripherals connected to nand_ce + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_ce Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_ce Mux Selection Field - sel + * + * Select peripheral signals connected nand_ce. + * + * 0 : Pin is connected to GPIO/LoanIO number 15. + * + * 1 : Pin is connected to Peripheral signal USB1.D0. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TXD0. + * + * 3 : Pin is connected to Peripheral signal NAND.ce. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO1. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO1_s +{ + uint32_t sel : 2; /* nand_ce Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO1_s ALT_SYSMGR_PINMUX_MIXED1IO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_OFST 0x104 + +/* + * Register : nand_cle Mux Selection Register - MIXED1IO2 + * + * This register is used to control the peripherals connected to nand_cle + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_cle Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_cle Mux Selection Field - sel + * + * Select peripheral signals connected nand_cle. + * + * 0 : Pin is connected to GPIO/LoanIO number 16. + * + * 1 : Pin is connected to Peripheral signal USB1.D1. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TXD1. + * + * 3 : Pin is connected to Peripheral signal NAND.cle. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO2. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO2_s +{ + uint32_t sel : 2; /* nand_cle Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO2_s ALT_SYSMGR_PINMUX_MIXED1IO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_OFST 0x108 + +/* + * Register : nand_re Mux Selection Register - MIXED1IO3 + * + * This register is used to control the peripherals connected to nand_re + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_re Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_re Mux Selection Field - sel + * + * Select peripheral signals connected nand_re. + * + * 0 : Pin is connected to GPIO/LoanIO number 17. + * + * 1 : Pin is connected to Peripheral signal USB1.D2. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TXD2. + * + * 3 : Pin is connected to Peripheral signal NAND.re. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO3. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO3_s +{ + uint32_t sel : 2; /* nand_re Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO3_s ALT_SYSMGR_PINMUX_MIXED1IO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_OFST 0x10c + +/* + * Register : nand_rb Mux Selection Register - MIXED1IO4 + * + * This register is used to control the peripherals connected to nand_rb + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_rb Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_rb Mux Selection Field - sel + * + * Select peripheral signals connected nand_rb. + * + * 0 : Pin is connected to GPIO/LoanIO number 18. + * + * 1 : Pin is connected to Peripheral signal USB1.D3. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TXD3. + * + * 3 : Pin is connected to Peripheral signal NAND.rb. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO4. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO4_s +{ + uint32_t sel : 2; /* nand_rb Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO4_s ALT_SYSMGR_PINMUX_MIXED1IO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_OFST 0x110 + +/* + * Register : nand_dq0 Mux Selection Register - MIXED1IO5 + * + * This register is used to control the peripherals connected to nand_dq0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq0 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq0. + * + * 0 : Pin is connected to GPIO/LoanIO number 19. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RXD0. + * + * 3 : Pin is connected to Peripheral signal NAND.dq0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO5. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO5_s +{ + uint32_t sel : 2; /* nand_dq0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO5_s ALT_SYSMGR_PINMUX_MIXED1IO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_OFST 0x114 + +/* + * Register : nand_dq1 Mux Selection Register - MIXED1IO6 + * + * This register is used to control the peripherals connected to nand_dq1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq1 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq1. + * + * 0 : Pin is connected to GPIO/LoanIO number 20. + * + * 1 : Pin is connected to Peripheral signal I2C3.SDA. + * + * 2 : Pin is connected to Peripheral signal RGMII1.MDIO. + * + * 3 : Pin is connected to Peripheral signal NAND.dq1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO6. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO6_s +{ + uint32_t sel : 2; /* nand_dq1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO6_s ALT_SYSMGR_PINMUX_MIXED1IO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_OFST 0x118 + +/* + * Register : nand_dq2 Mux Selection Register - MIXED1IO7 + * + * This register is used to control the peripherals connected to nand_dq2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq2 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq2. + * + * 0 : Pin is connected to GPIO/LoanIO number 21. + * + * 1 : Pin is connected to Peripheral signal I2C3.SCL. + * + * 2 : Pin is connected to Peripheral signal RGMII1.MDC. + * + * 3 : Pin is connected to Peripheral signal NAND.dq2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO7. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO7_s +{ + uint32_t sel : 2; /* nand_dq2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO7_s ALT_SYSMGR_PINMUX_MIXED1IO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_OFST 0x11c + +/* + * Register : nand_dq3 Mux Selection Register - MIXED1IO8 + * + * This register is used to control the peripherals connected to nand_dq3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq3 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq3. + * + * 0 : Pin is connected to GPIO/LoanIO number 22. + * + * 1 : Pin is connected to Peripheral signal USB1.D4. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RX_CTL. + * + * 3 : Pin is connected to Peripheral signal NAND.dq3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO8. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO8_s +{ + uint32_t sel : 2; /* nand_dq3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO8_s ALT_SYSMGR_PINMUX_MIXED1IO8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_OFST 0x120 + +/* + * Register : nand_dq4 Mux Selection Register - MIXED1IO9 + * + * This register is used to control the peripherals connected to nand_dq4 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq4 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq4 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq4. + * + * 0 : Pin is connected to GPIO/LoanIO number 23. + * + * 1 : Pin is connected to Peripheral signal USB1.D5. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TX_CTL. + * + * 3 : Pin is connected to Peripheral signal NAND.dq4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO9. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO9_s +{ + uint32_t sel : 2; /* nand_dq4 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO9_s ALT_SYSMGR_PINMUX_MIXED1IO9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_OFST 0x124 + +/* + * Register : nand_dq5 Mux Selection Register - MIXED1IO10 + * + * This register is used to control the peripherals connected to nand_dq5 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq5 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq5 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq5. + * + * 0 : Pin is connected to GPIO/LoanIO number 24. + * + * 1 : Pin is connected to Peripheral signal USB1.D6. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RX_CLK. + * + * 3 : Pin is connected to Peripheral signal NAND.dq5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO10. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO10_s +{ + uint32_t sel : 2; /* nand_dq5 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO10_s ALT_SYSMGR_PINMUX_MIXED1IO10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_OFST 0x128 + +/* + * Register : nand_dq6 Mux Selection Register - MIXED1IO11 + * + * This register is used to control the peripherals connected to nand_dq6 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq6 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq6 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq6. + * + * 0 : Pin is connected to GPIO/LoanIO number 25. + * + * 1 : Pin is connected to Peripheral signal USB1.D7. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RXD1. + * + * 3 : Pin is connected to Peripheral signal NAND.dq6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO11. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO11_s +{ + uint32_t sel : 2; /* nand_dq6 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO11_s ALT_SYSMGR_PINMUX_MIXED1IO11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_OFST 0x12c + +/* + * Register : nand_dq7 Mux Selection Register - MIXED1IO12 + * + * This register is used to control the peripherals connected to nand_dq7 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq7 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq7 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq7. + * + * 0 : Pin is connected to GPIO/LoanIO number 26. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RXD2. + * + * 3 : Pin is connected to Peripheral signal NAND.dq7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO12. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO12_s +{ + uint32_t sel : 2; /* nand_dq7 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO12. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO12_s ALT_SYSMGR_PINMUX_MIXED1IO12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO12 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_OFST 0x130 + +/* + * Register : nand_wp Mux Selection Register - MIXED1IO13 + * + * This register is used to control the peripherals connected to nand_wp + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_wp Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_wp Mux Selection Field - sel + * + * Select peripheral signals connected nand_wp. + * + * 0 : Pin is connected to GPIO/LoanIO number 27. + * + * 1 : Pin is connected to Peripheral signal QSPI.SS2. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RXD3. + * + * 3 : Pin is connected to Peripheral signal NAND.wp. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO13. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO13_s +{ + uint32_t sel : 2; /* nand_wp Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO13. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO13_s ALT_SYSMGR_PINMUX_MIXED1IO13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO13 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_OFST 0x134 + +/* + * Register : nand_we Mux Selection Register - MIXED1IO14 + * + * This register is used to control the peripherals connected to nand_we + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_we Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_we Mux Selection Field - sel + * + * Select peripheral signals connected nand_we. + * + * 0 : Pin is connected to GPIO/LoanIO number 28. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal QSPI.SS1. + * + * 3 : Pin is connected to Peripheral signal NAND.we. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO14. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO14_s +{ + uint32_t sel : 2; /* nand_we Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO14. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO14_s ALT_SYSMGR_PINMUX_MIXED1IO14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO14 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_OFST 0x138 + +/* + * Register : qspi_io0 Mux Selection Register - MIXED1IO15 + * + * This register is used to control the peripherals connected to qspi_io0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_io0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_io0 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_io0. + * + * 0 : Pin is connected to GPIO/LoanIO number 29. + * + * 1 : Pin is connected to Peripheral signal USB1.CLK. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.IO0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO15. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO15_s +{ + uint32_t sel : 2; /* qspi_io0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO15. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO15_s ALT_SYSMGR_PINMUX_MIXED1IO15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO15 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_OFST 0x13c + +/* + * Register : qspi_io1 Mux Selection Register - MIXED1IO16 + * + * This register is used to control the peripherals connected to qspi_io1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_io1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_io1 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_io1. + * + * 0 : Pin is connected to GPIO/LoanIO number 30. + * + * 1 : Pin is connected to Peripheral signal USB1.STP. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.IO1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO16. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO16_s +{ + uint32_t sel : 2; /* qspi_io1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO16. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO16_s ALT_SYSMGR_PINMUX_MIXED1IO16_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO16 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_OFST 0x140 + +/* + * Register : qspi_io2 Mux Selection Register - MIXED1IO17 + * + * This register is used to control the peripherals connected to qspi_io2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_io2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_io2 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_io2. + * + * 0 : Pin is connected to GPIO/LoanIO number 31. + * + * 1 : Pin is connected to Peripheral signal USB1.DIR. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.IO2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO17. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO17_s +{ + uint32_t sel : 2; /* qspi_io2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO17. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO17_s ALT_SYSMGR_PINMUX_MIXED1IO17_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO17 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_OFST 0x144 + +/* + * Register : qspi_io3 Mux Selection Register - MIXED1IO18 + * + * This register is used to control the peripherals connected to qspi_io3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_io3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_io3 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_io3. + * + * 0 : Pin is connected to GPIO/LoanIO number 32. + * + * 1 : Pin is connected to Peripheral signal USB1.NXT. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.IO3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO18. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO18_s +{ + uint32_t sel : 2; /* qspi_io3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO18. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO18_s ALT_SYSMGR_PINMUX_MIXED1IO18_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO18 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_OFST 0x148 + +/* + * Register : qspi_ss0 Mux Selection Register - MIXED1IO19 + * + * This register is used to control the peripherals connected to qspi_ss0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_ss0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_ss0 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_ss0. + * + * 0 : Pin is connected to GPIO/LoanIO number 33. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.SS0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO19. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO19_s +{ + uint32_t sel : 2; /* qspi_ss0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO19. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO19_s ALT_SYSMGR_PINMUX_MIXED1IO19_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO19 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_OFST 0x14c + +/* + * Register : qpsi_clk Mux Selection Register - MIXED1IO20 + * + * This register is used to control the peripherals connected to qpsi_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qpsi_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qpsi_clk Mux Selection Field - sel + * + * Select peripheral signals connected qpsi_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 34. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO20. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO20_s +{ + uint32_t sel : 2; /* qpsi_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO20. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO20_s ALT_SYSMGR_PINMUX_MIXED1IO20_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO20 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_OFST 0x150 + +/* + * Register : qspi_ss1 Mux Selection Register - MIXED1IO21 + * + * This register is used to control the peripherals connected to qspi_ss1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_ss1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_ss1 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_ss1. + * + * 0 : Pin is connected to GPIO/LoanIO number 35. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.SS1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO21. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO21_s +{ + uint32_t sel : 2; /* qspi_ss1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO21. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO21_s ALT_SYSMGR_PINMUX_MIXED1IO21_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO21 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_OFST 0x154 + +/* + * Register : emac1_mdio Mux Selection Register - MIXED2IO0 + * + * This register is used to control the peripherals connected to emac1_mdio + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | emac1_mdio Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_mdio Mux Selection Field - sel + * + * Select peripheral signals connected emac1_mdio. + * + * 0 : Pin is connected to GPIO/LoanIO number 54. + * + * 1 : Pin is connected to Peripheral signal SPIS0.CLK. + * + * 2 : Pin is connected to Peripheral signal SPIM0.CLK. + * + * 3 : Pin is connected to Peripheral signal RGMII1.MDIO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO0. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO0_s +{ + uint32_t sel : 2; /* emac1_mdio Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO0_s ALT_SYSMGR_PINMUX_MIXED2IO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_OFST 0x158 + +/* + * Register : emac1_mdc Mux Selection Register - MIXED2IO1 + * + * This register is used to control the peripherals connected to emac1_mdc + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | emac1_mdc Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_mdc Mux Selection Field - sel + * + * Select peripheral signals connected emac1_mdc. + * + * 0 : Pin is connected to GPIO/LoanIO number 55. + * + * 1 : Pin is connected to Peripheral signal SPIS0.MOSI. + * + * 2 : Pin is connected to Peripheral signal SPIM0.MOSI. + * + * 3 : Pin is connected to Peripheral signal RGMII1.MDC. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO1. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO1_s +{ + uint32_t sel : 2; /* emac1_mdc Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO1_s ALT_SYSMGR_PINMUX_MIXED2IO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_OFST 0x15c + +/* + * Register : emac1_tx_d2 Mux Selection Register - MIXED2IO2 + * + * This register is used to control the peripherals connected to emac1_tx_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_d2 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 56. + * + * 1 : Pin is connected to Peripheral signal SPIS0.MISO. + * + * 2 : Pin is connected to Peripheral signal SPIM0.MISO. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TXD2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO2. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO2_s +{ + uint32_t sel : 2; /* emac1_tx_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO2_s ALT_SYSMGR_PINMUX_MIXED2IO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_OFST 0x160 + +/* + * Register : emac1_tx_d3 Mux Selection Register - MIXED2IO3 + * + * This register is used to control the peripherals connected to emac1_tx_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_d3 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 57. + * + * 1 : Pin is connected to Peripheral signal SPIS0.SS0. + * + * 2 : Pin is connected to Peripheral signal SPIM0.SS0. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TXD3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO3. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO3_s +{ + uint32_t sel : 2; /* emac1_tx_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO3_s ALT_SYSMGR_PINMUX_MIXED2IO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_OFST 0x164 + +/* + * Register : emac1_rx_clk Mux Selection Register - MIXED2IO4 + * + * This register is used to control the peripherals connected to emac1_rx_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_clk Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 58. + * + * 1 : Pin is connected to Peripheral signal SPIM1.CLK. + * + * 2 : Pin is connected to Peripheral signal SPIS1.CLK. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RX_CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO4. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO4_s +{ + uint32_t sel : 2; /* emac1_rx_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO4_s ALT_SYSMGR_PINMUX_MIXED2IO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_OFST 0x168 + +/* + * Register : emac1_rx_ctl Mux Selection Register - MIXED2IO5 + * + * This register is used to control the peripherals connected to emac1_rx_ctl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_ctl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_ctl Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_ctl. + * + * 0 : Pin is connected to GPIO/LoanIO number 59. + * + * 1 : Pin is connected to Peripheral signal SPIM1.MOSI. + * + * 2 : Pin is connected to Peripheral signal SPIS1.MOSI. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RX_CTL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO5. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO5_s +{ + uint32_t sel : 2; /* emac1_rx_ctl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO5_s ALT_SYSMGR_PINMUX_MIXED2IO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_OFST 0x16c + +/* + * Register : emac1_rx_d2 Mux Selection Register - MIXED2IO6 + * + * This register is used to control the peripherals connected to emac1_rx_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_d2 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 60. + * + * 1 : Pin is connected to Peripheral signal SPIM1.MISO. + * + * 2 : Pin is connected to Peripheral signal SPIS1.MISO. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RXD2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO6. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO6_s +{ + uint32_t sel : 2; /* emac1_rx_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO6_s ALT_SYSMGR_PINMUX_MIXED2IO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_OFST 0x170 + +/* + * Register : emac1_rx_d3 Mux Selection Register - MIXED2IO7 + * + * This register is used to control the peripherals connected to emac1_rx_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_d3 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 61. + * + * 1 : Pin is connected to Peripheral signal SPIM1.SS0. + * + * 2 : Pin is connected to Peripheral signal SPIS1.SS0. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RXD3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO7. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO7_s +{ + uint32_t sel : 2; /* emac1_rx_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO7_s ALT_SYSMGR_PINMUX_MIXED2IO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_OFST 0x174 + +/* + * Register : GPIO/LoanIO 48 Input Mux Selection Register - GPLINMUX48 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 48. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO48Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO48Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 48. + * + * 0 : Source for GPIO/LoanIO 48 is GENERALIO0. + * + * 1 : Source for GPIO/LoanIO 48 is EMACIO14. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX48. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX48_s +{ + uint32_t sel : 1; /* GPIO/Loan IO48Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX48. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX48_s ALT_SYSMGR_PINMUX_GPLINMUX48_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX48 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_OFST 0x178 + +/* + * Register : GPIO/LoanIO 49 Input Mux Selection Register - GPLINMUX49 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 49. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO49Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO49Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 49. + * + * 0 : Source for GPIO/LoanIO 49 is GENERALIO1. + * + * 1 : Source for GPIO/LoanIO 49 is EMACIO15. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX49. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX49_s +{ + uint32_t sel : 1; /* GPIO/Loan IO49Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX49. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX49_s ALT_SYSMGR_PINMUX_GPLINMUX49_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX49 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_OFST 0x17c + +/* + * Register : GPIO/LoanIO 50 Input Mux Selection Register - GPLINMUX50 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 50. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO50Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO50Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 50. + * + * 0 : Source for GPIO/LoanIO 50 is GENERALIO2. + * + * 1 : Source for GPIO/LoanIO 50 is EMACIO16. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX50. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX50_s +{ + uint32_t sel : 1; /* GPIO/Loan IO50Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX50. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX50_s ALT_SYSMGR_PINMUX_GPLINMUX50_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX50 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_OFST 0x180 + +/* + * Register : GPIO/LoanIO 51 Input Mux Selection Register - GPLINMUX51 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 51. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO51Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO51Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 51. + * + * 0 : Source for GPIO/LoanIO 51 is GENERALIO3. + * + * 1 : Source for GPIO/LoanIO 51 is EMACIO17. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX51. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX51_s +{ + uint32_t sel : 1; /* GPIO/Loan IO51Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX51. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX51_s ALT_SYSMGR_PINMUX_GPLINMUX51_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX51 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_OFST 0x184 + +/* + * Register : GPIO/LoanIO 52 Input Mux Selection Register - GPLINMUX52 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 52. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO52Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO52Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 52. + * + * 0 : Source for GPIO/LoanIO 52 is GENERALIO4. + * + * 1 : Source for GPIO/LoanIO 52 is EMACIO18. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX52. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX52_s +{ + uint32_t sel : 1; /* GPIO/Loan IO52Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX52. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX52_s ALT_SYSMGR_PINMUX_GPLINMUX52_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX52 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_OFST 0x188 + +/* + * Register : GPIO/LoanIO 53 Input Mux Selection Register - GPLINMUX53 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 53. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO53Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO53Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 53. + * + * 0 : Source for GPIO/LoanIO 53 is GENERALIO5. + * + * 1 : Source for GPIO/LoanIO 53 is EMACIO19. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX53. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX53_s +{ + uint32_t sel : 1; /* GPIO/Loan IO53Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX53. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX53_s ALT_SYSMGR_PINMUX_GPLINMUX53_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX53 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_OFST 0x18c + +/* + * Register : GPIO/LoanIO 54 Input Mux Selection Register - GPLINMUX54 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 54. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO54Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO54Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 54. + * + * 0 : Source for GPIO/LoanIO 54 is GENERALIO6. + * + * 1 : Source for GPIO/LoanIO 54 is MIXED2IO0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX54. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX54_s +{ + uint32_t sel : 1; /* GPIO/Loan IO54Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX54. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX54_s ALT_SYSMGR_PINMUX_GPLINMUX54_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX54 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_OFST 0x190 + +/* + * Register : GPIO/LoanIO 55 Input Mux Selection Register - GPLINMUX55 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 55. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO55Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO55Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 55. + * + * 0 : Source for GPIO/LoanIO 55 is GENERALIO7. + * + * 1 : Source for GPIO/LoanIO 55 is MIXED2IO1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX55. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX55_s +{ + uint32_t sel : 1; /* GPIO/Loan IO55Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX55. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX55_s ALT_SYSMGR_PINMUX_GPLINMUX55_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX55 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_OFST 0x194 + +/* + * Register : GPIO/LoanIO 56 Input Mux Selection Register - GPLINMUX56 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 56. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO56Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO56Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 56. + * + * 0 : Source for GPIO/LoanIO 56 is GENERALIO8. + * + * 1 : Source for GPIO/LoanIO 56 is MIXED2IO2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX56. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX56_s +{ + uint32_t sel : 1; /* GPIO/Loan IO56Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX56. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX56_s ALT_SYSMGR_PINMUX_GPLINMUX56_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX56 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_OFST 0x198 + +/* + * Register : GPIO/LoanIO 57 Input Mux Selection Register - GPLINMUX57 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 57. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO57Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO57Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 57. + * + * 0 : Source for GPIO/LoanIO 57 is GENERALIO9. + * + * 1 : Source for GPIO/LoanIO 57 is MIXED2IO3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX57. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX57_s +{ + uint32_t sel : 1; /* GPIO/Loan IO57Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX57. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX57_s ALT_SYSMGR_PINMUX_GPLINMUX57_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX57 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_OFST 0x19c + +/* + * Register : GPIO/LoanIO 58 Input Mux Selection Register - GPLINMUX58 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 58. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO58Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO58Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 58. + * + * 0 : Source for GPIO/LoanIO 58 is GENERALIO10. + * + * 1 : Source for GPIO/LoanIO 58 is MIXED2IO4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX58. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX58_s +{ + uint32_t sel : 1; /* GPIO/Loan IO58Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX58. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX58_s ALT_SYSMGR_PINMUX_GPLINMUX58_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX58 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_OFST 0x1a0 + +/* + * Register : GPIO/LoanIO 59 Input Mux Selection Register - GPLINMUX59 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 59. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO59Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO59Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 59. + * + * 0 : Source for GPIO/LoanIO 59 is GENERALIO11. + * + * 1 : Source for GPIO/LoanIO 59 is MIXED2IO5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX59. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX59_s +{ + uint32_t sel : 1; /* GPIO/Loan IO59Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX59. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX59_s ALT_SYSMGR_PINMUX_GPLINMUX59_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX59 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_OFST 0x1a4 + +/* + * Register : GPIO/LoanIO 60 Input Mux Selection Register - GPLINMUX60 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 60. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO60Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO60Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 60. + * + * 0 : Source for GPIO/LoanIO 60 is GENERALIO12. + * + * 1 : Source for GPIO/LoanIO 60 is MIXED2IO6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX60. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX60_s +{ + uint32_t sel : 1; /* GPIO/Loan IO60Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX60. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX60_s ALT_SYSMGR_PINMUX_GPLINMUX60_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX60 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_OFST 0x1a8 + +/* + * Register : GPIO/LoanIO 61 Input Mux Selection Register - GPLINMUX61 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 61. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO61Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO61Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 61. + * + * 0 : Source for GPIO/LoanIO 61 is GENERALIO13. + * + * 1 : Source for GPIO/LoanIO 61 is MIXED2IO7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX61. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX61_s +{ + uint32_t sel : 1; /* GPIO/Loan IO61Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX61. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX61_s ALT_SYSMGR_PINMUX_GPLINMUX61_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX61 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_OFST 0x1ac + +/* + * Register : GPIO/LoanIO 62 Input Mux Selection Register - GPLINMUX62 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 62. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO62Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO62Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 62. + * + * 0 : Source for GPIO/LoanIO 62 is GENERALIO14. + * + * 1 : Source for GPIO/LoanIO 62 is GENERALIO23. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX62. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX62_s +{ + uint32_t sel : 1; /* GPIO/Loan IO62Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX62. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX62_s ALT_SYSMGR_PINMUX_GPLINMUX62_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX62 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_OFST 0x1b0 + +/* + * Register : GPIO/LoanIO 63 Input Mux Selection Register - GPLINMUX63 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 63. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO63Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO63Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 63. + * + * 0 : Source for GPIO/LoanIO 63 is GENERALIO15. + * + * 1 : Source for GPIO/LoanIO 63 is GENERALIO24. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX63. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX63_s +{ + uint32_t sel : 1; /* GPIO/Loan IO63Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX63. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX63_s ALT_SYSMGR_PINMUX_GPLINMUX63_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX63 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_OFST 0x1b4 + +/* + * Register : GPIO/LoanIO 64 Input Mux Selection Register - GPLINMUX64 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 64. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO64Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO64Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 64. + * + * 0 : Source for GPIO/LoanIO 64 is GENERALIO16. + * + * 1 : Source for GPIO/LoanIO 64 is GENERALIO25. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX64. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX64_s +{ + uint32_t sel : 1; /* GPIO/Loan IO64Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX64. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX64_s ALT_SYSMGR_PINMUX_GPLINMUX64_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX64 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_OFST 0x1b8 + +/* + * Register : GPIO/LoanIO 65 Input Mux Selection Register - GPLINMUX65 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 65. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO65Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO65Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 65. + * + * 0 : Source for GPIO/LoanIO 65 is GENERALIO17. + * + * 1 : Source for GPIO/LoanIO 65 is GENERALIO26. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX65. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX65_s +{ + uint32_t sel : 1; /* GPIO/Loan IO65Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX65. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX65_s ALT_SYSMGR_PINMUX_GPLINMUX65_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX65 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_OFST 0x1bc + +/* + * Register : GPIO/LoanIO 66 Input Mux Selection Register - GPLINMUX66 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 66. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO66Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO66Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 66. + * + * 0 : Source for GPIO/LoanIO 66 is GENERALIO18. + * + * 1 : Source for GPIO/LoanIO 66 is GENERALIO27. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX66. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX66_s +{ + uint32_t sel : 1; /* GPIO/Loan IO66Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX66. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX66_s ALT_SYSMGR_PINMUX_GPLINMUX66_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX66 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_OFST 0x1c0 + +/* + * Register : GPIO/LoanIO 67 Input Mux Selection Register - GPLINMUX67 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 67. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO67Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO67Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 67. + * + * 0 : Source for GPIO/LoanIO 67 is GENERALIO19. + * + * 1 : Source for GPIO/LoanIO 67 is GENERALIO28. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX67. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX67_s +{ + uint32_t sel : 1; /* GPIO/Loan IO67Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX67. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX67_s ALT_SYSMGR_PINMUX_GPLINMUX67_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX67 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_OFST 0x1c4 + +/* + * Register : GPIO/LoanIO 68 Input Mux Selection Register - GPLINMUX68 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 68. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO68Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO68Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 68. + * + * 0 : Source for GPIO/LoanIO 68 is GENERALIO20. + * + * 1 : Source for GPIO/LoanIO 68 is GENERALIO29. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX68. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX68_s +{ + uint32_t sel : 1; /* GPIO/Loan IO68Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX68. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX68_s ALT_SYSMGR_PINMUX_GPLINMUX68_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX68 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_OFST 0x1c8 + +/* + * Register : GPIO/LoanIO 69 Input Mux Selection Register - GPLINMUX69 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 69. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO69Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO69Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 69. + * + * 0 : Source for GPIO/LoanIO 69 is GENERALIO21. + * + * 1 : Source for GPIO/LoanIO 69 is GENERALIO30. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX69. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX69_s +{ + uint32_t sel : 1; /* GPIO/Loan IO69Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX69. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX69_s ALT_SYSMGR_PINMUX_GPLINMUX69_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX69 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_OFST 0x1cc + +/* + * Register : GPIO/LoanIO 70 Input Mux Selection Register - GPLINMUX70 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 70. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO70Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO70Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 70. + * + * 0 : Source for GPIO/LoanIO 70 is GENERALIO22. + * + * 1 : Source for GPIO/LoanIO 70 is GENERALIO31. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX70. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX70_s +{ + uint32_t sel : 1; /* GPIO/Loan IO70Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX70. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX70_s ALT_SYSMGR_PINMUX_GPLINMUX70_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX70 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_OFST 0x1d0 + +/* + * Register : GPIO/LoanIO 0 Output/Output Enable Mux Selection Register - GPLMUX0 + * + * Selection between GPIO and LoanIO output and output enable for GPIO0 and + * LoanIO0. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO0Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO0Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 0. + * + * 0 : LoanIO 0 controls GPIO/LOANIO[0] output and output enable signals. + * + * 1 : GPIO 0 controls GPIO/LOANI[0] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX0. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX0_s +{ + uint32_t sel : 1; /* GPIO/Loan IO0Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX0_s ALT_SYSMGR_PINMUX_GPLMUX0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_OFST 0x1d4 + +/* + * Register : GPIO/LoanIO 1 Output/Output Enable Mux Selection Register - GPLMUX1 + * + * Selection between GPIO and LoanIO output and output enable for GPIO1 and + * LoanIO1. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO1Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO1Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 1. + * + * 0 : LoanIO 1 controls GPIO/LOANIO[1] output and output enable signals. + * + * 1 : GPIO 1 controls GPIO/LOANI[1] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX1. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX1_s +{ + uint32_t sel : 1; /* GPIO/Loan IO1Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX1_s ALT_SYSMGR_PINMUX_GPLMUX1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_OFST 0x1d8 + +/* + * Register : GPIO/LoanIO 2 Output/Output Enable Mux Selection Register - GPLMUX2 + * + * Selection between GPIO and LoanIO output and output enable for GPIO2 and + * LoanIO2. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO2Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO2Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 2. + * + * 0 : LoanIO 2 controls GPIO/LOANIO[2] output and output enable signals. + * + * 1 : GPIO 2 controls GPIO/LOANI[2] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX2. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX2_s +{ + uint32_t sel : 1; /* GPIO/Loan IO2Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX2_s ALT_SYSMGR_PINMUX_GPLMUX2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_OFST 0x1dc + +/* + * Register : GPIO/LoanIO 3 Output/Output Enable Mux Selection Register - GPLMUX3 + * + * Selection between GPIO and LoanIO output and output enable for GPIO3 and + * LoanIO3. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO3Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO3Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 3. + * + * 0 : LoanIO 3 controls GPIO/LOANIO[3] output and output enable signals. + * + * 1 : GPIO 3 controls GPIO/LOANI[3] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX3. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX3_s +{ + uint32_t sel : 1; /* GPIO/Loan IO3Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX3_s ALT_SYSMGR_PINMUX_GPLMUX3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_OFST 0x1e0 + +/* + * Register : GPIO/LoanIO 4 Output/Output Enable Mux Selection Register - GPLMUX4 + * + * Selection between GPIO and LoanIO output and output enable for GPIO4 and + * LoanIO4. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO4Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO4Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 4. + * + * 0 : LoanIO 4 controls GPIO/LOANIO[4] output and output enable signals. + * + * 1 : GPIO 4 controls GPIO/LOANI[4] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX4. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX4_s +{ + uint32_t sel : 1; /* GPIO/Loan IO4Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX4_s ALT_SYSMGR_PINMUX_GPLMUX4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_OFST 0x1e4 + +/* + * Register : GPIO/LoanIO 5 Output/Output Enable Mux Selection Register - GPLMUX5 + * + * Selection between GPIO and LoanIO output and output enable for GPIO5 and + * LoanIO5. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO5Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO5Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 5. + * + * 0 : LoanIO 5 controls GPIO/LOANIO[5] output and output enable signals. + * + * 1 : GPIO 5 controls GPIO/LOANI[5] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX5. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX5_s +{ + uint32_t sel : 1; /* GPIO/Loan IO5Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX5_s ALT_SYSMGR_PINMUX_GPLMUX5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_OFST 0x1e8 + +/* + * Register : GPIO/LoanIO 6 Output/Output Enable Mux Selection Register - GPLMUX6 + * + * Selection between GPIO and LoanIO output and output enable for GPIO6 and + * LoanIO6. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO6Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO6Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 6. + * + * 0 : LoanIO 6 controls GPIO/LOANIO[6] output and output enable signals. + * + * 1 : GPIO 6 controls GPIO/LOANI[6] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX6. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX6_s +{ + uint32_t sel : 1; /* GPIO/Loan IO6Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX6_s ALT_SYSMGR_PINMUX_GPLMUX6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_OFST 0x1ec + +/* + * Register : GPIO/LoanIO 7 Output/Output Enable Mux Selection Register - GPLMUX7 + * + * Selection between GPIO and LoanIO output and output enable for GPIO7 and + * LoanIO7. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO7Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO7Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 7. + * + * 0 : LoanIO 7 controls GPIO/LOANIO[7] output and output enable signals. + * + * 1 : GPIO 7 controls GPIO/LOANI[7] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX7. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX7_s +{ + uint32_t sel : 1; /* GPIO/Loan IO7Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX7_s ALT_SYSMGR_PINMUX_GPLMUX7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_OFST 0x1f0 + +/* + * Register : GPIO/LoanIO 8 Output/Output Enable Mux Selection Register - GPLMUX8 + * + * Selection between GPIO and LoanIO output and output enable for GPIO8 and + * LoanIO8. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO8Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO8Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 8. + * + * 0 : LoanIO 8 controls GPIO/LOANIO[8] output and output enable signals. + * + * 1 : GPIO 8 controls GPIO/LOANI[8] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX8. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX8_s +{ + uint32_t sel : 1; /* GPIO/Loan IO8Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX8_s ALT_SYSMGR_PINMUX_GPLMUX8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_OFST 0x1f4 + +/* + * Register : GPIO/LoanIO 9 Output/Output Enable Mux Selection Register - GPLMUX9 + * + * Selection between GPIO and LoanIO output and output enable for GPIO9 and + * LoanIO9. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO9Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO9Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 9. + * + * 0 : LoanIO 9 controls GPIO/LOANIO[9] output and output enable signals. + * + * 1 : GPIO 9 controls GPIO/LOANI[9] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX9. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX9_s +{ + uint32_t sel : 1; /* GPIO/Loan IO9Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX9_s ALT_SYSMGR_PINMUX_GPLMUX9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_OFST 0x1f8 + +/* + * Register : GPIO/LoanIO 10 Output/Output Enable Mux Selection Register - GPLMUX10 + * + * Selection between GPIO and LoanIO output and output enable for GPIO10 and + * LoanIO10. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO10Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO10Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 10. + * + * 0 : LoanIO 10 controls GPIO/LOANIO[10] output and output enable signals. + * + * 1 : GPIO 10 controls GPIO/LOANI[10] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX10. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX10_s +{ + uint32_t sel : 1; /* GPIO/Loan IO10Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX10_s ALT_SYSMGR_PINMUX_GPLMUX10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_OFST 0x1fc + +/* + * Register : GPIO/LoanIO 11 Output/Output Enable Mux Selection Register - GPLMUX11 + * + * Selection between GPIO and LoanIO output and output enable for GPIO11 and + * LoanIO11. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO11Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO11Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 11. + * + * 0 : LoanIO 11 controls GPIO/LOANIO[11] output and output enable signals. + * + * 1 : GPIO 11 controls GPIO/LOANI[11] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX11. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX11_s +{ + uint32_t sel : 1; /* GPIO/Loan IO11Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX11_s ALT_SYSMGR_PINMUX_GPLMUX11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_OFST 0x200 + +/* + * Register : GPIO/LoanIO 12 Output/Output Enable Mux Selection Register - GPLMUX12 + * + * Selection between GPIO and LoanIO output and output enable for GPIO12 and + * LoanIO12. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO12Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO12Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 12. + * + * 0 : LoanIO 12 controls GPIO/LOANIO[12] output and output enable signals. + * + * 1 : GPIO 12 controls GPIO/LOANI[12] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX12_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX12. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX12_s +{ + uint32_t sel : 1; /* GPIO/Loan IO12Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX12. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX12_s ALT_SYSMGR_PINMUX_GPLMUX12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX12 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_OFST 0x204 + +/* + * Register : GPIO/LoanIO 13 Output/Output Enable Mux Selection Register - GPLMUX13 + * + * Selection between GPIO and LoanIO output and output enable for GPIO13 and + * LoanIO13. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO13Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO13Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 13. + * + * 0 : LoanIO 13 controls GPIO/LOANIO[13] output and output enable signals. + * + * 1 : GPIO 13 controls GPIO/LOANI[13] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX13_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX13. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX13_s +{ + uint32_t sel : 1; /* GPIO/Loan IO13Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX13. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX13_s ALT_SYSMGR_PINMUX_GPLMUX13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX13 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_OFST 0x208 + +/* + * Register : GPIO/LoanIO 14 Output/Output Enable Mux Selection Register - GPLMUX14 + * + * Selection between GPIO and LoanIO output and output enable for GPIO14 and + * LoanIO14. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO14Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO14Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 14. + * + * 0 : LoanIO 14 controls GPIO/LOANIO[14] output and output enable signals. + * + * 1 : GPIO 14 controls GPIO/LOANI[14] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX14_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX14. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX14_s +{ + uint32_t sel : 1; /* GPIO/Loan IO14Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX14. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX14_s ALT_SYSMGR_PINMUX_GPLMUX14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX14 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_OFST 0x20c + +/* + * Register : GPIO/LoanIO 15 Output/Output Enable Mux Selection Register - GPLMUX15 + * + * Selection between GPIO and LoanIO output and output enable for GPIO15 and + * LoanIO15. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO15Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO15Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 15. + * + * 0 : LoanIO 15 controls GPIO/LOANIO[15] output and output enable signals. + * + * 1 : GPIO 15 controls GPIO/LOANI[15] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX15_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX15. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX15_s +{ + uint32_t sel : 1; /* GPIO/Loan IO15Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX15. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX15_s ALT_SYSMGR_PINMUX_GPLMUX15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX15 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_OFST 0x210 + +/* + * Register : GPIO/LoanIO 16 Output/Output Enable Mux Selection Register - GPLMUX16 + * + * Selection between GPIO and LoanIO output and output enable for GPIO16 and + * LoanIO16. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO16Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO16Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 16. + * + * 0 : LoanIO 16 controls GPIO/LOANIO[16] output and output enable signals. + * + * 1 : GPIO 16 controls GPIO/LOANI[16] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX16_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX16. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX16_s +{ + uint32_t sel : 1; /* GPIO/Loan IO16Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX16. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX16_s ALT_SYSMGR_PINMUX_GPLMUX16_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX16 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_OFST 0x214 + +/* + * Register : GPIO/LoanIO 17 Output/Output Enable Mux Selection Register - GPLMUX17 + * + * Selection between GPIO and LoanIO output and output enable for GPIO17 and + * LoanIO17. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO17Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO17Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 17. + * + * 0 : LoanIO 17 controls GPIO/LOANIO[17] output and output enable signals. + * + * 1 : GPIO 17 controls GPIO/LOANI[17] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX17_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX17. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX17_s +{ + uint32_t sel : 1; /* GPIO/Loan IO17Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX17. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX17_s ALT_SYSMGR_PINMUX_GPLMUX17_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX17 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_OFST 0x218 + +/* + * Register : GPIO/LoanIO 18 Output/Output Enable Mux Selection Register - GPLMUX18 + * + * Selection between GPIO and LoanIO output and output enable for GPIO18 and + * LoanIO18. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO18Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO18Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 18. + * + * 0 : LoanIO 18 controls GPIO/LOANIO[18] output and output enable signals. + * + * 1 : GPIO 18 controls GPIO/LOANI[18] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX18_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX18. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX18_s +{ + uint32_t sel : 1; /* GPIO/Loan IO18Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX18. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX18_s ALT_SYSMGR_PINMUX_GPLMUX18_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX18 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_OFST 0x21c + +/* + * Register : GPIO/LoanIO 19 Output/Output Enable Mux Selection Register - GPLMUX19 + * + * Selection between GPIO and LoanIO output and output enable for GPIO19 and + * LoanIO19. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO19Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO19Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 19. + * + * 0 : LoanIO 19 controls GPIO/LOANIO[19] output and output enable signals. + * + * 1 : GPIO 19 controls GPIO/LOANI[19] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX19_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX19. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX19_s +{ + uint32_t sel : 1; /* GPIO/Loan IO19Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX19. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX19_s ALT_SYSMGR_PINMUX_GPLMUX19_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX19 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_OFST 0x220 + +/* + * Register : GPIO/LoanIO 20 Output/Output Enable Mux Selection Register - GPLMUX20 + * + * Selection between GPIO and LoanIO output and output enable for GPIO20 and + * LoanIO20. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO20Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO20Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 20. + * + * 0 : LoanIO 20 controls GPIO/LOANIO[20] output and output enable signals. + * + * 1 : GPIO 20 controls GPIO/LOANI[20] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX20_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX20. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX20_s +{ + uint32_t sel : 1; /* GPIO/Loan IO20Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX20. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX20_s ALT_SYSMGR_PINMUX_GPLMUX20_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX20 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_OFST 0x224 + +/* + * Register : GPIO/LoanIO 21 Output/Output Enable Mux Selection Register - GPLMUX21 + * + * Selection between GPIO and LoanIO output and output enable for GPIO21 and + * LoanIO21. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO21Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO21Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 21. + * + * 0 : LoanIO 21 controls GPIO/LOANIO[21] output and output enable signals. + * + * 1 : GPIO 21 controls GPIO/LOANI[21] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX21_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX21. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX21_s +{ + uint32_t sel : 1; /* GPIO/Loan IO21Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX21. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX21_s ALT_SYSMGR_PINMUX_GPLMUX21_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX21 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_OFST 0x228 + +/* + * Register : GPIO/LoanIO 22 Output/Output Enable Mux Selection Register - GPLMUX22 + * + * Selection between GPIO and LoanIO output and output enable for GPIO22 and + * LoanIO22. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO22Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO22Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 22. + * + * 0 : LoanIO 22 controls GPIO/LOANIO[22] output and output enable signals. + * + * 1 : GPIO 22 controls GPIO/LOANI[22] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX22_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX22. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX22_s +{ + uint32_t sel : 1; /* GPIO/Loan IO22Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX22. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX22_s ALT_SYSMGR_PINMUX_GPLMUX22_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX22 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_OFST 0x22c + +/* + * Register : GPIO/LoanIO 23 Output/Output Enable Mux Selection Register - GPLMUX23 + * + * Selection between GPIO and LoanIO output and output enable for GPIO23 and + * LoanIO23. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO23Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO23Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 23. + * + * 0 : LoanIO 23 controls GPIO/LOANIO[23] output and output enable signals. + * + * 1 : GPIO 23 controls GPIO/LOANI[23] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX23_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX23. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX23_s +{ + uint32_t sel : 1; /* GPIO/Loan IO23Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX23. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX23_s ALT_SYSMGR_PINMUX_GPLMUX23_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX23 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_OFST 0x230 + +/* + * Register : GPIO/LoanIO 24 Output/Output Enable Mux Selection Register - GPLMUX24 + * + * Selection between GPIO and LoanIO output and output enable for GPIO24 and + * LoanIO24. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO24Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO24Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 24. + * + * 0 : LoanIO 24 controls GPIO/LOANIO[24] output and output enable signals. + * + * 1 : GPIO 24 controls GPIO/LOANI[24] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX24_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX24. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX24_s +{ + uint32_t sel : 1; /* GPIO/Loan IO24Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX24. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX24_s ALT_SYSMGR_PINMUX_GPLMUX24_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX24 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_OFST 0x234 + +/* + * Register : GPIO/LoanIO 25 Output/Output Enable Mux Selection Register - GPLMUX25 + * + * Selection between GPIO and LoanIO output and output enable for GPIO25 and + * LoanIO25. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO25Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO25Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 25. + * + * 0 : LoanIO 25 controls GPIO/LOANIO[25] output and output enable signals. + * + * 1 : GPIO 25 controls GPIO/LOANI[25] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX25_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX25. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX25_s +{ + uint32_t sel : 1; /* GPIO/Loan IO25Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX25. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX25_s ALT_SYSMGR_PINMUX_GPLMUX25_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX25 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_OFST 0x238 + +/* + * Register : GPIO/LoanIO 26 Output/Output Enable Mux Selection Register - GPLMUX26 + * + * Selection between GPIO and LoanIO output and output enable for GPIO26 and + * LoanIO26. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO26Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO26Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 26. + * + * 0 : LoanIO 26 controls GPIO/LOANIO[26] output and output enable signals. + * + * 1 : GPIO 26 controls GPIO/LOANI[26] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX26_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX26. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX26_s +{ + uint32_t sel : 1; /* GPIO/Loan IO26Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX26. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX26_s ALT_SYSMGR_PINMUX_GPLMUX26_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX26 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_OFST 0x23c + +/* + * Register : GPIO/LoanIO 27 Output/Output Enable Mux Selection Register - GPLMUX27 + * + * Selection between GPIO and LoanIO output and output enable for GPIO27 and + * LoanIO27. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO27Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO27Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 27. + * + * 0 : LoanIO 27 controls GPIO/LOANIO[27] output and output enable signals. + * + * 1 : GPIO 27 controls GPIO/LOANI[27] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX27_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX27. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX27_s +{ + uint32_t sel : 1; /* GPIO/Loan IO27Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX27. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX27_s ALT_SYSMGR_PINMUX_GPLMUX27_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX27 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_OFST 0x240 + +/* + * Register : GPIO/LoanIO 28 Output/Output Enable Mux Selection Register - GPLMUX28 + * + * Selection between GPIO and LoanIO output and output enable for GPIO28 and + * LoanIO28. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO28Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO28Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 28. + * + * 0 : LoanIO 28 controls GPIO/LOANIO[28] output and output enable signals. + * + * 1 : GPIO 28 controls GPIO/LOANI[28] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX28_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX28. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX28_s +{ + uint32_t sel : 1; /* GPIO/Loan IO28Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX28. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX28_s ALT_SYSMGR_PINMUX_GPLMUX28_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX28 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_OFST 0x244 + +/* + * Register : GPIO/LoanIO 29 Output/Output Enable Mux Selection Register - GPLMUX29 + * + * Selection between GPIO and LoanIO output and output enable for GPIO29 and + * LoanIO29. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO29Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO29Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 29. + * + * 0 : LoanIO 29 controls GPIO/LOANIO[29] output and output enable signals. + * + * 1 : GPIO 29 controls GPIO/LOANI[29] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX29_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX29. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX29_s +{ + uint32_t sel : 1; /* GPIO/Loan IO29Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX29. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX29_s ALT_SYSMGR_PINMUX_GPLMUX29_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX29 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_OFST 0x248 + +/* + * Register : GPIO/LoanIO 30 Output/Output Enable Mux Selection Register - GPLMUX30 + * + * Selection between GPIO and LoanIO output and output enable for GPIO30 and + * LoanIO30. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO30Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO30Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 30. + * + * 0 : LoanIO 30 controls GPIO/LOANIO[30] output and output enable signals. + * + * 1 : GPIO 30 controls GPIO/LOANI[30] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX30_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX30. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX30_s +{ + uint32_t sel : 1; /* GPIO/Loan IO30Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX30. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX30_s ALT_SYSMGR_PINMUX_GPLMUX30_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX30 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_OFST 0x24c + +/* + * Register : GPIO/LoanIO 31 Output/Output Enable Mux Selection Register - GPLMUX31 + * + * Selection between GPIO and LoanIO output and output enable for GPIO31 and + * LoanIO31. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO31Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO31Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 31. + * + * 0 : LoanIO 31 controls GPIO/LOANIO[31] output and output enable signals. + * + * 1 : GPIO 31 controls GPIO/LOANI[31] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX31_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX31. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX31_s +{ + uint32_t sel : 1; /* GPIO/Loan IO31Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX31. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX31_s ALT_SYSMGR_PINMUX_GPLMUX31_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX31 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_OFST 0x250 + +/* + * Register : GPIO/LoanIO 32 Output/Output Enable Mux Selection Register - GPLMUX32 + * + * Selection between GPIO and LoanIO output and output enable for GPIO32 and + * LoanIO32. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO32Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO32Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 32. + * + * 0 : LoanIO 32 controls GPIO/LOANIO[32] output and output enable signals. + * + * 1 : GPIO 32 controls GPIO/LOANI[32] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX32_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX32. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX32_s +{ + uint32_t sel : 1; /* GPIO/Loan IO32Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX32. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX32_s ALT_SYSMGR_PINMUX_GPLMUX32_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX32 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_OFST 0x254 + +/* + * Register : GPIO/LoanIO 33 Output/Output Enable Mux Selection Register - GPLMUX33 + * + * Selection between GPIO and LoanIO output and output enable for GPIO33 and + * LoanIO33. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO33Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO33Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 33. + * + * 0 : LoanIO 33 controls GPIO/LOANIO[33] output and output enable signals. + * + * 1 : GPIO 33 controls GPIO/LOANI[33] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX33_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX33. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX33_s +{ + uint32_t sel : 1; /* GPIO/Loan IO33Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX33. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX33_s ALT_SYSMGR_PINMUX_GPLMUX33_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX33 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_OFST 0x258 + +/* + * Register : GPIO/LoanIO 34 Output/Output Enable Mux Selection Register - GPLMUX34 + * + * Selection between GPIO and LoanIO output and output enable for GPIO34 and + * LoanIO34. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO34Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO34Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 34. + * + * 0 : LoanIO 34 controls GPIO/LOANIO[34] output and output enable signals. + * + * 1 : GPIO 34 controls GPIO/LOANI[34] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX34_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX34. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX34_s +{ + uint32_t sel : 1; /* GPIO/Loan IO34Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX34. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX34_s ALT_SYSMGR_PINMUX_GPLMUX34_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX34 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_OFST 0x25c + +/* + * Register : GPIO/LoanIO 35 Output/Output Enable Mux Selection Register - GPLMUX35 + * + * Selection between GPIO and LoanIO output and output enable for GPIO35 and + * LoanIO35. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO35Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO35Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 35. + * + * 0 : LoanIO 35 controls GPIO/LOANIO[35] output and output enable signals. + * + * 1 : GPIO 35 controls GPIO/LOANI[35] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX35_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX35. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX35_s +{ + uint32_t sel : 1; /* GPIO/Loan IO35Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX35. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX35_s ALT_SYSMGR_PINMUX_GPLMUX35_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX35 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_OFST 0x260 + +/* + * Register : GPIO/LoanIO 36 Output/Output Enable Mux Selection Register - GPLMUX36 + * + * Selection between GPIO and LoanIO output and output enable for GPIO36 and + * LoanIO36. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO36Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO36Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 36. + * + * 0 : LoanIO 36 controls GPIO/LOANIO[36] output and output enable signals. + * + * 1 : GPIO 36 controls GPIO/LOANI[36] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX36_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX36. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX36_s +{ + uint32_t sel : 1; /* GPIO/Loan IO36Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX36. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX36_s ALT_SYSMGR_PINMUX_GPLMUX36_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX36 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_OFST 0x264 + +/* + * Register : GPIO/LoanIO 37 Output/Output Enable Mux Selection Register - GPLMUX37 + * + * Selection between GPIO and LoanIO output and output enable for GPIO37 and + * LoanIO37. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO37Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO37Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 37. + * + * 0 : LoanIO 37 controls GPIO/LOANIO[37] output and output enable signals. + * + * 1 : GPIO 37 controls GPIO/LOANI[37] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX37_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX37. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX37_s +{ + uint32_t sel : 1; /* GPIO/Loan IO37Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX37. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX37_s ALT_SYSMGR_PINMUX_GPLMUX37_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX37 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_OFST 0x268 + +/* + * Register : GPIO/LoanIO 38 Output/Output Enable Mux Selection Register - GPLMUX38 + * + * Selection between GPIO and LoanIO output and output enable for GPIO38 and + * LoanIO38. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO38Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO38Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 38. + * + * 0 : LoanIO 38 controls GPIO/LOANIO[38] output and output enable signals. + * + * 1 : GPIO 38 controls GPIO/LOANI[38] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX38_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX38. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX38_s +{ + uint32_t sel : 1; /* GPIO/Loan IO38Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX38. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX38_s ALT_SYSMGR_PINMUX_GPLMUX38_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX38 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_OFST 0x26c + +/* + * Register : GPIO/LoanIO 39 Output/Output Enable Mux Selection Register - GPLMUX39 + * + * Selection between GPIO and LoanIO output and output enable for GPIO39 and + * LoanIO39. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO39Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO39Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 39. + * + * 0 : LoanIO 39 controls GPIO/LOANIO[39] output and output enable signals. + * + * 1 : GPIO 39 controls GPIO/LOANI[39] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX39_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX39. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX39_s +{ + uint32_t sel : 1; /* GPIO/Loan IO39Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX39. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX39_s ALT_SYSMGR_PINMUX_GPLMUX39_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX39 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_OFST 0x270 + +/* + * Register : GPIO/LoanIO 40 Output/Output Enable Mux Selection Register - GPLMUX40 + * + * Selection between GPIO and LoanIO output and output enable for GPIO40 and + * LoanIO40. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO40Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO40Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 40. + * + * 0 : LoanIO 40 controls GPIO/LOANIO[40] output and output enable signals. + * + * 1 : GPIO 40 controls GPIO/LOANI[40] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX40_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX40. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX40_s +{ + uint32_t sel : 1; /* GPIO/Loan IO40Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX40. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX40_s ALT_SYSMGR_PINMUX_GPLMUX40_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX40 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_OFST 0x274 + +/* + * Register : GPIO/LoanIO 41 Output/Output Enable Mux Selection Register - GPLMUX41 + * + * Selection between GPIO and LoanIO output and output enable for GPIO41 and + * LoanIO41. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO41Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO41Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 41. + * + * 0 : LoanIO 41 controls GPIO/LOANIO[41] output and output enable signals. + * + * 1 : GPIO 41 controls GPIO/LOANI[41] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX41_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX41. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX41_s +{ + uint32_t sel : 1; /* GPIO/Loan IO41Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX41. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX41_s ALT_SYSMGR_PINMUX_GPLMUX41_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX41 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_OFST 0x278 + +/* + * Register : GPIO/LoanIO 42 Output/Output Enable Mux Selection Register - GPLMUX42 + * + * Selection between GPIO and LoanIO output and output enable for GPIO42 and + * LoanIO42. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO42Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO42Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 42. + * + * 0 : LoanIO 42 controls GPIO/LOANIO[42] output and output enable signals. + * + * 1 : GPIO 42 controls GPIO/LOANI[42] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX42_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX42. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX42_s +{ + uint32_t sel : 1; /* GPIO/Loan IO42Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX42. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX42_s ALT_SYSMGR_PINMUX_GPLMUX42_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX42 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_OFST 0x27c + +/* + * Register : GPIO/LoanIO 43 Output/Output Enable Mux Selection Register - GPLMUX43 + * + * Selection between GPIO and LoanIO output and output enable for GPIO43 and + * LoanIO43. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO43Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO43Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 43. + * + * 0 : LoanIO 43 controls GPIO/LOANIO[43] output and output enable signals. + * + * 1 : GPIO 43 controls GPIO/LOANI[43] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX43_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX43. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX43_s +{ + uint32_t sel : 1; /* GPIO/Loan IO43Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX43. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX43_s ALT_SYSMGR_PINMUX_GPLMUX43_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX43 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_OFST 0x280 + +/* + * Register : GPIO/LoanIO 44 Output/Output Enable Mux Selection Register - GPLMUX44 + * + * Selection between GPIO and LoanIO output and output enable for GPIO44 and + * LoanIO44. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO44Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO44Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 44. + * + * 0 : LoanIO 44 controls GPIO/LOANIO[44] output and output enable signals. + * + * 1 : GPIO 44 controls GPIO/LOANI[44] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX44_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX44. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX44_s +{ + uint32_t sel : 1; /* GPIO/Loan IO44Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX44. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX44_s ALT_SYSMGR_PINMUX_GPLMUX44_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX44 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_OFST 0x284 + +/* + * Register : GPIO/LoanIO 45 Output/Output Enable Mux Selection Register - GPLMUX45 + * + * Selection between GPIO and LoanIO output and output enable for GPIO45 and + * LoanIO45. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO45Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO45Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 45. + * + * 0 : LoanIO 45 controls GPIO/LOANIO[45] output and output enable signals. + * + * 1 : GPIO 45 controls GPIO/LOANI[45] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX45_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX45. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX45_s +{ + uint32_t sel : 1; /* GPIO/Loan IO45Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX45. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX45_s ALT_SYSMGR_PINMUX_GPLMUX45_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX45 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_OFST 0x288 + +/* + * Register : GPIO/LoanIO 46 Output/Output Enable Mux Selection Register - GPLMUX46 + * + * Selection between GPIO and LoanIO output and output enable for GPIO46 and + * LoanIO46. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO46Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO46Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 46. + * + * 0 : LoanIO 46 controls GPIO/LOANIO[46] output and output enable signals. + * + * 1 : GPIO 46 controls GPIO/LOANI[46] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX46_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX46. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX46_s +{ + uint32_t sel : 1; /* GPIO/Loan IO46Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX46. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX46_s ALT_SYSMGR_PINMUX_GPLMUX46_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX46 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_OFST 0x28c + +/* + * Register : GPIO/LoanIO 47 Output/Output Enable Mux Selection Register - GPLMUX47 + * + * Selection between GPIO and LoanIO output and output enable for GPIO47 and + * LoanIO47. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO47Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO47Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 47. + * + * 0 : LoanIO 47 controls GPIO/LOANIO[47] output and output enable signals. + * + * 1 : GPIO 47 controls GPIO/LOANI[47] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX47_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX47. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX47_s +{ + uint32_t sel : 1; /* GPIO/Loan IO47Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX47. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX47_s ALT_SYSMGR_PINMUX_GPLMUX47_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX47 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_OFST 0x290 + +/* + * Register : GPIO/LoanIO 48 Output/Output Enable Mux Selection Register - GPLMUX48 + * + * Selection between GPIO and LoanIO output and output enable for GPIO48 and + * LoanIO48. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO48Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO48Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 48. + * + * 0 : LoanIO 48 controls GPIO/LOANIO[48] output and output enable signals. + * + * 1 : GPIO 48 controls GPIO/LOANI[48] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX48_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX48. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX48_s +{ + uint32_t sel : 1; /* GPIO/Loan IO48Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX48. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX48_s ALT_SYSMGR_PINMUX_GPLMUX48_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX48 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_OFST 0x294 + +/* + * Register : GPIO/LoanIO 49 Output/Output Enable Mux Selection Register - GPLMUX49 + * + * Selection between GPIO and LoanIO output and output enable for GPIO49 and + * LoanIO49. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO49Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO49Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 49. + * + * 0 : LoanIO 49 controls GPIO/LOANIO[49] output and output enable signals. + * + * 1 : GPIO 49 controls GPIO/LOANI[49] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX49_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX49. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX49_s +{ + uint32_t sel : 1; /* GPIO/Loan IO49Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX49. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX49_s ALT_SYSMGR_PINMUX_GPLMUX49_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX49 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_OFST 0x298 + +/* + * Register : GPIO/LoanIO 50 Output/Output Enable Mux Selection Register - GPLMUX50 + * + * Selection between GPIO and LoanIO output and output enable for GPIO50 and + * LoanIO50. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO50Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO50Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 50. + * + * 0 : LoanIO 50 controls GPIO/LOANIO[50] output and output enable signals. + * + * 1 : GPIO 50 controls GPIO/LOANI[50] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX50_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX50. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX50_s +{ + uint32_t sel : 1; /* GPIO/Loan IO50Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX50. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX50_s ALT_SYSMGR_PINMUX_GPLMUX50_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX50 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_OFST 0x29c + +/* + * Register : GPIO/LoanIO 51 Output/Output Enable Mux Selection Register - GPLMUX51 + * + * Selection between GPIO and LoanIO output and output enable for GPIO51 and + * LoanIO51. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO51Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO51Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 51. + * + * 0 : LoanIO 51 controls GPIO/LOANIO[51] output and output enable signals. + * + * 1 : GPIO 51 controls GPIO/LOANI[51] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX51_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX51. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX51_s +{ + uint32_t sel : 1; /* GPIO/Loan IO51Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX51. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX51_s ALT_SYSMGR_PINMUX_GPLMUX51_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX51 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_OFST 0x2a0 + +/* + * Register : GPIO/LoanIO 52 Output/Output Enable Mux Selection Register - GPLMUX52 + * + * Selection between GPIO and LoanIO output and output enable for GPIO52 and + * LoanIO52. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO52Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO52Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 52. + * + * 0 : LoanIO 52 controls GPIO/LOANIO[52] output and output enable signals. + * + * 1 : GPIO 52 controls GPIO/LOANI[52] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX52_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX52. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX52_s +{ + uint32_t sel : 1; /* GPIO/Loan IO52Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX52. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX52_s ALT_SYSMGR_PINMUX_GPLMUX52_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX52 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_OFST 0x2a4 + +/* + * Register : GPIO/LoanIO 53 Output/Output Enable Mux Selection Register - GPLMUX53 + * + * Selection between GPIO and LoanIO output and output enable for GPIO53 and + * LoanIO53. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO53Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO53Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 53. + * + * 0 : LoanIO 53 controls GPIO/LOANIO[53] output and output enable signals. + * + * 1 : GPIO 53 controls GPIO/LOANI[53] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX53_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX53. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX53_s +{ + uint32_t sel : 1; /* GPIO/Loan IO53Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX53. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX53_s ALT_SYSMGR_PINMUX_GPLMUX53_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX53 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_OFST 0x2a8 + +/* + * Register : GPIO/LoanIO 54 Output/Output Enable Mux Selection Register - GPLMUX54 + * + * Selection between GPIO and LoanIO output and output enable for GPIO54 and + * LoanIO54. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO54Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO54Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 54. + * + * 0 : LoanIO 54 controls GPIO/LOANIO[54] output and output enable signals. + * + * 1 : GPIO 54 controls GPIO/LOANI[54] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX54_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX54. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX54_s +{ + uint32_t sel : 1; /* GPIO/Loan IO54Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX54. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX54_s ALT_SYSMGR_PINMUX_GPLMUX54_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX54 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_OFST 0x2ac + +/* + * Register : GPIO/LoanIO 55 Output/Output Enable Mux Selection Register - GPLMUX55 + * + * Selection between GPIO and LoanIO output and output enable for GPIO55 and + * LoanIO55. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO55Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO55Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 55. + * + * 0 : LoanIO 55 controls GPIO/LOANIO[55] output and output enable signals. + * + * 1 : GPIO 55 controls GPIO/LOANI[55] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX55_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX55. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX55_s +{ + uint32_t sel : 1; /* GPIO/Loan IO55Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX55. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX55_s ALT_SYSMGR_PINMUX_GPLMUX55_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX55 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_OFST 0x2b0 + +/* + * Register : GPIO/LoanIO 56 Output/Output Enable Mux Selection Register - GPLMUX56 + * + * Selection between GPIO and LoanIO output and output enable for GPIO56 and + * LoanIO56. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO56Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO56Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 56. + * + * 0 : LoanIO 56 controls GPIO/LOANIO[56] output and output enable signals. + * + * 1 : GPIO 56 controls GPIO/LOANI[56] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX56_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX56. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX56_s +{ + uint32_t sel : 1; /* GPIO/Loan IO56Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX56. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX56_s ALT_SYSMGR_PINMUX_GPLMUX56_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX56 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_OFST 0x2b4 + +/* + * Register : GPIO/LoanIO 57 Output/Output Enable Mux Selection Register - GPLMUX57 + * + * Selection between GPIO and LoanIO output and output enable for GPIO57 and + * LoanIO57. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO57Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO57Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 57. + * + * 0 : LoanIO 57 controls GPIO/LOANIO[57] output and output enable signals. + * + * 1 : GPIO 57 controls GPIO/LOANI[57] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX57_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX57. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX57_s +{ + uint32_t sel : 1; /* GPIO/Loan IO57Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX57. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX57_s ALT_SYSMGR_PINMUX_GPLMUX57_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX57 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_OFST 0x2b8 + +/* + * Register : GPIO/LoanIO 58 Output/Output Enable Mux Selection Register - GPLMUX58 + * + * Selection between GPIO and LoanIO output and output enable for GPIO58 and + * LoanIO58. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO58Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO58Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 58. + * + * 0 : LoanIO 58 controls GPIO/LOANIO[58] output and output enable signals. + * + * 1 : GPIO 58 controls GPIO/LOANI[58] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX58_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX58. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX58_s +{ + uint32_t sel : 1; /* GPIO/Loan IO58Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX58. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX58_s ALT_SYSMGR_PINMUX_GPLMUX58_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX58 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_OFST 0x2bc + +/* + * Register : GPIO/LoanIO 59 Output/Output Enable Mux Selection Register - GPLMUX59 + * + * Selection between GPIO and LoanIO output and output enable for GPIO59 and + * LoanIO59. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO59Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO59Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 59. + * + * 0 : LoanIO 59 controls GPIO/LOANIO[59] output and output enable signals. + * + * 1 : GPIO 59 controls GPIO/LOANI[59] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX59_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX59. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX59_s +{ + uint32_t sel : 1; /* GPIO/Loan IO59Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX59. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX59_s ALT_SYSMGR_PINMUX_GPLMUX59_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX59 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_OFST 0x2c0 + +/* + * Register : GPIO/LoanIO 60 Output/Output Enable Mux Selection Register - GPLMUX60 + * + * Selection between GPIO and LoanIO output and output enable for GPIO60 and + * LoanIO60. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO60Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO60Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 60. + * + * 0 : LoanIO 60 controls GPIO/LOANIO[60] output and output enable signals. + * + * 1 : GPIO 60 controls GPIO/LOANI[60] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX60_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX60. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX60_s +{ + uint32_t sel : 1; /* GPIO/Loan IO60Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX60. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX60_s ALT_SYSMGR_PINMUX_GPLMUX60_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX60 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_OFST 0x2c4 + +/* + * Register : GPIO/LoanIO 61 Output/Output Enable Mux Selection Register - GPLMUX61 + * + * Selection between GPIO and LoanIO output and output enable for GPIO61 and + * LoanIO61. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO61Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO61Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 61. + * + * 0 : LoanIO 61 controls GPIO/LOANIO[61] output and output enable signals. + * + * 1 : GPIO 61 controls GPIO/LOANI[61] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX61_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX61. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX61_s +{ + uint32_t sel : 1; /* GPIO/Loan IO61Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX61. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX61_s ALT_SYSMGR_PINMUX_GPLMUX61_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX61 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_OFST 0x2c8 + +/* + * Register : GPIO/LoanIO 62 Output/Output Enable Mux Selection Register - GPLMUX62 + * + * Selection between GPIO and LoanIO output and output enable for GPIO62 and + * LoanIO62. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO62Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO62Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 62. + * + * 0 : LoanIO 62 controls GPIO/LOANIO[62] output and output enable signals. + * + * 1 : GPIO 62 controls GPIO/LOANI[62] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX62_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX62. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX62_s +{ + uint32_t sel : 1; /* GPIO/Loan IO62Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX62. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX62_s ALT_SYSMGR_PINMUX_GPLMUX62_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX62 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_OFST 0x2cc + +/* + * Register : GPIO/LoanIO 63 Output/Output Enable Mux Selection Register - GPLMUX63 + * + * Selection between GPIO and LoanIO output and output enable for GPIO63 and + * LoanIO63. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO63Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO63Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 63. + * + * 0 : LoanIO 63 controls GPIO/LOANIO[63] output and output enable signals. + * + * 1 : GPIO 63 controls GPIO/LOANI[63] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX63_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX63. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX63_s +{ + uint32_t sel : 1; /* GPIO/Loan IO63Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX63. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX63_s ALT_SYSMGR_PINMUX_GPLMUX63_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX63 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_OFST 0x2d0 + +/* + * Register : GPIO/LoanIO 64 Output/Output Enable Mux Selection Register - GPLMUX64 + * + * Selection between GPIO and LoanIO output and output enable for GPIO64 and + * LoanIO64. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO64Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO64Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 64. + * + * 0 : LoanIO 64 controls GPIO/LOANIO[64] output and output enable signals. + * + * 1 : GPIO 64 controls GPIO/LOANI[64] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX64_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX64. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX64_s +{ + uint32_t sel : 1; /* GPIO/Loan IO64Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX64. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX64_s ALT_SYSMGR_PINMUX_GPLMUX64_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX64 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_OFST 0x2d4 + +/* + * Register : GPIO/LoanIO 65 Output/Output Enable Mux Selection Register - GPLMUX65 + * + * Selection between GPIO and LoanIO output and output enable for GPIO65 and + * LoanIO65. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO65Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO65Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 65. + * + * 0 : LoanIO 65 controls GPIO/LOANIO[65] output and output enable signals. + * + * 1 : GPIO 65 controls GPIO/LOANI[65] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX65_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX65. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX65_s +{ + uint32_t sel : 1; /* GPIO/Loan IO65Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX65. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX65_s ALT_SYSMGR_PINMUX_GPLMUX65_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX65 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_OFST 0x2d8 + +/* + * Register : GPIO/LoanIO 66 Output/Output Enable Mux Selection Register - GPLMUX66 + * + * Selection between GPIO and LoanIO output and output enable for GPIO66 and + * LoanIO66. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO66Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO66Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 66. + * + * 0 : LoanIO 66 controls GPIO/LOANIO[66] output and output enable signals. + * + * 1 : GPIO 66 controls GPIO/LOANI[66] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX66_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX66. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX66_s +{ + uint32_t sel : 1; /* GPIO/Loan IO66Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX66. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX66_s ALT_SYSMGR_PINMUX_GPLMUX66_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX66 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_OFST 0x2dc + +/* + * Register : GPIO/LoanIO 67 Output/Output Enable Mux Selection Register - GPLMUX67 + * + * Selection between GPIO and LoanIO output and output enable for GPIO67 and + * LoanIO67. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO67Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO67Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 67. + * + * 0 : LoanIO 67 controls GPIO/LOANIO[67] output and output enable signals. + * + * 1 : GPIO 67 controls GPIO/LOANI[67] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX67_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX67. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX67_s +{ + uint32_t sel : 1; /* GPIO/Loan IO67Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX67. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX67_s ALT_SYSMGR_PINMUX_GPLMUX67_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX67 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_OFST 0x2e0 + +/* + * Register : GPIO/LoanIO 68 Output/Output Enable Mux Selection Register - GPLMUX68 + * + * Selection between GPIO and LoanIO output and output enable for GPIO68 and + * LoanIO68. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO68Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO68Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 68. + * + * 0 : LoanIO 68 controls GPIO/LOANIO[68] output and output enable signals. + * + * 1 : GPIO 68 controls GPIO/LOANI[68] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX68_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX68. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX68_s +{ + uint32_t sel : 1; /* GPIO/Loan IO68Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX68. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX68_s ALT_SYSMGR_PINMUX_GPLMUX68_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX68 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_OFST 0x2e4 + +/* + * Register : GPIO/LoanIO 69 Output/Output Enable Mux Selection Register - GPLMUX69 + * + * Selection between GPIO and LoanIO output and output enable for GPIO69 and + * LoanIO69. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO69Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO69Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 69. + * + * 0 : LoanIO 69 controls GPIO/LOANIO[69] output and output enable signals. + * + * 1 : GPIO 69 controls GPIO/LOANI[69] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX69_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX69. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX69_s +{ + uint32_t sel : 1; /* GPIO/Loan IO69Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX69. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX69_s ALT_SYSMGR_PINMUX_GPLMUX69_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX69 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_OFST 0x2e8 + +/* + * Register : GPIO/LoanIO 70 Output/Output Enable Mux Selection Register - GPLMUX70 + * + * Selection between GPIO and LoanIO output and output enable for GPIO70 and + * LoanIO70. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO70Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO70Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 70. + * + * 0 : LoanIO 70 controls GPIO/LOANIO[70] output and output enable signals. + * + * 1 : GPIO 70 controls GPIO/LOANI[70] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX70_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX70. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX70_s +{ + uint32_t sel : 1; /* GPIO/Loan IO70Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX70. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX70_s ALT_SYSMGR_PINMUX_GPLMUX70_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX70 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_OFST 0x2ec + +/* + * Register : Select source for NAND signals (HPS Pins or FPGA Interface) - NANDUSEFPGA + * + * Selection between HPS Pins and FPGA Interface for NAND signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for NAND signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for NAND signals - sel + * + * Select connection for NAND. + * + * 0 : NAND uses HPS Pins. + * + * 1 : NAND uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_NANDUSEFPGA. + */ +struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s +{ + uint32_t sel : 1; /* Selection for NAND signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_NANDUSEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s ALT_SYSMGR_PINMUX_NANDUSEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_NANDUSEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_OFST 0x2f0 + +/* + * Register : Select source for RGMII1 signals (HPS Pins or FPGA Interface) - RGMII1USEFPGA + * + * Selection between HPS Pins and FPGA Interface for RGMII1 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | RW | 0x0 | Selection for RGMII1 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for RGMII1 signals - sel + * + * Select connection for RGMII1. + * + * 0 : RGMII1 uses HPS Pins. + * + * 1 : RGMII1 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_RGMII1USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s +{ + uint32_t sel : 1; /* Selection for RGMII1 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_RGMII1USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_OFST 0x2f8 + +/* + * Register : Select source for I2C0 signals (HPS Pins or FPGA Interface) - I2C0USEFPGA + * + * Selection between HPS Pins and FPGA Interface for I2C0 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for I2C0 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for I2C0 signals - sel + * + * Select connection for I2C0. + * + * 0 : I2C0 uses HPS Pins. + * + * 1 : I2C0 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_I2C0USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s +{ + uint32_t sel : 1; /* Selection for I2C0 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C0USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s ALT_SYSMGR_PINMUX_I2C0USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_I2C0USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_OFST 0x304 + +/* + * Register : Select source for RGMII0 signals (HPS Pins or FPGA Interface) - RGMII0USEFPGA + * + * Selection between HPS Pins and FPGA Interface for RGMII0 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | RW | 0x0 | Selection for RGMII0 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for RGMII0 signals - sel + * + * Select connection for RGMII0. + * + * 0 : RGMII0 uses HPS Pins. + * + * 1 : RGMII0 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_RGMII0USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s +{ + uint32_t sel : 1; /* Selection for RGMII0 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_RGMII0USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_OFST 0x314 + +/* + * Register : Select source for I2C3 signals (HPS Pins or FPGA Interface) - I2C3USEFPGA + * + * Selection between HPS Pins and FPGA Interface for I2C3 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for I2C3 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for I2C3 signals - sel + * + * Select connection for I2C3. + * + * 0 : I2C3 uses HPS Pins. + * + * 1 : I2C3 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_I2C3USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s +{ + uint32_t sel : 1; /* Selection for I2C3 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C3USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s ALT_SYSMGR_PINMUX_I2C3USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_I2C3USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_OFST 0x324 + +/* + * Register : Select source for I2C2 signals (HPS Pins or FPGA Interface) - I2C2USEFPGA + * + * Selection between HPS Pins and FPGA Interface for I2C2 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for I2C2 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for I2C2 signals - sel + * + * Select connection for I2C2. + * + * 0 : I2C2 uses HPS Pins. + * + * 1 : I2C2 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_I2C2USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s +{ + uint32_t sel : 1; /* Selection for I2C2 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C2USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s ALT_SYSMGR_PINMUX_I2C2USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_I2C2USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_OFST 0x328 + +/* + * Register : Select source for I2C1 signals (HPS Pins or FPGA Interface) - I2C1USEFPGA + * + * Selection between HPS Pins and FPGA Interface for I2C1 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for I2C1 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for I2C1 signals - sel + * + * Select connection for I2C1. + * + * 0 : I2C1 uses HPS Pins. + * + * 1 : I2C1 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_I2C1USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s +{ + uint32_t sel : 1; /* Selection for I2C1 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C1USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s ALT_SYSMGR_PINMUX_I2C1USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_I2C1USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_OFST 0x32c + +/* + * Register : Select source for SPIM1 signals (HPS Pins or FPGA Interface) - SPIM1USEFPGA + * + * Selection between HPS Pins and FPGA Interface for SPIM1 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [0] | RW | 0x0 | Selection for SPIM1 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for SPIM1 signals - sel + * + * Select connection for SPIM1. + * + * 0 : SPIM1 uses HPS Pins. + * + * 1 : SPIM1 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_SPIM1USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s +{ + uint32_t sel : 1; /* Selection for SPIM1 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_SPIM1USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_OFST 0x330 + +/* + * Register : Select source for SPIM0 signals (HPS Pins or FPGA Interface) - SPIM0USEFPGA + * + * Selection between HPS Pins and FPGA Interface for SPIM0 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [0] | RW | 0x0 | Selection for SPIM0 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for SPIM0 signals - sel + * + * Select connection for SPIM0. + * + * 0 : SPIM0 uses HPS Pins. + * + * 1 : SPIM0 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_SPIM0USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s +{ + uint32_t sel : 1; /* Selection for SPIM0 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_SPIM0USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_OFST 0x338 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_PINMUX. + */ +struct ALT_SYSMGR_PINMUX_s +{ + volatile ALT_SYSMGR_PINMUX_EMACIO0_t EMACIO0; /* ALT_SYSMGR_PINMUX_EMACIO0 */ + volatile ALT_SYSMGR_PINMUX_EMACIO1_t EMACIO1; /* ALT_SYSMGR_PINMUX_EMACIO1 */ + volatile ALT_SYSMGR_PINMUX_EMACIO2_t EMACIO2; /* ALT_SYSMGR_PINMUX_EMACIO2 */ + volatile ALT_SYSMGR_PINMUX_EMACIO3_t EMACIO3; /* ALT_SYSMGR_PINMUX_EMACIO3 */ + volatile ALT_SYSMGR_PINMUX_EMACIO4_t EMACIO4; /* ALT_SYSMGR_PINMUX_EMACIO4 */ + volatile ALT_SYSMGR_PINMUX_EMACIO5_t EMACIO5; /* ALT_SYSMGR_PINMUX_EMACIO5 */ + volatile ALT_SYSMGR_PINMUX_EMACIO6_t EMACIO6; /* ALT_SYSMGR_PINMUX_EMACIO6 */ + volatile ALT_SYSMGR_PINMUX_EMACIO7_t EMACIO7; /* ALT_SYSMGR_PINMUX_EMACIO7 */ + volatile ALT_SYSMGR_PINMUX_EMACIO8_t EMACIO8; /* ALT_SYSMGR_PINMUX_EMACIO8 */ + volatile ALT_SYSMGR_PINMUX_EMACIO9_t EMACIO9; /* ALT_SYSMGR_PINMUX_EMACIO9 */ + volatile ALT_SYSMGR_PINMUX_EMACIO10_t EMACIO10; /* ALT_SYSMGR_PINMUX_EMACIO10 */ + volatile ALT_SYSMGR_PINMUX_EMACIO11_t EMACIO11; /* ALT_SYSMGR_PINMUX_EMACIO11 */ + volatile ALT_SYSMGR_PINMUX_EMACIO12_t EMACIO12; /* ALT_SYSMGR_PINMUX_EMACIO12 */ + volatile ALT_SYSMGR_PINMUX_EMACIO13_t EMACIO13; /* ALT_SYSMGR_PINMUX_EMACIO13 */ + volatile ALT_SYSMGR_PINMUX_EMACIO14_t EMACIO14; /* ALT_SYSMGR_PINMUX_EMACIO14 */ + volatile ALT_SYSMGR_PINMUX_EMACIO15_t EMACIO15; /* ALT_SYSMGR_PINMUX_EMACIO15 */ + volatile ALT_SYSMGR_PINMUX_EMACIO16_t EMACIO16; /* ALT_SYSMGR_PINMUX_EMACIO16 */ + volatile ALT_SYSMGR_PINMUX_EMACIO17_t EMACIO17; /* ALT_SYSMGR_PINMUX_EMACIO17 */ + volatile ALT_SYSMGR_PINMUX_EMACIO18_t EMACIO18; /* ALT_SYSMGR_PINMUX_EMACIO18 */ + volatile ALT_SYSMGR_PINMUX_EMACIO19_t EMACIO19; /* ALT_SYSMGR_PINMUX_EMACIO19 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO0_t FLASHIO0; /* ALT_SYSMGR_PINMUX_FLSHIO0 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO1_t FLASHIO1; /* ALT_SYSMGR_PINMUX_FLSHIO1 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO2_t FLASHIO2; /* ALT_SYSMGR_PINMUX_FLSHIO2 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO3_t FLASHIO3; /* ALT_SYSMGR_PINMUX_FLSHIO3 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO4_t FLASHIO4; /* ALT_SYSMGR_PINMUX_FLSHIO4 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO5_t FLASHIO5; /* ALT_SYSMGR_PINMUX_FLSHIO5 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO6_t FLASHIO6; /* ALT_SYSMGR_PINMUX_FLSHIO6 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO7_t FLASHIO7; /* ALT_SYSMGR_PINMUX_FLSHIO7 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO8_t FLASHIO8; /* ALT_SYSMGR_PINMUX_FLSHIO8 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO9_t FLASHIO9; /* ALT_SYSMGR_PINMUX_FLSHIO9 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO10_t FLASHIO10; /* ALT_SYSMGR_PINMUX_FLSHIO10 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO11_t FLASHIO11; /* ALT_SYSMGR_PINMUX_FLSHIO11 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO0_t GENERALIO0; /* ALT_SYSMGR_PINMUX_GENERALIO0 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO1_t GENERALIO1; /* ALT_SYSMGR_PINMUX_GENERALIO1 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO2_t GENERALIO2; /* ALT_SYSMGR_PINMUX_GENERALIO2 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO3_t GENERALIO3; /* ALT_SYSMGR_PINMUX_GENERALIO3 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO4_t GENERALIO4; /* ALT_SYSMGR_PINMUX_GENERALIO4 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO5_t GENERALIO5; /* ALT_SYSMGR_PINMUX_GENERALIO5 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO6_t GENERALIO6; /* ALT_SYSMGR_PINMUX_GENERALIO6 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO7_t GENERALIO7; /* ALT_SYSMGR_PINMUX_GENERALIO7 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO8_t GENERALIO8; /* ALT_SYSMGR_PINMUX_GENERALIO8 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO9_t GENERALIO9; /* ALT_SYSMGR_PINMUX_GENERALIO9 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO10_t GENERALIO10; /* ALT_SYSMGR_PINMUX_GENERALIO10 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO11_t GENERALIO11; /* ALT_SYSMGR_PINMUX_GENERALIO11 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO12_t GENERALIO12; /* ALT_SYSMGR_PINMUX_GENERALIO12 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO13_t GENERALIO13; /* ALT_SYSMGR_PINMUX_GENERALIO13 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO14_t GENERALIO14; /* ALT_SYSMGR_PINMUX_GENERALIO14 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO15_t GENERALIO15; /* ALT_SYSMGR_PINMUX_GENERALIO15 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO16_t GENERALIO16; /* ALT_SYSMGR_PINMUX_GENERALIO16 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO17_t GENERALIO17; /* ALT_SYSMGR_PINMUX_GENERALIO17 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO18_t GENERALIO18; /* ALT_SYSMGR_PINMUX_GENERALIO18 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO19_t GENERALIO19; /* ALT_SYSMGR_PINMUX_GENERALIO19 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO20_t GENERALIO20; /* ALT_SYSMGR_PINMUX_GENERALIO20 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO21_t GENERALIO21; /* ALT_SYSMGR_PINMUX_GENERALIO21 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO22_t GENERALIO22; /* ALT_SYSMGR_PINMUX_GENERALIO22 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO23_t GENERALIO23; /* ALT_SYSMGR_PINMUX_GENERALIO23 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO24_t GENERALIO24; /* ALT_SYSMGR_PINMUX_GENERALIO24 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO25_t GENERALIO25; /* ALT_SYSMGR_PINMUX_GENERALIO25 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO26_t GENERALIO26; /* ALT_SYSMGR_PINMUX_GENERALIO26 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO27_t GENERALIO27; /* ALT_SYSMGR_PINMUX_GENERALIO27 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO28_t GENERALIO28; /* ALT_SYSMGR_PINMUX_GENERALIO28 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO29_t GENERALIO29; /* ALT_SYSMGR_PINMUX_GENERALIO29 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO30_t GENERALIO30; /* ALT_SYSMGR_PINMUX_GENERALIO30 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO31_t GENERALIO31; /* ALT_SYSMGR_PINMUX_GENERALIO31 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO0_t MIXED1IO0; /* ALT_SYSMGR_PINMUX_MIXED1IO0 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO1_t MIXED1IO1; /* ALT_SYSMGR_PINMUX_MIXED1IO1 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO2_t MIXED1IO2; /* ALT_SYSMGR_PINMUX_MIXED1IO2 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO3_t MIXED1IO3; /* ALT_SYSMGR_PINMUX_MIXED1IO3 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO4_t MIXED1IO4; /* ALT_SYSMGR_PINMUX_MIXED1IO4 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO5_t MIXED1IO5; /* ALT_SYSMGR_PINMUX_MIXED1IO5 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO6_t MIXED1IO6; /* ALT_SYSMGR_PINMUX_MIXED1IO6 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO7_t MIXED1IO7; /* ALT_SYSMGR_PINMUX_MIXED1IO7 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO8_t MIXED1IO8; /* ALT_SYSMGR_PINMUX_MIXED1IO8 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO9_t MIXED1IO9; /* ALT_SYSMGR_PINMUX_MIXED1IO9 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO10_t MIXED1IO10; /* ALT_SYSMGR_PINMUX_MIXED1IO10 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO11_t MIXED1IO11; /* ALT_SYSMGR_PINMUX_MIXED1IO11 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO12_t MIXED1IO12; /* ALT_SYSMGR_PINMUX_MIXED1IO12 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO13_t MIXED1IO13; /* ALT_SYSMGR_PINMUX_MIXED1IO13 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO14_t MIXED1IO14; /* ALT_SYSMGR_PINMUX_MIXED1IO14 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO15_t MIXED1IO15; /* ALT_SYSMGR_PINMUX_MIXED1IO15 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO16_t MIXED1IO16; /* ALT_SYSMGR_PINMUX_MIXED1IO16 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO17_t MIXED1IO17; /* ALT_SYSMGR_PINMUX_MIXED1IO17 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO18_t MIXED1IO18; /* ALT_SYSMGR_PINMUX_MIXED1IO18 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO19_t MIXED1IO19; /* ALT_SYSMGR_PINMUX_MIXED1IO19 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO20_t MIXED1IO20; /* ALT_SYSMGR_PINMUX_MIXED1IO20 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO21_t MIXED1IO21; /* ALT_SYSMGR_PINMUX_MIXED1IO21 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO0_t MIXED2IO0; /* ALT_SYSMGR_PINMUX_MIXED2IO0 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO1_t MIXED2IO1; /* ALT_SYSMGR_PINMUX_MIXED2IO1 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO2_t MIXED2IO2; /* ALT_SYSMGR_PINMUX_MIXED2IO2 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO3_t MIXED2IO3; /* ALT_SYSMGR_PINMUX_MIXED2IO3 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO4_t MIXED2IO4; /* ALT_SYSMGR_PINMUX_MIXED2IO4 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO5_t MIXED2IO5; /* ALT_SYSMGR_PINMUX_MIXED2IO5 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO6_t MIXED2IO6; /* ALT_SYSMGR_PINMUX_MIXED2IO6 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO7_t MIXED2IO7; /* ALT_SYSMGR_PINMUX_MIXED2IO7 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX48_t GPLINMUX48; /* ALT_SYSMGR_PINMUX_GPLINMUX48 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX49_t GPLINMUX49; /* ALT_SYSMGR_PINMUX_GPLINMUX49 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX50_t GPLINMUX50; /* ALT_SYSMGR_PINMUX_GPLINMUX50 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX51_t GPLINMUX51; /* ALT_SYSMGR_PINMUX_GPLINMUX51 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX52_t GPLINMUX52; /* ALT_SYSMGR_PINMUX_GPLINMUX52 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX53_t GPLINMUX53; /* ALT_SYSMGR_PINMUX_GPLINMUX53 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX54_t GPLINMUX54; /* ALT_SYSMGR_PINMUX_GPLINMUX54 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX55_t GPLINMUX55; /* ALT_SYSMGR_PINMUX_GPLINMUX55 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX56_t GPLINMUX56; /* ALT_SYSMGR_PINMUX_GPLINMUX56 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX57_t GPLINMUX57; /* ALT_SYSMGR_PINMUX_GPLINMUX57 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX58_t GPLINMUX58; /* ALT_SYSMGR_PINMUX_GPLINMUX58 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX59_t GPLINMUX59; /* ALT_SYSMGR_PINMUX_GPLINMUX59 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX60_t GPLINMUX60; /* ALT_SYSMGR_PINMUX_GPLINMUX60 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX61_t GPLINMUX61; /* ALT_SYSMGR_PINMUX_GPLINMUX61 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX62_t GPLINMUX62; /* ALT_SYSMGR_PINMUX_GPLINMUX62 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX63_t GPLINMUX63; /* ALT_SYSMGR_PINMUX_GPLINMUX63 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX64_t GPLINMUX64; /* ALT_SYSMGR_PINMUX_GPLINMUX64 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX65_t GPLINMUX65; /* ALT_SYSMGR_PINMUX_GPLINMUX65 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX66_t GPLINMUX66; /* ALT_SYSMGR_PINMUX_GPLINMUX66 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX67_t GPLINMUX67; /* ALT_SYSMGR_PINMUX_GPLINMUX67 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX68_t GPLINMUX68; /* ALT_SYSMGR_PINMUX_GPLINMUX68 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX69_t GPLINMUX69; /* ALT_SYSMGR_PINMUX_GPLINMUX69 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX70_t GPLINMUX70; /* ALT_SYSMGR_PINMUX_GPLINMUX70 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX0_t GPLMUX0; /* ALT_SYSMGR_PINMUX_GPLMUX0 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX1_t GPLMUX1; /* ALT_SYSMGR_PINMUX_GPLMUX1 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX2_t GPLMUX2; /* ALT_SYSMGR_PINMUX_GPLMUX2 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX3_t GPLMUX3; /* ALT_SYSMGR_PINMUX_GPLMUX3 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX4_t GPLMUX4; /* ALT_SYSMGR_PINMUX_GPLMUX4 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX5_t GPLMUX5; /* ALT_SYSMGR_PINMUX_GPLMUX5 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX6_t GPLMUX6; /* ALT_SYSMGR_PINMUX_GPLMUX6 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX7_t GPLMUX7; /* ALT_SYSMGR_PINMUX_GPLMUX7 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX8_t GPLMUX8; /* ALT_SYSMGR_PINMUX_GPLMUX8 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX9_t GPLMUX9; /* ALT_SYSMGR_PINMUX_GPLMUX9 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX10_t GPLMUX10; /* ALT_SYSMGR_PINMUX_GPLMUX10 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX11_t GPLMUX11; /* ALT_SYSMGR_PINMUX_GPLMUX11 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX12_t GPLMUX12; /* ALT_SYSMGR_PINMUX_GPLMUX12 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX13_t GPLMUX13; /* ALT_SYSMGR_PINMUX_GPLMUX13 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX14_t GPLMUX14; /* ALT_SYSMGR_PINMUX_GPLMUX14 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX15_t GPLMUX15; /* ALT_SYSMGR_PINMUX_GPLMUX15 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX16_t GPLMUX16; /* ALT_SYSMGR_PINMUX_GPLMUX16 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX17_t GPLMUX17; /* ALT_SYSMGR_PINMUX_GPLMUX17 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX18_t GPLMUX18; /* ALT_SYSMGR_PINMUX_GPLMUX18 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX19_t GPLMUX19; /* ALT_SYSMGR_PINMUX_GPLMUX19 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX20_t GPLMUX20; /* ALT_SYSMGR_PINMUX_GPLMUX20 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX21_t GPLMUX21; /* ALT_SYSMGR_PINMUX_GPLMUX21 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX22_t GPLMUX22; /* ALT_SYSMGR_PINMUX_GPLMUX22 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX23_t GPLMUX23; /* ALT_SYSMGR_PINMUX_GPLMUX23 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX24_t GPLMUX24; /* ALT_SYSMGR_PINMUX_GPLMUX24 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX25_t GPLMUX25; /* ALT_SYSMGR_PINMUX_GPLMUX25 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX26_t GPLMUX26; /* ALT_SYSMGR_PINMUX_GPLMUX26 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX27_t GPLMUX27; /* ALT_SYSMGR_PINMUX_GPLMUX27 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX28_t GPLMUX28; /* ALT_SYSMGR_PINMUX_GPLMUX28 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX29_t GPLMUX29; /* ALT_SYSMGR_PINMUX_GPLMUX29 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX30_t GPLMUX30; /* ALT_SYSMGR_PINMUX_GPLMUX30 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX31_t GPLMUX31; /* ALT_SYSMGR_PINMUX_GPLMUX31 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX32_t GPLMUX32; /* ALT_SYSMGR_PINMUX_GPLMUX32 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX33_t GPLMUX33; /* ALT_SYSMGR_PINMUX_GPLMUX33 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX34_t GPLMUX34; /* ALT_SYSMGR_PINMUX_GPLMUX34 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX35_t GPLMUX35; /* ALT_SYSMGR_PINMUX_GPLMUX35 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX36_t GPLMUX36; /* ALT_SYSMGR_PINMUX_GPLMUX36 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX37_t GPLMUX37; /* ALT_SYSMGR_PINMUX_GPLMUX37 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX38_t GPLMUX38; /* ALT_SYSMGR_PINMUX_GPLMUX38 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX39_t GPLMUX39; /* ALT_SYSMGR_PINMUX_GPLMUX39 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX40_t GPLMUX40; /* ALT_SYSMGR_PINMUX_GPLMUX40 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX41_t GPLMUX41; /* ALT_SYSMGR_PINMUX_GPLMUX41 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX42_t GPLMUX42; /* ALT_SYSMGR_PINMUX_GPLMUX42 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX43_t GPLMUX43; /* ALT_SYSMGR_PINMUX_GPLMUX43 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX44_t GPLMUX44; /* ALT_SYSMGR_PINMUX_GPLMUX44 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX45_t GPLMUX45; /* ALT_SYSMGR_PINMUX_GPLMUX45 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX46_t GPLMUX46; /* ALT_SYSMGR_PINMUX_GPLMUX46 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX47_t GPLMUX47; /* ALT_SYSMGR_PINMUX_GPLMUX47 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX48_t GPLMUX48; /* ALT_SYSMGR_PINMUX_GPLMUX48 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX49_t GPLMUX49; /* ALT_SYSMGR_PINMUX_GPLMUX49 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX50_t GPLMUX50; /* ALT_SYSMGR_PINMUX_GPLMUX50 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX51_t GPLMUX51; /* ALT_SYSMGR_PINMUX_GPLMUX51 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX52_t GPLMUX52; /* ALT_SYSMGR_PINMUX_GPLMUX52 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX53_t GPLMUX53; /* ALT_SYSMGR_PINMUX_GPLMUX53 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX54_t GPLMUX54; /* ALT_SYSMGR_PINMUX_GPLMUX54 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX55_t GPLMUX55; /* ALT_SYSMGR_PINMUX_GPLMUX55 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX56_t GPLMUX56; /* ALT_SYSMGR_PINMUX_GPLMUX56 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX57_t GPLMUX57; /* ALT_SYSMGR_PINMUX_GPLMUX57 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX58_t GPLMUX58; /* ALT_SYSMGR_PINMUX_GPLMUX58 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX59_t GPLMUX59; /* ALT_SYSMGR_PINMUX_GPLMUX59 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX60_t GPLMUX60; /* ALT_SYSMGR_PINMUX_GPLMUX60 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX61_t GPLMUX61; /* ALT_SYSMGR_PINMUX_GPLMUX61 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX62_t GPLMUX62; /* ALT_SYSMGR_PINMUX_GPLMUX62 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX63_t GPLMUX63; /* ALT_SYSMGR_PINMUX_GPLMUX63 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX64_t GPLMUX64; /* ALT_SYSMGR_PINMUX_GPLMUX64 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX65_t GPLMUX65; /* ALT_SYSMGR_PINMUX_GPLMUX65 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX66_t GPLMUX66; /* ALT_SYSMGR_PINMUX_GPLMUX66 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX67_t GPLMUX67; /* ALT_SYSMGR_PINMUX_GPLMUX67 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX68_t GPLMUX68; /* ALT_SYSMGR_PINMUX_GPLMUX68 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX69_t GPLMUX69; /* ALT_SYSMGR_PINMUX_GPLMUX69 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX70_t GPLMUX70; /* ALT_SYSMGR_PINMUX_GPLMUX70 */ + volatile ALT_SYSMGR_PINMUX_NANDUSEFPGA_t NANDUSEFPGA; /* ALT_SYSMGR_PINMUX_NANDUSEFPGA */ + volatile uint32_t _pad_0x2f4_0x2f7; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t RGMII1USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII1USEFPGA */ + volatile uint32_t _pad_0x2fc_0x303[2]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_I2C0USEFPGA_t I2C0USEFPGA; /* ALT_SYSMGR_PINMUX_I2C0USEFPGA */ + volatile uint32_t _pad_0x308_0x313[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t RGMII0USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII0USEFPGA */ + volatile uint32_t _pad_0x318_0x323[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_I2C3USEFPGA_t I2C3USEFPGA; /* ALT_SYSMGR_PINMUX_I2C3USEFPGA */ + volatile ALT_SYSMGR_PINMUX_I2C2USEFPGA_t I2C2USEFPGA; /* ALT_SYSMGR_PINMUX_I2C2USEFPGA */ + volatile ALT_SYSMGR_PINMUX_I2C1USEFPGA_t I2C1USEFPGA; /* ALT_SYSMGR_PINMUX_I2C1USEFPGA */ + volatile ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t SPIM1USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM1USEFPGA */ + volatile uint32_t _pad_0x334_0x337; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t SPIM0USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM0USEFPGA */ + volatile uint32_t _pad_0x33c_0x400[49]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_PINMUX. */ +typedef volatile struct ALT_SYSMGR_PINMUX_s ALT_SYSMGR_PINMUX_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_PINMUX. */ +struct ALT_SYSMGR_PINMUX_raw_s +{ + volatile uint32_t EMACIO0; /* ALT_SYSMGR_PINMUX_EMACIO0 */ + volatile uint32_t EMACIO1; /* ALT_SYSMGR_PINMUX_EMACIO1 */ + volatile uint32_t EMACIO2; /* ALT_SYSMGR_PINMUX_EMACIO2 */ + volatile uint32_t EMACIO3; /* ALT_SYSMGR_PINMUX_EMACIO3 */ + volatile uint32_t EMACIO4; /* ALT_SYSMGR_PINMUX_EMACIO4 */ + volatile uint32_t EMACIO5; /* ALT_SYSMGR_PINMUX_EMACIO5 */ + volatile uint32_t EMACIO6; /* ALT_SYSMGR_PINMUX_EMACIO6 */ + volatile uint32_t EMACIO7; /* ALT_SYSMGR_PINMUX_EMACIO7 */ + volatile uint32_t EMACIO8; /* ALT_SYSMGR_PINMUX_EMACIO8 */ + volatile uint32_t EMACIO9; /* ALT_SYSMGR_PINMUX_EMACIO9 */ + volatile uint32_t EMACIO10; /* ALT_SYSMGR_PINMUX_EMACIO10 */ + volatile uint32_t EMACIO11; /* ALT_SYSMGR_PINMUX_EMACIO11 */ + volatile uint32_t EMACIO12; /* ALT_SYSMGR_PINMUX_EMACIO12 */ + volatile uint32_t EMACIO13; /* ALT_SYSMGR_PINMUX_EMACIO13 */ + volatile uint32_t EMACIO14; /* ALT_SYSMGR_PINMUX_EMACIO14 */ + volatile uint32_t EMACIO15; /* ALT_SYSMGR_PINMUX_EMACIO15 */ + volatile uint32_t EMACIO16; /* ALT_SYSMGR_PINMUX_EMACIO16 */ + volatile uint32_t EMACIO17; /* ALT_SYSMGR_PINMUX_EMACIO17 */ + volatile uint32_t EMACIO18; /* ALT_SYSMGR_PINMUX_EMACIO18 */ + volatile uint32_t EMACIO19; /* ALT_SYSMGR_PINMUX_EMACIO19 */ + volatile uint32_t FLASHIO0; /* ALT_SYSMGR_PINMUX_FLSHIO0 */ + volatile uint32_t FLASHIO1; /* ALT_SYSMGR_PINMUX_FLSHIO1 */ + volatile uint32_t FLASHIO2; /* ALT_SYSMGR_PINMUX_FLSHIO2 */ + volatile uint32_t FLASHIO3; /* ALT_SYSMGR_PINMUX_FLSHIO3 */ + volatile uint32_t FLASHIO4; /* ALT_SYSMGR_PINMUX_FLSHIO4 */ + volatile uint32_t FLASHIO5; /* ALT_SYSMGR_PINMUX_FLSHIO5 */ + volatile uint32_t FLASHIO6; /* ALT_SYSMGR_PINMUX_FLSHIO6 */ + volatile uint32_t FLASHIO7; /* ALT_SYSMGR_PINMUX_FLSHIO7 */ + volatile uint32_t FLASHIO8; /* ALT_SYSMGR_PINMUX_FLSHIO8 */ + volatile uint32_t FLASHIO9; /* ALT_SYSMGR_PINMUX_FLSHIO9 */ + volatile uint32_t FLASHIO10; /* ALT_SYSMGR_PINMUX_FLSHIO10 */ + volatile uint32_t FLASHIO11; /* ALT_SYSMGR_PINMUX_FLSHIO11 */ + volatile uint32_t GENERALIO0; /* ALT_SYSMGR_PINMUX_GENERALIO0 */ + volatile uint32_t GENERALIO1; /* ALT_SYSMGR_PINMUX_GENERALIO1 */ + volatile uint32_t GENERALIO2; /* ALT_SYSMGR_PINMUX_GENERALIO2 */ + volatile uint32_t GENERALIO3; /* ALT_SYSMGR_PINMUX_GENERALIO3 */ + volatile uint32_t GENERALIO4; /* ALT_SYSMGR_PINMUX_GENERALIO4 */ + volatile uint32_t GENERALIO5; /* ALT_SYSMGR_PINMUX_GENERALIO5 */ + volatile uint32_t GENERALIO6; /* ALT_SYSMGR_PINMUX_GENERALIO6 */ + volatile uint32_t GENERALIO7; /* ALT_SYSMGR_PINMUX_GENERALIO7 */ + volatile uint32_t GENERALIO8; /* ALT_SYSMGR_PINMUX_GENERALIO8 */ + volatile uint32_t GENERALIO9; /* ALT_SYSMGR_PINMUX_GENERALIO9 */ + volatile uint32_t GENERALIO10; /* ALT_SYSMGR_PINMUX_GENERALIO10 */ + volatile uint32_t GENERALIO11; /* ALT_SYSMGR_PINMUX_GENERALIO11 */ + volatile uint32_t GENERALIO12; /* ALT_SYSMGR_PINMUX_GENERALIO12 */ + volatile uint32_t GENERALIO13; /* ALT_SYSMGR_PINMUX_GENERALIO13 */ + volatile uint32_t GENERALIO14; /* ALT_SYSMGR_PINMUX_GENERALIO14 */ + volatile uint32_t GENERALIO15; /* ALT_SYSMGR_PINMUX_GENERALIO15 */ + volatile uint32_t GENERALIO16; /* ALT_SYSMGR_PINMUX_GENERALIO16 */ + volatile uint32_t GENERALIO17; /* ALT_SYSMGR_PINMUX_GENERALIO17 */ + volatile uint32_t GENERALIO18; /* ALT_SYSMGR_PINMUX_GENERALIO18 */ + volatile uint32_t GENERALIO19; /* ALT_SYSMGR_PINMUX_GENERALIO19 */ + volatile uint32_t GENERALIO20; /* ALT_SYSMGR_PINMUX_GENERALIO20 */ + volatile uint32_t GENERALIO21; /* ALT_SYSMGR_PINMUX_GENERALIO21 */ + volatile uint32_t GENERALIO22; /* ALT_SYSMGR_PINMUX_GENERALIO22 */ + volatile uint32_t GENERALIO23; /* ALT_SYSMGR_PINMUX_GENERALIO23 */ + volatile uint32_t GENERALIO24; /* ALT_SYSMGR_PINMUX_GENERALIO24 */ + volatile uint32_t GENERALIO25; /* ALT_SYSMGR_PINMUX_GENERALIO25 */ + volatile uint32_t GENERALIO26; /* ALT_SYSMGR_PINMUX_GENERALIO26 */ + volatile uint32_t GENERALIO27; /* ALT_SYSMGR_PINMUX_GENERALIO27 */ + volatile uint32_t GENERALIO28; /* ALT_SYSMGR_PINMUX_GENERALIO28 */ + volatile uint32_t GENERALIO29; /* ALT_SYSMGR_PINMUX_GENERALIO29 */ + volatile uint32_t GENERALIO30; /* ALT_SYSMGR_PINMUX_GENERALIO30 */ + volatile uint32_t GENERALIO31; /* ALT_SYSMGR_PINMUX_GENERALIO31 */ + volatile uint32_t MIXED1IO0; /* ALT_SYSMGR_PINMUX_MIXED1IO0 */ + volatile uint32_t MIXED1IO1; /* ALT_SYSMGR_PINMUX_MIXED1IO1 */ + volatile uint32_t MIXED1IO2; /* ALT_SYSMGR_PINMUX_MIXED1IO2 */ + volatile uint32_t MIXED1IO3; /* ALT_SYSMGR_PINMUX_MIXED1IO3 */ + volatile uint32_t MIXED1IO4; /* ALT_SYSMGR_PINMUX_MIXED1IO4 */ + volatile uint32_t MIXED1IO5; /* ALT_SYSMGR_PINMUX_MIXED1IO5 */ + volatile uint32_t MIXED1IO6; /* ALT_SYSMGR_PINMUX_MIXED1IO6 */ + volatile uint32_t MIXED1IO7; /* ALT_SYSMGR_PINMUX_MIXED1IO7 */ + volatile uint32_t MIXED1IO8; /* ALT_SYSMGR_PINMUX_MIXED1IO8 */ + volatile uint32_t MIXED1IO9; /* ALT_SYSMGR_PINMUX_MIXED1IO9 */ + volatile uint32_t MIXED1IO10; /* ALT_SYSMGR_PINMUX_MIXED1IO10 */ + volatile uint32_t MIXED1IO11; /* ALT_SYSMGR_PINMUX_MIXED1IO11 */ + volatile uint32_t MIXED1IO12; /* ALT_SYSMGR_PINMUX_MIXED1IO12 */ + volatile uint32_t MIXED1IO13; /* ALT_SYSMGR_PINMUX_MIXED1IO13 */ + volatile uint32_t MIXED1IO14; /* ALT_SYSMGR_PINMUX_MIXED1IO14 */ + volatile uint32_t MIXED1IO15; /* ALT_SYSMGR_PINMUX_MIXED1IO15 */ + volatile uint32_t MIXED1IO16; /* ALT_SYSMGR_PINMUX_MIXED1IO16 */ + volatile uint32_t MIXED1IO17; /* ALT_SYSMGR_PINMUX_MIXED1IO17 */ + volatile uint32_t MIXED1IO18; /* ALT_SYSMGR_PINMUX_MIXED1IO18 */ + volatile uint32_t MIXED1IO19; /* ALT_SYSMGR_PINMUX_MIXED1IO19 */ + volatile uint32_t MIXED1IO20; /* ALT_SYSMGR_PINMUX_MIXED1IO20 */ + volatile uint32_t MIXED1IO21; /* ALT_SYSMGR_PINMUX_MIXED1IO21 */ + volatile uint32_t MIXED2IO0; /* ALT_SYSMGR_PINMUX_MIXED2IO0 */ + volatile uint32_t MIXED2IO1; /* ALT_SYSMGR_PINMUX_MIXED2IO1 */ + volatile uint32_t MIXED2IO2; /* ALT_SYSMGR_PINMUX_MIXED2IO2 */ + volatile uint32_t MIXED2IO3; /* ALT_SYSMGR_PINMUX_MIXED2IO3 */ + volatile uint32_t MIXED2IO4; /* ALT_SYSMGR_PINMUX_MIXED2IO4 */ + volatile uint32_t MIXED2IO5; /* ALT_SYSMGR_PINMUX_MIXED2IO5 */ + volatile uint32_t MIXED2IO6; /* ALT_SYSMGR_PINMUX_MIXED2IO6 */ + volatile uint32_t MIXED2IO7; /* ALT_SYSMGR_PINMUX_MIXED2IO7 */ + volatile uint32_t GPLINMUX48; /* ALT_SYSMGR_PINMUX_GPLINMUX48 */ + volatile uint32_t GPLINMUX49; /* ALT_SYSMGR_PINMUX_GPLINMUX49 */ + volatile uint32_t GPLINMUX50; /* ALT_SYSMGR_PINMUX_GPLINMUX50 */ + volatile uint32_t GPLINMUX51; /* ALT_SYSMGR_PINMUX_GPLINMUX51 */ + volatile uint32_t GPLINMUX52; /* ALT_SYSMGR_PINMUX_GPLINMUX52 */ + volatile uint32_t GPLINMUX53; /* ALT_SYSMGR_PINMUX_GPLINMUX53 */ + volatile uint32_t GPLINMUX54; /* ALT_SYSMGR_PINMUX_GPLINMUX54 */ + volatile uint32_t GPLINMUX55; /* ALT_SYSMGR_PINMUX_GPLINMUX55 */ + volatile uint32_t GPLINMUX56; /* ALT_SYSMGR_PINMUX_GPLINMUX56 */ + volatile uint32_t GPLINMUX57; /* ALT_SYSMGR_PINMUX_GPLINMUX57 */ + volatile uint32_t GPLINMUX58; /* ALT_SYSMGR_PINMUX_GPLINMUX58 */ + volatile uint32_t GPLINMUX59; /* ALT_SYSMGR_PINMUX_GPLINMUX59 */ + volatile uint32_t GPLINMUX60; /* ALT_SYSMGR_PINMUX_GPLINMUX60 */ + volatile uint32_t GPLINMUX61; /* ALT_SYSMGR_PINMUX_GPLINMUX61 */ + volatile uint32_t GPLINMUX62; /* ALT_SYSMGR_PINMUX_GPLINMUX62 */ + volatile uint32_t GPLINMUX63; /* ALT_SYSMGR_PINMUX_GPLINMUX63 */ + volatile uint32_t GPLINMUX64; /* ALT_SYSMGR_PINMUX_GPLINMUX64 */ + volatile uint32_t GPLINMUX65; /* ALT_SYSMGR_PINMUX_GPLINMUX65 */ + volatile uint32_t GPLINMUX66; /* ALT_SYSMGR_PINMUX_GPLINMUX66 */ + volatile uint32_t GPLINMUX67; /* ALT_SYSMGR_PINMUX_GPLINMUX67 */ + volatile uint32_t GPLINMUX68; /* ALT_SYSMGR_PINMUX_GPLINMUX68 */ + volatile uint32_t GPLINMUX69; /* ALT_SYSMGR_PINMUX_GPLINMUX69 */ + volatile uint32_t GPLINMUX70; /* ALT_SYSMGR_PINMUX_GPLINMUX70 */ + volatile uint32_t GPLMUX0; /* ALT_SYSMGR_PINMUX_GPLMUX0 */ + volatile uint32_t GPLMUX1; /* ALT_SYSMGR_PINMUX_GPLMUX1 */ + volatile uint32_t GPLMUX2; /* ALT_SYSMGR_PINMUX_GPLMUX2 */ + volatile uint32_t GPLMUX3; /* ALT_SYSMGR_PINMUX_GPLMUX3 */ + volatile uint32_t GPLMUX4; /* ALT_SYSMGR_PINMUX_GPLMUX4 */ + volatile uint32_t GPLMUX5; /* ALT_SYSMGR_PINMUX_GPLMUX5 */ + volatile uint32_t GPLMUX6; /* ALT_SYSMGR_PINMUX_GPLMUX6 */ + volatile uint32_t GPLMUX7; /* ALT_SYSMGR_PINMUX_GPLMUX7 */ + volatile uint32_t GPLMUX8; /* ALT_SYSMGR_PINMUX_GPLMUX8 */ + volatile uint32_t GPLMUX9; /* ALT_SYSMGR_PINMUX_GPLMUX9 */ + volatile uint32_t GPLMUX10; /* ALT_SYSMGR_PINMUX_GPLMUX10 */ + volatile uint32_t GPLMUX11; /* ALT_SYSMGR_PINMUX_GPLMUX11 */ + volatile uint32_t GPLMUX12; /* ALT_SYSMGR_PINMUX_GPLMUX12 */ + volatile uint32_t GPLMUX13; /* ALT_SYSMGR_PINMUX_GPLMUX13 */ + volatile uint32_t GPLMUX14; /* ALT_SYSMGR_PINMUX_GPLMUX14 */ + volatile uint32_t GPLMUX15; /* ALT_SYSMGR_PINMUX_GPLMUX15 */ + volatile uint32_t GPLMUX16; /* ALT_SYSMGR_PINMUX_GPLMUX16 */ + volatile uint32_t GPLMUX17; /* ALT_SYSMGR_PINMUX_GPLMUX17 */ + volatile uint32_t GPLMUX18; /* ALT_SYSMGR_PINMUX_GPLMUX18 */ + volatile uint32_t GPLMUX19; /* ALT_SYSMGR_PINMUX_GPLMUX19 */ + volatile uint32_t GPLMUX20; /* ALT_SYSMGR_PINMUX_GPLMUX20 */ + volatile uint32_t GPLMUX21; /* ALT_SYSMGR_PINMUX_GPLMUX21 */ + volatile uint32_t GPLMUX22; /* ALT_SYSMGR_PINMUX_GPLMUX22 */ + volatile uint32_t GPLMUX23; /* ALT_SYSMGR_PINMUX_GPLMUX23 */ + volatile uint32_t GPLMUX24; /* ALT_SYSMGR_PINMUX_GPLMUX24 */ + volatile uint32_t GPLMUX25; /* ALT_SYSMGR_PINMUX_GPLMUX25 */ + volatile uint32_t GPLMUX26; /* ALT_SYSMGR_PINMUX_GPLMUX26 */ + volatile uint32_t GPLMUX27; /* ALT_SYSMGR_PINMUX_GPLMUX27 */ + volatile uint32_t GPLMUX28; /* ALT_SYSMGR_PINMUX_GPLMUX28 */ + volatile uint32_t GPLMUX29; /* ALT_SYSMGR_PINMUX_GPLMUX29 */ + volatile uint32_t GPLMUX30; /* ALT_SYSMGR_PINMUX_GPLMUX30 */ + volatile uint32_t GPLMUX31; /* ALT_SYSMGR_PINMUX_GPLMUX31 */ + volatile uint32_t GPLMUX32; /* ALT_SYSMGR_PINMUX_GPLMUX32 */ + volatile uint32_t GPLMUX33; /* ALT_SYSMGR_PINMUX_GPLMUX33 */ + volatile uint32_t GPLMUX34; /* ALT_SYSMGR_PINMUX_GPLMUX34 */ + volatile uint32_t GPLMUX35; /* ALT_SYSMGR_PINMUX_GPLMUX35 */ + volatile uint32_t GPLMUX36; /* ALT_SYSMGR_PINMUX_GPLMUX36 */ + volatile uint32_t GPLMUX37; /* ALT_SYSMGR_PINMUX_GPLMUX37 */ + volatile uint32_t GPLMUX38; /* ALT_SYSMGR_PINMUX_GPLMUX38 */ + volatile uint32_t GPLMUX39; /* ALT_SYSMGR_PINMUX_GPLMUX39 */ + volatile uint32_t GPLMUX40; /* ALT_SYSMGR_PINMUX_GPLMUX40 */ + volatile uint32_t GPLMUX41; /* ALT_SYSMGR_PINMUX_GPLMUX41 */ + volatile uint32_t GPLMUX42; /* ALT_SYSMGR_PINMUX_GPLMUX42 */ + volatile uint32_t GPLMUX43; /* ALT_SYSMGR_PINMUX_GPLMUX43 */ + volatile uint32_t GPLMUX44; /* ALT_SYSMGR_PINMUX_GPLMUX44 */ + volatile uint32_t GPLMUX45; /* ALT_SYSMGR_PINMUX_GPLMUX45 */ + volatile uint32_t GPLMUX46; /* ALT_SYSMGR_PINMUX_GPLMUX46 */ + volatile uint32_t GPLMUX47; /* ALT_SYSMGR_PINMUX_GPLMUX47 */ + volatile uint32_t GPLMUX48; /* ALT_SYSMGR_PINMUX_GPLMUX48 */ + volatile uint32_t GPLMUX49; /* ALT_SYSMGR_PINMUX_GPLMUX49 */ + volatile uint32_t GPLMUX50; /* ALT_SYSMGR_PINMUX_GPLMUX50 */ + volatile uint32_t GPLMUX51; /* ALT_SYSMGR_PINMUX_GPLMUX51 */ + volatile uint32_t GPLMUX52; /* ALT_SYSMGR_PINMUX_GPLMUX52 */ + volatile uint32_t GPLMUX53; /* ALT_SYSMGR_PINMUX_GPLMUX53 */ + volatile uint32_t GPLMUX54; /* ALT_SYSMGR_PINMUX_GPLMUX54 */ + volatile uint32_t GPLMUX55; /* ALT_SYSMGR_PINMUX_GPLMUX55 */ + volatile uint32_t GPLMUX56; /* ALT_SYSMGR_PINMUX_GPLMUX56 */ + volatile uint32_t GPLMUX57; /* ALT_SYSMGR_PINMUX_GPLMUX57 */ + volatile uint32_t GPLMUX58; /* ALT_SYSMGR_PINMUX_GPLMUX58 */ + volatile uint32_t GPLMUX59; /* ALT_SYSMGR_PINMUX_GPLMUX59 */ + volatile uint32_t GPLMUX60; /* ALT_SYSMGR_PINMUX_GPLMUX60 */ + volatile uint32_t GPLMUX61; /* ALT_SYSMGR_PINMUX_GPLMUX61 */ + volatile uint32_t GPLMUX62; /* ALT_SYSMGR_PINMUX_GPLMUX62 */ + volatile uint32_t GPLMUX63; /* ALT_SYSMGR_PINMUX_GPLMUX63 */ + volatile uint32_t GPLMUX64; /* ALT_SYSMGR_PINMUX_GPLMUX64 */ + volatile uint32_t GPLMUX65; /* ALT_SYSMGR_PINMUX_GPLMUX65 */ + volatile uint32_t GPLMUX66; /* ALT_SYSMGR_PINMUX_GPLMUX66 */ + volatile uint32_t GPLMUX67; /* ALT_SYSMGR_PINMUX_GPLMUX67 */ + volatile uint32_t GPLMUX68; /* ALT_SYSMGR_PINMUX_GPLMUX68 */ + volatile uint32_t GPLMUX69; /* ALT_SYSMGR_PINMUX_GPLMUX69 */ + volatile uint32_t GPLMUX70; /* ALT_SYSMGR_PINMUX_GPLMUX70 */ + volatile uint32_t NANDUSEFPGA; /* ALT_SYSMGR_PINMUX_NANDUSEFPGA */ + volatile uint32_t _pad_0x2f4_0x2f7; /* *UNDEFINED* */ + volatile uint32_t RGMII1USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII1USEFPGA */ + volatile uint32_t _pad_0x2fc_0x303[2]; /* *UNDEFINED* */ + volatile uint32_t I2C0USEFPGA; /* ALT_SYSMGR_PINMUX_I2C0USEFPGA */ + volatile uint32_t _pad_0x308_0x313[3]; /* *UNDEFINED* */ + volatile uint32_t RGMII0USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII0USEFPGA */ + volatile uint32_t _pad_0x318_0x323[3]; /* *UNDEFINED* */ + volatile uint32_t I2C3USEFPGA; /* ALT_SYSMGR_PINMUX_I2C3USEFPGA */ + volatile uint32_t I2C2USEFPGA; /* ALT_SYSMGR_PINMUX_I2C2USEFPGA */ + volatile uint32_t I2C1USEFPGA; /* ALT_SYSMGR_PINMUX_I2C1USEFPGA */ + volatile uint32_t SPIM1USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM1USEFPGA */ + volatile uint32_t _pad_0x334_0x337; /* *UNDEFINED* */ + volatile uint32_t SPIM0USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM0USEFPGA */ + volatile uint32_t _pad_0x33c_0x400[49]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_PINMUX. */ +typedef volatile struct ALT_SYSMGR_PINMUX_raw_s ALT_SYSMGR_PINMUX_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR. + */ +struct ALT_SYSMGR_s +{ + volatile ALT_SYSMGR_SILICONID1_t siliconid1; /* ALT_SYSMGR_SILICONID1 */ + volatile ALT_SYSMGR_SILICONID2_t siliconid2; /* ALT_SYSMGR_SILICONID2 */ + volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_WDDBG_t wddbg; /* ALT_SYSMGR_WDDBG */ + volatile ALT_SYSMGR_BOOT_t bootinfo; /* ALT_SYSMGR_BOOT */ + volatile ALT_SYSMGR_HPSINFO_t hpsinfo; /* ALT_SYSMGR_HPSINFO */ + volatile ALT_SYSMGR_PARITYINJ_t parityinj; /* ALT_SYSMGR_PARITYINJ */ + volatile ALT_SYSMGR_FPGAINTF_t fpgaintfgrp; /* ALT_SYSMGR_FPGAINTF */ + volatile ALT_SYSMGR_SCANMGR_t scanmgrgrp; /* ALT_SYSMGR_SCANMGR */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_FRZCTL_t frzctrl; /* ALT_SYSMGR_FRZCTL */ + volatile ALT_SYSMGR_EMAC_t emacgrp; /* ALT_SYSMGR_EMAC */ + volatile ALT_SYSMGR_DMA_t dmagrp; /* ALT_SYSMGR_DMA */ + volatile uint32_t _pad_0x78_0x7f[2]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ISW_t iswgrp; /* ALT_SYSMGR_ISW */ + volatile uint32_t _pad_0xa0_0xbf[8]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ROMCODE_t romcodegrp; /* ALT_SYSMGR_ROMCODE */ + volatile ALT_SYSMGR_ROMHW_t romhwgrp; /* ALT_SYSMGR_ROMHW */ + volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */ + volatile ALT_SYSMGR_SDMMC_t sdmmcgrp; /* ALT_SYSMGR_SDMMC */ + volatile ALT_SYSMGR_NAND_t nandgrp; /* ALT_SYSMGR_NAND */ + volatile ALT_SYSMGR_USB_t usbgrp; /* ALT_SYSMGR_USB */ + volatile uint32_t _pad_0x11c_0x13f[9]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ECC_t eccgrp; /* ALT_SYSMGR_ECC */ + volatile uint32_t _pad_0x180_0x3ff[160]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_t pinmuxgrp; /* ALT_SYSMGR_PINMUX */ + volatile uint32_t _pad_0x800_0x4000[3584]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR. */ +typedef volatile struct ALT_SYSMGR_s ALT_SYSMGR_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR. */ +struct ALT_SYSMGR_raw_s +{ + volatile uint32_t siliconid1; /* ALT_SYSMGR_SILICONID1 */ + volatile uint32_t siliconid2; /* ALT_SYSMGR_SILICONID2 */ + volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */ + volatile uint32_t wddbg; /* ALT_SYSMGR_WDDBG */ + volatile uint32_t bootinfo; /* ALT_SYSMGR_BOOT */ + volatile uint32_t hpsinfo; /* ALT_SYSMGR_HPSINFO */ + volatile uint32_t parityinj; /* ALT_SYSMGR_PARITYINJ */ + volatile ALT_SYSMGR_FPGAINTF_raw_t fpgaintfgrp; /* ALT_SYSMGR_FPGAINTF */ + volatile ALT_SYSMGR_SCANMGR_raw_t scanmgrgrp; /* ALT_SYSMGR_SCANMGR */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_FRZCTL_raw_t frzctrl; /* ALT_SYSMGR_FRZCTL */ + volatile ALT_SYSMGR_EMAC_raw_t emacgrp; /* ALT_SYSMGR_EMAC */ + volatile ALT_SYSMGR_DMA_raw_t dmagrp; /* ALT_SYSMGR_DMA */ + volatile uint32_t _pad_0x78_0x7f[2]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ISW_raw_t iswgrp; /* ALT_SYSMGR_ISW */ + volatile uint32_t _pad_0xa0_0xbf[8]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ROMCODE_raw_t romcodegrp; /* ALT_SYSMGR_ROMCODE */ + volatile ALT_SYSMGR_ROMHW_raw_t romhwgrp; /* ALT_SYSMGR_ROMHW */ + volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */ + volatile ALT_SYSMGR_SDMMC_raw_t sdmmcgrp; /* ALT_SYSMGR_SDMMC */ + volatile ALT_SYSMGR_NAND_raw_t nandgrp; /* ALT_SYSMGR_NAND */ + volatile ALT_SYSMGR_USB_raw_t usbgrp; /* ALT_SYSMGR_USB */ + volatile uint32_t _pad_0x11c_0x13f[9]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ECC_raw_t eccgrp; /* ALT_SYSMGR_ECC */ + volatile uint32_t _pad_0x180_0x3ff[160]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_raw_t pinmuxgrp; /* ALT_SYSMGR_PINMUX */ + volatile uint32_t _pad_0x800_0x4000[3584]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR. */ +typedef volatile struct ALT_SYSMGR_raw_s ALT_SYSMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_SYSMGR_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h new file mode 100644 index 0000000000..b64111960b --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h @@ -0,0 +1,5158 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_UART */ + +#ifndef __ALTERA_ALT_UART_H__ +#define __ALTERA_ALT_UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : UART Module - ALT_UART + * UART Module + * + * Registers in the UART module + * + */ +/* + * Register : Rx Buffer, Tx Holding, and Divisor Latch Low - rbr_thr_dll + * + * This is a multi-function register. This register holds receives and transmit + * data and controls the least-signficant 8 bits of the baud rate divisor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | RW | 0x0 | Value + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Value - value + * + * Receive Buffer Register: + * + * This register contains the data byte received on the serial input port + * (uart_rxd). The data in this register is valid only if the Data Ready ( bit [0] + * in the Line Status Register(LSR)) is set to 1. If FIFOs are disabled(bit[0] of + * Register FCR is set to 0) the data in the RBR must be read before the next data + * arrives, otherwise it will be overwritten, resulting in an overrun error. If + * FIFOs are enabled(bit [0] of Register FCR is set to 1) this register accesses + * the head of the receive FIFO. If the receive FIFO is full, and this register is + * not read before the next data character arrives, then the data already in the + * FIFO will be preserved but any incoming data will be lost. An overrun error will + * also occur. + * + * Transmit Holding Register: + * + * This register contains data to be transmitted on the serial output port. Data + * should only be written to the THR when the THR Empty bit [5] of the LSR Register + * is set to 1. If FIFOs are disabled (bit [0] of Register FCR) is set to 0 and + * THRE is set to 1, writing a single character to the THR clears the THRE. Any + * additional writes to the THR before the THRE is set again causes the THR data to + * be overwritten. If FIFO's are enabled bit [0] of Register FCR is set to 1 and + * THRE is set up to 128 characters of data may be written to the THR before the + * FIFO is full. Any attempt to write data when the FIFO is full results in the + * write data being lost. + * + * Divisor Latch Low: + * + * This register makes up the lower 8-bits of a 16-bit, Read/write, Divisor Latch + * register that contains the baud rate divisor for the UART. This register may + * only be accessed when the DLAB bit [7] of the LCR Register is set to 1. The + * output baud rate is equal to the serial clock l4_sp_clk frequency divided by + * sixteen times the value of the baud rate divisor, as follows: + * + * baud rate = (serial clock freq) / (16 * divisor) + * + * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud + * clock is disabled and no serial communications will occur. Also, once the DLL is + * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before + * transmitting or receiving data. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */ +#define ALT_UART_RBR_THR_DLL_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */ +#define ALT_UART_RBR_THR_DLL_VALUE_MSB 7 +/* The width in bits of the ALT_UART_RBR_THR_DLL_VALUE register field. */ +#define ALT_UART_RBR_THR_DLL_VALUE_WIDTH 8 +/* The mask used to set the ALT_UART_RBR_THR_DLL_VALUE register field value. */ +#define ALT_UART_RBR_THR_DLL_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_RBR_THR_DLL_VALUE register field value. */ +#define ALT_UART_RBR_THR_DLL_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_RBR_THR_DLL_VALUE register field. */ +#define ALT_UART_RBR_THR_DLL_VALUE_RESET 0x0 +/* Extracts the ALT_UART_RBR_THR_DLL_VALUE field value from a register. */ +#define ALT_UART_RBR_THR_DLL_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_RBR_THR_DLL_VALUE register field value suitable for setting the register. */ +#define ALT_UART_RBR_THR_DLL_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_RBR_THR_DLL. + */ +struct ALT_UART_RBR_THR_DLL_s +{ + uint32_t value : 8; /* Value */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_RBR_THR_DLL. */ +typedef volatile struct ALT_UART_RBR_THR_DLL_s ALT_UART_RBR_THR_DLL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_RBR_THR_DLL register from the beginning of the component. */ +#define ALT_UART_RBR_THR_DLL_OFST 0x0 +/* The address of the ALT_UART_RBR_THR_DLL register. */ +#define ALT_UART_RBR_THR_DLL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RBR_THR_DLL_OFST)) + +/* + * Register : Interrupt Enable and Divisor Latch High - ier_dlh + * + * This is a multi-function register. This register enables/disables receive and + * transmit interrupts and also controls the most-significant 8-bits of the baud + * rate divisor. + * + * Divisor Latch High Register: + * + * This register is accessed when the DLAB bit [7] of the LCR Register is set to + * 1.Bits[7:0] contain the high order 8-bits of the baud rate divisor.The output + * baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen + * times the value of the baud rate divisor, as follows: + * + * baud rate = (serial clock freq) / (16 * divisor): + * + * Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud + * clock is disabled and no serial communications will occur. Also, once the DLL is + * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before + * transmitting or receiving data. + * + * Interrupt Enable Register: + * + * This register may only be accessed when the DLAB bit [7] of the LCR Register is + * set to 0.Allows control of the Interrupt Enables for transmit and receive + * functions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------------- + * [0] | RW | 0x0 | DLH[0] and Receive Data Interrupt Enable + * [1] | RW | 0x0 | DLH[1] and Transmit Data Interrupt Control + * [2] | RW | 0x0 | DLH[2] and Enable Receiver Line Status + * [3] | RW | 0x0 | DLH[3] and Enable Modem Status Interrupt + * [4] | RW | 0x0 | DLH[4] + * [5] | RW | 0x0 | DLH[5] + * [6] | RW | 0x0 | DLH[6] + * [7] | RW | 0x0 | DLH[7] and PTIME THRE Interrupt Mode Enable + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DLH[0] and Receive Data Interrupt Enable - erbfi_dlh0 + * + * Divisor Latch High Register: + * + * Bit 0 of DLH value. + * + * Interrupt Enable Register: + * + * Used to enable/disable the generation of the Receive Data Available Interrupt + * and the Character Timeout Interrupt(if FIFO's enabled). These are the second + * highest priority interrupts. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------ + * ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD | 0x0 | Interrupt Disable + * ALT_UART_IER_DLH_ERBFI_DLH0_E_END | 0x1 | Interrupt Enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0 + * + * Interrupt Disable + */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0 + * + * Interrupt Enable + */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_MSB 0 +/* The width in bits of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_ERBFI_DLH0 field value from a register. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_IER_DLH_ERBFI_DLH0 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : DLH[1] and Transmit Data Interrupt Control - etbei_dlhl + * + * Divisor Latch High Register: + * + * Bit 1 of DLH value. + * + * Interrupt Enable Register: + * + * Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable + * the generation of Transmitter Holding Register Empty Interrupt. This is the + * third highest priority interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD | 0x0 | Tx disable + * ALT_UART_IER_DLH_ETBEI_DLHL_E_END | 0x1 | Tx enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL + * + * Tx disable + */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL + * + * Tx enable + */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_MSB 1 +/* The width in bits of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_ETBEI_DLHL field value from a register. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_IER_DLH_ETBEI_DLHL register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : DLH[2] and Enable Receiver Line Status - elsi_dhl2 + * + * Divisor Latch High Register: + * + * Bit 2 of DLH value. + * + * Interrupt Enable Register: + * + * This is used to enable/disable the generation of Receiver Line Status Interrupt. + * This is the highest priority interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------- + * ALT_UART_IER_DLH_ELSI_DHL2_E_DISD | 0x0 | Disable interrupt line stat + * ALT_UART_IER_DLH_ELSI_DHL2_E_END | 0x1 | Enable interrupt line stat + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2 + * + * Disable interrupt line stat + */ +#define ALT_UART_IER_DLH_ELSI_DHL2_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2 + * + * Enable interrupt line stat + */ +#define ALT_UART_IER_DLH_ELSI_DHL2_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_MSB 2 +/* The width in bits of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_ELSI_DHL2 field value from a register. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_IER_DLH_ELSI_DHL2 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DLH[3] and Enable Modem Status Interrupt - edssi_dhl3 + * + * Divisor Latch High Register: + * + * Bit 3 of DLH value. + * + * Interrupt Enable Register: + * + * This is used to enable/disable the generation of Modem Status Interrupts. This + * is the fourth highest priority interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------- + * ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD | 0x0 | disable modem status interrupt + * ALT_UART_IER_DLH_EDSSI_DHL3_E_END | 0x1 | enable modem status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3 + * + * disable modem status interrupt + */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3 + * + * enable modem status interrupt + */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_MSB 3 +/* The width in bits of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_EDSSI_DHL3 field value from a register. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_IER_DLH_EDSSI_DHL3 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : DLH[4] - dlh4 + * + * Bit 4 of DLH value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH4 register field. */ +#define ALT_UART_IER_DLH_DLH4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH4 register field. */ +#define ALT_UART_IER_DLH_DLH4_MSB 4 +/* The width in bits of the ALT_UART_IER_DLH_DLH4 register field. */ +#define ALT_UART_IER_DLH_DLH4_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_DLH4 register field value. */ +#define ALT_UART_IER_DLH_DLH4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_IER_DLH_DLH4 register field value. */ +#define ALT_UART_IER_DLH_DLH4_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_IER_DLH_DLH4 register field. */ +#define ALT_UART_IER_DLH_DLH4_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_DLH4 field value from a register. */ +#define ALT_UART_IER_DLH_DLH4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_IER_DLH_DLH4 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_DLH4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : DLH[5] - dlh5 + * + * Bit 5 of DLH value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH5 register field. */ +#define ALT_UART_IER_DLH_DLH5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH5 register field. */ +#define ALT_UART_IER_DLH_DLH5_MSB 5 +/* The width in bits of the ALT_UART_IER_DLH_DLH5 register field. */ +#define ALT_UART_IER_DLH_DLH5_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_DLH5 register field value. */ +#define ALT_UART_IER_DLH_DLH5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_IER_DLH_DLH5 register field value. */ +#define ALT_UART_IER_DLH_DLH5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_IER_DLH_DLH5 register field. */ +#define ALT_UART_IER_DLH_DLH5_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_DLH5 field value from a register. */ +#define ALT_UART_IER_DLH_DLH5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_IER_DLH_DLH5 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_DLH5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : DLH[6] - dlh6 + * + * Bit 6 of DLH value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH6 register field. */ +#define ALT_UART_IER_DLH_DLH6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH6 register field. */ +#define ALT_UART_IER_DLH_DLH6_MSB 6 +/* The width in bits of the ALT_UART_IER_DLH_DLH6 register field. */ +#define ALT_UART_IER_DLH_DLH6_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_DLH6 register field value. */ +#define ALT_UART_IER_DLH_DLH6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_IER_DLH_DLH6 register field value. */ +#define ALT_UART_IER_DLH_DLH6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_IER_DLH_DLH6 register field. */ +#define ALT_UART_IER_DLH_DLH6_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_DLH6 field value from a register. */ +#define ALT_UART_IER_DLH_DLH6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_IER_DLH_DLH6 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_DLH6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : DLH[7] and PTIME THRE Interrupt Mode Enable - ptime_dlh7 + * + * Divisor Latch High Register: + * + * Bit 7 of DLH value. + * + * Interrupt Enable Register: + * + * This is used to enable/disable the generation of THRE Interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------ + * ALT_UART_IER_DLH_PTIME_DLH7_E_DISD | 0x0 | disable tx-hold-reg-empty interrupt + * ALT_UART_IER_DLH_PTIME_DLH7_E_END | 0x1 | enable tx-hold-reg-empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7 + * + * disable tx-hold-reg-empty interrupt + */ +#define ALT_UART_IER_DLH_PTIME_DLH7_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7 + * + * enable tx-hold-reg-empty interrupt + */ +#define ALT_UART_IER_DLH_PTIME_DLH7_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_MSB 7 +/* The width in bits of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_PTIME_DLH7 field value from a register. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_IER_DLH_PTIME_DLH7 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_IER_DLH. + */ +struct ALT_UART_IER_DLH_s +{ + uint32_t erbfi_dlh0 : 1; /* DLH[0] and Receive Data Interrupt Enable */ + uint32_t etbei_dlhl : 1; /* DLH[1] and Transmit Data Interrupt Control */ + uint32_t elsi_dhl2 : 1; /* DLH[2] and Enable Receiver Line Status */ + uint32_t edssi_dhl3 : 1; /* DLH[3] and Enable Modem Status Interrupt */ + uint32_t dlh4 : 1; /* DLH[4] */ + uint32_t dlh5 : 1; /* DLH[5] */ + uint32_t dlh6 : 1; /* DLH[6] */ + uint32_t ptime_dlh7 : 1; /* DLH[7] and PTIME THRE Interrupt Mode Enable */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_IER_DLH. */ +typedef volatile struct ALT_UART_IER_DLH_s ALT_UART_IER_DLH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_IER_DLH register from the beginning of the component. */ +#define ALT_UART_IER_DLH_OFST 0x4 +/* The address of the ALT_UART_IER_DLH register. */ +#define ALT_UART_IER_DLH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IER_DLH_OFST)) + +/* + * Register : Interrupt Identity Register (when read) - iir + * + * Returns interrupt identification and FIFO enable/disable when read. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [3:0] | R | 0x1 | Interrupt ID + * [5:4] | ??? | 0x0 | *UNDEFINED* + * [7:6] | R | 0x0 | FIFO Enabled + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt ID - id + * + * This indicates the highest priority pending interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------- + * ALT_UART_IIR_ID_E_MODMSTAT | 0x0 | Modem status + * ALT_UART_IIR_ID_E_NOINTRPENDING | 0x1 | No Interrupt pending + * ALT_UART_IIR_ID_E_THREMPTY | 0x2 | THR empty + * ALT_UART_IIR_ID_E_RXDATAVAILABLE | 0x4 | Receive data available + * ALT_UART_IIR_ID_E_RXLINESTAT | 0x6 | Receive line status + * ALT_UART_IIR_ID_E_CHARTMO | 0xc | Character timeout + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * Modem status + */ +#define ALT_UART_IIR_ID_E_MODMSTAT 0x0 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * No Interrupt pending + */ +#define ALT_UART_IIR_ID_E_NOINTRPENDING 0x1 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * THR empty + */ +#define ALT_UART_IIR_ID_E_THREMPTY 0x2 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * Receive data available + */ +#define ALT_UART_IIR_ID_E_RXDATAVAILABLE 0x4 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * Receive line status + */ +#define ALT_UART_IIR_ID_E_RXLINESTAT 0x6 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * Character timeout + */ +#define ALT_UART_IIR_ID_E_CHARTMO 0xc + +/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_ID register field. */ +#define ALT_UART_IIR_ID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_ID register field. */ +#define ALT_UART_IIR_ID_MSB 3 +/* The width in bits of the ALT_UART_IIR_ID register field. */ +#define ALT_UART_IIR_ID_WIDTH 4 +/* The mask used to set the ALT_UART_IIR_ID register field value. */ +#define ALT_UART_IIR_ID_SET_MSK 0x0000000f +/* The mask used to clear the ALT_UART_IIR_ID register field value. */ +#define ALT_UART_IIR_ID_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_UART_IIR_ID register field. */ +#define ALT_UART_IIR_ID_RESET 0x1 +/* Extracts the ALT_UART_IIR_ID field value from a register. */ +#define ALT_UART_IIR_ID_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_UART_IIR_ID register field value suitable for setting the register. */ +#define ALT_UART_IIR_ID_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : FIFO Enabled - fifoen + * + * This is used to indicate whether the FIFO's are enabled or disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------- + * ALT_UART_IIR_FIFOEN_E_DISD | 0x0 | FIFO disabled + * ALT_UART_IIR_FIFOEN_E_END | 0x3 | FIFO enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IIR_FIFOEN + * + * FIFO disabled + */ +#define ALT_UART_IIR_FIFOEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IIR_FIFOEN + * + * FIFO enabled + */ +#define ALT_UART_IIR_FIFOEN_E_END 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_FIFOEN register field. */ +#define ALT_UART_IIR_FIFOEN_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_FIFOEN register field. */ +#define ALT_UART_IIR_FIFOEN_MSB 7 +/* The width in bits of the ALT_UART_IIR_FIFOEN register field. */ +#define ALT_UART_IIR_FIFOEN_WIDTH 2 +/* The mask used to set the ALT_UART_IIR_FIFOEN register field value. */ +#define ALT_UART_IIR_FIFOEN_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_UART_IIR_FIFOEN register field value. */ +#define ALT_UART_IIR_FIFOEN_CLR_MSK 0xffffff3f +/* The reset value of the ALT_UART_IIR_FIFOEN register field. */ +#define ALT_UART_IIR_FIFOEN_RESET 0x0 +/* Extracts the ALT_UART_IIR_FIFOEN field value from a register. */ +#define ALT_UART_IIR_FIFOEN_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_UART_IIR_FIFOEN register field value suitable for setting the register. */ +#define ALT_UART_IIR_FIFOEN_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_IIR. + */ +struct ALT_UART_IIR_s +{ + const uint32_t id : 4; /* Interrupt ID */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t fifoen : 2; /* FIFO Enabled */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_IIR. */ +typedef volatile struct ALT_UART_IIR_s ALT_UART_IIR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_IIR register from the beginning of the component. */ +#define ALT_UART_IIR_OFST 0x8 +/* The address of the ALT_UART_IIR register. */ +#define ALT_UART_IIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IIR_OFST)) + +/* + * Register : FIFO Control (when written) - fcr + * + * Controls FIFO Operations when written. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------------- + * [0] | W | Unknown | FIFO Enable + * [1] | W | Unknown | Rx FIFO Reset + * [2] | W | Unknown | Tx FIFO Reset + * [3] | W | Unknown | DMA Mode + * [5:4] | W | Unknown | Tx Empty Trigger Level + * [7:6] | W | Unknown | Rx Trigger Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FIFO Enable - fifoe + * + * Enables/disables the transmit (Tx) and receive (Rx ) FIFO's. Whenever the value + * of this bit is changed both the Tx and Rx controller portion of FIFO's will be + * reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:--------------- + * ALT_UART_FCR_FIFOE_E_DISD | 0x0 | FIFOs disabled + * ALT_UART_FCR_FIFOE_E_END | 0x1 | FIFOs enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_FIFOE + * + * FIFOs disabled + */ +#define ALT_UART_FCR_FIFOE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_FIFOE + * + * FIFOs enabled + */ +#define ALT_UART_FCR_FIFOE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_FIFOE register field. */ +#define ALT_UART_FCR_FIFOE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_FIFOE register field. */ +#define ALT_UART_FCR_FIFOE_MSB 0 +/* The width in bits of the ALT_UART_FCR_FIFOE register field. */ +#define ALT_UART_FCR_FIFOE_WIDTH 1 +/* The mask used to set the ALT_UART_FCR_FIFOE register field value. */ +#define ALT_UART_FCR_FIFOE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_FCR_FIFOE register field value. */ +#define ALT_UART_FCR_FIFOE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_FCR_FIFOE register field is UNKNOWN. */ +#define ALT_UART_FCR_FIFOE_RESET 0x0 +/* Extracts the ALT_UART_FCR_FIFOE field value from a register. */ +#define ALT_UART_FCR_FIFOE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_FCR_FIFOE register field value suitable for setting the register. */ +#define ALT_UART_FCR_FIFOE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Rx FIFO Reset - rfifor + * + * Resets the control portion of the receive FIFO and treats the FIFO as empty. + * This will also de-assert the DMA Rxrequest and single signals. Note that this + * bit is self-clearing' and it is not necessary to clear this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------------- + * ALT_UART_FCR_RFIFOR_E_NORST | 0x0 | No Reset of Rx FIFO Control + * ALT_UART_FCR_RFIFOR_E_RST | 0x1 | Resets of Rx FIFO Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_RFIFOR + * + * No Reset of Rx FIFO Control + */ +#define ALT_UART_FCR_RFIFOR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_RFIFOR + * + * Resets of Rx FIFO Control + */ +#define ALT_UART_FCR_RFIFOR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RFIFOR register field. */ +#define ALT_UART_FCR_RFIFOR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RFIFOR register field. */ +#define ALT_UART_FCR_RFIFOR_MSB 1 +/* The width in bits of the ALT_UART_FCR_RFIFOR register field. */ +#define ALT_UART_FCR_RFIFOR_WIDTH 1 +/* The mask used to set the ALT_UART_FCR_RFIFOR register field value. */ +#define ALT_UART_FCR_RFIFOR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_FCR_RFIFOR register field value. */ +#define ALT_UART_FCR_RFIFOR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_FCR_RFIFOR register field is UNKNOWN. */ +#define ALT_UART_FCR_RFIFOR_RESET 0x0 +/* Extracts the ALT_UART_FCR_RFIFOR field value from a register. */ +#define ALT_UART_FCR_RFIFOR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_FCR_RFIFOR register field value suitable for setting the register. */ +#define ALT_UART_FCR_RFIFOR_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Tx FIFO Reset - xfifor + * + * Resets the control portion of the transmit FIFO and treats the FIFO as empty. + * This will also de-assert the DMA Tx request and single signals when additional + * DMA handshaking is used. + * + * Note that this bit is 'self-clearing' and it is not necessary to clear this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------------- + * ALT_UART_FCR_XFIFOR_E_NORST | 0x0 | No Reset of Tx FIFO Control + * ALT_UART_FCR_XFIFOR_E_RST | 0x1 | Resets Tx FIFO Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_XFIFOR + * + * No Reset of Tx FIFO Control + */ +#define ALT_UART_FCR_XFIFOR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_XFIFOR + * + * Resets Tx FIFO Control + */ +#define ALT_UART_FCR_XFIFOR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_XFIFOR register field. */ +#define ALT_UART_FCR_XFIFOR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_XFIFOR register field. */ +#define ALT_UART_FCR_XFIFOR_MSB 2 +/* The width in bits of the ALT_UART_FCR_XFIFOR register field. */ +#define ALT_UART_FCR_XFIFOR_WIDTH 1 +/* The mask used to set the ALT_UART_FCR_XFIFOR register field value. */ +#define ALT_UART_FCR_XFIFOR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_FCR_XFIFOR register field value. */ +#define ALT_UART_FCR_XFIFOR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_FCR_XFIFOR register field is UNKNOWN. */ +#define ALT_UART_FCR_XFIFOR_RESET 0x0 +/* Extracts the ALT_UART_FCR_XFIFOR field value from a register. */ +#define ALT_UART_FCR_XFIFOR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_FCR_XFIFOR register field value suitable for setting the register. */ +#define ALT_UART_FCR_XFIFOR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DMA Mode - dmam + * + * This determines the DMA signalling mode used for the uart_dma_tx_req_n and + * uart_dma_rx_req_n output signals when additional DMA handshaking signals are not + * selected. DMA mode 0 supports single DMA data transfers at a time. In mode 0, + * the uart_dma_tx_req_n signal goes active low under the following conditions: + * + * * When the Transmitter Holding Register is empty in non-FIFO mode. + * + * * When the transmitter FIFO is empty in FIFO mode with Programmable THRE + * interrupt mode disabled. + * + * * When the transmitter FIFO is at or below the programmed threshold with + * Programmable THRE interrupt mode enabled. + * + * It goes inactive under the following conditions + * + * * When a single character has been written into the Transmitter Holding + * Register or transmitter FIFO with Programmable THRE interrupt mode disabled. + * + * * When the transmitter FIFO is above the threshold with Programmable THRE + * interrupt mode enabled. + * + * DMA mode 1 supports multi-DMA data transfers, where multiple transfers are made + * continuously until the receiver FIFO has been emptied or the transmit FIFO has + * been filled. In mode 1 the uart_dma_tx_req_n signal is asserted under the + * following conditions: + * + * * When the transmitter FIFO is empty with Programmable THRE interrupt mode + * disabled. + * + * * When the transmitter FIFO is at or below the programmed threshold with + * Programmable THRE interrupt mode enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:--------------------------- + * ALT_UART_FCR_DMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode + * ALT_UART_FCR_DMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_DMAM + * + * Single DMA Transfer Mode + */ +#define ALT_UART_FCR_DMAM_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_DMAM + * + * Multiple DMA Transfer Mode + */ +#define ALT_UART_FCR_DMAM_E_MULT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_DMAM register field. */ +#define ALT_UART_FCR_DMAM_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_DMAM register field. */ +#define ALT_UART_FCR_DMAM_MSB 3 +/* The width in bits of the ALT_UART_FCR_DMAM register field. */ +#define ALT_UART_FCR_DMAM_WIDTH 1 +/* The mask used to set the ALT_UART_FCR_DMAM register field value. */ +#define ALT_UART_FCR_DMAM_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_FCR_DMAM register field value. */ +#define ALT_UART_FCR_DMAM_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_FCR_DMAM register field is UNKNOWN. */ +#define ALT_UART_FCR_DMAM_RESET 0x0 +/* Extracts the ALT_UART_FCR_DMAM field value from a register. */ +#define ALT_UART_FCR_DMAM_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_FCR_DMAM register field value suitable for setting the register. */ +#define ALT_UART_FCR_DMAM_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Tx Empty Trigger Level - tet + * + * This is used to select the empty threshold level at which the THRE Interrupts + * will be generated when the mode is active. It also determines when the uart DMA + * transmit request signal uart_dma_tx_req_n will be asserted when in certain modes + * of operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:----------------------- + * ALT_UART_FCR_TET_E_FIFOEMPTY | 0x0 | FIFO empty + * ALT_UART_FCR_TET_E_TWOCHARS | 0x1 | Two characters in FIFO + * ALT_UART_FCR_TET_E_QUARTERFULL | 0x2 | FIFO 1/4 full + * ALT_UART_FCR_TET_E_HALFFULL | 0x3 | FIFO 1/2 full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_TET + * + * FIFO empty + */ +#define ALT_UART_FCR_TET_E_FIFOEMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_TET + * + * Two characters in FIFO + */ +#define ALT_UART_FCR_TET_E_TWOCHARS 0x1 +/* + * Enumerated value for register field ALT_UART_FCR_TET + * + * FIFO 1/4 full + */ +#define ALT_UART_FCR_TET_E_QUARTERFULL 0x2 +/* + * Enumerated value for register field ALT_UART_FCR_TET + * + * FIFO 1/2 full + */ +#define ALT_UART_FCR_TET_E_HALFFULL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_TET register field. */ +#define ALT_UART_FCR_TET_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_TET register field. */ +#define ALT_UART_FCR_TET_MSB 5 +/* The width in bits of the ALT_UART_FCR_TET register field. */ +#define ALT_UART_FCR_TET_WIDTH 2 +/* The mask used to set the ALT_UART_FCR_TET register field value. */ +#define ALT_UART_FCR_TET_SET_MSK 0x00000030 +/* The mask used to clear the ALT_UART_FCR_TET register field value. */ +#define ALT_UART_FCR_TET_CLR_MSK 0xffffffcf +/* The reset value of the ALT_UART_FCR_TET register field is UNKNOWN. */ +#define ALT_UART_FCR_TET_RESET 0x0 +/* Extracts the ALT_UART_FCR_TET field value from a register. */ +#define ALT_UART_FCR_TET_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_UART_FCR_TET register field value suitable for setting the register. */ +#define ALT_UART_FCR_TET_SET(value) (((value) << 4) & 0x00000030) + +/* + * Field : Rx Trigger Level - rt + * + * This register is configured to implement FIFOs. Bits[7:6], Rx Trigger (or RT): + * This is used to select the trigger level in the receiver FIFO at which the + * Received Data Available Interrupt will be generated. In auto flow control mode + * it is used to determine when the uart_rts_n signal will be de-asserted. It also + * determines when the uart_dma_rx_req_n signal will be asserted when in certain + * modes of operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------- + * ALT_UART_FCR_RT_E_ONECHAR | 0x0 | one character in fifo + * ALT_UART_FCR_RT_E_QUARTERFULL | 0x1 | FIFO 1/4 full + * ALT_UART_FCR_RT_E_HALFFULL | 0x2 | FIFO 1/2 full + * ALT_UART_FCR_RT_E_FULLLESS2 | 0x3 | FIFO 2 less than full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_RT + * + * one character in fifo + */ +#define ALT_UART_FCR_RT_E_ONECHAR 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_RT + * + * FIFO 1/4 full + */ +#define ALT_UART_FCR_RT_E_QUARTERFULL 0x1 +/* + * Enumerated value for register field ALT_UART_FCR_RT + * + * FIFO 1/2 full + */ +#define ALT_UART_FCR_RT_E_HALFFULL 0x2 +/* + * Enumerated value for register field ALT_UART_FCR_RT + * + * FIFO 2 less than full + */ +#define ALT_UART_FCR_RT_E_FULLLESS2 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RT register field. */ +#define ALT_UART_FCR_RT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RT register field. */ +#define ALT_UART_FCR_RT_MSB 7 +/* The width in bits of the ALT_UART_FCR_RT register field. */ +#define ALT_UART_FCR_RT_WIDTH 2 +/* The mask used to set the ALT_UART_FCR_RT register field value. */ +#define ALT_UART_FCR_RT_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_UART_FCR_RT register field value. */ +#define ALT_UART_FCR_RT_CLR_MSK 0xffffff3f +/* The reset value of the ALT_UART_FCR_RT register field is UNKNOWN. */ +#define ALT_UART_FCR_RT_RESET 0x0 +/* Extracts the ALT_UART_FCR_RT field value from a register. */ +#define ALT_UART_FCR_RT_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_UART_FCR_RT register field value suitable for setting the register. */ +#define ALT_UART_FCR_RT_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_FCR. + */ +struct ALT_UART_FCR_s +{ + uint32_t fifoe : 1; /* FIFO Enable */ + uint32_t rfifor : 1; /* Rx FIFO Reset */ + uint32_t xfifor : 1; /* Tx FIFO Reset */ + uint32_t dmam : 1; /* DMA Mode */ + uint32_t tet : 2; /* Tx Empty Trigger Level */ + uint32_t rt : 2; /* Rx Trigger Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_FCR. */ +typedef volatile struct ALT_UART_FCR_s ALT_UART_FCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_FCR register from the beginning of the component. */ +#define ALT_UART_FCR_OFST 0x8 +/* The address of the ALT_UART_FCR register. */ +#define ALT_UART_FCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FCR_OFST)) + +/* + * Register : Line Control Register (When Written) - lcr + * + * Formats serial data. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [1:0] | RW | 0x0 | Data Length Select + * [2] | RW | 0x0 | Stop Bits + * [3] | RW | 0x0 | Parity Enable + * [4] | RW | 0x0 | Even Parity Select + * [5] | ??? | 0x0 | *UNDEFINED* + * [6] | RW | 0x0 | Break Control Bit + * [7] | RW | 0x0 | Divisor Latch Access Bit + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Length Select - dls + * + * Data Length Select.Selects the number of data bits per character that the + * peripheral will transmit and receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:------------ + * ALT_UART_LCR_DLS_E_LEN5 | 0x0 | 5 bits + * ALT_UART_LCR_DLS_E_LEN6 | 0x1 | 6 bits + * ALT_UART_LCR_DLS_E_LEN7 | 0x2 | 7 bits + * ALT_UART_LCR_DLS_E_LEN8 | 0x3 | 8 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LCR_DLS + * + * 5 bits + */ +#define ALT_UART_LCR_DLS_E_LEN5 0x0 +/* + * Enumerated value for register field ALT_UART_LCR_DLS + * + * 6 bits + */ +#define ALT_UART_LCR_DLS_E_LEN6 0x1 +/* + * Enumerated value for register field ALT_UART_LCR_DLS + * + * 7 bits + */ +#define ALT_UART_LCR_DLS_E_LEN7 0x2 +/* + * Enumerated value for register field ALT_UART_LCR_DLS + * + * 8 bits + */ +#define ALT_UART_LCR_DLS_E_LEN8 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLS register field. */ +#define ALT_UART_LCR_DLS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLS register field. */ +#define ALT_UART_LCR_DLS_MSB 1 +/* The width in bits of the ALT_UART_LCR_DLS register field. */ +#define ALT_UART_LCR_DLS_WIDTH 2 +/* The mask used to set the ALT_UART_LCR_DLS register field value. */ +#define ALT_UART_LCR_DLS_SET_MSK 0x00000003 +/* The mask used to clear the ALT_UART_LCR_DLS register field value. */ +#define ALT_UART_LCR_DLS_CLR_MSK 0xfffffffc +/* The reset value of the ALT_UART_LCR_DLS register field. */ +#define ALT_UART_LCR_DLS_RESET 0x0 +/* Extracts the ALT_UART_LCR_DLS field value from a register. */ +#define ALT_UART_LCR_DLS_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_UART_LCR_DLS register field value suitable for setting the register. */ +#define ALT_UART_LCR_DLS_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Stop Bits - stop + * + * Number of stop bits. Used to select the number of stop bits per character that + * the peripheral will transmit and receive.Note that regardless of the number of + * stop bits selected the receiver will only check the first stop bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------ + * ALT_UART_LCR_STOP_E_ONESTOP | 0x0 | one stop bit + * ALT_UART_LCR_STOP_E_ONEPOINT5STOP | 0x1 | 1.5 stop bits when DLS (LCR[1:0]) is zero + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LCR_STOP + * + * one stop bit + */ +#define ALT_UART_LCR_STOP_E_ONESTOP 0x0 +/* + * Enumerated value for register field ALT_UART_LCR_STOP + * + * 1.5 stop bits when DLS (LCR[1:0]) is zero + */ +#define ALT_UART_LCR_STOP_E_ONEPOINT5STOP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_STOP register field. */ +#define ALT_UART_LCR_STOP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_STOP register field. */ +#define ALT_UART_LCR_STOP_MSB 2 +/* The width in bits of the ALT_UART_LCR_STOP register field. */ +#define ALT_UART_LCR_STOP_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_STOP register field value. */ +#define ALT_UART_LCR_STOP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_LCR_STOP register field value. */ +#define ALT_UART_LCR_STOP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_LCR_STOP register field. */ +#define ALT_UART_LCR_STOP_RESET 0x0 +/* Extracts the ALT_UART_LCR_STOP field value from a register. */ +#define ALT_UART_LCR_STOP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_LCR_STOP register field value suitable for setting the register. */ +#define ALT_UART_LCR_STOP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Parity Enable - pen + * + * This bit is used to enable and disable parity generation and detection in a + * transmitted and received data character. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:---------------- + * ALT_UART_LCR_PEN_E_DISD | 0x0 | parity disabled + * ALT_UART_LCR_PEN_E_END | 0x1 | parity enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LCR_PEN + * + * parity disabled + */ +#define ALT_UART_LCR_PEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_LCR_PEN + * + * parity enabled + */ +#define ALT_UART_LCR_PEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_PEN register field. */ +#define ALT_UART_LCR_PEN_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_PEN register field. */ +#define ALT_UART_LCR_PEN_MSB 3 +/* The width in bits of the ALT_UART_LCR_PEN register field. */ +#define ALT_UART_LCR_PEN_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_PEN register field value. */ +#define ALT_UART_LCR_PEN_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_LCR_PEN register field value. */ +#define ALT_UART_LCR_PEN_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_LCR_PEN register field. */ +#define ALT_UART_LCR_PEN_RESET 0x0 +/* Extracts the ALT_UART_LCR_PEN field value from a register. */ +#define ALT_UART_LCR_PEN_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_LCR_PEN register field value suitable for setting the register. */ +#define ALT_UART_LCR_PEN_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Even Parity Select - eps + * + * This is used to select between even and odd parity, when parity is enabled (PEN + * set to one). If set to one, an even number of logic '1's is transmitted or + * checked. If set to zero, an odd number of logic '1's is transmitted or checked. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:------------ + * ALT_UART_LCR_EPS_E_ODDPAR | 0x0 | odd parity + * ALT_UART_LCR_EPS_E_EVENPAR | 0x1 | even parity + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LCR_EPS + * + * odd parity + */ +#define ALT_UART_LCR_EPS_E_ODDPAR 0x0 +/* + * Enumerated value for register field ALT_UART_LCR_EPS + * + * even parity + */ +#define ALT_UART_LCR_EPS_E_EVENPAR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_EPS register field. */ +#define ALT_UART_LCR_EPS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_EPS register field. */ +#define ALT_UART_LCR_EPS_MSB 4 +/* The width in bits of the ALT_UART_LCR_EPS register field. */ +#define ALT_UART_LCR_EPS_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_EPS register field value. */ +#define ALT_UART_LCR_EPS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_LCR_EPS register field value. */ +#define ALT_UART_LCR_EPS_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_LCR_EPS register field. */ +#define ALT_UART_LCR_EPS_RESET 0x0 +/* Extracts the ALT_UART_LCR_EPS field value from a register. */ +#define ALT_UART_LCR_EPS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_LCR_EPS register field value suitable for setting the register. */ +#define ALT_UART_LCR_EPS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Break Control Bit - break + * + * This is used to cause a break condition to be transmitted to the receiving + * device. If set to one the serial output is forced to the spacing (logic 0) + * state. When not in Loopback Mode, as determined by MCR[4], the sout line is + * forced low until the Break bit is cleared. When in Loopback Mode, the break + * condition is internally looped back to the receiver and the sir_out_n line is + * forced low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_BREAK register field. */ +#define ALT_UART_LCR_BREAK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_BREAK register field. */ +#define ALT_UART_LCR_BREAK_MSB 6 +/* The width in bits of the ALT_UART_LCR_BREAK register field. */ +#define ALT_UART_LCR_BREAK_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_BREAK register field value. */ +#define ALT_UART_LCR_BREAK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_LCR_BREAK register field value. */ +#define ALT_UART_LCR_BREAK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_LCR_BREAK register field. */ +#define ALT_UART_LCR_BREAK_RESET 0x0 +/* Extracts the ALT_UART_LCR_BREAK field value from a register. */ +#define ALT_UART_LCR_BREAK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_LCR_BREAK register field value suitable for setting the register. */ +#define ALT_UART_LCR_BREAK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Divisor Latch Access Bit - dlab + * + * Used to enable reading and writing of the Divisor Latch register (DLL and DLH) + * to set the baud rate of the UART. This bit must be cleared after initial baud + * rate setup in order to access other registers. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLAB register field. */ +#define ALT_UART_LCR_DLAB_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLAB register field. */ +#define ALT_UART_LCR_DLAB_MSB 7 +/* The width in bits of the ALT_UART_LCR_DLAB register field. */ +#define ALT_UART_LCR_DLAB_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_DLAB register field value. */ +#define ALT_UART_LCR_DLAB_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_LCR_DLAB register field value. */ +#define ALT_UART_LCR_DLAB_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_LCR_DLAB register field. */ +#define ALT_UART_LCR_DLAB_RESET 0x0 +/* Extracts the ALT_UART_LCR_DLAB field value from a register. */ +#define ALT_UART_LCR_DLAB_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_LCR_DLAB register field value suitable for setting the register. */ +#define ALT_UART_LCR_DLAB_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_LCR. + */ +struct ALT_UART_LCR_s +{ + uint32_t dls : 2; /* Data Length Select */ + uint32_t stop : 1; /* Stop Bits */ + uint32_t pen : 1; /* Parity Enable */ + uint32_t eps : 1; /* Even Parity Select */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t break_ : 1; /* Break Control Bit */ + uint32_t dlab : 1; /* Divisor Latch Access Bit */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_LCR. */ +typedef volatile struct ALT_UART_LCR_s ALT_UART_LCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_LCR register from the beginning of the component. */ +#define ALT_UART_LCR_OFST 0xc +/* The address of the ALT_UART_LCR register. */ +#define ALT_UART_LCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LCR_OFST)) + +/* + * Register : Modem Control Register - mcr + * + * Reports various operations of the modem signals + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [0] | RW | 0x0 | Data Terminal Ready + * [1] | RW | 0x0 | Request to Send + * [2] | RW | 0x0 | Out1 + * [3] | RW | 0x0 | out2 + * [4] | RW | 0x0 | LoopBack Bit + * [5] | RW | 0x0 | Auto Flow Control Enable + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Terminal Ready - dtr + * + * This is used to directly control the Data Terminal Ready output. The value + * written to this location is inverted and driven out on uart_dtr_n, that is: The + * Data Terminal Ready output is used to inform the modem or data set that the UART + * is ready to establish communications. + * + * Note that Loopback mode bit [4] of MCR is set to one, the uart_dtr_n output is + * held inactive high while the value of this location is internally looped back + * to an input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:--------------------------------- + * ALT_UART_MCR_DTR_E_LOGIC1 | 0x0 | uart_dtr_n de-asserted (logic 1) + * ALT_UART_MCR_DTR_E_LOGIC0 | 0x1 | uart_dtr_n asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_DTR + * + * uart_dtr_n de-asserted (logic 1) + */ +#define ALT_UART_MCR_DTR_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_DTR + * + * uart_dtr_n asserted (logic 0) + */ +#define ALT_UART_MCR_DTR_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_DTR register field. */ +#define ALT_UART_MCR_DTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_DTR register field. */ +#define ALT_UART_MCR_DTR_MSB 0 +/* The width in bits of the ALT_UART_MCR_DTR register field. */ +#define ALT_UART_MCR_DTR_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_DTR register field value. */ +#define ALT_UART_MCR_DTR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_MCR_DTR register field value. */ +#define ALT_UART_MCR_DTR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_MCR_DTR register field. */ +#define ALT_UART_MCR_DTR_RESET 0x0 +/* Extracts the ALT_UART_MCR_DTR field value from a register. */ +#define ALT_UART_MCR_DTR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_MCR_DTR register field value suitable for setting the register. */ +#define ALT_UART_MCR_DTR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Request to Send - rts + * + * This is used to directly control the Request to Send (uart_rts_n) output. The + * Request to Send (uart_rts_n) output is used to inform the modem or data set that + * the UART is ready to exchange data. When Auto RTS Flow Control is not enabled + * (MCR[5] set to zero), the uart_rts_n signal is set low by programming MCR[1] + * (RTS) to a high. If Auto Flow Control is active (MCR[5] set to one) and FIFO's + * enable (FCR[0] set to one), the uart_rts_n output is controlled in the same way, + * but is also gated with the receiver FIFO threshold trigger (uart_rts_n is + * inactive high when above the threshold). The uart_rts_n signal will be de- + * asserted when MCR[1] is set low. + * + * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held + * inactive high while the value of this location is internally looped back to an + * input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:--------------------------------- + * ALT_UART_MCR_RTS_E_LOGIC1 | 0x0 | uart_rts_n de-asserted (logic 1) + * ALT_UART_MCR_RTS_E_LOGIC0 | 0x1 | uart_rts_n asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_RTS + * + * uart_rts_n de-asserted (logic 1) + */ +#define ALT_UART_MCR_RTS_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_RTS + * + * uart_rts_n asserted (logic 0) + */ +#define ALT_UART_MCR_RTS_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_RTS register field. */ +#define ALT_UART_MCR_RTS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_RTS register field. */ +#define ALT_UART_MCR_RTS_MSB 1 +/* The width in bits of the ALT_UART_MCR_RTS register field. */ +#define ALT_UART_MCR_RTS_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_RTS register field value. */ +#define ALT_UART_MCR_RTS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_MCR_RTS register field value. */ +#define ALT_UART_MCR_RTS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_MCR_RTS register field. */ +#define ALT_UART_MCR_RTS_RESET 0x0 +/* Extracts the ALT_UART_MCR_RTS field value from a register. */ +#define ALT_UART_MCR_RTS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_MCR_RTS register field value suitable for setting the register. */ +#define ALT_UART_MCR_RTS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Out1 - out1 + * + * The value written to this location is inverted and driven out on uart_out1_n + * pin. + * + * Note that in Loopback mode (MCR[4] set to one), the uart_out1_n output is held + * inactive high while the value of this location is internally looped back to an + * input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:---------------------------------- + * ALT_UART_MCR_OUT1_E_LOGIC1 | 0x0 | uart_out1_n de-asserted (logic 1) + * ALT_UART_MCR_OUT1_E_LOGIC0 | 0x1 | uart_out1_n asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_OUT1 + * + * uart_out1_n de-asserted (logic 1) + */ +#define ALT_UART_MCR_OUT1_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_OUT1 + * + * uart_out1_n asserted (logic 0) + */ +#define ALT_UART_MCR_OUT1_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT1 register field. */ +#define ALT_UART_MCR_OUT1_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT1 register field. */ +#define ALT_UART_MCR_OUT1_MSB 2 +/* The width in bits of the ALT_UART_MCR_OUT1 register field. */ +#define ALT_UART_MCR_OUT1_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_OUT1 register field value. */ +#define ALT_UART_MCR_OUT1_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_MCR_OUT1 register field value. */ +#define ALT_UART_MCR_OUT1_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_MCR_OUT1 register field. */ +#define ALT_UART_MCR_OUT1_RESET 0x0 +/* Extracts the ALT_UART_MCR_OUT1 field value from a register. */ +#define ALT_UART_MCR_OUT1_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_MCR_OUT1 register field value suitable for setting the register. */ +#define ALT_UART_MCR_OUT1_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : out2 - out2 + * + * This is used to directly control the user-designated uart_out2_n output. The + * value written to this location is inverted and driven out on uart_out2_n + * + * Note: In Loopback mode bit 4 of the modem control register (MCR) is set to one, + * the uart_out2_n output is held inactive high while the value of this location is + * internally looped back to an input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:---------------------------------- + * ALT_UART_MCR_OUT2_E_LOGIC1 | 0x0 | uart_out2_n de-asserted (logic 1) + * ALT_UART_MCR_OUT2_E_LOGIC0 | 0x1 | uart_out2_n asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_OUT2 + * + * uart_out2_n de-asserted (logic 1) + */ +#define ALT_UART_MCR_OUT2_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_OUT2 + * + * uart_out2_n asserted (logic 0) + */ +#define ALT_UART_MCR_OUT2_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT2 register field. */ +#define ALT_UART_MCR_OUT2_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT2 register field. */ +#define ALT_UART_MCR_OUT2_MSB 3 +/* The width in bits of the ALT_UART_MCR_OUT2 register field. */ +#define ALT_UART_MCR_OUT2_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_OUT2 register field value. */ +#define ALT_UART_MCR_OUT2_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_MCR_OUT2 register field value. */ +#define ALT_UART_MCR_OUT2_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_MCR_OUT2 register field. */ +#define ALT_UART_MCR_OUT2_RESET 0x0 +/* Extracts the ALT_UART_MCR_OUT2 field value from a register. */ +#define ALT_UART_MCR_OUT2_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_MCR_OUT2 register field value suitable for setting the register. */ +#define ALT_UART_MCR_OUT2_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : LoopBack Bit - loopback + * + * This is used to put the UART into a diagnostic mode for test purposes. If UART + * mode is NOT active, bit [6] of the modem control register MCR is set to zero, + * data on the sout line is held high, while serial data output is looped back to + * the sin line, internally. In this mode all the interrupts are fully functional. + * Also, in loopback mode, the modem control inputs (uart_dsr_n, uart_cts_n, + * uart_ri_n, uart_dcd_n) are disconnected and the modem control outputs + * (uart_dtr_n, uart_rts_n, uart_out1_n, uart_out2_n) are loopedback to the inputs, + * internally. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_LOOPBACK register field. */ +#define ALT_UART_MCR_LOOPBACK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_LOOPBACK register field. */ +#define ALT_UART_MCR_LOOPBACK_MSB 4 +/* The width in bits of the ALT_UART_MCR_LOOPBACK register field. */ +#define ALT_UART_MCR_LOOPBACK_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_LOOPBACK register field value. */ +#define ALT_UART_MCR_LOOPBACK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_MCR_LOOPBACK register field value. */ +#define ALT_UART_MCR_LOOPBACK_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_MCR_LOOPBACK register field. */ +#define ALT_UART_MCR_LOOPBACK_RESET 0x0 +/* Extracts the ALT_UART_MCR_LOOPBACK field value from a register. */ +#define ALT_UART_MCR_LOOPBACK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_MCR_LOOPBACK register field value suitable for setting the register. */ +#define ALT_UART_MCR_LOOPBACK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Auto Flow Control Enable - afce + * + * When FIFOs are enabled, the Auto Flow Control enable bits are active. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:-------------------------------- + * ALT_UART_MCR_AFCE_E_DISD | 0x0 | Auto Flow Control Mode disabled + * ALT_UART_MCR_AFCE_E_END | 0x1 | Auto Flow Control Mode enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_AFCE + * + * Auto Flow Control Mode disabled + */ +#define ALT_UART_MCR_AFCE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_AFCE + * + * Auto Flow Control Mode enabled + */ +#define ALT_UART_MCR_AFCE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_AFCE register field. */ +#define ALT_UART_MCR_AFCE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_AFCE register field. */ +#define ALT_UART_MCR_AFCE_MSB 5 +/* The width in bits of the ALT_UART_MCR_AFCE register field. */ +#define ALT_UART_MCR_AFCE_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_AFCE register field value. */ +#define ALT_UART_MCR_AFCE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_MCR_AFCE register field value. */ +#define ALT_UART_MCR_AFCE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_MCR_AFCE register field. */ +#define ALT_UART_MCR_AFCE_RESET 0x0 +/* Extracts the ALT_UART_MCR_AFCE field value from a register. */ +#define ALT_UART_MCR_AFCE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_MCR_AFCE register field value suitable for setting the register. */ +#define ALT_UART_MCR_AFCE_SET(value) (((value) << 5) & 0x00000020) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_MCR. + */ +struct ALT_UART_MCR_s +{ + uint32_t dtr : 1; /* Data Terminal Ready */ + uint32_t rts : 1; /* Request to Send */ + uint32_t out1 : 1; /* Out1 */ + uint32_t out2 : 1; /* out2 */ + uint32_t loopback : 1; /* LoopBack Bit */ + uint32_t afce : 1; /* Auto Flow Control Enable */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_MCR. */ +typedef volatile struct ALT_UART_MCR_s ALT_UART_MCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_MCR register from the beginning of the component. */ +#define ALT_UART_MCR_OFST 0x10 +/* The address of the ALT_UART_MCR register. */ +#define ALT_UART_MCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MCR_OFST)) + +/* + * Register : Line Status Register - lsr + * + * Reports status of transmit and receive. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | R | 0x0 | Data Ready bit + * [1] | R | 0x0 | Overrun error + * [2] | R | 0x0 | Parity Error + * [3] | R | 0x0 | Framing Error + * [4] | R | 0x0 | Break Interrupt + * [5] | R | 0x1 | Transmit Holding Register Empty bit + * [6] | R | 0x1 | Transmitter Empty bit + * [7] | R | 0x0 | Receiver FIFO Error bit + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Ready bit - dr + * + * This is used to indicate that the receiver contains at least one character in + * the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the + * non-FIFO mode, or when the receiver FIFO is empty, in the FIFO mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------- + * ALT_UART_LSR_DR_E_NODATARDY | 0x0 | no data ready + * ALT_UART_LSR_DR_E_DATARDY | 0x1 | data ready + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_DR + * + * no data ready + */ +#define ALT_UART_LSR_DR_E_NODATARDY 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_DR + * + * data ready + */ +#define ALT_UART_LSR_DR_E_DATARDY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_DR register field. */ +#define ALT_UART_LSR_DR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_DR register field. */ +#define ALT_UART_LSR_DR_MSB 0 +/* The width in bits of the ALT_UART_LSR_DR register field. */ +#define ALT_UART_LSR_DR_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_DR register field value. */ +#define ALT_UART_LSR_DR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_LSR_DR register field value. */ +#define ALT_UART_LSR_DR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_LSR_DR register field. */ +#define ALT_UART_LSR_DR_RESET 0x0 +/* Extracts the ALT_UART_LSR_DR field value from a register. */ +#define ALT_UART_LSR_DR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_LSR_DR register field value suitable for setting the register. */ +#define ALT_UART_LSR_DR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Overrun error - oe + * + * This is used to indicate the occurrence of an overrun error. This occurs if a + * new data character was received before the previous data was read. In the non- + * FIFO mode, the OE bit is set when a new character arrives in the receiver before + * the previous character was read from the RBR. When this happens, the data in the + * RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is + * full and new character arrives at the receiver. The data in the FIFO is retained + * and the data in the receive shift register is lost.Reading the LSR clears the OE + * bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------- + * ALT_UART_LSR_OE_E_NOOVERRUN | 0x0 | no overrun error + * ALT_UART_LSR_OE_E_OVERRUN | 0x1 | overrun error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_OE + * + * no overrun error + */ +#define ALT_UART_LSR_OE_E_NOOVERRUN 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_OE + * + * overrun error + */ +#define ALT_UART_LSR_OE_E_OVERRUN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_OE register field. */ +#define ALT_UART_LSR_OE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_OE register field. */ +#define ALT_UART_LSR_OE_MSB 1 +/* The width in bits of the ALT_UART_LSR_OE register field. */ +#define ALT_UART_LSR_OE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_OE register field value. */ +#define ALT_UART_LSR_OE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_LSR_OE register field value. */ +#define ALT_UART_LSR_OE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_LSR_OE register field. */ +#define ALT_UART_LSR_OE_RESET 0x0 +/* Extracts the ALT_UART_LSR_OE field value from a register. */ +#define ALT_UART_LSR_OE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_LSR_OE register field value suitable for setting the register. */ +#define ALT_UART_LSR_OE_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Parity Error - pe + * + * This is used to indicate the occurrence of a parity error in the receiver if the + * Parity Enable (PEN) bit (LCR[3]) is set. Since the parity error is associated + * with a character received, it is revealed when the character with the parity + * error arrives at the top of the FIFO. It should be noted that the Parity Error + * (PE) bit (LSR[2]) will be set if a break interrupt has occurred, as indicated by + * Break Interrupt (BI) bit (LSR[4]). Reading the LSR clears the PE bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------- + * ALT_UART_LSR_PE_E_NOPARITYERR | 0x0 | no parity error + * ALT_UART_LSR_PE_E_PARITYERR | 0x1 | no parity error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_PE + * + * no parity error + */ +#define ALT_UART_LSR_PE_E_NOPARITYERR 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_PE + * + * no parity error + */ +#define ALT_UART_LSR_PE_E_PARITYERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_PE register field. */ +#define ALT_UART_LSR_PE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_PE register field. */ +#define ALT_UART_LSR_PE_MSB 2 +/* The width in bits of the ALT_UART_LSR_PE register field. */ +#define ALT_UART_LSR_PE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_PE register field value. */ +#define ALT_UART_LSR_PE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_LSR_PE register field value. */ +#define ALT_UART_LSR_PE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_LSR_PE register field. */ +#define ALT_UART_LSR_PE_RESET 0x0 +/* Extracts the ALT_UART_LSR_PE field value from a register. */ +#define ALT_UART_LSR_PE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_LSR_PE register field value suitable for setting the register. */ +#define ALT_UART_LSR_PE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Framing Error - fe + * + * This is used to indicate the occurrence of a framing error in the receiver. A + * framing error occurs when the receiver does not detect a valid STOP bit in the + * received data. In the FIFO mode, since the framing error is associated with a + * character received, it is revealed when the character with the framing error is + * at the top of the FIFO. When a framing error occurs the UART will try to + * resynchronize. It does this by assuming that the error was due to the start bit + * of the next character and then continues receiving the other bit i.e. data, + * and/or parity and stop. It should be noted that the Framing Error (FE) + * bit(LSR[3]) will be set if a break interrupt has occurred, as indicated by a + * Break Interrupt BIT bit (LSR[4]). Reading the LSR clears the FE bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------- + * ALT_UART_LSR_FE_E_NOFRMERR | 0x0 | no framing error + * ALT_UART_LSR_FE_E_FRMERR | 0x1 | framing error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_FE + * + * no framing error + */ +#define ALT_UART_LSR_FE_E_NOFRMERR 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_FE + * + * framing error + */ +#define ALT_UART_LSR_FE_E_FRMERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_FE register field. */ +#define ALT_UART_LSR_FE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_FE register field. */ +#define ALT_UART_LSR_FE_MSB 3 +/* The width in bits of the ALT_UART_LSR_FE register field. */ +#define ALT_UART_LSR_FE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_FE register field value. */ +#define ALT_UART_LSR_FE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_LSR_FE register field value. */ +#define ALT_UART_LSR_FE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_LSR_FE register field. */ +#define ALT_UART_LSR_FE_RESET 0x0 +/* Extracts the ALT_UART_LSR_FE field value from a register. */ +#define ALT_UART_LSR_FE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_LSR_FE register field value suitable for setting the register. */ +#define ALT_UART_LSR_FE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Break Interrupt - bi + * + * This is used to indicate the detection of a break sequence on the serial input + * data. Set whenever the serial input, sin, is held in a logic 0 state for longer + * than the sum of start time + data bits + parity + stop bits. A break condition + * on serial input causes one and only one character, consisting of all zeros, to + * be received by the UART. The character associated with the break condition is + * carried through the FIFO and is revealed when the character is at the top of the + * FIFO. Reading the LSR clears the BI bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_BI register field. */ +#define ALT_UART_LSR_BI_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_BI register field. */ +#define ALT_UART_LSR_BI_MSB 4 +/* The width in bits of the ALT_UART_LSR_BI register field. */ +#define ALT_UART_LSR_BI_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_BI register field value. */ +#define ALT_UART_LSR_BI_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_LSR_BI register field value. */ +#define ALT_UART_LSR_BI_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_LSR_BI register field. */ +#define ALT_UART_LSR_BI_RESET 0x0 +/* Extracts the ALT_UART_LSR_BI field value from a register. */ +#define ALT_UART_LSR_BI_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_LSR_BI register field value suitable for setting the register. */ +#define ALT_UART_LSR_BI_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Transmit Holding Register Empty bit - thre + * + * If THRE mode is disabled (IER[7] set to zero) this bit indicates that the THR or + * Tx FIFO is empty. This bit is set whenever data is transferred from the THR or + * Tx FIFO to the transmitter shift register and no new data has been written to + * the THR or Tx FIFO. This also causes a THRE Interrupt to occur, if the THRE + * Interrupt is enabled. If both THRE and FIFOs are enabled, both (IER[7] set to + * one and FCR[0] set to one respectively), the functionality will indicate the + * transmitter FIFO is full, and no longer controls THRE interrupts, which are then + * controlled by the FCR[5:4] thresholdsetting. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_THRE register field. */ +#define ALT_UART_LSR_THRE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_THRE register field. */ +#define ALT_UART_LSR_THRE_MSB 5 +/* The width in bits of the ALT_UART_LSR_THRE register field. */ +#define ALT_UART_LSR_THRE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_THRE register field value. */ +#define ALT_UART_LSR_THRE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_LSR_THRE register field value. */ +#define ALT_UART_LSR_THRE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_LSR_THRE register field. */ +#define ALT_UART_LSR_THRE_RESET 0x1 +/* Extracts the ALT_UART_LSR_THRE field value from a register. */ +#define ALT_UART_LSR_THRE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_LSR_THRE register field value suitable for setting the register. */ +#define ALT_UART_LSR_THRE_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transmitter Empty bit - temt + * + * If in FIFO mode and FIFO's enabled (FCR[0] set to one), this bit is set whenever + * the Transmitter Shift Register and the FIFO are both empty. If FIFO's are + * disabled, this bit is set whenever the Transmitter Holding Register and the + * Transmitter Shift Register are both empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:----------------------- + * ALT_UART_LSR_TEMT_E_NOTEMPTY | 0x0 | Transmit Empty not set + * ALT_UART_LSR_TEMT_E_EMPTY | 0x1 | Transmit Empty set + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_TEMT + * + * Transmit Empty not set + */ +#define ALT_UART_LSR_TEMT_E_NOTEMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_TEMT + * + * Transmit Empty set + */ +#define ALT_UART_LSR_TEMT_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_TEMT register field. */ +#define ALT_UART_LSR_TEMT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_TEMT register field. */ +#define ALT_UART_LSR_TEMT_MSB 6 +/* The width in bits of the ALT_UART_LSR_TEMT register field. */ +#define ALT_UART_LSR_TEMT_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_TEMT register field value. */ +#define ALT_UART_LSR_TEMT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_LSR_TEMT register field value. */ +#define ALT_UART_LSR_TEMT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_LSR_TEMT register field. */ +#define ALT_UART_LSR_TEMT_RESET 0x1 +/* Extracts the ALT_UART_LSR_TEMT field value from a register. */ +#define ALT_UART_LSR_TEMT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_LSR_TEMT register field value suitable for setting the register. */ +#define ALT_UART_LSR_TEMT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receiver FIFO Error bit - rfe + * + * This bit is only relevant when FIFO's are enabled (FCR[0] set to one). This is + * used to indicate if there is at least one parity error, framing error, or break + * indication in the FIFO. This bit is cleared when the LSR is read and the + * character with the error is at the top of the receiver FIFO and there are no + * subsequent errors in the FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:-------------------- + * ALT_UART_LSR_RFE_E_NOERR | 0x0 | no error in Rx FIFO + * ALT_UART_LSR_RFE_E_ERR | 0x1 | error in Rx FIFO + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_RFE + * + * no error in Rx FIFO + */ +#define ALT_UART_LSR_RFE_E_NOERR 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_RFE + * + * error in Rx FIFO + */ +#define ALT_UART_LSR_RFE_E_ERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_RFE register field. */ +#define ALT_UART_LSR_RFE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_RFE register field. */ +#define ALT_UART_LSR_RFE_MSB 7 +/* The width in bits of the ALT_UART_LSR_RFE register field. */ +#define ALT_UART_LSR_RFE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_RFE register field value. */ +#define ALT_UART_LSR_RFE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_LSR_RFE register field value. */ +#define ALT_UART_LSR_RFE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_LSR_RFE register field. */ +#define ALT_UART_LSR_RFE_RESET 0x0 +/* Extracts the ALT_UART_LSR_RFE field value from a register. */ +#define ALT_UART_LSR_RFE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_LSR_RFE register field value suitable for setting the register. */ +#define ALT_UART_LSR_RFE_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_LSR. + */ +struct ALT_UART_LSR_s +{ + const uint32_t dr : 1; /* Data Ready bit */ + const uint32_t oe : 1; /* Overrun error */ + const uint32_t pe : 1; /* Parity Error */ + const uint32_t fe : 1; /* Framing Error */ + const uint32_t bi : 1; /* Break Interrupt */ + const uint32_t thre : 1; /* Transmit Holding Register Empty bit */ + const uint32_t temt : 1; /* Transmitter Empty bit */ + const uint32_t rfe : 1; /* Receiver FIFO Error bit */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_LSR. */ +typedef volatile struct ALT_UART_LSR_s ALT_UART_LSR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_LSR register from the beginning of the component. */ +#define ALT_UART_LSR_OFST 0x14 +/* The address of the ALT_UART_LSR register. */ +#define ALT_UART_LSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LSR_OFST)) + +/* + * Register : Modem Status Register - msr + * + * It should be noted that whenever bits 0, 1, 2 or 3 are set to logic one, to + * indicate a change on the modem control inputs, a modem status interrupt will be + * generated if enabled via the IER regardless of when the change occurred. Since + * the delta bits (bits 0, 1, 3) can get set after a reset if their respective + * modem signals are active (see individual bits for details), a read of the MSR + * after reset can be performed to prevent unwanted interrupts. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [0] | R | 0x0 | Delta Clear to Send + * [1] | R | 0x0 | Delta Data Set Ready + * [2] | R | 0x0 | Trailing Edge of Ring Indicator + * [3] | R | 0x0 | Delta Data Carrier Detect + * [4] | R | 0x0 | Clear to Send + * [5] | R | 0x0 | Data Set Ready + * [6] | R | 0x0 | Ring Indicator + * [7] | R | 0x0 | Data Carrier Detect + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Delta Clear to Send - dcts + * + * This is used to indicate that the modem control line uart_cts_n has changed + * since the last time the MSR was read. That is: Reading the MSR clears the DCTS + * bit. In Loopback Mode bit [4] of MCR set to one, DCTS reflects changes on bit + * [1] RTS of register MCR. + * + * Note: If the DCTS bit is not set and the uart_cts_n signal is asserted (low) and + * a reset occurs (software or otherwise), then the DCTS bit will get set when the + * reset is removed if the uart_cts_n signal remains asserted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------------------------------------- + * ALT_UART_MSR_DCTS_E_NOCHG | 0x0 | no change on uart_cts_n since last read of MSR + * ALT_UART_MSR_DCTS_E_CHG | 0x1 | change on uart_cts_n since last read of MSR + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DCTS + * + * no change on uart_cts_n since last read of MSR + */ +#define ALT_UART_MSR_DCTS_E_NOCHG 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DCTS + * + * change on uart_cts_n since last read of MSR + */ +#define ALT_UART_MSR_DCTS_E_CHG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCTS register field. */ +#define ALT_UART_MSR_DCTS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCTS register field. */ +#define ALT_UART_MSR_DCTS_MSB 0 +/* The width in bits of the ALT_UART_MSR_DCTS register field. */ +#define ALT_UART_MSR_DCTS_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DCTS register field value. */ +#define ALT_UART_MSR_DCTS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_MSR_DCTS register field value. */ +#define ALT_UART_MSR_DCTS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_MSR_DCTS register field. */ +#define ALT_UART_MSR_DCTS_RESET 0x0 +/* Extracts the ALT_UART_MSR_DCTS field value from a register. */ +#define ALT_UART_MSR_DCTS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_MSR_DCTS register field value suitable for setting the register. */ +#define ALT_UART_MSR_DCTS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Delta Data Set Ready - ddsr + * + * This is used to indicate that the modem control line uart_dsr_n has changed + * since the last time the MSR was read. Reading the MSR clears the DDSR bit.In + * Loopback Mode (MCR[4] set to one), DDSR reflects changes on bit [0] DTR of + * register MCR . + * + * Note, if the DDSR bit is not set and the uart_dsr_n signal is asserted (low) and + * a reset occurs (software or otherwise), then the DDSR bit will get set when the + * reset is removed if the uart_dsr_n signal remains asserted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------------------------------------- + * ALT_UART_MSR_DDSR_E_NOCHG | 0x0 | no change on uart_dsr_n since last read of MSR + * ALT_UART_MSR_DDSR_E_CHG | 0x1 | change on uart_dsr_n since last read of MSR + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DDSR + * + * no change on uart_dsr_n since last read of MSR + */ +#define ALT_UART_MSR_DDSR_E_NOCHG 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DDSR + * + * change on uart_dsr_n since last read of MSR + */ +#define ALT_UART_MSR_DDSR_E_CHG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDSR register field. */ +#define ALT_UART_MSR_DDSR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDSR register field. */ +#define ALT_UART_MSR_DDSR_MSB 1 +/* The width in bits of the ALT_UART_MSR_DDSR register field. */ +#define ALT_UART_MSR_DDSR_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DDSR register field value. */ +#define ALT_UART_MSR_DDSR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_MSR_DDSR register field value. */ +#define ALT_UART_MSR_DDSR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_MSR_DDSR register field. */ +#define ALT_UART_MSR_DDSR_RESET 0x0 +/* Extracts the ALT_UART_MSR_DDSR field value from a register. */ +#define ALT_UART_MSR_DDSR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_MSR_DDSR register field value suitable for setting the register. */ +#define ALT_UART_MSR_DDSR_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Trailing Edge of Ring Indicator - teri + * + * This is used to indicate that a change on the input uart_ri_n (from an active + * low, to an inactive high state) has occurred since the last time the MSR was + * read. Reading the MSR clears the TERI bit. In Loopback Mode bit [4] of register + * MCR is set to one, TERI reflects when bit [2] of register MCR has changed state + * from a high to a low. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:---------------------------------------------- + * ALT_UART_MSR_TERI_E_NOCHG | 0x0 | no change on uart_ri_n since last read of MSR + * ALT_UART_MSR_TERI_E_CHG | 0x1 | change on uart_ri_n since last read of MSR + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_TERI + * + * no change on uart_ri_n since last read of MSR + */ +#define ALT_UART_MSR_TERI_E_NOCHG 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_TERI + * + * change on uart_ri_n since last read of MSR + */ +#define ALT_UART_MSR_TERI_E_CHG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_TERI register field. */ +#define ALT_UART_MSR_TERI_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_TERI register field. */ +#define ALT_UART_MSR_TERI_MSB 2 +/* The width in bits of the ALT_UART_MSR_TERI register field. */ +#define ALT_UART_MSR_TERI_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_TERI register field value. */ +#define ALT_UART_MSR_TERI_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_MSR_TERI register field value. */ +#define ALT_UART_MSR_TERI_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_MSR_TERI register field. */ +#define ALT_UART_MSR_TERI_RESET 0x0 +/* Extracts the ALT_UART_MSR_TERI field value from a register. */ +#define ALT_UART_MSR_TERI_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_MSR_TERI register field value suitable for setting the register. */ +#define ALT_UART_MSR_TERI_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Delta Data Carrier Detect - ddcd + * + * This is used to indicate that the modem control line dcd_n has changed since the + * last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback + * Mode bit [4] of register MCR is set to one, DDCD reflects changes bit [3] + * uart_out2 of register MCR. + * + * Note: If the DDCD bit is not set and the uart_dcd_n signal is asserted (low) and + * a reset occurs (software or otherwise), then the DDCD bit will get set when the + * reset is removed if the uart_dcd_n signal remains asserted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------------------------------------- + * ALT_UART_MSR_DDCD_E_NOCHG | 0x0 | no change on uart_dcd_n since last read of MSR + * ALT_UART_MSR_DDCD_E_CHG | 0x1 | change on uart_dcd_n since last read of MSR + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DDCD + * + * no change on uart_dcd_n since last read of MSR + */ +#define ALT_UART_MSR_DDCD_E_NOCHG 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DDCD + * + * change on uart_dcd_n since last read of MSR + */ +#define ALT_UART_MSR_DDCD_E_CHG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDCD register field. */ +#define ALT_UART_MSR_DDCD_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDCD register field. */ +#define ALT_UART_MSR_DDCD_MSB 3 +/* The width in bits of the ALT_UART_MSR_DDCD register field. */ +#define ALT_UART_MSR_DDCD_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DDCD register field value. */ +#define ALT_UART_MSR_DDCD_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_MSR_DDCD register field value. */ +#define ALT_UART_MSR_DDCD_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_MSR_DDCD register field. */ +#define ALT_UART_MSR_DDCD_RESET 0x0 +/* Extracts the ALT_UART_MSR_DDCD field value from a register. */ +#define ALT_UART_MSR_DDCD_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_MSR_DDCD register field value suitable for setting the register. */ +#define ALT_UART_MSR_DDCD_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Clear to Send - cts + * + * This is used to indicate the current state of the modem control line uart_cts_n. + * That is, this bit is the complement uart_cts_n. When the Clear to Send input + * (uart_cts_n) is asserted it is an indication that the modem or data set is ready + * to exchange data with the uart. In Loopback Mode bit [4] of register MCR is set + * to one, CTS is the same as bit [1] RTS of register MCR. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------------------------ + * ALT_UART_MSR_CTS_E_LOGIC1 | 0x0 | uart_cts_n input is de-asserted (logic 1) + * ALT_UART_MSR_CTS_E_LOGIC0 | 0x1 | uart_cts_n input is asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_CTS + * + * uart_cts_n input is de-asserted (logic 1) + */ +#define ALT_UART_MSR_CTS_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_CTS + * + * uart_cts_n input is asserted (logic 0) + */ +#define ALT_UART_MSR_CTS_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_CTS register field. */ +#define ALT_UART_MSR_CTS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_CTS register field. */ +#define ALT_UART_MSR_CTS_MSB 4 +/* The width in bits of the ALT_UART_MSR_CTS register field. */ +#define ALT_UART_MSR_CTS_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_CTS register field value. */ +#define ALT_UART_MSR_CTS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_MSR_CTS register field value. */ +#define ALT_UART_MSR_CTS_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_MSR_CTS register field. */ +#define ALT_UART_MSR_CTS_RESET 0x0 +/* Extracts the ALT_UART_MSR_CTS field value from a register. */ +#define ALT_UART_MSR_CTS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_MSR_CTS register field value suitable for setting the register. */ +#define ALT_UART_MSR_CTS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Data Set Ready - dsr + * + * This is used to indicate the current state of the modem control line uart_dsr_n. + * That is this bit is the complement f uart_dsr_n. When the Data Set Ready input + * (uart_dsr_n) is asserted it is an indication that the modem or data set is ready + * to establish communications with the uart. In Loopback Mode bit [4] of register + * MCR is set to one, DSR is the same as bit [0] (DTR) of register MCR. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------------------------ + * ALT_UART_MSR_DSR_E_LOGIC1 | 0x0 | uart_dsr_n input is de-asserted (logic 1) + * ALT_UART_MSR_DSR_E_LOGIC0 | 0x1 | uart_dsr_n input is asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DSR + * + * uart_dsr_n input is de-asserted (logic 1) + */ +#define ALT_UART_MSR_DSR_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DSR + * + * uart_dsr_n input is asserted (logic 0) + */ +#define ALT_UART_MSR_DSR_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DSR register field. */ +#define ALT_UART_MSR_DSR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DSR register field. */ +#define ALT_UART_MSR_DSR_MSB 5 +/* The width in bits of the ALT_UART_MSR_DSR register field. */ +#define ALT_UART_MSR_DSR_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DSR register field value. */ +#define ALT_UART_MSR_DSR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_MSR_DSR register field value. */ +#define ALT_UART_MSR_DSR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_MSR_DSR register field. */ +#define ALT_UART_MSR_DSR_RESET 0x0 +/* Extracts the ALT_UART_MSR_DSR field value from a register. */ +#define ALT_UART_MSR_DSR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_MSR_DSR register field value suitable for setting the register. */ +#define ALT_UART_MSR_DSR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Ring Indicator - ri + * + * This bit is used to indicate the current state of the modem control line + * uart_ri_n. That is this bit is the complement uart_ri_n. When the Ring Indicator + * input (uart_ri_n) is asserted it is an indication that a telephone ringing + * signal has been received by the modem or data set. In Loopback Mode bit [4] of + * register MCR set to one, RI is the same as bit [2] uart_out1_n of register MCR. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------------------------------- + * ALT_UART_MSR_RI_E_LOGIC1 | 0x0 | uart_ri_n input is de-asserted (logic 1) + * ALT_UART_MSR_RI_E_LOGIC0 | 0x1 | uart_ri_n input is asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_RI + * + * uart_ri_n input is de-asserted (logic 1) + */ +#define ALT_UART_MSR_RI_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_RI + * + * uart_ri_n input is asserted (logic 0) + */ +#define ALT_UART_MSR_RI_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_RI register field. */ +#define ALT_UART_MSR_RI_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_RI register field. */ +#define ALT_UART_MSR_RI_MSB 6 +/* The width in bits of the ALT_UART_MSR_RI register field. */ +#define ALT_UART_MSR_RI_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_RI register field value. */ +#define ALT_UART_MSR_RI_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_MSR_RI register field value. */ +#define ALT_UART_MSR_RI_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_MSR_RI register field. */ +#define ALT_UART_MSR_RI_RESET 0x0 +/* Extracts the ALT_UART_MSR_RI field value from a register. */ +#define ALT_UART_MSR_RI_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_MSR_RI register field value suitable for setting the register. */ +#define ALT_UART_MSR_RI_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Data Carrier Detect - dcd + * + * This is used to indicate the current state of the modem control line uart_dcd_n. + * That is this bit is the complement uart_dcd_n. When the Data Carrier Detect + * input (uart_dcd_n) is asserted it is an indication that the carrier has been + * detected by the modem or data set. In Loopback Mode (MCR[4] set to one), DCD is + * the same as MCR[3] (uart_out2). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------------------------ + * ALT_UART_MSR_DCD_E_LOGIC1 | 0x0 | uart_dcd_n input is de-asserted (logic 1) + * ALT_UART_MSR_DCD_E_LOGIC0 | 0x1 | uart_dcd_n input is asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DCD + * + * uart_dcd_n input is de-asserted (logic 1) + */ +#define ALT_UART_MSR_DCD_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DCD + * + * uart_dcd_n input is asserted (logic 0) + */ +#define ALT_UART_MSR_DCD_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCD register field. */ +#define ALT_UART_MSR_DCD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCD register field. */ +#define ALT_UART_MSR_DCD_MSB 7 +/* The width in bits of the ALT_UART_MSR_DCD register field. */ +#define ALT_UART_MSR_DCD_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DCD register field value. */ +#define ALT_UART_MSR_DCD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_MSR_DCD register field value. */ +#define ALT_UART_MSR_DCD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_MSR_DCD register field. */ +#define ALT_UART_MSR_DCD_RESET 0x0 +/* Extracts the ALT_UART_MSR_DCD field value from a register. */ +#define ALT_UART_MSR_DCD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_MSR_DCD register field value suitable for setting the register. */ +#define ALT_UART_MSR_DCD_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_MSR. + */ +struct ALT_UART_MSR_s +{ + const uint32_t dcts : 1; /* Delta Clear to Send */ + const uint32_t ddsr : 1; /* Delta Data Set Ready */ + const uint32_t teri : 1; /* Trailing Edge of Ring Indicator */ + const uint32_t ddcd : 1; /* Delta Data Carrier Detect */ + const uint32_t cts : 1; /* Clear to Send */ + const uint32_t dsr : 1; /* Data Set Ready */ + const uint32_t ri : 1; /* Ring Indicator */ + const uint32_t dcd : 1; /* Data Carrier Detect */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_MSR. */ +typedef volatile struct ALT_UART_MSR_s ALT_UART_MSR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_MSR register from the beginning of the component. */ +#define ALT_UART_MSR_OFST 0x18 +/* The address of the ALT_UART_MSR register. */ +#define ALT_UART_MSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MSR_OFST)) + +/* + * Register : Scratchpad Register - scr + * + * Scratchpad Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [7:0] | RW | 0x0 | Scratchpad Register + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Scratchpad Register - scr + * + * This register is for programmers to use as a temporary storage space. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_SCR_SCR register field. */ +#define ALT_UART_SCR_SCR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SCR_SCR register field. */ +#define ALT_UART_SCR_SCR_MSB 7 +/* The width in bits of the ALT_UART_SCR_SCR register field. */ +#define ALT_UART_SCR_SCR_WIDTH 8 +/* The mask used to set the ALT_UART_SCR_SCR register field value. */ +#define ALT_UART_SCR_SCR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_SCR_SCR register field value. */ +#define ALT_UART_SCR_SCR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_SCR_SCR register field. */ +#define ALT_UART_SCR_SCR_RESET 0x0 +/* Extracts the ALT_UART_SCR_SCR field value from a register. */ +#define ALT_UART_SCR_SCR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_SCR_SCR register field value suitable for setting the register. */ +#define ALT_UART_SCR_SCR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SCR. + */ +struct ALT_UART_SCR_s +{ + uint32_t scr : 8; /* Scratchpad Register */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SCR. */ +typedef volatile struct ALT_UART_SCR_s ALT_UART_SCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SCR register from the beginning of the component. */ +#define ALT_UART_SCR_OFST 0x1c +/* The address of the ALT_UART_SCR register. */ +#define ALT_UART_SCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SCR_OFST)) + +/* + * Register : Shadow Receive Buffer Register - srbr + * + * Used to accomadate burst accesses from the master. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [7:0] | RW | 0x0 | Shadow Receive Buffer + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Receive Buffer - srbr + * + * This is a shadow register for the RBR and has been allocated one 32-bit location + * so as to accommodate burst accesses from the master.This register contains the + * data byte received on the serial input port (sin). The data in this register is + * valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. + * If FIFOs are disabled, bit [0] of register FCR set to zero, the data in the RBR + * must be read before the next data arrives, otherwise it will be overwritten, + * resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this + * register accesses the head of the receive FIFO. If the receive FIFO is full and + * this register is not read before the next data character arrives, then the data + * already in the FIFO will be preserved but any incoming data will be lost. An + * overrun error will also occur. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_SRBR register field. */ +#define ALT_UART_SRBR_SRBR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_SRBR register field. */ +#define ALT_UART_SRBR_SRBR_MSB 7 +/* The width in bits of the ALT_UART_SRBR_SRBR register field. */ +#define ALT_UART_SRBR_SRBR_WIDTH 8 +/* The mask used to set the ALT_UART_SRBR_SRBR register field value. */ +#define ALT_UART_SRBR_SRBR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_SRBR_SRBR register field value. */ +#define ALT_UART_SRBR_SRBR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_SRBR_SRBR register field. */ +#define ALT_UART_SRBR_SRBR_RESET 0x0 +/* Extracts the ALT_UART_SRBR_SRBR field value from a register. */ +#define ALT_UART_SRBR_SRBR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_SRBR_SRBR register field value suitable for setting the register. */ +#define ALT_UART_SRBR_SRBR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SRBR. + */ +struct ALT_UART_SRBR_s +{ + uint32_t srbr : 8; /* Shadow Receive Buffer */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SRBR. */ +typedef volatile struct ALT_UART_SRBR_s ALT_UART_SRBR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SRBR register from the beginning of the component. */ +#define ALT_UART_SRBR_OFST 0x30 +/* The address of the ALT_UART_SRBR register. */ +#define ALT_UART_SRBR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_OFST)) + +/* + * Register : Shadow Transmit Buffer Register - sthr + * + * Used to accomadate burst accesses from the master. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [7:0] | RW | 0x0 | Shadow Transmit Buffer + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Transmit Buffer - sthr + * + * This is a shadow register for the THR and has been allocated sixteen 32-bit + * locations so as to accommodate burst accesses from the master. This register + * contains data to be transmitted on the serial output port (sout). Data should + * only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If + * FIFO's are disabled bit [0] of register FCR set to zero and THRE is set, writing + * a single character to the THR clears the THRE. Any additional writes to the THR + * before the THRE is set again causes the THR data to be overwritten. If FIFO's + * are enabled bit [0] of register FCR set to one and THRE is set, 128 characters + * of data may be written to the THR before the FIFO is full. The UART FIFO depth + * is configured for 128 characters. Any attempt to write data when the FIFO is + * full results in the write data being lost. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_STHR_STHR register field. */ +#define ALT_UART_STHR_STHR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_STHR_STHR register field. */ +#define ALT_UART_STHR_STHR_MSB 7 +/* The width in bits of the ALT_UART_STHR_STHR register field. */ +#define ALT_UART_STHR_STHR_WIDTH 8 +/* The mask used to set the ALT_UART_STHR_STHR register field value. */ +#define ALT_UART_STHR_STHR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_STHR_STHR register field value. */ +#define ALT_UART_STHR_STHR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_STHR_STHR register field. */ +#define ALT_UART_STHR_STHR_RESET 0x0 +/* Extracts the ALT_UART_STHR_STHR field value from a register. */ +#define ALT_UART_STHR_STHR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_STHR_STHR register field value suitable for setting the register. */ +#define ALT_UART_STHR_STHR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_STHR. + */ +struct ALT_UART_STHR_s +{ + uint32_t sthr : 8; /* Shadow Transmit Buffer */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_STHR. */ +typedef volatile struct ALT_UART_STHR_s ALT_UART_STHR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_STHR register from the beginning of the component. */ +#define ALT_UART_STHR_OFST 0x34 +/* The address of the ALT_UART_STHR register. */ +#define ALT_UART_STHR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STHR_OFST)) + +/* + * Register : FIFO Access Register - far + * + * This register is used in FIFO access testing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [0] | RW | 0x0 | FIFO ACCESS Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FIFO ACCESS Bit - srbr_sthr + * + * This register is used to enable a FIFO access mode for testing, so that the + * receive FIFO can be written by the master and the transmit FIFO can be read by + * the master when FIFO's are enabled. When FIFO's are not enabled it allows the + * RBR to be written by the master and the THR to be read by the master + * + * Note: That when the FIFO access mode is enabled/disabled, the control portion of + * the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:-------------------------- + * ALT_UART_FAR_SRBR_STHR_E_DISD | 0x0 | FIFO access mode disabled + * ALT_UART_FAR_SRBR_STHR_E_END | 0x1 | FIFO access mode enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FAR_SRBR_STHR + * + * FIFO access mode disabled + */ +#define ALT_UART_FAR_SRBR_STHR_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_FAR_SRBR_STHR + * + * FIFO access mode enabled + */ +#define ALT_UART_FAR_SRBR_STHR_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FAR_SRBR_STHR register field. */ +#define ALT_UART_FAR_SRBR_STHR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_FAR_SRBR_STHR register field. */ +#define ALT_UART_FAR_SRBR_STHR_MSB 0 +/* The width in bits of the ALT_UART_FAR_SRBR_STHR register field. */ +#define ALT_UART_FAR_SRBR_STHR_WIDTH 1 +/* The mask used to set the ALT_UART_FAR_SRBR_STHR register field value. */ +#define ALT_UART_FAR_SRBR_STHR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_FAR_SRBR_STHR register field value. */ +#define ALT_UART_FAR_SRBR_STHR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_FAR_SRBR_STHR register field. */ +#define ALT_UART_FAR_SRBR_STHR_RESET 0x0 +/* Extracts the ALT_UART_FAR_SRBR_STHR field value from a register. */ +#define ALT_UART_FAR_SRBR_STHR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_FAR_SRBR_STHR register field value suitable for setting the register. */ +#define ALT_UART_FAR_SRBR_STHR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_FAR. + */ +struct ALT_UART_FAR_s +{ + uint32_t srbr_sthr : 1; /* FIFO ACCESS Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_FAR. */ +typedef volatile struct ALT_UART_FAR_s ALT_UART_FAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_FAR register from the beginning of the component. */ +#define ALT_UART_FAR_OFST 0x70 +/* The address of the ALT_UART_FAR register. */ +#define ALT_UART_FAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FAR_OFST)) + +/* + * Register : Transmit FIFO Read Register - tfr + * + * Used in FIFO Access test mode. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [7:0] | R | 0x0 | Transmit FIFO Read + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Read - tfr + * + * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to + * one). When FIFO's are enabled, reading this register gives the data at the top + * of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the + * next data value that is currently at the top of the FIFO. When FIFO's are not + * enabled, reading this register gives the data in the THR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_TFR_TFR register field. */ +#define ALT_UART_TFR_TFR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_TFR_TFR register field. */ +#define ALT_UART_TFR_TFR_MSB 7 +/* The width in bits of the ALT_UART_TFR_TFR register field. */ +#define ALT_UART_TFR_TFR_WIDTH 8 +/* The mask used to set the ALT_UART_TFR_TFR register field value. */ +#define ALT_UART_TFR_TFR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_TFR_TFR register field value. */ +#define ALT_UART_TFR_TFR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_TFR_TFR register field. */ +#define ALT_UART_TFR_TFR_RESET 0x0 +/* Extracts the ALT_UART_TFR_TFR field value from a register. */ +#define ALT_UART_TFR_TFR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_TFR_TFR register field value suitable for setting the register. */ +#define ALT_UART_TFR_TFR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_TFR. + */ +struct ALT_UART_TFR_s +{ + const uint32_t tfr : 8; /* Transmit FIFO Read */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_TFR. */ +typedef volatile struct ALT_UART_TFR_s ALT_UART_TFR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_TFR register from the beginning of the component. */ +#define ALT_UART_TFR_OFST 0x74 +/* The address of the ALT_UART_TFR register. */ +#define ALT_UART_TFR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFR_OFST)) + +/* + * Register : Receive FIFO Write - RFW + * + * Used only with FIFO access test mode. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [7:0] | W | 0x0 | Receive FIFO Write Field + * [8] | W | 0x0 | Receive FIFO Parity Error + * [9] | W | 0x0 | Receive FIFO Framing Error + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Write Field - rfwd + * + * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to + * one). When FIFO's are enabled, the data that is written to the RFWD is pushed + * into the receive FIFO. Each consecutive write pushes the new data to the next + * write location in the receive FIFO. When FIFO's are not enabled, the data that + * is written to the RFWD is pushed into the RBR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFWD register field. */ +#define ALT_UART_RFW_RFWD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFWD register field. */ +#define ALT_UART_RFW_RFWD_MSB 7 +/* The width in bits of the ALT_UART_RFW_RFWD register field. */ +#define ALT_UART_RFW_RFWD_WIDTH 8 +/* The mask used to set the ALT_UART_RFW_RFWD register field value. */ +#define ALT_UART_RFW_RFWD_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_RFW_RFWD register field value. */ +#define ALT_UART_RFW_RFWD_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_RFW_RFWD register field. */ +#define ALT_UART_RFW_RFWD_RESET 0x0 +/* Extracts the ALT_UART_RFW_RFWD field value from a register. */ +#define ALT_UART_RFW_RFWD_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_RFW_RFWD register field value suitable for setting the register. */ +#define ALT_UART_RFW_RFWD_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Receive FIFO Parity Error - rfpe + * + * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to + * one). When FIFO's are enabled, this bit is used to write parity error detection + * information to the receive FIFO. When FIFO's are not enabled, this bit is used + * to write parity error detection information to the RBR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFPE register field. */ +#define ALT_UART_RFW_RFPE_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFPE register field. */ +#define ALT_UART_RFW_RFPE_MSB 8 +/* The width in bits of the ALT_UART_RFW_RFPE register field. */ +#define ALT_UART_RFW_RFPE_WIDTH 1 +/* The mask used to set the ALT_UART_RFW_RFPE register field value. */ +#define ALT_UART_RFW_RFPE_SET_MSK 0x00000100 +/* The mask used to clear the ALT_UART_RFW_RFPE register field value. */ +#define ALT_UART_RFW_RFPE_CLR_MSK 0xfffffeff +/* The reset value of the ALT_UART_RFW_RFPE register field. */ +#define ALT_UART_RFW_RFPE_RESET 0x0 +/* Extracts the ALT_UART_RFW_RFPE field value from a register. */ +#define ALT_UART_RFW_RFPE_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_UART_RFW_RFPE register field value suitable for setting the register. */ +#define ALT_UART_RFW_RFPE_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Receive FIFO Framing Error - RFFE + * + * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to + * one). When FIFO's are enabled, this bit is used to write framing error detection + * information to the receive FIFO. When FIFO's are not enabled, this bit is used + * to write framing error detection information to the RBR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFFE register field. */ +#define ALT_UART_RFW_RFFE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFFE register field. */ +#define ALT_UART_RFW_RFFE_MSB 9 +/* The width in bits of the ALT_UART_RFW_RFFE register field. */ +#define ALT_UART_RFW_RFFE_WIDTH 1 +/* The mask used to set the ALT_UART_RFW_RFFE register field value. */ +#define ALT_UART_RFW_RFFE_SET_MSK 0x00000200 +/* The mask used to clear the ALT_UART_RFW_RFFE register field value. */ +#define ALT_UART_RFW_RFFE_CLR_MSK 0xfffffdff +/* The reset value of the ALT_UART_RFW_RFFE register field. */ +#define ALT_UART_RFW_RFFE_RESET 0x0 +/* Extracts the ALT_UART_RFW_RFFE field value from a register. */ +#define ALT_UART_RFW_RFFE_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_UART_RFW_RFFE register field value suitable for setting the register. */ +#define ALT_UART_RFW_RFFE_SET(value) (((value) << 9) & 0x00000200) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_RFW. + */ +struct ALT_UART_RFW_s +{ + uint32_t rfwd : 8; /* Receive FIFO Write Field */ + uint32_t rfpe : 1; /* Receive FIFO Parity Error */ + uint32_t RFFE : 1; /* Receive FIFO Framing Error */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_RFW. */ +typedef volatile struct ALT_UART_RFW_s ALT_UART_RFW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_RFW register from the beginning of the component. */ +#define ALT_UART_RFW_OFST 0x78 +/* The address of the ALT_UART_RFW register. */ +#define ALT_UART_RFW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFW_OFST)) + +/* + * Register : UART Status Register - usr + * + * Status of FIFO Operations. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | R | 0x1 | Transmit FIFO Not Full + * [2] | R | 0x1 | Transmit FIFO Empty + * [3] | R | 0x0 | Receive FIFO Not Empty + * [4] | R | 0x0 | Receive FIFO Full + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Not Full - tfnf + * + * This Bit is used to indicate that the transmit FIFO in not full. This bit is + * cleared when the Tx FIFO is full. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------------------- + * ALT_UART_USR_TFNF_E_FULL | 0x0 | Transmit FIFO is full + * ALT_UART_USR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_USR_TFNF + * + * Transmit FIFO is full + */ +#define ALT_UART_USR_TFNF_E_FULL 0x0 +/* + * Enumerated value for register field ALT_UART_USR_TFNF + * + * Transmit FIFO is not full + */ +#define ALT_UART_USR_TFNF_E_NOTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFNF register field. */ +#define ALT_UART_USR_TFNF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFNF register field. */ +#define ALT_UART_USR_TFNF_MSB 1 +/* The width in bits of the ALT_UART_USR_TFNF register field. */ +#define ALT_UART_USR_TFNF_WIDTH 1 +/* The mask used to set the ALT_UART_USR_TFNF register field value. */ +#define ALT_UART_USR_TFNF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_USR_TFNF register field value. */ +#define ALT_UART_USR_TFNF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_USR_TFNF register field. */ +#define ALT_UART_USR_TFNF_RESET 0x1 +/* Extracts the ALT_UART_USR_TFNF field value from a register. */ +#define ALT_UART_USR_TFNF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_USR_TFNF register field value suitable for setting the register. */ +#define ALT_UART_USR_TFNF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Transmit FIFO Empty - tfe + * + * This is used to indicate that the transmit FIFO is completely empty. This bit is + * cleared when the Tx FIFO is no longer empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_UART_USR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty + * ALT_UART_USR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_USR_TFE + * + * Transmit FIFO is not empty + */ +#define ALT_UART_USR_TFE_E_NOTEMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_USR_TFE + * + * Transmit FIFO is empty + */ +#define ALT_UART_USR_TFE_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFE register field. */ +#define ALT_UART_USR_TFE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFE register field. */ +#define ALT_UART_USR_TFE_MSB 2 +/* The width in bits of the ALT_UART_USR_TFE register field. */ +#define ALT_UART_USR_TFE_WIDTH 1 +/* The mask used to set the ALT_UART_USR_TFE register field value. */ +#define ALT_UART_USR_TFE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_USR_TFE register field value. */ +#define ALT_UART_USR_TFE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_USR_TFE register field. */ +#define ALT_UART_USR_TFE_RESET 0x1 +/* Extracts the ALT_UART_USR_TFE field value from a register. */ +#define ALT_UART_USR_TFE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_USR_TFE register field value suitable for setting the register. */ +#define ALT_UART_USR_TFE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive FIFO Not Empty - rfne + * + * This Bit is used to indicate that the receive FIFO contains one or more entries. + * This bit is cleared when the Rx FIFO is empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------------- + * ALT_UART_USR_RFNE_E_EMPTY | 0x0 | Receiive FIFO is empty + * ALT_UART_USR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_USR_RFNE + * + * Receiive FIFO is empty + */ +#define ALT_UART_USR_RFNE_E_EMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_USR_RFNE + * + * Receive FIFO is not empty + */ +#define ALT_UART_USR_RFNE_E_NOTEMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFNE register field. */ +#define ALT_UART_USR_RFNE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFNE register field. */ +#define ALT_UART_USR_RFNE_MSB 3 +/* The width in bits of the ALT_UART_USR_RFNE register field. */ +#define ALT_UART_USR_RFNE_WIDTH 1 +/* The mask used to set the ALT_UART_USR_RFNE register field value. */ +#define ALT_UART_USR_RFNE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_USR_RFNE register field value. */ +#define ALT_UART_USR_RFNE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_USR_RFNE register field. */ +#define ALT_UART_USR_RFNE_RESET 0x0 +/* Extracts the ALT_UART_USR_RFNE field value from a register. */ +#define ALT_UART_USR_RFNE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_USR_RFNE register field value suitable for setting the register. */ +#define ALT_UART_USR_RFNE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive FIFO Full - rff + * + * This Bit is used to indicate that the receive FIFO is completely full. This bit + * is cleared when the Rx FIFO is no longer full. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------- + * ALT_UART_USR_RFF_E_NOTFULL | 0x0 | Receiive FIFO not full + * ALT_UART_USR_RFF_E_FULL | 0x1 | Transmit FIFO is full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_USR_RFF + * + * Receiive FIFO not full + */ +#define ALT_UART_USR_RFF_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_UART_USR_RFF + * + * Transmit FIFO is full + */ +#define ALT_UART_USR_RFF_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFF register field. */ +#define ALT_UART_USR_RFF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFF register field. */ +#define ALT_UART_USR_RFF_MSB 4 +/* The width in bits of the ALT_UART_USR_RFF register field. */ +#define ALT_UART_USR_RFF_WIDTH 1 +/* The mask used to set the ALT_UART_USR_RFF register field value. */ +#define ALT_UART_USR_RFF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_USR_RFF register field value. */ +#define ALT_UART_USR_RFF_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_USR_RFF register field. */ +#define ALT_UART_USR_RFF_RESET 0x0 +/* Extracts the ALT_UART_USR_RFF field value from a register. */ +#define ALT_UART_USR_RFF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_USR_RFF register field value suitable for setting the register. */ +#define ALT_UART_USR_RFF_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_USR. + */ +struct ALT_UART_USR_s +{ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t tfnf : 1; /* Transmit FIFO Not Full */ + const uint32_t tfe : 1; /* Transmit FIFO Empty */ + const uint32_t rfne : 1; /* Receive FIFO Not Empty */ + const uint32_t rff : 1; /* Receive FIFO Full */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_USR. */ +typedef volatile struct ALT_UART_USR_s ALT_UART_USR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_USR register from the beginning of the component. */ +#define ALT_UART_USR_OFST 0x7c +/* The address of the ALT_UART_USR register. */ +#define ALT_UART_USR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_USR_OFST)) + +/* + * Register : Transmit FIFO Level - tfl + * + * This register is used to specify the number of data entries in the Tx FIFO. + * Status Bits in USR register monitor the FIFO state. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [4:0] | R | 0x0 | Transmit FIFO Level + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Level - tfl + * + * This indicates the number of data entries in the transmit FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_TFL_TFL register field. */ +#define ALT_UART_TFL_TFL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_TFL_TFL register field. */ +#define ALT_UART_TFL_TFL_MSB 4 +/* The width in bits of the ALT_UART_TFL_TFL register field. */ +#define ALT_UART_TFL_TFL_WIDTH 5 +/* The mask used to set the ALT_UART_TFL_TFL register field value. */ +#define ALT_UART_TFL_TFL_SET_MSK 0x0000001f +/* The mask used to clear the ALT_UART_TFL_TFL register field value. */ +#define ALT_UART_TFL_TFL_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_UART_TFL_TFL register field. */ +#define ALT_UART_TFL_TFL_RESET 0x0 +/* Extracts the ALT_UART_TFL_TFL field value from a register. */ +#define ALT_UART_TFL_TFL_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_UART_TFL_TFL register field value suitable for setting the register. */ +#define ALT_UART_TFL_TFL_SET(value) (((value) << 0) & 0x0000001f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_TFL. + */ +struct ALT_UART_TFL_s +{ + const uint32_t tfl : 5; /* Transmit FIFO Level */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_TFL. */ +typedef volatile struct ALT_UART_TFL_s ALT_UART_TFL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_TFL register from the beginning of the component. */ +#define ALT_UART_TFL_OFST 0x80 +/* The address of the ALT_UART_TFL register. */ +#define ALT_UART_TFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFL_OFST)) + +/* + * Register : Receive FIFO Level Write - rfl + * + * This register is used to specify the number of data entries in the Tx FIFO. + * Status Bits in USR register monitor the FIFO state. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [4:0] | R | 0x0 | Receive FIFO Level Status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Level Status - rfl + * + * This indicates the number of data entries in the receive FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RFL_RFL register field. */ +#define ALT_UART_RFL_RFL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_RFL_RFL register field. */ +#define ALT_UART_RFL_RFL_MSB 4 +/* The width in bits of the ALT_UART_RFL_RFL register field. */ +#define ALT_UART_RFL_RFL_WIDTH 5 +/* The mask used to set the ALT_UART_RFL_RFL register field value. */ +#define ALT_UART_RFL_RFL_SET_MSK 0x0000001f +/* The mask used to clear the ALT_UART_RFL_RFL register field value. */ +#define ALT_UART_RFL_RFL_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_UART_RFL_RFL register field. */ +#define ALT_UART_RFL_RFL_RESET 0x0 +/* Extracts the ALT_UART_RFL_RFL field value from a register. */ +#define ALT_UART_RFL_RFL_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_UART_RFL_RFL register field value suitable for setting the register. */ +#define ALT_UART_RFL_RFL_SET(value) (((value) << 0) & 0x0000001f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_RFL. + */ +struct ALT_UART_RFL_s +{ + const uint32_t rfl : 5; /* Receive FIFO Level Status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_RFL. */ +typedef volatile struct ALT_UART_RFL_s ALT_UART_RFL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_RFL register from the beginning of the component. */ +#define ALT_UART_RFL_OFST 0x84 +/* The address of the ALT_UART_RFL register. */ +#define ALT_UART_RFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFL_OFST)) + +/* + * Register : Software Reset Register - srr + * + * Provides Software Resets for Tx/Rx FIFO's and the uart. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [0] | W | 0x0 | UART Reset + * [1] | W | 0x0 | Rx FIFO Reset + * [2] | W | 0x0 | Tx FIFO Reset + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : UART Reset - ur + * + * This asynchronously resets the UART and synchronously removes the reset + * assertion. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:-------------- + * ALT_UART_SRR_UR_E_NORST | 0x0 | No reset Uart + * ALT_UART_SRR_UR_E_RST | 0x1 | Reset Uart + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRR_UR + * + * No reset Uart + */ +#define ALT_UART_SRR_UR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_SRR_UR + * + * Reset Uart + */ +#define ALT_UART_SRR_UR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_UR register field. */ +#define ALT_UART_SRR_UR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_UR register field. */ +#define ALT_UART_SRR_UR_MSB 0 +/* The width in bits of the ALT_UART_SRR_UR register field. */ +#define ALT_UART_SRR_UR_WIDTH 1 +/* The mask used to set the ALT_UART_SRR_UR register field value. */ +#define ALT_UART_SRR_UR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SRR_UR register field value. */ +#define ALT_UART_SRR_UR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SRR_UR register field. */ +#define ALT_UART_SRR_UR_RESET 0x0 +/* Extracts the ALT_UART_SRR_UR field value from a register. */ +#define ALT_UART_SRR_UR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SRR_UR register field value suitable for setting the register. */ +#define ALT_UART_SRR_UR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Rx FIFO Reset - rfr + * + * This is a shadow register for the Rx FIFO Reset bit (FCR[1]). This can be used + * to remove the burden on software having to store previously written FCR values + * (which are pretty static) just to reset the receive FIFO. This resets the + * control portion of the receive FIFO and treats the FIFO as empty. This will also + * de-assert the DMA Rx request and single signals. Note that this bit is 'self- + * clearing' and it is not necessary to clear this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------- + * ALT_UART_SRR_RFR_E_NORST | 0x0 | No reset Rx FIFO + * ALT_UART_SRR_RFR_E_RST | 0x1 | Reset Rx FIFO + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRR_RFR + * + * No reset Rx FIFO + */ +#define ALT_UART_SRR_RFR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_SRR_RFR + * + * Reset Rx FIFO + */ +#define ALT_UART_SRR_RFR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_RFR register field. */ +#define ALT_UART_SRR_RFR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_RFR register field. */ +#define ALT_UART_SRR_RFR_MSB 1 +/* The width in bits of the ALT_UART_SRR_RFR register field. */ +#define ALT_UART_SRR_RFR_WIDTH 1 +/* The mask used to set the ALT_UART_SRR_RFR register field value. */ +#define ALT_UART_SRR_RFR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_SRR_RFR register field value. */ +#define ALT_UART_SRR_RFR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_SRR_RFR register field. */ +#define ALT_UART_SRR_RFR_RESET 0x0 +/* Extracts the ALT_UART_SRR_RFR field value from a register. */ +#define ALT_UART_SRR_RFR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_SRR_RFR register field value suitable for setting the register. */ +#define ALT_UART_SRR_RFR_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Tx FIFO Reset - xfr + * + * This is a shadow register forthe Tx FIFO Reset bit (FCR[2]). This can be used + * to remove the burden on software having to store previously written FCR values + * (which are pretty static) just to reset the transmit FIFO.This resets the + * control portion of the transmit FIFO and treats the FIFO as empty. This will + * also de-assert the DMA Tx request and single signals. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------- + * ALT_UART_SRR_XFR_E_NORST | 0x0 | No reset Tx FIFO + * ALT_UART_SRR_XFR_E_RST | 0x1 | Reset Tx FIFO + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRR_XFR + * + * No reset Tx FIFO + */ +#define ALT_UART_SRR_XFR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_SRR_XFR + * + * Reset Tx FIFO + */ +#define ALT_UART_SRR_XFR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_XFR register field. */ +#define ALT_UART_SRR_XFR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_XFR register field. */ +#define ALT_UART_SRR_XFR_MSB 2 +/* The width in bits of the ALT_UART_SRR_XFR register field. */ +#define ALT_UART_SRR_XFR_WIDTH 1 +/* The mask used to set the ALT_UART_SRR_XFR register field value. */ +#define ALT_UART_SRR_XFR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_SRR_XFR register field value. */ +#define ALT_UART_SRR_XFR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_SRR_XFR register field. */ +#define ALT_UART_SRR_XFR_RESET 0x0 +/* Extracts the ALT_UART_SRR_XFR field value from a register. */ +#define ALT_UART_SRR_XFR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_SRR_XFR register field value suitable for setting the register. */ +#define ALT_UART_SRR_XFR_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SRR. + */ +struct ALT_UART_SRR_s +{ + uint32_t ur : 1; /* UART Reset */ + uint32_t rfr : 1; /* Rx FIFO Reset */ + uint32_t xfr : 1; /* Tx FIFO Reset */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SRR. */ +typedef volatile struct ALT_UART_SRR_s ALT_UART_SRR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SRR register from the beginning of the component. */ +#define ALT_UART_SRR_OFST 0x88 +/* The address of the ALT_UART_SRR register. */ +#define ALT_UART_SRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRR_OFST)) + +/* + * Register : Shadow Request to Send - srts + * + * This is a shadow register for the RTS status (MCR[1]), this can be used to + * remove the burden of having to performing a read modify write on the MCR. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | RW | 0x0 | Shadow Request to Send + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Request to Send - srts + * + * This is used to directly control the Request to Send (uart_rts_n) output. The + * Request to Send (uart_rts_n) output is used to inform the modem or data set that + * the UART is read to exchange data. The uart_rts_n signal is set low by + * programming MCR[1] (RTS) to a high. In Auto Flow Control, (MCR[5] set to one) + * and FIFO's are enabled (FCR[0] set to one), the uart_rts_n output is controlled + * in the same way, but is also gated with the receiver FIFO threshold trigger + * (uart_rts_n is inactive high when above the threshold). + * + * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held + * inactive high while the value of this location is internally looped back to an + * input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------ + * ALT_UART_SRTS_SRTS_E_LOGIC0 | 0x1 | uart_rts_n logic0 + * ALT_UART_SRTS_SRTS_E_LOGIC1 | 0x0 | uart_rts_n logic1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRTS_SRTS + * + * uart_rts_n logic0 + */ +#define ALT_UART_SRTS_SRTS_E_LOGIC0 0x1 +/* + * Enumerated value for register field ALT_UART_SRTS_SRTS + * + * uart_rts_n logic1 + */ +#define ALT_UART_SRTS_SRTS_E_LOGIC1 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRTS_SRTS register field. */ +#define ALT_UART_SRTS_SRTS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRTS_SRTS register field. */ +#define ALT_UART_SRTS_SRTS_MSB 0 +/* The width in bits of the ALT_UART_SRTS_SRTS register field. */ +#define ALT_UART_SRTS_SRTS_WIDTH 1 +/* The mask used to set the ALT_UART_SRTS_SRTS register field value. */ +#define ALT_UART_SRTS_SRTS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SRTS_SRTS register field value. */ +#define ALT_UART_SRTS_SRTS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SRTS_SRTS register field. */ +#define ALT_UART_SRTS_SRTS_RESET 0x0 +/* Extracts the ALT_UART_SRTS_SRTS field value from a register. */ +#define ALT_UART_SRTS_SRTS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SRTS_SRTS register field value suitable for setting the register. */ +#define ALT_UART_SRTS_SRTS_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SRTS. + */ +struct ALT_UART_SRTS_s +{ + uint32_t srts : 1; /* Shadow Request to Send */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SRTS. */ +typedef volatile struct ALT_UART_SRTS_s ALT_UART_SRTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SRTS register from the beginning of the component. */ +#define ALT_UART_SRTS_OFST 0x8c +/* The address of the ALT_UART_SRTS register. */ +#define ALT_UART_SRTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRTS_OFST)) + +/* + * Register : Shadow Break Control Register - sbcr + * + * This is a shadow register for the Break bit [6] of the register LCR. This can be + * used to remove the burden of having to performing a read modify write on the + * LCR. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x0 | Shadow Break Control + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Break Control - sbcr + * + * This is used to cause a break condition to be transmitted to the receiving + * device. If set to one the serial output is forced to the spacing (logic 0) + * state. When not in Loopback Mode, as determined by MCR[4], the uart_txd line is + * forced low until the Break bit is cleared. When in Loopback Mode, the break + * condition is internally looped back to the receiver. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:---------------------------- + * ALT_UART_SBCR_SBCR_E_DISD | 0x0 | no break + * ALT_UART_SBCR_SBCR_E_END | 0x1 | break serial output spacing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SBCR_SBCR + * + * no break + */ +#define ALT_UART_SBCR_SBCR_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_SBCR_SBCR + * + * break serial output spacing + */ +#define ALT_UART_SBCR_SBCR_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SBCR_SBCR register field. */ +#define ALT_UART_SBCR_SBCR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SBCR_SBCR register field. */ +#define ALT_UART_SBCR_SBCR_MSB 0 +/* The width in bits of the ALT_UART_SBCR_SBCR register field. */ +#define ALT_UART_SBCR_SBCR_WIDTH 1 +/* The mask used to set the ALT_UART_SBCR_SBCR register field value. */ +#define ALT_UART_SBCR_SBCR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SBCR_SBCR register field value. */ +#define ALT_UART_SBCR_SBCR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SBCR_SBCR register field. */ +#define ALT_UART_SBCR_SBCR_RESET 0x0 +/* Extracts the ALT_UART_SBCR_SBCR field value from a register. */ +#define ALT_UART_SBCR_SBCR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SBCR_SBCR register field value suitable for setting the register. */ +#define ALT_UART_SBCR_SBCR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SBCR. + */ +struct ALT_UART_SBCR_s +{ + uint32_t sbcr : 1; /* Shadow Break Control */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SBCR. */ +typedef volatile struct ALT_UART_SBCR_s ALT_UART_SBCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SBCR register from the beginning of the component. */ +#define ALT_UART_SBCR_OFST 0x90 +/* The address of the ALT_UART_SBCR register. */ +#define ALT_UART_SBCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SBCR_OFST)) + +/* + * Register : Shadow DMA Mode - sdmam + * + * This is a shadow register for the DMA mode bit (FCR[3]). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [0] | RW | 0x0 | Shadow DMA Mode + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow DMA Mode - sdmam + * + * This can be used to remove the burden of having to store the previously written + * value to the FCR in memory and having to mask this value so that only the DMA + * Mode bit gets updated. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:--------------------------- + * ALT_UART_SDMAM_SDMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode + * ALT_UART_SDMAM_SDMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SDMAM_SDMAM + * + * Single DMA Transfer Mode + */ +#define ALT_UART_SDMAM_SDMAM_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_UART_SDMAM_SDMAM + * + * Multiple DMA Transfer Mode + */ +#define ALT_UART_SDMAM_SDMAM_E_MULT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SDMAM_SDMAM register field. */ +#define ALT_UART_SDMAM_SDMAM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SDMAM_SDMAM register field. */ +#define ALT_UART_SDMAM_SDMAM_MSB 0 +/* The width in bits of the ALT_UART_SDMAM_SDMAM register field. */ +#define ALT_UART_SDMAM_SDMAM_WIDTH 1 +/* The mask used to set the ALT_UART_SDMAM_SDMAM register field value. */ +#define ALT_UART_SDMAM_SDMAM_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SDMAM_SDMAM register field value. */ +#define ALT_UART_SDMAM_SDMAM_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SDMAM_SDMAM register field. */ +#define ALT_UART_SDMAM_SDMAM_RESET 0x0 +/* Extracts the ALT_UART_SDMAM_SDMAM field value from a register. */ +#define ALT_UART_SDMAM_SDMAM_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SDMAM_SDMAM register field value suitable for setting the register. */ +#define ALT_UART_SDMAM_SDMAM_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SDMAM. + */ +struct ALT_UART_SDMAM_s +{ + uint32_t sdmam : 1; /* Shadow DMA Mode */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SDMAM. */ +typedef volatile struct ALT_UART_SDMAM_s ALT_UART_SDMAM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SDMAM register from the beginning of the component. */ +#define ALT_UART_SDMAM_OFST 0x94 +/* The address of the ALT_UART_SDMAM register. */ +#define ALT_UART_SDMAM_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SDMAM_OFST)) + +/* + * Register : Shadow FIFO Enable - sfe + * + * This is a shadow register for the FIFO enable bit [0] of register FCR. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [0] | RW | 0x0 | Shadow FIFO Enable + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow FIFO Enable - sfe + * + * This can be used to remove the burden of having to store the previously written + * value to the FCR in memory and having to mask this value so that only the FIFO + * enable bit gets updated. This enables/disables the transmit (Tx) and receive (Rx + * ) FIFO's. If this bit is set to zero (disabled) after being enabled then both + * the Tx and Rx controller portion of FIFO's will be reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:-------------- + * ALT_UART_SFE_SFE_E_DISD | 0x0 | Disable Rx/Tx + * ALT_UART_SFE_SFE_E_END | 0x1 | Enable Rx/Tx + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SFE_SFE + * + * Disable Rx/Tx + */ +#define ALT_UART_SFE_SFE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_SFE_SFE + * + * Enable Rx/Tx + */ +#define ALT_UART_SFE_SFE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SFE_SFE register field. */ +#define ALT_UART_SFE_SFE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SFE_SFE register field. */ +#define ALT_UART_SFE_SFE_MSB 0 +/* The width in bits of the ALT_UART_SFE_SFE register field. */ +#define ALT_UART_SFE_SFE_WIDTH 1 +/* The mask used to set the ALT_UART_SFE_SFE register field value. */ +#define ALT_UART_SFE_SFE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SFE_SFE register field value. */ +#define ALT_UART_SFE_SFE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SFE_SFE register field. */ +#define ALT_UART_SFE_SFE_RESET 0x0 +/* Extracts the ALT_UART_SFE_SFE field value from a register. */ +#define ALT_UART_SFE_SFE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SFE_SFE register field value suitable for setting the register. */ +#define ALT_UART_SFE_SFE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SFE. + */ +struct ALT_UART_SFE_s +{ + uint32_t sfe : 1; /* Shadow FIFO Enable */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SFE. */ +typedef volatile struct ALT_UART_SFE_s ALT_UART_SFE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SFE register from the beginning of the component. */ +#define ALT_UART_SFE_OFST 0x98 +/* The address of the ALT_UART_SFE register. */ +#define ALT_UART_SFE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SFE_OFST)) + +/* + * Register : Shadow Rx Trigger - srt + * + * This is a shadow register for the Rx trigger bits (FCR[7:6]). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [1:0] | RW | 0x0 | Shadow Rx Trigger Bits + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Rx Trigger Bits - srt + * + * This can be used to remove the burden of having to store the previously written + * value to the FCR in memory and having to mask this value so that only the Rx + * trigger bit gets updated. This is used to select the trigger level in the + * receiver FIFO at which the Received Data Available Interrupt will be generated. + * It also determines when the uart_dma_rx_req_n signal will be asserted when DMA + * Mode (FCR[3]) is set to one. The enum below shows trigger levels that are + * supported. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------- + * ALT_UART_SRT_SRT_E_ONECHAR | 0x0 | one character in fifo + * ALT_UART_SRT_SRT_E_QUARTERFULL | 0x1 | FIFO 1/4 full + * ALT_UART_SRT_SRT_E_HALFFULL | 0x2 | FIFO 1/2 full + * ALT_UART_SRT_SRT_E_FULLLESS2 | 0x3 | FIFO 2 less than full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRT_SRT + * + * one character in fifo + */ +#define ALT_UART_SRT_SRT_E_ONECHAR 0x0 +/* + * Enumerated value for register field ALT_UART_SRT_SRT + * + * FIFO 1/4 full + */ +#define ALT_UART_SRT_SRT_E_QUARTERFULL 0x1 +/* + * Enumerated value for register field ALT_UART_SRT_SRT + * + * FIFO 1/2 full + */ +#define ALT_UART_SRT_SRT_E_HALFFULL 0x2 +/* + * Enumerated value for register field ALT_UART_SRT_SRT + * + * FIFO 2 less than full + */ +#define ALT_UART_SRT_SRT_E_FULLLESS2 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRT_SRT register field. */ +#define ALT_UART_SRT_SRT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRT_SRT register field. */ +#define ALT_UART_SRT_SRT_MSB 1 +/* The width in bits of the ALT_UART_SRT_SRT register field. */ +#define ALT_UART_SRT_SRT_WIDTH 2 +/* The mask used to set the ALT_UART_SRT_SRT register field value. */ +#define ALT_UART_SRT_SRT_SET_MSK 0x00000003 +/* The mask used to clear the ALT_UART_SRT_SRT register field value. */ +#define ALT_UART_SRT_SRT_CLR_MSK 0xfffffffc +/* The reset value of the ALT_UART_SRT_SRT register field. */ +#define ALT_UART_SRT_SRT_RESET 0x0 +/* Extracts the ALT_UART_SRT_SRT field value from a register. */ +#define ALT_UART_SRT_SRT_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_UART_SRT_SRT register field value suitable for setting the register. */ +#define ALT_UART_SRT_SRT_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SRT. + */ +struct ALT_UART_SRT_s +{ + uint32_t srt : 2; /* Shadow Rx Trigger Bits */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SRT. */ +typedef volatile struct ALT_UART_SRT_s ALT_UART_SRT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SRT register from the beginning of the component. */ +#define ALT_UART_SRT_OFST 0x9c +/* The address of the ALT_UART_SRT register. */ +#define ALT_UART_SRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRT_OFST)) + +/* + * Register : Shadow Tx Empty Trigger - stet + * + * This is a shadow register for the Tx empty trigger bits (FCR[5:4]). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | Shadow Tx Empty Trigger Bits + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Tx Empty Trigger Bits - stet + * + * This can be used to remove the burden of having to store the previously written + * value to the FCR in memory and having to mask this value so that only the Tx + * empty trigger bit gets updated. This is used to select the empty threshold level + * at which the THRE Interrupts will be generated when the mode is active. These + * threshold levels are also described in. The enum trigger levels are supported. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------- + * ALT_UART_STET_STET_E_FIFOEMPTY | 0x0 | FIFO empty + * ALT_UART_STET_STET_E_TWOCHARS | 0x1 | Two characters in FIFO + * ALT_UART_STET_STET_E_QUARTERFULL | 0x2 | FIFO quarter full + * ALT_UART_STET_STET_E_HALFFULL | 0x3 | FIFO half full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_STET_STET + * + * FIFO empty + */ +#define ALT_UART_STET_STET_E_FIFOEMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_STET_STET + * + * Two characters in FIFO + */ +#define ALT_UART_STET_STET_E_TWOCHARS 0x1 +/* + * Enumerated value for register field ALT_UART_STET_STET + * + * FIFO quarter full + */ +#define ALT_UART_STET_STET_E_QUARTERFULL 0x2 +/* + * Enumerated value for register field ALT_UART_STET_STET + * + * FIFO half full + */ +#define ALT_UART_STET_STET_E_HALFFULL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_STET_STET register field. */ +#define ALT_UART_STET_STET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_STET_STET register field. */ +#define ALT_UART_STET_STET_MSB 1 +/* The width in bits of the ALT_UART_STET_STET register field. */ +#define ALT_UART_STET_STET_WIDTH 2 +/* The mask used to set the ALT_UART_STET_STET register field value. */ +#define ALT_UART_STET_STET_SET_MSK 0x00000003 +/* The mask used to clear the ALT_UART_STET_STET register field value. */ +#define ALT_UART_STET_STET_CLR_MSK 0xfffffffc +/* The reset value of the ALT_UART_STET_STET register field. */ +#define ALT_UART_STET_STET_RESET 0x0 +/* Extracts the ALT_UART_STET_STET field value from a register. */ +#define ALT_UART_STET_STET_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_UART_STET_STET register field value suitable for setting the register. */ +#define ALT_UART_STET_STET_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_STET. + */ +struct ALT_UART_STET_s +{ + uint32_t stet : 2; /* Shadow Tx Empty Trigger Bits */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_STET. */ +typedef volatile struct ALT_UART_STET_s ALT_UART_STET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_STET register from the beginning of the component. */ +#define ALT_UART_STET_OFST 0xa0 +/* The address of the ALT_UART_STET register. */ +#define ALT_UART_STET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STET_OFST)) + +/* + * Register : Halt Tx - htx + * + * Used to halt transmission for testing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Halt Tx Bits + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Halt Tx Bits - htx + * + * This register is use to halt transmissions for testing, so that the transmit + * FIFO can be filled by the master when FIFO's are enabled. + * + * Note, if FIFO's are not enabled, the setting of the halt Tx register will have + * no effect on operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:----------------- + * ALT_UART_HTX_HTX_E_DISD | 0x0 | Halt Tx disabled + * ALT_UART_HTX_HTX_E_END | 0x1 | Halt Tx enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_HTX_HTX + * + * Halt Tx disabled + */ +#define ALT_UART_HTX_HTX_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_HTX_HTX + * + * Halt Tx enabled + */ +#define ALT_UART_HTX_HTX_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_HTX_HTX register field. */ +#define ALT_UART_HTX_HTX_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_HTX_HTX register field. */ +#define ALT_UART_HTX_HTX_MSB 0 +/* The width in bits of the ALT_UART_HTX_HTX register field. */ +#define ALT_UART_HTX_HTX_WIDTH 1 +/* The mask used to set the ALT_UART_HTX_HTX register field value. */ +#define ALT_UART_HTX_HTX_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_HTX_HTX register field value. */ +#define ALT_UART_HTX_HTX_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_HTX_HTX register field. */ +#define ALT_UART_HTX_HTX_RESET 0x0 +/* Extracts the ALT_UART_HTX_HTX field value from a register. */ +#define ALT_UART_HTX_HTX_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_HTX_HTX register field value suitable for setting the register. */ +#define ALT_UART_HTX_HTX_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_HTX. + */ +struct ALT_UART_HTX_s +{ + uint32_t htx : 1; /* Halt Tx Bits */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_HTX. */ +typedef volatile struct ALT_UART_HTX_s ALT_UART_HTX_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_HTX register from the beginning of the component. */ +#define ALT_UART_HTX_OFST 0xa4 +/* The address of the ALT_UART_HTX register. */ +#define ALT_UART_HTX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_HTX_OFST)) + +/* + * Register : DMA Software Acknowledge - dmasa + * + * DMA Operation Control + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | W | 0x0 | DMA Software Acknowledge Bits + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DMA Software Acknowledge Bits - dmasa + * + * This register is used to perform DMA software acknowledge if a transfer needs to + * be terminated due to an error condition. For example, if the DMA disables the + * channel, then the uart should clear its request. This will cause the Tx request, + * Tx single, Rx request and Rx single signals to de-assert. Note that this bit is + * 'self-clearing' and it is not necessary to clear this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_DMASA_DMASA register field. */ +#define ALT_UART_DMASA_DMASA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_DMASA_DMASA register field. */ +#define ALT_UART_DMASA_DMASA_MSB 0 +/* The width in bits of the ALT_UART_DMASA_DMASA register field. */ +#define ALT_UART_DMASA_DMASA_WIDTH 1 +/* The mask used to set the ALT_UART_DMASA_DMASA register field value. */ +#define ALT_UART_DMASA_DMASA_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_DMASA_DMASA register field value. */ +#define ALT_UART_DMASA_DMASA_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_DMASA_DMASA register field. */ +#define ALT_UART_DMASA_DMASA_RESET 0x0 +/* Extracts the ALT_UART_DMASA_DMASA field value from a register. */ +#define ALT_UART_DMASA_DMASA_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_DMASA_DMASA register field value suitable for setting the register. */ +#define ALT_UART_DMASA_DMASA_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_DMASA. + */ +struct ALT_UART_DMASA_s +{ + uint32_t dmasa : 1; /* DMA Software Acknowledge Bits */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_DMASA. */ +typedef volatile struct ALT_UART_DMASA_s ALT_UART_DMASA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_DMASA register from the beginning of the component. */ +#define ALT_UART_DMASA_OFST 0xa8 +/* The address of the ALT_UART_DMASA register. */ +#define ALT_UART_DMASA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_DMASA_OFST)) + +/* + * Register : Component Parameter Register - cpr + * + * Describes various fixed hardware setups states. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [1:0] | R | 0x2 | APB DATA WIDTH + * [3:2] | ??? | 0x0 | *UNDEFINED* + * [4] | R | 0x1 | Auto Flow Control + * [5] | R | 0x1 | THRE MODE + * [6] | R | 0x0 | SIR MODE Unsupported + * [7] | R | 0x0 | SIR LP MODE Unsupported + * [8] | R | 0x1 | ADDITIONAL FEATURES Supported + * [9] | R | 0x1 | FIFO ACCESS Supported + * [10] | R | 0x1 | FIFO STAT Supported + * [11] | R | 0x1 | SHADOW Supported + * [12] | R | 0x1 | Configuartion ID Register Present + * [13] | R | 0x1 | DMA EXTRA Supported + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [23:16] | R | 0x37 | FIFO Depth + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : APB DATA WIDTH - apbdatawidth + * + * Fixed to support an ABP data bus width of 32-bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------- + * ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_APBDATAWIDTH + * + * APB Data Width = 32-bits + */ +#define ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */ +#define ALT_UART_CPR_APBDATAWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */ +#define ALT_UART_CPR_APBDATAWIDTH_MSB 1 +/* The width in bits of the ALT_UART_CPR_APBDATAWIDTH register field. */ +#define ALT_UART_CPR_APBDATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_UART_CPR_APBDATAWIDTH register field value. */ +#define ALT_UART_CPR_APBDATAWIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_UART_CPR_APBDATAWIDTH register field value. */ +#define ALT_UART_CPR_APBDATAWIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_UART_CPR_APBDATAWIDTH register field. */ +#define ALT_UART_CPR_APBDATAWIDTH_RESET 0x2 +/* Extracts the ALT_UART_CPR_APBDATAWIDTH field value from a register. */ +#define ALT_UART_CPR_APBDATAWIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_UART_CPR_APBDATAWIDTH register field value suitable for setting the register. */ +#define ALT_UART_CPR_APBDATAWIDTH_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Auto Flow Control - afce_mode + * + * Allows auto flow control. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------ + * ALT_UART_CPR_AFCE_MOD_E_END | 0x1 | Auto Flow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_AFCE_MOD + * + * Auto Flow + */ +#define ALT_UART_CPR_AFCE_MOD_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_AFCE_MOD register field. */ +#define ALT_UART_CPR_AFCE_MOD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_AFCE_MOD register field. */ +#define ALT_UART_CPR_AFCE_MOD_MSB 4 +/* The width in bits of the ALT_UART_CPR_AFCE_MOD register field. */ +#define ALT_UART_CPR_AFCE_MOD_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_AFCE_MOD register field value. */ +#define ALT_UART_CPR_AFCE_MOD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_CPR_AFCE_MOD register field value. */ +#define ALT_UART_CPR_AFCE_MOD_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_CPR_AFCE_MOD register field. */ +#define ALT_UART_CPR_AFCE_MOD_RESET 0x1 +/* Extracts the ALT_UART_CPR_AFCE_MOD field value from a register. */ +#define ALT_UART_CPR_AFCE_MOD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_CPR_AFCE_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_AFCE_MOD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : THRE MODE - thre_mode + * + * Programmable Transmitter Hold Register Empty interrupt + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------------------------------ + * ALT_UART_CPR_THRE_MOD_E_END | 0x1 | Programmable Tx Hold Reg. Empty interrupt + * : | | present + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_THRE_MOD + * + * Programmable Tx Hold Reg. Empty interrupt present + */ +#define ALT_UART_CPR_THRE_MOD_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_THRE_MOD register field. */ +#define ALT_UART_CPR_THRE_MOD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_THRE_MOD register field. */ +#define ALT_UART_CPR_THRE_MOD_MSB 5 +/* The width in bits of the ALT_UART_CPR_THRE_MOD register field. */ +#define ALT_UART_CPR_THRE_MOD_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_THRE_MOD register field value. */ +#define ALT_UART_CPR_THRE_MOD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_CPR_THRE_MOD register field value. */ +#define ALT_UART_CPR_THRE_MOD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_CPR_THRE_MOD register field. */ +#define ALT_UART_CPR_THRE_MOD_RESET 0x1 +/* Extracts the ALT_UART_CPR_THRE_MOD field value from a register. */ +#define ALT_UART_CPR_THRE_MOD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_CPR_THRE_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_THRE_MOD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : SIR MODE Unsupported - sir_mode + * + * Sir mode not used in this application. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------------- + * ALT_UART_CPR_SIR_MOD_E_DISD | 0x0 | Sir Mode Not Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_SIR_MOD + * + * Sir Mode Not Supported + */ +#define ALT_UART_CPR_SIR_MOD_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_MOD register field. */ +#define ALT_UART_CPR_SIR_MOD_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_MOD register field. */ +#define ALT_UART_CPR_SIR_MOD_MSB 6 +/* The width in bits of the ALT_UART_CPR_SIR_MOD register field. */ +#define ALT_UART_CPR_SIR_MOD_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_SIR_MOD register field value. */ +#define ALT_UART_CPR_SIR_MOD_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_CPR_SIR_MOD register field value. */ +#define ALT_UART_CPR_SIR_MOD_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_CPR_SIR_MOD register field. */ +#define ALT_UART_CPR_SIR_MOD_RESET 0x0 +/* Extracts the ALT_UART_CPR_SIR_MOD field value from a register. */ +#define ALT_UART_CPR_SIR_MOD_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_CPR_SIR_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_SIR_MOD_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : SIR LP MODE Unsupported - sir_lp_mode + * + * LP Sir Mode not used in this application. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:-------------------------- + * ALT_UART_CPR_SIR_LP_MOD_E_DISD | 0x0 | LP Sir Mode Not Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_SIR_LP_MOD + * + * LP Sir Mode Not Supported + */ +#define ALT_UART_CPR_SIR_LP_MOD_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */ +#define ALT_UART_CPR_SIR_LP_MOD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */ +#define ALT_UART_CPR_SIR_LP_MOD_MSB 7 +/* The width in bits of the ALT_UART_CPR_SIR_LP_MOD register field. */ +#define ALT_UART_CPR_SIR_LP_MOD_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_SIR_LP_MOD register field value. */ +#define ALT_UART_CPR_SIR_LP_MOD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_CPR_SIR_LP_MOD register field value. */ +#define ALT_UART_CPR_SIR_LP_MOD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_CPR_SIR_LP_MOD register field. */ +#define ALT_UART_CPR_SIR_LP_MOD_RESET 0x0 +/* Extracts the ALT_UART_CPR_SIR_LP_MOD field value from a register. */ +#define ALT_UART_CPR_SIR_LP_MOD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_CPR_SIR_LP_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_SIR_LP_MOD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : ADDITIONAL FEATURES Supported - additional_feat + * + * Configures the uart to include fifo status register, shadow registers and + * encoded parameter register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------ + * ALT_UART_CPR_ADDITIONAL_FEAT_E_END | 0x1 | Additional Features Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT + * + * Additional Features Supported + */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_MSB 8 +/* The width in bits of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK 0x00000100 +/* The mask used to clear the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK 0xfffffeff +/* The reset value of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_RESET 0x1 +/* Extracts the ALT_UART_CPR_ADDITIONAL_FEAT field value from a register. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_UART_CPR_ADDITIONAL_FEAT register field value suitable for setting the register. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : FIFO ACCESS Supported - fifo_access + * + * Configures the peripheral to have a programmable FIFO access mode. This is used + * for test purposes, to allow the receiver FIFO to be written and the transmit + * FIFO to be read when FIFOs are implemented and enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------- + * ALT_UART_CPR_FIFO_ACCESS_E_END | 0x1 | FIFO Access Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS + * + * FIFO Access Supported + */ +#define ALT_UART_CPR_FIFO_ACCESS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */ +#define ALT_UART_CPR_FIFO_ACCESS_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */ +#define ALT_UART_CPR_FIFO_ACCESS_MSB 9 +/* The width in bits of the ALT_UART_CPR_FIFO_ACCESS register field. */ +#define ALT_UART_CPR_FIFO_ACCESS_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_FIFO_ACCESS register field value. */ +#define ALT_UART_CPR_FIFO_ACCESS_SET_MSK 0x00000200 +/* The mask used to clear the ALT_UART_CPR_FIFO_ACCESS register field value. */ +#define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK 0xfffffdff +/* The reset value of the ALT_UART_CPR_FIFO_ACCESS register field. */ +#define ALT_UART_CPR_FIFO_ACCESS_RESET 0x1 +/* Extracts the ALT_UART_CPR_FIFO_ACCESS field value from a register. */ +#define ALT_UART_CPR_FIFO_ACCESS_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_UART_CPR_FIFO_ACCESS register field value suitable for setting the register. */ +#define ALT_UART_CPR_FIFO_ACCESS_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : FIFO STAT Supported - fifo_stat + * + * Configures the peripheral to have three additional FIFO status registers. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------- + * ALT_UART_CPR_FIFO_STAT_E_END | 0x1 | FIFO Stat Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_FIFO_STAT + * + * FIFO Stat Supported + */ +#define ALT_UART_CPR_FIFO_STAT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_STAT register field. */ +#define ALT_UART_CPR_FIFO_STAT_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_STAT register field. */ +#define ALT_UART_CPR_FIFO_STAT_MSB 10 +/* The width in bits of the ALT_UART_CPR_FIFO_STAT register field. */ +#define ALT_UART_CPR_FIFO_STAT_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_FIFO_STAT register field value. */ +#define ALT_UART_CPR_FIFO_STAT_SET_MSK 0x00000400 +/* The mask used to clear the ALT_UART_CPR_FIFO_STAT register field value. */ +#define ALT_UART_CPR_FIFO_STAT_CLR_MSK 0xfffffbff +/* The reset value of the ALT_UART_CPR_FIFO_STAT register field. */ +#define ALT_UART_CPR_FIFO_STAT_RESET 0x1 +/* Extracts the ALT_UART_CPR_FIFO_STAT field value from a register. */ +#define ALT_UART_CPR_FIFO_STAT_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_UART_CPR_FIFO_STAT register field value suitable for setting the register. */ +#define ALT_UART_CPR_FIFO_STAT_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : SHADOW Supported - shadow + * + * Configures the peripheral to have seven additional registers that shadow some of + * the existing register bits that are regularly modified by software. These can be + * used to reduce the software overhead that is introduced by having to perform + * read-modify writes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------- + * ALT_UART_CPR_SHADOW_E_END | 0x1 | Shadow Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_SHADOW + * + * Shadow Supported + */ +#define ALT_UART_CPR_SHADOW_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SHADOW register field. */ +#define ALT_UART_CPR_SHADOW_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SHADOW register field. */ +#define ALT_UART_CPR_SHADOW_MSB 11 +/* The width in bits of the ALT_UART_CPR_SHADOW register field. */ +#define ALT_UART_CPR_SHADOW_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_SHADOW register field value. */ +#define ALT_UART_CPR_SHADOW_SET_MSK 0x00000800 +/* The mask used to clear the ALT_UART_CPR_SHADOW register field value. */ +#define ALT_UART_CPR_SHADOW_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_UART_CPR_SHADOW register field. */ +#define ALT_UART_CPR_SHADOW_RESET 0x1 +/* Extracts the ALT_UART_CPR_SHADOW field value from a register. */ +#define ALT_UART_CPR_SHADOW_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_UART_CPR_SHADOW register field value suitable for setting the register. */ +#define ALT_UART_CPR_SHADOW_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Configuartion ID Register Present - uart_add_encoded_param + * + * Configures the peripheral to have a configuration identification register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END | 0x1 | ID register present + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_UART_ADD_ENC_PARAM + * + * ID register present + */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB 12 +/* The width in bits of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK 0x00001000 +/* The mask used to clear the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK 0xffffefff +/* The reset value of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET 0x1 +/* Extracts the ALT_UART_CPR_UART_ADD_ENC_PARAM field value from a register. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_UART_CPR_UART_ADD_ENC_PARAM register field value suitable for setting the register. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : DMA EXTRA Supported - dma_extra + * + * Configures the peripheral to have four additional DMA signals on the interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------- + * ALT_UART_CPR_DMA_EXTRA_E_END | 0x1 | DMA Extra Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_DMA_EXTRA + * + * DMA Extra Supported + */ +#define ALT_UART_CPR_DMA_EXTRA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */ +#define ALT_UART_CPR_DMA_EXTRA_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */ +#define ALT_UART_CPR_DMA_EXTRA_MSB 13 +/* The width in bits of the ALT_UART_CPR_DMA_EXTRA register field. */ +#define ALT_UART_CPR_DMA_EXTRA_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_DMA_EXTRA register field value. */ +#define ALT_UART_CPR_DMA_EXTRA_SET_MSK 0x00002000 +/* The mask used to clear the ALT_UART_CPR_DMA_EXTRA register field value. */ +#define ALT_UART_CPR_DMA_EXTRA_CLR_MSK 0xffffdfff +/* The reset value of the ALT_UART_CPR_DMA_EXTRA register field. */ +#define ALT_UART_CPR_DMA_EXTRA_RESET 0x1 +/* Extracts the ALT_UART_CPR_DMA_EXTRA field value from a register. */ +#define ALT_UART_CPR_DMA_EXTRA_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_UART_CPR_DMA_EXTRA register field value suitable for setting the register. */ +#define ALT_UART_CPR_DMA_EXTRA_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : FIFO Depth - fifo_mode + * + * Receiver and Transmitter FIFO depth in bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------- + * ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES | 0x80 | FIFO Depth 128 bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_FIFO_MOD + * + * FIFO Depth 128 bytes + */ +#define ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES 0x80 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_MOD register field. */ +#define ALT_UART_CPR_FIFO_MOD_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_MOD register field. */ +#define ALT_UART_CPR_FIFO_MOD_MSB 23 +/* The width in bits of the ALT_UART_CPR_FIFO_MOD register field. */ +#define ALT_UART_CPR_FIFO_MOD_WIDTH 8 +/* The mask used to set the ALT_UART_CPR_FIFO_MOD register field value. */ +#define ALT_UART_CPR_FIFO_MOD_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_UART_CPR_FIFO_MOD register field value. */ +#define ALT_UART_CPR_FIFO_MOD_CLR_MSK 0xff00ffff +/* The reset value of the ALT_UART_CPR_FIFO_MOD register field. */ +#define ALT_UART_CPR_FIFO_MOD_RESET 0x37 +/* Extracts the ALT_UART_CPR_FIFO_MOD field value from a register. */ +#define ALT_UART_CPR_FIFO_MOD_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_UART_CPR_FIFO_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_FIFO_MOD_SET(value) (((value) << 16) & 0x00ff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_CPR. + */ +struct ALT_UART_CPR_s +{ + const uint32_t apbdatawidth : 2; /* APB DATA WIDTH */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t afce_mode : 1; /* Auto Flow Control */ + const uint32_t thre_mode : 1; /* THRE MODE */ + const uint32_t sir_mode : 1; /* SIR MODE Unsupported */ + const uint32_t sir_lp_mode : 1; /* SIR LP MODE Unsupported */ + const uint32_t additional_feat : 1; /* ADDITIONAL FEATURES Supported */ + const uint32_t fifo_access : 1; /* FIFO ACCESS Supported */ + const uint32_t fifo_stat : 1; /* FIFO STAT Supported */ + const uint32_t shadow : 1; /* SHADOW Supported */ + const uint32_t uart_add_encoded_param : 1; /* Configuartion ID Register Present */ + const uint32_t dma_extra : 1; /* DMA EXTRA Supported */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t fifo_mode : 8; /* FIFO Depth */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_CPR. */ +typedef volatile struct ALT_UART_CPR_s ALT_UART_CPR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_CPR register from the beginning of the component. */ +#define ALT_UART_CPR_OFST 0xf4 +/* The address of the ALT_UART_CPR register. */ +#define ALT_UART_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST)) + +/* + * Register : Component Version - ucv + * + * Used only with Additional Features + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------- + * [31:0] | R | 0x3331312a | ASCII version + * + */ +/* + * Field : ASCII version - uart_component_version + * + * ASCII value for each number in the version, followed by *For example 32_30_31_2A + * represents the version 2.01a + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_MSB 31 +/* The width in bits of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_WIDTH 32 +/* The mask used to set the ALT_UART_UCV_UART_COMPONENT_VER register field value. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_SET_MSK 0xffffffff +/* The mask used to clear the ALT_UART_UCV_UART_COMPONENT_VER register field value. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_CLR_MSK 0x00000000 +/* The reset value of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_RESET 0x3331312a +/* Extracts the ALT_UART_UCV_UART_COMPONENT_VER field value from a register. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_UART_UCV_UART_COMPONENT_VER register field value suitable for setting the register. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_UCV. + */ +struct ALT_UART_UCV_s +{ + const uint32_t uart_component_version : 32; /* ASCII version */ +}; + +/* The typedef declaration for register ALT_UART_UCV. */ +typedef volatile struct ALT_UART_UCV_s ALT_UART_UCV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_UCV register from the beginning of the component. */ +#define ALT_UART_UCV_OFST 0xf8 +/* The address of the ALT_UART_UCV register. */ +#define ALT_UART_UCV_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_UCV_OFST)) + +/* + * Register : Component Type Register - ctr + * + * Describes a hex value associated with the component. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------- + * [31:0] | R | 0x44570110 | Peripheral ID + * + */ +/* + * Field : Peripheral ID - peripheral_id + * + * This register contains the peripherals identification code. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */ +#define ALT_UART_CTR_PERIPHERAL_ID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */ +#define ALT_UART_CTR_PERIPHERAL_ID_MSB 31 +/* The width in bits of the ALT_UART_CTR_PERIPHERAL_ID register field. */ +#define ALT_UART_CTR_PERIPHERAL_ID_WIDTH 32 +/* The mask used to set the ALT_UART_CTR_PERIPHERAL_ID register field value. */ +#define ALT_UART_CTR_PERIPHERAL_ID_SET_MSK 0xffffffff +/* The mask used to clear the ALT_UART_CTR_PERIPHERAL_ID register field value. */ +#define ALT_UART_CTR_PERIPHERAL_ID_CLR_MSK 0x00000000 +/* The reset value of the ALT_UART_CTR_PERIPHERAL_ID register field. */ +#define ALT_UART_CTR_PERIPHERAL_ID_RESET 0x44570110 +/* Extracts the ALT_UART_CTR_PERIPHERAL_ID field value from a register. */ +#define ALT_UART_CTR_PERIPHERAL_ID_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_UART_CTR_PERIPHERAL_ID register field value suitable for setting the register. */ +#define ALT_UART_CTR_PERIPHERAL_ID_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_CTR. + */ +struct ALT_UART_CTR_s +{ + const uint32_t peripheral_id : 32; /* Peripheral ID */ +}; + +/* The typedef declaration for register ALT_UART_CTR. */ +typedef volatile struct ALT_UART_CTR_s ALT_UART_CTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_CTR register from the beginning of the component. */ +#define ALT_UART_CTR_OFST 0xfc +/* The address of the ALT_UART_CTR register. */ +#define ALT_UART_CTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CTR_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_UART. + */ +struct ALT_UART_s +{ + volatile ALT_UART_RBR_THR_DLL_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */ + volatile ALT_UART_IER_DLH_t ier_dlh; /* ALT_UART_IER_DLH */ + /* Union for registers colocated at base address offset #0x. */ + union + { + volatile ALT_UART_IIR_t iir; /* ALT_UART_IIR */ + volatile ALT_UART_FCR_t fcr; /* ALT_UART_FCR */ + } _u_0x8; + volatile ALT_UART_LCR_t lcr; /* ALT_UART_LCR */ + volatile ALT_UART_MCR_t mcr; /* ALT_UART_MCR */ + volatile ALT_UART_LSR_t lsr; /* ALT_UART_LSR */ + volatile ALT_UART_MSR_t msr; /* ALT_UART_MSR */ + volatile ALT_UART_SCR_t scr; /* ALT_UART_SCR */ + volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */ + volatile ALT_UART_SRBR_t srbr; /* ALT_UART_SRBR */ + volatile ALT_UART_STHR_t sthr; /* ALT_UART_STHR */ + volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */ + volatile ALT_UART_FAR_t far; /* ALT_UART_FAR */ + volatile ALT_UART_TFR_t tfr; /* ALT_UART_TFR */ + volatile ALT_UART_RFW_t RFW; /* ALT_UART_RFW */ + volatile ALT_UART_USR_t usr; /* ALT_UART_USR */ + volatile ALT_UART_TFL_t tfl; /* ALT_UART_TFL */ + volatile ALT_UART_RFL_t rfl; /* ALT_UART_RFL */ + volatile ALT_UART_SRR_t srr; /* ALT_UART_SRR */ + volatile ALT_UART_SRTS_t srts; /* ALT_UART_SRTS */ + volatile ALT_UART_SBCR_t sbcr; /* ALT_UART_SBCR */ + volatile ALT_UART_SDMAM_t sdmam; /* ALT_UART_SDMAM */ + volatile ALT_UART_SFE_t sfe; /* ALT_UART_SFE */ + volatile ALT_UART_SRT_t srt; /* ALT_UART_SRT */ + volatile ALT_UART_STET_t stet; /* ALT_UART_STET */ + volatile ALT_UART_HTX_t htx; /* ALT_UART_HTX */ + volatile ALT_UART_DMASA_t dmasa; /* ALT_UART_DMASA */ + volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */ + volatile ALT_UART_CPR_t cpr; /* ALT_UART_CPR */ + volatile ALT_UART_UCV_t ucv; /* ALT_UART_UCV */ + volatile ALT_UART_CTR_t ctr; /* ALT_UART_CTR */ +}; + +/* The typedef declaration for register group ALT_UART. */ +typedef volatile struct ALT_UART_s ALT_UART_t; +/* The struct declaration for the raw register contents of register group ALT_UART. */ +struct ALT_UART_raw_s +{ + volatile uint32_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */ + volatile uint32_t ier_dlh; /* ALT_UART_IER_DLH */ + /* Union for registers colocated at base address offset #0x. */ + union + { + volatile uint32_t iir; /* ALT_UART_IIR */ + volatile uint32_t fcr; /* ALT_UART_FCR */ + } _u_0x8; + volatile uint32_t lcr; /* ALT_UART_LCR */ + volatile uint32_t mcr; /* ALT_UART_MCR */ + volatile uint32_t lsr; /* ALT_UART_LSR */ + volatile uint32_t msr; /* ALT_UART_MSR */ + volatile uint32_t scr; /* ALT_UART_SCR */ + volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */ + volatile uint32_t srbr; /* ALT_UART_SRBR */ + volatile uint32_t sthr; /* ALT_UART_STHR */ + volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */ + volatile uint32_t far; /* ALT_UART_FAR */ + volatile uint32_t tfr; /* ALT_UART_TFR */ + volatile uint32_t RFW; /* ALT_UART_RFW */ + volatile uint32_t usr; /* ALT_UART_USR */ + volatile uint32_t tfl; /* ALT_UART_TFL */ + volatile uint32_t rfl; /* ALT_UART_RFL */ + volatile uint32_t srr; /* ALT_UART_SRR */ + volatile uint32_t srts; /* ALT_UART_SRTS */ + volatile uint32_t sbcr; /* ALT_UART_SBCR */ + volatile uint32_t sdmam; /* ALT_UART_SDMAM */ + volatile uint32_t sfe; /* ALT_UART_SFE */ + volatile uint32_t srt; /* ALT_UART_SRT */ + volatile uint32_t stet; /* ALT_UART_STET */ + volatile uint32_t htx; /* ALT_UART_HTX */ + volatile uint32_t dmasa; /* ALT_UART_DMASA */ + volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */ + volatile uint32_t cpr; /* ALT_UART_CPR */ + volatile uint32_t ucv; /* ALT_UART_UCV */ + volatile uint32_t ctr; /* ALT_UART_CTR */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_UART. */ +typedef volatile struct ALT_UART_raw_s ALT_UART_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_UART_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h new file mode 100644 index 0000000000..c6b312b415 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h @@ -0,0 +1,8026 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - hps */ + +#ifndef __ALTERA_HPS_H__ +#define __ALTERA_HPS_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#define ALT_HPS_ADDR 0 +/* + * Address Space : ALT_HPS + * + */ +/* + * Component Instance : stm + * + * Instance stm of component ALT_STM. + * + * + */ +/* The address of the ALT_STM_REG register for the ALT_STM instance. */ +#define ALT_STM_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_STM_ADDR) + ALT_STM_REG_OFST)) +/* The base address byte offset for the start of the ALT_STM component. */ +#define ALT_STM_OFST 0xfc000000 +/* The start address of the ALT_STM component. */ +#define ALT_STM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_STM_OFST)) +/* The lower bound address range of the ALT_STM component. */ +#define ALT_STM_LB_ADDR ALT_STM_ADDR +/* The upper bound address range of the ALT_STM component. */ +#define ALT_STM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_STM_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : dap + * + * Instance dap of component ALT_DAP. + * + * + */ +/* The address of the ALT_DAP_REG register for the ALT_DAP instance. */ +#define ALT_DAP_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_DAP_ADDR) + ALT_DAP_REG_OFST)) +/* The base address byte offset for the start of the ALT_DAP component. */ +#define ALT_DAP_OFST 0xff000000 +/* The start address of the ALT_DAP component. */ +#define ALT_DAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_DAP_OFST)) +/* The lower bound address range of the ALT_DAP component. */ +#define ALT_DAP_LB_ADDR ALT_DAP_ADDR +/* The upper bound address range of the ALT_DAP component. */ +#define ALT_DAP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_DAP_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : lwfpgaslaves + * + * Instance lwfpgaslaves of component ALT_LWFPGASLVS. + * + * + */ +/* The base address byte offset for the start of the ALT_LWFPGASLVS component. */ +#define ALT_LWFPGASLVS_OFST 0xff200000 +/* The start address of the ALT_LWFPGASLVS component. */ +#define ALT_LWFPGASLVS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_LWFPGASLVS_OFST)) +/* The lower bound address range of the ALT_LWFPGASLVS component. */ +#define ALT_LWFPGASLVS_LB_ADDR ALT_LWFPGASLVS_ADDR +/* The upper bound address range of the ALT_LWFPGASLVS component. */ +#define ALT_LWFPGASLVS_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWFPGASLVS_ADDR) + 0x200000) - 1)) + + +/* + * Component Instance : lwhps2fpgaregs + * + * Instance lwhps2fpgaregs of component ALT_LWH2F. + * + * + */ +/* + * Register Group Instance : idgrp + * + * Instance idgrp of register group ALT_LWH2F_ID. + * + * + */ +/* The address of the ALT_LWH2F_ID_PERIPH_ID_4 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_4_OFST)) +/* The address of the ALT_LWH2F_ID_PERIPH_ID_0 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_0_OFST)) +/* The address of the ALT_LWH2F_ID_PERIPH_ID_1 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_1_OFST)) +/* The address of the ALT_LWH2F_ID_PERIPH_ID_2 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_2_OFST)) +/* The address of the ALT_LWH2F_ID_PERIPH_ID_3 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_3_OFST)) +/* The address of the ALT_LWH2F_ID_COMP_ID_0 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_0_OFST)) +/* The address of the ALT_LWH2F_ID_COMP_ID_1 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_1_OFST)) +/* The address of the ALT_LWH2F_ID_COMP_ID_2 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_2_OFST)) +/* The address of the ALT_LWH2F_ID_COMP_ID_3 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_3_OFST)) +/* The base address byte offset for the start of the ALT_LWH2F_ID component. */ +#define ALT_LWH2F_ID_OFST 0x1000 +/* The start address of the ALT_LWH2F_ID component. */ +#define ALT_LWH2F_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ADDR) + ALT_LWH2F_ID_OFST)) +/* The lower bound address range of the ALT_LWH2F_ID component. */ +#define ALT_LWH2F_ID_LB_ADDR ALT_LWH2F_ID_ADDR +/* The upper bound address range of the ALT_LWH2F_ID component. */ +#define ALT_LWH2F_ID_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + 0x1000) - 1)) + + +/* + * Register Group Instance : mastergrp + * + * Instance mastergrp of register group ALT_LWH2F_MST. + * + * + */ +/* + * Register Group Instance : mastergrp_fpga2hpsregs + * + * Instance mastergrp_fpga2hpsregs of register group ALT_LWH2F_MST_F2H. + * + * + */ +/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register for the ALT_LWH2F_MST_MST_F2H instance. */ +#define ALT_LWH2F_MST_MST_F2H_FN_MOD_BM_ISS_ADDR ALT_LWH2F_FN_MOD_BM_ISS_ADDR(ALT_LWH2F_MST_MST_F2H_ADDR) +/* The address of the ALT_LWH2F_AHB_CNTL register for the ALT_LWH2F_MST_MST_F2H instance. */ +#define ALT_LWH2F_MST_MST_F2H_AHB_CNTL_ADDR ALT_LWH2F_AHB_CNTL_ADDR(ALT_LWH2F_MST_MST_F2H_ADDR) +/* The base address byte offset for the start of the ALT_LWH2F_MST_MST_F2H component. */ +#define ALT_LWH2F_MST_MST_F2H_OFST 0x0 +/* The start address of the ALT_LWH2F_MST_MST_F2H component. */ +#define ALT_LWH2F_MST_MST_F2H_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + ALT_LWH2F_MST_MST_F2H_OFST)) +/* The lower bound address range of the ALT_LWH2F_MST_MST_F2H component. */ +#define ALT_LWH2F_MST_MST_F2H_LB_ADDR ALT_LWH2F_MST_MST_F2H_ADDR +/* The upper bound address range of the ALT_LWH2F_MST_MST_F2H component. */ +#define ALT_LWH2F_MST_MST_F2H_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_MST_F2H_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_hps2fpgaregs + * + * Instance mastergrp_hps2fpgaregs of register group ALT_LWH2F_MST_H2F. + * + * + */ +/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register for the ALT_LWH2F_MST_MST_H2F instance. */ +#define ALT_LWH2F_MST_MST_H2F_FN_MOD_BM_ISS_ADDR ALT_LWH2F_FN_MOD_BM_ISS_ADDR(ALT_LWH2F_MST_MST_H2F_ADDR) +/* The address of the ALT_LWH2F_AHB_CNTL register for the ALT_LWH2F_MST_MST_H2F instance. */ +#define ALT_LWH2F_MST_MST_H2F_AHB_CNTL_ADDR ALT_LWH2F_AHB_CNTL_ADDR(ALT_LWH2F_MST_MST_H2F_ADDR) +/* The base address byte offset for the start of the ALT_LWH2F_MST_MST_H2F component. */ +#define ALT_LWH2F_MST_MST_H2F_OFST 0x1000 +/* The start address of the ALT_LWH2F_MST_MST_H2F component. */ +#define ALT_LWH2F_MST_MST_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + ALT_LWH2F_MST_MST_H2F_OFST)) +/* The lower bound address range of the ALT_LWH2F_MST_MST_H2F component. */ +#define ALT_LWH2F_MST_MST_H2F_LB_ADDR ALT_LWH2F_MST_MST_H2F_ADDR +/* The upper bound address range of the ALT_LWH2F_MST_MST_H2F component. */ +#define ALT_LWH2F_MST_MST_H2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_MST_H2F_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_b32 + * + * Instance mastergrp_b32 of register group ALT_LWH2F_MST_B32. + * + * + */ +/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register for the ALT_LWH2F_MST_MST_B32 instance. */ +#define ALT_LWH2F_MST_MST_B32_FN_MOD_BM_ISS_ADDR ALT_LWH2F_FN_MOD_BM_ISS_ADDR(ALT_LWH2F_MST_MST_B32_ADDR) +/* The address of the ALT_LWH2F_WR_TIDEMARK register for the ALT_LWH2F_MST_MST_B32 instance. */ +#define ALT_LWH2F_MST_MST_B32_WR_TIDEMARK_ADDR ALT_LWH2F_WR_TIDEMARK_ADDR(ALT_LWH2F_MST_MST_B32_ADDR) +/* The address of the ALT_LWH2F_FN_MOD register for the ALT_LWH2F_MST_MST_B32 instance. */ +#define ALT_LWH2F_MST_MST_B32_FN_MOD_ADDR ALT_LWH2F_FN_MOD_ADDR(ALT_LWH2F_MST_MST_B32_ADDR) +/* The base address byte offset for the start of the ALT_LWH2F_MST_MST_B32 component. */ +#define ALT_LWH2F_MST_MST_B32_OFST 0x3000 +/* The start address of the ALT_LWH2F_MST_MST_B32 component. */ +#define ALT_LWH2F_MST_MST_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + ALT_LWH2F_MST_MST_B32_OFST)) +/* The lower bound address range of the ALT_LWH2F_MST_MST_B32 component. */ +#define ALT_LWH2F_MST_MST_B32_LB_ADDR ALT_LWH2F_MST_MST_B32_ADDR +/* The upper bound address range of the ALT_LWH2F_MST_MST_B32 component. */ +#define ALT_LWH2F_MST_MST_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_MST_B32_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_LWH2F_MST component. */ +#define ALT_LWH2F_MST_OFST 0x2000 +/* The start address of the ALT_LWH2F_MST component. */ +#define ALT_LWH2F_MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ADDR) + ALT_LWH2F_MST_OFST)) +/* The lower bound address range of the ALT_LWH2F_MST component. */ +#define ALT_LWH2F_MST_LB_ADDR ALT_LWH2F_MST_ADDR +/* The upper bound address range of the ALT_LWH2F_MST component. */ +#define ALT_LWH2F_MST_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + 0x310c) - 1)) + + +/* + * Register Group Instance : slavegrp + * + * Instance slavegrp of register group ALT_LWH2F_SLV. + * + * + */ +/* + * Register Group Instance : slavegrp_b32 + * + * Instance slavegrp_b32 of register group ALT_LWH2F_SLV_B32. + * + * + */ +/* The address of the ALT_LWH2F_FN_MOD register for the ALT_LWH2F_SLV_SLV_B32 instance. */ +#define ALT_LWH2F_SLV_SLV_B32_FN_MOD_ADDR ALT_LWH2F_FN_MOD_ADDR(ALT_LWH2F_SLV_SLV_B32_ADDR) +/* The base address byte offset for the start of the ALT_LWH2F_SLV_SLV_B32 component. */ +#define ALT_LWH2F_SLV_SLV_B32_OFST 0x3000 +/* The start address of the ALT_LWH2F_SLV_SLV_B32 component. */ +#define ALT_LWH2F_SLV_SLV_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_SLV_ADDR) + ALT_LWH2F_SLV_SLV_B32_OFST)) +/* The lower bound address range of the ALT_LWH2F_SLV_SLV_B32 component. */ +#define ALT_LWH2F_SLV_SLV_B32_LB_ADDR ALT_LWH2F_SLV_SLV_B32_ADDR +/* The upper bound address range of the ALT_LWH2F_SLV_SLV_B32 component. */ +#define ALT_LWH2F_SLV_SLV_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_SLV_SLV_B32_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_LWH2F_SLV component. */ +#define ALT_LWH2F_SLV_OFST 0x42000 +/* The start address of the ALT_LWH2F_SLV component. */ +#define ALT_LWH2F_SLV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ADDR) + ALT_LWH2F_SLV_OFST)) +/* The lower bound address range of the ALT_LWH2F_SLV component. */ +#define ALT_LWH2F_SLV_LB_ADDR ALT_LWH2F_SLV_ADDR +/* The upper bound address range of the ALT_LWH2F_SLV component. */ +#define ALT_LWH2F_SLV_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_SLV_ADDR) + 0x310c) - 1)) + + +/* The base address byte offset for the start of the ALT_LWH2F component. */ +#define ALT_LWH2F_OFST 0xff400000 +/* The start address of the ALT_LWH2F component. */ +#define ALT_LWH2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_LWH2F_OFST)) +/* The lower bound address range of the ALT_LWH2F component. */ +#define ALT_LWH2F_LB_ADDR ALT_LWH2F_ADDR +/* The upper bound address range of the ALT_LWH2F component. */ +#define ALT_LWH2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_ADDR) + 0x80000) - 1)) + + +/* + * Component Instance : hps2fpgaregs + * + * Instance hps2fpgaregs of component ALT_H2F. + * + * + */ +/* + * Register Group Instance : idgrp + * + * Instance idgrp of register group ALT_H2F_IDGRP. + * + * + */ +/* The address of the ALT_H2F_ID_PERIPH_ID_4 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_4_OFST)) +/* The address of the ALT_H2F_ID_PERIPH_ID_0 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_0_OFST)) +/* The address of the ALT_H2F_ID_PERIPH_ID_1 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_1_OFST)) +/* The address of the ALT_H2F_ID_PERIPH_ID_2 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_2_OFST)) +/* The address of the ALT_H2F_ID_PERIPH_ID_3 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_3_OFST)) +/* The address of the ALT_H2F_ID_COMP_ID_0 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_0_OFST)) +/* The address of the ALT_H2F_ID_COMP_ID_1 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_1_OFST)) +/* The address of the ALT_H2F_ID_COMP_ID_2 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_2_OFST)) +/* The address of the ALT_H2F_ID_COMP_ID_3 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_3_OFST)) +/* The base address byte offset for the start of the ALT_H2F_IDGRP component. */ +#define ALT_H2F_IDGRP_OFST 0x1000 +/* The start address of the ALT_H2F_IDGRP component. */ +#define ALT_H2F_IDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_ADDR) + ALT_H2F_IDGRP_OFST)) +/* The lower bound address range of the ALT_H2F_IDGRP component. */ +#define ALT_H2F_IDGRP_LB_ADDR ALT_H2F_IDGRP_ADDR +/* The upper bound address range of the ALT_H2F_IDGRP component. */ +#define ALT_H2F_IDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + 0x1000) - 1)) + + +/* + * Register Group Instance : mastergrp + * + * Instance mastergrp of register group ALT_H2F_MSTGRP. + * + * + */ +/* + * Register Group Instance : mastergrp_b32 + * + * Instance mastergrp_b32 of register group ALT_H2F_MST_B32. + * + * + */ +/* The address of the ALT_H2F_FN_MOD2 register for the ALT_H2F_MST_MST_B32 instance. */ +#define ALT_H2F_MST_MST_B32_FN_MOD2_ADDR ALT_H2F_FN_MOD2_ADDR(ALT_H2F_MST_MST_B32_ADDR) +/* The address of the ALT_H2F_FN_MOD register for the ALT_H2F_MST_MST_B32 instance. */ +#define ALT_H2F_MST_MST_B32_FN_MOD_ADDR ALT_H2F_FN_MOD_ADDR(ALT_H2F_MST_MST_B32_ADDR) +/* The base address byte offset for the start of the ALT_H2F_MST_MST_B32 component. */ +#define ALT_H2F_MST_MST_B32_OFST 0x0 +/* The start address of the ALT_H2F_MST_MST_B32 component. */ +#define ALT_H2F_MST_MST_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_MSTGRP_ADDR) + ALT_H2F_MST_MST_B32_OFST)) +/* The lower bound address range of the ALT_H2F_MST_MST_B32 component. */ +#define ALT_H2F_MST_MST_B32_LB_ADDR ALT_H2F_MST_MST_B32_ADDR +/* The upper bound address range of the ALT_H2F_MST_MST_B32 component. */ +#define ALT_H2F_MST_MST_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_MST_MST_B32_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_b128 + * + * Instance mastergrp_b128 of register group ALT_H2F_MST_B128. + * + * + */ +/* The address of the ALT_H2F_FN_MOD2 register for the ALT_H2F_MST_MST_B128 instance. */ +#define ALT_H2F_MST_MST_B128_FN_MOD2_ADDR ALT_H2F_FN_MOD2_ADDR(ALT_H2F_MST_MST_B128_ADDR) +/* The address of the ALT_H2F_FN_MOD register for the ALT_H2F_MST_MST_B128 instance. */ +#define ALT_H2F_MST_MST_B128_FN_MOD_ADDR ALT_H2F_FN_MOD_ADDR(ALT_H2F_MST_MST_B128_ADDR) +/* The base address byte offset for the start of the ALT_H2F_MST_MST_B128 component. */ +#define ALT_H2F_MST_MST_B128_OFST 0x2000 +/* The start address of the ALT_H2F_MST_MST_B128 component. */ +#define ALT_H2F_MST_MST_B128_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_MSTGRP_ADDR) + ALT_H2F_MST_MST_B128_OFST)) +/* The lower bound address range of the ALT_H2F_MST_MST_B128 component. */ +#define ALT_H2F_MST_MST_B128_LB_ADDR ALT_H2F_MST_MST_B128_ADDR +/* The upper bound address range of the ALT_H2F_MST_MST_B128 component. */ +#define ALT_H2F_MST_MST_B128_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_MST_MST_B128_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_H2F_MSTGRP component. */ +#define ALT_H2F_MSTGRP_OFST 0x2000 +/* The start address of the ALT_H2F_MSTGRP component. */ +#define ALT_H2F_MSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_ADDR) + ALT_H2F_MSTGRP_OFST)) +/* The lower bound address range of the ALT_H2F_MSTGRP component. */ +#define ALT_H2F_MSTGRP_LB_ADDR ALT_H2F_MSTGRP_ADDR +/* The upper bound address range of the ALT_H2F_MSTGRP component. */ +#define ALT_H2F_MSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_MSTGRP_ADDR) + 0x210c) - 1)) + + +/* The base address byte offset for the start of the ALT_H2F component. */ +#define ALT_H2F_OFST 0xff500000 +/* The start address of the ALT_H2F component. */ +#define ALT_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_H2F_OFST)) +/* The lower bound address range of the ALT_H2F component. */ +#define ALT_H2F_LB_ADDR ALT_H2F_ADDR +/* The upper bound address range of the ALT_H2F component. */ +#define ALT_H2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_ADDR) + 0x8000) - 1)) + + +/* + * Component Instance : fpga2hpsregs + * + * Instance fpga2hpsregs of component ALT_F2H. + * + * + */ +/* + * Register Group Instance : idgrp + * + * Instance idgrp of register group ALT_F2H_IDGRP. + * + * + */ +/* The address of the ALT_F2H_ID_PERIPH_ID_4 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_4_OFST)) +/* The address of the ALT_F2H_ID_PERIPH_ID_0 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_0_OFST)) +/* The address of the ALT_F2H_ID_PERIPH_ID_1 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_1_OFST)) +/* The address of the ALT_F2H_ID_PERIPH_ID_2 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_2_OFST)) +/* The address of the ALT_F2H_ID_PERIPH_ID_3 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_3_OFST)) +/* The address of the ALT_F2H_ID_COMP_ID_0 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_0_OFST)) +/* The address of the ALT_F2H_ID_COMP_ID_1 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_1_OFST)) +/* The address of the ALT_F2H_ID_COMP_ID_2 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_2_OFST)) +/* The address of the ALT_F2H_ID_COMP_ID_3 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_3_OFST)) +/* The base address byte offset for the start of the ALT_F2H_IDGRP component. */ +#define ALT_F2H_IDGRP_OFST 0x1000 +/* The start address of the ALT_F2H_IDGRP component. */ +#define ALT_F2H_IDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_ADDR) + ALT_F2H_IDGRP_OFST)) +/* The lower bound address range of the ALT_F2H_IDGRP component. */ +#define ALT_F2H_IDGRP_LB_ADDR ALT_F2H_IDGRP_ADDR +/* The upper bound address range of the ALT_F2H_IDGRP component. */ +#define ALT_F2H_IDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + 0x1000) - 1)) + + +/* + * Register Group Instance : slavegrp + * + * Instance slavegrp of register group ALT_F2H_SLVGRP. + * + * + */ +/* + * Register Group Instance : slavegrp_b32 + * + * Instance slavegrp_b32 of register group ALT_F2H_SLV_B32. + * + * + */ +/* The address of the ALT_F2H_FN_MOD2 register for the ALT_F2H_SLV_SLV_B32 instance. */ +#define ALT_F2H_SLV_SLV_B32_FN_MOD2_ADDR ALT_F2H_FN_MOD2_ADDR(ALT_F2H_SLV_SLV_B32_ADDR) +/* The address of the ALT_F2H_FN_MOD register for the ALT_F2H_SLV_SLV_B32 instance. */ +#define ALT_F2H_SLV_SLV_B32_FN_MOD_ADDR ALT_F2H_FN_MOD_ADDR(ALT_F2H_SLV_SLV_B32_ADDR) +/* The base address byte offset for the start of the ALT_F2H_SLV_SLV_B32 component. */ +#define ALT_F2H_SLV_SLV_B32_OFST 0x0 +/* The start address of the ALT_F2H_SLV_SLV_B32 component. */ +#define ALT_F2H_SLV_SLV_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_SLVGRP_ADDR) + ALT_F2H_SLV_SLV_B32_OFST)) +/* The lower bound address range of the ALT_F2H_SLV_SLV_B32 component. */ +#define ALT_F2H_SLV_SLV_B32_LB_ADDR ALT_F2H_SLV_SLV_B32_ADDR +/* The upper bound address range of the ALT_F2H_SLV_SLV_B32 component. */ +#define ALT_F2H_SLV_SLV_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_SLV_SLV_B32_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_b128 + * + * Instance slavegrp_b128 of register group ALT_F2H_SLV_B128. + * + * + */ +/* The address of the ALT_F2H_FN_MOD2 register for the ALT_F2H_SLV_SLV_B128 instance. */ +#define ALT_F2H_SLV_SLV_B128_FN_MOD2_ADDR ALT_F2H_FN_MOD2_ADDR(ALT_F2H_SLV_SLV_B128_ADDR) +/* The address of the ALT_F2H_FN_MOD register for the ALT_F2H_SLV_SLV_B128 instance. */ +#define ALT_F2H_SLV_SLV_B128_FN_MOD_ADDR ALT_F2H_FN_MOD_ADDR(ALT_F2H_SLV_SLV_B128_ADDR) +/* The base address byte offset for the start of the ALT_F2H_SLV_SLV_B128 component. */ +#define ALT_F2H_SLV_SLV_B128_OFST 0x2000 +/* The start address of the ALT_F2H_SLV_SLV_B128 component. */ +#define ALT_F2H_SLV_SLV_B128_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_SLVGRP_ADDR) + ALT_F2H_SLV_SLV_B128_OFST)) +/* The lower bound address range of the ALT_F2H_SLV_SLV_B128 component. */ +#define ALT_F2H_SLV_SLV_B128_LB_ADDR ALT_F2H_SLV_SLV_B128_ADDR +/* The upper bound address range of the ALT_F2H_SLV_SLV_B128 component. */ +#define ALT_F2H_SLV_SLV_B128_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_SLV_SLV_B128_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_F2H_SLVGRP component. */ +#define ALT_F2H_SLVGRP_OFST 0x42000 +/* The start address of the ALT_F2H_SLVGRP component. */ +#define ALT_F2H_SLVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_ADDR) + ALT_F2H_SLVGRP_OFST)) +/* The lower bound address range of the ALT_F2H_SLVGRP component. */ +#define ALT_F2H_SLVGRP_LB_ADDR ALT_F2H_SLVGRP_ADDR +/* The upper bound address range of the ALT_F2H_SLVGRP component. */ +#define ALT_F2H_SLVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_SLVGRP_ADDR) + 0x210c) - 1)) + + +/* The base address byte offset for the start of the ALT_F2H component. */ +#define ALT_F2H_OFST 0xff600000 +/* The start address of the ALT_F2H component. */ +#define ALT_F2H_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_F2H_OFST)) +/* The lower bound address range of the ALT_F2H component. */ +#define ALT_F2H_LB_ADDR ALT_F2H_ADDR +/* The upper bound address range of the ALT_F2H component. */ +#define ALT_F2H_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_ADDR) + 0x80000) - 1)) + + +/* + * Component Instance : emac0 + * + * Instance emac0 of component ALT_EMAC. + * + * + */ +/* + * Register Group Instance : gmacgrp + * + * Instance gmacgrp of register group ALT_EMAC_GMAC. + * + * + */ +/* The address of the ALT_EMAC_GMAC_MAC_CFG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_CFG_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_FRM_FLT_ADDR ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_GMII_ADDR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_GMII_ADDR_ADDR ALT_EMAC_GMAC_GMII_ADDR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_GMII_DATA register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_GMII_DATA_ADDR ALT_EMAC_GMAC_GMII_DATA_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_FLOW_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_FLOW_CTL_ADDR ALT_EMAC_GMAC_FLOW_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_TAG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_VLAN_TAG_ADDR ALT_EMAC_GMAC_VLAN_TAG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VER register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_VER_ADDR ALT_EMAC_GMAC_VER_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_DBG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_DBG_ADDR ALT_EMAC_GMAC_DBG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LPI_CTL_STAT_ADDR ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LPI_TMRS_CTL_ADDR ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_INT_STAT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_INT_STAT_ADDR ALT_EMAC_GMAC_INT_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_INT_MSK_ADDR ALT_EMAC_GMAC_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR0_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR0_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR1_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR1_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR2_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR2_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR3_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR3_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR4_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR4_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR5_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR5_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR6_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR6_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR7_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR7_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR8_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR8_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR9_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR9_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR10_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR10_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR11_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR11_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR12_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR12_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR13_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR13_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR14_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR14_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR15_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR15_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MII_CTL_STAT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SGMII_RGMII_SMII_CTL_STAT_ADDR ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_CTL_ADDR ALT_EMAC_GMAC_MMC_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_RX_INT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_TX_INT_ADDR ALT_EMAC_GMAC_MMC_TX_INT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_TX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_TXOCTETCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX64OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX64OCTETS_GB_ADDR ALT_EMAC_GMAC_TX64OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_TX65TO127OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_TX128TO255OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_TX256TO511OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXUNICASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXUNICASTFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXMCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXBCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXUNDERFLOWERROR_ADDR ALT_EMAC_GMAC_TXUNDERFLOWERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXSINGLECOL_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXSINGLECOL_G_ADDR ALT_EMAC_GMAC_TXSINGLECOL_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMULTICOL_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXMULTICOL_G_ADDR ALT_EMAC_GMAC_TXMULTICOL_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXDEFERRED register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXDEFERRED_ADDR ALT_EMAC_GMAC_TXDEFERRED_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXLATECOL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXLATECOL_ADDR ALT_EMAC_GMAC_TXLATECOL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXEXESSCOL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXEXESSCOL_ADDR ALT_EMAC_GMAC_TXEXESSCOL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXCARRIERERR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXCARRIERERR_ADDR ALT_EMAC_GMAC_TXCARRIERERR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOCTETCNT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXOCTETCNT_ADDR ALT_EMAC_GMAC_TXOCTETCNT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXFRMCOUNT_G_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXEXCESSDEF register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXEXCESSDEF_ADDR ALT_EMAC_GMAC_TXEXCESSDEF_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXPAUSEFRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXPAUSEFRMS_ADDR ALT_EMAC_GMAC_TXPAUSEFRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXVLANFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXVLANFRMS_G_ADDR ALT_EMAC_GMAC_TXVLANFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOVERSIZE_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXOVERSIZE_G_ADDR ALT_EMAC_GMAC_TXOVERSIZE_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_RXFRMCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXOCTETCOUNT_G_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXBCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXBCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXMCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXMCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXCRCERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXCRCERROR_ADDR ALT_EMAC_GMAC_RXCRCERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXALIGNMENTERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXALIGNMENTERROR_ADDR ALT_EMAC_GMAC_RXALIGNMENTERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXRUNTERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXRUNTERROR_ADDR ALT_EMAC_GMAC_RXRUNTERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXJABBERERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXJABBERERROR_ADDR ALT_EMAC_GMAC_RXJABBERERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUNDERSIZE_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUNDERSIZE_G_ADDR ALT_EMAC_GMAC_RXUNDERSIZE_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOVERSIZE_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXOVERSIZE_G_ADDR ALT_EMAC_GMAC_RXOVERSIZE_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX64OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX64OCTETS_GB_ADDR ALT_EMAC_GMAC_RX64OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_RX65TO127OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_RX128TO255OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_RX256TO511OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUNICASTFRMS_G_ADDR ALT_EMAC_GMAC_RXUNICASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXLENERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXLENERROR_ADDR ALT_EMAC_GMAC_RXLENERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXOUTOFRANGETYPE_ADDR ALT_EMAC_GMAC_RXOUTOFRANGETYPE_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXPAUSEFRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXPAUSEFRMS_ADDR ALT_EMAC_GMAC_RXPAUSEFRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXFIFOOVF register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXFIFOOVF_ADDR ALT_EMAC_GMAC_RXFIFOOVF_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXVLANFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXVLANFRMS_GB_ADDR ALT_EMAC_GMAC_RXVLANFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXWDERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXWDERROR_ADDR ALT_EMAC_GMAC_RXWDERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXRCVERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXRCVERROR_ADDR ALT_EMAC_GMAC_RXRCVERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXCTLFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXCTLFRMS_G_ADDR ALT_EMAC_GMAC_RXCTLFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_IPC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_IPC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_FRAG_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_UDSBL_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUDP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUDP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXTCP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXTCP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_ERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXICMP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXICMP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_FRAG_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_UDSBL_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUDP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUDP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXTCP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXTCP_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCPERROCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXTCPERROCTETS_ADDR ALT_EMAC_GMAC_RXTCPERROCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXICMP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXICMP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_L3_L4_CTL0_ADDR ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR4_ADDR0_ADDR ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_L3_L4_CTL1_ADDR ALT_EMAC_GMAC_L3_L4_CTL1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR4_ADDR1_ADDR ALT_EMAC_GMAC_LYR4_ADDR1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_L3_L4_CTL2_ADDR ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR4_ADDR2_ADDR ALT_EMAC_GMAC_LYR4_ADDR2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_L3_L4_CTL3_ADDR ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR4_ADDR3_ADDR ALT_EMAC_GMAC_LYR4_ADDR3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG0_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG1_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG2_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG3_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG4_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG4_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG5_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG5_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG6_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG6_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG7_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG7_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_INCL_REG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_VLAN_INCL_REG_ADDR ALT_EMAC_GMAC_VLAN_INCL_REG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_VLAN_HASH_TABLE_REG_ADDR ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TS_CTL_ADDR ALT_EMAC_GMAC_TS_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SUB_SEC_INCREMENT_ADDR ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_SECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_ADDEND register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TS_ADDEND_ADDR ALT_EMAC_GMAC_TS_ADDEND_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TGT_TIME_SECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TGT_TIME_SECS_ADDR ALT_EMAC_GMAC_TGT_TIME_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TGT_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_STAT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TS_STAT_ADDR ALT_EMAC_GMAC_TS_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_PPS_CTL_ADDR ALT_EMAC_GMAC_PPS_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_AUX_TS_NANOSECS_ADDR ALT_EMAC_GMAC_AUX_TS_NANOSECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_AUX_TS_SECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_AUX_TS_SECS_ADDR ALT_EMAC_GMAC_AUX_TS_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_PPS0_INTERVAL_ADDR ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS0_WIDTH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_PPS0_WIDTH_ADDR ALT_EMAC_GMAC_PPS0_WIDTH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR16_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR16_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR17_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR17_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR18_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR18_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR19_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR19_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR20_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR20_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR21_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR21_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR22_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR22_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR23_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR23_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR24_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR24_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR25_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR25_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR26_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR26_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR27_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR27_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR28_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR28_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR29_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR29_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR30_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR30_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR31_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR31_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR32_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR32_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR33_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR33_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR34_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR34_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR35_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR35_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR36_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR36_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR37_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR37_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR38_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR38_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR39_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR39_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR40_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR40_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR41_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR41_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR42_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR42_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR43_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR43_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR44_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR44_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR45_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR45_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR46_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR46_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR47_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR47_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR48_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR48_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR49_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR49_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR50_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR50_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR51_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR51_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR52_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR52_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR53_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR53_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR54_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR54_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR55_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR55_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR56_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR56_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR57_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR57_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR58_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR58_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR59_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR59_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR60_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR60_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR61_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR61_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR62_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR62_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR63_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR63_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR64_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR64_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR65_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR65_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR66_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR66_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR67_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR67_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR68_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR68_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR69_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR69_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR70_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR70_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR71_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR71_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR72_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR72_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR73_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR73_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR74_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR74_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR75_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR75_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR76_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR76_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR77_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR77_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR78_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR78_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR79_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR79_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR80_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR80_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR81_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR81_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR82_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR82_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR83_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR83_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR84_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR84_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR85_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR85_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR86_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR86_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR87_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR87_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR88_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR88_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR89_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR89_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR90_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR90_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR91_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR91_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR92_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR92_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR93_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR93_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR94_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR94_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR95_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR95_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR96_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR96_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR97_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR97_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR98_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR98_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR99_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR99_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR100_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR100_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR101_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR101_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR102_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR102_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR103_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR103_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR104_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR104_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR105_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR105_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR106_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR106_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR107_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR107_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR108_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR108_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR109_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR109_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR110_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR110_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR111_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR111_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR112_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR112_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR113_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR113_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR114_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR114_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR115_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR115_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR116_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR116_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR117_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR117_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR118_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR118_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR119_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR119_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR120_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR120_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR121_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR121_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR122_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR122_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR123_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR123_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR124_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR124_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR125_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR125_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR126_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR126_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR127_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR127_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The base address byte offset for the start of the ALT_EMAC0_GMACGRP component. */ +#define ALT_EMAC0_GMACGRP_OFST 0x0 +/* The start address of the ALT_EMAC0_GMACGRP component. */ +#define ALT_EMAC0_GMACGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC0_ADDR) + ALT_EMAC0_GMACGRP_OFST)) +/* The lower bound address range of the ALT_EMAC0_GMACGRP component. */ +#define ALT_EMAC0_GMACGRP_LB_ADDR ALT_EMAC0_GMACGRP_ADDR +/* The upper bound address range of the ALT_EMAC0_GMACGRP component. */ +#define ALT_EMAC0_GMACGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC0_GMACGRP_ADDR) + 0xb80) - 1)) + + +/* + * Register Group Instance : dmagrp + * + * Instance dmagrp of register group ALT_EMAC_DMA. + * + * + */ +/* The address of the ALT_EMAC_DMA_BUS_MOD register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_BUS_MOD_ADDR ALT_EMAC_DMA_BUS_MOD_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_TX_POLL_DEMAND register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_TX_POLL_DEMAND_ADDR ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_POLL_DEMAND register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_RX_POLL_DEMAND_ADDR ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_RX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_TX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_STAT register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_STAT_ADDR ALT_EMAC_DMA_STAT_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_OP_MOD register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_OP_MOD_ADDR ALT_EMAC_DMA_OP_MOD_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_INT_EN register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_INT_EN_ADDR ALT_EMAC_DMA_INT_EN_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_MISSED_FRM_AND_BUF_OVF_CNTR_ADDR ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_INT_WDT register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_RX_INT_WDT_ADDR ALT_EMAC_DMA_RX_INT_WDT_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_AXI_BUS_MOD register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_AXI_BUS_MOD_ADDR ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_AHB_OR_AXI_STAT_ADDR ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_CUR_HOST_TX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_CUR_HOST_RX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_CUR_HOST_TX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_CUR_HOST_RX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_HW_FEATURE register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_HW_FEATURE_ADDR ALT_EMAC_DMA_HW_FEATURE_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The base address byte offset for the start of the ALT_EMAC0_DMAGRP component. */ +#define ALT_EMAC0_DMAGRP_OFST 0x1000 +/* The start address of the ALT_EMAC0_DMAGRP component. */ +#define ALT_EMAC0_DMAGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC0_ADDR) + ALT_EMAC0_DMAGRP_OFST)) +/* The lower bound address range of the ALT_EMAC0_DMAGRP component. */ +#define ALT_EMAC0_DMAGRP_LB_ADDR ALT_EMAC0_DMAGRP_ADDR +/* The upper bound address range of the ALT_EMAC0_DMAGRP component. */ +#define ALT_EMAC0_DMAGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC0_DMAGRP_ADDR) + 0x5c) - 1)) + + +/* The base address byte offset for the start of the ALT_EMAC0 component. */ +#define ALT_EMAC0_OFST 0xff700000 +/* The start address of the ALT_EMAC0 component. */ +#define ALT_EMAC0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_EMAC0_OFST)) +/* The lower bound address range of the ALT_EMAC0 component. */ +#define ALT_EMAC0_LB_ADDR ALT_EMAC0_ADDR +/* The upper bound address range of the ALT_EMAC0 component. */ +#define ALT_EMAC0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC0_ADDR) + 0x2000) - 1)) + + +/* + * Component Instance : emac1 + * + * Instance emac1 of component ALT_EMAC. + * + * + */ +/* + * Register Group Instance : gmacgrp + * + * Instance gmacgrp of register group ALT_EMAC_GMAC. + * + * + */ +/* The address of the ALT_EMAC_GMAC_MAC_CFG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_CFG_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_FRM_FLT_ADDR ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_GMII_ADDR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_GMII_ADDR_ADDR ALT_EMAC_GMAC_GMII_ADDR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_GMII_DATA register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_GMII_DATA_ADDR ALT_EMAC_GMAC_GMII_DATA_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_FLOW_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_FLOW_CTL_ADDR ALT_EMAC_GMAC_FLOW_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_TAG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_VLAN_TAG_ADDR ALT_EMAC_GMAC_VLAN_TAG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VER register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_VER_ADDR ALT_EMAC_GMAC_VER_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_DBG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_DBG_ADDR ALT_EMAC_GMAC_DBG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LPI_CTL_STAT_ADDR ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LPI_TMRS_CTL_ADDR ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_INT_STAT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_INT_STAT_ADDR ALT_EMAC_GMAC_INT_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_INT_MSK_ADDR ALT_EMAC_GMAC_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR0_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR0_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR1_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR1_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR2_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR2_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR3_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR3_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR4_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR4_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR5_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR5_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR6_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR6_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR7_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR7_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR8_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR8_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR9_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR9_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR10_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR10_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR11_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR11_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR12_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR12_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR13_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR13_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR14_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR14_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR15_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR15_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MII_CTL_STAT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SGMII_RGMII_SMII_CTL_STAT_ADDR ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_CTL_ADDR ALT_EMAC_GMAC_MMC_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_RX_INT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_TX_INT_ADDR ALT_EMAC_GMAC_MMC_TX_INT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_TX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_TXOCTETCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX64OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX64OCTETS_GB_ADDR ALT_EMAC_GMAC_TX64OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_TX65TO127OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_TX128TO255OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_TX256TO511OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXUNICASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXUNICASTFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXMCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXBCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXUNDERFLOWERROR_ADDR ALT_EMAC_GMAC_TXUNDERFLOWERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXSINGLECOL_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXSINGLECOL_G_ADDR ALT_EMAC_GMAC_TXSINGLECOL_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMULTICOL_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXMULTICOL_G_ADDR ALT_EMAC_GMAC_TXMULTICOL_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXDEFERRED register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXDEFERRED_ADDR ALT_EMAC_GMAC_TXDEFERRED_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXLATECOL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXLATECOL_ADDR ALT_EMAC_GMAC_TXLATECOL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXEXESSCOL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXEXESSCOL_ADDR ALT_EMAC_GMAC_TXEXESSCOL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXCARRIERERR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXCARRIERERR_ADDR ALT_EMAC_GMAC_TXCARRIERERR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOCTETCNT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXOCTETCNT_ADDR ALT_EMAC_GMAC_TXOCTETCNT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXFRMCOUNT_G_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXEXCESSDEF register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXEXCESSDEF_ADDR ALT_EMAC_GMAC_TXEXCESSDEF_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXPAUSEFRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXPAUSEFRMS_ADDR ALT_EMAC_GMAC_TXPAUSEFRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXVLANFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXVLANFRMS_G_ADDR ALT_EMAC_GMAC_TXVLANFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOVERSIZE_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXOVERSIZE_G_ADDR ALT_EMAC_GMAC_TXOVERSIZE_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_RXFRMCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXOCTETCOUNT_G_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXBCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXBCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXMCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXMCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXCRCERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXCRCERROR_ADDR ALT_EMAC_GMAC_RXCRCERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXALIGNMENTERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXALIGNMENTERROR_ADDR ALT_EMAC_GMAC_RXALIGNMENTERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXRUNTERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXRUNTERROR_ADDR ALT_EMAC_GMAC_RXRUNTERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXJABBERERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXJABBERERROR_ADDR ALT_EMAC_GMAC_RXJABBERERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUNDERSIZE_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUNDERSIZE_G_ADDR ALT_EMAC_GMAC_RXUNDERSIZE_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOVERSIZE_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXOVERSIZE_G_ADDR ALT_EMAC_GMAC_RXOVERSIZE_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX64OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX64OCTETS_GB_ADDR ALT_EMAC_GMAC_RX64OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_RX65TO127OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_RX128TO255OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_RX256TO511OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUNICASTFRMS_G_ADDR ALT_EMAC_GMAC_RXUNICASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXLENERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXLENERROR_ADDR ALT_EMAC_GMAC_RXLENERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXOUTOFRANGETYPE_ADDR ALT_EMAC_GMAC_RXOUTOFRANGETYPE_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXPAUSEFRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXPAUSEFRMS_ADDR ALT_EMAC_GMAC_RXPAUSEFRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXFIFOOVF register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXFIFOOVF_ADDR ALT_EMAC_GMAC_RXFIFOOVF_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXVLANFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXVLANFRMS_GB_ADDR ALT_EMAC_GMAC_RXVLANFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXWDERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXWDERROR_ADDR ALT_EMAC_GMAC_RXWDERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXRCVERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXRCVERROR_ADDR ALT_EMAC_GMAC_RXRCVERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXCTLFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXCTLFRMS_G_ADDR ALT_EMAC_GMAC_RXCTLFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_IPC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_IPC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_FRAG_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_UDSBL_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUDP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUDP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXTCP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXTCP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_ERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXICMP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXICMP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_FRAG_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_UDSBL_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUDP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUDP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXTCP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXTCP_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCPERROCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXTCPERROCTETS_ADDR ALT_EMAC_GMAC_RXTCPERROCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXICMP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXICMP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_L3_L4_CTL0_ADDR ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR4_ADDR0_ADDR ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_L3_L4_CTL1_ADDR ALT_EMAC_GMAC_L3_L4_CTL1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR4_ADDR1_ADDR ALT_EMAC_GMAC_LYR4_ADDR1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_L3_L4_CTL2_ADDR ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR4_ADDR2_ADDR ALT_EMAC_GMAC_LYR4_ADDR2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_L3_L4_CTL3_ADDR ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR4_ADDR3_ADDR ALT_EMAC_GMAC_LYR4_ADDR3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG0_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG1_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG2_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG3_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG4_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG4_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG5_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG5_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG6_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG6_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG7_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG7_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_INCL_REG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_VLAN_INCL_REG_ADDR ALT_EMAC_GMAC_VLAN_INCL_REG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_VLAN_HASH_TABLE_REG_ADDR ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TS_CTL_ADDR ALT_EMAC_GMAC_TS_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SUB_SEC_INCREMENT_ADDR ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_SECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_ADDEND register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TS_ADDEND_ADDR ALT_EMAC_GMAC_TS_ADDEND_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TGT_TIME_SECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TGT_TIME_SECS_ADDR ALT_EMAC_GMAC_TGT_TIME_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TGT_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_STAT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TS_STAT_ADDR ALT_EMAC_GMAC_TS_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_PPS_CTL_ADDR ALT_EMAC_GMAC_PPS_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_AUX_TS_NANOSECS_ADDR ALT_EMAC_GMAC_AUX_TS_NANOSECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_AUX_TS_SECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_AUX_TS_SECS_ADDR ALT_EMAC_GMAC_AUX_TS_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_PPS0_INTERVAL_ADDR ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS0_WIDTH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_PPS0_WIDTH_ADDR ALT_EMAC_GMAC_PPS0_WIDTH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR16_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR16_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR17_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR17_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR18_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR18_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR19_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR19_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR20_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR20_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR21_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR21_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR22_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR22_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR23_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR23_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR24_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR24_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR25_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR25_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR26_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR26_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR27_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR27_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR28_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR28_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR29_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR29_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR30_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR30_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR31_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR31_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR32_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR32_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR33_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR33_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR34_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR34_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR35_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR35_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR36_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR36_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR37_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR37_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR38_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR38_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR39_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR39_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR40_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR40_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR41_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR41_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR42_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR42_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR43_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR43_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR44_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR44_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR45_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR45_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR46_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR46_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR47_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR47_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR48_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR48_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR49_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR49_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR50_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR50_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR51_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR51_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR52_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR52_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR53_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR53_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR54_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR54_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR55_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR55_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR56_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR56_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR57_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR57_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR58_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR58_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR59_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR59_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR60_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR60_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR61_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR61_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR62_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR62_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR63_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR63_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR64_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR64_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR65_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR65_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR66_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR66_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR67_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR67_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR68_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR68_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR69_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR69_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR70_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR70_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR71_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR71_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR72_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR72_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR73_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR73_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR74_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR74_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR75_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR75_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR76_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR76_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR77_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR77_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR78_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR78_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR79_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR79_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR80_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR80_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR81_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR81_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR82_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR82_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR83_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR83_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR84_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR84_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR85_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR85_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR86_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR86_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR87_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR87_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR88_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR88_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR89_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR89_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR90_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR90_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR91_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR91_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR92_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR92_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR93_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR93_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR94_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR94_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR95_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR95_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR96_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR96_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR97_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR97_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR98_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR98_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR99_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR99_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR100_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR100_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR101_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR101_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR102_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR102_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR103_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR103_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR104_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR104_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR105_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR105_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR106_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR106_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR107_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR107_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR108_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR108_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR109_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR109_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR110_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR110_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR111_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR111_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR112_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR112_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR113_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR113_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR114_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR114_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR115_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR115_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR116_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR116_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR117_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR117_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR118_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR118_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR119_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR119_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR120_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR120_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR121_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR121_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR122_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR122_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR123_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR123_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR124_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR124_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR125_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR125_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR126_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR126_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR127_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR127_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The base address byte offset for the start of the ALT_EMAC1_GMACGRP component. */ +#define ALT_EMAC1_GMACGRP_OFST 0x0 +/* The start address of the ALT_EMAC1_GMACGRP component. */ +#define ALT_EMAC1_GMACGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC1_ADDR) + ALT_EMAC1_GMACGRP_OFST)) +/* The lower bound address range of the ALT_EMAC1_GMACGRP component. */ +#define ALT_EMAC1_GMACGRP_LB_ADDR ALT_EMAC1_GMACGRP_ADDR +/* The upper bound address range of the ALT_EMAC1_GMACGRP component. */ +#define ALT_EMAC1_GMACGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC1_GMACGRP_ADDR) + 0xb80) - 1)) + + +/* + * Register Group Instance : dmagrp + * + * Instance dmagrp of register group ALT_EMAC_DMA. + * + * + */ +/* The address of the ALT_EMAC_DMA_BUS_MOD register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_BUS_MOD_ADDR ALT_EMAC_DMA_BUS_MOD_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_TX_POLL_DEMAND register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_TX_POLL_DEMAND_ADDR ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_POLL_DEMAND register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_RX_POLL_DEMAND_ADDR ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_RX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_TX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_STAT register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_STAT_ADDR ALT_EMAC_DMA_STAT_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_OP_MOD register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_OP_MOD_ADDR ALT_EMAC_DMA_OP_MOD_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_INT_EN register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_INT_EN_ADDR ALT_EMAC_DMA_INT_EN_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_MISSED_FRM_AND_BUF_OVF_CNTR_ADDR ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_INT_WDT register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_RX_INT_WDT_ADDR ALT_EMAC_DMA_RX_INT_WDT_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_AXI_BUS_MOD register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_AXI_BUS_MOD_ADDR ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_AHB_OR_AXI_STAT_ADDR ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_CUR_HOST_TX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_CUR_HOST_RX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_CUR_HOST_TX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_CUR_HOST_RX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_HW_FEATURE register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_HW_FEATURE_ADDR ALT_EMAC_DMA_HW_FEATURE_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The base address byte offset for the start of the ALT_EMAC1_DMAGRP component. */ +#define ALT_EMAC1_DMAGRP_OFST 0x1000 +/* The start address of the ALT_EMAC1_DMAGRP component. */ +#define ALT_EMAC1_DMAGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC1_ADDR) + ALT_EMAC1_DMAGRP_OFST)) +/* The lower bound address range of the ALT_EMAC1_DMAGRP component. */ +#define ALT_EMAC1_DMAGRP_LB_ADDR ALT_EMAC1_DMAGRP_ADDR +/* The upper bound address range of the ALT_EMAC1_DMAGRP component. */ +#define ALT_EMAC1_DMAGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC1_DMAGRP_ADDR) + 0x5c) - 1)) + + +/* The base address byte offset for the start of the ALT_EMAC1 component. */ +#define ALT_EMAC1_OFST 0xff702000 +/* The start address of the ALT_EMAC1 component. */ +#define ALT_EMAC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_EMAC1_OFST)) +/* The lower bound address range of the ALT_EMAC1 component. */ +#define ALT_EMAC1_LB_ADDR ALT_EMAC1_ADDR +/* The upper bound address range of the ALT_EMAC1 component. */ +#define ALT_EMAC1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC1_ADDR) + 0x2000) - 1)) + + +/* + * Component Instance : sdmmc + * + * Instance sdmmc of component ALT_SDMMC. + * + * + */ +/* The address of the ALT_SDMMC_CTL register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CTL_OFST)) +/* The address of the ALT_SDMMC_PWREN register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_PWREN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_PWREN_OFST)) +/* The address of the ALT_SDMMC_CLKDIV register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CLKDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CLKDIV_OFST)) +/* The address of the ALT_SDMMC_CLKSRC register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CLKSRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CLKSRC_OFST)) +/* The address of the ALT_SDMMC_CLKENA register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CLKENA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CLKENA_OFST)) +/* The address of the ALT_SDMMC_TMOUT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_TMOUT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_TMOUT_OFST)) +/* The address of the ALT_SDMMC_CTYPE register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CTYPE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CTYPE_OFST)) +/* The address of the ALT_SDMMC_BLKSIZ register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BLKSIZ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BLKSIZ_OFST)) +/* The address of the ALT_SDMMC_BYTCNT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BYTCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BYTCNT_OFST)) +/* The address of the ALT_SDMMC_INTMSK register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_INTMSK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_INTMSK_OFST)) +/* The address of the ALT_SDMMC_CMDARG register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CMDARG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CMDARG_OFST)) +/* The address of the ALT_SDMMC_CMD register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CMD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CMD_OFST)) +/* The address of the ALT_SDMMC_RESP0 register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RESP0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP0_OFST)) +/* The address of the ALT_SDMMC_RESP1 register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RESP1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP1_OFST)) +/* The address of the ALT_SDMMC_RESP2 register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RESP2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP2_OFST)) +/* The address of the ALT_SDMMC_RESP3 register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RESP3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP3_OFST)) +/* The address of the ALT_SDMMC_MINTSTS register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_MINTSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_MINTSTS_OFST)) +/* The address of the ALT_SDMMC_RINTSTS register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RINTSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RINTSTS_OFST)) +/* The address of the ALT_SDMMC_STAT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_STAT_OFST)) +/* The address of the ALT_SDMMC_FIFOTH register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_FIFOTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_FIFOTH_OFST)) +/* The address of the ALT_SDMMC_CDETECT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CDETECT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CDETECT_OFST)) +/* The address of the ALT_SDMMC_WRTPRT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_WRTPRT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_WRTPRT_OFST)) +/* The address of the ALT_SDMMC_TCBCNT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_TCBCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_TCBCNT_OFST)) +/* The address of the ALT_SDMMC_TBBCNT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_TBBCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_TBBCNT_OFST)) +/* The address of the ALT_SDMMC_DEBNCE register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_DEBNCE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DEBNCE_OFST)) +/* The address of the ALT_SDMMC_USRID register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_USRID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_USRID_OFST)) +/* The address of the ALT_SDMMC_VERID register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_VERID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_VERID_OFST)) +/* The address of the ALT_SDMMC_HCON register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_HCON_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_HCON_OFST)) +/* The address of the ALT_SDMMC_UHS_REG register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_UHS_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_UHS_REG_OFST)) +/* The address of the ALT_SDMMC_RST_N register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RST_N_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RST_N_OFST)) +/* The address of the ALT_SDMMC_BMOD register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BMOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BMOD_OFST)) +/* The address of the ALT_SDMMC_PLDMND register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_PLDMND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_PLDMND_OFST)) +/* The address of the ALT_SDMMC_DBADDR register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_DBADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DBADDR_OFST)) +/* The address of the ALT_SDMMC_IDSTS register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_IDSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_IDSTS_OFST)) +/* The address of the ALT_SDMMC_IDINTEN register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_IDINTEN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_IDINTEN_OFST)) +/* The address of the ALT_SDMMC_DSCADDR register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_DSCADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DSCADDR_OFST)) +/* The address of the ALT_SDMMC_BUFADDR register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BUFADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BUFADDR_OFST)) +/* The address of the ALT_SDMMC_CARDTHRCTL register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CARDTHRCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CARDTHRCTL_OFST)) +/* The address of the ALT_SDMMC_BACK_END_POWER_R register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BACK_END_POWER_R_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BACK_END_POWER_R_OFST)) +/* The address of the ALT_SDMMC_DATA register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_DATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DATA_OFST)) +/* The base address byte offset for the start of the ALT_SDMMC component. */ +#define ALT_SDMMC_OFST 0xff704000 +/* The start address of the ALT_SDMMC component. */ +#define ALT_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SDMMC_OFST)) +/* The lower bound address range of the ALT_SDMMC component. */ +#define ALT_SDMMC_LB_ADDR ALT_SDMMC_ADDR +/* The upper bound address range of the ALT_SDMMC component. */ +#define ALT_SDMMC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDMMC_ADDR) + 0x400) - 1)) + + +/* + * Component Instance : qspiregs + * + * Instance qspiregs of component ALT_QSPI. + * + * + */ +/* The address of the ALT_QSPI_CFG register for the ALT_QSPI instance. */ +#define ALT_QSPI_CFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_CFG_OFST)) +/* The address of the ALT_QSPI_DEVRD register for the ALT_QSPI instance. */ +#define ALT_QSPI_DEVRD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DEVRD_OFST)) +/* The address of the ALT_QSPI_DEVWR register for the ALT_QSPI instance. */ +#define ALT_QSPI_DEVWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DEVWR_OFST)) +/* The address of the ALT_QSPI_DELAY register for the ALT_QSPI instance. */ +#define ALT_QSPI_DELAY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DELAY_OFST)) +/* The address of the ALT_QSPI_RDDATACAP register for the ALT_QSPI instance. */ +#define ALT_QSPI_RDDATACAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_RDDATACAP_OFST)) +/* The address of the ALT_QSPI_DEVSZ register for the ALT_QSPI instance. */ +#define ALT_QSPI_DEVSZ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DEVSZ_OFST)) +/* The address of the ALT_QSPI_SRAMPART register for the ALT_QSPI instance. */ +#define ALT_QSPI_SRAMPART_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_SRAMPART_OFST)) +/* The address of the ALT_QSPI_INDADDRTRIG register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDADDRTRIG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDADDRTRIG_OFST)) +/* The address of the ALT_QSPI_DMAPER register for the ALT_QSPI instance. */ +#define ALT_QSPI_DMAPER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DMAPER_OFST)) +/* The address of the ALT_QSPI_REMAPADDR register for the ALT_QSPI instance. */ +#define ALT_QSPI_REMAPADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_REMAPADDR_OFST)) +/* The address of the ALT_QSPI_MODBIT register for the ALT_QSPI instance. */ +#define ALT_QSPI_MODBIT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_MODBIT_OFST)) +/* The address of the ALT_QSPI_SRAMFILL register for the ALT_QSPI instance. */ +#define ALT_QSPI_SRAMFILL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_SRAMFILL_OFST)) +/* The address of the ALT_QSPI_TXTHRESH register for the ALT_QSPI instance. */ +#define ALT_QSPI_TXTHRESH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_TXTHRESH_OFST)) +/* The address of the ALT_QSPI_RXTHRESH register for the ALT_QSPI instance. */ +#define ALT_QSPI_RXTHRESH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_RXTHRESH_OFST)) +/* The address of the ALT_QSPI_IRQSTAT register for the ALT_QSPI instance. */ +#define ALT_QSPI_IRQSTAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_IRQSTAT_OFST)) +/* The address of the ALT_QSPI_IRQMSK register for the ALT_QSPI instance. */ +#define ALT_QSPI_IRQMSK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_IRQMSK_OFST)) +/* The address of the ALT_QSPI_LOWWRPROT register for the ALT_QSPI instance. */ +#define ALT_QSPI_LOWWRPROT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_LOWWRPROT_OFST)) +/* The address of the ALT_QSPI_UPPWRPROT register for the ALT_QSPI instance. */ +#define ALT_QSPI_UPPWRPROT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_UPPWRPROT_OFST)) +/* The address of the ALT_QSPI_WRPROT register for the ALT_QSPI instance. */ +#define ALT_QSPI_WRPROT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_WRPROT_OFST)) +/* The address of the ALT_QSPI_INDRD register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDRD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRD_OFST)) +/* The address of the ALT_QSPI_INDRDWATER register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDRDWATER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRDWATER_OFST)) +/* The address of the ALT_QSPI_INDRDSTADDR register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDRDSTADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRDSTADDR_OFST)) +/* The address of the ALT_QSPI_INDRDCNT register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDRDCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRDCNT_OFST)) +/* The address of the ALT_QSPI_INDWR register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWR_OFST)) +/* The address of the ALT_QSPI_INDWRWATER register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDWRWATER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWRWATER_OFST)) +/* The address of the ALT_QSPI_INDWRSTADDR register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDWRSTADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWRSTADDR_OFST)) +/* The address of the ALT_QSPI_INDWRCNT register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDWRCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWRCNT_OFST)) +/* The address of the ALT_QSPI_FLSHCMD register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMD_OFST)) +/* The address of the ALT_QSPI_FLSHCMDADDR register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDADDR_OFST)) +/* The address of the ALT_QSPI_FLSHCMDRDDATALO register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDRDDATALO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDRDDATALO_OFST)) +/* The address of the ALT_QSPI_FLSHCMDRDDATAUP register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDRDDATAUP_OFST)) +/* The address of the ALT_QSPI_FLSHCMDWRDATALO register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDWRDATALO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDWRDATALO_OFST)) +/* The address of the ALT_QSPI_FLSHCMDWRDATAUP register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDWRDATAUP_OFST)) +/* The address of the ALT_QSPI_MODULEID register for the ALT_QSPI instance. */ +#define ALT_QSPI_MODULEID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_MODULEID_OFST)) +/* The base address byte offset for the start of the ALT_QSPI component. */ +#define ALT_QSPI_OFST 0xff705000 +/* The start address of the ALT_QSPI component. */ +#define ALT_QSPI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_QSPI_OFST)) +/* The lower bound address range of the ALT_QSPI component. */ +#define ALT_QSPI_LB_ADDR ALT_QSPI_ADDR +/* The upper bound address range of the ALT_QSPI component. */ +#define ALT_QSPI_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_QSPI_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : fpgamgrregs + * + * Instance fpgamgrregs of component ALT_FPGAMGR. + * + * + */ +/* The address of the ALT_FPGAMGR_STAT register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_STAT_OFST)) +/* The address of the ALT_FPGAMGR_CTL register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_CTL_OFST)) +/* The address of the ALT_FPGAMGR_DCLKCNT register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_DCLKCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_DCLKCNT_OFST)) +/* The address of the ALT_FPGAMGR_DCLKSTAT register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_DCLKSTAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_DCLKSTAT_OFST)) +/* The address of the ALT_FPGAMGR_GPO register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_GPO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_GPO_OFST)) +/* The address of the ALT_FPGAMGR_GPI register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_GPI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_GPI_OFST)) +/* The address of the ALT_FPGAMGR_MISCI register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_MISCI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_MISCI_OFST)) +/* + * Register Group Instance : mon + * + * Instance mon of register group ALT_MON. + * + * + */ +/* The address of the ALT_MON_GPIO_INTEN register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INTEN_ADDR ALT_MON_GPIO_INTEN_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_INTMSK register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INTMSK_ADDR ALT_MON_GPIO_INTMSK_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_INTTYPE_LEVEL register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INTTYPE_LEVEL_ADDR ALT_MON_GPIO_INTTYPE_LEVEL_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_INT_POL register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INT_POL_ADDR ALT_MON_GPIO_INT_POL_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_INTSTAT register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INTSTAT_ADDR ALT_MON_GPIO_INTSTAT_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_RAW_INTSTAT register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_RAW_INTSTAT_ADDR ALT_MON_GPIO_RAW_INTSTAT_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_PORTA_EOI register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_PORTA_EOI_ADDR ALT_MON_GPIO_PORTA_EOI_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_EXT_PORTA register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_EXT_PORTA_ADDR ALT_MON_GPIO_EXT_PORTA_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_LS_SYNC register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_LS_SYNC_ADDR ALT_MON_GPIO_LS_SYNC_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_VER_ID_CODE register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_VER_ID_CODE_ADDR ALT_MON_GPIO_VER_ID_CODE_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_CFG_REG2 register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_CFG_REG2_ADDR ALT_MON_GPIO_CFG_REG2_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_CFG_REG1 register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_CFG_REG1_ADDR ALT_MON_GPIO_CFG_REG1_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The base address byte offset for the start of the ALT_FPGAMGR_MON component. */ +#define ALT_FPGAMGR_MON_OFST 0x800 +/* The start address of the ALT_FPGAMGR_MON component. */ +#define ALT_FPGAMGR_MON_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_MON_OFST)) +/* The lower bound address range of the ALT_FPGAMGR_MON component. */ +#define ALT_FPGAMGR_MON_LB_ADDR ALT_FPGAMGR_MON_ADDR +/* The upper bound address range of the ALT_FPGAMGR_MON component. */ +#define ALT_FPGAMGR_MON_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_FPGAMGR_MON_ADDR) + 0x80) - 1)) + + +/* The base address byte offset for the start of the ALT_FPGAMGR component. */ +#define ALT_FPGAMGR_OFST 0xff706000 +/* The start address of the ALT_FPGAMGR component. */ +#define ALT_FPGAMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_FPGAMGR_OFST)) +/* The lower bound address range of the ALT_FPGAMGR component. */ +#define ALT_FPGAMGR_LB_ADDR ALT_FPGAMGR_ADDR +/* The upper bound address range of the ALT_FPGAMGR component. */ +#define ALT_FPGAMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_FPGAMGR_ADDR) + 0x1000) - 1)) + + +/* + * Component Instance : acpidmap + * + * Instance acpidmap of component ALT_ACPIDMAP. + * + * + */ +/* The address of the ALT_ACPIDMAP_VID2RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID2RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID2WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID2WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2WR_OFST)) +/* The address of the ALT_ACPIDMAP_VID3RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID3RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID3WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID3WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3WR_OFST)) +/* The address of the ALT_ACPIDMAP_VID4RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID4RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID4WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID4WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4WR_OFST)) +/* The address of the ALT_ACPIDMAP_VID5RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID5RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID5WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID5WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5WR_OFST)) +/* The address of the ALT_ACPIDMAP_VID6RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID6RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID6WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID6WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6WR_OFST)) +/* The address of the ALT_ACPIDMAP_DYNRD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_DYNRD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNRD_OFST)) +/* The address of the ALT_ACPIDMAP_DYNWR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_DYNWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNWR_OFST)) +/* The address of the ALT_ACPIDMAP_VID2RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID2RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID2WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID2WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID3RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID3RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID3WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID3WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID4RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID4RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID4WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID4WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID5RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID5RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID5WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID5WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID6RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID6RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID6WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID6WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_DYNRD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_DYNRD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNRD_S_OFST)) +/* The address of the ALT_ACPIDMAP_DYNWR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_DYNWR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNWR_S_OFST)) +/* The base address byte offset for the start of the ALT_ACPIDMAP component. */ +#define ALT_ACPIDMAP_OFST 0xff707000 +/* The start address of the ALT_ACPIDMAP component. */ +#define ALT_ACPIDMAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_ACPIDMAP_OFST)) +/* The lower bound address range of the ALT_ACPIDMAP component. */ +#define ALT_ACPIDMAP_LB_ADDR ALT_ACPIDMAP_ADDR +/* The upper bound address range of the ALT_ACPIDMAP component. */ +#define ALT_ACPIDMAP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + 0x1000) - 1)) + + +/* + * Component Instance : gpio0 + * + * Instance gpio0 of component ALT_GPIO. + * + * + */ +/* The address of the ALT_GPIO_SWPORTA_DR register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_SWPORTA_DR_ADDR ALT_GPIO_SWPORTA_DR_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_SWPORTA_DDR register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_SWPORTA_DDR_ADDR ALT_GPIO_SWPORTA_DDR_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INTEN register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INTEN_ADDR ALT_GPIO_INTEN_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INTMSK register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INTMSK_ADDR ALT_GPIO_INTMSK_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INTTYPE_LEVEL register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INTTYPE_LEVEL_ADDR ALT_GPIO_INTTYPE_LEVEL_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INT_POL register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INT_POL_ADDR ALT_GPIO_INT_POL_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INTSTAT register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INTSTAT_ADDR ALT_GPIO_INTSTAT_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_RAW_INTSTAT register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_RAW_INTSTAT_ADDR ALT_GPIO_RAW_INTSTAT_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_DEBOUNCE register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_DEBOUNCE_ADDR ALT_GPIO_DEBOUNCE_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_PORTA_EOI register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_PORTA_EOI_ADDR ALT_GPIO_PORTA_EOI_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_EXT_PORTA register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_EXT_PORTA_ADDR ALT_GPIO_EXT_PORTA_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_LS_SYNC register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_LS_SYNC_ADDR ALT_GPIO_LS_SYNC_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_ID_CODE register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_ID_CODE_ADDR ALT_GPIO_ID_CODE_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_VER_ID_CODE register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_VER_ID_CODE_ADDR ALT_GPIO_VER_ID_CODE_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_CFG_REG2 register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_CFG_REG2_ADDR ALT_GPIO_CFG_REG2_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_CFG_REG1 register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_CFG_REG1_ADDR ALT_GPIO_CFG_REG1_ADDR(ALT_GPIO0_ADDR) +/* The base address byte offset for the start of the ALT_GPIO0 component. */ +#define ALT_GPIO0_OFST 0xff708000 +/* The start address of the ALT_GPIO0 component. */ +#define ALT_GPIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_GPIO0_OFST)) +/* The lower bound address range of the ALT_GPIO0 component. */ +#define ALT_GPIO0_LB_ADDR ALT_GPIO0_ADDR +/* The upper bound address range of the ALT_GPIO0 component. */ +#define ALT_GPIO0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_GPIO0_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : gpio1 + * + * Instance gpio1 of component ALT_GPIO. + * + * + */ +/* The address of the ALT_GPIO_SWPORTA_DR register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_SWPORTA_DR_ADDR ALT_GPIO_SWPORTA_DR_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_SWPORTA_DDR register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_SWPORTA_DDR_ADDR ALT_GPIO_SWPORTA_DDR_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INTEN register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INTEN_ADDR ALT_GPIO_INTEN_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INTMSK register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INTMSK_ADDR ALT_GPIO_INTMSK_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INTTYPE_LEVEL register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INTTYPE_LEVEL_ADDR ALT_GPIO_INTTYPE_LEVEL_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INT_POL register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INT_POL_ADDR ALT_GPIO_INT_POL_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INTSTAT register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INTSTAT_ADDR ALT_GPIO_INTSTAT_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_RAW_INTSTAT register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_RAW_INTSTAT_ADDR ALT_GPIO_RAW_INTSTAT_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_DEBOUNCE register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_DEBOUNCE_ADDR ALT_GPIO_DEBOUNCE_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_PORTA_EOI register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_PORTA_EOI_ADDR ALT_GPIO_PORTA_EOI_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_EXT_PORTA register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_EXT_PORTA_ADDR ALT_GPIO_EXT_PORTA_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_LS_SYNC register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_LS_SYNC_ADDR ALT_GPIO_LS_SYNC_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_ID_CODE register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_ID_CODE_ADDR ALT_GPIO_ID_CODE_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_VER_ID_CODE register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_VER_ID_CODE_ADDR ALT_GPIO_VER_ID_CODE_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_CFG_REG2 register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_CFG_REG2_ADDR ALT_GPIO_CFG_REG2_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_CFG_REG1 register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_CFG_REG1_ADDR ALT_GPIO_CFG_REG1_ADDR(ALT_GPIO1_ADDR) +/* The base address byte offset for the start of the ALT_GPIO1 component. */ +#define ALT_GPIO1_OFST 0xff709000 +/* The start address of the ALT_GPIO1 component. */ +#define ALT_GPIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_GPIO1_OFST)) +/* The lower bound address range of the ALT_GPIO1 component. */ +#define ALT_GPIO1_LB_ADDR ALT_GPIO1_ADDR +/* The upper bound address range of the ALT_GPIO1 component. */ +#define ALT_GPIO1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_GPIO1_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : gpio2 + * + * Instance gpio2 of component ALT_GPIO. + * + * + */ +/* The address of the ALT_GPIO_SWPORTA_DR register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_SWPORTA_DR_ADDR ALT_GPIO_SWPORTA_DR_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_SWPORTA_DDR register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_SWPORTA_DDR_ADDR ALT_GPIO_SWPORTA_DDR_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INTEN register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INTEN_ADDR ALT_GPIO_INTEN_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INTMSK register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INTMSK_ADDR ALT_GPIO_INTMSK_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INTTYPE_LEVEL register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INTTYPE_LEVEL_ADDR ALT_GPIO_INTTYPE_LEVEL_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INT_POL register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INT_POL_ADDR ALT_GPIO_INT_POL_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INTSTAT register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INTSTAT_ADDR ALT_GPIO_INTSTAT_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_RAW_INTSTAT register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_RAW_INTSTAT_ADDR ALT_GPIO_RAW_INTSTAT_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_DEBOUNCE register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_DEBOUNCE_ADDR ALT_GPIO_DEBOUNCE_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_PORTA_EOI register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_PORTA_EOI_ADDR ALT_GPIO_PORTA_EOI_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_EXT_PORTA register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_EXT_PORTA_ADDR ALT_GPIO_EXT_PORTA_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_LS_SYNC register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_LS_SYNC_ADDR ALT_GPIO_LS_SYNC_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_ID_CODE register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_ID_CODE_ADDR ALT_GPIO_ID_CODE_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_VER_ID_CODE register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_VER_ID_CODE_ADDR ALT_GPIO_VER_ID_CODE_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_CFG_REG2 register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_CFG_REG2_ADDR ALT_GPIO_CFG_REG2_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_CFG_REG1 register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_CFG_REG1_ADDR ALT_GPIO_CFG_REG1_ADDR(ALT_GPIO2_ADDR) +/* The base address byte offset for the start of the ALT_GPIO2 component. */ +#define ALT_GPIO2_OFST 0xff70a000 +/* The start address of the ALT_GPIO2 component. */ +#define ALT_GPIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_GPIO2_OFST)) +/* The lower bound address range of the ALT_GPIO2 component. */ +#define ALT_GPIO2_LB_ADDR ALT_GPIO2_ADDR +/* The upper bound address range of the ALT_GPIO2 component. */ +#define ALT_GPIO2_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_GPIO2_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : l3regs + * + * Instance l3regs of component ALT_L3. + * + * + */ +/* The address of the ALT_L3_REMAP register for the ALT_L3 instance. */ +#define ALT_L3_REMAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_REMAP_OFST)) +/* + * Register Group Instance : secgrp + * + * Instance secgrp of register group ALT_L3_SECGRP. + * + * + */ +/* The address of the ALT_L3_SEC_L4MAIN register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4MAIN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4MAIN_OFST)) +/* The address of the ALT_L3_SEC_L4SP register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4SP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4SP_OFST)) +/* The address of the ALT_L3_SEC_L4MP register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4MP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4MP_OFST)) +/* The address of the ALT_L3_SEC_L4OSC1 register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4OSC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4OSC1_OFST)) +/* The address of the ALT_L3_SEC_L4SPIM register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4SPIM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4SPIM_OFST)) +/* The address of the ALT_L3_SEC_STM register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_STM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_STM_OFST)) +/* The address of the ALT_L3_SEC_LWH2F register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_LWH2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_LWH2F_OFST)) +/* The address of the ALT_L3_SEC_USB1 register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_USB1_OFST)) +/* The address of the ALT_L3_SEC_NANDDATA register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_NANDDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_NANDDATA_OFST)) +/* The address of the ALT_L3_SEC_USB0 register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_USB0_OFST)) +/* The address of the ALT_L3_SEC_NAND register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_NAND_OFST)) +/* The address of the ALT_L3_SEC_QSPIDATA register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_QSPIDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_QSPIDATA_OFST)) +/* The address of the ALT_L3_SEC_FPGAMGRDATA register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_FPGAMGRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_FPGAMGRDATA_OFST)) +/* The address of the ALT_L3_SEC_H2F register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_H2F_OFST)) +/* The address of the ALT_L3_SEC_ACP register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_ACP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_ACP_OFST)) +/* The address of the ALT_L3_SEC_ROM register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_ROM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_ROM_OFST)) +/* The address of the ALT_L3_SEC_OCRAM register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_OCRAM_OFST)) +/* The address of the ALT_L3_SEC_SDRDATA register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_SDRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_SDRDATA_OFST)) +/* The base address byte offset for the start of the ALT_L3_SECGRP component. */ +#define ALT_L3_SECGRP_OFST 0x8 +/* The start address of the ALT_L3_SECGRP component. */ +#define ALT_L3_SECGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_SECGRP_OFST)) +/* The lower bound address range of the ALT_L3_SECGRP component. */ +#define ALT_L3_SECGRP_LB_ADDR ALT_L3_SECGRP_ADDR +/* The upper bound address range of the ALT_L3_SECGRP component. */ +#define ALT_L3_SECGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + 0x9c) - 1)) + + +/* + * Register Group Instance : idgrp + * + * Instance idgrp of register group ALT_L3_IDGRP. + * + * + */ +/* The address of the ALT_L3_ID_PERIPH_ID_4 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_4_OFST)) +/* The address of the ALT_L3_ID_PERIPH_ID_0 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_0_OFST)) +/* The address of the ALT_L3_ID_PERIPH_ID_1 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_1_OFST)) +/* The address of the ALT_L3_ID_PERIPH_ID_2 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_2_OFST)) +/* The address of the ALT_L3_ID_PERIPH_ID_3 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_3_OFST)) +/* The address of the ALT_L3_ID_COMP_ID_0 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_0_OFST)) +/* The address of the ALT_L3_ID_COMP_ID_1 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_1_OFST)) +/* The address of the ALT_L3_ID_COMP_ID_2 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_2_OFST)) +/* The address of the ALT_L3_ID_COMP_ID_3 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_3_OFST)) +/* The base address byte offset for the start of the ALT_L3_IDGRP component. */ +#define ALT_L3_IDGRP_OFST 0x1000 +/* The start address of the ALT_L3_IDGRP component. */ +#define ALT_L3_IDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_IDGRP_OFST)) +/* The lower bound address range of the ALT_L3_IDGRP component. */ +#define ALT_L3_IDGRP_LB_ADDR ALT_L3_IDGRP_ADDR +/* The upper bound address range of the ALT_L3_IDGRP component. */ +#define ALT_L3_IDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + 0x1000) - 1)) + + +/* + * Register Group Instance : mastergrp + * + * Instance mastergrp of register group ALT_L3_MSTGRP. + * + * + */ +/* + * Register Group Instance : mastergrp_l4main + * + * Instance mastergrp_l4main of register group ALT_L3_MST_L4MAIN. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4MAIN instance. */ +#define ALT_L3_MST_MST_L4MAIN_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4MAIN_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4MAIN component. */ +#define ALT_L3_MST_MST_L4MAIN_OFST 0x0 +/* The start address of the ALT_L3_MST_MST_L4MAIN component. */ +#define ALT_L3_MST_MST_L4MAIN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4MAIN_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4MAIN component. */ +#define ALT_L3_MST_MST_L4MAIN_LB_ADDR ALT_L3_MST_MST_L4MAIN_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4MAIN component. */ +#define ALT_L3_MST_MST_L4MAIN_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4MAIN_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_l4sp + * + * Instance mastergrp_l4sp of register group ALT_L3_MST_L4SP. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4SP instance. */ +#define ALT_L3_MST_MST_L4SP_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4SP_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4SP component. */ +#define ALT_L3_MST_MST_L4SP_OFST 0x1000 +/* The start address of the ALT_L3_MST_MST_L4SP component. */ +#define ALT_L3_MST_MST_L4SP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4SP_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4SP component. */ +#define ALT_L3_MST_MST_L4SP_LB_ADDR ALT_L3_MST_MST_L4SP_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4SP component. */ +#define ALT_L3_MST_MST_L4SP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4SP_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_l4mp + * + * Instance mastergrp_l4mp of register group ALT_L3_MST_L4MP. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4MP instance. */ +#define ALT_L3_MST_MST_L4MP_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4MP_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4MP component. */ +#define ALT_L3_MST_MST_L4MP_OFST 0x2000 +/* The start address of the ALT_L3_MST_MST_L4MP component. */ +#define ALT_L3_MST_MST_L4MP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4MP_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4MP component. */ +#define ALT_L3_MST_MST_L4MP_LB_ADDR ALT_L3_MST_MST_L4MP_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4MP component. */ +#define ALT_L3_MST_MST_L4MP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4MP_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_l4osc1 + * + * Instance mastergrp_l4osc1 of register group ALT_L3_MST_L4OSC1. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4OSC1 instance. */ +#define ALT_L3_MST_MST_L4OSC1_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4OSC1_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4OSC1 component. */ +#define ALT_L3_MST_MST_L4OSC1_OFST 0x3000 +/* The start address of the ALT_L3_MST_MST_L4OSC1 component. */ +#define ALT_L3_MST_MST_L4OSC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4OSC1_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4OSC1 component. */ +#define ALT_L3_MST_MST_L4OSC1_LB_ADDR ALT_L3_MST_MST_L4OSC1_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4OSC1 component. */ +#define ALT_L3_MST_MST_L4OSC1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4OSC1_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_l4spim + * + * Instance mastergrp_l4spim of register group ALT_L3_MST_L4SPIM. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4SPIM instance. */ +#define ALT_L3_MST_MST_L4SPIM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4SPIM_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4SPIM component. */ +#define ALT_L3_MST_MST_L4SPIM_OFST 0x4000 +/* The start address of the ALT_L3_MST_MST_L4SPIM component. */ +#define ALT_L3_MST_MST_L4SPIM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4SPIM_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4SPIM component. */ +#define ALT_L3_MST_MST_L4SPIM_LB_ADDR ALT_L3_MST_MST_L4SPIM_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4SPIM component. */ +#define ALT_L3_MST_MST_L4SPIM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4SPIM_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_stm + * + * Instance mastergrp_stm of register group ALT_L3_MST_STM. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_STM instance. */ +#define ALT_L3_MST_MST_STM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_STM_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_STM instance. */ +#define ALT_L3_MST_MST_STM_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_STM_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_STM component. */ +#define ALT_L3_MST_MST_STM_OFST 0x5000 +/* The start address of the ALT_L3_MST_MST_STM component. */ +#define ALT_L3_MST_MST_STM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_STM_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_STM component. */ +#define ALT_L3_MST_MST_STM_LB_ADDR ALT_L3_MST_MST_STM_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_STM component. */ +#define ALT_L3_MST_MST_STM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_STM_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_lwhps2fpga + * + * Instance mastergrp_lwhps2fpga of register group ALT_L3_MST_LWH2F. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_LWH2F instance. */ +#define ALT_L3_MST_MST_LWH2F_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_LWH2F_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_LWH2F instance. */ +#define ALT_L3_MST_MST_LWH2F_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_LWH2F_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_LWH2F component. */ +#define ALT_L3_MST_MST_LWH2F_OFST 0x6000 +/* The start address of the ALT_L3_MST_MST_LWH2F component. */ +#define ALT_L3_MST_MST_LWH2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_LWH2F_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_LWH2F component. */ +#define ALT_L3_MST_MST_LWH2F_LB_ADDR ALT_L3_MST_MST_LWH2F_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_LWH2F component. */ +#define ALT_L3_MST_MST_LWH2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_LWH2F_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_usb1 + * + * Instance mastergrp_usb1 of register group ALT_L3_MST_USB1. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_USB1 instance. */ +#define ALT_L3_MST_MST_USB1_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_USB1_ADDR) +/* The address of the ALT_L3_AHB_CNTL register for the ALT_L3_MST_MST_USB1 instance. */ +#define ALT_L3_MST_MST_USB1_AHB_CNTL_ADDR ALT_L3_AHB_CNTL_ADDR(ALT_L3_MST_MST_USB1_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_USB1 component. */ +#define ALT_L3_MST_MST_USB1_OFST 0x8000 +/* The start address of the ALT_L3_MST_MST_USB1 component. */ +#define ALT_L3_MST_MST_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_USB1_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_USB1 component. */ +#define ALT_L3_MST_MST_USB1_LB_ADDR ALT_L3_MST_MST_USB1_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_USB1 component. */ +#define ALT_L3_MST_MST_USB1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_USB1_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_nanddata + * + * Instance mastergrp_nanddata of register group ALT_L3_MST_NANDDATA. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_NANDDATA instance. */ +#define ALT_L3_MST_MST_NANDDATA_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_NANDDATA_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_NANDDATA instance. */ +#define ALT_L3_MST_MST_NANDDATA_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_NANDDATA_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_NANDDATA component. */ +#define ALT_L3_MST_MST_NANDDATA_OFST 0x9000 +/* The start address of the ALT_L3_MST_MST_NANDDATA component. */ +#define ALT_L3_MST_MST_NANDDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_NANDDATA_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_NANDDATA component. */ +#define ALT_L3_MST_MST_NANDDATA_LB_ADDR ALT_L3_MST_MST_NANDDATA_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_NANDDATA component. */ +#define ALT_L3_MST_MST_NANDDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_NANDDATA_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_usb0 + * + * Instance mastergrp_usb0 of register group ALT_L3_MST_USB0. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_USB0 instance. */ +#define ALT_L3_MST_MST_USB0_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_USB0_ADDR) +/* The address of the ALT_L3_AHB_CNTL register for the ALT_L3_MST_MST_USB0 instance. */ +#define ALT_L3_MST_MST_USB0_AHB_CNTL_ADDR ALT_L3_AHB_CNTL_ADDR(ALT_L3_MST_MST_USB0_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_USB0 component. */ +#define ALT_L3_MST_MST_USB0_OFST 0x1e000 +/* The start address of the ALT_L3_MST_MST_USB0 component. */ +#define ALT_L3_MST_MST_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_USB0_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_USB0 component. */ +#define ALT_L3_MST_MST_USB0_LB_ADDR ALT_L3_MST_MST_USB0_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_USB0 component. */ +#define ALT_L3_MST_MST_USB0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_USB0_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_nandregs + * + * Instance mastergrp_nandregs of register group ALT_L3_MST_NAND. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_NAND instance. */ +#define ALT_L3_MST_MST_NAND_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_NAND_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_NAND instance. */ +#define ALT_L3_MST_MST_NAND_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_NAND_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_NAND component. */ +#define ALT_L3_MST_MST_NAND_OFST 0x1f000 +/* The start address of the ALT_L3_MST_MST_NAND component. */ +#define ALT_L3_MST_MST_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_NAND_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_NAND component. */ +#define ALT_L3_MST_MST_NAND_LB_ADDR ALT_L3_MST_MST_NAND_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_NAND component. */ +#define ALT_L3_MST_MST_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_NAND_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_qspidata + * + * Instance mastergrp_qspidata of register group ALT_L3_MST_QSPIDATA. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_QSPIDATA instance. */ +#define ALT_L3_MST_MST_QSPIDATA_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_QSPIDATA_ADDR) +/* The address of the ALT_L3_AHB_CNTL register for the ALT_L3_MST_MST_QSPIDATA instance. */ +#define ALT_L3_MST_MST_QSPIDATA_AHB_CNTL_ADDR ALT_L3_AHB_CNTL_ADDR(ALT_L3_MST_MST_QSPIDATA_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_QSPIDATA component. */ +#define ALT_L3_MST_MST_QSPIDATA_OFST 0x20000 +/* The start address of the ALT_L3_MST_MST_QSPIDATA component. */ +#define ALT_L3_MST_MST_QSPIDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_QSPIDATA_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_QSPIDATA component. */ +#define ALT_L3_MST_MST_QSPIDATA_LB_ADDR ALT_L3_MST_MST_QSPIDATA_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_QSPIDATA component. */ +#define ALT_L3_MST_MST_QSPIDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_QSPIDATA_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_fpgamgrdata + * + * Instance mastergrp_fpgamgrdata of register group ALT_L3_MST_FPGAMGRDATA. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_FPGAMGRDATA instance. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_FPGAMGRDATA_ADDR) +/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_MST_MST_FPGAMGRDATA instance. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_MST_MST_FPGAMGRDATA_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_FPGAMGRDATA instance. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_FPGAMGRDATA_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_FPGAMGRDATA component. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_OFST 0x21000 +/* The start address of the ALT_L3_MST_MST_FPGAMGRDATA component. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_FPGAMGRDATA_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_FPGAMGRDATA component. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_LB_ADDR ALT_L3_MST_MST_FPGAMGRDATA_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_FPGAMGRDATA component. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_FPGAMGRDATA_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_hps2fpga + * + * Instance mastergrp_hps2fpga of register group ALT_L3_MST_H2F. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_H2F instance. */ +#define ALT_L3_MST_MST_H2F_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_H2F_ADDR) +/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_MST_MST_H2F instance. */ +#define ALT_L3_MST_MST_H2F_WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_MST_MST_H2F_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_H2F instance. */ +#define ALT_L3_MST_MST_H2F_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_H2F_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_H2F component. */ +#define ALT_L3_MST_MST_H2F_OFST 0x22000 +/* The start address of the ALT_L3_MST_MST_H2F component. */ +#define ALT_L3_MST_MST_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_H2F_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_H2F component. */ +#define ALT_L3_MST_MST_H2F_LB_ADDR ALT_L3_MST_MST_H2F_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_H2F component. */ +#define ALT_L3_MST_MST_H2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_H2F_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_acp + * + * Instance mastergrp_acp of register group ALT_L3_MST_ACP. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_ACP instance. */ +#define ALT_L3_MST_MST_ACP_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_ACP_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_ACP instance. */ +#define ALT_L3_MST_MST_ACP_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_ACP_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_ACP component. */ +#define ALT_L3_MST_MST_ACP_OFST 0x23000 +/* The start address of the ALT_L3_MST_MST_ACP component. */ +#define ALT_L3_MST_MST_ACP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_ACP_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_ACP component. */ +#define ALT_L3_MST_MST_ACP_LB_ADDR ALT_L3_MST_MST_ACP_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_ACP component. */ +#define ALT_L3_MST_MST_ACP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_ACP_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_rom + * + * Instance mastergrp_rom of register group ALT_L3_MST_ROM. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_ROM instance. */ +#define ALT_L3_MST_MST_ROM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_ROM_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_ROM instance. */ +#define ALT_L3_MST_MST_ROM_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_ROM_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_ROM component. */ +#define ALT_L3_MST_MST_ROM_OFST 0x24000 +/* The start address of the ALT_L3_MST_MST_ROM component. */ +#define ALT_L3_MST_MST_ROM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_ROM_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_ROM component. */ +#define ALT_L3_MST_MST_ROM_LB_ADDR ALT_L3_MST_MST_ROM_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_ROM component. */ +#define ALT_L3_MST_MST_ROM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_ROM_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_ocram + * + * Instance mastergrp_ocram of register group ALT_L3_MST_OCRAM. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_OCRAM instance. */ +#define ALT_L3_MST_MST_OCRAM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_OCRAM_ADDR) +/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_MST_MST_OCRAM instance. */ +#define ALT_L3_MST_MST_OCRAM_WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_MST_MST_OCRAM_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_OCRAM instance. */ +#define ALT_L3_MST_MST_OCRAM_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_OCRAM_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_OCRAM component. */ +#define ALT_L3_MST_MST_OCRAM_OFST 0x25000 +/* The start address of the ALT_L3_MST_MST_OCRAM component. */ +#define ALT_L3_MST_MST_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_OCRAM_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_OCRAM component. */ +#define ALT_L3_MST_MST_OCRAM_LB_ADDR ALT_L3_MST_MST_OCRAM_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_OCRAM component. */ +#define ALT_L3_MST_MST_OCRAM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_OCRAM_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_L3_MSTGRP component. */ +#define ALT_L3_MSTGRP_OFST 0x2000 +/* The start address of the ALT_L3_MSTGRP component. */ +#define ALT_L3_MSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_MSTGRP_OFST)) +/* The lower bound address range of the ALT_L3_MSTGRP component. */ +#define ALT_L3_MSTGRP_LB_ADDR ALT_L3_MSTGRP_ADDR +/* The upper bound address range of the ALT_L3_MSTGRP component. */ +#define ALT_L3_MSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + 0x2510c) - 1)) + + +/* + * Register Group Instance : slavegrp + * + * Instance slavegrp of register group ALT_L3_SLVGRP. + * + * + */ +/* + * Register Group Instance : slavegrp_dap + * + * Instance slavegrp_dap of register group ALT_L3_SLV_DAP. + * + * + */ +/* The address of the ALT_L3_FN_MOD2 register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_FN_MOD2_ADDR ALT_L3_FN_MOD2_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_DAP component. */ +#define ALT_L3_SLV_SLV_DAP_OFST 0x0 +/* The start address of the ALT_L3_SLV_SLV_DAP component. */ +#define ALT_L3_SLV_SLV_DAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_DAP_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_DAP component. */ +#define ALT_L3_SLV_SLV_DAP_LB_ADDR ALT_L3_SLV_SLV_DAP_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_DAP component. */ +#define ALT_L3_SLV_SLV_DAP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_DAP_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_mpu + * + * Instance slavegrp_mpu of register group ALT_L3_SLV_MPU. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_MPU instance. */ +#define ALT_L3_SLV_SLV_MPU_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_MPU_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_MPU instance. */ +#define ALT_L3_SLV_SLV_MPU_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_MPU_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_MPU instance. */ +#define ALT_L3_SLV_SLV_MPU_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_MPU_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_MPU component. */ +#define ALT_L3_SLV_SLV_MPU_OFST 0x1000 +/* The start address of the ALT_L3_SLV_SLV_MPU component. */ +#define ALT_L3_SLV_SLV_MPU_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_MPU_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_MPU component. */ +#define ALT_L3_SLV_SLV_MPU_LB_ADDR ALT_L3_SLV_SLV_MPU_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_MPU component. */ +#define ALT_L3_SLV_SLV_MPU_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_MPU_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_sdmmc + * + * Instance slavegrp_sdmmc of register group ALT_L3_SLV_SDMMC. + * + * + */ +/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_SDMMC instance. */ +#define ALT_L3_SLV_SLV_SDMMC_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_SDMMC instance. */ +#define ALT_L3_SLV_SLV_SDMMC_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_SDMMC instance. */ +#define ALT_L3_SLV_SLV_SDMMC_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_SDMMC instance. */ +#define ALT_L3_SLV_SLV_SDMMC_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_SDMMC component. */ +#define ALT_L3_SLV_SLV_SDMMC_OFST 0x2000 +/* The start address of the ALT_L3_SLV_SLV_SDMMC component. */ +#define ALT_L3_SLV_SLV_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_SDMMC_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_SDMMC component. */ +#define ALT_L3_SLV_SLV_SDMMC_LB_ADDR ALT_L3_SLV_SLV_SDMMC_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_SDMMC component. */ +#define ALT_L3_SLV_SLV_SDMMC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_SDMMC_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_dma + * + * Instance slavegrp_dma of register group ALT_L3_SLV_DMA. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_DMA instance. */ +#define ALT_L3_SLV_SLV_DMA_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_DMA_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_DMA instance. */ +#define ALT_L3_SLV_SLV_DMA_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_DMA_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_DMA instance. */ +#define ALT_L3_SLV_SLV_DMA_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_DMA_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_DMA component. */ +#define ALT_L3_SLV_SLV_DMA_OFST 0x3000 +/* The start address of the ALT_L3_SLV_SLV_DMA component. */ +#define ALT_L3_SLV_SLV_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_DMA_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_DMA component. */ +#define ALT_L3_SLV_SLV_DMA_LB_ADDR ALT_L3_SLV_SLV_DMA_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_DMA component. */ +#define ALT_L3_SLV_SLV_DMA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_DMA_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_fpga2hps + * + * Instance slavegrp_fpga2hps of register group ALT_L3_SLV_F2H. + * + * + */ +/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_SLV_SLV_F2H instance. */ +#define ALT_L3_SLV_SLV_FPGA2WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_F2H instance. */ +#define ALT_L3_SLV_SLV_FPGA2RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_F2H instance. */ +#define ALT_L3_SLV_SLV_FPGA2WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_F2H instance. */ +#define ALT_L3_SLV_SLV_FPGA2FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_F2H component. */ +#define ALT_L3_SLV_SLV_F2H_OFST 0x4000 +/* The start address of the ALT_L3_SLV_SLV_F2H component. */ +#define ALT_L3_SLV_SLV_F2H_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_F2H_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_F2H component. */ +#define ALT_L3_SLV_SLV_F2H_LB_ADDR ALT_L3_SLV_SLV_F2H_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_F2H component. */ +#define ALT_L3_SLV_SLV_F2H_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_F2H_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_etr + * + * Instance slavegrp_etr of register group ALT_L3_SLV_ETR. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_ETR instance. */ +#define ALT_L3_SLV_SLV_ETR_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_ETR_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_ETR instance. */ +#define ALT_L3_SLV_SLV_ETR_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_ETR_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_ETR instance. */ +#define ALT_L3_SLV_SLV_ETR_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_ETR_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_ETR component. */ +#define ALT_L3_SLV_SLV_ETR_OFST 0x5000 +/* The start address of the ALT_L3_SLV_SLV_ETR component. */ +#define ALT_L3_SLV_SLV_ETR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_ETR_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_ETR component. */ +#define ALT_L3_SLV_SLV_ETR_LB_ADDR ALT_L3_SLV_SLV_ETR_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_ETR component. */ +#define ALT_L3_SLV_SLV_ETR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_ETR_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_emac0 + * + * Instance slavegrp_emac0 of register group ALT_L3_SLV_EMAC0. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_EMAC0 instance. */ +#define ALT_L3_SLV_SLV_EMAC0_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_EMAC0_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_EMAC0 instance. */ +#define ALT_L3_SLV_SLV_EMAC0_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_EMAC0_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_EMAC0 instance. */ +#define ALT_L3_SLV_SLV_EMAC0_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_EMAC0_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_EMAC0 component. */ +#define ALT_L3_SLV_SLV_EMAC0_OFST 0x6000 +/* The start address of the ALT_L3_SLV_SLV_EMAC0 component. */ +#define ALT_L3_SLV_SLV_EMAC0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_EMAC0_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_EMAC0 component. */ +#define ALT_L3_SLV_SLV_EMAC0_LB_ADDR ALT_L3_SLV_SLV_EMAC0_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_EMAC0 component. */ +#define ALT_L3_SLV_SLV_EMAC0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_EMAC0_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_emac1 + * + * Instance slavegrp_emac1 of register group ALT_L3_SLV_EMAC1. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_EMAC1 instance. */ +#define ALT_L3_SLV_SLV_EMAC1_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_EMAC1_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_EMAC1 instance. */ +#define ALT_L3_SLV_SLV_EMAC1_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_EMAC1_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_EMAC1 instance. */ +#define ALT_L3_SLV_SLV_EMAC1_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_EMAC1_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_EMAC1 component. */ +#define ALT_L3_SLV_SLV_EMAC1_OFST 0x7000 +/* The start address of the ALT_L3_SLV_SLV_EMAC1 component. */ +#define ALT_L3_SLV_SLV_EMAC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_EMAC1_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_EMAC1 component. */ +#define ALT_L3_SLV_SLV_EMAC1_LB_ADDR ALT_L3_SLV_SLV_EMAC1_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_EMAC1 component. */ +#define ALT_L3_SLV_SLV_EMAC1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_EMAC1_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_usb0 + * + * Instance slavegrp_usb0 of register group ALT_L3_SLV_USB0. + * + * + */ +/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_USB0 instance. */ +#define ALT_L3_SLV_SLV_USB0_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_USB0 instance. */ +#define ALT_L3_SLV_SLV_USB0_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_USB0 instance. */ +#define ALT_L3_SLV_SLV_USB0_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_USB0 instance. */ +#define ALT_L3_SLV_SLV_USB0_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_USB0 component. */ +#define ALT_L3_SLV_SLV_USB0_OFST 0x8000 +/* The start address of the ALT_L3_SLV_SLV_USB0 component. */ +#define ALT_L3_SLV_SLV_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_USB0_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_USB0 component. */ +#define ALT_L3_SLV_SLV_USB0_LB_ADDR ALT_L3_SLV_SLV_USB0_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_USB0 component. */ +#define ALT_L3_SLV_SLV_USB0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_USB0_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_nand + * + * Instance slavegrp_nand of register group ALT_L3_SLV_NAND. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_NAND instance. */ +#define ALT_L3_SLV_SLV_NAND_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_NAND_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_NAND instance. */ +#define ALT_L3_SLV_SLV_NAND_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_NAND_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_NAND instance. */ +#define ALT_L3_SLV_SLV_NAND_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_NAND_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_NAND component. */ +#define ALT_L3_SLV_SLV_NAND_OFST 0x9000 +/* The start address of the ALT_L3_SLV_SLV_NAND component. */ +#define ALT_L3_SLV_SLV_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_NAND_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_NAND component. */ +#define ALT_L3_SLV_SLV_NAND_LB_ADDR ALT_L3_SLV_SLV_NAND_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_NAND component. */ +#define ALT_L3_SLV_SLV_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_NAND_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_usb1 + * + * Instance slavegrp_usb1 of register group ALT_L3_SLV_USB1. + * + * + */ +/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_USB1 instance. */ +#define ALT_L3_SLV_SLV_USB1_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_USB1 instance. */ +#define ALT_L3_SLV_SLV_USB1_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_USB1 instance. */ +#define ALT_L3_SLV_SLV_USB1_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_USB1 instance. */ +#define ALT_L3_SLV_SLV_USB1_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_USB1 component. */ +#define ALT_L3_SLV_SLV_USB1_OFST 0xa000 +/* The start address of the ALT_L3_SLV_SLV_USB1 component. */ +#define ALT_L3_SLV_SLV_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_USB1_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_USB1 component. */ +#define ALT_L3_SLV_SLV_USB1_LB_ADDR ALT_L3_SLV_SLV_USB1_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_USB1 component. */ +#define ALT_L3_SLV_SLV_USB1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_USB1_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_L3_SLVGRP component. */ +#define ALT_L3_SLVGRP_OFST 0x42000 +/* The start address of the ALT_L3_SLVGRP component. */ +#define ALT_L3_SLVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_SLVGRP_OFST)) +/* The lower bound address range of the ALT_L3_SLVGRP component. */ +#define ALT_L3_SLVGRP_LB_ADDR ALT_L3_SLVGRP_ADDR +/* The upper bound address range of the ALT_L3_SLVGRP component. */ +#define ALT_L3_SLVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + 0xa10c) - 1)) + + +/* The base address byte offset for the start of the ALT_L3 component. */ +#define ALT_L3_OFST 0xff800000 +/* The start address of the ALT_L3 component. */ +#define ALT_L3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_L3_OFST)) +/* The lower bound address range of the ALT_L3 component. */ +#define ALT_L3_LB_ADDR ALT_L3_ADDR +/* The upper bound address range of the ALT_L3 component. */ +#define ALT_L3_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_ADDR) + 0x80000) - 1)) + + +/* + * Component Instance : nanddata + * + * Instance nanddata of component ALT_NANDDATA. + * + * + */ +/* The base address byte offset for the start of the ALT_NANDDATA component. */ +#define ALT_NANDDATA_OFST 0xff900000 +/* The start address of the ALT_NANDDATA component. */ +#define ALT_NANDDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_NANDDATA_OFST)) +/* The lower bound address range of the ALT_NANDDATA component. */ +#define ALT_NANDDATA_LB_ADDR ALT_NANDDATA_ADDR +/* The upper bound address range of the ALT_NANDDATA component. */ +#define ALT_NANDDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NANDDATA_ADDR) + 0x100000) - 1)) + + +/* + * Component Instance : qspidata + * + * Instance qspidata of component ALT_QSPIDATA. + * + * + */ +/* The base address byte offset for the start of the ALT_QSPIDATA component. */ +#define ALT_QSPIDATA_OFST 0xffa00000 +/* The start address of the ALT_QSPIDATA component. */ +#define ALT_QSPIDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_QSPIDATA_OFST)) +/* The lower bound address range of the ALT_QSPIDATA component. */ +#define ALT_QSPIDATA_LB_ADDR ALT_QSPIDATA_ADDR +/* The upper bound address range of the ALT_QSPIDATA component. */ +#define ALT_QSPIDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_QSPIDATA_ADDR) + 0x100000) - 1)) + + +/* + * Component Instance : usb0 + * + * Instance usb0 of component ALT_USB. + * + * + */ +/* + * Register Group Instance : globgrp + * + * Instance globgrp of register group ALT_USB_GLOB. + * + * + */ +/* The address of the ALT_USB_GLOB_GOTGCTL register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GOTGCTL_ADDR ALT_USB_GLOB_GOTGCTL_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GOTGINT register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GOTGINT_ADDR ALT_USB_GLOB_GOTGINT_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GAHBCFG register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GAHBCFG_ADDR ALT_USB_GLOB_GAHBCFG_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GUSBCFG register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GUSBCFG_ADDR ALT_USB_GLOB_GUSBCFG_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRSTCTL register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GRSTCTL_ADDR ALT_USB_GLOB_GRSTCTL_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GINTSTS register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GINTSTS_ADDR ALT_USB_GLOB_GINTSTS_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GINTMSK register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GINTMSK_ADDR ALT_USB_GLOB_GINTMSK_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXSTSR register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GRXSTSR_ADDR ALT_USB_GLOB_GRXSTSR_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXSTSP register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GRXSTSP_ADDR ALT_USB_GLOB_GRXSTSP_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXFSIZ register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GRXFSIZ_ADDR ALT_USB_GLOB_GRXFSIZ_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GNPTXFSIZ register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GNPTXFSIZ_ADDR ALT_USB_GLOB_GNPTXFSIZ_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GNPTXSTS register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GNPTXSTS_ADDR ALT_USB_GLOB_GNPTXSTS_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GPVNDCTL register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GPVNDCTL_ADDR ALT_USB_GLOB_GPVNDCTL_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GGPIO register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GGPIO_ADDR ALT_USB_GLOB_GGPIO_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GUID register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GUID_ADDR ALT_USB_GLOB_GUID_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GSNPSID register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GSNPSID_ADDR ALT_USB_GLOB_GSNPSID_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG1 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GHWCFG1_ADDR ALT_USB_GLOB_GHWCFG1_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG2 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GHWCFG2_ADDR ALT_USB_GLOB_GHWCFG2_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG3 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GHWCFG3_ADDR ALT_USB_GLOB_GHWCFG3_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG4 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GHWCFG4_ADDR ALT_USB_GLOB_GHWCFG4_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GDFIFOCFG register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GDFIFOCFG_ADDR ALT_USB_GLOB_GDFIFOCFG_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_HPTXFSIZ register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_HPTXFSIZ_ADDR ALT_USB_GLOB_HPTXFSIZ_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF1 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF1_ADDR ALT_USB_GLOB_DIEPTXF1_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF2 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF2_ADDR ALT_USB_GLOB_DIEPTXF2_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF3 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF3_ADDR ALT_USB_GLOB_DIEPTXF3_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF4 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF4_ADDR ALT_USB_GLOB_DIEPTXF4_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF5 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF5_ADDR ALT_USB_GLOB_DIEPTXF5_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF6 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF6_ADDR ALT_USB_GLOB_DIEPTXF6_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF7 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF7_ADDR ALT_USB_GLOB_DIEPTXF7_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF8 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF8_ADDR ALT_USB_GLOB_DIEPTXF8_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF9 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF9_ADDR ALT_USB_GLOB_DIEPTXF9_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF10 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF10_ADDR ALT_USB_GLOB_DIEPTXF10_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF11 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF11_ADDR ALT_USB_GLOB_DIEPTXF11_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF12 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF12_ADDR ALT_USB_GLOB_DIEPTXF12_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF13 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF13_ADDR ALT_USB_GLOB_DIEPTXF13_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF14 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF14_ADDR ALT_USB_GLOB_DIEPTXF14_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF15 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF15_ADDR ALT_USB_GLOB_DIEPTXF15_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB0_GLOBGRP component. */ +#define ALT_USB0_GLOBGRP_OFST 0x0 +/* The start address of the ALT_USB0_GLOBGRP component. */ +#define ALT_USB0_GLOBGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_GLOBGRP_OFST)) +/* The lower bound address range of the ALT_USB0_GLOBGRP component. */ +#define ALT_USB0_GLOBGRP_LB_ADDR ALT_USB0_GLOBGRP_ADDR +/* The upper bound address range of the ALT_USB0_GLOBGRP component. */ +#define ALT_USB0_GLOBGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_GLOBGRP_ADDR) + 0x140) - 1)) + + +/* + * Register Group Instance : hostgrp + * + * Instance hostgrp of register group ALT_USB_HOST. + * + * + */ +/* The address of the ALT_USB_HOST_HCFG register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCFG_ADDR ALT_USB_HOST_HCFG_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFIR register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HFIR_ADDR ALT_USB_HOST_HFIR_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFNUM register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HFNUM_ADDR ALT_USB_HOST_HFNUM_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HPTXSTS register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HPTXSTS_ADDR ALT_USB_HOST_HPTXSTS_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HAINT register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HAINT_ADDR ALT_USB_HOST_HAINT_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HAINTMSK register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HAINTMSK_ADDR ALT_USB_HOST_HAINTMSK_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFLBADDR register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HFLBADDR_ADDR ALT_USB_HOST_HFLBADDR_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HPRT register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HPRT_ADDR ALT_USB_HOST_HPRT_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR0_ADDR ALT_USB_HOST_HCCHAR0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT0_ADDR ALT_USB_HOST_HCSPLT0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT0_ADDR ALT_USB_HOST_HCINT0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK0_ADDR ALT_USB_HOST_HCINTMSK0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ0_ADDR ALT_USB_HOST_HCTSIZ0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA0_ADDR ALT_USB_HOST_HCDMA0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB0_ADDR ALT_USB_HOST_HCDMAB0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR1_ADDR ALT_USB_HOST_HCCHAR1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT1_ADDR ALT_USB_HOST_HCSPLT1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT1_ADDR ALT_USB_HOST_HCINT1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK1_ADDR ALT_USB_HOST_HCINTMSK1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ1_ADDR ALT_USB_HOST_HCTSIZ1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA1_ADDR ALT_USB_HOST_HCDMA1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB1_ADDR ALT_USB_HOST_HCDMAB1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR2_ADDR ALT_USB_HOST_HCCHAR2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT2_ADDR ALT_USB_HOST_HCSPLT2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT2_ADDR ALT_USB_HOST_HCINT2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK2_ADDR ALT_USB_HOST_HCINTMSK2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ2_ADDR ALT_USB_HOST_HCTSIZ2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA2_ADDR ALT_USB_HOST_HCDMA2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB2_ADDR ALT_USB_HOST_HCDMAB2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR3_ADDR ALT_USB_HOST_HCCHAR3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT3_ADDR ALT_USB_HOST_HCSPLT3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT3_ADDR ALT_USB_HOST_HCINT3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK3_ADDR ALT_USB_HOST_HCINTMSK3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ3_ADDR ALT_USB_HOST_HCTSIZ3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA3_ADDR ALT_USB_HOST_HCDMA3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB3_ADDR ALT_USB_HOST_HCDMAB3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR4_ADDR ALT_USB_HOST_HCCHAR4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT4_ADDR ALT_USB_HOST_HCSPLT4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT4_ADDR ALT_USB_HOST_HCINT4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK4_ADDR ALT_USB_HOST_HCINTMSK4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ4_ADDR ALT_USB_HOST_HCTSIZ4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA4_ADDR ALT_USB_HOST_HCDMA4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB4_ADDR ALT_USB_HOST_HCDMAB4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR5_ADDR ALT_USB_HOST_HCCHAR5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT5_ADDR ALT_USB_HOST_HCSPLT5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT5_ADDR ALT_USB_HOST_HCINT5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK5_ADDR ALT_USB_HOST_HCINTMSK5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ5_ADDR ALT_USB_HOST_HCTSIZ5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA5_ADDR ALT_USB_HOST_HCDMA5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB5_ADDR ALT_USB_HOST_HCDMAB5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR6_ADDR ALT_USB_HOST_HCCHAR6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT6_ADDR ALT_USB_HOST_HCSPLT6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT6_ADDR ALT_USB_HOST_HCINT6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK6_ADDR ALT_USB_HOST_HCINTMSK6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ6_ADDR ALT_USB_HOST_HCTSIZ6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA6_ADDR ALT_USB_HOST_HCDMA6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB6_ADDR ALT_USB_HOST_HCDMAB6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR7_ADDR ALT_USB_HOST_HCCHAR7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT7_ADDR ALT_USB_HOST_HCSPLT7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT7_ADDR ALT_USB_HOST_HCINT7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK7_ADDR ALT_USB_HOST_HCINTMSK7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ7_ADDR ALT_USB_HOST_HCTSIZ7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA7_ADDR ALT_USB_HOST_HCDMA7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB7_ADDR ALT_USB_HOST_HCDMAB7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR8_ADDR ALT_USB_HOST_HCCHAR8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT8_ADDR ALT_USB_HOST_HCSPLT8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT8_ADDR ALT_USB_HOST_HCINT8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK8_ADDR ALT_USB_HOST_HCINTMSK8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ8_ADDR ALT_USB_HOST_HCTSIZ8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA8_ADDR ALT_USB_HOST_HCDMA8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB8_ADDR ALT_USB_HOST_HCDMAB8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR9_ADDR ALT_USB_HOST_HCCHAR9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT9_ADDR ALT_USB_HOST_HCSPLT9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT9_ADDR ALT_USB_HOST_HCINT9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK9_ADDR ALT_USB_HOST_HCINTMSK9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ9_ADDR ALT_USB_HOST_HCTSIZ9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA9_ADDR ALT_USB_HOST_HCDMA9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB9_ADDR ALT_USB_HOST_HCDMAB9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR10_ADDR ALT_USB_HOST_HCCHAR10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT10_ADDR ALT_USB_HOST_HCSPLT10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT10_ADDR ALT_USB_HOST_HCINT10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK10_ADDR ALT_USB_HOST_HCINTMSK10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ10_ADDR ALT_USB_HOST_HCTSIZ10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA10_ADDR ALT_USB_HOST_HCDMA10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB10_ADDR ALT_USB_HOST_HCDMAB10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR11_ADDR ALT_USB_HOST_HCCHAR11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT11_ADDR ALT_USB_HOST_HCSPLT11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT11_ADDR ALT_USB_HOST_HCINT11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK11_ADDR ALT_USB_HOST_HCINTMSK11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ11_ADDR ALT_USB_HOST_HCTSIZ11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA11_ADDR ALT_USB_HOST_HCDMA11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB11_ADDR ALT_USB_HOST_HCDMAB11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR12_ADDR ALT_USB_HOST_HCCHAR12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT12_ADDR ALT_USB_HOST_HCSPLT12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT12_ADDR ALT_USB_HOST_HCINT12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK12_ADDR ALT_USB_HOST_HCINTMSK12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ12_ADDR ALT_USB_HOST_HCTSIZ12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA12_ADDR ALT_USB_HOST_HCDMA12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB12_ADDR ALT_USB_HOST_HCDMAB12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR13_ADDR ALT_USB_HOST_HCCHAR13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT13_ADDR ALT_USB_HOST_HCSPLT13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT13_ADDR ALT_USB_HOST_HCINT13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK13_ADDR ALT_USB_HOST_HCINTMSK13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ13_ADDR ALT_USB_HOST_HCTSIZ13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA13_ADDR ALT_USB_HOST_HCDMA13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB13_ADDR ALT_USB_HOST_HCDMAB13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR14_ADDR ALT_USB_HOST_HCCHAR14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT14_ADDR ALT_USB_HOST_HCSPLT14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT14_ADDR ALT_USB_HOST_HCINT14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK14_ADDR ALT_USB_HOST_HCINTMSK14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ14_ADDR ALT_USB_HOST_HCTSIZ14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA14_ADDR ALT_USB_HOST_HCDMA14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB14_ADDR ALT_USB_HOST_HCDMAB14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR15_ADDR ALT_USB_HOST_HCCHAR15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT15_ADDR ALT_USB_HOST_HCSPLT15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT15_ADDR ALT_USB_HOST_HCINT15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK15_ADDR ALT_USB_HOST_HCINTMSK15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ15_ADDR ALT_USB_HOST_HCTSIZ15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA15_ADDR ALT_USB_HOST_HCDMA15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB15_ADDR ALT_USB_HOST_HCDMAB15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB0_HOSTGRP component. */ +#define ALT_USB0_HOSTGRP_OFST 0x400 +/* The start address of the ALT_USB0_HOSTGRP component. */ +#define ALT_USB0_HOSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_HOSTGRP_OFST)) +/* The lower bound address range of the ALT_USB0_HOSTGRP component. */ +#define ALT_USB0_HOSTGRP_LB_ADDR ALT_USB0_HOSTGRP_ADDR +/* The upper bound address range of the ALT_USB0_HOSTGRP component. */ +#define ALT_USB0_HOSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_HOSTGRP_ADDR) + 0x2fc) - 1)) + + +/* + * Register Group Instance : devgrp + * + * Instance devgrp of register group ALT_USB_DEV. + * + * + */ +/* The address of the ALT_USB_DEV_DCFG register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DCFG_ADDR ALT_USB_DEV_DCFG_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DCTL register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DCTL_ADDR ALT_USB_DEV_DCTL_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DSTS register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DSTS_ADDR ALT_USB_DEV_DSTS_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPMSK register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPMSK_ADDR ALT_USB_DEV_DIEPMSK_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPMSK register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPMSK_ADDR ALT_USB_DEV_DOEPMSK_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DAINT register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DAINT_ADDR ALT_USB_DEV_DAINT_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DAINTMSK register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DAINTMSK_ADDR ALT_USB_DEV_DAINTMSK_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DVBUSDIS register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DVBUSDIS_ADDR ALT_USB_DEV_DVBUSDIS_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DVBUSPULSE register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DVBUSPULSE_ADDR ALT_USB_DEV_DVBUSPULSE_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTHRCTL register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTHRCTL_ADDR ALT_USB_DEV_DTHRCTL_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPEMPMSK register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPEMPMSK_ADDR ALT_USB_DEV_DIEPEMPMSK_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL0_ADDR ALT_USB_DEV_DIEPCTL0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT0_ADDR ALT_USB_DEV_DIEPINT0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ0_ADDR ALT_USB_DEV_DIEPTSIZ0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA0_ADDR ALT_USB_DEV_DIEPDMA0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS0_ADDR ALT_USB_DEV_DTXFSTS0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB0_ADDR ALT_USB_DEV_DIEPDMAB0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL1_ADDR ALT_USB_DEV_DIEPCTL1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT1_ADDR ALT_USB_DEV_DIEPINT1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ1_ADDR ALT_USB_DEV_DIEPTSIZ1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA1_ADDR ALT_USB_DEV_DIEPDMA1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS1_ADDR ALT_USB_DEV_DTXFSTS1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB1_ADDR ALT_USB_DEV_DIEPDMAB1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL2_ADDR ALT_USB_DEV_DIEPCTL2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT2_ADDR ALT_USB_DEV_DIEPINT2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ2_ADDR ALT_USB_DEV_DIEPTSIZ2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA2_ADDR ALT_USB_DEV_DIEPDMA2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS2_ADDR ALT_USB_DEV_DTXFSTS2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB2_ADDR ALT_USB_DEV_DIEPDMAB2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL3_ADDR ALT_USB_DEV_DIEPCTL3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT3_ADDR ALT_USB_DEV_DIEPINT3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ3_ADDR ALT_USB_DEV_DIEPTSIZ3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA3_ADDR ALT_USB_DEV_DIEPDMA3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS3_ADDR ALT_USB_DEV_DTXFSTS3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB3_ADDR ALT_USB_DEV_DIEPDMAB3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL4_ADDR ALT_USB_DEV_DIEPCTL4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT4_ADDR ALT_USB_DEV_DIEPINT4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ4_ADDR ALT_USB_DEV_DIEPTSIZ4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA4_ADDR ALT_USB_DEV_DIEPDMA4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS4_ADDR ALT_USB_DEV_DTXFSTS4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB4_ADDR ALT_USB_DEV_DIEPDMAB4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL5_ADDR ALT_USB_DEV_DIEPCTL5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT5_ADDR ALT_USB_DEV_DIEPINT5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ5_ADDR ALT_USB_DEV_DIEPTSIZ5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA5_ADDR ALT_USB_DEV_DIEPDMA5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS5_ADDR ALT_USB_DEV_DTXFSTS5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB5_ADDR ALT_USB_DEV_DIEPDMAB5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL6_ADDR ALT_USB_DEV_DIEPCTL6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT6_ADDR ALT_USB_DEV_DIEPINT6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ6_ADDR ALT_USB_DEV_DIEPTSIZ6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA6_ADDR ALT_USB_DEV_DIEPDMA6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS6_ADDR ALT_USB_DEV_DTXFSTS6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB6_ADDR ALT_USB_DEV_DIEPDMAB6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL7_ADDR ALT_USB_DEV_DIEPCTL7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT7_ADDR ALT_USB_DEV_DIEPINT7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ7_ADDR ALT_USB_DEV_DIEPTSIZ7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA7_ADDR ALT_USB_DEV_DIEPDMA7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS7_ADDR ALT_USB_DEV_DTXFSTS7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB7_ADDR ALT_USB_DEV_DIEPDMAB7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL8_ADDR ALT_USB_DEV_DIEPCTL8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT8_ADDR ALT_USB_DEV_DIEPINT8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ8_ADDR ALT_USB_DEV_DIEPTSIZ8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA8_ADDR ALT_USB_DEV_DIEPDMA8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS8_ADDR ALT_USB_DEV_DTXFSTS8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB8_ADDR ALT_USB_DEV_DIEPDMAB8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL9_ADDR ALT_USB_DEV_DIEPCTL9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT9_ADDR ALT_USB_DEV_DIEPINT9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ9_ADDR ALT_USB_DEV_DIEPTSIZ9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA9_ADDR ALT_USB_DEV_DIEPDMA9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS9_ADDR ALT_USB_DEV_DTXFSTS9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB9_ADDR ALT_USB_DEV_DIEPDMAB9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL10_ADDR ALT_USB_DEV_DIEPCTL10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT10_ADDR ALT_USB_DEV_DIEPINT10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ10_ADDR ALT_USB_DEV_DIEPTSIZ10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA10_ADDR ALT_USB_DEV_DIEPDMA10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS10_ADDR ALT_USB_DEV_DTXFSTS10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB10_ADDR ALT_USB_DEV_DIEPDMAB10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL11_ADDR ALT_USB_DEV_DIEPCTL11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT11_ADDR ALT_USB_DEV_DIEPINT11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ11_ADDR ALT_USB_DEV_DIEPTSIZ11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA11_ADDR ALT_USB_DEV_DIEPDMA11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS11_ADDR ALT_USB_DEV_DTXFSTS11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB11_ADDR ALT_USB_DEV_DIEPDMAB11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL12_ADDR ALT_USB_DEV_DIEPCTL12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT12_ADDR ALT_USB_DEV_DIEPINT12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ12_ADDR ALT_USB_DEV_DIEPTSIZ12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA12_ADDR ALT_USB_DEV_DIEPDMA12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS12_ADDR ALT_USB_DEV_DTXFSTS12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB12_ADDR ALT_USB_DEV_DIEPDMAB12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL13_ADDR ALT_USB_DEV_DIEPCTL13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT13_ADDR ALT_USB_DEV_DIEPINT13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ13_ADDR ALT_USB_DEV_DIEPTSIZ13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA13_ADDR ALT_USB_DEV_DIEPDMA13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS13_ADDR ALT_USB_DEV_DTXFSTS13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB13_ADDR ALT_USB_DEV_DIEPDMAB13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL14_ADDR ALT_USB_DEV_DIEPCTL14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT14_ADDR ALT_USB_DEV_DIEPINT14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ14_ADDR ALT_USB_DEV_DIEPTSIZ14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA14_ADDR ALT_USB_DEV_DIEPDMA14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS14_ADDR ALT_USB_DEV_DTXFSTS14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB14_ADDR ALT_USB_DEV_DIEPDMAB14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL15_ADDR ALT_USB_DEV_DIEPCTL15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT15_ADDR ALT_USB_DEV_DIEPINT15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ15_ADDR ALT_USB_DEV_DIEPTSIZ15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA15_ADDR ALT_USB_DEV_DIEPDMA15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS15_ADDR ALT_USB_DEV_DTXFSTS15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB15_ADDR ALT_USB_DEV_DIEPDMAB15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL0_ADDR ALT_USB_DEV_DOEPCTL0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT0_ADDR ALT_USB_DEV_DOEPINT0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ0_ADDR ALT_USB_DEV_DOEPTSIZ0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA0_ADDR ALT_USB_DEV_DOEPDMA0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB0_ADDR ALT_USB_DEV_DOEPDMAB0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL1_ADDR ALT_USB_DEV_DOEPCTL1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT1_ADDR ALT_USB_DEV_DOEPINT1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ1_ADDR ALT_USB_DEV_DOEPTSIZ1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA1_ADDR ALT_USB_DEV_DOEPDMA1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB1_ADDR ALT_USB_DEV_DOEPDMAB1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL2_ADDR ALT_USB_DEV_DOEPCTL2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT2_ADDR ALT_USB_DEV_DOEPINT2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ2_ADDR ALT_USB_DEV_DOEPTSIZ2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA2_ADDR ALT_USB_DEV_DOEPDMA2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB2_ADDR ALT_USB_DEV_DOEPDMAB2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL3_ADDR ALT_USB_DEV_DOEPCTL3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT3_ADDR ALT_USB_DEV_DOEPINT3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ3_ADDR ALT_USB_DEV_DOEPTSIZ3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA3_ADDR ALT_USB_DEV_DOEPDMA3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB3_ADDR ALT_USB_DEV_DOEPDMAB3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL4_ADDR ALT_USB_DEV_DOEPCTL4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT4_ADDR ALT_USB_DEV_DOEPINT4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ4_ADDR ALT_USB_DEV_DOEPTSIZ4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA4_ADDR ALT_USB_DEV_DOEPDMA4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB4_ADDR ALT_USB_DEV_DOEPDMAB4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL5_ADDR ALT_USB_DEV_DOEPCTL5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT5_ADDR ALT_USB_DEV_DOEPINT5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ5_ADDR ALT_USB_DEV_DOEPTSIZ5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA5_ADDR ALT_USB_DEV_DOEPDMA5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB5_ADDR ALT_USB_DEV_DOEPDMAB5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL6_ADDR ALT_USB_DEV_DOEPCTL6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT6_ADDR ALT_USB_DEV_DOEPINT6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ6_ADDR ALT_USB_DEV_DOEPTSIZ6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA6_ADDR ALT_USB_DEV_DOEPDMA6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB6_ADDR ALT_USB_DEV_DOEPDMAB6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL7_ADDR ALT_USB_DEV_DOEPCTL7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT7_ADDR ALT_USB_DEV_DOEPINT7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ7_ADDR ALT_USB_DEV_DOEPTSIZ7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA7_ADDR ALT_USB_DEV_DOEPDMA7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB7_ADDR ALT_USB_DEV_DOEPDMAB7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL8_ADDR ALT_USB_DEV_DOEPCTL8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT8_ADDR ALT_USB_DEV_DOEPINT8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ8_ADDR ALT_USB_DEV_DOEPTSIZ8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA8_ADDR ALT_USB_DEV_DOEPDMA8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB8_ADDR ALT_USB_DEV_DOEPDMAB8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL9_ADDR ALT_USB_DEV_DOEPCTL9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT9_ADDR ALT_USB_DEV_DOEPINT9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ9_ADDR ALT_USB_DEV_DOEPTSIZ9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA9_ADDR ALT_USB_DEV_DOEPDMA9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB9_ADDR ALT_USB_DEV_DOEPDMAB9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL10_ADDR ALT_USB_DEV_DOEPCTL10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT10_ADDR ALT_USB_DEV_DOEPINT10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ10_ADDR ALT_USB_DEV_DOEPTSIZ10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA10_ADDR ALT_USB_DEV_DOEPDMA10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB10_ADDR ALT_USB_DEV_DOEPDMAB10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL11_ADDR ALT_USB_DEV_DOEPCTL11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT11_ADDR ALT_USB_DEV_DOEPINT11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ11_ADDR ALT_USB_DEV_DOEPTSIZ11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA11_ADDR ALT_USB_DEV_DOEPDMA11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB11_ADDR ALT_USB_DEV_DOEPDMAB11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL12_ADDR ALT_USB_DEV_DOEPCTL12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT12_ADDR ALT_USB_DEV_DOEPINT12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ12_ADDR ALT_USB_DEV_DOEPTSIZ12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA12_ADDR ALT_USB_DEV_DOEPDMA12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB12_ADDR ALT_USB_DEV_DOEPDMAB12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL13_ADDR ALT_USB_DEV_DOEPCTL13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT13_ADDR ALT_USB_DEV_DOEPINT13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ13_ADDR ALT_USB_DEV_DOEPTSIZ13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA13_ADDR ALT_USB_DEV_DOEPDMA13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB13_ADDR ALT_USB_DEV_DOEPDMAB13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL14_ADDR ALT_USB_DEV_DOEPCTL14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT14_ADDR ALT_USB_DEV_DOEPINT14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ14_ADDR ALT_USB_DEV_DOEPTSIZ14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA14_ADDR ALT_USB_DEV_DOEPDMA14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB14_ADDR ALT_USB_DEV_DOEPDMAB14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL15_ADDR ALT_USB_DEV_DOEPCTL15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT15_ADDR ALT_USB_DEV_DOEPINT15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ15_ADDR ALT_USB_DEV_DOEPTSIZ15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA15_ADDR ALT_USB_DEV_DOEPDMA15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB15_ADDR ALT_USB_DEV_DOEPDMAB15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB0_DEVGRP component. */ +#define ALT_USB0_DEVGRP_OFST 0x800 +/* The start address of the ALT_USB0_DEVGRP component. */ +#define ALT_USB0_DEVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_DEVGRP_OFST)) +/* The lower bound address range of the ALT_USB0_DEVGRP component. */ +#define ALT_USB0_DEVGRP_LB_ADDR ALT_USB0_DEVGRP_ADDR +/* The upper bound address range of the ALT_USB0_DEVGRP component. */ +#define ALT_USB0_DEVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_DEVGRP_ADDR) + 0x500) - 1)) + + +/* + * Register Group Instance : pwrclkgrp + * + * Instance pwrclkgrp of register group ALT_USB_PWRCLK. + * + * + */ +/* The address of the ALT_USB_PWRCLK_PCGCCTL register for the ALT_USB0_PWRCLKGRP instance. */ +#define ALT_USB0_PWRCLK_PCGCCTL_ADDR ALT_USB_PWRCLK_PCGCCTL_ADDR(ALT_USB0_PWRCLKGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB0_PWRCLKGRP component. */ +#define ALT_USB0_PWRCLKGRP_OFST 0xe00 +/* The start address of the ALT_USB0_PWRCLKGRP component. */ +#define ALT_USB0_PWRCLKGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_PWRCLKGRP_OFST)) +/* The lower bound address range of the ALT_USB0_PWRCLKGRP component. */ +#define ALT_USB0_PWRCLKGRP_LB_ADDR ALT_USB0_PWRCLKGRP_ADDR +/* The upper bound address range of the ALT_USB0_PWRCLKGRP component. */ +#define ALT_USB0_PWRCLKGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_PWRCLKGRP_ADDR) + 0x4) - 1)) + + +/* The base address byte offset for the start of the ALT_USB0 component. */ +#define ALT_USB0_OFST 0xffb00000 +/* The start address of the ALT_USB0 component. */ +#define ALT_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_USB0_OFST)) +/* The lower bound address range of the ALT_USB0 component. */ +#define ALT_USB0_LB_ADDR ALT_USB0_ADDR +/* The upper bound address range of the ALT_USB0 component. */ +#define ALT_USB0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_ADDR) + 0x40000) - 1)) + + +/* + * Component Instance : usb1 + * + * Instance usb1 of component ALT_USB. + * + * + */ +/* + * Register Group Instance : globgrp + * + * Instance globgrp of register group ALT_USB_GLOB. + * + * + */ +/* The address of the ALT_USB_GLOB_GOTGCTL register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GOTGCTL_ADDR ALT_USB_GLOB_GOTGCTL_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GOTGINT register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GOTGINT_ADDR ALT_USB_GLOB_GOTGINT_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GAHBCFG register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GAHBCFG_ADDR ALT_USB_GLOB_GAHBCFG_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GUSBCFG register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GUSBCFG_ADDR ALT_USB_GLOB_GUSBCFG_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRSTCTL register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GRSTCTL_ADDR ALT_USB_GLOB_GRSTCTL_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GINTSTS register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GINTSTS_ADDR ALT_USB_GLOB_GINTSTS_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GINTMSK register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GINTMSK_ADDR ALT_USB_GLOB_GINTMSK_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXSTSR register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GRXSTSR_ADDR ALT_USB_GLOB_GRXSTSR_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXSTSP register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GRXSTSP_ADDR ALT_USB_GLOB_GRXSTSP_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXFSIZ register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GRXFSIZ_ADDR ALT_USB_GLOB_GRXFSIZ_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GNPTXFSIZ register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GNPTXFSIZ_ADDR ALT_USB_GLOB_GNPTXFSIZ_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GNPTXSTS register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GNPTXSTS_ADDR ALT_USB_GLOB_GNPTXSTS_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GPVNDCTL register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GPVNDCTL_ADDR ALT_USB_GLOB_GPVNDCTL_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GGPIO register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GGPIO_ADDR ALT_USB_GLOB_GGPIO_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GUID register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GUID_ADDR ALT_USB_GLOB_GUID_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GSNPSID register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GSNPSID_ADDR ALT_USB_GLOB_GSNPSID_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG1 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GHWCFG1_ADDR ALT_USB_GLOB_GHWCFG1_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG2 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GHWCFG2_ADDR ALT_USB_GLOB_GHWCFG2_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG3 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GHWCFG3_ADDR ALT_USB_GLOB_GHWCFG3_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG4 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GHWCFG4_ADDR ALT_USB_GLOB_GHWCFG4_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GDFIFOCFG register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GDFIFOCFG_ADDR ALT_USB_GLOB_GDFIFOCFG_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_HPTXFSIZ register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_HPTXFSIZ_ADDR ALT_USB_GLOB_HPTXFSIZ_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF1 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF1_ADDR ALT_USB_GLOB_DIEPTXF1_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF2 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF2_ADDR ALT_USB_GLOB_DIEPTXF2_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF3 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF3_ADDR ALT_USB_GLOB_DIEPTXF3_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF4 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF4_ADDR ALT_USB_GLOB_DIEPTXF4_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF5 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF5_ADDR ALT_USB_GLOB_DIEPTXF5_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF6 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF6_ADDR ALT_USB_GLOB_DIEPTXF6_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF7 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF7_ADDR ALT_USB_GLOB_DIEPTXF7_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF8 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF8_ADDR ALT_USB_GLOB_DIEPTXF8_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF9 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF9_ADDR ALT_USB_GLOB_DIEPTXF9_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF10 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF10_ADDR ALT_USB_GLOB_DIEPTXF10_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF11 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF11_ADDR ALT_USB_GLOB_DIEPTXF11_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF12 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF12_ADDR ALT_USB_GLOB_DIEPTXF12_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF13 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF13_ADDR ALT_USB_GLOB_DIEPTXF13_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF14 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF14_ADDR ALT_USB_GLOB_DIEPTXF14_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF15 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF15_ADDR ALT_USB_GLOB_DIEPTXF15_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB1_GLOBGRP component. */ +#define ALT_USB1_GLOBGRP_OFST 0x0 +/* The start address of the ALT_USB1_GLOBGRP component. */ +#define ALT_USB1_GLOBGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_GLOBGRP_OFST)) +/* The lower bound address range of the ALT_USB1_GLOBGRP component. */ +#define ALT_USB1_GLOBGRP_LB_ADDR ALT_USB1_GLOBGRP_ADDR +/* The upper bound address range of the ALT_USB1_GLOBGRP component. */ +#define ALT_USB1_GLOBGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_GLOBGRP_ADDR) + 0x140) - 1)) + + +/* + * Register Group Instance : hostgrp + * + * Instance hostgrp of register group ALT_USB_HOST. + * + * + */ +/* The address of the ALT_USB_HOST_HCFG register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCFG_ADDR ALT_USB_HOST_HCFG_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFIR register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HFIR_ADDR ALT_USB_HOST_HFIR_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFNUM register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HFNUM_ADDR ALT_USB_HOST_HFNUM_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HPTXSTS register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HPTXSTS_ADDR ALT_USB_HOST_HPTXSTS_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HAINT register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HAINT_ADDR ALT_USB_HOST_HAINT_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HAINTMSK register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HAINTMSK_ADDR ALT_USB_HOST_HAINTMSK_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFLBADDR register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HFLBADDR_ADDR ALT_USB_HOST_HFLBADDR_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HPRT register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HPRT_ADDR ALT_USB_HOST_HPRT_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR0_ADDR ALT_USB_HOST_HCCHAR0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT0_ADDR ALT_USB_HOST_HCSPLT0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT0_ADDR ALT_USB_HOST_HCINT0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK0_ADDR ALT_USB_HOST_HCINTMSK0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ0_ADDR ALT_USB_HOST_HCTSIZ0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA0_ADDR ALT_USB_HOST_HCDMA0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB0_ADDR ALT_USB_HOST_HCDMAB0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR1_ADDR ALT_USB_HOST_HCCHAR1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT1_ADDR ALT_USB_HOST_HCSPLT1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT1_ADDR ALT_USB_HOST_HCINT1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK1_ADDR ALT_USB_HOST_HCINTMSK1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ1_ADDR ALT_USB_HOST_HCTSIZ1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA1_ADDR ALT_USB_HOST_HCDMA1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB1_ADDR ALT_USB_HOST_HCDMAB1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR2_ADDR ALT_USB_HOST_HCCHAR2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT2_ADDR ALT_USB_HOST_HCSPLT2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT2_ADDR ALT_USB_HOST_HCINT2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK2_ADDR ALT_USB_HOST_HCINTMSK2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ2_ADDR ALT_USB_HOST_HCTSIZ2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA2_ADDR ALT_USB_HOST_HCDMA2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB2_ADDR ALT_USB_HOST_HCDMAB2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR3_ADDR ALT_USB_HOST_HCCHAR3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT3_ADDR ALT_USB_HOST_HCSPLT3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT3_ADDR ALT_USB_HOST_HCINT3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK3_ADDR ALT_USB_HOST_HCINTMSK3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ3_ADDR ALT_USB_HOST_HCTSIZ3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA3_ADDR ALT_USB_HOST_HCDMA3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB3_ADDR ALT_USB_HOST_HCDMAB3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR4_ADDR ALT_USB_HOST_HCCHAR4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT4_ADDR ALT_USB_HOST_HCSPLT4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT4_ADDR ALT_USB_HOST_HCINT4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK4_ADDR ALT_USB_HOST_HCINTMSK4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ4_ADDR ALT_USB_HOST_HCTSIZ4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA4_ADDR ALT_USB_HOST_HCDMA4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB4_ADDR ALT_USB_HOST_HCDMAB4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR5_ADDR ALT_USB_HOST_HCCHAR5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT5_ADDR ALT_USB_HOST_HCSPLT5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT5_ADDR ALT_USB_HOST_HCINT5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK5_ADDR ALT_USB_HOST_HCINTMSK5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ5_ADDR ALT_USB_HOST_HCTSIZ5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA5_ADDR ALT_USB_HOST_HCDMA5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB5_ADDR ALT_USB_HOST_HCDMAB5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR6_ADDR ALT_USB_HOST_HCCHAR6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT6_ADDR ALT_USB_HOST_HCSPLT6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT6_ADDR ALT_USB_HOST_HCINT6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK6_ADDR ALT_USB_HOST_HCINTMSK6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ6_ADDR ALT_USB_HOST_HCTSIZ6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA6_ADDR ALT_USB_HOST_HCDMA6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB6_ADDR ALT_USB_HOST_HCDMAB6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR7_ADDR ALT_USB_HOST_HCCHAR7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT7_ADDR ALT_USB_HOST_HCSPLT7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT7_ADDR ALT_USB_HOST_HCINT7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK7_ADDR ALT_USB_HOST_HCINTMSK7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ7_ADDR ALT_USB_HOST_HCTSIZ7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA7_ADDR ALT_USB_HOST_HCDMA7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB7_ADDR ALT_USB_HOST_HCDMAB7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR8_ADDR ALT_USB_HOST_HCCHAR8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT8_ADDR ALT_USB_HOST_HCSPLT8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT8_ADDR ALT_USB_HOST_HCINT8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK8_ADDR ALT_USB_HOST_HCINTMSK8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ8_ADDR ALT_USB_HOST_HCTSIZ8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA8_ADDR ALT_USB_HOST_HCDMA8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB8_ADDR ALT_USB_HOST_HCDMAB8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR9_ADDR ALT_USB_HOST_HCCHAR9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT9_ADDR ALT_USB_HOST_HCSPLT9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT9_ADDR ALT_USB_HOST_HCINT9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK9_ADDR ALT_USB_HOST_HCINTMSK9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ9_ADDR ALT_USB_HOST_HCTSIZ9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA9_ADDR ALT_USB_HOST_HCDMA9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB9_ADDR ALT_USB_HOST_HCDMAB9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR10_ADDR ALT_USB_HOST_HCCHAR10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT10_ADDR ALT_USB_HOST_HCSPLT10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT10_ADDR ALT_USB_HOST_HCINT10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK10_ADDR ALT_USB_HOST_HCINTMSK10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ10_ADDR ALT_USB_HOST_HCTSIZ10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA10_ADDR ALT_USB_HOST_HCDMA10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB10_ADDR ALT_USB_HOST_HCDMAB10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR11_ADDR ALT_USB_HOST_HCCHAR11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT11_ADDR ALT_USB_HOST_HCSPLT11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT11_ADDR ALT_USB_HOST_HCINT11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK11_ADDR ALT_USB_HOST_HCINTMSK11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ11_ADDR ALT_USB_HOST_HCTSIZ11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA11_ADDR ALT_USB_HOST_HCDMA11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB11_ADDR ALT_USB_HOST_HCDMAB11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR12_ADDR ALT_USB_HOST_HCCHAR12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT12_ADDR ALT_USB_HOST_HCSPLT12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT12_ADDR ALT_USB_HOST_HCINT12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK12_ADDR ALT_USB_HOST_HCINTMSK12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ12_ADDR ALT_USB_HOST_HCTSIZ12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA12_ADDR ALT_USB_HOST_HCDMA12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB12_ADDR ALT_USB_HOST_HCDMAB12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR13_ADDR ALT_USB_HOST_HCCHAR13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT13_ADDR ALT_USB_HOST_HCSPLT13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT13_ADDR ALT_USB_HOST_HCINT13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK13_ADDR ALT_USB_HOST_HCINTMSK13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ13_ADDR ALT_USB_HOST_HCTSIZ13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA13_ADDR ALT_USB_HOST_HCDMA13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB13_ADDR ALT_USB_HOST_HCDMAB13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR14_ADDR ALT_USB_HOST_HCCHAR14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT14_ADDR ALT_USB_HOST_HCSPLT14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT14_ADDR ALT_USB_HOST_HCINT14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK14_ADDR ALT_USB_HOST_HCINTMSK14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ14_ADDR ALT_USB_HOST_HCTSIZ14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA14_ADDR ALT_USB_HOST_HCDMA14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB14_ADDR ALT_USB_HOST_HCDMAB14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR15_ADDR ALT_USB_HOST_HCCHAR15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT15_ADDR ALT_USB_HOST_HCSPLT15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT15_ADDR ALT_USB_HOST_HCINT15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK15_ADDR ALT_USB_HOST_HCINTMSK15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ15_ADDR ALT_USB_HOST_HCTSIZ15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA15_ADDR ALT_USB_HOST_HCDMA15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB15_ADDR ALT_USB_HOST_HCDMAB15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB1_HOSTGRP component. */ +#define ALT_USB1_HOSTGRP_OFST 0x400 +/* The start address of the ALT_USB1_HOSTGRP component. */ +#define ALT_USB1_HOSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_HOSTGRP_OFST)) +/* The lower bound address range of the ALT_USB1_HOSTGRP component. */ +#define ALT_USB1_HOSTGRP_LB_ADDR ALT_USB1_HOSTGRP_ADDR +/* The upper bound address range of the ALT_USB1_HOSTGRP component. */ +#define ALT_USB1_HOSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_HOSTGRP_ADDR) + 0x2fc) - 1)) + + +/* + * Register Group Instance : devgrp + * + * Instance devgrp of register group ALT_USB_DEV. + * + * + */ +/* The address of the ALT_USB_DEV_DCFG register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DCFG_ADDR ALT_USB_DEV_DCFG_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DCTL register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DCTL_ADDR ALT_USB_DEV_DCTL_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DSTS register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DSTS_ADDR ALT_USB_DEV_DSTS_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPMSK register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPMSK_ADDR ALT_USB_DEV_DIEPMSK_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPMSK register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPMSK_ADDR ALT_USB_DEV_DOEPMSK_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DAINT register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DAINT_ADDR ALT_USB_DEV_DAINT_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DAINTMSK register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DAINTMSK_ADDR ALT_USB_DEV_DAINTMSK_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DVBUSDIS register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DVBUSDIS_ADDR ALT_USB_DEV_DVBUSDIS_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DVBUSPULSE register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DVBUSPULSE_ADDR ALT_USB_DEV_DVBUSPULSE_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTHRCTL register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTHRCTL_ADDR ALT_USB_DEV_DTHRCTL_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPEMPMSK register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPEMPMSK_ADDR ALT_USB_DEV_DIEPEMPMSK_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL0_ADDR ALT_USB_DEV_DIEPCTL0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT0_ADDR ALT_USB_DEV_DIEPINT0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ0_ADDR ALT_USB_DEV_DIEPTSIZ0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA0_ADDR ALT_USB_DEV_DIEPDMA0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS0_ADDR ALT_USB_DEV_DTXFSTS0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB0_ADDR ALT_USB_DEV_DIEPDMAB0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL1_ADDR ALT_USB_DEV_DIEPCTL1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT1_ADDR ALT_USB_DEV_DIEPINT1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ1_ADDR ALT_USB_DEV_DIEPTSIZ1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA1_ADDR ALT_USB_DEV_DIEPDMA1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS1_ADDR ALT_USB_DEV_DTXFSTS1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB1_ADDR ALT_USB_DEV_DIEPDMAB1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL2_ADDR ALT_USB_DEV_DIEPCTL2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT2_ADDR ALT_USB_DEV_DIEPINT2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ2_ADDR ALT_USB_DEV_DIEPTSIZ2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA2_ADDR ALT_USB_DEV_DIEPDMA2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS2_ADDR ALT_USB_DEV_DTXFSTS2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB2_ADDR ALT_USB_DEV_DIEPDMAB2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL3_ADDR ALT_USB_DEV_DIEPCTL3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT3_ADDR ALT_USB_DEV_DIEPINT3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ3_ADDR ALT_USB_DEV_DIEPTSIZ3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA3_ADDR ALT_USB_DEV_DIEPDMA3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS3_ADDR ALT_USB_DEV_DTXFSTS3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB3_ADDR ALT_USB_DEV_DIEPDMAB3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL4_ADDR ALT_USB_DEV_DIEPCTL4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT4_ADDR ALT_USB_DEV_DIEPINT4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ4_ADDR ALT_USB_DEV_DIEPTSIZ4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA4_ADDR ALT_USB_DEV_DIEPDMA4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS4_ADDR ALT_USB_DEV_DTXFSTS4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB4_ADDR ALT_USB_DEV_DIEPDMAB4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL5_ADDR ALT_USB_DEV_DIEPCTL5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT5_ADDR ALT_USB_DEV_DIEPINT5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ5_ADDR ALT_USB_DEV_DIEPTSIZ5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA5_ADDR ALT_USB_DEV_DIEPDMA5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS5_ADDR ALT_USB_DEV_DTXFSTS5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB5_ADDR ALT_USB_DEV_DIEPDMAB5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL6_ADDR ALT_USB_DEV_DIEPCTL6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT6_ADDR ALT_USB_DEV_DIEPINT6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ6_ADDR ALT_USB_DEV_DIEPTSIZ6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA6_ADDR ALT_USB_DEV_DIEPDMA6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS6_ADDR ALT_USB_DEV_DTXFSTS6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB6_ADDR ALT_USB_DEV_DIEPDMAB6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL7_ADDR ALT_USB_DEV_DIEPCTL7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT7_ADDR ALT_USB_DEV_DIEPINT7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ7_ADDR ALT_USB_DEV_DIEPTSIZ7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA7_ADDR ALT_USB_DEV_DIEPDMA7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS7_ADDR ALT_USB_DEV_DTXFSTS7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB7_ADDR ALT_USB_DEV_DIEPDMAB7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL8_ADDR ALT_USB_DEV_DIEPCTL8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT8_ADDR ALT_USB_DEV_DIEPINT8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ8_ADDR ALT_USB_DEV_DIEPTSIZ8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA8_ADDR ALT_USB_DEV_DIEPDMA8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS8_ADDR ALT_USB_DEV_DTXFSTS8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB8_ADDR ALT_USB_DEV_DIEPDMAB8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL9_ADDR ALT_USB_DEV_DIEPCTL9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT9_ADDR ALT_USB_DEV_DIEPINT9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ9_ADDR ALT_USB_DEV_DIEPTSIZ9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA9_ADDR ALT_USB_DEV_DIEPDMA9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS9_ADDR ALT_USB_DEV_DTXFSTS9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB9_ADDR ALT_USB_DEV_DIEPDMAB9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL10_ADDR ALT_USB_DEV_DIEPCTL10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT10_ADDR ALT_USB_DEV_DIEPINT10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ10_ADDR ALT_USB_DEV_DIEPTSIZ10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA10_ADDR ALT_USB_DEV_DIEPDMA10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS10_ADDR ALT_USB_DEV_DTXFSTS10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB10_ADDR ALT_USB_DEV_DIEPDMAB10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL11_ADDR ALT_USB_DEV_DIEPCTL11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT11_ADDR ALT_USB_DEV_DIEPINT11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ11_ADDR ALT_USB_DEV_DIEPTSIZ11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA11_ADDR ALT_USB_DEV_DIEPDMA11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS11_ADDR ALT_USB_DEV_DTXFSTS11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB11_ADDR ALT_USB_DEV_DIEPDMAB11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL12_ADDR ALT_USB_DEV_DIEPCTL12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT12_ADDR ALT_USB_DEV_DIEPINT12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ12_ADDR ALT_USB_DEV_DIEPTSIZ12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA12_ADDR ALT_USB_DEV_DIEPDMA12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS12_ADDR ALT_USB_DEV_DTXFSTS12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB12_ADDR ALT_USB_DEV_DIEPDMAB12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL13_ADDR ALT_USB_DEV_DIEPCTL13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT13_ADDR ALT_USB_DEV_DIEPINT13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ13_ADDR ALT_USB_DEV_DIEPTSIZ13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA13_ADDR ALT_USB_DEV_DIEPDMA13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS13_ADDR ALT_USB_DEV_DTXFSTS13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB13_ADDR ALT_USB_DEV_DIEPDMAB13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL14_ADDR ALT_USB_DEV_DIEPCTL14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT14_ADDR ALT_USB_DEV_DIEPINT14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ14_ADDR ALT_USB_DEV_DIEPTSIZ14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA14_ADDR ALT_USB_DEV_DIEPDMA14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS14_ADDR ALT_USB_DEV_DTXFSTS14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB14_ADDR ALT_USB_DEV_DIEPDMAB14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL15_ADDR ALT_USB_DEV_DIEPCTL15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT15_ADDR ALT_USB_DEV_DIEPINT15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ15_ADDR ALT_USB_DEV_DIEPTSIZ15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA15_ADDR ALT_USB_DEV_DIEPDMA15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS15_ADDR ALT_USB_DEV_DTXFSTS15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB15_ADDR ALT_USB_DEV_DIEPDMAB15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL0_ADDR ALT_USB_DEV_DOEPCTL0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT0_ADDR ALT_USB_DEV_DOEPINT0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ0_ADDR ALT_USB_DEV_DOEPTSIZ0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA0_ADDR ALT_USB_DEV_DOEPDMA0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB0_ADDR ALT_USB_DEV_DOEPDMAB0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL1_ADDR ALT_USB_DEV_DOEPCTL1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT1_ADDR ALT_USB_DEV_DOEPINT1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ1_ADDR ALT_USB_DEV_DOEPTSIZ1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA1_ADDR ALT_USB_DEV_DOEPDMA1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB1_ADDR ALT_USB_DEV_DOEPDMAB1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL2_ADDR ALT_USB_DEV_DOEPCTL2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT2_ADDR ALT_USB_DEV_DOEPINT2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ2_ADDR ALT_USB_DEV_DOEPTSIZ2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA2_ADDR ALT_USB_DEV_DOEPDMA2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB2_ADDR ALT_USB_DEV_DOEPDMAB2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL3_ADDR ALT_USB_DEV_DOEPCTL3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT3_ADDR ALT_USB_DEV_DOEPINT3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ3_ADDR ALT_USB_DEV_DOEPTSIZ3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA3_ADDR ALT_USB_DEV_DOEPDMA3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB3_ADDR ALT_USB_DEV_DOEPDMAB3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL4_ADDR ALT_USB_DEV_DOEPCTL4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT4_ADDR ALT_USB_DEV_DOEPINT4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ4_ADDR ALT_USB_DEV_DOEPTSIZ4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA4_ADDR ALT_USB_DEV_DOEPDMA4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB4_ADDR ALT_USB_DEV_DOEPDMAB4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL5_ADDR ALT_USB_DEV_DOEPCTL5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT5_ADDR ALT_USB_DEV_DOEPINT5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ5_ADDR ALT_USB_DEV_DOEPTSIZ5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA5_ADDR ALT_USB_DEV_DOEPDMA5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB5_ADDR ALT_USB_DEV_DOEPDMAB5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL6_ADDR ALT_USB_DEV_DOEPCTL6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT6_ADDR ALT_USB_DEV_DOEPINT6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ6_ADDR ALT_USB_DEV_DOEPTSIZ6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA6_ADDR ALT_USB_DEV_DOEPDMA6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB6_ADDR ALT_USB_DEV_DOEPDMAB6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL7_ADDR ALT_USB_DEV_DOEPCTL7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT7_ADDR ALT_USB_DEV_DOEPINT7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ7_ADDR ALT_USB_DEV_DOEPTSIZ7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA7_ADDR ALT_USB_DEV_DOEPDMA7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB7_ADDR ALT_USB_DEV_DOEPDMAB7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL8_ADDR ALT_USB_DEV_DOEPCTL8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT8_ADDR ALT_USB_DEV_DOEPINT8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ8_ADDR ALT_USB_DEV_DOEPTSIZ8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA8_ADDR ALT_USB_DEV_DOEPDMA8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB8_ADDR ALT_USB_DEV_DOEPDMAB8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL9_ADDR ALT_USB_DEV_DOEPCTL9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT9_ADDR ALT_USB_DEV_DOEPINT9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ9_ADDR ALT_USB_DEV_DOEPTSIZ9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA9_ADDR ALT_USB_DEV_DOEPDMA9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB9_ADDR ALT_USB_DEV_DOEPDMAB9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL10_ADDR ALT_USB_DEV_DOEPCTL10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT10_ADDR ALT_USB_DEV_DOEPINT10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ10_ADDR ALT_USB_DEV_DOEPTSIZ10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA10_ADDR ALT_USB_DEV_DOEPDMA10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB10_ADDR ALT_USB_DEV_DOEPDMAB10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL11_ADDR ALT_USB_DEV_DOEPCTL11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT11_ADDR ALT_USB_DEV_DOEPINT11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ11_ADDR ALT_USB_DEV_DOEPTSIZ11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA11_ADDR ALT_USB_DEV_DOEPDMA11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB11_ADDR ALT_USB_DEV_DOEPDMAB11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL12_ADDR ALT_USB_DEV_DOEPCTL12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT12_ADDR ALT_USB_DEV_DOEPINT12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ12_ADDR ALT_USB_DEV_DOEPTSIZ12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA12_ADDR ALT_USB_DEV_DOEPDMA12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB12_ADDR ALT_USB_DEV_DOEPDMAB12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL13_ADDR ALT_USB_DEV_DOEPCTL13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT13_ADDR ALT_USB_DEV_DOEPINT13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ13_ADDR ALT_USB_DEV_DOEPTSIZ13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA13_ADDR ALT_USB_DEV_DOEPDMA13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB13_ADDR ALT_USB_DEV_DOEPDMAB13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL14_ADDR ALT_USB_DEV_DOEPCTL14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT14_ADDR ALT_USB_DEV_DOEPINT14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ14_ADDR ALT_USB_DEV_DOEPTSIZ14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA14_ADDR ALT_USB_DEV_DOEPDMA14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB14_ADDR ALT_USB_DEV_DOEPDMAB14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL15_ADDR ALT_USB_DEV_DOEPCTL15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT15_ADDR ALT_USB_DEV_DOEPINT15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ15_ADDR ALT_USB_DEV_DOEPTSIZ15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA15_ADDR ALT_USB_DEV_DOEPDMA15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB15_ADDR ALT_USB_DEV_DOEPDMAB15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB1_DEVGRP component. */ +#define ALT_USB1_DEVGRP_OFST 0x800 +/* The start address of the ALT_USB1_DEVGRP component. */ +#define ALT_USB1_DEVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_DEVGRP_OFST)) +/* The lower bound address range of the ALT_USB1_DEVGRP component. */ +#define ALT_USB1_DEVGRP_LB_ADDR ALT_USB1_DEVGRP_ADDR +/* The upper bound address range of the ALT_USB1_DEVGRP component. */ +#define ALT_USB1_DEVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_DEVGRP_ADDR) + 0x500) - 1)) + + +/* + * Register Group Instance : pwrclkgrp + * + * Instance pwrclkgrp of register group ALT_USB_PWRCLK. + * + * + */ +/* The address of the ALT_USB_PWRCLK_PCGCCTL register for the ALT_USB1_PWRCLKGRP instance. */ +#define ALT_USB1_PWRCLK_PCGCCTL_ADDR ALT_USB_PWRCLK_PCGCCTL_ADDR(ALT_USB1_PWRCLKGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB1_PWRCLKGRP component. */ +#define ALT_USB1_PWRCLKGRP_OFST 0xe00 +/* The start address of the ALT_USB1_PWRCLKGRP component. */ +#define ALT_USB1_PWRCLKGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_PWRCLKGRP_OFST)) +/* The lower bound address range of the ALT_USB1_PWRCLKGRP component. */ +#define ALT_USB1_PWRCLKGRP_LB_ADDR ALT_USB1_PWRCLKGRP_ADDR +/* The upper bound address range of the ALT_USB1_PWRCLKGRP component. */ +#define ALT_USB1_PWRCLKGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_PWRCLKGRP_ADDR) + 0x4) - 1)) + + +/* The base address byte offset for the start of the ALT_USB1 component. */ +#define ALT_USB1_OFST 0xffb40000 +/* The start address of the ALT_USB1 component. */ +#define ALT_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_USB1_OFST)) +/* The lower bound address range of the ALT_USB1 component. */ +#define ALT_USB1_LB_ADDR ALT_USB1_ADDR +/* The upper bound address range of the ALT_USB1 component. */ +#define ALT_USB1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_ADDR) + 0x40000) - 1)) + + +/* + * Component Instance : nandregs + * + * Instance nandregs of component ALT_NAND. + * + * + */ +/* + * Register Group Instance : config + * + * Instance config of register group ALT_NAND_CFG. + * + * + */ +/* The address of the ALT_NAND_CFG_DEVICE_RST register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICE_RST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_RST_OFST)) +/* The address of the ALT_NAND_CFG_TFR_SPARE_REG register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_TFR_SPARE_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TFR_SPARE_REG_OFST)) +/* The address of the ALT_NAND_CFG_LD_WAIT_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_LD_WAIT_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_LD_WAIT_CNT_OFST)) +/* The address of the ALT_NAND_CFG_PROGRAM_WAIT_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST)) +/* The address of the ALT_NAND_CFG_ERASE_WAIT_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_ERASE_WAIT_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ERASE_WAIT_CNT_OFST)) +/* The address of the ALT_NAND_CFG_INT_MON_CYCCNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_INT_MON_CYCCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_INT_MON_CYCCNT_OFST)) +/* The address of the ALT_NAND_CFG_RB_PIN_END register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RB_PIN_END_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RB_PIN_END_OFST)) +/* The address of the ALT_NAND_CFG_MULTIPLANE_OP register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_MULTIPLANE_OP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MULTIPLANE_OP_OFST)) +/* The address of the ALT_NAND_CFG_MULTIPLANE_RD_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_MULTIPLANE_RD_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MULTIPLANE_RD_EN_OFST)) +/* The address of the ALT_NAND_CFG_COPYBACK_DIS register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_COPYBACK_DIS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_COPYBACK_DIS_OFST)) +/* The address of the ALT_NAND_CFG_CACHE_WR_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_CACHE_WR_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CACHE_WR_EN_OFST)) +/* The address of the ALT_NAND_CFG_CACHE_RD_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_CACHE_RD_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CACHE_RD_EN_OFST)) +/* The address of the ALT_NAND_CFG_PREFETCH_MOD register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_PREFETCH_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_PREFETCH_MOD_OFST)) +/* The address of the ALT_NAND_CFG_CHIP_EN_DONT_CARE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CHIP_EN_DONT_CARE_OFST)) +/* The address of the ALT_NAND_CFG_ECC_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_ECC_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ECC_EN_OFST)) +/* The address of the ALT_NAND_CFG_GLOB_INT_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_GLOB_INT_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_GLOB_INT_EN_OFST)) +/* The address of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST)) +/* The address of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST)) +/* The address of the ALT_NAND_CFG_RE_2_WE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RE_2_WE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RE_2_WE_OFST)) +/* The address of the ALT_NAND_CFG_ACC_CLKS register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_ACC_CLKS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ACC_CLKS_OFST)) +/* The address of the ALT_NAND_CFG_NUMBER_OF_PLANES register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_NUMBER_OF_PLANES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_NUMBER_OF_PLANES_OFST)) +/* The address of the ALT_NAND_CFG_PAGES_PER_BLOCK register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_PAGES_PER_BLOCK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_PAGES_PER_BLOCK_OFST)) +/* The address of the ALT_NAND_CFG_DEVICE_WIDTH register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICE_WIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_WIDTH_OFST)) +/* The address of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST)) +/* The address of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST)) +/* The address of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST)) +/* The address of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST)) +/* The address of the ALT_NAND_CFG_ECC_CORRECTION register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_ECC_CORRECTION_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ECC_CORRECTION_OFST)) +/* The address of the ALT_NAND_CFG_RD_MOD register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RD_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RD_MOD_OFST)) +/* The address of the ALT_NAND_CFG_WR_MOD register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_WR_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_WR_MOD_OFST)) +/* The address of the ALT_NAND_CFG_COPYBACK_MOD register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_COPYBACK_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_COPYBACK_MOD_OFST)) +/* The address of the ALT_NAND_CFG_RDWR_EN_LO_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RDWR_EN_LO_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST)) +/* The address of the ALT_NAND_CFG_RDWR_EN_HI_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RDWR_EN_HI_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST)) +/* The address of the ALT_NAND_CFG_MAX_RD_DELAY register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_MAX_RD_DELAY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MAX_RD_DELAY_OFST)) +/* The address of the ALT_NAND_CFG_CS_SETUP_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_CS_SETUP_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CS_SETUP_CNT_OFST)) +/* The address of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST)) +/* The address of the ALT_NAND_CFG_SPARE_AREA_MARKER register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_SPARE_AREA_MARKER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_SPARE_AREA_MARKER_OFST)) +/* The address of the ALT_NAND_CFG_DEVICES_CONNECTED register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICES_CONNECTED_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICES_CONNECTED_OFST)) +/* The address of the ALT_NAND_CFG_DIE_MSK register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DIE_MSK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DIE_MSK_OFST)) +/* The address of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST)) +/* The address of the ALT_NAND_CFG_WR_PROTECT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_WR_PROTECT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_WR_PROTECT_OFST)) +/* The address of the ALT_NAND_CFG_RE_2_RE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RE_2_RE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RE_2_RE_OFST)) +/* The address of the ALT_NAND_CFG_POR_RST_COUNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_POR_RST_COUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_POR_RST_COUNT_OFST)) +/* The address of the ALT_NAND_CFG_WD_RST_COUNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_WD_RST_COUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_WD_RST_COUNT_OFST)) +/* The base address byte offset for the start of the ALT_NAND_CFG component. */ +#define ALT_NAND_CFG_OFST 0x0 +/* The start address of the ALT_NAND_CFG component. */ +#define ALT_NAND_CFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_CFG_OFST)) +/* The lower bound address range of the ALT_NAND_CFG component. */ +#define ALT_NAND_CFG_LB_ADDR ALT_NAND_CFG_ADDR +/* The upper bound address range of the ALT_NAND_CFG component. */ +#define ALT_NAND_CFG_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_CFG_ADDR) + 0x2b4) - 1)) + + +/* + * Register Group Instance : param + * + * Instance param of register group ALT_NAND_PARAM. + * + * + */ +/* The address of the ALT_NAND_PARAM_MANUFACTURER_ID register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_MANUFACTURER_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_MANUFACTURER_ID_OFST)) +/* The address of the ALT_NAND_PARAM_DEVICE_ID register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_DEVICE_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_ID_OFST)) +/* The address of the ALT_NAND_PARAM_DEVICE_PARAM_0 register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_PARAM_0_OFST)) +/* The address of the ALT_NAND_PARAM_DEVICE_PARAM_1 register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_PARAM_1_OFST)) +/* The address of the ALT_NAND_PARAM_DEVICE_PARAM_2 register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_PARAM_2_OFST)) +/* The address of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST)) +/* The address of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST)) +/* The address of the ALT_NAND_PARAM_REVISION register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_REVISION_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_REVISION_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_DEV_FEATURES register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_FEATURES_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_TIMING_MOD register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_TIMING_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_OFST)) +/* The address of the ALT_NAND_PARAM_FEATURES register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_FEATURES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_FEATURES_OFST)) +/* The base address byte offset for the start of the ALT_NAND_PARAM component. */ +#define ALT_NAND_PARAM_OFST 0x300 +/* The start address of the ALT_NAND_PARAM component. */ +#define ALT_NAND_PARAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_PARAM_OFST)) +/* The lower bound address range of the ALT_NAND_PARAM component. */ +#define ALT_NAND_PARAM_LB_ADDR ALT_NAND_PARAM_ADDR +/* The upper bound address range of the ALT_NAND_PARAM component. */ +#define ALT_NAND_PARAM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + 0xf4) - 1)) + + +/* + * Register Group Instance : status + * + * Instance status of register group ALT_NAND_STAT. + * + * + */ +/* The address of the ALT_NAND_STAT_TFR_MOD register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_TFR_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_TFR_MOD_OFST)) +/* The address of the ALT_NAND_STAT_INTR_STAT0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_STAT0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT0_OFST)) +/* The address of the ALT_NAND_STAT_INTR_EN0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_EN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN0_OFST)) +/* The address of the ALT_NAND_STAT_PAGE_CNT0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_PAGE_CNT0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT0_OFST)) +/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST)) +/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST)) +/* The address of the ALT_NAND_STAT_INTR_STAT1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_STAT1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT1_OFST)) +/* The address of the ALT_NAND_STAT_INTR_EN1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_EN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN1_OFST)) +/* The address of the ALT_NAND_STAT_PAGE_CNT1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_PAGE_CNT1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT1_OFST)) +/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST)) +/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST)) +/* The address of the ALT_NAND_STAT_INTR_STAT2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_STAT2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT2_OFST)) +/* The address of the ALT_NAND_STAT_INTR_EN2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_EN2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN2_OFST)) +/* The address of the ALT_NAND_STAT_PAGE_CNT2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_PAGE_CNT2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT2_OFST)) +/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST)) +/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST)) +/* The address of the ALT_NAND_STAT_INTR_STAT3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_STAT3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT3_OFST)) +/* The address of the ALT_NAND_STAT_INTR_EN3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_EN3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN3_OFST)) +/* The address of the ALT_NAND_STAT_PAGE_CNT3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_PAGE_CNT3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT3_OFST)) +/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST)) +/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST)) +/* The base address byte offset for the start of the ALT_NAND_STAT component. */ +#define ALT_NAND_STAT_OFST 0x400 +/* The start address of the ALT_NAND_STAT component. */ +#define ALT_NAND_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_STAT_OFST)) +/* The lower bound address range of the ALT_NAND_STAT component. */ +#define ALT_NAND_STAT_LB_ADDR ALT_NAND_STAT_ADDR +/* The upper bound address range of the ALT_NAND_STAT component. */ +#define ALT_NAND_STAT_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_STAT_ADDR) + 0x144) - 1)) + + +/* + * Register Group Instance : ecc + * + * Instance ecc of register group ALT_NAND_ECC. + * + * + */ +/* The address of the ALT_NAND_ECC_ECCCORINFO_B01 register for the ALT_NAND_ECC instance. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ECC_ADDR) + ALT_NAND_ECC_ECCCORINFO_B01_OFST)) +/* The address of the ALT_NAND_ECC_ECCCORINFO_B23 register for the ALT_NAND_ECC instance. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ECC_ADDR) + ALT_NAND_ECC_ECCCORINFO_B23_OFST)) +/* The base address byte offset for the start of the ALT_NAND_ECC component. */ +#define ALT_NAND_ECC_OFST 0x650 +/* The start address of the ALT_NAND_ECC component. */ +#define ALT_NAND_ECC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_ECC_OFST)) +/* The lower bound address range of the ALT_NAND_ECC component. */ +#define ALT_NAND_ECC_LB_ADDR ALT_NAND_ECC_ADDR +/* The upper bound address range of the ALT_NAND_ECC component. */ +#define ALT_NAND_ECC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_ECC_ADDR) + 0x14) - 1)) + + +/* + * Register Group Instance : dma + * + * Instance dma of register group ALT_NAND_DMA. + * + * + */ +/* The address of the ALT_NAND_DMA_DMA_EN register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_DMA_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_DMA_EN_OFST)) +/* The address of the ALT_NAND_DMA_DMA_INTR register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_DMA_INTR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_DMA_INTR_OFST)) +/* The address of the ALT_NAND_DMA_DMA_INTR_EN register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_DMA_INTR_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_DMA_INTR_EN_OFST)) +/* The address of the ALT_NAND_DMA_TGT_ERR_ADDR_LO register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_TGT_ERR_ADDR_LO_OFST)) +/* The address of the ALT_NAND_DMA_TGT_ERR_ADDR_HI register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_TGT_ERR_ADDR_HI_OFST)) +/* The address of the ALT_NAND_DMA_FLSH_BURST_LEN register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_FLSH_BURST_LEN_OFST)) +/* The address of the ALT_NAND_DMA_INTRLV register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_INTRLV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_INTRLV_OFST)) +/* The address of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST)) +/* The address of the ALT_NAND_DMA_LUN_STAT_CMD register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_LUN_STAT_CMD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_LUN_STAT_CMD_OFST)) +/* The base address byte offset for the start of the ALT_NAND_DMA component. */ +#define ALT_NAND_DMA_OFST 0x700 +/* The start address of the ALT_NAND_DMA component. */ +#define ALT_NAND_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_DMA_OFST)) +/* The lower bound address range of the ALT_NAND_DMA component. */ +#define ALT_NAND_DMA_LB_ADDR ALT_NAND_DMA_ADDR +/* The upper bound address range of the ALT_NAND_DMA component. */ +#define ALT_NAND_DMA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_DMA_ADDR) + 0xa4) - 1)) + + +/* The base address byte offset for the start of the ALT_NAND component. */ +#define ALT_NAND_OFST 0xffb80000 +/* The start address of the ALT_NAND component. */ +#define ALT_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_NAND_OFST)) +/* The lower bound address range of the ALT_NAND component. */ +#define ALT_NAND_LB_ADDR ALT_NAND_ADDR +/* The upper bound address range of the ALT_NAND component. */ +#define ALT_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_ADDR) + 0x800) - 1)) + + +/* + * Component Instance : fpgamgrdata + * + * Instance fpgamgrdata of component ALT_FPGAMGRDATA. + * + * + */ +/* The address of the ALT_FPGAMGRDATA_DATA register for the ALT_FPGAMGRDATA instance. */ +#define ALT_FPGAMGRDATA_DATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGRDATA_ADDR) + ALT_FPGAMGRDATA_DATA_OFST)) +/* The base address byte offset for the start of the ALT_FPGAMGRDATA component. */ +#define ALT_FPGAMGRDATA_OFST 0xffb90000 +/* The start address of the ALT_FPGAMGRDATA component. */ +#define ALT_FPGAMGRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_FPGAMGRDATA_OFST)) +/* The lower bound address range of the ALT_FPGAMGRDATA component. */ +#define ALT_FPGAMGRDATA_LB_ADDR ALT_FPGAMGRDATA_ADDR +/* The upper bound address range of the ALT_FPGAMGRDATA component. */ +#define ALT_FPGAMGRDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_FPGAMGRDATA_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : can0 + * + * Instance can0 of component ALT_CAN. + * + * + */ +/* + * Register Group Instance : protogrp + * + * Instance protogrp of register group ALT_CAN_PROTO. + * + * + */ +/* The address of the ALT_CAN_PROTO_CCTL register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CCTL_ADDR ALT_CAN_PROTO_CCTL_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CSTS register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CSTS_ADDR ALT_CAN_PROTO_CSTS_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CERC register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CERC_ADDR ALT_CAN_PROTO_CERC_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CBT register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CBT_ADDR ALT_CAN_PROTO_CBT_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CIR register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CIR_ADDR ALT_CAN_PROTO_CIR_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CTR register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CTR_ADDR ALT_CAN_PROTO_CTR_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CFR register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CFR_ADDR ALT_CAN_PROTO_CFR_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CRR register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CRR_ADDR ALT_CAN_PROTO_CRR_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_HWS register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_HWS_ADDR ALT_CAN_PROTO_HWS_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN0_PROTOGRP component. */ +#define ALT_CAN0_PROTOGRP_OFST 0x0 +/* The start address of the ALT_CAN0_PROTOGRP component. */ +#define ALT_CAN0_PROTOGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN0_ADDR) + ALT_CAN0_PROTOGRP_OFST)) +/* The lower bound address range of the ALT_CAN0_PROTOGRP component. */ +#define ALT_CAN0_PROTOGRP_LB_ADDR ALT_CAN0_PROTOGRP_ADDR +/* The upper bound address range of the ALT_CAN0_PROTOGRP component. */ +#define ALT_CAN0_PROTOGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_PROTOGRP_ADDR) + 0x28) - 1)) + + +/* + * Register Group Instance : msghandgrp + * + * Instance msghandgrp of register group ALT_CAN_MSGHAND. + * + * + */ +/* The address of the ALT_CAN_MSGHAND_MOTRX register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRX_ADDR ALT_CAN_MSGHAND_MOTRX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRA register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRA_ADDR ALT_CAN_MSGHAND_MOTRA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRB register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRB_ADDR ALT_CAN_MSGHAND_MOTRB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRC register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRC_ADDR ALT_CAN_MSGHAND_MOTRC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRD register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRD_ADDR ALT_CAN_MSGHAND_MOTRD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDX register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDX_ADDR ALT_CAN_MSGHAND_MONDX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDA register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDA_ADDR ALT_CAN_MSGHAND_MONDA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDB register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDB_ADDR ALT_CAN_MSGHAND_MONDB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDC register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDC_ADDR ALT_CAN_MSGHAND_MONDC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDD register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDD_ADDR ALT_CAN_MSGHAND_MONDD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPX register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPX_ADDR ALT_CAN_MSGHAND_MOIPX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPA register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPA_ADDR ALT_CAN_MSGHAND_MOIPA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPB register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPB_ADDR ALT_CAN_MSGHAND_MOIPB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPC register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPC_ADDR ALT_CAN_MSGHAND_MOIPC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPD register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPD_ADDR ALT_CAN_MSGHAND_MOIPD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALX register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALX_ADDR ALT_CAN_MSGHAND_MOVALX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALA register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALA_ADDR ALT_CAN_MSGHAND_MOVALA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALB register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALB_ADDR ALT_CAN_MSGHAND_MOVALB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALC register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALC_ADDR ALT_CAN_MSGHAND_MOVALC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALD register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALD_ADDR ALT_CAN_MSGHAND_MOVALD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN0_MSGHANDGRP component. */ +#define ALT_CAN0_MSGHANDGRP_OFST 0x84 +/* The start address of the ALT_CAN0_MSGHANDGRP component. */ +#define ALT_CAN0_MSGHANDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN0_ADDR) + ALT_CAN0_MSGHANDGRP_OFST)) +/* The lower bound address range of the ALT_CAN0_MSGHANDGRP component. */ +#define ALT_CAN0_MSGHANDGRP_LB_ADDR ALT_CAN0_MSGHANDGRP_ADDR +/* The upper bound address range of the ALT_CAN0_MSGHANDGRP component. */ +#define ALT_CAN0_MSGHANDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_MSGHANDGRP_ADDR) + 0x50) - 1)) + + +/* + * Register Group Instance : msgifgrp + * + * Instance msgifgrp of register group ALT_CAN_MSGIF. + * + * + */ +/* The address of the ALT_CAN_MSGIF_IF1CMR register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1CMR_ADDR ALT_CAN_MSGIF_IF1CMR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1MSK register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1MSK_ADDR ALT_CAN_MSGIF_IF1MSK_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1ARB register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1ARB_ADDR ALT_CAN_MSGIF_IF1ARB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1MCTR register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1MCTR_ADDR ALT_CAN_MSGIF_IF1MCTR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1DA register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1DA_ADDR ALT_CAN_MSGIF_IF1DA_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1DB register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1DB_ADDR ALT_CAN_MSGIF_IF1DB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2CMR register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2CMR_ADDR ALT_CAN_MSGIF_IF2CMR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2MSK register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2MSK_ADDR ALT_CAN_MSGIF_IF2MSK_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2ARB register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2ARB_ADDR ALT_CAN_MSGIF_IF2ARB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2MCTR register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2MCTR_ADDR ALT_CAN_MSGIF_IF2MCTR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2DA register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2DA_ADDR ALT_CAN_MSGIF_IF2DA_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2DB register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2DB_ADDR ALT_CAN_MSGIF_IF2DB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN0_MSGIFGRP component. */ +#define ALT_CAN0_MSGIFGRP_OFST 0x100 +/* The start address of the ALT_CAN0_MSGIFGRP component. */ +#define ALT_CAN0_MSGIFGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN0_ADDR) + ALT_CAN0_MSGIFGRP_OFST)) +/* The lower bound address range of the ALT_CAN0_MSGIFGRP component. */ +#define ALT_CAN0_MSGIFGRP_LB_ADDR ALT_CAN0_MSGIFGRP_ADDR +/* The upper bound address range of the ALT_CAN0_MSGIFGRP component. */ +#define ALT_CAN0_MSGIFGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_MSGIFGRP_ADDR) + 0x38) - 1)) + + +/* The base address byte offset for the start of the ALT_CAN0 component. */ +#define ALT_CAN0_OFST 0xffc00000 +/* The start address of the ALT_CAN0 component. */ +#define ALT_CAN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_CAN0_OFST)) +/* The lower bound address range of the ALT_CAN0 component. */ +#define ALT_CAN0_LB_ADDR ALT_CAN0_ADDR +/* The upper bound address range of the ALT_CAN0 component. */ +#define ALT_CAN0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_ADDR) + 0x200) - 1)) + + +/* + * Component Instance : can1 + * + * Instance can1 of component ALT_CAN. + * + * + */ +/* + * Register Group Instance : protogrp + * + * Instance protogrp of register group ALT_CAN_PROTO. + * + * + */ +/* The address of the ALT_CAN_PROTO_CCTL register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CCTL_ADDR ALT_CAN_PROTO_CCTL_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CSTS register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CSTS_ADDR ALT_CAN_PROTO_CSTS_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CERC register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CERC_ADDR ALT_CAN_PROTO_CERC_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CBT register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CBT_ADDR ALT_CAN_PROTO_CBT_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CIR register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CIR_ADDR ALT_CAN_PROTO_CIR_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CTR register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CTR_ADDR ALT_CAN_PROTO_CTR_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CFR register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CFR_ADDR ALT_CAN_PROTO_CFR_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CRR register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CRR_ADDR ALT_CAN_PROTO_CRR_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_HWS register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_HWS_ADDR ALT_CAN_PROTO_HWS_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN1_PROTOGRP component. */ +#define ALT_CAN1_PROTOGRP_OFST 0x0 +/* The start address of the ALT_CAN1_PROTOGRP component. */ +#define ALT_CAN1_PROTOGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN1_ADDR) + ALT_CAN1_PROTOGRP_OFST)) +/* The lower bound address range of the ALT_CAN1_PROTOGRP component. */ +#define ALT_CAN1_PROTOGRP_LB_ADDR ALT_CAN1_PROTOGRP_ADDR +/* The upper bound address range of the ALT_CAN1_PROTOGRP component. */ +#define ALT_CAN1_PROTOGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_PROTOGRP_ADDR) + 0x28) - 1)) + + +/* + * Register Group Instance : msghandgrp + * + * Instance msghandgrp of register group ALT_CAN_MSGHAND. + * + * + */ +/* The address of the ALT_CAN_MSGHAND_MOTRX register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRX_ADDR ALT_CAN_MSGHAND_MOTRX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRA register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRA_ADDR ALT_CAN_MSGHAND_MOTRA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRB register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRB_ADDR ALT_CAN_MSGHAND_MOTRB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRC register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRC_ADDR ALT_CAN_MSGHAND_MOTRC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRD register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRD_ADDR ALT_CAN_MSGHAND_MOTRD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDX register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDX_ADDR ALT_CAN_MSGHAND_MONDX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDA register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDA_ADDR ALT_CAN_MSGHAND_MONDA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDB register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDB_ADDR ALT_CAN_MSGHAND_MONDB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDC register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDC_ADDR ALT_CAN_MSGHAND_MONDC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDD register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDD_ADDR ALT_CAN_MSGHAND_MONDD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPX register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPX_ADDR ALT_CAN_MSGHAND_MOIPX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPA register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPA_ADDR ALT_CAN_MSGHAND_MOIPA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPB register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPB_ADDR ALT_CAN_MSGHAND_MOIPB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPC register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPC_ADDR ALT_CAN_MSGHAND_MOIPC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPD register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPD_ADDR ALT_CAN_MSGHAND_MOIPD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALX register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALX_ADDR ALT_CAN_MSGHAND_MOVALX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALA register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALA_ADDR ALT_CAN_MSGHAND_MOVALA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALB register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALB_ADDR ALT_CAN_MSGHAND_MOVALB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALC register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALC_ADDR ALT_CAN_MSGHAND_MOVALC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALD register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALD_ADDR ALT_CAN_MSGHAND_MOVALD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN1_MSGHANDGRP component. */ +#define ALT_CAN1_MSGHANDGRP_OFST 0x84 +/* The start address of the ALT_CAN1_MSGHANDGRP component. */ +#define ALT_CAN1_MSGHANDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN1_ADDR) + ALT_CAN1_MSGHANDGRP_OFST)) +/* The lower bound address range of the ALT_CAN1_MSGHANDGRP component. */ +#define ALT_CAN1_MSGHANDGRP_LB_ADDR ALT_CAN1_MSGHANDGRP_ADDR +/* The upper bound address range of the ALT_CAN1_MSGHANDGRP component. */ +#define ALT_CAN1_MSGHANDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_MSGHANDGRP_ADDR) + 0x50) - 1)) + + +/* + * Register Group Instance : msgifgrp + * + * Instance msgifgrp of register group ALT_CAN_MSGIF. + * + * + */ +/* The address of the ALT_CAN_MSGIF_IF1CMR register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1CMR_ADDR ALT_CAN_MSGIF_IF1CMR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1MSK register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1MSK_ADDR ALT_CAN_MSGIF_IF1MSK_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1ARB register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1ARB_ADDR ALT_CAN_MSGIF_IF1ARB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1MCTR register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1MCTR_ADDR ALT_CAN_MSGIF_IF1MCTR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1DA register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1DA_ADDR ALT_CAN_MSGIF_IF1DA_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1DB register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1DB_ADDR ALT_CAN_MSGIF_IF1DB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2CMR register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2CMR_ADDR ALT_CAN_MSGIF_IF2CMR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2MSK register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2MSK_ADDR ALT_CAN_MSGIF_IF2MSK_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2ARB register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2ARB_ADDR ALT_CAN_MSGIF_IF2ARB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2MCTR register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2MCTR_ADDR ALT_CAN_MSGIF_IF2MCTR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2DA register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2DA_ADDR ALT_CAN_MSGIF_IF2DA_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2DB register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2DB_ADDR ALT_CAN_MSGIF_IF2DB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN1_MSGIFGRP component. */ +#define ALT_CAN1_MSGIFGRP_OFST 0x100 +/* The start address of the ALT_CAN1_MSGIFGRP component. */ +#define ALT_CAN1_MSGIFGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN1_ADDR) + ALT_CAN1_MSGIFGRP_OFST)) +/* The lower bound address range of the ALT_CAN1_MSGIFGRP component. */ +#define ALT_CAN1_MSGIFGRP_LB_ADDR ALT_CAN1_MSGIFGRP_ADDR +/* The upper bound address range of the ALT_CAN1_MSGIFGRP component. */ +#define ALT_CAN1_MSGIFGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_MSGIFGRP_ADDR) + 0x38) - 1)) + + +/* The base address byte offset for the start of the ALT_CAN1 component. */ +#define ALT_CAN1_OFST 0xffc01000 +/* The start address of the ALT_CAN1 component. */ +#define ALT_CAN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_CAN1_OFST)) +/* The lower bound address range of the ALT_CAN1 component. */ +#define ALT_CAN1_LB_ADDR ALT_CAN1_ADDR +/* The upper bound address range of the ALT_CAN1 component. */ +#define ALT_CAN1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_ADDR) + 0x200) - 1)) + + +/* + * Component Instance : uart0 + * + * Instance uart0 of component ALT_UART. + * + * + */ +/* The address of the ALT_UART_RBR_THR_DLL register for the ALT_UART0 instance. */ +#define ALT_UART0_RBR_THR_DLL_ADDR ALT_UART_RBR_THR_DLL_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_IER_DLH register for the ALT_UART0 instance. */ +#define ALT_UART0_IER_DLH_ADDR ALT_UART_IER_DLH_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_IIR register for the ALT_UART0 instance. */ +#define ALT_UART0_IIR_ADDR ALT_UART_IIR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_FCR register for the ALT_UART0 instance. */ +#define ALT_UART0_FCR_ADDR ALT_UART_FCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_LCR register for the ALT_UART0 instance. */ +#define ALT_UART0_LCR_ADDR ALT_UART_LCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_MCR register for the ALT_UART0 instance. */ +#define ALT_UART0_MCR_ADDR ALT_UART_MCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_LSR register for the ALT_UART0 instance. */ +#define ALT_UART0_LSR_ADDR ALT_UART_LSR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_MSR register for the ALT_UART0 instance. */ +#define ALT_UART0_MSR_ADDR ALT_UART_MSR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SCR register for the ALT_UART0 instance. */ +#define ALT_UART0_SCR_ADDR ALT_UART_SCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SRBR register for the ALT_UART0 instance. */ +#define ALT_UART0_SRBR_ADDR ALT_UART_SRBR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_STHR register for the ALT_UART0 instance. */ +#define ALT_UART0_STHR_ADDR ALT_UART_STHR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_FAR register for the ALT_UART0 instance. */ +#define ALT_UART0_FAR_ADDR ALT_UART_FAR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_TFR register for the ALT_UART0 instance. */ +#define ALT_UART0_TFR_ADDR ALT_UART_TFR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_RFW register for the ALT_UART0 instance. */ +#define ALT_UART0_RFW_ADDR ALT_UART_RFW_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_USR register for the ALT_UART0 instance. */ +#define ALT_UART0_USR_ADDR ALT_UART_USR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_TFL register for the ALT_UART0 instance. */ +#define ALT_UART0_TFL_ADDR ALT_UART_TFL_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_RFL register for the ALT_UART0 instance. */ +#define ALT_UART0_RFL_ADDR ALT_UART_RFL_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SRR register for the ALT_UART0 instance. */ +#define ALT_UART0_SRR_ADDR ALT_UART_SRR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SRTS register for the ALT_UART0 instance. */ +#define ALT_UART0_SRTS_ADDR ALT_UART_SRTS_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SBCR register for the ALT_UART0 instance. */ +#define ALT_UART0_SBCR_ADDR ALT_UART_SBCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SDMAM register for the ALT_UART0 instance. */ +#define ALT_UART0_SDMAM_ADDR ALT_UART_SDMAM_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SFE register for the ALT_UART0 instance. */ +#define ALT_UART0_SFE_ADDR ALT_UART_SFE_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SRT register for the ALT_UART0 instance. */ +#define ALT_UART0_SRT_ADDR ALT_UART_SRT_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_STET register for the ALT_UART0 instance. */ +#define ALT_UART0_STET_ADDR ALT_UART_STET_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_HTX register for the ALT_UART0 instance. */ +#define ALT_UART0_HTX_ADDR ALT_UART_HTX_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_DMASA register for the ALT_UART0 instance. */ +#define ALT_UART0_DMASA_ADDR ALT_UART_DMASA_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_CPR register for the ALT_UART0 instance. */ +#define ALT_UART0_CPR_ADDR ALT_UART_CPR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_UCV register for the ALT_UART0 instance. */ +#define ALT_UART0_UCV_ADDR ALT_UART_UCV_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_CTR register for the ALT_UART0 instance. */ +#define ALT_UART0_CTR_ADDR ALT_UART_CTR_ADDR(ALT_UART0_ADDR) +/* The base address byte offset for the start of the ALT_UART0 component. */ +#define ALT_UART0_OFST 0xffc02000 +/* The start address of the ALT_UART0 component. */ +#define ALT_UART0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_UART0_OFST)) +/* The lower bound address range of the ALT_UART0 component. */ +#define ALT_UART0_LB_ADDR ALT_UART0_ADDR +/* The upper bound address range of the ALT_UART0 component. */ +#define ALT_UART0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_UART0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : uart1 + * + * Instance uart1 of component ALT_UART. + * + * + */ +/* The address of the ALT_UART_RBR_THR_DLL register for the ALT_UART1 instance. */ +#define ALT_UART1_RBR_THR_DLL_ADDR ALT_UART_RBR_THR_DLL_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_IER_DLH register for the ALT_UART1 instance. */ +#define ALT_UART1_IER_DLH_ADDR ALT_UART_IER_DLH_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_IIR register for the ALT_UART1 instance. */ +#define ALT_UART1_IIR_ADDR ALT_UART_IIR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_FCR register for the ALT_UART1 instance. */ +#define ALT_UART1_FCR_ADDR ALT_UART_FCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_LCR register for the ALT_UART1 instance. */ +#define ALT_UART1_LCR_ADDR ALT_UART_LCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_MCR register for the ALT_UART1 instance. */ +#define ALT_UART1_MCR_ADDR ALT_UART_MCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_LSR register for the ALT_UART1 instance. */ +#define ALT_UART1_LSR_ADDR ALT_UART_LSR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_MSR register for the ALT_UART1 instance. */ +#define ALT_UART1_MSR_ADDR ALT_UART_MSR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SCR register for the ALT_UART1 instance. */ +#define ALT_UART1_SCR_ADDR ALT_UART_SCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SRBR register for the ALT_UART1 instance. */ +#define ALT_UART1_SRBR_ADDR ALT_UART_SRBR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_STHR register for the ALT_UART1 instance. */ +#define ALT_UART1_STHR_ADDR ALT_UART_STHR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_FAR register for the ALT_UART1 instance. */ +#define ALT_UART1_FAR_ADDR ALT_UART_FAR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_TFR register for the ALT_UART1 instance. */ +#define ALT_UART1_TFR_ADDR ALT_UART_TFR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_RFW register for the ALT_UART1 instance. */ +#define ALT_UART1_RFW_ADDR ALT_UART_RFW_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_USR register for the ALT_UART1 instance. */ +#define ALT_UART1_USR_ADDR ALT_UART_USR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_TFL register for the ALT_UART1 instance. */ +#define ALT_UART1_TFL_ADDR ALT_UART_TFL_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_RFL register for the ALT_UART1 instance. */ +#define ALT_UART1_RFL_ADDR ALT_UART_RFL_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SRR register for the ALT_UART1 instance. */ +#define ALT_UART1_SRR_ADDR ALT_UART_SRR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SRTS register for the ALT_UART1 instance. */ +#define ALT_UART1_SRTS_ADDR ALT_UART_SRTS_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SBCR register for the ALT_UART1 instance. */ +#define ALT_UART1_SBCR_ADDR ALT_UART_SBCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SDMAM register for the ALT_UART1 instance. */ +#define ALT_UART1_SDMAM_ADDR ALT_UART_SDMAM_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SFE register for the ALT_UART1 instance. */ +#define ALT_UART1_SFE_ADDR ALT_UART_SFE_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SRT register for the ALT_UART1 instance. */ +#define ALT_UART1_SRT_ADDR ALT_UART_SRT_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_STET register for the ALT_UART1 instance. */ +#define ALT_UART1_STET_ADDR ALT_UART_STET_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_HTX register for the ALT_UART1 instance. */ +#define ALT_UART1_HTX_ADDR ALT_UART_HTX_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_DMASA register for the ALT_UART1 instance. */ +#define ALT_UART1_DMASA_ADDR ALT_UART_DMASA_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_CPR register for the ALT_UART1 instance. */ +#define ALT_UART1_CPR_ADDR ALT_UART_CPR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_UCV register for the ALT_UART1 instance. */ +#define ALT_UART1_UCV_ADDR ALT_UART_UCV_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_CTR register for the ALT_UART1 instance. */ +#define ALT_UART1_CTR_ADDR ALT_UART_CTR_ADDR(ALT_UART1_ADDR) +/* The base address byte offset for the start of the ALT_UART1 component. */ +#define ALT_UART1_OFST 0xffc03000 +/* The start address of the ALT_UART1 component. */ +#define ALT_UART1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_UART1_OFST)) +/* The lower bound address range of the ALT_UART1 component. */ +#define ALT_UART1_LB_ADDR ALT_UART1_ADDR +/* The upper bound address range of the ALT_UART1 component. */ +#define ALT_UART1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_UART1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : i2c0 + * + * Instance i2c0 of component ALT_I2C. + * + * + */ +/* The address of the ALT_I2C_CON register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_TAR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SAR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_RX_TL register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_TX_TL register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_EN register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_STAT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_TXFLR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_RXFLR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C0_ADDR) +/* The base address byte offset for the start of the ALT_I2C0 component. */ +#define ALT_I2C0_OFST 0xffc04000 +/* The start address of the ALT_I2C0 component. */ +#define ALT_I2C0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C0_OFST)) +/* The lower bound address range of the ALT_I2C0 component. */ +#define ALT_I2C0_LB_ADDR ALT_I2C0_ADDR +/* The upper bound address range of the ALT_I2C0 component. */ +#define ALT_I2C0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : i2c1 + * + * Instance i2c1 of component ALT_I2C. + * + * + */ +/* The address of the ALT_I2C_CON register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_TAR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SAR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_RX_TL register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_TX_TL register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_EN register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_STAT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_TXFLR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_RXFLR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C1_ADDR) +/* The base address byte offset for the start of the ALT_I2C1 component. */ +#define ALT_I2C1_OFST 0xffc05000 +/* The start address of the ALT_I2C1 component. */ +#define ALT_I2C1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C1_OFST)) +/* The lower bound address range of the ALT_I2C1 component. */ +#define ALT_I2C1_LB_ADDR ALT_I2C1_ADDR +/* The upper bound address range of the ALT_I2C1 component. */ +#define ALT_I2C1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : i2c2 + * + * Instance i2c2 of component ALT_I2C. + * + * + */ +/* The address of the ALT_I2C_CON register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_TAR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SAR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_RX_TL register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_TX_TL register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_EN register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_STAT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_TXFLR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_RXFLR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C2_ADDR) +/* The base address byte offset for the start of the ALT_I2C2 component. */ +#define ALT_I2C2_OFST 0xffc06000 +/* The start address of the ALT_I2C2 component. */ +#define ALT_I2C2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C2_OFST)) +/* The lower bound address range of the ALT_I2C2 component. */ +#define ALT_I2C2_LB_ADDR ALT_I2C2_ADDR +/* The upper bound address range of the ALT_I2C2 component. */ +#define ALT_I2C2_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C2_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : i2c3 + * + * Instance i2c3 of component ALT_I2C. + * + * + */ +/* The address of the ALT_I2C_CON register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_TAR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SAR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_RX_TL register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_TX_TL register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_EN register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_STAT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_TXFLR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_RXFLR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C3_ADDR) +/* The base address byte offset for the start of the ALT_I2C3 component. */ +#define ALT_I2C3_OFST 0xffc07000 +/* The start address of the ALT_I2C3 component. */ +#define ALT_I2C3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C3_OFST)) +/* The lower bound address range of the ALT_I2C3 component. */ +#define ALT_I2C3_LB_ADDR ALT_I2C3_ADDR +/* The upper bound address range of the ALT_I2C3 component. */ +#define ALT_I2C3_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C3_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : sptimer0 + * + * Instance sptimer0 of component ALT_TMR. + * + * + */ +/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMR1EOI register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMRSEOI register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_SPTMR0_ADDR) +/* The base address byte offset for the start of the ALT_SPTMR0 component. */ +#define ALT_SPTMR0_OFST 0xffc08000 +/* The start address of the ALT_SPTMR0 component. */ +#define ALT_SPTMR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPTMR0_OFST)) +/* The lower bound address range of the ALT_SPTMR0 component. */ +#define ALT_SPTMR0_LB_ADDR ALT_SPTMR0_ADDR +/* The upper bound address range of the ALT_SPTMR0 component. */ +#define ALT_SPTMR0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPTMR0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : sptimer1 + * + * Instance sptimer1 of component ALT_TMR. + * + * + */ +/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMR1EOI register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMRSEOI register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_SPTMR1_ADDR) +/* The base address byte offset for the start of the ALT_SPTMR1 component. */ +#define ALT_SPTMR1_OFST 0xffc09000 +/* The start address of the ALT_SPTMR1 component. */ +#define ALT_SPTMR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPTMR1_OFST)) +/* The lower bound address range of the ALT_SPTMR1 component. */ +#define ALT_SPTMR1_LB_ADDR ALT_SPTMR1_ADDR +/* The upper bound address range of the ALT_SPTMR1 component. */ +#define ALT_SPTMR1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPTMR1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : sdr + * + * Instance sdr of component ALT_SDR. + * + * + */ +/* + * Register Group Instance : ctrlgrp + * + * Instance ctrlgrp of register group ALT_SDR_CTL. + * + * + */ +/* The address of the ALT_SDR_CTL_CTLCFG register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_CTLCFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_CTLCFG_OFST)) +/* The address of the ALT_SDR_CTL_DRAMTIMING1 register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMTIMING1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING1_OFST)) +/* The address of the ALT_SDR_CTL_DRAMTIMING2 register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMTIMING2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING2_OFST)) +/* The address of the ALT_SDR_CTL_DRAMTIMING3 register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMTIMING3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING3_OFST)) +/* The address of the ALT_SDR_CTL_DRAMTIMING4 register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMTIMING4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING4_OFST)) +/* The address of the ALT_SDR_CTL_LOWPWRTIMING register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_LOWPWRTIMING_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_LOWPWRTIMING_OFST)) +/* The address of the ALT_SDR_CTL_DRAMODT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMODT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMODT_OFST)) +/* The address of the ALT_SDR_CTL_DRAMADDRW register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMADDRW_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMADDRW_OFST)) +/* The address of the ALT_SDR_CTL_DRAMIFWIDTH register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMIFWIDTH_OFST)) +/* The address of the ALT_SDR_CTL_DRAMDEVWIDTH register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMDEVWIDTH_OFST)) +/* The address of the ALT_SDR_CTL_DRAMSTS register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMSTS_OFST)) +/* The address of the ALT_SDR_CTL_DRAMINTR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMINTR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMINTR_OFST)) +/* The address of the ALT_SDR_CTL_SBECOUNT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_SBECOUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_SBECOUNT_OFST)) +/* The address of the ALT_SDR_CTL_DBECOUNT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DBECOUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DBECOUNT_OFST)) +/* The address of the ALT_SDR_CTL_ERRADDR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_ERRADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_ERRADDR_OFST)) +/* The address of the ALT_SDR_CTL_DROPCOUNT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DROPCOUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DROPCOUNT_OFST)) +/* The address of the ALT_SDR_CTL_DROPADDR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DROPADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DROPADDR_OFST)) +/* The address of the ALT_SDR_CTL_LOWPWREQ register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_LOWPWREQ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_LOWPWREQ_OFST)) +/* The address of the ALT_SDR_CTL_LOWPWRACK register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_LOWPWRACK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_LOWPWRACK_OFST)) +/* The address of the ALT_SDR_CTL_STATICCFG register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_STATICCFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_STATICCFG_OFST)) +/* The address of the ALT_SDR_CTL_CTLWIDTH register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_CTLWIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_CTLWIDTH_OFST)) +/* The address of the ALT_SDR_CTL_PORTCFG register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PORTCFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PORTCFG_OFST)) +/* The address of the ALT_SDR_CTL_FPGAPORTRST register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_FPGAPORTRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_FPGAPORTRST_OFST)) +/* The address of the ALT_SDR_CTL_PROTPORTDEFAULT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTPORTDEFAULT_OFST)) +/* The address of the ALT_SDR_CTL_PROTRULEADDR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTRULEADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULEADDR_OFST)) +/* The address of the ALT_SDR_CTL_PROTRULEID register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTRULEID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULEID_OFST)) +/* The address of the ALT_SDR_CTL_PROTRULEDATA register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTRULEDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULEDATA_OFST)) +/* The address of the ALT_SDR_CTL_PROTRULERDWR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTRULERDWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULERDWR_OFST)) +/* The address of the ALT_SDR_CTL_QOSLOWPRI register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_QOSLOWPRI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_QOSLOWPRI_OFST)) +/* The address of the ALT_SDR_CTL_QOSHIGHPRI register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_QOSHIGHPRI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_QOSHIGHPRI_OFST)) +/* The address of the ALT_SDR_CTL_QOSPRIORITYEN register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_QOSPRIORITYEN_OFST)) +/* The address of the ALT_SDR_CTL_MPPRIORITY register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_MPPRIORITY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_MPPRIORITY_OFST)) +/* The address of the ALT_SDR_CTL_REMAPPRIORITY register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_REMAPPRIORITY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_REMAPPRIORITY_OFST)) +/* + * Register Group Instance : ctrlgrp_mpweight + * + * Instance ctrlgrp_mpweight of register group ALT_SDR_CTL_MPWT. + * + * + */ +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_0_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_1_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_2_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_3_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) +/* The base address byte offset for the start of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_OFST 0xb0 +/* The start address of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_CTL_MPWEIGHT_OFST)) +/* The lower bound address range of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_LB_ADDR ALT_SDR_CTL_CTL_MPWEIGHT_ADDR +/* The upper bound address range of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) + 0x10) - 1)) + + +/* The base address byte offset for the start of the ALT_SDR_CTL component. */ +#define ALT_SDR_CTL_OFST 0x5000 +/* The start address of the ALT_SDR_CTL component. */ +#define ALT_SDR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_ADDR) + ALT_SDR_CTL_OFST)) +/* The lower bound address range of the ALT_SDR_CTL component. */ +#define ALT_SDR_CTL_LB_ADDR ALT_SDR_CTL_ADDR +/* The upper bound address range of the ALT_SDR_CTL component. */ +#define ALT_SDR_CTL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDR_CTL_ADDR) + 0x1000) - 1)) + + +/* The base address byte offset for the start of the ALT_SDR component. */ +#define ALT_SDR_OFST 0xffc20000 +/* The start address of the ALT_SDR component. */ +#define ALT_SDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SDR_OFST)) +/* The lower bound address range of the ALT_SDR component. */ +#define ALT_SDR_LB_ADDR ALT_SDR_ADDR +/* The upper bound address range of the ALT_SDR component. */ +#define ALT_SDR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDR_ADDR) + 0x20000) - 1)) + + +/* + * Component Instance : osc1timer0 + * + * Instance osc1timer0 of component ALT_TMR. + * + * + */ +/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMR1EOI register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMRSEOI register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_OSC1TMR0_ADDR) +/* The base address byte offset for the start of the ALT_OSC1TMR0 component. */ +#define ALT_OSC1TMR0_OFST 0xffd00000 +/* The start address of the ALT_OSC1TMR0 component. */ +#define ALT_OSC1TMR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_OSC1TMR0_OFST)) +/* The lower bound address range of the ALT_OSC1TMR0 component. */ +#define ALT_OSC1TMR0_LB_ADDR ALT_OSC1TMR0_ADDR +/* The upper bound address range of the ALT_OSC1TMR0 component. */ +#define ALT_OSC1TMR0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_OSC1TMR0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : osc1timer1 + * + * Instance osc1timer1 of component ALT_TMR. + * + * + */ +/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMR1EOI register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMRSEOI register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_OSC1TMR1_ADDR) +/* The base address byte offset for the start of the ALT_OSC1TMR1 component. */ +#define ALT_OSC1TMR1_OFST 0xffd01000 +/* The start address of the ALT_OSC1TMR1 component. */ +#define ALT_OSC1TMR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_OSC1TMR1_OFST)) +/* The lower bound address range of the ALT_OSC1TMR1 component. */ +#define ALT_OSC1TMR1_LB_ADDR ALT_OSC1TMR1_ADDR +/* The upper bound address range of the ALT_OSC1TMR1 component. */ +#define ALT_OSC1TMR1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_OSC1TMR1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : l4wd0 + * + * Instance l4wd0 of component ALT_L4WD. + * + * + */ +/* The address of the ALT_L4WD_CR register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_CR_ADDR ALT_L4WD_CR_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_TORR register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_TORR_ADDR ALT_L4WD_TORR_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CCVR register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_CCVR_ADDR ALT_L4WD_CCVR_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CRR register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_CRR_ADDR ALT_L4WD_CRR_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_STAT register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_STAT_ADDR ALT_L4WD_STAT_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_EOI register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_EOI_ADDR ALT_L4WD_EOI_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_MAX register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_CP_WDT_USER_TOP_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_MAX_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_CP_WDT_USER_TOP_INIT_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CD_WDT_TOP_RST register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_CD_WDT_TOP_RST_ADDR ALT_L4WD_CD_WDT_TOP_RST_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CP_WDT_CNT_RST register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_CP_WDT_CNT_RST_ADDR ALT_L4WD_CP_WDT_CNT_RST_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_COMP_PARAM_1 register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_COMP_PARAM_1_ADDR ALT_L4WD_COMP_PARAM_1_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_COMP_VER register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_COMP_VER_ADDR ALT_L4WD_COMP_VER_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_COMP_TYPE register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_COMP_TYPE_ADDR ALT_L4WD_COMP_TYPE_ADDR(ALT_L4WD0_ADDR) +/* The base address byte offset for the start of the ALT_L4WD0 component. */ +#define ALT_L4WD0_OFST 0xffd02000 +/* The start address of the ALT_L4WD0 component. */ +#define ALT_L4WD0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_L4WD0_OFST)) +/* The lower bound address range of the ALT_L4WD0 component. */ +#define ALT_L4WD0_LB_ADDR ALT_L4WD0_ADDR +/* The upper bound address range of the ALT_L4WD0 component. */ +#define ALT_L4WD0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L4WD0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : l4wd1 + * + * Instance l4wd1 of component ALT_L4WD. + * + * + */ +/* The address of the ALT_L4WD_CR register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_CR_ADDR ALT_L4WD_CR_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_TORR register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_TORR_ADDR ALT_L4WD_TORR_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CCVR register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_CCVR_ADDR ALT_L4WD_CCVR_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CRR register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_CRR_ADDR ALT_L4WD_CRR_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_STAT register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_STAT_ADDR ALT_L4WD_STAT_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_EOI register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_EOI_ADDR ALT_L4WD_EOI_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_MAX register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_CP_WDT_USER_TOP_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_MAX_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_CP_WDT_USER_TOP_INIT_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CD_WDT_TOP_RST register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_CD_WDT_TOP_RST_ADDR ALT_L4WD_CD_WDT_TOP_RST_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CP_WDT_CNT_RST register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_CP_WDT_CNT_RST_ADDR ALT_L4WD_CP_WDT_CNT_RST_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_COMP_PARAM_1 register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_COMP_PARAM_1_ADDR ALT_L4WD_COMP_PARAM_1_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_COMP_VER register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_COMP_VER_ADDR ALT_L4WD_COMP_VER_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_COMP_TYPE register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_COMP_TYPE_ADDR ALT_L4WD_COMP_TYPE_ADDR(ALT_L4WD1_ADDR) +/* The base address byte offset for the start of the ALT_L4WD1 component. */ +#define ALT_L4WD1_OFST 0xffd03000 +/* The start address of the ALT_L4WD1 component. */ +#define ALT_L4WD1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_L4WD1_OFST)) +/* The lower bound address range of the ALT_L4WD1 component. */ +#define ALT_L4WD1_LB_ADDR ALT_L4WD1_ADDR +/* The upper bound address range of the ALT_L4WD1 component. */ +#define ALT_L4WD1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L4WD1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : clkmgr + * + * Instance clkmgr of component ALT_CLKMGR. + * + * + */ +/* The address of the ALT_CLKMGR_CTL register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_CTL_OFST)) +/* The address of the ALT_CLKMGR_BYPASS register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_BYPASS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_BYPASS_OFST)) +/* The address of the ALT_CLKMGR_INTER register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_INTER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_INTER_OFST)) +/* The address of the ALT_CLKMGR_INTREN register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_INTREN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_INTREN_OFST)) +/* The address of the ALT_CLKMGR_DBCTL register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_DBCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_DBCTL_OFST)) +/* The address of the ALT_CLKMGR_STAT register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_STAT_OFST)) +/* + * Register Group Instance : mainpllgrp + * + * Instance mainpllgrp of register group ALT_CLKMGR_MAINPLL. + * + * + */ +/* The address of the ALT_CLKMGR_MAINPLL_VCO register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_VCO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_VCO_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MISC register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MISC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MISC_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MPUCLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MPUCLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MAINCLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINCLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_DBGATCLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_DBGATCLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MAINQSPICLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_EN register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_EN_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MAINDIV register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINDIV_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_DBGDIV register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_DBGDIV_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_TRACEDIV register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_TRACEDIV_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_L4SRC register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_L4SRC_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_STAT register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_STAT_OFST)) +/* The base address byte offset for the start of the ALT_CLKMGR_MAINPLL component. */ +#define ALT_CLKMGR_MAINPLL_OFST 0x40 +/* The start address of the ALT_CLKMGR_MAINPLL component. */ +#define ALT_CLKMGR_MAINPLL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_MAINPLL_OFST)) +/* The lower bound address range of the ALT_CLKMGR_MAINPLL component. */ +#define ALT_CLKMGR_MAINPLL_LB_ADDR ALT_CLKMGR_MAINPLL_ADDR +/* The upper bound address range of the ALT_CLKMGR_MAINPLL component. */ +#define ALT_CLKMGR_MAINPLL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + 0x40) - 1)) + + +/* + * Register Group Instance : perpllgrp + * + * Instance perpllgrp of register group ALT_CLKMGR_PERPLL. + * + * + */ +/* The address of the ALT_CLKMGR_PERPLL_VCO register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_VCO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_VCO_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_MISC register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_MISC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_MISC_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_EMAC0CLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_EMAC0CLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_EMAC1CLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_EMAC1CLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_PERQSPICLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_PERQSPICLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_PERBASECLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_PERBASECLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_S2FUSER1CLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_EN register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_EN_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_DIV register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_DIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_DIV_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_GPIODIV register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_GPIODIV_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_SRC register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_SRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_SRC_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_STAT register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_STAT_OFST)) +/* The base address byte offset for the start of the ALT_CLKMGR_PERPLL component. */ +#define ALT_CLKMGR_PERPLL_OFST 0x80 +/* The start address of the ALT_CLKMGR_PERPLL component. */ +#define ALT_CLKMGR_PERPLL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_PERPLL_OFST)) +/* The lower bound address range of the ALT_CLKMGR_PERPLL component. */ +#define ALT_CLKMGR_PERPLL_LB_ADDR ALT_CLKMGR_PERPLL_ADDR +/* The upper bound address range of the ALT_CLKMGR_PERPLL component. */ +#define ALT_CLKMGR_PERPLL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + 0x40) - 1)) + + +/* + * Register Group Instance : sdrpllgrp + * + * Instance sdrpllgrp of register group ALT_CLKMGR_SDRPLL. + * + * + */ +/* The address of the ALT_CLKMGR_SDRPLL_VCO register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_VCO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_VCO_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_CTL register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_CTL_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_DDRDQSCLK register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_DDRDQCLK register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_EN register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_EN_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_STAT register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_STAT_OFST)) +/* The base address byte offset for the start of the ALT_CLKMGR_SDRPLL component. */ +#define ALT_CLKMGR_SDRPLL_OFST 0xc0 +/* The start address of the ALT_CLKMGR_SDRPLL component. */ +#define ALT_CLKMGR_SDRPLL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_SDRPLL_OFST)) +/* The lower bound address range of the ALT_CLKMGR_SDRPLL component. */ +#define ALT_CLKMGR_SDRPLL_LB_ADDR ALT_CLKMGR_SDRPLL_ADDR +/* The upper bound address range of the ALT_CLKMGR_SDRPLL component. */ +#define ALT_CLKMGR_SDRPLL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + 0x20) - 1)) + + +/* The base address byte offset for the start of the ALT_CLKMGR component. */ +#define ALT_CLKMGR_OFST 0xffd04000 +/* The start address of the ALT_CLKMGR component. */ +#define ALT_CLKMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_CLKMGR_OFST)) +/* The lower bound address range of the ALT_CLKMGR component. */ +#define ALT_CLKMGR_LB_ADDR ALT_CLKMGR_ADDR +/* The upper bound address range of the ALT_CLKMGR component. */ +#define ALT_CLKMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_ADDR) + 0x200) - 1)) + + +/* + * Component Instance : rstmgr + * + * Instance rstmgr of component ALT_RSTMGR. + * + * + */ +/* The address of the ALT_RSTMGR_STAT register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_STAT_OFST)) +/* The address of the ALT_RSTMGR_CTL register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_CTL_OFST)) +/* The address of the ALT_RSTMGR_COUNTS register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_COUNTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_COUNTS_OFST)) +/* The address of the ALT_RSTMGR_MPUMODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_MPUMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_MPUMODRST_OFST)) +/* The address of the ALT_RSTMGR_PERMODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_PERMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_PERMODRST_OFST)) +/* The address of the ALT_RSTMGR_PER2MODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_PER2MODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_PER2MODRST_OFST)) +/* The address of the ALT_RSTMGR_BRGMODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_BRGMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_BRGMODRST_OFST)) +/* The address of the ALT_RSTMGR_MISCMODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_MISCMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_MISCMODRST_OFST)) +/* The base address byte offset for the start of the ALT_RSTMGR component. */ +#define ALT_RSTMGR_OFST 0xffd05000 +/* The start address of the ALT_RSTMGR component. */ +#define ALT_RSTMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_RSTMGR_OFST)) +/* The lower bound address range of the ALT_RSTMGR component. */ +#define ALT_RSTMGR_LB_ADDR ALT_RSTMGR_ADDR +/* The upper bound address range of the ALT_RSTMGR component. */ +#define ALT_RSTMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_RSTMGR_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : sysmgr + * + * Instance sysmgr of component ALT_SYSMGR. + * + * + */ +/* The address of the ALT_SYSMGR_SILICONID1 register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_SILICONID1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SILICONID1_OFST)) +/* The address of the ALT_SYSMGR_SILICONID2 register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_SILICONID2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SILICONID2_OFST)) +/* The address of the ALT_SYSMGR_WDDBG register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_WDDBG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_WDDBG_OFST)) +/* The address of the ALT_SYSMGR_BOOT register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_BOOT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_BOOT_OFST)) +/* The address of the ALT_SYSMGR_HPSINFO register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_HPSINFO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_HPSINFO_OFST)) +/* The address of the ALT_SYSMGR_PARITYINJ register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_PARITYINJ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_PARITYINJ_OFST)) +/* + * Register Group Instance : fpgaintfgrp + * + * Instance fpgaintfgrp of register group ALT_SYSMGR_FPGAINTF. + * + * + */ +/* The address of the ALT_SYSMGR_FPGAINTF_GBL register for the ALT_SYSMGR_FPGAINTF instance. */ +#define ALT_SYSMGR_FPGAINTF_GBL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + ALT_SYSMGR_FPGAINTF_GBL_OFST)) +/* The address of the ALT_SYSMGR_FPGAINTF_INDIV register for the ALT_SYSMGR_FPGAINTF instance. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + ALT_SYSMGR_FPGAINTF_INDIV_OFST)) +/* The address of the ALT_SYSMGR_FPGAINTF_MODULE register for the ALT_SYSMGR_FPGAINTF instance. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + ALT_SYSMGR_FPGAINTF_MODULE_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_FPGAINTF component. */ +#define ALT_SYSMGR_FPGAINTF_OFST 0x20 +/* The start address of the ALT_SYSMGR_FPGAINTF component. */ +#define ALT_SYSMGR_FPGAINTF_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_FPGAINTF_OFST)) +/* The lower bound address range of the ALT_SYSMGR_FPGAINTF component. */ +#define ALT_SYSMGR_FPGAINTF_LB_ADDR ALT_SYSMGR_FPGAINTF_ADDR +/* The upper bound address range of the ALT_SYSMGR_FPGAINTF component. */ +#define ALT_SYSMGR_FPGAINTF_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + 0x10) - 1)) + + +/* + * Register Group Instance : scanmgrgrp + * + * Instance scanmgrgrp of register group ALT_SYSMGR_SCANMGR. + * + * + */ +/* The address of the ALT_SYSMGR_SCANMGR_CTL register for the ALT_SYSMGR_SCANMGR instance. */ +#define ALT_SYSMGR_SCANMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_SCANMGR_ADDR) + ALT_SYSMGR_SCANMGR_CTL_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_SCANMGR component. */ +#define ALT_SYSMGR_SCANMGR_OFST 0x30 +/* The start address of the ALT_SYSMGR_SCANMGR component. */ +#define ALT_SYSMGR_SCANMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SCANMGR_OFST)) +/* The lower bound address range of the ALT_SYSMGR_SCANMGR component. */ +#define ALT_SYSMGR_SCANMGR_LB_ADDR ALT_SYSMGR_SCANMGR_ADDR +/* The upper bound address range of the ALT_SYSMGR_SCANMGR component. */ +#define ALT_SYSMGR_SCANMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_SCANMGR_ADDR) + 0x4) - 1)) + + +/* + * Register Group Instance : frzctrl + * + * Instance frzctrl of register group ALT_SYSMGR_FRZCTL. + * + * + */ +/* The address of the ALT_SYSMGR_FRZCTL_VIOCTL register for the ALT_SYSMGR_FRZCTL instance. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_VIOCTL_OFST)) +/* The address of the ALT_SYSMGR_FRZCTL_HIOCTL register for the ALT_SYSMGR_FRZCTL instance. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_HIOCTL_OFST)) +/* The address of the ALT_SYSMGR_FRZCTL_SRC register for the ALT_SYSMGR_FRZCTL instance. */ +#define ALT_SYSMGR_FRZCTL_SRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_SRC_OFST)) +/* The address of the ALT_SYSMGR_FRZCTL_HWCTL register for the ALT_SYSMGR_FRZCTL instance. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_HWCTL_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_FRZCTL component. */ +#define ALT_SYSMGR_FRZCTL_OFST 0x40 +/* The start address of the ALT_SYSMGR_FRZCTL component. */ +#define ALT_SYSMGR_FRZCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_FRZCTL_OFST)) +/* The lower bound address range of the ALT_SYSMGR_FRZCTL component. */ +#define ALT_SYSMGR_FRZCTL_LB_ADDR ALT_SYSMGR_FRZCTL_ADDR +/* The upper bound address range of the ALT_SYSMGR_FRZCTL component. */ +#define ALT_SYSMGR_FRZCTL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + 0x20) - 1)) + + +/* + * Register Group Instance : emacgrp + * + * Instance emacgrp of register group ALT_SYSMGR_EMAC. + * + * + */ +/* The address of the ALT_SYSMGR_EMAC_CTL register for the ALT_SYSMGR_EMAC instance. */ +#define ALT_SYSMGR_EMAC_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_EMAC_ADDR) + ALT_SYSMGR_EMAC_CTL_OFST)) +/* The address of the ALT_SYSMGR_EMAC_L3MST register for the ALT_SYSMGR_EMAC instance. */ +#define ALT_SYSMGR_EMAC_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_EMAC_ADDR) + ALT_SYSMGR_EMAC_L3MST_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_EMAC component. */ +#define ALT_SYSMGR_EMAC_OFST 0x60 +/* The start address of the ALT_SYSMGR_EMAC component. */ +#define ALT_SYSMGR_EMAC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_EMAC_OFST)) +/* The lower bound address range of the ALT_SYSMGR_EMAC component. */ +#define ALT_SYSMGR_EMAC_LB_ADDR ALT_SYSMGR_EMAC_ADDR +/* The upper bound address range of the ALT_SYSMGR_EMAC component. */ +#define ALT_SYSMGR_EMAC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_EMAC_ADDR) + 0x10) - 1)) + + +/* + * Register Group Instance : dmagrp + * + * Instance dmagrp of register group ALT_SYSMGR_DMA. + * + * + */ +/* The address of the ALT_SYSMGR_DMA_CTL register for the ALT_SYSMGR_DMA instance. */ +#define ALT_SYSMGR_DMA_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_DMA_ADDR) + ALT_SYSMGR_DMA_CTL_OFST)) +/* The address of the ALT_SYSMGR_DMA_PERSECURITY register for the ALT_SYSMGR_DMA instance. */ +#define ALT_SYSMGR_DMA_PERSECURITY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_DMA_ADDR) + ALT_SYSMGR_DMA_PERSECURITY_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_DMA component. */ +#define ALT_SYSMGR_DMA_OFST 0x70 +/* The start address of the ALT_SYSMGR_DMA component. */ +#define ALT_SYSMGR_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_DMA_OFST)) +/* The lower bound address range of the ALT_SYSMGR_DMA component. */ +#define ALT_SYSMGR_DMA_LB_ADDR ALT_SYSMGR_DMA_ADDR +/* The upper bound address range of the ALT_SYSMGR_DMA component. */ +#define ALT_SYSMGR_DMA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_DMA_ADDR) + 0x8) - 1)) + + +/* + * Register Group Instance : iswgrp + * + * Instance iswgrp of register group ALT_SYSMGR_ISW. + * + * + */ +/* The address of the ALT_SYSMGR_ISW_HANDOFF register for the ALT_SYSMGR_ISW instance. */ +#define ALT_SYSMGR_ISW_HANDOFF_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ISW_ADDR) + ALT_SYSMGR_ISW_HANDOFF_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_ISW component. */ +#define ALT_SYSMGR_ISW_OFST 0x80 +/* The start address of the ALT_SYSMGR_ISW component. */ +#define ALT_SYSMGR_ISW_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ISW_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ISW component. */ +#define ALT_SYSMGR_ISW_LB_ADDR ALT_SYSMGR_ISW_ADDR +/* The upper bound address range of the ALT_SYSMGR_ISW component. */ +#define ALT_SYSMGR_ISW_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ISW_ADDR) + 0x20) - 1)) + + +/* + * Register Group Instance : romcodegrp + * + * Instance romcodegrp of register group ALT_SYSMGR_ROMCODE. + * + * + */ +/* The address of the ALT_SYSMGR_ROMCODE_CTL register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_CTL_OFST)) +/* The address of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST)) +/* The address of the ALT_SYSMGR_ROMCODE_INITSWSTATE register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_INITSWSTATE_OFST)) +/* The address of the ALT_SYSMGR_ROMCODE_INITSWLASTLD register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_INITSWLASTLD_OFST)) +/* The address of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_OFST)) +/* + * Register Group Instance : romcodegrp_warmramgrp + * + * Instance romcodegrp_warmramgrp of register group ALT_SYSMGR_ROMCODE_WARMRAM. + * + * + */ +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_EN_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_EN_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_DATASTART_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_LEN_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_LEN_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_EXECUTION_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_CRC_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_CRC_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The base address byte offset for the start of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_OFST 0x20 +/* The start address of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_LB_ADDR ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR +/* The upper bound address range of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) + 0x20) - 1)) + + +/* The base address byte offset for the start of the ALT_SYSMGR_ROMCODE component. */ +#define ALT_SYSMGR_ROMCODE_OFST 0xc0 +/* The start address of the ALT_SYSMGR_ROMCODE component. */ +#define ALT_SYSMGR_ROMCODE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ROMCODE_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ROMCODE component. */ +#define ALT_SYSMGR_ROMCODE_LB_ADDR ALT_SYSMGR_ROMCODE_ADDR +/* The upper bound address range of the ALT_SYSMGR_ROMCODE component. */ +#define ALT_SYSMGR_ROMCODE_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + 0x40) - 1)) + + +/* + * Register Group Instance : romhwgrp + * + * Instance romhwgrp of register group ALT_SYSMGR_ROMHW. + * + * + */ +/* The address of the ALT_SYSMGR_ROMHW_CTL register for the ALT_SYSMGR_ROMHW instance. */ +#define ALT_SYSMGR_ROMHW_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMHW_ADDR) + ALT_SYSMGR_ROMHW_CTL_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_ROMHW component. */ +#define ALT_SYSMGR_ROMHW_OFST 0x100 +/* The start address of the ALT_SYSMGR_ROMHW component. */ +#define ALT_SYSMGR_ROMHW_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ROMHW_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ROMHW component. */ +#define ALT_SYSMGR_ROMHW_LB_ADDR ALT_SYSMGR_ROMHW_ADDR +/* The upper bound address range of the ALT_SYSMGR_ROMHW component. */ +#define ALT_SYSMGR_ROMHW_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ROMHW_ADDR) + 0x4) - 1)) + + +/* + * Register Group Instance : sdmmcgrp + * + * Instance sdmmcgrp of register group ALT_SYSMGR_SDMMC. + * + * + */ +/* The address of the ALT_SYSMGR_SDMMC_CTL register for the ALT_SYSMGR_SDMMC instance. */ +#define ALT_SYSMGR_SDMMC_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_SDMMC_ADDR) + ALT_SYSMGR_SDMMC_CTL_OFST)) +/* The address of the ALT_SYSMGR_SDMMC_L3MST register for the ALT_SYSMGR_SDMMC instance. */ +#define ALT_SYSMGR_SDMMC_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_SDMMC_ADDR) + ALT_SYSMGR_SDMMC_L3MST_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_SDMMC component. */ +#define ALT_SYSMGR_SDMMC_OFST 0x108 +/* The start address of the ALT_SYSMGR_SDMMC component. */ +#define ALT_SYSMGR_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SDMMC_OFST)) +/* The lower bound address range of the ALT_SYSMGR_SDMMC component. */ +#define ALT_SYSMGR_SDMMC_LB_ADDR ALT_SYSMGR_SDMMC_ADDR +/* The upper bound address range of the ALT_SYSMGR_SDMMC component. */ +#define ALT_SYSMGR_SDMMC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_SDMMC_ADDR) + 0x8) - 1)) + + +/* + * Register Group Instance : nandgrp + * + * Instance nandgrp of register group ALT_SYSMGR_NAND. + * + * + */ +/* The address of the ALT_SYSMGR_NAND_BOOTSTRAP register for the ALT_SYSMGR_NAND instance. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_NAND_ADDR) + ALT_SYSMGR_NAND_BOOTSTRAP_OFST)) +/* The address of the ALT_SYSMGR_NAND_L3MST register for the ALT_SYSMGR_NAND instance. */ +#define ALT_SYSMGR_NAND_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_NAND_ADDR) + ALT_SYSMGR_NAND_L3MST_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_NAND component. */ +#define ALT_SYSMGR_NAND_OFST 0x110 +/* The start address of the ALT_SYSMGR_NAND component. */ +#define ALT_SYSMGR_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_NAND_OFST)) +/* The lower bound address range of the ALT_SYSMGR_NAND component. */ +#define ALT_SYSMGR_NAND_LB_ADDR ALT_SYSMGR_NAND_ADDR +/* The upper bound address range of the ALT_SYSMGR_NAND component. */ +#define ALT_SYSMGR_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_NAND_ADDR) + 0x8) - 1)) + + +/* + * Register Group Instance : usbgrp + * + * Instance usbgrp of register group ALT_SYSMGR_USB. + * + * + */ +/* The address of the ALT_SYSMGR_USB_L3MST register for the ALT_SYSMGR_USB instance. */ +#define ALT_SYSMGR_USB_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_USB_ADDR) + ALT_SYSMGR_USB_L3MST_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_USB component. */ +#define ALT_SYSMGR_USB_OFST 0x118 +/* The start address of the ALT_SYSMGR_USB component. */ +#define ALT_SYSMGR_USB_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_USB_OFST)) +/* The lower bound address range of the ALT_SYSMGR_USB component. */ +#define ALT_SYSMGR_USB_LB_ADDR ALT_SYSMGR_USB_ADDR +/* The upper bound address range of the ALT_SYSMGR_USB component. */ +#define ALT_SYSMGR_USB_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_USB_ADDR) + 0x4) - 1)) + + +/* + * Register Group Instance : eccgrp + * + * Instance eccgrp of register group ALT_SYSMGR_ECC. + * + * + */ +/* The address of the ALT_SYSMGR_ECC_L2 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_L2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_L2_OFST)) +/* The address of the ALT_SYSMGR_ECC_OCRAM register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_OCRAM_OFST)) +/* The address of the ALT_SYSMGR_ECC_USB0 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_USB0_OFST)) +/* The address of the ALT_SYSMGR_ECC_USB1 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_USB1_OFST)) +/* The address of the ALT_SYSMGR_ECC_EMAC0 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_EMAC0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_EMAC0_OFST)) +/* The address of the ALT_SYSMGR_ECC_EMAC1 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_EMAC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_EMAC1_OFST)) +/* The address of the ALT_SYSMGR_ECC_DMA register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_DMA_OFST)) +/* The address of the ALT_SYSMGR_ECC_CAN0 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_CAN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_CAN0_OFST)) +/* The address of the ALT_SYSMGR_ECC_CAN1 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_CAN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_CAN1_OFST)) +/* The address of the ALT_SYSMGR_ECC_NAND register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_NAND_OFST)) +/* The address of the ALT_SYSMGR_ECC_QSPI register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_QSPI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_QSPI_OFST)) +/* The address of the ALT_SYSMGR_ECC_SDMMC register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_SDMMC_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_ECC component. */ +#define ALT_SYSMGR_ECC_OFST 0x140 +/* The start address of the ALT_SYSMGR_ECC component. */ +#define ALT_SYSMGR_ECC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ECC_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ECC component. */ +#define ALT_SYSMGR_ECC_LB_ADDR ALT_SYSMGR_ECC_ADDR +/* The upper bound address range of the ALT_SYSMGR_ECC component. */ +#define ALT_SYSMGR_ECC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + 0x40) - 1)) + + +/* + * Register Group Instance : pinmuxgrp + * + * Instance pinmuxgrp of register group ALT_SYSMGR_PINMUX. + * + * + */ +/* The address of the ALT_SYSMGR_PINMUX_EMACIO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO12 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO12_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO13 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO13_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO14 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO14_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO15 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO15_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO16 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO16_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO17 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO17_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO18 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO18_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO19 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO19_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO12 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO12_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO13 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO13_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO14 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO14_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO15 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO15_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO16 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO16_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO17 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO17_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO18 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO18_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO19 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO19_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO20 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO20_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO21 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO21_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO22 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO22_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO23 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO23_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO24 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO24_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO25 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO25_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO26 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO26_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO27 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO27_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO28 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO28_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO29 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO29_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO30 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO30_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO31 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO31_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO12 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO12_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO13 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO13_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO14 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO14_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO15 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO15_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO16 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO16_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO17 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO17_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO18 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO18_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO19 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO19_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO20 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO20_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO21 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO21_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX48 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX48_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX49 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX49_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX50 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX50_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX51 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX51_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX52 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX52_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX53 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX53_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX54 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX54_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX55 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX55_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX56 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX56_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX57 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX57_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX58 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX58_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX59 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX59_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX60 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX60_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX61 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX61_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX62 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX62_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX63 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX63_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX64 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX64_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX65 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX65_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX66 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX66_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX67 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX67_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX68 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX68_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX69 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX69_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX70 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX70_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX12 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX12_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX13 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX13_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX14 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX14_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX15 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX15_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX16 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX16_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX17 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX17_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX18 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX18_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX19 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX19_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX20 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX20_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX21 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX21_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX22 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX22_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX23 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX23_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX24 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX24_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX25 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX25_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX26 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX26_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX27 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX27_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX28 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX28_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX29 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX29_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX30 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX30_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX31 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX31_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX32 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX32_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX33 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX33_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX34 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX34_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX35 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX35_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX36 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX36_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX37 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX37_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX38 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX38_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX39 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX39_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX40 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX40_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX41 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX41_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX42 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX42_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX43 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX43_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX44 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX44_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX45 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX45_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX46 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX46_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX47 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX47_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX48 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX48_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX49 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX49_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX50 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX50_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX51 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX51_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX52 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX52_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX53 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX53_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX54 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX54_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX55 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX55_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX56 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX56_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX57 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX57_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX58 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX58_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX59 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX59_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX60 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX60_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX61 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX61_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX62 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX62_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX63 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX63_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX64 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX64_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX65 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX65_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX66 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX66_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX67 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX67_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX68 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX68_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX69 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX69_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX70 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX70_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_NANDUSEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_NANDUSEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_RGMII1USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_I2C0USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C0USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_RGMII0USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_I2C3USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C3USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_I2C2USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C2USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_I2C1USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C1USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_SPIM1USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_SPIM0USEFPGA_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_PINMUX component. */ +#define ALT_SYSMGR_PINMUX_OFST 0x400 +/* The start address of the ALT_SYSMGR_PINMUX component. */ +#define ALT_SYSMGR_PINMUX_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_PINMUX_OFST)) +/* The lower bound address range of the ALT_SYSMGR_PINMUX component. */ +#define ALT_SYSMGR_PINMUX_LB_ADDR ALT_SYSMGR_PINMUX_ADDR +/* The upper bound address range of the ALT_SYSMGR_PINMUX component. */ +#define ALT_SYSMGR_PINMUX_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + 0x400) - 1)) + + +/* The base address byte offset for the start of the ALT_SYSMGR component. */ +#define ALT_SYSMGR_OFST 0xffd08000 +/* The start address of the ALT_SYSMGR component. */ +#define ALT_SYSMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SYSMGR_OFST)) +/* The lower bound address range of the ALT_SYSMGR component. */ +#define ALT_SYSMGR_LB_ADDR ALT_SYSMGR_ADDR +/* The upper bound address range of the ALT_SYSMGR component. */ +#define ALT_SYSMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ADDR) + 0x4000) - 1)) + + +/* + * Component Instance : dmanonsecure + * + * Instance dmanonsecure of component ALT_DMANONSECURE. + * + * + */ +/* The address of the ALT_DMANONSECURE_REG register for the ALT_DMANONSECURE instance. */ +#define ALT_DMANONSECURE_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_DMANONSECURE_ADDR) + ALT_DMANONSECURE_REG_OFST)) +/* The base address byte offset for the start of the ALT_DMANONSECURE component. */ +#define ALT_DMANONSECURE_OFST 0xffe00000 +/* The start address of the ALT_DMANONSECURE component. */ +#define ALT_DMANONSECURE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_DMANONSECURE_OFST)) +/* The lower bound address range of the ALT_DMANONSECURE component. */ +#define ALT_DMANONSECURE_LB_ADDR ALT_DMANONSECURE_ADDR +/* The upper bound address range of the ALT_DMANONSECURE component. */ +#define ALT_DMANONSECURE_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_DMANONSECURE_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : dmasecure + * + * Instance dmasecure of component ALT_DMASECURE. + * + * + */ +/* The address of the ALT_DMASECURE_REG register for the ALT_DMASECURE instance. */ +#define ALT_DMASECURE_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_DMASECURE_ADDR) + ALT_DMASECURE_REG_OFST)) +/* The base address byte offset for the start of the ALT_DMASECURE component. */ +#define ALT_DMASECURE_OFST 0xffe01000 +/* The start address of the ALT_DMASECURE component. */ +#define ALT_DMASECURE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_DMASECURE_OFST)) +/* The lower bound address range of the ALT_DMASECURE component. */ +#define ALT_DMASECURE_LB_ADDR ALT_DMASECURE_ADDR +/* The upper bound address range of the ALT_DMASECURE component. */ +#define ALT_DMASECURE_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_DMASECURE_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : spis0 + * + * Instance spis0 of component ALT_SPIS. + * + * + */ +/* The address of the ALT_SPIS_CTLR0 register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_CTLR0_ADDR ALT_SPIS_CTLR0_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_SPIENR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_SPIENR_ADDR ALT_SPIS_SPIENR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_MWCR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_MWCR_ADDR ALT_SPIS_MWCR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_TXFTLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_TXFTLR_ADDR ALT_SPIS_TXFTLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RXFTLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RXFTLR_ADDR ALT_SPIS_RXFTLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_TXFLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_TXFLR_ADDR ALT_SPIS_TXFLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RXFLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RXFLR_ADDR ALT_SPIS_RXFLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_SR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_SR_ADDR ALT_SPIS_SR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_IMR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_IMR_ADDR ALT_SPIS_IMR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_ISR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_ISR_ADDR ALT_SPIS_ISR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RISR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RISR_ADDR ALT_SPIS_RISR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_TXOICR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_TXOICR_ADDR ALT_SPIS_TXOICR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RXOICR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RXOICR_ADDR ALT_SPIS_RXOICR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RXUICR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RXUICR_ADDR ALT_SPIS_RXUICR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_ICR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_ICR_ADDR ALT_SPIS_ICR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_DMACR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_DMACR_ADDR ALT_SPIS_DMACR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_DMATDLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_DMATDLR_ADDR ALT_SPIS_DMATDLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_DMARDLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_DMARDLR_ADDR ALT_SPIS_DMARDLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_IDR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_IDR_ADDR ALT_SPIS_IDR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_SPI_VER_ID register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_SPI_VER_ID_ADDR ALT_SPIS_SPI_VER_ID_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_DR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_DR_ADDR ALT_SPIS_DR_ADDR(ALT_SPIS0_ADDR) +/* The base address byte offset for the start of the ALT_SPIS0 component. */ +#define ALT_SPIS0_OFST 0xffe02000 +/* The start address of the ALT_SPIS0 component. */ +#define ALT_SPIS0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIS0_OFST)) +/* The lower bound address range of the ALT_SPIS0 component. */ +#define ALT_SPIS0_LB_ADDR ALT_SPIS0_ADDR +/* The upper bound address range of the ALT_SPIS0 component. */ +#define ALT_SPIS0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIS0_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : spis1 + * + * Instance spis1 of component ALT_SPIS. + * + * + */ +/* The address of the ALT_SPIS_CTLR0 register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_CTLR0_ADDR ALT_SPIS_CTLR0_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_SPIENR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_SPIENR_ADDR ALT_SPIS_SPIENR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_MWCR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_MWCR_ADDR ALT_SPIS_MWCR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_TXFTLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_TXFTLR_ADDR ALT_SPIS_TXFTLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RXFTLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RXFTLR_ADDR ALT_SPIS_RXFTLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_TXFLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_TXFLR_ADDR ALT_SPIS_TXFLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RXFLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RXFLR_ADDR ALT_SPIS_RXFLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_SR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_SR_ADDR ALT_SPIS_SR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_IMR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_IMR_ADDR ALT_SPIS_IMR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_ISR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_ISR_ADDR ALT_SPIS_ISR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RISR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RISR_ADDR ALT_SPIS_RISR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_TXOICR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_TXOICR_ADDR ALT_SPIS_TXOICR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RXOICR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RXOICR_ADDR ALT_SPIS_RXOICR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RXUICR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RXUICR_ADDR ALT_SPIS_RXUICR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_ICR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_ICR_ADDR ALT_SPIS_ICR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_DMACR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_DMACR_ADDR ALT_SPIS_DMACR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_DMATDLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_DMATDLR_ADDR ALT_SPIS_DMATDLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_DMARDLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_DMARDLR_ADDR ALT_SPIS_DMARDLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_IDR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_IDR_ADDR ALT_SPIS_IDR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_SPI_VER_ID register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_SPI_VER_ID_ADDR ALT_SPIS_SPI_VER_ID_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_DR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_DR_ADDR ALT_SPIS_DR_ADDR(ALT_SPIS1_ADDR) +/* The base address byte offset for the start of the ALT_SPIS1 component. */ +#define ALT_SPIS1_OFST 0xffe03000 +/* The start address of the ALT_SPIS1 component. */ +#define ALT_SPIS1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIS1_OFST)) +/* The lower bound address range of the ALT_SPIS1 component. */ +#define ALT_SPIS1_LB_ADDR ALT_SPIS1_ADDR +/* The upper bound address range of the ALT_SPIS1 component. */ +#define ALT_SPIS1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIS1_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : spim0 + * + * Instance spim0 of component ALT_SPIM. + * + * + */ +/* The address of the ALT_SPIM_CTLR0 register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_CTLR0_ADDR ALT_SPIM_CTLR0_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_CTLR1 register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_CTLR1_ADDR ALT_SPIM_CTLR1_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_SPIENR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_SPIENR_ADDR ALT_SPIM_SPIENR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_MWCR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_MWCR_ADDR ALT_SPIM_MWCR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_SER register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_SER_ADDR ALT_SPIM_SER_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_BAUDR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_BAUDR_ADDR ALT_SPIM_BAUDR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_TXFTLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_TXFTLR_ADDR ALT_SPIM_TXFTLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RXFTLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RXFTLR_ADDR ALT_SPIM_RXFTLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_TXFLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_TXFLR_ADDR ALT_SPIM_TXFLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RXFLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RXFLR_ADDR ALT_SPIM_RXFLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_SR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_SR_ADDR ALT_SPIM_SR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_IMR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_IMR_ADDR ALT_SPIM_IMR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_ISR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_ISR_ADDR ALT_SPIM_ISR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RISR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RISR_ADDR ALT_SPIM_RISR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_TXOICR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_TXOICR_ADDR ALT_SPIM_TXOICR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RXOICR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RXOICR_ADDR ALT_SPIM_RXOICR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RXUICR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RXUICR_ADDR ALT_SPIM_RXUICR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_ICR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_ICR_ADDR ALT_SPIM_ICR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_DMACR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_DMACR_ADDR ALT_SPIM_DMACR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_DMATDLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_DMATDLR_ADDR ALT_SPIM_DMATDLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_DMARDLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_DMARDLR_ADDR ALT_SPIM_DMARDLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_IDR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_IDR_ADDR ALT_SPIM_IDR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_SPI_VER_ID register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_SPI_VER_ID_ADDR ALT_SPIM_SPI_VER_ID_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_DR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_DR_ADDR ALT_SPIM_DR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RX_SMPL_DLY register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RX_SMPL_DLY_ADDR ALT_SPIM_RX_SMPL_DLY_ADDR(ALT_SPIM0_ADDR) +/* The base address byte offset for the start of the ALT_SPIM0 component. */ +#define ALT_SPIM0_OFST 0xfff00000 +/* The start address of the ALT_SPIM0 component. */ +#define ALT_SPIM0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIM0_OFST)) +/* The lower bound address range of the ALT_SPIM0 component. */ +#define ALT_SPIM0_LB_ADDR ALT_SPIM0_ADDR +/* The upper bound address range of the ALT_SPIM0 component. */ +#define ALT_SPIM0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIM0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : spim1 + * + * Instance spim1 of component ALT_SPIM. + * + * + */ +/* The address of the ALT_SPIM_CTLR0 register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_CTLR0_ADDR ALT_SPIM_CTLR0_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_CTLR1 register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_CTLR1_ADDR ALT_SPIM_CTLR1_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_SPIENR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_SPIENR_ADDR ALT_SPIM_SPIENR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_MWCR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_MWCR_ADDR ALT_SPIM_MWCR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_SER register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_SER_ADDR ALT_SPIM_SER_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_BAUDR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_BAUDR_ADDR ALT_SPIM_BAUDR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_TXFTLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_TXFTLR_ADDR ALT_SPIM_TXFTLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RXFTLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RXFTLR_ADDR ALT_SPIM_RXFTLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_TXFLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_TXFLR_ADDR ALT_SPIM_TXFLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RXFLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RXFLR_ADDR ALT_SPIM_RXFLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_SR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_SR_ADDR ALT_SPIM_SR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_IMR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_IMR_ADDR ALT_SPIM_IMR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_ISR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_ISR_ADDR ALT_SPIM_ISR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RISR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RISR_ADDR ALT_SPIM_RISR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_TXOICR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_TXOICR_ADDR ALT_SPIM_TXOICR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RXOICR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RXOICR_ADDR ALT_SPIM_RXOICR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RXUICR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RXUICR_ADDR ALT_SPIM_RXUICR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_ICR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_ICR_ADDR ALT_SPIM_ICR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_DMACR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_DMACR_ADDR ALT_SPIM_DMACR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_DMATDLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_DMATDLR_ADDR ALT_SPIM_DMATDLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_DMARDLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_DMARDLR_ADDR ALT_SPIM_DMARDLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_IDR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_IDR_ADDR ALT_SPIM_IDR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_SPI_VER_ID register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_SPI_VER_ID_ADDR ALT_SPIM_SPI_VER_ID_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_DR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_DR_ADDR ALT_SPIM_DR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RX_SMPL_DLY register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RX_SMPL_DLY_ADDR ALT_SPIM_RX_SMPL_DLY_ADDR(ALT_SPIM1_ADDR) +/* The base address byte offset for the start of the ALT_SPIM1 component. */ +#define ALT_SPIM1_OFST 0xfff01000 +/* The start address of the ALT_SPIM1 component. */ +#define ALT_SPIM1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIM1_OFST)) +/* The lower bound address range of the ALT_SPIM1 component. */ +#define ALT_SPIM1_LB_ADDR ALT_SPIM1_ADDR +/* The upper bound address range of the ALT_SPIM1 component. */ +#define ALT_SPIM1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIM1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : scanmgr + * + * Instance scanmgr of component ALT_SCANMGR. + * + * + */ +/* The address of the ALT_SCANMGR_STAT register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_STAT_OFST)) +/* The address of the ALT_SCANMGR_EN register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_EN_OFST)) +/* The address of the ALT_SCANMGR_FIFOSINGLEBYTE register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_FIFOSINGLEBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFOSINGLEBYTE_OFST)) +/* The address of the ALT_SCANMGR_FIFODOUBLEBYTE register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_FIFODOUBLEBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFODOUBLEBYTE_OFST)) +/* The address of the ALT_SCANMGR_FIFOTRIPLEBYTE register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_FIFOTRIPLEBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFOTRIPLEBYTE_OFST)) +/* The address of the ALT_SCANMGR_FIFOQUADBYTE register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_FIFOQUADBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFOQUADBYTE_OFST)) +/* The base address byte offset for the start of the ALT_SCANMGR component. */ +#define ALT_SCANMGR_OFST 0xfff02000 +/* The start address of the ALT_SCANMGR component. */ +#define ALT_SCANMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SCANMGR_OFST)) +/* The lower bound address range of the ALT_SCANMGR component. */ +#define ALT_SCANMGR_LB_ADDR ALT_SCANMGR_ADDR +/* The upper bound address range of the ALT_SCANMGR component. */ +#define ALT_SCANMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SCANMGR_ADDR) + 0x20) - 1)) + + +/* + * Component Instance : rom + * + * Instance rom of component ALT_ROM. + * + * + */ +/* The base address byte offset for the start of the ALT_ROM component. */ +#define ALT_ROM_OFST 0xfffd0000 +/* The start address of the ALT_ROM component. */ +#define ALT_ROM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_ROM_OFST)) +/* The lower bound address range of the ALT_ROM component. */ +#define ALT_ROM_LB_ADDR ALT_ROM_ADDR +/* The upper bound address range of the ALT_ROM component. */ +#define ALT_ROM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_ROM_ADDR) + 0x10000) - 1)) + + +/* + * Component Instance : mpuscu + * + * Instance mpuscu of component ALT_MPUSCU. + * + * + */ +/* The address of the ALT_MPUSCU_REG register for the ALT_MPUSCU instance. */ +#define ALT_MPUSCU_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUSCU_ADDR) + ALT_MPUSCU_REG_OFST)) +/* The base address byte offset for the start of the ALT_MPUSCU component. */ +#define ALT_MPUSCU_OFST 0xfffec000 +/* The start address of the ALT_MPUSCU component. */ +#define ALT_MPUSCU_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_MPUSCU_OFST)) +/* The lower bound address range of the ALT_MPUSCU component. */ +#define ALT_MPUSCU_LB_ADDR ALT_MPUSCU_ADDR +/* The upper bound address range of the ALT_MPUSCU component. */ +#define ALT_MPUSCU_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_MPUSCU_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : mpul2 + * + * Instance mpul2 of component ALT_MPUL2. + * + * + */ +/* The address of the ALT_MPUL2_REG register for the ALT_MPUL2 instance. */ +#define ALT_MPUL2_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_REG_OFST)) +/* The base address byte offset for the start of the ALT_MPUL2 component. */ +#define ALT_MPUL2_OFST 0xfffef000 +/* The start address of the ALT_MPUL2 component. */ +#define ALT_MPUL2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_MPUL2_OFST)) +/* The lower bound address range of the ALT_MPUL2 component. */ +#define ALT_MPUL2_LB_ADDR ALT_MPUL2_ADDR +/* The upper bound address range of the ALT_MPUL2 component. */ +#define ALT_MPUL2_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_MPUL2_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : ocram + * + * Instance ocram of component ALT_OCRAM. + * + * + */ +/* The base address byte offset for the start of the ALT_OCRAM component. */ +#define ALT_OCRAM_OFST 0xffff0000 +/* The start address of the ALT_OCRAM component. */ +#define ALT_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_OCRAM_OFST)) +/* The lower bound address range of the ALT_OCRAM component. */ +#define ALT_OCRAM_LB_ADDR ALT_OCRAM_ADDR +/* The upper bound address range of the ALT_OCRAM component. */ +#define ALT_OCRAM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_OCRAM_ADDR) + 0x10000) - 1)) + + +/* + * Address Space : ALT_HPS + * + * Address Map + * + * Address Range | Component + * :------------------------|:----------------- + * 0x00000000 - 0xfbffffff | Undefined + * 0xfc000000 - 0xfc000003 | ALT_STM + * 0xfc000004 - 0xfeffffff | Undefined + * 0xff000000 - 0xff000003 | ALT_DAP + * 0xff000004 - 0xff1fffff | Undefined + * 0xff200000 - 0xff3fffff | ALT_LWFPGASLVS + * 0xff400000 - 0xff47ffff | ALT_LWH2F + * 0xff480000 - 0xff4fffff | Undefined + * 0xff500000 - 0xff507fff | ALT_H2F + * 0xff508000 - 0xff5fffff | Undefined + * 0xff600000 - 0xff67ffff | ALT_F2H + * 0xff680000 - 0xff6fffff | Undefined + * 0xff700000 - 0xff701fff | ALT_EMAC0 + * 0xff702000 - 0xff703fff | ALT_EMAC1 + * 0xff704000 - 0xff7043ff | ALT_SDMMC + * 0xff704400 - 0xff704fff | Undefined + * 0xff705000 - 0xff7050ff | ALT_QSPI + * 0xff705100 - 0xff705fff | Undefined + * 0xff706000 - 0xff706fff | ALT_FPGAMGR + * 0xff707000 - 0xff707fff | ALT_ACPIDMAP + * 0xff708000 - 0xff70807f | ALT_GPIO0 + * 0xff708080 - 0xff708fff | Undefined + * 0xff709000 - 0xff70907f | ALT_GPIO1 + * 0xff709080 - 0xff709fff | Undefined + * 0xff70a000 - 0xff70a07f | ALT_GPIO2 + * 0xff70a080 - 0xff7fffff | Undefined + * 0xff800000 - 0xff87ffff | ALT_L3 + * 0xff880000 - 0xff8fffff | Undefined + * 0xff900000 - 0xff9fffff | ALT_NANDDATA + * 0xffa00000 - 0xffafffff | ALT_QSPIDATA + * 0xffb00000 - 0xffb3ffff | ALT_USB0 + * 0xffb40000 - 0xffb7ffff | ALT_USB1 + * 0xffb80000 - 0xffb807ff | ALT_NAND + * 0xffb80800 - 0xffb8ffff | Undefined + * 0xffb90000 - 0xffb90003 | ALT_FPGAMGRDATA + * 0xffb90004 - 0xffbfffff | Undefined + * 0xffc00000 - 0xffc001ff | ALT_CAN0 + * 0xffc00200 - 0xffc00fff | Undefined + * 0xffc01000 - 0xffc011ff | ALT_CAN1 + * 0xffc01200 - 0xffc01fff | Undefined + * 0xffc02000 - 0xffc020ff | ALT_UART0 + * 0xffc02100 - 0xffc02fff | Undefined + * 0xffc03000 - 0xffc030ff | ALT_UART1 + * 0xffc03100 - 0xffc03fff | Undefined + * 0xffc04000 - 0xffc040ff | ALT_I2C0 + * 0xffc04100 - 0xffc04fff | Undefined + * 0xffc05000 - 0xffc050ff | ALT_I2C1 + * 0xffc05100 - 0xffc05fff | Undefined + * 0xffc06000 - 0xffc060ff | ALT_I2C2 + * 0xffc06100 - 0xffc06fff | Undefined + * 0xffc07000 - 0xffc070ff | ALT_I2C3 + * 0xffc07100 - 0xffc07fff | Undefined + * 0xffc08000 - 0xffc080ff | ALT_SPTMR0 + * 0xffc08100 - 0xffc08fff | Undefined + * 0xffc09000 - 0xffc090ff | ALT_SPTMR1 + * 0xffc09100 - 0xffc1ffff | Undefined + * 0xffc20000 - 0xffc3ffff | ALT_SDR + * 0xffc40000 - 0xffcfffff | Undefined + * 0xffd00000 - 0xffd000ff | ALT_OSC1TMR0 + * 0xffd00100 - 0xffd00fff | Undefined + * 0xffd01000 - 0xffd010ff | ALT_OSC1TMR1 + * 0xffd01100 - 0xffd01fff | Undefined + * 0xffd02000 - 0xffd020ff | ALT_L4WD0 + * 0xffd02100 - 0xffd02fff | Undefined + * 0xffd03000 - 0xffd030ff | ALT_L4WD1 + * 0xffd03100 - 0xffd03fff | Undefined + * 0xffd04000 - 0xffd041ff | ALT_CLKMGR + * 0xffd04200 - 0xffd04fff | Undefined + * 0xffd05000 - 0xffd050ff | ALT_RSTMGR + * 0xffd05100 - 0xffd07fff | Undefined + * 0xffd08000 - 0xffd0bfff | ALT_SYSMGR + * 0xffd0c000 - 0xffdfffff | Undefined + * 0xffe00000 - 0xffe00003 | ALT_DMANONSECURE + * 0xffe00004 - 0xffe00fff | Undefined + * 0xffe01000 - 0xffe01003 | ALT_DMASECURE + * 0xffe01004 - 0xffe01fff | Undefined + * 0xffe02000 - 0xffe0207f | ALT_SPIS0 + * 0xffe02080 - 0xffe02fff | Undefined + * 0xffe03000 - 0xffe0307f | ALT_SPIS1 + * 0xffe03080 - 0xffefffff | Undefined + * 0xfff00000 - 0xfff000ff | ALT_SPIM0 + * 0xfff00100 - 0xfff00fff | Undefined + * 0xfff01000 - 0xfff010ff | ALT_SPIM1 + * 0xfff01100 - 0xfff01fff | Undefined + * 0xfff02000 - 0xfff0201f | ALT_SCANMGR + * 0xfff02020 - 0xfffcffff | Undefined + * 0xfffd0000 - 0xfffdffff | ALT_ROM + * 0xfffe0000 - 0xfffebfff | Undefined + * 0xfffec000 - 0xfffec003 | ALT_MPUSCU + * 0xfffec004 - 0xfffeefff | Undefined + * 0xfffef000 - 0xfffef003 | ALT_MPUL2 + * 0xfffef004 - 0xfffeffff | Undefined + * 0xffff0000 - 0xffffffff | ALT_OCRAM + */ + +#ifdef __ASSEMBLY__ +#define ALT_CAST(type, ptr) ptr +#else /* __ASSEMBLY__ */ +#define ALT_CAST(type, ptr) ((type) (ptr)) +#endif /* __ASSEMBLY__ */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_HPS_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h new file mode 100644 index 0000000000..f6090cd0ca --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h @@ -0,0 +1,259 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + + +/*! \file Altera - ALT_SOCAL */ + +#ifndef __ALTERA_SOCAL_H__ +#define __ALTERA_SOCAL_H__ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#include +#include +#include +#else /* __cplusplus */ +#include +#include +#include +#endif /* __cplusplus */ +#endif /* __ASSEMBLY__ */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup ALT_SOCAL_UTIL SoCAL Utilities + * + * This file contains utility and support functions for the Altera SoCAL. + * @{ + */ + +#ifdef __ASSEMBLY__ +#define ALT_CAST(type, ptr) ptr +#else /* __ASSEMBLY__ */ +/*! Cast the pointer to specified pointer type. + * + * Note: This macro expands to \e ptr value only for assembler language + * targets. + * + * \param type The pointer type to cast to + * \param ptr The pointer to apply the type cast to + */ +#define ALT_CAST(type, ptr) ((type) (ptr)) +#endif /* __ASSEMBLY__ */ + +/*! + * \addtogroup ALT_SOCAL_UTIL_RW_FUNC SoCAL Memory Read/Write Utilities + * + * This section implements read and write functionality for various + * memory untis. The memory unit terms used for these functions are + * consistent with those used in the ARM Architecture Reference Manual + * ARMv7-A and ARMv7-R edition manual. The terms used for units of memory are: + * + * Unit of Memory | Abbreviation | Size in Bits + * :---------------|:-------------|:------------: + * Byte | byte | 8 + * Half Word | hword | 16 + * Word | word | 32 + * Double Word | dword | 64 + * + * @{ + */ + +/*! Write the 8 bit byte to the destination address in device memory. + * \param dest - Write destination pointer address + * \param src - 8 bit data byte to write to memory + */ +#define alt_write_byte(dest, src) (*ALT_CAST(volatile uint8_t *, (dest)) = (src)) + +/*! Read and return the 8 bit byte from the source address in device memory. + * \param src Read source pointer address + * \returns 8 bit data byte value + */ +#define alt_read_byte(src) (*ALT_CAST(volatile uint8_t *, (src))) + +/*! Write the 16 bit half word to the destination address in device memory. + * \param dest - Write destination pointer address + * \param src - 16 bit data half word to write to memory + */ +#define alt_write_hword(dest, src) (*ALT_CAST(volatile uint16_t *, (dest)) = (src)) + +/*! Read and return the 16 bit half word from the source address in device memory. + * \param src Read source pointer address + * \returns 16 bit data half word value + */ +#define alt_read_hword(src) (*ALT_CAST(volatile uint16_t *, (src))) + +/*! Write the 32 bit word to the destination address in device memory. + * \param dest - Write destination pointer address + * \param src - 32 bit data word to write to memory + */ +#define alt_write_word(dest, src) (*ALT_CAST(volatile uint32_t *, (dest)) = (src)) + +/*! Read and return the 32 bit word from the source address in device memory. + * \param src Read source pointer address + * \returns 32 bit data word value + */ +#define alt_read_word(src) (*ALT_CAST(volatile uint32_t *, (src))) + +/*! Write the 64 bit double word to the destination address in device memory. + * \param dest - Write destination pointer address + * \param src - 64 bit data double word to write to memory + */ +#define alt_write_dword(dest, src) (*ALT_CAST(volatile uint64_t *, (dest)) = (src)) + +/*! Read and return the 64 bit double word from the source address in device memory. + * \param src Read source pointer address + * \returns 64 bit data double word value + */ +#define alt_read_dword(src) (*ALT_CAST(volatile uint64_t *, (src))) + +/*! @} */ + +/*! + * \addtogroup ALT_SOCAL_UTIL_SC_FUNC SoCAL Memory Bit Set/Clr/XOR/Replace Utilities + * + * This section implements useful macros to set, clear, change, and replace + * selected bits within a word in memory or a memory-mapped register. + * @{ + * + */ + +/*! Set selected bits in the 8 bit byte at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to set in destination byte + */ +#define alt_setbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) | (bits))) + +/*! Clear selected bits in the 8 bit byte at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to clear in destination byte + */ +#define alt_clrbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) & ~(bits))) + +/*! Change or toggle selected bits in the 8 bit byte at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to change in destination byte + */ +#define alt_xorbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) ^ (bits))) + +/*! Replace selected bits in the 8 bit byte at the destination address in device memory. + * \param dest - Destination pointer address + * \param msk - Bits to replace in destination byte + * \param src - Source bits to write to cleared bits in destination byte + */ +#define alt_replbits_byte(dest, msk, src) (alt_write_byte(dest,(alt_read_byte(dest) & ~(msk)) | ((src) & (msk)))) + +/*! Set selected bits in the 16 bit halfword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to set in destination halfword + */ +#define alt_setbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) | (bits))) + +/*! Clear selected bits in the 16 bit halfword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to clear in destination halfword + */ +#define alt_clrbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) & ~(bits))) + +/*! Change or toggle selected bits in the 16 bit halfword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to change in destination halfword + */ +#define alt_xorbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) ^ (bits))) + +/*! Replace selected bits in the 16 bit halfword at the destination address in device memory. + * \param dest - Destination pointer address + * \param msk - Bits to replace in destination halfword + * \param src - Source bits to write to cleared bits in destination halfword + */ +#define alt_replbits_hword(dest, msk, src) (alt_write_hword(dest,(alt_read_hword(dest) & ~(msk)) | ((src) & (msk)))) + +/*! Set selected bits in the 32 bit word at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to set in destination word + */ +#define alt_setbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) | (bits))) + +/*! Clear selected bits in the 32 bit word at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to clear in destination word + */ +#define alt_clrbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) & ~(bits))) + +/*! Change or toggle selected bits in the 32 bit word at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to change in destination word + */ +#define alt_xorbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) ^ (bits))) + +/*! Replace selected bits in the 32 bit word at the destination address in device memory. + * \param dest - Destination pointer address + * \param msk - Bits to replace in destination word + * \param src - Source bits to write to cleared bits in destination word + */ +#define alt_replbits_word(dest, msk, src) (alt_write_word(dest,(alt_read_word(dest) & ~(msk)) | ((src) & (msk)))) + +/*! Set selected bits in the 64 bit doubleword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to set in destination doubleword + */ +#define alt_setbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) | (bits))) + +/*! Clear selected bits in the 64 bit doubleword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to clear in destination doubleword + */ +#define alt_clrbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) & ~(bits))) + +/*! Change or toggle selected bits in the 64 bit doubleword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to change in destination doubleword + */ +#define alt_xorbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) ^ (bits))) + +/*! Replace selected bits in the 64 bit doubleword at the destination address in device memory. + * \param dest - Destination pointer address + * \param msk - Bits to replace in destination doubleword + * \param src - Source bits to write to cleared bits in destination word + */ +#define alt_replbits_dword(dest, msk, src) (alt_write_dword(dest,(alt_read_dword(dest) & ~(msk)) | ((src) & (msk)))) + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_SOCAL_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/tm27.h b/bsps/arm/altera-cyclone-v/include/tm27.h new file mode 100644 index 0000000000..c17c0107b4 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/tm27.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +#endif /* __tm27_h */ diff --git a/bsps/arm/atsam/headers.am b/bsps/arm/atsam/headers.am new file mode 100644 index 0000000000..1ec34a2e69 --- /dev/null +++ b/bsps/arm/atsam/headers.am @@ -0,0 +1,269 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/atsam/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/atsam-clock-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/atsam-i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/atsam-spi.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/pin-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/power.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/sc16is752.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/spi.h + +include_libchipdir = $(includedir)/libchip +include_libchip_HEADERS = +include_libchip_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/chip.h +include_libchip_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/compiler.h + +include_libchip_includedir = $(includedir)/libchip/include +include_libchip_include_HEADERS = +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/acc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/adc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/aes.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/afe_dma.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/afec.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/chip.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/dac_dma.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/efc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/exceptions.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/flashd.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/gmac.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/gmacd.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/hsmci.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/icm.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/isi.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/iso7816_4.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/mcan.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/mcid.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/mediaLB.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/mpu.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/pio.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/pio_capture.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/pio_it.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/pmc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/pwmc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/qspi.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/qspi_dma.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/rstc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/rtc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/rtt.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sdramc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/smc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/spi.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/spi_dma.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/ssc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/supc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/tc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/timetick.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/trace.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/trng.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/twi.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/twid.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/uart.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/uart_dma.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/usart.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/usart_dma.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/usbhs.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/video.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/wdt.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/xdma_hardware_interface.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/xdmac.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/xdmad.h + +include_libchip_include_same70dir = $(includedir)/libchip/include/same70 +include_libchip_include_same70_HEADERS = +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70j19.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70j20.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70j21.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70n19.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70n20.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70n21.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70q19.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70q20.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70q21.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/system_same70.h + +include_libchip_include_same70_componentdir = $(includedir)/libchip/include/same70/component +include_libchip_include_same70_component_HEADERS = +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_acc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_aes.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_afec.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_chipid.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_dacc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_efc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_gmac.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_gpbr.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_hsmci.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_icm.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_isi.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_matrix.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_mcan.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_pwm.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_qspi.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_rstc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_rswdt.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_rtc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_rtt.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_sdramc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_smc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_spi.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_ssc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_supc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_tc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_trng.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_twihs.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_uart.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_usart.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_usbhs.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_utmi.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_wdt.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_xdmac.h + +include_libchip_include_same70_piodir = $(includedir)/libchip/include/same70/pio +include_libchip_include_same70_pio_HEADERS = +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j19.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j20.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j21.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n19.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n20.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n21.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q19.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q20.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q21.h + +include_libchip_include_sams70dir = $(includedir)/libchip/include/sams70 +include_libchip_include_sams70_HEADERS = +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70j19.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70j20.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70j21.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70n19.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70n20.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70n21.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70q19.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70q20.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70q21.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/system_sams70.h + +include_libchip_include_sams70_componentdir = $(includedir)/libchip/include/sams70/component +include_libchip_include_sams70_component_HEADERS = +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_acc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_aes.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_afec.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_chipid.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_dacc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_efc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_gpbr.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_hsmci.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_icm.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_isi.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_pio.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_pmc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_pwm.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_rstc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_rswdt.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_rtc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_rtt.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_sdramc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_smc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_spi.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_ssc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_supc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_tc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_trng.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_twihs.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_uart.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_usart.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_usbhs.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_utmi.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_wdt.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_xdmac.h + +include_libchip_include_sams70_piodir = $(includedir)/libchip/include/sams70/pio +include_libchip_include_sams70_pio_HEADERS = +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j19.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j20.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j21.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n19.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n20.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n21.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q19.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q20.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q21.h + +include_libchip_include_samv71dir = $(includedir)/libchip/include/samv71 +include_libchip_include_samv71_HEADERS = +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71j19.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71j20.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71j21.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71n19.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71n20.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71n21.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71q19.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71q20.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71q21.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/system_samv71.h + +include_libchip_include_samv71_componentdir = $(includedir)/libchip/include/samv71/component +include_libchip_include_samv71_component_HEADERS = +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_acc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_aes.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_afec.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_chipid.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_dacc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_efc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_gmac.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_gpbr.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_hsmci.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_icm.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_isi.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_matrix.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_mlb.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_pio.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_pmc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_pwm.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_qspi.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_rstc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_rswdt.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_rtc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_rtt.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_sdramc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_smc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_spi.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_ssc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_supc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_tc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_trng.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_twihs.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_uart.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_usart.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_usbhs.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_utmi.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_wdt.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_xdmac.h + +include_libchip_include_samv71_piodir = $(includedir)/libchip/include/samv71/pio +include_libchip_include_samv71_pio_HEADERS = +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j19.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j20.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j21.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n19.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n20.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n21.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q19.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q20.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q21.h diff --git a/bsps/arm/atsam/include/bsp.h b/bsps/arm/atsam/include/bsp.h new file mode 100644 index 0000000000..cd0103ad70 --- /dev/null +++ b/bsps/arm/atsam/include/bsp.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_BSP_H +#define LIBBSP_ARM_ATSAM_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (13 << 4) + +#define BSP_ARMV7M_SYSTICK_PRIORITY (14 << 4) + +uint32_t atsam_systick_frequency(void); + +#define BSP_ARMV7M_SYSTICK_FREQUENCY atsam_systick_frequency() + +struct rtems_bsdnet_ifconfig; + +int if_atsam_attach(struct rtems_bsdnet_ifconfig *config, int attaching); + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "atsam0" + +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH if_atsam_attach + +/** + * @brief Interface driver configuration. + */ +typedef struct { + /** + * @brief Maximum retries for MDIO communication. + */ + uint32_t mdio_retries; + + /** + * @brief Address of PHY. + * + * Use 0xff to search for a PHY. + */ + uint8_t phy_addr; +} if_atsam_config; + +extern char atsam_memory_dtcm_begin[]; +extern char atsam_memory_dtcm_end[]; +extern char atsam_memory_dtcm_size[]; + +extern char atsam_memory_intflash_begin[]; +extern char atsam_memory_intflash_end[]; +extern char atsam_memory_intflash_size[]; + +extern char atsam_memory_intsram_begin[]; +extern char atsam_memory_intsram_end[]; +extern char atsam_memory_intsram_size[]; + +extern char atsam_memory_itcm_begin[]; +extern char atsam_memory_itcm_end[]; +extern char atsam_memory_itcm_size[]; + +extern char atsam_memory_nocache_begin[]; +extern char atsam_memory_nocache_end[]; +extern char atsam_memory_nocache_size[]; + +extern char atsam_memory_qspiflash_begin[]; +extern char atsam_memory_qspiflash_end[]; +extern char atsam_memory_qspiflash_size[]; + +extern char atsam_memory_sdram_begin[]; +extern char atsam_memory_sdram_end[]; +extern char atsam_memory_sdram_size[]; + +void atsam_rtc_get_time(rtems_time_of_day *tod); + + + +void bsp_restart( const void *const addr ); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_BSP_H */ diff --git a/bsps/arm/atsam/include/bsp/atsam-clock-config.h b/bsps/arm/atsam/include/bsp/atsam-clock-config.h new file mode 100644 index 0000000000..396986894b --- /dev/null +++ b/bsps/arm/atsam/include/bsp/atsam-clock-config.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef ATSAM_CLOCK_CONFIG_H +#define ATSAM_CLOCK_CONFIG_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if ATSAM_CHANGE_CLOCK_FROM_SRAM != 0 +/* Note: fast_text is the simplest section to put this code into. Other + * possibilities would include creating a new section. */ +#define ATSAM_START_SRAM_SECTION BSP_FAST_TEXT_SECTION +#else +#define ATSAM_START_SRAM_SECTION +#endif + +struct atsam_clock_config { + /* Initialization value for the PMC_PLLAR. */ + uint32_t pllar_init; + /* Initialization value for the PMC_MCKR. */ + uint32_t mckr_init; + /* Resulting frequency in Hz. */ + uint32_t mck_freq; +}; + +ATSAM_START_SRAM_SECTION +extern const struct atsam_clock_config atsam_clock_config; + +#define BOARD_MCK (atsam_clock_config.mck_freq) + +struct BOARD_Sdram_Config { + uint32_t sdramc_tr; + uint32_t sdramc_cr; + uint32_t sdramc_mdr; + uint32_t sdramc_cfr1; +}; + +ATSAM_START_SRAM_SECTION +extern const struct BOARD_Sdram_Config BOARD_Sdram_Config; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ATSAM_CLOCK_CONFIG_H */ diff --git a/bsps/arm/atsam/include/bsp/atsam-i2c.h b/bsps/arm/atsam/include/bsp/atsam-i2c.h new file mode 100644 index 0000000000..7425db9f7b --- /dev/null +++ b/bsps/arm/atsam/include/bsp/atsam-i2c.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_ATSAM_I2C_H +#define LIBBSP_ARM_ATSAM_ATSAM_I2C_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define TWI_AMOUNT_PINS 2 + +typedef enum { + TX_SEND_DATA, + TX_SEND_STOP, + TX_CONT_MESSAGE_NEEDED, + RX_SEND_DATA, + RX_SEND_STOP, + RX_CONT_MESSAGE_NEEDED, + TX_RX_STOP_SENT +}transfer_state; + +typedef struct { + uint8_t status; + uint8_t *data; + bool stop_request; + uint32_t data_size; + uint32_t already_transferred; + transfer_state trans_state; +} transfer_desc; + +typedef struct { + i2c_bus base; + i2c_msg *msgs; + Twihs *regs; + transfer_desc trans_desc; + uint32_t msg_todo; + uint32_t current_msg_todo; + uint8_t *current_msg_byte; + uint32_t input_clock; + bool read; + rtems_id task_id; + rtems_vector_number irq; +} atsam_i2c_bus; + +int i2c_bus_register_atsam( + const char *bus_path, + Twihs *register_base, + rtems_vector_number irq, + const Pin pins[TWI_AMOUNT_PINS] +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_ATSAM_I2C_H */ diff --git a/bsps/arm/atsam/include/bsp/atsam-spi.h b/bsps/arm/atsam/include/bsp/atsam-spi.h new file mode 100644 index 0000000000..548dd544f4 --- /dev/null +++ b/bsps/arm/atsam/include/bsp/atsam-spi.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_ATSAM_SPI_H +#define LIBBSP_ARM_ATSAM_ATSAM_SPI_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +int spi_bus_register_atsam( + const char *bus_path, + uint8_t spi_peripheral_id, + Spi *spi_regs, + const Pin *pins, + size_t pin_count +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_ATSAM_SPI_H */ diff --git a/bsps/arm/atsam/include/bsp/i2c.h b/bsps/arm/atsam/include/bsp/i2c.h new file mode 100644 index 0000000000..1ea1204ff5 --- /dev/null +++ b/bsps/arm/atsam/include/bsp/i2c.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_I2C_H +#define LIBBSP_ARM_ATSAM_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define ATSAM_I2C_0_BUS_PATH "/dev/i2c-0" +#define ATSAM_I2C_1_BUS_PATH "/dev/i2c-1" +#define ATSAM_I2C_2_BUS_PATH "/dev/i2c-2" + +int atsam_register_i2c_0(void); + +int atsam_register_i2c_1(void); + +int atsam_register_i2c_2(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_I2C_H */ diff --git a/bsps/arm/atsam/include/bsp/irq.h b/bsps/arm/atsam/include/bsp/irq.h new file mode 100644 index 0000000000..19370e4852 --- /dev/null +++ b/bsps/arm/atsam/include/bsp/irq.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_ESV_70_IRQ_H +#define LIBBSP_ARM_ATSAM_ESV_70_IRQ_H + +#include + +#ifndef ASM + #include + #include + #include +#endif + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX 64 + +#endif /* LIBBSP_ARM_ATSAM_ESV_70_IRQ_H */ diff --git a/bsps/arm/atsam/include/bsp/pin-config.h b/bsps/arm/atsam/include/bsp/pin-config.h new file mode 100644 index 0000000000..8f4a61428f --- /dev/null +++ b/bsps/arm/atsam/include/bsp/pin-config.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_PIN_CONFIG_H +#define LIBBSP_ARM_ATSAM_PIN_CONFIG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern const Pin atsam_pin_config[]; + +extern const size_t atsam_pin_config_count; + +extern const uint32_t atsam_matrix_ccfg_sysio; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_PIN_CONFIG_H */ diff --git a/bsps/arm/atsam/include/bsp/power.h b/bsps/arm/atsam/include/bsp/power.h new file mode 100644 index 0000000000..a352386a0e --- /dev/null +++ b/bsps/arm/atsam/include/bsp/power.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_POWER_H +#define LIBBSP_ARM_ATSAM_POWER_H + +#include + +#include + +#ifdef __cplusplus +extern "C"{ +#endif /* __cplusplus */ + +/** + * @brief Status of the Low Power Support + */ +typedef enum { + /** + * @brief Used for Initialization of Handlers + */ + ATSAM_POWER_INIT, + /** + * @brief Used for Switching On of Handlers + */ + ATSAM_POWER_ON, + /** + * @brief Used for Switching Off of Handlers + */ + ATSAM_POWER_OFF +} atsam_power_state; + +/** + * @brief Control structure for power control handling + */ +typedef struct atsam_power_control { + /** + * @brief Data pointer to the handler with its desired state + */ + void (*handler)( + const struct atsam_power_control *control, + atsam_power_state state + ); + /** + * @brief Data chunk that is used by the handler + */ + union { + void *arg; + struct { + uint8_t first; + uint8_t last; + } peripherals; + } data; +} atsam_power_control; + +/** + * @brief Performs a power state change according to the state parameter. + * + * The handlers of the control table are invoked in forward order (invocation + * starts with table index zero) for the ATSAM_POWER_INIT and ATSAM_POWER_OFF + * states, otherwise the handlers are invoked in reverse order (invocation + * starts with the last table index). + * + * @param controls Table with power controls. + * @param n Count of power control table entries. + * @param state The desired power state. + * + * @code + * #include + * #include + * + * #include + * + * static atsam_power_data_rtc_driver rtc_data = { .interval = 5 }; + * + * static const atsam_power_control power_controls[] = { + * ATSAM_POWER_CLOCK_DRIVER, + * ATSAM_POWER_RTC_DRIVER(&rtc_data), + * ATSAM_POWER_SLEEP_MODE + * }; + * + * static pthread_once_t once = PTHREAD_ONCE_INIT; + * + * static void init(void) + * { + * atsam_power_change_state( + * &power_controls[0], + * RTEMS_ARRAY_SIZE(power_controls), + * ATSAM_POWER_INIT + * ); + * } + * + * void power_init(void) + * { + * pthread_once(&once, init); + * } + * + * void low_power(void) + * { + * atsam_power_change_state( + * &power_controls[0], + * RTEMS_ARRAY_SIZE(power_controls), + * ATSAM_POWER_OFF + * ); + * atsam_power_change_state( + * &power_controls[0], + * RTEMS_ARRAY_SIZE(power_controls), + * ATSAM_POWER_ON + * ); + * } + * @end + */ +void atsam_power_change_state( + const atsam_power_control *controls, + size_t n, + atsam_power_state state +); + +/** + * @brief Power handler for a set of peripherals according to the specified + * peripheral indices. + * + * For the power off state, the peripherals are enabled in the PMC. + * + * For the power on state, the peripherals are disabled in the Power Management + * Controller (PMC). + * + * @see ATSAM_POWER_PERIPHERAL(). + */ +void atsam_power_handler_peripheral( + const atsam_power_control *controls, + atsam_power_state state +); + +/** + * @brief Power handler for the clock driver. + * + * For the power off state, the system tick is disabled. + * + * For the power on state, the system tick is enabled. In case no clock driver + * is used by the application, then this may lead to a spurious interrupt + * resulting in a fatal error. + * + * @see ATSAM_POWER_CLOCK_DRIVER(). + */ +void atsam_power_handler_clock_driver( + const atsam_power_control *controls, + atsam_power_state state +); + +/** + * @brief Power handler for the RTC driver. + * + * This handler installs an interrupt handler during power support initialization. + * + * For the power off state, the RTC alarm interrupt is set up according to the + * interval of the corresponding handler data. + * + * For the power on state, the RTC alarm interrupt is disabled. + * + * @see ATSAM_POWER_RTC_DRIVER(). + */ +void atsam_power_handler_rtc_driver( + const atsam_power_control *controls, + atsam_power_state state +); + +/** + * @brief Power handler to enter the processor sleep mode. + * + * For the power off state, the processor is set into the sleep mode and issues + * a wait for interrupt instruction. + * + * @see ATSAM_POWER_SLEEP_MODE(). + */ +void atsam_power_handler_sleep_mode( + const atsam_power_control *controls, + atsam_power_state state +); + +/** + * @brief Initializer for a peripheral power support. + * + * @param f The first peripheral index. + * @param l The last peripheral index. + */ +#define ATSAM_POWER_PERIPHERAL(f, l) \ + { \ + .handler = atsam_power_handler_peripheral, \ + .data = { .peripherals = { .first = f, .last = l } } \ + } + +#define ATSAM_POWER_HANDLER(h, a) \ + { \ + .handler = h, \ + .data = { .arg = a } \ + } + +#define ATSAM_POWER_CLOCK_DRIVER \ + { .handler = atsam_power_handler_clock_driver } + +#define ATSAM_POWER_SLEEP_MODE \ + { .handler = atsam_power_handler_sleep_mode } + +/** + * @brief Data for RTC driver power support. + * + * @see ATSAM_POWER_RTC_DRIVER(). + */ +typedef struct { + /** + * @brief Interval in seconds for which the power off mode should be active. + */ + uint8_t interval; +} atsam_power_data_rtc_driver; + +/** + * @brief Initializer for RTC driver power support. + * + * @param a Pointer to RTC driver power data. + * + * @see atsam_power_data_rtc_driver. + */ +#define ATSAM_POWER_RTC_DRIVER(a) \ + { \ + .handler = atsam_power_handler_rtc_driver, \ + .data = { .arg = a } \ + } + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_POWER_H */ diff --git a/bsps/arm/atsam/include/bsp/sc16is752.h b/bsps/arm/atsam/include/bsp/sc16is752.h new file mode 100644 index 0000000000..35d298a7ed --- /dev/null +++ b/bsps/arm/atsam/include/bsp/sc16is752.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_SC16IS752_H +#define LIBBSP_ARM_ATSAM_SC16IS752_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + sc16is752_spi_context base; + Pin irq_pin; +} atsam_sc16is752_spi_context; + +/** + * @brief Creates an SPI connected SC16IS752 device. + * + * This devices uses the interrupt server, see + * rtems_interrupt_server_initialize(). + * + * The device claims the interrupt of the PIO block. + * + * @param[in] ctx The device context. May have an arbitrary content. + * @param[in] device_path The device file path for the new device. + * @param[in] mode The SC16IS752 mode. + * @param[in] input_frequency The input frequency in Hertz of the SC16IS752 + * chip. See XTAL1 and XTAL2 pins. + * @param[in] spi_path The SPI bus device path. + * @param[in] spi_chip_select The SPI chip select (starts with 0, the SPI + * driver uses SPI_ChipSelect(1 << spi_chip_select)). + * @param[in] spi_speed_hz The SPI bus speed in Hertz. + * @param[in] irq_pin The interrupt pin, e.g. { PIO_PD28, PIOD, ID_PIOD, + * PIO_INPUT, PIO_IT_LOW_LEVEL }. + * + * @return See sc16is752_spi_create(). + */ +int atsam_sc16is752_spi_create( + atsam_sc16is752_spi_context *ctx, + const char *device_path, + sc16is752_mode mode, + uint32_t input_frequency, + const char *spi_path, + uint8_t spi_chip_select, + uint32_t spi_speed_hz, + const Pin *irq_pin +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_SC16IS752_H */ diff --git a/bsps/arm/atsam/include/bsp/spi.h b/bsps/arm/atsam/include/bsp/spi.h new file mode 100644 index 0000000000..958e629ba3 --- /dev/null +++ b/bsps/arm/atsam/include/bsp/spi.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_SPI_H +#define LIBBSP_ARM_ATSAM_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define ATSAM_SPI_0_BUS_PATH "/dev/spi-0" +#define ATSAM_SPI_1_BUS_PATH "/dev/spi-1" +#define ATSAM_SPI_2_BUS_PATH "/dev/spi-2" + +int atsam_register_spi_0(void); + +int atsam_register_spi_1(void); + +int atsam_register_spi_2(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_SPI_H */ diff --git a/bsps/arm/atsam/include/libchip/chip.h b/bsps/arm/atsam/include/libchip/chip.h new file mode 100644 index 0000000000..56e8cffbd1 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/chip.h @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef SAMS7_CHIP_H +#define SAMS7_CHIP_H + +#include "compiler.h" + + +/************************************************* + * Memory type and its attribute + *************************************************/ +#define SHAREABLE 1 +#define NON_SHAREABLE 0 +/********************************************************************************************************************************************************************* +* Memory Type Definition Memory TEX attribute C attribute B attribute S attribute +**********************************************************************************************************************************************************************/ + +#define STRONGLY_ORDERED_SHAREABLE_TYPE ((0x00 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos)) // DO not care // +#define SHAREABLE_DEVICE_TYPE ((0x00 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos)) // DO not care // +#define INNER_OUTER_NORMAL_WT_NWA_TYPE(x) ((0x00 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define INNER_OUTER_NORMAL_WB_NWA_TYPE(x) ((0x00 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define INNER_OUTER_NORMAL_NOCACHE_TYPE(x) ((0x01 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define INNER_OUTER_NORMAL_WB_RWA_TYPE(x) ((0x01 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define NON_SHAREABLE_DEVICE_TYPE ((0x02 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos)) // DO not care // + +/* Normal memory attributes with outer capability rules to Non_Cacable */ + +#define INNER_NORMAL_NOCACHE_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define INNER_NORMAL_WB_RWA_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define INNER_NORMAL_WT_NWA_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define INNER_NORMAL_WB_NWA_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) + +/* SCB Interrupt Control State Register Definitions */ +#ifndef SCB_VTOR_TBLBASE_Pos + #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ + #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ +#endif + + +/* + * Peripherals + */ +#include "include/acc.h" +#include "include/aes.h" +#include "include/afec.h" +#include "include/efc.h" +#include "include/pio.h" +#include "include/pio_it.h" +#include "include/efc.h" +#include "include/rstc.h" +#include "include/mpu.h" +#include "include/gmac.h" +#include "include/gmacd.h" +#include "include/video.h" +#include "include/icm.h" +#include "include/isi.h" +#include "include/exceptions.h" +#include "include/pio_capture.h" +#include "include/rtc.h" +#include "include/rtt.h" +#include "include/tc.h" +#include "include/timetick.h" +#include "include/twi.h" +#include "include/flashd.h" +#include "include/pmc.h" +#include "include/pwmc.h" +#include "include/mcan.h" +#include "include/supc.h" +#include "include/usart.h" +#include "include/uart.h" +#include "include/isi.h" +#include "include/hsmci.h" +#include "include/ssc.h" +#include "include/twi.h" +#include "include/trng.h" +#include "include/wdt.h" +#include "include/spi.h" +#include "include/qspi.h" +#include "include/trace.h" +#include "include/xdmac.h" +#include "include/xdma_hardware_interface.h" +#include "include/xdmad.h" +#include "include/mcid.h" +#include "include/twid.h" +#include "include/spi_dma.h" +#include "include/qspi_dma.h" +#include "include/uart_dma.h" +#include "include/usart_dma.h" +#include "include/twid.h" +#include "include/afe_dma.h" +#include "include/dac_dma.h" +#include "include/usbhs.h" + +#define ENABLE_PERIPHERAL(dwId) PMC_EnablePeripheral(dwId) +#define DISABLE_PERIPHERAL(dwId) PMC_DisablePeripheral(dwId) + +#endif /* SAMS7_CHIP_H */ diff --git a/bsps/arm/atsam/include/libchip/compiler.h b/bsps/arm/atsam/include/libchip/compiler.h new file mode 100644 index 0000000000..f36013ac21 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/compiler.h @@ -0,0 +1,476 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _COMPILER_H_ +#define _COMPILER_H_ + +#ifdef __rtems__ +#include +#endif /* __rtems__ */ +/* + * Peripherals registers definitions + */ +#if defined __SAMV71J19__ \ + || defined __SAMV71J20__ \ + || defined __SAMV71J21__ \ + || defined __SAMV71N19__ \ + || defined __SAMV71N20__ \ + || defined __SAMV71N21__ \ + || defined __SAMV71Q19__ \ + || defined __SAMV71Q20__ \ + || defined __SAMV71Q21__ + #include "include/samv71/samv71.h" +#elif defined __SAMS70J19__ \ + || defined __SAMS70J20__ \ + || defined __SAMS70J21__ \ + || defined __SAMS70N19__ \ + || defined __SAMS70N20__ \ + || defined __SAMS70N21__ \ + || defined __SAMS70Q19__ \ + || defined __SAMS70Q20__ \ + || defined __SAMS70Q21__ + #include "include/sams70/sams70.h" +#elif defined __SAME70J19__ \ + || defined __SAME70J20__ \ + || defined __SAME70J21__ \ + || defined __SAME70N19__ \ + || defined __SAME70N20__ \ + || defined __SAME70N21__ \ + || defined __SAME70Q19__ \ + || defined __SAME70Q20__ \ + || defined __SAME70Q21__ + #include "include/same70/same70.h" +#else + #error "please define correct macro for the chip first!" +#endif + + +//_____ D E C L A R A T I O N S ____________________________________________ + +#ifndef __ASSEMBLY__ + +#include +#include +#include +#include + +/* Define WEAK attribute */ +#if defined (__CC_ARM) + #define WEAK __attribute__ ((weak)) +#elif defined (__ICCARM__) + #define WEAK __weak +#elif defined (__GNUC__) + #define WEAK __attribute__ ((weak)) +#endif + +/* Define Compiler name of tool chains */ +#if defined (__CC_ARM) + #define COMPILER_NAME "KEIL" +#elif defined (__ICCARM__) + #define COMPILER_NAME "IAR" +#elif defined (__GNUC__) + #define COMPILER_NAME "GCC" +#endif + +/* Define NO_INIT attribute */ +#if defined (__CC_ARM) + #define NO_INIT +#elif defined (__ICCARM__) + #define NO_INIT __no_init +#elif defined (__GNUC__) + #define NO_INIT +#endif + + +/* Define memory sync for tool chains */ +#if defined (__CC_ARM) + #define memory_sync() __dsb(15);__isb(15); +#elif defined (__ICCARM__) + #define memory_sync() __DSB();__ISB(); +#elif defined (__GNUC__) + #define memory_sync() __DSB();__ISB(); +#endif + +/* Define memory barrier for tool chains */ +#if defined (__CC_ARM) + #define memory_barrier() __dmb(15); +#elif defined (__ICCARM__) + #define memory_barrier() __DMB(); +#elif defined (__GNUC__) + #define memory_barrier() __DMB(); +#endif + +/*! \name Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. + * + * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by + * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is + * equivalent to writing U32. + */ +//! @{ +#define TPASTE2(a, b) a##b +#define TPASTE3(a, b, c) a##b##c +//! @} + +/*! \name Absolute Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * No restriction of use if the tokens are \#defined. + * + * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined + * as 32 is equivalent to writing U32. + */ +//! @{ +#define ATPASTE2(a, b) TPASTE2(a, b) +#define ATPASTE3(a, b, c) TPASTE3(a, b, c) +//! @} + + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent structure and union + * definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent structure and union + * definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined (__CC_ARM) + #define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined (__ICCARM__) + #define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined (__GNUC__) + #define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Set aligned boundary. + */ +#if defined (__CC_ARM) + #define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined (__ICCARM__) + #define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined (__GNUC__) + #define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Set word-aligned boundary. + */ + +#if defined (__CC_ARM) + #define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +#elif defined (__ICCARM__) + #define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4) +#elif defined (__GNUC__) + #define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +#endif + + + +/*! \name Mathematics + * + * The same considerations as for clz and ctz apply here but GCC does not + * provide built-in functions to access the assembly instructions abs, min and + * max and it does not produce them by itself in most cases, so two sets of + * macros are defined here: + * - Abs, Min and Max to apply to constant expressions (values known at + * compile time); + * - abs, min and max to apply to non-constant expressions (values unknown at + * compile time), abs is found in stdlib.h. + */ +//! @{ + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values known at compile time. + */ +#define Abs(a) (((a) < 0) ? -(a) : (a)) + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Min(a, b) (((a) < (b)) ? (a) : (b)) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Max(a, b) (((a) > (b)) ? (a) : (b)) + +// abs() is already defined by stdlib.h + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define min(a, b) Min(a, b) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define max(a, b) Max(a, b) + +//! @} + +#define be32_to_cpu(x) __REV(x) +#define cpu_to_be32(x) __REV(x) +#define BE32_TO_CPU(x) __REV(x) +#define CPU_TO_BE32(x) __REV(x) + +/** + * \def UNUSED + * \brief Marking \a v as a unused parameter or value. + */ +#define UNUSED(v) (void)(v) + +/** + * \weakgroup interrupt_group + * + * @{ + */ + +/** + * \name Interrupt Service Routine definition + * + * @{ + */ + +/** + * \brief Initialize interrupt vectors + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to initialize them, except defined the vector function with + * right name. + * + * This must be called prior to \ref irq_register_handler. + */ +# define irq_initialize_vectors() \ + do { \ + } while (0) + +/** + * \brief Register handler for interrupt + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to register them, except defined the vector function with + * right name. + * + * Usage: + * \code + irq_initialize_vectors(); + irq_register_handler(foo_irq_handler); +\endcode + * + * \note The function \a func must be defined with the \ref ISR macro. + * \note The functions prototypes can be found in the device exception header + * files (exceptions.h). + */ +# define irq_register_handler(int_num, int_prio) \ + NVIC_ClearPendingIRQ((IRQn_Type)int_num); \ + NVIC_SetPriority((IRQn_Type)int_num, int_prio); \ + NVIC_EnableIRQ((IRQn_Type)int_num); \ + + //@} + + +# define cpu_irq_enable() \ + do { \ + /*g_interrupt_enabled = true; */ \ + __DMB(); \ + __enable_irq(); \ + } while (0) +# define cpu_irq_disable() \ + do { \ + __disable_irq(); \ + __DMB(); \ + /*g_interrupt_enabled = false; */ \ + } while (0) + + typedef uint32_t irqflags_t; + +#if !defined(__DOXYGEN__) + extern volatile bool g_interrupt_enabled; +#endif + +#define cpu_irq_is_enabled() (__get_PRIMASK() == 0) + + static volatile uint32_t cpu_irq_critical_section_counter; + static volatile bool cpu_irq_prev_interrupt_state; + + static inline irqflags_t cpu_irq_save(void) + { + irqflags_t flags = cpu_irq_is_enabled(); + cpu_irq_disable(); + return flags; + } + + static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) + { + return (flags); + } + + static inline void cpu_irq_restore(irqflags_t flags) + { + if (cpu_irq_is_enabled_flags(flags)) + cpu_irq_enable(); + } + /* + void cpu_irq_enter_critical(void); + void cpu_irq_leave_critical(void);*/ + + /** + * \weakgroup interrupt_deprecated_group + * @{ + */ + +#define Enable_global_interrupt() cpu_irq_enable() +#define Disable_global_interrupt() cpu_irq_disable() +#define Is_global_interrupt_enabled() cpu_irq_is_enabled() + + + //_____ M A C R O S ________________________________________________________ + + /*! \name Usual Constants + */ + //! @{ +#define DISABLE 0 +#define ENABLE 1 +#define DISABLED 0 +#define ENABLED 1 +#define OFF 0 +#define ON 1 +#define FALSE 0 +#define TRUE 1 +#ifndef __cplusplus + #if !defined(__bool_true_false_are_defined) + #define false FALSE + #define true TRUE + #endif +#endif +#define KO 0 +#define OK 1 +#define PASS 0 +#define FAIL 1 +#define LOW 0 +#define HIGH 1 +#define CLR 0 +#define SET 1 + //! @} + + /*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#define ctz(u) ((u) & (1ul << 0) ? 0 : \ + (u) & (1ul << 1) ? 1 : \ + (u) & (1ul << 2) ? 2 : \ + (u) & (1ul << 3) ? 3 : \ + (u) & (1ul << 4) ? 4 : \ + (u) & (1ul << 5) ? 5 : \ + (u) & (1ul << 6) ? 6 : \ + (u) & (1ul << 7) ? 7 : \ + (u) & (1ul << 8) ? 8 : \ + (u) & (1ul << 9) ? 9 : \ + (u) & (1ul << 10) ? 10 : \ + (u) & (1ul << 11) ? 11 : \ + (u) & (1ul << 12) ? 12 : \ + (u) & (1ul << 13) ? 13 : \ + (u) & (1ul << 14) ? 14 : \ + (u) & (1ul << 15) ? 15 : \ + (u) & (1ul << 16) ? 16 : \ + (u) & (1ul << 17) ? 17 : \ + (u) & (1ul << 18) ? 18 : \ + (u) & (1ul << 19) ? 19 : \ + (u) & (1ul << 20) ? 20 : \ + (u) & (1ul << 21) ? 21 : \ + (u) & (1ul << 22) ? 22 : \ + (u) & (1ul << 23) ? 23 : \ + (u) & (1ul << 24) ? 24 : \ + (u) & (1ul << 25) ? 25 : \ + (u) & (1ul << 26) ? 26 : \ + (u) & (1ul << 27) ? 27 : \ + (u) & (1ul << 28) ? 28 : \ + (u) & (1ul << 29) ? 29 : \ + (u) & (1ul << 30) ? 30 : \ + (u) & (1ul << 31) ? 31 : \ + 32) + +#endif // __ASSEMBLY__ + +#endif // _COMPILER_H_ diff --git a/bsps/arm/atsam/include/libchip/include/acc.h b/bsps/arm/atsam/include/libchip/include/acc.h new file mode 100644 index 0000000000..4d10665bc6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/acc.h @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (ACC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for ACC + * -# Initialize the ACC with ACC_Initialize(). + * -# Select the active channel using ACC_EnableChannel() + * -# Start the conversion with ACC_StartConversion() + * -# Wait the end of the conversion by polling status with ACC_GetStatus() + * -# Finally, get the converted data using ACC_GetConvertedData() + * + */ +#ifndef _ACC_ +#define _ACC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ +#define ACC_SELPLUS_AD12B0 0 +#define ACC_SELPLUS_AD12B1 1 +#define ACC_SELPLUS_AD12B2 2 +#define ACC_SELPLUS_AD12B3 3 +#define ACC_SELPLUS_AD12B4 4 +#define ACC_SELPLUS_AD12B5 5 +#define ACC_SELPLUS_AD12B6 6 +#define ACC_SELPLUS_AD12B7 7 +#define ACC_SELMINUS_TS 0 +#define ACC_SELMINUS_ADVREF 1 +#define ACC_SELMINUS_DAC0 2 +#define ACC_SELMINUS_DAC1 3 +#define ACC_SELMINUS_AD12B0 4 +#define ACC_SELMINUS_AD12B1 5 +#define ACC_SELMINUS_AD12B2 6 +#define ACC_SELMINUS_AD12B3 7 + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ +#define ACC_CfgModeReg(pAcc, mode) { \ + (pAcc)->ACC_MR = (mode);\ + } + +#define ACC_GetModeReg(pAcc) ((pAcc)->ACC_MR) + +#define ACC_StartConversion(pAcc) ((pAcc)->ACC_CR = ACC_CR_START) + +#define ACC_SoftReset(pAcc) ((pAcc)->ACC_CR = ACC_CR_SWRST) + +#define ACC_EnableChannel(pAcc, dwChannel) {\ + assert(dwChannel < 16);\ + (pAcc)->ACC_CHER = (1 << (dwChannel));\ + } + +#define ACC_DisableChannel(pAcc, dwChannel) {\ + assert(dwChannel < 16);\ + (pAcc)->ACC_CHDR = (1 << (dwChannel));\ + } + +#define ACC_EnableIt(pAcc, dwMode) {\ + assert(((dwMode)&0xFFF00000)== 0);\ + (pAcc)->ACC_IER = (dwMode);\ + } + +#define ACC_DisableIt(pAcc, dwMode) {\ + assert(((dwMode)&0xFFF00000)== 0);\ + (pAcc)->ACC_IDR = (dwMode);\ + } + +#define ACC_EnableDataReadyIt(pAcc) ((pAcc)->ACC_IER = AT91C_ACC_DRDY) + +#define ACC_GetStatus(pAcc) ((pAcc)->ACC_ISR) + +#define ACC_GetChannelStatus(pAcc) ((pAcc)->ACC_CHSR) + +#define ACC_GetInterruptMaskStatus(pAcc) ((pAcc)->ACC_IMR) + +#define ACC_GetLastConvertedData(pAcc) ((pAcc)->ACC_LCDR) + +#define ACC_CfgAnalogCtrlReg(pAcc, dwMode) {\ + assert(((dwMode) & 0xFFFCFF3C) == 0);\ + (pAcc)->ACC_ACR = (dwMode);\ + } + +#define ACC_CfgExtModeReg(pAcc, extmode) {\ + assert(((extmode) & 0xFF00FFFE) == 0);\ + (pAcc)->ACC_EMR = (extmode);\ + } + +#define ACC_GetAnalogCtrlReg(pAcc) ((pAcc)->ACC_ACR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void ACC_Configure(Acc *pAcc, uint8_t idAcc, uint8_t ucSelplus, + uint8_t ucSelminus, uint16_t wAc_en, uint16_t wEdge, uint16_t wInvert); + +extern void ACC_SetComparisonPair(Acc *pAcc, uint8_t ucSelplus, + uint8_t ucSelminus); + +extern uint32_t ACC_GetComparisonResult(Acc *pAcc, uint32_t dwStatus); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _ACC_ */ diff --git a/bsps/arm/atsam/include/libchip/include/adc.h b/bsps/arm/atsam/include/libchip/include/adc.h new file mode 100644 index 0000000000..a5585c9651 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/adc.h @@ -0,0 +1,179 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (ADC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for ADC. + * -# Initialize the ADC with ADC_Initialize(). + * -# Set ADC clock and timing with ADC_SetClock() and ADC_SetTiming(). + * -# Select the active channel using ADC_EnableChannel(). + * -# Start the conversion with ADC_StartConversion(). + * -# Wait the end of the conversion by polling status with ADC_GetStatus(). + * -# Finally, get the converted data using ADC_GetConvertedData() or + * ADC_GetLastConvertedData(). + * +*/ +#ifndef _ADC_ +#define _ADC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ + +/* Max. ADC Clock Frequency (Hz) */ +#define ADC_CLOCK_MAX 20000000 + +/* Max. normal ADC startup time (us) */ +#define ADC_STARTUP_NORMAL_MAX 40 +/* Max. fast ADC startup time (us) */ +#define ADC_STARTUP_FAST_MAX 12 + +/* Definitions for ADC channels */ +#define ADC_CHANNEL_0 0 +#define ADC_CHANNEL_1 1 +#define ADC_CHANNEL_2 2 +#define ADC_CHANNEL_3 3 +#define ADC_CHANNEL_4 4 +#define ADC_CHANNEL_5 5 +#define ADC_CHANNEL_6 6 +#define ADC_CHANNEL_7 7 +#define ADC_CHANNEL_8 8 +#define ADC_CHANNEL_9 9 +#define ADC_CHANNEL_10 10 +#define ADC_CHANNEL_11 11 +#define ADC_CHANNEL_12 12 +#define ADC_CHANNEL_13 13 +#define ADC_CHANNEL_14 14 +#define ADC_CHANNEL_15 15 + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ + +#define ADC_GetModeReg(pAdc) ((pAdc)->ADC_MR) + +#define ADC_StartConversion(pAdc) ((pAdc)->ADC_CR = ADC_CR_START) + +#define ADC_SetCalibMode(pAdc) ((pAdc)->ADC_CR |= ADC_CR_AUTOCAL) + +#define ADC_EnableChannel(pAdc, dwChannel) {\ + (pAdc)->ADC_CHER = (1 << (dwChannel));\ + } + +#define ADC_DisableChannel(pAdc, dwChannel) {\ + (pAdc)->ADC_CHDR = (1 << (dwChannel));\ + } + +#define ADC_EnableIt(pAdc, dwMode) {\ + (pAdc)->ADC_IER = (dwMode);\ + } + +#define ADC_DisableIt(pAdc, dwMode) {\ + (pAdc)->ADC_IDR = (dwMode);\ + } + +#define ADC_SetChannelGain(pAdc,dwMode) {\ + (pAdc)->ADC_CGR = dwMode;\ + } + +#define ADC_SetChannelOffset(pAdc,dwMode) {\ + (pAdc)->ADC_COR = dwMode;\ + } + +#define ADC_EnableDataReadyIt(pAdc) ((pAdc)->ADC_IER = ADC_IER_DRDY) + +#define ADC_GetStatus(pAdc) ((pAdc)->ADC_ISR) + +#define ADC_GetCompareMode(pAdc) (((pAdc)->ADC_EMR)& (ADC_EMR_CMPMODE_Msk)) + +#define ADC_GetChannelStatus(pAdc) ((pAdc)->ADC_CHSR) + +#define ADC_GetInterruptMaskStatus(pAdc) ((pAdc)->ADC_IMR) + +#define ADC_GetLastConvertedData(pAdc) ((pAdc)->ADC_LCDR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void ADC_Initialize(Adc *pAdc, uint32_t dwId); +extern uint32_t ADC_SetClock(Adc *pAdc, uint32_t dwPres, uint32_t dwMck); +extern void ADC_SetTiming(Adc *pAdc, uint32_t dwStartup, uint32_t dwTracking, + uint32_t dwSettling); +extern void ADC_SetTrigger(Adc *pAdc, uint32_t dwTrgSel); +extern void ADC_SetTriggerMode(Adc *pAdc, uint32_t dwMode); +extern void ADC_SetLowResolution(Adc *pAdc, uint32_t bEnDis); +extern void ADC_SetSleepMode(Adc *pAdc, uint8_t bEnDis); +extern void ADC_SetFastWakeup(Adc *pAdc, uint8_t bEnDis); +extern void ADC_SetSequenceMode(Adc *pAdc, uint8_t bEnDis); +extern void ADC_SetSequence(Adc *pAdc, uint32_t dwSEQ1, uint32_t dwSEQ2); +extern void ADC_SetSequenceByList(Adc *pAdc, uint8_t ucChList[], + uint8_t ucNumCh); +extern void ADC_SetAnalogChange(Adc *pAdc, uint8_t bEnDis); +extern void ADC_SetTagEnable(Adc *pAdc, uint8_t bEnDis); +extern void ADC_SetCompareChannel(Adc *pAdc, uint32_t dwChannel); +extern void ADC_SetCompareMode(Adc *pAdc, uint32_t dwMode); +extern void ADC_SetComparisonWindow(Adc *pAdc, uint32_t dwHi_Lo); +extern uint8_t ADC_CheckConfiguration(Adc *pAdc, uint32_t dwMcK); +extern uint32_t ADC_GetConvertedData(Adc *pAdc, uint32_t dwChannel); +extern void ADC_SetTsAverage(Adc *pADC, uint32_t dwAvg2Conv); +extern uint32_t ADC_GetTsXPosition(Adc *pADC); +extern uint32_t ADC_GetTsYPosition(Adc *pADC); +extern uint32_t ADC_GetTsPressure(Adc *pADC); +extern void ADC_SetTsDebounce(Adc *pADC, uint32_t dwTime); +extern void ADC_SetTsPenDetect(Adc *pADC, uint8_t bEnDis); +extern void ADC_SetStartupTime(Adc *pAdc, uint32_t dwUs); +extern void ADC_SetTrackingTime(Adc *pAdc, uint32_t dwNs); +extern void ADC_SetTriggerPeriod(Adc *pAdc, uint32_t dwPeriod); +extern void ADC_SetTsMode(Adc *pADC, uint32_t dwMode); +extern void ADC_TsCalibration(Adc *pAdc); + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _ADC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/aes.h b/bsps/arm/atsam/include/libchip/include/aes.h new file mode 100644 index 0000000000..1fca47989d --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/aes.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _AES_ +#define _AES_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*----------------------------------------------------------------------------*/ +/* Definition */ +/*----------------------------------------------------------------------------*/ +#define AES_MR_CIPHER_ENCRYPT 1 +#define AES_MR_CIPHER_DECRYPT 0 +/*----------------------------------------------------------------------------*/ +/* Exported functions */ +/*----------------------------------------------------------------------------*/ + +extern void AES_Start(void); +extern void AES_SoftReset(void); +extern void AES_Recount(void); +extern void AES_Configure(uint32_t mode); +extern void AES_EnableIt(uint32_t sources); +extern void AES_DisableIt(uint32_t sources); +extern uint32_t AES_GetStatus(void); +extern void AES_WriteKey(const uint32_t *pKey, uint32_t keyLength); +extern void AES_SetInput(uint32_t *data); +extern void AES_GetOutput(uint32_t *data); +extern void AES_SetVector(const uint32_t *pVector); +extern void AES_SetAadLen(uint32_t len); +extern void AES_SetDataLen(uint32_t len); +extern void AES_SetGcmHash(uint32_t *hash); +extern void AES_GetGcmTag(uint32_t *tag); +extern void AES_GetGcmCounter(uint32_t *counter); +extern void AES_GetGcmH(uint32_t *h); + + +#endif /* #ifndef _AES_ */ diff --git a/bsps/arm/atsam/include/libchip/include/afe_dma.h b/bsps/arm/atsam/include/libchip/include/afe_dma.h new file mode 100644 index 0000000000..6bcfbb3bcc --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/afe_dma.h @@ -0,0 +1,116 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (AFEC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for AFEC. + * -# Initialize the AFEC with AFEC_Initialize(). + * -# Set AFEC clock and timing with AFEC_SetClock() and AFEC_SetTiming(). + * -# Select the active channel using AFEC_EnableChannel(). + * -# Start the conversion with AFEC_StartConversion(). + * -# Wait the end of the conversion by polling status with AFEC_GetStatus(). + * -# Finally, get the converted data using AFEC_GetConvertedData() or + * AFEC_GetLastConvertedData(). + * +*/ +#ifndef _AFE_DMA_ +#define _AFE_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** AFE transfer complete callback. */ +typedef void (*AfeCallback)(uint8_t, void *); + +/** \brief Spi Transfer Request prepared by the application upper layer. + * + * This structure is sent to the AFE_SendCommand function to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct { + /** Pointer to the Rx data. */ + uint32_t *pRxBuff; + /** Rx size in bytes. */ + uint16_t RxSize; + /** Callback function invoked at the end of transfer. */ + AfeCallback callback; + /** Callback arguments. */ + void *pArgument; +} AfeCmd; + + +/** Constant structure associated with AFE port. This structure prevents + client applications to have access in the same time. */ +typedef struct { + /** Pointer to AFE Hardware registers */ + Afec *pAfeHw; + /** Current SpiCommand being processed */ + AfeCmd *pCurrentCommand; + /** Pointer to DMA driver */ + sXdmad *pXdmad; + /** AFEC Id as defined in the product datasheet */ + uint8_t afeId; + /** Mutual exclusion semaphore. */ + volatile int8_t semaphore; +} AfeDma; + + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ +#define AFE_OK 0 +#define AFE_ERROR 1 +#define AFE_ERROR_LOCK 2 +/*------------------------------------------------------------------------------ + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint32_t Afe_ConfigureDma(AfeDma *pAfed , + Afec *pAfeHw , + uint8_t AfeId, + sXdmad *pXdmad); +extern uint32_t Afe_SendData(AfeDma *pAfed, AfeCmd *pCommand); + + +#endif /* #ifndef _AFE_DMA_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/afec.h b/bsps/arm/atsam/include/libchip/include/afec.h new file mode 100644 index 0000000000..75c74ff2b6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/afec.h @@ -0,0 +1,190 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (AFEC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for AFEC. + * -# Initialize the AFEC with AFEC_Initialize(). + * -# Set AFEC clock and timing with AFEC_SetClock() and AFEC_SetTiming(). + * -# Select the active channel using AFEC_EnableChannel(). + * -# Start the conversion with AFEC_StartConversion(). + * -# Wait the end of the conversion by polling status with AFEC_GetStatus(). + * -# Finally, get the converted data using AFEC_GetConvertedData() or + * AFEC_GetLastConvertedData(). + * +*/ +#ifndef _AFEC_ +#define _AFEC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ + +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_SETTLING_Pos 20 +#define AFEC_MR_SETTLING_Msk (0x3u << AFEC_MR_SETTLING_Pos) +/**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_SETTLING_AST3 (0x0u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST3 3 periods of AFEClock */ +#define AFEC_MR_SETTLING_AST5 (0x1u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST5 5 periods of AFEClock */ +#define AFEC_MR_SETTLING_AST9 (0x2u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST9 9 periods of AFEClock*/ +#define AFEC_MR_SETTLING_AST17 (0x3u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST17 17 periods of AFEClock*/ + +/***************************** Single Trigger Mode ****************************/ +#define AFEC_EMR_STM_Pos 25 +#define AFEC_EMR_STM_Msk (0x1u << AFEC_EMR_STM_Pos) +/**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_STM_MULTI_TRIG (0x0u << 25) +/**< \brief (AFEC_EMR) Single Trigger Mode: Multiple triggers are required to + get an averaged result. */ +#define AFEC_EMR_STM_SINGLE_TRIG (0x1u << 25) +/**< \brief (AFEC_EMR) Single Trigger Mode: Only a Single Trigger is required + to get an averaged value. */ + +/***************************** TAG of the AFEC_LDCR Register ******************/ +#define AFEC_EMR_TAG_Pos 24 +#define AFEC_EMR_TAG_Msk (0x1u << AFEC_EMR_TAG_Pos) +/**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register */ +#define AFEC_EMR_TAG_CHNB_ZERO (0x0u << 24) +/**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Sets CHNB to zero +in AFEC_LDCR. */ +#define AFEC_EMR_TAG_APPENDS (0x1u << 24) +/**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Appends the channel +number to the conversion result in AFEC_LDCR register. */ + +/***************************** Compare All Channels ******************/ +#define AFEC_EMR_CMPALL_Pos 9 +#define AFEC_EMR_CMPALL_Msk (0x1u << AFEC_EMR_TAG_Pos) +/**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPALL_ONE_CHANNEL_COMP (0x0u << 9) +/**< \brief (AFEC_EMR) Compare All Channels: Only channel indicated in +CMPSEL field is compared. */ +#define AFEC_EMR_CMPALL_ALL_CHANNELS_COMP (0x1u << 9) +/**< \brief (AFEC_EMR) Compare All Channels: All channels are compared. */ + +#define AFEC_ACR_PGA0_ON (0x1u << 2) +#define AFEC_ACR_PGA1_ON (0x1u << 3) + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ + +#define AFEC_GetModeReg(pAFEC) ((pAFEC)->AFEC_MR) +#define AFEC_SetModeReg(pAFEC, mode) ((pAFEC)->AFEC_MR = mode) + +#define AFEC_GetExtModeReg(pAFEC) ((pAFEC)->AFEC_EMR) +#define AFEC_SetExtModeReg(pAFEC, mode) ((pAFEC)->AFEC_EMR = mode) + +#define AFEC_StartConversion(pAFEC) ((pAFEC)->AFEC_CR = AFEC_CR_START) + +#define AFEC_EnableChannel(pAFEC, dwChannel) {\ + (pAFEC)->AFEC_CHER = (1 << (dwChannel));\ + } + +#define AFEC_DisableChannel(pAFEC, dwChannel) {\ + (pAFEC)->AFEC_CHDR = (1 << (dwChannel));\ + } + +#define AFEC_EnableIt(pAFEC, dwMode) {\ + (pAFEC)->AFEC_IER = (dwMode);\ + } + +#define AFEC_DisableIt(pAFEC, dwMode) {\ + (pAFEC)->AFEC_IDR = (dwMode);\ + } + +#define AFEC_SetChannelGain(pAFEC,dwMode) {\ + (pAFEC)->AFEC_CGR = dwMode;\ + } + +#define AFEC_EnableDataReadyIt(pAFEC) ((pAFEC)->AFEC_IER = AFEC_IER_DRDY) + +#define AFEC_GetStatus(pAFEC) ((pAFEC)->AFEC_ISR) + +#define AFEC_GetCompareMode(pAFEC) (((pAFEC)->AFEC_EMR)& (AFEC_EMR_CMPMODE_Msk)) + +#define AFEC_GetChannelStatus(pAFEC) ((pAFEC)->AFEC_CHSR) + +#define AFEC_GetInterruptMaskStatus(pAFEC) ((pAFEC)->AFEC_IMR) + +#define AFEC_GetLastConvertedData(pAFEC) ((pAFEC)->AFEC_LCDR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void AFEC_Initialize(Afec *pAFEC, uint32_t dwId); +extern uint32_t AFEC_SetClock(Afec *pAFEC, uint32_t dwPres, uint32_t dwMck); +extern void AFEC_SetTiming(Afec *pAFEC, uint32_t dwStartup, + uint32_t dwTracking, + uint32_t dwSettling); +extern void AFEC_SetTrigger(Afec *pAFEC, uint32_t dwTrgSel); +extern void AFEC_SetAnalogChange(Afec *pAFE, uint8_t bEnDis); +extern void AFEC_SetSleepMode(Afec *pAFEC, uint8_t bEnDis); +extern void AFEC_SetFastWakeup(Afec *pAFEC, uint8_t bEnDis); +extern void AFEC_SetSequenceMode(Afec *pAFEC, uint8_t bEnDis); +extern void AFEC_SetSequence(Afec *pAFEC, uint32_t dwSEQ1, uint32_t dwSEQ2); +extern void AFEC_SetSequenceByList(Afec *pAFEC, uint8_t ucChList[], + uint8_t ucNumCh); +extern void AFEC_SetTagEnable(Afec *pAFEC, uint8_t bEnDis); +extern void AFEC_SetCompareChannel(Afec *pAFEC, uint32_t dwChannel); +extern void AFEC_SetCompareMode(Afec *pAFEC, uint32_t dwMode); +extern void AFEC_SetComparisonWindow(Afec *pAFEC, uint32_t dwHi_Lo); +extern uint8_t AFEC_CheckConfiguration(Afec *pAFEC, uint32_t dwMcK); +extern uint32_t AFEC_GetConvertedData(Afec *pAFEC, uint32_t dwChannel); +extern void AFEC_SetStartupTime(Afec *pAFEC, uint32_t dwUs); +extern void AFEC_SetTrackingTime(Afec *pAFEC, uint32_t dwNs); +extern void AFEC_SetAnalogOffset(Afec *pAFE, uint32_t dwChannel, + uint32_t aoffset); +extern void AFEC_SetAnalogControl(Afec *pAFE, uint32_t control); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _AFEC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/chip.h b/bsps/arm/atsam/include/libchip/include/chip.h new file mode 100644 index 0000000000..a9f1f01bea --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/chip.h @@ -0,0 +1 @@ +#include "../chip.h" diff --git a/bsps/arm/atsam/include/libchip/include/dac_dma.h b/bsps/arm/atsam/include/libchip/include/dac_dma.h new file mode 100644 index 0000000000..11d100b76d --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/dac_dma.h @@ -0,0 +1,150 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (DACC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for DACC + * -# Initialize the DACC with DACC_Initialize(). + * -# Select the active channel using DACC_EnableChannel() + * -# Start the conversion with DACC_StartConversion() + * -# Wait the end of the conversion by polling status with DACC_GetStatus() + * -# Finally, get the converted data using DACC_GetConvertedData() + * +*/ +#ifndef _DAC_DMA_ +#define _DAC_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** DAC transfer complete callback. */ +typedef void (*DacCallback)(uint8_t, void *); + +/** \brief Dac Transfer Request prepared by the application upper layer. + * + * This structure is sent to the DAC_SendCommand function to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct { + /** Pointer to the Tx data. */ + uint8_t *pTxBuff; + /** Tx size in bytes. */ + uint16_t TxSize; + /** Tx loop back. */ + uint16_t loopback; + /** DACC channel*/ + uint8_t dacChannel; + /** Callback function invoked at the end of transfer. */ + DacCallback callback; + /** Callback arguments. */ + void *pArgument; +} DacCmd; + + +/** Constant structure associated with DAC port. This structure prevents + client applications to have access in the same time. */ +typedef struct { + /** Pointer to DAC Hardware registers */ + Dacc *pDacHw; + /** Current SpiCommand being processed */ + DacCmd *pCurrentCommand; + /** Pointer to DMA driver */ + sXdmad *pXdmad; + /** DACC Id as defined in the product datasheet */ + uint8_t dacId; + /** Mutual exclusion semaphore. */ + volatile int8_t semaphore; +} DacDma; + + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ +#define DAC_OK 0 +#define DAC_ERROR 1 +#define DAC_ERROR_LOCK 2 + +#define DACC_CHANNEL_0 0 +#define DACC_CHANNEL_1 1 + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern uint32_t Dac_ConfigureDma(DacDma *pDacd , + Dacc *pDacHw , + uint8_t DacId, + sXdmad *pXdmad); +extern uint32_t Dac_SendData(DacDma *pDacd, DacCmd *pCommand); + + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ +#define DACC_SoftReset(pDACC) ((pDACC)->DACC_CR = DACC_CR_SWRST) +#define DACC_CfgModeReg(pDACC, mode) { (pDACC)->DACC_MR = (mode); } +#define DACC_GetModeReg(pDACC) ((pDACC)->DACC_MR) +#define DACC_CfgTrigger(pDACC, mode) { (pDACC)->DACC_TRIGR = (mode); } + +#define DACC_EnableChannel(pDACC, channel) {(pDACC)->DACC_CHER = (1 << (channel));} +#define DACC_DisableChannel(pDACC, channel) {(pDACC)->DACC_CHDR = (1 << (channel));} + +#define DACC_EnableIt(pDACC, mode) {(pDACC)->DACC_IER = (mode);} +#define DACC_DisableIt(pDACC, mode) {(pDACC)->DACC_IDR = (mode);} +#define DACC_GetStatus(pDACC) ((pDACC)->DACC_ISR) +#define DACC_GetChannelStatus(pDACC) ((pDACC)->DACC_CHSR) +#define DACC_GetInterruptMaskStatus(pDACC) ((pDACC)->DACC_IMR) + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _DAC_DMA_ */ diff --git a/bsps/arm/atsam/include/libchip/include/efc.h b/bsps/arm/atsam/include/libchip/include/efc.h new file mode 100644 index 0000000000..c4ff7c49f6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/efc.h @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Enhanced Embedded Flash Controller (EEFC) + * peripheral. + * + * \section Usage + * + * -# Enable/disable %flash ready interrupt sources using EFC_EnableFrdyIt() + * and EFC_DisableFrdyIt(). + * -# Translates the given address into which EEFC, page and offset values + * for difference density %flash memory using EFC_TranslateAddress(). + * -# Computes the address of a %flash access given the EFC, page and offset + * for difference density %flash memory using EFC_ComputeAddress(). + * -# Start the executing command with EFC_PerformCommand() + * -# Retrieve the current status of the EFC using EFC_GetStatus(). + * -# Retrieve the result of the last executed command with EFC_GetResult(). + */ + +#ifndef _EEFC_ +#define _EEFC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* TODO: Temporary definition for missing symbol in header file */ +#define IFLASH_SECTOR_SIZE 65536u + + +/* EFC command */ +#define EFC_FCMD_GETD 0x00 /* Get Flash Descriptor */ +#define EFC_FCMD_WP 0x01 /* Write page */ +#define EFC_FCMD_WPL 0x02 /* Write page and lock */ +#define EFC_FCMD_EWP 0x03 /* Erase page and write page */ +#define EFC_FCMD_EWPL 0x04 /* Erase page and write page then lock */ +#define EFC_FCMD_EA 0x05 /* Erase all */ +#define EFC_FCMD_EPA 0x07 /* Erase pages */ +#define EFC_FCMD_SLB 0x08 /* Set Lock Bit */ +#define EFC_FCMD_CLB 0x09 /* Clear Lock Bit */ +#define EFC_FCMD_GLB 0x0A /* Get Lock Bit */ +#define EFC_FCMD_SFB 0x0B /* Set GPNVM Bit */ +#define EFC_FCMD_CFB 0x0C /* Clear GPNVM Bit */ +#define EFC_FCMD_GFB 0x0D /* Get GPNVM Bit */ +#define EFC_FCMD_STUI 0x0E /* Start unique ID */ +#define EFC_FCMD_SPUI 0x0F /* Stop unique ID */ +#define EFC_FCMD_GCALB 0x10 /* Get CALIB Bit */ +#define EFC_FCMD_ES 0x11 /* Erase Sector */ +#define EFC_FCMD_WUS 0x12 /* Write User Signature */ +#define EFC_FCMD_EUS 0x13 /* Erase User Signature */ +#define EFC_FCMD_STUS 0x14 /* Start Read User Signature */ +#define EFC_FCMD_SPUS 0x15 /* Stop Read User Signature */ + +/* The IAP function entry address */ +#define CHIP_FLASH_IAP_ADDRESS (0x00800008) + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void EFC_EnableFrdyIt(Efc *efc); + +extern void EFC_DisableFrdyIt(Efc *efc); + +extern void EFC_SetWaitState(Efc *efc, uint8_t cycles); + +extern void EFC_TranslateAddress(Efc **pEfc, uint32_t dwAddress, + uint16_t *pwPage, uint16_t *pwOffset); + +extern void EFC_ComputeAddress(Efc *efc, uint16_t wPage, uint16_t wOffset, + uint32_t *pdwAddress); + +extern uint32_t EFC_PerformCommand(Efc *efc, uint32_t dwCommand, + uint32_t dwArgument, uint32_t dwUseIAP); + +extern uint32_t EFC_GetStatus(Efc *efc); + +extern uint32_t EFC_GetResult(Efc *efc); + +extern void EFC_SetFlashAccessMode(Efc *efc, uint32_t dwMode); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _EEFC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/exceptions.h b/bsps/arm/atsam/include/libchip/include/exceptions.h new file mode 100644 index 0000000000..2a18dae728 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/exceptions.h @@ -0,0 +1,52 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * Interface for default exception handlers. + */ + +#ifndef _EXCEPTIONS_ +#define _EXCEPTIONS_ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/* Function prototype for exception table items (interrupt handler). */ +typedef void(*IntFunc)(void); + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/* Default empty handler */ +extern void IrqHandlerNotUsed(void); + +#endif /* _EXCEPTIONS_ */ diff --git a/bsps/arm/atsam/include/libchip/include/flashd.h b/bsps/arm/atsam/include/libchip/include/flashd.h new file mode 100644 index 0000000000..c34325aa89 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/flashd.h @@ -0,0 +1,91 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * The flash driver provides the unified interface for flash program operations. + * + */ + +#ifndef _FLASHD_ +#define _FLASHD_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPNVBit_SecurityBit 0 +#define GPNVBit_BootMode 1 +#define GPNVBit_TCMBit1 6 +#define GPNVBit_TCMBit2 7 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void FLASHD_Initialize(uint32_t dwMCk, uint32_t dwUseIAP); + +extern uint32_t FLASHD_Erase(uint32_t dwAddress); + +extern uint32_t FLASHD_EraseSector(uint32_t dwAddress); + +extern uint32_t FLASHD_ErasePages(uint32_t dwAddress, uint32_t dwPageNum); + +extern uint32_t FLASHD_Write(uint32_t dwAddress, const void *pvBuffer, + uint32_t dwSize); + +extern uint32_t FLASHD_Lock(uint32_t dwStart, uint32_t dwEnd, + uint32_t *pdwActualStart, uint32_t *pdwActualEnd); + +extern uint32_t FLASHD_Unlock(uint32_t dwStart, uint32_t dwEnd, + uint32_t *pdwActualStart, uint32_t *pdwActualEnd); + +extern uint32_t FLASHD_IsLocked(uint32_t dwStart, uint32_t dwEnd); + +extern uint32_t FLASHD_SetGPNVM(uint8_t gpnvm); + +extern uint32_t FLASHD_ClearGPNVM(uint8_t gpnvm); + +extern uint32_t FLASHD_IsGPNVMSet(uint8_t gpnvm); + +#define FLASHD_IsSecurityBitSet() FLASHD_IsGPNVMSet(0) + +#define FLASHD_SetSecurityBit() FLASHD_SetGPNVM(0) + +extern uint32_t FLASHD_ReadUniqueID(uint32_t *pdwUniqueID); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _FLASHD_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/gmac.h b/bsps/arm/atsam/include/libchip/include/gmac.h new file mode 100644 index 0000000000..64e0079c25 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/gmac.h @@ -0,0 +1,349 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +/** \addtogroup gmac_module + * @{ + * Provides the interface to configure and use the GMAC peripheral. + * + * \section gmac_usage Usage + * - Configure Gmac::GMAC_NCFG with GMAC_Configure(), some of related controls + * are also available, such as: + * - GMAC_SetSpeed(): Setup GMAC working clock. + * - GMAC_FullDuplexEnable(): Working in full duplex or not. + * - GMAC_CpyAllEnable(): Copying all valid frames (\ref GMAC_NCFG_CAF). + * - ... + * - Setup Gmac::GMAC_NCR with GMAC_NetworkControl(), more related controls + * can modify with: + * - GMAC_ReceiveEnable(): Enable/Disable Rx. + * - GMAC_TransmitEnable(): Enable/Disable Tx. + * - GMAC_BroadcastDisable(): Enable/Disable broadcast receiving. + * - ... + * - Manage GMAC interrupts with GMAC_EnableIt(), GMAC_DisableIt(), + * GMAC_GetItMask() and GMAC_GetItStatus(). + * - Manage GMAC Tx/Rx status with GMAC_GetTxStatus(), GMAC_GetRxStatus() + * GMAC_ClearTxStatus() and GMAC_ClearRxStatus(). + * - Manage GMAC Queue with GMAC_SetTxQueue(), GMAC_GetTxQueue(), + * GMAC_SetRxQueue() and GMAC_GetRxQueue(), the queue descriptor can define + * by \ref sGmacRxDescriptor and \ref sGmacTxDescriptor. + * - Manage PHY through GMAC is performed by + * - GMAC_ManagementEnable(): Enable/Disable PHY management. + * - GMAC_PHYMaintain(): Execute PHY management commands. + * - GMAC_PHYData(): Return PHY management data. + * - GMAC_IsIdle(): Check if PHY is idle. + * - Setup GMAC parameters with following functions: + * - GMAC_SetHash(): Set Hash value. + * - GMAC_SetAddress(): Set MAC address. + * - Enable/Disable GMAC transceiver clock via GMAC_TransceiverClockEnable() + * - Switch GMAC MII/RMII mode through GMAC_RMIIEnable() + * + * For more accurate information, please look at the GMAC section of the + * Datasheet. + * + * \sa \ref gmacd_module + * + * Related files:\n + * gmac.c\n + * gmac.h.\n + * + * \defgroup gmac_defines GMAC Defines + * \defgroup gmac_structs GMAC Data Structs + * \defgroup gmac_functions GMAC Functions + */ +/**@}*/ + +#ifndef _GMAC_H +#define _GMAC_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Defines + *----------------------------------------------------------------------------*/ +/** \addtogroup gmac_defines + @{*/ + +#define NUM_GMAC_QUEUES 3 +/// Board GMAC base address + +#define GMAC_DUPLEX_HALF 0 +#define GMAC_DUPLEX_FULL 1 + +// +#define GMAC_SPEED_10M 0 +#define GMAC_SPEED_100M 1 +#define GMAC_SPEED_1000M 2 + +/*------------------------------------------------------------------------------ + Definitions +------------------------------------------------------------------------------ +*/ +/// The buffer addresses written into the descriptors must be aligned so the +/// last few bits are zero. These bits have special meaning for the GMAC +/// peripheral and cannot be used as part of the address. +#define GMAC_ADDRESS_MASK ((unsigned int)0xFFFFFFFC) +#define GMAC_LENGTH_FRAME ((unsigned int)0x3FFF) /// Length of frame mask + +// receive buffer descriptor bits +#define GMAC_RX_OWNERSHIP_BIT (1u << 0) +#define GMAC_RX_WRAP_BIT (1u << 1) +#define GMAC_RX_SOF_BIT (1u << 14) +#define GMAC_RX_EOF_BIT (1u << 15) + +// Transmit buffer descriptor bits +#define GMAC_TX_LAST_BUFFER_BIT (1u << 15) +#define GMAC_TX_WRAP_BIT (1u << 30) +#define GMAC_TX_USED_BIT (1u << 31) +#define GMAC_TX_RLE_BIT (1u << 29) /// Retry Limit Exceeded +#define GMAC_TX_UND_BIT (1u << 28) /// Tx Buffer Under-run +#define GMAC_TX_ERR_BIT (1u << 27) /// Exhausted in mid-frame +#define GMAC_TX_ERR_BITS \ + (GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT) + +// Interrupt bits +#define GMAC_INT_RX_BITS \ + (GMAC_IER_RCOMP | GMAC_IER_RXUBR | GMAC_IER_ROVR) +#define GMAC_INT_TX_ERR_BITS \ + (GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC | GMAC_IER_HRESP) +#define GMAC_INT_TX_BITS \ + (GMAC_INT_TX_ERR_BITS | GMAC_IER_TCOMP) +// Interrupt Status bits +#define GMAC_INT_RX_STATUS_BITS \ + (GMAC_ISR_RCOMP | GMAC_ISR_RXUBR | GMAC_ISR_ROVR) +#define GMAC_INT_TX_STATUS_ERR_BITS \ + (GMAC_ISR_TUR | GMAC_ISR_RLEX | GMAC_ISR_TFC | GMAC_ISR_HRESP) +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup gmac_structs + @{*/ + +/* This is the list of GMAC queue */ +typedef enum { + GMAC_QUE_0 = 0, + GMAC_QUE_1 = 1, + GMAC_QUE_2 = 2 +} gmacQueList_t; + +/** Receive buffer descriptor struct */ +typedef struct _GmacRxDescriptor { + union _GmacRxAddr { + uint32_t val; + struct _GmacRxAddrBM { + uint32_t bOwnership: 1, /**< User clear, GMAC set this to one once + it has successfully written a frame to + memory */ + bWrap: 1, /**< Marks last descriptor in receive buffer */ + addrDW: 30; /**< Address in number of DW */ + } bm; + } addr; /**< Address, Wrap & Ownership */ + union _GmacRxStatus { + uint32_t val; + struct _GmacRxStatusBM { + uint32_t len: 12, /** Length of frame including FCS */ + offset: 2, /** Receive buffer offset, + bits 13:12 of frame length for jumbo + frame */ + bSof: 1, /** Start of frame */ + bEof: 1, /** End of frame */ + bCFI: 1, /** Concatenation Format Indicator */ + vlanPriority: 3, /** VLAN priority (if VLAN detected) */ + bPriorityDetected: 1, /** Priority tag detected */ + bVlanDetected: 1, /**< VLAN tag detected */ + bTypeIDMatch: 1, /**< Type ID match */ + bAddr4Match: 1, /**< Address register 4 match */ + bAddr3Match: 1, /**< Address register 3 match */ + bAddr2Match: 1, /**< Address register 2 match */ + bAddr1Match: 1, /**< Address register 1 match */ + reserved: 1, + bExtAddrMatch: 1, /**< External address match */ + bUniHashMatch: 1, /**< Unicast hash match */ + bMultiHashMatch: 1, /**< Multicast hash match */ + bBroadcastDetected: 1; /**< Global all ones broadcast + address detected */ + } bm; + } status; +} sGmacRxDescriptor; /* GCC */ + +/** Transmit buffer descriptor struct */ +typedef struct _GmacTxDescriptor { + uint32_t addr; + union _GmacTxStatus { + uint32_t val; + struct _GmacTxStatusBM { + uint32_t len: 11, /**< Length of buffer */ + reserved: 4, + bLastBuffer: 1, /**< Last buffer (in the current frame) */ + bNoCRC: 1, /**< No CRC */ + reserved1: 10, + bExhausted: 1, /**< Buffer exhausted in mid frame */ + bUnderrun: 1, /**< Transmit under run */ + bError: 1, /**< Retry limit exceeded, error detected */ + bWrap: 1, /**< Marks last descriptor in TD list */ + bUsed: 1; /**< User clear, GMAC sets this once a frame + has been successfully transmitted */ + } bm; + } status; +} sGmacTxDescriptor; /* GCC */ + +/** @}*/ + +//----------------------------------------------------------------------------- +// PHY Exported functions +//----------------------------------------------------------------------------- +extern uint8_t GMAC_IsIdle(Gmac *pGmac); +extern void GMAC_PHYMaintain(Gmac *pGmac, + uint8_t bPhyAddr, + uint8_t bRegAddr, + uint8_t bRW, + uint16_t wData); +extern uint16_t GMAC_PHYData(Gmac *pGmac); +extern void GMAC_ClearStatistics(Gmac *pGmac); +extern void GMAC_IncreaseStatistics(Gmac *pGmac); +extern void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis); +extern uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck); +extern void GMAC_EnableMdio(Gmac *pGmac); +extern void GMAC_DisableMdio(Gmac *pGmac); +extern void GMAC_EnableMII(Gmac *pGmac); +extern void GMAC_EnableRMII(Gmac *pGmac); +extern void GMAC_EnableGMII(Gmac *pGmac); +extern void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex); +extern void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources, + gmacQueList_t queueIdx); +extern void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources); +extern void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources, + gmacQueList_t queueIdx); +extern void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources); +extern uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetTxStatus(Gmac *pGmac); +extern void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus); +extern uint32_t GMAC_GetRxStatus(Gmac *pGmac); +extern void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus); +extern void GMAC_ReceiveEnable(Gmac *pGmac, uint8_t bEnaDis); +extern void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis); +extern uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac); +extern void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr, + gmacQueList_t queueIdx); +extern uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx); +extern void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr, + gmacQueList_t queueIdx); +extern uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx); +extern void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR); +extern uint32_t GMAC_GetNetworkControl(Gmac *pGmac); +extern void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr); +extern void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, + uint32_t dwMacB); +extern void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac); +extern void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg); +extern void GMAC_SetDMAConfig(Gmac *pGmac, uint32_t dwDmaCfg, + gmacQueList_t queueIdx); +extern uint32_t GMAC_GetDMAConfig(Gmac *pGmac, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetConfigure(Gmac *pGmac); +extern void GMAC_TransmissionStart(Gmac *pGmac); +extern void GMAC_TransmissionHalt(Gmac *pGmac); +extern void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed); + +void GMAC_ClearScreener1Reg (Gmac *pGmac, gmacQueList_t queueIdx); + +void GMAC_WriteScreener1Reg(Gmac *pGmac, gmacQueList_t queueIdx, + uint32_t regVal); + +void GMAC_ClearScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx); + +void GMAC_WriteScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx, + uint32_t regVal); + +void GMAC_WriteEthTypeReg (Gmac *pGmac, gmacQueList_t queueIdx, + uint16_t etherType); + +void GMAC_WriteCompareReg(Gmac *pGmac, gmacQueList_t queueIdx, uint32_t c0Reg, + uint16_t c1Reg); + +void GMAC_EnableCbsQueA(Gmac *pGmac); + +void GMAC_DisableCbsQueA(Gmac *pGmac); + +void GMAC_EnableCbsQueB(Gmac *pGmac); + +void GMAC_DisableCbsQueB(Gmac *pGmac); + +void GMAC_ConfigIdleSlopeA(Gmac *pGmac, uint32_t idleSlopeA); + +void GMAC_ConfigIdleSlopeB(Gmac *pGmac, uint32_t idleSlopeB); + +void GMAC_SetTsuTmrIncReg(Gmac *pGmac, uint32_t nanoSec); + +uint16_t GMAC_GetPtpEvtMsgRxdMsbSec(Gmac *pGmac); + +uint32_t GMAC_GetPtpEvtMsgRxdLsbSec(Gmac *pGmac); + +uint32_t GMAC_GetPtpEvtMsgRxdNanoSec(Gmac *pGmac); + +void GMAC_SetTsuCompare(Gmac *pGmac, uint32_t seconds47, uint32_t seconds31, + uint32_t nanosec); + +void GMAC_SetTsuCompareNanoSec(Gmac *pGmac, uint32_t nanosec); + +void GMAC_SetTsuCompareSec31(Gmac *pGmac, uint32_t seconds31); + +void GMAC_SetTsuCompareSec47(Gmac *pGmac, uint16_t seconds47); + +uint32_t GMAC_GetRxEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetRxEvtFrameNsec(Gmac *pGmac); + +uint32_t GMAC_GetRxPeerEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetRxPeerEvtFrameNsec(Gmac *pGmac); + +uint32_t GMAC_GetTxEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetTxEvtFrameNsec(Gmac *pGmac); + +uint32_t GMAC_GetTxPeerEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetTxPeerEvtFrameNsec(Gmac *pGmac); + +#ifdef __cplusplus +} +#endif + +#endif // #ifndef GMAC_H + diff --git a/bsps/arm/atsam/include/libchip/include/gmacd.h b/bsps/arm/atsam/include/libchip/include/gmacd.h new file mode 100644 index 0000000000..9cda2f8a6c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/gmacd.h @@ -0,0 +1,283 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +/** \addtogroup gmacd_module + * @{ + * Implement GMAC data transfer and PHY management functions. + * + * \section Usage + * -# Implement GMAC interrupt handler, which must invoke GMACD_Handler() + * to handle GMAC interrupt events. + * -# Implement sGmacd instance in application. + * -# Initialize the instance with GMACD_Init() and GMACD_InitTransfer(), + * so that GMAC data can be transmitted/received. + * -# Some management callbacks can be set by GMACD_SetRxCallback() + * and GMACD_SetTxWakeupCallback(). + * -# Send ethernet packets using GMACD_Send(), GMACD_TxLoad() is used + * to check the free space in TX queue. + * -# Check and obtain received ethernet packets via GMACD_Poll(). + * + * \sa \ref gmacb_module, \ref gmac_module + * + * Related files:\n + * \ref gmacd.c\n + * \ref gmacd.h.\n + * + * \defgroup gmacd_defines GMAC Driver Defines + * \defgroup gmacd_types GMAC Driver Types + * \defgroup gmacd_functions GMAC Driver Functions + */ +/**@}*/ + +#ifndef _GMACD_H_ +#define _GMACD_H_ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ +/** \addtogroup gmacd_defines + @{*/ + + +/** \addtogroup gmacd_rc GMACD Return Codes + @{*/ +#define GMACD_OK 0 /**< Operation OK */ +#define GMACD_TX_BUSY 1 /**< TX in progress */ +#define GMACD_RX_NULL 1 /**< No data received */ +/** Buffer size not enough */ +#define GMACD_SIZE_TOO_SMALL 2 +/** Parameter error, TX packet invalid or RX size too small */ +#define GMACD_PARAM 3 +/** Transfer is not initialized */ +#define GMACD_NOT_INITIALIZED 4 +/** @}*/ + +/** @}*/ + +/* Should be a power of 2. + - Buffer Length to store the timestamps of 1588 event messages +*/ +#define EFRS_BUFFER_LEN (1u) + +/*--------------------------------------------------------------------------- +* Types +*---------------------------------------------------------------------------*/ +/** \addtogroup gmacd_types + @{*/ + +typedef enum ptpMsgType_t { + SYNC_MSG_TYPE = 0, + DELAY_REQ_MSG_TYPE = 1, + PDELAY_REQ_TYPE = 2, + PDELAY_RESP_TYPE = 3, + FOLLOW_UP_MSG_TYPE = 8, + DELAY_RESP_MSG_TYPE = 9 +} ptpMsgType; + + + +/** RX callback */ +typedef void (*fGmacdTransferCallback)(uint32_t status); +/** Wakeup callback */ +typedef void (*fGmacdWakeupCallback)(void); +/** Tx PTP message callback */ +typedef void (*fGmacdTxPtpEvtCallBack) (ptpMsgType msg, uint32_t sec, \ + uint32_t nanosec, uint16_t seqId); + +/** + * GMAC scatter-gather entry. + */ +typedef struct _GmacSG { + uint32_t size; + void *pBuffer; +} sGmacSG; + +/** + * GMAC scatter-gather list. + */ +typedef struct _GmacSGList { + uint32_t len; + sGmacSG *sg; +} sGmacSGList; + +/** + * GMAC Queue driver. + */ +typedef struct _GmacQueueDriver { + uint8_t *pTxBuffer; + /** Pointer to allocated RX buffer */ + uint8_t *pRxBuffer; + + /** Pointer to Rx TDs (must be 8-byte aligned) */ + sGmacRxDescriptor *pRxD; + /** Pointer to Tx TDs (must be 8-byte aligned) */ + sGmacTxDescriptor *pTxD; + + /** Optional callback to be invoked once a frame has been received */ + fGmacdTransferCallback fRxCb; + /** Optional callback to be invoked once several TD have been released */ + fGmacdWakeupCallback fWakupCb; + /** Optional callback list to be invoked once TD has been processed */ + fGmacdTransferCallback *fTxCbList; + + /** Optional callback to be invoked on transmit of PTP Event messages */ + fGmacdTxPtpEvtCallBack fTxPtpEvtCb; + + /** RX TD list size */ + uint16_t wRxListSize; + /** RX index for current processing TD */ + uint16_t wRxI; + + /** TX TD list size */ + uint16_t wTxListSize; + /** Circular buffer head pointer by upper layer (buffer to be sent) */ + uint16_t wTxHead; + /** Circular buffer tail pointer incremented by handlers (buffer sent) */ + uint16_t wTxTail; + + /** Number of free TD before wakeup callback is invoked */ + uint8_t bWakeupThreshold; + + /** RX buffer size */ + uint16_t wTxBufferSize; + uint16_t wRxBufferSize; + +} sGmacQd; + +/** + * GMAC driver struct. + */ +typedef struct _GmacDriver { + + /** Pointer to HW register base */ + Gmac *pHw; + /** HW ID */ + uint8_t bId; + /** Base Queue list params **/ + sGmacQd queueList[NUM_GMAC_QUEUES]; +} sGmacd; + +/** + * GMAC driver init struct. + */ +typedef struct _GmacInit { + uint32_t bIsGem: 1; + uint32_t reserved: 31; + + uint8_t bDmaBurstLength; + + /** RX descriptor and data buffers */ + uint8_t *pRxBuffer; + /** RX data buffers: should be wRxBufferSize * wRxSize byte long in a DMA + capable memory region */ + sGmacRxDescriptor *pRxD; + /** RX buffer descriptors: should have wRxSize entries in a DMA + capable memory region */ + uint16_t wRxBufferSize; /** size of a single RX data buffer */ + uint16_t wRxSize; /** number of RX descriptor and data buffers */ + + /** TX descriptor and data buffers */ + /** TX data buffers: should be wTxBufferSize * wTxSize byte long + in a DMA capable memory region */ + uint8_t *pTxBuffer; + /** TX buffer descriptors: should have wTxSize entries + in a DMA capable non-cached memory region */ + sGmacTxDescriptor *pTxD; + /** size of a single TX data buffer */ + uint16_t wTxBufferSize; + /** number of TX descriptor and data buffers */ + uint16_t wTxSize; + + fGmacdTransferCallback *pTxCb; /** should have wTxSize entries */ +} sGmacInit; +/** @}*/ + +/** \addtogroup gmacd_functions + @{*/ + +/*--------------------------------------------------------------------------- + * GMAC Exported functions + *---------------------------------------------------------------------------*/ + +extern void GMACD_Handler(sGmacd *pGmacd , gmacQueList_t queIdx); + +extern void GMACD_Init(sGmacd *pGmacd, + Gmac *pHw, + uint8_t bID, + uint8_t enableCAF, + uint8_t enableNBC); + +extern uint8_t GMACD_InitTransfer(sGmacd *pGmacd, + const sGmacInit *pInit, gmacQueList_t queIdx); + +extern void GMACD_Reset(sGmacd *pGmacd); + +extern uint8_t GMACD_SendSG(sGmacd *pGmacd, + const sGmacSGList *sgl, + fGmacdTransferCallback fTxCb, + gmacQueList_t queIdx); + +extern uint8_t GMACD_Send(sGmacd *pGmacd, + void *pBuffer, + uint32_t size, + fGmacdTransferCallback fTxCb, + gmacQueList_t queIdx); + +extern uint32_t GMACD_TxLoad(sGmacd *pGmacd, gmacQueList_t queIdx); + +extern uint8_t GMACD_Poll(sGmacd *pGmacd, + uint8_t *pFrame, + uint32_t frameSize, + uint32_t *pRcvSize, + gmacQueList_t queIdx); + +extern void GMACD_SetRxCallback(sGmacd *pGmacd, fGmacdTransferCallback + fRxCb, gmacQueList_t queIdx); + +extern uint8_t GMACD_SetTxWakeupCallback(sGmacd *pGmacd, + fGmacdWakeupCallback fWakeup, + uint8_t bThreshold, + gmacQueList_t queIdx); + +extern void GMACD_TxPtpEvtMsgCBRegister (sGmacd *pGmacd, + fGmacdTxPtpEvtCallBack pTxPtpEvtCb, + gmacQueList_t queIdx); + +/** @}*/ + +#endif // #ifndef _GMACD_H_ diff --git a/bsps/arm/atsam/include/libchip/include/hsmci.h b/bsps/arm/atsam/include/libchip/include/hsmci.h new file mode 100644 index 0000000000..f228a3e261 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/hsmci.h @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +/** \addtogroup hsmci_module Working with HSMCI + * \ingroup mcid_module + * + * \section Purpose + * + * The HSMCI driver provides the interface to configure and use the HSMCI + * peripheral. + * + * \section Usage + * + * -# HSMCI_Enable(), MCI_Disable(): Enable/Disable HSMCI interface. + * -# HSMCI_Reset(): Reset HSMCI interface. + * -# HSMCI_Select(): HSMCI slot and buswidth selection + * (\ref Hsmci::HSMCI_SDCR). + * -# HSMCI_ConfigureMode(): Configure the MCI CLKDIV in the _MR register + * (\ref Hsmci::HSMCI_MR). + * -# HSMCI_EnableIt(), HSMCI_DisableIt(), HSMCI_GetItMask(), HSMCI_GetStatus() + * HSMCI Interrupt control (\ref Hsmci::HSMCI_IER, \ref Hsmci::HSMCI_IDR, + * \ref Hsmci::HSMCI_IMR, \ref Hsmci::HSMCI_SR). + * -# HSMCI_ConfigureTransfer(): Setup block length and count for MCI transfer + * (\ref Hsmci::HSMCI_BLKR). + * -# HSMCI_SendCmd(): Send SD/MMC command with argument + * (\ref Hsmci::HSMCI_ARGR, \ref Hsmci::HSMCI_CMDR). + * -# HSMCI_GetResponse(): Get SD/MMC response after command finished + * (\ref Hsmci::HSMCI_RSPR). + * -# HSMCI_ConfigureDma(): Configure MCI DMA transfer + * (\ref Hsmci::HSMCI_DMA). + * -# HSMCI_Configure(): Configure the HSMCI interface (\ref Hsmci::HSMCI_CFG). + * -# HSMCI_HsEnable(), HSMCI_IsHsEnabled(): High Speed control. + * + * For more accurate information, please look at the HSMCI section of the + * Datasheet. + * + * \sa \ref mcid_module + * + * Related files :\n + * \ref hsmci.h\n + * \ref hsmci.c.\n + */ + +#ifndef HSMCID_H +#define HSMCID_H +/** \addtogroup hsmci_module + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup hsmci_functions HSMCI Functions + * @{ + */ + +extern void HSMCI_Enable(Hsmci *pRMci); +extern void HSMCI_Disable(Hsmci *pRMci); +extern void HSMCI_Reset(Hsmci *pRMci, uint8_t bBackup); + +extern void HSMCI_Select(Hsmci *pRMci, uint8_t bSlot, uint8_t bBusWidth); +extern void HSMCI_SetSlot(Hsmci *pRMci, uint8_t bSlot); +extern void HSMCI_SetBusWidth(Hsmci *pRMci, uint8_t bBusWidth); +extern uint8_t HSMCI_GetBusWidth(Hsmci *pRMci); + +extern void HSMCI_ConfigureMode(Hsmci *pRMci, uint32_t dwMode); +extern uint32_t HSMCI_GetMode(Hsmci *pRMci); +extern void HSMCI_ProofEnable(Hsmci *pRMci, uint8_t bRdProof, uint8_t bWrProof); +extern void HSMCI_PadvCtl(Hsmci *pRMci, uint8_t bPadv); +extern void HSMCI_FByteEnable(Hsmci *pRMci, uint8_t bFByteEn); +extern uint8_t HSMCI_IsFByteEnabled(Hsmci *pRMci); +extern void HSMCI_DivCtrl(Hsmci *pRMci, uint32_t bClkDiv, uint8_t bPwsDiv); + +extern void HSMCI_EnableIt(Hsmci *pRMci, uint32_t dwSources); +extern void HSMCI_DisableIt(Hsmci *pRMci, uint32_t dwSources); +extern uint32_t HSMCI_GetItMask(Hsmci *pRMci); + +extern void HSMCI_ConfigureTransfer(Hsmci *pRMci, uint16_t wBlkLen, + uint16_t wCnt); +extern void HSMCI_SetBlockLen(Hsmci *pRMci, uint16_t wBlkSize); +extern void HSMCI_SetBlockCount(Hsmci *pRMci, uint16_t wBlkCnt); + +extern void HSMCI_ConfigureCompletionTO(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_ConfigureDataTO(Hsmci *pRMci, uint32_t dwConfigure); + +extern void HSMCI_SendCmd(Hsmci *pRMci, uint32_t dwCmd, uint32_t dwArg); +extern uint32_t HSMCI_GetResponse(Hsmci *pRMci); +extern uint32_t HSMCI_Read(Hsmci *pRMci); +extern void HSMCI_ReadFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize); +extern void HSMCI_Write(Hsmci *pRMci, uint32_t dwData); +extern void HSMCI_WriteFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize); + +extern uint32_t HSMCI_GetStatus(Hsmci *pRMci); + +extern void HSMCI_ConfigureDma(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_EnableDma(Hsmci *pRMci, uint8_t bEnable); + +extern void HSMCI_Configure(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_HsEnable(Hsmci *pRMci, uint8_t bHsEnable); +extern uint8_t HSMCI_IsHsEnabled(Hsmci *pRMci); + +extern void HSMCI_BusWidthCtl(Hsmci *pRMci, uint8_t bBusWidth); +extern void HSMCI_SlotCtl(Hsmci *pRMci, uint8_t bSlot); +extern uint8_t HSMCI_GetSlot(Hsmci *pRMci); + +extern void HSMCI_ConfigureWP(Hsmci *pRMci, uint32_t dwConfigure); +extern uint32_t HSMCI_GetWPStatus(Hsmci *pRMci); + +#ifdef __cplusplus +} +#endif + +/** @}*/ +/**@}*/ +#endif //#ifndef HSMCID_H + diff --git a/bsps/arm/atsam/include/libchip/include/icm.h b/bsps/arm/atsam/include/libchip/include/icm.h new file mode 100644 index 0000000000..eee19260d5 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/icm.h @@ -0,0 +1,112 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _ICM_ +#define _ICM_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*------------------------------------------------------------------------------*/ +/* Definition */ +/*------------------------------------------------------------------------------*/ +#define ICM_RCFG_CDWBN (0x1u << 0) +/**< \brief (ICM_RCFG) Compare Digest or Write Back Digest */ +#define ICM_RCFG_WRAP (0x1u << 1) +/**< \brief (ICM_RCFG) Wrap Command */ +#define ICM_RCFG_EOM (0x1u << 2) +/**< \brief (ICM_RCFG) End Of Monitoring */ +#define ICM_RCFG_RHIEN (0x1u << 4) +/**< \brief (ICM_RCFG) Region Hash Completed interrupt enable */ +#define ICM_RCFG_DMIEN (0x1u << 5) +/**< \brief (ICM_RCFG) Digest Mismatch interrupt enable */ +#define ICM_RCFG_BEIEN (0x1u << 6) +/**< \brief (ICM_RCFG) Bus error interrupt enable */ +#define ICM_RCFG_WCIEN (0x1u << 7) +/**< \brief (ICM_RCFG) Warp condition interrupt enable */ +#define ICM_RCFG_ECIEN (0x1u << 8) +/**< \brief (ICM_RCFG) End bit condition interrupt enable */ +#define ICM_RCFG_SUIEN (0x1u << 9) +/**< \brief (ICM_RCFG) Monitoring Status Updated Condition Interrupt Enable */ +#define ICM_RCFG_PROCDLY (0x1u << 10) +/**< \brief (ICM_RCFG) Processing Delay*/ +#define ICM_RCFG_UALGO_Pos 12 +#define ICM_RCFG_UALGO_Msk (0x7u << ICM_RCFG_UALGO_Pos) +/**< \brief (ICM_RCFG) User SHA Algorithm */ +#define ICM_RCFG_ALGO_SHA1 (0x0u << 12) +/**< \brief (ICM_RCFG) SHA1 algorithm processed */ +#define ICM_RCFG_ALGO_SHA256 (0x1u << 12) +/**< \brief (ICM_RCFG) SHA256 algorithm processed */ +#define ICM_RCFG_ALGO_SHA224 (0x4u << 12) +/**< \brief (ICM_RCFG) SHA224 algorithm processed */ +#define ICM_RCFG_MRPROT_Pos 24 +#define ICM_RCFG_MRPROT_Msk (0x3fu << ICM_RCFG_MRPROT_Pos) +/**< \brief (ICM_RCFG) Memory Region AHB Protection */ +#define ICM_RCFG_MRPROT(value) \ + ((ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))) + +/*----------------------------------------------------------------------------*/ +/* Type */ +/*----------------------------------------------------------------------------*/ + +/** \brief Structure ICM region descriptor area. */ +typedef struct _LinkedListDescriporIcmRegion { + /** the first byte address of the Region. */ + uint32_t icm_raddr; + /** Configuration Structure Member. */ + uint32_t icm_rcfg; + /** Control Structure Member. */ + uint32_t icm_rctrl; + /** Next Address Structure Member. */ + uint32_t icm_rnext; +} LinkedListDescriporIcmRegion; + +/*----------------------------------------------------------------------------*/ +/* Exported functions */ +/*----------------------------------------------------------------------------*/ +extern void ICM_Enable(void); +extern void ICM_Disable(void); +extern void ICM_SoftReset(void); +extern void ICM_ReComputeHash(uint8_t region); +extern void ICM_EnableMonitor(uint8_t region); +extern void ICM_DisableMonitor(uint8_t region); +extern void ICM_Configure(uint32_t mode); +extern void ICM_EnableIt(uint32_t sources); +extern void ICM_DisableIt(uint32_t sources); +extern uint32_t ICM_GetIntStatus(void); +extern uint32_t ICM_GetStatus(void); +extern uint32_t ICM_GetUStatus(void); +extern void ICM_SetDescStartAddress(uint32_t addr); +extern void ICM_SetHashStartAddress(uint32_t addr); +extern void ICM_SetInitHashValue(uint32_t val); +#endif /* #ifndef _ICM_ */ diff --git a/bsps/arm/atsam/include/libchip/include/isi.h b/bsps/arm/atsam/include/libchip/include/isi.h new file mode 100644 index 0000000000..198dc98039 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/isi.h @@ -0,0 +1,200 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +/** \addtogroup isi_module + * @{ + * \section gmac_usage Usage + * - ISI_Init: initialize ISI with default parameters + * - ISI_EnableInterrupt: enable one or more interrupts + * - ISI_DisableInterrupt: disable one or more interrupts + * - ISI_Enable: enable isi module + * - ISI_Disable: disable isi module + * - ISI_CodecPathFull: enable codec path + * - ISI_SetFrame: set frame rate + * - ISI_BytesForOnePixel: return number of byte for one pixel + * - ISI_StatusRegister: return ISI status register + * - ISI_Reset: make a software reset + */ +/**@}*/ + +#ifndef ISI_H +#define ISI_H + + + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ +#define YUV_INPUT 0 +#define RGB_INPUT 1 +#define GRAYSCALE_INPUT 2 + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** ISI descriptors */ +typedef struct { + /** Current LCD index, used with AT91C_ISI_MAX_PREV_BUFFER */ + uint32_t CurrentLcdIndex; + /** set if Fifo Codec Empty is present */ + volatile uint32_t DisplayCodec; + /** upgrade for each Fifo Codec Overflow (statistics use) */ + uint32_t nb_codec_ovf; + /** upgrade for each Fifo Preview Overflow (statistics use) */ + uint32_t nb_prev_ovf; +} ISI_Descriptors; + +/** Frame Buffer Descriptors */ +typedef struct { + /** Address of the Current FrameBuffer */ + uint32_t Current; + /** Address of the Control */ + uint32_t Control; + /** Address of the Next FrameBuffer */ + uint32_t Next; +} ISI_FrameBufferDescriptors; + + +/** ISI Matrix Color Space Conversion YCrCb to RGB */ +typedef struct { + /** Color Space Conversion Matrix Coefficient C0*/ + uint8_t C0; + /** Color Space Conversion Matrix Coefficient C1 */ + uint8_t C1; + /** Color Space Conversion Matrix Coefficient C2 */ + uint8_t C2; + /** Color Space Conversion Matrix Coefficient C3 */ + uint8_t C3; + /** Color Space Conversion Red Chrominance Default Offset */ + uint8_t Croff; + /** Color Space Conversion Blue Chrominance Default Offset */ + uint8_t Cboff; + /** Color Space Conversion Luminance Default Offset */ + uint8_t Yoff; + /** Color Space Conversion Matrix Coefficient C4 */ + uint16_t C4; +} ISI_Y2R; + +/** ISI Matrix Color Space Conversion RGB to YCrCb */ +typedef struct { + /** Color Space Conversion Matrix Coefficient C0*/ + uint8_t C0; + /** Color Space Conversion Matrix Coefficient C1 */ + uint8_t C1; + /** Color Space Conversion Matrix Coefficient C2 */ + uint8_t C2; + /** Color Space Conversion Red Component Offset */ + uint8_t Roff; + /** Color Space Conversion Matrix Coefficient C3*/ + uint8_t C3; + /** Color Space Conversion Matrix Coefficient C4 */ + uint8_t C4; + /** Color Space Conversion Matrix Coefficient C5 */ + uint8_t C5; + /** Color Space Conversion Green Component Offset */ + uint8_t Goff; + /** Color Space Conversion Matrix Coefficient C6*/ + uint8_t C6; + /** Color Space Conversion Matrix Coefficient C7 */ + uint8_t C7; + /** Color Space Conversion Matrix Coefficient C8 */ + uint8_t C8; + /** Color Space Conversion Blue Component Offset */ + uint8_t Boff; +} ISI_R2Y; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void ISI_Enable(void); + +extern void ISI_Disable(void); + +void ISI_DmaChannelEnable(uint32_t channel); + +void ISI_DmaChannelDisable(uint32_t channel); + +extern void ISI_EnableInterrupt(uint32_t flag); + +extern void ISI_DisableInterrupt(uint32_t flag); + +extern void ISI_CodecPathFull(void); + +extern void ISI_SetFrameRate(uint32_t frame); + +extern uint8_t ISI_BytesForOnePixel(uint8_t bmpRgb); + +extern void ISI_Reset(void); + +extern void ISI_Init(pIsi_Video pVideo); + +extern uint32_t ISI_StatusRegister(void); + +extern void ISI_SetBlank( + uint8_t hBlank, + uint8_t vBlank); + +extern void ISI_SetSensorSize( + uint32_t hSize, + uint32_t vSize); + +extern void ISI_RgbPixelMapping(uint32_t wRgbPixelMapping); + +extern void ISI_RgbSwapMode(uint32_t swapMode); + +extern void ISI_YCrCbFormat(uint32_t wYuvSwapMode); + +extern void ISI_setGrayScaleMode(uint32_t wPixelFormat); + +extern void ISI_setInputStream(uint32_t wStreamMode); + +extern void ISI_setPreviewSize( + uint32_t hSize, + uint32_t vSize); + +extern void ISI_calcScalerFactor(void); + +extern void ISI_setDmaInPreviewPath( + uint32_t baseFrameBufDesc, + uint32_t dmaCtrl, + uint32_t frameBufferStartAddr); + +extern void ISI_setDmaInCodecPath( + uint32_t baseFrameBufDesc, + uint32_t dmaCtrl, + uint32_t frameBufferStartAddr); + +extern void ISI_SetMatrix4Yuv2Rgb (ISI_Y2R *yuv2rgb); +extern void ISI_SetMatrix4Rgb2Yuv (ISI_R2Y *rgb2yuv); + +#endif //#ifndef ISI_H + diff --git a/bsps/arm/atsam/include/libchip/include/iso7816_4.h b/bsps/arm/atsam/include/libchip/include/iso7816_4.h new file mode 100644 index 0000000000..3fa1ce97ea --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/iso7816_4.h @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +//------------------------------------------------------------------------------ +/** \page + * + * \section Purpose + * + * Definition of methods for ISO7816 driver. + * + * \section Usage + * + * -# ISO7816_Init + * -# ISO7816_IccPowerOff + * -# ISO7816_XfrBlockTPDU_T0 + * -# ISO7816_Escape + * -# ISO7816_RestartClock + * -# ISO7816_StopClock + * -# ISO7816_toAPDU + * -# ISO7816_Datablock_ATR + * -# ISO7816_SetDataRateandClockFrequency + * -# ISO7816_StatusReset + * -# ISO7816_cold_reset + * -# ISO7816_warm_reset + * -# ISO7816_Decode_ATR + *----------------------------------------------------------------------------*/ + +#ifndef ISO7816_4_H +#define ISO7816_4_H + +#include "chip.h" + +/*------------------------------------------------------------------------------ + * Constants Definition + *----------------------------------------------------------------------------*/ + +/** Size max of Answer To Reset */ +#define ATR_SIZE_MAX 55 + +/** NULL byte to restart byte procedure */ +#define ISO_NULL_VAL 0x60 + +/*------------------------------------------------------------------------------ + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void ISO7816_Init( + Usart *pUsart, + uint32_t usartId , + const Pin pPinIso7816RstMC); + +extern void ISO7816_IccPowerOff(void); + +extern uint16_t ISO7816_XfrBlockTPDU_T0( + const uint8_t *pAPDU, + uint8_t *pMessage, + uint16_t wLength); + +extern void ISO7816_Escape(void); + +extern void ISO7816_RestartClock(void); + +extern void ISO7816_StopClock(void); + +extern void ISO7816_toAPDU(void); + +extern void ISO7816_Datablock_ATR( + uint8_t *pAtr, + uint8_t *pLength); + +extern void ISO7816_SetDataRateandClockFrequency( + uint32_t dwClockFrequency, + uint32_t dwDataRate); + +extern uint8_t ISO7816_StatusReset(void); + +extern void ISO7816_cold_reset(void); + +extern void ISO7816_warm_reset(void); + +extern void ISO7816_Decode_ATR(uint8_t *pAtr); + +#endif /* ISO7816_4_H */ + diff --git a/bsps/arm/atsam/include/libchip/include/mcan.h b/bsps/arm/atsam/include/libchip/include/mcan.h new file mode 100644 index 0000000000..216c3b07ae --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/mcan.h @@ -0,0 +1,329 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef _MCAN_ +#define _MCAN_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *------------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + CAN_STD_ID = 0, + CAN_EXT_ID = 1 +} MCan_IdType; + +typedef enum { + CAN_DLC_0 = 0, + CAN_DLC_1 = 1, + CAN_DLC_2 = 2, + CAN_DLC_3 = 3, + CAN_DLC_4 = 4, + CAN_DLC_5 = 5, + CAN_DLC_6 = 6, + CAN_DLC_7 = 7, + CAN_DLC_8 = 8, + CAN_DLC_12 = 9, + CAN_DLC_16 = 10, + CAN_DLC_20 = 11, + CAN_DLC_24 = 12, + CAN_DLC_32 = 13, + CAN_DLC_48 = 14, + CAN_DLC_64 = 15 +} MCan_DlcType; + +typedef enum { + CAN_FIFO_0 = 0, + CAN_FIFO_1 = 1 +} MCan_FifoType; + +typedef enum { + CAN_INTR_LINE_0 = 0, + CAN_INTR_LINE_1 = 1 +} MCan_IntrLineType; + +typedef struct MailboxInfoTag { + uint32_t id; + uint32_t length; + uint32_t timestamp; +} MailboxInfoType; + + +typedef struct MailBox8Tag { + MailboxInfoType info; + uint8_t data[8]; +} Mailbox8Type; + +typedef struct MailBox12Tag { + MailboxInfoType info; + uint8_t data[12]; +} Mailbox12Type; + +typedef struct MailBox16Tag { + MailboxInfoType info; + uint8_t data[16]; +} Mailbox16Type; + +typedef struct MailBox20Tag { + MailboxInfoType info; + uint8_t data[20]; +} Mailbox20Type; + +typedef struct MailBox24Tag { + MailboxInfoType info; + uint8_t data[24]; +} Mailbox24Type; + +typedef struct MailBox32Tag { + MailboxInfoType info; + uint8_t data[32]; +} Mailbox32ype; + +typedef struct MailBox48Tag { + MailboxInfoType info; + uint8_t data[48]; +} Mailbox48Type; + +typedef struct MailBox64Tag { + MailboxInfoType info; + uint8_t data[64]; +} Mailbox64Type; + + + +typedef struct MCan_MsgRamPntrsTag { + uint32_t *pStdFilts; + uint32_t *pExtFilts; + uint32_t *pRxFifo0; + uint32_t *pRxFifo1; + uint32_t *pRxDedBuf; + uint32_t *pTxEvtFifo; + uint32_t *pTxDedBuf; + uint32_t *pTxFifoQ; +} MCan_MsgRamPntrs; + +typedef struct MCan_ConfigTag { + Mcan *pMCan; + uint32_t bitTiming; + uint32_t fastBitTiming; + uint32_t nmbrStdFilts; + uint32_t nmbrExtFilts; + uint32_t nmbrFifo0Elmts; + uint32_t nmbrFifo1Elmts; + uint32_t nmbrRxDedBufElmts; + uint32_t nmbrTxEvtFifoElmts; + uint32_t nmbrTxDedBufElmts; + uint32_t nmbrTxFifoQElmts; + uint32_t rxFifo0ElmtSize; + uint32_t rxFifo1ElmtSize; + uint32_t rxBufElmtSize; + // Element sizes and data sizes (encoded element size) + uint32_t txBufElmtSize; + // Element size and data size (encoded element size) + MCan_MsgRamPntrs msgRam; +} MCan_ConfigType; + +extern const MCan_ConfigType mcan0Config; +extern const MCan_ConfigType mcan1Config; + +__STATIC_INLINE uint32_t MCAN_IsTxComplete( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + return (mcan->MCAN_IR & MCAN_IR_TC); +} + +__STATIC_INLINE void MCAN_ClearTxComplete( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_TC; +} + +__STATIC_INLINE uint32_t MCAN_IsMessageStoredToRxDedBuffer( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + + return (mcan->MCAN_IR & MCAN_IR_DRX); +} + +__STATIC_INLINE void MCAN_ClearMessageStoredToRxBuffer( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_DRX; +} + +__STATIC_INLINE uint32_t MCAN_IsMessageStoredToRxFifo0( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + return (mcan->MCAN_IR & MCAN_IR_RF0N); +} + +__STATIC_INLINE void MCAN_ClearMessageStoredToRxFifo0( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_RF0N; +} + +__STATIC_INLINE uint32_t MCAN_IsMessageStoredToRxFifo1( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + return (mcan->MCAN_IR & MCAN_IR_RF1N); +} + +__STATIC_INLINE void MCAN_ClearMessageStoredToRxFifo1( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_RF1N; +} + +void MCAN_Init( + const MCan_ConfigType *mcanConfig); + +void MCAN_InitFdEnable( + const MCan_ConfigType *mcanConfig); + +void MCAN_InitFdBitRateSwitchEnable( + const MCan_ConfigType *mcanConfig); + +void MCAN_InitTxQueue( + const MCan_ConfigType *mcanConfig); + +void MCAN_InitLoopback( + const MCan_ConfigType *mcanConfig); + +void MCAN_Enable( + const MCan_ConfigType *mcanConfig); + +void MCAN_RequestIso11898_1( + const MCan_ConfigType *mcanConfig); + +void MCAN_RequestFd( + const MCan_ConfigType *mcanConfig); + +void MCAN_RequestFdBitRateSwitch( + const MCan_ConfigType *mcanConfig); + +void MCAN_LoopbackOn( + const MCan_ConfigType *mcanConfig); + +void MCAN_LoopbackOff( + const MCan_ConfigType *mcanConfig); + +void MCAN_IEnableMessageStoredToRxDedBuffer( + const MCan_ConfigType *mcanConfig, + MCan_IntrLineType line); + +uint8_t *MCAN_ConfigTxDedBuffer( + const MCan_ConfigType *mcanConfig, + uint8_t buffer, + uint32_t id, + MCan_IdType idType, + MCan_DlcType dlc); + +void MCAN_SendTxDedBuffer( + const MCan_ConfigType *mcanConfig, + uint8_t buffer); + +uint32_t MCAN_AddToTxFifoQ( + const MCan_ConfigType *mcanConfig, + uint32_t id, MCan_IdType idType, + MCan_DlcType dlc, uint8_t *data); + +uint8_t MCAN_IsBufferTxd( + const MCan_ConfigType *mcanConfig, + uint8_t buffer); + +void MCAN_ConfigRxBufferFilter( + const MCan_ConfigType *mcanConfig, + uint32_t buffer, + uint32_t filter, + uint32_t id, + MCan_IdType idType); + +void MCAN_ConfigRxClassicFilter( + const MCan_ConfigType *mcanConfig, + MCan_FifoType fifo, + uint8_t filter, + uint32_t id, + MCan_IdType idType, + uint32_t mask); + +uint8_t MCAN_IsNewDataInRxDedBuffer( + const MCan_ConfigType *mcanConfig, + uint8_t buffer); + +void MCAN_GetRxDedBuffer( + const MCan_ConfigType *mcanConfig, + uint8_t buffer, + Mailbox64Type *pRxMailbox); + +uint32_t MCAN_GetRxFifoBuffer( + const MCan_ConfigType *mcanConfig, + MCan_FifoType fifo, + Mailbox64Type *pRxMailbox); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _MCAN_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/mcid.h b/bsps/arm/atsam/include/libchip/include/mcid.h new file mode 100644 index 0000000000..385f7ad29d --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/mcid.h @@ -0,0 +1,170 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +/** + * \ingroup sdmmc_hal + * \addtogroup mcid_module MCI Driver (HAL for SD/MMC Lib) + * + * \section Purpose + * + * This driver implements SD(IO)/MMC command operations and MCI configuration + * routines to perform SD(IO)/MMC access. It's used for upper layer + * (\ref libsdmmc_module "SD/MMC driver") to perform SD/MMC operations. + * + * \section Usage + * + * -# MCID_Init(): Initializes a MCI driver instance and the underlying + * peripheral. + * -# MCID_SendCmd(): Starts a MCI transfer which described by + * \ref sSdmmcCommand. + * -# MCID_CancelCmd(): Cancel a pending command. + * -# MCID_IsCmdCompleted(): Check if MCI transfer is finished. + * -# MCID_Handler(): Interrupt handler which is called by ISR handler. + * -# MCID_IOCtrl(): IO control function to report HW attributes to upper + * layer driver and modify HW settings (such as clock + * frequency, High-speed support, etc. See + * \ref sdmmc_ioctrls). + * + * \sa \ref dmad_module "DMA Driver", \ref hsmci_module "HSMCI", + * \ref libsdmmc_module "SD/MMC Library" + * + * Related files:\n + * \ref mcid.h\n + * \ref mcid_dma.c.\n + */ + +#ifndef MCID_H +#define MCID_H +/** \addtogroup mcid_module + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/** \addtogroup mcid_defines MCI Driver Defines + * @{*/ + +/*---------------------------------------------------------------------------- + * Constants + *----------------------------------------------------------------------------*/ + +/** MCI States */ +#define MCID_IDLE 0 /**< Idle */ +#define MCID_LOCKED 1 /**< Locked for specific slot */ +#define MCID_CMD 2 /**< Processing the command */ +#define MCID_ERROR 3 /**< Command error */ + +/** MCI Initialize clock 400K Hz */ +#define MCI_INITIAL_SPEED 400000 + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup mcid_structs MCI Driver Data Structs + * @{ + */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief MCI Driver + */ +typedef struct _Mcid { + /** Pointer to a MCI peripheral. */ + Hsmci *pMciHw; + /** Pointer to a DMA driver */ + sXdmad *pXdmad; + /** Pointer to currently executing command. */ + void *pCmd; + /** MCK source, Hz */ + uint32_t dwMck; + /** DMA transfer channel */ + uint32_t dwDmaCh; + /** DMA transferred data index (bytes) */ + uint32_t dwXfrNdx; + /** DMA transfer size (bytes) */ + uint32_t dwXSize; + /** MCI peripheral identifier. */ + uint8_t bID; + /** Polling mode */ + uint8_t bPolling; + /** Reserved */ + uint8_t reserved; + /** state. */ + volatile uint8_t bState; +} sMcid; + +/** @}*/ +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup mcid_functions MCI Driver Functions + @{*/ +extern void MCID_Init(sMcid *pMcid, + Hsmci *pMci, uint8_t bID, uint32_t dwMck, + sXdmad *pXdmad, + uint8_t bPolling); + +extern void MCID_Reset(sMcid *pMcid); + +extern void MCID_SetSlot(Hsmci *pMci, uint8_t slot); + +extern uint32_t MCID_Lock(sMcid *pMcid, uint8_t bSlot); + +extern uint32_t MCID_Release(sMcid *pMcid); + +extern void MCID_Handler(sMcid *pMcid); + +extern uint32_t MCID_SendCmd(sMcid *pMcid, void *pCmd); + +extern uint32_t MCID_CancelCmd(sMcid *pMcid); + +extern uint32_t MCID_IsCmdCompleted(sMcid *pMcid); + +extern uint32_t MCID_IOCtrl(sMcid *pMcid, uint32_t bCtl, uint32_t param); + +#ifdef __cplusplus +} +#endif +/** @}*/ +/**@}*/ +#endif //#ifndef HSMCID_H + diff --git a/bsps/arm/atsam/include/libchip/include/mediaLB.h b/bsps/arm/atsam/include/libchip/include/mediaLB.h new file mode 100644 index 0000000000..566c444b01 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/mediaLB.h @@ -0,0 +1,45 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _MEDILB_H_ +#define _MEDILB_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + + + +#endif /* #ifndef _MEDILB_H_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/mpu.h b/bsps/arm/atsam/include/libchip/include/mpu.h new file mode 100644 index 0000000000..06f70d5d62 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/mpu.h @@ -0,0 +1,222 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _MPU_H_ +#define _MPU_H_ +#ifdef __rtems__ +#include +#endif /* __rtems__ */ + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +#define ARM_MODE_USR 0x10 + +#define PRIVILEGE_MODE 0 +#define USER_MODE 1 + +#define MPU_DEFAULT_ITCM_REGION (1) +#define MPU_DEFAULT_IFLASH_REGION (2) +#define MPU_DEFAULT_DTCM_REGION (3) +#define MPU_DEFAULT_SRAM_REGION_1 (4) +#define MPU_DEFAULT_SRAM_REGION_2 (5) +#define MPU_PERIPHERALS_REGION (6) +#define MPU_EXT_EBI_REGION (7) +#define MPU_DEFAULT_SDRAM_REGION (8) +#define MPU_QSPIMEM_REGION (9) +#define MPU_USBHSRAM_REGION (10) +#if defined MPU_HAS_NOCACHE_REGION + #define MPU_NOCACHE_SRAM_REGION (11) +#endif +#define MPU_SYSTEM_REGION (12) + +#define MPU_REGION_VALID (0x10) +#define MPU_REGION_ENABLE (0x01) +#define MPU_REGION_DISABLE (0x0) + +#define MPU_ENABLE (0x1 << MPU_CTRL_ENABLE_Pos) +#define MPU_HFNMIENA (0x1 << MPU_CTRL_HFNMIENA_Pos) +#define MPU_PRIVDEFENA (0x1 << MPU_CTRL_PRIVDEFENA_Pos) + + +#define MPU_REGION_BUFFERABLE (0x01 << MPU_RASR_B_Pos) +#define MPU_REGION_CACHEABLE (0x01 << MPU_RASR_C_Pos) +#define MPU_REGION_SHAREABLE (0x01 << MPU_RASR_S_Pos) + +#define MPU_REGION_EXECUTE_NEVER (0x01 << MPU_RASR_XN_Pos) + +#define MPU_AP_NO_ACCESS (0x00 << MPU_RASR_AP_Pos) +#define MPU_AP_PRIVILEGED_READ_WRITE (0x01 << MPU_RASR_AP_Pos) +#define MPU_AP_UNPRIVILEGED_READONLY (0x02 << MPU_RASR_AP_Pos) +#define MPU_AP_FULL_ACCESS (0x03 << MPU_RASR_AP_Pos) +#define MPU_AP_RES (0x04 << MPU_RASR_AP_Pos) +#define MPU_AP_PRIVILEGED_READONLY (0x05 << MPU_RASR_AP_Pos) +#define MPU_AP_READONLY (0x06 << MPU_RASR_AP_Pos) +#define MPU_AP_READONLY2 (0x07 << MPU_RASR_AP_Pos) + +#define MPU_TEX_B000 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B001 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B010 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B011 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B100 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B101 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B110 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B111 (0x01 << MPU_RASR_TEX_Pos) + +/* Default memory map + Address range Memory region Memory type Shareability Cache policy + 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT + 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA + 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable - + 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA + 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT + 0xA0000000- 0xBFFFFFFF Device Device Shareable + 0xC0000000- 0xDFFFFFFF Device Device Non Shareable + 0xE0000000- 0xFFFFFFFF System - - + */ + +/********* IFLASH memory macros *********************/ +#ifdef __rtems__ +#define ITCM_START_ADDRESS ((uintptr_t) atsam_memory_itcm_begin) +#define ITCM_END_ADDRESS ((uintptr_t) atsam_memory_itcm_end - 1) +#define IFLASH_START_ADDRESS ((uintptr_t) atsam_memory_intflash_begin) +#define IFLASH_END_ADDRESS ((uintptr_t) atsam_memory_intflash_end - 1) +#else /* !__rtems__ */ +#define ITCM_START_ADDRESS 0x00000000UL +#define ITCM_END_ADDRESS 0x003FFFFFUL +#define IFLASH_START_ADDRESS 0x00400000UL +#define IFLASH_END_ADDRESS 0x005FFFFFUL +#endif /* __rtems__ */ + + +#define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS) +#define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF) + +#define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1) +#define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS) + +/**************** DTCM *******************************/ +#ifdef __rtems__ +#define DTCM_START_ADDRESS ((uintptr_t) atsam_memory_dtcm_begin) +#define DTCM_END_ADDRESS ((uintptr_t) atsam_memory_dtcm_end - 1) +#else /* !__rtems__ */ +#define DTCM_START_ADDRESS 0x20000000UL +#define DTCM_END_ADDRESS 0x203FFFFFUL +#endif /* __rtems__ */ + + +/******* SRAM memory macros ***************************/ + +#ifdef __rtems__ +#define SRAM_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin) +#define SRAM_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1) +#else /* !__rtems__ */ +#define SRAM_START_ADDRESS 0x20400000UL +#define SRAM_END_ADDRESS 0x2045FFFFUL +#endif /* __rtems__ */ + +#ifndef __rtems__ +#if defined MPU_HAS_NOCACHE_REGION + #define NOCACHE_SRAM_REGION_SIZE 0x1000 +#endif +#endif /* __rtems__ */ + +/* Regions should be a 2^(N+1) where 4 < N < 31 */ +#ifdef __rtems__ +#define SRAM_FIRST_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin) +#define SRAM_FIRST_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1) +#else /* !__rtems__ */ +#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS) +#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB +#endif /* __rtems__ */ + +#if defined MPU_HAS_NOCACHE_REGION +#ifdef __rtems__ + #define SRAM_NOCACHE_START_ADDRESS ((uintptr_t) atsam_memory_nocache_begin) + #define SRAM_NOCACHE_END_ADDRESS ((uintptr_t) atsam_memory_nocache_end - 1) + #define NOCACHE_SRAM_REGION_SIZE (SRAM_NOCACHE_END_ADDRESS - SRAM_NOCACHE_START_ADDRESS) +#else /* !__rtems__ */ + #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1) + #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE) // (2^17) 128 - 0x1000 KB + #define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1) + #define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS) +#endif /* __rtems__ */ +#else +#ifndef __rtems__ + #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1) + #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB +#endif /* __rtems__ */ +#endif +/************** Peripherals memory region macros ********/ +#define PERIPHERALS_START_ADDRESS 0x40000000UL +#define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL +#ifdef __rtems__ +#define SYSTEM_START_ADDRESS 0xE0000000UL +#define SYSTEM_END_ADDRESS 0xFFFFFFFFUL +#endif /* __rtems__ */ + +/******* Ext EBI memory macros ***************************/ +#define EXT_EBI_START_ADDRESS 0x60000000UL +#define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL + +/******* Ext-SRAM memory macros ***************************/ +#ifdef __rtems__ +#define SDRAM_START_ADDRESS ((uintptr_t) atsam_memory_sdram_begin) +#define SDRAM_END_ADDRESS ((uintptr_t) atsam_memory_sdram_end - 1) +#else /* !__rtems__ */ +#define SDRAM_START_ADDRESS 0x70000000UL +#define SDRAM_END_ADDRESS 0x7FFFFFFFUL +#endif /* __rtems__ */ + +/******* QSPI macros ***************************/ +#ifdef __rtems__ +#define QSPI_START_ADDRESS ((uintptr_t) atsam_memory_qspiflash_begin) +#define QSPI_END_ADDRESS ((uintptr_t) atsam_memory_qspiflash_end - 1) +#else /* !__rtems__ */ +#define QSPI_START_ADDRESS 0x80000000UL +#define QSPI_END_ADDRESS 0x9FFFFFFFUL +#endif /* __rtems__ */ + +/************** USBHS_RAM region macros ******************/ +#define USBHSRAM_START_ADDRESS 0xA0100000UL +#define USBHSRAM_END_ADDRESS 0xA01FFFFFUL + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ +void MPU_Enable(uint32_t dwMPUEnable); +void MPU_SetRegion(uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr); +void MPU_SetRegionNum(uint32_t dwRegionNum); +void MPU_DisableRegion(void); +uint32_t MPU_CalMPURegionSize(uint32_t dwActualSizeInBytes); +void MPU_UpdateRegions(uint32_t dwRegionNum, uint32_t dwRegionBaseAddr, + uint32_t dwRegionAttr); + +#endif /* #ifndef _MMU_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/pio.h b/bsps/arm/atsam/include/libchip/include/pio.h new file mode 100644 index 0000000000..6cf463d1ec --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/pio.h @@ -0,0 +1,217 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * This file provides a basic API for PIO configuration and usage of + * user-controlled pins. Please refer to the board.h file for a list of + * available pin definitions. + * + * \section Usage + * + * -# Define a constant pin description array such as the following one, using + * the existing definitions provided by the board.h file if possible: + * \code + * const Pin pPins[] = {PIN_USART0_TXD, PIN_USART0_RXD}; + * \endcode + * Alternatively, it is possible to add new pins by provided the full Pin + * structure: + * \code + * // Pin instance to configure PA10 & PA11 as inputs with the internal + * // pull-up enabled. + * const Pin pPins = { + * (1 << 10) | (1 << 11), + * REG_PIOA, + * ID_PIOA, + * PIO_INPUT, + * PIO_PULLUP + * }; + * \endcode + * -# Configure a pin array by calling PIO_Configure() with a pointer to the + * array and its size (which is computed using the PIO_LISTSIZE macro). + * -# Change and get the value of a user-controlled pin using the PIO_Set, + * PIO_Clear and PIO_Get methods. + * -# Get the level being currently output by a user-controlled pin configured + * as an output using PIO_GetOutputDataStatus(). + */ + +#ifndef _PIO_ +#define _PIO_ + +/* + * Headers + */ + +#include "chip.h" + +#include + +/* + * Global Definitions + */ + +/** The pin is controlled by the associated signal of peripheral A. */ +#define PIO_PERIPH_A 0 +/** The pin is controlled by the associated signal of peripheral B. */ +#define PIO_PERIPH_B 1 +/** The pin is controlled by the associated signal of peripheral C. */ +#define PIO_PERIPH_C 2 +/** The pin is controlled by the associated signal of peripheral D. */ +#define PIO_PERIPH_D 3 +/** The pin is an input. */ +#define PIO_INPUT 4 +/** The pin is an output and has a default level of 0. */ +#define PIO_OUTPUT_0 5 +/** The pin is an output and has a default level of 1. */ +#define PIO_OUTPUT_1 6 + +/** Default pin configuration (no attribute). */ +#define PIO_DEFAULT (0 << 0) +/** The internal pin pull-up is active. */ +#define PIO_PULLUP (1 << 0) +/** The internal glitch filter is active. */ +#define PIO_DEGLITCH (1 << 1) +/** The pin is open-drain. */ +#define PIO_OPENDRAIN (1 << 2) + +/** The internal debouncing filter is active. */ +#define PIO_DEBOUNCE (1 << 3) + +/** Enable additional interrupt modes. */ +#define PIO_IT_AIME (1 << 4) + +/** Interrupt High Level/Rising Edge detection is active. */ +#define PIO_IT_RE_OR_HL (1 << 5) +/** Interrupt Edge detection is active. */ +#define PIO_IT_EDGE (1 << 6) + +/** Low level interrupt is active */ +#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME) +/** High level interrupt is active */ +#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME) +/** Falling edge interrupt is active */ +#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME) +/** Rising edge interrupt is active */ +#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME) +/** The WP is enable */ +#define PIO_WPMR_WPEN_EN (0x01 << 0) +/** The WP is disable */ +#define PIO_WPMR_WPEN_DIS (0x00 << 0) +/** Valid WP key */ +#define PIO_WPMR_WPKEY_VALID (0x50494F << 8) +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Global Macros + */ + +/** + * Calculates the size of an array of Pin instances. The array must be defined + * locally (i.e. not a pointer), otherwise the computation will not be correct. + * \param pPins Local array of Pin instances. + * \return Number of elements in array. + */ +#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin)) + +/* + * Global Types + */ + + +/* + * Describes the type and attribute of one PIO pin or a group of similar pins. + * The #type# field can have the following values: + * - PIO_PERIPH_A + * - PIO_PERIPH_B + * - PIO_OUTPUT_0 + * - PIO_OUTPUT_1 + * - PIO_INPUT + * + * The #attribute# field is a bitmask that can either be set to PIO_DEFAULt, + * or combine (using bitwise OR '|') any number of the following constants: + * - PIO_PULLUP + * - PIO_DEGLITCH + * - PIO_DEBOUNCE + * - PIO_OPENDRAIN + * - PIO_IT_LOW_LEVEL + * - PIO_IT_HIGH_LEVEL + * - PIO_IT_FALL_EDGE + * - PIO_IT_RISE_EDGE + */ +typedef struct _Pin { + /* Bitmask indicating which pin(s) to configure. */ + uint32_t mask; + /* Pointer to the PIO controller which has the pin(s). */ + Pio *pio; + /* Peripheral ID of the PIO controller which has the pin(s). */ + uint8_t id; + /* Pin type. */ + uint8_t type; + /* Pin attribute. */ + uint8_t attribute; +} Pin; + +/* + * Global Access Macros + */ + +/* + * Global Functions + */ + +extern uint8_t PIO_Configure(const Pin *list, uint32_t size); + +extern void PIO_Set(const Pin *pin); + +extern void PIO_Clear(const Pin *pin); + +extern uint8_t PIO_Get(const Pin *pin); + +extern uint8_t PIO_GetOutputDataStatus(const Pin *pin); + +extern void PIO_SetDebounceFilter(const Pin *pin, uint32_t cuttoff); + +extern void PIO_EnableWriteProtect(const Pin *pin); + +extern void PIO_DisableWriteProtect(const Pin *pin); + +extern void PIO_SetPinType(Pin *pin, uint8_t pinType); + +extern uint32_t PIO_GetWriteProtectViolationInfo(const Pin *pin); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PIO_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/pio_capture.h b/bsps/arm/atsam/include/libchip/include/pio_capture.h new file mode 100644 index 0000000000..087b19d0b4 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/pio_capture.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef PIO_CAPTURE_H +#define PIO_CAPTURE_H + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** \brief PIO Parallel Capture structure for initialize. + * + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct _SpioCaptureInit { + + /** PIO_PCRHR register is a BYTE, HALF-WORD or WORD */ + uint8_t dsize; + /** PDC size, data to be received */ + uint16_t dPDCsize; + /** Data to be received */ + uint32_t *pData; + /** Parallel Capture Mode Always Sampling */ + uint8_t alwaysSampling; + /** Parallel Capture Mode Half Sampling */ + uint8_t halfSampling; + /** Parallel Capture Mode First Sample */ + uint8_t modeFirstSample; + /** Callback function invoked at Mode Data Ready */ + void (*CbkDataReady)(struct _SpioCaptureInit *); + /** Callback function invoked at Mode Overrun Error */ + void (*CbkOverrun)(struct _SpioCaptureInit *); + /** Callback function invoked at End of Reception Transfer */ + void (*CbkEndReception)(struct _SpioCaptureInit *); + /** Callback function invoked at Reception Buffer Full */ + void (*CbkBuffFull)(struct _SpioCaptureInit *); + /** Callback arguments.*/ + void *pParam; + +} SpioCaptureInit; + + +/*---------------------------------------------------------------------------- + * Global Functions + *----------------------------------------------------------------------------*/ +extern void PIO_CaptureDisableIt(uint32_t itToDisable); +extern void PIO_CaptureEnableIt(uint32_t itToEnable); +extern void PIO_CaptureEnable(void); +extern void PIO_CaptureDisable(void); +extern void PIO_CaptureInit(SpioCaptureInit *pInit); + +#endif /* #ifndef PIO_CAPTURE_H */ + diff --git a/bsps/arm/atsam/include/libchip/include/pio_it.h b/bsps/arm/atsam/include/libchip/include/pio_it.h new file mode 100644 index 0000000000..b03973caa1 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/pio_it.h @@ -0,0 +1,117 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \par Purpose + * + * Configuration and handling of interrupts on PIO status changes. The API + * provided here have several advantages over the traditional PIO interrupt + * configuration approach: + * - It is highly portable + * - It automatically demultiplexes interrupts when multiples pins have been + * configured on a single PIO controller + * - It allows a group of pins to share the same interrupt + * + * However, it also has several minor drawbacks that may prevent from using it + * in particular applications: + * - It enables the clocks of all PIO controllers + * - PIO controllers all share the same interrupt handler, which does the + * demultiplexing and can be slower than direct configuration + * - It reserves space for a fixed number of interrupts, which can be + * increased by modifying the appropriate constant in pio_it.c. + * + * \par Usage + * + * -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts() + * with the desired priority (0 ... 7). + * -# Configure a status change interrupt on one or more pin(s) with + * PIO_ConfigureIt(). + * -# Enable & disable interrupts on pins using PIO_EnableIt() and + * PIO_DisableIt(). + */ + +#ifndef _PIO_IT_ +#define _PIO_IT_ + +/* + * Headers + */ + +#include "pio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Global functions + */ + +extern void PIO_InitializeInterrupts(uint32_t dwPriority); + +extern void PIO_ConfigureIt(const Pin *pPin, + void (*handler)(const Pin *, void *arg), void *arg); + + +/** + * Enables the given interrupt source if it has been configured. The status + * register of the corresponding PIO controller is cleared prior to enabling + * the interrupt. + * \param pPin Interrupt source to enable. + */ +static inline void PIO_EnableIt(const Pin *pPin) +{ + pPin->pio->PIO_ISR; + pPin->pio->PIO_IER = pPin->mask; +} + +/** + * Disables a given interrupt source, with no added side effects. + * + * \param pPin Interrupt source to disable. + */ +static inline void PIO_DisableIt(const Pin *pPin) +{ + pPin->pio->PIO_IDR = pPin->mask; +} + +extern void PIO_IT_InterruptHandler(void); + +extern void PioInterruptHandler(uint32_t id, Pio *pPio); + +extern void PIO_CaptureHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PIO_IT_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/pmc.h b/bsps/arm/atsam/include/libchip/include/pmc.h new file mode 100644 index 0000000000..4494513fff --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/pmc.h @@ -0,0 +1,101 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _PMC_ +#define _PMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include + + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* Definition for fast RC frequency */ +#define FAST_RC_4MHZ CKGR_MOR_MOSCRCF_4MHz +#define FAST_RC_8MHZ CKGR_MOR_MOSCRCF_8MHz +#define FAST_RC_12MHZ CKGR_MOR_MOSCRCF_12MHz + +/* Definitions for startup count. + * Note: 1 count unit stand for: 1 / 32768 * 8 = 244 us + */ +/* Default startup count for 4/8/12MHz fast RC (startup time: 10us) */ +#define DEFAUTL_FAST_RC_COUNT 1 +/* Default startup count for 3-20MHz main oscillator (startup time: 1.4ms) */ +#define DEFAUTL_MAIN_OSC_COUNT 8 +/* Default startup count for PLLA (startup time: 200us) */ +#define DEFAUTL_PLLA_COUNT 1 +/* Default startup count for UPLL */ +#define DEFAUTL_UPLL_COUNT 3 +/* No change for default startup count */ +#define DEFAUTL_COUNT_NO_CHANGE 0xFFFF + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void PMC_EnablePeripheral(uint32_t dwId); +extern void PMC_DisablePeripheral(uint32_t dwId); + +extern void PMC_EnableAllPeripherals(void); +extern void PMC_DisableAllPeripherals(void); + +extern uint32_t PMC_IsPeriphEnabled(uint32_t dwId); + +extern void PMC_SelectExtOsc(void); +extern void PMC_EnableExtOsc(void); +extern void PMC_DisableExtOsc(void); +extern void PMC_SelectExtBypassOsc(void); +extern void PMC_EnableIntRC4_8_12MHz(uint32_t fastRcFreq); +extern void PMC_DisableIntRC4_8_12MHz(void); +extern void PMC_SetPllaClock(uint32_t mul, uint32_t div); +extern void PMC_SetPllbClock(uint32_t mul, uint32_t div); +extern void PMC_SetMckSelection(uint32_t clockSource, uint32_t prescaler); +extern void PMC_DisableAllClocks(void); +extern void PMC_ConfigureMckWithPlla(uint32_t mul, uint32_t div, + uint32_t prescaler); +extern void PMC_ConfigureMckWithPllb(uint32_t mul, uint32_t div, + uint32_t prescaler); +extern void PMC_EnableXT32KFME(void); +extern void PMC_ConfigurePCK0(uint32_t MasterClk, uint32_t prescaler); +extern void PMC_ConfigurePCK1(uint32_t MasterClk, uint32_t prescaler); +extern void PMC_ConfigurePCK2(uint32_t MasterClk, uint32_t prescaler); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PMC_ */ diff --git a/bsps/arm/atsam/include/libchip/include/pwmc.h b/bsps/arm/atsam/include/libchip/include/pwmc.h new file mode 100644 index 0000000000..fccfb15556 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/pwmc.h @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \par Purpose + * + * Interface for configuration the Pulse Width Modulation Controller (PWM) + * peripheral. + * + * \par Usage + * + * -# Configures PWM clocks A & B to run at the given frequencies using + * \ref PWMC_ConfigureClocks(). + * -# Configure PWMC channel using \ref PWMC_ConfigureChannel(), + * \ref PWMC_ConfigureChannelExt() + * \ref PWMC_SetPeriod(), \ref PWMC_SetDutyCycle() and + * \ref PWMC_SetDeadTime(). + * -# Enable & disable channel using \ref PWMC_EnableChannel() and + * \ref PWMC_DisableChannel(). + * -# Enable & disable the period interrupt for the given PWM channel using + * \ref PWMC_EnableChannelIt() and \ref PWMC_DisableChannelIt(). + * -# Enable & disable the selected interrupts sources on a PWMC peripheral + * using \ref PWMC_EnableIt() and \ref PWMC_DisableIt(). + * -# Control synchronous channel using \ref PWMC_ConfigureSyncChannel(), + * \ref PWMC_SetSyncChannelUpdatePeriod() and + * \ref PWMC_SetSyncChannelUpdateUnlock(). + * -# Control PWM override output using \ref PWMC_SetOverrideValue(), + * \ref PWMC_EnableOverrideOutput() and \ref PWMC_DisableOverrideOutput(). + * -# Send data through the transmitter using \ref PWMC_WriteBuffer(). + * + */ + +#ifndef _PWMC_ +#define _PWMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void PWMC_ConfigureChannel( + Pwm *pPwm, + uint8_t channel, + uint32_t prescaler, + uint32_t alignment, + uint32_t polarity); +extern void PWMC_ConfigureChannelExt( + Pwm *pPwm, + uint8_t channel, + uint32_t prescaler, + uint32_t alignment, + uint32_t polarity, + uint32_t countEventSelect, + uint32_t DTEnable, + uint32_t DTHInverte, + uint32_t DTLInverte); +extern void PWMC_ConfigureClocks(Pwm *pPwm, uint32_t clka, uint32_t clkb, + uint32_t mck); +extern void PWMC_SetPeriod(Pwm *pPwm, uint8_t channel, uint16_t period); +extern void PWMC_SetDutyCycle(Pwm *pPwm, uint8_t channel, uint16_t duty); +extern void PWMC_SetDeadTime(Pwm *pPwm, uint8_t channel, uint16_t timeH, + uint16_t timeL); +extern void PWMC_ConfigureSyncChannel(Pwm *pPwm, + uint32_t channels, + uint32_t updateMode, + uint32_t requestMode, + uint32_t requestComparisonSelect); +extern void PWMC_SetSyncChannelUpdatePeriod(Pwm *pPwm, uint8_t period); +extern void PWMC_SetSyncChannelUpdateUnlock(Pwm *pPwm); +extern void PWMC_EnableChannel(Pwm *pPwm, uint8_t channel); +extern void PWMC_DisableChannel(Pwm *pPwm, uint8_t channel); +extern void PWMC_EnableChannelIt(Pwm *pPwm, uint8_t channel); +extern void PWMC_DisableChannelIt(Pwm *pPwm, uint8_t channel); +extern void PWMC_EnableIt(Pwm *pPwm, uint32_t sources1, uint32_t sources2); +extern void PWMC_DisableIt(Pwm *pPwm, uint32_t sources1, uint32_t sources2); +extern uint8_t PWMC_WriteBuffer(Pwm *pwmc, + void *buffer, + uint32_t length); +extern void PWMC_SetOverrideValue(Pwm *pPwm, uint32_t value); +extern void PWMC_EnableOverrideOutput(Pwm *pPwm, uint32_t value, + uint32_t sync); +extern void PWMC_OutputOverrideSelection(Pwm *pPwm, uint32_t value); +extern void PWMC_DisableOverrideOutput(Pwm *pPwm, uint32_t value, + uint32_t sync); +extern void PWMC_SetFaultMode(Pwm *pPwm, uint32_t mode); +extern void PWMC_FaultClear(Pwm *pPwm, uint32_t fault); +extern void PWMC_SetFaultProtectionValue(Pwm *pPwm, uint32_t value); +extern void PWMC_EnableFaultProtection(Pwm *pPwm, uint32_t value); +extern void PWMC_ConfigureComparisonUnit(Pwm *pPwm, uint32_t x, + uint32_t value, uint32_t mode); +extern void PWMC_ConfigureEventLineMode(Pwm *pPwm, uint32_t x, uint32_t mode); +extern uint32_t PWMC_GetStatus2(Pwm *pPwm); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PWMC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/qspi.h b/bsps/arm/atsam/include/libchip/include/qspi.h new file mode 100644 index 0000000000..c1f81f6ad6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/qspi.h @@ -0,0 +1,236 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + + +/** + * \file + * + * Interface for Serial Peripheral Interface (SPI) controller. + * + */ + +#ifndef _QSPI_ +#define _QSPI_ +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** + * + * Here are several macros which should be used when configuring a SPI + * peripheral. + * + * \section qspi_configuration_macros SPI Configuration Macros + * - \ref QSPI_PCS + * - \ref QSPI_SCBR + * - \ref QSPI_DLYBS + * - \ref QSPI_DLYBCT + */ + +/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */ +#define QSPI_SCBR(baudrate, masterClock) \ + ((uint32_t) (masterClock / baudrate) << 8) + +/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ +#define QSPI_DLYBS(delay, masterClock) \ + ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16) + +/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */ +#define QSPI_DLYBCT(delay, masterClock) \ + ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24) + +/*--------------------------------------------------------------------------- */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** \brief qspi access modes + */ +typedef enum { + CmdAccess = 0, + ReadAccess, + WriteAccess +} Access_t; + +/** \brief qspi modes SPI or QSPI + */ +typedef enum { + SpiMode = QSPI_MR_SMM_SPI, + QspiMemMode = QSPI_MR_SMM_MEMORY +} QspiMode_t; + + +/** \brief qspi clock modes , regarding clock phase and clock polarity + */ +typedef enum { + ClockMode_00 = 0, + ClockMode_10, + ClockMode_01, + ClockMode_11 +} QspiClockMode_t; + + +/** \brief qspi status codes + */ +typedef enum { + QSPI_SUCCESS = 0, + QSPI_BUSY, + QSPI_BUSY_SENDING, + QSPI_READ_ERROR, + QSPI_WRITE_ERROR, + QSPI_UNKNOWN_ERROR, + QSPI_INIT_ERROR, + QSPI_INPUT_ERROR, + QSPI_TOTAL_ERROR +} QspidStatus_t; + + +/** \brief qspi status regiter bits + */ +typedef enum { + IsReceived = QSPI_SR_RDRF, + IsTxSent = QSPI_SR_TDRE, + IsTxEmpty = QSPI_SR_TXEMPTY, + IsOverrun = QSPI_SR_OVRES, + IsCsRise = QSPI_SR_CSR, + IsCsAsserted = QSPI_SR_CSS, + IsEofInst = QSPI_SR_INSTRE, + IsEnabled = QSPI_SR_QSPIENS +} QspiStatus_t; + +/** \brief qspi command structure + */ +typedef struct { + uint8_t Instruction; + uint8_t Option; +} QspiMemCmd_t; + +/** \brief qspi buffer structure + */ +typedef struct { + uint32_t TxDataSize; /* Tx buffer size */ + uint32_t RxDataSize; /* Rx buffer size */ + const void *pDataTx; /* Tx buffer */ + void *pDataRx; /* Rx buffer */ +} QspiBuffer_t; + + +/** \brief qspi frame structure for QSPI mode + */ +typedef struct { + union _QspiInstFrame { + uint32_t val; + struct _QspiInstFrameBM { + uint32_t bwidth: 3, /** Width of QSPI Addr , inst data */ + reserved0: 1, /** Reserved*/ + bInstEn: 1, /** Enable Inst */ + bAddrEn: 1, /** Enable Address */ + bOptEn: 1, /** Enable Option */ + bDataEn: 1, /** Enable Data */ + bOptLen: 2, /** Option Length*/ + bAddrLen: 1, /** Addrs Length*/ + reserved1: 1, /** Option Length*/ + bXfrType: 2, /** Transfer type*/ + bContinuesRead: 1, /** Continoues read mode*/ + reserved2: 1, /** Reserved*/ + bDummyCycles: 5, /**< Unicast hash match */ + reserved3: 11; /** Reserved*/ + } bm; + } InstFrame; + uint32_t Addr; +} QspiInstFrame_t; + +/** \brief qspi driver structure + */ +typedef struct { + uint8_t qspiId; /* QSPI ID */ + Qspi *pQspiHw; /* QSPI Hw instance */ + QspiMode_t qspiMode; /* Qspi mode: SPI or QSPI */ + QspiMemCmd_t qspiCommand; /* Qspi command structure*/ + QspiBuffer_t qspiBuffer; /* Qspi buffer*/ + QspiInstFrame_t *pQspiFrame; /* Qspi QSPI mode Fram register informations*/ +} Qspid_t; + + +void QSPI_SwReset(Qspi *pQspi); + +void QSPI_Disable(Qspi *pQspi); + +void QSPI_Enable(Qspi *pQspi); + +QspidStatus_t QSPI_EndTransfer(Qspi *pQspi); + +uint32_t QSPI_GetStatus(Qspi *pQspi, const QspiStatus_t rStatus); + +void QSPI_ConfigureClock(Qspi *pQspi, QspiClockMode_t ClockMode, + uint32_t dwClockCfg); + +QspidStatus_t QSPI_SingleReadSPI(Qspid_t *pQspid, uint16_t *const pData); + +QspidStatus_t QSPI_MultiReadSPI(Qspid_t *pQspid, uint16_t * + const pData, uint32_t NumOfBytes); + +QspidStatus_t QSPI_SingleWriteSPI(Qspid_t *pQspid, uint16_t const *pData); + +QspidStatus_t QSPI_MultiWriteSPI(Qspid_t *pQspid, uint16_t const *pData , + uint32_t NumOfBytes); + +QspidStatus_t QSPI_EnableIt(Qspi *pQspi, uint32_t dwSources); + +QspidStatus_t QSPI_DisableIt(Qspi *pQspi, uint32_t dwSources); + +uint32_t QSPI_GetItMask(Qspi *pQspi); + +uint32_t QSPI_GetEnabledItStatus(Qspi *pQspi); + +QspidStatus_t QSPI_ConfigureInterface(Qspid_t *pQspid, QspiMode_t Mode, + uint32_t dwConfiguration); + +QspidStatus_t QSPI_SendCommand(Qspid_t *pQspi, uint8_t const KeepCfg); + +QspidStatus_t QSPI_SendCommandWithData(Qspid_t *pQspi, uint8_t const KeepCfg); + +QspidStatus_t QSPI_ReadCommand(Qspid_t *pQspi, uint8_t const KeepCfg); + +QspidStatus_t QSPI_EnableMemAccess(Qspid_t *pQspi, uint8_t const KeepCfg, + uint8_t ScrambleFlag); + +QspidStatus_t QSPI_ReadWriteMem(Qspid_t *pQspid, Access_t const ReadWrite); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _QSPI_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/qspi_dma.h b/bsps/arm/atsam/include/libchip/include/qspi_dma.h new file mode 100644 index 0000000000..8ee274e15d --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/qspi_dma.h @@ -0,0 +1,115 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Implementation of SPI driver, transfer data through DMA. + * + */ + +#ifndef QSPI_DMA_H +#define QSPI_DMA_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#ifndef __rtems__ +#include "../../../../utils/utility.h" +#endif /* __rtems__ */ + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define QSPID_ERROR 1 + +/** SPI driver is currently in use.*/ +#define QSPID_ERROR_LOCK 2 + +#define QSPID_CH_NOT_ENABLED 0xFF +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** SPI transfer complete callback. */ +typedef void (*QspidCallback)(uint8_t, void *); + +/** Constant structure associated with SPI port. This structure prevents + client applications to have access in the same time. */ +typedef struct _Qspid { + Qspid_t Qspid; + /** Pointer to DMA driver */ + sXdmad *pXdmad; + /** Polling */ + uint8_t Polling; + /** Tx ch num */ + uint8_t TxChNum; + /** Rx ch num */ + uint8_t RxChNum; + /** QSPI Xfr state. */ + volatile uint8_t progress; +} QspiDma_t; + +#ifdef __cplusplus +extern "C" { +#endif +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t QSPID_Configure(QspiDma_t *pQspidma, QspiMode_t Mode, + uint32_t dwConfiguration, sXdmad *pXdmad); + +uint32_t QSPID_EnableQspiRxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_EnableQspiTxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_DisableQspiRxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_DisableQspiTxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_DisableSpiChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_EnableSpiChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_ReadWriteQSPI(QspiDma_t *pQspidma, Access_t const ReadWrite); + +uint32_t QSPID_ReadWriteSPI(QspiDma_t *pQspidma, Access_t const ReadWrite); + +uint32_t QSPID_IsBusy(volatile uint8_t *QspiSemaphore); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_DMA_ */ diff --git a/bsps/arm/atsam/include/libchip/include/rstc.h b/bsps/arm/atsam/include/libchip/include/rstc.h new file mode 100644 index 0000000000..7c33a465b0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/rstc.h @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _RSTC_H +#define _RSTC_H + +/*--------------------------------------------------------------------------- + * Includes + *---------------------------------------------------------------------------*/ + +#include + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +void RSTC_ConfigureMode(uint32_t rmr); + +void RSTC_SetUserResetEnable(uint8_t enable); + +void RSTC_SetUserResetInterruptEnable(uint8_t enable); + +void RSTC_SetExtResetLength(uint8_t powl); + +void RSTC_ProcessorReset(void); + +void RSTC_ExtReset(void); + +uint8_t RSTC_GetNrstLevel(void); + +uint8_t RSTC_IsUserResetDetected(void); + +uint8_t RSTC_IsBusy(void); + +uint32_t RSTC_GetStatus(void); + +#endif /* #ifndef _RSTC_H */ + diff --git a/bsps/arm/atsam/include/libchip/include/rtc.h b/bsps/arm/atsam/include/libchip/include/rtc.h new file mode 100644 index 0000000000..9fd724824a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/rtc.h @@ -0,0 +1,102 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Interface for Real Time Clock (RTC) controller. + * + */ + +#ifndef _RTC_ +#define _RTC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +#define RTC_HOUR_BIT_LEN_MASK 0x3F +#define RTC_MIN_BIT_LEN_MASK 0x7F +#define RTC_SEC_BIT_LEN_MASK 0x7F +#define RTC_CENT_BIT_LEN_MASK 0x7F +#define RTC_YEAR_BIT_LEN_MASK 0xFF +#define RTC_MONTH_BIT_LEN_MASK 0x1F +#define RTC_DATE_BIT_LEN_MASK 0x3F +#define RTC_WEEK_BIT_LEN_MASK 0x07 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void RTC_SetHourMode(Rtc *pRtc, uint32_t dwMode); + +extern uint32_t RTC_GetHourMode(Rtc *pRtc); + +extern void RTC_EnableIt(Rtc *pRtc, uint32_t dwSources); + +extern void RTC_DisableIt(Rtc *pRtc, uint32_t dwSources); + +extern int RTC_SetTime(Rtc *pRtc, uint8_t ucHour, uint8_t ucMinute, + uint8_t ucSecond); + +extern void RTC_GetTime(Rtc *pRtc, uint8_t *pucHour, uint8_t *pucMinute, + uint8_t *pucSecond); + +extern int RTC_SetTimeAlarm(Rtc *pRtc, uint8_t *pucHour, uint8_t *pucMinute, + uint8_t *pucSecond); + +extern void RTC_GetDate(Rtc *pRtc, uint16_t *pwYear, uint8_t *pucMonth, + uint8_t *pucDay, uint8_t *pucWeek); + +extern int RTC_SetDate(Rtc *pRtc, uint16_t wYear, uint8_t ucMonth, + uint8_t ucDay, uint8_t ucWeek); + +extern int RTC_SetDateAlarm(Rtc *pRtc, uint8_t *pucMonth, uint8_t *pucDay); + +extern void RTC_ClearSCCR(Rtc *pRtc, uint32_t dwMask); + +extern uint32_t RTC_GetSR(Rtc *pRtc, uint32_t dwMask); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _RTC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/rtt.h b/bsps/arm/atsam/include/libchip/include/rtt.h new file mode 100644 index 0000000000..2dd2ca5eb5 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/rtt.h @@ -0,0 +1,82 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \par Purpose + * + * Interface for Real Time Timer (RTT) controller. + * + * \par Usage + * + * -# Changes the prescaler value of the given RTT and restarts it + * using \ref RTT_SetPrescaler(). + * -# Get current value of the RTT using \ref RTT_GetTime(). + * -# Enables the specified RTT interrupt using \ref RTT_EnableIT(). + * -# Get the status register value of the given RTT using \ref RTT_GetStatus(). + * -# Configures the RTT to generate an alarm at the given time + * using \ref RTT_SetAlarm(). + */ + +#ifndef _RTT_ +#define _RTT_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void RTT_SetPrescaler(Rtt *pRtt, uint16_t wPrescaler); + +extern uint32_t RTT_GetTime(Rtt *pRtt); + +extern void RTT_EnableIT(Rtt *pRtt, uint32_t dwSources); + +extern uint32_t RTT_GetStatus(Rtt *pRtt); + +extern void RTT_SetAlarm(Rtt *pRtt, uint32_t dwTime); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef RTT_H */ + diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_acc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_acc.h new file mode 100644 index 0000000000..9810e118f8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_acc.h @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_ACC_COMPONENT_ +#define _SAME70_ACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_ACC Analog Comparator Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Acc hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[7]; + __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */ +} Acc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos 0 +#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */ +#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))) +#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_VREFP (0x1u << 0) /**< \brief (ACC_MR) Select VREFP */ +#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_Pos 4 +#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */ +#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))) +#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */ +#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_EDGETYP_Pos 9 +#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */ +#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))) +#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */ +#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */ +#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */ +#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */ +#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */ +#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */ +#define ACC_ACR_HYST_Pos 1 +#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */ +#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */ +#define ACC_WPMR_WPKEY_Pos 8 +#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */ +#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) +#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */ +#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */ + +/*@}*/ + + +#endif /* _SAME70_ACC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_aes.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_aes.h new file mode 100644 index 0000000000..cd14abc0a1 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_aes.h @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_AES_COMPONENT_ +#define _SAME70_AES_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ============================================================================= */ +/** \addtogroup SAME70_AES Advanced Encryption Standard */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aes hardware registers */ +typedef struct { + __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */ + __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[2]; + __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */ + __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */ + __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */ + __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */ + __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */ + __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */ + __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */ +#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */ +#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */ +#define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */ +#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */ +#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */ +#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */ +#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */ +#define AES_MR_PROCDLY_Pos 4 +#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */ +#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))) +#define AES_MR_SMOD_Pos 8 +#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */ +#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))) +#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_KEYSIZE_Pos 10 +#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */ +#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))) +#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_OPMOD_Pos 12 +#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */ +#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))) +#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */ +#define AES_MR_CFBS_Pos 16 +#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */ +#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))) +#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */ +#define AES_MR_CKEY_Pos 20 +#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Countermeasure Key */ +#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))) +#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ +#define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) Countermeasure Type 1 */ +#define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AES_MR) Countermeasure type 1 is disabled. */ +#define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Countermeasure type 1 is enabled. */ +#define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) Countermeasure Type 2 */ +#define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Countermeasure type 2 is disabled. */ +#define AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Countermeasure type 2 is enabled. */ +#define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) Countermeasure Type 3 */ +#define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Countermeasure type 3 is disabled. */ +#define AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Countermeasure type 3 is enabled. */ +#define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) Countermeasure Type 4 */ +#define AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Countermeasure type 4 is disabled. */ +#define AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Countermeasure type 4 is enabled. */ +#define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) Countermeasure Type 5 */ +#define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Countermeasure type 5 is disabled. */ +#define AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Countermeasure type 5 is enabled. */ +#define AES_MR_CMTYP6 (0x1u << 29) /**< \brief (AES_MR) Countermeasure Type 6 */ +#define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AES_MR) Countermeasure type 6 is disabled. */ +#define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AES_MR) Countermeasure type 6 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */ +#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */ +#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */ +#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */ +#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */ +#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */ +#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */ +/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ +#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_Pos 12 +#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */ +#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */ +/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */ +#define AES_KEYWR_KEYW_Pos 0 +#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */ +#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))) +/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */ +#define AES_IDATAR_IDATA_Pos 0 +#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */ +#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))) +/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */ +#define AES_ODATAR_ODATA_Pos 0 +#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */ +/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */ +#define AES_IVR_IV_Pos 0 +#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */ +#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))) +/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos 0 +#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */ +#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))) +/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos 0 +#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */ +#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))) +/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */ +#define AES_GHASHR_GHASH_Pos 0 +#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */ +#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))) +/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */ +#define AES_TAGR_TAG_Pos 0 +#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */ +/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos 0 +#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */ +/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */ +#define AES_GCMHR_H_Pos 0 +#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */ +#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))) + +/*@}*/ + + +#endif /* _SAME70_AES_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_afec.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_afec.h new file mode 100644 index 0000000000..8b009b4ba1 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_afec.h @@ -0,0 +1,483 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_AFEC_COMPONENT_ +#define _SAME70_AFEC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Front-End Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_AFEC Analog Front-End Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Afec hardware registers */ +typedef struct { + __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */ + __I uint32_t Reserved1[6]; + __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */ + __I uint32_t Reserved3[7]; + __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */ + __I uint32_t Reserved5[11]; + __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */ +} Afec; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */ +#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */ +#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */ +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */ +#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGSEL_Pos 1 +#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos))) +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) Analog Comparator */ +#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */ +#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */ +#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */ +#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_PRESCAL_Pos 8 +#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */ +#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))) +#define AFEC_MR_STARTUP_Pos 16 +#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */ +#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos))) +#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_ONE (0x1u << 23) /**< \brief (AFEC_MR) One */ +#define AFEC_MR_TRACKTIM_Pos 24 +#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */ +#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))) +#define AFEC_MR_TRANSFER_Pos 28 +#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */ +#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))) +#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Enable */ +#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */ +#define AFEC_EMR_CMPMODE_Pos 0 +#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */ +#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos))) +#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPSEL_Pos 3 +#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */ +#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))) +#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPFILTER_Pos 12 +#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */ +#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))) +#define AFEC_EMR_RES_Pos 16 +#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */ +#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos))) +#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */ +#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_SIGNMODE_Pos 28 +#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */ +#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos))) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All channels: Signed conversions. */ +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */ +#define AFEC_SEQ1R_USCH0_Pos 0 +#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */ +#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))) +#define AFEC_SEQ1R_USCH1_Pos 4 +#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */ +#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))) +#define AFEC_SEQ1R_USCH2_Pos 8 +#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */ +#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))) +#define AFEC_SEQ1R_USCH3_Pos 12 +#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */ +#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))) +#define AFEC_SEQ1R_USCH4_Pos 16 +#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */ +#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))) +#define AFEC_SEQ1R_USCH5_Pos 20 +#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */ +#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))) +#define AFEC_SEQ1R_USCH6_Pos 24 +#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */ +#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))) +#define AFEC_SEQ1R_USCH7_Pos 28 +#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */ +#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))) +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */ +#define AFEC_SEQ2R_USCH8_Pos 0 +#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */ +#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))) +#define AFEC_SEQ2R_USCH9_Pos 4 +#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */ +#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))) +#define AFEC_SEQ2R_USCH10_Pos 8 +#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */ +#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))) +#define AFEC_SEQ2R_USCH11_Pos 12 +#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */ +#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))) +#define AFEC_SEQ2R_USCH12_Pos 16 +#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */ +#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos))) +#define AFEC_SEQ2R_USCH13_Pos 20 +#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */ +#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos))) +#define AFEC_SEQ2R_USCH14_Pos 24 +#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */ +#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos))) +#define AFEC_SEQ2R_USCH15_Pos 28 +#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */ +#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos))) +/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */ +#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */ +#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */ +#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */ +#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */ +#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */ +#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */ +#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */ +#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */ +#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */ +#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */ +#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */ +#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */ +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */ +#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */ +#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */ +#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */ +#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */ +#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */ +#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */ +#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */ +#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */ +#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */ +#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */ +#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */ +#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */ +/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */ +#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */ +#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */ +#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */ +#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */ +#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */ +#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */ +#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */ +#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */ +#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */ +#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */ +#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */ +#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */ +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */ +#define AFEC_LCDR_LDATA_Pos 0 +#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */ +#define AFEC_LCDR_CHNB_Pos 24 +#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */ +/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */ +#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */ +#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */ +#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */ +#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */ +#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */ +#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */ +#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */ +#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */ +#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */ +#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */ +#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */ +#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */ +#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */ +#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */ +#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */ +#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */ +/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */ +#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */ +#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */ +#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */ +#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */ +#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */ +#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */ +#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */ +#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */ +#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */ +#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */ +#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */ +#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */ +#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */ +#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */ +#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */ +#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */ +/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */ +#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */ +#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */ +#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */ +#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */ +#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */ +#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */ +#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */ +#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */ +#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */ +#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */ +#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */ +#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */ +#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */ +#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */ +#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */ +#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */ +/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */ +#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) */ +#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change (cleared on read) */ +/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */ +#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */ +#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */ +#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */ +#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */ +#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */ +#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */ +#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */ +#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */ +#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */ +#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */ +#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */ +#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */ +/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */ +#define AFEC_CWR_LOWTHRES_Pos 0 +#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */ +#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))) +#define AFEC_CWR_HIGHTHRES_Pos 16 +#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */ +#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))) +/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */ +#define AFEC_CGR_GAIN0_Pos 0 +#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for Channel 0 */ +#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))) +#define AFEC_CGR_GAIN1_Pos 2 +#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for Channel 1 */ +#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))) +#define AFEC_CGR_GAIN2_Pos 4 +#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for Channel 2 */ +#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))) +#define AFEC_CGR_GAIN3_Pos 6 +#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for Channel 3 */ +#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))) +#define AFEC_CGR_GAIN4_Pos 8 +#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for Channel 4 */ +#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))) +#define AFEC_CGR_GAIN5_Pos 10 +#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for Channel 5 */ +#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))) +#define AFEC_CGR_GAIN6_Pos 12 +#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for Channel 6 */ +#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))) +#define AFEC_CGR_GAIN7_Pos 14 +#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for Channel 7 */ +#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))) +#define AFEC_CGR_GAIN8_Pos 16 +#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for Channel 8 */ +#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))) +#define AFEC_CGR_GAIN9_Pos 18 +#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for Channel 9 */ +#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))) +#define AFEC_CGR_GAIN10_Pos 20 +#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for Channel 10 */ +#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))) +#define AFEC_CGR_GAIN11_Pos 22 +#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for Channel 11 */ +#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))) +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */ +#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */ +#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */ +#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */ +#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */ +#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */ +#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */ +#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */ +#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */ +#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */ +#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */ +#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */ +#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */ +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */ +#define AFEC_CSELR_CSEL_Pos 0 +#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */ +#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))) +/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */ +#define AFEC_CDR_DATA_Pos 0 +#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */ +/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */ +#define AFEC_COCR_AOFF_Pos 0 +#define AFEC_COCR_AOFF_Msk (0x3ffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */ +#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))) +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */ +#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos))) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */ +#define AFEC_TEMPCWR_TLOWTHRES_Pos 0 +#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */ +#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))) +#define AFEC_TEMPCWR_THIGHTHRES_Pos 16 +#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */ +#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))) +/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */ +#define AFEC_ACR_PGA0EN (0x1u << 2) /**< \brief (AFEC_ACR) PGA0 Enable */ +#define AFEC_ACR_PGA1EN (0x1u << 3) /**< \brief (AFEC_ACR) PGA1 Enable */ +#define AFEC_ACR_IBCTL_Pos 8 +#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFE Bias Current Control */ +#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))) +/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */ +#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */ +#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */ +#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */ +#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */ +#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */ +#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */ +#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */ +#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */ +#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */ +#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */ +#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */ +#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */ +/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */ +#define AFEC_COSR_CSEL (0x1u << 0) /**< \brief (AFEC_COSR) Sample & Hold unit Correction Select */ +/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */ +#define AFEC_CVR_OFFSETCORR_Pos 0 +#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */ +#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos))) +#define AFEC_CVR_GAINCORR_Pos 16 +#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */ +#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos))) +/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */ +#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */ +#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */ +#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */ +#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */ +#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */ +#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */ +#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */ +#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */ +#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */ +#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */ +#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */ +#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */ +/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */ +#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */ +#define AFEC_WPMR_WPKEY_Pos 8 +#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */ +#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos))) +#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */ +#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */ +#define AFEC_WPSR_WPVSRC_Pos 8 +#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_AFEC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_chipid.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_chipid.h new file mode 100644 index 0000000000..0bf098d895 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_chipid.h @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_CHIPID_COMPONENT_ +#define _SAME70_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAME70_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) /**< \brief (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) /**< \brief (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) /**< \brief (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) /**< \brief (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAME70_CHIPID_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_dacc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_dacc.h new file mode 100644 index 0000000000..a57a1e1b32 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_dacc.h @@ -0,0 +1,184 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_DACC_COMPONENT_ +#define _SAME70_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */ + __I uint32_t Reserved1[1]; + __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */ + __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status Register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */ +#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */ +#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */ +#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC. */ +#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). */ +#define DACC_MR_ZERO (0x1u << 5) /**< \brief (DACC_MR) Must always be written to 0. */ +#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */ +#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 are single-ended outputs. */ +#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */ +#define DACC_MR_PRESCALER_Pos 24 +#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */ +#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))) +/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */ +#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */ +#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */ +#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGSEL0_Pos 4 +#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */ +#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))) +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_TRGSEL1_Pos 8 +#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */ +#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))) +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_OSR0_Pos 16 +#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */ +#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))) +#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_Pos 20 +#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */ +#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))) +#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC Ready Flag */ +#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC Ready Flag */ +/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */ +#define DACC_CDR_DATA0_Pos 0 +#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */ +#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))) +#define DACC_CDR_DATA1_Pos 16 +#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */ +#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */ +#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */ +#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */ +#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */ +#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */ +#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */ +#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */ +#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */ +#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */ +#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */ +#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */ +#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */ +#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status Register -------- */ +#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */ +#define DACC_WPSR_WPVSRC_Pos 8 +#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_DACC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_efc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_efc.h new file mode 100644 index 0000000000..809db26a7a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_efc.h @@ -0,0 +1,111 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_EFC_COMPONENT_ +#define _SAME70_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ + __I uint32_t Reserved1[53]; + __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) +#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status (cleared on read) */ +#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) */ +#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ +/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */ +#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */ +#define EEFC_WPMR_WPKEY_Pos 8 +#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */ +#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos))) +#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_EFC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_gmac.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_gmac.h new file mode 100644 index 0000000000..6baf8fbd60 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_gmac.h @@ -0,0 +1,1240 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_GMAC_COMPONENT_ +#define _SAME70_GMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */ +/* ============================================================================= */ +/** \addtogroup SAME70_GMAC Gigabit Ethernet MAC */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GmacSa hardware registers */ +typedef struct { + __IO uint32_t GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top Register */ +} GmacSa; + +/** \brief GmacSt2Compare hardware registers */ +typedef struct { + __IO uint32_t GMAC_ST2COM0; /**< \brief 31:16 - Compare Value. 15:0 - Mask Value. */ + __IO uint32_t GMAC_ST2COM1; /**< \brief 31:9 - Reserved; 8:7 - Offset location in frame; 6:0 Offset value in bytes */ +} GmacSt2Compare; + +/** \brief Gmac hardware registers */ +#define GMACSA_NUMBER 4 +#define GMACST2COMPARE_NUMBER 24 +typedef struct { + __IO uint32_t GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */ + __IO uint32_t GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */ + __I uint32_t GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */ + __IO uint32_t GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */ + __IO uint32_t GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */ + __IO uint32_t GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */ + __IO uint32_t GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address Register */ + __IO uint32_t GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register */ + __IO uint32_t GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */ + __I uint32_t GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */ + __O uint32_t GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */ + __O uint32_t GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */ + __IO uint32_t GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */ + __IO uint32_t GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */ + __I uint32_t GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */ + __IO uint32_t GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */ + __IO uint32_t GMAC_TPSF; /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */ + __IO uint32_t GMAC_RPSF; /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */ + __IO uint32_t GMAC_RJFML; /**< \brief (Gmac Offset: 0x048) RX Jumbo Frame Max Length Register */ + __I uint32_t Reserved1[13]; + __IO uint32_t GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom */ + __IO uint32_t GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top */ + GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */ + __IO uint32_t GMAC_TIDM1; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */ + __IO uint32_t GMAC_TIDM2; /**< \brief (Gmac Offset: 0x0AC) Type ID Match 2 Register */ + __IO uint32_t GMAC_TIDM3; /**< \brief (Gmac Offset: 0x0B0) Type ID Match 3 Register */ + __IO uint32_t GMAC_TIDM4; /**< \brief (Gmac Offset: 0x0B4) Type ID Match 4 Register */ + __IO uint32_t GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */ + __IO uint32_t GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */ + __IO uint32_t GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */ + __IO uint32_t GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */ + __IO uint32_t GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register */ + __IO uint32_t GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t GMAC_NSC; /**< \brief (Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register */ + __IO uint32_t GMAC_SCL; /**< \brief (Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register */ + __IO uint32_t GMAC_SCH; /**< \brief (Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register */ + __I uint32_t GMAC_EFTSH; /**< \brief (Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_EFRSH; /**< \brief (Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register */ + __I uint32_t GMAC_PEFTSH; /**< \brief (Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_PEFRSH; /**< \brief (Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register */ + __I uint32_t Reserved3[2]; + __I uint32_t GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted Low Register */ + __I uint32_t GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted High Register */ + __I uint32_t GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */ + __I uint32_t GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */ + __I uint32_t GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */ + __I uint32_t GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */ + __I uint32_t GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Underruns Register */ + __I uint32_t GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */ + __I uint32_t GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */ + __I uint32_t GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */ + __I uint32_t GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */ + __I uint32_t GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */ + __I uint32_t GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */ + __I uint32_t GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received Low Received Register */ + __I uint32_t GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received High Received Register */ + __I uint32_t GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */ + __I uint32_t GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */ + __I uint32_t GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */ + __I uint32_t GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */ + __I uint32_t GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ + __I uint32_t GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ + __I uint32_t GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */ + __I uint32_t GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */ + __I uint32_t GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */ + __I uint32_t GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */ + __I uint32_t GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */ + __I uint32_t GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */ + __I uint32_t GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */ + __I uint32_t GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */ + __I uint32_t GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */ + __I uint32_t GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */ + __I uint32_t GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */ + __I uint32_t GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t GMAC_TISUBN; /**< \brief (Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */ + __IO uint32_t GMAC_TSH; /**< \brief (Gmac Offset: 0x1C0) 1588 Timer Seconds High Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t GMAC_TSL; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register */ + __IO uint32_t GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */ + __O uint32_t GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */ + __IO uint32_t GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */ + __I uint32_t GMAC_EFTSL; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_EFRSL; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */ + __I uint32_t GMAC_PEFTSL; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_PEFRSL; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */ + __I uint32_t Reserved6[128]; + __I uint32_t GMAC_ISRPQ[2]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) */ + __I uint32_t Reserved7[14]; + __IO uint32_t GMAC_TBQBAPQ[2]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved8[14]; + __IO uint32_t GMAC_RBQBAPQ[2]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved9[6]; + __IO uint32_t GMAC_RBSRPQ[2]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) */ + __I uint32_t Reserved10[5]; + __IO uint32_t GMAC_CBSCR; /**< \brief (Gmac Offset: 0x4BC) Credit-Based Shaping Control Register */ + __IO uint32_t GMAC_CBSISQA; /**< \brief (Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */ + __IO uint32_t GMAC_CBSISQB; /**< \brief (Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */ + __I uint32_t Reserved11[14]; + __IO uint32_t GMAC_ST1RPQ[4]; /**< \brief (Gmac Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) */ + __I uint32_t Reserved12[12]; + __IO uint32_t GMAC_ST2RPQ[8]; /**< \brief (Gmac Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) */ + __I uint32_t Reserved13[12]; + __I uint32_t Reserved14[28]; + __O uint32_t GMAC_IERPQ[2]; /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) */ + __I uint32_t Reserved15[6]; + __O uint32_t GMAC_IDRPQ[2]; /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) */ + __I uint32_t Reserved16[6]; + __IO uint32_t GMAC_IMRPQ[2]; /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) */ + __I uint32_t Reserved17[38]; + __IO uint32_t GMAC_ST2ER[4]; /**< \brief (Gmac Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) */ + __I uint32_t Reserved18[4]; + __IO GmacSt2Compare GMAC_ST2COMP[GMACST2COMPARE_NUMBER];/**< \brief (Gmac Offset: 0x700) Screener Type 2 Compare Registers */ +} Gmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */ +#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */ +#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */ +#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */ +#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */ +#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */ +#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */ +#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */ +#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */ +#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */ +#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */ +#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */ +#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */ +#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */ +#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */ +#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */ +#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */ +/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */ +#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */ +#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */ +#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */ +#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */ +#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */ +#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */ +#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */ +#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */ +#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */ +#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */ +#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */ +#define GMAC_NCFGR_RXBUFO_Pos 14 +#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */ +#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) +#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */ +#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */ +#define GMAC_NCFGR_CLK_Pos 18 +#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */ +#define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))) +#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ +#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_DBW_Pos 21 +#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */ +#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))) +#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */ +#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */ +#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */ +#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */ +#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */ +#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */ +#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */ +/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */ +#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */ +#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */ +/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */ +#define GMAC_UR_RMII (0x1u << 0) /**< \brief (GMAC_UR) Reduced MII Mode */ +/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */ +#define GMAC_DCFGR_FBLDO_Pos 0 +#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */ +#define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))) +#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */ +#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */ +#define GMAC_DCFGR_RXBMS_Pos 8 +#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))) +#define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 4/8 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 4/4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4/2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */ +#define GMAC_DCFGR_DRBS_Pos 16 +#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */ +#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) +#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */ +/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */ +#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */ +#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */ +#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */ +#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */ +#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */ +#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */ +/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address Register -------- */ +#define GMAC_RBQB_ADDR_Pos 2 +#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */ +#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) +/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address Register -------- */ +#define GMAC_TBQB_ADDR_Pos 2 +#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */ +#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) +/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */ +#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */ +#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */ +#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */ +#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */ +/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */ +#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */ +#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */ +#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */ +#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */ +#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Underrun */ +#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */ +#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */ +#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */ +#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */ +#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */ +#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */ +#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */ +#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */ +#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */ +#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */ +#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */ +#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */ +#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */ +#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */ +#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */ +#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */ +#define GMAC_ISR_TSU (0x1u << 29) /**< \brief (GMAC_ISR) TSU timer comparison interrupt */ +/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */ +#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */ +#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */ +#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */ +#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */ +#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Underrun */ +#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */ +#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */ +#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */ +#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */ +#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */ +#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */ +#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */ +#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */ +#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */ +#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */ +#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */ +#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */ +#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */ +#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */ +#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */ +#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */ +#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */ +#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */ +#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */ +#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */ +#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */ +#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Underrun */ +#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */ +#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */ +#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */ +#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */ +#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */ +#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */ +#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */ +#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */ +#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */ +#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */ +#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */ +#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */ +#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */ +#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */ +#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ +#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */ +/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */ +#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */ +#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */ +#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */ +#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */ +#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Underrun */ +#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */ +#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */ +#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */ +#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */ +#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */ +#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */ +#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */ +#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */ +#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */ +#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */ +#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */ +#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */ +#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */ +#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */ +#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */ +/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */ +#define GMAC_MAN_DATA_Pos 0 +#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */ +#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) +#define GMAC_MAN_WTN_Pos 16 +#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */ +#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) +#define GMAC_MAN_REGA_Pos 18 +#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */ +#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) +#define GMAC_MAN_PHYA_Pos 23 +#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */ +#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) +#define GMAC_MAN_OP_Pos 28 +#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */ +#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) +#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */ +#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */ +/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */ +#define GMAC_RPQ_RPQ_Pos 0 +#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */ +/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */ +#define GMAC_TPQ_TPQ_Pos 0 +#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */ +#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) +/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */ +#define GMAC_TPSF_TPB1ADR_Pos 0 +#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) Transmit Partial Store and Forward Address */ +#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))) +#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */ +/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */ +#define GMAC_RPSF_RPB1ADR_Pos 0 +#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) Receive Partial Store and Forward Address */ +#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))) +#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */ +/* -------- GMAC_RJFML : (GMAC Offset: 0x048) RX Jumbo Frame Max Length Register -------- */ +#define GMAC_RJFML_FML_Pos 0 +#define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos) /**< \brief (GMAC_RJFML) Frame Max Length */ +#define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))) +/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom -------- */ +#define GMAC_HRB_ADDR_Pos 0 +#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */ +#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) +/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top -------- */ +#define GMAC_HRT_ADDR_Pos 0 +#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */ +#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) +/* -------- GMAC_SAB : (GMAC Offset: N/A) Specific Address 1 Bottom Register -------- */ +#define GMAC_SAB_ADDR_Pos 0 +#define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos) /**< \brief (GMAC_SAB) Specific Address 1 */ +#define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))) +/* -------- GMAC_SAT : (GMAC Offset: N/A) Specific Address 1 Top Register -------- */ +#define GMAC_SAT_ADDR_Pos 0 +#define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos) /**< \brief (GMAC_SAT) Specific Address 1 */ +#define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))) +/* -------- GMAC_TIDM1 : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */ +#define GMAC_TIDM1_TID_Pos 0 +#define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos) /**< \brief (GMAC_TIDM1) Type ID Match 1 */ +#define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos))) +#define GMAC_TIDM1_ENID1 (0x1u << 31) /**< \brief (GMAC_TIDM1) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM2 : (GMAC Offset: 0x0AC) Type ID Match 2 Register -------- */ +#define GMAC_TIDM2_TID_Pos 0 +#define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos) /**< \brief (GMAC_TIDM2) Type ID Match 2 */ +#define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos))) +#define GMAC_TIDM2_ENID2 (0x1u << 31) /**< \brief (GMAC_TIDM2) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM3 : (GMAC Offset: 0x0B0) Type ID Match 3 Register -------- */ +#define GMAC_TIDM3_TID_Pos 0 +#define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos) /**< \brief (GMAC_TIDM3) Type ID Match 3 */ +#define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos))) +#define GMAC_TIDM3_ENID3 (0x1u << 31) /**< \brief (GMAC_TIDM3) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM4 : (GMAC Offset: 0x0B4) Type ID Match 4 Register -------- */ +#define GMAC_TIDM4_TID_Pos 0 +#define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos) /**< \brief (GMAC_TIDM4) Type ID Match 4 */ +#define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos))) +#define GMAC_TIDM4_ENID4 (0x1u << 31) /**< \brief (GMAC_TIDM4) Enable Copying of TID Matched Frames */ +/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */ +#define GMAC_WOL_IP_Pos 0 +#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))) +#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */ +#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */ +#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */ +/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */ +#define GMAC_IPGS_FL_Pos 0 +#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */ +#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) +/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */ +#define GMAC_SVLAN_VLAN_TYPE_Pos 0 +#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */ +#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) +#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */ +/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */ +#define GMAC_TPFCP_PEV_Pos 0 +#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */ +#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) +#define GMAC_TPFCP_PQ_Pos 8 +#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */ +#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) +/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom Register -------- */ +#define GMAC_SAMB1_ADDR_Pos 0 +#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */ +#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) +/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top Register -------- */ +#define GMAC_SAMT1_ADDR_Pos 0 +#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */ +#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) +/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register -------- */ +#define GMAC_NSC_NANOSEC_Pos 0 +#define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos) /**< \brief (GMAC_NSC) 1588 Timer Nanosecond Comparison Value */ +#define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))) +/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) 1588 Timer Second Comparison Low Register -------- */ +#define GMAC_SCL_SEC_Pos 0 +#define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos) /**< \brief (GMAC_SCL) 1588 Timer Second Comparison Value */ +#define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))) +/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) 1588 Timer Second Comparison High Register -------- */ +#define GMAC_SCH_SEC_Pos 0 +#define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos) /**< \brief (GMAC_SCH) 1588 Timer Second Comparison Value */ +#define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))) +/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_EFTSH_RUD_Pos 0 +#define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos) /**< \brief (GMAC_EFTSH) Register Update */ +/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) PTP Event Frame Received Seconds High Register -------- */ +#define GMAC_EFRSH_RUD_Pos 0 +#define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos) /**< \brief (GMAC_EFRSH) Register Update */ +/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_PEFTSH_RUD_Pos 0 +#define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos) /**< \brief (GMAC_PEFTSH) Register Update */ +/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register -------- */ +#define GMAC_PEFRSH_RUD_Pos 0 +#define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos) /**< \brief (GMAC_PEFRSH) Register Update */ +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted Low Register -------- */ +#define GMAC_OTLO_TXO_Pos 0 +#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */ +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted High Register -------- */ +#define GMAC_OTHI_TXO_Pos 0 +#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */ +/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */ +#define GMAC_FT_FTX_Pos 0 +#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */ +/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */ +#define GMAC_BCFT_BFTX_Pos 0 +#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */ +/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */ +#define GMAC_MFT_MFTX_Pos 0 +#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */ +/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */ +#define GMAC_PFT_PFTX_Pos 0 +#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */ +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */ +#define GMAC_BFT64_NFTX_Pos 0 +#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT127_NFTX_Pos 0 +#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT255_NFTX_Pos 0 +#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT511_NFTX_Pos 0 +#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1023_NFTX_Pos 0 +#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1518_NFTX_Pos 0 +#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_GTBFT1518_NFTX_Pos 0 +#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Underruns Register -------- */ +#define GMAC_TUR_TXUNR_Pos 0 +#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Underruns */ +/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */ +#define GMAC_SCF_SCOL_Pos 0 +#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */ +/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */ +#define GMAC_MCF_MCOL_Pos 0 +#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */ +/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */ +#define GMAC_EC_XCOL_Pos 0 +#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */ +/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */ +#define GMAC_LC_LCOL_Pos 0 +#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */ +/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */ +#define GMAC_DTF_DEFT_Pos 0 +#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */ +/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */ +#define GMAC_CSE_CSR_Pos 0 +#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */ +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received Low Received Register -------- */ +#define GMAC_ORLO_RXO_Pos 0 +#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */ +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received High Received Register -------- */ +#define GMAC_ORHI_RXO_Pos 0 +#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */ +/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */ +#define GMAC_FR_FRX_Pos 0 +#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */ +/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */ +#define GMAC_BCFR_BFRX_Pos 0 +#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */ +/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */ +#define GMAC_MFR_MFRX_Pos 0 +#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */ +/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */ +#define GMAC_PFR_PFRX_Pos 0 +#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */ +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */ +#define GMAC_BFR64_NFRX_Pos 0 +#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */ +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */ +#define GMAC_TBFR127_NFRX_Pos 0 +#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */ +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */ +#define GMAC_TBFR255_NFRX_Pos 0 +#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */ +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register -------- */ +#define GMAC_TBFR511_NFRX_Pos 0 +#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */ +#define GMAC_TBFR1023_NFRX_Pos 0 +#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */ +#define GMAC_TBFR1518_NFRX_Pos 0 +#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */ +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */ +#define GMAC_TMXBFR_NFRX_Pos 0 +#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */ +/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */ +#define GMAC_UFR_UFRX_Pos 0 +#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */ +/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */ +#define GMAC_OFR_OFRX_Pos 0 +#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */ +/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */ +#define GMAC_JR_JRX_Pos 0 +#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */ +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */ +#define GMAC_FCSE_FCKR_Pos 0 +#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */ +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */ +#define GMAC_LFFE_LFER_Pos 0 +#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */ +/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */ +#define GMAC_RSE_RXSE_Pos 0 +#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */ +/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */ +#define GMAC_AE_AER_Pos 0 +#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */ +/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */ +#define GMAC_RRE_RXRER_Pos 0 +#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */ +/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */ +#define GMAC_ROE_RXOVR_Pos 0 +#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */ +/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */ +#define GMAC_IHCE_HCKER_Pos 0 +#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */ +/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */ +#define GMAC_TCE_TCKER_Pos 0 +#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */ +/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */ +#define GMAC_UCE_UCKER_Pos 0 +#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */ +/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register -------- */ +#define GMAC_TISUBN_LSBTIR_Pos 0 +#define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos) /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register */ +#define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))) +/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register -------- */ +#define GMAC_TSH_TCS_Pos 0 +#define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos) /**< \brief (GMAC_TSH) Timer Count in Seconds */ +#define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))) +/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register -------- */ +#define GMAC_TSL_TCS_Pos 0 +#define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos) /**< \brief (GMAC_TSL) Timer Count in Seconds */ +#define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))) +/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */ +#define GMAC_TN_TNS_Pos 0 +#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */ +#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) +/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */ +#define GMAC_TA_ITDT_Pos 0 +#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */ +#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) +#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */ +/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */ +#define GMAC_TI_CNS_Pos 0 +#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */ +#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) +#define GMAC_TI_ACNS_Pos 8 +#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */ +#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) +#define GMAC_TI_NIT_Pos 16 +#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */ +#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) +/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_EFTSL_RUD_Pos 0 +#define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos) /**< \brief (GMAC_EFTSL) Register Update */ +/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_EFTN_RUD_Pos 0 +#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */ +/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register -------- */ +#define GMAC_EFRSL_RUD_Pos 0 +#define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos) /**< \brief (GMAC_EFRSL) Register Update */ +/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register -------- */ +#define GMAC_EFRN_RUD_Pos 0 +#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */ +/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_PEFTSL_RUD_Pos 0 +#define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos) /**< \brief (GMAC_PEFTSL) Register Update */ +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_PEFTN_RUD_Pos 0 +#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */ +/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register -------- */ +#define GMAC_PEFRSL_RUD_Pos 0 +#define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos) /**< \brief (GMAC_PEFRSL) Register Update */ +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register -------- */ +#define GMAC_PEFRN_RUD_Pos 0 +#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */ +/* -------- GMAC_ISRPQ[2] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) -------- */ +#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[2]) Receive Complete */ +#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[2]) RX Used Bit Read */ +#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[2]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[2]) Transmit Complete */ +#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[2]) Receive Overrun */ +#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[2]) HRESP Not OK */ +/* -------- GMAC_TBQBAPQ[2] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_TBQBAPQ_TXBQBA_Pos 2 +#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[2]) Transmit Buffer Queue Base Address */ +#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos))) +/* -------- GMAC_RBQBAPQ[2] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_RBQBAPQ_RXBQBA_Pos 2 +#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[2]) Receive Buffer Queue Base Address */ +#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos))) +/* -------- GMAC_RBSRPQ[2] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) -------- */ +#define GMAC_RBSRPQ_RBS_Pos 0 +#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[2]) Receive Buffer Size */ +#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos))) +/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register -------- */ +#define GMAC_CBSCR_QBE (0x1u << 0) /**< \brief (GMAC_CBSCR) Queue B CBS Enable */ +#define GMAC_CBSCR_QAE (0x1u << 1) /**< \brief (GMAC_CBSCR) Queue A CBS Enable */ +/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A -------- */ +#define GMAC_CBSISQA_IS_Pos 0 +#define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos) /**< \brief (GMAC_CBSISQA) IdleSlope */ +#define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos))) +/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B -------- */ +#define GMAC_CBSISQB_IS_Pos 0 +#define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos) /**< \brief (GMAC_CBSISQB) IdleSlope */ +#define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos))) +/* -------- GMAC_ST1RPQ[4] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST1RPQ_QNB_Pos 0 +#define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[4]) Queue Number (0-2) */ +#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos))) +#define GMAC_ST1RPQ_DSTCM_Pos 4 +#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match */ +#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos))) +#define GMAC_ST1RPQ_UDPM_Pos 12 +#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match */ +#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos))) +#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match Enable */ +#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match Enable */ +/* -------- GMAC_ST2RPQ[8] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST2RPQ_QNB_Pos 0 +#define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Queue Number (0-2) */ +#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos))) +#define GMAC_ST2RPQ_VLANP_Pos 4 +#define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[8]) VLAN Priority */ +#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos))) +#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[8]) VLAN Enable */ +#define GMAC_ST2RPQ_I2ETH_Pos 9 +#define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 EtherType register x */ +#define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos))) +#define GMAC_ST2RPQ_ETHE (0x1u << 12) /**< \brief (GMAC_ST2RPQ[8]) EtherType Enable */ +#define GMAC_ST2RPQ_COMPA_Pos 13 +#define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos))) +#define GMAC_ST2RPQ_COMPAE (0x1u << 18) /**< \brief (GMAC_ST2RPQ[8]) Compare A Enable */ +#define GMAC_ST2RPQ_COMPB_Pos 19 +#define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos))) +#define GMAC_ST2RPQ_COMPBE (0x1u << 24) /**< \brief (GMAC_ST2RPQ[8]) Compare B Enable */ +#define GMAC_ST2RPQ_COMPC_Pos 25 +#define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos))) +#define GMAC_ST2RPQ_COMPCE (0x1u << 30) /**< \brief (GMAC_ST2RPQ[8]) Compare C Enable */ +/* -------- GMAC_IERPQ[2] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) -------- */ +#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[2]) Receive Complete */ +#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[2]) RX Used Bit Read */ +#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[2]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[2]) Transmit Complete */ +#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[2]) Receive Overrun */ +#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[2]) HRESP Not OK */ +/* -------- GMAC_IDRPQ[2] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) -------- */ +#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[2]) Receive Complete */ +#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[2]) RX Used Bit Read */ +#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[2]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[2]) Transmit Complete */ +#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[2]) Receive Overrun */ +#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[2]) HRESP Not OK */ +/* -------- GMAC_IMRPQ[2] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) -------- */ +#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[2]) Receive Complete */ +#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[2]) RX Used Bit Read */ +#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[2]) AHB Error */ +#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[2]) Transmit Complete */ +#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[2]) Receive Overrun */ +#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[2]) HRESP Not OK */ +/* -------- GMAC_ST2ER[4] : (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) -------- */ +#define GMAC_ST2ER_COMPVAL_Pos 0 +#define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos) /**< \brief (GMAC_ST2ER[4]) Ethertype Compare Value */ +#define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos))) +/* -------- GMAC_ST2CW00 : (GMAC Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) -------- */ +#define GMAC_ST2CW00_MASKVAL_Pos 0 +#define GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos) /**< \brief (GMAC_ST2CW00) Mask Value */ +#define GMAC_ST2CW00_MASKVAL(value) ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos))) +#define GMAC_ST2CW00_COMPVAL_Pos 16 +#define GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos) /**< \brief (GMAC_ST2CW00) Compare Value */ +#define GMAC_ST2CW00_COMPVAL(value) ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos))) +/* -------- GMAC_ST2CW10 : (GMAC Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) -------- */ +#define GMAC_ST2CW10_OFFSVAL_Pos 0 +#define GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW10) Offset Value in Bytes */ +#define GMAC_ST2CW10_OFFSVAL(value) ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos))) +#define GMAC_ST2CW10_OFFSSTRT_Pos 7 +#define GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW10) Ethernet Frame Offset Start */ +#define GMAC_ST2CW10_OFFSSTRT(value) ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos))) +#define GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW10) Offset from the start of the frame */ +#define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the IP header field */ +#define GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW01 : (GMAC Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) -------- */ +#define GMAC_ST2CW01_MASKVAL_Pos 0 +#define GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos) /**< \brief (GMAC_ST2CW01) Mask Value */ +#define GMAC_ST2CW01_MASKVAL(value) ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos))) +#define GMAC_ST2CW01_COMPVAL_Pos 16 +#define GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos) /**< \brief (GMAC_ST2CW01) Compare Value */ +#define GMAC_ST2CW01_COMPVAL(value) ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos))) +/* -------- GMAC_ST2CW11 : (GMAC Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) -------- */ +#define GMAC_ST2CW11_OFFSVAL_Pos 0 +#define GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW11) Offset Value in Bytes */ +#define GMAC_ST2CW11_OFFSVAL(value) ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos))) +#define GMAC_ST2CW11_OFFSSTRT_Pos 7 +#define GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW11) Ethernet Frame Offset Start */ +#define GMAC_ST2CW11_OFFSSTRT(value) ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos))) +#define GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW11) Offset from the start of the frame */ +#define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the IP header field */ +#define GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW02 : (GMAC Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) -------- */ +#define GMAC_ST2CW02_MASKVAL_Pos 0 +#define GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos) /**< \brief (GMAC_ST2CW02) Mask Value */ +#define GMAC_ST2CW02_MASKVAL(value) ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos))) +#define GMAC_ST2CW02_COMPVAL_Pos 16 +#define GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos) /**< \brief (GMAC_ST2CW02) Compare Value */ +#define GMAC_ST2CW02_COMPVAL(value) ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos))) +/* -------- GMAC_ST2CW12 : (GMAC Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) -------- */ +#define GMAC_ST2CW12_OFFSVAL_Pos 0 +#define GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW12) Offset Value in Bytes */ +#define GMAC_ST2CW12_OFFSVAL(value) ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos))) +#define GMAC_ST2CW12_OFFSSTRT_Pos 7 +#define GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW12) Ethernet Frame Offset Start */ +#define GMAC_ST2CW12_OFFSSTRT(value) ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos))) +#define GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW12) Offset from the start of the frame */ +#define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the IP header field */ +#define GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW03 : (GMAC Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) -------- */ +#define GMAC_ST2CW03_MASKVAL_Pos 0 +#define GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos) /**< \brief (GMAC_ST2CW03) Mask Value */ +#define GMAC_ST2CW03_MASKVAL(value) ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos))) +#define GMAC_ST2CW03_COMPVAL_Pos 16 +#define GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos) /**< \brief (GMAC_ST2CW03) Compare Value */ +#define GMAC_ST2CW03_COMPVAL(value) ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos))) +/* -------- GMAC_ST2CW13 : (GMAC Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) -------- */ +#define GMAC_ST2CW13_OFFSVAL_Pos 0 +#define GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW13) Offset Value in Bytes */ +#define GMAC_ST2CW13_OFFSVAL(value) ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos))) +#define GMAC_ST2CW13_OFFSSTRT_Pos 7 +#define GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW13) Ethernet Frame Offset Start */ +#define GMAC_ST2CW13_OFFSSTRT(value) ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos))) +#define GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW13) Offset from the start of the frame */ +#define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the IP header field */ +#define GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW04 : (GMAC Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) -------- */ +#define GMAC_ST2CW04_MASKVAL_Pos 0 +#define GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos) /**< \brief (GMAC_ST2CW04) Mask Value */ +#define GMAC_ST2CW04_MASKVAL(value) ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos))) +#define GMAC_ST2CW04_COMPVAL_Pos 16 +#define GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos) /**< \brief (GMAC_ST2CW04) Compare Value */ +#define GMAC_ST2CW04_COMPVAL(value) ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos))) +/* -------- GMAC_ST2CW14 : (GMAC Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) -------- */ +#define GMAC_ST2CW14_OFFSVAL_Pos 0 +#define GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW14) Offset Value in Bytes */ +#define GMAC_ST2CW14_OFFSVAL(value) ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos))) +#define GMAC_ST2CW14_OFFSSTRT_Pos 7 +#define GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW14) Ethernet Frame Offset Start */ +#define GMAC_ST2CW14_OFFSSTRT(value) ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos))) +#define GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW14) Offset from the start of the frame */ +#define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the IP header field */ +#define GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW05 : (GMAC Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) -------- */ +#define GMAC_ST2CW05_MASKVAL_Pos 0 +#define GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos) /**< \brief (GMAC_ST2CW05) Mask Value */ +#define GMAC_ST2CW05_MASKVAL(value) ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos))) +#define GMAC_ST2CW05_COMPVAL_Pos 16 +#define GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos) /**< \brief (GMAC_ST2CW05) Compare Value */ +#define GMAC_ST2CW05_COMPVAL(value) ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos))) +/* -------- GMAC_ST2CW15 : (GMAC Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) -------- */ +#define GMAC_ST2CW15_OFFSVAL_Pos 0 +#define GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW15) Offset Value in Bytes */ +#define GMAC_ST2CW15_OFFSVAL(value) ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos))) +#define GMAC_ST2CW15_OFFSSTRT_Pos 7 +#define GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW15) Ethernet Frame Offset Start */ +#define GMAC_ST2CW15_OFFSSTRT(value) ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos))) +#define GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW15) Offset from the start of the frame */ +#define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the IP header field */ +#define GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW06 : (GMAC Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) -------- */ +#define GMAC_ST2CW06_MASKVAL_Pos 0 +#define GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos) /**< \brief (GMAC_ST2CW06) Mask Value */ +#define GMAC_ST2CW06_MASKVAL(value) ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos))) +#define GMAC_ST2CW06_COMPVAL_Pos 16 +#define GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos) /**< \brief (GMAC_ST2CW06) Compare Value */ +#define GMAC_ST2CW06_COMPVAL(value) ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos))) +/* -------- GMAC_ST2CW16 : (GMAC Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) -------- */ +#define GMAC_ST2CW16_OFFSVAL_Pos 0 +#define GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW16) Offset Value in Bytes */ +#define GMAC_ST2CW16_OFFSVAL(value) ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos))) +#define GMAC_ST2CW16_OFFSSTRT_Pos 7 +#define GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW16) Ethernet Frame Offset Start */ +#define GMAC_ST2CW16_OFFSSTRT(value) ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos))) +#define GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW16) Offset from the start of the frame */ +#define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the IP header field */ +#define GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW07 : (GMAC Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) -------- */ +#define GMAC_ST2CW07_MASKVAL_Pos 0 +#define GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos) /**< \brief (GMAC_ST2CW07) Mask Value */ +#define GMAC_ST2CW07_MASKVAL(value) ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos))) +#define GMAC_ST2CW07_COMPVAL_Pos 16 +#define GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos) /**< \brief (GMAC_ST2CW07) Compare Value */ +#define GMAC_ST2CW07_COMPVAL(value) ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos))) +/* -------- GMAC_ST2CW17 : (GMAC Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) -------- */ +#define GMAC_ST2CW17_OFFSVAL_Pos 0 +#define GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW17) Offset Value in Bytes */ +#define GMAC_ST2CW17_OFFSVAL(value) ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos))) +#define GMAC_ST2CW17_OFFSSTRT_Pos 7 +#define GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW17) Ethernet Frame Offset Start */ +#define GMAC_ST2CW17_OFFSSTRT(value) ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos))) +#define GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW17) Offset from the start of the frame */ +#define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the IP header field */ +#define GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW08 : (GMAC Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) -------- */ +#define GMAC_ST2CW08_MASKVAL_Pos 0 +#define GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos) /**< \brief (GMAC_ST2CW08) Mask Value */ +#define GMAC_ST2CW08_MASKVAL(value) ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos))) +#define GMAC_ST2CW08_COMPVAL_Pos 16 +#define GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos) /**< \brief (GMAC_ST2CW08) Compare Value */ +#define GMAC_ST2CW08_COMPVAL(value) ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos))) +/* -------- GMAC_ST2CW18 : (GMAC Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) -------- */ +#define GMAC_ST2CW18_OFFSVAL_Pos 0 +#define GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW18) Offset Value in Bytes */ +#define GMAC_ST2CW18_OFFSVAL(value) ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos))) +#define GMAC_ST2CW18_OFFSSTRT_Pos 7 +#define GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW18) Ethernet Frame Offset Start */ +#define GMAC_ST2CW18_OFFSSTRT(value) ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos))) +#define GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW18) Offset from the start of the frame */ +#define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the IP header field */ +#define GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW09 : (GMAC Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) -------- */ +#define GMAC_ST2CW09_MASKVAL_Pos 0 +#define GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos) /**< \brief (GMAC_ST2CW09) Mask Value */ +#define GMAC_ST2CW09_MASKVAL(value) ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos))) +#define GMAC_ST2CW09_COMPVAL_Pos 16 +#define GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos) /**< \brief (GMAC_ST2CW09) Compare Value */ +#define GMAC_ST2CW09_COMPVAL(value) ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos))) +/* -------- GMAC_ST2CW19 : (GMAC Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) -------- */ +#define GMAC_ST2CW19_OFFSVAL_Pos 0 +#define GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW19) Offset Value in Bytes */ +#define GMAC_ST2CW19_OFFSVAL(value) ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos))) +#define GMAC_ST2CW19_OFFSSTRT_Pos 7 +#define GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW19) Ethernet Frame Offset Start */ +#define GMAC_ST2CW19_OFFSSTRT(value) ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos))) +#define GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW19) Offset from the start of the frame */ +#define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the IP header field */ +#define GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW010 : (GMAC Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) -------- */ +#define GMAC_ST2CW010_MASKVAL_Pos 0 +#define GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos) /**< \brief (GMAC_ST2CW010) Mask Value */ +#define GMAC_ST2CW010_MASKVAL(value) ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos))) +#define GMAC_ST2CW010_COMPVAL_Pos 16 +#define GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos) /**< \brief (GMAC_ST2CW010) Compare Value */ +#define GMAC_ST2CW010_COMPVAL(value) ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos))) +/* -------- GMAC_ST2CW110 : (GMAC Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) -------- */ +#define GMAC_ST2CW110_OFFSVAL_Pos 0 +#define GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW110) Offset Value in Bytes */ +#define GMAC_ST2CW110_OFFSVAL(value) ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos))) +#define GMAC_ST2CW110_OFFSSTRT_Pos 7 +#define GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW110) Ethernet Frame Offset Start */ +#define GMAC_ST2CW110_OFFSSTRT(value) ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos))) +#define GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW110) Offset from the start of the frame */ +#define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the IP header field */ +#define GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW011 : (GMAC Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) -------- */ +#define GMAC_ST2CW011_MASKVAL_Pos 0 +#define GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos) /**< \brief (GMAC_ST2CW011) Mask Value */ +#define GMAC_ST2CW011_MASKVAL(value) ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos))) +#define GMAC_ST2CW011_COMPVAL_Pos 16 +#define GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos) /**< \brief (GMAC_ST2CW011) Compare Value */ +#define GMAC_ST2CW011_COMPVAL(value) ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos))) +/* -------- GMAC_ST2CW111 : (GMAC Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) -------- */ +#define GMAC_ST2CW111_OFFSVAL_Pos 0 +#define GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW111) Offset Value in Bytes */ +#define GMAC_ST2CW111_OFFSVAL(value) ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos))) +#define GMAC_ST2CW111_OFFSSTRT_Pos 7 +#define GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW111) Ethernet Frame Offset Start */ +#define GMAC_ST2CW111_OFFSSTRT(value) ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos))) +#define GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW111) Offset from the start of the frame */ +#define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the IP header field */ +#define GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW012 : (GMAC Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) -------- */ +#define GMAC_ST2CW012_MASKVAL_Pos 0 +#define GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos) /**< \brief (GMAC_ST2CW012) Mask Value */ +#define GMAC_ST2CW012_MASKVAL(value) ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos))) +#define GMAC_ST2CW012_COMPVAL_Pos 16 +#define GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos) /**< \brief (GMAC_ST2CW012) Compare Value */ +#define GMAC_ST2CW012_COMPVAL(value) ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos))) +/* -------- GMAC_ST2CW112 : (GMAC Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) -------- */ +#define GMAC_ST2CW112_OFFSVAL_Pos 0 +#define GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW112) Offset Value in Bytes */ +#define GMAC_ST2CW112_OFFSVAL(value) ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos))) +#define GMAC_ST2CW112_OFFSSTRT_Pos 7 +#define GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW112) Ethernet Frame Offset Start */ +#define GMAC_ST2CW112_OFFSSTRT(value) ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos))) +#define GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW112) Offset from the start of the frame */ +#define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the IP header field */ +#define GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW013 : (GMAC Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) -------- */ +#define GMAC_ST2CW013_MASKVAL_Pos 0 +#define GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos) /**< \brief (GMAC_ST2CW013) Mask Value */ +#define GMAC_ST2CW013_MASKVAL(value) ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos))) +#define GMAC_ST2CW013_COMPVAL_Pos 16 +#define GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos) /**< \brief (GMAC_ST2CW013) Compare Value */ +#define GMAC_ST2CW013_COMPVAL(value) ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos))) +/* -------- GMAC_ST2CW113 : (GMAC Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) -------- */ +#define GMAC_ST2CW113_OFFSVAL_Pos 0 +#define GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW113) Offset Value in Bytes */ +#define GMAC_ST2CW113_OFFSVAL(value) ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos))) +#define GMAC_ST2CW113_OFFSSTRT_Pos 7 +#define GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW113) Ethernet Frame Offset Start */ +#define GMAC_ST2CW113_OFFSSTRT(value) ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos))) +#define GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW113) Offset from the start of the frame */ +#define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the IP header field */ +#define GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW014 : (GMAC Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) -------- */ +#define GMAC_ST2CW014_MASKVAL_Pos 0 +#define GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos) /**< \brief (GMAC_ST2CW014) Mask Value */ +#define GMAC_ST2CW014_MASKVAL(value) ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos))) +#define GMAC_ST2CW014_COMPVAL_Pos 16 +#define GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos) /**< \brief (GMAC_ST2CW014) Compare Value */ +#define GMAC_ST2CW014_COMPVAL(value) ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos))) +/* -------- GMAC_ST2CW114 : (GMAC Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) -------- */ +#define GMAC_ST2CW114_OFFSVAL_Pos 0 +#define GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW114) Offset Value in Bytes */ +#define GMAC_ST2CW114_OFFSVAL(value) ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos))) +#define GMAC_ST2CW114_OFFSSTRT_Pos 7 +#define GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW114) Ethernet Frame Offset Start */ +#define GMAC_ST2CW114_OFFSSTRT(value) ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos))) +#define GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW114) Offset from the start of the frame */ +#define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the IP header field */ +#define GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW015 : (GMAC Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) -------- */ +#define GMAC_ST2CW015_MASKVAL_Pos 0 +#define GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos) /**< \brief (GMAC_ST2CW015) Mask Value */ +#define GMAC_ST2CW015_MASKVAL(value) ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos))) +#define GMAC_ST2CW015_COMPVAL_Pos 16 +#define GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos) /**< \brief (GMAC_ST2CW015) Compare Value */ +#define GMAC_ST2CW015_COMPVAL(value) ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos))) +/* -------- GMAC_ST2CW115 : (GMAC Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) -------- */ +#define GMAC_ST2CW115_OFFSVAL_Pos 0 +#define GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW115) Offset Value in Bytes */ +#define GMAC_ST2CW115_OFFSVAL(value) ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos))) +#define GMAC_ST2CW115_OFFSSTRT_Pos 7 +#define GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW115) Ethernet Frame Offset Start */ +#define GMAC_ST2CW115_OFFSSTRT(value) ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos))) +#define GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW115) Offset from the start of the frame */ +#define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the IP header field */ +#define GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW016 : (GMAC Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) -------- */ +#define GMAC_ST2CW016_MASKVAL_Pos 0 +#define GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos) /**< \brief (GMAC_ST2CW016) Mask Value */ +#define GMAC_ST2CW016_MASKVAL(value) ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos))) +#define GMAC_ST2CW016_COMPVAL_Pos 16 +#define GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos) /**< \brief (GMAC_ST2CW016) Compare Value */ +#define GMAC_ST2CW016_COMPVAL(value) ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos))) +/* -------- GMAC_ST2CW116 : (GMAC Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) -------- */ +#define GMAC_ST2CW116_OFFSVAL_Pos 0 +#define GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW116) Offset Value in Bytes */ +#define GMAC_ST2CW116_OFFSVAL(value) ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos))) +#define GMAC_ST2CW116_OFFSSTRT_Pos 7 +#define GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW116) Ethernet Frame Offset Start */ +#define GMAC_ST2CW116_OFFSSTRT(value) ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos))) +#define GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW116) Offset from the start of the frame */ +#define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the IP header field */ +#define GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW017 : (GMAC Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) -------- */ +#define GMAC_ST2CW017_MASKVAL_Pos 0 +#define GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos) /**< \brief (GMAC_ST2CW017) Mask Value */ +#define GMAC_ST2CW017_MASKVAL(value) ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos))) +#define GMAC_ST2CW017_COMPVAL_Pos 16 +#define GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos) /**< \brief (GMAC_ST2CW017) Compare Value */ +#define GMAC_ST2CW017_COMPVAL(value) ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos))) +/* -------- GMAC_ST2CW117 : (GMAC Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) -------- */ +#define GMAC_ST2CW117_OFFSVAL_Pos 0 +#define GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW117) Offset Value in Bytes */ +#define GMAC_ST2CW117_OFFSVAL(value) ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos))) +#define GMAC_ST2CW117_OFFSSTRT_Pos 7 +#define GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW117) Ethernet Frame Offset Start */ +#define GMAC_ST2CW117_OFFSSTRT(value) ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos))) +#define GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW117) Offset from the start of the frame */ +#define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the IP header field */ +#define GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW018 : (GMAC Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) -------- */ +#define GMAC_ST2CW018_MASKVAL_Pos 0 +#define GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos) /**< \brief (GMAC_ST2CW018) Mask Value */ +#define GMAC_ST2CW018_MASKVAL(value) ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos))) +#define GMAC_ST2CW018_COMPVAL_Pos 16 +#define GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos) /**< \brief (GMAC_ST2CW018) Compare Value */ +#define GMAC_ST2CW018_COMPVAL(value) ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos))) +/* -------- GMAC_ST2CW118 : (GMAC Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) -------- */ +#define GMAC_ST2CW118_OFFSVAL_Pos 0 +#define GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW118) Offset Value in Bytes */ +#define GMAC_ST2CW118_OFFSVAL(value) ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos))) +#define GMAC_ST2CW118_OFFSSTRT_Pos 7 +#define GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW118) Ethernet Frame Offset Start */ +#define GMAC_ST2CW118_OFFSSTRT(value) ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos))) +#define GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW118) Offset from the start of the frame */ +#define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the IP header field */ +#define GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW019 : (GMAC Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) -------- */ +#define GMAC_ST2CW019_MASKVAL_Pos 0 +#define GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos) /**< \brief (GMAC_ST2CW019) Mask Value */ +#define GMAC_ST2CW019_MASKVAL(value) ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos))) +#define GMAC_ST2CW019_COMPVAL_Pos 16 +#define GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos) /**< \brief (GMAC_ST2CW019) Compare Value */ +#define GMAC_ST2CW019_COMPVAL(value) ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos))) +/* -------- GMAC_ST2CW119 : (GMAC Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) -------- */ +#define GMAC_ST2CW119_OFFSVAL_Pos 0 +#define GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW119) Offset Value in Bytes */ +#define GMAC_ST2CW119_OFFSVAL(value) ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos))) +#define GMAC_ST2CW119_OFFSSTRT_Pos 7 +#define GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW119) Ethernet Frame Offset Start */ +#define GMAC_ST2CW119_OFFSSTRT(value) ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos))) +#define GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW119) Offset from the start of the frame */ +#define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the IP header field */ +#define GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW020 : (GMAC Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) -------- */ +#define GMAC_ST2CW020_MASKVAL_Pos 0 +#define GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos) /**< \brief (GMAC_ST2CW020) Mask Value */ +#define GMAC_ST2CW020_MASKVAL(value) ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos))) +#define GMAC_ST2CW020_COMPVAL_Pos 16 +#define GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos) /**< \brief (GMAC_ST2CW020) Compare Value */ +#define GMAC_ST2CW020_COMPVAL(value) ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos))) +/* -------- GMAC_ST2CW120 : (GMAC Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) -------- */ +#define GMAC_ST2CW120_OFFSVAL_Pos 0 +#define GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW120) Offset Value in Bytes */ +#define GMAC_ST2CW120_OFFSVAL(value) ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos))) +#define GMAC_ST2CW120_OFFSSTRT_Pos 7 +#define GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW120) Ethernet Frame Offset Start */ +#define GMAC_ST2CW120_OFFSSTRT(value) ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos))) +#define GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW120) Offset from the start of the frame */ +#define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the IP header field */ +#define GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW021 : (GMAC Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) -------- */ +#define GMAC_ST2CW021_MASKVAL_Pos 0 +#define GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos) /**< \brief (GMAC_ST2CW021) Mask Value */ +#define GMAC_ST2CW021_MASKVAL(value) ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos))) +#define GMAC_ST2CW021_COMPVAL_Pos 16 +#define GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos) /**< \brief (GMAC_ST2CW021) Compare Value */ +#define GMAC_ST2CW021_COMPVAL(value) ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos))) +/* -------- GMAC_ST2CW121 : (GMAC Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) -------- */ +#define GMAC_ST2CW121_OFFSVAL_Pos 0 +#define GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW121) Offset Value in Bytes */ +#define GMAC_ST2CW121_OFFSVAL(value) ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos))) +#define GMAC_ST2CW121_OFFSSTRT_Pos 7 +#define GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW121) Ethernet Frame Offset Start */ +#define GMAC_ST2CW121_OFFSSTRT(value) ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos))) +#define GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW121) Offset from the start of the frame */ +#define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the IP header field */ +#define GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW022 : (GMAC Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) -------- */ +#define GMAC_ST2CW022_MASKVAL_Pos 0 +#define GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos) /**< \brief (GMAC_ST2CW022) Mask Value */ +#define GMAC_ST2CW022_MASKVAL(value) ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos))) +#define GMAC_ST2CW022_COMPVAL_Pos 16 +#define GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos) /**< \brief (GMAC_ST2CW022) Compare Value */ +#define GMAC_ST2CW022_COMPVAL(value) ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos))) +/* -------- GMAC_ST2CW122 : (GMAC Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) -------- */ +#define GMAC_ST2CW122_OFFSVAL_Pos 0 +#define GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW122) Offset Value in Bytes */ +#define GMAC_ST2CW122_OFFSVAL(value) ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos))) +#define GMAC_ST2CW122_OFFSSTRT_Pos 7 +#define GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW122) Ethernet Frame Offset Start */ +#define GMAC_ST2CW122_OFFSSTRT(value) ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos))) +#define GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW122) Offset from the start of the frame */ +#define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the IP header field */ +#define GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW023 : (GMAC Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) -------- */ +#define GMAC_ST2CW023_MASKVAL_Pos 0 +#define GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos) /**< \brief (GMAC_ST2CW023) Mask Value */ +#define GMAC_ST2CW023_MASKVAL(value) ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos))) +#define GMAC_ST2CW023_COMPVAL_Pos 16 +#define GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos) /**< \brief (GMAC_ST2CW023) Compare Value */ +#define GMAC_ST2CW023_COMPVAL(value) ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos))) +/* -------- GMAC_ST2CW123 : (GMAC Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) -------- */ +#define GMAC_ST2CW123_OFFSVAL_Pos 0 +#define GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW123) Offset Value in Bytes */ +#define GMAC_ST2CW123_OFFSVAL(value) ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos))) +#define GMAC_ST2CW123_OFFSSTRT_Pos 7 +#define GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW123) Ethernet Frame Offset Start */ +#define GMAC_ST2CW123_OFFSSTRT(value) ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos))) +#define GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW123) Offset from the start of the frame */ +#define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the IP header field */ +#define GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field */ + +/*@}*/ + + +#endif /* _SAME70_GMAC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_gpbr.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_gpbr.h new file mode 100644 index 0000000000..a88b2b63c4 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_gpbr.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_GPBR_COMPONENT_ +#define _SAME70_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */ +/* ============================================================================= */ +/** \addtogroup SAME70_GPBR General Purpose Backup Registers */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAME70_GPBR_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_hsmci.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_hsmci.h new file mode 100644 index 0000000000..47f3e1c57c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_hsmci.h @@ -0,0 +1,335 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_HSMCI_COMPONENT_ +#define _SAME70_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + __I uint32_t Reserved1[2]; + __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + __I uint32_t Reserved2[35]; + __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[69]; + __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos))) +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos))) +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos))) +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos))) +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos))) +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos))) +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos))) +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos))) +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))) +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos))) +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended (cleared on read) */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error (cleared on read) */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error (cleared on read) */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error (cleared on read) */ +#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error (cleared on read) */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ +#define HSMCI_DMA_CHKSIZE_Pos 4 +#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos))) +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */ +#define HSMCI_WPMR_WPKEY_Pos 8 +#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */ +#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos))) +#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WPVSRC_Pos 8 +#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */ +/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) + +/*@}*/ + + +#endif /* _SAME70_HSMCI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_icm.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_icm.h new file mode 100644 index 0000000000..62a077414f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_icm.h @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_ICM_COMPONENT_ +#define _SAME70_ICM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */ +/* ============================================================================= */ +/** \addtogroup SAME70_ICM Integrity Check Monitor */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Icm hardware registers */ +typedef struct { + __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */ + __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */ + __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */ +} Icm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */ +#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */ +#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */ +#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */ +#define ICM_CFG_BBC_Pos 4 +#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */ +#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))) +#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */ +#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */ +#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */ +#define ICM_CFG_UALGO_Pos 13 +#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */ +#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))) +#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_HAPROT_Pos 16 +#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */ +#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))) +#define ICM_CFG_DAPROT_Pos 24 +#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */ +#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))) +/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */ +#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */ +#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */ +#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */ +#define ICM_CTRL_REHASH_Pos 4 +#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */ +#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))) +#define ICM_CTRL_RMDIS_Pos 8 +#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */ +#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))) +#define ICM_CTRL_RMEN_Pos 12 +#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */ +#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))) +/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */ +#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */ +#define ICM_SR_RAWRMDIS_Pos 8 +#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Raw Status */ +#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))) +#define ICM_SR_RMDIS_Pos 12 +#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */ +#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))) +/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */ +#define ICM_IER_RHC_Pos 0 +#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */ +#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))) +#define ICM_IER_RDM_Pos 4 +#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */ +#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))) +#define ICM_IER_RBE_Pos 8 +#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */ +#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))) +#define ICM_IER_RWC_Pos 12 +#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */ +#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))) +#define ICM_IER_REC_Pos 16 +#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */ +#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))) +#define ICM_IER_RSU_Pos 20 +#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */ +#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))) +#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */ +/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */ +#define ICM_IDR_RHC_Pos 0 +#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */ +#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))) +#define ICM_IDR_RDM_Pos 4 +#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */ +#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))) +#define ICM_IDR_RBE_Pos 8 +#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */ +#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))) +#define ICM_IDR_RWC_Pos 12 +#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */ +#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))) +#define ICM_IDR_REC_Pos 16 +#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */ +#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))) +#define ICM_IDR_RSU_Pos 20 +#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */ +#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))) +#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */ +/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */ +#define ICM_IMR_RHC_Pos 0 +#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */ +#define ICM_IMR_RDM_Pos 4 +#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */ +#define ICM_IMR_RBE_Pos 8 +#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */ +#define ICM_IMR_RWC_Pos 12 +#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */ +#define ICM_IMR_REC_Pos 16 +#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */ +#define ICM_IMR_RSU_Pos 20 +#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */ +#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */ +/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */ +#define ICM_ISR_RHC_Pos 0 +#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */ +#define ICM_ISR_RDM_Pos 4 +#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */ +#define ICM_ISR_RBE_Pos 8 +#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */ +#define ICM_ISR_RWC_Pos 12 +#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */ +#define ICM_ISR_REC_Pos 16 +#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */ +#define ICM_ISR_RSU_Pos 20 +#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */ +#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */ +/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */ +#define ICM_UASR_URAT_Pos 0 +#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */ +/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */ +#define ICM_DSCR_DASA_Pos 6 +#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */ +#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))) +/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */ +#define ICM_HASH_HASA_Pos 7 +#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */ +#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))) +/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */ +#define ICM_UIHVAL_VAL_Pos 0 +#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */ +#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))) + +/*@}*/ + + +#endif /* _SAME70_ICM_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_isi.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_isi.h new file mode 100644 index 0000000000..78839a68a6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_isi.h @@ -0,0 +1,280 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_ISI_COMPONENT_ +#define _SAME70_ISI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Image Sensor Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_ISI Image Sensor Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Isi hardware registers */ +typedef struct { + __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */ + __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */ + __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */ + __I uint32_t Reserved1[34]; + __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */ +} Isi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */ +#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */ +#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */ +#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */ +#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */ +#define ISI_CFG1_FRATE_Pos 8 +#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */ +#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))) +#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */ +#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */ +#define ISI_CFG1_THMASK_Pos 13 +#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */ +#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos))) +#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_SLD_Pos 16 +#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */ +#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))) +#define ISI_CFG1_SFD_Pos 24 +#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */ +#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))) +/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos 0 +#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))) +#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */ +#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */ +#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */ +#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */ +#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */ +#define ISI_CFG2_IM_HSIZE_Pos 16 +#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))) +#define ISI_CFG2_YCC_SWAP_Pos 28 +#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */ +#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))) +#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_RGB_CFG_Pos 30 +#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */ +#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))) +#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos 0 +#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */ +#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))) +#define ISI_PSIZE_PREV_HSIZE_Pos 16 +#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */ +#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))) +/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos 0 +#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */ +#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))) +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos 0 +#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))) +#define ISI_Y2R_SET0_C1_Pos 8 +#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))) +#define ISI_Y2R_SET0_C2_Pos 16 +#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))) +#define ISI_Y2R_SET0_C3_Pos 24 +#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))) +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos 0 +#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))) +#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */ +#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */ +#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */ +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos 0 +#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))) +#define ISI_R2Y_SET0_C1_Pos 8 +#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))) +#define ISI_R2Y_SET0_C2_Pos 16 +#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))) +#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */ +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos 0 +#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))) +#define ISI_R2Y_SET1_C4_Pos 8 +#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))) +#define ISI_R2Y_SET1_C5_Pos 16 +#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */ +#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))) +#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */ +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos 0 +#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */ +#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))) +#define ISI_R2Y_SET2_C7_Pos 8 +#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */ +#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))) +#define ISI_R2Y_SET2_C8_Pos 16 +#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */ +#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))) +#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */ +/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */ +#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */ +#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */ +#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */ +#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */ +/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */ +#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */ +#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */ +#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */ +#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */ +#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */ +#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */ +#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */ +#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */ +#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */ +#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */ +/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */ +#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */ +#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */ +#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */ +#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */ +#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */ +#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */ +#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */ +#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */ +/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */ +#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */ +#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */ +#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */ +#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */ +#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */ +#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */ +/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */ +#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */ +#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */ +#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */ +#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */ +#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */ +#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */ +#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */ +#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */ +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */ +#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */ +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */ +#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */ +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */ +#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */ +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos 2 +#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */ +#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))) +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */ +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos 2 +#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */ +#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))) +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos 2 +#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */ +#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))) +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */ +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos 2 +#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */ +#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))) +/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */ +#define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */ +#define ISI_WPMR_WPKEY_Pos 8 +#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */ +#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos))) +#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */ +#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */ +#define ISI_WPSR_WPVSRC_Pos 8 +#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_ISI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_matrix.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_matrix.h new file mode 100644 index 0000000000..f9325ce550 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_matrix.h @@ -0,0 +1,301 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_MATRIX_COMPONENT_ +#define _SAME70_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAME70_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MatrixPr hardware registers */ +typedef struct { + __IO uint32_t MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */ +} MatrixPr; +/** \brief Matrix hardware registers */ +#define MATRIXPR_NUMBER 9 +typedef struct { + __IO uint32_t MATRIX_MCFG0; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register 0 */ + __IO uint32_t MATRIX_MCFG1; /**< \brief (Matrix Offset: 0x0004) Master Configuration Register 1 */ + __IO uint32_t MATRIX_MCFG2; /**< \brief (Matrix Offset: 0x0008) Master Configuration Register 2 */ + __IO uint32_t MATRIX_MCFG3; /**< \brief (Matrix Offset: 0x000C) Master Configuration Register 3 */ + __IO uint32_t MATRIX_MCFG4; /**< \brief (Matrix Offset: 0x0010) Master Configuration Register 4 */ + __IO uint32_t MATRIX_MCFG5; /**< \brief (Matrix Offset: 0x0014) Master Configuration Register 5 */ + __IO uint32_t MATRIX_MCFG6; /**< \brief (Matrix Offset: 0x0018) Master Configuration Register 6 */ + __I uint32_t Reserved1[1]; + __IO uint32_t MATRIX_MCFG8; /**< \brief (Matrix Offset: 0x0020) Master Configuration Register 8 */ + __IO uint32_t MATRIX_MCFG9; /**< \brief (Matrix Offset: 0x0024) Master Configuration Register 9 */ + __IO uint32_t MATRIX_MCFG10; /**< \brief (Matrix Offset: 0x0028) Master Configuration Register 10 */ + __IO uint32_t MATRIX_MCFG11; /**< \brief (Matrix Offset: 0x002C) Master Configuration Register 11 */ + __I uint32_t Reserved2[4]; + __IO uint32_t MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + __I uint32_t Reserved3[7]; + MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 8 */ + __I uint32_t Reserved4[14]; + __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t CCFG_CAN0; /**< \brief (Matrix Offset: 0x0110) CAN0 Configuration Register */ + __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O and CAN1 Configuration Register */ + __I uint32_t Reserved6[3]; + __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */ + __I uint32_t Reserved7[47]; + __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */ +#define MATRIX_MCFG0_ULBT_Pos 0 +#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) /**< \brief (MATRIX_MCFG0) Undefined Length Burst Type */ +#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos))) +#define MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG0) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG0) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG0) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG0) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG0) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG0) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG0) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG0) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */ +#define MATRIX_MCFG1_ULBT_Pos 0 +#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) /**< \brief (MATRIX_MCFG1) Undefined Length Burst Type */ +#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos))) +#define MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG1) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG1) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG1) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG1) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG1) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG1) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG1) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG1) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */ +#define MATRIX_MCFG2_ULBT_Pos 0 +#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) /**< \brief (MATRIX_MCFG2) Undefined Length Burst Type */ +#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos))) +#define MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG2) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG2) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG2) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG2) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG2) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG2) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG2) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG2) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */ +#define MATRIX_MCFG3_ULBT_Pos 0 +#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) /**< \brief (MATRIX_MCFG3) Undefined Length Burst Type */ +#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos))) +#define MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG3) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG3) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG3) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG3) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG3) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG3) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG3) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG3) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */ +#define MATRIX_MCFG4_ULBT_Pos 0 +#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) /**< \brief (MATRIX_MCFG4) Undefined Length Burst Type */ +#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos))) +#define MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG4) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG4) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG4) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG4) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG4) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG4) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG4) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG4) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */ +#define MATRIX_MCFG5_ULBT_Pos 0 +#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) /**< \brief (MATRIX_MCFG5) Undefined Length Burst Type */ +#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos))) +#define MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG5) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG5) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG5) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG5) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG5) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG5) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG5) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG5) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */ +#define MATRIX_MCFG6_ULBT_Pos 0 +#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) /**< \brief (MATRIX_MCFG6) Undefined Length Burst Type */ +#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos))) +#define MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG6) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG6) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG6) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG6) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG6) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG6) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG6) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG6) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */ +#define MATRIX_MCFG8_ULBT_Pos 0 +#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) /**< \brief (MATRIX_MCFG8) Undefined Length Burst Type */ +#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos))) +#define MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG8) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG8) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG8) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG8) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG8) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG8) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG8) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG8) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG9 : (MATRIX Offset: 0x0024) Master Configuration Register 9 -------- */ +#define MATRIX_MCFG9_ULBT_Pos 0 +#define MATRIX_MCFG9_ULBT_Msk (0x7u << MATRIX_MCFG9_ULBT_Pos) /**< \brief (MATRIX_MCFG9) Undefined Length Burst Type */ +#define MATRIX_MCFG9_ULBT(value) ((MATRIX_MCFG9_ULBT_Msk & ((value) << MATRIX_MCFG9_ULBT_Pos))) +#define MATRIX_MCFG9_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG9) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG9_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG9) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG9_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG9) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG9_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG9) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG9_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG9) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG9_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG9) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG9_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG9) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG9_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG9) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG10 : (MATRIX Offset: 0x0028) Master Configuration Register 10 -------- */ +#define MATRIX_MCFG10_ULBT_Pos 0 +#define MATRIX_MCFG10_ULBT_Msk (0x7u << MATRIX_MCFG10_ULBT_Pos) /**< \brief (MATRIX_MCFG10) Undefined Length Burst Type */ +#define MATRIX_MCFG10_ULBT(value) ((MATRIX_MCFG10_ULBT_Msk & ((value) << MATRIX_MCFG10_ULBT_Pos))) +#define MATRIX_MCFG10_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG10) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG10_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG10) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG10_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG10) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG10_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG10) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG10_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG10) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG10_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG10) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG10_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG10) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG10_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG10) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG11 : (MATRIX Offset: 0x002C) Master Configuration Register 11 -------- */ +#define MATRIX_MCFG11_ULBT_Pos 0 +#define MATRIX_MCFG11_ULBT_Msk (0x7u << MATRIX_MCFG11_ULBT_Pos) /**< \brief (MATRIX_MCFG11) Undefined Length Burst Type */ +#define MATRIX_MCFG11_ULBT(value) ((MATRIX_MCFG11_ULBT_Msk & ((value) << MATRIX_MCFG11_ULBT_Pos))) +#define MATRIX_MCFG11_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG11) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG11_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG11) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG11_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG11) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG11_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG11) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG11_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG11) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG11_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG11) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG11_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG11) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG11_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG11) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS_M0PR_Pos 0 +#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */ +#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos))) +#define MATRIX_PRAS_M1PR_Pos 4 +#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */ +#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos))) +#define MATRIX_PRAS_M2PR_Pos 8 +#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */ +#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos))) +#define MATRIX_PRAS_M3PR_Pos 12 +#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */ +#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos))) +#define MATRIX_PRAS_M4PR_Pos 16 +#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */ +#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos))) +#define MATRIX_PRAS_M5PR_Pos 20 +#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */ +#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos))) +#define MATRIX_PRAS_M6PR_Pos 24 +#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */ +#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos))) +/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS_M8PR_Pos 0 +#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */ +#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos))) +#define MATRIX_PRBS_M9PR_Pos 4 +#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */ +#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos))) +#define MATRIX_PRBS_M10PR_Pos 8 +#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */ +#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos))) +#define MATRIX_PRBS_M11PR_Pos 12 +#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */ +#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos))) +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */ +#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */ +#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */ +#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */ +#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */ +#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */ +#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */ +#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 */ +#define MATRIX_MRCR_RCB9 (0x1u << 9) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 9 */ +#define MATRIX_MRCR_RCB10 (0x1u << 10) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 10 */ +#define MATRIX_MRCR_RCB11 (0x1u << 11) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 11 */ +/* -------- CCFG_CAN0 : (MATRIX Offset: 0x0110) CAN0 Configuration Register -------- */ +#define CCFG_CAN0_CAN0DMABA_Pos 16 +#define CCFG_CAN0_CAN0DMABA_Msk (0xffffu << CCFG_CAN0_CAN0DMABA_Pos) /**< \brief (CCFG_CAN0) CAN0 DMA Base Address */ +#define CCFG_CAN0_CAN0DMABA(value) ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos))) +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O and CAN1 Configuration Register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +#define CCFG_SYSIO_CAN1DMABA_Pos 16 +#define CCFG_SYSIO_CAN1DMABA_Msk (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos) /**< \brief (CCFG_SYSIO) CAN1 DMA Base Address */ +#define CCFG_SYSIO_CAN1DMABA(value) ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos))) +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /**< \brief (CCFG_SMCNFCS) SDRAM Enable */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_MATRIX_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_mcan.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_mcan.h new file mode 100644 index 0000000000..aa9784e723 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_mcan.h @@ -0,0 +1,845 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_MCAN_COMPONENT_ +#define _SAME70_MCAN_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Controller Area Network */ +/* ============================================================================= */ +/** \addtogroup SAME70_MCAN Controller Area Network */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mcan hardware registers */ +typedef struct { + __I uint32_t Reserved1[2]; + __IO uint32_t MCAN_CUST; /**< \brief (Mcan Offset: 0x08) Customer Register */ + __IO uint32_t MCAN_FBTP; /**< \brief (Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TEST; /**< \brief (Mcan Offset: 0x10) Test Register */ + __IO uint32_t MCAN_RWD; /**< \brief (Mcan Offset: 0x14) RAM Watchdog Register */ + __IO uint32_t MCAN_CCCR; /**< \brief (Mcan Offset: 0x18) CC Control Register */ + __IO uint32_t MCAN_BTP; /**< \brief (Mcan Offset: 0x1C) Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TSCC; /**< \brief (Mcan Offset: 0x20) Timestamp Counter Configuration Register */ + __IO uint32_t MCAN_TSCV; /**< \brief (Mcan Offset: 0x24) Timestamp Counter Value Register */ + __IO uint32_t MCAN_TOCC; /**< \brief (Mcan Offset: 0x28) Timeout Counter Configuration Register */ + __IO uint32_t MCAN_TOCV; /**< \brief (Mcan Offset: 0x2C) Timeout Counter Value Register */ + __I uint32_t Reserved2[4]; + __I uint32_t MCAN_ECR; /**< \brief (Mcan Offset: 0x40) Error Counter Register */ + __I uint32_t MCAN_PSR; /**< \brief (Mcan Offset: 0x44) Protocol Status Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t MCAN_IR; /**< \brief (Mcan Offset: 0x50) Interrupt Register */ + __IO uint32_t MCAN_IE; /**< \brief (Mcan Offset: 0x54) Interrupt Enable Register */ + __IO uint32_t MCAN_ILS; /**< \brief (Mcan Offset: 0x58) Interrupt Line Select Register */ + __IO uint32_t MCAN_ILE; /**< \brief (Mcan Offset: 0x5C) Interrupt Line Enable Register */ + __I uint32_t Reserved4[8]; + __IO uint32_t MCAN_GFC; /**< \brief (Mcan Offset: 0x80) Global Filter Configuration Register */ + __IO uint32_t MCAN_SIDFC; /**< \brief (Mcan Offset: 0x84) Standard ID Filter Configuration Register */ + __IO uint32_t MCAN_XIDFC; /**< \brief (Mcan Offset: 0x88) Extended ID Filter Configuration Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t MCAN_XIDAM; /**< \brief (Mcan Offset: 0x90) Extended ID AND Mask Register */ + __I uint32_t MCAN_HPMS; /**< \brief (Mcan Offset: 0x94) High Priority Message Status Register */ + __IO uint32_t MCAN_NDAT1; /**< \brief (Mcan Offset: 0x98) New Data 1 Register */ + __IO uint32_t MCAN_NDAT2; /**< \brief (Mcan Offset: 0x9C) New Data 2 Register */ + __IO uint32_t MCAN_RXF0C; /**< \brief (Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register */ + __I uint32_t MCAN_RXF0S; /**< \brief (Mcan Offset: 0xA4) Receive FIFO 0 Status Register */ + __IO uint32_t MCAN_RXF0A; /**< \brief (Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register */ + __IO uint32_t MCAN_RXBC; /**< \brief (Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register */ + __IO uint32_t MCAN_RXF1C; /**< \brief (Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register */ + __I uint32_t MCAN_RXF1S; /**< \brief (Mcan Offset: 0xB4) Receive FIFO 1 Status Register */ + __IO uint32_t MCAN_RXF1A; /**< \brief (Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register */ + __IO uint32_t MCAN_RXESC; /**< \brief (Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register */ + __IO uint32_t MCAN_TXBC; /**< \brief (Mcan Offset: 0xC0) Transmit Buffer Configuration Register */ + __I uint32_t MCAN_TXFQS; /**< \brief (Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register */ + __IO uint32_t MCAN_TXESC; /**< \brief (Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register */ + __I uint32_t MCAN_TXBRP; /**< \brief (Mcan Offset: 0xCC) Transmit Buffer Request Pending Register */ + __IO uint32_t MCAN_TXBAR; /**< \brief (Mcan Offset: 0xD0) Transmit Buffer Add Request Register */ + __IO uint32_t MCAN_TXBCR; /**< \brief (Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register */ + __I uint32_t MCAN_TXBTO; /**< \brief (Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register */ + __I uint32_t MCAN_TXBCF; /**< \brief (Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register */ + __IO uint32_t MCAN_TXBTIE; /**< \brief (Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register */ + __IO uint32_t MCAN_TXBCIE; /**< \brief (Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t MCAN_TXEFC; /**< \brief (Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register */ + __I uint32_t MCAN_TXEFS; /**< \brief (Mcan Offset: 0xF4) Transmit Event FIFO Status Register */ + __IO uint32_t MCAN_TXEFA; /**< \brief (Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register */ +} Mcan; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */ +#define MCAN_CUST_CSV_Pos 0 +#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos) /**< \brief (MCAN_CUST) Customer-specific Value */ +#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos))) +/* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */ +#define MCAN_FBTP_FSJW_Pos 0 +#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ +#define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos))) +#define MCAN_FBTP_FTSEG2_Pos 4 +#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ +#define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos))) +#define MCAN_FBTP_FTSEG1_Pos 8 +#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ +#define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos))) +#define MCAN_FBTP_FBRP_Pos 16 +#define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos) /**< \brief (MCAN_FBTP) Fast Baud Rate Prescaler */ +#define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos))) +#define MCAN_FBTP_TDC (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation */ +#define MCAN_FBTP_TDC_DISABLED (0x0u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation disabled. */ +#define MCAN_FBTP_TDC_ENABLED (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation enabled. */ +#define MCAN_FBTP_TDCO_Pos 24 +#define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation Offset */ +#define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos))) +/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */ +#define MCAN_TEST_LBCK (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back Mode (read/write) */ +#define MCAN_TEST_LBCK_DISABLED (0x0u << 4) /**< \brief (MCAN_TEST) Reset value. Loop Back mode is disabled. */ +#define MCAN_TEST_LBCK_ENABLED (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back mode is enabled (see Section 1.5.1.9). */ +#define MCAN_TEST_TX_Pos 5 +#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos) /**< \brief (MCAN_TEST) Control of Transmit Pin (read/write) */ +#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos))) +#define MCAN_TEST_TX_RESET (0x0u << 5) /**< \brief (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5) /**< \brief (MCAN_TEST) Sample Point can be monitored at pin CANTX. */ +#define MCAN_TEST_TX_DOMINANT (0x2u << 5) /**< \brief (MCAN_TEST) Dominant ('0') level at pin CANTX. */ +#define MCAN_TEST_TX_RECESSIVE (0x3u << 5) /**< \brief (MCAN_TEST) Recessive ('1') at pin CANTX. */ +#define MCAN_TEST_RX (0x1u << 7) /**< \brief (MCAN_TEST) Receive Pin (read-only) */ +#define MCAN_TEST_TDCV_Pos 8 +#define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos) /**< \brief (MCAN_TEST) Transceiver Delay Compensation Value (read-only) */ +#define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos))) +/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */ +#define MCAN_RWD_WDC_Pos 0 +#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos) /**< \brief (MCAN_RWD) Watchdog Configuration (read/write) */ +#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos))) +#define MCAN_RWD_WDV_Pos 8 +#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos) /**< \brief (MCAN_RWD) Watchdog Value (read-only) */ +#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos))) +/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */ +#define MCAN_CCCR_INIT (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization (read/write) */ +#define MCAN_CCCR_INIT_DISABLED (0x0u << 0) /**< \brief (MCAN_CCCR) Normal operation. */ +#define MCAN_CCCR_INIT_ENABLED (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization is started. */ +#define MCAN_CCCR_CCE (0x1u << 1) /**< \brief (MCAN_CCCR) Configuration Change Enable (read/write, write protection) */ +#define MCAN_CCCR_CCE_PROTECTED (0x0u << 1) /**< \brief (MCAN_CCCR) The processor has no write access to the protected configuration registers. */ +#define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1) /**< \brief (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */ +#define MCAN_CCCR_ASM (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_ASM_NORMAL (0x0u << 2) /**< \brief (MCAN_CCCR) Normal CAN operation. */ +#define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted operation mode active. */ +#define MCAN_CCCR_CSA (0x1u << 3) /**< \brief (MCAN_CCCR) Clock Stop Acknowledge (read-only) */ +#define MCAN_CCCR_CSR (0x1u << 4) /**< \brief (MCAN_CCCR) Clock Stop Request (read/write) */ +#define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4) /**< \brief (MCAN_CCCR) No clock stop is requested. */ +#define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4) /**< \brief (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */ +#define MCAN_CCCR_MON (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_MON_DISABLED (0x0u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is disabled. */ +#define MCAN_CCCR_MON_ENABLED (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is enabled. */ +#define MCAN_CCCR_DAR (0x1u << 6) /**< \brief (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) */ +#define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission disabled. */ +#define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */ +#define MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ +#define MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ +#define MCAN_CCCR_CME_Pos 8 +#define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos) /**< \brief (MCAN_CCCR) CAN Mode Enable (read/write, write protection) */ +#define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos))) +#define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8) /**< \brief (MCAN_CCCR) CAN operation according to ISO11898-1 enabled */ +#define MCAN_CCCR_CME_FD (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD operation enabled */ +#define MCAN_CCCR_CMR_Pos 10 +#define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos) /**< \brief (MCAN_CCCR) CAN Mode Request (read/write) */ +#define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos))) +#define MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10) /**< \brief (MCAN_CCCR) No mode change */ +#define MCAN_CCCR_CMR_FD (0x1u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation */ +#define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation with bit rate switching */ +#define MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10) /**< \brief (MCAN_CCCR) Request CAN operation according ISO11898-1 */ +#define MCAN_CCCR_FDO (0x1u << 12) /**< \brief (MCAN_CCCR) CAN FD Operation (read-only) */ +#define MCAN_CCCR_FDBS (0x1u << 13) /**< \brief (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) */ +#define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */ +/* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */ +#define MCAN_BTP_SJW_Pos 0 +#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */ +#define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos))) +#define MCAN_BTP_TSEG2_Pos 4 +#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */ +#define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos))) +#define MCAN_BTP_TSEG1_Pos 8 +#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */ +#define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos))) +#define MCAN_BTP_BRP_Pos 16 +#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */ +#define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos))) +/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */ +#define MCAN_TSCC_TSS_Pos 0 +#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos) /**< \brief (MCAN_TSCC) Timestamp Select */ +#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos))) +#define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value always 0x0000 */ +#define MCAN_TSCC_TSS_TCP_INC (0x1u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value incremented according to TCP */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0) /**< \brief (MCAN_TSCC) External timestamp counter value used */ +#define MCAN_TSCC_TCP_Pos 16 +#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos) /**< \brief (MCAN_TSCC) Timestamp Counter Prescaler */ +#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos))) +/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */ +#define MCAN_TSCV_TSC_Pos 0 +#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos) /**< \brief (MCAN_TSCV) Timestamp Counter (cleared on write) */ +#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos))) +/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */ +#define MCAN_TOCC_ETOC (0x1u << 0) /**< \brief (MCAN_TOCC) Enable Timeout Counter */ +#define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0) /**< \brief (MCAN_TOCC) Timeout Counter disabled. */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0) /**< \brief (MCAN_TOCC) Timeout Counter enabled. */ +#define MCAN_TOCC_TOS_Pos 1 +#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos) /**< \brief (MCAN_TOCC) Timeout Select */ +#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos))) +#define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1) /**< \brief (MCAN_TOCC) Continuous operation */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Tx Event FIFO */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */ +#define MCAN_TOCC_TOP_Pos 16 +#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos) /**< \brief (MCAN_TOCC) Timeout Period */ +#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos))) +/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */ +#define MCAN_TOCV_TOC_Pos 0 +#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos) /**< \brief (MCAN_TOCV) Timeout Counter (cleared on write) */ +#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos))) +/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */ +#define MCAN_ECR_TEC_Pos 0 +#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos) /**< \brief (MCAN_ECR) Transmit Error Counter */ +#define MCAN_ECR_REC_Pos 8 +#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos) /**< \brief (MCAN_ECR) Receive Error Counter */ +#define MCAN_ECR_RP (0x1u << 15) /**< \brief (MCAN_ECR) Receive Error Passive */ +#define MCAN_ECR_CEL_Pos 16 +#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos) /**< \brief (MCAN_ECR) CAN Error Logging (cleared on read) */ +/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */ +#define MCAN_PSR_LEC_Pos 0 +#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos) /**< \brief (MCAN_PSR) Last Error Code (set to 111 on read) */ +#define MCAN_PSR_LEC_NO_ERROR (0x0u << 0) /**< \brief (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */ +#define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0) /**< \brief (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. */ +#define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0) /**< \brief (MCAN_PSR) A fixed format part of a received frame has the wrong format. */ +#define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0) /**< \brief (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */ +#define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */ +#define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */ +#define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0) /**< \brief (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. */ +#define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0) /**< \brief (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */ +#define MCAN_PSR_ACT_Pos 3 +#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos) /**< \brief (MCAN_PSR) Activity */ +#define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3) /**< \brief (MCAN_PSR) Node is synchronizing on CAN communication */ +#define MCAN_PSR_ACT_IDLE (0x1u << 3) /**< \brief (MCAN_PSR) Node is neither receiver nor transmitter */ +#define MCAN_PSR_ACT_RECEIVER (0x2u << 3) /**< \brief (MCAN_PSR) Node is operating as receiver */ +#define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3) /**< \brief (MCAN_PSR) Node is operating as transmitter */ +#define MCAN_PSR_EP (0x1u << 5) /**< \brief (MCAN_PSR) Error Passive */ +#define MCAN_PSR_EW (0x1u << 6) /**< \brief (MCAN_PSR) Warning Status */ +#define MCAN_PSR_BO (0x1u << 7) /**< \brief (MCAN_PSR) Bus_Off Status */ +#define MCAN_PSR_FLEC_Pos 8 +#define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos) /**< \brief (MCAN_PSR) Fast Last Error Code (set to 111 on read) */ +#define MCAN_PSR_RESI (0x1u << 11) /**< \brief (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_RBRS (0x1u << 12) /**< \brief (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_REDL (0x1u << 13) /**< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) */ +/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */ +#define MCAN_IR_RF0N (0x1u << 0) /**< \brief (MCAN_IR) Receive FIFO 0 New Message */ +#define MCAN_IR_RF0W (0x1u << 1) /**< \brief (MCAN_IR) Receive FIFO 0 Watermark Reached */ +#define MCAN_IR_RF0F (0x1u << 2) /**< \brief (MCAN_IR) Receive FIFO 0 Full */ +#define MCAN_IR_RF0L (0x1u << 3) /**< \brief (MCAN_IR) Receive FIFO 0 Message Lost */ +#define MCAN_IR_RF1N (0x1u << 4) /**< \brief (MCAN_IR) Receive FIFO 1 New Message */ +#define MCAN_IR_RF1W (0x1u << 5) /**< \brief (MCAN_IR) Receive FIFO 1 Watermark Reached */ +#define MCAN_IR_RF1F (0x1u << 6) /**< \brief (MCAN_IR) Receive FIFO 1 Full */ +#define MCAN_IR_RF1L (0x1u << 7) /**< \brief (MCAN_IR) Receive FIFO 1 Message Lost */ +#define MCAN_IR_HPM (0x1u << 8) /**< \brief (MCAN_IR) High Priority Message */ +#define MCAN_IR_TC (0x1u << 9) /**< \brief (MCAN_IR) Transmission Completed */ +#define MCAN_IR_TCF (0x1u << 10) /**< \brief (MCAN_IR) Transmission Cancellation Finished */ +#define MCAN_IR_TFE (0x1u << 11) /**< \brief (MCAN_IR) Tx FIFO Empty */ +#define MCAN_IR_TEFN (0x1u << 12) /**< \brief (MCAN_IR) Tx Event FIFO New Entry */ +#define MCAN_IR_TEFW (0x1u << 13) /**< \brief (MCAN_IR) Tx Event FIFO Watermark Reached */ +#define MCAN_IR_TEFF (0x1u << 14) /**< \brief (MCAN_IR) Tx Event FIFO Full */ +#define MCAN_IR_TEFL (0x1u << 15) /**< \brief (MCAN_IR) Tx Event FIFO Element Lost */ +#define MCAN_IR_TSW (0x1u << 16) /**< \brief (MCAN_IR) Timestamp Wraparound */ +#define MCAN_IR_MRAF (0x1u << 17) /**< \brief (MCAN_IR) Message RAM Access Failure */ +#define MCAN_IR_TOO (0x1u << 18) /**< \brief (MCAN_IR) Timeout Occurred */ +#define MCAN_IR_DRX (0x1u << 19) /**< \brief (MCAN_IR) Message stored to Dedicated Receive Buffer */ +#define MCAN_IR_ELO (0x1u << 22) /**< \brief (MCAN_IR) Error Logging Overflow */ +#define MCAN_IR_EP (0x1u << 23) /**< \brief (MCAN_IR) Error Passive */ +#define MCAN_IR_EW (0x1u << 24) /**< \brief (MCAN_IR) Warning Status */ +#define MCAN_IR_BO (0x1u << 25) /**< \brief (MCAN_IR) Bus_Off Status */ +#define MCAN_IR_WDI (0x1u << 26) /**< \brief (MCAN_IR) Watchdog Interrupt */ +#define MCAN_IR_CRCE (0x1u << 27) /**< \brief (MCAN_IR) CRC Error */ +#define MCAN_IR_BE (0x1u << 28) /**< \brief (MCAN_IR) Bit Error */ +#define MCAN_IR_ACKE (0x1u << 29) /**< \brief (MCAN_IR) Acknowledge Error */ +#define MCAN_IR_FOE (0x1u << 30) /**< \brief (MCAN_IR) Format Error */ +#define MCAN_IR_STE (0x1u << 31) /**< \brief (MCAN_IR) Stuff Error */ +/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */ +#define MCAN_IE_RF0NE (0x1u << 0) /**< \brief (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable */ +#define MCAN_IE_RF0WE (0x1u << 1) /**< \brief (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF0FE (0x1u << 2) /**< \brief (MCAN_IE) Receive FIFO 0 Full Interrupt Enable */ +#define MCAN_IE_RF0LE (0x1u << 3) /**< \brief (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable */ +#define MCAN_IE_RF1NE (0x1u << 4) /**< \brief (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable */ +#define MCAN_IE_RF1WE (0x1u << 5) /**< \brief (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF1FE (0x1u << 6) /**< \brief (MCAN_IE) Receive FIFO 1 Full Interrupt Enable */ +#define MCAN_IE_RF1LE (0x1u << 7) /**< \brief (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable */ +#define MCAN_IE_HPME (0x1u << 8) /**< \brief (MCAN_IE) High Priority Message Interrupt Enable */ +#define MCAN_IE_TCE (0x1u << 9) /**< \brief (MCAN_IE) Transmission Completed Interrupt Enable */ +#define MCAN_IE_TCFE (0x1u << 10) /**< \brief (MCAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define MCAN_IE_TFEE (0x1u << 11) /**< \brief (MCAN_IE) Tx FIFO Empty Interrupt Enable */ +#define MCAN_IE_TEFNE (0x1u << 12) /**< \brief (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define MCAN_IE_TEFWE (0x1u << 13) /**< \brief (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define MCAN_IE_TEFFE (0x1u << 14) /**< \brief (MCAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define MCAN_IE_TEFLE (0x1u << 15) /**< \brief (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable */ +#define MCAN_IE_TSWE (0x1u << 16) /**< \brief (MCAN_IE) Timestamp Wraparound Interrupt Enable */ +#define MCAN_IE_MRAFE (0x1u << 17) /**< \brief (MCAN_IE) Message RAM Access Failure Interrupt Enable */ +#define MCAN_IE_TOOE (0x1u << 18) /**< \brief (MCAN_IE) Timeout Occurred Interrupt Enable */ +#define MCAN_IE_DRXE (0x1u << 19) /**< \brief (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable */ +#define MCAN_IE_ELOE (0x1u << 22) /**< \brief (MCAN_IE) Error Logging Overflow Interrupt Enable */ +#define MCAN_IE_EPE (0x1u << 23) /**< \brief (MCAN_IE) Error Passive Interrupt Enable */ +#define MCAN_IE_EWE (0x1u << 24) /**< \brief (MCAN_IE) Warning Status Interrupt Enable */ +#define MCAN_IE_BOE (0x1u << 25) /**< \brief (MCAN_IE) Bus_Off Status Interrupt Enable */ +#define MCAN_IE_WDIE (0x1u << 26) /**< \brief (MCAN_IE) Watchdog Interrupt Enable */ +#define MCAN_IE_CRCEE (0x1u << 27) /**< \brief (MCAN_IE) CRC Error Interrupt Enable */ +#define MCAN_IE_BEE (0x1u << 28) /**< \brief (MCAN_IE) Bit Error Interrupt Enable */ +#define MCAN_IE_ACKEE (0x1u << 29) /**< \brief (MCAN_IE) Acknowledge Error Interrupt Enable */ +#define MCAN_IE_FOEE (0x1u << 30) /**< \brief (MCAN_IE) Format Error Interrupt Enable */ +#define MCAN_IE_STEE (0x1u << 31) /**< \brief (MCAN_IE) Stuff Error Interrupt Enable */ +/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */ +#define MCAN_ILS_RF0NL (0x1u << 0) /**< \brief (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line */ +#define MCAN_ILS_RF0WL (0x1u << 1) /**< \brief (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF0FL (0x1u << 2) /**< \brief (MCAN_ILS) Receive FIFO 0 Full Interrupt Line */ +#define MCAN_ILS_RF0LL (0x1u << 3) /**< \brief (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line */ +#define MCAN_ILS_RF1NL (0x1u << 4) /**< \brief (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line */ +#define MCAN_ILS_RF1WL (0x1u << 5) /**< \brief (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF1FL (0x1u << 6) /**< \brief (MCAN_ILS) Receive FIFO 1 Full Interrupt Line */ +#define MCAN_ILS_RF1LL (0x1u << 7) /**< \brief (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line */ +#define MCAN_ILS_HPML (0x1u << 8) /**< \brief (MCAN_ILS) High Priority Message Interrupt Line */ +#define MCAN_ILS_TCL (0x1u << 9) /**< \brief (MCAN_ILS) Transmission Completed Interrupt Line */ +#define MCAN_ILS_TCFL (0x1u << 10) /**< \brief (MCAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define MCAN_ILS_TFEL (0x1u << 11) /**< \brief (MCAN_ILS) Tx FIFO Empty Interrupt Line */ +#define MCAN_ILS_TEFNL (0x1u << 12) /**< \brief (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define MCAN_ILS_TEFWL (0x1u << 13) /**< \brief (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define MCAN_ILS_TEFFL (0x1u << 14) /**< \brief (MCAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define MCAN_ILS_TEFLL (0x1u << 15) /**< \brief (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line */ +#define MCAN_ILS_TSWL (0x1u << 16) /**< \brief (MCAN_ILS) Timestamp Wraparound Interrupt Line */ +#define MCAN_ILS_MRAFL (0x1u << 17) /**< \brief (MCAN_ILS) Message RAM Access Failure Interrupt Line */ +#define MCAN_ILS_TOOL (0x1u << 18) /**< \brief (MCAN_ILS) Timeout Occurred Interrupt Line */ +#define MCAN_ILS_DRXL (0x1u << 19) /**< \brief (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line */ +#define MCAN_ILS_ELOL (0x1u << 22) /**< \brief (MCAN_ILS) Error Logging Overflow Interrupt Line */ +#define MCAN_ILS_EPL (0x1u << 23) /**< \brief (MCAN_ILS) Error Passive Interrupt Line */ +#define MCAN_ILS_EWL (0x1u << 24) /**< \brief (MCAN_ILS) Warning Status Interrupt Line */ +#define MCAN_ILS_BOL (0x1u << 25) /**< \brief (MCAN_ILS) Bus_Off Status Interrupt Line */ +#define MCAN_ILS_WDIL (0x1u << 26) /**< \brief (MCAN_ILS) Watchdog Interrupt Line */ +#define MCAN_ILS_CRCEL (0x1u << 27) /**< \brief (MCAN_ILS) CRC Error Interrupt Line */ +#define MCAN_ILS_BEL (0x1u << 28) /**< \brief (MCAN_ILS) Bit Error Interrupt Line */ +#define MCAN_ILS_ACKEL (0x1u << 29) /**< \brief (MCAN_ILS) Acknowledge Error Interrupt Line */ +#define MCAN_ILS_FOEL (0x1u << 30) /**< \brief (MCAN_ILS) Format Error Interrupt Line */ +#define MCAN_ILS_STEL (0x1u << 31) /**< \brief (MCAN_ILS) Stuff Error Interrupt Line */ +/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */ +#define MCAN_ILE_EINT0 (0x1u << 0) /**< \brief (MCAN_ILE) Enable Interrupt Line 0 */ +#define MCAN_ILE_EINT1 (0x1u << 1) /**< \brief (MCAN_ILE) Enable Interrupt Line 1 */ +/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */ +#define MCAN_GFC_RRFE (0x1u << 0) /**< \brief (MCAN_GFC) Reject Remote Frames Extended */ +#define MCAN_GFC_RRFE_FILTER (0x0u << 0) /**< \brief (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_REJECT (0x1u << 0) /**< \brief (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFS (0x1u << 1) /**< \brief (MCAN_GFC) Reject Remote Frames Standard */ +#define MCAN_GFC_RRFS_FILTER (0x0u << 1) /**< \brief (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_REJECT (0x1u << 1) /**< \brief (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_ANFE_Pos 2 +#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Extended */ +#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos))) +#define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +#define MCAN_GFC_ANFS_Pos 4 +#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Standard */ +#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos))) +#define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */ +#define MCAN_SIDFC_FLSSA_Pos 2 +#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos) /**< \brief (MCAN_SIDFC) Filter List Standard Start Address */ +#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos))) +#define MCAN_SIDFC_LSS_Pos 16 +#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos) /**< \brief (MCAN_SIDFC) List Size Standard */ +#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos))) +/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */ +#define MCAN_XIDFC_FLESA_Pos 2 +#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos) /**< \brief (MCAN_XIDFC) Filter List Extended Start Address */ +#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos))) +#define MCAN_XIDFC_LSE_Pos 16 +#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos) /**< \brief (MCAN_XIDFC) List Size Extended */ +#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos))) +/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */ +#define MCAN_XIDAM_EIDM_Pos 0 +#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos) /**< \brief (MCAN_XIDAM) Extended ID Mask */ +#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos))) +/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */ +#define MCAN_HPMS_BIDX_Pos 0 +#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos) /**< \brief (MCAN_HPMS) Buffer Index */ +#define MCAN_HPMS_MSI_Pos 6 +#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos) /**< \brief (MCAN_HPMS) Message Storage Indicator */ +#define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6) /**< \brief (MCAN_HPMS) No FIFO selected. */ +#define MCAN_HPMS_MSI_LOST (0x1u << 6) /**< \brief (MCAN_HPMS) FIFO message. */ +#define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 0. */ +#define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 1. */ +#define MCAN_HPMS_FIDX_Pos 8 +#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos) /**< \brief (MCAN_HPMS) Filter Index */ +#define MCAN_HPMS_FLST (0x1u << 15) /**< \brief (MCAN_HPMS) Filter List */ +/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */ +#define MCAN_NDAT1_ND0 (0x1u << 0) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND1 (0x1u << 1) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND2 (0x1u << 2) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND3 (0x1u << 3) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND4 (0x1u << 4) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND5 (0x1u << 5) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND6 (0x1u << 6) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND7 (0x1u << 7) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND8 (0x1u << 8) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND9 (0x1u << 9) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND10 (0x1u << 10) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND11 (0x1u << 11) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND12 (0x1u << 12) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND13 (0x1u << 13) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND14 (0x1u << 14) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND15 (0x1u << 15) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND16 (0x1u << 16) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND17 (0x1u << 17) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND18 (0x1u << 18) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND19 (0x1u << 19) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND20 (0x1u << 20) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND21 (0x1u << 21) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND22 (0x1u << 22) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND23 (0x1u << 23) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND24 (0x1u << 24) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND25 (0x1u << 25) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND26 (0x1u << 26) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND27 (0x1u << 27) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND28 (0x1u << 28) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND29 (0x1u << 29) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND30 (0x1u << 30) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND31 (0x1u << 31) /**< \brief (MCAN_NDAT1) New Data */ +/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */ +#define MCAN_NDAT2_ND32 (0x1u << 0) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND33 (0x1u << 1) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND34 (0x1u << 2) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND35 (0x1u << 3) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND36 (0x1u << 4) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND37 (0x1u << 5) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND38 (0x1u << 6) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND39 (0x1u << 7) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND40 (0x1u << 8) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND41 (0x1u << 9) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND42 (0x1u << 10) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND43 (0x1u << 11) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND44 (0x1u << 12) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND45 (0x1u << 13) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND46 (0x1u << 14) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND47 (0x1u << 15) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND48 (0x1u << 16) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND49 (0x1u << 17) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND50 (0x1u << 18) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND51 (0x1u << 19) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND52 (0x1u << 20) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND53 (0x1u << 21) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND54 (0x1u << 22) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND55 (0x1u << 23) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND56 (0x1u << 24) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND57 (0x1u << 25) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND58 (0x1u << 26) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND59 (0x1u << 27) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND60 (0x1u << 28) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND61 (0x1u << 29) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND62 (0x1u << 30) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND63 (0x1u << 31) /**< \brief (MCAN_NDAT2) New Data */ +/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */ +#define MCAN_RXF0C_F0SA_Pos 2 +#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos))) +#define MCAN_RXF0C_F0S_Pos 16 +#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos))) +#define MCAN_RXF0C_F0WM_Pos 24 +#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Watermark */ +#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos))) +#define MCAN_RXF0C_F0OM (0x1u << 31) /**< \brief (MCAN_RXF0C) FIFO 0 Operation Mode */ +/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */ +#define MCAN_RXF0S_F0FL_Pos 0 +#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_F0GI_Pos 8 +#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Get Index */ +#define MCAN_RXF0S_F0PI_Pos 16 +#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Put Index */ +#define MCAN_RXF0S_F0F (0x1u << 24) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_RF0L (0x1u << 25) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Message Lost */ +/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */ +#define MCAN_RXF0A_F0AI_Pos 0 +#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos) /**< \brief (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index */ +#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos))) +/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */ +#define MCAN_RXBC_RBSA_Pos 2 +#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos) /**< \brief (MCAN_RXBC) Receive Buffer Start Address */ +#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos))) +/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */ +#define MCAN_RXF1C_F1SA_Pos 2 +#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos))) +#define MCAN_RXF1C_F1S_Pos 16 +#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos))) +#define MCAN_RXF1C_F1WM_Pos 24 +#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Watermark */ +#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos))) +#define MCAN_RXF1C_F1OM (0x1u << 31) /**< \brief (MCAN_RXF1C) FIFO 1 Operation Mode */ +/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */ +#define MCAN_RXF1S_F1FL_Pos 0 +#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_F1GI_Pos 8 +#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Get Index */ +#define MCAN_RXF1S_F1PI_Pos 16 +#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Put Index */ +#define MCAN_RXF1S_F1F (0x1u << 24) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_RF1L (0x1u << 25) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Message Lost */ +#define MCAN_RXF1S_DMS_Pos 30 +#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos) /**< \brief (MCAN_RXF1S) Debug Message Status */ +#define MCAN_RXF1S_DMS_IDLE (0x0u << 30) /**< \brief (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */ +#define MCAN_RXF1S_DMS_MSG_A (0x1u << 30) /**< \brief (MCAN_RXF1S) Debug message A received. */ +#define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B received. */ +#define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */ +/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */ +#define MCAN_RXF1A_F1AI_Pos 0 +#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos) /**< \brief (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index */ +#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos))) +/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */ +#define MCAN_RXESC_F0DS_Pos 0 +#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 0 Data Field Size */ +#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos))) +#define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0) /**< \brief (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_F1DS_Pos 4 +#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 1 Data Field Size */ +#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos))) +#define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4) /**< \brief (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_RBDS_Pos 8 +#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos) /**< \brief (MCAN_RXESC) Receive Buffer Data Field Size */ +#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos))) +#define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8) /**< \brief (MCAN_RXESC) 64-byte data field */ +/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */ +#define MCAN_TXBC_TBSA_Pos 2 +#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos) /**< \brief (MCAN_TXBC) Tx Buffers Start Address */ +#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos))) +#define MCAN_TXBC_NDTB_Pos 16 +#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos) /**< \brief (MCAN_TXBC) Number of Dedicated Transmit Buffers */ +#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos))) +#define MCAN_TXBC_TFQS_Pos 24 +#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos) /**< \brief (MCAN_TXBC) Transmit FIFO/Queue Size */ +#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos))) +#define MCAN_TXBC_TFQM (0x1u << 30) /**< \brief (MCAN_TXBC) Tx FIFO/Queue Mode */ +/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */ +#define MCAN_TXFQS_TFFL_Pos 0 +#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Free Level */ +#define MCAN_TXFQS_TFGI_Pos 8 +#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Get Index */ +#define MCAN_TXFQS_TFQPI_Pos 16 +#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Put Index */ +#define MCAN_TXFQS_TFQF (0x1u << 21) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Full */ +/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */ +#define MCAN_TXESC_TBDS_Pos 0 +#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos) /**< \brief (MCAN_TXESC) Tx Buffer Data Field Size */ +#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos))) +#define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0) /**< \brief (MCAN_TXESC) 8-byte data field */ +#define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0) /**< \brief (MCAN_TXESC) 12-byte data field */ +#define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0) /**< \brief (MCAN_TXESC) 16-byte data field */ +#define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0) /**< \brief (MCAN_TXESC) 20-byte data field */ +#define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0) /**< \brief (MCAN_TXESC) 24-byte data field */ +#define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0) /**< \brief (MCAN_TXESC) 32-byte data field */ +#define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0) /**< \brief (MCAN_TXESC) 4- byte data field */ +#define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0) /**< \brief (MCAN_TXESC) 64-byte data field */ +/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */ +#define MCAN_TXBRP_TRP0 (0x1u << 0) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 0 */ +#define MCAN_TXBRP_TRP1 (0x1u << 1) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 1 */ +#define MCAN_TXBRP_TRP2 (0x1u << 2) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 2 */ +#define MCAN_TXBRP_TRP3 (0x1u << 3) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 3 */ +#define MCAN_TXBRP_TRP4 (0x1u << 4) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 4 */ +#define MCAN_TXBRP_TRP5 (0x1u << 5) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 5 */ +#define MCAN_TXBRP_TRP6 (0x1u << 6) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 6 */ +#define MCAN_TXBRP_TRP7 (0x1u << 7) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 7 */ +#define MCAN_TXBRP_TRP8 (0x1u << 8) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 8 */ +#define MCAN_TXBRP_TRP9 (0x1u << 9) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 9 */ +#define MCAN_TXBRP_TRP10 (0x1u << 10) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 10 */ +#define MCAN_TXBRP_TRP11 (0x1u << 11) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 11 */ +#define MCAN_TXBRP_TRP12 (0x1u << 12) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 12 */ +#define MCAN_TXBRP_TRP13 (0x1u << 13) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 13 */ +#define MCAN_TXBRP_TRP14 (0x1u << 14) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 14 */ +#define MCAN_TXBRP_TRP15 (0x1u << 15) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 15 */ +#define MCAN_TXBRP_TRP16 (0x1u << 16) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 16 */ +#define MCAN_TXBRP_TRP17 (0x1u << 17) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 17 */ +#define MCAN_TXBRP_TRP18 (0x1u << 18) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 18 */ +#define MCAN_TXBRP_TRP19 (0x1u << 19) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 19 */ +#define MCAN_TXBRP_TRP20 (0x1u << 20) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 20 */ +#define MCAN_TXBRP_TRP21 (0x1u << 21) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 21 */ +#define MCAN_TXBRP_TRP22 (0x1u << 22) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 22 */ +#define MCAN_TXBRP_TRP23 (0x1u << 23) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 23 */ +#define MCAN_TXBRP_TRP24 (0x1u << 24) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 24 */ +#define MCAN_TXBRP_TRP25 (0x1u << 25) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 25 */ +#define MCAN_TXBRP_TRP26 (0x1u << 26) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 26 */ +#define MCAN_TXBRP_TRP27 (0x1u << 27) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 27 */ +#define MCAN_TXBRP_TRP28 (0x1u << 28) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 28 */ +#define MCAN_TXBRP_TRP29 (0x1u << 29) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 29 */ +#define MCAN_TXBRP_TRP30 (0x1u << 30) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 30 */ +#define MCAN_TXBRP_TRP31 (0x1u << 31) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 31 */ +/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */ +#define MCAN_TXBAR_AR0 (0x1u << 0) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 0 */ +#define MCAN_TXBAR_AR1 (0x1u << 1) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 1 */ +#define MCAN_TXBAR_AR2 (0x1u << 2) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 2 */ +#define MCAN_TXBAR_AR3 (0x1u << 3) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 3 */ +#define MCAN_TXBAR_AR4 (0x1u << 4) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 4 */ +#define MCAN_TXBAR_AR5 (0x1u << 5) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 5 */ +#define MCAN_TXBAR_AR6 (0x1u << 6) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 6 */ +#define MCAN_TXBAR_AR7 (0x1u << 7) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 7 */ +#define MCAN_TXBAR_AR8 (0x1u << 8) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 8 */ +#define MCAN_TXBAR_AR9 (0x1u << 9) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 9 */ +#define MCAN_TXBAR_AR10 (0x1u << 10) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 10 */ +#define MCAN_TXBAR_AR11 (0x1u << 11) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 11 */ +#define MCAN_TXBAR_AR12 (0x1u << 12) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 12 */ +#define MCAN_TXBAR_AR13 (0x1u << 13) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 13 */ +#define MCAN_TXBAR_AR14 (0x1u << 14) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 14 */ +#define MCAN_TXBAR_AR15 (0x1u << 15) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 15 */ +#define MCAN_TXBAR_AR16 (0x1u << 16) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 16 */ +#define MCAN_TXBAR_AR17 (0x1u << 17) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 17 */ +#define MCAN_TXBAR_AR18 (0x1u << 18) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 18 */ +#define MCAN_TXBAR_AR19 (0x1u << 19) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 19 */ +#define MCAN_TXBAR_AR20 (0x1u << 20) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 20 */ +#define MCAN_TXBAR_AR21 (0x1u << 21) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 21 */ +#define MCAN_TXBAR_AR22 (0x1u << 22) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 22 */ +#define MCAN_TXBAR_AR23 (0x1u << 23) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 23 */ +#define MCAN_TXBAR_AR24 (0x1u << 24) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 24 */ +#define MCAN_TXBAR_AR25 (0x1u << 25) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 25 */ +#define MCAN_TXBAR_AR26 (0x1u << 26) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 26 */ +#define MCAN_TXBAR_AR27 (0x1u << 27) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 27 */ +#define MCAN_TXBAR_AR28 (0x1u << 28) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 28 */ +#define MCAN_TXBAR_AR29 (0x1u << 29) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 29 */ +#define MCAN_TXBAR_AR30 (0x1u << 30) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 30 */ +#define MCAN_TXBAR_AR31 (0x1u << 31) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */ +#define MCAN_TXBCR_CR0 (0x1u << 0) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 */ +#define MCAN_TXBCR_CR1 (0x1u << 1) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 */ +#define MCAN_TXBCR_CR2 (0x1u << 2) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 */ +#define MCAN_TXBCR_CR3 (0x1u << 3) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 */ +#define MCAN_TXBCR_CR4 (0x1u << 4) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 */ +#define MCAN_TXBCR_CR5 (0x1u << 5) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 */ +#define MCAN_TXBCR_CR6 (0x1u << 6) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 */ +#define MCAN_TXBCR_CR7 (0x1u << 7) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 */ +#define MCAN_TXBCR_CR8 (0x1u << 8) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 */ +#define MCAN_TXBCR_CR9 (0x1u << 9) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 */ +#define MCAN_TXBCR_CR10 (0x1u << 10) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 */ +#define MCAN_TXBCR_CR11 (0x1u << 11) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 */ +#define MCAN_TXBCR_CR12 (0x1u << 12) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 */ +#define MCAN_TXBCR_CR13 (0x1u << 13) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 */ +#define MCAN_TXBCR_CR14 (0x1u << 14) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 */ +#define MCAN_TXBCR_CR15 (0x1u << 15) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 */ +#define MCAN_TXBCR_CR16 (0x1u << 16) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 */ +#define MCAN_TXBCR_CR17 (0x1u << 17) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 */ +#define MCAN_TXBCR_CR18 (0x1u << 18) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 */ +#define MCAN_TXBCR_CR19 (0x1u << 19) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 */ +#define MCAN_TXBCR_CR20 (0x1u << 20) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 */ +#define MCAN_TXBCR_CR21 (0x1u << 21) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 */ +#define MCAN_TXBCR_CR22 (0x1u << 22) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 */ +#define MCAN_TXBCR_CR23 (0x1u << 23) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 */ +#define MCAN_TXBCR_CR24 (0x1u << 24) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 */ +#define MCAN_TXBCR_CR25 (0x1u << 25) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 */ +#define MCAN_TXBCR_CR26 (0x1u << 26) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 */ +#define MCAN_TXBCR_CR27 (0x1u << 27) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 */ +#define MCAN_TXBCR_CR28 (0x1u << 28) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 */ +#define MCAN_TXBCR_CR29 (0x1u << 29) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 */ +#define MCAN_TXBCR_CR30 (0x1u << 30) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 */ +#define MCAN_TXBCR_CR31 (0x1u << 31) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */ +#define MCAN_TXBTO_TO0 (0x1u << 0) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 0 */ +#define MCAN_TXBTO_TO1 (0x1u << 1) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 1 */ +#define MCAN_TXBTO_TO2 (0x1u << 2) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 2 */ +#define MCAN_TXBTO_TO3 (0x1u << 3) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 3 */ +#define MCAN_TXBTO_TO4 (0x1u << 4) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 4 */ +#define MCAN_TXBTO_TO5 (0x1u << 5) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 5 */ +#define MCAN_TXBTO_TO6 (0x1u << 6) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 6 */ +#define MCAN_TXBTO_TO7 (0x1u << 7) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 7 */ +#define MCAN_TXBTO_TO8 (0x1u << 8) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 8 */ +#define MCAN_TXBTO_TO9 (0x1u << 9) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 9 */ +#define MCAN_TXBTO_TO10 (0x1u << 10) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 10 */ +#define MCAN_TXBTO_TO11 (0x1u << 11) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 11 */ +#define MCAN_TXBTO_TO12 (0x1u << 12) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 12 */ +#define MCAN_TXBTO_TO13 (0x1u << 13) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 13 */ +#define MCAN_TXBTO_TO14 (0x1u << 14) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 14 */ +#define MCAN_TXBTO_TO15 (0x1u << 15) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 15 */ +#define MCAN_TXBTO_TO16 (0x1u << 16) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 16 */ +#define MCAN_TXBTO_TO17 (0x1u << 17) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 17 */ +#define MCAN_TXBTO_TO18 (0x1u << 18) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 18 */ +#define MCAN_TXBTO_TO19 (0x1u << 19) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 19 */ +#define MCAN_TXBTO_TO20 (0x1u << 20) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 20 */ +#define MCAN_TXBTO_TO21 (0x1u << 21) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 21 */ +#define MCAN_TXBTO_TO22 (0x1u << 22) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 22 */ +#define MCAN_TXBTO_TO23 (0x1u << 23) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 23 */ +#define MCAN_TXBTO_TO24 (0x1u << 24) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 24 */ +#define MCAN_TXBTO_TO25 (0x1u << 25) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 25 */ +#define MCAN_TXBTO_TO26 (0x1u << 26) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 26 */ +#define MCAN_TXBTO_TO27 (0x1u << 27) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 27 */ +#define MCAN_TXBTO_TO28 (0x1u << 28) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 28 */ +#define MCAN_TXBTO_TO29 (0x1u << 29) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 29 */ +#define MCAN_TXBTO_TO30 (0x1u << 30) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 30 */ +#define MCAN_TXBTO_TO31 (0x1u << 31) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 31 */ +/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */ +#define MCAN_TXBCF_CF0 (0x1u << 0) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 */ +#define MCAN_TXBCF_CF1 (0x1u << 1) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 */ +#define MCAN_TXBCF_CF2 (0x1u << 2) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 */ +#define MCAN_TXBCF_CF3 (0x1u << 3) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 */ +#define MCAN_TXBCF_CF4 (0x1u << 4) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 */ +#define MCAN_TXBCF_CF5 (0x1u << 5) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 */ +#define MCAN_TXBCF_CF6 (0x1u << 6) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 */ +#define MCAN_TXBCF_CF7 (0x1u << 7) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 */ +#define MCAN_TXBCF_CF8 (0x1u << 8) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 */ +#define MCAN_TXBCF_CF9 (0x1u << 9) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 */ +#define MCAN_TXBCF_CF10 (0x1u << 10) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 */ +#define MCAN_TXBCF_CF11 (0x1u << 11) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 */ +#define MCAN_TXBCF_CF12 (0x1u << 12) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 */ +#define MCAN_TXBCF_CF13 (0x1u << 13) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 */ +#define MCAN_TXBCF_CF14 (0x1u << 14) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 */ +#define MCAN_TXBCF_CF15 (0x1u << 15) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 */ +#define MCAN_TXBCF_CF16 (0x1u << 16) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 */ +#define MCAN_TXBCF_CF17 (0x1u << 17) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 */ +#define MCAN_TXBCF_CF18 (0x1u << 18) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 */ +#define MCAN_TXBCF_CF19 (0x1u << 19) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 */ +#define MCAN_TXBCF_CF20 (0x1u << 20) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 */ +#define MCAN_TXBCF_CF21 (0x1u << 21) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 */ +#define MCAN_TXBCF_CF22 (0x1u << 22) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 */ +#define MCAN_TXBCF_CF23 (0x1u << 23) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 */ +#define MCAN_TXBCF_CF24 (0x1u << 24) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 */ +#define MCAN_TXBCF_CF25 (0x1u << 25) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 */ +#define MCAN_TXBCF_CF26 (0x1u << 26) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 */ +#define MCAN_TXBCF_CF27 (0x1u << 27) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 */ +#define MCAN_TXBCF_CF28 (0x1u << 28) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 */ +#define MCAN_TXBCF_CF29 (0x1u << 29) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 */ +#define MCAN_TXBCF_CF30 (0x1u << 30) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 */ +#define MCAN_TXBCF_CF31 (0x1u << 31) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 */ +/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */ +#define MCAN_TXBTIE_TIE0 (0x1u << 0) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 */ +#define MCAN_TXBTIE_TIE1 (0x1u << 1) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 */ +#define MCAN_TXBTIE_TIE2 (0x1u << 2) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 */ +#define MCAN_TXBTIE_TIE3 (0x1u << 3) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 */ +#define MCAN_TXBTIE_TIE4 (0x1u << 4) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 */ +#define MCAN_TXBTIE_TIE5 (0x1u << 5) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 */ +#define MCAN_TXBTIE_TIE6 (0x1u << 6) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 */ +#define MCAN_TXBTIE_TIE7 (0x1u << 7) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 */ +#define MCAN_TXBTIE_TIE8 (0x1u << 8) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 */ +#define MCAN_TXBTIE_TIE9 (0x1u << 9) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 */ +#define MCAN_TXBTIE_TIE10 (0x1u << 10) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 */ +#define MCAN_TXBTIE_TIE11 (0x1u << 11) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 */ +#define MCAN_TXBTIE_TIE12 (0x1u << 12) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 */ +#define MCAN_TXBTIE_TIE13 (0x1u << 13) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 */ +#define MCAN_TXBTIE_TIE14 (0x1u << 14) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 */ +#define MCAN_TXBTIE_TIE15 (0x1u << 15) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 */ +#define MCAN_TXBTIE_TIE16 (0x1u << 16) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 */ +#define MCAN_TXBTIE_TIE17 (0x1u << 17) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 */ +#define MCAN_TXBTIE_TIE18 (0x1u << 18) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 */ +#define MCAN_TXBTIE_TIE19 (0x1u << 19) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 */ +#define MCAN_TXBTIE_TIE20 (0x1u << 20) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 */ +#define MCAN_TXBTIE_TIE21 (0x1u << 21) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 */ +#define MCAN_TXBTIE_TIE22 (0x1u << 22) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 */ +#define MCAN_TXBTIE_TIE23 (0x1u << 23) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 */ +#define MCAN_TXBTIE_TIE24 (0x1u << 24) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 */ +#define MCAN_TXBTIE_TIE25 (0x1u << 25) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 */ +#define MCAN_TXBTIE_TIE26 (0x1u << 26) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 */ +#define MCAN_TXBTIE_TIE27 (0x1u << 27) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 */ +#define MCAN_TXBTIE_TIE28 (0x1u << 28) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 */ +#define MCAN_TXBTIE_TIE29 (0x1u << 29) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 */ +#define MCAN_TXBTIE_TIE30 (0x1u << 30) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 */ +#define MCAN_TXBTIE_TIE31 (0x1u << 31) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 */ +/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */ +#define MCAN_TXBCIE_CFIE0 (0x1u << 0) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 */ +#define MCAN_TXBCIE_CFIE1 (0x1u << 1) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 */ +#define MCAN_TXBCIE_CFIE2 (0x1u << 2) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 */ +#define MCAN_TXBCIE_CFIE3 (0x1u << 3) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 */ +#define MCAN_TXBCIE_CFIE4 (0x1u << 4) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 */ +#define MCAN_TXBCIE_CFIE5 (0x1u << 5) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 */ +#define MCAN_TXBCIE_CFIE6 (0x1u << 6) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 */ +#define MCAN_TXBCIE_CFIE7 (0x1u << 7) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 */ +#define MCAN_TXBCIE_CFIE8 (0x1u << 8) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 */ +#define MCAN_TXBCIE_CFIE9 (0x1u << 9) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 */ +#define MCAN_TXBCIE_CFIE10 (0x1u << 10) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 */ +#define MCAN_TXBCIE_CFIE11 (0x1u << 11) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 */ +#define MCAN_TXBCIE_CFIE12 (0x1u << 12) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 */ +#define MCAN_TXBCIE_CFIE13 (0x1u << 13) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 */ +#define MCAN_TXBCIE_CFIE14 (0x1u << 14) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 */ +#define MCAN_TXBCIE_CFIE15 (0x1u << 15) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 */ +#define MCAN_TXBCIE_CFIE16 (0x1u << 16) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 */ +#define MCAN_TXBCIE_CFIE17 (0x1u << 17) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 */ +#define MCAN_TXBCIE_CFIE18 (0x1u << 18) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 */ +#define MCAN_TXBCIE_CFIE19 (0x1u << 19) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 */ +#define MCAN_TXBCIE_CFIE20 (0x1u << 20) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 */ +#define MCAN_TXBCIE_CFIE21 (0x1u << 21) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 */ +#define MCAN_TXBCIE_CFIE22 (0x1u << 22) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 */ +#define MCAN_TXBCIE_CFIE23 (0x1u << 23) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 */ +#define MCAN_TXBCIE_CFIE24 (0x1u << 24) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 */ +#define MCAN_TXBCIE_CFIE25 (0x1u << 25) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 */ +#define MCAN_TXBCIE_CFIE26 (0x1u << 26) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 */ +#define MCAN_TXBCIE_CFIE27 (0x1u << 27) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 */ +#define MCAN_TXBCIE_CFIE28 (0x1u << 28) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 */ +#define MCAN_TXBCIE_CFIE29 (0x1u << 29) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 */ +#define MCAN_TXBCIE_CFIE30 (0x1u << 30) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 */ +#define MCAN_TXBCIE_CFIE31 (0x1u << 31) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 */ +/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */ +#define MCAN_TXEFC_EFSA_Pos 2 +#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Start Address */ +#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos))) +#define MCAN_TXEFC_EFS_Pos 16 +#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Size */ +#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos))) +#define MCAN_TXEFC_EFWM_Pos 24 +#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Watermark */ +#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos))) +/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */ +#define MCAN_TXEFS_EFFL_Pos 0 +#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Fill Level */ +#define MCAN_TXEFS_EFGI_Pos 8 +#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Get Index */ +#define MCAN_TXEFS_EFPI_Pos 16 +#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Put Index */ +#define MCAN_TXEFS_EFF (0x1u << 24) /**< \brief (MCAN_TXEFS) Event FIFO Full */ +#define MCAN_TXEFS_TEFL (0x1u << 25) /**< \brief (MCAN_TXEFS) Tx Event FIFO Element Lost */ +/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */ +#define MCAN_TXEFA_EFAI_Pos 0 +#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos) /**< \brief (MCAN_TXEFA) Event FIFO Acknowledge Index */ +#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos))) + +/*@}*/ + + +#endif /* _SAME70_MCAN_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h new file mode 100644 index 0000000000..357ebaf4fd --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h @@ -0,0 +1,1711 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_PIO_COMPONENT_ +#define _SAME70_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + __I uint32_t Reserved3[1]; + __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + __I uint32_t Reserved4[1]; + __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + __I uint32_t Reserved6[2]; + __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + __I uint32_t Reserved7[1]; + __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + __I uint32_t Reserved8[1]; + __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + __I uint32_t Reserved9[1]; + __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + __I uint32_t Reserved10[1]; + __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + __I uint32_t Reserved11[1]; + __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved12[5]; + __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + __I uint32_t Reserved13[5]; + __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0118) I/O Drive Register */ + __I uint32_t Reserved14[13]; + __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x0150) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x0164) Parallel Capture Reception Holding Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filter Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-drive Enable */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-drive Disable */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-drive Status */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) IO Line Index */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +/* -------- PIO_DRIVER : (PIO Offset: 0x0118) I/O Drive Register -------- */ +#define PIO_DRIVER_LINE0 (0x1u << 0) /**< \brief (PIO_DRIVER) Drive of PIO Line 0 */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (0x1u << 0) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1 (0x1u << 1) /**< \brief (PIO_DRIVER) Drive of PIO Line 1 */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (0x0u << 1) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (0x1u << 1) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2 (0x1u << 2) /**< \brief (PIO_DRIVER) Drive of PIO Line 2 */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (0x1u << 2) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3 (0x1u << 3) /**< \brief (PIO_DRIVER) Drive of PIO Line 3 */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (0x0u << 3) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (0x1u << 3) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4 (0x1u << 4) /**< \brief (PIO_DRIVER) Drive of PIO Line 4 */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (0x1u << 4) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5 (0x1u << 5) /**< \brief (PIO_DRIVER) Drive of PIO Line 5 */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (0x0u << 5) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (0x1u << 5) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6 (0x1u << 6) /**< \brief (PIO_DRIVER) Drive of PIO Line 6 */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (0x1u << 6) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7 (0x1u << 7) /**< \brief (PIO_DRIVER) Drive of PIO Line 7 */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (0x0u << 7) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (0x1u << 7) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8 (0x1u << 8) /**< \brief (PIO_DRIVER) Drive of PIO Line 8 */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (0x1u << 8) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9 (0x1u << 9) /**< \brief (PIO_DRIVER) Drive of PIO Line 9 */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (0x0u << 9) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (0x1u << 9) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10 (0x1u << 10) /**< \brief (PIO_DRIVER) Drive of PIO Line 10 */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (0x1u << 10) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11 (0x1u << 11) /**< \brief (PIO_DRIVER) Drive of PIO Line 11 */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (0x0u << 11) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (0x1u << 11) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12 (0x1u << 12) /**< \brief (PIO_DRIVER) Drive of PIO Line 12 */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (0x1u << 12) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13 (0x1u << 13) /**< \brief (PIO_DRIVER) Drive of PIO Line 13 */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (0x0u << 13) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (0x1u << 13) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14 (0x1u << 14) /**< \brief (PIO_DRIVER) Drive of PIO Line 14 */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (0x1u << 14) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15 (0x1u << 15) /**< \brief (PIO_DRIVER) Drive of PIO Line 15 */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (0x0u << 15) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (0x1u << 15) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16 (0x1u << 16) /**< \brief (PIO_DRIVER) Drive of PIO Line 16 */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (0x1u << 16) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17 (0x1u << 17) /**< \brief (PIO_DRIVER) Drive of PIO Line 17 */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (0x0u << 17) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (0x1u << 17) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18 (0x1u << 18) /**< \brief (PIO_DRIVER) Drive of PIO Line 18 */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (0x1u << 18) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19 (0x1u << 19) /**< \brief (PIO_DRIVER) Drive of PIO Line 19 */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (0x0u << 19) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (0x1u << 19) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20 (0x1u << 20) /**< \brief (PIO_DRIVER) Drive of PIO Line 20 */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (0x1u << 20) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21 (0x1u << 21) /**< \brief (PIO_DRIVER) Drive of PIO Line 21 */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (0x0u << 21) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (0x1u << 21) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22 (0x1u << 22) /**< \brief (PIO_DRIVER) Drive of PIO Line 22 */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (0x1u << 22) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23 (0x1u << 23) /**< \brief (PIO_DRIVER) Drive of PIO Line 23 */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (0x0u << 23) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (0x1u << 23) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24 (0x1u << 24) /**< \brief (PIO_DRIVER) Drive of PIO Line 24 */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (0x1u << 24) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25 (0x1u << 25) /**< \brief (PIO_DRIVER) Drive of PIO Line 25 */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (0x0u << 25) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (0x1u << 25) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26 (0x1u << 26) /**< \brief (PIO_DRIVER) Drive of PIO Line 26 */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (0x1u << 26) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27 (0x1u << 27) /**< \brief (PIO_DRIVER) Drive of PIO Line 27 */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (0x0u << 27) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (0x1u << 27) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28 (0x1u << 28) /**< \brief (PIO_DRIVER) Drive of PIO Line 28 */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (0x1u << 28) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29 (0x1u << 29) /**< \brief (PIO_DRIVER) Drive of PIO Line 29 */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (0x0u << 29) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (0x1u << 29) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30 (0x1u << 30) /**< \brief (PIO_DRIVER) Drive of PIO Line 30 */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (0x1u << 30) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31 (0x1u << 31) /**< \brief (PIO_DRIVER) Drive of PIO Line 31 */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (0x0u << 31) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (0x1u << 31) /**< \brief (PIO_DRIVER) Highest drive */ +/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE_Pos 4 +#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos))) +#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error */ +/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos 0 +#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data */ + +/*@}*/ + + +#endif /* _SAME70_PIO_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h new file mode 100644 index 0000000000..63d9749f1f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h @@ -0,0 +1,723 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_PMC_COMPONENT_ +#define _SAME70_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t PMC_PCK[7]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + __I uint32_t Reserved5[1]; + __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + __I uint32_t Reserved6[26]; + __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved7[5]; + __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 */ + __I uint32_t Reserved8[3]; + __IO uint32_t PMC_PMMR; /**< \brief (Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register */ + __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_USBCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB FS Clock */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */ +#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */ +#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */ +#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_USBCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB FS Clock */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */ +#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */ +#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */ +#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_USBCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB FS Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */ +#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */ +#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */ +#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command (Write-only) */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) 4/8/12 MHz On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) 4/8/12 MHz RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos))) +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Clock Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */ +#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ +#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front End Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos))) +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos))) +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_MDIV_Pos 8 +#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */ +#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos))) +#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK[7] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[7]) Master Clock Source Selection */ +#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos))) +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[7]) Slow Clock is selected */ +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[7]) Main Clock is selected */ +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[7]) PLLA Clock is selected */ +#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[7]) Divided UPLL Clock is selected */ +#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[7]) Master Clock is selected */ +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[7]) Programmable Clock Prescaler */ +#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) 3 to 20 MHz Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */ +#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */ +#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */ +#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) 4/8/12 MHz RC Oscillator Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) 3 to 20 MHz Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */ +#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */ +#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */ +#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) 4/8/12 MHz RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) 3 to 20 MHz Crystal Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Source Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Clock Source Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) 4/8/12 MHz RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) 3 to 20 MHz Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask */ +#define PMC_IMR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask */ +#define PMC_IMR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask */ +#define PMC_IMR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) 4/8/12 MHz RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */ +#define PMC_FSMR_FLPM_Pos 21 +#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */ +#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos))) +#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 1 */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 2 */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 3 */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 4 */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 5 */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 6 */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 7 */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 8 */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 9 */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 10 */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 11 */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 12 */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 13 */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 14 */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 15 */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos 0 +#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ +#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos))) +#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */ +#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos 0 +#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) +#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL8_Pos 8 +#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) +#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL12_Pos 16 +#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */ +#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) +#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */ +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */ +#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */ +#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */ +#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */ +#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */ +#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */ +#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */ +#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */ +#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */ +#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */ +#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */ +#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */ +#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */ +#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */ +#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */ +#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */ +#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */ +#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */ +#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */ +#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */ +#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */ +#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */ +#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */ +#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */ +#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */ +#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */ +#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */ +#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */ +#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */ +/* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */ +#define PMC_PMMR_PLLA_MMAX_Pos 0 +#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) /**< \brief (PMC_PMMR) PLLA Maximum Allowed Multiplier Value */ +#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos))) +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */ +#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */ +#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */ +#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */ +#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */ +#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */ +#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */ +#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */ +#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */ +#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */ +#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */ +#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */ +#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */ +#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */ +#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */ +#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */ +#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */ +#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */ +#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */ +#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */ +#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */ +#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */ +#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */ +#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */ +#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */ +#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */ +#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status */ +#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status */ +#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status */ +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */ +#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */ + +/*@}*/ + + +#endif /* _SAME70_PMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_pwm.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_pwm.h new file mode 100644 index 0000000000..46ad816164 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_pwm.h @@ -0,0 +1,644 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_PWM_COMPONENT_ +#define _SAME70_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief PwmCmp hardware registers */ +typedef struct { + __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ +} PwmCmp; +/** \brief Pwm hardware registers */ +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 4 +typedef struct { + __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */ + __I uint32_t Reserved5[8]; + __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */ + __I uint32_t Reserved6[17]; + PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ + __I uint32_t Reserved7[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ + __I uint32_t Reserved8[96]; + __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint32_t Reserved9[7]; + __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint32_t Reserved10[2]; + __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint32_t Reserved11[3]; + __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint32_t Reserved12[2]; + __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint32_t Reserved13[3]; + __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Controller Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Controller Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */ +#define PWM_DMAR_DMADUTY_Pos 0 +#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */ +#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */ +/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */ +#define PWM_SSPR_SPRD_Pos 0 +#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */ +#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) +#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */ +/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */ +#define PWM_SSPUP_SPRDUP_Pos 0 +#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */ +#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */ +#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */ +#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */ +#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */ +#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */ +#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */ +#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */ +#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */ +#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */ +#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */ +#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */ +#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */ +#define PWM_ETRG1_MAXCNT_Pos 0 +#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */ +#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos))) +#define PWM_ETRG1_TRGMODE_Pos 24 +#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */ +#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos))) +#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */ +#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */ +#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */ +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#define PWM_LEBR1_LEBDELAY_Pos 0 +#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos))) +#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */ +#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */ +#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */ +#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */ +#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */ +#define PWM_ETRG2_MAXCNT_Pos 0 +#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */ +#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos))) +#define PWM_ETRG2_TRGMODE_Pos 24 +#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */ +#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos))) +#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */ +#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */ +#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */ +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#define PWM_LEBR2_LEBDELAY_Pos 0 +#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos))) +#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */ +#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */ +#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */ +#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */ +#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */ + +/*@}*/ + + +#endif /* _SAME70_PWM_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_qspi.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_qspi.h new file mode 100644 index 0000000000..79711335d6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_qspi.h @@ -0,0 +1,216 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_QSPI_COMPONENT_ +#define _SAME70_QSPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_QSPI Quad Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Qspi hardware registers */ +typedef struct { + __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */ + __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */ + __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */ + __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */ + __I uint32_t Reserved3[39]; + __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */ +} Qspi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */ +#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */ +#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */ +#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */ +#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */ +/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */ +#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */ +#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */ +#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */ +#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_CSMODE_Pos 4 +#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */ +#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos))) +#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_NBBITS_Pos 8 +#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */ +#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos))) +#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_DLYBCT_Pos 16 +#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */ +#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos))) +#define QSPI_MR_DLYCS_Pos 24 +#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */ +#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos))) +/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */ +#define QSPI_RDR_RD_Pos 0 +#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */ +/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */ +#define QSPI_TDR_TD_Pos 0 +#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */ +#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos))) +/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */ +#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */ +#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */ +#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */ +#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */ +#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */ +#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */ +#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */ +#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */ +/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */ +#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */ +#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */ +#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */ +#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */ +#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */ +#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */ +#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */ +/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */ +#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */ +#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */ +#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */ +#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */ +#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */ +#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */ +#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */ +/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */ +#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */ +#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */ +#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */ +#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */ +#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */ +#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */ +/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */ +#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */ +#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */ +#define QSPI_SCR_SCBR_Pos 8 +#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */ +#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos))) +#define QSPI_SCR_DLYBS_Pos 16 +#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */ +#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos))) +/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */ +#define QSPI_IAR_ADDR_Pos 0 +#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */ +#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos))) +/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */ +#define QSPI_ICR_INST_Pos 0 +#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */ +#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos))) +#define QSPI_ICR_OPT_Pos 16 +#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */ +#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos))) +/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */ +#define QSPI_IFR_WIDTH_Pos 0 +#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */ +#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos))) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */ +#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */ +#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */ +#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */ +#define QSPI_IFR_OPTL_Pos 8 +#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */ +#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos))) +#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */ +#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_TFRTYP_Pos 12 +#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */ +#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos))) +#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */ +#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_NBDUM_Pos 16 +#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */ +#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos))) +/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */ +#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */ +#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */ +/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */ +#define QSPI_SKR_USRK_Pos 0 +#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */ +#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos))) +/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */ +#define QSPI_WPMR_WPKEY_Pos 8 +#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */ +#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos))) +#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */ +#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */ +#define QSPI_WPSR_WPVSRC_Pos 8 +#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_QSPI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_rstc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_rstc.h new file mode 100644 index 0000000000..984c621ac4 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_rstc.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_RSTC_COMPONENT_ +#define _SAME70_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) +#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_RSTC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_rswdt.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_rswdt.h new file mode 100644 index 0000000000..959faa2875 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_rswdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_RSWDT_COMPONENT_ +#define _SAME70_RSWDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAME70_RSWDT Reinforced Safety Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rswdt hardware registers */ +typedef struct { + __O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */ + __IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */ + __I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */ +} Rswdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */ +#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */ +#define RSWDT_CR_KEY_Pos 24 +#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */ +#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) +#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */ +#define RSWDT_MR_WDV_Pos 0 +#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */ +#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) +#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */ +#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */ +#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */ +#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */ +#define RSWDT_MR_ALLONES_Pos 16 +#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */ +#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))) +#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */ +#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */ +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */ +#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */ + +/*@}*/ + + +#endif /* _SAME70_RSWDT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_rtc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_rtc.h new file mode 100644 index 0000000000..ef391274d5 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_rtc.h @@ -0,0 +1,234 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_RTC_COMPONENT_ +#define _SAME70_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAME70_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ + __I uint32_t Reserved1[45]; + __IO uint32_t RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos))) +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos))) +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ +#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ +#define RTC_MR_CORRECTION_Pos 8 +#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ +#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) +#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ +#define RTC_MR_OUT0_Pos 16 +#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */ +#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos))) +#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_Pos 20 +#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */ +#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos))) +#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_THIGH_Pos 24 +#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */ +#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos))) +#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */ +#define RTC_MR_TPERIOD_Pos 28 +#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */ +#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos))) +#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ +#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ +/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */ +#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protection Enable */ +#define RTC_WPMR_WPKEY_Pos 8 +#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protection Key */ +#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos))) +#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_RTC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_rtt.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_rtt.h new file mode 100644 index 0000000000..dd4dfd5b86 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_rtt.h @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_RTT_COMPONENT_ +#define _SAME70_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAME70_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ +#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status (cleared on read) */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status (cleared on read) */ + +/*@}*/ + + +#endif /* _SAME70_RTT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_sdramc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_sdramc.h new file mode 100644 index 0000000000..758f78919a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_sdramc.h @@ -0,0 +1,173 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_SDRAMC_COMPONENT_ +#define _SAME70_SDRAMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR SDRAM Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SDRAMC SDRAM Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sdramc hardware registers */ +typedef struct { + __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */ + __I uint32_t Reserved1[1]; + __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< \brief (Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< \brief (Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register */ +} Sdramc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos 0 +#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */ +#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos))) +#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */ +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos 0 +#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */ +#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos))) +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos 0 +#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */ +#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos))) +#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NR_Pos 2 +#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */ +#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos))) +#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */ +#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_CAS_Pos 5 +#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */ +#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos))) +#define SDRAMC_CR_CAS_LATENCY1 (0x0u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2 (0x1u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3 (0x2u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */ +#define SDRAMC_CR_TWR_Pos 8 +#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */ +#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos))) +#define SDRAMC_CR_TRC_TRFC_Pos 12 +#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */ +#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos))) +#define SDRAMC_CR_TRP_Pos 16 +#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */ +#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos))) +#define SDRAMC_CR_TRCD_Pos 20 +#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */ +#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos))) +#define SDRAMC_CR_TRAS_Pos 24 +#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */ +#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos))) +#define SDRAMC_CR_TXSR_Pos 28 +#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */ +#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos))) +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos 0 +#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */ +#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos))) +#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_PASR_Pos 4 +#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos))) +#define SDRAMC_LPR_TCSR_Pos 8 +#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos))) +#define SDRAMC_LPR_DS_Pos 10 +#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */ +#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos))) +#define SDRAMC_LPR_TIMEOUT_Pos 12 +#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled */ +#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos))) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */ +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */ +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */ +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status (cleared on read) */ +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos 0 +#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */ +#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos))) +#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */ +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CFR1_TMRD_Pos 0 +#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos) /**< \brief (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command */ +#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos))) +#define SDRAMC_CFR1_UNAL (0x1u << 8) /**< \brief (SDRAMC_CFR1) Support Unaligned Access */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is supported. */ +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */ +#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */ +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */ +#define SDRAMC_OCMS_KEY1_KEY1_Pos 0 +#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< \brief (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */ +#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos))) +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */ +#define SDRAMC_OCMS_KEY2_KEY2_Pos 0 +#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< \brief (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */ +#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos))) + +/*@}*/ + + +#endif /* _SAME70_SDRAMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_smc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_smc.h new file mode 100644 index 0000000000..02489ddf9a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_smc.h @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_SMC_COMPONENT_ +#define _SAME70_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC MODE Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ + __I uint32_t Reserved1[16]; + __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + __I uint32_t Reserved2[22]; + __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protection Status Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) Read Mode */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) Write Mode */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos))) +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ +#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */ +#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */ +#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ +#define SMC_MODE_PS_Pos 28 +#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ +#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos))) +#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY_Pos 8 +#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protection Key */ +#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) +#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */ +#define SMC_WPSR_WPVSRC_Pos 8 +#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_SMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_spi.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_spi.h new file mode 100644 index 0000000000..69517090e6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_spi.h @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_SPI_COMPONENT_ +#define _SAME70_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + __I uint32_t Reserved2[41]; + __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos))) +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_SPI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_ssc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_ssc.h new file mode 100644 index 0000000000..dd929003d7 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_ssc.h @@ -0,0 +1,280 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_SSC_COMPONENT_ +#define _SAME70_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + __I uint32_t Reserved2[2]; + __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved3[37]; + __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos))) +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos))) +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos))) +#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos))) +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos))) +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos))) +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos))) +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos))) +#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos))) +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos))) +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_SSC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_supc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_supc.h new file mode 100644 index 0000000000..54ad2e048b --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_supc.h @@ -0,0 +1,295 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_SUPC_COMPONENT_ +#define _SAME70_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos))) +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_BKUPRETON (0x1u << 17) /**< \brief (SUPC_MR) SRAM On In Backup Mode */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP0 */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP1 */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low-power Debouncer Clear */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos))) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_LPDBC_Pos 16 +#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low-power Debouncer Period */ +#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos))) +#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 0 */ +#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 1 */ +#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 2 */ +#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 3 */ +#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 4 */ +#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 5 */ +#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 6 */ +#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 7 */ +#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 8 */ +#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 9 */ +#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 10 */ +#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 11 */ +#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 12 */ +#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 13 */ +#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 0 */ +#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 1 */ +#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 2 */ +#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 3 */ +#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 4 */ +#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 5 */ +#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 6 */ +#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 7 */ +#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 8 */ +#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 9 */ +#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 10 */ +#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 11 */ +#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 12 */ +#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 13 */ +#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status (cleared on read) */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status (cleared on read) */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status (cleared on read) */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status (cleared on read) */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */ +#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */ +#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ + +/*@}*/ + + +#endif /* _SAME70_SUPC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_tc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_tc.h new file mode 100644 index 0000000000..ce068e41c9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_tc.h @@ -0,0 +1,346 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_TC_COMPONENT_ +#define _SAME70_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAME70_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ + __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ + __I uint32_t Reserved1[3]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_SBSMPLR_Pos 20 +#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ +#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))) +#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ +#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ +#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ +#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ +#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ +/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ +#define TC_RAB_RAB_Pos 0 +#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ +#define TC_EMR_TRIGSRCA_Pos 0 +#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */ +#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCB_Pos 4 +#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */ +#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). */ +#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) +#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_TC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_trng.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_trng.h new file mode 100644 index 0000000000..f1a18b7634 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_trng.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_TRNG_COMPONENT_ +#define _SAME70_TRNG_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR True Random Number Generator */ +/* ============================================================================= */ +/** \addtogroup SAME70_TRNG True Random Number Generator */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Trng hardware registers */ +typedef struct { + __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */ + __I uint32_t Reserved1[3]; + __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */ + __I uint32_t Reserved2[12]; + __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */ +#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to Provide Random Values */ +#define TRNG_CR_KEY_Pos 8 +#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */ +#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))) +#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */ +/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ +/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ +/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */ +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos 0 +#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */ + +/*@}*/ + + +#endif /* _SAME70_TRNG_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_twihs.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_twihs.h new file mode 100644 index 0000000000..6a5f39da61 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_twihs.h @@ -0,0 +1,250 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_TWIHS_COMPONENT_ +#define _SAME70_TWIHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */ +/* ============================================================================= */ +/** \addtogroup SAME70_TWIHS Two-wire Interface High Speed */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twihs hardware registers */ +typedef struct { + __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */ + __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */ + __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */ + __I uint32_t Reserved4[37]; + __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */ +} Twihs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */ +#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */ +#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */ +#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */ +#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */ +#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */ +#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */ +#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */ +#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */ +#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */ +#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */ +#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */ +#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */ +#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */ +#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */ +#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */ +#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */ +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */ +#define TWIHS_MMR_IADRSZ_Pos 8 +#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */ +#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) +#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */ +#define TWIHS_MMR_DADR_Pos 16 +#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */ +#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */ +#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */ +#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */ +#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */ +#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */ +#define TWIHS_SMR_MASK_Pos 8 +#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) +#define TWIHS_SMR_SADR_Pos 16 +#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */ +#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) +#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */ +#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */ +#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */ +#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */ +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */ +#define TWIHS_IADR_IADR_Pos 0 +#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */ +#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWIHS_CWGR_CLDIV_Pos 0 +#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */ +#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) +#define TWIHS_CWGR_CHDIV_Pos 8 +#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */ +#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) +#define TWIHS_CWGR_CKDIV_Pos 16 +#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */ +#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) +#define TWIHS_CWGR_HOLD_Pos 24 +#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */ +#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */ +#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ +#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */ +#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */ +#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */ +#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */ +#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */ +#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */ +#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */ +#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */ +#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */ +#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */ +#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */ +#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */ +#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */ +#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */ +#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL Line Value */ +#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA Line Value */ +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */ +#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */ +#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */ +#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */ +#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */ +#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */ +#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */ +#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */ +#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */ +#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */ +#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */ +#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */ +#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */ +#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */ +#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */ +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */ +#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */ +#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */ +#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */ +#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */ +#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */ +#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */ +#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */ +#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */ +#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */ +#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */ +#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */ +#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */ +#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */ +#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */ +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */ +#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */ +#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */ +#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */ +#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */ +#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */ +#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */ +#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */ +#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */ +#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */ +#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */ +#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */ +#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */ +#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */ +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */ +#define TWIHS_RHR_RXDATA_Pos 0 +#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */ +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */ +#define TWIHS_THR_TXDATA_Pos 0 +#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */ +#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */ +#define TWIHS_SMBTR_PRESC_Pos 0 +#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */ +#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) +#define TWIHS_SMBTR_TLOWS_Pos 8 +#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) +#define TWIHS_SMBTR_TLOWM_Pos 16 +#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) +#define TWIHS_SMBTR_THMAX_Pos 24 +#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */ +#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */ +#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */ +#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */ +#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */ +#define TWIHS_FILTR_THRES_Pos 8 +#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */ +#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */ +#define TWIHS_SWMR_SADR1_Pos 0 +#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */ +#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) +#define TWIHS_SWMR_SADR2_Pos 8 +#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */ +#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) +#define TWIHS_SWMR_SADR3_Pos 16 +#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */ +#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) +#define TWIHS_SWMR_DATAM_Pos 24 +#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */ +#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */ +#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */ +#define TWIHS_WPMR_WPKEY_Pos 8 +#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */ +#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) +#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */ +#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */ +#define TWIHS_WPSR_WPVSRC_Pos 8 +#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_TWIHS_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_uart.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_uart.h new file mode 100644 index 0000000000..451b72e618 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_uart.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_UART_COMPONENT_ +#define _SAME70_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAME70_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */ + __I uint32_t Reserved1[47]; + __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ +#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */ +#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */ +#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */ +#define UART_CMPR_VAL1_Pos 0 +#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */ +#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))) +#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */ +#define UART_CMPR_VAL2_Pos 16 +#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */ +#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))) +/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */ +#define UART_WPMR_WPKEY_Pos 8 +#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */ +#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))) +#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_UART_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_usart.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_usart.h new file mode 100644 index 0000000000..c8e7a4abda --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_usart.h @@ -0,0 +1,478 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_USART_COMPONENT_ +#define _SAME70_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAME70_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */ + __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + __I uint32_t Reserved1[5]; + __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */ + __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */ + __I uint32_t Reserved3[22]; + __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */ +#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ +#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ +#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos))) +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ +#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos))) +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */ +#define US_MR_USCLKS_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial clock (SCK) is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */ +#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos))) +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos))) +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos))) +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos))) +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */ +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ +#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ +#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ +#define US_IER_NSSE (0x1u << 19) /**< \brief (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable */ +#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ +#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ +#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ +#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ +#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ +#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ +#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ +#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ +#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */ +#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */ +#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */ +#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */ +#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */ +#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */ +#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */ +#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */ +#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */ +#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ +#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ +#define US_IDR_NSSE (0x1u << 19) /**< \brief (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable */ +#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ +#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ +#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ +#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ +#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ +#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ +#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ +#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ +#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */ +#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */ +#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */ +#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */ +#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */ +#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */ +#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */ +#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */ +#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */ +#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ +#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ +#define US_IMR_NSSE (0x1u << 19) /**< \brief (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask */ +#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ +#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ +#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ +#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ +#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ +#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ +#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ +#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ +#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */ +#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */ +#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */ +#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */ +#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */ +#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */ +#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */ +#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */ +#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */ +#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) */ +#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag (cleared on read) */ +#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag (cleared on read) */ +#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (cleared on read) */ +#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_NSSE (0x1u << 19) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_NSS (0x1u << 23) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ +#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) */ +/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +#define US_TTGR_PCYCLE_Pos 0 +#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */ +#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos))) +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) +#define US_FIDI_BETA2_Pos 0 +#define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos) /**< \brief (US_FIDI) LON BETA2 Length */ +#define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos))) +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos))) +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos))) +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ +#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) */ +/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos 0 +#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ +#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos))) +#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ +#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ +#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ +#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ +#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ +#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ +#define US_LINMR_DLC_Pos 8 +#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ +#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) +#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */ +#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */ +/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos 0 +#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ +#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) +/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */ +#define US_LINBRR_LINCD_Pos 0 +#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */ +#define US_LINBRR_LINFP_Pos 16 +#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */ +/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */ +#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */ +#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */ +#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */ +#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */ +#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */ +#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */ +#define US_LONMR_EOFS_Pos 16 +#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */ +#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos))) +/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */ +#define US_LONPR_LONPL_Pos 0 +#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */ +#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos))) +/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */ +#define US_LONDL_LONDL_Pos 0 +#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */ +#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos))) +/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */ +#define US_LONL2HDR_BLI_Pos 0 +#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */ +#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos))) +#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */ +#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */ +/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */ +#define US_LONBL_LONBL_Pos 0 +#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */ +/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */ +#define US_LONB1TX_BETA1TX_Pos 0 +#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */ +#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos))) +/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */ +#define US_LONB1RX_BETA1RX_Pos 0 +#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */ +#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos))) +/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */ +#define US_LONPRIO_PSNB_Pos 0 +#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */ +#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos))) +#define US_LONPRIO_NPS_Pos 8 +#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */ +#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos))) +/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */ +#define US_IDTTX_IDTTX_Pos 0 +#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */ +#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos))) +/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */ +#define US_IDTRX_IDTRX_Pos 0 +#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */ +#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos))) +/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */ +#define US_ICDIFF_ICDIFF_Pos 0 +#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */ +#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos))) +/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_USART_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_usbhs.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_usbhs.h new file mode 100644 index 0000000000..72ea8f5e34 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_usbhs.h @@ -0,0 +1,909 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_USBHS_COMPONENT_ +#define _SAME70_USBHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB High-Speed Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_USBHS USB High-Speed Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UsbhsDevdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UsbhsDevdma; +/** \brief UsbhsHstdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UsbhsHstdma; +/** \brief Usbhs hardware registers */ +#define USBHSDEVDMA_NUMBER 7 +#define USBHSHSTDMA_NUMBER 7 +typedef struct { + __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + __I uint32_t Reserved2[2]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + __I uint32_t Reserved3[2]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + __I uint32_t Reserved4[2]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + __I uint32_t Reserved5[2]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + __I uint32_t Reserved6[2]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + __I uint32_t Reserved7[2]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + __I uint32_t Reserved8[50]; + UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */ + __I uint32_t Reserved9[32]; + __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */ + __I uint32_t Reserved10[52]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + __I uint32_t Reserved11[2]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */ + __I uint32_t Reserved12[2]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + __I uint32_t Reserved13[2]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */ + __I uint32_t Reserved14[2]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + __I uint32_t Reserved15[2]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + __I uint32_t Reserved16[2]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + __I uint32_t Reserved17[2]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + __I uint32_t Reserved18[2]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */ + __I uint32_t Reserved19[26]; + UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */ + __I uint32_t Reserved20[32]; + __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */ + __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */ + __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */ +} Usbhs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */ +#define USBHS_DEVCTRL_UADD_Pos 0 +#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */ +#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos))) +#define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */ +#define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */ +#define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */ +#define USBHS_DEVCTRL_SPDCONF_Pos 10 +#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */ +#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos))) +#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (USBHS_DEVCTRL) Forced high speed. */ +#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ +#define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */ +#define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */ +#define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */ +#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */ +#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */ +/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */ +#define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */ +#define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */ +#define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */ +#define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */ +#define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */ +#define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */ +#define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */ +#define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */ +#define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */ +#define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */ +#define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */ +#define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */ +#define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */ +#define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */ +#define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */ +#define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */ +#define USBHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVISR) Endpoint 10 Interrupt */ +#define USBHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVISR) Endpoint 11 Interrupt */ +#define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */ +#define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */ +#define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */ +#define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */ +#define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */ +#define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */ +#define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */ +#define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */ +#define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */ +#define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */ +#define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */ +#define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */ +#define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */ +#define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */ +#define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */ +#define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */ +#define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */ +#define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */ +#define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */ +#define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIMR) Endpoint 10 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIMR) Endpoint 11 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */ +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */ +#define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */ +#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */ +#define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */ +#define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIDR) Endpoint 10 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIDR) Endpoint 11 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */ +#define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */ +#define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */ +#define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */ +#define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */ +#define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define USBHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIER) Endpoint 10 Interrupt Enable */ +#define USBHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIER) Endpoint 11 Interrupt Enable */ +#define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */ +#define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */ +#define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */ +#define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */ +#define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */ +#define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */ +#define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */ +#define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */ +#define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */ +#define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */ +#define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */ +#define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */ +#define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */ +#define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */ +#define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */ +#define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */ +#define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */ +#define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */ +#define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */ +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */ +#define USBHS_DEVFNUM_MFNUM_Pos 0 +#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */ +#define USBHS_DEVFNUM_FNUM_Pos 3 +#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */ +#define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */ +/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */ +#define USBHS_DEVEPTCFG_EPBK_Pos 2 +#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */ +#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos))) +#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos 4 +#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */ +#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos))) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */ +#define USBHS_DEVEPTCFG_EPTYPE_Pos 11 +#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */ +#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos))) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos 13 +#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */ +#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos))) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTISR_DTSEQ_Pos 8 +#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos 12 +#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */ +#define USBHS_DEVEPTISR_CURRBK_Pos 14 +#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */ +#define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */ +#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */ +#define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */ +#define USBHS_DEVEPTISR_BYCT_Pos 20 +#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */ +#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */ +#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */ +#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */ +#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */ +#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */ +#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */ +#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */ +#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */ +#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */ +#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */ +#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */ +#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */ +#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */ +#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */ +#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */ +#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */ +#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */ +#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */ +#define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */ +#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */ +#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */ +#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */ +#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */ +#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */ +#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */ +#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */ +#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */ +#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */ +#define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */ +#define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */ +#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */ +/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */ +#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */ +#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */ +#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */ +#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */ +#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */ +#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */ +#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */ +#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */ +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */ +#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */ +#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */ +#define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */ +#define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */ +#define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */ +#define USBHS_HSTCTRL_SPDCONF_Pos 12 +#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */ +#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos))) +#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (USBHS_HSTCTRL) Forced high speed. */ +#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ +/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */ +#define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */ +#define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */ +#define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */ +#define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */ +#define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */ +#define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */ +#define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */ +#define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */ +#define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */ +#define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */ +#define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */ +#define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */ +#define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */ +#define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */ +#define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */ +#define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */ +#define USBHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTISR) Pipe 10 Interrupt */ +#define USBHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTISR) Pipe 11 Interrupt */ +#define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */ +#define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */ +#define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */ +#define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */ +#define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */ +#define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */ +#define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */ +#define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */ +#define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */ +#define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */ +#define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */ +#define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIMR) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIMR) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */ +#define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIDR) Pipe 10 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIDR) Pipe 11 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */ +#define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIER) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIER) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */ +#define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */ +#define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */ +#define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */ +#define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */ +#define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */ +#define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */ +#define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */ +#define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */ +#define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */ +#define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */ +#define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */ +#define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */ +#define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */ +#define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */ +#define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */ +#define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */ +#define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */ +#define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */ +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */ +#define USBHS_HSTFNUM_MFNUM_Pos 0 +#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */ +#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos))) +#define USBHS_HSTFNUM_FNUM_Pos 3 +#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */ +#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos))) +#define USBHS_HSTFNUM_FLENHIGH_Pos 16 +#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */ +#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */ +#define USBHS_HSTADDR1_HSTADDRP0_Pos 0 +#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos))) +#define USBHS_HSTADDR1_HSTADDRP1_Pos 8 +#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos))) +#define USBHS_HSTADDR1_HSTADDRP2_Pos 16 +#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos))) +#define USBHS_HSTADDR1_HSTADDRP3_Pos 24 +#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */ +#define USBHS_HSTADDR2_HSTADDRP4_Pos 0 +#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos))) +#define USBHS_HSTADDR2_HSTADDRP5_Pos 8 +#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos))) +#define USBHS_HSTADDR2_HSTADDRP6_Pos 16 +#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos))) +#define USBHS_HSTADDR2_HSTADDRP7_Pos 24 +#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */ +#define USBHS_HSTADDR3_HSTADDRP8_Pos 0 +#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos))) +#define USBHS_HSTADDR3_HSTADDRP9_Pos 8 +#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */ +#define USBHS_HSTPIPCFG_PBK_Pos 2 +#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */ +#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos))) +#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PSIZE_Pos 4 +#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */ +#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos))) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos 8 +#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */ +#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos))) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */ +#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */ +#define USBHS_HSTPIPCFG_PTYPE_Pos 12 +#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */ +#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos))) +#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos 16 +#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */ +#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos))) +#define USBHS_HSTPIPCFG_INTFRQ_Pos 24 +#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */ +#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos))) +#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */ +#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */ +#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */ +#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */ +#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */ +#define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */ +#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */ +#define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */ +#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */ +#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */ +#define USBHS_HSTPIPISR_DTSEQ_Pos 8 +#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos 12 +#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */ +#define USBHS_HSTPIPISR_CURRBK_Pos 14 +#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */ +#define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */ +#define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */ +#define USBHS_HSTPIPISR_PBYCT_Pos 20 +#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */ +#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */ +#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */ +/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */ +#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */ +#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */ +#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */ +#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */ +#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */ +#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */ +#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */ +#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */ +#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */ +#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */ +#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */ +#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */ +#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */ +#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */ +#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */ +#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */ +#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */ +#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */ +#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */ +#define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */ +#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */ +#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */ +#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */ +#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */ +#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */ +#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */ +#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */ +/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define USBHS_HSTPIPINRQ_INRQ_Pos 0 +#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */ +#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos))) +#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */ +/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */ +#define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */ +#define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */ +#define USBHS_HSTPIPERR_COUNTER_Pos 5 +#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */ +#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos))) +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */ +#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */ +#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */ +#define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */ +#define USBHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (USBHS_CTRL) VBUS Hardware Control */ +#define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */ +#define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */ +#define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */ +#define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */ +/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */ +#define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */ +#define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBUS Request (Host mode only) */ +#define USBHS_SR_SPEED_Pos 12 +#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */ +#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */ +/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */ +#define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */ +#define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBUS Request Clear */ +/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */ +#define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */ +#define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBUS Request Set */ + +/*@}*/ + + +#endif /* _SAME70_USBHS_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_utmi.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_utmi.h new file mode 100644 index 0000000000..26ca52180b --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_utmi.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_UTMI_COMPONENT_ +#define _SAME70_UTMI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Transmitter Interface Macrocell */ +/* ============================================================================= */ +/** \addtogroup SAME70_UTMI USB Transmitter Interface Macrocell */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Utmi hardware registers */ +typedef struct { + __I uint32_t Reserved1[4]; + __IO uint32_t UTMI_OHCIICR; /**< \brief (Utmi Offset: 0x10) OHCI Interrupt Configuration Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t UTMI_CKTRIM; /**< \brief (Utmi Offset: 0x30) UTMI Clock Trimming Register */ +} Utmi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) OHCI Interrupt Configuration Register -------- */ +#define UTMI_OHCIICR_RES0 (0x1u << 0) /**< \brief (UTMI_OHCIICR) USB PORTx Reset */ +#define UTMI_OHCIICR_ARIE (0x1u << 4) /**< \brief (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */ +#define UTMI_OHCIICR_APPSTART (0x1u << 5) /**< \brief (UTMI_OHCIICR) Reserved */ +#define UTMI_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (UTMI_OHCIICR) USB Device Pull-up Disable */ +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) UTMI Clock Trimming Register -------- */ +#define UTMI_CKTRIM_FREQ_Pos 0 +#define UTMI_CKTRIM_FREQ_Msk (0x3u << UTMI_CKTRIM_FREQ_Pos) /**< \brief (UTMI_CKTRIM) UTMI Reference Clock Frequency */ +#define UTMI_CKTRIM_FREQ(value) ((UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos))) +#define UTMI_CKTRIM_FREQ_XTAL12 (0x0u << 0) /**< \brief (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16 (0x1u << 0) /**< \brief (UTMI_CKTRIM) 16 MHz reference clock */ + +/*@}*/ + + +#endif /* _SAME70_UTMI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_wdt.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_wdt.h new file mode 100644 index 0000000000..12ddb6da95 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_wdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_WDT_COMPONENT_ +#define _SAME70_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAME70_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */ + +/*@}*/ + + +#endif /* _SAME70_WDT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_xdmac.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_xdmac.h new file mode 100644 index 0000000000..28f3745e59 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_xdmac.h @@ -0,0 +1,616 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_XDMAC_COMPONENT_ +#define _SAME70_XDMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_XDMAC Extensible DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief XdmacChid hardware registers */ +typedef struct { + __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */ + __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */ + __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */ + __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */ + __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */ + __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */ + __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */ + __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */ + __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */ + __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */ + __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */ + __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */ + __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */ + __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */ + __I uint32_t Reserved1[2]; +} XdmacChid; +/** \brief Xdmac hardware registers */ +#define XDMACCHID_NUMBER 24 +typedef struct { + __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */ + __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */ + __I uint32_t Reserved1[3]; + XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */ +} Xdmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */ +#define XDMAC_GTYPE_NB_CH_Pos 0 +#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */ +#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) +#define XDMAC_GTYPE_FIFO_SZ_Pos 5 +#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */ +#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) +#define XDMAC_GTYPE_NB_REQ_Pos 16 +#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */ +#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */ +#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */ +#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */ +#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */ +#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */ +#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilobyte Enable */ +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */ +#define XDMAC_GWAC_PW0_Pos 0 +#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */ +#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) +#define XDMAC_GWAC_PW1_Pos 4 +#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */ +#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) +#define XDMAC_GWAC_PW2_Pos 8 +#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */ +#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) +#define XDMAC_GWAC_PW3_Pos 12 +#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */ +#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */ +#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */ +#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */ +#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */ +#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */ +#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */ +#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */ +#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */ +#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */ +#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */ +#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */ +#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */ +#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */ +#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */ +#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */ +#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */ +#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */ +#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */ +#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */ +#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */ +#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */ +#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */ +#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */ +#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */ +#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */ +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */ +#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */ +#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */ +#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */ +#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */ +#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */ +#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */ +#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */ +#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */ +#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */ +#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */ +#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */ +#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */ +#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */ +#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */ +#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */ +#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */ +#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */ +#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */ +#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */ +#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */ +#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */ +#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */ +#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */ +#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */ +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */ +#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */ +#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */ +#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */ +#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */ +#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */ +#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */ +#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */ +#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */ +#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */ +#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */ +#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */ +#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */ +#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */ +#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */ +#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */ +#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */ +#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */ +#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */ +#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */ +#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */ +#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */ +#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */ +#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */ +#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */ +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */ +#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */ +#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */ +#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */ +#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */ +#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */ +#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */ +#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */ +#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */ +#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */ +#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */ +#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */ +#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */ +#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */ +#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */ +#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */ +#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */ +#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */ +#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */ +#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */ +#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */ +#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */ +#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */ +#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */ +#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */ +/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */ +#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */ +#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */ +#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */ +#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */ +#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */ +#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */ +#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */ +#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */ +#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */ +#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */ +#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */ +#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */ +#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */ +#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */ +#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */ +#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */ +#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */ +#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */ +#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */ +#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */ +#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */ +#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */ +#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */ +#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */ +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */ +#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */ +#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */ +#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */ +#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */ +#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */ +#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */ +#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */ +#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */ +#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */ +#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */ +#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */ +#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */ +#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */ +#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */ +#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */ +#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */ +#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */ +#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */ +#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */ +#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */ +#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */ +#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */ +#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */ +#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */ +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */ +#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */ +#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */ +#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */ +#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */ +#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */ +#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */ +#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */ +#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */ +#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */ +#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */ +#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */ +#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */ +#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */ +#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */ +#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */ +#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */ +#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */ +#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */ +#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */ +#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */ +#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */ +#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */ +#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */ +#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */ +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */ +#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */ +#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */ +#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */ +#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */ +#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */ +#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */ +#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */ +#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */ +#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */ +#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */ +#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */ +#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */ +#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */ +#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */ +#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */ +#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */ +#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */ +#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */ +#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */ +#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */ +#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */ +#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */ +#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */ +#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */ +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */ +#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */ +#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */ +#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */ +#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */ +#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */ +#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */ +#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */ +#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */ +#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */ +#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */ +#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */ +#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */ +#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */ +#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */ +#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */ +#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */ +#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */ +#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */ +#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */ +#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */ +#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */ +#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */ +#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */ +#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */ +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */ +#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */ +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */ +#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */ +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */ +#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */ +#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */ +#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */ +#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */ +#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */ +#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */ +#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */ +#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */ +#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */ +#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */ +#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */ +#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */ +#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */ +#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */ +#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */ +#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */ +#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */ +#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */ +#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */ +#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */ +#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */ +#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */ +#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */ +#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */ +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */ +#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */ +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */ +#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */ +/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */ +#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */ +#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */ +#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */ +#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */ +#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */ +/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */ +#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */ +#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */ +#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */ +#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */ +#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */ +/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */ +#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */ +#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */ +#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */ +#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */ +#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */ +/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */ +#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */ +#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */ +#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */ +#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */ +#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */ +/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */ +#define XDMAC_CSA_SA_Pos 0 +#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */ +#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) +/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */ +#define XDMAC_CDA_DA_Pos 0 +#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */ +#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) +/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */ +#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */ +#define XDMAC_CNDA_NDA_Pos 2 +#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */ +#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos))) +/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */ +#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled. */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled. */ +#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDVIEW_Pos 3 +#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */ +#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) +#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */ +/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */ +#define XDMAC_CUBC_UBLEN_Pos 0 +#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */ +#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) +/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */ +#define XDMAC_CBC_BLEN_Pos 0 +#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */ +#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) +/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */ +#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */ +#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */ +#define XDMAC_CC_MBSIZE_Pos 1 +#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */ +#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) +#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */ +#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer. */ +#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer. */ +#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated. */ +#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */ +#define XDMAC_CC_CSIZE_Pos 8 +#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */ +#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) +#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_DWIDTH_Pos 11 +#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */ +#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) +#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */ +#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0. */ +#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1. */ +#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */ +#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0. */ +#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1. */ +#define XDMAC_CC_SAM_Pos 16 +#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */ +#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) +#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_Pos 18 +#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */ +#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) +#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */ +#define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */ +#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */ +#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */ +#define XDMAC_CC_PERID_Pos 24 +#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier */ +#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */ +#define XDMAC_CDS_MSP_SDS_MSP_Pos 0 +#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) +#define XDMAC_CDS_MSP_DDS_MSP_Pos 16 +#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) +/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */ +#define XDMAC_CSUS_SUBS_Pos 0 +#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */ +#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) +/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */ +#define XDMAC_CDUS_DUBS_Pos 0 +#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */ +#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) + +/*@}*/ + + +#endif /* _SAME70_XDMAC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j19.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j19.h new file mode 100644 index 0000000000..caae7f179b --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j19.h @@ -0,0 +1,431 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70J19_PIO_ +#define _SAME70J19_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j20.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j20.h new file mode 100644 index 0000000000..b4c8725975 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j20.h @@ -0,0 +1,437 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70J20_PIO_ +#define _SAME70J20_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j21.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j21.h new file mode 100644 index 0000000000..1c973f41f6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j21.h @@ -0,0 +1,437 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70J21_PIO_ +#define _SAME70J21_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n19.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n19.h new file mode 100644 index 0000000000..ee761f9ce8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n19.h @@ -0,0 +1,495 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70N19_PIO_ +#define _SAME70N19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n20.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n20.h new file mode 100644 index 0000000000..8bec67ff00 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n20.h @@ -0,0 +1,495 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70N20_PIO_ +#define _SAME70N20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n21.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n21.h new file mode 100644 index 0000000000..a0b3757033 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n21.h @@ -0,0 +1,495 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70N21_PIO_ +#define _SAME70N21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q19.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q19.h new file mode 100644 index 0000000000..532ba6d4e6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q19.h @@ -0,0 +1,668 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70Q19_PIO_ +#define _SAME70Q19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q20.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q20.h new file mode 100644 index 0000000000..f9b35f5d23 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q20.h @@ -0,0 +1,668 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70Q20_PIO_ +#define _SAME70Q20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q21.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q21.h new file mode 100644 index 0000000000..507b287f89 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q21.h @@ -0,0 +1,668 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70Q21_PIO_ +#define _SAME70Q21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70.h b/bsps/arm/atsam/include/libchip/include/same70/same70.h new file mode 100644 index 0000000000..f7e5a5c9ce --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70.h @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_ +#define _SAME70_ + +#if defined __SAME70J19__ + #include "same70j19.h" +#elif defined __SAME70J20__ + #include "same70j20.h" +#elif defined __SAME70J21__ + #include "same70j21.h" +#elif defined __SAME70N19__ + #include "same70n19.h" +#elif defined __SAME70N20__ + #include "same70n20.h" +#elif defined __SAME70N21__ + #include "same70n21.h" +#elif defined __SAME70Q19__ + #include "same70q19.h" +#elif defined __SAME70Q20__ + #include "same70q20.h" +#elif defined __SAME70Q21__ + #include "same70q21.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAME70_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70j19.h b/bsps/arm/atsam/include/libchip/include/same70/same70j19.h new file mode 100644 index 0000000000..a82d7c1ad8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70j19.h @@ -0,0 +1,623 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70J19_ +#define _SAME70J19_ + +/** \addtogroup SAME70J19_definitions SAME70J19 definitions + This file defines all structures and symbols for SAME70J19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70J19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70J19 Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70J19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70J19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70J19 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70J19 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70J19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J19 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAME70J19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70J19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70J19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70J19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70J19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAME70J19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J19 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70j19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70j20.h b/bsps/arm/atsam/include/libchip/include/same70/same70j20.h new file mode 100644 index 0000000000..a877891ea7 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70j20.h @@ -0,0 +1,630 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70J20_ +#define _SAME70J20_ + +/** \addtogroup SAME70J20_definitions SAME70J20 definitions + This file defines all structures and symbols for SAME70J20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70J20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70J20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70J20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70J20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70J20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70J20 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70J20 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70J20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J20 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAME70J20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70J20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70J20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70J20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70J20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAME70J20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J20 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70j20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70j21.h b/bsps/arm/atsam/include/libchip/include/same70/same70j21.h new file mode 100644 index 0000000000..812c28c3af --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70j21.h @@ -0,0 +1,630 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70J21_ +#define _SAME70J21_ + +/** \addtogroup SAME70J21_definitions SAME70J21 definitions + This file defines all structures and symbols for SAME70J21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70J21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70J21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70J21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70J21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70J21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70J21 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70J21 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70J21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J21 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAME70J21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70J21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70J21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70J21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70J21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAME70J21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J21 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70j21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70n19.h b/bsps/arm/atsam/include/libchip/include/same70/same70n19.h new file mode 100644 index 0000000000..ed565d4e31 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70n19.h @@ -0,0 +1,636 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70N19_ +#define _SAME70N19_ + +/** \addtogroup SAME70N19_definitions SAME70N19 definitions + This file defines all structures and symbols for SAME70N19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70N19 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70N19 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70N19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70N19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAME70N19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N19 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70n19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70n20.h b/bsps/arm/atsam/include/libchip/include/same70/same70n20.h new file mode 100644 index 0000000000..84b12656c9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70n20.h @@ -0,0 +1,636 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70N20_ +#define _SAME70N20_ + +/** \addtogroup SAME70N20_definitions SAME70N20 definitions + This file defines all structures and symbols for SAME70N20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70N20 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70N20 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70N20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70N20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAME70N20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N20 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70n20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70n21.h b/bsps/arm/atsam/include/libchip/include/same70/same70n21.h new file mode 100644 index 0000000000..ceaeef3b3c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70n21.h @@ -0,0 +1,636 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70N21_ +#define _SAME70N21_ + +/** \addtogroup SAME70N21_definitions SAME70N21 definitions + This file defines all structures and symbols for SAME70N21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70N21 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70N21 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70N21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70N21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAME70N21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N21 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70n21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70q19.h b/bsps/arm/atsam/include/libchip/include/same70/same70q19.h new file mode 100644 index 0000000000..136ac0e239 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70q19.h @@ -0,0 +1,684 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70Q19_ +#define _SAME70Q19_ + +/** \addtogroup SAME70Q19_definitions SAME70Q19 definitions + This file defines all structures and symbols for SAME70Q19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q19 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q19 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q19 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q19 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q19 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q19 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q19 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q19 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70Q19 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70Q19 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q19 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q19 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q19 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q19 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q19 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q19 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q19 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70q19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70q20.h b/bsps/arm/atsam/include/libchip/include/same70/same70q20.h new file mode 100644 index 0000000000..dc5858cda6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70q20.h @@ -0,0 +1,684 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70Q20_ +#define _SAME70Q20_ + +/** \addtogroup SAME70Q20_definitions SAME70Q20 definitions + This file defines all structures and symbols for SAME70Q20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q20 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q20 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q20 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q20 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q20 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q20 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q20 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q20 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70Q20 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70Q20 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q20 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q20 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q20 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q20 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q20 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q20 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q20 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70q20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70q21.h b/bsps/arm/atsam/include/libchip/include/same70/same70q21.h new file mode 100644 index 0000000000..3cd174e6cf --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70q21.h @@ -0,0 +1,689 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70Q21_ +#define _SAME70Q21_ + +/** \addtogroup SAME70Q21_definitions SAME70Q21 definitions + This file defines all structures and symbols for SAME70Q21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q21 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q21 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q21 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q21 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q21 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q21 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q21 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q21 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70Q21 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAME70Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70Q21 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAME70Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q21 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q21 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q21 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q21 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q21 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q21 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler ( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q21 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70q21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ +#define USBHS_RAM_ADDR (0xA0100000u)/**< USB RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/system_same70.h b/bsps/arm/atsam/include/libchip/include/same70/system_same70.h new file mode 100644 index 0000000000..fd0428426c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/system_same70.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef SYSTEM_SAME70_H_INCLUDED +#define SYSTEM_SAME70_H_INCLUDED +#ifdef __rtems__ +#include +#endif /* __rtems__ */ + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +#ifndef __rtems__ +void SystemInit(void); +#else /* __rtems__ */ +void ATSAM_START_SRAM_SECTION SystemInit(void); +#endif /* __rtems__ */ + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t dw_clk); + +void sysclk_enable_usb(void); +void sysclk_disable_usb(void); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAME70_H_INCLUDED */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_acc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_acc.h new file mode 100644 index 0000000000..84d991560e --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_acc.h @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_ACC_COMPONENT_ +#define _SAMS70_ACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_ACC Analog Comparator Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Acc hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[7]; + __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */ +} Acc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos 0 +#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */ +#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))) +#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_VREFP (0x1u << 0) /**< \brief (ACC_MR) Select VREFP */ +#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_Pos 4 +#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */ +#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))) +#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */ +#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_EDGETYP_Pos 9 +#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */ +#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))) +#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */ +#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */ +#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */ +#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */ +#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */ +#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */ +#define ACC_ACR_HYST_Pos 1 +#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */ +#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */ +#define ACC_WPMR_WPKEY_Pos 8 +#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */ +#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) +#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */ +#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */ + +/*@}*/ + + +#endif /* _SAMS70_ACC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_aes.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_aes.h new file mode 100644 index 0000000000..86d6e95a18 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_aes.h @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_AES_COMPONENT_ +#define _SAMS70_AES_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ============================================================================= */ +/** \addtogroup SAMS70_AES Advanced Encryption Standard */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aes hardware registers */ +typedef struct { + __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */ + __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[2]; + __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */ + __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */ + __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */ + __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */ + __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */ + __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */ + __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */ +#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */ +#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */ +#define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */ +#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */ +#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */ +#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */ +#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */ +#define AES_MR_PROCDLY_Pos 4 +#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */ +#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))) +#define AES_MR_SMOD_Pos 8 +#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */ +#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))) +#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_KEYSIZE_Pos 10 +#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */ +#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))) +#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_OPMOD_Pos 12 +#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */ +#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))) +#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */ +#define AES_MR_CFBS_Pos 16 +#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */ +#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))) +#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */ +#define AES_MR_CKEY_Pos 20 +#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Countermeasure Key */ +#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))) +#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ +#define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) Countermeasure Type 1 */ +#define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AES_MR) Countermeasure type 1 is disabled. */ +#define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Countermeasure type 1 is enabled. */ +#define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) Countermeasure Type 2 */ +#define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Countermeasure type 2 is disabled. */ +#define AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Countermeasure type 2 is enabled. */ +#define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) Countermeasure Type 3 */ +#define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Countermeasure type 3 is disabled. */ +#define AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Countermeasure type 3 is enabled. */ +#define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) Countermeasure Type 4 */ +#define AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Countermeasure type 4 is disabled. */ +#define AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Countermeasure type 4 is enabled. */ +#define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) Countermeasure Type 5 */ +#define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Countermeasure type 5 is disabled. */ +#define AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Countermeasure type 5 is enabled. */ +#define AES_MR_CMTYP6 (0x1u << 29) /**< \brief (AES_MR) Countermeasure Type 6 */ +#define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AES_MR) Countermeasure type 6 is disabled. */ +#define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AES_MR) Countermeasure type 6 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */ +#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */ +#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */ +#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */ +#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */ +#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */ +#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */ +/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ +#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_Pos 12 +#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */ +#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */ +/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */ +#define AES_KEYWR_KEYW_Pos 0 +#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */ +#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))) +/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */ +#define AES_IDATAR_IDATA_Pos 0 +#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */ +#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))) +/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */ +#define AES_ODATAR_ODATA_Pos 0 +#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */ +/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */ +#define AES_IVR_IV_Pos 0 +#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */ +#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))) +/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos 0 +#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */ +#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))) +/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos 0 +#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */ +#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))) +/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */ +#define AES_GHASHR_GHASH_Pos 0 +#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */ +#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))) +/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */ +#define AES_TAGR_TAG_Pos 0 +#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */ +/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos 0 +#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */ +/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */ +#define AES_GCMHR_H_Pos 0 +#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */ +#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))) + +/*@}*/ + + +#endif /* _SAMS70_AES_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_afec.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_afec.h new file mode 100644 index 0000000000..638bf0a4f1 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_afec.h @@ -0,0 +1,483 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_AFEC_COMPONENT_ +#define _SAMS70_AFEC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Front-End Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_AFEC Analog Front-End Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Afec hardware registers */ +typedef struct { + __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */ + __I uint32_t Reserved1[6]; + __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */ + __I uint32_t Reserved3[7]; + __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */ + __I uint32_t Reserved5[11]; + __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */ +} Afec; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */ +#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */ +#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */ +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */ +#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGSEL_Pos 1 +#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos))) +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) Analog Comparator */ +#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */ +#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */ +#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */ +#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_PRESCAL_Pos 8 +#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */ +#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))) +#define AFEC_MR_STARTUP_Pos 16 +#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */ +#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos))) +#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_ONE (0x1u << 23) /**< \brief (AFEC_MR) One */ +#define AFEC_MR_TRACKTIM_Pos 24 +#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */ +#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))) +#define AFEC_MR_TRANSFER_Pos 28 +#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */ +#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))) +#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Enable */ +#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */ +#define AFEC_EMR_CMPMODE_Pos 0 +#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */ +#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos))) +#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPSEL_Pos 3 +#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */ +#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))) +#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPFILTER_Pos 12 +#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */ +#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))) +#define AFEC_EMR_RES_Pos 16 +#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */ +#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos))) +#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */ +#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_SIGNMODE_Pos 28 +#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */ +#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos))) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All channels: Signed conversions. */ +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */ +#define AFEC_SEQ1R_USCH0_Pos 0 +#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */ +#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))) +#define AFEC_SEQ1R_USCH1_Pos 4 +#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */ +#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))) +#define AFEC_SEQ1R_USCH2_Pos 8 +#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */ +#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))) +#define AFEC_SEQ1R_USCH3_Pos 12 +#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */ +#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))) +#define AFEC_SEQ1R_USCH4_Pos 16 +#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */ +#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))) +#define AFEC_SEQ1R_USCH5_Pos 20 +#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */ +#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))) +#define AFEC_SEQ1R_USCH6_Pos 24 +#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */ +#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))) +#define AFEC_SEQ1R_USCH7_Pos 28 +#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */ +#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))) +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */ +#define AFEC_SEQ2R_USCH8_Pos 0 +#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */ +#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))) +#define AFEC_SEQ2R_USCH9_Pos 4 +#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */ +#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))) +#define AFEC_SEQ2R_USCH10_Pos 8 +#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */ +#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))) +#define AFEC_SEQ2R_USCH11_Pos 12 +#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */ +#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))) +#define AFEC_SEQ2R_USCH12_Pos 16 +#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */ +#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos))) +#define AFEC_SEQ2R_USCH13_Pos 20 +#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */ +#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos))) +#define AFEC_SEQ2R_USCH14_Pos 24 +#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */ +#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos))) +#define AFEC_SEQ2R_USCH15_Pos 28 +#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */ +#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos))) +/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */ +#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */ +#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */ +#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */ +#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */ +#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */ +#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */ +#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */ +#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */ +#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */ +#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */ +#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */ +#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */ +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */ +#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */ +#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */ +#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */ +#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */ +#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */ +#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */ +#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */ +#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */ +#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */ +#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */ +#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */ +#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */ +/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */ +#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */ +#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */ +#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */ +#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */ +#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */ +#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */ +#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */ +#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */ +#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */ +#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */ +#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */ +#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */ +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */ +#define AFEC_LCDR_LDATA_Pos 0 +#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */ +#define AFEC_LCDR_CHNB_Pos 24 +#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */ +/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */ +#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */ +#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */ +#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */ +#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */ +#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */ +#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */ +#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */ +#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */ +#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */ +#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */ +#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */ +#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */ +#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */ +#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */ +#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */ +#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */ +/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */ +#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */ +#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */ +#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */ +#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */ +#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */ +#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */ +#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */ +#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */ +#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */ +#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */ +#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */ +#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */ +#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */ +#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */ +#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */ +#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */ +/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */ +#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */ +#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */ +#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */ +#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */ +#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */ +#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */ +#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */ +#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */ +#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */ +#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */ +#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */ +#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */ +#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */ +#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */ +#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */ +#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */ +/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */ +#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) */ +#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change (cleared on read) */ +/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */ +#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */ +#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */ +#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */ +#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */ +#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */ +#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */ +#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */ +#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */ +#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */ +#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */ +#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */ +#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */ +/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */ +#define AFEC_CWR_LOWTHRES_Pos 0 +#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */ +#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))) +#define AFEC_CWR_HIGHTHRES_Pos 16 +#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */ +#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))) +/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */ +#define AFEC_CGR_GAIN0_Pos 0 +#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for Channel 0 */ +#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))) +#define AFEC_CGR_GAIN1_Pos 2 +#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for Channel 1 */ +#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))) +#define AFEC_CGR_GAIN2_Pos 4 +#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for Channel 2 */ +#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))) +#define AFEC_CGR_GAIN3_Pos 6 +#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for Channel 3 */ +#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))) +#define AFEC_CGR_GAIN4_Pos 8 +#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for Channel 4 */ +#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))) +#define AFEC_CGR_GAIN5_Pos 10 +#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for Channel 5 */ +#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))) +#define AFEC_CGR_GAIN6_Pos 12 +#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for Channel 6 */ +#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))) +#define AFEC_CGR_GAIN7_Pos 14 +#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for Channel 7 */ +#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))) +#define AFEC_CGR_GAIN8_Pos 16 +#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for Channel 8 */ +#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))) +#define AFEC_CGR_GAIN9_Pos 18 +#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for Channel 9 */ +#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))) +#define AFEC_CGR_GAIN10_Pos 20 +#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for Channel 10 */ +#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))) +#define AFEC_CGR_GAIN11_Pos 22 +#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for Channel 11 */ +#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))) +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */ +#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */ +#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */ +#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */ +#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */ +#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */ +#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */ +#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */ +#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */ +#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */ +#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */ +#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */ +#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */ +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */ +#define AFEC_CSELR_CSEL_Pos 0 +#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */ +#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))) +/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */ +#define AFEC_CDR_DATA_Pos 0 +#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */ +/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */ +#define AFEC_COCR_AOFF_Pos 0 +#define AFEC_COCR_AOFF_Msk (0x3ffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */ +#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))) +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */ +#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos))) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */ +#define AFEC_TEMPCWR_TLOWTHRES_Pos 0 +#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */ +#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))) +#define AFEC_TEMPCWR_THIGHTHRES_Pos 16 +#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */ +#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))) +/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */ +#define AFEC_ACR_PGA0EN (0x1u << 2) /**< \brief (AFEC_ACR) PGA0 Enable */ +#define AFEC_ACR_PGA1EN (0x1u << 3) /**< \brief (AFEC_ACR) PGA1 Enable */ +#define AFEC_ACR_IBCTL_Pos 8 +#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFE Bias Current Control */ +#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))) +/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */ +#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */ +#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */ +#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */ +#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */ +#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */ +#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */ +#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */ +#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */ +#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */ +#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */ +#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */ +#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */ +/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */ +#define AFEC_COSR_CSEL (0x1u << 0) /**< \brief (AFEC_COSR) Sample & Hold unit Correction Select */ +/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */ +#define AFEC_CVR_OFFSETCORR_Pos 0 +#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */ +#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos))) +#define AFEC_CVR_GAINCORR_Pos 16 +#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */ +#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos))) +/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */ +#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */ +#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */ +#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */ +#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */ +#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */ +#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */ +#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */ +#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */ +#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */ +#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */ +#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */ +#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */ +/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */ +#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */ +#define AFEC_WPMR_WPKEY_Pos 8 +#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */ +#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos))) +#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */ +#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */ +#define AFEC_WPSR_WPVSRC_Pos 8 +#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_AFEC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_chipid.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_chipid.h new file mode 100644 index 0000000000..b6ca561684 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_chipid.h @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_CHIPID_COMPONENT_ +#define _SAMS70_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAMS70_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) /**< \brief (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) /**< \brief (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) /**< \brief (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) /**< \brief (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAMS70_CHIPID_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_dacc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_dacc.h new file mode 100644 index 0000000000..d9f5fd020a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_dacc.h @@ -0,0 +1,184 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_DACC_COMPONENT_ +#define _SAMS70_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */ + __I uint32_t Reserved1[1]; + __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */ + __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status Register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */ +#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */ +#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */ +#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC. */ +#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). */ +#define DACC_MR_ZERO (0x1u << 5) /**< \brief (DACC_MR) Must always be written to 0. */ +#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */ +#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 are single-ended outputs. */ +#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */ +#define DACC_MR_PRESCALER_Pos 24 +#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */ +#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))) +/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */ +#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */ +#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */ +#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGSEL0_Pos 4 +#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */ +#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))) +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_TRGSEL1_Pos 8 +#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */ +#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))) +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_OSR0_Pos 16 +#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */ +#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))) +#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_Pos 20 +#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */ +#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))) +#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC Ready Flag */ +#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC Ready Flag */ +/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */ +#define DACC_CDR_DATA0_Pos 0 +#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */ +#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))) +#define DACC_CDR_DATA1_Pos 16 +#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */ +#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */ +#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */ +#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */ +#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */ +#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */ +#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */ +#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */ +#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */ +#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */ +#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */ +#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */ +#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */ +#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status Register -------- */ +#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */ +#define DACC_WPSR_WPVSRC_Pos 8 +#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_DACC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_efc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_efc.h new file mode 100644 index 0000000000..7ac6dedf1d --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_efc.h @@ -0,0 +1,111 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_EFC_COMPONENT_ +#define _SAMS70_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ + __I uint32_t Reserved1[53]; + __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) +#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status (cleared on read) */ +#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) */ +#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ +/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */ +#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */ +#define EEFC_WPMR_WPKEY_Pos 8 +#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */ +#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos))) +#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMS70_EFC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_gpbr.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_gpbr.h new file mode 100644 index 0000000000..7a4139a128 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_gpbr.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_GPBR_COMPONENT_ +#define _SAMS70_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */ +/* ============================================================================= */ +/** \addtogroup SAMS70_GPBR General Purpose Backup Registers */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAMS70_GPBR_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_hsmci.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_hsmci.h new file mode 100644 index 0000000000..53fbd4a024 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_hsmci.h @@ -0,0 +1,335 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_HSMCI_COMPONENT_ +#define _SAMS70_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAMS70_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + __I uint32_t Reserved1[2]; + __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + __I uint32_t Reserved2[35]; + __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[69]; + __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos))) +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos))) +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos))) +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos))) +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos))) +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos))) +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos))) +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos))) +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))) +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos))) +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended (cleared on read) */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error (cleared on read) */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error (cleared on read) */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error (cleared on read) */ +#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error (cleared on read) */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ +#define HSMCI_DMA_CHKSIZE_Pos 4 +#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos))) +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */ +#define HSMCI_WPMR_WPKEY_Pos 8 +#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */ +#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos))) +#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WPVSRC_Pos 8 +#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */ +/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) + +/*@}*/ + + +#endif /* _SAMS70_HSMCI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_icm.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_icm.h new file mode 100644 index 0000000000..3c2c3eb854 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_icm.h @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_ICM_COMPONENT_ +#define _SAMS70_ICM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */ +/* ============================================================================= */ +/** \addtogroup SAMS70_ICM Integrity Check Monitor */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Icm hardware registers */ +typedef struct { + __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */ + __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */ + __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */ +} Icm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */ +#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */ +#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */ +#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */ +#define ICM_CFG_BBC_Pos 4 +#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */ +#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))) +#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */ +#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */ +#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */ +#define ICM_CFG_UALGO_Pos 13 +#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */ +#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))) +#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_HAPROT_Pos 16 +#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */ +#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))) +#define ICM_CFG_DAPROT_Pos 24 +#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */ +#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))) +/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */ +#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */ +#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */ +#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */ +#define ICM_CTRL_REHASH_Pos 4 +#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */ +#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))) +#define ICM_CTRL_RMDIS_Pos 8 +#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */ +#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))) +#define ICM_CTRL_RMEN_Pos 12 +#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */ +#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))) +/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */ +#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */ +#define ICM_SR_RAWRMDIS_Pos 8 +#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Raw Status */ +#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))) +#define ICM_SR_RMDIS_Pos 12 +#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */ +#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))) +/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */ +#define ICM_IER_RHC_Pos 0 +#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */ +#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))) +#define ICM_IER_RDM_Pos 4 +#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */ +#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))) +#define ICM_IER_RBE_Pos 8 +#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */ +#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))) +#define ICM_IER_RWC_Pos 12 +#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */ +#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))) +#define ICM_IER_REC_Pos 16 +#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */ +#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))) +#define ICM_IER_RSU_Pos 20 +#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */ +#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))) +#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */ +/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */ +#define ICM_IDR_RHC_Pos 0 +#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */ +#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))) +#define ICM_IDR_RDM_Pos 4 +#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */ +#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))) +#define ICM_IDR_RBE_Pos 8 +#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */ +#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))) +#define ICM_IDR_RWC_Pos 12 +#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */ +#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))) +#define ICM_IDR_REC_Pos 16 +#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */ +#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))) +#define ICM_IDR_RSU_Pos 20 +#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */ +#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))) +#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */ +/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */ +#define ICM_IMR_RHC_Pos 0 +#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */ +#define ICM_IMR_RDM_Pos 4 +#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */ +#define ICM_IMR_RBE_Pos 8 +#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */ +#define ICM_IMR_RWC_Pos 12 +#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */ +#define ICM_IMR_REC_Pos 16 +#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */ +#define ICM_IMR_RSU_Pos 20 +#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */ +#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */ +/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */ +#define ICM_ISR_RHC_Pos 0 +#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */ +#define ICM_ISR_RDM_Pos 4 +#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */ +#define ICM_ISR_RBE_Pos 8 +#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */ +#define ICM_ISR_RWC_Pos 12 +#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */ +#define ICM_ISR_REC_Pos 16 +#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */ +#define ICM_ISR_RSU_Pos 20 +#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */ +#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */ +/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */ +#define ICM_UASR_URAT_Pos 0 +#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */ +/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */ +#define ICM_DSCR_DASA_Pos 6 +#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */ +#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))) +/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */ +#define ICM_HASH_HASA_Pos 7 +#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */ +#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))) +/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */ +#define ICM_UIHVAL_VAL_Pos 0 +#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */ +#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))) + +/*@}*/ + + +#endif /* _SAMS70_ICM_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_isi.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_isi.h new file mode 100644 index 0000000000..82dd0cbf91 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_isi.h @@ -0,0 +1,280 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_ISI_COMPONENT_ +#define _SAMS70_ISI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Image Sensor Interface */ +/* ============================================================================= */ +/** \addtogroup SAMS70_ISI Image Sensor Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Isi hardware registers */ +typedef struct { + __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */ + __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */ + __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */ + __I uint32_t Reserved1[34]; + __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */ +} Isi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */ +#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */ +#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */ +#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */ +#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */ +#define ISI_CFG1_FRATE_Pos 8 +#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */ +#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))) +#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */ +#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */ +#define ISI_CFG1_THMASK_Pos 13 +#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */ +#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos))) +#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_SLD_Pos 16 +#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */ +#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))) +#define ISI_CFG1_SFD_Pos 24 +#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */ +#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))) +/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos 0 +#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))) +#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */ +#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */ +#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */ +#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */ +#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */ +#define ISI_CFG2_IM_HSIZE_Pos 16 +#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))) +#define ISI_CFG2_YCC_SWAP_Pos 28 +#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */ +#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))) +#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_RGB_CFG_Pos 30 +#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */ +#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))) +#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos 0 +#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */ +#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))) +#define ISI_PSIZE_PREV_HSIZE_Pos 16 +#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */ +#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))) +/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos 0 +#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */ +#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))) +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos 0 +#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))) +#define ISI_Y2R_SET0_C1_Pos 8 +#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))) +#define ISI_Y2R_SET0_C2_Pos 16 +#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))) +#define ISI_Y2R_SET0_C3_Pos 24 +#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))) +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos 0 +#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))) +#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */ +#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */ +#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */ +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos 0 +#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))) +#define ISI_R2Y_SET0_C1_Pos 8 +#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))) +#define ISI_R2Y_SET0_C2_Pos 16 +#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))) +#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */ +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos 0 +#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))) +#define ISI_R2Y_SET1_C4_Pos 8 +#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))) +#define ISI_R2Y_SET1_C5_Pos 16 +#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */ +#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))) +#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */ +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos 0 +#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */ +#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))) +#define ISI_R2Y_SET2_C7_Pos 8 +#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */ +#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))) +#define ISI_R2Y_SET2_C8_Pos 16 +#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */ +#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))) +#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */ +/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */ +#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */ +#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */ +#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */ +#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */ +/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */ +#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */ +#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */ +#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */ +#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */ +#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */ +#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */ +#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */ +#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */ +#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */ +#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */ +/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */ +#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */ +#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */ +#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */ +#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */ +#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */ +#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */ +#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */ +#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */ +/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */ +#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */ +#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */ +#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */ +#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */ +#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */ +#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */ +/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */ +#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */ +#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */ +#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */ +#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */ +#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */ +#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */ +#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */ +#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */ +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */ +#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */ +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */ +#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */ +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */ +#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */ +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos 2 +#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */ +#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))) +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */ +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos 2 +#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */ +#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))) +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos 2 +#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */ +#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))) +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */ +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos 2 +#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */ +#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))) +/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */ +#define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */ +#define ISI_WPMR_WPKEY_Pos 8 +#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */ +#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos))) +#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */ +#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */ +#define ISI_WPSR_WPVSRC_Pos 8 +#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_ISI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h new file mode 100644 index 0000000000..b539d4d1f9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h @@ -0,0 +1,461 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_MATRIX_COMPONENT_ +#define _SAMS70_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAMS70_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Matrix hardware registers */ +typedef struct { + __IO uint32_t MATRIX_MCFG0; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register 0 */ + __IO uint32_t MATRIX_MCFG1; /**< \brief (Matrix Offset: 0x0004) Master Configuration Register 1 */ + __IO uint32_t MATRIX_MCFG2; /**< \brief (Matrix Offset: 0x0008) Master Configuration Register 2 */ + __IO uint32_t MATRIX_MCFG3; /**< \brief (Matrix Offset: 0x000C) Master Configuration Register 3 */ + __IO uint32_t MATRIX_MCFG4; /**< \brief (Matrix Offset: 0x0010) Master Configuration Register 4 */ + __IO uint32_t MATRIX_MCFG5; /**< \brief (Matrix Offset: 0x0014) Master Configuration Register 5 */ + __IO uint32_t MATRIX_MCFG6; /**< \brief (Matrix Offset: 0x0018) Master Configuration Register 6 */ + __I uint32_t Reserved1[1]; + __IO uint32_t MATRIX_MCFG8; /**< \brief (Matrix Offset: 0x0020) Master Configuration Register 8 */ + __I uint32_t Reserved2[7]; + __IO uint32_t MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + __I uint32_t Reserved3[7]; + __IO uint32_t MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS0; /**< \brief (Matrix Offset: 0x0084) Priority Register B for Slave 0 */ + __IO uint32_t MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ + __IO uint32_t MATRIX_PRBS1; /**< \brief (Matrix Offset: 0x008C) Priority Register B for Slave 1 */ + __IO uint32_t MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ + __IO uint32_t MATRIX_PRBS2; /**< \brief (Matrix Offset: 0x0094) Priority Register B for Slave 2 */ + __IO uint32_t MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ + __IO uint32_t MATRIX_PRBS3; /**< \brief (Matrix Offset: 0x009C) Priority Register B for Slave 3 */ + __IO uint32_t MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ + __IO uint32_t MATRIX_PRBS4; /**< \brief (Matrix Offset: 0x00A4) Priority Register B for Slave 4 */ + __IO uint32_t MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */ + __IO uint32_t MATRIX_PRBS5; /**< \brief (Matrix Offset: 0x00AC) Priority Register B for Slave 5 */ + __IO uint32_t MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */ + __IO uint32_t MATRIX_PRBS6; /**< \brief (Matrix Offset: 0x00B4) Priority Register B for Slave 6 */ + __IO uint32_t MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */ + __IO uint32_t MATRIX_PRBS7; /**< \brief (Matrix Offset: 0x00BC) Priority Register B for Slave 7 */ + __IO uint32_t MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */ + __IO uint32_t MATRIX_PRBS8; /**< \brief (Matrix Offset: 0x00C4) Priority Register B for Slave 8 */ + __I uint32_t Reserved4[14]; + __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ + __I uint32_t Reserved5[4]; + __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration Register */ + __I uint32_t Reserved6[3]; + __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */ + __I uint32_t Reserved7[47]; + __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */ +#define MATRIX_MCFG0_ULBT_Pos 0 +#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) /**< \brief (MATRIX_MCFG0) Undefined Length Burst Type */ +#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos))) +#define MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG0) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG0) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG0) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG0) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG0) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG0) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG0) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG0) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */ +#define MATRIX_MCFG1_ULBT_Pos 0 +#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) /**< \brief (MATRIX_MCFG1) Undefined Length Burst Type */ +#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos))) +#define MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG1) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG1) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG1) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG1) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG1) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG1) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG1) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG1) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */ +#define MATRIX_MCFG2_ULBT_Pos 0 +#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) /**< \brief (MATRIX_MCFG2) Undefined Length Burst Type */ +#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos))) +#define MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG2) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG2) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG2) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG2) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG2) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG2) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG2) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG2) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */ +#define MATRIX_MCFG3_ULBT_Pos 0 +#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) /**< \brief (MATRIX_MCFG3) Undefined Length Burst Type */ +#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos))) +#define MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG3) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG3) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG3) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG3) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG3) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG3) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG3) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG3) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */ +#define MATRIX_MCFG4_ULBT_Pos 0 +#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) /**< \brief (MATRIX_MCFG4) Undefined Length Burst Type */ +#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos))) +#define MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG4) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG4) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG4) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG4) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG4) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG4) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG4) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG4) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */ +#define MATRIX_MCFG5_ULBT_Pos 0 +#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) /**< \brief (MATRIX_MCFG5) Undefined Length Burst Type */ +#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos))) +#define MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG5) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG5) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG5) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG5) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG5) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG5) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG5) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG5) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */ +#define MATRIX_MCFG6_ULBT_Pos 0 +#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) /**< \brief (MATRIX_MCFG6) Undefined Length Burst Type */ +#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos))) +#define MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG6) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG6) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG6) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG6) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG6) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG6) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG6) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG6) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */ +#define MATRIX_MCFG8_ULBT_Pos 0 +#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) /**< \brief (MATRIX_MCFG8) Undefined Length Burst Type */ +#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos))) +#define MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG8) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG8) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG8) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG8) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG8) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG8) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG8) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG8) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS0_M0PR_Pos 0 +#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ +#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos))) +#define MATRIX_PRAS0_M1PR_Pos 4 +#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ +#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos))) +#define MATRIX_PRAS0_M2PR_Pos 8 +#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ +#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos))) +#define MATRIX_PRAS0_M3PR_Pos 12 +#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ +#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos))) +#define MATRIX_PRAS0_M4PR_Pos 16 +#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ +#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos))) +#define MATRIX_PRAS0_M5PR_Pos 20 +#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /**< \brief (MATRIX_PRAS0) Master 5 Priority */ +#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos))) +#define MATRIX_PRAS0_M6PR_Pos 24 +#define MATRIX_PRAS0_M6PR_Msk (0x3u << MATRIX_PRAS0_M6PR_Pos) /**< \brief (MATRIX_PRAS0) Master 6 Priority */ +#define MATRIX_PRAS0_M6PR(value) ((MATRIX_PRAS0_M6PR_Msk & ((value) << MATRIX_PRAS0_M6PR_Pos))) +/* -------- MATRIX_PRBS0 : (MATRIX Offset: 0x0084) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS0_M8PR_Pos 0 +#define MATRIX_PRBS0_M8PR_Msk (0x3u << MATRIX_PRBS0_M8PR_Pos) /**< \brief (MATRIX_PRBS0) Master 8 Priority */ +#define MATRIX_PRBS0_M8PR(value) ((MATRIX_PRBS0_M8PR_Msk & ((value) << MATRIX_PRBS0_M8PR_Pos))) +/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ +#define MATRIX_PRAS1_M0PR_Pos 0 +#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ +#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos))) +#define MATRIX_PRAS1_M1PR_Pos 4 +#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ +#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos))) +#define MATRIX_PRAS1_M2PR_Pos 8 +#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ +#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos))) +#define MATRIX_PRAS1_M3PR_Pos 12 +#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ +#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos))) +#define MATRIX_PRAS1_M4PR_Pos 16 +#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ +#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos))) +#define MATRIX_PRAS1_M5PR_Pos 20 +#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /**< \brief (MATRIX_PRAS1) Master 5 Priority */ +#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos))) +#define MATRIX_PRAS1_M6PR_Pos 24 +#define MATRIX_PRAS1_M6PR_Msk (0x3u << MATRIX_PRAS1_M6PR_Pos) /**< \brief (MATRIX_PRAS1) Master 6 Priority */ +#define MATRIX_PRAS1_M6PR(value) ((MATRIX_PRAS1_M6PR_Msk & ((value) << MATRIX_PRAS1_M6PR_Pos))) +/* -------- MATRIX_PRBS1 : (MATRIX Offset: 0x008C) Priority Register B for Slave 1 -------- */ +#define MATRIX_PRBS1_M8PR_Pos 0 +#define MATRIX_PRBS1_M8PR_Msk (0x3u << MATRIX_PRBS1_M8PR_Pos) /**< \brief (MATRIX_PRBS1) Master 8 Priority */ +#define MATRIX_PRBS1_M8PR(value) ((MATRIX_PRBS1_M8PR_Msk & ((value) << MATRIX_PRBS1_M8PR_Pos))) +/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ +#define MATRIX_PRAS2_M0PR_Pos 0 +#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ +#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos))) +#define MATRIX_PRAS2_M1PR_Pos 4 +#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ +#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos))) +#define MATRIX_PRAS2_M2PR_Pos 8 +#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ +#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos))) +#define MATRIX_PRAS2_M3PR_Pos 12 +#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ +#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos))) +#define MATRIX_PRAS2_M4PR_Pos 16 +#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ +#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos))) +#define MATRIX_PRAS2_M5PR_Pos 20 +#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /**< \brief (MATRIX_PRAS2) Master 5 Priority */ +#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos))) +#define MATRIX_PRAS2_M6PR_Pos 24 +#define MATRIX_PRAS2_M6PR_Msk (0x3u << MATRIX_PRAS2_M6PR_Pos) /**< \brief (MATRIX_PRAS2) Master 6 Priority */ +#define MATRIX_PRAS2_M6PR(value) ((MATRIX_PRAS2_M6PR_Msk & ((value) << MATRIX_PRAS2_M6PR_Pos))) +/* -------- MATRIX_PRBS2 : (MATRIX Offset: 0x0094) Priority Register B for Slave 2 -------- */ +#define MATRIX_PRBS2_M8PR_Pos 0 +#define MATRIX_PRBS2_M8PR_Msk (0x3u << MATRIX_PRBS2_M8PR_Pos) /**< \brief (MATRIX_PRBS2) Master 8 Priority */ +#define MATRIX_PRBS2_M8PR(value) ((MATRIX_PRBS2_M8PR_Msk & ((value) << MATRIX_PRBS2_M8PR_Pos))) +/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ +#define MATRIX_PRAS3_M0PR_Pos 0 +#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ +#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos))) +#define MATRIX_PRAS3_M1PR_Pos 4 +#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ +#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos))) +#define MATRIX_PRAS3_M2PR_Pos 8 +#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ +#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos))) +#define MATRIX_PRAS3_M3PR_Pos 12 +#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ +#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos))) +#define MATRIX_PRAS3_M4PR_Pos 16 +#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ +#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos))) +#define MATRIX_PRAS3_M5PR_Pos 20 +#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /**< \brief (MATRIX_PRAS3) Master 5 Priority */ +#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos))) +#define MATRIX_PRAS3_M6PR_Pos 24 +#define MATRIX_PRAS3_M6PR_Msk (0x3u << MATRIX_PRAS3_M6PR_Pos) /**< \brief (MATRIX_PRAS3) Master 6 Priority */ +#define MATRIX_PRAS3_M6PR(value) ((MATRIX_PRAS3_M6PR_Msk & ((value) << MATRIX_PRAS3_M6PR_Pos))) +/* -------- MATRIX_PRBS3 : (MATRIX Offset: 0x009C) Priority Register B for Slave 3 -------- */ +#define MATRIX_PRBS3_M8PR_Pos 0 +#define MATRIX_PRBS3_M8PR_Msk (0x3u << MATRIX_PRBS3_M8PR_Pos) /**< \brief (MATRIX_PRBS3) Master 8 Priority */ +#define MATRIX_PRBS3_M8PR(value) ((MATRIX_PRBS3_M8PR_Msk & ((value) << MATRIX_PRBS3_M8PR_Pos))) +/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ +#define MATRIX_PRAS4_M0PR_Pos 0 +#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ +#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos))) +#define MATRIX_PRAS4_M1PR_Pos 4 +#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ +#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos))) +#define MATRIX_PRAS4_M2PR_Pos 8 +#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ +#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos))) +#define MATRIX_PRAS4_M3PR_Pos 12 +#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ +#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos))) +#define MATRIX_PRAS4_M4PR_Pos 16 +#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ +#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos))) +#define MATRIX_PRAS4_M5PR_Pos 20 +#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /**< \brief (MATRIX_PRAS4) Master 5 Priority */ +#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos))) +#define MATRIX_PRAS4_M6PR_Pos 24 +#define MATRIX_PRAS4_M6PR_Msk (0x3u << MATRIX_PRAS4_M6PR_Pos) /**< \brief (MATRIX_PRAS4) Master 6 Priority */ +#define MATRIX_PRAS4_M6PR(value) ((MATRIX_PRAS4_M6PR_Msk & ((value) << MATRIX_PRAS4_M6PR_Pos))) +/* -------- MATRIX_PRBS4 : (MATRIX Offset: 0x00A4) Priority Register B for Slave 4 -------- */ +#define MATRIX_PRBS4_M8PR_Pos 0 +#define MATRIX_PRBS4_M8PR_Msk (0x3u << MATRIX_PRBS4_M8PR_Pos) /**< \brief (MATRIX_PRBS4) Master 8 Priority */ +#define MATRIX_PRBS4_M8PR(value) ((MATRIX_PRBS4_M8PR_Msk & ((value) << MATRIX_PRBS4_M8PR_Pos))) +/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */ +#define MATRIX_PRAS5_M0PR_Pos 0 +#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */ +#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos))) +#define MATRIX_PRAS5_M1PR_Pos 4 +#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */ +#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos))) +#define MATRIX_PRAS5_M2PR_Pos 8 +#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */ +#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos))) +#define MATRIX_PRAS5_M3PR_Pos 12 +#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */ +#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos))) +#define MATRIX_PRAS5_M4PR_Pos 16 +#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */ +#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos))) +#define MATRIX_PRAS5_M5PR_Pos 20 +#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /**< \brief (MATRIX_PRAS5) Master 5 Priority */ +#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos))) +#define MATRIX_PRAS5_M6PR_Pos 24 +#define MATRIX_PRAS5_M6PR_Msk (0x3u << MATRIX_PRAS5_M6PR_Pos) /**< \brief (MATRIX_PRAS5) Master 6 Priority */ +#define MATRIX_PRAS5_M6PR(value) ((MATRIX_PRAS5_M6PR_Msk & ((value) << MATRIX_PRAS5_M6PR_Pos))) +/* -------- MATRIX_PRBS5 : (MATRIX Offset: 0x00AC) Priority Register B for Slave 5 -------- */ +#define MATRIX_PRBS5_M8PR_Pos 0 +#define MATRIX_PRBS5_M8PR_Msk (0x3u << MATRIX_PRBS5_M8PR_Pos) /**< \brief (MATRIX_PRBS5) Master 8 Priority */ +#define MATRIX_PRBS5_M8PR(value) ((MATRIX_PRBS5_M8PR_Msk & ((value) << MATRIX_PRBS5_M8PR_Pos))) +/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */ +#define MATRIX_PRAS6_M0PR_Pos 0 +#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */ +#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos))) +#define MATRIX_PRAS6_M1PR_Pos 4 +#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */ +#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos))) +#define MATRIX_PRAS6_M2PR_Pos 8 +#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */ +#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos))) +#define MATRIX_PRAS6_M3PR_Pos 12 +#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */ +#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos))) +#define MATRIX_PRAS6_M4PR_Pos 16 +#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */ +#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos))) +#define MATRIX_PRAS6_M5PR_Pos 20 +#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos) /**< \brief (MATRIX_PRAS6) Master 5 Priority */ +#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos))) +#define MATRIX_PRAS6_M6PR_Pos 24 +#define MATRIX_PRAS6_M6PR_Msk (0x3u << MATRIX_PRAS6_M6PR_Pos) /**< \brief (MATRIX_PRAS6) Master 6 Priority */ +#define MATRIX_PRAS6_M6PR(value) ((MATRIX_PRAS6_M6PR_Msk & ((value) << MATRIX_PRAS6_M6PR_Pos))) +/* -------- MATRIX_PRBS6 : (MATRIX Offset: 0x00B4) Priority Register B for Slave 6 -------- */ +#define MATRIX_PRBS6_M8PR_Pos 0 +#define MATRIX_PRBS6_M8PR_Msk (0x3u << MATRIX_PRBS6_M8PR_Pos) /**< \brief (MATRIX_PRBS6) Master 8 Priority */ +#define MATRIX_PRBS6_M8PR(value) ((MATRIX_PRBS6_M8PR_Msk & ((value) << MATRIX_PRBS6_M8PR_Pos))) +/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */ +#define MATRIX_PRAS7_M0PR_Pos 0 +#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */ +#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos))) +#define MATRIX_PRAS7_M1PR_Pos 4 +#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */ +#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos))) +#define MATRIX_PRAS7_M2PR_Pos 8 +#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */ +#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos))) +#define MATRIX_PRAS7_M3PR_Pos 12 +#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */ +#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos))) +#define MATRIX_PRAS7_M4PR_Pos 16 +#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */ +#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos))) +#define MATRIX_PRAS7_M5PR_Pos 20 +#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos) /**< \brief (MATRIX_PRAS7) Master 5 Priority */ +#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos))) +#define MATRIX_PRAS7_M6PR_Pos 24 +#define MATRIX_PRAS7_M6PR_Msk (0x3u << MATRIX_PRAS7_M6PR_Pos) /**< \brief (MATRIX_PRAS7) Master 6 Priority */ +#define MATRIX_PRAS7_M6PR(value) ((MATRIX_PRAS7_M6PR_Msk & ((value) << MATRIX_PRAS7_M6PR_Pos))) +/* -------- MATRIX_PRBS7 : (MATRIX Offset: 0x00BC) Priority Register B for Slave 7 -------- */ +#define MATRIX_PRBS7_M8PR_Pos 0 +#define MATRIX_PRBS7_M8PR_Msk (0x3u << MATRIX_PRBS7_M8PR_Pos) /**< \brief (MATRIX_PRBS7) Master 8 Priority */ +#define MATRIX_PRBS7_M8PR(value) ((MATRIX_PRBS7_M8PR_Msk & ((value) << MATRIX_PRBS7_M8PR_Pos))) +/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */ +#define MATRIX_PRAS8_M0PR_Pos 0 +#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */ +#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos))) +#define MATRIX_PRAS8_M1PR_Pos 4 +#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */ +#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos))) +#define MATRIX_PRAS8_M2PR_Pos 8 +#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */ +#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos))) +#define MATRIX_PRAS8_M3PR_Pos 12 +#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */ +#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos))) +#define MATRIX_PRAS8_M4PR_Pos 16 +#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */ +#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos))) +#define MATRIX_PRAS8_M5PR_Pos 20 +#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos) /**< \brief (MATRIX_PRAS8) Master 5 Priority */ +#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos))) +#define MATRIX_PRAS8_M6PR_Pos 24 +#define MATRIX_PRAS8_M6PR_Msk (0x3u << MATRIX_PRAS8_M6PR_Pos) /**< \brief (MATRIX_PRAS8) Master 6 Priority */ +#define MATRIX_PRAS8_M6PR(value) ((MATRIX_PRAS8_M6PR_Msk & ((value) << MATRIX_PRAS8_M6PR_Pos))) +/* -------- MATRIX_PRBS8 : (MATRIX Offset: 0x00C4) Priority Register B for Slave 8 -------- */ +#define MATRIX_PRBS8_M8PR_Pos 0 +#define MATRIX_PRBS8_M8PR_Msk (0x3u << MATRIX_PRBS8_M8PR_Pos) /**< \brief (MATRIX_PRBS8) Master 8 Priority */ +#define MATRIX_PRBS8_M8PR(value) ((MATRIX_PRBS8_M8PR_Msk & ((value) << MATRIX_PRBS8_M8PR_Pos))) +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */ +#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */ +#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */ +#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */ +#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */ +#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */ +#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */ +#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 */ +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration Register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /**< \brief (CCFG_SMCNFCS) SDRAM Enable */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_MATRIX_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_pio.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_pio.h new file mode 100644 index 0000000000..690fdfe227 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_pio.h @@ -0,0 +1,1711 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_PIO_COMPONENT_ +#define _SAMS70_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + __I uint32_t Reserved3[1]; + __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + __I uint32_t Reserved4[1]; + __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + __I uint32_t Reserved6[2]; + __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + __I uint32_t Reserved7[1]; + __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + __I uint32_t Reserved8[1]; + __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + __I uint32_t Reserved9[1]; + __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + __I uint32_t Reserved10[1]; + __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + __I uint32_t Reserved11[1]; + __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved12[5]; + __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + __I uint32_t Reserved13[5]; + __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0118) I/O Drive Register */ + __I uint32_t Reserved14[13]; + __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x0150) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x0164) Parallel Capture Reception Holding Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filter Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-drive Enable */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-drive Disable */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-drive Status */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) IO Line Index */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +/* -------- PIO_DRIVER : (PIO Offset: 0x0118) I/O Drive Register -------- */ +#define PIO_DRIVER_LINE0 (0x1u << 0) /**< \brief (PIO_DRIVER) Drive of PIO Line 0 */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (0x1u << 0) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1 (0x1u << 1) /**< \brief (PIO_DRIVER) Drive of PIO Line 1 */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (0x0u << 1) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (0x1u << 1) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2 (0x1u << 2) /**< \brief (PIO_DRIVER) Drive of PIO Line 2 */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (0x1u << 2) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3 (0x1u << 3) /**< \brief (PIO_DRIVER) Drive of PIO Line 3 */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (0x0u << 3) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (0x1u << 3) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4 (0x1u << 4) /**< \brief (PIO_DRIVER) Drive of PIO Line 4 */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (0x1u << 4) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5 (0x1u << 5) /**< \brief (PIO_DRIVER) Drive of PIO Line 5 */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (0x0u << 5) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (0x1u << 5) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6 (0x1u << 6) /**< \brief (PIO_DRIVER) Drive of PIO Line 6 */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (0x1u << 6) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7 (0x1u << 7) /**< \brief (PIO_DRIVER) Drive of PIO Line 7 */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (0x0u << 7) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (0x1u << 7) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8 (0x1u << 8) /**< \brief (PIO_DRIVER) Drive of PIO Line 8 */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (0x1u << 8) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9 (0x1u << 9) /**< \brief (PIO_DRIVER) Drive of PIO Line 9 */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (0x0u << 9) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (0x1u << 9) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10 (0x1u << 10) /**< \brief (PIO_DRIVER) Drive of PIO Line 10 */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (0x1u << 10) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11 (0x1u << 11) /**< \brief (PIO_DRIVER) Drive of PIO Line 11 */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (0x0u << 11) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (0x1u << 11) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12 (0x1u << 12) /**< \brief (PIO_DRIVER) Drive of PIO Line 12 */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (0x1u << 12) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13 (0x1u << 13) /**< \brief (PIO_DRIVER) Drive of PIO Line 13 */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (0x0u << 13) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (0x1u << 13) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14 (0x1u << 14) /**< \brief (PIO_DRIVER) Drive of PIO Line 14 */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (0x1u << 14) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15 (0x1u << 15) /**< \brief (PIO_DRIVER) Drive of PIO Line 15 */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (0x0u << 15) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (0x1u << 15) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16 (0x1u << 16) /**< \brief (PIO_DRIVER) Drive of PIO Line 16 */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (0x1u << 16) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17 (0x1u << 17) /**< \brief (PIO_DRIVER) Drive of PIO Line 17 */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (0x0u << 17) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (0x1u << 17) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18 (0x1u << 18) /**< \brief (PIO_DRIVER) Drive of PIO Line 18 */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (0x1u << 18) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19 (0x1u << 19) /**< \brief (PIO_DRIVER) Drive of PIO Line 19 */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (0x0u << 19) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (0x1u << 19) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20 (0x1u << 20) /**< \brief (PIO_DRIVER) Drive of PIO Line 20 */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (0x1u << 20) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21 (0x1u << 21) /**< \brief (PIO_DRIVER) Drive of PIO Line 21 */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (0x0u << 21) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (0x1u << 21) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22 (0x1u << 22) /**< \brief (PIO_DRIVER) Drive of PIO Line 22 */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (0x1u << 22) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23 (0x1u << 23) /**< \brief (PIO_DRIVER) Drive of PIO Line 23 */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (0x0u << 23) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (0x1u << 23) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24 (0x1u << 24) /**< \brief (PIO_DRIVER) Drive of PIO Line 24 */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (0x1u << 24) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25 (0x1u << 25) /**< \brief (PIO_DRIVER) Drive of PIO Line 25 */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (0x0u << 25) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (0x1u << 25) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26 (0x1u << 26) /**< \brief (PIO_DRIVER) Drive of PIO Line 26 */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (0x1u << 26) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27 (0x1u << 27) /**< \brief (PIO_DRIVER) Drive of PIO Line 27 */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (0x0u << 27) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (0x1u << 27) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28 (0x1u << 28) /**< \brief (PIO_DRIVER) Drive of PIO Line 28 */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (0x1u << 28) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29 (0x1u << 29) /**< \brief (PIO_DRIVER) Drive of PIO Line 29 */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (0x0u << 29) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (0x1u << 29) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30 (0x1u << 30) /**< \brief (PIO_DRIVER) Drive of PIO Line 30 */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (0x1u << 30) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31 (0x1u << 31) /**< \brief (PIO_DRIVER) Drive of PIO Line 31 */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (0x0u << 31) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (0x1u << 31) /**< \brief (PIO_DRIVER) Highest drive */ +/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE_Pos 4 +#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos))) +#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error */ +/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos 0 +#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data */ + +/*@}*/ + + +#endif /* _SAMS70_PIO_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_pmc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_pmc.h new file mode 100644 index 0000000000..37f413b90c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_pmc.h @@ -0,0 +1,786 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_PMC_COMPONENT_ +#define _SAMS70_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t PMC_PCK0; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + __IO uint32_t PMC_PCK1; /**< \brief (Pmc Offset: 0x0044) Programmable Clock 1 Register */ + __IO uint32_t PMC_PCK2; /**< \brief (Pmc Offset: 0x0048) Programmable Clock 2 Register */ + __IO uint32_t PMC_PCK3; /**< \brief (Pmc Offset: 0x004C) Programmable Clock 3 Register */ + __IO uint32_t PMC_PCK4; /**< \brief (Pmc Offset: 0x0050) Programmable Clock 4 Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PMC_PCK6; /**< \brief (Pmc Offset: 0x0058) Programmable Clock 6 Register */ + __I uint32_t Reserved6[1]; + __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + __I uint32_t Reserved7[26]; + __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved8[5]; + __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 */ + __I uint32_t Reserved9[3]; + __IO uint32_t PMC_PMMR; /**< \brief (Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register */ + __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_USBCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB FS Clock */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */ +#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */ +#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_USBCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB FS Clock */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */ +#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */ +#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_USBCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB FS Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */ +#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */ +#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command (Write-only) */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) 4/8/12 MHz On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) 4/8/12 MHz RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos))) +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Clock Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */ +#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ +#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front End Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos))) +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos))) +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_MDIV_Pos 8 +#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */ +#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos))) +#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK0 : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK0_CSS_Pos 0 +#define PMC_PCK0_CSS_Msk (0x7u << PMC_PCK0_CSS_Pos) /**< \brief (PMC_PCK0) Master Clock Source Selection */ +#define PMC_PCK0_CSS(value) ((PMC_PCK0_CSS_Msk & ((value) << PMC_PCK0_CSS_Pos))) +#define PMC_PCK0_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK0) Slow Clock is selected */ +#define PMC_PCK0_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK0) Main Clock is selected */ +#define PMC_PCK0_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK0) PLLA Clock is selected */ +#define PMC_PCK0_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK0) Divided UPLL Clock is selected */ +#define PMC_PCK0_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK0) Master Clock is selected */ +#define PMC_PCK0_PRES_Pos 4 +#define PMC_PCK0_PRES_Msk (0xffu << PMC_PCK0_PRES_Pos) /**< \brief (PMC_PCK0) Programmable Clock Prescaler */ +#define PMC_PCK0_PRES(value) ((PMC_PCK0_PRES_Msk & ((value) << PMC_PCK0_PRES_Pos))) +/* -------- PMC_PCK1 : (PMC Offset: 0x0044) Programmable Clock 1 Register -------- */ +#define PMC_PCK1_CSS_Pos 0 +#define PMC_PCK1_CSS_Msk (0x7u << PMC_PCK1_CSS_Pos) /**< \brief (PMC_PCK1) Master Clock Source Selection */ +#define PMC_PCK1_CSS(value) ((PMC_PCK1_CSS_Msk & ((value) << PMC_PCK1_CSS_Pos))) +#define PMC_PCK1_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK1) Slow Clock is selected */ +#define PMC_PCK1_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK1) Main Clock is selected */ +#define PMC_PCK1_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK1) PLLA Clock is selected */ +#define PMC_PCK1_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK1) Divided UPLL Clock is selected */ +#define PMC_PCK1_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK1) Master Clock is selected */ +#define PMC_PCK1_PRES_Pos 4 +#define PMC_PCK1_PRES_Msk (0xffu << PMC_PCK1_PRES_Pos) /**< \brief (PMC_PCK1) Programmable Clock Prescaler */ +#define PMC_PCK1_PRES(value) ((PMC_PCK1_PRES_Msk & ((value) << PMC_PCK1_PRES_Pos))) +/* -------- PMC_PCK2 : (PMC Offset: 0x0048) Programmable Clock 2 Register -------- */ +#define PMC_PCK2_CSS_Pos 0 +#define PMC_PCK2_CSS_Msk (0x7u << PMC_PCK2_CSS_Pos) /**< \brief (PMC_PCK2) Master Clock Source Selection */ +#define PMC_PCK2_CSS(value) ((PMC_PCK2_CSS_Msk & ((value) << PMC_PCK2_CSS_Pos))) +#define PMC_PCK2_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK2) Slow Clock is selected */ +#define PMC_PCK2_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK2) Main Clock is selected */ +#define PMC_PCK2_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK2) PLLA Clock is selected */ +#define PMC_PCK2_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK2) Divided UPLL Clock is selected */ +#define PMC_PCK2_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK2) Master Clock is selected */ +#define PMC_PCK2_PRES_Pos 4 +#define PMC_PCK2_PRES_Msk (0xffu << PMC_PCK2_PRES_Pos) /**< \brief (PMC_PCK2) Programmable Clock Prescaler */ +#define PMC_PCK2_PRES(value) ((PMC_PCK2_PRES_Msk & ((value) << PMC_PCK2_PRES_Pos))) +/* -------- PMC_PCK3 : (PMC Offset: 0x004C) Programmable Clock 3 Register -------- */ +#define PMC_PCK3_CSS_Pos 0 +#define PMC_PCK3_CSS_Msk (0x7u << PMC_PCK3_CSS_Pos) /**< \brief (PMC_PCK3) Master Clock Source Selection */ +#define PMC_PCK3_CSS(value) ((PMC_PCK3_CSS_Msk & ((value) << PMC_PCK3_CSS_Pos))) +#define PMC_PCK3_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK3) Slow Clock is selected */ +#define PMC_PCK3_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK3) Main Clock is selected */ +#define PMC_PCK3_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK3) PLLA Clock is selected */ +#define PMC_PCK3_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK3) Divided UPLL Clock is selected */ +#define PMC_PCK3_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK3) Master Clock is selected */ +#define PMC_PCK3_PRES_Pos 4 +#define PMC_PCK3_PRES_Msk (0xffu << PMC_PCK3_PRES_Pos) /**< \brief (PMC_PCK3) Programmable Clock Prescaler */ +#define PMC_PCK3_PRES(value) ((PMC_PCK3_PRES_Msk & ((value) << PMC_PCK3_PRES_Pos))) +/* -------- PMC_PCK4 : (PMC Offset: 0x0050) Programmable Clock 4 Register -------- */ +#define PMC_PCK4_CSS_Pos 0 +#define PMC_PCK4_CSS_Msk (0x7u << PMC_PCK4_CSS_Pos) /**< \brief (PMC_PCK4) Master Clock Source Selection */ +#define PMC_PCK4_CSS(value) ((PMC_PCK4_CSS_Msk & ((value) << PMC_PCK4_CSS_Pos))) +#define PMC_PCK4_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK4) Slow Clock is selected */ +#define PMC_PCK4_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK4) Main Clock is selected */ +#define PMC_PCK4_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK4) PLLA Clock is selected */ +#define PMC_PCK4_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK4) Divided UPLL Clock is selected */ +#define PMC_PCK4_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK4) Master Clock is selected */ +#define PMC_PCK4_PRES_Pos 4 +#define PMC_PCK4_PRES_Msk (0xffu << PMC_PCK4_PRES_Pos) /**< \brief (PMC_PCK4) Programmable Clock Prescaler */ +#define PMC_PCK4_PRES(value) ((PMC_PCK4_PRES_Msk & ((value) << PMC_PCK4_PRES_Pos))) +/* -------- PMC_PCK6 : (PMC Offset: 0x0058) Programmable Clock 6 Register -------- */ +#define PMC_PCK6_CSS_Pos 0 +#define PMC_PCK6_CSS_Msk (0x7u << PMC_PCK6_CSS_Pos) /**< \brief (PMC_PCK6) Master Clock Source Selection */ +#define PMC_PCK6_CSS(value) ((PMC_PCK6_CSS_Msk & ((value) << PMC_PCK6_CSS_Pos))) +#define PMC_PCK6_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK6) Slow Clock is selected */ +#define PMC_PCK6_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK6) Main Clock is selected */ +#define PMC_PCK6_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK6) PLLA Clock is selected */ +#define PMC_PCK6_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK6) Divided UPLL Clock is selected */ +#define PMC_PCK6_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK6) Master Clock is selected */ +#define PMC_PCK6_PRES_Pos 4 +#define PMC_PCK6_PRES_Msk (0xffu << PMC_PCK6_PRES_Pos) /**< \brief (PMC_PCK6) Programmable Clock Prescaler */ +#define PMC_PCK6_PRES(value) ((PMC_PCK6_PRES_Msk & ((value) << PMC_PCK6_PRES_Pos))) +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) 3 to 20 MHz Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */ +#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */ +#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */ +#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) 4/8/12 MHz RC Oscillator Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) 3 to 20 MHz Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */ +#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */ +#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */ +#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) 4/8/12 MHz RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) 3 to 20 MHz Crystal Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Source Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Clock Source Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) 4/8/12 MHz RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) 3 to 20 MHz Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask */ +#define PMC_IMR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask */ +#define PMC_IMR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask */ +#define PMC_IMR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) 4/8/12 MHz RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */ +#define PMC_FSMR_FLPM_Pos 21 +#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */ +#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos))) +#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 1 */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 2 */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 3 */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 4 */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 5 */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 6 */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 7 */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 8 */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 9 */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 10 */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 11 */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 12 */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 13 */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 14 */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 15 */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos 0 +#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ +#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos))) +#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */ +#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos 0 +#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) +#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL8_Pos 8 +#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) +#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL12_Pos 16 +#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */ +#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) +#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */ +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */ +#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */ +#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */ +#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */ +#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */ +#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */ +#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */ +#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */ +#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */ +#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */ +#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */ +#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */ +#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */ +#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */ +#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */ +#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */ +#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */ +#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */ +#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */ +#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */ +#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */ +#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */ +#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */ +#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */ +#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */ +#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */ +#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */ +#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */ +#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */ +/* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */ +#define PMC_PMMR_PLLA_MMAX_Pos 0 +#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) /**< \brief (PMC_PMMR) PLLA Maximum Allowed Multiplier Value */ +#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos))) +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */ +#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */ +#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */ +#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */ +#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */ +#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */ +#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */ +#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */ +#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */ +#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */ +#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */ +#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */ +#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */ +#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */ +#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */ +#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */ +#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */ +#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */ +#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */ +#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */ +#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */ +#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */ +#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */ +#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */ +#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */ +#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */ +#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status */ +#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status */ +#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status */ +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */ +#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */ + +/*@}*/ + + +#endif /* _SAMS70_PMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_pwm.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_pwm.h new file mode 100644 index 0000000000..3cfbfb6ec8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_pwm.h @@ -0,0 +1,667 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_PWM_COMPONENT_ +#define _SAMS70_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief Pwm hardware registers */ +#define PWMCH_NUM_NUMBER 4 +typedef struct { + __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */ + __I uint32_t Reserved5[8]; + __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */ + __I uint32_t Reserved6[17]; + __IO uint32_t PWM_CMPV0; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD0; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM0; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD0; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ + __IO uint32_t PWM_CMPV1; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ + __O uint32_t PWM_CMPVUPD1; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ + __IO uint32_t PWM_CMPM1; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ + __O uint32_t PWM_CMPMUPD1; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ + __IO uint32_t PWM_CMPV2; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ + __O uint32_t PWM_CMPVUPD2; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ + __IO uint32_t PWM_CMPM2; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ + __O uint32_t PWM_CMPMUPD2; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ + __IO uint32_t PWM_CMPV3; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ + __O uint32_t PWM_CMPVUPD3; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ + __IO uint32_t PWM_CMPM3; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ + __O uint32_t PWM_CMPMUPD3; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ + __IO uint32_t PWM_CMPV4; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ + __O uint32_t PWM_CMPVUPD4; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ + __IO uint32_t PWM_CMPM4; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ + __O uint32_t PWM_CMPMUPD4; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ + __IO uint32_t PWM_CMPV5; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ + __O uint32_t PWM_CMPVUPD5; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ + __IO uint32_t PWM_CMPM5; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ + __O uint32_t PWM_CMPMUPD5; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ + __IO uint32_t PWM_CMPV6; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ + __O uint32_t PWM_CMPVUPD6; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ + __IO uint32_t PWM_CMPM6; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ + __O uint32_t PWM_CMPMUPD6; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ + __IO uint32_t PWM_CMPV7; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ + __O uint32_t PWM_CMPVUPD7; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ + __IO uint32_t PWM_CMPM7; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ + __O uint32_t PWM_CMPMUPD7; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ + __I uint32_t Reserved7[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ + __I uint32_t Reserved8[96]; + __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint32_t Reserved9[7]; + __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint32_t Reserved10[2]; + __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint32_t Reserved11[3]; + __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint32_t Reserved12[2]; + __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint32_t Reserved13[3]; + __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Controller Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Controller Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */ +#define PWM_DMAR_DMADUTY_Pos 0 +#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */ +#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */ +/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */ +#define PWM_SSPR_SPRD_Pos 0 +#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */ +#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) +#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */ +/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */ +#define PWM_SSPUP_SPRDUP_Pos 0 +#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */ +#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */ +#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */ +#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */ +#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */ +#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */ +#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */ +#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */ +#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */ +#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */ +#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */ +#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */ +#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */ +#define PWM_ETRG1_MAXCNT_Pos 0 +#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */ +#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos))) +#define PWM_ETRG1_TRGMODE_Pos 24 +#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */ +#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos))) +#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */ +#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */ +#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */ +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#define PWM_LEBR1_LEBDELAY_Pos 0 +#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos))) +#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */ +#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */ +#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */ +#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */ +#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */ +#define PWM_ETRG2_MAXCNT_Pos 0 +#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */ +#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos))) +#define PWM_ETRG2_TRGMODE_Pos 24 +#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */ +#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos))) +#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */ +#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */ +#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */ +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#define PWM_LEBR2_LEBDELAY_Pos 0 +#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos))) +#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */ +#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */ +#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */ +#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */ +#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */ + +/*@}*/ + + +#endif /* _SAMS70_PWM_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h new file mode 100644 index 0000000000..5cf18bc84f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h @@ -0,0 +1,216 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_QSPI_COMPONENT_ +#define _SAMS70_QSPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMS70_QSPI Quad Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Qspi hardware registers */ +typedef struct { + __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */ + __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */ + __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */ + __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */ + __I uint32_t Reserved3[39]; + __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */ +} Qspi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */ +#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */ +#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */ +#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */ +#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */ +/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */ +#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */ +#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */ +#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */ +#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_CSMODE_Pos 4 +#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */ +#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos))) +#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_NBBITS_Pos 8 +#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */ +#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos))) +#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_DLYBCT_Pos 16 +#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */ +#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos))) +#define QSPI_MR_DLYCS_Pos 24 +#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */ +#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos))) +/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */ +#define QSPI_RDR_RD_Pos 0 +#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */ +/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */ +#define QSPI_TDR_TD_Pos 0 +#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */ +#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos))) +/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */ +#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */ +#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */ +#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */ +#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */ +#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */ +#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */ +#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */ +#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */ +/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */ +#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */ +#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */ +#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */ +#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */ +#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */ +#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */ +#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */ +/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */ +#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */ +#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */ +#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */ +#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */ +#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */ +#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */ +#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */ +/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */ +#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */ +#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */ +#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */ +#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */ +#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */ +#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */ +/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */ +#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */ +#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */ +#define QSPI_SCR_SCBR_Pos 8 +#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */ +#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos))) +#define QSPI_SCR_DLYBS_Pos 16 +#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */ +#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos))) +/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */ +#define QSPI_IAR_ADDR_Pos 0 +#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */ +#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos))) +/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */ +#define QSPI_ICR_INST_Pos 0 +#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */ +#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos))) +#define QSPI_ICR_OPT_Pos 16 +#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */ +#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos))) +/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */ +#define QSPI_IFR_WIDTH_Pos 0 +#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */ +#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos))) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */ +#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */ +#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */ +#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */ +#define QSPI_IFR_OPTL_Pos 8 +#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */ +#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos))) +#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */ +#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_TFRTYP_Pos 12 +#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */ +#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos))) +#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */ +#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_NBDUM_Pos 16 +#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */ +#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos))) +/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */ +#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */ +#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */ +/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */ +#define QSPI_SKR_USRK_Pos 0 +#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */ +#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos))) +/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */ +#define QSPI_WPMR_WPKEY_Pos 8 +#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */ +#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos))) +#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */ +#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */ +#define QSPI_WPSR_WPVSRC_Pos 8 +#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_QSPI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_rstc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rstc.h new file mode 100644 index 0000000000..75a8b6cb5e --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rstc.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_RSTC_COMPONENT_ +#define _SAMS70_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) +#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMS70_RSTC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_rswdt.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rswdt.h new file mode 100644 index 0000000000..9f1247b865 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rswdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_RSWDT_COMPONENT_ +#define _SAMS70_RSWDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMS70_RSWDT Reinforced Safety Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rswdt hardware registers */ +typedef struct { + __O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */ + __IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */ + __I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */ +} Rswdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */ +#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */ +#define RSWDT_CR_KEY_Pos 24 +#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */ +#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) +#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */ +#define RSWDT_MR_WDV_Pos 0 +#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */ +#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) +#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */ +#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */ +#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */ +#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */ +#define RSWDT_MR_ALLONES_Pos 16 +#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */ +#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))) +#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */ +#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */ +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */ +#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */ + +/*@}*/ + + +#endif /* _SAMS70_RSWDT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_rtc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rtc.h new file mode 100644 index 0000000000..c4829bf588 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rtc.h @@ -0,0 +1,234 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_RTC_COMPONENT_ +#define _SAMS70_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAMS70_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ + __I uint32_t Reserved1[45]; + __IO uint32_t RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos))) +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos))) +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ +#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ +#define RTC_MR_CORRECTION_Pos 8 +#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ +#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) +#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ +#define RTC_MR_OUT0_Pos 16 +#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */ +#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos))) +#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_Pos 20 +#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */ +#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos))) +#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_THIGH_Pos 24 +#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */ +#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos))) +#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */ +#define RTC_MR_TPERIOD_Pos 28 +#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */ +#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos))) +#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ +#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ +/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */ +#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protection Enable */ +#define RTC_WPMR_WPKEY_Pos 8 +#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protection Key */ +#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos))) +#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMS70_RTC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_rtt.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rtt.h new file mode 100644 index 0000000000..ac0e7dfb15 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rtt.h @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_RTT_COMPONENT_ +#define _SAMS70_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAMS70_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ +#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status (cleared on read) */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status (cleared on read) */ + +/*@}*/ + + +#endif /* _SAMS70_RTT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_sdramc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_sdramc.h new file mode 100644 index 0000000000..03b275a84e --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_sdramc.h @@ -0,0 +1,173 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_SDRAMC_COMPONENT_ +#define _SAMS70_SDRAMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR SDRAM Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_SDRAMC SDRAM Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sdramc hardware registers */ +typedef struct { + __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */ + __I uint32_t Reserved1[1]; + __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< \brief (Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< \brief (Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register */ +} Sdramc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos 0 +#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */ +#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos))) +#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */ +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos 0 +#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */ +#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos))) +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos 0 +#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */ +#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos))) +#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NR_Pos 2 +#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */ +#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos))) +#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */ +#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_CAS_Pos 5 +#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */ +#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos))) +#define SDRAMC_CR_CAS_LATENCY1 (0x0u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2 (0x1u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3 (0x2u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */ +#define SDRAMC_CR_TWR_Pos 8 +#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */ +#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos))) +#define SDRAMC_CR_TRC_TRFC_Pos 12 +#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */ +#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos))) +#define SDRAMC_CR_TRP_Pos 16 +#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */ +#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos))) +#define SDRAMC_CR_TRCD_Pos 20 +#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */ +#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos))) +#define SDRAMC_CR_TRAS_Pos 24 +#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */ +#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos))) +#define SDRAMC_CR_TXSR_Pos 28 +#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */ +#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos))) +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos 0 +#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */ +#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos))) +#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_PASR_Pos 4 +#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos))) +#define SDRAMC_LPR_TCSR_Pos 8 +#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos))) +#define SDRAMC_LPR_DS_Pos 10 +#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */ +#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos))) +#define SDRAMC_LPR_TIMEOUT_Pos 12 +#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled */ +#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos))) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */ +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */ +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */ +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status (cleared on read) */ +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos 0 +#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */ +#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos))) +#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */ +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CFR1_TMRD_Pos 0 +#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos) /**< \brief (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command */ +#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos))) +#define SDRAMC_CFR1_UNAL (0x1u << 8) /**< \brief (SDRAMC_CFR1) Support Unaligned Access */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is supported. */ +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */ +#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */ +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */ +#define SDRAMC_OCMS_KEY1_KEY1_Pos 0 +#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< \brief (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */ +#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos))) +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */ +#define SDRAMC_OCMS_KEY2_KEY2_Pos 0 +#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< \brief (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */ +#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos))) + +/*@}*/ + + +#endif /* _SAMS70_SDRAMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_smc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_smc.h new file mode 100644 index 0000000000..a616e3a7b1 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_smc.h @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_SMC_COMPONENT_ +#define _SAMS70_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC MODE Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ + __I uint32_t Reserved1[16]; + __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + __I uint32_t Reserved2[22]; + __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protection Status Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) Read Mode */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) Write Mode */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos))) +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ +#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */ +#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */ +#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ +#define SMC_MODE_PS_Pos 28 +#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ +#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos))) +#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY_Pos 8 +#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protection Key */ +#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) +#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */ +#define SMC_WPSR_WPVSRC_Pos 8 +#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_SMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_spi.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_spi.h new file mode 100644 index 0000000000..f7ac02f0e9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_spi.h @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_SPI_COMPONENT_ +#define _SAMS70_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMS70_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + __I uint32_t Reserved2[41]; + __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos))) +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_SPI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_ssc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_ssc.h new file mode 100644 index 0000000000..2aa87c0f46 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_ssc.h @@ -0,0 +1,280 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_SSC_COMPONENT_ +#define _SAMS70_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + __I uint32_t Reserved2[2]; + __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved3[37]; + __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos))) +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos))) +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos))) +#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos))) +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos))) +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos))) +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos))) +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos))) +#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos))) +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos))) +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_SSC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_supc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_supc.h new file mode 100644 index 0000000000..9f60ebe2fc --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_supc.h @@ -0,0 +1,295 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_SUPC_COMPONENT_ +#define _SAMS70_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos))) +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_BKUPRETON (0x1u << 17) /**< \brief (SUPC_MR) SRAM On In Backup Mode */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP0 */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP1 */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low-power Debouncer Clear */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos))) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_LPDBC_Pos 16 +#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low-power Debouncer Period */ +#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos))) +#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 0 */ +#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 1 */ +#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 2 */ +#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 3 */ +#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 4 */ +#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 5 */ +#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 6 */ +#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 7 */ +#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 8 */ +#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 9 */ +#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 10 */ +#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 11 */ +#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 12 */ +#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 13 */ +#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 0 */ +#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 1 */ +#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 2 */ +#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 3 */ +#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 4 */ +#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 5 */ +#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 6 */ +#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 7 */ +#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 8 */ +#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 9 */ +#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 10 */ +#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 11 */ +#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 12 */ +#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 13 */ +#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status (cleared on read) */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status (cleared on read) */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status (cleared on read) */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status (cleared on read) */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */ +#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */ +#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ + +/*@}*/ + + +#endif /* _SAMS70_SUPC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_tc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_tc.h new file mode 100644 index 0000000000..3a058c97c0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_tc.h @@ -0,0 +1,346 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_TC_COMPONENT_ +#define _SAMS70_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAMS70_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ + __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ + __I uint32_t Reserved1[3]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_SBSMPLR_Pos 20 +#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ +#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))) +#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ +#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ +#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ +#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ +#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ +/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ +#define TC_RAB_RAB_Pos 0 +#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ +#define TC_EMR_TRIGSRCA_Pos 0 +#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */ +#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCB_Pos 4 +#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */ +#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). */ +#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) +#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMS70_TC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_trng.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_trng.h new file mode 100644 index 0000000000..928092bb36 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_trng.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_TRNG_COMPONENT_ +#define _SAMS70_TRNG_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR True Random Number Generator */ +/* ============================================================================= */ +/** \addtogroup SAMS70_TRNG True Random Number Generator */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Trng hardware registers */ +typedef struct { + __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */ + __I uint32_t Reserved1[3]; + __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */ + __I uint32_t Reserved2[12]; + __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */ +#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to Provide Random Values */ +#define TRNG_CR_KEY_Pos 8 +#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */ +#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))) +#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */ +/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ +/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ +/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */ +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos 0 +#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */ + +/*@}*/ + + +#endif /* _SAMS70_TRNG_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_twihs.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_twihs.h new file mode 100644 index 0000000000..a859622c92 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_twihs.h @@ -0,0 +1,250 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_TWIHS_COMPONENT_ +#define _SAMS70_TWIHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */ +/* ============================================================================= */ +/** \addtogroup SAMS70_TWIHS Two-wire Interface High Speed */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twihs hardware registers */ +typedef struct { + __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */ + __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */ + __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */ + __I uint32_t Reserved4[37]; + __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */ +} Twihs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */ +#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */ +#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */ +#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */ +#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */ +#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */ +#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */ +#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */ +#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */ +#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */ +#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */ +#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */ +#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */ +#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */ +#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */ +#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */ +#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */ +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */ +#define TWIHS_MMR_IADRSZ_Pos 8 +#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */ +#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) +#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */ +#define TWIHS_MMR_DADR_Pos 16 +#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */ +#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */ +#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */ +#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */ +#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */ +#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */ +#define TWIHS_SMR_MASK_Pos 8 +#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) +#define TWIHS_SMR_SADR_Pos 16 +#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */ +#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) +#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */ +#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */ +#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */ +#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */ +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */ +#define TWIHS_IADR_IADR_Pos 0 +#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */ +#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWIHS_CWGR_CLDIV_Pos 0 +#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */ +#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) +#define TWIHS_CWGR_CHDIV_Pos 8 +#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */ +#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) +#define TWIHS_CWGR_CKDIV_Pos 16 +#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */ +#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) +#define TWIHS_CWGR_HOLD_Pos 24 +#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */ +#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */ +#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ +#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */ +#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */ +#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */ +#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */ +#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */ +#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */ +#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */ +#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */ +#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */ +#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */ +#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */ +#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */ +#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */ +#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */ +#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL Line Value */ +#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA Line Value */ +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */ +#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */ +#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */ +#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */ +#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */ +#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */ +#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */ +#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */ +#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */ +#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */ +#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */ +#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */ +#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */ +#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */ +#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */ +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */ +#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */ +#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */ +#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */ +#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */ +#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */ +#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */ +#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */ +#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */ +#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */ +#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */ +#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */ +#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */ +#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */ +#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */ +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */ +#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */ +#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */ +#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */ +#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */ +#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */ +#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */ +#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */ +#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */ +#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */ +#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */ +#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */ +#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */ +#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */ +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */ +#define TWIHS_RHR_RXDATA_Pos 0 +#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */ +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */ +#define TWIHS_THR_TXDATA_Pos 0 +#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */ +#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */ +#define TWIHS_SMBTR_PRESC_Pos 0 +#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */ +#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) +#define TWIHS_SMBTR_TLOWS_Pos 8 +#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) +#define TWIHS_SMBTR_TLOWM_Pos 16 +#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) +#define TWIHS_SMBTR_THMAX_Pos 24 +#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */ +#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */ +#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */ +#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */ +#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */ +#define TWIHS_FILTR_THRES_Pos 8 +#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */ +#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */ +#define TWIHS_SWMR_SADR1_Pos 0 +#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */ +#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) +#define TWIHS_SWMR_SADR2_Pos 8 +#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */ +#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) +#define TWIHS_SWMR_SADR3_Pos 16 +#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */ +#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) +#define TWIHS_SWMR_DATAM_Pos 24 +#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */ +#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */ +#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */ +#define TWIHS_WPMR_WPKEY_Pos 8 +#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */ +#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) +#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */ +#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */ +#define TWIHS_WPSR_WPVSRC_Pos 8 +#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_TWIHS_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_uart.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_uart.h new file mode 100644 index 0000000000..d509699140 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_uart.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_UART_COMPONENT_ +#define _SAMS70_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMS70_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */ + __I uint32_t Reserved1[47]; + __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ +#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */ +#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */ +#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */ +#define UART_CMPR_VAL1_Pos 0 +#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */ +#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))) +#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */ +#define UART_CMPR_VAL2_Pos 16 +#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */ +#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))) +/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */ +#define UART_WPMR_WPKEY_Pos 8 +#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */ +#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))) +#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMS70_UART_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_usart.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_usart.h new file mode 100644 index 0000000000..aa666b91d8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_usart.h @@ -0,0 +1,478 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_USART_COMPONENT_ +#define _SAMS70_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMS70_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */ + __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + __I uint32_t Reserved1[5]; + __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */ + __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */ + __I uint32_t Reserved3[22]; + __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */ +#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ +#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ +#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos))) +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ +#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos))) +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */ +#define US_MR_USCLKS_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial clock (SCK) is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */ +#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos))) +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos))) +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos))) +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos))) +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */ +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ +#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ +#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ +#define US_IER_NSSE (0x1u << 19) /**< \brief (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable */ +#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ +#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ +#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ +#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ +#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ +#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ +#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ +#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ +#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */ +#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */ +#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */ +#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */ +#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */ +#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */ +#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */ +#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */ +#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */ +#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ +#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ +#define US_IDR_NSSE (0x1u << 19) /**< \brief (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable */ +#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ +#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ +#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ +#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ +#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ +#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ +#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ +#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ +#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */ +#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */ +#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */ +#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */ +#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */ +#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */ +#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */ +#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */ +#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */ +#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ +#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ +#define US_IMR_NSSE (0x1u << 19) /**< \brief (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask */ +#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ +#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ +#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ +#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ +#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ +#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ +#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ +#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ +#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */ +#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */ +#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */ +#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */ +#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */ +#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */ +#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */ +#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */ +#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */ +#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) */ +#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag (cleared on read) */ +#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag (cleared on read) */ +#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (cleared on read) */ +#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_NSSE (0x1u << 19) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_NSS (0x1u << 23) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ +#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) */ +/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +#define US_TTGR_PCYCLE_Pos 0 +#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */ +#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos))) +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) +#define US_FIDI_BETA2_Pos 0 +#define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos) /**< \brief (US_FIDI) LON BETA2 Length */ +#define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos))) +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos))) +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos))) +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ +#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) */ +/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos 0 +#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ +#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos))) +#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ +#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ +#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ +#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ +#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ +#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ +#define US_LINMR_DLC_Pos 8 +#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ +#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) +#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */ +#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */ +/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos 0 +#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ +#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) +/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */ +#define US_LINBRR_LINCD_Pos 0 +#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */ +#define US_LINBRR_LINFP_Pos 16 +#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */ +/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */ +#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */ +#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */ +#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */ +#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */ +#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */ +#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */ +#define US_LONMR_EOFS_Pos 16 +#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */ +#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos))) +/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */ +#define US_LONPR_LONPL_Pos 0 +#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */ +#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos))) +/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */ +#define US_LONDL_LONDL_Pos 0 +#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */ +#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos))) +/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */ +#define US_LONL2HDR_BLI_Pos 0 +#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */ +#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos))) +#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */ +#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */ +/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */ +#define US_LONBL_LONBL_Pos 0 +#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */ +/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */ +#define US_LONB1TX_BETA1TX_Pos 0 +#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */ +#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos))) +/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */ +#define US_LONB1RX_BETA1RX_Pos 0 +#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */ +#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos))) +/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */ +#define US_LONPRIO_PSNB_Pos 0 +#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */ +#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos))) +#define US_LONPRIO_NPS_Pos 8 +#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */ +#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos))) +/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */ +#define US_IDTTX_IDTTX_Pos 0 +#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */ +#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos))) +/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */ +#define US_IDTRX_IDTRX_Pos 0 +#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */ +#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos))) +/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */ +#define US_ICDIFF_ICDIFF_Pos 0 +#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */ +#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos))) +/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_USART_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_usbhs.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_usbhs.h new file mode 100644 index 0000000000..a9b0a838db --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_usbhs.h @@ -0,0 +1,905 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_USBHS_COMPONENT_ +#define _SAMS70_USBHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB High-Speed Interface */ +/* ============================================================================= */ +/** \addtogroup SAMS70_USBHS USB High-Speed Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UsbhsDevdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UsbhsDevdma; +/** \brief UsbhsHstdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UsbhsHstdma; +/** \brief Usbhs hardware registers */ +#define USBHSDEVDMA_NUMBER 7 +#define USBHSHSTDMA_NUMBER 7 +typedef struct { + __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + __I uint32_t Reserved2[2]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + __I uint32_t Reserved3[2]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + __I uint32_t Reserved4[2]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + __I uint32_t Reserved5[2]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + __I uint32_t Reserved6[2]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + __I uint32_t Reserved7[2]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + __I uint32_t Reserved8[50]; + UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */ + __I uint32_t Reserved9[32]; + __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */ + __I uint32_t Reserved10[52]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + __I uint32_t Reserved11[2]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */ + __I uint32_t Reserved12[2]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + __I uint32_t Reserved13[2]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */ + __I uint32_t Reserved14[2]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + __I uint32_t Reserved15[2]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + __I uint32_t Reserved16[2]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + __I uint32_t Reserved17[2]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + __I uint32_t Reserved18[2]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */ + __I uint32_t Reserved19[26]; + UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */ + __I uint32_t Reserved20[32]; + __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */ + __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */ + __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */ +} Usbhs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */ +#define USBHS_DEVCTRL_UADD_Pos 0 +#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */ +#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos))) +#define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */ +#define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */ +#define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */ +#define USBHS_DEVCTRL_SPDCONF_Pos 10 +#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */ +#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos))) +#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */ +#define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */ +#define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */ +#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */ +#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */ +/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */ +#define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */ +#define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */ +#define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */ +#define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */ +#define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */ +#define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */ +#define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */ +#define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */ +#define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */ +#define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */ +#define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */ +#define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */ +#define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */ +#define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */ +#define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */ +#define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */ +#define USBHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVISR) Endpoint 10 Interrupt */ +#define USBHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVISR) Endpoint 11 Interrupt */ +#define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */ +#define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */ +#define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */ +#define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */ +#define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */ +#define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */ +#define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */ +#define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */ +#define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */ +#define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */ +#define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */ +#define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */ +#define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */ +#define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */ +#define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */ +#define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */ +#define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */ +#define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */ +#define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */ +#define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIMR) Endpoint 10 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIMR) Endpoint 11 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */ +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */ +#define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */ +#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */ +#define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */ +#define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIDR) Endpoint 10 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIDR) Endpoint 11 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */ +#define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */ +#define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */ +#define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */ +#define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */ +#define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define USBHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIER) Endpoint 10 Interrupt Enable */ +#define USBHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIER) Endpoint 11 Interrupt Enable */ +#define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */ +#define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */ +#define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */ +#define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */ +#define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */ +#define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */ +#define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */ +#define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */ +#define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */ +#define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */ +#define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */ +#define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */ +#define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */ +#define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */ +#define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */ +#define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */ +#define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */ +#define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */ +#define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */ +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */ +#define USBHS_DEVFNUM_MFNUM_Pos 0 +#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */ +#define USBHS_DEVFNUM_FNUM_Pos 3 +#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */ +#define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */ +/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */ +#define USBHS_DEVEPTCFG_EPBK_Pos 2 +#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */ +#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos))) +#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos 4 +#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */ +#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos))) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */ +#define USBHS_DEVEPTCFG_EPTYPE_Pos 11 +#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */ +#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos))) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos 13 +#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */ +#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos))) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTISR_DTSEQ_Pos 8 +#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos 12 +#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */ +#define USBHS_DEVEPTISR_CURRBK_Pos 14 +#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */ +#define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */ +#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */ +#define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */ +#define USBHS_DEVEPTISR_BYCT_Pos 20 +#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */ +#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */ +#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */ +#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */ +#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */ +#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */ +#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */ +#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */ +#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */ +#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */ +#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */ +#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */ +#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */ +#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */ +#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */ +#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */ +#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */ +#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */ +#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */ +#define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */ +#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */ +#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */ +#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */ +#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */ +#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */ +#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */ +#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */ +#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */ +#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */ +#define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */ +#define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */ +#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */ +/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */ +#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */ +#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */ +#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */ +#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */ +#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */ +#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */ +#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */ +#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */ +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */ +#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */ +#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */ +#define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */ +#define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */ +#define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */ +#define USBHS_HSTCTRL_SPDCONF_Pos 12 +#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */ +#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos))) +#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */ +#define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */ +#define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */ +#define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */ +#define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */ +#define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */ +#define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */ +#define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */ +#define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */ +#define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */ +#define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */ +#define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */ +#define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */ +#define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */ +#define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */ +#define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */ +#define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */ +#define USBHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTISR) Pipe 10 Interrupt */ +#define USBHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTISR) Pipe 11 Interrupt */ +#define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */ +#define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */ +#define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */ +#define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */ +#define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */ +#define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */ +#define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */ +#define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */ +#define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */ +#define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */ +#define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */ +#define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIMR) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIMR) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */ +#define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIDR) Pipe 10 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIDR) Pipe 11 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */ +#define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIER) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIER) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */ +#define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */ +#define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */ +#define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */ +#define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */ +#define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */ +#define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */ +#define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */ +#define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */ +#define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */ +#define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */ +#define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */ +#define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */ +#define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */ +#define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */ +#define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */ +#define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */ +#define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */ +#define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */ +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */ +#define USBHS_HSTFNUM_MFNUM_Pos 0 +#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */ +#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos))) +#define USBHS_HSTFNUM_FNUM_Pos 3 +#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */ +#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos))) +#define USBHS_HSTFNUM_FLENHIGH_Pos 16 +#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */ +#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */ +#define USBHS_HSTADDR1_HSTADDRP0_Pos 0 +#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos))) +#define USBHS_HSTADDR1_HSTADDRP1_Pos 8 +#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos))) +#define USBHS_HSTADDR1_HSTADDRP2_Pos 16 +#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos))) +#define USBHS_HSTADDR1_HSTADDRP3_Pos 24 +#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */ +#define USBHS_HSTADDR2_HSTADDRP4_Pos 0 +#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos))) +#define USBHS_HSTADDR2_HSTADDRP5_Pos 8 +#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos))) +#define USBHS_HSTADDR2_HSTADDRP6_Pos 16 +#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos))) +#define USBHS_HSTADDR2_HSTADDRP7_Pos 24 +#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */ +#define USBHS_HSTADDR3_HSTADDRP8_Pos 0 +#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos))) +#define USBHS_HSTADDR3_HSTADDRP9_Pos 8 +#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */ +#define USBHS_HSTPIPCFG_PBK_Pos 2 +#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */ +#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos))) +#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PSIZE_Pos 4 +#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */ +#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos))) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos 8 +#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */ +#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos))) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */ +#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */ +#define USBHS_HSTPIPCFG_PTYPE_Pos 12 +#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */ +#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos))) +#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos 16 +#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */ +#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos))) +#define USBHS_HSTPIPCFG_INTFRQ_Pos 24 +#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */ +#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos))) +#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */ +#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */ +#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */ +#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */ +#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */ +#define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */ +#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */ +#define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */ +#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */ +#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */ +#define USBHS_HSTPIPISR_DTSEQ_Pos 8 +#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos 12 +#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */ +#define USBHS_HSTPIPISR_CURRBK_Pos 14 +#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */ +#define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */ +#define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */ +#define USBHS_HSTPIPISR_PBYCT_Pos 20 +#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */ +#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */ +#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */ +/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */ +#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */ +#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */ +#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */ +#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */ +#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */ +#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */ +#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */ +#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */ +#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */ +#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */ +#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */ +#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */ +#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */ +#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */ +#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */ +#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */ +#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */ +#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */ +#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */ +#define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */ +#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */ +#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */ +#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */ +#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */ +#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */ +#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */ +#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */ +/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define USBHS_HSTPIPINRQ_INRQ_Pos 0 +#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */ +#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos))) +#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */ +/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */ +#define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */ +#define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */ +#define USBHS_HSTPIPERR_COUNTER_Pos 5 +#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */ +#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos))) +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */ +#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */ +#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */ +#define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */ +#define USBHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (USBHS_CTRL) VBUS Hardware Control */ +#define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */ +#define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */ +#define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */ +#define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */ +/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */ +#define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */ +#define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBUS Request (Host mode only) */ +#define USBHS_SR_SPEED_Pos 12 +#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */ +#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */ +/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */ +#define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */ +#define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBUS Request Clear */ +/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */ +#define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */ +#define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBUS Request Set */ + +/*@}*/ + + +#endif /* _SAMS70_USBHS_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_utmi.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_utmi.h new file mode 100644 index 0000000000..b45b124527 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_utmi.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_UTMI_COMPONENT_ +#define _SAMS70_UTMI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Transmitter Interface Macrocell */ +/* ============================================================================= */ +/** \addtogroup SAMS70_UTMI USB Transmitter Interface Macrocell */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Utmi hardware registers */ +typedef struct { + __I uint32_t Reserved1[4]; + __IO uint32_t UTMI_OHCIICR; /**< \brief (Utmi Offset: 0x10) OHCI Interrupt Configuration Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t UTMI_CKTRIM; /**< \brief (Utmi Offset: 0x30) UTMI Clock Trimming Register */ +} Utmi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) OHCI Interrupt Configuration Register -------- */ +#define UTMI_OHCIICR_RES0 (0x1u << 0) /**< \brief (UTMI_OHCIICR) USB PORTx Reset */ +#define UTMI_OHCIICR_ARIE (0x1u << 4) /**< \brief (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */ +#define UTMI_OHCIICR_APPSTART (0x1u << 5) /**< \brief (UTMI_OHCIICR) Reserved */ +#define UTMI_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (UTMI_OHCIICR) USB Device Pull-up Disable */ +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) UTMI Clock Trimming Register -------- */ +#define UTMI_CKTRIM_FREQ_Pos 0 +#define UTMI_CKTRIM_FREQ_Msk (0x3u << UTMI_CKTRIM_FREQ_Pos) /**< \brief (UTMI_CKTRIM) UTMI Reference Clock Frequency */ +#define UTMI_CKTRIM_FREQ(value) ((UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos))) +#define UTMI_CKTRIM_FREQ_XTAL12 (0x0u << 0) /**< \brief (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16 (0x1u << 0) /**< \brief (UTMI_CKTRIM) 16 MHz reference clock */ + +/*@}*/ + + +#endif /* _SAMS70_UTMI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_wdt.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_wdt.h new file mode 100644 index 0000000000..28750e038e --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_wdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_WDT_COMPONENT_ +#define _SAMS70_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMS70_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */ + +/*@}*/ + + +#endif /* _SAMS70_WDT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_xdmac.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_xdmac.h new file mode 100644 index 0000000000..8a8d5893ff --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_xdmac.h @@ -0,0 +1,616 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_XDMAC_COMPONENT_ +#define _SAMS70_XDMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_XDMAC Extensible DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief XdmacChid hardware registers */ +typedef struct { + __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */ + __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */ + __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */ + __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */ + __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */ + __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */ + __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */ + __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */ + __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */ + __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */ + __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */ + __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */ + __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */ + __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */ + __I uint32_t Reserved1[2]; +} XdmacChid; +/** \brief Xdmac hardware registers */ +#define XDMACCHID_NUMBER 24 +typedef struct { + __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */ + __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */ + __I uint32_t Reserved1[3]; + XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */ +} Xdmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */ +#define XDMAC_GTYPE_NB_CH_Pos 0 +#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */ +#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) +#define XDMAC_GTYPE_FIFO_SZ_Pos 5 +#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */ +#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) +#define XDMAC_GTYPE_NB_REQ_Pos 16 +#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */ +#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */ +#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */ +#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */ +#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */ +#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */ +#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilobyte Enable */ +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */ +#define XDMAC_GWAC_PW0_Pos 0 +#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */ +#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) +#define XDMAC_GWAC_PW1_Pos 4 +#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */ +#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) +#define XDMAC_GWAC_PW2_Pos 8 +#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */ +#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) +#define XDMAC_GWAC_PW3_Pos 12 +#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */ +#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */ +#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */ +#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */ +#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */ +#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */ +#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */ +#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */ +#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */ +#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */ +#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */ +#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */ +#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */ +#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */ +#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */ +#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */ +#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */ +#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */ +#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */ +#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */ +#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */ +#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */ +#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */ +#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */ +#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */ +#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */ +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */ +#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */ +#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */ +#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */ +#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */ +#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */ +#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */ +#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */ +#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */ +#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */ +#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */ +#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */ +#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */ +#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */ +#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */ +#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */ +#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */ +#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */ +#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */ +#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */ +#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */ +#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */ +#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */ +#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */ +#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */ +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */ +#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */ +#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */ +#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */ +#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */ +#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */ +#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */ +#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */ +#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */ +#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */ +#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */ +#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */ +#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */ +#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */ +#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */ +#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */ +#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */ +#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */ +#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */ +#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */ +#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */ +#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */ +#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */ +#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */ +#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */ +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */ +#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */ +#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */ +#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */ +#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */ +#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */ +#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */ +#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */ +#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */ +#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */ +#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */ +#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */ +#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */ +#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */ +#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */ +#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */ +#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */ +#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */ +#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */ +#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */ +#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */ +#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */ +#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */ +#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */ +#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */ +/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */ +#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */ +#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */ +#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */ +#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */ +#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */ +#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */ +#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */ +#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */ +#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */ +#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */ +#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */ +#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */ +#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */ +#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */ +#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */ +#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */ +#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */ +#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */ +#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */ +#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */ +#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */ +#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */ +#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */ +#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */ +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */ +#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */ +#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */ +#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */ +#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */ +#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */ +#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */ +#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */ +#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */ +#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */ +#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */ +#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */ +#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */ +#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */ +#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */ +#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */ +#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */ +#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */ +#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */ +#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */ +#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */ +#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */ +#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */ +#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */ +#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */ +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */ +#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */ +#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */ +#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */ +#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */ +#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */ +#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */ +#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */ +#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */ +#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */ +#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */ +#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */ +#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */ +#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */ +#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */ +#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */ +#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */ +#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */ +#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */ +#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */ +#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */ +#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */ +#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */ +#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */ +#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */ +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */ +#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */ +#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */ +#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */ +#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */ +#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */ +#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */ +#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */ +#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */ +#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */ +#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */ +#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */ +#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */ +#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */ +#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */ +#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */ +#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */ +#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */ +#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */ +#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */ +#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */ +#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */ +#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */ +#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */ +#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */ +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */ +#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */ +#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */ +#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */ +#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */ +#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */ +#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */ +#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */ +#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */ +#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */ +#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */ +#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */ +#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */ +#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */ +#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */ +#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */ +#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */ +#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */ +#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */ +#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */ +#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */ +#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */ +#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */ +#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */ +#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */ +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */ +#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */ +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */ +#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */ +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */ +#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */ +#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */ +#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */ +#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */ +#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */ +#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */ +#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */ +#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */ +#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */ +#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */ +#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */ +#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */ +#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */ +#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */ +#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */ +#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */ +#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */ +#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */ +#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */ +#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */ +#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */ +#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */ +#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */ +#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */ +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */ +#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */ +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */ +#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */ +/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */ +#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */ +#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */ +#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */ +#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */ +#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */ +/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */ +#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */ +#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */ +#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */ +#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */ +#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */ +/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */ +#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */ +#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */ +#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */ +#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */ +#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */ +/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */ +#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */ +#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */ +#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */ +#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */ +#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */ +/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */ +#define XDMAC_CSA_SA_Pos 0 +#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */ +#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) +/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */ +#define XDMAC_CDA_DA_Pos 0 +#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */ +#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) +/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */ +#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */ +#define XDMAC_CNDA_NDA_Pos 2 +#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */ +#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos))) +/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */ +#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled. */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled. */ +#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDVIEW_Pos 3 +#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */ +#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) +#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */ +/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */ +#define XDMAC_CUBC_UBLEN_Pos 0 +#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */ +#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) +/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */ +#define XDMAC_CBC_BLEN_Pos 0 +#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */ +#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) +/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */ +#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */ +#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */ +#define XDMAC_CC_MBSIZE_Pos 1 +#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */ +#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) +#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */ +#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer. */ +#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer. */ +#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated. */ +#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */ +#define XDMAC_CC_CSIZE_Pos 8 +#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */ +#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) +#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_DWIDTH_Pos 11 +#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */ +#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) +#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */ +#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0. */ +#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1. */ +#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */ +#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0. */ +#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1. */ +#define XDMAC_CC_SAM_Pos 16 +#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */ +#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) +#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_Pos 18 +#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */ +#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) +#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */ +#define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */ +#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */ +#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */ +#define XDMAC_CC_PERID_Pos 24 +#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier */ +#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */ +#define XDMAC_CDS_MSP_SDS_MSP_Pos 0 +#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) +#define XDMAC_CDS_MSP_DDS_MSP_Pos 16 +#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) +/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */ +#define XDMAC_CSUS_SUBS_Pos 0 +#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */ +#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) +/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */ +#define XDMAC_CDUS_DUBS_Pos 0 +#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */ +#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) + +/*@}*/ + + +#endif /* _SAMS70_XDMAC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j19.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j19.h new file mode 100644 index 0000000000..c4d2927b7f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j19.h @@ -0,0 +1,406 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70J19_PIO_ +#define _SAMS70J19_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMS70J19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j20.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j20.h new file mode 100644 index 0000000000..0724b32eae --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j20.h @@ -0,0 +1,407 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70J20_PIO_ +#define _SAMS70J20_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMS70J20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j21.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j21.h new file mode 100644 index 0000000000..ded9233a47 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j21.h @@ -0,0 +1,407 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70J21_PIO_ +#define _SAMS70J21_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMS70J21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n19.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n19.h new file mode 100644 index 0000000000..ddb50ac46a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n19.h @@ -0,0 +1,464 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70N19_PIO_ +#define _SAMS70N19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMS70N19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n20.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n20.h new file mode 100644 index 0000000000..1f71c5270d --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n20.h @@ -0,0 +1,463 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70N20_PIO_ +#define _SAMS70N20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMS70N20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n21.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n21.h new file mode 100644 index 0000000000..9337105295 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n21.h @@ -0,0 +1,463 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70N21_PIO_ +#define _SAMS70N21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMS70N21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q19.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q19.h new file mode 100644 index 0000000000..a09aeb8038 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q19.h @@ -0,0 +1,637 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70Q19_PIO_ +#define _SAMS70Q19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMS70Q19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q20.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q20.h new file mode 100644 index 0000000000..21085a77c8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q20.h @@ -0,0 +1,637 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70Q20_PIO_ +#define _SAMS70Q20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMS70Q20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q21.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q21.h new file mode 100644 index 0000000000..f6a8772012 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q21.h @@ -0,0 +1,637 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70Q21_PIO_ +#define _SAMS70Q21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMS70Q21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70.h new file mode 100644 index 0000000000..19360d766a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70.h @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_ +#define _SAMS70_ + +#if defined __SAMS70J19__ + #include "sams70j19.h" +#elif defined __SAMS70J20__ + #include "sams70j20.h" +#elif defined __SAMS70J21__ + #include "sams70j21.h" +#elif defined __SAMS70N19__ + #include "sams70n19.h" +#elif defined __SAMS70N20__ + #include "sams70n20.h" +#elif defined __SAMS70N21__ + #include "sams70n21.h" +#elif defined __SAMS70Q19__ + #include "sams70q19.h" +#elif defined __SAMS70Q20__ + #include "sams70q20.h" +#elif defined __SAMS70Q21__ + #include "sams70q21.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAMS70_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70j19.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70j19.h new file mode 100644 index 0000000000..82e2d7f8e0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70j19.h @@ -0,0 +1,610 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70J19_ +#define _SAMS70J19_ + +/** \addtogroup SAMS70J19_definitions SAMS70J19 definitions + This file defines all structures and symbols for SAMS70J19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70J19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70J19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70J19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70J19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70J19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70J19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70J19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70J19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70J19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70J19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70J19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70J19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMS70J19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70J19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70J19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70J19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMS70J19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70J19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70J19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70J19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70J19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70J19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70J19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70J19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMS70J19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70J20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70J19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70J19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70J19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70J19 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70J19 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMS70J19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70J19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70J19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70J19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70J19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMS70J19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70J19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70J19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70J19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70J19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70J19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70J19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70J19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMS70J19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70J19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70J19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70J19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70J19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70J19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70J19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70J19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70J19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70J19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70j19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA11D0A00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70J19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70j20.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70j20.h new file mode 100644 index 0000000000..e9f40dd5eb --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70j20.h @@ -0,0 +1,610 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70J20_ +#define _SAMS70J20_ + +/** \addtogroup SAMS70J20_definitions SAMS70J20 definitions + This file defines all structures and symbols for SAMS70J20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70J20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70J20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70J20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70J20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70J20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70J20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70J20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70J20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70J20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70J20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70J20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70J20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMS70J20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70J20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70J20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70J20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMS70J20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70J20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70J20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70J20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70J20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70J20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70J20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70J20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMS70J20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70J20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70J20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70J20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70J20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70J20 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70J20 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMS70J20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70J20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70J20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70J20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70J20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMS70J20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70J20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70J20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70J20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70J20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70J20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70J20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70J20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMS70J20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70J20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70J20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70J20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70J20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70J20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70J20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70J20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70J20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70J20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70j20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1120C00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70J20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70j21.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70j21.h new file mode 100644 index 0000000000..db2dbb90a2 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70j21.h @@ -0,0 +1,610 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70J21_ +#define _SAMS70J21_ + +/** \addtogroup SAMS70J21_definitions SAMS70J21 definitions + This file defines all structures and symbols for SAMS70J21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70J21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70J21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70J21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70J21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70J21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70J21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70J21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70J21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70J21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70J21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70J21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70J21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMS70J21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70J21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70J21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70J21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMS70J21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70J21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70J21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70J21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70J21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70J21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70J21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70J21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMS70J21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70J21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70J21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70J21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70J21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70J21 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70J21 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMS70J21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70J21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70J21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70J21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70J21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMS70J21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70J21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70J21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70J21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70J21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70J21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70J21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70J21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMS70J21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70J21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70J21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70J21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70J21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70J21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70J21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70J21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70J21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70J21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70j21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1120E00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70J21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70n19.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70n19.h new file mode 100644 index 0000000000..8a810f1619 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70n19.h @@ -0,0 +1,616 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70N19_ +#define _SAMS70N19_ + +/** \addtogroup SAMS70N19_definitions SAMS70N19 definitions + This file defines all structures and symbols for SAMS70N19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70N19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70N19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70N19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70N19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70N19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70N19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70N19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70N19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70N19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70N19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70N19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70N19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMS70N19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70N19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70N19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70N19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMS70N19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70N19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70N19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70N19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70N19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70N19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70N19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70N19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMS70N19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70N19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70N19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70N19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70N19 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70N19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMS70N19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMS70N19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70N19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70N19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70N19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70N19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMS70N19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70N19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70N19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70N19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70N19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70N19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70N19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70N19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMS70N19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70N19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70N19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70N19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70N19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70N19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70N19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70N19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70N19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70N19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70n19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA11D0A00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70N19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70n20.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70n20.h new file mode 100644 index 0000000000..f95b970e67 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70n20.h @@ -0,0 +1,616 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70N20_ +#define _SAMS70N20_ + +/** \addtogroup SAMS70N20_definitions SAMS70N20 definitions + This file defines all structures and symbols for SAMS70N20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70N20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70N20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70N20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70N20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70N20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70N20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70N20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70N20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70N20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70N20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70N20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70N20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMS70N20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70N20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70N20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70N20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMS70N20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70N20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70N20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70N20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70N20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70N20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70N20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70N20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMS70N20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70N20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70N20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70N20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70N20 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70N20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMS70N20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMS70N20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70N20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70N20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70N20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70N20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMS70N20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70N20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70N20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70N20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70N20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70N20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70N20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70N20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMS70N20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70N20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70N20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70N20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70N20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70N20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70N20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70N20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70N20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70N20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70n20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1120C00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70N20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70n21.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70n21.h new file mode 100644 index 0000000000..61170b4d00 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70n21.h @@ -0,0 +1,616 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70N21_ +#define _SAMS70N21_ + +/** \addtogroup SAMS70N21_definitions SAMS70N21 definitions + This file defines all structures and symbols for SAMS70N21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70N21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70N21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70N21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70N21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70N21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70N21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70N21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70N21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70N21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70N21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70N21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70N21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMS70N21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70N21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70N21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70N21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMS70N21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70N21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70N21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70N21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70N21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70N21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70N21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70N21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMS70N21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70N21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70N21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70N21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70N21 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70N21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMS70N21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMS70N21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70N21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70N21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70N21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70N21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMS70N21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70N21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70N21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70N21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70N21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70N21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70N21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70N21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMS70N21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70N21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70N21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70N21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70N21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70N21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70N21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70N21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70N21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70N21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70n21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1120E00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70N21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70q19.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70q19.h new file mode 100644 index 0000000000..67d465f8ce --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70q19.h @@ -0,0 +1,664 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70Q19_ +#define _SAMS70Q19_ + +/** \addtogroup SAMS70Q19_definitions SAMS70Q19 definitions + This file defines all structures and symbols for SAMS70Q19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70Q19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70Q19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70Q19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70Q19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70Q19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70Q19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70Q19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70Q19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70Q19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70Q19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70Q19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70Q19 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMS70Q19 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMS70Q19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70Q19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70Q19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70Q19 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMS70Q19 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMS70Q19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70Q19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70Q19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70Q19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70Q19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70Q19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70Q19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70Q19 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMS70Q19 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMS70Q19 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMS70Q19 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMS70Q19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70Q19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70Q19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70Q19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70Q19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70Q19 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70Q19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMS70Q19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMS70Q19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70Q19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70Q19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70Q19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70Q19 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMS70Q19 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMS70Q19 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMS70Q19 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMS70Q19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70Q19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70Q19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70Q19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70Q19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70Q19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70Q19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70Q19 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMS70Q19 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMS70Q19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70Q19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70Q19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70Q19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70Q19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70Q19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70Q19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70Q19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70Q19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70Q19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70q19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA11D0A00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70Q19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70q20.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70q20.h new file mode 100644 index 0000000000..46c034cbab --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70q20.h @@ -0,0 +1,664 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70Q20_ +#define _SAMS70Q20_ + +/** \addtogroup SAMS70Q20_definitions SAMS70Q20 definitions + This file defines all structures and symbols for SAMS70Q20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70Q20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70Q20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70Q20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70Q20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70Q20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70Q20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70Q20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70Q20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70Q20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70Q20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70Q20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70Q20 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMS70Q20 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMS70Q20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70Q20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70Q20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70Q20 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMS70Q20 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMS70Q20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70Q20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70Q20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70Q20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70Q20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70Q20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70Q20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70Q20 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMS70Q20 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMS70Q20 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMS70Q20 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMS70Q20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70Q20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70Q20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70Q20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70Q20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70Q20 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70Q20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMS70Q20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMS70Q20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70Q20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70Q20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70Q20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70Q20 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMS70Q20 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMS70Q20 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMS70Q20 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMS70Q20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70Q20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70Q20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70Q20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70Q20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70Q20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70Q20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70Q20 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMS70Q20 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMS70Q20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70Q20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70Q20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70Q20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70Q20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70Q20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70Q20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70Q20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70Q20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70Q20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70q20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1120C00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70Q20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70q21.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70q21.h new file mode 100644 index 0000000000..1528f4139f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70q21.h @@ -0,0 +1,664 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70Q21_ +#define _SAMS70Q21_ + +/** \addtogroup SAMS70Q21_definitions SAMS70Q21 definitions + This file defines all structures and symbols for SAMS70Q21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70Q21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70Q21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70Q21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70Q21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70Q21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70Q21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70Q21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70Q21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70Q21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70Q21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70Q21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70Q21 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMS70Q21 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMS70Q21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70Q21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70Q21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70Q21 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMS70Q21 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMS70Q21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70Q21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70Q21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70Q21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70Q21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70Q21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70Q21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70Q21 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMS70Q21 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMS70Q21 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMS70Q21 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMS70Q21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70Q21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70Q21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70Q21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70Q21 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70Q21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMS70Q21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMS70Q21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70Q21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70Q21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70Q21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70Q21 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMS70Q21 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMS70Q21 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMS70Q21 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMS70Q21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70Q21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70Q21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70Q21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70Q21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70Q21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70Q21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70Q21 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMS70Q21 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMS70Q21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70Q21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70Q21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70Q21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70Q21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70Q21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70Q21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70Q21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70Q21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70Q21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70q21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1120E00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70Q21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/system_sams70.h b/bsps/arm/atsam/include/libchip/include/sams70/system_sams70.h new file mode 100644 index 0000000000..3e74f5c900 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/system_sams70.h @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef SYSTEM_SAMS70_H_INCLUDED +#define SYSTEM_SAMS70_H_INCLUDED +#ifdef __rtems__ +#include +#endif /* __rtems__ */ + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +#ifndef __rtems__ +void SystemInit(void); +#else /* __rtems__ */ +void ATSAM_START_SRAM_SECTION SystemInit(void); +#endif /* __rtems__ */ + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t dw_clk); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAMS70_H_INCLUDED */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_acc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_acc.h new file mode 100644 index 0000000000..593effacef --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_acc.h @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ACC_COMPONENT_ +#define _SAMV71_ACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_ACC Analog Comparator Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Acc hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[7]; + __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t ACC_VER; /**< \brief (Acc Offset: 0xFC) Version Register */ +} Acc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos 0 +#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */ +#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))) +#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_VREFP (0x1u << 0) /**< \brief (ACC_MR) Select VREFP */ +#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_Pos 4 +#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */ +#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))) +#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */ +#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_EDGETYP_Pos 9 +#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */ +#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))) +#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */ +#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */ +#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */ +#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */ +#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */ +#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */ +#define ACC_ACR_HYST_Pos 1 +#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */ +#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */ +#define ACC_WPMR_WPKEY_Pos 8 +#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */ +#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) +#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */ +#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */ +/* -------- ACC_VER : (ACC Offset: 0xFC) Version Register -------- */ +#define ACC_VER_VERSION_Pos 0 +#define ACC_VER_VERSION_Msk (0xfffu << ACC_VER_VERSION_Pos) /**< \brief (ACC_VER) Version of the Hardware Module */ +#define ACC_VER_MFN_Pos 16 +#define ACC_VER_MFN_Msk (0x7u << ACC_VER_MFN_Pos) /**< \brief (ACC_VER) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_ACC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_aes.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_aes.h new file mode 100644 index 0000000000..10680b0258 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_aes.h @@ -0,0 +1,198 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AES_COMPONENT_ +#define _SAMV71_AES_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ============================================================================= */ +/** \addtogroup SAMV71_AES Advanced Encryption Standard */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aes hardware registers */ +typedef struct { + __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */ + __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[2]; + __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */ + __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */ + __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */ + __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */ + __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */ + __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */ + __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */ + __I uint32_t Reserved2[20]; + __I uint32_t AES_VERSION; /**< \brief (Aes Offset: 0xFC) Version Register */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */ +#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */ +#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */ +#define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */ +#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */ +#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */ +#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */ +#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */ +#define AES_MR_PROCDLY_Pos 4 +#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */ +#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))) +#define AES_MR_SMOD_Pos 8 +#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */ +#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))) +#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_KEYSIZE_Pos 10 +#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */ +#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))) +#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_OPMOD_Pos 12 +#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */ +#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))) +#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */ +#define AES_MR_CFBS_Pos 16 +#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */ +#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))) +#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */ +#define AES_MR_CKEY_Pos 20 +#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Countermeasure Key */ +#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))) +#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ +#define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) Countermeasure Type 1 */ +#define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AES_MR) Countermeasure type 1 is disabled. */ +#define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Countermeasure type 1 is enabled. */ +#define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) Countermeasure Type 2 */ +#define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Countermeasure type 2 is disabled. */ +#define AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Countermeasure type 2 is enabled. */ +#define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) Countermeasure Type 3 */ +#define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Countermeasure type 3 is disabled. */ +#define AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Countermeasure type 3 is enabled. */ +#define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) Countermeasure Type 4 */ +#define AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Countermeasure type 4 is disabled. */ +#define AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Countermeasure type 4 is enabled. */ +#define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) Countermeasure Type 5 */ +#define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Countermeasure type 5 is disabled. */ +#define AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Countermeasure type 5 is enabled. */ +#define AES_MR_CMTYP6 (0x1u << 29) /**< \brief (AES_MR) Countermeasure Type 6 */ +#define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AES_MR) Countermeasure type 6 is disabled. */ +#define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AES_MR) Countermeasure type 6 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */ +#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */ +#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */ +#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */ +#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */ +#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */ +#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */ +/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ +#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_Pos 12 +#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */ +#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */ +/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */ +#define AES_KEYWR_KEYW_Pos 0 +#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */ +#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))) +/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */ +#define AES_IDATAR_IDATA_Pos 0 +#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */ +#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))) +/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */ +#define AES_ODATAR_ODATA_Pos 0 +#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */ +/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */ +#define AES_IVR_IV_Pos 0 +#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */ +#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))) +/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos 0 +#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */ +#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))) +/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos 0 +#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */ +#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))) +/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */ +#define AES_GHASHR_GHASH_Pos 0 +#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */ +#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))) +/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */ +#define AES_TAGR_TAG_Pos 0 +#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */ +/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos 0 +#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */ +/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */ +#define AES_GCMHR_H_Pos 0 +#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */ +#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))) +/* -------- AES_VERSION : (AES Offset: 0xFC) Version Register -------- */ +#define AES_VERSION_VERSION_Pos 0 +#define AES_VERSION_VERSION_Msk (0xfffu << AES_VERSION_VERSION_Pos) /**< \brief (AES_VERSION) Version of the Hardware Module */ +#define AES_VERSION_MFN_Pos 16 +#define AES_VERSION_MFN_Msk (0x7u << AES_VERSION_MFN_Pos) /**< \brief (AES_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_AES_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_afec.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_afec.h new file mode 100644 index 0000000000..b514a28b05 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_afec.h @@ -0,0 +1,490 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AFEC_COMPONENT_ +#define _SAMV71_AFEC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Front-End Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_AFEC Analog Front-End Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Afec hardware registers */ +typedef struct { + __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */ + __I uint32_t Reserved1[6]; + __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */ + __I uint32_t Reserved3[7]; + __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */ + __I uint32_t Reserved5[11]; + __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */ + __I uint32_t Reserved7[4]; + __I uint32_t AFEC_VERSION; /**< \brief (Afec Offset: 0xFC) AFEC Version Register */ +} Afec; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */ +#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */ +#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */ +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */ +#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGSEL_Pos 1 +#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos))) +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) Analog Comparator */ +#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */ +#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */ +#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */ +#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_PRESCAL_Pos 8 +#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */ +#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))) +#define AFEC_MR_STARTUP_Pos 16 +#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */ +#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos))) +#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_ONE (0x1u << 23) /**< \brief (AFEC_MR) One */ +#define AFEC_MR_TRACKTIM_Pos 24 +#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */ +#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))) +#define AFEC_MR_TRANSFER_Pos 28 +#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */ +#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))) +#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Enable */ +#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */ +#define AFEC_EMR_CMPMODE_Pos 0 +#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */ +#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos))) +#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPSEL_Pos 3 +#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */ +#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))) +#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPFILTER_Pos 12 +#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */ +#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))) +#define AFEC_EMR_RES_Pos 16 +#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */ +#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos))) +#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */ +#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_SIGNMODE_Pos 28 +#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */ +#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos))) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All channels: Signed conversions. */ +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */ +#define AFEC_SEQ1R_USCH0_Pos 0 +#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */ +#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))) +#define AFEC_SEQ1R_USCH1_Pos 4 +#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */ +#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))) +#define AFEC_SEQ1R_USCH2_Pos 8 +#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */ +#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))) +#define AFEC_SEQ1R_USCH3_Pos 12 +#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */ +#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))) +#define AFEC_SEQ1R_USCH4_Pos 16 +#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */ +#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))) +#define AFEC_SEQ1R_USCH5_Pos 20 +#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */ +#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))) +#define AFEC_SEQ1R_USCH6_Pos 24 +#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */ +#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))) +#define AFEC_SEQ1R_USCH7_Pos 28 +#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */ +#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))) +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */ +#define AFEC_SEQ2R_USCH8_Pos 0 +#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */ +#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))) +#define AFEC_SEQ2R_USCH9_Pos 4 +#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */ +#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))) +#define AFEC_SEQ2R_USCH10_Pos 8 +#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */ +#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))) +#define AFEC_SEQ2R_USCH11_Pos 12 +#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */ +#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))) +#define AFEC_SEQ2R_USCH12_Pos 16 +#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */ +#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos))) +#define AFEC_SEQ2R_USCH13_Pos 20 +#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */ +#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos))) +#define AFEC_SEQ2R_USCH14_Pos 24 +#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */ +#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos))) +#define AFEC_SEQ2R_USCH15_Pos 28 +#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */ +#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos))) +/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */ +#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */ +#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */ +#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */ +#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */ +#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */ +#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */ +#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */ +#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */ +#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */ +#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */ +#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */ +#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */ +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */ +#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */ +#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */ +#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */ +#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */ +#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */ +#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */ +#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */ +#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */ +#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */ +#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */ +#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */ +#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */ +/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */ +#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */ +#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */ +#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */ +#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */ +#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */ +#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */ +#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */ +#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */ +#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */ +#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */ +#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */ +#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */ +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */ +#define AFEC_LCDR_LDATA_Pos 0 +#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */ +#define AFEC_LCDR_CHNB_Pos 24 +#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */ +/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */ +#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */ +#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */ +#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */ +#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */ +#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */ +#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */ +#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */ +#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */ +#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */ +#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */ +#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */ +#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */ +#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */ +#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */ +#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */ +#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */ +/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */ +#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */ +#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */ +#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */ +#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */ +#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */ +#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */ +#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */ +#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */ +#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */ +#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */ +#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */ +#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */ +#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */ +#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */ +#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */ +#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */ +/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */ +#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */ +#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */ +#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */ +#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */ +#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */ +#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */ +#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */ +#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */ +#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */ +#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */ +#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */ +#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */ +#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */ +#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */ +#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */ +#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */ +/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */ +#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) */ +#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change (cleared on read) */ +/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */ +#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */ +#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */ +#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */ +#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */ +#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */ +#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */ +#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */ +#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */ +#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */ +#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */ +#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */ +#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */ +/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */ +#define AFEC_CWR_LOWTHRES_Pos 0 +#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */ +#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))) +#define AFEC_CWR_HIGHTHRES_Pos 16 +#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */ +#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))) +/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */ +#define AFEC_CGR_GAIN0_Pos 0 +#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for Channel 0 */ +#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))) +#define AFEC_CGR_GAIN1_Pos 2 +#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for Channel 1 */ +#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))) +#define AFEC_CGR_GAIN2_Pos 4 +#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for Channel 2 */ +#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))) +#define AFEC_CGR_GAIN3_Pos 6 +#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for Channel 3 */ +#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))) +#define AFEC_CGR_GAIN4_Pos 8 +#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for Channel 4 */ +#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))) +#define AFEC_CGR_GAIN5_Pos 10 +#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for Channel 5 */ +#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))) +#define AFEC_CGR_GAIN6_Pos 12 +#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for Channel 6 */ +#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))) +#define AFEC_CGR_GAIN7_Pos 14 +#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for Channel 7 */ +#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))) +#define AFEC_CGR_GAIN8_Pos 16 +#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for Channel 8 */ +#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))) +#define AFEC_CGR_GAIN9_Pos 18 +#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for Channel 9 */ +#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))) +#define AFEC_CGR_GAIN10_Pos 20 +#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for Channel 10 */ +#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))) +#define AFEC_CGR_GAIN11_Pos 22 +#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for Channel 11 */ +#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))) +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */ +#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */ +#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */ +#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */ +#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */ +#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */ +#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */ +#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */ +#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */ +#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */ +#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */ +#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */ +#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */ +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */ +#define AFEC_CSELR_CSEL_Pos 0 +#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */ +#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))) +/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */ +#define AFEC_CDR_DATA_Pos 0 +#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */ +/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */ +#define AFEC_COCR_AOFF_Pos 0 +#define AFEC_COCR_AOFF_Msk (0x3ffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */ +#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))) +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */ +#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos))) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */ +#define AFEC_TEMPCWR_TLOWTHRES_Pos 0 +#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */ +#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))) +#define AFEC_TEMPCWR_THIGHTHRES_Pos 16 +#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */ +#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))) +/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */ +#define AFEC_ACR_PGA0EN (0x1u << 2) /**< \brief (AFEC_ACR) PGA0 Enable */ +#define AFEC_ACR_PGA1EN (0x1u << 3) /**< \brief (AFEC_ACR) PGA1 Enable */ +#define AFEC_ACR_IBCTL_Pos 8 +#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFE Bias Current Control */ +#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))) +/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */ +#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */ +#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */ +#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */ +#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */ +#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */ +#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */ +#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */ +#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */ +#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */ +#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */ +#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */ +#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */ +/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */ +#define AFEC_COSR_CSEL (0x1u << 0) /**< \brief (AFEC_COSR) Sample & Hold unit Correction Select */ +/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */ +#define AFEC_CVR_OFFSETCORR_Pos 0 +#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */ +#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos))) +#define AFEC_CVR_GAINCORR_Pos 16 +#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */ +#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos))) +/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */ +#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */ +#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */ +#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */ +#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */ +#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */ +#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */ +#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */ +#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */ +#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */ +#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */ +#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */ +#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */ +/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */ +#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */ +#define AFEC_WPMR_WPKEY_Pos 8 +#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */ +#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos))) +#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */ +#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */ +#define AFEC_WPSR_WPVSRC_Pos 8 +#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */ +/* -------- AFEC_VERSION : (AFEC Offset: 0xFC) AFEC Version Register -------- */ +#define AFEC_VERSION_VERSION_Pos 0 +#define AFEC_VERSION_VERSION_Msk (0xfffu << AFEC_VERSION_VERSION_Pos) /**< \brief (AFEC_VERSION) Version of the Hardware Module */ +#define AFEC_VERSION_MFN_Pos 16 +#define AFEC_VERSION_MFN_Msk (0x7u << AFEC_VERSION_MFN_Pos) /**< \brief (AFEC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_AFEC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_chipid.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_chipid.h new file mode 100644 index 0000000000..591fead101 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_chipid.h @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_CHIPID_COMPONENT_ +#define _SAMV71_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAMV71_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) /**< \brief (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) /**< \brief (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) /**< \brief (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) /**< \brief (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAMV71_CHIPID_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_dacc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_dacc.h new file mode 100644 index 0000000000..6f12ae2511 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_dacc.h @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_DACC_COMPONENT_ +#define _SAMV71_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */ + __I uint32_t Reserved1[1]; + __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */ + __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t DACC_VERSION; /**< \brief (Dacc Offset: 0xFC) Version Register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */ +#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */ +#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */ +#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC. */ +#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). */ +#define DACC_MR_ZERO (0x1u << 5) /**< \brief (DACC_MR) Must always be written to 0. */ +#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */ +#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 are single-ended outputs. */ +#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */ +#define DACC_MR_PRESCALER_Pos 24 +#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */ +#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))) +/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */ +#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */ +#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */ +#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGSEL0_Pos 4 +#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */ +#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))) +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_TRGSEL1_Pos 8 +#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */ +#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))) +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_OSR0_Pos 16 +#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */ +#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))) +#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_Pos 20 +#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */ +#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))) +#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC Ready Flag */ +#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC Ready Flag */ +/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */ +#define DACC_CDR_DATA0_Pos 0 +#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */ +#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))) +#define DACC_CDR_DATA1_Pos 16 +#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */ +#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */ +#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */ +#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */ +#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */ +#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */ +#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */ +#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */ +#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */ +#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */ +#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */ +#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */ +#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */ +#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status Register -------- */ +#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */ +#define DACC_WPSR_WPVSRC_Pos 8 +#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */ +/* -------- DACC_VERSION : (DACC Offset: 0xFC) Version Register -------- */ +#define DACC_VERSION_VERSION_Pos 0 +#define DACC_VERSION_VERSION_Msk (0xfffu << DACC_VERSION_VERSION_Pos) /**< \brief (DACC_VERSION) Version */ +#define DACC_VERSION_MFN_Pos 16 +#define DACC_VERSION_MFN_Msk (0x7u << DACC_VERSION_MFN_Pos) /**< \brief (DACC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_DACC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_efc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_efc.h new file mode 100644 index 0000000000..1b7161d8c8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_efc.h @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_EFC_COMPONENT_ +#define _SAMV71_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ + __I uint32_t Reserved1[1]; + __I uint32_t EEFC_VERSION; /**< \brief (Efc Offset: 0x14) EEFC Version Register */ + __I uint32_t Reserved2[51]; + __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) +#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status (cleared on read) */ +#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) */ +#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ +/* -------- EEFC_VERSION : (EFC Offset: 0x14) EEFC Version Register -------- */ +#define EEFC_VERSION_VERSION_Pos 0 +#define EEFC_VERSION_VERSION_Msk (0xfffu << EEFC_VERSION_VERSION_Pos) /**< \brief (EEFC_VERSION) Version of the Hardware Module */ +#define EEFC_VERSION_MFN_Pos 16 +#define EEFC_VERSION_MFN_Msk (0x7u << EEFC_VERSION_MFN_Pos) /**< \brief (EEFC_VERSION) Metal Fix Number */ +/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */ +#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */ +#define EEFC_WPMR_WPKEY_Pos 8 +#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */ +#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos))) +#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMV71_EFC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_gmac.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_gmac.h new file mode 100644 index 0000000000..fae8b33872 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_gmac.h @@ -0,0 +1,1246 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_GMAC_COMPONENT_ +#define _SAMV71_GMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */ +/* ============================================================================= */ +/** \addtogroup SAMV71_GMAC Gigabit Ethernet MAC */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GmacSa hardware registers */ +typedef struct { + __IO uint32_t GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top Register */ +} GmacSa; + +/** \brief GmacSt2Compare hardware registers */ +typedef struct { + __IO uint32_t GMAC_ST2COM0; /**< \brief 31:16 - Compare Value. 15:0 - Mask Value. */ + __IO uint32_t GMAC_ST2COM1; /**< \brief 31:9 - Reserved; 8:7 - Offset location in frame; 6:0 Offset value in bytes */ +} GmacSt2Compare; + +/** \brief Gmac hardware registers */ +#define GMACSA_NUMBER 4 +#define GMACST2COMPARE_NUMBER 24 +typedef struct { + __IO uint32_t GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */ + __IO uint32_t GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */ + __I uint32_t GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */ + __IO uint32_t GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */ + __IO uint32_t GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */ + __IO uint32_t GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */ + __IO uint32_t GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address Register */ + __IO uint32_t GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register */ + __IO uint32_t GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */ + __I uint32_t GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */ + __O uint32_t GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */ + __O uint32_t GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */ + __IO uint32_t GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */ + __IO uint32_t GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */ + __I uint32_t GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */ + __IO uint32_t GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */ + __IO uint32_t GMAC_TPSF; /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */ + __IO uint32_t GMAC_RPSF; /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */ + __IO uint32_t GMAC_RJFML; /**< \brief (Gmac Offset: 0x048) RX Jumbo Frame Max Length Register */ + __I uint32_t Reserved1[13]; + __IO uint32_t GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom */ + __IO uint32_t GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top */ + GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */ + __IO uint32_t GMAC_TIDM1; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */ + __IO uint32_t GMAC_TIDM2; /**< \brief (Gmac Offset: 0x0AC) Type ID Match 2 Register */ + __IO uint32_t GMAC_TIDM3; /**< \brief (Gmac Offset: 0x0B0) Type ID Match 3 Register */ + __IO uint32_t GMAC_TIDM4; /**< \brief (Gmac Offset: 0x0B4) Type ID Match 4 Register */ + __IO uint32_t GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */ + __IO uint32_t GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */ + __IO uint32_t GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */ + __IO uint32_t GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */ + __IO uint32_t GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register */ + __IO uint32_t GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t GMAC_NSC; /**< \brief (Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register */ + __IO uint32_t GMAC_SCL; /**< \brief (Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register */ + __IO uint32_t GMAC_SCH; /**< \brief (Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register */ + __I uint32_t GMAC_EFTSH; /**< \brief (Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_EFRSH; /**< \brief (Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register */ + __I uint32_t GMAC_PEFTSH; /**< \brief (Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_PEFRSH; /**< \brief (Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register */ + __I uint32_t Reserved3[1]; + __I uint32_t GMAC_MID; /**< \brief (Gmac Offset: 0x0FC) Module ID Register */ + __I uint32_t GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted Low Register */ + __I uint32_t GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted High Register */ + __I uint32_t GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */ + __I uint32_t GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */ + __I uint32_t GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */ + __I uint32_t GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */ + __I uint32_t GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Underruns Register */ + __I uint32_t GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */ + __I uint32_t GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */ + __I uint32_t GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */ + __I uint32_t GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */ + __I uint32_t GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */ + __I uint32_t GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */ + __I uint32_t GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received Low Received Register */ + __I uint32_t GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received High Received Register */ + __I uint32_t GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */ + __I uint32_t GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */ + __I uint32_t GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */ + __I uint32_t GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */ + __I uint32_t GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ + __I uint32_t GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ + __I uint32_t GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */ + __I uint32_t GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */ + __I uint32_t GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */ + __I uint32_t GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */ + __I uint32_t GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */ + __I uint32_t GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */ + __I uint32_t GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */ + __I uint32_t GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */ + __I uint32_t GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */ + __I uint32_t GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */ + __I uint32_t GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */ + __I uint32_t GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t GMAC_TISUBN; /**< \brief (Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */ + __IO uint32_t GMAC_TSH; /**< \brief (Gmac Offset: 0x1C0) 1588 Timer Seconds High Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t GMAC_TSL; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register */ + __IO uint32_t GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */ + __O uint32_t GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */ + __IO uint32_t GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */ + __I uint32_t GMAC_EFTSL; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_EFRSL; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */ + __I uint32_t GMAC_PEFTSL; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_PEFRSL; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */ + __I uint32_t Reserved6[128]; + __I uint32_t GMAC_ISRPQ[2]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) */ + __I uint32_t Reserved7[14]; + __IO uint32_t GMAC_TBQBAPQ[2]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved8[14]; + __IO uint32_t GMAC_RBQBAPQ[2]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved9[6]; + __IO uint32_t GMAC_RBSRPQ[2]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) */ + __I uint32_t Reserved10[5]; + __IO uint32_t GMAC_CBSCR; /**< \brief (Gmac Offset: 0x4BC) Credit-Based Shaping Control Register */ + __IO uint32_t GMAC_CBSISQA; /**< \brief (Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */ + __IO uint32_t GMAC_CBSISQB; /**< \brief (Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */ + __I uint32_t Reserved11[14]; + __IO uint32_t GMAC_ST1RPQ[4]; /**< \brief (Gmac Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) */ + __I uint32_t Reserved12[12]; + __IO uint32_t GMAC_ST2RPQ[8]; /**< \brief (Gmac Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) */ + __I uint32_t Reserved13[12]; + __I uint32_t Reserved14[28]; + __O uint32_t GMAC_IERPQ[2]; /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) */ + __I uint32_t Reserved15[6]; + __O uint32_t GMAC_IDRPQ[2]; /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) */ + __I uint32_t Reserved16[6]; + __IO uint32_t GMAC_IMRPQ[2]; /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) */ + __I uint32_t Reserved17[38]; + __IO uint32_t GMAC_ST2ER[4]; /**< \brief (Gmac Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) */ + __I uint32_t Reserved18[4]; + __IO GmacSt2Compare GMAC_ST2COMP[GMACST2COMPARE_NUMBER];/**< \brief (Gmac Offset: 0x700) Screener Type 2 Compare Registers */ +} Gmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */ +#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */ +#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */ +#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */ +#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */ +#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */ +#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */ +#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */ +#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */ +#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */ +#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */ +#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */ +#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */ +#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */ +#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */ +#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */ +#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */ +/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */ +#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */ +#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */ +#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */ +#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */ +#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */ +#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */ +#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */ +#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */ +#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */ +#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */ +#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */ +#define GMAC_NCFGR_RXBUFO_Pos 14 +#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */ +#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) +#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */ +#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */ +#define GMAC_NCFGR_CLK_Pos 18 +#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */ +#define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))) +#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ +#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_DBW_Pos 21 +#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */ +#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))) +#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */ +#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */ +#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */ +#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */ +#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */ +#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */ +#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */ +/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */ +#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */ +#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */ +/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */ +#define GMAC_UR_RMII (0x1u << 0) /**< \brief (GMAC_UR) Reduced MII Mode */ +/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */ +#define GMAC_DCFGR_FBLDO_Pos 0 +#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */ +#define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))) +#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */ +#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */ +#define GMAC_DCFGR_RXBMS_Pos 8 +#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))) +#define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 4/8 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 4/4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4/2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */ +#define GMAC_DCFGR_DRBS_Pos 16 +#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */ +#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) +#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */ +/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */ +#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */ +#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */ +#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */ +#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */ +#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */ +#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */ +/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address Register -------- */ +#define GMAC_RBQB_ADDR_Pos 2 +#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */ +#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) +/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address Register -------- */ +#define GMAC_TBQB_ADDR_Pos 2 +#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */ +#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) +/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */ +#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */ +#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */ +#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */ +#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */ +/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */ +#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */ +#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */ +#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */ +#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */ +#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Underrun */ +#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */ +#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */ +#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */ +#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */ +#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */ +#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */ +#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */ +#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */ +#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */ +#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */ +#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */ +#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */ +#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */ +#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */ +#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */ +#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */ +#define GMAC_ISR_TSU (0x1u << 29) /**< \brief (GMAC_ISR) TSU timer comparison interrupt */ +/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */ +#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */ +#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */ +#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */ +#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */ +#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Underrun */ +#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */ +#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */ +#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */ +#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */ +#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */ +#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */ +#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */ +#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */ +#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */ +#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */ +#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */ +#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */ +#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */ +#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */ +#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */ +#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */ +#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */ +#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */ +#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */ +#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */ +#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */ +#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Underrun */ +#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */ +#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */ +#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */ +#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */ +#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */ +#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */ +#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */ +#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */ +#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */ +#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */ +#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */ +#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */ +#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */ +#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */ +#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ +#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */ +/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */ +#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */ +#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */ +#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */ +#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */ +#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Underrun */ +#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */ +#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */ +#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */ +#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */ +#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */ +#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */ +#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */ +#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */ +#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */ +#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */ +#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */ +#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */ +#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */ +#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */ +#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */ +/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */ +#define GMAC_MAN_DATA_Pos 0 +#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */ +#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) +#define GMAC_MAN_WTN_Pos 16 +#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */ +#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) +#define GMAC_MAN_REGA_Pos 18 +#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */ +#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) +#define GMAC_MAN_PHYA_Pos 23 +#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */ +#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) +#define GMAC_MAN_OP_Pos 28 +#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */ +#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) +#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */ +#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */ +/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */ +#define GMAC_RPQ_RPQ_Pos 0 +#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */ +/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */ +#define GMAC_TPQ_TPQ_Pos 0 +#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */ +#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) +/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */ +#define GMAC_TPSF_TPB1ADR_Pos 0 +#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) Transmit Partial Store and Forward Address */ +#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))) +#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */ +/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */ +#define GMAC_RPSF_RPB1ADR_Pos 0 +#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) Receive Partial Store and Forward Address */ +#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))) +#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */ +/* -------- GMAC_RJFML : (GMAC Offset: 0x048) RX Jumbo Frame Max Length Register -------- */ +#define GMAC_RJFML_FML_Pos 0 +#define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos) /**< \brief (GMAC_RJFML) Frame Max Length */ +#define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))) +/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom -------- */ +#define GMAC_HRB_ADDR_Pos 0 +#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */ +#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) +/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top -------- */ +#define GMAC_HRT_ADDR_Pos 0 +#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */ +#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) +/* -------- GMAC_SAB : (GMAC Offset: N/A) Specific Address 1 Bottom Register -------- */ +#define GMAC_SAB_ADDR_Pos 0 +#define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos) /**< \brief (GMAC_SAB) Specific Address 1 */ +#define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))) +/* -------- GMAC_SAT : (GMAC Offset: N/A) Specific Address 1 Top Register -------- */ +#define GMAC_SAT_ADDR_Pos 0 +#define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos) /**< \brief (GMAC_SAT) Specific Address 1 */ +#define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))) +/* -------- GMAC_TIDM1 : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */ +#define GMAC_TIDM1_TID_Pos 0 +#define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos) /**< \brief (GMAC_TIDM1) Type ID Match 1 */ +#define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos))) +#define GMAC_TIDM1_ENID1 (0x1u << 31) /**< \brief (GMAC_TIDM1) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM2 : (GMAC Offset: 0x0AC) Type ID Match 2 Register -------- */ +#define GMAC_TIDM2_TID_Pos 0 +#define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos) /**< \brief (GMAC_TIDM2) Type ID Match 2 */ +#define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos))) +#define GMAC_TIDM2_ENID2 (0x1u << 31) /**< \brief (GMAC_TIDM2) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM3 : (GMAC Offset: 0x0B0) Type ID Match 3 Register -------- */ +#define GMAC_TIDM3_TID_Pos 0 +#define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos) /**< \brief (GMAC_TIDM3) Type ID Match 3 */ +#define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos))) +#define GMAC_TIDM3_ENID3 (0x1u << 31) /**< \brief (GMAC_TIDM3) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM4 : (GMAC Offset: 0x0B4) Type ID Match 4 Register -------- */ +#define GMAC_TIDM4_TID_Pos 0 +#define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos) /**< \brief (GMAC_TIDM4) Type ID Match 4 */ +#define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos))) +#define GMAC_TIDM4_ENID4 (0x1u << 31) /**< \brief (GMAC_TIDM4) Enable Copying of TID Matched Frames */ +/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */ +#define GMAC_WOL_IP_Pos 0 +#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))) +#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */ +#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */ +#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */ +/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */ +#define GMAC_IPGS_FL_Pos 0 +#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */ +#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) +/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */ +#define GMAC_SVLAN_VLAN_TYPE_Pos 0 +#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */ +#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) +#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */ +/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */ +#define GMAC_TPFCP_PEV_Pos 0 +#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */ +#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) +#define GMAC_TPFCP_PQ_Pos 8 +#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */ +#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) +/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom Register -------- */ +#define GMAC_SAMB1_ADDR_Pos 0 +#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */ +#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) +/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top Register -------- */ +#define GMAC_SAMT1_ADDR_Pos 0 +#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */ +#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) +/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register -------- */ +#define GMAC_NSC_NANOSEC_Pos 0 +#define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos) /**< \brief (GMAC_NSC) 1588 Timer Nanosecond Comparison Value */ +#define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))) +/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) 1588 Timer Second Comparison Low Register -------- */ +#define GMAC_SCL_SEC_Pos 0 +#define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos) /**< \brief (GMAC_SCL) 1588 Timer Second Comparison Value */ +#define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))) +/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) 1588 Timer Second Comparison High Register -------- */ +#define GMAC_SCH_SEC_Pos 0 +#define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos) /**< \brief (GMAC_SCH) 1588 Timer Second Comparison Value */ +#define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))) +/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_EFTSH_RUD_Pos 0 +#define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos) /**< \brief (GMAC_EFTSH) Register Update */ +/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) PTP Event Frame Received Seconds High Register -------- */ +#define GMAC_EFRSH_RUD_Pos 0 +#define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos) /**< \brief (GMAC_EFRSH) Register Update */ +/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_PEFTSH_RUD_Pos 0 +#define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos) /**< \brief (GMAC_PEFTSH) Register Update */ +/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register -------- */ +#define GMAC_PEFRSH_RUD_Pos 0 +#define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos) /**< \brief (GMAC_PEFRSH) Register Update */ +/* -------- GMAC_MID : (GMAC Offset: 0x0FC) Module ID Register -------- */ +#define GMAC_MID_MREV_Pos 0 +#define GMAC_MID_MREV_Msk (0xffffu << GMAC_MID_MREV_Pos) /**< \brief (GMAC_MID) Module Revision */ +#define GMAC_MID_MID_Pos 16 +#define GMAC_MID_MID_Msk (0xffffu << GMAC_MID_MID_Pos) /**< \brief (GMAC_MID) Module Identification Number */ +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted Low Register -------- */ +#define GMAC_OTLO_TXO_Pos 0 +#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */ +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted High Register -------- */ +#define GMAC_OTHI_TXO_Pos 0 +#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */ +/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */ +#define GMAC_FT_FTX_Pos 0 +#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */ +/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */ +#define GMAC_BCFT_BFTX_Pos 0 +#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */ +/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */ +#define GMAC_MFT_MFTX_Pos 0 +#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */ +/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */ +#define GMAC_PFT_PFTX_Pos 0 +#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */ +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */ +#define GMAC_BFT64_NFTX_Pos 0 +#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT127_NFTX_Pos 0 +#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT255_NFTX_Pos 0 +#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT511_NFTX_Pos 0 +#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1023_NFTX_Pos 0 +#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1518_NFTX_Pos 0 +#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_GTBFT1518_NFTX_Pos 0 +#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Underruns Register -------- */ +#define GMAC_TUR_TXUNR_Pos 0 +#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Underruns */ +/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */ +#define GMAC_SCF_SCOL_Pos 0 +#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */ +/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */ +#define GMAC_MCF_MCOL_Pos 0 +#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */ +/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */ +#define GMAC_EC_XCOL_Pos 0 +#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */ +/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */ +#define GMAC_LC_LCOL_Pos 0 +#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */ +/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */ +#define GMAC_DTF_DEFT_Pos 0 +#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */ +/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */ +#define GMAC_CSE_CSR_Pos 0 +#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */ +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received Low Received Register -------- */ +#define GMAC_ORLO_RXO_Pos 0 +#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */ +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received High Received Register -------- */ +#define GMAC_ORHI_RXO_Pos 0 +#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */ +/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */ +#define GMAC_FR_FRX_Pos 0 +#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */ +/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */ +#define GMAC_BCFR_BFRX_Pos 0 +#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */ +/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */ +#define GMAC_MFR_MFRX_Pos 0 +#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */ +/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */ +#define GMAC_PFR_PFRX_Pos 0 +#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */ +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */ +#define GMAC_BFR64_NFRX_Pos 0 +#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */ +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */ +#define GMAC_TBFR127_NFRX_Pos 0 +#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */ +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */ +#define GMAC_TBFR255_NFRX_Pos 0 +#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */ +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register -------- */ +#define GMAC_TBFR511_NFRX_Pos 0 +#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */ +#define GMAC_TBFR1023_NFRX_Pos 0 +#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */ +#define GMAC_TBFR1518_NFRX_Pos 0 +#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */ +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */ +#define GMAC_TMXBFR_NFRX_Pos 0 +#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */ +/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */ +#define GMAC_UFR_UFRX_Pos 0 +#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */ +/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */ +#define GMAC_OFR_OFRX_Pos 0 +#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */ +/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */ +#define GMAC_JR_JRX_Pos 0 +#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */ +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */ +#define GMAC_FCSE_FCKR_Pos 0 +#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */ +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */ +#define GMAC_LFFE_LFER_Pos 0 +#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */ +/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */ +#define GMAC_RSE_RXSE_Pos 0 +#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */ +/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */ +#define GMAC_AE_AER_Pos 0 +#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */ +/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */ +#define GMAC_RRE_RXRER_Pos 0 +#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */ +/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */ +#define GMAC_ROE_RXOVR_Pos 0 +#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */ +/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */ +#define GMAC_IHCE_HCKER_Pos 0 +#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */ +/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */ +#define GMAC_TCE_TCKER_Pos 0 +#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */ +/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */ +#define GMAC_UCE_UCKER_Pos 0 +#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */ +/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register -------- */ +#define GMAC_TISUBN_LSBTIR_Pos 0 +#define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos) /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register */ +#define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))) +/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register -------- */ +#define GMAC_TSH_TCS_Pos 0 +#define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos) /**< \brief (GMAC_TSH) Timer Count in Seconds */ +#define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))) +/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register -------- */ +#define GMAC_TSL_TCS_Pos 0 +#define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos) /**< \brief (GMAC_TSL) Timer Count in Seconds */ +#define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))) +/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */ +#define GMAC_TN_TNS_Pos 0 +#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */ +#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) +/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */ +#define GMAC_TA_ITDT_Pos 0 +#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */ +#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) +#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */ +/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */ +#define GMAC_TI_CNS_Pos 0 +#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */ +#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) +#define GMAC_TI_ACNS_Pos 8 +#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */ +#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) +#define GMAC_TI_NIT_Pos 16 +#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */ +#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) +/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_EFTSL_RUD_Pos 0 +#define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos) /**< \brief (GMAC_EFTSL) Register Update */ +/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_EFTN_RUD_Pos 0 +#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */ +/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register -------- */ +#define GMAC_EFRSL_RUD_Pos 0 +#define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos) /**< \brief (GMAC_EFRSL) Register Update */ +/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register -------- */ +#define GMAC_EFRN_RUD_Pos 0 +#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */ +/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_PEFTSL_RUD_Pos 0 +#define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos) /**< \brief (GMAC_PEFTSL) Register Update */ +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_PEFTN_RUD_Pos 0 +#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */ +/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register -------- */ +#define GMAC_PEFRSL_RUD_Pos 0 +#define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos) /**< \brief (GMAC_PEFRSL) Register Update */ +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register -------- */ +#define GMAC_PEFRN_RUD_Pos 0 +#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */ +/* -------- GMAC_ISRPQ[2] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) -------- */ +#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[2]) Receive Complete */ +#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[2]) RX Used Bit Read */ +#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[2]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[2]) Transmit Complete */ +#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[2]) Receive Overrun */ +#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[2]) HRESP Not OK */ +/* -------- GMAC_TBQBAPQ[2] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_TBQBAPQ_TXBQBA_Pos 2 +#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[2]) Transmit Buffer Queue Base Address */ +#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos))) +/* -------- GMAC_RBQBAPQ[2] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_RBQBAPQ_RXBQBA_Pos 2 +#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[2]) Receive Buffer Queue Base Address */ +#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos))) +/* -------- GMAC_RBSRPQ[2] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) -------- */ +#define GMAC_RBSRPQ_RBS_Pos 0 +#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[2]) Receive Buffer Size */ +#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos))) +/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register -------- */ +#define GMAC_CBSCR_QBE (0x1u << 0) /**< \brief (GMAC_CBSCR) Queue B CBS Enable */ +#define GMAC_CBSCR_QAE (0x1u << 1) /**< \brief (GMAC_CBSCR) Queue A CBS Enable */ +/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A -------- */ +#define GMAC_CBSISQA_IS_Pos 0 +#define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos) /**< \brief (GMAC_CBSISQA) IdleSlope */ +#define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos))) +/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B -------- */ +#define GMAC_CBSISQB_IS_Pos 0 +#define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos) /**< \brief (GMAC_CBSISQB) IdleSlope */ +#define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos))) +/* -------- GMAC_ST1RPQ[4] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST1RPQ_QNB_Pos 0 +#define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[4]) Queue Number (0-2) */ +#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos))) +#define GMAC_ST1RPQ_DSTCM_Pos 4 +#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match */ +#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos))) +#define GMAC_ST1RPQ_UDPM_Pos 12 +#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match */ +#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos))) +#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match Enable */ +#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match Enable */ +/* -------- GMAC_ST2RPQ[8] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST2RPQ_QNB_Pos 0 +#define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Queue Number (0-2) */ +#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos))) +#define GMAC_ST2RPQ_VLANP_Pos 4 +#define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[8]) VLAN Priority */ +#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos))) +#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[8]) VLAN Enable */ +#define GMAC_ST2RPQ_I2ETH_Pos 9 +#define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 EtherType register x */ +#define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos))) +#define GMAC_ST2RPQ_ETHE (0x1u << 12) /**< \brief (GMAC_ST2RPQ[8]) EtherType Enable */ +#define GMAC_ST2RPQ_COMPA_Pos 13 +#define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos))) +#define GMAC_ST2RPQ_COMPAE (0x1u << 18) /**< \brief (GMAC_ST2RPQ[8]) Compare A Enable */ +#define GMAC_ST2RPQ_COMPB_Pos 19 +#define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos))) +#define GMAC_ST2RPQ_COMPBE (0x1u << 24) /**< \brief (GMAC_ST2RPQ[8]) Compare B Enable */ +#define GMAC_ST2RPQ_COMPC_Pos 25 +#define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos))) +#define GMAC_ST2RPQ_COMPCE (0x1u << 30) /**< \brief (GMAC_ST2RPQ[8]) Compare C Enable */ +/* -------- GMAC_IERPQ[2] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) -------- */ +#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[2]) Receive Complete */ +#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[2]) RX Used Bit Read */ +#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[2]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[2]) Transmit Complete */ +#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[2]) Receive Overrun */ +#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[2]) HRESP Not OK */ +/* -------- GMAC_IDRPQ[2] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) -------- */ +#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[2]) Receive Complete */ +#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[2]) RX Used Bit Read */ +#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[2]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[2]) Transmit Complete */ +#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[2]) Receive Overrun */ +#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[2]) HRESP Not OK */ +/* -------- GMAC_IMRPQ[2] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) -------- */ +#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[2]) Receive Complete */ +#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[2]) RX Used Bit Read */ +#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[2]) AHB Error */ +#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[2]) Transmit Complete */ +#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[2]) Receive Overrun */ +#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[2]) HRESP Not OK */ +/* -------- GMAC_ST2ER[4] : (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) -------- */ +#define GMAC_ST2ER_COMPVAL_Pos 0 +#define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos) /**< \brief (GMAC_ST2ER[4]) Ethertype Compare Value */ +#define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos))) +/* -------- GMAC_ST2CW00 : (GMAC Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) -------- */ +#define GMAC_ST2CW00_MASKVAL_Pos 0 +#define GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos) /**< \brief (GMAC_ST2CW00) Mask Value */ +#define GMAC_ST2CW00_MASKVAL(value) ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos))) +#define GMAC_ST2CW00_COMPVAL_Pos 16 +#define GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos) /**< \brief (GMAC_ST2CW00) Compare Value */ +#define GMAC_ST2CW00_COMPVAL(value) ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos))) +/* -------- GMAC_ST2CW10 : (GMAC Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) -------- */ +#define GMAC_ST2CW10_OFFSVAL_Pos 0 +#define GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW10) Offset Value in Bytes */ +#define GMAC_ST2CW10_OFFSVAL(value) ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos))) +#define GMAC_ST2CW10_OFFSSTRT_Pos 7 +#define GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW10) Ethernet Frame Offset Start */ +#define GMAC_ST2CW10_OFFSSTRT(value) ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos))) +#define GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW10) Offset from the start of the frame */ +#define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the IP header field */ +#define GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW01 : (GMAC Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) -------- */ +#define GMAC_ST2CW01_MASKVAL_Pos 0 +#define GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos) /**< \brief (GMAC_ST2CW01) Mask Value */ +#define GMAC_ST2CW01_MASKVAL(value) ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos))) +#define GMAC_ST2CW01_COMPVAL_Pos 16 +#define GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos) /**< \brief (GMAC_ST2CW01) Compare Value */ +#define GMAC_ST2CW01_COMPVAL(value) ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos))) +/* -------- GMAC_ST2CW11 : (GMAC Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) -------- */ +#define GMAC_ST2CW11_OFFSVAL_Pos 0 +#define GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW11) Offset Value in Bytes */ +#define GMAC_ST2CW11_OFFSVAL(value) ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos))) +#define GMAC_ST2CW11_OFFSSTRT_Pos 7 +#define GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW11) Ethernet Frame Offset Start */ +#define GMAC_ST2CW11_OFFSSTRT(value) ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos))) +#define GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW11) Offset from the start of the frame */ +#define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the IP header field */ +#define GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW02 : (GMAC Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) -------- */ +#define GMAC_ST2CW02_MASKVAL_Pos 0 +#define GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos) /**< \brief (GMAC_ST2CW02) Mask Value */ +#define GMAC_ST2CW02_MASKVAL(value) ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos))) +#define GMAC_ST2CW02_COMPVAL_Pos 16 +#define GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos) /**< \brief (GMAC_ST2CW02) Compare Value */ +#define GMAC_ST2CW02_COMPVAL(value) ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos))) +/* -------- GMAC_ST2CW12 : (GMAC Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) -------- */ +#define GMAC_ST2CW12_OFFSVAL_Pos 0 +#define GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW12) Offset Value in Bytes */ +#define GMAC_ST2CW12_OFFSVAL(value) ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos))) +#define GMAC_ST2CW12_OFFSSTRT_Pos 7 +#define GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW12) Ethernet Frame Offset Start */ +#define GMAC_ST2CW12_OFFSSTRT(value) ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos))) +#define GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW12) Offset from the start of the frame */ +#define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the IP header field */ +#define GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW03 : (GMAC Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) -------- */ +#define GMAC_ST2CW03_MASKVAL_Pos 0 +#define GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos) /**< \brief (GMAC_ST2CW03) Mask Value */ +#define GMAC_ST2CW03_MASKVAL(value) ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos))) +#define GMAC_ST2CW03_COMPVAL_Pos 16 +#define GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos) /**< \brief (GMAC_ST2CW03) Compare Value */ +#define GMAC_ST2CW03_COMPVAL(value) ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos))) +/* -------- GMAC_ST2CW13 : (GMAC Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) -------- */ +#define GMAC_ST2CW13_OFFSVAL_Pos 0 +#define GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW13) Offset Value in Bytes */ +#define GMAC_ST2CW13_OFFSVAL(value) ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos))) +#define GMAC_ST2CW13_OFFSSTRT_Pos 7 +#define GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW13) Ethernet Frame Offset Start */ +#define GMAC_ST2CW13_OFFSSTRT(value) ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos))) +#define GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW13) Offset from the start of the frame */ +#define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the IP header field */ +#define GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW04 : (GMAC Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) -------- */ +#define GMAC_ST2CW04_MASKVAL_Pos 0 +#define GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos) /**< \brief (GMAC_ST2CW04) Mask Value */ +#define GMAC_ST2CW04_MASKVAL(value) ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos))) +#define GMAC_ST2CW04_COMPVAL_Pos 16 +#define GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos) /**< \brief (GMAC_ST2CW04) Compare Value */ +#define GMAC_ST2CW04_COMPVAL(value) ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos))) +/* -------- GMAC_ST2CW14 : (GMAC Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) -------- */ +#define GMAC_ST2CW14_OFFSVAL_Pos 0 +#define GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW14) Offset Value in Bytes */ +#define GMAC_ST2CW14_OFFSVAL(value) ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos))) +#define GMAC_ST2CW14_OFFSSTRT_Pos 7 +#define GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW14) Ethernet Frame Offset Start */ +#define GMAC_ST2CW14_OFFSSTRT(value) ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos))) +#define GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW14) Offset from the start of the frame */ +#define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the IP header field */ +#define GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW05 : (GMAC Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) -------- */ +#define GMAC_ST2CW05_MASKVAL_Pos 0 +#define GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos) /**< \brief (GMAC_ST2CW05) Mask Value */ +#define GMAC_ST2CW05_MASKVAL(value) ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos))) +#define GMAC_ST2CW05_COMPVAL_Pos 16 +#define GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos) /**< \brief (GMAC_ST2CW05) Compare Value */ +#define GMAC_ST2CW05_COMPVAL(value) ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos))) +/* -------- GMAC_ST2CW15 : (GMAC Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) -------- */ +#define GMAC_ST2CW15_OFFSVAL_Pos 0 +#define GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW15) Offset Value in Bytes */ +#define GMAC_ST2CW15_OFFSVAL(value) ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos))) +#define GMAC_ST2CW15_OFFSSTRT_Pos 7 +#define GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW15) Ethernet Frame Offset Start */ +#define GMAC_ST2CW15_OFFSSTRT(value) ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos))) +#define GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW15) Offset from the start of the frame */ +#define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the IP header field */ +#define GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW06 : (GMAC Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) -------- */ +#define GMAC_ST2CW06_MASKVAL_Pos 0 +#define GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos) /**< \brief (GMAC_ST2CW06) Mask Value */ +#define GMAC_ST2CW06_MASKVAL(value) ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos))) +#define GMAC_ST2CW06_COMPVAL_Pos 16 +#define GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos) /**< \brief (GMAC_ST2CW06) Compare Value */ +#define GMAC_ST2CW06_COMPVAL(value) ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos))) +/* -------- GMAC_ST2CW16 : (GMAC Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) -------- */ +#define GMAC_ST2CW16_OFFSVAL_Pos 0 +#define GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW16) Offset Value in Bytes */ +#define GMAC_ST2CW16_OFFSVAL(value) ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos))) +#define GMAC_ST2CW16_OFFSSTRT_Pos 7 +#define GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW16) Ethernet Frame Offset Start */ +#define GMAC_ST2CW16_OFFSSTRT(value) ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos))) +#define GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW16) Offset from the start of the frame */ +#define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the IP header field */ +#define GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW07 : (GMAC Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) -------- */ +#define GMAC_ST2CW07_MASKVAL_Pos 0 +#define GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos) /**< \brief (GMAC_ST2CW07) Mask Value */ +#define GMAC_ST2CW07_MASKVAL(value) ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos))) +#define GMAC_ST2CW07_COMPVAL_Pos 16 +#define GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos) /**< \brief (GMAC_ST2CW07) Compare Value */ +#define GMAC_ST2CW07_COMPVAL(value) ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos))) +/* -------- GMAC_ST2CW17 : (GMAC Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) -------- */ +#define GMAC_ST2CW17_OFFSVAL_Pos 0 +#define GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW17) Offset Value in Bytes */ +#define GMAC_ST2CW17_OFFSVAL(value) ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos))) +#define GMAC_ST2CW17_OFFSSTRT_Pos 7 +#define GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW17) Ethernet Frame Offset Start */ +#define GMAC_ST2CW17_OFFSSTRT(value) ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos))) +#define GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW17) Offset from the start of the frame */ +#define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the IP header field */ +#define GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW08 : (GMAC Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) -------- */ +#define GMAC_ST2CW08_MASKVAL_Pos 0 +#define GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos) /**< \brief (GMAC_ST2CW08) Mask Value */ +#define GMAC_ST2CW08_MASKVAL(value) ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos))) +#define GMAC_ST2CW08_COMPVAL_Pos 16 +#define GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos) /**< \brief (GMAC_ST2CW08) Compare Value */ +#define GMAC_ST2CW08_COMPVAL(value) ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos))) +/* -------- GMAC_ST2CW18 : (GMAC Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) -------- */ +#define GMAC_ST2CW18_OFFSVAL_Pos 0 +#define GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW18) Offset Value in Bytes */ +#define GMAC_ST2CW18_OFFSVAL(value) ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos))) +#define GMAC_ST2CW18_OFFSSTRT_Pos 7 +#define GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW18) Ethernet Frame Offset Start */ +#define GMAC_ST2CW18_OFFSSTRT(value) ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos))) +#define GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW18) Offset from the start of the frame */ +#define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the IP header field */ +#define GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW09 : (GMAC Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) -------- */ +#define GMAC_ST2CW09_MASKVAL_Pos 0 +#define GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos) /**< \brief (GMAC_ST2CW09) Mask Value */ +#define GMAC_ST2CW09_MASKVAL(value) ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos))) +#define GMAC_ST2CW09_COMPVAL_Pos 16 +#define GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos) /**< \brief (GMAC_ST2CW09) Compare Value */ +#define GMAC_ST2CW09_COMPVAL(value) ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos))) +/* -------- GMAC_ST2CW19 : (GMAC Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) -------- */ +#define GMAC_ST2CW19_OFFSVAL_Pos 0 +#define GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW19) Offset Value in Bytes */ +#define GMAC_ST2CW19_OFFSVAL(value) ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos))) +#define GMAC_ST2CW19_OFFSSTRT_Pos 7 +#define GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW19) Ethernet Frame Offset Start */ +#define GMAC_ST2CW19_OFFSSTRT(value) ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos))) +#define GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW19) Offset from the start of the frame */ +#define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the IP header field */ +#define GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW010 : (GMAC Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) -------- */ +#define GMAC_ST2CW010_MASKVAL_Pos 0 +#define GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos) /**< \brief (GMAC_ST2CW010) Mask Value */ +#define GMAC_ST2CW010_MASKVAL(value) ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos))) +#define GMAC_ST2CW010_COMPVAL_Pos 16 +#define GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos) /**< \brief (GMAC_ST2CW010) Compare Value */ +#define GMAC_ST2CW010_COMPVAL(value) ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos))) +/* -------- GMAC_ST2CW110 : (GMAC Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) -------- */ +#define GMAC_ST2CW110_OFFSVAL_Pos 0 +#define GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW110) Offset Value in Bytes */ +#define GMAC_ST2CW110_OFFSVAL(value) ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos))) +#define GMAC_ST2CW110_OFFSSTRT_Pos 7 +#define GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW110) Ethernet Frame Offset Start */ +#define GMAC_ST2CW110_OFFSSTRT(value) ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos))) +#define GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW110) Offset from the start of the frame */ +#define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the IP header field */ +#define GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW011 : (GMAC Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) -------- */ +#define GMAC_ST2CW011_MASKVAL_Pos 0 +#define GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos) /**< \brief (GMAC_ST2CW011) Mask Value */ +#define GMAC_ST2CW011_MASKVAL(value) ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos))) +#define GMAC_ST2CW011_COMPVAL_Pos 16 +#define GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos) /**< \brief (GMAC_ST2CW011) Compare Value */ +#define GMAC_ST2CW011_COMPVAL(value) ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos))) +/* -------- GMAC_ST2CW111 : (GMAC Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) -------- */ +#define GMAC_ST2CW111_OFFSVAL_Pos 0 +#define GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW111) Offset Value in Bytes */ +#define GMAC_ST2CW111_OFFSVAL(value) ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos))) +#define GMAC_ST2CW111_OFFSSTRT_Pos 7 +#define GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW111) Ethernet Frame Offset Start */ +#define GMAC_ST2CW111_OFFSSTRT(value) ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos))) +#define GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW111) Offset from the start of the frame */ +#define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the IP header field */ +#define GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW012 : (GMAC Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) -------- */ +#define GMAC_ST2CW012_MASKVAL_Pos 0 +#define GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos) /**< \brief (GMAC_ST2CW012) Mask Value */ +#define GMAC_ST2CW012_MASKVAL(value) ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos))) +#define GMAC_ST2CW012_COMPVAL_Pos 16 +#define GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos) /**< \brief (GMAC_ST2CW012) Compare Value */ +#define GMAC_ST2CW012_COMPVAL(value) ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos))) +/* -------- GMAC_ST2CW112 : (GMAC Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) -------- */ +#define GMAC_ST2CW112_OFFSVAL_Pos 0 +#define GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW112) Offset Value in Bytes */ +#define GMAC_ST2CW112_OFFSVAL(value) ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos))) +#define GMAC_ST2CW112_OFFSSTRT_Pos 7 +#define GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW112) Ethernet Frame Offset Start */ +#define GMAC_ST2CW112_OFFSSTRT(value) ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos))) +#define GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW112) Offset from the start of the frame */ +#define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the IP header field */ +#define GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW013 : (GMAC Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) -------- */ +#define GMAC_ST2CW013_MASKVAL_Pos 0 +#define GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos) /**< \brief (GMAC_ST2CW013) Mask Value */ +#define GMAC_ST2CW013_MASKVAL(value) ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos))) +#define GMAC_ST2CW013_COMPVAL_Pos 16 +#define GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos) /**< \brief (GMAC_ST2CW013) Compare Value */ +#define GMAC_ST2CW013_COMPVAL(value) ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos))) +/* -------- GMAC_ST2CW113 : (GMAC Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) -------- */ +#define GMAC_ST2CW113_OFFSVAL_Pos 0 +#define GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW113) Offset Value in Bytes */ +#define GMAC_ST2CW113_OFFSVAL(value) ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos))) +#define GMAC_ST2CW113_OFFSSTRT_Pos 7 +#define GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW113) Ethernet Frame Offset Start */ +#define GMAC_ST2CW113_OFFSSTRT(value) ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos))) +#define GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW113) Offset from the start of the frame */ +#define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the IP header field */ +#define GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW014 : (GMAC Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) -------- */ +#define GMAC_ST2CW014_MASKVAL_Pos 0 +#define GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos) /**< \brief (GMAC_ST2CW014) Mask Value */ +#define GMAC_ST2CW014_MASKVAL(value) ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos))) +#define GMAC_ST2CW014_COMPVAL_Pos 16 +#define GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos) /**< \brief (GMAC_ST2CW014) Compare Value */ +#define GMAC_ST2CW014_COMPVAL(value) ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos))) +/* -------- GMAC_ST2CW114 : (GMAC Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) -------- */ +#define GMAC_ST2CW114_OFFSVAL_Pos 0 +#define GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW114) Offset Value in Bytes */ +#define GMAC_ST2CW114_OFFSVAL(value) ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos))) +#define GMAC_ST2CW114_OFFSSTRT_Pos 7 +#define GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW114) Ethernet Frame Offset Start */ +#define GMAC_ST2CW114_OFFSSTRT(value) ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos))) +#define GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW114) Offset from the start of the frame */ +#define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the IP header field */ +#define GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW015 : (GMAC Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) -------- */ +#define GMAC_ST2CW015_MASKVAL_Pos 0 +#define GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos) /**< \brief (GMAC_ST2CW015) Mask Value */ +#define GMAC_ST2CW015_MASKVAL(value) ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos))) +#define GMAC_ST2CW015_COMPVAL_Pos 16 +#define GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos) /**< \brief (GMAC_ST2CW015) Compare Value */ +#define GMAC_ST2CW015_COMPVAL(value) ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos))) +/* -------- GMAC_ST2CW115 : (GMAC Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) -------- */ +#define GMAC_ST2CW115_OFFSVAL_Pos 0 +#define GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW115) Offset Value in Bytes */ +#define GMAC_ST2CW115_OFFSVAL(value) ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos))) +#define GMAC_ST2CW115_OFFSSTRT_Pos 7 +#define GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW115) Ethernet Frame Offset Start */ +#define GMAC_ST2CW115_OFFSSTRT(value) ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos))) +#define GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW115) Offset from the start of the frame */ +#define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the IP header field */ +#define GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW016 : (GMAC Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) -------- */ +#define GMAC_ST2CW016_MASKVAL_Pos 0 +#define GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos) /**< \brief (GMAC_ST2CW016) Mask Value */ +#define GMAC_ST2CW016_MASKVAL(value) ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos))) +#define GMAC_ST2CW016_COMPVAL_Pos 16 +#define GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos) /**< \brief (GMAC_ST2CW016) Compare Value */ +#define GMAC_ST2CW016_COMPVAL(value) ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos))) +/* -------- GMAC_ST2CW116 : (GMAC Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) -------- */ +#define GMAC_ST2CW116_OFFSVAL_Pos 0 +#define GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW116) Offset Value in Bytes */ +#define GMAC_ST2CW116_OFFSVAL(value) ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos))) +#define GMAC_ST2CW116_OFFSSTRT_Pos 7 +#define GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW116) Ethernet Frame Offset Start */ +#define GMAC_ST2CW116_OFFSSTRT(value) ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos))) +#define GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW116) Offset from the start of the frame */ +#define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the IP header field */ +#define GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW017 : (GMAC Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) -------- */ +#define GMAC_ST2CW017_MASKVAL_Pos 0 +#define GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos) /**< \brief (GMAC_ST2CW017) Mask Value */ +#define GMAC_ST2CW017_MASKVAL(value) ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos))) +#define GMAC_ST2CW017_COMPVAL_Pos 16 +#define GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos) /**< \brief (GMAC_ST2CW017) Compare Value */ +#define GMAC_ST2CW017_COMPVAL(value) ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos))) +/* -------- GMAC_ST2CW117 : (GMAC Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) -------- */ +#define GMAC_ST2CW117_OFFSVAL_Pos 0 +#define GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW117) Offset Value in Bytes */ +#define GMAC_ST2CW117_OFFSVAL(value) ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos))) +#define GMAC_ST2CW117_OFFSSTRT_Pos 7 +#define GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW117) Ethernet Frame Offset Start */ +#define GMAC_ST2CW117_OFFSSTRT(value) ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos))) +#define GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW117) Offset from the start of the frame */ +#define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the IP header field */ +#define GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW018 : (GMAC Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) -------- */ +#define GMAC_ST2CW018_MASKVAL_Pos 0 +#define GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos) /**< \brief (GMAC_ST2CW018) Mask Value */ +#define GMAC_ST2CW018_MASKVAL(value) ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos))) +#define GMAC_ST2CW018_COMPVAL_Pos 16 +#define GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos) /**< \brief (GMAC_ST2CW018) Compare Value */ +#define GMAC_ST2CW018_COMPVAL(value) ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos))) +/* -------- GMAC_ST2CW118 : (GMAC Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) -------- */ +#define GMAC_ST2CW118_OFFSVAL_Pos 0 +#define GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW118) Offset Value in Bytes */ +#define GMAC_ST2CW118_OFFSVAL(value) ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos))) +#define GMAC_ST2CW118_OFFSSTRT_Pos 7 +#define GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW118) Ethernet Frame Offset Start */ +#define GMAC_ST2CW118_OFFSSTRT(value) ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos))) +#define GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW118) Offset from the start of the frame */ +#define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the IP header field */ +#define GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW019 : (GMAC Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) -------- */ +#define GMAC_ST2CW019_MASKVAL_Pos 0 +#define GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos) /**< \brief (GMAC_ST2CW019) Mask Value */ +#define GMAC_ST2CW019_MASKVAL(value) ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos))) +#define GMAC_ST2CW019_COMPVAL_Pos 16 +#define GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos) /**< \brief (GMAC_ST2CW019) Compare Value */ +#define GMAC_ST2CW019_COMPVAL(value) ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos))) +/* -------- GMAC_ST2CW119 : (GMAC Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) -------- */ +#define GMAC_ST2CW119_OFFSVAL_Pos 0 +#define GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW119) Offset Value in Bytes */ +#define GMAC_ST2CW119_OFFSVAL(value) ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos))) +#define GMAC_ST2CW119_OFFSSTRT_Pos 7 +#define GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW119) Ethernet Frame Offset Start */ +#define GMAC_ST2CW119_OFFSSTRT(value) ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos))) +#define GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW119) Offset from the start of the frame */ +#define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the IP header field */ +#define GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW020 : (GMAC Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) -------- */ +#define GMAC_ST2CW020_MASKVAL_Pos 0 +#define GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos) /**< \brief (GMAC_ST2CW020) Mask Value */ +#define GMAC_ST2CW020_MASKVAL(value) ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos))) +#define GMAC_ST2CW020_COMPVAL_Pos 16 +#define GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos) /**< \brief (GMAC_ST2CW020) Compare Value */ +#define GMAC_ST2CW020_COMPVAL(value) ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos))) +/* -------- GMAC_ST2CW120 : (GMAC Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) -------- */ +#define GMAC_ST2CW120_OFFSVAL_Pos 0 +#define GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW120) Offset Value in Bytes */ +#define GMAC_ST2CW120_OFFSVAL(value) ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos))) +#define GMAC_ST2CW120_OFFSSTRT_Pos 7 +#define GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW120) Ethernet Frame Offset Start */ +#define GMAC_ST2CW120_OFFSSTRT(value) ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos))) +#define GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW120) Offset from the start of the frame */ +#define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the IP header field */ +#define GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW021 : (GMAC Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) -------- */ +#define GMAC_ST2CW021_MASKVAL_Pos 0 +#define GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos) /**< \brief (GMAC_ST2CW021) Mask Value */ +#define GMAC_ST2CW021_MASKVAL(value) ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos))) +#define GMAC_ST2CW021_COMPVAL_Pos 16 +#define GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos) /**< \brief (GMAC_ST2CW021) Compare Value */ +#define GMAC_ST2CW021_COMPVAL(value) ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos))) +/* -------- GMAC_ST2CW121 : (GMAC Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) -------- */ +#define GMAC_ST2CW121_OFFSVAL_Pos 0 +#define GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW121) Offset Value in Bytes */ +#define GMAC_ST2CW121_OFFSVAL(value) ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos))) +#define GMAC_ST2CW121_OFFSSTRT_Pos 7 +#define GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW121) Ethernet Frame Offset Start */ +#define GMAC_ST2CW121_OFFSSTRT(value) ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos))) +#define GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW121) Offset from the start of the frame */ +#define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the IP header field */ +#define GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW022 : (GMAC Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) -------- */ +#define GMAC_ST2CW022_MASKVAL_Pos 0 +#define GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos) /**< \brief (GMAC_ST2CW022) Mask Value */ +#define GMAC_ST2CW022_MASKVAL(value) ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos))) +#define GMAC_ST2CW022_COMPVAL_Pos 16 +#define GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos) /**< \brief (GMAC_ST2CW022) Compare Value */ +#define GMAC_ST2CW022_COMPVAL(value) ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos))) +/* -------- GMAC_ST2CW122 : (GMAC Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) -------- */ +#define GMAC_ST2CW122_OFFSVAL_Pos 0 +#define GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW122) Offset Value in Bytes */ +#define GMAC_ST2CW122_OFFSVAL(value) ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos))) +#define GMAC_ST2CW122_OFFSSTRT_Pos 7 +#define GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW122) Ethernet Frame Offset Start */ +#define GMAC_ST2CW122_OFFSSTRT(value) ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos))) +#define GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW122) Offset from the start of the frame */ +#define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the IP header field */ +#define GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW023 : (GMAC Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) -------- */ +#define GMAC_ST2CW023_MASKVAL_Pos 0 +#define GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos) /**< \brief (GMAC_ST2CW023) Mask Value */ +#define GMAC_ST2CW023_MASKVAL(value) ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos))) +#define GMAC_ST2CW023_COMPVAL_Pos 16 +#define GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos) /**< \brief (GMAC_ST2CW023) Compare Value */ +#define GMAC_ST2CW023_COMPVAL(value) ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos))) +/* -------- GMAC_ST2CW123 : (GMAC Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) -------- */ +#define GMAC_ST2CW123_OFFSVAL_Pos 0 +#define GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW123) Offset Value in Bytes */ +#define GMAC_ST2CW123_OFFSVAL(value) ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos))) +#define GMAC_ST2CW123_OFFSSTRT_Pos 7 +#define GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW123) Ethernet Frame Offset Start */ +#define GMAC_ST2CW123_OFFSSTRT(value) ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos))) +#define GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW123) Offset from the start of the frame */ +#define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the IP header field */ +#define GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field */ + +/*@}*/ + + +#endif /* _SAMV71_GMAC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_gpbr.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_gpbr.h new file mode 100644 index 0000000000..8a1af5f2a9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_gpbr.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_GPBR_COMPONENT_ +#define _SAMV71_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */ +/* ============================================================================= */ +/** \addtogroup SAMV71_GPBR General Purpose Backup Registers */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_GPBR_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_hsmci.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_hsmci.h new file mode 100644 index 0000000000..f50b93deed --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_hsmci.h @@ -0,0 +1,342 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_HSMCI_COMPONENT_ +#define _SAMV71_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + __I uint32_t Reserved1[2]; + __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + __I uint32_t Reserved2[35]; + __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[4]; + __I uint32_t HSMCI_VERSION; /**< \brief (Hsmci Offset: 0xFC) Version Register */ + __I uint32_t Reserved4[64]; + __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos))) +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos))) +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos))) +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos))) +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos))) +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos))) +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos))) +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos))) +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))) +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos))) +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended (cleared on read) */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error (cleared on read) */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error (cleared on read) */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error (cleared on read) */ +#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error (cleared on read) */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ +#define HSMCI_DMA_CHKSIZE_Pos 4 +#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos))) +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */ +#define HSMCI_WPMR_WPKEY_Pos 8 +#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */ +#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos))) +#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WPVSRC_Pos 8 +#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */ +/* -------- HSMCI_VERSION : (HSMCI Offset: 0xFC) Version Register -------- */ +#define HSMCI_VERSION_VERSION_Pos 0 +#define HSMCI_VERSION_VERSION_Msk (0xfffu << HSMCI_VERSION_VERSION_Pos) /**< \brief (HSMCI_VERSION) Hardware Module Version */ +#define HSMCI_VERSION_MFN_Pos 16 +#define HSMCI_VERSION_MFN_Msk (0x7u << HSMCI_VERSION_MFN_Pos) /**< \brief (HSMCI_VERSION) Metal Fix Number */ +/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_HSMCI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_icm.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_icm.h new file mode 100644 index 0000000000..b4d9653bb0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_icm.h @@ -0,0 +1,224 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ICM_COMPONENT_ +#define _SAMV71_ICM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */ +/* ============================================================================= */ +/** \addtogroup SAMV71_ICM Integrity Check Monitor */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Icm hardware registers */ +typedef struct { + __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */ + __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */ + __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */ + __I uint32_t Reserved3[37]; + __I uint32_t ICM_ADDRSIZE; /**< \brief (Icm Offset: 0xEC) Address Size Register */ + __I uint32_t ICM_IPNAME[2]; /**< \brief (Icm Offset: 0xF0) IP Name 1 Register */ + __I uint32_t ICM_FEATURES; /**< \brief (Icm Offset: 0xF8) Feature Register */ + __I uint32_t ICM_VERSION; /**< \brief (Icm Offset: 0xFC) Version Register */ +} Icm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */ +#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */ +#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */ +#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */ +#define ICM_CFG_BBC_Pos 4 +#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */ +#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))) +#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */ +#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */ +#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */ +#define ICM_CFG_UALGO_Pos 13 +#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */ +#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))) +#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_HAPROT_Pos 16 +#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */ +#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))) +#define ICM_CFG_DAPROT_Pos 24 +#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */ +#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))) +/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */ +#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */ +#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */ +#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */ +#define ICM_CTRL_REHASH_Pos 4 +#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */ +#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))) +#define ICM_CTRL_RMDIS_Pos 8 +#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */ +#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))) +#define ICM_CTRL_RMEN_Pos 12 +#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */ +#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))) +/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */ +#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */ +#define ICM_SR_RAWRMDIS_Pos 8 +#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Raw Status */ +#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))) +#define ICM_SR_RMDIS_Pos 12 +#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */ +#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))) +/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */ +#define ICM_IER_RHC_Pos 0 +#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */ +#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))) +#define ICM_IER_RDM_Pos 4 +#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */ +#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))) +#define ICM_IER_RBE_Pos 8 +#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */ +#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))) +#define ICM_IER_RWC_Pos 12 +#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */ +#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))) +#define ICM_IER_REC_Pos 16 +#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */ +#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))) +#define ICM_IER_RSU_Pos 20 +#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */ +#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))) +#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */ +/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */ +#define ICM_IDR_RHC_Pos 0 +#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */ +#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))) +#define ICM_IDR_RDM_Pos 4 +#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */ +#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))) +#define ICM_IDR_RBE_Pos 8 +#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */ +#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))) +#define ICM_IDR_RWC_Pos 12 +#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */ +#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))) +#define ICM_IDR_REC_Pos 16 +#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */ +#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))) +#define ICM_IDR_RSU_Pos 20 +#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */ +#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))) +#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */ +/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */ +#define ICM_IMR_RHC_Pos 0 +#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */ +#define ICM_IMR_RDM_Pos 4 +#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */ +#define ICM_IMR_RBE_Pos 8 +#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */ +#define ICM_IMR_RWC_Pos 12 +#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */ +#define ICM_IMR_REC_Pos 16 +#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */ +#define ICM_IMR_RSU_Pos 20 +#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */ +#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */ +/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */ +#define ICM_ISR_RHC_Pos 0 +#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */ +#define ICM_ISR_RDM_Pos 4 +#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */ +#define ICM_ISR_RBE_Pos 8 +#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */ +#define ICM_ISR_RWC_Pos 12 +#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */ +#define ICM_ISR_REC_Pos 16 +#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */ +#define ICM_ISR_RSU_Pos 20 +#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */ +#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */ +/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */ +#define ICM_UASR_URAT_Pos 0 +#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */ +/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */ +#define ICM_DSCR_DASA_Pos 6 +#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */ +#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))) +/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */ +#define ICM_HASH_HASA_Pos 7 +#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */ +#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))) +/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */ +#define ICM_UIHVAL_VAL_Pos 0 +#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */ +#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))) +/* -------- ICM_ADDRSIZE : (ICM Offset: 0xEC) Address Size Register -------- */ +#define ICM_ADDRSIZE_ADDRSIZE_Pos 0 +#define ICM_ADDRSIZE_ADDRSIZE_Msk (0xffffu << ICM_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (ICM_ADDRSIZE) Peripheral Bus Address Area Size */ +/* -------- ICM_IPNAME[2] : (ICM Offset: 0xF0) IP Name 1 Register -------- */ +#define ICM_IPNAME_IPNAME_Pos 0 +#define ICM_IPNAME_IPNAME_Msk (0xffffffffu << ICM_IPNAME_IPNAME_Pos) /**< \brief (ICM_IPNAME[2]) IP Name in ASCII Format */ +/* -------- ICM_FEATURES : (ICM Offset: 0xF8) Feature Register -------- */ +#define ICM_FEATURES_CFGALGO (0x1u << 0) /**< \brief (ICM_FEATURES) Configurable Algorithms */ +#define ICM_FEATURES_RFU (0x1u << 1) /**< \brief (ICM_FEATURES) Reserved for Future Use */ +#define ICM_FEATURES_CFGPP (0x1u << 2) /**< \brief (ICM_FEATURES) Configurable Processing Period */ +#define ICM_FEATURES_HDPP (0x1u << 3) /**< \brief (ICM_FEATURES) Hardcoded Processing Period */ +#define ICM_FEATURES_PDC (0x1u << 4) /**< \brief (ICM_FEATURES) Peripheral DMA Logic */ +#define ICM_FEATURES_NAIS (0x1u << 5) /**< \brief (ICM_FEATURES) No Access to Intermediate State */ +#define ICM_FEATURES_EF (0x1u << 6) /**< \brief (ICM_FEATURES) Embedded LFSR */ +#define ICM_FEATURES_SI (0x1u << 7) /**< \brief (ICM_FEATURES) Scan Intrusion */ +#define ICM_FEATURES_BTYP (0x1u << 8) /**< \brief (ICM_FEATURES) Bridge Type */ +#define ICM_FEATURES_PDCOFF0C (0x1u << 9) /**< \brief (ICM_FEATURES) PDC Offset is 0x0C */ +#define ICM_FEATURES_HSHA1 (0x1u << 16) /**< \brief (ICM_FEATURES) SHA1 Hardcoded Mode */ +#define ICM_FEATURES_HSHA224 (0x1u << 17) /**< \brief (ICM_FEATURES) SHA224 Hardcoded Mode */ +#define ICM_FEATURES_HSHA256 (0x1u << 18) /**< \brief (ICM_FEATURES) SHA256 Hardcoded Mode */ +#define ICM_FEATURES_HSHA384 (0x1u << 19) /**< \brief (ICM_FEATURES) SHA384 Hardcoded Mode */ +#define ICM_FEATURES_HSHA512 (0x1u << 20) /**< \brief (ICM_FEATURES) SHA512 Hardcoded Mode */ +/* -------- ICM_VERSION : (ICM Offset: 0xFC) Version Register -------- */ +#define ICM_VERSION_VERSION_Pos 0 +#define ICM_VERSION_VERSION_Msk (0xfffu << ICM_VERSION_VERSION_Pos) /**< \brief (ICM_VERSION) Version of the Hardware Module */ +#define ICM_VERSION_MFN_Pos 16 +#define ICM_VERSION_MFN_Msk (0x7u << ICM_VERSION_MFN_Pos) /**< \brief (ICM_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_ICM_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_isi.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_isi.h new file mode 100644 index 0000000000..063bfb2c16 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_isi.h @@ -0,0 +1,287 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ISI_COMPONENT_ +#define _SAMV71_ISI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Image Sensor Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_ISI Image Sensor Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Isi hardware registers */ +typedef struct { + __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */ + __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */ + __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */ + __I uint32_t Reserved1[34]; + __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved2[4]; + __I uint32_t ISI_VERSION; /**< \brief (Isi Offset: 0xFC) Version Register */ +} Isi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */ +#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */ +#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */ +#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */ +#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */ +#define ISI_CFG1_FRATE_Pos 8 +#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */ +#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))) +#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */ +#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */ +#define ISI_CFG1_THMASK_Pos 13 +#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */ +#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos))) +#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_SLD_Pos 16 +#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */ +#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))) +#define ISI_CFG1_SFD_Pos 24 +#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */ +#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))) +/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos 0 +#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))) +#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */ +#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */ +#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */ +#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */ +#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */ +#define ISI_CFG2_IM_HSIZE_Pos 16 +#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))) +#define ISI_CFG2_YCC_SWAP_Pos 28 +#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */ +#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))) +#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_RGB_CFG_Pos 30 +#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */ +#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))) +#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos 0 +#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */ +#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))) +#define ISI_PSIZE_PREV_HSIZE_Pos 16 +#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */ +#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))) +/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos 0 +#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */ +#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))) +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos 0 +#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))) +#define ISI_Y2R_SET0_C1_Pos 8 +#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))) +#define ISI_Y2R_SET0_C2_Pos 16 +#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))) +#define ISI_Y2R_SET0_C3_Pos 24 +#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))) +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos 0 +#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))) +#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */ +#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */ +#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */ +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos 0 +#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))) +#define ISI_R2Y_SET0_C1_Pos 8 +#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))) +#define ISI_R2Y_SET0_C2_Pos 16 +#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))) +#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */ +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos 0 +#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))) +#define ISI_R2Y_SET1_C4_Pos 8 +#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))) +#define ISI_R2Y_SET1_C5_Pos 16 +#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */ +#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))) +#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */ +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos 0 +#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */ +#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))) +#define ISI_R2Y_SET2_C7_Pos 8 +#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */ +#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))) +#define ISI_R2Y_SET2_C8_Pos 16 +#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */ +#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))) +#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */ +/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */ +#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */ +#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */ +#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */ +#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */ +/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */ +#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */ +#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */ +#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */ +#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */ +#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */ +#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */ +#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */ +#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */ +#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */ +#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */ +/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */ +#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */ +#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */ +#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */ +#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */ +#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */ +#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */ +#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */ +#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */ +/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */ +#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */ +#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */ +#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */ +#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */ +#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */ +#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */ +/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */ +#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */ +#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */ +#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */ +#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */ +#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */ +#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */ +#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */ +#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */ +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */ +#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */ +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */ +#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */ +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */ +#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */ +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos 2 +#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */ +#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))) +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */ +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos 2 +#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */ +#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))) +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos 2 +#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */ +#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))) +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */ +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos 2 +#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */ +#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))) +/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */ +#define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */ +#define ISI_WPMR_WPKEY_Pos 8 +#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */ +#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos))) +#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */ +#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */ +#define ISI_WPSR_WPVSRC_Pos 8 +#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */ +/* -------- ISI_VERSION : (ISI Offset: 0xFC) Version Register -------- */ +#define ISI_VERSION_VERSION_Pos 0 +#define ISI_VERSION_VERSION_Msk (0xfffu << ISI_VERSION_VERSION_Pos) /**< \brief (ISI_VERSION) Version of the Hardware Module */ +#define ISI_VERSION_MFN_Pos 16 +#define ISI_VERSION_MFN_Msk (0x7u << ISI_VERSION_MFN_Pos) /**< \brief (ISI_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_ISI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_matrix.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_matrix.h new file mode 100644 index 0000000000..c8ec1289a2 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_matrix.h @@ -0,0 +1,181 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MATRIX_COMPONENT_ +#define _SAMV71_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAMV71_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MatrixPr hardware registers */ +typedef struct { + __IO uint32_t MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */ +} MatrixPr; +/** \brief Matrix hardware registers */ +#define MATRIXPR_NUMBER 9 +typedef struct { + __IO uint32_t MATRIX_MCFG[12]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + __I uint32_t Reserved2[7]; + MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 8 */ + __I uint32_t Reserved3[14]; + __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t CCFG_CAN0; /**< \brief (Matrix Offset: 0x0110) CAN0 Configuration Register */ + __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O and CAN1 Configuration Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */ + __I uint32_t Reserved6[47]; + __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */ + __I uint32_t Reserved7[4]; + __I uint32_t MATRIX_VERSION; /**< \brief (Matrix Offset: 0x01FC) Version Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG[12] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ +#define MATRIX_MCFG_ULBT_Pos 0 +#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[12]) Undefined Length Burst Type */ +#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) +#define MATRIX_MCFG_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG[12]) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG[12]) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG[12]) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG[12]) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG[12]) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG[12]) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG[12]) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG[12]) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS_M0PR_Pos 0 +#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */ +#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos))) +#define MATRIX_PRAS_M1PR_Pos 4 +#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */ +#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos))) +#define MATRIX_PRAS_M2PR_Pos 8 +#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */ +#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos))) +#define MATRIX_PRAS_M3PR_Pos 12 +#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */ +#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos))) +#define MATRIX_PRAS_M4PR_Pos 16 +#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */ +#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos))) +#define MATRIX_PRAS_M5PR_Pos 20 +#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */ +#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos))) +#define MATRIX_PRAS_M6PR_Pos 24 +#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */ +#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos))) +#define MATRIX_PRAS_M7PR_Pos 28 +#define MATRIX_PRAS_M7PR_Msk (0x3u << MATRIX_PRAS_M7PR_Pos) /**< \brief (MATRIX_PRAS) Master 7 Priority */ +#define MATRIX_PRAS_M7PR(value) ((MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos))) +/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS_M8PR_Pos 0 +#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */ +#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos))) +#define MATRIX_PRBS_M9PR_Pos 4 +#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */ +#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos))) +#define MATRIX_PRBS_M10PR_Pos 8 +#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */ +#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos))) +#define MATRIX_PRBS_M11PR_Pos 12 +#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */ +#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos))) +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */ +#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */ +#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */ +#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */ +#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */ +#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */ +#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */ +#define MATRIX_MRCR_RCB7 (0x1u << 7) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 7 */ +#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 */ +#define MATRIX_MRCR_RCB9 (0x1u << 9) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 9 */ +#define MATRIX_MRCR_RCB10 (0x1u << 10) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 10 */ +#define MATRIX_MRCR_RCB11 (0x1u << 11) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 11 */ +/* -------- CCFG_CAN0 : (MATRIX Offset: 0x0110) CAN0 Configuration Register -------- */ +#define CCFG_CAN0_CAN0DMABA_Pos 16 +#define CCFG_CAN0_CAN0DMABA_Msk (0xffffu << CCFG_CAN0_CAN0DMABA_Pos) /**< \brief (CCFG_CAN0) CAN0 DMA Base Address */ +#define CCFG_CAN0_CAN0DMABA(value) ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos))) +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O and CAN1 Configuration Register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +#define CCFG_SYSIO_CAN1DMABA_Pos 16 +#define CCFG_SYSIO_CAN1DMABA_Msk (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos) /**< \brief (CCFG_SYSIO) CAN1 DMA Base Address */ +#define CCFG_SYSIO_CAN1DMABA(value) ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos))) +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /**< \brief (CCFG_SMCNFCS) SDRAM Enable */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */ +/* -------- MATRIX_VERSION : (MATRIX Offset: 0x01FC) Version Register -------- */ +#define MATRIX_VERSION_VERSION_Pos 0 +#define MATRIX_VERSION_VERSION_Msk (0xfffu << MATRIX_VERSION_VERSION_Pos) /**< \brief (MATRIX_VERSION) Version of the Hardware Module */ +#define MATRIX_VERSION_MFN_Pos 16 +#define MATRIX_VERSION_MFN_Msk (0x7u << MATRIX_VERSION_MFN_Pos) /**< \brief (MATRIX_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_MATRIX_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h new file mode 100644 index 0000000000..cc11cd1929 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h @@ -0,0 +1,868 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MCAN_COMPONENT_ +#define _SAMV71_MCAN_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Controller Area Network */ +/* ============================================================================= */ +/** \addtogroup SAMV71_MCAN Controller Area Network */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mcan hardware registers */ +typedef struct { + __I uint32_t MCAN_CREL; /**< \brief (Mcan Offset: 0x00) Core Release Register */ + __I uint32_t MCAN_ENDN; /**< \brief (Mcan Offset: 0x04) Endian Register */ + __IO uint32_t MCAN_CUST; /**< \brief (Mcan Offset: 0x08) Customer Register */ + __IO uint32_t MCAN_FBTP; /**< \brief (Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TEST; /**< \brief (Mcan Offset: 0x10) Test Register */ + __IO uint32_t MCAN_RWD; /**< \brief (Mcan Offset: 0x14) RAM Watchdog Register */ + __IO uint32_t MCAN_CCCR; /**< \brief (Mcan Offset: 0x18) CC Control Register */ + __IO uint32_t MCAN_BTP; /**< \brief (Mcan Offset: 0x1C) Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TSCC; /**< \brief (Mcan Offset: 0x20) Timestamp Counter Configuration Register */ + __IO uint32_t MCAN_TSCV; /**< \brief (Mcan Offset: 0x24) Timestamp Counter Value Register */ + __IO uint32_t MCAN_TOCC; /**< \brief (Mcan Offset: 0x28) Timeout Counter Configuration Register */ + __IO uint32_t MCAN_TOCV; /**< \brief (Mcan Offset: 0x2C) Timeout Counter Value Register */ + __I uint32_t Reserved1[4]; + __I uint32_t MCAN_ECR; /**< \brief (Mcan Offset: 0x40) Error Counter Register */ + __I uint32_t MCAN_PSR; /**< \brief (Mcan Offset: 0x44) Protocol Status Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t MCAN_IR; /**< \brief (Mcan Offset: 0x50) Interrupt Register */ + __IO uint32_t MCAN_IE; /**< \brief (Mcan Offset: 0x54) Interrupt Enable Register */ + __IO uint32_t MCAN_ILS; /**< \brief (Mcan Offset: 0x58) Interrupt Line Select Register */ + __IO uint32_t MCAN_ILE; /**< \brief (Mcan Offset: 0x5C) Interrupt Line Enable Register */ + __I uint32_t Reserved3[8]; + __IO uint32_t MCAN_GFC; /**< \brief (Mcan Offset: 0x80) Global Filter Configuration Register */ + __IO uint32_t MCAN_SIDFC; /**< \brief (Mcan Offset: 0x84) Standard ID Filter Configuration Register */ + __IO uint32_t MCAN_XIDFC; /**< \brief (Mcan Offset: 0x88) Extended ID Filter Configuration Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t MCAN_XIDAM; /**< \brief (Mcan Offset: 0x90) Extended ID AND Mask Register */ + __I uint32_t MCAN_HPMS; /**< \brief (Mcan Offset: 0x94) High Priority Message Status Register */ + __IO uint32_t MCAN_NDAT1; /**< \brief (Mcan Offset: 0x98) New Data 1 Register */ + __IO uint32_t MCAN_NDAT2; /**< \brief (Mcan Offset: 0x9C) New Data 2 Register */ + __IO uint32_t MCAN_RXF0C; /**< \brief (Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register */ + __I uint32_t MCAN_RXF0S; /**< \brief (Mcan Offset: 0xA4) Receive FIFO 0 Status Register */ + __IO uint32_t MCAN_RXF0A; /**< \brief (Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register */ + __IO uint32_t MCAN_RXBC; /**< \brief (Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register */ + __IO uint32_t MCAN_RXF1C; /**< \brief (Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register */ + __I uint32_t MCAN_RXF1S; /**< \brief (Mcan Offset: 0xB4) Receive FIFO 1 Status Register */ + __IO uint32_t MCAN_RXF1A; /**< \brief (Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register */ + __IO uint32_t MCAN_RXESC; /**< \brief (Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register */ + __IO uint32_t MCAN_TXBC; /**< \brief (Mcan Offset: 0xC0) Transmit Buffer Configuration Register */ + __I uint32_t MCAN_TXFQS; /**< \brief (Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register */ + __IO uint32_t MCAN_TXESC; /**< \brief (Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register */ + __I uint32_t MCAN_TXBRP; /**< \brief (Mcan Offset: 0xCC) Transmit Buffer Request Pending Register */ + __IO uint32_t MCAN_TXBAR; /**< \brief (Mcan Offset: 0xD0) Transmit Buffer Add Request Register */ + __IO uint32_t MCAN_TXBCR; /**< \brief (Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register */ + __I uint32_t MCAN_TXBTO; /**< \brief (Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register */ + __I uint32_t MCAN_TXBCF; /**< \brief (Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register */ + __IO uint32_t MCAN_TXBTIE; /**< \brief (Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register */ + __IO uint32_t MCAN_TXBCIE; /**< \brief (Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + __I uint32_t Reserved5[2]; + __IO uint32_t MCAN_TXEFC; /**< \brief (Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register */ + __I uint32_t MCAN_TXEFS; /**< \brief (Mcan Offset: 0xF4) Transmit Event FIFO Status Register */ + __IO uint32_t MCAN_TXEFA; /**< \brief (Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register */ +} Mcan; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MCAN_CREL : (MCAN Offset: 0x00) Core Release Register -------- */ +#define MCAN_CREL_DAY_Pos 0 +#define MCAN_CREL_DAY_Msk (0xffu << MCAN_CREL_DAY_Pos) /**< \brief (MCAN_CREL) Timestamp Day */ +#define MCAN_CREL_MON_Pos 8 +#define MCAN_CREL_MON_Msk (0xffu << MCAN_CREL_MON_Pos) /**< \brief (MCAN_CREL) Timestamp Month */ +#define MCAN_CREL_YEAR_Pos 16 +#define MCAN_CREL_YEAR_Msk (0xfu << MCAN_CREL_YEAR_Pos) /**< \brief (MCAN_CREL) Timestamp Year */ +#define MCAN_CREL_SUBSTEP_Pos 20 +#define MCAN_CREL_SUBSTEP_Msk (0xfu << MCAN_CREL_SUBSTEP_Pos) /**< \brief (MCAN_CREL) Sub-step of Core Release */ +#define MCAN_CREL_STEP_Pos 24 +#define MCAN_CREL_STEP_Msk (0xfu << MCAN_CREL_STEP_Pos) /**< \brief (MCAN_CREL) Step of Core Release */ +#define MCAN_CREL_REL_Pos 28 +#define MCAN_CREL_REL_Msk (0xfu << MCAN_CREL_REL_Pos) /**< \brief (MCAN_CREL) Core Release */ +/* -------- MCAN_ENDN : (MCAN Offset: 0x04) Endian Register -------- */ +#define MCAN_ENDN_ETV_Pos 0 +#define MCAN_ENDN_ETV_Msk (0xffffffffu << MCAN_ENDN_ETV_Pos) /**< \brief (MCAN_ENDN) Endianness Test Value */ +/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */ +#define MCAN_CUST_CSV_Pos 0 +#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos) /**< \brief (MCAN_CUST) Customer-specific Value */ +#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos))) +/* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */ +#define MCAN_FBTP_FSJW_Pos 0 +#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ +#define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos))) +#define MCAN_FBTP_FTSEG2_Pos 4 +#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ +#define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos))) +#define MCAN_FBTP_FTSEG1_Pos 8 +#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ +#define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos))) +#define MCAN_FBTP_FBRP_Pos 16 +#define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos) /**< \brief (MCAN_FBTP) Fast Baud Rate Prescaler */ +#define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos))) +#define MCAN_FBTP_TDC (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation */ +#define MCAN_FBTP_TDC_DISABLED (0x0u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation disabled. */ +#define MCAN_FBTP_TDC_ENABLED (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation enabled. */ +#define MCAN_FBTP_TDCO_Pos 24 +#define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation Offset */ +#define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos))) +/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */ +#define MCAN_TEST_LBCK (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back Mode (read/write) */ +#define MCAN_TEST_LBCK_DISABLED (0x0u << 4) /**< \brief (MCAN_TEST) Reset value. Loop Back mode is disabled. */ +#define MCAN_TEST_LBCK_ENABLED (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back mode is enabled (see Section 1.5.1.9). */ +#define MCAN_TEST_TX_Pos 5 +#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos) /**< \brief (MCAN_TEST) Control of Transmit Pin (read/write) */ +#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos))) +#define MCAN_TEST_TX_RESET (0x0u << 5) /**< \brief (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5) /**< \brief (MCAN_TEST) Sample Point can be monitored at pin CANTX. */ +#define MCAN_TEST_TX_DOMINANT (0x2u << 5) /**< \brief (MCAN_TEST) Dominant ('0') level at pin CANTX. */ +#define MCAN_TEST_TX_RECESSIVE (0x3u << 5) /**< \brief (MCAN_TEST) Recessive ('1') at pin CANTX. */ +#define MCAN_TEST_RX (0x1u << 7) /**< \brief (MCAN_TEST) Receive Pin (read-only) */ +#define MCAN_TEST_TDCV_Pos 8 +#define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos) /**< \brief (MCAN_TEST) Transceiver Delay Compensation Value (read-only) */ +#define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos))) +/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */ +#define MCAN_RWD_WDC_Pos 0 +#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos) /**< \brief (MCAN_RWD) Watchdog Configuration (read/write) */ +#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos))) +#define MCAN_RWD_WDV_Pos 8 +#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos) /**< \brief (MCAN_RWD) Watchdog Value (read-only) */ +#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos))) +/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */ +#define MCAN_CCCR_INIT (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization (read/write) */ +#define MCAN_CCCR_INIT_DISABLED (0x0u << 0) /**< \brief (MCAN_CCCR) Normal operation. */ +#define MCAN_CCCR_INIT_ENABLED (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization is started. */ +#define MCAN_CCCR_CCE (0x1u << 1) /**< \brief (MCAN_CCCR) Configuration Change Enable (read/write, write protection) */ +#define MCAN_CCCR_CCE_PROTECTED (0x0u << 1) /**< \brief (MCAN_CCCR) The processor has no write access to the protected configuration registers. */ +#define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1) /**< \brief (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */ +#define MCAN_CCCR_ASM (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_ASM_NORMAL (0x0u << 2) /**< \brief (MCAN_CCCR) Normal CAN operation. */ +#define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted operation mode active. */ +#define MCAN_CCCR_CSA (0x1u << 3) /**< \brief (MCAN_CCCR) Clock Stop Acknowledge (read-only) */ +#define MCAN_CCCR_CSR (0x1u << 4) /**< \brief (MCAN_CCCR) Clock Stop Request (read/write) */ +#define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4) /**< \brief (MCAN_CCCR) No clock stop is requested. */ +#define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4) /**< \brief (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */ +#define MCAN_CCCR_MON (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_MON_DISABLED (0x0u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is disabled. */ +#define MCAN_CCCR_MON_ENABLED (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is enabled. */ +#define MCAN_CCCR_DAR (0x1u << 6) /**< \brief (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) */ +#define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission disabled. */ +#define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */ +#define MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ +#define MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ +#define MCAN_CCCR_CME_Pos 8 +#define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos) /**< \brief (MCAN_CCCR) CAN Mode Enable (read/write, write protection) */ +#define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos))) +#define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8) /**< \brief (MCAN_CCCR) CAN operation according to ISO11898-1 enabled */ +#define MCAN_CCCR_CME_FD (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD operation enabled */ +#define MCAN_CCCR_CMR_Pos 10 +#define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos) /**< \brief (MCAN_CCCR) CAN Mode Request (read/write) */ +#define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos))) +#define MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10) /**< \brief (MCAN_CCCR) No mode change */ +#define MCAN_CCCR_CMR_FD (0x1u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation */ +#define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation with bit rate switching */ +#define MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10) /**< \brief (MCAN_CCCR) Request CAN operation according ISO11898-1 */ +#define MCAN_CCCR_FDO (0x1u << 12) /**< \brief (MCAN_CCCR) CAN FD Operation (read-only) */ +#define MCAN_CCCR_FDBS (0x1u << 13) /**< \brief (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) */ +#define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */ +/* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */ +#define MCAN_BTP_SJW_Pos 0 +#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */ +#define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos))) +#define MCAN_BTP_TSEG2_Pos 4 +#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */ +#define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos))) +#define MCAN_BTP_TSEG1_Pos 8 +#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */ +#define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos))) +#define MCAN_BTP_BRP_Pos 16 +#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */ +#define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos))) +/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */ +#define MCAN_TSCC_TSS_Pos 0 +#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos) /**< \brief (MCAN_TSCC) Timestamp Select */ +#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos))) +#define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value always 0x0000 */ +#define MCAN_TSCC_TSS_TCP_INC (0x1u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value incremented according to TCP */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0) /**< \brief (MCAN_TSCC) External timestamp counter value used */ +#define MCAN_TSCC_TCP_Pos 16 +#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos) /**< \brief (MCAN_TSCC) Timestamp Counter Prescaler */ +#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos))) +/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */ +#define MCAN_TSCV_TSC_Pos 0 +#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos) /**< \brief (MCAN_TSCV) Timestamp Counter (cleared on write) */ +#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos))) +/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */ +#define MCAN_TOCC_ETOC (0x1u << 0) /**< \brief (MCAN_TOCC) Enable Timeout Counter */ +#define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0) /**< \brief (MCAN_TOCC) Timeout Counter disabled. */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0) /**< \brief (MCAN_TOCC) Timeout Counter enabled. */ +#define MCAN_TOCC_TOS_Pos 1 +#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos) /**< \brief (MCAN_TOCC) Timeout Select */ +#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos))) +#define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1) /**< \brief (MCAN_TOCC) Continuous operation */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Tx Event FIFO */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */ +#define MCAN_TOCC_TOP_Pos 16 +#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos) /**< \brief (MCAN_TOCC) Timeout Period */ +#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos))) +/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */ +#define MCAN_TOCV_TOC_Pos 0 +#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos) /**< \brief (MCAN_TOCV) Timeout Counter (cleared on write) */ +#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos))) +/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */ +#define MCAN_ECR_TEC_Pos 0 +#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos) /**< \brief (MCAN_ECR) Transmit Error Counter */ +#define MCAN_ECR_REC_Pos 8 +#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos) /**< \brief (MCAN_ECR) Receive Error Counter */ +#define MCAN_ECR_RP (0x1u << 15) /**< \brief (MCAN_ECR) Receive Error Passive */ +#define MCAN_ECR_CEL_Pos 16 +#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos) /**< \brief (MCAN_ECR) CAN Error Logging (cleared on read) */ +/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */ +#define MCAN_PSR_LEC_Pos 0 +#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos) /**< \brief (MCAN_PSR) Last Error Code (set to 111 on read) */ +#define MCAN_PSR_LEC_NO_ERROR (0x0u << 0) /**< \brief (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */ +#define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0) /**< \brief (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. */ +#define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0) /**< \brief (MCAN_PSR) A fixed format part of a received frame has the wrong format. */ +#define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0) /**< \brief (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */ +#define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */ +#define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */ +#define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0) /**< \brief (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. */ +#define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0) /**< \brief (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */ +#define MCAN_PSR_ACT_Pos 3 +#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos) /**< \brief (MCAN_PSR) Activity */ +#define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3) /**< \brief (MCAN_PSR) Node is synchronizing on CAN communication */ +#define MCAN_PSR_ACT_IDLE (0x1u << 3) /**< \brief (MCAN_PSR) Node is neither receiver nor transmitter */ +#define MCAN_PSR_ACT_RECEIVER (0x2u << 3) /**< \brief (MCAN_PSR) Node is operating as receiver */ +#define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3) /**< \brief (MCAN_PSR) Node is operating as transmitter */ +#define MCAN_PSR_EP (0x1u << 5) /**< \brief (MCAN_PSR) Error Passive */ +#define MCAN_PSR_EW (0x1u << 6) /**< \brief (MCAN_PSR) Warning Status */ +#define MCAN_PSR_BO (0x1u << 7) /**< \brief (MCAN_PSR) Bus_Off Status */ +#define MCAN_PSR_FLEC_Pos 8 +#define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos) /**< \brief (MCAN_PSR) Fast Last Error Code (set to 111 on read) */ +#define MCAN_PSR_RESI (0x1u << 11) /**< \brief (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_RBRS (0x1u << 12) /**< \brief (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_REDL (0x1u << 13) /**< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) */ +/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */ +#define MCAN_IR_RF0N (0x1u << 0) /**< \brief (MCAN_IR) Receive FIFO 0 New Message */ +#define MCAN_IR_RF0W (0x1u << 1) /**< \brief (MCAN_IR) Receive FIFO 0 Watermark Reached */ +#define MCAN_IR_RF0F (0x1u << 2) /**< \brief (MCAN_IR) Receive FIFO 0 Full */ +#define MCAN_IR_RF0L (0x1u << 3) /**< \brief (MCAN_IR) Receive FIFO 0 Message Lost */ +#define MCAN_IR_RF1N (0x1u << 4) /**< \brief (MCAN_IR) Receive FIFO 1 New Message */ +#define MCAN_IR_RF1W (0x1u << 5) /**< \brief (MCAN_IR) Receive FIFO 1 Watermark Reached */ +#define MCAN_IR_RF1F (0x1u << 6) /**< \brief (MCAN_IR) Receive FIFO 1 Full */ +#define MCAN_IR_RF1L (0x1u << 7) /**< \brief (MCAN_IR) Receive FIFO 1 Message Lost */ +#define MCAN_IR_HPM (0x1u << 8) /**< \brief (MCAN_IR) High Priority Message */ +#define MCAN_IR_TC (0x1u << 9) /**< \brief (MCAN_IR) Transmission Completed */ +#define MCAN_IR_TCF (0x1u << 10) /**< \brief (MCAN_IR) Transmission Cancellation Finished */ +#define MCAN_IR_TFE (0x1u << 11) /**< \brief (MCAN_IR) Tx FIFO Empty */ +#define MCAN_IR_TEFN (0x1u << 12) /**< \brief (MCAN_IR) Tx Event FIFO New Entry */ +#define MCAN_IR_TEFW (0x1u << 13) /**< \brief (MCAN_IR) Tx Event FIFO Watermark Reached */ +#define MCAN_IR_TEFF (0x1u << 14) /**< \brief (MCAN_IR) Tx Event FIFO Full */ +#define MCAN_IR_TEFL (0x1u << 15) /**< \brief (MCAN_IR) Tx Event FIFO Element Lost */ +#define MCAN_IR_TSW (0x1u << 16) /**< \brief (MCAN_IR) Timestamp Wraparound */ +#define MCAN_IR_MRAF (0x1u << 17) /**< \brief (MCAN_IR) Message RAM Access Failure */ +#define MCAN_IR_TOO (0x1u << 18) /**< \brief (MCAN_IR) Timeout Occurred */ +#define MCAN_IR_DRX (0x1u << 19) /**< \brief (MCAN_IR) Message stored to Dedicated Receive Buffer */ +#define MCAN_IR_BEC (0x1u << 20) /**< \brief (MCAN_IR) Bit Error Corrected */ +#define MCAN_IR_BEU (0x1u << 21) /**< \brief (MCAN_IR) Bit Error Uncorrected */ +#define MCAN_IR_ELO (0x1u << 22) /**< \brief (MCAN_IR) Error Logging Overflow */ +#define MCAN_IR_EP (0x1u << 23) /**< \brief (MCAN_IR) Error Passive */ +#define MCAN_IR_EW (0x1u << 24) /**< \brief (MCAN_IR) Warning Status */ +#define MCAN_IR_BO (0x1u << 25) /**< \brief (MCAN_IR) Bus_Off Status */ +#define MCAN_IR_WDI (0x1u << 26) /**< \brief (MCAN_IR) Watchdog Interrupt */ +#define MCAN_IR_CRCE (0x1u << 27) /**< \brief (MCAN_IR) CRC Error */ +#define MCAN_IR_BE (0x1u << 28) /**< \brief (MCAN_IR) Bit Error */ +#define MCAN_IR_ACKE (0x1u << 29) /**< \brief (MCAN_IR) Acknowledge Error */ +#define MCAN_IR_FOE (0x1u << 30) /**< \brief (MCAN_IR) Format Error */ +#define MCAN_IR_STE (0x1u << 31) /**< \brief (MCAN_IR) Stuff Error */ +/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */ +#define MCAN_IE_RF0NE (0x1u << 0) /**< \brief (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable */ +#define MCAN_IE_RF0WE (0x1u << 1) /**< \brief (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF0FE (0x1u << 2) /**< \brief (MCAN_IE) Receive FIFO 0 Full Interrupt Enable */ +#define MCAN_IE_RF0LE (0x1u << 3) /**< \brief (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable */ +#define MCAN_IE_RF1NE (0x1u << 4) /**< \brief (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable */ +#define MCAN_IE_RF1WE (0x1u << 5) /**< \brief (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF1FE (0x1u << 6) /**< \brief (MCAN_IE) Receive FIFO 1 Full Interrupt Enable */ +#define MCAN_IE_RF1LE (0x1u << 7) /**< \brief (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable */ +#define MCAN_IE_HPME (0x1u << 8) /**< \brief (MCAN_IE) High Priority Message Interrupt Enable */ +#define MCAN_IE_TCE (0x1u << 9) /**< \brief (MCAN_IE) Transmission Completed Interrupt Enable */ +#define MCAN_IE_TCFE (0x1u << 10) /**< \brief (MCAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define MCAN_IE_TFEE (0x1u << 11) /**< \brief (MCAN_IE) Tx FIFO Empty Interrupt Enable */ +#define MCAN_IE_TEFNE (0x1u << 12) /**< \brief (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define MCAN_IE_TEFWE (0x1u << 13) /**< \brief (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define MCAN_IE_TEFFE (0x1u << 14) /**< \brief (MCAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define MCAN_IE_TEFLE (0x1u << 15) /**< \brief (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable */ +#define MCAN_IE_TSWE (0x1u << 16) /**< \brief (MCAN_IE) Timestamp Wraparound Interrupt Enable */ +#define MCAN_IE_MRAFE (0x1u << 17) /**< \brief (MCAN_IE) Message RAM Access Failure Interrupt Enable */ +#define MCAN_IE_TOOE (0x1u << 18) /**< \brief (MCAN_IE) Timeout Occurred Interrupt Enable */ +#define MCAN_IE_DRXE (0x1u << 19) /**< \brief (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable */ +#define MCAN_IE_BECE (0x1u << 20) /**< \brief (MCAN_IE) Bit Error Corrected Interrupt Enable */ +#define MCAN_IE_BEUE (0x1u << 21) /**< \brief (MCAN_IE) Bit Error Uncorrected Interrupt Enable */ +#define MCAN_IE_ELOE (0x1u << 22) /**< \brief (MCAN_IE) Error Logging Overflow Interrupt Enable */ +#define MCAN_IE_EPE (0x1u << 23) /**< \brief (MCAN_IE) Error Passive Interrupt Enable */ +#define MCAN_IE_EWE (0x1u << 24) /**< \brief (MCAN_IE) Warning Status Interrupt Enable */ +#define MCAN_IE_BOE (0x1u << 25) /**< \brief (MCAN_IE) Bus_Off Status Interrupt Enable */ +#define MCAN_IE_WDIE (0x1u << 26) /**< \brief (MCAN_IE) Watchdog Interrupt Enable */ +#define MCAN_IE_CRCEE (0x1u << 27) /**< \brief (MCAN_IE) CRC Error Interrupt Enable */ +#define MCAN_IE_BEE (0x1u << 28) /**< \brief (MCAN_IE) Bit Error Interrupt Enable */ +#define MCAN_IE_ACKEE (0x1u << 29) /**< \brief (MCAN_IE) Acknowledge Error Interrupt Enable */ +#define MCAN_IE_FOEE (0x1u << 30) /**< \brief (MCAN_IE) Format Error Interrupt Enable */ +#define MCAN_IE_STEE (0x1u << 31) /**< \brief (MCAN_IE) Stuff Error Interrupt Enable */ +/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */ +#define MCAN_ILS_RF0NL (0x1u << 0) /**< \brief (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line */ +#define MCAN_ILS_RF0WL (0x1u << 1) /**< \brief (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF0FL (0x1u << 2) /**< \brief (MCAN_ILS) Receive FIFO 0 Full Interrupt Line */ +#define MCAN_ILS_RF0LL (0x1u << 3) /**< \brief (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line */ +#define MCAN_ILS_RF1NL (0x1u << 4) /**< \brief (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line */ +#define MCAN_ILS_RF1WL (0x1u << 5) /**< \brief (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF1FL (0x1u << 6) /**< \brief (MCAN_ILS) Receive FIFO 1 Full Interrupt Line */ +#define MCAN_ILS_RF1LL (0x1u << 7) /**< \brief (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line */ +#define MCAN_ILS_HPML (0x1u << 8) /**< \brief (MCAN_ILS) High Priority Message Interrupt Line */ +#define MCAN_ILS_TCL (0x1u << 9) /**< \brief (MCAN_ILS) Transmission Completed Interrupt Line */ +#define MCAN_ILS_TCFL (0x1u << 10) /**< \brief (MCAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define MCAN_ILS_TFEL (0x1u << 11) /**< \brief (MCAN_ILS) Tx FIFO Empty Interrupt Line */ +#define MCAN_ILS_TEFNL (0x1u << 12) /**< \brief (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define MCAN_ILS_TEFWL (0x1u << 13) /**< \brief (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define MCAN_ILS_TEFFL (0x1u << 14) /**< \brief (MCAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define MCAN_ILS_TEFLL (0x1u << 15) /**< \brief (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line */ +#define MCAN_ILS_TSWL (0x1u << 16) /**< \brief (MCAN_ILS) Timestamp Wraparound Interrupt Line */ +#define MCAN_ILS_MRAFL (0x1u << 17) /**< \brief (MCAN_ILS) Message RAM Access Failure Interrupt Line */ +#define MCAN_ILS_TOOL (0x1u << 18) /**< \brief (MCAN_ILS) Timeout Occurred Interrupt Line */ +#define MCAN_ILS_DRXL (0x1u << 19) /**< \brief (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line */ +#define MCAN_ILS_BECL (0x1u << 20) /**< \brief (MCAN_ILS) Bit Error Corrected Interrupt Line */ +#define MCAN_ILS_BEUL (0x1u << 21) /**< \brief (MCAN_ILS) Bit Error Uncorrected Interrupt Line */ +#define MCAN_ILS_ELOL (0x1u << 22) /**< \brief (MCAN_ILS) Error Logging Overflow Interrupt Line */ +#define MCAN_ILS_EPL (0x1u << 23) /**< \brief (MCAN_ILS) Error Passive Interrupt Line */ +#define MCAN_ILS_EWL (0x1u << 24) /**< \brief (MCAN_ILS) Warning Status Interrupt Line */ +#define MCAN_ILS_BOL (0x1u << 25) /**< \brief (MCAN_ILS) Bus_Off Status Interrupt Line */ +#define MCAN_ILS_WDIL (0x1u << 26) /**< \brief (MCAN_ILS) Watchdog Interrupt Line */ +#define MCAN_ILS_CRCEL (0x1u << 27) /**< \brief (MCAN_ILS) CRC Error Interrupt Line */ +#define MCAN_ILS_BEL (0x1u << 28) /**< \brief (MCAN_ILS) Bit Error Interrupt Line */ +#define MCAN_ILS_ACKEL (0x1u << 29) /**< \brief (MCAN_ILS) Acknowledge Error Interrupt Line */ +#define MCAN_ILS_FOEL (0x1u << 30) /**< \brief (MCAN_ILS) Format Error Interrupt Line */ +#define MCAN_ILS_STEL (0x1u << 31) /**< \brief (MCAN_ILS) Stuff Error Interrupt Line */ +/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */ +#define MCAN_ILE_EINT0 (0x1u << 0) /**< \brief (MCAN_ILE) Enable Interrupt Line 0 */ +#define MCAN_ILE_EINT1 (0x1u << 1) /**< \brief (MCAN_ILE) Enable Interrupt Line 1 */ +/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */ +#define MCAN_GFC_RRFE (0x1u << 0) /**< \brief (MCAN_GFC) Reject Remote Frames Extended */ +#define MCAN_GFC_RRFE_FILTER (0x0u << 0) /**< \brief (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_REJECT (0x1u << 0) /**< \brief (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFS (0x1u << 1) /**< \brief (MCAN_GFC) Reject Remote Frames Standard */ +#define MCAN_GFC_RRFS_FILTER (0x0u << 1) /**< \brief (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_REJECT (0x1u << 1) /**< \brief (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_ANFE_Pos 2 +#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Extended */ +#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos))) +#define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +#define MCAN_GFC_ANFS_Pos 4 +#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Standard */ +#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos))) +#define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */ +#define MCAN_SIDFC_FLSSA_Pos 2 +#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos) /**< \brief (MCAN_SIDFC) Filter List Standard Start Address */ +#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos))) +#define MCAN_SIDFC_LSS_Pos 16 +#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos) /**< \brief (MCAN_SIDFC) List Size Standard */ +#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos))) +/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */ +#define MCAN_XIDFC_FLESA_Pos 2 +#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos) /**< \brief (MCAN_XIDFC) Filter List Extended Start Address */ +#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos))) +#define MCAN_XIDFC_LSE_Pos 16 +#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos) /**< \brief (MCAN_XIDFC) List Size Extended */ +#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos))) +/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */ +#define MCAN_XIDAM_EIDM_Pos 0 +#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos) /**< \brief (MCAN_XIDAM) Extended ID Mask */ +#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos))) +/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */ +#define MCAN_HPMS_BIDX_Pos 0 +#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos) /**< \brief (MCAN_HPMS) Buffer Index */ +#define MCAN_HPMS_MSI_Pos 6 +#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos) /**< \brief (MCAN_HPMS) Message Storage Indicator */ +#define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6) /**< \brief (MCAN_HPMS) No FIFO selected. */ +#define MCAN_HPMS_MSI_LOST (0x1u << 6) /**< \brief (MCAN_HPMS) FIFO message. */ +#define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 0. */ +#define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 1. */ +#define MCAN_HPMS_FIDX_Pos 8 +#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos) /**< \brief (MCAN_HPMS) Filter Index */ +#define MCAN_HPMS_FLST (0x1u << 15) /**< \brief (MCAN_HPMS) Filter List */ +/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */ +#define MCAN_NDAT1_ND0 (0x1u << 0) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND1 (0x1u << 1) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND2 (0x1u << 2) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND3 (0x1u << 3) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND4 (0x1u << 4) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND5 (0x1u << 5) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND6 (0x1u << 6) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND7 (0x1u << 7) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND8 (0x1u << 8) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND9 (0x1u << 9) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND10 (0x1u << 10) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND11 (0x1u << 11) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND12 (0x1u << 12) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND13 (0x1u << 13) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND14 (0x1u << 14) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND15 (0x1u << 15) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND16 (0x1u << 16) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND17 (0x1u << 17) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND18 (0x1u << 18) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND19 (0x1u << 19) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND20 (0x1u << 20) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND21 (0x1u << 21) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND22 (0x1u << 22) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND23 (0x1u << 23) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND24 (0x1u << 24) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND25 (0x1u << 25) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND26 (0x1u << 26) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND27 (0x1u << 27) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND28 (0x1u << 28) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND29 (0x1u << 29) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND30 (0x1u << 30) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND31 (0x1u << 31) /**< \brief (MCAN_NDAT1) New Data */ +/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */ +#define MCAN_NDAT2_ND32 (0x1u << 0) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND33 (0x1u << 1) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND34 (0x1u << 2) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND35 (0x1u << 3) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND36 (0x1u << 4) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND37 (0x1u << 5) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND38 (0x1u << 6) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND39 (0x1u << 7) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND40 (0x1u << 8) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND41 (0x1u << 9) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND42 (0x1u << 10) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND43 (0x1u << 11) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND44 (0x1u << 12) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND45 (0x1u << 13) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND46 (0x1u << 14) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND47 (0x1u << 15) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND48 (0x1u << 16) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND49 (0x1u << 17) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND50 (0x1u << 18) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND51 (0x1u << 19) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND52 (0x1u << 20) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND53 (0x1u << 21) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND54 (0x1u << 22) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND55 (0x1u << 23) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND56 (0x1u << 24) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND57 (0x1u << 25) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND58 (0x1u << 26) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND59 (0x1u << 27) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND60 (0x1u << 28) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND61 (0x1u << 29) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND62 (0x1u << 30) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND63 (0x1u << 31) /**< \brief (MCAN_NDAT2) New Data */ +/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */ +#define MCAN_RXF0C_F0SA_Pos 2 +#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos))) +#define MCAN_RXF0C_F0S_Pos 16 +#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos))) +#define MCAN_RXF0C_F0WM_Pos 24 +#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Watermark */ +#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos))) +#define MCAN_RXF0C_F0OM (0x1u << 31) /**< \brief (MCAN_RXF0C) FIFO 0 Operation Mode */ +/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */ +#define MCAN_RXF0S_F0FL_Pos 0 +#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_F0GI_Pos 8 +#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Get Index */ +#define MCAN_RXF0S_F0PI_Pos 16 +#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Put Index */ +#define MCAN_RXF0S_F0F (0x1u << 24) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_RF0L (0x1u << 25) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Message Lost */ +/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */ +#define MCAN_RXF0A_F0AI_Pos 0 +#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos) /**< \brief (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index */ +#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos))) +/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */ +#define MCAN_RXBC_RBSA_Pos 2 +#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos) /**< \brief (MCAN_RXBC) Receive Buffer Start Address */ +#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos))) +/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */ +#define MCAN_RXF1C_F1SA_Pos 2 +#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos))) +#define MCAN_RXF1C_F1S_Pos 16 +#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos))) +#define MCAN_RXF1C_F1WM_Pos 24 +#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Watermark */ +#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos))) +#define MCAN_RXF1C_F1OM (0x1u << 31) /**< \brief (MCAN_RXF1C) FIFO 1 Operation Mode */ +/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */ +#define MCAN_RXF1S_F1FL_Pos 0 +#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_F1GI_Pos 8 +#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Get Index */ +#define MCAN_RXF1S_F1PI_Pos 16 +#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Put Index */ +#define MCAN_RXF1S_F1F (0x1u << 24) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_RF1L (0x1u << 25) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Message Lost */ +#define MCAN_RXF1S_DMS_Pos 30 +#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos) /**< \brief (MCAN_RXF1S) Debug Message Status */ +#define MCAN_RXF1S_DMS_IDLE (0x0u << 30) /**< \brief (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */ +#define MCAN_RXF1S_DMS_MSG_A (0x1u << 30) /**< \brief (MCAN_RXF1S) Debug message A received. */ +#define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B received. */ +#define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */ +/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */ +#define MCAN_RXF1A_F1AI_Pos 0 +#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos) /**< \brief (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index */ +#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos))) +/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */ +#define MCAN_RXESC_F0DS_Pos 0 +#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 0 Data Field Size */ +#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos))) +#define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0) /**< \brief (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_F1DS_Pos 4 +#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 1 Data Field Size */ +#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos))) +#define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4) /**< \brief (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_RBDS_Pos 8 +#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos) /**< \brief (MCAN_RXESC) Receive Buffer Data Field Size */ +#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos))) +#define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8) /**< \brief (MCAN_RXESC) 64-byte data field */ +/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */ +#define MCAN_TXBC_TBSA_Pos 2 +#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos) /**< \brief (MCAN_TXBC) Tx Buffers Start Address */ +#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos))) +#define MCAN_TXBC_NDTB_Pos 16 +#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos) /**< \brief (MCAN_TXBC) Number of Dedicated Transmit Buffers */ +#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos))) +#define MCAN_TXBC_TFQS_Pos 24 +#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos) /**< \brief (MCAN_TXBC) Transmit FIFO/Queue Size */ +#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos))) +#define MCAN_TXBC_TFQM (0x1u << 30) /**< \brief (MCAN_TXBC) Tx FIFO/Queue Mode */ +/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */ +#define MCAN_TXFQS_TFFL_Pos 0 +#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Free Level */ +#define MCAN_TXFQS_TFGI_Pos 8 +#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Get Index */ +#define MCAN_TXFQS_TFQPI_Pos 16 +#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Put Index */ +#define MCAN_TXFQS_TFQF (0x1u << 21) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Full */ +/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */ +#define MCAN_TXESC_TBDS_Pos 0 +#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos) /**< \brief (MCAN_TXESC) Tx Buffer Data Field Size */ +#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos))) +#define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0) /**< \brief (MCAN_TXESC) 8-byte data field */ +#define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0) /**< \brief (MCAN_TXESC) 12-byte data field */ +#define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0) /**< \brief (MCAN_TXESC) 16-byte data field */ +#define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0) /**< \brief (MCAN_TXESC) 20-byte data field */ +#define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0) /**< \brief (MCAN_TXESC) 24-byte data field */ +#define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0) /**< \brief (MCAN_TXESC) 32-byte data field */ +#define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0) /**< \brief (MCAN_TXESC) 4- byte data field */ +#define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0) /**< \brief (MCAN_TXESC) 64-byte data field */ +/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */ +#define MCAN_TXBRP_TRP0 (0x1u << 0) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 0 */ +#define MCAN_TXBRP_TRP1 (0x1u << 1) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 1 */ +#define MCAN_TXBRP_TRP2 (0x1u << 2) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 2 */ +#define MCAN_TXBRP_TRP3 (0x1u << 3) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 3 */ +#define MCAN_TXBRP_TRP4 (0x1u << 4) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 4 */ +#define MCAN_TXBRP_TRP5 (0x1u << 5) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 5 */ +#define MCAN_TXBRP_TRP6 (0x1u << 6) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 6 */ +#define MCAN_TXBRP_TRP7 (0x1u << 7) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 7 */ +#define MCAN_TXBRP_TRP8 (0x1u << 8) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 8 */ +#define MCAN_TXBRP_TRP9 (0x1u << 9) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 9 */ +#define MCAN_TXBRP_TRP10 (0x1u << 10) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 10 */ +#define MCAN_TXBRP_TRP11 (0x1u << 11) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 11 */ +#define MCAN_TXBRP_TRP12 (0x1u << 12) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 12 */ +#define MCAN_TXBRP_TRP13 (0x1u << 13) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 13 */ +#define MCAN_TXBRP_TRP14 (0x1u << 14) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 14 */ +#define MCAN_TXBRP_TRP15 (0x1u << 15) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 15 */ +#define MCAN_TXBRP_TRP16 (0x1u << 16) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 16 */ +#define MCAN_TXBRP_TRP17 (0x1u << 17) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 17 */ +#define MCAN_TXBRP_TRP18 (0x1u << 18) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 18 */ +#define MCAN_TXBRP_TRP19 (0x1u << 19) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 19 */ +#define MCAN_TXBRP_TRP20 (0x1u << 20) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 20 */ +#define MCAN_TXBRP_TRP21 (0x1u << 21) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 21 */ +#define MCAN_TXBRP_TRP22 (0x1u << 22) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 22 */ +#define MCAN_TXBRP_TRP23 (0x1u << 23) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 23 */ +#define MCAN_TXBRP_TRP24 (0x1u << 24) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 24 */ +#define MCAN_TXBRP_TRP25 (0x1u << 25) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 25 */ +#define MCAN_TXBRP_TRP26 (0x1u << 26) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 26 */ +#define MCAN_TXBRP_TRP27 (0x1u << 27) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 27 */ +#define MCAN_TXBRP_TRP28 (0x1u << 28) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 28 */ +#define MCAN_TXBRP_TRP29 (0x1u << 29) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 29 */ +#define MCAN_TXBRP_TRP30 (0x1u << 30) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 30 */ +#define MCAN_TXBRP_TRP31 (0x1u << 31) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 31 */ +/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */ +#define MCAN_TXBAR_AR0 (0x1u << 0) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 0 */ +#define MCAN_TXBAR_AR1 (0x1u << 1) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 1 */ +#define MCAN_TXBAR_AR2 (0x1u << 2) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 2 */ +#define MCAN_TXBAR_AR3 (0x1u << 3) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 3 */ +#define MCAN_TXBAR_AR4 (0x1u << 4) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 4 */ +#define MCAN_TXBAR_AR5 (0x1u << 5) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 5 */ +#define MCAN_TXBAR_AR6 (0x1u << 6) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 6 */ +#define MCAN_TXBAR_AR7 (0x1u << 7) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 7 */ +#define MCAN_TXBAR_AR8 (0x1u << 8) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 8 */ +#define MCAN_TXBAR_AR9 (0x1u << 9) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 9 */ +#define MCAN_TXBAR_AR10 (0x1u << 10) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 10 */ +#define MCAN_TXBAR_AR11 (0x1u << 11) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 11 */ +#define MCAN_TXBAR_AR12 (0x1u << 12) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 12 */ +#define MCAN_TXBAR_AR13 (0x1u << 13) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 13 */ +#define MCAN_TXBAR_AR14 (0x1u << 14) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 14 */ +#define MCAN_TXBAR_AR15 (0x1u << 15) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 15 */ +#define MCAN_TXBAR_AR16 (0x1u << 16) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 16 */ +#define MCAN_TXBAR_AR17 (0x1u << 17) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 17 */ +#define MCAN_TXBAR_AR18 (0x1u << 18) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 18 */ +#define MCAN_TXBAR_AR19 (0x1u << 19) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 19 */ +#define MCAN_TXBAR_AR20 (0x1u << 20) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 20 */ +#define MCAN_TXBAR_AR21 (0x1u << 21) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 21 */ +#define MCAN_TXBAR_AR22 (0x1u << 22) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 22 */ +#define MCAN_TXBAR_AR23 (0x1u << 23) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 23 */ +#define MCAN_TXBAR_AR24 (0x1u << 24) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 24 */ +#define MCAN_TXBAR_AR25 (0x1u << 25) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 25 */ +#define MCAN_TXBAR_AR26 (0x1u << 26) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 26 */ +#define MCAN_TXBAR_AR27 (0x1u << 27) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 27 */ +#define MCAN_TXBAR_AR28 (0x1u << 28) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 28 */ +#define MCAN_TXBAR_AR29 (0x1u << 29) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 29 */ +#define MCAN_TXBAR_AR30 (0x1u << 30) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 30 */ +#define MCAN_TXBAR_AR31 (0x1u << 31) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */ +#define MCAN_TXBCR_CR0 (0x1u << 0) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 */ +#define MCAN_TXBCR_CR1 (0x1u << 1) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 */ +#define MCAN_TXBCR_CR2 (0x1u << 2) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 */ +#define MCAN_TXBCR_CR3 (0x1u << 3) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 */ +#define MCAN_TXBCR_CR4 (0x1u << 4) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 */ +#define MCAN_TXBCR_CR5 (0x1u << 5) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 */ +#define MCAN_TXBCR_CR6 (0x1u << 6) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 */ +#define MCAN_TXBCR_CR7 (0x1u << 7) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 */ +#define MCAN_TXBCR_CR8 (0x1u << 8) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 */ +#define MCAN_TXBCR_CR9 (0x1u << 9) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 */ +#define MCAN_TXBCR_CR10 (0x1u << 10) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 */ +#define MCAN_TXBCR_CR11 (0x1u << 11) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 */ +#define MCAN_TXBCR_CR12 (0x1u << 12) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 */ +#define MCAN_TXBCR_CR13 (0x1u << 13) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 */ +#define MCAN_TXBCR_CR14 (0x1u << 14) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 */ +#define MCAN_TXBCR_CR15 (0x1u << 15) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 */ +#define MCAN_TXBCR_CR16 (0x1u << 16) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 */ +#define MCAN_TXBCR_CR17 (0x1u << 17) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 */ +#define MCAN_TXBCR_CR18 (0x1u << 18) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 */ +#define MCAN_TXBCR_CR19 (0x1u << 19) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 */ +#define MCAN_TXBCR_CR20 (0x1u << 20) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 */ +#define MCAN_TXBCR_CR21 (0x1u << 21) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 */ +#define MCAN_TXBCR_CR22 (0x1u << 22) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 */ +#define MCAN_TXBCR_CR23 (0x1u << 23) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 */ +#define MCAN_TXBCR_CR24 (0x1u << 24) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 */ +#define MCAN_TXBCR_CR25 (0x1u << 25) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 */ +#define MCAN_TXBCR_CR26 (0x1u << 26) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 */ +#define MCAN_TXBCR_CR27 (0x1u << 27) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 */ +#define MCAN_TXBCR_CR28 (0x1u << 28) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 */ +#define MCAN_TXBCR_CR29 (0x1u << 29) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 */ +#define MCAN_TXBCR_CR30 (0x1u << 30) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 */ +#define MCAN_TXBCR_CR31 (0x1u << 31) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */ +#define MCAN_TXBTO_TO0 (0x1u << 0) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 0 */ +#define MCAN_TXBTO_TO1 (0x1u << 1) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 1 */ +#define MCAN_TXBTO_TO2 (0x1u << 2) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 2 */ +#define MCAN_TXBTO_TO3 (0x1u << 3) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 3 */ +#define MCAN_TXBTO_TO4 (0x1u << 4) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 4 */ +#define MCAN_TXBTO_TO5 (0x1u << 5) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 5 */ +#define MCAN_TXBTO_TO6 (0x1u << 6) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 6 */ +#define MCAN_TXBTO_TO7 (0x1u << 7) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 7 */ +#define MCAN_TXBTO_TO8 (0x1u << 8) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 8 */ +#define MCAN_TXBTO_TO9 (0x1u << 9) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 9 */ +#define MCAN_TXBTO_TO10 (0x1u << 10) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 10 */ +#define MCAN_TXBTO_TO11 (0x1u << 11) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 11 */ +#define MCAN_TXBTO_TO12 (0x1u << 12) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 12 */ +#define MCAN_TXBTO_TO13 (0x1u << 13) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 13 */ +#define MCAN_TXBTO_TO14 (0x1u << 14) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 14 */ +#define MCAN_TXBTO_TO15 (0x1u << 15) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 15 */ +#define MCAN_TXBTO_TO16 (0x1u << 16) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 16 */ +#define MCAN_TXBTO_TO17 (0x1u << 17) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 17 */ +#define MCAN_TXBTO_TO18 (0x1u << 18) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 18 */ +#define MCAN_TXBTO_TO19 (0x1u << 19) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 19 */ +#define MCAN_TXBTO_TO20 (0x1u << 20) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 20 */ +#define MCAN_TXBTO_TO21 (0x1u << 21) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 21 */ +#define MCAN_TXBTO_TO22 (0x1u << 22) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 22 */ +#define MCAN_TXBTO_TO23 (0x1u << 23) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 23 */ +#define MCAN_TXBTO_TO24 (0x1u << 24) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 24 */ +#define MCAN_TXBTO_TO25 (0x1u << 25) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 25 */ +#define MCAN_TXBTO_TO26 (0x1u << 26) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 26 */ +#define MCAN_TXBTO_TO27 (0x1u << 27) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 27 */ +#define MCAN_TXBTO_TO28 (0x1u << 28) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 28 */ +#define MCAN_TXBTO_TO29 (0x1u << 29) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 29 */ +#define MCAN_TXBTO_TO30 (0x1u << 30) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 30 */ +#define MCAN_TXBTO_TO31 (0x1u << 31) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 31 */ +/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */ +#define MCAN_TXBCF_CF0 (0x1u << 0) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 */ +#define MCAN_TXBCF_CF1 (0x1u << 1) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 */ +#define MCAN_TXBCF_CF2 (0x1u << 2) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 */ +#define MCAN_TXBCF_CF3 (0x1u << 3) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 */ +#define MCAN_TXBCF_CF4 (0x1u << 4) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 */ +#define MCAN_TXBCF_CF5 (0x1u << 5) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 */ +#define MCAN_TXBCF_CF6 (0x1u << 6) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 */ +#define MCAN_TXBCF_CF7 (0x1u << 7) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 */ +#define MCAN_TXBCF_CF8 (0x1u << 8) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 */ +#define MCAN_TXBCF_CF9 (0x1u << 9) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 */ +#define MCAN_TXBCF_CF10 (0x1u << 10) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 */ +#define MCAN_TXBCF_CF11 (0x1u << 11) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 */ +#define MCAN_TXBCF_CF12 (0x1u << 12) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 */ +#define MCAN_TXBCF_CF13 (0x1u << 13) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 */ +#define MCAN_TXBCF_CF14 (0x1u << 14) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 */ +#define MCAN_TXBCF_CF15 (0x1u << 15) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 */ +#define MCAN_TXBCF_CF16 (0x1u << 16) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 */ +#define MCAN_TXBCF_CF17 (0x1u << 17) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 */ +#define MCAN_TXBCF_CF18 (0x1u << 18) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 */ +#define MCAN_TXBCF_CF19 (0x1u << 19) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 */ +#define MCAN_TXBCF_CF20 (0x1u << 20) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 */ +#define MCAN_TXBCF_CF21 (0x1u << 21) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 */ +#define MCAN_TXBCF_CF22 (0x1u << 22) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 */ +#define MCAN_TXBCF_CF23 (0x1u << 23) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 */ +#define MCAN_TXBCF_CF24 (0x1u << 24) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 */ +#define MCAN_TXBCF_CF25 (0x1u << 25) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 */ +#define MCAN_TXBCF_CF26 (0x1u << 26) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 */ +#define MCAN_TXBCF_CF27 (0x1u << 27) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 */ +#define MCAN_TXBCF_CF28 (0x1u << 28) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 */ +#define MCAN_TXBCF_CF29 (0x1u << 29) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 */ +#define MCAN_TXBCF_CF30 (0x1u << 30) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 */ +#define MCAN_TXBCF_CF31 (0x1u << 31) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 */ +/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */ +#define MCAN_TXBTIE_TIE0 (0x1u << 0) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 */ +#define MCAN_TXBTIE_TIE1 (0x1u << 1) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 */ +#define MCAN_TXBTIE_TIE2 (0x1u << 2) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 */ +#define MCAN_TXBTIE_TIE3 (0x1u << 3) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 */ +#define MCAN_TXBTIE_TIE4 (0x1u << 4) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 */ +#define MCAN_TXBTIE_TIE5 (0x1u << 5) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 */ +#define MCAN_TXBTIE_TIE6 (0x1u << 6) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 */ +#define MCAN_TXBTIE_TIE7 (0x1u << 7) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 */ +#define MCAN_TXBTIE_TIE8 (0x1u << 8) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 */ +#define MCAN_TXBTIE_TIE9 (0x1u << 9) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 */ +#define MCAN_TXBTIE_TIE10 (0x1u << 10) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 */ +#define MCAN_TXBTIE_TIE11 (0x1u << 11) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 */ +#define MCAN_TXBTIE_TIE12 (0x1u << 12) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 */ +#define MCAN_TXBTIE_TIE13 (0x1u << 13) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 */ +#define MCAN_TXBTIE_TIE14 (0x1u << 14) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 */ +#define MCAN_TXBTIE_TIE15 (0x1u << 15) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 */ +#define MCAN_TXBTIE_TIE16 (0x1u << 16) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 */ +#define MCAN_TXBTIE_TIE17 (0x1u << 17) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 */ +#define MCAN_TXBTIE_TIE18 (0x1u << 18) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 */ +#define MCAN_TXBTIE_TIE19 (0x1u << 19) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 */ +#define MCAN_TXBTIE_TIE20 (0x1u << 20) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 */ +#define MCAN_TXBTIE_TIE21 (0x1u << 21) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 */ +#define MCAN_TXBTIE_TIE22 (0x1u << 22) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 */ +#define MCAN_TXBTIE_TIE23 (0x1u << 23) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 */ +#define MCAN_TXBTIE_TIE24 (0x1u << 24) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 */ +#define MCAN_TXBTIE_TIE25 (0x1u << 25) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 */ +#define MCAN_TXBTIE_TIE26 (0x1u << 26) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 */ +#define MCAN_TXBTIE_TIE27 (0x1u << 27) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 */ +#define MCAN_TXBTIE_TIE28 (0x1u << 28) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 */ +#define MCAN_TXBTIE_TIE29 (0x1u << 29) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 */ +#define MCAN_TXBTIE_TIE30 (0x1u << 30) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 */ +#define MCAN_TXBTIE_TIE31 (0x1u << 31) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 */ +/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */ +#define MCAN_TXBCIE_CFIE0 (0x1u << 0) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 */ +#define MCAN_TXBCIE_CFIE1 (0x1u << 1) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 */ +#define MCAN_TXBCIE_CFIE2 (0x1u << 2) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 */ +#define MCAN_TXBCIE_CFIE3 (0x1u << 3) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 */ +#define MCAN_TXBCIE_CFIE4 (0x1u << 4) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 */ +#define MCAN_TXBCIE_CFIE5 (0x1u << 5) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 */ +#define MCAN_TXBCIE_CFIE6 (0x1u << 6) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 */ +#define MCAN_TXBCIE_CFIE7 (0x1u << 7) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 */ +#define MCAN_TXBCIE_CFIE8 (0x1u << 8) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 */ +#define MCAN_TXBCIE_CFIE9 (0x1u << 9) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 */ +#define MCAN_TXBCIE_CFIE10 (0x1u << 10) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 */ +#define MCAN_TXBCIE_CFIE11 (0x1u << 11) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 */ +#define MCAN_TXBCIE_CFIE12 (0x1u << 12) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 */ +#define MCAN_TXBCIE_CFIE13 (0x1u << 13) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 */ +#define MCAN_TXBCIE_CFIE14 (0x1u << 14) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 */ +#define MCAN_TXBCIE_CFIE15 (0x1u << 15) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 */ +#define MCAN_TXBCIE_CFIE16 (0x1u << 16) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 */ +#define MCAN_TXBCIE_CFIE17 (0x1u << 17) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 */ +#define MCAN_TXBCIE_CFIE18 (0x1u << 18) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 */ +#define MCAN_TXBCIE_CFIE19 (0x1u << 19) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 */ +#define MCAN_TXBCIE_CFIE20 (0x1u << 20) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 */ +#define MCAN_TXBCIE_CFIE21 (0x1u << 21) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 */ +#define MCAN_TXBCIE_CFIE22 (0x1u << 22) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 */ +#define MCAN_TXBCIE_CFIE23 (0x1u << 23) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 */ +#define MCAN_TXBCIE_CFIE24 (0x1u << 24) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 */ +#define MCAN_TXBCIE_CFIE25 (0x1u << 25) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 */ +#define MCAN_TXBCIE_CFIE26 (0x1u << 26) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 */ +#define MCAN_TXBCIE_CFIE27 (0x1u << 27) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 */ +#define MCAN_TXBCIE_CFIE28 (0x1u << 28) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 */ +#define MCAN_TXBCIE_CFIE29 (0x1u << 29) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 */ +#define MCAN_TXBCIE_CFIE30 (0x1u << 30) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 */ +#define MCAN_TXBCIE_CFIE31 (0x1u << 31) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 */ +/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */ +#define MCAN_TXEFC_EFSA_Pos 2 +#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Start Address */ +#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos))) +#define MCAN_TXEFC_EFS_Pos 16 +#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Size */ +#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos))) +#define MCAN_TXEFC_EFWM_Pos 24 +#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Watermark */ +#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos))) +/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */ +#define MCAN_TXEFS_EFFL_Pos 0 +#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Fill Level */ +#define MCAN_TXEFS_EFGI_Pos 8 +#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Get Index */ +#define MCAN_TXEFS_EFPI_Pos 16 +#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Put Index */ +#define MCAN_TXEFS_EFF (0x1u << 24) /**< \brief (MCAN_TXEFS) Event FIFO Full */ +#define MCAN_TXEFS_TEFL (0x1u << 25) /**< \brief (MCAN_TXEFS) Tx Event FIFO Element Lost */ +/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */ +#define MCAN_TXEFA_EFAI_Pos 0 +#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos) /**< \brief (MCAN_TXEFA) Event FIFO Acknowledge Index */ +#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_MCAN_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_mlb.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_mlb.h new file mode 100644 index 0000000000..8dbaeab759 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_mlb.h @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MLB_COMPONENT_ +#define _SAMV71_MLB_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Media LB */ +/* ============================================================================= */ +/** \addtogroup SAMV71_MLB Media LB */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mlb hardware registers */ +typedef struct { + __IO uint32_t MLB_MLBC0; /**< \brief (Mlb Offset: 0x000) MediaLB Control 0 Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t MLB_MS0; /**< \brief (Mlb Offset: 0x00C) MediaLB Channel Status 0 Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t MLB_MS1; /**< \brief (Mlb Offset: 0x014) MediaLB Channel Status1 Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t MLB_MSS; /**< \brief (Mlb Offset: 0x020) MediaLB System Status Register */ + __I uint32_t MLB_MSD; /**< \brief (Mlb Offset: 0x024) MediaLB System Data Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t MLB_MIEN; /**< \brief (Mlb Offset: 0x02C) MediaLB Interrupt Enable Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t MLB_MLBC1; /**< \brief (Mlb Offset: 0x03C) MediaLB Control 1 Register */ + __I uint32_t Reserved6[1]; + __I uint32_t Reserved7[15]; + __IO uint32_t MLB_HCTL; /**< \brief (Mlb Offset: 0x080) HBI Control Register */ + __I uint32_t Reserved8[1]; + __IO uint32_t MLB_HCMR[2]; /**< \brief (Mlb Offset: 0x088) HBI Channel Mask 0 Register */ + __I uint32_t MLB_HCER[2]; /**< \brief (Mlb Offset: 0x090) HBI Channel Error 0 Register */ + __I uint32_t MLB_HCBR[2]; /**< \brief (Mlb Offset: 0x098) HBI Channel Busy 0 Register */ + __I uint32_t Reserved9[8]; + __IO uint32_t MLB_MDAT[4]; /**< \brief (Mlb Offset: 0x0C0) MIF Data 0 Register */ + __IO uint32_t MLB_MDWE[4]; /**< \brief (Mlb Offset: 0x0D0) MIF Data Write Enable 0 Register */ + __IO uint32_t MLB_MCTL; /**< \brief (Mlb Offset: 0x0E0) MIF Control Register */ + __IO uint32_t MLB_MADR; /**< \brief (Mlb Offset: 0x0E4) MIF Address Register */ + __I uint32_t Reserved10[182]; + __IO uint32_t MLB_ACTL; /**< \brief (Mlb Offset: 0x3C0) AHB Control Register */ + __I uint32_t Reserved11[3]; + __IO uint32_t MLB_ACSR[2]; /**< \brief (Mlb Offset: 0x3D0) AHB Channel Status 0 Register */ + __IO uint32_t MLB_ACMR[2]; /**< \brief (Mlb Offset: 0x3D8) AHB Channel Mask 0 Register */ +} Mlb; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MLB_MLBC0 : (MLB Offset: 0x000) MediaLB Control 0 Register -------- */ +#define MLB_MLBC0_MLBEN (0x1u << 0) /**< \brief (MLB_MLBC0) MediaLB Enable */ +#define MLB_MLBC0_MLBCLK_Pos 2 +#define MLB_MLBC0_MLBCLK_Msk (0x7u << MLB_MLBC0_MLBCLK_Pos) /**< \brief (MLB_MLBC0) MLBCLK (MediaLB clock) speed select */ +#define MLB_MLBC0_MLBCLK(value) ((MLB_MLBC0_MLBCLK_Msk & ((value) << MLB_MLBC0_MLBCLK_Pos))) +#define MLB_MLBC0_MLBCLK_256_FS (0x0u << 2) /**< \brief (MLB_MLBC0) 256xFs (for MLBPEN = 0) */ +#define MLB_MLBC0_MLBCLK_512_FS (0x1u << 2) /**< \brief (MLB_MLBC0) 512xFs (for MLBPEN = 0) */ +#define MLB_MLBC0_MLBCLK_1024_FS (0x2u << 2) /**< \brief (MLB_MLBC0) 1024xFs (for MLBPEN = 0) */ +#define MLB_MLBC0_ZERO (0x1u << 5) /**< \brief (MLB_MLBC0) Must be Written to 0 */ +#define MLB_MLBC0_MLBLK (0x1u << 7) /**< \brief (MLB_MLBC0) MediaLB Lock Status (read-only) */ +#define MLB_MLBC0_ASYRETRY (0x1u << 12) /**< \brief (MLB_MLBC0) Asynchronous Tx Packet Retry */ +#define MLB_MLBC0_CTLRETRY (0x1u << 14) /**< \brief (MLB_MLBC0) Control Tx Packet Retry */ +#define MLB_MLBC0_FCNT_Pos 15 +#define MLB_MLBC0_FCNT_Msk (0x7u << MLB_MLBC0_FCNT_Pos) /**< \brief (MLB_MLBC0) The number of frames per sub-buffer for synchronous channels */ +#define MLB_MLBC0_FCNT(value) ((MLB_MLBC0_FCNT_Msk & ((value) << MLB_MLBC0_FCNT_Pos))) +#define MLB_MLBC0_FCNT_1_FRAME (0x0u << 15) /**< \brief (MLB_MLBC0) 1 frame per sub-buffer (Operation is the same as Standard mode.) */ +#define MLB_MLBC0_FCNT_2_FRAMES (0x1u << 15) /**< \brief (MLB_MLBC0) 2 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_4_FRAMES (0x2u << 15) /**< \brief (MLB_MLBC0) 4 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_8_FRAMES (0x3u << 15) /**< \brief (MLB_MLBC0) 8 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_16_FRAMES (0x4u << 15) /**< \brief (MLB_MLBC0) 16 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_32_FRAMES (0x5u << 15) /**< \brief (MLB_MLBC0) 32 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_64_FRAMES (0x6u << 15) /**< \brief (MLB_MLBC0) 64 frames per sub-buffer */ +/* -------- MLB_MS0 : (MLB Offset: 0x00C) MediaLB Channel Status 0 Register -------- */ +#define MLB_MS0_MCS_Pos 0 +#define MLB_MS0_MCS_Msk (0xffffffffu << MLB_MS0_MCS_Pos) /**< \brief (MLB_MS0) MediaLB Channel Status [31:0] (cleared by writing a 0) */ +#define MLB_MS0_MCS(value) ((MLB_MS0_MCS_Msk & ((value) << MLB_MS0_MCS_Pos))) +/* -------- MLB_MS1 : (MLB Offset: 0x014) MediaLB Channel Status1 Register -------- */ +#define MLB_MS1_MCS_Pos 0 +#define MLB_MS1_MCS_Msk (0xffffffffu << MLB_MS1_MCS_Pos) /**< \brief (MLB_MS1) MediaLB Channel Status [63:32] (cleared by writing a 0) */ +#define MLB_MS1_MCS(value) ((MLB_MS1_MCS_Msk & ((value) << MLB_MS1_MCS_Pos))) +/* -------- MLB_MSS : (MLB Offset: 0x020) MediaLB System Status Register -------- */ +#define MLB_MSS_RSTSYSCMD (0x1u << 0) /**< \brief (MLB_MSS) Reset System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_LKSYSCMD (0x1u << 1) /**< \brief (MLB_MSS) Network Lock System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_ULKSYSCMD (0x1u << 2) /**< \brief (MLB_MSS) Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_CSSYSCMD (0x1u << 3) /**< \brief (MLB_MSS) Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_SWSYSCMD (0x1u << 4) /**< \brief (MLB_MSS) Software System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_SERVREQ (0x1u << 5) /**< \brief (MLB_MSS) Service Request Enabled */ +/* -------- MLB_MSD : (MLB Offset: 0x024) MediaLB System Data Register -------- */ +#define MLB_MSD_SD0_Pos 0 +#define MLB_MSD_SD0_Msk (0xffu << MLB_MSD_SD0_Pos) /**< \brief (MLB_MSD) System Data (Byte 0) */ +#define MLB_MSD_SD1_Pos 8 +#define MLB_MSD_SD1_Msk (0xffu << MLB_MSD_SD1_Pos) /**< \brief (MLB_MSD) System Data (Byte 1) */ +#define MLB_MSD_SD2_Pos 16 +#define MLB_MSD_SD2_Msk (0xffu << MLB_MSD_SD2_Pos) /**< \brief (MLB_MSD) System Data (Byte 2) */ +#define MLB_MSD_SD3_Pos 24 +#define MLB_MSD_SD3_Msk (0xffu << MLB_MSD_SD3_Pos) /**< \brief (MLB_MSD) System Data (Byte 3) */ +/* -------- MLB_MIEN : (MLB Offset: 0x02C) MediaLB Interrupt Enable Register -------- */ +#define MLB_MIEN_ISOC_PE (0x1u << 0) /**< \brief (MLB_MIEN) Isochronous Rx Protocol Error Enable */ +#define MLB_MIEN_ISOC_BUFO (0x1u << 1) /**< \brief (MLB_MIEN) Isochronous Rx Buffer Overflow Enable */ +#define MLB_MIEN_SYNC_PE (0x1u << 16) /**< \brief (MLB_MIEN) Synchronous Protocol Error Enable */ +#define MLB_MIEN_ARX_DONE (0x1u << 17) /**< \brief (MLB_MIEN) Asynchronous Rx Done Enable */ +#define MLB_MIEN_ARX_PE (0x1u << 18) /**< \brief (MLB_MIEN) Asynchronous Rx Protocol Error Enable */ +#define MLB_MIEN_ARX_BREAK (0x1u << 19) /**< \brief (MLB_MIEN) Asynchronous Rx Break Enable */ +#define MLB_MIEN_ATX_DONE (0x1u << 20) /**< \brief (MLB_MIEN) Asynchronous Tx Packet Done Enable */ +#define MLB_MIEN_ATX_PE (0x1u << 21) /**< \brief (MLB_MIEN) Asynchronous Tx Protocol Error Enable */ +#define MLB_MIEN_ATX_BREAK (0x1u << 22) /**< \brief (MLB_MIEN) Asynchronous Tx Break Enable */ +#define MLB_MIEN_CRX_DONE (0x1u << 24) /**< \brief (MLB_MIEN) Control Rx Packet Done Enable */ +#define MLB_MIEN_CRX_PE (0x1u << 25) /**< \brief (MLB_MIEN) Control Rx Protocol Error Enable */ +#define MLB_MIEN_CRX_BREAK (0x1u << 26) /**< \brief (MLB_MIEN) Control Rx Break Enable */ +#define MLB_MIEN_CTX_DONE (0x1u << 27) /**< \brief (MLB_MIEN) Control Tx Packet Done Enable */ +#define MLB_MIEN_CTX_PE (0x1u << 28) /**< \brief (MLB_MIEN) Control Tx Protocol Error Enable */ +#define MLB_MIEN_CTX_BREAK (0x1u << 29) /**< \brief (MLB_MIEN) Control Tx Break Enable */ +/* -------- MLB_MLBC1 : (MLB Offset: 0x03C) MediaLB Control 1 Register -------- */ +#define MLB_MLBC1_LOCK (0x1u << 6) /**< \brief (MLB_MLBC1) MediaLB Lock Error Status (cleared by writing a 0) */ +#define MLB_MLBC1_CLKM (0x1u << 7) /**< \brief (MLB_MLBC1) MediaLB Clock Missing Status (cleared by writing a 0) */ +#define MLB_MLBC1_NDA_Pos 8 +#define MLB_MLBC1_NDA_Msk (0xffu << MLB_MLBC1_NDA_Pos) /**< \brief (MLB_MLBC1) Node Device Address */ +#define MLB_MLBC1_NDA(value) ((MLB_MLBC1_NDA_Msk & ((value) << MLB_MLBC1_NDA_Pos))) +/* -------- MLB_HCTL : (MLB Offset: 0x080) HBI Control Register -------- */ +#define MLB_HCTL_RST0 (0x1u << 0) /**< \brief (MLB_HCTL) Address Generation Unit 0 Software Reset */ +#define MLB_HCTL_RST1 (0x1u << 1) /**< \brief (MLB_HCTL) Address Generation Unit 1 Software Reset */ +#define MLB_HCTL_EN (0x1u << 15) /**< \brief (MLB_HCTL) HBI Enable */ +/* -------- MLB_HCMR[2] : (MLB Offset: 0x088) HBI Channel Mask 0 Register -------- */ +#define MLB_HCMR_CHM_Pos 0 +#define MLB_HCMR_CHM_Msk (0xffffffffu << MLB_HCMR_CHM_Pos) /**< \brief (MLB_HCMR[2]) Bitwise Channel Mask Bit [31:0] */ +#define MLB_HCMR_CHM(value) ((MLB_HCMR_CHM_Msk & ((value) << MLB_HCMR_CHM_Pos))) +/* -------- MLB_HCER[2] : (MLB Offset: 0x090) HBI Channel Error 0 Register -------- */ +#define MLB_HCER_CERR_Pos 0 +#define MLB_HCER_CERR_Msk (0xffffffffu << MLB_HCER_CERR_Pos) /**< \brief (MLB_HCER[2]) Bitwise Channel Error Bit [31:0] */ +/* -------- MLB_HCBR[2] : (MLB Offset: 0x098) HBI Channel Busy 0 Register -------- */ +#define MLB_HCBR_CHB_Pos 0 +#define MLB_HCBR_CHB_Msk (0xffffffffu << MLB_HCBR_CHB_Pos) /**< \brief (MLB_HCBR[2]) Bitwise Channel Busy Bit [31:0] */ +/* -------- MLB_MDAT[4] : (MLB Offset: 0x0C0) MIF Data 0 Register -------- */ +#define MLB_MDAT_DATA_Pos 0 +#define MLB_MDAT_DATA_Msk (0xffffffffu << MLB_MDAT_DATA_Pos) /**< \brief (MLB_MDAT[4]) CRT or DBR Data */ +#define MLB_MDAT_DATA(value) ((MLB_MDAT_DATA_Msk & ((value) << MLB_MDAT_DATA_Pos))) +/* -------- MLB_MDWE[4] : (MLB Offset: 0x0D0) MIF Data Write Enable 0 Register -------- */ +#define MLB_MDWE_MASK_Pos 0 +#define MLB_MDWE_MASK_Msk (0xffffffffu << MLB_MDWE_MASK_Pos) /**< \brief (MLB_MDWE[4]) Bitwise write enable for CTR data - bits[31:0] */ +#define MLB_MDWE_MASK(value) ((MLB_MDWE_MASK_Msk & ((value) << MLB_MDWE_MASK_Pos))) +/* -------- MLB_MCTL : (MLB Offset: 0x0E0) MIF Control Register -------- */ +#define MLB_MCTL_XCMP (0x1u << 0) /**< \brief (MLB_MCTL) Transfer Complete (Write 0 to Clear) */ +/* -------- MLB_MADR : (MLB Offset: 0x0E4) MIF Address Register -------- */ +#define MLB_MADR_ADDR_Pos 0 +#define MLB_MADR_ADDR_Msk (0x3fffu << MLB_MADR_ADDR_Pos) /**< \brief (MLB_MADR) CTR or DBR Address */ +#define MLB_MADR_ADDR(value) ((MLB_MADR_ADDR_Msk & ((value) << MLB_MADR_ADDR_Pos))) +#define MLB_MADR_TB (0x1u << 30) /**< \brief (MLB_MADR) Target Location Bit */ +#define MLB_MADR_TB_CTR (0x0u << 30) /**< \brief (MLB_MADR) Selects CTR */ +#define MLB_MADR_TB_DBR (0x1u << 30) /**< \brief (MLB_MADR) Selects DBR */ +#define MLB_MADR_WNR (0x1u << 31) /**< \brief (MLB_MADR) Write-Not-Read Selection */ +/* -------- MLB_ACTL : (MLB Offset: 0x3C0) AHB Control Register -------- */ +#define MLB_ACTL_SCE (0x1u << 0) /**< \brief (MLB_ACTL) Software Clear Enable */ +#define MLB_ACTL_SMX (0x1u << 1) /**< \brief (MLB_ACTL) AHB Interrupt Mux Enable */ +#define MLB_ACTL_DMA_MODE (0x1u << 2) /**< \brief (MLB_ACTL) DMA Mode */ +#define MLB_ACTL_MPB (0x1u << 4) /**< \brief (MLB_ACTL) DMA Packet Buffering Mode */ +#define MLB_ACTL_MPB_SINGLE_PACKET (0x0u << 4) /**< \brief (MLB_ACTL) Single-packet mode */ +#define MLB_ACTL_MPB_MULTIPLE_PACKET (0x1u << 4) /**< \brief (MLB_ACTL) Multiple-packet mode */ +/* -------- MLB_ACSR[2] : (MLB Offset: 0x3D0) AHB Channel Status 0 Register -------- */ +#define MLB_ACSR_CHS_Pos 0 +#define MLB_ACSR_CHS_Msk (0xffffffffu << MLB_ACSR_CHS_Pos) /**< \brief (MLB_ACSR[2]) Interrupt Status for Logical Channels [31:0] (cleared by writing a 1) */ +#define MLB_ACSR_CHS(value) ((MLB_ACSR_CHS_Msk & ((value) << MLB_ACSR_CHS_Pos))) +/* -------- MLB_ACMR[2] : (MLB Offset: 0x3D8) AHB Channel Mask 0 Register -------- */ +#define MLB_ACMR_CHM_Pos 0 +#define MLB_ACMR_CHM_Msk (0xffffffffu << MLB_ACMR_CHM_Pos) /**< \brief (MLB_ACMR[2]) Bitwise Channel Mask Bits 31 to 0 */ +#define MLB_ACMR_CHM(value) ((MLB_ACMR_CHM_Msk & ((value) << MLB_ACMR_CHM_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_MLB_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_pio.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_pio.h new file mode 100644 index 0000000000..835f663aa8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_pio.h @@ -0,0 +1,1717 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIO_COMPONENT_ +#define _SAMV71_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + __I uint32_t Reserved3[1]; + __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + __I uint32_t Reserved4[1]; + __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + __I uint32_t Reserved6[2]; + __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + __I uint32_t Reserved7[1]; + __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + __I uint32_t Reserved8[1]; + __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + __I uint32_t Reserved9[1]; + __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + __I uint32_t Reserved10[1]; + __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + __I uint32_t Reserved11[1]; + __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved12[4]; + __I uint32_t PIO_VERSION; /**< \brief (Pio Offset: 0x00FC) Version Register */ + __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + __I uint32_t Reserved13[5]; + __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0118) I/O Drive Register */ + __I uint32_t Reserved14[13]; + __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x0150) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x0164) Parallel Capture Reception Holding Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filter Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-drive Enable */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-drive Disable */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-drive Status */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) IO Line Index */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */ +/* -------- PIO_VERSION : (PIO Offset: 0x00FC) Version Register -------- */ +#define PIO_VERSION_VERSION_Pos 0 +#define PIO_VERSION_VERSION_Msk (0xfffu << PIO_VERSION_VERSION_Pos) /**< \brief (PIO_VERSION) Hardware Module Version */ +#define PIO_VERSION_MFN_Pos 16 +#define PIO_VERSION_MFN_Msk (0x7u << PIO_VERSION_MFN_Pos) /**< \brief (PIO_VERSION) Metal Fix Number */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +/* -------- PIO_DRIVER : (PIO Offset: 0x0118) I/O Drive Register -------- */ +#define PIO_DRIVER_LINE0 (0x1u << 0) /**< \brief (PIO_DRIVER) Drive of PIO Line 0 */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (0x1u << 0) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1 (0x1u << 1) /**< \brief (PIO_DRIVER) Drive of PIO Line 1 */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (0x0u << 1) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (0x1u << 1) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2 (0x1u << 2) /**< \brief (PIO_DRIVER) Drive of PIO Line 2 */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (0x1u << 2) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3 (0x1u << 3) /**< \brief (PIO_DRIVER) Drive of PIO Line 3 */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (0x0u << 3) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (0x1u << 3) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4 (0x1u << 4) /**< \brief (PIO_DRIVER) Drive of PIO Line 4 */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (0x1u << 4) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5 (0x1u << 5) /**< \brief (PIO_DRIVER) Drive of PIO Line 5 */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (0x0u << 5) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (0x1u << 5) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6 (0x1u << 6) /**< \brief (PIO_DRIVER) Drive of PIO Line 6 */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (0x1u << 6) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7 (0x1u << 7) /**< \brief (PIO_DRIVER) Drive of PIO Line 7 */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (0x0u << 7) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (0x1u << 7) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8 (0x1u << 8) /**< \brief (PIO_DRIVER) Drive of PIO Line 8 */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (0x1u << 8) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9 (0x1u << 9) /**< \brief (PIO_DRIVER) Drive of PIO Line 9 */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (0x0u << 9) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (0x1u << 9) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10 (0x1u << 10) /**< \brief (PIO_DRIVER) Drive of PIO Line 10 */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (0x1u << 10) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11 (0x1u << 11) /**< \brief (PIO_DRIVER) Drive of PIO Line 11 */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (0x0u << 11) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (0x1u << 11) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12 (0x1u << 12) /**< \brief (PIO_DRIVER) Drive of PIO Line 12 */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (0x1u << 12) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13 (0x1u << 13) /**< \brief (PIO_DRIVER) Drive of PIO Line 13 */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (0x0u << 13) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (0x1u << 13) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14 (0x1u << 14) /**< \brief (PIO_DRIVER) Drive of PIO Line 14 */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (0x1u << 14) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15 (0x1u << 15) /**< \brief (PIO_DRIVER) Drive of PIO Line 15 */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (0x0u << 15) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (0x1u << 15) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16 (0x1u << 16) /**< \brief (PIO_DRIVER) Drive of PIO Line 16 */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (0x1u << 16) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17 (0x1u << 17) /**< \brief (PIO_DRIVER) Drive of PIO Line 17 */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (0x0u << 17) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (0x1u << 17) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18 (0x1u << 18) /**< \brief (PIO_DRIVER) Drive of PIO Line 18 */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (0x1u << 18) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19 (0x1u << 19) /**< \brief (PIO_DRIVER) Drive of PIO Line 19 */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (0x0u << 19) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (0x1u << 19) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20 (0x1u << 20) /**< \brief (PIO_DRIVER) Drive of PIO Line 20 */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (0x1u << 20) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21 (0x1u << 21) /**< \brief (PIO_DRIVER) Drive of PIO Line 21 */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (0x0u << 21) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (0x1u << 21) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22 (0x1u << 22) /**< \brief (PIO_DRIVER) Drive of PIO Line 22 */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (0x1u << 22) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23 (0x1u << 23) /**< \brief (PIO_DRIVER) Drive of PIO Line 23 */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (0x0u << 23) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (0x1u << 23) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24 (0x1u << 24) /**< \brief (PIO_DRIVER) Drive of PIO Line 24 */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (0x1u << 24) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25 (0x1u << 25) /**< \brief (PIO_DRIVER) Drive of PIO Line 25 */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (0x0u << 25) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (0x1u << 25) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26 (0x1u << 26) /**< \brief (PIO_DRIVER) Drive of PIO Line 26 */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (0x1u << 26) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27 (0x1u << 27) /**< \brief (PIO_DRIVER) Drive of PIO Line 27 */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (0x0u << 27) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (0x1u << 27) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28 (0x1u << 28) /**< \brief (PIO_DRIVER) Drive of PIO Line 28 */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (0x1u << 28) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29 (0x1u << 29) /**< \brief (PIO_DRIVER) Drive of PIO Line 29 */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (0x0u << 29) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (0x1u << 29) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30 (0x1u << 30) /**< \brief (PIO_DRIVER) Drive of PIO Line 30 */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (0x1u << 30) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31 (0x1u << 31) /**< \brief (PIO_DRIVER) Drive of PIO Line 31 */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (0x0u << 31) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (0x1u << 31) /**< \brief (PIO_DRIVER) Highest drive */ +/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE_Pos 4 +#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos))) +#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error */ +/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos 0 +#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data */ + +/*@}*/ + + +#endif /* _SAMV71_PIO_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_pmc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_pmc.h new file mode 100644 index 0000000000..145abd2e94 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_pmc.h @@ -0,0 +1,729 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PMC_COMPONENT_ +#define _SAMV71_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t PMC_PCK[7]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + __I uint32_t Reserved5[1]; + __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + __I uint32_t Reserved6[26]; + __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved7[4]; + __I uint32_t PMC_VERSION; /**< \brief (Pmc Offset: 0x00FC) Version Register */ + __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 */ + __I uint32_t Reserved8[3]; + __IO uint32_t PMC_PMMR; /**< \brief (Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register */ + __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_USBCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB FS Clock */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */ +#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */ +#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */ +#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_USBCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB FS Clock */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */ +#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */ +#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */ +#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_USBCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB FS Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */ +#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */ +#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */ +#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command (Write-only) */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) 4/8/12 MHz On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) 4/8/12 MHz RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos))) +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Clock Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */ +#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ +#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front End Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos))) +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos))) +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_MDIV_Pos 8 +#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */ +#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos))) +#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK[7] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[7]) Master Clock Source Selection */ +#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos))) +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[7]) Slow Clock is selected */ +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[7]) Main Clock is selected */ +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[7]) PLLA Clock is selected */ +#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[7]) Divided UPLL Clock is selected */ +#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[7]) Master Clock is selected */ +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[7]) Programmable Clock Prescaler */ +#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) 3 to 20 MHz Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */ +#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */ +#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */ +#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) 4/8/12 MHz RC Oscillator Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) 3 to 20 MHz Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */ +#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */ +#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */ +#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) 4/8/12 MHz RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) 3 to 20 MHz Crystal Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Source Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Clock Source Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) 4/8/12 MHz RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) 3 to 20 MHz Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask */ +#define PMC_IMR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask */ +#define PMC_IMR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask */ +#define PMC_IMR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) 4/8/12 MHz RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */ +#define PMC_FSMR_FLPM_Pos 21 +#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */ +#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos))) +#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 1 */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 2 */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 3 */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 4 */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 5 */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 6 */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 7 */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 8 */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 9 */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 10 */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 11 */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 12 */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 13 */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 14 */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 15 */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */ +/* -------- PMC_VERSION : (PMC Offset: 0x00FC) Version Register -------- */ +#define PMC_VERSION_VERSION_Pos 0 +#define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos) /**< \brief (PMC_VERSION) Version of the Hardware Module */ +#define PMC_VERSION_MFN_Pos 16 +#define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos) /**< \brief (PMC_VERSION) Metal Fix Number */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos 0 +#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ +#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos))) +#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */ +#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos 0 +#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) +#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL8_Pos 8 +#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) +#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL12_Pos 16 +#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */ +#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) +#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */ +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */ +#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */ +#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */ +#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */ +#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */ +#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */ +#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */ +#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */ +#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */ +#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */ +#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */ +#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */ +#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */ +#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */ +#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */ +#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */ +#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */ +#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */ +#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */ +#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */ +#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */ +#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */ +#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */ +#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */ +#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */ +#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */ +#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */ +#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */ +#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */ +/* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */ +#define PMC_PMMR_PLLA_MMAX_Pos 0 +#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) /**< \brief (PMC_PMMR) PLLA Maximum Allowed Multiplier Value */ +#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos))) +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */ +#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */ +#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */ +#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */ +#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */ +#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */ +#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */ +#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */ +#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */ +#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */ +#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */ +#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */ +#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */ +#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */ +#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */ +#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */ +#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */ +#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */ +#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */ +#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */ +#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */ +#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */ +#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */ +#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */ +#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */ +#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */ +#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status */ +#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status */ +#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status */ +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */ +#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */ + +/*@}*/ + + +#endif /* _SAMV71_PMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_pwm.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_pwm.h new file mode 100644 index 0000000000..a3b40e8020 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_pwm.h @@ -0,0 +1,651 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PWM_COMPONENT_ +#define _SAMV71_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief PwmCmp hardware registers */ +typedef struct { + __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ +} PwmCmp; +/** \brief Pwm hardware registers */ +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 4 +typedef struct { + __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */ + __I uint32_t Reserved5[8]; + __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */ + __I uint32_t Reserved6[4]; + __I uint32_t PWM_VERSION; /**< \brief (Pwm Offset: 0xFC) Version Register */ + __I uint32_t Reserved7[12]; + PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ + __I uint32_t Reserved8[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ + __I uint32_t Reserved9[96]; + __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint32_t Reserved10[7]; + __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint32_t Reserved11[2]; + __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint32_t Reserved12[3]; + __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint32_t Reserved13[2]; + __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint32_t Reserved14[3]; + __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Controller Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Controller Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */ +#define PWM_DMAR_DMADUTY_Pos 0 +#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */ +#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */ +/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */ +#define PWM_SSPR_SPRD_Pos 0 +#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */ +#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) +#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */ +/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */ +#define PWM_SSPUP_SPRDUP_Pos 0 +#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */ +#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */ +#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */ +#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */ +#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */ +#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */ +#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */ +#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */ +#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_VERSION : (PWM Offset: 0xFC) Version Register -------- */ +#define PWM_VERSION_VERSION_Pos 0 +#define PWM_VERSION_VERSION_Msk (0xfffu << PWM_VERSION_VERSION_Pos) /**< \brief (PWM_VERSION) Version of the Hardware Module */ +#define PWM_VERSION_MFN_Pos 16 +#define PWM_VERSION_MFN_Msk (0x7u << PWM_VERSION_MFN_Pos) /**< \brief (PWM_VERSION) Metal Fix Number */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */ +#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */ +#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */ +#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */ +#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */ +#define PWM_ETRG1_MAXCNT_Pos 0 +#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */ +#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos))) +#define PWM_ETRG1_TRGMODE_Pos 24 +#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */ +#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos))) +#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */ +#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */ +#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */ +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#define PWM_LEBR1_LEBDELAY_Pos 0 +#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos))) +#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */ +#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */ +#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */ +#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */ +#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */ +#define PWM_ETRG2_MAXCNT_Pos 0 +#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */ +#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos))) +#define PWM_ETRG2_TRGMODE_Pos 24 +#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */ +#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos))) +#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */ +#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */ +#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */ +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#define PWM_LEBR2_LEBDELAY_Pos 0 +#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos))) +#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */ +#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */ +#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */ +#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */ +#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */ + +/*@}*/ + + +#endif /* _SAMV71_PWM_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_qspi.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_qspi.h new file mode 100644 index 0000000000..46e0380e05 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_qspi.h @@ -0,0 +1,223 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_QSPI_COMPONENT_ +#define _SAMV71_QSPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_QSPI Quad Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Qspi hardware registers */ +typedef struct { + __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */ + __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */ + __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */ + __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */ + __I uint32_t Reserved3[39]; + __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t QSPI_VERSION; /**< \brief (Qspi Offset: 0x00FC) Version Register */ +} Qspi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */ +#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */ +#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */ +#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */ +#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */ +/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */ +#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */ +#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */ +#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */ +#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_CSMODE_Pos 4 +#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */ +#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos))) +#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_NBBITS_Pos 8 +#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */ +#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos))) +#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_DLYBCT_Pos 16 +#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */ +#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos))) +#define QSPI_MR_DLYCS_Pos 24 +#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */ +#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos))) +/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */ +#define QSPI_RDR_RD_Pos 0 +#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */ +/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */ +#define QSPI_TDR_TD_Pos 0 +#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */ +#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos))) +/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */ +#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */ +#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */ +#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */ +#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */ +#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */ +#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */ +#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */ +#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */ +/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */ +#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */ +#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */ +#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */ +#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */ +#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */ +#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */ +#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */ +/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */ +#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */ +#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */ +#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */ +#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */ +#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */ +#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */ +#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */ +/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */ +#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */ +#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */ +#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */ +#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */ +#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */ +#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */ +/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */ +#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */ +#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */ +#define QSPI_SCR_SCBR_Pos 8 +#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */ +#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos))) +#define QSPI_SCR_DLYBS_Pos 16 +#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */ +#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos))) +/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */ +#define QSPI_IAR_ADDR_Pos 0 +#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */ +#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos))) +/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */ +#define QSPI_ICR_INST_Pos 0 +#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */ +#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos))) +#define QSPI_ICR_OPT_Pos 16 +#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */ +#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos))) +/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */ +#define QSPI_IFR_WIDTH_Pos 0 +#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */ +#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos))) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */ +#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */ +#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */ +#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */ +#define QSPI_IFR_OPTL_Pos 8 +#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */ +#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos))) +#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */ +#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_TFRTYP_Pos 12 +#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */ +#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos))) +#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */ +#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_NBDUM_Pos 16 +#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */ +#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos))) +/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */ +#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */ +#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */ +/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */ +#define QSPI_SKR_USRK_Pos 0 +#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */ +#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos))) +/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */ +#define QSPI_WPMR_WPKEY_Pos 8 +#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */ +#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos))) +#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */ +#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */ +#define QSPI_WPSR_WPVSRC_Pos 8 +#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */ +/* -------- QSPI_VERSION : (QSPI Offset: 0x00FC) Version Register -------- */ +#define QSPI_VERSION_VERSION_Pos 0 +#define QSPI_VERSION_VERSION_Msk (0xfffu << QSPI_VERSION_VERSION_Pos) /**< \brief (QSPI_VERSION) Hardware Module Version */ +#define QSPI_VERSION_MFN_Pos 16 +#define QSPI_VERSION_MFN_Msk (0x7u << QSPI_VERSION_MFN_Pos) /**< \brief (QSPI_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_QSPI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_rstc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rstc.h new file mode 100644 index 0000000000..0ff4473c32 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rstc.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RSTC_COMPONENT_ +#define _SAMV71_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) +#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMV71_RSTC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_rswdt.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rswdt.h new file mode 100644 index 0000000000..4c9d146f36 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rswdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RSWDT_COMPONENT_ +#define _SAMV71_RSWDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RSWDT Reinforced Safety Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rswdt hardware registers */ +typedef struct { + __O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */ + __IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */ + __I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */ +} Rswdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */ +#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */ +#define RSWDT_CR_KEY_Pos 24 +#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */ +#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) +#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */ +#define RSWDT_MR_WDV_Pos 0 +#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */ +#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) +#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */ +#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */ +#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */ +#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */ +#define RSWDT_MR_ALLONES_Pos 16 +#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */ +#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))) +#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */ +#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */ +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */ +#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */ + +/*@}*/ + + +#endif /* _SAMV71_RSWDT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_rtc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rtc.h new file mode 100644 index 0000000000..533e0ed724 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rtc.h @@ -0,0 +1,241 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RTC_COMPONENT_ +#define _SAMV71_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ + __I uint32_t Reserved1[45]; + __IO uint32_t RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t Reserved2[5]; + __I uint32_t RTC_VERSION; /**< \brief (Rtc Offset: 0xFC) Version Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos))) +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos))) +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ +#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ +#define RTC_MR_CORRECTION_Pos 8 +#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ +#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) +#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ +#define RTC_MR_OUT0_Pos 16 +#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */ +#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos))) +#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_Pos 20 +#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */ +#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos))) +#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_THIGH_Pos 24 +#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */ +#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos))) +#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */ +#define RTC_MR_TPERIOD_Pos 28 +#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */ +#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos))) +#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ +#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ +/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */ +#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protection Enable */ +#define RTC_WPMR_WPKEY_Pos 8 +#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protection Key */ +#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos))) +#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- RTC_VERSION : (RTC Offset: 0xFC) Version Register -------- */ +#define RTC_VERSION_VERSION_Pos 0 +#define RTC_VERSION_VERSION_Msk (0xfffu << RTC_VERSION_VERSION_Pos) /**< \brief (RTC_VERSION) Version of the Hardware Module */ +#define RTC_VERSION_MFN_Pos 16 +#define RTC_VERSION_MFN_Msk (0x7u << RTC_VERSION_MFN_Pos) /**< \brief (RTC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_RTC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_rtt.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rtt.h new file mode 100644 index 0000000000..aa49aa3fbd --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rtt.h @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RTT_COMPONENT_ +#define _SAMV71_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ +#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status (cleared on read) */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status (cleared on read) */ + +/*@}*/ + + +#endif /* _SAMV71_RTT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_sdramc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_sdramc.h new file mode 100644 index 0000000000..b524a1d438 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_sdramc.h @@ -0,0 +1,180 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SDRAMC_COMPONENT_ +#define _SAMV71_SDRAMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR SDRAM Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SDRAMC SDRAM Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sdramc hardware registers */ +typedef struct { + __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */ + __I uint32_t Reserved1[1]; + __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< \brief (Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< \brief (Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register */ + __I uint32_t Reserved2[49]; + __I uint32_t SDRAMC_VERSION; /**< \brief (Sdramc Offset: 0xFC) SDRAMC Version Register */ +} Sdramc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos 0 +#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */ +#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos))) +#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */ +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos 0 +#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */ +#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos))) +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos 0 +#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */ +#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos))) +#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NR_Pos 2 +#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */ +#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos))) +#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */ +#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_CAS_Pos 5 +#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */ +#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos))) +#define SDRAMC_CR_CAS_LATENCY1 (0x0u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2 (0x1u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3 (0x2u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */ +#define SDRAMC_CR_TWR_Pos 8 +#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */ +#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos))) +#define SDRAMC_CR_TRC_TRFC_Pos 12 +#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */ +#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos))) +#define SDRAMC_CR_TRP_Pos 16 +#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */ +#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos))) +#define SDRAMC_CR_TRCD_Pos 20 +#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */ +#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos))) +#define SDRAMC_CR_TRAS_Pos 24 +#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */ +#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos))) +#define SDRAMC_CR_TXSR_Pos 28 +#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */ +#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos))) +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos 0 +#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */ +#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos))) +#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_PASR_Pos 4 +#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos))) +#define SDRAMC_LPR_TCSR_Pos 8 +#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos))) +#define SDRAMC_LPR_DS_Pos 10 +#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */ +#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos))) +#define SDRAMC_LPR_TIMEOUT_Pos 12 +#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled */ +#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos))) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */ +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */ +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */ +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status (cleared on read) */ +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos 0 +#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */ +#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos))) +#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */ +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CFR1_TMRD_Pos 0 +#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos) /**< \brief (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command */ +#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos))) +#define SDRAMC_CFR1_UNAL (0x1u << 8) /**< \brief (SDRAMC_CFR1) Support Unaligned Access */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is supported. */ +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */ +#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */ +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */ +#define SDRAMC_OCMS_KEY1_KEY1_Pos 0 +#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< \brief (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */ +#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos))) +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */ +#define SDRAMC_OCMS_KEY2_KEY2_Pos 0 +#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< \brief (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */ +#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos))) +/* -------- SDRAMC_VERSION : (SDRAMC Offset: 0xFC) SDRAMC Version Register -------- */ +#define SDRAMC_VERSION_VERSION_Pos 0 +#define SDRAMC_VERSION_VERSION_Msk (0xfffu << SDRAMC_VERSION_VERSION_Pos) /**< \brief (SDRAMC_VERSION) Version of the Hardware Module */ +#define SDRAMC_VERSION_MFN_Pos 16 +#define SDRAMC_VERSION_MFN_Msk (0x7u << SDRAMC_VERSION_MFN_Pos) /**< \brief (SDRAMC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_SDRAMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_smc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_smc.h new file mode 100644 index 0000000000..b345c982bc --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_smc.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SMC_COMPONENT_ +#define _SAMV71_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC MODE Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ + __I uint32_t Reserved1[16]; + __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + __I uint32_t Reserved2[22]; + __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protection Status Register */ + __I uint32_t Reserved3[4]; + __I uint32_t SMC_VERSION; /**< \brief (Smc Offset: 0xFC) SMC Version Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) Read Mode */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) Write Mode */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos))) +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ +#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */ +#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */ +#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ +#define SMC_MODE_PS_Pos 28 +#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ +#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos))) +#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY_Pos 8 +#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protection Key */ +#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) +#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */ +#define SMC_WPSR_WPVSRC_Pos 8 +#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */ +/* -------- SMC_VERSION : (SMC Offset: 0xFC) SMC Version Register -------- */ +#define SMC_VERSION_VERSION_Pos 0 +#define SMC_VERSION_VERSION_Msk (0xfffu << SMC_VERSION_VERSION_Pos) /**< \brief (SMC_VERSION) Hardware Module Version */ +#define SMC_VERSION_MFN_Pos 16 +#define SMC_VERSION_MFN_Msk (0x7u << SMC_VERSION_MFN_Pos) /**< \brief (SMC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_SMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_spi.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_spi.h new file mode 100644 index 0000000000..ed85ef1a60 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_spi.h @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SPI_COMPONENT_ +#define _SAMV71_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + __I uint32_t Reserved2[41]; + __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[4]; + __I uint32_t SPI_VERSION; /**< \brief (Spi Offset: 0xFC) Version Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos))) +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ +/* -------- SPI_VERSION : (SPI Offset: 0xFC) Version Register -------- */ +#define SPI_VERSION_VERSION_Pos 0 +#define SPI_VERSION_VERSION_Msk (0xfffu << SPI_VERSION_VERSION_Pos) /**< \brief (SPI_VERSION) Version of the Hardware Module */ +#define SPI_VERSION_MFN_Pos 16 +#define SPI_VERSION_MFN_Msk (0x7u << SPI_VERSION_MFN_Pos) /**< \brief (SPI_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_SPI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_ssc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_ssc.h new file mode 100644 index 0000000000..5705d61a8c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_ssc.h @@ -0,0 +1,287 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SSC_COMPONENT_ +#define _SAMV71_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + __I uint32_t Reserved2[2]; + __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved3[37]; + __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t SSC_VERSION; /**< \brief (Ssc Offset: 0xFC) Version Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos))) +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos))) +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos))) +#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos))) +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos))) +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos))) +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos))) +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos))) +#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos))) +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos))) +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ +/* -------- SSC_VERSION : (SSC Offset: 0xFC) Version Register -------- */ +#define SSC_VERSION_VERSION_Pos 0 +#define SSC_VERSION_VERSION_Msk (0xffffu << SSC_VERSION_VERSION_Pos) /**< \brief (SSC_VERSION) Version of the Hardware Module */ +#define SSC_VERSION_MFN_Pos 16 +#define SSC_VERSION_MFN_Msk (0x7u << SSC_VERSION_MFN_Pos) /**< \brief (SSC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_SSC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_supc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_supc.h new file mode 100644 index 0000000000..1998c04dde --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_supc.h @@ -0,0 +1,302 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SUPC_COMPONENT_ +#define _SAMV71_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ + __I uint32_t Reserved1[57]; + __I uint32_t SYSC_VERSION; /**< \brief (Supc Offset: 0xFC) Version Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos))) +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_BKUPRETON (0x1u << 17) /**< \brief (SUPC_MR) SRAM On In Backup Mode */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP0 */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP1 */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low-power Debouncer Clear */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos))) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_LPDBC_Pos 16 +#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low-power Debouncer Period */ +#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos))) +#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 0 */ +#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 1 */ +#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 2 */ +#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 3 */ +#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 4 */ +#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 5 */ +#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 6 */ +#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 7 */ +#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 8 */ +#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 9 */ +#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 10 */ +#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 11 */ +#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 12 */ +#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 13 */ +#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 0 */ +#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 1 */ +#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 2 */ +#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 3 */ +#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 4 */ +#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 5 */ +#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 6 */ +#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 7 */ +#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 8 */ +#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 9 */ +#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 10 */ +#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 11 */ +#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 12 */ +#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 13 */ +#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status (cleared on read) */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status (cleared on read) */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status (cleared on read) */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status (cleared on read) */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */ +#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */ +#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +/* -------- SYSC_VERSION : (SUPC Offset: 0xFC) Version Register -------- */ +#define SYSC_VERSION_VERSION_Pos 0 +#define SYSC_VERSION_VERSION_Msk (0xfffu << SYSC_VERSION_VERSION_Pos) /**< \brief (SYSC_VERSION) Version of the Hardware Module */ +#define SYSC_VERSION_MFN_Pos 16 +#define SYSC_VERSION_MFN_Msk (0x7u << SYSC_VERSION_MFN_Pos) /**< \brief (SYSC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_SUPC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_tc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_tc.h new file mode 100644 index 0000000000..7457f031ce --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_tc.h @@ -0,0 +1,353 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TC_COMPONENT_ +#define _SAMV71_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAMV71_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ + __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ + __I uint32_t Reserved1[3]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t Reserved2[5]; + __I uint32_t TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_SBSMPLR_Pos 20 +#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ +#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))) +#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ +#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ +#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ +#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ +#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ +/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ +#define TC_RAB_RAB_Pos 0 +#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ +#define TC_EMR_TRIGSRCA_Pos 0 +#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */ +#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCB_Pos 4 +#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */ +#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). */ +#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) +#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ +#define TC_VER_VERSION_Pos 0 +#define TC_VER_VERSION_Msk (0xfffu << TC_VER_VERSION_Pos) /**< \brief (TC_VER) Version of the Hardware Module */ +#define TC_VER_MFN_Pos 16 +#define TC_VER_MFN_Msk (0x7u << TC_VER_MFN_Pos) /**< \brief (TC_VER) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_TC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_trng.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_trng.h new file mode 100644 index 0000000000..1892c83a23 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_trng.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TRNG_COMPONENT_ +#define _SAMV71_TRNG_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR True Random Number Generator */ +/* ============================================================================= */ +/** \addtogroup SAMV71_TRNG True Random Number Generator */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Trng hardware registers */ +typedef struct { + __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */ + __I uint32_t Reserved1[3]; + __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */ + __I uint32_t Reserved2[12]; + __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */ + __I uint32_t Reserved3[42]; + __I uint32_t TRNG_VERSION; /**< \brief (Trng Offset: 0xFC) Version Register */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */ +#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to Provide Random Values */ +#define TRNG_CR_KEY_Pos 8 +#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */ +#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))) +#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */ +/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ +/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ +/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */ +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos 0 +#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */ +/* -------- TRNG_VERSION : (TRNG Offset: 0xFC) Version Register -------- */ +#define TRNG_VERSION_VERSION_Pos 0 +#define TRNG_VERSION_VERSION_Msk (0xfffu << TRNG_VERSION_VERSION_Pos) /**< \brief (TRNG_VERSION) Version of the Hardware Module */ +#define TRNG_VERSION_MFN_Pos 16 +#define TRNG_VERSION_MFN_Msk (0x7u << TRNG_VERSION_MFN_Pos) /**< \brief (TRNG_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_TRNG_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_twihs.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_twihs.h new file mode 100644 index 0000000000..f8731a4ad3 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_twihs.h @@ -0,0 +1,264 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TWIHS_COMPONENT_ +#define _SAMV71_TWIHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */ +/* ============================================================================= */ +/** \addtogroup SAMV71_TWIHS Two-wire Interface High Speed */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twihs hardware registers */ +typedef struct { + __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */ + __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */ + __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */ + __I uint32_t Reserved4[32]; + __I uint32_t TWIHS_DR; /**< \brief (Twihs Offset: 0xD0) Debug Register */ + __I uint32_t Reserved5[4]; + __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved6[4]; + __I uint32_t TWIHS_VER; /**< \brief (Twihs Offset: 0xFC) Version Register */ +} Twihs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */ +#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */ +#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */ +#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */ +#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */ +#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */ +#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */ +#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */ +#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */ +#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */ +#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */ +#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */ +#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */ +#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */ +#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */ +#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */ +#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */ +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */ +#define TWIHS_MMR_IADRSZ_Pos 8 +#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */ +#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) +#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */ +#define TWIHS_MMR_DADR_Pos 16 +#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */ +#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */ +#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */ +#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */ +#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */ +#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */ +#define TWIHS_SMR_MASK_Pos 8 +#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) +#define TWIHS_SMR_SADR_Pos 16 +#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */ +#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) +#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */ +#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */ +#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */ +#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */ +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */ +#define TWIHS_IADR_IADR_Pos 0 +#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */ +#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWIHS_CWGR_CLDIV_Pos 0 +#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */ +#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) +#define TWIHS_CWGR_CHDIV_Pos 8 +#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */ +#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) +#define TWIHS_CWGR_CKDIV_Pos 16 +#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */ +#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) +#define TWIHS_CWGR_HOLD_Pos 24 +#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */ +#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */ +#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ +#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */ +#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */ +#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */ +#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */ +#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */ +#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */ +#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */ +#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */ +#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */ +#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */ +#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */ +#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */ +#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */ +#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */ +#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL Line Value */ +#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA Line Value */ +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */ +#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */ +#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */ +#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */ +#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */ +#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */ +#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */ +#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */ +#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */ +#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */ +#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */ +#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */ +#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */ +#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */ +#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */ +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */ +#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */ +#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */ +#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */ +#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */ +#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */ +#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */ +#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */ +#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */ +#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */ +#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */ +#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */ +#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */ +#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */ +#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */ +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */ +#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */ +#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */ +#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */ +#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */ +#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */ +#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */ +#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */ +#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */ +#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */ +#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */ +#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */ +#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */ +#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */ +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */ +#define TWIHS_RHR_RXDATA_Pos 0 +#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */ +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */ +#define TWIHS_THR_TXDATA_Pos 0 +#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */ +#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */ +#define TWIHS_SMBTR_PRESC_Pos 0 +#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */ +#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) +#define TWIHS_SMBTR_TLOWS_Pos 8 +#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) +#define TWIHS_SMBTR_TLOWM_Pos 16 +#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) +#define TWIHS_SMBTR_THMAX_Pos 24 +#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */ +#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */ +#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */ +#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */ +#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */ +#define TWIHS_FILTR_THRES_Pos 8 +#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */ +#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */ +#define TWIHS_SWMR_SADR1_Pos 0 +#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */ +#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) +#define TWIHS_SWMR_SADR2_Pos 8 +#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */ +#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) +#define TWIHS_SWMR_SADR3_Pos 16 +#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */ +#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) +#define TWIHS_SWMR_DATAM_Pos 24 +#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */ +#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) +/* -------- TWIHS_DR : (TWIHS Offset: 0xD0) Debug Register -------- */ +#define TWIHS_DR_SWEN (0x1u << 0) /**< \brief (TWIHS_DR) SleepWalking Enable */ +#define TWIHS_DR_CLKRQ (0x1u << 1) /**< \brief (TWIHS_DR) Clock Request */ +#define TWIHS_DR_SWMATCH (0x1u << 2) /**< \brief (TWIHS_DR) SleepWalking Match */ +#define TWIHS_DR_TRP (0x1u << 3) /**< \brief (TWIHS_DR) Transfer Pending */ +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */ +#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */ +#define TWIHS_WPMR_WPKEY_Pos 8 +#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */ +#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) +#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */ +#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */ +#define TWIHS_WPSR_WPVSRC_Pos 8 +#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */ +/* -------- TWIHS_VER : (TWIHS Offset: 0xFC) Version Register -------- */ +#define TWIHS_VER_VERSION_Pos 0 +#define TWIHS_VER_VERSION_Msk (0xfffu << TWIHS_VER_VERSION_Pos) /**< \brief (TWIHS_VER) Version of the Hardware Module */ +#define TWIHS_VER_MFN_Pos 16 +#define TWIHS_VER_MFN_Msk (0x7u << TWIHS_VER_MFN_Pos) /**< \brief (TWIHS_VER) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_TWIHS_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_uart.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_uart.h new file mode 100644 index 0000000000..9459816dfb --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_uart.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART_COMPONENT_ +#define _SAMV71_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMV71_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */ + __I uint32_t Reserved1[47]; + __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t Reserved2[5]; + __I uint32_t UART_VERSION; /**< \brief (Uart Offset: 0x00FC) Version Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ +#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */ +#define UART_CR_DBGE (0x1u << 15) /**< \brief (UART_CR) Debug Enable */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */ +#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */ +#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */ +#define UART_SR_SWES (0x1u << 21) /**< \brief (UART_SR) SleepWalking Enable Status */ +#define UART_SR_CLKREQ (0x1u << 22) /**< \brief (UART_SR) Clock Request */ +#define UART_SR_WKUPREQ (0x1u << 23) /**< \brief (UART_SR) Wake-Up Request */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */ +#define UART_CMPR_VAL1_Pos 0 +#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */ +#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))) +#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */ +#define UART_CMPR_VAL2_Pos 16 +#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */ +#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))) +/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */ +#define UART_WPMR_WPKEY_Pos 8 +#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */ +#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))) +#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +/* -------- UART_VERSION : (UART Offset: 0x00FC) Version Register -------- */ +#define UART_VERSION_VERSION_Pos 0 +#define UART_VERSION_VERSION_Msk (0xfffu << UART_VERSION_VERSION_Pos) /**< \brief (UART_VERSION) Hardware Module Version */ +#define UART_VERSION_MFN_Pos 16 +#define UART_VERSION_MFN_Msk (0x7u << UART_VERSION_MFN_Pos) /**< \brief (UART_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_UART_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_usart.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_usart.h new file mode 100644 index 0000000000..155c9ee2e0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_usart.h @@ -0,0 +1,485 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USART_COMPONENT_ +#define _SAMV71_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMV71_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */ + __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + __I uint32_t Reserved1[5]; + __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */ + __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */ + __I uint32_t Reserved3[22]; + __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t US_VERSION; /**< \brief (Usart Offset: 0x00FC) Version Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */ +#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ +#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ +#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos))) +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ +#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos))) +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */ +#define US_MR_USCLKS_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial clock (SCK) is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */ +#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos))) +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos))) +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos))) +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos))) +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */ +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ +#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ +#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ +#define US_IER_NSSE (0x1u << 19) /**< \brief (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable */ +#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ +#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ +#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ +#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ +#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ +#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ +#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ +#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ +#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */ +#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */ +#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */ +#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */ +#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */ +#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */ +#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */ +#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */ +#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */ +#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ +#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ +#define US_IDR_NSSE (0x1u << 19) /**< \brief (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable */ +#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ +#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ +#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ +#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ +#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ +#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ +#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ +#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ +#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */ +#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */ +#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */ +#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */ +#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */ +#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */ +#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */ +#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */ +#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */ +#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ +#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ +#define US_IMR_NSSE (0x1u << 19) /**< \brief (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask */ +#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ +#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ +#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ +#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ +#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ +#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ +#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ +#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ +#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */ +#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */ +#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */ +#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */ +#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */ +#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */ +#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */ +#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */ +#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */ +#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) */ +#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag (cleared on read) */ +#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag (cleared on read) */ +#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (cleared on read) */ +#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_NSSE (0x1u << 19) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_NSS (0x1u << 23) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ +#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) */ +/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +#define US_TTGR_PCYCLE_Pos 0 +#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */ +#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos))) +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) +#define US_FIDI_BETA2_Pos 0 +#define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos) /**< \brief (US_FIDI) LON BETA2 Length */ +#define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos))) +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos))) +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos))) +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ +#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) */ +/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos 0 +#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ +#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos))) +#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ +#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ +#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ +#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ +#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ +#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ +#define US_LINMR_DLC_Pos 8 +#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ +#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) +#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */ +#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */ +/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos 0 +#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ +#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) +/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */ +#define US_LINBRR_LINCD_Pos 0 +#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */ +#define US_LINBRR_LINFP_Pos 16 +#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */ +/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */ +#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */ +#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */ +#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */ +#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */ +#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */ +#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */ +#define US_LONMR_EOFS_Pos 16 +#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */ +#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos))) +/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */ +#define US_LONPR_LONPL_Pos 0 +#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */ +#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos))) +/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */ +#define US_LONDL_LONDL_Pos 0 +#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */ +#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos))) +/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */ +#define US_LONL2HDR_BLI_Pos 0 +#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */ +#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos))) +#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */ +#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */ +/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */ +#define US_LONBL_LONBL_Pos 0 +#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */ +/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */ +#define US_LONB1TX_BETA1TX_Pos 0 +#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */ +#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos))) +/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */ +#define US_LONB1RX_BETA1RX_Pos 0 +#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */ +#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos))) +/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */ +#define US_LONPRIO_PSNB_Pos 0 +#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */ +#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos))) +#define US_LONPRIO_NPS_Pos 8 +#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */ +#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos))) +/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */ +#define US_IDTTX_IDTTX_Pos 0 +#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */ +#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos))) +/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */ +#define US_IDTRX_IDTRX_Pos 0 +#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */ +#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos))) +/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */ +#define US_ICDIFF_ICDIFF_Pos 0 +#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */ +#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos))) +/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */ +/* -------- US_VERSION : (USART Offset: 0x00FC) Version Register -------- */ +#define US_VERSION_VERSION_Pos 0 +#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION) Hardware Module Version */ +#define US_VERSION_MFN_Pos 16 +#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_USART_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_usbhs.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_usbhs.h new file mode 100644 index 0000000000..95e34fd3b5 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_usbhs.h @@ -0,0 +1,961 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USBHS_COMPONENT_ +#define _SAMV71_USBHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB High-Speed Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_USBHS USB High-Speed Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UsbhsDevdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UsbhsDevdma; +/** \brief UsbhsHstdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UsbhsHstdma; +/** \brief Usbhs hardware registers */ +#define USBHSDEVDMA_NUMBER 7 +#define USBHSHSTDMA_NUMBER 7 +typedef struct { + __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + __I uint32_t Reserved2[2]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + __I uint32_t Reserved3[2]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + __I uint32_t Reserved4[2]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + __I uint32_t Reserved5[2]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + __I uint32_t Reserved6[2]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + __I uint32_t Reserved7[2]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + __I uint32_t Reserved8[50]; + UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */ + __I uint32_t Reserved9[32]; + __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */ + __I uint32_t Reserved10[52]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + __I uint32_t Reserved11[2]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */ + __I uint32_t Reserved12[2]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + __I uint32_t Reserved13[2]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */ + __I uint32_t Reserved14[2]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + __I uint32_t Reserved15[2]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + __I uint32_t Reserved16[2]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + __I uint32_t Reserved17[2]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + __I uint32_t Reserved18[2]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */ + __I uint32_t Reserved19[26]; + UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */ + __I uint32_t Reserved20[32]; + __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */ + __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */ + __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */ + __IO uint32_t USBHS_TSTA1; /**< \brief (Usbhs Offset: 0x0810) General Test A1 Register */ + __IO uint32_t USBHS_TSTA2; /**< \brief (Usbhs Offset: 0x0814) General Test A2 Register */ + __I uint32_t USBHS_VERSION; /**< \brief (Usbhs Offset: 0x0818) General Version Register */ + __I uint32_t Reserved21[4]; + __I uint32_t USBHS_FSM; /**< \brief (Usbhs Offset: 0x082C) General Finite State Machine Register */ +} Usbhs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */ +#define USBHS_DEVCTRL_UADD_Pos 0 +#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */ +#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos))) +#define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */ +#define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */ +#define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */ +#define USBHS_DEVCTRL_SPDCONF_Pos 10 +#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */ +#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos))) +#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (USBHS_DEVCTRL) Forced high speed. */ +#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ +#define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */ +#define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */ +#define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */ +#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */ +#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */ +/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */ +#define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */ +#define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */ +#define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */ +#define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */ +#define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */ +#define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */ +#define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */ +#define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */ +#define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */ +#define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */ +#define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */ +#define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */ +#define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */ +#define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */ +#define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */ +#define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */ +#define USBHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVISR) Endpoint 10 Interrupt */ +#define USBHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVISR) Endpoint 11 Interrupt */ +#define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */ +#define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */ +#define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */ +#define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */ +#define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */ +#define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */ +#define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */ +#define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */ +#define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */ +#define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */ +#define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */ +#define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */ +#define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */ +#define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */ +#define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */ +#define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */ +#define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */ +#define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */ +#define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */ +#define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIMR) Endpoint 10 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIMR) Endpoint 11 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */ +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */ +#define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */ +#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */ +#define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */ +#define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIDR) Endpoint 10 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIDR) Endpoint 11 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */ +#define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */ +#define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */ +#define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */ +#define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */ +#define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define USBHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIER) Endpoint 10 Interrupt Enable */ +#define USBHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIER) Endpoint 11 Interrupt Enable */ +#define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */ +#define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */ +#define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */ +#define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */ +#define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */ +#define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */ +#define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */ +#define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */ +#define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */ +#define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */ +#define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */ +#define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */ +#define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */ +#define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */ +#define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */ +#define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */ +#define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */ +#define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */ +#define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */ +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */ +#define USBHS_DEVFNUM_MFNUM_Pos 0 +#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */ +#define USBHS_DEVFNUM_FNUM_Pos 3 +#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */ +#define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */ +/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */ +#define USBHS_DEVEPTCFG_EPBK_Pos 2 +#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */ +#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos))) +#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos 4 +#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */ +#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos))) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */ +#define USBHS_DEVEPTCFG_EPTYPE_Pos 11 +#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */ +#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos))) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos 13 +#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */ +#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos))) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTISR_DTSEQ_Pos 8 +#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos 12 +#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */ +#define USBHS_DEVEPTISR_CURRBK_Pos 14 +#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */ +#define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */ +#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */ +#define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */ +#define USBHS_DEVEPTISR_BYCT_Pos 20 +#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */ +#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */ +#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */ +#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */ +#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */ +#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */ +#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */ +#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */ +#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */ +#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */ +#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */ +#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */ +#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */ +#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */ +#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */ +#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */ +#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */ +#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */ +#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */ +#define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */ +#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */ +#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */ +#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */ +#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */ +#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */ +#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */ +#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */ +#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */ +#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */ +#define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */ +#define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */ +#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */ +/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */ +#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */ +#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */ +#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */ +#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */ +#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */ +#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */ +#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */ +#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */ +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */ +#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */ +#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */ +#define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */ +#define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */ +#define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */ +#define USBHS_HSTCTRL_SPDCONF_Pos 12 +#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */ +#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos))) +#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (USBHS_HSTCTRL) Forced high speed. */ +#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ +/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */ +#define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */ +#define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */ +#define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */ +#define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */ +#define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */ +#define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */ +#define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */ +#define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */ +#define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */ +#define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */ +#define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */ +#define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */ +#define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */ +#define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */ +#define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */ +#define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */ +#define USBHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTISR) Pipe 10 Interrupt */ +#define USBHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTISR) Pipe 11 Interrupt */ +#define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */ +#define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */ +#define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */ +#define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */ +#define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */ +#define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */ +#define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */ +#define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */ +#define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */ +#define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */ +#define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */ +#define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIMR) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIMR) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */ +#define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIDR) Pipe 10 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIDR) Pipe 11 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */ +#define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIER) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIER) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */ +#define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */ +#define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */ +#define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */ +#define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */ +#define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */ +#define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */ +#define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */ +#define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */ +#define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */ +#define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */ +#define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */ +#define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */ +#define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */ +#define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */ +#define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */ +#define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */ +#define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */ +#define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */ +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */ +#define USBHS_HSTFNUM_MFNUM_Pos 0 +#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */ +#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos))) +#define USBHS_HSTFNUM_FNUM_Pos 3 +#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */ +#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos))) +#define USBHS_HSTFNUM_FLENHIGH_Pos 16 +#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */ +#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */ +#define USBHS_HSTADDR1_HSTADDRP0_Pos 0 +#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos))) +#define USBHS_HSTADDR1_HSTADDRP1_Pos 8 +#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos))) +#define USBHS_HSTADDR1_HSTADDRP2_Pos 16 +#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos))) +#define USBHS_HSTADDR1_HSTADDRP3_Pos 24 +#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */ +#define USBHS_HSTADDR2_HSTADDRP4_Pos 0 +#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos))) +#define USBHS_HSTADDR2_HSTADDRP5_Pos 8 +#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos))) +#define USBHS_HSTADDR2_HSTADDRP6_Pos 16 +#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos))) +#define USBHS_HSTADDR2_HSTADDRP7_Pos 24 +#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */ +#define USBHS_HSTADDR3_HSTADDRP8_Pos 0 +#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos))) +#define USBHS_HSTADDR3_HSTADDRP9_Pos 8 +#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */ +#define USBHS_HSTPIPCFG_PBK_Pos 2 +#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */ +#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos))) +#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PSIZE_Pos 4 +#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */ +#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos))) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos 8 +#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */ +#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos))) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */ +#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */ +#define USBHS_HSTPIPCFG_PTYPE_Pos 12 +#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */ +#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos))) +#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos 16 +#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */ +#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos))) +#define USBHS_HSTPIPCFG_INTFRQ_Pos 24 +#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */ +#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos))) +#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */ +#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */ +#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */ +#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */ +#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */ +#define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */ +#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */ +#define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */ +#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */ +#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */ +#define USBHS_HSTPIPISR_DTSEQ_Pos 8 +#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos 12 +#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */ +#define USBHS_HSTPIPISR_CURRBK_Pos 14 +#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */ +#define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */ +#define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */ +#define USBHS_HSTPIPISR_PBYCT_Pos 20 +#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */ +#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */ +#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */ +/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */ +#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */ +#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */ +#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */ +#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */ +#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */ +#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */ +#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */ +#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */ +#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */ +#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */ +#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */ +#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */ +#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */ +#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */ +#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */ +#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */ +#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */ +#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */ +#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */ +#define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */ +#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */ +#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */ +#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */ +#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */ +#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */ +#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */ +#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */ +/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define USBHS_HSTPIPINRQ_INRQ_Pos 0 +#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */ +#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos))) +#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */ +/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */ +#define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */ +#define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */ +#define USBHS_HSTPIPERR_COUNTER_Pos 5 +#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */ +#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos))) +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */ +#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */ +#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */ +#define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */ +#define USBHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (USBHS_CTRL) VBUS Hardware Control */ +#define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */ +#define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */ +#define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */ +#define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */ +/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */ +#define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */ +#define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBUS Request (Host mode only) */ +#define USBHS_SR_SPEED_Pos 12 +#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */ +#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */ +/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */ +#define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */ +#define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBUS Request Clear */ +/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */ +#define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */ +#define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBUS Request Set */ +/* -------- USBHS_TSTA1 : (USBHS Offset: 0x0810) General Test A1 Register -------- */ +#define USBHS_TSTA1_CounterA_Pos 0 +#define USBHS_TSTA1_CounterA_Msk (0x7fffu << USBHS_TSTA1_CounterA_Pos) /**< \brief (USBHS_TSTA1) Counter A */ +#define USBHS_TSTA1_CounterA(value) ((USBHS_TSTA1_CounterA_Msk & ((value) << USBHS_TSTA1_CounterA_Pos))) +#define USBHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (USBHS_TSTA1) Load CounterA */ +#define USBHS_TSTA1_CounterB_Pos 16 +#define USBHS_TSTA1_CounterB_Msk (0x3fu << USBHS_TSTA1_CounterB_Pos) /**< \brief (USBHS_TSTA1) Counter B */ +#define USBHS_TSTA1_CounterB(value) ((USBHS_TSTA1_CounterB_Msk & ((value) << USBHS_TSTA1_CounterB_Pos))) +#define USBHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (USBHS_TSTA1) Load CounterB */ +#define USBHS_TSTA1_SOFCntMa1_Pos 24 +#define USBHS_TSTA1_SOFCntMa1_Msk (0x7fu << USBHS_TSTA1_SOFCntMa1_Pos) /**< \brief (USBHS_TSTA1) SOF Counter Max */ +#define USBHS_TSTA1_SOFCntMa1(value) ((USBHS_TSTA1_SOFCntMa1_Msk & ((value) << USBHS_TSTA1_SOFCntMa1_Pos))) +#define USBHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (USBHS_TSTA1) Load SOF Counter */ +/* -------- USBHS_TSTA2 : (USBHS Offset: 0x0814) General Test A2 Register -------- */ +#define USBHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (USBHS_TSTA2) Full Detach Enable */ +#define USBHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (USBHS_TSTA2) HS Serial Mode */ +#define USBHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (USBHS_TSTA2) Loop-back Mode */ +#define USBHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (USBHS_TSTA2) Disable Gated Clock */ +#define USBHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (USBHS_TSTA2) Force SuspendM to 1 */ +#define USBHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (USBHS_TSTA2) Bypass DPLL */ +#define USBHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (USBHS_TSTA2) Host HS Disconnect Disable */ +#define USBHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (USBHS_TSTA2) Force HS Reset to 50 ms */ +#define USBHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (USBHS_TSTA2) Remove Pull-up When TX */ +/* -------- USBHS_VERSION : (USBHS Offset: 0x0818) General Version Register -------- */ +#define USBHS_VERSION_VERSION_Pos 0 +#define USBHS_VERSION_VERSION_Msk (0xfffu << USBHS_VERSION_VERSION_Pos) /**< \brief (USBHS_VERSION) Version Number */ +#define USBHS_VERSION_MFN_Pos 16 +#define USBHS_VERSION_MFN_Msk (0xfu << USBHS_VERSION_MFN_Pos) /**< \brief (USBHS_VERSION) Metal Fix Number */ +/* -------- USBHS_FSM : (USBHS Offset: 0x082C) General Finite State Machine Register -------- */ +#define USBHS_FSM_DRDSTATE_Pos 0 +#define USBHS_FSM_DRDSTATE_Msk (0xfu << USBHS_FSM_DRDSTATE_Pos) /**< \brief (USBHS_FSM) Dual Role Device State */ +#define USBHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (USBHS_FSM) This is the start state for A-devices (when the ID pin is 0) */ +#define USBHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */ +#define USBHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */ +#define USBHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (USBHS_FSM) In this state, the A-device that operates in Host mode is operational. */ +#define USBHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (USBHS_FSM) The A-device operating as a host is in the Suspend mode. */ +#define USBHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (USBHS_FSM) The A-device operates as a peripheral. */ +#define USBHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */ +#define USBHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */ +#define USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */ +#define USBHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (USBHS_FSM) This is the start state for B-device (when the ID pin is 1). */ +#define USBHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the peripheral. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (USBHS_FSM) In this state, the B-device is in Suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us)) before becoming Host. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */ +#define USBHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the Host. */ +#define USBHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (USBHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */ + +/*@}*/ + + +#endif /* _SAMV71_USBHS_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_utmi.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_utmi.h new file mode 100644 index 0000000000..abdde2f148 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_utmi.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UTMI_COMPONENT_ +#define _SAMV71_UTMI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Transmitter Interface Macrocell */ +/* ============================================================================= */ +/** \addtogroup SAMV71_UTMI USB Transmitter Interface Macrocell */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Utmi hardware registers */ +typedef struct { + __I uint32_t Reserved1[4]; + __IO uint32_t UTMI_OHCIICR; /**< \brief (Utmi Offset: 0x10) OHCI Interrupt Configuration Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t UTMI_CKTRIM; /**< \brief (Utmi Offset: 0x30) UTMI Clock Trimming Register */ +} Utmi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) OHCI Interrupt Configuration Register -------- */ +#define UTMI_OHCIICR_RES0 (0x1u << 0) /**< \brief (UTMI_OHCIICR) USB PORTx Reset */ +#define UTMI_OHCIICR_ARIE (0x1u << 4) /**< \brief (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */ +#define UTMI_OHCIICR_APPSTART (0x1u << 5) /**< \brief (UTMI_OHCIICR) Reserved */ +#define UTMI_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (UTMI_OHCIICR) USB Device Pull-up Disable */ +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) UTMI Clock Trimming Register -------- */ +#define UTMI_CKTRIM_FREQ_Pos 0 +#define UTMI_CKTRIM_FREQ_Msk (0x3u << UTMI_CKTRIM_FREQ_Pos) /**< \brief (UTMI_CKTRIM) UTMI Reference Clock Frequency */ +#define UTMI_CKTRIM_FREQ(value) ((UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos))) +#define UTMI_CKTRIM_FREQ_XTAL12 (0x0u << 0) /**< \brief (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16 (0x1u << 0) /**< \brief (UTMI_CKTRIM) 16 MHz reference clock */ + +/*@}*/ + + +#endif /* _SAMV71_UTMI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_wdt.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_wdt.h new file mode 100644 index 0000000000..1c6d5b4321 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_wdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_WDT_COMPONENT_ +#define _SAMV71_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMV71_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */ + +/*@}*/ + + +#endif /* _SAMV71_WDT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_xdmac.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_xdmac.h new file mode 100644 index 0000000000..a36f4525f0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_xdmac.h @@ -0,0 +1,625 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_XDMAC_COMPONENT_ +#define _SAMV71_XDMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_XDMAC Extensible DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief XdmacChid hardware registers */ +typedef struct { + __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */ + __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */ + __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */ + __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */ + __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */ + __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */ + __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */ + __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */ + __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */ + __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */ + __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */ + __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */ + __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */ + __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */ + __I uint32_t Reserved1[2]; +} XdmacChid; +/** \brief Xdmac hardware registers */ +#define XDMACCHID_NUMBER 24 +typedef struct { + __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */ + __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */ + __I uint32_t Reserved1[3]; + XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */ + __I uint32_t Reserved2[619]; + __IO uint32_t XDMAC_VERSION; /**< \brief (Xdmac Offset: 0xFFC) XDMAC Version Register */ +} Xdmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */ +#define XDMAC_GTYPE_NB_CH_Pos 0 +#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */ +#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) +#define XDMAC_GTYPE_FIFO_SZ_Pos 5 +#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */ +#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) +#define XDMAC_GTYPE_NB_REQ_Pos 16 +#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */ +#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */ +#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */ +#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */ +#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */ +#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */ +#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilobyte Enable */ +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */ +#define XDMAC_GWAC_PW0_Pos 0 +#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */ +#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) +#define XDMAC_GWAC_PW1_Pos 4 +#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */ +#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) +#define XDMAC_GWAC_PW2_Pos 8 +#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */ +#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) +#define XDMAC_GWAC_PW3_Pos 12 +#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */ +#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */ +#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */ +#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */ +#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */ +#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */ +#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */ +#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */ +#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */ +#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */ +#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */ +#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */ +#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */ +#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */ +#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */ +#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */ +#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */ +#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */ +#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */ +#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */ +#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */ +#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */ +#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */ +#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */ +#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */ +#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */ +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */ +#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */ +#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */ +#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */ +#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */ +#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */ +#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */ +#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */ +#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */ +#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */ +#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */ +#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */ +#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */ +#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */ +#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */ +#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */ +#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */ +#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */ +#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */ +#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */ +#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */ +#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */ +#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */ +#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */ +#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */ +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */ +#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */ +#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */ +#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */ +#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */ +#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */ +#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */ +#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */ +#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */ +#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */ +#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */ +#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */ +#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */ +#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */ +#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */ +#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */ +#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */ +#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */ +#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */ +#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */ +#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */ +#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */ +#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */ +#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */ +#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */ +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */ +#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */ +#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */ +#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */ +#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */ +#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */ +#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */ +#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */ +#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */ +#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */ +#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */ +#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */ +#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */ +#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */ +#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */ +#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */ +#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */ +#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */ +#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */ +#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */ +#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */ +#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */ +#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */ +#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */ +#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */ +/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */ +#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */ +#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */ +#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */ +#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */ +#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */ +#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */ +#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */ +#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */ +#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */ +#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */ +#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */ +#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */ +#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */ +#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */ +#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */ +#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */ +#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */ +#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */ +#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */ +#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */ +#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */ +#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */ +#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */ +#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */ +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */ +#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */ +#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */ +#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */ +#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */ +#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */ +#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */ +#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */ +#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */ +#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */ +#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */ +#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */ +#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */ +#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */ +#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */ +#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */ +#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */ +#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */ +#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */ +#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */ +#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */ +#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */ +#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */ +#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */ +#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */ +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */ +#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */ +#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */ +#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */ +#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */ +#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */ +#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */ +#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */ +#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */ +#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */ +#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */ +#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */ +#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */ +#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */ +#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */ +#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */ +#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */ +#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */ +#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */ +#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */ +#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */ +#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */ +#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */ +#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */ +#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */ +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */ +#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */ +#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */ +#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */ +#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */ +#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */ +#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */ +#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */ +#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */ +#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */ +#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */ +#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */ +#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */ +#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */ +#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */ +#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */ +#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */ +#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */ +#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */ +#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */ +#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */ +#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */ +#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */ +#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */ +#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */ +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */ +#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */ +#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */ +#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */ +#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */ +#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */ +#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */ +#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */ +#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */ +#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */ +#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */ +#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */ +#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */ +#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */ +#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */ +#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */ +#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */ +#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */ +#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */ +#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */ +#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */ +#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */ +#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */ +#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */ +#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */ +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */ +#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */ +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */ +#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */ +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */ +#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */ +#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */ +#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */ +#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */ +#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */ +#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */ +#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */ +#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */ +#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */ +#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */ +#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */ +#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */ +#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */ +#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */ +#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */ +#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */ +#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */ +#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */ +#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */ +#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */ +#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */ +#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */ +#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */ +#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */ +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */ +#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */ +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */ +#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */ +/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */ +#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */ +#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */ +#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */ +#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */ +#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */ +/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */ +#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */ +#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */ +#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */ +#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */ +#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */ +/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */ +#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */ +#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */ +#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */ +#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */ +#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */ +/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */ +#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */ +#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */ +#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */ +#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */ +#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */ +/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */ +#define XDMAC_CSA_SA_Pos 0 +#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */ +#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) +/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */ +#define XDMAC_CDA_DA_Pos 0 +#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */ +#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) +/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */ +#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */ +#define XDMAC_CNDA_NDA_Pos 2 +#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */ +#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos))) +/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */ +#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled. */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled. */ +#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDVIEW_Pos 3 +#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */ +#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) +#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */ +/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */ +#define XDMAC_CUBC_UBLEN_Pos 0 +#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */ +#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) +/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */ +#define XDMAC_CBC_BLEN_Pos 0 +#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */ +#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) +/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */ +#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */ +#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */ +#define XDMAC_CC_MBSIZE_Pos 1 +#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */ +#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) +#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */ +#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer. */ +#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer. */ +#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated. */ +#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */ +#define XDMAC_CC_CSIZE_Pos 8 +#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */ +#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) +#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_DWIDTH_Pos 11 +#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */ +#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) +#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */ +#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0. */ +#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1. */ +#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */ +#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0. */ +#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1. */ +#define XDMAC_CC_SAM_Pos 16 +#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */ +#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) +#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_Pos 18 +#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */ +#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) +#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */ +#define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */ +#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */ +#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */ +#define XDMAC_CC_PERID_Pos 24 +#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier */ +#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */ +#define XDMAC_CDS_MSP_SDS_MSP_Pos 0 +#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) +#define XDMAC_CDS_MSP_DDS_MSP_Pos 16 +#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) +/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */ +#define XDMAC_CSUS_SUBS_Pos 0 +#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */ +#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) +/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */ +#define XDMAC_CDUS_DUBS_Pos 0 +#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */ +#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) +/* -------- XDMAC_VERSION : (XDMAC Offset: 0xFFC) XDMAC Version Register -------- */ +#define XDMAC_VERSION_VERSION_Pos 0 +#define XDMAC_VERSION_VERSION_Msk (0xfffu << XDMAC_VERSION_VERSION_Pos) /**< \brief (XDMAC_VERSION) Version of the Hardware Module */ +#define XDMAC_VERSION_VERSION(value) ((XDMAC_VERSION_VERSION_Msk & ((value) << XDMAC_VERSION_VERSION_Pos))) +#define XDMAC_VERSION_MFN_Pos 16 +#define XDMAC_VERSION_MFN_Msk (0x7u << XDMAC_VERSION_MFN_Pos) /**< \brief (XDMAC_VERSION) Metal Fix Number */ +#define XDMAC_VERSION_MFN(value) ((XDMAC_VERSION_MFN_Msk & ((value) << XDMAC_VERSION_MFN_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_XDMAC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j19.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j19.h new file mode 100644 index 0000000000..c2adb67e71 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j19.h @@ -0,0 +1,441 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J19_PIO_ +#define _SAMV71J19_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71J19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j20.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j20.h new file mode 100644 index 0000000000..311e7f1a48 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j20.h @@ -0,0 +1,442 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J20_PIO_ +#define _SAMV71J20_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71J20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j21.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j21.h new file mode 100644 index 0000000000..f04d899e72 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j21.h @@ -0,0 +1,442 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J21_PIO_ +#define _SAMV71J21_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71J21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n19.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n19.h new file mode 100644 index 0000000000..d8060f8efd --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n19.h @@ -0,0 +1,499 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N19_PIO_ +#define _SAMV71N19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71N19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n20.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n20.h new file mode 100644 index 0000000000..b8670d4034 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n20.h @@ -0,0 +1,498 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N20_PIO_ +#define _SAMV71N20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71N20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n21.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n21.h new file mode 100644 index 0000000000..134f9f7e1a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n21.h @@ -0,0 +1,498 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N21_PIO_ +#define _SAMV71N21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71N21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q19.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q19.h new file mode 100644 index 0000000000..37925fd3f9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q19.h @@ -0,0 +1,672 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q19_PIO_ +#define _SAMV71Q19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMV71Q19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q20.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q20.h new file mode 100644 index 0000000000..fcd68f266f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q20.h @@ -0,0 +1,672 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q20_PIO_ +#define _SAMV71Q20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMV71Q20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q21.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q21.h new file mode 100644 index 0000000000..aaa19aad5b --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q21.h @@ -0,0 +1,672 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q21_PIO_ +#define _SAMV71Q21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMV71Q21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71.h new file mode 100644 index 0000000000..4bdbce555e --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71.h @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ +#define _SAMV71_ + +#ifdef __rtems__ +#include +#endif /* __rtems__ */ +#if defined __SAMV71J19__ + #include "samv71j19.h" +#elif defined __SAMV71J20__ + #include "samv71j20.h" +#elif defined __SAMV71J21__ + #include "samv71j21.h" +#elif defined __SAMV71N19__ + #include "samv71n19.h" +#elif defined __SAMV71N20__ + #include "samv71n20.h" +#elif defined __SAMV71N21__ + #include "samv71n21.h" +#elif defined __SAMV71Q19__ + #include "samv71q19.h" +#elif defined __SAMV71Q20__ + #include "samv71q20.h" +#elif defined __SAMV71Q21__ + #include "samv71q21.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAMV71_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71j19.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71j19.h new file mode 100644 index 0000000000..ad3c38f6ab --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71j19.h @@ -0,0 +1,637 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J19_ +#define _SAMV71J19_ + +/** \addtogroup SAMV71J19_definitions SAMV71J19 definitions + This file defines all structures and symbols for SAMV71J19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71J19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71J19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71J19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71J19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71J19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71J19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71J19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71J19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71J19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71J19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71J19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71J19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71J19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71J19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71J19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71J19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71J19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71J19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71J19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71J19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71J19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71J19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71J19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71J19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71J19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71J19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71J19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71J19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71J19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71J19 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71J19 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71J19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71J19 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMV71J19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71J19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71J19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71J19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71J19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71J19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71J19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71J19 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71J19 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71J19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71J19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71J19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71J19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71J19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71J19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71J19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71J19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71J19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71J19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71J19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71J19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71J19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71J19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71J19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71j19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA12D0A00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71J19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71j20.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71j20.h new file mode 100644 index 0000000000..9df556c9f0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71j20.h @@ -0,0 +1,637 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J20_ +#define _SAMV71J20_ + +/** \addtogroup SAMV71J20_definitions SAMV71J20 definitions + This file defines all structures and symbols for SAMV71J20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71J20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71J20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71J20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71J20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71J20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71J20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71J20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71J20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71J20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71J20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71J20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71J20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71J20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71J20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71J20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71J20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71J20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71J20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71J20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71J20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71J20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71J20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71J20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71J20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71J20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71J20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71J20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71J20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71J20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71J20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71J20 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71J20 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71J20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71J20 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMV71J20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71J20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71J20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71J20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71J20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71J20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71J20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71J20 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71J20 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71J20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71J20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71J20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71J20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71J20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71J20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71J20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71J20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71J20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71J20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71J20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71J20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71J20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71J20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71J20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71j20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220C00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71J20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71j21.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71j21.h new file mode 100644 index 0000000000..4c306b8e23 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71j21.h @@ -0,0 +1,637 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J21_ +#define _SAMV71J21_ + +/** \addtogroup SAMV71J21_definitions SAMV71J21 definitions + This file defines all structures and symbols for SAMV71J21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71J21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71J21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71J21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71J21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71J21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71J21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71J21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71J21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71J21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71J21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71J21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71J21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71J21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71J21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71J21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71J21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71J21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71J21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71J21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71J21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71J21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71J21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71J21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71J21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71J21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71J21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71J21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71J21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71J21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71J21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71J21 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71J21 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71J21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71J21 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMV71J21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71J21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71J21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71J21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71J21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71J21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71J21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71J21 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71J21 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71J21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71J21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71J21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71J21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71J21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71J21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71J21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71J21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71J21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71J21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71J21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71J21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71J21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71J21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71J21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71j21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220E00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71J21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71n19.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71n19.h new file mode 100644 index 0000000000..8f2c0b9731 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71n19.h @@ -0,0 +1,643 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N19_ +#define _SAMV71N19_ + +/** \addtogroup SAMV71N19_definitions SAMV71N19 definitions + This file defines all structures and symbols for SAMV71N19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71N19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71N19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71N19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71N19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71N19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71N19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71N19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71N19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71N19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71N19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71N19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71N19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71N19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71N19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71N19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71N19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71N19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71N19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71N19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71N19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71N19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71N19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71N19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71N19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71N19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71N19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71N19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71N19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71N19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71N19 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71N19 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71N19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71N19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71N19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71N19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71N19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71N19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71N19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71N19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71N19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71N19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71N19 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71N19 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71N19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71N19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71N19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71N19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71N19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71N19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71N19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71N19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71N19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71N19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71N19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71N19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71N19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71N19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71N19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71n19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA12D0A00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71N19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71n20.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71n20.h new file mode 100644 index 0000000000..e709e5f736 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71n20.h @@ -0,0 +1,643 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N20_ +#define _SAMV71N20_ + +/** \addtogroup SAMV71N20_definitions SAMV71N20 definitions + This file defines all structures and symbols for SAMV71N20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71N20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71N20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71N20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71N20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71N20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71N20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71N20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71N20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71N20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71N20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71N20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71N20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71N20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71N20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71N20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71N20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71N20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71N20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71N20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71N20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71N20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71N20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71N20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71N20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71N20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71N20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71N20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71N20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71N20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71N20 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71N20 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71N20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71N20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71N20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71N20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71N20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71N20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71N20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71N20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71N20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71N20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71N20 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71N20 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71N20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71N20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71N20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71N20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71N20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71N20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71N20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71N20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71N20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71N20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71N20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71N20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71N20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71N20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71N20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71n20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220C00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71N20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71n21.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71n21.h new file mode 100644 index 0000000000..dc1ef6e8a2 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71n21.h @@ -0,0 +1,643 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N21_ +#define _SAMV71N21_ + +/** \addtogroup SAMV71N21_definitions SAMV71N21 definitions + This file defines all structures and symbols for SAMV71N21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71N21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71N21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71N21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71N21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71N21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71N21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71N21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71N21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71N21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71N21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71N21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71N21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71N21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71N21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71N21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71N21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71N21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71N21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71N21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71N21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71N21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71N21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71N21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71N21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71N21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71N21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71N21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71N21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71N21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71N21 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71N21 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71N21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71N21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71N21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71N21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71N21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71N21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71N21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71N21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71N21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71N21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71N21 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71N21 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71N21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71N21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71N21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71N21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71N21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71N21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71N21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71N21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71N21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71N21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71N21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71N21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71N21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71N21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71N21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71n21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220E00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71N21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71q19.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71q19.h new file mode 100644 index 0000000000..e42381c63c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71q19.h @@ -0,0 +1,691 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q19_ +#define _SAMV71Q19_ + +/** \addtogroup SAMV71Q19_definitions SAMV71Q19 definitions + This file defines all structures and symbols for SAMV71Q19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71Q19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71Q19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71Q19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71Q19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71Q19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71Q19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71Q19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71Q19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71Q19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71Q19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71Q19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71Q19 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMV71Q19 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMV71Q19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71Q19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71Q19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71Q19 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMV71Q19 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMV71Q19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71Q19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71Q19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71Q19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71Q19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71Q19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71Q19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71Q19 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMV71Q19 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMV71Q19 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMV71Q19 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMV71Q19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71Q19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71Q19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71Q19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71Q19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71Q19 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71Q19 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71Q19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71Q19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71Q19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71Q19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71Q19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71Q19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71Q19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71Q19 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMV71Q19 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMV71Q19 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMV71Q19 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMV71Q19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71Q19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71Q19 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71Q19 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71Q19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71Q19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71Q19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71Q19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71Q19 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMV71Q19 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMV71Q19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71Q19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71Q19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71Q19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71Q19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71Q19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71Q19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71Q19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71Q19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71Q19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71q19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA12D0A00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71Q19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71q20.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71q20.h new file mode 100644 index 0000000000..cfc1780b56 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71q20.h @@ -0,0 +1,691 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q20_ +#define _SAMV71Q20_ + +/** \addtogroup SAMV71Q20_definitions SAMV71Q20 definitions + This file defines all structures and symbols for SAMV71Q20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71Q20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71Q20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71Q20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71Q20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71Q20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71Q20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71Q20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71Q20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71Q20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71Q20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71Q20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71Q20 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMV71Q20 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMV71Q20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71Q20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71Q20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71Q20 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMV71Q20 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMV71Q20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71Q20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71Q20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71Q20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71Q20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71Q20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71Q20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71Q20 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMV71Q20 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMV71Q20 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMV71Q20 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMV71Q20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71Q20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71Q20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71Q20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71Q20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71Q20 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71Q20 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71Q20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71Q20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71Q20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71Q20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71Q20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71Q20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71Q20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71Q20 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMV71Q20 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMV71Q20 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMV71Q20 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMV71Q20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71Q20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71Q20 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71Q20 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71Q20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71Q20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71Q20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71Q20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71Q20 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMV71Q20 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMV71Q20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71Q20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71Q20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71Q20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71Q20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71Q20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71Q20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71Q20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71Q20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71Q20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71q20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220C00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71Q20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71q21.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71q21.h new file mode 100644 index 0000000000..401ee9b8be --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71q21.h @@ -0,0 +1,696 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q21_ +#define _SAMV71Q21_ + +/** \addtogroup SAMV71Q21_definitions SAMV71Q21 definitions + This file defines all structures and symbols for SAMV71Q21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71Q21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71Q21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71Q21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71Q21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71Q21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71Q21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71Q21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71Q21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71Q21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71Q21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71Q21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71Q21 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMV71Q21 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMV71Q21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71Q21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71Q21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71Q21 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMV71Q21 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMV71Q21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71Q21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71Q21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71Q21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71Q21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71Q21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71Q21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71Q21 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMV71Q21 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMV71Q21 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMV71Q21 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMV71Q21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71Q21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71Q21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71Q21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71Q21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71Q21 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71Q21 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71Q21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71Q21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71Q21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71Q21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71Q21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71Q21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71Q21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71Q21 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMV71Q21 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMV71Q21 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMV71Q21 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMV71Q21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71Q21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71Q21 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71Q21 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71Q21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71Q21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71Q21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71Q21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71Q21 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMV71Q21 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMV71Q21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler ( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71Q21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71Q21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71Q21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71Q21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71Q21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71Q21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71Q21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71Q21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71Q21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71q21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ +#define USBHS_RAM_ADDR (0xA0100000u)/**< USB RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220E00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71Q21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/system_samv71.h b/bsps/arm/atsam/include/libchip/include/samv71/system_samv71.h new file mode 100644 index 0000000000..f38282d233 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/system_samv71.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef SYSTEM_SAMV71_H_INCLUDED +#define SYSTEM_SAMV71_H_INCLUDED +#ifdef __rtems__ +#include +#endif /* __rtems__ */ + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +#ifndef __rtems__ +void SystemInit(void); +#else /* __rtems__ */ +void ATSAM_START_SRAM_SECTION SystemInit(void); +#endif /* __rtems__ */ + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t dw_clk); + +void sysclk_enable_usb(void); +void sysclk_disable_usb(void); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAMV71_H_INCLUDED */ diff --git a/bsps/arm/atsam/include/libchip/include/sdramc.h b/bsps/arm/atsam/include/libchip/include/sdramc.h new file mode 100644 index 0000000000..078127fbe9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sdramc.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Definitions and function prototype for SDRAMC. + */ + +// --------------------------------------------------------------------------- +// SDRAM +// --------------------------------------------------------------------------- +/** SDRAMC Configuration */ +#define EBI_SDRAMC_ADDR (0x70000000u) + +/** SDRAM bus width */ +#define BOARD_SDRAM_BUSWIDTH 16 + + +typedef struct _SSdramc_config { + uint32_t dwColumnBits; // Number of Column Bits + uint32_t dwRowBits; // Number of Row Bits + uint32_t dwBanks; // Number of Banks + uint32_t dwCAS; // CAS Latency + uint32_t dwDataBusWidth; // Data Bus Width + uint32_t dwWriteRecoveryDelay; // Write Recovery Delay + uint32_t dwRowCycleDelay_RowRefreshCycle; // Row Cycle Delay and Row Refresh Cycle + uint32_t dwRowPrechargeDelay; // Row Precharge Delay + uint32_t dwRowColumnDelay; // Row to Column Delay + uint32_t dwActivePrechargeDelay; // Active to Precharge Delay + uint32_t dwExitSelfRefreshActiveDelay; // Exit Self Refresh to Active Delay + uint32_t dwBK1; // bk1 addr + +} SSdramc_config; + +typedef struct _SSdramc_Memory { + SSdramc_config cfg; + +} SSdramc_Memory; + +extern void SDRAMC_Configure(SSdramc_Memory *pMemory, + uint32_t dwClockFrequency); diff --git a/bsps/arm/atsam/include/libchip/include/smc.h b/bsps/arm/atsam/include/libchip/include/smc.h new file mode 100644 index 0000000000..72253ab38a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/smc.h @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** +* \file +* +* Definitions and function prototype for SMC module +*/ + +#ifndef _SMC_ +#define _SMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +typedef union _SmcStatus { + uint8_t BStatus; + struct _SmcStatusBits { + uint8_t smcSts: 1, /**< NAND Flash Controller Status */ + xfrDone: 1, /**< NFC Data Transfer Terminated */ + cmdDone: 1, /**< Command Done */ + rbEdge: 1, /**< Ready/Busy Line 3 Edge Detected*/ + hammingReady: 1; /**< Hamming ecc ready */ + } bStatus; +} SmcStatus; + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* + * NFC definitions + */ + +/** Base address of NFC SRAM */ +#define NFC_SRAM_BASE_ADDRESS 0x200000 +/** Base address for NFC Address Command */ +#define NFC_CMD_BASE_ADDR 0x70000000 + + +/* -------- NFCADDR_CMD : NFC Address Command -------- */ +#define NFCADDR_CMD_CMD1 (0xFFu << 2) +/* Command Register Value for Cycle 1 */ +#define NFCADDR_CMD_CMD2 (0xFFu << 10) +/* Command Register Value for Cycle 2 */ +#define NFCADDR_CMD_VCMD2 (0x1u << 18) +/* Valid Cycle 2 Command */ +#define NFCADDR_CMD_ACYCLE (0x7u << 19) +/* Number of Address required for the current command */ +#define NFCADDR_CMD_ACYCLE_NONE (0x0u << 19) +/* No address cycle */ +#define NFCADDR_CMD_ACYCLE_ONE (0x1u << 19) +/* One address cycle */ +#define NFCADDR_CMD_ACYCLE_TWO (0x2u << 19) +/* Two address cycles */ +#define NFCADDR_CMD_ACYCLE_THREE (0x3u << 19) +/* Three address cycles */ +#define NFCADDR_CMD_ACYCLE_FOUR (0x4u << 19) +/* Four address cycles */ +#define NFCADDR_CMD_ACYCLE_FIVE (0x5u << 19) +/* Five address cycles */ +#define NFCADDR_CMD_CSID (0x7u << 22) +/* Chip Select Identifier */ +#define NFCADDR_CMD_CSID_0 (0x0u << 22) +/* CS0 */ +#define NFCADDR_CMD_CSID_1 (0x1u << 22) +/* CS1 */ +#define NFCADDR_CMD_CSID_2 (0x2u << 22) +/* CS2 */ +#define NFCADDR_CMD_CSID_3 (0x3u << 22) +/* CS3 */ +#define NFCADDR_CMD_CSID_4 (0x4u << 22) +/* CS4 */ +#define NFCADDR_CMD_CSID_5 (0x5u << 22) +/* CS5 */ +#define NFCADDR_CMD_CSID_6 (0x6u << 22) +/* CS6 */ +#define NFCADDR_CMD_CSID_7 (0x7u << 22) +/* CS7 */ +#define NFCADDR_CMD_DATAEN (0x1u << 25) +/* NFC Data Enable */ +#define NFCADDR_CMD_DATADIS (0x0u << 25) +/* NFC Data disable */ +#define NFCADDR_CMD_NFCRD (0x0u << 26) +/* NFC Read Enable */ +#define NFCADDR_CMD_NFCWR (0x1u << 26) +/* NFC Write Enable */ +#define NFCADDR_CMD_NFCCMD (0x1u << 27) +/* NFC Command Enable */ + +/* + * ECC definitions (Hsiao Code Errors) + */ + +/** A single bit was incorrect but has been recovered. */ +#define Hsiao_ERROR_SINGLEBIT 1 + +/** The original code has been corrupted. */ +#define Hsiao_ERROR_ECC 2 + +/** Multiple bits are incorrect in the data and they cannot be corrected. */ +#define Hsiao_ERROR_MULTIPLEBITS 3 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/* + * NFC functions + */ + +extern void SMC_NFC_Configure(uint32_t mode); +extern void SMC_NFC_Reset(void); +extern void SMC_NFC_EnableNfc(void); +extern void SMC_NFC_EnableSpareRead(void); +extern void SMC_NFC_DisableSpareRead(void); +extern void SMC_NFC_EnableSpareWrite(void); +extern void SMC_NFC_DisableSpareWrite(void); +extern uint8_t SMC_NFC_isSpareRead(void); +extern uint8_t SMC_NFC_isSpareWrite(void); +extern uint8_t SMC_NFC_isTransferComplete(void); +extern uint8_t SMC_NFC_isReadyBusy(void); +extern uint8_t SMC_NFC_isNfcBusy(void); +extern uint32_t SMC_NFC_GetStatus(void); + +extern void SMC_NFC_SendCommand(uint32_t cmd, uint32_t addressCycle, + uint32_t cycle0); +extern void SMC_NFC_Wait_CommandDone(void); +extern void SMC_NFC_Wait_XfrDone(void); +extern void SMC_NFC_Wait_RBbusy(void); +extern void SMC_NFC_Wait_HammingReady(void); + +extern void SMC_ECC_Configure(uint32_t type, uint32_t pageSize); +extern uint32_t SMC_ECC_GetCorrectoinType(void); +extern uint8_t SMC_ECC_GetStatus(uint8_t eccNumber); + +extern void SMC_ECC_GetValue(uint32_t *ecc); +extern void SMC_ECC_GetEccParity(uint32_t pageDataSize, uint8_t *code, + uint8_t busWidth); +extern uint8_t SMC_ECC_VerifyHsiao(uint8_t *data, uint32_t size, + const uint8_t *originalCode, const uint8_t *verifyCode, uint8_t busWidth); + +#endif /* #ifndef _SMC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/spi.h b/bsps/arm/atsam/include/libchip/include/spi.h new file mode 100644 index 0000000000..0d888fbdfa --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/spi.h @@ -0,0 +1,116 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Interface for Serial Peripheral Interface (SPI) controller. + * + */ + +#ifndef _SPI_ +#define _SPI_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** + * + * Here are several macros which should be used when configuring a SPI + * peripheral. + * + * \section spi_configuration_macros SPI Configuration Macros + * - \ref SPI_PCS + * - \ref SPI_SCBR + * - \ref SPI_DLYBS + * - \ref SPI_DLYBCT + */ + +/** Calculate the PCS field value given the chip select NPCS value */ +#define SPI_PCS(npcs) SPI_MR_PCS((~(1 << npcs) & 0xF)) + +/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */ +#define SPI_SCBR(baudrate, masterClock) \ + SPI_CSR_SCBR((uint32_t)(masterClock / baudrate)) + +/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ +#define SPI_DLYBS(delay, masterClock) \ + SPI_CSR_DLYBS((uint32_t) (((masterClock / 1000000) * delay) / 1000)+1) + +/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */ +#define SPI_DLYBCT(delay, masterClock) \ + SPI_CSR_DLYBCT ((uint32_t) (((masterClock / 1000000) * delay) / 32000)+1) + +/*------------------------------------------------------------------------------ */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void SPI_Enable(Spi *spi); +extern void SPI_Disable(Spi *spi); + +extern void SPI_EnableIt(Spi *spi, uint32_t dwSources); +extern void SPI_DisableIt(Spi *spi, uint32_t dwSources); + +extern void SPI_Configure(Spi *spi, uint32_t dwId, uint32_t dwConfiguration); +extern void SPI_SetMode(Spi *spi, uint32_t dwConfiguration); + +extern void SPI_ChipSelect(Spi *spi, uint8_t cS); +extern void SPI_ReleaseCS(Spi *spi); + +extern void SPI_ConfigureNPCS(Spi *spi, uint32_t dwNpcs, + uint32_t dwConfiguration); +extern void SPI_ConfigureCSMode(Spi *spi, uint32_t dwNpcs, + uint32_t bReleaseOnLast); + +extern uint32_t SPI_Read(Spi *spi); +extern void SPI_Write(Spi *spi, uint32_t dwNpcs, uint16_t wData); +extern void SPI_WriteLast(Spi *spi, uint32_t dwNpcs, uint16_t wData); + +extern uint32_t SPI_GetStatus(Spi *spi); +extern uint32_t SPI_IsFinished(Spi *pSpi); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/spi_dma.h b/bsps/arm/atsam/include/libchip/include/spi_dma.h new file mode 100644 index 0000000000..72a77d512c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/spi_dma.h @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Implementation of SPI driver, transfer data through DMA. + * + */ + +#ifndef _SPI_DMA_ +#define _SPI_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define SPID_ERROR 1 + +/** SPI driver is currently in use.*/ +#define SPID_ERROR_LOCK 2 + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** Calculates the value of the SCBR field of the Chip Select Register + given MCK and SPCK.*/ +#define SPID_CSR_SCBR(mck, spck) SPI_CSR_SCBR((mck) / (spck)) + +/** Calculates the value of the DLYBS field of the Chip Select Register + given delay in ns and MCK.*/ +#define SPID_CSR_DLYBS(mck, delay) SPI_CSR_DLYBS((((delay) * \ + ((mck) / 1000000)) / 1000) + 1) + +/** Calculates the value of the DLYBCT field of the Chip Select Register + given delay in ns and MCK.*/ +#define SPID_CSR_DLYBCT(mck, delay) SPI_CSR_DLYBCT((((delay) / 32 * \ + ((mck) / 1000000)) / 1000) + 1) + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** SPI transfer complete callback. */ +typedef void (*SpidCallback)(uint8_t, void *); + +/** \brief Spi Transfer Request prepared by the application upper layer. + * + * This structure is sent to the SPI_SendCommand function to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct _SpidCmd { + /** Pointer to the Tx data. */ + uint8_t *pTxBuff; + /** Tx size in bytes. */ + uint8_t TxSize; + /** Pointer to the Rx data. */ + uint8_t *pRxBuff; + /** Rx size in bytes. */ + uint16_t RxSize; + /** SPI chip select. */ + uint8_t spiCs; + /** Callback function invoked at the end of transfer. */ + SpidCallback callback; + /** Callback arguments. */ + void *pArgument; +} SpidCmd; + +/** Constant structure associated with SPI port. This structure prevents + client applications to have access in the same time. */ +typedef struct _Spid { + /** Pointer to SPI Hardware registers */ + Spi *pSpiHw; + /** Current SpiCommand being processed */ + SpidCmd *pCurrentCommand; + /** Pointer to DMA driver */ + sXdmad *pXdmad; + /** SPI Id as defined in the product datasheet */ + uint8_t spiId; + /** Mutual exclusion semaphore. */ + volatile int8_t semaphore; +} Spid; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint32_t SPID_Configure(Spid *pSpid, + Spi *pSpiHw, + uint8_t spiId, + uint32_t SpiMode, + sXdmad *pXdmad); + +extern void SPID_ConfigureCS(Spid *pSpid, uint32_t dwCS, uint32_t dwCsr); + +extern uint32_t SPID_SendCommand(Spid *pSpid, SpidCmd *pCommand); + +extern void SPID_Handler(Spid *pSpid); + +extern void SPID_DmaHandler(Spid *pSpid); + +extern uint32_t SPID_IsBusy(const Spid *pSpid); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_DMA_ */ diff --git a/bsps/arm/atsam/include/libchip/include/ssc.h b/bsps/arm/atsam/include/libchip/include/ssc.h new file mode 100644 index 0000000000..bf76d6d2de --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/ssc.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Interface for Synchronous Serial (SSC) controller. + * + */ + +#ifndef _SSC_ +#define _SSC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void SSC_Configure(Ssc *ssc, uint32_t bitRate, uint32_t masterClock); +extern void SSC_ConfigureTransmitter(Ssc *ssc, uint32_t tcmr, uint32_t tfmr); +extern void SSC_ConfigureReceiver(Ssc *ssc, uint32_t rcmr, uint32_t rfmr); +extern void SSC_EnableTransmitter(Ssc *ssc); +extern void SSC_DisableTransmitter(Ssc *ssc); +extern void SSC_EnableReceiver(Ssc *ssc); +extern void SSC_DisableReceiver(Ssc *ssc); +extern void SSC_EnableInterrupts(Ssc *ssc, uint32_t sources); +extern void SSC_DisableInterrupts(Ssc *ssc, uint32_t sources); +extern void SSC_Write(Ssc *ssc, uint32_t frame); +extern uint32_t SSC_Read(Ssc *ssc); +extern uint8_t SSC_IsRxReady(Ssc *ssc); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SSC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/supc.h b/bsps/arm/atsam/include/libchip/include/supc.h new file mode 100644 index 0000000000..65d556372b --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/supc.h @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SUPC_H_ +#define _SUPC_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include + + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + + + +void SUPC_SelectExtCrystal32K(void); +uint8_t SUPC_IsSlowClkExtCrystal32K(void); +uint8_t SUPC_Read_Status(uint32_t status); +void SUPC_DisableSupplyMonitor(void); +void SUPC_DisableVoltageReg(void); +void SUPC_ConfigSupplyMonitor(uint32_t Config); +void SUPC_BrownoutDetectEnable(uint8_t enable); +void SUPC_BrownoutResetEnable(void); +void SUPC_SramBackupMode(uint8_t enable); +void SUPC_BypassXtal32KOsc(void); +void SUPC_EnablesWakeupInput(uint32_t Input, uint8_t enable); +void SUPC_SetLowPowerDebounce(uint8_t period); +void SUPC_SetWakeupDebounce(uint8_t period); +void SUPC_EnablesWakeupMode(uint32_t Regs, uint8_t enable); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PMC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/tc.h b/bsps/arm/atsam/include/libchip/include/tc.h new file mode 100644 index 0000000000..2136634475 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/tc.h @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef _TC_ +#define _TC_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void TC_Configure(Tc *pTc, uint32_t dwChannel, uint32_t dwMode); + +extern void TC_Start(Tc *pTc, uint32_t dwChannel); + +extern void TC_Stop(Tc *pTc, uint32_t dwChannel); + +extern uint32_t TC_FindMckDivisor(uint32_t dwFreq, uint32_t dwMCk, + uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _TC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/timetick.h b/bsps/arm/atsam/include/libchip/include/timetick.h new file mode 100644 index 0000000000..ac12a8b25a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/timetick.h @@ -0,0 +1,101 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \par Purpose + * + * Methods and definitions for Global time tick and wait functions. + * + * Defines a common and simplest use of Time Tick, to increase tickCount + * every 1ms, the application can get this value through GetTickCount(). + * + * \par Usage + * + * -# Configure the System Tick with TimeTick_Configure() when MCK changed + * \note + * Must be done before any invoke of GetTickCount(), Wait() or Sleep(). + * -# Uses GetTickCount to get current tick value. + * -# Uses Wait to wait several ms. + * -# Uses Sleep to enter wait for interrupt mode to wait several ms. + * + */ + +#ifndef _TIMETICK_ +#define _TIMETICK_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +typedef struct { + volatile uint32_t *pTimer1; + volatile uint32_t *pTimer2; + volatile uint32_t *pTimer3; + volatile uint32_t *pTimer4; +} SyTickDelayCounter_t; + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +typedef struct _TimeEvent { + uint32_t event; + uint32_t time_tick; + uint32_t time_start; + uint32_t occur; + struct _TimeEvent *pPreEvent; + struct _TimeEvent *pNextEvent; +} TimeEvent; + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +uint32_t TimeTick_Configure(void); + +void TimeTick_Increment(uint32_t dwInc); + +uint32_t GetDelayInTicks(uint32_t startTick, uint32_t endTick); + +uint32_t GetTicks(void); + +void Wait(volatile uint32_t dwMs); + +void Sleep(volatile uint32_t dwMs); + +extern void SetTimeEvent(TimeEvent *pEvent); + +#endif /* _TIMETICK_ */ diff --git a/bsps/arm/atsam/include/libchip/include/trace.h b/bsps/arm/atsam/include/libchip/include/trace.h new file mode 100644 index 0000000000..95a613f69a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/trace.h @@ -0,0 +1,231 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \par Purpose + * + * Standard output methods for reporting debug information, warnings and + * errors, which can be easily be turned on/off. + * + * \par Usage + * -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually + * disable ALL traces; otherwise use DBGU_Configure(). + * -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR() + * TRACE_FATAL() macros to output traces throughout the program. + * -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2 + * and Fatal 1. Disable a group of traces by changing the value of + * TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL + * are not generated. To generate no trace, use the reserved value 0. + * -# Trace disabling can be static or dynamic. If dynamic disabling is selected + * the trace level can be modified in runtime. If static disabling is selected + * the disabled traces are not compiled. + * + * \par traceLevels Trace level description + * -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program, + * and which do not produce meaningful information otherwise. + * -# TRACE_INFO (4): Informational trace about the program execution. Should + * enable the user to see the execution flow. + * -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case + * it can be discarded safely; it may even be expected. + * -# TRACE_ERROR (2): Indicates an error which may not stop the program execution, + * but which indicates there is a problem with the code. + * -# TRACE_FATAL (1): Indicates a major error which prevents the program from going + * any further. + */ + +#ifndef _TRACE_ +#define _TRACE_ + +/* + * Headers + */ + +#include "pio.h" + +#include + +/* + * Global Definitions + */ + +/** Softpack Version */ +#define SOFTPACK_VERSION "1.5" + + +#define TRACE_LEVEL_DEBUG 5 +#define TRACE_LEVEL_INFO 4 +#define TRACE_LEVEL_WARNING 3 +#define TRACE_LEVEL_ERROR 2 +#define TRACE_LEVEL_FATAL 1 +#define TRACE_LEVEL_NO_TRACE 0 + +/* By default, all traces are output except the debug one. */ +#if !defined(TRACE_LEVEL) + #define TRACE_LEVEL TRACE_LEVEL_INFO +#endif + +/* By default, trace level is static (not dynamic) */ +#if !defined(DYN_TRACES) + #define DYN_TRACES 0 +#endif + +#if defined(NOTRACE) + #error "Error: NOTRACE has to be not defined !" +#endif + +#undef NOTRACE +#if (DYN_TRACES==0) + #if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE) + #define NOTRACE + #endif +#endif + + + +/* ------------------------------------------------------------------------------ + * Global Macros + * ------------------------------------------------------------------------------ + */ + +extern void TRACE_CONFIGURE(uint32_t dwBaudRate, uint32_t dwMCk); + +/** + * Initializes the DBGU for ISP project + * + * \param mode DBGU mode. + * \param baudrate DBGU baudrate. + * \param mck Master clock frequency. + */ +#ifndef DYNTRACE + #define DYNTRACE 0 +#endif + +#if (TRACE_LEVEL==0) && (DYNTRACE==0) +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {} +#else +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \ + const Pin pinsUART0[] = {PINS_UART}; \ + PIO_Configure(pinsUART0, PIO_LISTSIZE(pinsUART0)); \ + UART_Configure(baudrate, mck); \ + } +#endif + +/** + * Outputs a formatted string using 'printf' if the log level is high + * enough. Can be disabled by defining TRACE_LEVEL=0 during compilation. + * \param ... Additional parameters depending on formatted string. + */ +#if defined(NOTRACE) + + /* Empty macro */ + #define TRACE_DEBUG(...) { } + #define TRACE_INFO(...) { } + #define TRACE_WARNING(...) { } + #define TRACE_ERROR(...) { } + #define TRACE_FATAL(...) { while (1); } + + #define TRACE_DEBUG_WP(...) { } + #define TRACE_INFO_WP(...) { } + #define TRACE_WARNING_WP(...) { } + #define TRACE_ERROR_WP(...) { } + #define TRACE_FATAL_WP(...) { while (1); } + +#elif (DYN_TRACES == 1) + + /* Trace output depends on dwTraceLevel value */ + #define TRACE_DEBUG(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf("-D- " __VA_ARGS__); } } + #define TRACE_INFO(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } } + #define TRACE_WARNING(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } } + #define TRACE_ERROR(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } } + #define TRACE_FATAL(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while (1); } } + + #define TRACE_DEBUG_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } } + #define TRACE_INFO_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } } + #define TRACE_WARNING_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } } + #define TRACE_ERROR_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } } + #define TRACE_FATAL_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while (1); } } + +#else + + /* Trace compilation depends on TRACE_LEVEL value */ + #if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG) + #define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); } + #define TRACE_DEBUG_WP(...) { printf(__VA_ARGS__); } + #else + #define TRACE_DEBUG(...) { } + #define TRACE_DEBUG_WP(...) { } + #endif + + #if (TRACE_LEVEL >= TRACE_LEVEL_INFO) + #define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); } + #define TRACE_INFO_WP(...) { printf(__VA_ARGS__); } + #else + #define TRACE_INFO(...) { } + #define TRACE_INFO_WP(...) { } + #endif + + #if (TRACE_LEVEL >= TRACE_LEVEL_WARNING) + #define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); } + #define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); } + #else + #define TRACE_WARNING(...) { } + #define TRACE_WARNING_WP(...) { } + #endif + + #if (TRACE_LEVEL >= TRACE_LEVEL_ERROR) + #define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); } + #define TRACE_ERROR_WP(...) { printf(__VA_ARGS__); } + #else + #define TRACE_ERROR(...) { } + #define TRACE_ERROR_WP(...) { } + #endif + + #if (TRACE_LEVEL >= TRACE_LEVEL_FATAL) + #define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while (1); } + #define TRACE_FATAL_WP(...) { printf(__VA_ARGS__); while (1); } + #else + #define TRACE_FATAL(...) { while (1); } + #define TRACE_FATAL_WP(...) { while (1); } + #endif + +#endif + + +/** + * Exported variables + */ +/** Depending on DYN_TRACES, dwTraceLevel is a modifiable runtime variable or a define */ +#if !defined(NOTRACE) && (DYN_TRACES == 1) + extern uint32_t dwTraceLevel; +#endif + +#endif //#ifndef TRACE_H + diff --git a/bsps/arm/atsam/include/libchip/include/trng.h b/bsps/arm/atsam/include/libchip/include/trng.h new file mode 100644 index 0000000000..29b28314c6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/trng.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _TRNG_ +#define _TRNG_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*----------------------------------------------------------------------------*/ +/* Exported functions */ +/*----------------------------------------------------------------------------*/ + +void TRNG_Enable(void); +void TRNG_Disable(void); +void TRNG_EnableIt(void); +void TRNG_DisableIt(void); +uint32_t TRNG_GetStatus(void); +uint32_t TRNG_GetRandData(void); + +#endif /* #ifndef _TRNG_ */ diff --git a/bsps/arm/atsam/include/libchip/include/twi.h b/bsps/arm/atsam/include/libchip/include/twi.h new file mode 100644 index 0000000000..6a5de366f2 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/twi.h @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Interface for configuration the Two Wire Interface (TWI) peripheral. + * + */ + +#ifndef _TWI_ +#define _TWI_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ +/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given + status register value.*/ +#define TWI_STATUS_TXRDY(status) ((status & TWIHS_SR_TXRDY) == TWIHS_SR_TXRDY) + +/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given + status register value.*/ +#define TWI_STATUS_RXRDY(status) ((status & TWIHS_SR_RXRDY) == TWIHS_SR_RXRDY) + +/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given + status register value.*/ +#define TWI_STATUS_TXCOMP(status) ((status & TWIHS_SR_TXCOMP) == TWIHS_SR_TXCOMP) + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * External function + *----------------------------------------------------------------------------*/ + +extern void TWI_ConfigureMaster(Twihs *pTwi, uint32_t twck, uint32_t mck); + +extern void TWI_ConfigureSlave(Twihs *pTwi, uint8_t slaveAddress); + +extern void TWI_Stop(Twihs *pTwi); + +extern void TWI_StartRead( + Twihs *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize); + +extern uint8_t TWI_ReadByte(Twihs *pTwi); + +extern void TWI_WriteByte(Twihs *pTwi, uint8_t byte); + +extern void TWI_StartWrite( + Twihs *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t byte); + +extern uint8_t TWI_ByteReceived(Twihs *pTwi); + +extern uint8_t TWI_ByteSent(Twihs *pTwi); + +extern uint8_t TWI_TransferComplete(Twihs *pTwi); + +extern void TWI_EnableIt(Twihs *pTwi, uint32_t sources); + +extern void TWI_DisableIt(Twihs *pTwi, uint32_t sources); + +extern uint32_t TWI_GetStatus(Twihs *pTwi); + +extern uint32_t TWI_GetMaskedStatus(Twihs *pTwi); + +extern void TWI_SendSTOPCondition(Twihs *pTwi); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _TWI_ */ diff --git a/bsps/arm/atsam/include/libchip/include/twid.h b/bsps/arm/atsam/include/libchip/include/twid.h new file mode 100644 index 0000000000..564a93339f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/twid.h @@ -0,0 +1,140 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _TWID_ +#define _TWID_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ + +/** TWI driver is currently busy. */ +#define TWID_ERROR_BUSY 1 + +/** Transfer is still pending.*/ +#define ASYNC_STATUS_PENDING 0xFF +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- +* Type +*----------------------------------------------------------------------------*/ +/** \brief Asynchronous transfer descriptor. */ +typedef struct _Async { + /** Asynchronous transfer status.*/ + volatile uint32_t status; + /** Callback function to invoke when transfer completes or fails.*/ + void *callback; + /** Driver storage area; do not use.*/ + uint8_t pStorage[9]; +} Async; + +/** \brief TWI driver structure. Holds the internal state of the driver.*/ +typedef struct _Twid { + /** Pointer to the underlying TWI peripheral.*/ + Twihs *pTwi; + /** Current asynchronous transfer being processed.*/ + Async *pTransfer; +} Twid; + +/** \brief TWI driver structure. Holds the internal state of the driver.*/ +typedef struct { + uint8_t Twi_id; + /** Pointer to the underlying TWI driver.*/ + Twid *pTwid; + /** Pointer to the underlying DMA driver for TWI.*/ + sXdmad *pTwiDma; +} TwihsDma; + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ +extern void TWID_Initialize(Twid *pTwid, Twihs *pTwi); +extern void TWID_DmaInitialize(TwihsDma *pTwidma, Twihs *pTwi, + uint8_t bPolling); + +extern void TWID_Handler(Twid *pTwid); + +extern uint32_t ASYNC_IsFinished(Async *pAsync); + +extern uint8_t TWID_Read( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_Write( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_DmaRead( + TwihsDma *pTwiXdma, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_DmaWrite( + TwihsDma *pTwiXdma, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +#ifdef __cplusplus +} +#endif + +#endif //#ifndef TWID_H + diff --git a/bsps/arm/atsam/include/libchip/include/uart.h b/bsps/arm/atsam/include/libchip/include/uart.h new file mode 100644 index 0000000000..4380856285 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/uart.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef UART_H +#define UART_H + + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +void UART_Configure(Uart *uart, uint32_t mode, uint32_t baudrate, + uint32_t masterClock); + +void UART_SetTransmitterEnabled(Uart *uart, uint8_t enabled); + +void UART_SetReceiverEnabled(Uart *uart, uint8_t enabled); + +void UART_PutChar(Uart *uart, uint8_t c); + +uint32_t UART_IsRxReady(Uart *uart); + +uint8_t UART_GetChar(Uart *uart); + +uint32_t UART_GetStatus(Uart *uart); + +void UART_EnableIt(Uart *uart, uint32_t mode); + +void UART_DisableIt(Uart *uart, uint32_t mode); + +uint32_t UART_GetItMask(Uart *uart); + +void UART_SendBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen); + +void UART_ReceiveBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen); + +void UART_CompareConfig(Uart *uart, uint8_t Val1, uint8_t Val2); + +uint32_t UART_IsTxReady(Uart *uart); + +#endif //#ifndef UART_H + diff --git a/bsps/arm/atsam/include/libchip/include/uart_dma.h b/bsps/arm/atsam/include/libchip/include/uart_dma.h new file mode 100644 index 0000000000..8329b6b930 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/uart_dma.h @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Implementation of UART driver, transfer data through DMA. + * + */ + +#ifndef _UART_DMA_ +#define _UART_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define UARTD_ERROR 1 + +/** UART driver is currently in use.*/ +#define UARTD_ERROR_LOCK 2 + + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** UART transfer complete callback. */ +typedef void (*UartdCallback)(uint8_t, void *); + +/** \brief usart Transfer Request prepared by the application upper layer. + * + * This structure is sent to the UART_Send or UART_Rcv to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct { + /** Pointer to the Buffer. */ + uint8_t *pBuff; + /** Buff size in bytes. */ + uint32_t BuffSize; + /** Dma channel num. */ + uint32_t ChNum; + /** Callback function invoked at the end of transfer. */ + UartdCallback callback; + /** Callback arguments. */ + void *pArgument; + /** flag to indicate the current transfer. */ + volatile uint8_t sempaphore; + /* DMA LLI structure */ + LinkedListDescriporView1 *pLLIview; + /* DMA transfer type */ + eXdmadProgState dmaProgrammingMode; + /* DMA LLI size */ + uint16_t dmaBlockSize; + /* Flag using ring buffer or FiFo*/ + uint8_t dmaRingBuffer; +} UartChannel; + +/** Constant structure associated with UART port. This structure prevents + client applications to have access in the same time. */ +typedef struct { + /** USART Id as defined in the product datasheet */ + uint8_t uartId; + /** Pointer to DMA driver */ + sXdmad *pXdmad; + /** Pointer to UART Hardware registers */ + Uart *pUartHw; + /** Current Uart Rx channel */ + UartChannel *pRxChannel; + /** Current Uart Tx channel */ + UartChannel *pTxChannel; +} UartDma; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t UARTD_Configure(UartDma *pUartd , + uint8_t uartId, + uint32_t uartMode, + uint32_t baud, + uint32_t clk); + +uint32_t UARTD_EnableTxChannels(UartDma *pUartd, UartChannel *pTxCh); + +uint32_t UARTD_EnableRxChannels(UartDma *pUartd, UartChannel *pRxCh); + +uint32_t UARTD_DisableTxChannels(UartDma *pUartd, UartChannel *pTxCh); + +uint32_t UARTD_DisableRxChannels(UartDma *pUartd, UartChannel *pRxCh); + +uint32_t UARTD_SendData(UartDma *pUartd); + +uint32_t UARTD_RcvData(UartDma *pUartd); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _UART_DMA_ */ diff --git a/bsps/arm/atsam/include/libchip/include/usart.h b/bsps/arm/atsam/include/libchip/include/usart.h new file mode 100644 index 0000000000..a1d1c378af --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/usart.h @@ -0,0 +1,164 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \par Purpose + * + * This module provides several definitions and methods for using an USART + * peripheral. + * + * \par Usage + * + * -# Enable the USART peripheral clock in the PMC. + * -# Enable the required USART PIOs (see pio.h). + * -# Configure the UART by calling USART_Configure. + * -# Enable the transmitter and/or the receiver of the USART using + * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. + * -# Send data through the USART using the USART_Write methods. + * -# Receive data from the USART using the USART_Read functions; the + * availability of data can be polled + * with USART_IsDataAvailable. + * -# Disable the transmitter and/or the receiver of the USART with + * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. + */ + +#ifndef _USART_ +#define _USART_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ + +/** \section USART_mode USART modes + * This section lists several common operating modes for an USART peripheral. + * + * \b Modes + * - USART_MODE_ASYNCHRONOUS + * - USART_MODE_IRDA + */ + +/** Basic asynchronous mode, i.e. 8 bits no parity.*/ +#define USART_MODE_ASYNCHRONOUS (US_MR_CHRL_8_BIT | US_MR_PAR_NO) + +#define MAX_RX_TIMEOUT 131071 + +/** IRDA mode*/ +#define USART_MODE_IRDA \ + (US_MR_USART_MODE_IRDA | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_FILTER) + +/** SPI mode*/ +#define AT91C_US_USMODE_SPIM 0xE +#define US_SPI_CPOL_0 (0x0<<16) +#define US_SPI_CPHA_0 (0x0<<8) +#define US_SPI_CPOL_1 (0x1<<16) +#define US_SPI_CPHA_1 (0x1<<8) +#define US_SPI_BPMODE_0 (US_SPI_CPOL_0|US_SPI_CPHA_1) +#define US_SPI_BPMODE_1 (US_SPI_CPOL_0|US_SPI_CPHA_0) +#define US_SPI_BPMODE_2 (US_SPI_CPOL_1|US_SPI_CPHA_1) +#define US_SPI_BPMODE_3 (US_SPI_CPOL_1|US_SPI_CPHA_0) + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Exported functions */ +/*------------------------------------------------------------------------------*/ + + +void USART_Configure(Usart *pUsart, uint32_t mode, uint32_t baudrate, + uint32_t masterClock); + +void USART_SetBaudrate(Usart *pUsart, uint8_t OverSamp, uint32_t baudrate, + uint32_t masterClock); + +uint32_t USART_GetStatus(Usart *usart); + + +void USART_ResetRx(Usart *pUsart); + +void USART_ResetTx(Usart *pUsart); + +void USART_EnableTx(Usart *pUsart); + +void USART_EnableRx(Usart *pUsart); + +void USART_DisableRx(Usart *pUsart); + +void USART_DisableTx(Usart *pUsart); + +void USART_EnableIt(Usart *usart, uint32_t mode); + +void USART_DisableIt(Usart *usart, uint32_t mode); + +uint32_t USART_GetItMask(Usart *usart); + +void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled); + +void USART_SetReceiverEnabled(Usart *usart, uint8_t enabled); + +void USART_SetRTSEnabled(Usart *usart, uint8_t enabled); + +void USART_Write(Usart *usart, uint16_t data, volatile uint32_t timeOut); + +uint16_t USART_Read(Usart *usart, volatile uint32_t timeOut); + +uint8_t USART_IsDataAvailable(Usart *usart); + +void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter); + +void USART_PutChar(Usart *usart, uint8_t c); + +uint32_t USART_IsRxReady(Usart *usart); + +uint8_t USART_GetChar(Usart *usart); + +void USART_EnableRecvTimeOut(Usart *usart, uint32_t timeout); + +void USART_EnableTxTimeGaurd(Usart *pUsart, uint32_t TimeGaurd); + +void USART_AcknowledgeRxTimeOut(Usart *usart, uint8_t Periodic); + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _USART_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/usart_dma.h b/bsps/arm/atsam/include/libchip/include/usart_dma.h new file mode 100644 index 0000000000..0329cd1818 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/usart_dma.h @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Implementation of USART driver, transfer data through DMA. + * + */ + +#ifndef _USART_DMA_H_ +#define _USART_DMA_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define USARTD_ERROR 1 + +/** USART driver is currently in use.*/ +#define USARTD_ERROR_LOCK 2 + + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** USART transfer complete callback. */ +typedef void (*UsartdCallback)(uint8_t, void *); + +/** \brief usart Transfer Request prepared by the application upper layer. + * + * This structure is sent to the USART_Send or USART_Rcv to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct { + /** Pointer to the Buffer. */ + uint8_t *pBuff; + /** Buff size in bytes. */ + uint32_t BuffSize; + /** Dma channel num. */ + uint8_t ChNum; + /** Callback function invoked at the end of transfer. */ + UsartdCallback callback; + /** Callback arguments. */ + void *pArgument; + /** flag to indicate the current transfer progress */ + volatile uint8_t dmaProgress; + /* DMA LLI structure */ + LinkedListDescriporView1 *pLLIview; + /* DMA transfer type */ + eXdmadProgState dmaProgrammingMode; + /* DMA LLI size or num of micro block*/ + uint16_t dmaBlockSize; + /* Flag using ring buffer or FiFo*/ + uint8_t dmaRingBuffer; +} UsartChannel; + +/** Constant structure associated with USART port. This structure prevents + client applications to have access in the same time. */ +typedef struct { + /** USART Id as defined in the product datasheet */ + uint8_t usartId; + /** Pointer to USART Hardware registers */ + Usart *pUsartHw; + /** Current Usart Rx channel */ + UsartChannel *pRxChannel; + /** Current Usart Tx channel */ + UsartChannel *pTxChannel; + /** Pointer to DMA driver */ + sXdmad *pXdmad; +} UsartDma; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t USARTD_Configure(UsartDma *pUsartd , + uint8_t USARTId, + uint32_t UsartMode, + uint32_t BaudRate, + uint32_t UsartClk); + +uint32_t USARTD_EnableTxChannels(UsartDma *pUsartd, UsartChannel *pTxCh); + +uint32_t USARTD_EnableRxChannels(UsartDma *pUsartd, UsartChannel *pRxCh); + +uint32_t USARTD_DisableTxChannels(UsartDma *pUsartd, UsartChannel *pTxCh); + +uint32_t USARTD_DisableRxChannels(UsartDma *pUsartd, UsartChannel *pTxCh); + +uint32_t USARTD_SendData(UsartDma *pUsartd); + +uint32_t USARTD_RcvData(UsartDma *pUsartd); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _USART_DMA_ */ diff --git a/bsps/arm/atsam/include/libchip/include/usbhs.h b/bsps/arm/atsam/include/libchip/include/usbhs.h new file mode 100644 index 0000000000..e30e15b313 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/usbhs.h @@ -0,0 +1,1699 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +#ifndef USBHS_H +#define USBHS_H +/** addtogroup usbd_hal + *@{ + */ + +#define USB_DEVICE_HS_SUPPORT + +//! Control endpoint size +#define USB_DEVICE_EP_CTRL_SIZE 64 + +/** Indicates chip has an UDP High Speed. */ +#define CHIP_USB_UDP + +/** Indicates chip has an internal pull-up. */ +#define CHIP_USB_PULLUP_INTERNAL + +/** Number of USB endpoints */ +#define CHIP_USB_NUMENDPOINTS 10 + +/** Endpoints max packet size */ +#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(ep) \ + ((ep == 0) ? 64 : 1024) + +/** Endpoints Number of Bank */ +#define CHIP_USB_ENDPOINTS_BANKS(ep) ((ep==0)?1:((ep<=2)?3:2)) + + +#define CHIP_USB_ENDPOINTS_HBW(ep) ((((ep)>=1) &&((ep)<=2))?true:false) + +/** Endpoints DMA support */ +#define CHIP_USB_ENDPOINTS_DMA(ep) ((((ep)>=1)&&((ep)<=7))?true:false) + +/** Max size of the FMA FIFO */ +#define DMA_MAX_FIFO_SIZE (65536/1) +/** fifo space size in DW */ +#define EPT_VIRTUAL_SIZE 8192 + + +//! @name USBHS Host IP properties +//! +//! @{ +//! Get maximal number of endpoints +#define uhd_get_pipe_max_nbr() (9) +#define USBHS_EPT_NUM (uhd_get_pipe_max_nbr()+1) +//! Get maximal number of banks of endpoints +#define uhd_get_pipe_bank_max_nbr(ep) ((ep == 0) ? 1 : ((ep <= 2) ? 3 : 2)) +//! Get maximal size of endpoint (3X, 1024/64) +#define uhd_get_pipe_size_max(ep) (((ep) == 0) ? 64 : 1024) +//! Get DMA support of endpoints +#define Is_uhd_pipe_dma_supported(ep) ((((ep) >= 1) && ((ep) <= 7)) ? true : false) +//! Get High Band Width support of endpoints +#define Is_uhd_pipe_high_bw_supported(ep) (((ep) >= 2) ? true : false) +//! @} + +typedef enum { + HOST_MODE = 0, + DEVICE_MODE = 1 +} USB_Mode_t; + +//! Maximum transfer size on USB DMA +#define UHD_PIPE_MAX_TRANS 0x8000 + +/** +================================= + USBHS_CTRL +================================= +**/ + +/** + * \brief Freeze or unfreeze USB clock + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ +__STATIC_INLINE void USBHS_FreezeClock(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_CTRL |= USBHS_CTRL_FRZCLK; +} + +/** + * \brief Freeze or unfreeze USB clock + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ +__STATIC_INLINE void USBHS_UnFreezeClock(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_FRZCLK); +} +/** + * \brief Freeze or unfreeze USB clock + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ +__STATIC_INLINE void USBHS_VBusHWC(Usbhs *pUsbhs, uint8_t Enable) +{ + + if (!Enable) + pUsbhs->USBHS_CTRL |= (1 << 8); + else + pUsbhs->USBHS_CTRL &= ~((uint32_t)(1 << 8)); +} + +/** + * \brief Enables or disables USB + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ + +__STATIC_INLINE void USBHS_UsbEnable(Usbhs *pUsbhs, uint8_t Enable) +{ + if (Enable) + pUsbhs->USBHS_CTRL |= USBHS_CTRL_USBE; + else + pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_USBE); +} + + +/** + * \brief Device or Host Mode + * \param pUsbhs Pointer to an USBHS instance. + * \param Mode Device or Host Mode + */ + +__STATIC_INLINE void USBHS_UsbMode(Usbhs *pUsbhs, USB_Mode_t Mode) +{ + if (Mode) + pUsbhs->USBHS_CTRL |= USBHS_CTRL_UIMOD_DEVICE; + else + pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_UIMOD_DEVICE); +} + +/********************* USBHS_SR *****************/ + +/** + * \brief Check if clock is usable or not + * \param pUsbhs Pointer to an USBHS instance. + * \return 1 if USB clock is usable + */ + +__STATIC_INLINE uint8_t USBHS_ISUsableClock(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_SR & USBHS_SR_CLKUSABLE) >> 14); +} + + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \return USB status + */ + +__STATIC_INLINE uint32_t USBHS_ReadStatus(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_SR); +} + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE uint32_t USBHS_GetUsbSpeed(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk)); +} + + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE bool USBHS_IsUsbFullSpeed(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_FULL_SPEED) ? + true : false; +} + + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE bool USBHS_IsUsbHighSpeed(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_HIGH_SPEED) ? + true : false; +} + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE bool USBHS_IsUsbLowSpeed(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_LOW_SPEED) ? + true : false; +} +/********************* USBHS_SCR *****************/ + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param AckType Interrupt Acknowledge type + */ + +__STATIC_INLINE void USBHS_Ack(Usbhs *pUsbhs, uint32_t AckType) +{ + pUsbhs->USBHS_SCR |= AckType; +} + +/********************* USBHS_SFR *****************/ + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param SetStatus Set USB status + */ + +__STATIC_INLINE void USBHS_Set(Usbhs *pUsbhs, uint32_t SetStatus) +{ + pUsbhs->USBHS_SFR |= SetStatus; +} + + +/*-------------------------------------------------------- +* =========== USB Device functions ====================== +*---------------------------------------------------------*/ + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \param SetStatus Set USB status + */ + +__STATIC_INLINE void USBHS_EnableAddress(Usbhs *pUsbhs, uint8_t Enable) +{ + if (Enable) + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN; + else + pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_ADDEN); +} + +/** + * \brief Configure USB address and enable or disable it + * \param pUsbhs Pointer to an USBHS instance. + * \param Addr USB device status + */ + +__STATIC_INLINE void USBHS_SetAddress(Usbhs *pUsbhs, uint8_t Addr) +{ + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(Addr); + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN; +} + +/** + * \brief Get USB address + * \param pUsbhs Pointer to an USBHS instance. + */ + +__STATIC_INLINE uint8_t USBHS_GetAddress(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_DEVCTRL & USBHS_DEVCTRL_UADD_Msk); +} + +/** + * \brief Attach or detach USB. + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Attachs or detach USB device + */ + +__STATIC_INLINE void USBHS_DetachUsb(Usbhs *pUsbhs, uint8_t Enable) +{ + if (Enable) + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH; + else + pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_DETACH); + +} + +/** + * \brief Force Low Speed mode + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enables the Full speed + */ + +__STATIC_INLINE void USBHS_ForceLowSpeed(Usbhs *pUsbhs, uint8_t Enable) +{ + if (Enable) + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_LS; + else + pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_LS); +} + +/** + * \brief Disable/Enables High Speed mode + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enables/disable option + */ + +__STATIC_INLINE void USBHS_EnableHighSpeed(Usbhs *pUsbhs, uint8_t Enable) +{ + uint32_t cfg = pUsbhs->USBHS_DEVCTRL; + cfg &= ~((uint32_t)USBHS_DEVCTRL_SPDCONF_Msk); + + if (Enable) + pUsbhs->USBHS_DEVCTRL |= cfg; + else + pUsbhs->USBHS_DEVCTRL |= (cfg | USBHS_DEVCTRL_SPDCONF_FORCED_FS); + +} + +/** + * \brief Set Remote WakeUp mode + * \param pUsbhs Pointer to an USBHS instance. + */ + +__STATIC_INLINE void USBHS_SetRemoteWakeUp(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP; +} + +/** + * \brief Disable/Enables Test mode + * \param pUsbhs Pointer to an USBHS instance. + * \param mode Enables/disable option + */ + +__STATIC_INLINE void USBHS_EnableTestMode(Usbhs *pUsbhs, uint32_t mode) +{ + pUsbhs->USBHS_DEVCTRL |= mode; +} + + +/** + * \brief Disable/Enables HS Test mode + * \param pUsbhs Pointer to an USBHS instance. + */ + +__STATIC_INLINE void USBHS_EnableHSTestMode(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF_HIGH_SPEED; +} + +/** + * \brief Read status for an interrupt + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt type + */ + +__STATIC_INLINE uint32_t USBHS_ReadIntStatus(Usbhs *pUsbhs, uint32_t IntType) +{ + return (pUsbhs->USBHS_DEVISR & IntType); +} + +/** + * \brief Read status for an Endpoint + * \param pUsbhs Pointer to an USBHS instance. + * \param EpNum Endpoint + */ + +__STATIC_INLINE uint32_t USBHS_ReadEpIntStatus(Usbhs *pUsbhs, uint8_t EpNum) +{ + return (pUsbhs->USBHS_DEVISR & (USBHS_DEVISR_PEP_0 << EpNum)); +} + +/** + * \brief Read status for a DMA Endpoint + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaNum DMA Endpoint + */ +__STATIC_INLINE uint32_t USBHS_ReadDmaIntStatus(Usbhs *pUsbhs, uint8_t DmaNum) +{ + return (pUsbhs->USBHS_DEVISR & (USBHS_DEVISR_DMA_1 << DmaNum)); +} + +/** + * \brief Acknowledge interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ + +__STATIC_INLINE void USBHS_AckInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVICR |= IntType; +} + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ + + +__STATIC_INLINE void USBHS_RaiseInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVIFR |= IntType; +} + +/** + * \brief Raise DMA interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ +__STATIC_INLINE void USBHS_RaiseDmaInt(Usbhs *pUsbhs, uint8_t Dma) +{ + assert(Dma < USBHSDEVDMA_NUMBER); + pUsbhs->USBHS_DEVIFR |= (USBHS_DEVIFR_DMA_1 << Dma); +} + +/** + * \brief check for interrupt of endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ + +__STATIC_INLINE uint32_t USBHS_IsIntEnable(Usbhs *pUsbhs, uint32_t IntType) +{ + return (pUsbhs->USBHS_DEVIMR & IntType); +} + +/** + * \brief Check if endpoint's interrupt is enabled for a given endpoint number + * \param pUsbhs Pointer to an USBHS instance. + * \param EpNum Endpoint number + */ + +__STATIC_INLINE uint32_t USBHS_IsIntEnableEP(Usbhs *pUsbhs, uint8_t EpNum) +{ + return (pUsbhs->USBHS_DEVIMR & (USBHS_DEVIMR_PEP_0 << EpNum)); +} + + +/** + * \brief Check if endpoint's DMA interrupt is enabled for a given endpoint + * DMA number + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaNum Endpoint's DMA number + */ + +__STATIC_INLINE uint32_t USBHS_IsDmaIntEnable(Usbhs *pUsbhs, uint8_t DmaNum) +{ + return (pUsbhs->USBHS_DEVIMR & (USBHS_DEVIMR_DMA_1 << DmaNum)); +} + + +/** + * \brief Enables Interrupt + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ +__STATIC_INLINE void USBHS_EnableInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVIER |= IntType; +} + +/** + * \brief Enables interrupt for a given endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaNum Endpoint's DMA number + */ +__STATIC_INLINE void USBHS_EnableIntEP(Usbhs *pUsbhs, uint8_t EpNum) +{ + pUsbhs->USBHS_DEVIER |= (USBHS_DEVIER_PEP_0 << EpNum); +} + +/** + * \brief Enables DMA interrupt for a given endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaEp Endpoint's DMA interrupt number + */ + +__STATIC_INLINE void USBHS_EnableDMAIntEP(Usbhs *pUsbhs, uint32_t DmaEp) +{ + assert(DmaEp < USBHSDEVDMA_NUMBER); + pUsbhs->USBHS_DEVIER |= (USBHS_DEVIER_DMA_1 << DmaEp); +} + +/** +* \brief Disables interrupt for endpoint. +* \param pUsbhs Pointer to an USBHS instance. +* \param IntType Int type +*/ + +__STATIC_INLINE void USBHS_DisableInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVIDR |= IntType; +} + +/** +* \brief Disables interrupt for endpoint. +* \param pUsbhs Pointer to an USBHS instance. +* \param Ep Endpoint number +*/ + +__STATIC_INLINE void USBHS_DisableIntEP(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVIDR |= (USBHS_DEVIDR_PEP_0 << Ep); +} + +/** +* \brief Disables DMA interrupt for endpoint. +* \param pUsbhs Pointer to an USBHS instance. +* \param DmaEp Endpoint's DMA number +*/ +__STATIC_INLINE void USBHS_DisableDMAIntEP(Usbhs *pUsbhs, uint8_t DmaEp) +{ + assert(DmaEp < USBHSDEVDMA_NUMBER); + pUsbhs->USBHS_DEVIDR |= (USBHS_DEVIDR_DMA_1 << DmaEp); +} + + +/** +* \brief Enables or disables endpoint. +* \param pUsbhs Pointer to an USBHS instance. +* \param Enable Enable/disable endpoint +*/ + +__STATIC_INLINE void USBHS_EnableEP(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable) +{ + if (Enable) + pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPEN0 << Ep); + else + pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPEN0 << Ep); + +} + + +/** +* \brief Rests Endpoint +* \param pUsbhs Pointer to an USBHS instance. +* \param Ep Endpoint Number +*/ + +__STATIC_INLINE void USBHS_ResetEP(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPRST0 << Ep); + pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPRST0 << Ep); +} + +/** +* \brief Checks if Endpoint is enable +* \param pUsbhs Pointer to an USBHS instance. +* \param Ep Endpoint Number +*/ + +__STATIC_INLINE uint32_t USBHS_IsEPEnabled(Usbhs *pUsbhs, uint8_t Ep) +{ + return (pUsbhs->USBHS_DEVEPT & (USBHS_DEVEPT_EPEN0 << Ep)); +} + +/** +* \brief Get MicrFrame number +* \param pUsbhs Pointer to an USBHS instance. +* \retruns Micro frame number +*/ +__STATIC_INLINE uint8_t USBHS_GetMicroFrameNum(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_MFNUM_Msk); +} + + +/** +* \brief Get Frame number +* \param pUsbhs Pointer to an USBHS instance. +* \retruns frame number +*/ +__STATIC_INLINE uint8_t USBHS_GetFrameNum(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNUM_Msk) + >> USBHS_DEVFNUM_FNUM_Pos); +} + +/** +* \brief Get Frame number CRC error +* \param pUsbhs Pointer to an USBHS instance. +* \retruns Frame number error status +*/ +__STATIC_INLINE uint8_t USBHS_GetFrameNumCrcErr(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNCERR) >> 15); +} + +/*----------------------------------------- +* =========== USB Device's Endpoint functions ======== +*------------------------------------------*/ + +/** + * Set Endpoints configuration + * Bank size, type and direction + */ +__STATIC_INLINE void USBHS_ConfigureEPs(Usbhs *pUsbhs, const uint8_t Ep, + const uint8_t Type, const uint8_t Dir, + const uint8_t Size, const uint8_t Bank) +{ + + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + ((Size << USBHS_DEVEPTCFG_EPSIZE_Pos) & USBHS_DEVEPTCFG_EPSIZE_Msk); + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + ((Dir << 8) & USBHS_DEVEPTCFG_EPDIR); + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + (((Type) << USBHS_DEVEPTCFG_EPTYPE_Pos) & USBHS_DEVEPTCFG_EPTYPE_Msk); + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + (((Bank) << USBHS_DEVEPTCFG_EPBK_Pos) & USBHS_DEVEPTCFG_EPBK_Msk); +} + + +/** + * Enable or disable Auto switch of banks + */ +__STATIC_INLINE void USBHS_AutoSwitchBankEnable(Usbhs *pUsbhs, uint8_t Ep, + uint8_t Enable) +{ + if (Enable) + pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_AUTOSW; + else + pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_AUTOSW); +} + + +/** + * Allocate Endpoint memory + */ +__STATIC_INLINE void USBHS_AllocateMemory(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_ALLOC; +} + + +/** + * Free allocated Endpoint memory + */ +__STATIC_INLINE void USBHS_FreeMemory(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_ALLOC); +} + + +/** + * Get Endpoint configuration + */ +__STATIC_INLINE uint32_t USBHS_GetConfigureEPs(Usbhs *pUsbhs, uint8_t Ep, + uint32_t IntType) +{ + return ((pUsbhs->USBHS_DEVEPTCFG[Ep]) & IntType); +} + +/** + * Get Endpoint Type + */ +__STATIC_INLINE uint8_t USBHS_GetEpType(Usbhs *pUsbhs, uint8_t Ep) +{ + return ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPTYPE_Msk) + >> USBHS_DEVEPTCFG_EPTYPE_Pos); +} + +/** + * Get Endpoint Size + */ +__STATIC_INLINE uint32_t USBHS_GetEpSize(Usbhs *pUsbhs, uint8_t Ep) +{ + return (8 << ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPSIZE_Msk) + >> USBHS_DEVEPTCFG_EPSIZE_Pos)); +} + + +/** + * Sets ISO endpoint's Number of Transfer for High Speed + */ +__STATIC_INLINE void USBHS_SetIsoTrans(Usbhs *pUsbhs, uint8_t Ep, + uint8_t nbTrans) +{ + pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_NBTRANS(nbTrans); +} + +/** + * Check for interrupt types enabled for a given endpoint + */ +__STATIC_INLINE uint32_t USBHS_IsEpIntEnable(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpIntType) +{ + return (pUsbhs->USBHS_DEVEPTIMR[Ep] & EpIntType); +} + + +/** + * Enables an interrupt type for a given endpoint + */ +__STATIC_INLINE void USBHS_EnableEPIntType(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTIER[Ep] |= EpInt; +} + +/** + * Enables an interrupt type for a given endpoint + */ +__STATIC_INLINE uint32_t USBHS_IsBankKilled(Usbhs *pUsbhs, uint8_t Ep) +{ + return (pUsbhs->USBHS_DEVEPTIMR[Ep] & USBHS_DEVEPTIMR_KILLBK); +} + +/** + * Enables an interrupt type for a given endpoint + */ +__STATIC_INLINE void USBHS_KillBank(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPTIER[Ep] = USBHS_DEVEPTIER_KILLBKS; +} +/** + * Disables an interrupt type for a given endpoint + */ +__STATIC_INLINE void USBHS_DisableEPIntType(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTIDR[Ep] |= EpInt; +} + +/** + * Clears register/acknowledge for a given endpoint + */ +__STATIC_INLINE void USBHS_AckEpInterrupt(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTICR[Ep] |= EpInt; +} + +/** + * Sets/Raise register for a given endpoint + */ +__STATIC_INLINE void USBHS_RaiseEPInt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTIFR[Ep] |= EpInt; +} + +/** + * Gets interrupt status for a given EP + */ +__STATIC_INLINE uint32_t USBHS_ReadEPStatus(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + return (pUsbhs->USBHS_DEVEPTISR[Ep] & EpInt); +} + +/** + * Check if given endpoint's bank is free + */ +__STATIC_INLINE uint8_t USBHS_IsBankFree(Usbhs *pUsbhs, uint8_t Ep) +{ + if ((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk)) + return false; + else + return true; +} + +/** + * Read endpoint's bank number in use + */ +__STATIC_INLINE uint8_t USBHS_NumOfBanksInUse(Usbhs *pUsbhs, uint8_t Ep) +{ + return ((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk) + >> USBHS_DEVEPTISR_NBUSYBK_Pos); +} + + +/** + * Read endpoint's byte count of the FIFO + */ +__STATIC_INLINE uint16_t USBHS_ByteCount(Usbhs *pUsbhs, uint8_t Ep) +{ + return (uint16_t)((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_BYCT_Msk) + >> USBHS_DEVEPTISR_BYCT_Pos); +} + +/*-------------------------------------------------------- +* =========== USB Device's Ep's DMA functions ========= +*---------------------------------------------------------*/ + +/** +* \brief Sets DMA next descriptor address +* \param pUsbDma USBHS device DMA instance +* \param Desc NDA address +*/ +__STATIC_INLINE void USBHS_SetDmaNDA(UsbhsDevdma *pUsbDma, uint32_t Desc) +{ + pUsbDma->USBHS_DEVDMANXTDSC = Desc; +} + +/** +* \brief Gets DMA next descriptor address +* \param pUsbDma USBHS device DMA instance +* \return Next DMA descriptor +*/ +__STATIC_INLINE uint32_t USBHS_GetDmaNDA(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMANXTDSC); +} + +/** +* \brief Sets USBHS's DMA Buffer addresse +* \param pUsbDma USBHS device DMA instance +* \param Addr DMA's buffer Addrs +*/ +__STATIC_INLINE void USBHS_SetDmaBuffAdd(UsbhsDevdma *pUsbDma, uint32_t Addr) +{ + pUsbDma->USBHS_DEVDMAADDRESS = Addr; +} + + +/** +* \brief Gets USBHS's DMA Buffer addresse +* \param pUsbDma USBHS device DMA instance +* \return DMA addrs +*/ +__STATIC_INLINE uint32_t USBHS_GetDmaBuffAdd(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMAADDRESS); +} + +/** +* \brief Setup the USBHS DMA +* \param pUsbDma USBHS device DMA instance +* \param Cfg DMA's configuration +*/ +__STATIC_INLINE void USBHS_ConfigureDma(UsbhsDevdma *pUsbDma, uint32_t Cfg) +{ + pUsbDma->USBHS_DEVDMACONTROL |= Cfg; +} + +/** +* \brief Get DMA configuration +* \param pUsbDma USBHS device DMA instance +* \return DMA control setup +*/ +__STATIC_INLINE uint32_t USBHS_GetDmaConfiguration(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMACONTROL); +} + + +/** +* \brief Set DMA status +* \param pUsbDma USBHS device DMA instance +* \Status Set DMA status +*/ +__STATIC_INLINE void USBHS_SetDmaStatus(UsbhsDevdma *pUsbDma, uint32_t Status) +{ + pUsbDma->USBHS_DEVDMASTATUS = Status; +} + + +/** +* \brief Get Dma Status +* \param pUsbDma USBHS device DMA instance +* \return Dma status +*/ +__STATIC_INLINE uint32_t USBHS_GetDmaStatus(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMASTATUS); +} + + +/** +* \brief Get DMA buffer's count +* \param pUsbDma USBHS device DMA instance +* \return Buffer count +*/ +__STATIC_INLINE uint16_t USBHS_GetDmaBuffCount(UsbhsDevdma *pUsbDma) +{ + return ((pUsbDma->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) + >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos); +} + + +/*-------------------------------------------------------- +* =========== USB Host Functions ======================== +*---------------------------------------------------------*/ + +/** Number of USB endpoints */ +#define CHIP_USB_NUMPIPE 10 +/** Number of USB endpoints */ +#define CHIP_USB_DMA_NUMPIPE 7 + +/** Endpoints max paxcket size */ +#define CHIP_USB_PIPE_MAXPACKETSIZE(ep) \ + ((ep == 0) ? 64 : 1024) + +/** Endpoints Number of Bank */ +#define CHIP_USB_PIPE_BANKS(ep) ((ep==0)?1:((ep<=2)?3:2)) + + +#define CHIP_USB_PIPE_HBW(ep) ((((ep)>=1) &&((ep)<=2))?true:false) + +/** Endpoints DMA support */ +#define CHIP_USB_PIPE_DMA(ep) ((((ep)>=1)&&((ep)<=7))?true:false) + +/** +* \brief Sets USB host's speed to Normal , it sets to HS from FS +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_SetHostHighSpeed(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk; + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_NORMAL; +} + +/** +* \brief Sets USB host's speed to Low speed +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_SetHostLowSpeed(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk; + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_LOW_POWER; +} + +/** +* \brief Sets USB host's speed to forced Full speed +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_SetHostForcedFullSpeed(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk; + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_FORCED_FS; +} + +/** +* \brief Sets USB host sends reste signal on USB Bus +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_Reset(void) +{ + USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESET; +} + +/** +* \brief Sets USB host sends reste signal on USB Bus +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_StopReset(void) +{ + USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_RESET; +} + +/** +* \brief Sets USB host send Resume on USB bus +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_Resume(void) +{ + USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESUME; +} + +/** +* \brief Sets USB host Enable the Generation of Start of Frame +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_EnableSOF(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SOFE; +} + +/** +* \brief Sets USB host Enable the Generation of Start of Frame +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE uint8_t USBHS_IsEnableSOF(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_HSTCTRL & USBHS_HSTCTRL_SOFE) >> 8; +} +/** +* \brief Sets USB host disable the Generation of Start of Frame +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_DisableSOF(void) +{ + USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SOFE; +} + +/** +* \brief Gets USB host interrupt status +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE uint32_t USBHS_GetHostStatus(Usbhs *pUsbhs, uint8_t IntType) +{ + return (pUsbhs->USBHS_HSTISR & IntType); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_GetHostPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert(PipeInt < CHIP_USB_NUMPIPE); + return (pUsbhs->USBHS_HSTISR & (USBHS_HSTISR_PEP_0 << PipeInt)); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_GetHostDmaPipeStatus(Usbhs *pUsbhs, + uint8_t PipeInt) +{ + assert(PipeInt); + assert(PipeInt < CHIP_USB_DMA_NUMPIPE); + return (pUsbhs->USBHS_HSTISR & (USBHS_HSTISR_DMA_1 << PipeInt)); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_ClearHostStatus(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTICR = IntType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostStatus(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTIFR = IntType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostDmaStatus(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert(PipeInt); + assert(PipeInt < CHIP_USB_DMA_NUMPIPE); + pUsbhs->USBHS_HSTIFR = (USBHS_HSTIFR_DMA_1 << PipeInt); +} + +/*** Interrupt Mask ****/ +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_IsHostIntEnable(Usbhs *pUsbhs, uint8_t IntType) +{ + return (pUsbhs->USBHS_HSTIMR & IntType); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostPipeIntEnable(Usbhs *pUsbhs, + uint8_t PipeInt) +{ + assert(PipeInt < CHIP_USB_NUMPIPE); + return (pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_PEP_0 << PipeInt)); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostDmaIntEnable(Usbhs *pUsbhs, + uint8_t PipeInt) +{ + assert(PipeInt); + assert(PipeInt < CHIP_USB_DMA_NUMPIPE); + return (pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_DMA_1 << PipeInt)); +} + +/*** Interrupt Disable ****/ +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostIntDisable(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTIDR = IntType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeIntDisable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert(PipeInt < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_PEP_0 << PipeInt); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDmaIntDisable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert(PipeInt); + assert(PipeInt < CHIP_USB_DMA_NUMPIPE); + pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_DMA_1 << PipeInt); +} + +/*** Interrupt Enable ****/ + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostIntEnable(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTIER = IntType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert(PipeInt < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTIER = (USBHS_HSTIER_PEP_0 << PipeInt); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert(PipeInt < CHIP_USB_DMA_NUMPIPE); + pUsbhs->USBHS_HSTIER |= (USBHS_HSTIER_DMA_1 << PipeInt); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetSOF(void) +{ + return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FNUM_Msk) >> + USBHS_HSTFNUM_FNUM_Pos); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetFramePos(void) +{ + return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FLENHIGH_Msk) >> + USBHS_HSTFNUM_FLENHIGH_Pos); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetMSOF(void) +{ + return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_MFNUM_Msk) >> + USBHS_HSTFNUM_MFNUM_Pos); +} + +__STATIC_INLINE void USBHS_HostSetAddr(Usbhs *pUsbhs, uint8_t Pipe, + uint8_t Addr) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + + if (Pipe < 4) + pUsbhs->USBHS_HSTADDR1 |= (Addr << (8 * Pipe)); + else if ((Pipe < 8) && (Pipe >= 4)) + pUsbhs->USBHS_HSTADDR2 |= (Addr << (8 * (Pipe - 4))); + else + pUsbhs->USBHS_HSTADDR3 |= (Addr << (8 * (Pipe - 8))); + +} + +__STATIC_INLINE uint8_t USBHS_HostGetAddr(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + + if (Pipe < 4) + return (pUsbhs->USBHS_HSTADDR1 >> (8 * Pipe)); + else if ((Pipe < 8) && (Pipe >= 4)) + return (pUsbhs->USBHS_HSTADDR2 >> (8 * (Pipe - 4))); + else + return (pUsbhs->USBHS_HSTADDR3 >> (8 * (Pipe - 8))); + +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PEN0 << Pipe); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeDisable(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PEN0 << Pipe); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + return (pUsbhs->USBHS_HSTPIP & (USBHS_HSTPIP_PEN0 << Pipe)); +} +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeReset(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PRST0 << Pipe); + pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PRST0 << Pipe); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostConfigure(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t pipeBank, uint8_t pipeSize, uint32_t pipeType, uint32_t pipeToken, + uint8_t pipeEpNum, uint8_t PipeIntFreq) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= (pipeBank | pipeToken | USBHS_HSTPIPCFG_PSIZE( + pipeSize) | pipeType | USBHS_HSTPIPCFG_PEPNUM(pipeEpNum) | + USBHS_HSTPIPCFG_INTFRQ(PipeIntFreq)); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostAllocMem(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_ALLOC; + +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostFreeMem(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_ALLOC; + +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetSize(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (8 << ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PSIZE_Msk) >> + USBHS_HSTPIPCFG_PSIZE_Pos)); + +} + +/** +* \brief Gets USB host interrupt status +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_HostSetToken(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t Token) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTOKEN_Msk; + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= Token; + +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_HostGetToken(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTOKEN_Msk); + +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetPipeType(Usbhs *pUsbhs, uint8_t Pipe, + uint8_t PipeType) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTYPE_Msk; + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= PipeType; + +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_HostGetPipeType(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTYPE_Msk); + +} + +__STATIC_INLINE uint8_t USBHS_GetPipeEpAddr(Usbhs *pUsbhs, uint8_t Pipe) +{ + + if (USBHS_HostGetToken(USBHS, Pipe) == USBHS_HSTPIPCFG_PTOKEN_IN) + return (((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >> + USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x80); + else + return (((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >> + USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x00); +} + + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnableAutoSw(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_AUTOSW; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDisableAutoSw(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_AUTOSW; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetIntFreq(Usbhs *pUsbhs, uint8_t Pipe, + uint8_t Freq) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_BINTERVAL(Freq); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnablePing(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_PINGEN; +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetDataTogSeq(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_DTSEQ_Msk) >> + USBHS_HSTPIPISR_DTSEQ_Pos); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetNumOfBusyBank(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_NBUSYBK_Msk) >> + USBHS_HSTPIPISR_NBUSYBK_Pos); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetCurrentBank(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_CURRBK_Msk) >> + USBHS_HSTPIPISR_CURRBK_Pos); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetPipeByteCount(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_PBYCT_Msk) >> + USBHS_HSTPIPISR_PBYCT_Pos); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostConfigOk(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_DEVEPTISR_CFGOK); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_HostGetIntTypeStatus(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t intType) +{ + return (pUsbhs->USBHS_HSTPIPISR[Pipe] & intType); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostAckPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPICR[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPIFR[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostPipeIntTypeEnable(Usbhs *pUsbhs, + uint8_t Pipe, uint32_t intType) +{ + return (pUsbhs->USBHS_HSTPIPIMR[Pipe] & intType); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDisablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPIDR[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPIER[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnableInReq(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPINRQ[Pipe] |= USBHS_HSTPIPINRQ_INMODE; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDisableInReq(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPINRQ[Pipe] &= ~USBHS_HSTPIPINRQ_INMODE; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_IsHostInReqEnable(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ((pUsbhs->USBHS_HSTPIPINRQ[Pipe] & USBHS_HSTPIPINRQ_INMODE) >> 8); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostInReq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t InReq) +{ + pUsbhs->USBHS_HSTPIPINRQ[Pipe] = USBHS_HSTPIPINRQ_INRQ(InReq - 1); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err) +{ + pUsbhs->USBHS_HSTPIPERR[Pipe] |= Err; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetErr(Usbhs *pUsbhs, uint8_t Pipe, + uint8_t Err) +{ + return (pUsbhs->USBHS_HSTPIPERR[Pipe] & Err); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostClearErr(Usbhs *pUsbhs, uint8_t Pipe, + uint8_t Err) +{ + pUsbhs->USBHS_HSTPIPERR[Pipe] = Err; +} + + +__STATIC_INLINE uint8_t USBHS_GetInterruptPipeNum(void) +{ + uint32_t status = USBHS->USBHS_HSTISR; + uint32_t mask = USBHS->USBHS_HSTIMR; + return ctz(((status & mask) >> 8) | (1 << USBHS_EPT_NUM)); +} + +static inline uint8_t USBHS_GetInterruptPipeDmaNum(void) +{ + uint32_t status = USBHS->USBHS_HSTISR; + uint32_t mask = USBHS->USBHS_HSTIMR; + return (ctz(((status & mask) >> 25) | (1 << (USBHS_EPT_NUM - 1))) + 1); +} +/*-------------------------------------------------------- +* =========== USB Host's pipe DMA functions ========= +*---------------------------------------------------------*/ + +/** +* \brief Sets DMA next descriptor address +* \param pUsbDma USBHS device DMA instance +* \param Desc NDA addrs +*/ +__STATIC_INLINE void USBHS_SetHostDmaNDA(UsbhsHstdma *pUsbDma, uint32_t Desc) +{ + pUsbDma->USBHS_HSTDMANXTDSC = Desc; +} + +/** +* \brief Gets DMA next descriptor address +* \param pUsbDma USBHS device DMA instance +* \return Next DMA descriptor +*/ +__STATIC_INLINE uint32_t USBHS_GetHostDmaNDA(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMANXTDSC); +} + +/** +* \brief Sets USBHS's DMA Buffer addresse +* \param pUsbDma USBHS device DMA instance +* \param Addr DMA's buffer Addrs +*/ +__STATIC_INLINE void USBHS_SetHostDmaBuffAdd(UsbhsHstdma *pUsbDma, + uint32_t Addr) +{ + pUsbDma->USBHS_HSTDMAADDRESS = Addr; +} + + +/** +* \brief Gets USBHS's DMA Buffer addresse +* \param pUsbDma USBHS device DMA instance +* \return DMA addrs +*/ +__STATIC_INLINE uint32_t USBHS_GetHostDmaBuffAdd(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMAADDRESS); +} + +/** +* \brief Setup the USBHS DMA +* \param pUsbDma USBHS device DMA instance +* \param Cfg DMA's configuration +*/ +__STATIC_INLINE void USBHS_HostConfigureDma(UsbhsHstdma *pUsbDma, uint32_t Cfg) +{ + pUsbDma->USBHS_HSTDMACONTROL |= Cfg; +} + +/** +* \brief Get DMA configuration +* \param pUsbDma USBHS device DMA instance +* \return DMA control setup +*/ +__STATIC_INLINE uint32_t USBHS_GetHostDmaConfiguration(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMACONTROL); +} + + +/** +* \brief Set DMA status +* \param pUsbDma USBHS device DMA instance +* \Status Set DMA status +*/ +__STATIC_INLINE void USBHS_SetHostPipeDmaStatus(UsbhsHstdma *pUsbDma, + uint32_t Status) +{ + pUsbDma->USBHS_HSTDMASTATUS = Status; +} + + +/** +* \brief Get Dma Status +* \param pUsbDma USBHS device DMA instance +* \return Dma status +*/ +__STATIC_INLINE uint32_t USBHS_GetHostPipeDmaStatus(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMASTATUS); +} + +/**@}*/ +#endif /* #ifndef USBHS_H */ diff --git a/bsps/arm/atsam/include/libchip/include/video.h b/bsps/arm/atsam/include/libchip/include/video.h new file mode 100644 index 0000000000..1ea18d214b --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/video.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _VIDEO_H +#define _VIDEO_H + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/** Type of video is YUV */ +#define YUV 0 +/** Type of video is RGB */ +#define RGB 1 + +/*---------------------------------------------------------------------------- + * Type + *----------------------------------------------------------------------------*/ +typedef struct _isi_Video { + /** LCD Vertical Size */ + uint32_t lcd_vsize; + /** LCD Horizontal Size*/ + uint32_t lcd_hsize; + /** LCD Number of Bit Per Pixel*/ + uint32_t lcd_nbpp; + /** LCD Frame Buffer Address*/ + uint32_t lcd_fb_addr; + /** Base address for the frame buffer descriptors list*/ + uint32_t Isi_fbd_base; + /** Start of Line Delay*/ + uint32_t Hblank; + /** Start of frame Delay */ + uint32_t Vblank; + /** Vertical size of the Image sensor [0..2047]*/ + uint32_t codec_vsize; + /** Horizontal size of the Image sensor [0..2047]*/ + uint32_t codec_hsize; + /** Base address for codec DMA*/ + uint32_t codec_fb_addr; + /** Base address for the frame buffer descriptors list*/ + uint32_t codec_fbd_base; + /** Buffer index */ + uint32_t IsiPrevBuffIndex; + /** Type of video */ + uint8_t rgb_or_yuv; +} isi_Video, *pIsi_Video; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void VIDEO_Ycc2Rgb(uint8_t *ycc, uint16_t *rgb, uint32_t len); + +#endif + diff --git a/bsps/arm/atsam/include/libchip/include/wdt.h b/bsps/arm/atsam/include/libchip/include/wdt.h new file mode 100644 index 0000000000..9d87ffa55f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/wdt.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * Interface for Watchdog Timer (WDT) controller. + * + * \section Usage + * -# Enable watchdog with given mode using \ref WDT_Enable(). + * -# Disable watchdog using \ref WDT_Disable() + * -# Restart the watchdog using \ref WDT_Restart(). + * -# Get watchdog status using \ref WDT_GetStatus(). + * -# Calculate watchdog period value using \ref WDT_GetPeriod(). + */ + +#ifndef _WDT_ +#define _WDT_ + +#include "chip.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void WDT_Enable(Wdt *pWDT, uint32_t dwMode); + +extern void WDT_Disable(Wdt *pWDT); + +extern void WDT_Restart(Wdt *pWDT); + +extern uint32_t WDT_GetStatus(Wdt *pWDT); + +extern uint32_t WDT_GetPeriod(uint32_t dwMs); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _WDT_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/xdma_hardware_interface.h b/bsps/arm/atsam/include/libchip/include/xdma_hardware_interface.h new file mode 100644 index 0000000000..c115a4f8c7 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/xdma_hardware_interface.h @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _XDMAD_IF_H +#define _XDMAD_IF_H + +/*---------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "chip.h" +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** DMA hardware interface */ +typedef struct _XdmaHardwareInterface { + uint8_t bXdmac; /**< DMA Controller number */ + uint32_t bPeriphID; /**< Peripheral ID */ + uint8_t bTransfer; /**< Transfer type 0: Tx, 1 :Rx*/ + uint8_t bIfID; /**< DMA Interface ID */ +} XdmaHardwareInterface; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint8_t XDMAIF_IsValidatedPeripherOnDma(uint8_t bPeriphID); +extern uint8_t XDMAIF_Get_ChannelNumber (uint8_t bPeriphID, uint8_t bTransfer); + +#endif //#ifndef _XDMAD_IF_H + diff --git a/bsps/arm/atsam/include/libchip/include/xdmac.h b/bsps/arm/atsam/include/libchip/include/xdmac.h new file mode 100644 index 0000000000..0b00dd505e --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/xdmac.h @@ -0,0 +1,640 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +/** \addtogroup dmac_module Working with DMAC + * \ingroup peripherals_module + * + * \section Usage + *
    + *
  • Enable or disable the a DMAC controller with DMAC_Enable() and or + * DMAC_Disable().
    • + *
  • Enable or disable %Dma interrupt using DMAC_EnableIt()or + * DMAC_DisableIt().
    • + *
  • Get %Dma interrupt status by DMAC_GetStatus() and + * DMAC_GetInterruptMask().
    • + *
  • Enable or disable specified %Dma channel with DMAC_EnableChannel() or + * DMAC_DisableChannel().
    • + *
  • Get %Dma channel status by DMAC_GetChannelStatus().
    • + *
  • ControlA and ControlB register is set by DMAC_SetControlA() and + * DMAC_SetControlB().
    • + *
  • Configure source and/or destination start address with + * DMAC_SetSourceAddr() and/or DMAC_SetDestinationAddr().
    • + *
  • Set %Dma descriptor address using DMAC_SetDescriptorAddr().
    • + *
  • Set source transfer buffer size with DMAC_SetBufferSize().
    • + *
  • Configure source and/or destination Picture-In-Picuture mode with + * DMAC_SetSourcePip() and/or DMAC_SetDestPip().
    • + *
+ * + * For more accurate information, please look at the DMAC section of the + * Datasheet. + * + * \sa \ref dmad_module + * + * Related files :\n + * \ref dmac.c\n + * \ref dmac.h.\n + * + */ + +#ifndef DMAC_H +#define DMAC_H +/**@{*/ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#ifndef __rtems__ +#include <../../../../utils/utility.h> +#endif /* __rtems__ */ +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ + +/** \addtogroup dmac_defines DMAC Definitions + * @{ + */ +/** Number of DMA channels */ +#define XDMAC_CONTROLLER_NUM 1 +/** Number of DMA channels */ +#define XDMAC_CHANNEL_NUM 24 +/** Max DMA single transfer size */ +#define XDMAC_MAX_BT_SIZE 0xFFFF +/** @}*/ + +/*---------------------------------------------------------------------------- + * Macro + *----------------------------------------------------------------------------*/ +#define XDMA_GET_DATASIZE(size) ((size==0)? XDMAC_CC_DWIDTH_BYTE : \ + ((size==1)? XDMAC_CC_DWIDTH_HALFWORD : \ + (XDMAC_CC_DWIDTH_WORD))) +#define XDMA_GET_CC_SAM(s) ((s==0)? XDMAC_CC_SAM_FIXED_AM : \ + ((s==1)? XDMAC_CC_SAM_INCREMENTED_AM : \ + ((s==2)? XDMAC_CC_SAM_UBS_AM : \ + XDMAC_CC_SAM_UBS_DS_AM))) +#define XDMA_GET_CC_DAM(d) ((d==0)? XDMAC_CC_DAM_FIXED_AM : \ + ((d==1)? XDMAC_CC_DAM_INCREMENTED_AM : \ + ((d==2)? XDMAC_CC_DAM_UBS_AM : \ + XDMAC_CC_DAM_UBS_DS_AM))) +#define XDMA_GET_CC_MEMSET(m) ((m==0)? XDMAC_CC_MEMSET_NORMAL_MODE : \ + XDMAC_CC_MEMSET_HW_MODE) + +/*------------------------------------------------------------------------------ + * Global functions + *----------------------------------------------------------------------------*/ +/** \addtogroup dmac_functions + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Get XDMAC global type. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetType(Xdmac *pXdmac) +{ + _Assert(pXdmac); + return pXdmac->XDMAC_GTYPE; +} + +/** + * \brief Get XDMAC global configuration. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetConfig(Xdmac *pXdmac) +{ + _Assert(pXdmac); + return pXdmac->XDMAC_GCFG; +} + +/** + * \brief Get XDMAC global weighted arbiter configuration. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetArbiter(Xdmac *pXdmac) +{ + _Assert(pXdmac); + return pXdmac->XDMAC_GWAC; +} + +/** + * \brief Enables XDMAC global interrupt. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param dwInteruptMask IT to be enabled. + */ +static inline void XDMAC_EnableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask) +{ + _Assert(pXdmac); + pXdmac->XDMAC_GIE = (XDMAC_GIE_IE0 << dwInteruptMask); +} + +/** + * \brief Disables XDMAC global interrupt + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param dwInteruptMask IT to be enabled + */ +static inline void XDMAC_DisableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask) +{ + _Assert(pXdmac); + pXdmac->XDMAC_GID = (XDMAC_GID_ID0 << dwInteruptMask); +} + +/** + * \brief Get XDMAC global interrupt mask. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetGItMask(Xdmac *pXdmac) +{ + _Assert(pXdmac); + return (pXdmac->XDMAC_GIM); +} + +/** + * \brief Get XDMAC global interrupt status. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetGIsr(Xdmac *pXdmac) +{ + _Assert(pXdmac); + return (pXdmac->XDMAC_GIS); +} + +/** + * \brief Get XDMAC masked global interrupt. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetMaskedGIsr(Xdmac *pXdmac) +{ + uint32_t _dwStatus; + _Assert(pXdmac); + _dwStatus = pXdmac->XDMAC_GIS; + _dwStatus &= pXdmac->XDMAC_GIM; + return _dwStatus; +} + +/** + * \brief enables the relevant channel of given XDMAC. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_EnableChannel(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel); +} + +/** + * \brief enables the relevant channels of given XDMAC. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param bmChannels Channels bitmap. + */ +static inline void XDMAC_EnableChannels(Xdmac *pXdmac, uint32_t bmChannels) +{ + _Assert(pXdmac); + pXdmac->XDMAC_GE = bmChannels; +} + +/** + * \brief Disables the relevant channel of given XDMAC. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_DisableChannel(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GD = (XDMAC_GD_DI0 << channel); +} + +/** + * \brief Disables the relevant channels of given XDMAC. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param bmChannels Channels bitmap. + */ +static inline void XDMAC_DisableChannels(Xdmac *pXdmac, uint32_t bmChannels) +{ + _Assert(pXdmac); + pXdmac->XDMAC_GD = bmChannels; +} + + +/** + * \brief Get Global channel status of given XDMAC. + * \note: When set to 1, this bit indicates that the channel x is enabled. + If a channel disable request is issued, this bit remains asserted + until pending transaction is completed. + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetGlobalChStatus(Xdmac *pXdmac) +{ + _Assert(pXdmac); + return pXdmac->XDMAC_GS; +} + +/** + * \brief Suspend the relevant channel's read. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_SuspendReadChannel(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GRS |= XDMAC_GRS_RS0 << channel; +} + +/** + * \brief Suspend the relevant channel's write. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_SuspendWriteChannel(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GWS |= XDMAC_GWS_WS0 << channel; +} + +/** + * \brief Suspend the relevant channel's read & write. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_SuspendReadWriteChannel(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GRWS = (XDMAC_GRWS_RWS0 << channel); +} + +/** + * \brief Resume the relevant channel's read & write. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_ResumeReadWriteChannel(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GRWR = (XDMAC_GRWR_RWR0 << channel); +} + +/** + * \brief Set software transfer request on the relevant channel. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_SoftwareTransferReq(Xdmac *pXdmac, uint8_t channel) +{ + + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GSWR = (XDMAC_GSWR_SWREQ0 << channel); +} + +/** + * \brief Get software transfer status of the relevant channel. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetSoftwareTransferStatus(Xdmac *pXdmac) +{ + + _Assert(pXdmac); + return pXdmac->XDMAC_GSWS; +} + +/** + * \brief Get interrupt status for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline uint32_t XDMAC_GetChannelIsr (Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + return pXdmac->XDMAC_CHID[channel].XDMAC_CIS; +} + +/** + * \brief Set software flush request on the relevant channel. + * \note: This API is used as polling without enabling FIE interrupt. + * The user can use it in interrupt mode after deleting while sentense. + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_SoftwareFlushReq(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GSWF = (XDMAC_GSWF_SWF0 << channel); + + while (!(XDMAC_GetChannelIsr(pXdmac, channel) & XDMAC_CIS_FIS)); +} + +/** + * \brief Disable interrupt with mask on the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param dwInteruptMask Interrupt mask. + */ +static inline void XDMAC_EnableChannelIt (Xdmac *pXdmac, uint8_t channel, + uint8_t dwInteruptMask) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CIE = dwInteruptMask; +} + +/** + * \brief Enable interrupt with mask on the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param dwInteruptMask Interrupt mask. + */ +static inline void XDMAC_DisableChannelIt (Xdmac *pXdmac, uint8_t channel, + uint8_t dwInteruptMask) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CID = dwInteruptMask; +} + +/** + * \brief Get interrupt mask for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline uint32_t XDMAC_GetChannelItMask (Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + return pXdmac->XDMAC_CHID[channel].XDMAC_CIM; +} + +/** + * \brief Get masked interrupt status for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline uint32_t XDMAC_GetMaskChannelIsr (Xdmac *pXdmac, uint8_t channel) +{ + uint32_t status; + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + status = pXdmac->XDMAC_CHID[channel].XDMAC_CIS; + status &= pXdmac->XDMAC_CHID[channel].XDMAC_CIM; + + return status; +} + +/** + * \brief Set source address for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param addr Source address. + */ +static inline void XDMAC_SetSourceAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CSA = addr; +} + +/** + * \brief Set destination address for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param addr Destination address. + */ +static inline void XDMAC_SetDestinationAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CDA = addr; +} + +/** + * \brief Set next descriptor's address & interface for the relevant channel of + * given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param addr Address of next descriptor. + * \param ndaif Interface of next descriptor. + */ +static inline void XDMAC_SetDescriptorAddr(Xdmac *pXdmac, uint8_t channel, + uint32_t addr, uint8_t ndaif) +{ + _Assert(pXdmac); + _Assert(ndaif < 2); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CNDA = (addr & 0xFFFFFFFC) | ndaif; +} + +/** + * \brief Set next descriptor's configuration for the relevant channel of + * given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param config Configuration of next descriptor. + */ +static inline void XDMAC_SetDescriptorControl(Xdmac *pXdmac, uint8_t channel, uint8_t config) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CNDC = config; +} + +/** + * \brief Set microblock length for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param ublen Microblock length. + */ +static inline void XDMAC_SetMicroblockControl(Xdmac *pXdmac, uint8_t channel, uint32_t ublen) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CUBC = XDMAC_CUBC_UBLEN(ublen); +} + +/** + * \brief Set block length for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param blen Block length. + */ +static inline void XDMAC_SetBlockControl(Xdmac *pXdmac, uint8_t channel, uint16_t blen) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CBC = XDMAC_CBC_BLEN(blen); +} + +/** + * \brief Set configuration for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param config Channel configuration. + */ +static inline void XDMAC_SetChannelConfig(Xdmac *pXdmac, uint8_t channel, uint32_t config) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CC = config; +} + +/** + * \brief Get the relevant channel's configuration of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline uint32_t XDMAC_GetChannelConfig(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + return pXdmac->XDMAC_CHID[channel].XDMAC_CC; +} + +/** + * \brief Set the relevant channel's data stride memory pattern of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param dds_msp Data stride memory pattern. + */ +static inline void XDMAC_SetDataStride_MemPattern(Xdmac *pXdmac, uint8_t channel, + uint32_t dds_msp) +{ + + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CDS_MSP = dds_msp; +} + +/** + * \brief Set the relevant channel's source microblock stride of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param subs Source microblock stride. + */ +static inline void XDMAC_SetSourceMicroBlockStride(Xdmac *pXdmac, uint8_t channel, + uint32_t subs) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CSUS = XDMAC_CSUS_SUBS(subs); +} + +/** + * \brief Set the relevant channel's destination microblock stride of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param dubs Destination microblock stride. + */ +static inline void XDMAC_SetDestinationMicroBlockStride(Xdmac *pXdmac, uint8_t channel, + uint32_t dubs) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CDUS = XDMAC_CDUS_DUBS(dubs); +} + +/** + * \brief Get the relevant channel's destination address of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline uint32_t XDMAC_GetChDestinationAddr(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + return pXdmac->XDMAC_CHID[channel].XDMAC_CDA; +} + +static inline void XDMAC_StartTransfer(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel); + pXdmac->XDMAC_GIE = (XDMAC_GIE_IE0 << channel); +} + +#ifdef __cplusplus +} +#endif + +/** @}*/ +/**@}*/ +#endif //#ifndef DMAC_H + diff --git a/bsps/arm/atsam/include/libchip/include/xdmad.h b/bsps/arm/atsam/include/libchip/include/xdmad.h new file mode 100644 index 0000000000..3b5e0838c2 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/xdmad.h @@ -0,0 +1,253 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _XDMAD_H +#define _XDMAD_H + + +/*---------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#include + + +/** \addtogroup dmad_defines DMA Driver Defines + @{*/ +/*---------------------------------------------------------------------------- + * Consts + *----------------------------------------------------------------------------*/ +#define XDMAD_TRANSFER_MEMORY 0xFF /**< DMA transfer from or to memory */ +#define XDMAD_ALLOC_FAILED 0xFFFF /**< Channel allocate failed */ + +#define XDMAD_TRANSFER_TX 0 +#define XDMAD_TRANSFER_RX 1 + +/* XDMA_MBR_UBC */ +#define XDMA_UBC_NDE (0x1u << 24) +#define XDMA_UBC_NDE_FETCH_DIS (0x0u << 24) +#define XDMA_UBC_NDE_FETCH_EN (0x1u << 24) +#define XDMA_UBC_NSEN (0x1u << 25) +#define XDMA_UBC_NSEN_UNCHANGED (0x0u << 25) +#define XDMA_UBC_NSEN_UPDATED (0x1u << 25) +#define XDMA_UBC_NDEN (0x1u << 26) +#define XDMA_UBC_NDEN_UNCHANGED (0x0u << 26) +#define XDMA_UBC_NDEN_UPDATED (0x1u << 26) +#define XDMA_UBC_NVIEW_Pos 27 +#define XDMA_UBC_NVIEW_Msk (0x3u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_Pos) + +/*---------------------------------------------------------------------------- + * MACRO + *----------------------------------------------------------------------------*/ + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup dmad_structs DMA Driver Structs + @{*/ + +/** DMA status or return code */ +typedef enum _XdmadStatus { + XDMAD_OK = 0, /**< Operation is successful */ + XDMAD_PARTIAL_DONE, + XDMAD_DONE, + XDMAD_BUSY, /**< Channel occupied or transfer not finished */ + XDMAD_ERROR, /**< Operation failed */ + XDMAD_CANCELED /**< Operation cancelled */ +} eXdmadStatus, eXdmadRC; + +/** DMA state for channel */ +typedef enum _XdmadState { + XDMAD_STATE_FREE = 0, /**< Free channel */ + XDMAD_STATE_ALLOCATED, /**< Allocated to some peripheral */ + XDMAD_STATE_START, /**< DMA started */ + XDMAD_STATE_IN_XFR, /**< DMA in transferring */ + XDMAD_STATE_DONE, /**< DMA transfer done */ + XDMAD_STATE_HALTED, /**< DMA transfer stopped */ +} eXdmadState; + +/** DMA Programming state for channel */ +typedef enum _XdmadProgState { + XDMAD_SINGLE = 0, + XDMAD_MULTI, + XDMAD_LLI, +} eXdmadProgState; + +/** DMA transfer callback */ +typedef void (*XdmadTransferCallback)(uint32_t Channel, void *pArg); + +/** DMA driver channel */ +typedef struct _XdmadChannel { + XdmadTransferCallback fCallback; /**< Callback */ + void *pArg; /**< Callback argument */ + uint8_t bIrqOwner; /**< Uses DMA handler or external one */ + uint8_t bSrcPeriphID; /**< HW ID for source */ + uint8_t bDstPeriphID; /**< HW ID for destination */ + uint8_t bSrcTxIfID; /**< DMA Tx Interface ID for source */ + uint8_t bSrcRxIfID; /**< DMA Rx Interface ID for source */ + uint8_t bDstTxIfID; /**< DMA Tx Interface ID for destination */ + uint8_t bDstRxIfID; /**< DMA Rx Interface ID for destination */ + volatile uint8_t state; /**< DMA channel state */ +} sXdmadChannel; + +/** DMA driver instance */ +typedef struct _Xdmad { + Xdmac *pXdmacs; + sXdmadChannel XdmaChannels[XDMACCHID_NUMBER]; + uint8_t numControllers; + uint8_t numChannels; + uint8_t xdmaMutex; +} sXdmad; + +typedef struct _XdmadCfg { + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; + /** Block Control Member. */ + uint32_t mbr_bc; + /** Data Stride Member. */ + uint32_t mbr_ds; + /** Source Microblock Stride Member. */ + uint32_t mbr_sus; + /** Destination Microblock Stride Member. */ + uint32_t mbr_dus; +} sXdmadCfg; + +/** \brief Structure for storing parameters for DMA view0 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView0 { + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Transfer Address Member. */ + uint32_t mbr_ta; +} LinkedListDescriporView0; + +/** \brief Structure for storing parameters for DMA view1 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView1 { + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; +} LinkedListDescriporView1; + +/** \brief Structure for storing parameters for DMA view2 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView2 { + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; +} LinkedListDescriporView2; + +/** \brief Structure for storing parameters for DMA view3 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView3 { + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; + /** Block Control Member. */ + uint32_t mbr_bc; + /** Data Stride Member. */ + uint32_t mbr_ds; + /** Source Microblock Stride Member. */ + uint32_t mbr_sus; + /** Destination Microblock Stride Member. */ + uint32_t mbr_dus; +} LinkedListDescriporView3; + +/** @}*/ + +extern sXdmad XDMAD_Instance; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup dmad_functions DMA Driver Functions + @{*/ +extern uint32_t XDMAD_AllocateChannel(sXdmad *pXdmad, + uint8_t bSrcID, uint8_t bDstID); +extern eXdmadRC XDMAD_FreeChannel(sXdmad *pXdmad, uint32_t dwChannel); + +extern eXdmadRC XDMAD_ConfigureTransfer(sXdmad *pXdmad, + uint32_t dwChannel, + sXdmadCfg *pXdmaParam, + uint32_t dwXdmaDescCfg, + uint32_t dwXdmaDescAddr, + uint32_t dwXdmaIntEn); + +extern eXdmadRC XDMAD_PrepareChannel(sXdmad *pXdmad, uint32_t dwChannel); + +extern eXdmadRC XDMAD_IsTransferDone(sXdmad *pXdmad, uint32_t dwChannel); + +extern eXdmadRC XDMAD_StartTransfer(sXdmad *pXdmad, uint32_t dwChannel); + +extern void XDMAD_DoNothingCallback(uint32_t Channel, void *pArg); + +extern eXdmadRC XDMAD_SetCallback(sXdmad *pXdmad, + uint32_t dwChannel, + XdmadTransferCallback fCallback, + void *pArg); + +extern eXdmadRC XDMAD_StopTransfer(sXdmad *pXdmad, uint32_t dwChannel); +/** @}*/ +/**@}*/ +#endif //#ifndef _XDMAD_H + diff --git a/bsps/arm/atsam/include/tm27.h b/bsps/arm/atsam/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/atsam/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/beagle/headers.am b/bsps/arm/beagle/headers.am new file mode 100644 index 0000000000..6692d0b69c --- /dev/null +++ b/bsps/arm/beagle/headers.am @@ -0,0 +1,14 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/beagle/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/bbb-gpio.h +include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/bbb-pwm.h +include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/beagleboneblack.h +include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/irq.h diff --git a/bsps/arm/beagle/include/bsp.h b/bsps/arm/beagle/include/bsp.h new file mode 100644 index 0000000000..1a69b5e308 --- /dev/null +++ b/bsps/arm/beagle/include/bsp.h @@ -0,0 +1,364 @@ +/** + * @file + * + * @ingroup arm_beagle + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2012 Claas Ziemke. All rights reserved. + * + * Claas Ziemke + * Kernerstrasse 11 + * 70182 Stuttgart + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified by Ben Gras to add lots + * of beagleboard/beaglebone definitions, delete lpc32xx specific + * ones, and merge with some other header files. + */ + +#ifndef LIBBSP_ARM_BEAGLE_BSP_H +#define LIBBSP_ARM_BEAGLE_BSP_H + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +/* UART base clock frequency */ +#define UART_CLOCK 48000000 + +/* Access memory-mapped I/O devices */ +#define mmio_read(a) (*(volatile uint32_t *)(a)) +#define mmio_write(a,v) (*(volatile uint32_t *)(a) = (v)) +#define mmio_set(a,v) mmio_write((a), mmio_read((a)) | (v)) +#define mmio_clear(a,v) mmio_write((a), mmio_read((a)) & ~(v)) + +#define REG16(x)(*((volatile uint16_t *)(x))) +#define REG(x)(*((volatile uint32_t *)(x))) +#define BIT(x)(0x1 << x) + +#define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick())) + +/* Write a uint32_t value to a memory address. */ +static inline void +write32(uint32_t address, uint32_t value) +{ + REG(address) = value; +} + +/* Read an uint32_t from a memory address */ +static inline uint32_t +read32(uint32_t address) +{ + return REG(address); +} + +/* Set a 32 bits value depending on a mask */ +static inline void +set32(uint32_t address, uint32_t mask, uint32_t value) +{ + uint32_t val; + val = read32(address); + /* clear the bits */ + val &= ~(mask); + /* apply the value using the mask */ + val |= (value & mask); + write32(address, val); +} + +/* Write a uint16_t value to a memory address. */ +static inline void +write16(uint32_t address, uint16_t value) +{ + REG16(address) = value; +} + +/* Read an uint16_t from a memory address */ +static inline uint16_t +read16(uint32_t address) +{ + return REG16(address); +} + +/* Data synchronization barrier */ +static inline void dsb(void) +{ + asm volatile("dsb" : : : "memory"); +} + +/* Instruction synchronization barrier */ +static inline void isb(void) +{ + asm volatile("isb" : : : "memory"); +} + +/* flush data cache */ +static inline void flush_data_cache(void) +{ + asm volatile( + "mov r0, #0\n" + "mcr p15, #0, r0, c7, c10, #4\n" + : /* No outputs */ + : /* No inputs */ + : "r0","memory" + ); +} + +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) + +#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define writeb(v,c) ({ unsigned char __v = v; __arch_putb(__v,c); __v; }) +#define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; }) +#define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; }) + +#define readb(c) ({ unsigned char __v = __arch_getb(c); __v; }) +#define readw(c) ({ unsigned short __v = __arch_getw(c); __v; }) +#define readl(c) ({ unsigned int __v = __arch_getl(c); __v; }) + +#define SYSTEM_CLOCK_12 12000000 +#define SYSTEM_CLOCK_13 13000000 +#define SYSTEM_CLOCK_192 19200000 +#define SYSTEM_CLOCK_96 96000000 + +#if !defined(IS_DM3730) && !defined(IS_AM335X) +#error Unrecognized BSP configured. +#endif + +#if IS_DM3730 +#define BSP_DEVICEMEM_START 0x48000000 +#define BSP_DEVICEMEM_END 0x5F000000 +#endif + +#if IS_AM335X +#define BSP_DEVICEMEM_START 0x44000000 +#define BSP_DEVICEMEM_END 0x57000000 +#endif + +/* per-target uart config */ +#if IS_AM335X +#define BSP_CONSOLE_UART 1 +#define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_1 +#define BSP_CONSOLE_UART_IRQ OMAP3_UART1_IRQ +#define BEAGLE_BASE_UART_1 0x44E09000 +#define BEAGLE_BASE_UART_2 0x48022000 +#define BEAGLE_BASE_UART_3 0x48024000 +#endif + +/* per-target uart config */ +#if IS_DM3730 +#define BSP_CONSOLE_UART 3 +#define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_3 +#define BSP_CONSOLE_UART_IRQ OMAP3_UART3_IRQ +#define BEAGLE_BASE_UART_1 0x4806A000 +#define BEAGLE_BASE_UART_2 0x4806C000 +#define BEAGLE_BASE_UART_3 0x49020000 +#endif + +/* GPIO pin config */ +#if IS_AM335X +#define BSP_GPIO_PIN_COUNT 128 +#define BSP_GPIO_PINS_PER_BANK 32 +#endif + +#if IS_DM3730 +#define BSP_GPIO_PIN_COUNT 192 +#define BSP_GPIO_PINS_PER_BANK 32 +#endif + +#if BSP_START_COPY_FDT_FROM_U_BOOT +#define BSP_FDT_IS_SUPPORTED +#endif + +/* i2c stuff */ +typedef struct { + uint32_t rx_or_tx; + uint32_t stat; + uint32_t ctrl; + uint32_t clk_hi; + uint32_t clk_lo; + uint32_t adr; + uint32_t rxfl; + uint32_t txfl; + uint32_t rxb; + uint32_t txb; + uint32_t s_tx; + uint32_t s_txfl; +} beagle_i2c; + +/* sctlr */ +/* Read System Control Register */ +static inline uint32_t read_sctlr() +{ + uint32_t ctl; + + asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t" + : [ctl] "=r" (ctl)); + return ctl; +} + +/* Write System Control Register */ +static inline void write_sctlr(uint32_t ctl) +{ + asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t" + : : [ctl] "r" (ctl)); + isb(); +} + +/* Read Auxiliary Control Register */ +static inline uint32_t read_actlr() +{ + uint32_t ctl; + + asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t" + : [ctl] "=r" (ctl)); + return ctl; +} + +/* Write Auxiliary Control Register */ +static inline void write_actlr(uint32_t ctl) +{ + asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t" + : : [ctl] "r" (ctl)); + isb(); +} + +/* Write Translation Table Base Control Register */ +static inline void write_ttbcr(uint32_t bcr) +{ + asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t" + : : [bcr] "r" (bcr)); + + isb(); +} + +/* Read Domain Access Control Register */ +static inline uint32_t read_dacr() +{ + uint32_t dacr; + + asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t" + : [dacr] "=r" (dacr)); + + return dacr; +} + + +/* Write Domain Access Control Register */ +static inline void write_dacr(uint32_t dacr) +{ + asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t" + : : [dacr] "r" (dacr)); + + isb(); +} + +static inline void refresh_tlb(void) +{ + dsb(); + + /* Invalidate entire unified TLB */ + asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t" + : : [zero] "r" (0)); + + /* Invalidate all instruction caches to PoU. + * Also flushes branch target cache. */ + asm volatile("mcr p15, 0, %[zero], c7, c5, 0" + : : [zero] "r" (0)); + + /* Invalidate entire branch predictor array */ + asm volatile("mcr p15, 0, %[zero], c7, c5, 6" + : : [zero] "r" (0)); /* flush BTB */ + + dsb(); + isb(); +} + +/* Read Translation Table Base Register 0 */ +static inline uint32_t read_ttbr0() +{ + uint32_t bar; + + asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t" + : [bar] "=r" (bar)); + + return bar & ARM_TTBR_ADDR_MASK; +} + + +/* Read Translation Table Base Register 0 */ +static inline uint32_t read_ttbr0_unmasked() +{ + uint32_t bar; + + asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t" + : [bar] "=r" (bar)); + + return bar; +} + +/* Write Translation Table Base Register 0 */ +static inline void write_ttbr0(uint32_t bar) +{ + dsb(); + isb(); + /* In our setup TTBR contains the base address *and* the flags + but other pieces of the kernel code expect ttbr to be the + base address of the l1 page table. We therefore add the + flags here and remove them in the read_ttbr0 */ + uint32_t v = (bar & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED; + asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t" + : : [bar] "r" (v)); + + refresh_tlb(); +} + +/* Behaviour on fatal error; default: test-friendly. + * set breakpoint to bsp_fatal_extension. + */ +/* Enabling BSP_PRESS_KEY_FOR_RESET prevents noninteractive testing */ +/*#define BSP_PRESS_KEY_FOR_RESET 1 */ +#define BSP_PRINT_EXCEPTION_CONTEXT 1 + /* human-readable exception info */ +#define BSP_RESET_BOARD_AT_EXIT 1 + /* causes qemu to exit, signaling end of test */ + + +/** + * @defgroup arm_beagle Beaglebone, Beagleboard Support + * + * @ingroup bsp_arm + * + * @brief Beaglebones and beagleboards support package + * + */ + +/** + * @brief Beagleboard specific set up of the MMU. + * + * Provide in the application to override. + */ +BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void); + +#endif /* LIBBSP_ARM_BEAGLE_BSP_H */ diff --git a/bsps/arm/beagle/include/bsp/bbb-gpio.h b/bsps/arm/beagle/include/bsp/bbb-gpio.h new file mode 100644 index 0000000000..ceb12a4dec --- /dev/null +++ b/bsps/arm/beagle/include/bsp/bbb-gpio.h @@ -0,0 +1,45 @@ +/** + * @file + * + * @ingroup arm_beagle + * + * @brief BeagleBone Black BSP definitions. + */ + +/** + * Copyright (c) 2015 Ketul Shah + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_BEAGLE_BBB_GPIO_H +#define LIBBSP_ARM_BEAGLE_BBB_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief BeagleBone Black GPIO functions. + */ +#define BBB_DIGITAL_IN 2 +#define BBB_DIGITAL_OUT 1 + +/** + * @brief BeagleBone Black GPIO pad configuration. + */ +#define BBB_PUDEN (1 << 3) +#define BBB_PUDDIS ~BBB_PUDEN +#define BBB_PU_EN (1 << 4) +#define BBB_PD_EN ~BBB_PU_EN +#define BBB_MUXMODE(X) (X & 0x7) +#define BBB_RXACTIVE (1 << 5) +#define BBB_SLEWCTRL (1 << 6) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_BEAGLE_BBB_GPIO_H */ diff --git a/bsps/arm/beagle/include/bsp/bbb-pwm.h b/bsps/arm/beagle/include/bsp/bbb-pwm.h new file mode 100644 index 0000000000..cf5d6fe552 --- /dev/null +++ b/bsps/arm/beagle/include/bsp/bbb-pwm.h @@ -0,0 +1,178 @@ +/** + * @file + * + * @ingroup arm_beagle + * + * @brief BeagleBone Black PWM support definitions. + */ + +/** + * Copyright (c) 2016 Punit Vara + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** Some constants are taken from + * https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.h + */ + +#ifndef LIBBSP_ARM_BEAGLE_BBB_PWM_H +#define LIBBSP_ARM_BEAGLE_BBB_PWM_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief BeagleBone Black PWM Macros. + */ +#define BBB_CONTROL_CONF_GPMC_AD(n) (0x800 + (n * 4)) +#define BBB_CONTROL_CONF_LCD_DATA(n) (0x8a0 + (n * 4)) + +/** + * @brief The set of possible PWM subsystem module + * + * Enumerated type to define various instance of pwm module. + */ +typedef enum{ + BBB_PWMSS0 = 0, + BBB_PWMSS1, + BBB_PWMSS2, + BBB_PWMSS_COUNT +}BBB_PWMSS; + +typedef enum{ + BBB_P8_13_2B = 3, + BBB_P8_19_2A, + BBB_P8_45_2A, + BBB_P8_46_2B, + BBB_P8_34_1B, + BBB_P8_36_1A, + BBB_P9_14_1A, + BBB_P9_16_1B, + BBB_P9_21_0B, + BBB_P9_22_0A, + BBB_P9_29_0B, + BBB_P9_31_0A +}bbb_pwm_pin_t; + +#define BBB_P8_13_MUX_PWM 4 +#define BBB_P8_19_MUX_PWM 4 +#define BBB_P8_45_MUX_PWM 3 +#define BBB_P8_46_MUX_PWM 3 +#define BBB_P8_34_MUX_PWM 2 +#define BBB_P8_36_MUX_PWM 2 +#define BBB_P9_14_MUX_PWM 6 +#define BBB_P9_16_MUX_PWM 6 +#define BBB_P9_21_MUX_PWM 3 +#define BBB_P9_22_MUX_PWM 3 +#define BBB_P9_29_MUX_PWM 1 +#define BBB_P9_31_MUX_PWM 1 +#define BBB_PWM_FREQ_THRESHOLD 0.5f + +/** + * @brief BeagleBone Black PWM API. + */ + +/** + * @brief This function intilizes clock for pwm sub system. + * + * @param PWMSS_ID It is the instance number of EPWM of pwm sub system. + * + * @return true if successful + * @return false if not successful + * + **/ +bool beagle_pwm_init(BBB_PWMSS pwmss_id); + +/* PWMSS setting + * set pulse argument of epwm module + * + * @param pwm_id : EPWMSS number , 0~2 + * @param pwm_freq : frequency to be generated + * @param dutyA : Duty Cycle(in percentage) in PWM channel A + * @param dutyB : Duty Cycle(in percentage) in PWM channel B + * + * @return : 1 for success + * @return : 0 for failed + * + * @example : beagle_pwm_configure(0 , 50.0f , 50.0f , 25.0f); // Generate 50HZ pwm in PWM0 , + * // duty cycle is 50% for ePWM0A , 25% for ePWM0B + * + * @Note : + * find an number nearst 65535 for TBPRD , to improve duty precision, + * + * Using big TBPRD can increase the range of CMPA and CMPB , + * and it means we can get better precision on duty cycle. + * + * EX : 20.25% duty cycle + * on TBPRD = 62500 , CMPA = 12656.25 ( .25 rejection) , real duty : 20.2496% (12656 /62500) + * on TBPRD = 6250 , CMPA = 1265.625 ( .625 rejection), real duty : 20.24% (1265 6250) + * on TBPRD = 500 , CMPA = 101.25 ( .25 rejection) , real duty : 20.2% (101/500) + * + * Divisor = CLKDIV * HSPCLKDIV + * 1 TBPRD : 10 ns (default) + * 65535 TBPRD : 655350 ns + * 65535 TBPRD : 655350 * Divisor ns = X TBPRD : Cycle + * + * accrooding to that , we must find a Divisor value , let X nearest 65535 . + * so , Divisor must Nearest Cycle/655350 + */ +int beagle_pwm_configure(BBB_PWMSS pwm_id, float pwm_freq, float duty_a, float duty_b); + +/** + * @brief This API enables the particular PWM module. + * + * @param pwmid It is the instance number of EPWM of pwm sub system. + * + * @return true if successful + * @return false if fail + * + **/ +bool beagle_pwm_enable(BBB_PWMSS pwmid); + +/** + * @brief This API disables the particular PWM module. + * + * @param pwmid It is the instance number of EPWM of pwm sub system. + * + * @return true if successful + * @return false if fail + * + **/ +bool beagle_pwm_disable(BBB_PWMSS pwmid); + +/** + * @brief This function enables pinmuxing for PWM module. + * + * @param pin_no It is individual pin at which freuqency need to be generated. + * It should be according to pwm sub system. + * + * @param pwm_id It is the instance number of EPWM of pwmsubsystem. + * + * @return true if successful + * @return false if fail + * + **/ +bool beagle_pwm_pinmux_setup(bbb_pwm_pin_t pin_no, BBB_PWMSS pwm_id); + +/** + * @brief This function determines whether PWMSS-wide clocks enabled or not. + * + * @param pwmss_id It is the instance number of PWMSS which clocks need to be + * checked. + * + * @return true if successful + * @return false if fail + * + **/ +bool beagle_pwmss_is_running(unsigned int pwmss_id); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_BEAGLE_BBB_PWM_H */ diff --git a/bsps/arm/beagle/include/bsp/beagleboneblack.h b/bsps/arm/beagle/include/bsp/beagleboneblack.h new file mode 100644 index 0000000000..c62f4aa92d --- /dev/null +++ b/bsps/arm/beagle/include/bsp/beagleboneblack.h @@ -0,0 +1,72 @@ +/** + * @file + * + * @ingroup arm_beagle + * + * @brief BeagleBone Black BSP definitions. + */ + +/** + * Copyright (c) 2015 Ketul Shah + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_BEAGLE_BEAGLEBONEBLACK_H +#define LIBBSP_ARM_BEAGLE_BEAGLEBONEBLACK_H + +/* In general GPIOs of BeagleBone Black/White can be addressed + * using two 46-pin dual-row expansion connectors P9 and P8, + * which are also known as Expansion A and Expansion B Connectors, + * respectively. + * + * Each Expansion Connector consists of 23 pins. So 2x23 pins would + * be available. It has 4 GPIO Banks each consists of 32 pins each. + * Toatal number of pins are 128 (32x4). + * + * So for mapping between generalized pin name and the unique pin + * numbers in this header file Macros are declared. + */ + +/* USER LEDs of BeagleBone Black */ +#define BBB_LED_USR0 53 /* USR LED0 */ +#define BBB_LED_USR1 54 /* USR LED1 */ +#define BBB_LED_USR2 55 /* USR LED2 */ +#define BBB_LED_USR3 56 /* USR LED3 */ + +/* Header P8 of BeagleBone Black */ +#define BBB_P8_7 66 /* GPIO2_2 */ +#define BBB_P8_8 67 /* GPIO2_3 */ +#define BBB_P8_9 69 /* GPIO2_5 */ +#define BBB_P8_10 68 /* GPIO2_4 */ +#define BBB_P8_11 45 /* GPIO1_13 */ +#define BBB_P8_12 44 /* GPIO1_12 */ +#define BBB_P8_13 23 /* GPIO0_23 */ +#define BBB_P8_14 26 /* GPIO0_26 */ +#define BBB_P8_15 47 /* GPIO1_15 */ +#define BBB_P8_16 46 /* GPIO1_14 */ +#define BBB_P8_17 27 /* GPIO0_27 */ +#define BBB_P8_18 65 /* GPIO2_1 */ +#define BBB_P8_19 22 /* GPIO0_22 */ +#define BBB_P8_26 61 /* GPIO1_29 */ + +/* Header P9 of BeagleBone Black */ +#define BBB_P9_11 30 /* GPIO0_30 */ +#define BBB_P9_12 60 /* GPIO1_28 */ +#define BBB_P9_13 31 /* GPIO0_31 */ +#define BBB_P9_14 50 /* GPIO1_18 */ +#define BBB_P9_15 48 /* GPIO1_16 */ +#define BBB_P9_16 51 /* GPIO1_19 */ +#define BBB_P9_17 5 /* GPIO0_5 */ +#define BBB_P9_18 4 /* GPIO0_4 */ +#define BBB_P9_23 49 /* GPIO1_17 */ +#define BBB_P9_24 15 /* GPIO0_15 */ +#define BBB_P9_26 14 /* GPIO1_14 */ +#define BBB_P9_27 115/* GPIO3_19 */ +#define BBB_P9_30 112/* GPIO3_16 */ +#define BBB_P9_41 20 /* GPIO0_20 */ +#define BBB_P9_42 7 /* GPIO0_7 */ + +#endif /* LIBBSP_ARM_BEAGLE_GPIO_H */ \ No newline at end of file diff --git a/bsps/arm/beagle/include/bsp/i2c.h b/bsps/arm/beagle/include/bsp/i2c.h new file mode 100644 index 0000000000..3ada3c4b0d --- /dev/null +++ b/bsps/arm/beagle/include/bsp/i2c.h @@ -0,0 +1,211 @@ +/** + * @file + * + * @ingroup arm_beagle + * + * @brief I2C support API. + */ + +/* + * Copyright (c) 2012 Claas Ziemke. All rights reserved. + * + * Claas Ziemke + * Kernerstrasse 11 + * 70182 Stuttgart + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_BEAGLE_I2C_H +#define LIBBSP_ARM_BEAGLE_I2C_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/* I2C Configuration Register (I2C_CON): */ + +#define BBB_I2C_CON_EN (1 << 15) /* I2C module enable */ +#define BBB_I2C_CON_BE (1 << 14) /* Big endian mode */ +#define BBB_I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ +#define BBB_I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define BBB_I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ + /* (master mode only) */ +#define BBB_I2C_CON_XA (1 << 8) /* Expand address */ +#define BBB_I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ +#define BBB_I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ +#define BBB_I2C_CON_CLR 0x0 /* Clear configuration register */ +/* I2C Status Register (I2C_STAT): */ + +#define BBB_I2C_STAT_SBD (1 << 15) /* Single byte data */ +#define BBB_I2C_STAT_BB (1 << 12) /* Bus busy */ +#define BBB_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define BBB_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define BBB_I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define BBB_I2C_STAT_GC (1 << 5) +#define BBB_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define BBB_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define BBB_I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define BBB_I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define BBB_I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define BBB_I2C_IE_GC_IE (1 << 5) +#define BBB_I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define BBB_I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define BBB_I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define BBB_I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define BBB_I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C SYSC Register (I2C_SYSC): */ +#define BBB_I2C_SYSC_SRST (1 << 1) + +#define BBB_I2C_TIMEOUT 1000 + +#define BBB_I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */ + +#define BBB_CONFIG_SYS_I2C_SPEED 100000 +#define BBB_CONFIG_SYS_I2C_SLAVE 1 +#define BBB_I2C_ALL_FLAGS 0x7FFF +#define BBB_I2C_ALL_IRQ_FLAGS 0xFFFF + +#define BBB_I2C_SYSCLK 48000000 +#define BBB_I2C_INTERNAL_CLK 12000000 +#define BBB_I2C_SPEED_CLK 100000 + +#define BBB_I2C_IRQ_ERROR \ + ( AM335X_I2C_IRQSTATUS_NACK \ + | AM335X_I2C_IRQSTATUS_ROVR \ + | AM335X_I2C_IRQSTATUS_AL \ + | AM335X_I2C_IRQSTATUS_ARDY \ + | AM335X_I2C_IRQSTATUS_RRDY \ + | AM335X_I2C_IRQSTATUS_XRDY \ + | AM335X_I2C_IRQSTATUS_XUDF ) + +#define BBB_I2C_IRQ_USED \ + ( AM335X_I2C_IRQSTATUS_ARDY \ + | AM335X_I2C_IRQSTATUS_XRDY ) + +#define BBB_I2C_0_BUS_PATH "/dev/i2c-0" +#define BBB_I2C_1_BUS_PATH "/dev/i2c-1" +#define BBB_I2C_2_BUS_PATH "/dev/i2c-2" + +#define BBB_I2C0_IRQ 70 +#define BBB_I2C1_IRQ 71 +#define BBB_I2C2_IRQ 30 + +#define BBB_MODE2 2 +#define BBB_MODE3 3 + +typedef enum { + I2C0, + I2C1, + I2C2, + I2C_COUNT +} bbb_i2c_id_t; + +typedef struct i2c_regs { + uint32_t BBB_I2C_REVNB_LO; + uint32_t BBB_I2C_REVNB_HI; + uint32_t dummy1[ 2 ]; + uint32_t BBB_I2C_SYSC; + uint32_t dummy2[ 4 ]; + uint32_t BBB_I2C_IRQSTATUS_RAW; + uint32_t BBB_I2C_IRQSTATUS; + uint32_t BBB_I2C_IRQENABLE_SET; + uint32_t BBB_I2C_IRQENABLE_CLR; + uint32_t BBB_I2C_WE; + uint32_t BBB_I2C_DMARXENABLE_SET; + uint32_t BBB_I2C_DMATXENABLE_SET; + uint32_t BBB_I2C_DMARXENABLE_CLR; + uint32_t BBB_I2C_DMATXENABLE_CLR; + uint32_t BBB_I2C_DMARXWAKE_EN; + uint32_t BBB_I2C_DMATXWAKE_EN; + uint32_t dummy3[ 16 ]; + uint32_t BBB_I2C_SYSS; + uint32_t BBB_I2C_BUF; + uint32_t BBB_I2C_CNT; + uint32_t BBB_I2C_DATA; + uint32_t dummy4; + uint32_t BBB_I2C_CON; + uint32_t BBB_I2C_OA; + uint32_t BBB_I2C_SA; + uint32_t BBB_I2C_PSC; + uint32_t BBB_I2C_SCLL; + uint32_t BBB_I2C_SCLH; + uint32_t BBB_I2C_SYSTEST; + uint32_t BBB_I2C_BUFSTAT; + uint32_t BBB_I2C_OA1; + uint32_t BBB_I2C_OA2; + uint32_t BBB_I2C_OA3; + uint32_t BBB_I2C_ACTOA; + uint32_t BBB_I2C_SBLOCK; +} bbb_i2c_regs; + +typedef struct bbb_i2c_bus { + i2c_bus base; + volatile bbb_i2c_regs *regs; + i2c_msg *msgs; + uint32_t msg_todo; + uint32_t current_msg_todo; + uint8_t *current_msg_byte; + uint32_t current_todo; + bool read; + bool hold; + rtems_id task_id; + rtems_vector_number irq; + uint32_t input_clock; + uint32_t already_transferred; +} bbb_i2c_bus; + +int am335x_i2c_bus_register( + const char *bus_path, + uintptr_t register_base, + uint32_t input_clock, + rtems_vector_number irq +); + +static inline int bbb_register_i2c_0( void ) +{ + return am335x_i2c_bus_register( + BBB_I2C_0_BUS_PATH, + AM335X_I2C0_BASE, + I2C_BUS_CLOCK_DEFAULT, + BBB_I2C0_IRQ + ); +} + +static inline int bbb_register_i2c_1( void ) +{ + return am335x_i2c_bus_register( + BBB_I2C_1_BUS_PATH, + AM335X_I2C1_BASE, + I2C_BUS_CLOCK_DEFAULT, + BBB_I2C1_IRQ + ); +} + +static inline int bbb_register_i2c_2( void ) +{ + return am335x_i2c_bus_register( + BBB_I2C_2_BUS_PATH, + AM335X_I2C2_BASE, + I2C_BUS_CLOCK_DEFAULT, + BBB_I2C2_IRQ + ); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_BEAGLE_I2C_H */ diff --git a/bsps/arm/beagle/include/bsp/irq.h b/bsps/arm/beagle/include/bsp/irq.h new file mode 100644 index 0000000000..4cbf3a271f --- /dev/null +++ b/bsps/arm/beagle/include/bsp/irq.h @@ -0,0 +1,23 @@ +/** + * @file + * + * @ingroup arm_beagle + * + * @brief Basic BSP IRQ info. + */ + +#ifndef LIBBSP_ARM_BEAGLE_IRQ_H +#define LIBBSP_ARM_BEAGLE_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 127 + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_BEAGLE_IRQ_H */ diff --git a/bsps/arm/beagle/include/tm27.h b/bsps/arm/beagle/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/beagle/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/csb336/headers.am b/bsps/arm/csb336/headers.am new file mode 100644 index 0000000000..911de17b50 --- /dev/null +++ b/bsps/arm/csb336/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/csb336/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/csb336/include/mc9328mxl.h +include_HEADERS += ../../../../../../bsps/arm/csb336/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/csb336/include/bsp/irq.h diff --git a/bsps/arm/csb336/include/bsp.h b/bsps/arm/csb336/include/bsp.h new file mode 100644 index 0000000000..ed036d5454 --- /dev/null +++ b/bsps/arm/csb336/include/bsp.h @@ -0,0 +1,68 @@ +/** + * @file + * + * @ingroup arm_csb336 + * + * @brief Global BSP definitions. + */ + +/* + * BSP CSB336 header file + * + * Copyright (c) 2004 Cogent Computer Systems + * Written by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ +#ifndef LIBBSP_ARM_CSB336_BSP_H +#define LIBBSP_ARM_CSB336_BSP_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup arm_csb336 CSB336 Support + * + * @ingroup bsp_arm + * + * @brief CSB336 support package. + * + * @{ + */ + +#define BSP_FEATURE_IRQ_EXTENSION + +/* What is the input clock freq in hertz? */ +#define BSP_OSC_FREQ 16000000 /* 16 MHz oscillator */ +#define BSP_XTAL_FREQ 32768 /* 32.768 KHz crystal */ + +int get_perclk1_freq(void); + +/** + * @brief Network driver configuration + */ +extern struct rtems_bsdnet_ifconfig *config; + +/* Change these to match your board */ +int rtems_mc9328mxl_enet_attach(struct rtems_bsdnet_ifconfig *config, + void *chip); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mc9328mxl_enet_attach + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ + diff --git a/bsps/arm/csb336/include/bsp/irq.h b/bsps/arm/csb336/include/bsp/irq.h new file mode 100644 index 0000000000..eb56fdd887 --- /dev/null +++ b/bsps/arm/csb336/include/bsp/irq.h @@ -0,0 +1,95 @@ +/* + * Interrupt handler Header file + * + * Copyright (c) 2010 embedded brains GmbH. + * + * Copyright (c) 2004 by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __IRQ_H__ +#define __IRQ_H__ + +#ifndef __asm__ + +#include +#include +#include + +#endif /* __asm__ */ + +/* possible interrupt sources on the MC9328MXL */ +#define BSP_INT_UART3_PFERR 0 +#define BSP_INT_UART3_RTS 1 +#define BSP_INT_UART3_DTR 2 +#define BSP_INT_UART3_UARTC 3 +#define BSP_INT_UART3_TX 4 +#define BSP_INT_PEN_UP 5 +#define BSP_INT_CSI 6 +#define BSP_INT_MMA_MAC 7 +#define BSP_INT_MMA 8 +#define BSP_INT_COMP 9 +#define BSP_INT_MSIRQ 10 +#define BSP_INT_GPIO_PORTA 11 +#define BSP_INT_GPIO_PORTB 12 +#define BSP_INT_GPIO_PORTC 13 +#define BSP_INT_LCDC 14 +#define BSP_INT_SIM_IRQ 15 +#define BSP_INT_SIM_DATA 16 +#define BSP_INT_RTC 17 +#define BSP_INT_RTC_SAM 18 +#define BSP_INT_UART2_PFERR 19 +#define BSP_INT_UART2_RTS 20 +#define BSP_INT_UART2_DTR 21 +#define BSP_INT_UART2_UARTC 22 +#define BSP_INT_UART2_TX 23 +#define BSP_INT_UART2_RX 24 +#define BSP_INT_UART1_PFERR 25 +#define BSP_INT_UART1_RTS 26 +#define BSP_INT_UART1_DTR 27 +#define BSP_INT_UART1_UARTC 28 +#define BSP_INT_UART1_TX 29 +#define BSP_INT_UART1_RX 30 +#define BSP_INT_RES31 31 +#define BSP_INT_RES32 32 +#define BSP_INT_PEN_DATA 33 +#define BSP_INT_PWM 34 +#define BSP_INT_MMC_IRQ 35 +#define BSP_INT_SSI2_TX 36 +#define BSP_INT_SSI2_RX 37 +#define BSP_INT_SSI2_ERR 38 +#define BSP_INT_I2C 39 +#define BSP_INT_SPI2 40 +#define BSP_INT_SPI1 41 +#define BSP_INT_SSI_TX 42 +#define BSP_INT_SSI_TX_ERR 43 +#define BSP_INT_SSI_RX 44 +#define BSP_INT_SSI_RX_ERR 45 +#define BSP_INT_TOUCH 46 +#define BSP_INT_USBD0 47 +#define BSP_INT_USBD1 48 +#define BSP_INT_USBD2 49 +#define BSP_INT_USBD3 50 +#define BSP_INT_USBD4 51 +#define BSP_INT_USBD5 52 +#define BSP_INT_USBD6 53 +#define BSP_INT_UART3_RX 54 +#define BSP_INT_BTSYS 55 +#define BSP_INT_BTTIM 56 +#define BSP_INT_BTWUI 57 +#define BSP_INT_TIMER2 58 +#define BSP_INT_TIMER1 59 +#define BSP_INT_DMA_ERR 60 +#define BSP_INT_DMA 61 +#define BSP_INT_GPIO_PORTD 62 +#define BSP_INT_WDT 63 +#define BSP_MAX_INT 64 + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) + +#endif /* __IRQ_H__ */ diff --git a/bsps/arm/csb336/include/mc9328mxl.h b/bsps/arm/csb336/include/mc9328mxl.h new file mode 100644 index 0000000000..dd0516283a --- /dev/null +++ b/bsps/arm/csb336/include/mc9328mxl.h @@ -0,0 +1,486 @@ +/* + * Motorola MC9328MXL Register definitions + * + * Copyright (c) 2003 by Cogent Computer Systems + * Written by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __MC9328MXL_H__ +#define __MC9328MXL_H__ + +#include + +#define bit(_x_) (1 << (_x_)) + +/* Define some constants relating to the CPU */ +#define MC9328MXL_NUM_INTS 64 /* CPU supports 64 interrupts */ + +/* Define the base addresses of the internal registers */ +#define MC9328MXL_AIPI1_BASE 0x00200000 +#define MC9328MXL_AIPI2_BASE 0x00210000 +#define MC9328MXL_WDOG_BASE 0x00201000 +#define MC9328MXL_TMR1_BASE 0x00202000 +#define MC9328MXL_TMR2_BASE 0x00203000 +#define MC9328MXL_RTC_BASE 0x00204000 +#define MC9328MXL_LCDC_BASE 0x00205000 +#define MC9328MXL_UART1_BASE 0x00206000 +#define MC9328MXL_UART2_BASE 0x00207000 +#define MC9328MXL_PWM_BASE 0x00208000 +#define MC9328MXL_DMAC_BASE 0x00209000 +#define MC9328MXL_USBD_BASE 0x00212000 +#define MC9328MXL_SPI1_BASE 0x00213000 +#define MC9328MXL_SPI2_BASE 0x00219000 +#define MC9328MXL_MMC_BASE 0x00214000 +#define MC9328MXL_I2C_BASE 0x00217000 +#define MC9328MXL_SSI_BASE 0x00218000 +#define MC9328MXL_MSHC_BASE 0x0021a000 +#define MC9328MXL_PLL_BASE 0x0021b000 +#define MC9328MXL_RESET_BASE 0x0021b800 +#define MC9328MXL_SYSCTRL_BASE 0x0021b804 +#define MC9328MXL_GPIOA_BASE 0x0021c000 +#define MC9328MXL_GPIOB_BASE 0x0021c100 +#define MC9328MXL_GPIOC_BASE 0x0021c200 +#define MC9328MXL_GPIOD_BASE 0x0021c300 +#define MC9328MXL_EIM_BASE 0x00220000 +#define MC9328MXL_SDRAM_BASE 0x00221000 +#define MC9328MXL_MMA_BASE 0x00222000 +#define MC9328MXL_AITC_BASE 0x00223000 +#define MC9328MXL_CSI_BASE 0x00224000 + + +#define MC9328MXL_TMR1_TCTL (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x00))) +#define MC9328MXL_TMR1_TPRER (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x04))) +#define MC9328MXL_TMR1_TCMP (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x08))) +#define MC9328MXL_TMR1_TCR (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x0c))) +#define MC9328MXL_TMR1_TCN (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x10))) +#define MC9328MXL_TMR1_TSTAT (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x14))) + +#define MC9328MXL_TMR2_TCTL (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x00))) +#define MC9328MXL_TMR2_TPRER (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x04))) +#define MC9328MXL_TMR2_TCMP (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x08))) +#define MC9328MXL_TMR2_TCR (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x0c))) +#define MC9328MXL_TMR2_TCN (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x10))) +#define MC9328MXL_TMR2_TSTAT (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x14))) + +#define MC9328MXL_TMR_TCTL_SWR (bit(15)) +#define MC9328MXL_TMR_TCTL_FRR (bit(8)) +#define MC9328MXL_TMR_TCTL_CAP_DIS (0 << 6) +#define MC9328MXL_TMR_TCTL_CAP_RISE (1 << 6) +#define MC9328MXL_TMR_TCTL_CAP_FALL (2 << 6) +#define MC9328MXL_TMR_TCTL_CAP_ANY (3 << 6) +#define MC9328MXL_TMR_TCTL_OM (bit(5)) +#define MC9328MXL_TMR_TCTL_IRQEN (bit(4)) +#define MC9328MXL_TMR_TCTL_CLKSRC_STOP (0 << 1) +#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 (1 << 1) +#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK_DIV16 (2 << 1) +#define MC9328MXL_TMR_TCTL_CLKSRC_TIN (3 << 1) +#define MC9328MXL_TMR_TCTL_CLKSRC_32KHX (4 << 1) +#define MC9328MXL_TMR_TCTL_TEN (bit(0)) + +#define MC9328MXL_UART1_RXD (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x00))) +#define MC9328MXL_UART1_TXD (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x40))) +#define MC9328MXL_UART1_CR1 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x80))) +#define MC9328MXL_UART1_CR2 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x84))) +#define MC9328MXL_UART1_CR3 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x88))) +#define MC9328MXL_UART1_CR4 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x8c))) +#define MC9328MXL_UART1_FCR (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x90))) +#define MC9328MXL_UART1_SR1 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x94))) +#define MC9328MXL_UART1_SR2 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x98))) +#define MC9328MXL_UART1_ESC (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x9c))) +#define MC9328MXL_UART1_TIM (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xa0))) +#define MC9328MXL_UART1_BIR (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xa4))) +#define MC9328MXL_UART1_BMR (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xa8))) +#define MC9328MXL_UART1_BRC (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xac))) +#define MC9328MXL_UART1_IPR1 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xb0))) +#define MC9328MXL_UART1_IPR2 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xb4))) +#define MC9328MXL_UART1_IPR3 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xb8))) +#define MC9328MXL_UART1_IPR4 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xbc))) +#define MC9328MXL_UART1_MPR1 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xc0))) +#define MC9328MXL_UART1_MPR2 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xc4))) +#define MC9328MXL_UART1_MPR3 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xc8))) +#define MC9328MXL_UART1_MPR4 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xcc))) +#define MC9328MXL_UART1_TS (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xd0))) + +#define MC9328MXL_UART2_RXD (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x00))) +#define MC9328MXL_UART2_TXD (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x40))) +#define MC9328MXL_UART2_CR1 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x80))) +#define MC9328MXL_UART2_CR2 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x84))) +#define MC9328MXL_UART2_CR3 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x88))) +#define MC9328MXL_UART2_CR4 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x8c))) +#define MC9328MXL_UART2_FCR (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x90))) +#define MC9328MXL_UART2_SR1 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x94))) +#define MC9328MXL_UART2_SR2 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x98))) +#define MC9328MXL_UART2_ESC (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x9c))) +#define MC9328MXL_UART2_TIM (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xa0))) +#define MC9328MXL_UART2_BIR (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xa4))) +#define MC9328MXL_UART2_BMR (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xa8))) +#define MC9328MXL_UART2_BRC (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xac))) +#define MC9328MXL_UART2_IPR1 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xb0))) +#define MC9328MXL_UART2_IPR2 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xb4))) +#define MC9328MXL_UART2_IPR3 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xb8))) +#define MC9328MXL_UART2_IPR4 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xbc))) +#define MC9328MXL_UART2_MPR1 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xc0))) +#define MC9328MXL_UART2_MPR2 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xc4))) +#define MC9328MXL_UART2_MPR3 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xc8))) +#define MC9328MXL_UART2_MPR4 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xcc))) +#define MC9328MXL_UART2_TS (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xd0))) + +typedef struct { + volatile uint32_t rxd; + volatile uint32_t _res0[15]; + volatile uint32_t txd; + volatile uint32_t _res1[15]; + volatile uint32_t cr1; + volatile uint32_t cr2; + volatile uint32_t cr3; + volatile uint32_t cr4; + volatile uint32_t fcr; + volatile uint32_t sr1; + volatile uint32_t sr2; + volatile uint32_t esc; + volatile uint32_t tim; + volatile uint32_t bir; + volatile uint32_t bmr; + volatile uint32_t brc; + volatile uint32_t ipr1; + volatile uint32_t ipr2; + volatile uint32_t ipr3; + volatile uint32_t ipr4; + volatile uint32_t mpr1; + volatile uint32_t mpr2; + volatile uint32_t mpr3; + volatile uint32_t mpr4; + volatile uint32_t ts; +} mc9328mxl_uart_regs_t; + +#define MC9328MXL_UART_RXD_CHARRDY (bit(15)) +#define MC9328MXL_UART_RXD_ERR (bit(14)) +#define MC9328MXL_UART_RXD_OVRRUN (bit(13)) +#define MC9328MXL_UART_RXD_FRMERR (bit(12)) +#define MC9328MXL_UART_RXD_BRK (bit(11)) +#define MC9328MXL_UART_RXD_PRERR (bit(10)) +#define MC9328MXL_UART_RXD_CHARMASK (0xff) + +#define MC9328MXL_UART_CR1_ADEN (bit(15)) +#define MC9328MXL_UART_CR1_ADBR (bit(14)) +#define MC9328MXL_UART_CR1_TRDYEN (bit(13)) +#define MC9328MXL_UART_CR1_IDEN (bit(12)) +#define MC9328MXL_UART_CR1_ICD4 (0x0 << 10) +#define MC9328MXL_UART_CR1_ICD8 (0x1 << 10) +#define MC9328MXL_UART_CR1_ICD16 (0x2 << 10) +#define MC9328MXL_UART_CR1_ICD32 (0x3 << 10) +#define MC9328MXL_UART_CR1_RRDYEN (bit(9)) +#define MC9328MXL_UART_CR1_RDMAEN (bit(8)) +#define MC9328MXL_UART_CR1_IREN (bit(7)) +#define MC9328MXL_UART_CR1_TXMPTYEN (bit(6)) +#define MC9328MXL_UART_CR1_RTSDEN (bit(5)) +#define MC9328MXL_UART_CR1_SNDBRK (bit(4)) +#define MC9328MXL_UART_CR1_TDMAEN (bit(3)) +#define MC9328MXL_UART_CR1_UARTCLKEN (bit(2)) +#define MC9328MXL_UART_CR1_DOZE (bit(1)) +#define MC9328MXL_UART_CR1_UARTEN (bit(0)) + + +#define MC9328MXL_UART_CR2_ESCI (bit(15)) +#define MC9328MXL_UART_CR2_IRTS (bit(14)) +#define MC9328MXL_UART_CR2_CTSC (bit(13)) +#define MC9328MXL_UART_CR2_CTS (bit(12)) +#define MC9328MXL_UART_CR2_ESCEN (bit(11)) +#define MC9328MXL_UART_CR2_RTEC_RE (0 << 9) +#define MC9328MXL_UART_CR2_RTEC_FE (1 << 9) +#define MC9328MXL_UART_CR2_RTEC_ANY (2 << 9) +#define MC9328MXL_UART_CR2_PREN (bit(8)) +#define MC9328MXL_UART_CR2_PROE (bit(7)) +#define MC9328MXL_UART_CR2_STPB (bit(6)) +#define MC9328MXL_UART_CR2_WS (bit(5)) +#define MC9328MXL_UART_CR2_RTSEN (bit(4)) +#define MC9328MXL_UART_CR2_TXEN (bit(2)) +#define MC9328MXL_UART_CR2_RXEN (bit(1)) +#define MC9328MXL_UART_CR2_SRST (bit(0)) + +#define MC9328MXL_UART_CR3_DPEC_RE (0 << 14) /* UART2 only */ +#define MC9328MXL_UART_CR3_DPEC_FE (1 << 14) /* UART2 only */ +#define MC9328MXL_UART_CR3_DPEC_ANY (2 << 14) /* UART2 only */ +#define MC9328MXL_UART_CR3_DTREN (bit(13)) /* UART2 only */ +#define MC9328MXL_UART_CR3_PARERREN (bit(12)) +#define MC9328MXL_UART_CR3_FRAERREN (bit(11)) +#define MC9328MXL_UART_CR3_DSR (bit(10)) /* UART2 only */ +#define MC9328MXL_UART_CR3_DCD (bit(9)) /* UART2 only */ +#define MC9328MXL_UART_CR3_RI (bit(8)) /* UART2 only */ +#define MC9328MXL_UART_CR3_RXDSEN (bit(6)) +#define MC9328MXL_UART_CR3_AIRINTEN (bit(5)) +#define MC9328MXL_UART_CR3_AWAKEN (bit(4)) +#define MC9328MXL_UART_CR3_REF25 (bit(3)) +#define MC9328MXL_UART_CR3_REF30 (bit(2)) +#define MC9328MXL_UART_CR3_INVT (bit(1)) +#define MC9328MXL_UART_CR3_BPEN (bit(0)) + +#define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10) +#define MC9328MXL_UART_CR4_INVR (bit(9)) +#define MC9328MXL_UART_CR4_ENIRI (bit(8)) +#define MC9328MXL_UART_CR4_WKEN (bit(7)) +#define MC9328MXL_UART_CR4_REF16 (bit(6)) +#define MC9328MXL_UART_CR4_IRSC (bit(5)) +#define MC9328MXL_UART_CR4_TCEN (bit(3)) +#define MC9328MXL_UART_CR4_BKEN (bit(2)) +#define MC9328MXL_UART_CR4_OREN (bit(1)) +#define MC9328MXL_UART_CR4_DREN (bit(0)) + +#define MC9328MXL_UART_FCR_TXTL(x) (((x) & 0x3f) << 10) +#define MC9328MXL_UART_FCR_RFDIV_1 (5 << 7) +#define MC9328MXL_UART_FCR_RFDIV_2 (4 << 7) +#define MC9328MXL_UART_FCR_RFDIV_3 (3 << 7) +#define MC9328MXL_UART_FCR_RFDIV_4 (2 << 7) +#define MC9328MXL_UART_FCR_RFDIV_5 (1 << 7) +#define MC9328MXL_UART_FCR_RFDIV_6 (0 << 7) +#define MC9328MXL_UART_FCR_RFDIV_7 (6 << 7) +#define MC9328MXL_UART_FCR_RFDIV_MASK (7 << 7) +#define MC9328MXL_UART_FCR_RXTL(x) (((x) & 0x3f) << 0) + +#define MC9328MXL_UART_SR1_PARERR (bit(15)) +#define MC9328MXL_UART_SR1_RTSS (bit(14)) +#define MC9328MXL_UART_SR1_TRDY (bit(13)) +#define MC9328MXL_UART_SR1_RTSD (bit(12)) +#define MC9328MXL_UART_SR1_ESCF (bit(11)) +#define MC9328MXL_UART_SR1_FRMERR (bit(10)) +#define MC9328MXL_UART_SR1_RRDY (bit(9)) +#define MC9328MXL_UART_SR1_RXDS (bit(6)) +#define MC9328MXL_UART_SR1_AIRINT (bit(5)) +#define MC9328MXL_UART_SR1_AWAKE (bit(4)) + +#define MC9328MXL_UART_SR2_ADET (bit(15)) +#define MC9328MXL_UART_SR2_TXFE (bit(14)) +#define MC9328MXL_UART_SR2_DTRF (bit(13)) +#define MC9328MXL_UART_SR2_IDLE (bit(12)) +#define MC9328MXL_UART_SR2_IRINT (bit(8)) +#define MC9328MXL_UART_SR2_WAKE (bit(7)) +#define MC9328MXL_UART_SR2_RTSF (bit(4)) +#define MC9328MXL_UART_SR2_TXDC (bit(3)) +#define MC9328MXL_UART_SR2_BRCD (bit(2)) +#define MC9328MXL_UART_SR2_ORE (bit(1)) +#define MC9328MXL_UART_SR2_RDR (bit(0)) + + +#define MC9328MXL_PLL_CSCR (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x00))) +#define MC9328MXL_PLL_MPCTL0 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x04))) +#define MC9328MXL_PLL_MPCTL1 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x08))) +#define MC9328MXL_PLL_SPCTL0 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x0c))) +#define MC9328MXL_PLL_SPCTL1 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x10))) +#define MC9328MXL_PLL_PCDR (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x20))) + +#define MC9328MXL_PLL_CSCR_CLKOSEL_PERCLK1 (0 << 29) +#define MC9328MXL_PLL_CSCR_CLKOSEL_HCLK (1 << 29) +#define MC9328MXL_PLL_CSCR_CLKOSEL_CLK48M (2 << 29) +#define MC9328MXL_PLL_CSCR_CLKOSEL_CLK16M (3 << 29) +#define MC9328MXL_PLL_CSCR_CLKOSEL_PREMCLK (4 << 29) +#define MC9328MXL_PLL_CSCR_CLKOSEL_FCLK (5 << 29) + +#define MC9328MXL_PLL_CSCR_USBDIV(_x_) (((_x_) & 0x7) << 26) +#define MC9328MXL_PLL_CSCR_SDCNT_1 (0 << 24) +#define MC9328MXL_PLL_CSCR_SDCNT_2 (1 << 24) +#define MC9328MXL_PLL_CSCR_SDCNT_3 (2 << 24) +#define MC9328MXL_PLL_CSCR_SDCNT_4 (3 << 24) + +#define MC9328MXL_PLL_CSCR_SPLLRSTRT (bit(22)) +#define MC9328MXL_PLL_CSCR_MPLLRSTRT (bit(21)) +#define MC9328MXL_PLL_CSCR_CLK16SEL (bit(18)) +#define MC9328MXL_PLL_CSCR_OSCEN (bit(17)) +#define MC9328MXL_PLL_CSCR_SYSSEL (bit(16)) +#define MC9328MXL_PLL_CSCR_PRESC (bit(15)) +#define MC9328MXL_PLL_CSCR_BLKDIV(_x_) (((_x_) & 0xf) << 10) +#define MC9328MXL_PLL_CSCR_SPEN (bit(1)) +#define MC9328MXL_PLL_CSCR_MPEN (bit(0)) + +#define MC9328MXL_PLL_PCDR_PCLK1_MASK (0x0000000f) +#define MC9328MXL_PLL_PCDR_PCLK1_SHIFT (0) +#define MC9328MXL_PLL_PCDR_PCLK2_MASK (0x000000f0) +#define MC9328MXL_PLL_PCDR_PCLK2_SHIFT (4) +#define MC9328MXL_PLL_PCDR_PCLK3_MASK (0x007f0000) +#define MC9328MXL_PLL_PCDR_PCLK3_SHIFT (16) + + +#define MC9328MXL_PLL_SPCTL_PD_MASK (0x3c000000) +#define MC9328MXL_PLL_SPCTL_PD_SHIFT (26) +#define MC9328MXL_PLL_SPCTL_MFD_MASK (0x03ff0000) +#define MC9328MXL_PLL_SPCTL_MFD_SHIFT (16) +#define MC9328MXL_PLL_SPCTL_MFI_MASK (0x00003c00) +#define MC9328MXL_PLL_SPCTL_MFI_SHIFT (10) +#define MC9328MXL_PLL_SPCTL_MFN_MASK (0x000003ff) +#define MC9328MXL_PLL_SPCTL_MFN_SHIFT (0) + + +#define MC9328MXL_GPIOA_DDIR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x00))) +#define MC9328MXL_GPIOA_OCR1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x04))) +#define MC9328MXL_GPIOA_OCR2 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x08))) +#define MC9328MXL_GPIOA_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x0c))) +#define MC9328MXL_GPIOA_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x10))) +#define MC9328MXL_GPIOA_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x14))) +#define MC9328MXL_GPIOA_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x18))) +#define MC9328MXL_GPIOA_DR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x1c))) +#define MC9328MXL_GPIOA_GIUS (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x20))) +#define MC9328MXL_GPIOA_SSR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x24))) +#define MC9328MXL_GPIOA_ICR1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x28))) +#define MC9328MXL_GPIOA_ICR2 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x2c))) +#define MC9328MXL_GPIOA_IMR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x30))) +#define MC9328MXL_GPIOA_ISR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x34))) +#define MC9328MXL_GPIOA_GPR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x38))) +#define MC9328MXL_GPIOA_SWR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x3c))) +#define MC9328MXL_GPIOA_PUEN (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x40))) + +#define MC9328MXL_GPIOB_DDIR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x00))) +#define MC9328MXL_GPIOB_OCR1 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x04))) +#define MC9328MXL_GPIOB_OCR2 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x08))) +#define MC9328MXL_GPIOB_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x0c))) +#define MC9328MXL_GPIOB_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x10))) +#define MC9328MXL_GPIOB_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x14))) +#define MC9328MXL_GPIOB_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x18))) +#define MC9328MXL_GPIOB_DR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x1c))) +#define MC9328MXL_GPIOB_GIUS (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x20))) +#define MC9328MXL_GPIOB_SSR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x24))) +#define MC9328MXL_GPIOB_ICR1 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x28))) +#define MC9328MXL_GPIOB_ICR2 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x2c))) +#define MC9328MXL_GPIOB_IMR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x30))) +#define MC9328MXL_GPIOB_ISR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x34))) +#define MC9328MXL_GPIOB_GPR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x38))) +#define MC9328MXL_GPIOB_SWR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x3c))) +#define MC9328MXL_GPIOB_PUEN (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x40))) + +#define MC9328MXL_GPIOC_DDIR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x00))) +#define MC9328MXL_GPIOC_OCR1 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x04))) +#define MC9328MXL_GPIOC_OCR2 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x08))) +#define MC9328MXL_GPIOC_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x0c))) +#define MC9328MXL_GPIOC_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x10))) +#define MC9328MXL_GPIOC_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x14))) +#define MC9328MXL_GPIOC_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x18))) +#define MC9328MXL_GPIOC_DR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x1c))) +#define MC9328MXL_GPIOC_GIUS (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x20))) +#define MC9328MXL_GPIOC_SSR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x24))) +#define MC9328MXL_GPIOC_ICR1 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x28))) +#define MC9328MXL_GPIOC_ICR2 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x2c))) +#define MC9328MXL_GPIOC_IMR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x30))) +#define MC9328MXL_GPIOC_ISR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x34))) +#define MC9328MXL_GPIOC_GPR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x38))) +#define MC9328MXL_GPIOC_SWR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x3c))) +#define MC9328MXL_GPIOC_PUEN (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x40))) + +#define MC9328MXL_GPIOD_DDIR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x00))) +#define MC9328MXL_GPIOD_OCR1 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x04))) +#define MC9328MXL_GPIOD_OCR2 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x08))) +#define MC9328MXL_GPIOD_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x0c))) +#define MC9328MXL_GPIOD_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x10))) +#define MC9328MXL_GPIOD_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x14))) +#define MC9328MXL_GPIOD_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x18))) +#define MC9328MXL_GPIOD_DR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x1c))) +#define MC9328MXL_GPIOD_GIUS (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x20))) +#define MC9328MXL_GPIOD_SSR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x24))) +#define MC9328MXL_GPIOD_ICR1 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x28))) +#define MC9328MXL_GPIOD_ICR2 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x2c))) +#define MC9328MXL_GPIOD_IMR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x30))) +#define MC9328MXL_GPIOD_ISR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x34))) +#define MC9328MXL_GPIOD_GPR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x38))) +#define MC9328MXL_GPIOD_SWR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x3c))) +#define MC9328MXL_GPIOD_PUEN (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x40))) + +#define MC9328MXL_AITC_INTCNTL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE) + 0x00))) +#define MC9328MXL_AITC_NIMASK (*((volatile uint32_t *)((MC9328MXL_AITC_BASE) + 0x04))) +#define MC9328MXL_AITC_INTENNUM (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x08))) +#define MC9328MXL_AITC_INTDISNUM (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x0c))) +#define MC9328MXL_AITC_INTENABLEH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x10))) +#define MC9328MXL_AITC_INTENABLEL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x14))) +#define MC9328MXL_AITC_INTTYPEH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x18))) +#define MC9328MXL_AITC_INTTYPEL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x1c))) +#define MC9328MXL_AITC_NIPIR7 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x20))) +#define MC9328MXL_AITC_NIPRI6 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x24))) +#define MC9328MXL_AITC_NIPRI5 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x28))) +#define MC9328MXL_AITC_NIPRI4 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x2c))) +#define MC9328MXL_AITC_NIPRI3 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x30))) +#define MC9328MXL_AITC_NIPRI2 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x34))) +#define MC9328MXL_AITC_NIPRI1 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x38))) +#define MC9328MXL_AITC_NIPRI0 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x3c))) +#define MC9328MXL_AITC_NIVECSR (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x40))) +#define MC9328MXL_AITC_FIVECSR (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x44))) +#define MC9328MXL_AITC_INTSRCH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x48))) +#define MC9328MXL_AITC_INTSRCL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x4c))) +#define MC9328MXL_AITC_INTFRCH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x50))) +#define MC9328MXL_AITC_INTFRCL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x54))) +#define MC9328MXL_AITC_NIPNDH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x58))) +#define MC9328MXL_AITC_NIPNDL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x5c))) +#define MC9328MXL_AITC_FIPNDH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x60))) +#define MC9328MXL_AITC_FIPNDL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x64))) + +#define MC9328MXL_INT_UART3_PFERR (0) +#define MC9328MXL_INT_UART3_RTS (1) +#define MC9328MXL_INT_UART3_DTR (2) +#define MC9328MXL_INT_UART3_UARTC (3) +#define MC9328MXL_INT_UART3_TX (4) +#define MC9328MXL_INT_PEN_UP (5) +#define MC9328MXL_INT_CSI (6) +#define MC9328MXL_INT_MMA_MAC (7) +#define MC9328MXL_INT_MMA (8) +#define MC9328MXL_INT_COMP (9) +#define MC9328MXL_INT_MSIRQ (10) +#define MC9328MXL_INT_GPIO_PORTA (11) +#define MC9328MXL_INT_GPIO_PORTB (12) +#define MC9328MXL_INT_GPIO_PORTC (13) +#define MC9328MXL_INT_LCDC (14) +#define MC9328MXL_INT_SIM_IRQ (15) +#define MC9328MXL_INT_SIM_DATA (16) +#define MC9328MXL_INT_RTC (17) +#define MC9328MXL_INT_RTC_SAM (18) +#define MC9328MXL_INT_UART2_PFERR (19) +#define MC9328MXL_INT_UART2_RTS (20) +#define MC9328MXL_INT_UART2_DTR (21) +#define MC9328MXL_INT_UART2_UARTC (22) +#define MC9328MXL_INT_UART2_TX (23) +#define MC9328MXL_INT_UART2_RX (24) +#define MC9328MXL_INT_UART1_PFERR (25) +#define MC9328MXL_INT_UART1_RTS (26) +#define MC9328MXL_INT_UART1_DTR (27) +#define MC9328MXL_INT_UART1_UARTC (28) +#define MC9328MXL_INT_UART1_TX (29) +#define MC9328MXL_INT_UART1_RX (30) +#define MC9328MXL_INT_PEN_DATA (33) +#define MC9328MXL_INT_PWM (34) +#define MC9328MXL_INT_MMC_IRQ (35) +#define MC9328MXL_INT_SSI2_TX (36) +#define MC9328MXL_INT_SSI2_RX (37) +#define MC9328MXL_INT_SSI2_ERR (38) +#define MC9328MXL_INT_I2C (39) +#define MC9328MXL_INT_SPI2 (40) +#define MC9328MXL_INT_SPI1 (41) +#define MC9328MXL_INT_SSI_TX (42) +#define MC9328MXL_INT_SSI_TX_ERR (43) +#define MC9328MXL_INT_SSI_RX (44) +#define MC9328MXL_INT_SSI_RX_ERR (45) +#define MC9328MXL_INT_TOUCH (46) +#define MC9328MXL_INT_USBD0 (47) +#define MC9328MXL_INT_USBD1 (48) +#define MC9328MXL_INT_USBD2 (49) +#define MC9328MXL_INT_USBD3 (50) +#define MC9328MXL_INT_USBD4 (51) +#define MC9328MXL_INT_USBD5 (52) +#define MC9328MXL_INT_USBD6 (53) +#define MC9328MXL_INT_UART3_RX (54) +#define MC9328MXL_INT_BTSYS (55) +#define MC9328MXL_INT_BTTIM (56) +#define MC9328MXL_INT_BTWUI (57) +#define MC9328MXL_INT_TIMER2 (58) +#define MC9328MXL_INT_TIMER1 (59) +#define MC9328MXL_INT_DMA_ERR (60) +#define MC9328MXL_INT_DMA (61) +#define MC9328MXL_INT_GPIO_PORTD (62) +#define MC9328MXL_INT_WDT (63) + +#define MC9328MXL_AITC_INTCTL_NIAD BIT(20) +#define MC9328MXL_AITC_INTCTL_FIAD BIT(19) +#define MC9328MXL_AITC_NIMASK_MASK (0X1F) +#define MC9328MXL_AITC_INTENNUM_MASK (0X3F) +#define MC9328MXL_AITC_INTDISNUM_MASK (0X3F) +#define MC9328MXL_AITC_NIPRIORITY(_int_, _pri_) \ + (((_pri_) & 0xf) << ((_int_) & 0x7) * 4) + + +#endif /* __MC9328MXL_H__ */ diff --git a/bsps/arm/csb336/include/tm27.h b/bsps/arm/csb336/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/csb336/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/csb337/headers.am b/bsps/arm/csb337/headers.am new file mode 100644 index 0000000000..4fff8adeac --- /dev/null +++ b/bsps/arm/csb337/headers.am @@ -0,0 +1,21 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200_dbgu.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200_emac.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200_gpio.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200_mem.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200_pmc.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200_usart.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/bits.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/font8x16.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/sed1356.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/sed1356_16bit.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/csb337/include/bsp/irq.h diff --git a/bsps/arm/csb337/include/at91rm9200.h b/bsps/arm/csb337/include/at91rm9200.h new file mode 100644 index 0000000000..3ed64c7073 --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200.h @@ -0,0 +1,344 @@ +/* + * Atmel AT91RM9200 Register definitions, used in KIT637_V6 (CSB637) + * + * Copyright (c) 2003 by Cogent Computer Systems + * Written by Mike Kelly + * + * Modified by Fernando Nicodemos + * from NCB - Sistemas Embarcados Ltda. (Brazil) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ + + +#ifndef __AT91RM9200_H__ +#define __AT91RM9200_H__ + +#include "bits.h" + +typedef volatile unsigned long vulong; + +/* Source Mode Register - 32 of them */ +#define AIC_SMR_BASE 0xFFFFF000 +#define AIC_SMR_REG(_x_) *(vulong *)(AIC_SMR_BASE + (_x_ & 0x7c)) + +/* Source Vector Register - 32 of them */ +#define AIC_SVR_BASE 0xFFFFF080 +#define AIC_SVR_REG(_x_) *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c)) + +/* Control Register - 32 of them */ +#define AIC_CTL_BASE 0xFFFFF100 +#define AIC_CTL_REG(_x_) *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f)) + +/* Register Offsets */ +/* offsets from AIC_SMR_BASE and AIC_SVR_BASE */ +#define AIC_SMR_FIQ 0x00 /* Advanced Interrupt Controller FIQ */ +#define AIC_SMR_SYSIRQ 0x04 /* Advanced Interrupt Controller SYSIRQ */ +#define AIC_SMR_PIOA 0x08 /* Parallel I/O Controller A */ +#define AIC_SMR_PIOB 0x0c /* Parallel I/O Controller B */ +#define AIC_SMR_PIOC 0x10 /* Parallel I/O Controller C */ +#define AIC_SMR_PIOD 0x14 /* Parallel I/O Controller D */ +#define AIC_SMR_US0 0x18 /* USART 0 */ +#define AIC_SMR_US1 0x1c /* USART 1 */ +#define AIC_SMR_US2 0x20 /* USART 2 */ +#define AIC_SMR_US3 0x24 /* USART 3 */ +#define AIC_SMR_MCI 0x28 /* Multimedia Card Interface */ +#define AIC_SMR_UDP 0x2c /* USB Device Port */ +#define AIC_SMR_TWI 0x30 /* Two-wire Interface */ +#define AIC_SMR_SPI 0x34 /* Serial Peripheral Interface */ +#define AIC_SMR_SSC0 0x38 /* Synchronous Serial Controller 0 */ +#define AIC_SMR_SSC1 0x3c /* Synchronous Serial Controller 1 */ +#define AIC_SMR_SSC2 0x40 /* Synchronous Serial Controller 2 */ +#define AIC_SMR_TC0 0x44 /* Timer/Counter 0 */ +#define AIC_SMR_TC1 0x48 /* Timer/Counter 1 */ +#define AIC_SMR_TC2 0x4c /* Timer/Counter 2 */ +#define AIC_SMR_TC3 0x50 /* Timer/Counter 3 */ +#define AIC_SMR_TC4 0x54 /* Timer/Counter 4 */ +#define AIC_SMR_TC5 0x58 /* Timer/Counter 5 */ +#define AIC_SMR_UHP 0x5c /* USB Host Port */ +#define AIC_SMR_EMAC 0x60 /* Ethernet MAC */ +#define AIC_SMR_IRQ0 0x64 /* Advanced Interrupt Controller IRQ0 */ +#define AIC_SMR_IRQ1 0x68 /* Advanced Interrupt Controller IRQ1 */ +#define AIC_SMR_IRQ2 0x6c /* Advanced Interrupt Controller IRQ2 */ +#define AIC_SMR_IRQ3 0x70 /* Advanced Interrupt Controller IRQ3 */ +#define AIC_SMR_IRQ4 0x74 /* Advanced Interrupt Controller IRQ4 */ +#define AIC_SMR_IRQ5 0x78 /* Advanced Interrupt Controller IRQ5 */ +#define AIC_SMR_IRQ6 0x7c /* Advanced Interrupt Controller IRQ6 */ + +/* from AIC_CTL_BASE */ +#define AIC_IVR 0x00 /* IRQ Vector Register */ +#define AIC_FVR 0x04 /* FIQ Vector Register */ +#define AIC_ISR 0x08 /* Interrupt Status Register */ +#define AIC_IPR 0x0C /* Interrupt Pending Register */ +#define AIC_IMR 0x10 /* Interrupt Mask Register */ +#define AIC_CISR 0x14 /* Core Interrupt Status Register */ +#define AIC_IECR 0x20 /* Interrupt Enable Command Register */ +#define AIC_IDCR 0x24 /* Interrupt Disable Command Register */ +#define AIC_ICCR 0x28 /* Interrupt Clear Command Register */ +#define AIC_ISCR 0x2C /* Interrupt Set Command Register */ +#define AIC_EOICR 0x30 /* End of Interrupt Command Register */ +#define AIC_SPU 0x34 /* Spurious Vector Register */ +#define AIC_DCR 0x38 /* Debug Control Register (Protect) */ +#define AIC_FFER 0x40 /* Fast Forcing Enable Register */ +#define AIC_FFDR 0x44 /* Fast Forcing Disable Register */ +#define AIC_FFSR 0x48 /* Fast Forcing Status Register */ + +/* Bit Defines */ +/* AIC_ISR - Interrupt Status Register */ +#define AIC_ISR_IRQID_MASK 0x1f /* current interrupt ID */ + +/* AIC_CISR - Core Interrupt Status Register */ +#define AIC_CISR_IRQ BIT1 /* 1 = Core IRQ is active */ +#define AIC_CISR_FIQ BIT0 /* 1 = Core FIQ is active */ + +/* AIC_DCR - Debug Control Register (Protect) */ +#define AIC_DCR_GMSK BIT1 /* 0 = AIC controls IRQ and FIQ */ +#define AIC_DCR_PROT BIT0 /* 1 = enable protection mode */ + +/* AIC_SMR */ +#define AIC_SMR_PRIOR(_x_) ((_x_ & 0x07) << 0) +#define AIC_SMR_SRC_LVL_LOW (0 << 5) /* Are these right? docs don't say which is high/low */ +#define AIC_SMR_SRC_EDGE_LOW (1 << 5) +#define AIC_SMR_SRC_LVL_HI (2 << 5) +#define AIC_SMR_SRC_EDGE_HI (3 << 5) + +/**************************************************************************/ +/* Debug Unit */ +/**************************************************************************/ +#define DBGU_BASE 0xFFFFF200 +#define DBGU_REG(_x_) *(vulong *)(DBGU_BASE + _x_) + +/* Register Offsets */ +#define DBGU_CR 0x00 /* Control Register */ +#define DBGU_MR 0x04 /* Mode Register */ +#define DBGU_IER 0x08 /* Interrupt Enable Register */ +#define DBGU_IDR 0x0C /* Interrupt Disable Register */ +#define DBGU_IMR 0x10 /* Interrupt Mask Register */ +#define DBGU_CSR 0x14 /* Channel Status Register */ +#define DBGU_RHR 0x18 /* Receiver Holding Register */ +#define DBGU_THR 0x1C /* Transmitter Holding Register */ +#define DBGU_BRGR 0x20 /* Baud Rate Generator Register */ +#define DBGU_C1R 0x40 /* Chip ID1 Register */ +#define DBGU_C2R 0x44 /* Chip ID2 Register */ +#define DBGU_FNTR 0x48 /* Force NTRST Register */ + +/**************************************************************************/ +/* USART 0-3 */ +/**************************************************************************/ +#define USART0_BASE 0xFFFC0000 +#define USART1_BASE 0xFFFC4000 +#define USART2_BASE 0xFFFC8000 +#define USART3_BASE 0xFFFCC000 +/* + * WARNING: The USART3_BASE at the AT91RM9200 Manual is wrong!!! + * Manual revision: Rev. 1768H-ATARM–16-Jun-09 + * USART3_BASE is NOT 0xFFECC000 + */ + +/****************/ +/* System Timer */ +/****************/ +#define ST_BASE 0xFFFFFD00 +#define ST_REG(_x_) *(vulong *)(ST_BASE + _x_) + +/* Register Offsets */ +#define ST_CR 0x00 /* Control Register */ +#define ST_PIMR 0x04 /* Period Interval Mode Register */ +#define ST_WDMR 0x08 /* Watchdog Mode Register */ +#define ST_RTMR 0x0C /* Real-time Mode Register */ +#define ST_SR 0x10 /* Status Register */ +#define ST_IER 0x14 /* Interrupt Enable Register */ +#define ST_IDR 0x18 /* Interrupt Disable Register */ +#define ST_IMR 0x1C /* Interrupt Mask Register */ +#define ST_RTAR 0x20 /* Real-time Alarm Register */ +#define ST_CRTR 0x24 /* Current Real-time Register */ + +/* Bit Defines */ +/* ST_CR - Control Register */ +#define ST_CR_WDRST BIT0 /* write 1 to reload WD counter */ + +/* ST_PIMR - Period Interval Mode Register */ +#define ST_PIMR_PIV_MASK 0x0000ffff + +/* ST_WDMR - Watchdog Mode Register */ +#define ST_WDMR_EXTEN BIT17 /* WDOVF is not implemented on AT91RM9200 */ +#define ST_WDMR_RSTEN BIT16 /* 1 = reset the AT91RM9200 when WD overflows */ +#define ST_WDMR_WDV_MASK 0x0000ffff /* WD counter is in the lower 16-bits */ + +/* ST_RTMR - Real-time Mode Register */ +#define ST_RTMR_RTPRES_MASK 0x0000ffff /* Real-Time Prescaler */ + +/* ST_SR - Status Register - Read Only */ +/* ST_IER - Interrupt Enable Register - Write Only */ +/* ST_IDR - Interrupt Disable Register - Write Only */ +/* ST_IMR - Interrupt Mask Register - Read Only */ +#define ST_SR_ALMS BIT3 +#define ST_SR_RTTINC BIT2 +#define ST_SR_WDOVF BIT1 +#define ST_SR_PITS BIT0 + +/* ST_RTAR - Real-time Alarm Register */ +#define ST_RTAR_ALMV_MASK 0x000fffff + +/* ST_CRTR - Current Real-time Register */ +#define ST_CRTR_CRTV_MASK 0x000fffff + + +/************************************************************************** + * Peripheral Data Control (DMA) + * Note that each of the following peripherals has it's own + * set of these registers starting at offset 0x100 from it's + * base address: DBGU, SPI, USART and SSC + * To access the DMA for a peripheral, use the macro for that + * peripheral but with these register offsets + **************************************************************************/ +/* Register Offsets */ +#define PDC_RPR 0x100 /* Receive Pointer Register */ +#define PDC_RCR 0x104 /* Receive Counter Register */ +#define PDC_TPR 0x108 /* Transmit Pointer Register */ +#define PDC_TCR 0x10c /* Transmit Counter Register */ +#define PDC_RNPR 0x110 /* Receive Next Pointer Register */ +#define PDC_RNCR 0x114 /* Receive Next Counter Register */ +#define PDC_TNPR 0x118 /* Transmit Next Pointer Register */ +#define PDC_TNCR 0x11c /* Transmit Next Counter Register */ +#define PDC_PTCR 0x120 /* PDC Transfer Control Register */ +#define PDC_PTSR 0x124 /* PDC Transfer Status Register */ + +/************************************************************************** + * Parallel I/O Unit + * There are four PIO blocks - A, B, C and D. They all have the + * same register set, but different base addresses + **************************************************************************/ +/* Port A */ +#define PIOA_BASE 0xFFFFF400 +#define PIOA_REG(_x_) *(vulong *)(PIOA_BASE + _x_) + +/* Port B */ +#define PIOB_BASE 0xFFFFF600 +#define PIOB_REG(_x_) *(vulong *)(PIOB_BASE + _x_) + +/* Port C */ +#define PIOC_BASE 0xFFFFF800 +#define PIOC_REG(_x_) *(vulong *)(PIOC_BASE + _x_) + +/* Port D */ +#define PIOD_BASE 0xFFFFFA00 +#define PIOD_REG(_x_) *(vulong *)(PIOD_BASE + _x_) + +/************************************************************************** + * Power Management and Clock Control + *************************************************************************/ +#define PMC_BASE 0xFFFFFC00 +#define PMC_REG(_x_) *(vulong *)(PMC_BASE + _x_) + +/************************************************************************** + * MAC Unit + *************************************************************************/ +#define EMAC_BASE 0xFFFBC000 +#define EMAC_REG(_x_) *(vulong *)(EMAC_BASE + _x_) + +/************************************************************************** + * Timer/Counter Unit + **************************************************************************/ +#define TC_BASE 0xFFFA0000 +#define TC_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_) +#define TC_TC0_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_) +#define TC_TC1_REG(_x_) *(vulong *)(TC_BASE + 0x40 + _x_) +#define TC_TC2_REG(_x_) *(vulong *)(TC_BASE + 0x80 + _x_) + +/* Offsets from TC_TC?_REG */ +#define TC_CCR 0x00 /* Channel Control Register */ +#define TC_CMR 0x04 /* Channel Mode Register */ +#define TC_CV 0x10 /* Counter Value */ +#define TC_RA 0x14 /* Register A */ +#define TC_RB 0x18 /* Register B */ +#define TC_RC 0x1C /* Register C */ +#define TC_SR 0x20 /* Status Register */ +#define TC_IER 0x24 /* Interrupt Enable Register */ +#define TC_IDR 0x28 /* Interrupt Disable Register */ +#define TC_IMR 0x2C /* Interrupt Mask Register */ + +/* Offsets from TC_BASE */ +#define TC_BCR 0xc0 /* Channel Control Register */ +#define TC_BMR 0xc4 /* Channel Control Register */ + +/* Block control register */ +#define TC_BCR_SYNC BIT1 /* Set to syncronize channels */ + +/* Block mode register */ +#define TC_BMR_TC0(_x_) ((_x_ & 0x3) << 0) /* TC0 clock source */ +#define TC_BMR_TC1(_x_) ((_x_ & 0x3) << 2) /* TC1 clock source */ +#define TC_BMR_TC2(_x_) ((_x_ & 0x3) << 4) /* TC2 clock source */ + +/* Channel Control register */ +#define TC_CCR_CLKEN BIT0 /* Enable clock */ +#define TC_CCR_CLKDIS BIT1 /* Disable clock */ +#define TC_CCR_SWTRG BIT2 /* Software trigger command */ + +/* Channel mode register */ +#define TC_CMR_TCCLKS(_x_) ((_x_ & 0x7) << 0) /* Clock source */ +#define TC_CMR_CLKI BIT3 /* Clock invert */ +#define TC_BURST(_x_) ((_x_ & 0x3 << 4) /* Burst signal selection */ +#define TC_WAVE BIT15 /* 0 for catpure, 1 for wave */ + +/* Channel mode register - capture mode (TC_WAVE = 0) */ +#define TC_CMR_LDBSTOP BIT6 /* Set to stop clock when RB loads */ +#define TC_CMR_LDBDIS BIT7 /* Set to disable clock when RB loads */ +#define TC_CMR_ETRGEDG(_x_) ((_x_ & 0x3) << 8) /* Select edge triggering mode */ +#define TC_CMR_ABETRG BIT10 /* Select ext trigger source */ +#define TC_CMR_CPCTRG BIT14 /* RC Compare trigger enable */ +#define TC_CMR_LDRA(_x_) ((_x_ & 0x3) << 16) /* RA loading selection */ +#define TC_CMR_LDRB(_x_) ((_x_ & 0x3) << 18) /* RB loading selection */ + +/* Channel mode register - wave mode (TC_WAVE = 1) */ +#define TC_CMR_CPCSTOP BIT6 /* Clock stopped w/ RC compare */ +#define TC_CMR_CPCDIS BIT7 /* Clock disabled w/ RC compare */ +#define TC_CMR_EEVTEDG(_x_) ((_x_ & 0x3) << 8) /* Ext event edge selection */ +#define TC_CMR_EEVT(_x_) ((_x_ & 0x3) << 10) /* Ext event selection */ +#define TC_CMR_ENETRG BIT12 /* Ext event trigger enable */ +#define TC_CMR_WAVESEL(_x_) ((_x_ & 0x3) << 13) /* Waveform selection */ +#define TC_CMR_ACPA(_x_) ((_x_ & 0x3) << 16) /* RA compare effect on TIOA */ +#define TC_CMR_ACPC(_x_) ((_x_ & 0x3) << 18) /* RC compare effect on TIOA */ +#define TC_CMR_AEEVT(_x_) ((_x_ & 0x3) << 20) /* Ext event effect on TIOA */ +#define TC_CMR_ASWTRG(_x_) ((_x_ & 0x3) << 22) /* SW trigger effect on TIOA */ +#define TC_CMR_BCPB(_x_) ((_x_ & 0x3) << 24) /* RB compare effect on TIOB */ +#define TC_CMR_BCPC(_x_) ((_x_ & 0x3) << 26) /* RC compare effect on TIOB */ +#define TC_CMR_BEEVT(_x_) ((_x_ & 0x3) << 28) /* Ext event effect on TIOB */ +#define TC_CMR_BSWTRG(_x_) ((_x_ & 0x3) << 30) /* SW trigger effect on TIOB */ + +/* Counter value */ +#define TC_CV_MASK 0xffff /* Timer counter mask */ + +/* Status, Interrupt enable, Interrupt disable, and Interrupt mask registers */ +#define TC_SR_COVFS BIT0 /* Counter overflow status */ +#define TC_SR_LOVRS BIT1 /* Load overrun status */ +#define TC_SR_CPAS BIT2 /* RA compare status */ +#define TC_SR_CPBS BIT3 /* RB compare status */ +#define TC_SR_CPCS BIT4 /* RC compare status */ +#define TC_SR_LDRAS BIT5 /* RA loading status */ +#define TC_SR_LDRBS BIT6 /* RB loading status */ +#define TC_SR_ETRGS BIT7 /* External trigger status */ +#define TC_SR_CLKSTA BIT16 /* Clock enabling status */ +#define TC_SR_MTIOA BIT17 /* TIOA Mirror */ +#define TC_SR_MTIOB BIT18 /* TIOB Mirror */ + +/*************************************************************************** + * External Bus Interface Unit + **************************************************************************/ +#define EBI_BASE 0xFFFFFF60 +#define EBI_REG(_x_) *(vulong *)(EBI_BASE + _x_) + +/*************************************************************************** + * Static Memory Interface Unit + ***************************************************************************/ +#define SMC_REG(_x_) *(vulong *)(EBI_BASE + 0x10 + _x_) + +/************************************************************************** + * SDRAM Memory Interface Unit + **************************************************************************/ +#define SDRC_REG(_x_) *(vulong *)(EBI_BASE + 0x30 + _x_) + +#endif /* __AT91RM9200_H__ */ + diff --git a/bsps/arm/csb337/include/at91rm9200_dbgu.h b/bsps/arm/csb337/include/at91rm9200_dbgu.h new file mode 100644 index 0000000000..9a65483db0 --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200_dbgu.h @@ -0,0 +1,89 @@ +/* + * Atmel AT91RM9200_DBGU Register definitions + * + * Copyright (c) 2003 by Cogent Computer Systems + * Written by Mike Kelly + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __AT91RM9200_DBGU_H__ +#define __AT91RM9200_DBGU_H__ + +#include "bits.h" + +/* Register Offsets */ +#define DBGU_CR 0x00 /* Control Register */ +#define DBGU_MR 0x04 /* Mode Register */ +#define DBGU_IER 0x08 /* Interrupt Enable Register */ +#define DBGU_IDR 0x0C /* Interrupt Disable Register */ +#define DBGU_IMR 0x10 /* Interrupt Mask Register */ +#define DBGU_SR 0x14 /* Channel Status Register */ +#define DBGU_RHR 0x18 /* Receiver Holding Register */ +#define DBGU_THR 0x1C /* Transmitter Holding Register */ +#define DBGU_BRGR 0x20 /* Baud Rate Generator Register */ +#define DBGU_C1R 0x40 /* Chip ID1 Register */ +#define DBGU_C2R 0x44 /* Chip ID2 Register */ +#define DBGU_FNTR 0x48 /* Force NTRST Register */ + +/* Bit Defines */ +/* Control Register, DBGU_CR, Offset 0x00 */ +#define DBGU_CR_RSTRX BIT2 /* 1 = Reset and disable receiver */ +#define DBGU_CR_RSTTX BIT3 /* 1 = Reset and disable transmitter */ +#define DBGU_CR_RXEN BIT4 /* 1 = Receiver enable */ +#define DBGU_CR_RXDIS BIT5 /* 1 = Receiver disable */ +#define DBGU_CR_TXEN BIT6 /* 1 = Transmitter enable */ +#define DBGU_CR_TXDIS BIT7 /* 1 = Transmitter disable */ +#define DBGU_CR_RSTSTA BIT8 /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */ + +/* Mode Register. DBGU_MR. Offset 0x04 */ +#define DBGU_MR_PAR_EVEN (0x0 << 9) /* Even Parity */ +#define DBGU_MR_PAR_ODD (0x1 << 9) /* Odd Parity */ +#define DBGU_MR_PAR_SPACE (0x2 << 9) /* Parity forced to 0 (Space) */ +#define DBGU_MR_PAR_MARK (0x3 << 9) /* Parity forced to 1 (Mark) */ +#define DBGU_MR_PAR_NONE (0x4 << 9) /* No Parity */ +#define DBGU_MR_PAR_MDROP (0x6 << 9) /* Multi-drop mode */ +#define DBGU_MR_CHMODE_NORM (0x0 << 14) /* Normal Mode */ +#define DBGU_MR_CHMODE_AUTO (0x1 << 14) /* Auto Echo: RXD drives TXD */ +#define DBGU_MR_CHMODE_LOC (0x2 << 14) /* Local Loopback: TXD drives RXD */ +#define DBGU_MR_CHMODE_REM (0x3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */ + +/* Interrupt Enable Register, DBGU_IER, Offset 0x08 */ +/* Interrupt Disable Register, DBGU_IDR, Offset 0x0C */ +/* Interrupt Mask Register, DBGU_IMR, Offset 0x10 */ +/* Channel Status Register, DBGU_SR, Offset 0x14 */ +#define DBGU_INT_RXRDY BIT0 /* RXRDY Interrupt */ +#define DBGU_INT_TXRDY BIT1 /* TXRDY Interrupt */ +#define DBGU_INT_ENDRX BIT3 /* End of Receive Transfer Interrupt */ +/*efine DBGU_INT_ENDTX BIT4 /* End of Transmit Interrupt */ +#define DBGU_INT_OVRE BIT5 /* Overrun Interrupt */ +#define DBGU_INT_FRAME BIT6 /* Framing Error Interrupt */ +#define DBGU_INT_PARE BIT7 /* Parity Error Interrupt */ +#define DBGU_INT_TXEMPTY BIT9 /* TXEMPTY Interrupt */ +#define DBGU_INT_TXBUFE BIT11 /* TXBUFE Interrupt */ +#define DBGU_INT_RXBUFF BIT12 /* RXBUFF Interrupt */ +#define DBGU_INT_COMM_TX BIT30 /* COMM_TX Interrupt */ +#define DBGU_INT_COMM_RX BIT31 /* COMM_RX Interrupt */ +#define DBGU_INT_ALL 0xC0001AFB /* all assigned bits */ + +/* FORCE_NTRST Register, DBGU_FNTR, Offset 0x48 */ +#define DBGU_FNTR_NTRST BIT0 /* 1 = Force NTRST low in JTAG */ + +typedef struct { + volatile uint32_t cr; + volatile uint32_t mr; + volatile uint32_t ier; + volatile uint32_t idr; + volatile uint32_t imr; + volatile uint32_t sr; + volatile uint32_t rhr; + volatile uint32_t thr; + volatile uint32_t brgr; + volatile uint32_t _res0[7]; + volatile uint32_t cidr; + volatile uint32_t exid; + volatile uint32_t fnr; +} at91rm9200_dbgu_regs_t; + +#endif /* __AT91RM9200_DBGU_H__ */ diff --git a/bsps/arm/csb337/include/at91rm9200_emac.h b/bsps/arm/csb337/include/at91rm9200_emac.h new file mode 100644 index 0000000000..77c42d1526 --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200_emac.h @@ -0,0 +1,160 @@ +/* + * Atmel AT91RM9200 EMAC Register definitions + * + * Copyright (c) 2003 by Cogent Computer Systems + * Written by Mike Kelly + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __AT91RM9200_EMAC_H__ +#define __AT91RM9200_EMAC_H__ + +#include + +/*Register offsets */ +#define EMAC_CTL 0x00 /* Network Control Register */ +#define EMAC_CFG 0x04 /* Network Configuration Register */ +#define EMAC_SR 0x08 /* Network Status Register */ +#define EMAC_TAR 0x0C /* Transmit Address Register */ +#define EMAC_TCR 0x10 /* Transmit Control Register */ +#define EMAC_TSR 0x14 /* Transmit Status Register */ +#define EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ +#define EMAC_RSR 0x20 /* Receive Status Register */ +#define EMAC_ISR 0x24 /* Interrupt Enable Register */ +#define EMAC_IER 0x28 /* Interrupt Enable Register */ +#define EMAC_IDR 0x2C /* Interrupt Disable Register */ +#define EMAC_IMR 0x30 /* Interrupt Mask Register */ +#define EMAC_MAN 0x34 /* PHY Maintenance Register */ +#define EMAC_FRA 0x40 /* Frames Transmitted OK Register */ +#define EMAC_SCOL 0x44 /* Single Collision Frame Register */ +#define EMAC_MCOL 0x48 /* Multiple Collision Frame Register */ +#define EMAC_OK 0x4C /* Frames Received OK Register */ +#define EMAC_SEQE 0x50 /* Frame Check Sequence Error Register */ +#define EMAC_ALE 0x54 /* Alignment Error Register */ +#define EMAC_DTE 0x58 /* Deferred Transmission Frame Register */ +#define EMAC_LCOL 0x5C /* Late Collision Register */ +#define EMAC_ECOL 0x60 /* Excessive Collision Register */ +#define EMAC_CSE 0x64 /* Carrier Sense Error Register */ +#define EMAC_TUE 0x68 /* Transmit Underrun Error Register */ +#define EMAC_CDE 0x6C /* Code Error Register */ +#define EMAC_ELR 0x70 /* Excessive Length Error Register */ +#define EMAC_RJB 0x74 /* Receive Jabber Register */ +#define EMAC_USF 0x78 /* Undersize Frame Register */ +#define EMAC_SQEE 0x7C /* SQE Test Error Register */ +#define EMAC_DRFC 0x80 /* Discarded RX Frame Register */ +#define EMAC_HSH 0x90 /* Hash Address High[63:32] */ +#define EMAC_HSL 0x94 /* Hash Address Low[31:0] */ +#define EMAC_SA1L 0x98 /* Specific Addr 1 Low, First 4 bytes */ +#define EMAC_SA1H 0x9C /* Specific Addr 1 High, Last 2 bytes */ +#define EMAC_SA2L 0xA0 /* Specific Addr 2 Low, First 4 bytes */ +#define EMAC_SA2H 0xA4 /* Specific Addr 2 High, Last 2 bytes */ +#define EMAC_SA3L 0xA8 /* Specific Addr 3 Low, First 4 bytes */ +#define EMAC_SA3H 0xAC /* Specific Addr 3 High, Last 2 bytes */ +#define EMAC_SA4L 0xB0 /* Specific Addr 4 Low, First 4 bytes */ +#define EMAC_SA4H 0xB4 /* Specific Addr 4 High, Last 2 bytesr */ + +/* Control Register, EMAC_CTL, Offset 0x0 */ +#define EMAC_CTL_LB BIT0 /* 1 = Set Loopback output signal */ +#define EMAC_CTL_LBL BIT1 /* 1 = Loopback local. */ +#define EMAC_CTL_RE BIT2 /* 1 = Receive enable. */ +#define EMAC_CTL_TE BIT3 /* 1 = Transmit enable. */ +#define EMAC_CTL_MPE BIT4 /* 1 = Management port enable. */ +#define EMAC_CTL_CSR BIT5 /* Write 1 to clear stats registers. */ +#define EMAC_CTL_ISR BIT6 /* Write to increment stats registers */ +#define EMAC_CTL_WES BIT7 /* 1 = Enable writing to stats regs */ +#define EMAC_CTL_BP BIT8 /* 1 = Force collision on all RX frames */ + +/* Configuration Register, EMAC_CFG, Offset 0x4 */ +#define EMAC_CFG_SPD BIT0 /* 1 = 10/100 Speed (not functional?) */ +#define EMAC_CFG_FD BIT1 /* 1 = Full duplex. */ +#define EMAC_CFG_BR BIT2 /* write 0 */ +#define EMAC_CFG_CAF BIT4 /* 1 = accept all frames */ +#define EMAC_CFG_NBC BIT5 /* 1 = disable reception of bcast frms */ +#define EMAC_CFG_MTI BIT6 /* 1 = Multicast hash enable */ +#define EMAC_CFG_UNI BIT7 /* 1 = Unicast hash enable. */ +#define EMAC_CFG_BIG BIT8 /* 1 = enable reception 1522 byte frms */ +#define EMAC_CFG_EAE BIT9 /* write 0 */ +#define EMAC_CFG_CLK_8 (0 << 10) /* MII Clock = HCLK divided by 8 */ +#define EMAC_CFG_CLK_16 (1 << 10) /* MII Clock = HCLK divided by 16 */ +#define EMAC_CFG_CLK_32 (2 << 10) /* MII Clock = HCLK divided by 32 */ +#define EMAC_CFG_CLK_64 (3 << 10) /* MII Clock = HCLK divided by 64 */ +#define EMAC_CFG_CLK_MASK (3 << 10) /* MII Clock mask */ +#define EMAC_CFG_RTY BIT12 /* Retry Test Mode - Must be 0 */ +#define EMAC_CFG_RMII BIT13 /* Reduced MII Mode Enable */ + +/* Status Register, EMAC_SR, Offset 0x8 */ +#define EMAC_LINK BIT0 /* Link pin */ +#define EMAC_MDIO BIT1 /* Real Time state of MDIO pin */ +#define EMAC_IDLE BIT2 /* 0 = PHY Logic is idle */ + +/* Transmit Control Register, EMAC_TCR, Offset 0x10 */ +#define EMAC_TCR_LEN(_x_) ((_x_ & 0x7FF) << 0) /* Tx frame len minus CRC */ +#define EMAC_TCR_NCRC BIT15 /* Do'nt append CRC on Tx */ + +/* Transmit Status Register, EMAC_TSR, Offset 0x14 */ +#define EMAC_TSR_OVR BIT0 /* 1 = Transmit buffer overrun */ +#define EMAC_TSR_COL BIT1 /* 1 = Collision occured */ +#define EMAC_TSR_RLE BIT2 /* 1 = Retry lmimt exceeded */ +#define EMAC_TSR_TXIDLE BIT3 /* 1 = Transmitter is idle */ +#define EMAC_TSR_BNQ BIT4 /* 1 = Transmit buffer not queued */ +#define EMAC_TSR_COMP BIT5 /* 1 = Transmit complete */ +#define EMAC_TSR_UND BIT6 /* 1 = Transmit underrun */ + +/* Receive Status Register, EMAC_RSR, Offset 0x20 */ +#define EMAC_RSR_BNA BIT0 /* 1 = Buffer not available */ +#define EMAC_RSR_REC BIT1 /* 1 = Frame received */ +#define EMAC_RSR_OVR BIT2 /* 1 = Receive overrun */ + +/* + * Interrupt Status Register, EMAC_ISR, Offsen 0x24 + * Interrupt Enable Register, EMAC_IER, Offset 0x28 + * Interrupt Disable Register, EMAC_IDR, Offset 0x2c + * Interrupt Mask Register, EMAC_IMR, Offset 0x30 + */ +#define EMAC_INT_DONE BIT0 /* Phy management done */ +#define EMAC_INT_RCOM BIT1 /* Receive complete */ +#define EMAC_INT_RBNA BIT2 /* Receive buffer not available */ +#define EMAC_INT_TOVR BIT3 /* Transmit buffer overrun */ +#define EMAC_INT_TUND BIT4 /* Transmit buffer underrun */ +#define EMAC_INT_RTRY BIT5 /* Transmit Retry limt */ +#define EMAC_INT_TBRE BIT6 /* Transmit buffer register empty */ +#define EMAC_INT_TCOM BIT7 /* Transmit complete */ +#define EMAC_INT_TIDLE BIT8 /* Transmit idle */ +#define EMAC_INT_LINK BIT9 /* Link pin changed value */ +#define EMAC_INT_ROVR BIT10 /* Receive overrun */ +#define EMAC_INT_ABT BIT11 /* Abort on DMA transfer */ + +/* PHY Maintenance Register, EMAC_MAN, Offset 0x34 */ +#define EMAC_MAN_DATA(_x_) ((_x_ & 0xFFFF) << 0)/* PHY data register */ +#define EMAC_MAN_CODE (0x2 << 16) /* IEEE Code */ +#define EMAC_MAN_REGA(_x_) ((_x_ & 0x1F) << 18) /* PHY register address */ +#define EMAC_MAN_PHYA(_x_) ((_x_ & 0x1F) << 23) /* PHY address */ +#define EMAC_MAN_WRITE (0x1 << 28) /* Transfer is a write */ +#define EMAC_MAN_READ (0x2 << 28) /* Transfer is a read */ +#define EMAC_MAN_HIGH BIT30 /* Must be set */ +#define EMAC_MAN_LOW BIT31 + +/* + * Bit assignments for Receive Buffer Descriptor + * Address - Word 0 + */ +#define RXBUF_ADD_BASE_MASK 0xfffffffc /* Base addr of the rx buf */ +#define RXBUF_ADD_WRAP BIT1 /* set indicates last buf */ +#define RXBUF_ADD_OWNED BIT0 /* 1 = SW owns the pointer */ + +/* Status - Word 1 */ +#define RXBUF_STAT_BCAST BIT31 /* Global bcast addr detected */ +#define RXBUF_STAT_MULTI BIT30 /* Multicast hash match */ +#define RXBUF_STAT_UNI BIT29 /* Unicast hash match */ +#define RXBUF_STAT_EXT BIT28 /* External address (optional) */ +#define RXBUF_STAT_UNK BIT27 /* Unknown source address */ +#define RXBUF_STAT_LOC1 BIT26 /* Local address 1 match */ +#define RXBUF_STAT_LOC2 BIT25 /* Local address 2 match */ +#define RXBUF_STAT_LOC3 BIT24 /* Local address 3 match */ +#define RXBUF_STAT_LOC4 BIT23 /* Local address 4 match */ +#define RXBUF_STAT_LEN_MASK 0x7ff /* Len of frame including FCS */ + +#endif /* __AT91RM9200_EMAC_H__ */ + diff --git a/bsps/arm/csb337/include/at91rm9200_gpio.h b/bsps/arm/csb337/include/at91rm9200_gpio.h new file mode 100644 index 0000000000..9fa18ad476 --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200_gpio.h @@ -0,0 +1,401 @@ +/* + * AT91RM9200 GPIO definitions + * + * Copyright (c) 2002 by Cogent Computer Systems + * Written by Mike Kelly + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef AT91RM9200_GPIO_H +#define AT91RM9200_GPIO_H + +#include + +/* Register Offsets */ +#define PIO_PER 0x00 /* PIO Enable Register */ +#define PIO_PDR 0x04 /* PIO Disable Register */ +#define PIO_PSR 0x08 /* PIO Status Register */ +#define PIO_OER 0x10 /* Output Enable Register */ +#define PIO_ODR 0x14 /* Output Disable Registerr */ +#define PIO_OSR 0x18 /* Output Status Register */ +#define PIO_IFER 0x20 /* Input Filter Enable Register */ +#define PIO_IFDR 0x24 /* Input Filter Disable Register */ +#define PIO_IFSR 0x28 /* Input Filter Status Register */ +#define PIO_SODR 0x30 /* Set Output Data Register */ +#define PIO_CODR 0x34 /* Clear Output Data Register */ +#define PIO_ODSR 0x38 /* Output Data Status Register */ +#define PIO_PDSR 0x3c /* Pin Data Status Register */ +#define PIO_IER 0x40 /* Interrupt Enable Register */ +#define PIO_IDR 0x44 /* Interrupt Disable Register */ +#define PIO_IMR 0x48 /* Interrupt Mask Register */ +#define PIO_ISR 0x4c /* Interrupt Status Register */ +#define PIO_MDER 0x50 /* Multi-driver Enable Register */ +#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ +#define PIO_MDSR 0x58 /* Multi-driver Status Register */ +#define PIO_PUDR 0x60 /* Pull-up Disable Register */ +#define PIO_PUER 0x64 /* Pull-up Enable Register */ +#define PIO_PUSR 0x68 /* Pad Pull-up Status Register */ +#define PIO_ASR 0x70 /* Select A Register */ +#define PIO_BSR 0x74 /* Select B Register */ +#define PIO_ABSR 0x78 /* AB Select Status Register */ +#define PIO_OWER 0xA0 /* Output Write Enable Register */ +#define PIO_OWDR 0xA4 /* Output Write Disable Register */ +#define PIO_OWSR 0xA8 /* Output Write Status Register */ + + +/* + * The AT91RM9200 GPIO's are spread across four 32-bit ports A-D. + * To make it easier to interface with them and to eliminate the need + * to track which GPIO is in which port, we convert the Port x, Bit y + * into a single GPIO number 0 - 127. + * + * Board specific defines will assign the board level signal to a + * virutal GPIO. + * + * PORT A + */ +#define GPIO_0 BIT0 +#define GPIO_1 BIT1 +#define GPIO_2 BIT2 +#define GPIO_3 BIT3 +#define GPIO_4 BIT4 +#define GPIO_5 BIT5 +#define GPIO_6 BIT6 +#define GPIO_7 BIT7 +#define GPIO_8 BIT8 +#define GPIO_9 BIT9 +#define GPIO_10 BIT10 +#define GPIO_11 BIT11 +#define GPIO_12 BIT12 +#define GPIO_13 BIT13 +#define GPIO_14 BIT14 +#define GPIO_15 BIT15 +#define GPIO_16 BIT16 +#define GPIO_17 BIT17 +#define GPIO_18 BIT18 +#define GPIO_19 BIT19 +#define GPIO_20 BIT20 +#define GPIO_21 BIT21 +#define GPIO_22 BIT22 +#define GPIO_23 BIT23 +#define GPIO_24 BIT24 +#define GPIO_25 BIT25 +#define GPIO_26 BIT26 +#define GPIO_27 BIT27 +#define GPIO_28 BIT28 +#define GPIO_29 BIT29 +#define GPIO_30 BIT30 +#define GPIO_31 BIT31 +/* PORT B */ +#define GPIO_32 BIT0 +#define GPIO_33 BIT1 +#define GPIO_34 BIT2 +#define GPIO_35 BIT3 +#define GPIO_36 BIT4 +#define GPIO_37 BIT5 +#define GPIO_38 BIT6 +#define GPIO_39 BIT7 +#define GPIO_40 BIT8 +#define GPIO_41 BIT9 +#define GPIO_42 BIT10 +#define GPIO_43 BIT11 +#define GPIO_44 BIT12 +#define GPIO_45 BIT13 +#define GPIO_46 BIT14 +#define GPIO_47 BIT15 +#define GPIO_48 BIT16 +#define GPIO_49 BIT17 +#define GPIO_50 BIT18 +#define GPIO_51 BIT19 +#define GPIO_52 BIT20 +#define GPIO_53 BIT21 +#define GPIO_54 BIT22 +#define GPIO_55 BIT23 +#define GPIO_56 BIT24 +#define GPIO_57 BIT25 +#define GPIO_58 BIT26 +#define GPIO_59 BIT27 +#define GPIO_60 BIT28 +#define GPIO_61 BIT29 +#define GPIO_62 BIT30 +#define GPIO_63 BIT31 +/* PORT C */ +#define GPIO_64 BIT0 +#define GPIO_65 BIT1 +#define GPIO_66 BIT2 +#define GPIO_67 BIT3 +#define GPIO_68 BIT4 +#define GPIO_69 BIT5 +#define GPIO_70 BIT6 +#define GPIO_71 BIT7 +#define GPIO_72 BIT8 +#define GPIO_73 BIT9 +#define GPIO_74 BIT10 +#define GPIO_75 BIT11 +#define GPIO_76 BIT12 +#define GPIO_77 BIT13 +#define GPIO_78 BIT14 +#define GPIO_79 BIT15 +#define GPIO_80 BIT16 +#define GPIO_81 BIT17 +#define GPIO_82 BIT18 +#define GPIO_83 BIT19 +#define GPIO_84 BIT20 +#define GPIO_85 BIT21 +#define GPIO_86 BIT22 +#define GPIO_87 BIT23 +#define GPIO_88 BIT24 +#define GPIO_89 BIT25 +#define GPIO_90 BIT26 +#define GPIO_91 BIT27 +#define GPIO_92 BIT28 +#define GPIO_93 BIT29 +#define GPIO_94 BIT30 +#define GPIO_95 BIT31 +/* PORT D */ +#define GPIO_96 BIT0 +#define GPIO_97 BIT1 +#define GPIO_98 BIT2 +#define GPIO_99 BIT3 +#define GPIO_100 BIT4 +#define GPIO_101 BIT5 +#define GPIO_102 BIT6 +#define GPIO_103 BIT7 +#define GPIO_104 BIT8 +#define GPIO_105 BIT9 +#define GPIO_106 BIT10 +#define GPIO_107 BIT11 +#define GPIO_108 BIT12 +#define GPIO_109 BIT13 +#define GPIO_110 BIT14 +#define GPIO_111 BIT15 +#define GPIO_112 BIT16 +#define GPIO_113 BIT17 +#define GPIO_114 BIT18 +#define GPIO_115 BIT19 +#define GPIO_116 BIT20 +#define GPIO_117 BIT21 +#define GPIO_118 BIT22 +#define GPIO_119 BIT23 +#define GPIO_120 BIT24 +#define GPIO_121 BIT25 +#define GPIO_122 BIT26 +#define GPIO_123 BIT27 +#define GPIO_124 BIT28 +#define GPIO_125 BIT29 +#define GPIO_126 BIT30 +#define GPIO_127 BIT31 + +/* + * Most of the GPIO pins can have one of two alternate functions + * in addition to being GPIO + * + * Port A, Alternate Function A + */ +#define PIOA_ASR_MISO BIT0 /* SPI Master In (RX), Slave out */ +#define PIOA_ASR_MOSI BIT1 /* SPI Master Out (TX), Slave In */ +#define PIOA_ASR_SPCK BIT2 /* SPI Clock */ +#define PIOA_ASR_NPCS0 BIT3 /* SPI Chip Select 0 */ +#define PIOA_ASR_NPCS1 BIT4 /* SPI Chip Select 1 */ +#define PIOA_ASR_NPCS2 BIT5 /* SPI Chip Select 2 */ +#define PIOA_ASR_NPCS3 BIT6 /* SPI Chip Select 3 */ +#define PIOA_ASR_ETXCK BIT7 /* EMAC TX Clock */ +#define PIOA_ASR_ETXEN BIT8 /* EMAC TXEN */ +#define PIOA_ASR_ETX0 BIT9 /* EMAC TXD0 */ +#define PIOA_ASR_ETX1 BIT10 /* EMAC TXD1 */ +#define PIOA_ASR_ECRS BIT11 /* EMAC CRS */ +#define PIOA_ASR_ERX0 BIT12 /* EMAC RXD0 */ +#define PIOA_ASR_ERX1 BIT13 /* EMAC RXD1 */ +#define PIOA_ASR_ERXER BIT14 /* EMAC RXER */ +#define PIOA_ASR_EMDC BIT15 /* EMAC MDC */ +#define PIOA_ASR_EMDIO BIT16 /* EMAC MDIO */ +#define PIOA_ASR_TXD0 BIT17 /* USART 0 Receive */ +#define PIOA_ASR_RXD0 BIT18 /* USART 0 Transmit */ +#define PIOA_ASR_SCK0 BIT19 /* USART 0 Clock */ +#define PIOA_ASR_CTS0 BIT20 /* USART 0 CTS */ +#define PIOA_ASR_RTS0 BIT21 /* USART 0 RTS */ +#define PIOA_ASR_RXD2 BIT22 /* USART 2 Receive */ +#define PIOA_ASR_TXD2 BIT23 /* USART 2 Transmit */ +#define PIOA_ASR_SCK2 BIT24 /* USART 2 Clock */ +#define PIOA_ASR_TWD BIT25 /* Two-Wire (I2C) Data */ +#define PIOA_ASR_TWCK BIT26 /* Two-Wire (I2C) Clock */ +#define PIOA_ASR_MCCK BIT27 /* MMC/SD Card Clock */ +#define PIOA_ASR_MCCDA BIT28 /* MMC/SD Card A Command */ +#define PIOA_ASR_MCDA0 BIT29 /* MMC/SD Card A Data 0 */ +#define PIOA_ASR_DRXD BIT30 /* Debug Uart Receive */ +#define PIOA_ASR_DTXD BIT31 /* Debug Uart Transmit */ + +/* Port A, Alternate Function B */ +#define PIOA_BSR_PCK3 BIT0 /* Peripheral Clock 3 */ +#define PIOA_BSR_PCK0 BIT1 /* Peripheral Clock 0 */ +#define PIOA_BSR_IRQ4 BIT2 /* IRQ4 */ +#define PIOA_BSR_IRQ5 BIT3 /* IRQ5 */ +/*#define PIOA_BSR_PCK1 BIT4 Peripheral Clock 1 ***DUPLICATED at BIT24 ??? */ +#define PIOA_BSR_TXD3 BIT5 /* USART 3 Transmit */ +#define PIOA_BSR_RXD3 BIT6 /* USART 3 Receive */ +#define PIOA_BSR_PCK2 BIT7 /* Peripheral Clock 2 */ +#define PIOA_BSR_MCCDB BIT8 /* MMC/SD Card B Command */ +#define PIOA_BSR_MCDB0 BIT9 /* MMC/SD Card B Data 0 */ +#define PIOA_BSR_MCDB1 BIT10 /* MMC/SD Card B Data 1 */ +#define PIOA_BSR_MCDB2 BIT11 /* MMC/SD Card B Data 2 */ +#define PIOA_BSR_MCDB3 BIT12 /* MMC/SD C ard B Data 3 */ +#define PIOA_BSR_TCLK0 BIT13 /* Timer 0 Clock */ +#define PIOA_BSR_TCLK1 BIT14 /* Timer 1 Clck */ +#define PIOA_BSR_TCLK2 BIT15 /* Timer 2 Clock */ +#define PIOA_BSR_IRQ6 BIT16 /* IRQ6 */ +#define PIOA_BSR_TIOA0 BIT17 /* Timer 0 I/O A */ +#define PIOA_BSR_TIOB0 BIT18 /* Timer 0 I/O B */ +#define PIOA_BSR_TIOA1 BIT19 /* Timer 1 I/O A */ +#define PIOA_BSR_TIOB1 BIT20 /* Timer 1 I/O B */ +#define PIOA_BSR_TIOA2 BIT21 /* Timer 2 I/O A */ +#define PIOA_BSR_TIOB2 BIT22 /* Timer 2 I/O B */ +#define PIOA_BSR_IRQ3 BIT23 /* IRQ3 */ +#define PIOA_BSR_PCK1 BIT24 /* Peripheral Clock 1 */ +#define PIOA_BSR_IRQ2 BIT25 /* IRQ2 */ +#define PIOA_BSR_IRQ1 BIT26 /* IRQ1 */ +#define PIOA_BSR_TCLK3 BIT27 /* Timer Block Clock 3 (docs only show 0-2?) */ +#define PIOA_BSR_TCLK4 BIT28 /* Timer Block Clock 4 */ +#define PIOA_BSR_TCLK5 BIT29 /* Timer Block Clock 5 */ +#define PIOA_BSR_CTS2 BIT30 /* USART 2 CTS */ +#define PIOA_BSR_RTS2 BIT31 /* USART 2 RTS */ + +/* Port B, Function A */ +#define PIOB_ASR_TF0 BIT0 /* AC'97/I2S 0 Transmit Frame */ +#define PIOB_ASR_TK0 BIT1 /* AC'97/I2S 0 Transmit Clock */ +#define PIOB_ASR_TD0 BIT2 /* AC'97/I2S 0 Transmit Data */ +#define PIOB_ASR_RD0 BIT3 /* AC'97/I2S 0 Receive Data */ +#define PIOB_ASR_RK0 BIT4 /* AC'97/I2S 0 Receive Clock */ +#define PIOB_ASR_RF0 BIT5 /* AC'97/I2S 0 Receive Frame */ +#define PIOB_ASR_TF1 BIT6 /* AC'97/I2S 1 Transmit Frame */ +#define PIOB_ASR_TK1 BIT7 /* AC'97/I2S 1 Transmit Clock */ +#define PIOB_ASR_TD1 BIT8 /* AC'97/I2S 1 Transmit Data */ +#define PIOB_ASR_RD1 BIT9 /* AC'97/I2S 1 Receive Data */ +#define PIOB_ASR_RK1 BIT10 /* AC'97/I2S 1 Receive Clock */ +#define PIOB_ASR_RF1 BIT11 /* AC'97/I2S 1 Receive Frame */ +#define PIOB_ASR_TF2 BIT12 /* AC'97/I2S 1 Transmit Frame */ +#define PIOB_ASR_TK2 BIT13 /* AC'97/I2S 1 Transmit Clock */ +#define PIOB_ASR_TD2 BIT14 /* AC'97/I2S 1 Transmit Data */ +#define PIOB_ASR_RD2 BIT15 /* AC'97/I2S 1 Receive Data */ +#define PIOB_ASR_RK2 BIT16 /* AC'97/I2S 1 Receive Clock */ +#define PIOB_ASR_RF2 BIT17 /* AC'97/I2S 1 Receive Frame */ +#define PIOB_ASR_RI1 BIT18 /* USART 1 RI */ +#define PIOB_ASR_DTR1 BIT19 /* USART 1 DTR */ +#define PIOB_ASR_TXD1 BIT20 /* USART 1 TXD */ +#define PIOB_ASR_RXD1 BIT21 /* USART 1 RXD */ +#define PIOB_ASR_SCK1 BIT22 /* USART 1 SCK */ +#define PIOB_ASR_DCD1 BIT23 /* USART 1 DCD */ +#define PIOB_ASR_CTS1 BIT24 /* USART 1 CTS */ +#define PIOB_ASR_DSR1 BIT25 /* USART 1 DSR */ +#define PIOB_ASR_RTS1 BIT26 /* USART 1 RTS */ +#define PIOB_ASR_PCK0 BIT27 /* Peripheral Clock 0 */ +#define PIOB_ASR_FIQ BIT28 /* FIQ */ +#define PIOB_ASR_IRQ0 BIT29 /* IRQ0 */ + +/* Port B, Function B */ +#define PIOB_BSR_RTS3 BIT0 /* USART 3 */ +#define PIOB_BSR_CTS3 BIT1 /* USART 3 */ +#define PIOB_BSR_SCK3 BIT2 /* USART 3 */ +#define PIOB_BSR_MCDA1 BIT3 /* MMC/SD Card A, Data 1 */ +#define PIOB_BSR_MCDA2 BIT4 /* MMC/SD Card A, Data 2 */ +#define PIOB_BSR_MCDA3 BIT5 /* MMC/SD Card A, Data 3 */ +#define PIOB_BSR_TIOA3 BIT6 /* Timer 3 IO A */ +#define PIOB_BSR_TIOB3 BIT7 /* Timer 3 IO B */ +#define PIOB_BSR_TIOA4 BIT8 /* Timer 4 IO A */ +#define PIOB_BSR_TIOB4 BIT9 /* Timer 4 IO B */ +#define PIOB_BSR_TIOA5 BIT10 /* Timer 5 IO A */ +#define PIOB_BSR_TIOB5 BIT11 /* Timer 5 IO B */ +#define PIOB_BSR_ETX2 BIT12 /* EMAC TXD2 */ +#define PIOB_BSR_ETX3 BIT13 /* EMAC TXD3 */ +#define PIOB_BSR_ETXER BIT14 /* EMAC TXER */ +#define PIOB_BSR_ERX2 BIT15 /* EMAC RXD2 */ +#define PIOB_BSR_ERX3 BIT16 /* EMAC RXD3 */ +#define PIOB_BSR_ERXDV BIT17 /* EMAC RXDV */ +#define PIOB_BSR_ECOL BIT18 /* EMAC COL */ +#define PIOB_BSR_ERXCK BIT19 /* EMAC RX Clock */ +#define PIOB_BSR_EF100 BIT25 /* EMAC Speed 100 (RMII Only) */ + +/* Port C, Alternate Function A */ +#define PIOC_ASR_BFCK BIT0 /* Burst Flash Clock */ +#define PIOC_ASR_BFRDY BIT1 /* Burst Flash Ready or SMC Card OE */ +#define PIOC_ASR_BFAVD BIT2 /* Burst Flash Address Valid */ +#define PIOC_ASR_BFBAA BIT3 /* Burst Flash Address Advance or SMC Card WE */ +#define PIOC_ASR_BFOE BIT4 /* Burst Flash OE */ +#define PIOC_ASR_BFWE BIT5 /* Burst Flash WE */ +#define PIOC_ASR_NWAIT BIT6 /* WAIT Input */ +#define PIOC_ASR_A23 BIT7 /* A23 */ +#define PIOC_ASR_A24 BIT8 /* A24 */ +#define PIOC_ASR_A25 BIT9 /* A25 or Compact Flash R/W */ +#define PIOC_ASR_NCS4 BIT10 /* CS4 or Compact Flash CS */ +#define PIOC_ASR_NCS5 BIT11 /* CS5 or Compact Flash CE1 */ +#define PIOC_ASR_NCS6 BIT12 /* CS6 or Compact Flash CE2 */ +#define PIOC_ASR_NCS7 BIT13 /* CS7 */ +#define PIOC_ASR_D16 BIT16 /* Databus Bit 16 */ +#define PIOC_ASR_D17 BIT17 /* Databus Bit 17 */ +#define PIOC_ASR_D18 BIT18 /* Databus Bit 18 */ +#define PIOC_ASR_D19 BIT19 /* Databus Bit 19 */ +#define PIOC_ASR_D20 BIT20 /* Databus Bit 20 */ +#define PIOC_ASR_D21 BIT21 /* Databus Bit 21 */ +#define PIOC_ASR_D22 BIT22 /* Databus Bit 22 */ +#define PIOC_ASR_D23 BIT23 /* Databus Bit 23 */ +#define PIOC_ASR_D24 BIT24 /* Databus Bit 24 */ +#define PIOC_ASR_D25 BIT25 /* Databus Bit 25 */ +#define PIOC_ASR_D26 BIT26 /* Databus Bit 26 */ +#define PIOC_ASR_D27 BIT27 /* Databus Bit 27 */ +#define PIOC_ASR_D28 BIT28 /* Databus Bit 28 */ +#define PIOC_ASR_D29 BIT29 /* Databus Bit 29 */ +#define PIOC_ASR_D30 BIT30 /* Databus Bit 30 */ +#define PIOC_ASR_D31 BIT31 /* Databus Bit 31 */ + +/* Port C, Alternate Function B - None */ + +/* Port D, Alternate Function A */ +#define PIOD_ASR_ETX0 BIT0 /* EMAC TXD0 */ +#define PIOD_ASR_ETX1 BIT1 /* EMAC TXD1 */ +#define PIOD_ASR_ETX2 BIT2 /* EMAC TXD2 */ +#define PIOD_ASR_ETX3 BIT3 /* EMAC TXD3 */ +#define PIOD_ASR_ETXEN BIT4 /* EMAC TXEN */ +#define PIOD_ASR_ETXER BIT5 /* EMAC TXER */ +#define PIOD_ASR_DTXD BIT6 /* Debug UART Transmit */ +#define PIOD_ASR_PCK0 BIT7 /* Peripheral Clock 0 */ +#define PIOD_ASR_PCK1 BIT8 /* Peripheral Clock 1 */ +#define PIOD_ASR_PCK2 BIT9 /* Peripheral Clock 2 */ +#define PIOD_ASR_PCK3 BIT10 /* Peripheral Clock 3 */ +#define PIOD_ASR_TD0 BIT15 /* AC'97/I2S 0 Transmit Data */ +#define PIOD_ASR_TD1 BIT16 /* AC'97/I2S 1 Transmit Data */ +#define PIOD_ASR_TD2 BIT17 /* AC'97/I2S 2 Transmit Data */ +#define PIOD_ASR_NPCS1 BIT18 /* SPI Chip Select 1 */ +#define PIOD_ASR_NPCS2 BIT19 /* SPI Chip Select 2 */ +#define PIOD_ASR_NPCS3 BIT20 /* SPI Chip Select 3 */ +#define PIOD_ASR_RTS0 BIT21 /* USART 0 RTS */ +#define PIOD_ASR_RTS1 BIT22 /* USART 1 RTS */ +#define PIOD_ASR_RTS2 BIT23 /* USART 2 RTS */ +#define PIOD_ASR_RTS3 BIT24 /* USART 3 RTS */ +#define PIOD_ASR_DTR1 BIT25 /* USART 1 DTR */ + +/* Port D, Alternate Function B */ + +#define PIOC_ASR_TSYNC BIT7 /* ETM Sync */ +#define PIOC_ASR_TCLK BIT8 /* ETM Clock */ +#define PIOC_ASR_TPS0 BIT9 /* ETM Processor Status 0 */ +#define PIOC_ASR_TPS1 BIT10 /* ETM Processor Status 1 */ +#define PIOC_ASR_TPS2 BIT11 /* ETM Processor Status 2 */ +#define PIOC_ASR_TPK0 BIT12 /* ETM Packet Data 0 */ +#define PIOC_ASR_TPK1 BIT13 /* ETM Packet Data 1 */ +#define PIOC_ASR_TPK2 BIT14 /* ETM Packet Data 2 */ +#define PIOC_ASR_TPK3 BIT15 /* ETM Packet Data 3 */ +#define PIOC_ASR_TPK4 BIT16 /* ETM Packet Data 4 */ +#define PIOC_ASR_TPK5 BIT17 /* ETM Packet Data 5 */ +#define PIOC_ASR_TPK6 BIT18 /* ETM Packet Data 6 */ +#define PIOC_ASR_TPK7 BIT19 /* ETM Packet Data 7 */ +#define PIOC_ASR_TPK8 BIT20 /* ETM Packet Data 8 */ +#define PIOC_ASR_TPK9 BIT21 /* ETM Packet Data 9 */ +#define PIOC_ASR_TPK10 BIT22 /* ETM Packet Data 10 */ +#define PIOC_ASR_TPK11 BIT23 /* ETM Packet Data 11 */ +#define PIOC_ASR_TPK12 BIT24 /* ETM Packet Data 12 */ +#define PIOC_ASR_TPK13 BIT25 /* ETM Packet Data 13 */ +#define PIOC_ASR_TPK14 BIT26 /* ETM Packet Data 14 */ +#define PIOC_ASR_TPK15 BIT27 /* ETM Packet Data 15 */ + +#endif diff --git a/bsps/arm/csb337/include/at91rm9200_mem.h b/bsps/arm/csb337/include/at91rm9200_mem.h new file mode 100644 index 0000000000..fafb18f6e8 --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200_mem.h @@ -0,0 +1,115 @@ +/* + * AT91RM9200 Memory Controller definitions + * + * Copyright (c) 2002 by Cogent Computer Systems + * Written by Mike Kelly + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef AT91RM9200_MEM_H +#define AT91RM9200_MEM_H + +/********************************************************************** + * External Bus Interface Unit + **********************************************************************/ +#define EBI_CSA 0x00 /* Chip Select Assignment Register */ +#define EBI_CFGR 0x04 /* Configuration Register */ + +/* Bit Defines */ +/* EBI_CSA - Chip Select Assignment Register */ +#define EBI_CSA_CS4_CF BIT4 /* 1 = CS4-6 are assigned to Compact Flash, 0 = Chip Selects */ +#define EBI_CSA_CS3_SMM BIT3 /* 1 = CS3 is assigned to SmartMedia, 0 = Chip Select */ +#define EBI_CSA_CS1_SDRAM BIT1 /* 1 = CS1 is assigned to SDRAM, 0 = Chip Select */ +#define EBI_CSA_CS0_BF BIT0 /* 1 = CS0 is assigned to Burst Flash, 0 = Chip Select */ + +/* EBI_CFGR - Configuration Register */ +#define EBI_CFGR_DBPU BIT0 /* 1 = Disable D0-15 pullups */ + +/*************************************************************************** + * Static Memory Interface Unit + ***************************************************************************/ +#define SMC_CSR0 0x00 /* Chip Select Register 0 */ +#define SMC_CSR1 0x04 /* Chip Select Register 1 */ +#define SMC_CSR2 0x08 /* Chip Select Register 2 */ +#define SMC_CSR3 0x0C /* Chip Select Register 3 */ +#define SMC_CSR4 0x10 /* Chip Select Register 4 */ +#define SMC_CSR5 0x14 /* Chip Select Register 5 */ +#define SMC_CSR6 0x18 /* Chip Select Register 6 */ +#define SMC_CSR7 0x1C /* Chip Select Register 7 */ + +/* Bit Defines */ +/* SMC_CSR0 -7 - Chip Selects 0 - 7 Register */ +#define SMC_CSR_RWHOLD(_x_) ((_x_ & 0x3) << 28) /* Hold CS after R/W strobes */ +#define SMC_CSR_RWSETUP(_x_) ((_x_ & 0x3) << 24) /* Setup CS before R/W strobes */ +#define SMC_CSR_ACSS_0 (0 << 16) /* Setup/Hold Address 0 clocks before/after CS */ +#define SMC_CSR_ACSS_1 (1 << 16) /* Setup/Hold Address 1 clock before/after CS */ +#define SMC_CSR_ACSS_2 (2 << 16) /* Setup/Hold Address 2 clocks before/after CS */ +#define SMC_CSR_ACSS_3 (3 << 16) /* Setup/Hold Address 3 clocks before/after CS */ +#define SMC_CSR_DRP_NORMAL 0 /* 0 = normal read protocol */ +#define SMC_CSR_DRP_EARLY BIT15 /* 1 = early read protocol */ +#define SMC_CSR_DBW_16 (1 << 13) /* CS DataBus Width = 16-Bits */ +#define SMC_CSR_DBW_8 (2 << 13) /* CS DataBus Width = 8 Bits */ +#define SMC_CSR_BAT_16_1 0 /* Single 16-Bit device (when DBW is 16) */ +#define SMC_CSR_BAT_16_2 BIT12 /* Dual 8-Bit devices (when DBW is 16) */ +#define SMC_CSR_TDF(_x_) ((_x_ & 0xf) << 8) /* Intercycle Data Float Time */ +#define SMC_CSR_WSEN BIT7 /* 1 = wait states are enabled */ +#define SMC_CSR_NWS(_x_) ((_x_ & 0x7f) << 0) /* Wait States + 1 */ + +/* ***************************************************************************** */ +/* SDRAM Memory Interface Unit */ +/* ***************************************************************************** */ +#define SDRC_MR 0x00 /* Mode Register */ +#define SDRC_TR 0x04 /* Refresh Timer Register */ +#define SDRC_CR 0x08 /* Configuration Register */ +#define SDRC_SRR 0x0C /* Self Refresh Register */ +#define SDRC_LPR 0x10 /* Low Power Register */ +#define SDRC_IER 0x14 /* Interrupt Enable Register */ +#define SDRC_IDR 0x18 /* Interrupt Disable Register */ +#define SDRC_IMR 0x1C /* Interrupt Mask Register */ +#define SDRC_ISR 0x20 /* Interrupt Status Register */ + +/* Bit Defines */ +/* SDRC_MR - Mode Register */ +#define SDRC_MR_DBW_16 BIT4 /* 1 = SDRAM is 16-bits wide, 0 = 32-bits */ +#define SDRC_MR_NORM (0 << 0) /* Normal Mode - All accesses to SDRAM are decoded normally */ +#define SDRC_MR_NOP (1 << 0) /* NOP Command is sent to SDRAM */ +#define SDRC_MR_PRE (2 << 0) /* Precharge All Command is sent to SDRAM */ +#define SDRC_MR_MRS (3 << 0) /* Mode Register Set Command is sent to SDRAM */ +#define SDRC_MR_REF (4 << 0) /* Refresh Command is sent to SDRAM */ + +/* SDRC_TR - Refresh Timer Register */ +#define SDRC_TR_COUNT(_x_) ((_x_ & 0xfff) << 0) + +/* SDRC_CR - Configuration Register */ +#define SDRC_CR_TXSR(_x_) ((_x_ & 0xf) << 27) /* CKE to ACT Time */ +#define SDRC_CR_TRAS(_x_) ((_x_ & 0xf) << 23) /* ACT to PRE Time */ +#define SDRC_CR_TRCD(_x_) ((_x_ & 0xf) << 19) /* RAS to CAS Time */ +#define SDRC_CR_TRP(_x_) ((_x_ & 0xf) << 15) /* PRE to ACT Time */ +#define SDRC_CR_TRC(_x_) ((_x_ & 0xf) << 11) /* REF to ACT Time */ +#define SDRC_CR_TWR(_x_) ((_x_ & 0xf) << 7) /* Write Recovery Time */ +#define SDRC_CR_CAS_2 (2 << 5) /* Cas Delay = 2, this is the only supported value */ +#define SDRC_CR_NB_2 0 /* 2 Banks per device */ +#define SDRC_CR_NB_4 BIT4 /* 4 Banks per device */ +#define SDRC_CR_NR_11 (0 << 2) /* Number of rows = 11 */ +#define SDRC_CR_NR_12 (1 << 2) /* Number of rows = 12 */ +#define SDRC_CR_NR_13 (2 << 2) /* Number of rows = 13 */ +#define SDRC_CR_NC_8 (0 << 0) /* Number of columns = 8 */ +#define SDRC_CR_NC_9 (1 << 0) /* Number of columns = 9 */ +#define SDRC_CR_NC_10 (2 << 0) /* Number of columns = 10 */ +#define SDRC_CR_NC_11 (3 << 0) /* Number of columns = 11 */ + +/* SDRC_SRR - Self Refresh Register */ +#define SDRC_SRR_SRCB BIT0 /* 1 = Enter Self Refresh */ + +/* SDRC_LPR - Low Power Register */ +#define SDRC_LPR_LPCB BIT0 /* 1 = De-assert CKE between accesses */ + +/* SDRC_IER - Interrupt Enable Register */ +/* SDRC_IDR - Interrupt Disable Register */ +/* SDRC_ISR - Interrupt Mask Register */ +/* SDRC_IMR - Interrupt Mask Register */ +#define SDRC_INT_RES BIT0 /* Refresh Error Status */ + +#endif diff --git a/bsps/arm/csb337/include/at91rm9200_pmc.h b/bsps/arm/csb337/include/at91rm9200_pmc.h new file mode 100644 index 0000000000..70cf77fc5a --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200_pmc.h @@ -0,0 +1,169 @@ +/* + * AT91RM9200 Power Management and Clock definitions + * + * Copyright (c) 2002 by Cogent Computer Systems + * Written by Mike Kelly + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __AT91RM9200_PMC_H__ +#define __AT91RM9200_PMC_H__ + +#include + +/*********************************************************************** + * Power Management and Clock Control Register Offsets + ***********************************************************************/ +int at91rm9200_get_mainclk(void); +int at91rm9200_get_slck(void); +int at91rm9200_get_mck(void); + + +#define PMC_SCER 0x00 /* System Clock Enable Register */ +#define PMC_SCDR 0x04 /* System Clock Disable Register */ +#define PMC_SCSR 0x08 /* System Clock Status Register */ +#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */ +#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ +#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */ +#define PMC_MOR 0x20 /* Main Oscillator Register */ +#define PMC_MCFR 0x24 /* Main Clock Frequency Register */ +#define PMC_PLLAR 0x28 /* PLL A Register */ +#define PMC_PLLBR 0x2C /* PLL B Register */ +#define PMC_MCKR 0x30 /* Master Clock Register */ +#define PMC_PCKR0 0x40 /* Programmable Clock Register 0 */ +#define PMC_PCKR1 0x44 /* Programmable Clock Register 1 */ +#define PMC_PCKR2 0x48 /* Programmable Clock Register 2 */ +#define PMC_PCKR3 0x4C /* Programmable Clock Register 3 */ +#define PMC_PCKR4 0x50 /* Programmable Clock Register 4 */ +#define PMC_PCKR5 0x54 /* Programmable Clock Register 5 */ +#define PMC_PCKR6 0x58 /* Programmable Clock Register 6 */ +#define PMC_PCKR7 0x5C /* Programmable Clock Register 7 */ +#define PMC_IER 0x60 /* Interrupt Enable Register */ +#define PMC_IDR 0x64 /* Interrupt Disable Register */ +#define PMC_SR 0x68 /* Status Register */ +#define PMC_IMR 0x6C /* Interrupt Mask Register */ + +/* Bit Defines */ + +/* PMC_SCDR - System Clock Disable Register */ +/* PMC_SCSR - System Clock Status Register */ +/* PMC_SCER - System Clock Enable Register */ +#define PMC_SCR_PCK7 BIT15 +#define PMC_SCR_PCK6 BIT14 +#define PMC_SCR_PCK5 BIT13 +#define PMC_SCR_PCK4 BIT12 +#define PMC_SCR_PCK3 BIT11 +#define PMC_SCR_PCK2 BIT10 +#define PMC_SCR_PCK1 BIT9 +#define PMC_SCR_PCK0 BIT8 +#define PMC_SCR_UHP BIT4 +#define PMC_SCR_MCKUDP BIT2 +#define PMC_SCR_UDP BIT1 +#define PMC_SCR_PCK BIT0 + +/* PMC_PCER - Peripheral Clock Enable Register */ +/* PMC_PCDR - Peripheral Clock Disable Register */ +/* PMC_PCSR - Peripheral Clock Status Register */ +#define PMC_PCR_PID_EMAC BIT24 /* Ethernet Peripheral Clock */ +#define PMC_PCR_PID_UHP BIT23 /* USB Host Ports Peripheral Clock */ +#define PMC_PCR_PID_TC5 BIT22 /* Timer/Counter 5 Peripheral Clock */ +#define PMC_PCR_PID_TC4 BIT21 /* Timer/Counter 4 Peripheral Clock */ +#define PMC_PCR_PID_TC3 BIT20 /* Timer/Counter 3 Peripheral Clock */ +#define PMC_PCR_PID_TC2 BIT19 /* Timer/Counter 2 Peripheral Clock */ +#define PMC_PCR_PID_TC1 BIT18 /* Timer/Counter 1 Peripheral Clock */ +#define PMC_PCR_PID_TC0 BIT17 /* Timer/Counter 0 Peripheral Clock */ +#define PMC_PCR_PID_SSC2 BIT16 /* Synchronous Serial 2 Peripheral Clock */ +#define PMC_PCR_PID_SSC1 BIT15 /* Synchronous Serial 1 Peripheral Clock */ +#define PMC_PCR_PID_SSC0 BIT14 /* Synchronous Serial 0 Peripheral Clock */ +#define PMC_PCR_PID_SPI BIT13 /* Serial Peripheral Interface Peripheral Clock */ +#define PMC_PCR_PID_TWI BIT12 /* Two-Wire Interface Peripheral Clock */ +#define PMC_PCR_PID_UDP BIT11 /* USB Device Port Peripheral Clock */ +#define PMC_PCR_PID_MCI BIT10 /* MMC/SD Card Peripheral Clock */ +#define PMC_PCR_PID_US3 BIT9 /* USART 3 Peripheral Clock */ +#define PMC_PCR_PID_US2 BIT8 /* USART 2 Peripheral Clock */ +#define PMC_PCR_PID_US1 BIT7 /* USART 1 Peripheral Clock */ +#define PMC_PCR_PID_US0 BIT6 /* USART 0 Peripheral Clock */ +#define PMC_PCR_PID_PIOD BIT5 /* Parallel I/O D Peripheral Clock */ +#define PMC_PCR_PID_PIOC BIT4 /* Parallel I/O C Peripheral Clock */ +#define PMC_PCR_PID_PIOB BIT3 /* Parallel I/O B Peripheral Clock */ +#define PMC_PCR_PID_PIOA BIT2 /* Parallel I/O A Peripheral Clock */ + +/* PMC_MOR - Main Oscillator Register */ +#define PMC_MOR_MOSCEN BIT0 + +/* PMC_MCFR - Main Clock Frequency Register */ +#define PMC_MCFR_MAINRDY BIT16 + +/* PMC_PLLAR - PLL A Register */ +#define PMC_PLLAR_MUST_SET BIT29 /* This bit must be set according to the docs */ +#define PMC_PLLAR_MUL(_x_) ((_x_ & 0x7ff) << 16) /* Multiplier */ +#define PMC_PLLAR_MUL_MASK (0x7ff << 16) /* Multiplier mask */ + +#define PMC_PLLAR_OUT_80_160 (0 << 14) /* select when PLL frequency is 80-160 Mhz */ +#define PMC_PLLAR_OUT_150_240 (2 << 14) /* select when PLL frequency is 150-240 Mhz */ +#define PMC_PLLAR_DIV(_x_) ((_x_ & 0xff) << 0) /* Divider */ +#define PMC_PLLAR_DIV_MASK (0xff) /* Divider mask */ + +/* PMC_PLLBR - PLL B Register */ +#define PMC_PLLBR_USB_96M BIT28 /* Set when PLL is 96Mhz to divide it by 2 for USB */ +#define PMC_PLLBR_MUL(_x_) ((_x_ & 0x7ff) << 16) /* Multiplier */ +#define PMC_PLLBR_MUL_MASK (0x7ff << 16) /* Multiplier mask */ +#define PMC_PLLBR_OUT_80_160 (0 << 14) /* select when PLL frequency is 80-160 Mhz */ +#define PMC_PLLBR_OUT_150_240 (2 << 14) /* select when PLL frequency is 150-240 Mhz */ +#define PMC_PLLBR_DIV(_x_) ((_x_ & 0xff) << 0) /* Divider */ +#define PMC_PLLBR_DIV_MASK (0xff) /* Divider mask */ + +/* PMC_MCKR - Master Clock Register */ +#define PMC_MCKR_MDIV_MASK (3 << 8) /* for masking out the MDIV field */ +#define PMC_MCKR_MDIV_1 (0 << 8) /* MCK = Core/1 */ +#define PMC_MCKR_MDIV_2 (1 << 8) /* MCK = Core/2 */ +#define PMC_MCKR_MDIV_3 (2 << 8) /* MCK = Core/3 */ +#define PMC_MCKR_MDIV_4 (3 << 8) /* MCK = Core/4 */ +#define PMC_MCKR_PRES_MASK (7 << 2) /* for masking out the PRES field */ +#define PMC_MCKR_PRES_1 (0 << 2) /* Core = CSS/1 */ +#define PMC_MCKR_PRES_2 (1 << 2) /* Core = CSS/2 */ +#define PMC_MCKR_PRES_4 (2 << 2) /* Core = CSS/4 */ +#define PMC_MCKR_PRES_8 (3 << 2) /* Core = CSS/8 */ +#define PMC_MCKR_PRES_16 (4 << 2) /* Core = CSS/16 */ +#define PMC_MCKR_PRES_32 (5 << 2) /* Core = CSS/32 */ +#define PMC_MCKR_PRES_64 (6 << 2) /* Core = CSS/64 */ +#define PMC_MCKR_CSS_MASK (3 << 0) /* for masking out the CSS field */ +#define PMC_MCKR_CSS_SLOW (0 << 0) /* Core Source = Slow Clock */ +#define PMC_MCKR_CSS_MAIN (1 << 0) /* Core Source = Main Oscillator */ +#define PMC_MCKR_CSS_PLLA (2 << 0) /* Core Source = PLL A */ +#define PMC_MCKR_CSS_PLLB (3 << 0) /* Core Source = PLL B */ + +/* PMC_PCKR0 - 7 - Programmable Clock Register 0 */ +#define PMC_PCKR_PRES_1 (0 << 2) /* Peripheral Clock = CSS/1 */ +#define PMC_PCKR_PRES_2 (1 << 2) /* Peripheral Clock = CSS/2 */ +#define PMC_PCKR_PRES_4 (2 << 2) /* Peripheral Clock = CSS/4 */ +#define PMC_PCKR_PRES_8 (3 << 2) /* Peripheral Clock = CSS/8 */ +#define PMC_PCKR_PRES_16 (4 << 2) /* Peripheral Clock = CSS/16 */ +#define PMC_PCKR_PRES_32 (5 << 2) /* Peripheral Clock = CSS/32 */ +#define PMC_PCKR_PRES_64 (6 << 2) /* Peripheral Clock = CSS/64 */ +#define PMC_PCKR_CSS_SLOW (0 << 0) /* Peripheral Clock Source = Slow Clock */ +#define PMC_PCKR_CSS_MAIN (1 << 0) /* Peripheral Clock Source = Main Oscillator */ +#define PMC_PCKR_CSS_PLLA (2 << 0) /* Peripheral Clock Source = PLL A */ +#define PMC_PCKR_CSS_PLLB (3 << 0) /* Peripheral Clock Source = PLL B */ + +/* PMC_IER - Interrupt Enable Register */ +/* PMC_IDR - Interrupt Disable Register */ +/* PMC_SR - Status Register */ +/* PMC_IMR - Interrupt Mask Register */ +#define PMC_INT_PCK7_RDY BIT15 +#define PMC_INT_PCK6_RDY BIT14 +#define PMC_INT_PCK5_RDY BIT13 +#define PMC_INT_PCK4_RDY BIT12 +#define PMC_INT_PCK3_RDY BIT11 +#define PMC_INT_PCK2_RDY BIT10 +#define PMC_INT_PCK1_RDY BIT9 +#define PMC_INT_PCK0_RDY BIT8 +#define PMC_INT_MCK_RDY BIT3 +#define PMC_INT_LOCKB BIT2 +#define PMC_INT_LCKA BIT1 +#define PMC_INT_MOSCS BIT0 + + +#endif diff --git a/bsps/arm/csb337/include/at91rm9200_usart.h b/bsps/arm/csb337/include/at91rm9200_usart.h new file mode 100644 index 0000000000..387f353992 --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200_usart.h @@ -0,0 +1,146 @@ +/* + * Atmel AT91RM9200_USART Register definitions, used in KIT637_V6 (CSB637) + * + * Copyright (c) 2003 by Cogent Computer Systems + * Written by Mike Kelly + * + * Modified by Fernando Nicodemos + * from NCB - Sistemas Embarcados Ltda. (Brazil) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ + +#ifndef __AT91RM9200_USART_H__ +#define __AT91RM9200_USART_H__ + +#include + +/* Register Offsets */ +#define US_CR 0x00 /* Control Register */ +#define US_MR 0x04 /* Mode Register */ +#define US_IER 0x08 /* Interrupt Enable Register */ +#define US_IDR 0x0C /* Interrupt Disable Register */ +#define US_IMR 0x10 /* Interrupt Mask Register */ +#define US_SR 0x14 /* Channel Status Register */ +#define US_RHR 0x18 /* Receiver Holding Register */ +#define US_THR 0x1C /* Transmitter Holding Register */ +#define US_BRGR 0x20 /* Baud Rate Generator Register */ +#define US_RTOR 0x24 /* Receiver Time-out Register */ +#define US_TTGR 0x28 /* Transmitter Timeguard Register */ +#define US_C1R 0x40 /* Chip ID1 Register - FI DI Ratio Register */ +#define US_C2R 0x44 /* Chip ID2 Register - Number of Erros Register */ +#define US_FNTR 0x48 /* Force NTRST Register */ +#define US_IF 0x4C /* IrDA Filter Register */ + +/* Bit Defines */ +/* Control Register, US_CR, Offset 0x00 */ +#define US_CR_RSTRX BIT2 /* 1 = Reset and disable receiver */ +#define US_CR_RSTTX BIT3 /* 1 = Reset and disable transmitter */ +#define US_CR_RXEN BIT4 /* 1 = Receiver enable */ +#define US_CR_RXDIS BIT5 /* 1 = Receiver disable */ +#define US_CR_TXEN BIT6 /* 1 = Transmitter enable */ +#define US_CR_TXDIS BIT7 /* 1 = Transmitter disable */ +#define US_CR_RSTSTA BIT8 /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */ +#define US_CR_STTBRK BIT9 /* 1 = Start transmission of a Break */ +#define US_CR_STPBRK BIT10 /* 1 = Stop transmission of a Break */ +#define US_CR_STTTO BIT11 /* 1 = Start Time-out */ +#define US_CR_SENDA BIT12 /* 1 = Send Address - MDROP mode only */ +#define US_CR_RSTIT BIT13 /* 1 = Reset Iteration */ +#define US_CR_RSTNACK BIT14 /* 1 = Reset Non Acknowledge */ +#define US_CR_RETTO BIT15 /* 1 = Restart Time-out */ +#define US_CR_DTREN BIT16 /* 1 = Data Terminal Ready Enable - AT91RM9200 only */ +#define US_CR_DTRDIS BIT17 /* 1 = Data Terminal Ready Disable - AT91RM9200 only */ +#define US_CR_RTSEN BIT18 /* 1 = Request To Send Enable */ +#define US_CR_RTSDIS BIT19 /* 1 = Request To Send Disable */ + + +/* Mode Register. US_MR. Offset 0x04 */ +#define US_MR_USMODE (0xF << 0) /* Mode of the USART */ +#define US_MR_USMODE_NORMAL 0 +#define US_MR_USMODE_RS485 1 +#define US_MR_USMODE_HWHS 2 +#define US_MR_USMODE_MODEM 3 +#define US_MR_USMODE_ISO7816_T0 4 +#define US_MR_USMODE_ISO7816_T1 6 +#define US_MR_USMODE_IRDA 8 +#define US_MR_USCLKS (3 << 4) /* Clock Selection */ +#define US_MR_USCLKS_MCK (0 << 4) +#define US_MR_USCLKS_MCK_DIV8 (1 << 4) +#define US_MR_USCLKS_SCK (3 << 4) +#define US_MR_CHRL (3 << 6) /* Character Length */ +#define US_MR_CHRL_5 (0 << 6) +#define US_MR_CHRL_6 (1 << 6) +#define US_MR_CHRL_7 (2 << 6) +#define US_MR_CHRL_8 (3 << 6) +#define US_MR_SYNC (1 << 8) /* Synchronous Mode Select */ +#define US_MR_PAR (7 << 9) /* Parity Type */ +#define US_MR_PAR_EVEN (0 << 9) /* Even Parity */ +#define US_MR_PAR_ODD (1 << 9) /* Odd Parity */ +#define US_MR_PAR_SPACE (2 << 9) /* Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (3 << 9) /* Parity forced to 1 (Mark) */ +#define US_MR_PAR_NONE (4 << 9) /* No Parity */ +#define US_MR_PAR_MDROP (6 << 9) /* Multi-drop mode */ +#define US_MR_NBSTOP (3 << 12) /* Number of Stop Bits */ +#define US_MR_NBSTOP_1 (0 << 12) +#define US_MR_NBSTOP_1_5 (1 << 12) +#define US_MR_NBSTOP_2 (2 << 12) +#define US_MR_CHMODE (3 << 14) /* Channel Mode */ +#define US_MR_CHMODE_NORM (0 << 14) /* Normal Mode */ +#define US_MR_CHMODE_AUTO (1 << 14) /* Auto Echo: RXD drives TXD */ +#define US_MR_CHMODE_LOC (2 << 14) /* Local Loopback: TXD drives RXD */ +#define US_MR_CHMODE_REM (3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */ +#define US_MR_MSBF (1 << 16) /* Bit Order */ +#define US_MR_MODE9 (1 << 17) /* 9-bit Character Length */ +#define US_MR_CLKO (1 << 18) /* Clock Output Select */ +#define US_MR_OVER (1 << 19) /* Oversampling Mode */ +#define US_MR_INACK (1 << 20) /* Inhibit Non Acknowledge */ +#define US_MR_DSNACK (1 << 21) /* Disable Successive NACK */ +#define US_MR_MAX_ITER (7 << 24) /* Max Iterations */ +#define US_MR_FILTER (1 << 28) /* Infrared Receive Line Filter */ + +/* Interrupt Enable Register, US_IER, Offset 0x08 */ +/* Interrupt Disable Register, US_IDR, Offset 0x0C */ +/* Interrupt Mask Register, US_IMR, Offset 0x10 */ +/* Channel Status Register, US_SR, Offset 0x14 */ +#define US_IER_RXRDY BIT0 /* RXRDY Interrupt */ +#define US_IER_TXRDY BIT1 /* TXRDY Interrupt */ +#define US_IER_RXBRK BIT2 /* End of Receive Transfer Interrupt */ +#define US_IER_ENDRX BIT3 /* End of Receiver Transfer */ +//#define US_IER_ENDTX BIT4 /* End of Transmit Interrupt */ +#define US_IER_OVRE BIT5 /* Overrun Interrupt */ +#define US_IER_FRAME BIT6 /* Framing Error Interrupt */ +#define US_IER_PARE BIT7 /* Parity Error */ +#define US_IER_TIMEOUT BIT8 /* Receiver Time-out */ +#define US_IER_TXEMPTY BIT9 /* Transmitter Empty */ +#define US_IER_ITERATION BIT10 /* Max number of Repetitions Reached */ +#define US_IER_TXBUFE BIT11 /* Transmission Buffer Empty */ +#define US_IER_RXBUFF BIT12 /* Reception Buffer Full */ +#define US_IER_NACK BIT13 /* Non Acknowledge */ +#define US_IER_RIIC BIT16 /* Ring Indicator Input Change [AT91RM9200 only] */ +#define US_IER_DSRIC BIT17 /* Data Set Ready Input Change [AT91RM9200 only] */ +#define US_IER_DCDIC BIT18 /* Data Carrier Detect Input Change [AT91RM9200 only] */ +#define US_IER_CTSIC BIT19 /* Clear to Send Input Change */ +#define US_IER_ALL 0xC0001AFB /* all assigned bits */ + +/* FORCE_NTRST Register, US_FNTR, Offset 0x48 */ +#define US_FNTR_NTRST BIT0 /* 1 = Force NTRST low in JTAG */ + +typedef struct { + volatile uint32_t cr; + volatile uint32_t mr; + volatile uint32_t ier; + volatile uint32_t idr; + volatile uint32_t imr; + volatile uint32_t sr; + volatile uint32_t rhr; + volatile uint32_t thr; + volatile uint32_t brgr; + volatile uint32_t _res0[7]; + volatile uint32_t cidr; + volatile uint32_t exid; + volatile uint32_t fnr; +} at91rm9200_usart_regs_t; + +#endif /* __AT91RM9200_USART_H__ */ diff --git a/bsps/arm/csb337/include/bits.h b/bsps/arm/csb337/include/bits.h new file mode 100644 index 0000000000..6f2c4036b6 --- /dev/null +++ b/bsps/arm/csb337/include/bits.h @@ -0,0 +1,48 @@ +/* + * Bit position definitions + * + * Copyright (c) 2002 by Cogent Computer Systems + * Written by Mike Kelly + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __BITS_H__ +#define __BITS_H__ + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#endif /* __BITS_H__ */ + diff --git a/bsps/arm/csb337/include/bsp.h b/bsps/arm/csb337/include/bsp.h new file mode 100644 index 0000000000..c99de2fd0a --- /dev/null +++ b/bsps/arm/csb337/include/bsp.h @@ -0,0 +1,78 @@ +/** + * @file + * + * @ingroup arm_csb337 + * + * @brief Global BSP definitions. + */ + +/* + * CSB337 BSP header file + * + * Copyright (c) 2004 by Cogent Computer Systems + * Writtent by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef LIBBSP_ARM_CSB337_BSP_H +#define LIBBSP_ARM_CSB337_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup arm_csb337 CSB337 Support + * + * @ingroup bsp_arm + * + * @brief CSB337 support package. + * + * @{ + */ + +#define BSP_FEATURE_IRQ_EXTENSION + +/* What is the input clock freq in hertz? */ +#define BSP_MAIN_FREQ 3686400 /* 3.6864 MHz */ +#define BSP_SLCK_FREQ 32768 /* 32.768 KHz */ + +/* What is the last interrupt? */ +#define BSP_MAX_INT AT91RM9200_MAX_INT + +/* + * forward reference the type to avoid conflicts between libchip serial + * and libchip rtc get and set register types. + */ +typedef struct _console_tbl console_tbl; +console_tbl *BSP_get_uart_from_minor(int minor); + +static inline int32_t BSP_get_baud(void) {return 38400;} + +#define ST_PIMR_PIV 33 /* 33 ticks of the 32.768Khz clock ~= 1msec */ + +/** + * @brief Network driver configuration + */ +extern struct rtems_bsdnet_ifconfig *config; + +/* Change these to match your board */ +int rtems_at91rm9200_emac_attach(struct rtems_bsdnet_ifconfig *config, int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_at91rm9200_emac_attach + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ + diff --git a/bsps/arm/csb337/include/bsp/irq.h b/bsps/arm/csb337/include/bsp/irq.h new file mode 100644 index 0000000000..771059a3e4 --- /dev/null +++ b/bsps/arm/csb337/include/bsp/irq.h @@ -0,0 +1,63 @@ +/* + * Interrupt handler Header file + * + * Copyright (c) 2010 embedded brains GmbH. + * + * Copyright (c) 2004 by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __IRQ_H__ +#define __IRQ_H__ + +#ifndef __asm__ + +#include +#include +#include + +#endif /* __asm__ */ + +/* possible interrupt sources on the AT91RM9200 */ +#define AT91RM9200_INT_FIQ 0 +#define AT91RM9200_INT_SYSIRQ 1 +#define AT91RM9200_INT_PIOA 2 +#define AT91RM9200_INT_PIOB 3 +#define AT91RM9200_INT_PIOC 4 +#define AT91RM9200_INT_PIOD 5 +#define AT91RM9200_INT_US0 6 +#define AT91RM9200_INT_US1 7 +#define AT91RM9200_INT_US2 8 +#define AT91RM9200_INT_US3 9 +#define AT91RM9200_INT_MCI 10 +#define AT91RM9200_INT_UDP 11 +#define AT91RM9200_INT_TWI 12 +#define AT91RM9200_INT_SPI 13 +#define AT91RM9200_INT_SSC0 14 +#define AT91RM9200_INT_SSC1 15 +#define AT91RM9200_INT_SSC2 16 +#define AT91RM9200_INT_TC0 17 +#define AT91RM9200_INT_TC1 18 +#define AT91RM9200_INT_TC2 19 +#define AT91RM9200_INT_TC3 20 +#define AT91RM9200_INT_TC4 21 +#define AT91RM9200_INT_TC5 22 +#define AT91RM9200_INT_UHP 23 +#define AT91RM9200_INT_EMAC 24 +#define AT91RM9200_INT_IRQ0 25 +#define AT91RM9200_INT_IRQ1 26 +#define AT91RM9200_INT_IRQ2 27 +#define AT91RM9200_INT_IRQ3 28 +#define AT91RM9200_INT_IRQ4 28 +#define AT91RM9200_INT_IRQ5 30 +#define AT91RM9200_INT_IRQ6 31 +#define AT91RM9200_MAX_INT 32 + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (AT91RM9200_MAX_INT - 1) + +#endif /* __IRQ_H__ */ diff --git a/bsps/arm/csb337/include/font8x16.h b/bsps/arm/csb337/include/font8x16.h new file mode 100644 index 0000000000..0445b67668 --- /dev/null +++ b/bsps/arm/csb337/include/font8x16.h @@ -0,0 +1,3615 @@ +/** + * @file + * + * @ingroup arm_csb337 + * + * @brief Simple 8 x 16 font, printable characters only. + */ + +/** + * @defgroup csb337_font Simple 8 x 16 font + * + * @ingroup arm_csb337 + * + * @brief Simple 8 x 16 font, printable characters only. + */ + +/* + * font8x16.h + * + * Simple 8 x 16 font printable Characters only. To lookup, subtract + * FIRST_CHAR from the Character, multiply x FONT_HEIGHT and get the next + * FONT_WIDTH bytes. + * + * Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ + * which includes this notice: + * + ************************************************************************** + * General notice: + * This code is part of a boot-monitor package developed as a generic base + * platform for embedded system designs. As such, it is likely to be + * distributed to various projects beyond the control of the original + * author. Please notify the author of any enhancements made or bugs found + * so that all may benefit from the changes. In addition, notification back + * to the author will allow the new user to pick up changes that may have + * been made by other users after this version of the code was distributed. + * + * Note1: the majority of this code was edited with 4-space tabs. + * Note2: as more and more contributions are accepted, the term "author" + * is becoming a mis-representation of credit. + * + * Original author: Ed Sutter + * Email: esutter@alcatel-lucent.com + * Phone: 908-582-2351 + ************************************************************************** + * + * Ed Sutter has been informed that this code is being used in RTEMS. + * + * This code was reformatted by Joel Sherrill from OAR Corporation and + * Fernando Nicodemos from NCB - Sistemas + * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding + * standards and to eliminate C++ style comments. + */ + +#define FONT_WIDTH 8 +#define FONT_HEIGHT 16 +#define FIRST_CHAR 0x20 +#define LAST_CHAR 0x7F +#define CURSOR_ON 0x7F +#define CURSOR_OFF 0x20 + +const uint8_t font8x16[] = { + + +/* Character (0x20): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character ! (0x21): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | **** | + | **** | + | **** | + | **** | + | ** | + | ** | + | | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x18, +0x3C, +0x3C, +0x3C, +0x3C, +0x18, +0x18, +0x00, +0x18, +0x18, +0x00, +0x00, +0x00, +0x00, + +/* Character " (0x22): + ht=16, width=8 + +--------+ + | | + | | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x36, +0x36, +0x36, +0x36, +0x14, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character # (0x23): + ht=16, width=8 + +--------+ + | | + | | + | ** ** | + | ** ** | + | ** ** | + |******* | + | ** ** | + | ** ** | + |******* | + | ** ** | + | ** ** | + | ** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x6C, +0x6C, +0x6C, +0xFE, +0x6C, +0x6C, +0xFE, +0x6C, +0x6C, +0x6C, +0x00, +0x00, +0x00, +0x00, + +/* Character $ (0x24): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | ***** | + |** ** | + |** * | + | **** | + | **** | + | * ** | + |** ** | + | ***** | + | ** | + | ** | + | | + | | + +--------+ */ +0x00, +0x00, +0x18, +0x18, +0x7C, +0xC6, +0xC0, +0x78, +0x3C, +0x06, +0xC6, +0x7C, +0x18, +0x18, +0x00, +0x00, + +/* Character % (0x25): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ** * | + | ** ** | + | ** | + | ** | + | ** | + | ** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x62, +0x66, +0x0C, +0x18, +0x30, +0x66, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character & (0x26): + ht=16, width=8 + +--------+ + | | + | | + | *** | + | ** ** | + | *** | + | ** | + | *** ** | + | ****** | + |** ** | + |** ** | + |** ** | + | *** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x38, +0x6C, +0x38, +0x30, +0x76, +0x7E, +0xCC, +0xCC, +0xCC, +0x76, +0x00, +0x00, +0x00, +0x00, + +/* Character ' (0x27): + ht=16, width=8 + +--------+ + | | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x0C, +0x0C, +0x0C, +0x18, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character ( (0x28): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x0C, +0x18, +0x30, +0x30, +0x30, +0x30, +0x30, +0x30, +0x18, +0x0C, +0x00, +0x00, +0x00, +0x00, + +/* Character ) (0x29): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x30, +0x18, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0x18, +0x30, +0x00, +0x00, +0x00, +0x00, + +/* Character * (0x2A): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ** ** | + | *** | + |******* | + | *** | + | ** ** | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x6C, +0x38, +0xFE, +0x38, +0x6C, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character (0x2B): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ** | + | ** | + | ****** | + | ** | + | ** | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x18, +0x18, +0x7E, +0x18, +0x18, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character , (0x2C): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | | + | | + | | + | | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x0C, +0x0C, +0x0C, +0x18, +0x00, +0x00, +0x00, + +/* Character - (0x2D): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | | + | | + | ****** | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0xFE, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character . (0x2E): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x18, +0x18, +0x00, +0x00, +0x00, +0x00, + +/* Character / (0x2F): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | * | + | ** | + | ** | + | ** | + | ** | + | ** | + | * | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x02, +0x06, +0x0C, +0x18, +0x30, +0x60, +0xC0, +0x80, +0x00, +0x00, +0x00, +0x00, + +/* Character 0 (0x30): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** *** | + |** **** | + |**** ** | + |*** ** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xCE, +0xDE, +0xF6, +0xE6, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character 1 (0x31): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | **** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ****** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x18, +0x78, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x7E, +0x00, +0x00, +0x00, +0x00, + +/* Character 2 (0x32): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + | ** | + | ** | + | ** | + | ** | + | ** | + |** ** | + |******* | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0x06, +0x0C, +0x18, +0x30, +0x60, +0xC6, +0xFE, +0x00, +0x00, +0x00, +0x00, + +/* Character 3 (0x33): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + | ** | + | ** | + | **** | + | ** | + | ** | + | ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0x06, +0x06, +0x3C, +0x06, +0x06, +0x06, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character 4 (0x34): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | *** | + | **** | + | ** ** | + |** ** | + |** ** | + |******* | + | ** | + | ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x0C, +0x1C, +0x3C, +0x6C, +0xCC, +0xCC, +0xFE, +0x0C, +0x0C, +0x1E, +0x00, +0x00, +0x00, +0x00, + +/* Character 5 (0x35): + ht=16, width=8 + +--------+ + | | + | | + |******* | + |** | + |** | + |** | + |****** | + | ** | + | ** | + | ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFE, +0xC0, +0xC0, +0xC0, +0xFC, +0x06, +0x06, +0x06, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character 6 (0x36): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** | + |** | + |****** | + |** ** | + |** ** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC0, +0xC0, +0xFC, +0xC6, +0xC6, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character 7 (0x37): + ht=16, width=8 + +--------+ + | | + | | + |******* | + |** ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFE, +0xC6, +0x06, +0x0C, +0x18, +0x30, +0x30, +0x30, +0x30, +0x30, +0x00, +0x00, +0x00, +0x00, + +/* Character 8 (0x38): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** ** | + | ***** | + |** ** | + |** ** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC6, +0x7C, +0xC6, +0xC6, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character 9 (0x39): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** ** | + |** ** | + | ****** | + | ** | + | ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC6, +0xC6, +0x7E, +0x06, +0x06, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character : (0x3A): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ** | + | ** | + | | + | | + | ** | + | ** | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x0C, +0x0C, +0x00, +0x00, +0x0C, +0x0C, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character ; (0x3B): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ** | + | ** | + | | + | | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x0C, +0x0C, +0x00, +0x00, +0x0C, +0x0C, +0x0C, +0x18, +0x00, +0x00, +0x00, + +/* Character < (0x3C): + ht=16, width=8 + +--------+ + | | + | | + | | + | ** | + | ** | + | ** | + | ** | + |** | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x0C, +0x18, +0x30, +0x60, +0xC0, +0x60, +0x30, +0x18, +0x0C, +0x00, +0x00, +0x00, +0x00, + +/* Character = (0x3D): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | | + |******* | + | | + |******* | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0xFE, +0x00, +0xFE, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character > (0x3E): + ht=16, width=8 + +--------+ + | | + | | + | | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x60, +0x30, +0x18, +0x0C, +0x06, +0x0C, +0x18, +0x30, +0x60, +0x00, +0x00, +0x00, +0x00, + +/* Character ? (0x3F): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + | ** | + | ** | + | ** | + | ** | + | | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0x0C, +0x18, +0x18, +0x18, +0x00, +0x18, +0x18, +0x00, +0x00, +0x00, +0x00, + +/* Character @ (0x40): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** ** | + |** **** | + |** **** | + |** **** | + |** *** | + |** | + | ****** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC6, +0xDE, +0xDE, +0xDE, +0xDC, +0xC0, +0x7E, +0x00, +0x00, +0x00, +0x00, + +/* Character A (0x41): + ht=16, width=8 + +--------+ + | | + | | + | *** | + | ** ** | + |** ** | + |** ** | + |** ** | + |******* | + |** ** | + |** ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x38, +0x6C, +0xC6, +0xC6, +0xC6, +0xFE, +0xC6, +0xC6, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character B (0x42): + ht=16, width=8 + +--------+ + | | + | | + |****** | + | ** ** | + | ** ** | + | ** ** | + | ***** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + |****** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFC, +0x66, +0x66, +0x66, +0x7C, +0x66, +0x66, +0x66, +0x66, +0xFC, +0x00, +0x00, +0x00, +0x00, + +/* Character C (0x43): + ht=16, width=8 + +--------+ + | | + | | + | **** | + | ** ** | + |** * | + |** | + |** | + |** | + |** | + |** * | + | ** ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x3C, +0x66, +0xC2, +0xC0, +0xC0, +0xC0, +0xC0, +0xC2, +0x66, +0x3C, +0x00, +0x00, +0x00, +0x00, + +/* Character D (0x44): + ht=16, width=8 + +--------+ + | | + | | + |***** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + |***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xF8, +0x6C, +0x66, +0x66, +0x66, +0x66, +0x66, +0x66, +0x6C, +0xF8, +0x00, +0x00, +0x00, +0x00, + +/* Character E (0x45): + ht=16, width=8 + +--------+ + | | + | | + |******* | + | ** ** | + | ** | + | ** * | + | ***** | + | ** * | + | ** | + | ** | + | ** ** | + |******* | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFE, +0x66, +0x60, +0x64, +0x7C, +0x64, +0x60, +0x60, +0x66, +0xFE, +0x00, +0x00, +0x00, +0x00, + +/* Character F (0x46): + ht=16, width=8 + +--------+ + | | + | | + |******* | + | ** ** | + | ** | + | ** * | + | ***** | + | ** * | + | ** | + | ** | + | ** | + |**** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFE, +0x66, +0x60, +0x64, +0x7C, +0x64, +0x60, +0x60, +0x60, +0xF0, +0x00, +0x00, +0x00, +0x00, + +/* Character G (0x47): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** | + |** | + |** | + |** *** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC0, +0xC0, +0xC0, +0xCE, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character H (0x48): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + |******* | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0xC6, +0xFE, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character I (0x49): + ht=16, width=8 + +--------+ + | | + | | + | **** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x3C, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x3C, +0x00, +0x00, +0x00, +0x00, + +/* Character J (0x4A): + ht=16, width=8 + +--------+ + | | + | | + | **** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + |** ** | + |** ** | + | *** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x3C, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0xD8, +0xD8, +0x70, +0x00, +0x00, +0x00, +0x00, + +/* Character K (0x4B): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + |**** | + |**** | + |** ** | + |** ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xCC, +0xD8, +0xF0, +0xF0, +0xD8, +0xCC, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character L (0x4C): + ht=16, width=8 + +--------+ + | | + | | + |**** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** * | + | ** ** | + |******* | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xF0, +0x60, +0x60, +0x60, +0x60, +0x60, +0x60, +0x62, +0x66, +0xFE, +0x00, +0x00, +0x00, +0x00, + +/* Character M (0x4D): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |*** *** | + |*** *** | + |******* | + |** * ** | + |** * ** | + |** * ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xEE, +0xEE, +0xFE, +0xD6, +0xD6, +0xD6, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character N (0x4E): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |*** ** | + |*** ** | + |**** ** | + |** **** | + |** *** | + |** *** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xE6, +0xE6, +0xF6, +0xDE, +0xCE, +0xCE, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character O (0x4F): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character P (0x50): + ht=16, width=8 + +--------+ + | | + | | + |****** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ***** | + | ** | + | ** | + | ** | + |**** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFC, +0x66, +0x66, +0x66, +0x66, +0x7C, +0x60, +0x60, +0x60, +0xF0, +0x00, +0x00, +0x00, +0x00, + +/* Character Q (0x51): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** * ** | + |** * ** | + | ***** | + | ** | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xD6, +0xD6, +0x7C, +0x06, +0x00, +0x00, +0x00, + +/* Character R (0x52): + ht=16, width=8 + +--------+ + | | + | | + |****** | + | ** ** | + | ** ** | + | ** ** | + | ***** | + | **** | + | ** ** | + | ** ** | + | ** ** | + |*** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFC, +0x66, +0x66, +0x66, +0x7C, +0x78, +0x6C, +0x66, +0x66, +0xE6, +0x00, +0x00, +0x00, +0x00, + +/* Character S (0x53): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** | + |** | + | *** | + | *** | + | ** | + | ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC0, +0xC0, +0x70, +0x1C, +0x06, +0x06, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character T (0x54): + ht=16, width=8 + +--------+ + | | + | | + | ****** | + | * ** * | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7E, +0x5A, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x3C, +0x00, +0x00, +0x00, +0x00, + +/* Character U (0x55): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character V (0x56): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | ** ** | + | *** | + | * | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0x6C, +0x38, +0x10, +0x00, +0x00, +0x00, +0x00, + +/* Character W (0x57): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |** ** | + |** * ** | + |** * ** | + |** * ** | + |******* | + |*** *** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0xD6, +0xD6, +0xD6, +0xFE, +0xEE, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character X (0x58): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |** ** | + | ** ** | + | *** | + | *** | + | ** ** | + |** ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0x6C, +0x38, +0x38, +0x6C, +0xC6, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character Y (0x59): + ht=16, width=8 + +--------+ + | | + | | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | **** | + | ** | + | ** | + | ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x66, +0x66, +0x66, +0x66, +0x66, +0x3C, +0x18, +0x18, +0x18, +0x3C, +0x00, +0x00, +0x00, +0x00, + +/* Character Z (0x5A): + ht=16, width=8 + +--------+ + | | + | | + |******* | + |** ** | + |* ** | + | ** | + | ** | + | ** | + | ** | + |** * | + |** ** | + |******* | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFE, +0xC6, +0x86, +0x0C, +0x18, +0x30, +0x60, +0xC2, +0xC6, +0xFE, +0x00, +0x00, +0x00, +0x00, + +/* Character [ (0x5B): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0x60, +0x60, +0x60, +0x60, +0x60, +0x60, +0x60, +0x60, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character \ (0x5C): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + |* | + |** | + | ** | + | ** | + | ** | + | ** | + | ** | + | * | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x80, +0xC0, +0x60, +0x30, +0x18, +0x0C, +0x06, +0x02, +0x00, +0x00, +0x00, +0x00, + +/* Character ] (0x5D): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character ^ (0x5E): + ht=16, width=8 + +--------+ + | | + | * | + | *** | + | ** ** | + |** ** | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x10, +0x38, +0x6C, +0xC6, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character _ (0x5F): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + |********| + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0xFF, +0x00, +0x00, + +/* Character ` (0x60): + ht=16, width=8 + +--------+ + | | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x18, +0x18, +0x18, +0x0C, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character A (0x61): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | **** | + | ** | + | ***** | + |** ** | + |** ** | + |** *** | + | *** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x78, +0x0C, +0x7C, +0xCC, +0xCC, +0xDC, +0x76, +0x00, +0x00, +0x00, +0x00, + +/* Character B (0x62): + ht=16, width=8 + +--------+ + | | + | | + |*** | + | ** | + | ** | + | ***** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + |****** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xE0, +0x60, +0x60, +0x7C, +0x66, +0x66, +0x66, +0x66, +0x66, +0xFC, +0x00, +0x00, +0x00, +0x00, + +/* Character C (0x63): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ***** | + |** ** | + |** | + |** | + |** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x7C, +0xC6, +0xC0, +0xC0, +0xC0, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character D (0x64): + ht=16, width=8 + +--------+ + | | + | | + | *** | + | ** | + | ** | + | ***** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | ****** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x1C, +0x0C, +0x0C, +0x7C, +0xCC, +0xCC, +0xCC, +0xCC, +0xCC, +0x7E, +0x00, +0x00, +0x00, +0x00, + +/* Character E (0x65): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ***** | + |** ** | + |** ** | + |******* | + |** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xFE, +0xC0, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character F (0x66): + ht=16, width=8 + +--------+ + | | + | | + | *** | + | ** ** | + | ** | + | ** | + |****** | + | ** | + | ** | + | ** | + | ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x1C, +0x36, +0x30, +0x30, +0xFC, +0x30, +0x30, +0x30, +0x30, +0x78, +0x00, +0x00, +0x00, +0x00, + +/* Character g (0x67): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | *** ** | + |** *** | + |** ** | + |** ** | + |** *** | + | *** ** | + | ** | + |** ** | + | ***** | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x76, +0xCE, +0xC6, +0xC6, +0xCE, +0x76, +0x06, +0xC6, +0x7C, +0x00, +0x00, + +/* Character h (0x68): + ht=16, width=8 + +--------+ + | | + | | + |*** | + | ** | + | ** | + | ***** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + |*** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xE0, +0x60, +0x60, +0x7C, +0x66, +0x66, +0x66, +0x66, +0x66, +0xE6, +0x00, +0x00, +0x00, +0x00, + +/* Character i (0x69): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | | + | *** | + | ** | + | ** | + | ** | + | ** | + | ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x18, +0x18, +0x00, +0x38, +0x18, +0x18, +0x18, +0x18, +0x18, +0x3C, +0x00, +0x00, +0x00, +0x00, + +/* Character j (0x6A): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | | + | *** | + | ** | + | ** | + | ** | + | ** | + | ** | + |** ** | + |** ** | + | **** | + | | + | | + +--------+ */ +0x00, +0x00, +0x0C, +0x0C, +0x00, +0x1C, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0xCC, +0xCC, +0x78, +0x00, +0x00, + +/* Character k (0x6B): + ht=16, width=8 + +--------+ + | | + | | + |*** | + | ** | + | ** | + | ** ** | + | ** ** | + | ** ** | + | **** | + | ** ** | + | ** ** | + |*** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xE0, +0x60, +0x60, +0x66, +0x66, +0x6C, +0x78, +0x6C, +0x66, +0xE6, +0x00, +0x00, +0x00, +0x00, + +/* Character l (0x6C): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | *** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x1C, +0x00, +0x00, +0x00, +0x00, + +/* Character m (0x6D): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ** ** | + |******* | + |** * ** | + |** * ** | + |** ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x6C, +0xFE, +0xD6, +0xD6, +0xC6, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character n (0x6E): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** *** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xDC, +0x66, +0x66, +0x66, +0x66, +0x66, +0x66, +0x00, +0x00, +0x00, +0x00, + +/* Character o (0x6F): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ***** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character p (0x70): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** *** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ***** | + | ** | + | ** | + |**** | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xDC, +0x66, +0x66, +0x66, +0x66, +0x7C, +0x60, +0x60, +0xF0, +0x00, +0x00, + +/* Character q (0x71): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | *** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | ***** | + | ** | + | ** | + | **** | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x76, +0xCC, +0xCC, +0xCC, +0xCC, +0x7C, +0x0C, +0x0C, +0x1E, +0x00, +0x00, + +/* Character r (0x72): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** *** | + | ** ** | + | ** | + | ** | + | ** | + | ** | + |**** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xDC, +0x66, +0x60, +0x60, +0x60, +0x60, +0xF0, +0x00, +0x00, +0x00, +0x00, + +/* Character s (0x73): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ***** | + |** ** | + |** | + | ***** | + | ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x7C, +0xC6, +0xC0, +0x7C, +0x06, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character t (0x74): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | ** | + |****** | + | ** | + | ** | + | ** | + | ** | + | ** ** | + | *** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x30, +0x30, +0x30, +0xFC, +0x30, +0x30, +0x30, +0x30, +0x36, +0x1C, +0x00, +0x00, +0x00, +0x00, + +/* Character u (0x75): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | *** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xCC, +0xCC, +0xCC, +0xCC, +0xCC, +0xCC, +0x76, +0x00, +0x00, +0x00, +0x00, + +/* Character v (0x76): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + | ** ** | + | *** | + | * | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0xC6, +0x6C, +0x38, +0x10, +0x00, +0x00, +0x00, +0x00, + +/* Character w (0x77): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** ** | + |** ** | + |** * ** | + |** * ** | + |** * ** | + |******* | + | ** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xC6, +0xC6, +0xD6, +0xD6, +0xD6, +0xFE, +0x6C, +0x00, +0x00, +0x00, +0x00, + +/* Character x (0x78): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** ** | + |** ** | + | ** ** | + | *** | + | ** ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xC6, +0xC6, +0x6C, +0x38, +0x6C, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character y (0x79): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + |** *** | + | *** ** | + | ** | + |** ** | + | ***** | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0xC6, +0xCE, +0x76, +0x06, +0xC6, +0x7C, +0x00, +0x00, + +/* Character z (0x7A): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |******* | + |* ** | + | ** | + | ** | + | ** | + | ** * | + |******* | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xFE, +0x86, +0x0C, +0x18, +0x30, +0x62, +0xFE, +0x00, +0x00, +0x00, +0x00, + +/* Character { (0x7B): + ht=16, width=8 + +--------+ + | | + | | + | *** | + | ** | + | ** | + | ** | + | *** | + | ** | + | ** | + | ** | + | ** | + | *** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x0E, +0x18, +0x18, +0x18, +0x70, +0x18, +0x18, +0x18, +0x18, +0x0E, +0x00, +0x00, +0x00, +0x00, + +/* Character | (0x7C): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | ** | + | ** | + | | + | ** | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x18, +0x18, +0x18, +0x18, +0x00, +0x18, +0x18, +0x18, +0x18, +0x18, +0x00, +0x00, +0x00, +0x00, + +/* Character } (0x7D): + ht=16, width=8 + +--------+ + | | + | | + | *** | + | ** | + | ** | + | ** | + | *** | + | ** | + | ** | + | ** | + | ** | + | *** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x70, +0x18, +0x18, +0x18, +0x0E, +0x18, +0x18, +0x18, +0x18, +0x70, +0x00, +0x00, +0x00, +0x00, + +/* Character ~ (0x7E): + ht=16, width=8 + +--------+ + | | + | | + | *** ** | + |** *** | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x76, +0xDC, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character DELTA (0x7F): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | * | + | *** | + | *** | + | ** ** | + | ** ** | + |******* | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x10, +0x38, +0x38, +0x6C, +0x6C, +0xFE, +0x00, +0x00, +0x00, +0x00, +0x00, +}; diff --git a/bsps/arm/csb337/include/sed1356.h b/bsps/arm/csb337/include/sed1356.h new file mode 100644 index 0000000000..d4451ab7e1 --- /dev/null +++ b/bsps/arm/csb337/include/sed1356.h @@ -0,0 +1,52 @@ +/** + * @file + * + * @ingroup arm_csb337 + * + * @brief Public Interface for SED Video Controller Operations. + */ + +/** + * @defgroup csb337_sed1356 SED Video Controller + * + * @ingroup arm_csb337 + * + * @brief Public Interface for SED Video Controller Operations. + */ + +/* + * Public Interface for SED Video Controller Operations + * + * COPYRIGHT (c) 1989-2009. + * On-Line Applications Research Corporation (OAR). + * + * Modified by Fernando Nicodemos + * from NCB - Sistemas Embarcados Ltda. (Brazil) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SED1356_h +#define __SED1356_h + +void sed_init(void); + +int sed_frame_buffer_size(void); + +void sed_clr_row(int char_row); + +void sed_putchar(char c); + +void sed_putstring(char *s); + +void sed_clearscreen(void); + +void sed_write_frame_buffer( + uint32_t i, + uint16_t wr16 +); + +#endif +/* end of file */ diff --git a/bsps/arm/csb337/include/sed1356_16bit.h b/bsps/arm/csb337/include/sed1356_16bit.h new file mode 100644 index 0000000000..5ccf85d01c --- /dev/null +++ b/bsps/arm/csb337/include/sed1356_16bit.h @@ -0,0 +1,566 @@ +/** + * @file + * + * @ingroup arm_csb337 + * + * @brief SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) + * 16-Bit access mode + */ + +/** + * @defgroup csb337_sed1356 SED Video Controller. + * + * @ingroup arm_csb337 + * + * @brief SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) + * 16-Bit access mode + */ + +/* + * sed1356.h: SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) + * 16-Bit access mode + * + * Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ + * which includes this notice: + * + ************************************************************************** + * General notice: + * This code is part of a boot-monitor package developed as a generic base + * platform for embedded system designs. As such, it is likely to be + * distributed to various projects beyond the control of the original + * author. Please notify the author of any enhancements made or bugs found + * so that all may benefit from the changes. In addition, notification back + * to the author will allow the new user to pick up changes that may have + * been made by other users after this version of the code was distributed. + * + * Note1: the majority of this code was edited with 4-space tabs. + * Note2: as more and more contributions are accepted, the term "author" + * is becoming a mis-representation of credit. + * + * Original author: Ed Sutter + * Email: esutter@alcatel-lucent.com + * Phone: 908-582-2351 + ************************************************************************** + * + * Ed Sutter has been informed that this code is being used in RTEMS. + * + * The code has been reformatted by Joel Sherrill from OAR Corporation and + * Fernando Nicodemos from NCB - Sistemas + * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding standards + * and to eliminate C++ style comments. + */ + +#ifndef __sed1356_16bit_h +#define __sed1356_16bit_h + +#include "bits.h" +/*------------------------------------------------------------------------ + * cpu specific code must define the following board specific macros. + * in cpuio.h. These examples assume the SED135x has been placed in + * the correct endian mode via hardware. + * #define SED_MEM_BASE 0xf0600000 <-- just example addresses, + * #define SED_REG_BASE 0xf0400000 <-- define for each board + * #define SED_STEP 1 <-- 1 = device is on 16-bit boundry, 2 = 32-bit boundry, 4 = 64-bit boundry + * #define SED_REG16(_x_) *(vushortr *)(SED_REG_BASE + (_x_ * SED_STEP)) // Control/Status Registers + * #define RD_FB16(_reg_,_val_) ((_val_) = *((vushort *)((SED_MEM_BASE + (_reg_ * SED_STEP))))) + * #define WR_FB16(_reg_,_val_) (*((vushort *)((SED_MEM_BASE + (_reg_ * 2)))) = (_val_)) + * Big endian processors + * #define H2SED(_x_) ((((x) & 0xff00U) >> 8) | (((x) & 0x00ffU) << 8)) + * Little endian + * #define H2SED(_x_) (_x_) + * + */ + +/* + * SED1356 registers - 16-Bit Access Mode. The first register + * referenced is the even addressed register. The byte offsets + * of the odd registers are shown in the comments + */ +#define SED1356_REG_REV_and_MISC SED_REG16(0x00) +#define SED1356_REG_GPIO_CFG SED_REG16(0x04) +#define SED1356_REG_GPIO_CTL SED_REG16(0x08) +#define SED1356_REG_MD_CFG_RD_LO_and_HI SED_REG16(0x0c) +#define SED1356_REG_MCLK_CFG SED_REG16(0x10) +#define SED1356_REG_LCD_PCLK_CFG SED_REG16(0x14) +#define SED1356_REG_CRT_PCLK_CFG SED_REG16(0x18) +#define SED1356_REG_MEDIA_PCLK_CFG SED_REG16(0x1c) +#define SED1356_REG_WAIT_STATE SED_REG16(0x1e) +#define SED1356_REG_MEM_CFG_and_REF_RATE SED_REG16(0x20) +#define SED1356_REG_MEM_TMG0_and_1 SED_REG16(0x2a) +#define SED1356_REG_PANEL_TYPE_and_MOD_RATE SED_REG16(0x30) +/* LCD Control registers */ +#define SED1356_REG_LCD_HOR_DISP SED_REG16(0x32) +#define SED1356_REG_LCD_HOR_NONDISP_and_START SED_REG16(0x34) +#define SED1356_REG_LCD_HOR_PULSE SED_REG16(0x36) +#define SED1356_REG_LCD_VER_DISP_HT_LO_and_HI SED_REG16(0x38) +#define SED1356_REG_LCD_VER_NONDISP_and_START SED_REG16(0x3a) +#define SED1356_REG_LCD_VER_PULSE SED_REG16(0x3c) +#define SED1356_REG_LCD_DISP_MODE_and_MISC SED_REG16(0x40) +#define SED1356_REG_LCD_DISP_START_LO_and_MID SED_REG16(0x42) +#define SED1356_REG_LCD_DISP_START_HI SED_REG16(0x44) +#define SED1356_REG_LCD_ADD_OFFSET_LO_and_HI SED_REG16(0x46) +#define SED1356_REG_LCD_PIXEL_PAN SED_REG16(0x48) +#define SED1356_REG_LCD_FIFO_THRESH_LO_and_HI SED_REG16(0x4a) +/* CRT/TV Control registers */ +#define SED1356_REG_CRT_HOR_DISP SED_REG16(0x50) +#define SED1356_REG_CRT_HOR_NONDISP_and_START SED_REG16(0x52) +#define SED1356_REG_CRT_HOR_PULSE SED_REG16(0x54) +#define SED1356_REG_CRT_VER_DISP_HT_LO_and_HI SED_REG16(0x56) +#define SED1356_REG_CRT_VER_NONDISP_and_START SED_REG16(0x58) +#define SED1356_REG_CRT_VER_PULSE_and_OUT_CTL SED_REG16(0x5a) +#define SED1356_REG_CRT_DISP_MODE SED_REG16(0x60) +#define SED1356_REG_CRT_DISP_START_LO_and_MID SED_REG16(0x62) +#define SED1356_REG_CRT_DISP_START_HI SED_REG16(0x64) +#define SED1356_REG_CRT_ADD_OFFSET_LO_and_HI SED_REG16(0x66) +#define SED1356_REG_CRT_PIXEL_PAN SED_REG16(0x68) +#define SED1356_REG_CRT_FIFO_THRESH_LO_and_HI SED_REG16(0x6a) +/* LCD Cursor Control Registers */ +#define SED1356_REG_LCD_CURSOR_CTL_and_START_ADD SED_REG16(0x70) +#define SED1356_REG_LCD_CURSOR_X_POS_LO_and_HI SED_REG16(0x72) +#define SED1356_REG_LCD_CURSOR_Y_POS_LO_and_HI SED_REG16(0x74) +#define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x76) +#define SED1356_REG_LCD_CURSOR_RED_CLR_0 SED_REG16(0x78) +#define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x7a) +#define SED1356_REG_LCD_CURSOR_RED_CLR_1 SED_REG16(0x7c) +#define SED1356_REG_LCD_CURSOR_FIFO_THRESH SED_REG16(0x7e) +/* CRT Cursor Control Registers */ +#define SED1356_REG_CRT_CURSOR_CTL_and_START_ADD SED_REG16(0x80) +#define SED1356_REG_CRT_CURSOR_X_POS_LO_and_HI SED_REG16(0x82) +#define SED1356_REG_CRT_CURSOR_Y_POS_LO_and_HI SED_REG16(0x84) +#define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x86) +#define SED1356_REG_CRT_CURSOR_RED_CLR_0 SED_REG16(0x88) +#define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x8a) +#define SED1356_REG_CRT_CURSOR_RED_CLR_1 SED_REG16(0x8c) +#define SED1356_REG_CRT_CURSOR_FIFO_THRESH SED_REG16(0x8e) +/* BitBlt Control Registers */ +#define SED1356_REG_BLT_CTL_0_and_1 SED_REG16(0x100) +#define SED1356_REG_BLT_ROP_CODE_and_BLT_OP SED_REG16(0x102) +#define SED1356_REG_BLT_SRC_START_LO_and_MID SED_REG16(0x104) +#define SED1356_REG_BLT_SRC_START_HI SED_REG16(0x106) +#define SED1356_REG_BLT_DEST_START_LO_and_MID SED_REG16(0x108) +#define SED1356_REG_BLT_DEST_START_HI SED_REG16(0x10a) +#define SED1356_REG_BLT_ADD_OFFSET_LO_and_HI SED_REG16(0x10c) +#define SED1356_REG_BLT_WID_LO_and_HI SED_REG16(0x110) +#define SED1356_REG_BLT_HGT_LO_and_HI SED_REG16(0x112) +#define SED1356_REG_BLT_BG_CLR_LO_and_HI SED_REG16(0x114) +#define SED1356_REG_BLT_FG_CLR_LO_and_HI SED_REG16(0x118) +/* Look-Up Table Control Registers */ +#define SED1356_REG_LUT_MODE SED_REG16(0x1e0) +#define SED1356_REG_LUT_ADD SED_REG16(0x1e2) +#define SED1356_REG_LUT_DATA SED_REG16(0x1e4) +/* Power and Miscellaneous Control Registers */ +#define SED1356_REG_PWR_CFG_and_STAT SED_REG16(0x1f0) +#define SED1356_REG_WATCHDOG_CTL SED_REG16(0x1f4) +#define SED1356_REG_DISP_MODE SED_REG16(0x1fc) + +/* + * Bit Assignments - Little Endian, Use H2SED() macro to access + * + * SED1356_REG_REV_and_MISC - even + */ +#define SED1356_REV_ID_MASK 0xfc /* ID bits - masks off the rev bits */ +#define SED1356_REV_ID_1356 BIT4 +#define SED1356_REV_ID_1355 BIT3 + +/* SED1356_REG_REV_and_MISC - odd */ +#define SED1356_MISC_HOST_DIS BIT7 << 8 /* 0 = enable host access, 1 = disable */ + +/* SED1356_REG_GPIO_CFG and SED1356_REG_GPIO_STAT */ +#define SED1356_GPIO_GPIO3 BIT3 /* 0 = input, 1 = output, if configured as GPIO */ +#define SED1356_GPIO_GPIO2 BIT2 +#define SED1356_GPIO_GPIO1 BIT1 + +/* SED1356_REG_MCLK_CFG */ +#define SED1356_MCLK_DIV2 BIT4 +#define SED1356_MCLK_SRC_BCLK BIT0 +#define SED1356_MCLK_SRC_CLKI 0x00 + +/* SED1356_REG_LCD_PCLK_CFG, SED1356_REG_CRT_PCLK_CFG + * and SED1356_REG_MEDIA_PCLK_CFG + */ +#define SED1356_PCLK_X2 BIT7 /* SED1356_REG_CRT_PCLK_CFG only */ +#define SED1356_PCLK_DIV1 0x00 << 4 +#define SED1356_PCLK_DIV2 0x01 << 4 +#define SED1356_PCLK_DIV3 0x02 << 4 +#define SED1356_PCLK_DIV4 0x03 << 4 +#define SED1356_PCLK_SRC_CLKI 0x00 +#define SED1356_PCLK_SRC_BCLK 0x01 +#define SED1356_PCLK_SRC_CLKI2 0x02 +#define SED1356_PCLK_SRC_MCLK 0x03 + +/* SED1356_REG_MEM_CFG_and_REF_RATE - even */ +#define SED1356_MEM_CFG_2CAS_EDO 0x00 +#define SED1356_MEM_CFG_2CAS_FPM 0x01 +#define SED1356_MEM_CFG_2WE_EDO 0x02 +#define SED1356_MEM_CFG_2WE_FPM 0x03 +#define SED1356_MEM_CFG_MASK 0x03 + +/* SED1356_REG_MEM_CFG_and_REF_RATE - odd */ +#define SED1356_REF_TYPE_CBR 0x00 << 6 << 8 +#define SED1356_REF_TYPE_SELF 0x01 << 6 << 8 +#define SED1356_REF_TYPE_NONE 0x02 << 6 << 8 +#define SED1356_REF_TYPE_MASK 0x03 << 6 << 8 +#define SED1356_REF_RATE_64 0x00 << 0 << 8 /* MCLK / 64 */ +#define SED1356_REF_RATE_128 0x01 << 0 << 8 /* MCLK / 128 */ +#define SED1356_REF_RATE_256 0x02 << 0 << 8 /* MCLK / 256 */ +#define SED1356_REF_RATE_512 0x03 << 0 << 8 /* MCLK / 512 */ +#define SED1356_REF_RATE_1024 0x04 << 0 << 8 /* MCLK / 1024 */ +#define SED1356_REF_RATE_2048 0x05 << 0 << 8 /* MCLK / 2048 */ +#define SED1356_REF_RATE_4096 0x06 << 0 << 8 /* MCLK / 4096 */ +#define SED1356_REF_RATE_8192 0x07 << 0 << 8 /* MCLK / 8192 */ +#define SED1356_REF_RATE_MASK 0x07 << 0 << 8 /* MCLK / 8192 */ + +/* SED1356_REG_MEM_TMG0_and_1 - even */ +#define SED1356_MEM_TMG0_EDO50_MCLK40 0x01 +#define SED1356_MEM_TMG0_EDO50_MCLK33 0x01 +#define SED1356_MEM_TMG0_EDO60_MCLK33 0x01 +#define SED1356_MEM_TMG0_EDO50_MCLK30 0x12 +#define SED1356_MEM_TMG0_EDO60_MCLK30 0x01 +#define SED1356_MEM_TMG0_EDO70_MCLK30 0x00 +#define SED1356_MEM_TMG0_EDO50_MCLK25 0x12 +#define SED1356_MEM_TMG0_EDO60_MCLK25 0x12 +#define SED1356_MEM_TMG0_EDO70_MCLK25 0x01 +#define SED1356_MEM_TMG0_EDO80_MCLK25 0x00 +#define SED1356_MEM_TMG0_EDO50_MCLK20 0x12 +#define SED1356_MEM_TMG0_EDO60_MCLK20 0x12 +#define SED1356_MEM_TMG0_EDO70_MCLK20 0x12 +#define SED1356_MEM_TMG0_EDO80_MCLK20 0x01 +#define SED1356_MEM_TMG0_FPM50_MCLK25 0x12 +#define SED1356_MEM_TMG0_FPM60_MCLK25 0x01 +#define SED1356_MEM_TMG0_FPM50_MCLK20 0x12 +#define SED1356_MEM_TMG0_FPM60_MCLK20 0x12 +#define SED1356_MEM_TMG0_FPM70_MCLK20 0x11 +#define SED1356_MEM_TMG0_FPM80_MCLK20 0x01 + +/* SED1356_REG_MEM_TMG0_and_1 - odd */ +#define SED1356_MEM_TMG1_EDO50_MCLK40 0x01 << 8 +#define SED1356_MEM_TMG1_EDO50_MCLK33 0x01 << 8 +#define SED1356_MEM_TMG1_EDO60_MCLK33 0x01 << 8 +#define SED1356_MEM_TMG1_EDO50_MCLK30 0x02 << 8 +#define SED1356_MEM_TMG1_EDO60_MCLK30 0x01 << 8 +#define SED1356_MEM_TMG1_EDO70_MCLK30 0x00 << 8 +#define SED1356_MEM_TMG1_EDO50_MCLK25 0x02 << 8 +#define SED1356_MEM_TMG1_EDO60_MCLK25 0x02 << 8 +#define SED1356_MEM_TMG1_EDO70_MCLK25 0x01 << 8 +#define SED1356_MEM_TMG1_EDO80_MCLK25 0x01 << 8 +#define SED1356_MEM_TMG1_EDO50_MCLK20 0x02 << 8 +#define SED1356_MEM_TMG1_EDO60_MCLK20 0x02 << 8 +#define SED1356_MEM_TMG1_EDO70_MCLK20 0x02 << 8 +#define SED1356_MEM_TMG1_EDO80_MCLK20 0x01 << 8 +#define SED1356_MEM_TMG1_FPM50_MCLK25 0x02 << 8 +#define SED1356_MEM_TMG1_FPM60_MCLK25 0x01 << 8 +#define SED1356_MEM_TMG1_FPM50_MCLK20 0x02 << 8 +#define SED1356_MEM_TMG1_FPM60_MCLK20 0x02 << 8 +#define SED1356_MEM_TMG1_FPM70_MCLK20 0x02 << 8 +#define SED1356_MEM_TMG1_FPM80_MCLK20 0x01 << 8 + + +/* Bit definitions + * + * SED1356_REG_PANEL_TYPE_AND_MOD_RATE - even + */ +#define SED1356_PANEL_TYPE_EL BIT7 +#define SED1356_PANEL_TYPE_4_9 (0x00 << 4) /* Passive 4-Bit, TFT 9-Bit */ +#define SED1356_PANEL_TYPE_8_12 (0x01 << 4) /* Passive 8-Bit, TFT 12-Bit */ +#define SED1356_PANEL_TYPE_16 (0x02 << 4) /* Passive 16-Bit, or TFT 18-Bit */ +#define SED1356_PANEL_TYPE_MASK (0x03 << 4) +#define SED1356_PANEL_TYPE_FMT BIT3 /* 0 = Passive Format 1, 1 = Passive Format 2 */ +#define SED1356_PANEL_TYPE_CLR BIT2 /* 0 = Passive Mono, 1 = Passive Color */ +#define SED1356_PANEL_TYPE_DUAL BIT1 /* 0 = Passive Single, 1 = Passive Dual */ +#define SED1356_PANEL_TYPE_TFT BIT0 /* 0 = Passive, 1 = TFT (DUAL, FMT & CLR are don't cares) */ + +/* SED1356_REG_CRT_HOR_PULSE, SED1356_REG_CRT_VER_PULSE, + * SED1356_REG_LCD_HOR_PULSE and SED1356_REG_LCD_VER_PULSE + */ +#define SED1356_PULSE_POL_HIGH BIT7 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */ +#define SED1356_PULSE_POL_LOW 0x00 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */ +#define SED1356_PULSE_WID(_x_) (_x_ & 0x0f) /* Pulse Width in Pixels */ + +/* SED1356_LCD_DISP_MODE_and_MISC - even */ +#define SED1356_LCD_DISP_BLANK BIT7 /* 1 = Blank LCD Display */ +#define SED1356_LCD_DISP_SWIV_NORM (0x00 << 4) /* Used with SED1356_REG_DISP_MODE Bit 6 */ +#define SED1356_LCD_DISP_SWIV_90 (0x00 << 4) +#define SED1356_LCD_DISP_SWIV_180 (0x01 << 4) +#define SED1356_LCD_DISP_SWIV_270 (0x01 << 4) +#define SED1356_LCD_DISP_SWIV_MASK (0x01 << 4) +#define SED1356_LCD_DISP_16BPP 0x05 /* Bit Per Pixel Selection */ +#define SED1356_LCD_DISP_15BPP 0x04 +#define SED1356_LCD_DISP_8BPP 0x03 +#define SED1356_LCD_DISP_4BPP 0x02 +#define SED1356_LCD_DISP_BPP_MASK 0x07 + +/* SED1356_LCD_DISP_MODE_and_MISC - odd */ +#define SED1356_LCD_MISC_DITH BIT1 << 8 /* 1 = Dither Disable, Passive Panel Only */ +#define SED1356_LCD_MISC_DUAL BIT0 << 8 /* 1 = Dual Panel Disable, Passive Panel Only */ + +/* SED1356_REG_CRT_VER_PULSE_and_OUT_CTL - odd */ +#define SED1356_CRT_OUT_CHROM BIT5 << 8 /* 1 = TV Chrominance Filter Enable */ +#define SED1356_CRT_OUT_LUM BIT4 << 8 /* 1 = TV Luminance Filter Enable */ +#define SED1356_CRT_OUT_DAC_LVL BIT3 << 8 /* 1 = 4.6ma IREF, 0 = 9.2 IREF */ +#define SED1356_CRT_OUT_SVIDEO BIT1 << 8 /* 1 = S-Video Output, 0 = Composite Video Output */ +#define SED1356_CRT_OUT_PAL BIT0 << 8 /* 1 = PAL Format Output, 0 = NTSC Format Output */ + +/* SED1356_REG_CRT_DISP_MODE */ +#define SED1356_CRT_DISP_BLANK BIT7 /* 1 = Blank CRT Display */ +#define SED1356_CRT_DISP_16BPP 0x05 /* Bit Per Pixel Selection */ +#define SED1356_CRT_DISP_15BPP 0x04 +#define SED1356_CRT_DISP_8BPP 0x03 +#define SED1356_CRT_DISP_4BPP 0x02 +#define SED1356_CRT_DISP_BPP_MASK 0x07 + +/* SED1356_DISP_MODE */ +#define SED1356_DISP_SWIV_NORM (0x00 << 6) /* Used with SED1356_LCD_DISP_MODE Bit 4 */ +#define SED1356_DISP_SWIV_90 (0x01 << 6) +#define SED1356_DISP_SWIV_180 (0x00 << 6) +#define SED1356_DISP_SWIV_270 (0x01 << 6) +#define SED1356_DISP_MODE_OFF 0x00 /* All Displays Off */ +#define SED1356_DISP_MODE_LCD 0x01 /* LCD Only */ +#define SED1356_DISP_MODE_CRT 0x02 /* CRT Only */ +#define SED1356_DISP_MODE_LCD_CRT 0x03 /* Simultaneous LCD and CRT */ +#define SED1356_DISP_MODE_TV 0x04 /* TV Only, Flicker Filter Off */ +#define SED1356_DISP_MODE_TV_LCD 0x05 /* Simultaneous LCD and TV, Flicker Filter Off */ +#define SED1356_DISP_MODE_TV_FLICK 0x06 /* TV Only, Flicker Filter On */ +#define SED1356_DISP_MODE_TV_LCD_FLICK 0x07 /* Simultaneous LCD and TV, Flicker Filter On */ + +/* SED1356_REG_PWR_CFG and SED1356_REG_PWR_STAT */ +#define SED1356_PWR_PCLK BIT1 /* SED1356_REG_PWR_STAT only */ +#define SED1356_PWR_MCLK BIT0 + +/* SED1356_REG_VER_NONDISP */ +#define SED1356_VER_NONDISP BIT7 /* vertical retrace status 1 = in retrace */ + +/* Display size defines */ +extern long PIXELS_PER_ROW; +extern long PIXELS_PER_COL; +#define BYTES_PER_PIXEL 2 +extern long COLS_PER_SCREEN; +extern long ROWS_PER_SCREEN; + +/* 16-bit pixels are RGB 565 - LSB of RED and BLUE are tied low at the */ +/* LCD Interface, while the LSB of GREEN is loaded as 0 */ +#define RED_SUBPIXEL(n) ((n & 0x1f) << 11) +#define GREEN_SUBPIXEL(n) ((n & 0x1f) << 5) +#define BLUE_SUBPIXEL(n) ((n & 0x1f) << 0) + +/* define a simple VGA style 16-color pallette */ +#if 0 +#define LU_BLACK (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)) +#define LU_BLUE (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f)) +#define LU_GREEN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00)) +#define LU_CYAN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f)) +#define LU_RED (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)) +#define LU_VIOLET (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f)) +#define LU_YELLOW (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00)) +#define LU_GREY (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f)) +#define LU_WHITE (RED_SUBPIXEL(0x17) | GREEN_SUBPIXEL(0x17) | BLUE_SUBPIXEL(0x17)) +#define LU_BRT_BLUE (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f)) +#define LU_BRT_GREEN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00)) +#define LU_BRT_CYAN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f)) +#define LU_BRT_RED (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)) +#define LU_BRT_VIOLET (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f)) +#define LU_BRT_YELLOW (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00)) +#define LU_BRT_WHITE (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f)) +/* RED, GREEN, BLUE Entry */ + { 0x00, 0x00, 0x00, }, /* LU_BLACK */ + { 0x00, 0x00, 0xA0, }, /* LU_BLUE */ + { 0x00, 0xA0, 0x00, }, /* LU_GREEN */ + { 0x00, 0xA0, 0xA0, }, /* LU_CYAN */ + { 0xA0, 0x00, 0x00, }, /* LU_RED */ + { 0xA0, 0x00, 0xA0, }, /* LU_VIOLET */ + { 0xA0, 0xA0, 0x00, }, /* LU_YELLOW */ + { 0xA0, 0xA0, 0xA0, }, /* LU_WHITE */ + { 0x50, 0x50, 0x50, }, /* LU_GREY */ + { 0x50, 0x50, 0xF0, }, /* LU_BRT_BLUE */ + { 0x50, 0xF0, 0x50, }, /* LU_BRT_GREEN */ + { 0x50, 0xF0, 0xF0, }, /* LU_BRT_CYAN */ + { 0xF0, 0x50, 0x50, }, /* LU_BRT_RED */ + { 0xF0, 0x50, 0xF0, }, /* LU_BRT_VIOLET */ + { 0xF0, 0xF0, 0x50, }, /* LU_BRT_YELLOW */ + { 0xF0, 0xF0, 0xF0, }, /* LU_BRT_WHITE */ +#endif + +#define BLUE (0x14 << 0) +#define GREEN (0x14 << 6) +#define RED (0x14 << 11) + +#define HALF_BLUE (0x0a << 0) +#define HALF_GREEN (0x0a << 6) +#define HALF_RED (0x0a << 11) + + +#define BRT_BLUE (0x1e << 0) +#define BRT_GREEN (0x1e << 6) +#define BRT_RED (0x1e << 11) + +#define LU_BLACK 0 +#define LU_BLUE (BLUE) +#define LU_GREEN (GREEN) +#define LU_CYAN (GREEN | BLUE) +#define LU_RED (RED) +#define LU_VIOLET (RED | BLUE) +#define LU_YELLOW (RED | GREEN) +#define LU_WHITE (RED | GREEN | BLUE) +#define LU_GREY (HALF_RED | HALF_GREEN | HALF_BLUE) +#define LU_BRT_BLUE (HALF_RED | HALF_GREEN | BRT_BLUE) +#define LU_BRT_GREEN (HALF_RED | BRT_GREEN | HALF_BLUE) +#define LU_BRT_CYAN (HALF_RED | BRT_GREEN | BRT_BLUE) +#define LU_BRT_RED (BRT_RED | HALF_GREEN | HALF_BLUE) +#define LU_BRT_VIOLET (BRT_RED | HALF_GREEN | BRT_BLUE) +#define LU_BRT_YELLOW (BRT_RED | BRT_GREEN | HALF_BLUE) +#define LU_BRT_WHITE (BRT_RED | BRT_GREEN | BRT_BLUE) + +const ushort vga_lookup[] = { +LU_BLACK, /* 0 */ +LU_BLUE, /* 1 */ +LU_GREEN, /* 2 */ +LU_CYAN, /* 3 */ +LU_RED, /* 4 */ +LU_VIOLET, /* 5 */ +LU_YELLOW, /* 6 */ +LU_WHITE, /* 7 */ +LU_GREY, /* 8 */ +LU_BRT_BLUE, /* 9 */ +LU_BRT_GREEN, /* 10 */ +LU_BRT_CYAN, /* 11 */ +LU_BRT_RED, /* 12 */ +LU_BRT_VIOLET, /* 13 */ +LU_BRT_YELLOW, /* 14 */ +LU_BRT_WHITE /* 15 */ +}; + +/* default foreground and background colors */ +#define SED_BG_DEF 1 +#define SED_FG_DEF 14 + +/* Draw defines */ +#define TOP 0 +#define BOTTOM (PIXELS_PER_COL-1) +#define LEFT 0 +#define RIGHT (PIXELS_PER_ROW-1) +#define CENTER_X (PIXELS_PER_ROW/2) +#define CENTER_Y (PIXELS_PER_COL/2) + + +/* Vertical and Horizontal Pulse, Start and Non-Display values vary depending + * upon the mode. The following section gives some insight into how the + * values are arrived at. + * ms = milliseconds, us = microseconds, ns = nanoseconds + * Mhz = Megaherz, Khz = Kiloherz, Hz = Herz + * + * *************************************************************************************************** + * CRT Mode is 640x480 @ 72Hz VESA compatible timing. PCLK = 31.5Mhz (31.75ns) + * *************************************************************************************************** + * + * CRT MODE HORIZONTAL TIMING PARAMETERS + * + * |<-------Tha------->| + * |___________________| ______ + * Display Enable _____________________| |____________________| + * | | + * Horizontal Pulse __ ________|___________________|________ __________ + * |_________| | | |________| + * |<- Thp ->| | | | + * | |<-Thbp->| | | + * | |<-Thfp->| + * |<----------------------Tht-------------------->| + * + * Tha - Active Display Time = 640 pixels + * Thp - Horizontal Pulse = 1.27us/31.75ns = 40 pixels + * Thbp - Horizontal Front Porch = 1.016us/31.75ns = 32 pixels + * Thfp - Horizontal Back Porch = 3.8us/31.75ns = 120 pixels + * Tht - Total Horizontal Time = 832 pixels x 32.75ns/pixel = 26.416us or 38.785Khz + * + * Correlation between horizontal timing parameters and SED registers + */ +#define SED_HOR_PULSE_WIDTH_CRT 0x07 /* Horizontal Pulse Width Register = (Thp/8) - 1 */ +#define SED_HOR_PULSE_START_CRT 0x02 /* Horizontal Pulse Start Position Register = ((Thfp + 2)/8) - 1 */ +#define SED_HOR_NONDISP_CRT 0x17 /* Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1 */ +/* + * CRT MODE VERTICAL TIMING PARAMTERS + * + * |<-------Tva------->| + * |___________________| ______ + * Display Enable _____________________| |_____________________| + * | | + * Vertical Pulse __ ________|___________________|________ __________ + * |_________| | | |________| + * |<- Tvp ->| | | | + * | |<-Tvbp->| | | + * | |<-Tvfp->| + * |<----------------------Tvt-------------------->| + * + * Tva - Active Display Time = 480 lines + * Tvp - Vertical Pulse = 3 lines + * Tvfp - Vertical Front Porch = 9 lines + * Tvbp - Vertical Back Porch = 28 lines + * Tvt - Total Horizontal Time = 520 lines x 26.416us/line = 13.73632ms or 72.8Hz + * + * Correlation between vertical timing parameters and SED registers + */ +#define SED_VER_PULSE_WIDTH_CRT 0x02 // VRTC/FPFRAME Pulse Width Register = Tvp - 1 +#define SED_VER_PULSE_START_CRT 0x08 // VRTC/FPFRAME Start Position Register = Tvfp - 1 +#define SED_VER_NONDISP_CRT 0x27 // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1 +/* + ***************************************************************************************************** + * DUAL LCD Mode is 640x480 @ 60Hz VGA compatible timing. PCLK = 25.175Mhz (39.722ns) + ***************************************************************************************************** + * + * LCD MODE HORIZONTAL TIMING PARAMTERS + * + * |<-------Tha------->| + * |___________________| ______ + * Display Enable _____________________| |____________________| + * | | + * Horizontal Pulse __ ________|___________________|________ __________ + * |_________| | | |________| + * |<- Thp ->| | | | + * | |<-Thbp->| | | + * | |<-Thfp->| + * |<----------------------Tht-------------------->| + * + * Tha - Active Display Time = 640 pixels + * Thp - Horizontal Pulse = 3.8us/39.72ns = 96 pixels + * Thfp - Horizontal Front Porch = .595us/39.72ns = 16 pixels + * Thbp - Horizontal Backporch = 1.9us/39.72ns = 48 pixels + * Tht - Total Horizontal Time = = 800 pixels @ 39.72ns/pixel = 31.776us or 31.47Khz + * + * Correlation between horizontal timing parameters and SED registers + *#define SED_HOR_PULSE_WIDTH_LCD 0x0b // HRTC/FPLINE Pulse Width Register = (Thp/8) - 1 + *#define SED_HOR_PULSE_START_LCD 0x02 // HRTC/FPLINE Start Position Register = (Thfp/8) - 2 + *#define SED_HOR_NONDISP_LCD 0x13 // Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1 + */ +extern long SED_HOR_PULSE_WIDTH_LCD; +extern long SED_HOR_PULSE_START_LCD; +extern long SED_HOR_NONDISP_LCD; + +/* + * + * LCD MODE VERTICAL TIMING PARAMTERS + * + * |<-------Tva------->| + * |___________________| ______ + * Display Enable _____________________| |_____________________| + * | | + * Vertical Pulse __ ________|___________________|________ __________ + * |_________| | | |________| + * |<- Tvp ->| | | | + * | |<-Tvbp->| | | + * | |<-Tvfp->| + * |<----------------------Tvt-------------------->| + * + * Tva - Active Display Time = 480 lines + * Tvp - Vertical Pulse = 2 lines + * Tvfp - Vertical Front Porch = 10 lines + * Tvbp - Vertical Backporch = 33 lines + * Tvt - Total Horizontal Time = 525 lines @ 31.776us/line = 16.682ms or 60Hz + * + * Correlation between vertical timing parameters and SED registers + *#define SED_VER_PULSE_WIDTH_LCD 0x01 // VRTC/FPFRAME Pulse Width Register = Tvp - 1 + *#define SED_VER_PULSE_START_LCD 0x09 // VRTC/FPFRAME Start Position Register = Tvfp - 1 + *#define SED_VER_NONDISP_LCD 0x2c // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1 + */ +extern long SED_VER_PULSE_WIDTH_LCD; +extern long SED_VER_PULSE_START_LCD; +extern long SED_VER_NONDISP_LCD; + +#endif diff --git a/bsps/arm/csb337/include/tm27.h b/bsps/arm/csb337/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/csb337/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/edb7312/headers.am b/bsps/arm/edb7312/headers.am new file mode 100644 index 0000000000..706c1e138e --- /dev/null +++ b/bsps/arm/edb7312/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/edb7312/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/edb7312/include/ep7312.h +include_HEADERS += ../../../../../../bsps/arm/edb7312/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/edb7312/include/bsp/irq.h diff --git a/bsps/arm/edb7312/include/bsp.h b/bsps/arm/edb7312/include/bsp.h new file mode 100644 index 0000000000..fa7a480970 --- /dev/null +++ b/bsps/arm/edb7312/include/bsp.h @@ -0,0 +1,72 @@ +/** + * @file + * @ingroup arm_edb7312 + * @brief Global BSP definitions. + */ + +/* + * Cirrus EP7312 BSP header file + * + * Copyright (c) 2002 by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ +#ifndef LIBBSP_ARM_EDB7312_BSP_H +#define LIBBSP_ARM_EDB7312_BSP_H + +#ifndef ASM + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION + +/** + * @defgroup arm_edb7312 EDB7312 Support + * @ingroup bsp_arm + * @brief EDB7312 Support Package + * @{ + */ + +/** + * @brief Define the interrupt mechanism for Time Test 27 + * + * NOTE: Following are not defined and are board independent + * + */ +struct rtems_bsdnet_ifconfig; +int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, + int attaching); + +/** + * @name Network driver configuration + * @{ + */ + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach + +/** @} */ + +/* + * Prototypes for methods called from .S but implemented in C + */ +void edb7312_interrupt_dispatch(rtems_vector_number vector); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif /* _BSP_H */ diff --git a/bsps/arm/edb7312/include/bsp/irq.h b/bsps/arm/edb7312/include/bsp/irq.h new file mode 100644 index 0000000000..04579a7c6f --- /dev/null +++ b/bsps/arm/edb7312/include/bsp/irq.h @@ -0,0 +1,92 @@ +/** + * @file + * @ingroup edb7312_interrupt + * @brief Interrupt definitions. + */ + +/* + * Cirrus EP7312 Intererrupt handler + * + * Copyright (c) 2010 embedded brains GmbH. + * + * Copyright (c) 2002 by Jay Monkman + * + * Copyright (c) 2002 by Charlie Steader + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ + +#ifndef __IRQ_H__ +#define __IRQ_H__ + +#ifndef __asm__ + +#include +#include +#include + +#endif /* __asm__ */ + +/** + * @defgroup edb7312_interrupt Interrupt Support + * @ingroup arm_edb7312 + * @brief Interrupt Support + * @{ + */ + +/** + * @name int interrupt status/mask register 1 + * @{ + */ + +#define BSP_EXTFIQ 0 +#define BSP_BLINT 1 +#define BSP_WEINT 2 +#define BSP_MCINT 3 +#define BSP_CSINT 4 +#define BSP_EINT1 5 +#define BSP_EINT2 6 +#define BSP_EINT3 7 +#define BSP_TC1OI 8 +#define BSP_TC2OI 9 +#define BSP_RTCMI 10 +#define BSP_TINT 11 +#define BSP_UTXINT1 12 +#define BSP_URXINT1 13 +#define BSP_UMSINT 14 +#define BSP_SSEOTI 15 + +/** @} */ + +/** + * @name int interrupt status/mask register 2 + * @{ + */ + +#define BSP_KBDINT 16 +#define BSP_SS2RX 17 +#define BSP_SS2TX 18 +#define BSP_UTXINT2 19 +#define BSP_URXINT2 20 + +/** @} */ + +/** + * @name int interrupt status/mask register 3 + * @{ + */ + +#define BSP_DAIINT 21 +#define BSP_MAX_INT 22 + +/** @} */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) + +/** @} */ + +#endif /* __IRQ_H__ */ diff --git a/bsps/arm/edb7312/include/ep7312.h b/bsps/arm/edb7312/include/ep7312.h new file mode 100644 index 0000000000..ba9d430bc6 --- /dev/null +++ b/bsps/arm/edb7312/include/ep7312.h @@ -0,0 +1,218 @@ +/** + * @file + * @ingroup edb7312_registers + * @brief Register declarations. + */ + +/* + * Cirrus EP7312 register declarations + * + * Copyright (c) 2002 by Charlie Steader + * + * Copyright (c) 2002 by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * + * Notes: The PLL registers (pll_ro and pll_wo) are either read only + * or write only. The data sheet says not to write the read + * only one or read the write only one. I'm not sure what will + * happen if you do. +*/ +#ifndef __EP7312_H__ +#define __EP7312_H__ + +#define EP7312_REG_BASE 0x80000000 + +/** + * @defgroup edb7312_registers Register Definitions + * @ingroup arm_edb7312 + * @brief Cirrus EP7312 Register Definitions + * @{ + */ + +#define EP7312_PADR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0000)) +#define EP7312_PBDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0001)) +#define EP7312_PDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0003)) +#define EP7312_PADDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0040)) +#define EP7312_PBDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0041)) +#define EP7312_PDDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0043)) +#define EP7312_PEDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0080)) +#define EP7312_PEDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x00C0)) +#define EP7312_SYSCON1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0100)) +#define EP7312_SYSFLG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0140)) +#define EP7312_MEMCFG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0180)) +#define EP7312_MEMCFG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x01C0)) +#define EP7312_INTSR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0240)) +#define EP7312_INTMR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0280)) +#define EP7312_LCDCON ((volatile uint32_t*)(EP7312_REG_BASE + 0x02C0)) +#define EP7312_TC1D ((volatile uint32_t*)(EP7312_REG_BASE + 0x0300)) +#define EP7312_TC2D ((volatile uint32_t*)(EP7312_REG_BASE + 0x0340)) +#define EP7312_RTCDR ((volatile uint32_t*)(EP7312_REG_BASE + 0x0380)) +#define EP7312_RTCMR ((volatile uint32_t*)(EP7312_REG_BASE + 0x03C0)) +#define EP7312_PMPCON ((volatile uint32_t*)(EP7312_REG_BASE + 0x0400)) +#define EP7312_CODR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0440)) +#define EP7312_UARTDR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0480)) +#define EP7312_UARTCR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x04C0)) +#define EP7312_SYNCIO ((volatile uint32_t*)(EP7312_REG_BASE + 0x0500)) +#define EP7312_PALLSW ((volatile uint32_t*)(EP7312_REG_BASE + 0x0540)) +#define EP7312_PALMSW ((volatile uint32_t*)(EP7312_REG_BASE + 0x0580)) +#define EP7312_STFCLR ((volatile uint32_t*)(EP7312_REG_BASE + 0x05C0)) +#define EP7312_BLEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0600)) +#define EP7312_MCEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0640)) +#define EP7312_TEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0680)) +#define EP7312_TC1EOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x06C0)) +#define EP7312_TC2EOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0700)) +#define EP7312_RTCEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0740)) +#define EP7312_UMSEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0780)) +#define EP7312_COEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x07C0)) +#define EP7312_HALT ((volatile uint32_t*)(EP7312_REG_BASE + 0x0800)) +#define EP7312_STDBY ((volatile uint32_t*)(EP7312_REG_BASE + 0x0840)) +#define EP7312_FBADDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x1000)) +#define EP7312_SYSCON2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1100)) +#define EP7312_SYSFLG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1140)) +#define EP7312_INTSR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1240)) +#define EP7312_INTMR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1280)) +#define EP7312_UARTDR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1480)) +#define EP7312_UARTCR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x14C0)) +#define EP7312_SS2DR ((volatile uint32_t*)(EP7312_REG_BASE + 0x1500)) +#define EP7312_SRXEOF ((volatile uint32_t*)(EP7312_REG_BASE + 0x1600)) +#define EP7312_SS2POP ((volatile uint32_t*)(EP7312_REG_BASE + 0x16C0)) +#define EP7312_KBDEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x1700)) +#define EP7312_DAIR ((volatile uint32_t*)(EP7312_REG_BASE + 0x2000)) +#define EP7312_DAIDR0 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2040)) +#define EP7312_DAIDR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2080)) +#define EP7312_DAIDR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x20C0)) +#define EP7312_DAISR ((volatile uint32_t*)(EP7312_REG_BASE + 0x2100)) +#define EP7312_SYSCON3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2200)) +#define EP7312_INTSR3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2240)) +#define EP7312_INTMR3 ((volatile uint8_t*)(EP7312_REG_BASE + 0x2280)) +#define EP7312_LEDFLSH ((volatile uint8_t*)(EP7312_REG_BASE + 0x22C0)) +#define EP7312_SDCONF ((volatile uint32_t*)(EP7312_REG_BASE + 0x2300)) +#define EP7312_SDRFPR ((volatile uint32_t*)(EP7312_REG_BASE + 0x2340)) +#define EP7312_UNIQID ((volatile uint32_t*)(EP7312_REG_BASE + 0x2440)) +#define EP7312_DAI64Fs ((volatile uint32_t*)(EP7312_REG_BASE + 0x2600)) +#define EP7312_PLLW ((volatile uint8_t*)(EP7312_REG_BASE + 0x2610)) +#define EP7312_PLLR ((volatile uint8_t*)(EP7312_REG_BASE + 0xA5A8)) +#define EP7312_RANDID0 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2700)) +#define EP7312_RANDID1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2704)) +#define EP7312_RANDID2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2708)) +#define EP7312_RANDID3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x270C)) + +/* serial port bits */ + +/** + * @name BITS in UBRLCR1 + * @{ + */ + +#define EP7312_UART_WRDLEN5 0x00000000 +#define EP7312_UART_WRDLEN6 0x00020000 +#define EP7312_UART_WRDLEN7 0x00040000 +#define EP7312_UART_WRDLEN8 0x00060000 +#define EP7312_UART_FIFOEN 0x00010000 +#define EP7312_UART_XSTOP 0x00008000 +#define EP7312_UART_EVENPRT 0x00004000 +#define EP7312_UART_PRTEN 0x00002000 +#define EP7312_UART_BREAK 0x00001000 + +/** @} */ + +/** + * @name BITS in INTSR1 + * @{ + */ + +#define EP7312_UART_UTXINT1 0x00002000 +#define EP7312_UART_URXINT1 0x00001000 + +/** @} */ + +/** + * @name BITS in UARTTDR1 + * @{ + */ + +#define EP7312_UART_FRMERR 0x00000100 +#define EP7312_UART_PARERR 0x00000200 +#define EP7312_UART_OVERR 0x00000400 + +/** @} */ + +/** + * @name BITS in system status flag register 1 + * @{ + */ + +#define EP7312_UART_UBUSY1 0x00000800 +#define EP7312_UART_URXFE1 0x00400000 +#define EP7312_UART_UTXFF1 0x00800000 + +/** @} */ + +/* system configuration bits */ + +/** + * @name BITS in SYSCON1 + * @{ + */ + +#define EP7312_SYSCON1_UART1EN 0x00000100 +#define EP7312_SYSCON1_TC1_PRESCALE 0x00000010 +#define EP7312_SYSCON1_TC1_512KHZ 0x00000020 +#define EP7312_SYSCON1_TC2_PRESCALE 0x00000040 +#define EP7312_SYSCON1_TC2_512KHZ 0x00000080 + +/** @} */ + +/** + * @name INTR1 (Interrupt 1) mask/status register bits + * @{ + */ + +#define EP7312_INTR1_EXTFIQ 0x00000001 +#define EP7312_INTR1_BLINT 0x00000002 +#define EP7312_INTR1_WEINT 0x00000004 +#define EP7312_INTR1_MCINT 0x00000008 +#define EP7312_INTR1_CSINT 0x00000010 +#define EP7312_INTR1_EINT1 0x00000020 +#define EP7312_INTR1_EINT2 0x00000040 +#define EP7312_INTR1_EINT3 0x00000080 +#define EP7312_INTR1_TC1OI 0x00000100 +#define EP7312_INTR1_TC2OI 0x00000200 +#define EP7312_INTR1_RTCMI 0x00000400 +#define EP7312_INTR1_TINT 0x00000800 +#define EP7312_INTR1_URXINT1 0x00001000 +#define EP7312_INTR1_UTXINT1 0x00002000 +#define EP7312_INTR1_UMSINT 0x00004000 +#define EP7312_INTR1_SSEOTI 0x00008000 + +/** @} */ + +/** + * @name INTR2 (Interrupt 2) mask/status register bits + * @{ + */ + +#define EP7312_INTR2_KBDINT 0x00000001 +#define EP7312_INTR2_SS2RX 0x00000002 +#define EP7312_INTR2_SS2TX 0x00000004 +#define EP7312_INTR2_URXINT2 0x00001000 +#define EP7312_INTR2_UTXINT2 0x00002000 + +/** @} */ + +/** + * @name INTR3 (Interrupt 3) mask/status register bits + * @{ + */ + +#define EP7312_INTR2_DAIINT 0x00000001 + +/** @} */ + +/** @} */ + +#endif /* __EP7312_H__ */ diff --git a/bsps/arm/edb7312/include/tm27.h b/bsps/arm/edb7312/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/edb7312/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/gdbarmsim/headers.am b/bsps/arm/gdbarmsim/headers.am new file mode 100644 index 0000000000..25e9fcafc7 --- /dev/null +++ b/bsps/arm/gdbarmsim/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/gdbarmsim/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/gdbarmsim/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/gdbarmsim/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/gdbarmsim/include/bsp/swi.h diff --git a/bsps/arm/gdbarmsim/include/bsp.h b/bsps/arm/gdbarmsim/include/bsp.h new file mode 100644 index 0000000000..798fa95cb4 --- /dev/null +++ b/bsps/arm/gdbarmsim/include/bsp.h @@ -0,0 +1,82 @@ +/** + * @file + * + * @ingroup arm_gdbarmsim + * + * @brief Global BSP definitions. + */ + +/* + * COPYRIGHT (c) 1989-2009. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_GDBARMSIM_BSP_H +#define LIBBSP_ARM_GDBARMSIM_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup arm_gdbarmsim GDBARMSIM Support + * + * @ingroup bsp_arm + * + * @brief GDBARMSIM support package. + * + * @{ + */ + +//#define BSP_GET_WORK_AREA_DEBUG 1 + +/** + * @brief Support for simulated clock tick + */ +void *clock_driver_sim_idle_body(uintptr_t); +#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body + +/* + * Access to the GDB simulator. + */ +int gdbarmsim_system(const char *); +int gdbarmsim_rename(const char *, const char *); +int gdbarmsim__isatty(int); +clock_t gdbarmsim_times(struct tms *); +int gdbarmsim_gettimeofday(struct timeval *, void *); +int gdbarmsim_unlink(const char *); +int gdbarmsim_link(void); +int gdbarmsim_stat(const char *, struct stat *); +int gdbarmsim_fstat(int, struct stat *); +int gdbarmsim_swistat(int fd, struct stat * st); +int gdbarmsim_close(int); +clock_t gdbarmsim_clock(void); +int gdbarmsim_swiclose(int); +int gdbarmsim_open(const char *, int, ...); +int gdbarmsim_swiopen(const char *, int); +int gdbarmsim_writec(const char c); +int gdbarmsim_write(int, char *, int); +int gdbarmsim_swiwrite(int, char *, int); +int gdbarmsim_lseek(int, int, int); +int gdbarmsim_swilseek(int, int, int); +int gdbarmsim_read(int, char *, int); +int gdbarmsim_swiread(int, char *, int); +void initialise_monitor_handles(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ + diff --git a/bsps/arm/gdbarmsim/include/bsp/irq.h b/bsps/arm/gdbarmsim/include/bsp/irq.h new file mode 100644 index 0000000000..3c86d22797 --- /dev/null +++ b/bsps/arm/gdbarmsim/include/bsp/irq.h @@ -0,0 +1,95 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief Dummy interrupt definitions. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_DUMMY_IRQ_H +#define LIBBSP_ARM_DUMMY_IRQ_H + +#ifndef ASM + +#include +#include +#include + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define DUMMY_IRQ_WDT 0 +#define DUMMY_IRQ_SOFTWARE 1 +#define DUMMY_IRQ_ARM_CORE_0 2 +#define DUMMY_IRQ_ARM_CORE_1 3 +#define DUMMY_IRQ_TIMER_0 4 +#define DUMMY_IRQ_TIMER_1 5 +#define DUMMY_IRQ_UART_0 6 +#define DUMMY_IRQ_UART_1 7 +#define DUMMY_IRQ_PWM 8 +#define DUMMY_IRQ_I2C_0 9 +#define DUMMY_IRQ_SPI_SSP_0 10 +#define DUMMY_IRQ_SSP_1 11 +#define DUMMY_IRQ_PLL 12 +#define DUMMY_IRQ_RTC 13 +#define DUMMY_IRQ_EINT_0 14 +#define DUMMY_IRQ_EINT_1 15 +#define DUMMY_IRQ_EINT_2 16 +#define DUMMY_IRQ_EINT_3 17 +#define DUMMY_IRQ_ADC_0 18 +#define DUMMY_IRQ_I2C_1 19 +#define DUMMY_IRQ_BOD 20 +#define DUMMY_IRQ_ETHERNET 21 +#define DUMMY_IRQ_USB 22 +#define DUMMY_IRQ_CAN 23 +#define DUMMY_IRQ_SD_MMC 24 +#define DUMMY_IRQ_DMA 25 +#define DUMMY_IRQ_TIMER_2 26 +#define DUMMY_IRQ_TIMER_3 27 +#define DUMMY_IRQ_UART_2 28 +#define DUMMY_IRQ_UART_3 29 +#define DUMMY_IRQ_I2C_2 30 +#define DUMMY_IRQ_I2S 31 + +#define DUMMY_IRQ_PRIORITY_VALUE_MIN 0U +#define DUMMY_IRQ_PRIORITY_VALUE_MAX 15U + +/** + * @brief Minimum vector number. + */ +#define BSP_INTERRUPT_VECTOR_MIN DUMMY_IRQ_WDT + +/** + * @brief Maximum vector number. + */ +#define BSP_INTERRUPT_VECTOR_MAX DUMMY_IRQ_I2S + +void bsp_interrupt_dispatch(void); + +#if 0 +void lpc24xx_irq_set_priority( rtems_vector_number vector, unsigned priority); + +unsigned lpc24xx_irq_priority( rtems_vector_number vector); +#endif + +/** @} */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_DUMMY_IRQ_H */ diff --git a/bsps/arm/gdbarmsim/include/bsp/swi.h b/bsps/arm/gdbarmsim/include/bsp/swi.h new file mode 100644 index 0000000000..e9eb434a58 --- /dev/null +++ b/bsps/arm/gdbarmsim/include/bsp/swi.h @@ -0,0 +1,110 @@ +/** + * @file + * + * @ingroup arm_gdbarmsim + * + * @brief Software interrupt definitions. + */ + +/** + * @defgroup gdbarmsim_swi SWI Definitions + * + * @ingroup arm_gdbarmsim + * + * @brief Software interrupt definitions. + */ + +/* + * Copied from libgloss 1 Oct 2009. + * Minor modifications to work with RTEMS. + */ + +/* SWI numbers for RDP (Demon) monitor. */ +#define SWI_WriteC 0x0 +#define SWI_Write0 0x2 +#define SWI_ReadC 0x4 +#define SWI_CLI 0x5 +#define SWI_GetEnv 0x10 +#define SWI_Exit 0x11 +#define SWI_EnterOS 0x16 + +#define SWI_GetErrno 0x60 +#define SWI_Clock 0x61 +#define SWI_Time 0x63 +#define SWI_Remove 0x64 +#define SWI_Rename 0x65 +#define SWI_Open 0x66 + +#define SWI_Close 0x68 +#define SWI_Write 0x69 +#define SWI_Read 0x6a +#define SWI_Seek 0x6b +#define SWI_Flen 0x6c + +#define SWI_IsTTY 0x6e +#define SWI_TmpNam 0x6f +#define SWI_InstallHandler 0x70 +#define SWI_GenerateError 0x71 + + +/* Now the SWI numbers and reason codes for RDI (Angel) monitors. */ +#define AngelSWI_ARM 0x123456 +#ifdef __thumb__ +#define AngelSWI 0xAB +#else +#define AngelSWI AngelSWI_ARM +#endif +/* For Thumb-2 code use the BKPT instruction instead of SWI. */ +#ifdef __thumb2__ +#define AngelSWIInsn "bkpt" +#define AngelSWIAsm bkpt +#else +#define AngelSWIInsn "swi" +#define AngelSWIAsm swi +#endif + +/* The reason codes: */ +#define AngelSWI_Reason_Open 0x01 +#define AngelSWI_Reason_Close 0x02 +#define AngelSWI_Reason_WriteC 0x03 +#define AngelSWI_Reason_Write0 0x04 +#define AngelSWI_Reason_Write 0x05 +#define AngelSWI_Reason_Read 0x06 +#define AngelSWI_Reason_ReadC 0x07 +#define AngelSWI_Reason_IsTTY 0x09 +#define AngelSWI_Reason_Seek 0x0A +#define AngelSWI_Reason_FLen 0x0C +#define AngelSWI_Reason_TmpNam 0x0D +#define AngelSWI_Reason_Remove 0x0E +#define AngelSWI_Reason_Rename 0x0F +#define AngelSWI_Reason_Clock 0x10 +#define AngelSWI_Reason_Time 0x11 +#define AngelSWI_Reason_System 0x12 +#define AngelSWI_Reason_Errno 0x13 +#define AngelSWI_Reason_GetCmdLine 0x15 +#define AngelSWI_Reason_HeapInfo 0x16 +#define AngelSWI_Reason_EnterSVC 0x17 +#define AngelSWI_Reason_ReportException 0x18 +#define ADP_Stopped_ApplicationExit ((2 << 16) + 38) +#define ADP_Stopped_RunTimeError ((2 << 16) + 35) + +#if defined(ARM_RDI_MONITOR) && !defined(__ASSEMBLER__) + +static inline int +do_AngelSWI (int reason, void * arg) +{ + int value; + __asm__ volatile ("mov r0, %1; mov r1, %2; " AngelSWIInsn " %a3; mov %0, r0" + : "=r" (value) /* Outputs */ + : "r" (reason), "r" (arg), "i" (AngelSWI) /* Inputs */ + : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" + /* Clobbers r0 and r1, and lr if in supervisor mode */); + /* Accordingly to page 13-77 of ARM DUI 0040D other registers + can also be clobbered. Some memory positions may also be + changed by a system call, so they should not be kept in + registers. Note: we are assuming the manual is right and + Angel is respecting the APCS. */ + return value; +} + +#endif diff --git a/bsps/arm/gdbarmsim/include/tm27.h b/bsps/arm/gdbarmsim/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/gdbarmsim/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/gumstix/headers.am b/bsps/arm/gumstix/headers.am new file mode 100644 index 0000000000..410ad6cf75 --- /dev/null +++ b/bsps/arm/gumstix/headers.am @@ -0,0 +1,12 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/gumstix/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/gumstix/include/ffuart.h +include_HEADERS += ../../../../../../bsps/arm/gumstix/include/pxa255.h +include_HEADERS += ../../../../../../bsps/arm/gumstix/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/gumstix/include/bsp/irq.h diff --git a/bsps/arm/gumstix/include/bsp.h b/bsps/arm/gumstix/include/bsp.h new file mode 100644 index 0000000000..caee8f9e19 --- /dev/null +++ b/bsps/arm/gumstix/include/bsp.h @@ -0,0 +1,84 @@ +/** + * @file + * @ingroup arm_gumstix + * @brief Global BSP definitions. + */ + +/* + * By Yang Xi . + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_GUMSTIX_BSP_H +#define LIBBSP_ARM_GUMSTIX_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup arm_gumstix Gumstix Support + * @ingroup bsp_arm + * @brief Gumstix support package + * @{ + */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_HAS_FRAME_BUFFER 1 + +/** @brief What is the input clock freq in hertz */ +#define BSP_MAIN_FREQ 3686400 /* 3.6864 MHz */ +#define BSP_SLCK_FREQ 32768 /* 32.768 KHz */ + +/** @brief What is the last interrupt */ +#define BSP_MAX_INT AT91RM9200_MAX_INT + +/* + * forward reference the type to avoid conflicts between libchip serial + * and libchip rtc get and set register types. + */ +typedef struct _console_tbl console_tbl; +console_tbl *BSP_get_uart_from_minor(int minor); + +static inline int32_t BSP_get_baud(void) {return 115200;} + +/** @brief How big should the interrupt stack be? */ +#define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024) + +#define ST_PIMR_PIV 33 /* 33 ticks of the 32.768Khz clock ~= 1msec */ + +#define outport_byte(port,val) *((unsigned char volatile*)(port)) = (val) +#define inport_byte(port,val) (val) = *((unsigned char volatile*)(port)) +#define outport_word(port,val) *((unsigned short volatile*)(port)) = (val) +#define inport_word(port,val) (val) = *((unsigned short volatile*)(port)) + +struct rtems_bsdnet_ifconfig; +extern int rtems_ne_driver_attach(struct rtems_bsdnet_ifconfig *, int); +#define BSP_NE2000_NETWORK_DRIVER_NAME "ne1" +#define BSP_NE2000_NETWORK_DRIVER_ATTACH rtems_ne_driver_attach + +#ifndef RTEMS_BSP_NETWORK_DRIVER_NAME +#define RTEMS_BSP_NETWORK_DRIVER_NAME BSP_NE2000_NETWORK_DRIVER_NAME +#endif + +#ifndef RTEMS_BSP_NETWORK_DRIVER_ATTACH +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_NE2000_NETWORK_DRIVER_ATTACH +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ + diff --git a/bsps/arm/gumstix/include/bsp/irq.h b/bsps/arm/gumstix/include/bsp/irq.h new file mode 100644 index 0000000000..a8b5d24da1 --- /dev/null +++ b/bsps/arm/gumstix/include/bsp/irq.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2010 embedded brains GmbH. + * + * Interrupt handler Header file for PXA By Yang Xi + * Copyright (c) 2004 by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __IRQ_H__ +#define __IRQ_H__ + +#ifndef __asm__ + +#include +#include +#include + +#include + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (PRIMARY_IRQS - 1) + +#endif /* __asm__ */ + +#endif /* __IRQ_H__ */ diff --git a/bsps/arm/gumstix/include/ffuart.h b/bsps/arm/gumstix/include/ffuart.h new file mode 100644 index 0000000000..68df822183 --- /dev/null +++ b/bsps/arm/gumstix/include/ffuart.h @@ -0,0 +1,48 @@ +/* + * FFUART for PXA250 CPU by Yang Xi + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __FFUART_H__ +#define __FFUART_H__ + +typedef struct { + /* + *Receive buffer(DLAB=0).Transmit buffer(DLAB=0). + *Divisor Latch Low(DLAB=1) + */ + volatile unsigned int rbr; + /*Interrupt enable(DLAB=0). Divisor Latch High(DLAB=1)*/ + volatile unsigned int ier; + /*Interrupt identification.FIFO control*/ + volatile unsigned int iir; + /*Line Control*/ + volatile unsigned int lcr; + /*Modem control*/ + volatile unsigned int mcr; + /*Line Status*/ + volatile unsigned int lsr; + /*Modem status*/ + volatile unsigned int msr; + /*Scratch Pad*/ + volatile unsigned int spr; + /*Infrared Selection*/ + volatile unsigned int isr; +} ffuart_reg_t; + + +#define EIGHT_BITS_NOPARITY_1STOPBIT 0x3 +#define DLAB 0x80 + + +/*Divisor = frequency_uart/(16 * BaudRate*)*/ +#define FREQUENCY_UART (14745600) + +#define SEND_EMPTY 0x20 +#define FULL_RECEIVE 0x01 + +#endif + diff --git a/bsps/arm/gumstix/include/pxa255.h b/bsps/arm/gumstix/include/pxa255.h new file mode 100644 index 0000000000..d5f2830c53 --- /dev/null +++ b/bsps/arm/gumstix/include/pxa255.h @@ -0,0 +1,128 @@ +/* + * By Yang Xi . + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __PXA_255_H__ +#define __PXA_255_H__ + +typedef unsigned int word_t; + +/*Interrupt*/ + +#define PRIMARY_IRQS 32 +#define GPIO_IRQS (85 - 2) /* The first two IRQs have level + one interrupts */ +#define GPIO_IRQ 10 + +#define IRQS (PRIMARY_IRQS + GPIO_IRQS) + +/* Interrupt Controller */ +#define INTERRUPT_OFFSET 0xd00000 +#define XSCALE_IRQ_OS_TIMER 26 +#define XSCALE_IRQ_PMU 12 +#define XSCALE_IRQ_STUART 20 +#define XSCALE_IRQ_NETWORK 16 + +#define PMU_IRQ 12 +#define CCNT_IRQ_ENABLE 1UL << 6 +#define PMN1_IRQ_ENABLE 1UL << 5 +#define PMN0_IRQ_ENABLE 1UL << 4 + +#define IODEVICE_VADDR 0x40000000 +#define XSCALE_INT (IODEVICE_VADDR + INTERRUPT_OFFSET) + +#define XSCALE_INT_ICMR (*(volatile word_t *)(XSCALE_INT + 0x04)) /* Mask register */ +#define XSCALE_INT_ICLR (*(volatile word_t *)(XSCALE_INT + 0x08)) /* FIQ / IRQ selection */ +#define XSCALE_INT_ICCR (*(volatile word_t *)(XSCALE_INT + 0x14)) /* Control register */ +#define XSCALE_INT_ICIP (*(volatile word_t *)(XSCALE_INT + 0x00)) /* IRQ pending */ +#define XSCALE_INT_ICFP (*(volatile word_t *)(XSCALE_INT + 0x0c)) /* FIQ pending */ +#define XSCALE_INT_ICPR (*(volatile word_t *)(XSCALE_INT + 0x10)) /* Pending (unmasked) */ + +/* GPIO */ +#define GPIO_OFFSET 0xe00000 +#define PXA_GPIO (IODEVICE_VADDR + GPIO_OFFSET) + +#define PXA_GEDR0 (*(volatile word_t *)(PXA_GPIO + 0x48)) /* GPIO edge detect 0 */ +#define PXA_GEDR1 (*(volatile word_t *)(PXA_GPIO + 0x4C)) /* GPIO edge detect 1 */ +#define PXA_GEDR2 (*(volatile word_t *)(PXA_GPIO + 0x50)) /* GPIO edge detect 2 */ + + +/* PXA2XX Timer */ + +#define TIMER_OFFSET 0x0a00000 +#define CLOCKS_OFFSET 0x1300000 +/*I change the TIMER_RATE to 36864,because when I use 3686400, the period will be calculate + to 30000*/ +#define TIMER_RATE 36864 + +#define XSCALE_TIMERS (IODEVICE_VADDR + TIMER_OFFSET) + +/* Match registers */ +#define XSCALE_OS_TIMER_MR0 (*(volatile word_t *)(XSCALE_TIMERS + 0x00)) +#define XSCALE_OS_TIMER_MR1 (*(volatile word_t *)(XSCALE_TIMERS + 0x04)) +#define XSCALE_OS_TIMER_MR2 (*(volatile word_t *)(XSCALE_TIMERS + 0x08)) +#define XSCALE_OS_TIMER_MR3 (*(volatile word_t *)(XSCALE_TIMERS + 0x0c)) + +/* Interrupt enable register */ +#define XSCALE_OS_TIMER_IER (*(volatile word_t *)(XSCALE_TIMERS + 0x1c)) +/* Watchdog match enable register */ +#define XSCALE_OS_TIMER_WMER (*(volatile word_t *)(XSCALE_TIMERS + 0x18)) +/* Timer count register */ +#define XSCALE_OS_TIMER_TCR (*(volatile word_t *)(XSCALE_TIMERS + 0x10)) +/* Timer status register */ +#define XSCALE_OS_TIMER_TSR (*(volatile word_t *)(XSCALE_TIMERS + 0x14)) + +#define XSCALE_CLOCKS (IODEVICE_VADDR + CLOCKS_VOFFSET) + +#define XSCALE_CLOCKS_CCCR (*(volatile word_t *)(XSCALE_CLOCKS + 0x00)) + +/*Use ffuart port as the console*/ +#define FFUART_BASE 0x40100000 + +/*Write to SKYEYE_MAGIC_ADDRESS to make SKYEYE exit*/ + +#define SKYEYE_MAGIC_ADDRESS (*(volatile word_t *)(0xb0000000)) +#define SKYEYE_MAGIC_NUMBER (0xf0f0f0f0) + +/*PMC*/ +#define PMC_PMNC 0 +#define PMC_CCNT 1 +#define PMC_INTEN 2 +#define PMC_FLAG 3 +#define PMC_EVTSEL 4 +#define PMC_PMN0 5 +#define PMC_PMN1 6 +#define PMC_PMN2 7 +#define PMC_PMN3 8 + +#define PMC_PMNC_E (0x01) +#define PMC_PMNC_PCR (0x01 << 1) +#define PMC_PMNC_CCR (0x01 << 2) +#define PMC_PMNC_CCD (0x01 << 3) +#define PMC_PMNC_PCD (0x01 << 4) + +/*LCD*/ +#define LCCR0 (*(volatile word_t *)(0x44000000)) +#define LCCR1 (*(volatile word_t *)(0x44000004)) +#define LCCR2 (*(volatile word_t *)(0x44000008)) +#define LCCR3 (*(volatile word_t *)(0x4400000C)) + +#define FDADR0 (*(volatile word_t *)(0x44000200)) +#define FSADR0 (*(volatile word_t *)(0x44000204)) +#define FIDR0 (*(volatile word_t *)(0x44000208)) +#define LDCMD0 (*(volatile word_t *)(0x4400020C)) + +#define FDADR1 (*(volatile word_t *)(0x44000210)) +#define FSADR1 (*(volatile word_t *)(0x44000214)) +#define FIDR1 (*(volatile word_t *)(0x44000218)) +#define LDCMD1 (*(volatile word_t *)(0x4400021C)) + +#define LCCR0_ENB 0x00000001 +#define LCCR1_PPL 0x000003FF +#define LCCR2_LPP 0x000003FF +#define LCCR3_BPP 0x07000000 +#endif diff --git a/bsps/arm/gumstix/include/tm27.h b/bsps/arm/gumstix/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/gumstix/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am new file mode 100644 index 0000000000..764a085442 --- /dev/null +++ b/bsps/arm/headers.am @@ -0,0 +1,45 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../bsps/arm/include/cmsis_gcc.h +include_HEADERS += ../../../../../bsps/arm/include/core_cm7.h +include_HEADERS += ../../../../../bsps/arm/include/core_cmFunc.h +include_HEADERS += ../../../../../bsps/arm/include/core_cmInstr.h +include_HEADERS += ../../../../../bsps/arm/include/core_cmSimd.h +include_HEADERS += ../../../../../bsps/arm/include/uart.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a8core-start.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-clock.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-irq.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-regs.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-start.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-cp15-start.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-errata.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-irq.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011-regs.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-regs.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-release-id.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/armv7m-irq.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/linker-symbols.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-dma.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-emc.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-i2s.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-lcd.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-timer.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/start.h + +include_libcpudir = $(includedir)/libcpu +include_libcpu_HEADERS = +include_libcpu_HEADERS += ../../../../../bsps/arm/include/libcpu/am335x.h +include_libcpu_HEADERS += ../../../../../bsps/arm/include/libcpu/mmu.h +include_libcpu_HEADERS += ../../../../../bsps/arm/include/libcpu/omap3.h +include_libcpu_HEADERS += ../../../../../bsps/arm/include/libcpu/omap_timer.h diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am new file mode 100644 index 0000000000..dd18164254 --- /dev/null +++ b/bsps/arm/imx/headers.am @@ -0,0 +1,22 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/imx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/imx/include/tm27.h + +include_arm_freescale_imxdir = $(includedir)/arm/freescale/imx +include_arm_freescale_imx_HEADERS = +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h b/bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h new file mode 100644 index 0000000000..5633de6f50 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h @@ -0,0 +1,64 @@ +/*- + * Copyright (c) 2014 Ian Lepore + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/freescale/imx/imx_ccmvar.h 292565 2015-12-21 20:17:24Z gonzo $ + */ + +#ifndef IMX_CCMVAR_H +#define IMX_CCMVAR_H + +/* + * We need a clock management system that works across unrelated SoCs and + * devices. For now, to keep imx development moving, define some barebones + * functionality that can be shared within the imx family by having each SoC + * implement functions with a common name. + * + * The usb enable functions are best-effort. They turn on the usb otg, host, + * and phy clocks in a SoC-specific manner, but it may take a lot more than that + * to make usb work on a given board. In particular, it can require specific + * pinmux setup of gpio pins connected to external phy parts, voltage regulators + * and overcurrent detectors, and so on. On such boards, u-boot or other early + * board setup code has to handle those things. + */ + +uint32_t imx_ccm_ipg_hz(void); +uint32_t imx_ccm_perclk_hz(void); +uint32_t imx_ccm_sdhci_hz(void); +uint32_t imx_ccm_uart_hz(void); +uint32_t imx_ccm_ahb_hz(void); + +#ifndef __rtems__ +void imx_ccm_usb_enable(device_t _usbdev); +void imx_ccm_usbphy_enable(device_t _phydev); +void imx_ccm_ssi_configure(device_t _ssidev); +void imx_ccm_hdmi_enable(void); +void imx_ccm_ipu_enable(int ipu); + +/* Routines to get and set the arm clock root divisor register. */ +uint32_t imx_ccm_get_cacrr(void); +void imx_ccm_set_cacrr(uint32_t _divisor); +#endif /* __rtems__ */ + +#endif diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h new file mode 100644 index 0000000000..299ed2bd7a --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_ECSPIREG_H +#define IMX_ECSPIREG_H + +#include + +typedef struct { + uint32_t rxdata; + uint32_t txdata; + uint32_t conreg; +#define IMX_ECSPI_CONREG_BURST_LENGTH(val) BSP_FLD32(val, 20, 31) +#define IMX_ECSPI_CONREG_BURST_LENGTH_GET(reg) BSP_FLD32GET(reg, 20, 31) +#define IMX_ECSPI_CONREG_BURST_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 20, 31) +#define IMX_ECSPI_CONREG_CHANNEL_SELECT(val) BSP_FLD32(val, 18, 19) +#define IMX_ECSPI_CONREG_CHANNEL_SELECT_GET(reg) BSP_FLD32GET(reg, 18, 19) +#define IMX_ECSPI_CONREG_CHANNEL_SELECT_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) +#define IMX_ECSPI_CONREG_DRCTL(val) BSP_FLD32(val, 16, 17) +#define IMX_ECSPI_CONREG_DRCTL_GET(reg) BSP_FLD32GET(reg, 16, 17) +#define IMX_ECSPI_CONREG_DRCTL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) +#define IMX_ECSPI_CONREG_PRE_DIVIDER(val) BSP_FLD32(val, 12, 15) +#define IMX_ECSPI_CONREG_PRE_DIVIDER_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define IMX_ECSPI_CONREG_PRE_DIVIDER_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define IMX_ECSPI_CONREG_POST_DIVIDER(val) BSP_FLD32(val, 8, 11) +#define IMX_ECSPI_CONREG_POST_DIVIDER_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define IMX_ECSPI_CONREG_POST_DIVIDER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define IMX_ECSPI_CONREG_CHANNEL_MODE(val) BSP_FLD32(val, 4, 7) +#define IMX_ECSPI_CONREG_CHANNEL_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_ECSPI_CONREG_CHANNEL_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define IMX_ECSPI_CONREG_SMC BSP_BIT32(3) +#define IMX_ECSPI_CONREG_XCH BSP_BIT32(2) +#define IMX_ECSPI_CONREG_HT BSP_BIT32(1) +#define IMX_ECSPI_CONREG_EN BSP_BIT32(0) + uint32_t configreg; +#define IMX_ECSPI_CONFIGREG_HT_LENGTH(val) BSP_FLD32(val, 24, 28) +#define IMX_ECSPI_CONFIGREG_HT_LENGTH_GET(reg) BSP_FLD32GET(reg, 24, 28) +#define IMX_ECSPI_CONFIGREG_HT_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 24, 28) +#define IMX_ECSPI_CONFIGREG_SCLK_CTL(val) BSP_FLD32(val, 20, 23) +#define IMX_ECSPI_CONFIGREG_SCLK_CTL_GET(reg) BSP_FLD32GET(reg, 20, 23) +#define IMX_ECSPI_CONFIGREG_SCLK_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23) +#define IMX_ECSPI_CONFIGREG_DATA_CTL(val) BSP_FLD32(val, 16, 19) +#define IMX_ECSPI_CONFIGREG_DATA_CTL_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define IMX_ECSPI_CONFIGREG_DATA_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define IMX_ECSPI_CONFIGREG_SS_POL(val) BSP_FLD32(val, 12, 15) +#define IMX_ECSPI_CONFIGREG_SS_POL_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define IMX_ECSPI_CONFIGREG_SS_POL_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define IMX_ECSPI_CONFIGREG_SS_CTL(val) BSP_FLD32(val, 8, 11) +#define IMX_ECSPI_CONFIGREG_SS_CTL_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define IMX_ECSPI_CONFIGREG_SS_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define IMX_ECSPI_CONFIGREG_SCLK_POL(val) BSP_FLD32(val, 4, 7) +#define IMX_ECSPI_CONFIGREG_SCLK_POL_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_ECSPI_CONFIGREG_SCLK_POL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define IMX_ECSPI_CONFIGREG_SCLK_PHA(val) BSP_FLD32(val, 0, 3) +#define IMX_ECSPI_CONFIGREG_SCLK_PHA_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define IMX_ECSPI_CONFIGREG_SCLK_PHA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define IMX_ECSPI_TC BSP_BIT32(7) +#define IMX_ECSPI_RO BSP_BIT32(6) +#define IMX_ECSPI_RF BSP_BIT32(5) +#define IMX_ECSPI_RDR BSP_BIT32(4) +#define IMX_ECSPI_RR BSP_BIT32(3) +#define IMX_ECSPI_TF BSP_BIT32(2) +#define IMX_ECSPI_TDR BSP_BIT32(1) +#define IMX_ECSPI_TE BSP_BIT32(0) + uint32_t intreg; + uint32_t dmareg; +#define IMX_ECSPI_DMAREG_RXTDEN BSP_BIT32(31) +#define IMX_ECSPI_DMAREG_RX_DMA_LENGTH(val) BSP_FLD32(val, 24, 29) +#define IMX_ECSPI_DMAREG_RX_DMA_LENGTH_GET(reg) BSP_FLD32GET(reg, 24, 29) +#define IMX_ECSPI_DMAREG_RX_DMA_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 24, 29) +#define IMX_ECSPI_DMAREG_RXDEN BSP_BIT32(23) +#define IMX_ECSPI_DMAREG_RX_THRESHOLD(val) BSP_FLD32(val, 16, 21) +#define IMX_ECSPI_DMAREG_RX_THRESHOLD_GET(reg) BSP_FLD32GET(reg, 16, 21) +#define IMX_ECSPI_DMAREG_RX_THRESHOLD_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) +#define IMX_ECSPI_DMAREG_TEDEN BSP_BIT32(7) +#define IMX_ECSPI_DMAREG_TX_THRESHOLD(val) BSP_FLD32(val, 0, 5) +#define IMX_ECSPI_DMAREG_TX_THRESHOLD_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define IMX_ECSPI_DMAREG_TX_THRESHOLD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t statreg; + uint32_t periodreg; +#define IMX_ECSPI_PERIODREG_CSD_CTL(val) BSP_FLD32(val, 16, 21) +#define IMX_ECSPI_PERIODREG_CSD_CTL_GET(reg) BSP_FLD32GET(reg, 16, 21) +#define IMX_ECSPI_PERIODREG_CSD_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) +#define IMX_ECSPI_PERIODREG_CSRC BSP_BIT32(15) +#define IMX_ECSPI_PERIODREG_SAMPLE_PERIOD(val) BSP_FLD32(val, 0, 14) +#define IMX_ECSPI_PERIODREG_SAMPLE_PERIOD_GET(reg) BSP_FLD32GET(reg, 0, 14) +#define IMX_ECSPI_PERIODREG_SAMPLE_PERIOD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 14) + uint32_t testreg; +#define IMX_ECSPI_TESTREG_LBC BSP_BIT32(31) +#define IMX_ECSPI_TESTREG_RXCNT(val) BSP_FLD32(val, 8, 14) +#define IMX_ECSPI_TESTREG_RXCNT_GET(reg) BSP_FLD32GET(reg, 8, 14) +#define IMX_ECSPI_TESTREG_RXCNT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 14) +#define IMX_ECSPI_TESTREG_TXCNT(val) BSP_FLD32(val, 0, 6) +#define IMX_ECSPI_TESTREG_TXCNT_GET(reg) BSP_FLD32GET(reg, 0, 6) +#define IMX_ECSPI_TESTREG_TXCNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) + uint32_t reserved_24[7]; + uint32_t msgdata; +} imx_ecspi; + +#endif /* IMX_ECSPIREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h new file mode 100644 index 0000000000..924166c70d --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_GPCREG_H +#define IMX_GPCREG_H + +#include + +typedef struct { + uint32_t lpcr_a7_bsc; + uint32_t lpcr_a7_ad; + uint32_t lpcr_m4; + uint32_t reserved_0c[2]; + uint32_t slpcr; + uint32_t reserved_18[2]; + uint32_t mlpcr; + uint32_t pgc_ack_sel_a7; + uint32_t pgc_ack_sel_m4; + uint32_t misc; + uint32_t imr1_core0_a7; + uint32_t imr2_core0_a7; + uint32_t imr3_core0_a7; + uint32_t imr4_core0_a7; + uint32_t imr1_core1_a7; + uint32_t imr2_core1_a7; + uint32_t imr3_core1_a7; + uint32_t imr4_core1_a7; + uint32_t imr1_m4; + uint32_t imr2_m4; + uint32_t imr3_m4; + uint32_t imr4_m4; + uint32_t reserved_60[4]; + uint32_t isr1_a7; + uint32_t isr2_a7; + uint32_t isr3_a7; + uint32_t isr4_a7; + uint32_t isr1_m4; + uint32_t isr2_m4; + uint32_t isr3_m4; + uint32_t isr4_m4; + uint32_t reserved_90[8]; + uint32_t slt0_cfg; + uint32_t slt1_cfg; + uint32_t slt2_cfg; + uint32_t slt3_cfg; + uint32_t slt4_cfg; + uint32_t slt5_cfg; + uint32_t slt6_cfg; + uint32_t slt7_cfg; + uint32_t slt8_cfg; + uint32_t slt9_cfg; + uint32_t reserved_d8[5]; + uint32_t pgc_cpu_mapping; +#define IMX_GPC_CPU_PGC_SCU_A7 BSP_BIT32(2) +#define IMX_GPC_CPU_PGC_CORE1_A7 BSP_BIT32(1) +#define IMX_GPC_CPU_PGC_CORE0_A7 BSP_BIT32(0) +#define IMX_GPC_PU_PGC_USB_HSIC_PHY BSP_BIT32(4) +#define IMX_GPC_PU_PGC_USB_OTG2_PHY BSP_BIT32(3) +#define IMX_GPC_PU_PGC_USB_OTG1_PHY BSP_BIT32(2) +#define IMX_GPC_PU_PGC_PCIE_PHY BSP_BIT32(1) +#define IMX_GPC_PU_PGC_MIPI_PHY BSP_BIT32(0) + uint32_t cpu_pgc_sw_pup_req; + uint32_t reserved_f4; + uint32_t pu_pgc_sw_pup_req; + uint32_t cpu_pgc_sw_pdn_req; + uint32_t reserved_100; + uint32_t pu_pgc_sw_pdn_req; + uint32_t reserved_108[10]; + uint32_t cpu_pgc_pup_status1; + uint32_t a7_mix_pgc_pup_status0; + uint32_t a7_mix_pgc_pup_status1; + uint32_t a7_mix_pgc_pup_status2; + uint32_t m4_mix_pgc_pup_status0; + uint32_t m4_mix_pgc_pup_status1; + uint32_t m4_mix_pgc_pup_status2; + uint32_t a7_pu_pgc_pup_status0; + uint32_t a7_pu_pgc_pup_status1; + uint32_t a7_pu_pgc_pup_status2; + uint32_t m4_pu_pgc_pup_status0; + uint32_t m4_pu_pgc_pup_status1; + uint32_t m4_pu_pgc_pup_status2; + uint32_t reserved_164[3]; + uint32_t cpu_pgc_pdn_status1; + uint32_t reserved_174[6]; + uint32_t a7_pu_pgc_pdn_status0; + uint32_t a7_pu_pgc_pdn_status1; + uint32_t a7_pu_pgc_pdn_status2; + uint32_t m4_pu_pgc_pdn_status0; + uint32_t m4_pu_pgc_pdn_status1; + uint32_t m4_pu_pgc_pdn_status2; + uint32_t reserved_1a4[3]; + uint32_t a7_mix_pdn_flg; + uint32_t a7_pu_pdn_flg; + uint32_t m4_mix_pdn_flg; + uint32_t m4_pu_pdn_flg; +#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM(val) BSP_FLD32(val, 24, 29) +#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_GET(reg) BSP_FLD32GET(reg, 24, 29) +#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SET(reg, val) BSP_FLD32SET(reg, val, 24, 29) +#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR(val) BSP_FLD32(val, 16, 21) +#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_GET(reg) BSP_FLD32GET(reg, 16, 21) +#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) +#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1(val) BSP_FLD32(val, 8, 13) +#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_GET(reg) BSP_FLD32GET(reg, 8, 13) +#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) +#define IMX_GPC_PGC_CTRL_L2RSTDIS(val) BSP_FLD32(val, 1, 6) +#define IMX_GPC_PGC_CTRL_L2RSTDIS_GET(reg) BSP_FLD32GET(reg, 1, 6) +#define IMX_GPC_PGC_CTRL_L2RSTDIS_SET(reg, val) BSP_FLD32SET(reg, val, 1, 6) +#define IMX_GPC_PGC_CTRL_PCR BSP_BIT32(0) + uint32_t reserved_1c0[400]; + uint32_t pgc_a7core0_ctrl; + uint32_t pgc_a7core0_pupscr; + uint32_t pgc_a7core0_pdnscr; + uint32_t pgc_a7core0_sr; + uint32_t reserved_810[12]; + uint32_t pgc_a7core1_ctrl; + uint32_t pgc_a7core1_pupscr; + uint32_t pgc_a7core1_pdnscr; + uint32_t pgc_a7core1_sr; + uint32_t reserved_850[12]; + uint32_t pgc_a7scu_ctrl; + uint32_t pgc_a7scu_pupscr; + uint32_t pgc_a7scu_pdnscr; + uint32_t pgc_a7scu_sr; + uint32_t pgc_scu_auxsw; + uint32_t reserved_894[11]; + uint32_t pgc_mix_ctrl; + uint32_t pgc_mix_pupscr; + uint32_t pgc_mix_pdnscr; + uint32_t pgc_mix_sr; + uint32_t reserved_8d0[12]; + uint32_t pgc_mipi_ctrl; + uint32_t pgc_mipi_pupscr; + uint32_t pgc_mipi_pdnscr; + uint32_t pgc_mipi_sr; + uint32_t reserved_910[12]; + uint32_t pgc_pcie_ctrl; + uint32_t pgc_pcie_pupscr; + uint32_t pgc_pcie_pdnscr; + uint32_t pgc_pcie_sr; + uint32_t reserved_950[176]; + uint32_t pgc_mipi_auxsw; + uint32_t reserved_c14[15]; + uint32_t pgc_pcie_auxsw; + uint32_t reserved_c54[43]; + uint32_t pgc_hsic_ctrl; + uint32_t pgc_hsic_pupscr; + uint32_t pgc_hsic_pdnscr; + uint32_t pgc_hsic_sr; +} imx_gpc; + +#endif /* IMX_GPCREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h new file mode 100644 index 0000000000..0f1b7f13c5 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_I2CREG_H +#define IMX_I2CREG_H + +#include + +typedef struct { + uint16_t iadr; +#define IMX_I2C_IADR_ADR(val) BSP_FLD16(val, 1, 7) +#define IMX_I2C_IADR_ADR_GET(reg) BSP_FLD16GET(reg, 1, 7) +#define IMX_I2C_IADR_ADR_SET(reg, val) BSP_FLD16SET(reg, val, 1, 7) + uint16_t reserved_02; + uint16_t ifdr; +#define IMX_I2C_IFDR_IC(val) BSP_FLD16(val, 0, 5) +#define IMX_I2C_IFDR_IC_GET(reg) BSP_FLD16GET(reg, 0, 5) +#define IMX_I2C_IFDR_IC_SET(reg, val) BSP_FLD16SET(reg, val, 0, 5) + uint16_t reserved_06; + uint16_t i2cr; +#define IMX_I2C_I2CR_IEN BSP_BIT16(7) +#define IMX_I2C_I2CR_IIEN BSP_BIT16(6) +#define IMX_I2C_I2CR_MSTA BSP_BIT16(5) +#define IMX_I2C_I2CR_MTX BSP_BIT16(4) +#define IMX_I2C_I2CR_TXAK BSP_BIT16(3) +#define IMX_I2C_I2CR_RSTA BSP_BIT16(2) + uint16_t reserved_0a; + uint16_t i2sr; +#define IMX_I2C_I2SR_ICF BSP_BIT16(7) +#define IMX_I2C_I2SR_IAAS BSP_BIT16(6) +#define IMX_I2C_I2SR_IBB BSP_BIT16(5) +#define IMX_I2C_I2SR_IAL BSP_BIT16(4) +#define IMX_I2C_I2SR_SRW BSP_BIT16(2) +#define IMX_I2C_I2SR_IIF BSP_BIT16(1) +#define IMX_I2C_I2SR_RXAK BSP_BIT16(0) + uint16_t reserved_0e; + uint16_t i2dr; +#define IMX_I2C_I2DR_DATA(val) BSP_FLD16(val, 0, 7) +#define IMX_I2C_I2DR_DATA_GET(reg) BSP_FLD16GET(reg, 0, 7) +#define IMX_I2C_I2DR_DATA_SET(reg, val) BSP_FLD16SET(reg, val, 0, 7) +} imx_i2c; + +#endif /* IMX_I2CREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h new file mode 100644 index 0000000000..b84fde26de --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h @@ -0,0 +1,61 @@ +/*- + * Copyright (c) 2015 Oleksandr Tymoshenko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/freescale/imx/imx_iomuxreg.h 322015 2017-08-03 14:43:41Z ian $ + */ + +#ifndef IMX_IOMUXREG_H +#define IMX_IOMUXREG_H + +#define IMX_IOMUXREG_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) +#define IMX_IOMUXREG_SHIFTIN(__x, __mask) ((__x) * IMX_IOMUXREG_LOWEST_SET_BIT(__mask)) + +#define IMX_IOMUXREG_BIT(n) (1 << (n)) +#define IMX_IOMUXREG_BITS(__m, __n) \ + ((IMX_IOMUXREG_BIT(MAX((__m), (__n)) + 1) - 1) ^ (IMX_IOMUXREG_BIT(MIN((__m), (__n))) - 1)) + +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0C +#define IOMUXC_GPR3_HDMI_MASK (3 << 2) +#define IOMUXC_GPR3_HDMI_IPU1_DI0 (0 << 2) +#define IOMUXC_GPR3_HDMI_IPU1_DI1 (1 << 2) +#define IOMUXC_GPR3_HDMI_IPU2_DI0 (2 << 2) +#define IOMUXC_GPR3_HDMI_IPU2_DI1 (3 << 2) + +#define IOMUX_GPR13 0x34 +#define IOMUX_GPR13_SATA_PHY_8(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(26, 24)) +#define IOMUX_GPR13_SATA_PHY_7(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(23, 19)) +#define IOMUX_GPR13_SATA_PHY_6(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(18, 16)) +#define IOMUX_GPR13_SATA_SPEED(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 15)) +#define IOMUX_GPR13_SATA_PHY_5(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 14)) +#define IOMUX_GPR13_SATA_PHY_4(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(13, 11)) +#define IOMUX_GPR13_SATA_PHY_3(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(10, 7)) +#define IOMUX_GPR13_SATA_PHY_2(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(6, 2)) +#define IOMUX_GPR13_SATA_PHY_1(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 1)) +#define IOMUX_GPR13_SATA_PHY_0(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 0)) + +#endif diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h b/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h new file mode 100644 index 0000000000..8050b56a84 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h @@ -0,0 +1,49 @@ +/*- + * Copyright (c) 2014 Ian Lepore + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/freescale/imx/imx_iomuxvar.h 321938 2017-08-02 18:28:06Z ian $ + */ + +#ifndef IMX_IOMUXVAR_H +#define IMX_IOMUXVAR_H + +/* + * IOMUX interface functions + */ +void iomux_set_function(u_int pin, u_int fn); +void iomux_set_pad(u_int pin, u_int cfg); +u_int iomux_get_pad_config(u_int pin); + +/* + * The IOMUX Controller device has a small set of "general purpose registers" + * which control various aspects of SoC operation that really have nothing to do + * with IO pin assignments or pad control. These functions let other soc level + * code manipulate these values. + */ +uint32_t imx_iomux_gpr_get(u_int regaddr); +void imx_iomux_gpr_set(u_int regaddr, uint32_t val); +void imx_iomux_gpr_set_masked(u_int regaddr, uint32_t clrbits, uint32_t setbits); + +#endif diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h new file mode 100644 index 0000000000..b5f3490b79 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_SRCREG_H +#define IMX_SRCREG_H + +#include + +typedef struct { + uint32_t scr; +#define IMX_SRC_SCR_DOM_EN BSP_BIT32(31) +#define IMX_SRC_SCR_LOCK BSP_BIT32(30) +#define IMX_SRC_SCR_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_SCR_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_SCR_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_SCR_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET(val) BSP_FLD32(val, 4, 7) +#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) + uint32_t a7rcr0; +#define IMX_SRC_A7RCR0_DOM_EN BSP_BIT32(31) +#define IMX_SRC_A7RCR0_LOCK BSP_BIT32(30) +#define IMX_SRC_A7RCR0_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_A7RCR0_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_A7RCR0_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_A7RCR0_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_A7RCR0_A7_L2RESET BSP_BIT32(21) +#define IMX_SRC_A7RCR0_A7_SOC_DBG_RESET BSP_BIT32(20) +#define IMX_SRC_A7RCR0_MASK_WDOG1_RST(val) BSP_FLD32(val, 16, 19) +#define IMX_SRC_A7RCR0_MASK_WDOG1_RST_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define IMX_SRC_A7RCR0_MASK_WDOG1_RST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define IMX_SRC_A7RCR0_A7_ETM_RESET1 BSP_BIT32(13) +#define IMX_SRC_A7RCR0_A7_ETM_RESET0 BSP_BIT32(12) +#define IMX_SRC_A7RCR0_A7_DBG_RESET1 BSP_BIT32(9) +#define IMX_SRC_A7RCR0_A7_DBG_RESET0 BSP_BIT32(8) +#define IMX_SRC_A7RCR0_A7_CORE_RESET1 BSP_BIT32(5) +#define IMX_SRC_A7RCR0_A7_CORE_RESET0 BSP_BIT32(4) +#define IMX_SRC_A7RCR0_A7_CORE_POR_RESET1 BSP_BIT32(1) +#define IMX_SRC_A7RCR0_A7_CORE_POR_RESET0 BSP_BIT32(0) + uint32_t a7rcr1; +#define IMX_SRC_A7RCR1_DOM_EN BSP_BIT32(31) +#define IMX_SRC_A7RCR1_LOCK BSP_BIT32(30) +#define IMX_SRC_A7RCR1_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_A7RCR1_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_A7RCR1_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_A7RCR1_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_A7RCR1_A7_CORE1_ENABLE BSP_BIT32(1) + uint32_t m4rcr; +#define IMX_SRC_M4RCR_DOM_EN BSP_BIT32(31) +#define IMX_SRC_M4RCR_LOCK BSP_BIT32(30) +#define IMX_SRC_M4RCR_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_M4RCR_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_M4RCR_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_M4RCR_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_M4RCR_WDOG3_RST_OPTION BSP_BIT32(9) +#define IMX_SRC_M4RCR_WDOG3_RST_OPTION_M4 BSP_BIT32(8) +#define IMX_SRC_M4RCR_MASK_WDOG3_RST(val) BSP_FLD32(val, 4, 7) +#define IMX_SRC_M4RCR_MASK_WDOG3_RST_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_SRC_M4RCR_MASK_WDOG3_RST_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define IMX_SRC_M4RCR_ENABLE_M4 BSP_BIT32(3) +#define IMX_SRC_M4RCR_SW_M4P_RST BSP_BIT32(2) +#define IMX_SRC_M4RCR_SW_M4C_RST BSP_BIT32(1) +#define IMX_SRC_M4RCR_SW_M4C_NON_SCLR_RST BSP_BIT32(0) + uint32_t reserved_10; + uint32_t ercr; + uint32_t reserved_18; + uint32_t hsicphy_rcr; + uint32_t usbophy1_rcr; + uint32_t usbophy2_rcr; + uint32_t mipiphy_rcr; + uint32_t pciephy_rcr; + uint32_t reserved_30[10]; + uint32_t sbmr1; + uint32_t srsr; + uint32_t reserved_60[2]; + uint32_t sisr; + uint32_t simr; + uint32_t sbmr2; + uint32_t gpr1; + uint32_t gpr2; + uint32_t gpr3; + uint32_t gpr4; + uint32_t gpr5; + uint32_t gpr6; + uint32_t gpr7; + uint32_t gpr8; + uint32_t gpr9; + uint32_t gpr10; + uint32_t reserved_9c[985]; + uint32_t ddrc_rcr; +} imx_src; + +#endif /* IMX_SRCREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h new file mode 100644 index 0000000000..35862601e2 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_UARTREG_H +#define IMX_UARTREG_H + +#include + +typedef struct { + uint32_t urxd; +#define IMX_UART_URXD_CHARRDY BSP_BIT32(15) +#define IMX_UART_URXD_ERR BSP_BIT32(14) +#define IMX_UART_URXD_OVRRUN BSP_BIT32(13) +#define IMX_UART_URXD_FRMERR BSP_BIT32(12) +#define IMX_UART_URXD_BRK BSP_BIT32(11) +#define IMX_UART_URXD_PRERR BSP_BIT32(10) +#define IMX_UART_URXD_RX_DATA(val) BSP_FLD32(val, 0, 7) +#define IMX_UART_URXD_RX_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define IMX_UART_URXD_RX_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t reserved_04[15]; + uint32_t utxd; +#define IMX_UART_UTXD_TX_DATA(val) BSP_FLD32(val, 0, 7) +#define IMX_UART_UTXD_TX_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define IMX_UART_UTXD_TX_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t reserved_44[15]; + uint32_t ucr1; +#define IMX_UART_UCR1_ADEN BSP_BIT32(15) +#define IMX_UART_UCR1_ADBR BSP_BIT32(14) +#define IMX_UART_UCR1_TRDYEN BSP_BIT32(13) +#define IMX_UART_UCR1_IDEN BSP_BIT32(12) +#define IMX_UART_UCR1_ICD(val) BSP_FLD32(val, 10, 11) +#define IMX_UART_UCR1_ICD_GET(reg) BSP_FLD32GET(reg, 10, 11) +#define IMX_UART_UCR1_ICD_SET(reg, val) BSP_FLD32SET(reg, val, 10, 11) +#define IMX_UART_UCR1_RRDYEN BSP_BIT32(9) +#define IMX_UART_UCR1_RXDMAEN BSP_BIT32(8) +#define IMX_UART_UCR1_IREN BSP_BIT32(7) +#define IMX_UART_UCR1_TXMPTYEN BSP_BIT32(6) +#define IMX_UART_UCR1_RTSDEN BSP_BIT32(5) +#define IMX_UART_UCR1_SNDBRK BSP_BIT32(4) +#define IMX_UART_UCR1_TXDMAEN BSP_BIT32(3) +#define IMX_UART_UCR1_ATDMAEN BSP_BIT32(2) +#define IMX_UART_UCR1_DOZE BSP_BIT32(1) +#define IMX_UART_UCR1_UARTEN BSP_BIT32(0) + uint32_t ucr2; +#define IMX_UART_UCR2_ESCI BSP_BIT32(15) +#define IMX_UART_UCR2_IRTS BSP_BIT32(14) +#define IMX_UART_UCR2_CTSC BSP_BIT32(13) +#define IMX_UART_UCR2_CTS BSP_BIT32(12) +#define IMX_UART_UCR2_ESCEN BSP_BIT32(11) +#define IMX_UART_UCR2_RTEC(val) BSP_FLD32(val, 9, 10) +#define IMX_UART_UCR2_RTEC_GET(reg) BSP_FLD32GET(reg, 9, 10) +#define IMX_UART_UCR2_RTEC_SET(reg, val) BSP_FLD32SET(reg, val, 9, 10) +#define IMX_UART_UCR2_PREN BSP_BIT32(8) +#define IMX_UART_UCR2_PROE BSP_BIT32(7) +#define IMX_UART_UCR2_STPB BSP_BIT32(6) +#define IMX_UART_UCR2_WS BSP_BIT32(5) +#define IMX_UART_UCR2_RTSEN BSP_BIT32(4) +#define IMX_UART_UCR2_ATEN BSP_BIT32(3) +#define IMX_UART_UCR2_TXEN BSP_BIT32(2) +#define IMX_UART_UCR2_RXEN BSP_BIT32(1) +#define IMX_UART_UCR2_SRST BSP_BIT32(0) + uint32_t ucr3; +#define IMX_UART_UCR3_DPEC(val) BSP_FLD32(val, 14, 15) +#define IMX_UART_UCR3_DPEC_GET(reg) BSP_FLD32GET(reg, 14, 15) +#define IMX_UART_UCR3_DPEC_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15) +#define IMX_UART_UCR3_DTREN BSP_BIT32(13) +#define IMX_UART_UCR3_PARERREN BSP_BIT32(12) +#define IMX_UART_UCR3_FRAERREN BSP_BIT32(11) +#define IMX_UART_UCR3_DSR BSP_BIT32(10) +#define IMX_UART_UCR3_DCD BSP_BIT32(9) +#define IMX_UART_UCR3_RI BSP_BIT32(8) +#define IMX_UART_UCR3_ADNIMP BSP_BIT32(7) +#define IMX_UART_UCR3_RXDSEN BSP_BIT32(6) +#define IMX_UART_UCR3_AIRINTEN BSP_BIT32(5) +#define IMX_UART_UCR3_AWAKEN BSP_BIT32(4) +#define IMX_UART_UCR3_DTRDEN BSP_BIT32(3) +#define IMX_UART_UCR3_RXDMUXSEL BSP_BIT32(2) +#define IMX_UART_UCR3_INVT BSP_BIT32(1) +#define IMX_UART_UCR3_ACIEN BSP_BIT32(0) + uint32_t ucr4; +#define IMX_UART_UCR4_CTSTL(val) BSP_FLD32(val, 10, 15) +#define IMX_UART_UCR4_CTSTL_GET(reg) BSP_FLD32GET(reg, 10, 15) +#define IMX_UART_UCR4_CTSTL_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15) +#define IMX_UART_UCR4_INVR BSP_BIT32(9) +#define IMX_UART_UCR4_ENIRI BSP_BIT32(8) +#define IMX_UART_UCR4_WKEN BSP_BIT32(7) +#define IMX_UART_UCR4_IDDMAEN BSP_BIT32(6) +#define IMX_UART_UCR4_IRSC BSP_BIT32(5) +#define IMX_UART_UCR4_LPBYP BSP_BIT32(4) +#define IMX_UART_UCR4_TCEN BSP_BIT32(3) +#define IMX_UART_UCR4_BKEN BSP_BIT32(2) +#define IMX_UART_UCR4_OREN BSP_BIT32(1) +#define IMX_UART_UCR4_DREN BSP_BIT32(0) + uint32_t ufcr; +#define IMX_UART_UFCR_TXTL(val) BSP_FLD32(val, 10, 15) +#define IMX_UART_UFCR_TXTL_GET(reg) BSP_FLD32GET(reg, 10, 15) +#define IMX_UART_UFCR_TXTL_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15) +#define IMX_UART_UFCR_RFDIV(val) BSP_FLD32(val, 7, 9) +#define IMX_UART_UFCR_RFDIV_GET(reg) BSP_FLD32GET(reg, 7, 9) +#define IMX_UART_UFCR_RFDIV_SET(reg, val) BSP_FLD32SET(reg, val, 7, 9) +#define IMX_UART_UFCR_DCEDTE BSP_BIT32(6) +#define IMX_UART_UFCR_RXTL(val) BSP_FLD32(val, 0, 5) +#define IMX_UART_UFCR_RXTL_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define IMX_UART_UFCR_RXTL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t usr1; +#define IMX_UART_USR1_PARITYERR BSP_BIT32(15) +#define IMX_UART_USR1_RTSS BSP_BIT32(14) +#define IMX_UART_USR1_TRDY BSP_BIT32(13) +#define IMX_UART_USR1_RTSD BSP_BIT32(12) +#define IMX_UART_USR1_ESCF BSP_BIT32(11) +#define IMX_UART_USR1_FRAMERR BSP_BIT32(10) +#define IMX_UART_USR1_RRDY BSP_BIT32(9) +#define IMX_UART_USR1_AGTIM BSP_BIT32(8) +#define IMX_UART_USR1_DTRD BSP_BIT32(7) +#define IMX_UART_USR1_RXDS BSP_BIT32(6) +#define IMX_UART_USR1_AIRINT BSP_BIT32(5) +#define IMX_UART_USR1_AWAKE BSP_BIT32(4) +#define IMX_UART_USR1_SAD BSP_BIT32(3) + uint32_t usr2; +#define IMX_UART_USR2_ADET BSP_BIT32(15) +#define IMX_UART_USR2_TXFE BSP_BIT32(14) +#define IMX_UART_USR2_DTRF BSP_BIT32(13) +#define IMX_UART_USR2_IDLE BSP_BIT32(12) +#define IMX_UART_USR2_ACST BSP_BIT32(11) +#define IMX_UART_USR2_RIDELT BSP_BIT32(10) +#define IMX_UART_USR2_RIIN BSP_BIT32(9) +#define IMX_UART_USR2_IRINT BSP_BIT32(8) +#define IMX_UART_USR2_WAKE BSP_BIT32(7) +#define IMX_UART_USR2_DCDDELT BSP_BIT32(6) +#define IMX_UART_USR2_DCDIN BSP_BIT32(5) +#define IMX_UART_USR2_RTSF BSP_BIT32(4) +#define IMX_UART_USR2_TXDC BSP_BIT32(3) +#define IMX_UART_USR2_BRCD BSP_BIT32(2) +#define IMX_UART_USR2_ORE BSP_BIT32(1) +#define IMX_UART_USR2_RDR BSP_BIT32(0) + uint32_t uesc; + uint32_t utim; + uint32_t ubir; + uint32_t ubmr; + uint32_t ubrc; + uint32_t onems; + uint32_t uts; +#define IMX_UART_UTS_FRCPERR BSP_BIT32(13) +#define IMX_UART_UTS_LOOP BSP_BIT32(12) +#define IMX_UART_UTS_DBGEN BSP_BIT32(11) +#define IMX_UART_UTS_LOOPIR BSP_BIT32(10) +#define IMX_UART_UTS_RXDBG BSP_BIT32(9) +#define IMX_UART_UTS_TXEMPTY BSP_BIT32(6) +#define IMX_UART_UTS_RXEMPTY BSP_BIT32(5) +#define IMX_UART_UTS_TXFULL BSP_BIT32(4) +#define IMX_UART_UTS_RXFULL BSP_BIT32(3) +#define IMX_UART_UTS_SOFTRST BSP_BIT32(0) + uint32_t umcr; +#define IMX_UART_UMCR_SLADDR(val) BSP_FLD32(val, 8, 15) +#define IMX_UART_UMCR_SLADDR_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define IMX_UART_UMCR_SLADDR_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define IMX_UART_UMCR_SADEN BSP_BIT32(3) +#define IMX_UART_UMCR_TXB8 BSP_BIT32(2) +#define IMX_UART_UMCR_SLAM BSP_BIT32(1) +#define IMX_UART_UMCR_MDEN BSP_BIT32(0) +} imx_uart; + +#endif /* IMX_UARTREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h new file mode 100644 index 0000000000..e26dfb2cc3 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h @@ -0,0 +1,62 @@ +/*- + * Copyright (c) 2012, 2013 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Oleksandr Rybalko under sponsorship + * from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/freescale/imx/imx_wdogreg.h 291367 2015-11-26 17:26:52Z ian $ + */ + +#define WDOG_CLK_FREQ 32768 + +#define WDOG_CR_REG 0x00 /* Control Register */ +#define WDOG_CR_WT_MASK 0xff00 /* Count of 0.5 sec */ +#define WDOG_CR_WT_SHIFT 8 +#define WDOG_CR_WDW (1 << 7) /* Suspend WDog */ +#define WDOG_CR_WDA (1 << 5) /* Don't touch ipp_wdog */ +#define WDOG_CR_SRS (1 << 4) /* Don't touch sys_reset */ +#define WDOG_CR_WDT (1 << 3) /* Assert ipp_wdog on tout */ +#define WDOG_CR_WDE (1 << 2) /* WDog Enable */ +#define WDOG_CR_WDBG (1 << 1) /* Suspend when DBG mode */ +#define WDOG_CR_WDZST (1 << 0) /* Suspend when LP mode */ + +#define WDOG_SR_REG 0x02 /* Service Register */ +#define WDOG_SR_STEP1 0x5555 +#define WDOG_SR_STEP2 0xaaaa + +#define WDOG_RSR_REG 0x04 /* Reset Status Register */ +#define WDOG_RSR_POR (1 << 4) /* Due to Power-On Reset */ +#define WDOG_RSR_TOUT (1 << 1) /* Due WDog timeout reset */ +#define WDOG_RSR_SFTW (1 << 0) /* Due Soft reset */ + +#define WDOG_ICR_REG 0x06 /* Interrupt Control Register */ +#define WDOG_ICR_WIE (1 << 15) /* Enable Interrupt */ +#define WDOG_ICR_WTIS (1 << 14) /* Interrupt has occurred */ +#define WDOG_ICR_WTCT_MASK 0x00ff +#define WDOG_ICR_WTCT_SHIFT 0 /* Interrupt hold time */ + +#define WDOG_MCR_REG 0x08 /* Miscellaneous Control Register */ +#define WDOG_MCR_PDE (1 << 0) + diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h new file mode 100644 index 0000000000..b5fb7127df --- /dev/null +++ b/bsps/arm/imx/include/bsp.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_IMX_BSP_H +#define LIBBSP_ARM_IMX_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_FDT_IS_SUPPORTED + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_ARM_GIC_DIST_BASE 0x31001000 + +#define BSP_ARM_GIC_CPUIF_BASE 0x31002000 + +#define BSP_ARM_A9MPCORE_GT_BASE 0 + +#define BSP_ARM_A9MPCORE_SCU_BASE 0 + +void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq); + +void *imx_get_reg_of_node(const void *fdt, int node); + +int imx_iomux_configure_pins(const void *fdt, uint32_t phandle); + +rtems_vector_number imx_get_irq_of_node( + const void *fdt, + int node, + size_t index +); + +void imx_uart_console_drain(void); + +/** + * @brief Registers an IMX I2C bus driver. + * + * @param[in] bus_path The I2C bus driver device path, e.g. "/dev/i2c-0". + * @param[in] alias_or_path The FDT alias or path, e.g. "i2c0". + * + * @retval 0 Successful operation. + * @retval -1 An error occurred. The errno is set to indicate the error. + */ +int i2c_bus_register_imx(const char *bus_path, const char *alias_or_path); + +/** + * @brief Registers an IMX ECSPI bus driver. + * + * @param[in] bus_path The ECSPI bus driver device path, e.g. "/dev/spi-0". + * @param[in] alias_or_path The FDT alias or path, e.g. "spi0". + * + * @retval 0 Successful operation. + * @retval -1 An error occurred. The errno is set to indicate the error. + */ +int spi_bus_register_imx(const char *bus_path, const char *alias_or_path); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_IMX_BSP_H */ diff --git a/bsps/arm/imx/include/bsp/irq.h b/bsps/arm/imx/include/bsp/irq.h new file mode 100644 index 0000000000..73d2e69b30 --- /dev/null +++ b/bsps/arm/imx/include/bsp/irq.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_IMX_IRQ_H +#define LIBBSP_ARM_IMX_IRQ_H + +#ifndef ASM + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 159 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_IMX_IRQ_H */ diff --git a/bsps/arm/imx/include/tm27.h b/bsps/arm/imx/include/tm27.h new file mode 100644 index 0000000000..c17c0107b4 --- /dev/null +++ b/bsps/arm/imx/include/tm27.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +#endif /* __tm27_h */ diff --git a/bsps/arm/include/bsp/arm-a8core-start.h b/bsps/arm/include/bsp/arm-a8core-start.h new file mode 100644 index 0000000000..416f282028 --- /dev/null +++ b/bsps/arm/include/bsp/arm-a8core-start.h @@ -0,0 +1,55 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief A8CORE_START Support + */ + +/* + * Copyright (c) 2014 Chris Johns . All rights reserved. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A8CORE_START_H +#define LIBBSP_ARM_SHARED_ARM_A8CORE_START_H + +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +BSP_START_TEXT_SECTION static inline arm_a8core_start_set_vector_base(void) +{ + /* + * Do not use bsp_vector_table_begin == 0, since this will get optimized away. + */ + if (bsp_vector_table_end != bsp_vector_table_size) { + uint32_t ctrl; + + arm_cp15_set_vector_base_address(bsp_vector_table_begin); + + ctrl = arm_cp15_get_control(); + ctrl &= ~ARM_CP15_CTRL_V; + arm_cp15_set_control(ctrl); + } +} + +BSP_START_TEXT_SECTION static inline arm_a8core_start_hook_1(void) +{ + arm_a8core_start_set_vector_base(); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_A8CORE_START_H */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-clock.h b/bsps/arm/include/bsp/arm-a9mpcore-clock.h new file mode 100644 index 0000000000..9a8c653801 --- /dev/null +++ b/bsps/arm/include/bsp/arm-a9mpcore-clock.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2013 Chris Johns . All rights reserved. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_CLOCK_H +#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_CLOCK_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * Return the peripheral clock. For systems such as the zynq this + * is controlled by the PL logic generation and can vary. Provide this + * function in your application to override the BSP default. + */ +uint32_t a9mpcore_clock_periphclk(void); + +/** + * @brief Do early clock initialization so that the CPU counter conversion + * works. + */ +static inline void a9mpcore_clock_initialize_early(void) +{ + rtems_counter_initialize_converter(a9mpcore_clock_periphclk()); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_CLOCK_H */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-irq.h b/bsps/arm/include/bsp/arm-a9mpcore-irq.h new file mode 100644 index 0000000000..f0d3c1b983 --- /dev/null +++ b/bsps/arm/include/bsp/arm-a9mpcore-irq.h @@ -0,0 +1,40 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM_A9MPCORE_IRQ Support + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_IRQ_H +#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define A9MPCORE_IRQ_GT 27 +#define A9MPCORE_IRQ_NFIQ 28 +#define A9MPCORE_IRQ_PT 29 +#define A9MPCORE_IRQ_PW 30 +#define A9MPCORE_IRQ_NIRQ 31 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_IRQ_H */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-regs.h b/bsps/arm/include/bsp/arm-a9mpcore-regs.h new file mode 100644 index 0000000000..d1538357d8 --- /dev/null +++ b/bsps/arm/include/bsp/arm-a9mpcore-regs.h @@ -0,0 +1,133 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM_A9MPCORE_REGS Support + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H +#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H + +#include + +typedef struct { + uint32_t ctrl; +#define A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0) +#define A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1) +#define A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2) +#define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3) +#define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4) +#define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5) +#define A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6) + uint32_t cfg; +#define A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1) +#define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7) +#define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15) +#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) + uint32_t pwrst; + uint32_t invss; +#define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3) +#define A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7) +#define A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11) +#define A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15) +#define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) + uint32_t reserved_09[8]; + uint32_t diagn_ctrl; +#define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0) + uint32_t reserved_10[3]; + uint32_t fltstart; + uint32_t fltend; + uint32_t reserved_48[2]; + uint32_t sac; + uint32_t snsac; +} a9mpcore_scu; + +typedef struct { +} a9mpcore_gic; + +typedef struct { + uint32_t cntrlower; + uint32_t cntrupper; +#define A9MPCORE_GT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15) +#define A9MPCORE_GT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define A9MPCORE_GT_CTRL_AUTOINC_EN BSP_BIT32(3) +#define A9MPCORE_GT_CTRL_IRQ_EN BSP_BIT32(2) +#define A9MPCORE_GT_CTRL_COMP_EN BSP_BIT32(1) +#define A9MPCORE_GT_CTRL_TMR_EN BSP_BIT32(0) + uint32_t ctrl; +#define A9MPCORE_GT_IRQST_EFLG BSP_BIT32(0) + uint32_t irqst; + uint32_t cmpvallower; + uint32_t cmpvalupper; + uint32_t autoinc; +} a9mpcore_gt; + +typedef struct { + uint32_t load; + uint32_t cntr; + uint32_t ctrl; +#define A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15) +#define A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2) +#define A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1) +#define A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0) + uint32_t irqst; +#define A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0) +} a9mpcore_pt; + +typedef struct { + uint32_t load; + uint32_t cntr; + uint32_t ctrl; + uint32_t irqst; + uint32_t rstst; + uint32_t dis; +} a9mpcore_pw; + +typedef struct { +} a9mpcore_idist; + +typedef struct { + a9mpcore_scu scu; + uint32_t reserved_58[42]; + a9mpcore_gic gic; + uint32_t reserved_100[64]; + a9mpcore_gt gt; + uint32_t reserved_21c[249]; + a9mpcore_pt pt; + uint32_t reserved_610[4]; + a9mpcore_pw pw; + uint32_t reserved_638[626]; + a9mpcore_idist idist; +} a9mpcore; + +#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-start.h b/bsps/arm/include/bsp/arm-a9mpcore-start.h new file mode 100644 index 0000000000..7d6185b39e --- /dev/null +++ b/bsps/arm/include/bsp/arm-a9mpcore-start.h @@ -0,0 +1,172 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief A9MPCORE_START Support + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H +#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H + +#include + +#include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_set_vector_base(void) +{ + /* + * Do not use bsp_vector_table_begin == 0, since this will get optimized away. + */ + if (bsp_vector_table_end != bsp_vector_table_size) { + uint32_t ctrl; + + /* + * For now we assume that every Cortex-A9 MPCore has the Security Extensions. + * Later it might be necessary to evaluate the ID_PFR1 register. + */ + arm_cp15_set_vector_base_address(bsp_vector_table_begin); + + ctrl = arm_cp15_get_control(); + ctrl &= ~ARM_CP15_CTRL_V; + arm_cp15_set_control(ctrl); + } +} + +BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_scu_invalidate( + volatile a9mpcore_scu *scu, + uint32_t cpu_id, + uint32_t ways +) +{ + scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4); +} + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_errata_764369_handler(volatile a9mpcore_scu *scu) +{ + if (arm_errata_is_applicable_processor_errata_764369()) { + scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE; + } +} + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_scu_enable(volatile a9mpcore_scu *scu) +{ + scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN; + arm_a9mpcore_start_errata_764369_handler(scu); +} + +#ifdef RTEMS_SMP +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_on_secondary_processor(void) +{ + uint32_t ctrl; + + arm_a9mpcore_start_set_vector_base(); + + arm_gic_irq_initialize_secondary_cpu(); + + ctrl = arm_cp15_start_setup_mmu_and_cache( + 0, + ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z + ); + + arm_cp15_set_domain_access_control( + ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT) + ); + + /* FIXME: Sharing the translation table between processors is brittle */ + arm_cp15_set_translation_table_base( + (uint32_t *) bsp_translation_table_base + ); + + ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; + arm_cp15_set_control(ctrl); + + _SMP_Start_multitasking_on_secondary_processor(); +} + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_enable_smp_in_auxiliary_control(void) +{ + /* + * Enable cache coherency support and cache/MMU maintenance broadcasts for + * this processor. + */ + uint32_t actlr = arm_cp15_get_auxiliary_control(); + actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW; + arm_cp15_set_auxiliary_control(actlr); +} +#endif + +BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void) +{ + volatile a9mpcore_scu *scu = + (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE; + uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id(); + + arm_cp15_branch_predictor_invalidate_all(); + + if (cpu_id == 0) { + arm_a9mpcore_start_scu_enable(scu); + } + +#ifdef RTEMS_SMP + arm_a9mpcore_start_enable_smp_in_auxiliary_control(); +#endif + + arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf); + +#ifdef RTEMS_SMP + if (cpu_id != 0) { + arm_a9mpcore_start_on_secondary_processor(); + } +#endif +} + +BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_global_timer(void) +{ + volatile a9mpcore_gt *gt = (volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE; + + gt->ctrl = 0; + gt->cntrlower = 0; + gt->cntrupper = 0; + gt->ctrl = A9MPCORE_GT_CTRL_TMR_EN; +} + +BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_1(void) +{ + arm_a9mpcore_start_global_timer(); + arm_a9mpcore_start_set_vector_base(); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H */ diff --git a/bsps/arm/include/bsp/arm-cp15-start.h b/bsps/arm/include/bsp/arm-cp15-start.h new file mode 100644 index 0000000000..a749f7dc98 --- /dev/null +++ b/bsps/arm/include/bsp/arm-cp15-start.h @@ -0,0 +1,187 @@ +/** + * @file + * + * @ingroup arm_start + * + * @brief Arm CP15 start. + */ + + +/* + * Copyright (c) 2013 Hesham AL-Matary. + * Copyright (c) 2009-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_CP15_START_H +#define LIBBSP_ARM_SHARED_ARM_CP15_START_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + uint32_t begin; + uint32_t end; + uint32_t flags; +} arm_cp15_start_section_config; + +#define ARMV7_CP15_START_DEFAULT_SECTIONS \ + { \ + .begin = (uint32_t) bsp_section_fast_text_begin, \ + .end = (uint32_t) bsp_section_fast_text_end, \ + .flags = ARMV7_MMU_CODE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_fast_data_begin, \ + .end = (uint32_t) bsp_section_fast_data_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_start_begin, \ + .end = (uint32_t) bsp_section_start_end, \ + .flags = ARMV7_MMU_CODE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_vector_begin, \ + .end = (uint32_t) bsp_section_vector_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_text_begin, \ + .end = (uint32_t) bsp_section_text_end, \ + .flags = ARMV7_MMU_CODE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_rodata_begin, \ + .end = (uint32_t) bsp_section_rodata_end, \ + .flags = ARMV7_MMU_DATA_READ_ONLY_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_data_begin, \ + .end = (uint32_t) bsp_section_data_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_bss_begin, \ + .end = (uint32_t) bsp_section_bss_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_work_begin, \ + .end = (uint32_t) bsp_section_work_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_stack_begin, \ + .end = (uint32_t) bsp_section_stack_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_nocache_begin, \ + .end = (uint32_t) bsp_section_nocache_end, \ + .flags = ARMV7_MMU_DEVICE \ + }, { \ + .begin = (uint32_t) bsp_section_nocachenoload_begin, \ + .end = (uint32_t) bsp_section_nocachenoload_end, \ + .flags = ARMV7_MMU_DEVICE \ + }, { \ + .begin = (uint32_t) bsp_translation_table_base, \ + .end = (uint32_t) bsp_translation_table_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + } + +BSP_START_DATA_SECTION extern const arm_cp15_start_section_config + arm_cp15_start_mmu_config_table[]; + +BSP_START_DATA_SECTION extern const size_t + arm_cp15_start_mmu_config_table_size; + +BSP_START_TEXT_SECTION static inline void +arm_cp15_start_set_translation_table_entries( + uint32_t *ttb, + const arm_cp15_start_section_config *config +) +{ + uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin); + uint32_t iend = + ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end)); + uint32_t index_mask = (1U << (32 - ARM_MMU_SECT_BASE_SHIFT)) - 1U; + + if (config->begin != config->end) { + while (i != iend) { + ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags; + i = (i + 1U) & index_mask; + } + } +} + +BSP_START_TEXT_SECTION static inline void +arm_cp15_start_setup_translation_table( + uint32_t *ttb, + uint32_t client_domain, + const arm_cp15_start_section_config *config_table, + size_t config_count +) +{ + uint32_t dac = ARM_CP15_DAC_DOMAIN(client_domain, ARM_CP15_DAC_CLIENT); + size_t i; + + arm_cp15_set_domain_access_control(dac); + arm_cp15_set_translation_table_base(ttb); + + /* Initialize translation table with invalid entries */ + for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) { + ttb [i] = 0; + } + + for (i = 0; i < config_count; ++i) { + arm_cp15_start_set_translation_table_entries(ttb, &config_table [i]); + } +} + +BSP_START_TEXT_SECTION static inline void +arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( + uint32_t ctrl, + uint32_t *ttb, + uint32_t client_domain, + const arm_cp15_start_section_config *config_table, + size_t config_count +) +{ + arm_cp15_start_setup_translation_table( + ttb, + client_domain, + config_table, + config_count + ); + + /* Enable MMU and cache */ + ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; + + arm_cp15_set_control(ctrl); +} + +BSP_START_TEXT_SECTION static inline uint32_t +arm_cp15_start_setup_mmu_and_cache(uint32_t ctrl_clear, uint32_t ctrl_set) +{ + uint32_t ctrl = arm_cp15_get_control(); + + ctrl &= ~ctrl_clear; + ctrl |= ctrl_set; + + arm_cp15_set_control(ctrl); + + arm_cp15_tlb_invalidate(); + + return ctrl; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_CP15_START_H */ diff --git a/bsps/arm/include/bsp/arm-errata.h b/bsps/arm/include/bsp/arm-errata.h new file mode 100644 index 0000000000..5108c98f15 --- /dev/null +++ b/bsps/arm/include/bsp/arm-errata.h @@ -0,0 +1,121 @@ +/** + * @file arm-errata.h + * + * @ingroup arm_shared + * + * @brief Create #defines which state which erratas shall get applied + */ + +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef ARM_ERRATA_H_ +#define ARM_ERRATA_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +static inline arm_release_id arm_errata_get_processor_release(void) +{ + const uint32_t MIDR = arm_cp15_get_id_code(); + const uint8_t REVISION = (MIDR & 0xF00000U) >> 20; + const uint8_t PATCH_LEVEL = (MIDR & 0xFU); + + return ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( + REVISION, + PATCH_LEVEL + ); +} + +static inline bool arm_errata_is_applicable_processor_errata_764369(void) +{ +#if defined(RTEMS_SMP) + const arm_release_id RELEASE = arm_errata_get_processor_release(); + bool is_applicable = false; + + /* Errata information for Cortex-A9 processors. + * Information taken from ARMs + * "Cortex-A series processors + * - Cortex-A9 + * - Software Developers Errata Notice + * - Revision r4 revisions + * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice" + * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html + * Please see this document for more information on these erratas */ + + switch( RELEASE ) { + case ARM_RELEASE_ID_R4_P1: + case ARM_RELEASE_ID_R4_P4: + case ARM_RELEASE_ID_R3_P0: + case ARM_RELEASE_ID_R2_P10: + case ARM_RELEASE_ID_R2_P8: + case ARM_RELEASE_ID_R2_P6: + case ARM_RELEASE_ID_R2_P4: + case ARM_RELEASE_ID_R2_P3: + case ARM_RELEASE_ID_R2_P2: + case ARM_RELEASE_ID_R2_P0: + is_applicable = true; + break; + default: + is_applicable = false; + break; + } + + return is_applicable; +#else + return false; +#endif +} + +static inline bool arm_errata_is_applicable_processor_errata_775420(void) +{ + const arm_release_id RELEASE = arm_errata_get_processor_release(); + bool is_applicable = false; + + /* Errata information for Cortex-A9 processors. + * Information taken from ARMs + * "Cortex-A series processors + * - Cortex-A9 + * - Software Developers Errata Notice + * - Revision r4 revisions + * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice" + * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html + * Please see this document for more information on these erratas */ + + switch( RELEASE ) { + case ARM_RELEASE_ID_R2_P10: + case ARM_RELEASE_ID_R2_P8: + case ARM_RELEASE_ID_R2_P6: + case ARM_RELEASE_ID_R2_P4: + case ARM_RELEASE_ID_R2_P3: + case ARM_RELEASE_ID_R2_P2: + is_applicable = true; + break; + default: + is_applicable = false; + break; + } + + return is_applicable; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ARM_ERRATA_H_ */ diff --git a/bsps/arm/include/bsp/arm-gic-irq.h b/bsps/arm/include/bsp/arm-gic-irq.h new file mode 100644 index 0000000000..09d3fe5ac2 --- /dev/null +++ b/bsps/arm/include/bsp/arm-gic-irq.h @@ -0,0 +1,112 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC IRQ + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H +#define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define ARM_GIC_IRQ_SGI_0 0 +#define ARM_GIC_IRQ_SGI_1 1 +#define ARM_GIC_IRQ_SGI_2 2 +#define ARM_GIC_IRQ_SGI_3 3 +#define ARM_GIC_IRQ_SGI_5 5 +#define ARM_GIC_IRQ_SGI_6 6 +#define ARM_GIC_IRQ_SGI_7 7 +#define ARM_GIC_IRQ_SGI_8 8 +#define ARM_GIC_IRQ_SGI_9 9 +#define ARM_GIC_IRQ_SGI_10 10 +#define ARM_GIC_IRQ_SGI_11 11 +#define ARM_GIC_IRQ_SGI_12 12 +#define ARM_GIC_IRQ_SGI_13 13 +#define ARM_GIC_IRQ_SGI_14 14 +#define ARM_GIC_IRQ_SGI_15 15 + +#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE) + +rtems_status_code arm_gic_irq_set_priority( + rtems_vector_number vector, + uint8_t priority +); + +rtems_status_code arm_gic_irq_get_priority( + rtems_vector_number vector, + uint8_t *priority +); + +void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +); + +void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +); + +typedef enum { + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF +} arm_gic_irq_software_irq_target_filter; + +static inline rtems_status_code arm_gic_irq_generate_software_irq( + rtems_vector_number vector, + arm_gic_irq_software_irq_target_filter filter, + uint8_t targets +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + if (vector <= ARM_GIC_IRQ_SGI_15) { + volatile gic_dist *dist = ARM_GIC_DIST; + + dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter) + | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets) + | GIC_DIST_ICDSGIR_SGIINTID(vector); + } else { + sc = RTEMS_INVALID_ID; + } + + return sc; +} + +static inline uint32_t arm_gic_irq_processor_count(void) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + + return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1; +} + +void arm_gic_irq_initialize_secondary_cpu(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */ diff --git a/bsps/arm/include/bsp/arm-gic-regs.h b/bsps/arm/include/bsp/arm-gic-regs.h new file mode 100644 index 0000000000..2375b5cf74 --- /dev/null +++ b/bsps/arm/include/bsp/arm-gic-regs.h @@ -0,0 +1,138 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC Register definitions + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H +#define LIBBSP_ARM_SHARED_ARM_GIC_REGS_H + +#include + +typedef struct { + uint32_t iccicr; +#define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0) + uint32_t iccpmr; +#define GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7) +#define GIC_CPUIF_ICCPMR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define GIC_CPUIF_ICCPMR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t iccbpr; +#define GIC_CPUIF_ICCBPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2) +#define GIC_CPUIF_ICCBPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define GIC_CPUIF_ICCBPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + uint32_t icciar; +#define GIC_CPUIF_ICCIAR_CPUID(val) BSP_FLD32(val, 10, 12) +#define GIC_CPUIF_ICCIAR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define GIC_CPUIF_ICCIAR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define GIC_CPUIF_ICCIAR_ACKINTID(val) BSP_FLD32(val, 0, 9) +#define GIC_CPUIF_ICCIAR_ACKINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define GIC_CPUIF_ICCIAR_ACKINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t icceoir; +#define GIC_CPUIF_ICCEOIR_CPUID(val) BSP_FLD32(val, 10, 12) +#define GIC_CPUIF_ICCEOIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define GIC_CPUIF_ICCEOIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define GIC_CPUIF_ICCEOIR_EOIINTID(val) BSP_FLD32(val, 0, 9) +#define GIC_CPUIF_ICCEOIR_EOIINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define GIC_CPUIF_ICCEOIR_EOIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t iccrpr; +#define GIC_CPUIF_ICCRPR_PRIORITY(val) BSP_FLD32(val, 0, 7) +#define GIC_CPUIF_ICCRPR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define GIC_CPUIF_ICCRPR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t icchpir; +#define GIC_CPUIF_ICCHPIR_CPUID(val) BSP_FLD32(val, 10, 12) +#define GIC_CPUIF_ICCHPIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define GIC_CPUIF_ICCHPIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define GIC_CPUIF_ICCHPIR_PENDINTID(val) BSP_FLD32(val, 0, 9) +#define GIC_CPUIF_ICCHPIR_PENDINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define GIC_CPUIF_ICCHPIR_PENDINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t iccabpr; +#define GIC_CPUIF_ICCABPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2) +#define GIC_CPUIF_ICCABPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define GIC_CPUIF_ICCABPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + uint32_t reserved_20[55]; + uint32_t icciidr; +#define GIC_CPUIF_ICCIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31) +#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) +#define GIC_CPUIF_ICCIIDR_ARCH_VERSION(val) BSP_FLD32(val, 16, 19) +#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define GIC_CPUIF_ICCIIDR_REVISION(val) BSP_FLD32(val, 12, 15) +#define GIC_CPUIF_ICCIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define GIC_CPUIF_ICCIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define GIC_CPUIF_ICCIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11) +#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) +} gic_cpuif; + +typedef struct { + uint32_t icddcr; +#define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0) + uint32_t icdictr; +#define GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15) +#define GIC_DIST_ICDICTR_LSPI_GET(reg) BSP_FLD32GET(reg, 11, 15) +#define GIC_DIST_ICDICTR_LSPI_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15) +#define GIC_DIST_ICDICTR_SECURITY_EXTN BSP_BIT32(10) +#define GIC_DIST_ICDICTR_CPU_NUMBER(val) BSP_FLD32(val, 5, 7) +#define GIC_DIST_ICDICTR_CPU_NUMBER_GET(reg) BSP_FLD32GET(reg, 5, 7) +#define GIC_DIST_ICDICTR_CPU_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) +#define GIC_DIST_ICDICTR_IT_LINES_NUMBER(val) BSP_FLD32(val, 0, 4) +#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) + uint32_t icdiidr; +#define GIC_DIST_ICDIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31) +#define GIC_DIST_ICDIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define GIC_DIST_ICDIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) +#define GIC_DIST_ICDIIDR_VARIANT(val) BSP_FLD32(val, 16, 19) +#define GIC_DIST_ICDIIDR_VARIANT_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define GIC_DIST_ICDIIDR_VARIANT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define GIC_DIST_ICDIIDR_REVISION(val) BSP_FLD32(val, 12, 15) +#define GIC_DIST_ICDIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define GIC_DIST_ICDIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define GIC_DIST_ICDIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11) +#define GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) + uint32_t reserved_0c[29]; + uint32_t icdisr[32]; + uint32_t icdiser[32]; + uint32_t icdicer[32]; + uint32_t icdispr[32]; + uint32_t icdicpr[32]; + uint32_t icdabr[32]; + uint32_t reserved_380[32]; + uint8_t icdipr[256]; + uint32_t reserved_500[192]; + uint8_t icdiptr[256]; + uint32_t reserved_900[192]; + uint32_t icdicfr[64]; + uint32_t reserved_d00[128]; + uint32_t icdsgir; +#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25) +#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_GET(reg) BSP_FLD32GET(reg, 24, 25) +#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25) +#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST(val) BSP_FLD32(val, 16, 23) +#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) +#define GIC_DIST_ICDSGIR_SATT BSP_BIT32(15) +#define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3) +#define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +} gic_dist; + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-gic-tm27.h b/bsps/arm/include/bsp/arm-gic-tm27.h new file mode 100644 index 0000000000..95f3077716 --- /dev/null +++ b/bsps/arm/include/bsp/arm-gic-tm27.h @@ -0,0 +1,103 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC TM27 Support + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H +#define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H + +#include + +#include +#include + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define ARM_GIC_TM27_IRQ_LOW ARM_GIC_IRQ_SGI_12 + +#define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13 + +#define ARM_GIC_TM27_PRIO_LOW 0x80 + +#define ARM_GIC_TM27_PRIO_HIGH 0x00 + +static inline void Install_tm27_vector(void (*handler)(rtems_vector_number)) +{ + rtems_status_code sc = rtems_interrupt_handler_install( + ARM_GIC_TM27_IRQ_LOW, + "tm27 low", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = arm_gic_irq_set_priority( + ARM_GIC_TM27_IRQ_LOW, + ARM_GIC_TM27_PRIO_LOW + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_interrupt_handler_install( + ARM_GIC_TM27_IRQ_HIGH, + "tm27 high", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = arm_gic_irq_set_priority( + ARM_GIC_TM27_IRQ_HIGH, + ARM_GIC_TM27_PRIO_HIGH + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline void Cause_tm27_intr(void) +{ + rtems_status_code sc = arm_gic_irq_generate_software_irq( + ARM_GIC_TM27_IRQ_LOW, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF, + 0 + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline void Clear_tm27_intr(void) +{ + /* Nothing to do */ +} + +static inline void Lower_tm27_intr(void) +{ + rtems_status_code sc = arm_gic_irq_generate_software_irq( + ARM_GIC_TM27_IRQ_HIGH, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF, + 0 + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */ diff --git a/bsps/arm/include/bsp/arm-gic.h b/bsps/arm/include/bsp/arm-gic.h new file mode 100644 index 0000000000..ab5840919a --- /dev/null +++ b/bsps/arm/include/bsp/arm-gic.h @@ -0,0 +1,207 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC Support + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_H +#define LIBBSP_ARM_SHARED_ARM_GIC_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_gic ARM GIC + * + * @ingroup arm_shared + * + * @brief ARM_GIC Support Package + */ + +#define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5) +#define GIC_ID_TO_ONE_BIT_REG_BIT(id) (1U << ((id) & 0x1fU)) + +#define GIC_ID_TO_TWO_BITS_REG_INDEX(id) ((id) >> 4) +#define GIC_ID_TO_TWO_BITS_REG_OFFSET(id) (((id) & 0xfU) << 1) + +static inline bool gic_id_is_enabled(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdiser[i] & bit) != 0; +} + +static inline void gic_id_enable(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdiser[i] = bit; +} + +static inline void gic_id_disable(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdicer[i] = bit; +} + +static inline bool gic_id_is_pending(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdispr[i] & bit) != 0; +} + +static inline void gic_id_set_pending(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdispr[i] = bit; +} + +static inline void gic_id_clear_pending(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdicpr[i] = bit; +} + +static inline bool gic_id_is_active(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdabr[i] & bit) != 0; +} + +static inline void gic_id_set_priority( + volatile gic_dist *dist, + uint32_t id, + uint8_t priority +) +{ + dist->icdipr[id] = priority; +} + +static inline uint8_t gic_id_get_priority(volatile gic_dist *dist, uint32_t id) +{ + return dist->icdipr[id]; +} + +static inline void gic_id_set_targets( + volatile gic_dist *dist, + uint32_t id, + uint8_t targets +) +{ + dist->icdiptr[id] = targets; +} + +static inline uint8_t gic_id_get_targets(volatile gic_dist *dist, uint32_t id) +{ + return dist->icdiptr[id]; +} + +typedef enum { + GIC_LEVEL_SENSITIVE, + GIC_EDGE_TRIGGERED +} gic_trigger_mode; + +static inline gic_trigger_mode gic_id_get_trigger_mode( + volatile gic_dist *dist, + uint32_t id +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1; + uint32_t bit = 1U << o; + + return (dist->icdicfr[i] & bit) != 0 ? + GIC_EDGE_TRIGGERED : GIC_LEVEL_SENSITIVE; +} + +static inline void gic_id_set_trigger_mode( + volatile gic_dist *dist, + uint32_t id, + gic_trigger_mode mode +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1; + uint32_t bit = mode << o; + uint32_t mask = 1U << o; + uint32_t icdicfr = dist->icdicfr[i]; + + icdicfr &= ~mask; + icdicfr |= bit; + + dist->icdicfr[i] = icdicfr; +} + +typedef enum { + GIC_N_TO_N, + GIC_1_TO_N +} gic_handling_model; + +static inline gic_handling_model gic_id_get_handling_model( + volatile gic_dist *dist, + uint32_t id +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id); + uint32_t bit = 1U << o; + + return (dist->icdicfr[i] & bit) != 0 ? GIC_1_TO_N : GIC_N_TO_N; +} + +static inline void gic_id_set_handling_model( + volatile gic_dist *dist, + uint32_t id, + gic_handling_model model +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id); + uint32_t bit = model << o; + uint32_t mask = 1U << o; + uint32_t icdicfr = dist->icdicfr[i]; + + icdicfr &= ~mask; + icdicfr |= bit; + + dist->icdicfr[i] = icdicfr; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_H */ diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h b/bsps/arm/include/bsp/arm-pl011-regs.h new file mode 100644 index 0000000000..2b930f4b4c --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl011-regs.h @@ -0,0 +1,130 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL011 Register definitions + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL011_REGS_H +#define LIBBSP_ARM_SHARED_ARM_PL011_REGS_H + +#include + +typedef struct { + uint32_t uartdr; +#define PL011_UARTDR_OE BSP_BIT32(11) +#define PL011_UARTDR_BE BSP_BIT32(10) +#define PL011_UARTDR_PE BSP_BIT32(9) +#define PL011_UARTDR_FE BSP_BIT32(8) +#define PL011_UARTDR_DATA(val) BSP_FLD32(val, 0, 7) +#define PL011_UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define PL011_UARTDR_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t uartrsr_uartecr; +#define PL011_UARTRSR_UARTECR_OE BSP_BIT32(3) +#define PL011_UARTRSR_UARTECR_BE BSP_BIT32(2) +#define PL011_UARTRSR_UARTECR_PE BSP_BIT32(1) +#define PL011_UARTRSR_UARTECR_FE BSP_BIT32(0) + uint32_t reserved_08[4]; + uint32_t uartfr; +#define PL011_UARTFR_RI BSP_BIT32(8) +#define PL011_UARTFR_TXFE BSP_BIT32(7) +#define PL011_UARTFR_RXFF BSP_BIT32(6) +#define PL011_UARTFR_TXFF BSP_BIT32(5) +#define PL011_UARTFR_RXFE BSP_BIT32(4) +#define PL011_UARTFR_BUSY BSP_BIT32(3) +#define PL011_UARTFR_DCD BSP_BIT32(2) +#define PL011_UARTFR_DSR BSP_BIT32(1) +#define PL011_UARTFR_CTS BSP_BIT32(0) + uint32_t reserved_1c; + uint32_t uartilpr; +#define PL011_UARTILPR_ILPDVSR(val) BSP_FLD32(val, 0, 7) +#define PL011_UARTILPR_ILPDVSR_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define PL011_UARTILPR_ILPDVSR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t uartibrd; +#define PL011_UARTIBRD_BAUD_DIVINT(val) BSP_FLD32(val, 0, 15) +#define PL011_UARTIBRD_BAUD_DIVINT_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define PL011_UARTIBRD_BAUD_DIVINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + uint32_t uartfbrd; +#define PL011_UARTFBRD_BAUD_DIVFRAC(val) BSP_FLD32(val, 0, 5) +#define PL011_UARTFBRD_BAUD_DIVFRAC_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define PL011_UARTFBRD_BAUD_DIVFRAC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t uartlcr_h; +#define PL011_UARTLCR_H_SPS BSP_BIT32(7) +#define PL011_UARTLCR_H_WLEN(val) BSP_FLD32(val, 5, 6) +#define PL011_UARTLCR_H_WLEN_GET(reg) BSP_FLD32GET(reg, 5, 6) +#define PL011_UARTLCR_H_WLEN_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6) +#define PL011_UARTLCR_H_WLEN_5 0x00U +#define PL011_UARTLCR_H_WLEN_6 0x01U +#define PL011_UARTLCR_H_WLEN_7 0x02U +#define PL011_UARTLCR_H_WLEN_8 0x03U +#define PL011_UARTLCR_H_FEN BSP_BIT32(4) +#define PL011_UARTLCR_H_STP2 BSP_BIT32(3) +#define PL011_UARTLCR_H_EPS BSP_BIT32(2) +#define PL011_UARTLCR_H_PEN BSP_BIT32(1) +#define PL011_UARTLCR_H_BRK BSP_BIT32(0) + uint32_t uartcr; +#define PL011_UARTCR_CTSEN BSP_BIT32(15) +#define PL011_UARTCR_RTSEN BSP_BIT32(14) +#define PL011_UARTCR_OUT2 BSP_BIT32(13) +#define PL011_UARTCR_OUT1 BSP_BIT32(12) +#define PL011_UARTCR_RTS BSP_BIT32(11) +#define PL011_UARTCR_DTR BSP_BIT32(10) +#define PL011_UARTCR_RXE BSP_BIT32(9) +#define PL011_UARTCR_TXE BSP_BIT32(8) +#define PL011_UARTCR_LBE BSP_BIT32(7) +#define PL011_UARTCR_SIRLP BSP_BIT32(3) +#define PL011_UARTCR_SIREN BSP_BIT32(2) +#define PL011_UARTCR_UARTEN BSP_BIT32(1) + uint32_t uartifls; +#define PL011_UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5) +#define PL011_UARTIFLS_RXIFLSEL_GET(reg) BSP_FLD32GET(reg, 3, 5) +#define PL011_UARTIFLS_RXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) +#define PL011_UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2) +#define PL011_UARTIFLS_TXIFLSEL_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define PL011_UARTIFLS_TXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + uint32_t uartimsc; + uint32_t uartris; + uint32_t uartmis; + uint32_t uarticr; +#define PL011_UARTI_OEI BSP_BIT32(10) +#define PL011_UARTI_BEI BSP_BIT32(9) +#define PL011_UARTI_PEI BSP_BIT32(8) +#define PL011_UARTI_FEI BSP_BIT32(7) +#define PL011_UARTI_RTI BSP_BIT32(6) +#define PL011_UARTI_TXI BSP_BIT32(5) +#define PL011_UARTI_RXI BSP_BIT32(4) +#define PL011_UARTI_DSRMI BSP_BIT32(3) +#define PL011_UARTI_DCDMI BSP_BIT32(2) +#define PL011_UARTI_CTSMI BSP_BIT32(1) +#define PL011_UARTI_RIMI BSP_BIT32(0) + uint32_t uartdmacr; +#define PL011_UARTDMACR_DMAONERR BSP_BIT32(2) +#define PL011_UARTDMACR_TXDMAE BSP_BIT32(1) +#define PL011_UARTDMACR_RXDMAE BSP_BIT32(0) + uint32_t reserved_4c[997]; + uint32_t uartperiphid0; + uint32_t uartperiphid1; + uint32_t uartperiphid2; + uint32_t uartperiphid3; + uint32_t uartpcellid0; + uint32_t uartpcellid1; + uint32_t uartpcellid2; + uint32_t uartpcellid3; +} pl011; + +#endif /* LIBBSP_ARM_SHARED_ARM_PL011_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-pl011.h b/bsps/arm/include/bsp/arm-pl011.h new file mode 100644 index 0000000000..08189c477c --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl011.h @@ -0,0 +1,51 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL011 Support Package + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL011_H +#define LIBBSP_ARM_SHARED_ARM_PL011_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + rtems_termios_device_context base; + volatile pl011 *regs; + rtems_vector_number irq; + uint32_t initial_baud; +} arm_pl011_context; + +bool arm_pl011_probe(rtems_termios_device_context *base); + +void arm_pl011_write_polled(rtems_termios_device_context *base, char c); + +extern const rtems_termios_device_handler arm_pl011_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_PL011_H */ diff --git a/bsps/arm/include/bsp/arm-pl050-regs.h b/bsps/arm/include/bsp/arm-pl050-regs.h new file mode 100644 index 0000000000..f90aeb6cf9 --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl050-regs.h @@ -0,0 +1,57 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL050 Register Definitions + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL050_REGS_H +#define LIBBSP_ARM_SHARED_ARM_PL050_REGS_H + +#include + +typedef struct { + uint32_t kmicr; +#define PL050_KMICR_KMITYPE BSP_BIT32(5) +#define PL050_KMICR_KMIRXINTREN BSP_BIT32(4) +#define PL050_KMICR_KMITXINTREN BSP_BIT32(3) +#define PL050_KMICR_KMIEN BSP_BIT32(2) +#define PL050_KMICR_FKMID BSP_BIT32(1) +#define PL050_KMICR_FKMIC BSP_BIT32(0) + uint32_t kmistat; +#define PL050_KMISTAT_TXEMPTY BSP_BIT32(6) +#define PL050_KMISTAT_TXBUSY BSP_BIT32(5) +#define PL050_KMISTAT_RXFULL BSP_BIT32(4) +#define PL050_KMISTAT_RXBUSY BSP_BIT32(3) +#define PL050_KMISTAT_RXPARITY BSP_BIT32(2) +#define PL050_KMISTAT_KMIC BSP_BIT32(1) +#define PL050_KMISTAT_KMID BSP_BIT32(0) + uint32_t kmidata; +#define PL050_KMIDATA_KMIDATA(val) BSP_FLD32(val, 0, 7) +#define PL050_KMIDATA_KMIDATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define PL050_KMIDATA_KMIDATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t kmiclkdiv; +#define PL050_KMICLKDIV_KMICLKDIV(val) BSP_FLD32(val, 0, 3) +#define PL050_KMICLKDIV_KMICLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define PL050_KMICLKDIV_KMICLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t kmiir; +#define PL050_KMIIR_KMITXINTR BSP_BIT32(1) +#define PL050_KMIIR_KMIRXINTR BSP_BIT32(0) +} pl050; + +#endif /* LIBBSP_ARM_SHARED_ARM_PL050_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-pl050.h b/bsps/arm/include/bsp/arm-pl050.h new file mode 100644 index 0000000000..af4e246124 --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl050.h @@ -0,0 +1,47 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL050 Support + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL050_H +#define LIBBSP_ARM_SHARED_ARM_PL050_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + rtems_termios_device_context base; + volatile pl050 *regs; + rtems_vector_number irq; + uint32_t initial_baud; +} arm_pl050_context; + +extern const rtems_termios_device_handler arm_pl050_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_PL050_H */ diff --git a/bsps/arm/include/bsp/arm-pl111-fb.h b/bsps/arm/include/bsp/arm-pl111-fb.h new file mode 100644 index 0000000000..0c8c6231e1 --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl111-fb.h @@ -0,0 +1,44 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL111 FB Support + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL111_FB_H +#define LIBBSP_ARM_SHARED_ARM_PL111_FB_H + +#include + +typedef struct pl111_fb_config { + volatile pl111 *regs; + uint32_t timing0; + uint32_t timing1; + uint32_t timing2; + uint32_t timing3; + uint32_t control; + uint32_t power_delay_in_us; + void (*set_up)(const struct pl111_fb_config *cfg); + void (*pins_set_up)(const struct pl111_fb_config *cfg); + void (*pins_tear_down)(const struct pl111_fb_config *cfg); + void (*tear_down)(const struct pl111_fb_config *cfg); +} pl111_fb_config; + +const pl111_fb_config *arm_pl111_fb_get_config(void); + +#endif /* LIBBSP_ARM_SHARED_ARM_PL111_FB_H */ diff --git a/bsps/arm/include/bsp/arm-pl111-regs.h b/bsps/arm/include/bsp/arm-pl111-regs.h new file mode 100644 index 0000000000..ed27ba41a0 --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl111-regs.h @@ -0,0 +1,184 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL111 Register definitions + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL111_REGS_H +#define LIBBSP_ARM_SHARED_ARM_PL111_REGS_H + +#include + +typedef struct { + uint32_t timing0; +#define PL111_LCD_TIMING0_PPL(val) BSP_FLD32(val, 2, 7) +#define PL111_LCD_TIMING0_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7) +#define PL111_LCD_TIMING0_PPL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 7) +#define PL111_LCD_TIMING0_HSW(val) BSP_FLD32(val, 8, 15) +#define PL111_LCD_TIMING0_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define PL111_LCD_TIMING0_HSW_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define PL111_LCD_TIMING0_HFP(val) BSP_FLD32(val, 16, 23) +#define PL111_LCD_TIMING0_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define PL111_LCD_TIMING0_HFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) +#define PL111_LCD_TIMING0_HBP(val) BSP_FLD32(val, 24, 31) +#define PL111_LCD_TIMING0_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define PL111_LCD_TIMING0_HBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) + uint32_t timing1; +#define PL111_LCD_TIMING1_LPP(val) BSP_FLD32(val, 0, 9) +#define PL111_LCD_TIMING1_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define PL111_LCD_TIMING1_LPP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) +#define PL111_LCD_TIMING1_VSW(val) BSP_FLD32(val, 10, 15) +#define PL111_LCD_TIMING1_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15) +#define PL111_LCD_TIMING1_VSW_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15) +#define PL111_LCD_TIMING1_VFP(val) BSP_FLD32(val, 16, 23) +#define PL111_LCD_TIMING1_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define PL111_LCD_TIMING1_VFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) +#define PL111_LCD_TIMING1_VBP(val) BSP_FLD32(val, 24, 31) +#define PL111_LCD_TIMING1_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define PL111_LCD_TIMING1_VBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) + uint32_t timing2; +#define PL111_LCD_TIMING2_PCD_LO(val) BSP_FLD32(val, 0, 4) +#define PL111_LCD_TIMING2_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define PL111_LCD_TIMING2_PCD_LO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define PL111_LCD_TIMING2_CLKSEL BSP_BIT32(5) +#define PL111_LCD_TIMING2_ACB(val) BSP_FLD32(val, 6, 10) +#define PL111_LCD_TIMING2_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10) +#define PL111_LCD_TIMING2_ACB_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10) +#define PL111_LCD_TIMING2_IVS BSP_BIT32(11) +#define PL111_LCD_TIMING2_IHS BSP_BIT32(12) +#define PL111_LCD_TIMING2_IPC BSP_BIT32(13) +#define PL111_LCD_TIMING2_IOE BSP_BIT32(14) +#define PL111_LCD_TIMING2_CPL(val) BSP_FLD32(val, 16, 25) +#define PL111_LCD_TIMING2_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25) +#define PL111_LCD_TIMING2_CPL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25) +#define PL111_LCD_TIMING2_BCD BSP_BIT32(26) +#define PL111_LCD_TIMING2_PCD_HI(val) BSP_FLD32(val, 27, 31) +#define PL111_LCD_TIMING2_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31) +#define PL111_LCD_TIMING2_PCD_HI_SET(reg, val) BSP_FLD32SET(reg, val, 27, 31) + uint32_t timing3; +#define PL111_LCD_TIMING3_LED(val) BSP_FLD32(val, 0, 6) +#define PL111_LCD_TIMING3_LED_GET(reg) BSP_FLD32GET(reg, 0, 6) +#define PL111_LCD_TIMING3_LED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) +#define PL111_LCD_TIMING3_LEE BSP_BIT32(16) + uint32_t upbase; + uint32_t lpbase; + uint32_t control; +#define PL111_LCD_CONTROL_LCD_EN BSP_BIT32(0) +#define PL111_LCD_CONTROL_LCD_BPP(val) BSP_FLD32(val, 1, 3) +#define PL111_LCD_CONTROL_LCD_BPP_GET(reg) BSP_FLD32GET(reg, 1, 3) +#define PL111_LCD_CONTROL_LCD_BPP_SET(reg, val) BSP_FLD32SET(reg, val, 1, 3) +#define PL111_LCD_CONTROL_LCD_BPP_1 0x00U +#define PL111_LCD_CONTROL_LCD_BPP_2 0x01U +#define PL111_LCD_CONTROL_LCD_BPP_4 0x02U +#define PL111_LCD_CONTROL_LCD_BPP_8 0x03U +#define PL111_LCD_CONTROL_LCD_BPP_16 0x04U +#define PL111_LCD_CONTROL_LCD_BPP_24 0x05U +#define PL111_LCD_CONTROL_LCD_BPP_16 0x06U +#define PL111_LCD_CONTROL_LCD_BPP_12 0x07U +#define PL111_LCD_CONTROL_LCD_BW BSP_BIT32(4) +#define PL111_LCD_CONTROL_LCD_TFT BSP_BIT32(5) +#define PL111_LCD_CONTROL_LCD_MONO8 BSP_BIT32(6) +#define PL111_LCD_CONTROL_LCD_DUAL BSP_BIT32(7) +#define PL111_LCD_CONTROL_BGR BSP_BIT32(8) +#define PL111_LCD_CONTROL_BEBO BSP_BIT32(9) +#define PL111_LCD_CONTROL_BEPO BSP_BIT32(10) +#define PL111_LCD_CONTROL_LCD_PWR BSP_BIT32(11) +#define PL111_LCD_CONTROL_LCD_V_COMP(val) BSP_FLD32(val, 12, 13) +#define PL111_LCD_CONTROL_LCD_V_COMP_GET(reg) BSP_FLD32GET(reg, 12, 13) +#define PL111_LCD_CONTROL_LCD_V_COMP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13) +#define PL111_LCD_CONTROL_WATERMARK BSP_BIT32(16) + uint32_t imsc; + uint32_t ris; + uint32_t mis; + uint32_t icr; +#define PL111_LCD_I_FUF BSP_BIT32(1) +#define PL111_LCD_I_LNBU BSP_BIT32(2) +#define PL111_LCD_I_VCOMP BSP_BIT32(3) +#define PL111_LCD_I_MBERROR BSP_BIT32(4) + uint32_t upcurr; + uint32_t lpcurr; + uint32_t reserved_34[115]; + uint16_t pal[256]; +#define PL111_LCD_PAL_R(val) BSP_FLD16(val, 0, 4) +#define PL111_LCD_PAL_R_GET(reg) BSP_FLD16GET(reg, 0, 4) +#define PL111_LCD_PAL_R_SET(reg, val) BSP_FLD16SET(reg, val, 0, 4) +#define PL111_LCD_PAL_G(val) BSP_FLD16(val, 5, 9) +#define PL111_LCD_PAL_G_GET(reg) BSP_FLD16GET(reg, 5, 9) +#define PL111_LCD_PAL_G_SET(reg, val) BSP_FLD16SET(reg, val, 5, 9) +#define PL111_LCD_PAL_B(val) BSP_FLD16(val, 10, 14) +#define PL111_LCD_PAL_B_GET(reg) BSP_FLD16GET(reg, 10, 14) +#define PL111_LCD_PAL_B_SET(reg, val) BSP_FLD16SET(reg, val, 10, 14) +#define PL111_LCD_PAL_I BSP_BIT16(15) +} pl111_lcd; + +typedef struct { + uint8_t image[1024]; + uint32_t ctrl; +#define PL111_CRSR_CTRL_ON BSP_BIT32(0) +#define PL111_CRSR_CTRL_NUMBER(val) BSP_FLD32(val, 4, 5) +#define PL111_CRSR_CTRL_NUMBER_GET(reg) BSP_FLD32GET(reg, 4, 5) +#define PL111_CRSR_CTRL_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5) + uint32_t config; +#define PL111_CRSR_CONFIG_SIZE BSP_BIT32(0) +#define PL111_CRSR_CONFIG_FRAME_SYNC BSP_BIT32(1) + uint32_t palette0; + uint32_t palette1; +#define PL111_CRSR_PALETTE_RED(val) BSP_FLD32(val, 0, 7) +#define PL111_CRSR_PALETTE_RED_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define PL111_CRSR_PALETTE_RED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) +#define PL111_CRSR_PALETTE_GREEN(val) BSP_FLD32(val, 8, 15) +#define PL111_CRSR_PALETTE_GREEN_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define PL111_CRSR_PALETTE_GREEN_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define PL111_CRSR_PALETTE_BLUE(val) BSP_FLD32(val, 16, 23) +#define PL111_CRSR_PALETTE_BLUE_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define PL111_CRSR_PALETTE_BLUE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) + uint32_t xy; +#define PL111_CRSR_XY_X(val) BSP_FLD32(val, 0, 9) +#define PL111_CRSR_XY_X_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define PL111_CRSR_XY_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) +#define PL111_CRSR_XY_X_EXP(val) BSP_FLD32(val, 10, 11) +#define PL111_CRSR_XY_X_EXP_GET(reg) BSP_FLD32GET(reg, 10, 11) +#define PL111_CRSR_XY_X_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 10, 11) +#define PL111_CRSR_XY_Y(val) BSP_FLD32(val, 16, 25) +#define PL111_CRSR_XY_Y_GET(reg) BSP_FLD32GET(reg, 16, 25) +#define PL111_CRSR_XY_Y_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25) +#define PL111_CRSR_XY_Y_EXP(val) BSP_FLD32(val, 25, 27) +#define PL111_CRSR_XY_Y_EXP_GET(reg) BSP_FLD32GET(reg, 25, 27) +#define PL111_CRSR_XY_Y_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 25, 27) + uint32_t clip; +#define PL111_CRSR_CLIP_X(val) BSP_FLD32(val, 0, 5) +#define PL111_CRSR_CLIP_X_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define PL111_CRSR_CLIP_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) +#define PL111_CRSR_CLIP_Y(val) BSP_FLD32(val, 8, 13) +#define PL111_CRSR_CLIP_Y_GET(reg) BSP_FLD32GET(reg, 8, 13) +#define PL111_CRSR_CLIP_Y_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) + uint32_t imsc; + uint32_t icr; + uint32_t ris; + uint32_t mis; +#define PL111_CRSR_I_CRSR BSP_BIT32(0) +} pl111_crsr; + +typedef struct { + pl111_lcd lcd; + uint32_t reserved_400[256]; + pl111_crsr crsr; +} pl111; + +#endif /* LIBBSP_ARM_SHARED_ARM_PL111_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-release-id.h b/bsps/arm/include/bsp/arm-release-id.h new file mode 100644 index 0000000000..e06be006da --- /dev/null +++ b/bsps/arm/include/bsp/arm-release-id.h @@ -0,0 +1,152 @@ +/** + * @file arm-release-id.h + * + * @ingroup arm_shared + * + * @brief Create #defines for release IDs + */ + +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef ARM_RELEASE_ID_H_ +#define ARM_RELEASE_ID_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* #define the IDs which identify a release. This must be done + * prior to #including bsp.h */ +#define ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( release_no, patch_level ) \ + ( ( ( ( release_no ) & 0xFFFF ) << 16 ) + ( ( patch_level ) & 0xFFFF ) ) + +typedef enum { + ARM_RELEASE_ID_R0_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 0 ), + ARM_RELEASE_ID_R0_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 1 ), + ARM_RELEASE_ID_R0_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 2 ), + ARM_RELEASE_ID_R0_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 3 ), + ARM_RELEASE_ID_R0_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 4 ), + ARM_RELEASE_ID_R0_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 5 ), + ARM_RELEASE_ID_R0_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 6 ), + ARM_RELEASE_ID_R0_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 7 ), + ARM_RELEASE_ID_R0_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 8 ), + ARM_RELEASE_ID_R0_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 9 ), + ARM_RELEASE_ID_R0_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 10 ), + ARM_RELEASE_ID_R1_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 0 ), + ARM_RELEASE_ID_R1_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 1 ), + ARM_RELEASE_ID_R1_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 2 ), + ARM_RELEASE_ID_R1_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 3 ), + ARM_RELEASE_ID_R1_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 4 ), + ARM_RELEASE_ID_R1_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 5 ), + ARM_RELEASE_ID_R1_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 6 ), + ARM_RELEASE_ID_R1_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 7 ), + ARM_RELEASE_ID_R1_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 8 ), + ARM_RELEASE_ID_R1_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 9 ), + ARM_RELEASE_ID_R1_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 10 ), + ARM_RELEASE_ID_R2_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 0 ), + ARM_RELEASE_ID_R2_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 1 ), + ARM_RELEASE_ID_R2_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 2 ), + ARM_RELEASE_ID_R2_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 3 ), + ARM_RELEASE_ID_R2_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 4 ), + ARM_RELEASE_ID_R2_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 5 ), + ARM_RELEASE_ID_R2_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 6 ), + ARM_RELEASE_ID_R2_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 7 ), + ARM_RELEASE_ID_R2_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 8 ), + ARM_RELEASE_ID_R2_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 9 ), + ARM_RELEASE_ID_R2_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 10 ), + ARM_RELEASE_ID_R3_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 0 ), + ARM_RELEASE_ID_R3_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 1 ), + ARM_RELEASE_ID_R3_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 2 ), + ARM_RELEASE_ID_R3_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 3 ), + ARM_RELEASE_ID_R3_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 4 ), + ARM_RELEASE_ID_R3_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 5 ), + ARM_RELEASE_ID_R3_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 6 ), + ARM_RELEASE_ID_R3_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 7 ), + ARM_RELEASE_ID_R3_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 8 ), + ARM_RELEASE_ID_R3_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 9 ), + ARM_RELEASE_ID_R3_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 10 ), + ARM_RELEASE_ID_R4_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 0 ), + ARM_RELEASE_ID_R4_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 1 ), + ARM_RELEASE_ID_R4_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 2 ), + ARM_RELEASE_ID_R4_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 3 ), + ARM_RELEASE_ID_R4_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 4 ), + ARM_RELEASE_ID_R4_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 5 ), + ARM_RELEASE_ID_R4_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 6 ), + ARM_RELEASE_ID_R4_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 7 ), + ARM_RELEASE_ID_R4_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 8 ), + ARM_RELEASE_ID_R4_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 9 ), + ARM_RELEASE_ID_R4_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 10 ), + ARM_RELEASE_ID_R5_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 0 ), + ARM_RELEASE_ID_R5_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 1 ), + ARM_RELEASE_ID_R5_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 2 ), + ARM_RELEASE_ID_R5_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 3 ), + ARM_RELEASE_ID_R5_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 4 ), + ARM_RELEASE_ID_R5_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 5 ), + ARM_RELEASE_ID_R5_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 6 ), + ARM_RELEASE_ID_R5_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 7 ), + ARM_RELEASE_ID_R5_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 8 ), + ARM_RELEASE_ID_R5_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 9 ), + ARM_RELEASE_ID_R5_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 10 ), + ARM_RELEASE_ID_R6_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 0 ), + ARM_RELEASE_ID_R6_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 1 ), + ARM_RELEASE_ID_R6_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 2 ), + ARM_RELEASE_ID_R6_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 3 ), + ARM_RELEASE_ID_R6_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 4 ), + ARM_RELEASE_ID_R6_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 5 ), + ARM_RELEASE_ID_R6_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 6 ), + ARM_RELEASE_ID_R6_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 7 ), + ARM_RELEASE_ID_R6_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 8 ), + ARM_RELEASE_ID_R6_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 9 ), + ARM_RELEASE_ID_R6_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 10 ), + ARM_RELEASE_ID_R7_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 0 ), + ARM_RELEASE_ID_R7_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 1 ), + ARM_RELEASE_ID_R7_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 2 ), + ARM_RELEASE_ID_R7_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 3 ), + ARM_RELEASE_ID_R7_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 4 ), + ARM_RELEASE_ID_R7_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 5 ), + ARM_RELEASE_ID_R7_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 6 ), + ARM_RELEASE_ID_R7_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 7 ), + ARM_RELEASE_ID_R7_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 8 ), + ARM_RELEASE_ID_R7_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 9 ), + ARM_RELEASE_ID_R7_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 10 ), + ARM_RELEASE_ID_R8_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 0 ), + ARM_RELEASE_ID_R8_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 1 ), + ARM_RELEASE_ID_R8_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 2 ), + ARM_RELEASE_ID_R8_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 3 ), + ARM_RELEASE_ID_R8_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 4 ), + ARM_RELEASE_ID_R8_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 5 ), + ARM_RELEASE_ID_R8_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 6 ), + ARM_RELEASE_ID_R8_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 7 ), + ARM_RELEASE_ID_R8_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 8 ), + ARM_RELEASE_ID_R8_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 9 ), + ARM_RELEASE_ID_R8_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 10 ), + ARM_RELEASE_ID_R9_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 0 ), + ARM_RELEASE_ID_R9_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 1 ), + ARM_RELEASE_ID_R9_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 2 ), + ARM_RELEASE_ID_R9_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 3 ), + ARM_RELEASE_ID_R9_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 4 ), + ARM_RELEASE_ID_R9_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 5 ), + ARM_RELEASE_ID_R9_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 6 ), + ARM_RELEASE_ID_R9_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 7 ), + ARM_RELEASE_ID_R9_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 8 ), + ARM_RELEASE_ID_R9_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 9 ), + ARM_RELEASE_ID_R9_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 10 ) +} arm_release_id; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ARM_RELEASE_ID_H_ */ \ No newline at end of file diff --git a/bsps/arm/include/bsp/armv7m-irq.h b/bsps/arm/include/bsp/armv7m-irq.h new file mode 100644 index 0000000000..f91ab362e7 --- /dev/null +++ b/bsps/arm/include/bsp/armv7m-irq.h @@ -0,0 +1,36 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARMV7M Support + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARMV7M_IRQ_H +#define LIBBSP_ARM_SHARED_ARMV7M_IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +void _ARMV7M_NVIC_Interrupt_dispatch(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARMV7M_IRQ_H */ diff --git a/bsps/arm/include/bsp/linker-symbols.h b/bsps/arm/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..1a996f51f2 --- /dev/null +++ b/bsps/arm/include/bsp/linker-symbols.h @@ -0,0 +1,167 @@ +/** + * @file + * + * @ingroup arm_linker + * + * @brief Symbols defined in linker command base file. + */ + +/* + * Copyright (c) 2008, 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_linker Linker Support + * + * @ingroup arm_shared + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM + #define LINKER_SYMBOL(sym) extern char sym []; +#else + #define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_stack_irq_begin) +LINKER_SYMBOL(bsp_stack_irq_end) +LINKER_SYMBOL(bsp_stack_irq_size) + +LINKER_SYMBOL(bsp_stack_fiq_begin) +LINKER_SYMBOL(bsp_stack_fiq_end) +LINKER_SYMBOL(bsp_stack_irq_size) + +LINKER_SYMBOL(bsp_stack_abt_begin) +LINKER_SYMBOL(bsp_stack_abt_end) +LINKER_SYMBOL(bsp_stack_abt_size) + +LINKER_SYMBOL(bsp_stack_und_begin) +LINKER_SYMBOL(bsp_stack_und_end) +LINKER_SYMBOL(bsp_stack_und_size) + +LINKER_SYMBOL(bsp_stack_hyp_begin) +LINKER_SYMBOL(bsp_stack_hyp_end) +LINKER_SYMBOL(bsp_stack_hyp_size) + +LINKER_SYMBOL(bsp_stack_svc_begin) +LINKER_SYMBOL(bsp_stack_svc_end) +LINKER_SYMBOL(bsp_stack_svc_size) + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_vector_begin) +LINKER_SYMBOL(bsp_section_vector_end) +LINKER_SYMBOL(bsp_section_vector_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_fast_text_begin) +LINKER_SYMBOL(bsp_section_fast_text_end) +LINKER_SYMBOL(bsp_section_fast_text_size) +LINKER_SYMBOL(bsp_section_fast_text_load_begin) +LINKER_SYMBOL(bsp_section_fast_text_load_end) + +LINKER_SYMBOL(bsp_section_fast_data_begin) +LINKER_SYMBOL(bsp_section_fast_data_end) +LINKER_SYMBOL(bsp_section_fast_data_size) +LINKER_SYMBOL(bsp_section_fast_data_load_begin) +LINKER_SYMBOL(bsp_section_fast_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_section_nocache_begin) +LINKER_SYMBOL(bsp_section_nocache_end) +LINKER_SYMBOL(bsp_section_nocache_size) +LINKER_SYMBOL(bsp_section_nocache_load_begin) +LINKER_SYMBOL(bsp_section_nocache_load_end) + +LINKER_SYMBOL(bsp_section_nocachenoload_begin) +LINKER_SYMBOL(bsp_section_nocachenoload_end) +LINKER_SYMBOL(bsp_section_nocachenoload_size) + +LINKER_SYMBOL(bsp_section_nocacheheap_begin) +LINKER_SYMBOL(bsp_section_nocacheheap_end) +LINKER_SYMBOL(bsp_section_nocacheheap_size) + +LINKER_SYMBOL(bsp_vector_table_begin) +LINKER_SYMBOL(bsp_vector_table_end) +LINKER_SYMBOL(bsp_vector_table_size) + +LINKER_SYMBOL(bsp_start_vector_table_begin) +LINKER_SYMBOL(bsp_start_vector_table_end) +LINKER_SYMBOL(bsp_start_vector_table_size) + +LINKER_SYMBOL(bsp_translation_table_base) +LINKER_SYMBOL(bsp_translation_table_end) + +#define BSP_FAST_TEXT_SECTION __attribute__((section(".bsp_fast_text"))) + +#define BSP_FAST_DATA_SECTION __attribute__((section(".bsp_fast_data"))) + +#define BSP_NOCACHE_SECTION __attribute__((section(".bsp_nocache"))) + +#define BSP_NOCACHE_SUBSECTION(subsection) \ + __attribute__((section(".bsp_nocache." # subsection))) + +#define BSP_NOCACHENOLOAD_SECTION __attribute__((section(".bsp_noload_nocache"))) + +#define BSP_NOCACHENOLOAD_SUBSECTION(subsection) \ + __attribute__((section(".bsp_noload_nocache." # subsection))) + +LINKER_SYMBOL(bsp_processor_count) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/arm/include/bsp/lpc-dma.h b/bsps/arm/include/bsp/lpc-dma.h new file mode 100644 index 0000000000..45d567b36c --- /dev/null +++ b/bsps/arm/include/bsp/lpc-dma.h @@ -0,0 +1,221 @@ +/** + * @file + * + * @ingroup lpc_dma + * + * @brief DMA support API. + */ + +/* + * Copyright (c) 2010-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_DMA_H +#define LIBBSP_ARM_SHARED_LPC_DMA_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_dma DMA Support + * + * @ingroup arm_lpc24xx + * @ingroup arm_lpc32xx + * + * @brief DMA support. + * + * @{ + */ + +/** + * @brief DMA descriptor item. + */ +typedef struct { + uint32_t src; + uint32_t dest; + uint32_t lli; + uint32_t ctrl; +} lpc_dma_descriptor; + +/** + * @brief DMA channel block. + */ +typedef struct { + lpc_dma_descriptor desc; + uint32_t cfg; + uint32_t reserved [3]; +} lpc_dma_channel; + +/** + * @brief DMA control block. + */ +typedef struct { + uint32_t int_stat; + uint32_t int_tc_stat; + uint32_t int_tc_clear; + uint32_t int_err_stat; + uint32_t int_err_clear; + uint32_t raw_tc_stat; + uint32_t raw_err_stat; + uint32_t enabled_channels; + uint32_t soft_burst_req; + uint32_t soft_single_req; + uint32_t soft_last_burst_req; + uint32_t soft_last_single_req; + uint32_t cfg; + uint32_t sync; + uint32_t reserved [50]; + lpc_dma_channel channels [LPC_DMA_CHANNEL_COUNT]; +} lpc_dma; + +/** + * @name DMA Configuration Register + * + * @{ + */ + +#define DMA_CFG_E BSP_BIT32(0) +#define DMA_CFG_M_0 BSP_BIT32(1) +#define DMA_CFG_M_1 BSP_BIT32(2) + +/** @} */ + +/** + * @name DMA Channel Control Register + * + * @{ + */ + +#define DMA_CH_CTRL_TSZ(val) BSP_FLD32(val, 0, 11) +#define DMA_CH_CTRL_TSZ_MAX DMA_CH_CTRL_TSZ(0xfff) + +#define DMA_CH_CTRL_SB(val) BSP_FLD32(val, 12, 14) +#define DMA_CH_CTRL_SB_1 DMA_CH_CTRL_SB(0) +#define DMA_CH_CTRL_SB_4 DMA_CH_CTRL_SB(1) +#define DMA_CH_CTRL_SB_8 DMA_CH_CTRL_SB(2) +#define DMA_CH_CTRL_SB_16 DMA_CH_CTRL_SB(3) +#define DMA_CH_CTRL_SB_32 DMA_CH_CTRL_SB(4) +#define DMA_CH_CTRL_SB_64 DMA_CH_CTRL_SB(5) +#define DMA_CH_CTRL_SB_128 DMA_CH_CTRL_SB(6) +#define DMA_CH_CTRL_SB_256 DMA_CH_CTRL_SB(7) + +#define DMA_CH_CTRL_DB(val) BSP_FLD32(val, 15, 17) +#define DMA_CH_CTRL_DB_1 DMA_CH_CTRL_DB(0) +#define DMA_CH_CTRL_DB_4 DMA_CH_CTRL_DB(1) +#define DMA_CH_CTRL_DB_8 DMA_CH_CTRL_DB(2) +#define DMA_CH_CTRL_DB_16 DMA_CH_CTRL_DB(3) +#define DMA_CH_CTRL_DB_32 DMA_CH_CTRL_DB(4) +#define DMA_CH_CTRL_DB_64 DMA_CH_CTRL_DB(5) +#define DMA_CH_CTRL_DB_128 DMA_CH_CTRL_DB(6) +#define DMA_CH_CTRL_DB_256 DMA_CH_CTRL_DB(7) + +#define DMA_CH_CTRL_SW(val) BSP_FLD32(val, 18, 20) +#define DMA_CH_CTRL_SW_8 DMA_CH_CTRL_SW(0) +#define DMA_CH_CTRL_SW_16 DMA_CH_CTRL_SW(1) +#define DMA_CH_CTRL_SW_32 DMA_CH_CTRL_SW(2) + +#define DMA_CH_CTRL_DW(val) BSP_FLD32(val, 21, 23) +#define DMA_CH_CTRL_DW_8 DMA_CH_CTRL_DW(0) +#define DMA_CH_CTRL_DW_16 DMA_CH_CTRL_DW(1) +#define DMA_CH_CTRL_DW_32 DMA_CH_CTRL_DW(2) + +#define DMA_CH_CTRL_S BSP_BIT32(24) +#define DMA_CH_CTRL_D BSP_BIT32(25) +#define DMA_CH_CTRL_SI BSP_BIT32(26) +#define DMA_CH_CTRL_DI BSP_BIT32(27) +#define DMA_CH_CTRL_PROT(val) BSP_FLD32(val, 28, 30) +#define DMA_CH_CTRL_I BSP_BIT32(31) + +/** @} */ + +/** + * @name DMA Channel Configuration Register + * + * @{ + */ + +#define DMA_CH_CFG_E BSP_BIT32(0) +#define DMA_CH_CFG_SPER(val) BSP_FLD32(val, 1, 5) +#define DMA_CH_CFG_DPER(val) BSP_FLD32(val, 6, 10) + +#define DMA_CH_CFG_FLOW(val) BSP_FLD32(val, 11, 13) +#define DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA DMA_CH_CFG_FLOW(0) +#define DMA_CH_CFG_FLOW_MEM_TO_PER_DMA DMA_CH_CFG_FLOW(1) +#define DMA_CH_CFG_FLOW_PER_TO_MEM_DMA DMA_CH_CFG_FLOW(2) +#define DMA_CH_CFG_FLOW_PER_TO_PER_DMA DMA_CH_CFG_FLOW(3) +#define DMA_CH_CFG_FLOW_PER_TO_PER_DEST DMA_CH_CFG_FLOW(4) +#define DMA_CH_CFG_FLOW_MEM_TO_PER_PER DMA_CH_CFG_FLOW(5) +#define DMA_CH_CFG_FLOW_PER_TO_MEM_PER DMA_CH_CFG_FLOW(6) +#define DMA_CH_CFG_FLOW_PER_TO_PER_SRC DMA_CH_CFG_FLOW(7) + +#define DMA_CH_CFG_IE BSP_BIT32(14) +#define DMA_CH_CFG_ITC BSP_BIT32(15) +#define DMA_CH_CFG_L BSP_BIT32(16) +#define DMA_CH_CFG_A BSP_BIT32(17) +#define DMA_CH_CFG_H BSP_BIT32(18) + +/** @} */ + +/** + * @name LPC24XX DMA Peripherals + * + * @{ + */ + +#define LPC24XX_DMA_PER_SSP_0_TX 0 +#define LPC24XX_DMA_PER_SSP_0_RX 1 +#define LPC24XX_DMA_PER_SSP_1_TX 2 +#define LPC24XX_DMA_PER_SSP_1_RX 3 +#define LPC24XX_DMA_PER_SD_MMC 4 +#define LPC24XX_DMA_PER_I2S_CH_0 5 +#define LPC24XX_DMA_PER_I2S_CH_1 6 + +/** @} */ + +/** + * @name LPC32XX DMA Peripherals + * + * @{ + */ + +#define LPC32XX_DMA_PER_I2S_0_CH_0 0 +#define LPC32XX_DMA_PER_I2S_0_CH_1 13 +#define LPC32XX_DMA_PER_I2S_1_CH_0 2 +#define LPC32XX_DMA_PER_I2S_1_CH_1 10 +#define LPC32XX_DMA_PER_NAND_0 1 +#define LPC32XX_DMA_PER_NAND_1 12 +#define LPC32XX_DMA_PER_SD_MMC 4 +#define LPC32XX_DMA_PER_SSP_0_RX 14 +#define LPC32XX_DMA_PER_SSP_0_TX 15 +#define LPC32XX_DMA_PER_SSP_1_RX 3 +#define LPC32XX_DMA_PER_SSP_1_TX 11 +#define LPC32XX_DMA_PER_UART_1_RX 6 +#define LPC32XX_DMA_PER_UART_1_TX 5 +#define LPC32XX_DMA_PER_UART_2_RX 8 +#define LPC32XX_DMA_PER_UART_2_TX 7 +#define LPC32XX_DMA_PER_UART_7_RX 10 +#define LPC32XX_DMA_PER_UART_7_TX 9 + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_DMA_H */ diff --git a/bsps/arm/include/bsp/lpc-emc.h b/bsps/arm/include/bsp/lpc-emc.h new file mode 100644 index 0000000000..31cb4241c8 --- /dev/null +++ b/bsps/arm/include/bsp/lpc-emc.h @@ -0,0 +1,170 @@ +/** + * @file + * + * @ingroup lpc_emc + * + * @brief EMC support API. + */ + +/* + * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_EMC_H +#define LIBBSP_ARM_SHARED_LPC_EMC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc_emc EMC Support + * + * @ingroup arm_lpc24xx + * @ingroup arm_lpc32xx + * + * @brief EMC Support + * + * @{ + */ + +/** + * @name EMC Control Register (EMCControl) + * + * @{ + */ + +#define EMC_CTRL_E BSP_BIT32(0) +#define EMC_CTRL_M BSP_BIT32(0) +#define EMC_CTRL_L BSP_BIT32(2) + +/** @} */ + +/** + * @name EMC Dynamic Memory Control Register (EMCDynamicControl) + * + * @{ + */ + +#define EMC_DYN_CTRL_CE BSP_BIT32(0) +#define EMC_DYN_CTRL_CS BSP_BIT32(1) +#define EMC_DYN_CTRL_SR BSP_BIT32(2) +#define EMC_DYN_CTRL_SRMCC BSP_BIT32(3) +#define EMC_DYN_CTRL_IMCC BSP_BIT32(4) +#define EMC_DYN_CTRL_MCC BSP_BIT32(5) +#define EMC_DYN_CTRL_I_MASK BSP_MSK32(7, 8) +#define EMC_DYN_CTRL_I_NORMAL BSP_FLD32(0x0, 7, 8) +#define EMC_DYN_CTRL_I_MODE BSP_FLD32(0x1, 7, 8) +#define EMC_DYN_CTRL_I_PALL BSP_FLD32(0x2, 7, 8) +#define EMC_DYN_CTRL_I_NOP BSP_FLD32(0x3, 7, 8) +#define EMC_DYN_CTRL_DP BSP_BIT32(13) + +/** @} */ + +/** + * @name EMC Dynamic Memory Read Configuration Register (EMCDynamicReadConfig) + * + * @{ + */ + +#define EMC_DYN_READ_CONFIG_SDR_STRAT(val) BSP_FLD32(val, 0, 1) +#define EMC_DYN_READ_CONFIG_SDR_POL_POS BSP_BIT32(4) +#define EMC_DYN_READ_CONFIG_DDR_STRAT(val) BSP_FLD32(val, 8, 9) +#define EMC_DYN_READ_CONFIG_DDR_POL_POS BSP_BIT32(12) + +/** @} */ + +/** + * @name EMC Dynamic Memory Configuration N Register (EMCDynamicConfigN) + * + * @{ + */ + +#define EMC_DYN_CFG_MD_LPC24XX(val) BSP_FLD32(val, 3, 4) +#define EMC_DYN_CFG_MD_LPC32XX(val) BSP_FLD32(val, 0, 2) +#define EMC_DYN_CFG_AM(val) BSP_FLD32(val, 7, 14) +#define EMC_DYN_CFG_B BSP_BIT32(19) +#define EMC_DYN_CFG_P BSP_BIT32(20) + +/** @} */ + +/** + * @name EMC Dynamic Memory RAS and CAS Delay N Register (EMCDynamicRasCasN) + * + * @{ + */ + +#define EMC_DYN_RASCAS_RAS(val) BSP_FLD32(val, 0, 3) +#define EMC_DYN_RASCAS_CAS(val, half) BSP_FLD32(((val) << 1) | (half), 7, 10) + +/** @} */ + +#define EMC_DYN_CHIP_COUNT 4 + +#define EMC_STATIC_CHIP_COUNT 4 + +typedef struct { + uint32_t config; + uint32_t rascas; + uint32_t reserved_0 [6]; +} lpc_emc_dynamic; + +typedef struct { + uint32_t config; + uint32_t waitwen; + uint32_t waitoen; + uint32_t waitrd; + uint32_t waitpage; + uint32_t waitwr; + uint32_t waitturn; + uint32_t reserved_0 [1]; +} lpc_emc_static; + +typedef struct { + uint32_t control; + uint32_t status; + uint32_t config; + uint32_t reserved_0 [5]; + uint32_t dynamiccontrol; + uint32_t dynamicrefresh; + uint32_t dynamicreadconfig; + uint32_t reserved_1; + uint32_t dynamictrp; + uint32_t dynamictras; + uint32_t dynamictsrex; + uint32_t dynamictapr; + uint32_t dynamictdal; + uint32_t dynamictwr; + uint32_t dynamictrc; + uint32_t dynamictrfc; + uint32_t dynamictxsr; + uint32_t dynamictrrd; + uint32_t dynamictmrd; + uint32_t dynamictcdlr; + uint32_t reserved_3 [8]; + uint32_t staticextendedwait; + uint32_t reserved_4 [31]; + lpc_emc_dynamic dynamic [EMC_DYN_CHIP_COUNT]; + uint32_t reserved_5 [32]; + lpc_emc_static emcstatic [EMC_STATIC_CHIP_COUNT]; +} lpc_emc; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_EMC_H */ diff --git a/bsps/arm/include/bsp/lpc-i2s.h b/bsps/arm/include/bsp/lpc-i2s.h new file mode 100644 index 0000000000..65e951b7d7 --- /dev/null +++ b/bsps/arm/include/bsp/lpc-i2s.h @@ -0,0 +1,132 @@ +/** + * @file + * + * @ingroup lpc_i2s + * + * @brief I2S API. + */ + +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_I2S_H +#define LIBBSP_ARM_SHARED_LPC_I2S_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_i2s I2S Support + * + * @ingroup arm_lpc24xx + * @ingroup arm_lpc32xx + * + * @brief I2S support. + * + * @{ + */ + +/** + * @brief I2S control block. + */ +typedef struct { + uint32_t dao; + uint32_t dai; + uint32_t txfifo; + uint32_t rxfifo; + uint32_t state; + uint32_t dma [2]; + uint32_t irq; + uint32_t txrate; + uint32_t rxrate; +} lpc_i2s; + +/** + * @name I2S Digital Audio Input and Output + * + * @{ + */ + +#define I2S_DAIO_WORDWIDTH(val) BSP_FLD32(val, 0, 1) +#define I2S_DAIO_MONO BSP_BIT32(2) +#define I2S_DAIO_STOP BSP_BIT32(3) +#define I2S_DAIO_RESET BSP_BIT32(4) +#define I2S_DAIO_WS_SEL BSP_BIT32(5) +#define I2S_DAIO_WS_HALFPERIOD(val) BSP_FLD32(val, 6, 14) +#define I2S_DAIO_MUTE BSP_BIT32(15) + +/** @} */ + +/** + * @name I2S Status Feedback + * + * @{ + */ + +#define I2S_STATE_IRQ BSP_BIT32(0) +#define I2S_STATE_DMAREQ_0 BSP_BIT32(1) +#define I2S_STATE_DMAREQ_1 BSP_BIT32(2) +#define I2S_STATE_RX_LEVEL_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define I2S_STATE_TX_LEVEL_GET(reg) BSP_FLD32GET(reg, 16, 19) + +/** @} */ + +/** + * @name I2S DMA Configuration + * + * @{ + */ + +#define I2S_DMA_RX_ENABLE BSP_BIT32(0) +#define I2S_DMA_TX_ENABLE BSP_BIT32(1) +#define I2S_DMA_RX_DEPTH(val) BSP_FLD32(val, 8, 11) +#define I2S_DMA_TX_DEPTH(val) BSP_FLD32(val, 16, 19) + +/** @} */ + +/** + * @name I2S Interrupt Request Control + * + * @{ + */ + +#define I2S_IRQ_RX BSP_BIT32(0) +#define I2S_IRQ_TX BSP_BIT32(1) +#define I2S_IRQ_RX_DEPTH(val) BSP_FLD32(val, 8, 11) +#define I2S_IRQ_TX_DEPTH(val) BSP_FLD32(val, 16, 19) + +/** @} */ + +/** + * @name I2S Transmit and Receive Clock Rate + * + * @{ + */ + +#define LPC24XX_I2S_RATE(val) BSP_FLD32(val, 0, 9) +#define LPC32XX_I2S_RATE_X_DIVIDER(val) BSP_FLD32(val, 0, 7) +#define LPC32XX_I2S_RATE_Y_DIVIDER(val) BSP_FLD32(val, 8, 15) + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_I2S_H */ diff --git a/bsps/arm/include/bsp/lpc-lcd.h b/bsps/arm/include/bsp/lpc-lcd.h new file mode 100644 index 0000000000..a3ca4fe11a --- /dev/null +++ b/bsps/arm/include/bsp/lpc-lcd.h @@ -0,0 +1,213 @@ +/** + * @file + * + * @ingroup lpc_lcd + * + * @brief LCD support API. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_LCD_H +#define LIBBSP_ARM_SHARED_LPC_LCD_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_lcd LCD Support + * + * @ingroup lpc + * @ingroup arm_lpc32xx + * + * @brief LCD support. + * + * @{ + */ + +typedef struct { + uint8_t img [1024]; + uint32_t ctrl; + uint32_t cfg; + uint32_t pal0; + uint32_t pal1; + uint32_t xy; + uint32_t clip; + uint32_t intmsk; + uint32_t intclr; + uint32_t intraw; + uint32_t intstat; +} lpc_cursor; + +typedef struct { + uint32_t timh; + uint32_t timv; + uint32_t pol; + uint32_t le; + uint32_t upbase; + uint32_t lpbase; + uint32_t ctrl; + uint32_t intmsk; + uint32_t intraw; + uint32_t intstat; + uint32_t intclr; + uint32_t upcurr; + uint32_t lpcurr; + uint8_t reserved_0 [0x200 - 0x034]; + uint16_t pal [256]; + uint8_t reserved_1 [0x800 - 0x400]; + lpc_cursor crsr; +} lpc_lcd; + +/** + * @name LCD Configuration Register + * + * @{ + */ + +#define LCD_CFG_CLKDIV(val) BSP_FLD32(val, 0, 4) +#define LCD_CFG_HCLK_ENABLE BSP_BIT32(5) +#define LCD_CFG_MODE_SELECT(val) BSP_FLD32(val, 6, 7) +#define LCD_CFG_DISPLAY_TYPE BSP_BIT32(8) + +/** @} */ + +/** + * @name LCD Horizontal Timing Register + * + * @{ + */ + +#define LCD_TIMH_PPL(val) BSP_FLD32(val, 2, 7) +#define LCD_TIMH_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7) +#define LCD_TIMH_HSW(val) BSP_FLD32(val, 8, 15) +#define LCD_TIMH_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define LCD_TIMH_HFP(val) BSP_FLD32(val, 16, 23) +#define LCD_TIMH_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define LCD_TIMH_HBP(val) BSP_FLD32(val, 24, 31) +#define LCD_TIMH_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31) + +/** @} */ + +/** + * @name LCD Vertical Timing Register + * + * @{ + */ + +#define LCD_TIMV_LPP(val) BSP_FLD32(val, 0, 9) +#define LCD_TIMV_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define LCD_TIMV_VSW(val) BSP_FLD32(val, 10, 15) +#define LCD_TIMV_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15) +#define LCD_TIMV_VFP(val) BSP_FLD32(val, 16, 23) +#define LCD_TIMV_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define LCD_TIMV_VBP(val) BSP_FLD32(val, 24, 31) +#define LCD_TIMV_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31) + +/** @} */ + +/** + * @name LCD Clock and Signal Polarity Register + * + * @{ + */ + +#define LCD_POL_PCD_LO(val) BSP_FLD32(val, 0, 4) +#define LCD_POL_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LCD_POL_CLKSEL BSP_BIT32(5) +#define LCD_POL_ACB(val) BSP_FLD32(val, 6, 10) +#define LCD_POL_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10) +#define LCD_POL_IVS BSP_BIT32(11) +#define LCD_POL_IHS BSP_BIT32(12) +#define LCD_POL_IPC BSP_BIT32(13) +#define LCD_POL_IOE BSP_BIT32(14) +#define LCD_POL_CPL(val) BSP_FLD32(val, 16, 25) +#define LCD_POL_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25) +#define LCD_POL_BCD BSP_BIT32(26) +#define LCD_POL_PCD_HI(val) BSP_FLD32(val, 27, 31) +#define LCD_POL_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31) + +/** @} */ + +/** + * @name LCD Line End Control Register + * + * @{ + */ + +#define LCD_LE_LED(val) BSP_FLD32(val, 0, 6) +#define LCD_LE_LEE BSP_BIT32(16) + +/** @} */ + +/** + * @name LCD Control Register + * + * @{ + */ + +#define LCD_CTRL_LCDEN BSP_BIT32(0) +#define LCD_CTRL_LCDBPP(val) BSP_FLD32(val, 1, 3) +#define LCD_CTRL_LCDBPP_GET(reg) BSP_FLD32GET(reg, 1, 3) +#define LCD_CTRL_LCDBW BSP_BIT32(4) +#define LCD_CTRL_LCDTFT BSP_BIT32(5) +#define LCD_CTRL_LCDMONO8 BSP_BIT32(6) +#define LCD_CTRL_LCDDUAL BSP_BIT32(7) +#define LCD_CTRL_BGR BSP_BIT32(8) +#define LCD_CTRL_BEBO BSP_BIT32(9) +#define LCD_CTRL_BEPO BSP_BIT32(10) +#define LCD_CTRL_LCDPWR BSP_BIT32(11) +#define LCD_CTRL_LCDVCOMP(val) BSP_FLD32(val, 12, 13) +#define LCD_CTRL_LCDVCOMP_GET(reg) BSP_FLD32GET(reg, 12, 13) +#define LCD_CTRL_WATERMARK BSP_BIT32(16) + +/** @} */ + +/** + * @name LCD Interrupt Registers + * + * @{ + */ + +#define LCD_INT_FUF BSP_BIT32(1) +#define LCD_INT_LNBU BSP_BIT32(2) +#define LCD_INT_VCOMP BSP_BIT32(3) +#define LCD_INT_BER BSP_BIT32(4) + +/** @} */ + +/** + * @name LCD Color Palette Register + * + * @{ + */ + +#define LCD_PAL_R(val) BSP_FLD16(val, 0, 4) +#define LCD_PAL_G(val) BSP_FLD16(val, 5, 9) +#define LCD_PAL_B(val) BSP_FLD16(val, 10, 14) +#define LCD_PAL_I BSP_BIT16(15) + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_LCD_H */ diff --git a/bsps/arm/include/bsp/lpc-timer.h b/bsps/arm/include/bsp/lpc-timer.h new file mode 100644 index 0000000000..4c7ad4f1d1 --- /dev/null +++ b/bsps/arm/include/bsp/lpc-timer.h @@ -0,0 +1,159 @@ +/** + * @file + * + * @ingroup lpc_timer + * + * @brief Timer API. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_TIMER_H +#define LIBBSP_ARM_SHARED_LPC_TIMER_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_timer Timer Support + * + * @ingroup arm_lpc24xx + * @ingroup arm_lpc32xx + * + * @brief Timer support. + * + * @{ + */ + +/** + * @name Interrupt Register Defines + * + * @{ + */ + +#define LPC_TIMER_IR_MR0 0x1U +#define LPC_TIMER_IR_MR1 0x2U +#define LPC_TIMER_IR_MR2 0x4U +#define LPC_TIMER_IR_MR3 0x8U +#define LPC_TIMER_IR_CR0 0x10U +#define LPC_TIMER_IR_CR1 0x20U +#define LPC_TIMER_IR_CR2 0x40U +#define LPC_TIMER_IR_CR3 0x80U +#define LPC_TIMER_IR_ALL 0xffU + +/** @} */ + +/** + * @name Timer Control Register Defines + * + * @{ + */ + +#define LPC_TIMER_TCR_EN 0x1U +#define LPC_TIMER_TCR_RST 0x2U + +/** @} */ + +/** + * @name Match Control Register Defines + * + * @{ + */ + +#define LPC_TIMER_MCR_MR0_INTR 0x1U +#define LPC_TIMER_MCR_MR0_RST 0x2U +#define LPC_TIMER_MCR_MR0_STOP 0x4U +#define LPC_TIMER_MCR_MR1_INTR 0x8U +#define LPC_TIMER_MCR_MR1_RST 0x10U +#define LPC_TIMER_MCR_MR1_STOP 0x20U +#define LPC_TIMER_MCR_MR2_INTR 0x40U +#define LPC_TIMER_MCR_MR2_RST 0x80U +#define LPC_TIMER_MCR_MR2_STOP 0x100U +#define LPC_TIMER_MCR_MR3_INTR 0x200U +#define LPC_TIMER_MCR_MR3_RST 0x400U +#define LPC_TIMER_MCR_MR3_STOP 0x800U + +/** @} */ + +/** + * @name Capture Control Register Defines + * + * @{ + */ + +#define LPC_TIMER_CCR_CAP0_RE 0x1U +#define LPC_TIMER_CCR_CAP0_FE 0x2U +#define LPC_TIMER_CCR_CAP0_INTR 0x4U +#define LPC_TIMER_CCR_CAP1_RE 0x8U +#define LPC_TIMER_CCR_CAP1_FE 0x10U +#define LPC_TIMER_CCR_CAP1_INTR 0x20U +#define LPC_TIMER_CCR_CAP2_RE 0x40U +#define LPC_TIMER_CCR_CAP2_FE 0x80U +#define LPC_TIMER_CCR_CAP2_INTR 0x100U +#define LPC_TIMER_CCR_CAP3_RE 0x200U +#define LPC_TIMER_CCR_CAP3_FE 0x400U +#define LPC_TIMER_CCR_CAP3_INTR 0x800U + +/** @} */ + +/** + * @name External Match Register Defines + * + * @{ + */ + +#define LPC_TIMER_EMR_EM0_RE 0x1U +#define LPC_TIMER_EMR_EM1_FE 0x2U +#define LPC_TIMER_EMR_EM2_INTR 0x4U +#define LPC_TIMER_EMR_EM3_RE 0x8U +#define LPC_TIMER_EMR_EMC0_FE 0x10U +#define LPC_TIMER_EMR_EMC1_INTR 0x20U +#define LPC_TIMER_EMR_EMC2_RE 0x40U +#define LPC_TIMER_EMR_EMC3_FE 0x80U + +/** @} */ + +/** + * @brief Timer control block. + */ +typedef struct { + uint32_t ir; + uint32_t tcr; + uint32_t tc; + uint32_t pr; + uint32_t pc; + uint32_t mcr; + uint32_t mr0; + uint32_t mr1; + uint32_t mr2; + uint32_t mr3; + uint32_t ccr; + uint32_t cr0; + uint32_t cr1; + uint32_t cr2; + uint32_t cr3; + uint32_t emr; + uint32_t ctcr; +} lpc_timer; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_TIMER_H */ diff --git a/bsps/arm/include/bsp/start.h b/bsps/arm/include/bsp/start.h new file mode 100644 index 0000000000..bf8eed4433 --- /dev/null +++ b/bsps/arm/include/bsp/start.h @@ -0,0 +1,183 @@ +/** + * @file + * + * @ingroup arm_start + * + * @brief ARM system low level start. + */ + +/* + * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_START_H +#define LIBBSP_ARM_SHARED_START_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_start System Start + * + * @ingroup arm_shared + * + * @brief ARM system low level start. + * + * @{ + */ + +#define BSP_START_TEXT_SECTION __attribute__((section(".bsp_start_text"))) + +#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data"))) + +/* +* Many ARM boot loaders pass arguments to loaded OS kernel +*/ +#ifdef BSP_START_HOOKS_WITH_LOADER_ARGS +#define BSP_START_HOOKS_LOADER_ARGS int saved_psr, int saved_machid, int saved_dtb_adr +#else +#define BSP_START_HOOKS_LOADER_ARGS void +#endif + +/** +* @brief System start entry. +*/ +void _start(void); + +/** +* @brief Start entry hook 0. +* +* This hook will be called from the start entry code after all modes and +* stack pointers are initialized but before the copying of the exception +* vectors. +*/ +void bsp_start_hook_0(BSP_START_HOOKS_LOADER_ARGS); + +/** +* @brief Start entry hook 1. +* +* This hook will be called from the start entry code after copying of the +* exception vectors but before the call to boot_card(). +*/ +void bsp_start_hook_1(BSP_START_HOOKS_LOADER_ARGS); + +/** + * @brief Similar to standard memcpy(). + * + * The memory areas must be word aligned. Copy code will be executed from the + * stack. If @a dest equals @a src nothing will be copied. + */ +void bsp_start_memcpy(int *dest, const int *src, size_t n); + +/** + * @brief ARM entry point to bsp_start_memcpy(). + */ +void bsp_start_memcpy_arm(int *dest, const int *src, size_t n); + +/** + * @brief Copies all standard sections from the load to the runtime area. + */ +BSP_START_TEXT_SECTION static inline void bsp_start_copy_sections(void) +{ + /* Copy .text section */ + bsp_start_memcpy( + (int *) bsp_section_text_begin, + (const int *) bsp_section_text_load_begin, + (size_t) bsp_section_text_size + ); + + /* Copy .rodata section */ + bsp_start_memcpy( + (int *) bsp_section_rodata_begin, + (const int *) bsp_section_rodata_load_begin, + (size_t) bsp_section_rodata_size + ); + + /* Copy .data section */ + bsp_start_memcpy( + (int *) bsp_section_data_begin, + (const int *) bsp_section_data_load_begin, + (size_t) bsp_section_data_size + ); + + /* Copy .fast_text section */ + bsp_start_memcpy( + (int *) bsp_section_fast_text_begin, + (const int *) bsp_section_fast_text_load_begin, + (size_t) bsp_section_fast_text_size + ); + + /* Copy .fast_data section */ + bsp_start_memcpy( + (int *) bsp_section_fast_data_begin, + (const int *) bsp_section_fast_data_load_begin, + (size_t) bsp_section_fast_data_size + ); +} + +BSP_START_TEXT_SECTION static inline void +bsp_start_memcpy_libc(void *dest, const void *src, size_t n) +{ + if (dest != src) { + memcpy(dest, src, n); + } +} + +/** + * @brief Copies the .data, .fast_text and .fast_data sections from the load to + * the runtime area using the C library memcpy(). + * + * Works only in case the .start, .text and .rodata sections reside in one + * memory region. + */ +BSP_START_TEXT_SECTION static inline void bsp_start_copy_sections_compact(void) +{ + /* Copy .data section */ + bsp_start_memcpy_libc( + bsp_section_data_begin, + bsp_section_data_load_begin, + (size_t) bsp_section_data_size + ); + + /* Copy .fast_text section */ + bsp_start_memcpy_libc( + bsp_section_fast_text_begin, + bsp_section_fast_text_load_begin, + (size_t) bsp_section_fast_text_size + ); + + /* Copy .fast_data section */ + bsp_start_memcpy_libc( + bsp_section_fast_data_begin, + bsp_section_fast_data_load_begin, + (size_t) bsp_section_fast_data_size + ); +} + +BSP_START_TEXT_SECTION static inline void bsp_start_clear_bss(void) +{ + memset(bsp_section_bss_begin, 0, (size_t) bsp_section_bss_size); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_START_H */ diff --git a/bsps/arm/include/cmsis_gcc.h b/bsps/arm/include/cmsis_gcc.h new file mode 100644 index 0000000000..d868f2e64b --- /dev/null +++ b/bsps/arm/include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/bsps/arm/include/core_cm7.h b/bsps/arm/include/core_cm7.h new file mode 100644 index 0000000000..20963c148c --- /dev/null +++ b/bsps/arm/include/core_cm7.h @@ -0,0 +1,2512 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsps/arm/include/core_cmFunc.h b/bsps/arm/include/core_cmFunc.h new file mode 100644 index 0000000000..ca319a55cb --- /dev/null +++ b/bsps/arm/include/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsps/arm/include/core_cmInstr.h b/bsps/arm/include/core_cmInstr.h new file mode 100644 index 0000000000..a0a506458d --- /dev/null +++ b/bsps/arm/include/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsps/arm/include/core_cmSimd.h b/bsps/arm/include/core_cmSimd.h new file mode 100644 index 0000000000..4d76bf9018 --- /dev/null +++ b/bsps/arm/include/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/bsps/arm/include/libcpu/am335x.h b/bsps/arm/include/libcpu/am335x.h new file mode 100644 index 0000000000..367e97cae9 --- /dev/null +++ b/bsps/arm/include/libcpu/am335x.h @@ -0,0 +1,704 @@ +/* + * Copyright (c) 2012 Claas Ziemke. All rights reserved. + * + * Claas Ziemke + * Kernerstrasse 11 + * 70182 Stuttgart + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified by Ben Gras to add lots + * of beagleboard/beaglebone definitions, delete lpc32xx specific + * ones, and merge with some other header files. + */ + +#if !defined(_AM335X_H_) +#define _AM335X_H_ + +/* Interrupt controller memory map */ +#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */ + +/* Interrupt controller memory map */ +#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */ + +#define AM335X_INT_EMUINT 0 + /* Emulation interrupt (EMUICINTR) */ +#define AM335X_INT_COMMTX 1 + /* CortexA8 COMMTX */ +#define AM335X_INT_COMMRX 2 + /* CortexA8 COMMRX */ +#define AM335X_INT_BENCH 3 + /* CortexA8 NPMUIRQ */ +#define AM335X_INT_ELM_IRQ 4 + /* Sinterrupt (Error location process completion) */ +#define AM335X_INT_NMI 7 + /* nmi_int */ +#define AM335X_INT_L3DEBUG 9 + /* l3_FlagMux_top_FlagOut1 */ +#define AM335X_INT_L3APPINT 10 + /* l3_FlagMux_top_FlagOut0 */ +#define AM335X_INT_PRCMINT 11 + /* irq_mpu */ +#define AM335X_INT_EDMACOMPINT 12 + /* tpcc_int_pend_po0 */ +#define AM335X_INT_EDMAMPERR 13 + /* tpcc_mpint_pend_po */ +#define AM335X_INT_EDMAERRINT 14 + /* tpcc_errint_pend_po */ +#define AM335X_INT_ADC_TSC_GENINT 16 + /* gen_intr_pend */ +#define AM335X_INT_USBSSINT 17 + /* usbss_intr_pend */ +#define AM335X_INT_USB0 18 + /* usb0_intr_pend */ +#define AM335X_INT_USB1 19 + /* usb1_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT0 20 + /* pr1_host_intr0_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT1 21 + /* pr1_host_intr1_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT2 22 + /* pr1_host_intr2_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT3 23 + /* pr1_host_intr3_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT4 24 + /* pr1_host_intr4_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT5 25 + /* pr1_host_intr5_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT6 26 + /* pr1_host_intr6_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT7 27 + /* pr1_host_intr7_intr_pend */ +#define AM335X_INT_MMCSD1INT 28 + /* MMCSD1 SINTERRUPTN */ +#define AM335X_INT_MMCSD2INT 29 + /* MMCSD2 SINTERRUPT */ +#define AM335X_INT_I2C2INT 30 + /* I2C2 POINTRPEND */ +#define AM335X_INT_eCAP0INT 31 + /* ecap_intr_intr_pend */ +#define AM335X_INT_GPIOINT2A 32 + /* GPIO 2 POINTRPEND1 */ +#define AM335X_INT_GPIOINT2B 33 + /* GPIO 2 POINTRPEND2 */ +#define AM335X_INT_USBWAKEUP 34 + /* USBSS slv0p_Swakeup */ +#define AM335X_INT_LCDCINT 36 + /* LCDC lcd_irq */ +#define AM335X_INT_GFXINT 37 + /* SGX530 THALIAIRQ */ +#define AM335X_INT_ePWM2INT 39 + /* (PWM Subsystem) epwm_intr_intr_pend */ +#define AM335X_INT_3PGSWRXTHR0 40 + /* (Ethernet) c0_rx_thresh_pend (RX_THRESH_PULSE) */ +#define AM335X_INT_3PGSWRXINT0 41 + /* CPSW (Ethernet) c0_rx_pend */ +#define AM335X_INT_3PGSWTXINT0 42 + /* CPSW (Ethernet) c0_tx_pend */ +#define AM335X_INT_3PGSWMISC0 43 + /* CPSW (Ethernet) c0_misc_pend */ +#define AM335X_INT_UART3INT 44 + /* UART3 niq */ +#define AM335X_INT_UART4INT 45 + /* UART4 niq */ +#define AM335X_INT_UART5INT 46 + /* UART5 niq */ +#define AM335X_INT_eCAP1INT 47 + /* (PWM Subsystem) ecap_intr_intr_pend */ +#define AM335X_INT_DCAN0_INT0 52 + /* DCAN0 dcan_intr0_intr_pend */ +#define AM335X_INT_DCAN0_INT1 53 + /* DCAN0 dcan_intr1_intr_pend */ +#define AM335X_INT_DCAN0_PARITY 54 + /* DCAN0 dcan_uerr_intr_pend */ +#define AM335X_INT_DCAN1_INT0 55 + /* DCAN1 dcan_intr0_intr_pend */ +#define AM335X_INT_DCAN1_INT1 56 + /* DCAN1 dcan_intr1_intr_pend */ +#define AM335X_INT_DCAN1_PARITY 57 + /* DCAN1 dcan_uerr_intr_pend */ +#define AM335X_INT_ePWM0_TZINT 58 + /* eHRPWM0 TZ interrupt (PWM epwm_tz_intr_pend Subsystem) */ +#define AM335X_INT_ePWM1_TZINT 59 + /* eHRPWM1 TZ interrupt (PWM epwm_tz_intr_pend Subsystem) */ +#define AM335X_INT_ePWM2_TZINT 60 + /* eHRPWM2 TZ interrupt (PWM epwm_tz_intr_pend Subsystem) */ +#define AM335X_INT_eCAP2INT 61 + /* eCAP2 (PWM Subsystem) ecap_intr_intr_pend */ +#define AM335X_INT_GPIOINT3A 62 + /* GPIO 3 POINTRPEND1 */ +#define AM335X_INT_GPIOINT3B 63 + /* GPIO 3 POINTRPEND2 */ +#define AM335X_INT_MMCSD0INT 64 + /* MMCSD0 SINTERRUPTN */ +#define AM335X_INT_SPI0INT 65 + /* McSPI0 SINTERRUPTN */ +#define AM335X_INT_TINT0 66 + /* Timer0 POINTR_PEND */ +#define AM335X_INT_TINT1_1MS 67 + /* DMTIMER_1ms POINTR_PEND */ +#define AM335X_INT_TINT2 68 + /* DMTIMER2 POINTR_PEND */ +#define AM335X_INT_TINT3 69 + /* DMTIMER3 POINTR_PEND */ +#define AM335X_INT_I2C0INT 70 + /* I2C0 POINTRPEND */ +#define AM335X_INT_I2C1INT 71 + /* I2C1 POINTRPEND */ +#define AM335X_INT_UART0INT 72 + /* UART0 niq */ +#define AM335X_INT_UART1INT 73 + /* UART1 niq */ +#define AM335X_INT_UART2INT 74 + /* UART2 niq */ +#define AM335X_INT_RTCINT 75 + /* RTC timer_intr_pend */ +#define AM335X_INT_RTCALARMINT 76 + /* RTC alarm_intr_pend */ +#define AM335X_INT_MBINT0 77 + /* Mailbox0 (mail_u0_irq) initiator_sinterrupt_q_n */ +#define AM335X_INT_M3_TXEV 78 + /* Wake M3 Subsystem TXEV */ +#define AM335X_INT_eQEP0INT 79 + /* eQEP0 (PWM Subsystem) eqep_intr_intr_pend */ +#define AM335X_INT_MCATXINT0 80 + /* McASP0 mcasp_x_intr_pend */ +#define AM335X_INT_MCARXINT0 81 + /* McASP0 mcasp_r_intr_pend */ +#define AM335X_INT_MCATXINT1 82 + /* McASP1 mcasp_x_intr_pend */ +#define AM335X_INT_MCARXINT1 83 + /* McASP1 mcasp_r_intr_pend */ +#define AM335X_INT_ePWM0INT 86 + /* (PWM Subsystem) epwm_intr_intr_pend */ +#define AM335X_INT_ePWM1INT 87 + /* (PWM Subsystem) epwm_intr_intr_pend */ +#define AM335X_INT_eQEP1INT 88 + /* (PWM Subsystem) eqep_intr_intr_pend */ +#define AM335X_INT_eQEP2INT 89 + /* (PWM Subsystem) eqep_intr_intr_pend */ +#define AM335X_INT_DMA_INTR_PIN2 90 + /* External DMA/Interrupt Pin2 */ +#define AM335X_INT_WDT1INT 91 + /* (Public Watchdog) WDTIMER1 PO_INT_PEND */ +#define AM335X_INT_TINT4 92 + /* DMTIMER4 POINTR_PEN */ +#define AM335X_INT_TINT5 93 + /* DMTIMER5 POINTR_PEN */ +#define AM335X_INT_TINT6 94 + /* DMTIMER6 POINTR_PEND */ +#define AM335X_INT_TINT7 95 + /* DMTIMER7 POINTR_PEND */ +#define AM335X_INT_GPIOINT0A 96 + /* GPIO 0 POINTRPEND1 */ +#define AM335X_INT_GPIOINT0B 97 + /* GPIO 0 POINTRPEND2 */ +#define AM335X_INT_GPIOINT1A 98 + /* GPIO 1 POINTRPEND1 */ +#define AM335X_INT_GPIOINT1B 99 + /* GPIO 1 POINTRPEND2 */ +#define AM335X_INT_GPMCINT 100 + /* GPMC gpmc_sinterrupt */ +#define AM335X_INT_DDRERR0 101 + /* EMIF sys_err_intr_pend */ +#define AM335X_INT_TCERRINT0 112 + /* TPTC0 tptc_erint_pend_po */ +#define AM335X_INT_TCERRINT1 113 + /* TPTC1 tptc_erint_pend_po */ +#define AM335X_INT_TCERRINT2 114 + /* TPTC2 tptc_erint_pend_po */ +#define AM335X_INT_ADC_TSC_PENINT 115 + /* ADC_TSC pen_intr_pend */ +#define AM335X_INT_SMRFLX_Sabertooth 120 + /* Smart Reflex 0 intrpen */ +#define AM335X_INT_SMRFLX_Core 121 + /* Smart Reflex 1 intrpend */ +#define AM335X_INT_DMA_INTR_PIN0 123 + /* pi_x_dma_event_intr0 (xdma_event_intr0) */ +#define AM335X_INT_DMA_INTR_PIN1 124 + /* pi_x_dma_event_intr1 (xdma_event_intr1) */ +#define AM335X_INT_SPI1INT 125 + /* McSPI1 SINTERRUPTN */ + +#define OMAP3_AM335X_NR_IRQ_VECTORS 125 + +#define AM335X_DMTIMER0_BASE 0x44E05000 + /* DMTimer0 Registers */ +#define AM335X_DMTIMER1_1MS_BASE 0x44E31000 + /* DMTimer1 1ms Registers (Accurate 1ms timer) */ +#define AM335X_DMTIMER2_BASE 0x48040000 + /* DMTimer2 Registers */ +#define AM335X_DMTIMER3_BASE 0x48042000 + /* DMTimer3 Registers */ +#define AM335X_DMTIMER4_BASE 0x48044000 + /* DMTimer4 Registers */ +#define AM335X_DMTIMER5_BASE 0x48046000 + /* DMTimer5 Registers */ +#define AM335X_DMTIMER6_BASE 0x48048000 + /* DMTimer6 Registers */ +#define AM335X_DMTIMER7_BASE 0x4804A000 + /* DMTimer7 Registers */ + +/* General-purpose timer registers + AM335x non 1MS timers have different offsets */ +#define AM335X_TIMER_TIDR 0x000 + /* IP revision code */ +#define AM335X_TIMER_TIOCP_CFG 0x010 + /* Controls params for GP timer L4 interface */ +#define AM335X_TIMER_IRQSTATUS_RAW 0x024 + /* Timer IRQSTATUS Raw Register */ +#define AM335X_TIMER_IRQSTATUS 0x028 + /* Timer IRQSTATUS Register */ +#define AM335X_TIMER_IRQENABLE_SET 0x02C + /* Timer IRQENABLE Set Register */ +#define AM335X_TIMER_IRQENABLE_CLR 0x030 + /* Timer IRQENABLE Clear Register */ +#define AM335X_TIMER_IRQWAKEEN 0x034 + /* Timer IRQ Wakeup Enable Register */ +#define AM335X_TIMER_TCLR 0x038 + /* Controls optional features */ +#define AM335X_TIMER_TCRR 0x03C + /* Internal counter value */ +#define AM335X_TIMER_TLDR 0x040 + /* Timer load value */ +#define AM335X_TIMER_TTGR 0x044 + /* Triggers counter reload */ +#define AM335X_TIMER_TWPS 0x048 + /* Indicates if Write-Posted pending */ +#define AM335X_TIMER_TMAR 0x04C + /* Value to be compared with counter */ +#define AM335X_TIMER_TCAR1 0x050 + /* First captured value of counter register */ +#define AM335X_TIMER_TSICR 0x054 + /* Control posted mode and functional SW reset */ +#define AM335X_TIMER_TCAR2 0x058 + /* Second captured value of counter register */ +#define AM335X_WDT_BASE 0x44E35000 + /* Watchdog timer */ +#define AM335X_WDT_WWPS 0x34 + /* Command posted status */ +#define AM335X_WDT_WSPR 0x48 + /* Activate/deactivate sequence */ + +/* RTC registers */ +#define AM335X_RTC_BASE 0x44E3E000 +#define AM335X_RTC_SECS 0x0 +#define AM335X_RTC_MINS 0x4 +#define AM335X_RTC_HOURS 0x8 +#define AM335X_RTC_DAYS 0xc +#define AM335X_RTC_MONTHS 0x10 +#define AM335X_RTC_YEARS 0x14 +#define AM335X_RTC_WEEKS 0x18 +#define AM335X_RTC_CTRL_REG 0x40 +#define AM335X_RTC_STATUS_REG 0x44 +#define AM335X_RTC_REV_REG 0x74 +#define AM335X_RTC_SYSCONFIG 0x78 +#define AM335X_RTC_KICK0 0x6c +#define AM335X_RTC_KICK1 0x70 +#define AM335X_RTC_OSC_CLOCK 0x54 + +#define AM335X_RTC_KICK0_KEY 0x83E70B13 +#define AM335X_RTC_KICK1_KEY 0x95A4F1E0 + +/* GPIO memory-mapped registers */ + +#define AM335X_GPIO0_BASE 0x44E07000 + /* GPIO Bank 0 base Register */ +#define AM335X_GPIO1_BASE 0x4804C000 + /* GPIO Bank 1 base Register */ +#define AM335X_GPIO2_BASE 0x481AC000 + /* GPIO Bank 2 base Register */ +#define AM335X_GPIO3_BASE 0x481AE000 + /* GPIO Bank 3 base Register */ + +#define AM335X_GPIO_REVISION 0x00 +#define AM335X_GPIO_SYSCONFIG 0x10 +#define AM335X_GPIO_EOI 0x20 +#define AM335X_GPIO_IRQSTATUS_RAW_0 0x24 +#define AM335X_GPIO_IRQSTATUS_RAW_1 0x28 +#define AM335X_GPIO_IRQSTATUS_0 0x2C +#define AM335X_GPIO_IRQSTATUS_1 0x30 +#define AM335X_GPIO_IRQSTATUS_SET_0 0x34 +#define AM335X_GPIO_IRQSTATUS_SET_1 0x38 +#define AM335X_GPIO_IRQSTATUS_CLR_0 0x3C +#define AM335X_GPIO_IRQSTATUS_CLR_1 0x40 +#define AM335X_GPIO_IRQWAKEN_0 0x44 +#define AM335X_GPIO_IRQWAKEN_1 0x48 +#define AM335X_GPIO_SYSSTATUS 0x114 +#define AM335X_GPIO_CTRL 0x130 +#define AM335X_GPIO_OE 0x134 +#define AM335X_GPIO_DATAIN 0x138 +#define AM335X_GPIO_DATAOUT 0x13C +#define AM335X_GPIO_LEVELDETECT0 0x140 +#define AM335X_GPIO_LEVELDETECT1 0x144 +#define AM335X_GPIO_RISINGDETECT 0x148 +#define AM335X_GPIO_FALLINGDETECT 0x14C +#define AM335X_GPIO_DEBOUNCENABLE 0x150 +#define AM335X_GPIO_DEBOUNCINGTIME 0x154 +#define AM335X_GPIO_CLEARDATAOUT 0x190 +#define AM335X_GPIO_SETDATAOUT 0x194 + +/* AM335X Pad Configuration Register Base */ +#define AM335X_PADCONF_BASE 0x44E10000 + +/* Memory mapped register offset for Control Module */ +#define AM335X_CONF_GPMC_AD0 0x800 +#define AM335X_CONF_GPMC_AD1 0x804 +#define AM335X_CONF_GPMC_AD2 0x808 +#define AM335X_CONF_GPMC_AD3 0x80C +#define AM335X_CONF_GPMC_AD4 0x810 +#define AM335X_CONF_GPMC_AD5 0x814 +#define AM335X_CONF_GPMC_AD6 0x818 +#define AM335X_CONF_GPMC_AD7 0x81C +#define AM335X_CONF_GPMC_AD8 0x820 +#define AM335X_CONF_GPMC_AD9 0x824 +#define AM335X_CONF_GPMC_AD10 0x828 +#define AM335X_CONF_GPMC_AD11 0x82C +#define AM335X_CONF_GPMC_AD12 0x830 +#define AM335X_CONF_GPMC_AD13 0x834 +#define AM335X_CONF_GPMC_AD14 0x838 +#define AM335X_CONF_GPMC_AD15 0x83C +#define AM335X_CONF_GPMC_A0 0x840 +#define AM335X_CONF_GPMC_A1 0x844 +#define AM335X_CONF_GPMC_A2 0x848 +#define AM335X_CONF_GPMC_A3 0x84C +#define AM335X_CONF_GPMC_A4 0x850 +#define AM335X_CONF_GPMC_A5 0x854 +#define AM335X_CONF_GPMC_A6 0x858 +#define AM335X_CONF_GPMC_A7 0x85C +#define AM335X_CONF_GPMC_A8 0x860 +#define AM335X_CONF_GPMC_A9 0x864 +#define AM335X_CONF_GPMC_A10 0x868 +#define AM335X_CONF_GPMC_A11 0x86C +#define AM335X_CONF_GPMC_WAIT0 0x870 +#define AM335X_CONF_GPMC_WPN 0x874 +#define AM335X_CONF_GPMC_BEN1 0x878 +#define AM335X_CONF_GPMC_CSN0 0x87C +#define AM335X_CONF_GPMC_CSN1 0x880 +#define AM335X_CONF_GPMC_CSN2 0x884 +#define AM335X_CONF_GPMC_CSN3 0x888 +#define AM335X_CONF_GPMC_CLK 0x88C +#define AM335X_CONF_GPMC_ADVN_ALE 0x890 +#define AM335X_CONF_GPMC_OEN_REN 0x894 +#define AM335X_CONF_GPMC_WEN 0x898 +#define AM335X_CONF_GPMC_BEN0_CLE 0x89C +#define AM335X_CONF_LCD_DATA0 0x8A0 +#define AM335X_CONF_LCD_DATA1 0x8A4 +#define AM335X_CONF_LCD_DATA2 0x8A8 +#define AM335X_CONF_LCD_DATA3 0x8AC +#define AM335X_CONF_LCD_DATA4 0x8B0 +#define AM335X_CONF_LCD_DATA5 0x8B4 +#define AM335X_CONF_LCD_DATA6 0x8B8 +#define AM335X_CONF_LCD_DATA7 0x8BC +#define AM335X_CONF_LCD_DATA8 0x8C0 +#define AM335X_CONF_LCD_DATA9 0x8C4 +#define AM335X_CONF_LCD_DATA10 0x8C8 +#define AM335X_CONF_LCD_DATA11 0x8CC +#define AM335X_CONF_LCD_DATA12 0x8D0 +#define AM335X_CONF_LCD_DATA13 0x8D4 +#define AM335X_CONF_LCD_DATA14 0x8D8 +#define AM335X_CONF_LCD_DATA15 0x8DC +#define AM335X_CONF_LCD_VSYNC 0x8E0 +#define AM335X_CONF_LCD_HSYNC 0x8E4 +#define AM335X_CONF_LCD_PCLK 0x8E8 +#define AM335X_CONF_LCD_AC_BIAS_EN 0x8EC +#define AM335X_CONF_MMC0_DAT3 0x8F0 +#define AM335X_CONF_MMC0_DAT2 0x8F4 +#define AM335X_CONF_MMC0_DAT1 0x8F8 +#define AM335X_CONF_MMC0_DAT0 0x8FC +#define AM335X_CONF_MMC0_CLK 0x900 +#define AM335X_CONF_MMC0_CMD 0x904 +#define AM335X_CONF_MII1_COL 0x908 +#define AM335X_CONF_MII1_CRS 0x90C +#define AM335X_CONF_MII1_RX_ER 0x910 +#define AM335X_CONF_MII1_TX_EN 0x914 +#define AM335X_CONF_MII1_RX_DV 0x918 +#define AM335X_CONF_MII1_TXD3 0x91C +#define AM335X_CONF_MII1_TXD2 0x920 +#define AM335X_CONF_MII1_TXD1 0x924 +#define AM335X_CONF_MII1_TXD0 0x928 +#define AM335X_CONF_MII1_TX_CLK 0x92C +#define AM335X_CONF_MII1_RX_CLK 0x930 +#define AM335X_CONF_MII1_RXD3 0x934 +#define AM335X_CONF_MII1_RXD2 0x938 +#define AM335X_CONF_MII1_RXD1 0x93C +#define AM335X_CONF_MII1_RXD0 0x940 +#define AM335X_CONF_RMII1_REF_CLK 0x944 +#define AM335X_CONF_MDIO 0x948 +#define AM335X_CONF_MDC 0x94C +#define AM335X_CONF_SPI0_SCLK 0x950 +#define AM335X_CONF_SPI0_D0 0x954 +#define AM335X_CONF_SPI0_D1 0x958 +#define AM335X_CONF_SPI0_CS0 0x95C +#define AM335X_CONF_SPI0_CS1 0x960 +#define AM335X_CONF_ECAP0_IN_PWM0_OUT 0x964 +#define AM335X_CONF_UART0_CTSN 0x968 +#define AM335X_CONF_UART0_RTSN 0x96C +#define AM335X_CONF_UART0_RXD 0x970 +#define AM335X_CONF_UART0_TXD 0x974 +#define AM335X_CONF_UART1_CTSN 0x978 +#define AM335X_CONF_UART1_RTSN 0x97C +#define AM335X_CONF_UART1_RXD 0x980 +#define AM335X_CONF_UART1_TXD 0x984 +#define AM335X_CONF_I2C0_SDA 0x988 +#define AM335X_CONF_I2C0_SCL 0x98C +#define AM335X_CONF_MCASP0_ACLKX 0x990 +#define AM335X_CONF_MCASP0_FSX 0x994 +#define AM335X_CONF_MCASP0_AXR0 0x998 +#define AM335X_CONF_MCASP0_AHCLKR 0x99C +#define AM335X_CONF_MCASP0_ACLKR 0x9A0 +#define AM335X_CONF_MCASP0_FSR 0x9A4 +#define AM335X_CONF_MCASP0_AXR1 0x9A8 +#define AM335X_CONF_MCASP0_AHCLKX 0x9AC +#define AM335X_CONF_XDMA_EVENT_INTR0 0x9B0 +#define AM335X_CONF_XDMA_EVENT_INTR1 0x9B4 +#define AM335X_CONF_WARMRSTN 0x9B8 +#define AM335X_CONF_NNMI 0x9C0 +#define AM335X_CONF_TMS 0x9D0 +#define AM335X_CONF_TDI 0x9D4 +#define AM335X_CONF_TDO 0x9D8 +#define AM335X_CONF_TCK 0x9DC +#define AM335X_CONF_TRSTN 0x9E0 +#define AM335X_CONF_EMU0 0x9E4 +#define AM335X_CONF_EMU1 0x9E8 +#define AM335X_CONF_RTC_PWRONRSTN 0x9F8 +#define AM335X_CONF_PMIC_POWER_EN 0x9FC +#define AM335X_CONF_EXT_WAKEUP 0xA00 +#define AM335X_CONF_RTC_KALDO_ENN 0xA04 +#define AM335X_CONF_USB0_DRVVBUS 0xA1C +#define AM335X_CONF_USB1_DRVVBUS 0xA34 + +/* Registers for PWM Subsystem */ +#define AM335X_PWMSS_CTRL (0x664) +#define AM335X_CM_PER_EPWMSS0_CLKCTRL (0xD4) +#define AM335X_CM_PER_EPWMSS1_CLKCTRL (0xCC) +#define AM335X_CM_PER_EPWMSS2_CLKCTRL (0xD8) +#define AM335X_CONTROL_MODULE (0x44e10000) +#define AM335X_CM_PER_ADDR (0x44e00000) +#define AM335X_PWMSS_CLKSTATUS (0xC) +#define AM335X_PWMSS0_MMAP_ADDR 0x48300000 +#define AM335X_PWMSS1_MMAP_ADDR 0x48302000 +#define AM335X_PWMSS2_MMAP_ADDR 0x48304000 +#define AM335X_PWMSS_MMAP_LEN 0x1000 +#define AM335X_PWMSS_IDVER 0x0 +#define AM335X_PWMSS_SYSCONFIG 0x4 +#define AM335X_PWMSS_CLKCONFIG 0x8 +#define AM335X_PWMSS_CLK_EN_ACK 0x100 +#define AM335X_EPWM_TBCTL 0x0 +#define AM335X_EPWM_TBSTS 0x2 +#define AM335X_EPWM_TBPHSHR 0x4 +#define AM335X_EPWM_TBPHS 0x6 +#define AM335X_EPWM_TBCNT 0x8 +#define AM335X_EPWM_TBPRD 0xA +#define AM335X_EPWM_CMPCTL 0xE +#define AM335X_EPWM_CMPAHR 0x10 +#define AM335X_EPWM_CMPA 0x12 +#define AM335X_EPWM_CMPB 0x14 +#define AM335X_EPWM_AQCTLA 0x16 +#define AM335X_EPWM_AQCTLB 0x18 +#define AM335X_EPWM_AQSFRC 0x1A +#define AM335X_EPWM_AQCSFRC 0x1C +#define AM335X_EPWM_DBCTL 0x1E +#define AM335X_EPWM_DBRED 0x20 +#define AM335X_EPWM_DBFED 0x22 +#define AM335X_TBCTL_CTRMODE_UP 0x0 +#define AM335X_TBCTL_CTRMODE_DOWN 0x1 +#define AM335X_TBCTL_CTRMODE_UPDOWN 0x2 +#define AM335X_TBCTL_CTRMODE_FREEZE 0x3 +#define AM335X_EPWM_AQCTLA_ZRO_XALOW (0x0001u) +#define AM335X_EPWM_AQCTLA_ZRO_XAHIGH (0x0002u) +#define AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE (0x0003u) +#define AM335X_EPWM_AQCTLA_CAU_SHIFT (0x0004u) +#define AM335X_EPWM_AQCTLA_ZRO_XBLOW (0x0001u) +#define AM335X_EPWM_AQCTLB_ZRO_XBHIGH (0x0002u) +#define AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE (0x0003u) +#define AM335X_EPWM_AQCTLB_CBU_SHIFT (0x0008u) +#define AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE (0x0003u) +#define AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN (0x00000001u) +#define AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN (0x00000002u) +#define AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN (0x00000004u) +#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_TBCTL_CLKDIV_MASK (3 << 10) +#define AM335X_TBCTL_HSPCLKDIV_MASK (3 << 7) +#define AM335X_EPWM_TBCTL_CLKDIV (0x1C00u) +#define AM335X_EPWM_TBCTL_CLKDIV_SHIFT (0x000Au) +#define AM335X_EPWM_TBCTL_HSPCLKDIV (0x0380u) +#define AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT (0x0007u) +#define AM335X_EPWM_TBCTL_PRDLD (0x0008u) +#define AM335X_EPWM_PRD_LOAD_SHADOW_MASK AM335X_EPWM_TBCTL_PRDLD +#define AM335X_EPWM_SHADOW_WRITE_ENABLE 0x0 +#define AM335X_EPWM_SHADOW_WRITE_DISABLE 0x1 +#define AM335X_EPWM_TBCTL_PRDLD_SHIFT (0x0003u) +#define AM335X_EPWM_TBCTL_CTRMODE (0x0003u) +#define AM335X_EPWM_COUNTER_MODE_MASK AM335X_EPWM_TBCTL_CTRMODE +#define AM335X_TBCTL_FREERUN (2 << 14) +#define AM335X_TBCTL_CTRMODE_SHIFT (0x0000u) +#define AM335X_EPWM_COUNT_UP (AM335X_TBCTL_CTRMODE_UP << \ + AM335X_TBCTL_CTRMODE_SHIFT) + +#define AM335X_EPWM_REGS (0x00000200) +#define AM335X_EPWM_0_REGS (AM335X_PWMSS0_MMAP_ADDR + AM335X_EPWM_REGS) +#define AM335X_EPWM_1_REGS (AM335X_PWMSS1_MMAP_ADDR + AM335X_EPWM_REGS) +#define AM335X_EPWM_2_REGS (AM335X_PWMSS2_MMAP_ADDR + AM335X_EPWM_REGS) + +#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC (0x0u) +#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST (0x00030000u) + +#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST (0x00030000u) +#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC (0x0u) +#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u) + +#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC (0x0u) +#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST (0x00030000u) + + + +/* I2C registers */ +#define AM335X_I2C0_BASE 0x44e0b000 + /* I2C0 base address */ +#define AM335X_I2C1_BASE 0x4802a000 + /* I2C1 base address */ +#define AM335X_I2C2_BASE 0x4819c000 + /* I2C2 base address */ +#define AM335X_I2C_REVNB_LO 0x00 + /* Module Revision Register (low bytes) */ +#define AM335X_I2C_REVNB_HI 0x04 + /* Module Revision Register (high bytes) */ +#define AM335X_I2C_SYSC 0x10 + /* System Configuration Register */ +#define AM335X_I2C_IRQSTATUS_RAW 0x24 + /* I2C Status Raw Register */ +#define AM335X_I2C_IRQSTATUS 0x28 + /* I2C Status Register */ +#define AM335X_I2C_IRQENABLE_SET 0x2c + /* I2C Interrupt Enable Set Register */ +#define AM335X_I2C_IRQENABLE_CLR 0x30 + /* I2C Interrupt Enable Clear Register */ +#define AM335X_I2C_WE 0x34 + /* I2C Wakeup Enable Register */ +#define AM335X_I2C_DMARXENABLE_SET 0x38 + /* Receive DMA Enable Set Register */ +#define AM335X_I2C_DMATXENABLE_SET 0x3c + /* Transmit DMA Enable Set Register */ +#define AM335X_I2C_DMARXENABLE_CLR 0x40 + /* Receive DMA Enable Clear Register */ +#define AM335X_I2C_DMATXENABLE_CLR 0x44 + /* Transmit DMA Enable Clear Register */ +#define AM335X_I2C_DMARXWAKE_EN 0x48 + /* Receive DMA Wakeup Register */ +#define AM335X_I2C_DMATXWAKE_EN 0x4c + /* Transmit DMA Wakeup Register */ +#define AM335X_I2C_SYSS 0x90 + /* System Status Register */ +#define AM335X_I2C_BUF 0x94 + /* Buffer Configuration Register */ +#define AM335X_I2C_CNT 0x98 + /* Data Counter Register */ +#define AM335X_I2C_DATA 0x9c + /* Data Access Register */ +#define AM335X_I2C_CON 0xa4 + /* I2C Configuration Register */ +#define AM335X_I2C_OA 0xa8 + /* I2C Own Address Register */ +#define AM335X_I2C_SA 0xac + /* I2C Slave Address Register */ +#define AM335X_I2C_PSC 0xb0 + /* I2C Clock Prescaler Register */ +#define AM335X_I2C_SCLL 0xb4 + /* I2C SCL Low Time Register */ +#define AM335X_I2C_SCLH 0xb8 + /* I2C SCL High Time Register */ +#define AM335X_I2C_SYSTEST 0xbc + /* System Test Register */ +#define AM335X_I2C_BUFSTAT 0xc0 + /* I2C Buffer Status Register */ +#define AM335X_I2C_OA1 0xc4 + /* I2C Own Address 1 Register */ +#define AM335X_I2C_OA2 0xc8 + /* I2C Own Address 2 Register */ +#define AM335X_I2C_OA3 0xcc + /* I2C Own Address 3 Register */ +#define AM335X_I2C_ACTOA 0xd0 + /* Active Own Address Register */ +#define AM335X_I2C_SBLOCK 0xd4 + /* I2C Clock Blocking Enable Register */ + +#define AM335X_CM_PER_L4LS_CLKSTCTRL (0x0) +#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) +#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL (0x00000003u) +#define AM335X_CM_PER_L4LS_CLKCTRL (0x60) +#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_I2C1_CLKCTRL (0x48) +#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_I2C2_CLKCTRL (0x44) +#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u) +#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u) +#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_I2C_CON_XSA (0x00000100u) +#define AM335X_I2C_CFG_10BIT_SLAVE_ADDR AM335X_I2C_CON_XSA +#define AM335X_I2C_CON_XSA_SHIFT (0x00000008u) +#define AM335X_I2C_CFG_7BIT_SLAVE_ADDR (0 << AM335X_I2C_CON_XSA_SHIFT) +#define AM335X_I2C_CON_I2C_EN (0x00008000u) +#define AM335X_I2C_CON_TRX (0x00000200u) +#define AM335X_I2C_CON_MST (0x00000400u) +#define AM335X_I2C_CON_STB (0x00000800u) +#define AM335X_I2C_SYSC_AUTOIDLE (0x00000001u) + +/*I2C0 module clock registers*/ + +#define AM335X_CM_WKUP_CONTROL_CLKCTRL (0x4) +#define AM335X_CM_WKUP_CLKSTCTRL (0x0) +#define AM335X_CM_WKUP_I2C0_CLKCTRL (0xb8) +#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC (0x0u) +#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST (0x00030000u) +#define AM335X_CM_WKUP_CLKSTCTRL_CLKACTIVITY_I2C0_GFCLK (0x00000800u) +#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_FUNC (0x0u) +#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST (0x00030000u) +#define AM335X_SOC_CM_WKUP_REGS (AM335X_CM_PER_ADDR + 0x400) + +/* I2C status Register */ +#define AM335X_I2C_IRQSTATUS_NACK (1 << 1) +#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11) +#define AM335X_I2C_IRQSTATUS_AL (1<<0) +#define AM335X_I2C_IRQSTATUS_ARDY (1 << 2) +#define AM335X_I2C_IRQSTATUS_RRDY (1 << 3) +#define AM335X_I2C_IRQSTATUS_XRDY (1 << 4) +#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10) +#define AM335X_I2C_BUF_TXFIFO_CLR (0x00000040u) +#define AM335X_I2C_BUF_RXFIFO_CLR (0x00004000u) +#define AM335X_I2C_IRQSTATUS_AAS (1 << 9) +#define AM335X_I2C_IRQSTATUS_BF (1 << 8) +#define AM335X_I2C_IRQSTATUS_STC (1 << 6) +#define AM335X_I2C_IRQSTATUS_GC (1 << 5) +#define AM335X_I2C_IRQSTATUS_XDR (1 << 14) +#define AM335X_I2C_IRQSTATUS_RDR (1 << 13) + +#define AM335X_I2C_INT_RECV_READY AM335X_I2C_IRQSTATUS_RRDY +#define AM335X_I2C_CON_STOP (0x00000002u) +#define AM335X_I2C_CON_START (0x00000001u) +#define AM335X_I2C_CFG_MST_RX AM335X_I2C_CON_MST +#define AM335X_I2C_CFG_MST_TX (AM335X_I2C_CON_TRX | AM335X_I2C_CON_MST) +#define AM335X_I2C_IRQSTATUS_RAW_BB (0x00001000u) +#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u) +#define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF + +#endif diff --git a/bsps/arm/include/libcpu/mmu.h b/bsps/arm/include/libcpu/mmu.h new file mode 100644 index 0000000000..b82e838695 --- /dev/null +++ b/bsps/arm/include/libcpu/mmu.h @@ -0,0 +1,32 @@ +/* + * ARM MMU header file + */ + +/* + * Copyright (c) 2004 by Cogent Computer Systems + * Written by Jay Monkman + */ + +#ifndef __LIBCPU_MMU_H__ +#define __LIBCPU_MMU_H__ + +#include + +#define MMU_SECT_SIZE 0x100000 + +#define MMU_CACHE_NONE 0x0 +#define MMU_CACHE_BUFFERED 0x1 +#define MMU_CACHE_WTHROUGH 0x2 +#define MMU_CACHE_WBACK 0x3 + +typedef struct { + uint32_t paddr; + uint32_t vaddr; + uint32_t size; /* in MB */ + uint8_t cache_flags; +} mmu_sect_map_t; + +void mmu_init(mmu_sect_map_t *map); +void mmu_set_cpu_async_mode(void); + +#endif /* __MMU_H__ */ diff --git a/bsps/arm/include/libcpu/omap3.h b/bsps/arm/include/libcpu/omap3.h new file mode 100644 index 0000000000..0cc43d6383 --- /dev/null +++ b/bsps/arm/include/libcpu/omap3.h @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2012 Claas Ziemke. All rights reserved. + * + * Claas Ziemke + * Kernerstrasse 11 + * 70182 Stuttgart + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified by Ben Gras to add lots + * of beagleboard/beaglebone definitions, delete lpc32xx specific + * ones, and merge with some other header files. + */ + +/* Interrupt controller memory map */ +#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */ + +/* Interrupt controller memory map */ +#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */ + +/* Interrupt controller registers */ +#define OMAP3_INTCPS_REVISION 0x000 /* IP revision code */ +#define OMAP3_INTCPS_SYSCONFIG 0x010 /* Controls params */ +#define OMAP3_INTCPS_SYSSTATUS 0x014 /* Status */ +#define OMAP3_INTCPS_SIR_IRQ 0x040 /* Active IRQ number */ +#define OMAP3_INTCPS_SIR_FIQ 0x044 /* Active FIQ number */ +#define OMAP3_INTCPS_CONTROL 0x048 /* New int agreement bits */ +#define OMAP3_INTCPS_PROTECTION 0x04C /* Protection for other regs */ +#define OMAP3_INTCPS_IDLE 0x050 /* Clock auto-idle/gating */ +#define OMAP3_INTCPS_IRQ_PRIORITY 0x060 /* Active IRQ priority level */ +#define OMAP3_INTCPS_FIQ_PRIORITY 0x064 /* Active FIQ priority level */ +#define OMAP3_INTCPS_THRESHOLD 0x068 /* Priority threshold */ +#define OMAP3_INTCPS_ITR0 0x080 /* Raw pre-masking interrupt status */ +#define OMAP3_INTCPS_MIR0 0x084 /* Interrupt mask */ +#define OMAP3_INTCPS_MIR1 0x0A4 /* Interrupt mask */ +#define OMAP3_INTCPS_MIR2 0x0C4 /* Interrupt mask */ +#define OMAP3_INTCPS_MIR3 0x0E4 /* Interrupt mask */ +#define OMAP3_INTCPS_MIR_CLEAR0 0x088 /* Clear interrupt mask bits */ +#define OMAP3_INTCPS_MIR_SET0 0x08C /* Set interrupt mask bits */ +#define OMAP3_INTCPS_ISR_SET0 0x090 /* Set software int bits */ +#define OMAP3_INTCPS_ISR_CLEAR0 0x094 /* Clear software int bits */ +#define OMAP3_INTCPS_PENDING_IRQ0 0x098 /* IRQ status post-masking */ +#define OMAP3_INTCPS_PENDING_IRQ1 0x0b8 /* IRQ status post-masking */ +#define OMAP3_INTCPS_PENDING_IRQ2 0x0d8 /* IRQ status post-masking */ +#define OMAP3_INTCPS_PENDING_IRQ3 0x0f8 /* IRQ status post-masking */ +#define OMAP3_INTCPS_PENDING_FIQ0 0x09C /* FIQ status post-masking */ +#define OMAP3_INTCPS_ILR0 0x100 /* Priority for interrupts */ + +/* SYSCONFIG */ +#define OMAP3_SYSCONFIG_AUTOIDLE 0x01 /* SYSCONFIG.AUTOIDLE bit */ + +#define OMAP3_INTR_ITR(base,n) \ + (base + OMAP3_INTCPS_ITR0 + 0x20 * (n)) +#define OMAP3_INTR_MIR(base,n) \ + (base + OMAP3_INTCPS_MIR0 + 0x20 * (n)) +#define OMAP3_INTR_MIR_CLEAR(base,n) \ + (base + OMAP3_INTCPS_MIR_CLEAR0 + 0x20 * (n)) +#define OMAP3_INTR_MIR_SET(base,n) \ + (base + OMAP3_INTCPS_MIR_SET0 + 0x20 * (n)) +#define OMAP3_INTR_ISR_SET(base,n) \ + (base + OMAP3_INTCPS_ISR_SET0 + 0x20 * (n)) +#define OMAP3_INTR_ISR_CLEAR(base,n) \ + (base + OMAP3_INTCPS_ISR_CLEAR0 + 0x20 * (n)) +#define OMAP3_INTR_PENDING_IRQ(base,n) \ + (base + OMAP3_INTCPS_PENDING_IRQ0 + 0x20 * (n)) +#define OMAP3_INTR_PENDING_FIQ(base,n) \ + (base + OMAP3_INTCPS_PENDING_FIQ0 + 0x20 * (n)) +#define OMAP3_INTR_ILR(base,m) \ + (base + OMAP3_INTCPS_ILR0 + 0x4 * (m)) + +#define OMAP3_INTR_SPURIOUSIRQ_MASK (0x1FFFFFF << 7) /* Spurious IRQ mask for SIR_IRQ */ +#define OMAP3_INTR_ACTIVEIRQ_MASK 0x7F /* Active IRQ mask for SIR_IRQ */ +#define OMAP3_INTR_NEWIRQAGR 0x1 /* New IRQ Generation */ + +#define OMAP3_DM337X_NR_IRQ_VECTORS 96 + +/* Interrupt mappings */ +#define OMAP3_MCBSP2_ST_IRQ 4 /* Sidestone McBSP2 overflow */ +#define OMAP3_MCBSP3_ST_IRQ 5 /* Sidestone McBSP3 overflow */ +#define OMAP3_SYS_NIRQ 7 /* External source (active low) */ +#define OMAP3_SMX_DBG_IRQ 9 /* L3 interconnect error for debug */ +#define OMAP3_SMX_APP_IRQ 10 /* L3 interconnect error for application */ +#define OMAP3_PRCM_IRQ 11 /* PRCM module */ +#define OMAP3_SDMA0_IRQ 12 /* System DMA request 0 */ +#define OMAP3_SDMA1_IRQ 13 /* System DMA request 1 */ +#define OMAP3_SDMA2_IRQ 14 /* System DMA request 2 */ +#define OMAP3_SDMA3_IRQ 15 /* System DMA request 3 */ +#define OMAP3_MCBSP1_IRQ 16 /* McBSP module 1 */ +#define OMAP3_MCBSP2_IRQ 17 /* McBSP module 2 */ +#define OMAP3_GPMC_IRQ 20 /* General-purpose memory controller */ +#define OMAP3_SGX_IRQ 21 /* 2D/3D graphics module */ +#define OMAP3_MCBSP3_IRQ 22 /* McBSP module 3 */ +#define OMAP3_MCBSP4_IRQ 23 /* McBSP module 4 */ +#define OMAP3_CAM0_IRQ 24 /* Camera interface request 0 */ +#define OMAP3_DSS_IRQ 25 /* Display subsystem module */ +#define OMAP3_MAIL_U0_IRQ 26 /* Mailbox user 0 request */ +#define OMAP3_MCBSP5_IRQ 27 /* McBSP module 5 */ +#define OMAP3_IVA2_MMU_IRQ 28 /* IVA2 MMU */ +#define OMAP3_GPIO1_IRQ 29 /* GPIO module 1 */ +#define OMAP3_GPIO2_IRQ 30 /* GPIO module 2 */ +#define OMAP3_GPIO3_IRQ 31 /* GPIO module 3 */ +#define OMAP3_GPIO4_IRQ 32 /* GPIO module 4 */ +#define OMAP3_GPIO5_IRQ 33 /* GPIO module 5 */ +#define OMAP3_GPIO6_IRQ 34 /* GPIO module 6 */ +#define OMAP3_WDT3_IRQ 36 /* Watchdog timer module 3 overflow */ +#define OMAP3_GPT1_IRQ 37 /* General-purpose timer module 1 */ +#define OMAP3_GPT2_IRQ 38 /* General-purpose timer module 2 */ +#define OMAP3_GPT3_IRQ 39 /* General-purpose timer module 3 */ +#define OMAP3_GPT4_IRQ 40 /* General-purpose timer module 4 */ +#define OMAP3_GPT5_IRQ 41 /* General-purpose timer module 5 */ +#define OMAP3_GPT6_IRQ 42 /* General-purpose timer module 6 */ +#define OMAP3_GPT7_IRQ 43 /* General-purpose timer module 7 */ +#define OMAP3_GPT8_IRQ 44 /* General-purpose timer module 8 */ +#define OMAP3_GPT9_IRQ 45 /* General-purpose timer module 9 */ +#define OMAP3_GPT10_IRQ 46 /* General-purpose timer module 10 */ +#define OMAP3_GPT11_IRQ 47 /* General-purpose timer module 11 */ +#define OMAP3_SPI4_IRQ 48 /* McSPI module 4 */ +#define OMAP3_MCBSP4_TX_IRQ 54 /* McBSP module 4 transmit */ +#define OMAP3_MCBSP4_RX_IRQ 55 /* McBSP module 4 receive */ +#define OMAP3_I2C1_IRQ 56 /* I2C module 1 */ +#define OMAP3_I2C2_IRQ 57 /* I2C module 2 */ +#define OMAP3_HDQ_IRQ 58 /* HDQ/1-Wire */ +#define OMAP3_MCBSP1_TX_IRQ 59 /* McBSP module 1 transmit */ +#define OMAP3_MCBSP1_RX_IRQ 60 /* McBSP module 1 receive */ +#define OMAP3_I2C3_IRQ 61 /* I2C module 3 */ +#define OMAP3_MCBSP2_TX_IRQ 62 /* McBSP module 2 transmit */ +#define OMAP3_MCBSP2_RX_IRQ 63 /* McBSP module 2 receive */ +#define OMAP3_SPI1_IRQ 65 /* McSPI module 1 */ +#define OMAP3_SPI2_IRQ 66 /* McSPI module 2 */ +#define OMAP3_UART1_IRQ 72 /* UART module 1 */ +#define OMAP3_UART2_IRQ 73 /* UART module 2 */ +#define OMAP3_UART3_IRQ 74 /* UART module 3 */ +#define OMAP3_PBIAS_IRQ 75 /* Merged interrupt for PBIASlite 1/2 */ +#define OMAP3_OHCI_IRQ 76 /* OHCI HSUSB MP Host Interrupt */ +#define OMAP3_EHCI_IRQ 77 /* EHCI HSUSB MP Host Interrupt */ +#define OMAP3_TLL_IRQ 78 /* HSUSB MP TLL Interrupt */ +#define OMAP3_MCBSP5_TX_IRQ 81 /* McBSP module 5 transmit */ +#define OMAP3_MCBSP5_RX_IRQ 82 /* McBSP module 5 receive */ +#define OMAP3_MMC1_IRQ 83 /* MMC/SD module 1 */ +#define OMAP3_MMC2_IRQ 86 /* MMC/SD module 2 */ +#define OMAP3_ICR_IRQ 87 /* MPU ICR */ +#define OMAP3_D2DFRINT_IRQ 88 /* 3G coproc (in stacked modem config) */ +#define OMAP3_MCBSP3_TX_IRQ 89 /* McBSP module 3 transmit */ +#define OMAP3_MCBSP3_RX_IRQ 90 /* McBSP module 3 receive */ +#define OMAP3_SPI3_IRQ 91 /* McSPI module 3 */ +#define OMAP3_HSUSB_MC_IRQ 92 /* High-speed USB OTG */ +#define OMAP3_HSUSB_DMA_IRQ 93 /* High-speed USB OTG DMA */ +#define OMAP3_MMC3_IRQ 94 /* MMC/SD module 3 */ + +/* General-purpose timer register map */ +#define OMAP3_GPTIMER1_BASE 0x48318000 + /* GPTIMER1 physical address */ +#define OMAP3_GPTIMER2_BASE 0x49032000 + /* GPTIMER2 physical address */ +#define OMAP3_GPTIMER3_BASE 0x49034000 + /* GPTIMER3 physical address */ +#define OMAP3_GPTIMER4_BASE 0x49036000 + /* GPTIMER4 physical address */ +#define OMAP3_GPTIMER5_BASE 0x49038000 + /* GPTIMER5 physical address */ +#define OMAP3_GPTIMER6_BASE 0x4903A000 + /* GPTIMER6 physical address */ +#define OMAP3_GPTIMER7_BASE 0x4903C000 + /* GPTIMER7 physical address */ +#define OMAP3_GPTIMER8_BASE 0x4903E000 + /* GPTIMER8 physical address */ +#define OMAP3_GPTIMER9_BASE 0x49040000 + /* GPTIMER9 physical address */ +#define OMAP3_GPTIMER10_BASE 0x48086000 + /* GPTIMER10 physical address */ +#define OMAP3_GPTIMER11_BASE 0x48088000 + /* GPTIMER11 physical address */ + + +/* General-purpose timer registers */ +#define OMAP3_TIMER_TIDR 0x000 + /* IP revision code */ +#define OMAP3_TIMER_TIOCP_CFG 0x010 + /* Controls params for GP timer L4 iface */ +#define OMAP3_TIMER_TISTAT 0x014 + /* Status (excl. interrupt status) */ +#define OMAP3_TIMER_TISR 0x018 + /* Pending interrupt status */ +#define OMAP3_TIMER_TIER 0x01C + /* Interrupt enable */ +#define OMAP3_TIMER_TWER 0x020 + /* Wakeup enable */ +#define OMAP3_TIMER_TCLR 0x024 + /* Controls optional features */ +#define OMAP3_TIMER_TCRR 0x028 + /* Internal counter value */ +#define OMAP3_TIMER_TLDR 0x02C + /* Timer load value */ +#define OMAP3_TIMER_TTGR 0x030 + /* Triggers counter reload */ +#define OMAP3_TIMER_TWPS 0x034 + /* Indicates if Write-Posted pending */ +#define OMAP3_TIMER_TMAR 0x038 + /* Value to be compared with counter */ +#define OMAP3_TIMER_TCAR1 0x03C + /* First captured value of counter reg */ +#define OMAP3_TIMER_TSICR 0x040 + /* Control posted mode and functional SW rst */ +#define OMAP3_TIMER_TCAR2 0x044 + /* Second captured value of counter register */ +#define OMAP3_TIMER_TPIR 0x048 + /* Positive increment (1 ms tick) */ +#define OMAP3_TIMER_TNIR 0x04C + /* Negative increment (1 ms tick) */ +#define OMAP3_TIMER_TCVR 0x050 + /* Defines TCRR is sub/over-period (1 ms tick) */ +#define OMAP3_TIMER_TOCR 0x054 + /* Masks tick interrupt */ +#define OMAP3_TIMER_TOWR 0x058 + /* Number of masked overflow interrupts */ + +/* Interrupt status register fields */ +#define OMAP3_TISR_MAT_IT_FLAG (1 << 0) /* Pending match interrupt status */ +#define OMAP3_TISR_OVF_IT_FLAG (1 << 1) /* Pending overflow interrupt status */ +#define OMAP3_TISR_TCAR_IT_FLAG (1 << 2) /* Pending capture interrupt status */ + +/* Interrupt enable register fields */ +#define OMAP3_TIER_MAT_IT_ENA (1 << 0) /* Enable match interrupt */ +#define OMAP3_TIER_OVF_IT_ENA (1 << 1) /* Enable overflow interrupt */ +#define OMAP3_TIER_TCAR_IT_ENA (1 << 2) /* Enable capture interrupt */ + +/* Timer control fields */ +#define OMAP3_TCLR_ST (1 << 0) /* Start/stop timer */ +#define OMAP3_TCLR_AR (1 << 1) /* Autoreload or one-shot mode */ +#define OMAP3_TCLR_PRE (1 << 5) /* Prescaler on */ +#define OMAP3_TCLR_PTV (1 << 1) /* looks like "bleed" from Minix */ +#define OMAP3_TCLR_OVF_TRG (1 << 10) /* Overflow trigger */ + + +#define OMAP3_CM_CLKSEL_GFX 0x48004b40 +#define OMAP3_CM_CLKEN_PLL 0x48004d00 +#define OMAP3_CM_FCLKEN1_CORE 0x48004A00 +#define OMAP3_CM_CLKSEL_CORE 0x48004A40 /* GPT10 src clock sel. */ +#define OMAP3_CM_FCLKEN_PER 0x48005000 +#define OMAP3_CM_CLKSEL_PER 0x48005040 +#define OMAP3_CM_CLKSEL_WKUP 0x48004c40 /* GPT1 source clock selection */ + + +#define CM_MODULEMODE_MASK (0x3 << 0) +#define CM_MODULEMODE_ENABLE (0x2 << 0) +#define CM_MODULEMODE_DISABLED (0x0 << 0) + +#define CM_CLKCTRL_IDLEST (0x3 << 16) +#define CM_CLKCTRL_IDLEST_FUNC (0x0 << 16) +#define CM_CLKCTRL_IDLEST_TRANS (0x1 << 16) +#define CM_CLKCTRL_IDLEST_IDLE (0x2 << 16) +#define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16) + +#define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */ + +#define CM_WKUP_TIMER1_CLKCTRL (CM_WKUP_BASE + 0xC4) + /* This register manages the TIMER1 clocks. [Memory Mapped] */ + +#define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */ +#define CM_PER_TIMER7_CLKCTRL (CM_PER_BASE + 0x7C) + /* This register manages the TIMER7 clocks. [Memory Mapped] */ + +/* CM_DPLL registers */ + +#define CM_DPLL_BASE 0x44E00500 /* Clock Module PLL Registers */ + +#define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28) + +#define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0) +#define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0) + /* Select CLK_M_OSC clock */ +#define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0) + /* Select CLK_32KHZ clock */ +#define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0) + /* Select TCLKIN clock */ +#define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0) + /* Select CLK_RC32K clock */ +#define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0) + /* Selects the CLK_32768 from 32KHz Crystal Osc */ + +#define CLKSEL_TIMER7_CLK (CM_DPLL_BASE + 0x04) +#define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0) +#define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */ +#define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */ +#define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */ +#define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */ + +/*RTC CLOCK BASE & Registers*/ +#define CM_RTC_BASE 0x44E00800 +#define CM_RTC_RTC_CLKCTRL 0x0 +#define CM_RTC_CLKSTCTRL 0x4 + + +#define OMAP3_CLKSEL_GPT1 (1 << 0) +#define OMAP3_CLKSEL_GPT10 (1 << 6) +#define OMAP3_CLKSEL_GPT11 (1 << 7) + +#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 + +#define ARM_TTBR_ADDR_MASK (0xffffc000) +#define ARM_TTBR_OUTER_NC (0x0 << 3) /* Non-cacheable*/ +#define ARM_TTBR_OUTER_WBWA (0x1 << 3) /* Outer Write-Back */ +#define ARM_TTBR_OUTER_WT (0x2 << 3) /* Outer Write-Through */ +#define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back */ +#define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA + +/* cpu control flags */ +/* CPU control register (CP15 register 1) */ +#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ +#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ +#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ +#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ +#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ +#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ +#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ +#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ +#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ +#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ +#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ +#define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */ +#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ +#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ +#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ +#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ +#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ +#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ +#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ +#define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ +#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ +#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ +#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ +#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ +#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ +#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ + +#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE + +/* VM bits */ + +/* Big page (1MB section) specific flags. */ +#define ARM_VM_SECTION (1 << 1) + /* 1MB section */ +#define ARM_VM_SECTION_PRESENT (1 << 1) + /* Section is present */ +#define ARM_VM_SECTION_B (1 << 2) + /* B Bit */ +#define ARM_VM_SECTION_C (1 << 3) + /* C Bit */ +#define ARM_VM_SECTION_DOMAIN (0xF << 5) + /* Domain Number */ +#define ARM_VM_SECTION_SUPER (0x1 << 10) + /* Super access only AP[1:0] */ +#define ARM_VM_SECTION_USER (0x3 << 10) + /* Super/User access AP[1:0] */ +#define ARM_VM_SECTION_TEX0 (1 << 12) + /* TEX[0] */ +#define ARM_VM_SECTION_TEX1 (1 << 13) + /* TEX[1] */ +#define ARM_VM_SECTION_TEX2 (1 << 14) + /* TEX[2] */ +#define ARM_VM_SECTION_RO (1 << 15) + /* Read only access AP[2] */ +#define ARM_VM_SECTION_SHAREABLE (1 << 16) + /* Shareable */ +#define ARM_VM_SECTION_NOTGLOBAL (1 << 17) + /* Not Global */ + +#define ARM_VM_SECTION_WB \ + (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B ) +/* inner and outer write-back, write-allocate */ +#define ARM_VM_SECTION_WT \ + (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C ) +/* inner and outer write-through, no write-allocate */ +#define ARM_VM_SECTION_WTWB \ + (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C ) +/* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */ + +/* shareable device */ +#define ARM_VM_SECTION_CACHED ARM_VM_SECTION_WTWB +#define ARM_VM_SECTION_DEVICE (ARM_VM_SECTION_B) diff --git a/bsps/arm/include/libcpu/omap_timer.h b/bsps/arm/include/libcpu/omap_timer.h new file mode 100644 index 0000000000..ef8787a571 --- /dev/null +++ b/bsps/arm/include/libcpu/omap_timer.h @@ -0,0 +1,39 @@ +/** + * @file + * + * @brief Clock driver configuration. + */ + +#include + +typedef struct omap_timer_registers +{ + uint32_t TIDR; + uint32_t TIOCP_CFG; + uint32_t TISTAT; + uint32_t TISR; + uint32_t TIER; + uint32_t TWER; + uint32_t TCLR; + uint32_t TCRR; + uint32_t TLDR; + uint32_t TTGR; + uint32_t TWPS; + uint32_t TMAR; + uint32_t TCAR1; + uint32_t TSICR; + uint32_t TCAR2; + uint32_t TPIR; + uint32_t TNIR; + uint32_t TCVR; + uint32_t TOCR; + uint32_t TOWR; + +} omap_timer_registers_t; + +typedef struct omap_timer +{ + uint32_t base; + int irq_nr; + struct omap_timer_registers *regs; +} omap_timer_t; diff --git a/bsps/arm/include/uart.h b/bsps/arm/include/uart.h new file mode 100644 index 0000000000..742c56bda3 --- /dev/null +++ b/bsps/arm/include/uart.h @@ -0,0 +1,163 @@ +/** + * @file + * + * @ingroup arm_comm + * + * @brief UART Support + */ + +/* + * This software is Copyright (C) 1998 by T.sqware - all rights limited + * It is provided in to the public domain "as is", can be freely modified + * as far as this copyight notice is kept unchanged, but does not imply + * an endorsement by T.sqware of the product in which it is included. + * + * Copyright (c) Canon Research France SA.] + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _BSPUART_H +#define _BSPUART_H + +#include + +void BSP_uart_init(int uart, int baud, int hwFlow); +void BSP_uart_set_baud(int aurt, int baud); +void BSP_uart_intr_ctrl(int uart, int cmd); +void BSP_uart_throttle(int uart); +void BSP_uart_unthrottle(int uart); +int BSP_uart_polled_status(int uart); +void BSP_uart_polled_write(int uart, int val); +int BSP_uart_polled_read(int uart); +void BSP_uart_termios_set(int uart, void *ttyp); +int BSP_uart_termios_write_com1(int minor, const char *buf, int len); +int BSP_uart_termios_write_com2(int minor, const char *buf, int len); +void BSP_uart_termios_isr_com1(); +void BSP_uart_termios_isr_com2(); +void BSP_uart_dbgisr_com1(void); +void BSP_uart_dbgisr_com2(void); +extern unsigned BSP_poll_char_via_serial(void); +extern void BSP_output_char_via_serial(int val); +extern int BSPConsolePort; +extern int BSPBaseBaud; +/* + * Command values for BSP_uart_intr_ctrl(), + * values are strange in order to catch errors + * with assert + */ +#define BSP_UART_INTR_CTRL_DISABLE (0) +#define BSP_UART_INTR_CTRL_GDB (0xaa) /* RX only */ +#define BSP_UART_INTR_CTRL_ENABLE (0xbb) /* Normal operations */ +#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) /* RX & line status */ + +/* Return values for uart_polled_status() */ +#define BSP_UART_STATUS_ERROR (-1) /* No character */ +#define BSP_UART_STATUS_NOCHAR (0) /* No character */ +#define BSP_UART_STATUS_CHAR (1) /* Character present */ +#define BSP_UART_STATUS_BREAK (2) /* Break point is detected */ + +/* PC UART definitions */ +#define BSP_UART_COM1 (0) +#define BSP_UART_COM2 (1) + +/* + * Base IO for UART + */ + +#define COM1_BASE_IO 0x3F8 +#define COM2_BASE_IO 0x2F8 + +/* + * Offsets from base + */ + +/* DLAB 0 */ +#define RBR RSRBR /* Rx Buffer Register (read) */ +#define THR RSTHR /* Tx Buffer Register (write) */ +#define IER RSIER /* Interrupt Enable Register */ + +/* DLAB X */ +#define IIR RSIIR /* Interrupt Ident Register (read) */ +#define FCR RSFCR /* FIFO Control Register (write) */ +#define LCR RSLCR /* Line Control Register */ +#define LSR RSLSR /* Line Status Register */ + +/* DLAB 1 */ +#define DLL RSDLL /* Divisor Latch, LSB */ +#define DLM RSDLH /* Divisor Latch, MSB */ + +/* Uart control */ +#define CNT RSCNT /* General Control register */ + +/* + * define bit for CNT + */ +#define UART_ENABLE 1 +#define PAD_ENABLE 2 + +/* + * Interrupt source definition via IIR + */ +#define NO_MORE_INTR 1 +#define TRANSMITTER_HODING_REGISTER_EMPTY 2 +#define RECEIVER_DATA_AVAIL 4 +#define RECEIVER_ERROR 6 +#define CHARACTER_TIMEOUT_INDICATION 12 + +/* + * Bits definition of IER + */ +#define RECEIVE_ENABLE 0x1 +#define TRANSMIT_ENABLE 0x2 +#define RECEIVER_LINE_ST_ENABLE 0x4 +#define INTERRUPT_DISABLE 0x0 + +/* + * Bits definition of the Line Status Register (LSR) + */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* Transmitter Holding Register Empty */ +#define TEMT 0x40 /* Transmitter Empty */ +#define ERFIFO 0x80 /* Error receive Fifo */ + +/* + * Bits definition of the Line Control Register (LCR) + */ +#define CHR_5_BITS 0 +#define CHR_6_BITS 1 +#define CHR_7_BITS 2 +#define CHR_8_BITS 3 + +#define WL 0x03 /* Word length mask */ +#define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */ +#define PEN 0x08 /* Parity Enabled */ +#define EPS 0x10 /* Even Parity Select, otherwise Odd */ +#define SP 0x20 /* Stick Parity */ +#define BCB 0x40 /* Break Control Bit */ +#define DLAB 0x80 /* Enable Divisor Latch Access */ + +/* + * Bits definition of the FIFO Control Register : WD16C552 or NS16550 + */ + +#define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */ +#define FIFO_EN 0x01 /* Enable the FIFO */ +#define XMIT_RESET 0x04 /* Transmit FIFO Reset */ +#define RCV_RESET 0x02 /* Receive FIFO Reset */ +#define FCR3 0x08 /* do not understand manual! */ + +#define RECEIVE_FIFO_TRIGGER1 0x0 /* trigger recieve interrupt after 1 byte */ +#define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger recieve interrupt after 4 byte */ +#define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger recieve interrupt after 8 byte */ +#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger recieve interrupt after 14 byte */ +#define TRIG_LEVEL 0xc0 /* Mask for the trigger level */ + +#endif /* _BSPUART_H */ diff --git a/bsps/arm/lm3s69xx/headers.am b/bsps/arm/lm3s69xx/headers.am new file mode 100644 index 0000000000..2572e1ab9c --- /dev/null +++ b/bsps/arm/lm3s69xx/headers.am @@ -0,0 +1,15 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp/io.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp/ssi.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp/syscon.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp/uart.h diff --git a/bsps/arm/lm3s69xx/include/bsp.h b/bsps/arm/lm3s69xx/include/bsp.h new file mode 100644 index 0000000000..b07656cb73 --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp.h @@ -0,0 +1,52 @@ +/** + * @file + * + * @ingroup arm_lm3s69xx + * + * @brief Global BSP Definitions + */ + +/* + * Copyright (c) 2011-2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LM3S69XX_BSP_H +#define LIBBSP_ARM_LM3S69XX_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (5 << 5) + +#define BSP_ARMV7M_SYSTICK_PRIORITY (6 << 5) + +#define BSP_ARMV7M_SYSTICK_FREQUENCY LM3S69XX_SYSTEM_CLOCK + +#ifndef ASM + +#include + +#include + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_LM3S69XX_BSP_H */ + +/** + * @defgroup arm_lm3s69xx LM3S69XX Support + * + * @ingroup bsp_arm + * + * @brief LM3S69XX Support Package + */ diff --git a/bsps/arm/lm3s69xx/include/bsp/io.h b/bsps/arm/lm3s69xx/include/bsp/io.h new file mode 100644 index 0000000000..f9ddf4c8ee --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp/io.h @@ -0,0 +1,191 @@ +/** + * @file + * + * @ingroup lm3s69xx_io + * + * @brief IO definitions. + */ + +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LM3S69XX_IO_H +#define LIBBSP_ARM_LM3S69XX_IO_H +#include +#include + +/** + * @defgroup lm3s69xx_io IO Support + * + * @ingroup arm_lm3s69xx + * + * @brief IO support. + */ + +typedef enum { + LM3S69XX_GPIO_DIRECTION_INPUT, + LM3S69XX_GPIO_DIRECTION_OUTPUT +} lm3s69xx_gpio_direction; + +typedef enum { + LM3S69XX_GPIO_OTYPE_PUSH_PULL, + LM3S69XX_GPIO_OTYPE_OPEN_DRAIN +} lm3s69xx_gpio_otype; + +typedef enum { + LM3S69XX_GPIO_DRIVE_2MA, + LM3S69XX_GPIO_DRIVE_4MA, + LM3S69XX_GPIO_DRIVE_8MA +} lm3s69xx_gpio_drive; + +typedef enum { + LM3S69XX_GPIO_NO_PULL, + LM3S69XX_GPIO_PULL_UP, + LM3S69XX_GPIO_PULL_DOWN +} lm3s69xx_gpio_pull; + +typedef enum { + LM3S69XX_GPIO_DIGITAL_DISABLE, + LM3S69XX_GPIO_DIGITAL_ENABLE, +} lm3s69xx_gpio_digital; + +typedef enum { + LM3S69XX_GPIO_AF_DISABLE, + LM3S69XX_GPIO_AF_ENABLE +} lm3s69xx_gpio_af; + +typedef enum { + LM3S69XX_GPIO_ANALOG_DISABLE, + LM3S69XX_GPIO_ANALOG_ENABLE +} lm3s69xx_gpio_analog; + +typedef enum { + LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL, + LM3S69XX_GPIO_SLEW_RATE_CONTROL +} lm3s69xx_gpio_slew_rate_control; + +typedef struct { + unsigned int pin_first : 8; + unsigned int pin_last : 8; + unsigned int digital : 1; + unsigned int alternate : 1; + unsigned int analog : 1; + unsigned int dir : 1; + unsigned int otype : 1; + unsigned int drive : 2; + unsigned int pull : 2; + unsigned int slr : 1; +} lm3s69xx_gpio_config; + +typedef enum { + LM3S69XX_PORT_A, + LM3S69XX_PORT_B, + LM3S69XX_PORT_C, + LM3S69XX_PORT_D, + LM3S69XX_PORT_E, + LM3S69XX_PORT_F, + LM3S69XX_PORT_G, +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 + LM3S69XX_PORT_H +#endif +} lm3s69xx_gpio_port; + +#define LM3S69XX_GPIO_PIN(port, idx) (((port) << 3) | (idx)) +#define LM3S69XX_GPIO_PORT_OF_PIN(pin) (((pin) >> 3) & 0xf) +#define LM3S69XX_GPIO_INDEX_OF_PIN(pin) ((pin) & 0x7) + +#define LM3S69XX_PIN_UART_TX(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_ENABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_OUTPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_2MA, \ + .pull = LM3S69XX_GPIO_NO_PULL, \ + .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_UART_RX(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_ENABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_INPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_2MA, \ + .pull = LM3S69XX_GPIO_PULL_UP, \ + .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_UART_RTS(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_ENABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_OUTPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_2MA, \ + .pull = LM3S69XX_GPIO_NO_PULL, \ + .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_UART_CTS(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_ENABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_INPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_2MA, \ + .pull = LM3S69XX_GPIO_PULL_UP, \ + .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_LED(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_DISABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_OUTPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_8MA, \ + .pull = LM3S69XX_GPIO_NO_PULL, \ + .slr = LM3S69XX_GPIO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_SSI_TX(port, idx) LM3S69XX_PIN_UART_TX(port, idx) +#define LM3S69XX_PIN_SSI_RX(port, idx) LM3S69XX_PIN_UART_RX(port, idx) + +#ifdef __cplusplus +extern "C" { +#endif + +void lm3s69xx_gpio_set_config(const lm3s69xx_gpio_config *config); +void lm3s69xx_gpio_set_config_array(const lm3s69xx_gpio_config *configs, unsigned int count); +void lm3s69xx_gpio_digital_enable(unsigned int pin, bool enable); +void lm3s69xx_gpio_analog_mode_select(unsigned int pin, bool enable); + +void lm3s69xx_gpio_set_pin(unsigned int pin, bool set); +bool lm3s69xx_gpio_get_pin(unsigned int pin); + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_LM3S69XX_IO_H */ diff --git a/bsps/arm/lm3s69xx/include/bsp/irq.h b/bsps/arm/lm3s69xx/include/bsp/irq.h new file mode 100644 index 0000000000..0b380c2ce2 --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp/irq.h @@ -0,0 +1,107 @@ +/** + * @file + * + * @ingroup lm3s69xx_interrupt + * + * @brief Interrupt definitions. + */ + +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LM3S69XX_IRQ_H +#define LIBBSP_ARM_LM3S69XX_IRQ_H + +#ifndef ASM + +#include +#include +#include +#include + +/** + * @defgroup lm3s69xx_interrupt Interrupt Support + * + * @ingroup arm_lm3s69xx + * + * @brief Interrupt support. + */ + +#endif /* ASM */ + +#define LM3S69XX_IRQ_GPIO_PORT_A 0 +#define LM3S69XX_IRQ_GPIO_PORT_B 1 +#define LM3S69XX_IRQ_GPIO_PORT_C 2 +#define LM3S69XX_IRQ_GPIO_PORT_D 3 +#define LM3S69XX_IRQ_GPIO_PORT_E 4 +#define LM3S69XX_IRQ_UART_0 5 +#define LM3S69XX_IRQ_UART_1 6 +#define LM3S69XX_IRQ_SSI_0 7 +#define LM3S69XX_IRQ_I2C_0 8 +#define LM3S69XX_IRQ_PWM_FAULT 9 +#define LM3S69XX_IRQ_PWM_GENERATOR_0 10 +#define LM3S69XX_IRQ_PWM_GENERATOR_1 11 +#define LM3S69XX_IRQ_PWM_GENERATOR_2 12 +#define LM3S69XX_IRQ_QEI_0 13 +#define LM3S69XX_IRQ_ADC0_SEQUENCE_0 14 +#define LM3S69XX_IRQ_ADC0_SEQUENCE_1 15 +#define LM3S69XX_IRQ_ADC0_SEQUENCE_2 16 +#define LM3S69XX_IRQ_ADC0_SEQUENCE_3 17 +#define LM3S69XX_IRQ_WATCHDOG_TIMER_0 18 +#define LM3S69XX_IRQ_TIMER_0_A 19 +#define LM3S69XX_IRQ_TIMER_0_B 20 +#define LM3S69XX_IRQ_TIMER_1_A 21 +#define LM3S69XX_IRQ_TIMER_1_B 22 +#define LM3S69XX_IRQ_TIMER_2_A 23 +#define LM3S69XX_IRQ_TIMER_2_B 24 +#define LM3S69XX_IRQ_ANALOG_COMPARATOR_0 25 +#define LM3S69XX_IRQ_ANALOG_COMPARATOR_1 26 +#define LM3S69XX_IRQ_SYSTEM_CONTROL 28 +#define LM3S69XX_IRQ_FLASH_MEMORY_CONTROL 29 +#define LM3S69XX_IRQ_GPIO_PORT_F 30 +#define LM3S69XX_IRQ_GPIO_PORT_G 31 +/* NOTE: lm3s3749 */ +#define LM3S69XX_IRQ_GPIO_PORT_H 32 +#define LM3S69XX_IRQ_UART_2 33 +/* NOTE: lm3s3749 */ +#define LM3S69XX_IRQ_SSI_1 34 +#define LM3S69XX_IRQ_TIMER_3_A 35 +#define LM3S69XX_IRQ_TIMER_3_B 36 +#define LM3S69XX_IRQ_I2C_1 37 + +/* NOTE: lm3s6965 */ +#define LM3S69XX_IRQ_QEI_1 38 +#define LM3S69XX_IRQ_ETHERNET_CONTROLLER 42 + +#define LM3S69XX_IRQ_HIBERNATION_MODULE 43 + +/* NOTE: lm3s3749 */ +#define LM3S69XX_IRQ_USB 44 +#define LM3S69XX_IRQ_PWM_GENERATOR_3 45 +#define LM3S69XX_IRQ_UDMA_SOFTWARE 46 +#define LM3S69XX_IRQ_UDMA_ERROR 47 + +#define LM3S69XX_IRQ_PRIORITY_VALUE_MIN 0 +#define LM3S69XX_IRQ_PRIORITY_VALUE_MAX 7 +#define LM3S69XX_IRQ_PRIORITY_COUNT (LM3S69XX_IRQ_PRIORITY_VALUE_MAX + 1) +#define LM3S69XX_IRQ_PRIORITY_HIGHEST LM3S69XX_IRQ_PRIORITY_VALUE_MIN +#define LM3S69XX_IRQ_PRIORITY_LOWEST LM3S69XX_IRQ_PRIORITY_VALUE_MAX + +#define BSP_INTERRUPT_VECTOR_MIN 0 +/* NOTE: for lm3s6965 - 43 */ +#define BSP_INTERRUPT_VECTOR_MAX 47 + +#endif /* LIBBSP_ARM_LM3S69XX_IRQ_H */ diff --git a/bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h b/bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h new file mode 100644 index 0000000000..ce3548d376 --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h @@ -0,0 +1,407 @@ +/** + * @file + * + * @ingroup lm3s69xx_reg + * + * @brief Register definitions. + */ + +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LM3S69XX_LM3S69XX_H +#define LIBBSP_ARM_LM3S69XX_LM3S69XX_H +#include +#include + +/** + * @defgroup lm3s69xx_reg Register Definitions + * + * @ingroup arm_lm3s69xx + * + * @brief Register Definitions + */ + +#define LM3S69XX_SYSCON_BASE 0x400fe000 + +#define LM3S69XX_UART_0_BASE 0x4000c000 +#define LM3S69XX_UART_1_BASE 0x4000d000 +#define LM3S69XX_UART_2_BASE 0x4000e000 + +#ifdef LM3S69XX_USE_AHB_FOR_GPIO +#define LM3S69XX_GPIO_A_BASE 0x40058000 +#define LM3S69XX_GPIO_B_BASE 0x40059000 +#define LM3S69XX_GPIO_C_BASE 0x4005a000 +#define LM3S69XX_GPIO_D_BASE 0x4005b000 +#define LM3S69XX_GPIO_E_BASE 0x4005c000 +#define LM3S69XX_GPIO_F_BASE 0x4005d000 +#if LM3S69XX_NUM_GPIO_BLOCKS > 6 +#define LM3S69XX_GPIO_G_BASE 0x4005e000 +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 +#define LM3S69XX_GPIO_H_BASE 0x4005f000 +#endif +#endif + +#define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(LM3S69XX_GPIO_A_BASE + (port) * 0x1000)) +#else /* LM3S69XX_USE_AHB_FOR_GPIO */ +#define LM3S69XX_GPIO_A_BASE 0x40004000 +#define LM3S69XX_GPIO_B_BASE 0x40005000 +#define LM3S69XX_GPIO_C_BASE 0x40006000 +#define LM3S69XX_GPIO_D_BASE 0x40007000 +#define LM3S69XX_GPIO_E_BASE 0x40024000 +#define LM3S69XX_GPIO_F_BASE 0x40025000 +#if LM3S69XX_NUM_GPIO_BLOCKS > 6 +#define LM3S69XX_GPIO_G_BASE 0x40026000 +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 +#define LM3S69XX_GPIO_H_BASE 0x40027000 +#endif +#endif + +#define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(((port) < 4) ? \ + (LM3S69XX_GPIO_A_BASE + (port) * 0x1000) : \ + (LM3S69XX_GPIO_E_BASE + ((port) - 4) * 0x1000))) +#endif /* LM3S69XX_USE_AHB_FOR_GPIO */ + +#define LM3S69XX_SSI_0_BASE 0x40008000 +#if LM3S69XX_NUM_SSI_BLOCKS > 1 +#define LM3S69XX_SSI_1_BASE 0x40009000 +#if LM3S69XX_NUM_SSI_BLOCKS > 2 +#define LM3S69XX_SSI_2_BASE 0x4000A000 +#if LM3S69XX_NUM_SSI_BLOCKS > 3 +#define LM3S69XX_SSI_3_BASE 0x4000B000 +#endif +#endif +#endif + +#define LM3S69XX_SYSCON ((volatile lm3s69xx_syscon *)LM3S69XX_SYSCON_BASE) + +#define LM3S69XX_PLL_FREQUENCY 400000000U + +typedef struct { + uint32_t data[256]; /* Masked data registers are included here. */ + uint32_t dir; + uint32_t is; + uint32_t ibe; + uint32_t iev; + uint32_t im; + uint32_t ris; + uint32_t mis; + uint32_t icr; + uint32_t afsel; + + uint32_t reserved_0[55]; + + uint32_t dr2r; + uint32_t dr4r; + uint32_t dr8r; + uint32_t odr; + uint32_t pur; + uint32_t pdr; + uint32_t slr; + uint32_t den; + uint32_t lock; + uint32_t cr; + uint32_t amsel; +} lm3s69xx_gpio; + +typedef struct { + uint32_t did0; + uint32_t did1; + + uint32_t dc0; + uint32_t reserved_0; + uint32_t dc1; + uint32_t dc2; + uint32_t dc3; + uint32_t dc4; + uint32_t dc5; + uint32_t dc6; + uint32_t dc7; + + uint32_t reserved_1; + +#define SYSCONPBORCTL_BORIOR BSP_BIT32(1) + uint32_t pborctl; + +#define SYSCONLDOPCTL_VADJ(val) BSP_FLD32(val, 0, 5) +#define SYSCONLDOPCTL_VADJ_MASK BSP_MSK32(0, 5) + uint32_t ldopctl; + + uint32_t reserved_2[2]; + + uint32_t srcr0; + uint32_t srcr1; + uint32_t srcr2; + + uint32_t reserved_3; + +#define SYSCONRIS_MOSCPUPRIS BSP_BIT32(8) +#define SYSCONRIS_USBPLLRIS BSP_BIT32(7) +#define SYSCONRIS_PLLLRIS BSP_BIT32(6) +#define SYSCONRIS_BORRIS BSP_BIT32(1) + uint32_t ris; + +#define SYSCONIMC_MOSCPUPIM BSP_BIT32(8) +#define SYSCONIMC_USBPLLLIM BSP_BIT32(7) +#define SYSCONIMC_PLLLIM BSP_BIT32(6) +#define SYSCONIMC_BORIM BSP_BIT32(1) + uint32_t imc; + +#define SYSCONMISC_MOSCPUPMIS BSP_BIT32(8) +#define SYSCONMISC_USBPLLLMIS BSP_BIT32(7) +#define SYSCONMISC_PLLLMIS BSP_BIT32(6) +#define SYSCONMISC_BORMIS BSP_BIT32(1) + uint32_t misc; + +#define SYSCONRESC_MOSCFAIL BSP_BIT32(16) +#define SYSCONRESC_SW BSP_BIT32(4) +#define SYSCONRESC_WDT BSP_BIT32(3) +#define SYSCONRESC_BOR BSP_BIT32(2) +#define SYSCONRESC_POR BSP_BIT32(1) +#define SYSCONRESC_EXT BSP_BIT32(0) + uint32_t resc; + +#define SYSCONRCC_AGC BSP_BIT32(27) +#define SYSCONRCC_SYSDIV(val) BSP_FLD32(val, 23, 26) +#define SYSCONRCC_SYSDIV_MSK BSP_MSK32(23, 26) +#define SYSCONRCC_USESYSDIV BSP_BIT32(22) +#define SYSCONRCC_USEPWMDIV BSP_BIT32(20) +#define SYSCONRCC_PWMDIV(val) BSP_FLD32(val, 17, 19) +#define SYSCONRCC_PWMDIV_DIV2_VAL 0 +#define SYSCONRCC_PWMDIV_DIV4_VAL 1 +#define SYSCONRCC_PWMDIV_DIV8_VAL 2 +#define SYSCONRCC_PWMDIV_DIV16_VAL 3 +#define SYSCONRCC_PWMDIV_DIV32_VAL 4 +#define SYSCONRCC_PWMDIV_DIV64_VAL 5 +#define SYSCONRCC_PWMDIV_MSK BSP_MSK32(17, 19) +#define SYSCONRCC_PWRDN BSP_BIT32(13) +#define SYSCONRCC_BYPASS BSP_BIT32(11) +#define SYSCONRCC_XTAL(val) BSP_FLD32(val, 6, 10) +#define SYSCONRCC_XTAL_MSK BSP_MSK32(6, 10) +#define SYSCONRCC_OSCSRC(val) BSP_FLD32(val, 4, 5) +#define SYSCONRCC_OSCSRC_MOSC SYSCONRCC_OSCSRC(0x0) +#define SYSCONRCC_OSCSRC_IOSC SYSCONRCC_OSCSRC(0x1) +#define SYSCONRCC_OSCSRC_IOSC_DIV_4 SYSCONRCC_OSCSRC(0x2) +#define SYSCONRCC_OSCSRC_30KHZ SYSCONRCC_OSCSRC(0x3) +#define SYSCONRCC_OSCSRC_MSK BSP_MSK32(4, 5) +#define SYSCONRCC_IOSCDIS BSP_BIT32(1) +#define SYSCONRCC_MOSCDIS BSP_BIT32(0) + uint32_t rcc; + +#define SYSCONPLLCFG_F(val) BSP_FLD32(val, 5, 13) +#define SYSCONPLLCFG_F_MSK BSP_MSK32(5, 13) +#define SYSCONPLLCFG_R(val) BSP_FLD32(val, 0, 4) +#define SYSCONPLLCFG_R_MSK BSP_MSK32(0, 4) + uint32_t pllcfg; + + uint32_t reserved_4; + +#define SYSCONGPIOHBCTL_PORTH BSP_BIT32(7) +#define SYSCONGPIOHBCTL_PORTG BSP_BIT32(6) +#define SYSCONGPIOHBCTL_PORTF BSP_BIT32(5) +#define SYSCONGPIOHBCTL_PORTE BSP_BIT32(4) +#define SYSCONGPIOHBCTL_PORTD BSP_BIT32(3) +#define SYSCONGPIOHBCTL_PORTC BSP_BIT32(2) +#define SYSCONGPIOHBCTL_PORTB BSP_BIT32(1) +#define SYSCONGPIOHBCTL_PORTA BSP_BIT32(0) + uint32_t gpiohbctl; + +#define SYSCONRCC2_USERCC2 BSP_BIT32(31) +#define SYSCONRCC2_DIV400 BSP_BIT32(30) +#define SYSCONRCC2_SYSDIV2(val) BSP_FLD32(val, 23, 28) +#define SYSCONRCC2_SYSDIV2_MSK BSP_MSK32(23, 28) +#define SYSCONRCC2_SYSDIV2EXT(val) BSP_FLD32(val, 22, 28) +#define SYSCONRCC2_SYSDIV2EXT_MSK BSP_MSK32(22, 28) +#define SYSCONRCC2_USBPWRDN BSP_BIT32(14) +#define SYSCONRCC2_PWRDN2 BSP_BIT32(13) +#define SYSCONRCC2_BYPASS2 BSP_BIT32(11) +#define SYSCONRCC2_OSCSRC2(val) BSP_FLD32(val, 4, 6) +#define SYSCONRCC2_OSCSRC2_MSK BSP_MSK32(4, 6) + uint32_t rcc2; + + uint32_t reserved_5[2]; + +#define SYSCONMOSCCTL_CVAL BSP_BIT32(0) + uint32_t moscctl; + + uint32_t reserved_6[32]; + +#define SYSCONRCGC0_PWM BSP_BIT32(20) +#define SYSCONRCGC0_ADC BSP_BIT32(16) +#define SYSCONRCGC0_MAXADCSPD(val) BSP_FLD32(val, 8, 9) +#define SYSCONRCGC0_MAXADCSPD_MSK BSP_MSK32(8, 9) +#define SYSCONRCGC0_HIB BSP_BIT32(6) +#define SYSCONRCGC0_WDT BSP_BIT32(3) + uint32_t rcgc0; + +#define SYSCONRCGC1_COMP1 BSP_BIT32(25) +#define SYSCONRCGC1_COMP0 BSP_BIT32(24) +#define SYSCONRCGC1_TIMER3 BSP_BIT32(19) +#define SYSCONRCGC1_TIMER2 BSP_BIT32(18) +#define SYSCONRCGC1_TIMER1 BSP_BIT32(17) +#define SYSCONRCGC1_TIMER0 BSP_BIT32(16) +#define SYSCONRCGC1_I2C1 BSP_BIT32(14) +#define SYSCONRCGC1_I2C0 BSP_BIT32(12) +#define SYSCONRCGC1_QEI0 BSP_BIT32(8) +#if LM3S69XX_NUM_SSI_BLOCKS > 1 +#define SYSCONRCGC1_SSI1 BSP_BIT32(5) +#endif +#define SYSCONRCGC1_SSI0 BSP_BIT32(4) +#define SYSCONRCGC1_UART2 BSP_BIT32(2) +#define SYSCONRCGC1_UART1 BSP_BIT32(1) +#define SYSCONRCGC1_UART0 BSP_BIT32(0) + uint32_t rcgc1; + +#define SYSCONRCGC2_USB0 BSP_BIT32(16) +#define SYSCONRCGC2_UDMA BSP_BIT32(13) +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 +#define SYSCONRCGC2_GPIOH BSP_BIT32(7) +#endif +#define SYSCONRCGC2_GPIOG BSP_BIT32(6) +#define SYSCONRCGC2_GPIOF BSP_BIT32(5) +#define SYSCONRCGC2_GPIOE BSP_BIT32(4) +#define SYSCONRCGC2_GPIOD BSP_BIT32(3) +#define SYSCONRCGC2_GPIOC BSP_BIT32(2) +#define SYSCONRCGC2_GPIOB BSP_BIT32(1) +#define SYSCONRCGC2_GPIOA BSP_BIT32(0) + uint32_t rcgc2; + + uint32_t reserved_7; + + uint32_t scgc0; + uint32_t scgc1; + uint32_t scgc2; + + uint32_t reserved_8; + + uint32_t dcgc0; + uint32_t dcgc1; + uint32_t dcgc2; + + uint32_t reserved_9[6]; + +#define SYSCONDSLPCLKCFG_DSDIVORIDE(val) BSP_FLD32(val, 23, 28) +#define SYSCONDSLPCLKCFG_DSDIVORIDE_MSK BSP_MSK32(23, 28) +#define SYSCONDSLPCLKCFG_DSOSCSRC(val) BSP_FLD32(val, 4, 6) +#define SYSCONDSLPCLKCFG_DSOSCSRC_MSK BSP_MSK32(4, 6) + uint32_t dslpclkcfg; +} lm3s69xx_syscon; + +typedef struct { +#define UARTDR_OE BSP_BIT32(11) +#define UARTDR_BE BSP_BIT32(10) +#define UARTDR_PE BSP_BIT32(9) +#define UARTDR_FE BSP_BIT32(8) +#define UARTDR_ERROR_MSK BSP_MSK32(8, 11) +#define UARTDR_DATA(val) BSP_FLD32(val, 0, 7) +#define UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) + uint32_t dr; + + uint32_t rsr_ecr; + uint32_t reserved_0[4]; + +#define UARTFR_TXFE BSP_BIT32(7) +#define UARTFR_RXFF BSP_BIT32(6) +#define UARTFR_TXFF BSP_BIT32(5) +#define UARTFR_RXFE BSP_BIT32(4) +#define UARTFR_BUSY BSP_BIT32(3) + uint32_t fr; + + uint32_t reserved_1; + + uint32_t ilpr; + uint32_t ibrd; + uint32_t fbrd; + +#define UARTLCRH_SPS BSP_BIT32(7) +#define UARTLCRH_WLEN(val) BSP_FLD32(val, 5, 6) +#define UARTLCRH_FEN BSP_BIT32(4) +#define UARTLCRH_STP2 BSP_BIT32(3) +#define UARTLCRH_EPS BSP_BIT32(2) +#define UARTLCRH_PEN BSP_BIT32(1) +#define UARTLCRH_BRK BSP_BIT32(0) + uint32_t lcrh; + +#define UARTCTL_RXE BSP_BIT32(9) +#define UARTCTL_TXE BSP_BIT32(8) +#define UARTCTL_LBE BSP_BIT32(7) +#define UARTCTL_SIRLP BSP_BIT32(2) +#define UARTCTL_SIREN BSP_BIT32(1) +#define UARTCTL_UARTEN BSP_BIT32(0) + uint32_t ctl; + +#define UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5) +#define UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2) + uint32_t ifls; + +#define UARTI_OE BSP_BIT32(10) +#define UARTI_BE BSP_BIT32(9) +#define UARTI_PE BSP_BIT32(8) +#define UARTI_FE BSP_BIT32(7) +#define UARTI_RT BSP_BIT32(6) +#define UARTI_TX BSP_BIT32(5) +#define UARTI_RX BSP_BIT32(4) + uint32_t im; + uint32_t ris; + uint32_t mis; + uint32_t icr; +#if LM3S69XX_HAS_UDMA + uint32_t dmactl; +#endif +} lm3s69xx_uart; + +typedef struct { +#define SSICR0_SCR(val) BSP_FLD32(val, 8, 15) +#define SSICR0_SPH BSP_BIT32(7) +#define SSICR0_SPO BSP_BIT32(6) +#define SSICR0_FRF(val) BSP_FLD32(val, 4, 5) +#define SSICR0_DSS(val) BSP_FLD32(val, 0, 3) + uint32_t cr0; + +#define SSICR1_SOD BSP_BIT32(3) +#define SSICR1_MS BSP_BIT32(2) +#define SSICR1_SSE BSP_BIT32(1) +#define SSICR1_LBM BSP_BIT32(0) + uint32_t cr1; + uint32_t dr; + +#define SSISR_BSY BSP_BIT32(4) +#define SSISR_RFF BSP_BIT32(3) +#define SSISR_RNE BSP_BIT32(2) +#define SSISR_TNF BSP_BIT32(1) +#define SSISR_TFE BSP_BIT32(0) + uint32_t sr; + +#define SSI_CPSRDIV(val) BSP_FLD32(val, 0, 7) + uint32_t cpsr; + +#define SSII_TX BSP_BIT32(3) +#define SSII_RX BSP_BIT32(2) +#define SSII_RT BSP_BIT32(1) +#define SSII_ROR BSP_BIT32(0) + uint32_t im; + uint32_t ris; + uint32_t mis; + uint32_t icr; + +#if LM3S69XX_HAS_UDMA +#define SSIDMACTL_TXDMAE BSP_BIT32(1) +#define SSIDMACTL_RXDMAE BSP_BIT32(0) + uint32_t dmactl; +#endif /* LM3S69XX_HAS_UDMA */ +} lm3s69xx_ssi; + +#endif /* LIBBSP_ARM_LM3S69XX_LM3S69XX_H */ diff --git a/bsps/arm/lm3s69xx/include/bsp/ssi.h b/bsps/arm/lm3s69xx/include/bsp/ssi.h new file mode 100644 index 0000000000..e6e44c5aae --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp/ssi.h @@ -0,0 +1,43 @@ +/** + * @file + * + * @ingroup lm3s69xx_ssi + * + * @brief SSI support. + */ + +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef LIBBSP_ARM_LM3S69XX_SSI_H +#define LIBBSP_ARM_LM3S69XX_SSI_H +#include +#include + +/** + * @defgroup lm3s69xx_ssi SSI Support + * + * @ingroup arm_lm3s69xx + * + * @brief SSI Support + */ + +#ifdef __cplusplus +extern "C" { +#endif + +extern rtems_libi2c_bus_t * const lm3s69xx_ssi_0; + +#if LM3S69XX_NUM_SSI_BLOCKS > 1 +extern rtems_libi2c_bus_t * const lm3s69xx_ssi_1; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_LM3S69XX_SSI_H */ diff --git a/bsps/arm/lm3s69xx/include/bsp/syscon.h b/bsps/arm/lm3s69xx/include/bsp/syscon.h new file mode 100644 index 0000000000..016839b5e5 --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp/syscon.h @@ -0,0 +1,43 @@ +/** + * @file + * + * @ingroup lm3s69xx_syscon + * + * @brief Syscon support. + */ + +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef LIBBSP_ARM_LM3S69XX_SYSCON_H +#define LIBBSP_ARM_LM3S69XX_SYSCON_H +#include + +/** + * @defgroup lm3s69xx_syscon Syscon Support + * + * @ingroup arm_lm3s69xx + * + * @brief Syscon Support + */ + +#ifdef __cplusplus +extern "C" { +#endif + +void lm3s69xx_syscon_enable_gpio_clock(unsigned int port, bool enable); +void lm3s69xx_syscon_enable_uart_clock(unsigned int port, bool enable); +void lm3s69xx_syscon_enable_ssi_clock(unsigned int port, bool enable); +void lm3s69xx_syscon_enable_pwm_clock(bool enable); +void lm3s69xx_syscon_set_pwmdiv(unsigned int div); +void lm3s69xx_syscon_delay_3x_clocks(unsigned long x_count); + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_LM3S69XX_SYSCON_H */ diff --git a/bsps/arm/lm3s69xx/include/bsp/uart.h b/bsps/arm/lm3s69xx/include/bsp/uart.h new file mode 100644 index 0000000000..544fed55eb --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp/uart.h @@ -0,0 +1,46 @@ +/** + * @file + * + * @ingroup lm3s69xx_uart + * + * brief UART support. + */ + +/* + * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LM3S69XX_UART_H +#define LIBBSP_ARM_LM3S69XX_UART_H + +#include + +/** + * defgroup lm3s69xx_uart UART Support + * + * @ingroup arm_lm3s69xx + * + * @brief UART support. + */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern const console_fns lm3s69xx_uart_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LM3S69XX_UART_H */ diff --git a/bsps/arm/lm3s69xx/include/tm27.h b/bsps/arm/lm3s69xx/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/lm3s69xx/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/lpc176x/headers.am b/bsps/arm/lpc176x/headers.am new file mode 100644 index 0000000000..aceb1c4fa5 --- /dev/null +++ b/bsps/arm/lpc176x/headers.am @@ -0,0 +1,30 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/lpc176x/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/adc-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/adc.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/can-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/can.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/common-types.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/dma.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/gpio-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/io-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/io.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/lpc-clock-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/lpc-gpio.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/lpc176x.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/mbed-pinmap.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/pwmout-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/pwmout.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/system-clocks.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/timer-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/timer.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/watchdog-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/watchdog.h diff --git a/bsps/arm/lpc176x/include/bsp.h b/bsps/arm/lpc176x/include/bsp.h new file mode 100644 index 0000000000..e81e1cd53c --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp.h @@ -0,0 +1,98 @@ +/** + * @file + * + * @ingroup lpc176x + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_BSP_H +#define LIBBSP_ARM_LPC176X_BSP_H + +#include + +#define LPC176X_PCLK ( LPC176X_CCLK / LPC176X_PCLKDIV ) +#define LPC176X_MPU_REGION_COUNT 8u + +#define BSP_FEATURE_IRQ_EXTENSION +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT ( 29u << 3u ) +#define BSP_ARMV7M_SYSTICK_PRIORITY ( 30u << 3u ) +#define BSP_ARMV7M_SYSTICK_FREQUENCY LPC176X_CCLK + +#ifndef ASM + +#include +#include + +/** Define operation count for Tests */ +#define OPERATION_COUNT 4 + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct rtems_bsdnet_ifconfig; + +/** + * @defgroup lpc176x LPC176X Support + * + * @ingroup bsp_arm + * + * @brief LPC176X support package. + * + * @{ + */ + +/** + * @brief Optimized idle task. + * + * This idle task sets the power mode to idle. This causes the processor + * clock to be stopped, while on-chip peripherals remain active. + * Any enabled interrupt from a peripheral or an external interrupt source + * will cause the processor to resume execution. + * + * To enable the idle task use the following in the system configuration: + * + * @code + * #include + * + * #define CONFIGURE_INIT + * + * #define CONFIGURE_IDLE_TASK_BODY bsp_idle_thread + * + * #include + * @endcode + */ +void*bsp_idle_thread( uintptr_t ignored ); + +#define BSP_CONSOLE_UART_BASE 0x4000C000U + +/** + * @brief Restarts the bsp with "addr" address + * @param addr Address used to restart the bsp + */ +void bsp_restart( const void *addr ); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_LPC176X_BSP_H */ diff --git a/bsps/arm/lpc176x/include/bsp/adc-defs.h b/bsps/arm/lpc176x/include/bsp/adc-defs.h new file mode 100755 index 0000000000..3daca807b7 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/adc-defs.h @@ -0,0 +1,96 @@ +/** + * @file adc-defs.h + * + * @ingroup lpc176x + * + * @brief ADC library for the lpc176x bsp. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef LPC176X_ADC_DEFS_H +#define LPC176X_ADC_DEFS_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief The ADC inputs of the board. + */ +typedef enum { + ADC_0, + ADC_1, + ADC_2, + ADC_3, + ADC_4, + ADC_5, + ADC_6, + ADC_7, + ADC_DEVICES_COUNT +} lpc176x_adc_number; + +#define MAX_ADC_CLK 13000000u + +#define ADC_RANGE 0xFFFu + +#define ADC_NUMBER_VALID( number ) ( ( (uint32_t) number ) < \ + ADC_DEVICES_COUNT ) + +#define ADC_CR_SEL( val ) BSP_FLD32( val, 0, 7 ) +#define ADC_CR_SEL_GET( val ) BSP_FLD32GET( val, 0, 7 ) +#define ADC_CR_SEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 7 ) +#define ADC_CR_CLKDIV( val ) BSP_FLD32( val, 8, 15 ) +#define ADC_CR_CLKDIV_GET( reg ) BSP_FLD32GET( reg, 8, 15 ) +#define ADC_CR_CLKDIV_SET( reg, val ) BSP_FLD32SET( reg, val, 8, 15 ) +#define ADC_CR_BURST BSP_BIT32( 16 ) +#define ADC_CR_CLKS( val ) BSP_FLD32( val, 17, 19 ) +#define ADC_CR_PDN BSP_BIT32( 21 ) +#define ADC_CR_START_NOW BSP_BIT32( 24 ) +#define ADC_CR_START( val ) BSP_FLD32( val, 24, 26 ) +#define ADC_CR_EDGE BSP_BIT32( 27 ) + +#define ADC_DR_VALUE( reg ) BSP_FLD32GET( reg, 4, 15 ) +#define ADC_DR_OVERRUN BSP_BIT32( 30 ) +#define ADC_DR_DONE BSP_BIT32( 31 ) + +#define ADC_DATA_CONVERSION_DONE( val ) ( ( val & ADC_DR_DONE ) != 0u ) + +/** + * @brief The ADC low-level device. + */ +typedef struct { + volatile uint32_t ADCR; + volatile uint32_t ADGDR; + volatile uint32_t RESERVED0; + volatile uint32_t ADINTEN; + volatile uint32_t ADDR[ ADC_DEVICES_COUNT ]; + volatile uint32_t ADSTAT; + volatile uint32_t ADTRM; +} lpc176x_adc_device; + +/** + * @brief Represents the pin and function for each ADC input. + */ +typedef struct { + uint32_t pin_number; + lpc176x_pin_function pin_function; +} lpc176x_adc_pin_map; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/bsps/arm/lpc176x/include/bsp/adc.h b/bsps/arm/lpc176x/include/bsp/adc.h new file mode 100755 index 0000000000..34df8b7efd --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/adc.h @@ -0,0 +1,60 @@ +/** + * @file adc.h + * + * @ingroup lpc176x + * + * @brief ADC library for the lpc176x bsp. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LPC176X_ADC_H +#define LPC176X_ADC_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Opens and initializes the ADC device. + * + * @param adc_number The ADC pin number to be initialized. + * @return RTEMS_SUCCESSFUL if the initialization was succesful, + * RTEMS_INVALID_NUMBER if wrong parameter. + */ +rtems_status_code adc_open( const lpc176x_pin_number pin_number ); + +/** + * @brief Closes the ADC device. + * + * @return RTEMS_SUCCESSFUL if closed succesfully. + */ +rtems_status_code adc_close( void ); + +/** + * @brief Starts a conversion, waits for it to finish and reads the value. + * + * @param pin_number The port to read the value. + * @param result The read result. (In a percentage between 0.0f and 1.0f). + */ +rtems_status_code adc_read( + const lpc176x_pin_number pin_number , + float *const result +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/bsps/arm/lpc176x/include/bsp/can-defs.h b/bsps/arm/lpc176x/include/bsp/can-defs.h new file mode 100755 index 0000000000..4db229eb1c --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/can-defs.h @@ -0,0 +1,183 @@ +/** + * @file can-defs.h + * + * @ingroup lpc176x + * + * @brief CAN controller for the lpc176x controller. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LPC176X_TIMER_DEFS_H +#define LPC176X_TIMER_DEFS_H + +#include +#include + +/* CAN ACCEPTANCE FILTER */ +#define CAN_ACCEPT_BASE_ADDR 0x4003C000 + +#define CAN_DRIVER_IS_MINOR_VALID( minor ) ( minor < CAN_DEVICES_NUMBER ) +#define CAN_DEFAULT_BAUD_RATE 1000000u +#define CAN_DEFAULT_INTERRUPT_CONFIGURATION 0 + +#define MAX_NUMBER_OF_CAN_BITS 25u +#define MIN_NUMBER_OF_CAN_BITS 4u +#define CAN_BRP_EXTRA_BIT 1u +#define CAN_TSEG_EXTRA_BITS 3u +#define MAX_TSEG1_TSEG2_BITS 22u + +#define CAN_GSR_RBS_MASK 1u +#define CAN_CMR_RRB_MASK 4u + +#define CAN_MAXIMUM_DATA_SIZE 8u +#define CAN10_MAXIMUM_ID 0x7FFu + +/** + * @brief The Time segments of a CAN bit. + */ +typedef enum { + CAN_TSEG1, + CAN_TSEG2, + CAN_NUMBER_OF_TSEG, +} can_tseg_number; + +#define CAN_BTR_TSEG1_SHIFT 16u +#define CAN_BTR_TSEG2_SHIFT 20u +#define CAN_BTR_SJW_SHIFT 14u +#define CAN_BTR_BRP_SHIFT 0u + +#define CAN_BTR_TSEG1_MASK 0x000F0000U +#define CAN_BTR_TSEG2_MASK 0x00700000U +#define CAN_BTR_SJW_MASK 0x0000C000U +#define CAN_BTR_BRP_MASK 0x000003FFU + +#define WRONG_BTR_VALUE 0xFFFFFFFF + +/** + * @brief The transmit buffers of the CAN device. + */ +typedef enum { + CAN_TRANSMIT1, + CAN_TRANSMIT2, + CAN_TRANSMIT3, + CAN_NUMBER_OF_TRANSMIT_BUFFERS +} can_transmit_number; + +/** + * @brief The CAN status and control masks to send a message + * for each transmit buffer. + */ +typedef struct { + uint32_t can_status_mask; + uint32_t not_cc_cmr_value; +} can_transmit_info; + +/** @brief Represents the CAN controller registers.*/ +typedef struct { + volatile uint32_t MOD; + volatile uint32_t CMR; + volatile uint32_t GSR; + volatile uint32_t ICR; + volatile uint32_t IER; + volatile uint32_t BTR; + volatile uint32_t EWL; + volatile uint32_t SR; + volatile registers_can_message receive; + volatile registers_can_message transmit[ CAN_NUMBER_OF_TRANSMIT_BUFFERS ]; +} can_device; + +/** + * @brief A TX or RX pin for each CAN device . + */ +typedef enum { + CAN_TX_PIN, + CAN_RX_PIN, + NUMBER_OF_CAN_PINS +} can_pin_number; + +/** + * @brief A driver entry for each low level device. + */ +typedef struct { + can_device *const device; + const lpc176x_module module; + const uint32_t pconp_pin; + const uint32_t pins[ NUMBER_OF_CAN_PINS ]; + const lpc176x_pin_function pinfunction; +} can_driver_entry; + +/** @brief Represents the CAN centralized registers. */ +typedef struct { + volatile uint32_t TX_SR; + volatile uint32_t RX_SR; + volatile uint32_t MSR; +} can_central; + +/** @brief Represents the acceptance filter registers. */ +typedef struct { + volatile uint32_t AFMR; + volatile uint32_t SFF_SA; + volatile uint32_t SFF_GRP_SA; + volatile uint32_t EFF_SA; + volatile uint32_t EFF_GRP_SA; + volatile uint32_t EOT; + volatile uint32_t LUT_ERR_ADR; + volatile uint32_t LUT_ERR; + volatile uint32_t FCANIE; + volatile uint32_t FCANIC0; + volatile uint32_t FCANIC1; +} can_acceptance_filter; + +/** + * @brief The possible CAN formats for a message. + */ +typedef enum { + CANStandard = 0, + CANExtended = 1, + CANAny = 2 +} can_format; + +/** + * @brief The types of message. + */ +typedef enum { + CANData = 0, + CANRemote = 1 +} can_type; + +#define CAN_INTERRUPT_TYPE_MASK 0x1ffu + +/** + * @brief The vector with all the callbacks for the CAN isr. + */ +typedef lpc176x_can_isr lpc176x_can_isr_vector[ CAN_IRQ_NUMBER ]; + +#define CAN_MOD_RM 0x00000001U + +#define CAN_ACCF_AFMR_ACCOF 0x00000001U +#define CAN_ACCF_AFMR_ACCBP 0x00000002U +#define CAN_ACCF_AFMR_EFCAN 0x00000004U + +#define CAN_IER_RIE 0x000000001U +#define CAN_IER_TIE1 0x000000002U +#define CAN_IER_EIE 0x000000004U +#define CAN_IER_DOIE 0x000000008U +#define CAN_IER_WUIE 0x000000010U +#define CAN_IER_EPIEX 0x000000020U +#define CAN_IER_ALIEX 0x000000040U +#define CAN_IER_BEIEX 0x000000080U +#define CAN_IER_IDIEX 0x000000100U +#define CAN_IER_TIE2 0x000000200U +#define CAN_IER_TIE3 0x000000400U + +#endif /*LPC176X_TIMER_DEFS_H*/ diff --git a/bsps/arm/lpc176x/include/bsp/can.h b/bsps/arm/lpc176x/include/bsp/can.h new file mode 100755 index 0000000000..7515ec2f53 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/can.h @@ -0,0 +1,179 @@ +/** + * @file can.h + * + * @ingroup lpc176x + * + * @brief CAN controller for the mbed lpc1768 board. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LPC176X_CAN_H +#define LPC176X_CAN_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief The CAN devices of the board. + */ +typedef enum { + CAN_0, + CAN_1, + CAN_DEVICES_NUMBER +} lpc176x_can_number; + +/** + * @brief A CAN message represented for the registers of the device. + */ +typedef struct { + uint32_t info; + uint32_t id; + uint32_t data_a; + uint32_t data_b; +} registers_can_message; + +/** + * @brief A CAN message represented with each logical parts + */ +typedef struct { + unsigned int reserved1 : 16; + unsigned int dlc : 4; /* Bits 16..19: DLC - Data Length Counter*/ + unsigned int reserved0 : 10; + unsigned int rtr : 1; /* Bit 30: Set if this is a RTR message*/ + unsigned int type : 1; /* Bit 31: Set if this is a 29-bit ID message*/ + unsigned int id; /* CAN Message ID (11-bit or 29-bit)*/ + unsigned char data[ 8 ]; /* CAN Message Data Bytes 0-7*/ +} low_level_can_message; + +/** + * @brief A CAN message represented of both forms. + */ +typedef union { + low_level_can_message low_level; + registers_can_message registers; +} can_message; + +/** + * @brief The possible interrupt sources for CAN. + */ +typedef enum { + IRQ_RX = 0, + IRQ_TX, + IRQ_ERROR, + IRQ_OVERRUN, + IRQ_WAKEUP, + IRQ_PASSIVE, + IRQ_ARB, + IRQ_BUS, + IRQ_READY, + CAN_IRQ_NUMBER +} can_irq_type; + +/** + * @brief An isr for a CAN interrupt + * + * @param number The CAN which rised the interrupt. + */ +typedef void (*lpc176x_can_isr) ( lpc176x_can_number number ); + +/** + * @brief A CAN frequency value + */ +typedef unsigned int can_freq; + +/** + * @brief Opens CAN device. + * @details It enables the module and gives it a clock, sets the pins, + * disables the interrupts, sets the frequency and bypasses + * the acceptance filter. + * + * @param minor The device to open. + * @param freq The desired frequency. + * @return RTEMS_SUCCESFUL on success. + */ +rtems_status_code can_open( lpc176x_can_number minor, can_freq freq ); + +/** + * @brief Closes the passed CAN device and shut it down. + * + * @param minor The device to close. + * @return RTEMS_SUCCESSFUL if ok, RTEMS_INVALID_NUMBER for a bad parameter. + */ +rtems_status_code can_close( lpc176x_can_number minor ); + +/** + * @brief Reads the CAN device. + * + * @param minor The CAN device to read. + * @param message The read message. + * @return RTEMS_SUCCESSFUL if read ok, RTEMS_IO_ERROR otherwise. + */ +rtems_status_code can_read( + const lpc176x_can_number minor, + can_message *message +); + +/** + * @brief Writes the passed CAN message into the selected CAN device. + * + * @param minor The device to write. + * @param message The message to write. + * @return RTEMS_SUCCESFUL if write ok. RTEMS_IO_ERROR otherwise. + */ +rtems_status_code can_write( + const lpc176x_can_number minor, + const can_message *const message +); + +/** + * @brief Registers an isr in the driver vector, and enables the interrupt +* in the device. + * + * @param number The CAN device to set + * @param type The interrupt type. + * @param isr The isr to register. + * @return RTEMS_SUCCESSFUL if ok RTEMS_INVALID_NUMBER otherwise. + */ +rtems_status_code can_register_isr( + const lpc176x_can_number number, + const can_irq_type type, + const lpc176x_can_isr isr +); + +/** + * @brief Creates a CAN message. + * @details [long description] + * + * @param msg The created message. + * @param _id The can id for the message. + * @param _data The data of the message. + * @param _len The length of the message. + * @return RTEMS_SUCCESFUL if created, RTEMS_INVALID_NUMBER otherwise. + */ +rtems_status_code create_can_message( + can_message *const msg, + const int _id, + const char *const _data, + const char _len +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ifndef LPC176X_CAN_H */ diff --git a/bsps/arm/lpc176x/include/bsp/common-types.h b/bsps/arm/lpc176x/include/bsp/common-types.h new file mode 100644 index 0000000000..943ff288a9 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/common-types.h @@ -0,0 +1,118 @@ +/** + * @file common-types.h + * + * @ingroup lpc176x + * + * @brief Definitions types used by some devices in common. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_COMMON_TYPES_H +#define LIBBSP_ARM_LPC176X_COMMON_TYPES_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief A pin of the board. + */ +typedef uint32_t lpc176x_pin_number; + +/** + * @brief Microseconds representation. + */ +typedef uint32_t lpc176x_microseconds; + +/** + * @brief lpc176x module representation. + * + * Enumerated type to define the set of modules for a lpc176x board. + */ +typedef enum { + LPC176X_MODULE_WD, + LPC176X_MODULE_ADC, + LPC176X_MODULE_CAN_0, + LPC176X_MODULE_CAN_1, + LPC176X_MODULE_ACCF, + LPC176X_MODULE_DAC, + LPC176X_MODULE_GPDMA, + LPC176X_MODULE_GPIO, + LPC176X_MODULE_I2S, + LPC176X_MODULE_MCI, + LPC176X_MODULE_MCPWM, + LPC176X_MODULE_PCB, + LPC176X_MODULE_PWM_0, + LPC176X_MODULE_PWM_1, + LPC176X_MODULE_QEI, + LPC176X_MODULE_RTC, + LPC176X_MODULE_SYSCON, + LPC176X_MODULE_TIMER_0, + LPC176X_MODULE_TIMER_1, + LPC176X_MODULE_TIMER_2, + LPC176X_MODULE_TIMER_3, + LPC176X_MODULE_UART_0, + LPC176X_MODULE_UART_1, + LPC176X_MODULE_UART_2, + LPC176X_MODULE_UART_3, + LPC176X_MODULE_USB +} lpc176x_module; + +/** + * @brief Defines all the clock modules. + * + * Enumerated type to define the set of clock modules for a lpc176x board. + */ +typedef enum { + LPC176X_MODULE_PCLK_DEFAULT = 0x4U, + LPC176X_MODULE_CCLK = 0x1U, + LPC176X_MODULE_CCLK_2 = 0x2U, + LPC176X_MODULE_CCLK_4 = 0x0U, + LPC176X_MODULE_CCLK_6 = 0x3U, + LPC176X_MODULE_CCLK_8 = 0x3U +} lpc176x_module_clock; + +/** + * @brief Fast Input/Output registers representation. + */ +typedef struct { + /** + * @brief Direction control register. + */ + uint32_t dir; + uint32_t reserved[ 3U ]; + /** + * @brief Mask register for port. + */ + uint32_t mask; + /** + * @brief Pinvalue register using 'mask'. + */ + uint32_t pin; + /** + * @brief Output Set register using 'mask'. + */ + uint32_t set; + /** + * @brief Output Clear register using 'maks'. + */ + uint32_t clr; +} lpc176x_fio; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_COMMON_TYPES_H */ \ No newline at end of file diff --git a/bsps/arm/lpc176x/include/bsp/dma.h b/bsps/arm/lpc176x/include/bsp/dma.h new file mode 100644 index 0000000000..65edfc4e30 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/dma.h @@ -0,0 +1,98 @@ +/** + * @file + * + * @ingroup lpc176x_dma + * + * @brief Direct memory access (DMA) support. + */ + +/* + * Copyright (c) 2008, 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_DMA_H +#define LIBBSP_ARM_LPC176X_DMA_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc176x_dma DMA Support + * + * @ingroup lpc176x + * + * @brief Direct memory access (DMA) support. + * + * @{ + */ + +/** + * @brief Initializes the general purpose DMA. + */ +void lpc176x_dma_initialize( void ); + +/** + * @brief Tries to obtain the DMA channel @a channel. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid channel number. + * @retval RTEMS_RESOURCE_IN_USE Channel already occupied. + */ +rtems_status_code lpc176x_dma_channel_obtain( unsigned channel ); + +/** + * @brief Releases the DMA channel @a channel. + * + * You must have obtained this channel with lpc176x_dma_channel_obtain() + * previously. + * + * If the channel number @a channel is out of range nothing will happen. + */ +void lpc176x_dma_channel_release( unsigned channel ); + +/** + * @brief Disables the DMA channel @a channel. + * + * If @a force is @c false the channel will be halted and disabled when the + * channel is inactive otherwise it will be disabled immediately. + * + * If the channel number @a channel is out of range nothing will happen. + */ +void lpc176x_dma_channel_disable( + unsigned channel, + bool force +); + +rtems_status_code lpc176x_dma_copy_initialize( void ); + +rtems_status_code lpc176x_dma_copy_release( void ); + +rtems_status_code lpc176x_dma_copy( + unsigned channel, + const void *dest, + const void *src, + size_t n, + size_t width +); + +rtems_status_code lpc176x_dma_copy_wait( unsigned channel ); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_DMA_H */ diff --git a/bsps/arm/lpc176x/include/bsp/gpio-defs.h b/bsps/arm/lpc176x/include/bsp/gpio-defs.h new file mode 100644 index 0000000000..c6ed499d35 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/gpio-defs.h @@ -0,0 +1,218 @@ +/** + * @file gpio-defs.h + * + * @ingroup lpc176x + * + * @brief API definitions of the GPIO driver for the lpc176x bsp in RTEMS. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_GPIO_DEFS_H +#define LIBBSP_ARM_LPC176X_GPIO_DEFS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* General Purpose Input/Output (GPIO) */ +#define LPC176X_GPIO_BASE_ADDR 0x40028000U +#define LPC176X_GPIO_INTERRUPT_STATUS 0x40028080U + +#define LPC176X_IOPIN0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x00U ) ) +#define LPC176X_IOSET0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x04U ) ) +#define LPC176X_IODIR0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x08U ) ) +#define LPC176X_IOCLR0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x0CU ) ) +#define LPC176X_IOPIN1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x10U ) ) +#define LPC176X_IOSET1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x14U ) ) +#define LPC176X_IODIR1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x18U ) ) +#define LPC176X_IOCLR1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x1CU ) ) + +/* GPIO Interrupt Registers */ +#define LPC176X_IO0_INT_EN_R ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0x90U ) ) +#define LPC176X_IO0_INT_EN_F ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0x94U ) ) +#define LPC176X_IO0_INT_STAT_R ( *(volatile uint32_t *) ( \ + LPC176X_GPIO_BASE_ADDR \ + + 0x84U ) ) +#define LPC176X_IO0_INT_STAT_F ( *(volatile uint32_t *) ( \ + LPC176X_GPIO_BASE_ADDR \ + + 0x88U ) ) +#define LPC176X_IO0_INT_CLR ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0x8CU ) ) +#define LPC176X_IO2_INT_EN_R ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0xB0U ) ) +#define LPC176X_IO2_INT_EN_F ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0xB4U ) ) +#define LPC176X_IO2_INT_STAT_R ( *(volatile uint32_t *) ( \ + LPC176X_GPIO_BASE_ADDR \ + + 0xA4U ) ) +#define LPC176X_IO2_INT_STAT_F ( *(volatile uint32_t *) ( \ + LPC176X_GPIO_BASE_ADDR \ + + 0xA8U ) ) +#define LPC176X_IO2_INT_CLR ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0xACU ) ) +#define LPC176X_IO_INT_STAT ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0x80U ) ) + +#define LPC176X_RESERVED_ISR_FUNCT_SIZE 2U +#define LPC176X_RESERVED_ISR_FUNCT_MAX_SIZE 5U + +#define LPC176X_MAX_PORT_NUMBER 160U +#define LPC176X_SET_BIT( reg, pin, value ) \ + reg = ( reg & ~( 1U << pin ) ) | ( ( value & 1U ) << pin ) + +#define LPC176X_INT_STATUS ( *(volatile uint32_t *) \ + ( LPC176X_GPIO_INTERRUPT_STATUS ) ) +#define LPC176X_INT_STATUS_P0 1U +#define LPC176X_INT_STATUS_P2 ( 1U << 2U ) +#define LPC176X_INT_ENABLE 1U +#define LPC176X_INT_DISABLE 0U + +#define LPC176X_IRQ_EINT_3 21U + +#define LPC176X_PIN_BIT( pin ) ( 1U << pin ) + +/** + * @brief The direction of the GPIO port (input or output). + * + * Enumerated type to define the set of function types for a gpio device. + */ +typedef enum { + LPC176X_GPIO_FUNCTION_INPUT, + LPC176X_GPIO_FUNCTION_OUTPUT, + LPC176X_GPIO_FUNCTION_COUNT +} +lpc176x_gpio_direction; + +/** + * @brief The interrupt sources edge for a GPIO. + * + * Enumerated type to define the set of interrupt types for a gpio device. + */ +typedef enum { + LPC176X_GPIO_INTERRUPT_DISABLE, + LPC176X_GPIO_INTERRUPT_RISING, + LPC176X_GPIO_INTERRUPT_FALLING, + LPC176X_GPIO_INTERRUPT_BOTH, + LPC176X_GPIO_INTERRUPT_COUNT +} lpc176x_gpio_interrupt; + +/** + * @brief The ports for a GPIO. + * + * Enumerated type to define the set of ports for a gpio device. + */ +typedef enum { + LPC176X_GPIO_PORT_0, + LPC176X_GPIO_PORT_1, + LPC176X_GPIO_PORT_2, + LPC176X_GPIO_PORT_3, + LPC176X_GPIO_PORT_4, + LPC176X_GPIO_PORTS_COUNT +} lpc176x_gpio_ports; + +/** + * @brief Addresses for a GPIO. + * + * Enumerated type to define the set of fio bases addresses + * for a gpio device. + */ +typedef enum { + LPC176X_FIO0_BASE_ADDRESS = 0x2009C000U, + LPC176X_FIO1_BASE_ADDRESS = 0x2009C020U, + LPC176X_FIO2_BASE_ADDRESS = 0x2009C040U, + LPC176X_FIO3_BASE_ADDRESS = 0x2009C060U, + LPC176X_FIO4_BASE_ADDRESS = 0x2009C080U, +} lpc176x_gpio_address; + +/** + * @brief Addresses for the two interrupts. + * + * Enumerated type to define the set of interrupt addresses + * for a gpio device. + */ +typedef enum { + LPC176X_IO0_INT_BASE_ADDRESS = 0x40028084U, + LPC176X_IO2_INT_BASE_ADDRESS = 0x400280A4U, +} lpc176x_interrupt_address; + +/** + * @brief GPIO Interrupt register map. + */ +typedef struct { + /** + * @brief Interrupt Enable for Rising edge. + */ + volatile uint32_t StatR; + /** + * @brief Interrupt Enable for Falling edge. + */ + volatile uint32_t StatF; + /** + * @brief Interrupt Clear. + */ + volatile uint32_t Clr; + /** + * @brief Interrupt Enable for Rising edge. + */ + volatile uint32_t EnR; + /** + * @brief Interrupt Enable for Falling edge. + */ + volatile uint32_t EnF; +} lpc176x_interrupt_control; + +/** + * @brief A function that attends an interrupt for GPIO. + * + * @param pin Pin number. + * @param edge Interrupt. + * @return Pointer to the interrupt function. + */ +typedef void (*lpc176x_gpio_interrupt_function) ( + const lpc176x_pin_number pin, + const lpc176x_gpio_interrupt edge +); + +/** + * @brief A registered interrupt function for the pin 'pin'. + */ +typedef struct { + /** + * @brief Pin board. + */ + lpc176x_pin_number pin; + /** + * @brief A function that attends an interrupt for 'pin'. + */ + lpc176x_gpio_interrupt_function function; +} lpc176x_registered_interrupt_function; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_GPIO_DEFS_H */ diff --git a/bsps/arm/lpc176x/include/bsp/io-defs.h b/bsps/arm/lpc176x/include/bsp/io-defs.h new file mode 100644 index 0000000000..f9cf3dbbbd --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/io-defs.h @@ -0,0 +1,142 @@ +/** + * @file io-defs.h + * + * @ingroup lpc176x + * + * @brief Input/output module definitions. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_IO_DEFS_H +#define LIBBSP_ARM_LPC176X_IO_DEFS_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define LPC176X_PLL0CON 0XAAU +#define LPC176X_PLL0CFG 0X55U + +#define LPC176X_CCLK_PRESCALER_DIVISOR 1000000U + +#define LPC176X_PINSEL ( &PINSEL0 ) +#define LPC176X_PINMODE ( &PINMODE0 ) + +#define LPC176X_PIN_SELECT( index ) ( ( index ) >> 4U ) +#define LPC176X_PIN_SELECT_SHIFT( index ) ( ( ( index ) & 0xFU ) << 1U ) +#define LPC176X_PIN_SELECT_MASK 0x3U +#define LPC176X_PIN_SELECT_MASK_SIZE 2U +#define LPC176X_PIN_UART_0_TXD 2U +#define LPC176X_PIN_UART_0_RXD 3U +#define LPC176X_PIN_UART_1_TXD 15U +#define LPC176X_PIN_UART_1_RXD 16U +#define LPC176X_PIN_UART_2_TXD 10U +#define LPC176X_PIN_UART_2_RXD 11U +#define LPC176X_PIN_UART_3_TXD 0U +#define LPC176X_PIN_UART_3_RXD 1U + +#define LPC176X_MODULE_BITS_COUNT 32U +#define LPC176X_MODULE_COUNT ( LPC176X_MODULE_USB + 1U ) + +#define LPC176X_IO_PORT_COUNT 5U +#define LPC176X_IO_INDEX_MAX ( LPC176X_IO_PORT_COUNT * \ + LPC176X_MODULE_BITS_COUNT ) +#define LPC176X_IO_INDEX_BY_PORT( port, bit ) ( ( ( port ) << 5U ) + ( bit ) ) +#define LPC176X_IO_PORT( index ) ( ( index ) >> 5U ) +#define LPC176X_IO_PORT_BIT( index ) ( ( index ) & 0x1FU ) + +/** + * @brief Defines the functions according to the pin. + * + * Enumerated type to define the set of pin function for a io device. + */ +typedef enum { + LPC176X_PIN_FUNCTION_00, + LPC176X_PIN_FUNCTION_01, + LPC176X_PIN_FUNCTION_10, + LPC176X_PIN_FUNCTION_11, + LPC176X_PIN_FUNCTION_COUNT +} +lpc176x_pin_function; + +/** + * @brief Defines the pin modes. + * + */ +typedef enum { + LPC176X_PIN_MODE_PULLUP, + LPC176X_PIN_MODE_REPEATER, + LPC176X_PIN_MODE_NONE, + LPC176X_PIN_MODE_PULLDOWN, + LPC176X_PIN_MODE_COUNT +} +lpc176x_pin_mode; + +/** + * @brief Defines all type of pins. + * + * Enumerated type to define the set of pin type for a io device. + */ +typedef enum { + LPC176X_PIN_TYPE_DEFAULT, + LPC176X_PIN_TYPE_ADC, + LPC176X_PIN_TYPE_DAC, + LPC176X_PIN_TYPE_OPEN_DRAIN +} lpc176x_pin_type; + +/** + * @brief Represents each pclksel number. + * + * Enumerated type to define the set of values for a pcklsel. + */ +typedef enum { + LPC176X_SCB_PCLKSEL0, + LPC176X_SCB_PCLKSEL1, + LPC176X_SCB_PCLKSEL_COUNT +} lpc176x_scb_value_pclksel; + +/** + * @brief Defines the module entry. + */ +typedef struct { + /** + * @brief Power entry bit. + */ + unsigned char power : 1; + /** + * @brief Clock entry bit. + */ + unsigned char clock : 1; + /** + * @brief Index entry bits. + */ + unsigned char index : 6; +} lpc176x_module_entry; + +#define LPC176X_MODULE_ENTRY( mod, pwr, clk, idx ) \ + [ mod ] = { \ + .power = pwr, \ + .clock = clk, \ + .index = idx \ + } + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_IO_DEFS_H */ diff --git a/bsps/arm/lpc176x/include/bsp/io.h b/bsps/arm/lpc176x/include/bsp/io.h new file mode 100644 index 0000000000..4a8510479c --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/io.h @@ -0,0 +1,88 @@ +/** + * @file io.h + * + * @ingroup lpc176x + * + * @brief Input/output module methods definitions. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_IO_H +#define LIBBSP_ARM_LPC176X_IO_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Sets pin to the selected function. + * + * @param pin The pin to set. + * @param function Defines the function to set. + */ +void lpc176x_pin_select( + uint32_t pin, + lpc176x_pin_function function +); + +/** + * @brief Sets pin to the selected mode. + * + * @param pin The pin to set. + * @param mode Defines the mode to set. + */ +void lpc176x_pin_set_mode( + const uint32_t pin, + const lpc176x_pin_mode mode +); + +/** + * @brief Enables the module power and clock. + * + * @param module Represents the module to be enabled. + * @param clock Represents the clock to set for this module. + * @return RTEMS_SUCCESFULL if the module was enabled succesfully. + */ +rtems_status_code lpc176x_module_enable( + lpc176x_module module, + lpc176x_module_clock clock +); + +/** + * @brief Checks if the current module is turned off and disables a module. + * + * @param module Represents the module to be disabled. + * @return RTEMS_SUCCESFULL if the module was disabled succesfully. + */ +rtems_status_code lpc176x_module_disable( lpc176x_module module ); + +/** + * @brief Checks if the current module is enabled or not. + * + * @param module Represents the module to be checked. + * @return TRUE if the module is enabled. + * FALSE otherwise. + */ +bool lpc176x_module_is_enabled( lpc176x_module module ); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_IO_H */ diff --git a/bsps/arm/lpc176x/include/bsp/irq.h b/bsps/arm/lpc176x/include/bsp/irq.h new file mode 100644 index 0000000000..719608c8f7 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/irq.h @@ -0,0 +1,108 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief LPC176X interrupt definitions. + */ + +/* + * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_IRQ_H +#define LIBBSP_ARM_LPC176X_IRQ_H + +#ifndef ASM +#include +#include +#include +#endif + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define BSP_INTERRUPT_VECTOR_MIN 0U + +#define LPC176X_IRQ_WDT 0U +#define LPC176X_IRQ_TIMER_0 1U +#define LPC176X_IRQ_TIMER_1 2U +#define LPC176X_IRQ_TIMER_2 3U +#define LPC176X_IRQ_TIMER_3 4U +#define LPC176X_IRQ_UART_0 5U +#define LPC176X_IRQ_UART_1 6U +#define LPC176X_IRQ_UART_2 7U +#define LPC176X_IRQ_UART_3 8U +#define LPC176X_IRQ_PWM_1 9U +#define LPC176X_IRQ_PLL 16U +#define LPC176X_IRQ_RTC 17U +#define LPC176X_IRQ_EINT_0 18U +#define LPC176X_IRQ_EINT_1 19U +#define LPC176X_IRQ_EINT_2 20U +#define LPC176X_IRQ_EINT_3 21U +#define LPC176X_IRQ_ADC_0 22U +#define LPC176X_IRQ_BOD 23U +#define LPC176X_IRQ_USB 24U +#define LPC176X_IRQ_CAN 25U +#define LPC176X_IRQ_DMA 26U +#define LPC176X_IRQ_I2S 27U +#define LPC176X_IRQ_SD_MMC 29U +#define LPC176X_IRQ_MCPWM 30U +#define LPC176X_IRQ_QEI 31U +#define LPC176X_IRQ_PLL_ALT 32U +#define LPC176X_IRQ_USB_ACTIVITY 33U +#define LPC176X_IRQ_CAN_ACTIVITY 34U +#define LPC176X_IRQ_UART_4 35U +#define LPC176X_IRQ_GPIO 38U +#define LPC176X_IRQ_PWM 39U +#define LPC176X_IRQ_EEPROM 40U + +#define BSP_INTERRUPT_VECTOR_MAX 40 + +#define LPC176X_IRQ_PRIORITY_VALUE_MIN 0U + +#define LPC176X_IRQ_PRIORITY_VALUE_MAX 31U + +#define LPC176X_IRQ_PRIORITY_COUNT ( LPC176X_IRQ_PRIORITY_VALUE_MAX + 1U ) +#define LPC176X_IRQ_PRIORITY_HIGHEST LPC176X_IRQ_PRIORITY_VALUE_MIN +#define LPC176X_IRQ_PRIORITY_LOWEST LPC176X_IRQ_PRIORITY_VALUE_MAX + +#ifndef ASM + +/** + * @brief Sets the priority according to the current interruption. + * + * @param vector Interrupt to be attended. + * @param priority Interrupts priority. + */ +void lpc176x_irq_set_priority( + rtems_vector_number vector, + unsigned priority +); + +/** + * @brief Gets the priority number according to the current interruption. + * + * @param vector Interrupts to be attended. + * @return The priority number according to the current interruption. + */ +unsigned lpc176x_irq_get_priority( rtems_vector_number vector ); + +#endif /* ASM */ + +/** @} */ + +#endif /* LIBBSP_ARM_LPC176X_IRQ_H */ diff --git a/bsps/arm/lpc176x/include/bsp/lpc-clock-config.h b/bsps/arm/lpc176x/include/bsp/lpc-clock-config.h new file mode 100644 index 0000000000..3eef02152e --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/lpc-clock-config.h @@ -0,0 +1,45 @@ +/** + * @file + * + * @ingroup lpc176x + * + * @brief Clock driver configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_LPC_CLOCK_CONFIG_H +#define LIBBSP_ARM_LPC176X_LPC_CLOCK_CONFIG_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define LPC_CLOCK_INTERRUPT LPC176X_IRQ_TIMER_0 +#define LPC_CLOCK_TIMER_BASE TMR0_BASE_ADDR +#define LPC_CLOCK_TIMECOUNTER_BASE TMR1_BASE_ADDR +#define LPC_CLOCK_REFERENCE LPC176X_PCLK +#define LPC_CLOCK_MODULE_ENABLE() \ + lpc176x_module_enable( LPC176X_MODULE_TIMER_0, LPC176X_MODULE_PCLK_DEFAULT ) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_LPC_CLOCK_CONFIG_H */ diff --git a/bsps/arm/lpc176x/include/bsp/lpc-gpio.h b/bsps/arm/lpc176x/include/bsp/lpc-gpio.h new file mode 100644 index 0000000000..9cb23df142 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/lpc-gpio.h @@ -0,0 +1,100 @@ +/** + * @file lpc-gpio.h + * + * @ingroup lpc176x + * + * @brief API of the GPIO driver for the lpc176x bsp in RTEMS. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_GPIO_H +#define LIBBSP_ARM_LPC176X_GPIO_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Configures the pin as input or output GPIO. + * + * @param pin The pin to configure + * @param dir Input or output. + */ +rtems_status_code lpc176x_gpio_config( + lpc176x_pin_number pin, + lpc176x_gpio_direction dir +); + +/** + * @brief Configures the pin as input, enables interrupt for an + * edge/s and sets isrfunct as the function to call when that + * interrupt occurs. + * + * @param pin The pin to configure. + * @param edge Which edge or edges will activate the interrupt. + * @param isrfunct The function that is called when the interrupt occurs. + * @return RTEMS_SUCCESSFULL if the configurations was success. + */ +rtems_status_code lpc176x_gpio_config_input_with_interrupt( + lpc176x_pin_number pin, + lpc176x_gpio_interrupt edge, + lpc176x_gpio_interrupt_function isrfunct +); + +/** + * @brief Sets the output pin to 1. + * + * @param pin The pin to set + */ +rtems_status_code lpc176x_gpio_set_pin( lpc176x_pin_number pin ); + +/** + * @brief Sets the output pin to 0. + * + * @param pin The pin to set + */ +rtems_status_code lpc176x_gpio_clear_pin( lpc176x_pin_number pin ); + +/** + * @brief Sets the output pin to 0 or 1 according to value. + * + * @param pin The pin to set + * @param value the value to set. + */ +rtems_status_code lpc176x_gpio_write_pin( + lpc176x_pin_number pin, + bool value +); + +/** + * @brief Returns the value at the given input pin. + * + * @param pin The pin where to read the value. + * @param pin_value TRUE if the pin value was getted successfuly. + * @return RTEMS_SUCCESSFUL if the pin value was getted successfuly. + */ +rtems_status_code lpc176x_gpio_get_pin_value( + lpc176x_pin_number pin, + bool *pin_value +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_GPIO_H */ diff --git a/bsps/arm/lpc176x/include/bsp/lpc176x.h b/bsps/arm/lpc176x/include/bsp/lpc176x.h new file mode 100644 index 0000000000..f10991f346 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/lpc176x.h @@ -0,0 +1,1585 @@ +/** + * @file lpc176x.h + * + * @ingroup lpc176x + * + * @brief Specific register definitions according to lpc176x family boards. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_H +#define LIBBSP_ARM_LPC176X_H + +#include + +#define LPC176X_PLL_CON_PLLE BSP_BIT32( 0 ) +#define LPC176X_PLL_CON_PLLC BSP_BIT32( 1 ) +#define LPC176X_PLL_SEL_MSEL( val ) BSP_FLD32( val, 0, 14 ) +#define LPC176X_PLL_SEL_MSEL_GET( reg ) BSP_FLD32GET( reg, 0, 14 ) +#define LPC176X_PLL_SEL_MSEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 14 ) +#define LPC176X_PLL_SEL_PSEL( val ) BSP_FLD32( val, 16, 23 ) +#define LPC176X_PLL_SEL_PSEL_GET( reg ) BSP_FLD32GET( reg, 16, 23 ) +#define LPC176X_PLL_SEL_PSEL_SET( reg, val ) BSP_FLD32SET( reg, val, 16, 23 ) +#define LPC176X_PLL_STAT_PLLE BSP_BIT32( 24 ) +#define LPC176X_PLL_STAT_PLLC BSP_BIT32( 25 ) +#define LPC176X_PLL_STAT_PLOCK BSP_BIT32( 26 ) + +/** + * @brief Phase-Locked Loop representation. + */ +typedef struct { + /** + * @brief PLL Control Register. + */ + uint32_t con; + /** + * @brief PLL Configuration Register. + */ + uint32_t cfg; + /** + * @brief PLL Status Register. + */ + uint32_t stat; + /** + * @brief PLL Feed Register. + */ + uint32_t feed; +} lpc176x_pll; + +#define LPC176X_SCB_BASE_ADDR 0x400FC000U +#define LPC176X_SCB_FLASHCFG_FLASHTIM( val ) BSP_FLD32( val, 12, 15 ) +#define LPC176X_SCB_FLASHCFG_FLASHTIM_GET( reg ) BSP_FLD32GET( reg, 12, 15 ) +#define LPC176X_SCB_FLASHCFG_FLASHTIM_SET( reg, val ) BSP_FLD32SET( reg, val, \ + 12, 15 ) +#define LPC176X_SCB_MEMMAP_MAP BSP_BIT32( 0 ) +/* POWER MODE CONTROL REGISTER (PCON) */ +/* Power mode control bit 0 */ +#define LPC176X_SCB_PCON_PM0 BSP_BIT32( 0 ) +/* Power mode control bit 1 */ +#define LPC176X_SCB_PCON_PM1 BSP_BIT32( 1 ) +/* Brown-Out Reduced ower Down */ +#define LPC176X_SCB_PCON_BODRPM BSP_BIT32( 2 ) +/* Brown-Out Global Disable */ +#define LPC176X_SCB_PCON_BOGD BSP_BIT32( 3 ) +/* Brown-Out Reset Disable */ +#define LPC176X_SCB_PCON_BORD BSP_BIT32( 4 ) +/* Sleep Mode entry flag */ +#define LPC176X_SCB_PCON_SMFLAG BSP_BIT32( 8 ) +/* Deep Sleep entry flag */ +#define LPC176X_SCB_PCON_DSFLAG BSP_BIT32( 9 ) +/* Power-Down entry flag */ +#define LPC176X_SCB_PCON_PDFLAG BSP_BIT32( 10 ) +/* Deep Power-Down entry flag */ +#define LPC176X_SCB_PCON_DPDFLAG BSP_BIT32( 11 ) +/* POWER CONTROL for PERIPHERALS REGISTER (PCONP) */ +/* 0 - Reserved */ +/* Timer/Counter 0 power/clock control bit */ +#define LPC176X_SCB_PCONP_TIMER_0 BSP_BIT32( 1 ) +/* Timer/Counter 1 power/clock control bit */ +#define LPC176X_SCB_PCONP_TIMER_1 BSP_BIT32( 2 ) +/* UART 0 power/clock control bit */ +#define LPC176X_SCB_PCONP_UART_0 BSP_BIT32( 3 ) +/* UART 1 power/clock control bit */ +#define LPC176X_SCB_PCONP_UART_1 BSP_BIT32( 4 ) +/* 5 - Reserved */ +/* PWM 1 power/clock control bit */ +#define LPC176X_SCB_PCONP_PWM_0 BSP_BIT32( 6 ) +/* The I2C0 interface power/clock control bit */ +#define LPC176X_SCB_PCONP_I2C_0 BSP_BIT32( 7 ) +/* The SPI interface power/clock control bit */ +#define LPC176X_SCB_PCONP_SPI BSP_BIT32( 8 ) +/* The RTC power/clock control bit */ +#define LPC176X_SCB_PCONP_RTC BSP_BIT32( 9 ) +/* The SSP1 interface power/clock control bit */ +#define LPC176X_SCB_PCONP_SSP_1 BSP_BIT32( 10 ) +/* 11 - Reserved */ +/* A/D converter (ADC) power/clock control bit */ +#define LPC176X_SCB_PCONP_ADC BSP_BIT32( 12 ) +/* CAN Controller 1 power/clock control bit */ +#define LPC176X_SCB_PCONP_CAN_1 BSP_BIT32( 13 ) +/* CAN Controller 2 power/clock control bit */ +#define LPC176X_SCB_PCONP_CAN_2 BSP_BIT32( 14 ) +/* Power/clock control bit for IOCON, GPIO, and GPIO interrupts*/ +#define LPC176X_SCB_PCONP_GPIO BSP_BIT32( 15 ) +/* Repetitive Interrupt Timer power/clock control bit */ +#define LPC176X_SCB_PCONP_RIT BSP_BIT32( 16 ) +/* Motor Control PWM */ +#define LPC176X_SCB_PCONP_MCPWM BSP_BIT32( 17 ) +/* Quadrate Encoder Interface power/clock control bit */ +#define LPC176X_SCB_PCONP_QEI BSP_BIT32( 18 ) +/* The IC21 interface power/clock control bit */ +#define LPC176X_SCB_PCONP_I2C_1 BSP_BIT32( 19 ) +/* 20 - Reserved */ +/* The SSP0 interface power/clock control bit */ +#define LPC176X_SCB_PCONP_SSP_0 BSP_BIT32( 21 ) +/* Timer 2 power/clock control bit */ +#define LPC176X_SCB_PCONP_TIMER_2 BSP_BIT32( 22 ) +/* Timer 3 power/clock control bit */ +#define LPC176X_SCB_PCONP_TIMER_3 BSP_BIT32( 23 ) +/* UART 2 power/clock control bit */ +#define LPC176X_SCB_PCONP_UART_2 BSP_BIT32( 24 ) +/* UART 3 power/clock control bit */ +#define LPC176X_SCB_PCONP_UART_3 BSP_BIT32( 25 ) +/* I2C interface 2 power/clock control bit */ +#define LPC176X_SCB_PCONP_I2C_2 BSP_BIT32( 26 ) +/* I2S interface power/clock control bit */ +#define LPC176X_SCB_PCONP_I2S BSP_BIT32( 27 ) +/* 28 - Reserved */ +/* GPDMA function power/clock control bit */ +#define LPC176X_SCB_PCONP_GPDMA BSP_BIT32( 29 ) +/* Ethernet block power/clock control bit */ +#define LPC176X_SCB_PCONP_ENET BSP_BIT32( 30 ) +/* USB interface power/clock control bit */ +#define LPC176X_SCB_PCONP_USB BSP_BIT32( 31 ) +#define LPC176X_SCB_CCLKSEL_CCLKDIV( val ) BSP_FLD32( val, 0, 7 ) +#define LPC176X_SCB_CCLKSEL_CCLKDIV_GET( reg ) BSP_FLD32GET( reg, 0, 7 ) +#define LPC176X_SCB_CCLKSEL_CCLKDIV_SET( reg, val ) BSP_FLD32SET( reg, \ + val, \ + 0, \ + 7 ) +#define LPC176X_SCB_CCLKSEL_CCLKSEL BSP_BIT32( 8 ) +#define LPC176X_SCB_USBCLKSEL_USBDIV( val ) BSP_FLD32( val, 0, 4 ) +#define LPC176X_SCB_USBCLKSEL_USBDIV_GET( reg ) BSP_FLD32GET( reg, 0, 4 ) +#define LPC176X_SCB_USBCLKSEL_USBDIV_SET( reg, val ) BSP_FLD32SET( reg, \ + val, \ + 0, \ + 4 ) +#define LPC176X_SCB_USBCLKSEL_USBSEL( val ) BSP_FLD32( val, 8, 9 ) +#define LPC176X_SCB_USBCLKSEL_USBSEL_GET( reg ) BSP_FLD32GET( reg, 8, 9 ) +#define LPC176X_SCB_USBCLKSEL_USBSEL_SET( reg, val ) BSP_FLD32SET( reg, \ + val, \ + 8, \ + 9 ) +#define LPC176X_SCB_CLKSRCSEL_CLKSRC BSP_BIT32( 0 ) +#define LPC176X_SCB_SCS_MCIPWR BSP_BIT32( 3 ) +#define LPC176X_SCB_SCS_OSC_RANGE_SEL BSP_BIT32( 4 ) +#define LPC176X_SCB_SCS_OSC_ENABLE BSP_BIT32( 5 ) +#define LPC176X_SCB_SCS_OSC_STATUS BSP_BIT32( 6 ) +#define LPC176X_SCB_PCLKSEL_PCLKDIV( val ) BSP_FLD32( val, 0, 4 ) +#define LPC176X_SCB_PCLKSEL_PCLKDIV_GET( reg ) BSP_FLD32GET( reg, 0, 4 ) +#define LPC176X_SCB_PCLKSEL_PCLKDIV_SET( reg, val ) BSP_FLD32SET( reg, \ + val, \ + 0, \ + 4 ) +#define LPC176X_SCB_PBOOST_BOOST BSP_BIT32( 0 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL( val ) BSP_FLD32( val, 3, 0 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL_GET( reg ) BSP_FLD32GET( reg, 3, 0 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL_SET( reg, val ) BSP_FLD32SET( reg, \ + val, 3, 0 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV( val ) BSP_FLD32( val, 7, 4 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV_GET( reg ) BSP_FLD32GET( reg, 7, 4 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV_SET( reg, val ) BSP_FLD32SET( reg, \ + val, 7, 4 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32( 8 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32( 9 ) + +/** + * @brief System Control Block representation. + */ +typedef struct { + /** + * @brief Flash Accelerator Configuration Register. + */ + uint32_t flashcfg; + uint32_t reserved_04[ 15 ]; + /** + * @brief Memopry Map Control. + */ + uint32_t memmap; + uint32_t reserved_44[ 15 ]; + /** + * @brief Phase-Locked Loop 0. + */ + lpc176x_pll pll_0; + uint32_t reserved_90[ 4 ]; + /** + * @brief Phase-Locked Loop 1. + */ + lpc176x_pll pll_1; + uint32_t reserved_b0[ 4 ]; + /** + * @brief Power Mode Control register. + */ + uint32_t pcon; + /** + * @brief Power Control for Peripherals register. + */ + uint32_t pconp; + uint32_t reserved_c8[ 15 ]; + /** + *@brief Selects the divide valuefor creating the CPU clock from the + * PPL0 output. + */ + uint32_t cclksel; + /** + * @brief Selects the divide value for creating the USB clock from the + * PPL0 output. + */ + uint32_t usbclksel; + /** + * @brief Clock Source Select register. + */ + uint32_t clksrcsel; + uint32_t reserved_110[ 12 ]; + /** + * @brief External Interrupt flag register. + */ + uint32_t extint; + uint32_t reserved_144; + /** + * @brief External Interrupt Mode register. + */ + uint32_t extmode; + /** + * @brief External Interrupt Polarity register. + */ + uint32_t extpolar; + uint32_t reserved_150[ 12 ]; + /** + * @brief Reset Source Identification Register. + */ + uint32_t rsid; + uint32_t reserved_184[ 7 ]; + /** + * @brief System Controls and Status Register. + */ + uint32_t scs; + uint32_t reserved_1a4; + /** + * @brief Peripheral Clock Selection registers 0 and 1. + */ + uint32_t pclksel[ 2 ]; + /** + * @brief Peripheral boost. + */ + uint32_t pboost; + uint32_t reserved_1b4[ 5 ]; + /** + * @brief Clock Output Configuration Register. + */ + uint32_t clkoutcfg; + /** + * @brief Reset Control bit 0 and 1. + */ + uint32_t rstcon[ 2 ]; + uint32_t reserved_1d4[ 4 ]; +} lpc176x_scb; + +#define LPC176X_BASE 0x00u +#define LPC176X_SCB ( *(volatile lpc176x_scb *) ( LPC176X_SCB_BASE_ADDR ) ) + +/* Fast I/O setup */ +#define LPC176X_FIO_BASE_ADDR 0x2009C000U +#define LPC176X_FIO ( (volatile lpc176x_fio *) LPC176X_FIO_BASE_ADDR ) + +#define FIO0DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) ) +#define FIO0MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) ) +#define FIO0PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) ) +#define FIO0SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) ) +#define FIO0CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) ) + +#define FIO1DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) ) +#define FIO1MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) ) +#define FIO1PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) ) +#define FIO1SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) ) +#define FIO1CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) ) + +#define FIO2DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) ) +#define FIO2MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) ) +#define FIO2PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) ) +#define FIO2SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) ) +#define FIO2CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) ) + +#define FIO3DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) ) +#define FIO3MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) ) +#define FIO3PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) ) +#define FIO3SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) ) +#define FIO3CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) ) + +#define FIO4DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) ) +#define FIO4MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) ) +#define FIO4PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) ) +#define FIO4SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) ) +#define FIO4CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) ) + +/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ +#define FIO0DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) ) +#define FIO1DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) ) +#define FIO2DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) ) +#define FIO3DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) ) +#define FIO4DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) ) + +#define FIO0DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x01U ) ) +#define FIO1DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x21U ) ) +#define FIO2DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x41U ) ) +#define FIO3DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x61U ) ) +#define FIO4DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x81U ) ) + +#define FIO0DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x02U ) ) +#define FIO1DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x22U ) ) +#define FIO2DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x42U ) ) +#define FIO3DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x62U ) ) +#define FIO4DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x82U ) ) + +#define FIO0DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x03U ) ) +#define FIO1DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x23U ) ) +#define FIO2DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x43U ) ) +#define FIO3DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x63U ) ) +#define FIO4DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x83U ) ) + +#define FIO0DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) ) +#define FIO1DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) ) +#define FIO2DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) ) +#define FIO3DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) ) +#define FIO4DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) ) + +#define FIO0DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x02U ) ) +#define FIO1DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x22U ) ) +#define FIO2DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x42U ) ) +#define FIO3DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x62U ) ) +#define FIO4DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x82U ) ) + +#define FIO0MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) ) +#define FIO1MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) ) +#define FIO2MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) ) +#define FIO3MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) ) +#define FIO4MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) ) + +#define FIO0MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x11U ) ) +#define FIO1MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x21U ) ) +#define FIO2MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x51U ) ) +#define FIO3MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x71U ) ) +#define FIO4MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x91U ) ) + +#define FIO0MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x12U ) ) +#define FIO1MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x32U ) ) +#define FIO2MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x52U ) ) +#define FIO3MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x72U ) ) +#define FIO4MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x92U ) ) + +#define FIO0MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x13U ) ) +#define FIO1MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x33U ) ) +#define FIO2MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x53U ) ) +#define FIO3MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x73U ) ) +#define FIO4MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x93U ) ) + +#define FIO0MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) ) +#define FIO1MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) ) +#define FIO2MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) ) +#define FIO3MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) ) +#define FIO4MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) ) + +#define FIO0MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x12U ) ) +#define FIO1MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x32U ) ) +#define FIO2MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x52U ) ) +#define FIO3MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x72U ) ) +#define FIO4MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x92U ) ) + +#define FIO0PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) ) +#define FIO1PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) ) +#define FIO2PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) ) +#define FIO3PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) ) +#define FIO4PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) ) + +#define FIO0PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x15U ) ) +#define FIO1PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x25U ) ) +#define FIO2PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x55U ) ) +#define FIO3PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x75U ) ) +#define FIO4PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x95U ) ) + +#define FIO0PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x16U ) ) +#define FIO1PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x36U ) ) +#define FIO2PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x56U ) ) +#define FIO3PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x76U ) ) +#define FIO4PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x96U ) ) + +#define FIO0PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x17U ) ) +#define FIO1PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x37U ) ) +#define FIO2PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x57U ) ) +#define FIO3PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x77U ) ) +#define FIO4PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x97U ) ) + +#define FIO0PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) ) +#define FIO1PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) ) +#define FIO2PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) ) +#define FIO3PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) ) +#define FIO4PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) ) + +#define FIO0PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x16U ) ) +#define FIO1PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x36U ) ) +#define FIO2PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x56U ) ) +#define FIO3PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x76U ) ) +#define FIO4PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x96U ) ) + +#define FIO0SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) ) +#define FIO1SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) ) +#define FIO2SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) ) +#define FIO3SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) ) +#define FIO4SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) ) + +#define FIO0SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x19U ) ) +#define FIO1SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x29U ) ) +#define FIO2SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x59U ) ) +#define FIO3SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x79U ) ) +#define FIO4SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x99U ) ) + +#define FIO0SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1AU ) ) +#define FIO1SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3AU ) ) +#define FIO2SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5AU ) ) +#define FIO3SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7AU ) ) +#define FIO4SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9AU ) ) + +#define FIO0SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1BU ) ) +#define FIO1SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3BU ) ) +#define FIO2SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5BU ) ) +#define FIO3SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7BU ) ) +#define FIO4SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9BU ) ) + +#define FIO0SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) ) +#define FIO1SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) ) +#define FIO2SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) ) +#define FIO3SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) ) +#define FIO4SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) ) + +#define FIO0SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1AU ) ) +#define FIO1SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3AU ) ) +#define FIO2SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5AU ) ) +#define FIO3SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7AU ) ) +#define FIO4SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x9AU ) ) + +#define FIO0CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) ) +#define FIO1CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) ) +#define FIO2CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) ) +#define FIO3CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) ) +#define FIO4CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) ) + +#define FIO0CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1DU ) ) +#define FIO1CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x2DU ) ) +#define FIO2CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5DU ) ) +#define FIO3CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7DU ) ) +#define FIO4CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9DU ) ) + +#define FIO0CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1EU ) ) +#define FIO1CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3EU ) ) +#define FIO2CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5EU ) ) +#define FIO3CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7EU ) ) +#define FIO4CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9EU ) ) + +#define FIO0CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1FU ) ) +#define FIO1CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3FU ) ) +#define FIO2CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5FU ) ) +#define FIO3CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7FU ) ) +#define FIO4CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9FU ) ) + +#define FIO0CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) ) +#define FIO1CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) ) +#define FIO2CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) ) +#define FIO3CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) ) +#define FIO4CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) ) + +#define FIO0CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1EU ) ) +#define FIO1CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3EU ) ) +#define FIO2CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5EU ) ) +#define FIO3CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7EU ) ) +#define FIO4CLRU ( *(volatile uint16_t *) ( FIO_BASE_ADDR + 0x9EU ) ) + +#define LPC176X_USB_CLOCK 48000000U +#define LPC176X_MODULE_CLOCK_MASK 0x3U + +/* Pin Connect Block */ +#define PINSEL_BASE_ADDR 0x4002C000U + +#define PINSEL0 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x00U ) ) +#define PINSEL1 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x04U ) ) +#define PINSEL2 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x08U ) ) +#define PINSEL3 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x0CU ) ) +#define PINSEL4 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x10U ) ) +#define PINSEL5 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x14U ) ) +#define PINSEL6 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x18U ) ) +#define PINSEL7 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x1CU ) ) +#define PINSEL8 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x20U ) ) +#define PINSEL9 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x24U ) ) +#define PINSEL10 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x28U ) ) +#define PINSEL11 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x2CU ) ) + +#define PINMODE0 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x40U ) ) +#define PINMODE1 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x44U ) ) +#define PINMODE2 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x48U ) ) +#define PINMODE3 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x4CU ) ) +#define PINMODE4 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x50U ) ) +#define PINMODE5 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x54U ) ) +#define PINMODE6 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x58U ) ) +#define PINMODE7 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x5CU ) ) +#define PINMODE8 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x60U ) ) +#define PINMODE9 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x64U ) ) + +/* Pulse Width Modulator (PWM) */ +#define PWM0_BASE_ADDR 0x40014000 + +#define PWM0IR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x00 ) ) +#define PWM0TCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x04 ) ) +#define PWM0TC ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x08 ) ) +#define PWM0PR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x0C ) ) +#define PWM0PC ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x10 ) ) +#define PWM0MCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x14 ) ) +#define PWM0MR0 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x18 ) ) +#define PWM0MR1 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x1C ) ) +#define PWM0MR2 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x20 ) ) +#define PWM0MR3 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x24 ) ) +#define PWM0CCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x28 ) ) +#define PWM0CR0 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x2C ) ) +#define PWM0CR1 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x30 ) ) +#define PWM0CR2 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x34 ) ) +#define PWM0CR3 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x38 ) ) +#define PWM0EMR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x3C ) ) +#define PWM0MR4 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x40 ) ) +#define PWM0MR5 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x44 ) ) +#define PWM0MR6 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x48 ) ) +#define PWM0PCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x4C ) ) +#define PWM0LER ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x50 ) ) +#define PWM0CTCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x70 ) ) + +#define PWM1_BASE_ADDR 0x40018000 + +#define PWM1IR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x00 ) ) +#define PWM1TCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x04 ) ) +#define PWM1TC ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x08 ) ) +#define PWM1PR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x0C ) ) +#define PWM1PC ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x10 ) ) +#define PWM1MCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x14 ) ) +#define PWM1MR0 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x18 ) ) +#define PWM1MR1 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x1C ) ) +#define PWM1MR2 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x20 ) ) +#define PWM1MR3 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x24 ) ) +#define PWM1CCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x28 ) ) +#define PWM1CR0 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x2C ) ) +#define PWM1CR1 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x30 ) ) +#define PWM1CR2 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x34 ) ) +#define PWM1CR3 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x38 ) ) +#define PWM1EMR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x3C ) ) +#define PWM1MR4 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x40 ) ) +#define PWM1MR5 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x44 ) ) +#define PWM1MR6 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x48 ) ) +#define PWM1PCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x4C ) ) +#define PWM1LER ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x50 ) ) +#define PWM1CTCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x70 ) ) + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define UART0_BASE_ADDR 0x4000C000 + +#define U0RBR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) ) +#define U0THR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) ) +#define U0DLL ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) ) +#define U0DLM ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x04 ) ) +#define U0IER ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x04 ) ) +#define U0IIR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x08 ) ) +#define U0FCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x08 ) ) +#define U0LCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x0C ) ) +#define U0LSR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x14 ) ) +#define U0SCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x1C ) ) +#define U0ACR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x20 ) ) +#define U0ICR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x24 ) ) +#define U0FDR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x28 ) ) +#define U0TER ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x30 ) ) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define UART1_BASE_ADDR 0x40010000 + +#define U1RBR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) ) +#define U1THR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) ) +#define U1DLL ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) ) +#define U1DLM ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x04 ) ) +#define U1IER ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x04 ) ) +#define U1IIR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x08 ) ) +#define U1FCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x08 ) ) +#define U1LCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x0C ) ) +#define U1MCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x10 ) ) +#define U1LSR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x14 ) ) +#define U1MSR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x18 ) ) +#define U1SCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x1C ) ) +#define U1ACR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x20 ) ) +#define U1FDR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x28 ) ) +#define U1TER ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x30 ) ) + +/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ +#define UART2_BASE_ADDR 0x40098000 + +#define U2RBR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) ) +#define U2THR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) ) +#define U2DLL ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) ) +#define U2DLM ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x04 ) ) +#define U2IER ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x04 ) ) +#define U2IIR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x08 ) ) +#define U2FCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x08 ) ) +#define U2LCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x0C ) ) +#define U2LSR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x14 ) ) +#define U2SCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x1C ) ) +#define U2ACR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x20 ) ) +#define U2ICR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x24 ) ) +#define U2FDR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x28 ) ) +#define U2TER ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x30 ) ) + +/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ +#define UART3_BASE_ADDR 0x4009C000 + +#define U3RBR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) ) +#define U3THR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) ) +#define U3DLL ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) ) +#define U3DLM ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x04 ) ) +#define U3IER ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x04 ) ) +#define U3IIR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x08 ) ) +#define U3FCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x08 ) ) +#define U3LCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x0C ) ) +#define U3LSR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x14 ) ) +#define U3SCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x1C ) ) +#define U3ACR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x20 ) ) +#define U3ICR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x24 ) ) +#define U3FDR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x28 ) ) +#define U3TER ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x30 ) ) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define SPI0_BASE_ADDR 0xE0020000 +#define S0SPCR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x00 ) ) +#define S0SPSR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x04 ) ) +#define S0SPDR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x08 ) ) +#define S0SPCCR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x0C ) ) +#define S0SPINT ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x1C ) ) + +/* Real Time Clock */ +#define RTC_BASE_ADDR 0x40024000 + +#define RTC_ILR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x00 ) ) +#define RTC_CTC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x04 ) ) +#define RTC_CCR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x08 ) ) +#define RTC_CIIR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x0C ) ) +#define RTC_AMR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x10 ) ) +#define RTC_CTIME0 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x14 ) ) +#define RTC_CTIME1 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x18 ) ) +#define RTC_CTIME2 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x1C ) ) +#define RTC_SEC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x20 ) ) +#define RTC_MIN ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x24 ) ) +#define RTC_HOUR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x28 ) ) +#define RTC_DOM ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x2C ) ) +#define RTC_DOW ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x30 ) ) +#define RTC_DOY ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x34 ) ) +#define RTC_MONTH ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x38 ) ) +#define RTC_YEAR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x3C ) ) +#define RTC_CISS ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x40 ) ) +#define RTC_ALSEC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x60 ) ) +#define RTC_ALMIN ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x64 ) ) +#define RTC_ALHOUR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x68 ) ) +#define RTC_ALDOM ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x6C ) ) +#define RTC_ALDOW ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x70 ) ) +#define RTC_ALDOY ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x74 ) ) +#define RTC_ALMON ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x78 ) ) +#define RTC_ALYEAR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x7C ) ) +#define RTC_PREINT ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x80 ) ) +#define RTC_PREFRAC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x84 ) ) + +/* A/D Converter 0 (AD0) */ +#define AD0_BASE_ADDR 0x40034000 + +#define AD0CR ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x00 ) ) +#define AD0GDR ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x04 ) ) +#define AD0INTEN ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x0C ) ) +#define AD0_DATA_START ( (volatile uint32_t *) ( AD0_BASE_ADDR + 0x10 ) ) +#define AD0DR0 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x10 ) ) +#define AD0DR1 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x14 ) ) +#define AD0DR2 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x18 ) ) +#define AD0DR3 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x1C ) ) +#define AD0DR4 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x20 ) ) +#define AD0DR5 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x24 ) ) +#define AD0DR6 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x28 ) ) +#define AD0DR7 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x2C ) ) +#define AD0STAT ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x30 ) ) + +/* D/A Converter */ +#define DAC_BASE_ADDR 0x4008C000 + +#define DACR ( *(volatile uint32_t *) ( DAC_BASE_ADDR + 0x00 ) ) + +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#define CAN_ACCEPT_BASE_ADDR 0x4003C000 + +#define CAN_AFMR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x00 ) ) +#define CAN_SFF_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x04 ) ) +#define CAN_SFF_GRP_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \ + 0x08 ) ) +#define CAN_EFF_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x0C ) ) +#define CAN_EFF_GRP_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \ + 0x10 ) ) +#define CAN_EOT ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x14 ) ) +#define CAN_LUT_ERR_ADR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \ + 0x18 ) ) +#define CAN_LUT_ERR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x1C ) ) + +#define CAN_CENTRAL_BASE_ADDR 0x40040000 + +#define CAN_TX_SR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x00 ) ) +#define CAN_RX_SR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x04 ) ) +#define CAN_MSR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x08 ) ) + +#define CAN1_BASE_ADDR 0x40044000 + +#define CAN1MOD ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x00 ) ) +#define CAN1CMR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x04 ) ) +#define CAN1GSR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x08 ) ) +#define CAN1ICR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x0C ) ) +#define CAN1IER ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x10 ) ) +#define CAN1BTR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x14 ) ) +#define CAN1EWL ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x18 ) ) +#define CAN1SR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x1C ) ) +#define CAN1RFS ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x20 ) ) +#define CAN1RID ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x24 ) ) +#define CAN1RDA ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x28 ) ) +#define CAN1RDB ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x2C ) ) + +#define CAN1TFI1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x30 ) ) +#define CAN1TID1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x34 ) ) +#define CAN1TDA1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x38 ) ) +#define CAN1TDB1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x3C ) ) +#define CAN1TFI2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x40 ) ) +#define CAN1TID2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x44 ) ) +#define CAN1TDA2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x48 ) ) +#define CAN1TDB2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x4C ) ) +#define CAN1TFI3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x50 ) ) +#define CAN1TID3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x54 ) ) +#define CAN1TDA3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x58 ) ) +#define CAN1TDB3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x5C ) ) + +#define CAN2_BASE_ADDR 0x40048000 + +#define CAN2MOD ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x00 ) ) +#define CAN2CMR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x04 ) ) +#define CAN2GSR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x08 ) ) +#define CAN2ICR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x0C ) ) +#define CAN2IER ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x10 ) ) +#define CAN2BTR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x14 ) ) +#define CAN2EWL ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x18 ) ) +#define CAN2SR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x1C ) ) +#define CAN2RFS ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x20 ) ) +#define CAN2RID ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x24 ) ) +#define CAN2RDA ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x28 ) ) +#define CAN2RDB ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x2C ) ) + +#define CAN2TFI1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x30 ) ) +#define CAN2TID1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x34 ) ) +#define CAN2TDA1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x38 ) ) +#define CAN2TDB1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x3C ) ) +#define CAN2TFI2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x40 ) ) +#define CAN2TID2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x44 ) ) +#define CAN2TDA2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x48 ) ) +#define CAN2TDB2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x4C ) ) +#define CAN2TFI3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x50 ) ) +#define CAN2TID3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x54 ) ) +#define CAN2TDA3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x58 ) ) +#define CAN2TDB3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x5C ) ) + +/* MultiMedia Card Interface(MCI) Controller */ +#define MCI_BASE_ADDR 0x400c0000 + +#define MCI_POWER ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x00 ) ) +#define MCI_CLOCK ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x04 ) ) +#define MCI_ARGUMENT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x08 ) ) +#define MCI_COMMAND ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x0C ) ) +#define MCI_RESP_CMD ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x10 ) ) +#define MCI_RESP0 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x14 ) ) +#define MCI_RESP1 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x18 ) ) +#define MCI_RESP2 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x1C ) ) +#define MCI_RESP3 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x20 ) ) +#define MCI_DATA_TMR ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x24 ) ) +#define MCI_DATA_LEN ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x28 ) ) +#define MCI_DATA_CTRL ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x2C ) ) +#define MCI_DATA_CNT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x30 ) ) +#define MCI_STATUS ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x34 ) ) +#define MCI_CLEAR ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x38 ) ) +#define MCI_MASK0 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x3C ) ) +#define MCI_MASK1 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x40 ) ) +#define MCI_FIFO_CNT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x48 ) ) +#define MCI_FIFO ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x80 ) ) + +/* I2S Interface Controller (I2S) */ +#define I2S_BASE_ADDR 0x400a8000 + +#define I2S_DAO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x00 ) ) +#define I2S_DAI ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x04 ) ) +#define I2S_TX_FIFO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x08 ) ) +#define I2S_RX_FIFO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x0C ) ) +#define I2S_STATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x10 ) ) +#define I2S_DMA1 ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x14 ) ) +#define I2S_DMA2 ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x18 ) ) +#define I2S_IRQ ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x1C ) ) +#define I2S_TXRATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x20 ) ) +#define I2S_RXRATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x24 ) ) + +/* General-purpose DMA Controller */ +#define DMA_BASE_ADDR 0x50004000 + +#define GPDMA_INT_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x000 ) ) +#define GPDMA_INT_TCSTAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x004 ) ) +#define GPDMA_INT_TCCLR ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x008 ) ) +#define GPDMA_INT_ERR_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x00C ) ) +#define GPDMA_INT_ERR_CLR ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x010 ) ) +#define GPDMA_RAW_INT_TCSTAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + \ + 0x014 ) ) +#define GPDMA_RAW_INT_ERR_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + \ + 0x018 ) ) +#define GPDMA_ENABLED_CHNS ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x01C ) ) +#define GPDMA_SOFT_BREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x020 ) ) +#define GPDMA_SOFT_SREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x024 ) ) +#define GPDMA_SOFT_LBREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x028 ) ) +#define GPDMA_SOFT_LSREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x02C ) ) +#define GPDMA_CONFIG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x030 ) ) +#define GPDMA_SYNC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x034 ) ) + +/* DMA channel 0 registers */ +#define GPDMA_CH0_BASE_ADDR ( DMA_BASE_ADDR + 0x100 ) +#define GPDMA_CH0_SRC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x100 ) ) +#define GPDMA_CH0_DEST ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x104 ) ) +#define GPDMA_CH0_LLI ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x108 ) ) +#define GPDMA_CH0_CTRL ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x10C ) ) +#define GPDMA_CH0_CFG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x110 ) ) + +/* DMA channel 1 registers */ +#define GPDMA_CH1_BASE_ADDR ( DMA_BASE_ADDR + 0x120 ) +#define GPDMA_CH1_SRC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x120 ) ) +#define GPDMA_CH1_DEST ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x124 ) ) +#define GPDMA_CH1_LLI ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x128 ) ) +#define GPDMA_CH1_CTRL ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x12C ) ) +#define GPDMA_CH1_CFG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x130 ) ) + +/* USB Controller */ +#define USB_INT_BASE_ADDR 0x400fc1c0 +#define USB_BASE_ADDR 0x2008c200 + +#define USB_INT_STAT ( *(volatile uint32_t *) ( USB_INT_BASE_ADDR + 0x00 ) ) + +/* USB Device Interrupt Registers */ +#define DEV_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x00 ) ) +#define DEV_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x04 ) ) +#define DEV_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x08 ) ) +#define DEV_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x0C ) ) +#define DEV_INT_PRIO ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x2C ) ) + +/* USB Device Endpoint Interrupt Registers */ +#define EP_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x30 ) ) +#define EP_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x34 ) ) +#define EP_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x38 ) ) +#define EP_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x3C ) ) +#define EP_INT_PRIO ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x40 ) ) + +/* USB Device Endpoint Realization Registers */ +#define REALIZE_EP ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x44 ) ) +#define EP_INDEX ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x48 ) ) +#define MAXPACKET_SIZE ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x4C ) ) + +/* USB Device Command Reagisters */ +#define CMD_CODE ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x10 ) ) +#define CMD_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x14 ) ) + +/* USB Device Data Transfer Registers */ +#define RX_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x18 ) ) +#define TX_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x1C ) ) +#define RX_PLENGTH ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x20 ) ) +#define TX_PLENGTH ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x24 ) ) +#define USB_CTRL ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x28 ) ) + +/* USB Device DMA Registers */ +#define DMA_REQ_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x50 ) ) +#define DMA_REQ_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x54 ) ) +#define DMA_REQ_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x58 ) ) +#define UDCA_HEAD ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x80 ) ) +#define EP_DMA_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x84 ) ) +#define EP_DMA_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x88 ) ) +#define EP_DMA_DIS ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x8C ) ) +#define DMA_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x90 ) ) +#define DMA_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x94 ) ) +#define EOT_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA0 ) ) +#define EOT_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA4 ) ) +#define EOT_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA8 ) ) +#define NDD_REQ_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xAC ) ) +#define NDD_REQ_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB0 ) ) +#define NDD_REQ_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB4 ) ) +#define SYS_ERR_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB8 ) ) +#define SYS_ERR_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xBC ) ) +#define SYS_ERR_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xC0 ) ) + +/* USB Host Controller */ +#define USBHC_BASE_ADDR 0x2008c000 + +#define HC_REVISION ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x00 ) ) +#define HC_CONTROL ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x04 ) ) +#define HC_CMD_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x08 ) ) +#define HC_INT_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x0C ) ) +#define HC_INT_EN ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x10 ) ) +#define HC_INT_DIS ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x14 ) ) +#define HC_HCCA ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x18 ) ) +#define HC_PERIOD_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x1C ) ) +#define HC_CTRL_HEAD_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x20 ) ) +#define HC_CTRL_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x24 ) ) +#define HC_BULK_HEAD_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x28 ) ) +#define HC_BULK_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x2C ) ) +#define HC_DONE_HEAD ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x30 ) ) +#define HC_FM_INTERVAL ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x34 ) ) +#define HC_FM_REMAINING ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x38 ) ) +#define HC_FM_NUMBER ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x3C ) ) +#define HC_PERIOD_START ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x40 ) ) +#define HC_LS_THRHLD ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x44 ) ) +#define HC_RH_DESCA ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x48 ) ) +#define HC_RH_DESCB ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x4C ) ) +#define HC_RH_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x50 ) ) +#define HC_RH_PORT_STAT1 ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x54 ) ) +#define HC_RH_PORT_STAT2 ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x58 ) ) + +/* USB OTG Controller */ +#define USBOTG_BASE_ADDR 0x2008c100 + +#define OTG_INT_STAT ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x00 ) ) +#define OTG_INT_EN ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x04 ) ) +#define OTG_INT_SET ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x08 ) ) +#define OTG_INT_CLR ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x0C ) ) +#define OTG_STAT_CTRL ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x10 ) ) +#define OTG_TIMER ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x14 ) ) + +#define USBOTG_I2C_BASE_ADDR 0x2008c300 + +#define OTG_I2C_RX ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x00 ) ) +#define OTG_I2C_TX ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x00 ) ) +#define OTG_I2C_STS ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x04 ) ) +#define OTG_I2C_CTL ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x08 ) ) +#define OTG_I2C_CLKHI ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + \ + 0x0C ) ) +#define OTG_I2C_CLKLO ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + \ + 0x10 ) ) + +#define USBOTG_CLK_BASE_ADDR 0x2008CFF0U + +#define OTG_CLK_CTRL ( *(volatile uint32_t *) ( USBOTG_CLK_BASE_ADDR + \ + 0x04U ) ) +#define OTG_CLK_STAT ( *(volatile uint32_t *) ( USBOTG_CLK_BASE_ADDR + \ + 0x08U ) ) + +/* Register Fields */ +#define GET_FIELD( val, mask, shift ) \ + ( ( ( val ) & ( mask ) ) >> ( shift ) ) + +#define SET_FIELD( val, field, mask, shift ) \ + ( ( ( val ) & ~( mask ) ) | ( ( ( field ) << ( shift ) ) & ( mask ) ) ) + +/* CLKSRCSEL */ +#define CLKSRCSEL_CLKSRC_MASK 0x00000003U + +#define GET_CLKSRCSEL_CLKSRC( reg ) \ + GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0 ) + +#define SET_CLKSRCSEL_CLKSRC( reg, val ) \ + SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0 ) + +/* PLLCON */ +#define PLLCON_PLLE 0x00000001U + +#define PLLCON_PLLC 0x00000002U + +/* PLLCFG */ +#define PLLCFG_MSEL_MASK 0x00007fffU + +#define GET_PLLCFG_MSEL( reg ) \ + GET_FIELD( reg, PLLCFG_MSEL_MASK, 0 ) + +#define SET_PLLCFG_MSEL( reg, val ) \ + SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0 ) + +#define PLLCFG_NSEL_MASK 0x00ff0000U + +#define GET_PLLCFG_NSEL( reg ) \ + GET_FIELD( reg, PLLCFG_NSEL_MASK, 16 ) + +#define SET_PLLCFG_NSEL( reg, val ) \ + SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16 ) + +/* PLLSTAT */ +#define PLLSTAT_MSEL_MASK 0x00007fffU + +#define GET_PLLSTAT_MSEL( reg ) \ + GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0 ) + +#define SET_PLLSTAT_MSEL( reg, val ) \ + SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0 ) + +#define PLLSTAT_NSEL_MASK 0x00ff0000U + +#define GET_PLLSTAT_NSEL( reg ) \ + GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16 ) + +#define SET_PLLSTAT_NSEL( reg, val ) \ + SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16 ) + +#define PLLSTAT_PLLE 0x01000000U + +#define PLLSTAT_PLLC 0x02000000U + +#define PLLSTAT_PLOCK 0x04000000U + +/* CCLKCFG */ +#define CCLKCFG_CCLKSEL_MASK 0x000000ffU + +#define GET_CCLKCFG_CCLKSEL( reg ) \ + GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0 ) + +#define SET_CCLKCFG_CCLKSEL( reg, val ) \ + SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0 ) + +/* MEMMAP */ +#define MEMMAP_MAP_MASK 0x00000003U + +#define GET_MEMMAP_MAP( reg ) \ + GET_FIELD( reg, MEMMAP_MAP_MASK, 0 ) + +#define SET_MEMMAP_MAP( reg, val ) \ + SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0 ) + +/* TIR */ +#define TIR_MR0 0x00000001U +#define TIR_MR1 0x00000002U +#define TIR_MR2 0x00000004U +#define TIR_MR3 0x00000008U +#define TIR_CR0 0x00000010U +#define TIR_CR1 0x00000020U +#define TIR_CR2 0x00000040U +#define TIR_CR3 0x00000080U + +/* TCR */ +#define TCR_EN 0x00000001U +#define TCR_RST 0x00000002U + +/* TMCR */ +#define TMCR_MR0I 0x00000001U +#define TMCR_MR0R 0x00000002U +#define TMCR_MR0S 0x00000004U +#define TMCR_MR1I 0x00000008U +#define TMCR_MR1R 0x00000010U +#define TMCR_MR1S 0x00000020U +#define TMCR_MR2I 0x00000040U +#define TMCR_MR2R 0x00000080U +#define TMCR_MR2S 0x00000100U +#define TMCR_MR3I 0x00000200U +#define TMCR_MR3R 0x00000400U +#define TMCR_MR3S 0x00000800U + +/* PCLKSEL0 */ +#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U + +#define GET_PCLKSEL0_PCLK_WDT( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0 ) + +#define SET_PCLKSEL0_PCLK_WDT( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0 ) + +#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU + +#define GET_PCLKSEL0_PCLK_TIMER0( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2 ) + +#define SET_PCLKSEL0_PCLK_TIMER0( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2 ) + +#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U + +#define GET_PCLKSEL0_PCLK_TIMER1( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4 ) + +#define SET_PCLKSEL0_PCLK_TIMER1( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4 ) + +#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U + +#define GET_PCLKSEL0_PCLK_UART0( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6 ) + +#define SET_PCLKSEL0_PCLK_UART0( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6 ) + +#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U + +#define GET_PCLKSEL0_PCLK_UART1( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8 ) + +#define SET_PCLKSEL0_PCLK_UART1( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8 ) + +#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U + +#define GET_PCLKSEL0_PCLK_PWM0( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10 ) + +#define SET_PCLKSEL0_PCLK_PWM0( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10 ) + +#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U + +#define GET_PCLKSEL0_PCLK_PWM1( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12 ) + +#define SET_PCLKSEL0_PCLK_PWM1( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12 ) + +#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U + +#define GET_PCLKSEL0_PCLK_I2C0( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14 ) + +#define SET_PCLKSEL0_PCLK_I2C0( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14 ) + +#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U + +#define GET_PCLKSEL0_PCLK_SPI( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16 ) + +#define SET_PCLKSEL0_PCLK_SPI( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16 ) + +#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U + +#define GET_PCLKSEL0_PCLK_RTC( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18 ) + +#define SET_PCLKSEL0_PCLK_RTC( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18 ) + +#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U + +#define GET_PCLKSEL0_PCLK_SSP1( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20 ) + +#define SET_PCLKSEL0_PCLK_SSP1( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20 ) + +#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U + +#define GET_PCLKSEL0_PCLK_DAC( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22 ) + +#define SET_PCLKSEL0_PCLK_DAC( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22 ) + +#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U + +#define GET_PCLKSEL0_PCLK_ADC( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24 ) + +#define SET_PCLKSEL0_PCLK_ADC( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24 ) + +#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U + +#define GET_PCLKSEL0_PCLK_CAN1( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26 ) + +#define SET_PCLKSEL0_PCLK_CAN1( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26 ) + +#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U + +#define GET_PCLKSEL0_PCLK_CAN2( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28 ) + +#define SET_PCLKSEL0_PCLK_CAN2( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28 ) + +/* PCLKSEL1 */ +#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U + +#define GET_PCLKSEL1_PCLK_BAT_RAM( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0 ) + +#define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0 ) + +#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU + +#define GET_PCLKSEL1_PCLK_GPIO( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2 ) + +#define SET_PCLKSEL1_PCLK_GPIO( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2 ) + +#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U + +#define GET_PCLKSEL1_PCLK_PCB( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4 ) + +#define SET_PCLKSEL1_PCLK_PCB( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4 ) + +#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U + +#define GET_PCLKSEL1_PCLK_I2C1( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6 ) + +#define SET_PCLKSEL1_PCLK_I2C1( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6 ) + +#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U + +#define GET_PCLKSEL1_PCLK_SSP0( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10 ) + +#define SET_PCLKSEL1_PCLK_SSP0( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10 ) + +#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U + +#define GET_PCLKSEL1_PCLK_TIMER2( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12 ) + +#define SET_PCLKSEL1_PCLK_TIMER2( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12 ) + +#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U + +#define GET_PCLKSEL1_PCLK_TIMER3( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14 ) + +#define SET_PCLKSEL1_PCLK_TIMER3( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14 ) + +#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U + +#define GET_PCLKSEL1_PCLK_UART2( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16 ) + +#define SET_PCLKSEL1_PCLK_UART2( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16 ) + +#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U + +#define GET_PCLKSEL1_PCLK_UART3( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18 ) + +#define SET_PCLKSEL1_PCLK_UART3( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18 ) + +#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U + +#define GET_PCLKSEL1_PCLK_I2C2( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20 ) + +#define SET_PCLKSEL1_PCLK_I2C2( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20 ) + +#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U + +#define GET_PCLKSEL1_PCLK_I2S( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22 ) + +#define SET_PCLKSEL1_PCLK_I2S( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22 ) + +#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U + +#define GET_PCLKSEL1_PCLK_MCI( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24 ) + +#define SET_PCLKSEL1_PCLK_MCI( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24 ) + +#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U + +#define GET_PCLKSEL1_PCLK_SYSCON( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28 ) + +#define SET_PCLKSEL1_PCLK_SYSCON( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28 ) + +/* RTC_ILR */ +#define RTC_ILR_RTCCIF 0x00000001U +#define RTC_ILR_RTCALF 0x00000002U +#define RTC_ILR_RTSSF 0x00000004U + +/* RTC_CCR */ +#define RTC_CCR_CLKEN 0x00000001U +#define RTC_CCR_CTCRST 0x00000002U +#define RTC_CCR_CLKSRC 0x00000010U + +/* GPDMA */ +typedef struct { + uint32_t src; + uint32_t dest; + uint32_t lli; + uint32_t ctrl; +} lpc176x_dma_descriptor; + +typedef struct { + lpc176x_dma_descriptor desc; + uint32_t cfg; +} lpc176x_dma_channel; + +#define GPDMA_CH_NUMBER 2 +#define GPDMA_STATUS_CH_0 0x00000001U +#define GPDMA_STATUS_CH_1 0x00000002U +#define GPDMA_CH_BASE_ADDR( i ) \ + ( (volatile lpc176x_dma_channel *) \ + ( ( i ) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR ) ) + +/* GPDMA_CONFIG */ +#define GPDMA_CONFIG_EN 0x00000001U +#define GPDMA_CONFIG_MODE 0x00000002U + +/* GPDMA_ENABLED_CHNS */ +#define GPDMA_ENABLED_CHNS_CH0 0x00000001U +#define GPDMA_ENABLED_CHNS_CH1 0x00000002U + +/* GPDMA_CH_CTRL */ +#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU + +#define GET_GPDMA_CH_CTRL_TSZ( reg ) \ + GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0 ) + +#define SET_GPDMA_CH_CTRL_TSZ( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0 ) + +#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU + +#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U + +#define GET_GPDMA_CH_CTRL_SBSZ( reg ) \ + GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12 ) + +#define SET_GPDMA_CH_CTRL_SBSZ( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12 ) + +#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U + +#define GET_GPDMA_CH_CTRL_DBSZ( reg ) \ + GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15 ) + +#define SET_GPDMA_CH_CTRL_DBSZ( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15 ) + +#define GPDMA_CH_CTRL_BSZ_1 0x00000000U + +#define GPDMA_CH_CTRL_BSZ_4 0x00000001U + +#define GPDMA_CH_CTRL_BSZ_8 0x00000002U + +#define GPDMA_CH_CTRL_BSZ_16 0x00000003U + +#define GPDMA_CH_CTRL_BSZ_32 0x00000004U + +#define GPDMA_CH_CTRL_BSZ_64 0x00000005U + +#define GPDMA_CH_CTRL_BSZ_128 0x00000006U + +#define GPDMA_CH_CTRL_BSZ_256 0x00000007U + +#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U + +#define GET_GPDMA_CH_CTRL_SW( reg ) \ + GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18 ) + +#define SET_GPDMA_CH_CTRL_SW( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18 ) + +#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U + +#define GET_GPDMA_CH_CTRL_DW( reg ) \ + GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21 ) + +#define SET_GPDMA_CH_CTRL_DW( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21 ) + +#define GPDMA_CH_CTRL_W_8 0x00000000U + +#define GPDMA_CH_CTRL_W_16 0x00000001U + +#define GPDMA_CH_CTRL_W_32 0x00000002U + +#define GPDMA_CH_CTRL_SI 0x04000000U + +#define GPDMA_CH_CTRL_DI 0x08000000U + +#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U + +#define GET_GPDMA_CH_CTRL_PROT( reg ) \ + GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28 ) + +#define SET_GPDMA_CH_CTRL_PROT( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28 ) + +#define GPDMA_CH_CTRL_ITC 0x80000000U + +/* GPDMA_CH_CFG */ +#define GPDMA_CH_CFG_EN 0x00000001U + +#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU + +#define GET_GPDMA_CH_CFG_SRCPER( reg ) \ + GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1 ) + +#define SET_GPDMA_CH_CFG_SRCPER( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1 ) + +#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U + +#define GET_GPDMA_CH_CFG_DESTPER( reg ) \ + GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6 ) + +#define SET_GPDMA_CH_CFG_DESTPER( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6 ) + +#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U + +#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U + +#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U + +#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U + +#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U + +#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U + +#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U + +#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U + +#define GET_GPDMA_CH_CFG_FLOW( reg ) \ + GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11 ) + +#define SET_GPDMA_CH_CFG_FLOW( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11 ) + +#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U + +#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U + +#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U + +#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U + +#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U + +#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U + +#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U + +#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U + +#define GPDMA_CH_CFG_IE 0x00004000U + +#define GPDMA_CH_CFG_ITC 0x00008000U + +#define GPDMA_CH_CFG_LOCK 0x00010000U + +#define GPDMA_CH_CFG_ACTIVE 0x00020000U + +#define GPDMA_CH_CFG_HALT 0x00040000U + +/* AHBCFG */ +#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U + +#define AHBCFG_BREAK_BURST_MASK 0x00000006U + +#define GET_AHBCFG_BREAK_BURST( reg ) \ + GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1 ) + +#define SET_AHBCFG_BREAK_BURST( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1 ) + +#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U + +#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U + +#define GET_AHBCFG_QUANTUM_SIZE( reg ) \ + GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4 ) + +#define SET_AHBCFG_QUANTUM_SIZE( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4 ) + +#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U + +#define GET_AHBCFG_DEFAULT_MASTER( reg ) \ + GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8 ) + +#define SET_AHBCFG_DEFAULT_MASTER( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8 ) + +#define AHBCFG_EP1_MASK 0x00007000U + +#define GET_AHBCFG_EP1( reg ) \ + GET_FIELD( reg, AHBCFG_EP1_MASK, 12 ) + +#define SET_AHBCFG_EP1( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12 ) + +#define AHBCFG_EP2_MASK 0x00070000U + +#define GET_AHBCFG_EP2( reg ) \ + GET_FIELD( reg, AHBCFG_EP2_MASK, 16 ) + +#define SET_AHBCFG_EP2( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16 ) + +#define AHBCFG_EP3_MASK 0x00700000U + +#define GET_AHBCFG_EP3( reg ) \ + GET_FIELD( reg, AHBCFG_EP3_MASK, 20 ) + +#define SET_AHBCFG_EP3( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20 ) + +#define AHBCFG_EP4_MASK 0x07000000U + +#define GET_AHBCFG_EP4( reg ) \ + GET_FIELD( reg, AHBCFG_EP4_MASK, 24 ) + +#define SET_AHBCFG_EP4( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24 ) + +#define AHBCFG_EP5_MASK 0x70000000U + +#define GET_AHBCFG_EP5( reg ) \ + GET_FIELD( reg, AHBCFG_EP5_MASK, 28 ) + +#define SET_AHBCFG_EP5( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28 ) + +/* I2S */ +static volatile lpc_i2s * const lpc176x_i2s = (lpc_i2s *) I2S_BASE_ADDR; + +/* ADC */ +#define ADC_CR_SEL( val ) BSP_FLD32( val, 0, 7 ) +#define ADC_CR_SEL_GET( val ) BSP_FLD32GET( val, 0, 7 ) +#define ADC_CR_SEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 7 ) +#define ADC_CR_CLKDIV( val ) BSP_FLD32( val, 8, 15 ) +#define ADC_CR_CLKDIV_GET( reg ) BSP_FLD32GET( reg, 8, 15 ) +#define ADC_CR_CLKDIV_SET( reg, val ) BSP_FLD32SET( reg, val, 8, 15 ) +#define ADC_CR_BURST BSP_BIT32( 16 ) +#define ADC_CR_CLKS( val ) BSP_FLD32( val, 17, 19 ) +#define ADC_CR_PDN BSP_BIT32( 21 ) +#define ADC_CR_START( val ) BSP_FLD32( val, 24, 26 ) +#define ADC_CR_EDGE BSP_BIT32( 27 ) + +#define ADC_DR_VALUE( reg ) BSP_FLD32GET( reg, 6, 15 ) +#define ADC_DR_OVERRUN BSP_BIT32( 30 ) +#define ADC_DR_DONE BSP_BIT32( 31 ) + +/* DAC */ +#define DAC_STEPS 1024 +#define DAC_VALUE( val ) BSP_FLD32( val, 6, 15 ) +#define DAC_BIAS BSP_BIT32( 16 ) + +#endif /* LIBBSP_ARM_LPC176X_H */ diff --git a/bsps/arm/lpc176x/include/bsp/mbed-pinmap.h b/bsps/arm/lpc176x/include/bsp/mbed-pinmap.h new file mode 100755 index 0000000000..3556bc5fbf --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/mbed-pinmap.h @@ -0,0 +1,50 @@ +/** + * @file mbed-pinmap.h + * + * @ingroup lpc176x + * + * @brief Pins of the mbed lpc1768 + * See http://mbed.org/media/uploads/chris/mbed-005.1.pdf for references + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#define DIP5 9U +#define DIP6 8U +#define DIP7 7U +#define DIP8 6U +#define DIP9 0U +#define DIP10 1U +#define DIP11 18U +#define DIP12 17U +#define DIP13 15U +#define DIP14 16U +#define DIP15 23U +#define DIP16 24U +#define DIP17 25U +#define DIP18 26U +#define DIP19 62U +#define DIP20 63U +#define DIP21 69U +#define DIP22 68U +#define DIP23 67U +#define DIP24 66U +#define DIP25 65U +#define DIP26 64U +#define DIP27 11U +#define DIP28 10U +#define DIP29 5U +#define DIP30 4U +#define LED1 50U +#define LED2 52U +#define LED3 53U +#define LED4 55U diff --git a/bsps/arm/lpc176x/include/bsp/pwmout-defs.h b/bsps/arm/lpc176x/include/bsp/pwmout-defs.h new file mode 100755 index 0000000000..f55b154a05 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/pwmout-defs.h @@ -0,0 +1,105 @@ +/** + * @file pwmout-defs.h + * + * @ingroup lpc176x + * + * @brief PWM-Out controller for the mbed lpc1768 board. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LPC176X_PWMOUT_DEFS_H +#define LPC176X_PWMOUT_DEFS_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define PWM_DEFAULT_PERIOD 20000u +#define PWM_DEFAULT_PULSEWIDTH 0u + +#define PWM_PRESCALER_USECOND ( LPC176X_CCLK / 1000000 ) +#define PWM_MCR_RESET_ON_MATCH0 ( 1 << 1 ) +#define PWM_PCR_ENABLE_PWM( pwmout ) ( 1 << ( 9 + pwmout ) ) +#define PWM_TCR_RESET ( 1 << 1 ) +#define PWM_TCR_ENABLE ( 1u ) +#define PWM_TCR_PWM ( 1 << 3 ) +#define PWM_LER_LATCH_MATCH_0 1u +#define PWM_LER_LATCH( match ) ( 1 << ( ( match ) + 1 ) ) + +/** + * @brief The low-level PWM output device. + */ +typedef struct { + volatile uint32_t IR; + volatile uint32_t TCR; + volatile uint32_t TC; + volatile uint32_t PR; + volatile uint32_t PC; + volatile uint32_t MCR; + volatile uint32_t MR0; + volatile uint32_t MR1; + volatile uint32_t MR2; + volatile uint32_t MR3; + volatile uint32_t CCR; + volatile uint32_t CR0; + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t CR3; + volatile uint32_t RESERVED0; + volatile uint32_t MR4; + volatile uint32_t MR5; + volatile uint32_t MR6; + volatile uint32_t PCR; + volatile uint32_t LER; + volatile uint32_t RESERVED1[ 7 ]; + volatile uint32_t CTCR; +} lpc176x_pwm_device; + +/** + * @brief Represents one pin and the respective function to be set + * for each PWM output. + */ +typedef struct { + uint32_t pin_number; + lpc176x_pin_function pin_function; +} lpc176x_pwm_pin; + +/** + * @brief The PWM outputs of the board. + */ +typedef enum { + PWMO_1, + PWMO_2, + PWMO_3, + PWMO_4, + PWMO_5, + PWMO_6, + PWM_OUTPUT_NUMBER +} lpc176x_pwm_number; + +/** + * @brief A pin for each PWM output. + */ +typedef enum { + PWM_FIRST_PIN, + PWM_SECOND_PIN, + PWM_NUMBER_OF_PINS +} lpc176x_pwm_pin_number; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/bsps/arm/lpc176x/include/bsp/pwmout.h b/bsps/arm/lpc176x/include/bsp/pwmout.h new file mode 100755 index 0000000000..1427fc5f3e --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/pwmout.h @@ -0,0 +1,73 @@ +/** + * @file pwmout.h + * + * @ingroup lpc176x + * + * @brief PWM-Out controller for the mbed lpc1768 board. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LPC176X_PWMOUT_H +#define LPC176X_PWMOUT_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Initializes the PWM output device and sets an initial period + * of 20000us. + * + * @param pin_number The PWM output pin. + * @return RTEMS_SUCCESSFULL if the PWM initialization was OK, + * RTEMS_INVALID_NUMBER for a wrong parameter. + */ +rtems_status_code pwm_init( const lpc176x_pin_number pin_number ); + +/** + * @brief Sets a period for the PWM output. (Note that this changes the period + * for all the PWM outputs.) + * + * @param pin_number The pin whose period we want to change. + * @param period The desired period in microseconds. + * + * @return RTEMS_SUCCESSFULL if the period's setting was OK, + * RTEMS_INVALID_NUMBER for a bad parameter. + */ +rtems_status_code pwm_period( + const lpc176x_pin_number pin_number, + const lpc176x_microseconds period +); + +/** + * @brief Sets a pulsewidth for the PWM output. + * + * @param pin_number The pin whose pulsewidth we want to change. + * @param pwidth The desired pulsewidth in microseconds. + * + * @return RTEMS_SUCCESSFULL if the pulsewidth's setting was OK, + * RTEMS_INVALID_NUMBER for a wrong parameter. + */ +rtems_status_code pwm_pulsewidth( + const lpc176x_pin_number pin_number, + const lpc176x_microseconds pwidth +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/bsps/arm/lpc176x/include/bsp/system-clocks.h b/bsps/arm/lpc176x/include/bsp/system-clocks.h new file mode 100644 index 0000000000..26087ff3e9 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/system-clocks.h @@ -0,0 +1,91 @@ +/** + * @file + * + * @ingroup lpc176x_clocks + * + * @brief System clocks. + */ + +/* + * Copyright (c) 2008, 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_SYSTEM_CLOCKS_H +#define LIBBSP_ARM_LPC176X_SYSTEM_CLOCKS_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc176x_clock System Clocks + * + * @ingroup lpc176x + * + * @brief System clocks. + * + * @{ + */ + +/** + * @brief Initializes the standard timer. + * + * This function uses Timer 1. + */ +void lpc176x_timer_initialize( void ); + +/** + * @brief Returns current standard timer value in CPU clocks. + * + * @return This function uses Timer 1. + */ +static inline unsigned lpc176x_get_timer1( void ) +{ + return LPC176X_T1TC; +} + +/** + * @brief Delay for @a us micro seconds. + * + * This function uses the standard timer and assumes that the CPU + * frequency is in whole MHz numbers. The delay value @a us will be + * converted to CPU ticks and there is no protection against integer + * overflows. + * + * This function uses Timer 1. + */ +void lpc176x_micro_seconds_delay( unsigned us ); + +/** + * @brief Returns the PLL output clock frequency in [Hz]. + * + * @return Returns zero in case of an unexpected PLL input frequency. + */ +unsigned lpc176x_pllclk( void ); + +/** + * @brief Returns the CPU clock frequency in [Hz]. + * + * @return Returns zero in case of an unexpected PLL input frequency. + */ +unsigned lpc176x_cclk( void ); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_SYSTEM_CLOCKS_H */ diff --git a/bsps/arm/lpc176x/include/bsp/timer-defs.h b/bsps/arm/lpc176x/include/bsp/timer-defs.h new file mode 100644 index 0000000000..3827aa9279 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/timer-defs.h @@ -0,0 +1,449 @@ +/** + * @file timer-defs.h + * + * @ingroup lpc176x + * + * @brief API definitions of the for the timer of the lpc176x bsp. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_TIMER_DEFS_H +#define LIBBSP_ARM_LPC176X_TIMER_DEFS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Timer 0 */ +#define LPC176X_TMR0_BASE_ADDR 0x40004000U + +#define LPC176X_T0IR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x00U ) ) +#define LPC176X_T0TCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x04U ) ) +#define LPC176X_T0TC ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x08U ) ) +#define LPC176X_T0PR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x0CU ) ) +#define LPC176X_T0PC ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x10U ) ) +#define LPC176X_T0MCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x14U ) ) +#define LPC176X_T0MR0 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x18U ) ) +#define LPC176X_T0MR1 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x1CU ) ) +#define LPC176X_T0MR2 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x20U ) ) +#define LPC176X_T0MR3 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x24U ) ) +#define LPC176X_T0CCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x28U ) ) +#define LPC176X_T0CR0 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x2CU ) ) +#define LPC176X_T0CR1 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x30U ) ) +#define LPC176X_T0CR2 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x34U ) ) +#define LPC176X_T0CR3 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x38U ) ) +#define LPC176X_T0EMR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x3CU ) ) +#define LPC176X_T0CTCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x70U ) ) + +/* Timer 1 */ +#define LPC176X_TMR1_BASE_ADDR 0x40008000U + +#define LPC176X_T1IR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x00U ) ) +#define LPC176X_T1TCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x04U ) ) +#define LPC176X_T1TC ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x08U ) ) +#define LPC176X_T1PR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x0CU ) ) +#define LPC176X_T1PC ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x10U ) ) +#define LPC176X_T1MCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x14U ) ) +#define LPC176X_T1MR0 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x18U ) ) +#define LPC176X_T1MR1 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x1CU ) ) +#define LPC176X_T1MR2 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x20U ) ) +#define LPC176X_T1MR3 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x24U ) ) +#define LPC176X_T1CCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x28U ) ) +#define LPC176X_T1CR0 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x2CU ) ) +#define LPC176X_T1CR1 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x30U ) ) +#define LPC176X_T1CR2 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x34U ) ) +#define LPC176X_T1CR3 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x38U ) ) +#define LPC176X_T1EMR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x3CU ) ) +#define LPC176X_T1CTCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x70U ) ) + +/* Timer 2 */ +#define LPC176X_TMR2_BASE_ADDR 0x40090000U + +#define LPC176X_T2IR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x00U ) ) +#define LPC176X_T2TCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x04U ) ) +#define LPC176X_T2TC ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x08U ) ) +#define LPC176X_T2PR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x0CU ) ) +#define LPC176X_T2PC ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x10U ) ) +#define LPC176X_T2MCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x14U ) ) +#define LPC176X_T2MR0 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x18U ) ) +#define LPC176X_T2MR1 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x1CU ) ) +#define LPC176X_T2MR2 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x20U ) ) +#define LPC176X_T2MR3 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x24U ) ) +#define LPC176X_T2CCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x28U ) ) +#define LPC176X_T2CR0 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x2CU ) ) +#define LPC176X_T2CR1 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x30U ) ) +#define LPC176X_T2CR2 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x34U ) ) +#define LPC176X_T2CR3 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x38U ) ) +#define LPC176X_T2EMR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x3CU ) ) +#define LPC176X_T2CTCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x70U ) ) + +/* Timer 3 */ +#define LPC176X_TMR3_BASE_ADDR 0x40094000U + +#define LPC176X_T3IR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x00U ) ) +#define LPC176X_T3TCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x04U ) ) +#define LPC176X_T3TC ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x08U ) ) +#define LPC176X_T3PR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x0CU ) ) +#define LPC176X_T3PC ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x10U ) ) +#define LPC176X_T3MCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x14U ) ) +#define LPC176X_T3MR0 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x18U ) ) +#define LPC176X_T3MR1 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x1CU ) ) +#define LPC176X_T3MR2 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x20U ) ) +#define LPC176X_T3MR3 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x24U ) ) +#define LPC176X_T3CCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x28U ) ) +#define LPC176X_T3CR0 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x2CU ) ) +#define LPC176X_T3CR1 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x30U ) ) +#define LPC176X_T3CR2 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x34U ) ) +#define LPC176X_T3CR3 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x38U ) ) +#define LPC176X_T3EMR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x3CU ) ) +#define LPC176X_T3CTCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x70U ) ) + +/** + * @brief Represents the timer device registers. + */ +typedef struct { + /** + * @brief Interrupt Register. + */ + volatile uint32_t IR; + /** + * @brief Timer Control Register. + */ + volatile uint32_t TCR; + /** + * @brief Timer Counter. + */ + volatile uint32_t TC; + /** + * @brief Prescale Register. + */ + volatile uint32_t PR; + /** + * @brief Prescale Counter. + */ + volatile uint32_t PC; + /** + * @brief Match Control Register. + */ + volatile uint32_t MCR; + /** + * @brief Match Register (0, 1, 2, 3) + */ + volatile uint32_t MR[ 4 ]; + /** + * @brief Capture Control Register. + */ + volatile uint32_t CCR; + /** + * @brief Capture Register (0, 1) + */ + volatile uint32_t CR[ 2 ]; + volatile uint32_t reserved0; + volatile uint32_t reserved1; + /** + * @brief External Match Register. + */ + volatile uint32_t EMR; + volatile uint32_t reserved2[ 12 ]; + /** + * @brief Count Control Register. + */ + volatile uint32_t CTCR; +} lpc176x_timer_device; + +#define LPC176X_PIN_SELECT_TIMER 3U +#define LPC176X_PINSEL_NO_PORT 999U + +#define LPC176X_TIMER_RESET ( 1U << 1U ) +#define LPC176X_TIMER_START 1U +#define LPC176X_TIMER_MODE_COUNTER_SOURCE_CAP0 0U +#define LPC176X_TIMER_MODE_COUNTER_SOURCE_CAP1 ( 1U << 2U ) +#define LPC176X_TIMER0_CAPTURE_PORTS { 58U, 59U } +#define LPC176X_TIMER1_CAPTURE_PORTS { 50U, 51U } +#define LPC176X_TIMER2_CAPTURE_PORTS { 4U, 5U } +#define LPC176X_TIMER3_CAPTURE_PORTS { 23U, 24U } +#define LPC176X_TIMER0_EMATCH_PORTS { 60U, \ + 61U, \ + LPC176X_PINSEL_NO_PORT, \ + LPC176X_PINSEL_NO_PORT } +#define LPC176X_TIMER1_EMATCH_PORTS { 54U, \ + 57U, \ + LPC176X_PINSEL_NO_PORT, \ + LPC176X_PINSEL_NO_PORT } +#define LPC176X_TIMER2_EMATCH_PORTS { 6U, 7U, 8U, 9U } +#define LPC176X_TIMER3_EMATCH_PORTS { 10U, \ + 11U, \ + LPC176X_PINSEL_NO_PORT, \ + LPC176X_PINSEL_NO_PORT } +#define LPC176X_TIMER_DEFAULT_RESOLUTION 1U +#define LPC176X_TIMER_MCR_MASK 7U +#define LPC176X_TIMER_MCR_MASK_SIZE 3U +#define LPC176X_TIMER_CCR_MASK 7U +#define LPC176X_TIMER_CCR_MASK_SIZE 3U +#define LPC176X_TIMER_EMR_MASK 3U +#define LPC176X_TIMER_EMR_MASK_SIZE 2U +#define LPC176X_TIMER_EMR_MASK_OFFSET 4U +#define LPC176X_TIMER_CLEAR_FUNCTION 0U +#define LPC176X_TIMER_PRESCALER_DIVISOR 1000000U +#define LPC176X_TIMER_VECTOR_NUMBER( timernumber ) ( timernumber + 1U ) +#define LPC176X_TIMER_INTERRUPT_SOURCE_BIT( i ) ( 1U << i ) +#define LPC176X_TIMER_MATCH_FUNCTION_COUNT 8U +#define LPC176X_TIMER_CAPTURE_FUNCTION_COUNT 8U + +#define LPC176X_ISR_NAME_STRING_SIZE 10U + +#define LPC176X_SET_MCR( mcr, match_port, function ) \ + SET_FIELD( mcr, \ + function, \ + ( 0x7U << ( 3U * match_port ) ), \ + ( 3U * match_port ) ) +#define LPC176X_SET_CCR( mcr, capture_port, function ) \ + SET_FIELD( mcr, function, ( 0x7U << ( 3U * capture_port ) ), \ + ( 3U * capture_port ) ) +#define LPC176X_SET_EMR( mcr, match_port, function ) \ + SET_FIELD( mcr, function, ( 0x3U << ( 2U * match_port + 4U ) ), \ + ( 2U * match_port + 4U ) ) + +/** + * @brief Capture ports of a timer. + * + * Enumerated type to define the set of capture ports for a timer device. + */ +typedef enum { + LPC176X_CAPn_0, + LPC176X_CAPn_1, + LPC176X_CAPTURE_PORTS_COUNT +} lpc176x_capture_port; + +/** + * @brief Match ports of a timer. + * + * Enumerated type to define the set of match ports for a timer device. + */ +typedef enum { + LPC176X_MATn_0, + LPC176X_MATn_1, + LPC176X_MATn_2, + LPC176X_MATn_3, + LPC176X_EMATCH_PORTS_COUNT +} lpc176x_match_port; + +/** + * @brief Timer modes of a timer. + * + * Enumerated type to define the set of modes for a timer device. + */ +typedef enum { + LPC176X_TIMER_MODE_TIMER, + LPC176X_TIMER_MODE_COUNTER_RISING_CAP0, + LPC176X_TIMER_MODE_COUNTER_FALLING_CAP0, + LPC176X_TIMER_MODE_COUNTER_BOTH_CAP0, + LPC176X_TIMER_MODE_COUNTER_RISING_CAP1 = ( 1U & ( 1U << 2U ) ), + LPC176X_TIMER_MODE_COUNTER_FALLING_CAP1 = ( 2U & ( 1U << 2U ) ), + LPC176X_TIMER_MODE_COUNTER_BOTH_CAP1 = ( 3U & ( 1U << 2U ) ), +} lpc176x_timer_mode; + +/** + * @brief The timer devices in the board. + * + * Enumerated type to define the timer device's numbers. + */ +typedef enum { + LPC176X_TIMER_0, + LPC176X_TIMER_1, + LPC176X_TIMER_2, + LPC176X_TIMER_3, + LPC176X_TIMER_COUNT +} lpc176x_timer_number; + +/** + * @brief The index for the isr_funct_vector representing the functions + * that attends each possible interrupt source for a timer. + * + * Enumerated type to define the set of isr timer functions . + */ +typedef enum { + LPC176X_MAT0_ISR_FUNCTION, + LPC176X_MAT1_ISR_FUNCTION, + LPC176X_MAT2_ISR_FUNCTION, + LPC176X_MAT3_ISR_FUNCTION, + LPC176X_CAP0_ISR_FUNCTION, + LPC176X_CAP1_ISR_FUNCTION, + LPC176X_ISR_FUNCTIONS_COUNT +} lpc176x_isr_function; + +/** + * @brief The possible functions at match. This options could be + * used together. + * + * Enumerated type to define the set of functions at mach for a + * timer device. + */ +typedef enum { + LPC176X_TIMER_MATCH_FUNCTION_NONE = 0U, + LPC176X_TIMER_MATCH_FUNCTION_INTERRUPT = 1U, + LPC176X_TIMER_MATCH_FUNCTION_RESET = ( 1U << 1U ), + LPC176X_TIMER_MATCH_FUNCTION_STOP = ( 1U << 2U ) +} lpc176x_match_function; + +/** + * @brief The possible functions at capture. This options could + * be used together. + * + * Enumerated type to define the set of functions at capture for + * a timer device. + */ +typedef enum { + LPC176X_TIMER_CAPTURE_FUNCTION_NONE = 0U, + LPC176X_TIMER_CAPTURE_FUNCTION_RISING = 1U, + LPC176X_TIMER_CAPTURE_FUNCTION_FALLING = ( 1U << 1U ), + LPC176X_TIMER_CAPTURE_FUNCTION_INTERRUPT = ( 1U << 2U ) +} lpc176x_capture_function; + +/** + * @brief The possible functions at match, for the external ports. + * + * Enumerated type to define the set of functions at match, for external + * ports, for a timer device. + */ +typedef enum { + LPC176X_TIMER_EXTMATCH_FUNCTION_NONE, + LPC176X_TIMER_EXTMATCH_FUNCTION_CLEAR, + LPC176X_TIMER_EXTMATCH_FUNCTION_SET, + LPC176X_TIMER_EXTMATCH_FUNCTION_TOGGLE +} lpc176x_ext_match_function; + +/** + * @brief A function that attends an interruption for a timer. + * + * @param tnumber Timer number. + * @return Pointer to the match function. + */ +typedef void (*lpc176x_isr_funct) ( const lpc176x_timer_number tnumber ); + +/** + * @brief The vector of functions that attends each possible interrupt + * source for a timer. + */ +typedef lpc176x_isr_funct const lpc176x_isr_funct_vector[ + LPC176X_ISR_FUNCTIONS_COUNT ]; + +/** + * @brief The Timer device representation. + */ +typedef struct { + /** + * @brief The address of the controlling registers for the timer. + */ + lpc176x_timer_device *const device; + /** + * @brief The module for the RTEMS module starting (power and clock). + */ + const lpc176x_module module; + /** + * @brief The Pins for the Capture ports of this timer. + */ + const lpc176x_pin_number pinselcap[ LPC176X_CAPTURE_PORTS_COUNT ]; + /** + * @brief The Pins for the external match ports of this timer. + */ + const lpc176x_pin_number pinselemat[ LPC176X_EMATCH_PORTS_COUNT ]; +} lpc176x_timer; + +/** + * @brief The Timer functions. + */ +typedef struct { + /** + * @brief The vector of isr functions for this timer. + */ + const lpc176x_isr_funct_vector *funct_vector; +} lpc176x_timer_functions; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_TIMER_DEFS_H */ \ No newline at end of file diff --git a/bsps/arm/lpc176x/include/bsp/timer.h b/bsps/arm/lpc176x/include/bsp/timer.h new file mode 100644 index 0000000000..6805b55f0e --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/timer.h @@ -0,0 +1,195 @@ +/** + * @file timer.h + * + * @ingroup lpc176x + * + * @brief Timer API for the lpc176x bsp. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_TIMER_H +#define LIBBSP_ARM_LPC176X_TIMER_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief resets timer counter and stops it. + * + * @param tnumber the device to be reseted + * @return RTEMS_SUCCESSFUL if the timer was reseted successfuly. + */ +rtems_status_code lpc176x_timer_reset( lpc176x_timer_number tnumber ); + +/** + * @brief Sets mode of the timer (timer, counter rising, counter falling + * or counter both edges) + * + * @param tnumber: the device to be setted + * @param mode: the desired mode + * @return RTEMS_SUCCESSFUL if the timer's mode was setted successfuly. + */ +rtems_status_code lpc176x_timer_set_mode( + lpc176x_timer_number tnumber, + lpc176x_timer_mode mode +); + +/** + * @brief Starts the timer counter + * + * @param tnumber: the device to be started + * @return RTEMS_SUCCESSFUL if the timer's was started successfuly. + */ +rtems_status_code lpc176x_timer_start( lpc176x_timer_number tnumber ); + +/** + * @brief true if timer is started. + * + * @param tnumber: the timer number to check. + * @param is_started: TRUE if the timer is running. + * @return RTEMS_SUCCESSFUL if the started timer check was successfuly. + */ +rtems_status_code lpc176x_timer_is_started( + lpc176x_timer_number tnumber, + bool *is_started +); + +/** + * @brief sets the resolution in microseconds of the timer + * + * @param tnumber: the device to be modified. + * @param resolution: how many microseconds will mean each timer + * counter unit. + * @return RTEMS_SUCCESSFUL if the timer resolution was setted successfuly. + */ +rtems_status_code lpc176x_timer_set_resolution( + lpc176x_timer_number tnumber, + lpc176x_microseconds resolution +); + +/** + * @brief Configures the timer match + * + * @param tnumber: the device to be modified + * @param match_port: which port of this timer will be setted + * @param function: what the timer should do when match: stop timer, clear, + * and/or interrupt + * @param match_value: the value that the timer should match. + * @return RTEMS_SUCCESSFUL if the timer was configured successfuly. + */ +rtems_status_code lpc176x_timer_match_config( + lpc176x_timer_number tnumber, + lpc176x_match_port match_port, + lpc176x_match_function function, + uint32_t match_value +); + +/** + * @brief Configures the capture ports + * + * @param tnumber: the device to be modified + * @param capture_port: which port of this timer will be setted + * @param function: At which edge/s will the capture work, and + * if it will interrupt + */ +rtems_status_code lpc176x_timer_capture_config( + lpc176x_timer_number tnumber, + lpc176x_capture_port capture_port, + lpc176x_capture_function function +); + +/** + * @brief Configures the external match ports + * + * @param tnumber: the device to be modified + * @param match_port: which match for this timer + * @param function: what should do when match: set, clear toggle or nothing + */ +rtems_status_code lpc176x_timer_external_match_config( + lpc176x_timer_number tnumber, + lpc176x_match_port match_port, + lpc176x_ext_match_function function +); + +/** + * @brief Gets the captured value + * + * @param tnumber: the device to be modified + * @param capnumber: which capture port for this timer + * @return the captured value + */ +uint32_t lpc176x_timer_get_capvalue( + lpc176x_timer_number tnumber, + lpc176x_capture_port capnumber +); + +/** + * @brief Gets the timer value + * + * @param tnumber: the device + * @return the timer value + */ +uint32_t lpc176x_timer_get_timer_value( lpc176x_timer_number tnumber ); + +/** + * @brief Sets the timer value + * + * @param tnumber: the timer to modify. + * @param timer_value the value to set. + */ +rtems_status_code lpc176x_timer_set_timer_value( + lpc176x_timer_number tnumber, + uint32_t lpc176x_timer_value +); + +/** + * @brief Timer generic isroutine. + * + * @param timernumber the number of timer. + */ +void lpc176x_timer_isr( void *lpc176x_timer_number ); + +/** + * @brief Initializes timer in timer mode and resets counter but + * without starting it, and without any capture or + * match function. + * + * @param tnumber which timer + * @return RTEMS_SUCCESSFUL when everything ok. + */ +rtems_status_code lpc176x_timer_init( lpc176x_timer_number tnumber ); + +/** + * @brief Initializes timer in timer mode and resets counter but + * without starting it, and without any capture or + * match function. + * + * @param tnumber which timer to init + * @param vector the functions to be used by the isr. + * @return RTEMS_SUCCESSFUL when everything ok. + */ +rtems_status_code lpc176x_timer_init_with_interrupt( + lpc176x_timer_number tnumber, + const lpc176x_isr_funct_vector *vector +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_TIMER_H */ \ No newline at end of file diff --git a/bsps/arm/lpc176x/include/bsp/watchdog-defs.h b/bsps/arm/lpc176x/include/bsp/watchdog-defs.h new file mode 100644 index 0000000000..44ea80527e --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/watchdog-defs.h @@ -0,0 +1,65 @@ +/** + * @file watchdog-defs.h + * + * @ingroup lpc176x + * + * @brief API definitions of the Watchdog driver for the lpc176x bsp in RTEMS. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_WATCHDOG_DEFS_H +#define LIBBSP_ARM_LPC176X_WATCHDOG_DEFS_H + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define LPC176X_WDMOD_BASE 0x40000000U +#define LPC176X_WDFEED_CON 0XAAU +#define LPC176X_WDFEED_CFG 0X55U +#define LPC176X_WD_PRESCALER_DIVISOR 4000000U +#define LPC176X_WWDT_MOD_WDEN BSP_BIT32( 0 ) +#define LPC176X_WWDT_MOD_WDRESET BSP_BIT32( 1 ) +#define LPC176X_WWDT_MOD_WDTOF BSP_BIT32( 2 ) +#define LPC176X_WWDT_MOD_WDINT BSP_BIT32( 3 ) +#define LPC176X_WWDT_CLKSEL_WDSEL_IRC 0x0U +#define LPC176X_WWDT_CLKSEL_WDSEL_PCLK 0x1U +#define LPC176X_WWDT_CLKSEL_WDSEL_RTC 0x2U +#define LPC176X_WD_INTERRUPT_VECTOR_NUMBER 0U +#define LPC176X_WDMOD ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + 0x00U ) ) +#define LPC176X_WDTC ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + 0x04U ) ) +#define LPC176X_WDFEED ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + \ + 0x08U ) ) +#define LPC176X_WDTV ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + 0x0CU ) ) +#define LPC176X_WDCLKSEL ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + \ + 0x10U ) ) + +/** + * @brief A function that attends an interruption for a watchdog. + */ +typedef rtems_interrupt_handler lpc176x_wd_isr_funct; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_WATCHDOG_DEFS_H */ diff --git a/bsps/arm/lpc176x/include/bsp/watchdog.h b/bsps/arm/lpc176x/include/bsp/watchdog.h new file mode 100644 index 0000000000..8b5f033605 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/watchdog.h @@ -0,0 +1,70 @@ +/** + * @file watchdog.h + * + * @ingroup lpc176x + * + * @brief API of the Watchdog driver for the lpc176x bsp in RTEMS. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_WATCHDOG_H +#define LIBBSP_ARM_LPC176X_WATCHDOG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Checks if the watchdog was executed by software or not. Set when + * the watchdog timer times out, cleared by software. + * + * @return TRUE if the watchdog was executed. + * FALSE otherwise. + */ +bool lpc176x_been_reset_by_watchdog( void ); + +/** + * @brief Resets the watchdog timer. + */ +void lpc176x_watchdog_reset( void ); + +/** + * @brief Configures the watchdog's timer. + * + * @param tcount Timer's out value. + * @return RTEMS_SUCCESSFUL if the watchdog was configured successfully. + */ +rtems_status_code lpc176x_watchdog_config( lpc176x_microseconds tcount ); + +/** + * @brief Configures the timer watchdog using interrupt. + * + * @param tcount Timer's out value. + * @param interrupt Interrupt to register. + * @return RTEMS_SUCCESSFUL if the watchdog was configured successfully + * with interrupts. + */ +rtems_status_code lpc176x_watchdog_config_with_interrupt( + lpc176x_wd_isr_funct interrupt, + lpc176x_microseconds tcount +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_WATCHDOG_H */ diff --git a/bsps/arm/lpc176x/include/tm27.h b/bsps/arm/lpc176x/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/lpc176x/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/lpc24xx/headers.am b/bsps/arm/lpc24xx/headers.am new file mode 100644 index 0000000000..e2f4d26042 --- /dev/null +++ b/bsps/arm/lpc24xx/headers.am @@ -0,0 +1,21 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/dma.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/io.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/lcd.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/lpc-clock-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/lpc-ethernet-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/lpc17xx.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/lpc24xx.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/ssp.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/start-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/system-clocks.h diff --git a/bsps/arm/lpc24xx/include/bsp.h b/bsps/arm/lpc24xx/include/bsp.h new file mode 100644 index 0000000000..5424808841 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp.h @@ -0,0 +1,128 @@ +/** + * @file + * + * @ingroup lpc24xx + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_BSP_H +#define LIBBSP_ARM_LPC24XX_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#define LPC24XX_PCLK (LPC24XX_CCLK / LPC24XX_PCLKDIV) + +#define LPC24XX_EMCCLK (LPC24XX_CCLK / LPC24XX_EMCCLKDIV) + +#define LPC24XX_MPU_REGION_COUNT 8 + +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (29 << 3) + +#define BSP_ARMV7M_SYSTICK_PRIORITY (30 << 3) + +#define BSP_ARMV7M_SYSTICK_FREQUENCY LPC24XX_CCLK + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct rtems_bsdnet_ifconfig; + +struct rtems_termios_device_context; + +/** + * @defgroup lpc24xx LPC24XX Support + * + * @ingroup bsp_arm + * + * @brief LPC24XX support package. + * + * @{ + */ + +/** + * @brief Network driver attach and detach function. + */ +int lpc_eth_attach_detach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +/** + * @brief Standard network driver attach and detach function. + */ +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach + +/** + * @brief Standard network driver name. + */ +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" + +/** + * @brief Optimized idle task. + * + * This idle task sets the power mode to idle. This causes the processor clock + * to be stopped, while on-chip peripherals remain active. Any enabled + * interrupt from a peripheral or an external interrupt source will cause the + * processor to resume execution. + * + * To enable the idle task use the following in the system configuration: + * + * @code + * #include + * + * #define CONFIGURE_INIT + * + * #define CONFIGURE_IDLE_TASK_BODY bsp_idle_thread + * + * #include + * @endcode + */ +void *bsp_idle_thread(uintptr_t ignored); + +#ifdef ARM_MULTILIB_ARCH_V4 + #define BSP_CONSOLE_UART_BASE 0xe000c000 +#else + #define BSP_CONSOLE_UART_BASE 0x4000c000 +#endif + +void bsp_restart(void *addr); + +bool lpc24xx_uart_probe_1(struct rtems_termios_device_context *context); + +bool lpc24xx_uart_probe_2(struct rtems_termios_device_context *context); + +bool lpc24xx_uart_probe_3(struct rtems_termios_device_context *context); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_LPC24XX_BSP_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/dma.h b/bsps/arm/lpc24xx/include/bsp/dma.h new file mode 100644 index 0000000000..b2e6c3e665 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/dma.h @@ -0,0 +1,95 @@ +/** + * @file + * + * @ingroup lpc24xx_dma + * + * @brief Direct memory access (DMA) support. + */ + +/* + * Copyright (c) 2008, 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_DMA_H +#define LIBBSP_ARM_LPC24XX_DMA_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc24xx_dma DMA Support + * + * @ingroup lpc24xx + * + * @brief Direct memory access (DMA) support. + * + * @{ + */ + +/** + * @brief Initializes the general purpose DMA. + */ +void lpc24xx_dma_initialize(void); + +/** + * @brief Tries to obtain the DMA channel @a channel. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid channel number. + * @retval RTEMS_RESOURCE_IN_USE Channel already occupied. + */ +rtems_status_code lpc24xx_dma_channel_obtain(unsigned channel); + +/** + * @brief Releases the DMA channel @a channel. + * + * You must have obtained this channel with lpc24xx_dma_channel_obtain() + * previously. + * + * If the channel number @a channel is out of range nothing will happen. + */ +void lpc24xx_dma_channel_release(unsigned channel); + +/** + * @brief Disables the DMA channel @a channel. + * + * If @a force is @c false the channel will be halted and disabled when the + * channel is inactive otherwise it will be disabled immediately. + * + * If the channel number @a channel is out of range nothing will happen. + */ +void lpc24xx_dma_channel_disable(unsigned channel, bool force); + +rtems_status_code lpc24xx_dma_copy_initialize(void); + +rtems_status_code lpc24xx_dma_copy_release(void); + +rtems_status_code lpc24xx_dma_copy( + unsigned channel, + void *dest, + const void *src, + size_t n, + size_t width +); + +rtems_status_code lpc24xx_dma_copy_wait(unsigned channel); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_DMA_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/i2c.h b/bsps/arm/lpc24xx/include/bsp/i2c.h new file mode 100644 index 0000000000..42836ddfa8 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/i2c.h @@ -0,0 +1,71 @@ +/** + * @file + * + * @ingroup lpc24xx_libi2c + * + * @brief LibI2C bus driver for the I2C modules. + */ + +/* + * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_I2C_H +#define LIBBSP_ARM_LPC24XX_I2C_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc24xx_libi2c LPC24XX Bus Drivers + * + * @ingroup libi2c + * + * @brief LibI2C bus drivers for LPC24XX. + * + * @{ + */ + +typedef struct { + rtems_libi2c_bus_t bus; + volatile lpc24xx_i2c *regs; + size_t index; + const lpc24xx_pin_range *pins; + rtems_vector_number vector; + rtems_id state_update; + uint8_t *volatile data; + uint8_t *volatile end; +} lpc24xx_i2c_bus_entry; + +extern const rtems_libi2c_bus_ops_t lpc24xx_i2c_ops; + +extern rtems_libi2c_bus_t *const lpc24xx_i2c_0; + +extern rtems_libi2c_bus_t *const lpc24xx_i2c_1; + +extern rtems_libi2c_bus_t *const lpc24xx_i2c_2; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_I2C_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/io.h b/bsps/arm/lpc24xx/include/bsp/io.h new file mode 100644 index 0000000000..9f58ee8efb --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/io.h @@ -0,0 +1,1154 @@ +/** + * @file + * + * @ingroup lpc24xx_io + * + * @brief Input and output module. + */ + +/* + * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_IO_H +#define LIBBSP_ARM_LPC24XX_IO_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc24xx_io IO Support and Configuration + * + * @ingroup lpc24xx + * + * @brief Input and output module. + * + * @{ + */ + +#define LPC24XX_IO_PORT_COUNT 5U + +#define LPC24XX_IO_INDEX_MAX (LPC24XX_IO_PORT_COUNT * 32U) + +#define LPC24XX_IO_INDEX_BY_PORT(port, bit) (((port) << 5U) + (bit)) + +#define LPC24XX_IO_PORT(index) ((index) >> 5U) + +#define LPC24XX_IO_PORT_BIT(index) ((index) & 0x1fU) + +typedef enum { + #ifdef ARM_MULTILIB_ARCH_V4 + LPC24XX_MODULE_ACF, + #endif + LPC24XX_MODULE_ADC, + #ifdef ARM_MULTILIB_ARCH_V4 + LPC24XX_MODULE_BAT_RAM, + #endif + LPC24XX_MODULE_CAN_0, + LPC24XX_MODULE_CAN_1, + LPC24XX_MODULE_DAC, + LPC24XX_MODULE_EMC, + LPC24XX_MODULE_ETHERNET, + LPC24XX_MODULE_GPDMA, + LPC24XX_MODULE_GPIO, + LPC24XX_MODULE_I2C_0, + LPC24XX_MODULE_I2C_1, + LPC24XX_MODULE_I2C_2, + LPC24XX_MODULE_I2S, + LPC24XX_MODULE_LCD, + LPC24XX_MODULE_MCI, + #ifdef ARM_MULTILIB_ARCH_V7M + LPC24XX_MODULE_MCPWM, + #endif + LPC24XX_MODULE_PCB, + LPC24XX_MODULE_PWM_0, + LPC24XX_MODULE_PWM_1, + #ifdef ARM_MULTILIB_ARCH_V7M + LPC24XX_MODULE_QEI, + #endif + LPC24XX_MODULE_RTC, + #ifdef ARM_MULTILIB_ARCH_V4 + LPC24XX_MODULE_SPI, + #endif + LPC24XX_MODULE_SSP_0, + LPC24XX_MODULE_SSP_1, + #ifdef ARM_MULTILIB_ARCH_V7M + LPC24XX_MODULE_SSP_2, + #endif + LPC24XX_MODULE_SYSCON, + LPC24XX_MODULE_TIMER_0, + LPC24XX_MODULE_TIMER_1, + LPC24XX_MODULE_TIMER_2, + LPC24XX_MODULE_TIMER_3, + LPC24XX_MODULE_UART_0, + LPC24XX_MODULE_UART_1, + LPC24XX_MODULE_UART_2, + LPC24XX_MODULE_UART_3, + #ifdef ARM_MULTILIB_ARCH_V7M + LPC24XX_MODULE_UART_4, + #endif + #ifdef ARM_MULTILIB_ARCH_V4 + LPC24XX_MODULE_WDT, + #endif + LPC24XX_MODULE_USB +} lpc24xx_module; + +#define LPC24XX_MODULE_COUNT (LPC24XX_MODULE_USB + 1) + +typedef enum { + LPC24XX_MODULE_PCLK_DEFAULT = 0x4U, + LPC24XX_MODULE_CCLK = 0x1U, + LPC24XX_MODULE_CCLK_2 = 0x2U, + LPC24XX_MODULE_CCLK_4 = 0x0U, + LPC24XX_MODULE_CCLK_6 = 0x3U, + LPC24XX_MODULE_CCLK_8 = 0x3U +} lpc24xx_module_clock; + +#define LPC24XX_MODULE_CLOCK_MASK 0x3U + +typedef enum { + LPC24XX_GPIO_DEFAULT = 0x0U, + LPC24XX_GPIO_RESISTOR_PULL_UP = 0x0U, + LPC24XX_GPIO_RESISTOR_NONE = 0x1U, + LPC24XX_GPIO_RESISTOR_PULL_DOWN = 0x2U, + LPC24XX_GPIO_INPUT = 0x0U, + #ifdef ARM_MULTILIB_ARCH_V7M + LPC17XX_GPIO_REPEATER = 0x3U, + LPC17XX_GPIO_HYSTERESIS = IOCON_HYS, + LPC17XX_GPIO_INPUT_INVERT = IOCON_INV, + LPC17XX_GPIO_FAST_MODE = IOCON_SLEW, + LPC17XX_GPIO_OPEN_DRAIN = IOCON_OD, + LPC17XX_GPIO_INPUT_FILTER = IOCON_FILTER, + #endif + LPC24XX_GPIO_OUTPUT = 0x8000U +} lpc24xx_gpio_settings; + +rtems_status_code lpc24xx_module_enable( + lpc24xx_module module, + lpc24xx_module_clock clock +); + +rtems_status_code lpc24xx_module_disable( + lpc24xx_module module +); + +bool lpc24xx_module_is_enabled(lpc24xx_module module); + +rtems_status_code lpc24xx_gpio_config( + unsigned index, + lpc24xx_gpio_settings settings +); + +static inline void lpc24xx_gpio_set(unsigned index) +{ + if (index <= LPC24XX_IO_INDEX_MAX) { + unsigned port = LPC24XX_IO_PORT(index); + unsigned bit = LPC24XX_IO_PORT_BIT(index); + + LPC24XX_FIO [port].set = 1U << bit; + } +} + +static inline void lpc24xx_gpio_clear(unsigned index) +{ + if (index <= LPC24XX_IO_INDEX_MAX) { + unsigned port = LPC24XX_IO_PORT(index); + unsigned bit = LPC24XX_IO_PORT_BIT(index); + + LPC24XX_FIO [port].clr = 1U << bit; + } +} + +static inline void lpc24xx_gpio_write(unsigned index, bool value) +{ + if (value) { + lpc24xx_gpio_set(index); + } else { + lpc24xx_gpio_clear(index); + } +} + +static inline bool lpc24xx_gpio_get(unsigned index) +{ + if (index <= LPC24XX_IO_INDEX_MAX) { + unsigned port = LPC24XX_IO_PORT(index); + unsigned bit = LPC24XX_IO_PORT_BIT(index); + + return (LPC24XX_FIO [port].pin & (1U << bit)) != 0; + } else { + return false; + } +} + +typedef enum { + /** + * @brief Sets the pin function. + */ + LPC24XX_PIN_SET_FUNCTION, + + /** + * @brief Checks if all pins are configured with the specified function. + */ + LPC24XX_PIN_CHECK_FUNCTION, + + /** + * @brief Configures the pins as input. + */ + LPC24XX_PIN_SET_INPUT, + + /** + * @brief Checks if all pins are configured as input. + */ + LPC24XX_PIN_CHECK_INPUT +} lpc24xx_pin_action; + +typedef union { + struct { + uint16_t port : 3; + uint16_t port_bit : 5; + uint16_t function : 3; + uint16_t type : 4; + uint16_t range : 1; + } fields; + uint16_t value; +} lpc24xx_pin_range; + +typedef enum { + LPC24XX_PIN_FUNCTION_00, + LPC24XX_PIN_FUNCTION_01, + LPC24XX_PIN_FUNCTION_10, + LPC24XX_PIN_FUNCTION_11 +} lpc24xx_pin_function; + +typedef enum { + LPC17XX_PIN_TYPE_DEFAULT, + LPC17XX_PIN_TYPE_ADC, + LPC17XX_PIN_TYPE_DAC, + LPC17XX_PIN_TYPE_I2C, + LPC17XX_PIN_TYPE_I2C_FAST_PLUS, + LPC17XX_PIN_TYPE_OPEN_DRAIN +} lpc17xx_pin_type; + +#ifdef ARM_MULTILIB_ARCH_V4 + #define LPC24XX_PIN(p, i, f0, f1) { { p, i, f0, 0, 0 } } + #define LPC24XX_PIN_WITH_TYPE(p, i, f0, f1, t) { { p, i, f0, t, 0 } } + #define LPC24XX_PIN_RANGE(p, i, j, f0, f1) \ + { { p, i, f0, 0, 0 } }, { { p, j, f0, 0, 1 } } +#else + #define LPC24XX_PIN(p, i, f0, f1) { { p, i, f1, 0, 0 } } + #define LPC24XX_PIN_WITH_TYPE(p, i, f0, f1, t) { { p, i, f1, t, 0 } } + #define LPC24XX_PIN_RANGE(p, i, j, f0, f1) \ + { { p, i, f1, 0, 0 } }, { { p, j, f1, 0, 1 } } +#endif + +#define LPC24XX_PIN_TERMINAL { { 0x7, 0x1f, 0x7, 0xf, 0x1 } } + +/** + * @brief Performs the @a action with the @a pins + * + * @code + * #include + * #include + * + * void example(void) + * { + * static const lpc24xx_pin_range pins [] = { + * LPC24XX_PIN_I2S_RX_CLK_P0_4, + * LPC24XX_PIN_I2S_RX_WS_P0_5, + * LPC24XX_PIN_I2S_RX_SDA_P0_6, + * LPC24XX_PIN_I2S_TX_CLK_P0_7, + * LPC24XX_PIN_I2S_TX_WS_P0_8, + * LPC24XX_PIN_I2S_TX_SDA_P0_9, + * LPC24XX_PIN_TERMINAL + * }; + * rtems_status_code sc = RTEMS_SUCCESSFUL; + * + * sc = lpc24xx_module_enable(LPC24XX_MODULE_I2S, LPC24XX_MODULE_CCLK_8); + * assert(sc == RTEMS_SUCCESSFUL); + * sc = lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION); + * assert(sc == RTEMS_SUCCESSFUL); + * } + * @endcode + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Check failed. + * @retval RTEMS_NOT_DEFINED Invalid action. + */ +rtems_status_code lpc24xx_pin_config( + const lpc24xx_pin_range *pins, + lpc24xx_pin_action action +); + +/** + * @brief Returns the first pin index of a pin range. + */ +static inline unsigned lpc24xx_pin_get_first_index( + const lpc24xx_pin_range *range +) +{ + return LPC24XX_IO_INDEX_BY_PORT(range->fields.port, range->fields.port_bit); +} + +/** + * @name ADC Pins + * + * @{ + */ + +#define LPC24XX_PIN_ADC_CHANNEL_0 \ + LPC24XX_PIN_WITH_TYPE(0, 23, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_1 \ + LPC24XX_PIN_WITH_TYPE(0, 24, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_2 \ + LPC24XX_PIN_WITH_TYPE(0, 25, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_3 \ + LPC24XX_PIN_WITH_TYPE(0, 26, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_4 \ + LPC24XX_PIN_WITH_TYPE(1, 30, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_5 \ + LPC24XX_PIN_WITH_TYPE(1, 31, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_6 \ + LPC24XX_PIN_WITH_TYPE(0, 12, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_7 \ + LPC24XX_PIN_WITH_TYPE(0, 13, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC) + +/** @} */ + +/** + * @name CAN 0 Pins + * + * @{ + */ + +#define LPC24XX_PIN_CAN_0_RD_P0_0 \ + LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_CAN_0_RD_P0_21 \ + LPC24XX_PIN(0, 21, LPC24XX_PIN_FUNCTION_11, 4) + +#define LPC24XX_PIN_CAN_0_TD_P0_1 \ + LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_CAN_0_TD_P0_22 \ + LPC24XX_PIN(0, 22, LPC24XX_PIN_FUNCTION_11, 4) + +/** @} */ + +/** + * @name CAN 1 Pins + * + * @{ + */ + +#define LPC24XX_PIN_CAN_1_RD_P0_4 \ + LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_CAN_1_RD_P2_7 \ + LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_CAN_1_TD_P0_5 \ + LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_CAN_1_TD_P2_8 \ + LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** + * @name DAC Pins + * + * @{ + */ + +#define LPC24XX_PIN_DAC \ + LPC24XX_PIN_WITH_TYPE(0, 26, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_DAC) + +/** @} */ + +/** + * @name Ethernet Pins + * + * @{ + */ + +#define LPC24XX_PIN_ETHERNET_MII \ + LPC24XX_PIN_RANGE(1, 0, 17, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_ETHERNET_RMII_0 \ + LPC24XX_PIN_RANGE(1, 0, 1, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_ETHERNET_RMII_1 \ + LPC24XX_PIN(1, 4, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_ETHERNET_RMII_2 \ + LPC24XX_PIN_RANGE(1, 8, 10, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_ETHERNET_RMII_3 \ + LPC24XX_PIN_RANGE(1, 14, 17, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** + * @name External Interrupt Pins + * + * @{ + */ + +#define LPC24XX_PIN_EINT_0 \ + LPC24XX_PIN(2, 10, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EINT_1 \ + LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EINT_2 \ + LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EINT_3 \ + LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** + * @name External Memory Controller (EMC) Pins + * + * @{ + */ + +#define LPC24XX_PIN_EMC_CS_0 \ + LPC24XX_PIN(4, 30, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CS_1 \ + LPC24XX_PIN(4, 31, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CS_2 \ + LPC24XX_PIN(2, 14, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CS_3 \ + LPC24XX_PIN(2, 15, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_DYCS_0 \ + LPC24XX_PIN(2, 20, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_DYCS_1 \ + LPC24XX_PIN(2, 21, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_DYCS_2 \ + LPC24XX_PIN(2, 22, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_DYCS_3 \ + LPC24XX_PIN(2, 23, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_OE \ + LPC24XX_PIN(4, 24, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_WE \ + LPC24XX_PIN(4, 25, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CAS \ + LPC24XX_PIN(2, 16, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_RAS \ + LPC24XX_PIN(2, 17, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_CLK_0 \ + LPC24XX_PIN(2, 18, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CLK_1 \ + LPC24XX_PIN(2, 19, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_CKE_0 \ + LPC24XX_PIN(2, 24, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CKE_1 \ + LPC24XX_PIN(2, 25, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CKE_2 \ + LPC24XX_PIN(2, 26, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CKE_3 \ + LPC24XX_PIN(2, 27, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_DQM_0 \ + LPC24XX_PIN(2, 28, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_DQM_1 \ + LPC24XX_PIN(2, 29, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_DQM_2 \ + LPC24XX_PIN(2, 30, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_DQM_3 \ + LPC24XX_PIN(2, 31, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_BLS0 \ + LPC24XX_PIN(4, 26, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_BLS1 \ + LPC24XX_PIN(4, 27, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_BLS2 \ + LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_BLS3 \ + LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_D_0_15 \ + LPC24XX_PIN_RANGE(3, 0, 15, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_D_15_31 \ + LPC24XX_PIN_RANGE(3, 15, 31, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_D_0_31 \ + LPC24XX_PIN_RANGE(3, 0, 31, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_A_0_12 \ + LPC24XX_PIN_RANGE(4, 0, 12, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_13 \ + LPC24XX_PIN_RANGE(4, 0, 13, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_14 \ + LPC24XX_PIN_RANGE(4, 0, 14, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_15 \ + LPC24XX_PIN_RANGE(4, 0, 15, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_16 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN(4, 16, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_17 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 17, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_18 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 18, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_19 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 19, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_20 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 20, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_21 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 21, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_22 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 22, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_23 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 23, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_24 \ + LPC24XX_PIN_EMC_A_0_23, \ + LPC24XX_PIN(5, 24, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_25 \ + LPC24XX_PIN_EMC_A_0_23, \ + LPC24XX_PIN_RANGE(5, 24, 25, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** + * @name I2C 0 Pins + * + * @{ + */ + +#define LPC24XX_PIN_I2C_0_SDA \ + LPC24XX_PIN_WITH_TYPE(0, 27, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_0_SCL \ + LPC24XX_PIN_WITH_TYPE(0, 28, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_I2C) + +/** @} */ + +/** + * @name I2C 1 Pins + * + * @{ + */ + +#define LPC24XX_PIN_I2C_1_SDA_P0_0 \ + LPC24XX_PIN_WITH_TYPE(0, 0, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_1_SDA_P0_19 \ + LPC24XX_PIN_WITH_TYPE(0, 19, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_1_SDA_P2_14 \ + LPC24XX_PIN_WITH_TYPE(2, 14, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C) + +#define LPC24XX_PIN_I2C_1_SCL_P0_1 \ + LPC24XX_PIN_WITH_TYPE(0, 1, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_1_SCL_P0_20 \ + LPC24XX_PIN_WITH_TYPE(0, 20, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_1_SCL_P2_15 \ + LPC24XX_PIN_WITH_TYPE(2, 15, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C) + +/** @} */ + +/** + * @name I2C 2 Pins + * + * @{ + */ + +#define LPC24XX_PIN_I2C_2_SDA_P0_10 \ + LPC24XX_PIN_WITH_TYPE(0, 10, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_2_SDA_P2_30 \ + LPC24XX_PIN_WITH_TYPE(2, 30, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_2_SDA_P4_20 \ + LPC24XX_PIN_WITH_TYPE(4, 20, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C) + +#define LPC24XX_PIN_I2C_2_SCL_P0_11 \ + LPC24XX_PIN_WITH_TYPE(0, 11, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_2_SCL_P2_31 \ + LPC24XX_PIN_WITH_TYPE(2, 31, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_2_SCL_P4_21 \ + LPC24XX_PIN_WITH_TYPE(4, 21, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C) + +/** @} */ + +/** + * @name I2S Pins + * + * @{ + */ + +#define LPC24XX_PIN_I2S_RX_CLK_P0_4 \ + LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_I2S_RX_CLK_P0_23 \ + LPC24XX_PIN(0, 23, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_I2S_RX_WS_P0_5 \ + LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_I2S_RX_WS_P0_24 \ + LPC24XX_PIN(0, 24, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_I2S_RX_SDA_P0_6 \ + LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_I2S_RX_SDA_P0_25 \ + LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_I2S_TX_CLK_P0_7 \ + LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_I2S_TX_CLK_P2_11 \ + LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_11, 3) + +#define LPC24XX_PIN_I2S_TX_WS_P0_8 \ + LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_I2S_TX_WS_P2_12 \ + LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_11, 3) + +#define LPC24XX_PIN_I2S_TX_SDA_P0_9 \ + LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_I2S_TX_SDA_P2_13 \ + LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_11, 3) + +/** @} */ + +/** + * @name LCD Pins + * + * @{ + */ + +#define LPC24XX_PIN_LCD_PWR \ + LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_LE \ + LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_DCLK \ + LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_FP \ + LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_ENAB_M \ + LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_LP \ + LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_CLKIN \ + LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_01, 7) + +#define LPC24XX_PIN_LCD_VD_0_P0_4 \ + LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_0_P2_6 \ + LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_11, 6) +#define LPC24XX_PIN_LCD_VD_1_P0_5 \ + LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_1_P2_7 \ + LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_11, 6) +#define LPC24XX_PIN_LCD_VD_2_P2_8 \ + LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_11, 6) +#define LPC24XX_PIN_LCD_VD_2_P4_28 \ + LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 7) +#define LPC24XX_PIN_LCD_VD_3_P2_9 \ + LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_11, 6) +#define LPC24XX_PIN_LCD_VD_3_P2_12 \ + LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 5) +#define LPC24XX_PIN_LCD_VD_3_P4_29 \ + LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 7) +#define LPC24XX_PIN_LCD_VD_4_P2_6 \ + LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_VD_4_P2_12 \ + LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 4) +#define LPC24XX_PIN_LCD_VD_5_P2_7 \ + LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_VD_5_P2_13 \ + LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 5) +#define LPC24XX_PIN_LCD_VD_6_P1_20 \ + LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_6_P2_8 \ + LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_VD_6_P4_28 \ + LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 5) +#define LPC24XX_PIN_LCD_VD_7_P1_21 \ + LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_7_P2_9 \ + LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_VD_7_P4_29 \ + LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 5) +#define LPC24XX_PIN_LCD_VD_8_P0_6 \ + LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_8_P1_22 \ + LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_8_P2_12 \ + LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_9_P0_7 \ + LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_9_P1_23 \ + LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_9_P2_13 \ + LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_10_P1_20 \ + LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_10_P1_24 \ + LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_10_P4_28 \ + LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 6) +#define LPC24XX_PIN_LCD_VD_11_P1_21 \ + LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_11_P1_25 \ + LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_11_P4_29 \ + LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 6) +#define LPC24XX_PIN_LCD_VD_12_P1_22 \ + LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_12_P1_26 \ + LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_13_P1_23 \ + LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_13_P1_27 \ + LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_14_P1_24 \ + LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_14_P1_28 \ + LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_15_P1_25 \ + LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_15_P1_29 \ + LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_16_P0_8 \ + LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_17_P0_9 \ + LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_18_P2_12 \ + LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_19_P2_13 \ + LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_20_P1_26 \ + LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_21_P1_27 \ + LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_22_P1_28 \ + LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_23_P1_29 \ + LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01, 7) + +/** @} */ + +/** + * @name PWM 0 Pins + * + * @{ + */ + +#define LPC24XX_PIN_PWM_0_CHANNEL_1_P1_2 \ + LPC24XX_PIN(1, 2, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CHANNEL_1_P3_16 \ + LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_PWM_0_CHANNEL_2_P1_3 \ + LPC24XX_PIN(1, 3, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CHANNEL_2_P3_17 \ + LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_PWM_0_CHANNEL_3_P1_5 \ + LPC24XX_PIN(1, 5, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CHANNEL_3_P3_18 \ + LPC24XX_PIN(3, 18, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_PWM_0_CHANNEL_4_P1_6 \ + LPC24XX_PIN(1, 6, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CHANNEL_4_P3_19 \ + LPC24XX_PIN(3, 19, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_PWM_0_CHANNEL_5_P1_7 \ + LPC24XX_PIN(1, 7, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CHANNEL_5_P3_20 \ + LPC24XX_PIN(3, 20, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_PWM_0_CHANNEL_6_P1_11 \ + LPC24XX_PIN(1, 11, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CHANNEL_6_P3_21 \ + LPC24XX_PIN(3, 21, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_PWM_0_CAPTURE_0_P1_12 \ + LPC24XX_PIN(1, 12, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CAPTURE_0_P3_22 \ + LPC24XX_PIN(3, 22, LPC24XX_PIN_FUNCTION_10, 2) + +/** @} */ + +/** + * @name PWM 1 Pins + * + * @{ + */ + +#define LPC24XX_PIN_PWM_1_CHANNEL_1_P1_18 \ + LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CHANNEL_1_P2_0 \ + LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CHANNEL_1_P3_24 \ + LPC24XX_PIN(3, 24, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_PWM_1_CHANNEL_2_P1_20 \ + LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CHANNEL_2_P2_1 \ + LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CHANNEL_2_P3_25 \ + LPC24XX_PIN(3, 25, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_PWM_1_CHANNEL_3_P1_21 \ + LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CHANNEL_3_P2_2 \ + LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CHANNEL_3_P3_26 \ + LPC24XX_PIN(3, 26, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_PWM_1_CHANNEL_4_P1_23 \ + LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CHANNEL_4_P2_3 \ + LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CHANNEL_4_P3_27 \ + LPC24XX_PIN(3, 27, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_PWM_1_CHANNEL_5_P1_24 \ + LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CHANNEL_5_P2_4 \ + LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CHANNEL_5_P3_28 \ + LPC24XX_PIN(3, 28, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_PWM_1_CHANNEL_6_P1_26 \ + LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CHANNEL_6_P2_5 \ + LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CHANNEL_6_P3_29 \ + LPC24XX_PIN(3, 29, LPC24XX_PIN_FUNCTIO9_11, 2) + +#define LPC24XX_PIN_PWM_1_CAPTURE_0_P1_28 \ + LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CAPTURE_0_P2_7 \ + LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CAPTURE_0_P3_23 \ + LPC24XX_PIN(3, 23, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_PWM_1_CAPTURE_1_P1_29 \ + LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_10, 2) + +/** @} */ + +#ifdef ARM_MULTILIB_ARCH_V4 + +/** + * @name SPI Pins + * + * @{ + */ + +#define LPC24XX_PIN_SPI_SCK \ + LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_11) +#define LPC24XX_PIN_SPI_SSEL \ + LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_11) +#define LPC24XX_PIN_SPI_MISO \ + LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_11) +#define LPC24XX_PIN_SPI_MOSI \ + LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_11) + +/** @} */ + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/** + * @name SSP 0 Pins + * + * @{ + */ + +#define LPC24XX_PIN_SSP_0_SCK_P0_15 \ + LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_0_SCK_P1_20 \ + LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_11, 5) +#define LPC24XX_PIN_SSP_0_SCK_P2_22 \ + LPC24XX_PIN(2, 22, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_SSP_0_SSEL_P0_16 \ + LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_0_SSEL_P1_21 \ + LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_SSP_0_SSEL_P2_23 \ + LPC24XX_PIN(2, 23, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_SSP_0_MISO_P0_17 \ + LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_0_MISO_P1_23 \ + LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_11, 5) +#define LPC24XX_PIN_SSP_0_MISO_P2_26 \ + LPC24XX_PIN(2, 26, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_SSP_0_MOSI_P0_18 \ + LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_0_MOSI_P1_24 \ + LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_11, 5) +#define LPC24XX_PIN_SSP_0_MOSI_P2_27 \ + LPC24XX_PIN(2, 27, LPC24XX_PIN_FUNCTION_11, 2) + +/** @} */ + +/** + * @name SSP 1 Pins + * + * @{ + */ + +#define LPC24XX_PIN_SSP_1_SCK_P0_6 \ + LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_SCK_P0_12 \ + LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_SCK_P4_20 \ + LPC24XX_PIN(4, 20, LPC24XX_PIN_FUNCTION_11, 3) + +#define LPC24XX_PIN_SSP_1_SSEL_P0_7 \ + LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_SSEL_P0_13 \ + LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_11, 2) +#define LPC24XX_PIN_SSP_1_SSEL_P4_21 \ + LPC24XX_PIN(4, 21, LPC24XX_PIN_FUNCTION_11, 3) + +#define LPC24XX_PIN_SSP_1_MISO_P0_8 \ + LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_MISO_P0_14 \ + LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_MISO_P4_22 \ + LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_11, 3) + +#define LPC24XX_PIN_SSP_1_MOSI_P0_9 \ + LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_MOSI_P1_31 \ + LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_MOSI_P4_23 \ + LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_11, 3) + +/** @} */ + +#ifdef ARM_MULTILIB_ARCH_V7M + +/** + * @name SSP 2 Pins + * + * @{ + */ + +#define LPC24XX_PIN_SSP_2_SCK_P1_0 \ + LPC24XX_PIN(1, 0, LPC24XX_PIN_FUNCTION_00, 4) + +#define LPC24XX_PIN_SSP_2_SSEL_P1_8 \ + LPC24XX_PIN(1, 8, LPC24XX_PIN_FUNCTION_00, 4) + +#define LPC24XX_PIN_SSP_2_MISO_P1_4 \ + LPC24XX_PIN(1, 4, LPC24XX_PIN_FUNCTION_00, 4) + +#define LPC24XX_PIN_SSP_2_MOSI_P1_1 \ + LPC24XX_PIN(1, 1, LPC24XX_PIN_FUNCTION_00, 4) + +/** @} */ + +#endif /* ARM_MULTILIB_ARCH_V7M */ + +/** + * @name UART 0 Pins + * + * @{ + */ + +#define LPC24XX_PIN_UART_0_TXD \ + LPC24XX_PIN(0, 2, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_UART_0_RXD \ + LPC24XX_PIN(0, 3, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** + * @name UART 1 Pins + * + * @{ + */ + +#define LPC24XX_PIN_UART_1_TXD_P0_15 \ + LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_UART_1_TXD_P2_0 \ + LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_UART_1_TXD_P3_16 \ + LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_11, 3) + +#define LPC24XX_PIN_UART_1_RXD_P0_16 \ + LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_UART_1_RXD_P2_1 \ + LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_UART_1_RXD_P3_17 \ + LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_11, 3) + +/** @} */ + +/** + * @name UART 2 Pins + * + * @{ + */ + +#define LPC24XX_PIN_UART_2_TXD_P0_10 \ + LPC24XX_PIN(0, 10, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_UART_2_TXD_P2_8 \ + LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_UART_2_TXD_P4_22 \ + LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_UART_2_RXD_P0_11 \ + LPC24XX_PIN(0, 11, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_UART_2_RXD_P2_9 \ + LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_UART_2_RXD_P4_23 \ + LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_10, 2) + +/** @} */ + +/** + * @name UART 3 Pins + * + * @{ + */ + +#define LPC24XX_PIN_UART_3_TXD_P0_0 \ + LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_UART_3_TXD_P0_25 \ + LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_UART_3_TXD_P4_28 \ + LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_UART_3_RXD_P0_1 \ + LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_UART_3_RXD_P0_26 \ + LPC24XX_PIN(0, 26, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_UART_3_RXD_P4_29 \ + LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_11, 2) + +/** @} */ + +#ifdef ARM_MULTILIB_ARCH_V7M + +/** + * @name UART 4 Pins + * + * @{ + */ + +#define LPC24XX_PIN_UART_4_TXD_P0_22 \ + LPC24XX_PIN(0, 22, LPC24XX_PIN_FUNCTION_00, 3) +#define LPC24XX_PIN_UART_4_TXD_P1_29 \ + LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_00, 5) +#define LPC24XX_PIN_UART_4_TXD_P5_4 \ + LPC24XX_PIN(5, 4, LPC24XX_PIN_FUNCTION_00, 4) + +#define LPC24XX_PIN_UART_4_RXD_P2_9 \ + LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_00, 3) +#define LPC24XX_PIN_UART_4_RXD_P5_3 \ + LPC24XX_PIN(5, 3, LPC24XX_PIN_FUNCTION_00, 4) + +#define LPC24XX_PIN_UART_4_OE_P0_21 \ + LPC24XX_PIN(0, 21, LPC24XX_PIN_FUNCTION_00, 3) + +#define LPC24XX_PIN_UART_4_SCLK_P0_21 \ + LPC24XX_PIN(0, 21, LPC24XX_PIN_FUNCTION_00, 5) + +#endif /* ARM_MULTILIB_ARCH_V7M */ + +/** @} */ + +/** + * @name USB Port 1 Pins + * + * @{ + */ + +#define LPC24XX_PIN_USB_D_PLUS_1\ + LPC24XX_PIN(0, 29, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_D_MINUS_1\ + LPC24XX_PIN(0, 30, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_UP_LED_1\ + LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_TX_E_1\ + LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_PPWR_1\ + LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_USB_TX_DP_1\ + LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_TX_DM_1\ + LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_RCV_1\ + LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_PWRD_1\ + LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_USB_RX_DP_1\ + LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_RX_DM_1\ + LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_LS_1\ + LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_HSTEN_1\ + LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_USB_SSPND_1\ + LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_INT_1\ + LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_OVRCR_1\ + LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_USB_SCL_1\ + LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_SDA_1 \ + LPC24XX_PIN_WITH_TYPE( \ + 1, 29, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_OPEN_DRAIN \ + ) +#define LPC24XX_PIN_USB_CONNECT_1\ + LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** + * @name USB Port 2 Pins + * + * @{ + */ + +#define LPC24XX_PIN_USB_PPWR_2\ + LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_UP_LED_2\ + LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_HSTEN_2\ + LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_CONNECT_2\ + LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01, 3) +#define LPC24XX_PIN_USB_D_PLUS_2\ + LPC24XX_PIN(0, 31, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_PWRD_2\ + LPC24XX_PIN(1, 30, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_OVRCR_2\ + LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_IO_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/irq.h b/bsps/arm/lpc24xx/include/bsp/irq.h new file mode 100644 index 0000000000..0f0e473a0c --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/irq.h @@ -0,0 +1,140 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief LPC24XX interrupt definitions. + */ + +/* + * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_IRQ_H +#define LIBBSP_ARM_LPC24XX_IRQ_H + +#ifndef ASM + #include + #include + #include +#endif + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#ifdef ARM_MULTILIB_ARCH_V4 + #define LPC24XX_IRQ_WDT 0 + #define LPC24XX_IRQ_SOFTWARE 1 + #define LPC24XX_IRQ_ARM_CORE_0 2 + #define LPC24XX_IRQ_ARM_CORE_1 3 + #define LPC24XX_IRQ_TIMER_0 4 + #define LPC24XX_IRQ_TIMER_1 5 + #define LPC24XX_IRQ_UART_0 6 + #define LPC24XX_IRQ_UART_1 7 + #define LPC24XX_IRQ_PWM 8 + #define LPC24XX_IRQ_I2C_0 9 + #define LPC24XX_IRQ_SPI_SSP_0 10 + #define LPC24XX_IRQ_SSP_1 11 + #define LPC24XX_IRQ_PLL 12 + #define LPC24XX_IRQ_RTC 13 + #define LPC24XX_IRQ_EINT_0 14 + #define LPC24XX_IRQ_EINT_1 15 + #define LPC24XX_IRQ_EINT_2 16 + #define LPC24XX_IRQ_EINT_3 17 + #define LPC24XX_IRQ_ADC_0 18 + #define LPC24XX_IRQ_I2C_1 19 + #define LPC24XX_IRQ_BOD 20 + #define LPC24XX_IRQ_ETHERNET 21 + #define LPC24XX_IRQ_USB 22 + #define LPC24XX_IRQ_CAN 23 + #define LPC24XX_IRQ_SD_MMC 24 + #define LPC24XX_IRQ_DMA 25 + #define LPC24XX_IRQ_TIMER_2 26 + #define LPC24XX_IRQ_TIMER_3 27 + #define LPC24XX_IRQ_UART_2 28 + #define LPC24XX_IRQ_UART_3 29 + #define LPC24XX_IRQ_I2C_2 30 + #define LPC24XX_IRQ_I2S 31 + + #define BSP_INTERRUPT_VECTOR_MAX 31 +#else + #define LPC24XX_IRQ_WDT 0 + #define LPC24XX_IRQ_TIMER_0 1 + #define LPC24XX_IRQ_TIMER_1 2 + #define LPC24XX_IRQ_TIMER_2 3 + #define LPC24XX_IRQ_TIMER_3 4 + #define LPC24XX_IRQ_UART_0 5 + #define LPC24XX_IRQ_UART_1 6 + #define LPC24XX_IRQ_UART_2 7 + #define LPC24XX_IRQ_UART_3 8 + #define LPC24XX_IRQ_PWM_1 9 + #define LPC24XX_IRQ_I2C_0 10 + #define LPC24XX_IRQ_I2C_1 11 + #define LPC24XX_IRQ_I2C_2 12 + #define LPC24XX_IRQ_SPI_SSP_0 14 + #define LPC24XX_IRQ_SSP_1 15 + #define LPC24XX_IRQ_PLL 16 + #define LPC24XX_IRQ_RTC 17 + #define LPC24XX_IRQ_EINT_0 18 + #define LPC24XX_IRQ_EINT_1 19 + #define LPC24XX_IRQ_EINT_2 20 + #define LPC24XX_IRQ_EINT_3 21 + #define LPC24XX_IRQ_ADC_0 22 + #define LPC24XX_IRQ_BOD 23 + #define LPC24XX_IRQ_USB 24 + #define LPC24XX_IRQ_CAN 25 + #define LPC24XX_IRQ_DMA 26 + #define LPC24XX_IRQ_I2S 27 + #define LPC24XX_IRQ_ETHERNET 28 + #define LPC24XX_IRQ_SD_MMC 29 + #define LPC24XX_IRQ_MCPWM 30 + #define LPC24XX_IRQ_QEI 31 + #define LPC24XX_IRQ_PLL_ALT 32 + #define LPC24XX_IRQ_USB_ACTIVITY 33 + #define LPC24XX_IRQ_CAN_ACTIVITY 34 + #define LPC24XX_IRQ_UART_4 35 + #define LPC24XX_IRQ_SSP_2 36 + #define LPC24XX_IRQ_LCD 37 + #define LPC24XX_IRQ_GPIO 38 + #define LPC24XX_IRQ_PWM 39 + #define LPC24XX_IRQ_EEPROM 40 + + #define BSP_INTERRUPT_VECTOR_MAX 40 +#endif + +#define LPC24XX_IRQ_PRIORITY_VALUE_MIN 0 +#ifdef ARM_MULTILIB_ARCH_V4 + #define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15 +#else + #define LPC24XX_IRQ_PRIORITY_VALUE_MAX 31 +#endif +#define LPC24XX_IRQ_PRIORITY_COUNT (LPC24XX_IRQ_PRIORITY_VALUE_MAX + 1) +#define LPC24XX_IRQ_PRIORITY_HIGHEST LPC24XX_IRQ_PRIORITY_VALUE_MIN +#define LPC24XX_IRQ_PRIORITY_LOWEST LPC24XX_IRQ_PRIORITY_VALUE_MAX + +#ifndef ASM + +void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority); + +unsigned lpc24xx_irq_get_priority(rtems_vector_number vector); + +#endif /* ASM */ + +/** @} */ + +#endif /* LIBBSP_ARM_LPC24XX_IRQ_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/lcd.h b/bsps/arm/lpc24xx/include/bsp/lcd.h new file mode 100644 index 0000000000..c415074bd4 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/lcd.h @@ -0,0 +1,91 @@ +/** + * @file + * + * @ingroup lpc24xx_lcd + * + * @brief LCD support. + */ + +/* + * Copyright (c) 2010-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_LCD_H +#define LIBBSP_ARM_LPC24XX_LCD_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_dma LCD Support + * + * @ingroup lpc24xx + * + * @brief LCD support. + * + * @{ + */ + +typedef enum { + #ifdef ARM_MULTILIB_ARCH_V4 + LCD_MODE_STN_4_BIT = 0, + LCD_MODE_STN_8_BIT, + LCD_MODE_STN_DUAL_PANEL_4_BIT, + LCD_MODE_STN_DUAL_PANEL_8_BIT, + LCD_MODE_TFT_12_BIT_4_4_4, + LCD_MODE_TFT_16_BIT_5_6_5, + LCD_MODE_TFT_16_BIT_1_5_5_5, + LCD_MODE_TFT_24_BIT, + LCD_MODE_DISABLED + #else + LCD_MODE_STN_4_BIT = 0x4, + LCD_MODE_STN_8_BIT = 0x6, + LCD_MODE_STN_DUAL_PANEL_4_BIT = 0x84, + LCD_MODE_STN_DUAL_PANEL_8_BIT = 0x86, + LCD_MODE_TFT_12_BIT_4_4_4 = 0x2e, + LCD_MODE_TFT_16_BIT_5_6_5 = 0x2c, + LCD_MODE_TFT_16_BIT_1_5_5_5 = 0x28, + LCD_MODE_TFT_24_BIT = 0x2a, + LCD_MODE_DISABLED = 0xff + #endif +} lpc24xx_lcd_mode; + +/** + * @brief Set the LCD @a mode. + * + * The pins are configured according to @a pins. + * + * @see lpc24xx_pin_config(). + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Invalid mode. + */ +rtems_status_code lpc24xx_lcd_set_mode( + lpc24xx_lcd_mode mode, + const lpc24xx_pin_range *pins +); + +lpc24xx_lcd_mode lpc24xx_lcd_current_mode(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_LCD_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/lpc-clock-config.h b/bsps/arm/lpc24xx/include/bsp/lpc-clock-config.h new file mode 100644 index 0000000000..5e6b469e0f --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/lpc-clock-config.h @@ -0,0 +1,49 @@ +/** + * @file + * + * @ingroup lpc24xx + * + * @brief Clock driver configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_LPC_CLOCK_CONFIG_H +#define LIBBSP_ARM_LPC24XX_LPC_CLOCK_CONFIG_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define LPC_CLOCK_INTERRUPT LPC24XX_IRQ_TIMER_0 + +#define LPC_CLOCK_TIMER_BASE TMR0_BASE_ADDR + +#define LPC_CLOCK_TIMECOUNTER_BASE TMR1_BASE_ADDR + +#define LPC_CLOCK_REFERENCE LPC24XX_PCLK + +#define LPC_CLOCK_MODULE_ENABLE() \ + lpc24xx_module_enable(LPC24XX_MODULE_TIMER_0, LPC24XX_MODULE_PCLK_DEFAULT) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_LPC_CLOCK_CONFIG_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/lpc-ethernet-config.h b/bsps/arm/lpc24xx/include/bsp/lpc-ethernet-config.h new file mode 100644 index 0000000000..d24f132567 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/lpc-ethernet-config.h @@ -0,0 +1,130 @@ +/** + * @file + * + * @ingroup lpc24xx + * + * @brief Ethernet driver configuration. + */ + +/* + * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_LPC_ETHERNET_CONFIG_H +#define LIBBSP_ARM_LPC24XX_LPC_ETHERNET_CONFIG_H + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define LPC_ETH_CONFIG_INTERRUPT LPC24XX_IRQ_ETHERNET + +#define LPC_ETH_CONFIG_REG_BASE MAC_BASE_ADDR + +#ifdef ARM_MULTILIB_ARCH_V4 + #define LPC_ETH_CONFIG_RX_UNIT_COUNT_DEFAULT 16 + #define LPC_ETH_CONFIG_RX_UNIT_COUNT_MAX 54 + + #define LPC_ETH_CONFIG_TX_UNIT_COUNT_DEFAULT 10 + #define LPC_ETH_CONFIG_TX_UNIT_COUNT_MAX 10 + + #define LPC_ETH_CONFIG_UNIT_MULTIPLE 1U + + #define LPC24XX_ETH_RAM_BEGIN 0x7fe00000U + #define LPC24XX_ETH_RAM_SIZE (16U * 1024U) +#else + #define LPC_ETH_CONFIG_RX_UNIT_COUNT_DEFAULT 16 + #define LPC_ETH_CONFIG_RX_UNIT_COUNT_MAX INT_MAX + + #define LPC_ETH_CONFIG_TX_UNIT_COUNT_DEFAULT 32 + #define LPC_ETH_CONFIG_TX_UNIT_COUNT_MAX INT_MAX + + #define LPC_ETH_CONFIG_UNIT_MULTIPLE 8U + + #define LPC_ETH_CONFIG_USE_TRANSMIT_DMA + + #define LPC24XX_ETH_RAM_BEGIN 0x20000000U + #define LPC24XX_ETH_RAM_SIZE (32U * 1024U) +#endif + +#ifdef LPC24XX_ETHERNET_RMII + #define LPC_ETH_CONFIG_RMII + + static void lpc_eth_config_module_enable(void) + { + static const lpc24xx_pin_range pins [] = { + #ifdef LPC24XX_PIN_ETHERNET_POWER_DOWN + LPC24XX_PIN_ETHERNET_POWER_DOWN, + #endif + LPC24XX_PIN_ETHERNET_RMII_0, + LPC24XX_PIN_ETHERNET_RMII_1, + LPC24XX_PIN_ETHERNET_RMII_2, + LPC24XX_PIN_ETHERNET_RMII_3, + LPC24XX_PIN_TERMINAL + }; + + lpc24xx_module_enable(LPC24XX_MODULE_ETHERNET, LPC24XX_MODULE_PCLK_DEFAULT); + lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION); + + #ifdef LPC24XX_PIN_ETHERNET_POWER_DOWN + { + unsigned pin = lpc24xx_pin_get_first_index(&pins[0]); + + lpc24xx_gpio_config(pin, LPC24XX_GPIO_OUTPUT); + lpc24xx_gpio_set(pin); + } + #endif + } +#else + static void lpc_eth_config_module_enable(void) + { + static const lpc24xx_pin_range pins [] = { + LPC24XX_PIN_ETHERNET_MII, + LPC24XX_PIN_TERMINAL + }; + + lpc24xx_module_enable(LPC24XX_MODULE_ETHERNET, LPC24XX_MODULE_PCLK_DEFAULT); + lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION); + } +#endif + +static void lpc_eth_config_module_disable(void) +{ + lpc24xx_module_disable(LPC24XX_MODULE_ETHERNET); +} + +static char *lpc_eth_config_alloc_table_area(size_t size) +{ + if (size < LPC24XX_ETH_RAM_SIZE) { + return (char *) LPC24XX_ETH_RAM_BEGIN; + } else { + return NULL; + } +} + +static void lpc_eth_config_free_table_area(char *table_area) +{ + /* Do nothing */ +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_LPC_ETHERNET_CONFIG_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/lpc17xx.h b/bsps/arm/lpc24xx/include/bsp/lpc17xx.h new file mode 100644 index 0000000000..9c35102e98 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/lpc17xx.h @@ -0,0 +1,207 @@ +/** + * @file + * + * @ingroup lpc24xx_regs + * + * @brief Register definitions. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LPC17XX_REGS_H +#define LPC17XX_REGS_H + +#include + +#define LPC17XX_BASE 0x00 + +typedef struct { +#define LPC17XX_WWDT_MOD_WDEN BSP_BIT32(0) +#define LPC17XX_WWDT_MOD_WDRESET BSP_BIT32(1) +#define LPC17XX_WWDT_MOD_WDTOF BSP_BIT32(2) +#define LPC17XX_WWDT_MOD_WDINT BSP_BIT32(3) +#define LPC17XX_WWDT_MOD_WDPROTECT BSP_BIT32(4) + uint32_t mod; + uint32_t tc; + uint32_t feed; + uint32_t tv; + uint32_t reserved_10; + uint32_t warnint; + uint32_t window; + uint32_t reserved_1c; +} lpc17xx_wwdt; + +#define LPC17XX_WWDT (*(volatile lpc17xx_wwdt *) (LPC17XX_BASE + 0x40000000)) + +typedef struct { +#define LPC17XX_PLL_CON_PLLE BSP_BIT32(0) +#define LPC17XX_PLL_SEL_MSEL(val) BSP_FLD32(val, 0, 4) +#define LPC17XX_PLL_SEL_MSEL_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LPC17XX_PLL_SEL_MSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define LPC17XX_PLL_SEL_PSEL(val) BSP_FLD32(val, 5, 6) +#define LPC17XX_PLL_SEL_PSEL_GET(reg) BSP_FLD32GET(reg, 5, 6) +#define LPC17XX_PLL_SEL_PSEL_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6) +#define LPC17XX_PLL_STAT_PLLE BSP_BIT32(8) +#define LPC17XX_PLL_STAT_PLOCK BSP_BIT32(10) + uint32_t con; + uint32_t cfg; + uint32_t stat; + uint32_t feed; +} lpc17xx_pll; + +typedef struct { + uint32_t flashcfg; +#define LPC17XX_SCB_FLASHCFG_FLASHTIM(val) BSP_FLD32(val, 12, 15) +#define LPC17XX_SCB_FLASHCFG_FLASHTIM_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define LPC17XX_SCB_FLASHCFG_FLASHTIM_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) + uint32_t reserved_04 [15]; + uint32_t memmap; +#define LPC17XX_SCB_MEMMAP_MAP BSP_BIT32(0) + uint32_t reserved_44 [15]; + lpc17xx_pll pll_0; + uint32_t reserved_90 [4]; + lpc17xx_pll pll_1; + uint32_t reserved_b0 [4]; + uint32_t pcon; +#define LPC17XX_SCB_PCON_PM0 BSP_BIT32(0) +#define LPC17XX_SCB_PCON_PM1 BSP_BIT32(1) +#define LPC17XX_SCB_PCON_BODRPM BSP_BIT32(2) +#define LPC17XX_SCB_PCON_BOGD BSP_BIT32(3) +#define LPC17XX_SCB_PCON_BORD BSP_BIT32(4) +#define LPC17XX_SCB_PCON_SMFLAG BSP_BIT32(8) +#define LPC17XX_SCB_PCON_DSFLAG BSP_BIT32(9) +#define LPC17XX_SCB_PCON_PDFLAG BSP_BIT32(10) +#define LPC17XX_SCB_PCON_DPDFLAG BSP_BIT32(11) + uint32_t pconp; +#define LPC17XX_SCB_PCONP_LCD BSP_BIT32(0) +#define LPC17XX_SCB_PCONP_TIMER_0 BSP_BIT32(1) +#define LPC17XX_SCB_PCONP_TIMER_1 BSP_BIT32(2) +#define LPC17XX_SCB_PCONP_UART_0 BSP_BIT32(3) +#define LPC17XX_SCB_PCONP_UART_1 BSP_BIT32(4) +#define LPC17XX_SCB_PCONP_PWM_0 BSP_BIT32(5) +#define LPC17XX_SCB_PCONP_PWM_1 BSP_BIT32(6) +#define LPC17XX_SCB_PCONP_I2C_0 BSP_BIT32(7) +#define LPC17XX_SCB_PCONP_UART_4 BSP_BIT32(8) +#define LPC17XX_SCB_PCONP_RTC BSP_BIT32(9) +#define LPC17XX_SCB_PCONP_SSP_1 BSP_BIT32(10) +#define LPC17XX_SCB_PCONP_EMC BSP_BIT32(11) +#define LPC17XX_SCB_PCONP_ADC BSP_BIT32(12) +#define LPC17XX_SCB_PCONP_CAN_0 BSP_BIT32(13) +#define LPC17XX_SCB_PCONP_CAN_1 BSP_BIT32(14) +#define LPC17XX_SCB_PCONP_GPIO BSP_BIT32(15) +#define LPC17XX_SCB_PCONP_QEI BSP_BIT32(17) +#define LPC17XX_SCB_PCONP_I2C_1 BSP_BIT32(18) +#define LPC17XX_SCB_PCONP_SSP_2 BSP_BIT32(19) +#define LPC17XX_SCB_PCONP_SSP_0 BSP_BIT32(20) +#define LPC17XX_SCB_PCONP_TIMER_2 BSP_BIT32(21) +#define LPC17XX_SCB_PCONP_TIMER_3 BSP_BIT32(22) +#define LPC17XX_SCB_PCONP_UART_2 BSP_BIT32(23) +#define LPC17XX_SCB_PCONP_UART_3 BSP_BIT32(24) +#define LPC17XX_SCB_PCONP_I2C_2 BSP_BIT32(25) +#define LPC17XX_SCB_PCONP_I2S BSP_BIT32(26) +#define LPC17XX_SCB_PCONP_SDC BSP_BIT32(27) +#define LPC17XX_SCB_PCONP_GPDMA BSP_BIT32(28) +#define LPC17XX_SCB_PCONP_ENET BSP_BIT32(29) +#define LPC17XX_SCB_PCONP_USB BSP_BIT32(30) +#define LPC17XX_SCB_PCONP_MCPWM BSP_BIT32(31) + uint32_t reserved_c8 [14]; + uint32_t emcclksel; +#define LPC17XX_SCB_EMCCLKSEL_EMCDIV BSP_BIT32(0) + uint32_t cclksel; +#define LPC17XX_SCB_CCLKSEL_CCLKDIV(val) BSP_FLD32(val, 0, 4) +#define LPC17XX_SCB_CCLKSEL_CCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LPC17XX_SCB_CCLKSEL_CCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define LPC17XX_SCB_CCLKSEL_CCLKSEL BSP_BIT32(8) + uint32_t usbclksel; +#define LPC17XX_SCB_USBCLKSEL_USBDIV(val) BSP_FLD32(val, 0, 4) +#define LPC17XX_SCB_USBCLKSEL_USBDIV_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LPC17XX_SCB_USBCLKSEL_USBDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define LPC17XX_SCB_USBCLKSEL_USBSEL(val) BSP_FLD32(val, 8, 9) +#define LPC17XX_SCB_USBCLKSEL_USBSEL_GET(reg) BSP_FLD32GET(reg, 8, 9) +#define LPC17XX_SCB_USBCLKSEL_USBSEL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9) + uint32_t clksrcsel; +#define LPC17XX_SCB_CLKSRCSEL_CLKSRC BSP_BIT32(0) + uint32_t reserved_110 [12]; + uint32_t extint; + uint32_t reserved_144; + uint32_t extmode; + uint32_t extpolar; + uint32_t reserved_150 [12]; + uint32_t rsid; + uint32_t reserved_184 [1]; + uint32_t matrixarb; + uint32_t reserved_18c [5]; + uint32_t scs; +#define LPC17XX_SCB_SCS_EMC_SHIFT_CTL BSP_BIT32(0) +#define LPC17XX_SCB_SCS_EMC_RESET_DIS BSP_BIT32(1) +#define LPC17XX_SCB_SCS_EMC_BURST_CTL BSP_BIT32(2) +#define LPC17XX_SCB_SCS_MCIPWR BSP_BIT32(3) +#define LPC17XX_SCB_SCS_OSC_RANGE_SEL BSP_BIT32(4) +#define LPC17XX_SCB_SCS_OSC_ENABLE BSP_BIT32(5) +#define LPC17XX_SCB_SCS_OSC_STATUS BSP_BIT32(6) + uint32_t reserved_1a4; + uint32_t pclksel; +#define LPC17XX_SCB_PCLKSEL_PCLKDIV(val) BSP_FLD32(val, 0, 4) +#define LPC17XX_SCB_PCLKSEL_PCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LPC17XX_SCB_PCLKSEL_PCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) + uint32_t reserved_1ac; + uint32_t pboost; +#define LPC17XX_SCB_PBOOST_BOOST BSP_BIT32(0) + uint32_t reserved_1b4 [5]; + uint32_t clkoutcfg; +#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL(val) BSP_FLD32(val, 3, 0) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_GET(reg) BSP_FLD32GET(reg, 3, 0) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 0) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV(val) BSP_FLD32(val, 7, 4) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_GET(reg) BSP_FLD32GET(reg, 7, 4) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_SET(reg, val) BSP_FLD32SET(reg, val, 7, 4) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32(8) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32(9) + uint32_t rstcon0; + uint32_t rstcon1; + uint32_t reserved_1d4 [2]; + uint32_t emcdlyctl; +#define LPC17XX_SCB_EMCDLYCTL_CMDDLY(val) BSP_FLD32(val, 0, 4) +#define LPC17XX_SCB_EMCDLYCTL_CMDDLY_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LPC17XX_SCB_EMCDLYCTL_CMDDLY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY(val) BSP_FLD32(val, 8, 12) +#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_GET(reg) BSP_FLD32GET(reg, 8, 12) +#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 12) +#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY(val) BSP_FLD32(val, 16, 20) +#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_GET(reg) BSP_FLD32GET(reg, 16, 20) +#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20) +#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY(val) BSP_FLD32(val, 24, 28) +#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_GET(reg) BSP_FLD32GET(reg, 24, 28) +#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_SET(reg, val) BSP_FLD32SET(reg, val, 24, 28) + uint32_t emccal; +#define LPC17XX_SCB_EMCCAL_CALVALUE(val) BSP_FLD32(val, 0, 7) +#define LPC17XX_SCB_EMCCAL_CALVALUE_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define LPC17XX_SCB_EMCCAL_CALVALUE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) +#define LPC17XX_SCB_EMCCAL_START BSP_BIT32(14) +#define LPC17XX_SCB_EMCCAL_DONE BSP_BIT32(15) +} lpc17xx_scb; + +#define LPC17XX_SCB (*(volatile lpc17xx_scb *) (LPC17XX_BASE + 0x400fc000)) + +typedef struct { + uint32_t reserved_00 [268435456]; + lpc17xx_wwdt wwdt; + uint32_t reserved_40000020 [258040]; + lpc17xx_scb scb; +} lpc17xx; + +#define LPC17XX (*(volatile lpc17xx *) (LPC17XX_BASE)) + +#endif /* LPC17XX_REGS_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/lpc24xx.h b/bsps/arm/lpc24xx/include/bsp/lpc24xx.h new file mode 100644 index 0000000000..64a910c041 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/lpc24xx.h @@ -0,0 +1,2206 @@ +/** + * @file + * + * @ingroup lpc24xx_regs + * + * @brief Register definitions. + */ + +/* + * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_LPC24XX_H +#define LIBBSP_ARM_LPC24XX_LPC24XX_H + +#include +#include +#include + +#ifdef ARM_MULTILIB_ARCH_V7M + #include +#endif + +/** + * @defgroup lpc24xx_regs Register Definitions + * + * @ingroup lpc24xx + * + * @brief Register definitions. + * + * @{ + */ + +#ifdef ARM_MULTILIB_ARCH_V4 + +/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 +#define VICIRQStatus (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x000)) +#define VICFIQStatus (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x004)) +#define VICRawIntr (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x008)) +#define VICIntSelect (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x00C)) +#define VICIntEnable (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x010)) +#define VICIntEnClear (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x014)) +#define VICSoftInt (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x018)) +#define VICSoftIntClear (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x01C)) +#define VICProtection (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x020)) +#define VICSWPrioMask (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x024)) + +#define VICVectAddrBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x100)) +#define VICVectAddr0 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x100)) +#define VICVectAddr1 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x104)) +#define VICVectAddr2 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x108)) +#define VICVectAddr3 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x10C)) +#define VICVectAddr4 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x110)) +#define VICVectAddr5 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x114)) +#define VICVectAddr6 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x118)) +#define VICVectAddr7 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x11C)) +#define VICVectAddr8 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x120)) +#define VICVectAddr9 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x124)) +#define VICVectAddr10 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x128)) +#define VICVectAddr11 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x12C)) +#define VICVectAddr12 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x130)) +#define VICVectAddr13 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x134)) +#define VICVectAddr14 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x138)) +#define VICVectAddr15 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x13C)) +#define VICVectAddr16 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x140)) +#define VICVectAddr17 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x144)) +#define VICVectAddr18 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x148)) +#define VICVectAddr19 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x14C)) +#define VICVectAddr20 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x150)) +#define VICVectAddr21 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x154)) +#define VICVectAddr22 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x158)) +#define VICVectAddr23 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x15C)) +#define VICVectAddr24 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x160)) +#define VICVectAddr25 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x164)) +#define VICVectAddr26 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x168)) +#define VICVectAddr27 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x16C)) +#define VICVectAddr28 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x170)) +#define VICVectAddr29 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x174)) +#define VICVectAddr30 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x178)) +#define VICVectAddr31 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x17C)) + +#define VICVectPriorityBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x200)) +#define VICVectPriority0 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x200)) +#define VICVectPriority1 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x204)) +#define VICVectPriority2 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x208)) +#define VICVectPriority3 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x20C)) +#define VICVectPriority4 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x210)) +#define VICVectPriority5 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x214)) +#define VICVectPriority6 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x218)) +#define VICVectPriority7 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x21C)) +#define VICVectPriority8 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x220)) +#define VICVectPriority9 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x224)) +#define VICVectPriority10 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x228)) +#define VICVectPriority11 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x22C)) +#define VICVectPriority12 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x230)) +#define VICVectPriority13 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x234)) +#define VICVectPriority14 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x238)) +#define VICVectPriority15 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x23C)) +#define VICVectPriority16 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x240)) +#define VICVectPriority17 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x244)) +#define VICVectPriority18 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x248)) +#define VICVectPriority19 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x24C)) +#define VICVectPriority20 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x250)) +#define VICVectPriority21 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x254)) +#define VICVectPriority22 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x258)) +#define VICVectPriority23 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x25C)) +#define VICVectPriority24 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x260)) +#define VICVectPriority25 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x264)) +#define VICVectPriority26 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x268)) +#define VICVectPriority27 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x26C)) +#define VICVectPriority28 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x270)) +#define VICVectPriority29 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x274)) +#define VICVectPriority30 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x278)) +#define VICVectPriority31 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x27C)) + +#define VICVectAddr (*(volatile uint32_t *) (VIC_BASE_ADDR + 0xF00)) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/* Pin Connect Block */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define PINSEL_BASE_ADDR 0xE002C000 +#else + #define PINSEL_BASE_ADDR 0x4002C000 +#endif + +#ifdef ARM_MULTILIB_ARCH_V4 + +#define PINSEL0 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x00)) +#define PINSEL1 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x04)) +#define PINSEL2 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x08)) +#define PINSEL3 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x0C)) +#define PINSEL4 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x10)) +#define PINSEL5 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x14)) +#define PINSEL6 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x18)) +#define PINSEL7 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x1C)) +#define PINSEL8 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x20)) +#define PINSEL9 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x24)) +#define PINSEL10 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x28)) +#define PINSEL11 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x2C)) + +#define PINMODE0 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x40)) +#define PINMODE1 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x44)) +#define PINMODE2 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x48)) +#define PINMODE3 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x4C)) +#define PINMODE4 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x50)) +#define PINMODE5 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x54)) +#define PINMODE6 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x58)) +#define PINMODE7 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x5C)) +#define PINMODE8 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x60)) +#define PINMODE9 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x64)) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/* General Purpose Input/Output (GPIO) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define GPIO_BASE_ADDR 0xE0028000 +#else + #define GPIO_BASE_ADDR 0x40028000 +#endif +#define IOPIN0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x00)) +#define IOSET0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x04)) +#define IODIR0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x08)) +#define IOCLR0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x0C)) +#define IOPIN1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x10)) +#define IOSET1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x14)) +#define IODIR1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x18)) +#define IOCLR1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x1C)) + +/* GPIO Interrupt Registers */ +#define IO0_INT_EN_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x94)) +#define IO0_INT_STAT_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x84)) +#define IO0_INT_STAT_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x88)) +#define IO0_INT_CLR (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x8C)) + +#define IO2_INT_EN_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB4)) +#define IO2_INT_STAT_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA4)) +#define IO2_INT_STAT_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA8)) +#define IO2_INT_CLR (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xAC)) + +#define IO_INT_STAT (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x80)) + +#ifdef ARM_MULTILIB_ARCH_V4 + +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG (*(volatile uint32_t *) (PARTCFG_BASE_ADDR + 0x00)) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/* Fast I/O setup */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define FIO_BASE_ADDR 0x3FFFC000 +#else + #define FIO_BASE_ADDR 0x20098000 +#endif +#define FIO0DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x00)) +#define FIO0MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x10)) +#define FIO0PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x14)) +#define FIO0SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x18)) +#define FIO0CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x1C)) + +#define FIO1DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x20)) +#define FIO1MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x30)) +#define FIO1PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x34)) +#define FIO1SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x38)) +#define FIO1CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x3C)) + +#define FIO2DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x40)) +#define FIO2MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x50)) +#define FIO2PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x54)) +#define FIO2SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x58)) +#define FIO2CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x5C)) + +#define FIO3DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x60)) +#define FIO3MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x70)) +#define FIO3PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x74)) +#define FIO3SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x78)) +#define FIO3CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x7C)) + +#define FIO4DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x80)) +#define FIO4MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x90)) +#define FIO4PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x94)) +#define FIO4SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x98)) +#define FIO4CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x9C)) + +#ifdef ARM_MULTILIB_ARCH_V7M + +#define FIO5DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xa0)) +#define FIO5MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb0)) +#define FIO5PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb4)) +#define FIO5SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb8)) +#define FIO5CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xbC)) + +#endif /* ARM_MULTILIB_ARCH_V7M */ + +/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ +#define FIO0DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x00)) +#define FIO1DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x20)) +#define FIO2DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x40)) +#define FIO3DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x60)) +#define FIO4DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x80)) + +#define FIO0DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x01)) +#define FIO1DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21)) +#define FIO2DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x41)) +#define FIO3DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x61)) +#define FIO4DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x81)) + +#define FIO0DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x02)) +#define FIO1DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x22)) +#define FIO2DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x42)) +#define FIO3DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x62)) +#define FIO4DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x82)) + +#define FIO0DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x03)) +#define FIO1DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x23)) +#define FIO2DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x43)) +#define FIO3DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x63)) +#define FIO4DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x83)) + +#define FIO0DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x80)) + +#define FIO0DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x82)) + +#define FIO0MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x90)) + +#define FIO0MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x91)) + +#define FIO0MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x92)) + +#define FIO0MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x93)) + +#define FIO0MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x90)) + +#define FIO0MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x92)) + +#define FIO0PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x94)) + +#define FIO0PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x25)) +#define FIO2PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x95)) + +#define FIO0PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x96)) + +#define FIO0PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x97)) + +#define FIO0PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x94)) + +#define FIO0PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x96)) + +#define FIO0SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x98)) + +#define FIO0SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x99)) + +#define FIO0SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9A)) + +#define FIO0SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9B)) + +#define FIO0SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x98)) + +#define FIO0SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9A)) + +#define FIO0CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9D)) + +#define FIO0CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9E)) + +#define FIO0CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9F)) + +#define FIO0CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9E)) + +#ifdef ARM_MULTILIB_ARCH_V4 + +/* System Control Block(SCB) modules include Memory Accelerator Module, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Reset, and Code Security/Debugging */ +#define SCB_BASE_ADDR 0xE01FC000 + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x000)) +#define MAMTIM (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x004)) +#define MEMMAP (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x040)) + +/* Phase Locked Loop (PLL) */ +#define PLLCON (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x080)) +#define PLLCFG (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x084)) +#define PLLSTAT (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x088)) +#define PLLFEED (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x08C)) + +/* Power Control */ +#define PCON (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C0)) +#define PCONP (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C4)) + +/* Clock Divider */ +// #define APBDIV (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x100)) +#define CCLKCFG (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x104)) +#define USBCLKCFG (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x108)) +#define CLKSRCSEL (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x10C)) +#define PCLKSEL0 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A8)) +#define PCLKSEL1 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1AC)) + +/* External Interrupts */ +#define EXTINT (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x140)) +#define INTWAKE (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x144)) +#define EXTMODE (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x148)) +#define EXTPOLAR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x14C)) + +/* Reset, reset source identification */ +#define RSIR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x180)) + +/* RSID, code security protection */ +#define CSPR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x184)) + +/* AHB configuration */ +#define AHBCFG1 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x188)) +#define AHBCFG2 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x18C)) + +/* System Controls and Status */ +#define SCS (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A0)) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/* External Memory Controller (EMC) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define EMC_BASE_ADDR 0xFFE08000 +#else + #define EMC_BASE_ADDR 0x2009c000 +#endif +#define EMC_CTRL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x000)) +#define EMC_STAT (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x004)) +#define EMC_CONFIG (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x008)) + +/* Dynamic RAM access registers */ +#define EMC_DYN_CTRL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x020)) +#define EMC_DYN_RFSH (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x024)) +#define EMC_DYN_RD_CFG (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x028)) +#define EMC_DYN_RP (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x030)) +#define EMC_DYN_RAS (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x034)) +#define EMC_DYN_SREX (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x038)) +#define EMC_DYN_APR (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x03C)) +#define EMC_DYN_DAL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x040)) +#define EMC_DYN_WR (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x044)) +#define EMC_DYN_RC (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x048)) +#define EMC_DYN_RFC (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x04C)) +#define EMC_DYN_XSR (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x050)) +#define EMC_DYN_RRD (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x054)) +#define EMC_DYN_MRD (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x058)) + +#define EMC_DYN_CFG0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x100)) +#define EMC_DYN_RASCAS0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x104)) +#define EMC_DYN_CFG1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x140)) +#define EMC_DYN_RASCAS1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x144)) +#define EMC_DYN_CFG2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x160)) +#define EMC_DYN_RASCAS2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x164)) +#define EMC_DYN_CFG3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x180)) +#define EMC_DYN_RASCAS3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x184)) + +/* static RAM access registers */ +#define EMC_STA_BASE_0 ((uint32_t *) (EMC_BASE_ADDR + 0x200)) +#define EMC_STA_CFG0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x200)) +#define EMC_STA_WAITWEN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x204)) +#define EMC_STA_WAITOEN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x208)) +#define EMC_STA_WAITRD0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x20C)) +#define EMC_STA_WAITPAGE0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x210)) +#define EMC_STA_WAITWR0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x214)) +#define EMC_STA_WAITTURN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x218)) + +#define EMC_STA_BASE_1 ((uint32_t *) (EMC_BASE_ADDR + 0x220)) +#define EMC_STA_CFG1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x220)) +#define EMC_STA_WAITWEN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x224)) +#define EMC_STA_WAITOEN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x228)) +#define EMC_STA_WAITRD1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x22C)) +#define EMC_STA_WAITPAGE1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x230)) +#define EMC_STA_WAITWR1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x234)) +#define EMC_STA_WAITTURN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x238)) + +#define EMC_STA_BASE_2 ((uint32_t *) (EMC_BASE_ADDR + 0x240)) +#define EMC_STA_CFG2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x240)) +#define EMC_STA_WAITWEN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x244)) +#define EMC_STA_WAITOEN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x248)) +#define EMC_STA_WAITRD2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x24C)) +#define EMC_STA_WAITPAGE2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x250)) +#define EMC_STA_WAITWR2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x254)) +#define EMC_STA_WAITTURN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x258)) + +#define EMC_STA_BASE_3 ((uint32_t *) (EMC_BASE_ADDR + 0x260)) +#define EMC_STA_CFG3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x260)) +#define EMC_STA_WAITWEN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x264)) +#define EMC_STA_WAITOEN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x268)) +#define EMC_STA_WAITRD3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x26C)) +#define EMC_STA_WAITPAGE3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x270)) +#define EMC_STA_WAITWR3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x274)) +#define EMC_STA_WAITTURN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x278)) + +#define EMC_STA_EXT_WAIT (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x880)) + + +/* Timer 0 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define TMR0_BASE_ADDR 0xE0004000 +#else + #define TMR0_BASE_ADDR 0x40004000 +#endif +#define T0IR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x00)) +#define T0TCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x04)) +#define T0TC (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x08)) +#define T0PR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x0C)) +#define T0PC (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x10)) +#define T0MCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x14)) +#define T0MR0 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x18)) +#define T0MR1 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x1C)) +#define T0MR2 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x20)) +#define T0MR3 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x24)) +#define T0CCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x28)) +#define T0CR0 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x2C)) +#define T0CR1 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x30)) +#define T0CR2 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x34)) +#define T0CR3 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x38)) +#define T0EMR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x3C)) +#define T0CTCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x70)) + +/* Timer 1 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define TMR1_BASE_ADDR 0xE0008000 +#else + #define TMR1_BASE_ADDR 0x40008000 +#endif +#define T1IR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x00)) +#define T1TCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x04)) +#define T1TC (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x08)) +#define T1PR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x0C)) +#define T1PC (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x10)) +#define T1MCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x14)) +#define T1MR0 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x18)) +#define T1MR1 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x1C)) +#define T1MR2 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x20)) +#define T1MR3 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x24)) +#define T1CCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x28)) +#define T1CR0 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x2C)) +#define T1CR1 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x30)) +#define T1CR2 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x34)) +#define T1CR3 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x38)) +#define T1EMR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x3C)) +#define T1CTCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x70)) + +/* Timer 2 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define TMR2_BASE_ADDR 0xE0070000 +#else + #define TMR2_BASE_ADDR 0x40090000 +#endif +#define T2IR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x00)) +#define T2TCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x04)) +#define T2TC (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x08)) +#define T2PR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x0C)) +#define T2PC (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x10)) +#define T2MCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x14)) +#define T2MR0 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x18)) +#define T2MR1 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x1C)) +#define T2MR2 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x20)) +#define T2MR3 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x24)) +#define T2CCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x28)) +#define T2CR0 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x2C)) +#define T2CR1 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x30)) +#define T2CR2 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x34)) +#define T2CR3 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x38)) +#define T2EMR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x3C)) +#define T2CTCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x70)) + +/* Timer 3 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define TMR3_BASE_ADDR 0xE0074000 +#else + #define TMR3_BASE_ADDR 0x40094000 +#endif +#define T3IR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x00)) +#define T3TCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x04)) +#define T3TC (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x08)) +#define T3PR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x0C)) +#define T3PC (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x10)) +#define T3MCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x14)) +#define T3MR0 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x18)) +#define T3MR1 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x1C)) +#define T3MR2 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x20)) +#define T3MR3 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x24)) +#define T3CCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x28)) +#define T3CR0 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x2C)) +#define T3CR1 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x30)) +#define T3CR2 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x34)) +#define T3CR3 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x38)) +#define T3EMR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x3C)) +#define T3CTCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x70)) + + +/* Pulse Width Modulator (PWM) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define PWM0_BASE_ADDR 0xE0014000 +#else + #define PWM0_BASE_ADDR 0x40014000 +#endif +#define PWM0IR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x00)) +#define PWM0TCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x04)) +#define PWM0TC (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x08)) +#define PWM0PR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x0C)) +#define PWM0PC (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x10)) +#define PWM0MCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x14)) +#define PWM0MR0 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x18)) +#define PWM0MR1 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x1C)) +#define PWM0MR2 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x20)) +#define PWM0MR3 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x24)) +#define PWM0CCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x28)) +#define PWM0CR0 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x2C)) +#define PWM0CR1 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x30)) +#define PWM0CR2 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x34)) +#define PWM0CR3 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x38)) +#define PWM0EMR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x3C)) +#define PWM0MR4 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x40)) +#define PWM0MR5 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x44)) +#define PWM0MR6 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x48)) +#define PWM0PCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x4C)) +#define PWM0LER (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x50)) +#define PWM0CTCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x70)) + +#ifdef ARM_MULTILIB_ARCH_V4 + #define PWM1_BASE_ADDR 0xE0018000 +#else + #define PWM1_BASE_ADDR 0x40018000 +#endif +#define PWM1IR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x00)) +#define PWM1TCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x04)) +#define PWM1TC (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x08)) +#define PWM1PR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x0C)) +#define PWM1PC (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x10)) +#define PWM1MCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x14)) +#define PWM1MR0 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x18)) +#define PWM1MR1 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x1C)) +#define PWM1MR2 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x20)) +#define PWM1MR3 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x24)) +#define PWM1CCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x28)) +#define PWM1CR0 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x2C)) +#define PWM1CR1 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x30)) +#define PWM1CR2 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x34)) +#define PWM1CR3 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x38)) +#define PWM1EMR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x3C)) +#define PWM1MR4 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x40)) +#define PWM1MR5 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x44)) +#define PWM1MR6 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x48)) +#define PWM1PCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x4C)) +#define PWM1LER (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x50)) +#define PWM1CTCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x70)) + + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define UART0_BASE_ADDR 0xE000C000 +#else + #define UART0_BASE_ADDR 0x4000C000 +#endif +#define U0RBR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00)) +#define U0THR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00)) +#define U0DLL (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00)) +#define U0DLM (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04)) +#define U0IER (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04)) +#define U0IIR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08)) +#define U0FCR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08)) +#define U0LCR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x0C)) +#define U0LSR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x14)) +#define U0SCR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x1C)) +#define U0ACR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x20)) +#define U0ICR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x24)) +#define U0FDR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x28)) +#define U0TER (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define UART1_BASE_ADDR 0xE0010000 +#else + #define UART1_BASE_ADDR 0x40010000 +#endif +#define U1RBR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00)) +#define U1THR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00)) +#define U1DLL (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00)) +#define U1DLM (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04)) +#define U1IER (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04)) +#define U1IIR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08)) +#define U1FCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08)) +#define U1LCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x0C)) +#define U1MCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x10)) +#define U1LSR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x14)) +#define U1MSR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x18)) +#define U1SCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x1C)) +#define U1ACR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x20)) +#define U1FDR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x28)) +#define U1TER (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define UART2_BASE_ADDR 0xE0078000 +#else + #define UART2_BASE_ADDR 0x40098000 +#endif +#define U2RBR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00)) +#define U2THR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00)) +#define U2DLL (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00)) +#define U2DLM (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04)) +#define U2IER (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04)) +#define U2IIR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08)) +#define U2FCR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08)) +#define U2LCR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x0C)) +#define U2LSR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x14)) +#define U2SCR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x1C)) +#define U2ACR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x20)) +#define U2ICR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x24)) +#define U2FDR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x28)) +#define U2TER (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define UART3_BASE_ADDR 0xE007C000 +#else + #define UART3_BASE_ADDR 0x4009C000 +#endif +#define U3RBR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00)) +#define U3THR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00)) +#define U3DLL (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00)) +#define U3DLM (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04)) +#define U3IER (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04)) +#define U3IIR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08)) +#define U3FCR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08)) +#define U3LCR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x0C)) +#define U3LSR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x14)) +#define U3SCR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x1C)) +#define U3ACR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x20)) +#define U3ICR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x24)) +#define U3FDR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x28)) +#define U3TER (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x30)) + +/* I2C Interface 0 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define I2C0_BASE_ADDR 0xE001C000 +#else + #define I2C0_BASE_ADDR 0x4001C000 +#endif +#define I20CONSET (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x00)) +#define I20STAT (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x04)) +#define I20DAT (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x08)) +#define I20ADR (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x0C)) +#define I20SCLH (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x10)) +#define I20SCLL (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x14)) +#define I20CONCLR (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x18)) + +/* I2C Interface 1 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define I2C1_BASE_ADDR 0xE005C000 +#else + #define I2C1_BASE_ADDR 0x4005C000 +#endif +#define I21CONSET (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x00)) +#define I21STAT (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x04)) +#define I21DAT (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x08)) +#define I21ADR (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x0C)) +#define I21SCLH (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x10)) +#define I21SCLL (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x14)) +#define I21CONCLR (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x18)) + +/* I2C Interface 2 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define I2C2_BASE_ADDR 0xE0080000 +#else + #define I2C2_BASE_ADDR 0x400a0000 +#endif +#define I22CONSET (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x00)) +#define I22STAT (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x04)) +#define I22DAT (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x08)) +#define I22ADR (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x0C)) +#define I22SCLH (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x10)) +#define I22SCLL (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x14)) +#define I22CONCLR (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x18)) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define SPI0_BASE_ADDR 0xE0020000 +#define S0SPCR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x00)) +#define S0SPSR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x04)) +#define S0SPDR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x08)) +#define S0SPCCR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x0C)) +#define S0SPINT (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x1C)) + +/* SSP0 Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define SSP0_BASE_ADDR 0xE0068000 +#else + #define SSP0_BASE_ADDR 0x40088000 +#endif +#define SSP0CR0 (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x00)) +#define SSP0CR1 (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x04)) +#define SSP0DR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x08)) +#define SSP0SR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x0C)) +#define SSP0CPSR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x10)) +#define SSP0IMSC (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x14)) +#define SSP0RIS (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x18)) +#define SSP0MIS (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x1C)) +#define SSP0ICR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x20)) +#define SSP0DMACR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x24)) + +/* SSP1 Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define SSP1_BASE_ADDR 0xE0030000 +#else + #define SSP1_BASE_ADDR 0x40030000 +#endif +#define SSP1CR0 (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x00)) +#define SSP1CR1 (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x04)) +#define SSP1DR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x08)) +#define SSP1SR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x0C)) +#define SSP1CPSR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x10)) +#define SSP1IMSC (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x14)) +#define SSP1RIS (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x18)) +#define SSP1MIS (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x1C)) +#define SSP1ICR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x20)) +#define SSP1DMACR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x24)) + +#ifdef ARM_MULTILIB_ARCH_V7M + +/* SSP2 Controller */ +#define SSP2_BASE_ADDR 0x400ac000 +#define SSP2CR0 (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x00)) +#define SSP2CR1 (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x04)) +#define SSP2DR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x08)) +#define SSP2SR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x0C)) +#define SSP2CPSR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x10)) +#define SSP2IMSC (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x14)) +#define SSP2RIS (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x18)) +#define SSP2MIS (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x1C)) +#define SSP2ICR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x20)) +#define SSP2DMACR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x24)) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/* Real Time Clock */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define RTC_BASE_ADDR 0xE0024000 +#else + #define RTC_BASE_ADDR 0x40024000 +#endif +#define RTC_ILR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x00)) +#define RTC_CTC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x04)) +#define RTC_CCR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x08)) +#define RTC_CIIR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x0C)) +#define RTC_AMR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x10)) +#define RTC_CTIME0 (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x14)) +#define RTC_CTIME1 (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x18)) +#define RTC_CTIME2 (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x1C)) +#define RTC_SEC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x20)) +#define RTC_MIN (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x24)) +#define RTC_HOUR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x28)) +#define RTC_DOM (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x2C)) +#define RTC_DOW (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x30)) +#define RTC_DOY (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x34)) +#define RTC_MONTH (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x38)) +#define RTC_YEAR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x3C)) +#define RTC_CISS (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x40)) +#define RTC_ALSEC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x60)) +#define RTC_ALMIN (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x64)) +#define RTC_ALHOUR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x68)) +#define RTC_ALDOM (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x6C)) +#define RTC_ALDOW (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x70)) +#define RTC_ALDOY (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x74)) +#define RTC_ALMON (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x78)) +#define RTC_ALYEAR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x7C)) +#define RTC_PREINT (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x80)) +#define RTC_PREFRAC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x84)) + + +/* A/D Converter 0 (AD0) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define AD0_BASE_ADDR 0xE0034000 +#else + #define AD0_BASE_ADDR 0x40034000 +#endif +#define AD0CR (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x00)) +#define AD0GDR (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x04)) +#define AD0INTEN (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x0C)) +#define AD0_DATA_START ((volatile uint32_t *) (AD0_BASE_ADDR + 0x10)) +#define AD0DR0 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x10)) +#define AD0DR1 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x14)) +#define AD0DR2 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x18)) +#define AD0DR3 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x1C)) +#define AD0DR4 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x20)) +#define AD0DR5 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x24)) +#define AD0DR6 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x28)) +#define AD0DR7 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x2C)) +#define AD0STAT (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x30)) + + +/* D/A Converter */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define DAC_BASE_ADDR 0xE006C000 +#else + #define DAC_BASE_ADDR 0x4008C000 +#endif +#define DACR (*(volatile uint32_t *) (DAC_BASE_ADDR + 0x00)) + + +/* Watchdog */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define WDG_BASE_ADDR 0xE0000000 +#else + #define WDG_BASE_ADDR 0x40000000 +#endif +#define WDMOD (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x00)) +#define WDTC (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x04)) +#define WDFEED (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x08)) +#define WDTV (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x0C)) +#define WDCLKSEL (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x10)) + +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#else + #define CAN_ACCEPT_BASE_ADDR 0x4003C000 +#endif +#define CAN_AFMR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_SFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x08)) +#define CAN_EFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x0C)) +#define CAN_EFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EOT (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x14)) +#define CAN_LUT_ERR_ADR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x1C)) + +#ifdef ARM_MULTILIB_ARCH_V4 + #define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#else + #define CAN_CENTRAL_BASE_ADDR 0x40040000 +#endif +#define CAN_TX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_MSR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x08)) + +#ifdef ARM_MULTILIB_ARCH_V4 + #define CAN1_BASE_ADDR 0xE0044000 +#else + #define CAN1_BASE_ADDR 0x40044000 +#endif +#define CAN1MOD (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x0C)) +#define CAN1IER (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x10)) +#define CAN1BTR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x20)) +#define CAN1RID (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x24)) +#define CAN1RDA (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x28)) +#define CAN1RDB (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x2C)) + +#define CAN1TFI1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x34)) +#define CAN1TDA1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x38)) +#define CAN1TDB1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x4C)) +#define CAN1TFI3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x58)) +#define CAN1TDB3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x5C)) + +#ifdef ARM_MULTILIB_ARCH_V4 + #define CAN2_BASE_ADDR 0xE0048000 +#else + #define CAN2_BASE_ADDR 0x40048000 +#endif +#define CAN2MOD (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x0C)) +#define CAN2IER (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x10)) +#define CAN2BTR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x20)) +#define CAN2RID (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x24)) +#define CAN2RDA (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x28)) +#define CAN2RDB (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x2C)) + +#define CAN2TFI1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x34)) +#define CAN2TDA1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x38)) +#define CAN2TDB1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x4C)) +#define CAN2TFI3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x58)) +#define CAN2TDB3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x5C)) + + +/* MultiMedia Card Interface(MCI) Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define MCI_BASE_ADDR 0xE008C000 +#else + #define MCI_BASE_ADDR 0x400c0000 +#endif +#define MCI_POWER (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x00)) +#define MCI_CLOCK (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x04)) +#define MCI_ARGUMENT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x08)) +#define MCI_COMMAND (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x0C)) +#define MCI_RESP_CMD (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x10)) +#define MCI_RESP0 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x14)) +#define MCI_RESP1 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x18)) +#define MCI_RESP2 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x1C)) +#define MCI_RESP3 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x20)) +#define MCI_DATA_TMR (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x24)) +#define MCI_DATA_LEN (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x28)) +#define MCI_DATA_CTRL (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x2C)) +#define MCI_DATA_CNT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x30)) +#define MCI_STATUS (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x34)) +#define MCI_CLEAR (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x38)) +#define MCI_MASK0 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x3C)) +#define MCI_MASK1 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x40)) +#define MCI_FIFO_CNT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x48)) +#define MCI_FIFO (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x80)) + + +/* I2S Interface Controller (I2S) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define I2S_BASE_ADDR 0xE0088000 +#else + #define I2S_BASE_ADDR 0x400a8000 +#endif +#define I2S_DAO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x00)) +#define I2S_DAI (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x04)) +#define I2S_TX_FIFO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x08)) +#define I2S_RX_FIFO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x0C)) +#define I2S_STATE (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x10)) +#define I2S_DMA1 (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x14)) +#define I2S_DMA2 (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x18)) +#define I2S_IRQ (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x1C)) +#define I2S_TXRATE (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x20)) +#define I2S_RXRATE (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x24)) + + +/* General-purpose DMA Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define DMA_BASE_ADDR 0xFFE04000 +#else + #define DMA_BASE_ADDR 0x20080000 +#endif +#define GPDMA_INT_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x000)) +#define GPDMA_INT_TCSTAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x004)) +#define GPDMA_INT_TCCLR (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x008)) +#define GPDMA_INT_ERR_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x00C)) +#define GPDMA_INT_ERR_CLR (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x010)) +#define GPDMA_RAW_INT_TCSTAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x014)) +#define GPDMA_RAW_INT_ERR_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x018)) +#define GPDMA_ENABLED_CHNS (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x01C)) +#define GPDMA_SOFT_BREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x020)) +#define GPDMA_SOFT_SREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x024)) +#define GPDMA_SOFT_LBREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x028)) +#define GPDMA_SOFT_LSREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x02C)) +#define GPDMA_CONFIG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x030)) +#define GPDMA_SYNC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x034)) + +/* DMA channel 0 registers */ +#define GPDMA_CH0_BASE_ADDR (DMA_BASE_ADDR + 0x100) +#define GPDMA_CH0_SRC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x100)) +#define GPDMA_CH0_DEST (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x104)) +#define GPDMA_CH0_LLI (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x108)) +#define GPDMA_CH0_CTRL (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x10C)) +#define GPDMA_CH0_CFG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x110)) + +/* DMA channel 1 registers */ +#define GPDMA_CH1_BASE_ADDR (DMA_BASE_ADDR + 0x120) +#define GPDMA_CH1_SRC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x120)) +#define GPDMA_CH1_DEST (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x124)) +#define GPDMA_CH1_LLI (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x128)) +#define GPDMA_CH1_CTRL (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x12C)) +#define GPDMA_CH1_CFG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x130)) + +/* USB Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define USB_INT_BASE_ADDR 0xE01FC1C0 + #define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ +#else + #define USB_INT_BASE_ADDR 0x400fc1c0 + #define USB_BASE_ADDR 0x2008c200 +#endif + +#define USB_INT_STAT (*(volatile uint32_t *) (USB_INT_BASE_ADDR + 0x00)) + +/* USB Device Interrupt Registers */ +#define DEV_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x00)) +#define DEV_INT_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x04)) +#define DEV_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0x08)) +#define DEV_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0x0C)) +#define DEV_INT_PRIO (*(volatile uint32_t *) (USB_BASE_ADDR + 0x2C)) + +/* USB Device Endpoint Interrupt Registers */ +#define EP_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x30)) +#define EP_INT_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x34)) +#define EP_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0x38)) +#define EP_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0x3C)) +#define EP_INT_PRIO (*(volatile uint32_t *) (USB_BASE_ADDR + 0x40)) + +/* USB Device Endpoint Realization Registers */ +#define REALIZE_EP (*(volatile uint32_t *) (USB_BASE_ADDR + 0x44)) +#define EP_INDEX (*(volatile uint32_t *) (USB_BASE_ADDR + 0x48)) +#define MAXPACKET_SIZE (*(volatile uint32_t *) (USB_BASE_ADDR + 0x4C)) + +/* USB Device Command Reagisters */ +#define CMD_CODE (*(volatile uint32_t *) (USB_BASE_ADDR + 0x10)) +#define CMD_DATA (*(volatile uint32_t *) (USB_BASE_ADDR + 0x14)) + +/* USB Device Data Transfer Registers */ +#define RX_DATA (*(volatile uint32_t *) (USB_BASE_ADDR + 0x18)) +#define TX_DATA (*(volatile uint32_t *) (USB_BASE_ADDR + 0x1C)) +#define RX_PLENGTH (*(volatile uint32_t *) (USB_BASE_ADDR + 0x20)) +#define TX_PLENGTH (*(volatile uint32_t *) (USB_BASE_ADDR + 0x24)) +#define USB_CTRL (*(volatile uint32_t *) (USB_BASE_ADDR + 0x28)) + +/* USB Device DMA Registers */ +#define DMA_REQ_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x50)) +#define DMA_REQ_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0x54)) +#define DMA_REQ_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0x58)) +#define UDCA_HEAD (*(volatile uint32_t *) (USB_BASE_ADDR + 0x80)) +#define EP_DMA_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x84)) +#define EP_DMA_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x88)) +#define EP_DMA_DIS (*(volatile uint32_t *) (USB_BASE_ADDR + 0x8C)) +#define DMA_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x90)) +#define DMA_INT_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x94)) +#define EOT_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA0)) +#define EOT_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA4)) +#define EOT_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA8)) +#define NDD_REQ_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0xAC)) +#define NDD_REQ_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB0)) +#define NDD_REQ_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB4)) +#define SYS_ERR_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB8)) +#define SYS_ERR_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xBC)) +#define SYS_ERR_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xC0)) + +/* USB Host Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define USBHC_BASE_ADDR 0xFFE0C000 +#else + #define USBHC_BASE_ADDR 0x2008c000 +#endif +#define HC_REVISION (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x00)) +#define HC_CONTROL (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x04)) +#define HC_CMD_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x08)) +#define HC_INT_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x0C)) +#define HC_INT_EN (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x10)) +#define HC_INT_DIS (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x14)) +#define HC_HCCA (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x18)) +#define HC_PERIOD_CUR_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x1C)) +#define HC_CTRL_HEAD_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x20)) +#define HC_CTRL_CUR_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x24)) +#define HC_BULK_HEAD_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x28)) +#define HC_BULK_CUR_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x2C)) +#define HC_DONE_HEAD (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x30)) +#define HC_FM_INTERVAL (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x34)) +#define HC_FM_REMAINING (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x38)) +#define HC_FM_NUMBER (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x3C)) +#define HC_PERIOD_START (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x40)) +#define HC_LS_THRHLD (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x44)) +#define HC_RH_DESCA (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x48)) +#define HC_RH_DESCB (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x4C)) +#define HC_RH_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x50)) +#define HC_RH_PORT_STAT1 (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x54)) +#define HC_RH_PORT_STAT2 (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x58)) + +/* USB OTG Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define USBOTG_BASE_ADDR 0xFFE0C100 +#else + #define USBOTG_BASE_ADDR 0x2008c100 +#endif +#define OTG_INT_STAT (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x00)) +#define OTG_INT_EN (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x04)) +#define OTG_INT_SET (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x08)) +#define OTG_INT_CLR (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x0C)) +#define OTG_STAT_CTRL (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x10)) +#define OTG_TIMER (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x14)) + +#ifdef ARM_MULTILIB_ARCH_V4 + #define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#else + #define USBOTG_I2C_BASE_ADDR 0x2008c300 +#endif +#define OTG_I2C_RX (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_TX (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_STS (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x04)) +#define OTG_I2C_CTL (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x08)) +#define OTG_I2C_CLKHI (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x0C)) +#define OTG_I2C_CLKLO (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x10)) + +#ifdef ARM_MULTILIB_ARCH_V4 + #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#else + #define USBOTG_CLK_BASE_ADDR 0x2008cff0 +#endif +#define OTG_CLK_CTRL (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x04)) +#define OTG_CLK_STAT (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x08)) + +/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#else + #define MAC_BASE_ADDR 0x20084000 +#endif +#define MAC_MAC1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ +#define MAC_MAC2 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ +#define MAC_IPGT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ +#define MAC_IPGR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ +#define MAC_CLRT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ +#define MAC_MAXF (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ +#define MAC_SUPP (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ +#define MAC_TEST (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x01C)) /* TEST reg */ +#define MAC_MCFG (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ +#define MAC_MCMD (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ +#define MAC_MADR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ +#define MAC_MWTD (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ +#define MAC_MRDD (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ +#define MAC_MIND (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ + +#define MAC_SA0 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ +#define MAC_SA1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ +#define MAC_SA2 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ + +#define MAC_COMMAND (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x100)) /* Command reg */ +#define MAC_STATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ +#define MAC_RXDESCRIPTOR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ +#define MAC_RXSTATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ +#define MAC_RXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ +#define MAC_RXPRODUCEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ +#define MAC_RXCONSUMEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ +#define MAC_TXDESCRIPTOR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ +#define MAC_TXSTATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ +#define MAC_TXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ +#define MAC_TXPRODUCEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ +#define MAC_TXCONSUMEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ + +#define MAC_TSV0 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ +#define MAC_TSV1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ +#define MAC_RSV (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ + +#define MAC_FLOWCONTROLCNT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ +#define MAC_FLOWCONTROLSTS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ + +#define MAC_RXFILTERCTRL (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ +#define MAC_RXFILTERWOLSTS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ +#define MAC_RXFILTERWOLCLR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ + +#define MAC_HASHFILTERL (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ +#define MAC_HASHFILTERH (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ + +#define MAC_INTSTATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ +#define MAC_INTENABLE (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ +#define MAC_INTCLEAR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ +#define MAC_INTSET (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ + +#define MAC_POWERDOWN (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ +#define MAC_MODULEID (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ + +/* LCD Controller */ + +#ifdef ARM_MULTILIB_ARCH_V4 + #define LCD_CFG (*(volatile uint32_t *) 0xE01FC1B8) + #define LCD_BASE_ADDR 0xFFE10000 +#else + #define LCD_CFG (*(volatile uint32_t *) 0x400FC1B8) + #define LCD_BASE_ADDR 0x20088000 +#endif +#define LCD_TIMH (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x000)) +#define LCD_TIMV (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x004)) +#define LCD_POL (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x008)) +#define LCD_LE (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x00C)) +#define LCD_UPBASE (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x010)) +#define LCD_LPBASE (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x014)) +#define LCD_CTRL (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x018)) +#define LCD_INTMSK (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x01C)) +#define LCD_INTRAW (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x020)) +#define LCD_INTSTAT (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x024)) +#define LCD_INTCLR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x028)) +#define LCD_UPCURR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x02C)) +#define LCD_LPCURR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x030)) +#define LCD_PAL_ADDR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x200)) +#define CRSR_IMG (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x800)) +#define CRSR_CTLR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC00)) +#define CRSR_CFG (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC04)) +#define CRSR_PAL0 (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC08)) +#define CRSR_PAL1 (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC0C)) +#define CRSR_XY (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC10)) +#define CRSR_CLIP (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC14)) +#define CRSR_INTMSK (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC20)) +#define CRSR_INTCLR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC24)) +#define CRSR_INTRAW (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC28)) +#define CRSR_INTSTAT (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC2C)) + +/* Register Fields */ + +#define GET_FIELD( val, mask, shift) \ + (((val) & (mask)) >> (shift)) + +#define SET_FIELD( val, field, mask, shift) \ + (((val) & ~(mask)) | (((field) << (shift)) & (mask))) + +/* CLKSRCSEL */ + +#define CLKSRCSEL_CLKSRC_MASK 0x00000003U + +#define GET_CLKSRCSEL_CLKSRC(reg) \ + GET_FIELD(reg, CLKSRCSEL_CLKSRC_MASK, 0) + +#define SET_CLKSRCSEL_CLKSRC(reg, val) \ + SET_FIELD(reg, val, CLKSRCSEL_CLKSRC_MASK, 0) + +/* PLLCON */ + +#define PLLCON_PLLE 0x00000001U + +#define PLLCON_PLLC 0x00000002U + +/* PLLCFG */ + +#define PLLCFG_MSEL_MASK 0x00007fffU + +#define GET_PLLCFG_MSEL(reg) \ + GET_FIELD(reg, PLLCFG_MSEL_MASK, 0) + +#define SET_PLLCFG_MSEL(reg, val) \ + SET_FIELD(reg, val, PLLCFG_MSEL_MASK, 0) + +#define PLLCFG_NSEL_MASK 0x00ff0000U + +#define GET_PLLCFG_NSEL(reg) \ + GET_FIELD(reg, PLLCFG_NSEL_MASK, 16) + +#define SET_PLLCFG_NSEL(reg, val) \ + SET_FIELD(reg, val, PLLCFG_NSEL_MASK, 16) + +/* PLLSTAT */ + +#define PLLSTAT_MSEL_MASK 0x00007fffU + +#define GET_PLLSTAT_MSEL(reg) \ + GET_FIELD(reg, PLLSTAT_MSEL_MASK, 0) + +#define SET_PLLSTAT_MSEL(reg, val) \ + SET_FIELD(reg, val, PLLSTAT_MSEL_MASK, 0) + +#define PLLSTAT_NSEL_MASK 0x00ff0000U + +#define GET_PLLSTAT_NSEL(reg) \ + GET_FIELD(reg, PLLSTAT_NSEL_MASK, 16) + +#define SET_PLLSTAT_NSEL(reg, val) \ + SET_FIELD(reg, val, PLLSTAT_NSEL_MASK, 16) + +#define PLLSTAT_PLLE 0x01000000U + +#define PLLSTAT_PLLC 0x02000000U + +#define PLLSTAT_PLOCK 0x04000000U + +/* CCLKCFG */ + +#define CCLKCFG_CCLKSEL_MASK 0x000000ffU + +#define GET_CCLKCFG_CCLKSEL(reg) \ + GET_FIELD(reg, CCLKCFG_CCLKSEL_MASK, 0) + +#define SET_CCLKCFG_CCLKSEL(reg, val) \ + SET_FIELD(reg, val, CCLKCFG_CCLKSEL_MASK, 0) + +/* MEMMAP */ + +#define MEMMAP_MAP_MASK 0x00000003U + +#define GET_MEMMAP_MAP(reg) \ + GET_FIELD(reg, MEMMAP_MAP_MASK, 0) + +#define SET_MEMMAP_MAP(reg, val) \ + SET_FIELD(reg, val, MEMMAP_MAP_MASK, 0) + +/* TIR */ + +#define TIR_MR0 0x00000001U + +#define TIR_MR1 0x00000002U + +#define TIR_MR2 0x00000004U + +#define TIR_MR3 0x00000008U + +#define TIR_CR0 0x00000010U + +#define TIR_CR1 0x00000020U + +#define TIR_CR2 0x00000040U + +#define TIR_CR3 0x00000080U + +/* TCR */ + +#define TCR_EN 0x00000001U + +#define TCR_RST 0x00000002U + +/* TMCR */ + +#define TMCR_MR0I 0x00000001U + +#define TMCR_MR0R 0x00000002U + +#define TMCR_MR0S 0x00000004U + +#define TMCR_MR1I 0x00000008U + +#define TMCR_MR1R 0x00000010U + +#define TMCR_MR1S 0x00000020U + +#define TMCR_MR2I 0x00000040U + +#define TMCR_MR2R 0x00000080U + +#define TMCR_MR2S 0x00000100U + +#define TMCR_MR3I 0x00000200U + +#define TMCR_MR3R 0x00000400U + +#define TMCR_MR3S 0x00000800U + +/* PCLKSEL0 */ + +#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U + +#define GET_PCLKSEL0_PCLK_WDT(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_WDT_MASK, 0) + +#define SET_PCLKSEL0_PCLK_WDT(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_WDT_MASK, 0) + +#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU + +#define GET_PCLKSEL0_PCLK_TIMER0(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_TIMER0_MASK, 2) + +#define SET_PCLKSEL0_PCLK_TIMER0(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2) + +#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U + +#define GET_PCLKSEL0_PCLK_TIMER1(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_TIMER1_MASK, 4) + +#define SET_PCLKSEL0_PCLK_TIMER1(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4) + +#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U + +#define GET_PCLKSEL0_PCLK_UART0(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_UART0_MASK, 6) + +#define SET_PCLKSEL0_PCLK_UART0(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_UART0_MASK, 6) + +#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U + +#define GET_PCLKSEL0_PCLK_UART1(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_UART1_MASK, 8) + +#define SET_PCLKSEL0_PCLK_UART1(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_UART1_MASK, 8) + +#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U + +#define GET_PCLKSEL0_PCLK_PWM0(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_PWM0_MASK, 10) + +#define SET_PCLKSEL0_PCLK_PWM0(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10) + +#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U + +#define GET_PCLKSEL0_PCLK_PWM1(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_PWM1_MASK, 12) + +#define SET_PCLKSEL0_PCLK_PWM1(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12) + +#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U + +#define GET_PCLKSEL0_PCLK_I2C0(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_I2C0_MASK, 14) + +#define SET_PCLKSEL0_PCLK_I2C0(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14) + +#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U + +#define GET_PCLKSEL0_PCLK_SPI(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_SPI_MASK, 16) + +#define SET_PCLKSEL0_PCLK_SPI(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_SPI_MASK, 16) + +#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U + +#define GET_PCLKSEL0_PCLK_RTC(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_RTC_MASK, 18) + +#define SET_PCLKSEL0_PCLK_RTC(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_RTC_MASK, 18) + +#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U + +#define GET_PCLKSEL0_PCLK_SSP1(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_SSP1_MASK, 20) + +#define SET_PCLKSEL0_PCLK_SSP1(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20) + +#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U + +#define GET_PCLKSEL0_PCLK_DAC(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_DAC_MASK, 22) + +#define SET_PCLKSEL0_PCLK_DAC(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_DAC_MASK, 22) + +#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U + +#define GET_PCLKSEL0_PCLK_ADC(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_ADC_MASK, 24) + +#define SET_PCLKSEL0_PCLK_ADC(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_ADC_MASK, 24) + +#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U + +#define GET_PCLKSEL0_PCLK_CAN1(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_CAN1_MASK, 26) + +#define SET_PCLKSEL0_PCLK_CAN1(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26) + +#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U + +#define GET_PCLKSEL0_PCLK_CAN2(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_CAN2_MASK, 28) + +#define SET_PCLKSEL0_PCLK_CAN2(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28) + +/* PCLKSEL1 */ + +#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U + +#define GET_PCLKSEL1_PCLK_BAT_RAM(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0) + +#define SET_PCLKSEL1_PCLK_BAT_RAM(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0) + +#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU + +#define GET_PCLKSEL1_PCLK_GPIO(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_GPIO_MASK, 2) + +#define SET_PCLKSEL1_PCLK_GPIO(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2) + +#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U + +#define GET_PCLKSEL1_PCLK_PCB(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_PCB_MASK, 4) + +#define SET_PCLKSEL1_PCLK_PCB(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_PCB_MASK, 4) + +#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U + +#define GET_PCLKSEL1_PCLK_I2C1(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_I2C1_MASK, 6) + +#define SET_PCLKSEL1_PCLK_I2C1(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6) + +#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U + +#define GET_PCLKSEL1_PCLK_SSP0(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_SSP0_MASK, 10) + +#define SET_PCLKSEL1_PCLK_SSP0(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10) + +#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U + +#define GET_PCLKSEL1_PCLK_TIMER2(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_TIMER2_MASK, 12) + +#define SET_PCLKSEL1_PCLK_TIMER2(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12) + +#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U + +#define GET_PCLKSEL1_PCLK_TIMER3(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_TIMER3_MASK, 14) + +#define SET_PCLKSEL1_PCLK_TIMER3(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14) + +#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U + +#define GET_PCLKSEL1_PCLK_UART2(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_UART2_MASK, 16) + +#define SET_PCLKSEL1_PCLK_UART2(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_UART2_MASK, 16) + +#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U + +#define GET_PCLKSEL1_PCLK_UART3(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_UART3_MASK, 18) + +#define SET_PCLKSEL1_PCLK_UART3(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_UART3_MASK, 18) + +#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U + +#define GET_PCLKSEL1_PCLK_I2C2(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_I2C2_MASK, 20) + +#define SET_PCLKSEL1_PCLK_I2C2(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20) + +#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U + +#define GET_PCLKSEL1_PCLK_I2S(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_I2S_MASK, 22) + +#define SET_PCLKSEL1_PCLK_I2S(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_I2S_MASK, 22) + +#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U + +#define GET_PCLKSEL1_PCLK_MCI(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_MCI_MASK, 24) + +#define SET_PCLKSEL1_PCLK_MCI(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_MCI_MASK, 24) + +#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U + +#define GET_PCLKSEL1_PCLK_SYSCON(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_SYSCON_MASK, 28) + +#define SET_PCLKSEL1_PCLK_SYSCON(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28) + +/* RTC_ILR */ + +#define RTC_ILR_RTCCIF 0x00000001U + +#define RTC_ILR_RTCALF 0x00000002U + +#define RTC_ILR_RTSSF 0x00000004U + +/* RTC_CCR */ + +#define RTC_CCR_CLKEN 0x00000001U + +#define RTC_CCR_CTCRST 0x00000002U + +#define RTC_CCR_CLKSRC 0x00000010U + +/* SSP */ + +typedef struct { + uint32_t cr0; + uint32_t cr1; + uint32_t dr; + uint32_t sr; + uint32_t cpsr; + uint32_t imsc; + uint32_t ris; + uint32_t mis; + uint32_t icr; + uint32_t dmacr; +} lpc24xx_ssp; + +/* SSP_CR0 */ + +#define SSP_CR0_DSS_MASK 0x0000000fU + +#define GET_SSP_CR0_DSS(reg) \ + GET_FIELD(reg, SSP_CR0_DSS_MASK, 0) + +#define SET_SSP_CR0_DSS(reg, val) \ + SET_FIELD(reg, val, SSP_CR0_DSS_MASK, 0) + +#define SSP_CR0_FRF_MASK 0x00000030U + +#define GET_SSP_CR0_FRF(reg) \ + GET_FIELD(reg, SSP_CR0_FRF_MASK, 4) + +#define SET_SSP_CR0_FRF(reg, val) \ + SET_FIELD(reg, val, SSP_CR0_FRF_MASK, 4) + +#define SSP_CR0_CPOL 0x00000040U + +#define SSP_CR0_CPHA 0x00000080U + +#define SSP_CR0_SCR_MASK 0x0000ff00U + +#define GET_SSP_CR0_SCR(reg) \ + GET_FIELD(reg, SSP_CR0_SCR_MASK, 8) + +#define SET_SSP_CR0_SCR(reg, val) \ + SET_FIELD(reg, val, SSP_CR0_SCR_MASK, 8) + +/* SSP_CR1 */ + +#define SSP_CR1_LBM 0x00000001U + +#define SSP_CR1_SSE 0x00000002U + +#define SSP_CR1_MS 0x00000004U + +#define SSP_CR1_SOD 0x00000008U + +/* SSP_SR */ + +#define SSP_SR_TFE 0x00000001U + +#define SSP_SR_TNF 0x00000002U + +#define SSP_SR_RNE 0x00000004U + +#define SSP_SR_RFF 0x00000008U + +#define SSP_SR_BSY 0x00000010U + +/* SSP_IMSC */ + +#define SSP_IMSC_RORIM 0x00000001U + +#define SSP_IMSC_RTIM 0x00000002U + +#define SSP_IMSC_RXIM 0x00000004U + +#define SSP_IMSC_TXIM 0x00000008U + +/* SSP_RIS */ + +#define SSP_RIS_RORRIS 0x00000001U + +#define SSP_RIS_RTRIS 0x00000002U + +#define SSP_RIS_RXRIS 0x00000004U + +#define SSP_RIS_TXRIS 0x00000008U + +/* SSP_MIS */ + +#define SSP_MIS_RORRIS 0x00000001U + +#define SSP_MIS_RTRIS 0x00000002U + +#define SSP_MIS_RXRIS 0x00000004U + +#define SSP_MIS_TXRIS 0x00000008U + +/* SSP_ICR */ + +#define SSP_ICR_RORRIS 0x00000001U + +#define SSP_ICR_RTRIS 0x00000002U + +#define SSP_ICR_RXRIS 0x00000004U + +#define SSP_ICR_TXRIS 0x00000008U + +/* SSP_DMACR */ + +#define SSP_DMACR_RXDMAE 0x00000001U + +#define SSP_DMACR_TXDMAE 0x00000002U + +/* GPDMA */ + +typedef struct { + uint32_t src; + uint32_t dest; + uint32_t lli; + uint32_t ctrl; +} lpc24xx_dma_descriptor; + +typedef struct { + lpc24xx_dma_descriptor desc; + uint32_t cfg; +} lpc24xx_dma_channel; + +#define GPDMA_CH_NUMBER 2 + +#define GPDMA_STATUS_CH_0 0x00000001U + +#define GPDMA_STATUS_CH_1 0x00000002U + +#define GPDMA_CH_BASE_ADDR(i) \ + ((volatile lpc24xx_dma_channel *) \ + ((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR)) + +/* GPDMA_CONFIG */ + +#define GPDMA_CONFIG_EN 0x00000001U + +#define GPDMA_CONFIG_MODE 0x00000002U + +/* GPDMA_ENABLED_CHNS */ + +#define GPDMA_ENABLED_CHNS_CH0 0x00000001U + +#define GPDMA_ENABLED_CHNS_CH1 0x00000002U + +/* GPDMA_CH_CTRL */ + +#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU + +#define GET_GPDMA_CH_CTRL_TSZ(reg) \ + GET_FIELD(reg, GPDMA_CH_CTRL_TSZ_MASK, 0) + +#define SET_GPDMA_CH_CTRL_TSZ(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0) + +#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU + +#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U + +#define GET_GPDMA_CH_CTRL_SBSZ(reg) \ + GET_FIELD(reg, GPDMA_CH_CTRL_SBSZ_MASK, 12) + +#define SET_GPDMA_CH_CTRL_SBSZ(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12) + +#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U + +#define GET_GPDMA_CH_CTRL_DBSZ(reg) \ + GET_FIELD(reg, GPDMA_CH_CTRL_DBSZ_MASK, 15) + +#define SET_GPDMA_CH_CTRL_DBSZ(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15) + +#define GPDMA_CH_CTRL_BSZ_1 0x00000000U + +#define GPDMA_CH_CTRL_BSZ_4 0x00000001U + +#define GPDMA_CH_CTRL_BSZ_8 0x00000002U + +#define GPDMA_CH_CTRL_BSZ_16 0x00000003U + +#define GPDMA_CH_CTRL_BSZ_32 0x00000004U + +#define GPDMA_CH_CTRL_BSZ_64 0x00000005U + +#define GPDMA_CH_CTRL_BSZ_128 0x00000006U + +#define GPDMA_CH_CTRL_BSZ_256 0x00000007U + +#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U + +#define GET_GPDMA_CH_CTRL_SW(reg) \ + GET_FIELD(reg, GPDMA_CH_CTRL_SW_MASK, 18) + +#define SET_GPDMA_CH_CTRL_SW(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CTRL_SW_MASK, 18) + +#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U + +#define GET_GPDMA_CH_CTRL_DW(reg) \ + GET_FIELD(reg, GPDMA_CH_CTRL_DW_MASK, 21) + +#define SET_GPDMA_CH_CTRL_DW(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CTRL_DW_MASK, 21) + +#define GPDMA_CH_CTRL_W_8 0x00000000U + +#define GPDMA_CH_CTRL_W_16 0x00000001U + +#define GPDMA_CH_CTRL_W_32 0x00000002U + +#define GPDMA_CH_CTRL_SI 0x04000000U + +#define GPDMA_CH_CTRL_DI 0x08000000U + +#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U + +#define GET_GPDMA_CH_CTRL_PROT(reg) \ + GET_FIELD(reg, GPDMA_CH_CTRL_PROT_MASK, 28) + +#define SET_GPDMA_CH_CTRL_PROT(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CTRL_PROT_MASK, 28) + +#define GPDMA_CH_CTRL_ITC 0x80000000U + +/* GPDMA_CH_CFG */ + +#define GPDMA_CH_CFG_EN 0x00000001U + +#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU + +#define GET_GPDMA_CH_CFG_SRCPER(reg) \ + GET_FIELD(reg, GPDMA_CH_CFG_SRCPER_MASK, 1) + +#define SET_GPDMA_CH_CFG_SRCPER(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1) + +#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U + +#define GET_GPDMA_CH_CFG_DESTPER(reg) \ + GET_FIELD(reg, GPDMA_CH_CFG_DESTPER_MASK, 6) + +#define SET_GPDMA_CH_CFG_DESTPER(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6) + +#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U + +#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U + +#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U + +#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U + +#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U + +#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U + +#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U + +#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U + +#define GET_GPDMA_CH_CFG_FLOW(reg) \ + GET_FIELD(reg, GPDMA_CH_CFG_FLOW_MASK, 11) + +#define SET_GPDMA_CH_CFG_FLOW(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CFG_FLOW_MASK, 11) + +#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U + +#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U + +#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U + +#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U + +#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U + +#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U + +#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U + +#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U + +#define GPDMA_CH_CFG_IE 0x00004000U + +#define GPDMA_CH_CFG_ITC 0x00008000U + +#define GPDMA_CH_CFG_LOCK 0x00010000U + +#define GPDMA_CH_CFG_ACTIVE 0x00020000U + +#define GPDMA_CH_CFG_HALT 0x00040000U + +/* AHBCFG */ + +#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U + +#define AHBCFG_BREAK_BURST_MASK 0x00000006U + +#define GET_AHBCFG_BREAK_BURST(reg) \ + GET_FIELD(reg, AHBCFG_BREAK_BURST_MASK, 1) + +#define SET_AHBCFG_BREAK_BURST(reg, val) \ + SET_FIELD(reg, val, AHBCFG_BREAK_BURST_MASK, 1) + +#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U + +#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U + +#define GET_AHBCFG_QUANTUM_SIZE(reg) \ + GET_FIELD(reg, AHBCFG_QUANTUM_SIZE_MASK, 4) + +#define SET_AHBCFG_QUANTUM_SIZE(reg, val) \ + SET_FIELD(reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4) + +#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U + +#define GET_AHBCFG_DEFAULT_MASTER(reg) \ + GET_FIELD(reg, AHBCFG_DEFAULT_MASTER_MASK, 8) + +#define SET_AHBCFG_DEFAULT_MASTER(reg, val) \ + SET_FIELD(reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8) + +#define AHBCFG_EP1_MASK 0x00007000U + +#define GET_AHBCFG_EP1(reg) \ + GET_FIELD(reg, AHBCFG_EP1_MASK, 12) + +#define SET_AHBCFG_EP1(reg, val) \ + SET_FIELD(reg, val, AHBCFG_EP1_MASK, 12) + +#define AHBCFG_EP2_MASK 0x00070000U + +#define GET_AHBCFG_EP2(reg) \ + GET_FIELD(reg, AHBCFG_EP2_MASK, 16) + +#define SET_AHBCFG_EP2(reg, val) \ + SET_FIELD(reg, val, AHBCFG_EP2_MASK, 16) + +#define AHBCFG_EP3_MASK 0x00700000U + +#define GET_AHBCFG_EP3(reg) \ + GET_FIELD(reg, AHBCFG_EP3_MASK, 20) + +#define SET_AHBCFG_EP3(reg, val) \ + SET_FIELD(reg, val, AHBCFG_EP3_MASK, 20) + +#define AHBCFG_EP4_MASK 0x07000000U + +#define GET_AHBCFG_EP4(reg) \ + GET_FIELD(reg, AHBCFG_EP4_MASK, 24) + +#define SET_AHBCFG_EP4(reg, val) \ + SET_FIELD(reg, val, AHBCFG_EP4_MASK, 24) + +#define AHBCFG_EP5_MASK 0x70000000U + +#define GET_AHBCFG_EP5(reg) \ + GET_FIELD(reg, AHBCFG_EP5_MASK, 28) + +#define SET_AHBCFG_EP5(reg, val) \ + SET_FIELD(reg, val, AHBCFG_EP5_MASK, 28) + +/* I2C */ + +typedef struct { + uint32_t conset; + uint32_t stat; + uint32_t dat; + uint32_t adr; + uint32_t sclh; + uint32_t scll; + uint32_t conclr; +} lpc24xx_i2c; + +#define LPC24XX_I2C_AA (1U << 2U) + +#define LPC24XX_I2C_SI (1U << 3U) + +#define LPC24XX_I2C_STO (1U << 4U) + +#define LPC24XX_I2C_STA (1U << 5U) + +#define LPC24XX_I2C_EN (1U << 6U) + +/* IO */ + +#ifdef ARM_MULTILIB_ARCH_V4 + #define LPC24XX_PINSEL ((volatile uint32_t *) &PINSEL0) + #define LPC24XX_PINMODE ((volatile uint32_t *) &PINMODE0) +#else + #define IOCON_FUNC(val) BSP_FLD32(val, 0, 2) + #define IOCON_FUNC_GET(reg) BSP_FLD32GET(reg, 0, 2) + #define IOCON_FUNC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + #define IOCON_MODE(val) BSP_FLD32(val, 3, 4) + #define IOCON_MODE_GET(reg) BSP_FLD32GET(reg, 3, 4) + #define IOCON_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 3, 4) + #define IOCON_HYS BSP_BIT32(5) + #define IOCON_INV BSP_BIT32(6) + #define IOCON_ADMODE BSP_BIT32(7) + #define IOCON_FILTER BSP_BIT32(8) + #define IOCON_HS BSP_BIT32(8) + #define IOCON_SLEW BSP_BIT32(9) + #define IOCON_HIDRIVE BSP_BIT32(9) + #define IOCON_OD BSP_BIT32(10) + #define IOCON_DACEN BSP_BIT32(16) + #define LPC17XX_IOCON ((volatile uint32_t *) PINSEL_BASE_ADDR) +#endif + +typedef struct { + uint32_t dir; + uint32_t reserved [3]; + uint32_t mask; + uint32_t pin; + uint32_t set; + uint32_t clr; +} lpc24xx_fio; + +#define LPC24XX_FIO ((volatile lpc24xx_fio *) FIO_BASE_ADDR) + +#ifdef ARM_MULTILIB_ARCH_V4 + +/* PCONP */ + +#define PCONP_GPDMA (1U << 29) +#define PCONP_ETHERNET (1U << 30) +#define PCONP_USB (1U << 31) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/* I2S */ + +static volatile lpc_i2s *const lpc24xx_i2s = (lpc_i2s *) I2S_BASE_ADDR; + +/* ADC */ + +#define ADC_CR_SEL(val) BSP_FLD32(val, 0, 7) +#define ADC_CR_SEL_GET(val) BSP_FLD32GET(val, 0, 7) +#define ADC_CR_SEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) +#define ADC_CR_CLKDIV(val) BSP_FLD32(val, 8, 15) +#define ADC_CR_CLKDIV_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define ADC_CR_CLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define ADC_CR_BURST BSP_BIT32(16) +#define ADC_CR_CLKS(val) BSP_FLD32(val, 17, 19) +#define ADC_CR_PDN BSP_BIT32(21) +#define ADC_CR_START(val) BSP_FLD32(val, 24, 26) +#define ADC_CR_EDGE BSP_BIT32(27) + +#define ADC_DR_VALUE(reg) BSP_FLD32GET(reg, 6, 15) +#define ADC_DR_OVERRUN BSP_BIT32(30) +#define ADC_DR_DONE BSP_BIT32(31) + +/* DAC */ + +#define DAC_STEPS 1024 +#define DAC_VALUE(val) BSP_FLD32(val, 6, 15) +#define DAC_BIAS BSP_BIT32(16) + +/** @} */ + +#endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/ssp.h b/bsps/arm/lpc24xx/include/bsp/ssp.h new file mode 100644 index 0000000000..1a77219d0e --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/ssp.h @@ -0,0 +1,47 @@ +/** + * @file + * + * @ingroup lpc24xx_libi2c + * + * @brief LibI2C bus driver for the Synchronous Serial Port (SSP). + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_SSP_H +#define LIBBSP_ARM_LPC24XX_SSP_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @ingroup lpc24xx_libi2c + * + * @{ + */ + +extern rtems_libi2c_bus_t * const lpc24xx_ssp_0; + +extern rtems_libi2c_bus_t * const lpc24xx_ssp_1; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_SSP_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/start-config.h b/bsps/arm/lpc24xx/include/bsp/start-config.h new file mode 100644 index 0000000000..4476cbdebe --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/start-config.h @@ -0,0 +1,121 @@ +/** + * @file + * + * @ingroup lpc24xx + * + * @brief BSP start configuration. + */ + +/* + * Copyright (c) 2011-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_START_CONFIG_H +#define LIBBSP_ARM_LPC24XX_START_CONFIG_H + +#include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Pico seconds @a ps to clock ticks for clock frequency @a f. + */ +#define LPC24XX_PS_TO_CLK(ps, f) \ + (((((uint64_t) (ps)) * ((uint64_t) (f))) + 1000000000000ULL - 1ULL) \ + / 1000000000000ULL) + +/** + * @brief Pico seconds @a ps to EMCCLK clock ticks adjusted by @a m. + */ +#define LPC24XX_PS_TO_EMCCLK(ps, m) \ + (LPC24XX_PS_TO_CLK(ps, LPC24XX_EMCCLK) > (m) ? \ + LPC24XX_PS_TO_CLK(ps, LPC24XX_EMCCLK) - (m) : 0) + +typedef struct { + uint32_t refresh; + uint32_t readconfig; + uint32_t trp; + uint32_t tras; + uint32_t tsrex; + uint32_t tapr; + uint32_t tdal; + uint32_t twr; + uint32_t trc; + uint32_t trfc; + uint32_t txsr; + uint32_t trrd; + uint32_t tmrd; + uint32_t emcdlyctl; +} lpc24xx_emc_dynamic_config; + +typedef struct { + volatile lpc_emc_dynamic *chip_select; + uint32_t address; + uint32_t config; + uint32_t rascas; + uint32_t mode; +} lpc24xx_emc_dynamic_chip_config; + +typedef struct { + volatile lpc_emc_static *chip_select; + struct { + uint32_t config; + uint32_t waitwen; + uint32_t waitoen; + uint32_t waitrd; + uint32_t waitpage; + uint32_t waitwr; + uint32_t waitrun; + } config; +} lpc24xx_emc_static_chip_config; + +extern BSP_START_DATA_SECTION const lpc24xx_pin_range + lpc24xx_start_config_pinsel []; + +extern BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config + lpc24xx_start_config_emc_dynamic []; + +extern BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config + lpc24xx_start_config_emc_dynamic_chip []; + +extern BSP_START_DATA_SECTION const size_t + lpc24xx_start_config_emc_dynamic_chip_count; + +extern BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config + lpc24xx_start_config_emc_static_chip []; + +extern BSP_START_DATA_SECTION const size_t + lpc24xx_start_config_emc_static_chip_count; + +#ifdef ARM_MULTILIB_ARCH_V7M + +extern BSP_START_DATA_SECTION const ARMV7M_MPU_Region + lpc24xx_start_config_mpu_region []; + +extern BSP_START_DATA_SECTION const size_t + lpc24xx_start_config_mpu_region_count; + +#endif /* ARM_MULTILIB_ARCH_V7M */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_START_CONFIG_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/system-clocks.h b/bsps/arm/lpc24xx/include/bsp/system-clocks.h new file mode 100644 index 0000000000..564d12ec10 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/system-clocks.h @@ -0,0 +1,89 @@ +/** + * @file + * + * @ingroup lpc24xx_clocks + * + * @brief System clocks. + */ + +/* + * Copyright (c) 2008, 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_SYSTEM_CLOCKS_H +#define LIBBSP_ARM_LPC24XX_SYSTEM_CLOCKS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc24xx_clock System Clocks + * + * @ingroup lpc24xx + * + * @brief System clocks. + * + * @{ + */ + +/** + * @brief Initializes the standard timer. + * + * This function uses Timer 1. + */ +void lpc24xx_timer_initialize(void); + +/** + * @brief Returns current standard timer value in CPU clocks. + * + * This function uses Timer 1. + */ +static inline unsigned lpc24xx_timer(void) +{ + return T1TC; +} + +/** + * @brief Delay for @a us micro seconds. + * + * This function uses the standard timer and assumes that the CPU frequency is + * in whole MHz numbers. The delay value @a us will be converted to CPU ticks + * and there is no protection against integer overflows. + * + * This function uses Timer 1. + */ +void lpc24xx_micro_seconds_delay(unsigned us); + +/** + * @brief Returns the PLL output clock frequency in [Hz]. + * + * Returns zero in case of an unexpected PLL input frequency. + */ +unsigned lpc24xx_pllclk(void); + +/** + * @brief Returns the CPU clock frequency in [Hz]. + * + * Returns zero in case of an unexpected PLL input frequency. + */ +unsigned lpc24xx_cclk(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_SYSTEM_CLOCKS_H */ diff --git a/bsps/arm/lpc24xx/include/tm27.h b/bsps/arm/lpc24xx/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/lpc24xx/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/lpc32xx/headers.am b/bsps/arm/lpc32xx/headers.am new file mode 100644 index 0000000000..40c0cfdb3d --- /dev/null +++ b/bsps/arm/lpc32xx/headers.am @@ -0,0 +1,19 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/boot.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/emc.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/hsu.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/lpc-clock-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/lpc-ethernet-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/lpc32xx.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/mmu.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/nand-mlc.h diff --git a/bsps/arm/lpc32xx/include/bsp.h b/bsps/arm/lpc32xx/include/bsp.h new file mode 100644 index 0000000000..0f9d1318cd --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp.h @@ -0,0 +1,259 @@ +/** + * @file + * + * @ingroup arm_lpc32xx + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_BSP_H +#define LIBBSP_ARM_LPC32XX_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct rtems_bsdnet_ifconfig; + +/** + * @defgroup arm_lpc32xx LPC32XX Support + * + * @ingroup bsp_arm + * + * @brief LPC32XX support package. + * + * @{ + */ + +/** + * @brief Network driver attach and detach function. + */ +int lpc_eth_attach_detach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +/** + * @brief Standard network driver attach and detach function. + */ +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach + +/** + * @brief Standard network driver name. + */ +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" + +/** + * @brief Optimized idle task. + * + * This idle task sets the power mode to idle. This causes the processor clock + * to be stopped, while on-chip peripherals remain active. Any enabled + * interrupt from a peripheral or an external interrupt source will cause the + * processor to resume execution. + * + * To enable the idle task use the following in the system configuration: + * + * @code + * #include + * + * #define CONFIGURE_INIT + * + * #define CONFIGURE_IDLE_TASK_BODY lpc32xx_idle + * + * #include + * @endcode + */ +void *lpc32xx_idle(uintptr_t ignored); + +#define LPC32XX_STANDARD_TIMER (&lpc32xx.timer_1) + +static inline unsigned lpc32xx_timer(void) +{ + volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER; + + return timer->tc; +} + +static inline void lpc32xx_micro_seconds_delay(unsigned us) +{ + unsigned start = lpc32xx_timer(); + unsigned delay = us * (LPC32XX_PERIPH_CLK / 1000000); + unsigned elapsed = 0; + + do { + elapsed = lpc32xx_timer() - start; + } while (elapsed < delay); +} + +#if LPC32XX_OSCILLATOR_MAIN == 13000000U + #define LPC32XX_HCLKPLL_CTRL_INIT_VALUE \ + (HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1)) + #define LPC32XX_HCLKDIV_CTRL_INIT_VALUE \ + (HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1) | HCLK_DIV_DDRAM_CLK(0)) +#else + #error "unexpected main oscillator frequency" +#endif + +bool lpc32xx_start_pll_setup( + uint32_t hclkpll_ctrl, + uint32_t hclkdiv_ctrl, + bool force +); + +uint32_t lpc32xx_sysclk(void); + +uint32_t lpc32xx_hclkpll_clk(void); + +uint32_t lpc32xx_periph_clk(void); + +uint32_t lpc32xx_hclk(void); + +uint32_t lpc32xx_arm_clk(void); + +uint32_t lpc32xx_ddram_clk(void); + +typedef enum { + LPC32XX_NAND_CONTROLLER_NONE, + LPC32XX_NAND_CONTROLLER_MLC, + LPC32XX_NAND_CONTROLLER_SLC +} lpc32xx_nand_controller; + +void lpc32xx_select_nand_controller(lpc32xx_nand_controller nand_controller); + +void bsp_restart(void *addr); + +void *bsp_idle_thread(uintptr_t arg); + +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +#define BSP_CONSOLE_UART_BASE LPC32XX_BASE_UART_5 + +/** + * @brief Begin of magic zero area. + * + * A read from this area returns zero. Writes have no effect. + */ +extern uint32_t lpc32xx_magic_zero_begin []; + +/** + * @brief End of magic zero area. + * + * A read from this area returns zero. Writes have no effect. + */ +extern uint32_t lpc32xx_magic_zero_end []; + +/** + * @brief Size of magic zero area. + * + * A read from this area returns zero. Writes have no effect. + */ +extern uint32_t lpc32xx_magic_zero_size []; + +#ifdef LPC32XX_SCRATCH_AREA_SIZE + /** + * @rief Scratch area. + * + * The usage is application specific. + */ + extern uint8_t lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE] + __attribute__((aligned(32))); +#endif + +#define LPC32XX_DO_STOP_GPDMA \ + do { \ + if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { \ + if ((lpc32xx.dma.cfg & DMA_CFG_E) != 0) { \ + int i = 0; \ + for (i = 0; i < 8; ++i) { \ + lpc32xx.dma.channels [i].cfg = 0; \ + } \ + lpc32xx.dma.cfg &= ~DMA_CFG_E; \ + } \ + LPC32XX_DMACLK_CTRL = 0; \ + } \ + } while (0) + +#define LPC32XX_DO_STOP_ETHERNET \ + do { \ + if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { \ + lpc32xx.eth.command = 0x38; \ + lpc32xx.eth.mac1 = 0xcf00; \ + lpc32xx.eth.mac1 = 0; \ + LPC32XX_MAC_CLK_CTRL = 0; \ + } \ + } while (0) + +#define LPC32XX_DO_STOP_USB \ + do { \ + if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { \ + LPC32XX_OTG_CLK_CTRL = 0; \ + LPC32XX_USB_CTRL = 0x80000; \ + } \ + } while (0) + +#define LPC32XX_DO_RESTART(addr) \ + do { \ + ARM_SWITCH_REGISTERS; \ + rtems_interrupt_level level; \ + uint32_t ctrl = 0; \ + \ + rtems_interrupt_disable(level); \ + \ + arm_cp15_data_cache_test_and_clean(); \ + arm_cp15_instruction_cache_invalidate(); \ + \ + ctrl = arm_cp15_get_control(); \ + ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); \ + arm_cp15_set_control(ctrl); \ + \ + __asm__ volatile ( \ + ARM_SWITCH_TO_ARM \ + "mov pc, %[addr]\n" \ + ARM_SWITCH_BACK \ + : ARM_SWITCH_OUTPUT \ + : [addr] "r" (addr) \ + ); \ + } while (0) + +/** @} */ + +/** + * @defgroup lpc LPC Support + * + * @ingroup arm_lpc32xx + * + * @brief LPC support package. + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_LPC32XX_BSP_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/boot.h b/bsps/arm/lpc32xx/include/bsp/boot.h new file mode 100644 index 0000000000..b9c845bc8f --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/boot.h @@ -0,0 +1,114 @@ +/** + * @file + * + * @ingroup lpc32xx_boot + * + * @brief Boot support API. + */ + +/* + * Copyright (c) 2010 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_BOOT_H +#define LIBBSP_ARM_LPC32XX_BOOT_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc32xx_boot Boot Support + * + * @ingroup arm_lpc32xx + * + * @brief Boot support. + * + * The NXP internal boot program shall be the "stage-0 program". + * + * The boot program within the first page of the first or second block shall be + * "stage-1 program". It will be invoked by the stage-0 program from NXP. + * + * The program loaded by the stage-1 program will be the "stage-2 program" or the + * "boot loader". + * + * The program loaded by the stage-2 program will be the "stage-3 program" or the + * "application". + * + * The stage-1 program image must have a format specified by NXP. + * + * The stage-2 and stage-3 program images may have any format. + * + * @{ + */ + +#define LPC32XX_BOOT_BLOCK_0 0 +#define LPC32XX_BOOT_BLOCK_1 1 + +#define LPC32XX_BOOT_ICR_SP_3AC_8IF 0xf0 +#define LPC32XX_BOOT_ICR_SP_4AC_8IF 0xd2 +#define LPC32XX_BOOT_ICR_LP_4AC_8IF 0xb4 +#define LPC32XX_BOOT_ICR_LP_5AC_8IF 0x96 + +typedef union { + struct { + uint8_t d0; + uint8_t reserved_0 [3]; + uint8_t d1; + uint8_t reserved_1 [3]; + uint8_t d2; + uint8_t reserved_2 [3]; + uint8_t d3; + uint8_t reserved_3 [3]; + uint8_t d4; + uint8_t reserved_4 [3]; + uint8_t d5; + uint8_t reserved_5 [3]; + uint8_t d6; + uint8_t reserved_6 [3]; + uint8_t d7; + uint8_t reserved_7 [3]; + uint8_t d8; + uint8_t reserved_8 [3]; + uint8_t d9; + uint8_t reserved_9 [3]; + uint8_t d10; + uint8_t reserved_10 [3]; + uint8_t d11; + uint8_t reserved_11 [3]; + uint8_t d12; + uint8_t reserved_12 [463]; + } field; + uint32_t data [MLC_SMALL_DATA_WORD_COUNT]; +} lpc32xx_boot_block; + +void lpc32xx_setup_boot_block( + lpc32xx_boot_block *boot_block, + uint8_t icr, + uint8_t page_count +); + +void lpc32xx_set_boot_block_bad( + lpc32xx_boot_block *boot_block +); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_BOOT_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/emc.h b/bsps/arm/lpc32xx/include/bsp/emc.h new file mode 100644 index 0000000000..c0ae18b395 --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/emc.h @@ -0,0 +1,161 @@ +/** + * @file + * + * @ingroup lpc32xx_emc + * + * @brief EMC support API. + */ + +/* + * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_EMC_H +#define LIBBSP_ARM_LPC32XX_EMC_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @addtogroup lpc_emc + * + * @brief EMC Support + * + * @{ + */ + +/** + * @name SDRAM Clock Control Register (SDRAMCLK_CTRL) + * + * @{ + */ + +#define SDRAMCLK_CLOCKS_DIS BSP_BIT32(0) +#define SDRAMCLK_DDR_MODE BSP_BIT32(1) +#define SDRAMCLK_DDR_DQSIN_DELAY(val) BSP_FLD32(val, 2, 6) +#define SDRAMCLK_RTC_TICK_EN BSP_BIT32(7) +#define SDRAMCLK_SW_DDR_CAL BSP_BIT32(8) +#define SDRAMCLK_CAL_DELAY BSP_BIT32(9) +#define SDRAMCLK_SENSITIVITY_FACTOR(val) BSP_FLD32(val, 10, 12) +#define SDRAMCLK_DCA_STATUS BSP_BIT32(13) +#define SDRAMCLK_COMMAND_DELAY(val) BSP_FLD32(val, 14, 18) +#define SDRAMCLK_SW_DDR_RESET BSP_BIT32(19) +#define SDRAMCLK_PIN_1_FAST BSP_BIT32(20) +#define SDRAMCLK_PIN_2_FAST BSP_BIT32(21) +#define SDRAMCLK_PIN_3_FAST BSP_BIT32(22) + +/** @} */ + +/** + * @name EMC AHB Control Register (EMCAHBControl) + * + * @{ + */ + +#define EMC_AHB_PORT_BUFF_EN BSP_BIT32(0) + +/** @} */ + +/** + * @name EMC AHB Timeout Register (EMCAHBTimeOut) + * + * @{ + */ + +#define EMC_AHB_TIMEOUT(val) BSP_FLD32(val, 0, 9) + +/** @} */ + +/** + * @name SDRAM Mode and Extended Mode Registers + * + * @{ + */ + +#define SDRAM_ADDR_ROW_16MB(val) ((uint32_t) (val) << 10) +#define SDRAM_ADDR_ROW_32MB(val) ((uint32_t) (val) << 11) +#define SDRAM_ADDR_ROW_64MB(val) ((uint32_t) (val) << 11) + +#define SDRAM_ADDR_BANK_16MB(ba1, ba0) \ + (((uint32_t) (ba1) << 23) | ((uint32_t) (ba0) << 22)) +#define SDRAM_ADDR_BANK_32MB(ba1, ba0) \ + (((uint32_t) (ba1) << 23) | ((uint32_t) (ba0) << 24)) +#define SDRAM_ADDR_BANK_64MB(ba1, ba0) \ + (((uint32_t) (ba1) << 25) | ((uint32_t) (ba0) << 24)) + +#define SDRAM_MODE_16MB(mode) \ + (SDRAM_ADDR_BANK_16MB(0, 0) | SDRAM_ADDR_ROW_16MB(mode)) +#define SDRAM_MODE_32MB(mode) \ + (SDRAM_ADDR_BANK_32MB(0, 0) | SDRAM_ADDR_ROW_32MB(mode)) +#define SDRAM_MODE_64MB(mode) \ + (SDRAM_ADDR_BANK_64MB(0, 0) | SDRAM_ADDR_ROW_64MB(mode)) + +#define SDRAM_EXTMODE_16MB(mode) \ + (SDRAM_ADDR_BANK_16MB(1, 0) | SDRAM_ADDR_ROW_16MB(mode)) +#define SDRAM_EXTMODE_32MB(mode) \ + (SDRAM_ADDR_BANK_32MB(1, 0) | SDRAM_ADDR_ROW_32MB(mode)) +#define SDRAM_EXTMODE_64MB(mode) \ + (SDRAM_ADDR_BANK_64MB(1, 0) | SDRAM_ADDR_ROW_64MB(mode)) + +#define SDRAM_MODE_BURST_LENGTH(val) BSP_FLD32(val, 0, 2) +#define SDRAM_MODE_BURST_INTERLEAVE BSP_BIT32(3) +#define SDRAM_MODE_CAS(val) BSP_FLD32(val, 4, 6) +#define SDRAM_MODE_TEST_MODE(val) BSP_FLD32(val, 7, 8) +#define SDRAM_MODE_WRITE_BURST_SINGLE_BIT BSP_BIT32(9) + +#define SDRAM_EXTMODE_PASR(val) BSP_FLD32(val, 0, 2) +#define SDRAM_EXTMODE_DRIVER_STRENGTH(val) BSP_FLD32(val, 5, 6) + +/** @} */ + +typedef struct { + uint32_t size; + uint32_t config; + uint32_t rascas; + uint32_t mode; + uint32_t extmode; +} lpc32xx_emc_dynamic_chip_config; + +typedef struct { + uint32_t sdramclk_ctrl; + uint32_t nop_time_in_us; + uint32_t control; + uint32_t refresh; + uint32_t readconfig; + uint32_t trp; + uint32_t tras; + uint32_t tsrex; + uint32_t twr; + uint32_t trc; + uint32_t trfc; + uint32_t txsr; + uint32_t trrd; + uint32_t tmrd; + uint32_t tcdlr; + lpc32xx_emc_dynamic_chip_config chip [EMC_DYN_CHIP_COUNT]; +} lpc32xx_emc_dynamic_config; + +void lpc32xx_emc_init(const lpc32xx_emc_dynamic_config *dyn_cfg); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_EMC_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/hsu.h b/bsps/arm/lpc32xx/include/bsp/hsu.h new file mode 100644 index 0000000000..ba97dfb423 --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/hsu.h @@ -0,0 +1,68 @@ +/** + * @file + * + * @ingroup lpc32xx_hsu + * + * @brief HSU support API. + */ + +/* + * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_HSU_H +#define LIBBSP_ARM_LPC32XX_HSU_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc32xx_hsu HSU Support + * + * @ingroup arm_lpc32xx + * + * @brief HSU Support + * + * @{ + */ + +typedef struct { + uint32_t fifo; + uint32_t level; + uint32_t iir; + uint32_t ctrl; + uint32_t rate; +} lpc32xx_hsu; + +typedef struct { + rtems_termios_device_context base; + volatile lpc32xx_hsu *hsu; + size_t chars_in_transmission; + rtems_vector_number irq; + uint32_t initial_baud; +} lpc32xx_hsu_context; + +extern const rtems_termios_device_handler lpc32xx_hsu_fns; + +bool lpc32xx_hsu_probe(rtems_termios_device_context *base); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_HSU_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/i2c.h b/bsps/arm/lpc32xx/include/bsp/i2c.h new file mode 100644 index 0000000000..e0bf8349ac --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/i2c.h @@ -0,0 +1,269 @@ +/** + * @file + * + * @ingroup lpc32xx_i2c + * + * @brief I2C support API. + */ + +/* + * Copyright (c) 2010 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_I2C_H +#define LIBBSP_ARM_LPC32XX_I2C_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc32xx_i2c I2C Support + * + * @ingroup arm_lpc32xx + * + * @brief I2C Support + * + * All writes and reads will be performed in master mode. Exclusive bus access + * will be assumed. + * + * @{ + */ + +/** + * @name I2C Clock Control Register (I2CCLK_CTRL) + * + * @{ + */ + +#define I2CCLK_1_EN BSP_BIT32(0) +#define I2CCLK_2_EN BSP_BIT32(1) +#define I2CCLK_1_HIGH_DRIVE BSP_BIT32(2) +#define I2CCLK_2_HIGH_DRIVE BSP_BIT32(3) +#define I2CCLK_USB_HIGH_DRIVE BSP_BIT32(4) + +/** @} */ + +/** + * @name I2C TX Data FIFO Register (I2Cn_TX) + * + * @{ + */ + +#define I2C_TX_READ BSP_BIT32(0) +#define I2C_TX_ADDR(val) BSP_FLD32(val, 1, 7) +#define I2C_TX_START BSP_BIT32(8) +#define I2C_TX_STOP BSP_BIT32(9) + +/** @} */ + +/** + * @name I2C Status Register (I2Cn_STAT) + * + * @{ + */ + +#define I2C_STAT_TDI BSP_BIT32(0) +#define I2C_STAT_AFI BSP_BIT32(1) +#define I2C_STAT_NAI BSP_BIT32(2) +#define I2C_STAT_DRMI BSP_BIT32(3) +#define I2C_STAT_DRSI BSP_BIT32(4) +#define I2C_STAT_ACTIVE BSP_BIT32(5) +#define I2C_STAT_SCL BSP_BIT32(6) +#define I2C_STAT_SDA BSP_BIT32(7) +#define I2C_STAT_RFF BSP_BIT32(8) +#define I2C_STAT_RFE BSP_BIT32(9) +#define I2C_STAT_TFF BSP_BIT32(10) +#define I2C_STAT_TFE BSP_BIT32(11) +#define I2C_STAT_TFFS BSP_BIT32(12) +#define I2C_STAT_TFES BSP_BIT32(13) + +/** @} */ + +/** + * @name I2C Control Register (I2Cn_CTRL) + * + * @{ + */ + +#define I2C_CTRL_TDIE BSP_BIT32(0) +#define I2C_CTRL_AFIE BSP_BIT32(1) +#define I2C_CTRL_NAIE BSP_BIT32(2) +#define I2C_CTRL_DRMIE BSP_BIT32(3) +#define I2C_CTRL_DRSIE BSP_BIT32(4) +#define I2C_CTRL_RFFIE BSP_BIT32(5) +#define I2C_CTRL_RFDAIE BSP_BIT32(6) +#define I2C_CTRL_TFFIO BSP_BIT32(7) +#define I2C_CTRL_RESET BSP_BIT32(8) +#define I2C_CTRL_SEVEN BSP_BIT32(9) +#define I2C_CTRL_TFFSIE BSP_BIT32(10) + +/** @} */ + +/** + * @brief Initializes the I2C module @a i2c. + * + * Valid @a clock_in_hz values are 100000 and 400000. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid @a i2c value. + * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value. + */ +rtems_status_code lpc32xx_i2c_init( + volatile lpc32xx_i2c *i2c, + unsigned clock_in_hz +); + +/** + * @brief Resets the I2C module @a i2c. + */ +void lpc32xx_i2c_reset(volatile lpc32xx_i2c *i2c); + +/** + * @brief Sets the I2C module @a i2c clock. + * + * Valid @a clock_in_hz values are 100000 and 400000. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value. + */ +rtems_status_code lpc32xx_i2c_clock( + volatile lpc32xx_i2c *i2c, + unsigned clock_in_hz +); + +/** + * @brief Starts a write transaction on the I2C module @a i2c. + * + * The address parameter @a addr must not contain the read/write bit. + * + * The error status may be delayed to the next + * lpc32xx_i2c_write_with_optional_stop() due to controller flaws. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + */ +rtems_status_code lpc32xx_i2c_write_start( + volatile lpc32xx_i2c *i2c, + unsigned addr +); + +/** + * @brief Writes data via the I2C module @a i2c with optional stop. + * + * The error status may be delayed to the next + * lpc32xx_i2c_write_with_optional_stop() due to controller flaws. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + */ +rtems_status_code lpc32xx_i2c_write_with_optional_stop( + volatile lpc32xx_i2c *i2c, + const uint8_t *out, + size_t n, + bool stop +); + +/** + * @brief Starts a read transaction on the I2C module @a i2c. + * + * The address parameter @a addr must not contain the read/write bit. + * + * The error status may be delayed to the next + * lpc32xx_i2c_read_with_optional_stop() due to controller flaws. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + */ +rtems_status_code lpc32xx_i2c_read_start( + volatile lpc32xx_i2c *i2c, + unsigned addr +); + +/** + * @brief Reads data via the I2C module @a i2c with optional stop. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + * @retval RTEMS_NOT_IMPLEMENTED Stop is @a false. + */ +rtems_status_code lpc32xx_i2c_read_with_optional_stop( + volatile lpc32xx_i2c *i2c, + uint8_t *in, + size_t n, + bool stop +); + +/** + * @brief Writes and reads data via the I2C module @a i2c. + * + * This will be one bus transaction. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + */ +rtems_status_code lpc32xx_i2c_write_and_read( + volatile lpc32xx_i2c *i2c, + unsigned addr, + const uint8_t *out, + size_t out_size, + uint8_t *in, + size_t in_size +); + +/** + * @brief Writes data via the I2C module @a i2c. + * + * This will be one bus transaction. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + */ +static inline rtems_status_code lpc32xx_i2c_write( + volatile lpc32xx_i2c *i2c, + unsigned addr, + const uint8_t *out, + size_t out_size +) +{ + return lpc32xx_i2c_write_and_read(i2c, addr, out, out_size, NULL, 0); +} + +/** + * @brief Reads data via the I2C module @a i2c. + * + * This will be one bus transaction. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + */ +static inline rtems_status_code lpc32xx_i2c_read( + volatile lpc32xx_i2c *i2c, + unsigned addr, + uint8_t *in, + size_t in_size +) +{ + return lpc32xx_i2c_write_and_read(i2c, addr, NULL, 0, in, in_size); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_I2C_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/irq.h b/bsps/arm/lpc32xx/include/bsp/irq.h new file mode 100644 index 0000000000..fbb13b5262 --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/irq.h @@ -0,0 +1,179 @@ +/** + * @file + * + * @ingroup lpc32xx_interrupt + * + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_IRQ_H +#define LIBBSP_ARM_LPC32XX_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc32xx_interrupt Interrupt Support + * + * @ingroup arm_lpc32xx + * + * @ingroup bsp_interrupt + * + * @{ + */ + +#define LPC32XX_IRQ_INDEX(module, subindex) ((module) + (subindex)) + +#define LPC32XX_IRQ_MODULE_MIC 0U +#define LPC32XX_IRQ_MODULE_SIC_1 32U +#define LPC32XX_IRQ_MODULE_SIC_2 64U +#define LPC32XX_IRQ_MODULE_COUNT 3U + +/* MIC interrupts */ +#define LPC32XX_IRQ_SIC_1_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 0) +#define LPC32XX_IRQ_SIC_2_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 1) +#define LPC32XX_IRQ_TIMER_4_OR_MCPWM LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 3) +#define LPC32XX_IRQ_TIMER_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 4) +#define LPC32XX_IRQ_TIMER_HS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 5) +#define LPC32XX_IRQ_WDG LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 6) +#define LPC32XX_IRQ_UART_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 7) +#define LPC32XX_IRQ_UART_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 8) +#define LPC32XX_IRQ_UART_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 9) +#define LPC32XX_IRQ_UART_6 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 10) +#define LPC32XX_IRQ_NAND_FLASH LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 11) +#define LPC32XX_IRQ_SDCARD_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 13) +#define LPC32XX_IRQ_LCD LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 14) +#define LPC32XX_IRQ_SDCARD_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 15) +#define LPC32XX_IRQ_TIMER_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 16) +#define LPC32XX_IRQ_TIMER_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 17) +#define LPC32XX_IRQ_TIMER_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 18) +#define LPC32XX_IRQ_TIMER_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 19) +#define LPC32XX_IRQ_SSP_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 20) +#define LPC32XX_IRQ_SSP_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 21) +#define LPC32XX_IRQ_I2S_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 22) +#define LPC32XX_IRQ_I2S_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 23) +#define LPC32XX_IRQ_UART_7 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 24) +#define LPC32XX_IRQ_UART_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 25) +#define LPC32XX_IRQ_UART_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 26) +#define LPC32XX_IRQ_TIMER_MS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 27) +#define LPC32XX_IRQ_DMA LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 28) +#define LPC32XX_IRQ_ETHERNET LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 29) +#define LPC32XX_IRQ_SIC_1_FIQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 30) +#define LPC32XX_IRQ_SIC_2_FIQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 31) + +/* SIC 1 interrupts */ +#define LPC32XX_IRQ_JTAG_COMM_TX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 1) +#define LPC32XX_IRQ_JTAG_COMM_RX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 2) +#define LPC32XX_IRQ_GPI_28 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 4) +#define LPC32XX_IRQ_TS_P LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 6) +#define LPC32XX_IRQ_TS_IRQ_OR_ADC LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 7) +#define LPC32XX_IRQ_TS_AUX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 8) +#define LPC32XX_IRQ_SPI_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 12) +#define LPC32XX_IRQ_PLL_USB LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 13) +#define LPC32XX_IRQ_PLL_HCLK LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 14) +#define LPC32XX_IRQ_PLL_397 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 17) +#define LPC32XX_IRQ_I2C_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 18) +#define LPC32XX_IRQ_I2C_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 19) +#define LPC32XX_IRQ_RTC LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 20) +#define LPC32XX_IRQ_KEYSCAN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 22) +#define LPC32XX_IRQ_SPI_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 23) +#define LPC32XX_IRQ_SW LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 24) +#define LPC32XX_IRQ_USB_OTG_TIMER LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 25) +#define LPC32XX_IRQ_USB_OTG_ATX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 26) +#define LPC32XX_IRQ_USB_HOST LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 27) +#define LPC32XX_IRQ_USB_DEV_DMA LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 28) +#define LPC32XX_IRQ_USB_DEV_LP LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 29) +#define LPC32XX_IRQ_USB_DEV_HP LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 30) +#define LPC32XX_IRQ_USB_I2C LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 31) + +/* SIC 2 interrupts */ +#define LPC32XX_IRQ_GPIO_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 0) +#define LPC32XX_IRQ_GPIO_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 1) +#define LPC32XX_IRQ_GPIO_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 2) +#define LPC32XX_IRQ_GPIO_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 3) +#define LPC32XX_IRQ_GPIO_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 4) +#define LPC32XX_IRQ_GPIO_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 5) +#define LPC32XX_IRQ_SPI_2_DATAIN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 6) +#define LPC32XX_IRQ_UART_2_HCTS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 7) +#define LPC32XX_IRQ_GPIO_P0_P1_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 8) +#define LPC32XX_IRQ_GPI_8 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 9) +#define LPC32XX_IRQ_GPI_9 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 10) +#define LPC32XX_IRQ_GPI_19 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 11) +#define LPC32XX_IRQ_UART_7_HCTS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 12) +#define LPC32XX_IRQ_GPI_7 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 15) +#define LPC32XX_IRQ_SDIO LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 18) +#define LPC32XX_IRQ_UART_5_RX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 19) +#define LPC32XX_IRQ_SPI_1_DATAIN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 20) +#define LPC32XX_IRQ_GPI_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 22) +#define LPC32XX_IRQ_GPI_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 23) +#define LPC32XX_IRQ_GPI_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 24) +#define LPC32XX_IRQ_GPI_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 25) +#define LPC32XX_IRQ_GPI_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 26) +#define LPC32XX_IRQ_GPI_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 27) +#define LPC32XX_IRQ_GPI_6 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 28) +#define LPC32XX_IRQ_SYSCLK LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 31) + +#define LPC32XX_IRQ_PRIORITY_VALUE_MIN 0U +#define LPC32XX_IRQ_PRIORITY_VALUE_MAX 15U +#define LPC32XX_IRQ_PRIORITY_COUNT (LPC32XX_IRQ_PRIORITY_VALUE_MAX + 1U) +#define LPC32XX_IRQ_PRIORITY_HIGHEST LPC32XX_IRQ_PRIORITY_VALUE_MIN +#define LPC32XX_IRQ_PRIORITY_LOWEST LPC32XX_IRQ_PRIORITY_VALUE_MAX + +#define BSP_INTERRUPT_VECTOR_MIN LPC32XX_IRQ_SIC_1_IRQ +#define BSP_INTERRUPT_VECTOR_MAX LPC32XX_IRQ_SYSCLK + +#define LPC32XX_IRQ_COUNT (BSP_INTERRUPT_VECTOR_MAX + 1) + +void lpc32xx_irq_set_priority(rtems_vector_number vector, unsigned priority); + +unsigned lpc32xx_irq_get_priority(rtems_vector_number vector); + +typedef enum { + LPC32XX_IRQ_ACTIVE_LOW_OR_FALLING_EDGE, + LPC32XX_IRQ_ACTIVE_HIGH_OR_RISING_EDGE +} lpc32xx_irq_activation_polarity; + +void lpc32xx_irq_set_activation_polarity(rtems_vector_number vector, lpc32xx_irq_activation_polarity activation_polarity); + +lpc32xx_irq_activation_polarity lpc32xx_irq_get_activation_polarity(rtems_vector_number vector); + +typedef enum { + LPC32XX_IRQ_LEVEL_SENSITIVE, + LPC32XX_IRQ_EDGE_SENSITIVE +} lpc32xx_irq_activation_type; + +void lpc32xx_irq_set_activation_type(rtems_vector_number vector, lpc32xx_irq_activation_type activation_type); + +lpc32xx_irq_activation_type lpc32xx_irq_get_activation_type(rtems_vector_number vector); + +void lpc32xx_set_exception_handler(Arm_symbolic_exception_name exception, void (*handler)(void)); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_LPC32XX_IRQ_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/lpc-clock-config.h b/bsps/arm/lpc32xx/include/bsp/lpc-clock-config.h new file mode 100644 index 0000000000..2b676b433f --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/lpc-clock-config.h @@ -0,0 +1,59 @@ +/** + * @file + * + * @ingroup lpc_clock + * + * @brief Clock driver configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H +#define LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc_clock Clock Support + * + * @ingroup lpc + * + * @brief Clock support. + * + * @{ + */ + +#define LPC_CLOCK_INTERRUPT LPC32XX_IRQ_TIMER_0 + +#define LPC_CLOCK_TIMER_BASE LPC32XX_BASE_TIMER_0 + +#define LPC_CLOCK_TIMECOUNTER_BASE LPC32XX_BASE_TIMER_1 + +#define LPC_CLOCK_REFERENCE LPC32XX_PERIPH_CLK + +#define LPC_CLOCK_MODULE_ENABLE() + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/lpc-ethernet-config.h b/bsps/arm/lpc32xx/include/bsp/lpc-ethernet-config.h new file mode 100644 index 0000000000..53e9e8415d --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/lpc-ethernet-config.h @@ -0,0 +1,98 @@ +/** + * @file + * + * @ingroup lpc_eth + * + * @brief Ethernet driver configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_LPC_ETHERNET_CONFIG_H +#define LIBBSP_ARM_LPC32XX_LPC_ETHERNET_CONFIG_H + +#include +#include + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc_eth Ethernet Support + * + * @ingroup lpc + * + * @brief Ethernet support. + * + * @{ + */ + +#define LPC_ETH_CONFIG_INTERRUPT LPC32XX_IRQ_ETHERNET + +#define LPC_ETH_CONFIG_REG_BASE LPC32XX_BASE_ETHERNET + +#define LPC_ETH_CONFIG_RX_UNIT_COUNT_DEFAULT 16 +#define LPC_ETH_CONFIG_RX_UNIT_COUNT_MAX INT_MAX + +#define LPC_ETH_CONFIG_TX_UNIT_COUNT_DEFAULT 32 +#define LPC_ETH_CONFIG_TX_UNIT_COUNT_MAX INT_MAX + +#define LPC_ETH_CONFIG_UNIT_MULTIPLE 8U + +#ifdef LPC32XX_ETHERNET_RMII + #define LPC_ETH_CONFIG_RMII + + static void lpc_eth_config_module_enable(void) + { + LPC32XX_MAC_CLK_CTRL = 0x1f; + } +#else + static void lpc_eth_config_module_enable(void) + { + LPC32XX_MAC_CLK_CTRL = 0x0f; + } +#endif + +static void lpc_eth_config_module_disable(void) +{ + LPC32XX_MAC_CLK_CTRL = 0; +} + +#define LPC_ETH_CONFIG_USE_TRANSMIT_DMA + +static char *lpc_eth_config_alloc_table_area(size_t size) +{ + return rtems_heap_allocate_aligned_with_boundary(size, 32, 0); +} + +static void lpc_eth_config_free_table_area(char *table_area) +{ + /* FIXME: Type */ + free(table_area, (int) 0xdeadbeef); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_LPC_ETHERNET_CONFIG_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/lpc32xx.h b/bsps/arm/lpc32xx/include/bsp/lpc32xx.h new file mode 100644 index 0000000000..2edb1e334e --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/lpc32xx.h @@ -0,0 +1,641 @@ +/** + * @file + * + * @ingroup lpc32xx_reg + * + * @brief Register base addresses. + */ + +/* + * Copyright (c) 2009, 2010 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http: + */ + +#ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H +#define LIBBSP_ARM_LPC32XX_LPC32XX_H + +#include + +#include +#include +#include +#include +#include + +/** + * @defgroup lpc32xx_reg Register Definitions + * + * @ingroup arm_lpc32xx + * + * @brief Register definitions. + * + * @{ + */ + +/** + * @name Register Base Addresses + * + * @{ + */ + +#define LPC32XX_BASE_ADC 0x40048000 +#define LPC32XX_BASE_SYSCON 0x40004000 +#define LPC32XX_BASE_DEBUG_CTRL 0x40040000 +#define LPC32XX_BASE_DMA 0x31000000 +#define LPC32XX_BASE_EMC 0x31080000 +#define LPC32XX_BASE_EMC_CS_0 0xe0000000 +#define LPC32XX_BASE_EMC_CS_1 0xe1000000 +#define LPC32XX_BASE_EMC_CS_2 0xe2000000 +#define LPC32XX_BASE_EMC_CS_3 0xe3000000 +#define LPC32XX_BASE_EMC_DYCS_0 0x80000000 +#define LPC32XX_BASE_EMC_DYCS_1 0xa0000000 +#define LPC32XX_BASE_ETB_CFG 0x310c0000 +#define LPC32XX_BASE_ETB_DATA 0x310e0000 +#define LPC32XX_BASE_ETHERNET 0x31060000 +#define LPC32XX_BASE_GPIO 0x40028000 +#define LPC32XX_BASE_I2C_1 0x400a0000 +#define LPC32XX_BASE_I2C_2 0x400a8000 +#define LPC32XX_BASE_I2S_0 0x20094000 +#define LPC32XX_BASE_I2S_1 0x2009c000 +#define LPC32XX_BASE_IRAM 0x08000000 +#define LPC32XX_BASE_IROM 0x0c000000 +#define LPC32XX_BASE_KEYSCAN 0x40050000 +#define LPC32XX_BASE_LCD 0x31040000 +#define LPC32XX_BASE_MCPWM 0x400e8000 +#define LPC32XX_BASE_MIC 0x40008000 +#define LPC32XX_BASE_NAND_MLC 0x200a8000 +#define LPC32XX_BASE_NAND_SLC 0x20020000 +#define LPC32XX_BASE_PWM_1 0x4005c000 +#define LPC32XX_BASE_PWM_2 0x4005c004 +#define LPC32XX_BASE_PWM_3 0x4002c000 +#define LPC32XX_BASE_PWM_4 0x40030000 +#define LPC32XX_BASE_RTC 0x40024000 +#define LPC32XX_BASE_RTC_RAM 0x40024080 +#define LPC32XX_BASE_SDCARD 0x20098000 +#define LPC32XX_BASE_SIC_1 0x4000c000 +#define LPC32XX_BASE_SIC_2 0x40010000 +#define LPC32XX_BASE_SPI_1 0x20088000 +#define LPC32XX_BASE_SPI_2 0x20090000 +#define LPC32XX_BASE_SSP_0 0x20084000 +#define LPC32XX_BASE_SSP_1 0x2008c000 +#define LPC32XX_BASE_TIMER_0 0x40044000 +#define LPC32XX_BASE_TIMER_1 0x4004c000 +#define LPC32XX_BASE_TIMER_2 0x40058000 +#define LPC32XX_BASE_TIMER_3 0x40060000 +#define LPC32XX_BASE_TIMER_5 0x4002c000 +#define LPC32XX_BASE_TIMER_6 0x40030000 +#define LPC32XX_BASE_TIMER_HS 0x40038000 +#define LPC32XX_BASE_TIMER_MS 0x40034000 +#define LPC32XX_BASE_UART_1 0x40014000 +#define LPC32XX_BASE_UART_2 0x40018000 +#define LPC32XX_BASE_UART_3 0x40080000 +#define LPC32XX_BASE_UART_4 0x40088000 +#define LPC32XX_BASE_UART_5 0x40090000 +#define LPC32XX_BASE_UART_6 0x40098000 +#define LPC32XX_BASE_UART_7 0x4001c000 +#define LPC32XX_BASE_USB 0x31020000 +#define LPC32XX_BASE_USB_OTG_I2C 0x31020300 +#define LPC32XX_BASE_WDT 0x4003c000 + +/** @} */ + +/** + * @name Miscanellanous Registers + * + * @{ + */ + +#define LPC32XX_U3CLK (*(volatile uint32_t *) 0x400040d0) +#define LPC32XX_U4CLK (*(volatile uint32_t *) 0x400040d4) +#define LPC32XX_U5CLK (*(volatile uint32_t *) 0x400040d8) +#define LPC32XX_U6CLK (*(volatile uint32_t *) 0x400040dc) +#define LPC32XX_IRDACLK (*(volatile uint32_t *) 0x400040e0) +#define LPC32XX_UART_CTRL (*(volatile uint32_t *) 0x40054000) +#define LPC32XX_UART_CLKMODE (*(volatile uint32_t *) 0x40054004) +#define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008) +#define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8) +#define LPC32XX_MAC_CLK_CTRL (*(volatile uint32_t *) 0x40004090) +#define LPC32XX_USB_DIV (*(volatile uint32_t *) 0x4000401c) +#define LPC32XX_OTG_CLK_CTRL (*(volatile uint32_t *) 0x31020ff4) +#define LPC32XX_OTG_CLK_STAT (*(volatile uint32_t *) 0x31020ff8) +#define LPC32XX_OTG_STAT_CTRL (*(volatile uint32_t *) 0x31020110) +#define LPC32XX_I2C_RX (*(volatile uint32_t *) 0x31020300) +#define LPC32XX_I2C_TX (*(volatile uint32_t *) 0x31020300) +#define LPC32XX_I2C_STS (*(volatile uint32_t *) 0x31020304) +#define LPC32XX_I2C_CTL (*(volatile uint32_t *) 0x31020308) +#define LPC32XX_I2C_CLKHI (*(volatile uint32_t *) 0x3102030c) +#define LPC32XX_I2C_CLKLO (*(volatile uint32_t *) 0x31020310) +#define LPC32XX_PWR_CTRL (*(volatile uint32_t *) 0x40004044) +#define LPC32XX_OSC_CTRL (*(volatile uint32_t *) 0x4000404c) +#define LPC32XX_SYSCLK_CTRL (*(volatile uint32_t *) 0x40004050) +#define LPC32XX_PLL397_CTRL (*(volatile uint32_t *) 0x40004048) +#define LPC32XX_HCLKPLL_CTRL (*(volatile uint32_t *) 0x40004058) +#define LPC32XX_HCLKDIV_CTRL (*(volatile uint32_t *) 0x40004040) +#define LPC32XX_TEST_CLK (*(volatile uint32_t *) 0x400040a4) +#define LPC32XX_AUTOCLK_CTRL (*(volatile uint32_t *) 0x400040ec) +#define LPC32XX_START_ER_PIN (*(volatile uint32_t *) 0x40004030) +#define LPC32XX_START_ER_INT (*(volatile uint32_t *) 0x40004020) +#define LPC32XX_P0_INTR_ER (*(volatile uint32_t *) 0x40004018) +#define LPC32XX_START_SR_PIN (*(volatile uint32_t *) 0x40004038) +#define LPC32XX_START_SR_INT (*(volatile uint32_t *) 0x40004028) +#define LPC32XX_START_RSR_PIN (*(volatile uint32_t *) 0x40004034) +#define LPC32XX_START_RSR_INT (*(volatile uint32_t *) 0x40004024) +#define LPC32XX_START_APR_PIN (*(volatile uint32_t *) 0x4000403c) +#define LPC32XX_START_APR_INT (*(volatile uint32_t *) 0x4000402c) +#define LPC32XX_USB_CTRL (*(volatile uint32_t *) 0x40004064) +#define LPC32XX_USBDIV_CTRL (*(volatile uint32_t *) 0x4000401c) +#define LPC32XX_MS_CTRL (*(volatile uint32_t *) 0x40004080) +#define LPC32XX_DMACLK_CTRL (*(volatile uint32_t *) 0x400040e8) +#define LPC32XX_FLASHCLK_CTRL (*(volatile uint32_t *) 0x400040c8) +#define LPC32XX_MACCLK_CTRL (*(volatile uint32_t *) 0x40004090) +#define LPC32XX_LCDCLK_CTRL (*(volatile uint32_t *) 0x40004054) +#define LPC32XX_I2S_CTRL (*(volatile uint32_t *) 0x4000407c) +#define LPC32XX_SSP_CTRL (*(volatile uint32_t *) 0x40004078) +#define LPC32XX_SPI_CTRL (*(volatile uint32_t *) 0x400040c4) +#define LPC32XX_I2CCLK_CTRL (*(volatile uint32_t *) 0x400040ac) +#define LPC32XX_TIMCLK_CTRL1 (*(volatile uint32_t *) 0x400040c0) +#define LPC32XX_TIMCLK_CTRL (*(volatile uint32_t *) 0x400040bc) +#define LPC32XX_ADCLK_CTRL (*(volatile uint32_t *) 0x400040b4) +#define LPC32XX_ADCLK_CTRL1 (*(volatile uint32_t *) 0x40004060) +#define LPC32XX_KEYCLK_CTRL (*(volatile uint32_t *) 0x400040b0) +#define LPC32XX_PWMCLK_CTRL (*(volatile uint32_t *) 0x400040b8) +#define LPC32XX_UARTCLK_CTRL (*(volatile uint32_t *) 0x400040e4) +#define LPC32XX_POS0_IRAM_CTRL (*(volatile uint32_t *) 0x40004110) +#define LPC32XX_POS1_IRAM_CTRL (*(volatile uint32_t *) 0x40004114) +#define LPC32XX_SDRAMCLK_CTRL (*(volatile uint32_t *) 0x40004068) + +/** @} */ + +/** + * @name Power Control Register (PWR_CTRL) + * + * @{ + */ + +#define PWR_STOP BSP_BIT32(0) +#define PWR_HIGHCORE_ALWAYS BSP_BIT32(1) +#define PWR_NORMAL_RUN_MODE BSP_BIT32(2) +#define PWR_SYSCLKEN_ALWAYS BSP_BIT32(3) +#define PWR_SYSCLKEN_HIGH BSP_BIT32(4) +#define PWR_HIGHCORE_HIGH BSP_BIT32(5) +#define PWR_SDRAM_AUTO_REFRESH BSP_BIT32(7) +#define PWR_UPDATE_EMCSREFREQ BSP_BIT32(8) +#define PWR_EMCSREFREQ BSP_BIT32(9) +#define PWR_HCLK_USES_PERIPH_CLK BSP_BIT32(10) + +/** @} */ + +/** + * @name HCLK PLL Control Register (HCLKPLL_CTRL) + * + * @{ + */ + +#define HCLK_PLL_LOCK BSP_BIT32(0) +#define HCLK_PLL_M(val) BSP_FLD32(val, 1, 8) +#define HCLK_PLL_M_GET(reg) BSP_FLD32GET(reg, 1, 8) +#define HCLK_PLL_N(val) BSP_FLD32(val, 9, 10) +#define HCLK_PLL_N_GET(reg) BSP_FLD32GET(reg, 9, 10) +#define HCLK_PLL_P(val) BSP_FLD32(val, 11, 12) +#define HCLK_PLL_P_GET(reg) BSP_FLD32GET(reg, 11, 12) +#define HCLK_PLL_FBD_FCLKOUT BSP_BIT32(13) +#define HCLK_PLL_DIRECT BSP_BIT32(14) +#define HCLK_PLL_BYPASS BSP_BIT32(15) +#define HCLK_PLL_POWER BSP_BIT32(16) + +/** @} */ + +/** + * @name HCLK Divider Control Register (HCLKDIV_CTRL) + * + * @{ + */ + +#define HCLK_DIV_HCLK(val) BSP_FLD32(val, 0, 1) +#define HCLK_DIV_HCLK_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define HCLK_DIV_PERIPH_CLK(val) BSP_FLD32(val, 2, 6) +#define HCLK_DIV_PERIPH_CLK_GET(reg) BSP_FLD32GET(reg, 2, 6) +#define HCLK_DIV_DDRAM_CLK(val) BSP_FLD32(val, 7, 8) +#define HCLK_DIV_DDRAM_CLK_GET(reg) BSP_FLD32GET(reg, 7, 8) + +/** @} */ + +/** + * @name Timer Clock Control Register (TIMCLK_CTRL) + * + * @{ + */ + +#define TIMCLK_CTRL_WDT BSP_BIT32(0) +#define TIMCLK_CTRL_HST BSP_BIT32(1) + +/** @} */ + +#define LPC32XX_FILL(a, b, s) uint8_t reserved_ ## b [b - a - sizeof(s)] +#define LPC32XX_RESERVE(a, b) uint8_t reserved_ ## b [b - a] + +typedef struct { +} lpc32xx_nand_slc; + +typedef struct { +} lpc32xx_ssp; + +typedef struct { +} lpc32xx_spi; + +typedef struct { +} lpc32xx_sd_card; + +typedef struct { +} lpc32xx_usb; + +typedef struct { +} lpc32xx_lcd; + +typedef struct { +} lpc32xx_etb; + +typedef struct { +} lpc32xx_syscon; + +typedef struct { +} lpc32xx_uart_ctrl; + +typedef struct { +} lpc32xx_uart; + +typedef struct { +} lpc32xx_ms_timer; + +typedef struct { +} lpc32xx_hs_timer; + +/** + * @name Watchdog Timer Interrupt Status Register (WDTIM_INT) + * + * @{ + */ + +#define WDTTIM_INT_MATCH_INT BSP_BIT32(0) + +/** @} */ + +/** + * @name Watchdog Timer Control Register (WDTIM_CTRL) + * + * @{ + */ + +#define WDTTIM_CTRL_COUNT_ENAB BSP_BIT32(0) +#define WDTTIM_CTRL_RESET_COUNT BSP_BIT32(1) +#define WDTTIM_CTRL_PAUSE_EN BSP_BIT32(2) + +/** @} */ + +/** + * @name Watchdog Timer Match Control Register (WDTIM_MCTRL) + * + * @{ + */ + +#define WDTTIM_MCTRL_MR0_INT BSP_BIT32(0) +#define WDTTIM_MCTRL_RESET_COUNT0 BSP_BIT32(1) +#define WDTTIM_MCTRL_STOP_COUNT0 BSP_BIT32(2) +#define WDTTIM_MCTRL_M_RES1 BSP_BIT32(3) +#define WDTTIM_MCTRL_M_RES2 BSP_BIT32(4) +#define WDTTIM_MCTRL_RESFRC1 BSP_BIT32(5) +#define WDTTIM_MCTRL_RESFRC2 BSP_BIT32(6) + +/** @} */ + +/** + * @name Watchdog Timer External Match Control Register (WDTIM_EMR) + * + * @{ + */ + +#define WDTTIM_EMR_EXT_MATCH0 BSP_BIT32(0) +#define WDTTIM_EMR_MATCH_CTRL(val) BSP_FLD32(val, 4, 5) +#define WDTTIM_EMR_MATCH_CTRL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5) + +/** @} */ + +/** + * @name Watchdog Timer Reset Source Register (WDTIM_RES) + * + * @{ + */ + +#define WDTTIM_RES_WDT BSP_BIT32(0) + +/** @} */ + +typedef struct { + uint32_t intr; + uint32_t ctrl; + uint32_t counter; + uint32_t mctrl; + uint32_t match0; + uint32_t emr; + uint32_t pulse; + uint32_t res; +} lpc32xx_wdt; + +typedef struct { +} lpc32xx_debug; + +typedef struct { +} lpc32xx_adc; + +typedef struct { +} lpc32xx_keyscan; + +typedef struct { +} lpc32xx_pwm; + +typedef struct { +} lpc32xx_mcpwm; + +typedef struct { + uint32_t mac1; + uint32_t mac2; + uint32_t ipgt; + uint32_t ipgr; + uint32_t clrt; + uint32_t maxf; + uint32_t supp; + uint32_t test; + uint32_t mcfg; + uint32_t mcmd; + uint32_t madr; + uint32_t mwtd; + uint32_t mrdd; + uint32_t mind; + uint32_t reserved_0 [2]; + uint32_t sa0; + uint32_t sa1; + uint32_t sa2; + uint32_t reserved_1 [45]; + uint32_t command; + uint32_t status; + uint32_t rxdescriptor; + uint32_t rxstatus; + uint32_t rxdescriptornum; + uint32_t rxproduceindex; + uint32_t rxconsumeindex; + uint32_t txdescriptor; + uint32_t txstatus; + uint32_t txdescriptornum; + uint32_t txproduceindex; + uint32_t txconsumeindex; + uint32_t reserved_2 [10]; + uint32_t tsv0; + uint32_t tsv1; + uint32_t rsv; + uint32_t reserved_3 [3]; + uint32_t flowcontrolcnt; + uint32_t flowcontrolsts; + uint32_t reserved_4 [34]; + uint32_t rxfilterctrl; + uint32_t rxfilterwolsts; + uint32_t rxfilterwolclr; + uint32_t reserved_5 [1]; + uint32_t hashfilterl; + uint32_t hashfilterh; + uint32_t reserved_6 [882]; + uint32_t intstatus; + uint32_t intenable; + uint32_t intclear; + uint32_t intset; + uint32_t reserved_7 [1]; + uint32_t powerdown; +} lpc32xx_eth; + +typedef struct { + uint32_t er; + uint32_t rsr; + uint32_t sr; + uint32_t apr; + uint32_t atr; + uint32_t itr; +} lpc32xx_irq; + +typedef struct { + uint32_t p3_inp_state; + uint32_t p3_outp_set; + uint32_t p3_outp_clr; + uint32_t p3_outp_state; + uint32_t p2_dir_set; + uint32_t p2_dir_clr; + uint32_t p2_dir_state; + uint32_t p2_inp_state; + uint32_t p2_outp_set; + uint32_t p2_outp_clr; + uint32_t p2_mux_set; + uint32_t p2_mux_clr; + uint32_t p2_mux_state; + LPC32XX_RESERVE(0x034, 0x040); + uint32_t p0_inp_state; + uint32_t p0_outp_set; + uint32_t p0_outp_clr; + uint32_t p0_outp_state; + uint32_t p0_dir_set; + uint32_t p0_dir_clr; + uint32_t p0_dir_state; + LPC32XX_RESERVE(0x05c, 0x060); + uint32_t p1_inp_state; + uint32_t p1_outp_set; + uint32_t p1_outp_clr; + uint32_t p1_outp_state; + uint32_t p1_dir_set; + uint32_t p1_dir_clr; + uint32_t p1_dir_state; + LPC32XX_RESERVE(0x07c, 0x110); + uint32_t p3_mux_set; + uint32_t p3_mux_clr; + uint32_t p3_mux_state; + LPC32XX_RESERVE(0x11c, 0x120); + uint32_t p0_mux_set; + uint32_t p0_mux_clr; + uint32_t p0_mux_state; + LPC32XX_RESERVE(0x12c, 0x130); + uint32_t p1_mux_set; + uint32_t p1_mux_clr; + uint32_t p1_mux_state; +} lpc32xx_gpio; + +typedef struct { + uint32_t rx_or_tx; + uint32_t stat; + uint32_t ctrl; + uint32_t clk_hi; + uint32_t clk_lo; + uint32_t adr; + uint32_t rxfl; + uint32_t txfl; + uint32_t rxb; + uint32_t txb; + uint32_t s_tx; + uint32_t s_txfl; +} lpc32xx_i2c; + +typedef struct { + uint32_t ucount; + uint32_t dcount; + uint32_t match0; + uint32_t match1; + uint32_t ctrl; + uint32_t intstat; + uint32_t key; + uint32_t sram [32]; +} lpc32xx_rtc; + +typedef struct { + uint32_t control; + uint32_t status; + uint32_t timeout; + uint32_t reserved_0 [5]; +} lpc32xx_emc_ahb; + +typedef struct { + union { + uint32_t w32; + uint16_t w16; + uint8_t w8; + } buff; + uint32_t reserved_0 [8191]; + union { + uint32_t w32; + uint16_t w16; + uint8_t w8; + } data; + uint32_t reserved_1 [8191]; + uint32_t cmd; + uint32_t addr; + uint32_t ecc_enc; + uint32_t ecc_dec; + uint32_t ecc_auto_enc; + uint32_t ecc_auto_dec; + uint32_t rpr; + uint32_t wpr; + uint32_t rubp; + uint32_t robp; + uint32_t sw_wp_add_low; + uint32_t sw_wp_add_hig; + uint32_t icr; + uint32_t time; + uint32_t irq_mr; + uint32_t irq_sr; + uint32_t reserved_2; + uint32_t lock_pr; + uint32_t isr; + uint32_t ceh; +} lpc32xx_nand_mlc; + +typedef struct { + lpc32xx_nand_slc nand_slc; + LPC32XX_FILL(0x20020000, 0x20084000, lpc32xx_nand_slc); + lpc32xx_ssp ssp_0; + LPC32XX_FILL(0x20084000, 0x20088000, lpc32xx_ssp); + lpc32xx_spi spi_1; + LPC32XX_FILL(0x20088000, 0x2008c000, lpc32xx_spi); + lpc32xx_ssp ssp_1; + LPC32XX_FILL(0x2008c000, 0x20090000, lpc32xx_ssp); + lpc32xx_spi spi_2; + LPC32XX_FILL(0x20090000, 0x20094000, lpc32xx_spi); + lpc_i2s i2s_0; + LPC32XX_FILL(0x20094000, 0x20098000, lpc_i2s); + lpc32xx_sd_card sd_card; + LPC32XX_FILL(0x20098000, 0x2009c000, lpc32xx_sd_card); + lpc_i2s i2s_1; + LPC32XX_FILL(0x2009c000, 0x200a8000, lpc_i2s); + lpc32xx_nand_mlc nand_mlc; + LPC32XX_FILL(0x200a8000, 0x31000000, lpc32xx_nand_mlc); + lpc_dma dma; + LPC32XX_FILL(0x31000000, 0x31020000, lpc_dma); + lpc32xx_usb usb; + LPC32XX_FILL(0x31020000, 0x31040000, lpc32xx_usb); + lpc32xx_lcd lcd; + LPC32XX_FILL(0x31040000, 0x31060000, lpc32xx_lcd); + lpc32xx_eth eth; + LPC32XX_FILL(0x31060000, 0x31080000, lpc32xx_eth); + lpc_emc emc; + LPC32XX_FILL(0x31080000, 0x31080400, lpc_emc); + lpc32xx_emc_ahb emc_ahb [5]; + LPC32XX_FILL(0x31080400, 0x310c0000, lpc32xx_emc_ahb [5]); + lpc32xx_etb etb; + LPC32XX_FILL(0x310c0000, 0x40004000, lpc32xx_etb); + lpc32xx_syscon syscon; + LPC32XX_FILL(0x40004000, 0x40008000, lpc32xx_syscon); + lpc32xx_irq mic; + LPC32XX_FILL(0x40008000, 0x4000c000, lpc32xx_irq); + lpc32xx_irq sic_1; + LPC32XX_FILL(0x4000c000, 0x40010000, lpc32xx_irq); + lpc32xx_irq sic_2; + LPC32XX_FILL(0x40010000, 0x40014000, lpc32xx_irq); + lpc32xx_uart uart_1; + LPC32XX_FILL(0x40014000, 0x40018000, lpc32xx_uart); + lpc32xx_uart uart_2; + LPC32XX_FILL(0x40018000, 0x4001c000, lpc32xx_uart); + lpc32xx_uart uart_7; + LPC32XX_FILL(0x4001c000, 0x40024000, lpc32xx_uart); + lpc32xx_rtc rtc; + LPC32XX_FILL(0x40024000, 0x40028000, lpc32xx_rtc); + lpc32xx_gpio gpio; + LPC32XX_FILL(0x40028000, 0x4002c000, lpc32xx_gpio); + lpc_timer timer_4; + LPC32XX_FILL(0x4002c000, 0x40030000, lpc_timer); + lpc_timer timer_5; + LPC32XX_FILL(0x40030000, 0x40034000, lpc_timer); + lpc32xx_ms_timer ms_timer; + LPC32XX_FILL(0x40034000, 0x40038000, lpc32xx_ms_timer); + lpc32xx_hs_timer hs_timer; + LPC32XX_FILL(0x40038000, 0x4003c000, lpc32xx_hs_timer); + lpc32xx_wdt wdt; + LPC32XX_FILL(0x4003c000, 0x40040000, lpc32xx_wdt); + lpc32xx_debug debug; + LPC32XX_FILL(0x40040000, 0x40044000, lpc32xx_debug); + lpc_timer timer_0; + LPC32XX_FILL(0x40044000, 0x40048000, lpc_timer); + lpc32xx_adc adc; + LPC32XX_FILL(0x40048000, 0x4004c000, lpc32xx_adc); + lpc_timer timer_1; + LPC32XX_FILL(0x4004c000, 0x40050000, lpc_timer); + lpc32xx_keyscan keyscan; + LPC32XX_FILL(0x40050000, 0x40054000, lpc32xx_keyscan); + lpc32xx_uart_ctrl uart_ctrl; + LPC32XX_FILL(0x40054000, 0x40058000, lpc32xx_uart_ctrl); + lpc_timer timer_2; + LPC32XX_FILL(0x40058000, 0x4005c000, lpc_timer); + lpc32xx_pwm pwm_1_and_pwm_2; + LPC32XX_FILL(0x4005c000, 0x40060000, lpc32xx_pwm); + lpc_timer timer3; + LPC32XX_FILL(0x40060000, 0x40080000, lpc_timer); + lpc32xx_uart uart_3; + LPC32XX_FILL(0x40080000, 0x40088000, lpc32xx_uart); + lpc32xx_uart uart_4; + LPC32XX_FILL(0x40088000, 0x40090000, lpc32xx_uart); + lpc32xx_uart uart_5; + LPC32XX_FILL(0x40090000, 0x40098000, lpc32xx_uart); + lpc32xx_uart uart_6; + LPC32XX_FILL(0x40098000, 0x400a0000, lpc32xx_uart); + lpc32xx_i2c i2c_1; + LPC32XX_FILL(0x400a0000, 0x400a8000, lpc32xx_i2c); + lpc32xx_i2c i2c_2; + LPC32XX_FILL(0x400a8000, 0x400e8000, lpc32xx_i2c); + lpc32xx_mcpwm mcpwm; +} lpc32xx_registers; + +extern volatile lpc32xx_registers lpc32xx; + +/** @} */ + +#endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/mmu.h b/bsps/arm/lpc32xx/include/bsp/mmu.h new file mode 100644 index 0000000000..32352b5ed9 --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/mmu.h @@ -0,0 +1,79 @@ +/** + * @file + * + * @ingroup lpc32xx_mmu + * + * @brief MMU support API. + */ + +/* + * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_MMU_H +#define LIBBSP_ARM_LPC32XX_MMU_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc32xx_mmu MMU Support + * + * @ingroup arm_lpc32xx + * + * @brief MMU support. + * + * @{ + */ + +#define LPC32XX_MMU_CLIENT_DOMAIN 15U + +#define LPC32XX_MMU_READ_ONLY \ + ((LPC32XX_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ + | ARM_MMU_SECT_DEFAULT) + +#define LPC32XX_MMU_READ_ONLY_CACHED \ + (LPC32XX_MMU_READ_ONLY | ARM_MMU_SECT_C | ARM_MMU_SECT_B) + +#define LPC32XX_MMU_READ_WRITE \ + ((LPC32XX_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ + | ARM_MMU_SECT_AP_0 \ + | ARM_MMU_SECT_DEFAULT) + +#define LPC32XX_MMU_READ_WRITE_CACHED \ + (LPC32XX_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B) + +/** + * @brief Sets the @a section_flags for the address range [@a begin, @a end). + * + * @return Previous section flags of the first modified entry. + */ +static inline uint32_t lpc32xx_set_translation_table_entries( + const void *begin, + const void *end, + uint32_t section_flags +) +{ + return arm_cp15_set_translation_table_entries(begin, end, section_flags); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_MMU_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/nand-mlc.h b/bsps/arm/lpc32xx/include/bsp/nand-mlc.h new file mode 100644 index 0000000000..2aa8312945 --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/nand-mlc.h @@ -0,0 +1,422 @@ +/** + * @file + * + * @ingroup lpc32xx_nand_mlc + * + * @brief NAND MLC controller API. + */ + +/* + * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * Copyright (c) 2011 Stephan Hoffmann + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_NAND_MLC_H +#define LIBBSP_ARM_LPC32XX_NAND_MLC_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc32xx_nand_mlc NAND MLC Controller + * + * @ingroup arm_lpc32xx + * + * @brief NAND MLC Controller. + * + * Timing constraints: + * + * -# (WR_LOW + 1) / HCLK >= tWP + * -# (WR_HIGH - WR_LOW) / HCLK >= tWH + * -# (WR_LOW + 1) / HCLK + (WR_HIGH - WR_LOW) / HCLK >= tWC + * -# (RD_LOW + 1) / HCLK >= tRP + * -# (RD_LOW + 1) / HCLK >= tREA + tSU + * -# (RD_HIGH - RD_LOW) / HCLK >= tREH + * -# (RD_LOW + 1) / HCLK + (RD_HIGH - RD_LOW) / HCLK >= tRC + * -# (RD_HIGH - RD_LOW) / HCLK + NAND_TA / HCLK >= tRHZ + * -# BUSY_DELAY / HCLK >= max(tWB, tRB) + * -# TCEA_DELAY / HCLK >= tCEA - tREA + * + * Known flash layouts (Format: SP = small pages, LP = large pages / address + * cycles / pages per block): + * + * -# SP/3/32 + * -# SP/4/32 + * -# LP/4/64 + * -# LP/5/64 + * -# LP/5/128 + * + * @{ + */ + +/** + * @name MLC NAND Flash Dimensions + * + * @{ + */ + +#define MLC_SMALL_PAGE_SIZE 528 +#define MLC_SMALL_DATA_SIZE 512 +#define MLC_SMALL_SPARE_SIZE 16 +#define MLC_SMALL_USER_SPARE_SIZE 6 +#define MLC_SMALL_ECC_SPARE_SIZE 10 +#define MLC_SMALL_DATA_WORD_COUNT (MLC_SMALL_DATA_SIZE / 4) +#define MLC_SMALL_SPARE_WORD_COUNT (MLC_SMALL_SPARE_SIZE / 4) +#define MLC_SMALL_PAGES_PER_LARGE_PAGE 4 +#define MLC_LARGE_PAGE_SIZE \ + (MLC_SMALL_PAGES_PER_LARGE_PAGE * MLC_SMALL_PAGE_SIZE) +#define MLC_LARGE_DATA_SIZE \ + (MLC_SMALL_PAGES_PER_LARGE_PAGE * MLC_SMALL_DATA_SIZE) +#define MLC_LARGE_SPARE_SIZE \ + (MLC_SMALL_PAGES_PER_LARGE_PAGE * MLC_SMALL_SPARE_SIZE) +#define MLC_LARGE_DATA_WORD_COUNT (MLC_LARGE_DATA_SIZE / 4) +#define MLC_LARGE_SPARE_WORD_COUNT (MLC_LARGE_SPARE_SIZE / 4) + +/** @} */ + +/** + * @name NAND Flash Clock Control Register (FLASHCLK_CTRL) + * + * @{ + */ + +#define FLASHCLK_IRQ_MLC BSP_BIT32(5) +#define FLASHCLK_MLC_DMA_RNB BSP_BIT32(4) +#define FLASHCLK_MLC_DMA_INT BSP_BIT32(3) +#define FLASHCLK_SELECT_SLC BSP_BIT32(2) +#define FLASHCLK_MLC_CLK_ENABLE BSP_BIT32(1) +#define FLASHCLK_SLC_CLK_ENABLE BSP_BIT32(0) + +/** @} */ + +/** + * @name MLC NAND Timing Register (MLC_TIME_REG) + * + * @{ + */ + +#define MLC_TIME_WR_LOW(val) BSP_FLD32(val, 0, 3) +#define MLC_TIME_WR_HIGH(val) BSP_FLD32(val, 4, 7) +#define MLC_TIME_RD_LOW(val) BSP_FLD32(val, 8, 11) +#define MLC_TIME_RD_HIGH(val) BSP_FLD32(val, 12, 15) +#define MLC_TIME_NAND_TA(val) BSP_FLD32(val, 16, 18) +#define MLC_TIME_BUSY_DELAY(val) BSP_FLD32(val, 19, 23) +#define MLC_TIME_TCEA_DELAY(val) BSP_FLD32(val, 24, 25) + +/** @} */ + +/** + * @name MLC NAND Lock Protection Register (MLC_LOCK_PR) + * + * @{ + */ + +#define MLC_UNLOCK_PROT 0xa25e + +/** @} */ + +/** + * @name MLC NAND Status Register (MLC_ISR) + * + * @{ + */ + +#define MLC_ISR_DECODER_FAILURE BSP_BIT32(6) +#define MLC_ISR_SYMBOL_ERRORS(reg) BSP_FLD32GET(reg, 4, 5) +#define MLC_ISR_ERRORS_DETECTED BSP_BIT32(3) +#define MLC_ISR_ECC_READY BSP_BIT32(2) +#define MLC_ISR_CONTROLLER_READY BSP_BIT32(1) +#define MLC_ISR_NAND_READY BSP_BIT32(0) + +/** @} */ + +/** + * @name MLC NAND Controller Configuration Register (MLC_ICR) + * + * @{ + */ + +#define MLC_ICR_SOFT_WRITE_PROT BSP_BIT32(3) +#define MLC_ICR_LARGE_PAGES BSP_BIT32(2) +#define MLC_ICR_ADDR_WORD_COUNT_4_5 BSP_BIT32(1) +#define MLC_ICR_IO_BUS_16 BSP_BIT32(0) + +/** @} */ + +/** + * @name MLC NAND Auto Encode Register (MLC_ECC_AUTO_ENC) + * + * @{ + */ + +#define MLC_ECC_AUTO_ENC_PROGRAM BSP_BIT32(8) + +/** @} */ + +/** + * @name NAND Status Register + * + * @{ + */ + +#define NAND_STATUS_ERROR (1U << 0) +#define NAND_STATUS_READY (1U << 6) +#define NAND_STATUS_NOT_PROTECTED (1U << 7) + +/** @} */ + +/** + * @brief MLC NAND controller configuration. + */ +typedef struct { + uint32_t flags; + + uint32_t block_count; + + /** + * @brief Value for the MLC NAND Timing Register (MLC_TIME_REG). + */ + uint32_t time; +} lpc32xx_mlc_config; + +/** + * @brief Selects small pages (512 Bytes user data and 16 Bytes spare data) + * or large pages (2048 Bytes user data and 64 Bytes spare data) if not set. + */ +#define MLC_SMALL_PAGES 0x1U + +/** + * @Brief Selects 4/5 address cycles for small/large pages or 3/4 address + * cycles if not set. + */ +#define MLC_MANY_ADDRESS_CYCLES 0x2U + +/** + * @brief Selects 64 pages per block or 128 pages per block if not set. + * + * This flag is only valid for large pages. + */ +#define MLC_NORMAL_BLOCKS 0x4U + +/** + * @brief Selects 16-bit IO width or 8-bit IO width if not set. + */ +#define MLC_IO_WIDTH_16_BIT 0x8U + +/** + * @brief Initializes the MLC NAND controller according to @a cfg. + */ +void lpc32xx_mlc_init(const lpc32xx_mlc_config *cfg); + +uint32_t lpc32xx_mlc_page_size(void); + +uint32_t lpc32xx_mlc_pages_per_block(void); + +uint32_t lpc32xx_mlc_block_count(void); + +uint32_t lpc32xx_mlc_io_width(void); + +void lpc32xx_mlc_write_protection( + uint32_t page_index_low, + uint32_t page_index_high +); + +void lpc32xx_mlc_read_id(uint8_t *id, size_t n); + +/** + * @brief Reads the page with index @a page_index. + * + * Bytes 6 to 15 of the spare area will contain the ECC. + * + * If the read is successful, then the @a symbol_error_count will contain the + * number of detected symbol errors (0, 1, 2, 3, or 4), else the value will be + * 0xffffffff. The @a symbol_error_count pointer may be @c NULL. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid @a page_index value. + * @retval RTEMS_IO_ERROR Uncorrectable bit error. + */ +rtems_status_code lpc32xx_mlc_read_page( + uint32_t page_index, + void *data, + void *spare, + uint32_t *symbol_error_count +); + +/** + * @brief Checks if the block with index @a block_index is valid. + * + * The initial valid block information of the manufacturer will be used. + * Unfortunately there seems to be no standard for this. A block will be + * considered as bad if the first or second page of this block does not contain + * 0xff at the 6th byte of the spare area. This should work for flashes with + * small pages and a 8-bit IO width. + * + * @retval RTEMS_SUCCESSFUL The block is valid. + * @retval RTEMS_INVALID_ID Invalid @a block_index value. + * @retval RTEMS_IO_ERROR Uncorrectable bit error. + * @retval RTEMS_INCORRECT_STATE The block is bad. + * @retval RTEMS_NOT_IMPLEMENTED No implementation available for this flash + * type. + */ +rtems_status_code lpc32xx_mlc_is_valid_block(uint32_t block_index); + +/** + * @brief Erases the block with index @a block_index. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid @a block_index value. + * @retval RTEMS_UNSATISFIED Erase error. + */ +rtems_status_code lpc32xx_mlc_erase_block(uint32_t block_index); + +/** + * @brief Erases the block with index @a block_index. + * + * In case of an erase error all pages and the spare areas of this block are + * programmed with zero values. This will hopefully mark the block as bad. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INCORRECT_STATE The block is bad. + * @retval RTEMS_INVALID_ID Invalid @a block_index value. + * @retval RTEMS_UNSATISFIED Erase error. + * @retval RTEMS_NOT_IMPLEMENTED No implementation available for this flash + * type. + */ +rtems_status_code lpc32xx_mlc_erase_block_safe(uint32_t block_index); + +/** + * @brief Erases the block with index @a block_index. + * + * Variant of lpc32xx_mlc_erase_block_safe() with more parameters for + * efficiency reasons. The @a page_begin must be the index of the first page + * of the block. The @a page_end must be the page index of the last page of + * the block plus one. + */ +rtems_status_code lpc32xx_mlc_erase_block_safe_3( + uint32_t block_index, + uint32_t page_begin, + uint32_t page_end +); + +/** + * @brief Writes zero values to the pages specified by @a page_begin and + * @a page_end. + * + * The data and spare area are cleared to zero. This marks the pages as bad. + */ +void lpc32xx_mlc_zero_pages(uint32_t page_begin, uint32_t page_end); + +/** + * @brief Writes the page with index @a page_index. + * + * Only the bytes 0 to 5 of the spare area can be used for user data, the bytes + * 6 to 15 will be used for the automatically generated ECC. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid @a page_index value. + * @retval RTEMS_IO_ERROR Write error. + */ +rtems_status_code lpc32xx_mlc_write_page_with_ecc( + uint32_t page_index, + const void *data, + const void *spare +); + +/** + * @brief Writes @a src_size Bytes from @a src to the flash area specified by + * @a block_begin and @a block_end. + * + * The @a page_buffer will be used as an intermediate buffer. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid @a block_begin or @a block_end value. + * @retval RTEMS_IO_ERROR Too many bad blocks or source area too big. + */ +rtems_status_code lpc32xx_mlc_write_blocks( + uint32_t block_begin, + uint32_t block_end, + const void *src, + size_t src_size, + uint32_t page_buffer [MLC_LARGE_DATA_WORD_COUNT] +); + +/** + * @brief Read blocks process function type. + * + * @see lpc32xx_mlc_read_blocks(). + * + * @retval false Continue processing. + * @retval true Stop processing. + */ +typedef bool (*lpc32xx_mlc_read_process)( + void *process_arg, + uint32_t page_index, + uint32_t page_size, + uint32_t page_data [MLC_LARGE_DATA_WORD_COUNT], + uint32_t page_spare [MLC_LARGE_SPARE_WORD_COUNT] +); + +/** + * @brief Reads the pages of block @a block_begin up to and excluding + * @a block_end. + * + * For each page @a process will be called with the @a process_arg parameter, + * the page_index, the page data and the page spare. + * + * The @a page_buffer_0 and @a page_buffer_1 will be used as + * intermediate buffers. + */ +rtems_status_code lpc32xx_mlc_read_blocks( + uint32_t block_begin, + uint32_t block_end, + lpc32xx_mlc_read_process process, + void *process_arg, + uint32_t page_buffer_0 [MLC_LARGE_DATA_WORD_COUNT], + uint32_t page_buffer_1 [MLC_LARGE_DATA_WORD_COUNT] +); + +/** + * @brief Checks if the page spare area indicates to a bad page. + * + * If the first (byte offset 0) or sixth (byte offset 5) byte of the spare area + * has a value other than 0xff, then it returns @a true (the page is bad), else + * it returns @a false (the page is not bad). + * + * Samsung uses the sixth byte to indicate a bad page. Mircon uses the first + * and sixth byte to indicate a bad page. + * + * This functions works only for small page flashes. + */ +static inline bool lpc32xx_mlc_is_bad_page(const uint32_t *spare) +{ + uint32_t first_byte_mask = 0x000000ff; + uint32_t sixth_byte_mask = 0x0000ff00; + + return (spare [0] & first_byte_mask) != first_byte_mask + || (spare [1] & sixth_byte_mask) != sixth_byte_mask; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_NAND_MLC_H */ diff --git a/bsps/arm/lpc32xx/include/tm27.h b/bsps/arm/lpc32xx/include/tm27.h new file mode 100644 index 0000000000..4cbc17a085 --- /dev/null +++ b/bsps/arm/lpc32xx/include/tm27.h @@ -0,0 +1,72 @@ +/* @file + * + * @ingroup arm_lpc32xx + * + * @brief Implementations of interrupt mechanisms for Time Test 27 + */ + +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +#include + +#include +#include +#include + +#define MUST_WAIT_FOR_INTERRUPT 1 + +static void Install_tm27_vector(void (*handler)(rtems_vector_number)) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + LPC32XX_SW_INT = 0; + + sc = rtems_interrupt_handler_install( + LPC32XX_IRQ_SW, + "SW", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +static void Cause_tm27_intr(void) +{ + LPC32XX_SW_INT = 0x1; +} + +static void Clear_tm27_intr(void) +{ + LPC32XX_SW_INT = 0; + lpc32xx_irq_set_priority(LPC32XX_IRQ_SW, LPC32XX_IRQ_PRIORITY_LOWEST); +} + +static void Lower_tm27_intr(void) +{ + bsp_interrupt_vector_enable(LPC32XX_IRQ_SW); + lpc32xx_irq_set_priority(LPC32XX_IRQ_SW, LPC32XX_IRQ_PRIORITY_HIGHEST); +} + +#endif /* __tm27_h */ diff --git a/bsps/arm/raspberrypi/headers.am b/bsps/arm/raspberrypi/headers.am new file mode 100644 index 0000000000..91cd18c86f --- /dev/null +++ b/bsps/arm/raspberrypi/headers.am @@ -0,0 +1,20 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/fbcons.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/mailbox.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/mmu.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/raspberrypi.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/rpi-fb.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/rpi-gpio.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/spi.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/usart.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/vc.h diff --git a/bsps/arm/raspberrypi/include/bsp.h b/bsps/arm/raspberrypi/include/bsp.h new file mode 100644 index 0000000000..ecd5b6af08 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp.h @@ -0,0 +1,69 @@ +/** + * @file + * + * @ingroup arm_raspberrypi + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2015 Yang Qiao + * Copyright (c) 2013 Alan Cudmore + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_BSP_H +#define LIBBSP_ARM_RASPBERRYPI_BSP_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#define RPI_L2_CACHE_ENABLE 1 + +#define BSP_GPIO_PIN_COUNT 32 +#define BSP_GPIO_PINS_PER_BANK 32 +#define BSP_GPIO_PINS_PER_SELECT_BANK 10 + +#define BSP_CONSOLE_UART0 0 +#define BSP_CONSOLE_FB 1 + +void rpi_init_cmdline(void); +const char *rpi_cmdline_get_cached(void); +const char *rpi_cmdline_get_raw(void); +const char *rpi_cmdline_get_arg(const char* arg); + +void rpi_video_init(void); +void rpi_fb_outch (char); +int rpi_video_is_initialized(void); + +void rpi_ipi_initialize(void); +void rpi_start_rtems_on_secondary_processor(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_BSP_H */ + +/** + * @defgroup arm_raspberrypi Raspberry Pi Support + * + * @ingroup bsp_arm + * + * @brief Raspberry Pi support package + * + */ diff --git a/bsps/arm/raspberrypi/include/bsp/fbcons.h b/bsps/arm/raspberrypi/include/bsp/fbcons.h new file mode 100644 index 0000000000..d0e126699a --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/fbcons.h @@ -0,0 +1,47 @@ +/** + * @file + * + * @ingroup raspberrypi_console + * + * @brief framebuffer graphic console support. + */ + +/* + * Copyright (c) 2015 Yang Qiao + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef _FBCONS_H_ +#define _FBCONS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This is the ASCII for "PI" in the upper word and 2835 + * in the lower which should be unique enough to + * distinguish this type of serial device from others. + */ + +#define FB_CONSOLE 0x50492835 + +bool fbcons_probe( int minor ); + +/* + * Driver function table + */ +extern const console_fns fbcons_fns; + +#ifdef __cplusplus +} +#endif + +#endif /* _FBCONS_H_ */ diff --git a/bsps/arm/raspberrypi/include/bsp/i2c.h b/bsps/arm/raspberrypi/include/bsp/i2c.h new file mode 100644 index 0000000000..4a8dbbf2ac --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/i2c.h @@ -0,0 +1,95 @@ +/** + * @file i2c.h + * + * @ingroup raspberrypi_i2c + * + * @brief Raspberry Pi specific I2C definitions. + */ + +/* + * Copyright (c) 2014-2015 Andre Marques + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_I2C_H +#define LIBBSP_ARM_RASPBERRYPI_I2C_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @name I2C constants. + * + * @{ + */ + +/** + * @brief BSC controller core clock rate in Hz. + * + * This is set to 150 MHz as per the BCM2835 datasheet. + */ +#define BSC_CORE_CLK_HZ 150000000 + +/** + * @brief Default bus clock. + * + * This sets the bus with a 100 kHz clock speed. + */ +#define DEFAULT_BUS_CLOCK 100000 + +/** @} */ + +/** + * @name I2C directives. + * + * @{ + */ + +/** + * @brief Setups the Raspberry Pi GPIO header to activate the BSC I2C bus. + */ +extern void rpi_i2c_init(void); + +/** + * @brief Registers the Raspberry Pi BSC I2C bus with the + * Linux I2C User-Space API. + * + * @param[in] bus_path Path to the bus device file. + * @param[in] bus_clock Bus clock in Hz. + * + * @retval 0 Bus registered successfully. + * @retval <0 Could not register the bus. The return value is a negative + * errno code. + */ +extern int rpi_i2c_register_bus( + const char *bus_path, + uint32_t bus_clock +); + +/** + * @brief Setups the Raspberry Pi BSC I2C bus (located on the GPIO header) + * on the "/dev/i2c" device file, using the default bus clock. + * + * @retval 0 Bus configured and registered successfully. + * @retval <0 See @see rpi_i2c_register_bus(). + */ +static inline int rpi_setup_i2c_bus(void) +{ + rpi_i2c_init(); + + return rpi_i2c_register_bus("/dev/i2c", DEFAULT_BUS_CLOCK); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_I2C_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/irq.h b/bsps/arm/raspberrypi/include/bsp/irq.h new file mode 100644 index 0000000000..4600534171 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/irq.h @@ -0,0 +1,76 @@ +/** + * @file + * + * @ingroup raspberrypi_interrupt + * + * @brief Interrupt definitions. + */ + +/** + * Copyright (c) 2013 Alan Cudmore + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASBPERRYPI_IRQ_H +#define LIBBSP_ARM_RASPBERRYPI_IRQ_H + +#ifndef ASM + +#include +#include +#include + +/** + * @defgroup raspberrypi_interrupt Interrrupt Support + * + * @ingroup arm_raspberrypi + * + * @brief Interrupt support. + */ + +#define BCM2835_INTC_TOTAL_IRQ 64 + 8 + + +#define BCM2835_IRQ_ID_GPU_TIMER_M0 0 +#define BCM2835_IRQ_ID_GPU_TIMER_M1 1 +#define BCM2835_IRQ_ID_GPU_TIMER_M2 2 +#define BCM2835_IRQ_ID_GPU_TIMER_M3 3 + +#define BCM2835_IRQ_ID_USB 9 +#define BCM2835_IRQ_ID_AUX 29 +#define BCM2835_IRQ_ID_SPI_SLAVE 43 +#define BCM2835_IRQ_ID_PWA0 45 +#define BCM2835_IRQ_ID_PWA1 46 +#define BCM2835_IRQ_ID_SMI 48 +#define BCM2835_IRQ_ID_GPIO_0 49 +#define BCM2835_IRQ_ID_GPIO_1 50 +#define BCM2835_IRQ_ID_GPIO_2 51 +#define BCM2835_IRQ_ID_GPIO_3 52 +#define BCM2835_IRQ_ID_I2C 53 +#define BCM2835_IRQ_ID_SPI 54 +#define BCM2835_IRQ_ID_PCM 55 +#define BCM2835_IRQ_ID_UART 57 +#define BCM2835_IRQ_ID_SD 62 + +#define BCM2835_IRQ_ID_BASIC_BASE_ID 64 +#define BCM2835_IRQ_ID_TIMER_0 64 +#define BCM2835_IRQ_ID_MAILBOX_0 65 +#define BCM2835_IRQ_ID_DOORBELL_0 66 +#define BCM2835_IRQ_ID_DOORBELL_1 67 +#define BCM2835_IRQ_ID_GPU0_HALTED 68 +#define BCM2835_IRQ_ID_GPU1_HALTED 69 +#define BCM2835_IRQ_ID_ILL_ACCESS_1 70 +#define BCM2835_IRQ_ID_ILL_ACCESS_0 71 + +#define BSP_INTERRUPT_VECTOR_MIN (0) +#define BSP_INTERRUPT_VECTOR_MAX (BCM2835_INTC_TOTAL_IRQ - 1) + +#define BSP_IRQ_COUNT (BCM2835_INTC_TOTAL_IRQ) + +#endif /* ASM */ +#endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/mailbox.h b/bsps/arm/raspberrypi/include/bsp/mailbox.h new file mode 100644 index 0000000000..e6cb0f8c27 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/mailbox.h @@ -0,0 +1,32 @@ +/** + * @file + * + * @ingroup raspberrypi + * + * @brief mailbox support. + */ +/* + * Copyright (c) 2015 Yang Qiao + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_MAILBOX_H +#define LIBBSP_ARM_RASPBERRYPI_MAILBOX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern unsigned int raspberrypi_mailbox_read(unsigned int channel); +extern void raspberrypi_mailbox_write(unsigned int channel, unsigned int data); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_MAILBOX_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/mmu.h b/bsps/arm/raspberrypi/include/bsp/mmu.h new file mode 100644 index 0000000000..45ecc5a2a4 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/mmu.h @@ -0,0 +1,68 @@ +/** + * @file + * + * @ingroup rapberrypi_mmu + * + * @brief MMU API. + */ + +/* + * Copyright (c) 2013 Alan Cudmore. + * based on work by: + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_MMU_H +#define LIBBSP_ARM_RASPBERRYPI_MMU_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup raspberrypi_mmu MMU Support + * + * @ingroup arm_raspberrypi + * + * @brief MMU support. + * + * @{ + */ + +#define RASPBERRYPI_MMU_CLIENT_DOMAIN 15U + +#define RASPBERRYPI_MMU_READ_ONLY \ + ((RASPBERRYPI_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ + | ARM_MMU_SECT_DEFAULT) + +#define RASPBERRYPI_MMU_READ_ONLY_CACHED \ + (RASPBERRYPI_MMU_READ_ONLY | ARM_MMU_SECT_C | ARM_MMU_SECT_B) + +#define RASPBERRYPI_MMU_READ_WRITE \ + ((RASPBERRYPI_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ + | ARM_MMU_SECT_AP_0 \ + | ARM_MMU_SECT_DEFAULT) + +#define RASPBERRYPI_MMU_READ_WRITE_CACHED \ + (RASPBERRYPI_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_MMU_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/raspberrypi.h b/bsps/arm/raspberrypi/include/bsp/raspberrypi.h new file mode 100644 index 0000000000..4ef5f713ad --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/raspberrypi.h @@ -0,0 +1,572 @@ +/** + * @file raspberrypi.h + * + * @ingroup raspberrypi_reg + * + * @brief Register definitions. + */ + +/* + * Copyright (c) 2014-2015 Andre Marques + * Copyright (c) 2013 Alan Cudmore. + * Copyright (c) 2015 Yang Qiao + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H +#define LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H + +#include +#include +#include + +/** + * @defgroup raspberrypi_reg Register Definitions + * + * @ingroup arm_raspberrypi + * + * @brief Register Definitions + * + * @{ + */ + +/** + * @name Register Macros + * + * @{ + */ + +#define BCM2835_REG(x) (*(volatile uint32_t *)(x)) +#define BCM2835_BIT(n) (1 << (n)) + +/** @} */ + +/** + * @name Peripheral Base Register Address + * + * @{ + */ + +#if (BSP_IS_RPI2 == 1) + #define RPI_PERIPHERAL_BASE 0x3F000000 +#else + #define RPI_PERIPHERAL_BASE 0x20000000 +#endif + +#define RPI_PERIPHERAL_SIZE 0x01000000 + +/** + * @name Internal ARM Timer Registers + * + * @{ + */ + +#define BCM2835_CLOCK_FREQ 250000000 + +#define BCM2835_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400) + +#define BCM2835_TIMER_LOD (BCM2835_TIMER_BASE + 0x00) +#define BCM2835_TIMER_VAL (BCM2835_TIMER_BASE + 0x04) +#define BCM2835_TIMER_CTL (BCM2835_TIMER_BASE + 0x08) +#define BCM2835_TIMER_CLI (BCM2835_TIMER_BASE + 0x0C) +#define BCM2835_TIMER_RIS (BCM2835_TIMER_BASE + 0x10) +#define BCM2835_TIMER_MIS (BCM2835_TIMER_BASE + 0x14) +#define BCM2835_TIMER_RLD (BCM2835_TIMER_BASE + 0x18) +#define BCM2835_TIMER_DIV (BCM2835_TIMER_BASE + 0x1C) +#define BCM2835_TIMER_CNT (BCM2835_TIMER_BASE + 0x20) + +#define BCM2835_TIMER_PRESCALE 0xF9 + +/** @} */ + +/** + * @name Power Management and Watchdog Registers + * + * @{ + */ + +#define BCM2835_PM_PASSWD_MAGIC 0x5a000000 + +#define BCM2835_PM_BASE (RPI_PERIPHERAL_BASE + 0x100000) + +#define BCM2835_PM_GNRIC (BCM2835_PM_BASE + 0x00) +#define BCM2835_PM_GNRIC_POWUP 0x00000001 +#define BCM2835_PM_GNRIC_POWOK 0x00000002 +#define BCM2835_PM_GNRIC_ISPOW 0x00000004 +#define BCM2835_PM_GNRIC_MEMREP 0x00000008 +#define BCM2835_PM_GNRIC_MRDONE 0x00000010 +#define BCM2835_PM_GNRIC_ISFUNC 0x00000020 +#define BCM2835_PM_GNRIC_RSTN 0x00000fc0 +#define BCM2835_PM_GNRIC_ENAB 0x00001000 +#define BCM2835_PM_GNRIC_CFG 0x007f0000 + +#define BCM2835_PM_AUDIO (BCM2835_PM_BASE + 0x04) +#define BCM2835_PM_AUDIO_APSM 0x000fffff +#define BCM2835_PM_AUDIO_CTRLEN 0x00100000 +#define BCM2835_PM_AUDIO_RSTN 0x00200000 + +#define BCM2835_PM_STATUS (BCM2835_PM_BASE + 0x18) + +#define BCM2835_PM_RSTC (BCM2835_PM_BASE + 0x1c) +#define BCM2835_PM_RSTC_DRCFG 0x00000003 +#define BCM2835_PM_RSTC_WRCFG 0x00000030 +#define BCM2835_PM_RSTC_WRCFG_FULL 0x00000020 +#define BCM2835_PM_RSTC_SRCFG 0x00000300 +#define BCM2835_PM_RSTC_QRCFG 0x00003000 +#define BCM2835_PM_RSTC_FRCFG 0x00030000 +#define BCM2835_PM_RSTC_HRCFG 0x00300000 + +#define BCM2835_PM_RSTS (BCM2835_PM_BASE + 0x20) +#define BCM2835_PM_RSTS_HADDRQ 0x00000001 +#define BCM2835_PM_RSTS_HADDRF 0x00000002 +#define BCM2835_PM_RSTS_HADDRH 0x00000004 +#define BCM2835_PM_RSTS_HADWRQ 0x00000010 +#define BCM2835_PM_RSTS_HADWRF 0x00000020 +#define BCM2835_PM_RSTS_HADWRH 0x00000040 +#define BCM2835_PM_RSTS_HADSRQ 0x00000100 +#define BCM2835_PM_RSTS_HADSRF 0x00000200 +#define BCM2835_PM_RSTS_HADSRH 0x00000400 +#define BCM2835_PM_RSTS_HADPOR 0x00001000 + +#define BCM2835_PM_WDOG (BCM2835_PM_BASE + 0x24) + +/** @} */ + +/** + * @name GPIO Registers + * + * @{ + */ + +#define BCM2835_GPIO_REGS_BASE (RPI_PERIPHERAL_BASE + 0x200000) + +#define BCM2835_GPIO_GPFSEL1 (BCM2835_GPIO_REGS_BASE + 0x04) +#define BCM2835_GPIO_GPSET0 (BCM2835_GPIO_REGS_BASE + 0x1C) +#define BCM2835_GPIO_GPCLR0 (BCM2835_GPIO_REGS_BASE + 0x28) +#define BCM2835_GPIO_GPLEV0 (BCM2835_GPIO_REGS_BASE + 0x34) +#define BCM2835_GPIO_GPEDS0 (BCM2835_GPIO_REGS_BASE + 0x40) +#define BCM2835_GPIO_GPREN0 (BCM2835_GPIO_REGS_BASE + 0x4C) +#define BCM2835_GPIO_GPFEN0 (BCM2835_GPIO_REGS_BASE + 0x58) +#define BCM2835_GPIO_GPHEN0 (BCM2835_GPIO_REGS_BASE + 0x64) +#define BCM2835_GPIO_GPLEN0 (BCM2835_GPIO_REGS_BASE + 0x70) +#define BCM2835_GPIO_GPAREN0 (BCM2835_GPIO_REGS_BASE + 0x7C) +#define BCM2835_GPIO_GPAFEN0 (BCM2835_GPIO_REGS_BASE + 0x88) +#define BCM2835_GPIO_GPPUD (BCM2835_GPIO_REGS_BASE + 0x94) +#define BCM2835_GPIO_GPPUDCLK0 (BCM2835_GPIO_REGS_BASE + 0x98) + +/** @} */ + +/** + * @name AUX Registers + * + * @{ + */ + +#define BCM2835_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000) + +#define AUX_ENABLES (BCM2835_AUX_BASE + 0x04) +#define AUX_MU_IO_REG (BCM2835_AUX_BASE + 0x40) +#define AUX_MU_IER_REG (BCM2835_AUX_BASE + 0x44) +#define AUX_MU_IIR_REG (BCM2835_AUX_BASE + 0x48) +#define AUX_MU_LCR_REG (BCM2835_AUX_BASE + 0x4C) +#define AUX_MU_MCR_REG (BCM2835_AUX_BASE + 0x50) +#define AUX_MU_LSR_REG (BCM2835_AUX_BASE + 0x54) +#define AUX_MU_MSR_REG (BCM2835_AUX_BASE + 0x58) +#define AUX_MU_SCRATCH (BCM2835_AUX_BASE + 0x5C) +#define AUX_MU_CNTL_REG (BCM2835_AUX_BASE + 0x60) +#define AUX_MU_STAT_REG (BCM2835_AUX_BASE + 0x64) +#define AUX_MU_BAUD_REG (BCM2835_AUX_BASE + 0x68) + +/** @} */ + +/** + * @name UART 0 (PL011) Registers + * + * @{ + */ + +#define BCM2835_UART0_BASE (RPI_PERIPHERAL_BASE + 0x201000) + +#define BCM2835_UART0_DR (BCM2835_UART0_BASE + 0x00) +#define BCM2835_UART0_RSRECR (BCM2835_UART0_BASE + 0x04) +#define BCM2835_UART0_FR (BCM2835_UART0_BASE + 0x18) +#define BCM2835_UART0_ILPR (BCM2835_UART0_BASE + 0x20) +#define BCM2835_UART0_IBRD (BCM2835_UART0_BASE + 0x24) +#define BCM2835_UART0_FBRD (BCM2835_UART0_BASE + 0x28) +#define BCM2835_UART0_LCRH (BCM2835_UART0_BASE + 0x2C) +#define BCM2835_UART0_CR (BCM2835_UART0_BASE + 0x30) +#define BCM2835_UART0_IFLS (BCM2835_UART0_BASE + 0x34) +#define BCM2835_UART0_IMSC (BCM2835_UART0_BASE + 0x38) +#define BCM2835_UART0_RIS (BCM2835_UART0_BASE + 0x3C) +#define BCM2835_UART0_MIS (BCM2835_UART0_BASE + 0x40) +#define BCM2835_UART0_ICR (BCM2835_UART0_BASE + 0x44) +#define BCM2835_UART0_DMACR (BCM2835_UART0_BASE + 0x48) +#define BCM2835_UART0_ITCR (BCM2835_UART0_BASE + 0x80) +#define BCM2835_UART0_ITIP (BCM2835_UART0_BASE + 0x84) +#define BCM2835_UART0_ITOP (BCM2835_UART0_BASE + 0x88) +#define BCM2835_UART0_TDR (BCM2835_UART0_BASE + 0x8C) + +#define BCM2835_UART0_MIS_RX 0x10 +#define BCM2835_UART0_MIS_TX 0x20 +#define BCM2835_UART0_IMSC_RX 0x10 +#define BCM2835_UART0_IMSC_TX 0x20 +#define BCM2835_UART0_FR_RXFE 0x10 +#define BCM2835_UART0_FR_TXFF 0x20 +#define BCM2835_UART0_ICR_RX 0x10 +#define BCM2835_UART0_ICR_TX 0x20 + +/** @} */ + +/** + * @name I2C (BSC) Registers + * + * @{ + */ + +#define BCM2835_I2C_BASE (RPI_PERIPHERAL_BASE + 0x804000) + +#define BCM2835_I2C_C (BCM2835_I2C_BASE + 0x00) +#define BCM2835_I2C_S (BCM2835_I2C_BASE + 0x04) +#define BCM2835_I2C_DLEN (BCM2835_I2C_BASE + 0x08) +#define BCM2835_I2C_A (BCM2835_I2C_BASE + 0x0C) +#define BCM2835_I2C_FIFO (BCM2835_I2C_BASE + 0x10) +#define BCM2835_I2C_DIV (BCM2835_I2C_BASE + 0x14) +#define BCM2835_I2C_DEL (BCM2835_I2C_BASE + 0x18) +#define BCM2835_I2C_CLKT (BCM2835_I2C_BASE + 0x1C) + +/** @} */ + +/** + * @name SPI Registers + * + * @{ + */ + +#define BCM2835_SPI_BASE (RPI_PERIPHERAL_BASE + 0x204000) + +#define BCM2835_SPI_CS (BCM2835_SPI_BASE + 0x00) +#define BCM2835_SPI_FIFO (BCM2835_SPI_BASE + 0x04) +#define BCM2835_SPI_CLK (BCM2835_SPI_BASE + 0x08) +#define BCM2835_SPI_DLEN (BCM2835_SPI_BASE + 0x0C) +#define BCM2835_SPI_LTOH (BCM2835_SPI_BASE + 0x10) +#define BCM2835_SPI_DC (BCM2835_SPI_BASE + 0x14) + +/** @} */ + +/** + * @name I2C/SPI slave BSC Registers + * + * @{ + */ + +#define BCM2835_I2C_SPI_BASE (RPI_PERIPHERAL_BASE + 0x214000) + +#define BCM2835_I2C_SPI_DR (BCM2835_I2C_SPI_BASE + 0x00) +#define BCM2835_I2C_SPI_RSR (BCM2835_I2C_SPI_BASE + 0x04) +#define BCM2835_I2C_SPI_SLV (BCM2835_I2C_SPI_BASE + 0x08) +#define BCM2835_I2C_SPI_CR (BCM2835_I2C_SPI_BASE + 0x0C) +#define BCM2835_I2C_SPI_FR (BCM2835_I2C_SPI_BASE + 0x10) +#define BCM2835_I2C_SPI_IFLS (BCM2835_I2C_SPI_BASE + 0x14) +#define BCM2835_I2C_SPI_IMSC (BCM2835_I2C_SPI_BASE + 0x18) +#define BCM2835_I2C_SPI_RIS (BCM2835_I2C_SPI_BASE + 0x1C) +#define BCM2835_I2C_SPI_MIS (BCM2835_I2C_SPI_BASE + 0x20) +#define BCM2835_I2C_SPI_ICR (BCM2835_I2C_SPI_BASE + 0x24) +#define BCM2835_I2C_SPI_DMACR (BCM2835_I2C_SPI_BASE + 0x28) +#define BCM2835_I2C_SPI_TDR (BCM2835_I2C_SPI_BASE + 0x2C) +#define BCM2835_I2C_SPI_GPUSTAT (BCM2835_I2C_SPI_BASE + 0x30) +#define BCM2835_I2C_SPI_HCTRL (BCM2835_I2C_SPI_BASE + 0x34) + +/** @} */ + +/** + * @name IRQ Registers + * + * @{ + */ + +#define BCM2835_BASE_INTC (RPI_PERIPHERAL_BASE + 0xB200) + +#define BCM2835_IRQ_BASIC (BCM2835_BASE_INTC + 0x00) +#define BCM2835_IRQ_PENDING1 (BCM2835_BASE_INTC + 0x04) +#define BCM2835_IRQ_PENDING2 (BCM2835_BASE_INTC + 0x08) +#define BCM2835_IRQ_FIQ_CTRL (BCM2835_BASE_INTC + 0x0C) +#define BCM2835_IRQ_ENABLE1 (BCM2835_BASE_INTC + 0x10) +#define BCM2835_IRQ_ENABLE2 (BCM2835_BASE_INTC + 0x14) +#define BCM2835_IRQ_ENABLE_BASIC (BCM2835_BASE_INTC + 0x18) +#define BCM2835_IRQ_DISABLE1 (BCM2835_BASE_INTC + 0x1C) +#define BCM2835_IRQ_DISABLE2 (BCM2835_BASE_INTC + 0x20) +#define BCM2835_IRQ_DISABLE_BASIC (BCM2835_BASE_INTC + 0x24) + +/** @} */ + +/** + * @name GPU Timer Registers + * + * @{ + */ + +/** + * NOTE: The GPU uses Compare registers 0 and 2 for + * it's own RTOS. 1 and 3 are available for use in + * RTEMS. + */ +#define BCM2835_GPU_TIMER_BASE (RPI_PERIPHERAL_BASE + 0x3000) + +#define BCM2835_GPU_TIMER_CS (BCM2835_GPU_TIMER_BASE + 0x00) +#define BCM2835_GPU_TIMER_CS_M0 0x00000001 +#define BCM2835_GPU_TIMER_CS_M1 0x00000002 +#define BCM2835_GPU_TIMER_CS_M2 0x00000004 +#define BCM2835_GPU_TIMER_CS_M3 0x00000008 +#define BCM2835_GPU_TIMER_CLO (BCM2835_GPU_TIMER_BASE + 0x04) +#define BCM2835_GPU_TIMER_CHI (BCM2835_GPU_TIMER_BASE + 0x08) +#define BCM2835_GPU_TIMER_C0 (BCM2835_GPU_TIMER_BASE + 0x0C) +#define BCM2835_GPU_TIMER_C1 (BCM2835_GPU_TIMER_BASE + 0x10) +#define BCM2835_GPU_TIMER_C2 (BCM2835_GPU_TIMER_BASE + 0x14) +#define BCM2835_GPU_TIMER_C3 (BCM2835_GPU_TIMER_BASE + 0x18) + +/** @} */ + +/** + * @name EMMC Registers + * + * @{ + */ + +/** + * NOTE: Since the SD controller follows the SDHCI standard, + * the rtems-libbsd tree already provides the remaining registers. + */ + +#define BCM2835_EMMC_BASE (RPI_PERIPHERAL_BASE + 0x300000) + +/** @} */ + +/** +* @name Mailbox Registers +* +* @{ +*/ + +#define BCM2835_MBOX_BASE (RPI_PERIPHERAL_BASE+0xB880) + +#define BCM2835_MBOX_PEEK (BCM2835_MBOX_BASE+0x10) +#define BCM2835_MBOX_READ (BCM2835_MBOX_BASE+0x00) +#define BCM2835_MBOX_WRITE (BCM2835_MBOX_BASE+0x20) +#define BCM2835_MBOX_STATUS (BCM2835_MBOX_BASE+0x18) +#define BCM2835_MBOX_SENDER (BCM2835_MBOX_BASE+0x14) +#define BCM2835_MBOX_CONFIG (BCM2835_MBOX_BASE+0x1C) + +#define BCM2835_MBOX_FULL 0x80000000 +#define BCM2835_MBOX_EMPTY 0x40000000 + +/** @} */ + +/** +* @name Mailbox Channels +* +* @{ +*/ + +/* Power Manager channel */ +#define BCM2835_MBOX_CHANNEL_PM 0 +/* Framebuffer channel */ +#define BCM2835_MBOX_CHANNEL_FB 1 + /* Virtual UART channel */ +#define BCM2835_MBOX_CHANNEL_VUART 2 + /* VCHIQ channel */ +#define BCM2835_MBOX_CHANNEL_VCHIQ 3 + /* LEDs channel */ +#define BCM2835_MBOX_CHANNEL_LED 4 + /* Button channel */ +#define BCM2835_MBOX_CHANNEL_BUTTON 5 + /* Touch screen channel */ +#define BCM2835_MBOX_CHANNEL_TOUCHS 6 +/* Property tags (ARM <-> VC) channel */ +#define BCM2835_MBOX_CHANNEL_PROP_AVC 8 + /* Property tags (VC <-> ARM) channel */ +#define BCM2835_MBOX_CHANNEL_PROP_VCA 9 + +/** @} */ + +/** +* @name USB Registers +* +* @{ +*/ + +#define BCM2835_USB_BASE (RPI_PERIPHERAL_BASE + 0x980000) /* DTC_OTG USB controller */ + +/** @} */ + +/** + * @name Raspberry Pi 2 CPU Cores Local Peripherals + * + * @{ + */ + +#define BCM2836_CORE_LOCAL_PERIPH_BASE 0x40000000 +#define BCM2836_CORE_LOCAL_PERIPH_SIZE 0x00040000 + +/** @} */ + +/** + * @name Raspberry Pi 2 Mailbox Register Defines + * + * @{ + */ + +#define BCM2836_MAILBOX_0_WRITE_SET_BASE 0x40000080 +#define BCM2836_MAILBOX_1_WRITE_SET_BASE 0x40000084 +#define BCM2836_MAILBOX_2_WRITE_SET_BASE 0x40000088 +#define BCM2836_MAILBOX_3_WRITE_SET_BASE 0x4000008C +#define BCM2836_MAILBOX_0_READ_CLEAR_BASE 0x400000C0 +#define BCM2836_MAILBOX_1_READ_CLEAR_BASE 0x400000C4 +#define BCM2836_MAILBOX_2_READ_CLEAR_BASE 0x400000C8 +#define BCM2836_MAILBOX_3_READ_CLEAR_BASE 0x400000CC + +/** @} */ + +/** + * @name Raspberry Pi 2 Core Timer + * + * @{ + */ + +#define BCM2836_CORE_TIMER_CTRL 0x40000000 + +#define BCM2836_CORE_TIMER_CTRL_APB_CLK 0x00000100 +#define BCM2836_CORE_TIMER_CTRL_INC_2 0x00000200 + +#define BCM2836_CORE_TIMER_PRESCALER 0x40000008 + +#define BCM2836_CORE_TIMER_LS32 0x4000001C +#define BCM2836_CORE_TIMER_MS32 0x40000020 + +/** @} */ + +/** + * @name Raspberry Pi 2 Local Timer + * + * @{ + */ + +#define BCM2836_LOCAL_TIMER_CTRL 0x40000034 + +#define BCM2836_LOCAL_TIMER_CTRL_IRQ_FLAG 0x80000000 +#define BCM2836_LOCAL_TIMER_CTRL_IRQ_EN 0x20000000 +#define BCM2836_LOCAL_TIMER_CTRL_TIMER_EN 0x10000000 +#define BCM2836_LOCAL_TIMER_RELOAD 0x0FFFFFFF + +#define BCM2836_LOCAL_TIMER_IRQ_RELOAD 0x40000038 + +#define BCM2836_LOCAL_TIMER_IRQ_CLEAR 0x80000000 +#define BCM2836_LOCAL_TIMER_RELOAD_NOW 0x40000000 + +#define BCM2836_LOCAL_TIMER_IRQ_ROUTING 0x40000024 +#define BCM2836_LOCAL_TIMER_ROU_CORE0_IRQ 0x00 +#define BCM2836_LOCAL_TIMER_ROU_CORE1_IRQ 0x01 +#define BCM2836_LOCAL_TIMER_ROU_CORE2_IRQ 0x02 +#define BCM2836_LOCAL_TIMER_ROU_CORE3_IRQ 0x03 +#define BCM2836_LOCAL_TIMER_ROU_CORE0_FIQ 0x04 +#define BCM2836_LOCAL_TIMER_ROU_CORE1_FIQ 0x05 +#define BCM2836_LOCAL_TIMER_ROU_CORE2_FIQ 0x06 +#define BCM2836_LOCAL_TIMER_ROU_CORE3_FIQ 0x07 + +/** @} */ + +/** + * @name Raspberry Pi 2 IRQ Routing + * + * @{ + */ + +#define BCM2836_GPU_IRQ_ROUTING 0x4000000C + +#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE0 0x00000000 +#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE1 0x00000001 +#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE2 0x00000002 +#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE4 0x00000003 + +#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE0 0x00000000 +#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE1 0x00000004 +#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE2 0x00000008 +#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C + +#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C + + +/** @} */ + +/** + * @name Raspberry Pi 2 Interrupt Register Defines + * + * @{ + */ + +/* Timers interrupt control registers */ +#define BCM2836_CORE0_TIMER_IRQ_CTRL_BASE 0x40000040 +#define BCM2836_CORE1_TIMER_IRQ_CTRL_BASE 0x40000044 +#define BCM2836_CORE2_TIMER_IRQ_CTRL_BASE 0x40000048 +#define BCM2836_CORE3_TIMER_IRQ_CTRL_BASE 0x4000004C + +#define BCM2836_CORE_TIMER_IRQ_CTRL(cpuidx) \ + (BCM2836_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx)) + +/* + * Where to route timer interrupt to, IRQ/FIQ + * Setting both the IRQ and FIQ bit gives an FIQ + */ +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_IRQ 0x01 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_IRQ 0x02 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_IRQ 0x04 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_IRQ 0x08 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_FIQ 0x10 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_FIQ 0x20 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_FIQ 0x40 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_FIQ 0x80 + +/* CPU mailbox registers */ +#define BCM2836_MAILBOX_IRQ_CTRL_BASE 0x40000050 +#define BCM2836_MAILBOX_IRQ_CTRL(cpuidx) \ + (BCM2836_MAILBOX_IRQ_CTRL_BASE + 0x4 * (cpuidx)) +/* + * Where to route mailbox interrupt to, IRQ/FIQ + * Setting both the IRQ and FIQ bit gives an FIQ + */ +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_IRQ 0x01 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_IRQ 0x02 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_IRQ 0x04 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_IRQ 0x08 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_FIQ 0x10 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_FIQ 0x20 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_FIQ 0x40 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_FIQ 0x80 + +#define BCM2836_IRQ_SOURCE_REG_BASE 0x40000060 +#define BCM2836_IRQ_SOURCE_REG(cpuidx) \ + (BCM2836_IRQ_SOURCE_REG_BASE + 0x4 * (cpuidx)) + +#define BCM2836_FIQ_SOURCE_REG_BASE 0x40000070 +#define BCM2836_FIQ_SOURCE_REG(cpuidx) \ + (BCM2836_FIQ_SOURCE_REG_BASE + 0x4 * (cpuidx)) + +#define BCM2836_IRQ_SOURCE_TIMER0 0x00000001 +#define BCM2836_IRQ_SOURCE_TIMER1 0x00000002 +#define BCM2836_IRQ_SOURCE_TIMER2 0x00000004 +#define BCM2836_IRQ_SOURCE_TIMER3 0x00000008 +#define BCM2836_IRQ_SOURCE_MBOX0 0x00000010 +#define BCM2836_IRQ_SOURCE_MBOX1 0x00000020 +#define BCM2836_IRQ_SOURCE_MBOX2 0x00000040 +#define BCM2836_IRQ_SOURCE_MBOX3 0x00000080 +#define BCM2836_IRQ_SOURCE_GPU 0x00000100 +#define BCM2836_IRQ_SOURCE_PMU 0x00000200 +#define BCM2836_IRQ_SOURCE_LOCAL_TIMER 0x00000800 + +/** @} */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/rpi-fb.h b/bsps/arm/raspberrypi/include/bsp/rpi-fb.h new file mode 100644 index 0000000000..4f3c07fea2 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/rpi-fb.h @@ -0,0 +1,55 @@ +/** + * @file + * + * @ingroup raspberrypi_fb + * + * @brief framebuffer support and setup + * + */ + +/* + * Copyright (c) 2015 Yang Qiao + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_FB_H +#define LIBBSP_ARM_RASPBERRYPI_FB_H + +#include + +/** + * @defgroup raspberrypi_fb + * + * @ingroup arm_raspberrypi + * + * @brief Framebuffer support and setup + * + * @{ + */ + +enum rpi_fb_init_result { + RPI_FB_INIT_OK = 0, + RPI_FB_INIT_ALREADY_INITIALIZED = 1, + RPI_FB_INIT_GENERIC_ERROR = -1, + RPI_FB_INIT_NO_DISPLAY = -2, + RPI_FB_INIT_CMDLINE_BAD_FORMAT = -3, + RPI_FB_INIT_CMDLINE_DONT_INIT = -4, + RPI_FB_INIT_CMDLINE_NO_MODE_REQ = -5, + RPI_FB_INIT_MODE_PROBE_ERROR = -6, + RPI_FB_INIT_SETUP_FAILED = -7, + RPI_FB_INIT_START_ADDR_UNKNOWN = -8, +}; + +int rpi_fb_init( void ); +int rpi_get_fix_screen_info( struct fb_fix_screeninfo *info ); +int rpi_get_var_screen_info( struct fb_var_screeninfo *info ); +bool rpi_fb_hdmi_is_present( void ); + +/** @} */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_FB_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/rpi-gpio.h b/bsps/arm/raspberrypi/include/bsp/rpi-gpio.h new file mode 100644 index 0000000000..82ba4b1f2a --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/rpi-gpio.h @@ -0,0 +1,70 @@ +/** + * @file rpi-gpio.h + * + * @ingroup raspberrypi_gpio + * + * @brief Raspberry Pi specific GPIO definitions. + */ + +/* + * Copyright (c) 2015 Andre Marques + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_RPI_GPIO_H +#define LIBBSP_ARM_RASPBERRYPI_RPI_GPIO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Raspberry Pi GPIO functions. + */ +#define RPI_DIGITAL_IN 0 +#define RPI_DIGITAL_OUT 1 +#define RPI_ALT_FUNC_0 4 +#define RPI_ALT_FUNC_1 5 +#define RPI_ALT_FUNC_2 6 +#define RPI_ALT_FUNC_3 7 +#define RPI_ALT_FUNC_4 3 +#define RPI_ALT_FUNC_5 2 +#define RPI_ALT_FUNC_MASK 7 + +/** + * @brief Setups a JTAG interface. + * + * @retval RTEMS_SUCCESSFUL JTAG interface successfully configured. + * @retval * At least one of the required pins is currently + * occupied, @see rtems_gpio_request_pin_group(). + */ +extern rtems_status_code rpi_gpio_select_jtag(void); + +/** + * @brief Setups a SPI interface. + * + * @retval RTEMS_SUCCESSFUL SPI interface successfully configured. + * @retval * At least one of the required pins is currently + * occupied, @see rtems_gpio_request_pin_group(). + */ +extern rtems_status_code rpi_gpio_select_spi(void); + +/** + * @brief Setups a I2C interface. + * + * @retval RTEMS_SUCCESSFUL I2C interface successfully configured. + * @retval * At least one of the required pins is currently + * occupied, @see rtems_gpio_request_pin_group(). + */ +extern rtems_status_code rpi_gpio_select_i2c(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_RPI_GPIO_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/spi.h b/bsps/arm/raspberrypi/include/bsp/spi.h new file mode 100644 index 0000000000..1bbbc6d2a4 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/spi.h @@ -0,0 +1,77 @@ +/** + * @file spi.h + * + * @ingroup raspberrypi_spi + * + * @brief Raspberry Pi specific SPI definitions. + */ + +/* + * Copyright (c) 2014-2015 Andre Marques + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_SPI_H +#define LIBBSP_ARM_RASPBERRYPI_SPI_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @name SPI constants. + * + * @{ + */ + +/** + * @brief GPU processor core clock rate in Hz. + * + * Unless configured otherwise on a "config.txt" file present on the SD card + * the GPU defaults to 250 MHz. Currently only 250 MHz is supported. + */ + +/* TODO: It would be nice if this value could be probed at startup, probably + * using the Mailbox interface since the usual way of setting this on + * the hardware is through a "config.txt" text file on the SD card. + * Having this setup on the configure.ac script would require changing + * the same setting on two different places. */ +#define GPU_CORE_CLOCK_RATE 250000000 + +/** @} */ + +/** + * @name SPI directives. + * + * @{ + */ + +/** + * @brief Setups the Raspberry Pi SPI bus (located on the GPIO header) + * on the "/dev/spi" device file, and registers the bus on the + * libi2c API. + * + * @param[in] bidirectional_mode If TRUE sets the SPI bus to use 2-wire SPI, + * where the MOSI data line doubles as the + * slave out (SO) and slave in (SI) data lines. + * If FALSE the bus defaults to the usual + * 3-wire SPI, with 2 separate data lines + * (MOSI and MISO). + * + * @retval Returns libi2c bus number. + * @retval <0 Could not register the bus. See @see rtems_libi2c_register_bus(). + */ +extern int rpi_spi_init(bool bidirectional_mode); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_SPI_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/usart.h b/bsps/arm/raspberrypi/include/bsp/usart.h new file mode 100644 index 0000000000..491392b1f7 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/usart.h @@ -0,0 +1,43 @@ +/** + * @file + * + * @ingroup raspberrypi_usart + * + * @brief USART support. + */ + + +/** + * @defgroup raspberrypi_usart USART Support + * + * @ingroup arm_raspberrypi + * + * @brief Universal Synchronous/Asynchronous Receiver/Transmitter (USART) Support + */ + +/* + * Copyright (c) 2013 Alan Cudmore. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_USART_H +#define LIBBSP_ARM_RASPBERRYPI_USART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define USART0_DEFAULT_BAUD 115000 + +extern const console_fns bcm2835_usart_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_USART_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/vc.h b/bsps/arm/raspberrypi/include/bsp/vc.h new file mode 100644 index 0000000000..e863732cd5 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/vc.h @@ -0,0 +1,157 @@ +/** + * @file + * + * @ingroup raspberrypi_vc + * + * @brief video core support. + * + */ + +/* + * Copyright (c) 2015 Yang Qiao + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_VC_H +#define LIBBSP_ARM_RASPBERRYPI_VC_H + +/** + * @defgroup raspberrypi_vc Register Definitions + * + * @ingroup arm_raspberrypi + * + * @brief Register Definitions + * + * @{ + */ + +typedef struct { + uint32_t width; + uint32_t height; +} bcm2835_get_display_size_entries; + +int bcm2835_mailbox_get_display_size( + bcm2835_get_display_size_entries *_entries ); + +typedef enum { + bcm2835_mailbox_pixel_order_bgr = 0, + bcm2835_mailbox_pixel_order_rgb = 1 +} bcm2835_pixel_order; + +typedef enum { + bcm2835_mailbox_alpha_mode_0_opaque = 0, + bcm2835_mailbox_alpha_mode_0_transparent = 1, + bcm2835_mailbox_alpha_mode_ignored = 2 +} bcm2835_alpha_mode; + +typedef struct { + uint32_t xres; + uint32_t yres; + uint32_t xvirt; + uint32_t yvirt; + uint32_t depth; + bcm2835_pixel_order pixel_order; + bcm2835_alpha_mode alpha_mode; + uint32_t voffset_x; + uint32_t voffset_y; + uint32_t overscan_left; + uint32_t overscan_right; + uint32_t overscan_top; + uint32_t overscan_bottom; + uint32_t base; + size_t size; + uint32_t pitch; +} bcm2835_init_frame_buffer_entries; + +int bcm2835_mailbox_init_frame_buffer( + bcm2835_init_frame_buffer_entries *_entries ); + +typedef struct { + uint32_t pitch; +} bcm2835_get_pitch_entries; + +int bcm2835_mailbox_get_pitch( bcm2835_get_pitch_entries *_entries ); + +typedef struct { + char cmdline[ 1024 ]; +} bcm2835_get_cmdline_entries; + +int bcm2835_mailbox_get_cmdline( bcm2835_get_cmdline_entries *_entries ); + +typedef enum { + bcm2835_mailbox_power_udid_sd_card = 0x00000000u, + bcm2835_mailbox_power_udid_uart0 = 0x00000001u, + bcm2835_mailbox_power_udid_uart1 = 0x00000002u, + bcm2835_mailbox_power_udid_usb_hcd = 0x00000003u, + bcm2835_mailbox_power_udid_i2c0 = 0x00000004u, + bcm2835_mailbox_power_udid_i2c1 = 0x00000005u, + bcm2835_mailbox_power_udid_i2c2 = 0x00000006u, + bcm2835_mailbox_power_udid_spi = 0x00000007u, + bcm2835_mailbox_power_udid_ccp2tx = 0x00000008u, +} bcm2835_power_device_id; + +typedef struct { + bcm2835_power_device_id dev_id; + uint32_t state; +} bcm2835_set_power_state_entries; + +#define BCM2835_MAILBOX_SET_POWER_STATE_REQ_ON ( 1 << 0 ) +#define BCM2835_MAILBOX_SET_POWER_STATE_REQ_WAIT ( 1 << 1 ) +#define BCM2835_MAILBOX_POWER_STATE_ON ( 1 << 0 ) +#define BCM2835_MAILBOX_POWER_STATE_NODEV ( 1 << 1 ) +int bcm2835_mailbox_set_power_state( bcm2835_set_power_state_entries *_entries ); + +int bcm2835_mailbox_get_power_state( bcm2835_set_power_state_entries *_entries ); + +typedef struct { + uint32_t base; + size_t size; +} bcm2835_get_arm_memory_entries; + +int bcm2835_mailbox_get_arm_memory( bcm2835_get_arm_memory_entries *_entries ); + +typedef struct { + uint32_t base; + size_t size; +} bcm2835_get_vc_memory_entries; + +int bcm2835_mailbox_get_vc_memory( bcm2835_get_vc_memory_entries *_entries ); + +typedef struct { + uint32_t fw_rev; +} bcm2835_mailbox_get_fw_rev_entries; + +int bcm2835_mailbox_get_firmware_revision( + bcm2835_mailbox_get_fw_rev_entries *_entries ); + +typedef struct { + uint32_t spec; +} bcm2835_get_board_spec_entries; + +int bcm2835_mailbox_get_board_model( bcm2835_get_board_spec_entries *_entries ); + +int bcm2835_mailbox_get_board_revision( + bcm2835_get_board_spec_entries *_entries ); + +typedef struct { + uint64_t board_serial; +} bcm2835_get_board_serial_entries; + +int bcm2835_mailbox_get_board_serial( + bcm2835_get_board_serial_entries *_entries ); + +typedef struct { + uint32_t clock_id; + uint32_t clock_rate; +} bcm2835_get_clock_rate_entries; + +int bcm2835_mailbox_get_clock_rate( + bcm2835_get_clock_rate_entries *_entries ); +/** @} */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_VC_H */ diff --git a/bsps/arm/raspberrypi/include/tm27.h b/bsps/arm/raspberrypi/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/raspberrypi/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/realview-pbx-a9/headers.am b/bsps/arm/realview-pbx-a9/headers.am new file mode 100644 index 0000000000..be4dc1aeb4 --- /dev/null +++ b/bsps/arm/realview-pbx-a9/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/realview-pbx-a9/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/realview-pbx-a9/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/realview-pbx-a9/include/bsp/irq.h diff --git a/bsps/arm/realview-pbx-a9/include/bsp.h b/bsps/arm/realview-pbx-a9/include/bsp.h new file mode 100644 index 0000000000..4423984e47 --- /dev/null +++ b/bsps/arm/realview-pbx-a9/include/bsp.h @@ -0,0 +1,67 @@ +/** + * @file + * + * @ingroup arm_realview-pbx-a9 + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_H +#define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_HAS_FRAME_BUFFER 1 + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_ARM_A9MPCORE_SCU_BASE 0x1f000000 + +#define BSP_ARM_GIC_CPUIF_BASE 0x1f000100 + +#define BSP_ARM_A9MPCORE_GT_BASE 0x1f000200 + +#define BSP_ARM_A9MPCORE_PT_BASE 0x1f000600 + +#define BSP_ARM_GIC_DIST_BASE 0x1f001000 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_REALVIEW_PBX_A9_BSP_H */ + +/** + * @defgroup arm_realview-pbx-a9 Realview PBX-A9 + * + * @ingroup bsp_arm + * + * @brief Realview PBX-A9 support package + * + */ diff --git a/bsps/arm/realview-pbx-a9/include/bsp/irq.h b/bsps/arm/realview-pbx-a9/include/bsp/irq.h new file mode 100644 index 0000000000..3c9790e9ef --- /dev/null +++ b/bsps/arm/realview-pbx-a9/include/bsp/irq.h @@ -0,0 +1,102 @@ +/** + * @file + * + * @ingroup realview-pbx-a9_interrupt + * + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_REALVIEW_PBX_A9_IRQ_H +#define LIBBSP_ARM_REALVIEW_PBX_A9_IRQ_H + +#ifndef ASM + +#include +#include + +#include +#include + +/** + * @defgroup realview-pbx-a9_interrupt Interrrupt Support + * + * @ingroup arm_realview-pbx-a9 + * + * @brief Interrupt support. + */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define RVPBXA9_IRQ_WATCHDOG_0 32 +#define RVPBXA9_IRQ_SW_IRQ 33 +#define RVPBXA9_IRQ_TIMER_0_1 36 +#define RVPBXA9_IRQ_TIMER_2_3 37 +#define RVPBXA9_IRQ_GPIO_0 38 +#define RVPBXA9_IRQ_GPIO_1 39 +#define RVPBXA9_IRQ_GPIO_2 40 +#define RVPBXA9_IRQ_RTC 42 +#define RVPBXA9_IRQ_SSP 43 +#define RVPBXA9_IRQ_UART_0 44 +#define RVPBXA9_IRQ_UART_1 45 +#define RVPBXA9_IRQ_UART_2 46 +#define RVPBXA9_IRQ_UART_3 47 +#define RVPBXA9_IRQ_SCI 48 +#define RVPBXA9_IRQ_MCI_A 49 +#define RVPBXA9_IRQ_MCI_B 50 +#define RVPBXA9_IRQ_AACI 51 +#define RVPBXA9_IRQ_KMI0 52 +#define RVPBXA9_IRQ_KMI1 53 +#define RVPBXA9_IRQ_CLCD 55 +#define RVPBXA9_IRQ_DMAC 56 +#define RVPBXA9_IRQ_PWRFAIL 57 +#define RVPBXA9_IRQ_CF_INT 59 +#define RVPBXA9_IRQ_ETHERNET 60 +#define RVPBXA9_IRQ_USB 61 +#define RVPBXA9_IRQ_T1_INT_0 64 +#define RVPBXA9_IRQ_T1_INT_1 65 +#define RVPBXA9_IRQ_T1_INT_2 66 +#define RVPBXA9_IRQ_T1_INT_3 67 +#define RVPBXA9_IRQ_T1_INT_4 68 +#define RVPBXA9_IRQ_T1_INT_5 69 +#define RVPBXA9_IRQ_T1_INT_6 70 +#define RVPBXA9_IRQ_T1_INT_7 71 +#define RVPBXA9_IRQ_WATCHDOG_1 72 +#define RVPBXA9_IRQ_TIMER_4_5 73 +#define RVPBXA9_IRQ_TIMER_6_7 74 +#define RVPBXA9_IRQ_PCI_INTR 80 +#define RVPBXA9_IRQ_P_NMI 81 +#define RVPBXA9_IRQ_P_NINT_0 82 +#define RVPBXA9_IRQ_P_NINT_1 83 +#define RVPBXA9_IRQ_P_NINT_2 84 +#define RVPBXA9_IRQ_P_NINT_3 85 +#define RVPBXA9_IRQ_P_NINT_4 86 +#define RVPBXA9_IRQ_P_NINT_5 87 +#define RVPBXA9_IRQ_P_NINT_6 88 +#define RVPBXA9_IRQ_P_NINT_7 89 + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 89 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_REALVIEW_PBX_A9_IRQ_H */ diff --git a/bsps/arm/realview-pbx-a9/include/tm27.h b/bsps/arm/realview-pbx-a9/include/tm27.h new file mode 100644 index 0000000000..c336d8d310 --- /dev/null +++ b/bsps/arm/realview-pbx-a9/include/tm27.h @@ -0,0 +1,41 @@ +/** + * @file + * + * @ingroup realview-pbx-a9_tm27 + * + * @brief GIC tmtests/tm27 support. + */ + + +/** + * @defgroup realview-pbx-a9_tm27 GIC tmtests/tm27 + * + * @ingroup arm_realview-pbx-a9 + * + * @brief GIC tmtests/tm27 support. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +#endif /* __tm27_h */ diff --git a/bsps/arm/rtl22xx/headers.am b/bsps/arm/rtl22xx/headers.am new file mode 100644 index 0000000000..70f14bf3ed --- /dev/null +++ b/bsps/arm/rtl22xx/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/rtl22xx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/rtl22xx/include/lpc22xx.h +include_HEADERS += ../../../../../../bsps/arm/rtl22xx/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/rtl22xx/include/bsp/irq.h diff --git a/bsps/arm/rtl22xx/include/bsp.h b/bsps/arm/rtl22xx/include/bsp.h new file mode 100644 index 0000000000..9b376daf0d --- /dev/null +++ b/bsps/arm/rtl22xx/include/bsp.h @@ -0,0 +1,226 @@ +/** + * @file + * @ingroup arm_rtl22xx + * @brief Global BSP definitions. + */ + +/* + * Philips LPC22XX/LPC21xx BSP header file + * + * by Ray,Xu + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ +#ifndef LIBBSP_ARM_RTL22XX_BSP_H +#define LIBBSP_ARM_RTL22XX_BSP_H + +#include +#include + +/** + * @defgroup arm_rtl22xx RTL22XX Support + * @ingroup bsp_arm + * @brief RTL22XX Support Package + * @{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION + +#define CONFIG_ARM_CLK 60000000L +/* cclk=cco/(2*P) */ +/* cco = cclk*2*P */ + +/** @brief system clk frequecy,<=60Mhz, defined in system configuration */ +#define LPC22xx_Fcclk CONFIG_ARM_CLK + +/* Fcco 156M~320Mhz*/ +/** @brief system clk frequecy,<=60Mhz, defined in system configuration */ +#define LPC22xx_Fcclk CONFIG_ARM_CLK +#define LPC22xx_Fcco LPC22xx_Fcclk * 4 +/** @brief VPB clk frequency,1,1/2,1/4 times of Fcclk */ +#define LPC22xx_Fpclk (LPC22xx_Fcclk /4) *1 + + + +/** + * @name Fcclk range: 10MHz ~ MCU allowed frequency + * @{ + */ + +#define Fcclk_MIN 10000000L +#define Fcclk_MAX 60000000L + +/** @} */ + +/** + * @name Fcco range: 156MHz ~ 320MHz + * @{ + */ + +#define Fcco_MIN 156000000L +#define Fcco_MAX 320000000L + +/** @} */ + +#define PLLFEED_DATA1 0xAA +#define PLLFEED_DATA2 0x55 + +/** + * @name PLL PLLCON register bit descriptions + * @{ + */ + +#define PLLCON_ENABLE_BIT 0 +#define PLLCON_CONNECT_BIT 1 + +/** @} */ + +/** + * @name PLL PLLSTAT register bit descriptions + * @{ + */ + +#define PLLSTAT_ENABLE_BIT 8 +#define PLLSTAT_CONNECT_BIT 9 +#define PLLSTAT_LOCK_BIT 10 + +/** @} */ + +/** + * @name PM Peripheral Type + * @{ + */ + +#define PC_TIMER0 0x2 +#define PC_TIMER1 0x4 +#define PC_UART0 0x8 +#define PC_UART1 0x10 +#define PC_PWM0 0x20 +#define PC_I2C 0x80 +#define PC_SPI0 0x100 +#define PC_RTC 0x200 + +/** @} */ + +/** @brief OSC [Hz] */ +#define FOSC 11059200 +/** @brief Core clk [Hz] */ +#define FCCLK FOSC<<2 + +/** + * @name System Configure + * @{ + */ + +/** @brief osc freq,10MHz~25MHz, change to a real one if needed */ +#define Fosc 11059200 +/** @brief system freq 2^n time of Fosc(1~32) <=60MHZ */ +#define Fcclk (Fosc << 2) +/** @brief CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz */ +#define Fcco (Fcclk <<2) +/** @brief VPB freq only(Fcclk / 4) 1~4 */ +#define Fpclk (Fcclk >>2) * 1 +/* This was M. That is a BAD BAD public constant. I renamed it to + * JOEL_M so it wouldn't conflict with user code. If you can find + * a better name, fix this. But nothing I found uses it. + */ + +/** @} */ + +#define JOEL_M Fcclk / Fosc +#define P_min Fcco_MIN / (2*Fcclk) + 1; +#define P_max Fcco_MAX / (2*Fcclk); + +#define UART_BPS 115200 + +/** @brief Time Precision time [us] */ +#define TIMER_PRECISION 10 + +/** @brief I2C Speed [bit/s] */ +#define I2CSPEED 20000 // 20 Kbit/s + +/** + * @name Uarts buffers size + * @{ + */ + +#define RXBUFSIZE 32 +#define TXBUFSIZE 32 + +/** @} */ + +/** @brief SPI Speed [bit/s] */ +#define SPISPEED 1500000 // 1.5 Mbit/s +/** @brief SPI EEPROM CS pin + * + * (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface) + */ +#define SPI_CS_PIN P0_13 +#define SPI_CS_PIN_FUNC PINSEL0_bit.SPI_CS_PIN + +/** + * @name Flash definition + * @{ + */ + +//#define RTL22XX_FLASH_SIZE (0x200000-RTL22XX_FLASH_BOOT) // Total area of Flash region in words 8 bit +/** @brief Total area of Flash region in words 8 bit */ +#define RTL22XX_FLASH_SIZE (0x80000-RTL22XX_FLASH_BOOT) +//#define RTL22XX_FLASH_SIZE (0x80000-RTL22XX_FLASH_BOOT) // Total area of Flash region in words 8 bit +#define RTL22XX_FLASH_BEGIN 0x80000000 +/** @brief First 0x8000 bytes reserved for boot loader etc. */ +#define RTL22XX_FLASH_BASE (RTL22XX_FLASH_BEGIN+RTL22XX_FLASH_BOOT) + +/** @} */ + +/** + * @name SRAM definition + * @{ + */ + +/** @brief Total area of Flash region in words 8 bit */ +#define SRAM_SIZE 0x100000 +/** @brief First 0x8000 bytes reserved for boot loader etc. */ +#define SRAM_BASE 0x81000000 + +/** @} */ + +/** @brief CS8900A definition */ +#define CS8900A_BASE 0x82000000 +/** @brief RTL8019AS definition */ +#define RTL8019AS_BASE 0x82000000 + +struct rtems_bsdnet_ifconfig; +int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, + int attaching); + +/** + * @name Network driver configuration + * @{ + */ + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach + +/** @} */ + +/* + * Prototypes for methods used across file boundaries in the BSP. + */ +extern void UART0_Ini(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ diff --git a/bsps/arm/rtl22xx/include/bsp/irq.h b/bsps/arm/rtl22xx/include/bsp/irq.h new file mode 100644 index 0000000000..31825ca56e --- /dev/null +++ b/bsps/arm/rtl22xx/include/bsp/irq.h @@ -0,0 +1,71 @@ +/* + * Interrupt handler Header file + * + * Copyright (c) 2010 embedded brains GmbH. + * + * Copyright (c) 2006 by Ray to support LPC ARM + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __IRQ_H__ +#define __IRQ_H__ + +#ifndef __asm__ + +#include +#include +#include + +#endif /* __asm__ */ + +/* possible interrupt sources on the LPC22xx */ +#define LPC22xx_INTERRUPT_WDINT 0 /* Watchdog int. 0 */ +#define LPC22xx_INTERRUPT_RSV0 1 /* Reserved int. 1 */ +#define LPC22xx_INTERRUPT_DBGRX 2 /* Embedded ICE DbgCommRx receive */ +#define LPC22xx_INTERRUPT_DBGTX 3 /* Embedded ICE DbgCommRx Transmit*/ +#define LPC22xx_INTERRUPT_TIMER0 4 /* Timer 0 */ +#define LPC22xx_INTERRUPT_TIMER1 5 /* Timer 1 */ +#define LPC22xx_INTERRUPT_UART0 6 /* UART 0 */ +#define LPC22xx_INTERRUPT_UART1 7 /* UART 1 */ +#define LPC22xx_INTERRUPT_PWM0 8 /* PWM */ +#define LPC22xx_INTERRUPT_I2C 9 /* I2C */ +#define LPC22xx_INTERRUPT_SPI0 10 /* SPI0 */ +#define LPC22xx_INTERRUPT_SPI1 11 /* SPI1 */ +#define LPC22xx_INTERRUPT_PLL 12 /* PLL */ +#define LPC22xx_INTERRUPT_RTC 13 /* RTC */ +#define LPC22xx_INTERRUPT_EINT0 14 /* Externel Interrupt 0 */ +#define LPC22xx_INTERRUPT_EINT1 15 /* Externel Interrupt 1 */ +#define LPC22xx_INTERRUPT_EINT2 16 /* Externel Interrupt 2 */ +#define LPC22xx_INTERRUPT_EINT3 17 /* Externel Interrupt 3 */ +#define LPC22xx_INTERRUPT_ADC 18 /* AD Converter */ +/* Following interrupt used by lpc229x */ +#define LPC22xx_INTERRUPT_CANERR 19 /* CAN LUTerr interrupt */ +#define LPC22xx_INTERRUPT_CAN1TX 20 /* CAN1 Tx interrupt */ +#define LPC22xx_INTERRUPT_CAN1RX 21 /* CAN1 Rx interrupt */ +#define LPC22xx_INTERRUPT_CAN2TX 22 /* CAN2 Tx interrupt */ +#define LPC22xx_INTERRUPT_CAN2RX 23 /* CAN2 Rx interrupt */ +#define LPC22xx_INTERRUPT_CAN3TX 24 /* CAN1 Tx interrupt */ +#define LPC22xx_INTERRUPT_CAN3RX 25 /* CAN1 Rx interrupt */ +#define LPC22xx_INTERRUPT_CAN4TX 26 /* CAN2 Tx interrupt */ +#define LPC22xx_INTERRUPT_CAN4RX 27 /* CAN2 Rx interrupt */ +#define BSP_MAX_INT 28 + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) + +#define UNDEFINED_INSTRUCTION_VECTOR_ADDR (*(u_long *)0x00000004L) +#define SOFTWARE_INTERRUPT_VECTOR_ADDR (*(u_long *)0x00000008L) +#define PREFETCH_ABORT_VECTOR_ADDR (*(u_long *)0x0000000CL) +#define DATA_ABORT_VECTOR_ADDR (*(u_long *)0x00000010L) +#define IRQ_VECTOR_ADDR (*(u_long *)0x00000018L) +#define FIQ_VECTOR_ADDR (*(u_long *)0x0000001CL) + +#define DATA_ABORT_ISR_ADDR (*(u_long *)0x00000030L) +#define IRQ_ISR_ADDR (*(u_long *)0x00000038L) +#define FIQ_ISR_ADDR (*(u_long *)0x0000003CL) + +#endif /* __IRQ_H__ */ diff --git a/bsps/arm/rtl22xx/include/lpc22xx.h b/bsps/arm/rtl22xx/include/lpc22xx.h new file mode 100644 index 0000000000..babaf8343d --- /dev/null +++ b/bsps/arm/rtl22xx/include/lpc22xx.h @@ -0,0 +1,475 @@ +/* + * Philips LPC22XX/LPC21xx Register definitions + * + * Copyright (c) 2006 by Ray + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __LPC22XX_H__ +#define __LPC22XX_H__ + +#include + +/* EXTERNAL MEMORY CONTROLLER (EMC) */ +#define BCFG0 (*((volatile unsigned int *) 0xFFE00000)) /* lpc22xx only */ +#define BCFG1 (*((volatile unsigned int *) 0xFFE00004)) /* lpc22xx only */ +#define BCFG2 (*((volatile unsigned int *) 0xFFE00008)) /* lpc22xx only */ +#define BCFG3 (*((volatile unsigned int *) 0xFFE0000C)) /* lpc22xx only */ + +/* External Interrupts */ +#define EXTINT (*((volatile unsigned char *) 0xE01FC140)) +#define EXTWAKE (*((volatile unsigned char *) 0xE01FC144)) +#ifdef CONFIG_ARCH_LPC22xx +#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) /* no in lpc210x*/ +#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) /* no in lpc210x*/ +#endif + +/* SMemory mapping control. */ +#define MEMMAP (*((volatile unsigned char *) 0xE01FC040)) + +/* Phase Locked Loop (PLL) */ +#define PLLCON (*((volatile unsigned char *) 0xE01FC080)) +#define PLLCFG (*((volatile unsigned char *) 0xE01FC084)) +#define PLLSTAT (*((volatile unsigned short*) 0xE01FC088)) +#define PLLFEED (*((volatile unsigned char *) 0xE01FC08C)) + +/* Power Control */ +#define PCON (*((volatile unsigned char *) 0xE01FC0C0)) +#define PCONP (*((volatile unsigned long *) 0xE01FC0C4)) + +/* VPB Divider */ +#define VPBDIV (*((volatile unsigned char *) 0xE01FC100)) + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*((volatile unsigned char *) 0xE01FC000)) +#define MAMTIM (*((volatile unsigned char *) 0xE01FC004)) + +/* Vectored Interrupt Controller (VIC) */ +#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000)) +#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004)) +#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008)) +#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C)) +#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010)) +#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014)) +#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018)) +#define VICSoftIntClear (*((volatile unsigned long *) 0xFFFFF01C)) +#define VICProtection (*((volatile unsigned long *) 0xFFFFF020)) +#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030)) +#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034)) + +#define VICVectAddrBase 0xFFFFF100 +#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100)) +#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104)) +#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108)) +#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C)) +#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110)) +#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114)) +#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118)) +#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C)) +#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120)) +#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124)) +#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128)) +#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C)) +#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130)) +#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134)) +#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138)) +#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C)) + +#define VICVectCntlBase 0xFFFFF200 +#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200)) +#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204)) +#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208)) +#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C)) +#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210)) +#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214)) +#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218)) +#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C)) +#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220)) +#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224)) +#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228)) +#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C)) +#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230)) +#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234)) +#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238)) +#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C)) + +/* Pin Connect Block */ +#define PINSEL0 (*((volatile unsigned long *) 0xE002C000)) +#define PINSEL1 (*((volatile unsigned long *) 0xE002C004)) + +#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) /* no in lpc210x*/ + + +/* General Purpose Input/Output (GPIO) */ +#ifndef CONFIG_ARCH_LPC22xx + +#define IOPIN (*((volatile unsigned long *) 0xE0028000)) /* lpc210x only */ +#define IOSET (*((volatile unsigned long *) 0xE0028004)) /* lpc210x only */ +#define IODIR (*((volatile unsigned long *) 0xE0028008)) /* lpc210x only */ +#define IOCLR (*((volatile unsigned long *) 0xE002800C)) /* lpc210x only */ + +#endif + +#ifdef CONFIG_ARCH_LPC22xx +#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) /* no in lpc210x*/ +#define IO0SET (*((volatile unsigned long *) 0xE0028004)) /* no in lpc210x*/ +#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) /* no in lpc210x*/ +#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) /* no in lpc210x*/ + +#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) /* no in lpc210x*/ +#define IO1SET (*((volatile unsigned long *) 0xE0028014)) /* no in lpc210x*/ +#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) /* no in lpc210x*/ +#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) /* no in lpc210x*/ +#endif + +#ifdef CONFIG_ARCH_LPC22xx + +#define IO2PIN (*((volatile unsigned long *) 0xE0028020)) /* lpc22xx only */ +#define IO2SET (*((volatile unsigned long *) 0xE0028024)) /* lpc22xx only */ +#define IO2DIR (*((volatile unsigned long *) 0xE0028028)) /* lpc22xx only */ +#define IO2CLR (*((volatile unsigned long *) 0xE002802C)) /* lpc22xx only */ + +#define IO3PIN (*((volatile unsigned long *) 0xE0028030)) /* lpc22xx only */ +#define IO3SET (*((volatile unsigned long *) 0xE0028034)) /* lpc22xx only */ +#define IO3DIR (*((volatile unsigned long *) 0xE0028038)) /* lpc22xx only */ +#define IO3CLR (*((volatile unsigned long *) 0xE002803C)) /* lpc22xx only */ + +#endif + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define U0RBR (*((volatile unsigned char *) 0xE000C000)) +#define U0THR (*((volatile unsigned char *) 0xE000C000)) +#define U0IER (*((volatile unsigned char *) 0xE000C004)) +#define U0IIR (*((volatile unsigned char *) 0xE000C008)) +#define U0FCR (*((volatile unsigned char *) 0xE000C008)) +#define U0LCR (*((volatile unsigned char *) 0xE000C00C)) +#define U0LSR (*((volatile unsigned char *) 0xE000C014)) +#define U0SCR (*((volatile unsigned char *) 0xE000C01C)) +#define U0DLL (*((volatile unsigned char *) 0xE000C000)) +#define U0DLM (*((volatile unsigned char *) 0xE000C004)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define U1RBR (*((volatile unsigned char *) 0xE0010000)) +#define U1THR (*((volatile unsigned char *) 0xE0010000)) +#define U1IER (*((volatile unsigned char *) 0xE0010004)) +#define U1IIR (*((volatile unsigned char *) 0xE0010008)) +#define U1FCR (*((volatile unsigned char *) 0xE0010008)) +#define U1LCR (*((volatile unsigned char *) 0xE001000C)) +#define U1MCR (*((volatile unsigned char *) 0xE0010010)) +#define U1LSR (*((volatile unsigned char *) 0xE0010014)) +#define U1MSR (*((volatile unsigned char *) 0xE0010018)) +#define U1SCR (*((volatile unsigned char *) 0xE001001C)) +#define U1DLL (*((volatile unsigned char *) 0xE0010000)) +#define U1DLM (*((volatile unsigned char *) 0xE0010004)) + +/* I2C (8/16 bit data bus) */ +#define I2CONSET (*((volatile unsigned char *) 0xE001C000)) +#define I2STAT (*((volatile unsigned char *) 0xE001C004)) +#define I2DAT (*((volatile unsigned char *) 0xE001C008)) +#define I2ADR (*((volatile unsigned char *) 0xE001C00C)) +#define I2SCLH (*((volatile unsigned short *) 0xE001C010)) +#define I2SCLL (*((volatile unsigned short *) 0xE001C014)) +#define I2CONCLR (*((volatile unsigned char *) 0xE001C018)) + +/* SPI (Serial Peripheral Interface) */ + /* only for lpc210x*/ +#define SPI_SPCR (*((volatile unsigned char *) 0xE0020000)) +#define SPI_SPSR (*((volatile unsigned char *) 0xE0020004)) +#define SPI_SPDR (*((volatile unsigned char *) 0xE0020008)) +#define SPI_SPCCR (*((volatile unsigned char *) 0xE002000C)) +#define SPI_SPINT (*((volatile unsigned char *) 0xE002001C)) + +#ifdef CONFIG_ARCH_LPC22xx +#define S0PCR (*((volatile unsigned char *) 0xE0020000)) /* no in lpc210x*/ +#define S0PSR (*((volatile unsigned char *) 0xE0020004)) /* no in lpc210x*/ +#define S0PDR (*((volatile unsigned char *) 0xE0020008)) /* no in lpc210x*/ +#define S0PCCR (*((volatile unsigned char *) 0xE002000C)) /* no in lpc210x*/ +#define S0PINT (*((volatile unsigned char *) 0xE002001C)) /* no in lpc210x*/ + +#define S1PCR (*((volatile unsigned char *) 0xE0030000)) /* no in lpc210x*/ +#define S1PSR (*((volatile unsigned char *) 0xE0030004)) /* no in lpc210x*/ +#define S1PDR (*((volatile unsigned char *) 0xE0030008)) /* no in lpc210x*/ +#define S1PCCR (*((volatile unsigned char *) 0xE003000C)) /* no in lpc210x*/ +#define S1PINT (*((volatile unsigned char *) 0xE003001C)) /* no in lpc210x*/ +#endif +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#define CAN1MOD (*((volatile unsigned long *) 0xE0044000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1CMR (*((volatile unsigned long *) 0xE0044004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1GSR (*((volatile unsigned long *) 0xE0044008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1ICR (*((volatile unsigned long *) 0xE004400C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1IER (*((volatile unsigned long *) 0xE0044010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1BTR (*((volatile unsigned long *) 0xE0044014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1EWL (*((volatile unsigned long *) 0xE004401C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1SR (*((volatile unsigned long *) 0xE0044020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1RFS (*((volatile unsigned long *) 0xE0044024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1RDA (*((volatile unsigned long *) 0xE0044028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1RDB (*((volatile unsigned long *) 0xE004402C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TFI1 (*((volatile unsigned long *) 0xE0044030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TID1 (*((volatile unsigned long *) 0xE0044034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDA1 (*((volatile unsigned long *) 0xE0044038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDB1 (*((volatile unsigned long *) 0xE004403C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TFI2 (*((volatile unsigned long *) 0xE0044040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TID2 (*((volatile unsigned long *) 0xE0044044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDA2 (*((volatile unsigned long *) 0xE0044048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDB2 (*((volatile unsigned long *) 0xE004404C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TFI3 (*((volatile unsigned long *) 0xE0044050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TID3 (*((volatile unsigned long *) 0xE0044054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDA3 (*((volatile unsigned long *) 0xE0044058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDB3 (*((volatile unsigned long *) 0xE004405C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN2MOD (*((volatile unsigned long *) 0xE0048000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2CMR (*((volatile unsigned long *) 0xE0048004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2GSR (*((volatile unsigned long *) 0xE0048008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2ICR (*((volatile unsigned long *) 0xE004800C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2IER (*((volatile unsigned long *) 0xE0048010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2BTR (*((volatile unsigned long *) 0xE0048014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2EWL (*((volatile unsigned long *) 0xE004801C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2SR (*((volatile unsigned long *) 0xE0048020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2RFS (*((volatile unsigned long *) 0xE0048024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2RDA (*((volatile unsigned long *) 0xE0048028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2RDB (*((volatile unsigned long *) 0xE004802C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TFI1 (*((volatile unsigned long *) 0xE0048030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TID1 (*((volatile unsigned long *) 0xE0048034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDA1 (*((volatile unsigned long *) 0xE0048038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDB1 (*((volatile unsigned long *) 0xE004803C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TFI2 (*((volatile unsigned long *) 0xE0048040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TID2 (*((volatile unsigned long *) 0xE0048044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDA2 (*((volatile unsigned long *) 0xE0048048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDB2 (*((volatile unsigned long *) 0xE004804C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TFI3 (*((volatile unsigned long *) 0xE0048050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TID3 (*((volatile unsigned long *) 0xE0048054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDA3 (*((volatile unsigned long *) 0xE0048058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDB3 (*((volatile unsigned long *) 0xE004805C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN3MOD (*((volatile unsigned long *) 0xE004C000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3CMR (*((volatile unsigned long *) 0xE004C004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3GSR (*((volatile unsigned long *) 0xE004C008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3ICR (*((volatile unsigned long *) 0xE004C00C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3IER (*((volatile unsigned long *) 0xE004C010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3BTR (*((volatile unsigned long *) 0xE004C014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3EWL (*((volatile unsigned long *) 0xE004C01C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3SR (*((volatile unsigned long *) 0xE004C020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3RFS (*((volatile unsigned long *) 0xE004C024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3RDA (*((volatile unsigned long *) 0xE004C028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3RDB (*((volatile unsigned long *) 0xE004C02C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TFI1 (*((volatile unsigned long *) 0xE004C030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TID1 (*((volatile unsigned long *) 0xE004C034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDA1 (*((volatile unsigned long *) 0xE004C038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDB1 (*((volatile unsigned long *) 0xE004C03C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TFI2 (*((volatile unsigned long *) 0xE004C040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TID2 (*((volatile unsigned long *) 0xE004C044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDA2 (*((volatile unsigned long *) 0xE004C048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDB2 (*((volatile unsigned long *) 0xE004C04C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TFI3 (*((volatile unsigned long *) 0xE004C050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TID3 (*((volatile unsigned long *) 0xE004C054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDA3 (*((volatile unsigned long *) 0xE004C058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDB3 (*((volatile unsigned long *) 0xE004C05C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN4MOD (*((volatile unsigned long *) 0xE0050000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4CMR (*((volatile unsigned long *) 0xE0050004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4GSR (*((volatile unsigned long *) 0xE0050008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4ICR (*((volatile unsigned long *) 0xE005000C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4IER (*((volatile unsigned long *) 0xE0050010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4BTR (*((volatile unsigned long *) 0xE0050014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4EWL (*((volatile unsigned long *) 0xE005001C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4SR (*((volatile unsigned long *) 0xE0050020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4RFS (*((volatile unsigned long *) 0xE0050024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4RDA (*((volatile unsigned long *) 0xE0050028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4RDB (*((volatile unsigned long *) 0xE005002C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TFI1 (*((volatile unsigned long *) 0xE0050030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TID1 (*((volatile unsigned long *) 0xE0050034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDA1 (*((volatile unsigned long *) 0xE0050038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDB1 (*((volatile unsigned long *) 0xE005003C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TFI2 (*((volatile unsigned long *) 0xE0050040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TID2 (*((volatile unsigned long *) 0xE0050044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDA2 (*((volatile unsigned long *) 0xE0050048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDB2 (*((volatile unsigned long *) 0xE005004C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TFI3 (*((volatile unsigned long *) 0xE0050050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TID3 (*((volatile unsigned long *) 0xE0050054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDA3 (*((volatile unsigned long *) 0xE0050058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDB3 (*((volatile unsigned long *) 0xE005005C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN5MOD (*((volatile unsigned long *) 0xE0054000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5CMR (*((volatile unsigned long *) 0xE0054004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5GSR (*((volatile unsigned long *) 0xE0054008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5ICR (*((volatile unsigned long *) 0xE005400C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5IER (*((volatile unsigned long *) 0xE0054010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5BTR (*((volatile unsigned long *) 0xE0054014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5EWL (*((volatile unsigned long *) 0xE005401C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5SR (*((volatile unsigned long *) 0xE0054020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5RFS (*((volatile unsigned long *) 0xE0054024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5RDA (*((volatile unsigned long *) 0xE0054028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5RDB (*((volatile unsigned long *) 0xE005402C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TFI1 (*((volatile unsigned long *) 0xE0054030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TID1 (*((volatile unsigned long *) 0xE0054034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDA1 (*((volatile unsigned long *) 0xE0054038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDB1 (*((volatile unsigned long *) 0xE005403C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TFI2 (*((volatile unsigned long *) 0xE0054040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TID2 (*((volatile unsigned long *) 0xE0054044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDA2 (*((volatile unsigned long *) 0xE0054048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDB2 (*((volatile unsigned long *) 0xE005404C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TFI3 (*((volatile unsigned long *) 0xE0054050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TID3 (*((volatile unsigned long *) 0xE0054054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDA3 (*((volatile unsigned long *) 0xE0054058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDB3 (*((volatile unsigned long *) 0xE005405C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#ifdef CONFIG_ARCH_LPC22xx +#define CAN6MOD (*((volatile unsigned long *) 0xE0058000)) /* lpc2292\lpc2294 only */ +#define CAN6CMR (*((volatile unsigned long *) 0xE0058004)) /* lpc2292\lpc2294 only */ +#define CAN6GSR (*((volatile unsigned long *) 0xE0058008)) /* lpc2292\lpc2294 only */ +#define CAN6ICR (*((volatile unsigned long *) 0xE005800C)) /* lpc2292\lpc2294 only */ +#define CAN6IER (*((volatile unsigned long *) 0xE0058010)) /* lpc2292\lpc2294 only */ +#define CAN6BTR (*((volatile unsigned long *) 0xE0058014)) /* lpc2292\lpc2294 only */ +#define CAN6EWL (*((volatile unsigned long *) 0xE005801C)) /* lpc2292\lpc2294 only */ +#define CAN6SR (*((volatile unsigned long *) 0xE0058020)) /* lpc2292\lpc2294 only */ +#define CAN6RFS (*((volatile unsigned long *) 0xE0058024)) /* lpc2292\lpc2294 only */ +#define CAN6RDA (*((volatile unsigned long *) 0xE0058028)) /* lpc2292\lpc2294 only */ +#define CAN6RDB (*((volatile unsigned long *) 0xE005802C)) /* lpc2292\lpc2294 only */ +#define CAN6TFI1 (*((volatile unsigned long *) 0xE0058030)) /* lpc2292\lpc2294 only */ +#define CAN6TID1 (*((volatile unsigned long *) 0xE0058034)) /* lpc2292\lpc2294 only */ +#define CAN6TDA1 (*((volatile unsigned long *) 0xE0058038)) /* lpc2292\lpc2294 only */ +#define CAN6TDB1 (*((volatile unsigned long *) 0xE005803C)) /* lpc2292\lpc2294 only */ +#define CAN6TFI2 (*((volatile unsigned long *) 0xE0058040)) /* lpc2292\lpc2294 only */ +#define CAN6TID2 (*((volatile unsigned long *) 0xE0058044)) /* lpc2292\lpc2294 only */ +#define CAN6TDA2 (*((volatile unsigned long *) 0xE0058048)) /* lpc2292\lpc2294 only */ +#define CAN6TDB2 (*((volatile unsigned long *) 0xE005804C)) /* lpc2292\lpc2294 only */ +#define CAN6TFI3 (*((volatile unsigned long *) 0xE0058050)) /* lpc2292\lpc2294 only */ +#define CAN6TID3 (*((volatile unsigned long *) 0xE0058054)) /* lpc2292\lpc2294 only */ +#define CAN6TDA3 (*((volatile unsigned long *) 0xE0058058)) /* lpc2292\lpc2294 only */ +#define CAN6TDB3 (*((volatile unsigned long *) 0xE005805C)) /* lpc2292\lpc2294 only */ +#endif + +#define CANTxSR (*((volatile unsigned long *) 0xE0040000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANRxSR (*((volatile unsigned long *) 0xE0040004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANMSR (*((volatile unsigned long *) 0xE0040008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CANAFMR (*((volatile unsigned long *) 0xE003C000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANSFF_sa (*((volatile unsigned long *) 0xE003C004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANSFF_GRP_sa (*((volatile unsigned long *) 0xE003C008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANEFF_sa (*((volatile unsigned long *) 0xE003C00C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANEFF_GRP_sa (*((volatile unsigned long *) 0xE003C010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANENDofTable (*((volatile unsigned long *) 0xE003C014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANLUTerrAd (*((volatile unsigned long *) 0xE003C018)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANLUTerr (*((volatile unsigned long *) 0xE003C01C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +/* CAN Acceptance Filter RAM */ +#define CANAFRAM (*((volatile unsigned long *) 0xE0038000)) + + +/* Timer 0 */ +#define T0IR (*((volatile unsigned long *) 0xE0004000)) +#define T0TCR (*((volatile unsigned long *) 0xE0004004)) +#define T0TC (*((volatile unsigned long *) 0xE0004008)) +#define T0PR (*((volatile unsigned long *) 0xE000400C)) +#define T0PC (*((volatile unsigned long *) 0xE0004010)) +#define T0MCR (*((volatile unsigned long *) 0xE0004014)) +#define T0MR0 (*((volatile unsigned long *) 0xE0004018)) +#define T0MR1 (*((volatile unsigned long *) 0xE000401C)) +#define T0MR2 (*((volatile unsigned long *) 0xE0004020)) +#define T0MR3 (*((volatile unsigned long *) 0xE0004024)) +#define T0CCR (*((volatile unsigned long *) 0xE0004028)) +#define T0CR0 (*((volatile unsigned long *) 0xE000402C)) +#define T0CR1 (*((volatile unsigned long *) 0xE0004030)) +#define T0CR2 (*((volatile unsigned long *) 0xE0004034)) +#define T0CR3 (*((volatile unsigned long *) 0xE0004038)) +#define T0EMR (*((volatile unsigned long *) 0xE000403C)) + +/* Timer 1 */ +#define T1IR (*((volatile unsigned long *) 0xE0008000)) +#define T1TCR (*((volatile unsigned long *) 0xE0008004)) +#define T1TC (*((volatile unsigned long *) 0xE0008008)) +#define T1PR (*((volatile unsigned long *) 0xE000800C)) +#define T1PC (*((volatile unsigned long *) 0xE0008010)) +#define T1MCR (*((volatile unsigned long *) 0xE0008014)) +#define T1MR0 (*((volatile unsigned long *) 0xE0008018)) +#define T1MR1 (*((volatile unsigned long *) 0xE000801C)) +#define T1MR2 (*((volatile unsigned long *) 0xE0008020)) +#define T1MR3 (*((volatile unsigned long *) 0xE0008024)) +#define T1CCR (*((volatile unsigned long *) 0xE0008028)) +#define T1CR0 (*((volatile unsigned long *) 0xE000802C)) +#define T1CR1 (*((volatile unsigned long *) 0xE0008030)) +#define T1CR2 (*((volatile unsigned long *) 0xE0008034)) +#define T1CR3 (*((volatile unsigned long *) 0xE0008038)) +#define T1EMR (*((volatile unsigned long *) 0xE000803C)) + +/* Pulse Width Modulator (PWM) */ +#define PWMIR (*((volatile unsigned long *) 0xE0014000)) +#define PWMTCR (*((volatile unsigned long *) 0xE0014004)) +#define PWMTC (*((volatile unsigned long *) 0xE0014008)) +#define PWMPR (*((volatile unsigned long *) 0xE001400C)) +#define PWMPC (*((volatile unsigned long *) 0xE0014010)) +#define PWMMCR (*((volatile unsigned long *) 0xE0014014)) +#define PWMMR0 (*((volatile unsigned long *) 0xE0014018)) +#define PWMMR1 (*((volatile unsigned long *) 0xE001401C)) +#define PWMMR2 (*((volatile unsigned long *) 0xE0014020)) +#define PWMMR3 (*((volatile unsigned long *) 0xE0014024)) +#define PWMMR4 (*((volatile unsigned long *) 0xE0014040)) +#define PWMMR5 (*((volatile unsigned long *) 0xE0014044)) +#define PWMMR6 (*((volatile unsigned long *) 0xE0014048)) +#define PWMPCR (*((volatile unsigned long *) 0xE001404C)) +#define PWMLER (*((volatile unsigned long *) 0xE0014050)) + +/* A/D CONVERTER */ +#ifndef CONFIG_ARCH_LPC2104 +#define ADCR (*((volatile unsigned long *) 0xE0034000)) /* no in lpc210x*/ +#define ADDR (*((volatile unsigned long *) 0xE0034004)) /* no in lpc210x*/ +#endif + +/* Real Time Clock */ +#define ILR (*((volatile unsigned char *) 0xE0024000)) +#define CTC (*((volatile unsigned short*) 0xE0024004)) +#define CCR (*((volatile unsigned char *) 0xE0024008)) +#define CIIR (*((volatile unsigned char *) 0xE002400C)) +#define AMR (*((volatile unsigned char *) 0xE0024010)) +#define CTIME0 (*((volatile unsigned long *) 0xE0024014)) +#define CTIME1 (*((volatile unsigned long *) 0xE0024018)) +#define CTIME2 (*((volatile unsigned long *) 0xE002401C)) +#define SEC (*((volatile unsigned char *) 0xE0024020)) +#define MIN (*((volatile unsigned char *) 0xE0024024)) +#define HOUR (*((volatile unsigned char *) 0xE0024028)) +#define DOM (*((volatile unsigned char *) 0xE002402C)) +#define DOW (*((volatile unsigned char *) 0xE0024030)) +#define DOY (*((volatile unsigned short*) 0xE0024034)) +#define MONTH (*((volatile unsigned char *) 0xE0024038)) +#define YEAR (*((volatile unsigned short*) 0xE002403C)) +#define ALSEC (*((volatile unsigned char *) 0xE0024060)) +#define ALMIN (*((volatile unsigned char *) 0xE0024064)) +#define ALHOUR (*((volatile unsigned char *) 0xE0024068)) +#define ALDOM (*((volatile unsigned char *) 0xE002406C)) +#define ALDOW (*((volatile unsigned char *) 0xE0024070)) +#define ALDOY (*((volatile unsigned short*) 0xE0024074)) +#define ALMON (*((volatile unsigned char *) 0xE0024078)) +#define ALYEAR (*((volatile unsigned short*) 0xE002407C)) +#define PREINT (*((volatile unsigned short*) 0xE0024080)) +#define PREFRAC (*((volatile unsigned short*) 0xE0024084)) + +/* Watchdog */ +#define WDMOD (*((volatile unsigned char *) 0xE0000000)) +#define WDTC (*((volatile unsigned long *) 0xE0000004)) +#define WDFEED (*((volatile unsigned char *) 0xE0000008)) +#define WDTV (*((volatile unsigned long *) 0xE000000C)) + +/* + Register define for constant +*/ +#define REG_U0RBR 0xE000C000 +#define REG_U1RBR 0xE0010000 + +/* PLL */ +#define REG_PLLCON 0xE01FC080 +#define REG_PLLCFG 0xE01FC084 +#define REG_PLLSTAT 0xE01FC088 +#define REG_PLLFEED 0xE01FC08C + +/* Power Control */ + +#define REG_PCON 0xE01FC0C0 +#define REG_PCOMP 0xE01FC0C4 +#define REG_PINSEL0 0xE002C000 +#define REG_MEMMAP 0xE01FC040 +#define REG_PLLSTAT 0xE01FC088 +#define REG_VPBDIV 0xE01FC100 + + +#endif /* __LPC22XX_H__ */ diff --git a/bsps/arm/rtl22xx/include/tm27.h b/bsps/arm/rtl22xx/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/rtl22xx/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/smdk2410/headers.am b/bsps/arm/smdk2410/headers.am new file mode 100644 index 0000000000..25d2eb723e --- /dev/null +++ b/bsps/arm/smdk2410/headers.am @@ -0,0 +1,14 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/smdk2410/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/smdk2410/include/s3c2400.h +include_HEADERS += ../../../../../../bsps/arm/smdk2410/include/s3c2410.h +include_HEADERS += ../../../../../../bsps/arm/smdk2410/include/s3c24xx.h +include_HEADERS += ../../../../../../bsps/arm/smdk2410/include/smc.h +include_HEADERS += ../../../../../../bsps/arm/smdk2410/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/smdk2410/include/bsp/irq.h diff --git a/bsps/arm/smdk2410/include/bsp.h b/bsps/arm/smdk2410/include/bsp.h new file mode 100644 index 0000000000..25764195d0 --- /dev/null +++ b/bsps/arm/smdk2410/include/bsp.h @@ -0,0 +1,80 @@ +/** + * @file + * @ingroup arm_smdk2410 + * @brief Global BSP definitons. + */ + +/* + * Copyright (c) Canon Research France SA.] + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SMDK2410_BSP_H +#define LIBBSP_ARM_SMDK2410_BSP_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION + +/** + * @brief functions to get the differents s3c2400 clks + * @{ + */ + +uint32_t get_FCLK(void); +uint32_t get_HCLK(void); +uint32_t get_PCLK(void); +uint32_t get_UCLK(void); + +/** @} */ + +/* What is the input clock freq in hertz? */ +/** @brief 12 MHz oscillator */ +#define BSP_OSC_FREQ 12000000 +/** @brief FCLK=133Mhz */ +#define M_MDIV 81 +#define M_PDIV 2 +#define M_SDIV 1 +/** @brief HCLK=FCLK/2, PCLK=FCLK/2 */ +#define M_CLKDIVN 2 +/** @brief enable refresh */ +#define REFEN 0x1 +/** @brief CBR(CAS before RAS)/auto refresh */ +#define TREFMD 0x0 +/** @brief 2 clk */ +#define Trp 0x0 +/** @brief 7 clk */ +#define Trc 0x3 +/** @brief 3 clk */ +#define Tchr 0x2 + +/** + * @brief This BSP provides its own IDLE thread to override the RTEMS one. + * + * So we prototype it and define the constant confdefs.h expects + * to configure a BSP specific one. + */ +void *bsp_idle_thread(uintptr_t ignored); + +/** @} */ + +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ + diff --git a/bsps/arm/smdk2410/include/bsp/irq.h b/bsps/arm/smdk2410/include/bsp/irq.h new file mode 100644 index 0000000000..8882b4362b --- /dev/null +++ b/bsps/arm/smdk2410/include/bsp/irq.h @@ -0,0 +1,96 @@ +/* irq.h + * + * Copyright (c) 2010 embedded brains GmbH. + * + * CopyRight (C) 2000 Canon Research France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * Common file, merged from s3c2400/irq/irq.h and s3c2410/irq/irq.h + */ + +#ifndef _IRQ_H_ +#define _IRQ_H_ + +#include +#include +#include + +#include + +#ifdef CPU_S3C2400 + /* possible interrupt sources */ +#define BSP_EINT0 0 +#define BSP_EINT1 1 +#define BSP_EINT2 2 +#define BSP_EINT3 3 +#define BSP_EINT4 4 +#define BSP_EINT5 5 +#define BSP_EINT6 6 +#define BSP_EINT7 7 +#define BSP_INT_TICK 8 +#define BSP_INT_WDT 9 +#define BSP_INT_TIMER0 10 +#define BSP_INT_TIMER1 11 +#define BSP_INT_TIMER2 12 +#define BSP_INT_TIMER3 13 +#define BSP_INT_TIMER4 14 +#define BSP_INT_UERR01 15 +#define _res0 16 +#define BSP_INT_DMA0 17 +#define BSP_INT_DMA1 18 +#define BSP_INT_DMA2 19 +#define BSP_INT_DMA3 20 +#define BSP_INT_MMC 21 +#define BSP_INT_SPI 22 +#define BSP_INT_URXD0 23 +#define BSP_INT_URXD1 24 +#define BSP_INT_USBD 25 +#define BSP_INT_USBH 26 +#define BSP_INT_IIC 27 +#define BSP_INT_UTXD0 28 +#define BSP_INT_UTXD1 29 +#define BSP_INT_RTC 30 +#define BSP_INT_ADC 31 +#define BSP_MAX_INT 32 + +#elif defined CPU_S3C2410 + /* possible interrupt sources */ +#define BSP_EINT0 0 +#define BSP_EINT1 1 +#define BSP_EINT2 2 +#define BSP_EINT3 3 +#define BSP_EINT4_7 4 +#define BSP_EINT8_23 5 +#define BSP_nBATT_FLT 7 +#define BSP_INT_TICK 8 +#define BSP_INT_WDT 9 +#define BSP_INT_TIMER0 10 +#define BSP_INT_TIMER1 11 +#define BSP_INT_TIMER2 12 +#define BSP_INT_TIMER3 13 +#define BSP_INT_TIMER4 14 +#define BSP_INT_UART2 15 +#define BSP_INT_LCD 16 +#define BSP_INT_DMA0 17 +#define BSP_INT_DMA1 18 +#define BSP_INT_DMA2 19 +#define BSP_INT_DMA3 20 +#define BSP_INT_SDI 21 +#define BSP_INT_SPI0 22 +#define BSP_INT_UART1 23 +#define BSP_INT_USBD 25 +#define BSP_INT_USBH 26 +#define BSP_INT_IIC 27 +#define BSP_INT_UART0 28 +#define BSP_INT_SPI1 29 +#define BSP_INT_RTC 30 +#define BSP_INT_ADC 31 +#define BSP_MAX_INT 32 +#endif + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) + +#endif /* _IRQ_H_ */ +/* end of include file */ diff --git a/bsps/arm/smdk2410/include/s3c2400.h b/bsps/arm/smdk2410/include/s3c2400.h new file mode 100644 index 0000000000..89a3cf73d8 --- /dev/null +++ b/bsps/arm/smdk2410/include/s3c2400.h @@ -0,0 +1,676 @@ +/************************************************ + * NAME : s3c2400.h + * Version : 3.7.2002 + * + * Based on 24x.h for the Samsung Development Board + ************************************************/ + +#ifndef S3C2400_H_ +#define S3C2400_H_ + +/* to be used in assembly code */ +#define rINTOFFSET_ADDR 0x14400014 +/* Memory control */ +#define rBWSCON (*(volatile unsigned *)0x14000000) +#define rBANKCON0 (*(volatile unsigned *)0x14000004) +#define rBANKCON1 (*(volatile unsigned *)0x14000008) +#define rBANKCON2 (*(volatile unsigned *)0x1400000C) +#define rBANKCON3 (*(volatile unsigned *)0x14000010) +#define rBANKCON4 (*(volatile unsigned *)0x14000014) +#define rBANKCON5 (*(volatile unsigned *)0x14000018) +#define rBANKCON6 (*(volatile unsigned *)0x1400001C) +#define rBANKCON7 (*(volatile unsigned *)0x14000020) +#define rREFRESH (*(volatile unsigned *)0x14000024) +#define rBANKSIZE (*(volatile unsigned *)0x14000028) +#define rMRSRB6 (*(volatile unsigned *)0x1400002C) +#define rMRSRB7 (*(volatile unsigned *)0x14000030) + + +/* INTERRUPT */ +#define rSRCPND (*(volatile unsigned *)0x14400000) +#define rINTMOD (*(volatile unsigned *)0x14400004) +#define rINTMSK (*(volatile unsigned *)0x14400008) +#define rPRIORITY (*(volatile unsigned *)0x1440000C) +#define rINTPND (*(volatile unsigned *)0x14400010) +#define rINTOFFSET (*(volatile unsigned *)0x14400014) + + +/* DMA */ +#define rDISRC0 (*(volatile unsigned *)0x14600000) +#define rDIDST0 (*(volatile unsigned *)0x14600004) +#define rDCON0 (*(volatile unsigned *)0x14600008) +#define rDSTAT0 (*(volatile unsigned *)0x1460000C) +#define rDCSRC0 (*(volatile unsigned *)0x14600010) +#define rDCDST0 (*(volatile unsigned *)0x14600014) +#define rDMASKTRIG0 (*(volatile unsigned *)0x14600018) +#define rDISRC1 (*(volatile unsigned *)0x14600020) +#define rDIDST1 (*(volatile unsigned *)0x14600024) +#define rDCON1 (*(volatile unsigned *)0x14600028) +#define rDSTAT1 (*(volatile unsigned *)0x1460002C) +#define rDCSRC1 (*(volatile unsigned *)0x14600030) +#define rDCDST1 (*(volatile unsigned *)0x14600034) +#define rDMASKTRIG1 (*(volatile unsigned *)0x14600038) +#define rDISRC2 (*(volatile unsigned *)0x14600040) +#define rDIDST2 (*(volatile unsigned *)0x14600044) +#define rDCON2 (*(volatile unsigned *)0x14600048) +#define rDSTAT2 (*(volatile unsigned *)0x1460004C) +#define rDCSRC2 (*(volatile unsigned *)0x14600050) +#define rDCDST2 (*(volatile unsigned *)0x14600054) +#define rDMASKTRIG2 (*(volatile unsigned *)0x14600058) +#define rDISRC3 (*(volatile unsigned *)0x14600060) +#define rDIDST3 (*(volatile unsigned *)0x14600064) +#define rDCON3 (*(volatile unsigned *)0x14600068) +#define rDSTAT3 (*(volatile unsigned *)0x1460006C) +#define rDCSRC3 (*(volatile unsigned *)0x14600070) +#define rDCDST3 (*(volatile unsigned *)0x14600074) +#define rDMASKTRIG3 (*(volatile unsigned *)0x14600078) + + +/* CLOCK & POWER MANAGEMENT */ +#define rLOCKTIME (*(volatile unsigned *)0x14800000) +#define rMPLLCON (*(volatile unsigned *)0x14800004) +#define rUPLLCON (*(volatile unsigned *)0x14800008) +#define rCLKCON (*(volatile unsigned *)0x1480000C) +#define rCLKSLOW (*(volatile unsigned *)0x14800010) +#define rCLKDIVN (*(volatile unsigned *)0x14800014) + + +/* LCD CONTROLLER */ +#define rLCDCON1 (*(volatile unsigned *)0x14A00000) +#define rLCDCON2 (*(volatile unsigned *)0x14A00004) +#define rLCDCON3 (*(volatile unsigned *)0x14A00008) +#define rLCDCON4 (*(volatile unsigned *)0x14A0000C) +#define rLCDCON5 (*(volatile unsigned *)0x14A00010) +#define rLCDSADDR1 (*(volatile unsigned *)0x14A00014) +#define rLCDSADDR2 (*(volatile unsigned *)0x14A00018) +#define rLCDSADDR3 (*(volatile unsigned *)0x14A0001C) +#define rREDLUT (*(volatile unsigned *)0x14A00020) +#define rGREENLUT (*(volatile unsigned *)0x14A00024) +#define rBLUELUT (*(volatile unsigned *)0x14A00028) +#define rDP1_2 (*(volatile unsigned *)0x14A0002C) +#define rDP4_7 (*(volatile unsigned *)0x14A00030) +#define rDP3_5 (*(volatile unsigned *)0x14A00034) +#define rDP2_3 (*(volatile unsigned *)0x14A00038) +#define rDP5_7 (*(volatile unsigned *)0x14A0003c) +#define rDP3_4 (*(volatile unsigned *)0x14A00040) +#define rDP4_5 (*(volatile unsigned *)0x14A00044) +#define rDP6_7 (*(volatile unsigned *)0x14A00048) +#define rDITHMODE (*(volatile unsigned *)0x14A0004C) +#define rTPAL (*(volatile unsigned *)0x14A00050) +#define GP32_PALETTE (*(volatile unsigned *)0x14A00400) /* SJS */ + + +/* UART */ +#define rULCON0 (*(volatile unsigned char *)0x15000000) +#define rUCON0 (*(volatile unsigned short *)0x15000004) +#define rUFCON0 (*(volatile unsigned char *)0x15000008) +#define rUMCON0 (*(volatile unsigned char *)0x1500000C) +#define rUTRSTAT0 (*(volatile unsigned char *)0x15000010) +#define rUERSTAT0 (*(volatile unsigned char *)0x15000014) +#define rUFSTAT0 (*(volatile unsigned short *)0x15000018) +#define rUMSTAT0 (*(volatile unsigned char *)0x1500001C) +#define rUBRDIV0 (*(volatile unsigned short *)0x15000028) + +#define rULCON1 (*(volatile unsigned char *)0x15004000) +#define rUCON1 (*(volatile unsigned short *)0x15004004) +#define rUFCON1 (*(volatile unsigned char *)0x15004008) +#define rUMCON1 (*(volatile unsigned char *)0x1500400C) +#define rUTRSTAT1 (*(volatile unsigned char *)0x15004010) +#define rUERSTAT1 (*(volatile unsigned char *)0x15004014) +#define rUFSTAT1 (*(volatile unsigned short *)0x15004018) +#define rUMSTAT1 (*(volatile unsigned char *)0x1500401C) +#define rUBRDIV1 (*(volatile unsigned short *)0x15004028) + +#ifdef __BIG_ENDIAN +#define rUTXH0 (*(volatile unsigned char *)0x15000023) +#define rURXH0 (*(volatile unsigned char *)0x15000027) +#define rUTXH1 (*(volatile unsigned char *)0x15004023) +#define rURXH1 (*(volatile unsigned char *)0x15004027) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x15000027) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x15004027) + +#define UTXH0 (0x15000020+3) /* byte_access address by DMA */ +#define URXH0 (0x15000024+3) +#define UTXH1 (0x15004020+3) +#define URXH1 (0x15004024+3) + +#else /* Little Endian */ +#define rUTXH0 (*(volatile unsigned char *)0x15000020) +#define rURXH0 (*(volatile unsigned char *)0x15000024) +#define rUTXH1 (*(volatile unsigned char *)0x15004020) +#define rURXH1 (*(volatile unsigned char *)0x15004024) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x15000024) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x15004024) + +#define UTXH0 (0x15000020) /* byte_access address by DMA */ +#define URXH0 (0x15000024) +#define UTXH1 (0x15004020) +#define URXH1 (0x15004024) +#endif + + +/* PWM TIMER */ +#define rTCFG0 (*(volatile unsigned *)0x15100000) +#define rTCFG1 (*(volatile unsigned *)0x15100004) +#define rTCON (*(volatile unsigned *)0x15100008) +#define rTCNTB0 (*(volatile unsigned *)0x1510000C) +#define rTCMPB0 (*(volatile unsigned *)0x15100010) +#define rTCNTO0 (*(volatile unsigned *)0x15100014) +#define rTCNTB1 (*(volatile unsigned *)0x15100018) +#define rTCMPB1 (*(volatile unsigned *)0x1510001C) +#define rTCNTO1 (*(volatile unsigned *)0x15100020) +#define rTCNTB2 (*(volatile unsigned *)0x15100024) +#define rTCMPB2 (*(volatile unsigned *)0x15100028) +#define rTCNTO2 (*(volatile unsigned *)0x1510002C) +#define rTCNTB3 (*(volatile unsigned *)0x15100030) +#define rTCMPB3 (*(volatile unsigned *)0x15100034) +#define rTCNTO3 (*(volatile unsigned *)0x15100038) +#define rTCNTB4 (*(volatile unsigned *)0x1510003C) +#define rTCNTO4 (*(volatile unsigned *)0x15100040) + + +/* USB DEVICE */ +#define rFUNC_ADDR_REG (*(volatile unsigned *)0x15200140) +#define rPWR_REG (*(volatile unsigned *)0x15200144) +#define rINT_REG (*(volatile unsigned *)0x15200148) +#define rINT_MASK_REG (*(volatile unsigned *)0x1520014C) +#define rFRAME_NUM_REG (*(volatile unsigned *)0x15200150) +#define rRESUME_CON_REG (*(volatile unsigned *)0x15200154) +#define rEP0_CSR (*(volatile unsigned *)0x15200160) +#define rEP0_MAXP (*(volatile unsigned *)0x15200164) +#define rEP0_OUT_CNT (*(volatile unsigned *)0x15200168) +#define rEP0_FIFO (*(volatile unsigned *)0x1520016C) +#define rEP1_IN_CSR (*(volatile unsigned *)0x15200180) +#define rEP1_IN_MAXP (*(volatile unsigned *)0x15200184) +#define rEP1_FIFO (*(volatile unsigned *)0x15200188) +#define rEP2_IN_CSR (*(volatile unsigned *)0x15200190) +#define rEP2_IN_MAXP (*(volatile unsigned *)0x15200194) +#define rEP2_FIFO (*(volatile unsigned *)0x15200198) +#define rEP3_OUT_CSR (*(volatile unsigned *)0x152001A0) +#define rEP3_OUT_MAXP (*(volatile unsigned *)0x152001A4) +#define rEP3_OUT_CNT (*(volatile unsigned *)0x152001A8) +#define rEP3_FIFO (*(volatile unsigned *)0x152001AC) +#define rEP4_OUT_CSR (*(volatile unsigned *)0x152001B0) +#define rEP4_OUT_MAXP (*(volatile unsigned *)0x152001B4) +#define rEP4_OUT_CNT (*(volatile unsigned *)0x152001B8) +#define rEP4_FIFO (*(volatile unsigned *)0x152001BC) +#define rDMA_CON (*(volatile unsigned *)0x152001C0) +#define rDMA_UNIT (*(volatile unsigned *)0x152001C4) +#define rDMA_FIFO (*(volatile unsigned *)0x152001C8) +#define rDMA_TX (*(volatile unsigned *)0x152001CC) +#define rTEST_MODE (*(volatile unsigned *)0x152001F4) +#define rIN_CON_REG (*(volatile unsigned *)0x152001F8) + + +/* WATCH DOG TIMER */ +#define rWTCON (*(volatile unsigned *)0x15300000) +#define rWTDAT (*(volatile unsigned *)0x15300004) +#define rWTCNT (*(volatile unsigned *)0x15300008) + + +/* IIC */ +#define rIICCON (*(volatile unsigned *)0x15400000) +#define rIICSTAT (*(volatile unsigned *)0x15400004) +#define rIICADD (*(volatile unsigned *)0x15400008) +#define rIICDS (*(volatile unsigned *)0x1540000C) + + +/* IIS */ +#define rIISCON (*(volatile unsigned *)0x15508000) +#define rIISMOD (*(volatile unsigned *)0x15508004) +#define rIISPSR (*(volatile unsigned *)0x15508008) +#define rIISFIFCON (*(volatile unsigned *)0x1550800C) + +#ifdef __BIG_ENDIAN +#define IISFIF ((volatile unsigned short *)0x15508012) + +#else /* Little Endian */ +#define IISFIF ((volatile unsigned short *)0x15508010) +#endif + + +/* I/O PORT */ +#define rPACON (*(volatile unsigned *)0x15600000) +#define rPADAT (*(volatile unsigned *)0x15600004) + +#define rPBCON (*(volatile unsigned *)0x15600008) +#define rPBDAT (*(volatile unsigned *)0x1560000C) +#define rPBUP (*(volatile unsigned *)0x15600010) + +#define rPCCON (*(volatile unsigned *)0x15600014) +#define rPCDAT (*(volatile unsigned *)0x15600018) +#define rPCUP (*(volatile unsigned *)0x1560001C) + +#define rPDCON (*(volatile unsigned *)0x15600020) +#define rPDDAT (*(volatile unsigned *)0x15600024) +#define rPDUP (*(volatile unsigned *)0x15600028) + +#define rPECON (*(volatile unsigned *)0x1560002C) +#define rPEDAT (*(volatile unsigned *)0x15600030) +#define rPEUP (*(volatile unsigned *)0x15600034) + +#define rPFCON (*(volatile unsigned *)0x15600038) +#define rPFDAT (*(volatile unsigned *)0x1560003C) +#define rPFUP (*(volatile unsigned *)0x15600040) + +#define rPGCON (*(volatile unsigned *)0x15600044) +#define rPGDAT (*(volatile unsigned *)0x15600048) +#define rPGUP (*(volatile unsigned *)0x1560004C) + +#define rOPENCR (*(volatile unsigned *)0x15600050) +#define rMISCCR (*(volatile unsigned *)0x15600054) +#define rEXTINT (*(volatile unsigned *)0x15600058) + + +/* RTC */ +#ifdef __BIG_ENDIAN +#define rRTCCON (*(volatile unsigned char *)0x15700043) +#define rRTCALM (*(volatile unsigned char *)0x15700053) +#define rALMSEC (*(volatile unsigned char *)0x15700057) +#define rALMMIN (*(volatile unsigned char *)0x1570005B) +#define rALMHOUR (*(volatile unsigned char *)0x1570005F) +#define rALMDAY (*(volatile unsigned char *)0x15700063) +#define rALMMON (*(volatile unsigned char *)0x15700067) +#define rALMYEAR (*(volatile unsigned char *)0x1570006B) +#define rRTCRST (*(volatile unsigned char *)0x1570006F) +#define rBCDSEC (*(volatile unsigned char *)0x15700073) +#define rBCDMIN (*(volatile unsigned char *)0x15700077) +#define rBCDHOUR (*(volatile unsigned char *)0x1570007B) +#define rBCDDAY (*(volatile unsigned char *)0x1570007F) +#define rBCDDATE (*(volatile unsigned char *)0x15700083) +#define rBCDMON (*(volatile unsigned char *)0x15700087) +#define rBCDYEAR (*(volatile unsigned char *)0x1570008B) +#define rTICINT (*(volatile unsigned char *)0x15700047) + +#else /* Little Endian */ +#define rRTCCON (*(volatile unsigned char *)0x15700040) +#define rRTCALM (*(volatile unsigned char *)0x15700050) +#define rALMSEC (*(volatile unsigned char *)0x15700054) +#define rALMMIN (*(volatile unsigned char *)0x15700058) +#define rALMHOUR (*(volatile unsigned char *)0x1570005C) +#define rALMDAY (*(volatile unsigned char *)0x15700060) +#define rALMMON (*(volatile unsigned char *)0x15700064) +#define rALMYEAR (*(volatile unsigned char *)0x15700068) +#define rRTCRST (*(volatile unsigned char *)0x1570006C) +#define rBCDSEC (*(volatile unsigned char *)0x15700070) +#define rBCDMIN (*(volatile unsigned char *)0x15700074) +#define rBCDHOUR (*(volatile unsigned char *)0x15700078) +#define rBCDDAY (*(volatile unsigned char *)0x1570007C) +#define rBCDDATE (*(volatile unsigned char *)0x15700080) +#define rBCDMON (*(volatile unsigned char *)0x15700084) +#define rBCDYEAR (*(volatile unsigned char *)0x15700088) +#define rTICINT (*(volatile unsigned char *)0x15700044) +#endif + + +/* ADC */ +#define rADCCON (*(volatile unsigned *)0x15800000) +#define rADCDAT (*(volatile unsigned *)0x15800004) + + +/* SPI */ +#define rSPCON (*(volatile unsigned *)0x15900000) +#define rSPSTA (*(volatile unsigned *)0x15900004) +#define rSPPIN (*(volatile unsigned *)0x15900008) +#define rSPPRE (*(volatile unsigned *)0x1590000C) +#define rSPTDAT (*(volatile unsigned *)0x15900010) +#define rSPRDAT (*(volatile unsigned *)0x15900014) + + +/* MMC INTERFACE */ +#define rMMCON (*(volatile unsigned *)0x15a00000) +#define rMMCRR (*(volatile unsigned *)0x15a00004) +#define rMMFCON (*(volatile unsigned *)0x15a00008) +#define rMMSTA (*(volatile unsigned *)0x15a0000C) +#define rMMFSTA (*(volatile unsigned *)0x15a00010) +#define rMMPRE (*(volatile unsigned *)0x15a00014) +#define rMMLEN (*(volatile unsigned *)0x15a00018) +#define rMMCR7 (*(volatile unsigned *)0x15a0001C) +#define rMMRSP0 (*(volatile unsigned *)0x15a00020) +#define rMMRSP1 (*(volatile unsigned *)0x15a00024) +#define rMMRSP2 (*(volatile unsigned *)0x15a00028) +#define rMMRSP3 (*(volatile unsigned *)0x15a0002C) +#define rMMCMD0 (*(volatile unsigned *)0x15a00030) +#define rMMCMD1 (*(volatile unsigned *)0x15a00034) +#define rMMCR16 (*(volatile unsigned *)0x15a00038) +#define rMMDAT (*(volatile unsigned *)0x15a0003C) + + +#define _ISR_STARTADDRESS rtems_vector_table +/* ISR */ +#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) +#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) +#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) +#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC)) +#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) +#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) +#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) +#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C)) + +#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) +#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) +#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) +#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C)) +#define pISR_EINT4 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) +#define pISR_EINT5 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) +#define pISR_EINT6 (*(unsigned *)(_ISR_STARTADDRESS+0x38)) +#define pISR_EINT7 (*(unsigned *)(_ISR_STARTADDRESS+0x3C)) +#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) +#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) +#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) +#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C)) +#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) +#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) +#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) +#define pISR_UERR01 (*(unsigned *)(_ISR_STARTADDRESS+0x5C)) +#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) +#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) +#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) +#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C)) +#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) +#define pISR_MMC (*(unsigned *)(_ISR_STARTADDRESS+0x74)) +#define pISR_SPI (*(unsigned *)(_ISR_STARTADDRESS+0x78)) +#define pISR_URXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x7C)) +#define pISR_URXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x80)) +#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) +#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) +#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C)) +#define pISR_UTXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) +#define pISR_UTXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) +#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) +#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0)) + + +/* PENDING BIT */ +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4 (0x1<<4) +#define BIT_EINT5 (0x1<<5) +#define BIT_EINT6 (0x1<<6) +#define BIT_EINT7 (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UERR01 (0x1<<15) +#define BIT_NOTUSED (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_MMC (0x1<<21) +#define BIT_SPI (0x1<<22) +#define BIT_URXD0 (0x1<<23) +#define BIT_URXD1 (0x1<<24) +#define BIT_USBD (0x1<<25) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UTXD0 (0x1<<28) +#define BIT_UTXD1 (0x1<<29) +#define BIT_RTC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xFFFFFFFF) + +#define ClearPending(bit) {\ + rSRCPND = bit;\ + rINTPND = bit;\ + rINTPND;\ + } +/* Wait until rINTPND is changed for the case that the ISR is very short. */ + +#ifndef ASM +/* Typedefs */ +typedef union { + struct _reg { + unsigned STOP_BIT:1; /* Enters STOP mode. This bit isn't be */ + /* cleared automatically. */ + unsigned SL_IDLE:1; /* SL_IDLE mode option. This bit isn't cleared */ + /* automatically. To enter SL_IDLE mode, */ + /* CLKCON register has to be 0xe. */ + unsigned IDLE_BIT:1; /* Enters IDLE mode. This bit isn't be cleared */ + /* automatically. */ + unsigned LCDC:1; /* Controls HCLK into LCDC block */ + unsigned USB_host:1; /* Controls HCLK into USB host block */ + unsigned USB_device:1; /* Controls PCLK into USB device block */ + unsigned PWMTIMER:1; /* Controls PCLK into PWMTIMER block */ + unsigned MMC:1; /* Controls PCLK into MMC interface block */ + unsigned UART0:1; /* Controls PCLK into UART0 block */ + unsigned UART1:1; /* Controls PCLK into UART1 block */ + unsigned GPIO:1; /* Controls PCLK into GPIO block */ + unsigned RTC:1; /* Controls PCLK into RTC control block. Even if */ + /* this bit is cleared to 0, RTC timer is alive. */ + unsigned ADC:1; /* Controls PCLK into ADC block */ + unsigned IIC:1; /* Controls PCLK into IIC block */ + unsigned IIS:1; /* Controls PCLK into IIS block */ + unsigned SPI:1; /* Controls PCLK into SPI block */ + } reg; + unsigned long all; +} CLKCON; + +typedef union +{ + struct { + unsigned ENVID:1; /* LCD video output and the logic 1=enable/0=disable. */ + unsigned BPPMODE:4; /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */ + /* 1110 = 16 bpp TFT skipmode */ + unsigned PNRMODE:2; /* TFT: 3 */ + unsigned MMODE:1; /* This bit determines the toggle rate of the VM. */ + /* 0 = Each Frame, 1 = The rate defined by the MVAL */ + unsigned CLKVAL:10; /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */ + unsigned LINECNT:10; /* (read only) These bits provide the status of the */ + /* line counter. Down count from LINEVAL to 0 */ + } reg; + unsigned long all; +} LCDCON1; + +typedef union { + struct { + unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */ + /* VSYNC pulse's high level width by counting the */ + /* number of inactive lines. */ + unsigned VFPD:8; /* TFT: Vertical front porch is the number of */ + /* inactive lines at the end of a frame, before */ + /* vertical synchronization period. */ + unsigned LINEVAL:10; /* TFT/STN: These bits determine the vertical size */ + /* of LCD panel. */ + unsigned VBPD:8; /* TFT: Vertical back porch is the number of inactive */ + /* lines at the start of a frame, after */ + /* vertical synchronization period. */ + } reg; + unsigned long all; +} LCDCON2; + +typedef union { + struct { + unsigned HFPD:8; /* TFT: Horizontal front porch is the number of */ + /* VCLK periods between the end of active data */ + /* and the rising edge of HSYNC. */ + unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */ + /* size of LCD panel. 2n bytes. */ + unsigned HBPD:7; /* TFT: Horizontal back porch is the number of VCLK */ + /* periods between the falling edge of HSYNC and */ + /* the start of active data. */ + } reg; + unsigned long all; +} LCDCON3; + +typedef union { + struct { + unsigned HSPW:8; /* TFT: Horizontal sync pulse width determines the */ + /* HSYNC pulse's high level width by counting the */ + /* number of the VCLK. */ + unsigned MVAL:8; /* STN: */ + unsigned ADDVAL:8; /* TFT: Palette Index offset value */ + unsigned PALADDEN:1; /* TFT: Palette Index offset enable. */ + /* 0 = Disable 1 = Enable */ + } reg; + unsigned long all; +} LCDCON4; + +typedef union { + struct { + unsigned HWSWP:1; /* STN/TFT: Half-Word swap control bit. */ + /* 0 = Swap Disable 1 = Swap Enable */ + unsigned BSWP:1; /* STN/TFT: Byte swap control bit. */ + /* 0 = Swap Disable 1 = Swap Enable */ + unsigned ENLEND:1; /* TFT: LEND output signal enable/disable. */ + /* 0 = Disable LEND signal. */ + /* 1 = Enable LEND signal */ + unsigned RESERVED1:1; + unsigned INVENDLINE:1;/* TFT: This bit indicates the LEND signal */ + /* polarity. 0 = normal 1 = inverted */ + unsigned RESERVED2:1; + unsigned INVVDEN:1; /* TFT: This bit indicates the VDEN signal */ + /* polarity. */ + /* 0 = normal 1 = inverted */ + unsigned INVVD:1; /* STN/TFT: This bit indicates the VD (video data) */ + /* pulse polarity. 0 = Normal. */ + /* 1 = VD is inverted. */ + unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */ + /* pulse polarity. 0 = normal 1 = inverted */ + unsigned INVVLINE:1; /* STN/TFT: This bit indicates the VLINE/HSYNC */ + /* pulse polarity. 0 = normal 1 = inverted */ + unsigned INVVCLK:1; /* STN/TFT: This bit controls the polarity of the */ + /* VCLK active edge. 0 = The video data is */ + /* fetched at VCLK falling edge. 1 = The video */ + /* data is fetched at VCLK rising edge */ + unsigned RESERVED3:2; + unsigned SELFREF:1; /* STN: */ + unsigned SLOWCLKSYNC:1; /* STN: */ + unsigned RESERVED4:2; /* must be 0 */ + unsigned HSTATUS:2; /* TFT: Horizontal Status (Read only) */ + /* 00 = HSYNC */ + /* 01 = BACK Porch. */ + /* 10 = ACTIVE */ + /* 11 = FRONT Porch */ + unsigned _VSTATUS:2; /* TFT: Vertical Status (Read only). */ + /* 00 = VSYNC */ + /* 01 = BACK Porch. */ + /* 10 = ACTIVE */ + /* 11 = FRONT Porch */ + } reg; + unsigned long all; +} LCDCON5; + +typedef union { + struct { + unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */ + /* A[21:1] of the start address of the LCD */ + /* frame buffer. */ + unsigned LCDBANK:7; /* A[28:22] */ + } reg; + unsigned long all; +} LCDSADDR1; + +typedef union { + struct { + unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/ + /* of the end address of the LCD frame buffer. */ + /* LCDBASEL = ((the fame end address) >>1) + 1 */ + /* = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */ + } reg; + unsigned long all; +} LCDSADDR2; + +typedef union { + struct { + unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */ + /* words) This value defines the width of the */ + /* view port in the frame */ + unsigned OFFSIZE:11; /* Virtual screen offset size(the number of half */ + /* words) This value defines the difference */ + /* between the address of the last half word */ + /* displayed on the previous LCD line and the */ + /* address of the first half word to be */ + /* displayed in the new LCD line. */ + } reg; + unsigned long all; +} LCDSADDR3; + +/* + * + */ + +typedef union { + struct { + unsigned IISIFENA:1; /* IIS interface enable (start) */ + unsigned IISPSENA:1; /* IIS prescaler enable */ + unsigned RXCHIDLE:1; /* Receive channel idle command */ + unsigned TXCHIDLE:1; /* Transmit channel idle command */ + unsigned RXDMAENA:1; /* Receive DMA service request enable */ + unsigned TXDMAENA:1; /* Transmit DMA service request enable */ + unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */ + unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */ + unsigned LRINDEX:1; /* Left/right channel index (read only) */ + } reg; + unsigned long all; +} IISCON; + +typedef union { + struct { + unsigned SBCLKFS:2; /* Serial bit clock frequency select */ + unsigned MCLKFS:1; /* Master clock frequency select */ + unsigned SDBITS:1; /* Serial data bit per channel */ + unsigned SIFMT:1; /* Serial interface format */ + unsigned ACTLEVCH:1; /* Active level pf left/right channel */ + unsigned TXRXMODE:2; /* Transmit/receive mode select */ + unsigned MODE:1; /* Master/slave mode select */ + } reg; + unsigned long all; +} IISMOD; + +typedef union { + struct { + unsigned PSB:5; /* Prescaler control B */ + unsigned PSA:5; /* Prescaler control A */ + } reg; + unsigned long all; +} IISPSR; + +typedef union { + struct { + unsigned RXFIFOCNT:4; /* (read only) */ + unsigned TXFIFOCNT:4; /* (read only) */ + /*signed RXFIFOENA:1; /* */ + unsigned TXFIFOENA:1; /* */ + unsigned RXFIFOMODE:1; /* */ + unsigned TXFIFOMODE:1; /* */ + } reg; + unsigned long all; +} IISSFIFCON; + +typedef union { + struct { + unsigned FENTRY:16; /* */ + } reg; + unsigned long all; +} IISSFIF; +#endif //ASM + +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT)) + +#define GP32_KEY_SELECT 512 +#define GP32_KEY_START 256 +#define GP32_KEY_A 64 +#define GP32_KEY_B 32 +#define GP32_KEY_L 16 +#define GP32_KEY_R 128 +#define GP32_KEY_UP 8 +#define GP32_KEY_DOWN 2 +#define GP32_KEY_LEFT 1 +#define GP32_KEY_RIGHT 4 + +#endif /*S3C2400_H_*/ diff --git a/bsps/arm/smdk2410/include/s3c2410.h b/bsps/arm/smdk2410/include/s3c2410.h new file mode 100644 index 0000000000..c6a0a0b452 --- /dev/null +++ b/bsps/arm/smdk2410/include/s3c2410.h @@ -0,0 +1,825 @@ +/************************************************ + * NAME : s3c2410.h + * Version : 3.7.2002 + * + * Based on 24x.h for the Samsung Development Board + ************************************************/ + +#ifndef S3C2410_H_ +#define S3C2410_H_ + +/* to be used in assembly code */ +#define rINTOFFSET_ADDR 0x4A000014 +/* Memory control */ +#define rBWSCON (*(volatile unsigned *)0x48000000) +#define rBANKCON0 (*(volatile unsigned *)0x48000004) +#define rBANKCON1 (*(volatile unsigned *)0x48000008) +#define rBANKCON2 (*(volatile unsigned *)0x4800000C) +#define rBANKCON3 (*(volatile unsigned *)0x48000010) +#define rBANKCON4 (*(volatile unsigned *)0x48000014) +#define rBANKCON5 (*(volatile unsigned *)0x48000018) +#define rBANKCON6 (*(volatile unsigned *)0x4800001C) +#define rBANKCON7 (*(volatile unsigned *)0x48000020) +#define rREFRESH (*(volatile unsigned *)0x48000024) +#define rBANKSIZE (*(volatile unsigned *)0x48000028) +#define rMRSRB6 (*(volatile unsigned *)0x4800002C) +#define rMRSRB7 (*(volatile unsigned *)0x48000030) + +/* USB Host Controller */ +#define rHcRevision (*(volatile unsigned *)0x49000000) +#define rHcControl (*(volatile unsigned *)0x49000004) +#define rHcCommonStatus (*(volatile unsigned *)0x49000008) +#define rHcInterruptStatus (*(volatile unsigned *)0x4900000C) +#define rHcInterruptEnable (*(volatile unsigned *)0x49000010) +#define rHcInterruptDisable (*(volatile unsigned *)0x49000014) +#define rHcHCCA (*(volatile unsigned *)0x49000018) +#define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C) +#define rHcControlHeadED (*(volatile unsigned *)0x49000020) +#define rHcControlCurrentED (*(volatile unsigned *)0x49000024) +#define rHcBulkHeadED (*(volatile unsigned *)0x49000028) +#define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C) +#define rHcDoneHead (*(volatile unsigned *)0x49000030) +#define rHcRmInterval (*(volatile unsigned *)0x49000034) +#define rHcFmRemaining (*(volatile unsigned *)0x49000038) +#define rHcFmNumber (*(volatile unsigned *)0x4900003C) +#define rHcPeriodicStart (*(volatile unsigned *)0x49000040) +#define rHcLSThreshold (*(volatile unsigned *)0x49000044) +#define rHcRhDescriptorA (*(volatile unsigned *)0x49000048) +#define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C) +#define rHcRhStatus (*(volatile unsigned *)0x49000050) +#define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054) +#define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058) + +/* INTERRUPT */ +#define rSRCPND (*(volatile unsigned *)0x4A000000) +#define rINTMOD (*(volatile unsigned *)0x4A000004) +#define rINTMSK (*(volatile unsigned *)0x4A000008) +#define rPRIORITY (*(volatile unsigned *)0x4A00000C) +#define rINTPND (*(volatile unsigned *)0x4A000010) +#define rINTOFFSET (*(volatile unsigned *)0x4A000014) +#define rSUBSRCPND (*(volatile unsigned *)0x4A000018) +#define rINTSUBMSK (*(volatile unsigned *)0x4A00001c) + + +/* DMA */ +#define rDISRC0 (*(volatile unsigned *)0x4B000000) +#define rDISRCC0 (*(volatile unsigned *)0x4B000004) +#define rDIDST0 (*(volatile unsigned *)0x4B000008) +#define rDIDSTC0 (*(volatile unsigned *)0x4B00000C) +#define rDCON0 (*(volatile unsigned *)0x4B000010) +#define rDSTAT0 (*(volatile unsigned *)0x4B000014) +#define rDCSRC0 (*(volatile unsigned *)0x4B000018) +#define rDCDST0 (*(volatile unsigned *)0x4B00001C) +#define rDMASKTRIG0 (*(volatile unsigned *)0x4B000020) +#define rDISRC1 (*(volatile unsigned *)0x4B000040) +#define rDISRCC1 (*(volatile unsigned *)0x4B000044) +#define rDIDST1 (*(volatile unsigned *)0x4B000048) +#define rDIDSTC1 (*(volatile unsigned *)0x4B00004C) +#define rDCON1 (*(volatile unsigned *)0x4B000050) +#define rDSTAT1 (*(volatile unsigned *)0x4B000054) +#define rDCSRC1 (*(volatile unsigned *)0x4B000058) +#define rDCDST1 (*(volatile unsigned *)0x4B00005C) +#define rDMASKTRIG1 (*(volatile unsigned *)0x4B000060) +#define rDISRC2 (*(volatile unsigned *)0x4B000080) +#define rDISRCC2 (*(volatile unsigned *)0x4B000084) +#define rDIDST2 (*(volatile unsigned *)0x4B000088) +#define rDIDSTC2 (*(volatile unsigned *)0x4B00008C) +#define rDCON2 (*(volatile unsigned *)0x4B000090) +#define rDSTAT2 (*(volatile unsigned *)0x4B000094) +#define rDCSRC2 (*(volatile unsigned *)0x4B000098) +#define rDCDST2 (*(volatile unsigned *)0x4B00009C) +#define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0) +#define rDISRC3 (*(volatile unsigned *)0x4B0000C0) +#define rDISRCC3 (*(volatile unsigned *)0x4B0000C4) +#define rDIDST3 (*(volatile unsigned *)0x4B0000C8) +#define rDIDSTC3 (*(volatile unsigned *)0x4B0000CC) +#define rDCON3 (*(volatile unsigned *)0x4B0000D0) +#define rDSTAT3 (*(volatile unsigned *)0x4B0000D4) +#define rDCSRC3 (*(volatile unsigned *)0x4B0000D8) +#define rDCDST3 (*(volatile unsigned *)0x4B0000DC) +#define rDMASKTRIG3 (*(volatile unsigned *)0x4B0000E0) + + +/* CLOCK & POWER MANAGEMENT */ +#define rLOCKTIME (*(volatile unsigned *)0x4C000000) +#define rMPLLCON (*(volatile unsigned *)0x4C000004) +#define rUPLLCON (*(volatile unsigned *)0x4C000008) +#define rCLKCON (*(volatile unsigned *)0x4C00000C) +#define rCLKSLOW (*(volatile unsigned *)0x4C000010) +#define rCLKDIVN (*(volatile unsigned *)0x4C000014) + + +/* LCD CONTROLLER */ +#define rLCDCON1 (*(volatile unsigned *)0x4D000000) +#define rLCDCON2 (*(volatile unsigned *)0x4D000004) +#define rLCDCON3 (*(volatile unsigned *)0x4D000008) +#define rLCDCON4 (*(volatile unsigned *)0x4D00000C) +#define rLCDCON5 (*(volatile unsigned *)0x4D000010) +#define rLCDSADDR1 (*(volatile unsigned *)0x4D000014) +#define rLCDSADDR2 (*(volatile unsigned *)0x4D000018) +#define rLCDSADDR3 (*(volatile unsigned *)0x4D00001C) +#define rREDLUT (*(volatile unsigned *)0x4D000020) +#define rGREENLUT (*(volatile unsigned *)0x4D000024) +#define rBLUELUT (*(volatile unsigned *)0x4D000028) +#define rREDLUT (*(volatile unsigned *)0x4D000020) +#define rGREENLUT (*(volatile unsigned *)0x4D000024) +#define rBLUELUT (*(volatile unsigned *)0x4D000028) +#define rDITHMODE (*(volatile unsigned *)0x4D00004C) +#define rTPAL (*(volatile unsigned *)0x4D000050) +#define rLCDINTPND (*(volatile unsigned *)0x4D000054) +#define rLCDSRCPND (*(volatile unsigned *)0x4D000058) +#define rLCDINTMSK (*(volatile unsigned *)0x4D00005C) +#define rTCONSEL (*(volatile unsigned *)0x4D000060) +#define PALETTE 0x4d000400 + +/* NAND Flash */ +#define rNFCONF (*(volatile unsigned *)0x4E000000) +#define rNFCMD (*(volatile unsigned *)0x4E000004) +#define rNFADDR (*(volatile unsigned *)0x4E000008) +#define rNFDATA (*(volatile unsigned *)0x4E00000C) +#define rNFSTAT (*(volatile unsigned *)0x4E000010) +#define rNFECC (*(volatile unsigned *)0x4E000014) + +/* UART */ +#define rULCON0 (*(volatile unsigned char *)0x50000000) +#define rUCON0 (*(volatile unsigned short *)0x50000004) +#define rUFCON0 (*(volatile unsigned char *)0x50000008) +#define rUMCON0 (*(volatile unsigned char *)0x5000000C) +#define rUTRSTAT0 (*(volatile unsigned char *)0x50000010) +#define rUERSTAT0 (*(volatile unsigned char *)0x50000014) +#define rUFSTAT0 (*(volatile unsigned short *)0x50000018) +#define rUMSTAT0 (*(volatile unsigned char *)0x5000001C) +#define rUBRDIV0 (*(volatile unsigned short *)0x50000028) + +#define rULCON1 (*(volatile unsigned char *)0x50004000) +#define rUCON1 (*(volatile unsigned short *)0x50004004) +#define rUFCON1 (*(volatile unsigned char *)0x50004008) +#define rUMCON1 (*(volatile unsigned char *)0x5000400C) +#define rUTRSTAT1 (*(volatile unsigned char *)0x50004010) +#define rUERSTAT1 (*(volatile unsigned char *)0x50004014) +#define rUFSTAT1 (*(volatile unsigned short *)0x50004018) +#define rUMSTAT1 (*(volatile unsigned char *)0x5000401C) +#define rUBRDIV1 (*(volatile unsigned short *)0x50004028) + +#define rULCON2 (*(volatile unsigned char *)0x50008000) +#define rUCON2 (*(volatile unsigned short *)0x50008004) +#define rUFCON2 (*(volatile unsigned char *)0x50008008) +#define rUTRSTAT2 (*(volatile unsigned char *)0x50008010) +#define rUERSTAT2 (*(volatile unsigned char *)0x50008014) +#define rUFSTAT2 (*(volatile unsigned short *)0x50008018) +#define rUBRDIV2 (*(volatile unsigned short *)0x50008028) + +#ifdef __BIG_ENDIAN +#define rUTXH0 (*(volatile unsigned char *)0x50000023) +#define rURXH0 (*(volatile unsigned char *)0x50000027) +#define rUTXH1 (*(volatile unsigned char *)0x50004023) +#define rURXH1 (*(volatile unsigned char *)0x50004027) +#define rUTXH2 (*(volatile unsigned char *)0x50008023) +#define rURXH2 (*(volatile unsigned char *)0x50008027) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x50000027) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x50004027) +#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch) +#define RdURXH2() (*(volatile unsigned char *)0x50008027) + +#define UTXH0 (0x50000020+3) /* byte_access address by DMA */ +#define URXH0 (0x50000024+3) +#define UTXH1 (0x50004020+3) +#define URXH1 (0x50004024+3) +#define UTXH2 (0x50008020+3) +#define URXH2 (0x50008024+3) + +#else /* Little Endian */ +#define rUTXH0 (*(volatile unsigned char *)0x50000020) +#define rURXH0 (*(volatile unsigned char *)0x50000024) +#define rUTXH1 (*(volatile unsigned char *)0x50004020) +#define rURXH1 (*(volatile unsigned char *)0x50004024) +#define rUTXH2 (*(volatile unsigned char *)0x50008020) +#define rURXH2 (*(volatile unsigned char *)0x50008024) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x50000024) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x50004024) +#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) +#define RdURXH2() (*(volatile unsigned char *)0x50008024) + +#define UTXH0 (0x50000020) +#define URXH0 (0x50000024) +#define UTXH1 (0x50004020) +#define URXH1 (0x50004024) +#define UTXH2 (0x50008020) +#define URXH2 (0x50008024) +#endif + + +/* PWM TIMER */ +#define rTCFG0 (*(volatile unsigned *)0x51000000) +#define rTCFG1 (*(volatile unsigned *)0x51000004) +#define rTCON (*(volatile unsigned *)0x51000008) +#define rTCNTB0 (*(volatile unsigned *)0x5100000C) +#define rTCMPB0 (*(volatile unsigned *)0x51000010) +#define rTCNTO0 (*(volatile unsigned *)0x51000014) +#define rTCNTB1 (*(volatile unsigned *)0x51000018) +#define rTCMPB1 (*(volatile unsigned *)0x5100001C) +#define rTCNTO1 (*(volatile unsigned *)0x51000020) +#define rTCNTB2 (*(volatile unsigned *)0x51000024) +#define rTCMPB2 (*(volatile unsigned *)0x51000028) +#define rTCNTO2 (*(volatile unsigned *)0x5100002C) +#define rTCNTB3 (*(volatile unsigned *)0x51000030) +#define rTCMPB3 (*(volatile unsigned *)0x51000034) +#define rTCNTO3 (*(volatile unsigned *)0x51000038) +#define rTCNTB4 (*(volatile unsigned *)0x5100003C) +#define rTCNTO4 (*(volatile unsigned *)0x51000040) + + +/* USB DEVICE */ +#ifdef __BIG_ENDIAN +#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address +#define rPWR_REG (*(volatile unsigned char *)0x52000147) //Power management +#define rEP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear +#define rUSB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear +#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable +#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016f) +#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte +#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte +#define rINDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index +#define rMAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet +#define rEP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status +#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status +#define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018b) +#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status +#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197) +#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count +#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f) +#define rEP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO +#define rEP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO +#define rEP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO +#define rEP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO +#define rEP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO +#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control +#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter +#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter +#define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter +#define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213) +#define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217) +#define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control +#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter +#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter +#define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter +#define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b) +#define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f) +#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control +#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter +#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter +#define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter +#define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253) +#define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257) +#define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control +#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter +#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter +#define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter +#define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b) +#define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f) + +#else // Little Endian +#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address +#define rPWR_REG (*(volatile unsigned char *)0x52000144) //Power management +#define rEP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear +#define rUSB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear +#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable +#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016c) +#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte +#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte +#define rINDEX_REG (*(volatile unsigned char *)0x52000178) //Register index +#define rMAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet +#define rEP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status +#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status +#define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188) +#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status +#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194) +#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count +#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c) +#define rEP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO +#define rEP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO +#define rEP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO +#define rEP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO +#define rEP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO +#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control +#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter +#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter +#define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter +#define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210) +#define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214) +#define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control +#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter +#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter +#define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter +#define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228) +#define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c) +#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control +#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter +#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter +#define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter +#define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250) +#define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254) +#define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control +#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter +#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter +#define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter +#define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268) +#define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c) +#endif // __BIG_ENDIAN + +/* WATCH DOG TIMER */ +#define rWTCON (*(volatile unsigned *)0x53000000) +#define rWTDAT (*(volatile unsigned *)0x53000004) +#define rWTCNT (*(volatile unsigned *)0x53000008) + + +/* IIC */ +#define rIICCON (*(volatile unsigned *)0x54000000) +#define rIICSTAT (*(volatile unsigned *)0x54000004) +#define rIICADD (*(volatile unsigned *)0x54000008) +#define rIICDS (*(volatile unsigned *)0x5400000C) + + +/* IIS */ +#define rIISCON (*(volatile unsigned *)0x55000000) +#define rIISMOD (*(volatile unsigned *)0x55000004) +#define rIISPSR (*(volatile unsigned *)0x55000008) +#define rIISFIFCON (*(volatile unsigned *)0x5500000C) + +#ifdef __BIG_ENDIAN +#define IISFIFO ((volatile unsigned short *)0x55000012) + +#else /* Little Endian */ +#define IISFIFO ((volatile unsigned short *)0x55000010) +#endif + + +/* I/O PORT */ +#define rGPACON (*(volatile unsigned *)0x56000000) //Port A control +#define rGPADAT (*(volatile unsigned *)0x56000004) //Port A data + +#define rGPBCON (*(volatile unsigned *)0x56000010) //Port B control +#define rGPBDAT (*(volatile unsigned *)0x56000014) //Port B data +#define rGPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B + +#define rGPCCON (*(volatile unsigned *)0x56000020) //Port C control +#define rGPCDAT (*(volatile unsigned *)0x56000024) //Port C data +#define rGPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C + +#define rGPDCON (*(volatile unsigned *)0x56000030) //Port D control +#define rGPDDAT (*(volatile unsigned *)0x56000034) //Port D data +#define rGPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D + +#define rGPECON (*(volatile unsigned *)0x56000040) //Port E control +#define rGPEDAT (*(volatile unsigned *)0x56000044) //Port E data +#define rGPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E + +#define rGPFCON (*(volatile unsigned *)0x56000050) //Port F control +#define rGPFDAT (*(volatile unsigned *)0x56000054) //Port F data +#define rGPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F + +#define rGPGCON (*(volatile unsigned *)0x56000060) //Port G control +#define rGPGDAT (*(volatile unsigned *)0x56000064) //Port G data +#define rGPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G + +#define rGPHCON (*(volatile unsigned *)0x56000070) //Port H control +#define rGPHDAT (*(volatile unsigned *)0x56000074) //Port H data +#define rGPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H + +#define rMISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control +#define rDCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control +#define rEXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control register 0 +#define rEXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control register 1 +#define rEXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control register 2 +#define rEINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved +#define rEINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved +#define rEINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control register 2 +#define rEINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control register 3 +#define rEINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask +#define rEINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending +#define rGSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status +#define rGSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32440000) + +/* RTC */ +#ifdef __BIG_ENDIAN +#define rRTCCON (*(volatile unsigned char *)0x57000043) //RTC control +#define rTICNT (*(volatile unsigned char *)0x57000047) //Tick time count +#define rRTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control +#define rALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second +#define rALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute +#define rALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour +#define rALMDATE (*(volatile unsigned char *)0x57000063) //Alarm date //edited by junon +#define rALMMON (*(volatile unsigned char *)0x57000067) //Alarm month +#define rALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year +#define rRTCRST (*(volatile unsigned char *)0x5700006f) //RTC round reset +#define rBCDSEC (*(volatile unsigned char *)0x57000073) //BCD second +#define rBCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute +#define rBCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour +#define rBCDDATE (*(volatile unsigned char *)0x5700007f) //BCD date //edited by junon +#define rBCDDAY (*(volatile unsigned char *)0x57000083) //BCD day //edited by junon +#define rBCDMON (*(volatile unsigned char *)0x57000087) //BCD month +#define rBCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year + +#else //Little Endian +#define rRTCCON (*(volatile unsigned char *)0x57000040) //RTC control +#define rTICNT (*(volatile unsigned char *)0x57000044) //Tick time count +#define rRTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control +#define rALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second +#define rALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute +#define rALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour +#define rALMDATE (*(volatile unsigned char *)0x57000060) //Alarm date // edited by junon +#define rALMMON (*(volatile unsigned char *)0x57000064) //Alarm month +#define rALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year +#define rRTCRST (*(volatile unsigned char *)0x5700006c) //RTC round reset +#define rBCDSEC (*(volatile unsigned char *)0x57000070) //BCD second +#define rBCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute +#define rBCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour +#define rBCDDATE (*(volatile unsigned char *)0x5700007c) //BCD date //edited by junon +#define rBCDDAY (*(volatile unsigned char *)0x57000080) //BCD day //edited by junon +#define rBCDMON (*(volatile unsigned char *)0x57000084) //BCD month +#define rBCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year +#endif //RTC + + +/* ADC */ +#define rADCCON (*(volatile unsigned *)0x58000000) +#define rADCTSC (*(volatile unsigned *)0x58000004) +#define rADCDLY (*(volatile unsigned *)0x58000008) +#define rADCDAT0 (*(volatile unsigned *)0x5800000c) +#define rADCDAT1 (*(volatile unsigned *)0x58000010) + + +/* SPI */ +#define rSPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control +#define rSPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status +#define rSPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control +#define rSPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud rate prescaler +#define rSPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data +#define rSPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data + +#define rSPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control +#define rSPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status +#define rSPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control +#define rSPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud rate prescaler +#define rSPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data +#define rSPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data + +/* SD interface */ +#define rSDICON (*(volatile unsigned *)0x5a000000) //SDI control +#define rSDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud rate prescaler +#define rSDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument +#define rSDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control +#define rSDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status +#define rSDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI response 0 +#define rSDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI response 1 +#define rSDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI response 2 +#define rSDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI response 3 +#define rSDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer +#define rSDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size +#define rSDIDATCON (*(volatile unsigned *)0x5a00002c) //SDI data control +#define rSDIDATCNT (*(volatile unsigned *)0x5a000030) //SDI data remain counter +#define rSDIDATSTA (*(volatile unsigned *)0x5a000034) //SDI data status +#define rSDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status +#define rSDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask. edited for 2440A + +#ifdef __BIG_ENDIAN +#define rSDIDAT (*(volatile unsigned *)0x5a00003F) //SDI data +#define SDIDAT 0x5a00003F +#else // Little Endian +#define rSDIDAT (*(volatile unsigned *)0x5a00003C) //SDI data +#define SDIDAT 0x5a00003C +#endif //SD Interface + + +#define _ISR_STARTADDRESS rtems_vector_table +/* ISR */ +#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) +#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) +#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) +#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC)) +#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) +#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) +#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) +#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C)) + +#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) +#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) +#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) +#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C)) +#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) +#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) +#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C)) +#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) +#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) +#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) +#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C)) +#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) +#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) +#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) +#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C)) +#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) +#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) +#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) +#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C)) +#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) +#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74)) +#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78)) +#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C)) +#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) +#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) +#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C)) +#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) +#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) +#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) +#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0)) + + +/* PENDING BIT */ +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4_7 (0x1<<4) +#define BIT_EINT8_23 (0x1<<5) +#define BIT_BAT_FLT (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UART2 (0x1<<15) +#define BIT_LCD (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_SDI (0x1<<21) +#define BIT_SPI0 (0x1<<22) +#define BIT_UART1 (0x1<<23) +#define BIT_USBD (0x1<<25) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UART0 (0x1<<28) +#define BIT_SPI1 (0x1<<29) +#define BIT_RTC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xFFFFFFFF) + +#define ClearPending(bit) {\ + rSRCPND = bit;\ + rINTPND = bit;\ + rINTPND;\ + } +/* Wait until rINTPND is changed for the case that the ISR is very short. */ +#ifndef ASM +/* Typedefs */ +typedef union { + struct _reg { + unsigned SM_BIT:1; /* Enters STOP mode. This bit isn't be */ + /* cleared automatically. */ + unsigned Reserved:1; /* SL_IDLE mode option. This bit isn't cleared */ + /* automatically. To enter SL_IDLE mode, */ + /* CLKCON register has to be 0xe. */ + unsigned IDLE_BIT:1; /* Enters IDLE mode. This bit isn't be cleared */ + /* automatically. */ + unsigned POWER_OFF:1; + unsigned NAND_flash:1; + unsigned LCDC:1; /* Controls HCLK into LCDC block */ + unsigned USB_host:1; /* Controls HCLK into USB host block */ + unsigned USB_device:1; /* Controls PCLK into USB device block */ + unsigned PWMTIMER:1; /* Controls PCLK into PWMTIMER block */ + unsigned SDI:1; /* Controls PCLK into MMC interface block */ + unsigned UART0:1; /* Controls PCLK into UART0 block */ + unsigned UART1:1; /* Controls PCLK into UART1 block */ + unsigned UART2:1; /* Controls PCLK into UART1 block */ + unsigned GPIO:1; /* Controls PCLK into GPIO block */ + unsigned RTC:1; /* Controls PCLK into RTC control block. Even if */ + /* this bit is cleared to 0, RTC timer is alive. */ + unsigned ADC:1; /* Controls PCLK into ADC block */ + unsigned IIC:1; /* Controls PCLK into IIC block */ + unsigned IIS:1; /* Controls PCLK into IIS block */ + unsigned SPI:1; /* Controls PCLK into SPI block */ + } reg; + unsigned long all; +} CLKCON; + +typedef union +{ + struct { + unsigned ENVID:1; /* LCD video output and the logic 1=enable/0=disable. */ + unsigned BPPMODE:4; /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */ + /* 1110 = 16 bpp TFT skipmode */ + unsigned PNRMODE:2; /* TFT: 3 */ + unsigned MMODE:1; /* This bit determines the toggle rate of the VM. */ + /* 0 = Each Frame, 1 = The rate defined by the MVAL */ + unsigned CLKVAL:10; /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */ + unsigned LINECNT:10; /* (read only) These bits provide the status of the */ + /* line counter. Down count from LINEVAL to 0 */ + } reg; + unsigned long all; +} LCDCON1; + +typedef union { + struct { + unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */ + /* VSYNC pulse's high level width by counting the */ + /* number of inactive lines. */ + unsigned VFPD:8; /* TFT: Vertical front porch is the number of */ + /* inactive lines at the end of a frame, before */ + /* vertical synchronization period. */ + unsigned LINEVAL:10; /* TFT/STN: These bits determine the vertical size */ + /* of LCD panel. */ + unsigned VBPD:8; /* TFT: Vertical back porch is the number of inactive */ + /* lines at the start of a frame, after */ + /* vertical synchronization period. */ + } reg; + unsigned long all; +} LCDCON2; + +typedef union { + struct { + unsigned HFPD:8; /* TFT: Horizontal front porch is the number of */ + /* VCLK periods between the end of active data */ + /* and the rising edge of HSYNC. */ + unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */ + /* size of LCD panel. 2n bytes. */ + unsigned HBPD:7; /* TFT: Horizontal back porch is the number of VCLK */ + /* periods between the falling edge of HSYNC and */ + /* the start of active data. */ + } reg; + unsigned long all; +} LCDCON3; + +typedef union { + struct { + unsigned HSPW:8; /* TFT: Horizontal sync pulse width determines the */ + /* HSYNC pulse's high level width by counting the */ + /* number of the VCLK. */ + unsigned MVAL:8; /* STN: */ + } reg; + unsigned long all; +} LCDCON4; + +typedef union { + struct { + unsigned HWSWP:1; /* STN/TFT: Half-Word swap control bit. */ + /* 0 = Swap Disable 1 = Swap Enable */ + unsigned BSWP:1; /* STN/TFT: Byte swap control bit. */ + /* 0 = Swap Disable 1 = Swap Enable */ + unsigned ENLEND:1; /* TFT: LEND output signal enable/disable. */ + /* 0 = Disable LEND signal. */ + /* 1 = Enable LEND signal */ + unsigned PWREN:1; + unsigned INVLEND:1;/* TFT: This bit indicates the LEND signal */ + /* polarity. 0 = normal 1 = inverted */ + unsigned INVPWREN:1; + unsigned INVVDEN:1; /* TFT: This bit indicates the VDEN signal */ + /* polarity. */ + /* 0 = normal 1 = inverted */ + unsigned INVVD:1; /* STN/TFT: This bit indicates the VD (video data) */ + /* pulse polarity. 0 = Normal. */ + /* 1 = VD is inverted. */ + unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */ + /* pulse polarity. 0 = normal 1 = inverted */ + unsigned INVVLINE:1; /* STN/TFT: This bit indicates the VLINE/HSYNC */ + /* pulse polarity. 0 = normal 1 = inverted */ + unsigned INVVCLK:1; /* STN/TFT: This bit controls the polarity of the */ + /* VCLK active edge. 0 = The video data is */ + /* fetched at VCLK falling edge. 1 = The video */ + /* data is fetched at VCLK rising edge */ + unsigned FRM565:1; + unsigned BPP24BL:1; + unsigned HSTATUS:2; /* TFT: Horizontal Status (Read only) */ + /* 00 = HSYNC */ + /* 01 = BACK Porch. */ + /* 10 = ACTIVE */ + /* 11 = FRONT Porch */ + unsigned _VSTATUS:2; /* TFT: Vertical Status (Read only). */ + /* 00 = VSYNC */ + /* 01 = BACK Porch. */ + /* 10 = ACTIVE */ + /* 11 = FRONT Porch */ + unsigned RESERVED:16; + } reg; + unsigned long all; +} LCDCON5; + +typedef union { + struct { + unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */ + /* A[21:1] of the start address of the LCD */ + /* frame buffer. */ + unsigned LCDBANK:9; /* A[28:22] */ + } reg; + unsigned long all; +} LCDSADDR1; + +typedef union { + struct { + unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/ + /* of the end address of the LCD frame buffer. */ + /* LCDBASEL = ((the fame end address) >>1) + 1 */ + /* = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */ + } reg; + unsigned long all; +} LCDSADDR2; + +typedef union { + struct { + unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */ + /* words) This value defines the width of the */ + /* view port in the frame */ + unsigned OFFSIZE:11; /* Virtual screen offset size(the number of half */ + /* words) This value defines the difference */ + /* between the address of the last half word */ + /* displayed on the previous LCD line and the */ + /* address of the first half word to be */ + /* displayed in the new LCD line. */ + } reg; + unsigned long all; +} LCDSADDR3; + +/* + * + */ + +typedef union { + struct { + unsigned IISIFENA:1; /* IIS interface enable (start) */ + unsigned IISPSENA:1; /* IIS prescaler enable */ + unsigned RXCHIDLE:1; /* Receive channel idle command */ + unsigned TXCHIDLE:1; /* Transmit channel idle command */ + unsigned RXDMAENA:1; /* Receive DMA service request enable */ + unsigned TXDMAENA:1; /* Transmit DMA service request enable */ + unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */ + unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */ + unsigned LRINDEX:1; /* Left/right channel index (read only) */ + } reg; + unsigned long all; +} IISCON; + +typedef union { + struct { + unsigned SBCLKFS:2; /* Serial bit clock frequency select */ + unsigned MCLKFS:1; /* Master clock frequency select */ + unsigned SDBITS:1; /* Serial data bit per channel */ + unsigned SIFMT:1; /* Serial interface format */ + unsigned ACTLEVCH:1; /* Active level pf left/right channel */ + unsigned TXRXMODE:2; /* Transmit/receive mode select */ + unsigned MODE:1; /* Master/slave mode select */ + } reg; + unsigned long all; +} IISMOD; + +typedef union { + struct { + unsigned PSB:5; /* Prescaler control B */ + unsigned PSA:5; /* Prescaler control A */ + } reg; + unsigned long all; +} IISPSR; + +typedef union { + struct { + unsigned RXFIFOCNT:6; /* (read only) */ + unsigned TXFIFOCNT:6; /* (read only) */ + unsigned RXFIFOENA:1; /* */ + unsigned TXFIFOENA:1; /* */ + unsigned RXFIFOMODE:1; /* */ + unsigned TXFIFOMODE:1; /* */ + } reg; + unsigned long all; +} IISSFIFCON; + +typedef union { + struct { + unsigned FENTRY:16; /* */ + } reg; + unsigned long all; +} IISSFIF; +#endif //ASM + +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT)) + +#define SMDK2410_KEY_SELECT 512 +#define SMDK2410_KEY_START 256 +#define SMDK2410_KEY_A 64 +#define SMDK2410_KEY_B 32 +#define SMDK2410_KEY_L 16 +#define SMDK2410_KEY_R 128 +#define SMDK2410_KEY_UP 8 +#define SMDK2410_KEY_DOWN 2 +#define SMDK2410_KEY_LEFT 1 +#define SMDK2410_KEY_RIGHT 4 + +#endif /*S3C2410_H_*/ diff --git a/bsps/arm/smdk2410/include/s3c24xx.h b/bsps/arm/smdk2410/include/s3c24xx.h new file mode 100644 index 0000000000..914b867abf --- /dev/null +++ b/bsps/arm/smdk2410/include/s3c24xx.h @@ -0,0 +1,17 @@ +/************************************************ + * NAME : s3c2400.h + * Version : 4.18.2008 + * + * share code for different Samsung CPU + ************************************************/ + +#ifndef S3C24XX_H_ +#define S3C24XX_H_ + +#ifdef CPU_S3C2400 +#include +#elif defined CPU_S3C2410 +#include +#endif + +#endif /*S3C24XX_H_*/ diff --git a/bsps/arm/smdk2410/include/smc.h b/bsps/arm/smdk2410/include/smc.h new file mode 100644 index 0000000000..10ec14a771 --- /dev/null +++ b/bsps/arm/smdk2410/include/smc.h @@ -0,0 +1,44 @@ +/** + * @file + * @ingroup smdk2410_smc + * @brief SMC disk driver initialization entry point + */ + +#ifndef __SMC_H__ +#define __SMC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#include "rtems/blkdev.h" + +/** + * @defgroup smdk2410_smc SMC Disk Driver + * @ingroup arm_smdk2410 + * @brief SMC Disk Driver Support + * @{ + */ + +/** + * @brief smc_initialize + * SMC disk driver initialization entry point. + */ +rtems_device_driver +smc_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +#define SMC_DRIVER_TABLE_ENTRY \ + { smc_initialize, GENERIC_BLOCK_DEVICE_DRIVER_ENTRIES } + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/arm/smdk2410/include/tm27.h b/bsps/arm/smdk2410/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/smdk2410/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/stm32f4/headers.am b/bsps/arm/stm32f4/headers.am new file mode 100644 index 0000000000..f1270b546e --- /dev/null +++ b/bsps/arm/stm32f4/headers.am @@ -0,0 +1,29 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/stm32f4/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/io.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/rcc.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32_i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32_usart.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f10xxx_exti.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f10xxx_gpio.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f10xxx_rcc.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_exti.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_gpio.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_otgfs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_tim.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/usart.h diff --git a/bsps/arm/stm32f4/include/bsp.h b/bsps/arm/stm32f4/include/bsp.h new file mode 100644 index 0000000000..50052bc810 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp.h @@ -0,0 +1,54 @@ +/** + * @file + * @ingroup arm_stm34f4 + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup arm_stm32f4 STM32F4 Support + * @ingroup bsp_arm + * @brief STM32f4 Support Package + * @{ + */ + +#ifndef LIBBSP_ARM_STM32F4_BSP_H +#define LIBBSP_ARM_STM32F4_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (13 << 4) + +#define BSP_ARMV7M_SYSTICK_PRIORITY (14 << 4) + +#define BSP_ARMV7M_SYSTICK_FREQUENCY STM32F4_HCLK + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_STM32F4_BSP_H */ diff --git a/bsps/arm/stm32f4/include/bsp/i2c.h b/bsps/arm/stm32f4/include/bsp/i2c.h new file mode 100644 index 0000000000..fa18b1f92f --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/i2c.h @@ -0,0 +1,96 @@ +/** + * @file + * @ingroup stm32f4_i2c I2C Support + * @brief I2C-module. + */ + +/* + * Copyright (c) 2013 Christian Mauderer. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* The I2C-module can not run with libi2c. The reason for this is, that libi2c + * needs a possibility to generate a stop condition separately. This controller + * wants to generate the condition automatically when sending or receiving data. + */ + +#ifndef LIBBSP_ARM_STM32F4_I2C_H +#define LIBBSP_ARM_STM32F4_I2C_H + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup stm32f4_i2c I2C Support + * @ingroup arm_stm32f4 + * @brief I2C Module + * @{ + */ + +typedef struct { + /** + * @brief The address of the slave without the read write bit. + * A 7-Bit address should be placed in the bits [6..0] + */ + uint16_t addr; + /** @brief Read (true) or write (false) data */ + bool read; + /** @brief Size of data to read or write */ + size_t len; + /** @brief Buffer for data */ + uint8_t *buf; +} stm32f4_i2c_message; + +typedef struct { + volatile stm32f4_i2c *regs; + size_t index; + rtems_vector_number vector; + rtems_id mutex; + rtems_id task_id; + uint8_t *data; + uint8_t *last; + size_t len; + bool read; + uint8_t addr_with_rw; +} stm32f4_i2c_bus_entry; + +/** @brief Initialise the i2c module. */ +rtems_status_code stm32f4_i2c_init(stm32f4_i2c_bus_entry *e); + +/** @brief Process a i2c message */ +rtems_status_code stm32f4_i2c_process_message( + stm32f4_i2c_bus_entry *e, + stm32f4_i2c_message *msg +); + +/** @brief Set another baud rate than the default one */ +rtems_status_code stm32f4_i2c_set_bitrate( + stm32f4_i2c_bus_entry *e, + uint32_t br +); + +extern stm32f4_i2c_bus_entry *const stm32f4_i2c1; +extern stm32f4_i2c_bus_entry *const stm32f4_i2c2; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_STM32F4_I2C_H */ diff --git a/bsps/arm/stm32f4/include/bsp/io.h b/bsps/arm/stm32f4/include/bsp/io.h new file mode 100644 index 0000000000..b7f8669cba --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/io.h @@ -0,0 +1,416 @@ +/** + * @file + * @ingroup stm32f4_io + * @brief IO support. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_IO_H +#define LIBBSP_ARM_STM32F4_IO_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup stm32f4_io IO Support + * @ingroup arm_stm32f4 + * @brief IO Support + * @{ + */ + +#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff) + +#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf) + +#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf) + +#ifdef STM32F4_FAMILY_F4XXXX + +/** + * @name Family F4XXXX + * @{ + */ + +typedef enum { + STM32F4_GPIO_MODE_INPUT, + STM32F4_GPIO_MODE_OUTPUT, + STM32F4_GPIO_MODE_AF, + STM32F4_GPIO_MODE_ANALOG +} stm32f4_gpio_mode; + +typedef enum { + STM32F4_GPIO_OTYPE_PUSH_PULL, + STM32F4_GPIO_OTYPE_OPEN_DRAIN +} stm32f4_gpio_otype; + +typedef enum { + STM32F4_GPIO_OSPEED_2_MHZ, + STM32F4_GPIO_OSPEED_25_MHZ, + STM32F4_GPIO_OSPEED_50_MHZ, + STM32F4_GPIO_OSPEED_100_MHZ +} stm32f4_gpio_ospeed; + +typedef enum { + STM32F4_GPIO_NO_PULL, + STM32F4_GPIO_PULL_UP, + STM32F4_GPIO_PULL_DOWN +} stm32f4_gpio_pull; + +typedef enum { + STM32F4_GPIO_AF_SYSTEM = 0, + STM32F4_GPIO_AF_TIM1 = 1, + STM32F4_GPIO_AF_TIM2 = 1, + STM32F4_GPIO_AF_TIM3 = 2, + STM32F4_GPIO_AF_TIM4 = 2, + STM32F4_GPIO_AF_TIM5 = 2, + STM32F4_GPIO_AF_TIM8 = 3, + STM32F4_GPIO_AF_TIM9 = 3, + STM32F4_GPIO_AF_TIM10 = 3, + STM32F4_GPIO_AF_TIM11 = 3, + STM32F4_GPIO_AF_I2C1 = 4, + STM32F4_GPIO_AF_I2C2 = 4, + STM32F4_GPIO_AF_I2C3 = 4, + STM32F4_GPIO_AF_SPI1 = 5, + STM32F4_GPIO_AF_SPI2 = 5, + STM32F4_GPIO_AF_SPI3 = 6, + STM32F4_GPIO_AF_USART1 = 7, + STM32F4_GPIO_AF_USART2 = 7, + STM32F4_GPIO_AF_USART3 = 7, + STM32F4_GPIO_AF_UART4 = 8, + STM32F4_GPIO_AF_UART5 = 8, + STM32F4_GPIO_AF_USART6 = 8, + STM32F4_GPIO_AF_CAN1 = 9, + STM32F4_GPIO_AF_CAN2 = 9, + STM32F4_GPIO_AF_TIM12 = 9, + STM32F4_GPIO_AF_TIM13 = 9, + STM32F4_GPIO_AF_TIM14 = 9, + STM32F4_GPIO_AF_OTG_FS = 10, + STM32F4_GPIO_AF_OTG_HS = 10, + STM32F4_GPIO_AF_ETH = 11, + STM32F4_GPIO_AF_FSMC = 12, + STM32F4_GPIO_AF_OTG_HS_FS = 12, + STM32F4_GPIO_AF_SDIO = 12, + STM32F4_GPIO_AF_DCMI = 13, + STM32F4_GPIO_AF_EVENTOUT = 15 +} stm32f4_gpio_af; + +typedef union { + struct { + uint32_t pin_first : 8; + uint32_t pin_last : 8; + uint32_t mode : 2; + uint32_t otype : 1; + uint32_t ospeed : 2; + uint32_t pupd : 2; + uint32_t output : 1; + uint32_t af : 4; + uint32_t reserved : 4; + } fields; + + uint32_t value; +} stm32f4_gpio_config; + +#define STM32F4_GPIO_CONFIG_TERMINAL \ + { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } } + +/** @} */ + +#endif /* STM32F4_FAMILY_F4XXXX */ +#ifdef STM32F4_FAMILY_F10XXX + +/** + * @name Family F10XXX + * @{ + */ + +typedef enum { + STM32F4_GPIO_MODE_INPUT, + STM32F4_GPIO_MODE_OUTPUT_10MHz, + STM32F4_GPIO_MODE_OUTPUT_2MHz, + STM32F4_GPIO_MODE_OUTPUT_50MHz +} stm32f4_gpio_mode; + +typedef enum { + STM32F4_GPIO_CNF_IN_ANALOG = 0, + STM32F4_GPIO_CNF_IN_FLOATING = 1, + STM32F4_GPIO_CNF_IN_PULL_UPDOWN = 2, + + STM32F4_GPIO_CNF_OUT_GPIO_PP = 0, + STM32F4_GPIO_CNF_OUT_GPIO_OD = 1, + STM32F4_GPIO_CNF_OUT_AF_PP = 2, + STM32F4_GPIO_CNF_OUT_AF_OD = 3, +} stm32f4_gpio_cnf; + +typedef enum { + STM32F4_GPIO_REMAP_DONT_CHANGE, + STM32F4_GPIO_REMAP_SPI1_0, + STM32F4_GPIO_REMAP_SPI1_1, + STM32F4_GPIO_REMAP_I2C1_0, + STM32F4_GPIO_REMAP_I2C1_1, + STM32F4_GPIO_REMAP_USART1_0, + STM32F4_GPIO_REMAP_USART1_1, + STM32F4_GPIO_REMAP_USART2_0, + STM32F4_GPIO_REMAP_USART2_1, + STM32F4_GPIO_REMAP_USART3_0, + STM32F4_GPIO_REMAP_USART3_1, + STM32F4_GPIO_REMAP_USART3_3, + STM32F4_GPIO_REMAP_TIM1_0, + STM32F4_GPIO_REMAP_TIM1_1, + STM32F4_GPIO_REMAP_TIM1_3, + STM32F4_GPIO_REMAP_TIM2_0, + STM32F4_GPIO_REMAP_TIM2_1, + STM32F4_GPIO_REMAP_TIM2_2, + STM32F4_GPIO_REMAP_TIM2_3, + STM32F4_GPIO_REMAP_TIM3_0, + STM32F4_GPIO_REMAP_TIM3_2, + STM32F4_GPIO_REMAP_TIM3_3, + STM32F4_GPIO_REMAP_TIM4_0, + STM32F4_GPIO_REMAP_TIM4_1, + STM32F4_GPIO_REMAP_CAN1_0, + STM32F4_GPIO_REMAP_CAN1_2, + STM32F4_GPIO_REMAP_CAN1_3, + STM32F4_GPIO_REMAP_PD01_0, + STM32F4_GPIO_REMAP_PD01_1, + STM32F4_GPIO_REMAP_TIM5CH4_0, + STM32F4_GPIO_REMAP_TIM5CH4_1, + STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0, + STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1, + STM32F4_GPIO_REMAP_ADC1_ETRGREG_0, + STM32F4_GPIO_REMAP_ADC1_ETRGREG_1, + STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0, + STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1, + STM32F4_GPIO_REMAP_ADC2_ETRGREG_0, + STM32F4_GPIO_REMAP_ADC2_ETRGREG_1, + STM32F4_GPIO_REMAP_ETH_0, + STM32F4_GPIO_REMAP_ETH_1, + STM32F4_GPIO_REMAP_CAN2_0, + STM32F4_GPIO_REMAP_CAN2_1, + STM32F4_GPIO_REMAP_MII_RMII_0, + STM32F4_GPIO_REMAP_MII_RMII_1, + STM32F4_GPIO_REMAP_SWJ_0, + STM32F4_GPIO_REMAP_SWJ_1, + STM32F4_GPIO_REMAP_SWJ_2, + STM32F4_GPIO_REMAP_SWJ_4, + STM32F4_GPIO_REMAP_SPI3_0, + STM32F4_GPIO_REMAP_SPI3_1, + STM32F4_GPIO_REMAP_TIM2ITR1_0, + STM32F4_GPIO_REMAP_TIM2ITR1_1, + STM32F4_GPIO_REMAP_PTP_PPS_0, + STM32F4_GPIO_REMAP_PTP_PPS_1, + STM32F4_GPIO_REMAP_TIM15_0, + STM32F4_GPIO_REMAP_TIM15_1, + STM32F4_GPIO_REMAP_TIM16_0, + STM32F4_GPIO_REMAP_TIM16_1, + STM32F4_GPIO_REMAP_TIM17_0, + STM32F4_GPIO_REMAP_TIM17_1, + STM32F4_GPIO_REMAP_CEC_0, + STM32F4_GPIO_REMAP_CEC_1, + STM32F4_GPIO_REMAP_TIM1_DMA_0, + STM32F4_GPIO_REMAP_TIM1_DMA_1, + STM32F4_GPIO_REMAP_TIM9_0, + STM32F4_GPIO_REMAP_TIM9_1, + STM32F4_GPIO_REMAP_TIM10_0, + STM32F4_GPIO_REMAP_TIM10_1, + STM32F4_GPIO_REMAP_TIM11_0, + STM32F4_GPIO_REMAP_TIM11_1, + STM32F4_GPIO_REMAP_TIM13_0, + STM32F4_GPIO_REMAP_TIM13_1, + STM32F4_GPIO_REMAP_TIM14_0, + STM32F4_GPIO_REMAP_TIM14_1, + STM32F4_GPIO_REMAP_FSMC_0, + STM32F4_GPIO_REMAP_FSMC_1, + STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0, + STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1, + STM32F4_GPIO_REMAP_TIM12_0, + STM32F4_GPIO_REMAP_TIM12_1, + STM32F4_GPIO_REMAP_MISC_0, + STM32F4_GPIO_REMAP_MISC_1, +} stm32f4_gpio_remap; + +typedef union { + struct { + uint32_t pin_first : 8; + uint32_t pin_last : 8; + uint32_t mode : 2; + uint32_t cnf : 2; + uint32_t output : 1; + uint32_t remap : 8; + uint32_t reserved : 3; + } fields; + + uint32_t value; +} stm32f4_gpio_config; + +#define STM32F4_GPIO_CONFIG_TERMINAL \ + { { 0xff, 0xff, 0x3, 0x3, 0x1, 0xff, 0x7 } } + +/** @} */ + +#endif /* STM32F4_FAMILY_F10XXX */ + +extern const stm32f4_gpio_config stm32f4_start_config_gpio []; + +void stm32f4_gpio_set_clock(int pin, bool set); + +void stm32f4_gpio_set_config(const stm32f4_gpio_config *config); + +/** + * @brief Sets the GPIO configuration of an array terminated by + * STM32F4_GPIO_CONFIG_TERMINAL. + */ +void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs); + +void stm32f4_gpio_set_output(int pin, bool set); + +bool stm32f4_gpio_get_input(int pin); + +#ifdef STM32F4_FAMILY_F4XXXX + +/** + * @name Family F4XXXX + * @{ + */ + +#define STM32F4_PIN_USART(port, idx, altfunc) \ + { \ + { \ + .pin_first = STM32F4_GPIO_PIN(port, idx), \ + .pin_last = STM32F4_GPIO_PIN(port, idx), \ + .mode = STM32F4_GPIO_MODE_AF, \ + .otype = STM32F4_GPIO_OTYPE_PUSH_PULL, \ + .ospeed = STM32F4_GPIO_OSPEED_2_MHZ, \ + .pupd = STM32F4_GPIO_PULL_UP, \ + .af = altfunc \ + } \ + } + +#define STM32F4_PIN_USART1_TX_PA9 STM32F4_PIN_USART(0, 9, STM32F4_GPIO_AF_USART1) +#define STM32F4_PIN_USART1_TX_PB6 STM32F4_PIN_USART(1, 6, STM32F4_GPIO_AF_USART1) +#define STM32F4_PIN_USART1_RX_PA10 STM32F4_PIN_USART(0, 10, STM32F4_GPIO_AF_USART1) +#define STM32F4_PIN_USART1_RX_PB7 STM32F4_PIN_USART(1, 7, STM32F4_GPIO_AF_USART1) + +#define STM32F4_PIN_USART2_TX_PA2 STM32F4_PIN_USART(0, 2, STM32F4_GPIO_AF_USART2) +#define STM32F4_PIN_USART2_TX_PD5 STM32F4_PIN_USART(3, 5, STM32F4_GPIO_AF_USART2) +#define STM32F4_PIN_USART2_RX_PA3 STM32F4_PIN_USART(0, 3, STM32F4_GPIO_AF_USART2) +#define STM32F4_PIN_USART2_RX_PD6 STM32F4_PIN_USART(3, 6, STM32F4_GPIO_AF_USART2) + +#define STM32F4_PIN_USART3_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_USART3) +#define STM32F4_PIN_USART3_TX_PD8 STM32F4_PIN_USART(3, 8, STM32F4_GPIO_AF_USART3) +#define STM32F4_PIN_USART3_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_USART3) +#define STM32F4_PIN_USART3_RX_PD9 STM32F4_PIN_USART(3, 9, STM32F4_GPIO_AF_USART3) + +#define STM32F4_PIN_UART4_TX_PA0 STM32F4_PIN_USART(0, 0, STM32F4_GPIO_AF_UART4) +#define STM32F4_PIN_UART4_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_UART4) +#define STM32F4_PIN_UART4_RX_PA1 STM32F4_PIN_USART(0, 1, STM32F4_GPIO_AF_UART4) +#define STM32F4_PIN_UART4_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_UART4) + +#define STM32F4_PIN_UART5_TX_PC12 STM32F4_PIN_USART(2, 12, STM32F4_GPIO_AF_UART5) +#define STM32F4_PIN_UART5_RX_PD2 STM32F4_PIN_USART(3, 2, STM32F4_GPIO_AF_UART5) + +#define STM32F4_PIN_USART6_TX_PC6 STM32F4_PIN_USART(2, 6, STM32F4_GPIO_AF_USART6) +#define STM32F4_PIN_USART6_RX_PC7 STM32F4_PIN_USART(2, 7, STM32F4_GPIO_AF_USART6) + +/** @} */ + +#endif /* STM32F4_FAMILY_F4XXXX */ +#ifdef STM32F4_FAMILY_F10XXX + +/** + * @name Family F10XXX + * @{ + */ + +#define STM32F4_PIN_USART_TX(port, idx, remapvalue) \ + { \ + { \ + .pin_first = STM32F4_GPIO_PIN(port, idx), \ + .pin_last = STM32F4_GPIO_PIN(port, idx), \ + .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \ + .cnf = STM32F4_GPIO_CNF_OUT_AF_PP, \ + .output = 0, \ + .remap = remapvalue \ + } \ + } + +#define STM32F4_PIN_USART_RX(port, idx, remapvalue) \ + { \ + { \ + .pin_first = STM32F4_GPIO_PIN(port, idx), \ + .pin_last = STM32F4_GPIO_PIN(port, idx), \ + .mode = STM32F4_GPIO_MODE_INPUT, \ + .cnf = STM32F4_GPIO_CNF_IN_FLOATING, \ + .output = 0, \ + .remap = remapvalue \ + } \ + } + +#define STM32F4_PIN_USART1_TX_MAP_0 STM32F4_PIN_USART_TX(0, 9, STM32F4_GPIO_REMAP_USART1_0) +#define STM32F4_PIN_USART1_RX_MAP_0 STM32F4_PIN_USART_RX(0, 10, STM32F4_GPIO_REMAP_USART1_0) +#define STM32F4_PIN_USART1_TX_MAP_1 STM32F4_PIN_USART_TX(1, 6, STM32F4_GPIO_REMAP_USART1_1) +#define STM32F4_PIN_USART1_RX_MAP_1 STM32F4_PIN_USART_RX(1, 7, STM32F4_GPIO_REMAP_USART1_1) + +#define STM32F4_PIN_USART2_TX_MAP_0 STM32F4_PIN_USART_TX(0, 2, STM32F4_GPIO_REMAP_USART2_0) +#define STM32F4_PIN_USART2_RX_MAP_0 STM32F4_PIN_USART_RX(0, 3, STM32F4_GPIO_REMAP_USART2_0) +#define STM32F4_PIN_USART2_TX_MAP_1 STM32F4_PIN_USART_TX(3, 5, STM32F4_GPIO_REMAP_USART2_1) +#define STM32F4_PIN_USART2_RX_MAP_1 STM32F4_PIN_USART_RX(3, 6, STM32F4_GPIO_REMAP_USART2_1) + +#define STM32F4_PIN_USART3_TX_MAP_0 STM32F4_PIN_USART_TX(1, 10, STM32F4_GPIO_REMAP_USART3_0) +#define STM32F4_PIN_USART3_RX_MAP_0 STM32F4_PIN_USART_RX(1, 11, STM32F4_GPIO_REMAP_USART3_0) +#define STM32F4_PIN_USART3_TX_MAP_1 STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_USART3_1) +#define STM32F4_PIN_USART3_RX_MAP_1 STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_USART3_1) +#define STM32F4_PIN_USART3_TX_MAP_3 STM32F4_PIN_USART_TX(3, 8, STM32F4_GPIO_REMAP_USART3_3) +#define STM32F4_PIN_USART3_RX_MAP_3 STM32F4_PIN_USART_RX(3, 9, STM32F4_GPIO_REMAP_USART3_3) + +#define STM32F4_PIN_UART4_TX STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_DONT_CHANGE) +#define STM32F4_PIN_UART4_RX STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_DONT_CHANGE) + +#define STM32F4_PIN_UART5_TX STM32F4_PIN_USART_TX(2, 12, STM32F4_GPIO_REMAP_DONT_CHANGE) +#define STM32F4_PIN_UART5_RX STM32F4_PIN_USART_RX(3, 2, STM32F4_GPIO_REMAP_DONT_CHANGE) + +#define STM32F4_PIN_I2C(port, idx, remapvalue) \ + { \ + { \ + .pin_first = STM32F4_GPIO_PIN(port, idx), \ + .pin_last = STM32F4_GPIO_PIN(port, idx), \ + .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \ + .cnf = STM32F4_GPIO_CNF_OUT_AF_OD, \ + .output = 0, \ + .remap = remapvalue \ + } \ + } + +#define STM32F4_PIN_I2C1_SCL_MAP0 STM32F4_PIN_I2C(1, 6, STM32F4_GPIO_REMAP_I2C1_0) +#define STM32F4_PIN_I2C1_SDA_MAP0 STM32F4_PIN_I2C(1, 7, STM32F4_GPIO_REMAP_I2C1_0) +#define STM32F4_PIN_I2C1_SCL_MAP1 STM32F4_PIN_I2C(1, 8, STM32F4_GPIO_REMAP_I2C1_1) +#define STM32F4_PIN_I2C1_SDA_MAP1 STM32F4_PIN_I2C(1, 9, STM32F4_GPIO_REMAP_I2C1_1) + +#define STM32F4_PIN_I2C2_SCL STM32F4_PIN_I2C(1, 10, STM32F4_GPIO_REMAP_DONT_CHANGE) +#define STM32F4_PIN_I2C2_SDA STM32F4_PIN_I2C(1, 11, STM32F4_GPIO_REMAP_DONT_CHANGE) + +/** @} */ + +#endif /* STM32F4_FAMILY_F10XXX */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_STM32F4_IO_H */ diff --git a/bsps/arm/stm32f4/include/bsp/irq.h b/bsps/arm/stm32f4/include/bsp/irq.h new file mode 100644 index 0000000000..4771f521fe --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/irq.h @@ -0,0 +1,141 @@ +/** + * @file + * @ingroup stm32f4_interrupt + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_IRQ_H +#define LIBBSP_ARM_STM32F4_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +/** + * @defgroup stm32f4_interrupt Interrupt Support + * @ingroup arm_stm32f4 + * @brief Interrupt Support + * @{ + */ + +#define STM32F4_IRQ_WWDG 0 +#define STM32F4_IRQ_PVD 1 +#define STM32F4_IRQ_TAMP_STAMP 2 +#define STM32F4_IRQ_RTC_WKUP 3 +#define STM32F4_IRQ_FLASH 4 +#define STM32F4_IRQ_RCC 5 +#define STM32F4_IRQ_EXTI0 6 +#define STM32F4_IRQ_EXTI1 7 +#define STM32F4_IRQ_EXTI2 8 +#define STM32F4_IRQ_EXTI3 9 +#define STM32F4_IRQ_EXTI4 10 +#define STM32F4_IRQ_DMA1_STREAM0 11 +#define STM32F4_IRQ_DMA1_STREAM1 12 +#define STM32F4_IRQ_DMA1_STREAM2 13 +#define STM32F4_IRQ_DMA1_STREAM3 14 +#define STM32F4_IRQ_DMA1_STREAM4 15 +#define STM32F4_IRQ_DMA1_STREAM5 16 +#define STM32F4_IRQ_DMA1_STREAM6 17 +#define STM32F4_IRQ_ADC 18 +#define STM32F4_IRQ_CAN1_TX 19 +#define STM32F4_IRQ_CAN1_RX0 20 +#define STM32F4_IRQ_CAN1_RX1 21 +#define STM32F4_IRQ_CAN1_SCE 22 +#define STM32F4_IRQ_EXTI9_5 23 +#define STM32F4_IRQ_TIM1_BRK_TIM9 24 +#define STM32F4_IRQ_TIM1_UP_TIM10 25 +#define STM32F4_IRQ_TIM1_TRG_COM_TIM11 26 +#define STM32F4_IRQ_TIM1_CC 27 +#define STM32F4_IRQ_TIM2 28 +#define STM32F4_IRQ_TIM3 29 +#define STM32F4_IRQ_TIM4 30 +#define STM32F4_IRQ_I2C1_EV 31 +#define STM32F4_IRQ_I2C1_ER 32 +#define STM32F4_IRQ_I2C2_EV 33 +#define STM32F4_IRQ_I2C2_ER 34 +#define STM32F4_IRQ_SPI1 35 +#define STM32F4_IRQ_SPI2 36 +#define STM32F4_IRQ_USART1 37 +#define STM32F4_IRQ_USART2 38 +#define STM32F4_IRQ_USART3 39 +#define STM32F4_IRQ_EXTI15_10 40 +#define STM32F4_IRQ_RTC_ALARM 41 +#define STM32F4_IRQ_OTG_FS_WKUP 42 +#define STM32F4_IRQ_TIM8_BRK_TIM12 43 +#define STM32F4_IRQ_TIM8_UP_TIM13 44 +#define STM32F4_IRQ_TIM8_TRG_COM_TIM14 45 +#define STM32F4_IRQ_TIM8_CC 46 +#define STM32F4_IRQ_DMA1_STREAM7 47 +#define STM32F4_IRQ_FSMC 48 +#define STM32F4_IRQ_SDIO 49 +#define STM32F4_IRQ_TIM5 50 +#define STM32F4_IRQ_SPI3 51 +#define STM32F4_IRQ_UART4 52 +#define STM32F4_IRQ_UART5 53 +#define STM32F4_IRQ_TIM6_DAC 54 +#define STM32F4_IRQ_TIM7 55 +#define STM32F4_IRQ_DMA2_STREAM0 56 +#define STM32F4_IRQ_DMA2_STREAM1 57 +#define STM32F4_IRQ_DMA2_STREAM2 58 +#define STM32F4_IRQ_DMA2_STREAM3 59 +#define STM32F4_IRQ_DMA2_STREAM4 60 +#define STM32F4_IRQ_ETH 61 +#define STM32F4_IRQ_ETH_WKUP 62 +#define STM32F4_IRQ_CAN2_TX 63 +#define STM32F4_IRQ_CAN2_RX0 64 +#define STM32F4_IRQ_CAN2_RX1 65 +#define STM32F4_IRQ_CAN2_SCE 66 +#define STM32F4_IRQ_OTG_FS 67 +#define STM32F4_IRQ_DMA2_STREAM5 68 +#define STM32F4_IRQ_DMA2_STREAM6 69 +#define STM32F4_IRQ_DMA2_STREAM7 70 +#define STM32F4_IRQ_USART6 71 +#define STM32F4_IRQ_I2C3_EV 72 +#define STM32F4_IRQ_I2C3_ER 73 +#define STM32F4_IRQ_OTG_HS_EP1_OUT 74 +#define STM32F4_IRQ_OTG_HS_EP1_IN 75 +#define STM32F4_IRQ_OTG_HS_WKUP 76 +#define STM32F4_IRQ_OTG_HS 77 +#define STM32F4_IRQ_DCMI 78 +#define STM32F4_IRQ_CRYP 79 +#define STM32F4_IRQ_HASH_RNG 80 +#define STM32F4_IRQ_FPU 81 + +#define STM32F4_IRQ_PRIORITY_VALUE_MIN 0 +#define STM32F4_IRQ_PRIORITY_VALUE_MAX 15 +#define STM32F4_IRQ_PRIORITY_COUNT (STM32F4_IRQ_PRIORITY_VALUE_MAX + 1) +#define STM32F4_IRQ_PRIORITY_HIGHEST STM32F4_IRQ_PRIORITY_VALUE_MIN +#define STM32F4_IRQ_PRIORITY_LOWEST STM32F4_IRQ_PRIORITY_VALUE_MAX + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 81 + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_IRQ_H */ diff --git a/bsps/arm/stm32f4/include/bsp/rcc.h b/bsps/arm/stm32f4/include/bsp/rcc.h new file mode 100644 index 0000000000..f1bd7d173c --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/rcc.h @@ -0,0 +1,196 @@ +/** + * @file + * @ingroup stm32f4_rcc + * @brief RCC support. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_RCC_H +#define LIBBSP_ARM_STM32F4_RCC_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup stm32f4_rcc RCC Support + * @ingroup arm_stm32f4 + * @brief RCC Support + * @{ + */ + +#define STM32F4_RCC_INDEX(reg, idx) (((reg) << 5) | (idx)) + +typedef enum { +#ifdef STM32F4_FAMILY_F4XXXX + + /** + * @name Family F4XXXX + * @{ + */ + + STM32F4_RCC_OTGHS = STM32F4_RCC_INDEX(0, 29), + STM32F4_RCC_ETHMAC = STM32F4_RCC_INDEX(0, 25), + STM32F4_RCC_DMA2 = STM32F4_RCC_INDEX(0, 22), + STM32F4_RCC_DMA1 = STM32F4_RCC_INDEX(0, 21), + STM32F4_RCC_CRC = STM32F4_RCC_INDEX(0, 12), + STM32F4_RCC_GPIOI = STM32F4_RCC_INDEX(0, 8), + STM32F4_RCC_GPIOH = STM32F4_RCC_INDEX(0, 7), + STM32F4_RCC_GPIOG = STM32F4_RCC_INDEX(0, 6), + STM32F4_RCC_GPIOF = STM32F4_RCC_INDEX(0, 5), + STM32F4_RCC_GPIOE = STM32F4_RCC_INDEX(0, 4), + STM32F4_RCC_GPIOD = STM32F4_RCC_INDEX(0, 3), + STM32F4_RCC_GPIOC = STM32F4_RCC_INDEX(0, 2), + STM32F4_RCC_GPIOB = STM32F4_RCC_INDEX(0, 1), + STM32F4_RCC_GPIOA = STM32F4_RCC_INDEX(0, 0), + + STM32F4_RCC_OTGFS = STM32F4_RCC_INDEX(1, 7), + STM32F4_RCC_RNG = STM32F4_RCC_INDEX(1, 6), + STM32F4_RCC_HASH = STM32F4_RCC_INDEX(1, 5), + STM32F4_RCC_CRYP = STM32F4_RCC_INDEX(1, 4), + STM32F4_RCC_DCMI = STM32F4_RCC_INDEX(1, 0), + + STM32F4_RCC_FSMCR = STM32F4_RCC_INDEX(2, 0), + + STM32F4_RCC_DAC = STM32F4_RCC_INDEX(4, 29), + STM32F4_RCC_PWR = STM32F4_RCC_INDEX(4, 28), + STM32F4_RCC_CAN2 = STM32F4_RCC_INDEX(4, 26), + STM32F4_RCC_CAN1 = STM32F4_RCC_INDEX(4, 25), + STM32F4_RCC_I2C3 = STM32F4_RCC_INDEX(4, 23), + STM32F4_RCC_I2C2 = STM32F4_RCC_INDEX(4, 22), + STM32F4_RCC_I2C1 = STM32F4_RCC_INDEX(4, 21), + STM32F4_RCC_UART5 = STM32F4_RCC_INDEX(4, 20), + STM32F4_RCC_UART4 = STM32F4_RCC_INDEX(4, 19), + STM32F4_RCC_USART3 = STM32F4_RCC_INDEX(4, 18), + STM32F4_RCC_USART2 = STM32F4_RCC_INDEX(4, 17), + STM32F4_RCC_SPI3 = STM32F4_RCC_INDEX(4, 15), + STM32F4_RCC_SPI2 = STM32F4_RCC_INDEX(4, 14), + STM32F4_RCC_WWDG = STM32F4_RCC_INDEX(4, 11), + STM32F4_RCC_TIM14 = STM32F4_RCC_INDEX(4, 8), + STM32F4_RCC_TIM13 = STM32F4_RCC_INDEX(4, 7), + STM32F4_RCC_TIM12 = STM32F4_RCC_INDEX(4, 6), + STM32F4_RCC_TIM7 = STM32F4_RCC_INDEX(4, 5), + STM32F4_RCC_TIM6 = STM32F4_RCC_INDEX(4, 4), + STM32F4_RCC_TIM5 = STM32F4_RCC_INDEX(4, 3), + STM32F4_RCC_TIM4 = STM32F4_RCC_INDEX(4, 2), + STM32F4_RCC_TIM3 = STM32F4_RCC_INDEX(4, 1), + STM32F4_RCC_TIM2 = STM32F4_RCC_INDEX(4, 0), + + STM32F4_RCC_TIM11 = STM32F4_RCC_INDEX(5, 18), + STM32F4_RCC_TIM10 = STM32F4_RCC_INDEX(5, 17), + STM32F4_RCC_TIM9 = STM32F4_RCC_INDEX(5, 16), + STM32F4_RCC_SYSCFG = STM32F4_RCC_INDEX(5, 14), + STM32F4_RCC_SPI1 = STM32F4_RCC_INDEX(5, 12), + STM32F4_RCC_SDIO = STM32F4_RCC_INDEX(5, 11), + STM32F4_RCC_ADC3 = STM32F4_RCC_INDEX(5, 10), + STM32F4_RCC_ADC2 = STM32F4_RCC_INDEX(5, 9), + STM32F4_RCC_ADC1 = STM32F4_RCC_INDEX(5, 8), + STM32F4_RCC_USART6 = STM32F4_RCC_INDEX(5, 5), + STM32F4_RCC_USART1 = STM32F4_RCC_INDEX(5, 4), + STM32F4_RCC_TIM8 = STM32F4_RCC_INDEX(5, 1), + STM32F4_RCC_TIM1 = STM32F4_RCC_INDEX(5, 0), + + /** @} */ + +#endif /* STM32F4_FAMILY_F4XXXX */ +#ifdef STM32F4_FAMILY_F10XXX + + /** + * @name Family F10 + * @{ + */ + + STM32F4_RCC_DMA1 = STM32F4_RCC_INDEX(0, 0), + STM32F4_RCC_DMA2 = STM32F4_RCC_INDEX(0, 1), + STM32F4_RCC_SRAM = STM32F4_RCC_INDEX(0, 2), + STM32F4_RCC_FLITF = STM32F4_RCC_INDEX(0, 4), + STM32F4_RCC_CRCEN = STM32F4_RCC_INDEX(0, 6), + STM32F4_RCC_FSMC = STM32F4_RCC_INDEX(0, 8), + STM32F4_RCC_SDIO = STM32F4_RCC_INDEX(0, 10), + STM32F4_RCC_OTGFS = STM32F4_RCC_INDEX(0, 12), + STM32F4_RCC_ETHMAC = STM32F4_RCC_INDEX(0, 14), + STM32F4_RCC_ETHMACTX = STM32F4_RCC_INDEX(0, 15), + STM32F4_RCC_ETHMACRX = STM32F4_RCC_INDEX(0, 16), + + STM32F4_RCC_AFIO = STM32F4_RCC_INDEX(1, 0), + STM32F4_RCC_GPIOA = STM32F4_RCC_INDEX(1, 2), + STM32F4_RCC_GPIOB = STM32F4_RCC_INDEX(1, 3), + STM32F4_RCC_GPIOC = STM32F4_RCC_INDEX(1, 4), + STM32F4_RCC_GPIOD = STM32F4_RCC_INDEX(1, 5), + STM32F4_RCC_GPIOE = STM32F4_RCC_INDEX(1, 6), + STM32F4_RCC_GPIOF = STM32F4_RCC_INDEX(1, 7), + STM32F4_RCC_GPIOG = STM32F4_RCC_INDEX(1, 8), + STM32F4_RCC_ADC1 = STM32F4_RCC_INDEX(1, 9), + STM32F4_RCC_ADC2 = STM32F4_RCC_INDEX(1, 10), + STM32F4_RCC_TIM1 = STM32F4_RCC_INDEX(1, 11), + STM32F4_RCC_SPI1 = STM32F4_RCC_INDEX(1, 12), + STM32F4_RCC_TIM8 = STM32F4_RCC_INDEX(1, 13), + STM32F4_RCC_USART1 = STM32F4_RCC_INDEX(1, 14), + STM32F4_RCC_ADC3 = STM32F4_RCC_INDEX(1, 15), + STM32F4_RCC_TIM9 = STM32F4_RCC_INDEX(1, 19), + STM32F4_RCC_TIM10 = STM32F4_RCC_INDEX(1, 20), + STM32F4_RCC_TIM11 = STM32F4_RCC_INDEX(1, 21), + + STM32F4_RCC_TIM2 = STM32F4_RCC_INDEX(2, 0), + STM32F4_RCC_TIM3 = STM32F4_RCC_INDEX(2, 1), + STM32F4_RCC_TIM4 = STM32F4_RCC_INDEX(2, 2), + STM32F4_RCC_TIM5 = STM32F4_RCC_INDEX(2, 3), + STM32F4_RCC_TIM6 = STM32F4_RCC_INDEX(2, 4), + STM32F4_RCC_TIM7 = STM32F4_RCC_INDEX(2, 5), + STM32F4_RCC_TIM12 = STM32F4_RCC_INDEX(2, 6), + STM32F4_RCC_TIM13 = STM32F4_RCC_INDEX(2, 7), + STM32F4_RCC_TIM14 = STM32F4_RCC_INDEX(2, 8), + STM32F4_RCC_WWDG = STM32F4_RCC_INDEX(2, 11), + STM32F4_RCC_SPI2 = STM32F4_RCC_INDEX(2, 14), + STM32F4_RCC_SPI3 = STM32F4_RCC_INDEX(2, 15), + STM32F4_RCC_USART2 = STM32F4_RCC_INDEX(2, 17), + STM32F4_RCC_USART3 = STM32F4_RCC_INDEX(2, 18), + STM32F4_RCC_UART4 = STM32F4_RCC_INDEX(2, 19), + STM32F4_RCC_UART5 = STM32F4_RCC_INDEX(2, 20), + STM32F4_RCC_I2C1 = STM32F4_RCC_INDEX(2, 21), + STM32F4_RCC_I2C2 = STM32F4_RCC_INDEX(2, 22), + STM32F4_RCC_USB = STM32F4_RCC_INDEX(2, 23), + STM32F4_RCC_CAN1 = STM32F4_RCC_INDEX(2, 24), + STM32F4_RCC_CAN2 = STM32F4_RCC_INDEX(2, 25), + STM32F4_RCC_BKP = STM32F4_RCC_INDEX(2, 27), + STM32F4_RCC_PWR = STM32F4_RCC_INDEX(2, 28), + STM32F4_RCC_DAC = STM32F4_RCC_INDEX(2, 29), + + /** @} */ + +#endif /* STM32F4_FAMILY_F10XXX */ +} stm32f4_rcc_index; + +void stm32f4_rcc_reset(stm32f4_rcc_index index); + +void stm32f4_rcc_set_reset(stm32f4_rcc_index index, bool set); + +void stm32f4_rcc_set_clock(stm32f4_rcc_index index, bool set); + +#ifdef STM32F4_FAMILY_F4XXXX +void stm32f4_rcc_set_low_power_clock(stm32f4_rcc_index index, bool set); +#endif /* STM32F4_FAMILY_F4XXXX */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_STM32F4_RCC_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32_i2c.h b/bsps/arm/stm32f4/include/bsp/stm32_i2c.h new file mode 100644 index 0000000000..21d9b34ed1 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32_i2c.h @@ -0,0 +1,113 @@ +/** + * @file + * @ingroup stm32_i2c + * @brief STM32 I2C support. + */ + +/* + * Copyright (c) 2013 Christian Mauderer. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32_I2C_H +#define LIBBSP_ARM_STM32F4_STM32_I2C_H + +#include + +/** + * @defgroup stm32_i2c STM32 I2C Support + * @ingroup stm32f4_i2c + * @brief STM32 I2C Support + * @{ + */ + +typedef struct { + uint32_t cr1; +#define STM32F4_I2C_CR1_SWRST BSP_BIT32(15) +#define STM32F4_I2C_CR1_ALERT BSP_BIT32(13) +#define STM32F4_I2C_CR1_PEC BSP_BIT32(12) +#define STM32F4_I2C_CR1_POS BSP_BIT32(11) +#define STM32F4_I2C_CR1_ACK BSP_BIT32(10) +#define STM32F4_I2C_CR1_STOP BSP_BIT32(9) +#define STM32F4_I2C_CR1_START BSP_BIT32(8) +#define STM32F4_I2C_CR1_NOSTRETCH BSP_BIT32(7) +#define STM32F4_I2C_CR1_ENGC BSP_BIT32(6) +#define STM32F4_I2C_CR1_ENPEC BSP_BIT32(5) +#define STM32F4_I2C_CR1_ENARP BSP_BIT32(4) +#define STM32F4_I2C_CR1_SMBTYPE BSP_BIT32(3) +#define STM32F4_I2C_CR1_SMBUS BSP_BIT32(1) +#define STM32F4_I2C_CR1_PE BSP_BIT32(0) + uint32_t cr2; +#define STM32F4_I2C_CR2_LAST BSP_BIT32(12) +#define STM32F4_I2C_CR2_DMAEN BSP_BIT32(11) +#define STM32F4_I2C_CR2_ITBUFEN BSP_BIT32(10) +#define STM32F4_I2C_CR2_ITEVTEN BSP_BIT32(9) +#define STM32F4_I2C_CR2_ITERREN BSP_BIT32(8) +#define STM32F4_I2C_CR2_FREQ(val) BSP_FLD32(val, 0, 5) +#define STM32F4_I2C_CR2_FREQ_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define STM32F4_I2C_CR2_FREQ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t oar1; +#define STM32F4_I2C_OAR1_ADDMODE BSP_BIT32(15) +#define STM32F4_I2C_OAR1_ADD(val) BSP_FLD32(val, 0, 9) +#define STM32F4_I2C_OAR1_ADD_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define STM32F4_I2C_OAR1_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t oar2; +#define STM32F4_I2C_OAR2_ADD2(val) BSP_FLD32(val, 1, 7) +#define STM32F4_I2C_OAR2_ADD2_GET(reg) BSP_FLD32GET(reg, 1, 7) +#define STM32F4_I2C_OAR2_ADD2_SET(reg, val) BSP_FLD32SET(reg, val, 1, 7) +#define STM32F4_I2C_OAR2_ENDUAL BSP_BIT32(0) + uint32_t dr; +#define STM32F4_I2C_DR(val) BSP_FLD32(val, 0, 7) +#define STM32F4_I2C_DR_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define STM32F4_I2C_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t sr1; +#define STM32F4_I2C_SR1_SMBALERT BSP_BIT32(15) +#define STM32F4_I2C_SR1_TIMEOUT BSP_BIT32(14) +#define STM32F4_I2C_SR1_PECERR BSP_BIT32(12) +#define STM32F4_I2C_SR1_OVR BSP_BIT32(11) +#define STM32F4_I2C_SR1_AF BSP_BIT32(10) +#define STM32F4_I2C_SR1_ARLO BSP_BIT32(9) +#define STM32F4_I2C_SR1_BERR BSP_BIT32(8) +#define STM32F4_I2C_SR1_TxE BSP_BIT32(7) +#define STM32F4_I2C_SR1_RxNE BSP_BIT32(6) +#define STM32F4_I2C_SR1_STOPF BSP_BIT32(4) +#define STM32F4_I2C_SR1_ADD10 BSP_BIT32(3) +#define STM32F4_I2C_SR1_BTF BSP_BIT32(2) +#define STM32F4_I2C_SR1_ADDR BSP_BIT32(1) +#define STM32F4_I2C_SR1_SB BSP_BIT32(0) + uint32_t sr2; +#define STM32F4_I2C_SR2_PEC(val) BSP_FLD32(val, 8, 15) +#define STM32F4_I2C_SR2_PEC_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define STM32F4_I2C_SR2_PEC_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define STM32F4_I2C_SR2_DUALF BSP_BIT32(7) +#define STM32F4_I2C_SR2_SMBHOST BSP_BIT32(6) +#define STM32F4_I2C_SR2_SMBDEFAULT BSP_BIT32(5) +#define STM32F4_I2C_SR2_GENCALL BSP_BIT32(4) +#define STM32F4_I2C_SR2_TRA BSP_BIT32(2) +#define STM32F4_I2C_SR2_BUSY BSP_BIT32(1) +#define STM32F4_I2C_SR2_MSL BSP_BIT32(0) + uint32_t ccr; +#define STM32F4_I2C_CCR_FS BSP_BIT32(15) +#define STM32F4_I2C_CCR_DUTY BSP_BIT32(14) +#define STM32F4_I2C_CCR_CCR(val) BSP_FLD32(val, 0, 11) +#define STM32F4_I2C_CCR_CCR_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define STM32F4_I2C_CCR_CCR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) +#define STM32F4_I2C_CCR_CCR_MAX STM32F4_I2C_CCR_CCR_GET(BSP_MSK32(0, 11)) + uint32_t trise; +#define STM32F4_I2C_TRISE(val) BSP_FLD32(val, 0, 5) +#define STM32F4_I2C_TRISE_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define STM32F4_I2C_TRISE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) +} stm32f4_i2c; + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_STM32_I2C_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32_usart.h b/bsps/arm/stm32f4/include/bsp/stm32_usart.h new file mode 100644 index 0000000000..c9c269533f --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32_usart.h @@ -0,0 +1,110 @@ +/** + * @file + * @ingroup stm32_usart + * @brief STM32 USART support + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32_USART_H +#define LIBBSP_ARM_STM32F4_STM32_USART_H + +#include + +/** + * @defgroup stm32_usart STM32 USART Support + * @ingroup stm32f4_usart + * @brief STM32 USART Support + * @{ + */ + +typedef struct { + uint32_t sr; +#define STM32F4_USART_SR_CTS BSP_BIT32(9) +#define STM32F4_USART_SR_LBD BSP_BIT32(8) +#define STM32F4_USART_SR_TXE BSP_BIT32(7) +#define STM32F4_USART_SR_TC BSP_BIT32(6) +#define STM32F4_USART_SR_RXNE BSP_BIT32(5) +#define STM32F4_USART_SR_IDLE BSP_BIT32(4) +#define STM32F4_USART_SR_ORE BSP_BIT32(3) +#define STM32F4_USART_SR_NF BSP_BIT32(2) +#define STM32F4_USART_SR_FE BSP_BIT32(1) +#define STM32F4_USART_SR_PE BSP_BIT32(0) + uint32_t dr; +#define STM32F4_USART_DR(val) BSP_FLD32(val, 0, 7) +#define STM32F4_USART_DR_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define STM32F4_USART_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t bbr; +#define STM32F4_USART_BBR_DIV_MANTISSA(val) BSP_FLD32(val, 4, 15) +#define STM32F4_USART_BBR_DIV_MANTISSA_GET(reg) BSP_FLD32GET(reg, 4, 15) +#define STM32F4_USART_BBR_DIV_MANTISSA_SET(reg, val) BSP_FLD32SET(reg, val, 4, 15) +#define STM32F4_USART_BBR_DIV_FRACTION(val) BSP_FLD32(val, 0, 3) +#define STM32F4_USART_BBR_DIV_FRACTION_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_USART_BBR_DIV_FRACTION_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t cr1; +#define STM32F4_USART_CR1_OVER8 BSP_BIT32(15) +#define STM32F4_USART_CR1_UE BSP_BIT32(13) +#define STM32F4_USART_CR1_M BSP_BIT32(12) +#define STM32F4_USART_CR1_WAKE BSP_BIT32(11) +#define STM32F4_USART_CR1_PCE BSP_BIT32(10) +#define STM32F4_USART_CR1_PS BSP_BIT32(9) +#define STM32F4_USART_CR1_PEIE BSP_BIT32(8) +#define STM32F4_USART_CR1_TXEIE BSP_BIT32(7) +#define STM32F4_USART_CR1_TCIE BSP_BIT32(6) +#define STM32F4_USART_CR1_RXNEIE BSP_BIT32(5) +#define STM32F4_USART_CR1_IDLEIE BSP_BIT32(4) +#define STM32F4_USART_CR1_TE BSP_BIT32(3) +#define STM32F4_USART_CR1_RE BSP_BIT32(2) +#define STM32F4_USART_CR1_RWU BSP_BIT32(1) +#define STM32F4_USART_CR1_SBK BSP_BIT32(0) + uint32_t cr2; +#define STM32F4_USART_CR2_LINEN BSP_BIT32(14) +#define STM32F4_USART_CR2_STOP(val) BSP_FLD32(val, 12, 13) +#define STM32F4_USART_CR2_STOP_GET(reg) BSP_FLD32GET(reg, 12, 13) +#define STM32F4_USART_CR2_STOP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13) +#define STM32F4_USART_CR2_CLKEN BSP_BIT32(11) +#define STM32F4_USART_CR2_CPOL BSP_BIT32(10) +#define STM32F4_USART_CR2_CPHA BSP_BIT32(9) +#define STM32F4_USART_CR2_LBCL BSP_BIT32(8) +#define STM32F4_USART_CR2_LBDIE BSP_BIT32(6) +#define STM32F4_USART_CR2_LBDL BSP_BIT32(5) +#define STM32F4_USART_CR2_ADD(val) BSP_FLD32(val, 0, 3) +#define STM32F4_USART_CR2_ADD_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_USART_CR2_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t cr3; +#define STM32F4_USART_CR3_ONEBIT BSP_BIT32(11) +#define STM32F4_USART_CR3_CTSIE BSP_BIT32(10) +#define STM32F4_USART_CR3_CTSE BSP_BIT32(9) +#define STM32F4_USART_CR3_RTSE BSP_BIT32(8) +#define STM32F4_USART_CR3_DMAT BSP_BIT32(7) +#define STM32F4_USART_CR3_DMAR BSP_BIT32(6) +#define STM32F4_USART_CR3_SCEN BSP_BIT32(5) +#define STM32F4_USART_CR3_NACK BSP_BIT32(4) +#define STM32F4_USART_CR3_HDSEL BSP_BIT32(3) +#define STM32F4_USART_CR3_IRLP BSP_BIT32(2) +#define STM32F4_USART_CR3_IREN BSP_BIT32(1) +#define STM32F4_USART_CR3_EIE BSP_BIT32(0) + uint32_t gtpr; +#define STM32F4_USART_GTPR_GT(val) BSP_FLD32(val, 8, 15) +#define STM32F4_USART_GTPR_GT_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define STM32F4_USART_GTPR_GT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define STM32F4_USART_GTPR_PSC(val) BSP_FLD32(val, 0, 7) +#define STM32F4_USART_GTPR_PSC_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define STM32F4_USART_GTPR_PSC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) +} stm32f4_usart; + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_STM32_USART_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f10xxx_exti.h b/bsps/arm/stm32f4/include/bsp/stm32f10xxx_exti.h new file mode 100644 index 0000000000..ecb4bb900c --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f10xxx_exti.h @@ -0,0 +1,50 @@ +/** + * @file + * @ingroup stm32f4_exti + * @brief STM32F10XXX EXTI support + */ + +/* + * Copyright (c) 2013 Christian Mauderer. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F10XXX_EXTI_H +#define LIBBSP_ARM_STM32F4_STM32F10XXX_EXTI_H + +#include + +/** + * @defgroup stm32f4_exti EXTI Support + * @ingroup arm_stm32f4 + * @brief STM32F10XXX EXTI Support + * @{ + */ + +typedef struct { + uint32_t imr; +#define STM32F4_EXTI_IMR(line) BSP_BIT32(line) + uint32_t emr; +#define STM32F4_EXTI_EMR(line) BSP_BIT32(line) + uint32_t rtsr; +#define STM32F4_EXTI_RTSR(line) BSP_BIT32(line) + uint32_t ftsr; +#define STM32F4_EXTI_FTSR(line) BSP_BIT32(line) + uint32_t swier; +#define STM32F4_EXTI_SWIER(line) BSP_BIT32(line) + uint32_t pr; +#define STM32F4_EXTI_PR(line) BSP_BIT32(line) +} stm32f4_exti; + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_STM32F10XXX_EXTI_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f10xxx_gpio.h b/bsps/arm/stm32f4/include/bsp/stm32f10xxx_gpio.h new file mode 100644 index 0000000000..ec7e675844 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f10xxx_gpio.h @@ -0,0 +1,51 @@ +/** + * @file + * @ingroup stm32f4_gpio + * @brief STM32F10XXX GPIO support. + */ + +/* + * Copyright (c) 2013 Christian Mauderer. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F10XXX_GPIO_H +#define LIBBSP_ARM_STM32F4_STM32F10XXX_GPIO_H + +#include + +/** + * @defgroup stm32f4_gpio GPIO Support + * @ingroup stm32f4_io + * @brief GPIO Support + * @{ + */ + +typedef struct { + uint32_t cr[2]; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t brr; + uint32_t lckr; +} stm32f4_gpio; + +typedef struct { + uint32_t evcr; + uint32_t mapr; + uint32_t exticr[4]; + uint32_t mapr2; +} stm32f4_afio; + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_STM32F10XXX_GPIO_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f10xxx_rcc.h b/bsps/arm/stm32f4/include/bsp/stm32f10xxx_rcc.h new file mode 100644 index 0000000000..c1c6629810 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f10xxx_rcc.h @@ -0,0 +1,48 @@ +/** + * @file + * @ingroup stm32f10xxx_rcc + * @brief STM32F10XXX RCC support. + */ + +/* + * Copyright (c) 2013 Christian Mauderer. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F10XXX_RCC_H +#define LIBBSP_ARM_STM32F4_STM32F10XXX_RCC_H + +#include + +/** + * @defgroup stm32f10xxx_rcc STM32F10XXX RCC Support + * @ingroup stm32f4_rcc + * @brief STM32F10XXX RCC Support + * @{ + */ + +typedef struct { + uint32_t cr; + uint32_t cfgr; + uint32_t cir; + uint32_t apbrstr [2]; + uint32_t ahbenr [1]; + uint32_t apbenr [2]; + uint32_t bdcr; + uint32_t csr; + uint32_t ahbstr; + uint32_t cfgr2; +} stm32f4_rcc; + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_STM32F10XXX_RCC_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4.h b/bsps/arm/stm32f4/include/bsp/stm32f4.h new file mode 100644 index 0000000000..154d4f6d7b --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4.h @@ -0,0 +1,258 @@ +/** + * @file + * @ingroup stm32f4_reg + * @brief Register definitions. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4_H +#define LIBBSP_ARM_STM32F4_STM32F4_H + +#include +#include + +#define STM32F4_BASE 0x00 + +#ifdef STM32F4_FAMILY_F4XXXX + +/** + * @defgroup stm32f4_reg Register Defintions + * @ingroup arm_stm32f4 + * @brief Register Definitions + * @{ + */ + +#define STM32F4_APB1_BASE (STM32F4_BASE + 0x40000000) +#define STM32F4_APB2_BASE (STM32F4_BASE + 0x40010000) +#define STM32F4_AHB1_BASE (STM32F4_BASE + 0x40020000) +#define STM32F4_AHB2_BASE (STM32F4_BASE + 0x50000000) + +/** + * @name STM32f4XXXX GPIO + * @{ + */ + +#include +#define STM32F4_GPIO(i) ((volatile stm32f4_gpio *) (STM32F4_BASE + 0x40020000) + (i)) + +/** @} */ + +/** + * @name STM32F4XXXX RCC + * @{ + */ + +#include +#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_AHB1_BASE + 0x3800)) + +/** @} */ + +/** + * @name STM32F4XXXX FLASH + * @{ + */ + +#include +#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_BASE + 0x40023C00)) + +/** @} */ + +#include + +/** + * @name STM32 I2C + * @{ + */ + +#define STM32F4_I2C3 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005C00)) +#define STM32F4_I2C2 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005800)) +#define STM32F4_I2C1 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005400)) + +/** @} */ + +/** + * @name STM32 USART + * @{ + */ + +#include +#define STM32F4_USART_1 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011000)) +#define STM32F4_USART_2 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400)) +#define STM32F4_USART_3 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800)) +#define STM32F4_USART_4 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004c00)) +#define STM32F4_USART_5 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000)) +#define STM32F4_USART_6 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011400)) + +/** @} */ + +/** + * @name STM32f4XXXX PWR + * @{ + */ + +#include +#define STM32F4_PWR ((volatile stm32f4_pwr *) (STM32F4_APB1_BASE + 0x7000)) + +/** @} */ + +/** + * @name STM32f4XXXX EXTI + * @{ + */ + +#include +#define STM32F4_EXTI ((volatile stm32f4_exti *) (STM32F4_APB2_BASE + 0x3c00)) + +/** @} */ + +/** + * @name STM32f4XXXX SYSCFG + * @{ + */ + +#include +#define STM32F4_SYSCFG ((volatile stm32f4_syscfg *) (STM32F4_APB2_BASE + 0x3800)) + +/** @} */ + +/** + * @name STM32f4XXXX FLASH + * @{ + */ + +#include +#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_AHB1_BASE + 0x3c00)) + +/** @} */ + +/** + * @name STM32f4XXXX TIM + * @{ + */ + +#include +#define STM32F4_TIM1 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x0000)) +#define STM32F4_TIM2 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0000)) +#define STM32F4_TIM3 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0400)) +#define STM32F4_TIM4 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0800)) +#define STM32F4_TIM5 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0c00)) +#define STM32F4_TIM6 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1000)) +#define STM32F4_TIM7 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1400)) +#define STM32F4_TIM8 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x0400)) +#define STM32F4_TIM9 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4000)) +#define STM32F4_TIM10 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4400)) +#define STM32F4_TIM11 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4800)) +#define STM32F4_TIM12 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1800)) +#define STM32F4_TIM13 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1c00)) +#define STM32F4_TIM14 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x2000)) + +/** @} */ + +/** + * @name STM32f4XXXX ADC + * @{ + */ + +#include +#define STM32F4_ADC1 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2000)) +#define STM32F4_ADC2 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2100)) +#define STM32F4_ADC3 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2200)) +#define STM32F4_ADC_COMMON ((volatile stm32f4_adc_com *) (STM32F4_APB2_BASE + 0x2300)) + +/** @} */ + +/** + * @name STM32f4XXXX OTGFS + * @{ + */ + +#include +#define STM32F4_OTGFS_BASE (STM32F4_AHB2_BASE + 0x0000) +#define STM32F4_OTGFS_CORE ((volatile stm32f4_otgfs *) (STM32F4_OTGFS_BASE + 0x000)) +#define STM32F4_OTGFS_DEV ((volatile stm32f4_otgfs_dregs *) (STM32F4_OTGFS_BASE + 0x800)) +#define STM32F4_OTGFS_INEP ((volatile stm32f4_otgfs_inepregs *) (STM32F4_OTGFS_BASE + 0x900)) +#define STM32F4_OTGFS_OUTEP ((volatile stm32f4_otgfs_outepregs *) (STM32F4_OTGFS_BASE + 0xb00)) +#define STM32F4_OTGFS_PWRCTL ((volatile stm32f4_otgfs_pwrctlregs *) (STM32F4_OTGFS_BASE + 0xe00)) + +#define STM32F4_OTGFS_FIFO_BASE (STM32F4_OTGFS_BASE + USB_FIFO_BASE) + +/** @} */ + +#endif /* STM32F4_FAMILY_F4XXXX */ + +#ifdef STM32F4_FAMILY_F10XXX + +/** + * @name STM32F10 EXTI + * @{ + */ + +#include +#define STM32F4_EXTI ((volatile stm32f4_exti *) (STM32F4_BASE + 0x40010400)) + +/** @} */ + +/** + * @name STM32F10XXX GPIO + * @{ + */ + +#include +#define STM32F4_GPIO(i) ((volatile stm32f4_gpio *) (STM32F4_BASE + 0x40010800 + i * 0x400)) +#define STM32F4_AFIO ((volatile stm32f4_afio *) (STM32F4_BASE + 0x40010000)) + +/** @} */ + +/** + * @name STM32F10XXX RCC + * @{ + */ + +#include +#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_BASE + 0x40021000)) + +/** @} */ + +/** + * @name STM32 I2C + * @{ + */ + +#include +#define STM32F4_I2C2 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005800)) +#define STM32F4_I2C1 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005400)) + +/** @} */ + +/** + * @name STM32 USART + * @{ + */ + +#include +#define STM32F4_USART_1 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40013800)) +#define STM32F4_USART_2 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400)) +#define STM32F4_USART_3 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800)) +#define STM32F4_USART_4 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004c00)) +#define STM32F4_USART_5 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000)) + +/** @} */ + +/** @} */ + +#endif /* STM32F4_FAMILY_F10XXX */ + +#endif /* LIBBSP_ARM_STM32F4_STM32F4_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h new file mode 100644 index 0000000000..b9c1f9d5be --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2014 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H + +#include + +struct stm32f4_adc_chan_s { + uint32_t sr; // 0x00: Status register +#define STM32F4_ADC_SR_OVR BSP_BIT32(5) // Overrun +#define STM32F4_ADC_SR_STRT BSP_BIT32(4) // Regular channel start flag +#define STM32F4_ADC_SR_JSTRT BSP_BIT32(3) // Injected channel start flag +#define STM32F4_ADC_SR_JEOC BSP_BIT32(2) // Injected channel end of conversion +#define STM32F4_ADC_SR_EOC BSP_BIT32(1) // Regular channel end of conversion +#define STM32F4_ADC_SR_AWD BSP_BIT32(0) // Analog watchdog flag + + uint32_t cr1; // 0x04: Control register 1 +#define STM32F4_ADC_CR1_OVRIE BSP_BIT32(26) // Overrun interrupt enable +#define STM32F4_ADC_CR1_RES(val) BSP_FLD32(val, 24, 25) // Resolution +#define STM32F4_ADC_CR1_RES_GET(reg) BSP_FLD32GET(reg, 24, 25) +#define STM32F4_ADC_CR1_RES_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25) +#define ADC_CR1_RES_12BIT 0 +#define ADC_CR1_RES_10BIT 1 +#define ADC_CR1_RES_8BIT 2 +#define ADC_CR1_RES_6BIT 3 +#define STM32F4_ADC_CR1_AWDEN BSP_BIT32(23) // Analog watchdog enable on regular channels +#define STM32F4_ADC_CR1_JAWDEN BSP_BIT32(22) // Analog watchdog enable on injected channels +#define STM32F4_ADC_CR1_DISCNUM(val) BSP_FLD32(val, 13, 15) // Discontinuous mode channel count +#define STM32F4_ADC_CR1_DISCNUM_GET(reg) BSP_FLD32GET(reg, 13, 15) +#define STM32F4_ADC_CR1_DISCNUM_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15) +#define STM32F4_ADC_CR1_JDISCEN BSP_BIT32(12) // Discontinous mode on injected channels +#define STM32F4_ADC_CR1_DISCEN BSP_BIT32(11) // Discontinous mode on regular channels +#define STM32F4_ADC_CR1_JAUTO BSP_BIT32(10) // Automated injected group conversion +#define STM32F4_ADC_CR1_AWDSGL BSP_BIT32(9) // Enable watchdog on single channel in scan mode +#define STM32F4_ADC_CR1_SCAN BSP_BIT32(8) // Scan mode +#define STM32F4_ADC_CR1_JEOCIE BSP_BIT32(7) // Interrupt enable for injected channels +#define STM32F4_ADC_CR1_AWDIE BSP_BIT32(6) // Analog watchdog interrupt enable +#define STM32F4_ADC_CR1_EOCIE BSP_BIT32(5) // Interrupt enable for EOC +#define STM32F4_ADC_CR1_AWDCH(val) BSP_FLD32(val, 0, 4) // Analog watchdog channel select bits +#define STM32F4_ADC_CR1_AWDCH_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define STM32F4_ADC_CR1_AWDCH_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) + + uint32_t cr2; // 0x08: Control register 2 +#define STM32F4_ADC_CR2_SWSTART BSP_BIT32(30) // Start conversion of regular channels +#define STM32F4_ADC_CR2_EXTEN(val) BSP_FLD32(val, 28, 29) // External trigger enable for regular channels +#define STM32F4_ADC_CR2_EXTEN_GET(reg) BSP_FLD32GET(reg, 28, 29) +#define STM32F4_ADC_CR2_EXTEN_SET(reg, val) BSP_FLD32SET(reg, val, 28, 29) +#define STM32F4_ADC_CR2_JEXTEN(val) BSP_FLD32(val, 20, 21) // External trigger enable for injected channels +#define STM32F4_ADC_CR2_JEXTEN_GET(reg) BSP_FLD32GET(reg, 20, 21) +#define STM32F4_ADC_CR2_JEXTEN_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21) +#define ADC_CR2_TRIGGER_DISABLE 0 +#define ADC_CR2_TRIGGER_RISING 1 +#define ADC_CR2_TRIGGER_FALLING 2 +#define ADC_CR2_TRIGGER_BOTH 3 +#define STM32F4_ADC_CR2_EXTSEL(val) BSP_FLD32(val, 24, 27) // External event select for regular group +#define STM32F4_ADC_CR2_EXTSEL_GET(reg) BSP_FLD32GET(reg, 24, 27) +#define STM32F4_ADC_CR2_EXTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27) +#define ADC_CR2_EVT_TIMER1_CC1 0x0 +#define ADC_CR2_EVT_TIMER1_CC2 0x1 +#define ADC_CR2_EVT_TIMER1_CC3 0x2 +#define ADC_CR2_EVT_TIMER2_CC2 0x3 +#define ADC_CR2_EVT_TIMER2_CC3 0x4 +#define ADC_CR2_EVT_TIMER2_CC4 0x5 +#define ADC_CR2_EVT_TIMER2_TRGO 0x6 +#define ADC_CR2_EVT_TIMER3_CC1 0x7 +#define ADC_CR2_EVT_TIMER3_TRGO 0x8 +#define ADC_CR2_EVT_TIMER4_CC1 0x9 +#define ADC_CR2_EVT_TIMER5_CC1 0xa +#define ADC_CR2_EVT_TIMER5_CC2 0xb +#define ADC_CR2_EVT_TIMER5_CC3 0xc +#define ADC_CR2_EVT_TIMER8_CC1 0xd +#define ADC_CR2_EVT_TIMER8_TRGO 0xe +#define ADC_CR2_EVT_EXTI_11 0xf +#define STM32F4_ADC_CR2_JSWSTART BSP_BIT32(22) // Start conversion of injected channels +#define STM32F4_ADC_CR2_JEXTSEL(val) BSP_FLD32(val, 16, 19) // External event select for injected group +#define STM32F4_ADC_CR2_JEXTSEL_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define STM32F4_ADC_CR2_JEXTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define ADC_CR2_JEVT_TIMER1_CC4 0x0 +#define ADC_CR2_JEVT_TIMER1_TRGO 0x1 +#define ADC_CR2_JEVT_TIMER2_CC1 0x2 +#define ADC_CR2_JEVT_TIMER2_TRGO 0x3 +#define ADC_CR2_JEVT_TIMER3_CC2 0x4 +#define ADC_CR2_JEVT_TIMER3_CC4 0x5 +#define ADC_CR2_JEVT_TIMER4_CC1 0x6 +#define ADC_CR2_JEVT_TIMER4_CC2 0x7 +#define ADC_CR2_JEVT_TIMER4_CC3 0x8 +#define ADC_CR2_JEVT_TIMER4_TRGO 0x9 +#define ADC_CR2_JEVT_TIMER5_CC4 0xa +#define ADC_CR2_JEVT_TIMER5_TRGO 0xb +#define ADC_CR2_JEVT_TIMER8_CC2 0xc +#define ADC_CR2_JEVT_TIMER8_CC3 0xd +#define ADC_CR2_JEVT_TIMER8_CC4 0xe +#define ADC_CR2_JEVT_EXTI_15 0xf +#define STM32F4_ADC_CR2_ALIGN BSP_BIT32(11) // Data alignment +#define STM32F4_ADC_CR2_ALIGN_RIGHT 0 +#define STM32F4_ADC_CR2_ALIGN_LEFT STM32F4_ADC_CR2_ALIGN +#define STM32F4_ADC_CR2_EOCS BSP_BIT32(10) // End of conversion selection +#define STM32F4_ADC_CR2_DDS BSP_BIT32(9) // DMA disable selection (single ADC mode) +#define STM32F4_ADC_CR2_DMA BSP_BIT32(8) // DMA access mode (single ADC) +#define STM32F4_ADC_CR2_CONT BSP_BIT32(1) // Continuous conversion +#define STM32F4_ADC_CR2_ADON BSP_BIT32(0) // A/D converter ON + + uint32_t smpr1; // 0x0C: Sample time register 1 +#define ADC_SAMPLE_3CYCLE 0 +#define ADC_SAMPLE_15CYCLE 1 +#define ADC_SAMPLE_28CYCLE 2 +#define ADC_SAMPLE_56CYCLE 3 +#define ADC_SAMPLE_84CYCLE 4 +#define ADC_SAMPLE_112CYCLE 5 +#define ADC_SAMPLE_144CYCLE 6 +#define ADC_SAMPLE_480CYCLE 7 +#define STM32F4_ADC_SMP18(val) BSP_FLD32(val, 24, 26) // Channel 18 sampling time selection +#define STM32F4_ADC_SMP18_GET(reg) BSP_FLD32GET(reg, 24, 26) +#define STM32F4_ADC_SMP18_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) +#define STM32F4_ADC_SMP17(val) BSP_FLD32(val, 21, 23) // Channel 17 sampling time selection +#define STM32F4_ADC_SMP17_GET(reg) BSP_FLD32GET(reg, 21, 23) +#define STM32F4_ADC_SMP17_SET(reg, val) BSP_FLD32SET(reg, val, 21, 23) +#define STM32F4_ADC_SMP16(val) BSP_FLD32(val, 18, 20) // Channel 16 sampling time selection +#define STM32F4_ADC_SMP16_GET(reg) BSP_FLD32GET(reg, 18, 20) +#define STM32F4_ADC_SMP16_SET(reg, val) BSP_FLD32SET(reg, val, 18, 20) +#define STM32F4_ADC_SMP15(val) BSP_FLD32(val, 15, 17) // Channel 15 sampling time selection +#define STM32F4_ADC_SMP15_GET(reg) BSP_FLD32GET(reg, 15, 17) +#define STM32F4_ADC_SMP15_SET(reg, val) BSP_FLD32SET(reg, val, 15, 17) +#define STM32F4_ADC_SMP14(val) BSP_FLD32(val, 12, 14) // Channel 14 sampling time selection +#define STM32F4_ADC_SMP14_GET(reg) BSP_FLD32GET(reg, 12, 14) +#define STM32F4_ADC_SMP14_SET(reg, val) BSP_FLD32SET(reg, val, 12, 14) +#define STM32F4_ADC_SMP13(val) BSP_FLD32(val, 9, 11) // Channel 13 sampling time selection +#define STM32F4_ADC_SMP13_GET(reg) BSP_FLD32GET(reg, 9, 11) +#define STM32F4_ADC_SMP13_SET(reg, val) BSP_FLD32SET(reg, val, 9, 11) +#define STM32F4_ADC_SMP12(val) BSP_FLD32(val, 6, 8) // Channel 12 sampling time selection +#define STM32F4_ADC_SMP12_GET(reg) BSP_FLD32GET(reg, 6, 8) +#define STM32F4_ADC_SMP12_SET(reg, val) BSP_FLD32SET(reg, val, 6, 8) +#define STM32F4_ADC_SMP11(val) BSP_FLD32(val, 3, 5) // Channel 11 sampling time selection +#define STM32F4_ADC_SMP11_GET(reg) BSP_FLD32GET(reg, 3, 5) +#define STM32F4_ADC_SMP11_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) +#define STM32F4_ADC_SMP10(val) BSP_FLD32(val, 0, 2) // Channel 10 sampling time selection +#define STM32F4_ADC_SMP10_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define STM32F4_ADC_SMP10_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + + uint32_t smpr2; // 0x10: Sample time register 2 +#define STM32F4_ADC_SMP9(val) BSP_FLD32(val, 27, 29) // Channel 9 sampling time selection +#define STM32F4_ADC_SMP9_GET(reg) BSP_FLD32GET(reg, 27, 29) +#define STM32F4_ADC_SMP9_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29) +#define STM32F4_ADC_SMP8(val) BSP_FLD32(val, 24, 26) // Channel 8 sampling time selection +#define STM32F4_ADC_SMP8_GET(reg) BSP_FLD32GET(reg, 24, 26) +#define STM32F4_ADC_SMP8_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) +#define STM32F4_ADC_SMP7(val) BSP_FLD32(val, 21, 23) // Channel 7 sampling time selection +#define STM32F4_ADC_SMP7_GET(reg) BSP_FLD32GET(reg, 21, 23) +#define STM32F4_ADC_SMP7_SET(reg, val) BSP_FLD32SET(reg, val, 21, 23) +#define STM32F4_ADC_SMP6(val) BSP_FLD32(val, 18, 20) // Channel 6 sampling time selection +#define STM32F4_ADC_SMP6_GET(reg) BSP_FLD32GET(reg, 18, 20) +#define STM32F4_ADC_SMP6_SET(reg, val) BSP_FLD32SET(reg, val, 18, 20) +#define STM32F4_ADC_SMP5(val) BSP_FLD32(val, 15, 17) // Channel 5 sampling time selection +#define STM32F4_ADC_SMP5_GET(reg) BSP_FLD32GET(reg, 15, 17) +#define STM32F4_ADC_SMP5_SET(reg, val) BSP_FLD32SET(reg, val, 15, 17) +#define STM32F4_ADC_SMP4(val) BSP_FLD32(val, 12, 14) // Channel 4 sampling time selection +#define STM32F4_ADC_SMP4_GET(reg) BSP_FLD32GET(reg, 12, 14) +#define STM32F4_ADC_SMP4_SET(reg, val) BSP_FLD32SET(reg, val, 12, 14) +#define STM32F4_ADC_SMP3(val) BSP_FLD32(val, 9, 11) // Channel 3 sampling time selection +#define STM32F4_ADC_SMP3_GET(reg) BSP_FLD32GET(reg, 9, 11) +#define STM32F4_ADC_SMP3_SET(reg, val) BSP_FLD32SET(reg, val, 9, 11) +#define STM32F4_ADC_SMP2(val) BSP_FLD32(val, 6, 8) // Channel 2 sampling time selection +#define STM32F4_ADC_SMP2_GET(reg) BSP_FLD32GET(reg, 6, 8) +#define STM32F4_ADC_SMP2_SET(reg, val) BSP_FLD32SET(reg, val, 6, 8) +#define STM32F4_ADC_SMP1(val) BSP_FLD32(val, 3, 5) // Channel 1 sampling time selection +#define STM32F4_ADC_SMP1_GET(reg) BSP_FLD32GET(reg, 3, 5) +#define STM32F4_ADC_SMP1_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) +#define STM32F4_ADC_SMP0(val) BSP_FLD32(val, 0, 2) // Channel 0 sampling time selection +#define STM32F4_ADC_SMP0_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define STM32F4_ADC_SMP0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + + uint32_t jofr[4]; // 0x14-0x20: Injected channel data offset registers +#define STM32F4_ADC_JOFFSET(val) BSP_FLD32(val, 0, 11) // Data offset for injected channel +#define STM32F4_ADC_JOFFSET_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define STM32F4_ADC_JOFFSET_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) + + uint32_t htr; // 0x24: Watchdog higher threshold register +#define STM32F4_ADC_HT(val) BSP_FLD32(val, 0, 11) // Analog watchdog higher threshold +#define STM32F4_ADC_HT_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define STM32F4_ADC_HT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) + + uint32_t ltr; // 0x28: Watchdog lower threshold register +#define STM32F4_ADC_LT(val) BSP_FLD32(val, 0, 11) // Analog watchdog lower threshold +#define STM32F4_ADC_LT_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define STM32F4_ADC_LT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) + + uint32_t sqr[3]; // 0x2c-0x34: Regular sequence registers +#define STM32F4_ADC_SQR_L(val) BSP_FLD32(val, 20, 23) // Regular channel sequence length +#define STM32F4_ADC_SQR_L_GET(reg) BSP_FLD32GET(reg, 20, 23) +#define STM32F4_ADC_SQR_L_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23) + + uint32_t jsqr; // 0x38: Injected sequence register +#define STM32F4_ADC_JSQR_JL(val) BSP_FLD32(val, 20, 21) // Injected sequence length +#define STM32F4_ADC_JSQR_JL_GET(reg) BSP_FLD32GET(reg, 20, 21) +#define STM32F4_ADC_JSQR_JL_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21) +#define STM32F4_ADC_JSQR_JSQ4(val) BSP_FLD32(val, 15, 19) // 4th conversion in injected sequence +#define STM32F4_ADC_JSQR_JSQ4_GET(reg) BSP_FLD32GET(reg, 15, 19) +#define STM32F4_ADC_JSQR_JSQ4_SET(reg, val) BSP_FLD32SET(reg, val, 15, 19) +#define STM32F4_ADC_JSQR_JSQ3(val) BSP_FLD32(val, 10, 14) // 3rd conversion in injected sequence +#define STM32F4_ADC_JSQR_JSQ3_GET(reg) BSP_FLD32GET(reg, 10, 14) +#define STM32F4_ADC_JSQR_JSQ3_SET(reg, val) BSP_FLD32SET(reg, val, 10, 14) +#define STM32F4_ADC_JSQR_JSQ2(val) BSP_FLD32(val, 5, 9) // 2nd conversion in injected sequence +#define STM32F4_ADC_JSQR_JSQ2_GET(reg) BSP_FLD32GET(reg, 5, 9) +#define STM32F4_ADC_JSQR_JSQ2_SET(reg, val) BSP_FLD32SET(reg, val, 5, 9) +#define STM32F4_ADC_JSQR_JSQ1(val) BSP_FLD32(val, 0, 4) // 1st conversion in injected sequence +#define STM32F4_ADC_JSQR_JSQ1_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define STM32F4_ADC_JSQR_JSQ1_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) + + uint32_t jdr[4]; // 0x3c-0x48: Injected data registers +#define STM32F4_ADC_JDATA(val) BSP_FLD32(val, 0, 15) // Injected data +#define STM32F4_ADC_JDATA_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_ADC_JDATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t dr; // 0x4c: Regular data register +#define STM32F4_ADC_DATA(val) BSP_FLD32(val, 0, 15) // Regular data +#define STM32F4_ADC_DATA_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_ADC_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + +} __attribute__ ((packed)); +typedef struct stm32f4_adc_chan_s stm32f4_adc_chan; + +struct stm32f4_adc_com_s { + uint32_t csr; // 0x00: Common status register +#define STM32F4_ADC_CSR_OVR3 BSP_BIT32(21) // Overrun flag ADC3 +#define STM32F4_ADC_CSR_STRT3 BSP_BIT32(20) // Regular start flag ADC3 +#define STM32F4_ADC_CSR_JSTRT3 BSP_BIT32(19) // Injected start flag ADC3 +#define STM32F4_ADC_CSR_JEOC3 BSP_BIT32(18) // Injected channel end of conversion flag ADC3 +#define STM32F4_ADC_CSR_EOC3 BSP_BIT32(17) // Channel end of conversion flag ADC3 +#define STM32F4_ADC_CSR_AWD3 BSP_BIT32(16) // Analog watchdog flag ADC3 +#define STM32F4_ADC_CSR_OVR2 BSP_BIT32(13) // Overrun flag ADC2 +#define STM32F4_ADC_CSR_STRT2 BSP_BIT32(12) // Regular start flag ADC2 +#define STM32F4_ADC_CSR_JSTRT2 BSP_BIT32(11) // Injected start flag ADC2 +#define STM32F4_ADC_CSR_JEOC2 BSP_BIT32(10) // Injected channel end of conversion flag ADC2 +#define STM32F4_ADC_CSR_EOC2 BSP_BIT32(9) // Channel end of conversion flag ADC2 +#define STM32F4_ADC_CSR_AWD2 BSP_BIT32(8) // Analog watchdog flag ADC2 +#define STM32F4_ADC_CSR_OVR1 BSP_BIT32(5) // Overrun flag ADC1 +#define STM32F4_ADC_CSR_STRT1 BSP_BIT32(4) // Regular start flag ADC1 +#define STM32F4_ADC_CSR_JSTRT1 BSP_BIT32(3) // Injected start flag ADC1 +#define STM32F4_ADC_CSR_JEOC1 BSP_BIT32(2) // Injected channel end of conversion flag ADC1 +#define STM32F4_ADC_CSR_EOC1 BSP_BIT32(1) // Channel end of conversion flag ADC1 +#define STM32F4_ADC_CSR_AWD1 BSP_BIT32(0) // Analog watchdog flag ADC1 + + uint32_t ccr; // 0x00: Common control register +#define STM32F4_ADC_CCR_TSVREFE BSP_BIT32(23) // Temp sensor and Vrefint enable +#define STM32F4_ADC_CCR_VBATE BSP_BIT32(22) // Vbat enable +#define STM32F4_ADC_CCR_ADCPRE(val) BSP_FLD32(val, 16, 17) // ADC prescalar +#define STM32F4_ADC_CCR_ADCPRE_GET(reg) BSP_FLD32GET(reg, 16, 17) +#define STM32F4_ADC_CCR_ADCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) +#define ADC_ADCPRE_PCLK2_2 0 +#define ADC_ADCPRE_PCLK2_4 1 +#define ADC_ADCPRE_PCLK2_6 2 +#define ADC_ADCPRE_PCLK2_8 3 +#define STM32F4_ADC_CCR_DMA(val) BSP_FLD32(val, 14, 15) // DMA access mode for multi ADC +#define STM32F4_ADC_CCR_DMA_GET(reg) BSP_FLD32GET(reg, 14, 15) +#define STM32F4_ADC_CCR_DMA_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15) +#define ADC_DMA_DISABLE 0 +#define ADC_DMA_MODE1 1 +#define ADC_DMA_MODE2 2 +#define ADC_DMA_MODE3 3 +#define STM32F4_ADC_CCR_DDS BSP_BIT32(13) // DMA disable selection +#define STM32F4_ADC_CCR_DELAY(val) BSP_FLD32(val, 8, 11) // Delay between sampling phases +#define STM32F4_ADC_CCR_DELAY_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_ADC_CCR_DELAY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define ADC_DELAY_5T 0 +#define ADC_DELAY_6T 1 +#define ADC_DELAY_7T 2 +#define ADC_DELAY_8T 3 +#define ADC_DELAY_9T 4 +#define ADC_DELAY_10T 5 +#define ADC_DELAY_11T 6 +#define ADC_DELAY_12T 7 +#define ADC_DELAY_13T 8 +#define ADC_DELAY_14T 9 +#define ADC_DELAY_15T 10 +#define ADC_DELAY_16T 11 +#define ADC_DELAY_17T 12 +#define ADC_DELAY_18T 13 +#define ADC_DELAY_19T 14 +#define ADC_DELAY_20T 15 +#define STM32F4_ADC_CCR_MULTI(val) BSP_FLD32(val, 0, 4) // Multi ADC mode +#define STM32F4_ADC_CCR_MULTI_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define STM32F4_ADC_CCR_MULTI_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define ADC_MULTI_INDEPENDENT 0x00 +#define ADC_MULTI_DUAL_REG_INJ 0x01 +#define ADC_MULTI_DUAL_REG_ALT 0x02 +#define ADC_MULTI_DUAL_INJ 0x05 +#define ADC_MULTI_DUAL_REG 0x06 +#define ADC_MULTI_DUAL_INTRL 0x07 +#define ADC_MULTI_DUAL_ALT_TRIG 0x09 +#define ADC_MULTI_TRIPLE_REG_INJ 0x11 +#define ADC_MULTI_TRIPLE_REG_ALT 0x12 +#define ADC_MULTI_TRIPLE_INJ 0x15 +#define ADC_MULTI_TRIPLE_REG 0x16 +#define ADC_MULTI_TRIPLE_INTRL 0x17 +#define ADC_MULTI_TRIPLE_ALT_TRIG 0x19 + + uint32_t cdr; // 0x00: Common regular data register +#define STM32F4_ADC_CDR_DATA2(val) BSP_FLD32(val, 16, 31) // 2nd data item +#define STM32F4_ADC_CDR_DATA2_GET(reg) BSP_FLD32GET(reg, 16, 31) +#define STM32F4_ADC_CDR_DATA2_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) +#define STM32F4_ADC_CDR_DATA1(val) BSP_FLD32(val, 0, 15) // 1st data item +#define STM32F4_ADC_CDR_DATA1_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_ADC_CDR_DATA1_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + +} __attribute__ ((packed)); +typedef struct stm32f4_adc_com_s stm32f4_adc_com; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_exti.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_exti.h new file mode 100644 index 0000000000..df44ad56e8 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_exti.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H + +#include + +#define EXTI_PORTA 0 +#define EXTI_PORTB 1 +#define EXTI_PORTC 2 +#define EXTI_PORTD 3 +#define EXTI_PORTE 4 +#define EXTI_PORTF 5 +#define EXTI_PORTG 6 +#define EXTI_PORTH 7 +#define EXTI_PORTI 8 + +#define STM32F4_EXTI_LINE22 BSP_BIT32(21) +#define STM32F4_EXTI_LINE21 BSP_BIT32(21) +#define STM32F4_EXTI_LINE20 BSP_BIT32(20) +#define STM32F4_EXTI_LINE19 BSP_BIT32(19) +#define STM32F4_EXTI_LINE18 BSP_BIT32(18) +#define STM32F4_EXTI_LINE17 BSP_BIT32(17) +#define STM32F4_EXTI_LINE16 BSP_BIT32(16) +#define STM32F4_EXTI_LINE15 BSP_BIT32(15) +#define STM32F4_EXTI_LINE14 BSP_BIT32(14) +#define STM32F4_EXTI_LINE13 BSP_BIT32(13) +#define STM32F4_EXTI_LINE12 BSP_BIT32(12) +#define STM32F4_EXTI_LINE11 BSP_BIT32(11) +#define STM32F4_EXTI_LINE10 BSP_BIT32(10) +#define STM32F4_EXTI_LINE9 BSP_BIT32(9) +#define STM32F4_EXTI_LINE8 BSP_BIT32(8) +#define STM32F4_EXTI_LINE7 BSP_BIT32(7) +#define STM32F4_EXTI_LINE6 BSP_BIT32(6) +#define STM32F4_EXTI_LINE5 BSP_BIT32(5) +#define STM32F4_EXTI_LINE4 BSP_BIT32(4) +#define STM32F4_EXTI_LINE3 BSP_BIT32(3) +#define STM32F4_EXTI_LINE2 BSP_BIT32(2) +#define STM32F4_EXTI_LINE1 BSP_BIT32(1) +#define STM32F4_EXTI_LINE0 BSP_BIT32(0) + +struct stm32f4_exti_s { + uint32_t imr; // Interrupt mask + uint32_t emr; // Event mask + uint32_t rtsr; // Rising trigger selection + uint32_t ftsr; // Falling trigger selection + uint32_t swier; // Software interrupt event + uint32_t pr; // Pending +} __attribute__ ((packed)); +typedef struct stm32f4_exti_s stm32f4_exti; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h new file mode 100755 index 0000000000..f81b19cd40 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H + +#include + +struct stm32f4_flash_s { + + uint32_t acr; // Access and control register +#define STM32F4_FLASH_ACR_DCRST BSP_BIT32(12) // Data cache reset +#define STM32F4_FLASH_ACR_ICRST BSP_BIT32(11) // Instruction cache reset +#define STM32F4_FLASH_ACR_DCEN BSP_BIT32(10) // Data cache enable +#define STM32F4_FLASH_ACR_ICEN BSP_BIT32(9) // Instruction cache enable +#define STM32F4_FLASH_ACR_PRFTEN BSP_BIT32(8) // Prefetch enable +#define STM32F4_FLASH_ACR_LATENCY(val) BSP_FLD32(val, 0, 2) // Flash access latency +#define STM32F4_FLASH_ACR_LATENCY_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define STM32F4_FLASH_ACR_LATENCY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + + uint32_t keyr; // Key register +#define STM32F4_FLASH_KEYR_KEY1 0x45670123 +#define STM32F4_FLASH_KEYR_KEY2 0xCDEF89AB + + uint32_t optkeyr; // Option key register +#define STM32F4_FLASH_OPTKEYR_OPTKEY1 0x08192A3B +#define STM32F4_FLASH_OPTKEYR_OPTKEY2 0x4C5D6E7F + + uint32_t sr; // Status register +#define STM32F4_FLASH_SR_BSY BSP_BIT32(16) // Busy +#define STM32F4_FLASH_SR_PGSERR BSP_BIT32(7) // Programming sequence error +#define STM32F4_FLASH_SR_PGPERR BSP_BIT32(6) // Programming parallelism error +#define STM32F4_FLASH_SR_PGAERR BSP_BIT32(5) // Programming alignment error +#define STM32F4_FLASH_SR_WRPERR BSP_BIT32(4) // Write protection error +#define STM32F4_FLASH_SR_OPERR BSP_BIT32(1) // Operation error +#define STM32F4_FLASH_SR_EOP BSP_BIT32(0) // End of operation + + uint32_t cr; // Control register +#define STM32F4_FLASH_CR_LOCK BSP_BIT32(31) // Lock +#define STM32F4_FLASH_CR_ERRIE BSP_BIT32(25) // Error interrupt enable +#define STM32F4_FLASH_CR_EOPIE BSP_BIT32(24) // End of operation interrupt enable +#define STM32F4_FLASH_CR_STRT BSP_BIT32(16) // Start +#define STM32F4_FLASH_CR_PSIZE(val) BSP_FLD32(val, 8, 9) // Program size +#define STM32F4_FLASH_CR_PSIZE_GET(reg) BSP_FLD32GET(reg, 8, 9) +#define STM32F4_FLASH_CR_PSIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9) +#define STM32F4_FLASH_CR_SNB BSP_FLD32(val, 3, 6) // Sector number +#define STM32F4_FLASH_CR_SNB_GET(reg) BSP_FLD32GET(reg, 3, 6) +#define STM32F4_FLASH_CR_SNB_SET(reg, val) BSP_FLD32SET(reg, val, 3, 6) +#define STM32F4_FLASH_CR_MER BSP_BIT32(2) // Mass erase +#define STM32F4_FLASH_CR_SER BSP_BIT32(1) // Sector erase +#define STM32F4_FLASH_CR_PG BSP_BIT32(0) // Programming + + uint32_t optcr; // Option control register +#define STM32F4_FLASH_OPTCR_NWRP(val) BSP_FLD32(val, 16, 27) // Not write protect +#define STM32F4_FLASH_OPTCR_NWRP_GET(reg) BSP_FLD32GET(reg, 16, 27) +#define STM32F4_FLASH_OPTCR_NWRP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 27) +#define STM32F4_FLASH_OPTCR_RDP(val) BSP_FLD32(val, 8, 15) // Read protect +#define STM32F4_FLASH_OPTCR_RDP_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define STM32F4_FLASH_OPTCR_RDP_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define STM32F4_FLASH_OPTCR_USER(val) BSP_FLD32(val, 5, 7) // User option bytes +#define STM32F4_FLASH_OPTCR_USER_GET(reg) BSP_FLD32GET(reg, 5, 7) +#define STM32F4_FLASH_OPTCR_USER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) +#define STM32F4_FLASH_OPTCR_BOR_LEVEL(val) BSP_FLD32(val, 2, 3) // BOR reset level +#define STM32F4_FLASH_OPTCR_BOR_LEVEL_GET(reg) BSP_FLD32GET(reg, 2, 3) +#define STM32F4_FLASH_OPTCR_BOR_LEVEL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3) +#define STM32F4_FLASH_CR_OPTSTRT BSP_BIT32(1) // Option start +#define STM32F4_FLASH_CR_OPTLOCK BSP_BIT32(0) // Option lock + +} __attribute__ ((packed)); +typedef struct stm32f4_flash_s stm32f4_flash; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_gpio.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_gpio.h new file mode 100644 index 0000000000..b129c23595 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_gpio.h @@ -0,0 +1,39 @@ +/** + * @file + * @ingroup stm32f4_gpio + * @brief STM32F4XXXX GPIO support. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_GPIO_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_GPIO_H + +#include + +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afr [2]; + uint32_t reserved_28 [246]; +} stm32f4_gpio; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_GPIO_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_otgfs.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_otgfs.h new file mode 100755 index 0000000000..cc2eb90c4c --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_otgfs.h @@ -0,0 +1,445 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H + +#include + +#define USB_OTG_NUM_EPS 4 +#define USB_OTG_MAX_TX_FIFOS 4 + +#define USB_FIFO_BASE 0x1000 +#define USB_FIFO_OFFS 0x1000 + +struct stm32f4_otgfs_s { + uint32_t gotgctl; // 0x00: Control and status register +#define STM32F4_OTGFS_GOTGCTL_BSVLD BSP_BIT32(19) // B-session valid +#define STM32F4_OTGFS_GOTGCTL_ASVLD BSP_BIT32(18) // A-session valid +#define STM32F4_OTGFS_GOTGCTL_DBCT BSP_BIT32(17) // Debounce time +#define STM32F4_OTGFS_GOTGCTL_CIDSTS BSP_BIT32(16) // Connector ID status +#define STM32F4_OTGFS_GOTGCTL_DHNPEN BSP_BIT32(11) // Device HNP enable +#define STM32F4_OTGFS_GOTGCTL_HSHNPEN BSP_BIT32(10) // Host set HNP enable +#define STM32F4_OTGFS_GOTGCTL_HNPRQ BSP_BIT32(9) // HNP request +#define STM32F4_OTGFS_GOTGCTL_HNGSCS BSP_BIT32(8) // Host negotiation status +#define STM32F4_OTGFS_GOTGCTL_SRQ BSP_BIT32(1) // Session request +#define STM32F4_OTGFS_GOTGCTL_SRQSCS BSP_BIT32(0) // Session request success + + uint32_t gotgint; // 0x04: Interrupt register +#define STM32F4_OTGFS_GOTGINT_DBCDNE BSP_BIT32(19) // Debounce done +#define STM32F4_OTGFS_GOTGINT_ADTOCHG BSP_BIT32(18) // A-device timeout change +#define STM32F4_OTGFS_GOTGINT_HNGDET BSP_BIT32(17) // Host negotiation detected +#define STM32F4_OTGFS_GOTGINT_HNSSCHG BSP_BIT32(9) // Host negotiation success status change +#define STM32F4_OTGFS_GOTGINT_SRSSCHG BSP_BIT32(8) // Session request status change +#define STM32F4_OTGFS_GOTGINT_SEDET BSP_BIT32(2) // Session end detected + + uint32_t gahbcfg; // 0x08: AHB configuration register +#define STM32F4_OTGFS_GAHBCFG_PTXFELVL BSP_BIT32(8) // Periodic txfifo empty level +#define STM32F4_OTGFS_GAHBCFG_TXFELVL BSP_BIT32(7) // Txfifo empty level +#define STM32F4_OTGFS_GAHBCFG_GINTMSK BSP_BIT32(0) // Global interrupt mask + + uint32_t gusbcfg; // 0x0C: USB configuration register +#define STM32F4_OTGFS_GUSBCFG_CTXPKT BSP_BIT32(31) // Corrupt TX packet +#define STM32F4_OTGFS_GUSBCFG_FDMOD BSP_BIT32(30) // Force device mode +#define STM32F4_OTGFS_GUSBCFG_FHMOD BSP_BIT32(29) // Force host mode +#define STM32F4_OTGFS_GUSBCFG_TRDT(val) BSP_FLD32(val, 10, 13) // USB turnaround time +#define STM32F4_OTGFS_GUSBCFG_TRDT_GET(reg) BSP_FLD32GET(reg, 10, 13) +#define STM32F4_OTGFS_GUSBCFG_TRDT_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13) +#define STM32F4_OTGFS_GUSBCFG_HNPCAP BSP_BIT32(9) // HNP-capable +#define STM32F4_OTGFS_GUSBCFG_SRPCAP BSP_BIT32(8) // SRP-capable +#define STM32F4_OTGFS_GUSBCFG_PHYSEL BSP_BIT32(6) // Full speed serial transceiver select +#define STM32F4_OTGFS_GUSBCFG_TOCAL(val) BSP_FLD32(val, 0, 2) // FS timeout calibration +#define STM32F4_OTGFS_GUSBCFG_TOCAL_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define STM32F4_OTGFS_GUSBCFG_TOCAL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + + uint32_t grstctl; // 0x10: Reset register +#define STM32F4_OTGFS_GRSTCTL_AHBIDL BSP_BIT32(31) // AHB master idle +#define STM32F4_OTGFS_GRSTCTL_TXFNUM(val) BSP_FLD32(val, 6, 10) // Tx fifo number +#define STM32F4_OTGFS_GRSTCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 6, 10) +#define STM32F4_OTGFS_GRSTCTL_TXFNUM_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10) +#define STM32F4_OTGFS_GRSTCTL_TXFNUM_ALL STM32F4_OTGFS_GRSTCTL_TXFNUM(0x10) +#define STM32F4_OTGFS_GRSTCTL_TXFFLSH BSP_BIT32(5) // TX fifo flush +#define STM32F4_OTGFS_GRSTCTL_RXFFLSH BSP_BIT32(4) // RX fifo flush +#define STM32F4_OTGFS_GRSTCTL_FCRST BSP_BIT32(2) // Host frame counter reset +#define STM32F4_OTGFS_GRSTCTL_HSRST BSP_BIT32(1) // HCLK soft reset +#define STM32F4_OTGFS_GRSTCTL_CSRST BSP_BIT32(0) // Core soft reset + + uint32_t gintsts; // 0x14: Core interrupt register +#define STM32F4_OTGFS_GINTSTS_WKUPINT BSP_BIT32(31) // Resume / remote wakeup detected interrupt +#define STM32F4_OTGFS_GINTSTS_SRQINT BSP_BIT32(30) // Session request / new session detected interrupt +#define STM32F4_OTGFS_GINTSTS_DISCINT BSP_BIT32(29) // Disconnect detected interrupt +#define STM32F4_OTGFS_GINTSTS_CIDSCHG BSP_BIT32(28) // Connector ID status change +#define STM32F4_OTGFS_GINTSTS_PTXFE BSP_BIT32(26) // Periodic TX fifo empty +#define STM32F4_OTGFS_GINTSTS_HCINT BSP_BIT32(25) // Host channels interrupt +#define STM32F4_OTGFS_GINTSTS_HPRTINT BSP_BIT32(24) // Host port interrupt +#define STM32F4_OTGFS_GINTSTS_IPXFR BSP_BIT32(21) // Incomplete periodic transfer +#define STM32F4_OTGFS_GINTSTS_IISOOXFR BSP_BIT32(21) // Incomplete isochronous OUT transfer +#define STM32F4_OTGFS_GINTSTS_IISOIXFR BSP_BIT32(20) // Incomplete isochronous IN transfer +#define STM32F4_OTGFS_GINTSTS_OEPINT BSP_BIT32(19) // OUT endpoint interrupt +#define STM32F4_OTGFS_GINTSTS_IEPINT BSP_BIT32(18) // IN endpoint interrupt +#define STM32F4_OTGFS_GINTSTS_EOPF BSP_BIT32(15) // End of periodic frame interrupt +#define STM32F4_OTGFS_GINTSTS_ISOODRP BSP_BIT32(14) // Isochronous OUT packet dropped interrupt +#define STM32F4_OTGFS_GINTSTS_ENUMDNE BSP_BIT32(13) // Enumeration done +#define STM32F4_OTGFS_GINTSTS_USBRST BSP_BIT32(12) // USB reset +#define STM32F4_OTGFS_GINTSTS_USBSUSP BSP_BIT32(11) // USB suspend +#define STM32F4_OTGFS_GINTSTS_ESUSP BSP_BIT32(10) // Early suspend +#define STM32F4_OTGFS_GINTSTS_GONAKEFF BSP_BIT32(7) // Global OUT NAK effective +#define STM32F4_OTGFS_GINTSTS_GINAKEFF BSP_BIT32(6) // Global IN non-periodic NAK effective +#define STM32F4_OTGFS_GINTSTS_NPTXFE BSP_BIT32(5) // Non-periodic TX fifo empty +#define STM32F4_OTGFS_GINTSTS_RXFLVL BSP_BIT32(4) // RX fifo non-empty +#define STM32F4_OTGFS_GINTSTS_SOF BSP_BIT32(3) // Start of frame +#define STM32F4_OTGFS_GINTSTS_OTGINT BSP_BIT32(2) // OTG interrupt +#define STM32F4_OTGFS_GINTSTS_MMIS BSP_BIT32(1) // Mode mismatch interrupt +#define STM32F4_OTGFS_GINTSTS_CMOD BSP_BIT32(0) // Current mode of operation + + uint32_t gintmsk; // 0x18: Interrupt mask register + + uint32_t grxstsr; // 0x1C: Receive status debug read + + uint32_t grxstsp; // 0x20: OTG status read and pop +#define STM32F4_OTGFS_GRXSTSP_FRMNUM(val) BSP_FLD32(val, 21, 24) // Frame number +#define STM32F4_OTGFS_GRXSTSP_FRMNUM_GET(reg) BSP_FLD32GET(reg, 21, 24) +#define STM32F4_OTGFS_GRXSTSP_FRMNUM_SET(reg, val) BSP_FLD32SET(reg, val, 21, 24) +#define STM32F4_OTGFS_GRXSTSP_PKTSTS(val) BSP_FLD32(val, 17, 20) // Packet status +#define STM32F4_OTGFS_GRXSTSP_PKTSTS_GET(reg) BSP_FLD32GET(reg, 17, 20) +#define STM32F4_OTGFS_GRXSTSP_PKTSTS_SET(reg, val) BSP_FLD32SET(reg, val, 17, 20) +#define PKTSTS_IN_DATA (0x2) +#define PKTSTS_IN_COMPLETE (0x3) +#define PKTSTS_TOGGLE_ERR (0x5) +#define PKTSTS_HALTED (0x7) +#define PKTSTS_OUTNAK (0x1) +#define PKTSTS_OUT_DATA (0x2) +#define PKTSTS_OUT_COMPLETE (0x3) +#define PKTSTS_SETUP_COMPLETE (0x4) +#define PKTSTS_SETUP_DATA (0x6) +#define STM32F4_OTGFS_GRXSTSP_DPIG(val) BSP_FLD32(val, 15, 16) // Data PID +#define STM32F4_OTGFS_GRXSTSP_DPID_GET(reg) BSP_FLD32GET(reg, 15, 16) +#define STM32F4_OTGFS_GRXSTSP_DPID_SET(reg, val) BSP_FLD32SET(reg, val, 15, 16) +#define STM32F4_OTGFS_GRXSTSP_DPID_DATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x0) +#define STM32F4_OTGFS_GRXSTSP_DPID_DATA1 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x1) +#define STM32F4_OTGFS_GRXSTSP_DPID_DATA2 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x2) +#define STM32F4_OTGFS_GRXSTSP_DPID_MDATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x3) +#define STM32F4_OTGFS_GRXSTSP_BCNT(val) BSP_FLD32(val, 4, 14) // Byte count +#define STM32F4_OTGFS_GRXSTSP_BCNT_GET(reg) BSP_FLD32GET(reg, 4, 14) +#define STM32F4_OTGFS_GRXSTSP_BCNT_SET(reg, val) BSP_FLD32SET(reg, val, 4, 14) +#define STM32F4_OTGFS_GRXSTSP_CHNUM(val) BSP_FLD32(val, 0, 3) // Channel number +#define STM32F4_OTGFS_GRXSTSP_CHNUM_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_OTGFS_GRXSTSP_CHNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_OTGFS_GRXSTSP_EPNUM(val) BSP_FLD32(val, 0, 3) // Endpoint number +#define STM32F4_OTGFS_GRXSTSP_EPNUM_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_OTGFS_GRXSTSP_EPNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + + uint32_t grxfsiz; // 0x24: Receive FIFO size register +#define STM32F4_OTGFS_GRXFSIZ_RXFD(val) BSP_FLD32(val, 0, 15) +#define STM32F4_OTGFS_GRXFSIZ_RXFD_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_GRXFSIZ_RXFD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) +#define STM32F4_OTGFS_GRXFSIZ_RXFD_MIN 16 +#define STM32F4_OTGFS_GRXFSIZ_RXFD_MAX 256 + + uint32_t dieptxf0; // 0x28: EP 0 transmit fifo size +#define STM32F4_OTGFS_DIEPTXF_DEPTH(val) BSP_FLD32(val, 16, 31) +#define STM32F4_OTGFS_DIEPTXF_DEPTH_GET(reg) BSP_FLD32GET(reg, 16, 31) +#define STM32F4_OTGFS_DIEPTXF_DEPTH_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) +#define STM32F4_OTGFS_DIEPTXF_DEPTH_MIN 16 +#define STM32F4_OTGFS_DIEPTXF_DEPTH_MAX 256 +#define STM32F4_OTGFS_DIEPTXF_SADDR(val) BSP_FLD32(val, 0, 15) +#define STM32F4_OTGFS_DIEPTXF_SADDR_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_DIEPTXF_SADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t resv2C; + + uint32_t gi2cctl; // 0x30 + uint32_t resv34; // 0x34 + + uint32_t gccfg; // 0x38: General core configuration register +#define STM32F4_OTGFS_GCCFG_NOVBUSSENS BSP_BIT32(21) // Vbus sensing disable +#define STM32F4_OTGFS_GCCFG_SOFOUTEN BSP_BIT32(20) // SOF output enable +#define STM32F4_OTGFS_GCCFG_VBUSBSEN BSP_BIT32(19) // Vbus sensing "B" device +#define STM32F4_OTGFS_GCCFG_VBUSASEN BSP_BIT32(18) // Vbus sensing "A" device +#define STM32F4_OTGFS_GCCFG_PWRDWN BSP_BIT32(16) // Power down + + uint32_t cid; // 0x3C: Product ID + + uint32_t resv40[48]; // 0x40 - 0x9C + + uint32_t hptxfsiz; // 0x100 + + uint32_t dieptxf[USB_OTG_MAX_TX_FIFOS]; // 0x104 + +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_s stm32f4_otgfs; + +struct stm32f4_otgfs_dregs_s { + uint32_t dcfg; // 0x800 +#define STM32F4_OTGFS_DCFG_PFIVL(val) BSP_FLD32(val, 11, 12) // Periodic frame interval +#define STM32F4_OTGFS_DCFG_PFIVL_GET(reg) BSP_FLD32GET(reg, 11, 12) +#define STM32F4_OTGFS_DCFG_PFIVL_SET(reg, val) BSP_FLD32SET(reg, val, 11, 12) +#define PFIVL_80 0 +#define PFIVL_85 1 +#define PFIVL_90 2 +#define PFIVL_95 3 +#define STM32F4_OTGFS_DCFG_DAD(val) BSP_FLD32(val, 4, 10) // Device address +#define STM32F4_OTGFS_DCFG_DAD_GET(reg) BSP_FLD32GET(reg, 4, 10) +#define STM32F4_OTGFS_DCFG_DAD_SET(reg, val) BSP_FLD32SET(reg, val, 4, 10) +#define STM32F4_OTGFS_DCFG_NZLSOHSK BSP_BIT32(2) // Non-zero-length status OUT handshake +#define STM32F4_OTGFS_DCFG_DSPD(val) BSP_FLD32(val, 0, 1) // Device speed +#define STM32F4_OTGFS_DCFG_DSPD_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define STM32F4_OTGFS_DCFG_DSPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define STM32F4_OTGFS_DCFG_DSPD_FULL STM32F4_OTGFS_DCFG_DSPD(0x3) + + uint32_t dctl; // 0x804 +#define STM32F4_OTGFS_DCTL_POPRGDNE BSP_BIT32(11) // Power-on programming done +#define STM32F4_OTGFS_DCTL_CGONAK BSP_BIT32(10) // Clear global OUT NAK +#define STM32F4_OTGFS_DCTL_SGONAK BSP_BIT32(9) // Set global OUT NAK +#define STM32F4_OTGFS_DCTL_CGINAK BSP_BIT32(8) // Clear global IN NAK +#define STM32F4_OTGFS_DCTL_SGINAK BSP_BIT32(7) // Set global IN NAK +#define STM32F4_OTGFS_DCTL_TCTL(val) BSP_FLD32(val, 4, 6) // Test control +#define STM32F4_OTGFS_DCTL_TCTL_GET(reg) BSP_FLD32GET(reg, 4, 6) +#define STM32F4_OTGFS_DCTL_TCTL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 6) +#define STM32F4_OTGFS_DCTL_GONSTS BSP_BIT32(3) // Global OUT NAK status +#define STM32F4_OTGFS_DCTL_GINSTS BSP_BIT32(2) // Global IN NAK status +#define STM32F4_OTGFS_DCTL_SDIS BSP_BIT32(1) // Soft disconnect +#define STM32F4_OTGFS_DCTL_RWUSIG BSP_BIT32(0) // Remote wakeup signalling + + uint32_t dsts; // 0x808 +#define STM32F4_OTGFS_DSTS_FNSOF(val) BSP_FLD32(val, 8, 21) // Frame number of received SOF +#define STM32F4_OTGFS_DSTS_FNSOF_GET(reg) BSP_FLD32GET(reg, 8, 21) +#define STM32F4_OTGFS_DSTS_EERR BSP_BIT32(3) // Erratic error +#define STM32F4_OTGFS_DSTS_ENUMSPD(val) BSP_FLD32(val, 1, 2) // Enumerated speed +#define STM32F4_OTGFS_DSTS_ENUMSPD_GET(reg) BSP_FLD32GET(reg, 1, 2) +#define STM32F4_OTGFS_DSTS_ENUMSPD_FULL STM32F4_OTGFS_DSTS_ENUMSPD(0x3) +#define STM32F4_OTGFS_DSTS_SUSPSTS BSP_BIT32(0) // Suspend status + + uint32_t unused4; // 0x80C + + uint32_t diepmsk; // 0x810 + + uint32_t doepmsk; // 0x814 + + uint32_t daint; // 0x818 +#define STM32F4_OTGFS_DAINT_OEPINT15 BSP_BIT32(31) // OUT endpoint 15 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT14 BSP_BIT32(30) // OUT endpoint 14 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT13 BSP_BIT32(29) // OUT endpoint 13 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT12 BSP_BIT32(28) // OUT endpoint 12 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT11 BSP_BIT32(27) // OUT endpoint 11 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT10 BSP_BIT32(26) // OUT endpoint 10 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT9 BSP_BIT32(25) // OUT endpoint 9 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT8 BSP_BIT32(24) // OUT endpoint 8 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT7 BSP_BIT32(23) // OUT endpoint 7 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT6 BSP_BIT32(22) // OUT endpoint 6 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT5 BSP_BIT32(21) // OUT endpoint 5 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT4 BSP_BIT32(20) // OUT endpoint 4 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT3 BSP_BIT32(19) // OUT endpoint 3 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT2 BSP_BIT32(18) // OUT endpoint 2 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT1 BSP_BIT32(17) // OUT endpoint 1 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT0 BSP_BIT32(16) // OUT endpoint 0 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT15 BSP_BIT32(15) // IN endpoint 15 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT14 BSP_BIT32(14) // IN endpoint 14 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT13 BSP_BIT32(13) // IN endpoint 13 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT12 BSP_BIT32(12) // IN endpoint 12 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT11 BSP_BIT32(11) // IN endpoint 11 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT10 BSP_BIT32(10) // IN endpoint 10 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT9 BSP_BIT32(9) // IN endpoint 9 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT8 BSP_BIT32(8) // IN endpoint 8 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT7 BSP_BIT32(7) // IN endpoint 7 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT6 BSP_BIT32(6) // IN endpoint 6 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT5 BSP_BIT32(5) // IN endpoint 5 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT4 BSP_BIT32(4) // IN endpoint 4 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT3 BSP_BIT32(3) // IN endpoint 3 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT2 BSP_BIT32(2) // IN endpoint 2 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT1 BSP_BIT32(1) // IN endpoint 1 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT0 BSP_BIT32(0) // IN endpoint 0 interrupt + + uint32_t daintmsk; // 0x81C +#define STM32F4_OTGFS_DAINTMSK_OEPM(val) BSP_FLD32(val, 16, 31) // OUT endpoint interrupt mask +#define STM32F4_OTGFS_DAINTMSK_OEPM_GET(reg) BSP_FLD32GET(reg, 16, 31) +#define STM32F4_OTGFS_DAINTMSK_OEPM_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) +#define STM32F4_OTGFS_DAINTMSK_IEPM(val) BSP_FLD32(val, 0, 15) // IN endpoint interrupt mask +#define STM32F4_OTGFS_DAINTMSK_IEPM_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_DAINTMSK_IEPM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t unused5[2]; // 0x820 - 0x824 + + uint32_t dvbusdis; // 0x828 +#define STM32F4_OTGFS_DVBUSDIS_VBUSDT(val) BSP_FLD32(val, 0, 15) // Device Vbus discharge time +#define STM32F4_OTGFS_DVBUSDIS_VBUSDT_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_DVBUSDIS_VBUSDT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t dvbuspulse; // 0x82C +#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP(val) BSP_FLD32(val, 0, 15) // Device Vbus pulsing time +#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t unused6; // 0x830 + + uint32_t diepempmsk; // 0x834 +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM15 BSP_BIT32(15) // IN endpoint 15 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM14 BSP_BIT32(14) // IN endpoint 14 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM13 BSP_BIT32(13) // IN endpoint 13 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM12 BSP_BIT32(12) // IN endpoint 12 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM11 BSP_BIT32(11) // IN endpoint 11 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM10 BSP_BIT32(10) // IN endpoint 10 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM9 BSP_BIT32(9) // IN endpoint 9 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM8 BSP_BIT32(8) // IN endpoint 8 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM7 BSP_BIT32(7) // IN endpoint 7 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM6 BSP_BIT32(6) // IN endpoint 6 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM5 BSP_BIT32(5) // IN endpoint 5 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM4 BSP_BIT32(4) // IN endpoint 4 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM3 BSP_BIT32(3) // IN endpoint 3 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM2 BSP_BIT32(2) // IN endpoint 2 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM1 BSP_BIT32(1) // IN endpoint 1 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM0 BSP_BIT32(0) // IN endpoint 0 TxFIFO empty interrupt mask + +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_dregs_s stm32f4_otgfs_dregs; + +struct stm32f4_otgfs_inepregs_s { + uint32_t diepctl; // 0x900 +#define STM32F4_OTGFS_DIEPCTL_EPENA BSP_BIT32(31) // Endpoint enable +#define STM32F4_OTGFS_DIEPCTL_EPDIS BSP_BIT32(30) // Endpoint disable +#define STM32F4_OTGFS_DIEPCTL_SODDFRM BSP_BIT32(29) // Set odd frame +#define STM32F4_OTGFS_DIEPCTL_SD0PID BSP_BIT32(28) // Set DATA0 PID / Set even frame +#define STM32F4_OTGFS_DIEPCTL_SEVNFRM BSP_BIT32(28) // Set DATA0 PID / Set even frame +#define STM32F4_OTGFS_DIEPCTL_SNAK BSP_BIT32(27) // Set NAK +#define STM32F4_OTGFS_DIEPCTL_CNAK BSP_BIT32(26) // Clear NAK +#define STM32F4_OTGFS_DIEPCTL_TXFNUM(val) BSP_FLD32(val, 22, 25) // TxFIFO number +#define STM32F4_OTGFS_DIEPCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 22, 25) +#define STM32F4_OTGFS_DIEPCTL_TXFNUM_SET(reg, val) BSP_FLD32SET(reg, val, 22, 25) +#define STM32F4_OTGFS_DIEPCTL_STALL BSP_BIT32(21) // Stall handshake +#define STM32F4_OTGFS_DIEPCTL_EPTYP(val) BSP_FLD32(val, 18, 19) // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt +#define STM32F4_OTGFS_DIEPCTL_EPTYP_GET(reg) BSP_FLD32GET(reg, 18, 19) +#define STM32F4_OTGFS_DIEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) +#define EPTYPE_CTRL 0 +#define EPTYPE_ISOC 1 +#define EPTYPE_BULK 2 +#define EPTYPE_INTR 3 +#define STM32F4_OTGFS_DIEPCTL_NAKSTS BSP_BIT32(17) // NAK status +#define STM32F4_OTGFS_DIEPCTL_EONUM_DPID BSP_BIT32(16) // Data PID / Even/odd frame +#define STM32F4_OTGFS_DIEPCTL_USBAEP BSP_BIT32(15) // USB active endpoint +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ(val) BSP_FLD32(val, 0, 1) // Maximum packet size (bytes) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define EP0_MPSIZ_8 3 +#define EP0_MPSIZ_16 2 +#define EP0_MPSIZ_32 1 +#define EP0_MPSIZ_64 0 +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_8 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_8) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_16 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_16) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_32 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_32) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_64 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_64) +#define STM32F4_OTGFS_DIEPCTL_MPSIZ(val) BSP_FLD32(val, 0, 10) // Maximum packet size (bytes) +#define STM32F4_OTGFS_DIEPCTL_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 10) +#define STM32F4_OTGFS_DIEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10) + + uint32_t reserved_04; + + uint32_t diepint; // 0x908 +#define STM32F4_OTGFS_DIEPINT_TXFE BSP_BIT32(7) // Transmit FIFO empty +#define STM32F4_OTGFS_DIEPINT_INEPNE BSP_BIT32(6) // IN endpoint NAK effective +#define STM32F4_OTGFS_DIEPINT_ITTXFE BSP_BIT32(4) // IN token received, TxFIFO empty +#define STM32F4_OTGFS_DIEPINT_TOC BSP_BIT32(3) // Timeout condition +#define STM32F4_OTGFS_DIEPINT_EPDISD BSP_BIT32(1) // Endpoint disabled +#define STM32F4_OTGFS_DIEPINT_XFRC BSP_BIT32(0) // Transfer complete + + uint32_t reserved_0C; + + uint32_t dieptsiz; // 0x910 +#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT(val) BSP_FLD32(val, 19, 20) // EP0 packet count +#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 20) +#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 20) +#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ(val) BSP_FLD32(val, 0, 6) // EP0 transfer size +#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 6) +#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) +#define STM32F4_OTGFS_DIEPTSIZ_MCNT(val) BSP_FLD32(val, 29, 30) // Multi count +#define STM32F4_OTGFS_DIEPTSIZ_MCNT_GET(reg) BSP_FLD32GET(reg, 29, 30) +#define STM32F4_OTGFS_DIEPTSIZ_MCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) +#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT(val) BSP_FLD32(val, 19, 28) // Packet count +#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 28) +#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28) +#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ(val) BSP_FLD32(val, 0, 18) // Transfer size +#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 18) +#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18) + + uint32_t reserved_14; + + uint32_t dtxfsts; // 0x918 +#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV(val) BSP_FLD32(val, 0, 15) // IN endpoint TxFIFO space available +#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_GET(reg) BSP_FLD32(reg, 0, 15) +#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t reserved_1C; + +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_inepregs_s stm32f4_otgfs_inepregs; + +struct stm32f4_otgfs_outepregs_s { + uint32_t doepctl; // 0xBx0: Endpoint control register +#define STM32F4_OTGFS_DOEPCTL_EPENA BSP_BIT32(31) // Endpoint enable +#define STM32F4_OTGFS_DOEPCTL_EPDIS BSP_BIT32(30) // Endpoint disable +#define STM32F4_OTGFS_DOEPCTL_SD1PID BSP_BIT32(29) // Set DATA1 PID / Set odd frame +#define STM32F4_OTGFS_DOEPCTL_SD0PID BSP_BIT32(28) // Set DATA0 PID / Set even frame +#define STM32F4_OTGFS_DOEPCTL_SNAK BSP_BIT32(27) // Set NAK +#define STM32F4_OTGFS_DOEPCTL_CNAK BSP_BIT32(26) // Clear NAK +#define STM32F4_OTGFS_DOEPCTL_STALL BSP_BIT32(21) // Stall handshake +#define STM32F4_OTGFS_DOEPCTL_SNPM BSP_BIT32(20) // Snoop mode +#define STM32F4_OTGFS_DOEPCTL_EPTYP(val) BSP_FLD32(val, 18, 19) // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt +#define STM32F4_OTGFS_DOEPCTL_EPTYP_GET(reg) BSP_FLD32GET(reg, 18, 19) +#define STM32F4_OTGFS_DOEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) +#define STM32F4_OTGFS_DOEPCTL_NAKSTS BSP_BIT32(17) // NAK status +#define STM32F4_OTGFS_DOEPCTL_EONUM_DPID BSP_BIT32(16) // Data PID / Even/odd frame +#define STM32F4_OTGFS_DOEPCTL_USBAEP BSP_BIT32(15) // USB active endpoint +#define STM32F4_OTGFS_DOEPCTL_MPSIZ(val) BSP_FLD32(val, 0, 10) // Maximum packet size (bytes) +#define STM32F4_OTGFS_DOEPCTL_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 10) +#define STM32F4_OTGFS_DOEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10) + + uint32_t resv04; + + uint32_t doepint; // 0xBx8: Endpoint interrupt register +#define STM32F4_OTGFS_DOEPINT_B2BSTUP BSP_BIT32(6) // Back-to-back SETUP packets received +#define STM32F4_OTGFS_DOEPINT_OTEPDIS BSP_BIT32(4) // OUT token received when endpoint disabled +#define STM32F4_OTGFS_DOEPINT_STUP BSP_BIT32(3) // SETUP phase done +#define STM32F4_OTGFS_DOEPINT_EPDISD BSP_BIT32(1) // Endpoint disabled interrupt +#define STM32F4_OTGFS_DOEPINT_XFRC BSP_BIT32(0) // Transfer complete + + uint32_t doeptsiz; // 0xBy0 +#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT(val) BSP_FLD32(val, 29, 30) // EP0 SETUP packet count +#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_GET(reg) BSP_FLD32GET(reg, 29, 30) +#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) +#define STM32F4_OTGFS_DOEPTSIZ_EP0_PKTCNT BSP_BIT32(19) // EP0 packet count +#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ(val) BSP_FLD32(val, 0, 6) // EP0 transfer size +#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 6) +#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) +#define STM32F4_OTGFS_DOEPTSIZ_RXDPID(val) BSP_FLD32(val, 29, 30) // Received data PID +#define STM32F4_OTGFS_DOEPTSIZ_RXDPID_GET(reg) BSP_FLD32GET(reg, 29, 30) +#define STM32F4_OTGFS_DOEPTSIZ_RXDPID_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) +#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT(val) BSP_FLD32(val, 19, 28) // Packet count +#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 28) +#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28) +#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ(val) BSP_FLD32(val, 0, 18) // Transfer size +#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 18) +#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18) + + uint32_t resv14[3]; +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_outepregs_s stm32f4_otgfs_outepregs; + +struct stm32f4_otgfs_pwrctlregs_s { + uint32_t pcgcctl; // 0xE00: Power and clock gating control register +#define STM32F4_OTGFS_PCGCCTL_PHYSUSP BSP_BIT32(4) // PHY suspend +#define STM32F4_OTGFS_PCGCCTL_GATEHCLK BSP_BIT32(1) // Gate HCLK +#define STM32F4_OTGFS_PCGCCTL_STPPCLK BSP_BIT32(0) // Stop PHY clk +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_pwrctlregs_s stm32f4_otgfs_pwrctlregs; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h new file mode 100755 index 0000000000..85af10738f --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H + +#include + +struct stm32f4_pwr_s { + + uint32_t cr; // Control register +#define STM32F4_PWR_CR_VOS BSP_BIT32(14) // Regulator scaling output selection +#define STM32F4_PWR_CR_FPDS BSP_BIT32(9) // Flash power-down in stop mode +#define STM32F4_PWR_CR_DBP BSP_BIT32(8) // Disable backup domain write protection +#define STM32F4_PWR_CR_PLS BSP_FLD32(val, 5, 7) // PVD level selection +#define STM32F4_PWR_CR_PLS_GET(reg) BSP_FLD32GET(reg, 5, 7) +#define STM32F4_PWR_CR_PLS_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) +#define STM32F4_PWR_CR_PVDE BSP_BIT32(4) // Power voltage detector enable +#define STM32F4_PWR_CR_CSBF BSP_BIT32(3) // Clear standby flag +#define STM32F4_PWR_CR_CWUF BSP_BIT32(2) // Clear wakeup flag +#define STM32F4_PWR_CR_PDDS BSP_BIT32(1) // Power-down deepsleep +#define STM32F4_PWR_CR_LPDS BSP_BIT32(0) // Low-power deepsleep + + uint32_t csr; // Control / status register +#define STM32F4_PWR_CSR_VOSRDY BSP_BIT32(14) // Regulator voltage scaling output selection ready bit +#define STM32F4_PWR_CSR_BRE BSP_BIT32(9) // Backup domain regulator enable +#define STM32F4_PWR_CSR_EWUP BSP_BIT32(8) // Enable WKUP pin +#define STM32F4_PWR_CSR_BRR BSP_BIT32(3) // Backup regulator ready +#define STM32F4_PWR_CSR_PVDO BSP_BIT32(2) // PVD output +#define STM32F4_PWR_CSR_SBF BSP_BIT32(1) // Standby flag +#define STM32F4_PWR_CSR_WUF BSP_BIT32(0) // Wakeup flag + +} __attribute__ ((packed)); +typedef struct stm32f4_pwr_s stm32f4_pwr; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h new file mode 100755 index 0000000000..5c004328d7 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h @@ -0,0 +1,289 @@ +/** + * @file + * @ingroup stm32f4xxxx_rcc + * @brief STM32F4XXXX RCC support. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H + +#include + +/** + * @defgroup stm32f4xxxx_rcc STM32F4XXXX RCC Support + * @ingroup stm32f4_rcc + * @brief STM32F4XXXX RCC Support + * @{ + */ + +typedef struct { + uint32_t cr; +#define STM32F4_RCC_CR_PLLI2SRDY BSP_BIT32(27) // PLLI2S clock ready flag +#define STM32F4_RCC_CR_PLLI2SON BSP_BIT32(26) // PLLI2S enable +#define STM32F4_RCC_CR_PLLRDY BSP_BIT32(25) // Main PLL clock ready flag +#define STM32F4_RCC_CR_PLLON BSP_BIT32(24) // Main PLL enable +#define STM32F4_RCC_CR_CSSON BSP_BIT32(19) // Clock security system enable +#define STM32F4_RCC_CR_HSEBYP BSP_BIT32(18) // HSE clock bypass +#define STM32F4_RCC_CR_HSERDY BSP_BIT32(17) // HSE clock ready flag +#define STM32F4_RCC_CR_HSEON BSP_BIT32(16) // HSE clock enable +#define STM32F4_RCC_CR_HSIRDY BSP_BIT32(1) // HSI clock ready flag +#define STM32F4_RCC_CR_HSION BSP_BIT32(0) // HSI clock enable + + uint32_t pllcfgr; +#define STM32F4_RCC_PLLCFGR_PLLQ(val) BSP_FLD32(val, 24, 27) +#define STM32F4_RCC_PLLCFGR_PLLQ_GET(reg) BSP_FLD32GET(reg, 24, 27) +#define STM32F4_RCC_PLLCFGR_PLLQ_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27) +#define STM32F4_RCC_PLLCFGR_SRC BSP_BIT32(22) // PLL entry clock source +#define STM32F4_RCC_PLLCFGR_SRC_HSE STM32F4_RCC_PLLCFGR_SRC +#define STM32F4_RCC_PLLCFGR_SRC_HSI 0 +#define STM32F4_RCC_PLLCFGR_PLLP(val) BSP_FLD32(val, 16, 17) +#define STM32F4_RCC_PLLCFGR_PLLP_GET(reg) BSP_FLD32GET(reg, 16, 17) +#define STM32F4_RCC_PLLCFGR_PLLP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) +#define STM32F4_RCC_PLLCFGR_PLLP_2 STM32F4_RCC_PLLCFGR_PLLP(0) +#define STM32F4_RCC_PLLCFGR_PLLP_4 STM32F4_RCC_PLLCFGR_PLLP(1) +#define STM32F4_RCC_PLLCFGR_PLLP_6 STM32F4_RCC_PLLCFGR_PLLP(2) +#define STM32F4_RCC_PLLCFGR_PLLP_8 STM32F4_RCC_PLLCFGR_PLLP(3) +#define STM32F4_RCC_PLLCFGR_PLLN(val) BSP_FLD32(val, 6, 14) +#define STM32F4_RCC_PLLCFGR_PLLN_GET(reg) BSP_FLD32GET(reg, 6, 14) +#define STM32F4_RCC_PLLCFGR_PLLN_SET(reg, val) BSP_FLD32SET(reg, val, 6, 14) +#define STM32F4_RCC_PLLCFGR_PLLM(val) BSP_FLD32(val, 0, 5) +#define STM32F4_RCC_PLLCFGR_PLLM_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define STM32F4_RCC_PLLCFGR_PLLM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + + uint32_t cfgr; +#define STM32F4_RCC_CFGR_MCO2(val) BSP_FLD32(val, 30, 31) // Microcontroller clock output 2 +#define STM32F4_RCC_CFGR_MCO2_GET(reg) BSP_FLD32GET(reg, 30, 31) +#define STM32F4_RCC_CFGR_MCO2_SET(reg, val) BSP_FLD32SET(reg, val, 30, 31) +#define STM32F4_RCC_CFGR_MCO2_SYSCLK STM32F4_RCC_CFGR_MCO2(0) +#define STM32F4_RCC_CFGR_MCO2_PLLI2S STM32F4_RCC_CFGR_MCO2(1) +#define STM32F4_RCC_CFGR_MCO2_HSE STM32F4_RCC_CFGR_MCO2(2) +#define STM32F4_RCC_CFGR_MCO2_PLL STM32F4_RCC_CFGR_MCO2(3) +#define STM32F4_RCC_CFGR_MCO2_PRE(val) BSP_FLD32(val, 27, 29) // MCO2 prescalar +#define STM32F4_RCC_CFGR_MCO2_PRE_GET(reg) BSP_FLD32GET(reg, 27, 29) +#define STM32F4_RCC_CFGR_MCO2_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29) +#define STM32F4_RCC_CFGR_MCO2_DIV1 STM32F4_RCC_CFGR_MCO2_PRE(0) +#define STM32F4_RCC_CFGR_MCO2_DIV2 STM32F4_RCC_CFGR_MCO2_PRE(4) +#define STM32F4_RCC_CFGR_MCO2_DIV3 STM32F4_RCC_CFGR_MCO2_PRE(5) +#define STM32F4_RCC_CFGR_MCO2_DIV4 STM32F4_RCC_CFGR_MCO2_PRE(6) +#define STM32F4_RCC_CFGR_MCO2_DIV5 STM32F4_RCC_CFGR_MCO2_PRE(7) +#define STM32F4_RCC_CFGR_MCO1_PRE(val) BSP_FLD32(val, 24, 26) // MCO1 prescalar +#define STM32F4_RCC_CFGR_MCO1_PRE_GET(reg) BSP_FLD32GET(reg, 24, 26) +#define STM32F4_RCC_CFGR_MCO1_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) +#define STM32F4_RCC_CFGR_MCO1_DIV1 STM32F4_RCC_CFGR_MCO1_PRE(0) +#define STM32F4_RCC_CFGR_MCO1_DIV2 STM32F4_RCC_CFGR_MCO1_PRE(4) +#define STM32F4_RCC_CFGR_MCO1_DIV3 STM32F4_RCC_CFGR_MCO1_PRE(5) +#define STM32F4_RCC_CFGR_MCO1_DIV4 STM32F4_RCC_CFGR_MCO1_PRE(6) +#define STM32F4_RCC_CFGR_MCO1_DIV5 STM32F4_RCC_CFGR_MCO1_PRE(7) +#define STM32F4_RCC_CFGR_I2SSCR BSP_BIT32(23) // I2S clock selection +#define STM32F4_RCC_CFGR_MCO1(val) BSP_FLD32(val, 21, 22) // Microcontroller clock output 1 +#define STM32F4_RCC_CFGR_MCO1_GET(reg) BSP_FLD32GET(reg, 21, 22) +#define STM32F4_RCC_CFGR_MCO1_SET(reg, val) BSP_FLD32SET(reg, val, 21, 22) +#define STM32F4_RCC_CFGR_MCO1_HSI STM32F4_RCC_CFGR_MCO1(0) +#define STM32F4_RCC_CFGR_MCO1_LSE STM32F4_RCC_CFGR_MCO1(1) +#define STM32F4_RCC_CFGR_MCO1_HSE STM32F4_RCC_CFGR_MCO1(2) +#define STM32F4_RCC_CFGR_MCO1_PLL STM32F4_RCC_CFGR_MCO1(3) +#define STM32F4_RCC_CFGR_RTCPRE(val) BSP_FLD32(val, 16, 20) // HSE division factor for RTC clock +#define STM32F4_RCC_CFGR_RTCPRE_GET(reg) BSP_FLD32GET(reg, 16, 20) +#define STM32F4_RCC_CFGR_RTCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20) +#define STM32F4_RCC_CFGR_PPRE2(val) BSP_FLD32(val, 13, 15) // APB high-speed prescalar (APB2) +#define STM32F4_RCC_CFGR_PPRE2_GET(reg) BSP_FLD32GET(reg, 13, 15) +#define STM32F4_RCC_CFGR_PPRE2_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15) +#define STM32F4_RCC_CFGR_PPRE2_DIV1 STM32F4_RCC_CFGR_PPRE2(0) +#define STM32F4_RCC_CFGR_PPRE2_DIV2 STM32F4_RCC_CFGR_PPRE2(4) +#define STM32F4_RCC_CFGR_PPRE2_DIV4 STM32F4_RCC_CFGR_PPRE2(5) +#define STM32F4_RCC_CFGR_PPRE2_DIV8 STM32F4_RCC_CFGR_PPRE2(6) +#define STM32F4_RCC_CFGR_PPRE2_DIV16 STM32F4_RCC_CFGR_PPRE2(7) +#define STM32F4_RCC_CFGR_PPRE1(val) BSP_FLD32(val, 10, 12) // APB low-speed prescalar (APB1) +#define STM32F4_RCC_CFGR_PPRE1_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define STM32F4_RCC_CFGR_PPRE1_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define STM32F4_RCC_CFGR_PPRE1_DIV1 STM32F4_RCC_CFGR_PPRE1(0) +#define STM32F4_RCC_CFGR_PPRE1_DIV2 STM32F4_RCC_CFGR_PPRE1(4) +#define STM32F4_RCC_CFGR_PPRE1_DIV4 STM32F4_RCC_CFGR_PPRE1(5) +#define STM32F4_RCC_CFGR_PPRE1_DIV8 STM32F4_RCC_CFGR_PPRE1(6) +#define STM32F4_RCC_CFGR_PPRE1_DIV16 STM32F4_RCC_CFGR_PPRE1(7) +#define STM32F4_RCC_CFGR_HPRE(val) BSP_FLD32(val, 4, 15) // AHB prescalar +#define STM32F4_RCC_CFGR_HPRE_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_RCC_CFGR_HPRE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_RCC_CFGR_HPRE_DIV1 STM32F4_RCC_CFGR_HPRE(0) +#define STM32F4_RCC_CFGR_HPRE_DIV2 STM32F4_RCC_CFGR_HPRE(8) +#define STM32F4_RCC_CFGR_HPRE_DIV4 STM32F4_RCC_CFGR_HPRE(9) +#define STM32F4_RCC_CFGR_HPRE_DIV8 STM32F4_RCC_CFGR_HPRE(10) +#define STM32F4_RCC_CFGR_HPRE_DIV16 STM32F4_RCC_CFGR_HPRE(11) +#define STM32F4_RCC_CFGR_HPRE_DIV64 STM32F4_RCC_CFGR_HPRE(12) +#define STM32F4_RCC_CFGR_HPRE_DIV128 STM32F4_RCC_CFGR_HPRE(13) +#define STM32F4_RCC_CFGR_HPRE_DIV256 STM32F4_RCC_CFGR_HPRE(14) +#define STM32F4_RCC_CFGR_HPRE_DIV512 STM32F4_RCC_CFGR_HPRE(15) +#define STM32F4_RCC_CFGR_SWS(val) BSP_FLD32(val, 2, 3) // System clock switch status +#define STM32F4_RCC_CFGR_SWS_GET(reg) BSP_FLD32GET(reg, 2, 3) +#define STM32F4_RCC_CFGR_SWS_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3) +#define STM32F4_RCC_CFGR_SWS_HSI STM32F4_RCC_CFGR_SWS(0) +#define STM32F4_RCC_CFGR_SWS_HSE STM32F4_RCC_CFGR_SWS(1) +#define STM32F4_RCC_CFGR_SWS_PLL STM32F4_RCC_CFGR_SWS(2) +#define STM32F4_RCC_CFGR_SW(val) BSP_FLD32(val, 0, 1) // System clock switch +#define STM32F4_RCC_CFGR_SW_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define STM32F4_RCC_CFGR_SW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define STM32F4_RCC_CFGR_SW_HSI STM32F4_RCC_CFGR_SW(0) +#define STM32F4_RCC_CFGR_SW_HSE STM32F4_RCC_CFGR_SW(1) +#define STM32F4_RCC_CFGR_SW_PLL STM32F4_RCC_CFGR_SW(2) + + uint32_t cir; + + uint32_t ahbrstr [3]; + + uint32_t reserved_1c; + + uint32_t apbrstr [2]; + + uint32_t reserved_28 [2]; + + uint32_t ahbenr [3]; + + uint32_t reserved_3c; + + uint32_t apbenr [2]; + + uint32_t reserved_48 [2]; + + uint32_t ahblpenr [3]; + + uint32_t reserved_5c; + + uint32_t apblpenr [2]; + + uint32_t reserved_68 [2]; + + uint32_t bdcr; + + uint32_t csr; + + uint32_t reserved_78 [2]; + + uint32_t sscgr; + + uint32_t plli2scfgr; + +} stm32f4_rcc; + +/** @} */ + +#define RCC_CR_HSION BSP_BIT32( 0 ) +#define RCC_CR_HSIRDY BSP_BIT32( 1 ) +#define RCC_CR_HSITRIM( val ) BSP_FLD32( val, 3, 7 ) +#define RCC_CR_HSITRIM_MSK BSP_MSK32( 3, 7 ) +#define RCC_CR_HSICAL( val ) BSP_FLD32( val, 8, 15 ) +#define RCC_CR_HSICAL_MSK BSP_MSK32( 8, 15 ) +#define RCC_CR_HSEON BSP_BIT32( 16 ) +#define RCC_CR_HSERDY BSP_BIT32( 17 ) +#define RCC_CR_HSEBYP BSP_BIT32( 18 ) +#define RCC_CR_CSSON BSP_BIT32( 19 ) +#define RCC_CR_PLLON BSP_BIT32( 24 ) +#define RCC_CR_PLLRDY BSP_BIT32( 25 ) +#define RCC_CR_PLLI2SON BSP_BIT32( 26 ) +#define RCC_CR_PLLI2SRDY BSP_BIT32( 27 ) + +#define RCC_PLLCFGR_PLLM( val ) BSP_FLD32( val, 0, 5 ) +#define RCC_PLLCFGR_PLLM_MSK BSP_MSK32( 0, 5 ) +#define RCC_PLLCFGR_PLLN( val ) BSP_FLD32( val, 6, 14 ) +#define RCC_PLLCFGR_PLLN_MSK BSP_MSK32( 6, 14 ) + +#define RCC_PLLCFGR_PLLP 16 +#define RCC_PLLCFGR_PLLP_MSK BSP_MSK32( 16, 17 ) +#define RCC_PLLCFGR_PLLP_BY_2 0 +#define RCC_PLLCFGR_PLLP_BY_4 BSP_FLD32( 1, 16, 17 ) +#define RCC_PLLCFGR_PLLP_BY_6 BSP_FLD32( 2, 16, 17 ) +#define RCC_PLLCFGR_PLLP_BY_8 BSP_FLD32( 3, 16, 17 ) + +#define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32( 22 ) +#define RCC_PLLCFGR_PLLSRC_HSI 0 + +#define RCC_PLLCFGR_PLLQ( val ) BSP_FLD32( val, 24, 27 ) +#define RCC_PLLCFGR_PLLQ_MSK BSP_MSK32( 24, 27 ) + +#define RCC_CFGR_SW 0 +#define RCC_CFGR_SW_MSK BSP_MSK32( 0, 1 ) +#define RCC_CFGR_SW_HSI 0 +#define RCC_CFGR_SW_HSE 1 +#define RCC_CFGR_SW_PLL 2 + +#define RCC_CFGR_SWS 2 +#define RCC_CFGR_SWS_MSK BSP_MSK32( 2, 3 ) +#define RCC_CFGR_SWS_HSI 0 +#define RCC_CFGR_SWS_HSE BSP_FLD32( 1, 2, 3 ) +#define RCC_CFGR_SWS_PLL BSP_FLD32( 2, 2, 3 ) + +#define RCC_CFGR_HPRE 4 +#define RCC_CFGR_HPRE_BY_1 0 +#define RCC_CFGR_HPRE_BY_2 BSP_FLD32( 8, 4, 7 ) +#define RCC_CFGR_HPRE_BY_4 BSP_FLD32( 9, 4, 7 ) +#define RCC_CFGR_HPRE_BY_8 BSP_FLD32( 10, 4, 7 ) +#define RCC_CFGR_HPRE_BY_16 BSP_FLD32( 11, 4, 7 ) +#define RCC_CFGR_HPRE_BY_64 BSP_FLD32( 12, 4, 7 ) +#define RCC_CFGR_HPRE_BY_128 BSP_FLD32( 13, 4, 7 ) +#define RCC_CFGR_HPRE_BY_256 BSP_FLD32( 14, 4, 7 ) +#define RCC_CFGR_HPRE_BY_512 BSP_FLD32( 15, 4, 7 ) + +#define RCC_CFGR_PPRE1 10 +#define RCC_CFGR_PPRE1_BY_1 0 +#define RCC_CFGR_PPRE1_BY_2 BSP_FLD32( 4, 10, 12 ) +#define RCC_CFGR_PPRE1_BY_4 BSP_FLD32( 5, 10, 12 ) +#define RCC_CFGR_PPRE1_BY_8 BSP_FLD32( 6, 10, 12 ) +#define RCC_CFGR_PPRE1_BY_16 BSP_FLD32( 7, 10, 12 ) + +#define RCC_CFGR_PPRE2 13 +#define RCC_CFGR_PPRE2 BSP_MSK32( 13, 15 ) +#define RCC_CFGR_PPRE2_BY_1 0 +#define RCC_CFGR_PPRE2_BY_2 BSP_FLD32( 4, 13, 15 ) +#define RCC_CFGR_PPRE2_BY_4 BSP_FLD32( 5, 13, 15 ) +#define RCC_CFGR_PPRE2_BY_8 BSP_FLD32( 6, 13, 15 ) +#define RCC_CFGR_PPRE2_BY_16 BSP_FLD32( 7, 13, 15 ) + +#define RCC_CFGR_RTCPRE( val ) BSP_FLD32( val, 16, 20 ) +#define RCC_CFGR_RTCPRE_MSK BSP_MSK32( 16, 20 ) + +#define RCC_CFGR_MCO1 21 +#define RCC_CFGR_MCO1_MSK BSP_MSK32( 21, 22 ) +#define RCC_CFGR_MCO1_HSI 0 +#define RCC_CFGR_MCO1_LSE BSP_FLD32( 1, 21, 22 ) +#define RCC_CFGR_MCO1_HSE BSP_FLD32( 2, 21, 22 ) +#define RCC_CFGR_MCO1_PLL BSP_FLD32( 3, 21, 22 ) + +#define RCC_CFGR_I2SSRC BSP_BIT32( 23 ) + +#define RCC_CFGR_MCO1PRE 24 +#define RCC_CFGR_MCO1PRE_MSK BSP_MSK32( 24, 26 ) +#define RCC_CFGR_MCO1PRE_BY_1 0 +#define RCC_CFGR_MCO1PRE_BY_2 BSP_FLD32( 4, 24, 26 ) +#define RCC_CFGR_MCO1PRE_BY_3 BSP_FLD32( 5, 24, 26 ) +#define RCC_CFGR_MCO1PRE_BY_4 BSP_FLD32( 6, 24, 26 ) +#define RCC_CFGR_MCO1PRE_BY_5 BSP_FLD32( 7, 24, 26 ) + +#define RCC_CFGR_MCO2PRE 27 +#define RCC_CFGR_MCO2PRE_MSK BSP_MSK32( 27, 29 ) +#define RCC_CFGR_MCO2PRE_BY_1 0 +#define RCC_CFGR_MCO2PRE_BY_2 BSP_FLD32( 4, 27, 29 ) +#define RCC_CFGR_MCO2PRE_BY_3 BSP_FLD32( 5, 27, 29 ) +#define RCC_CFGR_MCO2PRE_BY_4 BSP_FLD32( 6, 27, 29 ) +#define RCC_CFGR_MCO2PRE_BY_5 BSP_FLD32( 7, 27, 29 ) + +#define RCC_CFGR_MCO2 30 +#define RCC_CFGR_MCO2_MSK BSP_MSK32( 30, 31 ) +#define RCC_CFGR_MCO2_SYSCLK 0 +#define RCC_CFGR_MCO2_PLLI2S BSP_FLD32( 1, 30, 31 ) +#define RCC_CFGR_MCO2_HSE BSP_FLD32( 2, 30, 31 ) +#define RCC_CFGR_MCO2_PLL BSP_FLD32( 3, 30, 31 ) + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h new file mode 100755 index 0000000000..5249363cef --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H + +#include + +#define EXTI_PORTA 0 +#define EXTI_PORTB 1 +#define EXTI_PORTC 2 +#define EXTI_PORTD 3 +#define EXTI_PORTE 4 +#define EXTI_PORTF 5 +#define EXTI_PORTG 6 +#define EXTI_PORTH 7 +#define EXTI_PORTI 8 + +struct stm32f4_syscfg_s { + uint32_t memrmp; // Memory remap +#define STM32F4_SYSCFG_MEM_MODE(val) BSP_FLD32(val, 0, 1) +#define STM32F4_SYSCFG_MEM_MODE_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define STM32F4_SYSCFG_MEM_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) + uint32_t pmc; // Peripheral mode configuration +#define STM32F4_SYSCFG_RMII_SEL BSP_BIT32(23) + uint32_t exticr[4]; // External interrupt configuration +#define STM32F4_SYSCFG_EXTI0_IDX 0 +#define STM32F4_SYSCFG_EXTI0(val) BSP_FLD32(val, 0, 3) +#define STM32F4_SYSCFG_EXTI0_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_SYSCFG_EXTI0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_SYSCFG_EXTI1_IDX 0 +#define STM32F4_SYSCFG_EXTI1(val) BSP_FLD32(val, 4, 7) +#define STM32F4_SYSCFG_EXTI1_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_SYSCFG_EXTI1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_SYSCFG_EXTI2_IDX 0 +#define STM32F4_SYSCFG_EXTI2(val) BSP_FLD32(val, 8, 11) +#define STM32F4_SYSCFG_EXTI2_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_SYSCFG_EXTI2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define STM32F4_SYSCFG_EXTI3_IDX 0 +#define STM32F4_SYSCFG_EXTI3(val) BSP_FLD32(val, 12, 15) +#define STM32F4_SYSCFG_EXTI3_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define STM32F4_SYSCFG_EXTI3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define STM32F4_SYSCFG_EXTI4_IDX 1 +#define STM32F4_SYSCFG_EXTI4(val) BSP_FLD32(val, 0, 3) +#define STM32F4_SYSCFG_EXTI4_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_SYSCFG_EXTI4_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_SYSCFG_EXTI5_IDX 1 +#define STM32F4_SYSCFG_EXTI5(val) BSP_FLD32(val, 4, 7) +#define STM32F4_SYSCFG_EXTI5_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_SYSCFG_EXTI5_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_SYSCFG_EXTI6_IDX 1 +#define STM32F4_SYSCFG_EXTI6(val) BSP_FLD32(val, 8, 11) +#define STM32F4_SYSCFG_EXTI6_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_SYSCFG_EXTI6_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define STM32F4_SYSCFG_EXTI7_IDX 1 +#define STM32F4_SYSCFG_EXTI7(val) BSP_FLD32(val, 12, 15) +#define STM32F4_SYSCFG_EXTI7_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define STM32F4_SYSCFG_EXTI7_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define STM32F4_SYSCFG_EXTI8_IDX 2 +#define STM32F4_SYSCFG_EXTI8(val) BSP_FLD32(val, 0, 3) +#define STM32F4_SYSCFG_EXTI8_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_SYSCFG_EXTI8_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_SYSCFG_EXTI9_IDX 2 +#define STM32F4_SYSCFG_EXTI9(val) BSP_FLD32(val, 4, 7) +#define STM32F4_SYSCFG_EXTI9_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_SYSCFG_EXTI9_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_SYSCFG_EXTI10_IDX 2 +#define STM32F4_SYSCFG_EXTI10(val) BSP_FLD32(val, 8, 11) +#define STM32F4_SYSCFG_EXTI10_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_SYSCFG_EXTI10_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define STM32F4_SYSCFG_EXTI11_IDX 2 +#define STM32F4_SYSCFG_EXTI11(val) BSP_FLD32(val, 12, 15) +#define STM32F4_SYSCFG_EXTI11_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define STM32F4_SYSCFG_EXTI11_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define STM32F4_SYSCFG_EXTI12_IDX 3 +#define STM32F4_SYSCFG_EXTI12(val) BSP_FLD32(val, 0, 3) +#define STM32F4_SYSCFG_EXTI12_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_SYSCFG_EXTI12_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_SYSCFG_EXTI13_IDX 3 +#define STM32F4_SYSCFG_EXTI13(val) BSP_FLD32(val, 4, 7) +#define STM32F4_SYSCFG_EXTI13_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_SYSCFG_EXTI13_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_SYSCFG_EXTI14_IDX 3 +#define STM32F4_SYSCFG_EXTI14(val) BSP_FLD32(val, 8, 11) +#define STM32F4_SYSCFG_EXTI14_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_SYSCFG_EXTI14_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define STM32F4_SYSCFG_EXTI15_IDX 3 +#define STM32F4_SYSCFG_EXTI15(val) BSP_FLD32(val, 12, 15) +#define STM32F4_SYSCFG_EXTI15_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define STM32F4_SYSCFG_EXTI15_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) + uint32_t cmpcr; // Compensation cell control register +#define STM32F4_SYSCFG_CMPCR_READY BSP_BIT32(8) +#define STM32F4_SYSCFG_CMPCR_PD BSP_BIT32(0) +} __attribute__ ((packed)); +typedef struct stm32f4_syscfg_s stm32f4_syscfg; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_tim.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_tim.h new file mode 100755 index 0000000000..45038945b8 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_tim.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H + +#include + +struct stm32f4_tim_s { + uint16_t cr1; // Control register 1 +#define STM32F4_TIMER_CR1_CKD_DIV 0x0300 +#define STM32F4_TIMER_CR1_CKD_DIV1 0x0000 +#define STM32F4_TIMER_CR1_CKD_DIV2 0x0100 +#define STM32F4_TIMER_CR1_CKD_DIV3 0x0200 +#define STM32F4_TIMER_CR1_ARPE BSP_BIT16(7) +#define STM32F4_TIMER_CR1_CMS 0x0060 +#define STM32F4_TIMER_CR1_CMS_EDGE 0x0000 +#define STM32F4_TIMER_CR1_CMS_CENTER1 0x0020 +#define STM32F4_TIMER_CR1_CMS_CENTER2 0x0040 +#define STM32F4_TIMER_CR1_CMS_CENTER3 0x0060 +#define STM32F4_TIMER_CR1_DIR BSP_BIT16(4) +#define STM32F4_TIMER_CR1_DIR_UP 0x0000 +#define STM32F4_TIMER_CR1_DIR_DOWN 0x0010 +#define STM32F4_TIMER_CR1_DIR_OPM 0x0008 +#define STM32F4_TIMER_CR1_DIR_OPM_CONT 0x0000 +#define STM32F4_TIMER_CR1_DIR_OPM_STOP 0x0008 +#define STM32F4_TIMER_CR1_DIR_URS 0x0004 +#define STM32F4_TIMER_CR1_DIR_UDIS 0x0002 +#define STM32F4_TIMER_CR1_DIR_UDIS_EN 0x0000 +#define STM32F4_TIMER_CR1_DIR_UDIS_DIS 0x0002 +#define STM32F4_TIMER_CR1_CEN 0x0001 + uint16_t reserved_02; + uint16_t cr2; // Control register 2 + uint16_t reserved_06; + uint16_t smcr; // Slave mode control register + uint16_t reserved_0a; + uint16_t dier; // DMA / interrupt enable register +#define STM32F4_TIMER_DIER_TDE BSP_BIT16(14) // Trigger DMA request enable +#define STM32F4_TIMER_DIER_CC4DE BSP_BIT16(12) // Capture/compare 4 DMA request enable +#define STM32F4_TIMER_DIER_CC3DE BSP_BIT16(11) // Capture/compare 3 DMA request enable +#define STM32F4_TIMER_DIER_CC2DE BSP_BIT16(10) // Capture/compare 2 DMA request enable +#define STM32F4_TIMER_DIER_CC1DE BSP_BIT16(9) // Capture/compare 1 DMA request enable +#define STM32F4_TIMER_DIER_UDE BSP_BIT16(8) // Update DMA request enable +#define STM32F4_TIMER_DIER_TIE BSP_BIT16(6) // Trigger interrupt enable +#define STM32F4_TIMER_DIER_CC4IE BSP_BIT16(4) // Capture/compare 4 interrupt request enable +#define STM32F4_TIMER_DIER_CC3IE BSP_BIT16(3) // Capture/compare 3 interrupt request enable +#define STM32F4_TIMER_DIER_CC2IE BSP_BIT16(2) // Capture/compare 2 interrupt request enable +#define STM32F4_TIMER_DIER_CC1IE BSP_BIT16(1) // Capture/compare 1 interrupt request enable +#define STM32F4_TIMER_DIER_UIE BSP_BIT16(0) // Update interrupt request enable + + uint16_t reserved_0e; + uint16_t sr; // Status register +#define STM32F4_TIMER_SR_CC4OF BSP_BIT16(12) // Capture/compare 4 overcapture flag +#define STM32F4_TIMER_SR_CC3OF BSP_BIT16(11) // Capture/compare 3 overcapture flag +#define STM32F4_TIMER_SR_CC2OF BSP_BIT16(10) // Capture/compare 2 overcapture flag +#define STM32F4_TIMER_SR_CC1OF BSP_BIT16(9) // Capture/compare 1 overcapture flag +#define STM32F4_TIMER_SR_TIF BSP_BIT16(6) // Trigger interrupt flag +#define STM32F4_TIMER_SR_CC4IF BSP_BIT16(4) // Capture/compare 4 interrupt flag +#define STM32F4_TIMER_SR_CC3IF BSP_BIT16(3) // Capture/compare 3 interrupt flag +#define STM32F4_TIMER_SR_CC2IF BSP_BIT16(2) // Capture/compare 2 interrupt flag +#define STM32F4_TIMER_SR_CC1IF BSP_BIT16(1) // Capture/compare 1 interrupt flag +#define STM32F4_TIMER_SR_UIF BSP_BIT16(0) // Update interrupt flag + uint16_t reserved_12; + uint16_t egr; // Event generation register +#define STM32F4_TIMER_EGR_TG BSP_BIT16(6) // Trigger event +#define STM32F4_TIMER_EGR_CC4G BSP_BIT16(4) // Capture/compare 4 event +#define STM32F4_TIMER_EGR_CC3G BSP_BIT16(3) // Capture/compare 3 generation) +#define STM32F4_TIMER_EGR_CC2G BSP_BIT16(2) // Capture/compare 2 generation) +#define STM32F4_TIMER_EGR_CC1G BSP_BIT16(1) // Capture/compare 1 generation) +#define STM32F4_TIMER_EGR_UG BSP_BIT16(0) // Update event + uint16_t reserved_16; + uint16_t ccmr1; // Capture / compare mode register 1 +#define STM32F4_TIMER_CCMR1_OC2CE BSP_BIT16(15) // Output compare 2 clear enable +#define STM32F4_TIMER_CCMR1_OC2M(val) BSP_FLD16(val, 12, 14) +#define STM32F4_TIMER_CCMR1_OC2M_GET(reg) BSP_FLD16GET(reg, 12, 14) +#define STM32F4_TIMER_CCMR1_OC2M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14) +#define STM32F4_TIMER_CCMR1_OC2M_FROZEN STM32F4_TIMER_CCMR1_OC2M(0) +#define STM32F4_TIMER_CCMR1_OC2M_ACTIVE STM32F4_TIMER_CCMR1_OC2M(1) +#define STM32F4_TIMER_CCMR1_OC2M_INACTIVE STM32F4_TIMER_CCMR1_OC2M(2) +#define STM32F4_TIMER_CCMR1_OC2M_TOGGLE STM32F4_TIMER_CCMR1_OC2M(3) +#define STM32F4_TIMER_CCMR1_OC2M_FORCE_LOW STM32F4_TIMER_CCMR1_OC2M(4) +#define STM32F4_TIMER_CCMR1_OC2M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC2M(5) +#define STM32F4_TIMER_CCMR1_OC2M_PWM1 STM32F4_TIMER_CCMR1_OC2M(6) +#define STM32F4_TIMER_CCMR1_OC2M_PWM2 STM32F4_TIMER_CCMR1_OC2M(7) +#define STM32F4_TIMER_CCMR1_OC2PE BSP_BIT16(11) // Output compare 2 preload enable +#define STM32F4_TIMER_CCMR1_OC2FE BSP_BIT16(10) // Output compare 2 fast enable +#define STM32F4_TIMER_CCMR1_CC2S(val) BSP_FLD16(val, 8, 9) +#define STM32F4_TIMER_CCMR1_CC2S_GET(reg) BSP_FLD16GET(reg, 8, 9) +#define STM32F4_TIMER_CCMR1_CC2S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9) +#define STM32F4_TIMER_CCMR1_CC2S_OUTPUT STM32F4_TIMER_CCMR1_OC2S(0) +#define STM32F4_TIMER_CCMR1_CC2S_TI2 STM32F4_TIMER_CCMR1_OC2S(1) +#define STM32F4_TIMER_CCMR1_CC2S_TI1 STM32F4_TIMER_CCMR1_OC2S(2) +#define STM32F4_TIMER_CCMR1_CC2S_TRC STM32F4_TIMER_CCMR1_OC2S(3) +#define STM32F4_TIMER_CCMR1_OC1CE BSP_BIT16(7) // Output compare 1 clear enable +#define STM32F4_TIMER_CCMR1_OC1M(val) BSP_FLD16(val, 4, 6) +#define STM32F4_TIMER_CCMR1_OC1M_GET(reg) BSP_FLD16GET(reg, 4, 6) +#define STM32F4_TIMER_CCMR1_OC1M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6) +#define STM32F4_TIMER_CCMR1_OC1M_FROZEN STM32F4_TIMER_CCMR1_OC1M(0) +#define STM32F4_TIMER_CCMR1_OC1M_ACTIVE STM32F4_TIMER_CCMR1_OC1M(1) +#define STM32F4_TIMER_CCMR1_OC1M_INACTIVE STM32F4_TIMER_CCMR1_OC1M(2) +#define STM32F4_TIMER_CCMR1_OC1M_TOGGLE STM32F4_TIMER_CCMR1_OC1M(3) +#define STM32F4_TIMER_CCMR1_OC1M_FORCE_LOW STM32F4_TIMER_CCMR1_OC1M(4) +#define STM32F4_TIMER_CCMR1_OC1M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC1M(5) +#define STM32F4_TIMER_CCMR1_OC1M_PWM1 STM32F4_TIMER_CCMR1_OC1M(6) +#define STM32F4_TIMER_CCMR1_OC1M_PWM2 STM32F4_TIMER_CCMR1_OC1M(7) +#define STM32F4_TIMER_CCMR1_OC1PE BSP_BIT16(3) // Output compare 1 preload enable +#define STM32F4_TIMER_CCMR1_OC1FE BSP_BIT16(2) // Output compare 1 fast enable +#define STM32F4_TIMER_CCMR1_CC1S(val) BSP_FLD16(val, 0, 1) +#define STM32F4_TIMER_CCMR1_CC1S_GET(reg) BSP_FLD16GET(reg, 0, 1) +#define STM32F4_TIMER_CCMR1_CC1S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1) +#define STM32F4_TIMER_CCMR1_CC1S_OUTPUT STM32F4_TIMER_CCMR1_OC1S(0) +#define STM32F4_TIMER_CCMR1_CC1S_TI2 STM32F4_TIMER_CCMR1_OC1S(1) +#define STM32F4_TIMER_CCMR1_CC1S_TI1 STM32F4_TIMER_CCMR1_OC1S(2) +#define STM32F4_TIMER_CCMR1_CC1S_TRC STM32F4_TIMER_CCMR1_OC1S(3) + uint16_t reserved_1a; + uint16_t ccmr2; // Capture / compare mode register 2 +#define STM32F4_TIMER_CCMR2_OC4CE BSP_BIT16(15) // Output compare 4 clear enable +#define STM32F4_TIMER_CCMR2_OC4M(val) BSP_FLD16(val, 12, 14) +#define STM32F4_TIMER_CCMR2_OC4M_GET(reg) BSP_FLD16GET(reg, 12, 14) +#define STM32F4_TIMER_CCMR2_OC4M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14) +#define STM32F4_TIMER_CCMR2_OC4M_FROZEN STM32F4_TIMER_CCMR2_OC4M(0) +#define STM32F4_TIMER_CCMR2_OC4M_ACTIVE STM32F4_TIMER_CCMR2_OC4M(1) +#define STM32F4_TIMER_CCMR2_OC4M_INACTIVE STM32F4_TIMER_CCMR2_OC4M(2) +#define STM32F4_TIMER_CCMR2_OC4M_TOGGLE STM32F4_TIMER_CCMR2_OC4M(3) +#define STM32F4_TIMER_CCMR2_OC4M_FORCE_LOW STM32F4_TIMER_CCMR2_OC4M(4) +#define STM32F4_TIMER_CCMR2_OC4M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC4M(5) +#define STM32F4_TIMER_CCMR2_OC4M_PWM1 STM32F4_TIMER_CCMR2_OC4M(6) +#define STM32F4_TIMER_CCMR2_OC4M_PWM2 STM32F4_TIMER_CCMR2_OC4M(7) +#define STM32F4_TIMER_CCMR2_OC4PE BSP_BIT16(11) // Output compare 4 preload enable +#define STM32F4_TIMER_CCMR2_OC4FE BSP_BIT16(10) // Output compare 4 fast enable +#define STM32F4_TIMER_CCMR2_CC4S(val) BSP_FLD16(val, 8, 9) +#define STM32F4_TIMER_CCMR2_CC4S_GET(reg) BSP_FLD16GET(reg, 8, 9) +#define STM32F4_TIMER_CCMR2_CC4S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9) +#define STM32F4_TIMER_CCMR2_CC4S_OUTPUT STM32F4_TIMER_CCMR2_OC4S(0) +#define STM32F4_TIMER_CCMR2_CC4S_TI2 STM32F4_TIMER_CCMR2_OC4S(1) +#define STM32F4_TIMER_CCMR2_CC4S_TI1 STM32F4_TIMER_CCMR2_OC4S(2) +#define STM32F4_TIMER_CCMR2_CC4S_TRC STM32F4_TIMER_CCMR2_OC4S(3) +#define STM32F4_TIMER_CCMR2_OC3CE BSP_BIT16(7) // Output compare 3 clear enable +#define STM32F4_TIMER_CCMR2_OC3M(val) BSP_FLD16(val, 4, 6) +#define STM32F4_TIMER_CCMR2_OC3M_GET(reg) BSP_FLD16GET(reg, 4, 6) +#define STM32F4_TIMER_CCMR2_OC3M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6) +#define STM32F4_TIMER_CCMR2_OC3M_FROZEN STM32F4_TIMER_CCMR2_OC3M(0) +#define STM32F4_TIMER_CCMR2_OC3M_ACTIVE STM32F4_TIMER_CCMR2_OC3M(1) +#define STM32F4_TIMER_CCMR2_OC3M_INACTIVE STM32F4_TIMER_CCMR2_OC3M(2) +#define STM32F4_TIMER_CCMR2_OC3M_TOGGLE STM32F4_TIMER_CCMR2_OC3M(3) +#define STM32F4_TIMER_CCMR2_OC3M_FORCE_LOW STM32F4_TIMER_CCMR2_OC3M(4) +#define STM32F4_TIMER_CCMR2_OC3M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC3M(5) +#define STM32F4_TIMER_CCMR2_OC3M_PWM1 STM32F4_TIMER_CCMR2_OC3M(6) +#define STM32F4_TIMER_CCMR2_OC3M_PWM2 STM32F4_TIMER_CCMR2_OC3M(7) +#define STM32F4_TIMER_CCMR2_OC3PE BSP_BIT16(3) // Output compare 3 preload enable +#define STM32F4_TIMER_CCMR2_OC3FE BSP_BIT16(2) // Output compare 3 fast enable +#define STM32F4_TIMER_CCMR2_CC3S(val) BSP_FLD16(val, 0, 1) +#define STM32F4_TIMER_CCMR2_CC3S_GET(reg) BSP_FLD16GET(reg, 0, 1) +#define STM32F4_TIMER_CCMR2_CC3S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1) +#define STM32F4_TIMER_CCMR2_CC3S_OUTPUT STM32F4_TIMER_CCMR2_OC3S(0) +#define STM32F4_TIMER_CCMR2_CC3S_TI2 STM32F4_TIMER_CCMR2_OC3S(1) +#define STM32F4_TIMER_CCMR2_CC3S_TI1 STM32F4_TIMER_CCMR2_OC3S(2) +#define STM32F4_TIMER_CCMR2_CC3S_TRC STM32F4_TIMER_CCMR2_OC3S(3) + uint16_t reserved_1e; + uint16_t ccer; // Capture / compare enable register +#define STM32F4_TIMER_CCER_CC4NP BSP_BIT16(15) // Capture / compare 4 output polarity +#define STM32F4_TIMER_CCER_CC4P BSP_BIT16(13) // Capture / compare 4 output polarity +#define STM32F4_TIMER_CCER_CC4E BSP_BIT16(12) // Capture / compare 4 output enable +#define STM32F4_TIMER_CCER_CC3NP BSP_BIT16(11) // Capture / compare 3 output polarity +#define STM32F4_TIMER_CCER_CC3P BSP_BIT16(9) // Capture / compare 3 output polarity +#define STM32F4_TIMER_CCER_CC3E BSP_BIT16(8) // Capture / compare 3 output enable +#define STM32F4_TIMER_CCER_CC2NP BSP_BIT16(7) // Capture / compare 2 output polarity +#define STM32F4_TIMER_CCER_CC2P BSP_BIT16(5) // Capture / compare 2 output polarity +#define STM32F4_TIMER_CCER_CC2E BSP_BIT16(4) // Capture / compare 2 output enable +#define STM32F4_TIMER_CCER_CC1NP BSP_BIT16(3) // Capture / compare 1 output polarity +#define STM32F4_TIMER_CCER_CC1P BSP_BIT16(1) // Capture / compare 1 output polarity +#define STM32F4_TIMER_CCER_CC1E BSP_BIT16(0) // Capture / compare 1 output enable + uint16_t reserved_22; + uint32_t cnt; // Counter register +#define STM32F4_TIMER_DR(val) BSP_FLD32(val, 0, 31) +#define STM32F4_TIMER_DR_GET(reg) BSP_FLD32GET(reg, 0, 31) +#define STM32F4_TIMER_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31) + uint16_t psc; // Prescalar + uint16_t reserved_2a; + uint32_t arr; // Auto-reload register + uint16_t rcr; // Repetition counter register + uint16_t rserved_32; + uint32_t ccr[4];// Capture / compare registers + uint16_t bdtr; // Break and dead-time register + uint16_t reserved_46; + uint16_t dcr; // DMA control register + uint16_t reserved_4a; + uint16_t dmar; // DMA address for full transfer + uint16_t reserved_4e; + uint16_t or; // Option register + uint16_t reserved_52; +} __attribute__ ((packed)); +typedef struct stm32f4_tim_s stm32f4_tim; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H */ diff --git a/bsps/arm/stm32f4/include/bsp/usart.h b/bsps/arm/stm32f4/include/bsp/usart.h new file mode 100644 index 0000000000..bac0f6845a --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/usart.h @@ -0,0 +1,45 @@ +/** + * @file + * @ingroup stm32f4_usart + * @brief USART (universal synchronous/asynchronous receiver/transmitter) support. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_USART_H +#define LIBBSP_ARM_STM32F4_USART_H + +#include + +/** + * @defgroup stm32f4_usart USART Support + * @ingroup arm_stm32f4 + * @brief USART Support + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern const console_fns stm32f4_usart_fns; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_STM32F4_USART_H */ diff --git a/bsps/arm/stm32f4/include/tm27.h b/bsps/arm/stm32f4/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/stm32f4/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/tms570/headers.am b/bsps/arm/tms570/headers.am new file mode 100644 index 0000000000..4dd455e338 --- /dev/null +++ b/bsps/arm/tms570/headers.am @@ -0,0 +1,63 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/tms570/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/system-clocks.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-pinmux.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-pins.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-pom.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-rti.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-sci-driver.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-sci.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-vim.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570_hwinit.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570_selftest.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570_selftest_parity.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570lc4357-pins.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h + +include_bsp_ti_hercdir = $(includedir)/bsp/ti_herc +include_bsp_ti_herc_HEADERS = +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h diff --git a/bsps/arm/tms570/include/bsp.h b/bsps/arm/tms570/include/bsp.h new file mode 100644 index 0000000000..456380627f --- /dev/null +++ b/bsps/arm/tms570/include/bsp.h @@ -0,0 +1,42 @@ +/** + * @file bsp.h + * + * @ingroup tms570 + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_BSP_H +#define LIBBSP_ARM_TMS570_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +#include +#include + +#define BSP_OSCILATOR_CLOCK 8000000 +#define BSP_PLL_OUT_CLOCK 160000000 + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_TMS570_BSP_H */ diff --git a/bsps/arm/tms570/include/bsp/irq.h b/bsps/arm/tms570/include/bsp/irq.h new file mode 100644 index 0000000000..2952582453 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/irq.h @@ -0,0 +1,160 @@ +/** + * @file irq.h + * + * @ingroup tms570 + * + * @brief TMS570 interrupt definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_IRQ_H +#define LIBBSP_ARM_TMS570_IRQ_H + +#ifndef ASM +#include +#include +#include +#endif + +#define BSP_INTERRUPT_VECTOR_MIN 0U +#define TMS570_IRQ_ESM_HIGH 0 +#define TMS570_IRQ_RESERVED 1 +#define TMS570_IRQ_TIMER_0 2 +#define TMS570_IRQ_TIMER_1 3 +#define TMS570_IRQ_TIMER_2 4 +#define TMS570_IRQ_TIMER_3 5 +#define TMS570_IRQ_RTI_OVERFLOW_0 6 +#define TMS570_IRQ_RTI_OVERFLOW_1 7 +#define TMS570_IRQ_RTI_TIMEBASE 8 +#define TMS570_IRQ_GIO_HIGH 9 +#define TMS570_IRQ_HET_HIGH 10 +#define TMS570_IRQ_HET_TU_HIGH 11 +#define TMS570_IRQ_MIBSPI1_HIGH 12 +#define TMS570_IRQ_SCI_LEVEL_0 13 +#define TMS570_IRQ_ADC1_EVENT 14 +#define TMS570_IRQ_ADC1_GROUP_1 15 +#define TMS570_IRQ_CAN1_HIGH 16 +#define TMS570_IRQ_RESERVED 17 +#define TMS570_IRQ_FLEXRAY_HIGH 18 +#define TMS570_IRQ_CRC_1 19 +#define TMS570_IRQ_ESM_LOW 20 +#define TMS570_IRQ_SSI 21 +#define TMS570_IRQ_PMU 22 +#define TMS570_IRQ_GIO_LOW 23 +#define TMS570_IRQ_HET_LOW 24 +#define TMS570_IRQ_HET_TU_LOW 25 +#define TMS570_IRQ_MIBSPI1_LOW 26 +#define TMS570_IRQ_SCI_LEVEL_1 27 +#define TMS570_IRQ_ADC1_GROUP_2 28 +#define TMS570_IRQ_CAN1_LOW 29 +#define TMS570_IRQ_RESERVED +#define TMS570_IRQ_ADC1_MAG 31 +#define TMS570_IRQ_FLEXRAY_LOW 32 +#define TMS570_IRQ_DMA_FTCA 33 +#define TMS570_IRQ_DMA_LFSA 34 +#define TMS570_IRQ_CAN2_HIGH 35 +#define TMS570_IRQ_DMM_HIGH 36 +#define TMS570_IRQ_MIBSPI3_HIGH 37 +#define TMS570_IRQ_MIBSPI3_LOW 38 +#define TMS570_IRQ_DMA_HBCA 39 +#define TMS570_IRQ_DMA_BTCA 40 +#define TMS570_IRQ_DMA_BERA 41 +#define TMS570_IRQ_CAN2_LOW 42 +#define TMS570_IRQ_DMM_LOW 43 +#define TMS570_IRQ_CAN1_IF3 44 +#define TMS570_IRQ_CAN3_HIGH 45 +#define TMS570_IRQ_CAN2_IF3 46 +#define TMS570_IRQ_FPU 47 +#define TMS570_IRQ_FLEXRAY_TU 48 +#define TMS570_IRQ_SPI4_HIGH 49 +#define TMS570_IRQ_ADC2_EVENT 50 +#define TMS570_IRQ_ADC2_GROUP_1 51 +#define TMS570_IRQ_FLEXRAY_T0C 52 +#define TMS570_IRQ_MIBSPIP5_HIGH 53 +#define TMS570_IRQ_SPI4_LOW 54 +#define TMS570_IRQ_CAN3_LOW 55 +#define TMS570_IRQ_MIBSPIP5_LOW 56 +#define TMS570_IRQ_ADC2_GROUP_2 57 +#define TMS570_IRQ_FLEXRAY_TU_ERROR 58 +#define TMS570_IRQ_ADC2_MAG 59 +#define TMS570_IRQ_CAN3_IF3 60 +#define TMS570_IRQ_FSM_DONE 61 +#define TMS570_IRQ_FLEXRAY_T1C 62 +#define TMS570_IRQ_HET2_LEVEL_0 63 +#define TMS570_IRQ_SCI2_LEVEL_0 64 +#define TMS570_IRQ_HET_TU2_LEVEL_0 65 +#define TMS570_IRQ_IC2_INTERRUPT 66 +#define TMS570_IRQ_HET2_LEVEL_1 73 +#define TMS570_IRQ_SCI2_LEVEL_1 74 +#define TMS570_IRQ_HET_TU2_LEVEL_1 75 +#define TMS570_IRQ_EMAC_MISC 76 +#define TMS570_IRQ_EMAC_TX 77 +#define TMS570_IRQ_EMAC_THRESH 78 +#define TMS570_IRQ_EMAC_RX 79 +#define TMS570_IRQ_HWA_INT_REQ_H 80 +#define TMS570_IRQ_HWA_INT_REQ_H 81 +#define TMS570_IRQ_DCC_DONE_INTERRUPT 82 +#define TMS570_IRQ_DCC2_DONE_INTERRUPT 83 +#define TMS570_IRQ_HWAG1_INT_REQ_L 88 +#define TMS570_IRQ_HWAG2_INT_REQ_L 89 +#define BSP_INTERRUPT_VECTOR_MAX 94 + +#define TMS570_IRQ_PRIORITY_VALUE_MIN 0U +#define TMS570_IRQ_PRIORITY_VALUE_MAX 0U + +#define TMS570_IRQ_PRIORITY_COUNT ( TMS570_IRQ_PRIORITY_VALUE_MAX + 1U ) +#define TMS570_IRQ_PRIORITY_HIGHEST TMS570_IRQ_PRIORITY_VALUE_MIN +#define TMS570_IRQ_PRIORITY_LOWEST TMS570_IRQ_PRIORITY_VALUE_MAX + +#ifndef ASM + +/** + * @brief Set priority of the interrupt vector. + * + * This function is here because of compability. It should set + * priority of the interrupt vector. + * @warning It does not set any priority at HW layer. It is nearly imposible to + * @warning set priority of the interrupt on TMS570 in a nice way. + * @param[in] vector vector of isr + * @param[in] priority new priority assigned to the vector + * @return Void + */ +void tms570_irq_set_priority( + rtems_vector_number vector, + unsigned priority +); + +/** + * @brief Gets priority of the interrupt vector. + * + * This function is here because of compability. It returns priority + * of the isr vector last set by tms570_irq_set_priority function. + * + * @warning It does not return any real priority of the HW layer. + * @param[in] vector vector of isr + * @retval 0 vector is invalid. + * @retval priority priority of the interrupt + */ +unsigned tms570_irq_get_priority( rtems_vector_number vector ); + +#endif /* ASM */ + +/** @} */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/bsps/arm/tms570/include/bsp/system-clocks.h b/bsps/arm/tms570/include/bsp/system-clocks.h new file mode 100644 index 0000000000..0e1d1301d4 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/system-clocks.h @@ -0,0 +1,62 @@ +/** + * @file benchmark_timer.c + * + * @ingroup tms570 + * + * @brief System clocks. + */ + +/* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H +#define LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup tms570_clock System Clocks + * + * @ingroup tms570 + * + * @brief System clocks. + * + * @{ + */ + +/** + * @brief Returns current standard timer value in microseconds. + * + * This function uses RTI module free running counter 0 used + * which is used as system tick timebase as well. + */ +static inline unsigned tms570_timer(void) +{ + uint32_t actual_fcr0 = TMS570_RTI.CNT[0].FRCx; + return actual_fcr0; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h new file mode 100644 index 0000000000..1649fbeb4b --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h @@ -0,0 +1,626 @@ +/* The header file is generated by make_header.py from ADC.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_ADC +#define LIBBSP_ARM_TMS570_ADC + +#include + +typedef struct{ + uint32_t BUF0; /*Group 0-2 result buffer 0 register*/ + uint32_t BUF1; /*Group 0-2 result buffer 1 register*/ + uint32_t BUF2; /*Group 0-2 result buffer 2 register*/ + uint32_t BUF3; /*Group 0-2 result buffer 3 register*/ + uint32_t BUF4; /*Group 0-2 result buffer 4 register*/ + uint32_t BUF5; /*Group 0-2 result buffer 5 register*/ + uint32_t BUF6; /*Group 0-2 result buffer 6 register*/ + uint32_t BUF7; /*Group 0-2 result buffer 7 register*/ +} tms570_gxbuf_t; + +typedef struct{ + uint32_t RSTCR; /*ADC Reset Control Register*/ + uint32_t OPMODECR; /*ADC Operating Mode Control Register*/ + uint32_t CLOCKCR; /*ADC Clock Control Register*/ + uint32_t CALCR; /*ADC Calibration Mode Control Register*/ + uint32_t GxMODECR[3]; /*ADC Event Group Operating Mode Control Register*/ + uint32_t EVSRC; /*ADC Trigger Source Select Register*/ + uint32_t G1SRC; /*ADC Group1 Trigger Source Select Register*/ + uint32_t G2SRC; /*ADC Group2 Trigger Source Select Register*/ + uint32_t GxINTENA[3]; /*ADC Event Interrupt Enable Control Register*/ + uint32_t GxINTFLG[3]; /*ADC Event Group Interrupt Flag Register*/ + uint32_t GxINTCR[3]; /*ADC Event Group Threshold Interrupt Control Register*/ + uint32_t EVDMACR; /*ADC Event Group DMA Control Register*/ + uint32_t G1DMACR; /*ADC Group1 DMA Control Register*/ + uint32_t G2DMACR; /*ADC Group2 DMA Control Register*/ + uint32_t BNDCR; /*ADC Results Memory Configuration Register*/ + uint32_t BNDEND; /*ADC Results Memory Size Configuration Register*/ + uint32_t EVSAMP; /*ADC Event Group Sampling Time Configuration Register*/ + uint32_t G1SAMP; /*ADC Group1 Sampling Time Configuration Register()*/ + uint32_t G2SAMP; /*ADC Group2 Sampling Time Configuration Register*/ + uint32_t EVSR; /*ADC Event Group Status Register*/ + uint32_t G1SR; /*ADC Group1 Status Register*/ + uint32_t G2SR; /*ADC Group2 Status Register*/ + uint32_t GxSEL[3]; /*ADC Event Group Channel Select Register*/ + uint32_t CALR; /*ADC Calibration and Error Offset Correction Register*/ + uint32_t SMSTATE; /*ADC State Machine Status Register*/ + uint32_t LASTCONV; /*ADC Channel Last Conversion Value Register*/ + tms570_gxbuf_t GxBUF[3]; /*ADC Event Group Results Emulation FIFO Register*/ + uint32_t EVEMUBUFFER; /*ADC Event Group Results Emulation FIFO Register*/ + uint32_t G1EMUBUFFER; /*ADC Group1 Results Emulation FIFO Register*/ + uint32_t G2EMUBUFFER; /*ADC Group2 Results Emulation FIFO Register*/ + uint32_t EVTDIR; /*ADC ADEVT Pin Direction Control Register*/ + uint32_t EVTOUT; /*ADC ADEVT Pin Output Value Control Register*/ + uint32_t EVTIN; /*ADC ADEVT Pin Input Value Register*/ + uint32_t EVTSET; /*ADC ADEVT Pin Set Register*/ + uint32_t EVTCLR; /*ADC ADEVT Pin Clear Register*/ + uint32_t EVTPDR; /*ADC ADEVT Pin Open Drain Enable Register*/ + uint32_t EVTPDIS; /*ADC ADEVT Pin Pull Control Disable Register*/ + uint32_t EVTPSEL; /*ADC ADEVT Pin Pull Control Select Register*/ + uint32_t EVSAMPDISEN; /*ADC Event Group Sample Cap Discharge Control Register*/ + uint32_t G1SAMPDISEN; /*ADC Group1 Sample Cap Discharge Control Register*/ + uint32_t G2SAMPDISEN; /*ADC Group2 Sample Cap Discharge Control Register*/ + uint32_t MAGINTCR1; /*ADC Magnitude Compare Interrupt Control Register 2*/ + uint32_t MAGINT1MASK; /*ADC Magnitude Compare Mask Register 0*/ + uint32_t MAGINTCR2; /*ADC Magnitude Compare Interrupt Control Register 2*/ + uint32_t MAGINT2MASK; /*ADC Magnitude Compare Mask Register 0*/ + uint32_t MAGINTCR3; /*ADC Magnitude Compare Interrupt Control Register 2*/ + uint32_t MAGINT3MASK; /*ADC Magnitude Compare Mask Register 0*/ + uint8_t reserved1 [24]; + uint32_t MAGTHRINTENASET; /*ADC Magnitude Compare Interrupt Enable Set Register*/ + uint32_t MAGTHRINTENACLR; /*ADC Magnitude Compare Interrupt Enable Clear Register*/ + uint32_t MAGTHRINTFLG; /*ADC Magnitude Compare Interrupt Flag Register*/ + uint32_t MAGTHRINTOFFSET; /*ADC Magnitude Compare Interrupt Offset Register*/ + uint32_t GxFIFORESETCR[3]; /*ADC Event Group FIFO Reset Control Register*/ + uint32_t EVRAMWRADDR; /*ADC Event Group RAM Write Address Register*/ + uint32_t G1RAMWRADDR; /*ADC Group1 RAM Write Address Register*/ + uint32_t G2RAMWRADDR; /*ADC Group2 RAM Write Address Register*/ + uint32_t PARCR; /*ADC Parity Control Register*/ + uint32_t PARADDR; /*ADC Parity Error Address Register*/ + uint32_t PWRUPDLYCTRL; /*ADC Power-Up Delay Control Register*/ +} tms570_adc_t; + + +/*----------------------TMS570_ADC_BUFx----------------------*/ +/* field: G2_EMPTY_10bit_mode - Group2 FIFO Empty. */ +#define TMS570_ADC_BUFx_G2_EMPTY_10bit_mode BSP_BIT32(15) + +/* field: G2_CHID_10bit_mode - Group2 Channel Id. */ +#define TMS570_ADC_BUFx_G2_CHID_10bit_mode(val) BSP_FLD32(val,10, 14) +#define TMS570_ADC_BUFx_G2_CHID_10bit_mode_GET(reg) BSP_FLD32GET(reg,10, 14) +#define TMS570_ADC_BUFx_G2_CHID_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,10, 14) + +/* field: G2_DR_10bit_mode - Group2 Digital Conversion Result. */ +#define TMS570_ADC_BUFx_G2_DR_10bit_mode(val) BSP_FLD32(val,0, 9) +#define TMS570_ADC_BUFx_G2_DR_10bit_mode_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_ADC_BUFx_G2_DR_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + +/* field: G2_EMPTY_12bit_mode - Group2 FIFO Empty. */ +#define TMS570_ADC_BUFx_G2_EMPTY_12bit_mode BSP_BIT32(31) + +/* field: G2_CHID_12bit_mode - Group2 Channel Id. */ +#define TMS570_ADC_BUFx_G2_CHID_12bit_mode(val) BSP_FLD32(val,16, 20) +#define TMS570_ADC_BUFx_G2_CHID_12bit_mode_GET(reg) BSP_FLD32GET(reg,16, 20) +#define TMS570_ADC_BUFx_G2_CHID_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,16, 20) + +/* field: G2_DR_12bit_mode - Group2 Digital Conversion Result. */ +#define TMS570_ADC_BUFx_G2_DR_12bit_mode(val) BSP_FLD32(val,0, 11) +#define TMS570_ADC_BUFx_G2_DR_12bit_mode_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_ADC_BUFx_G2_DR_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*----------------------TMS570_ADC_RSTCR----------------------*/ +/* field: RESET - This bit is used to reset the ADC internal state machines and control/status registers. */ +#define TMS570_ADC_RSTCR_RESET BSP_BIT32(0) + + +/*--------------------TMS570_ADC_OPMODECR--------------------*/ +/* field: 10_12_BIT - This bit controls the resolution of the ADC core. */ +#define TMS570_ADC_OPMODECR_10_12_BIT BSP_BIT32(31) + + +/*---------------------TMS570_ADC_CLOCKCR---------------------*/ +/* field: PS - ADC Clock Prescaler. These bits define the prescaler value for the ADC core clock (ADCLK). */ +#define TMS570_ADC_CLOCKCR_PS(val) BSP_FLD32(val,0, 4) +#define TMS570_ADC_CLOCKCR_PS_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_ADC_CLOCKCR_PS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*----------------------TMS570_ADC_CALCR----------------------*/ +/* field: SELF_TEST - ADC Self Test Enable. */ +#define TMS570_ADC_CALCR_SELF_TEST BSP_BIT32(24) + +/* field: CAL_ST - ADC Calibration Conversion Start. */ +#define TMS570_ADC_CALCR_CAL_ST BSP_BIT32(16) + +/* field: BRIDGE_EN - Bridge Enable. */ +#define TMS570_ADC_CALCR_BRIDGE_EN BSP_BIT32(9) + +/* field: HILO - ADC Self Test mode and Calibration Mode Reference Source Selection. */ +#define TMS570_ADC_CALCR_HILO BSP_BIT32(8) + +/* field: CAL_EN - ADC Calibration Enable. */ +#define TMS570_ADC_CALCR_CAL_EN BSP_BIT32(0) + + +/*--------------------TMS570_ADC_GxMODECR--------------------*/ +/* field: No_Reset_on_ChnSel - No Event Group Results Memory Reset on New Channel Select. */ +#define TMS570_ADC_GxMODECR_No_Reset_on_ChnSel BSP_BIT32(16) + +/* field: EV_DATA_FMT - Event Group Read Data Format. */ +#define TMS570_ADC_GxMODECR_EV_DATA_FMT(val) BSP_FLD32(val,8, 9) +#define TMS570_ADC_GxMODECR_EV_DATA_FMT_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_ADC_GxMODECR_EV_DATA_FMT_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + + +/*----------------------TMS570_ADC_EVSRC----------------------*/ +/* field: EV_EDG_BOTH - rising and falling edge detected on the selected trigger source. */ +#define TMS570_ADC_EVSRC_EV_EDG_BOTH BSP_BIT32(4) + +/* field: EV_EDG_SEL - Event Group Trigger Edge Polarity Select. */ +#define TMS570_ADC_EVSRC_EV_EDG_SEL BSP_BIT32(3) + +/* field: EV_SRC - Event Group Trigger Source. */ +#define TMS570_ADC_EVSRC_EV_SRC(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_EVSRC_EV_SRC_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_EVSRC_EV_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*----------------------TMS570_ADC_G1SRC----------------------*/ +/* field: GI_EDG_BOTH - Group1 Trigger Edge Polarity Select. */ +#define TMS570_ADC_G1SRC_GI_EDG_BOTH BSP_BIT32(4) + +/* field: G1_EDG_SEL - Group1 Trigger Edge Polarity Select. */ +#define TMS570_ADC_G1SRC_G1_EDG_SEL BSP_BIT32(3) + +/* field: G1_SRC - Group1 Trigger Source. */ +#define TMS570_ADC_G1SRC_G1_SRC(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_G1SRC_G1_SRC_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_G1SRC_G1_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*----------------------TMS570_ADC_G2SRC----------------------*/ +/* field: G2_EDG_BOTH - Group2 Trigger Edge Polarity Select. */ +#define TMS570_ADC_G2SRC_G2_EDG_BOTH BSP_BIT32(4) + +/* field: G2_EDG_SEL - Group2 Trigger Edge Polarity Select. */ +#define TMS570_ADC_G2SRC_G2_EDG_SEL BSP_BIT32(3) + +/* field: G2_SRC - Group2 Trigger Source. */ +#define TMS570_ADC_G2SRC_G2_SRC(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_G2SRC_G2_SRC_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_G2SRC_G2_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*--------------------TMS570_ADC_GxINTENA--------------------*/ +/* field: EV_END_INT_EN - Event Group Conversion End Interrupt Enable. Please refer to Section 19.5. */ +#define TMS570_ADC_GxINTENA_EV_END_INT_EN BSP_BIT32(3) + +/* field: EV_OVR_INT_EN - write a new conversion result to the Event Group results memory which is already full. */ +#define TMS570_ADC_GxINTENA_EV_OVR_INT_EN BSP_BIT32(1) + +/* field: EV_THR_INT_EN - Event Group Threshold Interrupt Enable. */ +#define TMS570_ADC_GxINTENA_EV_THR_INT_EN BSP_BIT32(0) + + +/*--------------------TMS570_ADC_GxINTFLG--------------------*/ +/* field: EV_END - Event Group Conversion End. */ +#define TMS570_ADC_GxINTFLG_EV_END BSP_BIT32(3) + +/* field: EV_MEM_EMPTY - Event Group Results Memory Empty. This is a read-only bit; writes have no effect. It is not asource of an interrupt from the ADC module. */ +#define TMS570_ADC_GxINTFLG_EV_MEM_EMPTY BSP_BIT32(2) + +/* field: EV_MEM_OVERRUN - Event Group Memory Overrun. This is a read-only bit; writes have no effect. */ +#define TMS570_ADC_GxINTFLG_EV_MEM_OVERRUN BSP_BIT32(1) + +/* field: EV_THR_INT_FLG - Event Group Threshold Interrupt Flag. */ +#define TMS570_ADC_GxINTFLG_EV_THR_INT_FLG BSP_BIT32(0) + + +/*---------------------TMS570_ADC_GxINTCR---------------------*/ +/* field: Sign_Extension - These bits always read the same as the bit 8 of this register. */ +#define TMS570_ADC_GxINTCR_Sign_Extension(val) BSP_FLD32(val,9, 15) +#define TMS570_ADC_GxINTCR_Sign_Extension_GET(reg) BSP_FLD32GET(reg,9, 15) +#define TMS570_ADC_GxINTCR_Sign_Extension_SET(reg,val) BSP_FLD32SET(reg, val,9, 15) + +/* field: EV_THR - Event Group Threshold Counter. */ +#define TMS570_ADC_GxINTCR_EV_THR(val) BSP_FLD32(val,0, 8) +#define TMS570_ADC_GxINTCR_EV_THR_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_ADC_GxINTCR_EV_THR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*---------------------TMS570_ADC_EVDMACR---------------------*/ +/* field: EV_BLOCKS - Number of Event Group Result buffers to be transferred using DMA if the ADC module is */ +#define TMS570_ADC_EVDMACR_EV_BLOCKS(val) BSP_FLD32(val,16, 24) +#define TMS570_ADC_EVDMACR_EV_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24) +#define TMS570_ADC_EVDMACR_EV_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24) + +/* field: DMA_EV_END - Event Group Conversion End DMA Transfer Enable. */ +#define TMS570_ADC_EVDMACR_DMA_EV_END BSP_BIT32(3) + +/* field: EV_BLK_XFER - Event Group Block DMA Transfer Enable. */ +#define TMS570_ADC_EVDMACR_EV_BLK_XFER BSP_BIT32(2) + +/* field: EV_DMA_EN - Event Group DMA Transfer Enable. */ +#define TMS570_ADC_EVDMACR_EV_DMA_EN BSP_BIT32(0) + + +/*---------------------TMS570_ADC_G1DMACR---------------------*/ +/* field: G1_BLOCKS - Number of Group1 Result buffers to be transferred using DMA if the ADC module is configured */ +#define TMS570_ADC_G1DMACR_G1_BLOCKS(val) BSP_FLD32(val,16, 24) +#define TMS570_ADC_G1DMACR_G1_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24) +#define TMS570_ADC_G1DMACR_G1_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24) + +/* field: DMA_G1_END - Group1 Conversion End DMA Transfer Enable. */ +#define TMS570_ADC_G1DMACR_DMA_G1_END BSP_BIT32(3) + +/* field: G1_BLK_XFER - Group1 Block DMA Transfer Enable. */ +#define TMS570_ADC_G1DMACR_G1_BLK_XFER BSP_BIT32(2) + +/* field: G1_DMA_EN - Group1 DMA Transfer Enable. */ +#define TMS570_ADC_G1DMACR_G1_DMA_EN BSP_BIT32(0) + + +/*---------------------TMS570_ADC_G2DMACR---------------------*/ +/* field: G2_BLOCKS - Number of Group2 Result buffers to be transferred using DMA if the ADC module is configured */ +#define TMS570_ADC_G2DMACR_G2_BLOCKS(val) BSP_FLD32(val,16, 24) +#define TMS570_ADC_G2DMACR_G2_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24) +#define TMS570_ADC_G2DMACR_G2_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24) + +/* field: DMA_G2_END - Group2 Conversion End DMA Transfer Enable. */ +#define TMS570_ADC_G2DMACR_DMA_G2_END BSP_BIT32(3) + +/* field: G2_BLK_XFER - Group2 Block DMA Transfer Enable. */ +#define TMS570_ADC_G2DMACR_G2_BLK_XFER BSP_BIT32(2) + +/* field: G2_DMA_EN - Group2 DMA Transfer Enable. */ +#define TMS570_ADC_G2DMACR_G2_DMA_EN BSP_BIT32(0) + + +/*----------------------TMS570_ADC_BNDCR----------------------*/ +/* field: BNDA - Buffer Boundary A. */ +#define TMS570_ADC_BNDCR_BNDA(val) BSP_FLD32(val,16, 24) +#define TMS570_ADC_BNDCR_BNDA_GET(reg) BSP_FLD32GET(reg,16, 24) +#define TMS570_ADC_BNDCR_BNDA_SET(reg,val) BSP_FLD32SET(reg, val,16, 24) + +/* field: BNDB - Buffer Boundary B. */ +#define TMS570_ADC_BNDCR_BNDB(val) BSP_FLD32(val,0, 8) +#define TMS570_ADC_BNDCR_BNDB_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_ADC_BNDCR_BNDB_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*---------------------TMS570_ADC_BNDEND---------------------*/ +/* field: BUF_INIT_ACTIVE - ADC Results Memory Auto-initialization Status. */ +#define TMS570_ADC_BNDEND_BUF_INIT_ACTIVE BSP_BIT32(16) + +/* field: BNDEND - Buffer Boundary End. */ +#define TMS570_ADC_BNDEND_BNDEND(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_BNDEND_BNDEND_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_BNDEND_BNDEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*---------------------TMS570_ADC_EVSAMP---------------------*/ +/* field: EV_ACQ - Event Group Acquisition Time. */ +#define TMS570_ADC_EVSAMP_EV_ACQ(val) BSP_FLD32(val,0, 11) +#define TMS570_ADC_EVSAMP_EV_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_ADC_EVSAMP_EV_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*---------------------TMS570_ADC_G1SAMP---------------------*/ +/* field: G1_ACQ - Group1 Acquisition Time. These bits define the sampling window (SW) for the Group1 conversions. */ +#define TMS570_ADC_G1SAMP_G1_ACQ(val) BSP_FLD32(val,0, 11) +#define TMS570_ADC_G1SAMP_G1_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_ADC_G1SAMP_G1_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*---------------------TMS570_ADC_G2SAMP---------------------*/ +/* field: G2_ACQ - Group2 Acquisition Time. These bits define the sampling window (SW) for the Group2 conversions. */ +#define TMS570_ADC_G2SAMP_G2_ACQ(val) BSP_FLD32(val,0, 11) +#define TMS570_ADC_G2SAMP_G2_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_ADC_G2SAMP_G2_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*----------------------TMS570_ADC_EVSR----------------------*/ +/* field: EV_MEM_EMPTY - Event Group Results Memory Empty. */ +#define TMS570_ADC_EVSR_EV_MEM_EMPTY BSP_BIT32(3) + +/* field: EV_BUSY - Event Group Conversion Busy. */ +#define TMS570_ADC_EVSR_EV_BUSY BSP_BIT32(2) + +/* field: EV_STOP - Event Group Conversion Stopped. */ +#define TMS570_ADC_EVSR_EV_STOP BSP_BIT32(1) + +/* field: EV_END - Event Group Conversions Ended. */ +#define TMS570_ADC_EVSR_EV_END BSP_BIT32(0) + + +/*----------------------TMS570_ADC_G1SR----------------------*/ +/* field: G1_MEM_EMPTY - Group1 Results Memory Empty. */ +#define TMS570_ADC_G1SR_G1_MEM_EMPTY BSP_BIT32(3) + +/* field: G1_BUSY - Group1 Conversion Busy. */ +#define TMS570_ADC_G1SR_G1_BUSY BSP_BIT32(2) + +/* field: G1_STOP - Group1 Conversion Stopped. */ +#define TMS570_ADC_G1SR_G1_STOP BSP_BIT32(1) + +/* field: G1_END - Group1 Conversions Ended. */ +#define TMS570_ADC_G1SR_G1_END BSP_BIT32(0) + + +/*----------------------TMS570_ADC_G2SR----------------------*/ +/* field: G2_MEM_EMPTY - Group2 Results Memory Empty. */ +#define TMS570_ADC_G2SR_G2_MEM_EMPTY BSP_BIT32(3) + +/* field: G2_BUSY - Group2 Conversion Busy. */ +#define TMS570_ADC_G2SR_G2_BUSY BSP_BIT32(2) + +/* field: G2_STOP - Group2 Conversion Stopped. */ +#define TMS570_ADC_G2SR_G2_STOP BSP_BIT32(1) + +/* field: G2_END - Group2 Conversions Ended. */ +#define TMS570_ADC_G2SR_G2_END BSP_BIT32(0) + + +/*----------------------TMS570_ADC_GxSEL----------------------*/ +/* field: EV_SEL - Event Group channels selected. */ +#define TMS570_ADC_GxSEL_EV_SEL(val) BSP_FLD32(val,0, 15) +#define TMS570_ADC_GxSEL_EV_SEL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_ADC_GxSEL_EV_SEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_ADC_CALR----------------------*/ +/* field: ADCALR - ADC Calibration Result and Offset Error Correction Value. */ +#define TMS570_ADC_CALR_ADCALR(val) BSP_FLD32(val,0, 11) +#define TMS570_ADC_CALR_ADCALR_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_ADC_CALR_ADCALR_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*---------------------TMS570_ADC_SMSTATE---------------------*/ +/* field: LAST_CONV - ADC Input Channel's Last Converted Value. */ +#define TMS570_ADC_SMSTATE_LAST_CONV(val) BSP_FLD32(val,0, 23) +#define TMS570_ADC_SMSTATE_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_ADC_SMSTATE_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*--------------------TMS570_ADC_LASTCONV--------------------*/ +/* field: LAST_CONV - ADC Input Channel's Last Converted Value. */ +#define TMS570_ADC_LASTCONV_LAST_CONV(val) BSP_FLD32(val,0, 23) +#define TMS570_ADC_LASTCONV_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_ADC_LASTCONV_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*----------------------TMS570_ADC_GxBUF----------------------*/ +/* field: ADEVT_DIR - ADEVT Pin Direction. */ +#define TMS570_ADC_GxBUF_ADEVT_DIR BSP_BIT32(0) + + +/*-------------------TMS570_ADC_EVEMUBUFFER-------------------*/ +/* field: ADEVT_DIR - ADEVT Pin Direction. */ +#define TMS570_ADC_EVEMUBUFFER_ADEVT_DIR BSP_BIT32(0) + + +/*-------------------TMS570_ADC_G1EMUBUFFER-------------------*/ +/* field: ADEVT_DIR - ADEVT Pin Direction. */ +#define TMS570_ADC_G1EMUBUFFER_ADEVT_DIR BSP_BIT32(0) + + +/*-------------------TMS570_ADC_G2EMUBUFFER-------------------*/ +/* field: ADEVT_DIR - ADEVT Pin Direction. */ +#define TMS570_ADC_G2EMUBUFFER_ADEVT_DIR BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTDIR---------------------*/ +/* field: ADEVT_DIR - ADEVT Pin Direction. */ +#define TMS570_ADC_EVTDIR_ADEVT_DIR BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTOUT---------------------*/ +/* field: ADEVT_OUT - ADEVT Pin Output Value. */ +#define TMS570_ADC_EVTOUT_ADEVT_OUT BSP_BIT32(0) + + +/*----------------------TMS570_ADC_EVTIN----------------------*/ +/* field: ADEVT_IN - ADEVT Pin Input Value. This is a read-only bit which reflects the logic level on the ADEVT pin. */ +#define TMS570_ADC_EVTIN_ADEVT_IN BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTSET---------------------*/ +/* field: ADEVT_SET - ADEVT Pin Set. This bit drives the output of the ADEVT pin high. */ +#define TMS570_ADC_EVTSET_ADEVT_SET BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTCLR---------------------*/ +/* field: ADEVT_CLR - ADEVT Pin Clear. A read from this bit always returns the current state of the ADEVT pin. */ +#define TMS570_ADC_EVTCLR_ADEVT_CLR BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTPDR---------------------*/ +/* field: ADEVT_PDR - ADEVT Pin Open Drain Enable. */ +#define TMS570_ADC_EVTPDR_ADEVT_PDR BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTPDIS---------------------*/ +/* field: ADEVT_PDIS - ADEVT Pin Pull Control Disable. */ +#define TMS570_ADC_EVTPDIS_ADEVT_PDIS BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTPSEL---------------------*/ +/* field: ADEVT_PSEL - ADEVT Pin Pull Control Select. */ +#define TMS570_ADC_EVTPSEL_ADEVT_PSEL BSP_BIT32(0) + + +/*-------------------TMS570_ADC_EVSAMPDISEN-------------------*/ +/* field: EV_SAMP_DIS_CYC - Event Group sample cap discharge cycles. */ +#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15) +#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: EV_SAMP_DIS_EN - Event Group sample cap discharge enable. */ +#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_EN BSP_BIT32(0) + + +/*-------------------TMS570_ADC_G1SAMPDISEN-------------------*/ +/* field: G1_SAMP_DIS_CYC - Group1 sample cap discharge cycles. */ +#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15) +#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: G1_SAMP_DIS_EN - Group1 sample cap discharge enable. */ +#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_EN BSP_BIT32(0) + + +/*-------------------TMS570_ADC_G2SAMPDISEN-------------------*/ +/* field: G2_SAMP_DIS_CYC - for which the ADC internal sampling capacitor is allowed to discharge before sampling the input */ +#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15) +#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: G2_SAMP_DIS_EN - Group2 sample cap discharge enable. */ +#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_EN BSP_BIT32(0) + + +/*--------------------TMS570_ADC_MAGINTCRx--------------------*/ +/* field: MAG_CHID2 - These bits specify the channel number from 0 to 31 for which the conversion result needs to be */ +#define TMS570_ADC_MAGINTCRx_MAG_CHID2(val) BSP_FLD32(val,26, 30) +#define TMS570_ADC_MAGINTCRx_MAG_CHID2_GET(reg) BSP_FLD32GET(reg,26, 30) +#define TMS570_ADC_MAGINTCRx_MAG_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,26, 30) + +/* field: MAG_THR2 - These bits specify the 10-bit compare value which the ADC will use for the comparison with the */ +#define TMS570_ADC_MAGINTCRx_MAG_THR2(val) BSP_FLD32(val,16, 25) +#define TMS570_ADC_MAGINTCRx_MAG_THR2_GET(reg) BSP_FLD32GET(reg,16, 25) +#define TMS570_ADC_MAGINTCRx_MAG_THR2_SET(reg,val) BSP_FLD32SET(reg, val,16, 25) + +/* field: COMP_CHID2 - These bits specify the channel number from 0 to 31 whose last conversion result is compared */ +#define TMS570_ADC_MAGINTCRx_COMP_CHID2(val) BSP_FLD32(val,8, 12) +#define TMS570_ADC_MAGINTCRx_COMP_CHID2_GET(reg) BSP_FLD32GET(reg,8, 12) +#define TMS570_ADC_MAGINTCRx_COMP_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,8, 12) + +/* field: CHN_THR_COMP2 - Channel OR Threshold comparison. */ +#define TMS570_ADC_MAGINTCRx_CHN_THR_COMP2 BSP_BIT32(1) + +/* field: CMP_GE_LT2 - Greater than or equal to OR Less than comparison operator. */ +#define TMS570_ADC_MAGINTCRx_CMP_GE_LT2 BSP_BIT32(0) + + +/*-------------------TMS570_ADC_MAGINTxMASK-------------------*/ +/* field: MAG_INT0_MASK - These bits specify the mask for the comparison in order to generate the magnitude compare */ +#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK(val) BSP_FLD32(val,0, 9) +#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*-----------------TMS570_ADC_MAGTHRINTENASET-----------------*/ +/* field: MAG_INT_ENA_SET - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */ +#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------TMS570_ADC_MAGTHRINTENACLR-----------------*/ +/* field: MAG_INT_ENA_CLR - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */ +#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*------------------TMS570_ADC_MAGTHRINTFLG------------------*/ +/* field: MAG_INT_FLG - Magnitude Compare Interrupt Flags. */ +#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------TMS570_ADC_MAGTHRINTOFFSET-----------------*/ +/* field: MAG_INT_OFF - Magnitude Compare Interrupt Offset. */ +#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF(val) BSP_FLD32(val,0, 3) +#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_ADC_GxFIFORESETCR------------------*/ +/* field: EV_FIFO_RESET - allows the ADC module to overwrite the contents of the Event Group results memory starting from */ +#define TMS570_ADC_GxFIFORESETCR_EV_FIFO_RESET BSP_BIT32(0) + + +/*-------------------TMS570_ADC_EVRAMWRADDR-------------------*/ +/* field: G1_RAM_ADDR - Group1 results memory write pointer. */ +#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8) +#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*-------------------TMS570_ADC_G1RAMWRADDR-------------------*/ +/* field: G1_RAM_ADDR - Group1 results memory write pointer. */ +#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8) +#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*-------------------TMS570_ADC_G2RAMWRADDR-------------------*/ +/* field: G2_RAM_ADDR - Group2 results memory write pointer. */ +#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR(val) BSP_FLD32(val,0, 8) +#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*----------------------TMS570_ADC_PARCR----------------------*/ +/* field: TEST - This bit maps the parity bits into the ADC results' RAM frame so that the application can access */ +#define TMS570_ADC_PARCR_TEST BSP_BIT32(8) + +/* field: PARITY_ENA - PARITY ENA */ +#define TMS570_ADC_PARCR_PARITY_ENA(val) BSP_FLD32(val,0, 3) +#define TMS570_ADC_PARCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_ADC_PARCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_ADC_PARADDR---------------------*/ +/* field: ERROR_ADDRESS - These bits hold the address of the first parity error generated in the ADC results' RAM. */ +#define TMS570_ADC_PARADDR_ERROR_ADDRESS(val) BSP_FLD32(val,2, 11) +#define TMS570_ADC_PARADDR_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,2, 11) +#define TMS570_ADC_PARADDR_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,2, 11) + + +/*------------------TMS570_ADC_PWRUPDLYCTRL------------------*/ +/* field: PWRUP_DLY - This register defines the number of VCLK cycles that the ADC state machine has to wait after */ +#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY(val) BSP_FLD32(val,0, 9) +#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + + +#endif /* LIBBSP_ARM_TMS570_ADC */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h new file mode 100644 index 0000000000..941ed54753 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h @@ -0,0 +1,72 @@ +/* The header file is generated by make_header.py from CCMSR.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_CCMSR +#define LIBBSP_ARM_TMS570_CCMSR + +#include + +typedef struct{ + uint32_t CCMSR; /*CCM-R4F Status Register*/ + uint32_t CCMKEYR; /*CCM-R4F Key Register*/ +} tms570_ccmsr_t; + + +/*---------------------TMS570_CCMSR_CCMSR---------------------*/ +/* field: CMPE - Compare Error */ +#define TMS570_CCMSR_CCMSR_CMPE BSP_BIT32(16) + +/* field: STC - Self-test Complete */ +#define TMS570_CCMSR_CCMSR_STC BSP_BIT32(8) + +/* field: STET - Self-test Error Type */ +#define TMS570_CCMSR_CCMSR_STET BSP_BIT32(1) + +/* field: STE - Self-test Error */ +#define TMS570_CCMSR_CCMSR_STE BSP_BIT32(0) + + +/*--------------------TMS570_CCMSR_CCMKEYR--------------------*/ +/* field: MKEY - Mode Key */ +#define TMS570_CCMSR_CCMKEYR_MKEY(val) BSP_FLD32(val,0, 3) +#define TMS570_CCMSR_CCMKEYR_MKEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_CCMSR_CCMKEYR_MKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + + +#endif /* LIBBSP_ARM_TMS570_CCMSR */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h new file mode 100644 index 0000000000..f1352f67b6 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h @@ -0,0 +1,379 @@ +/* The header file is generated by make_header.py from CRC.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_CRC +#define LIBBSP_ARM_TMS570_CRC + +#include + +typedef struct{ + uint32_t CTRL0; /*CRC Global Control Register*/ + uint8_t reserved1 [4]; + uint32_t CTRL1; /*CRC Global Control Register 1*/ + uint8_t reserved2 [4]; + uint32_t CTRL2; /*CRC Global Control Register 2*/ + uint8_t reserved3 [4]; + uint32_t INTS; /*CRC Interrupt Enable Set Register*/ + uint8_t reserved4 [4]; + uint32_t INTR; /*CRC Interrupt Enable Reset Register*/ + uint8_t reserved5 [4]; + uint32_t STATUS; /*CRC Interrupt Status Register*/ + uint8_t reserved6 [4]; + uint32_t INT_OFFS_REG; /*CRC Interrupt Offset Register*/ + uint8_t reserved7 [4]; + uint32_t BUSY; /*CRC Busy Register*/ + uint8_t reserved8 [4]; + uint32_t PCOUNT_REG1; /*CRC Channel 1 Pattern Counter Preload Register*/ + uint32_t SCOUNT_REG1; /*CRC Channel 1 Sector Counter Preload Register*/ + uint32_t CURSEC_REG1; /*CRC Channel 1 Current Sector Register*/ + uint32_t WDTOPLD1; /*CRC Channel 1 Watchdog Timeout Preload Register*/ + uint32_t BCTOPLD1; /*CRC Channel 1 Block Complete Timeout Preload Register*/ + uint8_t reserved9 [12]; + uint32_t PSA_SIGREGL1; /*Channel 1 PSA Signature Low Register*/ + uint32_t PSA_SIGREGH1; /*Channel 1 PSA Signature High Register*/ + uint32_t REGL1; /*Channel 1 CRC Value Low Register*/ + uint32_t REGH1; /*Channel 1 CRC Value High Register*/ + uint32_t PSA_SECSIGREGL1; /*Channel 1 PSA Sector Signature Low Register*/ + uint32_t PSA_SECSIGREGH1; /*Channel 1 PSA Sector Signature High Register*/ + uint32_t RAW_DATAREGL1; /*Channel 1 Raw Data Low Register*/ + uint32_t RAW_DATAREGH1; /*Channel 1 Raw Data High Register*/ + uint32_t PCOUNT_REG2; /*CRC Channel 2 Pattern Counter Preload Register*/ + uint32_t SCOUNT_REG2; /*CRC Channel 2 Sector Counter Preload Register*/ + uint32_t CURSEC_REG2; /*CRC Current Sector Register 2*/ + uint32_t WDTOPLD2; /*CRC Channel 2 Watchdog Timeout Preload Register A*/ + uint32_t BCTOPLD2; /*CRC Channel 2 Block Complete Timeout Preload Register B*/ + uint8_t reserved10 [12]; + uint32_t PSA_SIGREGL2; /*Channel 2 PSA Signature Low Register*/ + uint32_t PSA_SIGREGH2; /*Channel 2 PSA Signature High Register*/ + uint32_t REGL2; /*Channel 2 CRC Value Low Register*/ + uint32_t REGH2; /*Channel 2 CRC Value High Register*/ + uint32_t PSA_SECSIGREGL2; /*Channel 2 PSA Sector Signature Low Register*/ + uint32_t PSA_SECSIGREGH2; /*Channel 2 PSA Sector Signature High Register*/ + uint32_t RAW_DATAREGL2; /*Channel 2 Raw Data Low Register*/ + uint32_t RAW_DATAREGH2; /*Channel 2 Raw Data High Register*/ + uint8_t reserved11 [128]; + uint32_t BUS_SEL; /*Data Bus Selection Register*/ +} tms570_crc_t; + + +/*----------------------TMS570_CRC_CTRL0----------------------*/ +/* field: CH2_PSA_SWREST - Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */ +#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_BIT32(8) + +/* field: CH1_PSA_SWREST - Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */ +#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_BIT32(0) + + +/*----------------------TMS570_CRC_CTRL1----------------------*/ +/* field: PWDN - Power Down. */ +#define TMS570_CRC_CTRL1_PWDN BSP_BIT32(0) + + +/*----------------------TMS570_CRC_CTRL2----------------------*/ +/* field: CH2_MODE - Channel 2 Mode Selection */ +#define TMS570_CRC_CTRL2_CH2_MODE(val) BSP_FLD32(val,8, 9) +#define TMS570_CRC_CTRL2_CH2_MODE_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_CRC_CTRL2_CH2_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: CH1_TRACEEN - Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. */ +#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_BIT32(4) + +/* field: CH1_MODE - Channel 1 Mode Selection */ +#define TMS570_CRC_CTRL2_CH1_MODE(val) BSP_FLD32(val,0, 1) +#define TMS570_CRC_CTRL2_CH1_MODE_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_CRC_CTRL2_CH1_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*----------------------TMS570_CRC_INTS----------------------*/ +/* field: CH2_TIMEOUTENS - Channel 2 Timeout Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_BIT32(12) + +/* field: CH2_UNDERENS - Channel 2 Underrun Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH2_UNDERENS BSP_BIT32(11) + +/* field: CH2_OVERENS - Channel 2 Overrun Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH2_OVERENS BSP_BIT32(10) + +/* field: CH2_CRCFAILENS - Channel 2 CRC Fail Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_BIT32(9) + +/* field: CH2_CCITENS - Channel 2 Compression Complete Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH2_CCITENS BSP_BIT32(8) + +/* field: CH1_TIMEOUTENS - Channel 1 Timeout Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_BIT32(4) + +/* field: CH1_UNDERENS - Channel 1 Underrun Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH1_UNDERENS BSP_BIT32(3) + +/* field: CH1_OVERENS - CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH1_OVERENS BSP_BIT32(2) + +/* field: CH1_CRCFAILENS - Channel 1 CRC Fail Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_BIT32(1) + +/* field: CH1_CCITENS - Channel 1 Compression Complete Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH1_CCITENS BSP_BIT32(0) + + +/*----------------------TMS570_CRC_INTR----------------------*/ +/* field: CH2_TIMEOUTENR - Channel 2 Timeout Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_BIT32(12) + +/* field: CH2_UNDERENR - Channel 2 Underrun Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH2_UNDERENR BSP_BIT32(11) + +/* field: CH2_OVERENR - Channel 2 Overrun Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH2_OVERENR BSP_BIT32(10) + +/* field: CH2_CRCFAILENR - Channel 2 CRC Fail Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_BIT32(9) + +/* field: CH2_CCITENR - Channel 2 Compression Complete Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH2_CCITENR BSP_BIT32(8) + +/* field: CH1_TIMEOUTENR - Channel 1 Timeout Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_BIT32(4) + +/* field: CH1_UNDERENR - interrupt. Writing a zero has no effect. */ +#define TMS570_CRC_INTR_CH1_UNDERENR BSP_BIT32(3) + +/* field: CH1_OVERENR - CH1_OVERENR */ +#define TMS570_CRC_INTR_CH1_OVERENR BSP_BIT32(2) + +/* field: CH1_CRCFAILENR - Channel 1 CRC Fail Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_BIT32(1) + +/* field: CH1_CCITENR - Channel 1 Compression Complete Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH1_CCITENR BSP_BIT32(0) + + +/*---------------------TMS570_CRC_STATUS---------------------*/ +/* field: CH2_TIMEOUT - Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. */ +#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_BIT32(12) + +/* field: CH2_UNDER - Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. */ +#define TMS570_CRC_STATUS_CH2_UNDER BSP_BIT32(11) + +/* field: CH2_OVER - Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. */ +#define TMS570_CRC_STATUS_CH2_OVER BSP_BIT32(10) + +/* field: CH2_CRCFAIL - Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. */ +#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_BIT32(9) + +/* field: CH2_CCIT - Channel 2 CRC Pattern Compression Complete Status Flag. */ +#define TMS570_CRC_STATUS_CH2_CCIT BSP_BIT32(8) + +/* field: CH1_TIMEOUT - Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). */ +#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_BIT32(4) + +/* field: CH1_UNDER - Channel 1 Underrun Interrupt Enable Bit. */ +#define TMS570_CRC_STATUS_CH1_UNDER BSP_BIT32(3) + +/* field: CH1_OVER - Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit disable the overrun interrupt. */ +#define TMS570_CRC_STATUS_CH1_OVER BSP_BIT32(2) + +/* field: CH1_CRCFAIL - Channel 1 CRC Fail Interrupt Enable Bit. */ +#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_BIT32(1) + +/* field: CH1_CCIT - Channel 1 CRC Pattern Compression Complete Status Flag. */ +#define TMS570_CRC_STATUS_CH1_CCIT BSP_BIT32(0) + + +/*------------------TMS570_CRC_INT_OFFS_REG------------------*/ +/* field: OFSTREG - CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. */ +#define TMS570_CRC_INT_OFFS_REG_OFSTREG(val) BSP_FLD32(val,0, 7) +#define TMS570_CRC_INT_OFFS_REG_OFSTREG_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_CRC_INT_OFFS_REG_OFSTREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_CRC_BUSY----------------------*/ +/* field: CH2_BUSY - CH2_BUSY. */ +#define TMS570_CRC_BUSY_CH2_BUSY BSP_BIT32(8) + +/* field: CH1_BUSY - CH1_BUSY. */ +#define TMS570_CRC_BUSY_CH1_BUSY BSP_BIT32(0) + + +/*-------------------TMS570_CRC_PCOUNT_REG1-------------------*/ +/* field: CRC_PAT_COUNT1 - Channel 1 Pattern Counter Preload Register. */ +#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1(val) BSP_FLD32(val,0, 19) +#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19) +#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) + + +/*-------------------TMS570_CRC_SCOUNT_REG1-------------------*/ +/* field: CRC_SEC_COUNT1 - Channel 1 Sector Counter Preload Register. */ +#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1(val) BSP_FLD32(val,0, 15) +#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_CRC_CURSEC_REG1-------------------*/ +/* field: CRC_CURSEC1 - Channel 1 Current Sector ID Register. */ +#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1(val) BSP_FLD32(val,0, 15) +#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_CRC_WDTOPLD1--------------------*/ +/* field: CRC_WDTOPLD1 - CRC_WDTOPLD1 */ +#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1(val) BSP_FLD32(val,0, 23) +#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*--------------------TMS570_CRC_BCTOPLD1--------------------*/ +/* field: CRC_BCTOPLD1 - Channel 1 Block Complete Timeout Counter Preload Register. */ +#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1(val) BSP_FLD32(val,0, 23) +#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*------------------TMS570_CRC_PSA_SIGREGL1------------------*/ +/* field: PSASIG1 - Channel 1 PSA Signature Low Register. */ +/* Whole 32 bits */ + +/*------------------TMS570_CRC_PSA_SIGREGH1------------------*/ +/* field: PSASIG1 - register. */ +/* Whole 32 bits */ + +/*----------------------TMS570_CRC_REGL1----------------------*/ +/* field: CRC1 - Channel 1 CRC Value Low Register. */ +/* Whole 32 bits */ + +/*----------------------TMS570_CRC_REGH1----------------------*/ +/* field: CRC1 - Channel 1 CRC Value Low Register. */ +/* Whole 32 bits */ + +/*-----------------TMS570_CRC_PSA_SECSIGREGL1-----------------*/ +/* field: PSASECSIG1 - Channel 1 PSA Sector Signature Low Register. */ +/* Whole 32 bits */ + +/*-----------------TMS570_CRC_PSA_SECSIGREGH1-----------------*/ +/* field: PSASECSIG1 - Channel 1 PSA Sector Signature High Register. */ +/* Whole 32 bits */ + +/*------------------TMS570_CRC_RAW_DATAREGL1------------------*/ +/* field: RAW_DATA1 - hannel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. */ +/* Whole 32 bits */ + +/*------------------TMS570_CRC_RAW_DATAREGH1------------------*/ +/* field: RAW_DATA1 - Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data. */ +/* Whole 32 bits */ + +/*-------------------TMS570_CRC_PCOUNT_REG2-------------------*/ +/* field: CRC_PAT_COUNT2 - Channel 2 Pattern Counter Preload Register. */ +#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2(val) BSP_FLD32(val,0, 19) +#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 19) +#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) + + +/*-------------------TMS570_CRC_SCOUNT_REG2-------------------*/ +/* field: CRC_SEC_COUNT2 - Channel 2 Sector Counter Preload Register. */ +#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2(val) BSP_FLD32(val,0, 15) +#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_CRC_CURSEC_REG2-------------------*/ +/* field: CRC_CURSEC2 - Channel 2 Current Sector ID Register. */ +#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2(val) BSP_FLD32(val,0, 15) +#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_CRC_WDTOPLD2--------------------*/ +/* field: CRC_WDTOPLD2 - Channel 2 Watchdog Timeout Counter Preload Register. */ +#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2(val) BSP_FLD32(val,0, 23) +#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*--------------------TMS570_CRC_BCTOPLD2--------------------*/ +/* field: CRC_BCTOPLD2 - Channel 2 Block Complete Timeout Counter Preload Register. */ +#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2(val) BSP_FLD32(val,0, 23) +#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*------------------TMS570_CRC_PSA_SIGREGL2------------------*/ +/* field: PSASIG2 - Channel 2 PSA Signature Low Register. */ +/* Whole 32 bits */ + +/*------------------TMS570_CRC_PSA_SIGREGH2------------------*/ +/* field: PSASIG2 - Channel 2 PSA Signature High Register. */ +/* Whole 32 bits */ + +/*----------------------TMS570_CRC_REGL2----------------------*/ +/* field: CRC2 - stored at CRC2[31:0] register. */ +/* Whole 32 bits */ + +/*----------------------TMS570_CRC_REGH2----------------------*/ +/* field: CRC2 - Channel 2 CRC Value High Register. */ +/* Whole 32 bits */ + +/*-----------------TMS570_CRC_PSA_SECSIGREGL2-----------------*/ +/* field: PSASECSIG2 - Channel 2 PSA Sector Signature Low Register. */ +/* Whole 32 bits */ + +/*-----------------TMS570_CRC_PSA_SECSIGREGH2-----------------*/ +/* field: PSASECSIG2 - Channel 2 PSA Sector Signature High Register. */ +/* Whole 32 bits */ + +/*------------------TMS570_CRC_RAW_DATAREGL2------------------*/ +/* field: RAW_DATA2 - Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. */ +/* Whole 32 bits */ + +/*------------------TMS570_CRC_RAW_DATAREGH2------------------*/ +/* field: RAW_DATA2 - Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. */ +/* Whole 32 bits */ + +/*---------------------TMS570_CRC_BUS_SEL---------------------*/ +/* field: MEn - Enable/disables the tracing of Peripheral Bus Master */ +#define TMS570_CRC_BUS_SEL_MEn BSP_BIT32(2) + +/* field: DTCMEn - Enable/disables the tracing of data TCM */ +#define TMS570_CRC_BUS_SEL_DTCMEn BSP_BIT32(1) + +/* field: ITCMEn - Enable/disables the tracing of instruction TCM */ +#define TMS570_CRC_BUS_SEL_ITCMEn BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_CRC */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h new file mode 100644 index 0000000000..c278f554ff --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h @@ -0,0 +1,941 @@ +/* The header file is generated by make_header.py from DCAN.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_DCAN +#define LIBBSP_ARM_TMS570_DCAN + +#include + +typedef struct{ + uint32_t CTL; /*CAN Control Register*/ + uint32_t ES; /*Error and Status Register*/ + uint32_t ERRC; /*Error Counter Register*/ + uint32_t BTR; /*Bit Timing Register*/ + uint32_t INT; /*Interrupt Register*/ + uint32_t TEST; /*Test Register*/ + uint8_t reserved1 [4]; + uint32_t PERR; /*Parity Error Code Register*/ + uint8_t reserved2 [96]; + uint32_t ABOTR; /*Auto-Bus-On Time Register*/ + uint32_t TXRQX; /*Transmission Request X Register*/ + uint32_t TXRQx[4]; /*Transmission Request Register*/ + uint32_t NWDATX; /*New Data X Register*/ + uint32_t NWDATx[4]; /*New Data Register*/ + uint32_t INTPNDX; /*Interrupt Pending X Register*/ + uint32_t INTPNDx[4]; /*Interrupt Pending Register*/ + uint32_t MSGVALX; /*Message Valid X Register*/ + uint32_t MSGVALx[4]; /*Message Valid Register*/ + uint8_t reserved3 [4]; + uint32_t INTMUXx[4]; /*Interrupt Multiplexer Register*/ + uint8_t reserved4 [24]; + uint32_t IF1CMD; /*IF1 Command Register*/ + uint32_t IF1MSK; /*IF1 Mask Register*/ + uint32_t IF1ARB; /*IF1 Arbitration Register*/ + uint32_t IF1MCTL; /*IF1 Message Control Register*/ + uint32_t IF1DATA; /*IF1 Data A Register*/ + uint32_t IF1DATB; /*IF1 Data B Register*/ + uint8_t reserved5 [8]; + uint32_t IF2CMD; /*IF2 Command Register*/ + uint32_t IF2MSK; /*IF2 Mask Register*/ + uint32_t IF2ARB; /*IF2 Arbitration Register*/ + uint32_t IF2MCTL; /*IF2 Message Control Register*/ + uint32_t IF2DATA; /*IF2 Data A Register*/ + uint32_t IF2DATB; /*IF2 Data B Register*/ + uint8_t reserved6 [8]; + uint32_t IF3OBS; /*IF3 Observation Register*/ + uint32_t IF3MSK; /*IF3 Mask Register*/ + uint32_t IF3ARB; /*IF3 Arbitration Register*/ + uint32_t IF3MCTL; /*IF3 Message Control Register*/ + uint32_t IF3DATA; /*IF3 Data A Register*/ + uint32_t IF3DATB; /*IF3 Data B Register*/ + uint8_t reserved7 [8]; + uint32_t IF3UEy[4]; /*IF3 Update Enable Register*/ + uint8_t reserved8 [112]; + uint32_t TIOC; /*CAN TX IO Control Register*/ + uint32_t RIOC; /*CAN RX IO Control Register*/ +} tms570_dcan_t; + + +/*----------------------TMS570_DCAN_CTL----------------------*/ +/* field: WUBA - Automatic wake up on bus activity when in local power down mode */ +#define TMS570_DCAN_CTL_WUBA BSP_BIT32(25) + +/* field: PDR - Request for local low power down mode */ +#define TMS570_DCAN_CTL_PDR BSP_BIT32(24) + +/* field: DE3 - Enable DMA request line for IF3 */ +#define TMS570_DCAN_CTL_DE3 BSP_BIT32(20) + +/* field: DE2 - Enable DMA request line for IF2 */ +#define TMS570_DCAN_CTL_DE2 BSP_BIT32(19) + +/* field: DE1 - Enable DMA request line for IF1 */ +#define TMS570_DCAN_CTL_DE1 BSP_BIT32(18) + +/* field: IE1 - Interrupt line 1 Enable */ +#define TMS570_DCAN_CTL_IE1 BSP_BIT32(17) + +/* field: InitDbg - Internal Init state while debug access */ +#define TMS570_DCAN_CTL_InitDbg BSP_BIT32(16) + +/* field: SWR - SW Reset Enable */ +#define TMS570_DCAN_CTL_SWR BSP_BIT32(15) + +/* field: PMD - Parity on/off */ +#define TMS570_DCAN_CTL_PMD(val) BSP_FLD32(val,10, 13) +#define TMS570_DCAN_CTL_PMD_GET(reg) BSP_FLD32GET(reg,10, 13) +#define TMS570_DCAN_CTL_PMD_SET(reg,val) BSP_FLD32SET(reg, val,10, 13) + +/* field: ABO - Auto-Bus-On Enable */ +#define TMS570_DCAN_CTL_ABO BSP_BIT32(9) + +/* field: IDS - Interruption Debug Support Enable */ +#define TMS570_DCAN_CTL_IDS BSP_BIT32(8) + +/* field: Test - Test Mode Enable */ +#define TMS570_DCAN_CTL_Test BSP_BIT32(7) + +/* field: CCE - Configuration Change Enable */ +#define TMS570_DCAN_CTL_CCE BSP_BIT32(6) + +/* field: DAR - Disable Automatic Retransmission */ +#define TMS570_DCAN_CTL_DAR BSP_BIT32(5) + +/* field: EIE - Error Interrupt Enable */ +#define TMS570_DCAN_CTL_EIE BSP_BIT32(3) + +/* field: SIE - Status Change Interrupt Enable */ +#define TMS570_DCAN_CTL_SIE BSP_BIT32(2) + +/* field: IE0 - Interrupt line 0 Enable */ +#define TMS570_DCAN_CTL_IE0 BSP_BIT32(1) + +/* field: Init - Initialization */ +#define TMS570_DCAN_CTL_Init BSP_BIT32(0) + + +/*-----------------------TMS570_DCAN_ES-----------------------*/ +/* field: PDA - Local power down mode acknowledge */ +#define TMS570_DCAN_ES_PDA BSP_BIT32(10) + +/* field: WakeUp_Pnd - Wake Up Pending */ +#define TMS570_DCAN_ES_WakeUp_Pnd BSP_BIT32(9) + +/* field: PER - Parity Error Detected */ +#define TMS570_DCAN_ES_PER BSP_BIT32(8) + +/* field: BOff - Bus-Off State */ +#define TMS570_DCAN_ES_BOff BSP_BIT32(7) + +/* field: EWarn - Warning State */ +#define TMS570_DCAN_ES_EWarn BSP_BIT32(6) + +/* field: EPass - Error Passive State */ +#define TMS570_DCAN_ES_EPass BSP_BIT32(5) + +/* field: RxOK - Received a message successfully */ +#define TMS570_DCAN_ES_RxOK BSP_BIT32(4) + +/* field: TxOK - Transmitted a message successfully */ +#define TMS570_DCAN_ES_TxOK BSP_BIT32(3) + +/* field: LEC - Last Error Code */ +#define TMS570_DCAN_ES_LEC(val) BSP_FLD32(val,0, 2) +#define TMS570_DCAN_ES_LEC_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_DCAN_ES_LEC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*----------------------TMS570_DCAN_ERRC----------------------*/ +/* field: RP - Receive Error Passive */ +#define TMS570_DCAN_ERRC_RP BSP_BIT32(15) + +/* field: REC - Receive Error Counter. Actual state of the Receive Error Counter. (values from 0 to 255). */ +#define TMS570_DCAN_ERRC_REC(val) BSP_FLD32(val,8, 14) +#define TMS570_DCAN_ERRC_REC_GET(reg) BSP_FLD32GET(reg,8, 14) +#define TMS570_DCAN_ERRC_REC_SET(reg,val) BSP_FLD32SET(reg, val,8, 14) + +/* field: TEC - Transmit Error Counter. Actual state of the Transmit Error Counter. (values from 0 to 255). */ +#define TMS570_DCAN_ERRC_TEC(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_ERRC_TEC_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_ERRC_TEC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_DCAN_BTR----------------------*/ +/* field: BRPE - Baud Rate Prescaler Extension. */ +#define TMS570_DCAN_BTR_BRPE(val) BSP_FLD32(val,16, 19) +#define TMS570_DCAN_BTR_BRPE_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_DCAN_BTR_BRPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: TSeg2 - Time segment after the sample point */ +#define TMS570_DCAN_BTR_TSeg2(val) BSP_FLD32(val,12, 14) +#define TMS570_DCAN_BTR_TSeg2_GET(reg) BSP_FLD32GET(reg,12, 14) +#define TMS570_DCAN_BTR_TSeg2_SET(reg,val) BSP_FLD32SET(reg, val,12, 14) + +/* field: TSeg1 - Time segment before the sample point */ +#define TMS570_DCAN_BTR_TSeg1(val) BSP_FLD32(val,8, 11) +#define TMS570_DCAN_BTR_TSeg1_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_DCAN_BTR_TSeg1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: SJW - Synchronization Jump Width */ +#define TMS570_DCAN_BTR_SJW(val) BSP_FLD32(val,6, 7) +#define TMS570_DCAN_BTR_SJW_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DCAN_BTR_SJW_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: BRP - Baud Rate Prescaler */ +#define TMS570_DCAN_BTR_BRP(val) BSP_FLD32(val,0, 5) +#define TMS570_DCAN_BTR_BRP_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DCAN_BTR_BRP_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_DCAN_INT----------------------*/ +/* field: Int1ID - Interrupt 1 Identifier (indicates the message object with the highest pending interrupt) */ +#define TMS570_DCAN_INT_Int1ID(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_INT_Int1ID_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_INT_Int1ID_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Int0ID - Interrupt Identifier (the number here indicates the source of the interrupt) */ +#define TMS570_DCAN_INT_Int0ID(val) BSP_FLD32(val,0, 15) +#define TMS570_DCAN_INT_Int0ID_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DCAN_INT_Int0ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_DCAN_TEST----------------------*/ +/* field: RDA - RAM Direct Access Enable */ +#define TMS570_DCAN_TEST_RDA BSP_BIT32(9) + +/* field: EXL - External Loop Back Mode */ +#define TMS570_DCAN_TEST_EXL BSP_BIT32(8) + +/* field: Rx - Receive Pin. Monitors the actual value of the CAN_RX pin. */ +#define TMS570_DCAN_TEST_Rx BSP_BIT32(7) + +/* field: Tx - Control of CAN_TX pin */ +#define TMS570_DCAN_TEST_Tx(val) BSP_FLD32(val,5, 6) +#define TMS570_DCAN_TEST_Tx_GET(reg) BSP_FLD32GET(reg,5, 6) +#define TMS570_DCAN_TEST_Tx_SET(reg,val) BSP_FLD32SET(reg, val,5, 6) + +/* field: LBack - Loop Back Mode */ +#define TMS570_DCAN_TEST_LBack BSP_BIT32(4) + +/* field: Silent - Silent Mode */ +#define TMS570_DCAN_TEST_Silent BSP_BIT32(3) + + +/*----------------------TMS570_DCAN_PERR----------------------*/ +/* field: Word_Number - Word number where parity error has been detected */ +#define TMS570_DCAN_PERR_Word_Number(val) BSP_FLD32(val,8, 10) +#define TMS570_DCAN_PERR_Word_Number_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_DCAN_PERR_Word_Number_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: Message_Number - */ +#define TMS570_DCAN_PERR_Message_Number(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_PERR_Message_Number_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_PERR_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_DCAN_ABOTR---------------------*/ +/* field: ABO_Time - Number of VBUS clock cycles before a Bus-Off recovery sequence is */ +/* Whole 32 bits */ + +/*---------------------TMS570_DCAN_TXRQX---------------------*/ +/* field: TxRqstReg8 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg8(val) BSP_FLD32(val,14, 15) +#define TMS570_DCAN_TXRQX_TxRqstReg8_GET(reg) BSP_FLD32GET(reg,14, 15) +#define TMS570_DCAN_TXRQX_TxRqstReg8_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) + +/* field: TxRqstReg7 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg7(val) BSP_FLD32(val,12, 13) +#define TMS570_DCAN_TXRQX_TxRqstReg7_GET(reg) BSP_FLD32GET(reg,12, 13) +#define TMS570_DCAN_TXRQX_TxRqstReg7_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) + +/* field: TxRqstReg6 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg6(val) BSP_FLD32(val,10, 11) +#define TMS570_DCAN_TXRQX_TxRqstReg6_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_DCAN_TXRQX_TxRqstReg6_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: TxRqstReg5 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg5(val) BSP_FLD32(val,8, 9) +#define TMS570_DCAN_TXRQX_TxRqstReg5_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_DCAN_TXRQX_TxRqstReg5_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: TxRqstReg4 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg4(val) BSP_FLD32(val,6, 7) +#define TMS570_DCAN_TXRQX_TxRqstReg4_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DCAN_TXRQX_TxRqstReg4_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: TxRqstReg3 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg3(val) BSP_FLD32(val,4, 5) +#define TMS570_DCAN_TXRQX_TxRqstReg3_GET(reg) BSP_FLD32GET(reg,4, 5) +#define TMS570_DCAN_TXRQX_TxRqstReg3_SET(reg,val) BSP_FLD32SET(reg, val,4, 5) + +/* field: TxRqstReg2 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg2(val) BSP_FLD32(val,2, 3) +#define TMS570_DCAN_TXRQX_TxRqstReg2_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_DCAN_TXRQX_TxRqstReg2_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: TxRqstReg1 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg1(val) BSP_FLD32(val,0, 1) +#define TMS570_DCAN_TXRQX_TxRqstReg1_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_DCAN_TXRQX_TxRqstReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_DCAN_TXRQx---------------------*/ +/* field: TxRqsX - Transmission Request Bits (for all message objects) */ +/* Whole 32 bits */ + +/*---------------------TMS570_DCAN_NWDATX---------------------*/ +/* field: NewDatReg8 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg8(val) BSP_FLD32(val,14, 15) +#define TMS570_DCAN_NWDATX_NewDatReg8_GET(reg) BSP_FLD32GET(reg,14, 15) +#define TMS570_DCAN_NWDATX_NewDatReg8_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) + +/* field: NewDatReg7 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg7(val) BSP_FLD32(val,12, 13) +#define TMS570_DCAN_NWDATX_NewDatReg7_GET(reg) BSP_FLD32GET(reg,12, 13) +#define TMS570_DCAN_NWDATX_NewDatReg7_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) + +/* field: NewDatReg6 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg6(val) BSP_FLD32(val,10, 11) +#define TMS570_DCAN_NWDATX_NewDatReg6_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_DCAN_NWDATX_NewDatReg6_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: NewDatReg5 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg5(val) BSP_FLD32(val,8, 9) +#define TMS570_DCAN_NWDATX_NewDatReg5_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_DCAN_NWDATX_NewDatReg5_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: NewDatReg4 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg4(val) BSP_FLD32(val,6, 7) +#define TMS570_DCAN_NWDATX_NewDatReg4_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DCAN_NWDATX_NewDatReg4_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: NewDatReg3 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg3(val) BSP_FLD32(val,4, 5) +#define TMS570_DCAN_NWDATX_NewDatReg3_GET(reg) BSP_FLD32GET(reg,4, 5) +#define TMS570_DCAN_NWDATX_NewDatReg3_SET(reg,val) BSP_FLD32SET(reg, val,4, 5) + +/* field: NewDatReg2 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg2(val) BSP_FLD32(val,2, 3) +#define TMS570_DCAN_NWDATX_NewDatReg2_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_DCAN_NWDATX_NewDatReg2_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: NewDatReg1 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg1(val) BSP_FLD32(val,0, 1) +#define TMS570_DCAN_NWDATX_NewDatReg1_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_DCAN_NWDATX_NewDatReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_DCAN_NWDATx---------------------*/ +/* field: NewDatX - New Data Bits (for all message objects) */ +/* Whole 32 bits */ + +/*--------------------TMS570_DCAN_INTPNDX--------------------*/ +/* field: IntPndReg8 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg8(val) BSP_FLD32(val,14, 15) +#define TMS570_DCAN_INTPNDX_IntPndReg8_GET(reg) BSP_FLD32GET(reg,14, 15) +#define TMS570_DCAN_INTPNDX_IntPndReg8_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) + +/* field: IntPndReg7 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg7(val) BSP_FLD32(val,12, 13) +#define TMS570_DCAN_INTPNDX_IntPndReg7_GET(reg) BSP_FLD32GET(reg,12, 13) +#define TMS570_DCAN_INTPNDX_IntPndReg7_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) + +/* field: IntPndReg6 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg6(val) BSP_FLD32(val,10, 11) +#define TMS570_DCAN_INTPNDX_IntPndReg6_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_DCAN_INTPNDX_IntPndReg6_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: IntPndReg5 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg5(val) BSP_FLD32(val,8, 9) +#define TMS570_DCAN_INTPNDX_IntPndReg5_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_DCAN_INTPNDX_IntPndReg5_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: IntPndReg4 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg4(val) BSP_FLD32(val,6, 7) +#define TMS570_DCAN_INTPNDX_IntPndReg4_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DCAN_INTPNDX_IntPndReg4_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: IntPndReg3 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg3(val) BSP_FLD32(val,4, 5) +#define TMS570_DCAN_INTPNDX_IntPndReg3_GET(reg) BSP_FLD32GET(reg,4, 5) +#define TMS570_DCAN_INTPNDX_IntPndReg3_SET(reg,val) BSP_FLD32SET(reg, val,4, 5) + +/* field: IntPndReg2 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg2(val) BSP_FLD32(val,2, 3) +#define TMS570_DCAN_INTPNDX_IntPndReg2_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_DCAN_INTPNDX_IntPndReg2_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: IntPndReg1 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg1(val) BSP_FLD32(val,0, 1) +#define TMS570_DCAN_INTPNDX_IntPndReg1_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_DCAN_INTPNDX_IntPndReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_DCAN_INTPNDx--------------------*/ +/* field: IntPndX - Interrupt Pending Bits (for all message objects) */ +/* Whole 32 bits */ + +/*--------------------TMS570_DCAN_MSGVALX--------------------*/ +/* field: MsgValReg8 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg8(val) BSP_FLD32(val,14, 15) +#define TMS570_DCAN_MSGVALX_MsgValReg8_GET(reg) BSP_FLD32GET(reg,14, 15) +#define TMS570_DCAN_MSGVALX_MsgValReg8_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) + +/* field: MsgValReg7 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg7(val) BSP_FLD32(val,12, 13) +#define TMS570_DCAN_MSGVALX_MsgValReg7_GET(reg) BSP_FLD32GET(reg,12, 13) +#define TMS570_DCAN_MSGVALX_MsgValReg7_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) + +/* field: MsgValReg6 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg6(val) BSP_FLD32(val,10, 11) +#define TMS570_DCAN_MSGVALX_MsgValReg6_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_DCAN_MSGVALX_MsgValReg6_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: MsgValReg5 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg5(val) BSP_FLD32(val,8, 9) +#define TMS570_DCAN_MSGVALX_MsgValReg5_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_DCAN_MSGVALX_MsgValReg5_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: MsgValReg4 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg4(val) BSP_FLD32(val,6, 7) +#define TMS570_DCAN_MSGVALX_MsgValReg4_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DCAN_MSGVALX_MsgValReg4_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: MsgValReg3 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg3(val) BSP_FLD32(val,4, 5) +#define TMS570_DCAN_MSGVALX_MsgValReg3_GET(reg) BSP_FLD32GET(reg,4, 5) +#define TMS570_DCAN_MSGVALX_MsgValReg3_SET(reg,val) BSP_FLD32SET(reg, val,4, 5) + +/* field: MsgValReg2 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg2(val) BSP_FLD32(val,2, 3) +#define TMS570_DCAN_MSGVALX_MsgValReg2_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_DCAN_MSGVALX_MsgValReg2_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: MsgValReg1 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg1(val) BSP_FLD32(val,0, 1) +#define TMS570_DCAN_MSGVALX_MsgValReg1_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_DCAN_MSGVALX_MsgValReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_DCAN_MSGVALx--------------------*/ +/* field: MsgVal1To32 - Message Valid Bits (for all message objects) */ +/* Whole 32 bits */ + +/*--------------------TMS570_DCAN_INTMUXx--------------------*/ +/* field: IntMux1To32 - Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt lines. */ +/* Whole 32 bits */ + +/*---------------------TMS570_DCAN_IF1CMD---------------------*/ +/* field: WR_RD - Write/Read */ +#define TMS570_DCAN_IF1CMD_WR_RD BSP_BIT32(23) + +/* field: Mask - Access Mask bits */ +#define TMS570_DCAN_IF1CMD_Mask BSP_BIT32(22) + +/* field: Arb - Access Arbitration bits */ +#define TMS570_DCAN_IF1CMD_Arb BSP_BIT32(21) + +/* field: Control - Access Control bits */ +#define TMS570_DCAN_IF1CMD_Control BSP_BIT32(20) + +/* field: ClrIntPnd - Clear Interrupt Pending bit */ +#define TMS570_DCAN_IF1CMD_ClrIntPnd BSP_BIT32(19) + +/* field: TxRqst_NewDat - Access Transmission Request bit */ +#define TMS570_DCAN_IF1CMD_TxRqst_NewDat BSP_BIT32(18) + +/* field: Data_A - Access Data Bytes 0-3 */ +#define TMS570_DCAN_IF1CMD_Data_A BSP_BIT32(17) + +/* field: Data_B - Access Data Bytes 4-7 */ +#define TMS570_DCAN_IF1CMD_Data_B BSP_BIT32(16) + +/* field: Busy - Busy flag */ +#define TMS570_DCAN_IF1CMD_Busy BSP_BIT32(15) + +/* field: DMA_Active - Activation of DMA feature for subsequent internal IF1/IF2 update */ +#define TMS570_DCAN_IF1CMD_DMA_Active BSP_BIT32(14) + +/* field: Message_Number - Number of message object in Message RAM that is used for data transfer */ +#define TMS570_DCAN_IF1CMD_Message_Number(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF1CMD_Message_Number_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF1CMD_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_DCAN_IF1MSK---------------------*/ +/* field: MXtd - Mask Extended Identifier */ +#define TMS570_DCAN_IF1MSK_MXtd BSP_BIT32(31) + +/* field: MDir - Mask Message Direction */ +#define TMS570_DCAN_IF1MSK_MDir BSP_BIT32(30) + +/* field: Msk - Identifier Mask */ +#define TMS570_DCAN_IF1MSK_Msk(val) BSP_FLD32(val,0, 28) +#define TMS570_DCAN_IF1MSK_Msk_GET(reg) BSP_FLD32GET(reg,0, 28) +#define TMS570_DCAN_IF1MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28) + + +/*---------------------TMS570_DCAN_IF1ARB---------------------*/ +/* field: MsgVal - Message Valid */ +#define TMS570_DCAN_IF1ARB_MsgVal BSP_BIT32(31) + +/* field: Xtd - Extended Identifier */ +#define TMS570_DCAN_IF1ARB_Xtd BSP_BIT32(30) + +/* field: Dir - Message direction */ +#define TMS570_DCAN_IF1ARB_Dir BSP_BIT32(29) + +/* field: ID - Message Identifier */ +#define TMS570_DCAN_IF1ARB_ID(val) BSP_FLD32(val,0, 28) +#define TMS570_DCAN_IF1ARB_ID_GET(reg) BSP_FLD32GET(reg,0, 28) +#define TMS570_DCAN_IF1ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28) + + +/*--------------------TMS570_DCAN_IF1MCTL--------------------*/ +/* field: NewDat - New Data */ +#define TMS570_DCAN_IF1MCTL_NewDat BSP_BIT32(15) + +/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */ +#define TMS570_DCAN_IF1MCTL_MsgLst BSP_BIT32(14) + +/* field: IntPnd - Interrupt Pending */ +#define TMS570_DCAN_IF1MCTL_IntPnd BSP_BIT32(13) + +/* field: UMask - Use Acceptance Mask */ +#define TMS570_DCAN_IF1MCTL_UMask BSP_BIT32(12) + +/* field: TxIE - Transmit Interrupt Enable */ +#define TMS570_DCAN_IF1MCTL_TxIE BSP_BIT32(11) + +/* field: RxIE - Receive Interrupt Enable */ +#define TMS570_DCAN_IF1MCTL_RxIE BSP_BIT32(10) + +/* field: RmtEn - Remote Enable */ +#define TMS570_DCAN_IF1MCTL_RmtEn BSP_BIT32(9) + +/* field: TxRqst - Transmit Request */ +#define TMS570_DCAN_IF1MCTL_TxRqst BSP_BIT32(8) + +/* field: EoB - Data Frame has 0-8 data bits */ +#define TMS570_DCAN_IF1MCTL_EoB BSP_BIT32(7) + +/* field: DLC - Data Length Code */ +#define TMS570_DCAN_IF1MCTL_DLC(val) BSP_FLD32(val,0, 3) +#define TMS570_DCAN_IF1MCTL_DLC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DCAN_IF1MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_DCAN_IF1DATA--------------------*/ +/* field: Data0 - Data 0 */ +#define TMS570_DCAN_IF1DATA_Data0(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF1DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF1DATA_Data0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + +/* field: Data1 - Data 1 */ +#define TMS570_DCAN_IF1DATA_Data1(val) BSP_FLD32(val,8, 15) +#define TMS570_DCAN_IF1DATA_Data1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_DCAN_IF1DATA_Data1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: Data2 - Data 2 */ +#define TMS570_DCAN_IF1DATA_Data2(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_IF1DATA_Data2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_IF1DATA_Data2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Data3 - Data 3 */ +#define TMS570_DCAN_IF1DATA_Data3(val) BSP_FLD32(val,24, 31) +#define TMS570_DCAN_IF1DATA_Data3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_DCAN_IF1DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + + +/*--------------------TMS570_DCAN_IF1DATB--------------------*/ +/* field: Data4 - Data 4 */ +#define TMS570_DCAN_IF1DATB_Data4(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF1DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF1DATB_Data4_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + +/* field: Data5 - Data 5 */ +#define TMS570_DCAN_IF1DATB_Data5(val) BSP_FLD32(val,8, 15) +#define TMS570_DCAN_IF1DATB_Data5_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_DCAN_IF1DATB_Data5_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: Data6 - Data 6 */ +#define TMS570_DCAN_IF1DATB_Data6(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_IF1DATB_Data6_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_IF1DATB_Data6_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Data7 - Data 7 */ +#define TMS570_DCAN_IF1DATB_Data7(val) BSP_FLD32(val,24, 31) +#define TMS570_DCAN_IF1DATB_Data7_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_DCAN_IF1DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + + +/*---------------------TMS570_DCAN_IF2CMD---------------------*/ +/* field: WR_RD - Write/Read */ +#define TMS570_DCAN_IF2CMD_WR_RD BSP_BIT32(23) + +/* field: Mask - Access Mask bits */ +#define TMS570_DCAN_IF2CMD_Mask BSP_BIT32(22) + +/* field: Arb - Access Arbitration bits */ +#define TMS570_DCAN_IF2CMD_Arb BSP_BIT32(21) + +/* field: Control - Access Control bits */ +#define TMS570_DCAN_IF2CMD_Control BSP_BIT32(20) + +/* field: ClrIntPnd - Clear Interrupt Pending bit */ +#define TMS570_DCAN_IF2CMD_ClrIntPnd BSP_BIT32(19) + +/* field: TxRqst_NewDat - Access Transmission Request bit */ +#define TMS570_DCAN_IF2CMD_TxRqst_NewDat BSP_BIT32(18) + +/* field: Data_A - Access Data Bytes 0-3 */ +#define TMS570_DCAN_IF2CMD_Data_A BSP_BIT32(17) + +/* field: Data_B - Access Data Bytes 4-7 */ +#define TMS570_DCAN_IF2CMD_Data_B BSP_BIT32(16) + +/* field: Busy - Busy flag */ +#define TMS570_DCAN_IF2CMD_Busy BSP_BIT32(15) + +/* field: DMA_Active - Activation of DMA feature for subsequent internal IF1/IF2 update */ +#define TMS570_DCAN_IF2CMD_DMA_Active BSP_BIT32(14) + +/* field: Message_Number - Number of message object in Message RAM that is used for data transfer */ +#define TMS570_DCAN_IF2CMD_Message_Number(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF2CMD_Message_Number_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF2CMD_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_DCAN_IF2MSK---------------------*/ +/* field: MXtd - Mask Extended Identifier */ +#define TMS570_DCAN_IF2MSK_MXtd BSP_BIT32(31) + +/* field: MDir - Mask Message Direction */ +#define TMS570_DCAN_IF2MSK_MDir BSP_BIT32(30) + +/* field: Msk - Identifier Mask */ +#define TMS570_DCAN_IF2MSK_Msk(val) BSP_FLD32(val,0, 28) +#define TMS570_DCAN_IF2MSK_Msk_GET(reg) BSP_FLD32GET(reg,0, 28) +#define TMS570_DCAN_IF2MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28) + + +/*---------------------TMS570_DCAN_IF2ARB---------------------*/ +/* field: MsgVal - Message Valid */ +#define TMS570_DCAN_IF2ARB_MsgVal BSP_BIT32(31) + +/* field: Xtd - Extended Identifier */ +#define TMS570_DCAN_IF2ARB_Xtd BSP_BIT32(30) + +/* field: Dir - Message direction */ +#define TMS570_DCAN_IF2ARB_Dir BSP_BIT32(29) + +/* field: ID - Message Identifier */ +#define TMS570_DCAN_IF2ARB_ID(val) BSP_FLD32(val,0, 28) +#define TMS570_DCAN_IF2ARB_ID_GET(reg) BSP_FLD32GET(reg,0, 28) +#define TMS570_DCAN_IF2ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28) + + +/*--------------------TMS570_DCAN_IF2MCTL--------------------*/ +/* field: NewDat - New Data */ +#define TMS570_DCAN_IF2MCTL_NewDat BSP_BIT32(15) + +/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */ +#define TMS570_DCAN_IF2MCTL_MsgLst BSP_BIT32(14) + +/* field: IntPnd - Interrupt Pending */ +#define TMS570_DCAN_IF2MCTL_IntPnd BSP_BIT32(13) + +/* field: UMask - Use Acceptance Mask */ +#define TMS570_DCAN_IF2MCTL_UMask BSP_BIT32(12) + +/* field: TxIE - Transmit Interrupt Enable */ +#define TMS570_DCAN_IF2MCTL_TxIE BSP_BIT32(11) + +/* field: RxIE - Receive Interrupt Enable */ +#define TMS570_DCAN_IF2MCTL_RxIE BSP_BIT32(10) + +/* field: RmtEn - Remote Enable */ +#define TMS570_DCAN_IF2MCTL_RmtEn BSP_BIT32(9) + +/* field: TxRqst - Transmit Request */ +#define TMS570_DCAN_IF2MCTL_TxRqst BSP_BIT32(8) + +/* field: EoB - Data Frame has 0-8 data bits */ +#define TMS570_DCAN_IF2MCTL_EoB BSP_BIT32(7) + +/* field: DLC - Data Length Code */ +#define TMS570_DCAN_IF2MCTL_DLC(val) BSP_FLD32(val,0, 3) +#define TMS570_DCAN_IF2MCTL_DLC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DCAN_IF2MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_DCAN_IF2DATA--------------------*/ +/* field: Data0 - Data 0 */ +#define TMS570_DCAN_IF2DATA_Data0(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF2DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF2DATA_Data0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + +/* field: Data1 - Data 1 */ +#define TMS570_DCAN_IF2DATA_Data1(val) BSP_FLD32(val,8, 15) +#define TMS570_DCAN_IF2DATA_Data1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_DCAN_IF2DATA_Data1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: Data2 - Data 2 */ +#define TMS570_DCAN_IF2DATA_Data2(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_IF2DATA_Data2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_IF2DATA_Data2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Data3 - Data 3 */ +#define TMS570_DCAN_IF2DATA_Data3(val) BSP_FLD32(val,24, 31) +#define TMS570_DCAN_IF2DATA_Data3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_DCAN_IF2DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + + +/*--------------------TMS570_DCAN_IF2DATB--------------------*/ +/* field: Data4 - Data 4 */ +#define TMS570_DCAN_IF2DATB_Data4(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF2DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF2DATB_Data4_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + +/* field: Data5 - Data 5 */ +#define TMS570_DCAN_IF2DATB_Data5(val) BSP_FLD32(val,8, 15) +#define TMS570_DCAN_IF2DATB_Data5_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_DCAN_IF2DATB_Data5_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: Data6 - Data 6 */ +#define TMS570_DCAN_IF2DATB_Data6(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_IF2DATB_Data6_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_IF2DATB_Data6_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Data7 - Data 7 */ +#define TMS570_DCAN_IF2DATB_Data7(val) BSP_FLD32(val,24, 31) +#define TMS570_DCAN_IF2DATB_Data7_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_DCAN_IF2DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + + +/*---------------------TMS570_DCAN_IF3OBS---------------------*/ +/* field: IF3_Upd - IF3 Update Data */ +#define TMS570_DCAN_IF3OBS_IF3_Upd BSP_BIT32(15) + +/* field: IF3_SDB - IF3 Status of Data B read access */ +#define TMS570_DCAN_IF3OBS_IF3_SDB BSP_BIT32(12) + +/* field: IF3_SDA - IF3 Status of Data A read access */ +#define TMS570_DCAN_IF3OBS_IF3_SDA BSP_BIT32(11) + +/* field: IF3_SC - IF3 Status of Control bits read access */ +#define TMS570_DCAN_IF3OBS_IF3_SC BSP_BIT32(10) + +/* field: IF3_SA - IF3 Status of Arbitration data read access */ +#define TMS570_DCAN_IF3OBS_IF3_SA BSP_BIT32(9) + +/* field: IF3_SM - IF3 Status of Mask data read access */ +#define TMS570_DCAN_IF3OBS_IF3_SM BSP_BIT32(8) + +/* field: Data_B - Data B read observation */ +#define TMS570_DCAN_IF3OBS_Data_B BSP_BIT32(4) + +/* field: Data_A - Data A read observation */ +#define TMS570_DCAN_IF3OBS_Data_A BSP_BIT32(3) + +/* field: Ctrl - Ctrl read observation */ +#define TMS570_DCAN_IF3OBS_Ctrl BSP_BIT32(2) + +/* field: Arb - Arbitration data read observation */ +#define TMS570_DCAN_IF3OBS_Arb BSP_BIT32(1) + +/* field: Mask - Mask data read observation */ +#define TMS570_DCAN_IF3OBS_Mask BSP_BIT32(0) + + +/*---------------------TMS570_DCAN_IF3MSK---------------------*/ +/* field: MXtd - Mask Extended Identifier */ +#define TMS570_DCAN_IF3MSK_MXtd BSP_BIT32(31) + +/* field: MDir - Mask Message Direction */ +#define TMS570_DCAN_IF3MSK_MDir BSP_BIT32(30) + +/* field: Msk - Identifier Mask */ +#define TMS570_DCAN_IF3MSK_Msk(val) BSP_FLD32(val,0, 28) +#define TMS570_DCAN_IF3MSK_Msk_GET(reg) BSP_FLD32GET(reg,0, 28) +#define TMS570_DCAN_IF3MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28) + + +/*---------------------TMS570_DCAN_IF3ARB---------------------*/ +/* field: MsgVal - Message Valid */ +#define TMS570_DCAN_IF3ARB_MsgVal BSP_BIT32(31) + +/* field: Xtd - Extended Identifier */ +#define TMS570_DCAN_IF3ARB_Xtd BSP_BIT32(30) + +/* field: Dir - Message direction */ +#define TMS570_DCAN_IF3ARB_Dir BSP_BIT32(29) + +/* field: ID - Message Identifier */ +#define TMS570_DCAN_IF3ARB_ID(val) BSP_FLD32(val,0, 28) +#define TMS570_DCAN_IF3ARB_ID_GET(reg) BSP_FLD32GET(reg,0, 28) +#define TMS570_DCAN_IF3ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28) + + +/*--------------------TMS570_DCAN_IF3MCTL--------------------*/ +/* field: NewDat - New Data */ +#define TMS570_DCAN_IF3MCTL_NewDat BSP_BIT32(15) + +/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */ +#define TMS570_DCAN_IF3MCTL_MsgLst BSP_BIT32(14) + +/* field: IntPnd - Interrupt Pending */ +#define TMS570_DCAN_IF3MCTL_IntPnd BSP_BIT32(13) + +/* field: UMask - Use Acceptance Mask */ +#define TMS570_DCAN_IF3MCTL_UMask BSP_BIT32(12) + +/* field: TxIE - Transmit Interrupt Enable */ +#define TMS570_DCAN_IF3MCTL_TxIE BSP_BIT32(11) + +/* field: RxIE - Receive Interrupt Enable */ +#define TMS570_DCAN_IF3MCTL_RxIE BSP_BIT32(10) + +/* field: RmtEn - Remote Enable */ +#define TMS570_DCAN_IF3MCTL_RmtEn BSP_BIT32(9) + +/* field: TxRqst - TxRqst */ +#define TMS570_DCAN_IF3MCTL_TxRqst BSP_BIT32(8) + +/* field: EoB - End of Block */ +#define TMS570_DCAN_IF3MCTL_EoB BSP_BIT32(7) + +/* field: DLC - Data Length Code */ +#define TMS570_DCAN_IF3MCTL_DLC(val) BSP_FLD32(val,0, 3) +#define TMS570_DCAN_IF3MCTL_DLC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DCAN_IF3MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_DCAN_IF3DATA--------------------*/ +/* field: Data0 - Data 0 */ +#define TMS570_DCAN_IF3DATA_Data0(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF3DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF3DATA_Data0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + +/* field: Data1 - Data 1 */ +#define TMS570_DCAN_IF3DATA_Data1(val) BSP_FLD32(val,8, 15) +#define TMS570_DCAN_IF3DATA_Data1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_DCAN_IF3DATA_Data1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: Data2 - Data 2 */ +#define TMS570_DCAN_IF3DATA_Data2(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_IF3DATA_Data2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_IF3DATA_Data2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Data3 - Data 3 */ +#define TMS570_DCAN_IF3DATA_Data3(val) BSP_FLD32(val,24, 31) +#define TMS570_DCAN_IF3DATA_Data3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_DCAN_IF3DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + + +/*--------------------TMS570_DCAN_IF3DATB--------------------*/ +/* field: Data4 - Data 4 */ +#define TMS570_DCAN_IF3DATB_Data4(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF3DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF3DATB_Data4_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + +/* field: Data5 - Data 5 */ +#define TMS570_DCAN_IF3DATB_Data5(val) BSP_FLD32(val,8, 15) +#define TMS570_DCAN_IF3DATB_Data5_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_DCAN_IF3DATB_Data5_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: Data6 - Data 6 */ +#define TMS570_DCAN_IF3DATB_Data6(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_IF3DATB_Data6_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_IF3DATB_Data6_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Data7 - Data 7 */ +#define TMS570_DCAN_IF3DATB_Data7(val) BSP_FLD32(val,24, 31) +#define TMS570_DCAN_IF3DATB_Data7_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_DCAN_IF3DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + + +/*---------------------TMS570_DCAN_IF3UEy---------------------*/ +/* field: IF3UpdEn - IF3 Update Enabled (for all message objects) */ +/* Whole 32 bits */ + +/*----------------------TMS570_DCAN_TIOC----------------------*/ +/* field: PU - CAN_TX Pullup/Pulldown select. This bit is only active when CAN_TX is configured to be an input. */ +#define TMS570_DCAN_TIOC_PU BSP_BIT32(18) + +/* field: PD - CAN_TX pull disable. This bit is only active when CAN_TX is configured to be an input. */ +#define TMS570_DCAN_TIOC_PD BSP_BIT32(17) + +/* field: OD - CAN_TX open drain enable. */ +#define TMS570_DCAN_TIOC_OD BSP_BIT32(16) + +/* field: Func - CAN_TX function. This bit changes the function of the CAN_TX pin. */ +#define TMS570_DCAN_TIOC_Func BSP_BIT32(3) + +/* field: Dir - CAN_TX data direction. */ +#define TMS570_DCAN_TIOC_Dir BSP_BIT32(2) + +/* field: Out - CAN_TX data out write. */ +#define TMS570_DCAN_TIOC_Out BSP_BIT32(1) + + +/*----------------------TMS570_DCAN_RIOC----------------------*/ +/* field: PU - CAN_RX Pullup/Pulldown select. This bit is only active when CAN_RX is configured to be an input. */ +#define TMS570_DCAN_RIOC_PU BSP_BIT32(18) + +/* field: PD - CAN_RX pull disable. This bit is only active when CAN_RX is configured to be an input. */ +#define TMS570_DCAN_RIOC_PD BSP_BIT32(17) + +/* field: OD - CAN_RX open drain enable. */ +#define TMS570_DCAN_RIOC_OD BSP_BIT32(16) + +/* field: Func - CAN_RX function. This bit changes the function of the CAN_RX pin. */ +#define TMS570_DCAN_RIOC_Func BSP_BIT32(3) + +/* field: Dir - CAN_RX data direction. */ +#define TMS570_DCAN_RIOC_Dir BSP_BIT32(2) + +/* field: Out - CAN_RX data out write. */ +#define TMS570_DCAN_RIOC_Out BSP_BIT32(1) + +/* field: In - CAN_RX data in. */ +#define TMS570_DCAN_RIOC_In BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_DCAN */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h new file mode 100644 index 0000000000..4c90276523 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h @@ -0,0 +1,183 @@ +/* The header file is generated by make_header.py from DCC.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_DCC +#define LIBBSP_ARM_TMS570_DCC + +#include + +typedef struct{ + uint32_t GCTRL; /*DCC Global Control Register*/ + uint32_t REV; /*DCC Revision Id Register*/ + uint32_t CNT0SEED; /*DCC Counter0 Seed Register*/ + uint32_t VALID0SEED; /*DCC Valid0 Seed Register*/ + uint32_t CNT1SEED; /*DCC Counter1 Seed Register*/ + uint32_t STAT; /*DCC Status Register*/ + uint32_t CNT0; /*DCC Counter0 Value Register*/ + uint32_t VALID0; /*DCC Valid0 Value Register*/ + uint32_t CNT1; /*DCC Counter1 Value Register*/ + uint32_t CNT1CLKSRC; /*DCC Counter1 Clock Source Selection Register*/ + uint32_t CNT0CLKSRC; /*DCC Counter0 Clock Source Selection Register*/ +} tms570_dcc_t; + + +/*----------------------TMS570_DCC_GCTRL----------------------*/ +/* field: DONE_INT_ENA - Done Interrupt Enable. */ +#define TMS570_DCC_GCTRL_DONE_INT_ENA(val) BSP_FLD32(val,12, 15) +#define TMS570_DCC_GCTRL_DONE_INT_ENA_GET(reg) BSP_FLD32GET(reg,12, 15) +#define TMS570_DCC_GCTRL_DONE_INT_ENA_SET(reg,val) BSP_FLD32SET(reg, val,12, 15) + +/* field: SINGLE_SHOT - Single-Shot Mode Enable. */ +#define TMS570_DCC_GCTRL_SINGLE_SHOT(val) BSP_FLD32(val,8, 11) +#define TMS570_DCC_GCTRL_SINGLE_SHOT_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_DCC_GCTRL_SINGLE_SHOT_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: ERR_ENA - Error Interrupt Enable. */ +#define TMS570_DCC_GCTRL_ERR_ENA(val) BSP_FLD32(val,4, 7) +#define TMS570_DCC_GCTRL_ERR_ENA_GET(reg) BSP_FLD32GET(reg,4, 7) +#define TMS570_DCC_GCTRL_ERR_ENA_SET(reg,val) BSP_FLD32SET(reg, val,4, 7) + +/* field: DCC_ENA - DCC Enable. */ +#define TMS570_DCC_GCTRL_DCC_ENA(val) BSP_FLD32(val,0, 3) +#define TMS570_DCC_GCTRL_DCC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DCC_GCTRL_DCC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-----------------------TMS570_DCC_REV-----------------------*/ +/* field: SCHEME - Reads return 01, writes have no effect. */ +#define TMS570_DCC_REV_SCHEME(val) BSP_FLD32(val,30, 31) +#define TMS570_DCC_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31) +#define TMS570_DCC_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31) + +/* field: FUNC - Functional release number. Reads return 0x000, writes have no effect. */ +#define TMS570_DCC_REV_FUNC(val) BSP_FLD32(val,16, 27) +#define TMS570_DCC_REV_FUNC_GET(reg) BSP_FLD32GET(reg,16, 27) +#define TMS570_DCC_REV_FUNC_SET(reg,val) BSP_FLD32SET(reg, val,16, 27) + +/* field: RTL - Design release number. Reads return 0x00, writes have no effect. */ +#define TMS570_DCC_REV_RTL(val) BSP_FLD32(val,11, 15) +#define TMS570_DCC_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15) +#define TMS570_DCC_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15) + +/* field: MAJOR - Major revision number. Reads return 0x2, writes have no effect. */ +#define TMS570_DCC_REV_MAJOR(val) BSP_FLD32(val,8, 10) +#define TMS570_DCC_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_DCC_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: CUSTOM - Custom version number. Reads return 0x0, writes have no effect. */ +#define TMS570_DCC_REV_CUSTOM(val) BSP_FLD32(val,6, 7) +#define TMS570_DCC_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DCC_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: MINOR - Minor revision number. Reads return 0x4, writes have no effect. */ +#define TMS570_DCC_REV_MINOR(val) BSP_FLD32(val,0, 5) +#define TMS570_DCC_REV_MINOR_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DCC_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*--------------------TMS570_DCC_CNT0SEED--------------------*/ +/* field: COUNT0_SEED - Seed value for DCC Counter0. */ +#define TMS570_DCC_CNT0SEED_COUNT0_SEED(val) BSP_FLD32(val,0, 19) +#define TMS570_DCC_CNT0SEED_COUNT0_SEED_GET(reg) BSP_FLD32GET(reg,0, 19) +#define TMS570_DCC_CNT0SEED_COUNT0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) + + +/*-------------------TMS570_DCC_VALID0SEED-------------------*/ +/* field: VALID0_SEED - XXX */ +#define TMS570_DCC_VALID0SEED_VALID0_SEED(val) BSP_FLD32(val,0, 15) +#define TMS570_DCC_VALID0SEED_VALID0_SEED_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DCC_VALID0SEED_VALID0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DCC_CNT1SEED--------------------*/ +/* field: COUNT1_SEED - Seed value for DCC Counter1. */ +#define TMS570_DCC_CNT1SEED_COUNT1_SEED(val) BSP_FLD32(val,0, 19) +#define TMS570_DCC_CNT1SEED_COUNT1_SEED_GET(reg) BSP_FLD32GET(reg,0, 19) +#define TMS570_DCC_CNT1SEED_COUNT1_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) + + +/*----------------------TMS570_DCC_STAT----------------------*/ +/* field: DONE_FLG - Single-Shot Sequence Done flag. */ +#define TMS570_DCC_STAT_DONE_FLG BSP_BIT32(1) + +/* field: ERR_FLG - Error flag. Indicates that a DCC error has occurred. */ +#define TMS570_DCC_STAT_ERR_FLG BSP_BIT32(0) + + +/*----------------------TMS570_DCC_CNT0----------------------*/ +/* field: COUNT0 - Current value of DCC Counter0. */ +#define TMS570_DCC_CNT0_COUNT0(val) BSP_FLD32(val,0, 19) +#define TMS570_DCC_CNT0_COUNT0_GET(reg) BSP_FLD32GET(reg,0, 19) +#define TMS570_DCC_CNT0_COUNT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) + + +/*---------------------TMS570_DCC_VALID0---------------------*/ +/* field: VALID0 - Current value for DCC Valid0. */ +#define TMS570_DCC_VALID0_VALID0(val) BSP_FLD32(val,0, 15) +#define TMS570_DCC_VALID0_VALID0_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DCC_VALID0_VALID0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_DCC_CNT1----------------------*/ +/* field: COUNT1 - Current value for DCC Counter1. */ +#define TMS570_DCC_CNT1_COUNT1(val) BSP_FLD32(val,0, 19) +#define TMS570_DCC_CNT1_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19) +#define TMS570_DCC_CNT1_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) + + +/*-------------------TMS570_DCC_CNT1CLKSRC-------------------*/ +/* field: KEY - Key to enable clock source selection for Counter1. */ +#define TMS570_DCC_CNT1CLKSRC_KEY(val) BSP_FLD32(val,12, 15) +#define TMS570_DCC_CNT1CLKSRC_KEY_GET(reg) BSP_FLD32GET(reg,12, 15) +#define TMS570_DCC_CNT1CLKSRC_KEY_SET(reg,val) BSP_FLD32SET(reg, val,12, 15) + +/* field: CNT1_CLKSRC - Clock Source for Counter1 when KEY is programmed to be 0xA. */ +#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC(val) BSP_FLD32(val,0, 3) +#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_DCC_CNT0CLKSRC-------------------*/ +/* field: CNT0_CLKSRC - Clock Source for Counter0 */ +#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC(val) BSP_FLD32(val,0, 3) +#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + + +#endif /* LIBBSP_ARM_TMS570_DCC */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h new file mode 100644 index 0000000000..717f05b010 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h @@ -0,0 +1,711 @@ +/* The header file is generated by make_header.py from DMA.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_DMA +#define LIBBSP_ARM_TMS570_DMA + +#include + +typedef struct{ + uint32_t STARTADD; /*DMA Memory Protection Region start Address Register*/ + uint32_t ENDADD; /*DMA Memory Protection Region End Address Register*/ +} tms570_memory_prot_t; + +typedef struct{ + uint32_t GCTRL; /*Global Control Register*/ + uint32_t PEND; /*Channel Pending Register*/ + uint8_t reserved1 [4]; + uint32_t DMASTAT; /*DMA Status Register*/ + uint8_t reserved2 [4]; + uint32_t HWCHENAS; /*HW Channel Enable Set and Status Register*/ + uint8_t reserved3 [4]; + uint32_t HWCHENAR; /*HW Channel Enable Reset and Status Register*/ + uint8_t reserved4 [4]; + uint32_t SWCHENAS; /*SW Channel Enable Set and Status Register*/ + uint8_t reserved5 [4]; + uint32_t SWCHENAR; /*SW Channel Enable Reset and Status Register*/ + uint8_t reserved6 [4]; + uint32_t CHPRIOS; /*Channel Priority Set Register*/ + uint8_t reserved7 [4]; + uint32_t CHPRIOR; /*Channel Priority Reset Register*/ + uint8_t reserved8 [4]; + uint32_t GCHIENAS; /*Global Channel Interrupt Enable Set Register*/ + uint8_t reserved9 [4]; + uint32_t GCHIENAR; /*Global Channel Interrupt Enable Reset Register*/ + uint8_t reserved10 [4]; + uint32_t DREQASI[4]; /*DMA Request Assignment Register 0*/ + uint8_t reserved11 [48]; + uint32_t PAR0; /*Port Assignment Register 0*/ + uint32_t PAR1; /*Port Assignment Register 1*/ + uint8_t reserved12 [24]; + uint32_t FTCMAP; /*FTC Interrupt Mapping Register*/ + uint8_t reserved13 [4]; + uint32_t LFSMAP; /*LFS Interrupt Mapping Register*/ + uint8_t reserved14 [4]; + uint32_t HBCMAP; /*HBC Interrupt Mapping Register*/ + uint8_t reserved15 [4]; + uint32_t BTCMAP; /*BTC Interrupt Mapping Register*/ + uint8_t reserved16 [4]; + uint32_t BERMAP; /*BER Interrupt Mapping Register*/ + uint8_t reserved17 [4]; + uint32_t FTCINTENAS; /*FTC Interrupt Enable Set*/ + uint8_t reserved18 [4]; + uint32_t FTCINTENAR; /*FTC Interrupt Enable Reset*/ + uint8_t reserved19 [4]; + uint32_t LFSINTENAS; /*LFS Interrupt Enable Set*/ + uint8_t reserved20 [4]; + uint32_t LFSINTENAR; /*LFS Interrupt Enable Reset*/ + uint8_t reserved21 [4]; + uint32_t HBCINTENAS; /*HBC Interrupt Enable Set*/ + uint8_t reserved22 [4]; + uint32_t HBCINTENAR; /*HBC Interrupt Enable Reset*/ + uint8_t reserved23 [4]; + uint32_t BTCINTENAS; /*BTC Interrupt Enable Set*/ + uint8_t reserved24 [4]; + uint32_t BTCINTENAR; /*BTC Interrupt Enable Reset*/ + uint8_t reserved25 [4]; + uint32_t GINTFLAG; /*Global Interrupt Flag Register*/ + uint8_t reserved26 [4]; + uint32_t FTCFLAG; /*FTC Interrupt Flag Register*/ + uint8_t reserved27 [4]; + uint32_t LFSFLAG; /*LFS Interrupt Flag Register*/ + uint8_t reserved28 [4]; + uint32_t HBCFLAG; /*HBC Interrupt Flag Register*/ + uint8_t reserved29 [4]; + uint32_t BTCFLAG; /*BTC Interrupt Flag Register*/ + uint8_t reserved30 [4]; + uint32_t BERFLAG; /*BER Interrupt Flag Register*/ + uint8_t reserved31 [4]; + uint32_t FTCAOFFSET; /*FTCA Interrupt Channel Offset Register*/ + uint32_t LFSAOFFSET; /*LFSA Interrupt Channel Offset Register*/ + uint32_t HBCAOFFSET; /*HBCA Interrupt Channel Offset Register*/ + uint32_t BTCAOFFSET; /*BTCA Interrupt Channel Offset Register*/ + uint32_t BERAOFFSET; /*BERA Interrupt Channel Offset Register*/ + uint32_t FTCBOFFSET; /*FTCB Interrupt Channel Offset Register*/ + uint32_t LFSBOFFSET; /*LFSB Interrupt Channel Offset Register*/ + uint32_t HBCBOFFSET; /*HBCB Interrupt Channel Offset Register*/ + uint32_t BTCBOFFSET; /*BTCB Interrupt Channel Offset Register*/ + uint32_t BERBOFFSET; /*BERB Interrupt Channel Offset Register*/ + uint8_t reserved32 [4]; + uint32_t PTCRL; /*Port Control Register*/ + uint32_t RTCTRL; /*RAM Test Control Register*/ + uint32_t DCTRL; /*Debug Control*/ + uint32_t WPR; /*Watch Point Register*/ + uint32_t WMR; /*Watch Mask Register*/ + uint8_t reserved33 [12]; + uint32_t PBACSADDR; /*Port B Active Channel Source Address Register*/ + uint32_t PBACDADDR; /*Port B Active Channel Destination Address Register*/ + uint32_t PBACTC; /*Port B Active Channel Transfer Count Register*/ + uint8_t reserved34 [4]; + uint32_t DMAPCR; /*Parity Control Register*/ + uint32_t DMAPAR; /*DMA Parity Error Address Register*/ + uint32_t DMAMPCTRL; /*DMA Memory Protection Control Register*/ + uint32_t DMAMPST; /*DMA Memory Protection Status Register*/ + tms570_memory_prot_t DMAMPROS[4];/*DMA Memory Protection Regions*/ +} tms570_dma_t; + + +/*--------------------TMS570_DMA_STARTADD--------------------*/ +/* field: STARTADDRESS - Start Address defines the address at which the region begins. */ +/* Whole 32 bits */ + +/*---------------------TMS570_DMA_ENDADD---------------------*/ +/* field: ENDADDRESS - End Address defines the address at which the region ends. */ +/* Whole 32 bits */ + +/*----------------------TMS570_DMA_GCTRL----------------------*/ +/* field: DMA_EN - DMA enable bit. */ +#define TMS570_DMA_GCTRL_DMA_EN BSP_BIT32(16) + +/* field: BUS_BUSY - This bit indicates status of DMA external AHB bus status. */ +#define TMS570_DMA_GCTRL_BUS_BUSY BSP_BIT32(14) + +/* field: DEBUG_MODE - Debug Mode. */ +#define TMS570_DMA_GCTRL_DEBUG_MODE(val) BSP_FLD32(val,8, 9) +#define TMS570_DMA_GCTRL_DEBUG_MODE_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_DMA_GCTRL_DEBUG_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: DMA_RES - DMA software reset */ +#define TMS570_DMA_GCTRL_DMA_RES BSP_BIT32(0) + + +/*----------------------TMS570_DMA_PEND----------------------*/ +/* field: PEND - Channel pending register. */ +#define TMS570_DMA_PEND_PEND(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_PEND_PEND_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_PEND_PEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_DMASTAT---------------------*/ +/* field: STCH - Status of DMA channels. */ +#define TMS570_DMA_DMASTAT_STCH(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_DMASTAT_STCH_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_DMASTAT_STCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_HWCHENAS--------------------*/ +/* field: HWCHENA - Hardware channel enable bit. */ +#define TMS570_DMA_HWCHENAS_HWCHENA(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_HWCHENAS_HWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_HWCHENAS_HWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_HWCHENAR--------------------*/ +/* field: HWCHDIS - HW channel disable bit. */ +#define TMS570_DMA_HWCHENAR_HWCHDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_HWCHENAR_HWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_HWCHENAR_HWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_SWCHENAS--------------------*/ +/* field: SWCHENA - SW channel enable bit. */ +#define TMS570_DMA_SWCHENAS_SWCHENA(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_SWCHENAS_SWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_SWCHENAS_SWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_SWCHENAR--------------------*/ +/* field: SWCHDIS - SW channel disable bit. */ +#define TMS570_DMA_SWCHENAR_SWCHDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_SWCHENAR_SWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_SWCHENAR_SWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_CHPRIOS---------------------*/ +/* field: CPS - Channel priority set bit. */ +#define TMS570_DMA_CHPRIOS_CPS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_CHPRIOS_CPS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_CHPRIOS_CPS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_CHPRIOR---------------------*/ +/* field: CPR - Channel priority reset bit. */ +#define TMS570_DMA_CHPRIOR_CPR(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_CHPRIOR_CPR_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_CHPRIOR_CPR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_GCHIENAS--------------------*/ +/* field: GCHIE - Global channel interrupt enable bit. */ +#define TMS570_DMA_GCHIENAS_GCHIE(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_GCHIENAS_GCHIE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_GCHIENAS_GCHIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_GCHIENAR--------------------*/ +/* field: GCHID - Global channel interrupt disable bit. */ +#define TMS570_DMA_GCHIENAR_GCHID(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_GCHIENAR_GCHID_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_GCHIENAR_GCHID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_DREQASI---------------------*/ +/* field: CH0ASI - Channel 0 assignment. This bit field chooses the DMA request assignment for channel 0. */ +#define TMS570_DMA_DREQASI_CH0ASI(val) BSP_FLD32(val,24, 29) +#define TMS570_DMA_DREQASI_CH0ASI_GET(reg) BSP_FLD32GET(reg,24, 29) +#define TMS570_DMA_DREQASI_CH0ASI_SET(reg,val) BSP_FLD32SET(reg, val,24, 29) + +/* field: CH1ASI - Channel 1 assignment. This bit field chooses the DMA request assignment for channel 1. */ +#define TMS570_DMA_DREQASI_CH1ASI(val) BSP_FLD32(val,16, 21) +#define TMS570_DMA_DREQASI_CH1ASI_GET(reg) BSP_FLD32GET(reg,16, 21) +#define TMS570_DMA_DREQASI_CH1ASI_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) + +/* field: CH2ASI - Channel 2 assignment. This bit field chooses the DMA request assignment for channel 2. */ +#define TMS570_DMA_DREQASI_CH2ASI(val) BSP_FLD32(val,8, 13) +#define TMS570_DMA_DREQASI_CH2ASI_GET(reg) BSP_FLD32GET(reg,8, 13) +#define TMS570_DMA_DREQASI_CH2ASI_SET(reg,val) BSP_FLD32SET(reg, val,8, 13) + +/* field: CH3ASI - Channel 3 assignment. This bit field chooses the DMA request assignment for channel 3. */ +#define TMS570_DMA_DREQASI_CH3ASI(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_DREQASI_CH3ASI_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_DREQASI_CH3ASI_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_DMA_PAR0----------------------*/ +/* field: CH0PA - These bit fields determine to which port channel 0 is assigned. */ +#define TMS570_DMA_PAR0_CH0PA(val) BSP_FLD32(val,28, 30) +#define TMS570_DMA_PAR0_CH0PA_GET(reg) BSP_FLD32GET(reg,28, 30) +#define TMS570_DMA_PAR0_CH0PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30) + +/* field: CH1PA - These bit fields determine to which port channel 1 is assigned. */ +#define TMS570_DMA_PAR0_CH1PA(val) BSP_FLD32(val,24, 26) +#define TMS570_DMA_PAR0_CH1PA_GET(reg) BSP_FLD32GET(reg,24, 26) +#define TMS570_DMA_PAR0_CH1PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26) + +/* field: CH2PA - These bit fields determine to which port channel 2 is assigned. */ +#define TMS570_DMA_PAR0_CH2PA(val) BSP_FLD32(val,20, 22) +#define TMS570_DMA_PAR0_CH2PA_GET(reg) BSP_FLD32GET(reg,20, 22) +#define TMS570_DMA_PAR0_CH2PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22) + +/* field: CH3PA - These bit fields determine to which port channel 3 is assigned. */ +#define TMS570_DMA_PAR0_CH3PA(val) BSP_FLD32(val,16, 18) +#define TMS570_DMA_PAR0_CH3PA_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_DMA_PAR0_CH3PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: CH4PA - These bit fields determine to which port channel 4 is assigned. */ +#define TMS570_DMA_PAR0_CH4PA(val) BSP_FLD32(val,12, 14) +#define TMS570_DMA_PAR0_CH4PA_GET(reg) BSP_FLD32GET(reg,12, 14) +#define TMS570_DMA_PAR0_CH4PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14) + +/* field: CH5PA - These bit fields determine to which port channel 5 is assigned. */ +#define TMS570_DMA_PAR0_CH5PA(val) BSP_FLD32(val,8, 10) +#define TMS570_DMA_PAR0_CH5PA_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_DMA_PAR0_CH5PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: CH6PA - These bit fields determine to which port channel 6 is assigned. */ +#define TMS570_DMA_PAR0_CH6PA(val) BSP_FLD32(val,4, 6) +#define TMS570_DMA_PAR0_CH6PA_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_DMA_PAR0_CH6PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: CH7PA - These bit fields determine to which port channel 7 is assigned. */ +#define TMS570_DMA_PAR0_CH7PA(val) BSP_FLD32(val,0, 2) +#define TMS570_DMA_PAR0_CH7PA_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_DMA_PAR0_CH7PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*----------------------TMS570_DMA_PAR1----------------------*/ +/* field: CH8PA - These bit fields determine to which port channel 8 is assigned. */ +#define TMS570_DMA_PAR1_CH8PA(val) BSP_FLD32(val,28, 30) +#define TMS570_DMA_PAR1_CH8PA_GET(reg) BSP_FLD32GET(reg,28, 30) +#define TMS570_DMA_PAR1_CH8PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30) + +/* field: CH9PA - These bit fields determine to which port channel 9 is assigned. */ +#define TMS570_DMA_PAR1_CH9PA(val) BSP_FLD32(val,24, 26) +#define TMS570_DMA_PAR1_CH9PA_GET(reg) BSP_FLD32GET(reg,24, 26) +#define TMS570_DMA_PAR1_CH9PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26) + +/* field: CH10PA - These bit fields determine to which port channel 10 is assigned. */ +#define TMS570_DMA_PAR1_CH10PA(val) BSP_FLD32(val,20, 22) +#define TMS570_DMA_PAR1_CH10PA_GET(reg) BSP_FLD32GET(reg,20, 22) +#define TMS570_DMA_PAR1_CH10PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22) + +/* field: CH11PA - These bit fields determine to which port channel 11 is assigned. */ +#define TMS570_DMA_PAR1_CH11PA(val) BSP_FLD32(val,16, 18) +#define TMS570_DMA_PAR1_CH11PA_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_DMA_PAR1_CH11PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: CH12PA - These bit fields determine to which port channel 12 is assigned. */ +#define TMS570_DMA_PAR1_CH12PA(val) BSP_FLD32(val,12, 14) +#define TMS570_DMA_PAR1_CH12PA_GET(reg) BSP_FLD32GET(reg,12, 14) +#define TMS570_DMA_PAR1_CH12PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14) + +/* field: CH13PA - These bit fields determine to which port channel 13 is assigned. */ +#define TMS570_DMA_PAR1_CH13PA(val) BSP_FLD32(val,8, 10) +#define TMS570_DMA_PAR1_CH13PA_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_DMA_PAR1_CH13PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: CH14PA - These bit fields determine to which port channel 14 is assigned. */ +#define TMS570_DMA_PAR1_CH14PA(val) BSP_FLD32(val,4, 6) +#define TMS570_DMA_PAR1_CH14PA_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_DMA_PAR1_CH14PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: CH15PA - These bit fields determine to which port channel 15 is assigned. */ +#define TMS570_DMA_PAR1_CH15PA(val) BSP_FLD32(val,0, 2) +#define TMS570_DMA_PAR1_CH15PA_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_DMA_PAR1_CH15PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*---------------------TMS570_DMA_FTCMAP---------------------*/ +/* field: FTCAB - Frame transfer complete (FTC) interrupt to Group A or Group B. */ +#define TMS570_DMA_FTCMAP_FTCAB(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_FTCMAP_FTCAB_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_FTCMAP_FTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_LFSMAP---------------------*/ +/* field: LFSAB - Last frame started (LFS) interrupt to Group A or Group B. */ +#define TMS570_DMA_LFSMAP_LFSAB(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_LFSMAP_LFSAB_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_LFSMAP_LFSAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_HBCMAP---------------------*/ +/* field: HBCAB - Half block complete (HBC) interrupt to Group A or Group B. */ +#define TMS570_DMA_HBCMAP_HBCAB(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_HBCMAP_HBCAB_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_HBCMAP_HBCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_BTCMAP---------------------*/ +/* field: BTCAB - Block transfer complete (BTC) interrupt to Group A or Group B */ +#define TMS570_DMA_BTCMAP_BTCAB(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_BTCMAP_BTCAB_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_BTCMAP_BTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_BERMAP---------------------*/ +/* field: BERAB - Bus error (BER) interrupt to Group A or Group B. */ +#define TMS570_DMA_BERMAP_BERAB(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_BERMAP_BERAB_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_BERMAP_BERAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_FTCINTENAS-------------------*/ +/* field: FTCINTENA - Frame transfer complete (FTC) interrupt enable. */ +#define TMS570_DMA_FTCINTENAS_FTCINTENA(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_FTCINTENAS_FTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_FTCINTENAS_FTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_FTCINTENAR-------------------*/ +/* field: FTCINTDIS - Frame transfer complete (FTC) interrupt disable. */ +#define TMS570_DMA_FTCINTENAR_FTCINTDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_FTCINTENAR_FTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_FTCINTENAR_FTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_LFSINTENAS-------------------*/ +/* field: LFSINTENA - Last frame started (LFS) interrupt enable. */ +#define TMS570_DMA_LFSINTENAS_LFSINTENA(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_LFSINTENAS_LFSINTENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_LFSINTENAS_LFSINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_LFSINTENAR-------------------*/ +/* field: LFSINTDIS - Last frame started (LFS) interrupt disable. */ +#define TMS570_DMA_LFSINTENAR_LFSINTDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_LFSINTENAR_LFSINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_LFSINTENAR_LFSINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_HBCINTENAS-------------------*/ +/* field: HBCINTENA - Half block complete (HBC) interrupt enable. */ +#define TMS570_DMA_HBCINTENAS_HBCINTENA(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_HBCINTENAS_HBCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_HBCINTENAS_HBCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_HBCINTENAR-------------------*/ +/* field: HBCINTDIS - Half block complete (HBC) interrupt disable. */ +#define TMS570_DMA_HBCINTENAR_HBCINTDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_HBCINTENAR_HBCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_HBCINTENAR_HBCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_BTCINTENAS-------------------*/ +/* field: BTCINTENA - Block transfer complete (BTC) interrupt enable. */ +#define TMS570_DMA_BTCINTENAS_BTCINTENA(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_BTCINTENAS_BTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_BTCINTENAS_BTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_BTCINTENAR-------------------*/ +/* field: BTCINTDIS - Block transfer complete (BTC) interurpt disable. */ +#define TMS570_DMA_BTCINTENAR_BTCINTDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_BTCINTENAR_BTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_BTCINTENAR_BTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_GINTFLAG--------------------*/ +/* field: GINT - Global interrupt flags. */ +#define TMS570_DMA_GINTFLAG_GINT(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_GINTFLAG_GINT_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_GINTFLAG_GINT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_FTCFLAG---------------------*/ +/* field: FTCI - Frame transfer complete (FTC) flags. */ +#define TMS570_DMA_FTCFLAG_FTCI(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_FTCFLAG_FTCI_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_FTCFLAG_FTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_LFSFLAG---------------------*/ +/* field: LFSI - Last frame started (LFS) flags. */ +#define TMS570_DMA_LFSFLAG_LFSI(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_LFSFLAG_LFSI_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_LFSFLAG_LFSI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_HBCFLAG---------------------*/ +/* field: HBCI - Half block transfer (HBC) complete flags. */ +#define TMS570_DMA_HBCFLAG_HBCI(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_HBCFLAG_HBCI_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_HBCFLAG_HBCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_BTCFLAG---------------------*/ +/* field: BTCI - Block transfer complete (BTC) flags. */ +#define TMS570_DMA_BTCFLAG_BTCI(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_BTCFLAG_BTCI_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_BTCFLAG_BTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_BERFLAG---------------------*/ +/* field: BERI - Bus error (BER) flags. */ +#define TMS570_DMA_BERFLAG_BERI(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_BERFLAG_BERI_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_BERFLAG_BERI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_FTCAOFFSET-------------------*/ +/* field: sbz - These bits should always be programmed as zero. */ +#define TMS570_DMA_FTCAOFFSET_sbz(val) BSP_FLD32(val,6, 7) +#define TMS570_DMA_FTCAOFFSET_sbz_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DMA_FTCAOFFSET_sbz_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: FTCA - Channel causing FTC interrupt Group A. */ +#define TMS570_DMA_FTCAOFFSET_FTCA(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_FTCAOFFSET_FTCA_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_FTCAOFFSET_FTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_LFSAOFFSET-------------------*/ +/* field: LFSA - Channel causing LFS interrupt Group A. */ +#define TMS570_DMA_LFSAOFFSET_LFSA(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_LFSAOFFSET_LFSA_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_LFSAOFFSET_LFSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_HBCAOFFSET-------------------*/ +/* field: HBCA - Channel causing HBC interrupt Group A. */ +#define TMS570_DMA_HBCAOFFSET_HBCA(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_HBCAOFFSET_HBCA_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_HBCAOFFSET_HBCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_BTCAOFFSET-------------------*/ +/* field: BTCA - Channel causing BTC interrupt Group A. */ +#define TMS570_DMA_BTCAOFFSET_BTCA(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_BTCAOFFSET_BTCA_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_BTCAOFFSET_BTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_BERAOFFSET-------------------*/ +/* field: BERA - Channel causing BER interrupt Group A. */ +#define TMS570_DMA_BERAOFFSET_BERA(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_BERAOFFSET_BERA_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_BERAOFFSET_BERA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_FTCBOFFSET-------------------*/ +/* field: FTCB - Channel causing FTC interrupt Group B. */ +#define TMS570_DMA_FTCBOFFSET_FTCB(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_FTCBOFFSET_FTCB_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_FTCBOFFSET_FTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_LFSBOFFSET-------------------*/ +/* field: LFSB - Channel causing LFS interrupt Group B. */ +#define TMS570_DMA_LFSBOFFSET_LFSB(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_LFSBOFFSET_LFSB_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_LFSBOFFSET_LFSB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_HBCBOFFSET-------------------*/ +/* field: HBCB - Channel causing HBC interrupt Group B. */ +#define TMS570_DMA_HBCBOFFSET_HBCB(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_HBCBOFFSET_HBCB_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_HBCBOFFSET_HBCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_BTCBOFFSET-------------------*/ +/* field: BTCB - interrupt for Group B if the corresponding interrupt enable is set. */ +#define TMS570_DMA_BTCBOFFSET_BTCB(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_BTCBOFFSET_BTCB_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_BTCBOFFSET_BTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_BERBOFFSET-------------------*/ +/* field: BERB - Channel causing BER interrupt Group B. */ +#define TMS570_DMA_BERBOFFSET_BERB(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_BERBOFFSET_BERB_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_BERBOFFSET_BERB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_DMA_PTCRL----------------------*/ +/* field: PENDB - Transfers pending for Port B. This flag determines if transfers are ongoing on port B. */ +#define TMS570_DMA_PTCRL_PENDB BSP_BIT32(24) + +/* field: BYB - Bypass FIFO B. */ +#define TMS570_DMA_PTCRL_BYB BSP_BIT32(18) + +/* field: PSFRHQPB - Priority scheme fix or rotate for high priority queue of Port B. */ +#define TMS570_DMA_PTCRL_PSFRHQPB BSP_BIT32(17) + +/* field: PSFRLQPB - Priority scheme fix or rotate for low priority queue of Port B. */ +#define TMS570_DMA_PTCRL_PSFRLQPB BSP_BIT32(16) + + +/*---------------------TMS570_DMA_RTCTRL---------------------*/ +/* field: RTC - RAM Test Control. */ +#define TMS570_DMA_RTCTRL_RTC BSP_BIT32(0) + + +/*----------------------TMS570_DMA_DCTRL----------------------*/ +/* field: CHNUM - Channel Number. */ +#define TMS570_DMA_DCTRL_CHNUM(val) BSP_FLD32(val,24, 28) +#define TMS570_DMA_DCTRL_CHNUM_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_DMA_DCTRL_CHNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: DMADBGS - DMA debug status. */ +#define TMS570_DMA_DCTRL_DMADBGS BSP_BIT32(16) + +/* field: DBGEN - Debug Enable. */ +#define TMS570_DMA_DCTRL_DBGEN BSP_BIT32(0) + + +/*-----------------------TMS570_DMA_WPR-----------------------*/ +/* field: WP - Watch point. */ +/* Whole 32 bits */ + +/*-----------------------TMS570_DMA_WMR-----------------------*/ +/* field: WM - Watch mask. */ +/* Whole 32 bits */ + +/*--------------------TMS570_DMA_PBACSADDR--------------------*/ +/* field: PBACSA - Port B Active Channel Source Address. */ +/* Whole 32 bits */ + +/*--------------------TMS570_DMA_PBACDADDR--------------------*/ +/* field: PBACDA - address of the active channel as broadcasted in Section 16.3.1.3 for Port B. */ +/* Whole 32 bits */ + +/*---------------------TMS570_DMA_PBACTC---------------------*/ +/* field: PBFTCOUNT - Port B active channel frame count. */ +#define TMS570_DMA_PBACTC_PBFTCOUNT(val) BSP_FLD32(val,16, 28) +#define TMS570_DMA_PBACTC_PBFTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 28) +#define TMS570_DMA_PBACTC_PBFTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 28) + +/* field: PBETCOUNT - Port B active channel element count. */ +#define TMS570_DMA_PBACTC_PBETCOUNT(val) BSP_FLD32(val,0, 12) +#define TMS570_DMA_PBACTC_PBETCOUNT_GET(reg) BSP_FLD32GET(reg,0, 12) +#define TMS570_DMA_PBACTC_PBETCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 12) + + +/*---------------------TMS570_DMA_DMAPCR---------------------*/ +/* field: ERRA - Error action. */ +#define TMS570_DMA_DMAPCR_ERRA BSP_BIT32(16) + +/* field: TEST - When this bit is set, the parity bits are memory mapped to make them accessible by the CPU. */ +#define TMS570_DMA_DMAPCR_TEST BSP_BIT32(8) + +/* field: PARITY_ENA - Parity error detection enable. */ +#define TMS570_DMA_DMAPCR_PARITY_ENA(val) BSP_FLD32(val,0, 3) +#define TMS570_DMA_DMAPCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DMA_DMAPCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_DMA_DMAPAR---------------------*/ +/* field: EDFLAG - Parity Error Detection Flag. */ +#define TMS570_DMA_DMAPAR_EDFLAG BSP_BIT32(24) + +/* field: ERRORADDRESS - Error address. These bits hold the address of the first parity error generated in the RAM. */ +#define TMS570_DMA_DMAPAR_ERRORADDRESS(val) BSP_FLD32(val,0, 11) +#define TMS570_DMA_DMAPAR_ERRORADDRESS_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_DMA_DMAPAR_ERRORADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*--------------------TMS570_DMA_DMAMPCTRL--------------------*/ +/* field: INT3AB - Interrupt assignment of region 3 to Group A or Group B. */ +#define TMS570_DMA_DMAMPCTRL_INT3AB BSP_BIT32(28) + +/* field: INT3ENA - Interrupt enable of region 3. */ +#define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_BIT32(27) + +/* field: REG3AP - Region 3 access permission. */ +#define TMS570_DMA_DMAMPCTRL_REG3AP(val) BSP_FLD32(val,25, 26) +#define TMS570_DMA_DMAMPCTRL_REG3AP_GET(reg) BSP_FLD32GET(reg,25, 26) +#define TMS570_DMA_DMAMPCTRL_REG3AP_SET(reg,val) BSP_FLD32SET(reg, val,25, 26) + +/* field: REG3ENA - Region 3 enable. */ +#define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_BIT32(24) + +/* field: INT2AB - Interrupt assignment of region 2 to Group A or Group B. */ +#define TMS570_DMA_DMAMPCTRL_INT2AB BSP_BIT32(20) + +/* field: INT2ENA - Interrupt enable of region 2. */ +#define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_BIT32(19) + +/* field: REG2AP - Region 2 access permission. These bits determine the access permission for region 2. */ +#define TMS570_DMA_DMAMPCTRL_REG2AP(val) BSP_FLD32(val,17, 18) +#define TMS570_DMA_DMAMPCTRL_REG2AP_GET(reg) BSP_FLD32GET(reg,17, 18) +#define TMS570_DMA_DMAMPCTRL_REG2AP_SET(reg,val) BSP_FLD32SET(reg, val,17, 18) + +/* field: REG2ENA - Region 2 enable. */ +#define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_BIT32(16) + +/* field: INT1AB - Interrupt assignment of region 1 to Group A or Group B. */ +#define TMS570_DMA_DMAMPCTRL_INT1AB BSP_BIT32(12) + +/* field: INT1ENA - Interrupt enable of region 1. */ +#define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_BIT32(11) + +/* field: REG1AP - Region 1 access permission. */ +#define TMS570_DMA_DMAMPCTRL_REG1AP(val) BSP_FLD32(val,9, 10) +#define TMS570_DMA_DMAMPCTRL_REG1AP_GET(reg) BSP_FLD32GET(reg,9, 10) +#define TMS570_DMA_DMAMPCTRL_REG1AP_SET(reg,val) BSP_FLD32SET(reg, val,9, 10) + +/* field: REG1ENA - Region 1 enable. */ +#define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_BIT32(8) + +/* field: INT0AB - Interrupt assignment of region 0 to Group A or Group B. */ +#define TMS570_DMA_DMAMPCTRL_INT0AB BSP_BIT32(4) + +/* field: INT0ENA - Interrupt enable of region 0. */ +#define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_BIT32(3) + +/* field: REG0AP - Region 0 access permission. These bits determine the access permission for region 0. */ +#define TMS570_DMA_DMAMPCTRL_REG0AP(val) BSP_FLD32(val,1, 2) +#define TMS570_DMA_DMAMPCTRL_REG0AP_GET(reg) BSP_FLD32GET(reg,1, 2) +#define TMS570_DMA_DMAMPCTRL_REG0AP_SET(reg,val) BSP_FLD32SET(reg, val,1, 2) + +/* field: REG0ENA - Region 0 enable. */ +#define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_BIT32(0) + + +/*---------------------TMS570_DMA_DMAMPST---------------------*/ +/* field: REG3FT - Region 3 fault. */ +#define TMS570_DMA_DMAMPST_REG3FT BSP_BIT32(24) + +/* field: REG2FT - Region 2 fault. */ +#define TMS570_DMA_DMAMPST_REG2FT BSP_BIT32(16) + +/* field: REG1FT - Region 1 fault. */ +#define TMS570_DMA_DMAMPST_REG1FT BSP_BIT32(8) + +/* field: REG0FT - Region 0 fault. */ +#define TMS570_DMA_DMAMPST_REG0FT BSP_BIT32(0) + + +/*--------------------TMS570_DMA_DMAMPROS--------------------*/ +/* field: STARTADDRESS - Start Address defines the address at which the region begins. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_DMA */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h new file mode 100644 index 0000000000..55d656ef86 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h @@ -0,0 +1,557 @@ +/* The header file is generated by make_header.py from DMM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_DMM +#define LIBBSP_ARM_TMS570_DMM + +#include + +typedef struct{ + uint32_t GLBCTRL; /*DMM Global Control Register*/ + uint32_t INTSET; /*DMM Interrupt Set Register*/ + uint32_t INTCLR; /*DMM Interrupt Clear Register*/ + uint32_t INTLVL; /*DMM Interrupt Level Register*/ + uint32_t INTFLG; /*DMM Interrupt Flag Register*/ + uint32_t OFF1; /*DMM Interrupt Offset 1 Register*/ + uint32_t OFF2; /*DMM Interrupt Offset 2 Register*/ + uint32_t DDMDEST; /*DMM Direct Data Mode Destination Register*/ + uint32_t DDMBL; /*DMM Direct Data Mode Blocksize Register*/ + uint32_t DDMPT; /*DMM Direct Data Mode Pointer Register*/ + uint32_t INTPT; /*DMM Direct Data Mode Interrupt Pointer Register*/ + uint32_t DEST0REG1; /*DMM Destination 0 Region 1*/ + uint32_t DEST0BL1; /*DMM Destination 0 Blocksize 1*/ + uint32_t DEST0REG2; /*DMM Destination 0 Region 2*/ + uint32_t DEST0BL2; /*DMM Destination 0 Blocksize 2*/ + uint32_t DEST1REG1; /*DMM Destination 1 Region 1*/ + uint32_t DEST1BL1; /*DMM Destination 1 Blocksize 1*/ + uint32_t DEST1REG2; /*DMM Destination 1 Region 2*/ + uint32_t DEST1BL2; /*DMM Destination 1 Blocksize 2*/ + uint32_t DEST2REG1; /*DMM Destination 2 Region 1*/ + uint32_t DEST2BL1; /*DMM Destination 2 Blocksize 1*/ + uint32_t DEST2REG2; /*DMM Destination 2 Region 2*/ + uint32_t DEST2BL2; /*DMM Destination 2 Blocksize 2*/ + uint32_t DEST3REG1; /*DMM Destination 3 Region 1*/ + uint32_t DEST3BL1; /*DMM Destination 3 Blocksize 1*/ + uint32_t DEST3REG2; /*DMM Destination 3 Region 2*/ + uint32_t DEST3BL2; /*DMM Destination 3 Blocksize 2*/ + uint32_t PC0; /*DMM Pin Control 0*/ + uint32_t PC1; /*DMM Pin Control 1*/ + uint32_t PC2; /*DMM Pin Control 2*/ + uint32_t PC3; /*DMM Pin Control 3*/ + uint32_t PC4; /*DMM Pin Control 4*/ + uint32_t PC5; /*DMM Pin Control 5*/ + uint32_t PC6; /*DMM Pin Control 6*/ + uint32_t PC7; /*DMM Pin Control 7*/ + uint32_t PC8; /*DMM Pin Control 8*/ +} tms570_dmm_t; + + +/*---------------------TMS570_DMM_GLBCTRL---------------------*/ +/* field: BUSY - Busy indicator. */ +#define TMS570_DMM_GLBCTRL_BUSY BSP_BIT32(24) + +/* field: CONTCLK - Continuous DMMCLK input. */ +#define TMS570_DMM_GLBCTRL_CONTCLK BSP_BIT32(18) + +/* field: COS - Continue on suspend. Influences behavior of module while in debug mode. */ +#define TMS570_DMM_GLBCTRL_COS BSP_BIT32(17) + +/* field: RESET - Reset. */ +#define TMS570_DMM_GLBCTRL_RESET BSP_BIT32(16) + +/* field: DDM_WIDTH - Packet Width in direct data mode. */ +#define TMS570_DMM_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,9, 10) +#define TMS570_DMM_GLBCTRL_DDM_WIDTH_GET(reg) BSP_FLD32GET(reg,9, 10) +#define TMS570_DMM_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,9, 10) + +/* field: TM_DMM - Packet Format. */ +#define TMS570_DMM_GLBCTRL_TM_DMM BSP_BIT32(8) + +/* field: ON_OFF - Switch module on or off */ +#define TMS570_DMM_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3) +#define TMS570_DMM_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DMM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_DMM_INTSET---------------------*/ +/* field: PROG_BUFF - Programmable Buffer Interrupt Set. */ +#define TMS570_DMM_INTSET_PROG_BUFF BSP_BIT32(17) + +/* field: EO_BUFF - EO_BUFF */ +#define TMS570_DMM_INTSET_EO_BUFF BSP_BIT32(16) + +/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST3REG2 BSP_BIT32(15) + +/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST3REG1 BSP_BIT32(14) + +/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST2REG2 BSP_BIT32(13) + +/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST2REG1 BSP_BIT32(12) + +/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST1REG2 BSP_BIT32(11) + +/* field: DEST1REG1 - DEST1REG1 */ +#define TMS570_DMM_INTSET_DEST1REG1 BSP_BIT32(10) + +/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST0REG2 BSP_BIT32(9) + +/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST0REG1 BSP_BIT32(8) + +/* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */ +#define TMS570_DMM_INTSET_BUSERROR BSP_BIT32(7) + +/* field: BUFF_OVF - Buffer Overflow. */ +#define TMS570_DMM_INTSET_BUFF_OVF BSP_BIT32(6) + +/* field: SRC_OVF - Source Overflow. */ +#define TMS570_DMM_INTSET_SRC_OVF BSP_BIT32(5) + +/* field: DEST3_ERR - Destination 3 Error. */ +#define TMS570_DMM_INTSET_DEST3_ERR BSP_BIT32(4) + +/* field: DEST2_ERR - Destination 2 Error Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST2_ERR BSP_BIT32(3) + +/* field: DEST1_ERR - Destination 1 Error Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST1_ERR BSP_BIT32(2) + +/* field: DEST0_ERR - Destination 0 Error Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST0_ERR BSP_BIT32(1) + +/* field: PACKET_ERR_INT - Packet Error. */ +#define TMS570_DMM_INTSET_PACKET_ERR_INT BSP_BIT32(0) + + +/*---------------------TMS570_DMM_INTCLR---------------------*/ +/* field: PROG_BUFF - Programmable Buffer Interrupt Set. */ +#define TMS570_DMM_INTCLR_PROG_BUFF BSP_BIT32(17) + +/* field: EO_BUFF - End of Buffer Interrupt Set. */ +#define TMS570_DMM_INTCLR_EO_BUFF BSP_BIT32(16) + +/* field: DEST3REG2 - was accessed at the startaddress of Destination 3 Region 2. */ +#define TMS570_DMM_INTCLR_DEST3REG2 BSP_BIT32(15) + +/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST3REG1 BSP_BIT32(14) + +/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST2REG2 BSP_BIT32(13) + +/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST2REG1 BSP_BIT32(12) + +/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST1REG2 BSP_BIT32(11) + +/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST1REG1 BSP_BIT32(10) + +/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST0REG2 BSP_BIT32(9) + +/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST0REG1 BSP_BIT32(8) + +/* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */ +#define TMS570_DMM_INTCLR_BUSERROR BSP_BIT32(7) + +/* field: BUFF_OVF - Buffer Overflow. */ +#define TMS570_DMM_INTCLR_BUFF_OVF BSP_BIT32(6) + +/* field: SRC_OVF - Source Overflow. */ +#define TMS570_DMM_INTCLR_SRC_OVF BSP_BIT32(5) + +/* field: DEST3_ERR - Destination 3 Error. */ +#define TMS570_DMM_INTCLR_DEST3_ERR BSP_BIT32(4) + +/* field: DEST2_ERR - Destination 2 Error Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST2_ERR BSP_BIT32(3) + +/* field: DEST1_ERR - Destination 1 Error Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST1_ERR BSP_BIT32(2) + +/* field: DEST0_ERR - Destination 0 Error Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST0_ERR BSP_BIT32(1) + +/* field: PACKET_ERR_INT - Packet Error. */ +#define TMS570_DMM_INTCLR_PACKET_ERR_INT BSP_BIT32(0) + + +/*---------------------TMS570_DMM_INTLVL---------------------*/ +/* field: PROG_BUFF - Programmable Buffer Interrupt Level */ +#define TMS570_DMM_INTLVL_PROG_BUFF BSP_BIT32(17) + +/* field: EO_BUFF - End of Buffer Interrupt Level */ +#define TMS570_DMM_INTLVL_EO_BUFF BSP_BIT32(16) + +/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST3REG2 BSP_BIT32(15) + +/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST3REG1 BSP_BIT32(14) + +/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST2REG2 BSP_BIT32(13) + +/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST2REG1 BSP_BIT32(12) + +/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST1REG2 BSP_BIT32(11) + +/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST1REG1 BSP_BIT32(10) + +/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST0REG2 BSP_BIT32(9) + +/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST0REG1 BSP_BIT32(8) + +/* field: BUSERROR - BMM Bus Error Response */ +#define TMS570_DMM_INTLVL_BUSERROR BSP_BIT32(7) + +/* field: BUFF_OVF - Write Buffer Overflow Interrupt Level */ +#define TMS570_DMM_INTLVL_BUFF_OVF BSP_BIT32(6) + +/* field: SRC_OVF - Source Overflow Interrupt Level */ +#define TMS570_DMM_INTLVL_SRC_OVF BSP_BIT32(5) + +/* field: DEST3_ERR - Destination 3 Error Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST3_ERR BSP_BIT32(4) + +/* field: DEST2_ERR - Destination 2 Error Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST2_ERR BSP_BIT32(3) + +/* field: DEST1_ERR - Destination 1 Error Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST1_ERR BSP_BIT32(2) + +/* field: DEST0_ERR - Destination 0 Error Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST0_ERR BSP_BIT32(1) + +/* field: PACKET_ERR_INT - Packet Error Interrupt Level */ +#define TMS570_DMM_INTLVL_PACKET_ERR_INT BSP_BIT32(0) + + +/*---------------------TMS570_DMM_INTFLG---------------------*/ +/* field: PROG_BUFF - Programmable Buffer Interrupt Flag */ +#define TMS570_DMM_INTFLG_PROG_BUFF BSP_BIT32(17) + +/* field: EO_BUFF - End of Buffer Interrupt Flag */ +#define TMS570_DMM_INTFLG_EO_BUFF BSP_BIT32(16) + +/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST3REG2 BSP_BIT32(15) + +/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST3REG1 BSP_BIT32(14) + +/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST2REG2 BSP_BIT32(13) + +/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST2REG1 BSP_BIT32(12) + +/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST1REG2 BSP_BIT32(11) + +/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST1REG1 BSP_BIT32(10) + +/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST0REG2 BSP_BIT32(9) + +/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST0REG1 BSP_BIT32(8) + +/* field: BUSERROR - BMM Bus Error Response. */ +#define TMS570_DMM_INTFLG_BUSERROR BSP_BIT32(7) + +/* field: BUFF_OVF - Write Buffer Overflow Interrupt Flag */ +#define TMS570_DMM_INTFLG_BUFF_OVF BSP_BIT32(6) + +/* field: SRC_OVF - Source Overflow Interrupt Flag */ +#define TMS570_DMM_INTFLG_SRC_OVF BSP_BIT32(5) + +/* field: DEST3_ERR - Destination 3 Error Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST3_ERR BSP_BIT32(4) + +/* field: DEST2_ERR - Destination 2 Error Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST2_ERR BSP_BIT32(3) + +/* field: DEST1_ERR - Destination 1 Error Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST1_ERR BSP_BIT32(2) + +/* field: DEST0_ERR - Destination 0 Error Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST0_ERR BSP_BIT32(1) + +/* field: PACKET_ERR_INT - Packet Error Interrupt Flag */ +#define TMS570_DMM_INTFLG_PACKET_ERR_INT BSP_BIT32(0) + + +/*----------------------TMS570_DMM_OFF1----------------------*/ +/* field: OFFSET - User and privilege mode (read): */ +#define TMS570_DMM_OFF1_OFFSET(val) BSP_FLD32(val,0, 4) +#define TMS570_DMM_OFF1_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_DMM_OFF1_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*----------------------TMS570_DMM_OFF2----------------------*/ +/* field: OFFSET - User and privilege mode (read): */ +#define TMS570_DMM_OFF2_OFFSET(val) BSP_FLD32(val,0, 4) +#define TMS570_DMM_OFF2_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_DMM_OFF2_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*---------------------TMS570_DMM_DDMDEST---------------------*/ +/* field: STARTADDR - These bits define the starting address of the buffer. */ +/* Whole 32 bits */ + +/*----------------------TMS570_DMM_DDMBL----------------------*/ +/* field: BLOCKSIZE - These bits define the size of the buffer region */ +#define TMS570_DMM_DDMBL_BLOCKSIZE(val) BSP_FLD32(val,0, 3) +#define TMS570_DMM_DDMBL_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DMM_DDMBL_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*----------------------TMS570_DMM_DDMPT----------------------*/ +/* field: POINTER - These bits hold the pointer to the next entry to be written in the buffer. */ +#define TMS570_DMM_DDMPT_POINTER(val) BSP_FLD32(val,0, 14) +#define TMS570_DMM_DDMPT_POINTER_GET(reg) BSP_FLD32GET(reg,0, 14) +#define TMS570_DMM_DDMPT_POINTER_SET(reg,val) BSP_FLD32SET(reg, val,0, 14) + + +/*----------------------TMS570_DMM_INTPT----------------------*/ +/* field: INTPT - Interrupt Pointer. When the buffer pointer (Section 30.3. */ +#define TMS570_DMM_INTPT_INTPT(val) BSP_FLD32(val,0, 14) +#define TMS570_DMM_INTPT_INTPT_GET(reg) BSP_FLD32GET(reg,0, 14) +#define TMS570_DMM_INTPT_INTPT_SET(reg,val) BSP_FLD32SET(reg, val,0, 14) + + +/*--------------------TMS570_DMM_DESTxREG1--------------------*/ +/* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */ +#define TMS570_DMM_DESTxREG1_BASEADDR(val) BSP_FLD32(val,18, 31) +#define TMS570_DMM_DESTxREG1_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31) +#define TMS570_DMM_DESTxREG1_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31) + +/* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */ +#define TMS570_DMM_DESTxREG1_BLOCKADDR(val) BSP_FLD32(val,0, 17) +#define TMS570_DMM_DESTxREG1_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17) +#define TMS570_DMM_DESTxREG1_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17) + + +/*--------------------TMS570_DMM_DESTxBL1--------------------*/ +/* field: BLOCKSIZE - These bits define the length of the buffer region. */ +#define TMS570_DMM_DESTxBL1_BLOCKSIZE(val) BSP_FLD32(val,0, 3) +#define TMS570_DMM_DESTxBL1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DMM_DESTxBL1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_DMM_DESTxREG2--------------------*/ +/* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */ +#define TMS570_DMM_DESTxREG2_BASEADDR(val) BSP_FLD32(val,18, 31) +#define TMS570_DMM_DESTxREG2_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31) +#define TMS570_DMM_DESTxREG2_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31) + +/* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */ +#define TMS570_DMM_DESTxREG2_BLOCKADDR(val) BSP_FLD32(val,0, 17) +#define TMS570_DMM_DESTxREG2_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17) +#define TMS570_DMM_DESTxREG2_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17) + + +/*--------------------TMS570_DMM_DESTxBL2--------------------*/ +/* field: BLOCKSIZE - These bits define the length of the buffer region. */ +#define TMS570_DMM_DESTxBL2_BLOCKSIZE(val) BSP_FLD32(val,0, 3) +#define TMS570_DMM_DESTxBL2_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DMM_DESTxBL2_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-----------------------TMS570_DMM_PC0-----------------------*/ +/* field: ENAFUNC - Functional mode of DMMENA pin. */ +#define TMS570_DMM_PC0_ENAFUNC BSP_BIT32(18) + +/* field: DATAxFUNC - Functional mode of DMMDATA[x] pin. */ +#define TMS570_DMM_PC0_DATAxFUNC(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC0_DATAxFUNC_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC0_DATAxFUNC_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKFUNC - Functional mode of DMMCLK pin. */ +#define TMS570_DMM_PC0_CLKFUNC BSP_BIT32(1) + +/* field: SYNCFUNC - Functional mode of DMMSYNC pin. */ +#define TMS570_DMM_PC0_SYNCFUNC BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC1-----------------------*/ +/* field: ENADIR - Direction of DMMENA pin. */ +#define TMS570_DMM_PC1_ENADIR BSP_BIT32(18) + +/* field: DATAxDIR - Direction of DMMDATA[x] pin. */ +#define TMS570_DMM_PC1_DATAxDIR(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC1_DATAxDIR_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC1_DATAxDIR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKDIR - Direction of DMMCLK pin. */ +#define TMS570_DMM_PC1_CLKDIR BSP_BIT32(1) + +/* field: SYNCDIR - Direction of DMMSYNC pin. */ +#define TMS570_DMM_PC1_SYNCDIR BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC2-----------------------*/ +/* field: ENAIN - DMMENA input. This bit reflects the state of the pin in all modes. */ +#define TMS570_DMM_PC2_ENAIN BSP_BIT32(18) + +/* field: DATAxIN - DMMDATA[x] input. This bit reflects the state of the pin in all modes. */ +#define TMS570_DMM_PC2_DATAxIN(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC2_DATAxIN_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC2_DATAxIN_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKIN - DMMCLK input. This bit reflects the state of the pin in all modes. */ +#define TMS570_DMM_PC2_CLKIN BSP_BIT32(1) + +/* field: SYNCIN - DMMSYNC input. */ +#define TMS570_DMM_PC2_SYNCIN BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC3-----------------------*/ +/* field: ENAOUT - Output state of DMMENA pin. */ +#define TMS570_DMM_PC3_ENAOUT BSP_BIT32(18) + +/* field: DATAxOUT - Output state of DMMDATA[x] pin. This bit sets the pin to logic low or high level. */ +#define TMS570_DMM_PC3_DATAxOUT(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC3_DATAxOUT_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC3_DATAxOUT_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKOUT - Output state of DMMCLK pin. */ +#define TMS570_DMM_PC3_CLKOUT BSP_BIT32(1) + +/* field: SYNCOUT - Output state of DMMSYNC pin. This bit sets the pin to logic low or high level. */ +#define TMS570_DMM_PC3_SYNCOUT BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC4-----------------------*/ +/* field: ENASET - control register bit to 1 regardless of the current value in the ENAOUT bit. */ +#define TMS570_DMM_PC4_ENASET BSP_BIT32(18) + +/* field: DATAxSET - Sets output state of DMMDATA[x] pin to logic high. */ +#define TMS570_DMM_PC4_DATAxSET(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC4_DATAxSET_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC4_DATAxSET_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKSET - Sets output state of DMMCLK pin to logic high. */ +#define TMS570_DMM_PC4_CLKSET BSP_BIT32(1) + +/* field: SYNCSET - Sets output state of DMMSYNC pin logic high. */ +#define TMS570_DMM_PC4_SYNCSET BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC5-----------------------*/ +/* field: ENACLR - Sets output state of DMMENA pin to logic low. */ +#define TMS570_DMM_PC5_ENACLR BSP_BIT32(18) + +/* field: DATAxCLR - Sets output state of DMMDATA[x] pin to logic low. */ +#define TMS570_DMM_PC5_DATAxCLR(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC5_DATAxCLR_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC5_DATAxCLR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKCLR - Sets output state of DMMCLK pin to logic low. */ +#define TMS570_DMM_PC5_CLKCLR BSP_BIT32(1) + +/* field: SYNCCLR - Sets output state of DMMSYNC pin to logic low. */ +#define TMS570_DMM_PC5_SYNCCLR BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC6-----------------------*/ +/* field: ENAPDR - Open Drain enable. */ +#define TMS570_DMM_PC6_ENAPDR BSP_BIT32(18) + +/* field: DATAxPDR - Open Drain enable. */ +#define TMS570_DMM_PC6_DATAxPDR(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC6_DATAxPDR_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC6_DATAxPDR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKPDR - Open Drain enable. */ +#define TMS570_DMM_PC6_CLKPDR BSP_BIT32(1) + +/* field: SYNCPDR - Open Drain enable. */ +#define TMS570_DMM_PC6_SYNCPDR BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC7-----------------------*/ +/* field: ENAPDIS - Pull disable. */ +#define TMS570_DMM_PC7_ENAPDIS BSP_BIT32(18) + +/* field: DATAxPDIS - Pull disable. */ +#define TMS570_DMM_PC7_DATAxPDIS(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC7_DATAxPDIS_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC7_DATAxPDIS_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKPDIS - Pull disable. */ +#define TMS570_DMM_PC7_CLKPDIS BSP_BIT32(1) + +/* field: SYNCPDIS - Pull disable. */ +#define TMS570_DMM_PC7_SYNCPDIS BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC8-----------------------*/ +/* field: ENAPSEL - Pull disable. */ +#define TMS570_DMM_PC8_ENAPSEL BSP_BIT32(18) + +/* field: DATAxPSEL - Pull disable. */ +#define TMS570_DMM_PC8_DATAxPSEL(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC8_DATAxPSEL_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC8_DATAxPSEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKPSEL - Pull disable. */ +#define TMS570_DMM_PC8_CLKPSEL BSP_BIT32(1) + +/* field: SYNCPSEL - Pull disable. */ +#define TMS570_DMM_PC8_SYNCPSEL BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_DMM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h new file mode 100644 index 0000000000..decf5bbeff --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h @@ -0,0 +1,126 @@ +/* The header file is generated by make_header.py from EFUSE.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_EFUSE +#define LIBBSP_ARM_TMS570_EFUSE + +#include + +typedef struct{ + uint32_t EFCBOUND; /*EFC Boundary Control Register*/ + uint8_t reserved1 [12]; + uint32_t EFCPINS; /*EFC Pins Register*/ + uint8_t reserved2 [12]; + uint32_t EFC_ERR_STAT; /*EFC Error Status Register*/ + uint8_t reserved3 [8]; + uint32_t EFC_ST_CY; /*EFC Self Test Cycles Register*/ + uint32_t EFC_ST_SIG; /*EFC Self Test Signature Register*/ +} tms570_efuse_t; + + +/*-------------------TMS570_EFUSE_EFCBOUND-------------------*/ +/* field: EFC_Self_Test_Error - This bit drives the self test error signal when bit 17 (Self Test Error OE) is high. */ +#define TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error BSP_BIT32(21) + +/* field: EFC_Single_Bit_Error - This bit drives the single bit error signal when bit 16 (Single bit Error OE) is high. */ +#define TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error BSP_BIT32(20) + +/* field: EFC_Instruction_Error - This bit drives the instruction error signal when bit 15 (Instruction Error OE) is high. */ +#define TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error BSP_BIT32(19) + +/* field: EFC_Autoload_Error - This bit drives the Autoload Error signal when bit 14 (Autoload Error OE) is high. */ +#define TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error BSP_BIT32(18) + +/* field: Self_Test_Error_OE - The Self Test Error Output Enable bit determines if the EFC Self Test signal comes from the */ +#define TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE BSP_BIT32(17) + +/* field: Single_Bit_Error_OE - The single bit error output enable signal determines if the EFC Single Bit Error signal comes */ +#define TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE BSP_BIT32(16) + +/* field: Instruction_Error_OE - comes from the eFuse controller or from bit 19 of the boundary register. */ +#define TMS570_EFUSE_EFCBOUND_Instruction_Error_OE BSP_BIT32(15) + +/* field: Autoload_Error_OE - The autoload error output enable signal determines if the EFC Autoload Error signal comes */ +#define TMS570_EFUSE_EFCBOUND_Autoload_Error_OE BSP_BIT32(14) + +/* field: EFC_ECC_Selftest - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */ +#define TMS570_EFUSE_EFCBOUND_EFC_ECC_Selftest BSP_BIT32(13) + +/* field: Input_Enable - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */ +#define TMS570_EFUSE_EFCBOUND_Input_Enable(val) BSP_FLD32(val,0, 3) +#define TMS570_EFUSE_EFCBOUND_Input_Enable_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_EFUSE_EFCBOUND_Input_Enable_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_EFUSE_EFCPINS--------------------*/ +/* field: EFC_Selftest_Done - This bit can be polled to determine when the EFC ECC selftest is complete */ +#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Done BSP_BIT32(15) + +/* field: EFC_Selftest_Error - This bit indicates the pass/fail status of the EFC ECC Selftest once the EFC Selftest Done */ +#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Error BSP_BIT32(14) + +/* field: EFC_Single_Bit_Error - This bit indicates if a single bit error was corrected by the ECC logic during the autoload */ +#define TMS570_EFUSE_EFCPINS_EFC_Single_Bit_Error BSP_BIT32(12) + +/* field: EFC_Instruction_Error - This bit indicates an error occured during a factory test or program operation. */ +#define TMS570_EFUSE_EFCPINS_EFC_Instruction_Error BSP_BIT32(11) + +/* field: EFC_Autoload_Error - This bit indicates that some non-correctable error occurred during the autoload sequence */ +#define TMS570_EFUSE_EFCPINS_EFC_Autoload_Error BSP_BIT32(10) + + +/*-----------------TMS570_EFUSE_EFC_ERR_STAT-----------------*/ +/* field: Instruc_Done - Instruction done. */ +#define TMS570_EFUSE_EFC_ERR_STAT_Instruc_Done BSP_BIT32(5) + +/* field: Error_Code - The error status of the last instruction executed by the eFuse Controller */ +#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code(val) BSP_FLD32(val,0, 4) +#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*-------------------TMS570_EFUSE_EFC_ST_CY-------------------*/ +/* field: Cycles - This register is used to determine the number of cycles to run the eFuse controller ECC logic self test. */ +/* Whole 32 bits */ + +/*------------------TMS570_EFUSE_EFC_ST_SIG------------------*/ +/* field: Signature - This register is used to hold the expected signature for the eFuse ECC logic self test. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_EFUSE */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h new file mode 100644 index 0000000000..c7c564cf49 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h @@ -0,0 +1,285 @@ +/* The header file is generated by make_header.py from EMACC.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_EMACC +#define LIBBSP_ARM_TMS570_EMACC + +#include + +typedef struct{ + uint32_t REVID; /*EMAC Control Module Revision ID Register*/ + uint32_t SOFTRESET; /*EMAC Control Module Software Reset Register*/ + uint8_t reserved1 [4]; + uint32_t INTCONTROL; /*EMAC Control Module Interrupt Control Register*/ + uint32_t C0RXTHRESHEN; /*EMAC Control Module Receive Threshold Interrupt Enable Register*/ + uint32_t C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/ + uint32_t C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/ + uint32_t C0MISCEN; /*EMAC Control Module Miscellaneous Interrupt Enable Register*/ + uint8_t reserved2 [32]; + uint32_t C0RXTHRESHSTAT; /*EMAC Control Module Receive Threshold Interrupt Status Register*/ + uint32_t C0RXSTAT; /*EMAC Control Module Receive Interrupt Status Register*/ + uint32_t C0TXSTAT; /*EMAC Control Module Transmit Interrupt Status Register*/ + uint32_t C0MISCSTAT; /*EMAC Control Module Miscellaneous Interrupt Status Register*/ + uint8_t reserved3 [32]; + uint32_t C0RXIMAX; /*EMAC Control Module Receive Interrupts Per Millisecond Register*/ + uint32_t C0TXIMAX; /*EMAC Control Module Transmit Interrupts Per Millisecond Register*/ +} tms570_emacc_t; + + +/*---------------------TMS570_EMACC_REVID---------------------*/ +/* field: REV - Identifies the EMAC Control Module revision. */ +/* Whole 32 bits */ + +/*-------------------TMS570_EMACC_SOFTRESET-------------------*/ +/* field: RESET - Software reset bit for the EMAC Control Module. */ +#define TMS570_EMACC_SOFTRESET_RESET BSP_BIT32(0) + + +/*------------------TMS570_EMACC_INTCONTROL------------------*/ +/* field: C0TXPACEEN - Enable pacing for TX interrupt pulse generation */ +#define TMS570_EMACC_INTCONTROL_C0TXPACEEN BSP_BIT32(17) + +/* field: C0RXPACEEN - Enable pacing for RX interrupt pulse generation */ +#define TMS570_EMACC_INTCONTROL_C0RXPACEEN BSP_BIT32(16) + +/* field: INTPRESCALE - Number of internal EMAC module reference clock periods within a 4 us time window (see */ +#define TMS570_EMACC_INTCONTROL_INTPRESCALE(val) BSP_FLD32(val,0, 11) +#define TMS570_EMACC_INTCONTROL_INTPRESCALE_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_EMACC_INTCONTROL_INTPRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*-----------------TMS570_EMACC_C0RXTHRESHEN-----------------*/ +/* field: RXCH7THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 7 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH7THRESHEN BSP_BIT32(7) + +/* field: RXCH6THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 6 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH6THRESHEN BSP_BIT32(6) + +/* field: RXCH5THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 5 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH5THRESHEN BSP_BIT32(5) + +/* field: RXCH4THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 4 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH4THRESHEN BSP_BIT32(4) + +/* field: RXCH3THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 3 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH3THRESHEN BSP_BIT32(3) + +/* field: RXCH2THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 2 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH2THRESHEN BSP_BIT32(2) + +/* field: RXCH1THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 1 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH1THRESHEN BSP_BIT32(1) + +/* field: RXCH0THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 0 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH0THRESHEN BSP_BIT32(0) + + +/*--------------------TMS570_EMACC_C0RXEN--------------------*/ +/* field: RXCH7EN - Enable C0RXPULSE interrupt generation for RX Channel 7 */ +#define TMS570_EMACC_C0RXEN_RXCH7EN BSP_BIT32(7) + +/* field: RXCH6EN - Enable C0RXPULSE interrupt generation for RX Channel 6 */ +#define TMS570_EMACC_C0RXEN_RXCH6EN BSP_BIT32(6) + +/* field: RXCH5EN - Enable C0RXPULSE interrupt generation for RX Channel 5 */ +#define TMS570_EMACC_C0RXEN_RXCH5EN BSP_BIT32(5) + +/* field: RXCH4EN - Enable C0RXPULSE interrupt generation for RX Channel 4 */ +#define TMS570_EMACC_C0RXEN_RXCH4EN BSP_BIT32(4) + +/* field: RXCH3EN - Enable C0RXPULSE interrupt generation for RX Channel 3 */ +#define TMS570_EMACC_C0RXEN_RXCH3EN BSP_BIT32(3) + +/* field: RXCH2EN - Enable C0RXPULSE interrupt generation for RX Channel 2 */ +#define TMS570_EMACC_C0RXEN_RXCH2EN BSP_BIT32(2) + +/* field: RXCH1EN - Enable C0RXPULSE interrupt generation for RX Channel 1 */ +#define TMS570_EMACC_C0RXEN_RXCH1EN BSP_BIT32(1) + +/* field: RXCH0EN - Enable C0RXPULSE interrupt generation for RX Channel 0 */ +#define TMS570_EMACC_C0RXEN_RXCH0EN BSP_BIT32(0) + + +/*--------------------TMS570_EMACC_C0TXEN--------------------*/ +/* field: TXCH7EN - Enable C0TXPULSE interrupt generation for TX Channel 7 */ +#define TMS570_EMACC_C0TXEN_TXCH7EN BSP_BIT32(7) + +/* field: TXCH6EN - TXCH6EN */ +#define TMS570_EMACC_C0TXEN_TXCH6EN BSP_BIT32(6) + +/* field: TXCH5EN - Enable C0TXPULSE interrupt generation for TX Channel 5 */ +#define TMS570_EMACC_C0TXEN_TXCH5EN BSP_BIT32(5) + +/* field: TXCH4EN - Enable C0TXPULSE interrupt generation for TX Channel 4 */ +#define TMS570_EMACC_C0TXEN_TXCH4EN BSP_BIT32(4) + +/* field: TXCH3EN - Enable C0TXPULSE interrupt generation for TX Channel 3 */ +#define TMS570_EMACC_C0TXEN_TXCH3EN BSP_BIT32(3) + +/* field: TXCH2EN - Enable C0TXPULSE interrupt generation for TX Channel 2 */ +#define TMS570_EMACC_C0TXEN_TXCH2EN BSP_BIT32(2) + +/* field: TXCH1EN - Enable C0TXPULSE interrupt generation for TX Channel 1 */ +#define TMS570_EMACC_C0TXEN_TXCH1EN BSP_BIT32(1) + +/* field: TXCH0EN - Enable C0TXPULSE interrupt generation for TX Channel 0 */ +#define TMS570_EMACC_C0TXEN_TXCH0EN BSP_BIT32(0) + + +/*-------------------TMS570_EMACC_C0MISCEN-------------------*/ +/* field: STATPENDEN - Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated */ +#define TMS570_EMACC_C0MISCEN_STATPENDEN BSP_BIT32(3) + +/* field: HOSTPENDEN - HOSTPENDEN */ +#define TMS570_EMACC_C0MISCEN_HOSTPENDEN BSP_BIT32(2) + +/* field: LINKINT0EN - Enable C0MISCPULSE interrupt generation when MDIO LINKINT0 interrupts (corresponding to */ +#define TMS570_EMACC_C0MISCEN_LINKINT0EN BSP_BIT32(1) + +/* field: USERINT0EN - Enable C0MISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding */ +#define TMS570_EMACC_C0MISCEN_USERINT0EN BSP_BIT32(0) + + +/*----------------TMS570_EMACC_C0RXTHRESHSTAT----------------*/ +/* field: RXCH7THRESHSTAT - Interrupt status for RX Channel 7 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH7THRESHSTAT BSP_BIT32(7) + +/* field: RXCH6THRESHSTAT - Interrupt status for RX Channel 6 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH6THRESHSTAT BSP_BIT32(6) + +/* field: RXCH5THRESHSTAT - Interrupt status for RX Channel 5 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH5THRESHSTAT BSP_BIT32(5) + +/* field: RXCH4THRESHSTAT - Interrupt status for RX Channel 4 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH4THRESHSTAT BSP_BIT32(4) + +/* field: RXCH3THRESHSTAT - Interrupt status for RX Channel 3 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH3THRESHSTAT BSP_BIT32(3) + +/* field: RXCH2THRESHSTAT - Interrupt status for RX Channel 2 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH2THRESHSTAT BSP_BIT32(2) + +/* field: RXCH1THRESHSTAT - Interrupt status for RX Channel 1 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH1THRESHSTAT BSP_BIT32(1) + +/* field: RXCH0THRESHSTAT - Interrupt status for RX Channel 0 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH0THRESHSTAT BSP_BIT32(0) + + +/*-------------------TMS570_EMACC_C0RXSTAT-------------------*/ +/* field: RXCH7STAT - RXCH7STAT */ +#define TMS570_EMACC_C0RXSTAT_RXCH7STAT BSP_BIT32(7) + +/* field: RXCH6STAT - Interrupt status for RX Channel 6 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH6STAT BSP_BIT32(6) + +/* field: RXCH5STAT - Interrupt status for RX Channel 5 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH5STAT BSP_BIT32(5) + +/* field: RXCH4STAT - Interrupt status for RX Channel 4 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH4STAT BSP_BIT32(4) + +/* field: RXCH3STAT - Interrupt status for RX Channel 3 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH3STAT BSP_BIT32(3) + +/* field: RXCH2STAT - H2STAT Interrupt status for RX Channel 2 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH2STAT BSP_BIT32(2) + +/* field: RXCH1STAT - Interrupt status for RX Channel 1 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH1STAT BSP_BIT32(1) + +/* field: RXCH0STAT - Interrupt status for RX Channel 0 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH0STAT BSP_BIT32(0) + + +/*-------------------TMS570_EMACC_C0TXSTAT-------------------*/ +/* field: TXCH7STAT - Interrupt status for TX Channel 7 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH7STAT BSP_BIT32(7) + +/* field: TXCH6STAT - TXCH6STAT */ +#define TMS570_EMACC_C0TXSTAT_TXCH6STAT BSP_BIT32(6) + +/* field: TXCH5STAT - Interrupt status for TX Channel 5 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH5STAT BSP_BIT32(5) + +/* field: TXCH4STAT - Interrupt status for TX Channel 4 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH4STAT BSP_BIT32(4) + +/* field: TXCH3STAT - Interrupt status for TX Channel 3 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH3STAT BSP_BIT32(3) + +/* field: TXCH2STAT - Interrupt status for TX Channel 2 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH2STAT BSP_BIT32(2) + +/* field: TXCH1STAT - Interrupt status for TX Channel 1 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH1STAT BSP_BIT32(1) + +/* field: TXCH0STAT - Interrupt status for TX Channel 0 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH0STAT BSP_BIT32(0) + + +/*------------------TMS570_EMACC_C0MISCSTAT------------------*/ +/* field: STATPENDSTAT - Interrupt status for EMAC STATPEND masked by the C0MISCEN register */ +#define TMS570_EMACC_C0MISCSTAT_STATPENDSTAT BSP_BIT32(3) + +/* field: HOSTPENDSTAT - Interrupt status for EMAC HOSTPEND masked by the C0MISCEN register */ +#define TMS570_EMACC_C0MISCSTAT_HOSTPENDSTAT BSP_BIT32(2) + +/* field: LINKINT0STAT - Interrupt status for MDIO LINKINT0 masked by the C0MISCEN register */ +#define TMS570_EMACC_C0MISCSTAT_LINKINT0STAT BSP_BIT32(1) + +/* field: USERINT0STAT - Interrupt status for MDIO USERINT0 masked by the C0MISCEN register */ +#define TMS570_EMACC_C0MISCSTAT_USERINT0STAT BSP_BIT32(0) + + +/*-------------------TMS570_EMACC_C0RXIMAX-------------------*/ +/* field: RXIMAX - RXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond when */ +#define TMS570_EMACC_C0RXIMAX_RXIMAX(val) BSP_FLD32(val,0, 5) +#define TMS570_EMACC_C0RXIMAX_RXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_EMACC_C0RXIMAX_RXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_EMACC_C0TXIMAX-------------------*/ +/* field: TXIMAX - TXIMAX is the desired number of C0TXPULSE interrupts generated per millisecond when */ +#define TMS570_EMACC_C0TXIMAX_TXIMAX(val) BSP_FLD32(val,0, 5) +#define TMS570_EMACC_C0TXIMAX_TXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_EMACC_C0TXIMAX_TXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + + +#endif /* LIBBSP_ARM_TMS570_EMACC */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h new file mode 100644 index 0000000000..c6e63210aa --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h @@ -0,0 +1,898 @@ +/* The header file is generated by make_header.py from EMACM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_EMACM +#define LIBBSP_ARM_TMS570_EMACM + +#include + +typedef struct{ + uint32_t TXREVID; /*Transmit Revision ID Register*/ + uint32_t TXCONTROL; /*Transmit Control Register*/ + uint32_t TXTEARDOWN; /*Transmit Teardown Register*/ + uint8_t reserved1 [4]; + uint32_t RXREVID; /*Receive Revision ID Register*/ + uint32_t RXCONTROL; /*Receive Control Register*/ + uint32_t RXTEARDOWN; /*Receive Teardown Register*/ + uint8_t reserved2 [100]; + uint32_t TXINTSTATRAW; /*Transmit Interrupt Status (Unmasked) Register*/ + uint32_t TXINTSTATMASKED; /*Transmit Interrupt Status (Masked) Register*/ + uint32_t TXINTMASKSET; /*Transmit Interrupt Mask Set Register*/ + uint32_t TXINTMASKCLEAR; /*Transmit Interrupt Clear Register*/ + uint32_t MACINVECTOR; /*MAC Input Vector Register*/ + uint32_t MACEOIVECTOR; /*MAC End Of Interrupt Vector Register*/ + uint8_t reserved3 [8]; + uint32_t RXINTSTATRAW; /*Receive Interrupt Status (Unmasked) Register*/ + uint32_t RXINTSTATMASKED; /*Receive Interrupt Status (Masked) Register*/ + uint32_t RXINTMASKSET; /*Receive Interrupt Mask Set Register*/ + uint32_t RXINTMASKCLEAR; /*Receive Interrupt Mask Clear Register*/ + uint32_t MACINTSTATRAW; /*MAC Interrupt Status (Unmasked) Register*/ + uint32_t MACINTSTATMASKED; /*MAC Interrupt Status (Masked) Register*/ + uint32_t MACINTMASKSET; /*MAC Interrupt Mask Set Register*/ + uint32_t MACINTMASKCLEAR; /*MAC Interrupt Mask Clear Register*/ + uint8_t reserved4 [64]; + uint32_t RXMBPENABLE; /*Receive Multicast/Broadcast/Promiscuous Channel Enable*/ + uint32_t RXUNICASTSET; /*Receive Unicast Enable Set Register*/ + uint32_t RXUNICASTCLEAR; /*Receive Unicast Clear Register*/ + uint32_t RXMAXLEN; /*Receive Maximum Length Register*/ + uint32_t RXBUFFEROFFSET; /*Receive Buffer Offset Register*/ + uint32_t RXFILTERLOWTHRESH; /*Receive Filter Low Priority Frame Threshold Register*/ + uint8_t reserved5 [8]; + uint32_t RXFLOWTHRESH[8]; /*Receive Channel Flow Control Threshold Register*/ + uint32_t RXFREEBUFFER[8]; /*Receive Channel Free Buffer Count Register*/ + uint32_t MACCONTROL; /*MAC Control Register*/ + uint32_t MACSTATUS; /*MAC Status Register*/ + uint32_t EMCONTROL; /*Emulation Control Register*/ + uint32_t FIFOCONTROL; /*FIFO Control Register*/ + uint32_t MACCONFIG; /*MAC Configuration Register*/ + uint32_t SOFTRESET; /*Soft Reset Register*/ + uint8_t reserved6 [88]; + uint32_t MACSRCADDRLO; /*MAC Source Address Low Bytes Register*/ + uint32_t MACSRCADDRHI; /*MAC Source Address High Bytes Register*/ + uint32_t MACHASH1; /*MAC Hash Address Register 1*/ + uint32_t MACHASH2; /*MAC Hash Address Register 2*/ + uint32_t BOFFTEST; /*Back Off Test Register*/ + uint32_t TPACETEST; /*Transmit Pacing Algorithm Test Register*/ + uint32_t RXPAUSE; /*Receive Pause Timer Register*/ + uint32_t TXPAUSE; /*Transmit Pause Timer Register*/ + uint8_t reserved7 [784]; + uint32_t MACADDRLO; /*MAC Address Low Bytes Register*/ + uint32_t MACADDRHI; /*MAC Address High Bytes Register*/ + uint32_t MACINDEX; /*MAC Index Register*/ + uint8_t reserved8 [244]; + uint32_t TXHDP[8]; /*Transmit Channel DMA Head Descriptor Pointer Register*/ + uint32_t RXHDP[8]; /*Receive Channel DMA Head Descriptor Pointer Register*/ + uint32_t TXCP[8]; /*Transmit Channel Completion Pointer Register*/ + uint32_t RXCP[8]; /*Receive Channel Completion Pointer Register*/ +} tms570_emacm_t; + + +/*--------------------TMS570_EMACM_TXREVID--------------------*/ +/* field: TXREV - Transmit module revision */ +/* Whole 32 bits */ + +/*-------------------TMS570_EMACM_TXCONTROL-------------------*/ +/* field: TXEN - Transmit enable */ +#define TMS570_EMACM_TXCONTROL_TXEN BSP_BIT32(0) + + +/*------------------TMS570_EMACM_TXTEARDOWN------------------*/ +/* field: TXTDNCH - Transmit teardown channel. */ +#define TMS570_EMACM_TXTEARDOWN_TXTDNCH(val) BSP_FLD32(val,0, 2) +#define TMS570_EMACM_TXTEARDOWN_TXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_EMACM_TXTEARDOWN_TXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*--------------------TMS570_EMACM_RXREVID--------------------*/ +/* field: RXREV - Receive module revision */ +/* Whole 32 bits */ + +/*-------------------TMS570_EMACM_RXCONTROL-------------------*/ +/* field: RXEN - Receive enable */ +#define TMS570_EMACM_RXCONTROL_RXEN BSP_BIT32(0) + + +/*------------------TMS570_EMACM_RXTEARDOWN------------------*/ +/* field: RXTDNCH - Receive teardown channel. */ +#define TMS570_EMACM_RXTEARDOWN_RXTDNCH(val) BSP_FLD32(val,0, 2) +#define TMS570_EMACM_RXTEARDOWN_RXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_EMACM_RXTEARDOWN_RXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------TMS570_EMACM_TXINTSTATRAW-----------------*/ +/* field: TX7PEND - TX7PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX7PEND BSP_BIT32(7) + +/* field: TX6PEND - TX6PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX6PEND BSP_BIT32(6) + +/* field: TX5PEND - TX5PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX5PEND BSP_BIT32(5) + +/* field: TX4PEND - X4PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX4PEND BSP_BIT32(4) + +/* field: TX3PEND - TX3PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX3PEND BSP_BIT32(3) + +/* field: TX2PEND - TX2PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX2PEND BSP_BIT32(2) + +/* field: TX1PEND - TX1PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX1PEND BSP_BIT32(1) + +/* field: TX0PEND - TX0PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX0PEND BSP_BIT32(0) + + +/*----------------TMS570_EMACM_TXINTSTATMASKED----------------*/ +/* field: TX7PEND - TX7PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX7PEND BSP_BIT32(7) + +/* field: TX6PEND - TX6PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX6PEND BSP_BIT32(6) + +/* field: TX5PEND - TX5PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX5PEND BSP_BIT32(5) + +/* field: TX4PEND - TX4PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX4PEND BSP_BIT32(4) + +/* field: TX3PEND - TX3PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX3PEND BSP_BIT32(3) + +/* field: TX2PEND - TX2PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX2PEND BSP_BIT32(2) + +/* field: TX1PEND - TX1PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX1PEND BSP_BIT32(1) + +/* field: TX0PEND - TX0PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX0PEND BSP_BIT32(0) + + +/*-----------------TMS570_EMACM_TXINTMASKSET-----------------*/ +/* field: TX7MASK - Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX7MASK BSP_BIT32(7) + +/* field: TX6MASK - Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX6MASK BSP_BIT32(6) + +/* field: TX5MASK - Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX5MASK BSP_BIT32(5) + +/* field: TX4MASK - Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX4MASK BSP_BIT32(4) + +/* field: TX3MASK - Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX3MASK BSP_BIT32(3) + +/* field: TX2MASK - Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX2MASK BSP_BIT32(2) + +/* field: TX1MASK - Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX1MASK BSP_BIT32(1) + +/* field: TX0MASK - Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX0MASK BSP_BIT32(0) + + +/*----------------TMS570_EMACM_TXINTMASKCLEAR----------------*/ +/* field: TX7MASK - Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX7MASK BSP_BIT32(7) + +/* field: TX6MASK - Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX6MASK BSP_BIT32(6) + +/* field: TX5MASK - Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX5MASK BSP_BIT32(5) + +/* field: TX4MASK - Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX4MASK BSP_BIT32(4) + +/* field: TX3MASK - Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX3MASK BSP_BIT32(3) + +/* field: TX2MASK - Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX2MASK BSP_BIT32(2) + +/* field: TX1MASK - Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX1MASK BSP_BIT32(1) + +/* field: TX0MASK - Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX0MASK BSP_BIT32(0) + + +/*------------------TMS570_EMACM_MACINVECTOR------------------*/ +/* field: STATPEND - EMAC module statistics interrupt (STATPEND) pending status bit */ +#define TMS570_EMACM_MACINVECTOR_STATPEND BSP_BIT32(27) + +/* field: HOSTPEND - EMAC module host error interrupt (HOSTPEND) pending status bit */ +#define TMS570_EMACM_MACINVECTOR_HOSTPEND BSP_BIT32(26) + +/* field: LINKINT0 - MDIO module USERPHYSEL0 (LINKINT0) status bit */ +#define TMS570_EMACM_MACINVECTOR_LINKINT0 BSP_BIT32(25) + +/* field: USERINT0 - MDIO module USERACCESS0 (USERINT0) status bit */ +#define TMS570_EMACM_MACINVECTOR_USERINT0 BSP_BIT32(24) + +/* field: TXPEND - Transmit channels 0-7 interrupt (TXnPEND) pending status. Bit 16 is TX0PEND. */ +#define TMS570_EMACM_MACINVECTOR_TXPEND(val) BSP_FLD32(val,16, 23) +#define TMS570_EMACM_MACINVECTOR_TXPEND_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_EMACM_MACINVECTOR_TXPEND_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: RXTHRESHPEND - Receive channels 0-7 interrupt (RXnTHRESHPEND) pending status. */ +#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND(val) BSP_FLD32(val,8, 15) +#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: RXPEND - Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 0 is RX0PEND. */ +#define TMS570_EMACM_MACINVECTOR_RXPEND(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_MACINVECTOR_RXPEND_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_MACINVECTOR_RXPEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------TMS570_EMACM_MACEOIVECTOR-----------------*/ +/* field: INTVECT - Acknowledge EMAC Control Module Interrupts */ +#define TMS570_EMACM_MACEOIVECTOR_INTVECT(val) BSP_FLD32(val,0, 4) +#define TMS570_EMACM_MACEOIVECTOR_INTVECT_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_EMACM_MACEOIVECTOR_INTVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*-----------------TMS570_EMACM_RXINTSTATRAW-----------------*/ +/* field: RX7THRESHPEND - RX7THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX7THRESHPEND BSP_BIT32(15) + +/* field: RX6THRESHPEND - RX6THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX6THRESHPEND BSP_BIT32(14) + +/* field: RX5THRESHPEND - RX5THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX5THRESHPEND BSP_BIT32(13) + +/* field: RX4THRESHPEND - RX4THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX4THRESHPEND BSP_BIT32(12) + +/* field: RX3THRESHPEND - RX3THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX3THRESHPEND BSP_BIT32(11) + +/* field: RX2THRESHPEND - RX2THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX2THRESHPEND BSP_BIT32(10) + +/* field: RX1THRESHPEND - RX1THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX1THRESHPEND BSP_BIT32(9) + +/* field: RX0THRESHPEND - RX0THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX0THRESHPEND BSP_BIT32(8) + +/* field: RX7PEND - RX7PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX7PEND BSP_BIT32(7) + +/* field: RX6PEND - RX6PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX6PEND BSP_BIT32(6) + +/* field: RX5PEND - RX5PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX5PEND BSP_BIT32(5) + +/* field: RX4PEND - RX4PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX4PEND BSP_BIT32(4) + +/* field: RX3PEND - RX3PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX3PEND BSP_BIT32(3) + +/* field: RX2PEND - RX2PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX2PEND BSP_BIT32(2) + +/* field: RX1PEND - RX1PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX1PEND BSP_BIT32(1) + +/* field: RX0PEND - RX0PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX0PEND BSP_BIT32(0) + + +/*----------------TMS570_EMACM_RXINTSTATMASKED----------------*/ +/* field: RX7THRESHPEND - RX7THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX7THRESHPEND BSP_BIT32(15) + +/* field: RX6THRESHPEND - RX6THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX6THRESHPEND BSP_BIT32(14) + +/* field: RX5THRESHPEND - RX5THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX5THRESHPEND BSP_BIT32(13) + +/* field: RX4THRESHPEND - RX4THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX4THRESHPEND BSP_BIT32(12) + +/* field: RX3THRESHPEND - RX3THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX3THRESHPEND BSP_BIT32(11) + +/* field: RX2THRESHPEND - RX2THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX2THRESHPEND BSP_BIT32(10) + +/* field: RX1THRESHPEND - RX1THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX1THRESHPEND BSP_BIT32(9) + +/* field: RX0THRESHPEND - RX0THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX0THRESHPEND BSP_BIT32(8) + +/* field: RX7PEND - RX7PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX7PEND BSP_BIT32(7) + +/* field: RX6PEND - RX6PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX6PEND BSP_BIT32(6) + +/* field: RX5PEND - RX5PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX5PEND BSP_BIT32(5) + +/* field: RX4PEND - RX4PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX4PEND BSP_BIT32(4) + +/* field: RX3PEND - RX3PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX3PEND BSP_BIT32(3) + +/* field: RX2PEND - RX2PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX2PEND BSP_BIT32(2) + +/* field: RX1PEND - RX1PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX1PEND BSP_BIT32(1) + +/* field: RX0PEND - RX0PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX0PEND BSP_BIT32(0) + + +/*-----------------TMS570_EMACM_RXINTMASKSET-----------------*/ +/* field: RX7THRESHMASK - Receive channel 7 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX7THRESHMASK BSP_BIT32(15) + +/* field: RX6THRESHMASK - Receive channel 6 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX6THRESHMASK BSP_BIT32(14) + +/* field: RX5THRESHMASK - Receive channel 5 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX5THRESHMASK BSP_BIT32(13) + +/* field: RX4THRESHMASK - Receive channel 4 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX4THRESHMASK BSP_BIT32(12) + +/* field: RX3THRESHMASK - Receive channel 3 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX3THRESHMASK BSP_BIT32(11) + +/* field: RX2THRESHMASK - Receive channel 2 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX2THRESHMASK BSP_BIT32(10) + +/* field: RX1THRESHMASK - Receive channel 1 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX1THRESHMASK BSP_BIT32(9) + +/* field: RX0THRESHMASK - Receive channel 0 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX0THRESHMASK BSP_BIT32(8) + +/* field: RX7MASK - Receive channel 7 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX7MASK BSP_BIT32(7) + +/* field: RX6MASK - Receive channel 6 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX6MASK BSP_BIT32(6) + +/* field: RX5MASK - Receive channel 5 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX5MASK BSP_BIT32(5) + +/* field: RX4MASK - Receive channel 4 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX4MASK BSP_BIT32(4) + +/* field: RX3MASK - Receive channel 3 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX3MASK BSP_BIT32(3) + +/* field: RX2MASK - Receive channel 2 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX2MASK BSP_BIT32(2) + +/* field: RX1MASK - Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX1MASK BSP_BIT32(1) + +/* field: RX0MASK - Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX0MASK BSP_BIT32(0) + + +/*----------------TMS570_EMACM_RXINTMASKCLEAR----------------*/ +/* field: RX7THRESHMASK - Receive channel 7 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX7THRESHMASK BSP_BIT32(15) + +/* field: RX6THRESHMASK - Receive channel 6 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX6THRESHMASK BSP_BIT32(14) + +/* field: RX5THRESHMASK - Receive channel 5 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX5THRESHMASK BSP_BIT32(13) + +/* field: RX4THRESHMASK - Receive channel 4 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX4THRESHMASK BSP_BIT32(12) + +/* field: RX3THRESHMASK - Receive channel 3 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX3THRESHMASK BSP_BIT32(11) + +/* field: RX2THRESHMASK - Receive channel 2 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX2THRESHMASK BSP_BIT32(10) + +/* field: RX1THRESHMASK - Receive channel 1 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX1THRESHMASK BSP_BIT32(9) + +/* field: RX0THRESHMASK - Receive channel 0 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX0THRESHMASK BSP_BIT32(8) + +/* field: RX7MASK - Receive channel 7 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX7MASK BSP_BIT32(7) + +/* field: RX6MASK - Receive channel 6 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX6MASK BSP_BIT32(6) + +/* field: RX5MASK - Receive channel 5 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX5MASK BSP_BIT32(5) + +/* field: RX4MASK - Receive channel 4 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX4MASK BSP_BIT32(4) + +/* field: RX3MASK - Receive channel 3 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX3MASK BSP_BIT32(3) + +/* field: RX2MASK - Receive channel 2 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX2MASK BSP_BIT32(2) + +/* field: RX1MASK - Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX1MASK BSP_BIT32(1) + +/* field: RX0MASK - Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX0MASK BSP_BIT32(0) + + +/*-----------------TMS570_EMACM_MACINTSTATRAW-----------------*/ +/* field: HOSTPEND - Host pending interrupt (HOSTPEND); raw interrupt read (before mask). */ +#define TMS570_EMACM_MACINTSTATRAW_HOSTPEND BSP_BIT32(1) + +/* field: STATPEND - Statistics pending interrupt (STATPEND); raw interrupt read (before mask). */ +#define TMS570_EMACM_MACINTSTATRAW_STATPEND BSP_BIT32(0) + + +/*---------------TMS570_EMACM_MACINTSTATMASKED---------------*/ +/* field: HOSTPEND - Host pending interrupt (HOSTPEND); masked interrupt read. */ +#define TMS570_EMACM_MACINTSTATMASKED_HOSTPEND BSP_BIT32(1) + +/* field: STATPEND - Statistics pending interrupt (STATPEND); masked interrupt read. */ +#define TMS570_EMACM_MACINTSTATMASKED_STATPEND BSP_BIT32(0) + + +/*-----------------TMS570_EMACM_MACINTMASKSET-----------------*/ +/* field: HOSTMASK - Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_MACINTMASKSET_HOSTMASK BSP_BIT32(1) + +/* field: STATMASK - Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_MACINTMASKSET_STATMASK BSP_BIT32(0) + + +/*----------------TMS570_EMACM_MACINTMASKCLEAR----------------*/ +/* field: HOSTMASK - Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_MACINTMASKCLEAR_HOSTMASK BSP_BIT32(1) + +/* field: STATMASK - Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_MACINTMASKCLEAR_STATMASK BSP_BIT32(0) + + +/*------------------TMS570_EMACM_RXMBPENABLE------------------*/ +/* field: RXPASSCRC - Pass receive CRC enable bit */ +#define TMS570_EMACM_RXMBPENABLE_RXPASSCRC BSP_BIT32(30) + +/* field: RXQOSEN - Receive quality of service enable bit */ +#define TMS570_EMACM_RXMBPENABLE_RXQOSEN BSP_BIT32(29) + +/* field: RXNOCHAIN - Receive no buffer chaining bit */ +#define TMS570_EMACM_RXMBPENABLE_RXNOCHAIN BSP_BIT32(28) + +/* field: RXCMFEN - Receive copy MAC control frames enable bit. */ +#define TMS570_EMACM_RXMBPENABLE_RXCMFEN BSP_BIT32(24) + +/* field: RXCSFEN - Receive copy short frames enable bit. */ +#define TMS570_EMACM_RXMBPENABLE_RXCSFEN BSP_BIT32(23) + +/* field: RXCEFEN - Receive copy error frames enable bit. */ +#define TMS570_EMACM_RXMBPENABLE_RXCEFEN BSP_BIT32(22) + +/* field: RXCAFEN - Receive copy all frames enable bit. */ +#define TMS570_EMACM_RXMBPENABLE_RXCAFEN BSP_BIT32(21) + +/* field: RXPROMCH - Receive promiscuous channel select */ +#define TMS570_EMACM_RXMBPENABLE_RXPROMCH(val) BSP_FLD32(val,16, 18) +#define TMS570_EMACM_RXMBPENABLE_RXPROMCH_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_EMACM_RXMBPENABLE_RXPROMCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: RXBROADEN - Receive broadcast enable. */ +#define TMS570_EMACM_RXMBPENABLE_RXBROADEN BSP_BIT32(13) + +/* field: RXBROADCH - Receive broadcast channel select */ +#define TMS570_EMACM_RXMBPENABLE_RXBROADCH(val) BSP_FLD32(val,8, 10) +#define TMS570_EMACM_RXMBPENABLE_RXBROADCH_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_EMACM_RXMBPENABLE_RXBROADCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: RXMULTEN - RX multicast enable. */ +#define TMS570_EMACM_RXMBPENABLE_RXMULTEN BSP_BIT32(5) + + +/*-----------------TMS570_EMACM_RXUNICASTSET-----------------*/ +/* field: RXCH7EN - Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH7EN BSP_BIT32(7) + +/* field: RXCH6EN - Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH6EN BSP_BIT32(6) + +/* field: RXCH5EN - Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH5EN BSP_BIT32(5) + +/* field: RXCH4EN - Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH4EN BSP_BIT32(4) + +/* field: RXCH3EN - Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH3EN BSP_BIT32(3) + +/* field: RXCH2EN - Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH2EN BSP_BIT32(2) + +/* field: RXCH1EN - Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH1EN BSP_BIT32(1) + +/* field: RXCH0EN - Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH0EN BSP_BIT32(0) + + +/*----------------TMS570_EMACM_RXUNICASTCLEAR----------------*/ +/* field: RXCH7EN - Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH7EN BSP_BIT32(7) + +/* field: RXCH6EN - Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH6EN BSP_BIT32(6) + +/* field: RXCH5EN - Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH5EN BSP_BIT32(5) + +/* field: RXCH4EN - Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH4EN BSP_BIT32(4) + +/* field: RXCH3EN - Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH3EN BSP_BIT32(3) + +/* field: RXCH2EN - Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH2EN BSP_BIT32(2) + +/* field: RXCH1EN - Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH1EN BSP_BIT32(1) + +/* field: RXCH0EN - Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH0EN BSP_BIT32(0) + + +/*-------------------TMS570_EMACM_RXMAXLEN-------------------*/ +/* field: RXMAXLEN - Receive maximum frame length. These bits determine the maximum length of a received frame. */ +#define TMS570_EMACM_RXMAXLEN_RXMAXLEN(val) BSP_FLD32(val,0, 15) +#define TMS570_EMACM_RXMAXLEN_RXMAXLEN_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_EMACM_RXMAXLEN_RXMAXLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------TMS570_EMACM_RXBUFFEROFFSET----------------*/ +/* field: RXBUFFEROFFSET - Receive buffer offset value. */ +#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET(val) BSP_FLD32(val,0, 15) +#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------TMS570_EMACM_RXFILTERLOWTHRESH---------------*/ +/* field: RXFILTERTHRESH - Receive filter low threshold. */ +#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------TMS570_EMACM_RXFLOWTHRESH-----------------*/ +/* field: RXnFLOWTHRESH - Receive flow threshold. */ +#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------TMS570_EMACM_RXFREEBUFFER-----------------*/ +/* field: RXnFREEBUF - Receive free buffer count. These bits contain the count of free buffers available. */ +#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF(val) BSP_FLD32(val,0, 15) +#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_EMACM_MACCONTROL------------------*/ +/* field: RMIISPEED - RMII interface transmit and receive speed select. */ +#define TMS570_EMACM_MACCONTROL_RMIISPEED BSP_BIT32(15) + +/* field: RXOFFLENBLOCK - Receive offset / length word write block. */ +#define TMS570_EMACM_MACCONTROL_RXOFFLENBLOCK BSP_BIT32(14) + +/* field: RXOWNERSHIP - Receive ownership write bit value. */ +#define TMS570_EMACM_MACCONTROL_RXOWNERSHIP BSP_BIT32(13) + +/* field: CMDIDLE - Command Idle bit */ +#define TMS570_EMACM_MACCONTROL_CMDIDLE BSP_BIT32(11) + +/* field: TXSHORTGAPEN - Transmit Short Gap Enable */ +#define TMS570_EMACM_MACCONTROL_TXSHORTGAPEN BSP_BIT32(10) + +/* field: TXPTYPE - Transmit queue priority type */ +#define TMS570_EMACM_MACCONTROL_TXPTYPE BSP_BIT32(9) + +/* field: TXPACE - Transmit pacing enable bit */ +#define TMS570_EMACM_MACCONTROL_TXPACE BSP_BIT32(6) + +/* field: GMIIEN - GMII enable bit */ +#define TMS570_EMACM_MACCONTROL_GMIIEN BSP_BIT32(5) + +/* field: TXFLOWEN - Transmit flow control enable bit. */ +#define TMS570_EMACM_MACCONTROL_TXFLOWEN BSP_BIT32(4) + +/* field: RXBUFFERFLOWEN - Receive buffer flow control enable bit */ +#define TMS570_EMACM_MACCONTROL_RXBUFFERFLOWEN BSP_BIT32(3) + +/* field: LOOPBACK - Loopback mode. The loopback mode forces internal full-duplex mode regardless of the FULLDUPLEX bit. */ +#define TMS570_EMACM_MACCONTROL_LOOPBACK BSP_BIT32(1) + +/* field: FULLDUPLEX - Full duplex mode. */ +#define TMS570_EMACM_MACCONTROL_FULLDUPLEX BSP_BIT32(0) + + +/*-------------------TMS570_EMACM_MACSTATUS-------------------*/ +/* field: IDLE - EMAC idle bit. This bit is cleared to 0 at reset; one clock after reset, it goes to 1. */ +#define TMS570_EMACM_MACSTATUS_IDLE BSP_BIT32(31) + +/* field: TXERRCODE - Transmit host error code. These bits indicate that EMAC detected transmit DMA related host errors. */ +#define TMS570_EMACM_MACSTATUS_TXERRCODE(val) BSP_FLD32(val,20, 23) +#define TMS570_EMACM_MACSTATUS_TXERRCODE_GET(reg) BSP_FLD32GET(reg,20, 23) +#define TMS570_EMACM_MACSTATUS_TXERRCODE_SET(reg,val) BSP_FLD32SET(reg, val,20, 23) + +/* field: TXERRCH - Transmit host error channel. These bits indicate which transmit channel the host error occurred on. */ +#define TMS570_EMACM_MACSTATUS_TXERRCH(val) BSP_FLD32(val,16, 18) +#define TMS570_EMACM_MACSTATUS_TXERRCH_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_EMACM_MACSTATUS_TXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: RXERRCODE - Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. */ +#define TMS570_EMACM_MACSTATUS_RXERRCODE(val) BSP_FLD32(val,12, 15) +#define TMS570_EMACM_MACSTATUS_RXERRCODE_GET(reg) BSP_FLD32GET(reg,12, 15) +#define TMS570_EMACM_MACSTATUS_RXERRCODE_SET(reg,val) BSP_FLD32SET(reg, val,12, 15) + +/* field: RXERRCH - Receive host error channel. These bits indicate which receive channel the host error occurred on. */ +#define TMS570_EMACM_MACSTATUS_RXERRCH(val) BSP_FLD32(val,8, 10) +#define TMS570_EMACM_MACSTATUS_RXERRCH_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_EMACM_MACSTATUS_RXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: RXQOSACT - Receive Quality of Service (QOS) active bit. */ +#define TMS570_EMACM_MACSTATUS_RXQOSACT BSP_BIT32(2) + +/* field: RXFLOWACT - Receive flow control active bit. */ +#define TMS570_EMACM_MACSTATUS_RXFLOWACT BSP_BIT32(1) + +/* field: TXFLOWACT - Transmit flow control active bit. */ +#define TMS570_EMACM_MACSTATUS_TXFLOWACT BSP_BIT32(0) + + +/*-------------------TMS570_EMACM_EMCONTROL-------------------*/ +/* field: SOFT - Emulation soft bit. */ +#define TMS570_EMACM_EMCONTROL_SOFT BSP_BIT32(1) + +/* field: FREE - Emulation free bit. */ +#define TMS570_EMACM_EMCONTROL_FREE BSP_BIT32(0) + + +/*------------------TMS570_EMACM_FIFOCONTROL------------------*/ +/* field: TXCELLTHRESH - Transmit FIFO cell threshold. */ +#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH(val) BSP_FLD32(val,0, 1) +#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*-------------------TMS570_EMACM_MACCONFIG-------------------*/ +/* field: TXCELLDEPTH - Transmit cell depth. These bits indicate the number of cells in the transmit FIFO. */ +#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH(val) BSP_FLD32(val,24, 31) +#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: RXCELLDEPTH - Receive cell depth. These bits indicate the number of cells in the receive FIFO. */ +#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH(val) BSP_FLD32(val,16, 23) +#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: ADDRESSTYPE - Address type */ +#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE(val) BSP_FLD32(val,8, 15) +#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: MACCFIG - MAC configuration value */ +#define TMS570_EMACM_MACCONFIG_MACCFIG(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_MACCONFIG_MACCFIG_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_MACCONFIG_MACCFIG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_EMACM_SOFTRESET-------------------*/ +/* field: SOFTRESET - Software reset. Writing a 1 to this bit causes the EMAC logic to be reset. */ +#define TMS570_EMACM_SOFTRESET_SOFTRESET BSP_BIT32(0) + + +/*-----------------TMS570_EMACM_MACSRCADDRLO-----------------*/ +/* field: MACSRCADDR0 - MAC source address lower 8-0 bits (byte 0) */ +#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0(val) BSP_FLD32(val,8, 15) +#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: MACSRCADDR1 - MAC source address bits 15-8 (byte 1) */ +#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------TMS570_EMACM_MACSRCADDRHI-----------------*/ +/* field: MACSRCADDR2 - MAC source address bits 23-16 (byte 2) */ +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2(val) BSP_FLD32(val,24, 31) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: MACSRCADDR3 - MAC source address bits 31-24 (byte 3) */ +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3(val) BSP_FLD32(val,16, 23) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: MACSRCADDR4 - MAC source address bits 39-32 (byte 4) */ +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4(val) BSP_FLD32(val,8, 15) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: MACSRCADDR5 - MAC source address bits 47-40 (byte 5) */ +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_EMACM_MACHASH1-------------------*/ +/* field: MACHASH1 - Least-significant 32 bits of the hash table corresponding to hash values 0 to 31. */ +/* Whole 32 bits */ + +/*-------------------TMS570_EMACM_MACHASH2-------------------*/ +/* field: MACHASH2 - Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. */ +/* Whole 32 bits */ + +/*-------------------TMS570_EMACM_BOFFTEST-------------------*/ +/* field: RNDNUM - Backoff random number generator. */ +#define TMS570_EMACM_BOFFTEST_RNDNUM(val) BSP_FLD32(val,16, 25) +#define TMS570_EMACM_BOFFTEST_RNDNUM_GET(reg) BSP_FLD32GET(reg,16, 25) +#define TMS570_EMACM_BOFFTEST_RNDNUM_SET(reg,val) BSP_FLD32SET(reg, val,16, 25) + +/* field: COLLCOUNT - Collision count. These bits indicate the number of collisions the current frame has experienced. */ +#define TMS570_EMACM_BOFFTEST_COLLCOUNT(val) BSP_FLD32(val,12, 15) +#define TMS570_EMACM_BOFFTEST_COLLCOUNT_GET(reg) BSP_FLD32GET(reg,12, 15) +#define TMS570_EMACM_BOFFTEST_COLLCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,12, 15) + +/* field: TXBACKOFF - Backoff count. */ +#define TMS570_EMACM_BOFFTEST_TXBACKOFF(val) BSP_FLD32(val,0, 9) +#define TMS570_EMACM_BOFFTEST_TXBACKOFF_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_EMACM_BOFFTEST_TXBACKOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*-------------------TMS570_EMACM_TPACETEST-------------------*/ +/* field: PACEVAL - Pacing register current value. A nonzero value in this field indicates that transmit pacing is active. */ +#define TMS570_EMACM_TPACETEST_PACEVAL(val) BSP_FLD32(val,0, 4) +#define TMS570_EMACM_TPACETEST_PACEVAL_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_EMACM_TPACETEST_PACEVAL_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*--------------------TMS570_EMACM_RXPAUSE--------------------*/ +/* field: PAUSETIMER - Receive pause timer value. */ +#define TMS570_EMACM_RXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15) +#define TMS570_EMACM_RXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_EMACM_RXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_EMACM_TXPAUSE--------------------*/ +/* field: PAUSETIMER - Transmit pause timer value. */ +#define TMS570_EMACM_TXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15) +#define TMS570_EMACM_TXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_EMACM_TXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_EMACM_MACADDRLO-------------------*/ +/* field: VALID - Address valid bit. */ +#define TMS570_EMACM_MACADDRLO_VALID BSP_BIT32(20) + +/* field: MATCHFILT - Match or filter bit */ +#define TMS570_EMACM_MACADDRLO_MATCHFILT BSP_BIT32(19) + +/* field: CHANNEL - Channel select. Determines which receive channel a valid address match will be transferred to. */ +#define TMS570_EMACM_MACADDRLO_CHANNEL(val) BSP_FLD32(val,16, 18) +#define TMS570_EMACM_MACADDRLO_CHANNEL_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_EMACM_MACADDRLO_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: MACADDR0 - MAC address lower 8-0 bits (byte 0) */ +#define TMS570_EMACM_MACADDRLO_MACADDR0(val) BSP_FLD32(val,8, 15) +#define TMS570_EMACM_MACADDRLO_MACADDR0_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_EMACM_MACADDRLO_MACADDR0_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: MACADDR1 - MAC address bits 15-8 (byte 1) */ +#define TMS570_EMACM_MACADDRLO_MACADDR1(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_MACADDRLO_MACADDR1_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_MACADDRLO_MACADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_EMACM_MACADDRHI-------------------*/ +/* field: MACADDR2 - MAC source address bits 23-16 (byte 2) */ +#define TMS570_EMACM_MACADDRHI_MACADDR2(val) BSP_FLD32(val,24, 31) +#define TMS570_EMACM_MACADDRHI_MACADDR2_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_EMACM_MACADDRHI_MACADDR2_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: MACADDR3 - MAC source address bits 31-24 (byte 3) */ +#define TMS570_EMACM_MACADDRHI_MACADDR3(val) BSP_FLD32(val,16, 23) +#define TMS570_EMACM_MACADDRHI_MACADDR3_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_EMACM_MACADDRHI_MACADDR3_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: MACADDR4 - MAC source address bits 39-32 (byte 4) */ +#define TMS570_EMACM_MACADDRHI_MACADDR4(val) BSP_FLD32(val,8, 15) +#define TMS570_EMACM_MACADDRHI_MACADDR4_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_EMACM_MACADDRHI_MACADDR4_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: MACADDR5 - MAC source address bits 47-40 (byte 5). Bit 40 is the group bit. It is forced to 0 and read as 0. */ +#define TMS570_EMACM_MACADDRHI_MACADDR5(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_MACADDRHI_MACADDR5_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_MACADDRHI_MACADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_EMACM_MACINDEX-------------------*/ +/* field: MACINDEX - MAC address index. All eight addresses share the upper 40 bits. */ +#define TMS570_EMACM_MACINDEX_MACINDEX(val) BSP_FLD32(val,0, 2) +#define TMS570_EMACM_MACINDEX_MACINDEX_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_EMACM_MACINDEX_MACINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*---------------------TMS570_EMACM_TXHDP---------------------*/ +/* field: TXnHDP - Transmit channel n DMA Head Descriptor pointer. */ +/* Whole 32 bits */ + +/*---------------------TMS570_EMACM_RXHDP---------------------*/ +/* field: RXnHDP - Receive channel n DMA Head Descriptor pointer. */ +/* Whole 32 bits */ + +/*---------------------TMS570_EMACM_TXCP---------------------*/ +/* field: TXnCP - Transmit channel n completion pointer register is written by the host with the buffer descriptor */ +/* Whole 32 bits */ + +/*---------------------TMS570_EMACM_RXCP---------------------*/ +/* field: RXnCP - Receive channel n completion pointer register is written by the host with the buffer descriptor */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_EMACM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h new file mode 100644 index 0000000000..0810fd097f --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h @@ -0,0 +1,468 @@ +/* The header file is generated by make_header.py from EMIF.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_EMIF +#define LIBBSP_ARM_TMS570_EMIF + +#include + +typedef struct{ + uint32_t MIDR; /*Module ID Register*/ + uint32_t AWCC; /*Asynchronous Wait Cycle Configuration Register*/ + uint32_t SDCR; /*SDRAM Configuration Register*/ + uint32_t SDRCR; /*SDRAM Refresh Control Register*/ + uint32_t CE2CFG; /*Asynchronous 1 Configuration Register*/ + uint32_t CE3CFG; /*Asynchronous 2 Configuration Register*/ + uint32_t CE4CFG; /*Asynchronous 3 Configuration Register*/ + uint32_t CE5CFG; /*Asynchronous 4 Configuration Register*/ + uint32_t SDTIMR; /*SDRAM Timing Register*/ + uint8_t reserved1 [24]; + uint32_t SDSRETR; /*SDRAM Self Refresh Exit Timing Register*/ + uint32_t INTRAW; /*EMIF Interrupt Raw Register*/ + uint32_t INTMSK; /*EMIF Interrupt Mask Register*/ + uint32_t INTMSKSET; /*EMIF Interrupt Mask Set Register*/ + uint32_t INTMSKCLR; /*EMIF Interrupt Mask Clear Register*/ + uint8_t reserved2 [24]; + uint32_t PMCR; /*Page Mode Control Register*/ +} tms570_emif_t; + + +/*----------------------TMS570_EMIF_MIDR----------------------*/ +/* field: REV - Module ID of EMIF. See the device-specific data manual. */ +/* Whole 32 bits */ + +/*----------------------TMS570_EMIF_AWCC----------------------*/ +/* field: WP1 - EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin. */ +#define TMS570_EMIF_AWCC_WP1 BSP_BIT32(29) + +/* field: WP0 - EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin. */ +#define TMS570_EMIF_AWCC_WP0 BSP_BIT32(28) + +/* field: CS5_WAIT - Chip Select 5 WAIT signal selection. */ +#define TMS570_EMIF_AWCC_CS5_WAIT(val) BSP_FLD32(val,22, 23) +#define TMS570_EMIF_AWCC_CS5_WAIT_GET(reg) BSP_FLD32GET(reg,22, 23) +#define TMS570_EMIF_AWCC_CS5_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,22, 23) + +/* field: CS4_WAIT - Chip Select 4 WAIT signal selection. */ +#define TMS570_EMIF_AWCC_CS4_WAIT(val) BSP_FLD32(val,20, 21) +#define TMS570_EMIF_AWCC_CS4_WAIT_GET(reg) BSP_FLD32GET(reg,20, 21) +#define TMS570_EMIF_AWCC_CS4_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,20, 21) + +/* field: CS3_WAIT - be used for memory accesses to chip select 3 memory space. */ +#define TMS570_EMIF_AWCC_CS3_WAIT(val) BSP_FLD32(val,18, 19) +#define TMS570_EMIF_AWCC_CS3_WAIT_GET(reg) BSP_FLD32GET(reg,18, 19) +#define TMS570_EMIF_AWCC_CS3_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,18, 19) + +/* field: CS2_WAIT - Chip Select 2 WAIT signal selection. */ +#define TMS570_EMIF_AWCC_CS2_WAIT(val) BSP_FLD32(val,16, 17) +#define TMS570_EMIF_AWCC_CS2_WAIT_GET(reg) BSP_FLD32GET(reg,16, 17) +#define TMS570_EMIF_AWCC_CS2_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,16, 17) + +/* field: MAX_EXT_WAIT - Maximum extended wait cycles. */ +#define TMS570_EMIF_AWCC_MAX_EXT_WAIT(val) BSP_FLD32(val,0, 7) +#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_EMIF_SDCR----------------------*/ +/* field: SR - Self-Refresh mode bit. */ +#define TMS570_EMIF_SDCR_SR BSP_BIT32(31) + +/* field: PD - Power Down bit. This bit controls entering and exiting of the power-down mode. */ +#define TMS570_EMIF_SDCR_PD BSP_BIT32(30) + +/* field: PDWR - Perform refreshes during power down. */ +#define TMS570_EMIF_SDCR_PDWR BSP_BIT32(29) + +/* field: NM - Narrow mode bit. This bit defines whether a 16- or 32-bit-wide SDRAM is connected to the EMIF. */ +#define TMS570_EMIF_SDCR_NM BSP_BIT32(14) + +/* field: CL - CAS Latency. */ +#define TMS570_EMIF_SDCR_CL(val) BSP_FLD32(val,9, 11) +#define TMS570_EMIF_SDCR_CL_GET(reg) BSP_FLD32GET(reg,9, 11) +#define TMS570_EMIF_SDCR_CL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11) + +/* field: BIT11_9LOCK - Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */ +#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_BIT32(8) + +/* field: IBANK - Internal SDRAM Bank size. */ +#define TMS570_EMIF_SDCR_IBANK(val) BSP_FLD32(val,4, 6) +#define TMS570_EMIF_SDCR_IBANK_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_EMIF_SDCR_IBANK_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: PAGESIZE - Page Size. This field defines the internal page size of connected SDRAM devices. */ +#define TMS570_EMIF_SDCR_PAGESIZE(val) BSP_FLD32(val,0, 2) +#define TMS570_EMIF_SDCR_PAGESIZE_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_EMIF_SDCR_PAGESIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*---------------------TMS570_EMIF_SDRCR---------------------*/ +/* field: RR - Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles. */ +#define TMS570_EMIF_SDRCR_RR(val) BSP_FLD32(val,0, 12) +#define TMS570_EMIF_SDRCR_RR_GET(reg) BSP_FLD32GET(reg,0, 12) +#define TMS570_EMIF_SDRCR_RR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12) + + +/*---------------------TMS570_EMIF_CE2CFG---------------------*/ +/* field: SS - Select Strobe bit. */ +#define TMS570_EMIF_CE2CFG_SS BSP_BIT32(31) + +/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */ +#define TMS570_EMIF_CE2CFG_EW BSP_BIT32(30) + +/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE2CFG_W_SETUP(val) BSP_FLD32(val,26, 29) +#define TMS570_EMIF_CE2CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29) +#define TMS570_EMIF_CE2CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29) + +/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE2CFG_W_STROBE(val) BSP_FLD32(val,20, 25) +#define TMS570_EMIF_CE2CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25) +#define TMS570_EMIF_CE2CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) + +/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE2CFG_W_HOLD(val) BSP_FLD32(val,17, 19) +#define TMS570_EMIF_CE2CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19) +#define TMS570_EMIF_CE2CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19) + +/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE2CFG_R_SETUP(val) BSP_FLD32(val,13, 16) +#define TMS570_EMIF_CE2CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16) +#define TMS570_EMIF_CE2CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16) + +/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE2CFG_R_STROBE(val) BSP_FLD32(val,7, 12) +#define TMS570_EMIF_CE2CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12) +#define TMS570_EMIF_CE2CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12) + +/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE2CFG_R_HOLD(val) BSP_FLD32(val,4, 6) +#define TMS570_EMIF_CE2CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_EMIF_CE2CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TA - Minimum Turn-Around time. */ +#define TMS570_EMIF_CE2CFG_TA(val) BSP_FLD32(val,2, 3) +#define TMS570_EMIF_CE2CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_EMIF_CE2CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */ +#define TMS570_EMIF_CE2CFG_ASIZE(val) BSP_FLD32(val,0, 1) +#define TMS570_EMIF_CE2CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_EMIF_CE2CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_EMIF_CE3CFG---------------------*/ +/* field: SS - Select Strobe bit. */ +#define TMS570_EMIF_CE3CFG_SS BSP_BIT32(31) + +/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */ +#define TMS570_EMIF_CE3CFG_EW BSP_BIT32(30) + +/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE3CFG_W_SETUP(val) BSP_FLD32(val,26, 29) +#define TMS570_EMIF_CE3CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29) +#define TMS570_EMIF_CE3CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29) + +/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE3CFG_W_STROBE(val) BSP_FLD32(val,20, 25) +#define TMS570_EMIF_CE3CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25) +#define TMS570_EMIF_CE3CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) + +/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE3CFG_W_HOLD(val) BSP_FLD32(val,17, 19) +#define TMS570_EMIF_CE3CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19) +#define TMS570_EMIF_CE3CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19) + +/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE3CFG_R_SETUP(val) BSP_FLD32(val,13, 16) +#define TMS570_EMIF_CE3CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16) +#define TMS570_EMIF_CE3CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16) + +/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE3CFG_R_STROBE(val) BSP_FLD32(val,7, 12) +#define TMS570_EMIF_CE3CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12) +#define TMS570_EMIF_CE3CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12) + +/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE3CFG_R_HOLD(val) BSP_FLD32(val,4, 6) +#define TMS570_EMIF_CE3CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_EMIF_CE3CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TA - Minimum Turn-Around time. */ +#define TMS570_EMIF_CE3CFG_TA(val) BSP_FLD32(val,2, 3) +#define TMS570_EMIF_CE3CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_EMIF_CE3CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */ +#define TMS570_EMIF_CE3CFG_ASIZE(val) BSP_FLD32(val,0, 1) +#define TMS570_EMIF_CE3CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_EMIF_CE3CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_EMIF_CE4CFG---------------------*/ +/* field: SS - Select Strobe bit. */ +#define TMS570_EMIF_CE4CFG_SS BSP_BIT32(31) + +/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */ +#define TMS570_EMIF_CE4CFG_EW BSP_BIT32(30) + +/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE4CFG_W_SETUP(val) BSP_FLD32(val,26, 29) +#define TMS570_EMIF_CE4CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29) +#define TMS570_EMIF_CE4CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29) + +/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE4CFG_W_STROBE(val) BSP_FLD32(val,20, 25) +#define TMS570_EMIF_CE4CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25) +#define TMS570_EMIF_CE4CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) + +/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE4CFG_W_HOLD(val) BSP_FLD32(val,17, 19) +#define TMS570_EMIF_CE4CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19) +#define TMS570_EMIF_CE4CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19) + +/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE4CFG_R_SETUP(val) BSP_FLD32(val,13, 16) +#define TMS570_EMIF_CE4CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16) +#define TMS570_EMIF_CE4CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16) + +/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE4CFG_R_STROBE(val) BSP_FLD32(val,7, 12) +#define TMS570_EMIF_CE4CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12) +#define TMS570_EMIF_CE4CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12) + +/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE4CFG_R_HOLD(val) BSP_FLD32(val,4, 6) +#define TMS570_EMIF_CE4CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_EMIF_CE4CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TA - Minimum Turn-Around time. */ +#define TMS570_EMIF_CE4CFG_TA(val) BSP_FLD32(val,2, 3) +#define TMS570_EMIF_CE4CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_EMIF_CE4CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */ +#define TMS570_EMIF_CE4CFG_ASIZE(val) BSP_FLD32(val,0, 1) +#define TMS570_EMIF_CE4CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_EMIF_CE4CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_EMIF_CE5CFG---------------------*/ +/* field: SS - Select Strobe bit. */ +#define TMS570_EMIF_CE5CFG_SS BSP_BIT32(31) + +/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */ +#define TMS570_EMIF_CE5CFG_EW BSP_BIT32(30) + +/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_W_SETUP(val) BSP_FLD32(val,26, 29) +#define TMS570_EMIF_CE5CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29) +#define TMS570_EMIF_CE5CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29) + +/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_W_STROBE(val) BSP_FLD32(val,20, 25) +#define TMS570_EMIF_CE5CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25) +#define TMS570_EMIF_CE5CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) + +/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_W_HOLD(val) BSP_FLD32(val,17, 19) +#define TMS570_EMIF_CE5CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19) +#define TMS570_EMIF_CE5CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19) + +/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_R_SETUP(val) BSP_FLD32(val,13, 16) +#define TMS570_EMIF_CE5CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16) +#define TMS570_EMIF_CE5CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16) + +/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_R_STROBE(val) BSP_FLD32(val,7, 12) +#define TMS570_EMIF_CE5CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12) +#define TMS570_EMIF_CE5CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12) + +/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_R_HOLD(val) BSP_FLD32(val,4, 6) +#define TMS570_EMIF_CE5CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_EMIF_CE5CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TA - and writes, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_TA(val) BSP_FLD32(val,2, 3) +#define TMS570_EMIF_CE5CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_EMIF_CE5CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */ +#define TMS570_EMIF_CE5CFG_ASIZE(val) BSP_FLD32(val,0, 1) +#define TMS570_EMIF_CE5CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_EMIF_CE5CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_EMIF_SDTIMR---------------------*/ +/* field: T_RFC - Specifies the Trfc value of the SDRAM. */ +#define TMS570_EMIF_SDTIMR_T_RFC(val) BSP_FLD32(val,27, 31) +#define TMS570_EMIF_SDTIMR_T_RFC_GET(reg) BSP_FLD32GET(reg,27, 31) +#define TMS570_EMIF_SDTIMR_T_RFC_SET(reg,val) BSP_FLD32SET(reg, val,27, 31) + +/* field: T_RP - Precharge (PRE) to Activate (ACTV) or Refresh (REFR) command, minus 1: */ +#define TMS570_EMIF_SDTIMR_T_RP(val) BSP_FLD32(val,24, 26) +#define TMS570_EMIF_SDTIMR_T_RP_GET(reg) BSP_FLD32GET(reg,24, 26) +#define TMS570_EMIF_SDTIMR_T_RP_SET(reg,val) BSP_FLD32SET(reg, val,24, 26) + +/* field: T_RCD - Specifies the Trcd value of the SDRAM. */ +#define TMS570_EMIF_SDTIMR_T_RCD(val) BSP_FLD32(val,20, 22) +#define TMS570_EMIF_SDTIMR_T_RCD_GET(reg) BSP_FLD32GET(reg,20, 22) +#define TMS570_EMIF_SDTIMR_T_RCD_SET(reg,val) BSP_FLD32SET(reg, val,20, 22) + +/* field: T_WR - Specifies the Twr value of the SDRAM. */ +#define TMS570_EMIF_SDTIMR_T_WR(val) BSP_FLD32(val,16, 18) +#define TMS570_EMIF_SDTIMR_T_WR_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_EMIF_SDTIMR_T_WR_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: T_RAS - Specifies the Tras value of the SDRAM. */ +#define TMS570_EMIF_SDTIMR_T_RAS(val) BSP_FLD32(val,12, 15) +#define TMS570_EMIF_SDTIMR_T_RAS_GET(reg) BSP_FLD32GET(reg,12, 15) +#define TMS570_EMIF_SDTIMR_T_RAS_SET(reg,val) BSP_FLD32SET(reg, val,12, 15) + +/* field: T_RC - Specifies the Trc value of the SDRAM. */ +#define TMS570_EMIF_SDTIMR_T_RC(val) BSP_FLD32(val,8, 11) +#define TMS570_EMIF_SDTIMR_T_RC_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_EMIF_SDTIMR_T_RC_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: T_RRD - Specifies the Trrd value of the SDRAM. */ +#define TMS570_EMIF_SDTIMR_T_RRD(val) BSP_FLD32(val,4, 6) +#define TMS570_EMIF_SDTIMR_T_RRD_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_EMIF_SDTIMR_T_RRD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + + +/*--------------------TMS570_EMIF_SDSRETR--------------------*/ +/* field: T_XS - This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, */ +#define TMS570_EMIF_SDSRETR_T_XS(val) BSP_FLD32(val,0, 4) +#define TMS570_EMIF_SDSRETR_T_XS_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_EMIF_SDSRETR_T_XS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*---------------------TMS570_EMIF_INTRAW---------------------*/ +/* field: WR - Wait Rise. */ +#define TMS570_EMIF_INTRAW_WR BSP_BIT32(2) + +/* field: LT - Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size. */ +#define TMS570_EMIF_INTRAW_LT BSP_BIT32(1) + +/* field: AT - Asynchronous Timeout. */ +#define TMS570_EMIF_INTRAW_AT BSP_BIT32(0) + + +/*---------------------TMS570_EMIF_INTMSK---------------------*/ +/* field: WR_MASKED - Wait Rise Masked. */ +#define TMS570_EMIF_INTMSK_WR_MASKED BSP_BIT32(2) + +/* field: LT_MASKED - Masked Line Trap. */ +#define TMS570_EMIF_INTMSK_LT_MASKED BSP_BIT32(1) + +/* field: AT_MASKED - Asynchronous Timeout Masked. */ +#define TMS570_EMIF_INTMSK_AT_MASKED BSP_BIT32(0) + + +/*-------------------TMS570_EMIF_INTMSKSET-------------------*/ +/* field: WR_MASK_SET - Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. */ +#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_BIT32(2) + +/* field: LT_MASK_SET - LT_MASK_SET Mask set for LT_MASKED bit in the EMIF interrupt mask register (INTMSK). */ +#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_BIT32(1) + +/* field: AT_MASK_SET - Asynchronous Timeout Mask Set. */ +#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_BIT32(0) + + +/*-------------------TMS570_EMIF_INTMSKCLR-------------------*/ +/* field: WR_MASK_CLR - Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. */ +#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_BIT32(2) + +/* field: LT_MASK_CLR - 1 to this bit clears this bit, clears the LT_MASK_SET bit in the EMIF interrupt mask set register */ +#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_BIT32(1) + +/* field: AT_MASK_CLR - Asynchronous Timeout Mask Clear. */ +#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_BIT32(0) + + +/*----------------------TMS570_EMIF_PMCR----------------------*/ +/* field: CS5_PG_DEL - Page access delay for NOR Flash connected on CS5. CS5 is not available on this device. */ +#define TMS570_EMIF_PMCR_CS5_PG_DEL(val) BSP_FLD32(val,26, 31) +#define TMS570_EMIF_PMCR_CS5_PG_DEL_GET(reg) BSP_FLD32GET(reg,26, 31) +#define TMS570_EMIF_PMCR_CS5_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,26, 31) + +/* field: CS5_PG_SIZE - Page Size for NOR Flash connected on CS5. CS5 is not available on this device. */ +#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_BIT32(25) + +/* field: CS5_PG_MD_EN - Page Mode enable for NOR Flash connected on CS5. CS5 is not available on this device. */ +#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_BIT32(24) + +/* field: CS4_PG_DEL - Page access delay for NOR Flash connected on CS4. */ +#define TMS570_EMIF_PMCR_CS4_PG_DEL(val) BSP_FLD32(val,18, 23) +#define TMS570_EMIF_PMCR_CS4_PG_DEL_GET(reg) BSP_FLD32GET(reg,18, 23) +#define TMS570_EMIF_PMCR_CS4_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,18, 23) + +/* field: CS4_PG_SIZE - Page Size for NOR Flash connected on CS4. */ +#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_BIT32(17) + +/* field: CS4_PG_MD_EN - Page Mode enable for NOR Flash connected on CS4. */ +#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_BIT32(16) + +/* field: CS3_PG_DEL - the page read data to be valid, minus one cycle. This value must not be cleared to 0. */ +#define TMS570_EMIF_PMCR_CS3_PG_DEL(val) BSP_FLD32(val,10, 15) +#define TMS570_EMIF_PMCR_CS3_PG_DEL_GET(reg) BSP_FLD32GET(reg,10, 15) +#define TMS570_EMIF_PMCR_CS3_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,10, 15) + +/* field: CS3_PG_SIZE - Page Size for NOR Flash connected on CS3. */ +#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_BIT32(9) + +/* field: CS3_PG_MD_EN - Page Mode enable for NOR Flash connected on CS3. */ +#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_BIT32(8) + +/* field: CS2_PG_DEL - Page access delay for NOR Flash connected on CS2. */ +#define TMS570_EMIF_PMCR_CS2_PG_DEL(val) BSP_FLD32(val,2, 7) +#define TMS570_EMIF_PMCR_CS2_PG_DEL_GET(reg) BSP_FLD32GET(reg,2, 7) +#define TMS570_EMIF_PMCR_CS2_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 7) + +/* field: CS2_PG_SIZE - Page Size for NOR Flash connected on CS2. */ +#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_BIT32(1) + +/* field: CS2_PG_MD_EN - Page Mode enable for NOR Flash connected on CS2. */ +#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_EMIF */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h new file mode 100644 index 0000000000..3ea4b6b43c --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h @@ -0,0 +1,170 @@ +/* The header file is generated by make_header.py from ESM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_ESM +#define LIBBSP_ARM_TMS570_ESM + +#include + +typedef struct{ + uint32_t EEPAPR1; /*ESM Enable ERROR Pin Action/Response Register 1*/ + uint32_t DEPAPR1; /*ESM Disable ERROR Pin Action/Response Register 1*/ + uint32_t IESR1; /*ESM Interrupt Enable Set/Status Register 1*/ + uint32_t IECR1; /*ESM Interrupt Enable Clear/Status Register 1*/ + uint32_t ILSR1; /*Interrupt Level Set/Status Register 1*/ + uint32_t ILCR1; /*Interrupt Level Clear/Status Register 1*/ + uint32_t SR[3]; /*ESM Status Register*/ + uint32_t EPSR; /*ESM ERROR Pin Status Register*/ + uint32_t IOFFHR; /*ESM Interrupt Offset High Register*/ + uint32_t IOFFLR; /*ESM Interrupt Offset Low Register*/ + uint32_t LTCR; /*ESM Low-Time Counter Register*/ + uint32_t LTCPR; /*ESM Low-Time Counter Preload Register*/ + uint32_t EKR; /*ESM Error Key Register*/ + uint32_t SSR2; /*ESM Status Shadow Register 2*/ + uint32_t IEPSR4; /*ESM Influence ERROR Pin Set/Status Register 4*/ + uint32_t IEPCR4; /*ESM Influence ERROR Pin Clear/Status Register 4*/ + uint32_t IESR4; /*ESM Interrupt Enable Set/Status Register 4*/ + uint32_t IECR4; /*ESM Interrupt Enable Clear/Status Register 4*/ + uint32_t ILSR4; /*Interrupt Level Set/Status Register 4*/ + uint32_t ILCR4; /*Interrupt Level Clear/Status Register 4*/ + uint32_t SR4; /*ESM Status Register 4*/ +} tms570_esm_t; + + +/*---------------------TMS570_ESM_EEPAPR1---------------------*/ +/* field: IEPSET - Enable ERROR Pin Action/Response on Group 1. */ +/* Whole 32 bits */ + +/*---------------------TMS570_ESM_DEPAPR1---------------------*/ +/* field: IEPCLR - Disable ERROR Pin Action/Response on Group 1. */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_IESR1----------------------*/ +/* field: INTENSET - Set interrupt Enable */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_IECR1----------------------*/ +/* field: INTENCLR - Clear Interrupt Enable */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_ILSR1----------------------*/ +/* field: INTLVLSET - Set Interrupt Priority */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_ILCR1----------------------*/ +/* field: INTLVLCLR - Clear Interrupt Priority. */ +/* Whole 32 bits */ + +/*-----------------------TMS570_ESM_SR-----------------------*/ +/* field: ESF - Error Status Flag. Provides status information on a pending error. */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_EPSR----------------------*/ +/* field: EPSF - ERROR Pin Status Flag. Provides status information for the ERROR Pin. */ +#define TMS570_ESM_EPSR_EPSF BSP_BIT32(0) + + +/*---------------------TMS570_ESM_IOFFHR---------------------*/ +/* field: INTOFFH - Offset High Level Interrupt. */ +#define TMS570_ESM_IOFFHR_INTOFFH(val) BSP_FLD32(val,0, 6) +#define TMS570_ESM_IOFFHR_INTOFFH_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_ESM_IOFFHR_INTOFFH_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + +/*---------------------TMS570_ESM_IOFFLR---------------------*/ +/* field: INTOFFL - Offset Low Level Interrupt. */ +#define TMS570_ESM_IOFFLR_INTOFFL(val) BSP_FLD32(val,0, 6) +#define TMS570_ESM_IOFFLR_INTOFFL_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_ESM_IOFFLR_INTOFFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + +/*----------------------TMS570_ESM_LTCR----------------------*/ +/* field: LTC - ERROR Pin Low-Time Counter */ +#define TMS570_ESM_LTCR_LTC(val) BSP_FLD32(val,0, 15) +#define TMS570_ESM_LTCR_LTC_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_ESM_LTCR_LTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_ESM_LTCPR----------------------*/ +/* field: LTCP - ERROR Pin Low-Time Counter Pre-load Value */ +#define TMS570_ESM_LTCPR_LTCP(val) BSP_FLD32(val,0, 15) +#define TMS570_ESM_LTCPR_LTCP_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_ESM_LTCPR_LTCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-----------------------TMS570_ESM_EKR-----------------------*/ +/* field: EKEY - Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. */ +#define TMS570_ESM_EKR_EKEY(val) BSP_FLD32(val,0, 3) +#define TMS570_ESM_EKR_EKEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_ESM_EKR_EKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*----------------------TMS570_ESM_SSR2----------------------*/ +/* field: ESF - Error Status Flag. Shadow register for status information on pending error. */ +/* Whole 32 bits */ + +/*---------------------TMS570_ESM_IEPSR4---------------------*/ +/* field: IEPSET - Set Influence on ERROR Pin */ +/* Whole 32 bits */ + +/*---------------------TMS570_ESM_IEPCR4---------------------*/ +/* field: IEPCLR - Clear Influence on ERROR Pin */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_IESR4----------------------*/ +/* field: INTENSET - Set Interrupt Enable */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_IECR4----------------------*/ +/* field: INTENCLR - Clear Interrupt Enable */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_ILSR4----------------------*/ +/* field: INTLVLSET - Set Interrupt Level */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_ILCR4----------------------*/ +/* field: INTLVLCLR - Clear Interrupt Level */ +/* Whole 32 bits */ + +/*-----------------------TMS570_ESM_SR4-----------------------*/ +/* field: ESF - Error Status Flag. Provides status information on a pending error. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_ESM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h new file mode 100644 index 0000000000..6c5a127d0b --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h @@ -0,0 +1,675 @@ +/* The header file is generated by make_header.py from FLASH.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_FLASH +#define LIBBSP_ARM_TMS570_FLASH + +#include + +typedef struct{ + uint32_t FRDCNTL; /*Flash Option Control Register*/ + uint8_t reserved1 [4]; + uint32_t FEDACTRL1; /*Flash Error Detection and Correction Control Register 1*/ + uint32_t FEDACTRL2; /*Flash Error Detection and Correction Control Register 2*/ + uint32_t FCORERRCNT; /*Flash Correctable Error Count Register*/ + uint32_t FCORERRADD; /*Flash Correctable Error Address Register*/ + uint32_t FCORERRPOS; /*Flash Correctable Error Position Register*/ + uint32_t FEDACSTATUS; /*Flash Error Detection and Correction Status Register*/ + uint32_t FUNCERRADD; /*Flash Un-Correctable Error Address Register*/ + uint32_t FEDACSDIS; /*Flash Error Detection and Correction Sector Disable Register*/ + uint32_t FPRIMADDTAG; /*Flash Primary Address Tag Register*/ + uint32_t FDUPADDTAG; /*Flash Duplicate Address Tag Register*/ + uint32_t FBPROT; /*Flash Bank Protection Register*/ + uint32_t FBSE; /*Flash Bank Sector Enable Register*/ + uint32_t FBBUSY; /*Flash Bank Busy Register*/ + uint32_t FBAC; /*Flash Bank Access Control Register*/ + uint32_t FBFALLBACK; /*Flash Bank Fallback Power Register*/ + uint32_t FBPRDY; /*Flash Bank/Pump Ready Register*/ + uint32_t FPAC1; /*Flash Pump Access Control Register 1*/ + uint32_t FPAC2; /*Flash Pump Access Control Register 2*/ + uint32_t FMAC; /*Flash Module Access Control Register*/ + uint32_t FMSTAT; /*Flash Module Status Register*/ + uint32_t FEMUDMSW; /*EEPROM Emulation Data MSW Register*/ + uint32_t FEMUDLSW; /*EEPROM Emulation Data LSW Register*/ + uint32_t FEMUECC; /*EEPROM Emulation ECC Register*/ + uint8_t reserved2 [4]; + uint32_t FEMUADDR; /*EEPROM Emulation Address Register*/ + uint32_t FDIAGCTRL; /*Diagnostic Control Register*/ + uint32_t FRAWDATAH; /*Uncorrected Raw Data High Register*/ + uint32_t FRAWDATAL; /*Uncorrected Raw Data Low Register*/ + uint32_t FRAWECC; /*Uncorrected Raw ECC Register*/ + uint32_t FPAROVR; /*Parity Override Register*/ + uint8_t reserved3 [64]; + uint32_t FEDACSDIS2; /*Flash Error Detection and Correction Sector Disable Register 2*/ + uint8_t reserved4 [452]; + uint32_t FSMWRENA; /*FSM Register Write Enable*/ + uint8_t reserved5 [24]; + uint32_t FSMSECTOR; /*FSM Sector Register*/ + uint8_t reserved6 [16]; + uint32_t EEPROMCONFIG; /*EEPROM Emulation Configuration Register*/ + uint8_t reserved7 [76]; + uint32_t EECTRL1; /*EEPROM Emulation Error Detection and Correction Control Register 1*/ + uint32_t EECTRL2; /*EEPROM Emulation Error Detection and Correction Control Register 2*/ + uint32_t EECORERRCNT; /*EEPROM Emulation Correctable Error Count Register*/ + uint32_t EECORERRADD; /*EEPROM Emulation Correctable Error Address Register*/ + uint32_t EECORERRPOS; /*EEPROM Emulation Correctable Error Bit Position Register*/ + uint32_t EESTATUS; /*EEPROM Emulation Error Status Register*/ + uint32_t EEUNCERRADD; /*EEPROM Emulation Un-Correctable Error Address Register*/ + uint8_t reserved8 [220]; + uint32_t FCFGBANK; /*Flash Bank Configuration Register*/ +} tms570_flash_t; + + +/*--------------------TMS570_FLASH_FRDCNTL--------------------*/ +/* field: RWAIT - Random/data Read Wait State */ +#define TMS570_FLASH_FRDCNTL_RWAIT(val) BSP_FLD32(val,8, 11) +#define TMS570_FLASH_FRDCNTL_RWAIT_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_FLASH_FRDCNTL_RWAIT_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: ASWSTEN - Address Setup Wait State Enable */ +#define TMS570_FLASH_FRDCNTL_ASWSTEN BSP_BIT32(4) + +/* field: ENPIPE - Enable Pipeline Mode */ +#define TMS570_FLASH_FRDCNTL_ENPIPE BSP_BIT32(0) + + +/*-------------------TMS570_FLASH_FEDACTRL1-------------------*/ +/* field: SUSP_IGNR - Suspend Ignore. */ +#define TMS570_FLASH_FEDACTRL1_SUSP_IGNR BSP_BIT32(24) + +/* field: EDACMODE - Error Correction Mode. */ +#define TMS570_FLASH_FEDACTRL1_EDACMODE(val) BSP_FLD32(val,16, 19) +#define TMS570_FLASH_FEDACTRL1_EDACMODE_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLASH_FEDACTRL1_EDACMODE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: EOFEN - Event on Ones Fail Enable */ +#define TMS570_FLASH_FEDACTRL1_EOFEN BSP_BIT32(10) + +/* field: EZFEN - Event on Zeros Fail Enable */ +#define TMS570_FLASH_FEDACTRL1_EZFEN BSP_BIT32(9) + +/* field: EPEN - Error Profiling Enable. */ +#define TMS570_FLASH_FEDACTRL1_EPEN BSP_BIT32(8) + +/* field: EDACEN - Error Detection and Correction Enable */ +#define TMS570_FLASH_FEDACTRL1_EDACEN(val) BSP_FLD32(val,0, 3) +#define TMS570_FLASH_FEDACTRL1_EDACEN_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_FLASH_FEDACTRL1_EDACEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_FLASH_FEDACTRL2-------------------*/ +/* field: SEC_THRESHOLD - Single Error Correction Threshold */ +#define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD(val) BSP_FLD32(val,0, 15) +#define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_FLASH_FCORERRCNT------------------*/ +/* field: FERRCNT - Single Error Correction Count */ +#define TMS570_FLASH_FCORERRCNT_FERRCNT(val) BSP_FLD32(val,0, 15) +#define TMS570_FLASH_FCORERRCNT_FERRCNT_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLASH_FCORERRCNT_FERRCNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_FLASH_FCORERRADD------------------*/ +/* field: COR_ERR_ADD - Correctable Error Address */ +#define TMS570_FLASH_FCORERRADD_COR_ERR_ADD(val) BSP_FLD32(val,3, 31) +#define TMS570_FLASH_FCORERRADD_COR_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31) +#define TMS570_FLASH_FCORERRADD_COR_ERR_ADD_SET(reg,val) BSP_FLD32SET(reg, val,3, 31) + +/* field: B_OFF - Byte Offset */ +#define TMS570_FLASH_FCORERRADD_B_OFF(val) BSP_FLD32(val,0, 2) +#define TMS570_FLASH_FCORERRADD_B_OFF_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_FLASH_FCORERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*------------------TMS570_FLASH_FCORERRPOS------------------*/ +/* field: BUS2 - Bus 2 Error */ +#define TMS570_FLASH_FCORERRPOS_BUS2 BSP_BIT32(9) + +/* field: TYPE - ErrorType */ +#define TMS570_FLASH_FCORERRPOS_TYPE BSP_BIT32(8) + +/* field: ERR_POS - The bit address of the single bit error */ +#define TMS570_FLASH_FCORERRPOS_ERR_POS(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FCORERRPOS_ERR_POS_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FCORERRPOS_ERR_POS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_FLASH_FEDACSTATUS------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +#define TMS570_FLASH_FEDACSTATUS_Reserved(val) BSP_FLD32(val,26, 31) +#define TMS570_FLASH_FEDACSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,26, 31) +#define TMS570_FLASH_FEDACSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,26, 31) + +/* field: FSM_DONE - Flash State Machine Done */ +#define TMS570_FLASH_FEDACSTATUS_FSM_DONE BSP_BIT32(24) + +/* field: COMB2_MAL_G - Bus 2 Compare Malfunction Flag. */ +#define TMS570_FLASH_FEDACSTATUS_COMB2_MAL_G BSP_BIT32(19) + +/* field: ECC_B2_MAL_ - Bus 2 ECC Malfunction Error Flag */ +#define TMS570_FLASH_FEDACSTATUS_ECC_B2_MAL_ BSP_BIT32(18) + +/* field: B2_UNC_ERR - Bus 2 uncorrectable error */ +#define TMS570_FLASH_FEDACSTATUS_B2_UNC_ERR BSP_BIT32(17) + +/* field: B2_COR_ERR - Bus 2 Correctable Error */ +#define TMS570_FLASH_FEDACSTATUS_B2_COR_ERR BSP_BIT32(16) + +/* field: D_UNC_ERR - Diagnostic Uncorrectable Error */ +#define TMS570_FLASH_FEDACSTATUS_D_UNC_ERR BSP_BIT32(12) + +/* field: ADD_TAG_ERR - Address Tag Register Error Flag */ +#define TMS570_FLASH_FEDACSTATUS_ADD_TAG_ERR BSP_BIT32(11) + +/* field: ADD_PAR_ERR - Address Parity Error Flag */ +#define TMS570_FLASH_FEDACSTATUS_ADD_PAR_ERR BSP_BIT32(10) + +/* field: B1_UNC_ERR - Bus 1 Uncorrectable Error Flag */ +#define TMS570_FLASH_FEDACSTATUS_B1_UNC_ERR BSP_BIT32(8) + +/* field: D_CORR_ERR - Diagnostic Correctable Error Status Flag */ +#define TMS570_FLASH_FEDACSTATUS_D_CORR_ERR BSP_BIT32(3) + +/* field: ERR_ONE_FLG - Error on One Fail Status Flag */ +#define TMS570_FLASH_FEDACSTATUS_ERR_ONE_FLG BSP_BIT32(2) + +/* field: ERR_ZERO__FLG - Error on Zero Fail Status Flag */ +#define TMS570_FLASH_FEDACSTATUS_ERR_ZERO__FLG BSP_BIT32(1) + +/* field: ERR_PRF_FLG - Error Profiling Status Flag */ +#define TMS570_FLASH_FEDACSTATUS_ERR_PRF_FLG BSP_BIT32(0) + + +/*------------------TMS570_FLASH_FUNCERRADD------------------*/ +/* field: UNC_ERR_ADD - Un-correctable Error Address */ +#define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD(val) BSP_FLD32(val,3, 31) +#define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31) +#define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD_SET(reg,val) BSP_FLD32SET(reg, val,3, 31) + +/* field: B_OFF - Byte offset */ +#define TMS570_FLASH_FUNCERRADD_B_OFF(val) BSP_FLD32(val,0, 2) +#define TMS570_FLASH_FUNCERRADD_B_OFF_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_FLASH_FUNCERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-------------------TMS570_FLASH_FEDACSDIS-------------------*/ +/* field: BankID1_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS_BankID1_Inverse(val) BSP_FLD32(val,29, 31) +#define TMS570_FLASH_FEDACSDIS_BankID1_Inverse_GET(reg) BSP_FLD32GET(reg,29, 31) +#define TMS570_FLASH_FEDACSDIS_BankID1_Inverse_SET(reg,val) BSP_FLD32SET(reg, val,29, 31) + +/* field: SectorID1_inverse - The sector ID inverse bits are used with the sector ID bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS_SectorID1_inverse(val) BSP_FLD32(val,24, 27) +#define TMS570_FLASH_FEDACSDIS_SectorID1_inverse_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_FLASH_FEDACSDIS_SectorID1_inverse_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: BankID1 - The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS_BankID1(val) BSP_FLD32(val,21, 23) +#define TMS570_FLASH_FEDACSDIS_BankID1_GET(reg) BSP_FLD32GET(reg,21, 23) +#define TMS570_FLASH_FEDACSDIS_BankID1_SET(reg,val) BSP_FLD32SET(reg, val,21, 23) + +/* field: SectorID1 - The sector ID bits are used with the sector ID inverse bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS_SectorID1(val) BSP_FLD32(val,16, 19) +#define TMS570_FLASH_FEDACSDIS_SectorID1_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLASH_FEDACSDIS_SectorID1_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: BankID0_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS_BankID0_Inverse(val) BSP_FLD32(val,13, 15) +#define TMS570_FLASH_FEDACSDIS_BankID0_Inverse_GET(reg) BSP_FLD32GET(reg,13, 15) +#define TMS570_FLASH_FEDACSDIS_BankID0_Inverse_SET(reg,val) BSP_FLD32SET(reg, val,13, 15) + +/* field: SectorID0_inverse - The sector ID inverse bits are used with the sector ID bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS_SectorID0_inverse(val) BSP_FLD32(val,8, 11) +#define TMS570_FLASH_FEDACSDIS_SectorID0_inverse_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_FLASH_FEDACSDIS_SectorID0_inverse_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: BankID0 - The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS_BankID0(val) BSP_FLD32(val,5, 7) +#define TMS570_FLASH_FEDACSDIS_BankID0_GET(reg) BSP_FLD32GET(reg,5, 7) +#define TMS570_FLASH_FEDACSDIS_BankID0_SET(reg,val) BSP_FLD32SET(reg, val,5, 7) + +/* field: SectorID0 - The sector ID bits are used with the sector ID inverse bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS_SectorID0(val) BSP_FLD32(val,0, 3) +#define TMS570_FLASH_FEDACSDIS_SectorID0_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_FLASH_FEDACSDIS_SectorID0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_FLASH_FPRIMADDTAG------------------*/ +/* field: PRIM_ADD_TAG - Primary Address Tag Register */ +#define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG(val) BSP_FLD32(val,4, 31) +#define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG_GET(reg) BSP_FLD32GET(reg,4, 31) +#define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG_SET(reg,val) BSP_FLD32SET(reg, val,4, 31) + +/* field: 0 - Always 0000 */ +#define TMS570_FLASH_FPRIMADDTAG_0(val) BSP_FLD32(val,0, 3) +#define TMS570_FLASH_FPRIMADDTAG_0_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_FLASH_FPRIMADDTAG_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_FLASH_FDUPADDTAG------------------*/ +/* field: DUP_ADD_TAG - Primary Address Tag Register */ +#define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG(val) BSP_FLD32(val,4, 31) +#define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG_GET(reg) BSP_FLD32GET(reg,4, 31) +#define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG_SET(reg,val) BSP_FLD32SET(reg, val,4, 31) + + +/*--------------------TMS570_FLASH_FBPROT--------------------*/ +/* field: PROTL1DIS - PROTL1DIS: Level 1 Protection Disabled */ +#define TMS570_FLASH_FBPROT_PROTL1DIS BSP_BIT32(0) + + +/*---------------------TMS570_FLASH_FBSE---------------------*/ +/* field: BSE - Bank Sector Enable */ +#define TMS570_FLASH_FBSE_BSE(val) BSP_FLD32(val,0, 15) +#define TMS570_FLASH_FBSE_BSE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLASH_FBSE_BSE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_FLASH_FBBUSY--------------------*/ +/* field: BUSY - Bank Busy */ +#define TMS570_FLASH_FBBUSY_BUSY(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FBBUSY_BUSY_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FBBUSY_BUSY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_FLASH_FBAC---------------------*/ +/* field: OTPPROTDIS - OTP Sector Protection Disable. */ +#define TMS570_FLASH_FBAC_OTPPROTDIS(val) BSP_FLD32(val,16, 23) +#define TMS570_FLASH_FBAC_OTPPROTDIS_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_FLASH_FBAC_OTPPROTDIS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: 15_8 - BAGP 0-FFh Bank Active Grace Period. */ +#define TMS570_FLASH_FBAC_15_8(val) BSP_FLD32(val,8, 15) +#define TMS570_FLASH_FBAC_15_8_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_FLASH_FBAC_15_8_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: VREADST - VREAD Setup. */ +#define TMS570_FLASH_FBAC_VREADST(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FBAC_VREADST_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FBAC_VREADST_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_FLASH_FBFALLBACK------------------*/ +/* field: BANKPWR7 - Bank 7 Fallback Power Mode */ +#define TMS570_FLASH_FBFALLBACK_BANKPWR7(val) BSP_FLD32(val,14, 15) +#define TMS570_FLASH_FBFALLBACK_BANKPWR7_GET(reg) BSP_FLD32GET(reg,14, 15) +#define TMS570_FLASH_FBFALLBACK_BANKPWR7_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) + +/* field: BANKPWR1 - Bank 1 Fallback Power Mode */ +#define TMS570_FLASH_FBFALLBACK_BANKPWR1(val) BSP_FLD32(val,2, 3) +#define TMS570_FLASH_FBFALLBACK_BANKPWR1_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_FLASH_FBFALLBACK_BANKPWR1_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: BANKPWR0 - Bank 0 Fallback Power Mode */ +#define TMS570_FLASH_FBFALLBACK_BANKPWR0(val) BSP_FLD32(val,0, 1) +#define TMS570_FLASH_FBFALLBACK_BANKPWR0_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_FLASH_FBFALLBACK_BANKPWR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_FLASH_FBPRDY--------------------*/ +/* field: BANKBUSY - Bank busy bits (one bit for each bank) */ +#define TMS570_FLASH_FBPRDY_BANKBUSY(val) BSP_FLD32(val,16, 23) +#define TMS570_FLASH_FBPRDY_BANKBUSY_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_FLASH_FBPRDY_BANKBUSY_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: PUMPRDY - Flash pump ready flag */ +#define TMS570_FLASH_FBPRDY_PUMPRDY BSP_BIT32(15) + +/* field: BANKRDY - Bank ready bits (one bit for each bank) */ +#define TMS570_FLASH_FBPRDY_BANKRDY(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FBPRDY_BANKRDY_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FBPRDY_BANKRDY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_FLASH_FPAC1---------------------*/ +/* field: PSLEEP - Pump Sleep. */ +#define TMS570_FLASH_FPAC1_PSLEEP(val) BSP_FLD32(val,16, 26) +#define TMS570_FLASH_FPAC1_PSLEEP_GET(reg) BSP_FLD32GET(reg,16, 26) +#define TMS570_FLASH_FPAC1_PSLEEP_SET(reg,val) BSP_FLD32SET(reg, val,16, 26) + +/* field: PUMPPWR - Flash Charge Pump Fallback Power Mode */ +#define TMS570_FLASH_FPAC1_PUMPPWR BSP_BIT32(0) + + +/*---------------------TMS570_FLASH_FPAC2---------------------*/ +/* field: PAGP - Pump Active Grace Period */ +#define TMS570_FLASH_FPAC2_PAGP(val) BSP_FLD32(val,0, 15) +#define TMS570_FLASH_FPAC2_PAGP_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLASH_FPAC2_PAGP_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_FLASH_FMAC---------------------*/ +/* field: BANK - Bank Enable. */ +#define TMS570_FLASH_FMAC_BANK(val) BSP_FLD32(val,0, 2) +#define TMS570_FLASH_FMAC_BANK_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_FLASH_FMAC_BANK_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*--------------------TMS570_FLASH_FMSTAT--------------------*/ +/* field: ILA - Illegal Address */ +#define TMS570_FLASH_FMSTAT_ILA BSP_BIT32(14) + +/* field: PGV - Program Verify */ +#define TMS570_FLASH_FMSTAT_PGV BSP_BIT32(12) + +/* field: EV - Erase Verify */ +#define TMS570_FLASH_FMSTAT_EV BSP_BIT32(10) + +/* field: BUSY - Busy */ +#define TMS570_FLASH_FMSTAT_BUSY BSP_BIT32(8) + +/* field: ERS - Erase Active */ +#define TMS570_FLASH_FMSTAT_ERS BSP_BIT32(7) + +/* field: PGM - Program Active */ +#define TMS570_FLASH_FMSTAT_PGM BSP_BIT32(6) + +/* field: INVDAT - Invalid Data */ +#define TMS570_FLASH_FMSTAT_INVDAT BSP_BIT32(5) + +/* field: CSTAT - Command Status */ +#define TMS570_FLASH_FMSTAT_CSTAT BSP_BIT32(4) + +/* field: VOLTSTAT - Core Voltage Status */ +#define TMS570_FLASH_FMSTAT_VOLTSTAT BSP_BIT32(3) + +/* field: ESUSP - Erase Suspended */ +#define TMS570_FLASH_FMSTAT_ESUSP BSP_BIT32(2) + +/* field: PSUSP - Program Suspended */ +#define TMS570_FLASH_FMSTAT_PSUSP BSP_BIT32(1) + +/* field: SLOCK - Sector Lock Status */ +#define TMS570_FLASH_FMSTAT_SLOCK BSP_BIT32(0) + + +/*-------------------TMS570_FLASH_FEMUDMSW-------------------*/ +/* field: EMU_DMSW - EEPROM Emulation Most Significant Data Word */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLASH_FEMUDLSW-------------------*/ +/* field: EMU_DLSW - EEPROM Emulation Least Significant Data Word */ +/* Whole 32 bits */ + +/*--------------------TMS570_FLASH_FEMUECC--------------------*/ +/* field: EMU_ECC - This register can be written by the CPU in any mode. */ +#define TMS570_FLASH_FEMUECC_EMU_ECC(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FEMUECC_EMU_ECC_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FEMUECC_EMU_ECC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_FLASH_FEMUADDR-------------------*/ +/* field: EMU_ADDR - EEPROM Emulation Address */ +#define TMS570_FLASH_FEMUADDR_EMU_ADDR(val) BSP_FLD32(val,3, 21) +#define TMS570_FLASH_FEMUADDR_EMU_ADDR_GET(reg) BSP_FLD32GET(reg,3, 21) +#define TMS570_FLASH_FEMUADDR_EMU_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,3, 21) + + +/*-------------------TMS570_FLASH_FDIAGCTRL-------------------*/ +/* field: DIAG_TRIG - Diagnostic Trigger */ +#define TMS570_FLASH_FDIAGCTRL_DIAG_TRIG BSP_BIT32(24) + +/* field: DIAG_EN_KEY - Diagnostic Enable Key */ +#define TMS570_FLASH_FDIAGCTRL_DIAG_EN_KEY(val) BSP_FLD32(val,16, 19) +#define TMS570_FLASH_FDIAGCTRL_DIAG_EN_KEY_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLASH_FDIAGCTRL_DIAG_EN_KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: DIAG_ECC_SEL - Diagnostic SECDED Select */ +#define TMS570_FLASH_FDIAGCTRL_DIAG_ECC_SEL(val) BSP_FLD32(val,12, 14) +#define TMS570_FLASH_FDIAGCTRL_DIAG_ECC_SEL_GET(reg) BSP_FLD32GET(reg,12, 14) +#define TMS570_FLASH_FDIAGCTRL_DIAG_ECC_SEL_SET(reg,val) BSP_FLD32SET(reg, val,12, 14) + + +/*-------------------TMS570_FLASH_FRAWDATAH-------------------*/ +/* field: RAW_DATA_ - Uncorrected Raw Data */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLASH_FRAWDATAL-------------------*/ +/* field: RAW_DATA_ - Uncorrected Raw Data. Same as FRAW_DATAH but stores lower 32 bits. */ +/* Whole 32 bits */ + +/*--------------------TMS570_FLASH_FRAWECC--------------------*/ +/* field: PIPE_BUF - Error came from pipeline buffer hit */ +#define TMS570_FLASH_FRAWECC_PIPE_BUF BSP_BIT32(8) + +/* field: RAW_ECC - Uncorrected Raw ECC */ +#define TMS570_FLASH_FRAWECC_RAW_ECC(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FRAWECC_RAW_ECC_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FRAWECC_RAW_ECC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*--------------------TMS570_FLASH_FPAROVR--------------------*/ +/* field: BNK_INV_PAR - Buffer Invert Parity */ +#define TMS570_FLASH_FPAROVR_BNK_INV_PAR BSP_BIT32(16) + +/* field: BUS_PAR_DIS - Disable Bus Parity */ +#define TMS570_FLASH_FPAROVR_BUS_PAR_DIS(val) BSP_FLD32(val,12, 15) +#define TMS570_FLASH_FPAROVR_BUS_PAR_DIS_GET(reg) BSP_FLD32GET(reg,12, 15) +#define TMS570_FLASH_FPAROVR_BUS_PAR_DIS_SET(reg,val) BSP_FLD32SET(reg, val,12, 15) + +/* field: PAR_OVR_KEY - When this value is 101, the selected ADD_INV_PAR and DAT_INV_PAR fields will become active. */ +#define TMS570_FLASH_FPAROVR_PAR_OVR_KEY(val) BSP_FLD32(val,9, 11) +#define TMS570_FLASH_FPAROVR_PAR_OVR_KEY_GET(reg) BSP_FLD32GET(reg,9, 11) +#define TMS570_FLASH_FPAROVR_PAR_OVR_KEY_SET(reg,val) BSP_FLD32SET(reg, val,9, 11) + +/* field: ADD_INV_PAR - Address Odd Parity */ +#define TMS570_FLASH_FPAROVR_ADD_INV_PAR BSP_BIT32(8) + +/* field: DAT_INV_PAR - Data Odd Parity */ +#define TMS570_FLASH_FPAROVR_DAT_INV_PAR(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FPAROVR_DAT_INV_PAR_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FPAROVR_DAT_INV_PAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_FLASH_FEDACSDIS2------------------*/ +/* field: BankID3_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse(val) BSP_FLD32(val,29, 31) +#define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse_GET(reg) BSP_FLD32GET(reg,29, 31) +#define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse_SET(reg,val) BSP_FLD32SET(reg, val,29, 31) + +/* field: SectorID3_inverse - The sector ID inverse bits are used with the sector ID bits to determine which sector is disabled. */ +#define TMS570_FLASH_FEDACSDIS2_SectorID3_inverse(val) BSP_FLD32(val,24, 27) +#define TMS570_FLASH_FEDACSDIS2_SectorID3_inverse_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_FLASH_FEDACSDIS2_SectorID3_inverse_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: BankID3 - The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS2_BankID3(val) BSP_FLD32(val,21, 23) +#define TMS570_FLASH_FEDACSDIS2_BankID3_GET(reg) BSP_FLD32GET(reg,21, 23) +#define TMS570_FLASH_FEDACSDIS2_BankID3_SET(reg,val) BSP_FLD32SET(reg, val,21, 23) + +/* field: SectorID3 - The sector ID bits are used with the sector ID inverse bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS2_SectorID3(val) BSP_FLD32(val,16, 19) +#define TMS570_FLASH_FEDACSDIS2_SectorID3_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLASH_FEDACSDIS2_SectorID3_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: BankID2_Inverse - is disabled. The only bank that supports sector disable is bank 7. */ +#define TMS570_FLASH_FEDACSDIS2_BankID2_Inverse(val) BSP_FLD32(val,13, 15) +#define TMS570_FLASH_FEDACSDIS2_BankID2_Inverse_GET(reg) BSP_FLD32GET(reg,13, 15) +#define TMS570_FLASH_FEDACSDIS2_BankID2_Inverse_SET(reg,val) BSP_FLD32SET(reg, val,13, 15) + +/* field: SectorID2_inverse - The sector ID inverse bits are used with the sector ID bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS2_SectorID2_inverse(val) BSP_FLD32(val,8, 11) +#define TMS570_FLASH_FEDACSDIS2_SectorID2_inverse_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_FLASH_FEDACSDIS2_SectorID2_inverse_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: BankID2 - The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS2_BankID2(val) BSP_FLD32(val,5, 7) +#define TMS570_FLASH_FEDACSDIS2_BankID2_GET(reg) BSP_FLD32GET(reg,5, 7) +#define TMS570_FLASH_FEDACSDIS2_BankID2_SET(reg,val) BSP_FLD32SET(reg, val,5, 7) + +/* field: SectorID2 - The sector ID bits are used with the sector ID inverse bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS2_SectorID2(val) BSP_FLD32(val,0, 3) +#define TMS570_FLASH_FEDACSDIS2_SectorID2_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_FLASH_FEDACSDIS2_SectorID2_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_FLASH_FSMWRENA-------------------*/ +/* field: WR_ENA - Flash State Machine Write Enable */ +#define TMS570_FLASH_FSMWRENA_WR_ENA(val) BSP_FLD32(val,0, 2) +#define TMS570_FLASH_FSMWRENA_WR_ENA_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_FLASH_FSMWRENA_WR_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-------------------TMS570_FLASH_FSMSECTOR-------------------*/ +/* field: SECT_ERASED - Sectors Erased */ +#define TMS570_FLASH_FSMSECTOR_SECT_ERASED(val) BSP_FLD32(val,16, 31) +#define TMS570_FLASH_FSMSECTOR_SECT_ERASED_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_FLASH_FSMSECTOR_SECT_ERASED_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + + +/*-----------------TMS570_FLASH_EEPROMCONFIG-----------------*/ +/* field: EWAIT - EEPROM Wait state Counter */ +#define TMS570_FLASH_EEPROMCONFIG_EWAIT(val) BSP_FLD32(val,16, 19) +#define TMS570_FLASH_EEPROMCONFIG_EWAIT_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLASH_EEPROMCONFIG_EWAIT_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: AUTOSUSP_EN - Auto Suspend Enable */ +#define TMS570_FLASH_EEPROMCONFIG_AUTOSUSP_EN BSP_BIT32(8) + +/* field: AUTOSTART_GRACE - Auto-suspend Startup Grace Period */ +#define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*--------------------TMS570_FLASH_EECTRL1--------------------*/ +/* field: EDACMODE - Error Correction Mode. */ +#define TMS570_FLASH_EECTRL1_EDACMODE(val) BSP_FLD32(val,16, 19) +#define TMS570_FLASH_EECTRL1_EDACMODE_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLASH_EECTRL1_EDACMODE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: EE_EOFEN - EEPROM Emulation Event on a correctable One's Fail Enable bit */ +#define TMS570_FLASH_EECTRL1_EE_EOFEN BSP_BIT32(10) + +/* field: EE_EZFEN - EEPROM Emulation Event on a correctable Zero's Fail Enable bit */ +#define TMS570_FLASH_EECTRL1_EE_EZFEN BSP_BIT32(9) + +/* field: EE_EPEN - EEPROM Emulation Error Profiling Enable. */ +#define TMS570_FLASH_EECTRL1_EE_EPEN BSP_BIT32(8) + + +/*--------------------TMS570_FLASH_EECTRL2--------------------*/ +/* field: EE_SEC_THRESHOLD - EEPROM Emulation Single Error Correction Threshold */ +#define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD(val) BSP_FLD32(val,0, 15) +#define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_FLASH_EECORERRCNT------------------*/ +/* field: EE_ERRCNT - Single Error Correction Count */ +#define TMS570_FLASH_EECORERRCNT_EE_ERRCNT(val) BSP_FLD32(val,0, 15) +#define TMS570_FLASH_EECORERRCNT_EE_ERRCNT_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLASH_EECORERRCNT_EE_ERRCNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_FLASH_EECORERRADD------------------*/ +/* field: COR_ERR_ADD - Correctable Error Address */ +#define TMS570_FLASH_EECORERRADD_COR_ERR_ADD(val) BSP_FLD32(val,3, 31) +#define TMS570_FLASH_EECORERRADD_COR_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31) +#define TMS570_FLASH_EECORERRADD_COR_ERR_ADD_SET(reg,val) BSP_FLD32SET(reg, val,3, 31) + +/* field: B_OFF - Byte offset */ +#define TMS570_FLASH_EECORERRADD_B_OFF(val) BSP_FLD32(val,0, 2) +#define TMS570_FLASH_EECORERRADD_B_OFF_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_FLASH_EECORERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*------------------TMS570_FLASH_EECORERRPOS------------------*/ +/* field: TYPE - ErrorType */ +#define TMS570_FLASH_EECORERRPOS_TYPE BSP_BIT32(8) + +/* field: EE_ERR_POS - The bit address of the single bit error */ +#define TMS570_FLASH_EECORERRPOS_EE_ERR_POS(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_EECORERRPOS_EE_ERR_POS_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_EECORERRPOS_EE_ERR_POS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_FLASH_EESTATUS-------------------*/ +/* field: EE_D_UNC_ERR - Diagnostic Mode Uncorrectable Error Status Flag */ +#define TMS570_FLASH_EESTATUS_EE_D_UNC_ERR BSP_BIT32(12) + +/* field: EE_UNC_ERR - EEPROM Emulation Uncorrectable Error Flag */ +#define TMS570_FLASH_EESTATUS_EE_UNC_ERR BSP_BIT32(8) + +/* field: EE_CMG - EEPROM Emulation Compare Malfunction Good */ +#define TMS570_FLASH_EESTATUS_EE_CMG BSP_BIT32(6) + +/* field: EE_CME - . */ +#define TMS570_FLASH_EESTATUS_EE_CME BSP_BIT32(4) + +/* field: EE_D_COR_ERR - Diagnostic Correctable Error Flag */ +#define TMS570_FLASH_EESTATUS_EE_D_COR_ERR BSP_BIT32(3) + +/* field: EE_ERR_ONE_FLG - Error on One Fail Error Flag */ +#define TMS570_FLASH_EESTATUS_EE_ERR_ONE_FLG BSP_BIT32(2) + +/* field: EE_ERR_ZERO_FLG - Error on Zero Fail Error Flag */ +#define TMS570_FLASH_EESTATUS_EE_ERR_ZERO_FLG BSP_BIT32(1) + +/* field: EE_ERR_PRF_FLG - Error Profiling Error Flag */ +#define TMS570_FLASH_EESTATUS_EE_ERR_PRF_FLG BSP_BIT32(0) + + +/*------------------TMS570_FLASH_EEUNCERRADD------------------*/ +/* field: UNC_ERR_ADD - Un-correctable Error Address */ +#define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD(val) BSP_FLD32(val,3, 31) +#define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31) +#define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD_SET(reg,val) BSP_FLD32SET(reg, val,3, 31) + +/* field: B_OFF - Byte offset */ +#define TMS570_FLASH_EEUNCERRADD_B_OFF(val) BSP_FLD32(val,0, 2) +#define TMS570_FLASH_EEUNCERRADD_B_OFF_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_FLASH_EEUNCERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-------------------TMS570_FLASH_FCFGBANK-------------------*/ +/* field: EE_BANK_WIDTH - Bank 7 width (144 bits wide) */ +#define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH(val) BSP_FLD32(val,20, 31) +#define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH_GET(reg) BSP_FLD32GET(reg,20, 31) +#define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,20, 31) + +/* field: MAIN_BANK_WIDTH - Width of main flash banks (144 bits wide) */ +#define TMS570_FLASH_FCFGBANK_MAIN_BANK_WIDTH(val) BSP_FLD32(val,4, 15) +#define TMS570_FLASH_FCFGBANK_MAIN_BANK_WIDTH_GET(reg) BSP_FLD32GET(reg,4, 15) +#define TMS570_FLASH_FCFGBANK_MAIN_BANK_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,4, 15) + + + +#endif /* LIBBSP_ARM_TMS570_FLASH */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h new file mode 100644 index 0000000000..e077ab65fd --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h @@ -0,0 +1,618 @@ +/* The header file is generated by make_header.py from FLEX_RAY.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_FLEX_RAY +#define LIBBSP_ARM_TMS570_FLEX_RAY + +#include + +typedef struct{ + uint32_t GSN0; /*Global Static Number 0*/ + uint32_t GSN1; /*Global Static Number 1*/ + uint8_t reserved1 [8]; + uint32_t GCS; /*Global Control Set*/ + uint32_t GCR; /*Global Control Reset*/ + uint32_t TSCB; /*Transfer Status Current Buffer*/ + uint32_t LTBCC; /*Last Transferred Buffer to Communication Controller*/ + uint32_t LTBSM; /*Last Transferred Buffer to System Memory*/ + uint32_t TBA; /*Transfer Base Address*/ + uint32_t NTBA; /*Next Transfer Base Address*/ + uint32_t BAMS; /*Base Address of Mirrored Status*/ + uint32_t SAMP; /*Start Address of Memory Protection*/ + uint32_t EAMP; /*End Address of Memory Protection*/ + uint8_t reserved2 [8]; + uint32_t TSMO1; /*Transfer to System Memory Occurred 1*/ + uint32_t TSMO2; /*Transfer to System Memory Occurred 2*/ + uint32_t TSMO3; /*Transfer to System Memory Occurred 3*/ + uint32_t TSMO4; /*Transfer to System Memory Occurred 4*/ + uint32_t TCCO1; /*Transfer to Communication Controller Occurred 1*/ + uint32_t TCCO2; /*Transfer to Communication Controller Occurred 2*/ + uint32_t TCCO3; /*Transfer to Communication Controller Occurred 3*/ + uint32_t TCCO4; /*Transfer to Communication Controller Occurred 4*/ + uint32_t TOOFF; /*Transfer Occurred Offset*/ + uint8_t reserved3 [12]; + uint32_t PEADR; /*Parity Error Address*/ + uint32_t TEIF; /*Transfer Error Interrupt*/ + uint32_t TEIRES; /*Transfer Error Interrupt Enable Set*/ + uint32_t TEIRER; /*Transfer Error Interrupt Enable Reset*/ + uint32_t TTSMS1; /*Trigger Transfer to System Memory Set 1*/ + uint32_t TTSMR1; /*Trigger Transfer to System Memory Reset 1*/ + uint32_t TTSMS2; /*Trigger Transfer to System Memory Set 2*/ + uint32_t TTSMR2; /*Trigger Transfer to System Memory Reset 2*/ + uint32_t TTSMS3; /*Trigger Transfer to System Memory Set 3*/ + uint32_t TTSMR3; /*Trigger Transfer to System Memory Reset 3*/ + uint32_t TTSMS4; /*Trigger Transfer to System Memory Set 4*/ + uint32_t TTSMR4; /*Trigger Transfer to System Memory Reset 4*/ + uint32_t TTCCS1; /*Trigger Transfer to Communication Controller Set 1*/ + uint32_t TTCCR1; /*Trigger Transfer to Communication Controller Reset 1*/ + uint32_t TTCCS2; /*Trigger Transfer to Communication Controller Set 2*/ + uint32_t TTCCR2; /*Trigger Transfer to Communication Controller Reset 2*/ + uint32_t TTCCS3; /*Trigger Transfer to Communication Controller Set 3*/ + uint32_t TTCCR3; /*Trigger Transfer to Communication Controller Reset 3*/ + uint32_t TTCCS4; /*Trigger Transfer to Communication Controller Set 4*/ + uint32_t TTCCR4; /*Trigger Transfer to Communication Controller Reset 4*/ + uint32_t ETESMS1; /*Enable Transfer on Event to System Memory Set 1*/ + uint32_t ETESMR1; /*Enable Transfer on Event to System Memory Reset 1*/ + uint32_t ETESMS2; /*Enable Transfer on Event to System Memory Set 2*/ + uint32_t ETESMR2; /*Enable Transfer on Event to System Memory Reset 2*/ + uint32_t ETESMS3; /*Enable Transfer on Event to System Memory Set 3*/ + uint32_t ETESMR3; /*Enable Transfer on Event to System Memory Reset 3*/ + uint32_t ETESMS4; /*Enable Transfer on Event to System Memory Set 4*/ + uint32_t ETESMR4; /*Enable Transfer on Event to System Memory Reset 4*/ + uint32_t CESMS1; /*Clear on Event to System Memory Set 1*/ + uint32_t CESMR1; /*Clear on Event to System Memory Reset 1*/ + uint32_t CESMS2; /*Clear on Event to System Memory Set 2*/ + uint32_t CESMR2; /*Clear on Event to System Memory Reset 2*/ + uint32_t CESMS3; /*Clear on Event to System Memory Set 3*/ + uint32_t CESMR3; /*Clear on Event to System Memory Reset 3*/ + uint32_t CESMS4; /*Clear on Event to System Memory Set 4*/ + uint32_t CESMR4; /*Clear on Event to System Memory Reset 4*/ + uint32_t TSMIES1; /*Transfer to System Memory Interrupt Enable Set 1*/ + uint32_t TSMIER1; /*Transfer to System Memory Interrupt Enable Reset 1*/ + uint32_t TSMIES2; /*Transfer to System Memory Interrupt Enable Set 2*/ + uint32_t TSMIER2; /*Transfer to System Memory Interrupt Enable Reset 2*/ + uint32_t TSMIES3; /*Transfer to System Memory Interrupt Enable Set 3*/ + uint32_t TSMIER3; /*Transfer to System Memory Interrupt Enable Reset 3*/ + uint32_t TSMIES4; /*Transfer to System Memory Interrupt Enable Set 4*/ + uint32_t TSMIER4; /*Transfer to System Memory Interrupt Enable Reset 4*/ + uint32_t TCCIES1; /*Transfer to Communication Controller Interrupt Enable Set 1*/ + uint32_t TCCIER1; /*Transfer to Communication Controller Interrupt Enable Reset 1*/ + uint32_t TCCIES2; /*Transfer to Communication Controller Interrupt Enable Set 2*/ + uint32_t TCCIER2; /*Transfer to Communication Controller Interrupt Enable Reset 2*/ + uint32_t TCCIES3; /*Transfer to Communication Controller Interrupt Enable Set 3*/ + uint32_t TCCIER3; /*Transfer to Communication Controller Interrupt Enable Reset 3*/ + uint32_t TCCIES4; /*Transfer to Communication Controller Interrupt Enable Set 4*/ + uint32_t TCCIER4; /*Transfer to Communication Controller Interrupt Enable Reset 4*/ +} tms570_flex_ray_t; + + +/*--------------------TMS570_FLEX_RAY_GSN0--------------------*/ +/* field: Data_A - Data_A(15-0) */ +#define TMS570_FLEX_RAY_GSN0_Data_A(val) BSP_FLD32(val,16, 31) +#define TMS570_FLEX_RAY_GSN0_Data_A_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_FLEX_RAY_GSN0_Data_A_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: Data_B - (complement of Data_A(15-0)) */ +#define TMS570_FLEX_RAY_GSN0_Data_B(val) BSP_FLD32(val,0, 15) +#define TMS570_FLEX_RAY_GSN0_Data_B_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLEX_RAY_GSN0_Data_B_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_FLEX_RAY_GSN1--------------------*/ +/* field: Data_C - Data_C(15-0) */ +#define TMS570_FLEX_RAY_GSN1_Data_C(val) BSP_FLD32(val,16, 31) +#define TMS570_FLEX_RAY_GSN1_Data_C_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_FLEX_RAY_GSN1_Data_C_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: Data_D - (complement of Data_C(15-0)) */ +#define TMS570_FLEX_RAY_GSN1_Data_D(val) BSP_FLD32(val,0, 15) +#define TMS570_FLEX_RAY_GSN1_Data_D_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLEX_RAY_GSN1_Data_D_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_FLEX_RAY_GCS--------------------*/ +/* field: ENDVBM - Endianness Correction on VBusp Master */ +#define TMS570_FLEX_RAY_GCS_ENDVBM BSP_BIT32(31) + +/* field: ENDVBS - Endianness correction on VBusp Slave */ +#define TMS570_FLEX_RAY_GCS_ENDVBS BSP_BIT32(30) + +/* field: ENDRx - Endianness Correction for No (header or payload) Data Sink Access */ +#define TMS570_FLEX_RAY_GCS_ENDRx(val) BSP_FLD32(val,28, 29) +#define TMS570_FLEX_RAY_GCS_ENDRx_GET(reg) BSP_FLD32GET(reg,28, 29) +#define TMS570_FLEX_RAY_GCS_ENDRx_SET(reg,val) BSP_FLD32SET(reg, val,28, 29) + +/* field: ENDHx - Endianness Correction for Header */ +#define TMS570_FLEX_RAY_GCS_ENDHx(val) BSP_FLD32(val,26, 27) +#define TMS570_FLEX_RAY_GCS_ENDHx_GET(reg) BSP_FLD32GET(reg,26, 27) +#define TMS570_FLEX_RAY_GCS_ENDHx_SET(reg,val) BSP_FLD32SET(reg, val,26, 27) + +/* field: ENDPx - Endianness Correction for Payload */ +#define TMS570_FLEX_RAY_GCS_ENDPx(val) BSP_FLD32(val,24, 25) +#define TMS570_FLEX_RAY_GCS_ENDPx_GET(reg) BSP_FLD32GET(reg,24, 25) +#define TMS570_FLEX_RAY_GCS_ENDPx_SET(reg,val) BSP_FLD32SET(reg, val,24, 25) + +/* field: PRIO - Transfer Priority */ +#define TMS570_FLEX_RAY_GCS_PRIO BSP_BIT32(21) + +/* field: PEFT - Parity for Test */ +#define TMS570_FLEX_RAY_GCS_PEFT BSP_BIT32(20) + +/* field: PELx - Parity Lock */ +#define TMS570_FLEX_RAY_GCS_PELx(val) BSP_FLD32(val,16, 19) +#define TMS570_FLEX_RAY_GCS_PELx_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLEX_RAY_GCS_PELx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: CETESM - Clear ETESM Register */ +#define TMS570_FLEX_RAY_GCS_CETESM BSP_BIT32(14) + +/* field: CTTCC - Clear TTCC Register */ +#define TMS570_FLEX_RAY_GCS_CTTCC BSP_BIT32(13) + +/* field: CTTSM - Clear TTSM Register */ +#define TMS570_FLEX_RAY_GCS_CTTSM BSP_BIT32(12) + +/* field: ETSM - Enable Transfer Status Mirrored */ +#define TMS570_FLEX_RAY_GCS_ETSM BSP_BIT32(8) + +/* field: SILE - Status Interrupt Line Enable */ +#define TMS570_FLEX_RAY_GCS_SILE BSP_BIT32(5) + +/* field: EILE - Error Interrupt Line Enable */ +#define TMS570_FLEX_RAY_GCS_EILE BSP_BIT32(4) + +/* field: TUH - Transfer Unit Halted */ +#define TMS570_FLEX_RAY_GCS_TUH BSP_BIT32(1) + +/* field: TUE - Transfer Unit Enabled */ +#define TMS570_FLEX_RAY_GCS_TUE BSP_BIT32(0) + + +/*--------------------TMS570_FLEX_RAY_GCR--------------------*/ +/* field: ENDVBM - Endianness Correction on VBusp Master */ +#define TMS570_FLEX_RAY_GCR_ENDVBM BSP_BIT32(31) + +/* field: ENDVBS - Endianness correction on VBusp Slave */ +#define TMS570_FLEX_RAY_GCR_ENDVBS BSP_BIT32(30) + +/* field: ENDRx - Endianness Correction for No (header or payload) Data Sink Access */ +#define TMS570_FLEX_RAY_GCR_ENDRx(val) BSP_FLD32(val,28, 29) +#define TMS570_FLEX_RAY_GCR_ENDRx_GET(reg) BSP_FLD32GET(reg,28, 29) +#define TMS570_FLEX_RAY_GCR_ENDRx_SET(reg,val) BSP_FLD32SET(reg, val,28, 29) + +/* field: ENDHx - Endianness Correction for Header */ +#define TMS570_FLEX_RAY_GCR_ENDHx(val) BSP_FLD32(val,26, 27) +#define TMS570_FLEX_RAY_GCR_ENDHx_GET(reg) BSP_FLD32GET(reg,26, 27) +#define TMS570_FLEX_RAY_GCR_ENDHx_SET(reg,val) BSP_FLD32SET(reg, val,26, 27) + +/* field: ENDPx - Endianness Correction for Payload */ +#define TMS570_FLEX_RAY_GCR_ENDPx(val) BSP_FLD32(val,24, 25) +#define TMS570_FLEX_RAY_GCR_ENDPx_GET(reg) BSP_FLD32GET(reg,24, 25) +#define TMS570_FLEX_RAY_GCR_ENDPx_SET(reg,val) BSP_FLD32SET(reg, val,24, 25) + +/* field: PRIO - Transfer Priority */ +#define TMS570_FLEX_RAY_GCR_PRIO BSP_BIT32(21) + +/* field: PEFT - Parity for Test */ +#define TMS570_FLEX_RAY_GCR_PEFT BSP_BIT32(20) + +/* field: PELx - Parity Lock */ +#define TMS570_FLEX_RAY_GCR_PELx(val) BSP_FLD32(val,16, 19) +#define TMS570_FLEX_RAY_GCR_PELx_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLEX_RAY_GCR_PELx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: CETESM - Clear ETESM Register */ +#define TMS570_FLEX_RAY_GCR_CETESM BSP_BIT32(14) + +/* field: CTTCC - Clear TTCC Register */ +#define TMS570_FLEX_RAY_GCR_CTTCC BSP_BIT32(13) + +/* field: CTTSM - Clear TTSM Register */ +#define TMS570_FLEX_RAY_GCR_CTTSM BSP_BIT32(12) + +/* field: ETSM - Enable Transfer Status Mirrored */ +#define TMS570_FLEX_RAY_GCR_ETSM BSP_BIT32(8) + +/* field: SILE - Status Interrupt Line Enable */ +#define TMS570_FLEX_RAY_GCR_SILE BSP_BIT32(5) + +/* field: EILE - Error Interrupt Line Enable */ +#define TMS570_FLEX_RAY_GCR_EILE BSP_BIT32(4) + +/* field: TUH - Transfer Unit Halted */ +#define TMS570_FLEX_RAY_GCR_TUH BSP_BIT32(1) + +/* field: TUE - Transfer Unit Enabled */ +#define TMS570_FLEX_RAY_GCR_TUE BSP_BIT32(0) + + +/*--------------------TMS570_FLEX_RAY_TSCB--------------------*/ +/* field: TSMS - Transfer State Machine Status */ +#define TMS570_FLEX_RAY_TSCB_TSMS(val) BSP_FLD32(val,16, 20) +#define TMS570_FLEX_RAY_TSCB_TSMS_GET(reg) BSP_FLD32GET(reg,16, 20) +#define TMS570_FLEX_RAY_TSCB_TSMS_SET(reg,val) BSP_FLD32SET(reg, val,16, 20) + +/* field: STUH - Status of Transfer Unit State Machine for Halt Detection */ +#define TMS570_FLEX_RAY_TSCB_STUH BSP_BIT32(12) + +/* field: IDLE - Detects Transfer State Machine State IDLE */ +#define TMS570_FLEX_RAY_TSCB_IDLE BSP_BIT32(8) + +/* field: BN - Buffer Number */ +#define TMS570_FLEX_RAY_TSCB_BN(val) BSP_FLD32(val,0, 6) +#define TMS570_FLEX_RAY_TSCB_BN_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_FLEX_RAY_TSCB_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + +/*-------------------TMS570_FLEX_RAY_LTBCC-------------------*/ +/* field: BN - Buffer number. */ +#define TMS570_FLEX_RAY_LTBCC_BN(val) BSP_FLD32(val,0, 6) +#define TMS570_FLEX_RAY_LTBCC_BN_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_FLEX_RAY_LTBCC_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + +/*-------------------TMS570_FLEX_RAY_LTBSM-------------------*/ +/* field: BN - Buffer number. */ +#define TMS570_FLEX_RAY_LTBSM_BN(val) BSP_FLD32(val,0, 6) +#define TMS570_FLEX_RAY_LTBSM_BN_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_FLEX_RAY_LTBSM_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + +/*--------------------TMS570_FLEX_RAY_TBA--------------------*/ +/* field: TBA - Transfer Base Address. */ +/* Whole 32 bits */ + +/*--------------------TMS570_FLEX_RAY_NTBA--------------------*/ +/* field: nTBA - nTBA(31-0) */ +/* Whole 32 bits */ + +/*--------------------TMS570_FLEX_RAY_BAMS--------------------*/ +/* field: BAMS - Base Address of Mirrored Status32-bit base pointer, 2 LSB are not significant (32-bit */ +/* Whole 32 bits */ + +/*--------------------TMS570_FLEX_RAY_SAMP--------------------*/ +/* field: SAMP - Start Address Memory Protection. */ +/* Whole 32 bits */ + +/*--------------------TMS570_FLEX_RAY_EAMP--------------------*/ +/* field: EAMP - End Address Memory Protection. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TSMO1-------------------*/ +/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TSMO2-------------------*/ +/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TSMO3-------------------*/ +/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TSMO4-------------------*/ +/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TCCO1-------------------*/ +/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TCCO2-------------------*/ +/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TCCO3-------------------*/ +/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TCCO4-------------------*/ +/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TOOFF-------------------*/ +/* field: TDIR - Transfer Direction. */ +#define TMS570_FLEX_RAY_TOOFF_TDIR BSP_BIT32(8) + +/* field: OFF - Offset Vector */ +#define TMS570_FLEX_RAY_TOOFF_OFF(val) BSP_FLD32(val,0, 7) +#define TMS570_FLEX_RAY_TOOFF_OFF_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLEX_RAY_TOOFF_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_FLEX_RAY_PEADR-------------------*/ +/* field: ADR - Address of failing TCR location. */ +#define TMS570_FLEX_RAY_PEADR_ADR(val) BSP_FLD32(val,0, 8) +#define TMS570_FLEX_RAY_PEADR_ADR_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_FLEX_RAY_PEADR_ADR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*--------------------TMS570_FLEX_RAY_TEIF--------------------*/ +/* field: MPV - Memory Protection Violation. */ +#define TMS570_FLEX_RAY_TEIF_MPV BSP_BIT32(17) + +/* field: PE - Parity Error. The flag signals a parity error to the host. */ +#define TMS570_FLEX_RAY_TEIF_PE BSP_BIT32(16) + +/* field: RSTAT - Status of VBUS on read transfers. */ +#define TMS570_FLEX_RAY_TEIF_RSTAT(val) BSP_FLD32(val,8, 10) +#define TMS570_FLEX_RAY_TEIF_RSTAT_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_FLEX_RAY_TEIF_RSTAT_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: WSTAT - Status of VBUS on write transfers. */ +#define TMS570_FLEX_RAY_TEIF_WSTAT(val) BSP_FLD32(val,4, 6) +#define TMS570_FLEX_RAY_TEIF_WSTAT_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_FLEX_RAY_TEIF_WSTAT_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TNR - Transfer Not Ready. */ +#define TMS570_FLEX_RAY_TEIF_TNR BSP_BIT32(1) + +/* field: FAC - Forbidden Access. */ +#define TMS570_FLEX_RAY_TEIF_FAC BSP_BIT32(0) + + +/*-------------------TMS570_FLEX_RAY_TEIRES-------------------*/ +/* field: RSTATE - Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors). */ +#define TMS570_FLEX_RAY_TEIRES_RSTATE(val) BSP_FLD32(val,8, 10) +#define TMS570_FLEX_RAY_TEIRES_RSTATE_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_FLEX_RAY_TEIRES_RSTATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: WSTATE - Write Error Interrupt Generation (interrupt generation on VBUS write transfer errors). */ +#define TMS570_FLEX_RAY_TEIRES_WSTATE(val) BSP_FLD32(val,4, 6) +#define TMS570_FLEX_RAY_TEIRES_WSTATE_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_FLEX_RAY_TEIRES_WSTATE_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TNRE - Transfer Not Ready Enable. */ +#define TMS570_FLEX_RAY_TEIRES_TNRE BSP_BIT32(1) + +/* field: FACE - Forbidden Access Enable. */ +#define TMS570_FLEX_RAY_TEIRES_FACE BSP_BIT32(0) + + +/*-------------------TMS570_FLEX_RAY_TEIRER-------------------*/ +/* field: RSTATE - Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors). */ +#define TMS570_FLEX_RAY_TEIRER_RSTATE(val) BSP_FLD32(val,8, 10) +#define TMS570_FLEX_RAY_TEIRER_RSTATE_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_FLEX_RAY_TEIRER_RSTATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: WSTATE - Write Error Interrupt Generation (interrupt generation on VBUS write transfer errors). */ +#define TMS570_FLEX_RAY_TEIRER_WSTATE(val) BSP_FLD32(val,4, 6) +#define TMS570_FLEX_RAY_TEIRER_WSTATE_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_FLEX_RAY_TEIRER_WSTATE_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TNRE - Transfer Not Ready Enable. */ +#define TMS570_FLEX_RAY_TEIRER_TNRE BSP_BIT32(1) + +/* field: FACE - Forbidden Access Enable. */ +#define TMS570_FLEX_RAY_TEIRER_FACE BSP_BIT32(0) + + +/*-------------------TMS570_FLEX_RAY_TTSMS1-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMR1-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMS2-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMR2-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMS3-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMR3-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMS4-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMR4-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCS1-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCR1-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCS2-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCR2-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCS3-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCR3-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCS4-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCR4-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMS1------------------*/ +/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMR1------------------*/ +/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMS2------------------*/ +/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMR2------------------*/ +/* field: ETESMS1 - message buffers 0 to 31. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMS3------------------*/ +/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMR3------------------*/ +/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMS4------------------*/ +/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMR4------------------*/ +/* field: ETESMS1 - message buffers 0 to 31. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMS1-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMR1-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMS2-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMR2-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMS3-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMR3-------------------*/ +/* field: CESMS1 - CESMS1(31-0) */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMS4-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMR4-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIES1------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIER1------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIES2------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIER2------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIES3------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIER3------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIES4------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIER4------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIES1------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIER1------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIES2------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIER2------------------*/ +/* field: TCCIES1 - to message buffers 0 to 31. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIES3------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIER3------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIES4------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIER4------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_FLEX_RAY */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h new file mode 100644 index 0000000000..3cb7851754 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h @@ -0,0 +1,324 @@ +/* The header file is generated by make_header.py from GIO.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_GIO +#define LIBBSP_ARM_TMS570_GIO + +#include + +typedef struct{ + uint32_t DIR; /*GIO Data Direction Register*/ + uint32_t DIN; /*GIO Data Input Register*/ + uint32_t DOUT; /*GIO Data Output Register*/ + uint32_t DSET; /*GIO Data Set Register*/ + uint32_t DCLR; /*GIO Data Clear Register*/ + uint32_t PDR; /*GIO Open Drain Register*/ + uint32_t PULDIS; /*GIO Pull Disable Register*/ + uint32_t PSL; /*GIO Pull Select Register*/ +} tms570_gio_port_t; + +typedef struct{ + uint32_t GCR0; /*GIO Global Control Register*/ + uint8_t reserved1 [4]; + uint32_t INTDET; /*GIO Interrupt Detect Register*/ + uint32_t POL; /*GIO Interrupt Polarity Register*/ + uint32_t ENASET; /*GIO Interrupt Enable Set Register*/ + uint32_t ENACLR; /*GIO Interrupt Enable Clear Register*/ + uint32_t LVLSET; /*GIO Interrupt Priority Set Register*/ + uint32_t LVLCLR; /*GIO Interrupt Priority Clear Register*/ + uint32_t FLG; /*GIO Interrupt Flag Register*/ + uint32_t OFF1; /*GIO Offset 1 Register*/ + uint32_t OFF2; /*GIO Offset 2 Register*/ + uint32_t EMU1; /*GIO Emulation 1 Register*/ + uint32_t EMU2; /*GIO Emulation 2 Register*/ + tms570_gio_port_t ports[8]; /*GIO ports*/ +} tms570_gio_t; + + +/*-----------------------TMS570_GIO_DIR-----------------------*/ +/* field: GIODIR - GIO data direction, pins [7:0] */ +#define TMS570_GIO_DIR_GIODIR(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_DIR_GIODIR_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_DIR_GIODIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_GIO_DIN-----------------------*/ +/* field: GIODIN - GIO data input, pins [7:0] */ +#define TMS570_GIO_DIN_GIODIN(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_DIN_GIODIN_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_DIN_GIODIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_GIO_DOUT----------------------*/ +/* field: GIODOUT - IO data output, pins[7:0]. */ +#define TMS570_GIO_DOUT_GIODOUT(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_DOUT_GIODOUT_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_DOUT_GIODOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_GIO_DSET----------------------*/ +/* field: GIODSET - GIO data set, pins[7:0]. This bit drives the output of GIO pin high. */ +#define TMS570_GIO_DSET_GIODSET(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_DSET_GIODSET_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_DSET_GIODSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_GIO_DCLR----------------------*/ +/* field: GIODCLR - GIO data clear, pins[7:0]. This bit drives the output of GIO pin low. */ +#define TMS570_GIO_DCLR_GIODCLR(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_DCLR_GIODCLR_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_DCLR_GIODCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_GIO_PDR-----------------------*/ +/* field: 7_0 - GIOPDRH GIO open drain, pins[7:0] */ +#define TMS570_GIO_PDR_7_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_PDR_7_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_PDR_7_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_GIO_PULDIS---------------------*/ +/* field: GIOPULDIS - GIO pull disable, pins[7:0]. */ +#define TMS570_GIO_PULDIS_GIOPULDIS(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_PULDIS_GIOPULDIS_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_PULDIS_GIOPULDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_GIO_PSL-----------------------*/ +/* field: GIOPSL - GIO pull select, pins[7:0] */ +#define TMS570_GIO_PSL_GIOPSL(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_PSL_GIOPSL_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_PSL_GIOPSL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_GIO_GCR0----------------------*/ +/* field: RESET - GIO reset. */ +#define TMS570_GIO_GCR0_RESET BSP_BIT32(0) + + +/*---------------------TMS570_GIO_INTDET---------------------*/ +/* field: GIOINTDET_3 - Interrupt detection select for pins GIOD[7:0] */ +#define TMS570_GIO_INTDET_GIOINTDET_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_INTDET_GIOINTDET_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_INTDET_GIOINTDET_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOINTDET_2 - Interrupt detection select for pins GIOC[7:0] */ +#define TMS570_GIO_INTDET_GIOINTDET_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_INTDET_GIOINTDET_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_INTDET_GIOINTDET_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOINTDET_1 - Interrupt detection select for pins GIOB[7:0] */ +#define TMS570_GIO_INTDET_GIOINTDET_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_INTDET_GIOINTDET_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_INTDET_GIOINTDET_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOINTDET_0 - Interrupt detection select for pins GIOA[7:0] */ +#define TMS570_GIO_INTDET_GIOINTDET_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_INTDET_GIOINTDET_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_INTDET_GIOINTDET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_GIO_POL-----------------------*/ +/* field: GIOPOL_3 - Interrupt polarity select for pins GIOD[7:0] */ +#define TMS570_GIO_POL_GIOPOL_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_POL_GIOPOL_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_POL_GIOPOL_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOPOL_2 - Interrupt polarity select for pins GIOC[7:0] */ +#define TMS570_GIO_POL_GIOPOL_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_POL_GIOPOL_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_POL_GIOPOL_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOPOL_1 - Interrupt polarity select for pins GIOB[7:0] */ +#define TMS570_GIO_POL_GIOPOL_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_POL_GIOPOL_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_POL_GIOPOL_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOPOL_0 - Interrupt polarity select for pins GIOA[7:0] */ +#define TMS570_GIO_POL_GIOPOL_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_POL_GIOPOL_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_POL_GIOPOL_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_GIO_ENASET---------------------*/ +/* field: GIOENASET_3 - nterrupt enable for pins GIOD[7:0] */ +#define TMS570_GIO_ENASET_GIOENASET_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_ENASET_GIOENASET_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_ENASET_GIOENASET_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOENASET_2 - Interrupt enable for pins GIOC[7:0] */ +#define TMS570_GIO_ENASET_GIOENASET_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_ENASET_GIOENASET_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_ENASET_GIOENASET_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOENASET_1 - Interrupt enable for pins GIOB[7:0] */ +#define TMS570_GIO_ENASET_GIOENASET_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_ENASET_GIOENASET_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_ENASET_GIOENASET_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOENASET_0 - Interrupt enable for pins GIOA[7:0] */ +#define TMS570_GIO_ENASET_GIOENASET_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_ENASET_GIOENASET_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_ENASET_GIOENASET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_GIO_ENACLR---------------------*/ +/* field: GIOENACLR_3 - Interrupt enable for pins GIOD[7:0] */ +#define TMS570_GIO_ENACLR_GIOENACLR_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_ENACLR_GIOENACLR_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_ENACLR_GIOENACLR_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOENACLR_2 - Interrupt enable for pins GIOC[7:0] */ +#define TMS570_GIO_ENACLR_GIOENACLR_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_ENACLR_GIOENACLR_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_ENACLR_GIOENACLR_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOENACLR_1 - Interrupt enable for pins GIOB[7:0] */ +#define TMS570_GIO_ENACLR_GIOENACLR_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_ENACLR_GIOENACLR_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_ENACLR_GIOENACLR_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOENACLR_0 - Interrupt enable for pins GIOA[7:0] */ +#define TMS570_GIO_ENACLR_GIOENACLR_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_ENACLR_GIOENACLR_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_ENACLR_GIOENACLR_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_GIO_LVLSET---------------------*/ +/* field: GIOLVLSET_3 - GIO high priority interrupt for pins GIOD[7:0]. */ +#define TMS570_GIO_LVLSET_GIOLVLSET_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_LVLSET_GIOLVLSET_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_LVLSET_GIOLVLSET_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOLVLSET_2 - GIO high priority interrupt for pins GIOC[7:0]. */ +#define TMS570_GIO_LVLSET_GIOLVLSET_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_LVLSET_GIOLVLSET_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_LVLSET_GIOLVLSET_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOLVLSET_1 - GIO high priority interrupt for pins GIOB[7:0]. */ +#define TMS570_GIO_LVLSET_GIOLVLSET_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_LVLSET_GIOLVLSET_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_LVLSET_GIOLVLSET_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOLVLSET_0 - GIO high priority interrupt for pins GIOA[7:0]. */ +#define TMS570_GIO_LVLSET_GIOLVLSET_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_LVLSET_GIOLVLSET_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_LVLSET_GIOLVLSET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_GIO_LVLCLR---------------------*/ +/* field: GIOLVLCLR_3 - GIO low priority interrupt for pins GIOD[7:0] */ +#define TMS570_GIO_LVLCLR_GIOLVLCLR_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOLVLCLR_2 - GIO low priority interrupt for pins GIOC[7:0] */ +#define TMS570_GIO_LVLCLR_GIOLVLCLR_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOLVLCLR_1 - GIO low priority interrupt for pins GIOB[7:0] */ +#define TMS570_GIO_LVLCLR_GIOLVLCLR_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOLVLCLR_0 - GIO low priority interrupt for pins GIOA[7:0] */ +#define TMS570_GIO_LVLCLR_GIOLVLCLR_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_GIO_FLG-----------------------*/ +/* field: GIOFLG_3 - GIO flag for pins GIOD[7:0]. */ +#define TMS570_GIO_FLG_GIOFLG_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_FLG_GIOFLG_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_FLG_GIOFLG_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOFLG_2 - GIO flag for pins GIOC[7:0]. */ +#define TMS570_GIO_FLG_GIOFLG_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_FLG_GIOFLG_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_FLG_GIOFLG_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOFLG_1 - GIO flag for pins GIOB[7:0]. */ +#define TMS570_GIO_FLG_GIOFLG_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_FLG_GIOFLG_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_FLG_GIOFLG_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOFLG_0 - GIO flag for pins GIOA[7:0]. */ +#define TMS570_GIO_FLG_GIOFLG_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_FLG_GIOFLG_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_FLG_GIOFLG_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_GIO_OFF1----------------------*/ +/* field: GIOOFF1 - GIO offset 1. These bits index the currently pending high-priority interrupt. */ +#define TMS570_GIO_OFF1_GIOOFF1(val) BSP_FLD32(val,0, 5) +#define TMS570_GIO_OFF1_GIOOFF1_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_GIO_OFF1_GIOOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_GIO_OFF2----------------------*/ +/* field: GIOOFF2 - GIO offset 2. These bits index the currently pending low-priority interrupt. */ +#define TMS570_GIO_OFF2_GIOOFF2(val) BSP_FLD32(val,0, 5) +#define TMS570_GIO_OFF2_GIOOFF2_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_GIO_OFF2_GIOOFF2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_GIO_EMU1----------------------*/ +/* field: GIOEMU1 - GIO offset emulation 1. These bits index the currently pending high-priority interrupt. */ +#define TMS570_GIO_EMU1_GIOEMU1(val) BSP_FLD32(val,0, 5) +#define TMS570_GIO_EMU1_GIOEMU1_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_GIO_EMU1_GIOEMU1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_GIO_EMU2----------------------*/ +/* field: GIOEMU2 - GIO offset emulation 2. These bits index the currently pending low-priority interrupt. */ +#define TMS570_GIO_EMU2_GIOEMU2(val) BSP_FLD32(val,0, 5) +#define TMS570_GIO_EMU2_GIOEMU2_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_GIO_EMU2_GIOEMU2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_GIO_ports----------------------*/ +/* field: GIOEMU2 - GIO offset emulation 2. These bits index the currently pending low-priority interrupt. */ +#define TMS570_GIO_ports_GIOEMU2(val) BSP_FLD32(val,0, 5) +#define TMS570_GIO_ports_GIOEMU2_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_GIO_ports_GIOEMU2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + + +#endif /* LIBBSP_ARM_TMS570_GIO */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h new file mode 100644 index 0000000000..3df27be461 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h @@ -0,0 +1,333 @@ +/* The header file is generated by make_header.py from HTU.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_HTU +#define LIBBSP_ARM_TMS570_HTU + +#include + +typedef struct{ + uint32_t GC; /*Global Control Register*/ + uint32_t CPENA; /*Control Packet Enable Register*/ + uint32_t BUSY0; /*Control Packet Busy Register 0*/ + uint32_t BUSY1; /*Control Packet Busy Register 1*/ + uint32_t BUSY2; /*Control Packet Busy Register 2*/ + uint32_t BUSY3; /*Control Packet Busy Register 3*/ + uint32_t ACPE; /*Active Control Packet and Error Register*/ + uint8_t reserved1 [4]; + uint32_t RLBECTRL; /*Request Lost and Bus Error Control Register*/ + uint32_t BFINTS; /*Buffer Full Interrupt Enable Set Register*/ + uint32_t BFINTC; /*Buffer Full Interrupt Enable Clear Register*/ + uint8_t reserved2 [8]; + uint32_t INTOFF0; /*Interrupt Offset Register 0*/ + uint32_t INTOFF1; /*Interrupt Offset Register 1*/ + uint32_t BIM; /*Buffer Initialization Mode Register*/ + uint32_t RLOSTFL; /*Request Lost Flag Register*/ + uint32_t BFINTFL; /*Buffer Full Interrupt Flag Register*/ + uint32_t BERINTFL; /*BER Interrupt Flag Register*/ + uint32_t MP1S; /*Memory Protection 1 Start Address Register*/ + uint32_t MP1E; /*Memory Protection 1 End Address Register*/ + uint32_t DCTRL; /*Debug Control Register*/ + uint32_t WPR; /*Watch Point Register*/ + uint32_t WMR; /*Watch Mask Register*/ + uint32_t ID; /*Module Identification Register*/ + uint32_t PCR; /*Parity Control Register*/ + uint32_t PAR; /*Parity Address Register*/ + uint8_t reserved3 [4]; + uint32_t MPCS; /*Memory Protection Control and Status Register*/ + uint32_t MP0S; /*Memory Protection 0 Start Address Register*/ + uint32_t MP0E; /*Memory Protection 0 End Address Register*/ +} tms570_htu_t; + + +/*-----------------------TMS570_HTU_GC-----------------------*/ +/* field: VBUSHOLD - Hold the VBUS bus */ +#define TMS570_HTU_GC_VBUSHOLD BSP_BIT32(24) + +/* field: HTUEN - Transfer Unit Enable Bit */ +#define TMS570_HTU_GC_HTUEN BSP_BIT32(16) + +/* field: DEBM - Debug Mode */ +#define TMS570_HTU_GC_DEBM BSP_BIT32(8) + +/* field: HTURES - HTU Software Reset Request */ +#define TMS570_HTU_GC_HTURES BSP_BIT32(0) + + +/*----------------------TMS570_HTU_CPENA----------------------*/ +/* field: CPENA - CP Enable Bits */ +#define TMS570_HTU_CPENA_CPENA(val) BSP_FLD32(val,0, 15) +#define TMS570_HTU_CPENA_CPENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_HTU_CPENA_CPENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_HTU_BUSY0----------------------*/ +/* field: BUSY0A - Busy Flag for CP A of DCP 0 */ +#define TMS570_HTU_BUSY0_BUSY0A BSP_BIT32(24) + +/* field: BUSY0B - Busy Flag for CP B of DCP 0 */ +#define TMS570_HTU_BUSY0_BUSY0B BSP_BIT32(16) + +/* field: BUSY1A - Busy Flag for CP A of DCP 1 */ +#define TMS570_HTU_BUSY0_BUSY1A BSP_BIT32(8) + +/* field: BUSY1B - Busy Flag for CP B of DCP 1 */ +#define TMS570_HTU_BUSY0_BUSY1B BSP_BIT32(0) + + +/*----------------------TMS570_HTU_BUSY1----------------------*/ +/* field: BUSY2A - Busy Flag for CP A of DCP 2 */ +#define TMS570_HTU_BUSY1_BUSY2A BSP_BIT32(24) + +/* field: BUSY2B - Busy Flag for CP B of DCP 2 */ +#define TMS570_HTU_BUSY1_BUSY2B BSP_BIT32(16) + +/* field: BUSY3A - Busy Flag for CP A of DCP 3 */ +#define TMS570_HTU_BUSY1_BUSY3A BSP_BIT32(8) + +/* field: BUSY3B - Busy Flag for CP B of DCP 3 */ +#define TMS570_HTU_BUSY1_BUSY3B BSP_BIT32(0) + + +/*----------------------TMS570_HTU_BUSY2----------------------*/ +/* field: BUSY4A - Busy Flag for CP A of DCP 4 */ +#define TMS570_HTU_BUSY2_BUSY4A BSP_BIT32(24) + +/* field: BUSY4B - Busy Flag for CP B of DCP 4 */ +#define TMS570_HTU_BUSY2_BUSY4B BSP_BIT32(16) + +/* field: BUSY5A - Busy Flag for CP A of DCP 5 */ +#define TMS570_HTU_BUSY2_BUSY5A BSP_BIT32(8) + +/* field: BUSY5B - Busy Flag for CP B of DCP 5 */ +#define TMS570_HTU_BUSY2_BUSY5B BSP_BIT32(0) + + +/*----------------------TMS570_HTU_BUSY3----------------------*/ +/* field: BUSY6A - Busy Flag for CP A of DCP 6 */ +#define TMS570_HTU_BUSY3_BUSY6A BSP_BIT32(24) + +/* field: BUSY6B - Busy Flag for CP B of DCP 6 */ +#define TMS570_HTU_BUSY3_BUSY6B BSP_BIT32(16) + +/* field: BUSY7A - Busy Flag for CP A of DCP 7 */ +#define TMS570_HTU_BUSY3_BUSY7A BSP_BIT32(8) + +/* field: BUSY7B - Busy Flag for CP B of DCP 7 */ +#define TMS570_HTU_BUSY3_BUSY7B BSP_BIT32(0) + + +/*----------------------TMS570_HTU_ACPE----------------------*/ +/* field: ERRF - Error Flag */ +#define TMS570_HTU_ACPE_ERRF BSP_BIT32(31) + + +/*--------------------TMS570_HTU_RLBECTRL--------------------*/ +/* field: BERINTENA - Bus Error Interrupt Enable Bit */ +#define TMS570_HTU_RLBECTRL_BERINTENA BSP_BIT32(16) + +/* field: CORL - Continue On Request Lost Error */ +#define TMS570_HTU_RLBECTRL_CORL BSP_BIT32(8) + +/* field: RLINTENA - Request Lost Interrupt Enable Bit */ +#define TMS570_HTU_RLBECTRL_RLINTENA BSP_BIT32(0) + + +/*---------------------TMS570_HTU_BFINTS---------------------*/ +/* field: BFINTENA - Bus Full Interrupt Enable Bits. */ +#define TMS570_HTU_BFINTS_BFINTENA(val) BSP_FLD32(val,0, 15) +#define TMS570_HTU_BFINTS_BFINTENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_HTU_BFINTS_BFINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_HTU_BFINTC---------------------*/ +/* field: BFINTDIS - */ +#define TMS570_HTU_BFINTC_BFINTDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_HTU_BFINTC_BFINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_HTU_BFINTC_BFINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_HTU_INTOFF0---------------------*/ +/* field: INTTYPE0 - Interrupt Type of Interrupt Line 0. */ +#define TMS570_HTU_INTOFF0_INTTYPE0(val) BSP_FLD32(val,8, 10) +#define TMS570_HTU_INTOFF0_INTTYPE0_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_HTU_INTOFF0_INTTYPE0_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: CPOFF0 - CP Offset. */ +#define TMS570_HTU_INTOFF0_CPOFF0(val) BSP_FLD32(val,0, 4) +#define TMS570_HTU_INTOFF0_CPOFF0_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_HTU_INTOFF0_CPOFF0_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*---------------------TMS570_HTU_INTOFF1---------------------*/ +/* field: INTTYPE1 - INTTYPE1 Interrupt Type of Interrupt Line 1. */ +#define TMS570_HTU_INTOFF1_INTTYPE1(val) BSP_FLD32(val,8, 10) +#define TMS570_HTU_INTOFF1_INTTYPE1_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_HTU_INTOFF1_INTTYPE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: CPOFF1 - CP Offset. */ +#define TMS570_HTU_INTOFF1_CPOFF1(val) BSP_FLD32(val,0, 4) +#define TMS570_HTU_INTOFF1_CPOFF1_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_HTU_INTOFF1_CPOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*-----------------------TMS570_HTU_BIM-----------------------*/ +/* field: BIM - Buffer Initialization Mode */ +#define TMS570_HTU_BIM_BIM(val) BSP_FLD32(val,0, 7) +#define TMS570_HTU_BIM_BIM_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_HTU_BIM_BIM_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_HTU_RLOSTFL---------------------*/ +/* field: CPRLFL - CP Request Lost Flags */ +#define TMS570_HTU_RLOSTFL_CPRLFL(val) BSP_FLD32(val,0, 15) +#define TMS570_HTU_RLOSTFL_CPRLFL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_HTU_RLOSTFL_CPRLFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_HTU_BFINTFL---------------------*/ +/* field: BFINTFL - Buffer Full Interrupt Flags */ +#define TMS570_HTU_BFINTFL_BFINTFL(val) BSP_FLD32(val,0, 15) +#define TMS570_HTU_BFINTFL_BFINTFL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_HTU_BFINTFL_BFINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_HTU_BERINTFL--------------------*/ +/* field: BERINTFL - Bus Error Interrupt Flags */ +#define TMS570_HTU_BERINTFL_BERINTFL(val) BSP_FLD32(val,0, 15) +#define TMS570_HTU_BERINTFL_BERINTFL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_HTU_BERINTFL_BERINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_HTU_MP1S----------------------*/ +/* field: STARTADDRESS1 - he start address defines at which main memory address the region begins. */ +/* Whole 32 bits */ + +/*----------------------TMS570_HTU_MP1E----------------------*/ +/* field: ENDADDRESS1 - The end address defines at which address the region ends. */ +/* Whole 32 bits */ + +/*----------------------TMS570_HTU_DCTRL----------------------*/ +/* field: CPNUM - CP Number. These bit fields indicate the CP which should cause the watch point to match. */ +#define TMS570_HTU_DCTRL_CPNUM(val) BSP_FLD32(val,24, 27) +#define TMS570_HTU_DCTRL_CPNUM_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_HTU_DCTRL_CPNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: HTUDBGS - HTU Debug Status. */ +#define TMS570_HTU_DCTRL_HTUDBGS BSP_BIT32(16) + +/* field: DBREN - Debug Request Enable */ +#define TMS570_HTU_DCTRL_DBREN BSP_BIT32(0) + + +/*-----------------------TMS570_HTU_WPR-----------------------*/ +/* field: WP - Watch Point Register */ +/* Whole 32 bits */ + +/*-----------------------TMS570_HTU_WMR-----------------------*/ +/* field: WM - Watch Mask Register */ +/* Whole 32 bits */ + +/*-----------------------TMS570_HTU_ID-----------------------*/ +/* field: CLASS - Module Class */ +#define TMS570_HTU_ID_CLASS(val) BSP_FLD32(val,16, 23) +#define TMS570_HTU_ID_CLASS_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_HTU_ID_CLASS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: TYPE - Subtype within a Class */ +#define TMS570_HTU_ID_TYPE(val) BSP_FLD32(val,8, 15) +#define TMS570_HTU_ID_TYPE_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_HTU_ID_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: REV - Module Revision Number */ +#define TMS570_HTU_ID_REV(val) BSP_FLD32(val,0, 7) +#define TMS570_HTU_ID_REV_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_HTU_ID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_HTU_PCR-----------------------*/ +/* field: COPE - Continue on Parity Error */ +#define TMS570_HTU_PCR_COPE BSP_BIT32(16) + +/* field: TEST - Test. */ +#define TMS570_HTU_PCR_TEST BSP_BIT32(8) + +/* field: PARITY_ENA - Enable/Disable Parity Checking. */ +#define TMS570_HTU_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3) +#define TMS570_HTU_PCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_HTU_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-----------------------TMS570_HTU_PAR-----------------------*/ +/* field: PEFT - Parity Error Fault Flag. */ +#define TMS570_HTU_PAR_PEFT BSP_BIT32(16) + +/* field: PAOFF - PAOFF */ +#define TMS570_HTU_PAR_PAOFF(val) BSP_FLD32(val,0, 8) +#define TMS570_HTU_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_HTU_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*----------------------TMS570_HTU_MPCS----------------------*/ +/* field: CPNUM0 - Control Packet Number for single memory protection region configuration. */ +#define TMS570_HTU_MPCS_CPNUM0(val) BSP_FLD32(val,24, 27) +#define TMS570_HTU_MPCS_CPNUM0_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_HTU_MPCS_CPNUM0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: MPEFT1 - MPEFT1 */ +#define TMS570_HTU_MPCS_MPEFT1 BSP_BIT32(17) + +/* field: MPEFT0 - Memory Protection Error Fault Flag 0. */ +#define TMS570_HTU_MPCS_MPEFT0 BSP_BIT32(16) + +/* field: CPNUM1 - Control Packet Number for single memory protection region configuration. */ +#define TMS570_HTU_MPCS_CPNUM1(val) BSP_FLD32(val,8, 11) +#define TMS570_HTU_MPCS_CPNUM1_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_HTU_MPCS_CPNUM1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + + +/*----------------------TMS570_HTU_MP0S----------------------*/ +/* field: ISTARTADDRESS0 - The start address defines at which main memory address the region begins. */ +/* Whole 32 bits */ + +/*----------------------TMS570_HTU_MP0E----------------------*/ +/* field: ENDADDRESS0 - The end address defines at which address the region ends. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_HTU */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h new file mode 100644 index 0000000000..63ed3f8d95 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h @@ -0,0 +1,363 @@ +/* The header file is generated by make_header.py from I2C.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_I2C +#define LIBBSP_ARM_TMS570_I2C + +#include + +typedef struct{ + uint32_t OAR; /*I2C Own Address Manager*/ + uint32_t IMR; /*I2C Interupt Mask Register*/ + uint32_t STR; /*I2C Status Register*/ + uint32_t CKL; /*I2C Clock Divider Low Register*/ + uint32_t CKH; /*I2C Clock Control High Register*/ + uint32_t CNT; /*I2C Data Count Register*/ + uint32_t DRR; /*I2C Data Receive Register*/ + uint32_t SAR; /*I2C Slave Address Register*/ + uint32_t DXR; /*I2C Data Transmit Register*/ + uint32_t MDR; /*I2C Mode Register*/ + uint32_t IVR; /*I2C Interrupt Vector Register*/ + uint32_t EMDR; /*I2C Extended Mode Register*/ + uint32_t PSC; /*I2C Prescale Register*/ + uint32_t PID11; /*I2C Peripheral ID Register 1*/ + uint32_t PID12; /*I2C Peripheral ID Register 2*/ + uint32_t DMACR; /*I2C DMA Control Register*/ + uint8_t reserved1 [8]; + uint32_t PFNC; /*I2C Pin Function Register*/ + uint32_t DIR; /*I2C Pin Direction Register*/ + uint32_t DIN; /*I2C Data Input Register*/ + uint32_t DOUT; /*I2C Data Output Register*/ + uint32_t SET; /*I2C Data Set Register*/ + uint32_t CLR; /*I2C Data Clear Register*/ + uint32_t PDR; /*I2C Pin Open Drain Register*/ + uint32_t PDIS; /*I2C Pull Disable Register*/ + uint32_t PSEL; /*I2C Pull Select Register*/ + uint32_t pSRS; /*I2C Pins Slew Rate Select Register*/ +} tms570_i2c_t; + + +/*-----------------------TMS570_I2C_OAR-----------------------*/ +/* field: OA - Own address */ +#define TMS570_I2C_OAR_OA(val) BSP_FLD32(val,0, 9) +#define TMS570_I2C_OAR_OA_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_I2C_OAR_OA_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*-----------------------TMS570_I2C_IMR-----------------------*/ +/* field: AASEN - Address As Slave Interrupt Enable */ +#define TMS570_I2C_IMR_AASEN BSP_BIT32(6) + +/* field: SCDEN - Stop Condition Interrupt Enable */ +#define TMS570_I2C_IMR_SCDEN BSP_BIT32(5) + +/* field: TXRDYEN - Transmit Data Ready Interrupt Enable */ +#define TMS570_I2C_IMR_TXRDYEN BSP_BIT32(4) + +/* field: RXRDYEN - Receive Data Ready Interrupt Enable */ +#define TMS570_I2C_IMR_RXRDYEN BSP_BIT32(3) + +/* field: ARDYEN - Register Access Ready Interrupt Enable */ +#define TMS570_I2C_IMR_ARDYEN BSP_BIT32(2) + +/* field: NACKEN - No Acknowledgement Interrupt Enable */ +#define TMS570_I2C_IMR_NACKEN BSP_BIT32(1) + +/* field: ALEN - Arbitration Lost Interrupt Enable */ +#define TMS570_I2C_IMR_ALEN BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_STR-----------------------*/ +/* field: SDIR - Slave direction */ +#define TMS570_I2C_STR_SDIR BSP_BIT32(14) + +/* field: NACKSNT - No acknowledge sent */ +#define TMS570_I2C_STR_NACKSNT BSP_BIT32(13) + +/* field: BB - Bus busy */ +#define TMS570_I2C_STR_BB BSP_BIT32(12) + +/* field: RSFULL - Receiver shift full */ +#define TMS570_I2C_STR_RSFULL BSP_BIT32(11) + +/* field: XSMT - XSMT */ +#define TMS570_I2C_STR_XSMT BSP_BIT32(10) + +/* field: AAS - Address as slave */ +#define TMS570_I2C_STR_AAS BSP_BIT32(9) + +/* field: AD0 - Address zero status */ +#define TMS570_I2C_STR_AD0 BSP_BIT32(8) + +/* field: SCD - SCD */ +#define TMS570_I2C_STR_SCD BSP_BIT32(5) + +/* field: TXRDY - Transmit data ready interrupt flag */ +#define TMS570_I2C_STR_TXRDY BSP_BIT32(4) + +/* field: RXRDY - Receive data ready interrupt flag */ +#define TMS570_I2C_STR_RXRDY BSP_BIT32(3) + +/* field: ARDY - Register access ready interrupt flag */ +#define TMS570_I2C_STR_ARDY BSP_BIT32(2) + +/* field: NACK - No acknowledgement interrupt */ +#define TMS570_I2C_STR_NACK BSP_BIT32(1) + +/* field: AL - Arbitration lost interrupt flag */ +#define TMS570_I2C_STR_AL BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_CKL-----------------------*/ +/* field: CLKL - Low time clock division factor */ +#define TMS570_I2C_CKL_CLKL(val) BSP_FLD32(val,0, 15) +#define TMS570_I2C_CKL_CLKL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_I2C_CKL_CLKL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-----------------------TMS570_I2C_CKH-----------------------*/ +/* field: CLKH - High time clock division factor */ +#define TMS570_I2C_CKH_CLKH(val) BSP_FLD32(val,0, 15) +#define TMS570_I2C_CKH_CLKH_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_I2C_CKH_CLKH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-----------------------TMS570_I2C_CNT-----------------------*/ +/* field: CNT - Data counter */ +#define TMS570_I2C_CNT_CNT(val) BSP_FLD32(val,0, 15) +#define TMS570_I2C_CNT_CNT_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_I2C_CNT_CNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-----------------------TMS570_I2C_DRR-----------------------*/ +/* field: DATARX - Receive data */ +#define TMS570_I2C_DRR_DATARX(val) BSP_FLD32(val,0, 7) +#define TMS570_I2C_DRR_DATARX_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_I2C_DRR_DATARX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_I2C_SAR-----------------------*/ +/* field: SA - 7- or 10-bit programmable slave address */ +#define TMS570_I2C_SAR_SA(val) BSP_FLD32(val,0, 9) +#define TMS570_I2C_SAR_SA_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_I2C_SAR_SA_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*-----------------------TMS570_I2C_DXR-----------------------*/ +/* field: DATATX - Transmit data */ +#define TMS570_I2C_DXR_DATATX(val) BSP_FLD32(val,0, 7) +#define TMS570_I2C_DXR_DATATX_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_I2C_DXR_DATATX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_I2C_MDR-----------------------*/ +/* field: NACKMOD - No-acknowledge (NACK) mode */ +#define TMS570_I2C_MDR_NACKMOD BSP_BIT32(15) + +/* field: FREE - Free running bit */ +#define TMS570_I2C_MDR_FREE BSP_BIT32(14) + +/* field: STT - Start condition */ +#define TMS570_I2C_MDR_STT BSP_BIT32(13) + +/* field: STP - Stop condition */ +#define TMS570_I2C_MDR_STP BSP_BIT32(11) + +/* field: MST - Master/slave mode bit */ +#define TMS570_I2C_MDR_MST BSP_BIT32(10) + +/* field: TRX - Transmit/receive bit */ +#define TMS570_I2C_MDR_TRX BSP_BIT32(9) + +/* field: XA - Expand address enable bit */ +#define TMS570_I2C_MDR_XA BSP_BIT32(8) + +/* field: RM - RM */ +#define TMS570_I2C_MDR_RM BSP_BIT32(7) + +/* field: DLB - Digital loop back enable bit */ +#define TMS570_I2C_MDR_DLB BSP_BIT32(6) + +/* field: nIRS - I2C reset enable bit */ +#define TMS570_I2C_MDR_nIRS BSP_BIT32(5) + +/* field: STB - Start byte mode enable bit (Master mode only) */ +#define TMS570_I2C_MDR_STB BSP_BIT32(4) + +/* field: FDF - Free data format enable bit */ +#define TMS570_I2C_MDR_FDF BSP_BIT32(3) + +/* field: BC - Bit count */ +#define TMS570_I2C_MDR_BC(val) BSP_FLD32(val,0, 2) +#define TMS570_I2C_MDR_BC_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_I2C_MDR_BC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------------TMS570_I2C_IVR-----------------------*/ +/* field: TESTMD - Reserved for internal testing. */ +#define TMS570_I2C_IVR_TESTMD(val) BSP_FLD32(val,8, 11) +#define TMS570_I2C_IVR_TESTMD_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_I2C_IVR_TESTMD_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: INTCODE - Interrupt Code Bits */ +#define TMS570_I2C_IVR_INTCODE(val) BSP_FLD32(val,0, 2) +#define TMS570_I2C_IVR_INTCODE_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_I2C_IVR_INTCODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*----------------------TMS570_I2C_EMDR----------------------*/ +/* field: IGNACK - Ignore NACK mode */ +#define TMS570_I2C_EMDR_IGNACK BSP_BIT32(1) + +/* field: BCM - Backwards compatibility mode */ +#define TMS570_I2C_EMDR_BCM BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_PSC-----------------------*/ +/* field: PSC - Prescale */ +#define TMS570_I2C_PSC_PSC(val) BSP_FLD32(val,0, 7) +#define TMS570_I2C_PSC_PSC_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_I2C_PSC_PSC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_I2C_PID11----------------------*/ +/* field: CLASS - Peripheral class */ +#define TMS570_I2C_PID11_CLASS(val) BSP_FLD32(val,8, 15) +#define TMS570_I2C_PID11_CLASS_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_I2C_PID11_CLASS_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: REVISION - Revision level of the I2C */ +#define TMS570_I2C_PID11_REVISION(val) BSP_FLD32(val,0, 7) +#define TMS570_I2C_PID11_REVISION_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_I2C_PID11_REVISION_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_I2C_PID12----------------------*/ +/* field: TYPE - Peripheral type */ +#define TMS570_I2C_PID12_TYPE(val) BSP_FLD32(val,0, 7) +#define TMS570_I2C_PID12_TYPE_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_I2C_PID12_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_I2C_DMACR----------------------*/ +/* field: TXDMAEN - Transmitter DMA enable */ +#define TMS570_I2C_DMACR_TXDMAEN BSP_BIT32(1) + +/* field: RXDMAEN - Receive DMA enable */ +#define TMS570_I2C_DMACR_RXDMAEN BSP_BIT32(0) + + +/*----------------------TMS570_I2C_PFNC----------------------*/ +/* field: PINFUNC - SDA and SCL Pin Function */ +#define TMS570_I2C_PFNC_PINFUNC BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_DIR-----------------------*/ +/* field: SDADIR - SDA direction */ +#define TMS570_I2C_DIR_SDADIR BSP_BIT32(1) + +/* field: SCLDIR - SCL direction */ +#define TMS570_I2C_DIR_SCLDIR BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_DIN-----------------------*/ +/* field: SDAIN - Serial data in */ +#define TMS570_I2C_DIN_SDAIN BSP_BIT32(1) + +/* field: SCLIN - Serial clock data in */ +#define TMS570_I2C_DIN_SCLIN BSP_BIT32(0) + + +/*----------------------TMS570_I2C_DOUT----------------------*/ +/* field: SDAOUT - SDA Data Output */ +#define TMS570_I2C_DOUT_SDAOUT BSP_BIT32(1) + +/* field: SCLOUT - SCL Data Output */ +#define TMS570_I2C_DOUT_SCLOUT BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_SET-----------------------*/ +/* field: SDASET - Serial Data Set */ +#define TMS570_I2C_SET_SDASET BSP_BIT32(1) + +/* field: SCLSET - Serial Clock Set */ +#define TMS570_I2C_SET_SCLSET BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_CLR-----------------------*/ +/* field: SDACLR - Serial Data Clear */ +#define TMS570_I2C_CLR_SDACLR BSP_BIT32(1) + +/* field: SCLCLR - Serial Clock Clear */ +#define TMS570_I2C_CLR_SCLCLR BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_PDR-----------------------*/ +/* field: SDAPDR - SDA pin open drain enable */ +#define TMS570_I2C_PDR_SDAPDR BSP_BIT32(1) + +/* field: SCLPDR - SCL pin open drain enable */ +#define TMS570_I2C_PDR_SCLPDR BSP_BIT32(0) + + +/*----------------------TMS570_I2C_PDIS----------------------*/ +/* field: SDAPDIS - SDA pull disable */ +#define TMS570_I2C_PDIS_SDAPDIS BSP_BIT32(1) + +/* field: SCLPDIS - SCL pull disable */ +#define TMS570_I2C_PDIS_SCLPDIS BSP_BIT32(0) + + +/*----------------------TMS570_I2C_PSEL----------------------*/ +/* field: SDAPSEL - SDA pull select */ +#define TMS570_I2C_PSEL_SDAPSEL BSP_BIT32(1) + +/* field: SCLPSEL - SCL pull select */ +#define TMS570_I2C_PSEL_SCLPSEL BSP_BIT32(0) + + +/*----------------------TMS570_I2C_pSRS----------------------*/ +/* field: SDASRS - SDA Slew Rate select */ +#define TMS570_I2C_pSRS_SDASRS BSP_BIT32(1) + +/* field: SCLSRS - SCL Slew Rate select */ +#define TMS570_I2C_pSRS_SCLSRS BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_I2C */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h new file mode 100644 index 0000000000..f6197e811c --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h @@ -0,0 +1,235 @@ +/* The header file is generated by make_header.py from IOMM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_IOMM +#define LIBBSP_ARM_TMS570_IOMM + +#include + +typedef struct{ + uint32_t PINMMR0; /*Pin Multiplexing Control Register 0*/ + uint32_t PINMMR1; /*Pin Multiplexing Control Register 1*/ + uint32_t PINMMR2; /*Pin Multiplexing Control Register 2*/ + uint32_t PINMMR3; /*Pin Multiplexing Control Register 3*/ + uint32_t PINMMR4; /*Pin Multiplexing Control Register 4*/ + uint32_t PINMMR5; /*Pin Multiplexing Control Register 5*/ + uint32_t PINMMR6; /*Pin Multiplexing Control Register 6*/ + uint32_t PINMMR7; /*Pin Multiplexing Control Register 7*/ + uint32_t PINMMR8; /*Pin Multiplexing Control Register 8*/ + uint32_t PINMMR9; /*Pin Multiplexing Control Register 9*/ + uint32_t PINMMR10; /*Pin Multiplexing Control Register 10*/ + uint32_t PINMMR11; /*Pin Multiplexing Control Register 11*/ + uint32_t PINMMR12; /*Pin Multiplexing Control Register 12*/ + uint32_t PINMMR13; /*Pin Multiplexing Control Register 13*/ + uint32_t PINMMR14; /*Pin Multiplexing Control Register 14*/ + uint32_t PINMMR15; /*Pin Multiplexing Control Register 15*/ + uint32_t PINMMR16; /*Pin Multiplexing Control Register 16*/ + uint32_t PINMMR17; /*Pin Multiplexing Control Register 17*/ + uint32_t PINMMR18; /*Pin Multiplexing Control Register 18*/ + uint32_t PINMMR19; /*Pin Multiplexing Control Register 19*/ + uint32_t PINMMR20; /*Pin Multiplexing Control Register 20*/ + uint32_t PINMMR21; /*Pin Multiplexing Control Register 21*/ + uint32_t PINMMR22; /*Pin Multiplexing Control Register 22*/ + uint32_t PINMMR23; /*Pin Multiplexing Control Register 23*/ + uint32_t PINMMR24; /*Pin Multiplexing Control Register 24*/ + uint32_t PINMMR25; /*Pin Multiplexing Control Register 25*/ + uint32_t PINMMR26; /*Pin Multiplexing Control Register 26*/ + uint32_t PINMMR27; /*Pin Multiplexing Control Register 27*/ + uint32_t PINMMR28; /*Pin Multiplexing Control Register 28*/ + uint32_t PINMMR29; /*Pin Multiplexing Control Register 29*/ + uint32_t PINMMR30; /*Pin Multiplexing Control Register 30*/ +} tms570_pinmux_t; + +typedef struct{ + uint32_t REVISION_REG; /*Revision Register*/ + uint8_t reserved1 [28]; + uint32_t ENDIAN_REG; /*Device Endianness Register*/ + uint8_t reserved2 [20]; + uint32_t KICK_REG0; /*Kicker Register 0*/ + uint32_t KICK_REG1; /*Kicker Register 1*/ + uint8_t reserved3 [160]; + uint32_t ERR_RAW_STATUS_REG;/*Error Raw Status / Set Register*/ + uint32_t ERR_ENABLED_STATUS_REG;/*Error Enabled Status / Clear Register*/ + uint32_t ERR_ENABLE_REG; /*Error Signaling Enable Register*/ + uint32_t ERR_ENABLE_CLR_REG;/*Error Signaling Enable Clear Register*/ + uint8_t reserved4 [4]; + uint32_t FAULT_ADDRESS_REG; /*Fault Address Register*/ + uint32_t FAULT_STATUS_REG; /*Fault Status Register*/ + uint32_t FAULT_CLEAR_REG; /*Fault Clear Register*/ + uint8_t reserved5 [16]; + tms570_pinmux_t PINMUX; /*Pin Multiplexing Control Registers*/ +} tms570_iomm_t; + + +/*--------------------TMS570_IOMM_PINMMRx--------------------*/ +/* field: PINMMRx24To31 - Each of these byte-fields control the functionality on a given ball/pin. */ +#define TMS570_IOMM_PINMMRx_PINMMRx24To31(val) BSP_FLD32(val,24, 31) +#define TMS570_IOMM_PINMMRx_PINMMRx24To31_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_IOMM_PINMMRx_PINMMRx24To31_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: PINMMRx16To23 - Each of these byte-fields control the functionality on a given ball/pin. */ +#define TMS570_IOMM_PINMMRx_PINMMRx16To23(val) BSP_FLD32(val,16, 23) +#define TMS570_IOMM_PINMMRx_PINMMRx16To23_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_IOMM_PINMMRx_PINMMRx16To23_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: PINMMRx8To16 - Each of these byte-fields control the functionality on a given ball/pin. */ +#define TMS570_IOMM_PINMMRx_PINMMRx8To16(val) BSP_FLD32(val,8, 15) +#define TMS570_IOMM_PINMMRx_PINMMRx8To16_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_IOMM_PINMMRx_PINMMRx8To16_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: PINMMRx0To7 - Each of these byte-fields control the functionality on a given ball/pin. */ +#define TMS570_IOMM_PINMMRx_PINMMRx0To7(val) BSP_FLD32(val,0, 7) +#define TMS570_IOMM_PINMMRx_PINMMRx0To7_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_IOMM_PINMMRx_PINMMRx0To7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_IOMM_REVISION_REG------------------*/ +/* field: REV_SCHEME - Revision Scheme */ +#define TMS570_IOMM_REVISION_REG_REV_SCHEME(val) BSP_FLD32(val,30, 31) +#define TMS570_IOMM_REVISION_REG_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31) +#define TMS570_IOMM_REVISION_REG_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31) + +/* field: REV_MODULE - Module Id */ +#define TMS570_IOMM_REVISION_REG_REV_MODULE(val) BSP_FLD32(val,16, 27) +#define TMS570_IOMM_REVISION_REG_REV_MODULE_GET(reg) BSP_FLD32GET(reg,16, 27) +#define TMS570_IOMM_REVISION_REG_REV_MODULE_SET(reg,val) BSP_FLD32SET(reg, val,16, 27) + +/* field: REV_RTL - RTL Revision */ +#define TMS570_IOMM_REVISION_REG_REV_RTL(val) BSP_FLD32(val,11, 15) +#define TMS570_IOMM_REVISION_REG_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15) +#define TMS570_IOMM_REVISION_REG_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15) + +/* field: REV_MAJOR - Major Revision */ +#define TMS570_IOMM_REVISION_REG_REV_MAJOR(val) BSP_FLD32(val,8, 10) +#define TMS570_IOMM_REVISION_REG_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_IOMM_REVISION_REG_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: REV_CUSTOM - REV CUSTOM 0 Custom Revision */ +#define TMS570_IOMM_REVISION_REG_REV_CUSTOM(val) BSP_FLD32(val,6, 7) +#define TMS570_IOMM_REVISION_REG_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_IOMM_REVISION_REG_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: REV_MINOR - Minor Revision */ +#define TMS570_IOMM_REVISION_REG_REV_MINOR(val) BSP_FLD32(val,0, 5) +#define TMS570_IOMM_REVISION_REG_REV_MINOR_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_IOMM_REVISION_REG_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_IOMM_ENDIAN_REG-------------------*/ +/* field: ENDIAN - Device endianness */ +#define TMS570_IOMM_ENDIAN_REG_ENDIAN BSP_BIT32(0) + + +/*-------------------TMS570_IOMM_KICK_REG0-------------------*/ +/* field: KICK0 - Kicker 0 Register. */ +/* Whole 32 bits */ + +/*-------------------TMS570_IOMM_KICK_REG1-------------------*/ +/* field: KICK1 - Kicker 1 Register. */ +/* Whole 32 bits */ + +/*---------------TMS570_IOMM_ERR_RAW_STATUS_REG---------------*/ +/* field: ADDR_ERR - Addressing Error Status and Error Signaling Enable. */ +#define TMS570_IOMM_ERR_RAW_STATUS_REG_ADDR_ERR BSP_BIT32(1) + +/* field: PROT_ERR - register inside the IOMM is written in the CPU's user mode of operation. */ +#define TMS570_IOMM_ERR_RAW_STATUS_REG_PROT_ERR BSP_BIT32(0) + + +/*-------------TMS570_IOMM_ERR_ENABLED_STATUS_REG-------------*/ +/* field: ENABLED_ADDR_ERR - Addressing Error Signaling Enable Status and Status Clear */ +#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_ADDR_ERR BSP_BIT32(1) + +/* field: ENABLED_PROT_ERR - Protection Error Signaling Enable Status and Status Clear */ +#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_PROT_ERR BSP_BIT32(0) + + +/*-----------------TMS570_IOMM_ERR_ENABLE_REG-----------------*/ +/* field: ADDR_ERR_EN - Addressing Error Signaling Enable */ +#define TMS570_IOMM_ERR_ENABLE_REG_ADDR_ERR_EN BSP_BIT32(1) + +/* field: PROT_ERR_EN - Protection ErrorSignaling Enable */ +#define TMS570_IOMM_ERR_ENABLE_REG_PROT_ERR_EN BSP_BIT32(0) + + +/*---------------TMS570_IOMM_ERR_ENABLE_CLR_REG---------------*/ +/* field: ADDR_ERR_EN_CLR - Addressing Error Signaling Enable Clear */ +#define TMS570_IOMM_ERR_ENABLE_CLR_REG_ADDR_ERR_EN_CLR BSP_BIT32(1) + +/* field: PROT_ERR_EN_CLR - Protection Error Signaling Enable Clear */ +#define TMS570_IOMM_ERR_ENABLE_CLR_REG_PROT_ERR_EN_CLR BSP_BIT32(0) + + +/*---------------TMS570_IOMM_FAULT_ADDRESS_REG---------------*/ +/* field: FAULT_ADDR - Fault Address. */ +/* Whole 32 bits */ + +/*----------------TMS570_IOMM_FAULT_STATUS_REG----------------*/ +/* field: FAULT_ID - Faulting Transaction ID */ +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID(val) BSP_FLD32(val,24, 27) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: FAULT_MSTID - ID of Master that initiated the faulting transaction */ +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_MSTID(val) BSP_FLD32(val,16, 23) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_MSTID_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_MSTID_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: FAULT_PRIVID - Faulting Privilege ID */ +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_PRIVID(val) BSP_FLD32(val,9, 12) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_PRIVID_GET(reg) BSP_FLD32GET(reg,9, 12) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_PRIVID_SET(reg,val) BSP_FLD32SET(reg, val,9, 12) + +/* field: FAULT_TYPE - Type of fault detected */ +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE(val) BSP_FLD32(val,0, 5) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------TMS570_IOMM_FAULT_CLEAR_REG----------------*/ +/* field: FAULT_CLEAR - Fault Clear */ +#define TMS570_IOMM_FAULT_CLEAR_REG_FAULT_CLEAR BSP_BIT32(0) + + +/*---------------------TMS570_IOMM_PINMUX---------------------*/ +/* field: FAULT_CLEAR - Fault Clear */ +#define TMS570_IOMM_PINMUX_FAULT_CLEAR BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_IOMM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h new file mode 100644 index 0000000000..d2c3a3bfe8 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h @@ -0,0 +1,594 @@ +/* The header file is generated by make_header.py from LIN.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_LIN +#define LIBBSP_ARM_TMS570_LIN + +#include + +typedef struct{ + uint32_t GCR0; /*SCI Global Control Register 0*/ + uint32_t GCR1; /*SCI Global Control Register 1*/ + uint32_t GCR2; /*SCI Global Control Register 2*/ + uint32_t SETINT; /*SCI Set Interrupt Register*/ + uint32_t CLEARINT; /*SCI Clear Interrupt Register*/ + uint32_t SETINTLVL; /*SCI Set Interrupt Level Register*/ + uint32_t CLEARINTLVL; /*SCI Clear Interrupt Level Register*/ + uint32_t FLR; /*SCI Flags Register*/ + uint32_t INTVECT0; /*SCI Interrupt Vector Offset 0*/ + uint32_t INTVECT1; /*SCI Interrupt Vector Offset 1*/ + uint32_t FORMAT; /*SCI Format Control Register*/ + uint32_t BRS; /*Baud Rate Selection Register*/ + uint32_t ED; /*Receiver Emulation Data Buffer*/ + uint32_t RD; /*Receiver Data Buffer*/ + uint32_t TD; /*Transmit Data Buffer*/ + uint32_t PIO0; /*SCI Pin I/O Control Register 0*/ + uint32_t PIO1; /*SCI Pin I/O Control Register 1*/ + uint32_t PIO2; /*SCI Pin I/O Control Register 2*/ + uint32_t PIO3; /*SCI Pin I/O Control Register 3*/ + uint32_t PIO4; /*SCI Pin I/O Control Register 4*/ + uint32_t PIO5; /*SCI Pin I/O Control Register 5*/ + uint32_t PIO6; /*SCI Pin I/O Control Register 6*/ + uint32_t PIO7; /*SCI Pin I/O Control Register 7*/ + uint32_t PIO8; /*SCI Pin I/O Control Register 8*/ + uint32_t COMP; /*LIN Compare Register*/ + uint32_t RD0; /*LIN Receive Buffer 0 Register*/ + uint32_t RD1; /*LIN Receive Buffer 1 Register*/ + uint32_t MASK; /*LIN Mask Register*/ + uint32_t ID; /*LIN Identification Register*/ + uint32_t TD0; /*LIN Transmit Buffer 0*/ + uint32_t TD1; /*LIN Transmit Buffer 1*/ + uint32_t MBRSR; /*Maximum Baud Rate Selection Register*/ + uint8_t reserved1 [16]; + uint32_t IODFTCTRL; /*Input/Output Error Enable Register*/ +} tms570_lin_t; + + +/*----------------------TMS570_LIN_GCR0----------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +#define TMS570_LIN_GCR0_Reserved(val) BSP_FLD32(val,1, 31) +#define TMS570_LIN_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31) +#define TMS570_LIN_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31) + +/* field: RESET - This bit resets the SCI module. */ +#define TMS570_LIN_GCR0_RESET BSP_BIT32(0) + + +/*----------------------TMS570_LIN_GCR1----------------------*/ +/* field: TXENA - Transmit enable. */ +#define TMS570_LIN_GCR1_TXENA BSP_BIT32(25) + +/* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */ +#define TMS570_LIN_GCR1_RXENA BSP_BIT32(24) + +/* field: CONT - Continue on suspend. */ +#define TMS570_LIN_GCR1_CONT BSP_BIT32(17) + +/* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */ +#define TMS570_LIN_GCR1_LOOP_BACK BSP_BIT32(16) + +/* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */ +#define TMS570_LIN_GCR1_POWERDOWN BSP_BIT32(9) + +/* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */ +#define TMS570_LIN_GCR1_SLEEP BSP_BIT32(8) + +/* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */ +#define TMS570_LIN_GCR1_SWnRST BSP_BIT32(7) + +/* field: CLOCK - CLOCK */ +#define TMS570_LIN_GCR1_CLOCK BSP_BIT32(5) + +/* field: STOP - SCI number of stop bits per frame. */ +#define TMS570_LIN_GCR1_STOP BSP_BIT32(4) + +/* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */ +#define TMS570_LIN_GCR1_PARITY BSP_BIT32(3) + +/* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */ +#define TMS570_LIN_GCR1_PARITY_ENA BSP_BIT32(2) + +/* field: TIMING_MODE - SCI timing mode bit. */ +#define TMS570_LIN_GCR1_TIMING_MODE BSP_BIT32(1) + +/* field: COMM_MODE - SCI communication mode bit. */ +#define TMS570_LIN_GCR1_COMM_MODE BSP_BIT32(0) + + +/*----------------------TMS570_LIN_GCR2----------------------*/ +/* field: CC - Compare checksum. LIN mode only. */ +#define TMS570_LIN_GCR2_CC BSP_BIT32(17) + +/* field: SC - Send checksum byte. This bit is effective in LIN mode only. */ +#define TMS570_LIN_GCR2_SC BSP_BIT32(16) + +/* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */ +#define TMS570_LIN_GCR2_GEN_WU BSP_BIT32(8) + +/* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */ +#define TMS570_LIN_GCR2_POWERDOWN BSP_BIT32(0) + + +/*---------------------TMS570_LIN_SETINT---------------------*/ +/* field: SET_FE_INT - */ +#define TMS570_LIN_SETINT_SET_FE_INT BSP_BIT32(26) + +/* field: SET_OE_INT - SET OE INT */ +#define TMS570_LIN_SETINT_SET_OE_INT BSP_BIT32(25) + +/* field: SET_PE_INT - Set parity interrupt. */ +#define TMS570_LIN_SETINT_SET_PE_INT BSP_BIT32(24) + +/* field: SET_RX_DMA_ALL - SET RX DMA ALL */ +#define TMS570_LIN_SETINT_SET_RX_DMA_ALL BSP_BIT32(18) + +/* field: SET_RX_DMA - SET RX DMA */ +#define TMS570_LIN_SETINT_SET_RX_DMA BSP_BIT32(17) + +/* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */ +#define TMS570_LIN_SETINT_SET_TX_DMA BSP_BIT32(16) + +/* field: SET_RX_INT - SET RX INT */ +#define TMS570_LIN_SETINT_SET_RX_INT BSP_BIT32(9) + +/* field: SET_TX_INT - Set transmitter interrupt. */ +#define TMS570_LIN_SETINT_SET_TX_INT BSP_BIT32(8) + +/* field: SET_WAKEUP_INT - Set wakeup interrupt. */ +#define TMS570_LIN_SETINT_SET_WAKEUP_INT BSP_BIT32(1) + +/* field: SET_BRKDT_INT - Set breakdetect interrupt. */ +#define TMS570_LIN_SETINT_SET_BRKDT_INT BSP_BIT32(0) + + +/*--------------------TMS570_LIN_CLEARINT--------------------*/ +/* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_FE_INT BSP_BIT32(26) + +/* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_CE_INT BSP_BIT32(25) + +/* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_PE_INT BSP_BIT32(24) + +/* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */ +#define TMS570_LIN_CLEARINT_CLR_RX_DMA_ALL BSP_BIT32(18) + +/* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */ +#define TMS570_LIN_CLEARINT_CLR_RX_DMA BSP_BIT32(17) + +/* field: CLR_TX_DMA - CLR TX DMA */ +#define TMS570_LIN_CLEARINT_CLR_TX_DMA BSP_BIT32(16) + +/* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_RX_INT BSP_BIT32(9) + +/* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_TX_INT BSP_BIT32(8) + +/* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_WAKEUP_INT BSP_BIT32(1) + +/* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_BRKDT_INT BSP_BIT32(0) + + +/*--------------------TMS570_LIN_SETINTLVL--------------------*/ +/* field: SET_FE_INT_LVL - Set framing-error interrupt level. */ +#define TMS570_LIN_SETINTLVL_SET_FE_INT_LVL BSP_BIT32(26) + +/* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */ +#define TMS570_LIN_SETINTLVL_SET_CE_INT_LVL BSP_BIT32(25) + +/* field: SET_PE_INT_LVL - Set parity error interrupt level. */ +#define TMS570_LIN_SETINTLVL_SET_PE_INT_LVL BSP_BIT32(24) + +/* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */ +#define TMS570_LIN_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_BIT32(18) + +/* field: SET_RX_INT_LVL - Set receiver interrupt level. */ +#define TMS570_LIN_SETINTLVL_SET_RX_INT_LVL BSP_BIT32(9) + +/* field: SET_TX_INT_LVL - Set transmitter interrupt level. */ +#define TMS570_LIN_SETINTLVL_SET_TX_INT_LVL BSP_BIT32(8) + +/* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */ +#define TMS570_LIN_SETINTLVL_SET_WAKEUP_INT_LVL BSP_BIT32(1) + +/* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */ +#define TMS570_LIN_SETINTLVL_SET_BRKDT_INT_LVL BSP_BIT32(0) + + +/*-------------------TMS570_LIN_CLEARINTLVL-------------------*/ +/* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */ +#define TMS570_LIN_CLEARINTLVL_CLR_FE_INT_LVL BSP_BIT32(26) + +/* field: CLR_CE_INT_LVL - CLR CE INT LVL */ +#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25) + +/* field: CLR_CE_INT_LVL - CLR CE INT LVL */ +#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25) + +/* field: CLR_PE_INT_LVL - */ +#define TMS570_LIN_CLEARINTLVL_CLR_PE_INT_LVL BSP_BIT32(24) + +/* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */ +#define TMS570_LIN_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_BIT32(18) + +/* field: CLR_RX_INT_LVL - Clear receiver interrupt. */ +#define TMS570_LIN_CLEARINTLVL_CLR_RX_INT_LVL BSP_BIT32(9) + +/* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */ +#define TMS570_LIN_CLEARINTLVL_8 BSP_BIT32(8) + +/* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */ +#define TMS570_LIN_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_BIT32(1) + +/* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */ +#define TMS570_LIN_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_BIT32(0) + + +/*-----------------------TMS570_LIN_FLR-----------------------*/ +/* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */ +#define TMS570_LIN_FLR_FE BSP_BIT32(26) + +/* field: OE - Overrun error flag. */ +#define TMS570_LIN_FLR_OE BSP_BIT32(25) + +/* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */ +#define TMS570_LIN_FLR_PE BSP_BIT32(24) + +/* field: RXWAKE - Receiver wakeup detect flag. */ +#define TMS570_LIN_FLR_RXWAKE BSP_BIT32(12) + +/* field: TX_EMPTY - Transmitter empty flag. */ +#define TMS570_LIN_FLR_TX_EMPTY BSP_BIT32(11) + +/* field: TXWAKE - Transmitter wakeup method select. */ +#define TMS570_LIN_FLR_TXWAKE BSP_BIT32(10) + +/* field: RXRDY - Receiver ready flag. */ +#define TMS570_LIN_FLR_RXRDY BSP_BIT32(9) + +/* field: TXRDY - Transmitter buffer register ready flag. */ +#define TMS570_LIN_FLR_TXRDY BSP_BIT32(8) + +/* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */ +#define TMS570_LIN_FLR_BUSY BSP_BIT32(3) + +/* field: IDLE - SCI receiver in idle state. */ +#define TMS570_LIN_FLR_IDLE BSP_BIT32(2) + +/* field: WAKEUP - Wakeup flag. */ +#define TMS570_LIN_FLR_WAKEUP BSP_BIT32(1) + +/* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */ +#define TMS570_LIN_FLR_BRKDT BSP_BIT32(0) + + +/*--------------------TMS570_LIN_INTVECT0--------------------*/ +/* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */ +#define TMS570_LIN_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3) +#define TMS570_LIN_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_LIN_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_LIN_INTVECT1--------------------*/ +/* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */ +#define TMS570_LIN_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3) +#define TMS570_LIN_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_LIN_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_LIN_FORMAT---------------------*/ +/* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */ +#define TMS570_LIN_FORMAT_CHAR(val) BSP_FLD32(val,0, 2) +#define TMS570_LIN_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_LIN_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------------TMS570_LIN_BRS-----------------------*/ +/* field: BAUD - SCI 24-bit baud selection. */ +#define TMS570_LIN_BRS_BAUD(val) BSP_FLD32(val,0, 23) +#define TMS570_LIN_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_LIN_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*-----------------------TMS570_LIN_ED-----------------------*/ +/* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */ +#define TMS570_LIN_ED_ED(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_LIN_RD-----------------------*/ +/* field: RD - Receiver data. */ +#define TMS570_LIN_RD_RD(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_LIN_TD-----------------------*/ +/* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */ +#define TMS570_LIN_TD_TD(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_LIN_PIO0----------------------*/ +/* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */ +#define TMS570_LIN_PIO0_TX_FUNC BSP_BIT32(2) + +/* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */ +#define TMS570_LIN_PIO0_RX_FUNC BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO1----------------------*/ +/* field: TX_DIR - Transmit pin direction. */ +#define TMS570_LIN_PIO1_TX_DIR BSP_BIT32(2) + +/* field: RX_DIR - Receive pin direction. */ +#define TMS570_LIN_PIO1_RX_DIR BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO2----------------------*/ +/* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */ +#define TMS570_LIN_PIO2_TX_IN BSP_BIT32(2) + +/* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */ +#define TMS570_LIN_PIO2_RX_IN BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO3----------------------*/ +/* field: TX_OUT - Transmit pin out. */ +#define TMS570_LIN_PIO3_TX_OUT BSP_BIT32(2) + +/* field: RX_OUT - Receive pin out. */ +#define TMS570_LIN_PIO3_RX_OUT BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO4----------------------*/ +/* field: TX_SET - Transmit pin set. */ +#define TMS570_LIN_PIO4_TX_SET BSP_BIT32(2) + +/* field: RX_SET - Receive pin set. */ +#define TMS570_LIN_PIO4_RX_SET BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO5----------------------*/ +/* field: TX_CLR - Transmit pin clear. */ +#define TMS570_LIN_PIO5_TX_CLR BSP_BIT32(2) + +/* field: RX_CLR - Receive pin clear. */ +#define TMS570_LIN_PIO5_RX_CLR BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO6----------------------*/ +/* field: TX_PDR - Transmit pin open drain enable. */ +#define TMS570_LIN_PIO6_TX_PDR BSP_BIT32(2) + +/* field: RX_PDR - Receive pin open drain enable. */ +#define TMS570_LIN_PIO6_RX_PDR BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO7----------------------*/ +/* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */ +#define TMS570_LIN_PIO7_TX_PD BSP_BIT32(2) + +/* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */ +#define TMS570_LIN_PIO7_RX_PD BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO8----------------------*/ +/* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */ +#define TMS570_LIN_PIO8_TX_PSL BSP_BIT32(2) + +/* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */ +#define TMS570_LIN_PIO8_RX_PSL BSP_BIT32(1) + + +/*----------------------TMS570_LIN_COMP----------------------*/ +/* field: SDEL - 2-bit synch delimiter compare. These bits are effective in LIN mode only. */ +#define TMS570_LIN_COMP_SDEL(val) BSP_FLD32(val,8, 9) +#define TMS570_LIN_COMP_SDEL_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_LIN_COMP_SDEL_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: SBREAK - Synch break extend. These bits are effective in LIN mode only. */ +#define TMS570_LIN_COMP_SBREAK(val) BSP_FLD32(val,0, 2) +#define TMS570_LIN_COMP_SBREAK_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_LIN_COMP_SBREAK_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------------TMS570_LIN_RD0-----------------------*/ +/* field: RD0 - Receive buffer 0. Byte 0 of the response data byte. */ +#define TMS570_LIN_RD0_RD0(val) BSP_FLD32(val,24, 31) +#define TMS570_LIN_RD0_RD0_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_LIN_RD0_RD0_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: RD1 - Receive buffer 1. Byte 1 of the response data byte. */ +#define TMS570_LIN_RD0_RD1(val) BSP_FLD32(val,16, 23) +#define TMS570_LIN_RD0_RD1_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_LIN_RD0_RD1_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: RD2 - Receive buffer 2. Byte 2 of the response data byte. */ +#define TMS570_LIN_RD0_RD2(val) BSP_FLD32(val,8, 15) +#define TMS570_LIN_RD0_RD2_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_LIN_RD0_RD2_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: RD3 - Receive buffer 3. Byte 3 of the response data byte. */ +#define TMS570_LIN_RD0_RD3(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_RD0_RD3_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_RD0_RD3_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_LIN_RD1-----------------------*/ +/* field: RD4 - Receive buffer 4. Byte 4 of the response data byte. */ +#define TMS570_LIN_RD1_RD4(val) BSP_FLD32(val,24, 31) +#define TMS570_LIN_RD1_RD4_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_LIN_RD1_RD4_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: RD5 - Receive buffer 5. Byte 5 of the response data byte. */ +#define TMS570_LIN_RD1_RD5(val) BSP_FLD32(val,16, 23) +#define TMS570_LIN_RD1_RD5_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_LIN_RD1_RD5_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: RD6 - Receive buffer 6. Byte 6 of the response data byte. */ +#define TMS570_LIN_RD1_RD6(val) BSP_FLD32(val,8, 15) +#define TMS570_LIN_RD1_RD6_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_LIN_RD1_RD6_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: RD7 - Receive buffer 7. Byte 7 of the response data byte. */ +#define TMS570_LIN_RD1_RD7(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_RD1_RD7_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_RD1_RD7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_LIN_MASK----------------------*/ +/* field: RX_ID_MASK - Receive ID mask. These bits are effective in LIN mode only. */ +#define TMS570_LIN_MASK_RX_ID_MASK(val) BSP_FLD32(val,16, 23) +#define TMS570_LIN_MASK_RX_ID_MASK_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_LIN_MASK_RX_ID_MASK_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: TX_ID_MASK - Transmit ID mask. These bits are effective in LIN mode only. */ +#define TMS570_LIN_MASK_TX_ID_MASK(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_MASK_TX_ID_MASK_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_MASK_TX_ID_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_LIN_ID-----------------------*/ +/* field: RECEIVED_ID - Received identification. These bits are effective in LIN mode only. */ +#define TMS570_LIN_ID_RECEIVED_ID(val) BSP_FLD32(val,16, 23) +#define TMS570_LIN_ID_RECEIVED_ID_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_LIN_ID_RECEIVED_ID_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: ID_SLAVETASK_BYTE - ID-SlaveTask Byte. These bits are effective in LIN mode only. */ +#define TMS570_LIN_ID_ID_SLAVETASK_BYTE(val) BSP_FLD32(val,8, 15) +#define TMS570_LIN_ID_ID_SLAVETASK_BYTE_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_LIN_ID_ID_SLAVETASK_BYTE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: ID_BYTE - ID byte. This field is effective in LIN mode only. This byte is the LIN mode message ID. */ +#define TMS570_LIN_ID_ID_BYTE(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_ID_ID_BYTE_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_ID_ID_BYTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_LIN_TD0-----------------------*/ +/* field: TD0 - 8-Bit transmit buffer 0. */ +#define TMS570_LIN_TD0_TD0(val) BSP_FLD32(val,24, 31) +#define TMS570_LIN_TD0_TD0_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_LIN_TD0_TD0_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: TD1 - 8-Bit transmit buffer 1. */ +#define TMS570_LIN_TD0_TD1(val) BSP_FLD32(val,16, 23) +#define TMS570_LIN_TD0_TD1_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_LIN_TD0_TD1_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: TD2 - 8-Bit transmit buffer 2. */ +#define TMS570_LIN_TD0_TD2(val) BSP_FLD32(val,8, 15) +#define TMS570_LIN_TD0_TD2_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_LIN_TD0_TD2_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: TD3 - 8-Bit transmit buffer 3. */ +#define TMS570_LIN_TD0_TD3(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_TD0_TD3_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_TD0_TD3_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_LIN_TD1-----------------------*/ +/* field: TD4 - 8-Bit transmit buffer 4. */ +#define TMS570_LIN_TD1_TD4(val) BSP_FLD32(val,24, 31) +#define TMS570_LIN_TD1_TD4_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_LIN_TD1_TD4_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: TD5 - 8-Bit transmit buffer 5. */ +#define TMS570_LIN_TD1_TD5(val) BSP_FLD32(val,16, 23) +#define TMS570_LIN_TD1_TD5_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_LIN_TD1_TD5_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: TD6 - 8-Bit transmit buffer 6. */ +#define TMS570_LIN_TD1_TD6(val) BSP_FLD32(val,8, 15) +#define TMS570_LIN_TD1_TD6_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_LIN_TD1_TD6_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: TD7 - 8-Bit transmit buffer 7. */ +#define TMS570_LIN_TD1_TD7(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_TD1_TD7_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_TD1_TD7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_LIN_MBRSR----------------------*/ +/* field: MBR - Maximum baud rate prescaler. This bit is effective in LIN mode only. */ +#define TMS570_LIN_MBRSR_MBR(val) BSP_FLD32(val,0, 12) +#define TMS570_LIN_MBRSR_MBR_GET(reg) BSP_FLD32GET(reg,0, 12) +#define TMS570_LIN_MBRSR_MBR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12) + + +/*--------------------TMS570_LIN_IODFTCTRL--------------------*/ +/* field: FEN - Frame error enable. This bit is used to create a frame error. */ +#define TMS570_LIN_IODFTCTRL_FEN BSP_BIT32(26) + +/* field: PEN - Parity error enable. This bit is used to create a parity error. */ +#define TMS570_LIN_IODFTCTRL_PEN BSP_BIT32(25) + +/* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */ +#define TMS570_LIN_IODFTCTRL_BRKD_TENA BSP_BIT32(24) + +/* field: PIN_SAMPLE_MASK - Pin sample mask. */ +#define TMS570_LIN_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20) +#define TMS570_LIN_IODFTCTRL_PIN_SAMPLE_MASK_GET(reg) BSP_FLD32GET(reg,19, 20) +#define TMS570_LIN_IODFTCTRL_PIN_SAMPLE_MASK_SET(reg,val) BSP_FLD32SET(reg, val,19, 20) + +/* field: TX_SHIFT - Transmit shift. */ +#define TMS570_LIN_IODFTCTRL_TX_SHIFT(val) BSP_FLD32(val,16, 18) +#define TMS570_LIN_IODFTCTRL_TX_SHIFT_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_LIN_IODFTCTRL_TX_SHIFT_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: IODFTENA - IODFT enable key. Write access permitted in Privilege mode only. */ +#define TMS570_LIN_IODFTCTRL_IODFTENA(val) BSP_FLD32(val,8, 11) +#define TMS570_LIN_IODFTCTRL_IODFTENA_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_LIN_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */ +#define TMS570_LIN_IODFTCTRL_LPBENA BSP_BIT32(1) + +/* field: RXPENA - Module analog loopback through receive pin enable. */ +#define TMS570_LIN_IODFTCTRL_RXPENA BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_LIN */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h new file mode 100644 index 0000000000..704a0bc8a4 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h @@ -0,0 +1,230 @@ +/* The header file is generated by make_header.py from MDIO.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_MDIO +#define LIBBSP_ARM_TMS570_MDIO + +#include + +typedef struct{ + uint32_t REVID; /*MDIO Revision ID Register*/ + uint32_t CONTROL; /*MDIO Control Register*/ + uint32_t ALIVE; /*PHY Alive Status register*/ + uint32_t LINK; /*PHY Link Status Register*/ + uint32_t LINKINTRAW; /*MDIO Link Status Change Interrupt (Unmasked) Register*/ + uint32_t LINKINTMASKED; /*MDIO Link Status Change Interrupt (Masked) Register*/ + uint8_t reserved1 [8]; + uint32_t USERINTRAW; /*MDIO User Command Complete Interrupt (Unmasked) Register*/ + uint32_t USERINTMASKED; /*MDIO User Command Complete Interrupt (Masked) Register*/ + uint32_t USERINTMASKSET; /*MDIO User Command Complete Interrupt Mask Set Register*/ + uint32_t USERINTMASKCLEAR; /*MDIO User Command Complete Interrupt Mask Clear Register*/ + uint8_t reserved2 [80]; + uint32_t USERACCESS0; /*MDIO User Access Register 0*/ + uint32_t USERPHYSEL0; /*MDIO User PHY Select Register 0*/ + uint32_t USERACCESS1; /*MDIO User Access Register 1*/ + uint32_t USERPHYSEL1; /*MDIO User PHY Select Register 1*/ +} tms570_mdio_t; + + +/*---------------------TMS570_MDIO_REVID---------------------*/ +/* field: REV - Identifies the MDIO Module revision. */ +/* Whole 32 bits */ + +/*--------------------TMS570_MDIO_CONTROL--------------------*/ +/* field: IDLE - State machine IDLE status bit. */ +#define TMS570_MDIO_CONTROL_IDLE BSP_BIT32(31) + +/* field: ENABLE - State machine enable control bit. */ +#define TMS570_MDIO_CONTROL_ENABLE BSP_BIT32(30) + +/* field: HIGHEST_USER_CHANNEL - Highest user channel that is available in the module. It is currently set to 1. */ +#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL(val) BSP_FLD32(val,24, 28) +#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: PREAMBLE - Preamble disable */ +#define TMS570_MDIO_CONTROL_PREAMBLE BSP_BIT32(20) + +/* field: FAULT - Fault indicator. */ +#define TMS570_MDIO_CONTROL_FAULT BSP_BIT32(19) + +/* field: FAULTENB - Fault detect enable. */ +#define TMS570_MDIO_CONTROL_FAULTENB BSP_BIT32(18) + +/* field: CLKDIV - Clock Divider bits. */ +#define TMS570_MDIO_CONTROL_CLKDIV(val) BSP_FLD32(val,0, 15) +#define TMS570_MDIO_CONTROL_CLKDIV_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_MDIO_CONTROL_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_MDIO_ALIVE---------------------*/ +/* field: ALIVE - MDIO Alive bits. */ +/* Whole 32 bits */ + +/*----------------------TMS570_MDIO_LINK----------------------*/ +/* field: LINK - MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. */ +/* Whole 32 bits */ + +/*-------------------TMS570_MDIO_LINKINTRAW-------------------*/ +/* field: USERPHY1 - MDIO Link change event, raw value. */ +#define TMS570_MDIO_LINKINTRAW_USERPHY1 BSP_BIT32(1) + +/* field: USERPHY0 - MDIO Link change event, raw value. */ +#define TMS570_MDIO_LINKINTRAW_USERPHY0 BSP_BIT32(0) + + +/*-----------------TMS570_MDIO_LINKINTMASKED-----------------*/ +/* field: USERPHY1 - MDIO Link change interrupt, masked value. */ +#define TMS570_MDIO_LINKINTMASKED_USERPHY1 BSP_BIT32(1) + +/* field: USERPHY0 - MDIO Link change interrupt, masked value. */ +#define TMS570_MDIO_LINKINTMASKED_USERPHY0 BSP_BIT32(0) + + +/*-------------------TMS570_MDIO_USERINTRAW-------------------*/ +/* field: USERACCESS1 - MDIO User command complete event bit. */ +#define TMS570_MDIO_USERINTRAW_USERACCESS1 BSP_BIT32(1) + +/* field: USERACCESS0 - MDIO User command complete event bit. */ +#define TMS570_MDIO_USERINTRAW_USERACCESS0 BSP_BIT32(0) + + +/*-----------------TMS570_MDIO_USERINTMASKED-----------------*/ +/* field: USERACCESS1 - Masked value of MDIO User command complete interrupt. */ +#define TMS570_MDIO_USERINTMASKED_USERACCESS1 BSP_BIT32(1) + +/* field: USERACCESS0 - Masked value of MDIO User command complete interrupt. */ +#define TMS570_MDIO_USERINTMASKED_USERACCESS0 BSP_BIT32(0) + + +/*-----------------TMS570_MDIO_USERINTMASKSET-----------------*/ +/* field: USERACCESS1 - MDIO user interrupt mask set for USERINTMASKED[1]. */ +#define TMS570_MDIO_USERINTMASKSET_USERACCESS1 BSP_BIT32(1) + +/* field: USERACCESS0 - MDIO user interrupt mask set for USERINTMASKED[0]. */ +#define TMS570_MDIO_USERINTMASKSET_USERACCESS0 BSP_BIT32(0) + + +/*----------------TMS570_MDIO_USERINTMASKCLEAR----------------*/ +/* field: USERACCESS1 - MDIO user command complete interrupt mask clear for USERINTMASKED[1]. */ +#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS1 BSP_BIT32(1) + +/* field: USERACCESS0 - MDIO user command complete interrupt mask clear for USERINTMASKED[0]. */ +#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS0 BSP_BIT32(0) + + +/*------------------TMS570_MDIO_USERACCESS0------------------*/ +/* field: GO - Go bit. */ +#define TMS570_MDIO_USERACCESS0_GO BSP_BIT32(31) + +/* field: WRITE - Write enable bit. */ +#define TMS570_MDIO_USERACCESS0_WRITE BSP_BIT32(30) + +/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */ +#define TMS570_MDIO_USERACCESS0_ACK BSP_BIT32(29) + +/* field: REGADR - Register address bits. */ +#define TMS570_MDIO_USERACCESS0_REGADR(val) BSP_FLD32(val,21, 25) +#define TMS570_MDIO_USERACCESS0_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25) +#define TMS570_MDIO_USERACCESS0_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25) + +/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */ +#define TMS570_MDIO_USERACCESS0_PHYADR(val) BSP_FLD32(val,16, 20) +#define TMS570_MDIO_USERACCESS0_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20) +#define TMS570_MDIO_USERACCESS0_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20) + +/* field: DATA - User data bits. */ +#define TMS570_MDIO_USERACCESS0_DATA(val) BSP_FLD32(val,0, 15) +#define TMS570_MDIO_USERACCESS0_DATA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_MDIO_USERACCESS0_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_MDIO_USERPHYSEL0------------------*/ +/* field: LINKSEL - Link status determination select bit. */ +#define TMS570_MDIO_USERPHYSEL0_LINKSEL BSP_BIT32(7) + +/* field: LINKINTENB - Link change interrupt enable. */ +#define TMS570_MDIO_USERPHYSEL0_LINKINTENB BSP_BIT32(6) + +/* field: PHYADRMON - PHY address whose link status is to be monitored. */ +#define TMS570_MDIO_USERPHYSEL0_PHYADRMON(val) BSP_FLD32(val,0, 4) +#define TMS570_MDIO_USERPHYSEL0_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_MDIO_USERPHYSEL0_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*------------------TMS570_MDIO_USERACCESS1------------------*/ +/* field: GO - Go bit. */ +#define TMS570_MDIO_USERACCESS1_GO BSP_BIT32(31) + +/* field: WRITE - Write enable bit. */ +#define TMS570_MDIO_USERACCESS1_WRITE BSP_BIT32(30) + +/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */ +#define TMS570_MDIO_USERACCESS1_ACK BSP_BIT32(29) + +/* field: REGADR - Register address bits. */ +#define TMS570_MDIO_USERACCESS1_REGADR(val) BSP_FLD32(val,21, 25) +#define TMS570_MDIO_USERACCESS1_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25) +#define TMS570_MDIO_USERACCESS1_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25) + +/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */ +#define TMS570_MDIO_USERACCESS1_PHYADR(val) BSP_FLD32(val,16, 20) +#define TMS570_MDIO_USERACCESS1_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20) +#define TMS570_MDIO_USERACCESS1_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20) + +/* field: DATA - User data bits. */ +#define TMS570_MDIO_USERACCESS1_DATA(val) BSP_FLD32(val,0, 15) +#define TMS570_MDIO_USERACCESS1_DATA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_MDIO_USERACCESS1_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_MDIO_USERPHYSEL1------------------*/ +/* field: LINKSEL - Link status determination select bit. */ +#define TMS570_MDIO_USERPHYSEL1_LINKSEL BSP_BIT32(7) + +/* field: LINKINTENB - Link change interrupt enable. */ +#define TMS570_MDIO_USERPHYSEL1_LINKINTENB BSP_BIT32(6) + +/* field: PHYADRMON - PHY address whose link status is to be monitored. */ +#define TMS570_MDIO_USERPHYSEL1_PHYADRMON(val) BSP_FLD32(val,0, 4) +#define TMS570_MDIO_USERPHYSEL1_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_MDIO_USERPHYSEL1_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + + +#endif /* LIBBSP_ARM_TMS570_MDIO */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h new file mode 100644 index 0000000000..06b8bbeb0a --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h @@ -0,0 +1,332 @@ +/* The header file is generated by make_header.py from N2HET.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_NHET +#define LIBBSP_ARM_TMS570_NHET + +#include + +typedef struct{ + uint32_t GCR; /*Global Configuration Register*/ + uint32_t PFR; /*Prescale Factor Register*/ + uint32_t ADDR; /*NHET Current Address Register*/ + uint32_t OFF1; /*Offset Index Priority Level 1 Register*/ + uint32_t OFF2; /*Offset Index Priority Level 2 Register*/ + uint32_t INTENAS; /*Interrupt Enable Set Register*/ + uint32_t INTENAC; /*Interrupt Enable Clear Register*/ + uint32_t EXC1; /*Exception Control Register 1*/ + uint32_t EXC2; /*Exception Control Register 2*/ + uint32_t PRY; /*Interrupt Priority Register*/ + uint32_t FLG; /*Interrupt Flag Register*/ + uint32_t AND; /*AND Share Control Register*/ + uint8_t reserved1 [4]; + uint32_t HRSH; /*HR Share Control Register*/ + uint32_t XOR; /*HR XOR-Share Control Register*/ + uint32_t REQENS; /*Request Enable Set Register*/ + uint32_t REQENC; /*Request Enable Clear Register*/ + uint32_t REQDS; /*Request Destination Select Register*/ + uint8_t reserved2 [4]; + uint32_t DIR; /*NHET Direction Register*/ + uint32_t DIN; /*NHET Data Input Register*/ + uint32_t DOUT; /*NHET Data Output Register*/ + uint32_t DSET; /*NHET Data Set Register*/ + uint32_t DCLR; /*NHET Data Clear Register*/ + uint32_t PDR; /*NHET Open Drain Register*/ + uint32_t PULDIS; /*NHET Pull Disable Register*/ + uint32_t PSL; /*NHET Pull Select Register*/ + uint8_t reserved3 [8]; + uint32_t PCR; /*Parity Control Register*/ + uint32_t PAR; /*Parity Address Register*/ + uint32_t PPR; /*Parity Pin Register*/ + uint32_t SFPRLD; /*Suppression Filter Preload Register*/ + uint32_t SFENA; /*Suppression Filter Enable Register*/ + uint8_t reserved4 [4]; + uint32_t LBPSEL; /*Loop Back Pair Select Register*/ + uint32_t LBPDIR; /*Loop Back Pair Direction Register*/ + uint32_t PINDIS; /*NHET Pin Disable Register*/ +} tms570_nhet_t; + + +/*----------------------TMS570_NHET_GCR----------------------*/ +/* field: HET_PIN_ENA - Enables the output buffers of the pin structures depending on the value of nDIS and DIR. */ +#define TMS570_NHET_GCR_HET_PIN_ENA BSP_BIT32(24) + +/* field: MP - Master Priority */ +#define TMS570_NHET_GCR_MP(val) BSP_FLD32(val,21, 22) +#define TMS570_NHET_GCR_MP_GET(reg) BSP_FLD32GET(reg,21, 22) +#define TMS570_NHET_GCR_MP_SET(reg,val) BSP_FLD32SET(reg, val,21, 22) + +/* field: PPF - Protect Program Fields */ +#define TMS570_NHET_GCR_PPF BSP_BIT32(18) + +/* field: IS - Ignore Suspend */ +#define TMS570_NHET_GCR_IS BSP_BIT32(17) + +/* field: CMS - Clk_master/slave */ +#define TMS570_NHET_GCR_CMS BSP_BIT32(16) + + +/*----------------------TMS570_NHET_PFR----------------------*/ +/* field: LRPFC - oop Resolution Pre-scale Factor Code */ +#define TMS570_NHET_PFR_LRPFC(val) BSP_FLD32(val,8, 10) +#define TMS570_NHET_PFR_LRPFC_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_NHET_PFR_LRPFC_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: HRPFC - High Resolution Pre-scale Factor Code */ +#define TMS570_NHET_PFR_HRPFC(val) BSP_FLD32(val,0, 5) +#define TMS570_NHET_PFR_HRPFC_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_NHET_PFR_HRPFC_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_NHET_ADDR----------------------*/ +/* field: HETADDR - N2HET Current Address */ +#define TMS570_NHET_ADDR_HETADDR(val) BSP_FLD32(val,0, 8) +#define TMS570_NHET_ADDR_HETADDR_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_NHET_ADDR_HETADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*----------------------TMS570_NHET_OFF1----------------------*/ +/* field: OFFSET1 - HETOFF1[5:0] indexes the currently pending high-priority interrupt. */ +#define TMS570_NHET_OFF1_OFFSET1(val) BSP_FLD32(val,0, 5) +#define TMS570_NHET_OFF1_OFFSET1_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_NHET_OFF1_OFFSET1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_NHET_OFF2----------------------*/ +/* field: OFFSET2 - HETOFF2[5:0] indexes the currently pending low-priority interrupt. */ +#define TMS570_NHET_OFF2_OFFSET2(val) BSP_FLD32(val,0, 5) +#define TMS570_NHET_OFF2_OFFSET2_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_NHET_OFF2_OFFSET2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*--------------------TMS570_NHET_INTENAS--------------------*/ +/* field: HETINTENAS - Interrupt Enable Set bits. HETINTENAS is readable and writable in any operation mode. */ +/* Whole 32 bits */ + +/*--------------------TMS570_NHET_INTENAC--------------------*/ +/* field: HETINTENAC - Interrupt Enable Clear bits. HETINTENAC is readable and writable in any operation mode. */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_EXC1----------------------*/ +/* field: APCNT_OVRFL_ENA - APCNT Overflow Enable */ +#define TMS570_NHET_EXC1_APCNT_OVRFL_ENA BSP_BIT32(24) + +/* field: APCNT_UNRFL_ENA - APCNT Underflow Enable */ +#define TMS570_NHET_EXC1_APCNT_UNRFL_ENA BSP_BIT32(16) + +/* field: PRGM_OVRFL_ENA - Program Overflow Enable */ +#define TMS570_NHET_EXC1_PRGM_OVRFL_ENA BSP_BIT32(8) + +/* field: APCNT_OVRFL_PRY - APCNT Overflow Exception Interrupt Priority */ +#define TMS570_NHET_EXC1_APCNT_OVRFL_PRY BSP_BIT32(2) + +/* field: APCNT_UNRFL_PRY - APCNT Underflow Exception Interrupt Priority */ +#define TMS570_NHET_EXC1_APCNT_UNRFL_PRY BSP_BIT32(1) + +/* field: PRGM_OVRFL_PRY - ProgramOverflow Exception Interrupt Priority */ +#define TMS570_NHET_EXC1_PRGM_OVRFL_PRY BSP_BIT32(0) + + +/*----------------------TMS570_NHET_EXC2----------------------*/ +/* field: DEBUG_STATUS_FLAG - Debug Status Flag. */ +#define TMS570_NHET_EXC2_DEBUG_STATUS_FLAG BSP_BIT32(8) + +/* field: APCNT_OVRFL_FLAG - APCNT Overflow Flag */ +#define TMS570_NHET_EXC2_APCNT_OVRFL_FLAG BSP_BIT32(2) + +/* field: APCNT_UNDFL_FLAG - APCNT Underflow Flag */ +#define TMS570_NHET_EXC2_APCNT_UNDFL_FLAG BSP_BIT32(1) + +/* field: PRGM_OVERFL_FLAG - Program Overflow Flag */ +#define TMS570_NHET_EXC2_PRGM_OVERFL_FLAG BSP_BIT32(0) + + +/*----------------------TMS570_NHET_PRY----------------------*/ +/* field: HETPRY - HET Interrupt Priority Level bits */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_FLG----------------------*/ +/* field: HETFLAG - Interrupt Flag Register Bits */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_AND----------------------*/ +/* field: AND_SHARE - AND Share Enable */ +#define TMS570_NHET_AND_AND_SHARE(val) BSP_FLD32(val,0, 15) +#define TMS570_NHET_AND_AND_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_NHET_AND_AND_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_NHET_HRSH----------------------*/ +/* field: HR_SHARE - HR Share Bits */ +#define TMS570_NHET_HRSH_HR_SHARE(val) BSP_FLD32(val,0, 15) +#define TMS570_NHET_HRSH_HR_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_NHET_HRSH_HR_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_NHET_XOR----------------------*/ +/* field: XOR_SHARE - XOR Share Enable */ +#define TMS570_NHET_XOR_XOR_SHARE(val) BSP_FLD32(val,0, 15) +#define TMS570_NHET_XOR_XOR_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_NHET_XOR_XOR_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_NHET_REQENS---------------------*/ +/* field: REQ_ENA_n - Request Enable Bits */ +#define TMS570_NHET_REQENS_REQ_ENA_n(val) BSP_FLD32(val,0, 7) +#define TMS570_NHET_REQENS_REQ_ENA_n_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_NHET_REQENS_REQ_ENA_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_NHET_REQENC---------------------*/ +/* field: REQ_DIS_n - Request Disable Bits */ +#define TMS570_NHET_REQENC_REQ_DIS_n(val) BSP_FLD32(val,0, 7) +#define TMS570_NHET_REQENC_REQ_DIS_n_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_NHET_REQENC_REQ_DIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_NHET_REQDS---------------------*/ +/* field: TDBS_n - HTU, DMA or Both Select Bits */ +#define TMS570_NHET_REQDS_TDBS_n(val) BSP_FLD32(val,16, 23) +#define TMS570_NHET_REQDS_TDBS_n_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_NHET_REQDS_TDBS_n_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: TDS_n - HTU or DMA Select Bits */ +#define TMS570_NHET_REQDS_TDS_n(val) BSP_FLD32(val,0, 7) +#define TMS570_NHET_REQDS_TDS_n_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_NHET_REQDS_TDS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_NHET_DIR----------------------*/ +/* field: HETDIR_n - Data direction of NHET pins */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_DIN----------------------*/ +/* field: HETDIN_n - Data input. This bit displays the logic state of the pin. */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_DOUT----------------------*/ +/* field: HETDOUT_n - Data out write. Writes to this bit will only take effect when the pin is configured as an output. */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_DSET----------------------*/ +/* field: HETDSET_n - This register allows bits of HETDOUT to be set while avoiding the pitfalls of a readmodify- write */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_DCLR----------------------*/ +/* field: HETDCLR_n - This register allows bits of HETDOUT to be cleared while avoiding the pitfalls of a read-modifywrite */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_PDR----------------------*/ +/* field: HETPDR_n - Open drain control for HET[n] pins */ +/* Whole 32 bits */ + +/*---------------------TMS570_NHET_PULDIS---------------------*/ +/* field: HETPULDIS_n - Pull disable for N2HET pins */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_PSL----------------------*/ +/* field: HETPSL_n - Pull select for NHET pins */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_PCR----------------------*/ +/* field: TEST - Test Bit. */ +#define TMS570_NHET_PCR_TEST BSP_BIT32(8) + +/* field: PARITY_ENA - Enable/disable parity checking. */ +#define TMS570_NHET_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3) +#define TMS570_NHET_PCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_NHET_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*----------------------TMS570_NHET_PAR----------------------*/ +/* field: PAOFF - Parity Error Address Offset. */ +#define TMS570_NHET_PAR_PAOFF(val) BSP_FLD32(val,2, 12) +#define TMS570_NHET_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,2, 12) +#define TMS570_NHET_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,2, 12) + + +/*----------------------TMS570_NHET_PPR----------------------*/ +/* field: HETPPR_n - NHET Parity Pin Select Bits - Allows HET[n] pins to be configured to drive to a known state when */ +/* Whole 32 bits */ + +/*---------------------TMS570_NHET_SFPRLD---------------------*/ +/* field: CCDIV - Counter Clock Divider */ +#define TMS570_NHET_SFPRLD_CCDIV(val) BSP_FLD32(val,16, 17) +#define TMS570_NHET_SFPRLD_CCDIV_GET(reg) BSP_FLD32GET(reg,16, 17) +#define TMS570_NHET_SFPRLD_CCDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 17) + +/* field: CPRLD - Counter Preload Value */ +#define TMS570_NHET_SFPRLD_CPRLD(val) BSP_FLD32(val,0, 9) +#define TMS570_NHET_SFPRLD_CPRLD_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_NHET_SFPRLD_CPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*---------------------TMS570_NHET_SFENA---------------------*/ +/* field: HETSFENA_n - Suppression Filter Enable Bits */ +/* Whole 32 bits */ + +/*---------------------TMS570_NHET_LBPSEL---------------------*/ +/* field: LBPTYPE - Loop Back Pair Type Select Bits */ +#define TMS570_NHET_LBPSEL_LBPTYPE(val) BSP_FLD32(val,16, 31) +#define TMS570_NHET_LBPSEL_LBPTYPE_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_NHET_LBPSEL_LBPTYPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: LBPSEL - Loop Back Pair Select Bits */ +#define TMS570_NHET_LBPSEL_LBPSEL(val) BSP_FLD32(val,0, 15) +#define TMS570_NHET_LBPSEL_LBPSEL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_NHET_LBPSEL_LBPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_NHET_LBPDIR---------------------*/ +/* field: LBPTSTENA - Loopback Test Enable Key */ +#define TMS570_NHET_LBPDIR_LBPTSTENA(val) BSP_FLD32(val,16, 19) +#define TMS570_NHET_LBPDIR_LBPTSTENA_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_NHET_LBPDIR_LBPTSTENA_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: LBPDIR - Loop Back Pair Direction Bits */ +#define TMS570_NHET_LBPDIR_LBPDIR(val) BSP_FLD32(val,0, 15) +#define TMS570_NHET_LBPDIR_LBPDIR_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_NHET_LBPDIR_LBPDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_NHET_PINDIS---------------------*/ +/* field: HETPINDIS_n - N2HET Pin Disable Bits */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_NHET */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h new file mode 100644 index 0000000000..2c5ed29760 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h @@ -0,0 +1,195 @@ +/* The header file is generated by make_header.py from PBIST.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_PBIST +#define LIBBSP_ARM_TMS570_PBIST + +#include + +typedef struct{ + uint32_t DNW[88]; /*Reserved DO NOT WRITE*/ + uint32_t RAMT; /*RAM Configuration Register*/ + uint32_t DLR; /*Datalogger Register*/ + uint8_t reserved1 [24]; + uint32_t PACT; /*PBIST Activate/ROM Clock Enable Register*/ + uint32_t PBISTID; /*PBIST ID Register*/ + uint32_t OVER; /*Override Register*/ + uint8_t reserved2 [4]; + uint32_t FSRF0; /*Fail Status Fail Register 0*/ + uint8_t reserved3 [4]; + uint32_t FSRC0; /*Fail Status Count Register 0*/ + uint32_t FSRC1; /*Fail Status Count Register 1*/ + uint32_t FSRA0; /*Fail Status Address 0 Register*/ + uint32_t FSRA1; /*Fail Status Address 1 Register*/ + uint32_t FSRDL0; /*Fail Status Data Register 0*/ + uint8_t reserved4 [4]; + uint32_t FSRDL1; /*Fail Status Data Register 1*/ + uint8_t reserved5 [12]; + uint32_t ROM; /*ROM Mask Register*/ + uint32_t ALGO; /*ROM Algorithm Mask Register*/ + uint32_t RINFOL; /*RAM Info Mask Lower Register*/ + uint32_t RINFOUL; /*RAM Info Mask Lower Register*/ +} tms570_pbist_t; + + +/*----------------------TMS570_PBIST_DNW----------------------*/ +/* field: Reserved - Do not write */ +/* Whole 32 bits */ + +/*---------------------TMS570_PBIST_RAMT---------------------*/ +/* field: RGS - Ram Group Select. Refer Table 2-5 for information on the RGS value for each memory. */ +#define TMS570_PBIST_RAMT_RGS(val) BSP_FLD32(val,24, 31) +#define TMS570_PBIST_RAMT_RGS_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_PBIST_RAMT_RGS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: RDS - Return Data Select. Refer Table 2-5 for information on the RDS values for each memory. */ +#define TMS570_PBIST_RAMT_RDS(val) BSP_FLD32(val,16, 23) +#define TMS570_PBIST_RAMT_RDS_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_PBIST_RAMT_RDS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: DWR - Data Width Register */ +#define TMS570_PBIST_RAMT_DWR(val) BSP_FLD32(val,8, 15) +#define TMS570_PBIST_RAMT_DWR_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_PBIST_RAMT_DWR_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: SMS - Sense Margin Select Register */ +#define TMS570_PBIST_RAMT_SMS(val) BSP_FLD32(val,6, 7) +#define TMS570_PBIST_RAMT_SMS_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_PBIST_RAMT_SMS_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: PLS - Pipeline Latency Select */ +#define TMS570_PBIST_RAMT_PLS(val) BSP_FLD32(val,2, 5) +#define TMS570_PBIST_RAMT_PLS_GET(reg) BSP_FLD32GET(reg,2, 5) +#define TMS570_PBIST_RAMT_PLS_SET(reg,val) BSP_FLD32SET(reg, val,2, 5) + +/* field: RLS - RAM Latency Select */ +#define TMS570_PBIST_RAMT_RLS(val) BSP_FLD32(val,0, 1) +#define TMS570_PBIST_RAMT_RLS_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PBIST_RAMT_RLS_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*----------------------TMS570_PBIST_DLR----------------------*/ +/* field: DLR4 - Config access: setting this bit allows the host processor to configure the PBIST controller registers */ +#define TMS570_PBIST_DLR_DLR4 BSP_BIT32(4) + +/* field: DLR2 - ROM-based testing: setting this bit enables the PBIST controller to execute test algorithms that are */ +#define TMS570_PBIST_DLR_DLR2 BSP_BIT32(2) + + +/*---------------------TMS570_PBIST_PACT---------------------*/ +/* field: PACT1 - PBIST Activate */ +#define TMS570_PBIST_PACT_PACT1 BSP_BIT32(1) + +/* field: PACT0 - ROM Clock Enable Register */ +#define TMS570_PBIST_PACT_PACT0 BSP_BIT32(0) + + +/*--------------------TMS570_PBIST_PBISTID--------------------*/ +/* field: PBIST_ID - This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. */ +#define TMS570_PBIST_PBISTID_PBIST_ID(val) BSP_FLD32(val,0, 7) +#define TMS570_PBIST_PBISTID_PBIST_ID_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_PBIST_PBISTID_PBIST_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_PBIST_OVER---------------------*/ +/* field: OVER0 - RINFO Override Bit */ +#define TMS570_PBIST_OVER_OVER0 BSP_BIT32(0) + + +/*---------------------TMS570_PBIST_FSRF0---------------------*/ +/* field: FSRF0 - Fail Status 0. */ +#define TMS570_PBIST_FSRF0_FSRF0 BSP_BIT32(0) + + +/*---------------------TMS570_PBIST_FSRC0---------------------*/ +/* field: FSRC0 - Fail Status Count 0. Indicates the number of failures on port 0. */ +#define TMS570_PBIST_FSRC0_FSRC0(val) BSP_FLD32(val,0, 7) +#define TMS570_PBIST_FSRC0_FSRC0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_PBIST_FSRC0_FSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_PBIST_FSRC1---------------------*/ +/* field: FSRC1 - Fail Status Count 1. Indicates the number of failures on port 1. */ +#define TMS570_PBIST_FSRC1_FSRC1(val) BSP_FLD32(val,0, 7) +#define TMS570_PBIST_FSRC1_FSRC1_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_PBIST_FSRC1_FSRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_PBIST_FSRA0---------------------*/ +/* field: FSRA0 - Fail Status Address 0. Contains the address of the first failure. */ +#define TMS570_PBIST_FSRA0_FSRA0(val) BSP_FLD32(val,0, 15) +#define TMS570_PBIST_FSRA0_FSRA0_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_PBIST_FSRA0_FSRA0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_PBIST_FSRA1---------------------*/ +/* field: FSRA1 - Fail Status Address 1. Contains the address of the first failure. */ +#define TMS570_PBIST_FSRA1_FSRA1(val) BSP_FLD32(val,0, 15) +#define TMS570_PBIST_FSRA1_FSRA1_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_PBIST_FSRA1_FSRA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_PBIST_FSRDL0--------------------*/ +/* field: FSRDL1 - Failure data on port 1 */ +/* Whole 32 bits */ + +/*--------------------TMS570_PBIST_FSRDL1--------------------*/ +/* field: FSRDL1 - Failure data on port 1 */ +/* Whole 32 bits */ + +/*----------------------TMS570_PBIST_ROM----------------------*/ +/* field: ROM - ROM Mask */ +#define TMS570_PBIST_ROM_ROM(val) BSP_FLD32(val,0, 1) +#define TMS570_PBIST_ROM_ROM_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PBIST_ROM_ROM_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_PBIST_ALGO---------------------*/ +/* field: ROM_ALG_MASK - Each bit corresponds to a specific algorithm */ +/* Whole 32 bits */ + +/*--------------------TMS570_PBIST_RINFOL--------------------*/ +/* field: RAM_ALG_MASK_LOW - Each bit corresponds to a specific algorithm */ +/* Whole 32 bits */ + +/*--------------------TMS570_PBIST_RINFOUL--------------------*/ +/* field: RAM_ALG_MASK_UP - Each bit corresponds to a specific algorithm */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_PBIST */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h new file mode 100644 index 0000000000..4d5613aa9f --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h @@ -0,0 +1,120 @@ +/* The header file is generated by make_header.py from PCR.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_PCR +#define LIBBSP_ARM_TMS570_PCR + +#include + +typedef struct{ + uint32_t PMPROTSET0; /*Peripheral Memory Protection Set Register 0*/ + uint32_t PMPROTSET1; /*Peripheral Memory Protection Set Register 1*/ + uint8_t reserved1 [8]; + uint32_t PMPROTCLR0; /*Peripheral Memory Protection Clear Register 0*/ + uint32_t PMPROTCLR1; /*Peripheral Memory Protection Clear Register 1*/ + uint8_t reserved2 [8]; + uint32_t PPROTSET0; /*Peripheral Protection Set Register 0*/ + uint32_t PPROTSET1; /*Peripheral Protection Set Register 1*/ + uint32_t PPROTSET2; /*Peripheral Protection Set Register 2*/ + uint32_t PPROTSET3; /*Peripheral Protection Set Register 3*/ + uint8_t reserved3 [16]; + uint32_t PPROTCLR0; /*Peripheral Protection Clear Register 0*/ + uint32_t PPROTCLR1; /*Peripheral Protection Clear Register 1*/ + uint32_t PPROTCLR2; /*Peripheral Protection Clear Register 2*/ + uint32_t PPROTCLR3; /*Peripheral Protection Clear Register 3*/ + uint8_t reserved4 [16]; + uint32_t PCSPWRDWNSET0; /*Peripheral Memory Power-Down Set Register 0*/ + uint32_t PCSPWRDWNSET1; /*Peripheral Memory Power-Down Set Register 1*/ + uint8_t reserved5 [8]; + uint32_t PCSPWRDWNCLR0; /*Peripheral Memory Power-Down Clear Register 0*/ + uint32_t PCSPWRDWNCLR1; /*Peripheral Memory Power-Down Clear Register 1*/ + uint8_t reserved6 [8]; + uint32_t PSPWRDWNSET0; /*Peripheral Power-Down Set Register 0*/ + uint32_t PSPWRDWNSET1; /*Peripheral Power-Down Set Register 1*/ + uint32_t PSPWRDWNSET2; /*Peripheral Power-Down Set Register 2*/ + uint32_t PSPWRDWNSET3; /*Peripheral Power-Down Set Register 3*/ + uint8_t reserved7 [16]; + uint32_t PSPWRDWNCLR0; /*Peripheral Power-Down Clear Register 0*/ + uint32_t PSPWRDWNCLR1; /*Peripheral Power-Down Clear Register 1*/ + uint32_t PSPWRDWNCLR2; /*Peripheral Power-Down Clear Register 2*/ + uint32_t PSPWRDWNCLR3; /*Peripheral Power-Down Clear Register 3*/ +} tms570_pcr_t; + + +/*-------------------TMS570_PCR_PMPROTSET0-------------------*/ +/* field: PCSPROTSET - Peripheral memory frame protection set. */ +/* Whole 32 bits */ + +/*-------------------TMS570_PCR_PMPROTSET1-------------------*/ +/* field: PCSPROTSET - Peripheral memory frame protection set. */ +/* Whole 32 bits */ + +/*-------------------TMS570_PCR_PMPROTCLR0-------------------*/ +/* field: PCSPROTCLR - Peripheral memory frame protection clear. */ +/* Whole 32 bits */ + +/*-------------------TMS570_PCR_PMPROTCLR1-------------------*/ +/* field: PCSPROTCLR - Peripheral memory frame protection clear. */ +/* Whole 32 bits */ + +/*--------------------TMS570_PCR_PPROTSETx--------------------*/ +/* field: PROTSET - Peripheral select quadrant protection set. */ +/* Whole 32 bits */ + +/*--------------------TMS570_PCR_PPROTCLRx--------------------*/ +/* field: PROTCLR - Peripheral select quadrant protection clear. */ +/* Whole 32 bits */ + +/*------------------TMS570_PCR_PCSPWRDWNSETx------------------*/ +/* field: PWRDNSET - Peripheral memory clock power-down set. */ +/* Whole 32 bits */ + +/*------------------TMS570_PCR_PCSPWRDWNCLRx------------------*/ +/* field: PWRDNCLR - Peripheral memory clock power-down clear. */ +/* Whole 32 bits */ + +/*------------------TMS570_PCR_PSPWRDWNSETx------------------*/ +/* field: PWRDWNSET - Peripheral select quadrant clock power-down set. */ +/* Whole 32 bits */ + +/*------------------TMS570_PCR_PSPWRDWNCLRx------------------*/ +/* field: PWRDWNCLR - Peripheral select quadrant clock power-down clear. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_PCR */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h new file mode 100644 index 0000000000..1cb8b03308 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h @@ -0,0 +1,298 @@ +/* The header file is generated by make_header.py from PLL.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_PLL +#define LIBBSP_ARM_TMS570_PLL + +#include + +typedef struct{ + uint32_t PLLCTL3; /*PLL Control 3 Register*/ + uint8_t reserved1 [108]; + uint32_t CLKSLIP; /*PLL Clock Slip Control Register*/ + uint8_t reserved2 [7600]; + uint32_t SSWPLL1; /*PLL Modulation Depth Measurement Control Register*/ + uint32_t SSWPLL2; /*SSW PLL BIST Control Register 2*/ + uint32_t SSWPLL3; /*SSW PLL BIST Control Register 3*/ + uint32_t CSDIS; /*Clock Source Disable Register*/ + uint32_t CSDISSET; /*Clock Source Disable Set Register*/ + uint32_t CSDISCLR; /*Clock Source Disable Clear Register*/ + uint8_t reserved3 [24]; + uint32_t CSVSTAT; /*Clock Source Valid Status Register*/ + uint8_t reserved4 [24]; + uint32_t PLLCTL1; /*PLL Control 1 Register*/ + uint32_t PLLCTL2; /*PLL Control 2 Register*/ + uint8_t reserved5 [16]; + uint32_t LPOMONCTL; /*LPO/Clock Monitor Control Register*/ + uint32_t CLKTEST; /*Clock Test Register*/ + uint8_t reserved6 [16]; + uint32_t GPREG1; /*General Purpose Register*/ + uint8_t reserved7 [72]; + uint32_t GLBSTAT; /*Global Status Register*/ +} tms570_pll_t; + + +/*---------------------TMS570_PLL_PLLCTL3---------------------*/ +/* field: ODPLL2 - Internal PLL Output Divider */ +#define TMS570_PLL_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31) +#define TMS570_PLL_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31) +#define TMS570_PLL_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31) + +/* field: PLLDIV2 - PLL2 Output Clock Divider */ +#define TMS570_PLL_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28) +#define TMS570_PLL_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_PLL_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: REFCLKDIV2 - Reference Clock Divider */ +#define TMS570_PLL_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21) +#define TMS570_PLL_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21) +#define TMS570_PLL_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) + +/* field: PLLMUL2 - PLL2 Multiplication Factor */ +#define TMS570_PLL_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15) +#define TMS570_PLL_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_PLL_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_PLL_CLKSLIP---------------------*/ +/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */ +#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13) +#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13) +#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13) + +/* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */ +#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3) +#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_PLL_SSWPLL1---------------------*/ +/* field: CAPTURE_WINDOW_INDEX - The capture counter present in the PLL wrapper will count the PLL clock edges when */ +#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX(val) BSP_FLD32(val,8, 15) +#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: COUNTER_READ_READY - Counter read ready. */ +#define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_BIT32(6) + +/* field: COUNTER_RESET - Counter reset. */ +#define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_BIT32(5) + +/* field: COUNTER_EN - Counter enable. */ +#define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_BIT32(4) + +/* field: TAP_COUNTER_DIS - The value in this register is used to program a particular bit in CLKOUT counter. */ +#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS(val) BSP_FLD32(val,1, 3) +#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_GET(reg) BSP_FLD32GET(reg,1, 3) +#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_SET(reg,val) BSP_FLD32SET(reg, val,1, 3) + +/* field: EXT_COUNTER_EN - Modulation Depth Measurement mode */ +#define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_BIT32(0) + + +/*---------------------TMS570_PLL_SSWPLL2---------------------*/ +/* field: SSW_CAPTURE_COUNT - Capture count. This register returns the value of the capture count. */ +/* Whole 32 bits */ + +/*---------------------TMS570_PLL_SSWPLL3---------------------*/ +/* field: SSW_CAPTURE_COUNT - Value of CLKout count register. */ +/* Whole 32 bits */ + +/*----------------------TMS570_PLL_CSDIS----------------------*/ +/* field: CLKSR_7_3_OFF - Clock source[7-3] off. */ +#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7) +#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: CLKSR_1_0_OFF - Clock source[1-0] off. */ +#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1) +#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_PLL_CSDISSET--------------------*/ +/* field: SETCLKSR_7_3_OFF - Set clock source[7-3] to the disabled state. */ +#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7) +#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: SETCLKSR_1_0_OFF - Set clock source[1-0] to the disabled state. */ +#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1) +#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_PLL_CSDISCLR--------------------*/ +/* field: CLRCLKSR_7_3_OFF - Enables clock source[7-3]. */ +#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7) +#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: CLRCLKSR_1_0_OFF - Enables clock source[1-0]. */ +#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1) +#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_PLL_CSVSTAT---------------------*/ +/* field: CLKSR_7_3V - Clock source[7-0] valid. */ +#define TMS570_PLL_CSVSTAT_CLKSR_7_3V(val) BSP_FLD32(val,3, 7) +#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: CLKSR_1_0V - Clock source[1-0] valid. */ +#define TMS570_PLL_CSVSTAT_CLKSR_1_0V(val) BSP_FLD32(val,0, 1) +#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_PLL_PLLCTL1---------------------*/ +/* field: ROS - Reset on PLL Slip */ +#define TMS570_PLL_PLLCTL1_ROS BSP_BIT32(31) + +/* field: MASK_SLIP - Mask detection of PLL slip */ +#define TMS570_PLL_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30) +#define TMS570_PLL_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30) +#define TMS570_PLL_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) + +/* field: PLLDIV - PLL Output Clock Divider */ +#define TMS570_PLL_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28) +#define TMS570_PLL_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_PLL_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: ROF - Reset on Oscillator Fail */ +#define TMS570_PLL_PLLCTL1_ROF BSP_BIT32(23) + +/* field: REFCLKDIV - Reference Clock Divider */ +#define TMS570_PLL_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21) +#define TMS570_PLL_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21) +#define TMS570_PLL_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) + +/* field: PLLMUL - PLL Multiplication Factor */ +#define TMS570_PLL_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15) +#define TMS570_PLL_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_PLL_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_PLL_PLLCTL2---------------------*/ +/* field: FMENA - Frequency Modulation Enable. */ +#define TMS570_PLL_PLLCTL2_FMENA BSP_BIT32(31) + +/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */ +#define TMS570_PLL_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30) +#define TMS570_PLL_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30) +#define TMS570_PLL_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30) + +/* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */ +#define TMS570_PLL_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20) +#define TMS570_PLL_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20) +#define TMS570_PLL_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20) + +/* field: ODPLL - Internal PLL Output Divider. */ +#define TMS570_PLL_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11) +#define TMS570_PLL_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11) +#define TMS570_PLL_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11) + +/* field: SPR_AMOUNT - Spreading Amount. */ +#define TMS570_PLL_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8) +#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*--------------------TMS570_PLL_LPOMONCTL--------------------*/ +/* field: BIAS_ENABLE - Bias enable. */ +#define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24) + +/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */ +#define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16) + +/* field: HFTRIM - High frequency oscillator trim value. */ +#define TMS570_PLL_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12) +#define TMS570_PLL_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12) +#define TMS570_PLL_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12) + + +/*---------------------TMS570_PLL_CLKTEST---------------------*/ +/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */ +#define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26) + +/* field: RANGEDETCTRL - Range detection control. */ +#define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_BIT32(25) + +/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */ +#define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_BIT32(24) + +/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */ +#define TMS570_PLL_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19) +#define TMS570_PLL_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_PLL_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + + +/*---------------------TMS570_PLL_GPREG1---------------------*/ +/* field: EMIF_FUNC - Enable EMIF functions to be output. */ +#define TMS570_PLL_GPREG1_EMIF_FUNC BSP_BIT32(31) + +/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */ +#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25) +#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25) +#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) + +/* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */ +#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19) +#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */ +#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15) +#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_PLL_GLBSTAT---------------------*/ +/* field: FBSLIP - PLL over cycle slip detection. */ +#define TMS570_PLL_GLBSTAT_FBSLIP BSP_BIT32(9) + +/* field: RFSLIP - PLL under cycle slip detection. */ +#define TMS570_PLL_GLBSTAT_RFSLIP BSP_BIT32(8) + +/* field: OSCFAIL - Oscillator fail flag bit. */ +#define TMS570_PLL_GLBSTAT_OSCFAIL BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_PLL */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h new file mode 100644 index 0000000000..c834b83999 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h @@ -0,0 +1,258 @@ +/* The header file is generated by make_header.py from PMM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_PMM +#define LIBBSP_ARM_TMS570_PMM + +#include + +typedef struct{ + uint32_t LOGICPDPWRCTRL0; /*Logic Power Domain Control Register 0*/ + uint8_t reserved1 [12]; + uint32_t MEMPDPWRCTRL0; /*Memory Power Domain Control Register 0*/ + uint8_t reserved2 [12]; + uint32_t PDCLKDISREG; /*Power Domain Clock Disable Register*/ + uint32_t PDCLKDISSETREG; /*Power Domain Clock Disable Set Register*/ + uint32_t PDCLKDISCLRREG; /*Power Domain Clock Disable Clear Register*/ + uint8_t reserved3 [20]; + uint32_t LOGICPDPWRSTAT[4]; /*Logic Power Domain PD2 Power Status Registers*/ + uint8_t reserved4 [48]; + uint32_t MEMPDPWRSTAT[3]; /*Memory Power Domain RAM_PD1 Power Status Registers*/ + uint8_t reserved5 [20]; + uint32_t GLOBALCTRL1; /*Global Control Register 1*/ + uint8_t reserved6 [4]; + uint32_t GLOBALSTAT; /*Global Status Register*/ + uint32_t PRCKEYREG; /*PSCON Diagnostic Compare Key Register*/ + uint32_t LPDDCSTAT1; /*LogicPD PSCON Diagnostic Compare Status Register 1*/ + uint32_t LPDDCSTAT2; /*LogicPD PSCON Diagnostic Compare Status Register 2*/ + uint32_t MPDDCSTAT1; /*Memory PD PSCON Diagnostic Compare Status Register 1*/ + uint32_t MPDDCSTAT2; /*Memory PD PSCON Diagnostic Compare Status Register 2*/ + uint32_t ISODIAGSTAT; /*Isolation Diagnostic Status Register*/ +} tms570_pmm_t; + + +/*-----------------TMS570_PMM_LOGICPDPWRCTRL0-----------------*/ +/* field: LOGICPDON0 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0(val) BSP_FLD32(val,24, 27) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: LOGICPDON1 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON1(val) BSP_FLD32(val,16, 19) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON1_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON1_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: LOGICPDON2 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON2(val) BSP_FLD32(val,8, 11) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON2_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON2_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: LOGICPDON3 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3(val) BSP_FLD32(val,0, 3) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_PMM_MEMPDPWRCTRL0------------------*/ +/* field: MEMPDON0 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0(val) BSP_FLD32(val,24, 27) +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: MEMPDON1 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON1(val) BSP_FLD32(val,16, 19) +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON1_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON1_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: MEMPDON2 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2(val) BSP_FLD32(val,8, 11) +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + + +/*-------------------TMS570_PMM_PDCLKDISREG-------------------*/ +/* field: PDCLK_DIS_3 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[3]. */ +#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_3 BSP_BIT32(3) + +/* field: PDCLK_DIS_2 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. */ +#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_2 BSP_BIT32(2) + +/* field: PDCLK_DIS_1 - ead in User and Privileged Mode returns the current value of PDCLK_DIS[1]. */ +#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_1 BSP_BIT32(1) + +/* field: PDCLK_DIS_0 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. */ +#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_0 BSP_BIT32(0) + + +/*-----------------TMS570_PMM_PDCLKDISSETREG-----------------*/ +/* field: PDCLK_DISSET_3 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[3]. */ +#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_3 BSP_BIT32(3) + +/* field: PDCLK_DISSET_2 - Privileged Mode only. */ +#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_2 BSP_BIT32(2) + +/* field: PDCLK_DISSET_1 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[1]. */ +#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_1 BSP_BIT32(1) + +/* field: PDCLK_DISSET_0 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[0]. */ +#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_0 BSP_BIT32(0) + + +/*-----------------TMS570_PMM_PDCLKDISCLRREG-----------------*/ +/* field: PDCLK_DISCLR_3 - PDCLK_DISCLR[3] */ +#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_3 BSP_BIT32(3) + +/* field: PDCLK_DISCLR_2 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. */ +#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_2 BSP_BIT32(2) + +/* field: PDCLK_DISCLR_1 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[1]. */ +#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_1 BSP_BIT32(1) + +/* field: PDCLK_DISCLR_0 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. */ +#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_0 BSP_BIT32(0) + + +/*-----------------TMS570_PMM_LOGICPDPWRSTAT-----------------*/ +/* field: LOGIC_IN_TRANS0 - Logic in transition status for power domain PD2. */ +#define TMS570_PMM_LOGICPDPWRSTAT_LOGIC_IN_TRANS0 BSP_BIT32(24) + +/* field: MEM_IN_TRANS0 - Memory in transition status for power domain PD2. */ +#define TMS570_PMM_LOGICPDPWRSTAT_MEM_IN_TRANS0 BSP_BIT32(16) + +/* field: DOMAIN_ON0 - Current state of power domain PD2. */ +#define TMS570_PMM_LOGICPDPWRSTAT_DOMAIN_ON0 BSP_BIT32(8) + +/* field: LOGICPDPWR_STAT0 - Logic power domain PD2 power state. */ +#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0(val) BSP_FLD32(val,0, 1) +#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*------------------TMS570_PMM_MEMPDPWRSTAT------------------*/ +/* field: LOGIC_IN_TRANS0 - Logic in transition status for power domain RAM_PD1. */ +#define TMS570_PMM_MEMPDPWRSTAT_LOGIC_IN_TRANS0 BSP_BIT32(24) + +/* field: MEM_IN_TRANS0 - Memory in transition status for power domain RAM_PD1. */ +#define TMS570_PMM_MEMPDPWRSTAT_MEM_IN_TRANS0 BSP_BIT32(16) + +/* field: DOMAIN_ON0 - Current state of power domain RAM_PD1. */ +#define TMS570_PMM_MEMPDPWRSTAT_DOMAIN_ON0 BSP_BIT32(8) + +/* field: MEMPDPWR_STAT0 - Memory power domain RAM_PD1 power state. */ +#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0(val) BSP_FLD32(val,0, 1) +#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*-------------------TMS570_PMM_GLOBALCTRL1-------------------*/ +/* field: PMCTRL_PWRDN - PMC/PSCON Power Down */ +#define TMS570_PMM_GLOBALCTRL1_PMCTRL_PWRDN BSP_BIT32(8) + +/* field: AUTO_CLK_WAKE_ENA - Automatic Clock Enable on Wake Up */ +#define TMS570_PMM_GLOBALCTRL1_AUTO_CLK_WAKE_ENA BSP_BIT32(0) + + +/*-------------------TMS570_PMM_GLOBALSTAT-------------------*/ +/* field: PMCTRL_IDLE - State of PMC and all PSCONs. */ +#define TMS570_PMM_GLOBALSTAT_PMCTRL_IDLE BSP_BIT32(0) + + +/*--------------------TMS570_PMM_PRCKEYREG--------------------*/ +/* field: MKEY - Diagnostic PSCON Mode Key. The mode key is applied to all individual PSCON compare units. */ +#define TMS570_PMM_PRCKEYREG_MKEY(val) BSP_FLD32(val,0, 3) +#define TMS570_PMM_PRCKEYREG_MKEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_PMM_PRCKEYREG_MKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_PMM_LPDDCSTAT1-------------------*/ +/* field: LCMPE - Logic Power Domain Compare Error */ +#define TMS570_PMM_LPDDCSTAT1_LCMPE(val) BSP_FLD32(val,16, 19) +#define TMS570_PMM_LPDDCSTAT1_LCMPE_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_PMM_LPDDCSTAT1_LCMPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: LSTC - Logic Power Domain Self-test Complete */ +#define TMS570_PMM_LPDDCSTAT1_LSTC(val) BSP_FLD32(val,0, 3) +#define TMS570_PMM_LPDDCSTAT1_LSTC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_PMM_LPDDCSTAT1_LSTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_PMM_LPDDCSTAT2-------------------*/ +/* field: LSTET - Logic Power Domain Self-test Error Type */ +#define TMS570_PMM_LPDDCSTAT2_LSTET(val) BSP_FLD32(val,16, 19) +#define TMS570_PMM_LPDDCSTAT2_LSTET_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_PMM_LPDDCSTAT2_LSTET_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: LSTE - Logic Power Domain Self-test Error */ +#define TMS570_PMM_LPDDCSTAT2_LSTE(val) BSP_FLD32(val,0, 3) +#define TMS570_PMM_LPDDCSTAT2_LSTE_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_PMM_LPDDCSTAT2_LSTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_PMM_MPDDCSTAT1-------------------*/ +/* field: MCMPE - Memory Power Domain Compare Error */ +#define TMS570_PMM_MPDDCSTAT1_MCMPE(val) BSP_FLD32(val,16, 18) +#define TMS570_PMM_MPDDCSTAT1_MCMPE_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_PMM_MPDDCSTAT1_MCMPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: MSTC - Memory Power Domain Self-test Complete */ +#define TMS570_PMM_MPDDCSTAT1_MSTC(val) BSP_FLD32(val,0, 2) +#define TMS570_PMM_MPDDCSTAT1_MSTC_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_PMM_MPDDCSTAT1_MSTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-------------------TMS570_PMM_MPDDCSTAT2-------------------*/ +/* field: MSTET - Memory Power Domain Self-test Error Type */ +#define TMS570_PMM_MPDDCSTAT2_MSTET(val) BSP_FLD32(val,16, 18) +#define TMS570_PMM_MPDDCSTAT2_MSTET_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_PMM_MPDDCSTAT2_MSTET_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: MSTE - Memory Power Domain Self-test Error */ +#define TMS570_PMM_MPDDCSTAT2_MSTE(val) BSP_FLD32(val,0, 2) +#define TMS570_PMM_MPDDCSTAT2_MSTE_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_PMM_MPDDCSTAT2_MSTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-------------------TMS570_PMM_ISODIAGSTAT-------------------*/ +/* field: ISO_DIAG - Isolation Diagnostic */ +#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG(val) BSP_FLD32(val,0, 3) +#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + + +#endif /* LIBBSP_ARM_TMS570_PMM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h new file mode 100644 index 0000000000..1a4df19f8a --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h @@ -0,0 +1,309 @@ +/* The header file is generated by make_header.py from POM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_POM +#define LIBBSP_ARM_TMS570_POM + +#include + +typedef struct{ + uint32_t PROGSTART; /*POM Program Region Start Address Register*/ + uint32_t OVLSTART; /*POM Overlay Region Start Address Register*/ + uint32_t REGSIZE; /*POM Region Size Register */ + uint32_t Reser; /*Reserved*/ +} tms570_pom_region_t; + +typedef struct{ + uint32_t GLBCTRL; /*POM Global Control Register*/ + uint32_t REV; /*POM Revision ID*/ + uint32_t CLKCTRL; /*POM Clock Gate Control Register*/ + uint32_t FLG; /*POM Status Register*/ + uint8_t reserved1 [496]; + tms570_pom_region_t REG[32];/*Program Regions*/ + uint8_t reserved2 [2816]; + uint32_t ITCTRL; /*POM Integration Control Register*/ + uint8_t reserved3 [156]; + uint32_t CLAIMSET; /*POM Claim Set Register*/ + uint32_t CLAIMCLR; /*POM Claim Clear Register*/ + uint8_t reserved4 [8]; + uint32_t LOCKACCESS; /*POM Lock Access Register*/ + uint32_t LOCKSTATUS; /*POM Lock Status Register*/ + uint32_t AUTHSTATUS; /*POM Authentication Status Register*/ + uint8_t reserved5 [12]; + uint32_t DEVID; /*POM Device ID Register*/ + uint32_t DEVTYPE; /*POM Device Type Register*/ + uint32_t PERIPHERALID4; /*POM Peripheral ID 4 Register*/ + uint32_t PERIPHERALID5; /*POM Peripheral ID 5 Register*/ + uint32_t PERIPHERALID6; /*POM Peripheral ID 6 Register*/ + uint32_t PERIPHERALID7; /*POM Peripheral ID 7 Register*/ + uint32_t PERIPHERALID0; /*POM Peripheral ID 0 Register*/ + uint32_t PERIPHERALID1; /*POM Peripheral ID 1 Register*/ + uint32_t PERIPHERALID2; /*POM Peripheral ID 2 Register*/ + uint32_t PERIPHERALID3; /*POM Peripheral ID 3 Register*/ + uint32_t COMPONENTID0; /*POM Component ID 0 Register*/ + uint32_t COMPONENTID1; /*POM Component ID 1 Register*/ + uint32_t COMPONENTID2; /*POM Component ID 2 Register*/ + uint32_t COMPONENTID3; /*POM Component ID 3 Register*/ +} tms570_pom_t; + + +/*--------------------TMS570_POM_PROGSTART--------------------*/ +/* field: STARTADDRESS - Defines the start address of the program memory region. */ +#define TMS570_POM_PROGSTART_STARTADDRESS(val) BSP_FLD32(val,0, 22) +#define TMS570_POM_PROGSTART_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 22) +#define TMS570_POM_PROGSTART_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 22) + + +/*--------------------TMS570_POM_OVLSTART--------------------*/ +/* field: STARTADDRESS - Defines the start address of the overlay memory region. */ +#define TMS570_POM_OVLSTART_STARTADDRESS(val) BSP_FLD32(val,0, 22) +#define TMS570_POM_OVLSTART_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 22) +#define TMS570_POM_OVLSTART_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 22) + + +/*---------------------TMS570_POM_REGSIZE---------------------*/ +/* field: SIZE - Region size */ +#define TMS570_POM_REGSIZE_SIZE(val) BSP_FLD32(val,0, 3) +#define TMS570_POM_REGSIZE_SIZE_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_POM_REGSIZE_SIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_POM_GLBCTRL---------------------*/ +/* field: OTADDR - Overlay target Address. */ +#define TMS570_POM_GLBCTRL_OTADDR(val) BSP_FLD32(val,23, 31) +#define TMS570_POM_GLBCTRL_OTADDR_GET(reg) BSP_FLD32GET(reg,23, 31) +#define TMS570_POM_GLBCTRL_OTADDR_SET(reg,val) BSP_FLD32SET(reg, val,23, 31) + +/* field: ETO - Enable Timeout. Refer to Section 18.2.2 for more details on the timeout error. */ +#define TMS570_POM_GLBCTRL_ETO(val) BSP_FLD32(val,8, 11) +#define TMS570_POM_GLBCTRL_ETO_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_POM_GLBCTRL_ETO_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: ON_OFF - Turn functionality of POM on or off. */ +#define TMS570_POM_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3) +#define TMS570_POM_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_POM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-----------------------TMS570_POM_REV-----------------------*/ +/* field: SCHEME - Used to distinguish between different ID schemes. */ +#define TMS570_POM_REV_SCHEME(val) BSP_FLD32(val,30, 31) +#define TMS570_POM_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31) +#define TMS570_POM_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31) + +/* field: FUNC - Indicates the SW compatible module family */ +#define TMS570_POM_REV_FUNC(val) BSP_FLD32(val,16, 27) +#define TMS570_POM_REV_FUNC_GET(reg) BSP_FLD32GET(reg,16, 27) +#define TMS570_POM_REV_FUNC_SET(reg,val) BSP_FLD32SET(reg, val,16, 27) + +/* field: RTL - RTL version number */ +#define TMS570_POM_REV_RTL(val) BSP_FLD32(val,11, 15) +#define TMS570_POM_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15) +#define TMS570_POM_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15) + +/* field: MAJOR - Major revision number */ +#define TMS570_POM_REV_MAJOR(val) BSP_FLD32(val,8, 10) +#define TMS570_POM_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_POM_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: CUSTOM - Indicates a device specific implementation */ +#define TMS570_POM_REV_CUSTOM(val) BSP_FLD32(val,6, 7) +#define TMS570_POM_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_POM_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: 5_0 - MINOR 8h Minor revision number */ +#define TMS570_POM_REV_5_0(val) BSP_FLD32(val,0, 5) +#define TMS570_POM_REV_5_0_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_POM_REV_5_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*---------------------TMS570_POM_CLKCTRL---------------------*/ +/* field: CLK_GATE_OFF - Do not modify this bit. Leave it in its reset state. */ +#define TMS570_POM_CLKCTRL_CLK_GATE_OFF BSP_BIT32(0) + + +/*-----------------------TMS570_POM_FLG-----------------------*/ +/* field: TO - Timeout. */ +#define TMS570_POM_FLG_TO BSP_BIT32(0) + + +/*---------------------TMS570_POM_ITCTRL---------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*--------------------TMS570_POM_CLAIMSET--------------------*/ +/* field: SET1 - The module is claimed */ +#define TMS570_POM_CLAIMSET_SET1 BSP_BIT32(1) + +/* field: SET0 - The module is claimed */ +#define TMS570_POM_CLAIMSET_SET0 BSP_BIT32(0) + + +/*--------------------TMS570_POM_CLAIMCLR--------------------*/ +/* field: CLR1 - The module is claimed */ +#define TMS570_POM_CLAIMCLR_CLR1 BSP_BIT32(1) + +/* field: CLR0 - The module is claimed */ +#define TMS570_POM_CLAIMCLR_CLR0 BSP_BIT32(0) + + +/*-------------------TMS570_POM_LOCKACCESS-------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*-------------------TMS570_POM_LOCKSTATUS-------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*-------------------TMS570_POM_AUTHSTATUS-------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*----------------------TMS570_POM_DEVID----------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*---------------------TMS570_POM_DEVTYPE---------------------*/ +/* field: Sub_Type - Other */ +#define TMS570_POM_DEVTYPE_Sub_Type(val) BSP_FLD32(val,4, 7) +#define TMS570_POM_DEVTYPE_Sub_Type_GET(reg) BSP_FLD32GET(reg,4, 7) +#define TMS570_POM_DEVTYPE_Sub_Type_SET(reg,val) BSP_FLD32SET(reg, val,4, 7) + +/* field: Major_Type - Debug Control */ +#define TMS570_POM_DEVTYPE_Major_Type(val) BSP_FLD32(val,0, 3) +#define TMS570_POM_DEVTYPE_Major_Type_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_POM_DEVTYPE_Major_Type_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_POM_PERIPHERALID4------------------*/ +/* field: 4KB_Count - Only 4KB implemented */ +#define TMS570_POM_PERIPHERALID4_4KB_Count(val) BSP_FLD32(val,4, 7) +#define TMS570_POM_PERIPHERALID4_4KB_Count_GET(reg) BSP_FLD32GET(reg,4, 7) +#define TMS570_POM_PERIPHERALID4_4KB_Count_SET(reg,val) BSP_FLD32SET(reg, val,4, 7) + +/* field: JEP_Continuation - JEP106 Code */ +#define TMS570_POM_PERIPHERALID4_JEP_Continuation(val) BSP_FLD32(val,0, 3) +#define TMS570_POM_PERIPHERALID4_JEP_Continuation_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_POM_PERIPHERALID4_JEP_Continuation_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_POM_PERIPHERALID5------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*------------------TMS570_POM_PERIPHERALID6------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*------------------TMS570_POM_PERIPHERALID7------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*------------------TMS570_POM_PERIPHERALID0------------------*/ +/* field: Part_Number - Reads 0, since POMREV defines the module */ +#define TMS570_POM_PERIPHERALID0_Part_Number(val) BSP_FLD32(val,0, 7) +#define TMS570_POM_PERIPHERALID0_Part_Number_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_POM_PERIPHERALID0_Part_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_POM_PERIPHERALID1------------------*/ +/* field: JEP106_Identity - Part of TI JEDEC number */ +#define TMS570_POM_PERIPHERALID1_JEP106_Identity(val) BSP_FLD32(val,4, 7) +#define TMS570_POM_PERIPHERALID1_JEP106_Identity_GET(reg) BSP_FLD32GET(reg,4, 7) +#define TMS570_POM_PERIPHERALID1_JEP106_Identity_SET(reg,val) BSP_FLD32SET(reg, val,4, 7) + +/* field: Part_Number - Reads 0, since POMREV defines the module */ +#define TMS570_POM_PERIPHERALID1_Part_Number(val) BSP_FLD32(val,0, 3) +#define TMS570_POM_PERIPHERALID1_Part_Number_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_POM_PERIPHERALID1_Part_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_POM_PERIPHERALID2------------------*/ +/* field: Revision - Reads 0, since POMREV defines the module */ +#define TMS570_POM_PERIPHERALID2_Revision(val) BSP_FLD32(val,4, 7) +#define TMS570_POM_PERIPHERALID2_Revision_GET(reg) BSP_FLD32GET(reg,4, 7) +#define TMS570_POM_PERIPHERALID2_Revision_SET(reg,val) BSP_FLD32SET(reg, val,4, 7) + +/* field: JEDEC - Indicates JEDEC assigned value */ +#define TMS570_POM_PERIPHERALID2_JEDEC BSP_BIT32(3) + +/* field: JEP106_Identity - JEDEC+JEP106 Identity Code (POMPERIPHERALID2)+JEP106 Identity Code */ +#define TMS570_POM_PERIPHERALID2_JEP106_Identity(val) BSP_FLD32(val,0, 2) +#define TMS570_POM_PERIPHERALID2_JEP106_Identity_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_POM_PERIPHERALID2_JEP106_Identity_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*------------------TMS570_POM_PERIPHERALID3------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*------------------TMS570_POM_COMPONENTID0------------------*/ +/* field: Preamble - Preamble */ +#define TMS570_POM_COMPONENTID0_Preamble(val) BSP_FLD32(val,0, 7) +#define TMS570_POM_COMPONENTID0_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_POM_COMPONENTID0_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_POM_COMPONENTID1------------------*/ +/* field: Component_Class - CoreSight Component */ +#define TMS570_POM_COMPONENTID1_Component_Class(val) BSP_FLD32(val,4, 7) +#define TMS570_POM_COMPONENTID1_Component_Class_GET(reg) BSP_FLD32GET(reg,4, 7) +#define TMS570_POM_COMPONENTID1_Component_Class_SET(reg,val) BSP_FLD32SET(reg, val,4, 7) + +/* field: Preamble - Preamble */ +#define TMS570_POM_COMPONENTID1_Preamble(val) BSP_FLD32(val,0, 3) +#define TMS570_POM_COMPONENTID1_Preamble_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_POM_COMPONENTID1_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_POM_COMPONENTID2------------------*/ +/* field: Preamble - Preamble */ +#define TMS570_POM_COMPONENTID2_Preamble(val) BSP_FLD32(val,0, 7) +#define TMS570_POM_COMPONENTID2_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_POM_COMPONENTID2_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_POM_COMPONENTID3------------------*/ +/* field: Preamble - Preamble */ +#define TMS570_POM_COMPONENTID3_Preamble(val) BSP_FLD32(val,0, 7) +#define TMS570_POM_COMPONENTID3_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_POM_COMPONENTID3_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + + +#endif /* LIBBSP_ARM_TMS570_POM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h new file mode 100644 index 0000000000..029b3b5721 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h @@ -0,0 +1,359 @@ +/* The header file is generated by make_header.py from RTI.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_RTI +#define LIBBSP_ARM_TMS570_RTI + +#include + +typedef struct{ + uint32_t COMPx; /*RTI Compare x Register*/ + uint32_t UDCPx; /*RTI Update Compare x Register*/ +} tms570_rti_compare_t; + +typedef struct{ + uint32_t FRCx; /*RTI Free Running Counter x Register*/ + uint32_t UCx; /*RTI Up Counter x Register*/ + uint32_t CPUCx; /*RTI Compare Up Counter x Register*/ + uint8_t reserved1 [4]; + uint32_t CAFRCx; /*RTI Capture Free Running Counter x Register*/ + uint32_t CAUCx; /*RTI Capture Up Counter x Register*/ + uint32_t rsvd[2]; /*Reserved*/ +} tms570_rti_counter_t; + +typedef struct{ + uint32_t GCTRL; /*RTI Global Control Register*/ + uint32_t TBCTRL; /*RTI Timebase Control Register*/ + uint32_t CAPCTRL; /*RTI Capture Control Register*/ + uint32_t COMPCTRL; /*RTI Compare Control Register*/ + tms570_rti_counter_t CNT[2];/*Counters*/ + tms570_rti_compare_t CMP[4];/*Compares*/ + uint32_t TBLCOMP; /*RTI Timebase Low Compare Register*/ + uint32_t TBHCOMP; /*RTI Timebase High Compare Register*/ + uint8_t reserved2 [8]; + uint32_t SETINTENA; /*RTI Set Interrupt Enable Register*/ + uint32_t CLEARINTENA; /*RTI Clear Interrupt Enable Register*/ + uint32_t INTFLAG; /*RTI Interrupt Flag Register*/ + uint8_t reserved3 [4]; + uint32_t DWDCTRL; /*Digital Watchdog Control Register*/ + uint32_t DWDPRLD; /*Digital Watchdog Preload Register*/ + uint32_t WDSTATUS; /*Watchdog Status Register*/ + uint32_t WDKEY; /*RTI Watchdog Key Register*/ + uint32_t DWDCNTR; /*RTI Digital Watchdog Down Counter Register*/ + uint32_t WWDRXNCTRL; /*Digital Windowed Watchdog Reaction Control Register*/ + uint32_t WWDSIZECTRL; /*Digital Windowed Watchdog Window Size Control Register*/ + uint32_t INTCLRENABLE; /*RTI Compare Interrupt Clear Enable Register*/ + uint32_t COMP0CLR; /*RTI Compare 0 Clear Register*/ + uint32_t COMP1CLR; /*RTI Compare 1 Clear Register*/ + uint32_t COMP2CLR; /*RTI Compare 2 Clear Register*/ + uint32_t COMP3CLR; /*RTI Compare 3 Clear Register*/ +} tms570_rti_t; + + +/*----------------------TMS570_RTI_COMPx----------------------*/ +/* field: COMPx - Compare x. */ +/* Whole 32 bits */ + +/*----------------------TMS570_RTI_UDCPx----------------------*/ +/* field: UDCPx - Update compare x. */ +/* Whole 32 bits */ + +/*----------------------TMS570_RTI_FRCx----------------------*/ +/* field: FRC0 - FRC0 */ +/* Whole 32 bits */ + +/*-----------------------TMS570_RTI_UCx-----------------------*/ +/* field: UC0 - Up counter 0. */ +/* Whole 32 bits */ + +/*----------------------TMS570_RTI_CPUCx----------------------*/ +/* field: CPUC0 - Compare up counter 0. This register holds the value that is compared with the up counter 0. */ +/* Whole 32 bits */ + +/*---------------------TMS570_RTI_CAFRCx---------------------*/ +/* field: CAFRC0 - Capture free running counter 0. */ +/* Whole 32 bits */ + +/*----------------------TMS570_RTI_CAUCx----------------------*/ +/* field: CAUC0 - Capture up counter 0. */ +/* Whole 32 bits */ + +/*----------------------TMS570_RTI_rsvd----------------------*/ +/* field: CAUC0 - Capture up counter 0. */ +/* Whole 32 bits */ + +/*----------------------TMS570_RTI_GCTRL----------------------*/ +/* field: NTUSEL - Select NTU signal. */ +#define TMS570_RTI_GCTRL_NTUSEL(val) BSP_FLD32(val,16, 19) +#define TMS570_RTI_GCTRL_NTUSEL_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_RTI_GCTRL_NTUSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: COS - Continue on suspend. */ +#define TMS570_RTI_GCTRL_COS BSP_BIT32(15) + +/* field: CNT1EN - Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1). */ +#define TMS570_RTI_GCTRL_CNT1EN BSP_BIT32(1) + +/* field: CNT0EN - Counter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0). */ +#define TMS570_RTI_GCTRL_CNT0EN BSP_BIT32(0) + + +/*---------------------TMS570_RTI_TBCTRL---------------------*/ +/* field: INC - Increment free running counter 0. */ +#define TMS570_RTI_TBCTRL_INC BSP_BIT32(1) + +/* field: TBEXT - Timebase external. */ +#define TMS570_RTI_TBCTRL_TBEXT BSP_BIT32(0) + + +/*---------------------TMS570_RTI_CAPCTRL---------------------*/ +/* field: CAPCNTR1 - Capture counter 1. */ +#define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_BIT32(1) + +/* field: CAPCNTR0 - Capture counter 0. */ +#define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_BIT32(0) + + +/*--------------------TMS570_RTI_COMPCTRL--------------------*/ +/* field: COMPSEL3 - Compare select 3. */ +#define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_BIT32(12) + +/* field: COMPSEL2 - Compare select 2. */ +#define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_BIT32(8) + +/* field: COMPSEL1 - Compare select 1. */ +#define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_BIT32(4) + +/* field: COMPSEL0 - Compare select 0. */ +#define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_BIT32(0) + + +/*---------------------TMS570_RTI_TBLCOMP---------------------*/ +/* field: TBLCOMP - Timebase low compare value. */ +/* Whole 32 bits */ + +/*---------------------TMS570_RTI_TBHCOMP---------------------*/ +/* field: TBHCOMP - Timebase high compare value. */ +/* Whole 32 bits */ + +/*--------------------TMS570_RTI_SETINTENA--------------------*/ +/* field: SETOVL1INT - Set free running counter 1 overflow interrupt. */ +#define TMS570_RTI_SETINTENA_SETOVL1INT BSP_BIT32(18) + +/* field: SETOVL0INT - Set free running counter 0 overflow interrupt. */ +#define TMS570_RTI_SETINTENA_SETOVL0INT BSP_BIT32(17) + +/* field: SETTBINT - Set timebase interrupt. */ +#define TMS570_RTI_SETINTENA_SETTBINT BSP_BIT32(16) + +/* field: SETDMA3 - Set compare DMA request 3. */ +#define TMS570_RTI_SETINTENA_SETDMA3 BSP_BIT32(11) + +/* field: SETDMA2 - Set compare DMA request 2. */ +#define TMS570_RTI_SETINTENA_SETDMA2 BSP_BIT32(10) + +/* field: SETDMA1 - Set compare DMA request 1. */ +#define TMS570_RTI_SETINTENA_SETDMA1 BSP_BIT32(9) + +/* field: SETDMA0 - Set compare DMA request 0. */ +#define TMS570_RTI_SETINTENA_SETDMA0 BSP_BIT32(8) + +/* field: SETINT3 - Set compare interrupt 3. */ +#define TMS570_RTI_SETINTENA_SETINT3 BSP_BIT32(3) + +/* field: SETINT2 - Set compare interrupt 2. */ +#define TMS570_RTI_SETINTENA_SETINT2 BSP_BIT32(2) + +/* field: SETINT1 - Set compare interrupt 1. */ +#define TMS570_RTI_SETINTENA_SETINT1 BSP_BIT32(1) + +/* field: SETINT0 - Set compare interrupt 0. */ +#define TMS570_RTI_SETINTENA_SETINT0 BSP_BIT32(0) + + +/*-------------------TMS570_RTI_CLEARINTENA-------------------*/ +/* field: CLEAROVL1INT - Clear free running counter 1 overflow interrupt. */ +#define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_BIT32(18) + +/* field: CLEAROVL0INT - Clear free running counter 0 overflow interrupt. */ +#define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_BIT32(17) + +/* field: CLEARTBINT - Clear timebase interrupt. */ +#define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_BIT32(16) + +/* field: CLEARDMA3 - Clear compare DMA request 3. */ +#define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_BIT32(11) + +/* field: CLEARDMA2 - Clear compare DMA request 2. */ +#define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_BIT32(10) + +/* field: CLEARDMA1 - Clear compare DMA request 1. */ +#define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_BIT32(9) + +/* field: CLEARDMA0 - Clear compare DMA request 0. */ +#define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_BIT32(8) + +/* field: CLEARINT3 - Clear compare interrupt 3. */ +#define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_BIT32(3) + +/* field: CLEARINT2 - Clear compare interrupt 2. */ +#define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_BIT32(2) + +/* field: CLEARINT1 - Clear compare interrupt 1. */ +#define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_BIT32(1) + +/* field: CLEARINT0 - Clear compare interrupt 0. */ +#define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_BIT32(0) + + +/*---------------------TMS570_RTI_INTFLAG---------------------*/ +/* field: OVL1INT - Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending. */ +#define TMS570_RTI_INTFLAG_OVL1INT BSP_BIT32(18) + +/* field: OVL0INT - Free running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending. */ +#define TMS570_RTI_INTFLAG_OVL0INT BSP_BIT32(17) + +/* field: TBINT - Timebase interrupt flag. */ +#define TMS570_RTI_INTFLAG_TBINT BSP_BIT32(16) + +/* field: INT3 - Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending. */ +#define TMS570_RTI_INTFLAG_INT3 BSP_BIT32(3) + +/* field: INT2 - Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending. */ +#define TMS570_RTI_INTFLAG_INT2 BSP_BIT32(2) + +/* field: INT1 - Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. */ +#define TMS570_RTI_INTFLAG_INT1 BSP_BIT32(1) + +/* field: INT0 - Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending. */ +#define TMS570_RTI_INTFLAG_INT0 BSP_BIT32(0) + + +/*---------------------TMS570_RTI_DWDCTRL---------------------*/ +/* field: DWDCTRL - DWDCTRL Digital Watchdog Control. */ +/* Whole 32 bits */ + +/*---------------------TMS570_RTI_DWDPRLD---------------------*/ +/* field: DWDPRLD - Digital Watchdog Preload Value. */ +#define TMS570_RTI_DWDPRLD_DWDPRLD(val) BSP_FLD32(val,0, 15) +#define TMS570_RTI_DWDPRLD_DWDPRLD_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_RTI_DWDPRLD_DWDPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_RTI_WDSTATUS--------------------*/ +/* field: DWWD_ST - Windowed Watchdog Status */ +#define TMS570_RTI_WDSTATUS_DWWD_ST BSP_BIT32(5) + +/* field: END_TIME_VIOL - Windowed Watchdog End Time Violation Status. */ +#define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_BIT32(4) + +/* field: START_TIME_VIOL - Windowed Watchdog Start Time Violation Status. */ +#define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_BIT32(3) + +/* field: KEY_ST - Watchdog key status. */ +#define TMS570_RTI_WDSTATUS_KEY_ST BSP_BIT32(2) + +/* field: DWD_ST - DWD status. */ +#define TMS570_RTI_WDSTATUS_DWD_ST BSP_BIT32(1) + + +/*----------------------TMS570_RTI_WDKEY----------------------*/ +/* field: WDKEY - Watchdog key. These bits provide the key sequence location. */ +#define TMS570_RTI_WDKEY_WDKEY(val) BSP_FLD32(val,0, 15) +#define TMS570_RTI_WDKEY_WDKEY_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_RTI_WDKEY_WDKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_RTI_DWDCNTR---------------------*/ +/* field: DWDCNTR - DWD down counter. */ +#define TMS570_RTI_DWDCNTR_DWDCNTR(val) BSP_FLD32(val,0, 24) +#define TMS570_RTI_DWDCNTR_DWDCNTR_GET(reg) BSP_FLD32GET(reg,0, 24) +#define TMS570_RTI_DWDCNTR_DWDCNTR_SET(reg,val) BSP_FLD32SET(reg, val,0, 24) + + +/*-------------------TMS570_RTI_WWDRXNCTRL-------------------*/ +/* field: WWDRXN - The DWWD reaction */ +#define TMS570_RTI_WWDRXNCTRL_WWDRXN(val) BSP_FLD32(val,0, 3) +#define TMS570_RTI_WWDRXNCTRL_WWDRXN_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_RTI_WWDRXNCTRL_WWDRXN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_RTI_WWDSIZECTRL-------------------*/ +/* field: WWDSIZE - The DWWD window size */ +/* Whole 32 bits */ + +/*------------------TMS570_RTI_INTCLRENABLE------------------*/ +/* field: INTCLRENABLE3 - Enables the auto-clear functionality on the compare 3 interrupt. */ +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3(val) BSP_FLD32(val,24, 27) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: INTCLRENABLE2 - Enables the auto-clear functionality on the compare 2 interrupt. */ +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2(val) BSP_FLD32(val,16, 19) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: INTCLRENABLE1 - Enables the auto-clear functionality on the compare 1 interrupt. */ +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1(val) BSP_FLD32(val,8, 11) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: INTCLRENABLE0 - Enables the auto-clear functionality on the compare 0 interrupt. */ +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0(val) BSP_FLD32(val,0, 3) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_RTI_COMP0CLR--------------------*/ +/* field: CMP0CLR - Compare 0 clear. */ +/* Whole 32 bits */ + +/*--------------------TMS570_RTI_COMP1CLR--------------------*/ +/* field: CMP0CLR - Compare 1 clear. */ +/* Whole 32 bits */ + +/*--------------------TMS570_RTI_COMP2CLR--------------------*/ +/* field: CMP2CLR - Compare 2 clear. */ +/* Whole 32 bits */ + +/*--------------------TMS570_RTI_COMP3CLR--------------------*/ +/* field: CMP3CLR - Compare 3 clear. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_RTI */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h new file mode 100644 index 0000000000..cd54b29050 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h @@ -0,0 +1,227 @@ +/* The header file is generated by make_header.py from RTP.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_RTP +#define LIBBSP_ARM_TMS570_RTP + +#include + +typedef struct{ + uint32_t GLBCTRL; /*RTP Global Control Register*/ + uint32_t TRENA; /*RTP Trace Enable Register*/ + uint32_t GSR; /*RTP Global Status Register*/ + uint32_t RAM1REG1; /*RTP RAM 1 Trace Region 1 Register*/ + uint32_t RAM1REG2; /*RTP RAM 1 Trace Region 2 Register*/ + uint32_t RAM2REG1; /*RTP RAM 2 Trace Region 1 Register*/ + uint32_t RAM2REG2; /*RTP RAM 2 Trace Region 2 Register*/ + uint8_t reserved1 [8]; + uint32_t PERREG1; /*RTP Peripheral Trace Region 1 Register*/ + uint32_t PERREG2; /*RTP Peripheral Trace Region 2 Register*/ + uint32_t DDMW; /*RTP Direct Data Mode Write Register*/ + uint8_t reserved2 [4]; + uint32_t PC0; /*RTP Pin Control 0 Register*/ + uint32_t PC1; /*RTP Pin Control 1 Register*/ + uint32_t PC2; /*RTP Pin Control 2 Register*/ + uint32_t PC3; /*RTP Pin Control 3 Register*/ + uint32_t PC4; /*RTP Pin Control 4 Register*/ + uint32_t PC5; /*RTP Pin Control 5 Register*/ + uint32_t PC6; /*RTP Pin Control 6 Register*/ + uint32_t PC7; /*RTP Pin Control 7 Register*/ + uint32_t PC8; /*RTP Pin Control 8 Register*/ +} tms570_rtp_t; + + +/*---------------------TMS570_RTP_GLBCTRL---------------------*/ +/* field: TEST - By setting the bit, the FIFO RAM will be mapped into the SYSTEM Peripheral frame starting at */ +#define TMS570_RTP_GLBCTRL_TEST BSP_BIT32(24) + +/* field: PRESCALER - The prescaler divides HCLK down to the desired RTPCLK frequency. */ +#define TMS570_RTP_GLBCTRL_PRESCALER(val) BSP_FLD32(val,16, 18) +#define TMS570_RTP_GLBCTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_RTP_GLBCTRL_PRESCALER_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: DDM_WIDTH - Direct data mode word size width. */ +#define TMS570_RTP_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,12, 13) +#define TMS570_RTP_GLBCTRL_DDM_WIDTH_GET(reg) BSP_FLD32GET(reg,12, 13) +#define TMS570_RTP_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) + +/* field: DDM_RW - */ +#define TMS570_RTP_GLBCTRL_DDM_RW BSP_BIT32(11) + +/* field: TM_DDM - Trace Mode or Direct Data Mode */ +#define TMS570_RTP_GLBCTRL_TM_DDM BSP_BIT32(10) + +/* field: PW - Port width. This bit field configures the RTP to the desired port width. */ +#define TMS570_RTP_GLBCTRL_PW(val) BSP_FLD32(val,8, 9) +#define TMS570_RTP_GLBCTRL_PW_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_RTP_GLBCTRL_PW_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: RESET - This bit resets the state machine and the registers to their reset value. */ +#define TMS570_RTP_GLBCTRL_RESET BSP_BIT32(7) + +/* field: CONTCLK - Continuous RTPCLK enable. */ +#define TMS570_RTP_GLBCTRL_CONTCLK BSP_BIT32(6) + +/* field: HOVF - Halt on overflow. */ +#define TMS570_RTP_GLBCTRL_HOVF BSP_BIT32(5) + +/* field: INV_RGN - Trace inside or outside of defined trace regions. */ +#define TMS570_RTP_GLBCTRL_INV_RGN BSP_BIT32(4) + +/* field: ON_OFF - ON/Off switch. */ +#define TMS570_RTP_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3) +#define TMS570_RTP_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_RTP_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*----------------------TMS570_RTP_TRENA----------------------*/ +/* field: ENA4 - Enable tracing for peripherals. */ +#define TMS570_RTP_TRENA_ENA4 BSP_BIT32(24) + +/* field: ENA2 - Enable tracing for RAM block 2. */ +#define TMS570_RTP_TRENA_ENA2 BSP_BIT32(8) + +/* field: ENA1 - */ +#define TMS570_RTP_TRENA_ENA1 BSP_BIT32(0) + + +/*-----------------------TMS570_RTP_GSR-----------------------*/ +/* field: EMPTYSER - Serializer empty. This bit determines if there is data left in the serializer. */ +#define TMS570_RTP_GSR_EMPTYSER BSP_BIT32(12) + +/* field: EMPTYPER - Peripheral FIFO empty. This bit determines if there are entries left in the FIFO. */ +#define TMS570_RTP_GSR_EMPTYPER BSP_BIT32(11) + +/* field: EMPTY2 - RAM block 2 FIFO empty. This bit determines if there are entries left in the FIFO. */ +#define TMS570_RTP_GSR_EMPTY2 BSP_BIT32(9) + +/* field: EMPTY1 - RAM block 1 FIFO empty. This bit determines if there are entries left in the FIFO. */ +#define TMS570_RTP_GSR_EMPTY1 BSP_BIT32(8) + +/* field: OVFPER - Overflow peripheral FIFO. */ +#define TMS570_RTP_GSR_OVFPER BSP_BIT32(3) + +/* field: OVF2 - Overflow RAM block 2 FIFO. */ +#define TMS570_RTP_GSR_OVF2 BSP_BIT32(1) + +/* field: OVF1 - Overflow RAM block 1 FIFO. */ +#define TMS570_RTP_GSR_OVF1 BSP_BIT32(0) + + +/*--------------------TMS570_RTP_RAM1REGx--------------------*/ +/* field: CPU_DMA - CPU and/or other master access. */ +#define TMS570_RTP_RAM1REGx_CPU_DMA(val) BSP_FLD32(val,29, 30) +#define TMS570_RTP_RAM1REGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30) +#define TMS570_RTP_RAM1REGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) + +/* field: RW - Read/Write. */ +#define TMS570_RTP_RAM1REGx_RW BSP_BIT32(28) + +/* field: BLOCKSIZE - These bits define the length of the trace region. */ +#define TMS570_RTP_RAM1REGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27) +#define TMS570_RTP_RAM1REGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_RTP_RAM1REGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */ +#define TMS570_RTP_RAM1REGx_STARTADDR(val) BSP_FLD32(val,0, 17) +#define TMS570_RTP_RAM1REGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 17) +#define TMS570_RTP_RAM1REGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17) + + +/*--------------------TMS570_RTP_RAM2REGx--------------------*/ +/* field: CPU_DMA - CPU and/or other master access. */ +#define TMS570_RTP_RAM2REGx_CPU_DMA(val) BSP_FLD32(val,29, 30) +#define TMS570_RTP_RAM2REGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30) +#define TMS570_RTP_RAM2REGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) + +/* field: RW - Read/Write. */ +#define TMS570_RTP_RAM2REGx_RW BSP_BIT32(28) + +/* field: BLOCKSIZE - These bits define the length of the trace region. */ +#define TMS570_RTP_RAM2REGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27) +#define TMS570_RTP_RAM2REGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_RTP_RAM2REGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */ +#define TMS570_RTP_RAM2REGx_STARTADDR(val) BSP_FLD32(val,0, 23) +#define TMS570_RTP_RAM2REGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_RTP_RAM2REGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*---------------------TMS570_RTP_PERREGx---------------------*/ +/* field: CPU_DMA - CPU and/or other master access. */ +#define TMS570_RTP_PERREGx_CPU_DMA(val) BSP_FLD32(val,29, 30) +#define TMS570_RTP_PERREGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30) +#define TMS570_RTP_PERREGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) + +/* field: RW - Read/Write. */ +#define TMS570_RTP_PERREGx_RW BSP_BIT32(28) + +/* field: BLOCKSIZE - These bits define the length of the trace region. */ +#define TMS570_RTP_PERREGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27) +#define TMS570_RTP_PERREGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_RTP_PERREGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */ +#define TMS570_RTP_PERREGx_STARTADDR(val) BSP_FLD32(val,0, 23) +#define TMS570_RTP_PERREGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_RTP_PERREGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*----------------------TMS570_RTP_DDMW----------------------*/ +/* field: DATA - This register must be written to in a Direct Data Mode write operation to store the data into */ +/* Whole 32 bits */ + +/*-----------------------TMS570_RTP_PCx-----------------------*/ +/* field: ENAFUNC - Functional mode of RTPENA pin. */ +#define TMS570_RTP_PCx_ENAFUNC BSP_BIT32(18) + +/* field: CLKFUNC - Functional mode of RTPCLK pin. */ +#define TMS570_RTP_PCx_CLKFUNC BSP_BIT32(17) + +/* field: SYNCFUNC - Functional mode of RTPSYNC pin. */ +#define TMS570_RTP_PCx_SYNCFUNC BSP_BIT32(16) + +/* field: DATAFUNC - Functional mode of RTPDATA[15:0] pins. */ +#define TMS570_RTP_PCx_DATAFUNC(val) BSP_FLD32(val,0, 15) +#define TMS570_RTP_PCx_DATAFUNC_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_RTP_PCx_DATAFUNC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + + +#endif /* LIBBSP_ARM_TMS570_RTP */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h new file mode 100644 index 0000000000..6b954f7fcf --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h @@ -0,0 +1,450 @@ +/* The header file is generated by make_header.py from SCI.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_SCI +#define LIBBSP_ARM_TMS570_SCI + +#include + +typedef struct{ + uint32_t GCR0; /*SCI Global Control Register 0*/ + uint32_t GCR1; /*SCI Global Control Register 1*/ + uint32_t GCR2; /*SCI Global Control Register 2*/ + uint32_t SETINT; /*SCI Set Interrupt Register*/ + uint32_t CLEARINT; /*SCI Clear Interrupt Register*/ + uint32_t SETINTLVL; /*SCI Set Interrupt Level Register*/ + uint32_t CLEARINTLVL; /*SCI Clear Interrupt Level Register*/ + uint32_t FLR; /*SCI Flags Register*/ + uint32_t INTVECT0; /*SCI Interrupt Vector Offset 0*/ + uint32_t INTVECT1; /*SCI Interrupt Vector Offset 1*/ + uint32_t FORMAT; /*SCI Format Control Register*/ + uint32_t BRS; /*Baud Rate Selection Register*/ + uint32_t ED; /*Receiver Emulation Data Buffer*/ + uint32_t RD; /*Receiver Data Buffer*/ + uint32_t TD; /*Transmit Data Buffer*/ + uint32_t PIO0; /*SCI Pin I/O Control Register 0*/ + uint32_t PIO1; /*SCI Pin I/O Control Register 1*/ + uint32_t PIO2; /*SCI Pin I/O Control Register 2*/ + uint32_t PIO3; /*SCI Pin I/O Control Register 3*/ + uint32_t PIO4; /*SCI Pin I/O Control Register 4*/ + uint32_t PIO5; /*SCI Pin I/O Control Register 5*/ + uint32_t PIO6; /*SCI Pin I/O Control Register 6*/ + uint32_t PIO7; /*SCI Pin I/O Control Register 7*/ + uint32_t PIO8; /*SCI Pin I/O Control Register 8*/ + uint8_t reserved1 [48]; + uint32_t IODFTCTRL; /*Input/Output Error Enable Register*/ +} tms570_sci_t; + + +/*----------------------TMS570_SCI_GCR0----------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +#define TMS570_SCI_GCR0_Reserved(val) BSP_FLD32(val,1, 31) +#define TMS570_SCI_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31) +#define TMS570_SCI_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31) + +/* field: RESET - This bit resets the SCI module. */ +#define TMS570_SCI_GCR0_RESET BSP_BIT32(0) + + +/*----------------------TMS570_SCI_GCR1----------------------*/ +/* field: TXENA - Transmit enable. */ +#define TMS570_SCI_GCR1_TXENA BSP_BIT32(25) + +/* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */ +#define TMS570_SCI_GCR1_RXENA BSP_BIT32(24) + +/* field: CONT - Continue on suspend. */ +#define TMS570_SCI_GCR1_CONT BSP_BIT32(17) + +/* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */ +#define TMS570_SCI_GCR1_LOOP_BACK BSP_BIT32(16) + +/* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */ +#define TMS570_SCI_GCR1_POWERDOWN BSP_BIT32(9) + +/* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */ +#define TMS570_SCI_GCR1_SLEEP BSP_BIT32(8) + +/* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */ +#define TMS570_SCI_GCR1_SWnRST BSP_BIT32(7) + +/* field: CLOCK - CLOCK */ +#define TMS570_SCI_GCR1_CLOCK BSP_BIT32(5) + +/* field: STOP - SCI number of stop bits per frame. */ +#define TMS570_SCI_GCR1_STOP BSP_BIT32(4) + +/* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */ +#define TMS570_SCI_GCR1_PARITY BSP_BIT32(3) + +/* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */ +#define TMS570_SCI_GCR1_PARITY_ENA BSP_BIT32(2) + +/* field: TIMING_MODE - SCI timing mode bit. */ +#define TMS570_SCI_GCR1_TIMING_MODE BSP_BIT32(1) + +/* field: COMM_MODE - SCI communication mode bit. */ +#define TMS570_SCI_GCR1_COMM_MODE BSP_BIT32(0) + + +/*----------------------TMS570_SCI_GCR2----------------------*/ +/* field: CC - Compare checksum. LIN mode only. */ +#define TMS570_SCI_GCR2_CC BSP_BIT32(17) + +/* field: SC - Send checksum byte. This bit is effective in LIN mode only. */ +#define TMS570_SCI_GCR2_SC BSP_BIT32(16) + +/* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */ +#define TMS570_SCI_GCR2_GEN_WU BSP_BIT32(8) + +/* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */ +#define TMS570_SCI_GCR2_POWERDOWN BSP_BIT32(0) + + +/*---------------------TMS570_SCI_SETINT---------------------*/ +/* field: SET_FE_INT - */ +#define TMS570_SCI_SETINT_SET_FE_INT BSP_BIT32(26) + +/* field: SET_OE_INT - SET OE INT */ +#define TMS570_SCI_SETINT_SET_OE_INT BSP_BIT32(25) + +/* field: SET_PE_INT - Set parity interrupt. */ +#define TMS570_SCI_SETINT_SET_PE_INT BSP_BIT32(24) + +/* field: SET_RX_DMA_ALL - SET RX DMA ALL */ +#define TMS570_SCI_SETINT_SET_RX_DMA_ALL BSP_BIT32(18) + +/* field: SET_RX_DMA - SET RX DMA */ +#define TMS570_SCI_SETINT_SET_RX_DMA BSP_BIT32(17) + +/* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */ +#define TMS570_SCI_SETINT_SET_TX_DMA BSP_BIT32(16) + +/* field: SET_RX_INT - SET RX INT */ +#define TMS570_SCI_SETINT_SET_RX_INT BSP_BIT32(9) + +/* field: SET_TX_INT - Set transmitter interrupt. */ +#define TMS570_SCI_SETINT_SET_TX_INT BSP_BIT32(8) + +/* field: SET_WAKEUP_INT - Set wakeup interrupt. */ +#define TMS570_SCI_SETINT_SET_WAKEUP_INT BSP_BIT32(1) + +/* field: SET_BRKDT_INT - Set breakdetect interrupt. */ +#define TMS570_SCI_SETINT_SET_BRKDT_INT BSP_BIT32(0) + + +/*--------------------TMS570_SCI_CLEARINT--------------------*/ +/* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_FE_INT BSP_BIT32(26) + +/* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_CE_INT BSP_BIT32(25) + +/* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_PE_INT BSP_BIT32(24) + +/* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */ +#define TMS570_SCI_CLEARINT_CLR_RX_DMA_ALL BSP_BIT32(18) + +/* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */ +#define TMS570_SCI_CLEARINT_CLR_RX_DMA BSP_BIT32(17) + +/* field: CLR_TX_DMA - CLR TX DMA */ +#define TMS570_SCI_CLEARINT_CLR_TX_DMA BSP_BIT32(16) + +/* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_RX_INT BSP_BIT32(9) + +/* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_TX_INT BSP_BIT32(8) + +/* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_WAKEUP_INT BSP_BIT32(1) + +/* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_BRKDT_INT BSP_BIT32(0) + + +/*--------------------TMS570_SCI_SETINTLVL--------------------*/ +/* field: SET_FE_INT_LVL - Set framing-error interrupt level. */ +#define TMS570_SCI_SETINTLVL_SET_FE_INT_LVL BSP_BIT32(26) + +/* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */ +#define TMS570_SCI_SETINTLVL_SET_CE_INT_LVL BSP_BIT32(25) + +/* field: SET_PE_INT_LVL - Set parity error interrupt level. */ +#define TMS570_SCI_SETINTLVL_SET_PE_INT_LVL BSP_BIT32(24) + +/* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */ +#define TMS570_SCI_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_BIT32(18) + +/* field: SET_RX_INT_LVL - Set receiver interrupt level. */ +#define TMS570_SCI_SETINTLVL_SET_RX_INT_LVL BSP_BIT32(9) + +/* field: SET_TX_INT_LVL - Set transmitter interrupt level. */ +#define TMS570_SCI_SETINTLVL_SET_TX_INT_LVL BSP_BIT32(8) + +/* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */ +#define TMS570_SCI_SETINTLVL_SET_WAKEUP_INT_LVL BSP_BIT32(1) + +/* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */ +#define TMS570_SCI_SETINTLVL_SET_BRKDT_INT_LVL BSP_BIT32(0) + + +/*-------------------TMS570_SCI_CLEARINTLVL-------------------*/ +/* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */ +#define TMS570_SCI_CLEARINTLVL_CLR_FE_INT_LVL BSP_BIT32(26) + +/* field: CLR_CE_INT_LVL - CLR CE INT LVL */ +#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25) + +/* field: CLR_CE_INT_LVL - CLR CE INT LVL */ +#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25) + +/* field: CLR_PE_INT_LVL - */ +#define TMS570_SCI_CLEARINTLVL_CLR_PE_INT_LVL BSP_BIT32(24) + +/* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */ +#define TMS570_SCI_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_BIT32(18) + +/* field: CLR_RX_INT_LVL - Clear receiver interrupt. */ +#define TMS570_SCI_CLEARINTLVL_CLR_RX_INT_LVL BSP_BIT32(9) + +/* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */ +#define TMS570_SCI_CLEARINTLVL_8 BSP_BIT32(8) + +/* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */ +#define TMS570_SCI_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_BIT32(1) + +/* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */ +#define TMS570_SCI_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_BIT32(0) + + +/*-----------------------TMS570_SCI_FLR-----------------------*/ +/* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */ +#define TMS570_SCI_FLR_FE BSP_BIT32(26) + +/* field: OE - Overrun error flag. */ +#define TMS570_SCI_FLR_OE BSP_BIT32(25) + +/* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */ +#define TMS570_SCI_FLR_PE BSP_BIT32(24) + +/* field: RXWAKE - Receiver wakeup detect flag. */ +#define TMS570_SCI_FLR_RXWAKE BSP_BIT32(12) + +/* field: TX_EMPTY - Transmitter empty flag. */ +#define TMS570_SCI_FLR_TX_EMPTY BSP_BIT32(11) + +/* field: TXWAKE - Transmitter wakeup method select. */ +#define TMS570_SCI_FLR_TXWAKE BSP_BIT32(10) + +/* field: RXRDY - Receiver ready flag. */ +#define TMS570_SCI_FLR_RXRDY BSP_BIT32(9) + +/* field: TXRDY - Transmitter buffer register ready flag. */ +#define TMS570_SCI_FLR_TXRDY BSP_BIT32(8) + +/* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */ +#define TMS570_SCI_FLR_BUSY BSP_BIT32(3) + +/* field: IDLE - SCI receiver in idle state. */ +#define TMS570_SCI_FLR_IDLE BSP_BIT32(2) + +/* field: WAKEUP - Wakeup flag. */ +#define TMS570_SCI_FLR_WAKEUP BSP_BIT32(1) + +/* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */ +#define TMS570_SCI_FLR_BRKDT BSP_BIT32(0) + + +/*--------------------TMS570_SCI_INTVECT0--------------------*/ +/* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */ +#define TMS570_SCI_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3) +#define TMS570_SCI_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SCI_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SCI_INTVECT1--------------------*/ +/* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */ +#define TMS570_SCI_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3) +#define TMS570_SCI_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SCI_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_SCI_FORMAT---------------------*/ +/* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */ +#define TMS570_SCI_FORMAT_CHAR(val) BSP_FLD32(val,0, 2) +#define TMS570_SCI_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_SCI_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------------TMS570_SCI_BRS-----------------------*/ +/* field: BAUD - SCI 24-bit baud selection. */ +#define TMS570_SCI_BRS_BAUD(val) BSP_FLD32(val,0, 23) +#define TMS570_SCI_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_SCI_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*-----------------------TMS570_SCI_ED-----------------------*/ +/* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */ +#define TMS570_SCI_ED_ED(val) BSP_FLD32(val,0, 7) +#define TMS570_SCI_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SCI_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SCI_RD-----------------------*/ +/* field: RD - Receiver data. */ +#define TMS570_SCI_RD_RD(val) BSP_FLD32(val,0, 7) +#define TMS570_SCI_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SCI_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SCI_TD-----------------------*/ +/* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */ +#define TMS570_SCI_TD_TD(val) BSP_FLD32(val,0, 7) +#define TMS570_SCI_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SCI_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_SCI_PIO0----------------------*/ +/* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */ +#define TMS570_SCI_PIO0_TX_FUNC BSP_BIT32(2) + +/* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */ +#define TMS570_SCI_PIO0_RX_FUNC BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO1----------------------*/ +/* field: TX_DIR - Transmit pin direction. */ +#define TMS570_SCI_PIO1_TX_DIR BSP_BIT32(2) + +/* field: RX_DIR - Receive pin direction. */ +#define TMS570_SCI_PIO1_RX_DIR BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO2----------------------*/ +/* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */ +#define TMS570_SCI_PIO2_TX_IN BSP_BIT32(2) + +/* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */ +#define TMS570_SCI_PIO2_RX_IN BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO3----------------------*/ +/* field: TX_OUT - Transmit pin out. */ +#define TMS570_SCI_PIO3_TX_OUT BSP_BIT32(2) + +/* field: RX_OUT - Receive pin out. */ +#define TMS570_SCI_PIO3_RX_OUT BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO4----------------------*/ +/* field: TX_SET - Transmit pin set. */ +#define TMS570_SCI_PIO4_TX_SET BSP_BIT32(2) + +/* field: RX_SET - Receive pin set. */ +#define TMS570_SCI_PIO4_RX_SET BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO5----------------------*/ +/* field: TX_CLR - Transmit pin clear. */ +#define TMS570_SCI_PIO5_TX_CLR BSP_BIT32(2) + +/* field: RX_CLR - Receive pin clear. */ +#define TMS570_SCI_PIO5_RX_CLR BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO6----------------------*/ +/* field: TX_PDR - Transmit pin open drain enable. */ +#define TMS570_SCI_PIO6_TX_PDR BSP_BIT32(2) + +/* field: RX_PDR - Receive pin open drain enable. */ +#define TMS570_SCI_PIO6_RX_PDR BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO7----------------------*/ +/* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */ +#define TMS570_SCI_PIO7_TX_PD BSP_BIT32(2) + +/* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */ +#define TMS570_SCI_PIO7_RX_PD BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO8----------------------*/ +/* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */ +#define TMS570_SCI_PIO8_TX_PSL BSP_BIT32(2) + +/* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */ +#define TMS570_SCI_PIO8_RX_PSL BSP_BIT32(1) + + +/*--------------------TMS570_SCI_IODFTCTRL--------------------*/ +/* field: FEN - Frame error enable. This bit is used to create a frame error. */ +#define TMS570_SCI_IODFTCTRL_FEN BSP_BIT32(26) + +/* field: PEN - Parity error enable. This bit is used to create a parity error. */ +#define TMS570_SCI_IODFTCTRL_PEN BSP_BIT32(25) + +/* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */ +#define TMS570_SCI_IODFTCTRL_BRKD_TENA BSP_BIT32(24) + +/* field: PIN_SAMPLE_MASK - Pin sample mask. */ +#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20) +#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_GET(reg) BSP_FLD32GET(reg,19, 20) +#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_SET(reg,val) BSP_FLD32SET(reg, val,19, 20) + +/* field: TX_SHIFT - Transmit shift. */ +#define TMS570_SCI_IODFTCTRL_TX_SHIFT(val) BSP_FLD32(val,16, 18) +#define TMS570_SCI_IODFTCTRL_TX_SHIFT_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_SCI_IODFTCTRL_TX_SHIFT_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: IODFTENA - IODFT enable key. Write access permitted in Privilege mode only. */ +#define TMS570_SCI_IODFTCTRL_IODFTENA(val) BSP_FLD32(val,8, 11) +#define TMS570_SCI_IODFTCTRL_IODFTENA_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_SCI_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */ +#define TMS570_SCI_IODFTCTRL_LPBENA BSP_BIT32(1) + +/* field: RXPENA - Module analog loopback through receive pin enable. */ +#define TMS570_SCI_IODFTCTRL_RXPENA BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_SCI */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h new file mode 100644 index 0000000000..35335c61e0 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h @@ -0,0 +1,918 @@ +/* The header file is generated by make_header.py from SPI.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_SPI +#define LIBBSP_ARM_TMS570_SPI + +#include + +typedef struct{ + uint32_t GCR0; /*SPI Global Control Register 0*/ + uint32_t GCR1; /*SPI Global Control Register 1*/ + uint32_t INT0; /*SPI Interrupt Register*/ + uint32_t LVL; /*SPI Interrupt Level Register*/ + uint32_t FLG; /*SPI Flag Register*/ + uint32_t PC0; /*SPI Pin Control Register 0*/ + uint32_t PC1; /*SPI Pin Control Register 1*/ + uint32_t PC2; /*SPI Pin Control Register 2*/ + uint32_t PC3; /*SPI Pin Control Register 3*/ + uint32_t PC4; /*SPI Pin Control Register 4*/ + uint32_t PC5; /*SPI Pin Control Register 5*/ + uint32_t PC6; /*SPI Pin Control Register 6*/ + uint32_t PC7; /*SPI Pin Control Register 7*/ + uint32_t PC8; /*SPI Pin Control Register 8*/ + uint32_t DAT0; /*SPI Transmit Data Register 0*/ + uint32_t DAT1; /*SPI Transmit Data Register 1*/ + uint32_t BUF; /*SPI Receive Buffer Register*/ + uint32_t EMU; /*SPI Emulation Register*/ + uint32_t DELAY; /*SPI Delay Register*/ + uint32_t DEF; /*SPI Default Chip Select Register*/ + uint32_t FMT0; /*SPI Data Format Register 0*/ + uint32_t FMT1; /*SPI Data Format Register 1*/ + uint32_t FMT2; /*SPI Data Format Register 2*/ + uint32_t FMT3; /*SPI Data Format Register 3*/ + uint32_t INTVECT0; /*Interrupt Vector 0*/ + uint32_t INTVECT1; /*Interrupt Vector 1*/ + uint8_t reserved1 [4]; + uint32_t PMCTRL; /*Parallel/Modulo Mode Control Register*/ + uint32_t MIBSPIE; /*Multi-buffer Mode Enable Register*/ + uint32_t TGITENST; /*TG Interrupt Enable Set Register*/ + uint32_t TGITENCR; /*TG Interrupt Enable Clear Register*/ + uint32_t TGITLVST; /*Transfer Group Interrupt Level Set Register*/ + uint32_t TGITLVCR; /*Transfer Group Interrupt Level Clear Register*/ + uint32_t TGINTFLG; /*Transfer Group Interrupt Flag Register*/ + uint8_t reserved2 [8]; + uint32_t TICKCNT; /*Tick Count Register*/ + uint32_t LTGPEND; /*Last TG End Pointer*/ + uint32_t TGCTRL[16]; /*TG Control Registers*/ + uint32_t DMACTRL[8]; /*DMA Channel Control Register*/ + uint32_t DMACOUNT[8]; /*DMA COUNT Register*/ + uint32_t DMACNTLEN; /*DMA Large Count*/ + uint8_t reserved3 [4]; + uint32_t UERRCTRL; /*Multi-buffer RAM Uncorrectable Parity Error Control Register*/ + uint32_t UERRSTAT; /*Multi-buffer RAM Uncorrectable Parity Error Status Register*/ + uint32_t UERRADDRRX; /*RXRAM Uncorrectable Parity Error Address Register*/ + uint32_t UERRADDRTX; /*TXRAM Uncorrectable Parity Error Address Register*/ + uint32_t RXOVRN_BUF_ADDR; /*RXRAM Overrun Buffer Address Register*/ + uint32_t IOLPBKTSTCR; /*I/O Loopback Test Control Register*/ + uint32_t EXT_PRESCALE1; /*SPI Extended Prescale Register 1*/ + uint32_t EXT_PRESCALE2; /*SPI Extended Prescale Register 2*/ +} tms570_spi_t; + + +/*----------------------TMS570_SPI_GCR0----------------------*/ +/* field: nRESET - This is the local reset control for the module. */ +#define TMS570_SPI_GCR0_nRESET BSP_BIT32(0) + + +/*----------------------TMS570_SPI_GCR1----------------------*/ +/* field: SPIEN - SPI enable. This bit enables SPI transfers. */ +#define TMS570_SPI_GCR1_SPIEN BSP_BIT32(24) + +/* field: LOOPBACK - Internal loop-back test mode. The internal self-test option can be enabled by setting this bit. */ +#define TMS570_SPI_GCR1_LOOPBACK BSP_BIT32(16) + +/* field: POWERDOWN - When active, the SPI state machine enters a power-down state. */ +#define TMS570_SPI_GCR1_POWERDOWN BSP_BIT32(8) + +/* field: CLKMOD - Clock mode. This bit selects either an internal or external clock source. */ +#define TMS570_SPI_GCR1_CLKMOD BSP_BIT32(1) + +/* field: MASTER - SPISIMO/SPISOMI pin direction determination. */ +#define TMS570_SPI_GCR1_MASTER BSP_BIT32(0) + + +/*----------------------TMS570_SPI_INT0----------------------*/ +/* field: ENABLEHIGHZ - SPIENA pin high-impedance enable. */ +#define TMS570_SPI_INT0_ENABLEHIGHZ BSP_BIT32(24) + +/* field: DMAREQEN - DMA request enable. */ +#define TMS570_SPI_INT0_DMAREQEN BSP_BIT32(16) + + +/*-----------------------TMS570_SPI_LVL-----------------------*/ +/* field: TXINTLVL - Transmit interrupt level. */ +#define TMS570_SPI_LVL_TXINTLVL BSP_BIT32(9) + +/* field: RXINTLVL - Receive interrupt level. */ +#define TMS570_SPI_LVL_RXINTLVL BSP_BIT32(8) + +/* field: RXOVRNINTLVL - Receive overrun interrupt level. */ +#define TMS570_SPI_LVL_RXOVRNINTLVL BSP_BIT32(6) + +/* field: BITERRLVL - Bit error interrupt level. */ +#define TMS570_SPI_LVL_BITERRLVL BSP_BIT32(4) + +/* field: DESYNCLVL - Desynchronized slave interrupt level. (master mode only). */ +#define TMS570_SPI_LVL_DESYNCLVL BSP_BIT32(3) + +/* field: PARERRLVL - Parity error interrupt level. */ +#define TMS570_SPI_LVL_PARERRLVL BSP_BIT32(2) + +/* field: TIMEOUTLVL - SPIENA pin time-out interrupt level. */ +#define TMS570_SPI_LVL_TIMEOUTLVL BSP_BIT32(1) + +/* field: DLENERRLVL - Data length error interrupt level (line) select. */ +#define TMS570_SPI_LVL_DLENERRLVL BSP_BIT32(0) + + +/*-----------------------TMS570_SPI_FLG-----------------------*/ +/* field: BUFINITACTIVE - Indicates the status of multi-buffer initialization process. */ +#define TMS570_SPI_FLG_BUFINITACTIVE BSP_BIT32(24) + +/* field: TXINTFLG - Transmitter-empty interrupt flag. */ +#define TMS570_SPI_FLG_TXINTFLG BSP_BIT32(9) + +/* field: RXINTFLG - Receiver-full interrupt flag. */ +#define TMS570_SPI_FLG_RXINTFLG BSP_BIT32(8) + +/* field: RXOVRNINTFLG - Receiver overrun flag. */ +#define TMS570_SPI_FLG_RXOVRNINTFLG BSP_BIT32(6) + +/* field: BITERRFLG - Mismatch of internal transmit data and transmitted data. */ +#define TMS570_SPI_FLG_BITERRFLG BSP_BIT32(4) + +/* field: DESYNCFLG - Desynchronization of slave device. */ +#define TMS570_SPI_FLG_DESYNCFLG BSP_BIT32(3) + +/* field: PARITYERRFLG - Calculated parity differs from received parity bit. */ +#define TMS570_SPI_FLG_PARITYERRFLG BSP_BIT32(2) + +/* field: TIMEOUTFLG - Time-out caused by nonactivation of ENA signal. */ +#define TMS570_SPI_FLG_TIMEOUTFLG BSP_BIT32(1) + +/* field: DLENERRFLG - Data-length error flag. */ +#define TMS570_SPI_FLG_DLENERRFLG BSP_BIT32(0) + + +/*-----------------------TMS570_SPI_PC0-----------------------*/ +/* field: SOMIFUN - Slave out, master in function. */ +#define TMS570_SPI_PC0_SOMIFUN(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC0_SOMIFUN_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC0_SOMIFUN_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMOFUN - Slave in, master out function. */ +#define TMS570_SPI_PC0_SIMOFUN(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC0_SIMOFUN_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC0_SIMOFUN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIFUN0 - SOMIFUN0 */ +#define TMS570_SPI_PC0_SOMIFUN0 BSP_BIT32(11) + +/* field: SIMOFUN0 - Slave in, master out function. */ +#define TMS570_SPI_PC0_SIMOFUN0 BSP_BIT32(10) + +/* field: CLKFUN - CLKFUN */ +#define TMS570_SPI_PC0_CLKFUN BSP_BIT32(9) + +/* field: ENAFUN - SPIENA function. */ +#define TMS570_SPI_PC0_ENAFUN BSP_BIT32(8) + +/* field: SCSFUN - SPISCSx function. */ +#define TMS570_SPI_PC0_SCSFUN(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC0_SCSFUN_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC0_SCSFUN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC1-----------------------*/ +/* field: SOMIDIR - SPISOMIx direction. Controls the direction of SPISOMIx when used for general-purpose I/O. */ +#define TMS570_SPI_PC1_SOMIDIR(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC1_SOMIDIR_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC1_SOMIDIR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMODIR - SPISIMOx direction. Controls the direction of SPISIMOx when used for general-purpose I/O. */ +#define TMS570_SPI_PC1_SIMODIR(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC1_SIMODIR_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC1_SIMODIR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIDIR0 - PISOMI0 direction. */ +#define TMS570_SPI_PC1_SOMIDIR0 BSP_BIT32(11) + +/* field: SIMODIR0 - SPISIMO0 direction. */ +#define TMS570_SPI_PC1_SIMODIR0 BSP_BIT32(10) + +/* field: CLKDIR - SPICLK direction. */ +#define TMS570_SPI_PC1_CLKDIR BSP_BIT32(9) + +/* field: ENADIR - SPIENA direction. */ +#define TMS570_SPI_PC1_ENADIR BSP_BIT32(8) + +/* field: SCSDIR - SPISCSx direction. */ +#define TMS570_SPI_PC1_SCSDIR(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC1_SCSDIR_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC1_SCSDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC2-----------------------*/ +/* field: SOMIDIN - SPISOMIx data in. The value of the SPISOMIx pins. */ +#define TMS570_SPI_PC2_SOMIDIN(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC2_SOMIDIN_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC2_SOMIDIN_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMODIN - SPISIMOx data in. The value of the SPISIMOx pins. */ +#define TMS570_SPI_PC2_SIMODIN(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC2_SIMODIN_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC2_SIMODIN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIDIN0 - SPISOMI0 data in. The value of the SPISOMI0 pin. */ +#define TMS570_SPI_PC2_SOMIDIN0 BSP_BIT32(11) + +/* field: SIMODIN0 - SPISIMO0 data in. The value of the SPISIMO0 pin. */ +#define TMS570_SPI_PC2_SIMODIN0 BSP_BIT32(10) + +/* field: CLKDIN - Clock data in. The value of the SPICLK pin. pin. */ +#define TMS570_SPI_PC2_CLKDIN BSP_BIT32(9) + +/* field: ENADIN - SPIENA data in. The the value of the SPIENA pin. */ +#define TMS570_SPI_PC2_ENADIN BSP_BIT32(8) + +/* field: SCSDIN - SPISCSx data in. The value of the SPISCSx pin. */ +#define TMS570_SPI_PC2_SCSDIN(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC2_SCSDIN_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC2_SCSDIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC3-----------------------*/ +/* field: SOMIDOUT - SPISOMIx data out write. */ +#define TMS570_SPI_PC3_SOMIDOUT(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC3_SOMIDOUT_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC3_SOMIDOUT_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMODOUT - SPISIMOx data out write. */ +#define TMS570_SPI_PC3_SIMODOUT(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC3_SIMODOUT_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC3_SIMODOUT_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIDOUT0 - SPISOMI0 data out write. */ +#define TMS570_SPI_PC3_SOMIDOUT0 BSP_BIT32(11) + +/* field: SIMODOUT0 - SPISIMO0 data out write. */ +#define TMS570_SPI_PC3_SIMODOUT0 BSP_BIT32(10) + +/* field: CLKDOUT - SPICLK data out write. */ +#define TMS570_SPI_PC3_CLKDOUT BSP_BIT32(9) + +/* field: ENADOUT - SPIENA data out write. */ +#define TMS570_SPI_PC3_ENADOUT BSP_BIT32(8) + +/* field: SCSDOUT - SPISCSx data out write. */ +#define TMS570_SPI_PC3_SCSDOUT(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC3_SCSDOUT_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC3_SCSDOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC4-----------------------*/ +/* field: SOMISET - SPISOMIx data out set. */ +#define TMS570_SPI_PC4_SOMISET(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC4_SOMISET_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC4_SOMISET_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMOSET - SPISIMOx data out set. */ +#define TMS570_SPI_PC4_SIMOSET(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC4_SIMOSET_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC4_SIMOSET_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMISET0 - SPISOMI0 data out set. */ +#define TMS570_SPI_PC4_SOMISET0 BSP_BIT32(11) + +/* field: SIMOSET0 - purpose */ +#define TMS570_SPI_PC4_SIMOSET0 BSP_BIT32(10) + +/* field: CLKSET - SPICLK data out set. */ +#define TMS570_SPI_PC4_CLKSET BSP_BIT32(9) + +/* field: ENASET - SPIENA data out set. */ +#define TMS570_SPI_PC4_ENASET BSP_BIT32(8) + +/* field: SCSSET - SPISCSx data out set. */ +#define TMS570_SPI_PC4_SCSSET(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC4_SCSSET_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC4_SCSSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC5-----------------------*/ +/* field: SOMICLR - SPISOMIx data out clear. */ +#define TMS570_SPI_PC5_SOMICLR(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC5_SOMICLR_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC5_SOMICLR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMOCLR - SPISIMOx data out clear. */ +#define TMS570_SPI_PC5_SIMOCLR(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC5_SIMOCLR_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC5_SIMOCLR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMICLR0 - SPISOMI0 data out cleart. */ +#define TMS570_SPI_PC5_SOMICLR0 BSP_BIT32(11) + +/* field: SIMOCLR0 - SPISIMO0 data out clear. */ +#define TMS570_SPI_PC5_SIMOCLR0 BSP_BIT32(10) + +/* field: CLKCLR - SPICLK data out clear. */ +#define TMS570_SPI_PC5_CLKCLR BSP_BIT32(9) + +/* field: ENACLR - SPIENA data out clear. */ +#define TMS570_SPI_PC5_ENACLR BSP_BIT32(8) + +/* field: SCSCLR - SPISCSx data out clear. */ +#define TMS570_SPI_PC5_SCSCLR(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC5_SCSCLR_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC5_SCSCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC6-----------------------*/ +/* field: SOMIPDR - SPISOMIx open drain enable. */ +#define TMS570_SPI_PC6_SOMIPDR(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC6_SOMIPDR_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC6_SOMIPDR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMOPDR - SPISIMOx open drain enable. */ +#define TMS570_SPI_PC6_SIMOPDR(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC6_SIMOPDR_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC6_SIMOPDR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIPDR0 - SOMI0 open-drain enable. */ +#define TMS570_SPI_PC6_SOMIPDR0 BSP_BIT32(11) + +/* field: SIMOPDR0 - SPISIMO0 open-drain enable. */ +#define TMS570_SPI_PC6_SIMOPDR0 BSP_BIT32(10) + +/* field: CLKPDR - CLK open drain enable. */ +#define TMS570_SPI_PC6_CLKPDR BSP_BIT32(9) + +/* field: ENAPDR - SPIENA pin open drain enable. */ +#define TMS570_SPI_PC6_ENAPDR BSP_BIT32(8) + +/* field: SCSPDR - SPISCSx open drain enable. */ +#define TMS570_SPI_PC6_SCSPDR(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC6_SCSPDR_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC6_SCSPDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC7-----------------------*/ +/* field: SOMIDIS - SOMIx pull control enable/disable. */ +#define TMS570_SPI_PC7_SOMIDIS(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC7_SOMIDIS_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC7_SOMIDIS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMODIS - SIMOx pull control enable/disable. */ +#define TMS570_SPI_PC7_SIMODIS(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC7_SIMODIS_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC7_SIMODIS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIPDIS0 - SPISOMI0 pull control enable/disable. */ +#define TMS570_SPI_PC7_SOMIPDIS0 BSP_BIT32(11) + +/* field: SIMOPDIS0 - SPISIMO0 pull control enable/disable. */ +#define TMS570_SPI_PC7_SIMOPDIS0 BSP_BIT32(10) + +/* field: CLKPDIS - CLK pull control enable/disable. */ +#define TMS570_SPI_PC7_CLKPDIS BSP_BIT32(9) + +/* field: ENAPDIS - ENAPDIS ENABLE pull control enable/disable. */ +#define TMS570_SPI_PC7_ENAPDIS BSP_BIT32(8) + +/* field: SCSPDIS - SCSx pull control enable/disable. */ +#define TMS570_SPI_PC7_SCSPDIS(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC7_SCSPDIS_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC7_SCSPDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC8-----------------------*/ +/* field: SOMIPSEL - SPISOMIx pull select. This bit selects the type of pull logic at the SOMIx pin. */ +#define TMS570_SPI_PC8_SOMIPSEL(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC8_SOMIPSEL_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC8_SOMIPSEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMOPSEL - SIMOPSEL SPISIMOx pull select. This bit selects the type of pull logic at the SPISIMOx pin. */ +#define TMS570_SPI_PC8_SIMOPSEL(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC8_SIMOPSEL_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC8_SIMOPSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIPSEL0 - SOMI pull select. This bit selects the type of pull logic at the SOMI pin. */ +#define TMS570_SPI_PC8_SOMIPSEL0 BSP_BIT32(11) + +/* field: SIMOPSEL0 - SPISIMO pull select. This bit selects the type of pull logic at the SPISIMO pin. */ +#define TMS570_SPI_PC8_SIMOPSEL0 BSP_BIT32(10) + +/* field: CLKPSEL - CLK pull select. This bit selects the type of pull logic at the CLK pin. */ +#define TMS570_SPI_PC8_CLKPSEL BSP_BIT32(9) + +/* field: ENAPSEL - ENABLE pull select. This bit selects the type of pull logic at the ENABLE pin. */ +#define TMS570_SPI_PC8_ENAPSEL BSP_BIT32(8) + +/* field: SCSPSEL - SCSx pull select. This bit selects the type of pull logic at the SCSx pin. */ +#define TMS570_SPI_PC8_SCSPSEL(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC8_SCSPSEL_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC8_SCSPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_SPI_DAT0----------------------*/ +/* field: TXDATA - SPI transmit data. When written, these bits will be copied to the shift register if it is empty. */ +#define TMS570_SPI_DAT0_TXDATA(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_DAT0_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_DAT0_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_SPI_DAT1----------------------*/ +/* field: CSHOLD - Chip select hold mode. */ +#define TMS570_SPI_DAT1_CSHOLD BSP_BIT32(28) + +/* field: WDEL - Enable the delay counter at the end of the current transaction. */ +#define TMS570_SPI_DAT1_WDEL BSP_BIT32(26) + +/* field: DFSEL - Data word format select */ +#define TMS570_SPI_DAT1_DFSEL(val) BSP_FLD32(val,24, 25) +#define TMS570_SPI_DAT1_DFSEL_GET(reg) BSP_FLD32GET(reg,24, 25) +#define TMS570_SPI_DAT1_DFSEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 25) + +/* field: CSNR - Chip select number. CSNR defines the chip-select that will be activated during the data transfer. */ +#define TMS570_SPI_DAT1_CSNR(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_DAT1_CSNR_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_DAT1_CSNR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: TXDATA - ransfer data.When written, these bits are copied to the shift register if it is empty. */ +#define TMS570_SPI_DAT1_TXDATA(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_DAT1_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_DAT1_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-----------------------TMS570_SPI_BUF-----------------------*/ +/* field: RXEMPTY - Receive data buffer empty. */ +#define TMS570_SPI_BUF_RXEMPTY BSP_BIT32(31) + +/* field: RXOVR - Receive data buffer overrun. */ +#define TMS570_SPI_BUF_RXOVR BSP_BIT32(30) + +/* field: TXFULL - Transmit data buffer full.This flag is a read-only flag. */ +#define TMS570_SPI_BUF_TXFULL BSP_BIT32(29) + +/* field: BITERR - Bit error.There was a mismatch of internal transmit data and transmitted data. */ +#define TMS570_SPI_BUF_BITERR BSP_BIT32(28) + +/* field: DESYNC - Desynchronization of slave device.This bit is valid in master mode only. */ +#define TMS570_SPI_BUF_DESYNC BSP_BIT32(27) + +/* field: PARITYERR - Parity error.The calculated parity differs from the received parity bit. */ +#define TMS570_SPI_BUF_PARITYERR BSP_BIT32(26) + +/* field: TIMEOUT - Time-out because of non-activation of ENA pin. */ +#define TMS570_SPI_BUF_TIMEOUT BSP_BIT32(25) + +/* field: DLENERR - Data length error flag. */ +#define TMS570_SPI_BUF_DLENERR BSP_BIT32(24) + +/* field: LCSNR - control field. It contains the chip select number that was activated during the last word transfer. */ +#define TMS570_SPI_BUF_LCSNR(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_BUF_LCSNR_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_BUF_LCSNR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: RXDATA - SPI receive data. */ +#define TMS570_SPI_BUF_RXDATA(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_BUF_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_BUF_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-----------------------TMS570_SPI_EMU-----------------------*/ +/* field: EMU_RXDATA - SPI receive data. The SPI emulation register is a mirror of the SPIBUF register. */ +#define TMS570_SPI_EMU_EMU_RXDATA(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_EMU_EMU_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_EMU_EMU_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_SPI_DELAY----------------------*/ +/* field: C2TDELAY - Chip-select-active to transmit-start delay. See Figure 25-45 for an example. */ +#define TMS570_SPI_DELAY_C2TDELAY(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_DELAY_C2TDELAY_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_DELAY_C2TDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: T2CDELAY - T2CDELAY */ +#define TMS570_SPI_DELAY_T2CDELAY(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_DELAY_T2CDELAY_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_DELAY_T2CDELAY_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: T2EDELAY - Transmit-data-finished to ENA-pin-inactive time-out. T2EDELAY is used in master mode only. */ +#define TMS570_SPI_DELAY_T2EDELAY(val) BSP_FLD32(val,8, 15) +#define TMS570_SPI_DELAY_T2EDELAY_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_SPI_DELAY_T2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: C2EDELAY - Chip-select-active to ENA-signal-active time-out. */ +#define TMS570_SPI_DELAY_C2EDELAY(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_DELAY_C2EDELAY_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_DELAY_C2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_DEF-----------------------*/ +/* field: CDEF - Chip select default pattern. Master-mode only. */ +#define TMS570_SPI_DEF_CDEF(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_DEF_CDEF_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_DEF_CDEF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_SPI_FMTx----------------------*/ +/* field: WDELAY - Delay in between transmissions for data format x (x= 0,1,2,3). */ +#define TMS570_SPI_FMTx_WDELAY(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_FMTx_WDELAY_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_FMTx_WDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: PARPOL - Parity polarity: even or odd. PARPOLx can be modified in privilege mode only. */ +#define TMS570_SPI_FMTx_PARPOL BSP_BIT32(23) + +/* field: PARITYENA - Parity enable for data format x. */ +#define TMS570_SPI_FMTx_PARITYENA BSP_BIT32(22) + +/* field: WAITENA - The master waits for the ENA signal from slave for data format x. */ +#define TMS570_SPI_FMTx_WAITENA BSP_BIT32(21) + +/* field: SHIFTDIR - Shift direction for data format x. */ +#define TMS570_SPI_FMTx_SHIFTDIR BSP_BIT32(20) + +/* field: HDUPLEX_ENAx - Half Duplex transfer mode enable for Data Format x. */ +#define TMS570_SPI_FMTx_HDUPLEX_ENAx BSP_BIT32(19) + +/* field: DIS_CS_TIMERS - Disable chip-select timers for this format. */ +#define TMS570_SPI_FMTx_DIS_CS_TIMERS BSP_BIT32(18) + +/* field: POLARITY - POLARITY */ +#define TMS570_SPI_FMTx_POLARITY BSP_BIT32(17) + +/* field: PHASE - SPI data format x clock delay. PHASEx defines the clock delay of data format x. */ +#define TMS570_SPI_FMTx_PHASE BSP_BIT32(16) + +/* field: PRESCALE - SPI data format x prescaler. */ +#define TMS570_SPI_FMTx_PRESCALE(val) BSP_FLD32(val,8, 15) +#define TMS570_SPI_FMTx_PRESCALE_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_SPI_FMTx_PRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: CHARLEN - SPI data format x data-word length. CHARLENx defines the word length of data format x. */ +#define TMS570_SPI_FMTx_CHARLEN(val) BSP_FLD32(val,0, 4) +#define TMS570_SPI_FMTx_CHARLEN_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_SPI_FMTx_CHARLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*--------------------TMS570_SPI_INTVECT0--------------------*/ +/* field: INTVECT0 - INTVECT0. Interrupt vector for interrupt line INT0. */ +#define TMS570_SPI_INTVECT0_INTVECT0(val) BSP_FLD32(val,1, 5) +#define TMS570_SPI_INTVECT0_INTVECT0_GET(reg) BSP_FLD32GET(reg,1, 5) +#define TMS570_SPI_INTVECT0_INTVECT0_SET(reg,val) BSP_FLD32SET(reg, val,1, 5) + +/* field: SUSPEND0 - Transfer suspended / Transfer finished interrupt flag. */ +#define TMS570_SPI_INTVECT0_SUSPEND0 BSP_BIT32(0) + + +/*--------------------TMS570_SPI_INTVECT1--------------------*/ +/* field: INTVECT1 - INTVECT1. Interrupt vector for interrupt line INT1. */ +#define TMS570_SPI_INTVECT1_INTVECT1(val) BSP_FLD32(val,1, 5) +#define TMS570_SPI_INTVECT1_INTVECT1_GET(reg) BSP_FLD32GET(reg,1, 5) +#define TMS570_SPI_INTVECT1_INTVECT1_SET(reg,val) BSP_FLD32SET(reg, val,1, 5) + +/* field: SUSPEND1 - Transfer suspended / Transfer finished interrupt flag. */ +#define TMS570_SPI_INTVECT1_SUSPEND1 BSP_BIT32(0) + + +/*---------------------TMS570_SPI_PMCTRL---------------------*/ +/* field: MOD_CLK_POL_3 - Modulo mode SPICLK polarity. */ +#define TMS570_SPI_PMCTRL_MOD_CLK_POL_3 BSP_BIT32(29) + +/* field: MMODE_3 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */ +#define TMS570_SPI_PMCTRL_MMODE_3(val) BSP_FLD32(val,26, 28) +#define TMS570_SPI_PMCTRL_MMODE_3_GET(reg) BSP_FLD32GET(reg,26, 28) +#define TMS570_SPI_PMCTRL_MMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,26, 28) + +/* field: PMODE_3 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */ +#define TMS570_SPI_PMCTRL_PMODE_3(val) BSP_FLD32(val,24, 25) +#define TMS570_SPI_PMCTRL_PMODE_3_GET(reg) BSP_FLD32GET(reg,24, 25) +#define TMS570_SPI_PMCTRL_PMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 25) + +/* field: MOD_CLK_POL_2 - Modulo mode SPICLK polarity. */ +#define TMS570_SPI_PMCTRL_MOD_CLK_POL_2 BSP_BIT32(21) + +/* field: MMODE_2 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */ +#define TMS570_SPI_PMCTRL_MMODE_2(val) BSP_FLD32(val,18, 20) +#define TMS570_SPI_PMCTRL_MMODE_2_GET(reg) BSP_FLD32GET(reg,18, 20) +#define TMS570_SPI_PMCTRL_MMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,18, 20) + +/* field: PMODE_2 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */ +#define TMS570_SPI_PMCTRL_PMODE_2(val) BSP_FLD32(val,16, 17) +#define TMS570_SPI_PMCTRL_PMODE_2_GET(reg) BSP_FLD32GET(reg,16, 17) +#define TMS570_SPI_PMCTRL_PMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 17) + +/* field: MOD_CLK_POL_1 - Modulo mode SPICLK polarity. */ +#define TMS570_SPI_PMCTRL_MOD_CLK_POL_1 BSP_BIT32(13) + +/* field: MMODE_1 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */ +#define TMS570_SPI_PMCTRL_MMODE_1(val) BSP_FLD32(val,10, 12) +#define TMS570_SPI_PMCTRL_MMODE_1_GET(reg) BSP_FLD32GET(reg,10, 12) +#define TMS570_SPI_PMCTRL_MMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,10, 12) + +/* field: PMODE_1 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */ +#define TMS570_SPI_PMCTRL_PMODE_1(val) BSP_FLD32(val,8, 9) +#define TMS570_SPI_PMCTRL_PMODE_1_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_SPI_PMCTRL_PMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: MOD_CLK_POL_0 - Modulo mode SPICLK polarity. */ +#define TMS570_SPI_PMCTRL_MOD_CLK_POL_0 BSP_BIT32(5) + +/* field: MMODE_0 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */ +#define TMS570_SPI_PMCTRL_MMODE_0(val) BSP_FLD32(val,2, 4) +#define TMS570_SPI_PMCTRL_MMODE_0_GET(reg) BSP_FLD32GET(reg,2, 4) +#define TMS570_SPI_PMCTRL_MMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,2, 4) + +/* field: PMODE_0 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */ +#define TMS570_SPI_PMCTRL_PMODE_0(val) BSP_FLD32(val,0, 1) +#define TMS570_SPI_PMCTRL_PMODE_0_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_SPI_PMCTRL_PMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_SPI_MIBSPIE---------------------*/ +/* field: RXRAM_ACCESS - Receive-RAM access control. */ +#define TMS570_SPI_MIBSPIE_RXRAM_ACCESS BSP_BIT32(16) + +/* field: MSPIENA - Multi-buffer mode enable. */ +#define TMS570_SPI_MIBSPIE_MSPIENA BSP_BIT32(0) + + +/*--------------------TMS570_SPI_TGITENST--------------------*/ +/* field: SET_INTENRDY - TG interrupt set (enable) when transfer finished. */ +#define TMS570_SPI_TGITENST_SET_INTENRDY(val) BSP_FLD32(val,16, 31) +#define TMS570_SPI_TGITENST_SET_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_SPI_TGITENST_SET_INTENRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: SET_INTENSUS - TG interrupt set (enabled) when transfer suspended */ +#define TMS570_SPI_TGITENST_SET_INTENSUS(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_TGITENST_SET_INTENSUS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_TGITENST_SET_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SPI_TGITENCR--------------------*/ +/* field: CLR_INTENRDY - TG interrupt clear (disabled) when transfer finished. */ +#define TMS570_SPI_TGITENCR_CLR_INTENRDY(val) BSP_FLD32(val,16, 31) +#define TMS570_SPI_TGITENCR_CLR_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_SPI_TGITENCR_CLR_INTENRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: CLR_INTENSUS - CLR INTENSUS */ +#define TMS570_SPI_TGITENCR_CLR_INTENSUS(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_TGITENCR_CLR_INTENSUS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_TGITENCR_CLR_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SPI_TGITLVST--------------------*/ +/* field: SET_INTLVLRDY - Transfer-group completed interrupt level set. */ +#define TMS570_SPI_TGITLVST_SET_INTLVLRDY(val) BSP_FLD32(val,16, 31) +#define TMS570_SPI_TGITLVST_SET_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_SPI_TGITLVST_SET_INTLVLRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: SET_INTLVLSUS - Transfer-group suspended interrupt level set. */ +#define TMS570_SPI_TGITLVST_SET_INTLVLSUS(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_TGITLVST_SET_INTLVLSUS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_TGITLVST_SET_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SPI_TGITLVCR--------------------*/ +/* field: CLR_INTLVLRDY - Transfer-group completed interrupt level clear. */ +#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY(val) BSP_FLD32(val,16, 31) +#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: CLR_INTLVLSUS - Transfer group suspended interrupt level clear. */ +#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SPI_TGINTFLG--------------------*/ +/* field: INTFLGRDY - Transfer-group interrupt flag for a transfer-completed interrupt. */ +#define TMS570_SPI_TGINTFLG_INTFLGRDY(val) BSP_FLD32(val,16, 31) +#define TMS570_SPI_TGINTFLG_INTFLGRDY_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_SPI_TGINTFLG_INTFLGRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: INTFLGSUS - ransfer-group interrupt flag for a transfer-suspend interrupt. */ +#define TMS570_SPI_TGINTFLG_INTFLGSUS(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_TGINTFLG_INTFLGSUS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_TGINTFLG_INTFLGSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_SPI_TICKCNT---------------------*/ +/* field: TICKENA - Tick counter enable. */ +#define TMS570_SPI_TICKCNT_TICKENA BSP_BIT32(31) + +/* field: RELOAD - Pre-load the tick counter. */ +#define TMS570_SPI_TICKCNT_RELOAD BSP_BIT32(30) + +/* field: CLKCTRL - Tick counter clock source control. */ +#define TMS570_SPI_TICKCNT_CLKCTRL(val) BSP_FLD32(val,28, 29) +#define TMS570_SPI_TICKCNT_CLKCTRL_GET(reg) BSP_FLD32GET(reg,28, 29) +#define TMS570_SPI_TICKCNT_CLKCTRL_SET(reg,val) BSP_FLD32SET(reg, val,28, 29) + +/* field: TICKVALUE - counter is loaded with the contents of TICKVALUE every time an underflow condition occurs and */ +#define TMS570_SPI_TICKCNT_TICKVALUE(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_TICKCNT_TICKVALUE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_TICKCNT_TICKVALUE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_SPI_LTGPEND---------------------*/ +/* field: TG_IN_SERVICE - The TG number currently being serviced by the sequencer. */ +#define TMS570_SPI_LTGPEND_TG_IN_SERVICE(val) BSP_FLD32(val,24, 28) +#define TMS570_SPI_LTGPEND_TG_IN_SERVICE_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_SPI_LTGPEND_TG_IN_SERVICE_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: LPEND - Last TG end pointer. */ +#define TMS570_SPI_LTGPEND_LPEND(val) BSP_FLD32(val,8, 14) +#define TMS570_SPI_LTGPEND_LPEND_GET(reg) BSP_FLD32GET(reg,8, 14) +#define TMS570_SPI_LTGPEND_LPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 14) + + +/*---------------------TMS570_SPI_TGCTRL---------------------*/ +/* field: TGENA - TGx enable. */ +#define TMS570_SPI_TGCTRL_TGENA BSP_BIT32(31) + +/* field: ONESHOTx - Single transfer for TGx. */ +#define TMS570_SPI_TGCTRL_ONESHOTx BSP_BIT32(30) + +/* field: PRSTx - TGx pointer reset mode. Configures the way to resolve trigger events during an ongoing transfer. */ +#define TMS570_SPI_TGCTRL_PRSTx BSP_BIT32(29) + +/* field: TGTDx - TG triggered. */ +#define TMS570_SPI_TGCTRL_TGTDx BSP_BIT32(28) + + +/*---------------------TMS570_SPI_DMACTRL---------------------*/ +/* field: ONESHOT - Auto-disable of DMA channel after ICOUNT+1 transfers. */ +#define TMS570_SPI_DMACTRL_ONESHOT BSP_BIT32(31) + +/* field: BUFIDx - Buffer utilized for DMA transfer. */ +#define TMS570_SPI_DMACTRL_BUFIDx(val) BSP_FLD32(val,24, 30) +#define TMS570_SPI_DMACTRL_BUFIDx_GET(reg) BSP_FLD32GET(reg,24, 30) +#define TMS570_SPI_DMACTRL_BUFIDx_SET(reg,val) BSP_FLD32SET(reg, val,24, 30) + +/* field: RXDMA_MAPx - Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA */ +#define TMS570_SPI_DMACTRL_RXDMA_MAPx(val) BSP_FLD32(val,20, 23) +#define TMS570_SPI_DMACTRL_RXDMA_MAPx_GET(reg) BSP_FLD32GET(reg,20, 23) +#define TMS570_SPI_DMACTRL_RXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,20, 23) + +/* field: TXDMA_MAPx - Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA */ +#define TMS570_SPI_DMACTRL_TXDMA_MAPx(val) BSP_FLD32(val,16, 19) +#define TMS570_SPI_DMACTRL_TXDMA_MAPx_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SPI_DMACTRL_TXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: RXDMAENAx - Receive data DMA channel enable. */ +#define TMS570_SPI_DMACTRL_RXDMAENAx BSP_BIT32(15) + +/* field: TXDAMENAx - Transmit data DMA channel enable. */ +#define TMS570_SPI_DMACTRL_TXDAMENAx BSP_BIT32(14) + +/* field: NOBRKx - Non-interleaved DMA block transfer. This bit is available in master mode only. */ +#define TMS570_SPI_DMACTRL_NOBRKx BSP_BIT32(13) + +/* field: ICOUNTx - Initial count of DMA transfers. */ +#define TMS570_SPI_DMACTRL_ICOUNTx(val) BSP_FLD32(val,8, 12) +#define TMS570_SPI_DMACTRL_ICOUNTx_GET(reg) BSP_FLD32GET(reg,8, 12) +#define TMS570_SPI_DMACTRL_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,8, 12) + +/* field: COUNT_BIT17x - The 17th bit of the COUNT field of DMAxCOUNT register. */ +#define TMS570_SPI_DMACTRL_COUNT_BIT17x BSP_BIT32(6) + +/* field: COUNTx - Actual number of remaining DMA transfers. */ +#define TMS570_SPI_DMACTRL_COUNTx(val) BSP_FLD32(val,0, 5) +#define TMS570_SPI_DMACTRL_COUNTx_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_SPI_DMACTRL_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*--------------------TMS570_SPI_DMACOUNT--------------------*/ +/* field: ICOUNTx - Every time COUNTx hits zero, it is reloaded with ICOUNTx. */ +#define TMS570_SPI_DMACOUNT_ICOUNTx(val) BSP_FLD32(val,16, 31) +#define TMS570_SPI_DMACOUNT_ICOUNTx_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_SPI_DMACOUNT_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: COUNTx - The actual number of remaining DMA transfers. */ +#define TMS570_SPI_DMACOUNT_COUNTx(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_DMACOUNT_COUNTx_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_DMACOUNT_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SPI_DMACNTLEN--------------------*/ +/* field: LARGE_COUNT - Select either the 16-bit DMAxCOUNT counters or the smaller counters in DMAxCTRL. */ +#define TMS570_SPI_DMACNTLEN_LARGE_COUNT BSP_BIT32(0) + + +/*--------------------TMS570_SPI_UERRCTRL--------------------*/ +/* field: PTESTEN - Parity memory test enable. */ +#define TMS570_SPI_UERRCTRL_PTESTEN BSP_BIT32(8) + +/* field: EDEN - Error detection enable. These bits enable parity error detection. */ +#define TMS570_SPI_UERRCTRL_EDEN(val) BSP_FLD32(val,0, 3) +#define TMS570_SPI_UERRCTRL_EDEN_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SPI_UERRCTRL_EDEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SPI_UERRSTAT--------------------*/ +/* field: EDFLG1 - RXRAM. */ +#define TMS570_SPI_UERRSTAT_EDFLG1 BSP_BIT32(1) + +/* field: EDFLG0 - Uncorrectable parity error detection flag. */ +#define TMS570_SPI_UERRSTAT_EDFLG0 BSP_BIT32(0) + + +/*-------------------TMS570_SPI_UERRADDRRX-------------------*/ +/* field: OVERADDR1 - Uncorrectable parity error address for RXRAM. */ +#define TMS570_SPI_UERRADDRRX_OVERADDR1(val) BSP_FLD32(val,0, 9) +#define TMS570_SPI_UERRADDRRX_OVERADDR1_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_SPI_UERRADDRRX_OVERADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*-------------------TMS570_SPI_UERRADDRTX-------------------*/ +/* field: UERRADDR0 - a parity error is generated while reading from TXRAM. */ +#define TMS570_SPI_UERRADDRTX_UERRADDR0(val) BSP_FLD32(val,0, 8) +#define TMS570_SPI_UERRADDRTX_UERRADDR0_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_SPI_UERRADDRTX_UERRADDR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*-----------------TMS570_SPI_RXOVRN_BUF_ADDR-----------------*/ +/* field: RXOVRN_BUF_ADDR - Address in RXRAM at which an overwrite occurred. */ +#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR(val) BSP_FLD32(val,0, 9) +#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*-------------------TMS570_SPI_IOLPBKTSTCR-------------------*/ +/* field: SCS_FAIL_FLG - Bit indicating a failure on SPISCS pin compare during analog loopback. */ +#define TMS570_SPI_IOLPBKTSTCR_SCS_FAIL_FLG BSP_BIT32(24) + +/* field: CTRL_BITERR - Controls inducing of BITERR during I/O loopback test mode. */ +#define TMS570_SPI_IOLPBKTSTCR_CTRL_BITERR BSP_BIT32(20) + +/* field: CTRL_DESYNC - Controls inducing of the desync error during I/O loopback test mode. */ +#define TMS570_SPI_IOLPBKTSTCR_CTRL_DESYNC BSP_BIT32(19) + +/* field: CTRL_PARERR - Controls inducing of the parity errors during I/O loopback test mode. */ +#define TMS570_SPI_IOLPBKTSTCR_CTRL_PARERR BSP_BIT32(18) + +/* field: CTRL_TIMEOUT - Controls inducing of the timeout error during I/O loopback test mode. */ +#define TMS570_SPI_IOLPBKTSTCR_CTRL_TIMEOUT BSP_BIT32(17) + +/* field: CTRL_DLENERR - Controls inducing of the data length error during I/O loopback test mode. */ +#define TMS570_SPI_IOLPBKTSTCR_CTRL_DLENERR BSP_BIT32(16) + +/* field: IOLPBKSTENA - Module I/O loopback test enable key. */ +#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA(val) BSP_FLD32(val,8, 11) +#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: ERR_SCS_PIN - Inject error on chip-select pin number x. */ +#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN(val) BSP_FLD32(val,3, 5) +#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_GET(reg) BSP_FLD32GET(reg,3, 5) +#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_SET(reg,val) BSP_FLD32SET(reg, val,3, 5) + +/* field: CTRL_SCS_PIN - Enable/disable the injection of an error on the SPISCS[3:0] pins. */ +#define TMS570_SPI_IOLPBKTSTCR_CTRL_SCS_PIN BSP_BIT32(2) + +/* field: LPBK_TYPE - Module I/O loopback type (analog/digital). */ +#define TMS570_SPI_IOLPBKTSTCR_LPBK_TYPE BSP_BIT32(1) + +/* field: RXP_ENA - Enable analog loopback through the receive pin. */ +#define TMS570_SPI_IOLPBKTSTCR_RXP_ENA BSP_BIT32(0) + + +/*------------------TMS570_SPI_EXT_PRESCALEx------------------*/ +/* field: EPRESCALE_FMTx - EPRESCALE_FMTx. Extended Prescale value for SPIFMTx. */ +#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx(val) BSP_FLD32(val,16, 26) +#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_GET(reg) BSP_FLD32GET(reg,16, 26) +#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 26) + + + +#endif /* LIBBSP_ARM_TMS570_SPI */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h new file mode 100644 index 0000000000..e935f450b8 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h @@ -0,0 +1,158 @@ +/* The header file is generated by make_header.py from STC.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_STC +#define LIBBSP_ARM_TMS570_STC + +#include + +typedef struct{ + uint32_t STCGCR0; /*STC Global Control Register 0*/ + uint32_t STCGCR1; /*STCGlobal Control Register 1*/ + uint32_t STCTPR; /*Self-Test Run Timeout Counter Preload Register*/ + uint32_t STC_CADDR; /*STC Current ROM Address Register*/ + uint32_t STCCICR; /*STC Current Interval Count Register*/ + uint32_t STCGSTAT; /*Self-Test Global Status Register*/ + uint32_t STCFSTAT; /*Self-Test Fail Status Register*/ + uint32_t CPU1_CURMISR3; /*CPU1 Current MISR Register 3*/ + uint32_t CPU1_CURMISR2; /*CPU1 Current MISR Register 2*/ + uint32_t CPU1_CURMISR1; /*CPU1 Current MISR Register 1*/ + uint32_t CPU1_CURMISR0; /*CPU1 Current MISR Register 0*/ + uint32_t CPU2_CURMISR3; /*CPU2 Current MISR Register 3*/ + uint32_t CPU2_CURMISR2; /*CPU2 Current MISR Register 2*/ + uint32_t CPU2_CURMISR1; /*CPU2 Current MISR Register 1*/ + uint32_t CPU2_CURMISR0; /*CPU2 Current MISR Register 0*/ + uint32_t STCSCSCR; /*Signature Compare Self-Check Register*/ +} tms570_stc_t; + + +/*---------------------TMS570_STC_STCGCR0---------------------*/ +/* field: INTCOUNT - Number of intervals of self-test run */ +#define TMS570_STC_STCGCR0_INTCOUNT(val) BSP_FLD32(val,16, 31) +#define TMS570_STC_STCGCR0_INTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_STC_STCGCR0_INTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: RS_CNT - Restart or Continue */ +#define TMS570_STC_STCGCR0_RS_CNT BSP_BIT32(0) + + +/*---------------------TMS570_STC_STCGCR1---------------------*/ +/* field: STC_ENA - Self-test run enable key */ +#define TMS570_STC_STCGCR1_STC_ENA(val) BSP_FLD32(val,0, 3) +#define TMS570_STC_STCGCR1_STC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_STC_STCGCR1_STC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_STC_STCTPR---------------------*/ +/* field: RTOD - Self-test timeout count preload */ +/* Whole 32 bits */ + +/*--------------------TMS570_STC_STC_CADDR--------------------*/ +/* field: ADDR - Current ROM Address */ +/* Whole 32 bits */ + +/*---------------------TMS570_STC_STCCICR---------------------*/ +/* field: N - Interval Number */ +#define TMS570_STC_STCCICR_N(val) BSP_FLD32(val,0, 15) +#define TMS570_STC_STCCICR_N_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_STC_STCCICR_N_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_STC_STCGSTAT--------------------*/ +/* field: TEST_FAIL - Test Fail */ +#define TMS570_STC_STCGSTAT_TEST_FAIL BSP_BIT32(1) + +/* field: TEST_DONE - Test Done */ +#define TMS570_STC_STCGSTAT_TEST_DONE BSP_BIT32(0) + + +/*--------------------TMS570_STC_STCFSTAT--------------------*/ +/* field: TO_ERR - Timeout Error */ +#define TMS570_STC_STCFSTAT_TO_ERR BSP_BIT32(2) + +/* field: CPU2_FAIL - CPU2 failure info */ +#define TMS570_STC_STCFSTAT_CPU2_FAIL BSP_BIT32(1) + +/* field: CPU1_FAIL - CPU1 failure info */ +#define TMS570_STC_STCFSTAT_CPU1_FAIL BSP_BIT32(0) + + +/*------------------TMS570_STC_CPU1_CURMISR3------------------*/ +/* field: MISR - MISR data from CPU1 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU1_CURMISR2------------------*/ +/* field: MISR - MISR data from CPU1 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU1_CURMISR1------------------*/ +/* field: MISR - MISR data from CPU1 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU1_CURMISR0------------------*/ +/* field: MISR - MISR data from CPU1 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU2_CURMISR3------------------*/ +/* field: MISR - MISR data from CPU2 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU2_CURMISR2------------------*/ +/* field: MISR - MISR data from CPU2 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU2_CURMISR1------------------*/ +/* field: MISR - MISR data from CPU2 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU2_CURMISR0------------------*/ +/* field: MISR - MISR data from CPU2 */ +/* Whole 32 bits */ + +/*--------------------TMS570_STC_STCSCSCR--------------------*/ +/* field: FAULT_INS - Enable / Disable fault insertion. */ +#define TMS570_STC_STCSCSCR_FAULT_INS BSP_BIT32(4) + +/* field: SELF_CHECK_KEY - Signature compare logic self-check enable key */ +#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY(val) BSP_FLD32(val,0, 3) +#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + + +#endif /* LIBBSP_ARM_TMS570_STC */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h new file mode 100644 index 0000000000..e191970ad6 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h @@ -0,0 +1,695 @@ +/* The header file is generated by make_header.py from SYS.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_SYS1 +#define LIBBSP_ARM_TMS570_SYS1 + +#include + +typedef struct{ + uint32_t SYSPC1; /*SYS Pin Control Register 1*/ + uint32_t SYSPC2; /*SYS Pin Control Register 2*/ + uint32_t SYSPC3; /*SYS Pin Control Register 3*/ + uint32_t SYSPC4; /*SYS Pin Control Register 4*/ + uint32_t SYSPC5; /*SYS Pin Control Register 5*/ + uint32_t SYSPC6; /*SYS Pin Control Register 6*/ + uint32_t SYSPC7; /*SYS Pin Control Register 7*/ + uint32_t SYSPC8; /*SYS Pin Control Register 8*/ + uint32_t SYSPC9; /*SYS Pin Control Register 9*/ + uint8_t reserved1 [12]; + uint32_t CSDIS; /*Clock Source Disable Register*/ + uint32_t CSDISSET; /*Clock Source Disable Set Register*/ + uint32_t CSDISCLR; /*Clock Source Disable Clear Register*/ + uint32_t CDDIS; /*Clock Domain Disable Register*/ + uint32_t CDDISSET; /*Clock Domain Disable Set Register*/ + uint32_t CDDISCLR; /*Clock Domain Disable Clear Register*/ + uint32_t GHVSRC; /*GCLK, HCLK, VCLK, and VCLK2 Source Register*/ + uint32_t VCLKASRC; /*Peripheral Asynchronous Clock Source Register*/ + uint32_t RCLKSRC; /*RTI Clock Source Register*/ + uint32_t CSVSTAT; /*Clock Source Valid Status Register*/ + uint32_t MSTGCR; /*Memory Self-Test Global Control Register*/ + uint32_t MINITGCR; /*Memory Hardware Initialization Global Control Register*/ + uint32_t MSIENA; /*Memory Self-Test/Initialization Enable Register*/ + uint8_t reserved2 [4]; + uint32_t MSTCGSTAT; /*MSTC Global Status Register*/ + uint32_t MINISTAT; /*Memory Hardware Initialization Status Register*/ + uint32_t PLLCTL1; /*PLL Control Register 1*/ + uint32_t PLLCTL2; /*PLL Control Register 2*/ + uint32_t SYSPC10; /*SYS Pin Control Register 10*/ + uint32_t DIEIDL; /*Die Identification Register, Lower Word*/ + uint32_t DIEIDH; /*Die Identification Register, Upper Word*/ + uint8_t reserved3 [4]; + uint32_t LPOMONCTL; /*LPO/Clock Monitor Control Register*/ + uint32_t CLKTEST; /*Clock Test Register*/ + uint32_t DFTCTRLREG1; /*DFT Control Register*/ + uint32_t DFTCTRLREG2; /*DFT Control Register 2*/ + uint8_t reserved4 [8]; + uint32_t GPREG1; /*General Purpose Register*/ + uint8_t reserved5 [4]; + uint32_t IMPFASTS; /*Imprecise Fault Status Register*/ + uint32_t IMPFTADD; /*Imprecise Fault Write Address Register*/ + uint32_t SSIR1; /*System Software Interrupt Request 1 Register*/ + uint32_t SSIR2; /*System Software Interrupt Request 2 Register*/ + uint32_t SSIR3; /*System Software Interrupt Request 3 Register*/ + uint32_t SSIR4; /*System Software Interrupt Request 4 Register*/ + uint32_t RAMGCR; /*RAM Control Register*/ + uint32_t BMMCR1; /*Bus Matrix Module Control Register 1*/ + uint8_t reserved6 [4]; + uint32_t CPURSTCR; /*CPU Reset Control Register*/ + uint32_t CLKCNTL; /*Clock Control Register*/ + uint32_t ECPCNTL; /*ECP Control Register*/ + uint8_t reserved7 [4]; + uint32_t DEVCR1; /*DEV Parity Control Register 1*/ + uint32_t SYSECR; /*System Exception Control Register*/ + uint32_t SYSESR; /*System Exception Status Register*/ + uint32_t SYSTASR; /*System Test Abort Status Register*/ + uint32_t GLBSTAT; /*Global Status Register*/ + uint32_t DEVID; /*Device Identification Register*/ + uint32_t SSIVEC; /*Software Interrupt Vector Register*/ + uint32_t SSIF; /*System Software Interrupt Flag Register*/ +} tms570_sys1_t; + + +/*---------------------TMS570_SYS1_SYSPCx---------------------*/ +/* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */ +#define TMS570_SYS1_SYSPCx_ECPCLKFUN BSP_BIT32(0) + + +/*---------------------TMS570_SYS1_CSDIS---------------------*/ +/* field: CLKSROFF - Clock source[7-3] off. */ +#define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,3, 7) +#define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: CLKSROFF - Clock source[1-0] off. */ +#define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,0, 1) +#define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_SYS1_CSDISSET--------------------*/ +/* field: SETCLKSR_OFF - Set clock source[7-3] to the disabled state. */ +#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,3, 7) +#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: SETCLKSR_OFF - Set clock source[1-0] to the disabled state. */ +#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,0, 1) +#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_SYS1_CSDISCLR--------------------*/ +/* field: CLRCLKSR_OFF - Enables clock source[7-3]. */ +#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,3, 7) +#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: CLRCLKSR_OFF - Enables clock source[1-0]. */ +#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,0, 1) +#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_SYS1_CDDIS---------------------*/ +/* field: VCLKAOFF - VCLKA[4-3] domain off. */ +#define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,10, 11) +#define TMS570_SYS1_CDDIS_VCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: VCLK3OFF - VCLK3 domain off. */ +#define TMS570_SYS1_CDDIS_VCLK3OFF BSP_BIT32(8) + +/* field: RTICLK1OFF - RTICLK1 domain off. */ +#define TMS570_SYS1_CDDIS_RTICLK1OFF BSP_BIT32(6) + +/* field: VCLKAOFF - VCLKA[2-1] domain off. */ +#define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,4, 5) +#define TMS570_SYS1_CDDIS_VCLKAOFF_GET(reg) BSP_FLD32GET(reg,4, 5) +#define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,4, 5) + +/* field: VCLK2OFF - VCLK2 domain off. */ +#define TMS570_SYS1_CDDIS_VCLK2OFF BSP_BIT32(3) + +/* field: VCLKPOFF - VCLK_periph domain off. */ +#define TMS570_SYS1_CDDIS_VCLKPOFF BSP_BIT32(2) + +/* field: HCLKOFF - HCLK and VCLK_sys domains off. */ +#define TMS570_SYS1_CDDIS_HCLKOFF BSP_BIT32(1) + +/* field: GCLKOFF - GCLK domain off. */ +#define TMS570_SYS1_CDDIS_GCLKOFF BSP_BIT32(0) + + +/*--------------------TMS570_SYS1_CDDISSET--------------------*/ +/* field: SETVCLKA_OFF - Set VCLKA[4-3] domain. */ +#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF(val) BSP_FLD32(val,10, 11) +#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: SETVCLK3OFF - Set VCLK3 domain. */ +#define TMS570_SYS1_CDDISSET_SETVCLK3OFF BSP_BIT32(8) + +/* field: SETRTI1CLKOFF - Set RTICLK1 domain. */ +#define TMS570_SYS1_CDDISSET_SETRTI1CLKOFF BSP_BIT32(6) + +/* field: SETTVCLKA2OFF - Set VCLKA2 domain. */ +#define TMS570_SYS1_CDDISSET_SETTVCLKA2OFF BSP_BIT32(5) + +/* field: SETVCLKA1OFF - Set VCLKA1 domain. */ +#define TMS570_SYS1_CDDISSET_SETVCLKA1OFF BSP_BIT32(4) + +/* field: SETVCLK2OFF - Set VCLK2 domain. */ +#define TMS570_SYS1_CDDISSET_SETVCLK2OFF BSP_BIT32(3) + +/* field: SETVCLKPOFF - Set VCLK_periph domain. */ +#define TMS570_SYS1_CDDISSET_SETVCLKPOFF BSP_BIT32(2) + +/* field: SETHCLKOFF - Set HCLK and VCLK_sys domains. */ +#define TMS570_SYS1_CDDISSET_SETHCLKOFF BSP_BIT32(1) + +/* field: SETGCLKOFF - Set GCLK domain. */ +#define TMS570_SYS1_CDDISSET_SETGCLKOFF BSP_BIT32(0) + + +/*--------------------TMS570_SYS1_CDDISCLR--------------------*/ +/* field: CLRVCLKAOFF - Clear VCLKA[4-3] domain. */ +#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF(val) BSP_FLD32(val,10, 11) +#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: Reserved - Reserved */ +#define TMS570_SYS1_CDDISCLR_Reserved BSP_BIT32(9) + +/* field: CLRVCLK3OFF - Clear VCLK3 domain. */ +#define TMS570_SYS1_CDDISCLR_CLRVCLK3OFF BSP_BIT32(8) + +/* field: CLRRTI1CLKOFF - Clear RTICLK1 domain. */ +#define TMS570_SYS1_CDDISCLR_CLRRTI1CLKOFF BSP_BIT32(6) + +/* field: CLRTVCLKA2OFF - Clear VCLKA2 domain. */ +#define TMS570_SYS1_CDDISCLR_CLRTVCLKA2OFF BSP_BIT32(5) + +/* field: CLRVCLKA1OFF - Clear VCLKA1 domain. */ +#define TMS570_SYS1_CDDISCLR_CLRVCLKA1OFF BSP_BIT32(4) + +/* field: CLRVCLK2OFF - Clear VCLK2 domain. */ +#define TMS570_SYS1_CDDISCLR_CLRVCLK2OFF BSP_BIT32(3) + +/* field: CLRVCLKPOFF - CLRVCLKPOFF */ +#define TMS570_SYS1_CDDISCLR_CLRVCLKPOFF BSP_BIT32(2) + +/* field: CLRHCLKOFF - Clear HCLK and VCLK_sys domains. */ +#define TMS570_SYS1_CDDISCLR_CLRHCLKOFF BSP_BIT32(1) + +/* field: CLRGCLKOFF - Clear GCLK domain. */ +#define TMS570_SYS1_CDDISCLR_CLRGCLKOFF BSP_BIT32(0) + + +/*---------------------TMS570_SYS1_GHVSRC---------------------*/ +/* field: GHVWAKE - GCLK, HCLK, VCLK, VCLK2 source on wakeup. */ +#define TMS570_SYS1_GHVSRC_GHVWAKE(val) BSP_FLD32(val,24, 27) +#define TMS570_SYS1_GHVSRC_GHVWAKE_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_SYS1_GHVSRC_GHVWAKE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: HVLPM - HCLK, VCLK, VCLK2 source on wakeup when GCLK is turned off. */ +#define TMS570_SYS1_GHVSRC_HVLPM(val) BSP_FLD32(val,16, 19) +#define TMS570_SYS1_GHVSRC_HVLPM_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SYS1_GHVSRC_HVLPM_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: GHVSRC - GCLK, HCLK, VCLK, VCLK2 current source. */ +#define TMS570_SYS1_GHVSRC_GHVSRC(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_GHVSRC_GHVSRC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_GHVSRC_GHVSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SYS1_VCLKASRC--------------------*/ +/* field: VCLKA2S - Peripheral asynchronous clock2 source. */ +#define TMS570_SYS1_VCLKASRC_VCLKA2S(val) BSP_FLD32(val,8, 11) +#define TMS570_SYS1_VCLKASRC_VCLKA2S_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_SYS1_VCLKASRC_VCLKA2S_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: VCLKA1S - Peripheral asynchronous clock1 source. */ +#define TMS570_SYS1_VCLKASRC_VCLKA1S(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_VCLKASRC_VCLKA1S_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_VCLKASRC_VCLKA1S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SYS1_RCLKSRC--------------------*/ +/* field: RTI1DIV - RTI clock1 Divider. */ +#define TMS570_SYS1_RCLKSRC_RTI1DIV(val) BSP_FLD32(val,8, 9) +#define TMS570_SYS1_RCLKSRC_RTI1DIV_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_SYS1_RCLKSRC_RTI1DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: RTI1SRC - RTI clock1 source. */ +#define TMS570_SYS1_RCLKSRC_RTI1SRC(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_RCLKSRC_RTI1SRC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_RCLKSRC_RTI1SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SYS1_CSVSTAT--------------------*/ +/* field: CLKSRV - Clock source[7-0] valid. */ +#define TMS570_SYS1_CSVSTAT_CLKSRV(val) BSP_FLD32(val,3, 7) +#define TMS570_SYS1_CSVSTAT_CLKSRV_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_SYS1_CSVSTAT_CLKSRV_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: CLKSR - Clock source[1-0] valid. */ +#define TMS570_SYS1_CSVSTAT_CLKSR(val) BSP_FLD32(val,0, 1) +#define TMS570_SYS1_CSVSTAT_CLKSR_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_SYS1_CSVSTAT_CLKSR_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_SYS1_MSTGCR---------------------*/ +/* field: ROM_DIV - Prescaler divider bits for ROM clock source. */ +#define TMS570_SYS1_MSTGCR_ROM_DIV(val) BSP_FLD32(val,8, 9) +#define TMS570_SYS1_MSTGCR_ROM_DIV_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_SYS1_MSTGCR_ROM_DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: MSTGENA - Memory self-test controller global enable key */ +#define TMS570_SYS1_MSTGCR_MSTGENA(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_MSTGCR_MSTGENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_MSTGCR_MSTGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SYS1_MINITGCR--------------------*/ +/* field: MINITGENA - Memory hardware initialization global enable key. */ +#define TMS570_SYS1_MINITGCR_MINITGENA(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_MINITGCR_MINITGENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_MINITGCR_MINITGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_SYS1_MSIENA---------------------*/ +/* field: MSIENA - PBIST controller and memory initialization enable register. */ +/* Whole 32 bits */ + +/*-------------------TMS570_SYS1_MSTCGSTAT-------------------*/ +/* field: MINIDONE - Memory hardware initialization complete status. */ +#define TMS570_SYS1_MSTCGSTAT_MINIDONE BSP_BIT32(8) + +/* field: MSTDONE - Memory self-test run complete status. */ +#define TMS570_SYS1_MSTCGSTAT_MSTDONE BSP_BIT32(0) + + +/*--------------------TMS570_SYS1_MINISTAT--------------------*/ +/* field: MIDONE - Memory hardware initialization status bit. */ +/* Whole 32 bits */ + +/*--------------------TMS570_SYS1_PLLCTL1--------------------*/ +/* field: ROS - Reset on PLL Slip */ +#define TMS570_SYS1_PLLCTL1_ROS BSP_BIT32(31) + +/* field: MASK_SLIP - Mask detection of PLL slip */ +#define TMS570_SYS1_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30) +#define TMS570_SYS1_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30) +#define TMS570_SYS1_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) + +/* field: PLLDIV - PLL Output Clock Divider */ +#define TMS570_SYS1_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28) +#define TMS570_SYS1_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_SYS1_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: ROF - Reset on Oscillator Fail */ +#define TMS570_SYS1_PLLCTL1_ROF BSP_BIT32(23) + +/* field: REFCLKDIV - Reference Clock Divider */ +#define TMS570_SYS1_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21) +#define TMS570_SYS1_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21) +#define TMS570_SYS1_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) + +/* field: PLLMUL - PLL Multiplication Factor */ +#define TMS570_SYS1_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15) +#define TMS570_SYS1_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SYS1_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SYS1_PLLCTL2--------------------*/ +/* field: FMENA - Frequency Modulation Enable. */ +#define TMS570_SYS1_PLLCTL2_FMENA BSP_BIT32(31) + +/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */ +#define TMS570_SYS1_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30) +#define TMS570_SYS1_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30) +#define TMS570_SYS1_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30) + +/* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */ +#define TMS570_SYS1_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20) +#define TMS570_SYS1_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20) +#define TMS570_SYS1_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20) + +/* field: ODPLL - Internal PLL Output Divider. */ +#define TMS570_SYS1_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11) +#define TMS570_SYS1_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11) +#define TMS570_SYS1_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11) + +/* field: SPR_AMOUNT - Spreading Amount. */ +#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8) +#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*--------------------TMS570_SYS1_SYSPC10--------------------*/ +/* field: ECPCLK_SLEW - ECPCLK slew control. This bit controls between the fast or slow slew mode. */ +#define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_BIT32(0) + + +/*---------------------TMS570_SYS1_DIEIDL---------------------*/ +/* field: LOT - These read only bits contain the lower 10 bits of the device lot number. */ +#define TMS570_SYS1_DIEIDL_LOT(val) BSP_FLD32(val,22, 31) +#define TMS570_SYS1_DIEIDL_LOT_GET(reg) BSP_FLD32GET(reg,22, 31) +#define TMS570_SYS1_DIEIDL_LOT_SET(reg,val) BSP_FLD32SET(reg, val,22, 31) + +/* field: WAFER - These read only bits contain the wafer number of the device. */ +#define TMS570_SYS1_DIEIDL_WAFER(val) BSP_FLD32(val,16, 21) +#define TMS570_SYS1_DIEIDL_WAFER_GET(reg) BSP_FLD32GET(reg,16, 21) +#define TMS570_SYS1_DIEIDL_WAFER_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) + +/* field: Y_WAFER_COORDINATE - These read only bits contain the Y wafer coordinate of the device */ +#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE(val) BSP_FLD32(val,8, 15) +#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: X_WAFER_COORDINATE - These read only bits contain the X wafer coordinate of the device */ +#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE(val) BSP_FLD32(val,0, 7) +#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_SYS1_DIEIDH---------------------*/ +/* field: LOT - This read-only register contains the upper 14 bits of the device lot number. */ +#define TMS570_SYS1_DIEIDH_LOT(val) BSP_FLD32(val,0, 13) +#define TMS570_SYS1_DIEIDH_LOT_GET(reg) BSP_FLD32GET(reg,0, 13) +#define TMS570_SYS1_DIEIDH_LOT_SET(reg,val) BSP_FLD32SET(reg, val,0, 13) + + +/*-------------------TMS570_SYS1_LPOMONCTL-------------------*/ +/* field: BIAS_ENABLE - Bias enable. */ +#define TMS570_SYS1_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24) + +/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */ +#define TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16) + +/* field: HFTRIM - High frequency oscillator trim value. */ +#define TMS570_SYS1_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12) +#define TMS570_SYS1_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12) +#define TMS570_SYS1_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12) + + +/*--------------------TMS570_SYS1_CLKTEST--------------------*/ +/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */ +#define TMS570_SYS1_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26) + +/* field: RANGEDETCTRL - Range detection control. */ +#define TMS570_SYS1_CLKTEST_RANGEDETCTRL BSP_BIT32(25) + +/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */ +#define TMS570_SYS1_CLKTEST_RANGEDETENASSEL BSP_BIT32(24) + +/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */ +#define TMS570_SYS1_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19) +#define TMS570_SYS1_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SYS1_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: SEL_GIO_PIN - GIOB[0] pin clock source valid, clock source select */ +#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN(val) BSP_FLD32(val,8, 11) +#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: SEL_ECP_PIN - ECLK pin clock source select */ +#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_SYS1_DFTCTRLREG1------------------*/ +/* field: DFTWRITE - DFT logic access. */ +#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE(val) BSP_FLD32(val,12, 13) +#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_GET(reg) BSP_FLD32GET(reg,12, 13) +#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) + +/* field: DFTREAD - DFT logic access. */ +#define TMS570_SYS1_DFTCTRLREG1_DFTREAD(val) BSP_FLD32(val,8, 9) +#define TMS570_SYS1_DFTCTRLREG1_DFTREAD_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_SYS1_DFTCTRLREG1_DFTREAD_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */ +#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_SYS1_DFTCTRLREG2------------------*/ +/* field: IMPDF - DFT Implementation defined bits. */ +#define TMS570_SYS1_DFTCTRLREG2_IMPDF(val) BSP_FLD32(val,4, 31) +#define TMS570_SYS1_DFTCTRLREG2_IMPDF_GET(reg) BSP_FLD32GET(reg,4, 31) +#define TMS570_SYS1_DFTCTRLREG2_IMPDF_SET(reg,val) BSP_FLD32SET(reg, val,4, 31) + +/* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */ +#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_SYS1_GPREG1---------------------*/ +/* field: EMIF_FUNC - Enable EMIF functions to be output. */ +#define TMS570_SYS1_GPREG1_EMIF_FUNC BSP_BIT32(31) + +/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */ +#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25) +#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25) +#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) + +/* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */ +#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19) +#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */ +#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15) +#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SYS1_IMPFASTS--------------------*/ +/* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */ +#define TMS570_SYS1_IMPFASTS_ECPCLKFUN BSP_BIT32(0) + + +/*--------------------TMS570_SYS1_IMPFTADD--------------------*/ +/* field: IMPFTADD - These bits contain the fault address when an imprecise abort occurs. */ +/* Whole 32 bits */ + +/*---------------------TMS570_SYS1_SSIRx---------------------*/ +/* field: SSKEY1 - System software interrupt request key. A 075h written to these bits initiates IRQ/FIQ interrupts. */ +#define TMS570_SYS1_SSIRx_SSKEY1(val) BSP_FLD32(val,8, 15) +#define TMS570_SYS1_SSIRx_SSKEY1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_SYS1_SSIRx_SSKEY1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: SSDATA1 - System software interrupt data. These bits contain user read/write register bits. */ +#define TMS570_SYS1_SSIRx_SSDATA1(val) BSP_FLD32(val,0, 7) +#define TMS570_SYS1_SSIRx_SSDATA1_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SYS1_SSIRx_SSDATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_SYS1_RAMGCR---------------------*/ +/* field: RAM_DFT_EN - Functional mode RAM DFT (Design For Test) port enable key. */ +#define TMS570_SYS1_RAMGCR_RAM_DFT_EN(val) BSP_FLD32(val,16, 19) +#define TMS570_SYS1_RAMGCR_RAM_DFT_EN_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SYS1_RAMGCR_RAM_DFT_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: WST_AENA0 - eSRAM data phase wait state enable bit. */ +#define TMS570_SYS1_RAMGCR_WST_AENA0 BSP_BIT32(2) + +/* field: WST_DENA0 - eSRAM data phase wait state enable bit. */ +#define TMS570_SYS1_RAMGCR_WST_DENA0 BSP_BIT32(0) + + +/*---------------------TMS570_SYS1_BMMCR1---------------------*/ +/* field: MEMSW - Memory swap key. */ +#define TMS570_SYS1_BMMCR1_MEMSW(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_BMMCR1_MEMSW_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_BMMCR1_MEMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SYS1_CPURSTCR--------------------*/ +/* field: CPU_RESET - CPU Reset. */ +#define TMS570_SYS1_CPURSTCR_CPU_RESET BSP_BIT32(0) + + +/*--------------------TMS570_SYS1_CLKCNTL--------------------*/ +/* field: VCLK2R - VBUS clock2 ratio. */ +#define TMS570_SYS1_CLKCNTL_VCLK2R(val) BSP_FLD32(val,24, 27) +#define TMS570_SYS1_CLKCNTL_VCLK2R_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_SYS1_CLKCNTL_VCLK2R_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: VCLKR - VBUS clock ratio. */ +#define TMS570_SYS1_CLKCNTL_VCLKR(val) BSP_FLD32(val,16, 19) +#define TMS570_SYS1_CLKCNTL_VCLKR_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SYS1_CLKCNTL_VCLKR_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: PENA - Peripheral enable bit. */ +#define TMS570_SYS1_CLKCNTL_PENA BSP_BIT32(8) + + +/*--------------------TMS570_SYS1_ECPCNTL--------------------*/ +/* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */ +#define TMS570_SYS1_ECPCNTL_ECPSSEL BSP_BIT32(24) + +/* field: ECPCOS - ECP continue on suspend. */ +#define TMS570_SYS1_ECPCNTL_ECPCOS BSP_BIT32(23) + +/* field: ECPINSEL - Select ECP input clock source. */ +#define TMS570_SYS1_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17) +#define TMS570_SYS1_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17) +#define TMS570_SYS1_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17) + +/* field: ECPDIV - ECP divider value. */ +#define TMS570_SYS1_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15) +#define TMS570_SYS1_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SYS1_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_SYS1_DEVCR1---------------------*/ +/* field: DEVPARSEL - Device parity select bit key. */ +#define TMS570_SYS1_DEVCR1_DEVPARSEL(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_DEVCR1_DEVPARSEL_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_DEVCR1_DEVPARSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_SYS1_SYSECR---------------------*/ +/* field: RESET - Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset. */ +#define TMS570_SYS1_SYSECR_RESET(val) BSP_FLD32(val,14, 15) +#define TMS570_SYS1_SYSECR_RESET_GET(reg) BSP_FLD32GET(reg,14, 15) +#define TMS570_SYS1_SYSECR_RESET_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) + + +/*---------------------TMS570_SYS1_SYSESR---------------------*/ +/* field: PORST - Power-up reset. This bit is set when VCCOR (VCC Out of Range) is detected. */ +#define TMS570_SYS1_SYSESR_PORST BSP_BIT32(15) + +/* field: OSCRST - Reset caused by an oscillator failure or PLL cycle slip. */ +#define TMS570_SYS1_SYSESR_OSCRST BSP_BIT32(14) + +/* field: WDRST - Watchdog reset flag. */ +#define TMS570_SYS1_SYSESR_WDRST BSP_BIT32(13) + +/* field: CPURST - CPU reset flag. This bit is set when the CPU is reset. */ +#define TMS570_SYS1_SYSESR_CPURST BSP_BIT32(5) + +/* field: SWRST - Software reset flag. This bit is set when a software system reset has occurred. */ +#define TMS570_SYS1_SYSESR_SWRST BSP_BIT32(4) + +/* field: EXTRST - External reset flag. This bit is set when a reset is caused by the external reset pin nRST. */ +#define TMS570_SYS1_SYSESR_EXTRST BSP_BIT32(3) + +/* field: MPMODE - This indicates the current memory protection unit (MPU) mode. */ +#define TMS570_SYS1_SYSESR_MPMODE BSP_BIT32(0) + + +/*--------------------TMS570_SYS1_SYSTASR--------------------*/ +/* field: EFUSE_Abort - Test Abort status flag. */ +#define TMS570_SYS1_SYSTASR_EFUSE_Abort(val) BSP_FLD32(val,0, 4) +#define TMS570_SYS1_SYSTASR_EFUSE_Abort_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_SYS1_SYSTASR_EFUSE_Abort_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*--------------------TMS570_SYS1_GLBSTAT--------------------*/ +/* field: FBSLIP - PLL over cycle slip detection. */ +#define TMS570_SYS1_GLBSTAT_FBSLIP BSP_BIT32(9) + +/* field: RFSLIP - PLL under cycle slip detection. */ +#define TMS570_SYS1_GLBSTAT_RFSLIP BSP_BIT32(8) + +/* field: OSCFAIL - Oscillator fail flag bit. */ +#define TMS570_SYS1_GLBSTAT_OSCFAIL BSP_BIT32(0) + + +/*---------------------TMS570_SYS1_DEVID---------------------*/ +/* field: CP15 - CP15 CPU. This bit indicates whether the CPU has a coprocessor 15 (CP15). */ +#define TMS570_SYS1_DEVID_CP15 BSP_BIT32(31) + +/* field: TECH - These bits define the process technology by which the device was manufactured. */ +#define TMS570_SYS1_DEVID_TECH(val) BSP_FLD32(val,13, 16) +#define TMS570_SYS1_DEVID_TECH_GET(reg) BSP_FLD32GET(reg,13, 16) +#define TMS570_SYS1_DEVID_TECH_SET(reg,val) BSP_FLD32SET(reg, val,13, 16) + +/* field: I_O_VOLTAGE - Input/output voltage. This bit defines the I/O voltage of the device. */ +#define TMS570_SYS1_DEVID_I_O_VOLTAGE BSP_BIT32(12) + +/* field: PERIPHERAL_PARITY - The peripheral memories have no parity. */ +#define TMS570_SYS1_DEVID_PERIPHERAL_PARITY BSP_BIT32(11) + +/* field: FLASH_ECC - These bits indicate which parity is present for the program memory. */ +#define TMS570_SYS1_DEVID_FLASH_ECC(val) BSP_FLD32(val,9, 10) +#define TMS570_SYS1_DEVID_FLASH_ECC_GET(reg) BSP_FLD32GET(reg,9, 10) +#define TMS570_SYS1_DEVID_FLASH_ECC_SET(reg,val) BSP_FLD32SET(reg, val,9, 10) + +/* field: RAM_ECC - RAM ECC. This bit indicates whether or not RAM memory ECC is present. */ +#define TMS570_SYS1_DEVID_RAM_ECC BSP_BIT32(8) + +/* field: VERSION - Version. These bits provide the revision of the device. */ +#define TMS570_SYS1_DEVID_VERSION(val) BSP_FLD32(val,3, 7) +#define TMS570_SYS1_DEVID_VERSION_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_SYS1_DEVID_VERSION_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: PLATFORM_ID - The device is part of the TMS570Px family. The TMS570Px ID is always 5h. */ +#define TMS570_SYS1_DEVID_PLATFORM_ID(val) BSP_FLD32(val,0, 2) +#define TMS570_SYS1_DEVID_PLATFORM_ID_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_SYS1_DEVID_PLATFORM_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*---------------------TMS570_SYS1_SSIVEC---------------------*/ +/* field: SSIDATA - System software interrupt data key. */ +#define TMS570_SYS1_SSIVEC_SSIDATA(val) BSP_FLD32(val,8, 15) +#define TMS570_SYS1_SSIVEC_SSIDATA_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_SYS1_SSIVEC_SSIDATA_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: SSIVECT - These bits contain the source for the system software interrupt. */ +#define TMS570_SYS1_SSIVEC_SSIVECT(val) BSP_FLD32(val,0, 7) +#define TMS570_SYS1_SSIVEC_SSIVECT_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SYS1_SSIVEC_SSIVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_SYS1_SSIF----------------------*/ +/* field: SSI_FLAG - System software interrupt flag[4-1]. */ +#define TMS570_SYS1_SSIF_SSI_FLAG(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_SSIF_SSI_FLAG_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_SSIF_SSI_FLAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + + +#endif /* LIBBSP_ARM_TMS570_SYS1 */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h new file mode 100644 index 0000000000..29ec5a141c --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h @@ -0,0 +1,170 @@ +/* The header file is generated by make_header.py from SYS2.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_SYS2 +#define LIBBSP_ARM_TMS570_SYS2 + +#include + +typedef struct{ + uint32_t PLLCTL3; /*PLL Control Register 3*/ + uint8_t reserved1 [4]; + uint32_t STCCLKDIV; /*CPU Logic BIST Clock Divider*/ + uint8_t reserved2 [24]; + uint32_t ECPCNTL; /*ECP Control Register*/ + uint8_t reserved3 [20]; + uint32_t CLK2CNTRL; /*Clock 2 Control Register*/ + uint32_t VCLKACON1; /*Peripheral Asynchronous Clock Configuration 1 Register*/ + uint8_t reserved4 [44]; + uint32_t CLKSLIP; /*Clock Slip Register*/ + uint8_t reserved5 [120]; + uint32_t EFC_CTLREG; /*EFUSE Controller Control Register*/ + uint32_t DIEDL_REG0; /*Die Identification Register*/ + uint32_t DIEDH_REG1; /*Die Identification Register*/ + uint32_t DIEDL_REG2; /*Die Identification Register*/ + uint32_t DIEDH_REG3; /*Die Identification Register*/ +} tms570_sys2_t; + + +/*--------------------TMS570_SYS2_PLLCTL3--------------------*/ +/* field: ODPLL2 - Internal PLL Output Divider */ +#define TMS570_SYS2_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31) +#define TMS570_SYS2_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31) +#define TMS570_SYS2_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31) + +/* field: PLLDIV2 - PLL2 Output Clock Divider */ +#define TMS570_SYS2_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28) +#define TMS570_SYS2_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_SYS2_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: REFCLKDIV2 - REFCLKDIV2 */ +#define TMS570_SYS2_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21) +#define TMS570_SYS2_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21) +#define TMS570_SYS2_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) + +/* field: PLLMUL2 - PLL2 Multiplication Factor */ +#define TMS570_SYS2_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15) +#define TMS570_SYS2_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SYS2_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_SYS2_STCCLKDIV-------------------*/ +/* field: CLKDIV - Clock divider/prescaler for CPU clock during logic BIST */ +#define TMS570_SYS2_STCCLKDIV_CLKDIV(val) BSP_FLD32(val,24, 26) +#define TMS570_SYS2_STCCLKDIV_CLKDIV_GET(reg) BSP_FLD32GET(reg,24, 26) +#define TMS570_SYS2_STCCLKDIV_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 26) + + +/*--------------------TMS570_SYS2_ECPCNTL--------------------*/ +/* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */ +#define TMS570_SYS2_ECPCNTL_ECPSSEL BSP_BIT32(24) + +/* field: ECPCOS - ECP continue on suspend. */ +#define TMS570_SYS2_ECPCNTL_ECPCOS BSP_BIT32(23) + +/* field: ECPINSEL - Select ECP input clock source. */ +#define TMS570_SYS2_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17) +#define TMS570_SYS2_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17) +#define TMS570_SYS2_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17) + +/* field: ECPDIV - ECP divider value. */ +#define TMS570_SYS2_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15) +#define TMS570_SYS2_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SYS2_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_SYS2_CLK2CNTRL-------------------*/ +/* field: VCLK3R - VBUS clock3 ratio. */ +#define TMS570_SYS2_CLK2CNTRL_VCLK3R(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS2_CLK2CNTRL_VCLK3R_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS2_CLK2CNTRL_VCLK3R_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_SYS2_VCLKACON1-------------------*/ +/* field: VCLKA4R - Clock divider for the VCLKA4 source. Output will be present on VCLKA4_DIVR. */ +#define TMS570_SYS2_VCLKACON1_VCLKA4R(val) BSP_FLD32(val,24, 26) +#define TMS570_SYS2_VCLKACON1_VCLKA4R_GET(reg) BSP_FLD32GET(reg,24, 26) +#define TMS570_SYS2_VCLKACON1_VCLKA4R_SET(reg,val) BSP_FLD32SET(reg, val,24, 26) + +/* field: VCLKA4_DIV_CDDIS - Disable the VCLKA4 divider output. */ +#define TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS BSP_BIT32(20) + +/* field: VCLKA4S - Peripheral asynchronous clock4 source. */ +#define TMS570_SYS2_VCLKACON1_VCLKA4S(val) BSP_FLD32(val,16, 19) +#define TMS570_SYS2_VCLKACON1_VCLKA4S_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SYS2_VCLKACON1_VCLKA4S_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: VCLKA3R - Clock divider for the VCLKA3 source. Output will be present on VCLKA3_DIVR. */ +#define TMS570_SYS2_VCLKACON1_VCLKA3R(val) BSP_FLD32(val,8, 10) +#define TMS570_SYS2_VCLKACON1_VCLKA3R_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_SYS2_VCLKACON1_VCLKA3R_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: VCLKA3_DIV_CDDIS - Disable the VCLKA3 divider output. */ +#define TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS BSP_BIT32(4) + +/* field: VCLKA3S - Peripheral asynchronous clock3 source. */ +#define TMS570_SYS2_VCLKACON1_VCLKA3S(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS2_VCLKACON1_VCLKA3S_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS2_VCLKACON1_VCLKA3S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SYS2_CLKSLIP--------------------*/ +/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */ +#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13) +#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13) +#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13) + +/* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */ +#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_SYS2_EFC_CTLREG-------------------*/ +/* field: EFC_INSTR_WEN - Enable user write of 4 EFUSE controller instructions. */ +#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-----------------------TMS570_SYS2_x-----------------------*/ +/* field: DIE - This read-only register contains the lower/upper word (31:0) of the die ID information. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_SYS2 */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h new file mode 100644 index 0000000000..5304504afc --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h @@ -0,0 +1,84 @@ +/* The header file is generated by make_header.py from TCR.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_TCR +#define LIBBSP_ARM_TMS570_TCR + +#include + +typedef struct{ + uint32_t TCR[128]; /*Transfer Configuration RAM*/ + uint32_t TCR_Parity[128]; /*TCR Parity Test Mode*/ +} tms570_tcr_t; + + +/*-----------------------TMS570_TCR_TCR-----------------------*/ +/* field: STXR - Set Transmit Request. */ +#define TMS570_TCR_TCR_STXR BSP_BIT32(18) + +/* field: THTSM - Transfer Header to System Memory. */ +#define TMS570_TCR_TCR_THTSM BSP_BIT32(17) + +/* field: TPTSM - Transfer Payload to System Memory. */ +#define TMS570_TCR_TCR_TPTSM BSP_BIT32(16) + +/* field: THTCC - Transfer Header to Communication Controller. */ +#define TMS570_TCR_TCR_THTCC BSP_BIT32(15) + +/* field: TPTCC - Transfer Payload to Communication Controller. */ +#define TMS570_TCR_TCR_TPTCC BSP_BIT32(14) + +/* field: TSO - Transfer Start Offset. */ +#define TMS570_TCR_TCR_TSO(val) BSP_FLD32(val,0, 13) +#define TMS570_TCR_TCR_TSO_GET(reg) BSP_FLD32GET(reg,0, 13) +#define TMS570_TCR_TCR_TSO_SET(reg,val) BSP_FLD32SET(reg, val,0, 13) + + +/*-------------------TMS570_TCR_TCR_Parity-------------------*/ +/* field: PAB2 - Parity Bit for TCRx Byte 2. Parity information for byte 2 of TCRx(18-16). */ +#define TMS570_TCR_TCR_Parity_PAB2 BSP_BIT32(16) + +/* field: PAB1 - Parity Bit for TCRx Byte 1. Parity information for byte 1 of TCRx(15:8). */ +#define TMS570_TCR_TCR_Parity_PAB1 BSP_BIT32(8) + +/* field: PAB0 - Parity Bit for Byte 0. */ +#define TMS570_TCR_TCR_Parity_PAB0 BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_TCR */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h new file mode 100644 index 0000000000..1a48848e76 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h @@ -0,0 +1,170 @@ +/* The header file is generated by make_header.py from TCRAM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_TCRAM +#define LIBBSP_ARM_TMS570_TCRAM + +#include + +typedef struct{ + uint32_t RAMCTRL; /*TCRAM Module Control Register*/ + uint32_t RAMTHRESHOLD; /*TCRAM Module Single-Bit Error Correction Threshold Register*/ + uint32_t RAMOCCUR; /*TCRAM Module Single-Bit Error Occurrences Control Register*/ + uint32_t RAMINTCTRL; /*TCRAM Module Interrupt Control Register*/ + uint32_t RAMERRSTATUS; /*TCRAM Module Error Status Register*/ + uint32_t RAMSERRADDR; /*TCRAM Module Single-Bit Error Address Register*/ + uint8_t reserved1 [4]; + uint32_t RAMUERRADDR; /*TCRAM Module Uncorrectable Error Address Register*/ + uint8_t reserved2 [16]; + uint32_t RAMTEST; /*TCRAM Module Test Mode Control Register*/ + uint8_t reserved3 [4]; + uint32_t RAMADDRDECVECT; /*TCRAM Module Test Mode Vector Register*/ + uint32_t RAMPERADDR; /*TCRAM Module Parity Error Address Register*/ +} tms570_tcram_t; + + +/*--------------------TMS570_TCRAM_RAMCTRL--------------------*/ +/* field: EMU_TRACE_DIS - Emulation Mode Trace Disable. */ +#define TMS570_TCRAM_RAMCTRL_EMU_TRACE_DIS BSP_BIT32(30) + +/* field: ADDR_PARITY_OVERRIDE - Address Parity Override. */ +#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE(val) BSP_FLD32(val,24, 27) +#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: ADDR_PARITY_DISABLE - Address Parity Detect Disable. */ +#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE(val) BSP_FLD32(val,16, 19) +#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: ECC_WR_EN - ECC Memory Write Enable. */ +#define TMS570_TCRAM_RAMCTRL_ECC_WR_EN BSP_BIT32(8) + +/* field: ECC_DETECT_EN - ECC Detect Enable. */ +#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN(val) BSP_FLD32(val,0, 3) +#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-----------------TMS570_TCRAM_RAMTHRESHOLD-----------------*/ +/* field: THRESHOLD - Single-bit Error Threshold Count. */ +#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD(val) BSP_FLD32(val,0, 15) +#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_TCRAM_RAMOCCUR-------------------*/ +/* field: SINGLE_ERROR - Single-bit Error Correction Occurrences. */ +#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR(val) BSP_FLD32(val,0, 15) +#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_TCRAM_RAMINTCTRL------------------*/ +/* field: SERR_EN - Single-bit Error Correction Interrupt Enable. */ +#define TMS570_TCRAM_RAMINTCTRL_SERR_EN BSP_BIT32(0) + + +/*-----------------TMS570_TCRAM_RAMERRSTATUS-----------------*/ +/* field: WADDR_PAR_FAIL - This bit indicates a Write Address Parity Failure. */ +#define TMS570_TCRAM_RAMERRSTATUS_WADDR_PAR_FAIL BSP_BIT32(9) + +/* field: RADDR_PAR_FAIL - This bit indicates a Read Address Parity Failure. */ +#define TMS570_TCRAM_RAMERRSTATUS_RADDR_PAR_FAIL BSP_BIT32(8) + +/* field: DERR - This bit indicates a multi-bit error detected by the Cortex-R4F SECDED logic. */ +#define TMS570_TCRAM_RAMERRSTATUS_DERR BSP_BIT32(5) + +/* field: ADDR_COMP_LOGIC_FAIL - Address decode logic element failed. */ +#define TMS570_TCRAM_RAMERRSTATUS_ADDR_COMP_LOGIC_FAIL BSP_BIT32(4) + +/* field: ADDR_DEC_FAIL - Address decode failed. */ +#define TMS570_TCRAM_RAMERRSTATUS_ADDR_DEC_FAIL BSP_BIT32(2) + +/* field: SERR - Single Error Status. */ +#define TMS570_TCRAM_RAMERRSTATUS_SERR BSP_BIT32(0) + + +/*------------------TMS570_TCRAM_RAMSERRADDR------------------*/ +/* field: SINGLE_ERROR_ADDRESS - This register captures the bits 17-3 of the address for which the Cortex-R4F CPU */ +#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS(val) BSP_FLD32(val,3, 17) +#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,3, 17) +#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,3, 17) + + +/*------------------TMS570_TCRAM_RAMUERRADDR------------------*/ +/* field: UNCORRECTABLE - address parity error. */ +#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE(val) BSP_FLD32(val,3, 22) +#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_GET(reg) BSP_FLD32GET(reg,3, 22) +#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_SET(reg,val) BSP_FLD32SET(reg, val,3, 22) + + +/*--------------------TMS570_TCRAM_RAMTEST--------------------*/ +/* field: TRIGGER - Test Trigger. */ +#define TMS570_TCRAM_RAMTEST_TRIGGER BSP_BIT32(8) + +/* field: TEST_MODE - Test Mode. This field selects either equality of inequality testing schemes. */ +#define TMS570_TCRAM_RAMTEST_TEST_MODE(val) BSP_FLD32(val,6, 7) +#define TMS570_TCRAM_RAMTEST_TEST_MODE_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_TCRAM_RAMTEST_TEST_MODE_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: TEST_ENABLE - Test Enable. */ +#define TMS570_TCRAM_RAMTEST_TEST_ENABLE(val) BSP_FLD32(val,0, 3) +#define TMS570_TCRAM_RAMTEST_TEST_ENABLE_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_TCRAM_RAMTEST_TEST_ENABLE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*----------------TMS570_TCRAM_RAMADDRDECVECT----------------*/ +/* field: ECC_SELECT - ECC Select. */ +#define TMS570_TCRAM_RAMADDRDECVECT_ECC_SELECT BSP_BIT32(26) + +/* field: RAM_CHIP_SELECT - RAM Chip Select. */ +#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT(val) BSP_FLD32(val,0, 15) +#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_TCRAM_RAMPERADDR------------------*/ +/* field: ADDRESS_PARITY - Parity Error Address. */ +#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY(val) BSP_FLD32(val,3, 22) +#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_GET(reg) BSP_FLD32GET(reg,3, 22) +#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_SET(reg,val) BSP_FLD32SET(reg, val,3, 22) + + + +#endif /* LIBBSP_ARM_TMS570_TCRAM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h new file mode 100644 index 0000000000..d0347a4509 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h @@ -0,0 +1,190 @@ +/* The header file is generated by make_header.py from VIM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_VIM +#define LIBBSP_ARM_TMS570_VIM + +#include + +typedef struct{ + uint32_t PARFLG; /*Interrupt Vector Table Parity Flag Register*/ + uint32_t PARCTL; /*Interrupt Vector Table Parity Control Register*/ + uint32_t ADDERR; /*Address Parity Error Register*/ + uint32_t FBPARERR; /*Fall-Back Address Parity Error Register*/ + uint8_t reserved1 [4]; + uint32_t IRQINDEX; /*IRQ Index Offset Vector Register*/ + uint32_t FIQINDEX; /*FIQ Index Offset Vector Register*/ + uint8_t reserved2 [8]; + uint32_t FIRQPR[3]; /*FIQ/IRQ Program Control Register*/ + uint8_t reserved3 [4]; + uint32_t INTREQ[3]; /*Pending Interrupt Read Location Register*/ + uint8_t reserved4 [4]; + uint32_t REQENASET[3]; /*Interrupt Enable Set Register */ + uint8_t reserved5 [4]; + uint32_t REQENACLR[3]; /*Interrupt Enable Clear Register */ + uint8_t reserved6 [4]; + uint32_t WAKEENASET[3]; /*Wake-Up Enable Set Register*/ + uint8_t reserved7 [4]; + uint32_t WAKEENACLR[3]; /*Wake-Up Enable Clear Registers*/ + uint8_t reserved8 [4]; + uint32_t IRQVECREG; /*IRQ Interrupt Vector Register*/ + uint32_t FIQVECREG; /*FIQ Interrupt Vector Register*/ + uint32_t CAPEVT; /*Capture Event Register*/ + uint8_t reserved9 [4]; + uint32_t CHANCTRL[24]; /*VIM Interrupt Control Register*/ +} tms570_vim_t; + + +/*---------------------TMS570_VIM_PARFLG---------------------*/ +/* field: PARFLG - The PARFLG indicates that a parity error has been found and that theInterrupt Vector Table is */ +#define TMS570_VIM_PARFLG_PARFLG BSP_BIT32(0) + + +/*---------------------TMS570_VIM_PARCTL---------------------*/ +/* field: TEST - This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the */ +#define TMS570_VIM_PARCTL_TEST BSP_BIT32(8) + +/* field: PARENA - VIM parity enable. */ +#define TMS570_VIM_PARCTL_PARENA(val) BSP_FLD32(val,0, 3) +#define TMS570_VIM_PARCTL_PARENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_VIM_PARCTL_PARENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_VIM_ADDERR---------------------*/ +/* field: Interrupt_Vector_Table - Interrupt Vector Table offset. */ +#define TMS570_VIM_ADDERR_Interrupt_Vector_Table(val) BSP_FLD32(val,9, 31) +#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_GET(reg) BSP_FLD32GET(reg,9, 31) +#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_SET(reg,val) BSP_FLD32SET(reg, val,9, 31) + +/* field: ADDERR - Address parity error register. */ +#define TMS570_VIM_ADDERR_ADDERR(val) BSP_FLD32(val,2, 8) +#define TMS570_VIM_ADDERR_ADDERR_GET(reg) BSP_FLD32GET(reg,2, 8) +#define TMS570_VIM_ADDERR_ADDERR_SET(reg,val) BSP_FLD32SET(reg, val,2, 8) + +/* field: Word_offset - Word offset. Reads are always 0; writes have no effect. */ +#define TMS570_VIM_ADDERR_Word_offset(val) BSP_FLD32(val,0, 1) +#define TMS570_VIM_ADDERR_Word_offset_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_VIM_ADDERR_Word_offset_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_VIM_FBPARERR--------------------*/ +/* field: FBPARERR - Fall back address parity error. */ +/* Whole 32 bits */ + +/*--------------------TMS570_VIM_IRQINDEX--------------------*/ +/* field: IRQINDEX - IRQ index vector. */ +#define TMS570_VIM_IRQINDEX_IRQINDEX(val) BSP_FLD32(val,0, 7) +#define TMS570_VIM_IRQINDEX_IRQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_VIM_IRQINDEX_IRQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*--------------------TMS570_VIM_FIQINDEX--------------------*/ +/* field: FIQINDEX - FIQ index offset vector. */ +#define TMS570_VIM_FIQINDEX_FIQINDEX(val) BSP_FLD32(val,0, 7) +#define TMS570_VIM_FIQINDEX_FIQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_VIM_FIQINDEX_FIQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_VIM_FIRQPR---------------------*/ +/* field: FIRQPRx - FIQ/IRQ program control bits. 96 bit register. 0-1 bits reserved. */ +/* Whole 32 bits */ + +/*---------------------TMS570_VIM_INTREQ---------------------*/ +/* field: INTREQx - Pending interrupt bits. 96 bit register. */ +/* Whole 32 bits */ + +/*--------------------TMS570_VIM_REQENASET--------------------*/ +/* field: REQENASETx - Request enable set bits. 96 bit register. 0-1 bits reserved. */ +/* Whole 32 bits */ + +/*--------------------TMS570_VIM_REQENACLR--------------------*/ +/* field: REQENACLRx - Request enable clear bits. 96 bit register. 0-1 bits reserved. */ +/* Whole 32 bits */ + +/*-------------------TMS570_VIM_WAKEENASET-------------------*/ +/* field: WAKEENASETx - Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled. */ +/* Whole 32 bits */ + +/*-------------------TMS570_VIM_WAKEENACLR-------------------*/ +/* field: WAKEENACLRx - Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is enabled. */ +/* Whole 32 bits */ + +/*--------------------TMS570_VIM_IRQVECREG--------------------*/ +/* field: IRQVECREG - IRQ interrupt vector register. */ +/* Whole 32 bits */ + +/*--------------------TMS570_VIM_FIQVECREG--------------------*/ +/* field: FIQVECREG - FIQ interrupt vector register. */ +/* Whole 32 bits */ + +/*---------------------TMS570_VIM_CAPEVT---------------------*/ +/* field: CAPEVTSRC1 - Capture event source 1 mapping control. */ +#define TMS570_VIM_CAPEVT_CAPEVTSRC1(val) BSP_FLD32(val,16, 22) +#define TMS570_VIM_CAPEVT_CAPEVTSRC1_GET(reg) BSP_FLD32GET(reg,16, 22) +#define TMS570_VIM_CAPEVT_CAPEVTSRC1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22) + +/* field: CAPEVTSRC0 - the capture event source 0 of the RTI: */ +#define TMS570_VIM_CAPEVT_CAPEVTSRC0(val) BSP_FLD32(val,0, 6) +#define TMS570_VIM_CAPEVT_CAPEVTSRC0_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_VIM_CAPEVT_CAPEVTSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + +/*--------------------TMS570_VIM_CHANCTRL--------------------*/ +/* field: CHANMAPx0 - CHANMAPx 0(6-0). Interrupt CHANx 0 mapping control. */ +#define TMS570_VIM_CHANCTRL_CHANMAPx0(val) BSP_FLD32(val,24, 30) +#define TMS570_VIM_CHANCTRL_CHANMAPx0_GET(reg) BSP_FLD32GET(reg,24, 30) +#define TMS570_VIM_CHANCTRL_CHANMAPx0_SET(reg,val) BSP_FLD32SET(reg, val,24, 30) + +/* field: CHANMAPx1 - CHANMAPx 1(6-0). Interrupt CHANx 1 mapping control. */ +#define TMS570_VIM_CHANCTRL_CHANMAPx1(val) BSP_FLD32(val,16, 22) +#define TMS570_VIM_CHANCTRL_CHANMAPx1_GET(reg) BSP_FLD32GET(reg,16, 22) +#define TMS570_VIM_CHANCTRL_CHANMAPx1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22) + +/* field: CHANMAPx2 - CHANMAPx 2(6-0). Interrupt CHANx 2 mapping control. */ +#define TMS570_VIM_CHANCTRL_CHANMAPx2(val) BSP_FLD32(val,8, 14) +#define TMS570_VIM_CHANCTRL_CHANMAPx2_GET(reg) BSP_FLD32GET(reg,8, 14) +#define TMS570_VIM_CHANCTRL_CHANMAPx2_SET(reg,val) BSP_FLD32SET(reg, val,8, 14) + +/* field: CHANMAPx3 - CHANMAPx 3(6-0). Interrupt CHANx 3 mapping control. */ +#define TMS570_VIM_CHANCTRL_CHANMAPx3(val) BSP_FLD32(val,0, 6) +#define TMS570_VIM_CHANCTRL_CHANMAPx3_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_VIM_CHANCTRL_CHANMAPx3_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + + +#endif /* LIBBSP_ARM_TMS570_VIM */ diff --git a/bsps/arm/tms570/include/bsp/tms570-pinmux.h b/bsps/arm/tms570/include/bsp/tms570-pinmux.h new file mode 100644 index 0000000000..8b93c66bfa --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-pinmux.h @@ -0,0 +1,137 @@ +/** + * @file tms570-pinmux.h + * + * @ingroup tms570 + * + * @brief I/O Multiplexing Module (IOMM) basic support + */ + +/* + * Copyright (c) 2015 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_PINMUX_H +#define LIBBSP_ARM_TMS570_PINMUX_H + +#ifndef ASM +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +#define TMS570_PIN_NUM_SHIFT 0 +#define TMS570_PIN_NUM_MASK 0x000007ff + +/* + * Request clear of interconnection in setup + * to ensure that previous peripheral to pin + * connection is not enabled in parallel to other one. + * Mask is ored with pin number in such list. + */ +#define TMS570_PIN_CLEAR_RQ_MASK 0x00000800 + +#define TMS570_PIN_FNC_SHIFT 12 +#define TMS570_PIN_FNC_MASK 0x0000f000 + +#define TMS570_PIN_NUM_FNC_MASK 0x0000ffff + +#define TMS570_PIN_IN_ALT_SHIFT 16 +#define TMS570_PIN_IN_ALT_MASK 0xffff0000 + +#define TMS570_PIN_FNC_AUTO (-1) + +#define TMS570_PIN_AND_FNC(pin, fnc) \ + ((pin) | ((fnc) << TMS570_PIN_FNC_SHIFT)) + +#define TMS570_PIN_WITH_IN_ALT(pin_num_and_fnc, pin_in_alt_num_and_fnc) \ + ((pin_num_and_fnc) | ((pin_in_alt_num_and_fnc) << TMS570_PIN_IN_ALT_SHIFT)) + +#define TMS570_BALL_WITH_MMR(mmrx, pos) \ + ((pos) | ((mmrx) << 2)) + +/* Generic functions select pin to peripheral connection */ + +void tms570_bsp_pin_set_function(int pin_num, int pin_fnc); + +void tms570_bsp_pin_clear_function(int pin_num, int pin_fnc); + +void tms570_bsp_pin_config_one(uint32_t pin_num_and_fnc); + +void tms570_bsp_pinmmr_config(const uint32_t *pinmmr_values, int reg_start, int reg_count); + +static inline void +tms570_bsp_pin_to_pinmmrx(volatile uint32_t **pinmmrx, unsigned int *pin_shift, + int pin_num) +{ + pin_num = (pin_num & TMS570_PIN_NUM_MASK) >> TMS570_PIN_NUM_SHIFT; + *pinmmrx = &TMS570_IOMM.PINMUX.PINMMR0 + (pin_num >> 2); + *pin_shift = (pin_num & 0x3)*8; +} + +#define TMS570_PINMMR_REG_SINGLE_VAL_ACTION(reg, pin) \ + (((((pin) & TMS570_PIN_NUM_MASK) >> 2 != (reg)) || ((pin) & TMS570_PIN_CLEAR_RQ_MASK))? 0: \ + 1 << ((((pin) & TMS570_PIN_FNC_MASK) >> TMS570_PIN_FNC_SHIFT) + \ + ((pin) & 3) * 8) \ + ) + +#define TMS570_PINMMR_REG_VAL_ACTION(reg, pin) \ + TMS570_PINMMR_REG_SINGLE_VAL_ACTION(reg, pin) | \ + ((pin) & TMS570_PIN_IN_ALT_MASK? \ + TMS570_PINMMR_REG_SINGLE_VAL_ACTION(reg, (pin) >> TMS570_PIN_IN_ALT_SHIFT ): \ + 0) | + +/** + * Macro which computes value for PINMMRx register from pin list + * which is defined as macro calling action macro for each pin + * + * @param reg PINMMR register number (0 .. 30 for TMS570LS3137) + * @param pin_list declared as macro with parameters + * \c per_pin_action and \c common_arg which expands + * to list of \c per_pin_action(\c common_arg, \c TMS570_BALL_xx_function) + * + * @retval number which represents connections which should be enabled + * in given PINMMR register. Pin setup for other registers than specified + * are ignored + */ +#define TMS570_PINMMR_REG_VAL(reg, pin_list) \ + pin_list(TMS570_PINMMR_REG_VAL_ACTION, reg) 0 + +#define TMS570_PINMMR_COMA_LIST_ACTION(reg, pin) \ + (pin), + +/** + * Macro which generates list of pin and function specification from + * from pin list which is defined as macro calling action macro for each pin + * + * @param pin_list declared as macro with parameters + * \c per_pin_action and \c common_arg which expands + * to list of \c per_pin_action(\c common_arg, \c TMS570_BALL_xx_function) + * + * @retval list of coma separated pin+function combined values which is terminated by coma + * at the end + */ +#define TMS570_PINMMR_COMA_LIST(pin_list) \ + pin_list(TMS570_PINMMR_COMA_LIST_ACTION, 0) + + +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570-pins.h b/bsps/arm/tms570/include/bsp/tms570-pins.h new file mode 100644 index 0000000000..f8db69fa19 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-pins.h @@ -0,0 +1,10 @@ +/** + * @file tms570-pins.h + * + * @ingroup tms570 + * + * @brief Select pin mapping according to selected chip. + * Defaults to TMS570LS3137ZWT for now. + */ + +#include diff --git a/bsps/arm/tms570/include/bsp/tms570-pom.h b/bsps/arm/tms570/include/bsp/tms570-pom.h new file mode 100644 index 0000000000..2c54a016dc --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-pom.h @@ -0,0 +1,60 @@ +/** + * @file tms570-pom.h + * @ingroup tms570 + * @brief Parameter Overlay Module (POM) header file + */ + +/* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_POM_H +#define LIBBSP_ARM_TMS570_POM_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define TMS570_POM_REGIONS 32 +#define TMS570_POM_GLBCTRL_ENABLE 0x000000a0a + +/* Specification of memory size used for field REGSIZE of tms570_pom_region_t */ +#define TMS570_POM_REGSIZE_DISABLED 0x0 +#define TMS570_POM_REGSIZE_64B 0x1 +#define TMS570_POM_REGSIZE_128B 0x2 +#define TMS570_POM_REGSIZE_256B 0x3 +#define TMS570_POM_REGSIZE_512B 0x4 +#define TMS570_POM_REGSIZE_1KB 0x5 +#define TMS570_POM_REGSIZE_2KB 0x6 +#define TMS570_POM_REGSIZE_4KB 0x7 +#define TMS570_POM_REGSIZE_8KB 0x8 +#define TMS570_POM_REGSIZE_16KB 0x9 +#define TMS570_POM_REGSIZE_32KB 0xa +#define TMS570_POM_REGSIZE_64KB 0xb +#define TMS570_POM_REGSIZE_128KB 0xc +#define TMS570_POM_REGSIZE_256KB 0xd + +#define TMS570_POM_REGADDRMASK ((1<<23)-1) + +void tms570_initialize_and_clear(void); +void tms570_pom_remap(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_POM_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570-rti.h b/bsps/arm/tms570/include/bsp/tms570-rti.h new file mode 100644 index 0000000000..552db88a62 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-rti.h @@ -0,0 +1,46 @@ +/** + * @file tms570-rti.h + * + * @ingroup tms570 + * + * @brief Real Time Interrupt module (RTI) header file. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_RTI_H +#define LIBBSP_ARM_TMS570_RTI_H + +#ifndef ASM + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570-sci-driver.h b/bsps/arm/tms570/include/bsp/tms570-sci-driver.h new file mode 100644 index 0000000000..61693ce0ff --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-sci-driver.h @@ -0,0 +1,65 @@ +/** + * @file tms570-sci-driver.h + * + * @ingroup tms570 + * + * @brief Declaration of serial's driver inner structure. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef TMS570_SCI_DRIVER +#define TMS570_SCI_DRIVER + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Low-level driver specific data structure */ +typedef struct { + rtems_termios_device_context base; + const char *device_name; + volatile tms570_sci_t *regs; + int tx_chars_in_hw; + rtems_vector_number irq; +} tms570_sci_context; + +extern const rtems_termios_device_handler tms570_sci_handler_polled; + +extern const rtems_termios_device_handler tms570_sci_handler_interrupt; + +extern tms570_sci_context driver_context_table[]; + +void tms570_sci_initialize(tms570_sci_context *ctx); + +bool tms570_sci_set_attributes( + rtems_termios_device_context *base, + const struct termios *term +); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* TMS570_SCI_DRIVER */ diff --git a/bsps/arm/tms570/include/bsp/tms570-sci.h b/bsps/arm/tms570/include/bsp/tms570-sci.h new file mode 100644 index 0000000000..9c502dcd6a --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-sci.h @@ -0,0 +1,45 @@ +/** + * @file tms570-sci.h + * + * @ingroup tms570 + * + * @brief Serial Communication Interface (SCI) header file. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_SCI_H +#define LIBBSP_ARM_TMS570_SCI_H + +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/bsps/arm/tms570/include/bsp/tms570-vim.h b/bsps/arm/tms570/include/bsp/tms570-vim.h new file mode 100644 index 0000000000..9fa7e056f4 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-vim.h @@ -0,0 +1,48 @@ +/** + * @file tms570-vim.h + * + * @ingroup tms570 + * + * @brief Vectored Interrupt Module (VIM) header file. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_VIM_H +#define LIBBSP_ARM_TMS570_VIM_H + +#ifndef ASM +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + + +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570.h b/bsps/arm/tms570/include/bsp/tms570.h new file mode 100644 index 0000000000..f278a93606 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570.h @@ -0,0 +1,137 @@ +/* This file is generated by make_central_header.py */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570 +#define LIBBSP_ARM_TMS570 + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TMS570_ADC1 (*(volatile tms570_adc_t*)0xFFF7C000) +#define TMS570_ADC2 (*(volatile tms570_adc_t*)0xFFF7C200) +#define TMS570_CCMSR (*(volatile tms570_ccmsr_t*)0XFFFFF600) +#define TMS570_CRC (*(volatile tms570_crc_t*)0xFE000000) +#define TMS570_DCAN1 (*(volatile tms570_dcan_t*)0xFFF7DC00) +#define TMS570_DCAN2 (*(volatile tms570_dcan_t*)0xFFF7DE00) +#define TMS570_DCAN3 (*(volatile tms570_dcan_t*)0xFFF7E000) +#define TMS570_DCC1 (*(volatile tms570_dcc_t*)0xFFFFEC00) +#define TMS570_DCC2 (*(volatile tms570_dcc_t*)0xFFFFF400) +#define TMS570_DMA (*(volatile tms570_dma_t*)0xFFFFF000) +#define TMS570_DMM (*(volatile tms570_dmm_t*)0xFFFFF700) +#define TMS570_EFUSE (*(volatile tms570_efuse_t*)0XFFF8C01C) +#define TMS570_EMACC (*(volatile tms570_emacc_t*)0xFCF78800) +#define TMS570_EMACM (*(volatile tms570_emacm_t*)0xFCF78000) +#define TMS570_EMIF (*(volatile tms570_emif_t*)0xFCFFE800) +#define TMS570_ESM (*(volatile tms570_esm_t*)0XFFFFF500) +#define TMS570_FLASH (*(volatile tms570_flash_t*)0XFFF87000) +#define TMS570_FLEX_RAY (*(volatile tms570_flex_ray_t*)0xFFF7C800) +#define TMS570_GIO (*(volatile tms570_gio_t*)0xFFF7BC00) +#define TMS570_GIO_PORTA (*(volatile tms570_gio_port_t*)0xFFF7BC34) +#define TMS570_GIO_PORTB (*(volatile tms570_gio_port_t*)0xFFF7BC54) +#define TMS570_GIO_PORTC (*(volatile tms570_gio_port_t*)0xFFF7BC74) +#define TMS570_GIO_PORTD (*(volatile tms570_gio_port_t*)0xFFF7BC94) +#define TMS570_GIO_PORTE (*(volatile tms570_gio_port_t*)0xFFF7BCB4) +#define TMS570_GIO_PORTF (*(volatile tms570_gio_port_t*)0xFFF7BCD4) +#define TMS570_GIO_PORTG (*(volatile tms570_gio_port_t*)0xFFF7BCF4) +#define TMS570_GIO_PORTH (*(volatile tms570_gio_port_t*)0xFFF7BD14) +#define TMS570_HTU1 (*(volatile tms570_htu_t*)0xFFF7A400) +#define TMS570_HTU2 (*(volatile tms570_htu_t*)0xFFF7A500) +#define TMS570_I2C (*(volatile tms570_i2c_t*)0xFFF7D400) +#define TMS570_IOMM (*(volatile tms570_iomm_t*)0XFFFFEA00) +#define TMS570_PINMUX (*(volatile tms570_pinmux_t*)0xFFFFEB10) +#define TMS570_LIN (*(volatile tms570_lin_t*)0xFFF7E400) +#define TMS570_MDIO (*(volatile tms570_mdio_t*)0xFCF78900) +#define TMS570_NHET1 (*(volatile tms570_nhet_t*)0xFFF7B800) +#define TMS570_NHET2 (*(volatile tms570_nhet_t*)0xFFF7B900) +#define TMS570_PBIST (*(volatile tms570_pbist_t*)0xFFFFE400) +#define TMS570_PLL (*(volatile tms570_pll_t*)0XFFFFE100) +#define TMS570_PMM (*(volatile tms570_pmm_t*)0xFFFF0000) +#define TMS570_RTI (*(volatile tms570_rti_t*)0xFFFFFC00) +#define TMS570_RTP (*(volatile tms570_rtp_t*)0xFFFFFA00) +#define TMS570_SCI (*(volatile tms570_sci_t*)0xFFF7E500) +#define TMS570_TCR (*(volatile tms570_tcr_t*)0xFFF7C800) +#define TMS570_TCRAM1 (*(volatile tms570_tcram_t*)0xFFFFF800) +#define TMS570_TCRAM2 (*(volatile tms570_tcram_t*)0xFFFFF900) +#define TMS570_VIM (*(volatile tms570_vim_t*)0XFFFFFDEC) +#define TMS570_POM (*(volatile tms570_pom_t*)0XFFA04000) +#define TMS570_SPI1 (*(volatile tms570_spi_t*)0xFFF7F400) +#define TMS570_SPI2 (*(volatile tms570_spi_t*)0xFFF7F600) +#define TMS570_SPI3 (*(volatile tms570_spi_t*)0xFFF7F800) +#define TMS570_SPI4 (*(volatile tms570_spi_t*)0xFFF7FA00) +#define TMS570_SPI5 (*(volatile tms570_spi_t*)0xFFF7FC00) +#define TMS570_STC (*(volatile tms570_stc_t*)0xFFFFE600) +#define TMS570_SYS1 (*(volatile tms570_sys1_t*)0xFFFFFF00) +#define TMS570_SYS2 (*(volatile tms570_sys2_t*)0xFFFFE100) +#define TMS570_PCR (*(volatile tms570_pcr_t*)0xFFFFE000) +#endif /* LIBBSP_ARM_TMS570 */ diff --git a/bsps/arm/tms570/include/bsp/tms570_hwinit.h b/bsps/arm/tms570/include/bsp/tms570_hwinit.h new file mode 100644 index 0000000000..2c84b6e5fa --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570_hwinit.h @@ -0,0 +1,31 @@ +#ifndef LIBBSP_ARM_TMS570_HWINIT_H +#define LIBBSP_ARM_TMS570_HWINIT_H + +#define TMS570_TCRAM_START_PTR ( (void *) ( 0x08000000U ) ) +#define TMS570_TCRAM_WINDOW_END_PTR ( (void *) ( 0x08080000U ) ) + +#define TMS570_SDRAM_START_PTR ( (void *) ( 0x80000000U ) ) +#define TMS570_SDRAM_WINDOW_END_PTR ( (void *) ( 0xA0000000U ) ) + +/* Ti TMS570 core setup implemented in assembly */ +void _esmCcmErrorsClear_( void ); +void _coreEnableEventBusExport_( void ); +void _errata_CORTEXR4_66_( void ); +void _errata_CORTEXR4_57_( void ); +void _coreEnableRamEcc_( void ); +void _coreDisableRamEcc_( void ); +void _mpuInit_( void ); + +void tms570_emif_sdram_init( void ); +void tms570_memory_init( uint32_t ram ); +void tms570_system_hw_init( void ); +void tms570_pinmux_init( void ); +void tms570_pll_init( void ); +void tms570_trim_lpo_init( void ); +void tms570_flash_init( void ); +void tms570_periph_init( void ); +void tms570_map_clock_init( void ); +void tms570_system_hw_init( void ); +void tms570_esm_init( void ); + +#endif /* LIBBSP_ARM_TMS570_HWINIT_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570_selftest.h b/bsps/arm/tms570/include/bsp/tms570_selftest.h new file mode 100644 index 0000000000..bbec8c2adf --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570_selftest.h @@ -0,0 +1,214 @@ +/** + * @file tms570_selftest.h + * + * @ingroup tms570 + * + * @brief Definition of TMS570 selftest error codes, addresses and functions. + */ +/* + * Copyright (c) 2016 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Algorithms are based on Ti manuals and Ti HalCoGen generated + * code available under following copyright. + */ +/* + * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef LIBBSP_ARM_TMS570_SELFTEST_H +#define LIBBSP_ARM_TMS570_SELFTEST_H + +#include +#include + +#define CCMSELFCHECK_FAIL1 1U +#define CCMSELFCHECK_FAIL2 2U +#define CCMSELFCHECK_FAIL3 3U +#define CCMSELFCHECK_FAIL4 4U +#define PBISTSELFCHECK_FAIL1 5U +#define EFCCHECK_FAIL1 6U +#define EFCCHECK_FAIL2 7U +#define FMCECCCHECK_FAIL1 8U +#define CHECKB0RAMECC_FAIL1 9U +#define CHECKB1RAMECC_FAIL1 10U +#define CHECKFLASHECC_FAIL1 11U +#define VIMPARITYCHECK_FAIL1 12U +#define DMAPARITYCHECK_FAIL1 13U +#define HET1PARITYCHECK_FAIL1 14U +#define HTU1PARITYCHECK_FAIL1 15U +#define HET2PARITYCHECK_FAIL1 16U +#define HTU2PARITYCHECK_FAIL1 17U +#define ADC1PARITYCHECK_FAIL1 18U +#define ADC2PARITYCHECK_FAIL1 19U +#define CAN1PARITYCHECK_FAIL1 20U +#define CAN2PARITYCHECK_FAIL1 21U +#define CAN3PARITYCHECK_FAIL1 22U +#define MIBSPI1PARITYCHECK_FAIL1 23U +#define MIBSPI3PARITYCHECK_FAIL1 24U +#define MIBSPI5PARITYCHECK_FAIL1 25U +#define CHECKRAMECC_FAIL1 26U +#define CHECKRAMECC_FAIL2 27U +#define CHECKCLOCKMONITOR_FAIL1 28U +#define CHECKFLASHEEPROMECC_FAIL1 29U +#define CHECKFLASHEEPROMECC_FAIL2 31U +#define CHECKFLASHEEPROMECC_FAIL3 32U +#define CHECKFLASHEEPROMECC_FAIL4 33U +#define CHECKPLL1SLIP_FAIL1 34U +#define CHECKRAMADDRPARITY_FAIL1 35U +#define CHECKRAMADDRPARITY_FAIL2 36U +#define CHECKRAMUERRTEST_FAIL1 37U +#define CHECKRAMUERRTEST_FAIL2 38U +#define FMCBUS1PARITYCHECK_FAIL1 39U +#define FMCBUS1PARITYCHECK_FAIL2 40U +#define PBISTSELFCHECK_FAIL2 41U +#define PBISTSELFCHECK_FAIL3 42U + +/* PBIST and STC ROM - PBIST RAM GROUPING */ +#define PBIST_ROM_PBIST_RAM_GROUP 1U +#define STC_ROM_PBIST_RAM_GROUP 2U + +#define VIMRAMLOC (*(volatile uint32_t *)0xFFF82000U) +#define VIMRAMPARLOC (*(volatile uint32_t *)0xFFF82400U) + +#define NHET1RAMPARLOC (*(volatile uint32_t *)0xFF462000U) +#define NHET2RAMPARLOC (*(volatile uint32_t *)0xFF442000U) +#define adcPARRAM1 (*(volatile uint32_t *)(0xFF3E0000U + 0x1000U)) +#define adcPARRAM2 (*(volatile uint32_t *)(0xFF3A0000U + 0x1000U)) +#define canPARRAM1 (*(volatile uint32_t *)(0xFF1E0000U + 0x10U)) +#define canPARRAM2 (*(volatile uint32_t *)(0xFF1C0000U + 0x10U)) +#define canPARRAM3 (*(volatile uint32_t *)(0xFF1A0000U + 0x10U)) +#define HTU1PARLOC (*(volatile uint32_t *)0xFF4E0200U) +#define HTU2PARLOC (*(volatile uint32_t *)0xFF4C0200U) + +#define NHET1RAMLOC (*(volatile uint32_t *)0xFF460000U) +#define NHET2RAMLOC (*(volatile uint32_t *)0xFF440000U) +#define HTU1RAMLOC (*(volatile uint32_t *)0xFF4E0000U) +#define HTU2RAMLOC (*(volatile uint32_t *)0xFF4C0000U) + +#define adcRAM1 (*(volatile uint32_t *)0xFF3E0000U) +#define adcRAM2 (*(volatile uint32_t *)0xFF3A0000U) +#define canRAM1 (*(volatile uint32_t *)0xFF1E0000U) +#define canRAM2 (*(volatile uint32_t *)0xFF1C0000U) +#define canRAM3 (*(volatile uint32_t *)0xFF1A0000U) + +#define DMARAMPARLOC (*(volatile uint32_t *)(0xFFF80A00U)) +#define DMARAMLOC (*(volatile uint32_t *)(0xFFF80000U)) + +#define MIBSPI1RAMLOC (*(volatile uint32_t *)(0xFF0E0000U)) +#define MIBSPI3RAMLOC (*(volatile uint32_t *)(0xFF0C0000U)) +#define MIBSPI5RAMLOC (*(volatile uint32_t *)(0xFF0A0000U)) + +#define mibspiPARRAM1 (*(volatile uint32_t *)(0xFF0E0000U + 0x00000400U)) +#define mibspiPARRAM3 (*(volatile uint32_t *)(0xFF0C0000U + 0x00000400U)) +#define mibspiPARRAM5 (*(volatile uint32_t *)(0xFF0A0000U + 0x00000400U)) + +/** @enum pbistPort + * @brief Alias names for pbist Port number + * + * This enumeration is used to provide alias names for the pbist Port number + * - PBIST_PORT0 + * - PBIST_PORT1 + * + * @Note Check the datasheet for the port avaiability + */ +enum pbistPort { + PBIST_PORT0 = 0U, /**< Alias for PBIST Port 0 */ + PBIST_PORT1 = 1U /**< Alias for PBIST Port 1 < Check datasheet for Port 1 availability > */ +}; + +enum { + PBIST_TripleReadSlow = 0x00000001U, /** + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_SELFTEST_PARITY_H +#define LIBBSP_ARM_TMS570_SELFTEST_PARITY_H + +#include + +/** + * The magic number used to switch most of the peripherals + * into parity protection test mode + */ +#define TMS570_SELFTEST_PAR_CR_KEY 0xA + +typedef struct tms570_selftest_par_desc tms570_selftest_par_desc_t; + +typedef void tms570_selftest_par_fnc_t( const tms570_selftest_par_desc_t *desc ); + +/** + * Decriptor specifying registers addresses and values used to test + * that parity protection is working for given hardware + * module/peripheral. It is used during initial chip self-tests. + */ +struct tms570_selftest_par_desc { + unsigned char esm_prim_grp; /**< ESM primary signalling group number. */ + unsigned char esm_prim_chan; /**< ESM primary signalling channel number. */ + unsigned char esm_sec_grp; /**< ESM optional/alternative signalling group. */ + unsigned char esm_sec_chan; /**< ESM optional/alternative signalling channel. */ + int fail_code; /**< Error code reported to + bsp_selftest_fail_notification() in the case of the test failure. */ + volatile uint32_t *ram_loc; /**< Address of memory protected by parity. */ + volatile uint32_t *par_loc; /**< Address of mapping of parity bits into CPU + * address space. */ + uint32_t par_xor; /**< Bitmask used to alter parity to cause + * intentional parity failure. */ + volatile uint32_t *par_cr_reg; /**< Address of module parity test control register. */ + uint32_t par_cr_test; /**< Mask of bit which cause switch to a test mode. */ + volatile uint32_t *par_st_reg; /**< Optional module parity status register which. */ + uint32_t par_st_clear; /**< Optional value which is written to status register + * to clear error. */ + tms570_selftest_par_fnc_t *partest_fnc; /**< Function which specialized for given kind + * of peripheral/module mechanism testing. */ + volatile void *fnc_data; /**< Pointer to the base of tested peripheral registers. + * It is required by some test functions (CAN and MibSPI) */ +}; + +extern const tms570_selftest_par_desc_t + tms570_selftest_par_het1_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_htu1_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_het2_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_htu2_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_adc1_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_adc2_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_can1_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_can2_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_can3_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_vim_desc; +const tms570_selftest_par_desc_t + tms570_selftest_par_dma_desc; +const tms570_selftest_par_desc_t + tms570_selftest_par_spi1_desc; +const tms570_selftest_par_desc_t + tms570_selftest_par_spi3_desc; +const tms570_selftest_par_desc_t + tms570_selftest_par_spi5_desc; + +extern const tms570_selftest_par_desc_t *const +tms570_selftest_par_list[]; + +extern const int tms570_selftest_par_list_size; + +void tms570_selftest_par_check_std( const tms570_selftest_par_desc_t *desc ); + +void tms570_selftest_par_check_can( const tms570_selftest_par_desc_t *desc ); + +void tms570_selftest_par_check_mibspi( const tms570_selftest_par_desc_t *desc ); + +void tms570_selftest_par_run( + const tms570_selftest_par_desc_t * + const *desc_arr, + int desc_cnt +); + +#endif /* LIBBSP_ARM_TMS570_SELFTEST_PARITY_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h b/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h new file mode 100644 index 0000000000..2beeae8bab --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h @@ -0,0 +1,1114 @@ +/** + * @file tms570lc4357-pins.h + * + * @ingroup tms570 + * + * @brief Specification of individual pins mapping to the package + */ + +/* + * Copyright (c) 2015-2017 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_TMS570LC4357_PINS_H +#define LIBBSP_ARM_TMS570_TMS570LC4357_PINS_H + +#define TMS570_PIN_MMR_ALT_AD2EVT TMS570_BALL_WITH_MMR(80, 0) +#define TMS570_PIN_MMR_ALT_ECAP1 TMS570_BALL_WITH_MMR(80, 1) +#define TMS570_PIN_MMR_ALT_ECAP2 TMS570_BALL_WITH_MMR(80, 2) +#define TMS570_PIN_MMR_ALT_ECAP3 TMS570_BALL_WITH_MMR(80, 3) +#define TMS570_PIN_MMR_ALT_ECAP4 TMS570_BALL_WITH_MMR(81, 0) +#define TMS570_PIN_MMR_ALT_ECAP5 TMS570_BALL_WITH_MMR(81, 1) +#define TMS570_PIN_MMR_ALT_ECAP6 TMS570_BALL_WITH_MMR(81, 2) +#define TMS570_PIN_MMR_ALT_GIOA_0 TMS570_BALL_WITH_MMR(83, 3) +#define TMS570_PIN_MMR_ALT_GIOA_1 TMS570_BALL_WITH_MMR(84, 0) +#define TMS570_PIN_MMR_ALT_GIOA_2 TMS570_BALL_WITH_MMR(84, 1) +#define TMS570_PIN_MMR_ALT_GIOA_3 TMS570_BALL_WITH_MMR(84, 2) +#define TMS570_PIN_MMR_ALT_GIOA_4 TMS570_BALL_WITH_MMR(84, 3) +#define TMS570_PIN_MMR_ALT_GIOA_5 TMS570_BALL_WITH_MMR(85, 0) +#define TMS570_PIN_MMR_ALT_GIOA_6 TMS570_BALL_WITH_MMR(85, 1) +#define TMS570_PIN_MMR_ALT_GIOA_7 TMS570_BALL_WITH_MMR(85, 2) +#define TMS570_PIN_MMR_ALT_GIOB_0 TMS570_BALL_WITH_MMR(85, 3) +#define TMS570_PIN_MMR_ALT_GIOB_1 TMS570_BALL_WITH_MMR(86, 0) +#define TMS570_PIN_MMR_ALT_GIOB_2 TMS570_BALL_WITH_MMR(86, 1) +#define TMS570_PIN_MMR_ALT_GIOB_3 TMS570_BALL_WITH_MMR(86, 2) +#define TMS570_PIN_MMR_ALT_GIOB_4 TMS570_BALL_WITH_MMR(86, 3) +#define TMS570_PIN_MMR_ALT_GIOB_5 TMS570_BALL_WITH_MMR(87, 0) +#define TMS570_PIN_MMR_ALT_GIOB_6 TMS570_BALL_WITH_MMR(87, 1) +#define TMS570_PIN_MMR_ALT_GIOB_7 TMS570_BALL_WITH_MMR(87, 2) +#define TMS570_PIN_MMR_ALT_HET1_17 TMS570_BALL_WITH_MMR(92, 0) +#define TMS570_PIN_MMR_ALT_HET1_19 TMS570_BALL_WITH_MMR(92, 1) +#define TMS570_PIN_MMR_ALT_HET1_21 TMS570_BALL_WITH_MMR(92, 2) +#define TMS570_PIN_MMR_ALT_HET1_23 TMS570_BALL_WITH_MMR(92, 3) +#define TMS570_PIN_MMR_ALT_HET1_25 TMS570_BALL_WITH_MMR(93, 0) +#define TMS570_PIN_MMR_ALT_HET1_27 TMS570_BALL_WITH_MMR(93, 1) +#define TMS570_PIN_MMR_ALT_HET1_29 TMS570_BALL_WITH_MMR(93, 2) +#define TMS570_PIN_MMR_ALT_HET1_31 TMS570_BALL_WITH_MMR(93, 3) +#define TMS570_PIN_MMR_ALT_HET2_00 TMS570_BALL_WITH_MMR(94, 0) +#define TMS570_PIN_MMR_ALT_HET2_01 TMS570_BALL_WITH_MMR(94, 1) +#define TMS570_PIN_MMR_ALT_HET2_02 TMS570_BALL_WITH_MMR(94, 2) +#define TMS570_PIN_MMR_ALT_HET2_03 TMS570_BALL_WITH_MMR(94, 3) +#define TMS570_PIN_MMR_ALT_HET2_04 TMS570_BALL_WITH_MMR(95, 0) +#define TMS570_PIN_MMR_ALT_HET2_05 TMS570_BALL_WITH_MMR(95, 1) +#define TMS570_PIN_MMR_ALT_HET2_06 TMS570_BALL_WITH_MMR(95, 2) +#define TMS570_PIN_MMR_ALT_HET2_07 TMS570_BALL_WITH_MMR(95, 3) +#define TMS570_PIN_MMR_ALT_HET2_08 TMS570_BALL_WITH_MMR(96, 0) +#define TMS570_PIN_MMR_ALT_HET2_09 TMS570_BALL_WITH_MMR(96, 1) +#define TMS570_PIN_MMR_ALT_HET2_10 TMS570_BALL_WITH_MMR(96, 2) +#define TMS570_PIN_MMR_ALT_HET2_11 TMS570_BALL_WITH_MMR(96, 3) +#define TMS570_PIN_MMR_ALT_HET2_12 TMS570_BALL_WITH_MMR(97, 0) +#define TMS570_PIN_MMR_ALT_HET2_13 TMS570_BALL_WITH_MMR(97, 1) +#define TMS570_PIN_MMR_ALT_HET2_14 TMS570_BALL_WITH_MMR(97, 2) +#define TMS570_PIN_MMR_ALT_HET2_15 TMS570_BALL_WITH_MMR(97, 3) +#define TMS570_PIN_MMR_ALT_HET2_16 TMS570_BALL_WITH_MMR(98, 0) +#define TMS570_PIN_MMR_ALT_HET2_18 TMS570_BALL_WITH_MMR(98, 1) +#define TMS570_PIN_MMR_ALT_HET2_20 TMS570_BALL_WITH_MMR(98, 2) +#define TMS570_PIN_MMR_ALT_HET2_22 TMS570_BALL_WITH_MMR(98, 3) +#define TMS570_PIN_MMR_ALT_MDIO TMS570_BALL_WITH_MMR(87, 3) +#define TMS570_PIN_MMR_ALT_MIBSPI1NCS_4 TMS570_BALL_WITH_MMR(88, 0) +#define TMS570_PIN_MMR_ALT_MIBSPI1NCS_5 TMS570_BALL_WITH_MMR(88, 1) +#define TMS570_PIN_MMR_ALT_MIBSPI2NCS_1 TMS570_BALL_WITH_MMR(88, 2) +#define TMS570_PIN_MMR_ALT_MII_COL TMS570_BALL_WITH_MMR(89, 2) +#define TMS570_PIN_MMR_ALT_MII_CRS TMS570_BALL_WITH_MMR(89, 3) +#define TMS570_PIN_MMR_ALT_MII_RXCLK TMS570_BALL_WITH_MMR(90, 2) +#define TMS570_PIN_MMR_ALT_MII_RXD_0 TMS570_BALL_WITH_MMR(90, 3) +#define TMS570_PIN_MMR_ALT_MII_RXD_1 TMS570_BALL_WITH_MMR(91, 0) +#define TMS570_PIN_MMR_ALT_MII_RXD_2 TMS570_BALL_WITH_MMR(91, 1) +#define TMS570_PIN_MMR_ALT_MII_RXD_3 TMS570_BALL_WITH_MMR(91, 2) +#define TMS570_PIN_MMR_ALT_MII_RX_DV TMS570_BALL_WITH_MMR(90, 0) +#define TMS570_PIN_MMR_ALT_MII_RX_ER TMS570_BALL_WITH_MMR(90, 1) +#define TMS570_PIN_MMR_ALT_MII_TX_CLK TMS570_BALL_WITH_MMR(91, 3) +#define TMS570_PIN_MMR_ALT_eQEP1A TMS570_BALL_WITH_MMR(81, 3) +#define TMS570_PIN_MMR_ALT_eQEP1B TMS570_BALL_WITH_MMR(82, 0) +#define TMS570_PIN_MMR_ALT_eQEP1I TMS570_BALL_WITH_MMR(82, 1) +#define TMS570_PIN_MMR_ALT_eQEP1S TMS570_BALL_WITH_MMR(82, 2) +#define TMS570_PIN_MMR_ALT_eQEP2A TMS570_BALL_WITH_MMR(82, 3) +#define TMS570_PIN_MMR_ALT_eQEP2B TMS570_BALL_WITH_MMR(83, 0) +#define TMS570_PIN_MMR_ALT_eQEP2I TMS570_BALL_WITH_MMR(83, 1) +#define TMS570_PIN_MMR_ALT_eQEP2S TMS570_BALL_WITH_MMR(83, 2) +#define TMS570_PIN_MMR_ALT_nTZ1_1 TMS570_BALL_WITH_MMR(99, 0) +#define TMS570_PIN_MMR_ALT_nTZ1_2 TMS570_BALL_WITH_MMR(99, 1) +#define TMS570_PIN_MMR_ALT_nTZ1_3 TMS570_BALL_WITH_MMR(99, 2) + +#define TMS570_BALL_N19 TMS570_BALL_WITH_MMR(0, 0) +#define TMS570_BALL_N19_AD1EVT TMS570_PIN_AND_FNC(TMS570_BALL_N19, 0) +#define TMS570_BALL_N19_MII_RX_ER TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N19, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RX_ER, 1)) +#define TMS570_BALL_N19_RMII_RX_ER TMS570_PIN_AND_FNC(TMS570_BALL_N19, 3) +#define TMS570_BALL_N19_nTZ1_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N19, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_nTZ1_1, 0)) + +#define TMS570_BALL_D4 TMS570_BALL_WITH_MMR(0, 1) +#define TMS570_BALL_D4_EMIF_ADDR_00 TMS570_PIN_AND_FNC(TMS570_BALL_D4, 0) +#define TMS570_BALL_D4_HET2_01 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D4, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_01, 1)) + +#define TMS570_BALL_D5 TMS570_BALL_WITH_MMR(0, 2) +#define TMS570_BALL_D5_EMIF_ADDR_01 TMS570_PIN_AND_FNC(TMS570_BALL_D5, 0) +#define TMS570_BALL_D5_HET2_03 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D5, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_03, 1)) + +#define TMS570_BALL_C4 TMS570_BALL_WITH_MMR(0, 3) +#define TMS570_BALL_C4_EMIF_ADDR_06 TMS570_PIN_AND_FNC(TMS570_BALL_C4, 0) +#define TMS570_BALL_C4_RTP_DATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_C4, 1) +#define TMS570_BALL_C4_HET2_11 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C4, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_11, 1)) + +#define TMS570_BALL_C5 TMS570_BALL_WITH_MMR(1, 0) +#define TMS570_BALL_C5_EMIF_ADDR_07 TMS570_PIN_AND_FNC(TMS570_BALL_C5, 0) +#define TMS570_BALL_C5_RTP_DATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_C5, 1) +#define TMS570_BALL_C5_HET2_13 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C5, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_13, 1)) + +#define TMS570_BALL_C6 TMS570_BALL_WITH_MMR(1, 1) +#define TMS570_BALL_C6_EMIF_ADDR_08 TMS570_PIN_AND_FNC(TMS570_BALL_C6, 0) +#define TMS570_BALL_C6_RTP_DATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_C6, 1) +#define TMS570_BALL_C6_HET2_15 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C6, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_15, 1)) + +#define TMS570_BALL_C7 TMS570_BALL_WITH_MMR(1, 2) +#define TMS570_BALL_C7_EMIF_ADDR_09 TMS570_PIN_AND_FNC(TMS570_BALL_C7, 0) +#define TMS570_BALL_C7_RTP_DATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_C7, 1) + +#define TMS570_BALL_C8 TMS570_BALL_WITH_MMR(1, 3) +#define TMS570_BALL_C8_EMIF_ADDR_10 TMS570_PIN_AND_FNC(TMS570_BALL_C8, 0) +#define TMS570_BALL_C8_RTP_DATA_09 TMS570_PIN_AND_FNC(TMS570_BALL_C8, 1) + +#define TMS570_BALL_C9 TMS570_BALL_WITH_MMR(2, 0) +#define TMS570_BALL_C9_EMIF_ADDR_11 TMS570_PIN_AND_FNC(TMS570_BALL_C9, 0) +#define TMS570_BALL_C9_RTP_DATA_08 TMS570_PIN_AND_FNC(TMS570_BALL_C9, 1) + +#define TMS570_BALL_C10 TMS570_BALL_WITH_MMR(2, 1) +#define TMS570_BALL_C10_EMIF_ADDR_12 TMS570_PIN_AND_FNC(TMS570_BALL_C10, 0) +#define TMS570_BALL_C10_RTP_DATA_06 TMS570_PIN_AND_FNC(TMS570_BALL_C10, 1) + +#define TMS570_BALL_C11 TMS570_BALL_WITH_MMR(2, 2) +#define TMS570_BALL_C11_EMIF_ADDR_13 TMS570_PIN_AND_FNC(TMS570_BALL_C11, 0) +#define TMS570_BALL_C11_RTP_DATA_05 TMS570_PIN_AND_FNC(TMS570_BALL_C11, 1) + +#define TMS570_BALL_C12 TMS570_BALL_WITH_MMR(2, 3) +#define TMS570_BALL_C12_EMIF_ADDR_14 TMS570_PIN_AND_FNC(TMS570_BALL_C12, 0) +#define TMS570_BALL_C12_RTP_DATA_04 TMS570_PIN_AND_FNC(TMS570_BALL_C12, 1) + +#define TMS570_BALL_C13 TMS570_BALL_WITH_MMR(3, 0) +#define TMS570_BALL_C13_EMIF_ADDR_15 TMS570_PIN_AND_FNC(TMS570_BALL_C13, 0) +#define TMS570_BALL_C13_RTP_DATA_03 TMS570_PIN_AND_FNC(TMS570_BALL_C13, 1) + +#define TMS570_BALL_D14 TMS570_BALL_WITH_MMR(3, 1) +#define TMS570_BALL_D14_EMIF_ADDR_16 TMS570_PIN_AND_FNC(TMS570_BALL_D14, 0) +#define TMS570_BALL_D14_RTP_DATA_02 TMS570_PIN_AND_FNC(TMS570_BALL_D14, 1) + +#define TMS570_BALL_C14 TMS570_BALL_WITH_MMR(3, 2) +#define TMS570_BALL_C14_EMIF_ADDR_17 TMS570_PIN_AND_FNC(TMS570_BALL_C14, 0) +#define TMS570_BALL_C14_RTP_DATA_01 TMS570_PIN_AND_FNC(TMS570_BALL_C14, 1) + +#define TMS570_BALL_D15 TMS570_BALL_WITH_MMR(3, 3) +#define TMS570_BALL_D15_EMIF_ADDR_18 TMS570_PIN_AND_FNC(TMS570_BALL_D15, 0) +#define TMS570_BALL_D15_RTP_DATA_00 TMS570_PIN_AND_FNC(TMS570_BALL_D15, 1) + +#define TMS570_BALL_C15 TMS570_BALL_WITH_MMR(4, 0) +#define TMS570_BALL_C15_EMIF_ADDR_19 TMS570_PIN_AND_FNC(TMS570_BALL_C15, 0) +#define TMS570_BALL_C15_RTP_nENA TMS570_PIN_AND_FNC(TMS570_BALL_C15, 1) + +#define TMS570_BALL_C16 TMS570_BALL_WITH_MMR(4, 1) +#define TMS570_BALL_C16_EMIF_ADDR_20 TMS570_PIN_AND_FNC(TMS570_BALL_C16, 0) +#define TMS570_BALL_C16_RTP_nSYNC TMS570_PIN_AND_FNC(TMS570_BALL_C16, 1) + +#define TMS570_BALL_C17 TMS570_BALL_WITH_MMR(4, 2) +#define TMS570_BALL_C17_EMIF_ADDR_21 TMS570_PIN_AND_FNC(TMS570_BALL_C17, 0) +#define TMS570_BALL_C17_RTP_CLK TMS570_PIN_AND_FNC(TMS570_BALL_C17, 1) + +#define TMS570_BALL_D16 TMS570_BALL_WITH_MMR(8, 3) +#define TMS570_BALL_D16_EMIF_BA_1 TMS570_PIN_AND_FNC(TMS570_BALL_D16, 0) +#define TMS570_BALL_D16_ TMS570_PIN_AND_FNC(TMS570_BALL_D16, 1) +#define TMS570_BALL_D16_HET2_05 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D16, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_05, 1)) + +#define TMS570_BALL_K3 TMS570_BALL_WITH_MMR(9, 0) +#define TMS570_BALL_K3_EMIF_CLK TMS570_PIN_AND_FNC(TMS570_BALL_K3, 1) +#define TMS570_BALL_K3_ECLK2 TMS570_PIN_AND_FNC(TMS570_BALL_K3, 2) + +#define TMS570_BALL_R4 TMS570_BALL_WITH_MMR(9, 1) +#define TMS570_BALL_R4_EMIF_nCAS TMS570_PIN_AND_FNC(TMS570_BALL_R4, 0) +#define TMS570_BALL_R4_GIOB_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R4, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_3, 1)) + +#define TMS570_BALL_N17 TMS570_BALL_WITH_MMR(9, 2) +#define TMS570_BALL_N17_EMIF_nCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_N17, 0) +#define TMS570_BALL_N17_RTP_DATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_N17, 1) +#define TMS570_BALL_N17_HET2_07 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N17, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_07, 1)) + +#define TMS570_BALL_L17 TMS570_BALL_WITH_MMR(9, 3) +#define TMS570_BALL_L17_EMIF_nCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_L17, 0) +#define TMS570_BALL_L17_GIOB_4 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_L17, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_4, 1)) + +#define TMS570_BALL_K17 TMS570_BALL_WITH_MMR(10, 0) +#define TMS570_BALL_K17_EMIF_nCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_K17, 0) +#define TMS570_BALL_K17_RTP_DATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_K17, 1) +#define TMS570_BALL_K17_HET2_09 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_K17, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_09, 1)) + +#define TMS570_BALL_M17 TMS570_BALL_WITH_MMR(10, 1) +#define TMS570_BALL_M17_EMIF_nCSl_4 TMS570_PIN_AND_FNC(TMS570_BALL_M17, 0) +#define TMS570_BALL_M17_RTP_DATA_07 TMS570_PIN_AND_FNC(TMS570_BALL_M17, 1) +#define TMS570_BALL_M17_GIOB_5 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_M17, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_5, 1)) + +#define TMS570_BALL_R3 TMS570_BALL_WITH_MMR(10, 2) +#define TMS570_BALL_R3_EMIF_nRAS TMS570_PIN_AND_FNC(TMS570_BALL_R3, 0) +#define TMS570_BALL_R3_GIOB_6 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R3, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_6, 1)) + +#define TMS570_BALL_P3 TMS570_BALL_WITH_MMR(10, 3) +#define TMS570_BALL_P3_EMIF_nWAIT TMS570_PIN_AND_FNC(TMS570_BALL_P3, 0) +#define TMS570_BALL_P3_GIOB_7 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_P3, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_7, 1)) + +#define TMS570_BALL_D17 TMS570_BALL_WITH_MMR(11, 0) +#define TMS570_BALL_D17_EMIF_nWE TMS570_PIN_AND_FNC(TMS570_BALL_D17, 0) +#define TMS570_BALL_D17_EMIF_RNW TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D17, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_J1, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_E9 TMS570_BALL_WITH_MMR(11, 1) +#define TMS570_BALL_E9_ETMDATA_08 TMS570_PIN_AND_FNC(TMS570_BALL_E9, 0) +#define TMS570_BALL_E9_EMIF_ADDR_05 TMS570_PIN_AND_FNC(TMS570_BALL_E9, 1) + +#define TMS570_BALL_E8 TMS570_BALL_WITH_MMR(11, 2) +#define TMS570_BALL_E8_ETMDATA_09 TMS570_PIN_AND_FNC(TMS570_BALL_E8, 0) +#define TMS570_BALL_E8_EMIF_ADDR_04 TMS570_PIN_AND_FNC(TMS570_BALL_E8, 1) + +#define TMS570_BALL_E7 TMS570_BALL_WITH_MMR(11, 3) +#define TMS570_BALL_E7_ETMDATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_E7, 0) +#define TMS570_BALL_E7_EMIF_ADDR_03 TMS570_PIN_AND_FNC(TMS570_BALL_E7, 1) + +#define TMS570_BALL_E6 TMS570_BALL_WITH_MMR(12, 0) +#define TMS570_BALL_E6_ETMDATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_E6, 0) +#define TMS570_BALL_E6_EMIF_ADDR_02 TMS570_PIN_AND_FNC(TMS570_BALL_E6, 1) + +#define TMS570_BALL_E13 TMS570_BALL_WITH_MMR(12, 1) +#define TMS570_BALL_E13_ETMDATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_E13, 0) +#define TMS570_BALL_E13_EMIF_BA_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E13, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_J4, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_E12 TMS570_BALL_WITH_MMR(12, 2) +#define TMS570_BALL_E12_ETMDATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_E12, 0) +#define TMS570_BALL_E12_EMIF_nOE TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E12, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_A13, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_E11 TMS570_BALL_WITH_MMR(12, 3) +#define TMS570_BALL_E11_ETMDATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_E11, 0) +#define TMS570_BALL_E11_EMIF_nDQM_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E11, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_P2, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_E10 TMS570_BALL_WITH_MMR(13, 0) +#define TMS570_BALL_E10_ETMDATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_E10, 0) +#define TMS570_BALL_E10_EMIF_nDQM_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E10, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_B13, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_K15 TMS570_BALL_WITH_MMR(13, 1) +#define TMS570_BALL_K15_ETMDATA_16 TMS570_PIN_AND_FNC(TMS570_BALL_K15, 0) +#define TMS570_BALL_K15_EMIF_DATA_00 TMS570_PIN_AND_FNC(TMS570_BALL_K15, 1) + +#define TMS570_BALL_L15 TMS570_BALL_WITH_MMR(13, 2) +#define TMS570_BALL_L15_ETMDATA_17 TMS570_PIN_AND_FNC(TMS570_BALL_L15, 0) +#define TMS570_BALL_L15_EMIF_DATA_01 TMS570_PIN_AND_FNC(TMS570_BALL_L15, 1) + +#define TMS570_BALL_M15 TMS570_BALL_WITH_MMR(13, 3) +#define TMS570_BALL_M15_ETMDATA_18 TMS570_PIN_AND_FNC(TMS570_BALL_M15, 0) +#define TMS570_BALL_M15_EMIF_DATA_02 TMS570_PIN_AND_FNC(TMS570_BALL_M15, 1) + +#define TMS570_BALL_N15 TMS570_BALL_WITH_MMR(14, 0) +#define TMS570_BALL_N15_ETMDATA_19 TMS570_PIN_AND_FNC(TMS570_BALL_N15, 0) +#define TMS570_BALL_N15_EMIF_DATA_03 TMS570_PIN_AND_FNC(TMS570_BALL_N15, 1) + +#define TMS570_BALL_E5 TMS570_BALL_WITH_MMR(14, 1) +#define TMS570_BALL_E5_ETMDATA_20 TMS570_PIN_AND_FNC(TMS570_BALL_E5, 0) +#define TMS570_BALL_E5_EMIF_DATA_04 TMS570_PIN_AND_FNC(TMS570_BALL_E5, 1) + +#define TMS570_BALL_F5 TMS570_BALL_WITH_MMR(14, 2) +#define TMS570_BALL_F5_ETMDATA_21 TMS570_PIN_AND_FNC(TMS570_BALL_F5, 0) +#define TMS570_BALL_F5_EMIF_DATA_05 TMS570_PIN_AND_FNC(TMS570_BALL_F5, 1) + +#define TMS570_BALL_G5 TMS570_BALL_WITH_MMR(14, 3) +#define TMS570_BALL_G5_ETMDATA_22 TMS570_PIN_AND_FNC(TMS570_BALL_G5, 0) +#define TMS570_BALL_G5_EMIF_DATA_06 TMS570_PIN_AND_FNC(TMS570_BALL_G5, 1) + +#define TMS570_BALL_K5 TMS570_BALL_WITH_MMR(15, 0) +#define TMS570_BALL_K5_ETMDATA_23 TMS570_PIN_AND_FNC(TMS570_BALL_K5, 0) +#define TMS570_BALL_K5_EMIF_DATA_07 TMS570_PIN_AND_FNC(TMS570_BALL_K5, 1) + +#define TMS570_BALL_L5 TMS570_BALL_WITH_MMR(15, 1) +#define TMS570_BALL_L5_ETMDATA_24 TMS570_PIN_AND_FNC(TMS570_BALL_L5, 0) +#define TMS570_BALL_L5_EMIF_DATA_08 TMS570_PIN_AND_FNC(TMS570_BALL_L5, 1) +#define TMS570_BALL_L5_HET2_24 TMS570_PIN_AND_FNC(TMS570_BALL_L5, 2) +#define TMS570_BALL_L5_MIBSPI5NCS_4 TMS570_PIN_AND_FNC(TMS570_BALL_L5, 3) + +#define TMS570_BALL_M5 TMS570_BALL_WITH_MMR(15, 2) +#define TMS570_BALL_M5_ETMDATA_25 TMS570_PIN_AND_FNC(TMS570_BALL_M5, 0) +#define TMS570_BALL_M5_EMIF_DATA_09 TMS570_PIN_AND_FNC(TMS570_BALL_M5, 1) +#define TMS570_BALL_M5_HET2_25 TMS570_PIN_AND_FNC(TMS570_BALL_M5, 2) +#define TMS570_BALL_M5_MIBSPI5NCS_5 TMS570_PIN_AND_FNC(TMS570_BALL_M5, 3) + +#define TMS570_BALL_N5 TMS570_BALL_WITH_MMR(15, 3) +#define TMS570_BALL_N5_ETMDATA_26 TMS570_PIN_AND_FNC(TMS570_BALL_N5, 0) +#define TMS570_BALL_N5_EMIF_DATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_N5, 1) +#define TMS570_BALL_N5_HET2_26 TMS570_PIN_AND_FNC(TMS570_BALL_N5, 2) + +#define TMS570_BALL_P5 TMS570_BALL_WITH_MMR(16, 0) +#define TMS570_BALL_P5_ETMDATA_27 TMS570_PIN_AND_FNC(TMS570_BALL_P5, 0) +#define TMS570_BALL_P5_EMIF_DATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_P5, 1) +#define TMS570_BALL_P5_HET2_27 TMS570_PIN_AND_FNC(TMS570_BALL_P5, 2) + +#define TMS570_BALL_R5 TMS570_BALL_WITH_MMR(16, 1) +#define TMS570_BALL_R5_ETMDATA_28 TMS570_PIN_AND_FNC(TMS570_BALL_R5, 0) +#define TMS570_BALL_R5_EMIF_DATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_R5, 1) +#define TMS570_BALL_R5_HET2_28 TMS570_PIN_AND_FNC(TMS570_BALL_R5, 2) +#define TMS570_BALL_R5_GIOA_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R5, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_0, 1)) + +#define TMS570_BALL_R6 TMS570_BALL_WITH_MMR(16, 2) +#define TMS570_BALL_R6_ETMDATA_29 TMS570_PIN_AND_FNC(TMS570_BALL_R6, 0) +#define TMS570_BALL_R6_EMIF_DATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_R6, 1) +#define TMS570_BALL_R6_HET2_29 TMS570_PIN_AND_FNC(TMS570_BALL_R6, 2) +#define TMS570_BALL_R6_GIOA_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R6, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_1, 1)) + +#define TMS570_BALL_R7 TMS570_BALL_WITH_MMR(16, 3) +#define TMS570_BALL_R7_ETMDATA_30 TMS570_PIN_AND_FNC(TMS570_BALL_R7, 0) +#define TMS570_BALL_R7_EMIF_DATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_R7, 1) +#define TMS570_BALL_R7_HET2_30 TMS570_PIN_AND_FNC(TMS570_BALL_R7, 2) +#define TMS570_BALL_R7_GIOA_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R7, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_3, 1)) + +#define TMS570_BALL_R8 TMS570_BALL_WITH_MMR(17, 0) +#define TMS570_BALL_R8_ETMDATA_31 TMS570_PIN_AND_FNC(TMS570_BALL_R8, 0) +#define TMS570_BALL_R8_EMIF_DATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_R8, 1) +#define TMS570_BALL_R8_HET2_31 TMS570_PIN_AND_FNC(TMS570_BALL_R8, 2) +#define TMS570_BALL_R8_GIOA_4 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R8, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_4, 1)) + +#define TMS570_BALL_R9 TMS570_BALL_WITH_MMR(17, 1) +#define TMS570_BALL_R9_ETMTRACECLKIN TMS570_PIN_AND_FNC(TMS570_BALL_R9, 0) +#define TMS570_BALL_R9_EXTCLKIN2 TMS570_PIN_AND_FNC(TMS570_BALL_R9, 1) +#define TMS570_BALL_R9_GIOA_5 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R9, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_5, 1)) + +#define TMS570_BALL_R10 TMS570_BALL_WITH_MMR(17, 2) +#define TMS570_BALL_R10_ETMTRACECLKOUT TMS570_PIN_AND_FNC(TMS570_BALL_R10, 0) +#define TMS570_BALL_R10_GIOA_6 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R10, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_6, 1)) + +#define TMS570_BALL_R11 TMS570_BALL_WITH_MMR(17, 3) +#define TMS570_BALL_R11_ETMTRACECTL TMS570_PIN_AND_FNC(TMS570_BALL_R11, 0) +#define TMS570_BALL_R11_GIOA_7 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R11, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_7, 1)) + +#define TMS570_BALL_B15 TMS570_BALL_WITH_MMR(18, 0) +#define TMS570_BALL_B15_FRAYTX1 TMS570_PIN_AND_FNC(TMS570_BALL_B15, 0) +#define TMS570_BALL_B15_GIOA_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B15, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_2, 1)) + +#define TMS570_BALL_B8 TMS570_BALL_WITH_MMR(18, 1) +#define TMS570_BALL_B8_FRAYTX2 TMS570_PIN_AND_FNC(TMS570_BALL_B8, 0) +#define TMS570_BALL_B8_GIOB_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B8, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_0, 1)) + +#define TMS570_BALL_B16 TMS570_BALL_WITH_MMR(18, 2) +#define TMS570_BALL_B16_FRAYTXEN1 TMS570_PIN_AND_FNC(TMS570_BALL_B16, 0) +#define TMS570_BALL_B16_GIOB_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B16, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_1, 1)) + +#define TMS570_BALL_B9 TMS570_BALL_WITH_MMR(18, 3) +#define TMS570_BALL_B9_FRAYTXEN2 TMS570_PIN_AND_FNC(TMS570_BALL_B9, 0) +#define TMS570_BALL_B9_GIOB_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B9, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_2, 1)) + +#define TMS570_BALL_C1 TMS570_BALL_WITH_MMR(19, 0) +#define TMS570_BALL_C1_GIOA_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C1, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_2, 0)) +#define TMS570_BALL_C1_HET2_00 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C1, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_00, 1)) +#define TMS570_BALL_C1_eQEP2I TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C1, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP2I, 1)) + +#define TMS570_BALL_E1 TMS570_BALL_WITH_MMR(19, 1) +#define TMS570_BALL_E1_GIOA_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E1, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_3, 0)) +#define TMS570_BALL_E1_HET2_02 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E1, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_02, 1)) + +#define TMS570_BALL_B5 TMS570_BALL_WITH_MMR(19, 2) +#define TMS570_BALL_B5_GIOA_5 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B5, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_5, 0)) +#define TMS570_BALL_B5_EXTCLKIN TMS570_PIN_AND_FNC(TMS570_BALL_B5, 3) +#define TMS570_BALL_B5_ePWM1A TMS570_PIN_AND_FNC(TMS570_BALL_B5, 5) + +#define TMS570_BALL_H3 TMS570_BALL_WITH_MMR(19, 3) +#define TMS570_BALL_H3_GIOA_6 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H3, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_6, 0)) +#define TMS570_BALL_H3_HET2_04 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H3, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_04, 1)) +#define TMS570_BALL_H3_ePWM1B TMS570_PIN_AND_FNC(TMS570_BALL_H3, 5) + +#define TMS570_BALL_M1 TMS570_BALL_WITH_MMR(20, 0) +#define TMS570_BALL_M1_GIOA_7 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_M1, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_7, 0)) +#define TMS570_BALL_M1_HET2_06 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_M1, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_06, 1)) +#define TMS570_BALL_M1_ePWM2A TMS570_PIN_AND_FNC(TMS570_BALL_M1, 5) + +#define TMS570_BALL_F2 TMS570_BALL_WITH_MMR(20, 1) +#define TMS570_BALL_F2_GIOB_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F2, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_2, 0)) +#define TMS570_BALL_F2_DCAN4TX TMS570_PIN_AND_FNC(TMS570_BALL_F2, 3) + +#define TMS570_BALL_W10 TMS570_BALL_WITH_MMR(20, 2) +#define TMS570_BALL_W10_GIOB_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W10, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_3, 0)) +#define TMS570_BALL_W10_DCAN4RX TMS570_PIN_AND_FNC(TMS570_BALL_W10, 3) + +#define TMS570_BALL_J2 TMS570_BALL_WITH_MMR(20, 3) +#define TMS570_BALL_J2_GIOB_6 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J2, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_6, 0)) +#define TMS570_BALL_J2_nERROR1 TMS570_PIN_AND_FNC(TMS570_BALL_J2, 1) + +#define TMS570_BALL_F1 TMS570_BALL_WITH_MMR(21, 0) +#define TMS570_BALL_F1_GIOB_7 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F1, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_7, 0)) +#define TMS570_BALL_F1_nERROR2 TMS570_PIN_AND_FNC(TMS570_BALL_F1, 1) +#define TMS570_BALL_F1_nTZ1_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F1, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_nTZ1_2, 0)) + +#define TMS570_BALL_R2 TMS570_BALL_WITH_MMR(21, 1) +#define TMS570_BALL_R2_MIBSPI1NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_R2, 0) +#define TMS570_BALL_R2_MIBSPI1SOMI_1 TMS570_PIN_AND_FNC(TMS570_BALL_R2, 1) +#define TMS570_BALL_R2_MII_TXD_2 TMS570_PIN_AND_FNC(TMS570_BALL_R2, 2) +#define TMS570_BALL_R2_ECAP6 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R2, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_ECAP6, 1)) + +#define TMS570_BALL_F3 TMS570_BALL_WITH_MMR(21, 2) +#define TMS570_BALL_F3_MIBSPI1NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_F3, 0) +#define TMS570_BALL_F3_MII_COL TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F3, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_COL, 1)) +#define TMS570_BALL_F3_HET1_17 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F3, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_17, 1)) +#define TMS570_BALL_F3_eQEP1S TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F3, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP1S, 1)) + +#define TMS570_BALL_G3 TMS570_BALL_WITH_MMR(21, 3) +#define TMS570_BALL_G3_MIBSPI1NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_G3, 0) +#define TMS570_BALL_G3_MDIO TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G3, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MDIO, 1)) +#define TMS570_BALL_G3_HET1_19 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G3, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_19, 1)) + +#define TMS570_BALL_J3 TMS570_BALL_WITH_MMR(22, 0) +#define TMS570_BALL_J3_MIBSPI1NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_J3, 0) +#define TMS570_BALL_J3_HET1_21 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J3, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_21, 1)) +#define TMS570_BALL_J3_nTZ1_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J3, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_nTZ1_3, 0)) + +#define TMS570_BALL_G19 TMS570_BALL_WITH_MMR(22, 1) +#define TMS570_BALL_G19_MIBSPI1NENA TMS570_PIN_AND_FNC(TMS570_BALL_G19, 0) +#define TMS570_BALL_G19_MII_RXD_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G19, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RXD_2, 1)) +#define TMS570_BALL_G19_HET1_23 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G19, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_23, 1)) +#define TMS570_BALL_G19_ECAP4 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G19, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_ECAP4, 1)) + +#define TMS570_BALL_V9 TMS570_BALL_WITH_MMR(22, 2) +#define TMS570_BALL_V9_MIBSPI3CLK TMS570_PIN_AND_FNC(TMS570_BALL_V9, 0) +#define TMS570_BALL_V9_AD1EXT_SEL_01 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V9, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_H17, 4) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_V9_eQEP1A TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V9, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP1A, 1)) + +#define TMS570_BALL_V10 TMS570_BALL_WITH_MMR(22, 3) +#define TMS570_BALL_V10_MIBSPI3NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_V10, 0) +#define TMS570_BALL_V10_AD2EVT TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V10, 1), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_AD2EVT, 1)) +#define TMS570_BALL_V10_eQEP1I TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V10, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP1I, 1)) + +#define TMS570_BALL_V5 TMS570_BALL_WITH_MMR(23, 0) +#define TMS570_BALL_V5_MIBSPI3NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_V5, 0) +#define TMS570_BALL_V5_MDCLK TMS570_PIN_AND_FNC(TMS570_BALL_V5, 2) +#define TMS570_BALL_V5_HET1_25 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V5, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_25, 1)) + +#define TMS570_BALL_B2 TMS570_BALL_WITH_MMR(23, 1) +#define TMS570_BALL_B2_MIBSPI3NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_B2, 0) +#define TMS570_BALL_B2_I2C1_SDA TMS570_PIN_AND_FNC(TMS570_BALL_B2, 1) +#define TMS570_BALL_B2_HET1_27 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B2, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_27, 1)) +#define TMS570_BALL_B2_nTZ1_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B2, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_nTZ1_2, 1)) + +#define TMS570_BALL_C3 TMS570_BALL_WITH_MMR(23, 2) +#define TMS570_BALL_C3_MIBSPI3NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_C3, 0) +#define TMS570_BALL_C3_I2C1_SCL TMS570_PIN_AND_FNC(TMS570_BALL_C3, 1) +#define TMS570_BALL_C3_HET1_29 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C3, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_29, 1)) +#define TMS570_BALL_C3_nTZ1_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C3, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_nTZ1_1, 1)) + +#define TMS570_BALL_W9 TMS570_BALL_WITH_MMR(23, 3) +#define TMS570_BALL_W9_MIBSPI3NENA TMS570_PIN_AND_FNC(TMS570_BALL_W9, 0) +#define TMS570_BALL_W9_MIBSPI3NCS_5 TMS570_PIN_AND_FNC(TMS570_BALL_W9, 1) +#define TMS570_BALL_W9_HET1_31 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W9, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_31, 1)) +#define TMS570_BALL_W9_eQEP1B TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W9, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP1B, 1)) + +#define TMS570_BALL_W8 TMS570_BALL_WITH_MMR(24, 0) +#define TMS570_BALL_W8_MIBSPI3SIMO TMS570_PIN_AND_FNC(TMS570_BALL_W8, 0) +#define TMS570_BALL_W8_AD1EXT_SEL_00 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W8, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_E16, 4) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_W8_ECAP3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W8, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_ECAP3, 1)) + +#define TMS570_BALL_V8 TMS570_BALL_WITH_MMR(24, 1) +#define TMS570_BALL_V8_MIBSPI3SOMI TMS570_PIN_AND_FNC(TMS570_BALL_V8, 0) +#define TMS570_BALL_V8_EXT_ENA TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V8, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_G16, 4) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_V8_ECAP2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V8, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_ECAP2, 1)) + +#define TMS570_BALL_H19 TMS570_BALL_WITH_MMR(24, 2) +#define TMS570_BALL_H19_MIBSPI5CLK TMS570_PIN_AND_FNC(TMS570_BALL_H19, 0) +#define TMS570_BALL_H19_DMM_DATA_04 TMS570_PIN_AND_FNC(TMS570_BALL_H19, 1) +#define TMS570_BALL_H19_MII_TXEN TMS570_PIN_AND_FNC(TMS570_BALL_H19, 2) +#define TMS570_BALL_H19_RMII_TXEN TMS570_PIN_AND_FNC(TMS570_BALL_H19, 3) + +#define TMS570_BALL_E19 TMS570_BALL_WITH_MMR(24, 3) +#define TMS570_BALL_E19_MIBSPI5NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_E19, 0) +#define TMS570_BALL_E19_DMM_DATA_05 TMS570_PIN_AND_FNC(TMS570_BALL_E19, 1) +#define TMS570_BALL_E19_ePWM4A TMS570_PIN_AND_FNC(TMS570_BALL_E19, 5) + +#define TMS570_BALL_B6 TMS570_BALL_WITH_MMR(25, 0) +#define TMS570_BALL_B6_MIBSPI5NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_B6, 0) +#define TMS570_BALL_B6_DMM_DATA_06 TMS570_PIN_AND_FNC(TMS570_BALL_B6, 1) + +#define TMS570_BALL_W6 TMS570_BALL_WITH_MMR(25, 1) +#define TMS570_BALL_W6_MIBSPI5NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_W6, 0) +#define TMS570_BALL_W6_DMM_DATA_02 TMS570_PIN_AND_FNC(TMS570_BALL_W6, 1) + +#define TMS570_BALL_T12 TMS570_BALL_WITH_MMR(25, 2) +#define TMS570_BALL_T12_MIBSPI5NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_T12, 0) +#define TMS570_BALL_T12_DMM_DATA_03 TMS570_PIN_AND_FNC(TMS570_BALL_T12, 1) + +#define TMS570_BALL_H18 TMS570_BALL_WITH_MMR(25, 3) +#define TMS570_BALL_H18_MIBSPI5NENA TMS570_PIN_AND_FNC(TMS570_BALL_H18, 0) +#define TMS570_BALL_H18_DMM_DATA_07 TMS570_PIN_AND_FNC(TMS570_BALL_H18, 1) +#define TMS570_BALL_H18_MII_RXD_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H18, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RXD_3, 1)) +#define TMS570_BALL_H18_ECAP5 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H18, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_ECAP5, 1)) + +#define TMS570_BALL_J19 TMS570_BALL_WITH_MMR(26, 0) +#define TMS570_BALL_J19_MIBSPI5SIMO_0 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 0) +#define TMS570_BALL_J19_DMM_DATA_08 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 1) +#define TMS570_BALL_J19_MII_TXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 2) +#define TMS570_BALL_J19_RMII_TXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 3) + +#define TMS570_BALL_E16 TMS570_BALL_WITH_MMR(26, 1) +#define TMS570_BALL_E16_MIBSPI5SIMO_1 TMS570_PIN_AND_FNC(TMS570_BALL_E16, 0) +#define TMS570_BALL_E16_DMM_DATA_09 TMS570_PIN_AND_FNC(TMS570_BALL_E16, 1) +#define TMS570_BALL_E16_AD1EXT_SEL_00 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E16, 4), \ + TMS570_PIN_AND_FNC(TMS570_BALL_W8, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_H17 TMS570_BALL_WITH_MMR(26, 2) +#define TMS570_BALL_H17_MIBSPI5SIMO_2 TMS570_PIN_AND_FNC(TMS570_BALL_H17, 0) +#define TMS570_BALL_H17_DMM_DATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_H17, 1) +#define TMS570_BALL_H17_AD1EXT_SEL_01 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H17, 4), \ + TMS570_PIN_AND_FNC(TMS570_BALL_V9, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_G17 TMS570_BALL_WITH_MMR(26, 3) +#define TMS570_BALL_G17_MIBSPI5SIMO_3 TMS570_PIN_AND_FNC(TMS570_BALL_G17, 0) +#define TMS570_BALL_G17_DMM_DATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_G17, 1) +#define TMS570_BALL_G17_I2C2_SDA TMS570_PIN_AND_FNC(TMS570_BALL_G17, 2) +#define TMS570_BALL_G17_AD1EXT_SEL_02 TMS570_PIN_AND_FNC(TMS570_BALL_G17, 4) + +#define TMS570_BALL_J18 TMS570_BALL_WITH_MMR(27, 0) +#define TMS570_BALL_J18_MIBSPI5SOMI_0 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 0) +#define TMS570_BALL_J18_DMM_DATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 1) +#define TMS570_BALL_J18_MII_TXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 2) +#define TMS570_BALL_J18_RMII_TXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 3) + +#define TMS570_BALL_E17 TMS570_BALL_WITH_MMR(27, 1) +#define TMS570_BALL_E17_MIBSPI5SOMI_1 TMS570_PIN_AND_FNC(TMS570_BALL_E17, 0) +#define TMS570_BALL_E17_DMM_DATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_E17, 1) +#define TMS570_BALL_E17_AD1EXT_SEL_03 TMS570_PIN_AND_FNC(TMS570_BALL_E17, 4) + +#define TMS570_BALL_H16 TMS570_BALL_WITH_MMR(27, 2) +#define TMS570_BALL_H16_MIBSPI5SOMI_2 TMS570_PIN_AND_FNC(TMS570_BALL_H16, 0) +#define TMS570_BALL_H16_DMM_DATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_H16, 1) +#define TMS570_BALL_H16_AD1EXT_SEL_04 TMS570_PIN_AND_FNC(TMS570_BALL_H16, 4) + +#define TMS570_BALL_G16 TMS570_BALL_WITH_MMR(27, 3) +#define TMS570_BALL_G16_MIBSPI5SOMI_3 TMS570_PIN_AND_FNC(TMS570_BALL_G16, 0) +#define TMS570_BALL_G16_DMM_DATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_G16, 1) +#define TMS570_BALL_G16_I2C2_SCL TMS570_PIN_AND_FNC(TMS570_BALL_G16, 2) +#define TMS570_BALL_G16_EXT_ENA TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G16, 4), \ + TMS570_PIN_AND_FNC(TMS570_BALL_V8, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_K18 TMS570_BALL_WITH_MMR(28, 0) +#define TMS570_BALL_K18_HET1_00 TMS570_PIN_AND_FNC(TMS570_BALL_K18, 0) +#define TMS570_BALL_K18_MIBSPI4CLK TMS570_PIN_AND_FNC(TMS570_BALL_K18, 1) +#define TMS570_BALL_K18_ePWM2B TMS570_PIN_AND_FNC(TMS570_BALL_K18, 5) + +#define TMS570_BALL_V2 TMS570_BALL_WITH_MMR(28, 1) +#define TMS570_BALL_V2_HET1_01 TMS570_PIN_AND_FNC(TMS570_BALL_V2, 0) +#define TMS570_BALL_V2_MIBSPI4NENA TMS570_PIN_AND_FNC(TMS570_BALL_V2, 1) +#define TMS570_BALL_V2_HET2_08 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V2, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_08, 1)) +#define TMS570_BALL_V2_eQEP2A TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V2, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP2A, 1)) + +#define TMS570_BALL_W5 TMS570_BALL_WITH_MMR(28, 2) +#define TMS570_BALL_W5_HET1_02 TMS570_PIN_AND_FNC(TMS570_BALL_W5, 0) +#define TMS570_BALL_W5_MIBSPI4SIMO TMS570_PIN_AND_FNC(TMS570_BALL_W5, 1) +#define TMS570_BALL_W5_ePWM3A TMS570_PIN_AND_FNC(TMS570_BALL_W5, 5) + +#define TMS570_BALL_U1 TMS570_BALL_WITH_MMR(28, 3) +#define TMS570_BALL_U1_HET1_03 TMS570_PIN_AND_FNC(TMS570_BALL_U1, 0) +#define TMS570_BALL_U1_MIBSPI4NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_U1, 1) +#define TMS570_BALL_U1_HET2_10 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_U1, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_10, 1)) +#define TMS570_BALL_U1_eQEP2B TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_U1, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP2B, 1)) + +#define TMS570_BALL_B12 TMS570_BALL_WITH_MMR(29, 0) +#define TMS570_BALL_B12_HET1_04 TMS570_PIN_AND_FNC(TMS570_BALL_B12, 0) +#define TMS570_BALL_B12_MIBSPI4NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_B12, 1) +#define TMS570_BALL_B12_ePWM4B TMS570_PIN_AND_FNC(TMS570_BALL_B12, 5) + +#define TMS570_BALL_V6 TMS570_BALL_WITH_MMR(29, 1) +#define TMS570_BALL_V6_HET1_05 TMS570_PIN_AND_FNC(TMS570_BALL_V6, 0) +#define TMS570_BALL_V6_MIBSPI4SOMI TMS570_PIN_AND_FNC(TMS570_BALL_V6, 1) +#define TMS570_BALL_V6_HET2_12 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V6, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_12, 1)) +#define TMS570_BALL_V6_ePWM3B TMS570_PIN_AND_FNC(TMS570_BALL_V6, 5) + +#define TMS570_BALL_W3 TMS570_BALL_WITH_MMR(29, 2) +#define TMS570_BALL_W3_HET1_06 TMS570_PIN_AND_FNC(TMS570_BALL_W3, 0) +#define TMS570_BALL_W3_SCI3RX TMS570_PIN_AND_FNC(TMS570_BALL_W3, 1) +#define TMS570_BALL_W3_ePWM5A TMS570_PIN_AND_FNC(TMS570_BALL_W3, 5) + +#define TMS570_BALL_T1 TMS570_BALL_WITH_MMR(29, 3) +#define TMS570_BALL_T1_HET1_07 TMS570_PIN_AND_FNC(TMS570_BALL_T1, 0) +#define TMS570_BALL_T1_MIBSPI4NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_T1, 1) +#define TMS570_BALL_T1_HET2_14 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_T1, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_14, 1)) +#define TMS570_BALL_T1_ePWM7B TMS570_PIN_AND_FNC(TMS570_BALL_T1, 5) + +#define TMS570_BALL_E18 TMS570_BALL_WITH_MMR(30, 0) +#define TMS570_BALL_E18_HET1_08 TMS570_PIN_AND_FNC(TMS570_BALL_E18, 0) +#define TMS570_BALL_E18_MIBSPI1SIMO_1 TMS570_PIN_AND_FNC(TMS570_BALL_E18, 1) +#define TMS570_BALL_E18_MII_TXD_3 TMS570_PIN_AND_FNC(TMS570_BALL_E18, 2) + +#define TMS570_BALL_V7 TMS570_BALL_WITH_MMR(30, 1) +#define TMS570_BALL_V7_HET1_09 TMS570_PIN_AND_FNC(TMS570_BALL_V7, 0) +#define TMS570_BALL_V7_MIBSPI4NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_V7, 1) +#define TMS570_BALL_V7_HET2_16 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V7, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_16, 1)) +#define TMS570_BALL_V7_ePWM7A TMS570_PIN_AND_FNC(TMS570_BALL_V7, 5) + +#define TMS570_BALL_D19 TMS570_BALL_WITH_MMR(30, 2) +#define TMS570_BALL_D19_HET1_10 TMS570_PIN_AND_FNC(TMS570_BALL_D19, 0) +#define TMS570_BALL_D19_MIBSPI4NCS_4 TMS570_PIN_AND_FNC(TMS570_BALL_D19, 1) +#define TMS570_BALL_D19_MII_TX_CLK TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D19, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_TX_CLK, 1)) +#define TMS570_BALL_D19_nTZ1_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D19, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_nTZ1_3, 1)) + +#define TMS570_BALL_E3 TMS570_BALL_WITH_MMR(30, 3) +#define TMS570_BALL_E3_HET1_11 TMS570_PIN_AND_FNC(TMS570_BALL_E3, 0) +#define TMS570_BALL_E3_MIBSPI3NCS_4 TMS570_PIN_AND_FNC(TMS570_BALL_E3, 1) +#define TMS570_BALL_E3_HET2_18 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E3, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_18, 1)) +#define TMS570_BALL_E3_EPWM1SYNCO TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E3, 5), \ + TMS570_PIN_AND_FNC(TMS570_BALL_A4, 5) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_B4 TMS570_BALL_WITH_MMR(31, 0) +#define TMS570_BALL_B4_HET1_12 TMS570_PIN_AND_FNC(TMS570_BALL_B4, 0) +#define TMS570_BALL_B4_MIBSPI4NCS_5 TMS570_PIN_AND_FNC(TMS570_BALL_B4, 1) +#define TMS570_BALL_B4_MII_CRS TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B4, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_CRS, 1)) +#define TMS570_BALL_B4_RMII_CRS_DV TMS570_PIN_AND_FNC(TMS570_BALL_B4, 3) + +#define TMS570_BALL_N2 TMS570_BALL_WITH_MMR(31, 1) +#define TMS570_BALL_N2_HET1_13 TMS570_PIN_AND_FNC(TMS570_BALL_N2, 0) +#define TMS570_BALL_N2_SCI3TX TMS570_PIN_AND_FNC(TMS570_BALL_N2, 1) +#define TMS570_BALL_N2_HET2_20 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N2, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_20, 1)) +#define TMS570_BALL_N2_ePWM5B TMS570_PIN_AND_FNC(TMS570_BALL_N2, 5) + +#define TMS570_BALL_N1 TMS570_BALL_WITH_MMR(31, 2) +#define TMS570_BALL_N1_HET1_15 TMS570_PIN_AND_FNC(TMS570_BALL_N1, 0) +#define TMS570_BALL_N1_MIBSPI1NCS_4 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N1, 1), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MIBSPI1NCS_4, 1)) +#define TMS570_BALL_N1_HET2_22 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N1, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_22, 1)) +#define TMS570_BALL_N1_ECAP1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N1, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_ECAP1, 1)) + +#define TMS570_BALL_A4 TMS570_BALL_WITH_MMR(31, 3) +#define TMS570_BALL_A4_HET1_16 TMS570_PIN_AND_FNC(TMS570_BALL_A4, 0) +#define TMS570_BALL_A4_EPWM1SYNCI TMS570_PIN_AND_FNC(TMS570_BALL_A4, 3) +#define TMS570_BALL_A4_EPWM1SYNCO TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A4, 5), \ + TMS570_PIN_AND_FNC(TMS570_BALL_E3, 5) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_A13 TMS570_BALL_WITH_MMR(32, 0) +#define TMS570_BALL_A13_HET1_17 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A13, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_17, 0)) +#define TMS570_BALL_A13_EMIF_nOE TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A13, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_E12, 1) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_A13_SCI4RX TMS570_PIN_AND_FNC(TMS570_BALL_A13, 2) + +#define TMS570_BALL_J1 TMS570_BALL_WITH_MMR(32, 1) +#define TMS570_BALL_J1_HET1_18 TMS570_PIN_AND_FNC(TMS570_BALL_J1, 0) +#define TMS570_BALL_J1_EMIF_RNW TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J1, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_D17, 1) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_J1_ePWM6A TMS570_PIN_AND_FNC(TMS570_BALL_J1, 5) + +#define TMS570_BALL_B13 TMS570_BALL_WITH_MMR(32, 2) +#define TMS570_BALL_B13_HET1_19 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B13, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_19, 0)) +#define TMS570_BALL_B13_EMIF_nDQM_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B13, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_E10, 1) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_B13_SCI4TX TMS570_PIN_AND_FNC(TMS570_BALL_B13, 2) + +#define TMS570_BALL_P2 TMS570_BALL_WITH_MMR(32, 3) +#define TMS570_BALL_P2_HET1_20 TMS570_PIN_AND_FNC(TMS570_BALL_P2, 0) +#define TMS570_BALL_P2_EMIF_nDQM_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_P2, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_E11, 1) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_P2_ePWM6B TMS570_PIN_AND_FNC(TMS570_BALL_P2, 5) + +#define TMS570_BALL_H4 TMS570_BALL_WITH_MMR(33, 0) +#define TMS570_BALL_H4_HET1_21 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H4, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_21, 0)) +#define TMS570_BALL_H4_EMIF_nDQM_2 TMS570_PIN_AND_FNC(TMS570_BALL_H4, 1) + +#define TMS570_BALL_B3 TMS570_BALL_WITH_MMR(33, 1) +#define TMS570_BALL_B3_HET1_22 TMS570_PIN_AND_FNC(TMS570_BALL_B3, 0) +#define TMS570_BALL_B3_EMIF_nDQM_3 TMS570_PIN_AND_FNC(TMS570_BALL_B3, 1) + +#define TMS570_BALL_J4 TMS570_BALL_WITH_MMR(33, 2) +#define TMS570_BALL_J4_HET1_23 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J4, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_23, 0)) +#define TMS570_BALL_J4_EMIF_BA_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J4, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_E13, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_P1 TMS570_BALL_WITH_MMR(33, 3) +#define TMS570_BALL_P1_HET1_24 TMS570_PIN_AND_FNC(TMS570_BALL_P1, 0) +#define TMS570_BALL_P1_MIBSPI1NCS_5 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_P1, 1), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MIBSPI1NCS_5, 1)) +#define TMS570_BALL_P1_MII_RXD_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_P1, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RXD_0, 1)) +#define TMS570_BALL_P1_RMII_RXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_P1, 3) + +#define TMS570_BALL_A14 TMS570_BALL_WITH_MMR(34, 0) +#define TMS570_BALL_A14_HET1_26 TMS570_PIN_AND_FNC(TMS570_BALL_A14, 0) +#define TMS570_BALL_A14_MII_RXD_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A14, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RXD_1, 1)) +#define TMS570_BALL_A14_RMII_RXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_A14, 3) + +#define TMS570_BALL_K19 TMS570_BALL_WITH_MMR(34, 1) +#define TMS570_BALL_K19_HET1_28 TMS570_PIN_AND_FNC(TMS570_BALL_K19, 0) +#define TMS570_BALL_K19_MII_RXCLK TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_K19, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RXCLK, 1)) +#define TMS570_BALL_K19_RMII_REFCLK TMS570_PIN_AND_FNC(TMS570_BALL_K19, 3) + +#define TMS570_BALL_B11 TMS570_BALL_WITH_MMR(34, 2) +#define TMS570_BALL_B11_HET1_30 TMS570_PIN_AND_FNC(TMS570_BALL_B11, 0) +#define TMS570_BALL_B11_MII_RX_DV TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B11, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RX_DV, 1)) +#define TMS570_BALL_B11_eQEP2S TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B11, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP2S, 1)) + +#define TMS570_BALL_D8 TMS570_BALL_WITH_MMR(34, 3) +#define TMS570_BALL_D8_HET2_01 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D8, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_01, 0)) + +#define TMS570_BALL_D7 TMS570_BALL_WITH_MMR(35, 0) +#define TMS570_BALL_D7_HET2_02 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D7, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_02, 0)) + +#define TMS570_BALL_D3 TMS570_BALL_WITH_MMR(35, 1) +#define TMS570_BALL_D3_HET2_12 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D3, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_12, 0)) +#define TMS570_BALL_D3_MIBSPI2NENA TMS570_PIN_AND_FNC(TMS570_BALL_D3, 4) +#define TMS570_BALL_D3_MIBSPI2NCS_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D3, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MIBSPI2NCS_1, 1)) + +#define TMS570_BALL_D2 TMS570_BALL_WITH_MMR(35, 2) +#define TMS570_BALL_D2_HET2_13 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D2, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_13, 0)) +#define TMS570_BALL_D2_MIBSPI2SOMI TMS570_PIN_AND_FNC(TMS570_BALL_D2, 4) + +#define TMS570_BALL_D1 TMS570_BALL_WITH_MMR(35, 3) +#define TMS570_BALL_D1_HET2_14 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D1, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_14, 0)) +#define TMS570_BALL_D1_MIBSPI2SIMO TMS570_PIN_AND_FNC(TMS570_BALL_D1, 4) + +#define TMS570_BALL_P4 TMS570_BALL_WITH_MMR(36, 0) +#define TMS570_BALL_P4_HET2_19 TMS570_PIN_AND_FNC(TMS570_BALL_P4, 0) +#define TMS570_BALL_P4_LIN2RX TMS570_PIN_AND_FNC(TMS570_BALL_P4, 1) + +#define TMS570_BALL_T5 TMS570_BALL_WITH_MMR(36, 1) +#define TMS570_BALL_T5_HET2_20 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_T5, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_20, 0)) +#define TMS570_BALL_T5_LIN2TX TMS570_PIN_AND_FNC(TMS570_BALL_T5, 1) + +#define TMS570_BALL_T4 TMS570_BALL_WITH_MMR(36, 2) +#define TMS570_BALL_T4_MII_RXCLK TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_T4, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RXCLK, 0)) + +#define TMS570_BALL_U7 TMS570_BALL_WITH_MMR(36, 3) +#define TMS570_BALL_U7_MII_TX_CLK TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_U7, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_TX_CLK, 0)) + +#define TMS570_BALL_E2 TMS570_BALL_WITH_MMR(37, 0) +#define TMS570_BALL_E2_HET2_03 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E2, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_03, 0)) +#define TMS570_BALL_E2_MIBSPI2CLK TMS570_PIN_AND_FNC(TMS570_BALL_E2, 4) + +#define TMS570_BALL_N3 TMS570_BALL_WITH_MMR(37, 1) +#define TMS570_BALL_N3_HET2_07 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N3, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_07, 0)) +#define TMS570_BALL_N3_MIBSPI2NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_N3, 4) + +/* Default pinmux select */ + +#define TMS570_PINMMR_DEFAULT_INIT_LIST(per_pin_action, common_arg) \ + per_pin_action(common_arg, TMS570_BALL_N19_AD1EVT) \ + per_pin_action(common_arg, TMS570_BALL_D4_EMIF_ADDR_00) \ + per_pin_action(common_arg, TMS570_BALL_D5_EMIF_ADDR_01) \ + per_pin_action(common_arg, TMS570_BALL_C4_EMIF_ADDR_06) \ + per_pin_action(common_arg, TMS570_BALL_C5_EMIF_ADDR_07) \ + per_pin_action(common_arg, TMS570_BALL_C6_EMIF_ADDR_08) \ + per_pin_action(common_arg, TMS570_BALL_C7_EMIF_ADDR_09) \ + per_pin_action(common_arg, TMS570_BALL_C8_EMIF_ADDR_10) \ + per_pin_action(common_arg, TMS570_BALL_C9_EMIF_ADDR_11) \ + per_pin_action(common_arg, TMS570_BALL_C10_EMIF_ADDR_12) \ + per_pin_action(common_arg, TMS570_BALL_C11_EMIF_ADDR_13) \ + per_pin_action(common_arg, TMS570_BALL_C12_EMIF_ADDR_14) \ + per_pin_action(common_arg, TMS570_BALL_C13_EMIF_ADDR_15) \ + per_pin_action(common_arg, TMS570_BALL_D14_EMIF_ADDR_16) \ + per_pin_action(common_arg, TMS570_BALL_C14_EMIF_ADDR_17) \ + per_pin_action(common_arg, TMS570_BALL_D15_EMIF_ADDR_18) \ + per_pin_action(common_arg, TMS570_BALL_C15_EMIF_ADDR_19) \ + per_pin_action(common_arg, TMS570_BALL_C16_EMIF_ADDR_20) \ + per_pin_action(common_arg, TMS570_BALL_C17_EMIF_ADDR_21) \ + per_pin_action(common_arg, TMS570_BALL_D16_EMIF_BA_1) \ + per_pin_action(common_arg, TMS570_BALL_R4_EMIF_nCAS) \ + per_pin_action(common_arg, TMS570_BALL_N17_EMIF_nCS_0) \ + per_pin_action(common_arg, TMS570_BALL_L17_EMIF_nCS_2) \ + per_pin_action(common_arg, TMS570_BALL_K17_EMIF_nCS_3) \ + per_pin_action(common_arg, TMS570_BALL_M17_EMIF_nCSl_4) \ + per_pin_action(common_arg, TMS570_BALL_R3_EMIF_nRAS) \ + per_pin_action(common_arg, TMS570_BALL_P3_EMIF_nWAIT) \ + per_pin_action(common_arg, TMS570_BALL_D17_EMIF_nWE) \ + per_pin_action(common_arg, TMS570_BALL_E9_ETMDATA_08) \ + per_pin_action(common_arg, TMS570_BALL_E8_ETMDATA_09) \ + per_pin_action(common_arg, TMS570_BALL_E7_ETMDATA_10) \ + per_pin_action(common_arg, TMS570_BALL_E6_ETMDATA_11) \ + per_pin_action(common_arg, TMS570_BALL_E13_ETMDATA_12) \ + per_pin_action(common_arg, TMS570_BALL_E12_ETMDATA_13) \ + per_pin_action(common_arg, TMS570_BALL_E11_ETMDATA_14) \ + per_pin_action(common_arg, TMS570_BALL_E10_ETMDATA_15) \ + per_pin_action(common_arg, TMS570_BALL_K15_ETMDATA_16) \ + per_pin_action(common_arg, TMS570_BALL_L15_ETMDATA_17) \ + per_pin_action(common_arg, TMS570_BALL_M15_ETMDATA_18) \ + per_pin_action(common_arg, TMS570_BALL_N15_ETMDATA_19) \ + per_pin_action(common_arg, TMS570_BALL_E5_ETMDATA_20) \ + per_pin_action(common_arg, TMS570_BALL_F5_ETMDATA_21) \ + per_pin_action(common_arg, TMS570_BALL_G5_ETMDATA_22) \ + per_pin_action(common_arg, TMS570_BALL_K5_ETMDATA_23) \ + per_pin_action(common_arg, TMS570_BALL_L5_ETMDATA_24) \ + per_pin_action(common_arg, TMS570_BALL_M5_ETMDATA_25) \ + per_pin_action(common_arg, TMS570_BALL_N5_ETMDATA_26) \ + per_pin_action(common_arg, TMS570_BALL_P5_ETMDATA_27) \ + per_pin_action(common_arg, TMS570_BALL_R5_ETMDATA_28) \ + per_pin_action(common_arg, TMS570_BALL_R6_ETMDATA_29) \ + per_pin_action(common_arg, TMS570_BALL_R7_ETMDATA_30) \ + per_pin_action(common_arg, TMS570_BALL_R8_ETMDATA_31) \ + per_pin_action(common_arg, TMS570_BALL_R9_ETMTRACECLKIN) \ + per_pin_action(common_arg, TMS570_BALL_R10_ETMTRACECLKOUT) \ + per_pin_action(common_arg, TMS570_BALL_R11_ETMTRACECTL) \ + per_pin_action(common_arg, TMS570_BALL_B15_FRAYTX1) \ + per_pin_action(common_arg, TMS570_BALL_B8_FRAYTX2) \ + per_pin_action(common_arg, TMS570_BALL_B16_FRAYTXEN1) \ + per_pin_action(common_arg, TMS570_BALL_B9_FRAYTXEN2) \ + per_pin_action(common_arg, TMS570_BALL_C1_GIOA_2) \ + per_pin_action(common_arg, TMS570_BALL_E1_GIOA_3) \ + per_pin_action(common_arg, TMS570_BALL_B5_GIOA_5) \ + per_pin_action(common_arg, TMS570_BALL_H3_GIOA_6) \ + per_pin_action(common_arg, TMS570_BALL_M1_GIOA_7) \ + per_pin_action(common_arg, TMS570_BALL_F2_GIOB_2) \ + per_pin_action(common_arg, TMS570_BALL_W10_GIOB_3) \ + per_pin_action(common_arg, TMS570_BALL_J2_GIOB_6) \ + per_pin_action(common_arg, TMS570_BALL_F1_GIOB_7) \ + per_pin_action(common_arg, TMS570_BALL_R2_MIBSPI1NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_F3_MIBSPI1NCS_1) \ + per_pin_action(common_arg, TMS570_BALL_G3_MIBSPI1NCS_2) \ + per_pin_action(common_arg, TMS570_BALL_J3_MIBSPI1NCS_3) \ + per_pin_action(common_arg, TMS570_BALL_G19_MIBSPI1NENA) \ + per_pin_action(common_arg, TMS570_BALL_V9_MIBSPI3CLK) \ + per_pin_action(common_arg, TMS570_BALL_V10_MIBSPI3NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_V5_MIBSPI3NCS_1) \ + per_pin_action(common_arg, TMS570_BALL_B2_MIBSPI3NCS_2) \ + per_pin_action(common_arg, TMS570_BALL_C3_MIBSPI3NCS_3) \ + per_pin_action(common_arg, TMS570_BALL_W9_MIBSPI3NENA) \ + per_pin_action(common_arg, TMS570_BALL_W8_MIBSPI3SIMO) \ + per_pin_action(common_arg, TMS570_BALL_V8_MIBSPI3SOMI) \ + per_pin_action(common_arg, TMS570_BALL_H19_MIBSPI5CLK) \ + per_pin_action(common_arg, TMS570_BALL_E19_MIBSPI5NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_B6_MIBSPI5NCS_1) \ + per_pin_action(common_arg, TMS570_BALL_W6_MIBSPI5NCS_2) \ + per_pin_action(common_arg, TMS570_BALL_T12_MIBSPI5NCS_3) \ + per_pin_action(common_arg, TMS570_BALL_H18_MIBSPI5NENA) \ + per_pin_action(common_arg, TMS570_BALL_J19_MIBSPI5SIMO_0) \ + per_pin_action(common_arg, TMS570_BALL_E16_MIBSPI5SIMO_1) \ + per_pin_action(common_arg, TMS570_BALL_H17_MIBSPI5SIMO_2) \ + per_pin_action(common_arg, TMS570_BALL_G17_MIBSPI5SIMO_3) \ + per_pin_action(common_arg, TMS570_BALL_J18_MIBSPI5SOMI_0) \ + per_pin_action(common_arg, TMS570_BALL_E17_MIBSPI5SOMI_1) \ + per_pin_action(common_arg, TMS570_BALL_H16_MIBSPI5SOMI_2) \ + per_pin_action(common_arg, TMS570_BALL_G16_MIBSPI5SOMI_3) \ + per_pin_action(common_arg, TMS570_BALL_K18_HET1_00) \ + per_pin_action(common_arg, TMS570_BALL_V2_HET1_01) \ + per_pin_action(common_arg, TMS570_BALL_W5_HET1_02) \ + per_pin_action(common_arg, TMS570_BALL_U1_HET1_03) \ + per_pin_action(common_arg, TMS570_BALL_B12_HET1_04) \ + per_pin_action(common_arg, TMS570_BALL_V6_HET1_05) \ + per_pin_action(common_arg, TMS570_BALL_W3_HET1_06) \ + per_pin_action(common_arg, TMS570_BALL_T1_HET1_07) \ + per_pin_action(common_arg, TMS570_BALL_E18_HET1_08) \ + per_pin_action(common_arg, TMS570_BALL_V7_HET1_09) \ + per_pin_action(common_arg, TMS570_BALL_D19_HET1_10) \ + per_pin_action(common_arg, TMS570_BALL_E3_HET1_11) \ + per_pin_action(common_arg, TMS570_BALL_B4_HET1_12) \ + per_pin_action(common_arg, TMS570_BALL_N2_HET1_13) \ + per_pin_action(common_arg, TMS570_BALL_N1_HET1_15) \ + per_pin_action(common_arg, TMS570_BALL_A4_HET1_16) \ + per_pin_action(common_arg, TMS570_BALL_A13_HET1_17) \ + per_pin_action(common_arg, TMS570_BALL_J1_HET1_18) \ + per_pin_action(common_arg, TMS570_BALL_B13_HET1_19) \ + per_pin_action(common_arg, TMS570_BALL_P2_HET1_20) \ + per_pin_action(common_arg, TMS570_BALL_H4_HET1_21) \ + per_pin_action(common_arg, TMS570_BALL_B3_HET1_22) \ + per_pin_action(common_arg, TMS570_BALL_J4_HET1_23) \ + per_pin_action(common_arg, TMS570_BALL_P1_HET1_24) \ + per_pin_action(common_arg, TMS570_BALL_A14_HET1_26) \ + per_pin_action(common_arg, TMS570_BALL_K19_HET1_28) \ + per_pin_action(common_arg, TMS570_BALL_B11_HET1_30) \ + per_pin_action(common_arg, TMS570_BALL_D8_HET2_01) \ + per_pin_action(common_arg, TMS570_BALL_D7_HET2_02) \ + per_pin_action(common_arg, TMS570_BALL_D3_HET2_12) \ + per_pin_action(common_arg, TMS570_BALL_D2_HET2_13) \ + per_pin_action(common_arg, TMS570_BALL_D1_HET2_14) \ + per_pin_action(common_arg, TMS570_BALL_P4_HET2_19) \ + per_pin_action(common_arg, TMS570_BALL_T5_HET2_20) \ + per_pin_action(common_arg, TMS570_BALL_T4_MII_RXCLK) \ + per_pin_action(common_arg, TMS570_BALL_U7_MII_TX_CLK) \ + per_pin_action(common_arg, TMS570_BALL_E2_HET2_03) \ + per_pin_action(common_arg, TMS570_BALL_N3_HET2_07) \ + +/* End of default PINMMR list */ + +#endif /*LIBBSP_ARM_TMS570_TMS570LC4357_PINS_H*/ diff --git a/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h b/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h new file mode 100644 index 0000000000..63c08e8ddb --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h @@ -0,0 +1,690 @@ +/** + * @file tms570ls3137zwt-pins.h + * + * @ingroup tms570 + * + * @brief Specification of individual pins mapping to the package + */ + +/* + * Copyright (c) 2015 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_TMS570LS3137ZWT_PINS_H +#define LIBBSP_ARM_TMS570_TMS570LS3137ZWT_PINS_H + +#define TMS570_BALL_W10 TMS570_BALL_WITH_MMR(0, 0) +#define TMS570_BALL_W10_GIOB_3 TMS570_PIN_AND_FNC(TMS570_BALL_W10, 0) + +#define TMS570_BALL_A5 TMS570_BALL_WITH_MMR(0, 1) +#define TMS570_BALL_A5_GIOA_0 TMS570_PIN_AND_FNC(TMS570_BALL_A5, 0) + +#define TMS570_BALL_C3 TMS570_BALL_WITH_MMR(0, 2) +#define TMS570_BALL_C3_MIBSPI3NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_C3, 0) +#define TMS570_BALL_C3_I2C_SCL TMS570_PIN_AND_FNC(TMS570_BALL_C3, 1) +#define TMS570_BALL_C3_HET1_29 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C3, 2), \ + TMS570_PIN_AND_FNC(TMS570_BALL_A3, 0) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_B2 TMS570_BALL_WITH_MMR(0, 3) +#define TMS570_BALL_B2_MIBSPI3NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_B2, 0) +#define TMS570_BALL_B2_I2C_SDA TMS570_PIN_AND_FNC(TMS570_BALL_B2, 1) +#define TMS570_BALL_B2_HET1_27 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B2, 2), \ + TMS570_PIN_AND_FNC(TMS570_BALL_A9, 0) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_C2 TMS570_BALL_WITH_MMR(1, 0) +#define TMS570_BALL_C2_GIOA_1 TMS570_PIN_AND_FNC(TMS570_BALL_C2, 0) + +#define TMS570_BALL_E3 TMS570_BALL_WITH_MMR(1, 1) +#define TMS570_BALL_E3_HET1_11 TMS570_PIN_AND_FNC(TMS570_BALL_E3, 0) +#define TMS570_BALL_E3_MIBSPI3NCS_4 TMS570_PIN_AND_FNC(TMS570_BALL_E3, 1) +#define TMS570_BALL_E3_HET2_18 TMS570_PIN_AND_FNC(TMS570_BALL_E3, 2) + +#define TMS570_BALL_E5 TMS570_BALL_WITH_MMR(1, 2) +#define TMS570_BALL_E5_ETMDATA_20 TMS570_PIN_AND_FNC(TMS570_BALL_E5, 0) +#define TMS570_BALL_E5_EMIF_DATA_4 TMS570_PIN_AND_FNC(TMS570_BALL_E5, 1) + +#define TMS570_BALL_F5 TMS570_BALL_WITH_MMR(1, 3) +#define TMS570_BALL_F5_ETMDATA_21 TMS570_PIN_AND_FNC(TMS570_BALL_F5, 0) +#define TMS570_BALL_F5_EMIF_DATA_5 TMS570_PIN_AND_FNC(TMS570_BALL_F5, 1) + +#define TMS570_BALL_C1 TMS570_BALL_WITH_MMR(2, 0) +#define TMS570_BALL_C1_GIOA_2 TMS570_PIN_AND_FNC(TMS570_BALL_C1, 0) +#define TMS570_BALL_C1_HET2_00 TMS570_PIN_AND_FNC(TMS570_BALL_C1, 3) + +#define TMS570_BALL_G5 TMS570_BALL_WITH_MMR(2, 1) +#define TMS570_BALL_G5_ETMDATA_22 TMS570_PIN_AND_FNC(TMS570_BALL_G5, 0) +#define TMS570_BALL_G5_EMIF_DATA_6 TMS570_PIN_AND_FNC(TMS570_BALL_G5, 1) + +#define TMS570_BALL_E1 TMS570_BALL_WITH_MMR(2, 2) +#define TMS570_BALL_E1_GIOA_3 TMS570_PIN_AND_FNC(TMS570_BALL_E1, 0) +#define TMS570_BALL_E1_HET2_02 TMS570_PIN_AND_FNC(TMS570_BALL_E1, 1) + +#define TMS570_BALL_B5 TMS570_BALL_WITH_MMR(2, 3) +#define TMS570_BALL_B5_GIOA_5 TMS570_PIN_AND_FNC(TMS570_BALL_B5, 0) +#define TMS570_BALL_B5_EXTCLKIN TMS570_PIN_AND_FNC(TMS570_BALL_B5, 1) + +#define TMS570_BALL_K5 TMS570_BALL_WITH_MMR(3, 0) +#define TMS570_BALL_K5_ETMDATA_23 TMS570_PIN_AND_FNC(TMS570_BALL_K5, 0) +#define TMS570_BALL_K5_EMIF_DATA_7 TMS570_PIN_AND_FNC(TMS570_BALL_K5, 1) + +#define TMS570_BALL_B3 TMS570_BALL_WITH_MMR(3, 1) +#define TMS570_BALL_B3_HET1_22 TMS570_PIN_AND_FNC(TMS570_BALL_B3, 0) + +#define TMS570_BALL_H3 TMS570_BALL_WITH_MMR(3, 2) +#define TMS570_BALL_H3_GIOA_6 TMS570_PIN_AND_FNC(TMS570_BALL_H3, 0) +#define TMS570_BALL_H3_HET2_04 TMS570_PIN_AND_FNC(TMS570_BALL_H3, 1) + +#define TMS570_BALL_L5 TMS570_BALL_WITH_MMR(3, 3) +#define TMS570_BALL_L5_ETMDATA_24 TMS570_PIN_AND_FNC(TMS570_BALL_L5, 0) +#define TMS570_BALL_L5_EMIF_DATA_8 TMS570_PIN_AND_FNC(TMS570_BALL_L5, 1) + +#define TMS570_BALL_M1 TMS570_BALL_WITH_MMR(4, 0) +#define TMS570_BALL_M1_GIOA_7 TMS570_PIN_AND_FNC(TMS570_BALL_M1, 0) +#define TMS570_BALL_M1_HET2_06 TMS570_PIN_AND_FNC(TMS570_BALL_M1, 1) + +#define TMS570_BALL_M5 TMS570_BALL_WITH_MMR(4, 1) +#define TMS570_BALL_M5_ETMDATA_25 TMS570_PIN_AND_FNC(TMS570_BALL_M5, 0) +#define TMS570_BALL_M5_EMIF_DATA_9 TMS570_PIN_AND_FNC(TMS570_BALL_M5, 1) + +#define TMS570_BALL_V2 TMS570_BALL_WITH_MMR(4, 2) +#define TMS570_BALL_V2_HET1_01 TMS570_PIN_AND_FNC(TMS570_BALL_V2, 0) +#define TMS570_BALL_V2_SPI4NENA TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V2, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(24, 0), 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_V2_HET2_08 TMS570_PIN_AND_FNC(TMS570_BALL_V2, 4) + +#define TMS570_BALL_U1 TMS570_BALL_WITH_MMR(4, 3) +#define TMS570_BALL_U1_HET1_03 TMS570_PIN_AND_FNC(TMS570_BALL_U1, 0) +#define TMS570_BALL_U1_SPI4NCS_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_U1, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(24, 1), 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_U1_HET2_10 TMS570_PIN_AND_FNC(TMS570_BALL_U1, 4) + +#define TMS570_BALL_K18 TMS570_BALL_WITH_MMR(5, 0) +#define TMS570_BALL_K18_HET1_00 TMS570_PIN_AND_FNC(TMS570_BALL_K18, 0) +#define TMS570_BALL_K18_SPI4CLK TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_K18, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(23, 1), 0) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_W5 TMS570_BALL_WITH_MMR(5, 1) +#define TMS570_BALL_W5_HET1_02 TMS570_PIN_AND_FNC(TMS570_BALL_W5, 0) +#define TMS570_BALL_W5_SPI4SIMO TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W5, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(23, 2), 0) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_V6 TMS570_BALL_WITH_MMR(5, 2) +#define TMS570_BALL_V6_HET1_05 TMS570_PIN_AND_FNC(TMS570_BALL_V6, 0) +#define TMS570_BALL_V6_SPI4SOMI TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V6, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(23, 3), 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_V6_HET2_12 TMS570_PIN_AND_FNC(TMS570_BALL_V6, 2) + +#define TMS570_BALL_N5 TMS570_BALL_WITH_MMR(5, 3) +#define TMS570_BALL_N5_ETMDATA_26 TMS570_PIN_AND_FNC(TMS570_BALL_N5, 0) +#define TMS570_BALL_N5_EMIF_DATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_N5, 1) + +#define TMS570_BALL_T1 TMS570_BALL_WITH_MMR(6, 0) +#define TMS570_BALL_T1_HET1_07 TMS570_PIN_AND_FNC(TMS570_BALL_T1, 0) +#define TMS570_BALL_T1_HET2_14 TMS570_PIN_AND_FNC(TMS570_BALL_T1, 3) + +#define TMS570_BALL_P5 TMS570_BALL_WITH_MMR(6, 1) +#define TMS570_BALL_P5_ETMDATA_27 TMS570_PIN_AND_FNC(TMS570_BALL_P5, 0) +#define TMS570_BALL_P5_EMIF_DATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_P5, 1) + +#define TMS570_BALL_V7 TMS570_BALL_WITH_MMR(6, 2) +#define TMS570_BALL_V7_HET1_09 TMS570_PIN_AND_FNC(TMS570_BALL_V7, 0) +#define TMS570_BALL_V7_HET2_16 TMS570_PIN_AND_FNC(TMS570_BALL_V7, 1) + +#define TMS570_BALL_R5 TMS570_BALL_WITH_MMR(6, 3) +#define TMS570_BALL_R5_ETMDATA_28 TMS570_PIN_AND_FNC(TMS570_BALL_R5, 0) +#define TMS570_BALL_R5_EMIF_DATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_R5, 1) + +#define TMS570_BALL_R6 TMS570_BALL_WITH_MMR(7, 0) +#define TMS570_BALL_R6_ETMDATA_29 TMS570_PIN_AND_FNC(TMS570_BALL_R6, 0) +#define TMS570_BALL_R6_EMIF_DATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_R6, 1) + +#define TMS570_BALL_V5 TMS570_BALL_WITH_MMR(7, 1) +#define TMS570_BALL_V5_MIBSPI3NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_V5, 0) +#define TMS570_BALL_V5_HET1_25 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V5, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_M3, 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_V5_MDCLK TMS570_PIN_AND_FNC(TMS570_BALL_V5, 2) + +#define TMS570_BALL_W3 TMS570_BALL_WITH_MMR(7, 2) +#define TMS570_BALL_W3_HET1_06 TMS570_PIN_AND_FNC(TMS570_BALL_W3, 0) +#define TMS570_BALL_W3_SCIRX TMS570_PIN_AND_FNC(TMS570_BALL_W3, 1) + +#define TMS570_BALL_R7 TMS570_BALL_WITH_MMR(7, 3) +#define TMS570_BALL_R7_ETMDATA_30 TMS570_PIN_AND_FNC(TMS570_BALL_R7, 0) +#define TMS570_BALL_R7_EMIF_DATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_R7, 1) + +#define TMS570_BALL_N2 TMS570_BALL_WITH_MMR(8, 0) +#define TMS570_BALL_N2_HET1_13 TMS570_PIN_AND_FNC(TMS570_BALL_N2, 0) +#define TMS570_BALL_N2_SCITX TMS570_PIN_AND_FNC(TMS570_BALL_N2, 1) + +#define TMS570_BALL_G3 TMS570_BALL_WITH_MMR(8, 1) +#define TMS570_BALL_G3_MIBSPI1NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_G3, 0) +#define TMS570_BALL_G3_HET1_19 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G3, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_B13, 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_G3_MDIO TMS570_PIN_AND_FNC(TMS570_BALL_G3, 2) + +#define TMS570_BALL_N1 TMS570_BALL_WITH_MMR(8, 2) +#define TMS570_BALL_N1_HET1_15 TMS570_PIN_AND_FNC(TMS570_BALL_N1, 0) +#define TMS570_BALL_N1_MIBSPI1NCS_4 TMS570_PIN_AND_FNC(TMS570_BALL_N1, 1) + +#define TMS570_BALL_R8 TMS570_BALL_WITH_MMR(8, 3) +#define TMS570_BALL_R8_ETMDATA_31 TMS570_PIN_AND_FNC(TMS570_BALL_R8, 0) +#define TMS570_BALL_R8_EMIF_DATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_R8, 1) + +#define TMS570_BALL_R9 TMS570_BALL_WITH_MMR(9, 0) +#define TMS570_BALL_R9_ETMTRACECLKIN TMS570_PIN_AND_FNC(TMS570_BALL_R9, 0) +#define TMS570_BALL_R9_EXTCLKIN2 TMS570_PIN_AND_FNC(TMS570_BALL_R9, 1) + +#define TMS570_BALL_W9 TMS570_BALL_WITH_MMR(9, 1) +#define TMS570_BALL_W9_MIBSPI3NENA TMS570_PIN_AND_FNC(TMS570_BALL_W9, 0) +#define TMS570_BALL_W9_MIBSPI3NCS_5 TMS570_PIN_AND_FNC(TMS570_BALL_W9, 1) +#define TMS570_BALL_W9_HET1_31 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W9, 2), \ + TMS570_PIN_AND_FNC(TMS570_BALL_J17, 0) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_V10 TMS570_BALL_WITH_MMR(9, 2) +#define TMS570_BALL_V10_MIBSPI3NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_V10, 0) +#define TMS570_BALL_V10_AD2EVT TMS570_PIN_AND_FNC(TMS570_BALL_V10, 1) + +#define TMS570_BALL_J3 TMS570_BALL_WITH_MMR(9, 3) +#define TMS570_BALL_J3_MIBSPI1NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_J3, 0) +#define TMS570_BALL_J3_HET1_21 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J3, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_H4, 0) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_N19 TMS570_BALL_WITH_MMR(10, 0) +#define TMS570_BALL_N19_AD1EVT TMS570_PIN_AND_FNC(TMS570_BALL_N19, 0) +#define TMS570_BALL_N19_MII_RX_ER TMS570_PIN_AND_FNC(TMS570_BALL_N19, 1) +#define TMS570_BALL_N19_RMII_RX_ER TMS570_PIN_AND_FNC(TMS570_BALL_N19, 2) + +#define TMS570_BALL_N15 TMS570_BALL_WITH_MMR(10, 1) +#define TMS570_BALL_N15_ETMDATA_19 TMS570_PIN_AND_FNC(TMS570_BALL_N15, 0) +#define TMS570_BALL_N15_EMIF_DATA_3 TMS570_PIN_AND_FNC(TMS570_BALL_N15, 1) + +#define TMS570_BALL_N17 TMS570_BALL_WITH_MMR(10, 2) +#define TMS570_BALL_N17_EMIF_nCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_N17, 0) +#define TMS570_BALL_N17_RTP_DATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_N17, 1) +#define TMS570_BALL_N17_HET2_07 TMS570_PIN_AND_FNC(TMS570_BALL_N17, 2) + +#define TMS570_BALL_M15 TMS570_BALL_WITH_MMR(10, 3) +#define TMS570_BALL_M15_ETMDATA_18 TMS570_PIN_AND_FNC(TMS570_BALL_M15, 0) +#define TMS570_BALL_M15_EMIF_DATA_2 TMS570_PIN_AND_FNC(TMS570_BALL_M15, 1) + +#define TMS570_BALL_K17 TMS570_BALL_WITH_MMR(11, 0) +#define TMS570_BALL_K17_EMIF_nCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_K17, 0) +#define TMS570_BALL_K17_RTP_DATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_K17, 1) +#define TMS570_BALL_K17_HET2_09 TMS570_PIN_AND_FNC(TMS570_BALL_K17, 2) + +#define TMS570_BALL_M17 TMS570_BALL_WITH_MMR(11, 1) +#define TMS570_BALL_M17_EMIF_nCS_4 TMS570_PIN_AND_FNC(TMS570_BALL_M17, 0) +#define TMS570_BALL_M17_RTP_DATA_07 TMS570_PIN_AND_FNC(TMS570_BALL_M17, 1) + +#define TMS570_BALL_L15 TMS570_BALL_WITH_MMR(11, 2) +#define TMS570_BALL_L15_ETMDATA_17 TMS570_PIN_AND_FNC(TMS570_BALL_L15, 0) +#define TMS570_BALL_L15_EMIF_DATA_1 TMS570_PIN_AND_FNC(TMS570_BALL_L15, 1) + +#define TMS570_BALL_P1 TMS570_BALL_WITH_MMR(11, 3) +#define TMS570_BALL_P1_HET1_24 TMS570_PIN_AND_FNC(TMS570_BALL_P1, 0) +#define TMS570_BALL_P1_MIBSPI1NCS_5 TMS570_PIN_AND_FNC(TMS570_BALL_P1, 1) +#define TMS570_BALL_P1_MII_RXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_P1, 2) +#define TMS570_BALL_P1_RMII_RXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_P1, 3) + +#define TMS570_BALL_A14 TMS570_BALL_WITH_MMR(12, 0) +#define TMS570_BALL_A14_HET1_26 TMS570_PIN_AND_FNC(TMS570_BALL_A14, 0) +#define TMS570_BALL_A14_MII_RXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_A14, 1) +#define TMS570_BALL_A14_RMII_RXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_A14, 2) + +#define TMS570_BALL_K15 TMS570_BALL_WITH_MMR(12, 1) +#define TMS570_BALL_K15_ETMDATA_16 TMS570_PIN_AND_FNC(TMS570_BALL_K15, 0) +#define TMS570_BALL_K15_EMIF_DATA_0 TMS570_PIN_AND_FNC(TMS570_BALL_K15, 1) + +#define TMS570_BALL_G19 TMS570_BALL_WITH_MMR(12, 2) +#define TMS570_BALL_G19_MIBSPI1NENA TMS570_PIN_AND_FNC(TMS570_BALL_G19, 0) +#define TMS570_BALL_G19_HET1_23 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G19, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_J4, 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_G19_MII_RXD_2 TMS570_PIN_AND_FNC(TMS570_BALL_G19, 2) + +#define TMS570_BALL_H18 TMS570_BALL_WITH_MMR(12, 3) +#define TMS570_BALL_H18_MIBSPI5NENA TMS570_PIN_AND_FNC(TMS570_BALL_H18, 0) +#define TMS570_BALL_H18_DMM_DATA_7 TMS570_PIN_AND_FNC(TMS570_BALL_H18, 1) +#define TMS570_BALL_H18_MII_RXD_3 TMS570_PIN_AND_FNC(TMS570_BALL_H18, 2) + +#define TMS570_BALL_J18 TMS570_BALL_WITH_MMR(13, 0) +#define TMS570_BALL_J18_MIBSPI5SOMI_0 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 0) +#define TMS570_BALL_J18_DMM_DATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 1) +#define TMS570_BALL_J18_MII_TXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 2) +#define TMS570_BALL_J18_RMII_TXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 3) + +#define TMS570_BALL_J19 TMS570_BALL_WITH_MMR(13, 1) +#define TMS570_BALL_J19_MIBSPI5SIMO_0 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 0) +#define TMS570_BALL_J19_DMM_DATA_8 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 1) +#define TMS570_BALL_J19_MII_TXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 2) +#define TMS570_BALL_J19_RMII_TXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 3) + +#define TMS570_BALL_H19 TMS570_BALL_WITH_MMR(13, 2) +#define TMS570_BALL_H19_MIBSPI5CLK TMS570_PIN_AND_FNC(TMS570_BALL_H19, 0) +#define TMS570_BALL_H19_DMM_DATA_4 TMS570_PIN_AND_FNC(TMS570_BALL_H19, 1) +#define TMS570_BALL_H19_MII_TXEN TMS570_PIN_AND_FNC(TMS570_BALL_H19, 2) +#define TMS570_BALL_H19_RMII_TXEN TMS570_PIN_AND_FNC(TMS570_BALL_H19, 3) + +#define TMS570_BALL_R2 TMS570_BALL_WITH_MMR(13, 3) +#define TMS570_BALL_R2_MIBSPI1NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_R2, 0) +#define TMS570_BALL_R2_MIBSPI1SOMI_1 TMS570_PIN_AND_FNC(TMS570_BALL_R2, 1) +#define TMS570_BALL_R2_MII_TXD_2 TMS570_PIN_AND_FNC(TMS570_BALL_R2, 2) + +#define TMS570_BALL_E18 TMS570_BALL_WITH_MMR(14, 0) +#define TMS570_BALL_E18_HET1_08 TMS570_PIN_AND_FNC(TMS570_BALL_E18, 0) +#define TMS570_BALL_E18_MIBSPI1SIMO_1 TMS570_PIN_AND_FNC(TMS570_BALL_E18, 1) +#define TMS570_BALL_E18_MII_TXD_3 TMS570_PIN_AND_FNC(TMS570_BALL_E18, 2) + +#define TMS570_BALL_K19 TMS570_BALL_WITH_MMR(14, 1) +#define TMS570_BALL_K19_HET1_28 TMS570_PIN_AND_FNC(TMS570_BALL_K19, 0) +#define TMS570_BALL_K19_MII_RXCLK TMS570_PIN_AND_FNC(TMS570_BALL_K19, 1) +#define TMS570_BALL_K19_RMII_REFCLK TMS570_PIN_AND_FNC(TMS570_BALL_K19, 2) +#define TMS570_BALL_K19_MII_RX_AVCLK4 TMS570_PIN_AND_FNC(TMS570_BALL_K19, 3) + +#define TMS570_BALL_D17 TMS570_BALL_WITH_MMR(14, 2) +#define TMS570_BALL_D17_EMIF_nWE TMS570_PIN_AND_FNC(TMS570_BALL_D17, 0) +#define TMS570_BALL_D17_EMIF_RNW TMS570_PIN_AND_FNC(TMS570_BALL_D17, 1) + +#define TMS570_BALL_D16 TMS570_BALL_WITH_MMR(14, 3) +#define TMS570_BALL_D16_EMIF_BA_1 TMS570_PIN_AND_FNC(TMS570_BALL_D16, 0) +#define TMS570_BALL_D16_HET2_05 TMS570_PIN_AND_FNC(TMS570_BALL_D16, 1) + +#define TMS570_BALL_C17 TMS570_BALL_WITH_MMR(15, 0) +#define TMS570_BALL_C17_EMIF_ADDR_21 TMS570_PIN_AND_FNC(TMS570_BALL_C17, 0) +#define TMS570_BALL_C17_RTP_CLK TMS570_PIN_AND_FNC(TMS570_BALL_C17, 1) + +#define TMS570_BALL_C16 TMS570_BALL_WITH_MMR(15, 1) +#define TMS570_BALL_C16_EMIF_ADDR_20 TMS570_PIN_AND_FNC(TMS570_BALL_C16, 0) +#define TMS570_BALL_C16_RTP_nSYNC TMS570_PIN_AND_FNC(TMS570_BALL_C16, 1) + +#define TMS570_BALL_C15 TMS570_BALL_WITH_MMR(15, 2) +#define TMS570_BALL_C15_EMIF_ADDR_19 TMS570_PIN_AND_FNC(TMS570_BALL_C15, 0) +#define TMS570_BALL_C15_RTP_nENA TMS570_PIN_AND_FNC(TMS570_BALL_C15, 1) + +#define TMS570_BALL_D15 TMS570_BALL_WITH_MMR(15, 3) +#define TMS570_BALL_D15_EMIF_ADDR_18 TMS570_PIN_AND_FNC(TMS570_BALL_D15, 0) +#define TMS570_BALL_D15_RTP_DATA_0 TMS570_PIN_AND_FNC(TMS570_BALL_D15, 1) + +#define TMS570_BALL_E13 TMS570_BALL_WITH_MMR(16, 0) +#define TMS570_BALL_E13_ETMDATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_E13, 0) +#define TMS570_BALL_E13_EMIF_BA_0 TMS570_PIN_AND_FNC(TMS570_BALL_E13, 1) + +#define TMS570_BALL_C14 TMS570_BALL_WITH_MMR(16, 1) +#define TMS570_BALL_C14_EMIF_ADDR_17 TMS570_PIN_AND_FNC(TMS570_BALL_C14, 0) +#define TMS570_BALL_C14_RTP_DATA_01 TMS570_PIN_AND_FNC(TMS570_BALL_C14, 1) + +#define TMS570_BALL_D14 TMS570_BALL_WITH_MMR(16, 2) +#define TMS570_BALL_D14_EMIF_ADDR_16 TMS570_PIN_AND_FNC(TMS570_BALL_D14, 0) +#define TMS570_BALL_D14_RTP_DATA_02 TMS570_PIN_AND_FNC(TMS570_BALL_D14, 1) + +#define TMS570_BALL_E12 TMS570_BALL_WITH_MMR(16, 3) +#define TMS570_BALL_E12_ETMDATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_E12, 0) +#define TMS570_BALL_E12_EMIF_nOE TMS570_PIN_AND_FNC(TMS570_BALL_E12, 1) + +#define TMS570_BALL_D19 TMS570_BALL_WITH_MMR(17, 0) +#define TMS570_BALL_D19_HET1_10 TMS570_PIN_AND_FNC(TMS570_BALL_D19, 0) +#define TMS570_BALL_D19_MII_TX_CLK TMS570_PIN_AND_FNC(TMS570_BALL_D19, 1) +#define TMS570_BALL_D19_MII_TX_AVCLK4 TMS570_PIN_AND_FNC(TMS570_BALL_D19, 3) + +#define TMS570_BALL_E11 TMS570_BALL_WITH_MMR(17, 1) +#define TMS570_BALL_E11_ETMDATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_E11, 0) +#define TMS570_BALL_E11_EMIF_nDQM_1 TMS570_PIN_AND_FNC(TMS570_BALL_E11, 1) + +#define TMS570_BALL_B4 TMS570_BALL_WITH_MMR(17, 2) +#define TMS570_BALL_B4_HET1_12 TMS570_PIN_AND_FNC(TMS570_BALL_B4, 0) +#define TMS570_BALL_B4_MII_CRS TMS570_PIN_AND_FNC(TMS570_BALL_B4, 1) +#define TMS570_BALL_B4_RMII_CRS_DV TMS570_PIN_AND_FNC(TMS570_BALL_B4, 2) + +#define TMS570_BALL_E9 TMS570_BALL_WITH_MMR(17, 3) +#define TMS570_BALL_E9_ETMDATA_8 TMS570_PIN_AND_FNC(TMS570_BALL_E9, 0) +#define TMS570_BALL_E9_EMIF_ADDR_5 TMS570_PIN_AND_FNC(TMS570_BALL_E9, 1) + +#define TMS570_BALL_C13 TMS570_BALL_WITH_MMR(18, 0) +#define TMS570_BALL_C13_EMIF_ADDR_15 TMS570_PIN_AND_FNC(TMS570_BALL_C13, 0) +#define TMS570_BALL_C13_RTP_DATA_03 TMS570_PIN_AND_FNC(TMS570_BALL_C13, 1) + +#define TMS570_BALL_A11 TMS570_BALL_WITH_MMR(18, 1) +#define TMS570_BALL_A11_HET1_14 TMS570_PIN_AND_FNC(TMS570_BALL_A11, 0) + +#define TMS570_BALL_C12 TMS570_BALL_WITH_MMR(18, 2) +#define TMS570_BALL_C12_EMIF_ADDR_14 TMS570_PIN_AND_FNC(TMS570_BALL_C12, 0) +#define TMS570_BALL_C12_RTP_DATA_04 TMS570_PIN_AND_FNC(TMS570_BALL_C12, 1) + +#define TMS570_BALL_M2 TMS570_BALL_WITH_MMR(18, 3) +#define TMS570_BALL_M2_GIOB_0 TMS570_PIN_AND_FNC(TMS570_BALL_M2, 0) + +#define TMS570_BALL_E8 TMS570_BALL_WITH_MMR(19, 0) +#define TMS570_BALL_E8_ETMDATA_09 TMS570_PIN_AND_FNC(TMS570_BALL_E8, 0) +#define TMS570_BALL_E8_EMIF_ADDR_4 TMS570_PIN_AND_FNC(TMS570_BALL_E8, 1) + +#define TMS570_BALL_B11 TMS570_BALL_WITH_MMR(19, 1) +#define TMS570_BALL_B11_HET1_30 TMS570_PIN_AND_FNC(TMS570_BALL_B11, 0) +#define TMS570_BALL_B11_MII_RX_DV TMS570_PIN_AND_FNC(TMS570_BALL_B11, 1) + +#define TMS570_BALL_E10 TMS570_BALL_WITH_MMR(19, 2) +#define TMS570_BALL_E10_ETMDATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_E10, 0) +#define TMS570_BALL_E10_EMIF_nDQM_0 TMS570_PIN_AND_FNC(TMS570_BALL_E10, 1) + +#define TMS570_BALL_E7 TMS570_BALL_WITH_MMR(19, 3) +#define TMS570_BALL_E7_ETMDATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_E7, 0) +#define TMS570_BALL_E7_EMIF_ADDR_3 TMS570_PIN_AND_FNC(TMS570_BALL_E7, 1) + +#define TMS570_BALL_C11 TMS570_BALL_WITH_MMR(20, 0) +#define TMS570_BALL_C11_EMIF_ADDR_13 TMS570_PIN_AND_FNC(TMS570_BALL_C11, 0) +#define TMS570_BALL_C11_RTP_DATA_05 TMS570_PIN_AND_FNC(TMS570_BALL_C11, 1) + +#define TMS570_BALL_C10 TMS570_BALL_WITH_MMR(20, 1) +#define TMS570_BALL_C10_EMIF_ADDR_12 TMS570_PIN_AND_FNC(TMS570_BALL_C10, 0) +#define TMS570_BALL_C10_RTP_DATA_06 TMS570_PIN_AND_FNC(TMS570_BALL_C10, 1) + +#define TMS570_BALL_F3 TMS570_BALL_WITH_MMR(20, 2) +#define TMS570_BALL_F3_MIBSPI1NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_F3, 0) +#define TMS570_BALL_F3_HET1_17 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F3, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_A13, 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_F3_MII_COL TMS570_PIN_AND_FNC(TMS570_BALL_F3, 2) + +#define TMS570_BALL_C9 TMS570_BALL_WITH_MMR(20, 3) +#define TMS570_BALL_C9_EMIF_ADDR_11 TMS570_PIN_AND_FNC(TMS570_BALL_C9, 0) +#define TMS570_BALL_C9_RTP_DATA_08 TMS570_PIN_AND_FNC(TMS570_BALL_C9, 1) + +#define TMS570_BALL_D5 TMS570_BALL_WITH_MMR(21, 0) +#define TMS570_BALL_D5_EMIF_ADDR_1 TMS570_PIN_AND_FNC(TMS570_BALL_D5, 0) +#define TMS570_BALL_D5_HET2_03 TMS570_PIN_AND_FNC(TMS570_BALL_D5, 1) + +#define TMS570_BALL_K2 TMS570_BALL_WITH_MMR(21, 1) +#define TMS570_BALL_K2_GIOB_1 TMS570_PIN_AND_FNC(TMS570_BALL_K2, 0) + +#define TMS570_BALL_C8 TMS570_BALL_WITH_MMR(21, 2) +#define TMS570_BALL_C8_EMIF_ADDR_10 TMS570_PIN_AND_FNC(TMS570_BALL_C8, 0) +#define TMS570_BALL_C8_RTP_DATA_09 TMS570_PIN_AND_FNC(TMS570_BALL_C8, 1) + +#define TMS570_BALL_C7 TMS570_BALL_WITH_MMR(21, 3) +#define TMS570_BALL_C7_EMIF_ADDR_9 TMS570_PIN_AND_FNC(TMS570_BALL_C7, 0) +#define TMS570_BALL_C7_RTP_DATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_C7, 1) + +#define TMS570_BALL_D4 TMS570_BALL_WITH_MMR(22, 0) +#define TMS570_BALL_D4_EMIF_ADDR_0 TMS570_PIN_AND_FNC(TMS570_BALL_D4, 0) +#define TMS570_BALL_D4_HET2_01 TMS570_PIN_AND_FNC(TMS570_BALL_D4, 1) + +#define TMS570_BALL_C5 TMS570_BALL_WITH_MMR(22, 1) +#define TMS570_BALL_C5_EMIF_ADDR_7 TMS570_PIN_AND_FNC(TMS570_BALL_C5, 0) +#define TMS570_BALL_C5_RTP_DATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_C5, 1) +#define TMS570_BALL_C5_HET2_13 TMS570_PIN_AND_FNC(TMS570_BALL_C5, 2) + +#define TMS570_BALL_C4 TMS570_BALL_WITH_MMR(22, 2) +#define TMS570_BALL_C4_EMIF_ADDR_6 TMS570_PIN_AND_FNC(TMS570_BALL_C4, 0) +#define TMS570_BALL_C4_RTP_DATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_C4, 1) +#define TMS570_BALL_C4_HET2_11 TMS570_PIN_AND_FNC(TMS570_BALL_C4, 2) + +#define TMS570_BALL_E6 TMS570_BALL_WITH_MMR(22, 3) +#define TMS570_BALL_E6_ETMDATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_E6, 0) +#define TMS570_BALL_E6_EMIF_ADDR_2 TMS570_PIN_AND_FNC(TMS570_BALL_E6, 1) + +#define TMS570_BALL_C6 TMS570_BALL_WITH_MMR(23, 0) +#define TMS570_BALL_C6_EMIF_ADDR_8 TMS570_PIN_AND_FNC(TMS570_BALL_C6, 0) +#define TMS570_BALL_C6_RTP_DATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_C6, 1) +#define TMS570_BALL_C6_HET2_15 TMS570_PIN_AND_FNC(TMS570_BALL_C6, 2) + +#define TMS570_MMR_SELECT_SPI4CLK TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(23, 1), 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_K18, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_MMR_SELECT_SPI4SIMO TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(23, 2), 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_W5, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_MMR_SELECT_SPI4SOMI TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(23, 3), 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_V6, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_MMR_SELECT_SPI4NENA TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(24, 0), 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_V2, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_MMR_SELECT_SPI4NCS_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(24, 1), 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_U1, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_A13 TMS570_BALL_WITH_MMR(24, 2) +#define TMS570_BALL_A13_HET1_17 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A13, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_F3, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_B13 TMS570_BALL_WITH_MMR(24, 3) +#define TMS570_BALL_B13_HET1_19 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B13, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_G3, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_H4 TMS570_BALL_WITH_MMR(25, 0) +#define TMS570_BALL_H4_HET1_21 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H4, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_J3, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_J4 TMS570_BALL_WITH_MMR(25, 1) +#define TMS570_BALL_J4_HET1_23 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J4, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_G19, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_M3 TMS570_BALL_WITH_MMR(25, 2) +#define TMS570_BALL_M3_HET1_25 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_M3, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_V5, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_A9 TMS570_BALL_WITH_MMR(25, 3) +#define TMS570_BALL_A9_HET1_27 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A9, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_B2, 2) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_A3 TMS570_BALL_WITH_MMR(26, 0) +#define TMS570_BALL_A3_HET1_29 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A3, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_C3, 2) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_J17 TMS570_BALL_WITH_MMR(26, 1) +#define TMS570_BALL_J17_HET1_31 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J17, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_W9, 2) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_W6 TMS570_BALL_WITH_MMR(26, 2) +#define TMS570_BALL_W6_MIBSPI5NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_W6, 0) +#define TMS570_BALL_W6_DMM_DATA_2 TMS570_PIN_AND_FNC(TMS570_BALL_W6, 1) + +#define TMS570_BALL_T12 TMS570_BALL_WITH_MMR(26, 3) +#define TMS570_BALL_T12_MIBSPI5NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_T12, 0) +#define TMS570_BALL_T12_DMM_DATA_3 TMS570_PIN_AND_FNC(TMS570_BALL_T12, 1) + +#define TMS570_BALL_E19 TMS570_BALL_WITH_MMR(27, 0) +#define TMS570_BALL_E19_MIBSPI5NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_E19, 0) +#define TMS570_BALL_E19_DMM_DATA_5 TMS570_PIN_AND_FNC(TMS570_BALL_E19, 1) + +#define TMS570_BALL_B6 TMS570_BALL_WITH_MMR(27, 1) +#define TMS570_BALL_B6_MIBSPI5NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_B6, 0) +#define TMS570_BALL_B6_DMM_DATA_6 TMS570_PIN_AND_FNC(TMS570_BALL_B6, 1) + +#define TMS570_BALL_E16 TMS570_BALL_WITH_MMR(27, 2) +#define TMS570_BALL_E16_MIBSPI5SIMO_1 TMS570_PIN_AND_FNC(TMS570_BALL_E16, 0) +#define TMS570_BALL_E16_DMM_DATA_9 TMS570_PIN_AND_FNC(TMS570_BALL_E16, 1) + +#define TMS570_BALL_H17 TMS570_BALL_WITH_MMR(27, 3) +#define TMS570_BALL_H17_MIBSPI5SIMO_2 TMS570_PIN_AND_FNC(TMS570_BALL_H17, 0) +#define TMS570_BALL_H17_DMM_DATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_H17, 1) + +#define TMS570_BALL_G17 TMS570_BALL_WITH_MMR(28, 0) +#define TMS570_BALL_G17_MIBSPI5SIMO_3 TMS570_PIN_AND_FNC(TMS570_BALL_G17, 0) +#define TMS570_BALL_G17_DMM_DATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_G17, 1) + +#define TMS570_BALL_E17 TMS570_BALL_WITH_MMR(28, 1) +#define TMS570_BALL_E17_MIBSPI5SOMI_1 TMS570_PIN_AND_FNC(TMS570_BALL_E17, 0) +#define TMS570_BALL_E17_DMM_DATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_E17, 1) + +#define TMS570_BALL_H16 TMS570_BALL_WITH_MMR(28, 2) +#define TMS570_BALL_H16_MIBSPI5SOMI_2 TMS570_PIN_AND_FNC(TMS570_BALL_H16, 0) +#define TMS570_BALL_H16_DMM_DATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_H16, 1) + +#define TMS570_BALL_G16 TMS570_BALL_WITH_MMR(28, 3) +#define TMS570_BALL_G16_MIBSPI5SOMI_3 TMS570_PIN_AND_FNC(TMS570_BALL_G16, 0) +#define TMS570_BALL_G16_DMM_DATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_G16, 1) + +#define TMS570_BALL_D3 TMS570_BALL_WITH_MMR(29, 0) +#define TMS570_BALL_D3_SPI2NENA TMS570_PIN_AND_FNC(TMS570_BALL_D3, 0) +#define TMS570_BALL_D3_SPI2NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_D3, 1) + +#define TMS570_MMR_SELECT_EMIF_CLK_SEL TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(29, 1), 0) + +#define TMS570_BALL_F2 TMS570_BALL_WITH_MMR(29, 2) +#define TMS570_BALL_F2_GIOB_2 TMS570_PIN_AND_FNC(TMS570_BALL_F2, 0) + +#define TMS570_MMR_SELECT_GMII_SEL TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(29, 3), 0) + +#define TMS570_MMR_SELECT_ADC_TRG1 TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(30, 0), 0) +#define TMS570_MMR_SELECT_ADC_TRG2 TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(30, 0), 1) + +/* Default pinmux select */ + +#define TMS570_PINMMR_DEFAULT_INIT_LIST(per_pin_action, common_arg) \ + per_pin_action(common_arg, TMS570_BALL_W10_GIOB_3) \ + per_pin_action(common_arg, TMS570_BALL_A5_GIOA_0) \ + per_pin_action(common_arg, TMS570_BALL_C3_MIBSPI3NCS_3) \ + per_pin_action(common_arg, TMS570_BALL_B2_MIBSPI3NCS_2) \ + per_pin_action(common_arg, TMS570_BALL_C2_GIOA_1) \ + per_pin_action(common_arg, TMS570_BALL_E3_HET1_11) \ + per_pin_action(common_arg, TMS570_BALL_E5_ETMDATA_20) \ + per_pin_action(common_arg, TMS570_BALL_F5_ETMDATA_21) \ + per_pin_action(common_arg, TMS570_BALL_C1_GIOA_2) \ + per_pin_action(common_arg, TMS570_BALL_G5_ETMDATA_22) \ + per_pin_action(common_arg, TMS570_BALL_E1_GIOA_3) \ + per_pin_action(common_arg, TMS570_BALL_B5_GIOA_5) \ + per_pin_action(common_arg, TMS570_BALL_K5_ETMDATA_23) \ + per_pin_action(common_arg, TMS570_BALL_B3_HET1_22) \ + per_pin_action(common_arg, TMS570_BALL_H3_GIOA_6) \ + per_pin_action(common_arg, TMS570_BALL_L5_ETMDATA_24) \ + per_pin_action(common_arg, TMS570_BALL_M1_GIOA_7) \ + per_pin_action(common_arg, TMS570_BALL_M5_ETMDATA_25) \ + per_pin_action(common_arg, TMS570_BALL_V2_HET1_01) \ + per_pin_action(common_arg, TMS570_BALL_U1_HET1_03) \ + per_pin_action(common_arg, TMS570_BALL_K18_HET1_00) \ + per_pin_action(common_arg, TMS570_BALL_W5_HET1_02) \ + per_pin_action(common_arg, TMS570_BALL_V6_HET1_05) \ + per_pin_action(common_arg, TMS570_BALL_N5_ETMDATA_26) \ + per_pin_action(common_arg, TMS570_BALL_T1_HET1_07) \ + per_pin_action(common_arg, TMS570_BALL_P5_ETMDATA_27) \ + per_pin_action(common_arg, TMS570_BALL_V7_HET1_09) \ + per_pin_action(common_arg, TMS570_BALL_R5_ETMDATA_28) \ + per_pin_action(common_arg, TMS570_BALL_R6_ETMDATA_29) \ + per_pin_action(common_arg, TMS570_BALL_V5_MIBSPI3NCS_1) \ + per_pin_action(common_arg, TMS570_BALL_W3_HET1_06) \ + per_pin_action(common_arg, TMS570_BALL_R7_ETMDATA_30) \ + per_pin_action(common_arg, TMS570_BALL_N2_HET1_13) \ + per_pin_action(common_arg, TMS570_BALL_G3_MIBSPI1NCS_2) \ + per_pin_action(common_arg, TMS570_BALL_N1_HET1_15) \ + per_pin_action(common_arg, TMS570_BALL_R8_ETMDATA_31) \ + per_pin_action(common_arg, TMS570_BALL_R9_ETMTRACECLKIN) \ + per_pin_action(common_arg, TMS570_BALL_W9_MIBSPI3NENA) \ + per_pin_action(common_arg, TMS570_BALL_V10_MIBSPI3NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_J3_MIBSPI1NCS_3) \ + per_pin_action(common_arg, TMS570_BALL_N19_AD1EVT) \ + per_pin_action(common_arg, TMS570_BALL_N15_ETMDATA_19) \ + per_pin_action(common_arg, TMS570_BALL_N17_EMIF_nCS_0) \ + per_pin_action(common_arg, TMS570_BALL_M15_ETMDATA_18) \ + per_pin_action(common_arg, TMS570_BALL_K17_EMIF_nCS_3) \ + per_pin_action(common_arg, TMS570_BALL_M17_EMIF_nCS_4) \ + per_pin_action(common_arg, TMS570_BALL_L15_ETMDATA_17) \ + per_pin_action(common_arg, TMS570_BALL_P1_HET1_24) \ + per_pin_action(common_arg, TMS570_BALL_A14_HET1_26) \ + per_pin_action(common_arg, TMS570_BALL_K15_ETMDATA_16) \ + per_pin_action(common_arg, TMS570_BALL_G19_MIBSPI1NENA) \ + per_pin_action(common_arg, TMS570_BALL_H18_MIBSPI5NENA) \ + per_pin_action(common_arg, TMS570_BALL_J18_MIBSPI5SOMI_0) \ + per_pin_action(common_arg, TMS570_BALL_J19_MIBSPI5SIMO_0) \ + per_pin_action(common_arg, TMS570_BALL_H19_MIBSPI5CLK) \ + per_pin_action(common_arg, TMS570_BALL_R2_MIBSPI1NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_E18_HET1_08) \ + per_pin_action(common_arg, TMS570_BALL_K19_HET1_28) \ + per_pin_action(common_arg, TMS570_BALL_D17_EMIF_nWE) \ + per_pin_action(common_arg, TMS570_BALL_D16_EMIF_BA_1) \ + per_pin_action(common_arg, TMS570_BALL_C17_EMIF_ADDR_21) \ + per_pin_action(common_arg, TMS570_BALL_C16_EMIF_ADDR_20) \ + per_pin_action(common_arg, TMS570_BALL_C15_EMIF_ADDR_19) \ + per_pin_action(common_arg, TMS570_BALL_D15_EMIF_ADDR_18) \ + per_pin_action(common_arg, TMS570_BALL_E13_ETMDATA_12) \ + per_pin_action(common_arg, TMS570_BALL_C14_EMIF_ADDR_17) \ + per_pin_action(common_arg, TMS570_BALL_D14_EMIF_ADDR_16) \ + per_pin_action(common_arg, TMS570_BALL_E12_ETMDATA_13) \ + per_pin_action(common_arg, TMS570_BALL_D19_HET1_10) \ + per_pin_action(common_arg, TMS570_BALL_E11_ETMDATA_14) \ + per_pin_action(common_arg, TMS570_BALL_B4_HET1_12) \ + per_pin_action(common_arg, TMS570_BALL_E9_ETMDATA_8) \ + per_pin_action(common_arg, TMS570_BALL_C13_EMIF_ADDR_15) \ + per_pin_action(common_arg, TMS570_BALL_A11_HET1_14) \ + per_pin_action(common_arg, TMS570_BALL_C12_EMIF_ADDR_14) \ + per_pin_action(common_arg, TMS570_BALL_M2_GIOB_0) \ + per_pin_action(common_arg, TMS570_BALL_E8_ETMDATA_09) \ + per_pin_action(common_arg, TMS570_BALL_B11_HET1_30) \ + per_pin_action(common_arg, TMS570_BALL_E10_ETMDATA_15) \ + per_pin_action(common_arg, TMS570_BALL_E7_ETMDATA_10) \ + per_pin_action(common_arg, TMS570_BALL_C11_EMIF_ADDR_13) \ + per_pin_action(common_arg, TMS570_BALL_C10_EMIF_ADDR_12) \ + per_pin_action(common_arg, TMS570_BALL_F3_MIBSPI1NCS_1) \ + per_pin_action(common_arg, TMS570_BALL_C9_EMIF_ADDR_11) \ + per_pin_action(common_arg, TMS570_BALL_D5_EMIF_ADDR_1) \ + per_pin_action(common_arg, TMS570_BALL_K2_GIOB_1) \ + per_pin_action(common_arg, TMS570_BALL_C8_EMIF_ADDR_10) \ + per_pin_action(common_arg, TMS570_BALL_C7_EMIF_ADDR_9) \ + per_pin_action(common_arg, TMS570_BALL_D4_EMIF_ADDR_0) \ + per_pin_action(common_arg, TMS570_BALL_C5_EMIF_ADDR_7) \ + per_pin_action(common_arg, TMS570_BALL_C4_EMIF_ADDR_6) \ + per_pin_action(common_arg, TMS570_BALL_E6_ETMDATA_11) \ + per_pin_action(common_arg, TMS570_BALL_C6_EMIF_ADDR_8) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_SPI4CLK) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_SPI4SIMO) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_SPI4SOMI) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_SPI4NENA) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_SPI4NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_A13_HET1_17) \ + per_pin_action(common_arg, TMS570_BALL_B13_HET1_19) \ + per_pin_action(common_arg, TMS570_BALL_H4_HET1_21) \ + per_pin_action(common_arg, TMS570_BALL_J4_HET1_23) \ + per_pin_action(common_arg, TMS570_BALL_M3_HET1_25) \ + per_pin_action(common_arg, TMS570_BALL_A9_HET1_27) \ + per_pin_action(common_arg, TMS570_BALL_A3_HET1_29) \ + per_pin_action(common_arg, TMS570_BALL_J17_HET1_31) \ + per_pin_action(common_arg, TMS570_BALL_W6_MIBSPI5NCS_2) \ + per_pin_action(common_arg, TMS570_BALL_T12_MIBSPI5NCS_3) \ + per_pin_action(common_arg, TMS570_BALL_E19_MIBSPI5NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_B6_MIBSPI5NCS_1) \ + per_pin_action(common_arg, TMS570_BALL_E16_MIBSPI5SIMO_1) \ + per_pin_action(common_arg, TMS570_BALL_H17_MIBSPI5SIMO_2) \ + per_pin_action(common_arg, TMS570_BALL_G17_MIBSPI5SIMO_3) \ + per_pin_action(common_arg, TMS570_BALL_E17_MIBSPI5SOMI_1) \ + per_pin_action(common_arg, TMS570_BALL_H16_MIBSPI5SOMI_2) \ + per_pin_action(common_arg, TMS570_BALL_G16_MIBSPI5SOMI_3) \ + per_pin_action(common_arg, TMS570_BALL_D3_SPI2NENA) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_EMIF_CLK_SEL) \ + per_pin_action(common_arg, TMS570_BALL_F2_GIOB_2) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_GMII_SEL) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_ADC_TRG1) \ + +/* End of default PINMMR list */ + +#endif /*LIBBSP_ARM_TMS570_TMS570LS3137ZWT_PINS_H*/ diff --git a/bsps/arm/tms570/include/tm27.h b/bsps/arm/tms570/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/tms570/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/xilinx-zynq/headers.am b/bsps/arm/xilinx-zynq/headers.am new file mode 100644 index 0000000000..708bd6411a --- /dev/null +++ b/bsps/arm/xilinx-zynq/headers.am @@ -0,0 +1,15 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h diff --git a/bsps/arm/xilinx-zynq/include/bsp.h b/bsps/arm/xilinx-zynq/include/bsp.h new file mode 100644 index 0000000000..afc6a66a06 --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp.h @@ -0,0 +1,80 @@ +/** + * @file + * @ingroup arm_zynq + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_BSP_H +#define LIBBSP_ARM_XILINX_ZYNQ_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_zynq Xilinx-Zynq Support + * @ingroup bsp_arm + * @brief Xilinz-Zynq Board Support Package + * @{ + */ + +#define BSP_ARM_A9MPCORE_SCU_BASE 0xf8f00000 + +#define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100 + +#define BSP_ARM_A9MPCORE_GT_BASE 0xf8f00200 + +#define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600 + +#define BSP_ARM_GIC_DIST_BASE 0xf8f01000 + +#define BSP_ARM_L2C_310_BASE 0xf8f02000 + +#define BSP_ARM_L2C_310_ID 0x410000c8 + +/** + * @brief Zynq specific set up of the MMU. + * + * Provide in the application to override + * the defaults in the BSP. Note the defaults do not map in the GP0 and GP1 + * AXI ports. You should add the specific regions that map into your + * PL rather than just open the whole of the GP[01] address space up. + */ +BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void); + +uint32_t zynq_clock_cpu_1x(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h b/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h new file mode 100644 index 0000000000..c06a47c7f1 --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H +#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H + +#include + +typedef struct { + uint32_t control; +#define CADENCE_I2C_CONTROL_DIV_A(val) BSP_FLD32(val, 14, 15) +#define CADENCE_I2C_CONTROL_DIV_A_GET(reg) BSP_FLD32GET(reg, 14, 15) +#define CADENCE_I2C_CONTROL_DIV_A_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15) +#define CADENCE_I2C_CONTROL_DIV_B(val) BSP_FLD32(val, 8, 13) +#define CADENCE_I2C_CONTROL_DIV_B_GET(reg) BSP_FLD32GET(reg, 8, 13) +#define CADENCE_I2C_CONTROL_DIV_B_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) +#define CADENCE_I2C_CONTROL_CLR_FIFO BSP_BIT32(6) +#define CADENCE_I2C_CONTROL_SLVMON BSP_BIT32(5) +#define CADENCE_I2C_CONTROL_HOLD BSP_BIT32(4) +#define CADENCE_I2C_CONTROL_ACKEN BSP_BIT32(3) +#define CADENCE_I2C_CONTROL_NEA BSP_BIT32(2) +#define CADENCE_I2C_CONTROL_MS BSP_BIT32(1) +#define CADENCE_I2C_CONTROL_RW BSP_BIT32(0) + uint32_t status; +#define CADENCE_I2C_STATUS_BA BSP_BIT32(8) +#define CADENCE_I2C_STATUS_RXOVF BSP_BIT32(7) +#define CADENCE_I2C_STATUS_TXDV BSP_BIT32(6) +#define CADENCE_I2C_STATUS_RXDV BSP_BIT32(5) +#define CADENCE_I2C_STATUS_RXRW BSP_BIT32(3) + uint32_t address; +#define CADENCE_I2C_ADDRESS(val) BSP_FLD32(val, 0, 9) +#define CADENCE_I2C_ADDRESS_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define CADENCE_I2C_ADDRESS_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t data; + uint32_t irqstatus; +#define CADENCE_I2C_IXR_ARB_LOST BSP_BIT32(9) +#define CADENCE_I2C_IXR_RX_UNF BSP_BIT32(7) +#define CADENCE_I2C_IXR_TX_OVR BSP_BIT32(6) +#define CADENCE_I2C_IXR_RX_OVR BSP_BIT32(5) +#define CADENCE_I2C_IXR_SLV_RDY BSP_BIT32(4) +#define CADENCE_I2C_IXR_TO BSP_BIT32(3) +#define CADENCE_I2C_IXR_NACK BSP_BIT32(2) +#define CADENCE_I2C_IXR_DATA BSP_BIT32(1) +#define CADENCE_I2C_IXR_COMP BSP_BIT32(0) + uint32_t transfer_size; +#define CADENCE_I2C_TRANSFER_SIZE(val) BSP_FLD32(val, 0, 7) +#define CADENCE_I2C_TRANSFER_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define CADENCE_I2C_TRANSFER_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t slave_mon_pause; +#define CADENCE_I2C_SLAVE_MON_PAUSE(val) BSP_FLD32(val, 0, 3) +#define CADENCE_I2C_SLAVE_MON_PAUSE_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define CADENCE_I2C_SLAVE_MON_PAUSE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t timeout; +#define CADENCE_I2C_TIMEOUT(val) BSP_FLD32(val, 0, 7) +#define CADENCE_I2C_TIMEOUT_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define CADENCE_I2C_TIMEOUT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t irqmask; + uint32_t irqenable; + uint32_t irqdisable; +} cadence_i2c; + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h b/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h new file mode 100644 index 0000000000..9697cf3354 --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_H +#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +int i2c_bus_register_cadence( + const char *bus_path, + uintptr_t register_base, + uint32_t input_clock, + rtems_vector_number irq +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/i2c.h b/bsps/arm/xilinx-zynq/include/bsp/i2c.h new file mode 100644 index 0000000000..709ea0178e --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/i2c.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_I2C_H +#define LIBBSP_ARM_XILINX_ZYNQ_I2C_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +static inline int zynq_register_i2c_0(void) +{ + return i2c_bus_register_cadence( + "/dev/i2c-0", + 0xe0004000, + zynq_clock_cpu_1x(), + ZYNQ_IRQ_I2C_0 + ); +} + +static inline int zynq_register_i2c_1(void) +{ + return i2c_bus_register_cadence( + "/dev/i2c-1", + 0xe0005000, + zynq_clock_cpu_1x(), + ZYNQ_IRQ_I2C_1 + ); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_I2C_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/irq.h b/bsps/arm/xilinx-zynq/include/bsp/irq.h new file mode 100644 index 0000000000..e8288938fe --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/irq.h @@ -0,0 +1,115 @@ +/** + * @file + * @ingroup zynq_interrupt + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H +#define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H + +#ifndef ASM + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup zynq_interrupt Interrupt Support + * @ingroup arm_zynq + * @brief Interrupt Support + * @{ + */ + +#define ZYNQ_IRQ_CPU_0 32 +#define ZYNQ_IRQ_CPU_1 33 +#define ZYNQ_IRQ_L2_CACHE 34 +#define ZYNQ_IRQ_OCM 35 +#define ZYNQ_IRQ_PMU_0 37 +#define ZYNQ_IRQ_PMU_1 38 +#define ZYNQ_IRQ_XADC 39 +#define ZYNQ_IRQ_DVI 40 +#define ZYNQ_IRQ_SWDT 41 +#define ZYNQ_IRQ_TTC_0_0 42 +#define ZYNQ_IRQ_TTC_1_0 43 +#define ZYNQ_IRQ_TTC_2_0 44 +#define ZYNQ_IRQ_DMAC_ABORT 45 +#define ZYNQ_IRQ_DMAC_0 46 +#define ZYNQ_IRQ_DMAC_1 47 +#define ZYNQ_IRQ_DMAC_2 48 +#define ZYNQ_IRQ_DMAC_3 49 +#define ZYNQ_IRQ_SMC 50 +#define ZYNQ_IRQ_QUAD_SPI 51 +#define ZYNQ_IRQ_GPIO 52 +#define ZYNQ_IRQ_USB_0 53 +#define ZYNQ_IRQ_ETHERNET_0 54 +#define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55 +#define ZYNQ_IRQ_SDIO_0 56 +#define ZYNQ_IRQ_I2C_0 57 +#define ZYNQ_IRQ_SPI_0 58 +#define ZYNQ_IRQ_UART_0 59 +#define ZYNQ_IRQ_CAN_0 60 +#define ZYNQ_IRQ_FPGA_0 61 +#define ZYNQ_IRQ_FPGA_1 62 +#define ZYNQ_IRQ_FPGA_2 63 +#define ZYNQ_IRQ_FPGA_3 64 +#define ZYNQ_IRQ_FPGA_4 65 +#define ZYNQ_IRQ_FPGA_5 66 +#define ZYNQ_IRQ_FPGA_6 67 +#define ZYNQ_IRQ_FPGA_7 68 +#define ZYNQ_IRQ_TTC_0_1 69 +#define ZYNQ_IRQ_TTC_1_1 70 +#define ZYNQ_IRQ_TTC_2_1 71 +#define ZYNQ_IRQ_DMAC_4 72 +#define ZYNQ_IRQ_DMAC_5 73 +#define ZYNQ_IRQ_DMAC_6 74 +#define ZYNQ_IRQ_DMAC_7 75 +#define ZYNQ_IRQ_USB_1 76 +#define ZYNQ_IRQ_ETHERNET_1 77 +#define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78 +#define ZYNQ_IRQ_SDIO_1 79 +#define ZYNQ_IRQ_I2C_1 80 +#define ZYNQ_IRQ_SPI_1 81 +#define ZYNQ_IRQ_UART_1 82 +#define ZYNQ_IRQ_CAN_1 83 +#define ZYNQ_IRQ_FPGA_8 84 +#define ZYNQ_IRQ_FPGA_9 85 +#define ZYNQ_IRQ_FPGA_10 86 +#define ZYNQ_IRQ_FPGA_11 87 +#define ZYNQ_IRQ_FPGA_12 88 +#define ZYNQ_IRQ_FPGA_13 89 +#define ZYNQ_IRQ_FPGA_14 90 +#define ZYNQ_IRQ_FPGA_15 91 +#define ZYNQ_IRQ_PARITY 92 + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 92 + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h b/bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h new file mode 100644 index 0000000000..127f272fd9 --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h @@ -0,0 +1,150 @@ +/** + * @file + * @ingroup zynq_uart_regs + * @brief UART register definitions. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup zynq_uart_regs UART Register Definitions + * @ingroup zynq_uart + * @brief UART Register Definitions + * @{ + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H +#define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H + +#include + +#define ZYNQ_UART_FIFO_DEPTH 64 + +typedef struct zynq_uart { + uint32_t control; +#define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8) +#define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7) +#define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6) +#define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5) +#define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4) +#define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3) +#define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2) +#define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1) +#define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0) + uint32_t mode; +#define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9) +#define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9) +#define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9) +#define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U +#define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U +#define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U +#define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U +#define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7) +#define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7) +#define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7) +#define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U +#define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U +#define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U +#define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5) +#define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5) +#define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) +#define ZYNQ_UART_MODE_PAR_EVEN 0x00U +#define ZYNQ_UART_MODE_PAR_ODD 0x01U +#define ZYNQ_UART_MODE_PAR_SPACE 0x02U +#define ZYNQ_UART_MODE_PAR_MARK 0x03U +#define ZYNQ_UART_MODE_PAR_NONE 0x04U +#define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2) +#define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2) +#define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2) +#define ZYNQ_UART_MODE_CHRL_8 0x00U +#define ZYNQ_UART_MODE_CHRL_7 0x02U +#define ZYNQ_UART_MODE_CHRL_6 0x03U +#define ZYNQ_UART_MODE_CLKS BSP_BIT32(0) + uint32_t irq_en; + uint32_t irq_dis; + uint32_t irq_mask; + uint32_t irq_sts; +#define ZYNQ_UART_TOVR BSP_BIT32(12) +#define ZYNQ_UART_TNFUL BSP_BIT32(11) +#define ZYNQ_UART_TTRIG BSP_BIT32(10) +#define ZYNQ_UART_DMSI BSP_BIT32(9) +#define ZYNQ_UART_TIMEOUT BSP_BIT32(8) +#define ZYNQ_UART_PARE BSP_BIT32(7) +#define ZYNQ_UART_FRAME BSP_BIT32(6) +#define ZYNQ_UART_ROVR BSP_BIT32(5) +#define ZYNQ_UART_TFUL BSP_BIT32(4) +#define ZYNQ_UART_TEMPTY BSP_BIT32(3) +#define ZYNQ_UART_RFUL BSP_BIT32(2) +#define ZYNQ_UART_REMPTY BSP_BIT32(1) +#define ZYNQ_UART_RTRIG BSP_BIT32(0) + uint32_t baud_rate_gen; +#define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15) +#define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + uint32_t rx_timeout; +#define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7) +#define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t rx_fifo_trg_lvl; +#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5) +#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t modem_ctrl; +#define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5) +#define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1) +#define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0) + uint32_t modem_sts; +#define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8) +#define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7) +#define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6) +#define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5) +#define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4) +#define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3) +#define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2) +#define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1) +#define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0) + uint32_t channel_sts; +#define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14) +#define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13) +#define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12) +#define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11) +#define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10) +#define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4) +#define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3) +#define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2) +#define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1) +#define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0) + uint32_t tx_rx_fifo; +#define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7) +#define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t baud_rate_div; +#define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7) +#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t flow_delay; +#define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5) +#define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t reserved_3c[2]; + uint32_t tx_fifo_trg_lvl; +#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5) +#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) +} zynq_uart; + +/** @} */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h b/bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h new file mode 100644 index 0000000000..4d3edfabef --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h @@ -0,0 +1,67 @@ +/** + * @file + * @ingroup zynq_uart + * @brief UART support. + */ + +/* + * Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_H +#define LIBBSP_ARM_XILINX_ZYNQ_UART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup zynq_uart UART Support + * @ingroup arm_zynq + * @brief UART Support + */ + +typedef struct { + rtems_termios_device_context base; + volatile struct zynq_uart *regs; + bool transmitting; + rtems_vector_number irq; +} zynq_uart_context; + +const rtems_termios_device_handler zynq_uart_handler; + +extern zynq_uart_context zynq_uart_instances[2]; + +#define ZYNQ_UART_DEFAULT_BAUD 115200 + +void zynq_uart_initialize(rtems_termios_device_context *base); + +int zynq_uart_read_polled(rtems_termios_device_context *base); + +void zynq_uart_write_polled( + rtems_termios_device_context *base, + char c +); + +/** + * Flush TX FIFO and wait until it is empty. Used in bsp_reset. + */ +void zynq_uart_reset_tx_flush(zynq_uart_context *ctx); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_H */ diff --git a/bsps/arm/xilinx-zynq/include/tm27.h b/bsps/arm/xilinx-zynq/include/tm27.h new file mode 100644 index 0000000000..39b8ecafec --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/tm27.h @@ -0,0 +1,36 @@ +/** + * @file + * @ingroup zynq_tm27 + * @brief Interrupt mechanisms for tm27 test. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/** + * @defgroup zynq_tm27 TM27 Test Support + * @ingroup arm_zynq + * @brief Interrupt Mechanisms for tm27 test + */ + +#include + +#endif /* __tm27_h */ diff --git a/bsps/bfin/TLL6527M/headers.am b/bsps/bfin/TLL6527M/headers.am new file mode 100644 index 0000000000..1ee13168de --- /dev/null +++ b/bsps/bfin/TLL6527M/headers.am @@ -0,0 +1,7 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/bfin/TLL6527M/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/bfin/TLL6527M/include/cplb.h +include_HEADERS += ../../../../../../bsps/bfin/TLL6527M/include/tm27.h diff --git a/bsps/bfin/TLL6527M/include/bsp.h b/bsps/bfin/TLL6527M/include/bsp.h new file mode 100644 index 0000000000..d027d8feff --- /dev/null +++ b/bsps/bfin/TLL6527M/include/bsp.h @@ -0,0 +1,129 @@ +/** + * @file bsp.h + * @ingroup bfin_tll6527m + * @brief Global BSP definitions. + * + * This include file contains all board IO definitions for TLL6527M. + */ + +/* + * COPYRIGHT (c) 2010 by ECE Northeastern University. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license + */ + +#ifndef LIBBSP_BFIN_TLL6527M_BSP_H +#define LIBBSP_BFIN_TLL6527M_BSP_H + +#ifndef ASM + +#include +#include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup bfin_tll6527m TLL6527M Support + * @ingroup bsp_bfin + * @brief TLL6527M Support Package + * @{ + */ + +/* + * PLL and clock setup values: + */ + +/* + * PLL configuration for TLL6527M + * + * XTL = 27 MHz + * CLKIN = 13 MHz + * VCO = 391 MHz + * CCLK = 391 MHz + * SCLK = 130 MHz + */ + +/** + * @name PLL Configuration + * @{ + */ + +#define PLL_CSEL 0x0000 ///< @brief CCLK = VCO */ +#define PLL_SSEL 0x0003 ///< @brief SCLK = CCLK/3 */ +#define PLL_MSEL 0x3A00 ///< @brief VCO = 29xCLKIN */ +#define PLL_DF 0x0001 ///< @brief CLKIN = XTL/2 */ + +/** @} */ + +/** + * @name Clock setup values + * @{ + */ + +#define CLKIN (25000000) ///< @brief Input clock to the PLL */ +#define CCLK (600000000) ///< @brief CORE CLOCK */ +#define SCLK (100000000) ///< @brief SYSTEM CLOCK */ + +/** @} */ + +/** + * @name UART setup values + * @{ + */ + +#define BAUDRATE 57600 ///< @brief Console Baudrate */ +#define WORD_5BITS 0x00 ///< @brief 5 bits word */ +#define WORD_6BITS 0x01 ///< @brief 6 bits word */ +#define WORD_7BITS 0x02 ///< @brief 7 bits word */ +#define WORD_8BITS 0x03 ///< @brief 8 bits word */ +#define EVEN_PARITY 0x18 ///< @brief Enable EVEN parity */ +#define ODD_PARITY 0x08 ///< @brief Enable ODD parity */ +#define TWO_STP_BIT 0x04 ///< @brief 2 stop bits */ + +/** @} */ + +/** + * @brief Install an interrupt handler + * + * This method installs an interrupt handle. + * + * @param[in] handler is the isr routine + * @param[in] vector is the vector number + * @param[in] type indicates whether RTEMS or RAW intr + * + * @return returns old vector + */ +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Internal BSP methods that are used across file boundaries + */ +void Init_RTC(void); + +/* + * Prototype for methods in .S files that are referenced from C. + */ +void bfin_null_isr(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/bfin/TLL6527M/include/cplb.h b/bsps/bfin/TLL6527M/include/cplb.h new file mode 100644 index 0000000000..b6035ca142 --- /dev/null +++ b/bsps/bfin/TLL6527M/include/cplb.h @@ -0,0 +1,47 @@ +/** + * @file + * @ingroup tll6527m_cplb + * @brief CPLB configurations. + */ + +/* cplb.h + * + * Copyright (c) 2006 by Atos Automacao Industrial Ltda. + * written by Alain Schaefer + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef _CPLB_H +#define _CPLB_H + +/** + * @defgroup tll6527m_cplb CPLB Configuration + * @ingroup bfin_tll6527m + * @brief CPLB Configuration + * @{ + */ + +/* CPLB configurations */ +#define CPLB_DEF_CACHE_WT CPLB_L1_CHBL | CPLB_WT +#define CPLB_DEF_CACHE_WB CPLB_L1_CHBL +#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY + +#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT +#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR + +#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID +#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID + +#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID +#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE +#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID +#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL + +#define CPLB_DDOCACHE_WT CPLB_DNOCACHE | CPLB_DEF_CACHE_WT +#define CPLB_DDOCACHE_WB CPLB_DNOCACHE | CPLB_DEF_CACHE_WB + +/** @} */ + +#endif /* _CPLB_H */ diff --git a/bsps/bfin/TLL6527M/include/tm27.h b/bsps/bfin/TLL6527M/include/tm27.h new file mode 100644 index 0000000000..787004f8a6 --- /dev/null +++ b/bsps/bfin/TLL6527M/include/tm27.h @@ -0,0 +1,50 @@ +/** + * @file + * @ingroup tll6527m_tm27 + * @brief Interrupt mechanisms for tm27 test. + */ + +/* + * tm27.h + * + * COPYRIGHT (c) 2010 by ECE Northeastern University. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/** + * @defgroup tll6527m_tm27 TM27 Test Support + * @ingroup bfin_tll6527m + * @brief Interrupt Mechanisms for TM27 + * @{ + */ + +/* + * Define the interrupt mechanism for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector(handler) \ +{ \ + set_vector( handler, 0x06, 1 ); \ +} + +#define Cause_tm27_intr() asm volatile("raise 0x06;" : :); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +/** @} */ + +#endif diff --git a/bsps/bfin/bf537Stamp/headers.am b/bsps/bfin/bf537Stamp/headers.am new file mode 100644 index 0000000000..ae18fe2d1d --- /dev/null +++ b/bsps/bfin/bf537Stamp/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/bfin/bf537Stamp/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/bfin/bf537Stamp/include/tm27.h diff --git a/bsps/bfin/bf537Stamp/include/bsp.h b/bsps/bfin/bf537Stamp/include/bsp.h new file mode 100644 index 0000000000..8b14be13f6 --- /dev/null +++ b/bsps/bfin/bf537Stamp/include/bsp.h @@ -0,0 +1,122 @@ +/* bsp.h + * + * This include file contains all board IO definitions for bf537Stamp. + * + * Copyright (c) 2006 by Atos Automacao Industrial Ltda. + * written by Alain Schaefer + * and Antonio Giovanini + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + + +#ifndef LIBBSP_BFIN_BF537STAMP_BSP_H +#define LIBBSP_BFIN_BF537STAMP_BSP_H + +#ifndef ASM + +#include +#include + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* configure data cache to use 16K of each SRAM bank when enabled */ +#define BSP_DATA_CACHE_CONFIG (3 << DMEM_CONTROL_DMC_SHIFT) + + +/* + * PLL and clock setup values: + */ + +/* + * PLL configuration for bf533Stamp + * + * XTL = 27 MHz + * CLKIN = 13 MHz + * VCO = 391 MHz + * CCLK = 391 MHz + * SCLK = 130 MHz + */ + +#define PLL_CSEL 0x0000 /* CCLK = VCO */ +#define PLL_SSEL 0x0003 /* SCLK = CCLK/3 */ +#define PLL_MSEL 0x3A00 /* VCO = 29xCLKIN */ +#define PLL_DF 0x0001 /* CLKIN = XTL/2 */ + +#define CCLK 500000000 /* CORE CLOCK */ +#define SCLK 100000000 /* SYSTEM CLOCK */ + +#define CONSOLE_FORCE_BAUD 57600 + +/* + * Blackfin environment memory map + */ +#define L1_DATA_SRAM_A 0xff800000L + +#define FIFOLENGTH 0x100 + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#define rtems_bsp_delay( microseconds ) \ + { \ + } + +/* Constants */ + +#define RAM_START 0 +#define RAM_END 0x4000000 + +/* functions */ + +/* + * Helper Function to use the EzKits LEDS. + * Can be used by the Application. + */ +void setLED(uint8_t value); + +/* + * Helper Function to use the EzKits LEDS + */ +uint8_t getLEDs(void); +void setLEDs(uint8_t value); +uint8_t getButtons(void); + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +/* + * Internal BSP methods that are used across file boundaries + */ +void Init_RTC(void); + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int bf537Stamp_network_driver_attach(struct rtems_bsdnet_ifconfig *, int); + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH bf537Stamp_network_driver_attach + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/bfin/bf537Stamp/include/tm27.h b/bsps/bfin/bf537Stamp/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/bfin/bf537Stamp/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/bfin/eZKit533/headers.am b/bsps/bfin/eZKit533/headers.am new file mode 100644 index 0000000000..0a6e170dbc --- /dev/null +++ b/bsps/bfin/eZKit533/headers.am @@ -0,0 +1,7 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/bfin/eZKit533/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/bfin/eZKit533/include/cplb.h +include_HEADERS += ../../../../../../bsps/bfin/eZKit533/include/tm27.h diff --git a/bsps/bfin/eZKit533/include/bsp.h b/bsps/bfin/eZKit533/include/bsp.h new file mode 100644 index 0000000000..865ed72259 --- /dev/null +++ b/bsps/bfin/eZKit533/include/bsp.h @@ -0,0 +1,166 @@ +/** + * @file + * @ingroup bfin_ezkit533 + * @brief Global BSP definitions. + */ + +/* bsp.h + * + * This include file contains all board IO definitions for eZKit533. + * + * Copyright (c) 2006 by Atos Automacao Industrial Ltda. + * written by Alain Schaefer + * and Antonio Giovanini + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + + +#ifndef LIBBSP_BFIN_EZKIT533_BSP_H +#define LIBBSP_BFIN_EZKIT533_BSP_H + +#ifndef ASM + +#include + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup bfin_ezkit533 eZKit533 Support + * @ingroup bsp_bfin + * @brief eZKit533 Board Support Package + * @{ + */ + +/** + * @name PLL and clock setup values: + * @brief PLL configuration for ezkit533 + * + * XTL = 27 MHz + * CLKIN = 13 MHz + * VCO = 391 MHz + * CCLK = 391 MHz + * SCLK = 130 MHz + * + * @{ + * + */ + +#define PLL_CSEL 0x0000 ///< @brief CCLK = VCO */ +#define PLL_SSEL 0x0003 ///< @brief SCLK = CCLK/3 */ +#define PLL_MSEL 0x3A00 ///< @brief VCO = 29xCLKIN */ +#define PLL_DF 0x0001 ///< @brief CLKIN = XTL/2 */ + +#define CCLK 391000000 ///< @brief CORE CLOCK */ +#define SCLK 130000000 ///< @brief SYSTEM CLOCK */ + +/** @} */ + +/** + * @name UART setup values + * @{ + */ + +#define BAUDRATE 57600 ///< @brief Console Baudrate */ +#define WORD_5BITS 0x00 ///< @brief 5 bits word */ +#define WORD_6BITS 0x01 ///< @brief 6 bits word */ +#define WORD_7BITS 0x02 ///< @brief 7 bits word */ +#define WORD_8BITS 0x03 ///< @brief 8 bits word */ +#define EVEN_PARITY 0x18 ///< @brief Enable EVEN parity */ +#define ODD_PARITY 0x08 ///< @brief Enable ODD parity */ +#define TWO_STP_BIT 0x04 ///< @brief 2 stop bits */ + +/** @} */ + +/** + * @name Ezkit flash ports + * @{ + */ + +#define FlashA_PortB_Dir 0x20270007L +#define FlashA_PortB_Data 0x20270005L + +/** @} */ + +/** + * @brief Blackfin environment memory map + */ +#define L1_DATA_SRAM_A 0xff800000L + +#define FIFOLENGTH 0x100 + +/** + * @name Constants + * @{ + */ + +#define RAM_START 0 +#define RAM_END 0x100000 + +/** @} */ + +/** + * @name functions + * @{ + */ + +/** + * @brief Helper Function to use the EzKits LEDS. + * Can be used by the Application. + */ +void setLED (uint8_t value); + +/** + * @brief Helper Function to use the EzKits LEDS + */ +uint8_t getLED (void); + +/** + * @brief Install an interrupt handler + * + * This method installs an interrupt handle. + * + * @param[in] handler is the isr routine + * @param[in] vector is the vector number + * @param[in] type indicates whether RTEMS or RAW intr + * + * @return returns old vector + */ +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Internal BSP methods that are used across file boundaries + */ +void Init_RTC(void); + +/* + * Prototype for methods in .S files that are referenced from C. + */ +void bfin_null_isr(void); + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/bfin/eZKit533/include/cplb.h b/bsps/bfin/eZKit533/include/cplb.h new file mode 100644 index 0000000000..2c215e8954 --- /dev/null +++ b/bsps/bfin/eZKit533/include/cplb.h @@ -0,0 +1,47 @@ +/** + * @file + * @ingroup ezkit533_cplb + * @brief CPLB configurations. + */ + +/* cplb.h + * + * Copyright (c) 2006 by Atos Automacao Industrial Ltda. + * written by Alain Schaefer + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef _CPLB_H +#define _CPLB_H + +/** + * @defgroup ezkit533_cplb CPLB Configuration + * @ingroup bfin_ezkit533 + * @brief CPLB Configuration + * @{ + */ + +/* CPLB configurations */ +#define CPLB_DEF_CACHE_WT CPLB_L1_CHBL | CPLB_WT +#define CPLB_DEF_CACHE_WB CPLB_L1_CHBL +#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY + +#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT +#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR + +#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID +#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID + +#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID +#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE +#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID +#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL + +#define CPLB_DDOCACHE_WT CPLB_DNOCACHE | CPLB_DEF_CACHE_WT +#define CPLB_DDOCACHE_WB CPLB_DNOCACHE | CPLB_DEF_CACHE_WB + +/** @} */ + +#endif /* _CPLB_H */ diff --git a/bsps/bfin/eZKit533/include/tm27.h b/bsps/bfin/eZKit533/include/tm27.h new file mode 100644 index 0000000000..6aaf4cfa1d --- /dev/null +++ b/bsps/bfin/eZKit533/include/tm27.h @@ -0,0 +1,48 @@ +/** + * @file + * @ingroup ezkit533_tm27 + * @brief Interrupt mechanisms for the tm27 test. + */ + +/* + * tm27.h + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/** + * @defgroup ezkit533_tm27 TM27 Test Support + * @ingroup bfin_ezkit533 + * @brief Interrupt Mechanisms for TM27 + * @{ + */ + +/* + * Define the interrupt mechanism for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector(handler) \ +{ \ + set_vector( handler, 0x06, 1 ); \ +} + +#define Cause_tm27_intr() __asm__ volatile("raise 0x06;" : :); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +/** @} */ + +#endif diff --git a/bsps/bfin/headers.am b/bsps/bfin/headers.am new file mode 100644 index 0000000000..67f3f02572 --- /dev/null +++ b/bsps/bfin/headers.am @@ -0,0 +1,37 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../bsps/bfin/include/bf52x.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/bfin/include/bsp/interrupt.h + +include_libcpudir = $(includedir)/libcpu +include_libcpu_HEADERS = +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/bf533.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/bf537.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/cecRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/coreTimerRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/dmaRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/ebiuRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/ethernet.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/ethernetRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/gpioRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/interrupt.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/memoryRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/mmu.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/mmuRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/ppiRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/rtcRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/sicRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/spi.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/spiRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/sport.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/sportRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/timerRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/twi.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/twiRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/uart.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/uartRegs.h +include_libcpu_HEADERS += ../../../../../bsps/bfin/include/libcpu/wdogRegs.h diff --git a/bsps/bfin/include/bf52x.h b/bsps/bfin/include/bf52x.h new file mode 100644 index 0000000000..6c3d087c79 --- /dev/null +++ b/bsps/bfin/include/bf52x.h @@ -0,0 +1,131 @@ +/** + *@file bf52x.h + * + *@brief + * - This file provides the register address for the 52X model. The file is + * based on the 533 implementation with some addition to support 52X range of + * processors. + * + * Target: TLL6527v1-0 + * Compiler: + * + * COPYRIGHT (c) 2010 by ECE Northeastern University. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license + * + * @author Rohan Kangralkar, ECE, Northeastern University + * (kangralkar.r@husky.neu.edu) + * + * LastChange: + */ + +#ifndef _BF52X_H_ +#define _BF52X_H_ + +/* register (or register block) addresses */ + +#define SIC_BASE_ADDRESS 0xffc00100 +#define WDOG_BASE_ADDRESS 0xffc00200 +#define RTC_BASE_ADDRESS 0xffc00300 +#define UART0_BASE_ADDRESS 0xffc00400 +#define UART1_BASE_ADDRESS 0xffc02000 +#define SPI_BASE_ADDRESS 0xffc00500 +#define TIMER_BASE_ADDRESS 0xffc00600 +#define TIMER_CHANNELS 3 +#define TIMER_PITCH 0x10 +#define TIMER0_BASE_ADDRESS 0xffc00600 +#define TIMER1_BASE_ADDRESS 0xffc00610 +#define TIMER2_BASE_ADDRESS 0xffc00620 +#define TIMER_ENABLE 0xffc00640 +#define TIMER_DISABLE 0xffc00644 +#define TIMER_STATUS 0xffc00648 +#define PORTFIO_BASE_ADDRESS 0xffc00700 +#define SPORT0_BASE_ADDRESS 0xffc00800 +#define SPORT1_BASE_ADDRESS 0xffc00900 +#define EBIU_BASE_ADDRESS 0xffc00a00 +#define DMA_TC_PER 0xffc00b0c +#define DMA_TC_CNT 0xffc00b10 +#define DMA_BASE_ADDRESS 0xffc00c00 +#define DMA_CHANNELS 8 +#define DMA_PITCH 0x40 +#define DMA0_BASE_ADDRESS 0xffc00c00 +#define DMA1_BASE_ADDRESS 0xffc00c40 +#define DMA2_BASE_ADDRESS 0xffc00c80 +#define DMA3_BASE_ADDRESS 0xffc00cc0 +#define DMA4_BASE_ADDRESS 0xffc00d00 +#define DMA5_BASE_ADDRESS 0xffc00d40 +#define DMA6_BASE_ADDRESS 0xffc00d80 +#define DMA7_BASE_ADDRESS 0xffc00dc0 +#define DMA8_BASE_ADDRESS 0xffc00e00 +#define DMA9_BASE_ADDRESS 0xffc00e40 +#define DMA10_BASE_ADDRESS 0xffc00e80 +#define DMA11_BASE_ADDRESS 0xffc00ec0 +#define MDMA_BASE_ADDRESS 0xffc00e00 +#define MDMA_CHANNELS 2 +#define MDMA_D_S 0x40 +#define MDMA_PITCH 0x80 +#define MDMA0D_BASE_ADDRESS 0xffc00e00 +#define MDMA0S_BASE_ADDRESS 0xffc00e40 +#define MDMA1D_BASE_ADDRESS 0xffc00e80 +#define MDMA1S_BASE_ADDRESS 0xffc00ec0 +#define PPI_BASE_ADDRESS 0xffc01000 + + +/* register fields */ + +#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 +#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 +#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 +#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 +#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 +#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 +#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f +#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 + +#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 +#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 +#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 +#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 +#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 +#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 +#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f +#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 + +#define TIMER_ENABLE_TIMEN2 0x0004 +#define TIMER_ENABLE_TIMEN1 0x0002 +#define TIMER_ENABLE_TIMEN0 0x0001 + +#define TIMER_DISABLE_TIMDIS2 0x0004 +#define TIMER_DISABLE_TIMDIS1 0x0002 +#define TIMER_DISABLE_TIMDIS0 0x0001 + +#define TIMER_STATUS_TRUN2 0x00004000 +#define TIMER_STATUS_TRUN1 0x00002000 +#define TIMER_STATUS_TRUN0 0x00001000 +#define TIMER_STATUS_TOVF_ERR2 0x00000040 +#define TIMER_STATUS_TOVF_ERR1 0x00000020 +#define TIMER_STATUS_TOVF_ERR0 0x00000010 +#define TIMER_STATUS_TIMIL2 0x00000004 +#define TIMER_STATUS_TIMIL1 0x00000002 +#define TIMER_STATUS_TIMIL0 0x00000001 + +/* Core Event Controller vectors */ + +#define CEC_EMULATION_VECTOR 0 +#define CEC_RESET_VECTOR 1 +#define CEC_NMI_VECTOR 2 +#define CEC_EXCEPTIONS_VECTOR 3 +#define CEC_HARDWARE_ERROR_VECTOR 5 +#define CEC_CORE_TIMER_VECTOR 6 +#define CEC_INTERRUPT_BASE_VECTOR 7 +#define CEC_INTERRUPT_COUNT 9 + + +/* System Interrupt Controller vectors */ + +#define SIC_IAR_COUNT 8 + +#endif /* _BF52X_H_ */ + diff --git a/bsps/bfin/include/bsp/interrupt.h b/bsps/bfin/include/bsp/interrupt.h new file mode 100644 index 0000000000..7a98775dd5 --- /dev/null +++ b/bsps/bfin/include/bsp/interrupt.h @@ -0,0 +1,144 @@ +/** + *@file interrupt.h + * + *@brief + * - This file implements interrupt dispatcher. The init code is taken from + * the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR + * registers some portion is written twice. + * + * Target: TLL6527v1-0 + * Compiler: + * + * COPYRIGHT (c) 2010 by ECE Northeastern University. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license + * + * @author Rohan Kangralkar, ECE, Northeastern University + * (kangralkar.r@husky.neu.edu) + * + * LastChange: + */ + +#ifndef _BFIN_INTERRUPT_H_ +#define _BFIN_INTERRUPT_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** The type of interrupts handled by the SIC + */ +typedef enum { + IRQ_PLL_WAKEUP_INTERRUPT, /* 0 */ + IRQ_DMA_ERROR_0, /* 1 */ + IRQ_DMAR0_BLOCK_INTERRUPT, /* 2 */ + IRQ_DMAR1_BLOCK_INTERRUPT, /* 3 */ + IRQ_DMAR0_OVERFLOW_ERROR, /* 4 */ + IRQ_DMAR1_OVERFLOW_ERROR, /* 5 */ + IRQ_PPI_STATUS, /* 6 */ + IRQ_MAC_STATUS, /* 7 */ + IRQ_SPORT0_STATUS, /* 8 */ + IRQ_SPORT1_STATUS, /* 9 */ + IRQ_RESERVED_10, /* 10 */ + IRQ_RESERVED_11, /* 11 */ + IRQ_UART0_STATUS, /* 12 */ + IRQ_UART1_STATUS, /* 13 */ + IRQ_REAL_TIME_CLOCK, /* 14 */ + IRQ_DMA0_PPI_NFC, /* 15 */ + IRQ_DMA3_SPORT0_RX, /* 16 */ + IRQ_DMA4_SPORT0_TX, /* 17 */ + IRQ_DMA5_SPORT1_RX, /* 18 */ + IRQ_DMA6_SPORT1_TX, /* 19 */ + IRQ_TWI_INTERRUPT, /* 20 */ + IRQ_DMA7_SPI, /* 21 */ + IRQ_DMA8_UART0_RX, /* 22 */ + IRQ_DMA9_UART0_TX, /* 23 */ + IRQ_DMA10_UART1_RX, /* 24 */ + IRQ_DMA11_UART1_TX, /* 25 */ + IRQ_OTP, /* 26 */ + IRQ_GP_COUNTER, /* 27 */ + IRQ_DMA1_MAC_RX_HOSTDP, /* 28 */ + IRQ_PORT_H_INTERRUPT_A, /* 29 */ + IRQ_DMA2_MAC_TX_NFC, /* 30 */ + IRQ_PORT_H_INTERRUPT_B, /* 31 */ + SIC_ISR0_MAX, /* 32 ***/ + IRQ_TIMER0 = SIC_ISR0_MAX, /* 32 */ + IRQ_TIMER1, /* 33 */ + IRQ_TIMER2, /* 34 */ + IRQ_TIMER3, /* 35 */ + IRQ_TIMER4, /* 36 */ + IRQ_TIMER5, /* 37 */ + IRQ_TIMER6, /* 38 */ + IRQ_TIMER7, /* 39 */ + IRQ_PORT_G_INTERRUPT_A, /* 40 */ + IRQ_PORT_G_INTERRUPT_B, /* 41 */ + IRQ_MDMA0_STREAM_0_INTERRUPT, /* 42 */ + IRQ_MDMA1_STREAM_0_INTERRUPT, /* 43 */ + IRQ_SOFTWARE_WATCHDOG_INTERRUPT, /* 44 */ + IRQ_PORT_F_INTERRUPT_A, /* 45 */ + IRQ_PORT_F_INTERRUPT_B, /* 46 */ + IRQ_SPI_STATUS, /* 47 */ + IRQ_NFC_STATUS, /* 48 */ + IRQ_HOSTDP_STATUS, /* 49 */ + IRQ_HOREAD_DONE_INTERRUPT, /* 50 */ + IRQ_RESERVED_19, /* 51 */ + IRQ_USB_INT0_INTERRUPT, /* 52 */ + IRQ_USB_INT1_INTERRUPT, /* 53 */ + IRQ_USB_INT2_INTERRUPT, /* 54 */ + IRQ_USB_DMAINT, /* 55 */ + IRQ_MAX, /* 56 */ +} e_isr_t; + + + + +/* source is the source to the SIC (the bit number in SIC_ISR). isr is + the function that will be called when the interrupt is active. */ +typedef struct bfin_isr_s { +#if INTERRUPT_USE_TABLE + e_isr_t source; + void (*pFunc)(void *arg); + void *pArg; + int priority; /** not used */ +#else + int source; + void (*isr)(void *arg); + void *_arg; + /* the following are for internal use only */ + uint32_t mask0; + uint32_t mask1; + uint32_t vector; + struct bfin_isr_s *next; +#endif +} bfin_isr_t; + +/** + * This routine registers a new ISR. It will write a new entry to the IVT table + * @param isr contains a callback function and source + * @return rtems status code + */ +rtems_status_code bfin_interrupt_register(bfin_isr_t *isr); + +/** + * This function unregisters a registered interrupt handler. + * @param isr + */ +rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr); + +/** + * blackfin interrupt initialization routine. It initializes the bfin ISR + * dispatcher. It will also create SIC CEC map which will be used for + * identifying the ISR. + */ +void bfin_interrupt_init(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* _BFIN_INTERRUPT_H_ */ + diff --git a/bsps/bfin/include/libcpu/bf533.h b/bsps/bfin/include/libcpu/bf533.h new file mode 100644 index 0000000000..78cfaa0125 --- /dev/null +++ b/bsps/bfin/include/libcpu/bf533.h @@ -0,0 +1,135 @@ +/* Blackfin BF533 Definitions + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _bf533_h_ +#define _bf533_h_ + +/* register (or register block) addresses */ + +#define SIC_BASE_ADDRESS 0xffc00100 +#define WDOG_BASE_ADDRESS 0xffc00200 +#define RTC_BASE_ADDRESS 0xffc00300 +#define UART0_BASE_ADDRESS 0xffc00400 +#define SPI_BASE_ADDRESS 0xffc00500 +#define TIMER_BASE_ADDRESS 0xffc00600 +#define TIMER_CHANNELS 3 +#define TIMER_PITCH 0x10 +#define TIMER0_BASE_ADDRESS 0xffc00600 +#define TIMER1_BASE_ADDRESS 0xffc00610 +#define TIMER2_BASE_ADDRESS 0xffc00620 +#define TIMER_ENABLE 0xffc00640 +#define TIMER_DISABLE 0xffc00644 +#define TIMER_STATUS 0xffc00648 +#define PORTFIO_BASE_ADDRESS 0xffc00700 +#define SPORT0_BASE_ADDRESS 0xffc00800 +#define SPORT1_BASE_ADDRESS 0xffc00900 +#define EBIU_BASE_ADDRESS 0xffc00a00 +#define DMA_TC_PER 0xffc00b0c +#define DMA_TC_CNT 0xffc00b10 +#define DMA_BASE_ADDRESS 0xffc00c00 +#define DMA_CHANNELS 8 +#define DMA_PITCH 0x40 +#define DMA0_BASE_ADDRESS 0xffc00c00 +#define DMA1_BASE_ADDRESS 0xffc00c40 +#define DMA2_BASE_ADDRESS 0xffc00c80 +#define DMA3_BASE_ADDRESS 0xffc00cc0 +#define DMA4_BASE_ADDRESS 0xffc00d00 +#define DMA5_BASE_ADDRESS 0xffc00d40 +#define DMA6_BASE_ADDRESS 0xffc00d80 +#define DMA7_BASE_ADDRESS 0xffc00dc0 +#define MDMA_BASE_ADDRESS 0xffc00e00 +#define MDMA_CHANNELS 2 +#define MDMA_D_S 0x40 +#define MDMA_PITCH 0x80 +#define MDMA0D_BASE_ADDRESS 0xffc00e00 +#define MDMA0S_BASE_ADDRESS 0xffc00e40 +#define MDMA1D_BASE_ADDRESS 0xffc00e80 +#define MDMA1S_BASE_ADDRESS 0xffc00ec0 +#define PPI_BASE_ADDRESS 0xffc01000 + + +/* register fields */ + +#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 +#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 +#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 +#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 +#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 +#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 +#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f +#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 + +#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 +#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 +#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 +#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 +#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 +#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 +#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f +#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 + +#define TIMER_ENABLE_TIMEN2 0x0004 +#define TIMER_ENABLE_TIMEN1 0x0002 +#define TIMER_ENABLE_TIMEN0 0x0001 + +#define TIMER_DISABLE_TIMDIS2 0x0004 +#define TIMER_DISABLE_TIMDIS1 0x0002 +#define TIMER_DISABLE_TIMDIS0 0x0001 + +#define TIMER_STATUS_TRUN2 0x00004000 +#define TIMER_STATUS_TRUN1 0x00002000 +#define TIMER_STATUS_TRUN0 0x00001000 +#define TIMER_STATUS_TOVF_ERR2 0x00000040 +#define TIMER_STATUS_TOVF_ERR1 0x00000020 +#define TIMER_STATUS_TOVF_ERR0 0x00000010 +#define TIMER_STATUS_TIMIL2 0x00000004 +#define TIMER_STATUS_TIMIL1 0x00000002 +#define TIMER_STATUS_TIMIL0 0x00000001 + +/* Core Event Controller vectors */ + +#define CEC_EMULATION_VECTOR 0 +#define CEC_RESET_VECTOR 1 +#define CEC_NMI_VECTOR 2 +#define CEC_EXCEPTIONS_VECTOR 3 +#define CEC_HARDWARE_ERROR_VECTOR 5 +#define CEC_CORE_TIMER_VECTOR 6 +#define CEC_INTERRUPT_BASE_VECTOR 7 +#define CEC_INTERRUPT_COUNT 9 + + +/* System Interrupt Controller vectors */ + +#define SIC_IAR_COUNT 3 + +#define SIC_PLL_WAKEUP_VECTOR 0 +#define SIC_DMA_ERROR_VECTOR 1 +#define SIC_PPI_ERROR_VECTOR 2 +#define SIC_SPORT0_ERROR_VECTOR 3 +#define SIC_SPORT1_ERROR_VECTOR 4 +#define SIC_SPI_ERROR_VECTOR 5 +#define SIC_UART0_ERROR_VECTOR 6 +#define SIC_RTC_VECTOR 7 +#define SIC_DMA0_PPI_VECTOR 8 +#define SIC_DMA1_SPORT0_RX_VECTOR 9 +#define SIC_DMA2_SPORT0_TX_VECTOR 10 +#define SIC_DMA3_SPORT1_RX_VECTOR 11 +#define SIC_DMA4_SPORT1_TX_VECTOR 12 +#define SIC_DMA5_SPI_VECTOR 13 +#define SIC_DMA6_UART0_RX_VECTOR 14 +#define SIC_DMA7_UART0_TX_VECTOR 15 +#define SIC_TIMER0_VECTOR 16 +#define SIC_TIMER1_VECTOR 17 +#define SIC_TIMER2_VECTOR 18 +#define SIC_MDMA0_VECTOR 21 +#define SIC_MDMA1_VECTOR 22 +#define SIC_WATCHDOG_VECTOR 23 + +#endif /* _bf533_h_ */ diff --git a/bsps/bfin/include/libcpu/bf537.h b/bsps/bfin/include/libcpu/bf537.h new file mode 100644 index 0000000000..8ed235205f --- /dev/null +++ b/bsps/bfin/include/libcpu/bf537.h @@ -0,0 +1,225 @@ +/* Blackfin BF537 Definitions + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _bf537_h_ +#define _bf537_h_ + +/* register (or register block) addresses */ + +#define SIC_BASE_ADDRESS 0xffc00100 +#define WDOG_BASE_ADDRESS 0xffc00200 +#define RTC_BASE_ADDRESS 0xffc00300 +#define UART0_BASE_ADDRESS 0xffc00400 +#define SPI_BASE_ADDRESS 0xffc00500 +#define TIMER_BASE_ADDRESS 0xffc00600 +#define TIMER_CHANNELS 8 +#define TIMER_PITCH 0x10 +#define TIMER0_BASE_ADDRESS 0xffc00600 +#define TIMER1_BASE_ADDRESS 0xffc00610 +#define TIMER2_BASE_ADDRESS 0xffc00620 +#define TIMER3_BASE_ADDRESS 0xffc00630 +#define TIMER4_BASE_ADDRESS 0xffc00640 +#define TIMER5_BASE_ADDRESS 0xffc00650 +#define TIMER6_BASE_ADDRESS 0xffc00660 +#define TIMER7_BASE_ADDRESS 0xffc00670 +#define TIMER_ENABLE 0xffc00680 +#define TIMER_DISABLE 0xffc00684 +#define TIMER_STATUS 0xffc00688 +#define PORTFIO_BASE_ADDRESS 0xffc00700 +#define SPORT0_BASE_ADDRESS 0xffc00800 +#define SPORT1_BASE_ADDRESS 0xffc00900 +#define EBIU_BASE_ADDRESS 0xffc00a00 +#define DMA_TC_PER 0xffc00b0c +#define DMA_TC_CNT 0xffc00b10 +#define DMA_BASE_ADDRESS 0xffc00c00 +#define DMA_CHANNELS 12 +#define DMA_PITCH 0x40 +#define DMA0_BASE_ADDRESS 0xffc00c00 +#define DMA1_BASE_ADDRESS 0xffc00c40 +#define DMA2_BASE_ADDRESS 0xffc00c80 +#define DMA3_BASE_ADDRESS 0xffc00cc0 +#define DMA4_BASE_ADDRESS 0xffc00d00 +#define DMA5_BASE_ADDRESS 0xffc00d40 +#define DMA6_BASE_ADDRESS 0xffc00d80 +#define DMA7_BASE_ADDRESS 0xffc00dc0 +#define DMA8_BASE_ADDRESS 0xffc00e00 +#define DMA9_BASE_ADDRESS 0xffc00e40 +#define DMA10_BASE_ADDRESS 0xffc00e80 +#define DMA11_BASE_ADDRESS 0xffc00ec0 +#define MDMA_BASE_ADDRESS 0xffc00f00 +#define MDMA_CHANNELS 2 +#define MDMA_D_S 0x40 +#define MDMA_PITCH 0x80 +#define MDMA0D_BASE_ADDRESS 0xffc00f00 +#define MDMA0S_BASE_ADDRESS 0xffc00f40 +#define MDMA1D_BASE_ADDRESS 0xffc00f80 +#define MDMA1S_BASE_ADDRESS 0xffc00fc0 +#define PPI_BASE_ADDRESS 0xffc01000 +#define TWI_BASE_ADDRESS 0xffc01400 +#define PORTGIO_BASE_ADDRESS 0xffc01500 +#define PORTHIO_BASE_ADDRESS 0xffc01700 +#define UART1_BASE_ADDRESS 0xffc02000 +#define CAN_BASE_ADDRESS 0xffc02a00 +#define CAN_AM_BASE_ADDRESS 0xffc02b00 +#define CAN_MB_BASE_ADDRESS 0xffc02c00 +#define EMAC_BASE_ADDRESS 0xffc03000 +#define PORTF_FER 0xffc03200 +#define PORTG_FER 0xffc03204 +#define PORTH_FER 0xffc03208 +#define PORT_MUX 0xffc0320c +#define HMDMA0_BASE_ADDRESS 0xffc03300 +#define HMDMA1_BASE_ADDRESS 0xffc03340 + + +/* register fields */ + +#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 +#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 +#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 +#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 +#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 +#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 +#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f +#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 + +#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 +#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 +#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 +#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 +#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 +#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 +#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f +#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 + +#define TIMER_ENABLE_TIMEN7 0x0080 +#define TIMER_ENABLE_TIMEN6 0x0040 +#define TIMER_ENABLE_TIMEN5 0x0020 +#define TIMER_ENABLE_TIMEN4 0x0010 +#define TIMER_ENABLE_TIMEN3 0x0008 +#define TIMER_ENABLE_TIMEN2 0x0004 +#define TIMER_ENABLE_TIMEN1 0x0002 +#define TIMER_ENABLE_TIMEN0 0x0001 + +#define TIMER_DISABLE_TIMDIS7 0x0080 +#define TIMER_DISABLE_TIMDIS6 0x0040 +#define TIMER_DISABLE_TIMDIS5 0x0020 +#define TIMER_DISABLE_TIMDIS4 0x0010 +#define TIMER_DISABLE_TIMDIS3 0x0008 +#define TIMER_DISABLE_TIMDIS2 0x0004 +#define TIMER_DISABLE_TIMDIS1 0x0002 +#define TIMER_DISABLE_TIMDIS0 0x0001 + +#define TIMER_STATUS_TRUN7 0x80000000 +#define TIMER_STATUS_TRUN6 0x40000000 +#define TIMER_STATUS_TRUN5 0x20000000 +#define TIMER_STATUS_TRUN4 0x10000000 +#define TIMER_STATUS_TOVF_ERR7 0x00800000 +#define TIMER_STATUS_TOVF_ERR6 0x00400000 +#define TIMER_STATUS_TOVF_ERR5 0x00200000 +#define TIMER_STATUS_TOVF_ERR4 0x00100000 +#define TIMER_STATUS_TIMIL7 0x00080000 +#define TIMER_STATUS_TIMIL6 0x00040000 +#define TIMER_STATUS_TIMIL5 0x00020000 +#define TIMER_STATUS_TIMIL4 0x00010000 +#define TIMER_STATUS_TRUN3 0x00008000 +#define TIMER_STATUS_TRUN2 0x00004000 +#define TIMER_STATUS_TRUN1 0x00002000 +#define TIMER_STATUS_TRUN0 0x00001000 +#define TIMER_STATUS_TOVF_ERR3 0x00000080 +#define TIMER_STATUS_TOVF_ERR2 0x00000040 +#define TIMER_STATUS_TOVF_ERR1 0x00000020 +#define TIMER_STATUS_TOVF_ERR0 0x00000010 +#define TIMER_STATUS_TIMIL3 0x00000008 +#define TIMER_STATUS_TIMIL2 0x00000004 +#define TIMER_STATUS_TIMIL1 0x00000002 +#define TIMER_STATUS_TIMIL0 0x00000001 + +#define PORT_MUX_PGTE 0x0800 +#define PORT_MUX_PGRE 0x0400 +#define PORT_MUX_PGSE 0x0200 +#define PORT_MUX_PFFE 0x0100 +#define PORT_MUX_PFS4E 0x0080 +#define PORT_MUX_PFS5E 0x0040 +#define PORT_MUX_PFS6E 0x0020 +#define PORT_MUX_PFTE 0x0010 +#define PORT_MUX_PFDE 0x0008 +#define PORT_MUX_PJCE_MASK 0x0006 +#define PORT_MUX_PJCE_DR0SEC_DTOSEC 0x0000 +#define PORT_MUX_PJCE_CANRX_CANTX 0x0002 +#define PORT_MUX_PJCE_SPISSEL7 0x0004 +#define PORT_MUX_PJSE 0x0001 + + +/* Core Event Controller vectors */ + +#define CEC_EMULATION_VECTOR 0 +#define CEC_RESET_VECTOR 1 +#define CEC_NMI_VECTOR 2 +#define CEC_EXCEPTIONS_VECTOR 3 +#define CEC_HARDWARE_ERROR_VECTOR 5 +#define CEC_CORE_TIMER_VECTOR 6 +#define CEC_INTERRUPT_BASE_VECTOR 7 +#define CEC_INTERRUPT_COUNT 9 + + +/* System Interrupt Controller vectors */ + +#define SIC_IAR_COUNT 4 + +#define SIC_PLL_WAKEUP_VECTOR 0 +#define SIC_DMA_ERROR_VECTOR 1 +#define SIC_DMAR0_BLOCK_DONE_VECTOR 1 +#define SIC_DMAR1_BLOCK_DONE_VECTOR 1 +#define SIC_DMAR0_OVERFLOW_VECTOR 1 +#define SIC_DMAR1_OVERFLOW_VECTOR 1 +#define SIC_CAN_ERROR_VECTOR 2 +#define SIC_MAC_ERROR_VECTOR 2 +#define SIC_SPORT0_ERROR_VECTOR 2 +#define SIC_SPORT1_ERROR_VECTOR 2 +#define SIC_PPI_ERROR_VECTOR 2 +#define SIC_SPI_ERROR_VECTOR 2 +#define SIC_UART0_ERROR_VECTOR 2 +#define SIC_UART1_ERROR_VECTOR 2 +#define SIC_RTC_VECTOR 3 +#define SIC_DMA0_PPI_VECTOR 4 +#define SIC_DMA3_SPORT0_RX_VECTOR 5 +#define SIC_DMA4_SPORT0_TX_VECTOR 6 +#define SIC_DMA5_SPORT1_RX_VECTOR 7 +#define SIC_DMA5_SPORT1_TX_VECTOR 8 +#define SIC_TWI_VECTOR 9 +#define SIC_DMA7_SPI_VECTOR 10 +#define SIC_DMA8_UART0_RX_VECTOR 11 +#define SIC_DMA9_UART0_TX_VECTOR 12 +#define SIC_DMA10_UART1_RX_VECTOR 13 +#define SIC_DMA11_UART1_TX_VECTOR 14 +#define SIC_CAN_RX_VECTOR 15 +#define SIC_CAN_TX_VECTOR 16 +#define SIC_DMA1_MAC_RX_VECTOR 17 +#define SIC_PORTH_IRQ_A_VECTOR 17 +#define SIC_DMA2_MAC_TX_VECTOR 18 +#define SIC_PORTH_IRQ_B_VECTOR 18 +#define SIC_TIMER0_VECTOR 19 +#define SIC_TIMER1_VECTOR 20 +#define SIC_TIMER2_VECTOR 21 +#define SIC_TIMER3_VECTOR 22 +#define SIC_TIMER4_VECTOR 23 +#define SIC_TIMER5_VECTOR 24 +#define SIC_TIMER6_VECTOR 25 +#define SIC_TIMER7_VECTOR 26 +#define SIC_PORTF_IRQ_A_VECTOR 27 +#define SIC_PORTG_IRQ_A_VECTOR 27 +#define SIC_PORTG_IRQ_B_VECTOR 28 +#define SIC_MDMA0_VECTOR 29 +#define SIC_MDMA1_VECTOR 30 +#define SIC_WATCHDOG_VECTOR 31 +#define SIC_PORTF_IRQ_B_VECTOR 31 + + +#endif /* _bf537_h_ */ diff --git a/bsps/bfin/include/libcpu/cecRegs.h b/bsps/bfin/include/libcpu/cecRegs.h new file mode 100644 index 0000000000..89564c6f70 --- /dev/null +++ b/bsps/bfin/include/libcpu/cecRegs.h @@ -0,0 +1,46 @@ +/* Blackfin Core Event Controller Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _cecRegs_h_ +#define _cecRegs_h_ + +/* register addresses */ +#define CEC_EVT_BASE 0xffe02000 +#define CEC_EVT_COUNT 16 +#define CEC_EVT_PITCH 0x04 +#define CEC_EVT0 0xffe02000 +#define CEC_EVT1 0xffe02004 +#define CEC_EVT2 0xffe02008 +#define CEC_EVT3 0xffe0200c +#define CEC_EVT4 0xffe02010 +#define CEC_EVT5 0xffe02014 +#define CEC_EVT6 0xffe02018 +#define CEC_EVT7 0xffe0201c +#define CEC_EVT8 0xffe02020 +#define CEC_EVT9 0xffe02024 +#define CEC_EVT10 0xffe02028 +#define CEC_EVT11 0xffe0202c +#define CEC_EVT12 0xffe02030 +#define CEC_EVT13 0xffe02034 +#define CEC_EVT14 0xffe02038 +#define CEC_EVT15 0xffe0203c +#define CEC_IMASK 0xffe02104 +#define CEC_IPEND 0xffe02108 +#define CEC_ILAT 0xffe0210c +#define CEC_IPRIO 0xffe02110 + + +/* register fields */ + +#define CEC_IPRIO_IPRIO_MARK_MASK 0x0000000f +#define CEC_IPRIO_IPRIO_MARK_SHIFT 0 + + +#endif /* _cecRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/coreTimerRegs.h b/bsps/bfin/include/libcpu/coreTimerRegs.h new file mode 100644 index 0000000000..c5b257783c --- /dev/null +++ b/bsps/bfin/include/libcpu/coreTimerRegs.h @@ -0,0 +1,29 @@ +/* Blackfin Core Timer Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _coreTimerRegs_h_ +#define _coreTimerRegs_h_ + +/* register addresses */ + +#define TCNTL 0xffe03000 +#define TPERIOD 0xffe03004 +#define TSCALE 0xffe03008 +#define TCOUNT 0xffe0300c + + +/* register fields */ + +#define TCNTL_TINT 0x00000008 +#define TCNTL_TAUTORLD 0x00000004 +#define TCNTL_TMREN 0x00000002 +#define TCNTL_TMPWR 0x00000001 + +#endif /* _coreTimerRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/dmaRegs.h b/bsps/bfin/include/libcpu/dmaRegs.h new file mode 100644 index 0000000000..7c895b7cab --- /dev/null +++ b/bsps/bfin/include/libcpu/dmaRegs.h @@ -0,0 +1,97 @@ +/* Blackfin DMA Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _dmaRegs_h_ +#define _dmaRegs_h_ + + +/* register addresses */ + +#define DMA_NEXT_DESC_PTR_OFFSET 0x0000 +#define DMA_START_ADDR_OFFSET 0x0004 +#define DMA_CONFIG_OFFSET 0x0008 +#define DMA_X_COUNT_OFFSET 0x0010 +#define DMA_X_MODIFY_OFFSET 0x0014 +#define DMA_Y_COUNT_OFFSET 0x0018 +#define DMA_Y_MODIFY_OFFSET 0x001c +#define DMA_CURR_DESC_PTR_OFFSET 0x0020 +#define DMA_CURR_ADDR_OFFSET 0x0024 +#define DMA_IRQ_STATUS_OFFSET 0x0028 +#define DMA_PERIPHERAL_MAP_OFFSET 0x002c +#define DMA_CURR_X_COUNT_OFFSET 0x0030 +#define DMA_CURR_Y_COUNT_OFFSET 0x0038 + +#define HMDMA_CONTROL_OFFSET 0x0000 +#define HMDMA_ECINIT_OFFSET 0x0004 +#define HMDMA_BCINIT_OFFSET 0x0008 +#define HMDMA_ECURGENT_OFFSET 0x000c +#define HMDMA_ECOVERFLOW_OFFSET 0x0010 +#define HMDMA_ECOUNT_OFFSET 0x0014 +#define HMDMA_BCOUNT_OFFSET 0x0018 + + +/* register fields */ + +#define DMA_CONFIG_FLOW_MASK 0x7000 +#define DMA_CONFIG_FLOW_STOP 0x0000 +#define DMA_CONFIG_FLOW_AUTOBUFFER 0x1000 +#define DMA_CONFIG_FLOW_DESC_ARRAY 0x4000 +#define DMA_CONFIG_FLOW_DESC_SMALL 0x6000 +#define DMA_CONFIG_FLOW_DESC_LARGE 0x7000 +#define DMA_CONFIG_NDSIZE_MASK 0x0f00 +#define DMA_CONFIG_NDSIZE_SHIFT 8 +#define DMA_CONFIG_DI_EN 0x0080 +#define DMA_CONFIG_DI_SEL 0x0040 +#define DMA_CONFIG_SYNC 0x0020 +#define DMA_CONFIG_DMA2D 0x0010 +#define DMA_CONFIG_WDSIZE_MASK 0x000c +#define DMA_CONFIG_WDSIZE_8 0x0000 +#define DMA_CONFIG_WDSIZE_16 0x0004 +#define DMA_CONFIG_WDSIZE_32 0x0008 +#define DMA_CONFIG_WNR 0x0002 +#define DMA_CONFIG_DMAEN 0x0001 + +#define DMA_IRQ_STATUS_DMA_RUN 0x0008 +#define DMA_IRQ_STATUS_DFETCH 0x0004 +#define DMA_IRQ_STATUS_DMA_ERR 0x0002 +#define DMA_IRQ_STATUS_DMA_DONE 0x0001 + +#define DMA_PERIPHERAL_MAP_PMAP_MASK 0xf000 +#define DMA_PERIPHERAL_MAP_PMAP_PPI 0x0000 +#define DMA_PERIPHERAL_MAP_PMAP_ETHRX 0x1000 +#define DMA_PERIPHERAL_MAP_PMAP_ETHTX 0x2000 +#define DMA_PERIPHERAL_MAP_PMAP_SPORT0RX 0x3000 +#define DMA_PERIPHERAL_MAP_PMAP_SPORT0TX 0x4000 +#define DMA_PERIPHERAL_MAP_PMAP_SPORT1RX 0x5000 +#define DMA_PERIPHERAL_MAP_PMAP_SPORT1TX 0x6000 +#define DMA_PERIPHERAL_MAP_PMAP_SPI 0x7000 +#define DMA_PERIPHERAL_MAP_PMAP_UART0RX 0x8000 +#define DMA_PERIPHERAL_MAP_PMAP_UART0TX 0x9000 +#define DMA_PERIPHERAL_MAP_PMAP_UART1RX 0xa000 +#define DMA_PERIPHERAL_MAP_PMAP_UART1TX 0xb000 +#define DMA_PERIPHERAL_MAP_CTYPE 0x0040 + +#define HMDMA_CONTROL_BDI 0x8000 +#define HMDMA_CONTROL_OI 0x4000 +#define HMDMA_CONTROL_PS 0x2000 +#define HMDMA_CONTROL_RBC 0x1000 +#define HMDMA_CONTROL_DRQ_MASK 0x0300 +#define HMDMA_CONTROL_DRQ_NONE 0x0000 +#define HMDMA_CONTROL_DRQ_SINGLE 0x0100 +#define HMDMA_CONTROL_DRQ_MULTIPLE 0x0200 +#define HMDMA_CONTROL_DRQ_URGENT_MULTIPLE 0x0300 +#define HMDMA_CONTROL_MBDI 0x0040 +#define HMDMA_CONTROL_BDIE 0x0020 +#define HMDMA_CONTROL_OIE 0x0010 +#define HMDMA_CONTROL_UTE 0x0008 +#define HMDMA_CONTROL_REP 0x0002 +#define HMDMA_CONTROL_HMDMAEN 0x0001 + +#endif /* _dmaRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/ebiuRegs.h b/bsps/bfin/include/libcpu/ebiuRegs.h new file mode 100644 index 0000000000..1a07ff6985 --- /dev/null +++ b/bsps/bfin/include/libcpu/ebiuRegs.h @@ -0,0 +1,133 @@ +/* Blackfin External Peripheral Interface Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _ebiuRegs_h_ +#define _ebiuRegs_h_ + +/* register addresses */ + +#define EBIU_AMGCTL (EBIU_BASE_ADDRESS + 0x0000) +#define EBIU_AMBCTL0 (EBIU_BASE_ADDRESS + 0x0004) +#define EBIU_AMBCTL1 (EBIU_BASE_ADDRESS + 0x0008) +#define EBIU_SDGCTL (EBIU_BASE_ADDRESS + 0x0010) +#define EBIU_SDBCTL (EBIU_BASE_ADDRESS + 0x0014) +#define EBIU_SDRRC (EBIU_BASE_ADDRESS + 0x0018) +#define EBIU_SDSTAT (EBIU_BASE_ADDRESS + 0x001c) + +/* register fields */ + +#define EBIU_AMGCTL_CDPRIO 0x0100 +#define EBIU_AMGCTL_AMBEN_MASK 0x000e +#define EBIU_AMGCTL_AMBEN_SHIFT 1 +#define EBIU_AMGCTL_AMCKEN 0x0001 + +#define EBIU_AMBCTL0_B1WAT_MASK 0xf0000000 +#define EBIU_AMBCTL0_B1WAT_SHIFT 28 +#define EBIU_AMBCTL0_B1RAT_MASK 0x0f000000 +#define EBIU_AMBCTL0_B1RAT_SHIFT 24 +#define EBIU_AMBCTL0_B1HT_MASK 0x00c00000 +#define EBIU_AMBCTL0_B1HT_SHIFT 22 +#define EBIU_AMBCTL0_B1ST_MASK 0x00300000 +#define EBIU_AMBCTL0_B1ST_SHIFT 20 +#define EBIU_AMBCTL0_B1TT_MASK 0x000c0000 +#define EBIU_AMBCTL0_B1TT_SHIFT 18 +#define EBIU_AMBCTL0_B1RDYPOL 0x00020000 +#define EBIU_AMBCTL0_B1RDYEN 0x00010000 +#define EBIU_AMBCTL0_B0WAT_MASK 0x0000f000 +#define EBIU_AMBCTL0_B0WAT_SHIFT 12 +#define EBIU_AMBCTL0_B0RAT_MASK 0x00000f00 +#define EBIU_AMBCTL0_B0RAT_SHIFT 8 +#define EBIU_AMBCTL0_B0HT_MASK 0x000000c0 +#define EBIU_AMBCTL0_B0HT_SHIFT 6 +#define EBIU_AMBCTL0_B0ST_MASK 0x00000030 +#define EBIU_AMBCTL0_B0ST_SHIFT 4 +#define EBIU_AMBCTL0_B0TT_MASK 0x0000000c +#define EBIU_AMBCTL0_B0TT_SHIFT 2 +#define EBIU_AMBCTL0_B0RDYPOL 0x00000002 +#define EBIU_AMBCTL0_B0RDYEN 0x00000001 + +#define EBIU_AMBCTL1_B3WAT_MASK 0xf0000000 +#define EBIU_AMBCTL1_B3WAT_SHIFT 28 +#define EBIU_AMBCTL1_B3RAT_MASK 0x0f000000 +#define EBIU_AMBCTL1_B3RAT_SHIFT 24 +#define EBIU_AMBCTL1_B3HT_MASK 0x00c00000 +#define EBIU_AMBCTL1_B3HT_SHIFT 22 +#define EBIU_AMBCTL1_B3ST_MASK 0x00300000 +#define EBIU_AMBCTL1_B3ST_SHIFT 20 +#define EBIU_AMBCTL1_B3TT_MASK 0x000c0000 +#define EBIU_AMBCTL1_B3TT_SHIFT 18 +#define EBIU_AMBCTL1_B3RDYPOL 0x00020000 +#define EBIU_AMBCTL1_B3RDYEN 0x00010000 +#define EBIU_AMBCTL1_B2WAT_MASK 0x0000f000 +#define EBIU_AMBCTL1_B2WAT_SHIFT 12 +#define EBIU_AMBCTL1_B2RAT_MASK 0x00000f00 +#define EBIU_AMBCTL1_B2RAT_SHIFT 8 +#define EBIU_AMBCTL1_B2HT_MASK 0x000000c0 +#define EBIU_AMBCTL1_B2HT_SHIFT 6 +#define EBIU_AMBCTL1_B2ST_MASK 0x00000030 +#define EBIU_AMBCTL1_B2ST_SHIFT 4 +#define EBIU_AMBCTL1_B2TT_MASK 0x0000000c +#define EBIU_AMBCTL1_B2TT_SHIFT 2 +#define EBIU_AMBCTL1_B2RDYPOL 0x00000002 +#define EBIU_AMBCTL1_B2RDYEN 0x00000001 + +#define EBIU_SDGCTL_CDDBG 0x40000000 +#define EBIU_SDGCTL_TCSR 0x20000000 +#define EBIU_SDGCTL_EMREN 0x10000000 +#define EBIU_SDGCTL_FBBRW 0x04000000 +#define EBIU_SDGCTL_EBUFE 0x02000000 +#define EBIU_SDGCTL_SRFS 0x01000000 +#define EBIU_SDGCTL_PSSE 0x00800000 +#define EBIU_SDGCTL_PSM 0x00400000 +#define EBIU_SDGCTL_PUPSD 0x00200000 +#define EBIU_SDGCTL_TWR_MASK 0x00180000 +#define EBIU_SDGCTL_TWR_SHIFT 19 +#define EBIU_SDGCTL_TRCD_MASK 0x00038000 +#define EBIU_SDGCTL_TRCD_SHIFT 15 +#define EBIU_SDGCTL_TRP_MASK 0x00003800 +#define EBIU_SDGCTL_TRP_SHIFT 11 +#define EBIU_SDGCTL_TRAS_MASK 0x000003c0 +#define EBIU_SDGCTL_TRAS_SHIFT 6 +#define EBIU_SDGCTL_PASR_MASK 0x00000030 +#define EBIU_SDGCTL_PASR_ALL 0x00000000 +#define EBIU_SDGCTL_PASR_0_1 0x00000010 +#define EBIU_SDGCTL_PASR_0 0x00000020 +#define EBIU_SDGCTL_CL_MASK 0x0000000c +#define EBIU_SDGCTL_CL_SHIFT 2 +#define EBIU_SDGCTL_SCTLE 0x00000001 + +#define EBIU_SDBCTL_EBCAW_MASK 0x0030 +#define EBIU_SDBCTL_SHIFT 4 +#define EBIU_SDBCTL_EBCAW_8 0x0000 +#define EBIU_SDBCTL_EBCAW_9 0x0010 +#define EBIU_SDBCTL_EBCAW_10 0x0020 +#define EBIU_SDBCTL_EBCAW_11 0x0030 +#define EBIU_SDBCTL_EBSZ_MASK 0x000e +#define EBIU_SDBCTL_EBSZ_SHIFT 1 +#define EBIU_SDBCTL_EBSZ_16M 0x0000 +#define EBIU_SDBCTL_EBSZ_32M 0x0002 +#define EBIU_SDBCTL_EBSZ_64M 0x0004 +#define EBIU_SDBCTL_EBSZ_128M 0x0006 +#define EBIU_SDBCTL_EBSZ_256M 0x0008 +#define EBIU_SDBCTL_EBSZ_512M 0x000a +#define EBIU_SDBCTL_EBE 0x0001 + +#define EBIU_SDRRC_RDIV_MASK 0x0fff +#define EBIU_SDRRC_RDIV_SHIFT 0 + +#define EBIU_SDSTAT_BGSTAT 0x0020 +#define EBIU_SDSTAT_SDEASE 0x0010 +#define EBIU_SDSTAT_SDRS 0x0008 +#define EBIU_SDSTAT_SDPUA 0x0004 +#define EBIU_SDSTAT_SDSRA 0x0002 +#define EBIU_SDSTAT_SDCI 0x0001 + + +#endif /* _ebiuRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/ethernet.h b/bsps/bfin/include/libcpu/ethernet.h new file mode 100644 index 0000000000..0a8fc0c4b0 --- /dev/null +++ b/bsps/bfin/include/libcpu/ethernet.h @@ -0,0 +1,54 @@ +/* + * RTEMS network driver for Blackfin embedded ethernet controller + * + * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _ethernet_h_ +#define _ethernet_h_ + + +#define BFIN_ETHERNET_DEBUG_NONE 0x0000 +#define BFIN_ETHERNET_DEBUG_ALL 0xFFFF + +#define BFIN_ETHERNET_DEBUG (BFIN_ETHERNET_DEBUG_NONE) + + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef struct { + uint32_t sclk; + void *ethBaseAddress; + void *rxdmaBaseAddress; + void *txdmaBaseAddress; + int rxDescCount; + int txDescCount; + enum {rmii, mii} phyType; + int phyAddr; +} bfin_ethernet_configuration_t; + + +void bfin_ethernet_rxdma_isr(int vector); +void bfin_ethernet_txdma_isr(int vector); +void bfin_ethernet_mac_isr(int vector); + +int bfin_ethernet_driver_attach(struct rtems_bsdnet_ifconfig *config, + int attaching, + bfin_ethernet_configuration_t *chip); + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ethernet_h_ */ + diff --git a/bsps/bfin/include/libcpu/ethernetRegs.h b/bsps/bfin/include/libcpu/ethernetRegs.h new file mode 100644 index 0000000000..7bf85c576b --- /dev/null +++ b/bsps/bfin/include/libcpu/ethernetRegs.h @@ -0,0 +1,419 @@ +/* Blackfin Ethernet Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _ethernetRegs_h_ +#define _ethernetRegs_h_ + +/* register addresses */ + +#define EMAC_OPMODE_OFFSET 0x0000 +#define EMAC_ADDRLO_OFFSET 0x0004 +#define EMAC_ADDRHI_OFFSET 0x0008 +#define EMAC_HASHLO_OFFSET 0x000c +#define EMAC_HASHHI_OFFSET 0x0010 +#define EMAC_STAADD_OFFSET 0x0014 +#define EMAC_STADAT_OFFSET 0x0018 +#define EMAC_FLC_OFFSET 0x001c +#define EMAC_VLAN1_OFFSET 0x0020 +#define EMAC_VLAN2_OFFSET 0x0024 +#define EMAC_WKUP_CTL_OFFSET 0x002c +#define EMAC_WKUP_FFMSK0_OFFSET 0x0030 +#define EMAC_WKUP_FFMSK1_OFFSET 0x0034 +#define EMAC_WKUP_FFMSK2_OFFSET 0x0038 +#define EMAC_WKUP_FFMSK3_OFFSET 0x003c +#define EMAC_WKUP_FFCMD_OFFSET 0x0040 +#define EMAC_WKUP_FFOFF_OFFSET 0x0044 +#define EMAC_WKUP_FFCRC01_OFFSET 0x0048 +#define EMAC_WKUP_FFCRC23_OFFSET 0x004c +#define EMAC_SYSCTL_OFFSET 0x0060 +#define EMAC_SYSTAT_OFFSET 0x0064 +#define EMAC_RX_STAT_OFFSET 0x0068 +#define EMAC_RX_STKY_OFFSET 0x006c +#define EMAC_RX_IRQE_OFFSET 0x0070 +#define EMAC_TX_STAT_OFFSET 0x0074 +#define EMAC_TX_STKY_OFFSET 0x0078 +#define EMAC_TX_IRQE_OFFSET 0x007c +#define EMAC_MMC_CTL_OFFSET 0x0080 +#define EMAC_MMC_RIRQS_OFFSET 0x0084 +#define EMAC_MMC_RIRQE_OFFSET 0x0088 +#define EMAC_MMC_TIRQS_OFFSET 0x008c +#define EMAC_MMC_TIRQE_OFFSET 0x0090 + +#define EMAC_RXC_OK_OFFSET 0x0100 +#define EMAC_RXC_FCS_OFFSET 0x0104 +#define EMAC_RXC_ALIGN_OFFSET 0x0108 +#define EMAC_RXC_OCTET_OFFSET 0x010c +#define EMAC_RXC_DMAOVF_OFFSET 0x0110 +#define EMAC_RXC_UNICST_OFFSET 0x0114 +#define EMAC_RXC_MULTI_OFFSET 0x0118 +#define EMAC_RXC_BROAD_OFFSET 0x011c +#define EMAC_RXC_LNERRI_OFFSET 0x0120 +#define EMAC_RXC_LNERRO_OFFSET 0x0124 +#define EMAC_RXC_LONG_OFFSET 0x0128 +#define EMAC_RXC_MACCTL_OFFSET 0x012c +#define EMAC_RXC_OPCODE_OFFSET 0x0130 +#define EMAC_RXC_PAUSE_OFFSET 0x0134 +#define EMAC_RXC_ALLFRM_OFFSET 0x0138 +#define EMAC_RXC_ALLOCT_OFFSET 0x013c +#define EMAC_RXC_TYPED_OFFSET 0x0140 +#define EMAC_RXC_SHORT_OFFSET 0x0144 +#define EMAC_RXC_EQ64_OFFSET 0x0148 +#define EMAC_RXC_LT128_OFFSET 0x014c +#define EMAC_RXC_LT256_OFFSET 0x0150 +#define EMAC_RXC_LT512_OFFSET 0x0154 +#define EMAC_RXC_LT1024_OFFSET 0x0158 +#define EMAC_RXC_GE1024_OFFSET 0x015c + +#define EMAC_TXC_OK_OFFSET 0x0180 +#define EMAC_TXC_1COL_OFFSET 0x0184 +#define EMAC_TXC_GT1COL_OFFSET 0x0188 +#define EMAC_TXC_OCTET_OFFSET 0x018c +#define EMAC_TXC_DEFER_OFFSET 0x0190 +#define EMAC_TXC_LATECL_OFFSET 0x0194 +#define EMAC_TXC_XS_COL_OFFSET 0x0198 +#define EMAC_TXC_DMAUND_OFFSET 0x019c +#define EMAC_TXC_CRSERR_OFFSET 0x01a0 +#define EMAC_TXC_UNICST_OFFSET 0x01a4 +#define EMAC_TXC_MULTI_OFFSET 0x01a8 +#define EMAC_TXC_BROAD_OFFSET 0x01ac +#define EMAC_TXC_ES_DFR_OFFSET 0x01b0 +#define EMAC_TXC_MACCTL_OFFSET 0x01b4 +#define EMAC_TXC_ALLFRM_OFFSET 0x01b8 +#define EMAC_TXC_ALLOCT_OFFSET 0x01bc +#define EMAC_TXC_EQ64_OFFSET 0x01c0 +#define EMAC_TXC_LT128_OFFSET 0x01c4 +#define EMAC_TXC_LT256_OFFSET 0x01c8 +#define EMAC_TXC_LT512_OFFSET 0x01cc +#define EMAC_TXC_LT1024_OFFSET 0x01d0 +#define EMAC_TXC_GE1024_OFFSET 0x01d4 +#define EMAC_TXC_ABORT_OFFSET 0x01d8 + + +/* register fields */ + +#define EMAC_OPMODE_DRO 0x10000000 +#define EMAC_OPMODE_LB 0x08000000 +#define EMAC_OPMODE_FDMODE 0x04000000 +#define EMAC_OPMODE_RMII_10 0x02000000 +#define EMAC_OPMODE_RMII 0x01000000 +#define EMAC_OPMODE_LCTRE 0x00800000 +#define EMAC_OPMODE_DRTY 0x00400000 +#define EMAC_OPMODE_BOLMT_MASK 0x00300000 +#define EMAC_OPMODE_BOLMT_1023 0x00000000 +#define EMAC_OPMODE_BOLMT_255 0x00100000 +#define EMAC_OPMODE_BOLMT_15 0x00200000 +#define EMAC_OPMODE_BOLMT_1 0x00300000 +#define EMAC_OPMODE_DC 0x00080000 +#define EMAC_OPMODE_DTXCRC 0x00040000 +#define EMAC_OPMODE_DTXPAD 0x00020000 +#define EMAC_OPMODE_TE 0x00010000 +#define EMAC_OPMODE_RAF 0x00001000 +#define EMAC_OPMODE_PSF 0x00000800 +#define EMAC_OPMODE_PBF 0x00000400 +#define EMAC_OPMODE_DBF 0x00000200 +#define EMAC_OPMODE_IFE 0x00000100 +#define EMAC_OPMODE_PR 0x00000080 +#define EMAC_OPMODE_PAM 0x00000040 +#define EMAC_OPMODE_HM 0x00000020 +#define EMAC_OPMODE_HU 0x00000010 +#define EMAC_OPMODE_ASTP 0x00000002 +#define EMAC_OPMODE_RE 0x00000001 + +#define EMAC_STAADD_PHYAD_MASK 0x0000f800 +#define EMAC_STAADD_PHYAD_SHIFT 11 +#define EMAC_STAADD_REGAD_MASK 0x000007c0 +#define EMAC_STAADD_REGAD_SHIFT 6 +#define EMAC_STAADD_STAIE 0x00000008 +#define EMAC_STAADD_STADISPRE 0x00000004 +#define EMAC_STAADD_STAOP 0x00000002 +#define EMAC_STAADD_STABUSY 0x00000001 + +#define EMAC_FLC_FLCPAUSE_MASK 0xffff0000 +#define EMAC_FLC_FLCPAUSE_SHIFT 16 +#define EMAC_FLC_BKPRSEN 0x00000008 +#define EMAC_FLC_PCF 0x00000004 +#define EMAC_FLC_FLCE 0x00000002 +#define EMAC_FLC_FLCBUSY 0x00000001 + +#define EMAC_WKUP_CTL_RWKS_MASK 0x00000f00 +#define EMAC_WKUP_CTL_RWKS_SHIFT 8 +#define EMAC_WKUP_CTL_MPKS 0x00000020 +#define EMAC_WKUP_CTL_GUWKE 0x00000008 +#define EMAC_WKUP_CTL_RWKE 0x00000004 +#define EMAC_WKUP_CTL_MPKE 0x00000002 +#define EMAC_WKUP_CTL_CAPWKFRM 0x00000001 + +#define EMAC_WKUP_FFCMD_3_TYPE 0x08000000 +#define EMAC_WKUP_FFCMD_3_EN 0x01000000 +#define EMAC_WKUP_FFCMD_2_TYPE 0x00080000 +#define EMAC_WKUP_FFCMD_2_EN 0x00010000 +#define EMAC_WKUP_FFCMD_1_TYPE 0x00000800 +#define EMAC_WKUP_FFCMD_1_EN 0x00000100 +#define EMAC_WKUP_FFCMD_0_TYPE 0x00000008 +#define EMAC_WKUP_FFCMD_0_EN 0x00000001 + +#define EMAC_WKUP_FFOFF_3_MASK 0xff000000 +#define EMAC_WKUP_FFOFF_3_SHIFT 24 +#define EMAC_WKUP_FFOFF_2_MASK 0x00ff0000 +#define EMAC_WKUP_FFOFF_2_SHIFT 16 +#define EMAC_WKUP_FFOFF_1_MASK 0x0000ff00 +#define EMAC_WKUP_FFOFF_1_SHIFT 8 +#define EMAC_WKUP_FFOFF_0_MASK 0x000000ff +#define EMAC_WKUP_FFOFF_0_SHIFT 0 + +#define EMAC_WKUP_FFCRC01_1_MASK 0xffff0000 +#define EMAC_WKUP_FFCRC01_1_SHIFT 16 +#define EMAC_WKUP_FFCRC01_0_MASK 0x0000ffff +#define EMAC_WKUP_FFCRC01_0_SHIFT 0 + +#define EMAC_WKUP_FFCRC23_3_MASK 0xffff0000 +#define EMAC_WKUP_FFCRC23_3_SHIFT 16 +#define EMAC_WKUP_FFCRC23_2_MASK 0x0000ffff +#define EMAC_WKUP_FFCRC23_2_SHIFT 0 + +#define EMAC_SYSCTL_MDCDIV_MASK 0x00003f00 +#define EMAC_SYSCTL_MDCDIV_SHIFT 8 +#define EMAC_SYSCTL_TXDWA 0x00000010 +#define EMAC_SYSCTL_RXCKS 0x00000004 +#define EMAC_SYSCTL_RXDWA 0x00000002 +#define EMAC_SYSCTL_PHYIE 0x00000001 + +#define EMAC_SYSTAT_STMDONE 0x00000080 +#define EMAC_SYSTAT_TXDMAERR 0x00000040 +#define EMAC_SYSTAT_RXDMAERR 0x00000020 +#define EMAC_SYSTAT_WAKEDET 0x00000010 +#define EMAC_SYSTAT_TXFSINT 0x00000008 +#define EMAC_SYSTAT_RXFSINT 0x00000004 +#define EMAC_SYSTAT_MMCINT 0x00000002 +#define EMAC_SYSTAT_PHYINT 0x00000001 + +#define EMAC_RX_STAT_RX_ACCEPT 0x80000000 +#define EMAC_RX_STAT_RX_VLAN2 0x40000000 +#define EMAC_RX_STAT_RX_VLAN1 0x20000000 +#define EMAC_RX_STAT_RX_TYPE 0x10000000 +#define EMAC_RX_STAT_RX_UCTL 0x08000000 +#define EMAC_RX_STAT_RX_CTL 0x04000000 +#define EMAC_RX_STAT_RX_BROAD_MULTI_MASK 0x03000000 +#define EMAC_RX_STAT_RX_BROAD_MULTI_ILLEGAL 0x03000000 +#define EMAC_RX_STAT_RX_BROAD_MULTI_BROADCAST 0x02000000 +#define EMAC_RX_STAT_RX_BROAD_MULTI_GROUP 0x01000000 +#define EMAC_RX_STAT_RX_BROAD_MULTI_UNICAST 0x00000000 +#define EMAC_RX_STAT_RX_RANGE 0x00800000 +#define EMAC_RX_STAT_RX_LATE 0x00400000 +#define EMAC_RX_STAT_RX_PHY 0x00200000 +#define EMAC_RX_STAT_RX_DMAO 0x00100000 +#define EMAC_RX_STAT_RX_ADDR 0x00080000 +#define EMAC_RX_STAT_RX_FRAG 0x00040000 +#define EMAC_RX_STAT_RX_LEN 0x00020000 +#define EMAC_RX_STAT_RX_CRC 0x00010000 +#define EMAC_RX_STAT_RX_ALIGN 0x00008000 +#define EMAC_RX_STAT_RX_LONG 0x00004000 +#define EMAC_RX_STAT_RX_OK 0x00002000 +#define EMAC_RX_STAT_RX_COMP 0x00001000 +#define EMAC_RX_STAT_RX_FRLEN_MASK 0x000007ff +#define EMAC_RX_STAT_RX_FRLEN_SHIFT 0 + +#define EMAC_RX_STKY_RX_ACCEPT 0x80000000 +#define EMAC_RX_STKY_RX_VLAN2 0x40000000 +#define EMAC_RX_STKY_RX_VLAN1 0x20000000 +#define EMAC_RX_STKY_RX_TYPE 0x10000000 +#define EMAC_RX_STKY_RX_UCTL 0x08000000 +#define EMAC_RX_STKY_RX_CTL 0x04000000 +#define EMAC_RX_STKY_RX_BROAD 0x02000000 +#define EMAC_RX_STKY_RX_MULTI 0x01000000 +#define EMAC_RX_STKY_RX_RANGE 0x00800000 +#define EMAC_RX_STKY_RX_LATE 0x00400000 +#define EMAC_RX_STKY_RX_PHY 0x00200000 +#define EMAC_RX_STKY_RX_DMAO 0x00100000 +#define EMAC_RX_STKY_RX_ADDR 0x00080000 +#define EMAC_RX_STKY_RX_FRAG 0x00040000 +#define EMAC_RX_STKY_RX_LEN 0x00020000 +#define EMAC_RX_STKY_RX_CRC 0x00010000 +#define EMAC_RX_STKY_RX_ALIGN 0x00008000 +#define EMAC_RX_STKY_RX_LONG 0x00004000 +#define EMAC_RX_STKY_RX_OK 0x00002000 +#define EMAC_RX_STKY_RX_COMP 0x00001000 + +#define EMAC_RX_IRQE_RX_ACCEPT 0x80000000 +#define EMAC_RX_IRQE_RX_VLAN2 0x40000000 +#define EMAC_RX_IRQE_RX_VLAN1 0x20000000 +#define EMAC_RX_IRQE_RX_TYPE 0x10000000 +#define EMAC_RX_IRQE_RX_UCTL 0x08000000 +#define EMAC_RX_IRQE_RX_CTL 0x04000000 +#define EMAC_RX_IRQE_RX_BROAD 0x02000000 +#define EMAC_RX_IRQE_RX_MULTI 0x01000000 +#define EMAC_RX_IRQE_RX_RANGE 0x00800000 +#define EMAC_RX_IRQE_RX_LATE 0x00400000 +#define EMAC_RX_IRQE_RX_PHY 0x00200000 +#define EMAC_RX_IRQE_RX_DMAO 0x00100000 +#define EMAC_RX_IRQE_RX_ADDR 0x00080000 +#define EMAC_RX_IRQE_RX_FRAG 0x00040000 +#define EMAC_RX_IRQE_RX_LEN 0x00020000 +#define EMAC_RX_IRQE_RX_CRC 0x00010000 +#define EMAC_RX_IRQE_RX_ALIGN 0x00008000 +#define EMAC_RX_IRQE_RX_LONG 0x00004000 +#define EMAC_RX_IRQE_RX_OK 0x00002000 +#define EMAC_RX_IRQE_RX_COMP 0x00001000 + +#define EMAC_TX_STAT_TX_FRLEN_MASK 0x07ff0000 +#define EMAC_TX_STAT_TX_FRLEN_SHIFT 16 +#define EMAC_TX_STAT_TX_RETRY 0x00008000 +#define EMAC_TX_STAT_TX_LOSS 0x00004000 +#define EMAC_TX_STAT_TX_CRS 0x00002000 +#define EMAC_TX_STAT_TX_DEFER 0x00001000 +#define EMAC_TX_STAT_TX_CCNT_MASK 0x00000f00 +#define EMAC_TX_STAT_TX_CCNT_SHIFT 8 +#define EMAC_TX_STAT_TX_MULTI_BROAD_MASK 0x000000c0 +#define EMAC_TX_STAT_TX_MULTI_BROAD_ILLEGAL 0x000000c0 +#define EMAC_TX_STAT_TX_MULTI_BROAD_GROUP 0x00000080 +#define EMAC_TX_STAT_TX_MULTI_BROAD_BROADCAST 0x00000040 +#define EMAC_TX_STAT_TX_MULTI_BROAD_UNICAST 0x00000000 +#define EMAC_TX_STAT_TX_EDEFER 0x00000020 +#define EMAC_TX_STAT_TX_DMAU 0x00000010 +#define EMAC_TX_STAT_TX_LATE 0x00000008 +#define EMAC_TX_STAT_TX_ECOLL 0x00000004 +#define EMAC_TX_STAT_TX_OK 0x00000002 +#define EMAC_TX_STAT_TX_COMP 0x00000001 + +#define EMAC_TX_STKY_TX_RETRY 0x00008000 +#define EMAC_TX_STKY_TX_LOSS 0x00004000 +#define EMAC_TX_STKY_TX_CRS 0x00002000 +#define EMAC_TX_STKY_TX_DEFER 0x00001000 +#define EMAC_TX_STKY_TX_CCNT_MASK 0x00000f00 +#define EMAC_TX_STKY_TX_CCNT_SHIFT 8 +#define EMAC_TX_STKY_TX_MULTI 0x00000080 +#define EMAC_TX_STKY_TX_BROAD 0x00000040 +#define EMAC_TX_STKY_TX_EDEFER 0x00000020 +#define EMAC_TX_STKY_TX_DMAU 0x00000010 +#define EMAC_TX_STKY_TX_LATE 0x00000008 +#define EMAC_TX_STAT_TX_ECOLL 0x00000004 +#define EMAC_TX_STAT_TX_OK 0x00000002 +#define EMAC_TX_STAT_TX_COMP 0x00000001 + +#define EMAC_TX_IRQE_TX_RETRY 0x00008000 +#define EMAC_TX_IRQE_TX_LOSS 0x00004000 +#define EMAC_TX_IRQE_TX_CRS 0x00002000 +#define EMAC_TX_IRQE_TX_DEFER 0x00001000 +#define EMAC_TX_IRQE_TX_CCNT_MASK 0x00000f00 +#define EMAC_TX_IRQE_TX_CCNT_SHIFT 8 +#define EMAC_TX_IRQE_TX_MULTI 0x00000080 +#define EMAC_TX_IRQE_TX_BROAD 0x00000040 +#define EMAC_TX_IRQE_TX_EDEFER 0x00000020 +#define EMAC_TX_IRQE_TX_DMAU 0x00000010 +#define EMAC_TX_IRQE_TX_LATE 0x00000008 +#define EMAC_TX_IRQE_TX_ECOLL 0x00000004 +#define EMAC_TX_IRQE_TX_OK 0x00000002 +#define EMAC_TX_IRQE_TX_COMP 0x00000001 + +#define EMAC_MMC_RIRQS_RX_GE1024_CNT 0x00800000 +#define EMAC_MMC_RIRQS_RX_LT1024_CNT 0x00400000 +#define EMAC_MMC_RIRQS_RX_LT512_CNT 0x00200000 +#define EMAC_MMC_RIRQS_RX_LT256_CNT 0x00100000 +#define EMAC_MMC_RIRQS_RX_LT128_CNT 0x00080000 +#define EMAC_MMC_RIRQS_RX_EQ64_CNT 0x00040000 +#define EMAC_MMC_RIRQS_RX_SHORT_CNT 0x00020000 +#define EMAC_MMC_RIRQS_RX_TYPED_CNT 0x00010000 +#define EMAC_MMC_RIRQS_RX_ALLO_CNT 0x00008000 +#define EMAC_MMC_RIRQS_RX_ALLF_CNT 0x00004000 +#define EMAC_MMC_RIRQS_RX_PAUSE_CNT 0x00002000 +#define EMAC_MMC_RIRQS_RX_OPCODE_CNT 0x00001000 +#define EMAC_MMC_RIRQS_RX_MACCTL_CNT 0x00000800 +#define EMAC_MMC_RIRQS_RX_LONG_CNT 0x00000400 +#define EMAC_MMC_RIRQS_RX_ORL_CNT 0x00000200 +#define EMAC_MMC_RIRQS_RX_IRL_CNT 0x00000100 +#define EMAC_MMC_RIRQS_RX_BROAD_CNT 0x00000080 +#define EMAC_MMC_RIRQS_RX_MULTI_CNT 0x00000040 +#define EMAC_MMC_RIRQS_RX_UNI_CNT 0x00000020 +#define EMAC_MMC_RIRQS_RX_LOST_CNT 0x00000010 +#define EMAC_MMC_RIRQS_RX_OCTET_CNT 0x00000008 +#define EMAC_MMC_RIRQS_RX_ALIGN_CNT 0x00000004 +#define EMAC_MMC_RIRQS_RX_FCS_CNT 0x00000002 +#define EMAC_MMC_RIRQS_RX_OK_CNT 0x00000001 + +#define EMAC_MMC_RIRQE_RX_GE1024_CNT 0x00800000 +#define EMAC_MMC_RIRQE_RX_LT1024_CNT 0x00400000 +#define EMAC_MMC_RIRQE_RX_LT512_CNT 0x00200000 +#define EMAC_MMC_RIRQE_RX_LT256_CNT 0x00100000 +#define EMAC_MMC_RIRQE_RX_LT128_CNT 0x00080000 +#define EMAC_MMC_RIRQE_RX_EQ64_CNT 0x00040000 +#define EMAC_MMC_RIRQE_RX_SHORT_CNT 0x00020000 +#define EMAC_MMC_RIRQE_RX_TYPED_CNT 0x00010000 +#define EMAC_MMC_RIRQE_RX_ALLO_CNT 0x00008000 +#define EMAC_MMC_RIRQE_RX_ALLF_CNT 0x00004000 +#define EMAC_MMC_RIRQE_RX_PAUSE_CNT 0x00002000 +#define EMAC_MMC_RIRQE_RX_OPCODE_CNT 0x00001000 +#define EMAC_MMC_RIRQE_RX_MACCTL_CNT 0x00000800 +#define EMAC_MMC_RIRQE_RX_LONG_CNT 0x00000400 +#define EMAC_MMC_RIRQE_RX_ORL_CNT 0x00000200 +#define EMAC_MMC_RIRQE_RX_IRL_CNT 0x00000100 +#define EMAC_MMC_RIRQE_RX_BROAD_CNT 0x00000080 +#define EMAC_MMC_RIRQE_RX_MULTI_CNT 0x00000040 +#define EMAC_MMC_RIRQE_RX_UNI_CNT 0x00000020 +#define EMAC_MMC_RIRQE_RX_LOST_CNT 0x00000010 +#define EMAC_MMC_RIRQE_RX_OCTET_CNT 0x00000008 +#define EMAC_MMC_RIRQE_RX_ALIGN_CNT 0x00000004 +#define EMAC_MMC_RIRQE_RX_FCS_CNT 0x00000002 +#define EMAC_MMC_RIRQE_RX_OK_CNT 0x00000001 + +#define EMAC_MMC_TIRQS_TX_ABORT_CNT 0x00400000 +#define EMAC_MMC_TIRQS_TX_GE1024_CNT 0x00200000 +#define EMAC_MMC_TIRQS_TX_LT1024_CNT 0x00100000 +#define EMAC_MMC_TIRQS_TX_LT512_CNT 0x00080000 +#define EMAC_MMC_TIRQS_TX_LT256_CNT 0x00040000 +#define EMAC_MMC_TIRQS_TX_LT128_CNT 0x00020000 +#define EMAC_MMC_TIRQS_TX_EQ64_CNT 0x00010000 +#define EMAC_MMC_TIRQS_TX_ALLO_CNT 0x00008000 +#define EMAC_MMC_TIRQS_TX_ALLF_CNT 0x00004000 +#define EMAC_MMC_TIRQS_TX_MACCTL_CNT 0x00002000 +#define EMAC_MMC_TIRQS_TX_EXDEF_CNT 0x00001000 +#define EMAC_MMC_TIRQS_TX_BROAD_CNT 0x00000800 +#define EMAC_MMC_TIRQS_TX_MULTI_CNT 0x00000400 +#define EMAC_MMC_TIRQS_TX_UNI_CNT 0x00000200 +#define EMAC_MMC_TIRQS_TX_CRS_CNT 0x00000100 +#define EMAC_MMC_TIRQS_TX_LOST_CNT 0x00000080 +#define EMAC_MMC_TIRQS_TX_ABORTC_CNT 0x00000040 +#define EMAC_MMC_TIRQS_TX_LATE_CNT 0x00000020 +#define EMAC_MMC_TIRQS_TX_DEFER_CNT 0x00000010 +#define EMAC_MMC_TIRQS_TX_OCTET_CNT 0x00000008 +#define EMAC_MMC_TIRQS_TX_MCOLL_CNT 0x00000004 +#define EMAC_MMC_TIRQS_TX_SCOLL_CNT 0x00000002 +#define EMAC_MMC_TIRQS_TX_OK_CNT 0x00000001 + +#define EMAC_MMC_TIRQE_TX_ABORT_CNT 0x00400000 +#define EMAC_MMC_TIRQE_TX_GE1024_CNT 0x00200000 +#define EMAC_MMC_TIRQE_TX_LT1024_CNT 0x00100000 +#define EMAC_MMC_TIRQE_TX_LT512_CNT 0x00080000 +#define EMAC_MMC_TIRQE_TX_LT256_CNT 0x00040000 +#define EMAC_MMC_TIRQE_TX_LT128_CNT 0x00020000 +#define EMAC_MMC_TIRQE_TX_EQ64_CNT 0x00010000 +#define EMAC_MMC_TIRQE_TX_ALLO_CNT 0x00008000 +#define EMAC_MMC_TIRQE_TX_ALLF_CNT 0x00004000 +#define EMAC_MMC_TIRQE_TX_MACCTL_CNT 0x00002000 +#define EMAC_MMC_TIRQE_TX_EXDEF_CNT 0x00001000 +#define EMAC_MMC_TIRQE_TX_BROAD_CNT 0x00000800 +#define EMAC_MMC_TIRQE_TX_MULTI_CNT 0x00000400 +#define EMAC_MMC_TIRQE_TX_UNI_CNT 0x00000200 +#define EMAC_MMC_TIRQE_TX_CRS_CNT 0x00000100 +#define EMAC_MMC_TIRQE_TX_LOST_CNT 0x00000080 +#define EMAC_MMC_TIRQE_TX_ABORTC_CNT 0x00000040 +#define EMAC_MMC_TIRQE_TX_LATE_CNT 0x00000020 +#define EMAC_MMC_TIRQE_TX_DEFER_CNT 0x00000010 +#define EMAC_MMC_TIRQE_TX_OCTET_CNT 0x00000008 +#define EMAC_MMC_TIRQE_TX_MCOLL_CNT 0x00000004 +#define EMAC_MMC_TIRQE_TX_SCOLL_CNT 0x00000002 +#define EMAC_MMC_TIRQE_TX_OK_CNT 0x00000001 + +#define EMAC_MMC_CTL_MMCE 0x00000008 +#define EMAC_MMC_CTL_CCOR 0x00000004 +#define EMAC_MMC_CTL_CROLL 0x00000002 +#define EMAC_MMC_CTL_RSTC 0x00000001 + + +#endif /* _ethernetRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/gpioRegs.h b/bsps/bfin/include/libcpu/gpioRegs.h new file mode 100644 index 0000000000..02862916e1 --- /dev/null +++ b/bsps/bfin/include/libcpu/gpioRegs.h @@ -0,0 +1,36 @@ +/* Blackfin GPIO Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _gpioRegs_h_ +#define _gpioRegs_h_ + + +/* register addresses */ + +#define PORTIO_OFFSET 0x0000 +#define PORTIO_CLEAR_OFFSET 0x0004 +#define PORTIO_SET_OFFSET 0x0008 +#define PORTIO_TOGGLE_OFFSET 0x000c +#define PORTIO_MASKA_OFFSET 0x0010 +#define PORTIO_MASKA_CLEAR_OFFSET 0x0014 +#define PORTIO_MASKA_SET_OFFSET 0x0018 +#define PORTIO_MASKA_TOGGLE_OFFSET 0x001c +#define PORTIO_MASKB_OFFSET 0x0020 +#define PORTIO_MASKB_CLEAR_OFFSET 0x0024 +#define PORTIO_MASKB_SET_OFFSET 0x0028 +#define PORTIO_MASKB_TOGGLE_OFFSET 0x002c +#define PORTIO_DIR_OFFSET 0x0030 +#define PORTIO_POLAR_OFFSET 0x0034 +#define PORTIO_EDGE_OFFSET 0x0038 +#define PORTIO_BOTH_OFFSET 0x003c +#define PORTIO_INEN_OFFSET 0x0040 + + +#endif /* _gpioRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/interrupt.h b/bsps/bfin/include/libcpu/interrupt.h new file mode 100644 index 0000000000..2c6b538bde --- /dev/null +++ b/bsps/bfin/include/libcpu/interrupt.h @@ -0,0 +1,80 @@ +/* + * RTEMS support for Blackfin interrupt controller + * + * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _interrupt_h_ +#define _interrupt_h_ + +/* Some rules for using this module: + + SIC_IARx registers must not be changed after calling + bfin_interrupt_init(). + + The bfin_isr structures must stick around for as long as the isr is + registered. + + For any interrupt source (SIC bit) that could be shared, it is only + safe to disable an ISR through this module if the ultimate source is + also disabled (the ultimate source must be disabled prior to disabling + it through this module, and must remain disabled until after enabling + it through this module). + + For any source that is shared with modules that cannot be disabled, + give careful thought to the control of those interrupts. + bfin_interrupt_enable_all() or bfin_interrupt_enable_global() can + be used to help solve the problems caused by that. + + + Note that this module does not provide prioritization. It is assumed + that the priorities afforded by the CEC are sufficient. If finer + grained priority control is required then this wlll need to be + redesigned. +*/ + + +#ifdef __cplusplus +extern "C" { +#endif + +/* source is the source to the SIC (the bit number in SIC_ISR). isr is + the function that will be called when the interrupt is active. */ +typedef struct bfin_isr_s { + int source; + void (*isr)(int source); + /* the following are for internal use only */ + uint32_t mask; + int vector; + struct bfin_isr_s *next; +} bfin_isr_t; + +/* If non-default mapping is desired, the BSP should set the SIC_IARx + registers prior to calling this. */ +void bfin_interrupt_init(void); + +/* ISR starts out disabled */ +void bfin_interrupt_register(bfin_isr_t *isr); +void bfin_interrupt_unregister(bfin_isr_t *isr); + +/* enable/disable specific ISR */ +void bfin_interrupt_enable(bfin_isr_t *isr, bool enable); + +/* atomically enable/disable all ISRs attached to specified source */ +void bfin_interrupt_enable_all(int source, bool enable); + +/* disable a source independently of the individual ISR enables (starts + out all enabled) */ +void bfin_interrupt_enable_global(int source, bool enable); + +#ifdef __cplusplus +} +#endif + +#endif /* _interrupt_h_ */ + diff --git a/bsps/bfin/include/libcpu/memoryRegs.h b/bsps/bfin/include/libcpu/memoryRegs.h new file mode 100644 index 0000000000..130235e3d1 --- /dev/null +++ b/bsps/bfin/include/libcpu/memoryRegs.h @@ -0,0 +1,58 @@ +/* Blackfin Memory Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _memoryRegs_h_ +#define _memoryRegs_h_ + +/* register addresses */ +#define DMEM_CONTROL 0xffe00004 +#define DTEST_COMMAND 0xffe00300 +#define DTEST_DATA0 0xffe00400 +#define DTEST_DATA1 0xffe00404 + +#define IMEM_CONTROL 0xffe01004 + + +/* register fields */ +#define DMEM_CONTROL_PORT_PREF1 0x00002000 +#define DMEM_CONTROL_PORT_PREF0 0x00001000 +#define DMEM_CONTROL_DCBS 0x00000010 +#define DMEM_CONTROL_DMC_MASK 0x0000000c +#define DMEM_CONTROL_DMC_SHIFT 2 +#define DMEM_CONTROL_ENDCPLB 0x00000002 + +#define DTEST_COMMAND_ACCESS_WAY1 0x02000000 +#define DTEST_COMMAND_ACCESS_INSTRUCTION 0x01000000 +#define DTEST_COMMAND_ACCESS_BANKB 0x00800000 +#define DTEST_COMMAND_SRAM_ADDR_13_12_MASK 0x00030000 +#define DTEST_COMMAND_SRAM_ADDR_13_12_SHIFT 16 +#define DTEST_COMMAND_DATA_CACHE_SELECT 0x00004000 +#define DTEST_COMMAND_SET_INDEX_MASK 0x000007e0 +#define DTEST_COMMAND_SET_INDEX_SHIFT 5 +#define DTEST_COMMAND_DOUBLE_WORD_INDEX_MASK 0x00000018 +#define DTEST_COMMAND_DOUBLE_WORD_INDEX_SHIFT 3 +#define DTEST_COMMAND_ACCESS_DATA_ARRAY 0x00000004 +#define DTEST_COMMAND_WRITE_ACCESS 0x00000002 + +#define DTEST_DATA0_TAG_19_2_MASK 0xffffc000 +#define DTEST_DATA0_TAG_19_2_SHIFT 14 +#define DTEST_DATA0_TAG 0x00000800 +#define DTEST_DATA0_LRU 0x00000004 +#define DTEST_DATA0_DIRTY 0x00000002 +#define DTEST_DATA0_VALID 0x00000001 + +#define IMEM_CONTROL_LRUPRIORST 0x00002000 +#define IMEM_CONTROL_ILOC_MASK 0x00000078 +#define IMEM_CONTROL_ILOC_SHIFT 3 +#define IMEM_CONTROL_IMC 0x00000004 +#define IMEM_CONTROL_ENICPLB 0x00000002 + + +#endif /* _memoryRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/mmu.h b/bsps/bfin/include/libcpu/mmu.h new file mode 100644 index 0000000000..d6e2ea58a9 --- /dev/null +++ b/bsps/bfin/include/libcpu/mmu.h @@ -0,0 +1,73 @@ +/* Blackfin MMU Support + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + + +/* NOTE: this currently only implements a static table. It should be made + to handle more regions than fit in the CPLBs, with an exception handler + to do replacements as needed. This would of course require great care + to insure any storage required by the exception handler, including any + stack space, the exception handler itself, and the region descriptors + it needs to update the CPLBs, are in regions that will never be + replaced. */ + +#ifndef _mmu_h_ +#define _mmu_h_ + +#include + + +#define INSTR_NOCACHE (ICPLB_DATA_CPLB_USER_RD | \ + ICPLB_DATA_CPLB_VALID) + +#define INSTR_CACHEABLE (ICPLB_DATA_CPLB_L1_CHBL | \ + ICPLB_DATA_CPLB_USER_RD | \ + ICPLB_DATA_CPLB_VALID) + +#define DATA_NOCACHE (DCPLB_DATA_CPLB_DIRTY | \ + DCPLB_DATA_CPLB_SUPV_WR | \ + DCPLB_DATA_CPLB_USER_WR | \ + DCPLB_DATA_CPLB_USER_RD | \ + DCPLB_DATA_CPLB_VALID) + +#define DATA_WRITEBACK (DCPLB_DATA_CPLB_L1_AOW | \ + DCPLB_DATA_CPLB_L1_CHBL | \ + DCPLB_DATA_CPLB_DIRTY | \ + DCPLB_DATA_CPLB_SUPV_WR | \ + DCPLB_DATA_CPLB_USER_WR | \ + DCPLB_DATA_CPLB_USER_RD | \ + DCPLB_DATA_CPLB_VALID) + + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef struct { + struct { + void *address; + uint32_t flags; + } instruction[ICPLB_COUNT]; + struct { + void *address; + uint32_t flags; + } data[DCPLB_COUNT]; +} bfin_mmu_config_t; + + +void bfin_mmu_init(bfin_mmu_config_t *config); + + +#ifdef __cplusplus +} +#endif + +#endif /* _mmu_h_ */ + diff --git a/bsps/bfin/include/libcpu/mmuRegs.h b/bsps/bfin/include/libcpu/mmuRegs.h new file mode 100644 index 0000000000..271ef4dcf5 --- /dev/null +++ b/bsps/bfin/include/libcpu/mmuRegs.h @@ -0,0 +1,54 @@ +/* Blackfin MMU Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _mmuRegs_h_ +#define _mmuRegs_h_ + +/* register addresses */ +#define DCPLB_ADDR0 0xffe00100 +#define DCPLB_DATA0 0xffe00200 +#define DCPLB_COUNT 16 +#define DCPLB_ADDR_PITCH 4 +#define DCPLB_DATA_PITCH 4 +#define ICPLB_ADDR0 0xffe01100 +#define ICPLB_DATA0 0xffe01200 +#define ICPLB_COUNT 16 +#define ICPLB_ADDR_PITCH 4 +#define ICPLB_DATA_PITCH 4 + + +/* register fields */ +#define DCPLB_DATA_PAGE_SIZE_MASK 0x00030000 +#define DCPLB_DATA_PAGE_SIZE_1KB 0x00000000 +#define DCPLB_DATA_PAGE_SIZE_4KB 0x00010000 +#define DCPLB_DATA_PAGE_SIZE_1MB 0x00020000 +#define DCPLB_DATA_PAGE_SIZE_4MB 0x00030000 +#define DCPLB_DATA_CPLB_L1_AOW 0x00008000 +#define DCPLB_DATA_CPLB_WT 0x00004000 +#define DCPLB_DATA_CPLB_L1_CHBL 0x00001000 +#define DCPLB_DATA_CPLB_DIRTY 0x00000080 +#define DCPLB_DATA_CPLB_SUPV_WR 0x00000010 +#define DCPLB_DATA_CPLB_USER_WR 0x00000008 +#define DCPLB_DATA_CPLB_USER_RD 0x00000004 +#define DCPLB_DATA_CPLB_LOCK 0x00000002 +#define DCPLB_DATA_CPLB_VALID 0x00000001 + +#define ICPLB_DATA_PAGE_SIZE_MASK 0x00030000 +#define ICPLB_DATA_PAGE_SIZE_1KB 0x00000000 +#define ICPLB_DATA_PAGE_SIZE_4KB 0x00010000 +#define ICPLB_DATA_PAGE_SIZE_1MB 0x00020000 +#define ICPLB_DATA_PAGE_SIZE_4MB 0x00030000 +#define ICPLB_DATA_CPLB_L1_CHBL 0x00001000 +#define ICPLB_DATA_CPLB_LRUPRIO 0x00000100 +#define ICPLB_DATA_CPLB_USER_RD 0x00000004 +#define ICPLB_DATA_CPLB_LOCK 0x00000002 +#define ICPLB_DATA_CPLB_VALID 0x00000001 + +#endif /* _mmuRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/ppiRegs.h b/bsps/bfin/include/libcpu/ppiRegs.h new file mode 100644 index 0000000000..0ff301aefc --- /dev/null +++ b/bsps/bfin/include/libcpu/ppiRegs.h @@ -0,0 +1,58 @@ +/* Blackfin Parallel Peripheral Interface Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _ppiRegs_h_ +#define _ppiRegs_h_ + + +/* register addresses */ + +#define PPI_CONTROL_OFFSET 0x0000 +#define PPI_STATUS_OFFSET 0x0004 +#define PPI_COUNT_OFFSET 0x0008 +#define PPI_DELAY_OFFSET 0x000c +#define PPI_FRAME_OFFSET 0x0010 + + +/* register fields */ + +#define PPI_CONTROL_POLS 0x8000 +#define PPI_CONTROL_POLC 0x4000 +#define PPI_CONTROL_DLEN_MASK 0x3800 +#define PPI_CONTROL_DLEN_8 0x0000 +#define PPI_CONTROL_DLEN_10 0x0800 +#define PPI_CONTROL_DLEN_11 0x1000 +#define PPI_CONTROL_DLEN_12 0x1800 +#define PPI_CONTROL_DLEN_13 0x2000 +#define PPI_CONTROL_DLEN_14 0x2800 +#define PPI_CONTROL_DLEN_15 0x3000 +#define PPI_CONTROL_DLEN_16 0x3800 +#define PPI_CONTROL_SKIP_EO 0x0400 +#define PPI_CONTROL_SKIP_EN 0x0200 +#define PPI_CONTROL_PACK_EN 0x0080 +#define PPI_CONTROL_FLD_SEL 0x0040 +#define PPI_CONTROL_PORT_CFG_MASK 0x0030 +#define PPI_CONTROL_PORT_CFG_SHIFT 4 +#define PPI_CONTROL_XFR_TYPE_MASK 0x000c +#define PPI_CONTROL_XFR_TYPE_SHIFT 2 +#define PPI_CONTROL_PORT_DIR 0x0002 +#define PPI_CONTROL_PORT_EN 0x0001 + +#define PPI_STATUS_ERR_NCOR 0x8000 +#define PPI_STATUS_ERR_DET 0x4000 +#define PPI_STATUS_UNDR 0x2000 +#define PPI_STATUS_OVR 0x1000 +#define PPI_STATUS_FT_ERR 0x0800 +#define PPI_STATUS_FLD 0x0400 +#define PPI_STATUS_LT_ERR_UNDR 0x0200 +#define PPI_STATUS_LT_ERR_OVR 0x0100 + + +#endif /* _ppiRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/rtcRegs.h b/bsps/bfin/include/libcpu/rtcRegs.h new file mode 100644 index 0000000000..09245c2b91 --- /dev/null +++ b/bsps/bfin/include/libcpu/rtcRegs.h @@ -0,0 +1,65 @@ +/* Blackfin RTC Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _rtcRegs_h_ +#define _rtcRegs_h_ + +/* register addresses */ + +#define RTC_STAT (RTC_BASE_ADDRESS + 0x0000) +#define RTC_ICTL (RTC_BASE_ADDRESS + 0x0004) +#define RTC_ISTAT (RTC_BASE_ADDRESS + 0x0008) +#define RTC_SWCNT (RTC_BASE_ADDRESS + 0x000c) +#define RTC_ALARM (RTC_BASE_ADDRESS + 0x0010) +#define RTC_PREN (RTC_BASE_ADDRESS + 0x0014) + + +/* register fields */ + +#define RTC_STAT_DAYS_MASK 0xfffe0000 +#define RTC_STAT_DAYS_SHIFT 17 +#define RTC_STAT_HOURS_MASK 0x0001f000 +#define RTC_STAT_HOURS_SHIFT 12 +#define RTC_STAT_MINUTES_MASK 0x00000fc0 +#define RTC_STAT_MINUTES_SHIFT 6 +#define RTC_STAT_SECONDS_MASK 0x0000003f +#define RTC_STAT_SECONDS_SHIFT 0 + +#define RTC_ICTL_WCIE 0x8000 +#define RTC_ICTL_DAIE 0x0040 +#define RTC_ICTL_24HIE 0x0020 +#define RTC_ICTL_HIE 0x0010 +#define RTC_ICTL_MIE 0x0008 +#define RTC_ICTL_SIE 0x0004 +#define RTC_ICTL_AIE 0x0002 +#define RTC_ICTL_SWIE 0x0001 + +#define RTC_ISTAT_WC 0x8000 +#define RTC_ISTAT_WP 0x4000 +#define RTC_ISTAT_DAEF 0x0040 +#define RTC_ISTAT_24HE 0x0020 +#define RTC_ISTAT_HEF 0x0010 +#define RTC_ISTAT_MEF 0x0008 +#define RTC_ISTAT_SEF 0x0004 +#define RTC_ISTAT_AEF 0x0002 +#define RTC_ISTAT_SWEF 0x0001 + +#define RTC_ALARM_DAYS_MASK 0xfff70000 +#define RTC_ALARM_DAYS_SHIFT 17 +#define RTC_ALARM_HOURS_MASK 0x0001f000 +#define RTC_ALARM_HOURS_SHIFT 12 +#define RTC_ALARM_MINUTES_MASK 0x00000fc0 +#define RTC_ALARM_MINUTES_SHIFT 10 +#define RTC_ALARM_SECONDS_MASK 0x0000003f +#define RTC_ALARM_SECONDS_SHIFT 0 + +#define RTC_PREN_PREN 0x0001 + +#endif /* _rtcRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/sicRegs.h b/bsps/bfin/include/libcpu/sicRegs.h new file mode 100644 index 0000000000..79fdd0d77c --- /dev/null +++ b/bsps/bfin/include/libcpu/sicRegs.h @@ -0,0 +1,43 @@ +/* Blackfin System Interrupt Controller Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _sicRegs_h_ +#define _sicRegs_h_ + +/* register addresses */ + +#define SIC_IMASK (SIC_BASE_ADDRESS + 0x000c) +#define SIC_IMASK_PITCH (0x40) + +#define SIC_ISR (SIC_BASE_ADDRESS + 0x0020) +#define SIC_ISR_PITCH (0x40) + +#define SIC_IAR_BASE_ADDRESS (SIC_BASE_ADDRESS + 0x0010) +#define SIC_IAR_PITCH 0x04 + +#define SIC_IAR0 (SIC_BASE_ADDRESS + 0x0010) +#if SIC_IAR_COUNT > 1 +#define SIC_IAR1 (SIC_BASE_ADDRESS + 0x0014) +#endif +#if SIC_IAR_COUNT > 2 +#define SIC_IAR2 (SIC_BASE_ADDRESS + 0x0018) +#endif +#if SIC_IAR_COUNT > 3 +#define SIC_IAR3 (SIC_BASE_ADDRESS + 0x001c) +#endif + +#define SIC_IWR (SIC_BASE_ADDRESS + 0x0024) + + +/* register fields */ + + + +#endif /* _sicRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/spi.h b/bsps/bfin/include/libcpu/spi.h new file mode 100644 index 0000000000..db8bfaa612 --- /dev/null +++ b/bsps/bfin/include/libcpu/spi.h @@ -0,0 +1,53 @@ +/* + * RTEMS driver for Blackfin SPI + * + * COPYRIGHT (c) 2010 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _spi_h +#define _spi_h + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + void *base; + /* remaining entries are for internal use */ + rtems_id sem; + int bytes_per_word; + uint16_t idle_pattern; + uint8_t *rd_ptr; + const uint8_t *wr_ptr; + int len; +} bfin_spi_state_t; + +typedef struct { + rtems_libi2c_bus_t bus; + bfin_spi_state_t p; +} bfin_spi_bus_t; + + +void bfin_spi_isr(int v); + +rtems_status_code bfin_spi_init(rtems_libi2c_bus_t *bus); + +rtems_status_code bfin_spi_send_start(rtems_libi2c_bus_t *bus); + +int bfin_spi_read_bytes(rtems_libi2c_bus_t *bus, unsigned char *buf, int len); + +int bfin_spi_write_bytes(rtems_libi2c_bus_t *bus, unsigned char *buf, int len); + +int bfin_spi_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg); + +#ifdef __cplusplus +} +#endif + + +#endif /* _spi_h */ diff --git a/bsps/bfin/include/libcpu/spiRegs.h b/bsps/bfin/include/libcpu/spiRegs.h new file mode 100644 index 0000000000..dcf792bb69 --- /dev/null +++ b/bsps/bfin/include/libcpu/spiRegs.h @@ -0,0 +1,69 @@ +/* Blackfin SPI Registers + * + * Copyright (c) 2010 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _spiRegs_h_ +#define _spiRegs_h_ + + +/* register addresses */ + +#define SPI_CTL_OFFSET 0x0000 +#define SPI_FLG_OFFSET 0x0004 +#define SPI_STAT_OFFSET 0x0008 +#define SPI_TDBR_OFFSET 0x000c +#define SPI_RDBR_OFFSET 0x0010 +#define SPI_BAUD_OFFSET 0x0014 +#define SPI_SHADOW_OFFSET 0x0018 + + +/* register fields */ + +#define SPI_CTL_SPE 0x4000 +#define SPI_CTL_WOM 0x2000 +#define SPI_CTL_MSTR 0x1000 +#define SPI_CTL_CPOL 0x0800 +#define SPI_CTL_CPHA 0x0400 +#define SPI_CTL_LSBF 0x0200 +#define SPI_CTL_SIZE 0x0100 +#define SPI_CTL_EMISO 0x0020 +#define SPI_CTL_PSSE 0x0010 +#define SPI_CTL_GM 0x0008 +#define SPI_CTL_SZ 0x0004 +#define SPI_CTL_TIMOD_MASK 0x0003 +#define SPI_CTL_TIMOD_RDBR 0x0000 +#define SPI_CTL_TIMOD_TDBR 0x0001 +#define SPI_CTL_TIMOD_DMA_RDBR 0x0002 +#define SPI_CTL_TIMOD_DMA_TDBR 0x0003 + +#define SPI_FLG_FLG7 0x8000 +#define SPI_FLG_FLG6 0x4000 +#define SPI_FLG_FLG5 0x2000 +#define SPI_FLG_FLG4 0x1000 +#define SPI_FLG_FLG3 0x0800 +#define SPI_FLG_FLG2 0x0400 +#define SPI_FLG_FLG1 0x0200 +#define SPI_FLG_FLS7 0x0080 +#define SPI_FLG_FLS6 0x0040 +#define SPI_FLG_FLS5 0x0020 +#define SPI_FLG_FLS4 0x0010 +#define SPI_FLG_FLS3 0x0008 +#define SPI_FLG_FLS2 0x0004 +#define SPI_FLG_FLS1 0x0002 + +#define SPI_STAT_TXCOL 0x0040 +#define SPI_STAT_RXS 0x0020 +#define SPI_STAT_RBSY 0x0010 +#define SPI_STAT_TXS 0x0008 +#define SPI_STAT_TXE 0x0004 +#define SPI_STAT_MODF 0x0002 +#define SPI_STAT_SPIF 0x0001 + + +#endif /* _spiRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/sport.h b/bsps/bfin/include/libcpu/sport.h new file mode 100644 index 0000000000..6ed481b593 --- /dev/null +++ b/bsps/bfin/include/libcpu/sport.h @@ -0,0 +1,2 @@ +/* placeholder */ + diff --git a/bsps/bfin/include/libcpu/sportRegs.h b/bsps/bfin/include/libcpu/sportRegs.h new file mode 100644 index 0000000000..f9f263b024 --- /dev/null +++ b/bsps/bfin/include/libcpu/sportRegs.h @@ -0,0 +1,111 @@ +/* Blackfin SPORT Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _sportRegs_h_ +#define _sportRegs_h_ + + +/* register addresses */ + +#define SPORT_TCR1_OFFSET 0x0000 +#define SPORT_TCR2_OFFSET 0x0004 +#define SPORT_TCLKDIV_OFFSET 0x0008 +#define SPORT_TFSDIV_OFFSET 0x000c +#define SPORT_TX_OFFSET 0x0010 +#define SPORT_RX_OFFSET 0x0018 +#define SPORT_RCR1_OFFSET 0x0020 +#define SPORT_RCR2_OFFSET 0x0024 +#define SPORT_RCLKDIV_OFFSET 0x0028 +#define SPORT_RFSDIV_OFFSET 0x002c +#define SPORT_STAT_OFFSET 0x0030 +#define SPORT_CHNL_OFFSET 0x0034 +#define SPORT_MCMC1_OFFSET 0x0038 +#define SPORT_MCMC2_OFFSET 0x003c +#define SPORT_MTCS0_OFFSET 0x0040 +#define SPORT_MTCS1_OFFSET 0x0044 +#define SPORT_MTCS2_OFFSET 0x0048 +#define SPORT_MTCS3_OFFSET 0x004c +#define SPORT_MRCS0_OFFSET 0x0050 +#define SPORT_MRCS1_OFFSET 0x0054 +#define SPORT_MRCS2_OFFSET 0x0058 +#define SPORT_MRCS3_OFFSET 0x005c + + +/* register fields */ + +#define SPORT_TCR1_TCKFE 0x4000 +#define SPORT_TCR1_LATFS 0x2000 +#define SPORT_TCR1_LTFS 0x1000 +#define SPORT_TCR1_DITFS 0x0800 +#define SPORT_TCR1_TFSR 0x0400 +#define SPORT_TCR1_ITFS 0x0200 +#define SPORT_TCR1_TLSBIT 0x0010 +#define SPORT_TCR1_TDTYPE_MASK 0x000c +#define SPORT_TCR1_TDTYPE_NORMAL 0x0000 +#define SPORT_TCR1_TDTYPE_ULAW 0x0008 +#define SPORT_TCR1_TDTYPE_ALAW 0x000c +#define SPORT_TCR1_ITCLK 0x0002 +#define SPORT_TCR1_TSPEN 0x0001 + +#define SPORT_TCR2_TRFST 0x0400 +#define SPORT_TCR2_TSFSE 0x0200 +#define SPORT_TCR2_TXSE 0x0100 +#define SPORT_TCR2_SLEN_MASK 0x001f +#define SPORT_TCR2_SLEN_SHIFT 0 + +#define SPORT_RCR1_RCKFE 0x4000 +#define SPORT_RCR1_LARFS 0x2000 +#define SPORT_RCR1_LRFS 0x1000 +#define SPORT_RCR1_RFSR 0x0400 +#define SPORT_RCR1_IRFS 0x0200 +#define SPORT_RCR1_RLSBIT 0x0010 +#define SPORT_RCR1_RDTYPE_MASK 0x000c +#define SPORT_RCR1_RDTYPE_ZEROFILL 0x0000 +#define SPORT_RCR1_RDTYPE_SIGNEXTEND 0x0004 +#define SPORT_RCR1_RDTYPE_ULAW 0x0008 +#define SPORT_RCR1_RDTYPE_ALAW 0x000c +#define SPORT_RCR1_IRCLK 0x0002 +#define SPORT_RCR1_RSPEN 0x0001 + +#define SPORT_RCR2_RRFST 0x0400 +#define SPORT_RCR2_RSFSE 0x0200 +#define SPORT_RCR2_RXSE 0x0100 +#define SPORT_RCR2_SLEN_MASK 0x001f +#define SPORT_RCR2_SLEN_SHIFT 0 + +#define SPORT_STAT_TXHRE 0x0040 +#define SPORT_STAT_TOVF 0x0020 +#define SPORT_STAT_TUVF 0x0010 +#define SPORT_STAT_TXF 0x0008 +#define SPORT_STAT_ROVF 0x0004 +#define SPORT_STAT_RUVF 0x0002 +#define SPORT_STAT_RXNE 0x0001 + +#define SPORT_CHNL_CHNL_MASK 0x03ff +#define SPORT_CHNL_CHNL_SHIFT 0 + +#define SPORT_MCMC1_WSIZE_MASK 0xf000 +#define SPORT_MCMC1_WSIZE_SHIFT 12 +#define SPORT_MCMC1_WOFF_MASK 0x03ff +#define SPORT_MCMC1_WOFF_SHIFT 0 + +#define SPORT_MCMC2_MFD_MASK 0xf000 +#define SPORT_MCMC2_MFD_SHIFT 12 +#define SPORT_MCMC2_FSDR 0x0080 +#define SPORT_MCMC2_MCMEN 0x0010 +#define SPORT_MCMC2_MCDRXPE 0x0008 +#define SPORT_MCMC2_MCDTXPE 0x0004 +#define SPORT_MCMC2_MCCRM_MASK 0x0003 +#define SPORT_MCMC2_MCCRM_BYPASS 0x0000 +#define SPORT_MCMC2_MCCRM_2_4 0x0002 +#define SPORT_MCMC2_MCCRM_8_16 0x0003 + + +#endif /* _sportRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/timerRegs.h b/bsps/bfin/include/libcpu/timerRegs.h new file mode 100644 index 0000000000..b66bae3339 --- /dev/null +++ b/bsps/bfin/include/libcpu/timerRegs.h @@ -0,0 +1,45 @@ +/* Blackfin General Purpose Timer Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _timerRegs_h_ +#define _timerRegs_h_ + + +/* register addresses */ + +#define TIMER_CONFIG_OFFSET 0x00 +#define TIMER_WIDTH_OFFSET 0x04 +#define TIMER_PERIOD_OFFSET 0x08 +#define TIMER_COUNTER_OFFSET 0x0c + + +/* register fields */ + +#define TIMER_CONFIG_ERR_TYP_MASK 0xc000 +#define TIMER_CONFIG_ERR_TYP_NONE 0x0000 +#define TIMER_CONFIG_ERR_TYP_OVERFLOW 0x4000 +#define TIMER_CONFIG_ERR_TYP_PERIOD 0x8000 +#define TIMER_CONFIG_ERR_TYP_WIDTH 0xc000 +#define TIMER_CONFIG_EMU_RUN 0x0200 +#define TIMER_CONFIG_TOGGLE_HI 0x0100 +#define TIMER_CONFIG_CLK_SEL 0x0080 +#define TIMER_CONFIG_OUT_DIS 0x0040 +#define TIMER_CONFIG_TIN_SEL 0x0020 +#define TIMER_CONFIG_IRQ_ENA 0x0010 +#define TIMER_CONFIG_PERIOD_CNT 0x0008 +#define TIMER_CONFIG_PULSE_HI 0x0004 +#define TIMER_CONFIG_TMODE_MASK 0x0003 +#define TIMER_CONFIG_TMODE_RESET 0x0000 +#define TIMER_CONFIG_TMODE_PWM_OUT 0x0001 +#define TIMER_CONFIG_TMODE_WDTH_CAP 0x0002 +#define TIMER_CONFIG_TMODE_EXT_CLK 0x0003 + + +#endif /* _timerRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/twi.h b/bsps/bfin/include/libcpu/twi.h new file mode 100644 index 0000000000..2392ba532b --- /dev/null +++ b/bsps/bfin/include/libcpu/twi.h @@ -0,0 +1,68 @@ +/* not yet implemented */ + +/* + * RTEMS driver for Blackfin TWI (I2C) + * + * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _twi_h_ +#define _twi_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef struct { + uint32_t sclk; + void *base; + bool fast; + int8_t slave_address; +} bfin_twi_config_t; + +typedef struct bfin_twi_request_s { + bool write; + int count; + void *data; + /* Chained requests are done with repeated start conditions in between. + These are useful for atomic address write/data read transactions + (which can be important in multi-master configurations), and for + doing 10-bit addressing. */ + struct bfin_twi_request_s *next; +} bfin_twi_request_t; + +typedef rtems_status_code (*bfin_twi_callback_t)(int channel, + void *arg, + bool general_call, + bool write, + bool done, + int read_count, + uint8_t *data); + + +rtems_status_code bfin_twi_init(int channel, bfin_twi_config_t *config); + +rtems_status_code bfin_twi_register_callback(int channel, + bfin_twi_callback_t callback, + void *arg); + +void bfin_twi_isr(int source); + +rtems_status_code bfin_twi_request(int channel, uint8_t address, + bfin_twi_request_t *request, + rtems_interval timeout); + + +#ifdef __cplusplus +} +#endif + +#endif /* _twi_h_ */ + diff --git a/bsps/bfin/include/libcpu/twiRegs.h b/bsps/bfin/include/libcpu/twiRegs.h new file mode 100644 index 0000000000..c776f7886e --- /dev/null +++ b/bsps/bfin/include/libcpu/twiRegs.h @@ -0,0 +1,118 @@ +/* Blackfin Two Wire Interface Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _twiRegs_h_ +#define _twiRegs_h_ + + +/* register addresses */ + +#define TWI_CLKDIV_OFFSET 0x0000 +#define TWI_CONTROL_OFFSET 0x0004 +#define TWI_SLAVE_CTL_OFFSET 0x0008 +#define TWI_SLAVE_STAT_OFFSET 0x000c +#define TWI_SLAVE_ADDR_OFFSET 0x0010 +#define TWI_MASTER_CTL_OFFSET 0x0014 +#define TWI_MASTER_STAT_OFFSET 0x0018 +#define TWI_MASTER_ADDR_OFFSET 0x001c +#define TWI_INT_STAT_OFFSET 0x0020 +#define TWI_INT_MASK_OFFSET 0x0024 +#define TWI_FIFO_CTL_OFFSET 0x0028 +#define TWI_FIFO_STAT_OFFSET 0x002c +#define TWI_XMT_DATA8_OFFSET 0x0080 +#define TWI_XMT_DATA16_OFFSET 0x0084 +#define TWI_RCV_DATA8_OFFSET 0x0088 +#define TWI_RCV_DATA16_OFFSET 0x008c + + +/* register fields */ + +#define TWI_CLKDIV_CLKHI_MASK 0xff00 +#define TWI_CLKDIV_CLKHI_SHIFT 8 +#define TWI_CLKDIV_CLKLOW_MASK 0x00ff +#define TWI_CLKDIV_CLKLOW_SHIFT 0 + +#define TWI_CONTROL_SCCB 0x0200 +#define TWI_CONTROL_TWI_ENA 0x0080 +#define TWI_CONTROL_PRESCALE_MASK 0x007f +#define TWI_CONTROL_PRESCALE_SHIFT 0 + +#define TWI_SLAVE_CTL_GEN 0x0010 +#define TWI_SLAVE_CTL_NAK 0x0008 +#define TWI_SLAVE_CTL_STDVAL 0x0004 +#define TWI_SLAVE_CTL_SEN 0x0001 + +#define TWI_SLAVE_STAT_GCALL 0x0002 +#define TWI_SLAVE_STAT_SDIR 0x0001 + +#define TWI_SLAVE_ADDR_SADDR_MASK 0x007f +#define TWI_SLAVE_ADDR_SADDR_SHIFT 0 + +#define TWI_MASTER_CTL_SCLOVR 0x8000 +#define TWI_MASTER_CTL_SDAOVR 0x4000 +#define TWI_MASTER_CTL_DCNT_MASK 0x3fc0 +#define TWI_MASTER_CTL_DCNT_SHIFT 6 +#define TWI_MASTER_CTL_RSTART 0x0020 +#define TWI_MASTER_CTL_STOP 0x0010 +#define TWI_MASTER_CTL_FAST 0x0008 +#define TWI_MASTER_CTL_MDIR 0x0004 +#define TWI_MASTER_CTL_MEN 0x0001 + +#define TWI_MASTER_STAT_BUSBUSY 0x0100 +#define TWI_MASTER_STAT_SCLSEN 0x0080 +#define TWI_MASTER_STAT_SDASEN 0x0040 +#define TWI_MASTER_STAT_BUFWRERR 0x0020 +#define TWI_MASTER_STAT_BUFRDERR 0x0010 +#define TWI_MASTER_STAT_DNAK 0x0008 +#define TWI_MASTER_STAT_ANAK 0x0004 +#define TWI_MASTER_STAT_LOSTARB 0x0002 +#define TWI_MASTER_STAT_MPROG 0x0001 + +#define TWI_MASTER_ADDR_MADDR_MASK 0x007f +#define TWI_MASTER_ADDR_MADDR_SHIFT 0 + +#define TWI_INT_STAT_RCVSERV 0x0080 +#define TWI_INT_STAT_XMTSERV 0x0040 +#define TWI_INT_STAT_MERR 0x0020 +#define TWI_INT_STAT_MCOMP 0x0010 +#define TWI_INT_STAT_SOVF 0x0008 +#define TWI_INT_STAT_SERR 0x0004 +#define TWI_INT_STAT_SCOMP 0x0002 +#define TWI_INT_STAT_SINIT 0x0001 + +#define TWI_INT_MASK_RCVSERVM 0x0080 +#define TWI_INT_MASK_XMTSERVM 0x0040 +#define TWI_INT_MASK_MERRM 0x0020 +#define TWI_INT_MASK_MCOMPM 0x0010 +#define TWI_INT_MASK_SOVFM 0x0008 +#define TWI_INT_MASK_SERRM 0x0004 +#define TWI_INT_MASK_SCOMPM 0x0002 +#define TWI_INT_MASK_SINITM 0x0001 + +#define TWI_FIFO_CTL_RCVINTLEN 0x0008 +#define TWI_FIFO_CTL_XMTINTLEN 0x0004 +#define TWI_FIFO_CTL_RCVFLUSH 0x0002 +#define TWI_FIFO_CTL_XMTFLUSH 0x0001 + +#define TWI_FIFO_STAT_RCVSTAT_MASK 0x000c +#define TWI_FIFO_STAT_RCVSTAT_EMPTY 0x0000 +#define TWI_FIFO_STAT_RCVSTAT_SHIFT 2 +#define TWI_FIFO_STAT_XMTSTAT_MASK 0x0003 +#define TWI_FIFO_STAT_XMTSTAT_FULL 0x0003 +#define TWI_FIFO_STAT_XMTSTAT_SHIFT 0 + +#define TWI_XMT_DATA8_XMTDATA8_MASK 0x00ff +#define TWI_XMT_DATA8_XMTDATA8_SHIFT 0 + +#define TWI_RCV_DATA8_RCVDATA8_MASK 0x00ff +#define TWI_RCV_DATA8_RCVDATA8_SHIFT 0 + + +#endif /* _twiRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/uart.h b/bsps/bfin/include/libcpu/uart.h new file mode 100644 index 0000000000..730e0e261f --- /dev/null +++ b/bsps/bfin/include/libcpu/uart.h @@ -0,0 +1,135 @@ +/* + * RTEMS driver for Blackfin UARTs + * + * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + + +#ifndef _UART_H_ +#define _UART_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** bfin_uart_channel object + */ +typedef struct { + const char *name; /** Holds name of the device */ + uint32_t uart_baseAddress; /** UART base address */ + uint32_t uart_rxDmaBaseAddress; /** RX DMA base address */ + uint32_t uart_txDmaBaseAddress; /** TX DMA base address */ + bool uart_useInterrupts; /** are interrupts used */ + bool uart_useDma; /** is dma used */ + int uart_baud; /** baud rate, 0 for default */ + + void *termios; /** termios associated */ + uint8_t volatile flags; /** flags for internal use */ + uint16_t length; /** length for internal use */ +} bfin_uart_channel_t; + + +typedef struct { + uint32_t freq; + int num_channels; + bfin_uart_channel_t *channels; +} bfin_uart_config_t; + +/** + * @param base_address defines the UART base address + * @param source defines the source that caused the interrupt. This argument + * will help us in identifying if Rx or TX caused the interrupt. + */ +typedef struct { + uint32_t base_address; + int source; +} bfin_uart_arg_t; + + + +char bfin_uart_poll_read(rtems_device_minor_number minor); + +void bfin_uart_poll_write(int minor, char c); + + +/** +* Uart initialization function. +* @param major major number of the device +* @param config configuration parameters +* @return rtems status code +*/ +rtems_status_code bfin_uart_initialize(rtems_device_major_number major, + bfin_uart_config_t *config); + + + +/** + * Opens the device in different modes. The supported modes are + * 1. Polling + * 2. Interrupt + * 3. DMA + * At exit the uart_Exit function will be called to flush the device. + * + * @param major Major number of the device + * @param minor Minor number of the device + * @param arg + * @return + */ +rtems_device_driver bfin_uart_open(rtems_device_major_number major, + rtems_device_minor_number minor, void *arg); + + + +/** + * This function implements TX dma ISR. It clears the IRQ and dequeues a char + * The channel argument will have the base address. Since there are two uart + * and both the uarts can use the same tx dma isr. + * + * TODO: 1. Error checking 2. sending correct length ie after looking at the + * number of elements the uart transmitted. + * + * @param _arg argument passed to the interrupt handler. It contains the + * channel argument. + */ +void bfinUart_txDmaIsr(void *_arg); + + + +/** + * RX DMA ISR. + * The polling route is used for receiving the characters. This is a place + * holder for future implementation. + * @param _arg + */ +void bfinUart_rxDmaIsr(void *_arg); + + +/** + * This function implements TX ISR. The function gets called when the TX FIFO is + * empty. It clears the interrupt and dequeues the character. It only tx one + * character at a time. + * + * TODO: error handling. + * @param _arg gets the channel information. + */ +void bfinUart_txIsr(void *_arg); + + +/** +* This function implements RX ISR +*/ +void bfinUart_rxIsr(void *_arg); + + +#ifdef __cplusplus +} +#endif + +#endif /* _UART_H_ */ + diff --git a/bsps/bfin/include/libcpu/uartRegs.h b/bsps/bfin/include/libcpu/uartRegs.h new file mode 100644 index 0000000000..f48052e49b --- /dev/null +++ b/bsps/bfin/include/libcpu/uartRegs.h @@ -0,0 +1,70 @@ +/* Blackfin UART Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _uartRegs_h_ +#define _uartRegs_h_ + +/* register addresses */ + +#define UART_RBR_OFFSET 0x0000 +#define UART_THR_OFFSET 0x0000 +#define UART_DLL_OFFSET 0x0000 +#define UART_IER_OFFSET 0x0004 +#define UART_DLH_OFFSET 0x0004 +#define UART_IIR_OFFSET 0x0008 +#define UART_LCR_OFFSET 0x000c +#define UART_MCR_OFFSET 0x0010 +#define UART_LSR_OFFSET 0x0014 +#define UART_SCR_OFFSET 0x001c +#define UART_GCTL_OFFSET 0x0024 + + +/* register fields */ + +#define UART_LCR_DLAB 0x80 +#define UART_LCR_SB 0x40 +#define UART_LCR_STP 0x20 +#define UART_LCR_EPS 0x10 +#define UART_LCR_PEN 0x08 +#define UART_LCR_STB 0x04 +#define UART_LCR_WLS_MASK 0x03 +#define UART_LCR_WLS_5 0x00 +#define UART_LCR_WLS_6 0x01 +#define UART_LCR_WLS_7 0x02 +#define UART_LCR_WLS_8 0x03 + +#define UART_MCR_LOOP 0x10 + +#define UART_LSR_TEMT 0x40 +#define UART_LSR_THRE 0x20 +#define UART_LSR_BI 0x10 +#define UART_LSR_FE 0x08 +#define UART_LSR_PE 0x04 +#define UART_LSR_OE 0x02 +#define UART_LSR_DR 0x01 + +#define UART_IER_ELSI 0x04 +#define UART_IER_ETBEI 0x02 +#define UART_IER_ERBFI 0x01 + +#define UART_IIR_STATUS_MASK 0x06 +#define UART_IIR_STATUS_THRE 0x02 +#define UART_IIR_STATUS_RDR 0x04 +#define UART_IIR_STATUS_LS 0x06 +#define UART_IIR_NINT 0x01 + +#define UART_GCTL_FFE 0x20 +#define UART_GCTL_FPE 0x10 +#define UART_GCTL_RPOLC 0x08 +#define UART_GCTL_TPOLC 0x04 +#define UART_GCTL_IREN 0x02 +#define UART_GCTL_UCEN 0x01 + +#endif /* _uartRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/wdogRegs.h b/bsps/bfin/include/libcpu/wdogRegs.h new file mode 100644 index 0000000000..9e76d345b0 --- /dev/null +++ b/bsps/bfin/include/libcpu/wdogRegs.h @@ -0,0 +1,33 @@ +/* Blackfin Watchdog Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _wdogRegs_h_ +#define _wdogRegs_h_ + +/* register addresses */ + +#define WDOG_CTL (WDOG_BASE_ADDRESS + 0x0000) +#define WDOG_CNT (WDOG_BASE_ADDRESS + 0x0004) +#define WDOG_STAT (WDOG_BASE_ADDRESS + 0x0008) + + +/* register fields */ + +#define WDOG_CTL_WDRO 0x8000 +#define WDOG_CTL_WDEN_MASK 0x0ff0 +#define WDOG_CTL_WDEN_DISABLE 0x0ad0 +#define WDOG_CTL_WDEV_MASK 0x0006 +#define WDOG_CTL_WDEV_RESET 0x0000 +#define WDOG_CTL_WDEV_NMI 0x0002 +#define WDOG_CTL_WDEV_GPI 0x0004 +#define WDOG_CTL_WDEV_DISABLE 0x0006 + + +#endif /* _wdogRegs_h_ */ diff --git a/bsps/epiphany/epiphany_sim/headers.am b/bsps/epiphany/epiphany_sim/headers.am new file mode 100644 index 0000000000..bbe2514398 --- /dev/null +++ b/bsps/epiphany/epiphany_sim/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/epiphany/epiphany_sim/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/epiphany/epiphany_sim/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/epiphany/epiphany_sim/include/bsp/irq.h diff --git a/bsps/epiphany/epiphany_sim/include/bsp.h b/bsps/epiphany/epiphany_sim/include/bsp.h new file mode 100644 index 0000000000..46d495a8c5 --- /dev/null +++ b/bsps/epiphany/epiphany_sim/include/bsp.h @@ -0,0 +1,65 @@ +/** + * @defgroup bsp_epiphany Epiphany + * + * @ingroup bsp_epiphany + * + * @brief Epiphany Support Package + */ + +/* + * Copyright (c) 2015 University of York. + * Hesham ALMatary + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef LIBBSP_EPIPHANY_EPIPHANY_SIM_H +#define LIBBSP_EPIPHANY_EPIPHANY_SIM_H + +#include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Constants + * + * @{ + */ +void *clock_driver_sim_idle_body(uintptr_t); +#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_EPIPHANY_EPIPHANY_SIM_H */ diff --git a/bsps/epiphany/epiphany_sim/include/bsp/irq.h b/bsps/epiphany/epiphany_sim/include/bsp/irq.h new file mode 100644 index 0000000000..2b15a4536c --- /dev/null +++ b/bsps/epiphany/epiphany_sim/include/bsp/irq.h @@ -0,0 +1,49 @@ +/** + * @file + * + * @ingroup Epiphany_IRQ + * + * @brief Interrupt definitions. + */ + +/* + * + * Copyright (c) 2015 University of York. + * Hesham ALMatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef LIBBSP_GENERIC_EPIPHANY_IRQ_H +#define LIBBSP_GENERIC_EPIPHANY_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#define BSP_INTERRUPT_VECTOR_MIN 0x0 +#define BSP_INTERRUPT_VECTOR_MAX 0x24 + +#endif /* ASM */ +#endif /* LIBBSP_GENERIC_OR1K_IRQ_H */ diff --git a/bsps/epiphany/epiphany_sim/include/tm27.h b/bsps/epiphany/epiphany_sim/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/epiphany/epiphany_sim/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/epiphany/headers.am b/bsps/epiphany/headers.am new file mode 100644 index 0000000000..0ce8fb808b --- /dev/null +++ b/bsps/epiphany/headers.am @@ -0,0 +1,5 @@ +## This file was generated by "./boostrap -H". + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/epiphany/include/bsp/linker-symbols.h diff --git a/bsps/epiphany/include/bsp/linker-symbols.h b/bsps/epiphany/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..c218b7ff99 --- /dev/null +++ b/bsps/epiphany/include/bsp/linker-symbols.h @@ -0,0 +1,81 @@ +#ifndef LIBBSP_EPIPHANY_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_EPIPHANY_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup epiphany_linker Linker Support + * + * @ingroup epiphany_shared + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM + #define LINKER_SYMBOL(sym) extern char sym []; +#else + #define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_vector_begin) +LINKER_SYMBOL(bsp_section_vector_end) +LINKER_SYMBOL(bsp_section_vector_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_vector_table_begin) +LINKER_SYMBOL(bsp_vector_table_end) +LINKER_SYMBOL(bsp_vector_table_size) + +LINKER_SYMBOL(bsp_start_vector_table_begin) +LINKER_SYMBOL(bsp_start_vector_table_end) +LINKER_SYMBOL(bsp_start_vector_table_size) + +LINKER_SYMBOL(bsp_translation_table_base) +LINKER_SYMBOL(bsp_translation_table_end) + +LINKER_SYMBOL(_bsp_processor_count) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_EPIPHANY_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/headers.am b/bsps/headers.am new file mode 100644 index 0000000000..ab7fa34c58 --- /dev/null +++ b/bsps/headers.am @@ -0,0 +1,83 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../bsps/include/mpci.h +include_HEADERS += ../../bsps/include/shm_driver.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../bsps/include/bsp/VME.h +include_bsp_HEADERS += ../../bsps/include/bsp/VMEDMA.h +include_bsp_HEADERS += ../../bsps/include/bsp/bootcard.h +include_bsp_HEADERS += ../../bsps/include/bsp/bspVmeDmaList.h +include_bsp_HEADERS += ../../bsps/include/bsp/console-polled.h +include_bsp_HEADERS += ../../bsps/include/bsp/console-termios.h +include_bsp_HEADERS += ../../bsps/include/bsp/default-initial-extension.h +include_bsp_HEADERS += ../../bsps/include/bsp/fatal.h +include_bsp_HEADERS += ../../bsps/include/bsp/fdt.h +include_bsp_HEADERS += ../../bsps/include/bsp/gpio.h +include_bsp_HEADERS += ../../bsps/include/bsp/irq-generic.h +include_bsp_HEADERS += ../../bsps/include/bsp/irq-info.h +include_bsp_HEADERS += ../../bsps/include/bsp/mm.h +include_bsp_HEADERS += ../../bsps/include/bsp/stackalloc.h +include_bsp_HEADERS += ../../bsps/include/bsp/u-boot.h +include_bsp_HEADERS += ../../bsps/include/bsp/uart-output-char.h +include_bsp_HEADERS += ../../bsps/include/bsp/utility.h +include_bsp_HEADERS += ../../bsps/include/bsp/vmeTsi148.h +include_bsp_HEADERS += ../../bsps/include/bsp/vmeTsi148DMA.h +include_bsp_HEADERS += ../../bsps/include/bsp/vmeUniverse.h +include_bsp_HEADERS += ../../bsps/include/bsp/vmeUniverseDMA.h +include_bsp_HEADERS += ../../bsps/include/bsp/vme_am_defs.h + +include_libchipdir = $(includedir)/libchip +include_libchip_HEADERS = +include_libchip_HEADERS += ../../bsps/include/libchip/am29lv160.h +include_libchip_HEADERS += ../../bsps/include/libchip/ata.h +include_libchip_HEADERS += ../../bsps/include/libchip/ata_internal.h +include_libchip_HEADERS += ../../bsps/include/libchip/cs8900.h +include_libchip_HEADERS += ../../bsps/include/libchip/disp_hcms29xx.h +include_libchip_HEADERS += ../../bsps/include/libchip/ds1375-rtc.h +include_libchip_HEADERS += ../../bsps/include/libchip/greth.h +include_libchip_HEADERS += ../../bsps/include/libchip/i2c-2b-eeprom.h +include_libchip_HEADERS += ../../bsps/include/libchip/i2c-ds1621.h +include_libchip_HEADERS += ../../bsps/include/libchip/i2c-sc620.h +include_libchip_HEADERS += ../../bsps/include/libchip/i82586var.h +include_libchip_HEADERS += ../../bsps/include/libchip/icm7170.h +include_libchip_HEADERS += ../../bsps/include/libchip/ide_ctrl.h +include_libchip_HEADERS += ../../bsps/include/libchip/ide_ctrl_cfg.h +include_libchip_HEADERS += ../../bsps/include/libchip/ide_ctrl_io.h +include_libchip_HEADERS += ../../bsps/include/libchip/if_dcreg.h +include_libchip_HEADERS += ../../bsps/include/libchip/if_fxpvar.h +include_libchip_HEADERS += ../../bsps/include/libchip/m48t08.h +include_libchip_HEADERS += ../../bsps/include/libchip/mc146818a.h +include_libchip_HEADERS += ../../bsps/include/libchip/mc68681.h +include_libchip_HEADERS += ../../bsps/include/libchip/ns16550.h +include_libchip_HEADERS += ../../bsps/include/libchip/ns16550_p.h +include_libchip_HEADERS += ../../bsps/include/libchip/open_eth.h +include_libchip_HEADERS += ../../bsps/include/libchip/rtc.h +include_libchip_HEADERS += ../../bsps/include/libchip/serial.h +include_libchip_HEADERS += ../../bsps/include/libchip/sersupp.h +include_libchip_HEADERS += ../../bsps/include/libchip/smc91111.h +include_libchip_HEADERS += ../../bsps/include/libchip/smc91111exp.h +include_libchip_HEADERS += ../../bsps/include/libchip/sonic.h +include_libchip_HEADERS += ../../bsps/include/libchip/spi-flash-m25p40.h +include_libchip_HEADERS += ../../bsps/include/libchip/spi-fram-fm25l256.h +include_libchip_HEADERS += ../../bsps/include/libchip/spi-memdrv.h +include_libchip_HEADERS += ../../bsps/include/libchip/spi-sd-card.h +include_libchip_HEADERS += ../../bsps/include/libchip/wd80x3.h +include_libchip_HEADERS += ../../bsps/include/libchip/z85c30.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += ../../bsps/include/rtems/umon.h + +include_rtems_zilogdir = $(includedir)/rtems/zilog +include_rtems_zilog_HEADERS = +include_rtems_zilog_HEADERS += ../../bsps/include/rtems/zilog/z8036.h +include_rtems_zilog_HEADERS += ../../bsps/include/rtems/zilog/z8530.h + +include_umondir = $(includedir)/umon +include_umon_HEADERS = +include_umon_HEADERS += ../../bsps/include/umon/cli.h +include_umon_HEADERS += ../../bsps/include/umon/monlib.h +include_umon_HEADERS += ../../bsps/include/umon/tfs.h diff --git a/bsps/i386/headers.am b/bsps/i386/headers.am new file mode 100644 index 0000000000..8a3d39cfbb --- /dev/null +++ b/bsps/i386/headers.am @@ -0,0 +1,20 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../bsps/i386/include/i386_io.h +include_HEADERS += ../../../../../bsps/i386/include/uart.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/i386/include/bsp/apic.h +include_bsp_HEADERS += ../../../../../bsps/i386/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../bsps/i386/include/bsp/irq_asm.h +include_bsp_HEADERS += ../../../../../bsps/i386/include/bsp/realmode_int.h +include_bsp_HEADERS += ../../../../../bsps/i386/include/bsp/smp-imps.h +include_bsp_HEADERS += ../../../../../bsps/i386/include/bsp/tty_drv.h + +include_libcpudir = $(includedir)/libcpu +include_libcpu_HEADERS = +include_libcpu_HEADERS += ../../../../../bsps/i386/include/libcpu/byteorder.h +include_libcpu_HEADERS += ../../../../../bsps/i386/include/libcpu/cpuModel.h +include_libcpu_HEADERS += ../../../../../bsps/i386/include/libcpu/page.h diff --git a/bsps/i386/include/bsp/apic.h b/bsps/i386/include/bsp/apic.h new file mode 100644 index 0000000000..9ae103b963 --- /dev/null +++ b/bsps/i386/include/bsp/apic.h @@ -0,0 +1,125 @@ +/** + * @file + * @ingroup i386_apic + * @brief Local and I/O APIC definitions + */ + +/* + * Author: Erich Boleyn + * http://www.uruk.org/~erich/ + * + * Copyright (c) 1997-2011 Erich Boleyn. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup i386_apci + * @ingroup i386_pci + * @brief Intel Architecture local and I/O APIC definitions + * @{ + */ + +/* + * Header file for Intel Architecture local and I/O APIC definitions. + * + * This file was created from information in the Intel Pentium Pro + * Family Developer's Manual, Volume 3: Operating System Writer's + * Manual, order number 242692-001, which can be ordered from the + * Intel literature center. + */ + +#ifndef _APIC_H +#define _APIC_H + +/* + * APIC Defines. + */ + +/* + * Recommendation: Don't use this except for MSI interrupt delivery. + * In general, the "Destination Mode" can be used to control this, since + * it is DIFFERENT (0xF) for Pentium and P6, but not on the same APIC + * version for AMD Opteron. + */ +#define APIC_BCAST_ID 0xFF + +/* + * APIC register definitions + */ + +/* + * Shared defines for I/O and local APIC definitions + */ +/** @brief APIC version register */ +#define APIC_VERSION(x) ((x) & 0xFF) +#define APIC_MAXREDIR(x) (((x) >> 16) & 0xFF) +/** @brief APIC id register */ +#define APIC_ID(x) ((x) >> 24) +#define APIC_VER_NEW 0x10 + +#define IOAPIC_REGSEL 0 +#define IOAPIC_RW 0x10 +#define IOAPIC_ID 0 +#define IOAPIC_VER 1 +#define IOAPIC_REDIR 0x10 + +#define LAPIC_ID 0x20 +#define LAPIC_VER 0x30 +#define LAPIC_TPR 0x80 +#define LAPIC_APR 0x90 +#define LAPIC_PPR 0xA0 +#define LAPIC_EOI 0xB0 +#define LAPIC_LDR 0xD0 +#define LAPIC_DFR 0xE0 +#define LAPIC_SPIV 0xF0 +#define LAPIC_SPIV_ENABLE_APIC 0x100 +#define LAPIC_ISR 0x100 +#define LAPIC_TMR 0x180 +#define LAPIC_IRR 0x200 +#define LAPIC_ESR 0x280 +#define LAPIC_ICR 0x300 +#define LAPIC_ICR_DS_SELF 0x40000 +#define LAPIC_ICR_DS_ALLINC 0x80000 +#define LAPIC_ICR_DS_ALLEX 0xC0000 +#define LAPIC_ICR_TM_LEVEL 0x8000 +#define LAPIC_ICR_LEVELASSERT 0x4000 +#define LAPIC_ICR_STATUS_PEND 0x1000 +#define LAPIC_ICR_DM_LOGICAL 0x800 +#define LAPIC_ICR_DM_LOWPRI 0x100 +#define LAPIC_ICR_DM_SMI 0x200 +#define LAPIC_ICR_DM_NMI 0x400 +#define LAPIC_ICR_DM_INIT 0x500 +#define LAPIC_ICR_DM_SIPI 0x600 +#define LAPIC_LVTT 0x320 +#define LAPIC_LVTPC 0x340 +#define LAPIC_LVT0 0x350 +#define LAPIC_LVT1 0x360 +#define LAPIC_LVTE 0x370 +#define LAPIC_TICR 0x380 +#define LAPIC_TCCR 0x390 +#define LAPIC_TDCR 0x3E0 + +#endif /* _APIC_H */ + +/** @} */ diff --git a/bsps/i386/include/bsp/irq.h b/bsps/i386/include/bsp/irq.h new file mode 100644 index 0000000000..f7e673c8a7 --- /dev/null +++ b/bsps/i386/include/bsp/irq.h @@ -0,0 +1,96 @@ +/** + * @file + * @ingroup i386_irq + * @brief Interrupt handlers + */ + +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * CopyRight (C) 1998 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup i386_irq Interrupt handlers + * @ingroup i386_shared + * @brief Data structure and the functions to write interrupt handlers + * @{ + */ + +#ifndef _IRQ_H_ +#define _IRQ_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief + * Include some preprocessor value also used by assember code + */ + +#include +#include +#define BSP_SHARED_HANDLER_SUPPORT 1 +#include +#include + +/*-------------------------------------------------------------------------+ +| Constants ++--------------------------------------------------------------------------*/ + +/** @brief Base vector for our IRQ handlers. */ +#define BSP_IRQ_VECTOR_BASE BSP_ASM_IRQ_VECTOR_BASE +#define BSP_IRQ_LINES_NUMBER 16 +#define BSP_IRQ_MAX_ON_i8259A (BSP_IRQ_LINES_NUMBER - 1) + +/* + * Define the number of valid vectors. This is different to the number of IRQ + * signals supported. Use this value to allocation vector data or range check. + */ +#define BSP_IRQ_VECTOR_NUMBER 17 +#define BSP_IRQ_VECTOR_LOWEST_OFFSET 0 +#define BSP_IRQ_VECTOR_MAX_OFFSET (BSP_IRQ_VECTOR_NUMBER - 1) + +/** @brief + * Interrupt offset in comparison to BSP_ASM_IRQ_VECTOR_BASE + * NB : 1) Interrupt vector number in IDT = offset + BSP_ASM_IRQ_VECTOR_BASE + * 2) The same name should be defined on all architecture + * so that handler connection can be unchanged. + */ +#define BSP_PERIODIC_TIMER 0 /* fixed on all builds of PC */ +#define BSP_KEYBOARD 1 /* fixed on all builds of PC */ +#define BSP_UART_COM2_IRQ 3 /* fixed for ISA bus */ +#define BSP_UART_COM1_IRQ 4 /* fixed for ISA bus */ +#define BSP_UART_COM3_IRQ 5 +#define BSP_UART_COM4_IRQ 6 +#define BSP_RT_TIMER1 8 +#define BSP_RT_TIMER3 10 +#define BSP_SMP_IPI 16 /* not part of the ATPIC */ + +#define BSP_INTERRUPT_VECTOR_MIN BSP_IRQ_VECTOR_LOWEST_OFFSET +#define BSP_INTERRUPT_VECTOR_MAX BSP_IRQ_VECTOR_MAX_OFFSET + +/** @brief + * Type definition for RTEMS managed interrupts + */ +typedef unsigned short rtems_i8259_masks; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _IRQ_H_ */ diff --git a/bsps/i386/include/bsp/irq_asm.h b/bsps/i386/include/bsp/irq_asm.h new file mode 100644 index 0000000000..05cb4e6cc3 --- /dev/null +++ b/bsps/i386/include/bsp/irq_asm.h @@ -0,0 +1,45 @@ +/** + * @file + * @ingroup i386_irq + * @brief + */ + +/* irq_asm.h + * + * This include file has defines to represent some contant used + * to program and manage the Intel 8259 interrupt controller + * + * + * COPYRIGHT (c) 1998 valette@crf.canon.fr + * + * Copyright (c) 2016 Chris Johns + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __I8259S_H__ +#define __I8259S_H__ + +#define BSP_ASM_IRQ_VECTOR_BASE 0x20 + /** @brief PIC's command and mask registers */ +#define PIC_MASTER_COMMAND_IO_PORT 0x20 ///< Master PIC command register +#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 ///< Slave PIC command register +#define PIC_MASTER_IMR_IO_PORT 0x21 ///< Master PIC Interrupt Mask Register +#define PIC_SLAVE_IMR_IO_PORT 0xa1 ///< Slave PIC Interrupt Mask Register + + /** @brief Command for specific EOI (End Of Interrupt): Interrupt acknowledge */ +#define PIC_EOSI 0x60 ///< End of Specific Interrupt (EOSI) +#define PIC_EOI 0x20 ///< Generic End of Interrupt (EOI) + +/* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */ +#define PIC_OCW3_RIS 0x01 /* 1 = read IS, 0 = read IR */ +#define PIC_OCW3_RR 0x02 /* register read */ +#define PIC_OCW3_P 0x04 /* poll mode command */ +/* 0x08 must be 1 to select OCW3 vs OCW2 */ +#define PIC_OCW3_SEL 0x08 /* must be 1 */ +/* 0x10 must be 0 to select OCW3 vs ICW1 */ +#define PIC_OCW3_SMM 0x20 /* special mode mask */ +#define PIC_OCW3_ESMM 0x40 /* enable SMM */ + +#endif diff --git a/bsps/i386/include/bsp/realmode_int.h b/bsps/i386/include/bsp/realmode_int.h new file mode 100644 index 0000000000..e8a1e36d01 --- /dev/null +++ b/bsps/i386/include/bsp/realmode_int.h @@ -0,0 +1,97 @@ +/** + * @file realmode_int.h + * + * @ingroup i386_shared + * + * @brief Definitioins supporting real mode interrupt calls. + * + * Interface allows calling given interrupt number with content of the + * registers defined. For passing or receiving higher amounts of the data + * there is a buffer accessible from real mode available. Real mode pointer + * to this buffer is passed to the interrupt in the registers. + */ + +/* + * Copyright (C) 2014 Jan Doležal (dolezj21@fel.cvut.cz) + * CTU in Prague. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _REALMODE_INT_H +#define _REALMODE_INT_H + +#include +#include + +#ifndef ASM /* ASM */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* --- BIOS service interrupt number --- */ +/* number of interrupt servicing video functions */ +#define INTERRUPT_NO_VIDEO_SERVICES 0x10 + +/** + * @brief Used for passing and retrieving registers content to/from real mode + * interrupt call. + */ +typedef struct { + uint32_t reg_eax; + uint32_t reg_ebx; + uint32_t reg_ecx; + uint32_t reg_edx; + uint32_t reg_esi; + uint32_t reg_edi; + uint16_t reg_ds; + uint16_t reg_es; + uint16_t reg_fs; + uint16_t reg_gs; +} RTEMS_PACKED i386_realmode_interrupt_registers; + +/** + * @brief Returns buffer and its size usable with real mode interrupt call. + * + * Provides position to real mode buffer. It is buffer + * accessible from real mode context - it is located below + * address ~0x100000 in order for it to be accessible + * This buffer is meant to be pointed to by segReg:GenPurpReg + * and through this get bigger portion of an information to/from + * interrupt service routine than just by using register. + * + * @param[out] size pointer to variable, where the size of buffer + * will be filled + * @retval pointer to buffer + */ +extern void *i386_get_default_rm_buffer(uint16_t *size); + +/** + * @brief Call to real mode interrupt with specified int NO and processor + * registers. + * + * This function allows calling interrupts in real mode and to set processor + * registers as desired before interrupt call is made and to retrieve the + * registers content after call was made. + * + * @param[in] interrupt_number interrupt number to be called + * @param[in] ir pointer to structure containing registers to be passed to + * interrupt and to retrieve register content after call was made. + * @retval 0 call failed (GDT too small or pagin is on) + * @retval 1 call successful + */ +extern int i386_real_interrupt_call( + uint8_t interrupt_number, + i386_realmode_interrupt_registers *ir +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* _REALMODE_INT_H */ diff --git a/bsps/i386/include/bsp/smp-imps.h b/bsps/i386/include/bsp/smp-imps.h new file mode 100644 index 0000000000..60e688547b --- /dev/null +++ b/bsps/i386/include/bsp/smp-imps.h @@ -0,0 +1,245 @@ +/** + * @file + * @ingroup i386_smp + * @brief Intel MultiProcessor Specification (MPS) + * version 1.1 and 1.4 SMP hardware control + */ + +/* + * Author: Erich Boleyn + * http://www.uruk.org/~erich/ + * + * Copyright (c) 1997-2011 Erich Boleyn. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Header file implementing Intel MultiProcessor Specification (MPS) + * version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs, + * with hooks for running correctly on a standard PC without the hardware. + * + * This file was created from information in the Intel MPS version 1.4 + * document, order number 242016-004, which can be ordered from the + * Intel literature center. + */ + +/* + * This file is based upon code by Eric Boleyn as documented above. + * RTEMS support was added and minimal other changes were made. + * This should make it easier to compare this file with the original + * version. + * + * COPYRIGHT (c) 2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup i386_smp SMP + * @ingroup i386_shared + * @brief + * Header file implementing Intel MultiProcessor Specification (MPS) + * version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs, + * with hooks for running correctly on a standard PC without the hardware. + */ + +#ifndef _SMP_IMPS_H +#define _SMP_IMPS_H + +/* make sure "apic.h" is included */ +#ifndef _APIC_H +#error Must include "apic.h" before "smp-imps.h" +#endif /* !_APIC_H */ + +/* + * Defines used. + */ + +#define IMPS_READ(x) (*((volatile unsigned *) (x))) +#define IMPS_WRITE(x,y) (*((volatile unsigned *) (x)) = (y)) + +#ifdef IMPS_DEBUG +#define IMPS_DEBUG_PRINT(x) KERNEL_PRINT(x) +#else /* !IMPS_DEBUG */ +#define IMPS_DEBUG_PRINT(x) +#endif /* !IMPS_DEBUG */ + +#define IMPS_MAX_CPUS APIC_BCAST_ID + +/** @brief + * This is the value that must be in the "sig" member of the MP + * Floating Pointer Structure. + */ +#define IMPS_FPS_SIGNATURE ('_' | ('M'<<8) | ('P'<<16) | ('_'<<24)) +#define IMPS_FPS_IMCRP_BIT 0x80 +#define IMPS_FPS_DEFAULT_MAX 7 + +/** @brief + * This is the value that must be in the "sig" member of the MP + * Configuration Table Header. + */ +#define IMPS_CTH_SIGNATURE ('P' | ('C'<<8) | ('M'<<16) | ('P'<<24)) + +/** @brief + * These are the "type" values for Base MP Configuration Table entries. + */ +#define IMPS_FLAG_ENABLED 1 +#define IMPS_BCT_PROCESSOR 0 +#define IMPS_CPUFLAG_BOOT 2 +#define IMPS_BCT_BUS 1 +#define IMPS_BCT_IOAPIC 2 +#define IMPS_BCT_IO_INTERRUPT 3 +#define IMPS_BCT_LOCAL_INTERRUPT 4 +#define IMPS_INT_INT 0 +#define IMPS_INT_NMI 1 +#define IMPS_INT_SMI 2 +#define IMPS_INT_EXTINT 3 + + +/* + * Typedefs and data item definitions done here. + */ + +typedef struct imps_fps imps_fps; ///< MP floating pointer structure +typedef struct imps_cth imps_cth; ///< MP configuration table header +typedef struct imps_processor imps_processor; +typedef struct imps_bus imps_bus; +typedef struct imps_ioapic imps_ioapic; +typedef struct imps_interrupt imps_interrupt; + + +/* + * Data structures defined here + */ + +/** @brief + * MP Floating Pointer Structure (fps) + * + * Look at page 4-3 of the MP spec for the starting definitions of + * this structure. + */ +struct imps_fps +{ + unsigned sig; + imps_cth *cth_ptr; + unsigned char length; + unsigned char spec_rev; + unsigned char checksum; + unsigned char feature_info[5]; +}; + +/** @brief + * MP Configuration Table Header (cth) + * + * Look at page 4-5 of the MP spec for the starting definitions of + * this structure. + */ +struct imps_cth +{ + unsigned sig; + unsigned short base_length; + unsigned char spec_rev; + unsigned char checksum; + char oem_id[8]; + char prod_id[12]; + unsigned oem_table_ptr; + unsigned short oem_table_size; + unsigned short entry_count; + unsigned lapic_addr; + unsigned short extended_length; + unsigned char extended_checksum; + char reserved[1]; +}; + +/** @brief + * Base MP Configuration Table Types. They are sorted according to + * type (i.e. all of type 0 come first, etc.). Look on page 4-6 for + * the start of the descriptions. + */ + +struct imps_processor +{ + unsigned char type; ///< must be 0 + unsigned char apic_id; + unsigned char apic_ver; + unsigned char flags; + unsigned signature; + unsigned features; + char reserved[8]; +}; + +struct imps_bus +{ + unsigned char type; ///< must be 1 + unsigned char id; + char bus_type[6]; +}; + +struct imps_ioapic +{ + unsigned char type; ///< must be 2 + unsigned char id; + unsigned char ver; + unsigned char flags; + unsigned addr; +}; + +struct imps_interrupt +{ + unsigned char type; ///< must be 3 or 4 + unsigned char int_type; + unsigned short flags; + unsigned char source_bus_id; + unsigned char source_bus_irq; + unsigned char dest_apic_id; + unsigned char dest_apic_intin; +}; + +/* + * Exported globals here. + */ + +/** @brief + * These map from virtual cpu numbers to APIC id's and back. + */ +extern unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS]; +extern unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS]; + +/** @brief base address of application processor reset code at 0x70000 */ +extern char _binary_appstart_bin_start[]; +extern char _binary_appstart_bin_size[]; + +/* + * Defines that use variables + */ +#define IMPS_LAPIC_READ(x) (*((volatile unsigned *) (imps_lapic_addr+(x)))) +#define IMPS_LAPIC_WRITE(x, y) \ + (*((volatile unsigned *) (imps_lapic_addr+(x))) = (y)) + +#endif /* !_SMP_IMPS_H */ + +/** @} */ diff --git a/bsps/i386/include/bsp/tty_drv.h b/bsps/i386/include/bsp/tty_drv.h new file mode 100644 index 0000000000..cbfb346f22 --- /dev/null +++ b/bsps/i386/include/bsp/tty_drv.h @@ -0,0 +1,104 @@ +/** + * @file + * @ingroup i386_tty + * @brief ttySx driver + */ + +#ifndef __tty_drv__ +#define __tty_drv__ +/*************************************************************************** + * + * Copyright (c) 1999 ConnectTel, Inc. All Rights Reserved. + * + * MODULE DESCRIPTION: Prototype routines for the ttySx driver. + * + * by: Rosimildo da Silva: + * rdasilva@connecttel.com + * http://www.connecttel.com + * + ****************************************************************************/ + +/** + * @defgroup i386_tty ttSx + * @ingroup i386_comm + * @brief i386 tySx driver + * @{ + */ + +/* functions */ +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief ttyS1 entry points */ +rtems_device_driver tty1_initialize( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver tty1_open( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver tty1_control( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +/** @brief tty1 & tty2 shared entry points */ +rtems_device_driver tty_close( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver tty_read( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver tty_write( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +/** @brief tty2 entry points */ +rtems_device_driver tty2_initialize( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver tty2_open( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver tty2_control( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +#define TTY1_DRIVER_TABLE_ENTRY \ + { tty1_initialize, tty1_open, tty_close, \ + tty_read, tty_write, tty1_control } + +#define TTY2_DRIVER_TABLE_ENTRY \ + { tty2_initialize, tty2_open, tty_close, \ + tty_read, tty_write, tty2_control } + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __tty_drv__ */ diff --git a/bsps/i386/include/i386_io.h b/bsps/i386/include/i386_io.h new file mode 100644 index 0000000000..1308d58b6b --- /dev/null +++ b/bsps/i386/include/i386_io.h @@ -0,0 +1,73 @@ +/** + * @file + * @ingroup i386_io + * @brief I/O + */ + +/* + * Copyright (c) 2000 - Rosimildo da Silva. All Rights Reserved. + * + * MODULE DESCRIPTION: + * + * IO Functions for the PC platform equivalent to DOS/Linux. They make + * eaiser the porting of code from these platforms. + * + * by: Rosimildo da Silva: rdasilva@connecttel.com + * + */ + +/** + * @defgroup i386_io I/O + * @ingroup i386_comm + * @brief I/O + * @{ + */ + +#ifndef i386_io_h__ +#define i386_io_h__ + +#define rtems_inb(port) \ +({ \ + register int _inb_result; \ + \ + __asm__ volatile ("xorl %%eax,%%eax; inb %%dx,%%al" : \ + "=a" (_inb_result) : "d" (port)); \ + _inb_result; \ +}) + +#define rtems_inw(port) \ +({ \ + register int _inbw_result; \ + \ + __asm__ volatile ("xorl %%eax,%%eax; inw %%dx,%%ax" : \ + "=a" (_inbw_result) : "d" (port)); \ + _inbw_result; \ +}) + +#define rtems_outb(port, data) \ + __asm__ volatile ("outb %%al,%%dx" : : "a" (data), "d" (port)) + +#define rtems_outw(port, data) \ + __asm__ volatile ("outw %%ax,%%dx" : : "a" (data), "d" (port)) + +#define outp(port, val) rtems_outb(port,val) +#define inp(port) rtems_inb(port) + +#define outb(val, port) rtems_outb(port,val) +#define inb(port) rtems_inb(port) + +#define outb_p(val, port) rtems_outb(port,val) +#define inb_p(port) rtems_inb(port) + +#define outportb(port,val) rtems_outb(port,val) +#define inportb(port) rtems_inb(port) + +#define outw(val, port) rtems_outw(port,val) +#define inw(port) rtems_inw(port) + +#define cli() __asm__ __volatile__("cli") +#define sti() __asm__ __volatile__("sti"); + +#endif /* i386_io_h__ */ + +/** @} */ diff --git a/bsps/i386/include/libcpu/byteorder.h b/bsps/i386/include/libcpu/byteorder.h new file mode 100644 index 0000000000..939e51fe84 --- /dev/null +++ b/bsps/i386/include/libcpu/byteorder.h @@ -0,0 +1,31 @@ +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_BYTEORDER_H +#define _LIBCPU_BYTEORDER_H + +static inline void st_le32(volatile uint32_t *addr, uint32_t value) +{ + *(addr)=value ; +} + +static inline uint32_t ld_le32(volatile uint32_t *addr) +{ + return(*addr); +} + +static inline void st_le16(volatile uint16_t *addr, uint16_t value) +{ + *(addr)=value ; +} + +static inline uint16_t ld_le16(volatile uint16_t *addr) +{ + return(*addr); +} + + +#endif diff --git a/bsps/i386/include/libcpu/cpuModel.h b/bsps/i386/include/libcpu/cpuModel.h new file mode 100644 index 0000000000..d17839b7ea --- /dev/null +++ b/bsps/i386/include/libcpu/cpuModel.h @@ -0,0 +1,51 @@ +/* + * This file contains declaration for variables and code + * that may be used to get the Intel Cpu identification + * that has been performed by checkCPUtypeSetCr0 function. + */ + +/* + * COPYRIGHT (c) 1998 valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef libcpu_cpuModel_h +#define libcpu_cpuModel_h + +/* + * Tell us the machine setup.. + */ + +extern char hard_math; /* floating point coprocessor present indicator */ +extern char x86; /* type of cpu (3 = 386, 4 =486, ...) */ +extern char x86_model; +extern char x86_mask; +extern int x86_capability; /* cpuid:EDX */ +extern int x86_capability_x; /* cpuid:ECX */ +extern int x86_capability_ebx; /* cpuid:EBX */ +extern int x86_capability_cores; /* cpuid.(EAX=4, ECX=0) - physical cores */ +extern char x86_vendor_id[13]; +extern int have_cpuid; +extern unsigned char Cx86_step; /* cyrix processor identification */ + +/* Display this information on console in ascii form */ +extern void printCpuInfo(void); + +/* determine if the CPU has a TSC */ +#define x86_has_tsc() \ + (x86_capability & (1 << 4)) + +static inline unsigned long long +rdtsc(void) +{ + /* Return the value of the on-chip cycle counter. */ + unsigned long long result; + __asm__ volatile(".byte 0x0F, 0x31" : "=A" (result)); + return result; +} /* rdtsc */ + + +#endif diff --git a/bsps/i386/include/libcpu/page.h b/bsps/i386/include/libcpu/page.h new file mode 100644 index 0000000000..5e9cec2227 --- /dev/null +++ b/bsps/i386/include/libcpu/page.h @@ -0,0 +1,39 @@ +/* + * @file page.h + * + * Copyright (C) 1998 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_i386_PAGE_H +#define _LIBCPU_i386_PAGE_H + +#ifndef ASM + +#include + +/* C declaration for paging management */ + +extern int _CPU_is_cache_enabled(void); +extern int _CPU_is_paging_enabled(void); +extern int init_paging(void); +extern void _CPU_enable_paging(void); +extern void _CPU_disable_paging(void); +extern void _CPU_disable_cache(void); +extern void _CPU_enable_cache(void); +extern int _CPU_map_phys_address + (void **mappedAddress, void *physAddress, + int size, int flag); +extern int _CPU_unmap_virt_address (void *mappedAddress, int size); +extern int _CPU_change_memory_mapping_attribute + (void **newAddress, void *mappedAddress, + unsigned int size, unsigned int flag); +extern int _CPU_display_memory_attribute(void); + +# endif /* ASM */ + +#endif diff --git a/bsps/i386/include/uart.h b/bsps/i386/include/uart.h new file mode 100644 index 0000000000..96e4a312b4 --- /dev/null +++ b/bsps/i386/include/uart.h @@ -0,0 +1,191 @@ +/** + * @file + * @ingroup i386_uart + * @brief i386 UART definitions + */ + +/* + * This software is Copyright (C) 1998 by T.sqware - all rights limited + * It is provided in to the public domain "as is", can be freely modified + * as far as this copyight notice is kept unchanged, but does not imply + * an endorsement by T.sqware of the product in which it is included. + */ + +/** + * @defgroup i386_uart UART + * @ingroup i386_comm + * @brief i386 UART definitions + * @{ + */ + +#ifndef _BSPUART_H +#define _BSPUART_H + +#ifdef __cplusplus +extern "C" { +#endif + +void BSP_uart_init(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits, int hwFlow); +void BSP_uart_set_attributes(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits); +void BSP_uart_set_baud(int uart, unsigned long baud); +void BSP_uart_intr_ctrl(int uart, int cmd); +void BSP_uart_throttle(int uart); +void BSP_uart_unthrottle(int uart); +int BSP_uart_polled_status(int uart); +void BSP_uart_polled_write(int uart, int val); +int BSP_uart_polled_read(int uart); +void BSP_uart_termios_set(int uart, void *ttyp); +int BSP_uart_termios_read_com1(int uart); +int BSP_uart_termios_read_com2(int uart); +ssize_t BSP_uart_termios_write_com1(int minor, const char *buf, size_t len); +ssize_t BSP_uart_termios_write_com2(int minor, const char *buf, size_t len); +void BSP_uart_termios_isr_com1(void *); +void BSP_uart_termios_isr_com2(void *); +void BSP_uart_dbgisr_com1(void); +void BSP_uart_dbgisr_com2(void); +extern int BSP_poll_char_via_serial(void); +extern void BSP_output_char_via_serial(char val); +extern int BSPConsolePort; +extern int BSPBaseBaud; + +/** @brief + * Command values for BSP_uart_intr_ctrl(), + * values are strange in order to catch errors + * with assert + */ +#define BSP_UART_INTR_CTRL_DISABLE (0) +#define BSP_UART_INTR_CTRL_GDB (0xaa) ///< RX only +#define BSP_UART_INTR_CTRL_ENABLE (0xbb) ///< Normal operations +#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) ///< RX & line status + +/** @brief Return values for uart_polled_status() */ +#define BSP_UART_STATUS_ERROR (-1) ///< No character +#define BSP_UART_STATUS_NOCHAR (0) ///< No character +#define BSP_UART_STATUS_CHAR (1) ///< Character present +#define BSP_UART_STATUS_BREAK (2) ///< Break point is detected + +/** @brief PC UART definitions */ +#define BSP_UART_COM1 (0) +#define BSP_UART_COM2 (1) + +/** @brief + * Base IO for UART + */ + +#define COM1_BASE_IO 0x3F8 +#define COM2_BASE_IO 0x2F8 + +/** @brief + * Offsets from base + */ + +/** @brief DLAB 0 */ +#define RBR (0) ///< Rx Buffer Register (read) +#define THR (0) ///< Tx Buffer Register (write) +#define IER (1) ///< Interrupt Enable Register + +/** @brief DLAB X */ +#define IIR (2) ///< Interrupt Ident Register (read) +#define FCR (2) ///< FIFO Control Register (write) +#define LCR (3) ///< Line Control Register +#define MCR (4) ///< Modem Control Register +#define LSR (5) ///< Line Status Register +#define MSR (6) ///< Modem Status Register +#define SCR (7) ///< Scratch register + +/** @brief DLAB 1 */ +#define DLL (0) ///< Divisor Latch, LSB +#define DLM (1) ///< Divisor Latch, MSB +#define AFR (2) ///< Alternate Function register + +/** @brief + * Interrupt source definition via IIR + */ +#define MODEM_STATUS 0 +#define NO_MORE_INTR 1 +#define TRANSMITTER_HODING_REGISTER_EMPTY 2 +#define RECEIVER_DATA_AVAIL 4 +#define RECEIVER_ERROR 6 +#define CHARACTER_TIMEOUT_INDICATION 12 + +/** @brief + * Bits definition of IER + */ +#define RECEIVE_ENABLE 0x1 +#define TRANSMIT_ENABLE 0x2 +#define RECEIVER_LINE_ST_ENABLE 0x4 +#define MODEM_ENABLE 0x8 +#define INTERRUPT_DISABLE 0x0 + +/** @brief + * Bits definition of the Line Status Register (LSR) + */ +#define DR 0x01 ///< Data Ready +#define OE 0x02 ///< Overrun Error +#define PE 0x04 ///< Parity Error +#define FE 0x08 ///< Framing Error +#define BI 0x10 ///< Break Interrupt +#define THRE 0x20 ///< Transmitter Holding Register Empty +#define TEMT 0x40 ///< Transmitter Empty +#define ERFIFO 0x80 ///< Error receive Fifo + +/** @brief + * Bits definition of the MODEM Control Register (MCR) + */ +#define DTR 0x01 ///< Data Terminal Ready +#define RTS 0x02 ///< Request To Send +#define OUT_1 0x04 ///< Output 1, (reserved on COMPAQ I/O Board) +#define OUT_2 0x08 ///< Output 2, Enable Asynchronous Port Interrupts +#define LB 0x10 ///< Enable Internal Loop Back + +/** @brief + * Bits definition of the Line Control Register (LCR) + */ +#define CHR_5_BITS 0 +#define CHR_6_BITS 1 +#define CHR_7_BITS 2 +#define CHR_8_BITS 3 + +#define WL 0x03 ///< Word length mask +#define STB 0x04 ///< 1 Stop Bit, otherwise 2 Stop Bits +#define PEN 0x08 ///< Parity Enabled +#define EPS 0x10 ///< Even Parity Select, otherwise Odd +#define SP 0x20 ///< Stick Parity +#define BCB 0x40 ///< Break Control Bit +#define DLAB 0x80 ///< Enable Divisor Latch Access + +/** @brief + * Bits definition of the MODEM Status Register (MSR) + */ +#define DCTS 0x01 ///< Delta Clear To Send +#define DDSR 0x02 ///< Delta Data Set Ready +#define TERI 0x04 ///< Trailing Edge Ring Indicator +#define DDCD 0x08 ///< Delta Carrier Detect Indicator +#define CTS 0x10 ///< Clear To Send (when loop back is active) +#define DSR 0x20 ///< Data Set Ready (when loop back is active) +#define RI 0x40 ///< Ring Indicator (when loop back is active) +#define DCD 0x80 ///< Data Carrier Detect (when loop back is active) + +/** @brief + * Bits definition of the FIFO Control Register : WD16C552 or NS16550 + */ + +#define FIFO_CTRL 0x01 ///< Set to 1 permit access to other bits +#define FIFO_EN 0x01 ///< Enable the FIFO +#define XMIT_RESET 0x02 ///< Transmit FIFO Reset +#define RCV_RESET 0x04 ///< Receive FIFO Reset +#define FCR3 0x08 ///< do not understand manual! + +#define RECEIVE_FIFO_TRIGGER1 0x0 ///< trigger recieve interrupt after 1 byte +#define RECEIVE_FIFO_TRIGGER4 0x40 ///< trigger recieve interrupt after 4 byte +#define RECEIVE_FIFO_TRIGGER8 0x80 ///< trigger recieve interrupt after 8 byte +#define RECEIVE_FIFO_TRIGGER12 0xc0 ///< trigger recieve interrupt after 12 byte +#define TRIG_LEVEL 0xc0 ///< Mask for the trigger level + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSPUART_H */ diff --git a/bsps/i386/pc386/headers.am b/bsps/i386/pc386/headers.am new file mode 100644 index 0000000000..0109c11eed --- /dev/null +++ b/bsps/i386/pc386/headers.am @@ -0,0 +1,25 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/i386/pc386/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/i386/pc386/include/crt.h +include_HEADERS += ../../../../../../bsps/i386/pc386/include/edid.h +include_HEADERS += ../../../../../../bsps/i386/pc386/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/i386/pc386/include/bsp/bspimpl.h +include_bsp_HEADERS += ../../../../../../bsps/i386/pc386/include/bsp/exar17d15x.h +include_bsp_HEADERS += ../../../../../../bsps/i386/pc386/include/bsp/fb_default_mode.h +include_bsp_HEADERS += ../../../../../../bsps/i386/pc386/include/bsp/fb_vesa.h +include_bsp_HEADERS += ../../../../../../bsps/i386/pc386/include/bsp/rtd316.h +include_bsp_HEADERS += ../../../../../../bsps/i386/pc386/include/bsp/tblsizes.h +include_bsp_HEADERS += ../../../../../../bsps/i386/pc386/include/bsp/vbe3.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += ../../../../../../bsps/i386/pc386/include/rtems/kd.h +include_rtems_HEADERS += ../../../../../../bsps/i386/pc386/include/rtems/keyboard.h +include_rtems_HEADERS += ../../../../../../bsps/i386/pc386/include/rtems/ps2_drv.h +include_rtems_HEADERS += ../../../../../../bsps/i386/pc386/include/rtems/vgacons.h diff --git a/bsps/i386/pc386/include/bsp.h b/bsps/i386/pc386/include/bsp.h new file mode 100644 index 0000000000..4ff89527b2 --- /dev/null +++ b/bsps/i386/pc386/include/bsp.h @@ -0,0 +1,264 @@ +/** + * @file + * + * @ingroup i386_pc386 + * + * @brief Global BSP definitions. + */ + +/*-------------------------------------------------------------------------+ +| bsp.h v1.1 - PC386 BSP - 1997/08/07 ++--------------------------------------------------------------------------+ +| This include file contains definitions related to the PC386 BSP. ++--------------------------------------------------------------------------+ +| (C) Copyright 1997 - +| - NavIST Group - Real-Time Distributed Systems and Industrial Automation +| +| http://pandora.ist.utl.pt +| +| Instituto Superior Tecnico * Lisboa * PORTUGAL ++--------------------------------------------------------------------------+ +| Modified by Eric Valette the 20/05/98 in order to add definitions used +| to enhance video putchar capabilities. +| +| Copyright (C) 1998 valette@crf.canon.fr +| +| Canon Centre Recherche France. +| ++--------------------------------------------------------------------------+ +| Disclaimer: +| +| This file is provided "AS IS" without warranty of any kind, either +| expressed or implied. ++--------------------------------------------------------------------------+ +| This code is based on: +| bsp.h,v 1.5 1995/12/19 20:07:30 joel Exp - go32 BSP +| With the following copyright notice: +| ************************************************************************** +| * COPYRIGHT (c) 1989-1999. +| * On-Line Applications Research Corporation (OAR). +| * +| * The license and distribution terms for this file may be +| * found in the file LICENSE in this distribution or at +| * http://www.rtems.org/license/LICENSE. +| ************************************************************************** ++--------------------------------------------------------------------------*/ + +#ifndef LIBBSP_I386_PC386_BSP_H +#define LIBBSP_I386_PC386_BSP_H + +#ifndef ASM + +#include +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @degroup pc386_i386 PC386 Support + * + * @ingroup bsp_i386 + * + * @brief PC386 support. + */ + +#define BSP_HAS_FRAME_BUFFER 1 + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; + +/* app. may provide a routine (called _very_ early) to tell us + * which ports to use for printk / console. BSP provides a default + * implementation (weak alias) which does nothing (use BSP default + * ports). + */ +extern void +BSP_runtime_console_select(int *pPrintkPort, int *pConsolePort); + +extern int rtems_ne_driver_attach(struct rtems_bsdnet_ifconfig *, int); +#define BSP_NE2000_NETWORK_DRIVER_NAME "ne1" +#define BSP_NE2000_NETWORK_DRIVER_ATTACH rtems_ne_driver_attach + +extern int rtems_wd_driver_attach(struct rtems_bsdnet_ifconfig *, int); +#define BSP_WD8003_NETWORK_DRIVER_NAME "wd1" +#define BSP_WD8003_NETWORK_DRIVER_ATTACH rtems_wd_driver_attach + +extern int rtems_dec21140_driver_attach(struct rtems_bsdnet_ifconfig *, int); +#define BSP_DEC21140_NETWORK_DRIVER_NAME "dc1" +#define BSP_DEC21140_NETWORK_DRIVER_ATTACH rtems_dec21140_driver_attach + +extern int rtems_3c509_driver_attach(struct rtems_bsdnet_ifconfig *config); +#define BSP_3C509_NETWORK_DRIVER_NAME "3c1" +#define BSP_3C509_NETWORK_DRIVER_ATTACH rtems_3c509_driver_attach + +#ifndef RTEMS_BSP_NETWORK_DRIVER_NAME +#define RTEMS_BSP_NETWORK_DRIVER_NAME BSP_DEC21140_NETWORK_DRIVER_NAME +#endif + +#ifndef RTEMS_BSP_NETWORK_DRIVER_ATTACH +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_DEC21140_NETWORK_DRIVER_ATTACH +#endif + +/*-------------------------------------------------------------------------+ +| Constants ++--------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------+ +| Constants relating to the 8254 (or 8253) programmable interval timers. ++--------------------------------------------------------------------------*/ +#define IO_TIMER1 0x40 + /* Port address of the control port and timer channels */ +#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */ +#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */ +#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */ +#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */ +#define TIMER_SEL0 0x00 /* select counter 0 */ +#define TIMER_SEL1 0x40 /* select counter 1 */ +#define TIMER_SEL2 0x80 /* select counter 2 */ +#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ +#define TIMER_ONESHOT 0x02 /* mode 1, one shot */ +#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ +#define TIMER_SQWAVE 0x06 /* mode 3, square wave */ +#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ +#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ +#define TIMER_LATCH 0x00 /* latch counter for reading */ +#define TIMER_LSB 0x10 /* r/w counter LSB */ +#define TIMER_MSB 0x20 /* r/w counter MSB */ +#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ +#define TIMER_BCD 0x01 /* count in BCD */ +#define TIMER_RD_BACK 0xc0 /* Read Back Command */ + /* READ BACK command layout in the Command Register */ +#define RB_NOT_COUNT 0x40 /* Don't select counter latch */ +#define RB_NOT_STATUS 0x20 /* Don't select status latch */ +#define RB_COUNT_0 0x02 /* Counter 0 latch */ +#define RB_COUNT_1 0x04 /* Counter 1 latch */ +#define RB_COUNT_2 0x08 /* Counter 2 latch */ +#define RB_OUTPUT 0x80 /* Output of the counter is 1 */ + +#define TIMER_TICK 1193182 /* The internal tick rate in ticks per second */ + +#if defined( RTEMS_SMP ) + extern ISR_lock_Control rtems_i386_i8254_access_lock; +#endif + + +/*-------------------------------------------------------------------------+ +| Console Defines +| WARNING: These Values MUST match the order in +| Console_Configuration_Ports ++--------------------------------------------------------------------------*/ +#define BSP_CONSOLE_VGA 0 +#define BSP_CONSOLE_COM1 1 +#define BSP_CONSOLE_COM2 2 + +/*-------------------------------------------------------------------------+ +| Convert microseconds to ticks and ticks to microseconds. ++--------------------------------------------------------------------------*/ +#define US_TO_TICK(us) (((us)*105+44)/88) +#define TICK_TO_US(tk) (((tk)*88+52)/105) + +/*-------------------------------------------------------------------------+ +| External Variables. ++--------------------------------------------------------------------------*/ +extern interrupt_gate_descriptor Interrupt_descriptor_table[IDT_SIZE]; +extern segment_descriptors _Global_descriptor_table [GDT_SIZE]; + +/*-------------------------------------------------------------------------+ +| Function Prototypes. ++--------------------------------------------------------------------------*/ +void _IBMPC_initVideo(void); /* from 'outch.c' */ +void _IBMPC_outch (char); /* from 'outch.c' */ +char _IBMPC_inch (void); /* from 'inch.c' */ +char _IBMPC_inch_sleep (void); /* from 'inch.c' */ +int BSP_wait_polled_input(void); /* from 'inch.c' */ +int rtems_kbpoll( void ); /* from 'inch.c' */ +int getch( void ); /* from 'inch.c' */ +void add_to_queue( unsigned short b ); /* from 'inch.c' */ + +void Wait_X_ms(unsigned int timeToWait); /* from 'timer.c' */ +void Calibrate_loop_1ms(void); /* from 'timer.c' */ + +void rtems_irq_mngt_init(void); /* from 'irq_init.c' */ + +void Clock_driver_install_handler(void); /* from 'ckinit.c' */ +void Clock_driver_support_initialize_hardware(void); /* from 'ckinit.c' */ + +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +void kbd_reset_setup(char *str, int *ints); /* from 'pc_keyb.c' */ +size_t read_aux(char * buffer, size_t count); /* from 'ps2_mouse.c' */ + +bool bsp_get_serial_mouse_device( /* from 'serial_mouse.c' */ + const char **name, + const char **type +); + +void register_leds( /* from 'keyboard.c' */ + int console, + unsigned int led, + unsigned int *addr, + unsigned int mask +); + +/* Definitions for BSPConsolePort */ +#define BSP_CONSOLE_PORT_CONSOLE (-1) +#define BSP_CONSOLE_PORT_COM1 (BSP_UART_COM1) +#define BSP_CONSOLE_PORT_COM2 (BSP_UART_COM2) + +/* + * Command line. + */ +const char* bsp_cmdline(void); +const char* bsp_cmdline_arg(const char* arg); + +#if BSP_ENABLE_IDE +/* + * IDE command line parsing. + */ +void bsp_ide_cmdline_init(void); + +/* + * indicate, that BSP has IDE driver + */ +#define RTEMS_BSP_HAS_IDE_DRIVER +#endif + +/* GDB stub stuff */ +void init_remote_gdb( void ); +void i386_stub_glue_init(int uart); +void i386_stub_glue_init_breakin(void); +int i386_stub_glue_uart(void); +void breakpoint(void); + +#define BSP_MAXIMUM_DEVICES 6 + +/* + * Debug helper methods + */ +typedef __FILE FILE; +uint32_t BSP_irq_count_dump(FILE *f); + +/* + * Prototypes just called from .S files. This lets the .S file include + * bsp.h just to establish the dependency. + */ +void raw_idt_notify(void); +void C_dispatch_isr(int vector); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif /* _BSP_H */ diff --git a/bsps/i386/pc386/include/bsp/bspimpl.h b/bsps/i386/pc386/include/bsp/bspimpl.h new file mode 100644 index 0000000000..314fb91eb9 --- /dev/null +++ b/bsps/i386/pc386/include/bsp/bspimpl.h @@ -0,0 +1,47 @@ +/** + * @file + * + * BSP specific helpers + */ + +/* + * COPYRIGHT (c) 2016. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __BSPIMPL_h +#define __BSPIMPL_h + +#include + +/* + * PCI Support Methods + */ +const pci_config_access_functions *pci_bios_initialize(void); +const pci_config_access_functions *pci_io_initialize(void); + +/* + * Helper to parse boot command line arguments related to the console driver + */ +void pc386_parse_console_arguments(void); + +/* + * Helper to parse boot command line arguments related to gdb + */ +void pc386_parse_gdb_arguments(void); + +/* + * Dynamically probe for Legacy UARTS + */ +void legacy_uart_probe(void); + +/* + * Dynamically probe for PCI UARTS + */ +void pci_uart_probe(void); + +#endif diff --git a/bsps/i386/pc386/include/bsp/exar17d15x.h b/bsps/i386/pc386/include/bsp/exar17d15x.h new file mode 100644 index 0000000000..9e1194ffec --- /dev/null +++ b/bsps/i386/pc386/include/bsp/exar17d15x.h @@ -0,0 +1,55 @@ +/** + * @file + * + * @ingroup i386_pc386 + * + * @brief Exar Multiport PCI UART interface. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _BSP_EXAR17D15X__h +#define _BSP_EXAR17D15X__h + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * This macro defines the standard device driver table entry for + * a console device driver. + */ +#define EXAR17D15X_DRIVER_TABLE_ENTRY \ + { exar17d15x_initialize, NULL, NULL, NULL, NULL, NULL } + +/** + * @brief Exar 17D15x Initialization Entry Point + * + * This method initializes the Exar XR17D15x device driver. + * + * @param[in] major is the device driver major number + * @param[in] minor is the device driver minor number + * @param[in] arg is the parameters to this call + * + * @return This method returns RTEMS_SUCCESSFUL when + * the device driver is successfully initialized. + */ +rtems_device_driver exar17d15x_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/i386/pc386/include/bsp/fb_default_mode.h b/bsps/i386/pc386/include/bsp/fb_default_mode.h new file mode 100644 index 0000000000..948ffee5b6 --- /dev/null +++ b/bsps/i386/pc386/include/bsp/fb_default_mode.h @@ -0,0 +1,25 @@ +/** + * @file fb_default_mode.h + * + * @ingroup i386_pc386 + * + * @brief Variable for the definition of the default graphical mode to be + * initialized. + */ + +/* + * @brief Allows to enable initialization of specific framebuffer driver (e.g. + * VESA real mode) from an application by setting the value of this variable + * to non null value in user's module. The value of this variable will be then + * updated when linked with an application's object. + * + * Further the value should point to string in the following format: + * "x[-]" - e.g. "1024x768-32" + * "auto" - select the graphic mode automatically + * "none" / "off" - do not initialize the driver + * the given parameters are used if applicable. + * + * Command line argument "--video=" has priority over this string if + * it is read/implemented by the driver. + */ +extern const char * const rtems_fb_default_mode; diff --git a/bsps/i386/pc386/include/bsp/fb_vesa.h b/bsps/i386/pc386/include/bsp/fb_vesa.h new file mode 100644 index 0000000000..d8bfd1bcb4 --- /dev/null +++ b/bsps/i386/pc386/include/bsp/fb_vesa.h @@ -0,0 +1,132 @@ +/** + * @file fb_vesa.h + * + * @ingroup i386_pc386 + * + * @brief Headers specific for framebuffer drivers utilizing VESA VBE. + */ + +/* + * Copyright (C) 2014 Jan Doležal (dolezj21@fel.cvut.cz) + * CTU in Prague. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include + +#ifndef _FB_VESA_H +#define _FB_VESA_H + +#ifndef ASM /* ASM */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/* ----- Prototypes ----- */ + +/** + * @brief Returns information about graphic's controller in the \p info_block + * structure. + * + * @param[out] info_block pointer to the struct to be filled with + * controller information + * @param[in] queried_VBE_Version if >0x200 then video bios is asked to fill in + * parameters which appeared with second version + * of VBE. + * @retval ax register content as defined in VBE RETURN STATUS paragraph + * @retval -1 error calling graphical bios + */ +uint32_t VBE_controller_information ( + VBE_vbe_info_block *info_block, + uint16_t queried_VBE_Version +); + +/** + * @brief Fills structure \p info_block with informations about selected mode in + * \p mode_number variable. + * + * @param[out] info_block pointer to the struct to be filled with + * mode information + * @param[in] mode_number detailes of this mode to be filled + * @retval ax register content as defined in VBE RETURN STATUS paragraph + * @retval -1 error calling graphical bios + */ +uint32_t VBE_mode_information ( + VBE_mode_info_block *info_block, + uint16_t mode_number +); + +/** + * @brief Sets graphics mode selected. If mode has refreshRateCtrl bit set, than + * the \p info_block must be filled accordingly. + * + * @param[in] mode_number number of mode to be set + * @param[in] info_block pointer to struct containing refresh rate control info + * @retval ax register content as defined in VBE RETURN STATUS paragraph + * @retval -1 error calling graphical bios + */ +uint32_t VBE_set_mode ( + uint16_t mode_number, + VBE_CRTC_info_block *info_block +); + +/** + * @brief Get currently set mode number. + * + * @param[out] mode_number variable to be filled with current mode number + * @retval ax register content as defined in VBE RETURN STATUS paragraph + * @retval -1 error calling graphical bios + */ +uint32_t VBE_current_mode ( + uint16_t *mode_number +); + +/** + * @brief Gets information about display data channel implemented in the + * graphic's controller. + * + * @param[in] controller_unit_number + * @param[out] seconds_to_transfer_EDID_block approximate time to transfer one + * EDID block rounded up to seconds + * @param[out] DDC_level_supported contains DDC version supported and + * screen blanking state during transfer + * @retval ax register content as defined in VBE RETURN STATUS paragraph + * @retval -1 error calling graphical bios + */ +uint32_t VBE_report_DDC_capabilities ( + uint16_t controller_unit_number, + uint8_t *seconds_to_transfer_EDID_block, + uint8_t *DDC_level_supported +); + +/** + * @brief Reads selected EDID block from display attached to controller's + * interface. + * + * @param[in] controller_unit_number + * @param[in] EDID_block_number block no. to be read from the display + * @param[out] buffer place to store block fetched from the display + * @retval ax register content as defined in VBE RETURN STATUS paragraph + * @retval -1 error calling graphical bios + */ +uint32_t VBE_read_EDID ( + uint16_t controller_unit_number, + uint16_t EDID_block_number, + EDID_edid1 *buffer +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* _FB_VESA_H */ diff --git a/bsps/i386/pc386/include/bsp/rtd316.h b/bsps/i386/pc386/include/bsp/rtd316.h new file mode 100644 index 0000000000..aabad2c263 --- /dev/null +++ b/bsps/i386/pc386/include/bsp/rtd316.h @@ -0,0 +1,77 @@ +/** + * @file + * + * @ingroup i386_pc386 + * + * @brief RTD316 driver interface defintions. + */ + +/* + * COPYRIGHT (c) 1989-2014. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _BSP_RTD_316_h +#define _BSP_RTD_316_h + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * This macro defines the standard device driver table entry for + * a console device driver. + */ +#define RTD316_DRIVER_TABLE_ENTRY \ + { rtd316_initialize, NULL, NULL, NULL, NULL, NULL } + +/** + * @brief RTD316 Initialization Entry Point + * + * This method initializes the RTD316 device driver. + * + * @param[in] major is the device driver major number + * @param[in] minor is the device driver minor number + * @param[in] arg is the parameters to this call + * + * @return This method returns RTEMS_SUCCESSFUL when + * the device driver is successfully initialized. + */ +rtems_device_driver rtd316_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +/** + * @brief RTD316 Obtain Register Helper + * + * This method is used to read registers on the RTD316. + * + * @param[in] addr is the base address + * @param[in] reg is the register number + * + * @return This method returns the value of the register. + */ +uint8_t rtd316_com_get_register(uint32_t addr, uint8_t reg); + +/** + * @brief RTD316 Set Register Helper + * + * This method is used to set registers on the RTD316. + * + * @param[in] addr is the base address + * @param[in] reg is the register number + */ +void rtd316_com_set_register(uint32_t addr,uint8_t reg, uint8_t val); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/i386/pc386/include/bsp/tblsizes.h b/bsps/i386/pc386/include/bsp/tblsizes.h new file mode 100644 index 0000000000..cea8619c8f --- /dev/null +++ b/bsps/i386/pc386/include/bsp/tblsizes.h @@ -0,0 +1,24 @@ +/** + * @file + * + * @ingroup i386_pc386 + * + * @brief Sizes of Global and Interrupt descriptor tables. + */ + +/* + * This header file is also used in assembler modules. + * + * Copyright (C) 2014 Jan Doležal (dolezj21@fel.cvut.cz) + * CTU in Prague. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +#define IDT_SIZE (256) +#define NUM_SYSTEM_GDT_DESCRIPTORS 4 +#define GDT_SIZE (NUM_SYSTEM_GDT_DESCRIPTORS + NUM_APP_DRV_GDT_DESCRIPTORS) diff --git a/bsps/i386/pc386/include/bsp/vbe3.h b/bsps/i386/pc386/include/bsp/vbe3.h new file mode 100644 index 0000000000..b62ab6f3ac --- /dev/null +++ b/bsps/i386/pc386/include/bsp/vbe3.h @@ -0,0 +1,619 @@ +/** + * @file vbe3.h + * + * @ingroup i386_pc386 + * + * @brief VESA Bios Extension definitions. + * + * This file contains definitions for constants related to VBE. + * More information can be found at + * . + * VESA public standards may be found at + * . + */ + +/* + * Copyright (C) 2014 Jan Doležal (dolezj21@fel.cvut.cz) + * CTU in Prague. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _VBE_H +#define _VBE_H + +#ifndef ASM /* ASM */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include + +/* VESA BIOS EXTENSION (VBE) Core functions Standard + Version: 3.0 Date: September 16, 1998 */ + +/** AL == 4Fh: Function is supported \n + * AL != 4Fh: Function is not supported */ +#define VBE_functionSupported 0x4F +/** AH == 00h: Function call successful */ +#define VBE_callSuccessful 0x00 +/** AH == 01h: Function call failed */ +#define VBE_callFailed 0x01 +/** AH == 02h: Function is not supported in the current hardware configuration*/ +#define VBE_notSupportedInCurHWConf 0x02 +/** AH == 03h: Function call invalid in current video mode */ +#define VBE_callInvalid 0x03 + +/* VBE Mode Numbers */ +/** D0-D8 = Mode number */ +#define VBE_modeNumberMask 0x01FF +#define VBE_modeNumberShift 0x00 +/** If D8 == 0, this is not a VESA defined VBE mode \n + If D8 == 1, this is a VESA defined VBE mode */ +#define VBE_VESAmodeMask 0x0100 +#define VBE_VESAmodeShift 0x08 +/* D9-D10 = Reserved by VESA for future expansion (= 0) */ +/** If D11 == 0, Use current BIOS default refresh rate \n + If D11 == 1, Use user specified CRTC values for refresh rate */ +#define VBE_refreshRateCtrlMask 0x0800 +#define VBE_refreshRateCtrlShift 0x0B +/* D12-13 = Reserved for VBE/AF (must be 0) */ +/** If D14 == 0, Use Banked/Windowed Frame Buffer \n + If D14 == 1, Use Linear/Flat Frame Buffer */ +#define VBE_linearFlatFrameBufMask 0x4000 +#define VBE_linearFlatFrameBufShift 0x0E +/** If D15 == 0, Clear display memory \n + If D15 == 1, Preserve display memory */ +#define VBE_preserveDispMemMask 0x8000 +#define VBE_preserveDispMemShift 0x0F + +/* Graphics modes */ +/** 15-bit mode, Resolution: 640x400, Colors: 256 */ +#define VBE_R640x400C256 0x100 +/** 15-bit mode, Resolution: 640x480, Colors: 256 */ +#define VBE_R640x480C256 0x101 +/** 15-bit mode, Resolution: 800x600, Colors: 16 */ +#define VBE_R800x600C16 0x102 +/** 7-bit mode, Resolution: 800x600, Colors: 16 */ +#define VBE_b7R800x600C16 0x6A +/** 15-bit mode, Resolution: 800x600, Colors: 256 */ +#define VBE_R800x600C256 0x103 +/** 15-bit mode, Resolution: 1024x768, Colors: 16 */ +#define VBE_R1024x768C16 0x104 +/** 15-bit mode, Resolution: 1024x768, Colors: 256 */ +#define VBE_R1024x768C256 0x105 +/** 15-bit mode, Resolution: 1280x1024, Colors: 16 */ +#define VBE_R1280x1024C16 0x106 +/** 15-bit mode, Resolution: 1280x1024, Colors: 256 */ +#define VBE_R1280x1024C256 0x107 +/** 15-bit mode, Resolution: 320x200, Colors: 32K (1:5:5:5) */ +#define VBE_R320x200C32K 0x10D +/** 15-bit mode, Resolution: 320x200, Colors: 64K (5:6:5) */ +#define VBE_R320x200C64K 0x10E +/** 15-bit mode, Resolution: 320x200, Colors: 16.8M (8:8:8) */ +#define VBE_R320x200C17M 0x10F +/** 15-bit mode, Resolution: 640x480, Colors: 32K (1:5:5:5) */ +#define VBE_R640x480C32K 0x110 +/** 15-bit mode, Resolution: 640x480, Colors: 64K (5:6:5) */ +#define VBE_R640x480C64K 0x111 +/** 15-bit mode, Resolution: 640x480, Colors: 16.8M (8:8:8) */ +#define VBE_R640x480C17M 0x112 +/** 15-bit mode, Resolution: 800x600, Colors: 32K (1:5:5:5) */ +#define VBE_R800x600C32K 0x113 +/** 15-bit mode, Resolution: 800x600, Colors: 64K (5:6:5) */ +#define VBE_R800x600C64K 0x114 +/** 15-bit mode, Resolution: 800x600, Colors: 16.8M (8:8:8) */ +#define VBE_R800x600C17M 0x115 +/** 15-bit mode, Resolution: 1024x768, Colors: 32K (1:5:5:5) */ +#define VBE_R1024x768C32K 0x116 +/** 15-bit mode, Resolution: 1024x768, Colors: 64K (5:6:5) */ +#define VBE_R1024x768C64K 0x117 +/** 15-bit mode, Resolution: 1024x768, Colors: 16.8M (8:8:8) */ +#define VBE_R1024x768C17M 0x118 +/** 15-bit mode, Resolution: 1280x1024, Colors: 32K (1:5:5:5) */ +#define VBE_R1280x1024C32K 0x119 +/** 15-bit mode, Resolution: 1280x1024, Colors: 64K (5:6:5) */ +#define VBE_R1280x1024C64K 0x11A +/** 15-bit mode, Resolution: 1280x1024, Colors: 16.8M (8:8:8) */ +#define VBE_R1280x1024C17M 0x11B +#define VBE_SpecialMode 0x81FF + +/* Text modes */ +#define VBE_C80R60 0x108 /**< 15-bit mode, Columns: 80, Rows: 60 */ +#define VBE_C132R25 0x109 /**< 15-bit mode, Columns: 132, Rows: 25 */ +#define VBE_C132R43 0x10A /**< 15-bit mode, Columns: 132, Rows: 43 */ +#define VBE_C132R50 0x10B /**< 15-bit mode, Columns: 132, Rows: 50 */ +#define VBE_C132R60 0x10C /**< 15-bit mode, Columns: 132, Rows: 60 */ + +/* VBE function numbers - passed in AX register */ +/** VBE function - Return VBE Controller Information */ +#define VBE_RetVBEConInf 0x4F00 +/** VBE function - Return VBE Mode Information */ +#define VBE_RetVBEModInf 0x4F01 +/** VBE function - Set VBE Mode */ +#define VBE_SetVBEMod 0x4F02 +/** VBE function - Return Current VBE Mode */ +#define VBE_RetCurVBEMod 0x4F03 +/** VBE function - Save/Restore State */ +#define VBE_SavResSta 0x4F04 +/** VBE function - Display Window Control */ +#define VBE_DisWinCon 0x4F05 +/** VBE function - Set/Get Logical Scan Line Length */ +#define VBE_SetGetLogScaLinLen 0x4F06 +/** VBE function - Set/Get Display Start */ +#define VBE_SetGetDisSta 0x4F07 +/** VBE function - Set/Get DAC Palette Format */ +#define VBE_SetGetDACPalFor 0x4F08 +/** VBE function - Set/Get Palette Data */ +#define VBE_SetGetPalDat 0x4F09 +/** VBE function - Return VBE Protected Mode Interface */ +#define VBE_RetVBEProModInt 0x4F0A +/** VBE function - Get/Set pixel clock */ +#define VBE_GetSetpixclo 0x4F0B +/** VBE function - Power Management Extensions (PM) */ +#define VBE_PowManExt 0x4F10 +/** VBE function - Flat Panel Interface Extensions (FP) */ +#define VBE_FlaPanIntExt 0x4F11 +/** VBE function - Audio Interface Extensions (AI) */ +#define VBE_AudIntExt 0x4F13 +/** VBE function - OEM Extensions */ +#define VBE_OEMExt 0x4F14 +/** VBE function - Display Data Channel (DDC), Serial Control Interface (SCI) */ +#define VBE_DisDatCha 0x4F15 + +/* VBE subfunction numbers - passed in BL register */ +#define VBE_RetVBESupSpeInf 0x00 /**< Return VBE Supplemental + * Specification Information */ +/* *** Structures *** */ +/** + * @brief Far pointer as defined by VBE standard. + */ +typedef struct { + /** @brief Offset to segment described by \a selector. */ + uint16_t offset; + /** @brief Selector or Segment depending on whether this is used from 16bit + protected mode or from real mode. */ + uint16_t selector; +} RTEMS_PACKED VBE_far_pointer; + +/** + * @brief Protected mode info block as defined by VBE standard. + */ +typedef struct { + /** PM Info Block Signature */ + uint8_t Signature[4]; + /** Offset of PM entry point within BIOS */ + uint16_t EntryPoint; + /** Offset of PM initialization entry point */ + uint16_t PMInitialize; + /** Selector to BIOS data area emulation block */ + uint16_t BIOSDataSel; + /** Selector to access A0000h physical memmory */ + uint16_t A0000Sel; + /** Selector to access B0000h physical memmory */ + uint16_t B0000Sel; + /** Selector to access B8000h physical memmory */ + uint16_t B8000Sel; + /** Selector to access code segment as data */ + uint16_t CodeSegSel; + /** Set to 1 when in protected mode */ + uint8_t InProtectMode; + /** Checksum byte for structure. Sum over all structure bytes gives 0. */ + uint8_t Checksum; +} RTEMS_PACKED VBE_protected_mode_info_block; + +/** General VBE signature */ +#define VBE_SIGNATURE "VESA" +/** Signature for VBE 2.0 and higher */ +#define VBE20plus_SIGNATURE "VBE2" +/** for STUB see VBE CORE FUNCTIONS VERSION 3.0 - Appendix 1 */ +#define VBE_STUB_VideoModeList 0xFFFF +#define VBE_END_OF_VideoModeList 0xFFFF +/** + * @brief Information about VBE implementation. + */ +typedef struct { + /** VBE Signature */ + uint8_t VbeSignature[4]; + /** VBE Version */ + uint16_t VbeVersion; + /** VBE_far_pointer to OEM String */ + uint8_t *OemStringPtr; + /** Capabilities of graphics controller */ + uint8_t Capabilities[4]; + /** VBE_far_pointer to VideoModeList */ + uint32_t *VideoModePtr; + /** Number of 64kb memory blocks */ + uint16_t TotalMemory; + /* Added for VBE 2.0+ */ + /** VBE implementation Software revision */ + uint16_t OemSoftwareRev; + /** VBE_far_pointer to Vendor Name String */ + uint8_t *OemVendorNamePtr; + /** VBE_far_pointer to Product Name String */ + uint8_t *OemProductNamePtr; + /** VBE_far_pointer to Product Revision String */ + uint8_t *OemProductRevPtr; + /** Reserved for VBE implementation scratch */ + uint8_t Reserved[222]; + /** Data Area for OEM Strings */ + uint8_t OemData[256]; +} RTEMS_PACKED VBE_vbe_info_block; + +/** + * @brief Describes graphic's mode parameter. + */ +typedef struct { + /* Mandatory information for all VBE revisions */ + /** mode attributes */ + uint16_t ModeAttributes; + /** window A attributes */ + uint8_t WinAAttributes; + /** window B attributes */ + uint8_t WinBAttributes; + /** window granularity */ + uint16_t WinGranularity; + /** window size */ + uint16_t WinSize; + /** window A start segment */ + uint16_t WinASegment; + /** window B start segment */ + uint16_t WinBSegment; + /** real mode pointer to window function */ + uint32_t *WinFuncPtr; + /** bytes per scan line */ + uint16_t BytesPerScanLine; + /* Mandatory information for VBE 1.2 and above */ + /** horizontal resolution in px or chars */ + uint16_t XResolution; + /** vertical resolution in px or chars */ + uint16_t YResolution; + /** character cell width in pixels */ + uint8_t XCharSize; + /** character cell height in pixels */ + uint8_t YCharSize; + /** number of memory planes */ + uint8_t NumberOfPlanes; + /** bits per pixel */ + uint8_t BitsPerPixel; + /** number of banks */ + uint8_t NumberOfBanks; + /** memory model type */ + uint8_t MemoryModel; + /** bank size in KB */ + uint8_t BankSize; + /** number of images */ + uint8_t NumberOfImagePages; + /** reserved for page function */ + uint8_t Reserved0; + /* Direct Color fields (required for direct/6 and YUV/7 memory models) */ + /** size of direct color red mask in bits */ + uint8_t RedMaskSize; + /** bit position of lsb of red mask */ + uint8_t RedFieldPosition; + /** size of direct color green mask in b */ + uint8_t GreenMaskSize; + /** bit position of lsb of green mask */ + uint8_t GreenFieldPosition; + /** size of direct color blue mask in b */ + uint8_t BlueMaskSize; + /** bit position of lsb of blue mask */ + uint8_t BlueFieldPosition; + /** size of direct color reserved mask */ + uint8_t RsvdMaskSize; + /** bit position of lsb of reserved mask */ + uint8_t RsvdFieldPosition; + /** direct color mode attributes */ + uint8_t DirectColorModeInfo; + /* Mandatory information for VBE 2.0 and above */ + /** physical address for flat memory frame buffer */ + uint32_t *PhysBasePtr; + /** Reserved - always set to 0 */ + uint32_t Reserved1; + /** Reserved - always set to 0 */ + uint16_t Reserved2; + /* Mandatory information for VBE 3.0 and above */ + /** bytes per scan line for linear modes */ + uint16_t LinBytesPerScanLine; + /** number of images for banked modes */ + uint8_t BnkNumberOfImagePages; + /** number of images for linear modes */ + uint8_t LinNumberOfImagePages; + /* linear modes */ + /** size of direct color red mask */ + uint8_t LinRedMaskSize; + /** bit position of lsb of red mask */ + uint8_t LinRedFieldPosition; + /** size of direct color green mask */ + uint8_t LinGreenMaskSize; + /** bit position of lsb of green mask */ + uint8_t LinGreenFieldPosition; + /** size of direct color blue mask */ + uint8_t LinBlueMaskSize; + /** bit position of lsb of blue mask */ + uint8_t LinBlueFieldPosition; + /** size of direct color reserved mask */ + uint8_t LinRsvdMaskSize; + /** bit position of lsb of reserved mask */ + uint8_t LinRsvdFieldPosition; + /** maximum pixel clock (in Hz) for graphics mode */ + uint32_t MaxPixelClock; + /** remainder of VBE_mode_info_block */ + uint8_t Reserved3[189]; +} RTEMS_PACKED VBE_mode_info_block; + +/** + * @brief Describes monitor synchronization. + */ +typedef struct { + /** Horizontal total in pixels */ + uint16_t HorizontalTotal; + /** Horizontal sync start in pixels */ + uint16_t HorizontalSyncStart; + /** Horizontal sync end in pixels */ + uint16_t HorizontalSyncEnd; + /** Vertical total in lines */ + uint16_t VerticalTotal; + /** Vertical sync start in lines */ + uint16_t VerticalSyncStart; + /** Vertical sync end in lines */ + uint16_t VerticalSyncEnd; + /** Flags (Interlaced, Double Scan etc) */ + uint8_t Flags; + /** Pixel clock in units of Hz */ + uint32_t PixelClock; + /** Refresh rate in units of 0.01 Hz */ + uint16_t RefreshRate; + /** remainder of VBE_mode_info_block */ + uint8_t Reserved[40]; +} RTEMS_PACKED VBE_CRTC_info_block; + +/** + * @brief Describes palette entry. + */ +typedef struct { + /** Blue channel value (6 or 8 bits) */ + uint8_t Blue; + /** Green channel value (6 or 8 bits) */ + uint8_t Green; + /** Red channel value(6 or 8 bits) */ + uint8_t Red; + /** DWORD alignment byte (unused) */ + uint8_t Alignment; +} RTEMS_PACKED VBE_palette_entry; + +/** + * @brief Supplemental VBE info block. + */ +typedef struct { + /** Supplemental VBE Signature */ + uint8_t SupVbeSignature[7]; + /** Supplemental VBE Version */ + uint16_t SupVbeVersion; + /** Bitfield of supported subfunctions */ + uint8_t SupVbeSubFunc[8]; + /** OEM Software revision */ + uint16_t OemSoftwareRev; + /** VBE_far_pointer to Vendor Name String */ + uint8_t *OemVendorNamePtr; + /** VBE_far_pointer to Product Name String */ + uint8_t *OemProductNamePtr; + /** VBE_far_pointer to Product Revision String */ + uint8_t *OemProductRevPtr; + /** VBE_far_pointer to OEM String */ + uint8_t *OemStringPtr; + /** Reserved for description strings and future expansion */ + uint8_t Reserved[221]; +} RTEMS_PACKED VBE_supplemental_vbe_info_block; + +/* VBE_vbe_info_block Capabilities */ +/** VBE Info Block - Capabilities\n + D0 = 0 DAC is fixed width, with 6 bits per primary color \n + D0 = 1 DAC width is switchable to 8 bits per primary color */ +#define VBE_DACswitchableMask 0x0001 +/** VBE Info Block - Capabilities\n + D1 = 0 Controller is VGA compatible \n + D1 = 1 Controller is not VGA compatible */ +#define VBE_notVGAcompatibleMask 0x0002 +/** VBE Info Block - Capabilities\n + D2 = 0 Normal RAMDAC operation \n + D2 = 1 When programming large blocks of information to the RAMDAC, + use the blank bit in Function 09h. */ +#define VBE_specialRAMDACopMask 0x0004 +/** VBE Info Block - Capabilities\n + D3 = 0 No hardware stereoscopic signaling support \n + D3 = 1 Hardware stereoscopic signaling supported by controller */ +#define VBE_hwStereoscopicMask 0x0008 +/** VBE Info Block - Capabilities\n + D4 = 0 Stereo signaling supported via external VESA stereo connector \n + D4 = 1 Stereo signaling supported via VESA EVC connector */ +#define VBE_supportEVCconnMask 0x0010 +/* D5-31 = Reserved */ + +/* VBE_mode_info_block ModeAttributes */ +/** Mode Info Block - Mode Attributes\n + D0 = Mode supported by hardware configuration. + 0 = Mode not supported in hardware\n + 1 = Mode supported in hardware */ +#define VBE_modSupInHWMask 0x0001 +/* D1 = 1 (Reserved) */ +/** Mode Info Block - Mode Attributes\n + D2 = TTY Output functions supported by BIOS. + 0 = TTY Output functions not supported by BIOS\n + 1 = TTY Output functions supported by BIOS */ +#define VBE_TTYOutSupByBIOSMask 0x0004 +/** Mode Info Block - Mode Attributes\n + D3 = Monochrome/color mode (see note below). + 0 = Monochrome mode\n + 1 = Color mode */ +#define VBE_ColorModeMask 0x0008 +/** Mode Info Block - Mode Attributes\n + D4 = Mode type. + 0 = Text mode\n + 1 = Graphics mode */ +#define VBE_GraphicsModeMask 0x0010 +/** Mode Info Block - Mode Attributes\n + D5 = VGA compatible mode. + 0 = Yes\n + 1 = No */ +#define VBE_VGACompModeMask 0x0020 +/** Mode Info Block - Mode Attributes\n + D6 = VGA compatible windowed memory mode is available. + 0 = Yes\n + 1 = No */ +#define VBE_VGACompWinMemModeMask 0x0040 +/** Mode Info Block - Mode Attributes\n + D7 = Linear frame buffer mode is available. + 0 = No\n + 1 = Yes */ +#define VBE_LinFraBufModeAvaiMask 0x0080 +/** Mode Info Block - Mode Attributes\n + D8 = Double scan mode is available. + 0 = No\n + 1 = Yes */ +#define VBE_DblScnModeAvaiMask 0x0100 +/** Mode Info Block - Mode Attributes\n + D9 = Interlaced mode is available. + 0 = No\n + 1 = Yes */ +#define VBE_InterlModeAvaiMask 0x0200 +/** Mode Info Block - Mode Attributes\n + D10 = Hardware triple buffering support. + 0 = No\n + 1 = Yes */ +#define VBE_HWTripBufSupMask 0x0400 +/** Mode Info Block - Mode Attributes\n + D11 = Hardware stereoscopic display support. + 0 = No\n + 1 = Yes */ +#define VBE_HWSterDispSupMask 0x0800 +/** Mode Info Block - Mode Attributes\n + D12 = Dual display start address support. + 0 = No\n + 1 = Yes */ +#define VBE_DualDispStAdrSupMask 0x1000 +/* D13-D15 = Reserved */ + +/* VBE_mode_info_block WinXAttributes */ +/** D0 = Relocatable window(s) supported. + 0 = Single non-relocatable window only\n + 1 = Relocatable window(s) are supported */ +#define VBE_RelocWinSupMask 0x01 +/** D1 = Window readable. + 0 = Window is not readable\n + 1 = Window is readable */ +#define VBE_WinReadableMask 0x02 +/** D2 = Window writeable. + 0 = Window is not writeable\n + 1 = Window is writeable */ +#define VBE_WinWritableMask 0x04 +/* D3-D7 = Reserved */ + +/* VBE_mode_info_block MemoryModel */ +#define VBE_TextMode 0x00 +#define VBE_CGAGraphics 0x01 +#define VBE_HerculesGraphics 0x02 +#define VBE_Planar 0x03 +#define VBE_PackedPixel 0x04 +#define VBE_NonChain4Color256 0x05 +#define VBE_DirectColor 0x06 +#define VBE_YUV 0x07 + /* 0x08-0x0F Reserved, to be defined by VESA */ + /* 0x10-0xFF To be defined by OEM */ + +/* VBE_mode_info_block DirectColorModeInfo */ +/** D0 = Color ramp is fixed/programmable. + 0 = Color ramp is fixed\n + 1 = Color ramp is programmable */ +#define VBE_ColRampProgMask 0x01 +/** D1 = Bits in Rsvd field are usable/reserved. + 0 = Bits in Rsvd field are reserved\n + 1 = Bits in Rsvd field are usable by the application */ +#define VBE_RsvdBitsUsableMask 0x02 + +/* VBE_CRTC_info_block Flags */ +/** CRTC Info Block - Flags\n + D0 = Double Scan Mode Enable. + 0 = Graphics mode is not double scanned\n + 1 = Graphics mode is double scanned */ +#define VBE_GrModeDblScanMask 0x01 +/** CRTC Info Block - Flags\n + D1 = Interlaced Mode Enable. + 0 = Graphics mode is non-interlaced\n + 1 = Graphics mode is interlaced */ +#define VBE_GrModeInterlMask 0x02 +/** CRTC Info Block - Flags\n + D2 = Horizontal sync polarity. + 0 = Horizontal sync polarity is positive (+)\n + 1 = Horizontal sync polarity is negative (-) */ +#define VBE_HorSncPolNegMask 0x04 +/** CRTC Info Block - Flags\n + D3 = Vertical sync polarity. + 0 = Vertical sync polarity is positive (+)\n + 1 = Vertical sync polarity is negative (-) */ +#define VBE_VerSncPolNegMask 0x08 + + +/* VESA BIOS Extensions/Display Data Channel Standard + Version: 1.1 November 18, 1999 */ + +/* VBE/DDC subfunction numbers - passed in BL register */ +/** VBE/DDC subfunction - Report VBE/DDC Capabilities */ +#define VBEDDC_Capabilities 0x0 +/** VBE/DDC subfunction - Read EDID */ +#define VBEDDC_ReadEDID 0x1 + +/* DDC Capabilities */ +/* DDC level supported - returned in BL register */ +/** 0 - DDC1 not supported; 1 - DDC1 supported */ +#define VBEDDC_1SupportedMask 0x1 +/** 0 - DDC2 not supported; 1 - DDC2 supported */ +#define VBEDDC_2SupportedMask 0x2 +/** 0 - Screen not blanked during data transfer\n + 1 - Screen blanked during data transfer */ +#define VBEDDC_scrBlnkDatTrMs 0x4 + + +/* VESA BIOS Extensions/Serial Control Interface Standard + Version: 1.0 Revision: 2 Date: July 2, 1997 */ + +/* VBE/SCI subfunction numbers - passed in BL register */ +/** VBE/SCI subfunction - Report VBE/SCI Capabilities */ +#define VBESCI_ReportCapabil 0x10 +/** VBE/SCI subfunction - Begin SCL/SDA control */ +#define VBESCI_BegSCLSDACtrl 0x11 +/** VBE/SCI subfunction - End SCL/SDA control */ +#define VBESCI_EndSCLSDACtrl 0x12 +/** VBE/SCI subfunction - Write SCL clock line */ +#define VBESCI_WrtSCLClkLine 0x13 +/** VBE/SCI subfunction - Write SDA data line */ +#define VBESCI_WrtSDADatLine 0x14 +/** VBE/SCI subfunction - Read SCL clock line */ +#define VBESCI_RdySCLClkLine 0x15 +/** VBE/SCI subfunction - Read SDA data line */ +#define VBESCI_RdySDADatLine 0x16 + +/* SCI Capabilities */ +/* I2C level supported - returned in BL register */ +/** Can write to SCL clock line */ +#define VBESCI_capSCLwrtMask 0x1 +/** Can write to SDA data line */ +#define VBESCI_capSDAwrtMask 0x2 +/** Can read from SCL clock line */ +#define VBESCI_capSCLrdyMask 0x4 +/** Can read from SDA data line */ +#define VBESCI_capSDArdyMask 0x8 + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* _VBE_H */ diff --git a/bsps/i386/pc386/include/crt.h b/bsps/i386/pc386/include/crt.h new file mode 100644 index 0000000000..ba0534a5aa --- /dev/null +++ b/bsps/i386/pc386/include/crt.h @@ -0,0 +1,94 @@ +/** + * @file + * + * @ingroup i386_pc386 + * + * @brief CRT controller definitions. + */ + +/* + * crt.h - This file contains definitions for constants related to PC console. + * More information can be found at + * + * + * Copyright (C) 1998 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _CRT_H +#define _CRT_H + +/* + * Bitmap video origins in text mode. + */ + + /* In monochrome */ +#define V_MONO 0xb0000 + /* In color */ +#define V_COLOR 0xb8000 + +/* + * Video Option Byte location. It must be maintained + * by the BIOS. + */ +#define VIDEO_MODE_ADDR 0x449 +/* + * Video controller base IO address location in + * BIOS data area + */ +#define DISPLAY_CRT_BASE_IO_ADDR 0x463 +/* + * Number of collums and lines locations for the + * actual video Configuration + */ +#define NB_MAX_COL_ADDR 0x44a +#define NB_MAX_ROW_ADDR 0x484 + + /* + * Miscellaneous information set by the BIOS in offset video_mode, + */ + +# define VGAMODE7 0x7 /* VGA mode 7 */ + + /* Color codes in text mode for background and foreground. */ +#define BLACK 0x0 +#define BLUE 0x1 +#define GREEN 0x2 +#define CYAN 0x3 +#define RED 0x4 +#define MAGENTA 0x5 +#define BROWN 0x6 +#define WHITE 0x7 + +#define GRAY 0x8 +#define LT_BLUE 0x9 +#define LT_GREEN 0xa +#define LT_CYAN 0xb +#define LT_RED 0xc +#define LT_MAGENTA 0xd +#define YELLOW 0xe +#define LT_WHITE 0xf + +#define BLINK 0x8 /* Mask used to determine blinking */ +#define OFF 0 +#define ON 1 + +/* + * CRT Controller register offset definitions + */ + +# define CC_CURSSTART 0x0a /* Cursor start scan line */ +# define CC_CURSEND 0x0b /* Cursor end scan line */ +# define CC_STARTADDRHI 0x0c /* start video ram addr msb */ +# define CC_STARTADDRLO 0x0d /* start video ram lsb */ +# define CC_CURSHIGH 0x0e /* Cursor high location (8 msb) */ +# define CC_CURSLOW 0x0f /* Cursor low location (8 msb) */ +# define CC_VRETSTART 0x10 /* vertical synchro start lsb */ +# define CC_VRETEND 0x11 /* vertical syn end (also it control) */ +# define CC_VDISPEND 0x12 /* vertical display end lsb register */ + +#endif /* _CRT_H */ diff --git a/bsps/i386/pc386/include/edid.h b/bsps/i386/pc386/include/edid.h new file mode 100644 index 0000000000..836294dcad --- /dev/null +++ b/bsps/i386/pc386/include/edid.h @@ -0,0 +1,520 @@ +/** + * @file edid.h + * + * @ingroup i386_pc386 + * + * @brief VESA EDID definitions. + * + * This file contains definitions for constants related to + * VESA Extended Display Identification Data. + * More information can be found at + * + * VESA public standards may be found at + * + */ + +/* + * Copyright (C) 2014 Jan Doležal (dolezj21@fel.cvut.cz) + * CTU in Prague. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _EDID_H +#define _EDID_H + +#ifndef ASM /* ASM */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include +#define EDID_INLINE_ROUTINE RTEMS_INLINE_ROUTINE + +/* VESA Enhanced Extended Display Identification Data (E-EDID) Proposed + Release A, March 27, 2007 */ + +/* *** Detailed Timing Descriptor Flags *** */ +#define EDID1_DTD_Flag_InterlacedOff 7 +#define EDID1_DTD_Flag_InterlacedMask 0x1 +#define EDID1_DTD_Flag_StereoModeOff 0 +#define EDID1_DTD_Flag_StereoModeMask 0xC1 +/* values for stereo flag */ +#define EDID1_DTD_Stereo_FldSeqRightOnSync 0x40 +#define EDID1_DTD_Stereo_FldSeqLeftOnSync 0x80 +#define EDID1_DTD_Stereo_2wItlvdRightOnEven 0x41 +#define EDID1_DTD_Stereo_2wItlvdLeftOnEven 0x81 +#define EDID1_DTD_Stereo_4wInterleaved 0xC0 +#define EDID1_DTD_Stereo_SideBySideItlvd 0xC1 +/* Analog = 0, Digital = 1 */ +#define EDID1_DTD_Flag_DigitalOff 4 +#define EDID1_DTD_Flag_DigitalMask 0x1 +/* Analog */ +#define EDID1_DTD_BipolarAnalogComposSyncOff 3 +#define EDID1_DTD_BipolarAnalogComposSyncMask 0x1 +#define EDID1_DTD_WithSerrationsOff 2 +#define EDID1_DTD_WithSerrationsMask 0x1 +/* Digital */ +#define EDID1_DTD_DigitalSeparateSyncOff 3 +#define EDID1_DTD_DigitalSeparateSyncMask 0x1 + /* when DigitalSeparateSync == 0 -> it is composite + and WithSerrations defined up in Analog part applies */ +#define EDID1_DTD_VerticalSyncIsPositiveOff 2 +#define EDID1_DTD_VerticalSyncIsPositiveMask 0x1 +#define EDID1_DTD_HorizontalSyncIsPositiveOff 1 +#define EDID1_DTD_HorizontalSyncIsPositiveMask 0x1 + +typedef struct { + uint8_t PixelClock_div10000[2]; + uint8_t HorizontalActiveLow; + uint8_t HorizontalBlankingLow; + uint8_t HorizontalBlanking_ActiveHigh; + uint8_t VerticalActiveLow; + uint8_t VerticalBlankingLow; + uint8_t VerticalBlanking_ActiveHigh; + uint8_t HorizontalSyncOffsetLow; + uint8_t HorizontalSyncPulseWidthLow; + uint8_t VerticalSyncPulseWidth_OffsetLow; + uint8_t Vert_Hor_SyncPulseWidth_Offset_High; + uint8_t HorizontalImageSizeLow; + uint8_t VerticalImageSizeLow; + uint8_t Vertical_HorizontalImageSizeHigh; + uint8_t HorizontalBorder; + uint8_t VerticalBorder; + uint8_t Flags; +} RTEMS_PACKED EDID_detailed_timing_descriptor; + +EDID_INLINE_ROUTINE uint16_t DTD_horizontal_active ( + EDID_detailed_timing_descriptor *dtd) +{ + return (dtd->HorizontalActiveLow | + (dtd->HorizontalBlanking_ActiveHigh & 0xF0) << 4); +} + +EDID_INLINE_ROUTINE uint16_t DTD_horizontal_blanking ( + EDID_detailed_timing_descriptor *dtd) +{ + return (dtd->HorizontalBlankingLow | + (dtd->HorizontalBlanking_ActiveHigh & 0xF) << 8); +} + +EDID_INLINE_ROUTINE uint16_t DTD_vertical_active ( + EDID_detailed_timing_descriptor *dtd) +{ + return (dtd->VerticalActiveLow | + (dtd->VerticalBlanking_ActiveHigh & 0xF0) << 4); +} + +EDID_INLINE_ROUTINE uint16_t DTD_vertical_blanking ( + EDID_detailed_timing_descriptor *dtd) +{ + return (dtd->VerticalBlankingLow | + (dtd->VerticalBlanking_ActiveHigh & 0xF) << 8); +} + +EDID_INLINE_ROUTINE uint16_t DTD_vertical_sync_pulse_width ( + EDID_detailed_timing_descriptor *dtd) +{ + return ((dtd->VerticalSyncPulseWidth_OffsetLow & 0xF) | + (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0x3) << 4); +} + +EDID_INLINE_ROUTINE uint16_t DTD_vertical_sync_offset ( + EDID_detailed_timing_descriptor *dtd) +{ + return ((dtd->VerticalSyncPulseWidth_OffsetLow >> 4) | + (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0xC) << 2); +} + +EDID_INLINE_ROUTINE uint16_t DTD_horizontal_sync_pulse_width ( + EDID_detailed_timing_descriptor *dtd) +{ + return (dtd->HorizontalSyncPulseWidthLow | + (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0x30) << 4); +} + +EDID_INLINE_ROUTINE uint16_t DTD_horizontal_sync_offset ( + EDID_detailed_timing_descriptor *dtd) +{ + return (dtd->HorizontalSyncOffsetLow | + (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0xC0) << 2); +} + +EDID_INLINE_ROUTINE uint16_t DTD_vertical_image_size ( + EDID_detailed_timing_descriptor *dtd) +{ + return (dtd->VerticalImageSizeLow | + (dtd->Vertical_HorizontalImageSizeHigh & 0xF) << 8); +} + +EDID_INLINE_ROUTINE uint16_t DTD_horizontal_image_size ( + EDID_detailed_timing_descriptor *dtd) +{ + return (dtd->HorizontalImageSizeLow | + (dtd->Vertical_HorizontalImageSizeHigh & 0xF0) << 4); +} + +typedef struct { + uint8_t ColorPointWhitePointIndexNumber; + uint8_t ColorPointWhiteLowBits; + uint8_t ColorPointWhite_x; + uint8_t ColorPointWhite_y; + uint8_t ColorPointWhiteGamma; +} RTEMS_PACKED EDID_color_point_data; + +/* Basic Display Parameters */ +/* Monitor Descriptor - Data Type Tag */ +#define EDID_DTT_MonitorSerialNumber 0xFF + +#define EDID_DTT_ASCIIString 0xFE + +#define EDID_DTT_MonitorRangeLimits 0xFD +typedef struct { + uint8_t MinVerticalRateInHz; + uint8_t MaxVerticalRateInHz; + uint8_t MinHorizontalInKHz; + uint8_t MaxHorizontalInKHz; + uint8_t MaxSupportedPixelClockIn10MHz; +/* see VESA, Generalized Timing Formula Standard - GTF + Version 1.0, December 18, 1996 */ + uint8_t GTFStandard[8]; +} RTEMS_PACKED EDID_monitor_range_limits; + +#define EDID_DTT_MonitorName 0xFC + +#define EDID_DTT_AdditionalColorPointData 0xFB +/* Standard Timing Identification */ +#define EDID_DTT_AdditionalSTI 0xFA + +#define EDID_DTT_DisplayColorManagement 0xF9 + +#define EDID_DTT_CVT3ByteTimingCodes 0xF8 + +#define EDID1_CVT_AspectRatioOff 2 +#define EDID1_CVT_AspectRatioMask 0x3 +#define EDID1_CVT_AddressableLinesHighOff 4 +#define EDID1_CVT_AddressableLinesHighMask 0xF + /* next 5 bits indicate supported vertical rates */ +#define EDID1_CVT_VerticalRate60HzRBOff 0 +#define EDID1_CVT_VerticalRate60HzRBMask 0x1 +#define EDID1_CVT_VerticalRate85HzOff 1 +#define EDID1_CVT_VerticalRate85HzMask 0x1 +#define EDID1_CVT_VerticalRate75HzOff 2 +#define EDID1_CVT_VerticalRate75HzMask 0x1 +#define EDID1_CVT_VerticalRate60HzOff 3 +#define EDID1_CVT_VerticalRate60HzMask 0x1 +#define EDID1_CVT_VerticalRate50HzOff 4 +#define EDID1_CVT_VerticalRate50HzMask 0x1 +#define EDID1_CVT_PreferredVerticalRateOff 5 +#define EDID1_CVT_PreferredVerticalRateMask 0x3 + +#define EDID_CVT_AspectRatio_4_3 0 +#define EDID_CVT_AspectRatio_16_9 1 +#define EDID_CVT_AspectRatio_16_10 2 +#define EDID_CVT_AspectRatio_15_9 3 +#define EDID_CVT_PrefVertRate50Hz 0 +#define EDID_CVT_PrefVertRate60Hz 1 +#define EDID_CVT_PrefVertRate75Hz 2 +#define EDID_CVT_PrefVertRate85Hz 3 +typedef struct { + uint8_t AddressableLinesLow; + uint8_t AspectRatio_AddressableLinesHigh; + uint8_t VerticalRate_PreferredVerticalRate; +} RTEMS_PACKED EDID_CVT_3_byte_code_descriptor; +typedef struct { + uint8_t VersionNumber; + EDID_CVT_3_byte_code_descriptor cvt[4]; +} RTEMS_PACKED EDID_CVT_timing_codes_3B; + +EDID_INLINE_ROUTINE uint16_t edid1_CVT_addressable_lines_high ( + EDID_CVT_3_byte_code_descriptor *cvt) +{ + return (cvt->AddressableLinesLow | + (cvt->VerticalRate_PreferredVerticalRate & + (EDID1_CVT_AddressableLinesHighMask<AspectRatio_AddressableLinesHigh >> EDID1_CVT_AspectRatioOff) & + EDID1_CVT_AspectRatioMask; +} + +#define EDID_DTT_EstablishedTimingsIII 0xF7 +typedef struct { + uint8_t RevisionNumber; + uint8_t EST_III[12]; +} RTEMS_PACKED EDID_established_timings_III; +enum EST_III { + EST_1152x864_75Hz = 0, + EST_1024x768_85Hz = 1, + EST_800x600_85Hz = 2, + EST_848x480_60Hz = 3, + EST_640x480_85Hz = 4, + EST_720x400_85Hz = 5, + EST_640x400_85Hz = 6, + EST_640x350_85Hz = 7, + + EST_1280x1024_85Hz = 8, + EST_1280x1024_60Hz = 9, + EST_1280x960_85Hz = 10, + EST_1280x960_60Hz = 11, + EST_1280x768_85Hz = 12, + EST_1280x768_75Hz = 13, + EST_1280x768_60Hz = 14, + EST_1280x768_60HzRB = 15, + + EST_1400x1050_75Hz = 16, + EST_1400x1050_60Hz = 17, + EST_1400x1050_60HzRB= 18, + EST_1400x900_85Hz = 19, + EST_1400x900_75Hz = 20, + EST_1400x900_60Hz = 21, + EST_1400x900_60HzRB = 22, + EST_1360x768_60Hz = 23, + + EST_1600x1200_70Hz = 24, + EST_1600x1200_65Hz = 25, + EST_1600x1200_60Hz = 26, + EST_1680x1050_85Hz = 27, + EST_1680x1050_75Hz = 28, + EST_1680x1050_60Hz = 29, + EST_1680x1050_60HzRB= 30, + EST_1400x1050_85Hz = 31, + + EST_1920x1200_60Hz = 32, + EST_1920x1200_60HzRB= 33, + EST_1856x1392_75Hz = 34, + EST_1856x1392_60Hz = 35, + EST_1792x1344_75Hz = 36, + EST_1792x1344_60Hz = 37, + EST_1600x1200_85Hz = 38, + EST_1600x1200_75Hz = 39, + + EST_1920x1440_75Hz = 44, + EST_1920x1440_60Hz = 45, + EST_1920x1200_85Hz = 46, + EST_1920x1200_75Hz = 47, +}; + +#define EDID_DTT_DescriptorSpaceUnused 0x10 +/* DTT 0x0 - 0xF are manufacturer specific */ + +typedef struct { + uint8_t Flag0[2]; + uint8_t Flag1; + uint8_t DataTypeTag; + uint8_t Flag2; + uint8_t DescriptorData[13]; +} RTEMS_PACKED EDID_monitor_descriptor; + +union EDID_DTD_MD { + EDID_detailed_timing_descriptor dtd; + EDID_monitor_descriptor md; +} RTEMS_PACKED; + +#define EDID1_STI_ImageAspectRatioOff 0 +#define EDID1_STI_ImageAspectRatioMask 0x3 +#define EDID1_STI_RefreshRateOff 2 +#define EDID1_STI_RefreshRateMask 0x3F + +#define EDID_STI_DescriptorUnused 0x0101 +#define EDID_STI_AspectRatio_16_10 0 +#define EDID_STI_AspectRatio_4_3 1 +#define EDID_STI_AspectRatio_5_4 2 +#define EDID_STI_AspectRatio_16_9 3 +typedef struct { + uint8_t HorizontalActivePixels; + uint8_t ImageAspectRatio_RefreshRate; +} RTEMS_PACKED EDID_standard_timing_identification; + +/* Video Input Definition */ +/* Analog = 0, Digital = 1 */ +#define EDID1_VID_DigitalSignalLevelOff 7 +#define EDID1_VID_DigitalSignalLevelMask 0x1 +/* for EDID1_VID_DigitalSignalLevelOff = 1 (Digital) */ +#define EDID1_VID_ColorBitDepthOff 4 +#define EDID1_VID_ColorBitDepthMask 0x7 /* see CBD */ +#define EDID1_VID_DigitalVideoStandardSuppOff 0 +#define EDID1_VID_DigitalVideoStandardSuppMask 0xF /* see DVS */ +/* for EDID1_VID_DigitalSignalLevelOff = 0 (Analog) */ +#define EDID1_VID_SignalLevelStandardOff 5 +#define EDID1_VID_SignalLevelStandardMask 0x3 +#define EDID1_VID_VideoSetupBlankOff 4 +#define EDID1_VID_VideoSetupBlankMask 0x1 +#define EDID1_VID_SeparateSyncHandVSignalsOff 3 +#define EDID1_VID_SeparateSyncHandVSignalsMask 0x1 +#define EDID1_VID_SyncSignalOnHorizontalOff 2 +#define EDID1_VID_SyncSignalOnHorizontalMask 0x1 +#define EDID1_VID_SyncSignalOnGreenOff 1 +#define EDID1_VID_SyncSignalOnGreenMask 0x1 +#define EDID1_VID_SerationOnVerticalSyncOff 0 +#define EDID1_VID_SerationOnVerticalSyncMask 0x1 +/* Analog Interface Data Format - Signal Level Standard */ +#define EDID_SLS_0700_0300_1000Vpp 0x0 +#define EDID_SLS_0714_0286_1000Vpp 0x1 +#define EDID_SLS_1000_0400_1400Vpp 0x2 +#define EDID_SLS_0700_0000_0700Vpp 0x3 + +/* Color Bit Depths */ +#define CBD_undef 0x0 +#define CBD_6bPerPrimaryColor 0x1 +#define CBD_8bPerPrimaryColor 0x2 +#define CBD_10bPerPrimaryColor 0x3 +#define CBD_12bPerPrimaryColor 0x4 +#define CBD_14bPerPrimaryColor 0x5 +#define CBD_16bPerPrimaryColor 0x6 +#define CBD_reserved 0x7 + +/* Digital Video Standard Supported */ +#define DVS_undef 0x0 +#define DVS_DVI 0x1 +#define DVS_HDMI-a 0x2 +#define DVS_HDMI-b 0x3 +#define DVS_MDDI 0x4 +#define DVS_DiplayPort 0x5 + +/* Feature Support */ +#define EDID1_Feature_GTFSupported_mask 0x1 +#define EDID1_Feature_GTFSupported_off 0 +#define EDID1_Feature_PreferredTimingMode_mask 0x1 +#define EDID1_Feature_PreferredTimingMode_off 1 +#define EDID1_Feature_StandardDefaultColorSpace_mask 0x1 +#define EDID1_Feature_StandardDefaultColorSpace_off 2 +#define EDID1_Feature_DisplayType_mask 0x2 +#define EDID1_Feature_DisplayType_off 3 + /* Refer to VESA DPMS Specification */ +#define EDID1_Feature_ActiveOff_mask 0x1 +#define EDID1_Feature_ActiveOff_off 5 +#define EDID1_Feature_Suspend_mask 0x1 +#define EDID1_Feature_Suspend_off 6 +#define EDID1_Feature_StandBy_mask 0x1 +#define EDID1_Feature_StandBy_off 7 + /* analog - Display Color Type */ +#define EDID_DisplayType_Monochrome 0 +#define EDID_DisplayType_RGBcolor 1 +#define EDID_DisplayType_nonRGBcolor 2 +#define EDID_DisplayType_undef 3 + /* digital - Supported Color Encoding Formats */ +#define EDID_DisplayType_RGB444 0 +#define EDID_DisplayType_RGB444YCrCb444 1 +#define EDID_DisplayType_RGB444YCrCb422 2 +#define EDID_DisplayType_RGB444YCrCb444YCrCb422 3 + +typedef struct { + uint8_t Header[8]; +/* Vendor Product Identification */ + uint8_t IDManufacturerName[2]; + uint8_t IDProductCode[2]; + uint8_t IDSerialNumber[4]; + uint8_t WeekofManufacture; + uint8_t YearofManufacture; +/* EDID Structure Version Revision Level */ + uint8_t Version; + uint8_t Revision; +/* Basic Display Parameters Features */ + /* Video Input Definition */ + uint8_t VideoInputDefinition; + uint8_t MaxHorizontalImageSize; + uint8_t MaxVerticalImageSize; + uint8_t DisplayTransferCharacteristic; + /* Feature Support */ + uint8_t Features; +/* Color Characteristics */ + uint8_t GreenRedLow; + uint8_t WhiteBlueLow; + uint8_t RedXHigh; + uint8_t RedYHigh; + uint8_t GreenXHigh; + uint8_t GreenYHigh; + uint8_t BlueXHigh; + uint8_t BlueYHigh; + uint8_t WhiteXHigh; + uint8_t WhiteYHigh; +/* Established Timings I, II, Manufacturer's */ + uint8_t EST_I_II_Man[3]; +/* Standard Timing Identification */ + EDID_standard_timing_identification STI[8]; +/* Detailed Timing Descriptions / Monitor Descriptions */ + union EDID_DTD_MD dtd_md[4]; + uint8_t ExtensionFlag; + uint8_t Checksum; +} RTEMS_PACKED EDID_edid1; + +EDID_INLINE_ROUTINE uint16_t edid1_RedX (EDID_edid1 *edid) { + return (edid->RedXHigh<<2) | (edid->GreenRedLow>>6); +} +EDID_INLINE_ROUTINE uint16_t edid1_RedY (EDID_edid1 *edid) { + return (edid->RedYHigh<<2) | (edid->GreenRedLow>>4)&&0x3; +} +EDID_INLINE_ROUTINE uint16_t edid1_GreenX (EDID_edid1 *edid) { + return (edid->GreenXHigh<<2) | (edid->GreenRedLow>>2)&&0x3; +} +EDID_INLINE_ROUTINE uint16_t edid1_GreenY (EDID_edid1 *edid) { + return (edid->GreenYHigh<<2) | (edid->GreenRedLow&0x3); +} +EDID_INLINE_ROUTINE uint16_t edid1_BlueX (EDID_edid1 *edid) { + return (edid->BlueXHigh<<2) | (edid->WhiteBlueLow>>6); +} +EDID_INLINE_ROUTINE uint16_t edid1_BlueY (EDID_edid1 *edid) { + return (edid->BlueYHigh<<2) | (edid->WhiteBlueLow>>4)&&0x3; +} +EDID_INLINE_ROUTINE uint16_t edid1_WhiteX (EDID_edid1 *edid) { + return (edid->WhiteXHigh<<2) | (edid->WhiteBlueLow>>2)&&0x3; +} +EDID_INLINE_ROUTINE uint16_t edid1_WhiteY (EDID_edid1 *edid) { + return (edid->WhiteYHigh<<2) | (edid->WhiteBlueLow&0x3); +} + +EDID_INLINE_ROUTINE int edid1_STI_is_unused ( + const EDID_standard_timing_identification *edid_sti) { + return (edid_sti->HorizontalActivePixels == + (uint8_t)EDID_STI_DescriptorUnused) && + (edid_sti->ImageAspectRatio_RefreshRate == + (uint8_t)(EDID_STI_DescriptorUnused >> 8)); +} + +enum edid1_established_timings { +/* Established Timings I */ + EST_800x600_60Hz = 0, + EST_800x600_56Hz = 1, + EST_640x480_75Hz = 2, + EST_640x480_72Hz = 3, + EST_640x480_67Hz = 4, + EST_640x480_60Hz = 5, + EST_720x400_88Hz = 6, + EST_720x400_70Hz = 7, +/* Established Timings II */ + EST_1280x1024_75Hz = 8, + EST_1024x768_75Hz = 9, + EST_1024x768_70Hz = 10, + EST_1024x768_60Hz = 11, + EST_1024x768_87Hz = 12, + EST_832x624_75Hz = 13, + EST_800x600_75Hz = 14, + EST_800x600_72Hz = 15, +/* Manufacturer's Timings */ + EST_1152x870_75Hz = 23, +}; + +EDID_INLINE_ROUTINE uint8_t edid1_established_tim ( + EDID_edid1 *edid, + enum edid1_established_timings est) +{ + return (uint8_t)(edid->EST_I_II_Man[est/8] & (est%8)); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* _VBE_H */ diff --git a/bsps/i386/pc386/include/rtems/kd.h b/bsps/i386/pc386/include/rtems/kd.h new file mode 100644 index 0000000000..c97e4f7bdd --- /dev/null +++ b/bsps/i386/pc386/include/rtems/kd.h @@ -0,0 +1,111 @@ +/** + * @file + * + * @ingroup i386_pc386 + * + * @brief KD definitions. + */ + +/* + * by: Rosimildo da Silva: rdasilva@connecttel.com + * + * + */ + +#ifndef _LINUX_KD_H +#define _LINUX_KD_H +#include + +/* 0x4B is 'K', to avoid collision with termios and vt */ + +#define KIOCSOUND 0x4B2F /* start sound generation (0 for off) */ +#define KDMKTONE 0x4B30 /* generate tone */ + +#define KDGETLED 0x4B31 /* return current led state */ +#define KDSETLED 0x4B32 /* set led state [lights, not flags] */ +#define LED_SCR 0x01 /* scroll lock led */ +#define LED_CAP 0x04 /* caps lock led */ +#define LED_NUM 0x02 /* num lock led */ + +#define KDGKBTYPE 0x4B33 /* get keyboard type */ +#define KB_84 0x01 +#define KB_101 0x02 /* this is what we always answer */ +#define KB_OTHER 0x03 + +#define KDSETMODE 0x4B3A /* set text/graphics mode */ +#define KD_TEXT 0x00 +#define KD_GRAPHICS 0x01 +#define KD_TEXT0 0x02 /* obsolete */ +#define KD_TEXT1 0x03 /* obsolete */ +#define KDGETMODE 0x4B3B /* get current mode */ + +#define K_RAW 0x00 +#define K_XLATE 0x01 +#define K_MEDIUMRAW 0x02 +#define K_UNICODE 0x03 +#define KDGKBMODE 0x4B44 /* gets current keyboard mode */ +#define KDSKBMODE 0x4B45 /* sets current keyboard mode */ + +#define K_METABIT 0x03 +#define K_ESCPREFIX 0x04 +#define KDGKBMETA 0x4B62 /* gets meta key handling mode */ +#define KDSKBMETA 0x4B63 /* sets meta key handling mode */ + +#define K_SCROLLLOCK 0x01 +#define K_CAPSLOCK 0x02 +#define K_NUMLOCK 0x04 +#define KDGKBLED 0x4B64 /* get led flags (not lights) */ +#define KDSKBLED 0x4B65 /* set led flags (not lights) */ + +struct kbentry { + unsigned char kb_table; + unsigned char kb_index; + unsigned short kb_value; +}; +#define K_NORMTAB 0x00 +#define K_SHIFTTAB 0x01 +#define K_ALTTAB 0x02 +#define K_ALTSHIFTTAB 0x03 + +#define KDGKBENT 0x4B46 /* gets one entry in translation table */ +#define KDSKBENT 0x4B47 /* sets one entry in translation table */ + +struct kbsentry { + unsigned char kb_func; + unsigned char kb_string[512]; +}; + +struct kbdiacr { + unsigned char diacr, base, result; +}; +struct kbdiacrs { + unsigned int kb_cnt; /* number of entries in following array */ + struct kbdiacr kbdiacr[256]; /* MAX_DIACR from keyboard.h */ +}; +#define KDGKBDIACR 0x4B4A /* read kernel accent table */ +#define KDSKBDIACR 0x4B4B /* write kernel accent table */ + +struct kbkeycode { + unsigned int scancode, keycode; +}; +#define KDGETKEYCODE 0x4B4C /* read kernel keycode table entry */ +#define KDSETKEYCODE 0x4B4D /* write kernel keycode table entry */ + +#define KDSIGACCEPT 0x4B4E /* accept kbd generated signals */ + +#define KDGHWCLK 0x4B50 /* get hardware clock */ +#define KDSHWCLK 0x4B51 /* set hardware clock */ + +struct kbd_repeat { + int delay; /* in msec; <= 0: don't change */ + int rate; /* in msec; <= 0: don't change */ +}; + +#define KDKBDREP 0x4B52 /* set keyboard delay/repeat rate; + * actually used values are returned */ + +/* note: 0x4B00-0x4B4E all have had a value at some time; + don't reuse for the time being */ +/* note: 0x4B60-0x4B6D, 0x4B70-0x4B72 used above */ + +#endif /* _LINUX_KD_H */ diff --git a/bsps/i386/pc386/include/rtems/keyboard.h b/bsps/i386/pc386/include/rtems/keyboard.h new file mode 100644 index 0000000000..ffc8aabfbd --- /dev/null +++ b/bsps/i386/pc386/include/rtems/keyboard.h @@ -0,0 +1,604 @@ +/** + * @file + * + * @ingroup i386_pc386 + * + * @brief Keyboard definitions. + */ + +/* + * Submitted by: Rosimildo da Silva: rdasilva@connecttel.com + */ + +#ifndef __RTEMS_KEYBOARD_H +#define __RTEMS_KEYBOARD_H + +#include + +#define KG_SHIFT 0 +#define KG_CTRL 2 +#define KG_ALT 3 +#define KG_ALTGR 1 +#define KG_SHIFTL 4 +#define KG_SHIFTR 5 +#define KG_CTRLL 6 +#define KG_CTRLR 7 +#define KG_CAPSSHIFT 8 + +#define NR_SHIFT 9 + +#define NR_KEYS 128 +#define MAX_NR_KEYMAPS 256 +/* This means 64Kb if all keymaps are allocated. Only the superuser + may increase the number of keymaps beyond MAX_NR_OF_USER_KEYMAPS. */ +#define MAX_NR_OF_USER_KEYMAPS 256 /* should be at least 7 */ + +extern const int NR_TYPES; +extern unsigned short *key_maps[MAX_NR_KEYMAPS]; +extern unsigned short plain_map[NR_KEYS]; +extern unsigned char keyboard_type; + +#define MAX_NR_FUNC 256 /* max nr of strings assigned to keys */ +#define MAX_NR_CONSOLES 1 + +extern char *func_table[MAX_NR_FUNC]; + +#define KT_LATIN 0 /* we depend on this being zero */ +#define KT_LETTER 11 /* symbol that can be acted upon by CapsLock */ +#define KT_FN 1 +#define KT_SPEC 2 +#define KT_PAD 3 +#define KT_DEAD 4 +#define KT_CONS 5 +#define KT_CUR 6 +#define KT_SHIFT 7 +#define KT_META 8 +#define KT_ASCII 9 +#define KT_LOCK 10 +#define KT_SLOCK 12 + +#define K(t,v) (((t)<<8)|(v)) +#define KTYP(x) ((x) >> 8) +#define KVAL(x) ((x) & 0xff) + +#define K_F1 K(KT_FN,0) +#define K_F2 K(KT_FN,1) +#define K_F3 K(KT_FN,2) +#define K_F4 K(KT_FN,3) +#define K_F5 K(KT_FN,4) +#define K_F6 K(KT_FN,5) +#define K_F7 K(KT_FN,6) +#define K_F8 K(KT_FN,7) +#define K_F9 K(KT_FN,8) +#define K_F10 K(KT_FN,9) +#define K_F11 K(KT_FN,10) +#define K_F12 K(KT_FN,11) +#define K_F13 K(KT_FN,12) +#define K_F14 K(KT_FN,13) +#define K_F15 K(KT_FN,14) +#define K_F16 K(KT_FN,15) +#define K_F17 K(KT_FN,16) +#define K_F18 K(KT_FN,17) +#define K_F19 K(KT_FN,18) +#define K_F20 K(KT_FN,19) +#define K_FIND K(KT_FN,20) +#define K_INSERT K(KT_FN,21) +#define K_REMOVE K(KT_FN,22) +#define K_SELECT K(KT_FN,23) +#define K_PGUP K(KT_FN,24) /* PGUP is a synonym for PRIOR */ +#define K_PGDN K(KT_FN,25) /* PGDN is a synonym for NEXT */ +#define K_MACRO K(KT_FN,26) +#define K_HELP K(KT_FN,27) +#define K_DO K(KT_FN,28) +#define K_PAUSE K(KT_FN,29) +#define K_F21 K(KT_FN,30) +#define K_F22 K(KT_FN,31) +#define K_F23 K(KT_FN,32) +#define K_F24 K(KT_FN,33) +#define K_F25 K(KT_FN,34) +#define K_F26 K(KT_FN,35) +#define K_F27 K(KT_FN,36) +#define K_F28 K(KT_FN,37) +#define K_F29 K(KT_FN,38) +#define K_F30 K(KT_FN,39) +#define K_F31 K(KT_FN,40) +#define K_F32 K(KT_FN,41) +#define K_F33 K(KT_FN,42) +#define K_F34 K(KT_FN,43) +#define K_F35 K(KT_FN,44) +#define K_F36 K(KT_FN,45) +#define K_F37 K(KT_FN,46) +#define K_F38 K(KT_FN,47) +#define K_F39 K(KT_FN,48) +#define K_F40 K(KT_FN,49) +#define K_F41 K(KT_FN,50) +#define K_F42 K(KT_FN,51) +#define K_F43 K(KT_FN,52) +#define K_F44 K(KT_FN,53) +#define K_F45 K(KT_FN,54) +#define K_F46 K(KT_FN,55) +#define K_F47 K(KT_FN,56) +#define K_F48 K(KT_FN,57) +#define K_F49 K(KT_FN,58) +#define K_F50 K(KT_FN,59) +#define K_F51 K(KT_FN,60) +#define K_F52 K(KT_FN,61) +#define K_F53 K(KT_FN,62) +#define K_F54 K(KT_FN,63) +#define K_F55 K(KT_FN,64) +#define K_F56 K(KT_FN,65) +#define K_F57 K(KT_FN,66) +#define K_F58 K(KT_FN,67) +#define K_F59 K(KT_FN,68) +#define K_F60 K(KT_FN,69) +#define K_F61 K(KT_FN,70) +#define K_F62 K(KT_FN,71) +#define K_F63 K(KT_FN,72) +#define K_F64 K(KT_FN,73) +#define K_F65 K(KT_FN,74) +#define K_F66 K(KT_FN,75) +#define K_F67 K(KT_FN,76) +#define K_F68 K(KT_FN,77) +#define K_F69 K(KT_FN,78) +#define K_F70 K(KT_FN,79) +#define K_F71 K(KT_FN,80) +#define K_F72 K(KT_FN,81) +#define K_F73 K(KT_FN,82) +#define K_F74 K(KT_FN,83) +#define K_F75 K(KT_FN,84) +#define K_F76 K(KT_FN,85) +#define K_F77 K(KT_FN,86) +#define K_F78 K(KT_FN,87) +#define K_F79 K(KT_FN,88) +#define K_F80 K(KT_FN,89) +#define K_F81 K(KT_FN,90) +#define K_F82 K(KT_FN,91) +#define K_F83 K(KT_FN,92) +#define K_F84 K(KT_FN,93) +#define K_F85 K(KT_FN,94) +#define K_F86 K(KT_FN,95) +#define K_F87 K(KT_FN,96) +#define K_F88 K(KT_FN,97) +#define K_F89 K(KT_FN,98) +#define K_F90 K(KT_FN,99) +#define K_F91 K(KT_FN,100) +#define K_F92 K(KT_FN,101) +#define K_F93 K(KT_FN,102) +#define K_F94 K(KT_FN,103) +#define K_F95 K(KT_FN,104) +#define K_F96 K(KT_FN,105) +#define K_F97 K(KT_FN,106) +#define K_F98 K(KT_FN,107) +#define K_F99 K(KT_FN,108) +#define K_F100 K(KT_FN,109) +#define K_F101 K(KT_FN,110) +#define K_F102 K(KT_FN,111) +#define K_F103 K(KT_FN,112) +#define K_F104 K(KT_FN,113) +#define K_F105 K(KT_FN,114) +#define K_F106 K(KT_FN,115) +#define K_F107 K(KT_FN,116) +#define K_F108 K(KT_FN,117) +#define K_F109 K(KT_FN,118) +#define K_F110 K(KT_FN,119) +#define K_F111 K(KT_FN,120) +#define K_F112 K(KT_FN,121) +#define K_F113 K(KT_FN,122) +#define K_F114 K(KT_FN,123) +#define K_F115 K(KT_FN,124) +#define K_F116 K(KT_FN,125) +#define K_F117 K(KT_FN,126) +#define K_F118 K(KT_FN,127) +#define K_F119 K(KT_FN,128) +#define K_F120 K(KT_FN,129) +#define K_F121 K(KT_FN,130) +#define K_F122 K(KT_FN,131) +#define K_F123 K(KT_FN,132) +#define K_F124 K(KT_FN,133) +#define K_F125 K(KT_FN,134) +#define K_F126 K(KT_FN,135) +#define K_F127 K(KT_FN,136) +#define K_F128 K(KT_FN,137) +#define K_F129 K(KT_FN,138) +#define K_F130 K(KT_FN,139) +#define K_F131 K(KT_FN,140) +#define K_F132 K(KT_FN,141) +#define K_F133 K(KT_FN,142) +#define K_F134 K(KT_FN,143) +#define K_F135 K(KT_FN,144) +#define K_F136 K(KT_FN,145) +#define K_F137 K(KT_FN,146) +#define K_F138 K(KT_FN,147) +#define K_F139 K(KT_FN,148) +#define K_F140 K(KT_FN,149) +#define K_F141 K(KT_FN,150) +#define K_F142 K(KT_FN,151) +#define K_F143 K(KT_FN,152) +#define K_F144 K(KT_FN,153) +#define K_F145 K(KT_FN,154) +#define K_F146 K(KT_FN,155) +#define K_F147 K(KT_FN,156) +#define K_F148 K(KT_FN,157) +#define K_F149 K(KT_FN,158) +#define K_F150 K(KT_FN,159) +#define K_F151 K(KT_FN,160) +#define K_F152 K(KT_FN,161) +#define K_F153 K(KT_FN,162) +#define K_F154 K(KT_FN,163) +#define K_F155 K(KT_FN,164) +#define K_F156 K(KT_FN,165) +#define K_F157 K(KT_FN,166) +#define K_F158 K(KT_FN,167) +#define K_F159 K(KT_FN,168) +#define K_F160 K(KT_FN,169) +#define K_F161 K(KT_FN,170) +#define K_F162 K(KT_FN,171) +#define K_F163 K(KT_FN,172) +#define K_F164 K(KT_FN,173) +#define K_F165 K(KT_FN,174) +#define K_F166 K(KT_FN,175) +#define K_F167 K(KT_FN,176) +#define K_F168 K(KT_FN,177) +#define K_F169 K(KT_FN,178) +#define K_F170 K(KT_FN,179) +#define K_F171 K(KT_FN,180) +#define K_F172 K(KT_FN,181) +#define K_F173 K(KT_FN,182) +#define K_F174 K(KT_FN,183) +#define K_F175 K(KT_FN,184) +#define K_F176 K(KT_FN,185) +#define K_F177 K(KT_FN,186) +#define K_F178 K(KT_FN,187) +#define K_F179 K(KT_FN,188) +#define K_F180 K(KT_FN,189) +#define K_F181 K(KT_FN,190) +#define K_F182 K(KT_FN,191) +#define K_F183 K(KT_FN,192) +#define K_F184 K(KT_FN,193) +#define K_F185 K(KT_FN,194) +#define K_F186 K(KT_FN,195) +#define K_F187 K(KT_FN,196) +#define K_F188 K(KT_FN,197) +#define K_F189 K(KT_FN,198) +#define K_F190 K(KT_FN,199) +#define K_F191 K(KT_FN,200) +#define K_F192 K(KT_FN,201) +#define K_F193 K(KT_FN,202) +#define K_F194 K(KT_FN,203) +#define K_F195 K(KT_FN,204) +#define K_F196 K(KT_FN,205) +#define K_F197 K(KT_FN,206) +#define K_F198 K(KT_FN,207) +#define K_F199 K(KT_FN,208) +#define K_F200 K(KT_FN,209) +#define K_F201 K(KT_FN,210) +#define K_F202 K(KT_FN,211) +#define K_F203 K(KT_FN,212) +#define K_F204 K(KT_FN,213) +#define K_F205 K(KT_FN,214) +#define K_F206 K(KT_FN,215) +#define K_F207 K(KT_FN,216) +#define K_F208 K(KT_FN,217) +#define K_F209 K(KT_FN,218) +#define K_F210 K(KT_FN,219) +#define K_F211 K(KT_FN,220) +#define K_F212 K(KT_FN,221) +#define K_F213 K(KT_FN,222) +#define K_F214 K(KT_FN,223) +#define K_F215 K(KT_FN,224) +#define K_F216 K(KT_FN,225) +#define K_F217 K(KT_FN,226) +#define K_F218 K(KT_FN,227) +#define K_F219 K(KT_FN,228) +#define K_F220 K(KT_FN,229) +#define K_F221 K(KT_FN,230) +#define K_F222 K(KT_FN,231) +#define K_F223 K(KT_FN,232) +#define K_F224 K(KT_FN,233) +#define K_F225 K(KT_FN,234) +#define K_F226 K(KT_FN,235) +#define K_F227 K(KT_FN,236) +#define K_F228 K(KT_FN,237) +#define K_F229 K(KT_FN,238) +#define K_F230 K(KT_FN,239) +#define K_F231 K(KT_FN,240) +#define K_F232 K(KT_FN,241) +#define K_F233 K(KT_FN,242) +#define K_F234 K(KT_FN,243) +#define K_F235 K(KT_FN,244) +#define K_F236 K(KT_FN,245) +#define K_F237 K(KT_FN,246) +#define K_F238 K(KT_FN,247) +#define K_F239 K(KT_FN,248) +#define K_F240 K(KT_FN,249) +#define K_F241 K(KT_FN,250) +#define K_F242 K(KT_FN,251) +#define K_F243 K(KT_FN,252) +#define K_F244 K(KT_FN,253) +#define K_F245 K(KT_FN,254) +#define K_UNDO K(KT_FN,255) + +#define K_HOLE K(KT_SPEC,0) +#define K_ENTER K(KT_SPEC,1) +#define K_SH_REGS K(KT_SPEC,2) +#define K_SH_MEM K(KT_SPEC,3) +#define K_SH_STAT K(KT_SPEC,4) +#define K_BREAK K(KT_SPEC,5) +#define K_CONS K(KT_SPEC,6) +#define K_CAPS K(KT_SPEC,7) +#define K_NUM K(KT_SPEC,8) +#define K_HOLD K(KT_SPEC,9) +#define K_SCROLLFORW K(KT_SPEC,10) +#define K_SCROLLBACK K(KT_SPEC,11) +#define K_BOOT K(KT_SPEC,12) +#define K_CAPSON K(KT_SPEC,13) +#define K_COMPOSE K(KT_SPEC,14) +#define K_SAK K(KT_SPEC,15) +#define K_DECRCONSOLE K(KT_SPEC,16) +#define K_INCRCONSOLE K(KT_SPEC,17) +#define K_SPAWNCONSOLE K(KT_SPEC,18) +#define K_BARENUMLOCK K(KT_SPEC,19) + +#define K_ALLOCATED K(KT_SPEC,126) /* dynamically allocated keymap */ +#define K_NOSUCHMAP K(KT_SPEC,127) /* returned by KDGKBENT */ + +#define K_P0 K(KT_PAD,0) +#define K_P1 K(KT_PAD,1) +#define K_P2 K(KT_PAD,2) +#define K_P3 K(KT_PAD,3) +#define K_P4 K(KT_PAD,4) +#define K_P5 K(KT_PAD,5) +#define K_P6 K(KT_PAD,6) +#define K_P7 K(KT_PAD,7) +#define K_P8 K(KT_PAD,8) +#define K_P9 K(KT_PAD,9) +#define K_PPLUS K(KT_PAD,10) /* key-pad plus */ +#define K_PMINUS K(KT_PAD,11) /* key-pad minus */ +#define K_PSTAR K(KT_PAD,12) /* key-pad asterisk (star) */ +#define K_PSLASH K(KT_PAD,13) /* key-pad slash */ +#define K_PENTER K(KT_PAD,14) /* key-pad enter */ +#define K_PCOMMA K(KT_PAD,15) /* key-pad comma: kludge... */ +#define K_PDOT K(KT_PAD,16) /* key-pad dot (period): kludge... */ +#define K_PPLUSMINUS K(KT_PAD,17) /* key-pad plus/minus */ +#define K_PPARENL K(KT_PAD,18) /* key-pad left parenthesis */ +#define K_PPARENR K(KT_PAD,19) /* key-pad right parenthesis */ + +#define NR_PAD 20 + +#define K_DGRAVE K(KT_DEAD,0) +#define K_DACUTE K(KT_DEAD,1) +#define K_DCIRCM K(KT_DEAD,2) +#define K_DTILDE K(KT_DEAD,3) +#define K_DDIERE K(KT_DEAD,4) +#define K_DCEDIL K(KT_DEAD,5) + +#define NR_DEAD 6 + +#define K_DOWN K(KT_CUR,0) +#define K_LEFT K(KT_CUR,1) +#define K_RIGHT K(KT_CUR,2) +#define K_UP K(KT_CUR,3) + +#define K_SHIFT K(KT_SHIFT,KG_SHIFT) +#define K_CTRL K(KT_SHIFT,KG_CTRL) +#define K_ALT K(KT_SHIFT,KG_ALT) +#define K_ALTGR K(KT_SHIFT,KG_ALTGR) +#define K_SHIFTL K(KT_SHIFT,KG_SHIFTL) +#define K_SHIFTR K(KT_SHIFT,KG_SHIFTR) +#define K_CTRLL K(KT_SHIFT,KG_CTRLL) +#define K_CTRLR K(KT_SHIFT,KG_CTRLR) +#define K_CAPSSHIFT K(KT_SHIFT,KG_CAPSSHIFT) + +#define K_ASC0 K(KT_ASCII,0) +#define K_ASC1 K(KT_ASCII,1) +#define K_ASC2 K(KT_ASCII,2) +#define K_ASC3 K(KT_ASCII,3) +#define K_ASC4 K(KT_ASCII,4) +#define K_ASC5 K(KT_ASCII,5) +#define K_ASC6 K(KT_ASCII,6) +#define K_ASC7 K(KT_ASCII,7) +#define K_ASC8 K(KT_ASCII,8) +#define K_ASC9 K(KT_ASCII,9) +#define K_HEX0 K(KT_ASCII,10) +#define K_HEX1 K(KT_ASCII,11) +#define K_HEX2 K(KT_ASCII,12) +#define K_HEX3 K(KT_ASCII,13) +#define K_HEX4 K(KT_ASCII,14) +#define K_HEX5 K(KT_ASCII,15) +#define K_HEX6 K(KT_ASCII,16) +#define K_HEX7 K(KT_ASCII,17) +#define K_HEX8 K(KT_ASCII,18) +#define K_HEX9 K(KT_ASCII,19) +#define K_HEXa K(KT_ASCII,20) +#define K_HEXb K(KT_ASCII,21) +#define K_HEXc K(KT_ASCII,22) +#define K_HEXd K(KT_ASCII,23) +#define K_HEXe K(KT_ASCII,24) +#define K_HEXf K(KT_ASCII,25) + +#define NR_ASCII 26 + +#define K_SHIFTLOCK K(KT_LOCK,KG_SHIFT) +#define K_CTRLLOCK K(KT_LOCK,KG_CTRL) +#define K_ALTLOCK K(KT_LOCK,KG_ALT) +#define K_ALTGRLOCK K(KT_LOCK,KG_ALTGR) +#define K_SHIFTLLOCK K(KT_LOCK,KG_SHIFTL) +#define K_SHIFTRLOCK K(KT_LOCK,KG_SHIFTR) +#define K_CTRLLLOCK K(KT_LOCK,KG_CTRLL) +#define K_CTRLRLOCK K(KT_LOCK,KG_CTRLR) + +#define K_SHIFT_SLOCK K(KT_SLOCK,KG_SHIFT) +#define K_CTRL_SLOCK K(KT_SLOCK,KG_CTRL) +#define K_ALT_SLOCK K(KT_SLOCK,KG_ALT) +#define K_ALTGR_SLOCK K(KT_SLOCK,KG_ALTGR) +#define K_SHIFTL_SLOCK K(KT_SLOCK,KG_SHIFTL) +#define K_SHIFTR_SLOCK K(KT_SLOCK,KG_SHIFTR) +#define K_CTRLL_SLOCK K(KT_SLOCK,KG_CTRLL) +#define K_CTRLR_SLOCK K(KT_SLOCK,KG_CTRLR) + +#define NR_LOCK 8 + +#define MAX_DIACR 256 + +extern struct kbdiacr accent_table[MAX_DIACR]; +extern unsigned int accent_table_size; + +/* kbd_kern.h --- header file from linux --- */ +extern int shift_state; + +extern char *func_table[MAX_NR_FUNC]; +extern char func_buf[]; +extern char *funcbufptr; +extern int funcbufsize, funcbufleft; + +/* + * kbd->xxx contains the VC-local things (flag settings etc..) + * + * Note: externally visible are LED_SCR, LED_NUM, LED_CAP defined in kd.h + * The code in KDGETLED / KDSETLED depends on the internal and + * external order being the same. + * + * Note: lockstate is used as index in the array key_map. + */ +struct kbd_struct { + + unsigned char lockstate; +/* 8 modifiers - the names do not have any meaning at all; + they can be associated to arbitrarily chosen keys */ +#define VC_SHIFTLOCK KG_SHIFT /* shift lock mode */ +#define VC_ALTGRLOCK KG_ALTGR /* altgr lock mode */ +#define VC_CTRLLOCK KG_CTRL /* control lock mode */ +#define VC_ALTLOCK KG_ALT /* alt lock mode */ +#define VC_SHIFTLLOCK KG_SHIFTL /* shiftl lock mode */ +#define VC_SHIFTRLOCK KG_SHIFTR /* shiftr lock mode */ +#define VC_CTRLLLOCK KG_CTRLL /* ctrll lock mode */ +#define VC_CTRLRLOCK KG_CTRLR /* ctrlr lock mode */ + unsigned char slockstate; /* for `sticky' Shift, Ctrl, etc. */ + + unsigned char ledmode:2; /* one 2-bit value */ +#define LED_SHOW_FLAGS 0 /* traditional state */ +#define LED_SHOW_IOCTL 1 /* only change leds upon ioctl */ +#define LED_SHOW_MEM 2 /* `heartbeat': peek into memory */ + + unsigned char ledflagstate:3; /* flags, not lights */ + unsigned char default_ledflagstate:3; +#define VC_SCROLLOCK 0 /* scroll-lock mode */ +#define VC_NUMLOCK 1 /* numeric lock mode */ +#define VC_CAPSLOCK 2 /* capslock mode */ + + unsigned char kbdmode:2; /* one 2-bit value */ +#define VC_XLATE 0 /* translate keycodes using keymap */ +#define VC_MEDIUMRAW 1 /* medium raw (keycode) mode */ +#define VC_RAW 2 /* raw (scancode) mode */ +#define VC_UNICODE 3 /* Unicode mode */ + + unsigned char modeflags:5; +#define VC_APPLIC 0 /* application key mode */ +#define VC_CKMODE 1 /* cursor key mode */ +#define VC_REPEAT 2 /* keyboard repeat */ +#define VC_CRLF 3 /* 0 - enter sends CR, 1 - enter sends CRLF */ +#define VC_META 4 /* 0 - meta, 1 - meta=prefix with ESC */ +}; + +extern struct kbd_struct kbd_table[]; + + +void kbd_set_driver_handler( + void ( *handler )( void *, unsigned short, unsigned long ) +); + +static inline void show_console(void) +{ +} + +static inline void set_console(int nr) +{ +} + +void set_leds(void); + +static inline int vc_kbd_mode(struct kbd_struct * kbd, int flag) +{ + return ((kbd->modeflags >> flag) & 1); +} + +static inline int vc_kbd_led(struct kbd_struct * kbd, int flag) +{ + return ((kbd->ledflagstate >> flag) & 1); +} + +static inline void set_vc_kbd_mode(struct kbd_struct * kbd, int flag) +{ + kbd->modeflags |= 1 << flag; +} + +static inline void set_vc_kbd_led(struct kbd_struct * kbd, int flag) +{ + kbd->ledflagstate |= 1 << flag; +} + +static inline void clr_vc_kbd_mode(struct kbd_struct * kbd, int flag) +{ + kbd->modeflags &= ~(1 << flag); +} + +static inline void clr_vc_kbd_led(struct kbd_struct * kbd, int flag) +{ + kbd->ledflagstate &= ~(1 << flag); +} + +static inline void chg_vc_kbd_lock(struct kbd_struct * kbd, int flag) +{ + kbd->lockstate ^= 1 << flag; +} + +static inline void chg_vc_kbd_slock(struct kbd_struct * kbd, int flag) +{ + kbd->slockstate ^= 1 << flag; +} + +static inline void chg_vc_kbd_mode(struct kbd_struct * kbd, int flag) +{ + kbd->modeflags ^= 1 << flag; +} + +static inline void chg_vc_kbd_led(struct kbd_struct * kbd, int flag) +{ + kbd->ledflagstate ^= 1 << flag; + set_leds(); +} + +#define U(x) ((x) ^ 0xf000) + +/* keyboard.c */ +int kbd_init(void); +int getkeycode(unsigned int scancode); +int setkeycode(unsigned int scancode, unsigned int keycode); +void compute_shiftstate(void); +unsigned char getledstate(void); +void setledstate(struct kbd_struct *kbd, unsigned int led); +void handle_scancode(unsigned char scancode, int down); + +/* kbd_parser.c */ +void register_kbd_msg_queue( char *qname, int port ); +void unregister_kbd_msg_queue( int port ); + +/* defkeymap.c */ +extern unsigned int keymap_count; + +/* inch.c */ +void add_to_queue( unsigned short ); +int getch( void ); +int BSP_wait_polled_input(void); +int rtems_kbpoll( void ); + +/* outch.c */ +void _IBMPC_initVideo(void); + +/* pc_keyb.c */ +void keyboard_interrupt(void *unused); + +/* vt.c */ +int vt_ioctl( unsigned int cmd, unsigned long arg); + +#endif diff --git a/bsps/i386/pc386/include/rtems/ps2_drv.h b/bsps/i386/pc386/include/rtems/ps2_drv.h new file mode 100644 index 0000000000..536b56a6ed --- /dev/null +++ b/bsps/i386/pc386/include/rtems/ps2_drv.h @@ -0,0 +1,79 @@ +/** + * @file + * + * @ingroup i386_pc386 + * + * @brief Paux driver routines. + */ + +#ifndef __paux_drv__ +#define __paux_drv__ +/*************************************************************************** + * + * Copyright (c) 1999 ConnectTel, Inc. All Rights Reserved. + * + * MODULE DESCRIPTION: Prototype routines for the paux driver. + * + * by: Rosimildo da Silva: + * rdasilva@connecttel.com + * http://www.connecttel.com + * + ****************************************************************************/ + +/* functions */ +#ifdef __cplusplus +extern "C" { +#endif + +/* paux prototype entry points */ +rtems_device_driver paux_initialize( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver paux_open( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver paux_control( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver paux_close( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver paux_read( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver paux_write( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver paux_control( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +#define PAUX_DRIVER_TABLE_ENTRY \ + { paux_initialize, paux_open, paux_close, \ + paux_read, paux_write, paux_control } + +#ifdef __cplusplus +} +#endif + +#endif /* __paux_drv__ */ diff --git a/bsps/i386/pc386/include/rtems/vgacons.h b/bsps/i386/pc386/include/rtems/vgacons.h new file mode 100644 index 0000000000..df7615bf5e --- /dev/null +++ b/bsps/i386/pc386/include/rtems/vgacons.h @@ -0,0 +1,49 @@ +/** + * @file + * + * @ingroup i386_pc386 + * + * @brief VGA definitions. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _VGACONS_H_ +#define _VGACONS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This is the ASCII for "PC" in the upper word and 0386 + * in the lower which should be unique enough to + * distinguish this type of serial device from others. + */ + +#define VGA_CONSOLE 0x80670386 + +#define VGACONS_UART0 0 +#define VGACONS_UART1 1 + +bool vgacons_probe( int minor ); + +/* + * Driver function table + */ +extern const console_fns vgacons_fns; + +#ifdef __cplusplus +} +#endif + +#endif /* _VGACONS_H_ */ diff --git a/bsps/i386/pc386/include/tm27.h b/bsps/i386/pc386/include/tm27.h new file mode 100644 index 0000000000..b53ab8e97a --- /dev/null +++ b/bsps/i386/pc386/include/tm27.h @@ -0,0 +1,38 @@ +/** + * @file + * + * @ingroup i386_pc386 + * + * @brief Implementation of interrupt mechanisms for Time Test 27. + */ + +/* + * tm27.h + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector(handler) + +#define Cause_tm27_intr() __asm__ volatile("int $0x90" : :); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/include/bsp/VME.h b/bsps/include/bsp/VME.h new file mode 100644 index 0000000000..bdaa45870e --- /dev/null +++ b/bsps/include/bsp/VME.h @@ -0,0 +1,133 @@ +/** + * @file + * + * @ingroup shared_vme + * + * @brief SVGM et al. BSP's VME support + */ + +#ifndef RTEMS_BSP_VME_API_H +#define RTEMS_BSP_VME_API_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2002, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include + +/* address modifiers & friends */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_vme VME related declarations + * + * @ingroup shared_vmeuniverse + * + * @brief BSP-specific configuration routine; sets up + * VME windows and installs the VME interrupt manager. + */ + +void BSP_vme_config(); + +/* translate through host bridge and vme master window of vme bridge */ +int +BSP_vme2local_adrs(unsigned long am, unsigned long vmeaddr, unsigned long *plocaladdr); + +/* how a CPU address is mapped to the VME bus (if at all) */ +int +BSP_local2vme_adrs(unsigned long am, unsigned long localaddr, unsigned long *pvmeaddr); + +/* interrupt handlers and levels */ +typedef void (*BSP_VME_ISR_t)(void *usrArg, unsigned long vector); + +int +BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *arg); +int +BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *arg); + +/* retrieve the currently installed ISR for a given vector */ +BSP_VME_ISR_t +BSP_getVME_isr(unsigned long vector, void **parg); + +int +BSP_enableVME_int_lvl(unsigned int level); + +int +BSP_disableVME_int_lvl(unsigned int level); + +int +BSP_VMEOutboundPortCfg( + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long pci_address, + unsigned long size); + +int +BSP_VMEInboundPortCfg( + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long pci_address, + unsigned long size); + +void +BSP_VMEOutboundPortsShow(FILE *f); + +void +BSP_VMEInboundPortsShow(FILE *f); + +/* Assert VME SYSRESET */ +void +BSP_VMEResetBus(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/VMEDMA.h b/bsps/include/bsp/VMEDMA.h new file mode 100644 index 0000000000..636f6d365c --- /dev/null +++ b/bsps/include/bsp/VMEDMA.h @@ -0,0 +1,309 @@ +/** + * @file + * + * @ingroup shared_vmedma + * + * @brief Public interface of DMA routines + */ + +#ifndef BSP_VME_DMA_H +#define BSP_VME_DMA_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2006, 2007 + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_vmedma VMEDMA Support + * + * @ingroup shared_vmeuniverse + * + * @brief VMEDMA Support Package + */ + + +/* NOTE: Access to DMA Channels is *not* protected / thread-safe. + * It is the responsability of the user to provide appropriate + * locking/serialization. + */ + +/* Simple abstraction of DMA controller setup / bus utilization: */ + +/* Since VME is the bottleneck, the settings for PCI are always + * chosen aggressively. + */ + + +/* Optimize for throughput; accept longer latencies: + * Choose a large block size (1k) and immediately re-request + * the bus at block boundaries. + */ +#define BSP_VMEDMA_OPT_THROUGHPUT 1 +/* Optimize for latency, accept throughput penalty: + * Choose a small block size (32b) and immediately re-request + * the bus at block boundaries. + */ +#define BSP_VMEDMA_OPT_LOWLATENCY 2 + +/* Optimize for bus sharing with other devices: + * Choose relatively small block size (128) and back off for 64us + * at each block boundary. + */ +#define BSP_VMEDMA_OPT_SHAREDBUS 3 + +/* Choose bridge default/reset configuration: + * (see manual) + */ +#define BSP_VMEDMA_OPT_DEFAULT 4 + +/* Provide custom configuration pass pointer to array + * with as many 32-bit words the particular bridge chip + * expects. + */ +#define BSP_VMEDMA_OPT_CUSTOM 5 + +/* VME Transfer modes */ + +/* Bitwise OR of the VME address-modifier/transfer-type + * with driver specific (no standard AM code for 2eVME and + * 2eSST defined) and optional special flags (see below) + */ + +/* Additional qualifiers: */ + +/* Don't increment VME address */ +#define BSP_VMEDMA_MODE_NOINC_VME (1<<20) +/* Don't increment PCI address */ +#define BSP_VMEDMA_MODE_NOINC_PCI (1<<21) + +/* Direction */ +#define BSP_VMEDMA_MODE_PCI2VME (1<<31) + +typedef void *BSP_VMEDmaListDescriptor; + +/* Program the device for the selected mode; + * + * 'bus_mode': one of the ...VMEDMA_OPT... choices + * listed above. + * 'xfer_mode': VME address-modifier optionally ORed with + * ...VMEDMA_MODE... bits listed above. + * 'custom': (only used if bus_mode is VMEDMA_OPT_CUSTOM) + * pointer to a list of setup parameters (chip-driver + * specific). + * + * RETURNS: 0 on success, nonzero on error (mode or channel + * unsupported). + * + * NOTES: The setup is preserved across multiple DMA transfers. + * It is the responsibility of the driver to reprogram + * the setup if the hardware does not preserve it. + * However - in linked list mode, some fields may be + * read from the list descriptors. + * + * Usually this routine must be used even in linked-list + * mode to program the 'bus_mode'. + * + * Direction of transfer is specified by a bit in the + * 'xfer_mode' (BSP_VMEDMA_MODE_PCI2VME). + */ +int +BSP_VMEDmaSetup(int channel, uint32_t bus_mode, uint32_t xfer_mode, void *custom_setup); + +/* Start direct (not linked-list) transfer. + * + * RETURNS: 0 on success, nonzero on failure + */ +int +BSP_VMEDmaStart(int channel, uint32_t pci_addr, uint32_t vme_addr, uint32_t n_bytes); + +/* Transfer status/result */ +#define BSP_VMEDMA_STATUS_OK 0 +/* Unsupported channel */ +#define BSP_VMEDMA_STATUS_UNSUP (-1) +/* Bus error on VME */ +#define BSP_VMEDMA_STATUS_BERR_VME 1 +/* Bus error on PCI */ +#define BSP_VMEDMA_STATUS_BERR_PCI 2 +/* Channel busy */ +#define BSP_VMEDMA_STATUS_BUSY 3 +/* Setup/programming error */ +#define BSP_VMEDMA_STATUS_PERR 4 +/* Other/unspecified error */ +#define BSP_VMEDMA_STATUS_OERR 5 + +/* Retrieve status of last transfer. + * + * RETURNS: 0 if the transfer was successful, + * nonzero on error (e.g., one of the + * values defined above). + * + * NOTE: Driver is allowed to pass other, + * device specific codes + */ + +uint32_t +BSP_VMEDmaStatus(int channel); + +/* + * Hook a callback (executed from ISR context) to DMA interrupt and + * enable it. + * If called with NULL callback then an existing callback is removed + * and the interrupt disabled. + * + * RETURNS: 0 on success, nonzero on failure (IRQ in use, unsupported + * channel). + */ +typedef void (*BSP_VMEDmaIRQCallback)(void *usr_arg); + +int +BSP_VMEDmaInstallISR(int channel, BSP_VMEDmaIRQCallback cb, void *usr_arg); + +/* + * DMA List operations. + * + * Note that the list is totally unprotected, i.e., the user is + * responsible for maintaining coherency against concurrent + * access by multiple threads or hardware. + * We assume the user builds/updates a list, hands it over to + * the hardware (list start command) and leaves it alone until + * the DMA controller is done with it. + */ + +/* Modify a list entry. If the list element pointer is NULL + * then a new list element is allocated. + * Only the fields with its corresponding bit set in the mask + * argument are touched. + * + * RETURNS: 'd' or newly allocated descriptor or NULL (no memory, + * or invalid setup). + */ +#define BSP_VMEDMA_MSK_ATTR (1<<0) +#define BSP_VMEDMA_MSK_PCIA (1<<1) +#define BSP_VMEDMA_MSK_VMEA (1<<2) +#define BSP_VMEDMA_MSK_BCNT (1<<3) +#define BSP_VMEDMA_MSK_ALL (0xf) +BSP_VMEDmaListDescriptor +BSP_VMEDmaListDescriptorSetup( + BSP_VMEDmaListDescriptor d, + uint32_t attr_mask, + uint32_t xfer_mode, + uint32_t pci_addr, + uint32_t vme_addr, + uint32_t n_bytes); + +/* De-allocate a list descriptor previously obtained by + * BSP_VMEDmaListDescriptorSetup(0,...); + * + * RETURNS: 0 on success, nonzero on failure (d currently on a list) + */ +int +BSP_VMEDmaListDescriptorDestroy(BSP_VMEDmaListDescriptor d); + +/* Traverse a list of descriptors and destroy all elements */ +int +BSP_VMEDmaListDestroy(BSP_VMEDmaListDescriptor anchor); + +/* Enqueue a list descriptor 'd' after 'tail' + * + * If 'tail' is NULL then 'd' is removed from + * the list it is currently on. + * + * RETURNS: 0 on success, nonzero if 'd' is already + * on a list (enqueue) or if it is not currently + * on a list (dequeue). + * + * NOTE: it is obviously the user's responsibility to update + * list queue/tail pointers when changing the + * structure of the list. + */ +int +BSP_VMEDmaListDescriptorEnq( + BSP_VMEDmaListDescriptor tail, + BSP_VMEDmaListDescriptor d); + +/* Obtain next and previous descriptors */ +BSP_VMEDmaListDescriptor +BSP_VMEDmaListDescriptorNext(BSP_VMEDmaListDescriptor d); + +BSP_VMEDmaListDescriptor +BSP_VMEDmaListDescriptorPrev(BSP_VMEDmaListDescriptor d); + +/* Set and get a 'usrData' pointer in the descriptor */ +void +BSP_VMEDmaListDescriptorSetUsr(BSP_VMEDmaListDescriptor d, void *usrData); + +void * +BSP_VMEDmaListDescriptorGetUsr(BSP_VMEDmaListDescriptor d); + +/* Refresh an entire list. Some DMA controllers modify certain + * fields (e.g., byte count) and this command restores the original + * setup. + */ + +int +BSP_VMEDmaListRefresh(BSP_VMEDmaListDescriptor anchor); + +/* Start linked-list operation. + * + * RETURNS: 0 on success, nonzero on failure + */ +int +BSP_VMEDmaListStart(int channel, BSP_VMEDmaListDescriptor list); + +#ifdef DEBUG +void +BSP_VMEDmaListDump(BSP_VMEDmaListDescriptor p); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/bootcard.h b/bsps/include/bsp/bootcard.h new file mode 100644 index 0000000000..aaac42e8e2 --- /dev/null +++ b/bsps/include/bsp/bootcard.h @@ -0,0 +1,188 @@ +/** + * @file + * + * @ingroup bsp_bootcard + * + * @brief Standard system startup. + */ + +/* + * Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_BOOTCARD_H +#define LIBBSP_SHARED_BOOTCARD_H + +#include + +#include +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup shared_bootcard Bootcard + * + * @ingroup bsp_shared + * + * @brief Standard system startup. + * + * @{ + */ + +/** + * @brief Global pointer to the command line of boot_card(). + */ +extern const char *bsp_boot_cmdline; + +void bsp_start(void); + +void bsp_predriver_hook(void); + +void bsp_reset(void); + +/** + * @brief Standard system initialization procedure. + * + * You may pass a command line in @a cmdline. It is later available via the + * global @ref bsp_boot_cmdline variable. + * + * This is the C entry point for ALL RTEMS BSPs. It is invoked from the + * assembly language initialization file usually called @c start.S which does + * the basic CPU setup (stack, C runtime environment, zero BSS, load other + * sections) and calls afterwards boot_card(). The boot card function provides + * the framework for the BSP initialization sequence. For the basic flow of + * initialization see RTEMS C User's Guide, Initialization Manager. + * + * This style of initialization ensures that the C++ global constructors are + * executed after RTEMS is initialized. + */ +void boot_card(const char *cmdline) RTEMS_NO_RETURN; + +#ifdef CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK + /** + * @brief Gives the BSP a chance to reduce the work area size with sbrk() + * adding more later. + * + * bsp_sbrk_init() may reduce the work area size passed in. The routine + * returns the 'sbrk_amount' to be used when extending the heap. Note that + * the return value may be zero. + * + * In case the @a area size is altered, then the remaining size of the + * @a area must be greater than or equal to @a min_size. + */ + ptrdiff_t bsp_sbrk_init(Heap_Area *area, uintptr_t min_size); +#endif + +static inline void bsp_work_area_initialize_default( + void *area_begin, + uintptr_t area_size +) +{ + Heap_Area area = { + .begin = area_begin, + .size = area_size + }; + + #if BSP_DIRTY_MEMORY == 1 + memset(area.begin, 0xCF, area.size); + #endif + + #ifdef CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK + { + uintptr_t overhead = _Heap_Area_overhead(CPU_HEAP_ALIGNMENT); + uintptr_t work_space_size = rtems_configuration_get_work_space_size(); + ptrdiff_t sbrk_amount = bsp_sbrk_init( + &area, + work_space_size + + overhead + + (rtems_configuration_get_unified_work_area() ? 0 : overhead) + ); + + rtems_heap_set_sbrk_amount(sbrk_amount); + } + #endif + + /* + * The following may be helpful in debugging what goes wrong when + * you are allocating the Work Area in a new BSP. + */ + #ifdef BSP_GET_WORK_AREA_DEBUG + { + void *sp = __builtin_frame_address(0); + void *end = (char *) area.begin + area.size; + printk( + "work_area_start = 0x%p\n" + "work_area_size = %lu 0x%08lx\n" + "end = 0x%p\n" + "current stack pointer = 0x%p%s\n", + area.begin, + (unsigned long) area.size, /* decimal */ + (unsigned long) area.size, /* hexadecimal */ + end, + sp, + (uintptr_t) sp >= (uintptr_t) area.begin + && (uintptr_t) sp <= (uintptr_t) end ? + " OVERLAPS!" : "" + ); + } + #endif + + _Workspace_Handler_initialization(&area, 1, NULL); + + #ifdef BSP_GET_WORK_AREA_DEBUG + printk( + "heap_start = 0x%p\n" + "heap_size = %lu\n", + area.begin, + (unsigned long) area.size + ); + #endif + + RTEMS_Malloc_Initialize(&area, 1, NULL); +} + +static inline void bsp_work_area_initialize_with_table( + Heap_Area *areas, + size_t area_count +) +{ + _Workspace_Handler_initialization(areas, area_count, _Heap_Extend); + RTEMS_Malloc_Initialize(areas, area_count, _Heap_Extend); +} + +void bsp_work_area_initialize(void); + +/** + * @brief Standard start routine for secondary processors. + * + * This function is usually called by low-level startup code of secondary + * processors or boot loaders starting a secondary processor. The final step + * of this function is a call to + * _SMP_Start_multitasking_on_secondary_processor(). + */ +void bsp_start_on_secondary_processor(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_BOOTCARD_H */ diff --git a/bsps/include/bsp/bspVmeDmaList.h b/bsps/include/bsp/bspVmeDmaList.h new file mode 100644 index 0000000000..414afab5c9 --- /dev/null +++ b/bsps/include/bsp/bspVmeDmaList.h @@ -0,0 +1,140 @@ +/** + * @file + * + * @ingroup shared_bspvmedmalist + * + * @brief This header should only be used inside a BSP + * chosing to use bspVmeDmaList for implementing VMEDMA.h + */ + +#ifndef BSP_VME_DMA_LIST_H +#define BSP_VME_DMA_LIST_H + + + +/* + * The bspVmeDmaList utility implements part of the API defined by + * 'VMEDMA.h' namely all 'VMEDmaListDescriptor' related entry points: + * + * BSP_VMEDmaListDescriptorDestroy(), + * BSP_VMEDmaListDestroy(), + * BSP_VMEDmaListDescriptorEnq(), + * BSP_VMEDmaListDescriptorNext(), + * BSP_VMEDmaListDescriptorPrev(), + * BSP_VMEDmaListDescriptorSetUsr(), + * BSP_VMEDmaListDescriptorGetUsr(), + * BSP_VMEDmaListRefresh() + * + * Also, it provides helper routines to assist BSPs with implementing + * + * BSP_VMEDmaListDescriptorSetup() + * + * and + * + * BSP_VMEDmaListStart() + * + * by providing + * + * BSP_VMEDmaListDescriptorNewTool(), + * BSP_VMEDmaListDescriptorSetupTool(), + * + * and + * + * BSP_VMEDmaListDescriptorStartTool() + */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2006, 2007 + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct VMEDmaListNodeRec_ *VMEDmaListNode; + +typedef struct VMEDmaListClassRec_ *VMEDmaListClass; + +/** + * @defgroup shared_bspvmedmalist Create and setup a new descriptor. + * + * @ingroup shared_vmeuniverse + * + * @brief The BSP must supply the appropriate controller class. + */ + +VMEDmaListNode +BSP_VMEDmaListDescriptorNewTool( + VMEDmaListClass pc, + uint32_t attr_mask, + uint32_t xfer_mode, + uint32_t pci_addr, + uint32_t vme_addr, + uint32_t n_bytes); + +/* Setup an existing descriptor */ +VMEDmaListNode +BSP_VMEDmaListDescriptorSetupTool( + VMEDmaListNode n, + uint32_t attr_mask, + uint32_t xfer_mode, + uint32_t pci_addr, + uint32_t vme_addr, + uint32_t n_bytes); + + +/* Start a list DMA transfer on 'controller'. The 'controller' information + * must be provided by the BSP. + */ +int +BSP_VMEDmaListDescriptorStartTool(volatile void *controller, int channel, VMEDmaListNode n); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/console-polled.h b/bsps/include/bsp/console-polled.h new file mode 100644 index 0000000000..09a99c30cb --- /dev/null +++ b/bsps/include/bsp/console-polled.h @@ -0,0 +1,43 @@ +/** + * @file + * + * @ingroup Console + * + * This file defines the interfaces between the single port + * polled console framework and the BSP. + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __BSP_CONSOLE_POLLED_h +#define __BSP_CONSOLE_POLLED_h + +/** + * This method polls the specified character @a ch to the specified + * console @a port. + * + * @param[in] port is the output port + * @param[in] ch is the character to print + */ +void console_outbyte_polled(int port, char ch); + +/** + * This method polls the specified @a port for an input character. + * console @a port. + * + * @param[in] port is the input port + * + * @return This method returns the character read of -1 if there is no data. + */ +int console_inbyte_nonblocking(int port); + +/** + * This method is invoked to initialize the console hardware device(s). + */ +void console_initialize_hardware(void); + +#endif diff --git a/bsps/include/bsp/console-termios.h b/bsps/include/bsp/console-termios.h new file mode 100644 index 0000000000..413dde4663 --- /dev/null +++ b/bsps/include/bsp/console-termios.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef BSP_CONSOLE_TERMIOS_H +#define BSP_CONSOLE_TERMIOS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup ConsoleTermios Termios Console Driver + * + * @ingroup TermiostypesSupport + * + * @brief Console driver for Termios devices. + * + * In order to use this driver add the following lines to the Makefile.am of + * the BSP: + * + * @code + * libbsp_a_SOURCES += ../../shared/console-termios-init.c + * libbsp_a_SOURCES += ../../shared/console-termios.c + * libbsp_a_SOURCES += console/console-config.c + * @endcode + * + * Define the console_device_table and console_device_count in the + * console-config.c file of the BSP. + * + * @{ + */ + +/** + * @brief Console device probe function type. + * + * @param[in] context The Termios device context. + * + * @retval true Install this device. + * @retval false Otherwise. + */ +typedef bool (*console_device_probe)(rtems_termios_device_context *context); + +/** + * @brief Console device information. + */ +typedef struct { + /** + * @brief The device file path. + * + * The "/dev/console" device will be automatically installed as the first + * device of console_device_table with a successful probe. + */ + const char *device_file; + + /** + * @brief The device probe function. + */ + console_device_probe probe; + + /** + * @brief The Termios device handler. + */ + const rtems_termios_device_handler *handler; + + /** + * @brief The Termios device flow control handler. + */ + const rtems_termios_device_flow *flow; + + /** + * @brief The Termios device context. + */ + rtems_termios_device_context *context; +} console_device; + +/** + * @brief Returns true and does nothing else. + */ +bool console_device_probe_default(rtems_termios_device_context *context); + +/** + * @brief Table for console devices installed via console_initialize() during + * system initialization. + * + * It must be provided by the BSP. + * + * @see console_device_count. + */ +extern const console_device console_device_table[]; + +/** + * @brief Count of entries in the console_device_table. + * + * It must be provided by the BSP. + */ +extern const size_t console_device_count; + +/** @{ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* BSP_CONSOLE_TERMIOS_H */ diff --git a/bsps/include/bsp/default-initial-extension.h b/bsps/include/bsp/default-initial-extension.h new file mode 100644 index 0000000000..1c795b7278 --- /dev/null +++ b/bsps/include/bsp/default-initial-extension.h @@ -0,0 +1,53 @@ +/** + * @file + * + * @ingroup shared_defaultinitialextension + * + * @brief DEFAULT_INITIAL_EXTENSION Support + */ + +/* + * Copyright (c) 2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_DEFAULT_INITIAL_EXTENSION_H +#define LIBBSP_SHARED_DEFAULT_INITIAL_EXTENSION_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup shared_defaultinitialextension DEFAULT_INITIAL_EXTENSION Support + * + * @ingroup shared_include + * + * @brief DEFAULT_INITIAL_EXTENSION Support Package + */ + +void bsp_fatal_extension( + rtems_fatal_source source, + bool always_set_to_false, + rtems_fatal_code error +); + +#define BSP_INITIAL_EXTENSION \ + { NULL, NULL, NULL, NULL, NULL, NULL, NULL, bsp_fatal_extension, NULL } + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_DEFAULT_INITIAL_EXTENSION_H */ diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h new file mode 100644 index 0000000000..ca2e39aba8 --- /dev/null +++ b/bsps/include/bsp/fatal.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2012, 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_BSP_FATAL_H +#define LIBBSP_SHARED_BSP_FATAL_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FATAL_CODE_BLOCK(idx) ((unsigned long) (idx) * 256UL) + +/** + * @brief BSP fatal error codes. + */ +typedef enum { + /* Generic BSP fatal codes */ + BSP_FATAL_INTERRUPT_INITIALIZATION = BSP_FATAL_CODE_BLOCK(0), + BSP_FATAL_SPURIOUS_INTERRUPT, + BSP_FATAL_CONSOLE_MULTI_INIT, + BSP_FATAL_CONSOLE_NO_MEMORY_0, + BSP_FATAL_CONSOLE_NO_MEMORY_1, + BSP_FATAL_CONSOLE_NO_MEMORY_2, + BSP_FATAL_CONSOLE_NO_MEMORY_3, + BSP_FATAL_CONSOLE_REGISTER_DEV_0, + BSP_FATAL_CONSOLE_REGISTER_DEV_1, + BSP_FATAL_CONSOLE_NO_DEV, + BSP_FATAL_CONSOLE_INSTALL_0, + BSP_FATAL_CONSOLE_INSTALL_1, + BSP_FATAL_CONSOLE_REGISTER_DEV_2, + + /* ARM fatal codes */ + BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(1), + BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE, + BSP_ARM_PL111_FATAL_REGISTER_DEV, + BSP_ARM_PL111_FATAL_SEM_CREATE, + BSP_ARM_PL111_FATAL_SEM_RELEASE, + BSP_ARM_A9MPCORE_FATAL_CLOCK_SMP_INIT, + BSP_ARM_ARMV7M_CPU_COUNTER_INIT, + BSP_ARM_FATAL_GENERIC_TIMER_CLOCK_IRQ_INSTALL, + + /* LEON3 fatal codes */ + LEON3_FATAL_NO_IRQMP_CONTROLLER = BSP_FATAL_CODE_BLOCK(2), + LEON3_FATAL_CONSOLE_REGISTER_DEV, + LEON3_FATAL_CLOCK_INITIALIZATION, + LEON3_FATAL_INVALID_CACHE_CONFIG_MAIN_PROCESSOR, + LEON3_FATAL_INVALID_CACHE_CONFIG_SECONDARY_PROCESSOR, + LEON3_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT, + + /* LPC24XX fatal codes */ + LPC24XX_FATAL_PL111_SET_UP = BSP_FATAL_CODE_BLOCK(3), + LPC24XX_FATAL_PL111_PINS_SET_UP, + LPC24XX_FATAL_PL111_PINS_TEAR_DOWN, + LPC24XX_FATAL_PL111_TEAR_DOWN, + + /* MPC5200 fatal codes */ + MPC5200_FATAL_PCF8563_INVALID_YEAR = BSP_FATAL_CODE_BLOCK(4), + MPC5200_FATAL_SLICETIMER_0_IRQ_INSTALL, + MPC5200_FATAL_SLICETIMER_1_IRQ_INSTALL, + MPC5200_FATAL_TM27_IRQ_INSTALL, + MPC5200_FATAL_MSCAN_A_INIT, + MPC5200_FATAL_MSCAN_B_INIT, + MPC5200_FATAL_MSCAN_A_SET_MODE, + MPC5200_FATAL_MSCAN_B_SET_MODE, + MPC5200_FATAL_ATA_DISK_IO_INIT, + MPC5200_FATAL_ATA_DISK_CREATE, + MPC5200_FATAL_ATA_DMA_SINGLE_IRQ_INSTALL, + MPC5200_FATAL_ATA_LOCK_CREATE, + MPC5200_FATAL_ATA_LOCK_DESTROY, + + /* MPC55XX fatal codes */ + MPC55XX_FATAL_FMPLL_LOCK = BSP_FATAL_CODE_BLOCK(5), + MPC55XX_FATAL_CLOCK_EMIOS_IRQ_INSTALL, + MPC55XX_FATAL_CLOCK_EMIOS_PRESCALER, + MPC55XX_FATAL_CLOCK_EMIOS_INTERVAL, + MPC55XX_FATAL_CLOCK_PIT_IRQ_INSTALL, + MPC55XX_FATAL_CONSOLE_GENERIC_COUNT, + MPC55XX_FATAL_CONSOLE_GENERIC_REGISTER, + MPC55XX_FATAL_CONSOLE_GENERIC_REGISTER_CONSOLE, + MPC55XX_FATAL_CONSOLE_ESCI_BAUD, + MPC55XX_FATAL_CONSOLE_ESCI_ATTRIBUTES, + MPC55XX_FATAL_CONSOLE_ESCI_IRQ_INSTALL, + MPC55XX_FATAL_CONSOLE_LINFLEX_BAUD, + MPC55XX_FATAL_CONSOLE_LINFLEX_ATTRIBUTES, + MPC55XX_FATAL_CONSOLE_LINFLEX_RX_IRQ_INSTALL, + MPC55XX_FATAL_CONSOLE_LINFLEX_TX_IRQ_INSTALL, + MPC55XX_FATAL_CONSOLE_LINFLEX_ERR_IRQ_INSTALL, + MPC55XX_FATAL_CONSOLE_LINFLEX_RX_IRQ_REMOVE, + MPC55XX_FATAL_CONSOLE_LINFLEX_TX_IRQ_REMOVE, + MPC55XX_FATAL_CONSOLE_LINFLEX_ERR_IRQ_REMOVE, + MPC55XX_FATAL_EDMA_IRQ_INSTALL, + MPC55XX_FATAL_EDMA_IRQ_REMOVE, + + /* MRM332 fatal codes */ + MRM332_FATAL_SPURIOUS_INTERRUPT = BSP_FATAL_CODE_BLOCK(6), + + /* PowerPC fatal codes */ + PPC_FATAL_EXCEPTION_INITIALIZATION = BSP_FATAL_CODE_BLOCK(7), + + /* Libchip fatal codes */ + DWMAC_FATAL_TOO_MANY_RBUFS_CONFIGURED = BSP_FATAL_CODE_BLOCK(8), + + /* ARM fatal codes */ + ARM_FATAL_L2C_310_UNEXPECTED_ID = BSP_FATAL_CODE_BLOCK(9), + ARM_FATAL_L2C_310_UNEXPECTED_NUM_WAYS, + ARM_FATAL_L2C_310_EXCLUSIVE_CONFIG, + + /* QorIQ fatal codes */ + QORIQ_FATAL_SMP_IPI_HANDLER_INSTALL = BSP_FATAL_CODE_BLOCK(10), + QORIQ_FATAL_FDT_NO_BUS_FREQUENCY, + QORIQ_FATAL_FDT_NO_CLOCK_FREQUENCY, + QORIQ_FATAL_FDT_NO_TIMEBASE_FREQUENCY, + QORIQ_FATAL_RESTART_FAILED, + QORIQ_FATAL_RESTART_INSTALL_INTERRUPT, + QORIQ_FATAL_RESTART_INTERRUPT_FAILED, + + /* ATSAM fatal codes */ + ATSAM_FATAL_XDMA_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(11), + ATSAM_FATAL_PIO_IRQ_A, + ATSAM_FATAL_PIO_IRQ_B, + ATSAM_FATAL_PIO_IRQ_C, + ATSAM_FATAL_PIO_IRQ_D, + ATSAM_FATAL_PIO_IRQ_E, + ATSAM_FATAL_PIO_CONFIGURE_IT, + + /* i.MX fatal codes */ + IMX_FATAL_GENERIC_TIMER_FREQUENCY = BSP_FATAL_CODE_BLOCK(12) +} bsp_fatal_code; + +RTEMS_NO_RETURN static inline void +bsp_fatal( bsp_fatal_code code ) +{ + rtems_fatal( RTEMS_FATAL_SOURCE_BSP, (rtems_fatal_code) code ); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_BSP_FATAL_H */ diff --git a/bsps/include/bsp/fdt.h b/bsps/include/bsp/fdt.h new file mode 100644 index 0000000000..4ed05b136c --- /dev/null +++ b/bsps/include/bsp/fdt.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_FDT_H +#define LIBBSP_SHARED_FDT_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * BSPs that implement the FDT support functions must define + * BSP_FDT_IS_SUPPORTED. + */ + +/** + * @brief Copies the specified source FDT to a dedicated global data area. + * + * The source FDT is usually provided by a bootloader and may be located in a + * memory area that is used by the program. The low-level initialization + * should copy the FDT for later use. + * + * The copy can be accessed by bsp_fdt_get(). + * + * @param[in] src The source FDT. + */ +void bsp_fdt_copy(const void *src); + +/** + * @brief Returns the FDT of the BSP. + * + * @return The FDT of the BSP. + */ +const void *bsp_fdt_get(void); + +/** + * @brief Maps the interrupt number of the FDT to the interrupt vector used by + * the interrupt management. + * + * This function is used by the libbsd to implement the OFW_BUS_MAP_INTR bus + * method. + * + * @param[in] intr The FDT interrupt number cells. + * @param[in] icells The FDT interrupt cell count. + * + * @return The interrupt vector of the FDT interrupt number. + */ +uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_FDT_H */ diff --git a/bsps/include/bsp/gpio.h b/bsps/include/bsp/gpio.h new file mode 100644 index 0000000000..64a877ae7a --- /dev/null +++ b/bsps/include/bsp/gpio.h @@ -0,0 +1,955 @@ +/** + * @file gpio.h + * + * @ingroup rtems_gpio + * + * @brief RTEMS GPIO API definition. + */ + +/* + * Copyright (c) 2014-2015 Andre Marques + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_GPIO_H +#define LIBBSP_SHARED_GPIO_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if !defined(BSP_GPIO_PIN_COUNT) || !defined(BSP_GPIO_PINS_PER_BANK) + #error "BSP_GPIO_PIN_COUNT or BSP_GPIO_PINS_PER_BANK is not defined." +#endif + +#if BSP_GPIO_PIN_COUNT <= 0 || BSP_GPIO_PINS_PER_BANK <= 0 + #error "Invalid BSP_GPIO_PIN_COUNT or BSP_GPIO_PINS_PER_BANK." +#endif + +#if BSP_GPIO_PINS_PER_BANK > 32 + #error "Invalid BSP_GPIO_PINS_PER_BANK. Must be in the range of 1 to 32." +#endif + +#define GPIO_LAST_BANK_PINS BSP_GPIO_PIN_COUNT % BSP_GPIO_PINS_PER_BANK + +#if GPIO_LAST_BANK_PINS > 0 + #define GPIO_BANK_COUNT (BSP_GPIO_PIN_COUNT / BSP_GPIO_PINS_PER_BANK) + 1 +#else + #define GPIO_BANK_COUNT BSP_GPIO_PIN_COUNT / BSP_GPIO_PINS_PER_BANK + #undef GPIO_LAST_BANK_PINS + #define GPIO_LAST_BANK_PINS BSP_GPIO_PINS_PER_BANK +#endif + +#if defined(BSP_GPIO_PINS_PER_SELECT_BANK) && BSP_GPIO_PINS_PER_SELECT_BANK > 32 + #error "Invalid BSP_GPIO_PINS_PER_SELECT_BANK. Must under and including 32." +#elif defined(BSP_GPIO_PINS_PER_SELECT_BANK) <= 32 + #define GPIO_SELECT_BANK_COUNT \ + BSP_GPIO_PINS_PER_BANK / BSP_GPIO_PINS_PER_SELECT_BANK +#endif + +#define INTERRUPT_SERVER_PRIORITY 1 +#define INTERRUPT_SERVER_STACK_SIZE 2 * RTEMS_MINIMUM_STACK_SIZE +#define INTERRUPT_SERVER_MODES RTEMS_TIMESLICE | RTEMS_PREEMPT +#define INTERRUPT_SERVER_ATTRIBUTES RTEMS_DEFAULT_ATTRIBUTES + +#define GPIO_INPUT_ERROR ~0 + +/** + * @name GPIO data structures + * + * @{ + */ + +/** + * @brief The set of possible configurations for a GPIO pull-up resistor. + * + * Enumerated type to define the possible pull-up resistor configurations + * for a GPIO pin. + */ +typedef enum +{ + PULL_UP = 1, + PULL_DOWN, + NO_PULL_RESISTOR +} rtems_gpio_pull_mode; + +/** + * @brief The set of possible functions a pin can have. + * + * Enumerated type to define a pin function. + */ +typedef enum +{ + DIGITAL_INPUT = 0, + DIGITAL_OUTPUT, + BSP_SPECIFIC, + NOT_USED +} rtems_gpio_function; + +/** + * @brief The set of possible interrupts a GPIO pin can generate. + * + * Enumerated type to define a GPIO pin interrupt. + */ +typedef enum +{ + FALLING_EDGE = 0, + RISING_EDGE, + LOW_LEVEL, + HIGH_LEVEL, + BOTH_EDGES, + BOTH_LEVELS, + NONE +} rtems_gpio_interrupt; + +/** + * @brief The set of possible handled states an user-defined interrupt + * handler can return. + * + * Enumerated type to define an interrupt handler handled state. + */ +typedef enum +{ + IRQ_HANDLED, + IRQ_NONE +} rtems_gpio_irq_state; + +/** + * @brief The set of flags to specify an user-defined interrupt handler + * uniqueness on a GPIO pin. + * + * Enumerated type to define an interrupt handler shared flag. + */ +typedef enum +{ + SHARED_HANDLER, + UNIQUE_HANDLER +} rtems_gpio_handler_flag; + +/** + * @brief Object containing relevant information for assigning a BSP specific + * function to a pin. + * + * Encapsulates relevant data for a BSP specific GPIO function. + */ +typedef struct +{ + /* The BSP defined function code. */ + uint32_t io_function; + + void *pin_data; +} rtems_gpio_specific_data; + +/** + * @brief Object containing configuration information + * regarding interrupts. + */ +typedef struct +{ + rtems_gpio_interrupt active_interrupt; + + rtems_gpio_handler_flag handler_flag; + + bool threaded_interrupts; + + /* Interrupt handler function. */ + rtems_gpio_irq_state (*handler) (void *arg); + + /* Interrupt handler function arguments. */ + void *arg; + + /* Software switch debounce settings. It should contain the amount of clock + * ticks that must pass between interrupts to ensure that the interrupt + * was not caused by a switch bounce. + * If set to 0 this feature is disabled . */ + uint32_t debounce_clock_tick_interval; +} rtems_gpio_interrupt_configuration; + +/** + * @brief Object containing configuration information + * to request/update a GPIO pin. + */ +typedef struct +{ + /* Processor pin number. */ + uint32_t pin_number; + rtems_gpio_function function; + + /* Pull resistor setting. */ + rtems_gpio_pull_mode pull_mode; + + /* If digital out pin, set to TRUE to set the pin to logical high, + * or FALSE for logical low. If not a digital out then this + * is ignored. */ + bool output_enabled; + + /* If true inverts digital in/out applicational logic. */ + bool logic_invert; + + /* Pin interrupt configuration. Should be NULL if not used. */ + rtems_gpio_interrupt_configuration *interrupt; + + /* Structure with BSP specific data, to use during the pin request. + * If function == BSP_SPECIFIC this should have a pointer to + * a rtems_gpio_specific_data structure. + * + * If not this field may be NULL. This is passed to the BSP function + * so any BSP specific data can be passed to it through this pointer. */ + void *bsp_specific; +} rtems_gpio_pin_conf; + +/** + * @brief Object containing configuration information + * to assign GPIO functions to multiple pins + * at the same time. To be used by BSP code only. + */ +typedef struct +{ + /* Global GPIO pin number. */ + uint32_t pin_number; + + /* RTEMS GPIO pin function code. */ + rtems_gpio_function function; + + /* BSP specific function code. Only used if function == BSP_SPECIFIC */ + uint32_t io_function; + + /* BSP specific data. */ + void *bsp_specific; +} rtems_gpio_multiple_pin_select; + +/** + * @brief Object containing configuration information + * to request a GPIO pin group. + */ +typedef struct +{ + const rtems_gpio_pin_conf *digital_inputs; + uint32_t input_count; + + const rtems_gpio_pin_conf *digital_outputs; + uint32_t output_count; + + const rtems_gpio_pin_conf *bsp_specifics; + uint32_t bsp_specific_pin_count; +} rtems_gpio_group_definition; + +/** + * @brief Opaque type for a GPIO pin group. + */ +typedef struct rtems_gpio_group rtems_gpio_group; + +/** @} */ + +/** + * @name gpio Usage + * + * @{ + */ + +/** + * @brief Initializes the GPIO API. + * + * @retval RTEMS_SUCCESSFUL API successfully initialized. + * @retval * @see rtems_semaphore_create(). + */ +extern rtems_status_code rtems_gpio_initialize(void); + +/** + * @brief Instantiates a GPIO pin group. + * To define the group @see rtems_gpio_define_pin_group(). + * + * @retval rtems_gpio_group pointer. + */ +extern rtems_gpio_group *rtems_gpio_create_pin_group(void); + +/** + * @brief Requests a GPIO pin group configuration. + * + * @param[in] group_definition rtems_gpio_group_definition structure filled with + * the group pins configurations. + * @param[out] group Reference to the created group. + * + * @retval RTEMS_SUCCESSFUL Pin group was configured successfully. + * @retval RTEMS_UNSATISFIED @var group_definition or @var group is NULL, + * the @var pins are not from the same bank, + * no pins were defined or could not satisfy at + * least one given configuration. + * @retval RTEMS_RESOURCE_IN_USE At least one pin is already being used. + * @retval * @see rtems_semaphore_create(). + */ +extern rtems_status_code rtems_gpio_define_pin_group( + const rtems_gpio_group_definition *group_definition, + rtems_gpio_group *group +); + +/** + * @brief Writes a value to the group's digital outputs. The pins order + * is as defined in the group definition. + * + * @param[in] data Data to write/send. + * @param[in] group Reference to the group. + * + * @retval RTEMS_SUCCESSFUL Data successfully written. + * @retval RTEMS_NOT_DEFINED Group has no output pins. + * @retval RTEMS_UNSATISFIED Could not operate on at least one of the pins. + */ +extern rtems_status_code rtems_gpio_write_group( + uint32_t data, + rtems_gpio_group *group +); + +/** + * @brief Reads the value/level of the group's digital inputs. The pins order + * is as defined in the group definition. + * + * @param[in] group Reference to the group. + * + * @retval The function returns a 32-bit bitmask with the group's input pins + * current logical values. + * @retval GPIO_INPUT_ERROR Group has no input pins. + */ +extern uint32_t rtems_gpio_read_group(rtems_gpio_group *group); + +/** + * @brief Performs a BSP specific operation on a group of pins. The pins order + * is as defined in the group definition. + * + * @param[in] group Reference to the group. + * @param[in] arg Pointer to a BSP defined structure with BSP-specific + * data. This field is handled by the BSP. + * + * @retval RTEMS_SUCCESSFUL Operation completed with success. + * @retval RTEMS_NOT_DEFINED Group has no BSP specific pins, or the BSP does not + * support BSP specific operations for groups. + * @retval RTEMS_UNSATISFIED Could not operate on at least one of the pins. + */ +extern rtems_status_code rtems_gpio_group_bsp_specific_operation( + rtems_gpio_group *group, + void *arg +); + +/** + * @brief Requests a GPIO pin configuration. + * + * @param[in] conf rtems_gpio_pin_conf structure filled with the pin information + * and desired configurations. + * + * @retval RTEMS_SUCCESSFUL Pin was configured successfully. + * @retval RTEMS_UNSATISFIED Could not satisfy the given configuration. + */ +extern rtems_status_code rtems_gpio_request_configuration( + const rtems_gpio_pin_conf *conf +); + +/** + * @brief Updates the current configuration of a GPIO pin . + * + * @param[in] conf rtems_gpio_pin_conf structure filled with the pin information + * and desired configurations. + * + * @retval RTEMS_SUCCESSFUL Pin configuration was updated successfully. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED The pin is not being used. + * @retval RTEMS_UNSATISFIED Could not update the pin's configuration. + */ +extern rtems_status_code rtems_gpio_update_configuration( + const rtems_gpio_pin_conf *conf +); + +/** + * @brief Sets multiple output GPIO pins with the logical high. + * + * @param[in] pin_numbers Array with the GPIO pin numbers to set. + * @param[in] count Number of GPIO pins to set. + * + * @retval RTEMS_SUCCESSFUL All pins were set successfully. + * @retval RTEMS_INVALID_ID At least one pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED At least one of the received pins + * is not configured as a digital output. + * @retval RTEMS_UNSATISFIED Could not set the GPIO pins. + */ +extern rtems_status_code rtems_gpio_multi_set( + uint32_t *pin_numbers, + uint32_t pin_count +); + +/** + * @brief Sets multiple output GPIO pins with the logical low. + * + * @param[in] pin_numbers Array with the GPIO pin numbers to clear. + * @param[in] count Number of GPIO pins to clear. + * + * @retval RTEMS_SUCCESSFUL All pins were cleared successfully. + * @retval RTEMS_INVALID_ID At least one pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED At least one of the received pins + * is not configured as a digital output. + * @retval RTEMS_UNSATISFIED Could not clear the GPIO pins. + */ +extern rtems_status_code rtems_gpio_multi_clear( + uint32_t *pin_numbers, + uint32_t pin_count +); + +/** + * @brief Returns the value (level) of multiple GPIO input pins. + * + * @param[in] pin_numbers Array with the GPIO pin numbers to read. + * @param[in] count Number of GPIO pins to read. + * + * @retval Bitmask with the values of the corresponding pins. + * 0 for logical low and 1 for logical high. + * @retval GPIO_INPUT_ERROR Could not read at least one pin level. + */ +extern uint32_t rtems_gpio_multi_read( + uint32_t *pin_numbers, + uint32_t pin_count +); + +/** + * @brief Sets an output GPIO pin with the logical high. + * + * @param[in] pin_number GPIO pin number. + * + * @retval RTEMS_SUCCESSFUL Pin was set successfully. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED The received pin is not configured + * as a digital output. + * @retval RTEMS_UNSATISFIED Could not set the GPIO pin. + */ +extern rtems_status_code rtems_gpio_set(uint32_t pin_number); + +/** + * @brief Sets an output GPIO pin with the logical low. + * + * @param[in] pin_number GPIO pin number. + * + * @retval RTEMS_SUCCESSFUL Pin was cleared successfully. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED The received pin is not configured + * as a digital output. + * @retval RTEMS_UNSATISFIED Could not clear the GPIO pin. + */ +extern rtems_status_code rtems_gpio_clear(uint32_t pin_number); + +/** + * @brief Returns the value (level) of a GPIO input pin. + * + * @param[in] pin_number GPIO pin number. + * + * @retval The function returns 0 or 1 depending on the pin current + * logical value. + * @retval -1 Pin number is invalid, or not a digital input pin. + */ +extern int rtems_gpio_get_value(uint32_t pin_number); + +/** + * @brief Requests multiple GPIO pin configurations. If the BSP provides + * support for parallel selection each call to this function will + * result in a single call to the GPIO hardware, else each pin + * configuration will be done in individual and sequential calls. + * All pins must belong to the same GPIO bank. + * + * @param[in] pins Array of rtems_gpio_pin_conf structures filled with the pins + * information and desired configurations. All pins must belong + * to the same GPIO bank. + * @param[in] pin_count Number of pin configurations in the @var pins array. + * + * @retval RTEMS_SUCCESSFUL All pins were configured successfully. + * @retval RTEMS_INVALID_ID At least one pin number in the @var pins array + * is invalid. + * @retval RTEMS_RESOURCE_IN_USE At least one pin is already being used. + * @retval RTEMS_UNSATISFIED Could not satisfy at least one given configuration. + */ +extern rtems_status_code rtems_gpio_multi_select( + const rtems_gpio_pin_conf *pins, + uint8_t pin_count +); + +/** + * @brief Assigns a certain function to a GPIO pin. + * + * @param[in] pin_number GPIO pin number. + * @param[in] function The new function for the pin. + * @param[in] output_enabled If TRUE and @var function is DIGITAL_OUTPUT, + * then the pin is set with the logical high. + * Otherwise it is set with logical low. + * @param[in] logic_invert Reverses the digital I/O logic for DIGITAL_INPUT + * and DIGITAL_OUTPUT pins. + * @param[in] bsp_specific Pointer to a BSP defined structure with BSP-specific + * data. This field is handled by the BSP. + * + * @retval RTEMS_SUCCESSFUL Pin was configured successfully. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_RESOURCE_IN_USE The received pin is already being used. + * @retval RTEMS_UNSATISFIED Could not assign the GPIO function. + * @retval RTEMS_NOT_DEFINED GPIO function not defined, or NOT_USED. + */ +extern rtems_status_code rtems_gpio_request_pin( + uint32_t pin_number, + rtems_gpio_function function, + bool output_enable, + bool logic_invert, + void *bsp_specific +); + +/** + * @brief Configures a single GPIO pin pull resistor. + * + * @param[in] pin_number GPIO pin number. + * @param[in] mode The pull resistor mode. + * + * @retval RTEMS_SUCCESSFUL Pull resistor successfully configured. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_UNSATISFIED Could not set the pull mode. + */ +extern rtems_status_code rtems_gpio_resistor_mode( + uint32_t pin_number, + rtems_gpio_pull_mode mode +); + +/** + * @brief Releases a GPIO pin, making it available to be used again. + * + * @param[in] pin_number GPIO pin number. + * + * @retval RTEMS_SUCCESSFUL Pin successfully disabled. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval * Could not disable an active interrupt on this pin, + * @see rtems_gpio_disable_interrupt(). + */ +extern rtems_status_code rtems_gpio_release_pin(uint32_t pin_number); + +/** + * @brief Releases a GPIO pin, making it available to be used again. + * + * @param[in] conf GPIO pin configuration to be released. + * + * @retval RTEMS_SUCCESSFUL Pin successfully disabled. + * @retval RTEMS_UNSATISFIED Pin configuration is NULL. + * @retval * @see rtems_gpio_release_pin(). + */ +extern rtems_status_code rtems_gpio_release_configuration( + const rtems_gpio_pin_conf *conf +); + +/** + * @brief Releases multiple GPIO pins, making them available to be used again. + * + * @param[in] pins Array of rtems_gpio_pin_conf structures. + * @param[in] pin_count Number of pin configurations in the @var pins array. + * + * @retval RTEMS_SUCCESSFUL Pins successfully disabled. + * @retval RTEMS_UNSATISFIED @var pins array is NULL. + * @retval * @see rtems_gpio_release_pin(). + */ +extern rtems_status_code rtems_gpio_release_multiple_pins( + const rtems_gpio_pin_conf *pins, + uint32_t pin_count +); + +/** + * @brief Releases a GPIO pin group, making the pins used available to be + * repurposed. + * + * @param[in] conf GPIO pin configuration to be released. + * + * @retval RTEMS_SUCCESSFUL Pins successfully disabled. + * @retval * @see rtems_gpio_release_pin(), @see rtems_semaphore_delete() or + * @see rtems_semaphore_flush(). + */ +extern rtems_status_code rtems_gpio_release_pin_group( + rtems_gpio_group *group +); + +/** + * @brief Attaches a debouncing function to a given pin/switch. + * Debouncing is done by requiring a certain number of clock ticks to + * pass between interrupts. Any interrupt fired too close to the last + * will be ignored as it is probably the result of an involuntary + * switch/button bounce after being released. + * + * @param[in] pin_number GPIO pin number. + * @param[in] ticks Minimum number of clock ticks that must pass between + * interrupts so it can be considered a legitimate + * interrupt. + * + * @retval RTEMS_SUCCESSFUL Debounce function successfully attached to the pin. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED The current pin is not configured as a digital + * input, hence it can not be connected to a switch, + * or interrupts are not enabled for this pin. + */ +extern rtems_status_code rtems_gpio_debounce_switch( + uint32_t pin_number, + int ticks +); + +/** + * @brief Connects a new user-defined interrupt handler to a given pin. + * + * @param[in] pin_number GPIO pin number. + * @param[in] handler Pointer to a function that will be called every time + * the enabled interrupt for the given pin is generated. + * This function must return information about its + * handled/unhandled state. + * @param[in] arg Void pointer to the arguments of the user-defined handler. + * + * @retval RTEMS_SUCCESSFUL Handler successfully connected to this pin. + * @retval RTEMS_NO_MEMORY Could not connect more user-defined handlers to + * the given pin. + * @retval RTEMS_NOT_CONFIGURED The given pin has no interrupt configured. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_TOO_MANY The pin's current handler is set as unique. + * @retval RTEMS_RESOURCE_IN_USE The current user-defined handler for this pin + * is unique. + */ +extern rtems_status_code rtems_gpio_interrupt_handler_install( + uint32_t pin_number, + rtems_gpio_irq_state (*handler) (void *arg), + void *arg +); + +/** + * @brief Enables interrupts to be generated on a given GPIO pin. + * When fired that interrupt will call the given handler. + * + * @param[in] pin_number GPIO pin number. + * @param[in] interrupt Type of interrupt to enable for the pin. + * @param[in] flag Defines the uniqueness of the interrupt handler for the pin. + * @param[in] threaded_handling Defines if the handler should be called from a + * thread/task or from normal ISR contex. + * @param[in] handler Pointer to a function that will be called every time + * @var interrupt is generated. This function must return + * information about its handled/unhandled state. + * @param[in] arg Void pointer to the arguments of the user-defined handler. + * + * @retval RTEMS_SUCCESSFUL Interrupt successfully enabled for this pin. + * @retval RTEMS_UNSATISFIED Could not install the GPIO ISR, create/start + * the handler task, or enable the interrupt + * on the pin. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED The received pin is not configured + * as a digital input, the pin is on a + * pin grouping. + * @retval RTEMS_RESOURCE_IN_USE The pin already has an enabled interrupt, + * or the handler threading policy does not match + * the bank's policy. + * @retval RTEMS_NO_MEMORY Could not store the pin's interrupt configuration. + */ +extern rtems_status_code rtems_gpio_enable_interrupt( + uint32_t pin_number, + rtems_gpio_interrupt interrupt, + rtems_gpio_handler_flag flag, + bool threaded_handling, + rtems_gpio_irq_state (*handler) (void *arg), + void *arg +); + +/** + * @brief Disconnects an user-defined interrupt handler from the given pin. + * If in the end there are no more user-defined handlers connected + * to the pin, interrupts are disabled on the given pin. + * + * @param[in] pin_number GPIO pin number. + * @param[in] handler Pointer to the user-defined handler + * @param[in] arg Void pointer to the arguments of the user-defined handler. + * + * @retval RTEMS_SUCCESSFUL Handler successfully disconnected from this pin. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED Pin has no active interrupts. + * @retval * @see rtems_gpio_disable_interrupt() + */ +extern rtems_status_code rtems_gpio_interrupt_handler_remove( + uint32_t pin_number, + rtems_gpio_irq_state (*handler) (void *arg), + void *arg +); + +/** + * @brief Stops interrupts from being generated on a given GPIO pin + * and removes the corresponding handler. + * + * @param[in] pin_number GPIO pin number. + * + * @retval RTEMS_SUCCESSFUL Interrupt successfully disabled for this pin. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED Pin has no active interrupts. + * @retval RTEMS_UNSATISFIED Could not remove the current interrupt handler, + * could not recognize the current active interrupt + * on this pin or could not disable interrupts on + * this pin. + */ +extern rtems_status_code rtems_gpio_disable_interrupt(uint32_t pin_number); + +/** + * @brief Sets multiple output GPIO pins with the logical high. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] bitmask Bitmask of GPIO pins to set in the given bank. + * + * @retval RTEMS_SUCCESSFUL All pins were set successfully. + * @retval RTEMS_UNSATISFIED Could not set at least one of the pins. + */ +extern rtems_status_code rtems_gpio_bsp_multi_set( + uint32_t bank, + uint32_t bitmask +); + +/** + * @brief Sets multiple output GPIO pins with the logical low. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] bitmask Bitmask of GPIO pins to clear in the given bank. + * + * @retval RTEMS_SUCCESSFUL All pins were cleared successfully. + * @retval RTEMS_UNSATISFIED Could not clear at least one of the pins. + */ +extern rtems_status_code rtems_gpio_bsp_multi_clear( + uint32_t bank, + uint32_t bitmask +); + +/** + * @brief Returns the value (level) of multiple GPIO input pins. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] bitmask Bitmask of GPIO pins to read in the given bank. + * + * @retval The function must return a bitmask with the values of the + * corresponding pins. 0 for logical low and 1 for logical high. + * @retval GPIO_INPUT_ERROR Could not read at least one pin level. + */ +extern uint32_t rtems_gpio_bsp_multi_read(uint32_t bank, uint32_t bitmask); + +/** + * @brief Performs a BSP specific operation on a group of pins. + * The implementation for this function may be omitted if the target + * does not support the feature, by returning RTEMS_NOT_DEFINED. + * + * @param[in] bank GPIO bank number. + * @param[in] pins Array filled with BSP specific pin numbers. All pins belong + * to the same select bank. + * @param[in] pin_count Number of pin configurations in the @var pins array. + * @param[in] arg Pointer to a BSP defined structure with BSP-specific + * data. This field is handled by the BSP. + * + * @retval RTEMS_SUCCESSFUL Operation completed with success. + * @retval RTEMS_NOT_DEFINED Group has no BSP specific pins, or the BSP does not + * support BSP specific operations for groups. + * @retval RTEMS_UNSATISFIED Could not operate on at least one of the pins. + */ +extern rtems_status_code rtems_gpio_bsp_specific_group_operation( + uint32_t bank, + uint32_t *pins, + uint32_t pin_count, + void *arg +); + +/** + * @brief Assigns GPIO functions to all the given pins in a single register + * operation. + * The implementation for this function may be omitted if the target + * does not support the feature, by returning RTEMS_NOT_DEFINED. + * + * @param[in] pins Array of rtems_gpio_multiple_pin_select structures filled + * with the pins desired functions. All pins belong to the + * same select bank. + * @param[in] pin_count Number of pin configurations in the @var pins array. + * @param[in] select_bank Select bank number of the received pins. + * + * @retval RTEMS_SUCCESSFUL Functions were assigned successfully. + * @retval RTEMS_NOT_DEFINED The BSP does not support multiple pin function + * assignment. + * @retval RTEMS_UNSATISFIED Could not assign the functions to the pins. + */ +extern rtems_status_code rtems_gpio_bsp_multi_select( + rtems_gpio_multiple_pin_select *pins, + uint32_t pin_count, + uint32_t select_bank +); + +/** + * @brief Sets an output GPIO pin with the logical high. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * + * @retval RTEMS_SUCCESSFUL Pin was set successfully. + * @retval RTEMS_UNSATISFIED Could not set the given pin. + */ +extern rtems_status_code rtems_gpio_bsp_set(uint32_t bank, uint32_t pin); + +/** + * @brief Sets an output GPIO pin with the logical low. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * + * @retval RTEMS_SUCCESSFUL Pin was cleared successfully. + * @retval RTEMS_UNSATISFIED Could not clear the given pin. + */ +extern rtems_status_code rtems_gpio_bsp_clear(uint32_t bank, uint32_t pin); + +/** + * @brief Returns the value (level) of a GPIO input pin. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * + * @retval The function must return 0 if the pin level is a logical low, + * or non zero if it has a logical high. + * @retval GPIO_INPUT_ERROR Could not read the pin level. + */ +extern uint32_t rtems_gpio_bsp_get_value(uint32_t bank, uint32_t pin); + +/** + * @brief Assigns the digital input function to the given pin. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * @param[in] bsp_specific Pointer to a BSP defined structure with BSP-specific + * data. + * + * @retval RTEMS_SUCCESSFUL Function was assigned successfully. + * @retval RTEMS_UNSATISFIED Could not assign the function to the pin. + */ +extern rtems_status_code rtems_gpio_bsp_select_input( + uint32_t bank, + uint32_t pin, + void *bsp_specific +); + +/** + * @brief Assigns the digital output function to the given pin. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * @param[in] bsp_specific Pointer to a BSP defined structure with BSP-specific + * data. + * + * @retval RTEMS_SUCCESSFUL Function was assigned successfully. + * @retval RTEMS_UNSATISFIED Could not assign the function to the pin. + */ +extern rtems_status_code rtems_gpio_bsp_select_output( + uint32_t bank, + uint32_t pin, + void *bsp_specific +); + +/** + * @brief Assigns a BSP specific function to the given pin. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * @param[in] function BSP defined GPIO function. + * @param[in] pin_data Pointer to a BSP defined structure with BSP-specific + * data. + * + * @retval RTEMS_SUCCESSFUL Function was assigned successfully. + * @retval RTEMS_UNSATISFIED Could not assign the function to the pin. + */ +extern rtems_status_code rtems_gpio_bsp_select_specific_io( + uint32_t bank, + uint32_t pin, + uint32_t function, + void *pin_data +); + +/** + * @brief Configures a single GPIO pin pull resistor. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * @param[in] mode The pull resistor mode. + * + * @retval RTEMS_SUCCESSFUL Pull resistor successfully configured. + * @retval RTEMS_UNSATISFIED Could not set the pull mode. + */ +extern rtems_status_code rtems_gpio_bsp_set_resistor_mode( + uint32_t bank, + uint32_t pin, + rtems_gpio_pull_mode mode +); + +/** + * @brief Reads and returns a vector/bank interrupt event line. + * The bitmask should indicate with a 1 if the corresponding pin + * as a pending interrupt, or 0 if otherwise. The function + * should clear the interrupt event line before returning. + * This must be implemented by each BSP. + * + * @param[in] vector GPIO vector/bank. + * + * @retval Bitmask (max 32-bit) representing a GPIO bank, where a bit set + * indicates an active interrupt on that pin. + */ +extern uint32_t rtems_gpio_bsp_interrupt_line(rtems_vector_number vector); + +/** + * @brief Calculates a vector number for a given GPIO bank. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * + * @retval The corresponding rtems_vector_number. + */ +extern rtems_vector_number rtems_gpio_bsp_get_vector(uint32_t bank); + +/** + * @brief Enables interrupts to be generated on a given GPIO pin. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * @param[in] interrupt Type of interrupt to enable for the pin. + * + * @retval RTEMS_SUCCESSFUL Interrupt successfully enabled for this pin. + * @retval RTEMS_UNSATISFIED Could not enable the interrupt on the pin. + */ +extern rtems_status_code rtems_gpio_bsp_enable_interrupt( + uint32_t bank, + uint32_t pin, + rtems_gpio_interrupt interrupt +); + +/** + * @brief Stops interrupts from being generated on a given GPIO pin. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * @param[in] active_interrupt Interrupt type currently active on this pin. + * + * @retval RTEMS_SUCCESSFUL Interrupt successfully disabled for this pin. + * @retval RTEMS_UNSATISFIED Could not disable interrupts on this pin. + */ +extern rtems_status_code rtems_gpio_bsp_disable_interrupt( + uint32_t bank, + uint32_t pin, + rtems_gpio_interrupt interrupt +); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_GPIO_H */ diff --git a/bsps/include/bsp/irq-generic.h b/bsps/include/bsp/irq-generic.h new file mode 100644 index 0000000000..187aea84d1 --- /dev/null +++ b/bsps/include/bsp/irq-generic.h @@ -0,0 +1,304 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief Generic BSP interrupt support API. + */ + +/* + * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette. + * + * Copyright (c) 2008, 2017 embedded brains GmbH. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * Copyright (c) 2016 Chris Johns + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_IRQ_GENERIC_H +#define LIBBSP_SHARED_IRQ_GENERIC_H + +#include + +#include +#include + +#ifdef RTEMS_SMP + #include +#endif + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if !defined(BSP_INTERRUPT_VECTOR_MIN) || !defined(BSP_INTERRUPT_VECTOR_MAX) || (BSP_INTERRUPT_VECTOR_MAX + 1) < BSP_INTERRUPT_VECTOR_MIN + #error "invalid BSP_INTERRUPT_VECTOR_MIN or BSP_INTERRUPT_VECTOR_MAX" +#endif + +#if defined(BSP_INTERRUPT_USE_INDEX_TABLE) && !defined(BSP_INTERRUPT_HANDLER_TABLE_SIZE) + #error "if you define BSP_INTERRUPT_USE_INDEX_TABLE, you have to define BSP_INTERRUPT_HANDLER_TABLE_SIZE etc. as well" +#endif + +#if defined(BSP_INTERRUPT_NO_HEAP_USAGE) && !defined(BSP_INTERRUPT_USE_INDEX_TABLE) + #error "if you define BSP_INTERRUPT_NO_HEAP_USAGE, you have to define BSP_INTERRUPT_USE_INDEX_TABLE etc. as well" +#endif + +#define BSP_INTERRUPT_VECTOR_NUMBER \ + (BSP_INTERRUPT_VECTOR_MAX - BSP_INTERRUPT_VECTOR_MIN + 1) + +#ifndef BSP_INTERRUPT_HANDLER_TABLE_SIZE + #define BSP_INTERRUPT_HANDLER_TABLE_SIZE BSP_INTERRUPT_VECTOR_NUMBER +#endif + +/* Internal macros for SMP support, do not use externally */ +#ifdef RTEMS_SMP + #define bsp_interrupt_disable(level) do { (void) level; } while (0) + #define bsp_interrupt_enable(level) do { } while (0) + #define bsp_interrupt_fence(order) _Atomic_Fence(order) +#else + #define bsp_interrupt_disable(level) rtems_interrupt_disable(level) + #define bsp_interrupt_enable(level) rtems_interrupt_enable(level) + #define bsp_interrupt_fence(order) do { } while (0) +#endif + +#define bsp_interrupt_assert(e) _Assert(e) + +struct bsp_interrupt_handler_entry { + rtems_interrupt_handler handler; + void *arg; + const char *info; + struct bsp_interrupt_handler_entry *next; +}; + +typedef struct bsp_interrupt_handler_entry bsp_interrupt_handler_entry; + +extern bsp_interrupt_handler_entry bsp_interrupt_handler_table []; + +#ifdef BSP_INTERRUPT_USE_INDEX_TABLE + #if BSP_INTERRUPT_HANDLER_TABLE_SIZE < 0x100 + typedef uint8_t bsp_interrupt_handler_index_type; + #elif BSP_INTERRUPT_HANDLER_TABLE_SIZE < 0x10000 + typedef uint16_t bsp_interrupt_handler_index_type; + #else + typedef uint32_t bsp_interrupt_handler_index_type; + #endif + extern bsp_interrupt_handler_index_type bsp_interrupt_handler_index_table []; +#endif + +static inline rtems_vector_number bsp_interrupt_handler_index( + rtems_vector_number vector +) +{ + #ifdef BSP_INTERRUPT_USE_INDEX_TABLE + return bsp_interrupt_handler_index_table [vector - BSP_INTERRUPT_VECTOR_MIN]; + #else + return vector - BSP_INTERRUPT_VECTOR_MIN; + #endif +} + +/** + * @defgroup bsp_interrupt BSP Interrupt Support + * + * @ingroup bsp_shared + * + * @brief Generic BSP Interrupt Support + * + * The BSP interrupt support manages a sequence of interrupt vector numbers + * ranging from @ref BSP_INTERRUPT_VECTOR_MIN to @ref BSP_INTERRUPT_VECTOR_MAX + * including the end points. It provides methods to + * @ref bsp_interrupt_handler_install() "install", + * @ref bsp_interrupt_handler_remove() "remove" and + * @ref bsp_interrupt_handler_dispatch() "dispatch" interrupt handlers for each + * vector number. It implements parts of the RTEMS interrupt manager. + * + * The entry points to a list of interrupt handlers are stored in a table + * (= handler table). + * + * You have to configure the BSP interrupt support in the file + * for each BSP. For a minimum configuration you have to provide + * @ref BSP_INTERRUPT_VECTOR_MIN and @ref BSP_INTERRUPT_VECTOR_MAX. + * + * For boards with small memory requirements you can define + * @ref BSP_INTERRUPT_USE_INDEX_TABLE. With an enabled index table the handler + * table will be accessed via a small index table. You can define the size of + * the handler table with @ref BSP_INTERRUPT_HANDLER_TABLE_SIZE. + * + * Normally new list entries are allocated from the heap. You may define + * @ref BSP_INTERRUPT_NO_HEAP_USAGE, if you do not want to use the heap. For + * this option you have to define @ref BSP_INTERRUPT_USE_INDEX_TABLE as well. + * + * You have to provide some special routines in your BSP (follow the links for + * the details): + * - bsp_interrupt_facility_initialize() + * - bsp_interrupt_vector_enable() + * - bsp_interrupt_vector_disable() + * - bsp_interrupt_handler_default() + * + * The following now deprecated functions are provided for backward + * compatibility: + * - BSP_get_current_rtems_irq_handler() + * - BSP_install_rtems_irq_handler() + * - BSP_install_rtems_shared_irq_handler() + * - BSP_remove_rtems_irq_handler() + * - BSP_rtems_irq_mngt_set() + * - BSP_rtems_irq_mngt_get() + * + * @{ + */ + +#ifdef BSP_INTERRUPT_CUSTOM_VALID_VECTOR + bool bsp_interrupt_is_valid_vector(rtems_vector_number vector); +#else + /** + * @brief Returns true if the interrupt vector with number @a vector is + * valid. + */ + static inline bool bsp_interrupt_is_valid_vector(rtems_vector_number vector) + { + return (rtems_vector_number) BSP_INTERRUPT_VECTOR_MIN <= vector + && vector <= (rtems_vector_number) BSP_INTERRUPT_VECTOR_MAX; + } +#endif + +/** + * @brief Default interrupt handler. + * + * This routine will be called from bsp_interrupt_handler_dispatch() with the + * current vector number @a vector when the handler list for this vector is + * empty or the vector number is out of range. + * + * @note This function must cope with arbitrary vector numbers @a vector. + */ +void bsp_interrupt_handler_default(rtems_vector_number vector); + +/** + * @brief Initialize BSP interrupt support. + * + * You must call this function before you can install, remove and dispatch + * interrupt handlers. There is no protection against concurrent + * initialization. This function must be called at most once. The BSP + * specific bsp_interrupt_facility_initialize() function will be called after + * all internals are initialized. If the BSP specific initialization fails, + * then this is a fatal error. The fatal error source is + * RTEMS_FATAL_SOURCE_BSP and the fatal error code is + * BSP_FATAL_INTERRUPT_INITIALIZATION. + */ +void bsp_interrupt_initialize(void); + +/** + * @brief BSP specific initialization. + * + * This routine will be called form bsp_interrupt_initialize() and shall do the + * following: + * - Initialize the facilities that call bsp_interrupt_handler_dispatch(). For + * example on PowerPC the external exception handler. + * - Initialize the interrupt controller. You shall set the interrupt + * controller in a state such that interrupts are disabled for all vectors. + * The vectors will be enabled with your bsp_interrupt_vector_enable() function + * and disabled via your bsp_interrupt_vector_disable() function. These + * functions have to work afterwards. + * + * @return On success RTEMS_SUCCESSFUL shall be returned. + */ +rtems_status_code bsp_interrupt_facility_initialize(void); + +/** + * @brief Enables the interrupt vector with number @a vector. + * + * This function shall enable the vector at the corresponding facility (in most + * cases the interrupt controller). It will be called then the first handler + * is installed for the vector in bsp_interrupt_handler_install() for example. + * + * @note The implementation should use + * bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)) to valdiate the + * vector number. + * + * @note You must not install or remove an interrupt handler in this function. + * This may result in a deadlock. + */ +void bsp_interrupt_vector_enable(rtems_vector_number vector); + +/** + * @brief Disables the interrupt vector with number @a vector. + * + * This function shall disable the vector at the corresponding facility (in + * most cases the interrupt controller). It will be called then the last + * handler is removed for the vector in bsp_interrupt_handler_remove() for + * example. + * + * @note The implementation should use + * bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)) to valdiate the + * vector number. + * + * @note You must not install or remove an interrupt handler in this function. + * This may result in a deadlock. + */ +void bsp_interrupt_vector_disable(rtems_vector_number vector); + +/** + * @brief Sequencially calls all interrupt handlers for the vector number @a + * vector. + * + * If the vector number is out of range or the handler list is empty + * bsp_interrupt_handler_default() will be called with argument @a vector. + * + * You can call this function within every context which can be disabled via + * rtems_interrupt_disable(). + */ +static inline void bsp_interrupt_handler_dispatch(rtems_vector_number vector) +{ + if (bsp_interrupt_is_valid_vector(vector)) { + const bsp_interrupt_handler_entry *e = + &bsp_interrupt_handler_table [bsp_interrupt_handler_index(vector)]; + + do { + rtems_interrupt_handler handler; + void *arg; + + arg = e->arg; + bsp_interrupt_fence(ATOMIC_ORDER_ACQUIRE); + handler = e->handler; + (*handler)(arg); + + e = e->next; + } while (e != NULL); + } else { + bsp_interrupt_handler_default(vector); + } +} + +/** + * @brief Is interrupt handler empty. + * + * This routine returns true if the handler is empty and has not been + * initialised else false is returned. The interrupt lock is not used + * so this call can be used from within interrupts. + * + * @return If empty true shall be returned else false is returned. + */ +bool bsp_interrupt_handler_is_empty(rtems_vector_number vector); + +/** @} */ + +/* For internal use only */ +void bsp_interrupt_lock(void); + +/* For internal use only */ +void bsp_interrupt_unlock(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_IRQ_GENERIC_H */ diff --git a/bsps/include/bsp/irq-info.h b/bsps/include/bsp/irq-info.h new file mode 100644 index 0000000000..ea6d629e76 --- /dev/null +++ b/bsps/include/bsp/irq-info.h @@ -0,0 +1,56 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief Generic BSP interrupt information API. + */ + +/* + * Copyright (c) 2008, 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_IRQ_INFO_H +#define LIBBSP_SHARED_IRQ_INFO_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Prints interrupt information via the printk plugin @a print with the + * context @a context. + */ +void bsp_interrupt_report_with_plugin( + const rtems_printer *printer +); + +/** + * @brief Prints interrupt information via the default printk plugin. + */ +void bsp_interrupt_report(void); + +/** + * @brief Shell command entry for interrupt information. + */ +extern struct rtems_shell_cmd_tt bsp_interrupt_shell_command; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_IRQ_INFO_H */ diff --git a/bsps/include/bsp/mm.h b/bsps/include/bsp/mm.h new file mode 100644 index 0000000000..2152f686ba --- /dev/null +++ b/bsps/include/bsp/mm.h @@ -0,0 +1,41 @@ +/** + * @file + * + * @ingroup shared_mm + * + * @brief MM Support + */ + +/* + * Copyright (c) 2013 Hesham AL-Matary. + * Copyright (c) 2013 Gedare Bloom. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LIBBSP_MM_H +#define __LIBBSP_MM_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_mm MM Support + * + * @ingroup shared_include + * + * @brief MM Support Package + */ + +void bsp_memory_management_initialize(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsps/include/bsp/stackalloc.h b/bsps/include/bsp/stackalloc.h new file mode 100644 index 0000000000..89414c8e6e --- /dev/null +++ b/bsps/include/bsp/stackalloc.h @@ -0,0 +1,94 @@ +/** + * @file + * + * @ingroup bsp_stack + * + * @brief Task stack initialization, allocation and free functions. + */ + +/* + * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_STACK_ALLOC_H +#define LIBBSP_SHARED_STACK_ALLOC_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup bsp_stack Task Stack Allocator + * + * @ingroup bsp_shared + * + * @brief Task stack initialization, allocation and free functions. + * + * Initialize the task stack allocator with bsp_stack_initialize(). To enable + * the task stack allocator use the following in the system configuration: + * + * @code + * #include + * + * #define CONFIGURE_INIT + * + * #include + * @endcode + * + * @{ + */ + +/** + * @brief Task stack allocator initialization for + * @ref CONFIGURE_TASK_STACK_ALLOCATOR_INIT. + */ +void bsp_stack_allocate_init(size_t stack_space_size); + +/** + * @brief Task stack allocator for @ref CONFIGURE_TASK_STACK_ALLOCATOR. + * + * In case the designated task stack space from bsp_stack_initialize() is + * completely in use the work space will be used to allocate the stack. + */ +void *bsp_stack_allocate(size_t size); + +/** + * @brief Task stack free function for @ref CONFIGURE_TASK_STACK_DEALLOCATOR. + */ +void bsp_stack_free(void *stack); + +/** + * @brief Task stack allocator initialization configuration option. + */ +#define CONFIGURE_TASK_STACK_ALLOCATOR_INIT bsp_stack_allocate_init + +/** + * @brief Task stack allocator configuration option. + */ +#define CONFIGURE_TASK_STACK_ALLOCATOR bsp_stack_allocate + +/** + * @brief Task stack deallocator configuration option. + */ +#define CONFIGURE_TASK_STACK_DEALLOCATOR bsp_stack_free + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_STACK_ALLOC_H */ diff --git a/bsps/include/bsp/u-boot.h b/bsps/include/bsp/u-boot.h new file mode 100644 index 0000000000..866cd9bbb0 --- /dev/null +++ b/bsps/include/bsp/u-boot.h @@ -0,0 +1,66 @@ +/** + * @file + * + * @ingroup shared_uboot + * + * @brief U_BOOT Support + */ + +/* + * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_U_BOOT_H +#define LIBBSP_SHARED_U_BOOT_H + +#include + +#include +#include + +#ifdef U_BOOT_64_BIT_PHYS_SIZE + typedef uint64_t phys_size_t; +#else + typedef unsigned long phys_size_t; +#endif + +#ifdef U_BOOT_GENERIC_BOARD_INFO + #include +#else + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern bd_t bsp_uboot_board_info; + +/** + * @defgroup shared_uboot U_BOOT Support + * + * @ingroup shared_include + * + * @brief U_BOOT Support Package + */ + +void bsp_uboot_copy_board_info(const bd_t *src); + +/* FIXME: Do not use this function */ +void dumpUBootBDInfo(bd_t *u); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_U_BOOT_H */ diff --git a/bsps/include/bsp/uart-output-char.h b/bsps/include/bsp/uart-output-char.h new file mode 100644 index 0000000000..a6648d1ad4 --- /dev/null +++ b/bsps/include/bsp/uart-output-char.h @@ -0,0 +1,60 @@ +/** + * @file + * + * @ingroup bsp_kit + * + * @brief Output character definitions for standard UARTs. + */ + +/* + * Copyright (c) 2010 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_UART_OUTPUT_CHAR_H +#define LIBBSP_SHARED_UART_OUTPUT_CHAR_H + +#include + +#include + +#define CONSOLE_RBR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x00)) +#define CONSOLE_THR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x00)) +#define CONSOLE_DLL (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x00)) +#define CONSOLE_DLM (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x04)) +#define CONSOLE_IER (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x04)) +#define CONSOLE_IIR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x08)) +#define CONSOLE_FCR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x08)) +#define CONSOLE_LCR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x0C)) +#define CONSOLE_MCR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x10)) +#define CONSOLE_LSR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x14)) +#define CONSOLE_SCR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x1C)) +#define CONSOLE_ACR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x20)) +#define CONSOLE_ICR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x24)) +#define CONSOLE_FDR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x28)) +#define CONSOLE_TER (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x30)) + +#define CONSOLE_LSR_RDR 0x1 +#define CONSOLE_LSR_THRE 0x20 +#define CONSOLE_LSR_TEMT 0x40 + +#define BSP_CONSOLE_UART_INIT(dll) \ + do { \ + CONSOLE_LCR = 0x00; \ + CONSOLE_IER = 0x00; \ + CONSOLE_LCR = 0x80; \ + CONSOLE_DLL = (dll & 0xFF); \ + CONSOLE_DLM = (dll >> 8); \ + CONSOLE_LCR = 0x03; \ + CONSOLE_FCR = 0x07; \ + } while (0) + +#endif /* LIBBSP_SHARED_UART_OUTPUT_CHAR_H */ diff --git a/bsps/include/bsp/utility.h b/bsps/include/bsp/utility.h new file mode 100644 index 0000000000..fee28f445a --- /dev/null +++ b/bsps/include/bsp/utility.h @@ -0,0 +1,156 @@ +/** + * @file + * + * @ingroup bsp_kit + * + * @brief Utility macros. + */ + +/* + * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_SHARED_UTILITY_H +#define LIBCPU_SHARED_UTILITY_H + +#include + +#define BSP_BIT8(bit) \ + ((uint8_t) (((unsigned int) 1) << (bit))) + +#define BSP_MSK8(first_bit, last_bit) \ + ((uint8_t) ((BSP_BIT8((last_bit) - (first_bit) + 1) - 1) << (first_bit))) + +#define BSP_FLD8(val, first_bit, last_bit) \ + ((uint8_t) \ + ((((unsigned int) (val)) << (first_bit)) & BSP_MSK8(first_bit, last_bit))) + +#define BSP_FLD8GET(reg, first_bit, last_bit) \ + ((uint8_t) (((reg) & BSP_MSK8(first_bit, last_bit)) >> (first_bit))) + +#define BSP_FLD8SET(reg, val, first_bit, last_bit) \ + ((uint8_t) (((reg) & ~BSP_MSK8(first_bit, last_bit)) \ + | BSP_FLD8(val, first_bit, last_bit))) + +#define BSP_BIT16(bit) \ + ((uint16_t) (((unsigned int) 1) << (bit))) + +#define BSP_MSK16(first_bit, last_bit) \ + ((uint16_t) ((BSP_BIT16((last_bit) - (first_bit) + 1) - 1) << (first_bit))) + +#define BSP_FLD16(val, first_bit, last_bit) \ + ((uint16_t) \ + ((((unsigned int) (val)) << (first_bit)) & BSP_MSK16(first_bit, last_bit))) + +#define BSP_FLD16GET(reg, first_bit, last_bit) \ + ((uint16_t) (((reg) & BSP_MSK16(first_bit, last_bit)) >> (first_bit))) + +#define BSP_FLD16SET(reg, val, first_bit, last_bit) \ + ((uint16_t) (((reg) & ~BSP_MSK16(first_bit, last_bit)) \ + | BSP_FLD16(val, first_bit, last_bit))) + +#define BSP_BIT32(bit) \ + ((uint32_t) (((uint32_t) 1) << (bit))) + +#define BSP_MSK32(first_bit, last_bit) \ + ((uint32_t) ((BSP_BIT32((last_bit) - (first_bit) + 1) - 1) << (first_bit))) + +#define BSP_FLD32(val, first_bit, last_bit) \ + ((uint32_t) \ + ((((uint32_t) (val)) << (first_bit)) & BSP_MSK32(first_bit, last_bit))) + +#define BSP_FLD32GET(reg, first_bit, last_bit) \ + ((uint32_t) (((reg) & BSP_MSK32(first_bit, last_bit)) >> (first_bit))) + +#define BSP_FLD32SET(reg, val, first_bit, last_bit) \ + ((uint32_t) (((reg) & ~BSP_MSK32(first_bit, last_bit)) \ + | BSP_FLD32(val, first_bit, last_bit))) + +#define BSP_BIT64(bit) \ + ((uint64_t) (((uint64_t) 1) << (bit))) + +#define BSP_MSK64(first_bit, last_bit) \ + ((uint64_t) ((BSP_BIT64((last_bit) - (first_bit) + 1) - 1) << (first_bit))) + +#define BSP_FLD64(val, first_bit, last_bit) \ + ((uint64_t) \ + ((((uint64_t) (val)) << (first_bit)) & BSP_MSK64(first_bit, last_bit))) + +#define BSP_FLD64GET(reg, first_bit, last_bit) \ + ((uint64_t) (((reg) & BSP_MSK64(first_bit, last_bit)) >> (first_bit))) + +#define BSP_FLD64SET(reg, val, first_bit, last_bit) \ + ((uint64_t) (((reg) & ~BSP_MSK64(first_bit, last_bit)) \ + | BSP_FLD64(val, first_bit, last_bit))) + +#define BSP_BBIT8(bit) \ + BSP_BIT8(7 - (bit)) + +#define BSP_BMSK8(first_bit, last_bit) \ + BSP_MSK8(7 - (last_bit), 7 - (first_bit)) + +#define BSP_BFLD8(val, first_bit, last_bit) \ + BSP_FLD8(val, 7 - (last_bit), 7 - (first_bit)) + +#define BSP_BFLD8GET(reg, first_bit, last_bit) \ + BSP_FLD8GET(reg, 7 - (last_bit), 7 - (first_bit)) + +#define BSP_BFLD8SET(reg, val, first_bit, last_bit) \ + BSP_FLD8SET(reg, val, 7 - (last_bit), 7 - (first_bit)) + +#define BSP_BBIT16(bit) \ + BSP_BIT16(15 - (bit)) + +#define BSP_BMSK16(first_bit, last_bit) \ + BSP_MSK16(15 - (last_bit), 15 - (first_bit)) + +#define BSP_BFLD16(val, first_bit, last_bit) \ + BSP_FLD16(val, 15 - (last_bit), 15 - (first_bit)) + +#define BSP_BFLD16GET(reg, first_bit, last_bit) \ + BSP_FLD16GET(reg, 15 - (last_bit), 15 - (first_bit)) + +#define BSP_BFLD16SET(reg, val, first_bit, last_bit) \ + BSP_FLD16SET(reg, val, 15 - (last_bit), 15 - (first_bit)) + +#define BSP_BBIT32(bit) \ + BSP_BIT32(31 - (bit)) + +#define BSP_BMSK32(first_bit, last_bit) \ + BSP_MSK32(31 - (last_bit), 31 - (first_bit)) + +#define BSP_BFLD32(val, first_bit, last_bit) \ + BSP_FLD32(val, 31 - (last_bit), 31 - (first_bit)) + +#define BSP_BFLD32GET(reg, first_bit, last_bit) \ + BSP_FLD32GET(reg, 31 - (last_bit), 31 - (first_bit)) + +#define BSP_BFLD32SET(reg, val, first_bit, last_bit) \ + BSP_FLD32SET(reg, val, 31 - (last_bit), 31 - (first_bit)) + +#define BSP_BBIT64(bit) \ + BSP_BIT64(63 - (bit)) + +#define BSP_BMSK64(first_bit, last_bit) \ + BSP_MSK64(63 - (last_bit), 63 - (first_bit)) + +#define BSP_BFLD64(val, first_bit, last_bit) \ + BSP_FLD64(val, 63 - (last_bit), 63 - (first_bit)) + +#define BSP_BFLD64GET(reg, first_bit, last_bit) \ + BSP_FLD64GET(reg, 63 - (last_bit), 63 - (first_bit)) + +#define BSP_BFLD64SET(reg, val, first_bit, last_bit) \ + BSP_FLD64SET(reg, val, 63 - (last_bit), 63 - (first_bit)) + +#endif /* LIBCPU_SHARED_UTILITY_H */ diff --git a/bsps/include/bsp/vmeTsi148.h b/bsps/include/bsp/vmeTsi148.h new file mode 100644 index 0000000000..6183940a2d --- /dev/null +++ b/bsps/include/bsp/vmeTsi148.h @@ -0,0 +1,662 @@ +/** + * @file + * + * @ingroup shared_vmetsi148 + * + * @brief Driver for the Tundra Tsi148 pci-vme bridge + */ + +#ifndef VME_TSI148_DRIVER_H +#define VME_TSI148_DRIVER_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include +#include + + +/** + * @defgroup shared_vmetsi148 VMETSI148 Support + * + * @ingroup shared_vmeuniverse + * + * @brief VMETSI148 Support Package + */ + +/* NOTE: A64 currently not implemented */ + +/* These can be ored with the AM */ + +/* NOTE: unlike the universe, the tsi148 doesn't allow for disabling posted writes ! */ + +#define VME_MODE_PREFETCH_ENABLE VME_AM_IS_MEMORY +#define _LD_VME_MODE_PREFETCHSZ 24 +#define VME_MODE_PREFETCH_SIZE(x) (((x)&3)<<_LD_VME_MODE_PREFETCHSZ) + +/* These bits can be or'ed with the address-modifier when calling + * the 'XlateAddr' routine below to further qualify the + * search criteria. + */ +#define VME_MODE_MATCH_MASK (3<<30) +#define VME_MODE_EXACT_MATCH (2<<30) /* all bits must match */ +#define VME_MODE_AS_MATCH (1<<30) /* only A16/24/32 must match */ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile uint32_t BERegister; /* emphasize contents are big endian */ + +/* + * Scan the PCI busses for the Nth (N=='instance') Tsi148 VME bridge. + * + * RETURNS: + * contents of the IRQ_LINE PCI config register on Success, + * the base address of the Tsi148 register block is stored in + * *pbase. + * -1 on error (no Tsi found, error accessing PCI config space). + * + * SIDE_EFFECTS: PCI busmaster and response to memory addresses is enabled. + */ +int +vmeTsi148FindPciBase(int instance, BERegister **pbase); + +/* Initialize driver for Nth Tsi148 device found. + * This routine does not change any registers but + * just scans the PCI bus for Tsi bridges and initializes + * a driver slot. + * + * RETURNS: 0 on success, nonzero on error (or if no Tsi148 + * device is found). + */ +int +vmeTsi148InitInstance(unsigned instance); + +/* Initialize driver with 1st Tsi148 bridge found + * RETURNS: (see vmeTsi148InitInstance()). + */ +int +vmeTsi148Init(void); + +/* Setup the tsi148 chip, i.e. disable most of its + * mappings, reset interrupts etc. + */ +void +vmeTsi148ResetXX(BERegister *base); + +/* Setup the tsi148 connected to the first driver slot */ +void +vmeTsi148Reset(void); + +/* Pull VME SYSRESET line */ +void +vmeTsi148ResetBusXX(BERegister *base); + +/* Pull VME SYSRESET line of the 1st controller */ +void +vmeTsi148ResetBus(void); + +/* NOTE: all non-'XX' versions of driver entry points which + * have an associated 'XX' entry point operate on the + * device connected to the 1st driver slot. + */ + +/* configure a outbound port + * + * port: port number 0..7 + * + * address_space: vxWorks compliant addressing mode identifier + * (see vme.h). The most important are: + * 0x0d - A32, Sup, Data + * 0x3d - A24, Sup, Data + * 0x2d - A16, Sup, Data + * additionally, the value 0 is accepted; it will + * disable this port. + * vme_address: address on the vme_bus of this port. + * local_address: address on the pci_bus of this port. + * length: size of this port. + * + * NOTE: the addresses and length parameters must meet certain alignment + * requirements (see Tsi148 documentation). + * + * RETURNS: 0 on success, -1 on failure. Error messages printed to stderr. + */ + +int +vmeTsi148OutboundPortCfgXX( + BERegister *base, + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long pci_address, + unsigned long length); + +int +vmeTsi148OutboundPortCfg( + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long pci_address, + unsigned long length); + + +/* configure a VME inbound (PCI master) port */ +int +vmeTsi148InboundPortCfgXX( + BERegister *base, + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long pci_address, + unsigned long length); + +int +vmeTsi148InboundPortCfg( + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long pci_address, + unsigned long length); + +/* Translate an address through the bridge + * + * vmeTsi248XlateAddr(0,0,as,addr,&result) + * yields a VME a address that reflects + * a local memory location as seen from the VME bus through the + * tsi148 VME inbound port. + * + * Likewise does vmeTsi148XlateAddr(1,0,as,addr,&result) + * translate a VME bus addr (backwards, through the VME outbound + * port) to the PCI side of the bridge. + * + * A valid address space modifier must be specified. + * If VME_MODE_EXACT_MATCH is set, all the mode bits must + * match the requested mode. If VME_MODE_EXACT_MATCH is not + * set in the mode word, only the basic mode (address-space, + * sup/usr and pgm/data) is compared. + * + * The 'reverse' parameter may be used to find a reverse + * mapping, i.e. the pci address in a outbound window can be + * found if the respective vme address is known etc. + * + * RETURNS: translated address in *pbusAdrs / *plocalAdrs + * + * 0: success + * -1: address/modifier not found in any bridge port + * -2: invalid modifier + */ + +int +vmeTsi148XlateAddrXX( + BERegister *base, /* TSI 148 base address */ + int outbound, /* look in the outbound windows */ + int reverse, /* reverse mapping; for outbound ports: map local to VME */ + unsigned long as, /* address space */ + unsigned long aIn, /* address to look up */ + unsigned long *paOut/* where to put result */ + ); + +int +vmeTsi148XlateAddr( + int outbound, /* look in the outbound windows */ + int reverse, /* reverse mapping; for outbound: map local to VME */ + unsigned long as, /* address space */ + unsigned long aIn, /* address to look up */ + unsigned long *paOut/* where to put result */ + ); + + +/* avoid pulling stdio.h into this header. + * Applications that want a declaration of the + * following routines should + * #include + * #define _VME_TSI148_DECLARE_SHOW_ROUTINES + * #include + */ +#ifdef _VME_TSI148_DECLARE_SHOW_ROUTINES + +/* Print the current configuration of all outbound ports to + * f (stdout if NULL) + */ + +void +vmeTsi148OutboundPortsShowXX(BERegister *base, FILE *f); + +void +vmeTsi148OutboundPortsShow(FILE *f); + +/* Print the current configuration of all inbound ports to + * f (stdout if NULL) + */ + +void +vmeTsi148InboundPortsShowXX(BERegister *base, FILE *f); + +void +vmeTsi148InboundPortsShow(FILE *f); + +#endif + + +/* Disable all in- or out-bound ports, respectively */ +void +vmeTsi148DisableAllInboundPortsXX(BERegister *base); + +void +vmeTsi148DisableAllInboundPorts(void); + +void +vmeTsi148DisableAllOutboundPortsXX(BERegister *base); + +void +vmeTsi148DisableAllOutboundPorts(void); + +# define TSI_VEAT_VES (1<<31) +# define TSI_VEAT_VEOF (1<<30) +# define TSI_VEAT_VESCL (1<<29) +# define TSI_VEAT_2eOT (1<<21) +# define TSI_VEAT_2eST (1<<20) +# define TSI_VEAT_BERR (1<<19) +# define TSI_VEAT_LWORD (1<<18) +# define TSI_VEAT_WRITE (1<<17) +# define TSI_VEAT_IACK (1<<16) +# define TSI_VEAT_DS1 (1<<15) +# define TSI_VEAT_DS0 (1<<14) +# define TSI_VEAT_AM(v) (((v)>>8)&63) +# define TSI_VEAT_XAM(v) ((v)&255) + +/* Check and clear the error (AKA 'exception') register. + * Note that the Tsi148 does *not* propagate VME bus errors of any kind to + * the PCI status register and hence this routine (or registering an ISR + * to the TSI_VERR_INT_VEC) is the only means for detecting a bus error. + * + * RETURNS: + * 0 if no error has occurred since this routine was last called. + * Contents of the 'VEAT' register (bit definitions as above) + * otherwise. + * If a non-NULL 'paddr' argument is provided then the lower 32-bit + * of the error address is stored in *paddr (only if return value is + * non-zero). + * + * SIDE EFFECTS: this routine clears the error attribute register, allowing + * for future errors to be latched. + */ +unsigned long +vmeTsi148ClearVMEBusErrorsXX(BERegister *base, uint32_t *paddr); + +unsigned long +vmeTsi148ClearVMEBusErrors(uint32_t *paddr); + +/* Map internal register block to VME. + * + * This routine is intended for BSP implementors. The registers must be + * accessible from VME so that the interrupt handler can flush the + * bridge FIFO (see below). + * + * vme_base: VME address where the TSI registers (4k) can be mapped. + * This VME address must fall into a range covered by + * any pre-configured outbound window. + * address_space: The desired VME address space. + * (all of SUP/USR/PGM/DATA are always accepted). + * + * See NOTES [vmeTsi148InstallIrqMgrAlt()] below for further information. + * + * RETURNS: 0 on success, nonzero on error. It is not possible (and results + * in a non-zero return code) to change the CRG VME address after + * initializing the interrupt manager as it uses the CRG. + */ +int +vmeTsi148MapCRGXX(BERegister *base, uint32_t vme_base, uint32_t address_space); + +int +vmeTsi148MapCRG(uint32_t vme_base, uint32_t address_space); + + +/* VME Interrupt Handler functionality */ + +/* we dont use the current RTEMS/BSP interrupt API for the + * following reasons: + * + * - RTEMS/BSP API does not pass an argument to the ISR :-( :-( + * - no separate vector space for VME vectors. Some vectors would + * have to overlap with existing PCI/ISA vectors. + * - RTEMS/BSP API allocates a structure for every possible vector + * - the irq_on(), irq_off() functions add more bloat than helping. + * They are (currently) only used by the framework to disable + * interrupts at the device level before removing a handler + * and to enable interrupts after installing a handler. + * These operations may as well be done by the driver itself. + * + * Hence, we maintain our own (VME) handler table and hook our PCI + * handler into the standard RTEMS/BSP environment. Our handler then + * dispatches VME interrupts. + */ + +typedef void (*VmeTsi148ISR) (void *usrArg, unsigned long vector); + +/* install a handler for a VME vector + * RETURNS 0 on success, nonzero on failure. + */ +int +vmeTsi148InstallISR(unsigned long vector, VmeTsi148ISR handler, void *usrArg); + +/* remove a handler for a VME vector. The vector and usrArg parameters + * must match the respective parameters used when installing the handler. + * RETURNS 0 on success, nonzero on failure. + */ +int +vmeTsi148RemoveISR(unsigned long vector, VmeTsi148ISR handler, void *usrArg); + +/* query for the currently installed ISR and usr parameter at a given vector + * RETURNS: ISR or 0 (vector too big or no ISR installed) + */ +VmeTsi148ISR +vmeTsi148ISRGet(unsigned long vector, void **parg); + +/* utility routines to enable/disable a VME IRQ level + * + * To enable/disable the internal interrupt sources (special vectors above) + * pass a vector argument > 255. + * + * RETURNS 0 on success, nonzero on failure + */ +int +vmeTsi148IntEnable(unsigned int level); + +int +vmeTsi148IntDisable(unsigned int level); + +/* Check if an interrupt level or internal source is enabled: + * + * 'level': VME level 1..7 or internal special vector > 255 + * + * RETURNS: value > 0 if interrupt is currently enabled, + * zero if interrupt is currently disabled, + * -1 on error (invalid argument). + */ + +int +vmeTsi148IntIsEnabled(unsigned int level); + +/* Set IACK width (1,2, or 4 bytes) for a given interrupt level. + * + * 'width' arg may be 0,1,2 or 4. If zero, the currently active + * value is returned but not modified. + * + * RETURNS: old width or -1 if invalid argument. + */ + +int +vmeTsi148SetIackWidth(int level, int width); + +/* Change the routing of IRQ 'level' to 'pin'. + * If the BSP connects more than one of the four + * physical interrupt lines from the tsi148 to + * the board's PIC then you may change the physical + * line a given 'level' is using. By default, + * all 7 VME levels use the first wire (pin==0) and + * all internal sources use the (optional) second + * wire (pin==1) [The driver doesn't support more than + * four wires]. + * This feature is useful if you want to make use of + * different hardware priorities of the PIC. Let's + * say you want to give IRQ level 7 the highest priority. + * You could then give 'pin 0' a higher priority (at the + * PIC) and 'pin 1' a lower priority and issue. + * + * for ( i=1; i<7; i++ ) vmeTsi148IntRoute(i, 1); + * + * PARAMETERS: + * 'level' : VME interrupt level '1..7' or one of + * the internal sources. Pass the internal + * source's vector number (>=256). + * 'pin' : a value of 0 routes the requested IRQ to + * the first line registered with the manager, + * a value of 1 routes it to the second wire + * etc. + * + * RETURNS: 0 on success, nonzero on error (invalid arguments) + * + * NOTES: - DONT change the tsi148 'map' registers + * directly. The driver caches routing internally. + * - support for the extra wires (beyond wire #0) is + * board dependent. If the board only provides + * a single physical wire from the tsi148 to + * the PIC then the feature might not be available. + */ +int +vmeTsi148IntRoute(unsigned int level, unsigned int pin); + +/* Raise a VME Interrupt at 'level' and respond with 'vector' to a + * handler on the VME bus. (The handler could be a different board + * or the tsi148 itself. + * + * Note that you could install a interrupt handler at TSI_VME_SW_IACK_INT_VEC + * to be notified of an IACK cycle having completed. + * + * This routine is mainly FOR TESTING. + * + * NOTES: + * - the VICR register is modified. + * - NO MUTUAL EXCLUSION PROTECTION (reads VICR, modifies then writes back). + * If several users need access to VICR it is their responsibility to serialize access. + * + * Arguments: + * 'level': interrupt level, 1..7 + * 'vector': vector number (0..255) that the tsi148 puts on the bus in response to + * an IACK cycle. + * + * RETURNS: + * 0: Success + * -1: Invalid argument (level not 1..7, vector >= 256) + * -2: Interrupt 'level' already asserted (maybe nobody handles it). + * You can manually clear it be setting the IRQC bit in + * VICR. Make sure really nobody responds to avoid spurious + * interrupts (consult tsi148 docs). + */ + +int +vmeTsi148IntRaiseXX(BERegister *base, int level, unsigned vector); + +int +vmeTsi148IntRaise(int level, unsigned vector); + +/* Loopback test of the VME interrupt subsystem. + * - installs ISRs on 'vector' and on TSI_VME_SW_IACK_INT_VEC + * - asserts VME interrupt 'level' + * - waits for both interrupts: 'ordinary' VME interrupt of 'level' and + * IACK completion interrupt ('special' vector TSI_VME_SW_IACK_INT_VEC). + * + * NOTES: + * - make sure no other handler responds to 'level'. + * - make sure no ISR is installed on both vectors yet. + * - ISRs installed by this routine are removed after completion. + * - no concurrent access protection of all involved resources + * (levels, vectors and registers [see vmeTsi148IntRaise()]) + * is implemented. + * - this routine is intended for TESTING (when implementing new BSPs etc.). + * - one RTEMS message queue is temporarily used (created/deleted). + * + * RETURNS: + * 0: Success. + * -1: Invalid arguments. + * 1: Test failed (outstanding interrupts). + * rtems_status_code: Failed RTEMS directive. + */ + +int +vmeTsi148IntLoopbackTst(int level, unsigned vector); + +/* use these special vectors to connect a handler to the + * tsi148 specific interrupts (such as "DMA done", SW or + * error irqs etc.) + * NOTE: The wrapper clears all status LINT bits (except + * for regular VME irqs). Also note that it is the user's + * responsibility to enable the necessary interrupts in + * LINT_EN + * + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * DO NOT CHANGE THE ORDER OF THESE VECTORS - THE DRIVER + * DEPENDS ON IT + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * + * Deliberately, these vectors match the universe driver's + */ +/* 256 no VOWN interrupt */ +#define TSI_DMA_INT_VEC 257 +#define TSI_LERR_INT_VEC 258 +#define TSI_VERR_INT_VEC 259 +/* 260 is reserved */ +#define TSI_VME_SW_IACK_INT_VEC 261 +/* 262 no PCI SW IRQ */ +#define TSI_SYSFAIL_INT_VEC 263 +#define TSI_ACFAIL_INT_VEC 264 +#define TSI_MBOX0_INT_VEC 265 +#define TSI_MBOX1_INT_VEC 266 +#define TSI_MBOX2_INT_VEC 267 +#define TSI_MBOX3_INT_VEC 268 +#define TSI_LM0_INT_VEC 269 +#define TSI_LM1_INT_VEC 270 +#define TSI_LM2_INT_VEC 271 +#define TSI_LM3_INT_VEC 272 + +/* New vectors; only on TSI148 */ +#define TSI_VIES_INT_VEC 273 +#define TSI_DMA1_INT_VEC 274 + +#define TSI_NUM_INT_VECS 275 + +#ifdef __INSIDE_RTEMS_BSP__ + +#include + +/* the tsi148 interrupt handler is capable of routing all sorts of + * (VME) interrupts to 4 different lines (some of) which may be hooked up + * in a (board specific) way to a PIC. + * + * This driver initially supports at most two lines (i.e., if the user + * doesn't re-route anything). By default, it routes the + * 7 VME interrupts to the main line and optionally, it routes the 'special' + * interrupts generated by the tsi148 itself (DMA done, SW irq etc.) + * to a second line. If no second line is available, all IRQs are routed + * to the main line. + * + * The routing of interrupts to the two lines can be modified (using + * the vmeTsi148IntRoute() call - see above - i.e., to make use of + * different hardware priorities and/or more physically available lines. + * + * Because the driver has no way to figure out which lines are actually + * wired to the PIC, this information has to be provided when installing + * the manager. + * + * Hence the manager sets up routing VME interrupts to 1 or 2 tsi148 + * OUTPUTS. However, it must also be told to which PIC INPUTS they + * are wired. + * Optionally, the first PIC input line can be read from PCI config space + * but the second must be passed to this routine. Note that the info read + * from PCI config space is wrong for some boards! + * + * PARAMETERS: + * flags: VMETSI148_IRQ_MGR_FLAG_SHARED: + * use the BSP_install_rtems_shared_irq_handler() instead + * of BSP_install_rtems_irq_handler(). Use this if the PIC + * line is used by other devices, too. + * CAVEAT: shared interrupts need RTEMS workspace, i.e., the + * VME interrupt manager can only be installed + * *after workspace is initialized* if 'shared' is nonzero + * (i.e., *not* from bspstart()). + * + * tsi_pin_0: to which output pin (of the tsi148) should the 7 + * VME irq levels be routed. + * + * pic_pin_0: specifies to which PIC input the 'main' output is + * wired on your board. If passed a value < 0, the driver + * reads this information from PCI config space ("IRQ line"). + * ... : up to three additional tsi_pin/pic_pin pairs can be + * specified if your board provides more physical wires. + * In any case must the varargs list be terminated by '-1'. + * + * RETURNS: 0 on success, -1 on failure. + * + * NOTES: The Tsi148 always does 'posted' writes through a FIFO buffer. + * This effectively makes VME write operations asynchronous + * which can have undesired side-effects. + * In particular, consider the case of an ISR clearing the + * interrupt condition by writing to a CSR. The write operation + * doesn't really do anything but goes into the FIFO and + * the user ISR returns. At this point, the interrupt manager + * may find the IRQ still pending, trying another IACK + * cycle. Because it is probable that at this time the FIFO + * has been flushed and the CSR-write operation been effective, + * the IACK then times out. + * Note that this phenomenon becomes more obvious as CPUs + * become faster. + * + * To avoid this race condition and many VME drivers having + * to be re-written, a VME read (having the desired side-effect + * of flushing the write FIFO) must be issued between the + * user ISR returning and the interrupt manager checking for + * more pending interrupts. + * + * Therefore, the BSP needs to map the Tsi148 register + * block to VME so that a read over VME can be effectuated. + * (In addition to being mapped to VME, the mapped address + * range must be accessible through an outbound window.) + */ + +#define VMETSI148_IRQ_MGR_FLAG_SHARED 1 +int +vmeTsi148InstallIrqMgrAlt(int shared, int tsi_pin0, int pic_pin0, ...); + +int +vmeTsi148InstallIrqMgrVa(int shared, int tsi_pin0, int pic_pin0, va_list ap); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/vmeTsi148DMA.h b/bsps/include/bsp/vmeTsi148DMA.h new file mode 100644 index 0000000000..da7c99302b --- /dev/null +++ b/bsps/include/bsp/vmeTsi148DMA.h @@ -0,0 +1,102 @@ +/** + * @file + * + * @ingroup shared_vmetsi148dma + * + * @brief vmeTsi148DMA Support + */ + +#ifndef VME_TSI148_DMA_H +#define VME_TSI148_DMA_H + +#include + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2006, 2007 + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_vmetsi148dma DMA List + * + * @ingroup shared_vmeuniverse + * + * @brief DMA List access functions for use by bspVmeDmaList + */ + +extern struct VMEDmaListClassRec_ vmeTsi148DmaListClass; + +typedef struct VmeTsi148DmaListDescriptorRec_ *VmeTsi148DmaListDescriptor; + +int +vmeTsi148DmaSetupXX(BERegister *base, int channel, uint32_t mode, uint32_t xfer_mode, void *custom); + +int +vmeTsi148DmaSetup(int channel, uint32_t mode, uint32_t xfer_mode, void *custom); + +int +vmeTsi148DmaListStartXX(BERegister *base, int channel, VmeTsi148DmaListDescriptor d); + +int +vmeTsi148DmaListStart(int channel, VmeTsi148DmaListDescriptor d); + +int +vmeTsi148DmaStartXX(BERegister *base, int channel, uint32_t pci_addr, uint32_t vme_addr, uint32_t n_bytes); + +int +vmeTsi148DmaStart(int channel, uint32_t pci_addr, uint32_t vme_addr, uint32_t n_bytes); + +uint32_t +vmeTsi148DmaStatusXX(BERegister *base, int channel); + +uint32_t +vmeTsi148DmaStatus(int channel); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/vmeUniverse.h b/bsps/include/bsp/vmeUniverse.h new file mode 100644 index 0000000000..7cb9f8d2de --- /dev/null +++ b/bsps/include/bsp/vmeUniverse.h @@ -0,0 +1,1045 @@ +/** + * @file + * + * @ingroup shared_vmeuniverse + * + * @brief Driver for the Tundra Universe II pci-vme bridge + */ + +#ifndef VME_UNIVERSE_UTIL_H +#define VME_UNIVERSE_UTIL_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2000-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +/** + * @defgroup shared_vmeuniverse Register definitions + * + * @ingroup bsp_shared + * + * @brief all registers contents in PCI space are LITTLE ENDIAN + */ + +#ifdef __vxworks +#include +#else + +#include + +#endif + +/* These bits can be or'ed with the address-modifier when calling + * the 'XlateAddr' routine below to further qualify the + * search criteria. + */ +#define VME_MODE_MATCH_MASK (3<<30) +#define VME_MODE_EXACT_MATCH (2<<30) /* all bits must match */ +#define VME_MODE_AS_MATCH (1<<30) /* only A16/24/32 must match */ + + +typedef unsigned long LERegister; /* emphasize contents are little endian */ + +/****** NOTE: USE OF VmeUniverseDMAPacket IS DEPRECATED ********* + ****** USE API IN VMEDMA.h INSTEAD *********/ + +/* NOTE: DMA packet descriptors MUST be 32 byte aligned */ +typedef struct VmeUniverseDMAPacketRec_ { + LERegister dctl __attribute__((aligned(32))); + LERegister dtbc __attribute__((packed)); + LERegister dla __attribute__((packed)); + LERegister dummy1 __attribute__((packed)); + LERegister dva __attribute__((packed)); + LERegister dummy2 __attribute__((packed)); + LERegister dcpp __attribute__((packed)); + LERegister dummy3 __attribute__((packed)); +} VmeUniverseDMAPacketRec, *VmeUniverseDMAPacket; /* DEPRECATED */ + +/* PCI CSR register */ +#define UNIV_REGOFF_PCI_CSR 0x4 +# define UNIV_PCI_CSR_D_PE (1<<31) /* detected parity error; write 1 to clear */ +# define UNIV_PCI_CSR_S_SERR (1<<30) /* SERR (signalled error) asserted; write 1 to clear */ +# define UNIV_PCI_CSR_R_MA (1<<29) /* received master abort; write 1 to clear */ +# define UNIV_PCI_CSR_R_TA (1<<28) /* received target abort; write 1 to clear */ +# define UNIV_PCI_CSR_S_TA (1<<27) /* signalled target abort; write 1 to clear */ +# define UNIV_PCI_CSR_DEVSEL_MASK (3<<25) /* device select timing (RO) */ +# define UNIV_PCI_CSR_DP_D (1<<24) /* data parity error detected; write 1 to clear */ +# define UNIV_PCI_CSR_TFBBC (1<<23) /* target fast back to back capable (RO) */ +# define UNIV_PCI_CSR_MFBBC (1<<9) /* master fast back to back capable (RO) */ +# define UNIV_PCI_CSR_SERR_EN (1<<8) /* enable SERR driver */ +# define UNIV_PCI_CSR_WAIT (1<<7) /* wait cycle control (RO) */ +# define UNIV_PCI_CSR_PERESP (1<<6) /* parity error response enable */ +# define UNIV_PCI_CSR_VGAPS (1<<5) /* VGA palette snoop (RO) */ +# define UNIV_PCI_CSR_MWI_EN (1<<4) /* Memory write and invalidate enable (RO) */ +# define UNIV_PCI_CSR_SC (1<<3) /* special cycles (RO) */ +# define UNIV_PCI_CSR_BM (1<<2) /* master enable (MUST SET TO ENABLE VME SLAVES) */ +# define UNIV_PCI_CSR_MS (1<<1) /* target memory enable */ +# define UNIV_PCI_CSR_IOS (1<<0) /* target IO enable */ + +/* Special cycle (ADOH, RMW) control register */ +#define UNIV_REGOFF_SCYC_CTL 0x170 /* write 0 to disable */ +# define UNIV_SCYC_CTL_LAS_IO (1<<2) /* PCI address space (1: IO, 0: mem) */ +# define UNIV_SCYC_CTL_SCYC_RMW (1<<0) /* do a RMW cycle when reading PCI address */ +# define UNIV_SCYC_CTL_SCYC_ADOH (2<<0) /* do a ADOH cycle when reading/writing PCI address */ + +/* Special cycle address register */ +#define UNIV_REGOFF_SCYC_ADDR 0x174 /* PCI address (must be long word aligned) */ + +/* Special cycle Swap/Compare/Enable */ +#define UNIV_REGOFF_SCYC_EN 0x178 /* mask determining the bits involved in the compare and swap operations for VME RMW cycles */ + +/* Special cycle compare data register */ +#define UNIV_REGOFF_SCYC_CMP 0x17c /* data to compare with word returned from VME RMW read */ + +/* Special cycle swap data register */ +#define UNIV_REGOFF_SCYC_SWP 0x180 /* If enabled bits of CMP match, corresponding SWP bits are written back to VME (under control of EN) */ + +/* PCI miscellaneous register */ +#define UNIV_REGOFF_LMISC 0x184 +# define UNIV_LMISC_CRT_MASK (7<<28) /* Univ. I only, not used on II */ +# define UNIV_LMISC_CRT_INF (0<<28) /* Coupled Request Timeout */ +# define UNIV_LMISC_CRT_128_US (1<<28) /* Coupled Request Timeout */ +# define UNIV_LMISC_CRT_256_US (2<<28) /* Coupled Request Timeout */ +# define UNIV_LMISC_CRT_512_US (3<<28) /* Coupled Request Timeout */ +# define UNIV_LMISC_CRT_1024_US (4<<28) /* Coupled Request Timeout */ +# define UNIV_LMISC_CRT_2048_US (5<<28) /* Coupled Request Timeout */ +# define UNIV_LMISC_CRT_4096_US (6<<28) /* Coupled Request Timeout */ + +# define UNIV_LMISC_CWT_MASK (7<<24) /* coupled window timer */ +# define UNIV_LMISC_CWT_DISABLE 0 /* disabled (release VME after 1 coupled xaction) */ +# define UNIV_LMISC_CWT_16 (1<<24) /* 16 PCI clock cycles */ +# define UNIV_LMISC_CWT_32 (2<<24) /* 32 PCI clock cycles */ +# define UNIV_LMISC_CWT_64 (3<<24) /* 64 PCI clock cycles */ +# define UNIV_LMISC_CWT_128 (4<<24) /* 128 PCI clock cycles */ +# define UNIV_LMISC_CWT_256 (5<<24) /* 256 PCI clock cycles */ +# define UNIV_LMISC_CWT_512 (6<<24) /* 512 PCI clock cycles */ + +/* PCI Command Error Log Register */ +#define UNIV_REGOFF_L_CMDERR 0x18c +# define UNIV_L_CMDERR_CMDERR(reg) (((reg)>>28)&0xf) /* extract PCI cmd error log */ +# define UNIV_L_CMDERR_M_ERR (1<<27) /* multiple errors have occurred */ +# define UNIV_L_CMDERR_L_STAT (1<<23) /* PCI error log status valid (write 1 to clear and enable logging) */ + +/* PCI Address Error Log */ +#define UNIV_REGOFF_LAERR 0x190 /* PCI fault address (if L_CMDERR_L_STAT valid) */ +/* DMA Xfer Control Register */ +#define UNIV_REGOFF_DCTL 0x200 +# define UNIV_DCTL_L2V (1<<31) /* PCI->VME if set */ +# define UNIV_DCTL_VDW_MSK (3<<22) /* VME max. width mask 0x00c00000 */ +# define UNIV_DCTL_VDW_8 (0<<22) /* VME max. width 8 */ +# define UNIV_DCTL_VDW_16 (1<<22) /* VME max. width 16 */ +# define UNIV_DCTL_VDW_32 (2<<22) /* VME max. width 32 */ +# define UNIV_DCTL_VDW_64 (3<<22) /* VME max. width 64 */ +# define UNIV_DCTL_VAS_MSK (7<<16) /* VME AS mask 0x00070000 */ +# define UNIV_DCTL_VAS_A16 (0<<16) /* VME A16 */ +# define UNIV_DCTL_VAS_A24 (1<<16) /* VME A24 */ +# define UNIV_DCTL_VAS_A32 (2<<16) /* VME A32 */ +# define UNIV_DCTL_PGM_MSK (3<<14) /* VME PGM/DATA mask 0x0000c000 */ +# define UNIV_DCTL_PGM (1<<14) /* VME PGM(1)/DATA(0) */ +# define UNIV_DCTL_SUPER_MSK (3<<12) /* VME SUPER/USR mask 0x00003000 */ +# define UNIV_DCTL_SUPER (1<<12) /* VME SUPER(1)/USR(0) */ +# define UNIV_DCTL_NO_VINC (1<<9) /* VME no VME address increment [Universe IIa/b ONLY */ +# define UNIV_DCTL_VCT (1<<8) /* VME enable BLT */ +# define UNIV_DCTL_LD64EN (1<<7) /* PCI 64 enable */ + +/* DMA Xfer byte count register (is updated by DMA) */ +#define UNIV_REGOFF_DTBC 0x204 +/* DMA Xfer local (PCI) address (direction is set in DCTL) */ +#define UNIV_REGOFF_DLA 0x208 +/* DMA Xfer VME address (direction is set in DCTL) + * NOTE: (*UNIV_DVA) & ~7 == (*UNIV_DLA) & ~7 MUST HOLD + */ +#define UNIV_REGOFF_DVA 0x210 + +/* DMA Xfer VME command packet pointer + * NOTE: The address stored here MUST be 32-byte aligned + */ +#define UNIV_REGOFF_DCPP 0x218 +/* these bits are only used in linked lists */ +# define UNIV_DCPP_IMG_NULL (1<<0) /* last packet in list */ +# define UNIV_DCPP_IMG_PROCESSED (1<<1) /* packet processed */ + +/* DMA Xfer General Control/Status register */ +#define UNIV_REGOFF_DGCS 0x220 +# define UNIV_DGCS_GO (1<<31) /* start xfer */ +# define UNIV_DGCS_STOP_REQ (1<<30) /* stop xfer (immediate abort) */ +# define UNIV_DGCS_HALT_REQ (1<<29) /* halt xfer (abort after current packet) */ +# define UNIV_DGCS_CHAIN (1<<27) /* enable linked list mode */ +# define UNIV_DGCS_VON_MSK (7<<20) /* VON mask */ +# define UNIV_DGCS_VON_DONE (0<<20) /* VON counter disabled (do until done) */ +# define UNIV_DGCS_VON_256 (1<<20) /* VON yield bus after 256 bytes */ +# define UNIV_DGCS_VON_512 (2<<20) /* VON yield bus after 512 bytes */ +# define UNIV_DGCS_VON_1024 (3<<20) /* VON yield bus after 1024 bytes */ +# define UNIV_DGCS_VON_2048 (4<<20) /* VON yield bus after 2048 bytes */ +# define UNIV_DGCS_VON_4096 (5<<20) /* VON yield bus after 4096 bytes */ +# define UNIV_DGCS_VON_8192 (6<<20) /* VON yield bus after 8192 bytes */ +# define UNIV_DGCS_VON_16384 (7<<20) /* VON yield bus after 16384 bytes */ +# define UNIV_DGCS_VOFF_MSK (15<<16) /* VOFF mask */ +# define UNIV_DGCS_VOFF_0_US (0<<16) /* re-request VME master after 0 us */ +# define UNIV_DGCS_VOFF_2_US (8<<16) /* re-request VME master after 2 us */ +# define UNIV_DGCS_VOFF_4_US (9<<16) /* re-request VME master after 4 us */ +# define UNIV_DGCS_VOFF_8_US (10<<16)/* re-request VME master after 8 us */ +# define UNIV_DGCS_VOFF_16_US (1<<16) /* re-request VME master after 16 us */ +# define UNIV_DGCS_VOFF_32_US (2<<16) /* re-request VME master after 32 us */ +# define UNIV_DGCS_VOFF_64_US (3<<16) /* re-request VME master after 64 us */ +# define UNIV_DGCS_VOFF_128_US (4<<16) /* re-request VME master after 128 us */ +# define UNIV_DGCS_VOFF_256_US (5<<16) /* re-request VME master after 256 us */ +# define UNIV_DGCS_VOFF_512_US (6<<16) /* re-request VME master after 512 us */ +# define UNIV_DGCS_VOFF_1024_US (7<<16) /* re-request VME master after 1024 us */ +/* Status Bits (write 1 to clear) */ +# define UNIV_DGCS_ACT (1<<15) /* DMA active */ +# define UNIV_DGCS_STOP (1<<14) /* DMA stopped */ +# define UNIV_DGCS_HALT (1<<13) /* DMA halted */ +# define UNIV_DGCS_DONE (1<<11) /* DMA done (OK) */ +# define UNIV_DGCS_LERR (1<<10) /* PCI bus error */ +# define UNIV_DGCS_VERR (1<<9) /* VME bus error */ +# define UNIV_DGCS_P_ERR (1<<8) /* programming protocol error (e.g. PCI master disabled) */ +# define UNIV_DGCS_STATUS_CLEAR\ + (UNIV_DGCS_ACT|UNIV_DGCS_STOP|UNIV_DGCS_HALT|\ + UNIV_DGCS_DONE|UNIV_DGCS_LERR|UNIV_DGCS_VERR|UNIV_DGCS_P_ERR) +# define UNIV_DGCS_P_ERR (1<<8) /* programming protocol error (e.g. PCI master disabled) */ +/* Interrupt Mask Bits */ +# define UNIV_DGCS_INT_STOP (1<<6) /* interrupt when stopped */ +# define UNIV_DGCS_INT_HALT (1<<5) /* interrupt when halted */ +# define UNIV_DGCS_INT_DONE (1<<3) /* interrupt when done */ +# define UNIV_DGCS_INT_LERR (1<<2) /* interrupt on LERR */ +# define UNIV_DGCS_INT_VERR (1<<1) /* interrupt on VERR */ +# define UNIV_DGCS_INT_P_ERR (1<<0) /* interrupt on P_ERR */ +# define UNIV_DGCS_INT_MSK (0x0000006f) /* interrupt mask */ + +/* DMA Linked List Update Enable Register */ +#define UNIV_REGOFF_D_LLUE 0x224 +# define UNIV_D_LLUE_UPDATE (1<<31) + + +/* PCI (local) interrupt enable register */ +#define UNIV_REGOFF_LINT_EN 0x300 +# define UNIV_LINT_EN_LM3 (1<<23) /* location monitor 3 mask */ +# define UNIV_LINT_EN_LM2 (1<<22) /* location monitor 2 mask */ +# define UNIV_LINT_EN_LM1 (1<<21) /* location monitor 1 mask */ +# define UNIV_LINT_EN_LM0 (1<<20) /* location monitor 0 mask */ +# define UNIV_LINT_EN_MBOX3 (1<<19) /* mailbox 3 mask */ +# define UNIV_LINT_EN_MBOX2 (1<<18) /* mailbox 2 mask */ +# define UNIV_LINT_EN_MBOX1 (1<<17) /* mailbox 1 mask */ +# define UNIV_LINT_EN_MBOX0 (1<<16) /* mailbox 0 mask */ +# define UNIV_LINT_EN_ACFAIL (1<<15) /* ACFAIL irq mask */ +# define UNIV_LINT_EN_SYSFAIL (1<<14) /* SYSFAIL irq mask */ +# define UNIV_LINT_EN_SW_INT (1<<13) /* PCI (local) software irq */ +# define UNIV_LINT_EN_SW_IACK (1<<12) /* VME software IACK mask */ +# define UNIV_LINT_EN_VERR (1<<10) /* PCI VERR irq mask */ +# define UNIV_LINT_EN_LERR (1<<9) /* PCI LERR irq mask */ +# define UNIV_LINT_EN_DMA (1<<8) /* PCI DMA irq mask */ +# define UNIV_LINT_EN_VIRQ7 (1<<7) /* VIRQ7 mask (universe does IACK automatically) */ +# define UNIV_LINT_EN_VIRQ6 (1<<6) /* VIRQ6 mask */ +# define UNIV_LINT_EN_VIRQ5 (1<<5) /* VIRQ5 mask */ +# define UNIV_LINT_EN_VIRQ4 (1<<4) /* VIRQ4 mask */ +# define UNIV_LINT_EN_VIRQ3 (1<<3) /* VIRQ3 mask */ +# define UNIV_LINT_EN_VIRQ2 (1<<2) /* VIRQ2 mask */ +# define UNIV_LINT_EN_VIRQ1 (1<<1) /* VIRQ1 mask */ +# define UNIV_LINT_EN_VOWN (1<<0) /* VOWN mask */ + +/* PCI (local) interrupt status register */ +#define UNIV_REGOFF_LINT_STAT 0x304 +# define UNIV_LINT_STAT_LM3 (1<<23) /* location monitor 3 status */ +# define UNIV_LINT_STAT_LM2 (1<<22) /* location monitor 2 status */ +# define UNIV_LINT_STAT_LM1 (1<<21) /* location monitor 1 status */ +# define UNIV_LINT_STAT_LM0 (1<<20) /* location monitor 0 status */ +# define UNIV_LINT_STAT_MBOX3 (1<<19) /* mailbox 3 status */ +# define UNIV_LINT_STAT_MBOX2 (1<<18) /* mailbox 2 status */ +# define UNIV_LINT_STAT_MBOX1 (1<<17) /* mailbox 1 status */ +# define UNIV_LINT_STAT_MBOX0 (1<<16) /* mailbox 0 status */ +# define UNIV_LINT_STAT_ACFAIL (1<<15) /* ACFAIL irq status */ +# define UNIV_LINT_STAT_SYSFAIL (1<<14) /* SYSFAIL irq status */ +# define UNIV_LINT_STAT_SW_INT (1<<13) /* PCI (local) software irq */ +# define UNIV_LINT_STAT_SW_IACK (1<<12) /* VME software IACK status */ +# define UNIV_LINT_STAT_VERR (1<<10) /* PCI VERR irq status */ +# define UNIV_LINT_STAT_LERR (1<<9) /* PCI LERR irq status */ +# define UNIV_LINT_STAT_DMA (1<<8) /* PCI DMA irq status */ +# define UNIV_LINT_STAT_VIRQ7 (1<<7) /* VIRQ7 status */ +# define UNIV_LINT_STAT_VIRQ6 (1<<6) /* VIRQ6 status */ +# define UNIV_LINT_STAT_VIRQ5 (1<<5) /* VIRQ5 status */ +# define UNIV_LINT_STAT_VIRQ4 (1<<4) /* VIRQ4 status */ +# define UNIV_LINT_STAT_VIRQ3 (1<<3) /* VIRQ3 status */ +# define UNIV_LINT_STAT_VIRQ2 (1<<2) /* VIRQ2 status */ +# define UNIV_LINT_STAT_VIRQ1 (1<<1) /* VIRQ1 status */ +# define UNIV_LINT_STAT_VOWN (1<<0) /* VOWN status */ +# define UNIV_LINT_STAT_CLR (0xfff7ff)/* Clear all status bits */ + +/* PCI (local) interrupt map 0 register */ +#define UNIV_REGOFF_LINT_MAP0 0x308 /* mapping of VME IRQ sources to PCI irqs */ +# define UNIV_LINT_MAP0_VIRQ7(lint) (((lint)&0x7)<<(7*4)) +# define UNIV_LINT_MAP0_VIRQ6(lint) (((lint)&0x7)<<(6*4)) +# define UNIV_LINT_MAP0_VIRQ5(lint) (((lint)&0x7)<<(5*4)) +# define UNIV_LINT_MAP0_VIRQ4(lint) (((lint)&0x7)<<(4*4)) +# define UNIV_LINT_MAP0_VIRQ3(lint) (((lint)&0x7)<<(3*4)) +# define UNIV_LINT_MAP0_VIRQ2(lint) (((lint)&0x7)<<(2*4)) +# define UNIV_LINT_MAP0_VIRQ1(lint) (((lint)&0x7)<<(1*4)) +# define UNIV_LINT_MAP0_VOWN(lint) (((lint)&0x7)<<(0*4)) + +#define UNIV_REGOFF_LINT_MAP1 0x30c /* mapping of internal / VME IRQ sources to PCI irqs */ +# define UNIV_LINT_MAP1_ACFAIL(lint) (((lint)&0x7)<<(7*4)) +# define UNIV_LINT_MAP1_SYSFAIL(lint) (((lint)&0x7)<<(6*4)) +# define UNIV_LINT_MAP1_SW_INT(lint) (((lint)&0x7)<<(5*4)) +# define UNIV_LINT_MAP1_SW_IACK(lint) (((lint)&0x7)<<(4*4)) +# define UNIV_LINT_MAP1_VERR(lint) (((lint)&0x7)<<(2*4)) +# define UNIV_LINT_MAP1_LERR(lint) (((lint)&0x7)<<(1*4)) +# define UNIV_LINT_MAP1_DMA(lint) (((lint)&0x7)<<(0*4)) + +/* enabling of generation of VME bus IRQs, TODO */ +#define UNIV_REGOFF_VINT_EN 0x310 +# define UNIV_VINT_EN_DISABLE_ALL 0 +# define UNIV_VINT_EN_SWINT (1<<12) +# define UNIV_VINT_EN_SWINT_LVL(l) (1<<(((l)&7)+24)) /* universe II only */ + + +/* status of generation of VME bus IRQs */ +#define UNIV_REGOFF_VINT_STAT 0x314 +# define UNIV_VINT_STAT_LINT(lint) (1<<((lint)&7)) +# define UNIV_VINT_STAT_LINT_MASK (0xff) +# define UNIV_VINT_STAT_CLR (0xfe0f17ff) +# define UNIV_VINT_STAT_SWINT(l) (1<<(((l)&7)+24)) + +#define UNIV_REGOFF_VINT_MAP0 0x318 /* VME destination of PCI IRQ source, TODO */ + +#define UNIV_REGOFF_VINT_MAP1 0x31c /* VME destination of PCI IRQ source, TODO */ +# define UNIV_VINT_MAP1_SWINT(level) (((level)&0x7)<<16) + +/* NOTE: The universe seems to always set LSB (which has a special purpose in + * the STATID register: enable raising a SW_INT on IACK) on the + * vector it puts out on the bus... + */ +#define UNIV_REGOFF_VINT_STATID 0x320 /* our status/id response to IACK, TODO */ +# define UNIV_VINT_STATID(id) ((id)<<24) + +#define UNIV_REGOFF_VIRQ1_STATID 0x324 /* status/id of VME IRQ level 1 */ +#define UNIV_REGOFF_VIRQ2_STATID 0x328 /* status/id of VME IRQ level 2 */ +#define UNIV_REGOFF_VIRQ3_STATID 0x32c /* status/id of VME IRQ level 3 */ +#define UNIV_REGOFF_VIRQ4_STATID 0x330 /* status/id of VME IRQ level 4 */ +#define UNIV_REGOFF_VIRQ5_STATID 0x334 /* status/id of VME IRQ level 5 */ +#define UNIV_REGOFF_VIRQ6_STATID 0x338 /* status/id of VME IRQ level 6 */ +#define UNIV_REGOFF_VIRQ7_STATID 0x33c /* status/id of VME IRQ level 7 */ +# define UNIV_VIRQ_ERR (1<<8) /* set if universe encountered a bus error when doing IACK */ +# define UNIV_VIRQ_STATID_MASK (0xff) + +#define UNIV_REGOFF_LINT_MAP2 0x340 /* mapping of internal sources to PCI irqs */ +# define UNIV_LINT_MAP2_LM3(lint) (((lint)&0x7)<<7*4) /* location monitor 3 */ +# define UNIV_LINT_MAP2_LM2(lint) (((lint)&0x7)<<6*4) /* location monitor 2 */ +# define UNIV_LINT_MAP2_LM1(lint) (((lint)&0x7)<<5*4) /* location monitor 1 */ +# define UNIV_LINT_MAP2_LM0(lint) (((lint)&0x7)<<4*4) /* location monitor 0 */ +# define UNIV_LINT_MAP2_MBOX3(lint) (((lint)&0x7)<<3*4) /* mailbox 3 */ +# define UNIV_LINT_MAP2_MBOX2(lint) (((lint)&0x7)<<2*4) /* mailbox 2 */ +# define UNIV_LINT_MAP2_MBOX1(lint) (((lint)&0x7)<<1*4) /* mailbox 1 */ +# define UNIV_LINT_MAP2_MBOX0(lint) (((lint)&0x7)<<0*4) /* mailbox 0 */ + +#define UNIV_REGOFF_VINT_MAP2 0x344 /* mapping of internal sources to VME irqs */ +# define UNIV_VINT_MAP2_MBOX3(vint) (((vint)&0x7)<<3*4) /* mailbox 3 */ +# define UNIV_VINT_MAP2_MBOX2(vint) (((vint)&0x7)<<2*4) /* mailbox 2 */ +# define UNIV_VINT_MAP2_MBOX1(vint) (((vint)&0x7)<<1*4) /* mailbox 1 */ +# define UNIV_VINT_MAP2_MBOX0(vint) (((vint)&0x7)<<0*4) /* mailbox 0 */ + +#define UNIV_REGOFF_MBOX0 0x348 /* mailbox 0 */ +#define UNIV_REGOFF_MBOX1 0x34c /* mailbox 1 */ +#define UNIV_REGOFF_MBOX2 0x350 /* mailbox 2 */ +#define UNIV_REGOFF_MBOX3 0x354 /* mailbox 3 */ + +#define UNIV_REGOFF_SEMA0 0x358 /* semaphore 0 */ +#define UNIV_REGOFF_SEMA1 0x35c /* semaphore 0 */ +/* TODO define semaphore register bits */ + +#define UNIV_REGOFF_MAST_CTL 0x400 /* master control register */ +# define UNIV_MAST_CTL_MAXRTRY(val) (((val)&0xf)<<7*4) /* max # of pci master retries */ +# define UNIV_MAST_CTL_PWON(val) (((val)&0xf)<<6*4) /* posted write xfer count */ +# define UNIV_MAST_CTL_VRL(val) (((val)&0x3)<<22) /* VME bus request level */ +# define UNIV_MAST_CTL_VRM (1<<21) /* bus request mode (demand = 0, fair = 1) */ +# define UNIV_MAST_CTL_VREL (1<<20) /* bus release mode (when done = 0, on request = 1) */ +# define UNIV_MAST_CTL_VOWN (1<<19) /* bus ownership (release = 0, acquire/hold = 1) */ +# define UNIV_MAST_CTL_VOWN_ACK (1<<18) /* bus ownership (not owned = 0, acquired/held = 1) */ +# define UNIV_MAST_CTL_PABS(val) (((val)&0x3)<<3*4) /* PCI aligned burst size (32,64,128 byte / 0x3 is reserved) */ +# define UNIV_MAST_CTL_BUS_NO(val) (((val)&0xff)<<0*4) /* PCI bus number */ + +#define UNIV_REGOFF_MISC_CTL 0x404 /* misc control register */ +# define UNIV_MISC_CTL_VBTO(val) (((val)&0x7)<<7*4) /* VME bus timeout (0=disable, 16*2^(val-1) us) */ +# define UNIV_MISC_CTL_VARB (1<<26) /* VME bus arbitration mode (0=round robin, 1= priority) */ +# define UNIV_MISC_CTL_VARBTO(val) (((val)&0x3)<<6*4) /* arbitration time out: disable, 16us, 256us, reserved */ +# define UNIV_MISC_CTL_SW_LRST (1<<23) /* software PCI reset */ +# define UNIV_MISC_CTL_SW_SYSRST (1<<22) /* software VME reset */ +# define UNIV_MISC_CTL_BI (1<<20) /* BI mode */ +# define UNIV_MISC_CTL_ENGBI (1<<19) /* enable global BI mode initiator */ +# define UNIV_MISC_CTL_SYSCON (1<<17) /* (R/W) 1:universe is system controller */ +# define UNIV_MISC_CTL_V64AUTO (1<<16) /* (R/W) 1:initiate VME64 auto id slave participation */ + +/* U2SPEC described in VGM manual */ +/* NOTE: the Joerger vtr10012_8 needs the timing to be tweaked!!!! READt27 must be _no_delay_ + */ +#define UNIV_REGOFF_U2SPEC 0x4fc +# define UNIV_U2SPEC_DTKFLTR (1<<12) /* DTAck filter: 0: slow, better filter; 1: fast, poorer filter */ +# define UNIV_U2SPEC_MASt11 (1<<10) /* Master parameter t11 (DS hi time during BLT and MBLTs) */ +# define UNIV_U2SPEC_READt27_DEFAULT (0<<8) /* VME master parameter t27: (latch data after DTAck + 25ns) */ +# define UNIV_U2SPEC_READt27_FAST (1<<8) /* VME master parameter t27: (latch data faster than 25ns) */ +# define UNIV_U2SPEC_READt27_NODELAY (2<<8) /* VME master parameter t27: (latch data without any delay) */ +# define UNIV_U2SPEC_POSt28_FAST (1<<2) /* VME slave parameter t28: (faster time of DS to DTAck for posted write) */ +# define UNIV_U2SPEC_PREt28_FAST (1<<0) /* VME slave parameter t28: (faster time of DS to DTAck for prefetch read) */ + +/* Location Monitor control register */ +#define UNIV_REGOFF_LM_CTL 0xf64 +# define UNIV_LM_CTL_EN (1<<31) /* image enable */ +# define UNIV_LM_CTL_PGM (1<<23) /* program AM */ +# define UNIV_LM_CTL_DATA (1<<22) /* data AM */ +# define UNIV_LM_CTL_SUPER (1<<21) /* supervisor AM */ +# define UNIV_LM_CTL_USER (1<<20) /* user AM */ +# define UNIV_LM_CTL_VAS_A16 (0<<16) /* A16 */ +# define UNIV_LM_CTL_VAS_A24 (1<<16) /* A16 */ +# define UNIV_LM_CTL_VAS_A32 (2<<16) /* A16 */ + +/* Location Monitor base address */ +#define UNIV_REGOFF_LM_BS 0xf68 + +/* VMEbus register access image control register */ +#define UNIV_REGOFF_VRAI_CTL 0xf70 +# define UNIV_VRAI_CTL_EN (1<<31) /* image enable */ +# define UNIV_VRAI_CTL_PGM (1<<23) /* program AM */ +# define UNIV_VRAI_CTL_DATA (1<<22) /* data AM */ +# define UNIV_VRAI_CTL_SUPER (1<<21) /* supervisor AM */ +# define UNIV_VRAI_CTL_USER (1<<20) /* user AM */ +# define UNIV_VRAI_CTL_VAS_A16 (0<<16) /* A16 */ +# define UNIV_VRAI_CTL_VAS_A24 (1<<16) /* A14 */ +# define UNIV_VRAI_CTL_VAS_A32 (2<<16) /* A32 */ +# define UNIV_VRAI_CTL_VAS_MSK (3<<16) + +/* VMEbus register acces image base address register */ +#define UNIV_REGOFF_VRAI_BS 0xf74 + +/* VMEbus CSR control register */ +#define UNIV_REGOFF_VCSR_CTL 0xf80 +# define UNIV_VCSR_CTL_EN (1<<31) /* image enable */ +# define UNIV_VCSR_CTL_LAS_PCI_MEM (0<<0) /* pci mem space */ +# define UNIV_VCSR_CTL_LAS_PCI_IO (1<<0) /* pci IO space */ +# define UNIV_VCSR_CTL_LAS_PCI_CFG (2<<0) /* pci config space */ + +/* VMEbus CSR translation offset */ +#define UNIV_REGOFF_VCSR_TO 0xf84 + +/* VMEbus AM code error log */ +#define UNIV_REGOFF_V_AMERR 0xf88 +# define UNIV_V_AMERR_AMERR(reg) (((reg)>>26)&0x3f) /* extract error log code */ +# define UNIV_V_AMERR_IACK (1<<25) /* VMEbus IACK signal */ +# define UNIV_V_AMERR_M_ERR (1<<24) /* multiple errors occurred */ +# define UNIV_V_AMERR_V_STAT (1<<23) /* log status valid (write 1 to clear) */ + +/* VMEbus address error log */ +#define UNIV_REGOFF_VAERR 0xf8c /* address of fault address (if MERR_V_STAT valid) */ + +/* VMEbus CSR bit clear register */ +#define UNIV_REGOFF_VCSR_CLR 0xff4 +# define UNIV_VCSR_CLR_RESET (1<<31) /* read/negate LRST (can only be written from VME bus */ +# define UNIV_VCSR_CLR_SYSFAIL (1<<30) /* read/negate SYSFAIL */ +# define UNIV_VCSR_CLR_FAIL (1<<29) /* read: board has failed */ + +/* VMEbus CSR bit set register */ +#define UNIV_REGOFF_VCSR_SET (0xff8) +# define UNIV_VCSR_SET_RESET (1<<31) /* read/assert LRST (can only be written from VME bus */ +# define UNIV_VCSR_SET_SYSFAIL (1<<30) /* read/assert SYSFAIL */ +# define UNIV_VCSR_SET_FAIL (1<<29) /* read: board has failed */ + +/* VMEbus CSR base address register */ +#define UNIV_REGOFF_VCSR_BS 0xffc +#define UNIV_VCSR_BS_MASK (0xf8000000) + +/* offset of universe registers in VME-CSR slot */ +#define UNIV_CSR_OFFSET 0x7f000 + +#ifdef __cplusplus +extern "C" { +#endif + +/* base address and IRQ line of 1st universe bridge + * NOTE: vmeUniverseInit() must be called before + * these may be used. + */ +extern volatile LERegister *vmeUniverse0BaseAddr; +extern int vmeUniverse0PciIrqLine; + + +/* Initialize the driver */ +int +vmeUniverseInit(void); + +/* setup the universe chip, i.e. disable most of its + * mappings, reset interrupts etc. + */ +void +vmeUniverseReset(void); + +/* avoid pulling stdio.h into this header. + * Applications that want a declaration of the + * following routines should + * #include + * #define _VME_UNIVERSE_DECLARE_SHOW_ROUTINES + * #include + */ +/* print the current configuration of all master ports to + * f (stderr if NULL) + */ +void +vmeUniverseMasterPortsShow(FILE *f); + +/* print the current configuration of all slave ports to + * f (stderr if NULL) + */ +void +vmeUniverseSlavePortsShow(FILE *f); + +/* disable all master or slave ports, respectively */ +void +vmeUniverseDisableAllMasters(void); + +void +vmeUniverseDisableAllSlaves(void); + +/* configure a master port + * + * port: port number 0..3 (0..7 for a UniverseII) + * + * address_space: vxWorks compliant addressing mode identifier + * (see vme.h). The most important are: + * 0x0d - A32, Sup, Data + * 0x3d - A24, Sup, Data + * 0x2d - A16, Sup, Data + * additionally, the value 0 is accepted; it will + * disable this port. + * vme_address: address on the vme_bus of this port. + * local_address: address on the pci_bus of this port. + * length: size of this port. + * + * NOTE: the addresses and length parameters must be aligned on a + * 2^16 byte (0x10000) boundary, except for port 4 (only available + * on a UniverseII), where the alignment can be 4k (4096). + * + * RETURNS: 0 on success, -1 on failure. Error messages printed to stderr. + */ + +int +vmeUniverseMasterPortCfg( + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long local_address, + unsigned long length); + +/* translate an address through the bridge + * + * vmeUniverseXlateAddr(0,0,as,addr,&result) + * yields a VME a address that reflects + * a local memory location as seen from the VME bus through the universe + * VME slave. + * + * likewise does vmeUniverseXlateAddr(1,0,as,addr,&result) + * translate a VME bus addr (through the VME master) to the + * PCI side of the bridge. + * + * a valid address space modifier must be specified. + * + * The 'reverse' parameter may be used to find a reverse + * mapping, i.e. the pci address in a master window can be + * found if the respective vme address is known etc. + * + * RETURNS: translated address in *pbusAdrs / *plocalAdrs + * + * 0: success + * -1: address/modifier not found in any bridge port + * -2: invalid modifier + */ +int +vmeUniverseXlateAddr( + int master, /* look in the master windows */ + int reverse, /* reverse mapping; for masters: map local to VME */ + unsigned long as, /* address space */ + unsigned long addr, /* address to look up */ + unsigned long *paOut/* where to put result */ + ); + +/* configure a VME slave (PCI master) port */ +int +vmeUniverseSlavePortCfg( + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long local_address, + unsigned long length); + +/****** NOTE: USE OF vmeUniverseStartDMA IS DEPRECATED ********* + ****** USE API IN VMEDMA.h/vmeUniverseDMA.h INSTEAD *********/ + +/* start a (direct, not linked) DMA transfer + * + * NOTE: DCTL and DGCS must be set up + * prior to calling this routine + */ +int +vmeUniverseStartDMA( + unsigned long local_addr, + unsigned long vme_addr, + unsigned long count); /* DEPRECATED */ + +int +vmeUniverseStartDMAXX( + volatile LERegister *ubase, + unsigned long local_addr, + unsigned long vme_addr, + unsigned long count); /* DEPRECATED */ + + +/* read a register in PCI memory space + * (offset being one of the declared constants) + */ +unsigned long +vmeUniverseReadReg(unsigned long offset); + +/* write a register in PCI memory space */ +void +vmeUniverseWriteReg(unsigned long value, unsigned long offset); + +/* convert an array of unsigned long values to LE (as needed + * when the universe reads e.g. DMA descriptors from PCI) + */ +void +vmeUniverseCvtToLE(unsigned long *ptr, unsigned long num); + +/* reset the VME bus */ +void +vmeUniverseResetBus(void); + +/* The ...XX routines take the universe base address as an additional + * argument - this allows for programming secondary devices. + */ + +unsigned long +vmeUniverseReadRegXX(volatile LERegister *ubase, unsigned long offset); + +void +vmeUniverseWriteRegXX(volatile LERegister *ubase, unsigned long value, unsigned long offset); + +int +vmeUniverseXlateAddrXX( + volatile LERegister *ubase, + int master, + int reverse, + unsigned long as, + unsigned long addr, + unsigned long *paOut + ); + +int +vmeUniverseMasterPortCfgXX( + volatile LERegister *ubase, + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long local_address, + unsigned long length); + +int +vmeUniverseSlavePortCfgXX( + volatile LERegister *ubase, + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long local_address, + unsigned long length); + +void +vmeUniverseDisableAllMastersXX(volatile LERegister *ubase); + +void +vmeUniverseDisableAllSlavesXX(volatile LERegister *ubase); + +/* print the current configuration of all master ports to + * f (stderr if NULL) + */ +void +vmeUniverseMasterPortsShowXX( + volatile LERegister *ubase,FILE *f); + +/* print the current configuration of all slave ports to + * f (stderr if NULL) + */ +void +vmeUniverseSlavePortsShowXX( + volatile LERegister *ubase,FILE *f); + +/* Raise a VME Interrupt at 'level' and respond with 'vector' to a + * handler on the VME bus. (The handler could be a different board + * or the universe itself - [only works with universe II]). + * + * Note that you could install a interrupt handler at UNIV_VME_SW_IACK_INT_VEC + * to be notified of an IACK cycle having completed. + * + * This routine is mainly FOR TESTING. + * + * NOTES: + * - several registers are modified: the vector is written to VINT_STATID + * and (universe 1 chip only) the level is written to the SW_INT bits + * int VINT_MAP1 + * - NO MUTUAL EXCLUSION PROTECTION (reads VINT_EN, modifies then writes back). + * If several users need access to VINT_EN and/or VINT_STATID (and VINT_MAP1 + * on the universe 1) it is their responsibility to serialize access. + * + * Arguments: + * 'level': interrupt level, 1..7 + * 'vector': vector number (0..254) that the universe puts on the bus in response to + * an IACK cycle. NOTE: the vector number *must be even* (hardware restriction + * of the universe -- it always clears the LSB when the interrupter is + * a software interrupt). + * + * RETURNS: + * 0: Success + * -1: Invalid argument (level not 1..7, vector odd or >= 256) + * -2: Interrupt 'level' already asserted (maybe nobody handles it). + * You can manually clear it be writing the respective bit in + * VINT_STAT. Make sure really nobody responds to avoid spurious + * interrupts (consult universe docs). + */ + +int +vmeUniverseIntRaiseXX(volatile LERegister *base, int level, unsigned vector); + +int +vmeUniverseIntRaise(int level, unsigned vector); + +/* Map internal register block to VME. + * + * This routine is intended for BSP implementors. The registers can be + * made accessible from VME so that the interrupt handler can flush the + * bridge FIFO (see below). The preferred method is by accessing VME CSR, + * though, if these are mapped [and the BSP provides an outbound window]. + * On the universe we can also disable posted writes in the 'ordinary' + * outbound windows. + * + * vme_base: VME address where the universe registers (4k) can be mapped. + * This VME address must fall into a range covered by + * any pre-configured outbound window. + * address_space: The desired VME address space. + * (all of SUP/USR/PGM/DATA are always accepted). + * + * See NOTES [vmeUniverseInstallIrqMgrAlt()] below for further information. + * + * RETURNS: 0 on success, nonzero on error. It is not possible (and results + * in a non-zero return code) to change the CRG VME address after + * initializing the interrupt manager as it uses the CRG. + */ +int +vmeUniverseMapCRGXX(volatile LERegister *base, unsigned long vme_base, unsigned long address_space); + +int +vmeUniverseMapCRG(unsigned long vme_base, unsigned long address_space); + + +#ifdef __rtems__ + +/* VME Interrupt Handler functionality */ + +/* we dont use the current RTEMS/BSP interrupt API for the + * following reasons: + * + * - RTEMS/BSP API does not pass an argument to the ISR :-( :-( + * - no separate vector space for VME vectors. Some vectors would + * have to overlap with existing PCI/ISA vectors. + * - RTEMS/BSP API allocates a structure for every possible vector + * - the irq_on(), irq_off() functions add more bloat than helping. + * They are (currently) only used by the framework to disable + * interrupts at the device level before removing a handler + * and to enable interrupts after installing a handler. + * These operations may as well be done by the driver itself. + * + * Hence, we maintain our own (VME) handler table and hook our PCI + * handler into the standard RTEMS/BSP environment. Our handler then + * dispatches VME interrupts. + */ + +typedef void (*VmeUniverseISR) (void *usrArg, unsigned long vector); + +/* use these special vectors to connect a handler to the + * universe specific interrupts (such as "DMA done", + * VOWN, error irqs etc.) + * NOTE: The wrapper clears all status LINT bits (except + * for regular VME irqs). Also note that it is the user's + * responsibility to enable the necessary interrupts in + * LINT_EN + * + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * DO NOT CHANGE THE ORDER OF THESE VECTORS - THE DRIVER + * DEPENDS ON IT + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * + */ +#define UNIV_VOWN_INT_VEC 256 +#define UNIV_DMA_INT_VEC 257 +#define UNIV_LERR_INT_VEC 258 +#define UNIV_VERR_INT_VEC 259 +/* 260 is reserved */ +#define UNIV_VME_SW_IACK_INT_VEC 261 +#define UNIV_PCI_SW_INT_VEC 262 +#define UNIV_SYSFAIL_INT_VEC 263 +#define UNIV_ACFAIL_INT_VEC 264 +#define UNIV_MBOX0_INT_VEC 265 +#define UNIV_MBOX1_INT_VEC 266 +#define UNIV_MBOX2_INT_VEC 267 +#define UNIV_MBOX3_INT_VEC 268 +#define UNIV_LM0_INT_VEC 269 +#define UNIV_LM1_INT_VEC 270 +#define UNIV_LM2_INT_VEC 271 +#define UNIV_LM3_INT_VEC 272 + +#define UNIV_NUM_INT_VECS 273 + + +/* install a handler for a VME vector + * RETURNS 0 on success, nonzero on failure. + */ +int +vmeUniverseInstallISR(unsigned long vector, VmeUniverseISR handler, void *usrArg); + +/* remove a handler for a VME vector. The vector and usrArg parameters + * must match the respective parameters used when installing the handler. + * RETURNS 0 on success, nonzero on failure. + */ +int +vmeUniverseRemoveISR(unsigned long vector, VmeUniverseISR handler, void *usrArg); + +/* query for the currently installed ISR and usr parameter at a given vector + * RETURNS: ISR or 0 (vector too big or no ISR installed) + */ +VmeUniverseISR +vmeUniverseISRGet(unsigned long vector, void **parg); + +/* utility routines to enable/disable a VME IRQ level. + * + * To enable/disable the internal interrupt sources (special vectors above) + * pass a vector argument > 255. + * + * RETURNS 0 on success, nonzero on failure + */ +int +vmeUniverseIntEnable(unsigned int level); +int +vmeUniverseIntDisable(unsigned int level); + +/* Check if an interrupt level or internal source is enabled: + * + * 'level': VME level 1..7 or internal special vector > 255 + * + * RETURNS: value > 0 if interrupt is currently enabled, + * zero if interrupt is currently disabled, + * -1 on error (invalid argument). + */ +int +vmeUniverseIntIsEnabled(unsigned int level); + + +/* Change the routing of IRQ 'level' to 'pin'. + * If the BSP connects more than one of the eight + * physical interrupt lines from the universe to + * the board's PIC then you may change the physical + * line a given 'level' is using. By default, + * all 7 VME levels use the first wire (pin==0) and + * all internal sources use the (optional) second + * wire (pin==1). + * This feature is useful if you want to make use of + * different hardware priorities of the PIC. Let's + * say you want to give IRQ level 7 the highest priority. + * You could then give 'pin 0' a higher priority (at the + * PIC) and 'pin 1' a lower priority and issue. + * + * for ( i=1; i<7; i++ ) vmeUniverseIntRoute(i, 1); + * + * PARAMETERS: + * 'level' : VME interrupt level '1..7' or one of + * the internal sources. Pass the internal + * source's vector number (>=256). + * 'pin' : a value of 0 routes the requested IRQ to + * the first line registered with the manager + * (vmeIrqUnivOut parameter), a value of 1 + * routes it to the alternate wire + * (specialIrqUnivOut) + * RETURNS: 0 on success, nonzero on error (invalid arguments) + * + * NOTES: - DONT change the universe 'map' registers + * directly. The driver caches routing internally. + * - support for the 'specialIrqUnivOut' wire is + * board dependent. If the board only provides + * a single physical wire from the universe to + * the PIC then the feature might not be available. + */ +int +vmeUniverseIntRoute(unsigned int level, unsigned int pin); + +/* Loopback test of the VME interrupt subsystem. + * - installs ISRs on 'vector' and on UNIV_VME_SW_IACK_INT_VEC + * - asserts VME interrupt 'level' + * - waits for both interrupts: 'ordinary' VME interrupt of 'level' and + * IACK completion interrupt ('special' vector UNIV_VME_SW_IACK_INT_VEC). + * + * NOTES: + * - make sure no other handler responds to 'level'. + * - make sure no ISR is installed on both vectors yet. + * - ISRs installed by this routine are removed after completion. + * - no concurrent access protection of all involved resources + * (levels, vectors and registers [see vmeUniverseIntRaise()]) + * is implemented. + * - this routine is intended for TESTING (when implementing new BSPs etc.). + * - one RTEMS message queue is temporarily used (created/deleted). + * - the universe 1 always yields a zero vector (VIRQx_STATID) in response + * to a self-generated VME interrupt. As a workaround, the routine + * only accepts a zero vector when running on a universe 1. + * + * RETURNS: + * 0: Success. + * -1: Invalid arguments. + * 1: Test failed (outstanding interrupts). + * rtems_status_code: Failed RTEMS directive. + */ +int +vmeUniverseIntLoopbackTst(int level, unsigned vector); + + +/* the universe interrupt handler is capable of routing all sorts of + * (VME) interrupts to 8 different lines (some of) which may be hooked up + * in a (board specific) way to a PIC. + * + * This driver only supports at most two lines. By default, it routes the + * 7 VME interrupts to the main line and optionally, it routes the 'special' + * interrupts generated by the universe itself (DMA done, VOWN etc.) + * to a second line. If no second line is available, all IRQs are routed + * to the main line. + * + * The routing of interrupts to the two lines can be modified (using + * the vmeUniverseIntRoute() call - see above - i.e., to make use of + * different hardware priorities of the two pins. + * + * Because the driver has no way to figure out which lines are actually + * wired to the PIC, this information has to be provided when installing + * the manager. + * + * Hence the manager sets up routing VME interrupts to 1 or 2 universe + * OUTPUTS. However, it must also be told to which PIC INPUTS they + * are wired. + * Optionally, the first PIC input line can be read from PCI config space + * but the second must be passed to this routine. Note that the info read + * from PCI config space is wrong for many boards! + * + * PARAMETERS: + * vmeIrqUnivOut: to which output pin (of the universe) should the 7 + * VME irq levels be routed. + * vmeIrqPicLine: specifies to which PIC input the 'main' output is + * wired. If passed a value < 0, the driver reads this + * information from PCI config space ("IRQ line"). + * specialIrqUnivOut: to which output pin (of the universe) should the + * internally irqs be routed. Use 'vmeIRQunivOut' + * if < 0. + * specialIrqPicLine: specifies to which PIC input the 'special' output + * pin is wired. The wiring of the 'vmeIRQunivOut' to + * the PIC is determined by reading PCI config space. + * + * RETURNS: 0 on success, -1 on failure. + * + */ + +/* This routine is outside of the __INSIDE_RTEMS_BSP__ test for bwrds compatibility ONLY */ +int +vmeUniverseInstallIrqMgr(int vmeIrqUnivOut, + int vmeIrqPicLine, + int specialIrqUnivOut, + int specialIrqPicLine); + + +#if defined(__INSIDE_RTEMS_BSP__) +#include + +/* up to 4 universe outputs are now supported by this alternate + * entry point. + * Terminate the vararg list (uni_pin/pic_pin pairs) with a + * '-1' uni_pin. + * E.g., the old interface is now just a wrapper to + * vmeUniverseInstallIrqMgrAlt(0, vmeUnivOut, vmePicLint, specUnivOut, specPicLine, -1); + * + * The 'IRQ_MGR_SHARED' flag uses the BSP_install_rtems_shared_irq_handler() + * API. CAVEAT: shared interrupts need RTEMS workspace, i.e., the + * VME interrupt manager can only be installed *after workspace is initialized* + * if 'shared' is nonzero (i.e., *not* from bspstart()). + * + * If 'PW_WORKAROUND' flag is set then the interrupt manager will try to + * find a way to access the control registers from VME so that the universe's + * posted write FIFO can be flushed after the user ISR returns: + * + * The installation routine looks first for CSR registers in CSR space (this + * requires: + * - a VME64 crate with autoid or geographical addressing + * - the firmware or BSP to figure out the slot number and program the CSR base + * in the universe. + * - the BSP to open an outbound window to CSR space. + * + * If CSR registers cannot be found then the installation routine looks for CRG registers: + * - BSP must map CRG on VME + * - CRG must be visible in outbound window + * CAVEAT: multiple boards with same BSP on single backplane must not map their CRG + * to the same address! + */ + +#define VMEUNIVERSE_IRQ_MGR_FLAG_SHARED 1 /* use shared interrupts */ +#define VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND 2 /* use shared interrupts */ + +int +vmeUniverseInstallIrqMgrAlt(int flags, int uni_pin0, int pic_pin0, ...); + +int +vmeUniverseInstallIrqMgrVa(int flags, int uni_pin0, int pic_pin0, va_list ap); + +#endif /* __INSIDE_RTEMS_BSP__ */ +#endif /* __rtems__ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/vmeUniverseDMA.h b/bsps/include/bsp/vmeUniverseDMA.h new file mode 100644 index 0000000000..d0a3d6f0e7 --- /dev/null +++ b/bsps/include/bsp/vmeUniverseDMA.h @@ -0,0 +1,95 @@ +/** + * @file + * + * @ingroup shared_vmeuniversedma + * + * @brief vmeUniverseDMA Support + */ + +#ifndef VME_UNIVERSE_DMA_H +#define VME_UNIVERSE_DMA_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2006, 2007 + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_vmeuniversedma vmeUniverseDMA Support + * + * @ingroup shared_vmeuniverse + * + * @brief vmeUniverseDMA Support Package + */ + +extern struct VMEDmaListClassRec_ vmeUniverseDmaListClass; + +int +vmeUniverseDmaSetupXX(volatile LERegister *base, int channel, uint32_t mode, uint32_t xfer_mode, void *custom); + +int +vmeUniverseDmaSetup(int channel, uint32_t mode, uint32_t xfer_mode, void *custom); + +int +vmeUniverseDmaStartXX(volatile LERegister *base, int channel, uint32_t pci_addr, uint32_t vme_addr, uint32_t n_bytes); + +int +vmeUniverseDmaStart(int channel, uint32_t pci_addr, uint32_t vme_addr, uint32_t n_bytes); + +uint32_t +vmeUniverseDmaStatusXX(volatile LERegister *base, int channel); + +uint32_t +vmeUniverseDmaStatus(int channel); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/vme_am_defs.h b/bsps/include/bsp/vme_am_defs.h new file mode 100644 index 0000000000..efa28b3aa0 --- /dev/null +++ b/bsps/include/bsp/vme_am_defs.h @@ -0,0 +1,198 @@ +/** + * @file + * + * @ingroup shared_vmeamdefs + * + * @brief vxworks compatible addressing modes + */ + +#ifndef VME_AM_DEFINITIONS_H +#define VME_AM_DEFINITIONS_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2002-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +/** + * @defgroup shared_vmeamdefs VME_AM_DEFS + * + * @ingroup shared_vmeuniverse + * + * @brief 64-bit *addresses* are not supported [data are]. + */ + +#ifndef VME_AM_STD_SUP_BLT +#define VME_AM_STD_SUP_BLT 0x3f +#endif +#ifndef VME_AM_STD_SUP_ASCENDING +#define VME_AM_STD_SUP_ASCENDING 0x3f +#endif +#ifndef VME_AM_STD_SUP_PGM +#define VME_AM_STD_SUP_PGM 0x3e +#endif +#ifndef VME_AM_STD_SUP_MBLT +#define VME_AM_STD_SUP_MBLT 0x3c +#endif +#ifndef VME_AM_STD_USR_BLT +#define VME_AM_STD_USR_BLT 0x3b +#endif +#ifndef VME_AM_STD_USR_ASCENDING +#define VME_AM_STD_USR_ASCENDING 0x3b +#endif +#ifndef VME_AM_STD_USR_PGM +#define VME_AM_STD_USR_PGM 0x3a +#endif +#ifndef VME_AM_STD_SUP_DATA +#define VME_AM_STD_SUP_DATA 0x3d +#endif +#ifndef VME_AM_STD_USR_DATA +#define VME_AM_STD_USR_DATA 0x39 +#endif +#ifndef VME_AM_STD_USR_MBLT +#define VME_AM_STD_USR_MBLT 0x38 +#endif +#ifndef VME_AM_EXT_SUP_BLT +#define VME_AM_EXT_SUP_BLT 0x0f +#endif +#ifndef VME_AM_EXT_SUP_ASCENDING +#define VME_AM_EXT_SUP_ASCENDING 0x0f +#endif +#ifndef VME_AM_EXT_SUP_PGM +#define VME_AM_EXT_SUP_PGM 0x0e +#endif +#ifndef VME_AM_EXT_SUP_DATA +#define VME_AM_EXT_SUP_DATA 0x0d +#endif +#ifndef VME_AM_EXT_SUP_MBLT +#define VME_AM_EXT_SUP_MBLT 0x0c +#endif +#ifndef VME_AM_EXT_USR_BLT +#define VME_AM_EXT_USR_BLT 0x0b +#endif +#ifndef VME_AM_EXT_USR_ASCENDING +#define VME_AM_EXT_USR_ASCENDING 0x0b +#endif +#ifndef VME_AM_EXT_USR_PGM +#define VME_AM_EXT_USR_PGM 0x0a +#endif +#ifndef VME_AM_EXT_USR_DATA +#define VME_AM_EXT_USR_DATA 0x09 +#endif +#ifndef VME_AM_EXT_USR_MBLT +#define VME_AM_EXT_USR_MBLT 0x08 +#endif +#ifndef VME_AM_2eVME_6U +#define VME_AM_2eVME_6U 0x20 +#endif +#ifndef VME_AM_2eVME_3U +#define VME_AM_2eVME_3U 0x21 +#endif +#ifndef VME_AM_CSR +#define VME_AM_CSR 0x2f +#endif +#ifndef VME_AM_SUP_SHORT_IO +#define VME_AM_SUP_SHORT_IO 0x2d +#endif +#ifndef VME_AM_USR_SHORT_IO +#define VME_AM_USR_SHORT_IO 0x29 +#endif +#ifndef VME_AM_IS_SHORT +#define VME_AM_IS_SHORT(a) (((a) & 0x30) == 0x20) +#endif +#ifndef VME_AM_IS_STD +#define VME_AM_IS_STD(a) (((a) & 0x30) == 0x30) +#endif +#ifndef VME_AM_IS_EXT +#define VME_AM_IS_EXT(a) (((a) & 0x30) == 0x00) +#endif +#ifndef VME_AM_IS_SUP +#define VME_AM_IS_SUP(a) ((a) & 4) +#endif + +/* Mask for standard address modifiers */ + +#ifndef VME_AM_MASK +#define VME_AM_MASK 0x3f +#endif + +/* Hint that a window is mapping memory; the + * driver may assume it to be safe to enable decoupled + * cycles, caching and the like... + */ +#ifndef VME_AM_IS_MEMORY +#define VME_AM_IS_MEMORY (1<<8) +#endif + +/* I don't know AMs for 2eSST so we use some extra bits; + * HOWEVER: these are just qualifiers to the VME_AM_2eVME_xx modes + * i.e., if you want 2eSST you must also select 2eVME... + */ + +/* 2eSST broadcast; you still need to set one of the speed bits */ +#define VME_AM_2eSST_BCST (1<<9) +/* Low speed (driver specific) */ +#define VME_AM_2eSST_LO (1<<10) +/* Mid speed (driver specific) */ +#define VME_AM_2eSST_MID (2<<10) +/* High speed (driver specific) */ +#define VME_AM_2eSST_HI (3<<10) + +#define VME_AM_IS_2eSST(am) ((am) & (3<<10)) + +/* Use 8/16/32-bit transfers for coupled- or BLT cycles + * (MBLT, 2exxx are probably always 64-bit) + */ +#define VME_MODE_DBW_MSK (3<<12) +#define VME_MODE_DBW8 (1<<12) +#define VME_MODE_DBW16 (2<<12) +#define VME_MODE_DBW32 (3<<12) + +/* Unused Flags 1<<14 .. 1<<23 are reserved + * + * (20-23 used by DMA API). + * Flags 1<<24 .. 1<<31 are for driver specific options + */ + + +#endif diff --git a/bsps/include/libchip/am29lv160.h b/bsps/include/libchip/am29lv160.h new file mode 100644 index 0000000000..49d8e248ac --- /dev/null +++ b/bsps/include/libchip/am29lv160.h @@ -0,0 +1,55 @@ +/* + * RTEMS Project (http://www.rtems.org/) + * + * Copyright 2007 Chris Johns (chrisj@rtems.org) + */ + +/** + * Flash Disk Device Driver. + * + * Am29LV160D 16 Megabit (2M x 8bit) 3.0 Volt-only + * Boot Sctor Flash Memory. + */ + +#if !defined (_RTEMS_AM29LV160_H_) +#define _RTEMS_AM29LV160_H_ + +#include + +/** + * The segments in the AM29LV160 top boot block device. + */ +#define rtems_am29lv160t_segment_count (4) +extern const rtems_fdisk_segment_desc rtems_am29lv160t_segments[4]; + +/** + * The segments in the AM29LV160 bottom boot block device. + */ +#define rtems_am29lv160b_segment_count (4) +extern const rtems_fdisk_segment_desc rtems_am29lv160b_segments[4]; + +/** + * The segments in the AM29LV160 top boot block device. + */ +extern const rtems_fdisk_driver_handlers rtems_am29lv160_handlers; + +/** + * The device configuration. + */ +typedef struct rtems_am29lv160_config +{ + int bus_8bit; + void* base; +} rtems_am29lv160_config; + +/** + * External reference to the configuration. + */ +extern const rtems_am29lv160_config rtems_am29lv160_configuration[]; + +/** + * External reference to the configuration size + */ +extern uint32_t rtems_am29lv160_configuration_size; + +#endif diff --git a/bsps/include/libchip/ata.h b/bsps/include/libchip/ata.h new file mode 100644 index 0000000000..66cc46747d --- /dev/null +++ b/bsps/include/libchip/ata.h @@ -0,0 +1,50 @@ +/* + * ata.h + * + * ATA RTEMS driver header file. This file should be included from an + * application. + * + * Copyright (C) 2002 OKTET Ltd., St.-Petersburg, Russia + * Author: Eugeny S. Mints + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __ATA_H__ +#define __ATA_H__ + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +rtems_device_driver rtems_ata_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *args); + +#define ATA_DRIVER_TABLE_ENTRY \ + {rtems_ata_initialize, RTEMS_GENERIC_BLOCK_DEVICE_DRIVER_ENTRIES} + +/* ATA IOCTL request codes */ +#define ATAIO_SET_MULTIPLE_MODE _IO('A', 1) + +/* + * ATA driver configuration parameters + * FIXME: should be configured more easy... + */ +#define ATA_DRIVER_MESSAGE_QUEUE_SIZE 50 +#define ATA_DRIVER_TASK_STACK_SIZE 16*1024 +#define ATA_DRIVER_TASK_DEFAULT_PRIORITY 140 + extern rtems_task_priority rtems_ata_driver_task_priority; +#ifdef __cplusplus +} +#endif + + +#endif /* __ATA_H__ */ diff --git a/bsps/include/libchip/ata_internal.h b/bsps/include/libchip/ata_internal.h new file mode 100644 index 0000000000..985b6f597c --- /dev/null +++ b/bsps/include/libchip/ata_internal.h @@ -0,0 +1,323 @@ +/* + * ata_internal.h + * + * ATA RTEMS driver internal header file + * + * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia + * Authors: Eugeny S. Mints + * Alexandra Kossovsky + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ +#ifndef __ATA_INTERNAL_H__ +#define __ATA_INTERNAL_H__ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Conversion from and to little-endian byte order. (no-op on i386/i486) + * + * Naming: Ca_b_c, where a: F = from, T = to, b: LE = little-endian, + * BE = big-endian, c: W = word (16 bits), L = longword (32 bits) + */ +#define CF_LE_W(v) le16toh(v) +#define CF_LE_L(v) le32toh(v) +#define CT_LE_W(v) htole16(v) +#define CT_LE_L(v) htole32(v) + +#define ATA_UNDEFINED_VALUE (-1) + +/* Sector size for all ATA devices */ +#define ATA_SECTOR_SIZE 512 + + +#define ATA_MAX_CMD_REG_OFFSET 8 + + +/* ATA Commands */ + +/* Types of ATA commands */ +#define ATA_COMMAND_TYPE_NON_DATA 0 +#define ATA_COMMAND_TYPE_PIO_IN 1 +#define ATA_COMMAND_TYPE_PIO_OUT 2 +#define ATA_COMMAND_TYPE_DMA 3 + +/* ATA commands opcodes */ +/* + * Commands present in both ATA-2 and ATA-4 specs. + * Some commands have two values in ATA-2, + * in such case value from ATA-4 used. + * Some commands have slightly different names in these specifications, + * so names from ATA-4 are used. + */ +#define ATA_COMMAND_NOP 0x00 +#define ATA_COMMAND_READ_SECTORS 0x20 +#define ATA_COMMAND_WRITE_SECTORS 0x30 +#define ATA_COMMAND_READ_VERIFY_SECTORS 0x40 +#define ATA_COMMAND_SEEK 0x70 /* or 0x7. */ +#define ATA_COMMAND_EXECUTE_DEVICE_DIAGNOSTIC 0x90 +#define ATA_COMMAND_INITIALIZE_DEVICE_PARAMETERS 0x91 +#define ATA_COMMAND_DOWNLOAD_MICROCODE 0x92 +#define ATA_COMMAND_READ_MULTIPLE 0xc4 +#define ATA_COMMAND_WRITE_MULTIPLE 0xc5 +#define ATA_COMMAND_SET_MULTIPLE_MODE 0xc6 +#define ATA_COMMAND_READ_DMA 0xc8 +#define ATA_COMMAND_WRITE_DMA 0xca +#define ATA_COMMAND_STANDBY_IMMEDIATE 0xe0 /* or 0x94 */ +#define ATA_COMMAND_IDLE_IMMEDIATE 0xe1 /* or 0x95 */ +#define ATA_COMMAND_STANDBY 0xe2 /* or 0x96 */ +#define ATA_COMMAND_IDLE 0xe3 /* or 0x97 */ +#define ATA_COMMAND_READ_BUFFER 0xe4 +#define ATA_COMMAND_CHECK_POWER_MODE 0xe5 /* or 0x98 in ATA-2 */ +#define ATA_COMMAND_SLEEP 0xe6 /* or 0x99 */ +#define ATA_COMMAND_WRITE_BUFFER 0xe8 +#define ATA_COMMAND_IDENTIFY_DEVICE 0xec +#define ATA_COMMAND_SET_FEATURES 0xef + +/* Commands present in both ATA-2 and ATA-4 specs: removable media */ +#define ATA_COMMAND_MEDIA_LOCK 0xde +#define ATA_COMMAND_MEDIA_UNLOCK 0xdf +#define ATA_COMMAND_MEDIA_EJECT 0xed + + +/* Commands present in ATA-2, but not in ATA-4 (not used) */ +#define ATA_COMMAND_RECALIBRATE 0x10 /* or 0x1. */ +#define ATA_COMMAND_READ_SECTOR_NON_RETRY 0x21 +#define ATA_COMMAND_READ_LONG_RETRY 0x22 +#define ATA_COMMAND_READ_LONG_NON_RETRY 0x23 +#define ATA_COMMAND_WRITE_SECTOR_NON_RETRY 0x31 +#define ATA_COMMAND_WRITE_LONG_RETRY 0x32 +#define ATA_COMMAND_WRITE_LONG_NON_RETRY 0x33 +#define ATA_COMMAND_WRITE_VERIFY 0x3c +#define ATA_COMMAND_READ_VERIFY_SECTOR_NON_RETRY 0x41 +#define ATA_COMMAND_FORMAT_TRACK 0x50 +#define ATA_COMMAND_READ_DMA_NON_RETRY 0xc9 +#define ATA_COMMAND_WRITE_DMA_NON_RETRY 0xcb +#define ATA_COMMAND_ACKNOWLEGE_MEDIA_CHANGE 0xdb +#define ATA_COMMAND_BOOT_POST_BOOT 0xdc +#define ATA_COMMAND_BOOT_PRE_BOOT 0xdd +#define ATA_COMMAND_WRITE_SAME 0xe9 + +/* Commands from ATA-4 specification: CFA feature set */ +#define ATA_COMMAND_CFA_REQUEST_EXTENDED_ERROR_CODE 0x03 +#define ATA_COMMAND_CFA_WRITE_SECTORS_WITHOUT_ERASE 0x38 +#define ATA_COMMAND_CFA_TRANSLATE_SECTOR 0x87 +#define ATA_COMMAND_CFA_ERASE_SECTORS 0xc0 +#define ATA_COMMAND_CFA_WRITE_MULTIPLE_WITHOUT_ERASE 0xcd + +/* Commands from ATA-4 specification: commands to use with PACKET command */ +#define ATA_COMMAND_DEVICE_RESET 0x08 +#define ATA_COMMAND_PACKET 0xa0 +#define ATA_COMMAND_IDENTIFY_PACKET_DEVICE 0xa1 +#define ATA_COMMAND_SERVICE 0xa2 + +/* Commands from ATA-4 specification: SECURITY commands */ +#define ATA_COMMAND_SECURITY_SET_PASSWORD 0xf1 +#define ATA_COMMAND_SECURITY_UNLOCK 0xf2 +#define ATA_COMMAND_SECURITY_ERASE_PREPARE 0xf3 +#define ATA_COMMAND_SECURITY_ERASE_UNIT 0xf4 +#define ATA_COMMAND_SECURITY_FREEZE_LOCK 0xf5 +#define ATA_COMMAND_SECURITY_DISABLE_PASSWORD 0xf6 + +/* Commands from ATA-4 specification: other commands */ +#define ATA_COMMAND_SMART 0xb0 +#define ATA_COMMAND_READ_DMA_QUEUED 0xc7 +#define ATA_COMMAND_WRITE_DMA_QUEUED 0xcc +#define ATA_COMMAND_GET_MEDIA_STATUS 0xda +#define ATA_COMMAND_FLUSH_CACHE 0xe7 +#define ATA_COMMAND_READ_NATIVE_MAX_ADDRESS 0xf8 +#define ATA_COMMAND_SET_MAX_ADDRESS 0xf9 + +#define ATA_REGISTERS_VALUE(reg) (1 << (reg)) + +/* ATA IDENTIFY DEVICE command words and bits */ +#define ATA_IDENT_WORD_RW_MULT 47 +#define ATA_IDENT_WORD_CAPABILITIES 49 +#define ATA_IDENT_WORD_FIELD_VALIDITY 53 +#define ATA_IDENT_WORD_NUM_OF_CURR_LOG_CLNDS 54 +#define ATA_IDENT_WORD_NUM_OF_CURR_LOG_HEADS 55 +#define ATA_IDENT_WORD_NUM_OF_CURR_LOG_SECS 56 +#define ATA_IDENT_WORD_MULT_SECS 59 +#define ATA_IDENT_WORD_NUM_OF_USR_SECS0 60 +#define ATA_IDENT_WORD_NUM_OF_USR_SECS1 61 +#define ATA_IDENT_WORD_PIO_SPPRTD 64 + +#define ATA_IDENT_BIT_VALID 0x02 + +/* + * It is OR for all ATA_REGISTERS_VALUE(reg), where reg is neccessary + * for setting block position + */ +#define ATA_REGISTERS_POSITION 0xfc + +#define ATA_MINOR_NUM_RESERVED_PER_ATA_DEVICE 64 + +#define ATA_MAX_RTEMS_INT_VEC_NUMBER 255 + +#define ATA_MAX_NAME_LENGTH 10 + +/* diagnostic codes */ +#define ATA_DEV0_PASSED_DEV1_PASSED_OR_NOT_PRSNT 0x01 +#define ATA_DEV0_PASSED_DEV1_FAILED 0x81 +#define ATA_DEV1_PASSED_DEV0_FAILED 0x80 + +/* + * Obtain ata device parameters by controller minor number and device number + */ +#define ATA_DEV_INFO(controller_minor, dev) \ + ata_ide_ctrls[controller_minor].device[dev] + +/* ATA RTEMS driver internal data stuctures */ + +/* Command block registers */ +typedef struct ata_registers_s { + uint16_t regs[8]; /* command block registers */ + uint16_t to_read; /* mask: which ata registers should be read */ + uint16_t to_write; /* mask: which ata registers should be written */ +} ata_registers_t; + +/* ATA request */ +typedef struct ata_req_s { + rtems_chain_node link; /* link in requests chain */ + char type; /* request type */ + ata_registers_t regs; /* ATA command */ + uint32_t cnt; /* Number of sectors to be exchanged */ + uint32_t cbuf; /* number of current buffer from breq in use */ + uint32_t pos; /* current position in 'cbuf' */ + rtems_blkdev_request *breq; /* blkdev_request which corresponds to the + * ata request + */ + rtems_id sema; /* semaphore which is used if synchronous + * processing of the ata request is required + */ + rtems_status_code status; /* status of ata request processing */ + int info; /* device info code */ +} ata_req_t; + +/* call callback provided by block device request if it is defined */ +#define ATA_EXEC_CALLBACK(areq, status) \ + do {\ + if ((areq)->breq != NULL) \ + rtems_blkdev_request_done((areq)->breq, status); \ + } while (0) + +/* ATA RTEMS driver events types */ +typedef enum ata_msg_type_s { + ATA_MSG_GEN_EVT = 1, /* general event */ + ATA_MSG_SUCCESS_EVT, /* success event */ + ATA_MSG_ERROR_EVT, /* error event */ + ATA_MSG_PROCESS_NEXT_EVT /* process next request event */ +} ata_msg_type_t; + +/* ATA RTEMS driver message */ +typedef struct ata_queue_msg_s { + ata_msg_type_t type; /* message type */ + rtems_device_minor_number ctrl_minor; /* IDE controller minor number */ + int error; /* error code */ +} ata_queue_msg_t; + +/* macros for messages processing */ +#define ATA_FILL_MSG(msg, evt_type, ctrl, err)\ + do {\ + msg.type = evt_type;\ + msg.ctrl_minor = ctrl;\ + msg.error = err;\ + } while (0) + +#define ATA_SEND_EVT(msg, type, ctrl, err)\ + do {\ + rtems_status_code rc;\ + ATA_FILL_MSG(msg, type, ctrl, err);\ + rc = rtems_message_queue_send(ata_queue_id, &msg,\ + sizeof(ata_queue_msg_t));\ + if (rc != RTEMS_SUCCESSFUL)\ + rtems_fatal_error_occurred(RTEMS_INTERNAL_ERROR);\ + } while (0) + +/* + * Array of such structures is indexed by interrupt vecotrs and used for + * mapping of IDE controllers and interrupt vectors + */ +typedef struct ata_int_st_s { + rtems_chain_node link; + rtems_device_minor_number ctrl_minor; +} ata_int_st_t; + +/* + * Mapping of rtems ATA devices to the following pairs: + * (IDE controller number served the device, device number on the controller) + */ +typedef struct ata_ide_dev_s { + int ctrl_minor;/* minor number of IDE controller served rtems ATA device */ + int device; /* device number on IDE controller (0 or 1) */ +} ata_ide_dev_t; + +/* + * ATA device description + */ +typedef struct ata_dev_s { + int8_t present; /* 1 -- present, 0 -- not present, */ + /* -1 -- non-initialized */ + uint16_t cylinders; + uint16_t heads; + uint16_t sectors; + uint32_t lba_sectors; /* for small disk */ + /* == cylinders * heads * sectors */ + + uint8_t lba_avaible; /* 0 - CHS mode, 1 - LBA mode */ + + uint16_t modes_available; /* OR of values for this modes */ + uint16_t mode_active; +} ata_dev_t; + +/* + * This structure describes controller state, devices configuration on the + * controller and chain of ATA requests to the controller. Array of such + * structures is indexed by controller minor number + */ +typedef struct ata_ide_ctrl_s { + bool present; /* controller state */ + ata_dev_t device[2]; /* ata diveces description */ + rtems_chain_control reqs; /* requests chain */ +} ata_ide_ctrl_t; + +/* Block device request with a single buffer provided */ +typedef struct blkdev_request1 { + rtems_blkdev_request req; + rtems_blkdev_sg_buffer sg[1]; +} blkdev_request1; + +void ata_breq_init(blkdev_request1 *breq, uint16_t *sector_buffer); + +rtems_status_code ata_identify_device( + rtems_device_minor_number ctrl_minor, + int dev, + uint16_t *sector_buffer, + ata_dev_t *device_entry +); + +void ata_process_request_on_init_phase( + rtems_device_minor_number ctrl_minor, + ata_req_t *areq +); + +#ifdef __cplusplus +} +#endif + +#endif /* __ATA_INTERNAL_H__ */ diff --git a/bsps/include/libchip/cs8900.h b/bsps/include/libchip/cs8900.h new file mode 100644 index 0000000000..79c943842d --- /dev/null +++ b/bsps/include/libchip/cs8900.h @@ -0,0 +1,761 @@ +/* + ------------------------------------------------------------------------ + + Copyright Cybertec Pty Ltd, 2000 + All rights reserved Cybertec Pty Ltd, 2000 + + Port to the DIMM PC copyright (c) 2004 Angelo Fraietta + This project has been assisted by the Commonwealth Government + through the Australia Council, its arts funding and advisory body. + + COPYRIGHT (c) 1989-1998. + On-Line Applications Research Corporation (OAR). + + The license and distribution terms for this file may be + found in the file LICENSE in this distribution or at + http://www.rtems.org/license/LICENSE. + + ------------------------------------------------------------------------ + + CS8900 RTEMS driver. + + This is a generic driver that requires a BSP backend. The BSP backend + provides the glue to the specific bus for the target hardware. It has + been tested with Coldfire processors, and the PC. These targets have + completely different bus, byte order and interrupt structures. + + An example BSP backend is provided in the pci386 BSP. + + The BSP provides the following functions: + + cs8900_io_set_reg + cs8900_io_get_reg + cs8900_mem_set_reg + cs8900_mem_get_reg + cs8900_put_data_block + cs8900_get_data_block + cs8900_tx_load + cs8900_attach_interrupt + cs8900_detach_interrupt + + The header file provides documentation for these functions. There + are four types of functions. + + The I/O set/get functions access the CS8900 I/O registers via the + I/O Mode. For example on a PC with an ISA bus you would use the + IA32 in/out port instructions. The cs8900_device structure passed + to these functions provide these functions with the I/O base + address. The BSP must provide these functions. + + The Memory set/get functions access the CS8900 internal registers + and frame buffers directly from a 4K byte block of host memory. + Memory mode provides a faster access to the CS8900. The cs8900_device + structure passed to these functions provides the memory base + address. The BSP needs to provide these functions but they do not + need to be implemented if the mem_base field is set to 0. The + driver will use I/O mode only. + + The Block transfer functions are used to read or write a block + of memory from the CS8900. This saves the driver making a number + of small calls. The BSP driver must know if I/O or Memory mode + can be used. + + The final group of functions is to handle interrupts. The BSP + must take care of save and restoring any interrupt state + information. + + The BSP declares a 'cs8900_device' structure for each device being + attached to the networking stack. It also creates a + 'struct rtems_bsdnet_ifconfig' which is used to attach the interface + to the networking stack. The following code declares the BSD config: + + static cs8900_device cs8900; + + static struct rtems_bsdnet_ifconfig cs8900_ifconfig = + { + "cs0", + cs8900_driver_attach, + NULL, + NULL, + NULL, + NULL, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 + }; + + The device linked to the BSD config structure with: + + cs8900_ifconfig.drv_ctrl = &cs8900; + + If you have a specific hardware address you should point the BSD + config structure to that address. If you do not the driver will read + the MAC address from the CS8900. This assumes the CS8900 has read + the address from an external EEPROM or has been setup by a BIOS or + boot monitor. For EEPROM less you need to supply the MAC address. + + Set the I/O and Memory base addresses. If the Memory base address + is 0 the driver will use I/O mode only. A typical initialisation + looks like: + + printf ("RTEMS BSD Network initialisation.\n"); + rtems_bsdnet_initialize_network (); + + #define ETHERNET_IO_BASE 0x300 + #define ETHERNET_MEM_BASE 0 + #define ETHERNET_IRQ_LEVEL 0 + + cs8900_device *cs = &cs8900; + + memset (cs, 0, sizeof (cs8900_device)); + + cs->dev = 0; + cs->io_base = ETHERNET_IO_BASE; + cs->mem_base = ETHERNET_MEM_BASE; + cs->irq_level = ETHERNET_IRQ_LEVEL; + cs->rx_queue_size = 30; + + cs8900_ifconfig.drv_ctrl = &cs8900; + + printf ("CS8900 initialisation\n"); + + rtems_bsdnet_attach (&cs8900_ifconfig); + + flags = IFF_UP; + if (rtems_bsdnet_ifconfig (cs8900_ifconfig.name, + SIOCSIFFLAGS, + &flags) < 0) + { + printf ("error: can't bring up %s: %s\n", + cs8900_ifconfig.name, strerror (errno)); + return; + } + + rtems_bsdnet_do_bootp_and_rootfs (); + + The IRQ level is the one documented in the CS8900 datasheet and below + in the CS8900 device structure. You need to map your target IRQ to the + CS8900 in the BSP driver. + + */ + +#if !defined(_CS8900_H_) +#define _CS8900_H_ + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include + +/* #include what does this provide? joel to chris */ + +#define ET_MINLEN 60 + +/* + * CS8900 device register definitions + */ + +/* + * Crystal ESIA product id. + */ + +#define CS8900_ESIA_ID (0x630e) + +/* + * IO Registers. + */ + +#define CS8900_IO_RX_TX_DATA_PORT0 (0x0000) +#define CS8900_IO_TX_TX_DATA_PORT1 (0x0002) +#define CS8900_IO_TxCMD (0x0004) +#define CS8900_IO_TxLength (0x0006) +#define CS8900_IO_ISQ (0x0008) +#define CS8900_IO_PACKET_PAGE_PTR (0x000a) +#define CS8900_IO_PP_DATA_PORT0 (0x000c) +#define CS8900_IO_PP_DATA_PORT1 (0x000e) + +/* + * Packet Page Registers. + */ + +/* + * Bus Interface Registers. + */ + +#define CS8900_PP_PROD_ID (0x0000) +#define CS8900_PP_IO_BASE (0x0020) +#define CS8900_PP_INT (0x0022) +#define CS8900_PP_DMA_CHANNEL (0x0024) +#define CS8900_PP_DMA_SOF (0x0026) +#define CS8900_PP_DMA_FRM_CNT (0x0028) +#define CS8900_PP_DMA_RX_BCNT (0x002a) +#define CS8900_PP_MEM_BASE (0x002c) +#define CS8900_PP_BPROM_BASE (0x0030) +#define CS8900_PP_BPROM_AMASK (0x0034) +#define CS8900_PP_EEPROM_CMD (0x0040) +#define CS8900_PP_EEPROM_DATA (0x0042) +#define CS8900_PP_RX_FRAME_BCNT (0x0050) + +/* + * Configuration and Control Registers. + */ + +#define CS8900_PP_RxCFG (0x0102) +#define CS8900_PP_RxCTL (0x0104) +#define CS8900_PP_TxCFG (0x0106) +#define CS8900_PP_TxCMD_READ (0x0108) +#define CS8900_PP_BufCFG (0x010a) +#define CS8900_PP_LineCFG (0x0112) +#define CS8900_PP_SelfCTL (0x0114) +#define CS8900_PP_BusCTL (0x0116) +#define CS8900_PP_TestCTL (0x0118) + +/* + * Status and Event Registers. + */ + +#define CS8900_PP_ISQ (0x0120) +#define CS8900_PP_RxEvent (0x0124) +#define CS8900_PP_TxEvent (0x0128) +#define CS8900_PP_BufEvent (0x012c) +#define CS8900_PP_RxMISS (0x0130) +#define CS8900_PP_TxCol (0x0132) +#define CS8900_PP_LineST (0x0134) +#define CS8900_PP_SelfST (0x0136) +#define CS8900_PP_BusST (0x0138) +#define CS8900_PP_TDR (0x013c) + +/* + * Initiate Transmit Registers. + */ + +#define CS8900_PP_TxCMD (0x0144) +#define CS8900_PP_TxLength (0x0146) + +/* + * Address Filter Registers. + */ + +#define CS8900_PP_LAF (0x0150) +#define CS8900_PP_IA (0x0158) + +/* + * Frame Location. + */ + +#define CS8900_PP_RxStatus (0x0400) +#define CS8900_PP_RxLength (0x0402) +#define CS8900_PP_RxFrameLoc (0x0404) +#define CS8900_PP_TxFrameLoc (0x0a00) + +/* + * Bit Definitions of Registers. + */ + +/* + * IO Packet Page Pointer. + */ + +#define CS8900_PPP_AUTO_INCREMENT (0x8000) + +/* + * Reg 3. Receiver Configuration. + */ + +#define CS8900_RX_CONFIG_SKIP_1 (1 << 6) +#define CS8900_RX_CONFIG_STREAM_ENABLE (1 << 7) +#define CS8900_RX_CONFIG_RX_OK (1 << 8) +#define CS8900_RX_CONFIG_RX_DMA (1 << 9) +#define CS8900_RX_CONFIG_RX_AUTO_DMA (1 << 10) +#define CS8900_RX_CONFIG_BUFFER_CRC (1 << 11) +#define CS8900_RX_CONFIG_CRC_ERROR (1 << 12) +#define CS8900_RX_CONFIG_RUNT (1 << 13) +#define CS8900_RX_CONFIG_EXTRA_DATA (1 << 14) + +/* + * Reg 4. Receiver Event. + */ + +#define CS8900_RX_EVENT_HASH_IA_MATCH (1 << 6) +#define CS8900_RX_EVENT_DRIBBLE_BITS (1 << 7) +#define CS8900_RX_EVENT_RX_OK (1 << 8) +#define CS8900_RX_EVENT_HASHED (1 << 9) +#define CS8900_RX_EVENT_IA (1 << 10) +#define CS8900_RX_EVENT_BROADCAST (1 << 11) +#define CS8900_RX_EVENT_CRC_ERROR (1 << 12) +#define CS8900_RX_EVENT_RUNT (1 << 13) +#define CS8900_RX_EVENT_EXTRA_DATA (1 << 14) + +/* + * Reg 5. Receiver Control. + */ + +#define CS8900_RX_CTRL_HASH_IA_MATCH (1 << 6) +#define CS8900_RX_CTRL_PROMISCUOUS (1 << 7) +#define CS8900_RX_CTRL_RX_OK (1 << 8) +#define CS8900_RX_CTRL_MULTICAST (1 << 9) +#define CS8900_RX_CTRL_INDIVIDUAL (1 << 10) +#define CS8900_RX_CTRL_BROADCAST (1 << 11) +#define CS8900_RX_CTRL_CRC_ERROR (1 << 12) +#define CS8900_RX_CTRL_RUNT (1 << 13) +#define CS8900_RX_CTRL_EXTRA_DATA (1 << 14) + +/* + * Reg 7. Transmit Configuration. + */ + +#define CS8900_TX_CONFIG_LOSS_OF_CARRIER (1 << 6) +#define CS8900_TX_CONFIG_SQ_ERROR (1 << 7) +#define CS8900_TX_CONFIG_TX_OK (1 << 8) +#define CS8900_TX_CONFIG_OUT_OF_WINDOW (1 << 9) +#define CS8900_TX_CONFIG_JABBER (1 << 10) +#define CS8900_TX_CONFIG_ANY_COLLISION (1 << 11) +#define CS8900_TX_CONFIG_16_COLLISION (1 << 15) + +/* + * Reg 8. Transmit Event. + */ + +#define CS8900_TX_EVENT_LOSS_OF_CARRIER (1 << 6) +#define CS8900_TX_EVENT_SQ_ERROR (1 << 7) +#define CS8900_TX_EVENT_TX_OK (1 << 8) +#define CS8900_TX_EVENT_OUT_OF_WINDOW (1 << 9) +#define CS8900_TX_EVENT_JABBER (1 << 10) +#define CS8900_TX_EVENT_16_COLLISIONS (1 << 15) + +/* + * Reg 9. Transmit Command Status. + */ + +#define CS8900_TX_CMD_STATUS_TX_START_5 (0 << 6) +#define CS8900_TX_CMD_STATUS_TX_START_381 (1 << 6) +#define CS8900_TX_CMD_STATUS_TX_START_1021 (2 << 6) +#define CS8900_TX_CMD_STATUS_TX_START_ENTIRE (3 << 6) +#define CS8900_TX_CMD_STATUS_FORCE (1 << 8) +#define CS8900_TX_CMD_STATUS_ONE_COLLISION (1 << 9) +#define CS8900_TX_CMD_STATUS_INHIBIT_CRC (1 << 12) +#define CS8900_TX_CMD_STATUS_TX_PAD_DISABLED (1 << 13) + +/* + * Reg B. Buffer Configuration. + */ + +#define CS8900_BUFFER_CONFIG_SW_INT (1 << 6) +#define CS8900_BUFFER_CONFIG_RX_DMA_DONE (1 << 7) +#define CS8900_BUFFER_CONFIG_RDY_FOR_TX (1 << 8) +#define CS8900_BUFFER_CONFIG_TX_UNDERRUN (1 << 9) +#define CS8900_BUFFER_CONFIG_RX_MISSED (1 << 10) +#define CS8900_BUFFER_CONFIG_RX_128_BYTES (1 << 11) +#define CS8900_BUFFER_CONFIG_TX_COL_OVF (1 << 12) +#define CS8900_BUFFER_CONFIG_RX_MISSED_OVF (1 << 13) +#define CS8900_BUFFER_CONFIG_RX_DEST_MATCH (1 << 15) + +/* + * Reg C. Buffer Event. + */ + +#define CS8900_BUFFER_EVENT_SW_INT (1 << 6) +#define CS8900_BUFFER_EVENT_RX_DMA_DONE (1 << 7) +#define CS8900_BUFFER_EVENT_RDY_FOR_TX (1 << 8) +#define CS8900_BUFFER_EVENT_TX_UNDERRUN (1 << 9) +#define CS8900_BUFFER_EVENT_RX_MISSED (1 << 10) +#define CS8900_BUFFER_EVENT_RX_128_BYTES (1 << 11) +#define CS8900_BUFFER_EVENT_RX_DEST_MATCH (1 << 15) + +/* + * Reg 13. Line Control. + */ + +#define CS8900_LINE_CTRL_RX_ON (1 << 6) +#define CS8900_LINE_CTRL_TX_ON (1 << 7) +#define CS8900_LINE_CTRL_AUI (1 << 8) +#define CS8900_LINE_CTRL_10BASET (0 << 9) +#define CS8900_LINE_CTRL_AUTO_AUI_10BASET (1 << 9) +#define CS8900_LINE_CTRL_MOD_BACKOFF (1 << 11) +#define CS8900_LINE_CTRL_POLARITY_DISABLED (1 << 12) +#define CS8900_LINE_CTRL_2_PART_DEF_DISABLED (1 << 13) +#define CS8900_LINE_CTRL_LO_RX_SQUELCH (1 << 14) + +/* + * Reg 14. Line Status. + */ + +#define CS8900_LINE_STATUS_LINK_OK (1 << 7) +#define CS8900_LINE_STATUS_AUI (1 << 8) +#define CS8900_LINE_STATUS_10_BASE_T (1 << 9) +#define CS8900_LINE_STATUS_POLARITY_OK (1 << 12) +#define CS8900_LINE_STATUS_CRS (1 << 14) + +/* + * Reg 15. Self Control. + */ + +#define CS8900_SELF_CTRL_RESET (1 << 6) +#define CS8900_SELF_CTRL_SW_SUSPEND (1 << 8) +#define CS8900_SELF_CTRL_HW_SLEEP (1 << 9) +#define CS8900_SELF_CTRL_HW_STANDBY (1 << 10) +#define CS8900_SELF_CTRL_HC0E (1 << 12) +#define CS8900_SELF_CTRL_HC1E (1 << 13) +#define CS8900_SELF_CTRL_HCB0 (1 << 14) +#define CS8900_SELF_CTRL_HCB1 (1 << 15) + +/* + * Reg 16. Self Status. + */ + +#define CS8900_SELF_STATUS_3_3_V (1 << 6) +#define CS8900_SELF_STATUS_INITD (1 << 7) +#define CS8900_SELF_STATUS_SIBUST (1 << 8) +#define CS8900_SELF_STATUS_EEPROM_PRESENT (1 << 9) +#define CS8900_SELF_STATUS_EEPROM_OK (1 << 10) +#define CS8900_SELF_STATUS_EL_PRESENT (1 << 11) +#define CS8900_SELF_STATUS_EE_SIZE (1 << 12) + +/* + * Reg 17. Bus Control. + */ + +#define CS8900_BUS_CTRL_RESET_RX_DMA (1 << 6) +#define CS8900_BUS_CTRL_USE_SA (1 << 9) +#define CS8900_BUS_CTRL_MEMORY_ENABLE (1 << 10) +#define CS8900_BUS_CTRL_DMA_BURST (1 << 11) +#define CS8900_BUS_CTRL_IOCHRDYE (1 << 12) +#define CS8900_BUS_CTRL_RX_DMA_SIZE (1 << 13) +#define CS8900_BUS_CTRL_ENABLE_INT (1 << 15) + +/* + * Reg 18. Bus Status. + */ + +#define CS8900_BUS_STATUS_TX_BID_ERROR (1 << 7) +#define CS8900_BUS_STATUS_RDY_FOR_TX_NOW (1 << 8) + +/* + * Trace for debugging the isq processing. Define to 1 to enable. + */ +#define CS8900_TRACE 0 +#define CS8900_TRACE_SIZE (400) + +/* + * The default receive queue size. If the BSP sets this field to + * 0 this default is used. + */ +#define CS8900_RX_QUEUE_SIZE (30) + +/* + * Stats, more for debugging than anything else. + */ + +typedef struct +{ + unsigned long rx_packets; /* total packets received */ + unsigned long tx_packets; /* total packets transmitted */ + unsigned long rx_bytes; /* total bytes received */ + unsigned long tx_bytes; /* total bytes transmitted */ + unsigned long rx_interrupts; /* total number of rx interrupts */ + unsigned long tx_interrupts; /* total number of tx interrupts */ + + /* detailed rx errors: */ + unsigned long rx_dropped; /* no mbufs in queue */ + unsigned long rx_no_mbufs; /* no mbufs */ + unsigned long rx_no_clusters; /* no clusters */ + unsigned long rx_oversize_errors; + unsigned long rx_crc_errors; /* recved pkt with crc error */ + unsigned long rx_runt_errors; + unsigned long rx_missed_errors; /* receiver missed packet */ + + /* detailed tx errors */ + unsigned long tx_ok; + unsigned long tx_collisions; + unsigned long tx_bid_errors; + unsigned long tx_wait_for_rdy4tx; + unsigned long tx_rdy4tx; + unsigned long tx_underrun_errors; + unsigned long tx_dropped; + unsigned long tx_resends; + + /* interrupt watch dog */ + unsigned long int_swint_req; + unsigned long int_swint_res; + unsigned long int_lockup; + + unsigned long interrupts; + +} eth_statistics; + +/* + * CS8900 device structure + */ + +typedef struct +{ + /* + * Device number. + */ + + int dev; + + /* + * Memory base addresses. Making mem_base 0 forces the + * driver to perform only I/O space accesses. + */ + + unsigned long io_base; + unsigned long mem_base; + + /* + * The IRQ level as defined in the datasheet for the CS8900. + * + * ISA BUS Pin Value + * IRQ10 INTRQ0 0 + * IRQ11 INTRQ1 1 + * IRQ12 INTRQ2 2 + * IRQ5 INTRQ3 3 + */ + + int irq_level; + + /* + * The MAC address. + */ + + unsigned char mac_address[6]; + + /* + * The bsdnet information structure. + */ + + struct arpcom arpcom; + + /* + * Driver state and resources. + */ + + int accept_bcast; + int tx_active; + + rtems_id rx_task; + rtems_id tx_task; + + /* + * The queues. FIXME : these should be changed to be mbuf lists. + */ + + struct mbuf *rx_ready_head; + struct mbuf *rx_ready_tail; + int rx_ready_len; + + struct mbuf *rx_loaded_head; + struct mbuf *rx_loaded_tail; + int rx_loaded_len; + + /* + * Number of mbufs queued for the interrupt handler to + * loop reading. + */ + + int rx_queue_size; + +#if CS8900_TRACE + unsigned short trace_key[CS8900_TRACE_SIZE]; + unsigned long trace_var[CS8900_TRACE_SIZE]; + unsigned long trace_time[CS8900_TRACE_SIZE]; + int trace_in; +#endif + + /** + * Standard(!) ethernet statistics + */ + + eth_statistics eth_stats; + +} cs8900_device; + +/* + * Link active returns the state of the PHY. + * + * @param cs Pointer to the device structure. + */ + +int cs8900_link_active (cs8900_device *cs); + +/** + * The RTEMS network stack driver attach function that is loaded into the + * the rtems_bsdnet_ifconfig struct. The network stack will call this + * function when attaching the driver. The BSP must load the 'drv_ctrl' + * field of the structure before calling the 'rtems_bsdnet_attach' + * function. + * + * @param config The RTEMS BSD config structure. + * + * @param attaching True is the stack is attaching the interface. + * + * @retval int Set to 1 if the device has attached. + */ + +int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, + int attaching); + +/** + * The BSP specific interrupt wrapper calls this function when a device + * interrupt occurs. + * + * @param v The RTEMS vector number that generated the interrupt. + * + * @param cs Pointer to the device structure passed to the interrupt + * catch function provided by the BSP. + * + * @retval rtems_isr The standard ISR return type. + */ + +rtems_isr cs8900_interrupt (rtems_vector_number v, void *cs); + +/** + * Get the MAC address for the interface. + * + * @param cs Pointer to the device structure. + * + * @param mac_address Pointer to the memory to load the MAC address. This + * is a 6 byte buffer so do not exceeed the bounds. + */ + +void cs8900_get_mac_addr (cs8900_device *cs, unsigned char *mac_address); + +/** + * Catch the device interrupt. When the interrupt is called call the + * function 'cs8900_interrupt'. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + */ + +void cs8900_attach_interrupt (cs8900_device *cs); + +/** + * Detach the device interrupt. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + */ + +void cs8900_detach_interrupt (cs8900_device *cs); + +/** + * Write to an IO space register. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param reg Register offset from the IO base. + * + * @param data The data to be written to the register. + */ + +void cs8900_io_set_reg (cs8900_device *cs, + unsigned short reg, unsigned short data); + +/** + * Read an IO space register. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param reg Register offset from the IO base. + * + * @retval unsigned short The register data. + */ + +unsigned short cs8900_io_get_reg (cs8900_device *cs, unsigned short reg); + +/** + * Write to a memory space register. Will only be called is the mem_base + * field of the 'cs' struct is not 0. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param reg Register offset from the memory base. + * + * @param data The data to be written to the register. + */ + +void cs8900_mem_set_reg (cs8900_device *cs, + unsigned long reg, unsigned short data); + +/** + * Read a memory space register. Will only be called is the mem_base + * field of the 'cs' struct is not 0. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param reg Register offset from the IO base. + * + * @retval unsigned short The register data. + */ + +unsigned short cs8900_mem_get_reg (cs8900_device *cs, unsigned long reg); + +/** + * Write a block of data to the interface. The BSP codes if this is an IO or + * memory space write. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param len The length of data to write. + * + * @param data Pointer to the data to be written. + */ + +void cs8900_put_data_block (cs8900_device *cs, int len, unsigned char *data); + +/** + * Read a block of data from the interface. The BSP codes if this is an IO or + * memory space write. The read must not be longer than the MTU size. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param data Pointer to the buffer where the data is to be written. + * + * @retval unsigned short The number of bytes read from the device. + */ + +unsigned short cs8900_get_data_block (cs8900_device *cs, unsigned char *data); + +/** + * Load a mbuf chain to the device ready for tranmission. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param m Pointer to the head of an mbuf chain. + */ + +void cs8900_tx_load (cs8900_device *cs, struct mbuf *m); + +#endif diff --git a/bsps/include/libchip/disp_hcms29xx.h b/bsps/include/libchip/disp_hcms29xx.h new file mode 100644 index 0000000000..84b74b6910 --- /dev/null +++ b/bsps/include/libchip/disp_hcms29xx.h @@ -0,0 +1,156 @@ +/*===============================================================*\ +| Project: display driver for HCMS29xx | ++-----------------------------------------------------------------+ +| File: disp_hcms29xx.h | ++-----------------------------------------------------------------+ +| Copyright (c) 2008 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| http://www.rtems.org/license/LICENSE. | ++-----------------------------------------------------------------+ +| this file declares the SPI based driver for a HCMS29xx 4 digit | +| alphanumeric LED display | +\*===============================================================*/ + +#ifndef _DISP_HCMS29XX_H +#define _DISP_HCMS29XX_H +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif +#define DISP_HCMS29XX_TEXT_CNT (128) + + typedef struct { + rtems_device_minor_number minor; /* minor device number */ + /* + * in the disp_buffer, the string to be displayed is placed + */ + char disp_buffer[DISP_HCMS29XX_TEXT_CNT]; + int disp_buf_cnt; /* number of valid chars in disp_buffer */ + /* + * in the trns buffer the string is transfered to display task + */ + char trns_buffer[DISP_HCMS29XX_TEXT_CNT]; + /* + * in the dev_buffer, characters will be accumulated before display... + */ + char dev_buffer[DISP_HCMS29XX_TEXT_CNT]; + int dev_buf_cnt; /* number of valid chars in dev_buffer */ + + rtems_id trns_sema_id; /* ID of disp trns buffer sema */ + rtems_id task_id; /* ID of disp task */ + bool rotate; /* FLAG: display is upside down */ + } spi_disp_hcms29xx_param_t; + + typedef struct { + rtems_libi2c_drv_t libi2c_drv_entry; + spi_disp_hcms29xx_param_t disp_param; + } disp_hcms29xx_drv_t; + /* + * pass this descriptor pointer to rtems_libi2c_register_drv + */ + extern rtems_libi2c_drv_t *disp_hcms29xx_driver_descriptor; + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_device_driver disp_hcms29xx_dev_initialize + ( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| prepare the display device driver to accept write calls | +| register device with its name | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_device_driver disp_hcms29xx_dev_open +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| open the display device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_device_driver disp_hcms29xx_dev_write +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| write to display device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_device_driver disp_hcms29xx_dev_close +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| close the display device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +#define DISP_HCMS29XX_DRIVER { \ + disp_hcms29xx_dev_initialize, \ + disp_hcms29xx_dev_open, \ + NULL, \ + disp_hcms29xx_dev_write, \ + NULL, \ + disp_hcms29xx_dev_close} + + +#ifdef __cplusplus +} +#endif + +#endif /* _DISP_HCMS29XX_H */ diff --git a/bsps/include/libchip/ds1375-rtc.h b/bsps/include/libchip/ds1375-rtc.h new file mode 100644 index 0000000000..a5be96293f --- /dev/null +++ b/bsps/include/libchip/ds1375-rtc.h @@ -0,0 +1,99 @@ +#ifndef DS1375_I2C_RTC_H +#define DS1375_I2C_RTC_H + +/* Driver for the Maxim 1375 i2c RTC (TOD only; very simple...) */ + +/* + * Authorship + * ---------- + * This software was created by + * + * Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern rtc_fns rtc_ds1375_fns; + +bool +rtc_ds1375_device_probe( int minor ); + +uint32_t +rtc_ds1375_get_register( uintptr_t port, uint8_t reg ); + +void +rtc_ds1375_set_register( uintptr_t port, uint8_t reg, uint32_t value ); + +/* + * BSP must supply string constant argument 'i2cname' which matches + * the registered device name of the raw i2c device (created with mknod). + * E.g., "/dev/i2c.ds1375-raw" + * + * NOTE: The i2c bus driver must already be up and 'i2cname' already + * be available when this ENTRY is registered or initialized. + * + * If you want to allow applications to add the RTC driver to + * the configuration table then the i2c subsystem must be + * initialized by the BSP from the predriver_hook. + */ +#define DS1375_RTC_TBL_ENTRY(i2cname) \ +{ \ + sDeviceName: "/dev/rtc", \ + deviceType: RTC_CUSTOM, \ + pDeviceFns: &rtc_ds1375_fns, \ + deviceProbe: rtc_ds1375_device_probe, \ + ulCtrlPort1: (uintptr_t)(i2cname), \ + ulDataPort: 0, \ + getRegister: rtc_ds1375_get_register, \ + setRegister: rtc_ds1375_set_register, \ +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/libchip/greth.h b/bsps/include/libchip/greth.h new file mode 100644 index 0000000000..c6e000dbd3 --- /dev/null +++ b/bsps/include/libchip/greth.h @@ -0,0 +1,152 @@ +/* + * Gaisler Research ethernet MAC driver + * adapted from Opencores driver by Marko Isomaki + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + + +#ifndef _GR_ETH_ +#define _GR_ETH_ + + +/* Configuration Information */ + +typedef struct { + void *base_address; + rtems_vector_number vector; + uint32_t txd_count; + uint32_t rxd_count; +} greth_configuration_t; + +/* Ethernet configuration registers */ + +typedef struct _greth_regs { + volatile uint32_t ctrl; /* Ctrl Register */ + volatile uint32_t status; /* Status Register */ + volatile uint32_t mac_addr_msb; /* Bit 47-32 of MAC address */ + volatile uint32_t mac_addr_lsb; /* Bit 31-0 of MAC address */ + volatile uint32_t mdio_ctrl; /* MDIO control and status */ + volatile uint32_t txdesc; /* Transmit descriptor pointer */ + volatile uint32_t rxdesc; /* Receive descriptor pointer */ +} greth_regs; + +#define GRETH_TOTAL_BD 128 +#define GRETH_MAXBUF_LEN 1520 + +/* Tx BD */ +#define GRETH_TXD_ENABLE 0x0800 /* Tx BD Enable */ +#define GRETH_TXD_WRAP 0x1000 /* Tx BD Wrap (last BD) */ +#define GRETH_TXD_IRQ 0x2000 /* Tx BD IRQ Enable */ +#define GRETH_TXD_MORE 0x20000 /* Tx BD More (more descs for packet) */ +#define GRETH_TXD_IPCS 0x40000 /* Tx BD insert ip chksum */ +#define GRETH_TXD_TCPCS 0x80000 /* Tx BD insert tcp chksum */ +#define GRETH_TXD_UDPCS 0x100000 /* Tx BD insert udp chksum */ + +#define GRETH_TXD_UNDERRUN 0x4000 /* Tx BD Underrun Status */ +#define GRETH_TXD_RETLIM 0x8000 /* Tx BD Retransmission Limit Status */ +#define GRETH_TXD_LATECOL 0x10000 /* Tx BD Late Collision */ + +#define GRETH_TXD_STATS (GRETH_TXD_UNDERRUN | \ + GRETH_TXD_RETLIM | \ + GRETH_TXD_LATECOL) + +#define GRETH_TXD_CS (GRETH_TXD_IPCS | \ + GRETH_TXD_TCPCS | \ + GRETH_TXD_UDPCS) + +/* Rx BD */ +#define GRETH_RXD_ENABLE 0x0800 /* Rx BD Enable */ +#define GRETH_RXD_WRAP 0x1000 /* Rx BD Wrap (last BD) */ +#define GRETH_RXD_IRQ 0x2000 /* Rx BD IRQ Enable */ + +#define GRETH_RXD_DRIBBLE 0x4000 /* Rx BD Dribble Nibble Status */ +#define GRETH_RXD_TOOLONG 0x8000 /* Rx BD Too Long Status */ +#define GRETH_RXD_CRCERR 0x10000 /* Rx BD CRC Error Status */ +#define GRETH_RXD_OVERRUN 0x20000 /* Rx BD Overrun Status */ +#define GRETH_RXD_LENERR 0x40000 /* Rx BD Length Error */ +#define GRETH_RXD_ID 0x40000 /* Rx BD IP Detected */ +#define GRETH_RXD_IR 0x40000 /* Rx BD IP Chksum Error */ +#define GRETH_RXD_UD 0x40000 /* Rx BD UDP Detected*/ +#define GRETH_RXD_UR 0x40000 /* Rx BD UDP Chksum Error */ +#define GRETH_RXD_TD 0x40000 /* Rx BD TCP Detected */ +#define GRETH_RXD_TR 0x40000 /* Rx BD TCP Chksum Error */ + + +#define GRETH_RXD_STATS (GRETH_RXD_OVERRUN | \ + GRETH_RXD_DRIBBLE | \ + GRETH_RXD_TOOLONG | \ + GRETH_RXD_CRCERR) + +/* CTRL Register */ +#define GRETH_CTRL_TXEN 0x00000001 /* Transmit Enable */ +#define GRETH_CTRL_RXEN 0x00000002 /* Receive Enable */ +#define GRETH_CTRL_TXIRQ 0x00000004 /* Transmit Enable */ +#define GRETH_CTRL_RXIRQ 0x00000008 /* Receive Enable */ +#define GRETH_CTRL_FULLD 0x00000010 /* Full Duplex */ +#define GRETH_CTRL_PRO 0x00000020 /* Promiscuous (receive all) */ +#define GRETH_CTRL_RST 0x00000040 /* Reset MAC */ + +/* Status Register */ +#define GRETH_STATUS_RXERR 0x00000001 /* Receive Error */ +#define GRETH_STATUS_TXERR 0x00000002 /* Transmit Error IRQ */ +#define GRETH_STATUS_RXIRQ 0x00000004 /* Receive Frame IRQ */ +#define GRETH_STATUS_TXIRQ 0x00000008 /* Transmit Error IRQ */ +#define GRETH_STATUS_RXAHBERR 0x00000010 /* Receiver AHB Error */ +#define GRETH_STATUS_TXAHBERR 0x00000020 /* Transmitter AHB Error */ + +/* MDIO Control */ +#define GRETH_MDIO_WRITE 0x00000001 /* MDIO Write */ +#define GRETH_MDIO_READ 0x00000002 /* MDIO Read */ +#define GRETH_MDIO_LINKFAIL 0x00000004 /* MDIO Link failed */ +#define GRETH_MDIO_BUSY 0x00000008 /* MDIO Link Busy */ +#define GRETH_MDIO_REGADR 0x000007C0 /* Register Address */ +#define GRETH_MDIO_PHYADR 0x0000F800 /* PHY address */ +#define GRETH_MDIO_DATA 0xFFFF0000 /* MDIO DATA */ + + +/* MII registers */ +#define GRETH_MII_EXTADV_1000FD 0x00000200 +#define GRETH_MII_EXTADV_1000HD 0x00000100 +#define GRETH_MII_EXTPRT_1000FD 0x00000800 +#define GRETH_MII_EXTPRT_1000HD 0x00000400 + +#define GRETH_MII_100T4 0x00000200 +#define GRETH_MII_100TXFD 0x00000100 +#define GRETH_MII_100TXHD 0x00000080 +#define GRETH_MII_10FD 0x00000040 +#define GRETH_MII_10HD 0x00000020 + + + +/* Attach routine */ + +int rtems_greth_driver_attach ( + struct rtems_bsdnet_ifconfig *config, + greth_configuration_t *chip +); + +/* PHY data */ +struct phy_device_info +{ + int vendor; + int device; + int rev; + + int adv; + int part; + + int extadv; + int extpart; +}; + +/* +#ifdef CPU_U32_FIX +void ipalign(struct mbuf *m); +#endif + +*/ +#endif + diff --git a/bsps/include/libchip/i2c-2b-eeprom.h b/bsps/include/libchip/i2c-2b-eeprom.h new file mode 100644 index 0000000000..93730d1e3b --- /dev/null +++ b/bsps/include/libchip/i2c-2b-eeprom.h @@ -0,0 +1,74 @@ +#ifndef I2C_2B_EEPROM_DRIVER_H +#define I2C_2B_EEPROM_DRIVER_H + +/* Trivial i2c driver for reading and writing "2-byte eeproms". + * On 'open' the file-pointer is reset to 0, subsequent + * read/write operations slurp/write data from there... + */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2005, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* pass one of these to rtems_libi2c_register_drv() */ + +/* These ops provide no write access */ +extern rtems_libi2c_drv_t *i2c_2b_eeprom_ro_driver_descriptor; + +/* Use these for writing and reading */ +extern rtems_libi2c_drv_t *i2c_2b_eeprom_driver_descriptor; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/libchip/i2c-ds1621.h b/bsps/include/libchip/i2c-ds1621.h new file mode 100644 index 0000000000..64df69f465 --- /dev/null +++ b/bsps/include/libchip/i2c-ds1621.h @@ -0,0 +1,81 @@ +#ifndef I2C_DS_1621_DRIVER_H +#define I2C_DS_1621_DRIVER_H + +/* Trivial i2c driver for the maxim DS1621 temperature sensor; + * just implements reading constant conversions with 8-bit + * resolution. + * Demonstrates the implementation of a i2c high-level driver. + */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2005, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#define DS1621_CMD_READ_TEMP 0xaa +#define DS1621_CMD_CSR_ACCESS 0xac +#define DS1621_CMD_START_CONV 0xee + +/* CSR bits */ +#define DS1621_CSR_DONE (1<<7) +#define DS1621_CSR_TEMP_HI (1<<6) /* T >= hi register */ +#define DS1621_CSR_TEMP_LO (1<<5) /* T <= lo register */ +#define DS1621_CSR_NVMEM_BSY (1<<4) /* non-volatile memory busy */ +#define DS1621_CSR_OUT_POL (1<<1) /* Thermostat output active polarity */ +#define DS1621_CSR_1SHOT (1<<0) /* Oneshot mode */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* for registration with libi2c */ +extern rtems_libi2c_drv_t *i2c_ds1621_driver_descriptor; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/libchip/i2c-sc620.h b/bsps/include/libchip/i2c-sc620.h new file mode 100644 index 0000000000..27721b91c3 --- /dev/null +++ b/bsps/include/libchip/i2c-sc620.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef I2C_SC620_H +#define I2C_SC620_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief I2C driver for SEMTECH SC620 octal LED driver. + * + * A write() must use two character buffer. The buffer[0] value specifies the + * register and the buffer[1] value specifies the register data. + * + * A read() must use a one character buffer. The buffer[0] value specifies the + * register on function entry. The buffer[0] value contains the register value + * after a successful operation. + */ +extern rtems_libi2c_drv_t i2c_sc620_driver; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* I2C_SC620_H */ diff --git a/bsps/include/libchip/i82586var.h b/bsps/include/libchip/i82586var.h new file mode 100644 index 0000000000..c9421a6732 --- /dev/null +++ b/bsps/include/libchip/i82586var.h @@ -0,0 +1,319 @@ +/* $NetBSD: i82586var.h,v 1.15 2001/01/22 22:28:45 bjh21 Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Paul Kranenburg and Charles M. Hannum. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*- + * Copyright (c) 1992, 1993, University of Vermont and State + * Agricultural College. + * Copyright (c) 1992, 1993, Garrett A. Wollman. + * + * Portions: + * Copyright (c) 1994, 1995, Rafal K. Boni + * Copyright (c) 1990, 1991, William F. Jolitz + * Copyright (c) 1990, The Regents of the University of California + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of Vermont + * and State Agricultural College and Garrett A. Wollman, by William F. + * Jolitz, and by the University of California, Berkeley, Lawrence + * Berkeley Laboratory, and its contributors. + * 4. Neither the names of the Universities nor the names of the authors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR AUTHORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Intel 82586 Ethernet chip + * Register, bit, and structure definitions. + * + * Original StarLAN driver written by Garrett Wollman with reference to the + * Clarkson Packet Driver code for this chip written by Russ Nelson and others. + * + * BPF support code taken from hpdev/if_le.c, supplied with tcpdump. + * + * 3C507 support is loosely based on code donated to NetBSD by Rafal Boni. + * + * Majorly cleaned up and 3C507 code merged by Charles Hannum. + * + * Converted to SUN ie driver by Charles D. Cranor, + * October 1994, January 1995. + * This sun version based on i386 version 1.30. + */ + +#ifndef I82586_DEBUG +#define I82586_DEBUG 0 +#endif + +/* Debug elements */ +#define IED_RINT 0x01 +#define IED_TINT 0x02 +#define IED_RNR 0x04 +#define IED_CNA 0x08 +#define IED_READFRAME 0x10 +#define IED_ENQ 0x20 +#define IED_XMIT 0x40 +#define IED_ALL 0x7f + +#define B_PER_F 3 /* recv buffers per frame */ +#define IE_RBUF_SIZE 256 /* size of each receive buffer; + MUST BE POWER OF TWO */ +#define NTXBUF 2 /* number of transmit commands */ +#define IE_TBUF_SIZE ETHER_MAX_LEN /* length of transmit buffer */ + +#define IE_MAXMCAST (IE_TBUF_SIZE/6)/* must fit in transmit buffer */ + + +#define INTR_ENTER 0 /* intr hook called on ISR entry */ +#define INTR_EXIT 1 /* intr hook called on ISR exit */ +#define INTR_LOOP 2 /* intr hook called on ISR loop */ +#define INTR_ACK 3 /* intr hook called on ie_ack */ + +#define CHIP_PROBE 0 /* reset called from chip probe */ +#define CARD_RESET 1 /* reset called from card reset */ + +#if I82586_DEBUG +#define I82586_INTS_REQ 0 +#define I82586_INTS_IN 1 +#define I82586_INTS_LOOPS 2 +#define I82586_INTS_OUT 3 +#define I82586_RX_INT 4 +#define I82586_RX_DROP 5 +#define I82586_RX_ERR 6 +#define I82586_RX_OK 7 +#define I82586_RX_START 8 +#define I82586_START_TX 9 +#define I82586_TX_START 10 +#define I82586_TX_INT 11 +#define I82586_TX_REQ 12 +#define I82586_TX_EVT 13 +#define I82586_TX_EMIT 14 +#define I82586_TX_BAD 15 +#define I82586_TX_ACTIVE 16 +#define I82586_TRACE_CNT 17 + +#define I82586_TRACE_FLOW (10000) +#endif + +/* + * Ethernet status, per interface. + * + * The chip uses two types of pointers: 16 bit and 24 bit + * 24 bit pointers cover the board's memory. + * 16 bit pointers are offsets from the ISCP's `ie_base' + * + * The board's memory is represented by the bus handle `bh'. The MI + * i82586 driver deals exclusively with offsets relative to the + * board memory bus handle. The `ie_softc' fields below that are marked + * `MD' are in the domain of the front-end driver; they opaque to the + * MI driver part. + * + * The front-end is required to manage the SCP and ISCP structures. i.e. + * allocate room for them on the board's memory, and arrange to point the + * chip at the SCB stucture, the offset of which is passed to the MI + * driver in `sc_scb'. + * + * The following functions provide the glue necessary to deal with + * host and bus idiosyncracies: + * + * hwreset - board reset + * hwinit - board initialization + * chan_attn - get chip to look at prepared commands + * intrhook - board dependent interrupt processing + * + * All of the following shared-memory access function use an offset + * relative to the bus handle to indicate the shared memory location. + * The bus_{read/write}N function take or return offset into the + * shared memory in the host's byte-order. + * + * memcopyin - copy device memory: board to KVA + * memcopyout - copy device memory: KVA to board + * bus_read16 - read a 16-bit i82586 pointer + `offset' argument will be 16-bit aligned + * bus_write16 - write a 16-bit i82586 pointer + `offset' argument will be 16-bit aligned + * bus_write24 - write a 24-bit i82586 pointer + `offset' argument will be 32-bit aligned + * bus_barrier - perform a bus barrier operation, forcing + all outstanding reads/writes to complete + * + */ + +struct ie_softc { + struct arpcom arpcom; + + /* + * For RTEMS we run the tx and rx handlers under a task due to the + * network semaphore stuff. + */ + + rtems_id intr_task; + rtems_id tx_task; + + void *sc_iobase; /* (MD) KVA of base of 24 bit addr space */ + void *sc_maddr; /* (MD) KVA of base of chip's RAM + (16bit addr space) */ + u_int sc_msize; /* (MD) how much RAM we have/use */ + + /* Bus glue */ + void (*hwreset) (struct ie_softc *, int); + void (*hwinit) (struct ie_softc *); + void (*chan_attn) (struct ie_softc *, int); + int (*intrhook) (struct ie_softc *, int where); + + void (*memcopyin) (struct ie_softc *, void *, int, size_t); + void (*memcopyout) (struct ie_softc *, const void *, + int, size_t); + u_int16_t (*ie_bus_read16) (struct ie_softc *, int offset); + void (*ie_bus_write16) (struct ie_softc *, int offset, + u_int16_t value); + void (*ie_bus_write24) (struct ie_softc *, int offset, + int addr); + void (*ie_bus_barrier) (struct ie_softc *, int offset, + int length, int flags); + + /* Media management */ + int (*sc_mediachange) (struct ie_softc *); + /* card dependent media change */ + void (*sc_mediastatus) (struct ie_softc *, struct ifmediareq *); + /* card dependent media status */ + + /* + * Offsets (relative to bus handle) of the i82586 SYSTEM structures. + */ + int scp; /* Offset to the SCP (set by front-end) */ + int iscp; /* Offset to the ISCP (set by front-end) */ + int scb; /* Offset to SCB (set by front-end) */ + + /* + * Offset and size of a block of board memory where the buffers + * are to be allocated from (initialized by front-end). + */ + int buf_area; /* Start of descriptors and buffers */ + int buf_area_sz; /* Size of above */ + + /* + * The buffers & descriptors (recv and xmit) + */ + int rframes; /* Offset to `nrxbuf' frame descriptors */ + int rbds; /* Offset to `nrxbuf' buffer descriptors */ + int rbufs; /* Offset to `nrxbuf' receive buffers */ +#define IE_RBUF_ADDR(sc, i) (sc->rbufs + ((i) * IE_RBUF_SIZE)) + int rfhead, rftail; + int rbhead, rbtail; + int nframes; /* number of frames in use */ + int nrxbuf; /* number of recv buffs in use */ + int rnr_expect; /* XXX - expect a RCVR not ready interrupt */ + + int nop_cmds; /* Offset to NTXBUF no-op commands */ + int xmit_cmds; /* Offset to NTXBUF transmit commands */ + int xbds; /* Offset to NTXBUF buffer descriptors */ + int xbufs; /* Offset to NTXBUF transmit buffers */ +#define IE_XBUF_ADDR(sc, i) (sc->xbufs + ((i) * IE_TBUF_SIZE)) + + int xchead, xctail; + int xmit_busy; + int do_xmitnopchain; /* Controls use of xmit NOP chains */ + int xmit_req; + + /* Multicast addresses */ + char *mcast_addrs; /* Current MC filter addresses */ + int mcast_addrs_size; /* Current size of MC buffer */ + int mcast_count; /* Current # of addrs in buffer */ + int want_mcsetup; /* run mcsetup at next opportunity */ + + int promisc; /* are we in promisc mode? */ + int async_cmd_inprogress; /* we didn't wait for 586 to accept + a command */ + +#if I82586_DEBUG +#define I82586_TRACE(s, e, d) \ +do { rtems_interrupt_level level; rtems_interrupt_disable (level); \ + (s)->trace_flow[(s)->trace_flow_in++] = (e); \ + (s)->trace_flow[(s)->trace_flow_in++] = (unsigned int)(d); \ + if ((s)->trace_flow_in >= I82586_TRACE_FLOW) { \ + (s)->trace_flow_in = 0; \ + (s)->trace_flow_wrap = 1; \ + } \ + rtems_interrupt_enable (level); \ + } while (0) + + int sc_debug; + unsigned int trace_flow[I82586_TRACE_FLOW * 2]; + unsigned int trace_flow_wrap; +#endif + unsigned int trace_flow_in; +}; + +/* Exported functions */ +rtems_isr i82586_intr (rtems_vector_number , void *); +int i82586_proberam (struct ie_softc *); +int i82586_attach (struct rtems_bsdnet_ifconfig *config, int attaching); + +/* Shortcut macros to optional (driver uses default if unspecified) callbacks */ +#define xIE_BUS_BARRIER(sc, offset, length, flags) \ +do { \ + if ((sc)->ie_bus_barrier) \ + ((sc)->ie_bus_barrier)((sc), (offset), (length), (flags));\ + else \ + bus_space_barrier((sc)->bt, (sc)->bh, (offset), (length), \ + (flags)); \ +} while (0) + +#define IE_BUS_BARRIER(sc, offset, length, flags) diff --git a/bsps/include/libchip/icm7170.h b/bsps/include/libchip/icm7170.h new file mode 100644 index 0000000000..6b95c905a4 --- /dev/null +++ b/bsps/include/libchip/icm7170.h @@ -0,0 +1,97 @@ +/* + * This file contains the definitions for the following real-time clocks: + * + * + Harris Semiconduction ICM7170 + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LIBCHIP_ICM7170_h +#define __LIBCHIP_ICM7170_h + +/* + * Register indices + */ + +#define ICM7170_CONTROL 0x11 + + +#define ICM7170_COUNTER_HUNDREDTHS 0x00 +#define ICM7170_HOUR 0x01 +#define ICM7170_MINUTE 0x02 +#define ICM7170_SECOND 0x03 +#define ICM7170_MONTH 0x04 +#define ICM7170_DATE 0x05 +#define ICM7170_YEAR 0x06 +#define ICM7170_DAY_OF_WEEK 0x07 + +/* + * Configuration information in the parameters field + */ + +#define ICM7170_AT_32_KHZ 0x00 +#define ICM7170_AT_1_MHZ 0x01 +#define ICM7170_AT_2_MHZ 0x02 +#define ICM7170_AT_4_MHZ 0x03 + +/* + * Driver function table + */ + +extern rtc_fns icm7170_fns; + +/* + * Default register access routines + */ + +uint32_t icm7170_get_register( /* registers are at 1 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void icm7170_set_register( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +uint32_t icm7170_get_register_2( /* registers are at 2 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void icm7170_set_register_2( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +uint32_t icm7170_get_register_4( /* registers are at 4 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void icm7170_set_register_4( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +uint32_t icm7170_get_register_8( /* registers are at 8 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void icm7170_set_register_8( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +#endif +/* end of include file */ diff --git a/bsps/include/libchip/ide_ctrl.h b/bsps/include/libchip/ide_ctrl.h new file mode 100644 index 0000000000..de32e4bed9 --- /dev/null +++ b/bsps/include/libchip/ide_ctrl.h @@ -0,0 +1,35 @@ +/* + * ide_ctrl.h + * + * This file describes the IDE controller driver for all boards. + * + * Copyright (C) 2002 OKTET Ltd., St.-Petersburg, Russia + * Author: Eugeny S. Mints + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __IDE_CTRL_H__ +#define __IDE_CTRL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +rtems_device_driver ide_controller_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *args); + + +#define IDE_CONTROLLER_DRIVER_TABLE_ENTRY \ + {ide_controller_initialize, NULL, NULL, NULL, NULL, NULL} + + +#ifdef __cplusplus +} +#endif + + +#endif /* __IDE_CTRL_H__ */ diff --git a/bsps/include/libchip/ide_ctrl_cfg.h b/bsps/include/libchip/ide_ctrl_cfg.h new file mode 100644 index 0000000000..3339a28d2b --- /dev/null +++ b/bsps/include/libchip/ide_ctrl_cfg.h @@ -0,0 +1,123 @@ +/* + * ide_ctrl_cfg.h + * + * LibChip library IDE controller header file - structures used for + * configuration and plugin interface definition. + * + * Copyright (C) 2002 OKTET Ltd., St.-Petersburg, Russia + * Author: Eugeny S. Mints + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __IDE_CTRL_CFG_H__ +#define __IDE_CTRL_CFG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Avaible drivers for IDE controllers + */ +typedef enum { + IDE_STD, + IDE_CUSTOM /* BSP specific driver */ +} ide_ctrl_devs_t; + +/* ATA modes: bit masks used in ctrl_config_io_speed call */ +#define ATA_MODES_PIO3 0x001 +#define ATA_MODES_PIO4 0x002 + +#define ATA_MODES_PIO 0x003 + +#define ATA_MODES_DMA0 0x004 +#define ATA_MODES_DMA1 0x008 +#define ATA_MODES_DMA2 0x010 + +#define ATA_MODES_UDMA0 0x020 +#define ATA_MODES_UDMA1 0x040 +#define ATA_MODES_UDMA2 0x080 +#define ATA_MODES_UDMA3 0x100 +#define ATA_MODES_UDMA4 0x200 +#define ATA_MODES_UDMA5 0x400 + +#define ATA_MODES_UDMA 0x7e0 +#define ATA_MODES_DMA 0x7fc + + +/* + * Each driver for a particular controller have to provide following + * functions in such a structure. The only field which should not be NULL + * is contInit. + */ +typedef struct ide_ctrl_fns_s { + bool (*ctrl_probe)(int minor); /* probe routine */ + void (*ctrl_initialize)(int minor); + int (*ctrl_control)(int minor, uint32_t command, + void *arg); + /* + * Functions which allow read/write registers of a particular controller. + * (these functions may be used from ide_controller_read_register, + * ide_controller_write_register) + */ + void (*ctrl_reg_read)(int minor, int regist, uint16_t *value); + void (*ctrl_reg_write)(int minor, int regist, uint16_t value); + + /* + * The function allows to escape overhead for read/write register + * functions calls + */ + void (*ctrl_read_block)(int minor, uint32_t block_size, + rtems_blkdev_sg_buffer *bufs, uint32_t *cbuf, + uint32_t *pos); + void (*ctrl_write_block)(int minor, uint32_t block_size, + rtems_blkdev_sg_buffer *bufs, uint32_t *cbuf, + uint32_t *pos); + + rtems_status_code (*ctrl_config_io_speed)(int minor, + uint16_t modes_available); +} ide_ctrl_fns_t; + +/* + * IDE Controller configuration. Table of such configurations is provided + * by BSP + */ +typedef struct ide_controller_bsp_table_s { + char *name; /* device name */ + ide_ctrl_devs_t type; /* chip type */ + ide_ctrl_fns_t *fns; /* pointer to the set of driver routines */ + bool (*probe)(int minor); /* general probe routine */ + uint8_t status; /* initialized/non initialized. Should be set + * to zero by static initialization + */ + uint32_t port1; /* port number for the port of the device */ + bool int_driven; /* interrupt/poll driven */ + rtems_vector_number int_vec; /* the interrupt vector of the device */ + void *params; /* contains either device specific data or a + * pointer to s device specific information + * table + */ +} ide_controller_bsp_table_t; + +/* IDE controllers Table */ +extern ide_controller_bsp_table_t IDE_Controller_Table[]; + +/* Number of rows in IDE_Controller_Table */ +extern unsigned long IDE_Controller_Count; + + +#define IDE_CTRL_MAX_MINOR_NUMBER 4 + +#define IDE_CTRL_NON_INITIALIZED 0 +#define IDE_CTRL_INITIALIZED 1 + +#ifdef __cplusplus +} +#endif + + +#endif /* __IDE_CTRL_CFG_H__ */ diff --git a/bsps/include/libchip/ide_ctrl_io.h b/bsps/include/libchip/ide_ctrl_io.h new file mode 100644 index 0000000000..9534b0e88f --- /dev/null +++ b/bsps/include/libchip/ide_ctrl_io.h @@ -0,0 +1,186 @@ +/* + * ide_ctrl_io.h + * + * LibChip library IDE controller header file - IO operations defined for + * IDE controllers. + * + * Copyright (C) 2002 OKTET Ltd., St.-Petersburg, Russia + * Author: Eugeny S. Mints + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __IDE_CTRL_IO_H__ +#define __IDE_CTRL_IO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* Command Block Registers */ +#define IDE_REGISTER_DATA 0 +#define IDE_REGISTER_ERROR 1 +#define IDE_REGISTER_FEATURES IDE_REGISTER_ERROR +#define IDE_REGISTER_SECTOR_COUNT 2 +#define IDE_REGISTER_SECTOR_NUMBER 3 +#define IDE_REGISTER_LBA0 IDE_REGISTER_SECTOR_NUMBER +#define IDE_REGISTER_CYLINDER_LOW 4 +#define IDE_REGISTER_LBA1 IDE_REGISTER_CYLINDER_LOW +#define IDE_REGISTER_CYLINDER_HIGH 5 +#define IDE_REGISTER_LBA2 IDE_REGISTER_CYLINDER_HIGH +#define IDE_REGISTER_DEVICE_HEAD 6 +#define IDE_REGISTER_LBA3 IDE_REGISTER_DEVICE_HEAD +#define IDE_REGISTER_STATUS 7 +#define IDE_REGISTER_COMMAND IDE_REGISTER_STATUS + +/* Control Block Registers */ +#define IDE_REGISTER_ALTERNATE_STATUS 6 +#define IDE_REGISTER_DEVICE_CONTROL IDE_REGISTER_ALTERNATE_STATUS + +/* offsets used to access registers */ +#define IDE_REGISTER_DEVICE_CONTROL_OFFSET 8 +#define IDE_REGISTER_ALTERNATE_STATUS_OFFSET IDE_REGISTER_DEVICE_CONTROL_OFFSET +#define IDE_REGISTER_DATA_BYTE 9 +#define IDE_REGISTER_DATA_WORD 10 + +/* + * Registers bits + */ +#define IDE_REGISTER_STATUS_BSY 0x80 /* Busy bit */ +#define IDE_REGISTER_STATUS_DRDY 0x40 /* Device ready */ +#define IDE_REGISTER_STATUS_DF 0x20 /* Device fault */ +#define IDE_REGISTER_STATUS_DSC 0x10 /* Device seek complete-- */ + /* obsolete */ +#define IDE_REGISTER_STATUS_DRQ 0x08 /* Data request */ +#define IDE_REGISTER_STATUS_CORR 0x04 /* Corrected data-- */ + /* vendor specific--obsolete */ +#define IDE_REGISTER_STATUS_IDX 0x02 /* Index-- */ + /* vendor specific--obsolete */ +#define IDE_REGISTER_STATUS_ERR 0x01 /* Error */ + +#define IDE_REGISTER_DEVICE_CONTROL_SRST 0x04 /* Host software reset bit */ +#define IDE_REGISTER_DEVICE_CONTROL_nIEN 0x02 /* Negated interrupt enable */ + +#define IDE_REGISTER_DEVICE_HEAD_L 0x40 /* LBA mode bit */ +#define IDE_REGISTER_DEVICE_HEAD_DEV 0x10 /* Device0/Device1 bit */ +#define IDE_REGISTER_DEVICE_HEAD_DEV_POS 4 /* Dev0/Dev1 bit position */ +#define IDE_REGISTER_DEVICE_HEAD_HS 0x0f /* Head/LBA24_27 bits */ +#define IDE_REGISTER_LBA3_L 0x40 +#define IDE_REGISTER_LBA3_DEV 0x10 +#define IDE_REGISTER_LBA3_LBA 0x0f + +#define IDE_REGISTER_ERROR_ICRC (1 << 7) /* Interface CRC error on */ + /* UDMA data transfer */ +#define IDE_REGISTER_ERROR_UNC (1 << 6) /* Uncorrectable data error */ +#if CCJ_COULD_NOT_FIND_THIS_ERROR +#define IDE_REGISTER_ERROR_WP (1 << 6) /* Write protect */ +#endif +#define IDE_REGISTER_ERROR_MC (1 << 5) /* Media changed */ +#define IDE_REGISTER_ERROR_IDNF (1 << 4) /* Sector ID not found */ +#define IDE_REGISTER_ERROR_MCR (1 << 3) /* Media change requested */ + /* obsolette */ +#define IDE_REGISTER_ERROR_ABRT (1 << 2) /* Aborted command */ +#define IDE_REGISTER_ERROR_NM (1 << 1) /* No media, End of Media. */ +#define IDE_REGISTER_ERROR_AMNF (1 << 0) /* Address mark not found */ + /* --obsolette in ATA-4 */ +#define IDE_REGISTER_ERROR_MED (1 << 0) /* Media error is detected */ + +/* + * ide_controller_read_data_block -- + * Read data block via controller's data register + * + * PARAMETERS: + * minor - minor number of controller + * block_size - number of bytes to read + * bufs - set of buffers to store data + * cbuf - number of current buffer from the set + * pos - position inside current buffer 'cbuf' + * + * RETURNS: + * NONE + */ +void +ide_controller_read_data_block(rtems_device_minor_number minor, + uint32_t block_size, + rtems_blkdev_sg_buffer *bufs, + uint32_t *cbuf, + uint32_t *pos); + +/* + * ide_controller_write_data_block -- + * Write data block via controller's data register + * + * PARAMETERS: + * minor - minor number of controller + * block_size - number of bytes to write + * bufs - set of buffers which store data + * cbuf - number of current buffer from the set + * pos - position inside current buffer 'cbuf' + * + * RETURNS: + * NONE + */ +void +ide_controller_write_data_block(rtems_device_minor_number minor, + uint32_t block_size, + rtems_blkdev_sg_buffer *bufs, + uint32_t *cbuf, + uint32_t *pos); + +/* + * ide_controller_read_register -- + * Read controller's register + * + * PARAMETERS: + * minor - minor number of controller + * reg - register to read + * value - placeholder for result + * + * RETURNS + * NONE + */ +void +ide_controller_read_register(rtems_device_minor_number minor, + int reg, + uint16_t *value); + +/* + * ide_controller_write_register -- + * Write controller's register + * + * PARAMETERS: + * minor - minor number of controller + * reg - register to write + * value - value to write + * + * RETURNS: + * NONE + */ +void +ide_controller_write_register(rtems_device_minor_number minor, + int reg, uint16_t value); + +/* + * ide_controller_config_io_speed -- + * Set controller's speed of IO operations + * + * PARAMETERS: + * minor - minor number of controller + * modes_available - speeds available + * + * RETURNS: + * RTEMS_SUCCESSFUL on success, or error code if + * error occured + */ +rtems_status_code +ide_controller_config_io_speed(int minor, uint16_t modes_available); + +#ifdef __cplusplus +} +#endif + + +#endif /* __IDE_CTRL_IO_H__ */ diff --git a/bsps/include/libchip/if_dcreg.h b/bsps/include/libchip/if_dcreg.h new file mode 100644 index 0000000000..07395c1884 --- /dev/null +++ b/bsps/include/libchip/if_dcreg.h @@ -0,0 +1,1120 @@ +/* + * Copyright (c) 1997, 1998, 1999 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/pci/if_dcreg.h,v 1.4.2.21 2003/02/12 22:19:34 mbr Exp $ + */ + +/* + * 21143 and clone common register definitions. + */ + +#define DC_BUSCTL 0x00 /* bus control */ +#define DC_TXSTART 0x08 /* tx start demand */ +#define DC_RXSTART 0x10 /* rx start demand */ +#define DC_RXADDR 0x18 /* rx descriptor list start addr */ +#define DC_TXADDR 0x20 /* tx descriptor list start addr */ +#define DC_ISR 0x28 /* interrupt status register */ +#define DC_NETCFG 0x30 /* network config register */ +#define DC_IMR 0x38 /* interrupt mask */ +#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ +#define DC_SIO 0x48 /* MII and ROM/EEPROM access */ +#define DC_ROM 0x50 /* ROM programming address */ +#define DC_TIMER 0x58 /* general timer */ +#define DC_10BTSTAT 0x60 /* SIA status */ +#define DC_SIARESET 0x68 /* SIA connectivity */ +#define DC_10BTCTRL 0x70 /* SIA transmit and receive */ +#define DC_WATCHDOG 0x78 /* SIA and general purpose port */ + +/* + * There are two general 'types' of MX chips that we need to be + * concerned with. One is the original 98713, which has its internal + * NWAY support controlled via the MDIO bits in the serial I/O + * register. The other is everything else (from the 98713A on up), + * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, + * just like the 21143. This type setting also governs which of the + * 'magic' numbers we write to CSR16. The PNIC II falls into the + * 98713A/98715/98715A/98725 category. + */ +#define DC_TYPE_98713 0x1 +#define DC_TYPE_98713A 0x2 +#define DC_TYPE_987x5 0x3 + +/* Other type of supported chips. */ +#define DC_TYPE_21143 0x4 /* Intel 21143 */ +#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ +#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ +#define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */ +#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ +#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ +#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ +#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */ + +#define DC_IS_MACRONIX(x) \ + (x->dc_type == DC_TYPE_98713 || \ + x->dc_type == DC_TYPE_98713A || \ + x->dc_type == DC_TYPE_987x5) + +#define DC_IS_ADMTEK(x) \ + (x->dc_type == DC_TYPE_AL981 || \ + x->dc_type == DC_TYPE_AN985) + +#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) +#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) +#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) +#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985) +#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) +#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) +#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) +#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT) + +/* MII/symbol mode port types */ +#define DC_PMODE_MII 0x1 +#define DC_PMODE_SYM 0x2 +#define DC_PMODE_SIA 0x3 + +/* + * Bus control bits. + */ +#define DC_BUSCTL_RESET 0x00000001 +#define DC_BUSCTL_ARBITRATION 0x00000002 +#define DC_BUSCTL_SKIPLEN 0x0000007C +#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 +#define DC_BUSCTL_BURSTLEN 0x00003F00 +#define DC_BUSCTL_CACHEALIGN 0x0000C000 +#define DC_BUSCTL_TXPOLL 0x000E0000 +#define DC_BUSCTL_DBO 0x00100000 +#define DC_BUSCTL_MRME 0x00200000 +#define DC_BUSCTL_MRLE 0x00800000 +#define DC_BUSCTL_MWIE 0x01000000 +#define DC_BUSCTL_ONNOW_ENB 0x04000000 + +#define DC_SKIPLEN_1LONG 0x00000004 +#define DC_SKIPLEN_2LONG 0x00000008 +#define DC_SKIPLEN_3LONG 0x00000010 +#define DC_SKIPLEN_4LONG 0x00000020 +#define DC_SKIPLEN_5LONG 0x00000040 + +#define DC_CACHEALIGN_NONE 0x00000000 +#define DC_CACHEALIGN_8LONG 0x00004000 +#define DC_CACHEALIGN_16LONG 0x00008000 +#define DC_CACHEALIGN_32LONG 0x0000C000 + +#define DC_BURSTLEN_USECA 0x00000000 +#define DC_BURSTLEN_1LONG 0x00000100 +#define DC_BURSTLEN_2LONG 0x00000200 +#define DC_BURSTLEN_4LONG 0x00000400 +#define DC_BURSTLEN_8LONG 0x00000800 +#define DC_BURSTLEN_16LONG 0x00001000 +#define DC_BURSTLEN_32LONG 0x00002000 + +#define DC_TXPOLL_OFF 0x00000000 +#define DC_TXPOLL_1 0x00020000 +#define DC_TXPOLL_2 0x00040000 +#define DC_TXPOLL_3 0x00060000 +#define DC_TXPOLL_4 0x00080000 +#define DC_TXPOLL_5 0x000A0000 +#define DC_TXPOLL_6 0x000C0000 +#define DC_TXPOLL_7 0x000E0000 + +/* + * Interrupt status bits. + */ +#define DC_ISR_TX_OK 0x00000001 +#define DC_ISR_TX_IDLE 0x00000002 +#define DC_ISR_TX_NOBUF 0x00000004 +#define DC_ISR_TX_JABBERTIMEO 0x00000008 +#define DC_ISR_LINKGOOD 0x00000010 +#define DC_ISR_TX_UNDERRUN 0x00000020 +#define DC_ISR_RX_OK 0x00000040 +#define DC_ISR_RX_NOBUF 0x00000080 +#define DC_ISR_RX_READ 0x00000100 +#define DC_ISR_RX_WATDOGTIMEO 0x00000200 +#define DC_ISR_TX_EARLY 0x00000400 +#define DC_ISR_TIMER_EXPIRED 0x00000800 +#define DC_ISR_LINKFAIL 0x00001000 +#define DC_ISR_BUS_ERR 0x00002000 +#define DC_ISR_RX_EARLY 0x00004000 +#define DC_ISR_ABNORMAL 0x00008000 +#define DC_ISR_NORMAL 0x00010000 +#define DC_ISR_RX_STATE 0x000E0000 +#define DC_ISR_TX_STATE 0x00700000 +#define DC_ISR_BUSERRTYPE 0x03800000 +#define DC_ISR_100MBPSLINK 0x08000000 +#define DC_ISR_MAGICKPACK 0x10000000 + +#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ +#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ +#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ +#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ +#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ +#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ +#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ +#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ + +#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ +#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ +#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ +#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ +#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ +#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ +#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ +#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ + +/* + * Network config bits. + */ +#define DC_NETCFG_RX_HASHPERF 0x00000001 +#define DC_NETCFG_RX_ON 0x00000002 +#define DC_NETCFG_RX_HASHONLY 0x00000004 +#define DC_NETCFG_RX_BADFRAMES 0x00000008 +#define DC_NETCFG_RX_INVFILT 0x00000010 +#define DC_NETCFG_BACKOFFCNT 0x00000020 +#define DC_NETCFG_RX_PROMISC 0x00000040 +#define DC_NETCFG_RX_ALLMULTI 0x00000080 +#define DC_NETCFG_FULLDUPLEX 0x00000200 +#define DC_NETCFG_LOOPBACK 0x00000C00 +#define DC_NETCFG_FORCECOLL 0x00001000 +#define DC_NETCFG_TX_ON 0x00002000 +#define DC_NETCFG_TX_THRESH 0x0000C000 +#define DC_NETCFG_TX_BACKOFF 0x00020000 +#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ +#define DC_NETCFG_HEARTBEAT 0x00080000 +#define DC_NETCFG_STORENFWD 0x00200000 +#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ +#define DC_NETCFG_PCS 0x00800000 +#define DC_NETCFG_SCRAMBLER 0x01000000 +#define DC_NETCFG_NO_RXCRC 0x02000000 +#define DC_NETCFG_RX_ALL 0x40000000 +#define DC_NETCFG_CAPEFFECT 0x80000000 + +#define DC_OPMODE_NORM 0x00000000 +#define DC_OPMODE_INTLOOP 0x00000400 +#define DC_OPMODE_EXTLOOP 0x00000800 + +#if 0 +#define DC_TXTHRESH_72BYTES 0x00000000 +#define DC_TXTHRESH_96BYTES 0x00004000 +#define DC_TXTHRESH_128BYTES 0x00008000 +#define DC_TXTHRESH_160BYTES 0x0000C000 +#endif + +#define DC_TXTHRESH_MIN 0x00000000 +#define DC_TXTHRESH_INC 0x00004000 +#define DC_TXTHRESH_MAX 0x0000C000 + + +/* + * Interrupt mask bits. + */ +#define DC_IMR_TX_OK 0x00000001 +#define DC_IMR_TX_IDLE 0x00000002 +#define DC_IMR_TX_NOBUF 0x00000004 +#define DC_IMR_TX_JABBERTIMEO 0x00000008 +#define DC_IMR_LINKGOOD 0x00000010 +#define DC_IMR_TX_UNDERRUN 0x00000020 +#define DC_IMR_RX_OK 0x00000040 +#define DC_IMR_RX_NOBUF 0x00000080 +#define DC_IMR_RX_READ 0x00000100 +#define DC_IMR_RX_WATDOGTIMEO 0x00000200 +#define DC_IMR_TX_EARLY 0x00000400 +#define DC_IMR_TIMER_EXPIRED 0x00000800 +#define DC_IMR_LINKFAIL 0x00001000 +#define DC_IMR_BUS_ERR 0x00002000 +#define DC_IMR_RX_EARLY 0x00004000 +#define DC_IMR_ABNORMAL 0x00008000 +#define DC_IMR_NORMAL 0x00010000 +#define DC_IMR_100MBPSLINK 0x08000000 +#define DC_IMR_MAGICKPACK 0x10000000 + +#define DC_INTRS \ + (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ + DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ + DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) +/* + * Serial I/O (EEPROM/ROM) bits. + */ +#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ +#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ +#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ +#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ +#define DC_SIO_ROMDATA4 0x00000010 +#define DC_SIO_ROMDATA5 0x00000020 +#define DC_SIO_ROMDATA6 0x00000040 +#define DC_SIO_ROMDATA7 0x00000080 +#define DC_SIO_EESEL 0x00000800 +#define DC_SIO_ROMSEL 0x00001000 +#define DC_SIO_ROMCTL_WRITE 0x00002000 +#define DC_SIO_ROMCTL_READ 0x00004000 +#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ +#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ +#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ +#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ + +#define DC_EECMD_WRITE 0x140 +#define DC_EECMD_READ 0x180 +#define DC_EECMD_ERASE 0x1c0 + +#define DC_EE_NODEADDR_OFFSET 0x70 +#define DC_EE_NODEADDR 10 + +/* + * General purpose timer register + */ +#define DC_TIMER_VALUE 0x0000FFFF +#define DC_TIMER_CONTINUOUS 0x00010000 + +/* + * 10baseT status register + */ +#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ +#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ +#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ +#define DC_TSTAT_AUTOPOLARITY 0x00000008 +#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ +#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ +#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ +#define DC_TSTAT_REMFAULT 0x00000800 +#define DC_TSTAT_ANEGSTAT 0x00007000 +#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ +#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ + +#define DC_ASTAT_DISABLE 0x00000000 +#define DC_ASTAT_TXDISABLE 0x00001000 +#define DC_ASTAT_ABDETECT 0x00002000 +#define DC_ASTAT_ACKDETECT 0x00003000 +#define DC_ASTAT_CMPACKDETECT 0x00004000 +#define DC_ASTAT_AUTONEGCMP 0x00005000 +#define DC_ASTAT_LINKCHECK 0x00006000 + +/* + * PHY reset register + */ +#define DC_SIA_RESET 0x00000001 +#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ + +/* + * 10baseT control register + */ +#define DC_TCTL_ENCODER_ENB 0x00000001 +#define DC_TCTL_LOOPBACK 0x00000002 +#define DC_TCTL_DRIVER_ENB 0x00000004 +#define DC_TCTL_LNKPULSE_ENB 0x00000008 +#define DC_TCTL_HALFDUPLEX 0x00000040 +#define DC_TCTL_AUTONEGENBL 0x00000080 +#define DC_TCTL_RX_SQUELCH 0x00000100 +#define DC_TCTL_COLL_SQUELCH 0x00000200 +#define DC_TCTL_COLL_DETECT 0x00000400 +#define DC_TCTL_SQE_ENB 0x00000800 +#define DC_TCTL_LINKTEST 0x00001000 +#define DC_TCTL_AUTOPOLARITY 0x00002000 +#define DC_TCTL_SET_POL_PLUS 0x00004000 +#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ +#define DC_TCTL_100BTXHALF 0x00010000 +#define DC_TCTL_100BTXFULL 0x00020000 +#define DC_TCTL_100BT4 0x00040000 + +/* + * Watchdog timer register + */ +#define DC_WDOG_JABBERDIS 0x00000001 +#define DC_WDOG_HOSTUNJAB 0x00000002 +#define DC_WDOG_JABBERCLK 0x00000004 +#define DC_WDOG_RXWDOGDIS 0x00000010 +#define DC_WDOG_RXWDOGCLK 0x00000020 +#define DC_WDOG_MUSTBEZERO 0x00000100 +#define DC_WDOG_AUIBNC 0x00100000 +#define DC_WDOG_ACTIVITY 0x00200000 +#define DC_WDOG_RX_MATCH 0x00400000 +#define DC_WDOG_LINK 0x00800000 +#define DC_WDOG_CTLWREN 0x08000000 + +/* + * Size of a setup frame. + */ +#define DC_SFRAME_LEN 192 + +/* + * 21x4x TX/RX list structure. + */ + +struct dc_desc { + u_int32_t dc_status; + u_int32_t dc_ctl; + u_int32_t dc_ptr1; + u_int32_t dc_ptr2; +}; + +#define dc_data dc_ptr1 +#define dc_next dc_ptr2 + +#define DC_RXSTAT_FIFOOFLOW 0x00000001 +#define DC_RXSTAT_CRCERR 0x00000002 +#define DC_RXSTAT_DRIBBLE 0x00000004 +#define DC_RXSTAT_MIIERE 0x00000008 +#define DC_RXSTAT_WATCHDOG 0x00000010 +#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ +#define DC_RXSTAT_COLLSEEN 0x00000040 +#define DC_RXSTAT_GIANT 0x00000080 +#define DC_RXSTAT_LASTFRAG 0x00000100 +#define DC_RXSTAT_FIRSTFRAG 0x00000200 +#define DC_RXSTAT_MULTICAST 0x00000400 +#define DC_RXSTAT_RUNT 0x00000800 +#define DC_RXSTAT_RXTYPE 0x00003000 +#define DC_RXSTAT_DE 0x00004000 +#define DC_RXSTAT_RXERR 0x00008000 +#define DC_RXSTAT_RXLEN 0x3FFF0000 +#define DC_RXSTAT_OWN 0x80000000 + +#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) +#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) + +#define DC_RXCTL_BUFLEN1 0x00000FFF +#define DC_RXCTL_BUFLEN2 0x00FFF000 +#define DC_RXCTL_RLINK 0x01000000 +#define DC_RXCTL_RLAST 0x02000000 + +#define DC_TXSTAT_DEFER 0x00000001 +#define DC_TXSTAT_UNDERRUN 0x00000002 +#define DC_TXSTAT_LINKFAIL 0x00000003 +#define DC_TXSTAT_COLLCNT 0x00000078 +#define DC_TXSTAT_SQE 0x00000080 +#define DC_TXSTAT_EXCESSCOLL 0x00000100 +#define DC_TXSTAT_LATECOLL 0x00000200 +#define DC_TXSTAT_NOCARRIER 0x00000400 +#define DC_TXSTAT_CARRLOST 0x00000800 +#define DC_TXSTAT_JABTIMEO 0x00004000 +#define DC_TXSTAT_ERRSUM 0x00008000 +#define DC_TXSTAT_OWN 0x80000000 + +#define DC_TXCTL_BUFLEN1 0x000007FF +#define DC_TXCTL_BUFLEN2 0x003FF800 +#define DC_TXCTL_FILTTYPE0 0x00400000 +#define DC_TXCTL_PAD 0x00800000 +#define DC_TXCTL_TLINK 0x01000000 +#define DC_TXCTL_TLAST 0x02000000 +#define DC_TXCTL_NOCRC 0x04000000 +#define DC_TXCTL_SETUP 0x08000000 +#define DC_TXCTL_FILTTYPE1 0x10000000 +#define DC_TXCTL_FIRSTFRAG 0x20000000 +#define DC_TXCTL_LASTFRAG 0x40000000 +#define DC_TXCTL_FINT 0x80000000 + +#define DC_FILTER_PERFECT 0x00000000 +#define DC_FILTER_HASHPERF 0x00400000 +#define DC_FILTER_INVERSE 0x10000000 +#define DC_FILTER_HASHONLY 0x10400000 + +#define DC_MAXFRAGS 16 +#ifdef DEVICE_POLLING +#define DC_RX_LIST_CNT 192 +#else +#define DC_RX_LIST_CNT 64 +#endif +#define DC_TX_LIST_CNT 256 +#define DC_MIN_FRAMELEN 60 +#define DC_RXLEN 1536 + +#define DC_INC(x, y) (x) = (x + 1) % y + +struct dc_list_data { + struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; + struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; +}; + +struct dc_chain_data { + struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; + struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; + u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)]; + u_int8_t dc_pad[DC_MIN_FRAMELEN]; + int dc_tx_prod; + int dc_tx_cons; + int dc_tx_cnt; + int dc_rx_prod; +}; + +struct dc_mediainfo { + int dc_media; + u_int8_t *dc_gp_ptr; + u_int8_t dc_gp_len; + u_int8_t *dc_reset_ptr; + u_int8_t dc_reset_len; + struct dc_mediainfo *dc_next; +}; + + +struct dc_type { + u_int16_t dc_vid; + u_int16_t dc_did; + char *dc_name; + int dc_devsig; + int dc_bus; + int dc_dev; + int dc_fun; +}; + +struct dc_mii_frame { + u_int8_t mii_stdelim; + u_int8_t mii_opcode; + u_int8_t mii_phyaddr; + u_int8_t mii_regaddr; + u_int8_t mii_turnaround; + u_int16_t mii_data; +}; + +/* + * MII constants + */ +#define DC_MII_STARTDELIM 0x01 +#define DC_MII_READOP 0x02 +#define DC_MII_WRITEOP 0x01 +#define DC_MII_TURNAROUND 0x02 + + +/* + * Registers specific to clone devices. + * This mainly relates to RX filter programming: not all 21x4x clones + * use the standard DEC filter programming mechanism. + */ + +/* + * ADMtek specific registers and constants for the AL981 and AN985. + * The AN985 doesn't use the magic PHY registers. + */ +#define DC_AL_CR 0x88 /* command register */ +#define DC_AL_PAR0 0xA4 /* station address */ +#define DC_AL_PAR1 0xA8 /* station address */ +#define DC_AL_MAR0 0xAC /* multicast hash filter */ +#define DC_AL_MAR1 0xB0 /* multicast hash filter */ +#define DC_AL_BMCR 0xB4 /* built in PHY control */ +#define DC_AL_BMSR 0xB8 /* built in PHY status */ +#define DC_AL_VENID 0xBC /* built in PHY ID0 */ +#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ +#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ +#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ +#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ + +#define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */ +#define DC_ADMTEK_PHYADDR 0x1 +#define DC_AL_EE_NODEADDR 4 +/* End of ADMtek specific registers */ + +/* + * ASIX specific registers. + */ +#define DC_AX_FILTIDX 0x68 /* RX filter index */ +#define DC_AX_FILTDATA 0x70 /* RX filter data */ + +/* + * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). + */ +#define DC_AX_NETCFG_RX_BROAD 0x00000100 + +/* + * RX Filter Index Register values + */ +#define DC_AX_FILTIDX_PAR0 0x00000000 +#define DC_AX_FILTIDX_PAR1 0x00000001 +#define DC_AX_FILTIDX_MAR0 0x00000002 +#define DC_AX_FILTIDX_MAR1 0x00000003 +/* End of ASIX specific registers */ + +/* + * Macronix specific registers. The Macronix chips have a special + * register for reading the NWAY status, which we don't use, plus + * a magic packet register, which we need to tweak a bit per the + * Macronix application notes. + */ +#define DC_MX_MAGICPACKET 0x80 +#define DC_MX_NWAYSTAT 0xA0 + +/* + * Magic packet register + */ +#define DC_MX_MPACK_DISABLE 0x00400000 + +/* + * NWAY status register. + */ +#define DC_MX_NWAY_10BTHALF 0x08000000 +#define DC_MX_NWAY_10BTFULL 0x10000000 +#define DC_MX_NWAY_100BTHALF 0x20000000 +#define DC_MX_NWAY_100BTFULL 0x40000000 +#define DC_MX_NWAY_100BT4 0x80000000 + +/* + * These are magic values that must be written into CSR16 + * (DC_MX_MAGICPACKET) in order to put the chip into proper + * operating mode. The magic numbers are documented in the + * Macronix 98715 application notes. + */ +#define DC_MX_MAGIC_98713 0x0F370000 +#define DC_MX_MAGIC_98713A 0x0B3C0000 +#define DC_MX_MAGIC_98715 0x0B3C0000 +#define DC_MX_MAGIC_98725 0x0B3C0000 +/* End of Macronix specific registers */ + +/* + * PNIC 82c168/82c169 specific registers. + * The PNIC has its own special NWAY support, which doesn't work, + * and shortcut ways of reading the EEPROM and MII bus. + */ +#define DC_PN_GPIO 0x60 /* general purpose pins control */ +#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ +#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ +#define DC_PN_MII 0xA0 /* MII access register */ +#define DC_PN_NWAY 0xB8 /* Internal NWAY register */ + +/* Serial I/O EEPROM register */ +#define DC_PN_SIOCTL_DATA 0x0000003F +#define DC_PN_SIOCTL_OPCODE 0x00000300 +#define DC_PN_SIOCTL_BUSY 0x80000000 + +#define DC_PN_EEOPCODE_ERASE 0x00000300 +#define DC_PN_EEOPCODE_READ 0x00000600 +#define DC_PN_EEOPCODE_WRITE 0x00000100 + +/* + * The first two general purpose pins control speed selection and + * 100Mbps loopback on the 82c168 chip. The control bits should always + * be set (to make the data pins outputs) and the speed selction and + * loopback bits set accordingly when changing media. Physically, this + * will set the state of a relay mounted on the card. + */ +#define DC_PN_GPIO_DATA0 0x000000001 +#define DC_PN_GPIO_DATA1 0x000000002 +#define DC_PN_GPIO_DATA2 0x000000004 +#define DC_PN_GPIO_DATA3 0x000000008 +#define DC_PN_GPIO_CTL0 0x000000010 +#define DC_PN_GPIO_CTL1 0x000000020 +#define DC_PN_GPIO_CTL2 0x000000040 +#define DC_PN_GPIO_CTL3 0x000000080 +#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ +#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ +#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 +#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 +#define DC_PN_GPIO_SETBIT(sc, r) \ + DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) +#define DC_PN_GPIO_CLRBIT(sc, r) \ + { \ + DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ + DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ + } + +/* shortcut MII access register */ +#define DC_PN_MII_DATA 0x0000FFFF +#define DC_PN_MII_RESERVER 0x00020000 +#define DC_PN_MII_REGADDR 0x007C0000 +#define DC_PN_MII_PHYADDR 0x0F800000 +#define DC_PN_MII_OPCODE 0x30000000 +#define DC_PN_MII_BUSY 0x80000000 + +#define DC_PN_MIIOPCODE_READ 0x60020000 +#define DC_PN_MIIOPCODE_WRITE 0x50020000 + +/* Internal NWAY bits */ +#define DC_PN_NWAY_RESET 0x00000001 /* reset */ +#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ +#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ +#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ +#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ +#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ +#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ +#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ +#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ +#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ +#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ +#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ +#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ +#define DC_PN_NWAY_CAP10HDX 0x00002000 +#define DC_PN_NWAY_CAP10FDX 0x00004000 +#define DC_PN_NWAY_CAP100FDX 0x00008000 +#define DC_PN_NWAY_CAP100HDX 0x00010000 +#define DC_PN_NWAY_CAP100T4 0x00020000 +#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ +#define DC_PN_NWAY_REMFAULT 0x04000000 +#define DC_PN_NWAY_LPAR10HDX 0x08000000 +#define DC_PN_NWAY_LPAR10FDX 0x10000000 +#define DC_PN_NWAY_LPAR100FDX 0x20000000 +#define DC_PN_NWAY_LPAR100HDX 0x40000000 +#define DC_PN_NWAY_LPAR100T4 0x80000000 + +/* End of PNIC specific registers */ + +/* + * CONEXANT specific registers. + */ + +#define DC_CONEXANT_PHYADDR 0x1 +#define DC_CONEXANT_EE_NODEADDR 0x19A + +/* End of CONEXANT specific registers */ + + +struct dc_softc { + struct arpcom arpcom; /* interface info */ + rtems_irq_connect_data irqInfo; + volatile u_int32_t membase; + rtems_id daemontid; +#if 0 + bus_space_handle_t dc_bhandle; /* bus space handle */ + bus_space_tag_t dc_btag; /* bus space tag */ + void *dc_intrhand; + struct resource *dc_irq; + struct resource *dc_res; +#endif + struct dc_type *dc_info; /* adapter info */ +/* device_t dc_miibus; */ + u_int8_t dc_unit; /* interface number */ + char *dc_name; + u_int8_t dc_type; + u_int8_t dc_pmode; + u_int8_t dc_link; + u_int8_t dc_cachesize; + int dc_romwidth; + int dc_pnic_rx_bug_save; + unsigned char *dc_pnic_rx_buf; + int dc_if_flags; + int dc_if_media; + u_int32_t dc_flags; + u_int32_t dc_txthresh; + u_int8_t *dc_srom; + struct dc_mediainfo *dc_mi; +/* + struct callout_handle dc_stat_ch; +*/ + struct dc_list_data *dc_ldata; + struct dc_chain_data dc_cdata; +#ifdef __alpha__ + int dc_srm_media; +#endif +#ifdef DEVICE_POLLING + int rxcycles; /* ... when polling */ +#endif + int suspended; /* 0 = normal 1 = suspended */ + + u_int32_t saved_maps[5]; /* pci data */ + u_int32_t saved_biosaddr; + u_int8_t saved_intline; + u_int8_t saved_cachelnsz; + u_int8_t saved_lattimer; +}; + +#define DC_TX_POLL 0x00000001 +#define DC_TX_COALESCE 0x00000002 +#define DC_TX_ADMTEK_WAR 0x00000004 +#define DC_TX_USE_TX_INTR 0x00000008 +#define DC_RX_FILTER_TULIP 0x00000010 +#define DC_TX_INTR_FIRSTFRAG 0x00000020 +#define DC_PNIC_RX_BUG_WAR 0x00000040 +#define DC_TX_FIXED_RING 0x00000080 +#define DC_TX_STORENFWD 0x00000100 +#define DC_REDUCED_MII_POLL 0x00000200 +#define DC_TX_INTR_ALWAYS 0x00000400 +#define DC_21143_NWAY 0x00000800 +#define DC_128BIT_HASH 0x00001000 +#define DC_64BIT_HASH 0x00002000 +#define DC_TULIP_LEDS 0x00004000 +#define DC_TX_ONE 0x00008000 + +/* + * register space access macros + */ +#define _readl_(addr) (*(volatile unsigned int *)((void *)(addr))) +#define _writel_(b, addr) (*(volatile unsigned int *)((void *)(addr)) = (b)) + +#define CSR_READ_4(sc, reg) _readl_(((sc->membase)+(reg))) +#define CSR_WRITE_4(sc, reg, val) _writel_(val, ((sc->membase)+(reg))) + + + + + + +#define DC_TIMEOUT 1000 +#define ETHER_ALIGN 2 + +/* + * General constants that are fun to know. + */ + +/* + * DEC PCI vendor ID + */ +#define DC_VENDORID_DEC 0x1011 + +/* + * DEC/Intel 21143 PCI device ID + */ +#define DC_DEVICEID_21143 0x0019 + +/* + * Macronix PCI vendor ID + */ +#define DC_VENDORID_MX 0x10D9 + +/* + * Macronix PMAC device IDs. + */ +#define DC_DEVICEID_98713 0x0512 +#define DC_DEVICEID_987x5 0x0531 +#define DC_DEVICEID_98727 0x0532 +#define DC_DEVICEID_98732 0x0532 + +/* Macronix PCI revision codes. */ +#define DC_REVISION_98713 0x00 +#define DC_REVISION_98713A 0x10 +#define DC_REVISION_98715 0x20 +#define DC_REVISION_98715AEC_C 0x25 +#define DC_REVISION_98725 0x30 + +/* + * Compex PCI vendor ID. + */ +#define DC_VENDORID_CP 0x11F6 + +/* + * Compex PMAC PCI device IDs. + */ +#define DC_DEVICEID_98713_CP 0x9881 + +/* + * Lite-On PNIC PCI vendor ID + */ +#define DC_VENDORID_LO 0x11AD + +/* + * 82c168/82c169 PNIC device IDs. Both chips have the same device + * ID but different revisions. Revision 0x10 is the 82c168, and + * 0x20 is the 82c169. + */ +#define DC_DEVICEID_82C168 0x0002 + +#define DC_REVISION_82C168 0x10 +#define DC_REVISION_82C169 0x20 + +/* + * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A + * with wake on lan/magic packet support. + */ +#define DC_DEVICEID_82C115 0xc115 + +/* + * Davicom vendor ID. + */ +#define DC_VENDORID_DAVICOM 0x1282 + +/* + * Davicom device IDs. + */ +#define DC_DEVICEID_DM9009 0x9009 +#define DC_DEVICEID_DM9100 0x9100 +#define DC_DEVICEID_DM9102 0x9102 + +/* + * The DM9102A has the same PCI device ID as the DM9102, + * but a higher revision code. + */ +#define DC_REVISION_DM9102 0x10 +#define DC_REVISION_DM9102A 0x30 + +/* + * ADMtek vendor ID. + */ +#define DC_VENDORID_ADMTEK 0x1317 + +/* + * ADMtek device IDs. + */ +#define DC_DEVICEID_AL981 0x0981 +#define DC_DEVICEID_AN985 0x0985 + +/* + * ASIX vendor ID. + */ +#define DC_VENDORID_ASIX 0x125B + +/* + * ASIX device IDs. + */ +#define DC_DEVICEID_AX88140A 0x1400 + +/* + * The ASIX AX88140 and ASIX AX88141 have the same vendor and + * device IDs but different revision values. + */ +#define DC_REVISION_88140 0x00 +#define DC_REVISION_88141 0x10 + +/* + * Accton vendor ID. + */ +#define DC_VENDORID_ACCTON 0x1113 + +/* + * Accton device IDs. + */ +#define DC_DEVICEID_EN1217 0x1217 +#define DC_DEVICEID_EN2242 0x1216 + +/* + * Conexant vendor ID. + */ +#define DC_VENDORID_CONEXANT 0x14f1 + +/* + * Conexant device IDs. + */ +#define DC_DEVICEID_RS7112 0x1803 + +/* + * PCI low memory base and low I/O base register, and + * other PCI registers. + */ + +#define DC_PCI_CFID 0x00 /* Id */ +#define DC_PCI_CFCS 0x04 /* Command and status */ +#define DC_PCI_CFRV 0x08 /* Revision */ +#define DC_PCI_CFLT 0x0C /* Latency timer */ +#define DC_PCI_CFBIO 0x10 /* Base I/O address */ +#define DC_PCI_CFBMA 0x14 /* Base memory address */ +#define DC_PCI_CCIS 0x28 /* Card info struct */ +#define DC_PCI_CSID 0x2C /* Subsystem ID */ +#define DC_PCI_CBER 0x30 /* Expansion ROM base address */ +#define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */ +#define DC_PCI_CFIT 0x3C /* Interrupt */ +#define DC_PCI_CFDD 0x40 /* Device and driver area */ +#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ +#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ +#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ +#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ +#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ +#define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */ +#define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */ + +/* PCI ID register */ +#define DC_CFID_VENDOR 0x0000FFFF +#define DC_CFID_DEVICE 0xFFFF0000 + +/* PCI command/status register */ +#define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */ +#define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */ +#define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */ +#define DC_CFCS_MWI_ENB 0x00000010 /* mem write and inval enable */ +#define DC_CFCS_PARITYERR_ENB 0x00000040 /* parity error enable */ +#define DC_CFCS_SYSERR_ENB 0x00000100 /* system error enable */ +#define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */ +#define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */ +#define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */ +#define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */ +#define DC_CFCS_TGTABRT 0x10000000 /* received target abort */ +#define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */ +#define DC_CFCS_SYSERR 0x40000000 /* asserted system error */ +#define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */ + +/* PCI revision register */ +#define DC_CFRV_STEPPING 0x0000000F +#define DC_CFRV_REVISION 0x000000F0 +#define DC_CFRV_SUBCLASS 0x00FF0000 +#define DC_CFRV_BASECLASS 0xFF000000 + +#define DC_21143_PB_REV 0x00000030 +#define DC_21143_TB_REV 0x00000030 +#define DC_21143_PC_REV 0x00000030 +#define DC_21143_TC_REV 0x00000030 +#define DC_21143_PD_REV 0x00000041 +#define DC_21143_TD_REV 0x00000041 + +/* PCI latency timer register */ +#define DC_CFLT_CACHELINESIZE 0x000000FF +#define DC_CFLT_LATENCYTIMER 0x0000FF00 + +/* PCI subsystem ID register */ +#define DC_CSID_VENDOR 0x0000FFFF +#define DC_CSID_DEVICE 0xFFFF0000 + +/* PCI cababilities pointer */ +#define DC_CCAP_OFFSET 0x000000FF + +/* PCI interrupt config register */ +#define DC_CFIT_INTLINE 0x000000FF +#define DC_CFIT_INTPIN 0x0000FF00 +#define DC_CFIT_MIN_GNT 0x00FF0000 +#define DC_CFIT_MAX_LAT 0xFF000000 + +/* PCI capability register */ +#define DC_CCID_CAPID 0x000000FF +#define DC_CCID_NEXTPTR 0x0000FF00 +#define DC_CCID_PM_VERS 0x00070000 +#define DC_CCID_PME_CLK 0x00080000 +#define DC_CCID_DVSPEC_INT 0x00200000 +#define DC_CCID_STATE_D1 0x02000000 +#define DC_CCID_STATE_D2 0x04000000 +#define DC_CCID_PME_D0 0x08000000 +#define DC_CCID_PME_D1 0x10000000 +#define DC_CCID_PME_D2 0x20000000 +#define DC_CCID_PME_D3HOT 0x40000000 +#define DC_CCID_PME_D3COLD 0x80000000 + +/* PCI power management control/status register */ +#define DC_CPMC_STATE 0x00000003 +#define DC_CPMC_PME_ENB 0x00000100 +#define DC_CPMC_PME_STS 0x00008000 + +#define DC_PSTATE_D0 0x0 +#define DC_PSTATE_D1 0x1 +#define DC_PSTATE_D2 0x2 +#define DC_PSTATE_D3 0x3 + +/* Device specific region */ +/* Configuration and driver area */ +#define DC_CFDD_DRVUSE 0x0000FFFF +#define DC_CFDD_SNOOZE_MODE 0x40000000 +#define DC_CFDD_SLEEP_MODE 0x80000000 + +/* Configuration wake-up command register */ +#define DC_CWUC_MUST_BE_ZERO 0x00000001 +#define DC_CWUC_SECUREON_ENB 0x00000002 +#define DC_CWUC_FORCE_WUL 0x00000004 +#define DC_CWUC_BNC_ABILITY 0x00000008 +#define DC_CWUC_AUI_ABILITY 0x00000010 +#define DC_CWUC_TP10_ABILITY 0x00000020 +#define DC_CWUC_MII_ABILITY 0x00000040 +#define DC_CWUC_SYM_ABILITY 0x00000080 +#define DC_CWUC_LOCK 0x00000100 + +/* + * SROM nonsense. + */ + +#define DC_IB_CTLRCNT 0x13 +#define DC_IB_LEAF0_CNUM 0x1A +#define DC_IB_LEAF0_OFFSET 0x1B + +struct dc_info_leaf { + u_int16_t dc_conntype; + u_int8_t dc_blkcnt; + u_int8_t dc_rsvd; + u_int16_t dc_infoblk; +}; + +#define DC_CTYPE_10BT 0x0000 +#define DC_CTYPE_10BT_NWAY 0x0100 +#define DC_CTYPE_10BT_FDX 0x0204 +#define DC_CTYPE_10B2 0x0001 +#define DC_CTYPE_10B5 0x0002 +#define DC_CTYPE_100BT 0x0003 +#define DC_CTYPE_100BT_FDX 0x0205 +#define DC_CTYPE_100T4 0x0006 +#define DC_CTYPE_100FX 0x0007 +#define DC_CTYPE_100FX_FDX 0x0208 +#define DC_CTYPE_MII_10BT 0x0009 +#define DC_CTYPE_MII_10BT_FDX 0x020A +#define DC_CTYPE_MII_100BT 0x000D +#define DC_CTYPE_MII_100BT_FDX 0x020E +#define DC_CTYPE_MII_100T4 0x000F +#define DC_CTYPE_MII_100FX 0x0010 +#define DC_CTYPE_MII_100FX_FDX 0x0211 +#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 +#define DC_CTYPE_PUP_AUTOSENSE 0x8800 +#define DC_CTYPE_NOMEDIA 0xFFFF + +#define DC_EBLOCK_SIA 0x0002 +#define DC_EBLOCK_MII 0x0003 +#define DC_EBLOCK_SYM 0x0004 +#define DC_EBLOCK_RESET 0x0005 +#define DC_EBLOCK_PHY_SHUTDOWN 0x0006 + +struct dc_leaf_hdr { + u_int16_t dc_mtype; + u_int8_t dc_mcnt; + u_int8_t dc_rsvd; +}; + +struct dc_eblock_hdr { + u_int8_t dc_len; + u_int8_t dc_type; +}; + +struct dc_eblock_sia { + struct dc_eblock_hdr dc_sia_hdr; + u_int8_t dc_sia_code; + u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ + u_int8_t dc_sia_gpio_ctl[2]; + u_int8_t dc_sia_gpio_dat[2]; +}; + +#define DC_SIA_CODE_10BT 0x00 +#define DC_SIA_CODE_10B2 0x01 +#define DC_SIA_CODE_10B5 0x02 +#define DC_SIA_CODE_10BT_FDX 0x04 +#define DC_SIA_CODE_EXT 0x40 + +/* + * Note that the first word in the gpr and reset + * sequences is always a control word. + */ +struct dc_eblock_mii { + struct dc_eblock_hdr dc_mii_hdr; + u_int8_t dc_mii_phynum; + u_int8_t dc_gpr_len; +/* u_int16_t dc_gpr_dat[n]; */ +/* u_int8_t dc_reset_len; */ +/* u_int16_t dc_reset_dat[n]; */ +/* There are other fields after these, but we don't + * care about them since they can be determined by looking + * at the PHY. + */ +}; + +struct dc_eblock_sym { + struct dc_eblock_hdr dc_sym_hdr; + u_int8_t dc_sym_code; + u_int8_t dc_sym_gpio_ctl[2]; + u_int8_t dc_sym_gpio_dat[2]; + u_int8_t dc_sym_cmd[2]; +}; + +#define DC_SYM_CODE_100BT 0x03 +#define DC_SYM_CODE_100BT_FDX 0x05 +#define DC_SYM_CODE_100T4 0x06 +#define DC_SYM_CODE_100FX 0x07 +#define DC_SYM_CODE_100FX_FDX 0x08 + +struct dc_eblock_reset { + struct dc_eblock_hdr dc_reset_hdr; + u_int8_t dc_reset_len; +/* u_int16_t dc_reset_dat[n]; */ +}; + +#ifdef __alpha__ +#undef vtophys +#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) +#endif diff --git a/bsps/include/libchip/if_fxpvar.h b/bsps/include/libchip/if_fxpvar.h new file mode 100644 index 0000000000..f29f52c080 --- /dev/null +++ b/bsps/include/libchip/if_fxpvar.h @@ -0,0 +1,203 @@ +/* + * Copyright (c) 1995, David Greenman + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/fxp/if_fxpvar.h,v 1.17.2.3 2001/06/08 20:36:58 jlemon Exp $ + */ + +/* + * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast + * Ethernet driver + */ + +/* + * Number of transmit control blocks. This determines the number + * of transmit buffers that can be chained in the CB list. + * This must be a power of two. + */ +#define FXP_NTXCB 128 + +/* + * Number of completed TX commands at which point an interrupt + * will be generated to garbage collect the attached buffers. + * Must be at least one less than FXP_NTXCB, and should be + * enough less so that the transmitter doesn't becomes idle + * during the buffer rundown (which would reduce performance). + */ +#define FXP_CXINT_THRESH 120 + +/* + * TxCB list index mask. This is used to do list wrap-around. + */ +#define FXP_TXCB_MASK (FXP_NTXCB - 1) + +/* + * Number of receive frame area buffers. These are large so chose + * wisely. + */ +#if 0 +#define FXP_NRFABUFS 64 +#else +#define FXP_NRFABUFS 16 +#endif +/* + * Maximum number of seconds that the receiver can be idle before we + * assume it's dead and attempt to reset it by reprogramming the + * multicast filter. This is part of a work-around for a bug in the + * NIC. See fxp_stats_update(). + */ +#define FXP_MAX_RX_IDLE 15 + +#if __FreeBSD_version < 500000 +#define FXP_LOCK(_sc) +#define FXP_UNLOCK(_sc) +#define mtx_init(a, b, c) +#define mtx_destroy(a) +struct mtx { int dummy; }; +#else +#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) +#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) +#endif + +#ifdef __alpha__ +#undef vtophys +#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va)) +#endif /* __alpha__ */ + +/* + * NOTE: Elements are ordered for optimal cacheline behavior, and NOT + * for functional grouping. + */ +struct fxp_softc { + struct arpcom arpcom; /* per-interface network data */ +#ifdef NOTUSED + struct resource *mem; /* resource descriptor for registers */ + int rtp; /* register resource type */ + int rgd; /* register descriptor in use */ + struct resource *irq; /* resource descriptor for interrupt */ +#endif + void *ih; /* interrupt handler cookie */ + struct mtx sc_mtx; +#ifdef NOTUSED /* change for RTEMS */ + bus_space_tag_t sc_st; /* bus space tag */ + bus_space_handle_t sc_sh; /* bus space handle */ +#else + unsigned char pci_bus; /* RTEMS PCI bus number */ + unsigned char pci_dev; /* RTEMS PCI slot/device number */ + unsigned char pci_fun; /* RTEMS PCI function number */ + bool pci_regs_are_io; /* RTEMS dev regs are I/O mapped */ + u_int32_t pci_regs_base; /* RTEMS i386 register base */ + rtems_id daemonTid; /* Task ID of deamon */ + rtems_vector_number irq_num; + +#endif + struct mbuf *rfa_headm; /* first mbuf in receive frame area */ + struct mbuf *rfa_tailm; /* last mbuf in receive frame area */ + struct fxp_cb_tx *cbl_first; /* first active TxCB in list */ + int tx_queued; /* # of active TxCB's */ + int need_mcsetup; /* multicast filter needs programming */ + struct fxp_cb_tx *cbl_last; /* last active TxCB in list */ + struct fxp_stats *fxp_stats; /* Pointer to interface stats */ + int rx_idle_secs; /* # of seconds RX has been idle */ + enum {fxp_timeout_stopped,fxp_timeout_running,fxp_timeout_stop_rq} + stat_ch; /* status of status updater */ + struct fxp_cb_tx *cbl_base; /* base of TxCB list */ + struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */ +#ifdef NOTUSED + struct ifmedia sc_media; /* media information */ + device_t miibus; + device_t dev; +#endif + int eeprom_size; /* size of serial EEPROM */ + int suspended; /* 0 = normal 1 = suspended (APM) */ + int cu_resume_bug; + int chip; + int flags; + u_int32_t saved_maps[5]; /* pci data */ + u_int32_t saved_biosaddr; + u_int8_t saved_intline; + u_int8_t saved_cachelnsz; + u_int8_t saved_lattimer; +}; + +#define FXP_CHIP_82557 1 /* 82557 chip type */ + +#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */ +#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */ +#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */ +#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */ +#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */ +#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */ +#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */ +#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */ + +/* Macros to ease CSR access. */ +#if 0 +#define CSR_READ_1(sc, reg) \ + bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) +#define CSR_READ_2(sc, reg) \ + bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) +#define CSR_READ_4(sc, reg) \ + bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) +#define CSR_WRITE_1(sc, reg, val) \ + bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) +#define CSR_WRITE_2(sc, reg, val) \ + bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) +#else +#define CSR_READ_1(sc, reg) fxp_csr_read_1(sc,reg) +#define CSR_READ_2(sc, reg) fxp_csr_read_2(sc,reg) +#define CSR_READ_4(sc, reg) fxp_csr_read_4(sc,reg) + +#define CSR_WRITE_1(sc, reg, val) \ + do { \ + if ((sc)->pci_regs_are_io) \ + outport_byte((sc)->pci_regs_base+(reg),val); \ + else \ + *((volatile u_int8_t*)((sc)->pci_regs_base)+(reg)) = val; \ + }while (0) + +#define CSR_WRITE_2(sc, reg, val) \ + do { \ + if ((sc)->pci_regs_are_io) \ + outport_word((sc)->pci_regs_base+(reg),val); \ + else \ + *((volatile u_int16_t*)((u_int8_t*)((sc)->pci_regs_base)+(reg))) = val; \ + }while (0) + +#define CSR_WRITE_4(sc, reg, val) \ + do { \ + if ((sc)->pci_regs_are_io) \ + outport_long((sc)->pci_regs_base+(reg),val); \ + else \ + *((volatile u_int32_t*)((u_int8_t*)((sc)->pci_regs_base)+(reg))) = val; \ + }while (0) + +#endif + +#define sc_if arpcom.ac_if + +#define FXP_UNIT(_sc) (_sc)->arpcom.ac_if.if_unit diff --git a/bsps/include/libchip/m48t08.h b/bsps/include/libchip/m48t08.h new file mode 100644 index 0000000000..3c46d384d5 --- /dev/null +++ b/bsps/include/libchip/m48t08.h @@ -0,0 +1,87 @@ +/* + * This file contains the definitions for the following real-time clocks: + * + * + Mostek M48T08 + * + Mostek M48T18 + * + Dallas Semiconductor DS1643 + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LIBCHIP_M48T08_h +#define __LIBCHIP_M48T08_h + +/* + * Register indices + */ + +#define M48T08_CONTROL 0 +#define M48T08_SECOND 1 +#define M48T08_MINUTE 2 +#define M48T08_HOUR 3 +#define M48T08_DAY_OF_WEEK 4 +#define M48T08_DATE 5 +#define M48T08_MONTH 6 +#define M48T08_YEAR 7 + +/* + * Driver function table + */ + +extern rtc_fns m48t08_fns; + +/* + * Default register access routines + */ + +uint32_t m48t08_get_register( /* registers are at 1 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void m48t08_set_register( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +uint32_t m48t08_get_register_2( /* registers are at 2 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void m48t08_set_register_2( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +uint32_t m48t08_get_register_4( /* registers are at 4 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void m48t08_set_register_4( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +uint32_t m48t08_get_register_8( /* registers are at 8 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void m48t08_set_register_8( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +#endif +/* end of include file */ diff --git a/bsps/include/libchip/mc146818a.h b/bsps/include/libchip/mc146818a.h new file mode 100644 index 0000000000..4eb5af04d7 --- /dev/null +++ b/bsps/include/libchip/mc146818a.h @@ -0,0 +1,68 @@ +/* + * This file contains the definitions for the following real-time clocks: + * + * + Motorola MC146818A + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LIBCHIP_MC146818A_h +#define __LIBCHIP_MC146818A_h + +/* + * Register addresses within chip + */ +#define MC146818A_SEC 0x00 /* seconds */ +#define MC146818A_SECALRM 0x01 /* seconds alarm */ +#define MC146818A_MIN 0x02 /* minutes */ +#define MC146818A_MINALRM 0x03 /* minutes alarm */ +#define MC146818A_HRS 0x04 /* hours */ +#define MC146818A_HRSALRM 0x05 /* hours alarm */ +#define MC146818A_WDAY 0x06 /* week day */ +#define MC146818A_DAY 0x07 /* day of month */ +#define MC146818A_MONTH 0x08 /* month of year */ +#define MC146818A_YEAR 0x09 /* month of year */ + +#define MC146818A_STATUSA 0x0a /* status register A */ +#define MC146818ASA_TUP 0x80 /* time update in progress */ +#define MC146818ASA_DIVIDER 0x20 /* divider for 32768 crystal */ +#define MC146818ASA_1024 0x06 /* divide to 1024 Hz */ + +#define MC146818A_STATUSB 0x0b /* status register B */ +#define MC146818ASB_DST 0x01 /* Daylight Savings Time */ +#define MC146818ASB_24HR 0x02 /* 0 = 12 hours, 1 = 24 hours */ +#define MC146818ASB_HALT 0x80 /* stop clock updates */ + +#define MC146818A_STATUSD 0x0d /* status register D */ +#define MC146818ASD_PWR 0x80 /* clock lost power */ + + +/* + * Driver function table + */ +extern rtc_fns mc146818a_fns; +bool mc146818a_probe( + int minor +); + +/* + * Default register access routines + */ +uint32_t mc146818a_get_register( + uintptr_t ulCtrlPort, + uint8_t ucRegNum +); + +void mc146818a_set_register( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +#endif +/* end of include file */ diff --git a/bsps/include/libchip/mc68681.h b/bsps/include/libchip/mc68681.h new file mode 100644 index 0000000000..e498a41b30 --- /dev/null +++ b/bsps/include/libchip/mc68681.h @@ -0,0 +1,122 @@ +/* + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MC68681_H_ +#define _MC68681_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * These are just used in the interface between this driver and + * the read/write register routines when accessing the first + * control port. + */ + +#define MC68681_STATUS 1 +#define MC68681_RX_BUFFER 3 + +#define MC68681_MODE 0 +#define MC68681_CLOCK_SELECT 1 +#define MC68681_COMMAND 2 +#define MC68681_TX_BUFFER 3 + +/* + * Data Port bit map configuration + * + * D0 : Baud Rate Set Selection + * D1 - D2 : Extended Baud Rate Setting + */ + +#define MC68681_DATA_BAUD_RATE_SET_1 0 /* ACR[7] = 0 */ +#define MC68681_DATA_BAUD_RATE_SET_2 1 /* ACR[7] = 1 */ + +#define MC68681_XBRG_IGNORED (0 << 1) +#define MC68681_XBRG_ENABLED (1 << 1) +#define MC68681_XBRG_DISABLED (2 << 1) +#define MC68681_XBRG_MASK (3 << 1) + +/* + * Custom baud rate table information + */ + +typedef unsigned char mc68681_baud_t; +typedef mc68681_baud_t mc68681_baud_table_t[RTEMS_TERMIOS_NUMBER_BAUD_RATES]; + +#define MC68681_BAUD_NOT_VALID 0xFF + +extern mc68681_baud_t + mc68681_baud_rate_table[4][RTEMS_TERMIOS_NUMBER_BAUD_RATES]; + + +/* + * Driver function table + */ + +extern const console_fns mc68681_fns; +extern const console_fns mc68681_fns_polled; + +/* + * Default register access routines + */ + +uint8_t mc68681_get_register( /* registers are at 1 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void mc68681_set_register( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint8_t ucData +); + +uint8_t mc68681_get_register_2( /* registers are at 2 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void mc68681_set_register_2( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint8_t ucData +); + +uint8_t mc68681_get_register_4( /* registers are at 4 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void mc68681_set_register_4( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint8_t ucData +); + +uint8_t mc68681_get_register_8( /* registers are at 8 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void mc68681_set_register_8( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint8_t ucData +); + + +#ifdef __cplusplus +} +#endif + +#endif /* _MC68681_H_ */ diff --git a/bsps/include/libchip/ns16550.h b/bsps/include/libchip/ns16550.h new file mode 100644 index 0000000000..4f1b98bf0b --- /dev/null +++ b/bsps/include/libchip/ns16550.h @@ -0,0 +1,99 @@ +/** + * @file + * + */ + +/* + * COPYRIGHT (c) 1998 by Radstone Technology + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _NS16550_H_ +#define _NS16550_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Driver function table + */ + +extern const console_fns ns16550_fns; +extern const console_fns ns16550_fns_polled; + +/* + * Flow control function tables + */ + +extern const console_flow ns16550_flow_RTSCTS; +extern const console_flow ns16550_flow_DTRCTS; + +/* + * Helpers for printk + */ +void ns16550_outch_polled(console_tbl *c, char out); +int ns16550_inch_polled(console_tbl *c); + +/* Alternative NS16550 driver using the Termios device context */ + +typedef uint8_t (*ns16550_get_reg)(uintptr_t port, uint8_t reg); + +typedef void (*ns16550_set_reg)(uintptr_t port, uint8_t reg, uint8_t value); + +typedef struct { + rtems_termios_device_context base; + ns16550_get_reg get_reg; + ns16550_set_reg set_reg; + uintptr_t port; + rtems_vector_number irq; + uint32_t clock; + uint32_t initial_baud; + bool has_fractional_divider_register; + uint8_t modem_control; + uint8_t line_control; + uint32_t baud_divisor; + size_t out_total; + size_t out_remaining; + size_t out_current; + const char *out_buf; + rtems_termios_tty *tty; +} ns16550_context; + +extern const rtems_termios_device_handler ns16550_handler_interrupt; +extern const rtems_termios_device_handler ns16550_handler_polled; +extern const rtems_termios_device_handler ns16550_handler_task; + +extern const rtems_termios_device_flow ns16550_flow_rtscts; +extern const rtems_termios_device_flow ns16550_flow_dtrcts; + +void ns16550_polled_putchar(rtems_termios_device_context *base, char out); + +int ns16550_polled_getchar(rtems_termios_device_context *base); + +bool ns16550_probe(rtems_termios_device_context *base); + +#ifdef __cplusplus +} +#endif + +#endif /* _NS16550_H_ */ diff --git a/bsps/include/libchip/ns16550_p.h b/bsps/include/libchip/ns16550_p.h new file mode 100755 index 0000000000..e3d0eba557 --- /dev/null +++ b/bsps/include/libchip/ns16550_p.h @@ -0,0 +1,142 @@ +/** + * @file + * + */ + +/* + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _NS16550_P_H_ +#define _NS16550_P_H_ + +#ifndef ASM +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Define NS16550_STATIC to nothing while debugging so the entry points + * will show up in the symbol table. + */ + +#define NS16550_STATIC static + +#define NS16550_RECEIVE_BUFFER 0 +#define NS16550_TRANSMIT_BUFFER 0 +#define NS16550_DIVISOR_LATCH_L 0 +#define NS16550_INTERRUPT_ENABLE 1 +#define NS16550_DIVISOR_LATCH_M 1 +#define NS16550_INTERRUPT_ID 2 +#define NS16550_FIFO_CONTROL 2 +#define NS16550_LINE_CONTROL 3 +#define NS16550_MODEM_CONTROL 4 +#define NS16550_LINE_STATUS 5 +#define NS16550_MODEM_STATUS 6 +#define NS16550_SCRATCH_PAD 7 +#define NS16550_FRACTIONAL_DIVIDER 10 + +/* + * Define serial port interrupt enable register structure. + */ + +#define SP_INT_RX_ENABLE 0x01 +#define SP_INT_TX_ENABLE 0x02 +#define SP_INT_LS_ENABLE 0x04 +#define SP_INT_MS_ENABLE 0x08 + +#define NS16550_ENABLE_ALL_INTR (SP_INT_RX_ENABLE | SP_INT_TX_ENABLE) +#define NS16550_DISABLE_ALL_INTR 0x00 +#define NS16550_ENABLE_ALL_INTR_EXCEPT_TX (SP_INT_RX_ENABLE) + +/* + * Define serial port interrupt ID register structure. + */ + +#define SP_IID_0 0x01 +#define SP_IID_1 0x02 +#define SP_IID_2 0x04 +#define SP_IID_3 0x08 + +/* + * Define serial port fifo control register structure. + */ + +#define SP_FIFO_ENABLE 0x01 +#define SP_FIFO_RXRST 0x02 +#define SP_FIFO_TXRST 0x04 +#define SP_FIFO_DMA 0x08 +#define SP_FIFO_RXLEVEL 0xc0 + +#define SP_FIFO_SIZE 16 + +/* + * Define serial port line control register structure. + */ + +#define SP_LINE_SIZE 0x03 +#define SP_LINE_STOP 0x04 +#define SP_LINE_PAR 0x08 +#define SP_LINE_ODD 0x10 +#define SP_LINE_STICK 0x20 +#define SP_LINE_BREAK 0x40 +#define SP_LINE_DLAB 0x80 + +/* + * Line status register character size definitions. + */ + +#define FIVE_BITS 0x0 /* five bits per character */ +#define SIX_BITS 0x1 /* six bits per character */ +#define SEVEN_BITS 0x2 /* seven bits per character */ +#define EIGHT_BITS 0x3 /* eight bits per character */ + +/* + * Define serial port modem control register structure. + */ + +#define SP_MODEM_DTR 0x01 +#define SP_MODEM_RTS 0x02 +#define SP_MODEM_IRQ 0x08 +#define SP_MODEM_LOOP 0x10 +#define SP_MODEM_DIV4 0x80 + +/* + * Define serial port line status register structure. + */ + +#define SP_LSR_RDY 0x01 +#define SP_LSR_EOVRUN 0x02 +#define SP_LSR_EPAR 0x04 +#define SP_LSR_EFRAME 0x08 +#define SP_LSR_BREAK 0x10 +#define SP_LSR_THOLD 0x20 +#define SP_LSR_TX 0x40 +#define SP_LSR_EFIFO 0x80 + +#ifdef __cplusplus +} +#endif + +#endif /* _NS16550_P_H_ */ diff --git a/bsps/include/libchip/open_eth.h b/bsps/include/libchip/open_eth.h new file mode 100644 index 0000000000..66a5204230 --- /dev/null +++ b/bsps/include/libchip/open_eth.h @@ -0,0 +1,173 @@ +/* Opencores ethernet MAC driver */ +/* adapted from linux driver by Jiri Gaisler */ + +#ifndef _OPEN_ETH_ +#define _OPEN_ETH_ + + +/* Configuration Information */ + +typedef struct { + void *base_address; + uint32_t vector; + uint32_t txd_count; + uint32_t rxd_count; + uint32_t en100MHz; +} open_eth_configuration_t; + + +/* Ethernet buffer descriptor */ + +typedef struct _oeth_rxtxdesc { + volatile uint32_t len_status; /* Length and status */ + volatile uint32_t *addr; /* Buffer pointer */ +} oeth_rxtxdesc; + +/* Ethernet configuration registers */ + +typedef struct _oeth_regs { + volatile uint32_t moder; /* Mode Register */ + volatile uint32_t int_src; /* Interrupt Source Register */ + volatile uint32_t int_mask; /* Interrupt Mask Register */ + volatile uint32_t ipgt; /* Back to Bak Inter Packet Gap Register */ + volatile uint32_t ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */ + volatile uint32_t ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */ + volatile uint32_t packet_len; /* Packet Length Register (min. and max.) */ + volatile uint32_t collconf; /* Collision and Retry Configuration Register */ + volatile uint32_t tx_bd_num; /* Transmit Buffer Descriptor Number Register */ + volatile uint32_t ctrlmoder; /* Control Module Mode Register */ + volatile uint32_t miimoder; /* MII Mode Register */ + volatile uint32_t miicommand; /* MII Command Register */ + volatile uint32_t miiaddress; /* MII Address Register */ + volatile uint32_t miitx_data; /* MII Transmit Data Register */ + volatile uint32_t miirx_data; /* MII Receive Data Register */ + volatile uint32_t miistatus; /* MII Status Register */ + volatile uint32_t mac_addr0; /* MAC Individual Address Register 0 */ + volatile uint32_t mac_addr1; /* MAC Individual Address Register 1 */ + volatile uint32_t hash_addr0; /* Hash Register 0 */ + volatile uint32_t hash_addr1; /* Hash Register 1 */ + volatile uint32_t txctrl; /* Transmitter control register */ + uint32_t empty[235]; /* Unused space */ + oeth_rxtxdesc xd[128]; /* TX & RX descriptors */ +} oeth_regs; + +#define OETH_TOTAL_BD 128 +#define OETH_MAXBUF_LEN 0x610 + +/* Tx BD */ +#define OETH_TX_BD_READY 0x8000 /* Tx BD Ready */ +#define OETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */ +#define OETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */ +#define OETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */ +#define OETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */ + +#define OETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */ +#define OETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */ +#define OETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */ +#define OETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */ +#define OETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */ +#define OETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */ +#define OETH_TX_BD_STATS (OETH_TX_BD_UNDERRUN | \ + OETH_TX_BD_RETRY | \ + OETH_TX_BD_RETLIM | \ + OETH_TX_BD_LATECOL | \ + OETH_TX_BD_DEFER | \ + OETH_TX_BD_CARRIER) + +/* Rx BD */ +#define OETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */ +#define OETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */ +#define OETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */ + +#define OETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */ +#define OETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */ +#define OETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */ +#define OETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */ +#define OETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */ +#define OETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */ +#define OETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */ +#define OETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */ +#define OETH_RX_BD_STATS (OETH_RX_BD_MISS | \ + OETH_RX_BD_OVERRUN | \ + OETH_RX_BD_INVSIMB | \ + OETH_RX_BD_DRIBBLE | \ + OETH_RX_BD_TOOLONG | \ + OETH_RX_BD_SHORT | \ + OETH_RX_BD_CRCERR | \ + OETH_RX_BD_LATECOL) + +/* MODER Register */ +#define OETH_MODER_RXEN 0x00000001 /* Receive Enable */ +#define OETH_MODER_TXEN 0x00000002 /* Transmit Enable */ +#define OETH_MODER_NOPRE 0x00000004 /* No Preamble */ +#define OETH_MODER_BRO 0x00000008 /* Reject Broadcast */ +#define OETH_MODER_IAM 0x00000010 /* Use Individual Hash */ +#define OETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */ +#define OETH_MODER_IFG 0x00000040 /* Min. IFG not required */ +#define OETH_MODER_LOOPBCK 0x00000080 /* Loop Back */ +#define OETH_MODER_NOBCKOF 0x00000100 /* No Backoff */ +#define OETH_MODER_EXDFREN 0x00000200 /* Excess Defer */ +#define OETH_MODER_FULLD 0x00000400 /* Full Duplex */ +#define OETH_MODER_RST 0x00000800 /* Reset MAC */ +#define OETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */ +#define OETH_MODER_CRCEN 0x00002000 /* CRC Enable */ +#define OETH_MODER_HUGEN 0x00004000 /* Huge Enable */ +#define OETH_MODER_PAD 0x00008000 /* Pad Enable */ +#define OETH_MODER_RECSMALL 0x00010000 /* Receive Small */ + +/* Interrupt Source Register */ +#define OETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */ +#define OETH_INT_TXE 0x00000002 /* Transmit Error IRQ */ +#define OETH_INT_RXF 0x00000004 /* Receive Frame IRQ */ +#define OETH_INT_RXE 0x00000008 /* Receive Error IRQ */ +#define OETH_INT_BUSY 0x00000010 /* Busy IRQ */ +#define OETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */ +#define OETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */ + +/* Interrupt Mask Register */ +#define OETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */ +#define OETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */ +#define OETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */ +#define OETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */ +#define OETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */ +#define OETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */ +#define OETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */ + +/* Control Module Mode Register */ +#define OETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */ +#define OETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */ +#define OETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */ + +/* MII Mode Register */ +#define OETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */ +#define OETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */ +#define OETH_MIIMODER_RST 0x00000200 /* MIIM Reset */ + +/* MII Command Register */ +#define OETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */ +#define OETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */ +#define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */ + +/* MII Address Register */ +#define OETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */ +#define OETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */ + +/* MII Status Register */ +#define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */ +#define OETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */ +#define OETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */ + +/* Attatch routine */ + +int rtems_open_eth_driver_attach ( + struct rtems_bsdnet_ifconfig *config, + open_eth_configuration_t *chip +); + +/* +#ifdef CPU_U32_FIX +void ipalign(struct mbuf *m); +#endif + +*/ +#endif /* _OPEN_ETH_ */ diff --git a/bsps/include/libchip/rtc.h b/bsps/include/libchip/rtc.h new file mode 100644 index 0000000000..49dd51c2e2 --- /dev/null +++ b/bsps/include/libchip/rtc.h @@ -0,0 +1,80 @@ +/* + * This file contains the Real-Time Clock definitions. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LIBCHIP_RTC_h +#define __LIBCHIP_RTC_h + +#include +#include + +#include + +/* + * Types for get and set register routines + */ + +typedef uint32_t (*getRegister_f)(uintptr_t port, uint8_t reg); +typedef void (*setRegister_f)(uintptr_t port, uint8_t reg, uint32_t value); + +typedef struct _rtc_fns { + void (*deviceInitialize)(int minor); + int (*deviceGetTime)(int minor, rtems_time_of_day *time); + int (*deviceSetTime)(int minor, const rtems_time_of_day *time); +} rtc_fns; + +typedef enum { + RTC_M48T08, /* SGS-Thomsom M48T08 or M48T18 */ + RTC_ICM7170, /* Harris ICM-7170 */ + RTC_CUSTOM, /* BSP specific driver */ + RTC_MC146818A /* Motorola MC146818A */ +} rtc_devs; + +/* + * Each field is interpreted thus: + * + * sDeviceName This is the name of the device. + * + * deviceType This indicates the chip type. + * + * pDeviceFns This is a pointer to the set of driver routines to use. + * + * pDeviceParams This contains either device specific data or a pointer to a + * device specific information table. + * + * ulCtrlPort1 This is the primary control port number for the device. + * + * ulDataPort This is the port number for the data port of the device + * + * getRegister This is the routine used to read register values. + * + * setRegister This is the routine used to write register values. + */ + +typedef struct _rtc_tbl { + const char *sDeviceName; + rtc_devs deviceType; + const rtc_fns *pDeviceFns; + bool (*deviceProbe)(int minor); + void *pDeviceParams; + uintptr_t ulCtrlPort1; + uintptr_t ulDataPort; + getRegister_f getRegister; + setRegister_f setRegister; +} rtc_tbl; + +extern rtc_tbl RTC_Table[]; +extern size_t RTC_Count; + + +extern bool rtc_probe( int minor ); + +#endif +/* end of include file */ diff --git a/bsps/include/libchip/serial.h b/bsps/include/libchip/serial.h new file mode 100644 index 0000000000..49a7bebdca --- /dev/null +++ b/bsps/include/libchip/serial.h @@ -0,0 +1,235 @@ +/** + * @file + * + * @brief The generic libchip serial driver interface + */ + + +/* + * This file contains the TTY driver table definition + * + * This driver uses the termios pseudo driver. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LIBCHIP_SERIAL_h +#define __LIBCHIP_SERIAL_h + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Types for get and set register routines + */ + +/** + * @typedef getRegister_f + * + * This type function provides a hook for the bsp specific method + * that gets register data from the given port and register. + */ +typedef uint8_t (*getRegister_f)(uintptr_t port, uint8_t reg); + +/** + * @typedef setData_f + * + * This type function provides a hook for the bsp specific method + * that sets register data from the given port and register to the + * given value. + */ +typedef void (*setRegister_f)(uintptr_t port, uint8_t reg, uint8_t value); + +/** + * @typedef getData_f + * + * This type function provides a hook for the bsp specific method + * that gets data from the specified port. + */ +typedef uint8_t (*getData_f)(uintptr_t port); + +/** + * @typedef setData_f + * + * This type function provides a hook for the bsp specific method + * that writes value to the specified port. + */ +typedef void (*setData_f)(uintptr_t port, uint8_t value); + +/** + * @typedef _console_fns + * + * This type definition provides a structure of functions each + * methood provides an interfce to the serial por to do a specific + * function. + */ +typedef struct _console_fns { + bool (*deviceProbe)(int minor); + int (*deviceFirstOpen)(int major, int minor, void *arg); + int (*deviceLastClose)(int major, int minor, void *arg); + int (*deviceRead)(int minor); + ssize_t (*deviceWrite)(int minor, const char *buf, size_t len); + void (*deviceInitialize)(int minor); + void (*deviceWritePolled)(int minor, char cChar); + int (*deviceSetAttributes)(int minor, const struct termios *t); + bool deviceOutputUsesInterrupts; +} console_fns; + +/** + * @typedef _console_flow + * + * This type definition provides a structure of functions + * that provide flow control for the transmit buffer. + */ +typedef struct _console_flow { + int (*deviceStopRemoteTx)(int minor); + int (*deviceStartRemoteTx)(int minor); +} console_flow; + + +/** + * This type defination provides an enumerated type of all + * supported libchip console drivers. + */ +typedef enum { + SERIAL_MC68681, /* Motorola MC68681 or Exar 88681 */ + SERIAL_NS16550, /* National Semiconductor NS16550 */ + SERIAL_NS16550_WITH_FDR, /* National Semiconductor NS16550 + with Fractional Divider Register (FDR) */ + SERIAL_Z85C30, /* Zilog Z85C30 */ + SERIAL_CUSTOM /* BSP specific driver */ +} console_devs; + +/** + * This type defination provides an structure that is used to + * uniquely identify a specific serial port. + */ +typedef struct _console_tbl { + /** This is the name of the device. */ + const char *sDeviceName; + /** This indicates the chip type. It is especially important when + * multiple devices share the same interrupt vector and must be + * distinguished. + */ + console_devs deviceType; + /** pDeviceFns This is a pointer to the set of driver routines to use. */ + const console_fns *pDeviceFns; + /** This value is passed to the serial device driver for use. In termios + * itself the number is ignored. + */ + bool (*deviceProbe)(int minor); + /** This is a pointer to the set of flow control routines to + * use. Serial device drivers will typically supply RTSCTS + * and DTRCTS handshake routines for DCE to DCE communication, + * however for DCE to DTE communication, no such routines + * should be necessary as RTS will be driven automatically + * when the transmitter is active. + */ + const console_flow *pDeviceFlow; + /** The high water mark in the input buffer is set to the buffer + * size less ulMargin. Once this level is reached, the driver's + * flow control routine used to stop the remote transmitter will + * be called. This figure should be greater than or equal to + * the number of stages of FIFO between the transmitter and + * receiver. + * + * @note At the current time, this parameter is hard coded + * in termios and this number is ignored. + */ + uint32_t ulMargin; + /** After the high water mark specified by ulMargin has been + * reached, the driver's routine to re-start the remote + * transmitter will be called once the level in the input + * buffer has fallen by ulHysteresis bytes. + * + * @note At the current time, this parameter is hard coded in termios. + */ + uint32_t ulHysteresis; + /** This contains either device specific data or a pointer to a + * device specific structure containing additional information + * not provided in this table. + */ + void *pDeviceParams; + /** This is the primary control port number for the device. This + * may be used to specify different instances of the same device type. + */ + uint32_t ulCtrlPort1; + /** This is the secondary control port number, of use when a given + * device has more than one available channel. + */ + uint32_t ulCtrlPort2; + /** This is the port number for the data port of the device */ + uint32_t ulDataPort; + /** This is the routine used to read register values. */ + getRegister_f getRegister; + /** This is the routine used to write register values. */ + setRegister_f setRegister; + /** This is the routine used to read the data register (RX). */ + getData_f getData; + /* This is the routine used to write the data register (TX). */ + setData_f setData; + /** This is the baud rate clock speed.*/ + uint32_t ulClock; + /** This encodes the interrupt vector of the device. */ + unsigned int ulIntVector; +} console_tbl; + +/** + * This type defination provides data for the console port. + */ +typedef struct _console_data { + void *termios_data; + volatile bool bActive; + /** This field may be used for any purpose required by the driver */ + void *pDeviceContext; +} console_data; + +/** + * This is a dynamically sized set of tables containing the serial + * port information. + */ +extern console_tbl **Console_Port_Tbl; +/** + * This is the number of serial ports defined in the Console_Port_Tbl. + */ +extern unsigned long Console_Port_Count; + +/** + * The statically configured serial port information tables which + * are used to initially populate the dynamic tables. + */ +extern console_tbl Console_Configuration_Ports[]; +/** + * The number of serial ports defined in Console_Configuration_Ports + * */ +extern unsigned long Console_Configuration_Count; + +/** + * This is an array of per port information. + */ +extern console_data *Console_Port_Data; + +extern rtems_device_minor_number Console_Port_Minor; + +/** + * @brief Selects the minor number of the console device. + * + * @see Console_Port_Minor. + */ +void bsp_console_select(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/libchip/sersupp.h b/bsps/include/libchip/sersupp.h new file mode 100644 index 0000000000..6d24d25b61 --- /dev/null +++ b/bsps/include/libchip/sersupp.h @@ -0,0 +1,19 @@ +#ifndef __LIBCHIP_SERIAL_SUPPORT_h +#define __LIBCHIP_SERIAL_SUPPORT_h + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +bool libchip_serial_default_probe( + int minor +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/include/libchip/smc91111.h b/bsps/include/libchip/smc91111.h new file mode 100644 index 0000000000..7ec83716d0 --- /dev/null +++ b/bsps/include/libchip/smc91111.h @@ -0,0 +1,558 @@ +#ifndef _SMC91111_H_ +#define _SMC91111_H_ + +#include +#include + +#define LAN91CXX_TCR 0x00 +#define LAN91CXX_EPH_STATUS 0x01 +#define LAN91CXX_RCR 0x02 +#define LAN91CXX_COUNTER 0x03 +#define LAN91CXX_MIR 0x04 +#define LAN91CXX_MCR 0x05 /* Other than 91C111*/ +#define LAN91CXX_RPCR 0x05 /* 91C111 only*/ +#define LAN91CXX_RESERVED_0 0x06 +#define LAN91CXX_BS 0x07 +#define LAN91CXX_CONFIG 0x08 +#define LAN91CXX_BASE_REG 0x09 +#define LAN91CXX_IA01 0x0a +#define LAN91CXX_IA23 0x0b +#define LAN91CXX_IA45 0x0c +#define LAN91CXX_GENERAL 0x0d /* 91C96 - was "RESERVED_1" for others*/ +#define LAN91CXX_CONTROL 0x0e +#define LAN91CXX_BS2 0x0f +#define LAN91CXX_MMU_COMMAND 0x10 +#define LAN91CXX_PNR 0x11 +#define LAN91CXX_FIFO_PORTS 0x12 +#define LAN91CXX_POINTER 0x13 +#define LAN91CXX_DATA_HIGH 0x14 +#define LAN91CXX_DATA 0x15 +#define LAN91CXX_INTERRUPT 0x16 +#define LAN91CXX_BS3 0x17 +#define LAN91CXX_MT01 0x18 +#define LAN91CXX_MT23 0x19 +#define LAN91CXX_MT45 0x1a +#define LAN91CXX_MT67 0x1b +#define LAN91CXX_MGMT 0x1c +#define LAN91CXX_REVISION 0x1d +#define LAN91CXX_ERCV 0x1e +#define LAN91CXX_BS4 0x1f + +#define LAN91CXX_RCR_SOFT_RST 0x8000 /* soft reset*/ +#define LAN91CXX_RCR_FILT_CAR 0x4000 /* filter carrier*/ +#define LAN91CXX_RCR_ABORT_ENB 0x2000 /* abort on collision*/ +#define LAN91CXX_RCR_STRIP_CRC 0x0200 /* strip CRC*/ +#define LAN91CXX_RCR_RXEN 0x0100 /* enable RX*/ +#define LAN91CXX_RCR_ALMUL 0x0004 /* receive all muticasts*/ +#define LAN91CXX_RCR_PRMS 0x0002 /* promiscuous*/ +#define LAN91CXX_RCR_RX_ABORT 0x0001 /* set when abort due to long frame*/ + +#define LAN91CXX_TCR_SWFDUP 0x8000 /* Switched Full Duplex mode*/ +#define LAN91CXX_TCR_ETEN_TYPE 0x4000 /* ETEN type (91C96) 0 <=> like a 91C94*/ +#define LAN91CXX_TCR_EPH_LOOP 0x2000 /* loopback mode*/ +#define LAN91CXX_TCR_STP_SQET 0x1000 /* Stop transmission on SQET error*/ +#define LAN91CXX_TCR_FDUPLX 0x0800 /* full duplex*/ +#define LAN91CXX_TCR_MON_CSN 0x0400 /* monitor carrier during tx (91C96)*/ +#define LAN91CXX_TCR_NOCRC 0x0100 /* does not append CRC to frames*/ +#define LAN91CXX_TCR_PAD_EN 0x0080 /* pads frames with 00 to min length*/ +#define LAN91CXX_TCR_FORCOL 0x0004 /* force collision*/ +#define LAN91CXX_TCR_LLOOP 0x0002 /* local loopback (91C96)*/ +#define LAN91CXX_TCR_TXENA 0x0001 /* enable*/ + +#define LAN91CXX_POINTER_RCV 0x8000 +#define LAN91CXX_POINTER_AUTO_INCR 0x4000 +#define LAN91CXX_POINTER_READ 0x2000 +#define LAN91CXX_POINTER_ETEN 0x1000 +#define LAN91CXX_POINTER_NOT_EMPTY 0x0800 + + +#define LAN91CXX_INTERRUPT_TX_IDLE_M 0x8000 /* (91C96)*/ +#define LAN91CXX_INTERRUPT_ERCV_INT_M 0x4000 +#define LAN91CXX_INTERRUPT_EPH_INT_M 0x2000 +#define LAN91CXX_INTERRUPT_RX_OVRN_INT_M 0x1000 +#define LAN91CXX_INTERRUPT_ALLOC_INT_M 0x0800 +#define LAN91CXX_INTERRUPT_TX_EMPTY_INT_M 0x0400 +#define LAN91CXX_INTERRUPT_TX_INT_M 0x0200 +#define LAN91CXX_INTERRUPT_RCV_INT_M 0x0100 +#define LAN91CXX_INTERRUPT_TX_IDLE 0x0080 /* (91C96)*/ +#define LAN91CXX_INTERRUPT_ERCV_INT 0x0040 /* also ack*/ +#define LAN91CXX_INTERRUPT_EPH_INT 0x0020 +#define LAN91CXX_INTERRUPT_RX_OVRN_INT 0x0010 /* also ack*/ +#define LAN91CXX_INTERRUPT_ALLOC_INT 0x0008 +#define LAN91CXX_INTERRUPT_TX_EMPTY_INT 0x0004 /* also ack*/ +#define LAN91CXX_INTERRUPT_TX_INT 0x0002 /* also ack*/ +#define LAN91CXX_INTERRUPT_RCV_INT 0x0001 + +#define LAN91CXX_INTERRUPT_TX_SET 0x0006 /* TX_EMPTY + TX*/ +#define LAN91CXX_INTERRUPT_TX_SET_ACK 0x0004 /* TX_EMPTY and not plain TX*/ +#define LAN91CXX_INTERRUPT_TX_FIFO_ACK 0x0002 /* TX alone*/ +#define LAN91CXX_INTERRUPT_TX_SET_M 0x0600 /* TX_EMPTY + TX*/ + +#define LAN91CXX_CONTROL_RCV_BAD 0x4000 +#define LAN91CXX_CONTROL_AUTO_RELEASE 0x0800 +#define LAN91CXX_CONTROL_LE_ENABLE 0x0080 +#define LAN91CXX_CONTROL_CR_ENABLE 0x0040 +#define LAN91CXX_CONTROL_TE_ENABLE 0x0020 + +/* These are for setting the MAC address in the 91C96 serial EEPROM*/ +#define LAN91CXX_CONTROL_EEPROM_SELECT 0x0004 +#define LAN91CXX_CONTROL_RELOAD 0x0002 +#define LAN91CXX_CONTROL_STORE 0x0001 +#define LAN91CXX_CONTROL_EEPROM_BUSY 0x0003 +#define LAN91CXX_ESA_EEPROM_OFFSET 0x0020 + +#define LAN91CXX_STATUS_TX_UNRN 0x8000 +#define LAN91CXX_STATUS_LINK_OK 0x4000 +#define LAN91CXX_STATUS_CTR_ROL 0x1000 +#define LAN91CXX_STATUS_EXC_DEF 0x0800 +#define LAN91CXX_STATUS_LOST_CARR 0x0400 +#define LAN91CXX_STATUS_LATCOL 0x0200 +#define LAN91CXX_STATUS_WAKEUP 0x0100 +#define LAN91CXX_STATUS_TX_DEFR 0x0080 +#define LAN91CXX_STATUS_LTX_BRD 0x0040 +#define LAN91CXX_STATUS_SQET 0x0020 +#define LAN91CXX_STATUS_16COL 0x0010 +#define LAN91CXX_STATUS_LTX_MULT 0x0008 +#define LAN91CXX_STATUS_MUL_COL 0x0004 +#define LAN91CXX_STATUS_SNGL_COL 0x0002 +#define LAN91CXX_STATUS_TX_SUC 0x0001 + +#define LAN91CXX_MMU_COMMAND_BUSY 0x0001 + +#define LAN91CXX_MMU_noop 0x0000 +#define LAN91CXX_MMU_alloc_for_tx 0x0020 +#define LAN91CXX_MMU_reset_mmu 0x0040 +#define LAN91CXX_MMU_rem_rx_frame 0x0060 +#define LAN91CXX_MMU_rem_tx_frame 0x0070 /* (91C96) only when TX stopped*/ +#define LAN91CXX_MMU_remrel_rx_frame 0x0080 +#define LAN91CXX_MMU_rel_packet 0x00a0 +#define LAN91CXX_MMU_enq_packet 0x00c0 +#define LAN91CXX_MMU_reset_tx_fifo 0x00e0 + +#define LAN91CXX_CONTROLBYTE_CRC 0x1000 +#define LAN91CXX_CONTROLBYTE_ODD 0x2000 +#define LAN91CXX_CONTROLBYTE_RX 0x4000 + +#define LAN91CXX_RX_STATUS_ALIGNERR 0x8000 +#define LAN91CXX_RX_STATUS_BCAST 0x4000 +#define LAN91CXX_RX_STATUS_BADCRC 0x2000 +#define LAN91CXX_RX_STATUS_ODDFRM 0x1000 +#define LAN91CXX_RX_STATUS_TOOLONG 0x0800 +#define LAN91CXX_RX_STATUS_TOOSHORT 0x0400 +#define LAN91CXX_RX_STATUS_HASHVALMASK 0x007e /* MASK*/ +#define LAN91CXX_RX_STATUS_MCAST 0x0001 +#define LAN91CXX_RX_STATUS_BAD \ + (LAN91CXX_RX_STATUS_ALIGNERR | \ + LAN91CXX_RX_STATUS_BADCRC | \ + LAN91CXX_RX_STATUS_TOOLONG | \ + LAN91CXX_RX_STATUS_TOOSHORT) + +#define LAN91CXX_RX_STATUS_IS_ODD(__cpd,__stat) ((__stat) & LAN91CXX_RX_STATUS_ODDFRM) +#define LAN91CXX_CONTROLBYTE_IS_ODD(__cpd,__val) ((__val) & LAN91CXX_CONTROLBYTE_ODD) + +/* Attribute memory registers in PCMCIA mode*/ +#define LAN91CXX_ECOR 0x8000 +#define LAN91CXX_ECOR_RESET (1<<7) +#define LAN91CXX_ECOR_LEVIRQ (1<<6) +#define LAN91CXX_ECOR_ATTWR (1<<2) +#define LAN91CXX_ECOR_ENABLE (1<<0) + +#define LAN91CXX_ECSR 0x8002 +#define LAN91CXX_ECSR_IOIS8 (1<<5) +#define LAN91CXX_ECSR_PWRDWN (1<<2) +#define LAN91CXX_ECSR_INTR (1<<1) + +/* These are for manipulating the MII interface*/ +#define LAN91CXX_MGMT_MDO 0x0001 +#define LAN91CXX_MGMT_MDI 0x0002 +#define LAN91CXX_MGMT_MCLK 0x0004 +#define LAN91CXX_MGMT_MDOE 0x0008 + +/* Internal PHY registers (91c111)*/ +#define LAN91CXX_PHY_CTRL 0 +#define LAN91CXX_PHY_STAT 1 +#define LAN91CXX_PHY_ID1 2 +#define LAN91CXX_PHY_ID2 3 +#define LAN91CXX_PHY_AUTO_AD 4 +#define LAN91CXX_PHY_AUTO_CAP 5 +#define LAN91CXX_PHY_CONFIG1 16 +#define LAN91CXX_PHY_CONFIG2 17 +#define LAN91CXX_PHY_STATUS_OUT 18 +#define LAN91CXX_PHY_MASK 19 + +/* PHY control bits*/ +#define LAN91CXX_PHY_CTRL_COLTST (1 << 7) +#define LAN91CXX_PHY_CTRL_DPLX (1 << 8) +#define LAN91CXX_PHY_CTRL_ANEG_RST (1 << 9) +#define LAN91CXX_PHY_CTRL_MII_DIS (1 << 10) +#define LAN91CXX_PHY_CTRL_PDN (1 << 11) +#define LAN91CXX_PHY_CTRL_ANEG_EN (1 << 12) +#define LAN91CXX_PHY_CTRL_SPEED (1 << 13) +#define LAN91CXX_PHY_CTRL_LPBK (1 << 14) +#define LAN91CXX_PHY_CTRL_RST (1 << 15) + +/* PHY Configuration Register 1 */ +#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ +#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ +#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ +#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ +#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ +#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ +#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ +#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ +#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ +#define PHY_CFG1_TLVL_MASK 0x003C +#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ + +/* PHY Configuration Register 2 */ +#define PHY_CFG2_REG 0x11 +#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ +#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ +#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ +#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ + +/* PHY Status Output (and Interrupt status) Register */ +#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ +#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ +#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ +#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ +#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ +#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ +#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ +#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ +#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ +#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ +#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ + +/* PHY Interrupt/Status Mask Register */ +#define PHY_MASK_REG 0x13 /* Interrupt Mask */ + +#define LAN91CXX_RPCR_LEDA_LINK (0 << 2) +#define LAN91CXX_RPCR_LEDA_TXRX (4 << 2) +#define LAN91CXX_RPCR_LEDA_RX (6 << 2) +#define LAN91CXX_RPCR_LEDA_TX (7 << 2) +#define LAN91CXX_RPCR_LEDB_LINK (0 << 5) +#define LAN91CXX_RPCR_LEDB_TXRX (4 << 5) +#define LAN91CXX_RPCR_LEDB_RX (6 << 5) +#define LAN91CXX_RPCR_LEDB_TX (7 << 5) +#define LAN91CXX_RPCR_ANEG (1 << 11) +#define LAN91CXX_RPCR_DPLX (1 << 12) +#define LAN91CXX_RPCR_SPEED (1 << 13) + +/* PHY Control Register */ +#define PHY_CNTL_REG 0x00 +#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ +#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ +#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ +#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ +#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ +#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ +#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ +#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ +#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ + +/* PHY Status Register */ +#define PHY_STAT_REG 0x01 +#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ +#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ +#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ +#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ +#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ +#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ +#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ +#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ +#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ +#define PHY_STAT_LINK 0x0004 /* 1=valid link */ +#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ +#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ +#define PHY_STAT_RESERVED 0x0780 /* Reserved bits mask. */ + +/* PHY Identifier Registers */ +#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ +#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ + +/* PHY Auto-Negotiation Advertisement Register */ +#define PHY_AD_REG 0x04 +#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ +#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ +#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ +#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ +#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ +#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ +#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ +#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ +#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ + + +static int debugflag_out = 0; + +#define dbc_printf(lvl,format, args...) do { \ + if (!debugflag_out) { \ + if (lvl & DEBUG) { \ + printk(format,##args); \ + } \ + } \ +} while(0) + +#define db64_printf(format, args...) dbc_printf(64,format,##args); +#define db16_printf(format, args...) dbc_printf(16,format,##args); +#define db9_printf(format, args...) dbc_printf(9,format,##args); +#define db4_printf(format, args...) dbc_printf(4,format,##args); +#define db2_printf(format, args...) dbc_printf(2,format,##args); +#define db1_printf(format, args...) dbc_printf(1,format,##args); +#define db_printf(format, args...) dbc_printf(0xffff,format,##args); + +#if DEBUG & 1 +#define DEBUG_FUNCTION() do { db_printf("# %s\n", __FUNCTION__); } while (0) +#else +#define DEBUG_FUNCTION() do {} while(0) +#endif + + +/* ------------------------------------------------------------------------*/ + +struct smsc_lan91cxx_stats { + unsigned int tx_good ; + unsigned int tx_max_collisions ; + unsigned int tx_late_collisions ; + unsigned int tx_underrun ; + unsigned int tx_carrier_loss ; + unsigned int tx_deferred ; + unsigned int tx_sqetesterrors ; + unsigned int tx_single_collisions; + unsigned int tx_mult_collisions ; + unsigned int tx_total_collisions ; + unsigned int rx_good ; + unsigned int rx_crc_errors ; + unsigned int rx_align_errors ; + unsigned int rx_resource_errors ; + unsigned int rx_overrun_errors ; + unsigned int rx_collisions ; + unsigned int rx_short_frames ; + unsigned int rx_too_long_frames ; + unsigned int rx_symbol_errors ; + unsigned int interrupts ; + unsigned int rx_count ; + unsigned int rx_deliver ; + unsigned int rx_resource ; + unsigned int rx_restart ; + unsigned int tx_count ; + unsigned int tx_complete ; + unsigned int tx_dropped ; +}; +#define INCR_STAT(c,n) (((c)->stats.n)++) + +struct lan91cxx_priv_data; + +typedef struct lan91cxx_priv_data { + + /* frontend */ + struct arpcom arpcom; + rtems_id rxDaemonTid; + rtems_id txDaemonTid; + + scmv91111_configuration_t config; + + /* backend */ + int rpc_cur_mode; + int autoneg_active; + int phyaddr; + unsigned int lastPhy18; + + int txbusy; /* A packet has been sent*/ + unsigned long txkey; /* Used to ack when packet sent*/ + unsigned short* base; /* Base I/O address of controller*/ + /* (as it comes out of reset)*/ + int interrupt; /* Interrupt vector used by controller*/ + unsigned char enaddr[6]; /* Controller ESA*/ + /* Function to configure the ESA - may fetch ESA from EPROM or */ + /* RedBoot config option. Use of the 'config_enaddr()' function*/ + /* is depreciated in favor of the 'provide_esa()' function and*/ + /* 'hardwired_esa' boolean*/ + void (*config_enaddr)(struct lan91cxx_priv_data* cpd); + int hardwired_esa; + int txpacket; + int rxpacket; + int within_send; + int c111_reva; /* true if this is a revA LAN91C111*/ + struct smsc_lan91cxx_stats stats; +} lan91cxx_priv_data; + +/* ------------------------------------------------------------------------*/ + +#ifdef LAN91CXX_32BIT_RX +typedef unsigned int rxd_t; +#else +typedef unsigned short rxd_t; +#endif + +typedef struct _debug_regs_pair { + int reg; char *name; struct _debug_regs_pair *bits; +} debug_regs_pair; + +static debug_regs_pair debug_regs[] = { + {LAN91CXX_TCR , "LAN91CXX_TCR" ,0}, + {LAN91CXX_EPH_STATUS , "LAN91CXX_EPH_STATUS",0}, + {LAN91CXX_RCR , "LAN91CXX_RCR" ,0}, + {LAN91CXX_COUNTER , "LAN91CXX_COUNTER" ,0}, + {LAN91CXX_MIR , "LAN91CXX_MIR" ,0}, + {LAN91CXX_MCR , "LAN91CXX_MCR" ,0}, + {LAN91CXX_RPCR , "LAN91CXX_RPCR" ,0}, + {LAN91CXX_RESERVED_0 , "LAN91CXX_RESERVED_0",0}, + {LAN91CXX_BS , "LAN91CXX_BS" ,0}, + {LAN91CXX_CONFIG , "LAN91CXX_CONFIG" ,0}, + {LAN91CXX_BASE_REG , "LAN91CXX_BASE_REG" ,0}, + {LAN91CXX_IA01 , "LAN91CXX_IA01" ,0}, + {LAN91CXX_IA23 , "LAN91CXX_IA23" ,0}, + {LAN91CXX_IA45 , "LAN91CXX_IA45" ,0}, + {LAN91CXX_GENERAL , "LAN91CXX_GENERAL" ,0}, + {LAN91CXX_CONTROL , "LAN91CXX_CONTROL" ,0}, + {LAN91CXX_BS2 , "LAN91CXX_BS2" ,0}, + {LAN91CXX_MMU_COMMAND, "LAN91CXX_MMU_COMMAND",0}, + {LAN91CXX_PNR , "LAN91CXX_PNR" ,0}, + {LAN91CXX_FIFO_PORTS , "LAN91CXX_FIFO_PORTS" ,0}, + {LAN91CXX_POINTER , "LAN91CXX_POINTER" ,0}, + {LAN91CXX_DATA_HIGH , "LAN91CXX_DATA_HIGH" ,0}, + {LAN91CXX_DATA , "LAN91CXX_DATA" ,0}, + {LAN91CXX_INTERRUPT , "LAN91CXX_INTERRUPT" ,0}, + {LAN91CXX_BS3 , "LAN91CXX_BS3" ,0}, + {LAN91CXX_MT01 , "LAN91CXX_MT01" ,0}, + {LAN91CXX_MT23 , "LAN91CXX_MT23" ,0}, + {LAN91CXX_MT45 , "LAN91CXX_MT45" ,0}, + {LAN91CXX_MT67 , "LAN91CXX_MT67" ,0}, +/*{LAN91CXX_MGMT , "LAN91CXX_MGMT" ,0}, */ + {LAN91CXX_REVISION , "LAN91CXX_REVISION" ,0}, + {LAN91CXX_ERCV , "LAN91CXX_ERCV" ,0}, + {LAN91CXX_BS4 , "LAN91CXX_BS4" ,0}, + + + + {-1,0} +}; + +static char *dbg_prefix = ""; + +#ifndef SMSC_PLATFORM_DEFINED_GET_REG +static __inline__ unsigned short +get_reg(struct lan91cxx_priv_data *cpd, int regno) +{ + unsigned short val; debug_regs_pair *dbg = debug_regs; int c; + uint32_t Irql; + + /*rtems_interrupt_disable(Irql);*/ + + HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS), CYG_CPU_TO_LE16(regno>>3)); + HAL_READ_UINT16(cpd->base+((regno&0x7)), val); + val = CYG_LE16_TO_CPU(val); + + /*rtems_interrupt_enable(Irql);*/ + +#if DEBUG & 32 + while ((c = dbg->reg) != -1) { + if (c == regno) { + db_printf("%sread reg [%d:%x] -> 0x%04x (%-20s)\n", dbg_prefix, regno>>3,(regno&0x7)*2, val, dbg->name); + break; + } + dbg++; + } +#else + db2_printf("%sread reg %d:%x -> 0x%04x\n", dbg_prefix, regno>>3,(regno&0x7)*2, val); +#endif + + return val; +} +#endif /* SMSC_PLATFORM_DEFINED_GET_REG*/ + +#ifndef SMSC_PLATFORM_DEFINED_PUT_REG +static __inline__ void +put_reg(struct lan91cxx_priv_data *cpd, int regno, unsigned short val) +{ + debug_regs_pair *dbg = debug_regs; int c; + uint32_t Irql; + +#if DEBUG & 32 + while ((c = dbg->reg) != -1) { + if (c == regno) { + db_printf("%swrite reg [%d:%x] <- 0x%04x (%-20s)\n", dbg_prefix, regno>>3, (regno&0x07)*2, val, dbg->name); + break; + } + dbg++; + } +#else + db2_printf("%swrite reg %d:%x <- 0x%04x\n", dbg_prefix, regno>>3,(regno&0x7)*2, val); +#endif + + /*rtems_interrupt_disable(Irql);*/ + + HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS), CYG_CPU_TO_LE16(regno>>3)); + HAL_WRITE_UINT16(cpd->base+((regno&0x7)), CYG_CPU_TO_LE16(val)); + + /*rtems_interrupt_enable(Irql);*/ + +} +#endif /* SMSC_PLATFORM_DEFINED_PUT_REG*/ + +#ifndef SMSC_PLATFORM_DEFINED_PUT_DATA +/* ------------------------------------------------------------------------*/ +/* Assumes bank2 has been selected*/ +static __inline__ void +put_data(struct lan91cxx_priv_data *cpd, unsigned short val) +{ + db2_printf("%s[wdata] <- 0x%04x\n", dbg_prefix, val); + + HAL_WRITE_UINT16(cpd->base+((LAN91CXX_DATA & 0x7)), val); + +} + +/* Assumes bank2 has been selected*/ +static __inline__ void +put_data8(struct lan91cxx_priv_data *cpd, unsigned char val) +{ + db2_printf("%s[bdata] <- 0x%02x\n", dbg_prefix, val); + + HAL_WRITE_UINT8(((unsigned char *)(cpd->base+((LAN91CXX_DATA & 0x7))))+1, val); + +} + +#endif /* SMSC_PLATFORM_DEFINED_PUT_DATA*/ + +#ifndef SMSC_PLATFORM_DEFINED_GET_DATA +/* Assumes bank2 has been selected*/ +static __inline__ rxd_t +get_data(struct lan91cxx_priv_data *cpd) +{ + rxd_t val; + +#ifdef LAN91CXX_32BIT_RX + HAL_READ_UINT32(cpd->base+((LAN91CXX_DATA_HIGH & 0x7)), val); +#else + HAL_READ_UINT16(cpd->base+((LAN91CXX_DATA & 0x7)), val); +#endif + + db2_printf("%s[rdata] -> 0x%08x\n", dbg_prefix, val); + return val; +} +#endif /* SMSC_PLATFORM_DEFINED_GET_DATA*/ + +/* ------------------------------------------------------------------------*/ +/* Read the bank register (this one is bank-independent)*/ +#ifndef SMSC_PLATFORM_DEFINED_GET_BANKSEL +static __inline__ unsigned short +get_banksel(struct lan91cxx_priv_data *cpd) +{ + unsigned short val; + + HAL_READ_UINT16(cpd->base+(LAN91CXX_BS), val); + val = CYG_LE16_TO_CPU(val); + db2_printf("read bank sel val 0x%04x\n", val); + return val; +} +#endif + + + + + +#endif /* _SMC_91111_H_ */ + + diff --git a/bsps/include/libchip/smc91111exp.h b/bsps/include/libchip/smc91111exp.h new file mode 100644 index 0000000000..08e086d9e7 --- /dev/null +++ b/bsps/include/libchip/smc91111exp.h @@ -0,0 +1,26 @@ +#ifndef _SMC91111_EXP_H_ +#define _SMC91111_EXP_H_ + +#include + +typedef struct scmv91111_configuration { + void *baseaddr; + rtems_vector_number vector; + unsigned int pio; + unsigned int ctl_rspeed; + unsigned int ctl_rfduplx; + unsigned int ctl_autoneg; +#ifdef BSP_FEATURE_IRQ_EXTENSION + const char * info; + rtems_option options; + rtems_interrupt_handler interrupt_wrapper; + void * arg; +#endif +} scmv91111_configuration_t; + +int _rtems_smc91111_driver_attach (struct rtems_bsdnet_ifconfig *config, + scmv91111_configuration_t * scm_config); + +#endif /* _SMC_91111_EXP_H_ */ + + diff --git a/bsps/include/libchip/sonic.h b/bsps/include/libchip/sonic.h new file mode 100644 index 0000000000..fe119ff20a --- /dev/null +++ b/bsps/include/libchip/sonic.h @@ -0,0 +1,458 @@ +/* + * RTEMS NETWORK DRIVER FOR NATIONAL DP83932 `SONIC' + * SYSTEMS-ORIENTED NETWORK INTERFACE CONTROLLER + * + * REUSABLE CHIP DRIVER CONFIGURATION + * + * References: + * + * 1) DP83932C-20/25/33 MHz SONIC(TM) Systems-Oriented Network Interface + * Controller data sheet. TL/F/10492, RRD-B30M105, National Semiconductor, + * 1995. + * + * 2) Software Driver Programmer's Guide for the DP83932 SONIC(TM), + * Application Note 746, Wesley Lee and Mike Lui, TL/F/11140, + * RRD-B30M75, National Semiconductor, March, 1991. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _SONIC_DP83932_ +#define _SONIC_DP83932_ + + + /* + * Debug levels + * + */ + +#define SONIC_DEBUG_NONE 0x0000 +#define SONIC_DEBUG_ALL 0xFFFF +#define SONIC_DEBUG_PRINT_REGISTERS 0x0001 +#define SONIC_DEBUG_MEMORY 0x0002 +#define SONIC_DEBUG_MEMORY_ALLOCATE 0x0004 +#define SONIC_DEBUG_MEMORY_DESCRIPTORS 0x0008 +#define SONIC_DEBUG_FRAGMENTS 0x0008 +#define SONIC_DEBUG_CAM 0x0010 +#define SONIC_DEBUG_DESCRIPTORS 0x0020 +#define SONIC_DEBUG_ERRORS 0x0040 +#define SONIC_DEBUG_DUMP_TX_MBUFS 0x0080 +#define SONIC_DEBUG_DUMP_RX_MBUFS 0x0100 + +#define SONIC_DEBUG_DUMP_MBUFS \ + (SONIC_DEBUG_DUMP_TX_MBUFS|SONIC_DEBUG_DUMP_RX_MBUFS) + +#define SONIC_DEBUG (SONIC_DEBUG_NONE) +/* +#define SONIC_DEBUG (SONIC_DEBUG_ERRORS | SONIC_DEBUG_PRINT_REGISTERS |\ + SONIC_DEBUG_DESCRIPTORS) +*/ + +/* + ((SONIC_DEBUG_ALL) & ~(SONIC_DEBUG_PRINT_REGISTERS|SONIC_DEBUG_DUMP_MBUFS)) + ((SONIC_DEBUG_ALL) & ~(SONIC_DEBUG_DUMP_MBUFS)) +*/ + +#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS) +extern char SONIC_Reg_name[64][6]; +#endif + + +/* + * Configuration Information + */ + +typedef void (*sonic_write_register_t)( + void *base, + uint32_t regno, + uint32_t value +); + +typedef uint32_t (*sonic_read_register_t)( + void *base, + uint32_t regno +); + +typedef struct { + void *base_address; + uint32_t vector; + uint32_t dcr_value; + uint32_t dc2_value; + uint32_t tda_count; + uint32_t rda_count; + sonic_write_register_t write_register; + sonic_read_register_t read_register; +} sonic_configuration_t; + +/* + ****************************************************************** + * * + * Device Registers * + * * + ****************************************************************** + */ +#define SONIC_REG_CR 0x00 /* Command */ +#define SONIC_REG_DCR 0x01 /* Data configuration */ +#define SONIC_REG_RCR 0x02 /* Receive control */ +#define SONIC_REG_TCR 0x03 /* Transmit control */ +#define SONIC_REG_IMR 0x04 /* Interrupt mask */ +#define SONIC_REG_ISR 0x05 /* Interrupt status */ +#define SONIC_REG_UTDA 0x06 /* Upper transmit descriptor address */ +#define SONIC_REG_CTDA 0x07 /* Current transmit descriptor address */ +#define SONIC_REG_URDA 0x0D /* Upper receive descriptor address */ +#define SONIC_REG_CRDA 0x0E /* Current receive descriptor address */ +#define SONIC_REG_EOBC 0x13 /* End of buffer word count */ +#define SONIC_REG_URRA 0x14 /* Upper receive resource */ +#define SONIC_REG_RSA 0x15 /* Resource start address */ +#define SONIC_REG_REA 0x16 /* Resource end address */ +#define SONIC_REG_RRP 0x17 /* Resouce read pointer */ +#define SONIC_REG_RWP 0x18 /* Resouce write pointer */ +#define SONIC_REG_CEP 0x21 /* CAM entry pointer */ +#define SONIC_REG_CAP2 0x22 /* CAM address port 2 */ +#define SONIC_REG_CAP1 0x23 /* CAM address port 1 */ +#define SONIC_REG_CAP0 0x24 /* CAM address port 0 */ +#define SONIC_REG_CE 0x25 /* CAM enable */ +#define SONIC_REG_CDP 0x26 /* CAM descriptor pointer */ +#define SONIC_REG_CDC 0x27 /* CAM descriptor count */ +#define SONIC_REG_SR 0x28 /* Silicon revision */ +#define SONIC_REG_WT0 0x29 /* Watchdog timer 0 */ +#define SONIC_REG_WT1 0x2A /* Watchdog timer 1 */ +#define SONIC_REG_RSC 0x2B /* Receive sequence counter */ +#define SONIC_REG_CRCT 0x2C /* CRC error tally */ +#define SONIC_REG_FAET 0x2D /* FAE tally */ +#define SONIC_REG_MPT 0x2E /* Missed packet tally */ +#define SONIC_REG_MDT 0x2F /* TX Maximum Deferral */ +#define SONIC_REG_DCR2 0x3F /* Data configuration 2 */ + +/* + * Command register + */ +#define CR_LCAM 0x0200 +#define CR_RRRA 0x0100 +#define CR_RST 0x0080 +#define CR_ST 0x0020 +#define CR_STP 0x0010 +#define CR_RXEN 0x0008 +#define CR_RXDIS 0x0004 +#define CR_TXP 0x0002 +#define CR_HTX 0x0001 + +/* + * Data configuration register + */ +#define DCR_EXBUS 0x8000 +#define DCR_LBR 0x2000 +#define DCR_PO1 0x1000 +#define DCR_PO0 0x0800 +#define DCR_SBUS 0x0400 +#define DCR_USR1 0x0200 +#define DCR_USR0 0x0100 +#define DCR_WC1 0x0080 +#define DCR_WC0 0x0040 +#define DCR_DW 0x0020 +#define DCR_BMS 0x0010 +#define DCR_RFT1 0x0008 +#define DCR_RFT0 0x0004 +#define DCR_TFT1 0x0002 +#define DCR_TFT0 0x0001 + +/* data configuration register aliases */ +#define DCR_SYNC DCR_SBUS /* synchronous (memory cycle 2 clocks) */ +#define DCR_ASYNC 0 /* asynchronous (memory cycle 3 clocks) */ + +#define DCR_WAIT0 0 /* 0 wait states added */ +#define DCR_WAIT1 DCR_WC0 /* 1 wait state added */ +#define DCR_WAIT2 DCR_WC1 /* 2 wait states added */ +#define DCR_WAIT3 (DCR_WC1|DCR_WC0) /* 3 wait states added */ + +#define DCR_DW16 0 /* use 16-bit DMA accesses */ +#define DCR_DW32 DCR_DW /* use 32-bit DMA accesses */ + +#define DCR_DMAEF 0 /* DMA until TX/RX FIFO has emptied/filled */ +#define DCR_DMABLOCK DCR_BMS /* DMA until RX/TX threshold crossed */ + +#define DCR_RFT4 0 /* receive threshold 4 bytes */ +#define DCR_RFT8 DCR_RFT0 /* receive threshold 8 bytes */ +#define DCR_RFT16 DCR_RFT1 /* receive threshold 16 bytes */ +#define DCR_RFT24 (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */ + +#define DCR_TFT8 0 /* transmit threshold 8 bytes */ +#define DCR_TFT16 DCR_TFT0 /* transmit threshold 16 bytes */ +#define DCR_TFT24 DCR_TFT1 /* transmit threshold 24 bytes */ +#define DCR_TFT28 (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */ + +/* + * Receive control register + */ +#define RCR_ERR 0x8000 +#define RCR_RNT 0x4000 +#define RCR_BRD 0x2000 +#define RCR_PRO 0x1000 +#define RCR_AMC 0x0800 +#define RCR_LB1 0x0400 +#define RCR_LB0 0x0200 +#define RCR_MC 0x0100 +#define RCR_BC 0x0080 +#define RCR_LPKT 0x0040 +#define RCR_CRS 0x0020 +#define RCR_COL 0x0010 +#define RCR_CRCR 0x0008 +#define RCR_FAER 0x0004 +#define RCR_LBK 0x0002 +#define RCR_PRX 0x0001 + +/* + * Transmit control register + */ +#define TCR_PINT 0x8000 +#define TCR_POWC 0x4000 +#define TCR_CRCI 0x2000 +#define TCR_EXDIS 0x1000 +#define TCR_EXD 0x0400 +#define TCR_DEF 0x0200 +#define TCR_NCRS 0x0100 +#define TCR_CRSL 0x0080 +#define TCR_EXC 0x0040 +#define TCR_OWC 0x0020 +#define TCR_PMB 0x0008 +#define TCR_FU 0x0004 +#define TCR_BCM 0x0002 +#define TCR_PTX 0x0001 + +/* + * Interrupt mask register + */ +#define IMR_BREN 0x4000 +#define IMR_HBLEN 0x2000 +#define IMR_LCDEN 0x1000 +#define IMR_PINTEN 0x0800 +#define IMR_PRXEN 0x0400 +#define IMR_PTXEN 0x0200 +#define IMR_TXEREN 0x0100 +#define IMR_TCEN 0x0080 +#define IMR_RDEEN 0x0040 +#define IMR_RBEEN 0x0020 +#define IMR_RBAEEN 0x0010 +#define IMR_CRCEN 0x0008 +#define IMR_FAEEN 0x0004 +#define IMR_MPEN 0x0002 +#define IMR_RFOEN 0x0001 + +/* + * Interrupt status register + */ +#define ISR_BR 0x4000 +#define ISR_HBL 0x2000 +#define ISR_LCD 0x1000 +#define ISR_PINT 0x0800 +#define ISR_PKTRX 0x0400 +#define ISR_TXDN 0x0200 +#define ISR_TXER 0x0100 +#define ISR_TC 0x0080 +#define ISR_RDE 0x0040 +#define ISR_RBE 0x0020 +#define ISR_RBAE 0x0010 +#define ISR_CRC 0x0008 +#define ISR_FAE 0x0004 +#define ISR_MP 0x0002 +#define ISR_RFO 0x0001 + +/* + * Data configuration register 2 + */ +#define DCR2_EXPO3 0x8000 +#define DCR2_EXPO2 0x4000 +#define DCR2_EXPO1 0x2000 +#define DCR2_EXPO0 0x1000 +#define DCR2_HBDIS 0x0800 +#define DCR2_PH 0x0010 +#define DCR2_PCM 0x0004 +#define DCR2_PCNM 0x0002 +#define DCR2_RJCM 0x0001 + +/* + * Known values for the Silicon Revision Register. + * Note that DP83934 has revision 5 and seems to work. + */ + +#define SONIC_REVISION_B 4 +#define SONIC_REVISION_DP83934 5 +#define SONIC_REVISION_C 6 + +/* + ****************************************************************** + * * + * Transmit Buffer Management * + * * + ****************************************************************** + */ + +/* + * Transmit descriptor area entry. + * There is one transmit descriptor for each packet to be transmitted. + * Statically reserve space for up to MAXIMUM_FRAGS_PER_PACKET fragments + * per descriptor. + */ +#define MAXIMUM_FRAGS_PER_DESCRIPTOR 6 +struct TransmitDescriptor { + uint32_t status; + uint32_t pkt_config; + uint32_t pkt_size; + uint32_t frag_count; + + /* + * Packet fragment pointers + */ + struct TransmitDescriptorFragLink { + uint32_t frag_lsw; /* LSW of fragment address */ +#define frag_link frag_lsw + uint32_t frag_msw; /* MSW of fragment address */ + uint32_t frag_size; + } frag[MAXIMUM_FRAGS_PER_DESCRIPTOR]; + + /* + * Space for link if all fragment pointers are used. + */ + uint32_t link_pad; + + /* + * Extra RTEMS stuff + */ + struct TransmitDescriptor *next; /* Circularly-linked list */ + struct mbuf *mbufp; /* First mbuf in packet */ + volatile uint32_t *linkp; /* Pointer to un[xxx].link */ +}; +typedef struct TransmitDescriptor TransmitDescriptor_t; +typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t; + +/* + * Transmit Configuration. + * For standard Ethernet transmission, all bits in the transmit + * configuration field are set to 0. + */ +#define TDA_CONFIG_PINT 0x8000 +#define TDA_CONFIG_POWC 0x4000 +#define TDA_CONFIG_CRCI 0x2000 +#define TDA_CONFIG_EXDIS 0x1000 + +/* + * Transmit status + */ +#define TDA_STATUS_COLLISION_MASK 0xF800 +#define TDA_STATUS_COLLISION_SHIFT 11 +#define TDA_STATUS_EXD 0x0400 +#define TDA_STATUS_DEF 0x0200 +#define TDA_STATUS_NCRS 0x0100 +#define TDA_STATUS_CRSL 0x0080 +#define TDA_STATUS_EXC 0x0040 +#define TDA_STATUS_OWC 0x0020 +#define TDA_STATUS_PMB 0x0008 +#define TDA_STATUS_FU 0x0004 +#define TDA_STATUS_BCM 0x0002 +#define TDA_STATUS_PTX 0x0001 + +#define TDA_LINK_EOL 0x0001 +#define TDA_LINK_EOL_MASK 0xFFFE + + + +/* + ****************************************************************** + * * + * Receive Buffer Management * + * * + ****************************************************************** + */ + +/* + * Receive resource area entry. + * There is one receive resource entry for each receive buffer area (RBA). + * This driver allows only one packet per receive buffer area, so one + * receive resource entry corresponds to one correctly-received packet. + */ +struct ReceiveResource { + uint32_t buff_ptr_lsw; /* LSW of RBA address */ + uint32_t buff_ptr_msw; /* MSW of RBA address */ + uint32_t buff_wc_lsw; /* LSW of RBA size (16-bit words) */ + uint32_t buff_wc_msw; /* MSW of RBA size (16-bit words) */ +}; +typedef struct ReceiveResource ReceiveResource_t; +typedef volatile ReceiveResource_t *ReceiveResourcePointer_t; + +/* + * Receive descriptor area entry. + * There is one receive descriptor for each packet received. + */ +struct ReceiveDescriptor { + uint32_t status; + uint32_t byte_count; + uint32_t pkt_lsw; /* LSW of packet address */ + uint32_t pkt_msw; /* MSW of packet address */ + uint32_t seq_no; + uint32_t link; + uint32_t in_use; + + /* + * Extra RTEMS stuff + */ + volatile struct ReceiveDescriptor *next; /* Circularly-linked list */ + struct mbuf *mbufp; /* First mbuf in packet */ +}; +typedef struct ReceiveDescriptor ReceiveDescriptor_t; +typedef volatile ReceiveDescriptor_t *ReceiveDescriptorPointer_t; + +typedef struct { + uint32_t cep; /* CAM Entry Pointer */ + uint32_t cap0; /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */ + uint32_t cap1; /* CAM Address Port 1 xx-xx-YY-YY-xxxx */ + uint32_t cap2; /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */ + uint32_t ce; +} CamDescriptor_t; + +typedef volatile CamDescriptor_t *CamDescriptorPointer_t; + +/* + * Receive status + */ +#define RDA_STATUS_ERR 0x8800 +#define RDA_STATUS_RNT 0x4000 +#define RDA_STATUS_BRD 0x2000 +#define RDA_STATUS_PRO 0x1000 +#define RDA_STATUS_AMC 0x0800 +#define RDA_STATUS_LB1 0x0400 +#define RDA_STATUS_LB0 0x0200 +#define RDA_STATUS_MC 0x0100 +#define RDA_STATUS_BC 0x0080 +#define RDA_STATUS_LPKT 0x0040 +#define RDA_STATUS_CRS 0x0020 +#define RDA_STATUS_COL 0x0010 +#define RDA_STATUS_CRCR 0x0008 +#define RDA_STATUS_FAER 0x0004 +#define RDA_STATUS_LBK 0x0002 +#define RDA_STATUS_PRX 0x0001 + +#define RDA_LINK_EOL 0x0001 +#define RDA_LINK_EOL_MASK 0xFFFE +#define RDA_IN_USE 0x0000 /* SONIC has finished with the packet */ + /* and the driver can process it */ +#define RDA_FREE 0xFFFF /* SONIC can use it */ + +/* + * Attach routine + */ + +int rtems_sonic_driver_attach ( + struct rtems_bsdnet_ifconfig *config, + sonic_configuration_t *chip +); + +#ifdef CPU_U32_FIX +void ipalign(struct mbuf *m); +#endif + +#endif /* _SONIC_DP83932_ */ diff --git a/bsps/include/libchip/spi-flash-m25p40.h b/bsps/include/libchip/spi-flash-m25p40.h new file mode 100644 index 0000000000..2009b6fed3 --- /dev/null +++ b/bsps/include/libchip/spi-flash-m25p40.h @@ -0,0 +1,44 @@ +/*===============================================================*\ +| Project: SPI driver for M25P40 like spi flash device | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +\*===============================================================*/ +/* + * FIXME: currently, this driver only supports read/write accesses + * erase accesses are to be completed + */ + + +#ifndef _LIBCHIP_SPI_FLASH_M25P40_H +#define _LIBCHIP_SPI_FLASH_M25P40_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * pass one of these descriptor pointers to rtems_libi2c_register_drv + */ +extern rtems_libi2c_drv_t *spi_flash_m25p40_rw_driver_descriptor; + +extern rtems_libi2c_drv_t *spi_flash_m25p40_ro_driver_descriptor; + +#ifdef __cplusplus +} +#endif + +#endif /* _LIBCHIP_SPI_FLASH_M25P40_H */ diff --git a/bsps/include/libchip/spi-fram-fm25l256.h b/bsps/include/libchip/spi-fram-fm25l256.h new file mode 100644 index 0000000000..a2167a3074 --- /dev/null +++ b/bsps/include/libchip/spi-fram-fm25l256.h @@ -0,0 +1,44 @@ +/*===============================================================*\ +| Project: SPI driver for FM25L256 like spi fram device | ++-----------------------------------------------------------------+ +| Copyright (c) 2008 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +\*===============================================================*/ +/* + * FIXME: currently, this driver only supports read/write accesses + * erase accesses are to be completed + */ + + +#ifndef _LIBCHIP_SPI_FRAM_FM25L256_H +#define _LIBCHIP_SPI_FRAM_FM25L256_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * pass one of these descriptor pointers to rtems_libi2c_register_drv + */ +extern rtems_libi2c_drv_t *spi_fram_fm25l256_rw_driver_descriptor; + +extern rtems_libi2c_drv_t *spi_fram_fm25l256_ro_driver_descriptor; + +#ifdef __cplusplus +} +#endif + +#endif /* _LIBCHIP_SPI_FRAM_FM25L256_H */ diff --git a/bsps/include/libchip/spi-memdrv.h b/bsps/include/libchip/spi-memdrv.h new file mode 100644 index 0000000000..ed4aa55b6f --- /dev/null +++ b/bsps/include/libchip/spi-memdrv.h @@ -0,0 +1,90 @@ +/*===============================================================*\ +| Project: SPI driver for spi memory devices | ++-----------------------------------------------------------------+ +| Copyright (c) 2008 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +\*===============================================================*/ + + +#ifndef _LIBCHIP_SPI_MEMDRV_H +#define _LIBCHIP_SPI_MEMDRV_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code spi_memdrv_write +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| write a block of data to memory | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, /* major device number */ + rtems_device_major_number minor, /* minor device number */ + void *arg /* ptr to write argument struct */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code spi_memdrv_read +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| read a block of data from memory | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, /* major device number */ + rtems_device_major_number minor, /* minor device number */ + void *arg /* ptr to read argument struct */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ + + typedef struct { + uint32_t baudrate; /* tfr rate, bits per second */ + bool erase_before_program; + uint32_t empty_state; /* value of erased cells */ + uint32_t page_size; /* programming page size in byte */ + uint32_t sector_size; /* erase sector size in byte */ + uint32_t mem_size; /* total capacity in byte */ + } spi_memdrv_param_t; + + typedef struct { + rtems_libi2c_drv_t libi2c_drv_entry; /* general i2c/spi params */ + spi_memdrv_param_t spi_memdrv_param; /* private parameters */ + } spi_memdrv_t; + + extern rtems_driver_address_table spi_memdrv_rw_ops; + extern rtems_driver_address_table spi_memdrv_ro_ops; + +#ifdef __cplusplus +} +#endif + +#endif /* _LIBCHIP_SPI_MEMDRV_H */ diff --git a/bsps/include/libchip/spi-sd-card.h b/bsps/include/libchip/spi-sd-card.h new file mode 100644 index 0000000000..77e905a155 --- /dev/null +++ b/bsps/include/libchip/spi-sd-card.h @@ -0,0 +1,86 @@ +/** + * @file + * + * @brief SD Card LibI2C driver. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBI2C_SD_CARD_H +#define LIBI2C_SD_CARD_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define SD_CARD_IDLE_TOKEN 0xff + +/** + * 1 idle token before command + * 6 bytes for the command + * 1 to 8 bytes for response start (N_CR) + * 1 to 2 bytes for response + * 1 idle token after command (minimum N_RC) + */ +#define SD_CARD_COMMAND_SIZE 18 + +#define SD_CARD_TRANSFER_MODE_DEFAULT { .baudrate = 400000, .bits_per_char = 8, .lsb_first = FALSE, .clock_inv = FALSE, .clock_phs = FALSE, .idle_char = SD_CARD_IDLE_TOKEN } + +#define SD_CARD_COMMAND_DEFAULT { \ + SD_CARD_IDLE_TOKEN, \ + 0x40, 0, 0, 0, 0, 0x95, \ + SD_CARD_IDLE_TOKEN, SD_CARD_IDLE_TOKEN, \ + SD_CARD_IDLE_TOKEN, SD_CARD_IDLE_TOKEN, \ + SD_CARD_IDLE_TOKEN, SD_CARD_IDLE_TOKEN, \ + SD_CARD_IDLE_TOKEN, SD_CARD_IDLE_TOKEN, \ + SD_CARD_IDLE_TOKEN, SD_CARD_IDLE_TOKEN, \ + SD_CARD_IDLE_TOKEN \ +} + +/* Default speed = 400kbps, default timeout = 100ms, n_ac_max is in bytes */ +#define SD_CARD_N_AC_MAX_DEFAULT 5000 + +typedef struct { + const char *device_name; + rtems_device_minor_number bus; + rtems_libi2c_tfr_mode_t transfer_mode; + uint8_t command [SD_CARD_COMMAND_SIZE]; + uint8_t response [SD_CARD_COMMAND_SIZE]; + int response_index; + uint32_t n_ac_max; + uint32_t block_number; + uint32_t block_size; + uint32_t block_size_shift; + bool busy; + bool verbose; + bool schedule_if_busy; + uint32_t retries; +} sd_card_driver_entry; + +extern sd_card_driver_entry sd_card_driver_table []; + +extern size_t sd_card_driver_table_size; + +rtems_status_code sd_card_register( void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBI2C_SD_CARD_H */ diff --git a/bsps/include/libchip/wd80x3.h b/bsps/include/libchip/wd80x3.h new file mode 100644 index 0000000000..b4aa12e735 --- /dev/null +++ b/bsps/include/libchip/wd80x3.h @@ -0,0 +1,139 @@ +/** + * @file + * + * @ingroup i386_pc386 + * + * @brief DP8390 Ethernet controller definitions. + */ + +/* + * Information about the DP8390 Ethernet controller. + */ + +#ifndef __BSP_WD80x3_h +#define __BSP_WD80x3_h + +/* Register descriptions */ +/* Controller DP8390. */ + +#define DATAPORT 0x10 /* Port Window. */ +#define RESET 0x1f /* Issue a read for reset */ +#define W83CREG 0x00 /* I/O port definition */ +#define ADDROM 0x08 + +/* page 0 read or read/write registers */ + +#define CMDR 0x00+RO +#define CLDA0 0x01+RO /* current local dma addr 0 for read */ +#define CLDA1 0x02+RO /* current local dma addr 1 for read */ +#define BNRY 0x03+RO /* boundary reg for rd and wr */ +#define TSR 0x04+RO /* tx status reg for rd */ +#define NCR 0x05+RO /* number of collision reg for rd */ +#define FIFO 0x06+RO /* FIFO for rd */ +#define ISR 0x07+RO /* interrupt status reg for rd and wr */ +#define CRDA0 0x08+RO /* current remote dma address 0 for rd */ +#define CRDA1 0x09+RO /* current remote dma address 1 for rd */ +#define RSR 0x0C+RO /* rx status reg for rd */ +#define CNTR0 0x0D+RO /* tally cnt 0 for frm alg err for rd */ +#define CNTR1 RO+0x0E /* tally cnt 1 for crc err for rd */ +#define CNTR2 0x0F+RO /* tally cnt 2 for missed pkt for rd */ + +/* page 0 write registers */ + +#define PSTART 0x01+RO /* page start register */ +#define PSTOP 0x02+RO /* page stop register */ +#define TPSR 0x04+RO /* tx start page start reg */ +#define TBCR0 0x05+RO /* tx byte count 0 reg */ +#define TBCR1 0x06+RO /* tx byte count 1 reg */ +#define RSAR0 0x08+RO /* remote start address reg 0 */ +#define RSAR1 0x09+RO /* remote start address reg 1 */ +#define RBCR0 0x0A+RO /* remote byte count reg 0 */ +#define RBCR1 0x0B+RO /* remote byte count reg 1 */ +#define RCR 0x0C+RO /* rx configuration reg */ +#define TCR 0x0D+RO /* tx configuration reg */ +#define DCR RO+0x0E /* data configuration reg */ +#define IMR 0x0F+RO /* interrupt mask reg */ + +/* page 1 registers */ + +#define PAR 0x01+RO /* physical addr reg base for rd and wr */ +#define CURR 0x07+RO /* current page reg for rd and wr */ +#define MAR 0x08+RO /* multicast addr reg base fro rd and WR */ +#define MARsize 8 /* size of multicast addr space */ + +/*-----W83CREG command bits-----*/ +#define MSK_RESET 0x80 /* W83CREG masks */ +#define MSK_ENASH 0x40 +#define MSK_DECOD 0x3F /* memory decode bits, corresponding */ + /* to SA 18-13. SA 19 assumed to be 1 */ + +/*-----CMDR command bits-----*/ +#define MSK_STP 0x01 /* stop the chip */ +#define MSK_STA 0x02 /* start the chip */ +#define MSK_TXP 0x04 /* initial txing of a frm */ +#define MSK_RRE 0x08 /* remote read */ +#define MSK_RWR 0x10 /* remote write */ +#define MSK_RD2 0x20 /* no DMA used */ +#define MSK_PG0 0x00 /* select register page 0 */ +#define MSK_PG1 0x40 /* select register page 1 */ +#define MSK_PG2 0x80 /* select register page 2 */ + +/*-----ISR and TSR status bits-----*/ +#define MSK_PRX 0x01 /* rx with no error */ +#define MSK_PTX 0x02 /* tx with no error */ +#define MSK_RXE 0x04 /* rx with error */ +#define MSK_TXE 0x08 /* tx with error */ +#define MSK_OVW 0x10 /* overwrite warning */ +#define MSK_CNT 0x20 /* MSB of one of the tally counters is set */ +#define MSK_RDC 0x40 /* remote dma completed */ +#define MSK_RST 0x80 /* reset state indicator */ + +/*-----DCR command bits-----*/ +#define MSK_WTS 0x01 /* word transfer mode selection */ +#define MSK_BOS 0x02 /* byte order selection */ +#define MSK_LAS 0x04 /* long addr selection */ +#define MSK_BMS 0x08 /* burst mode selection */ +#define MSK_ARM 0x10 /* autoinitialize remote */ +#define MSK_FT00 0x00 /* burst lrngth selection */ +#define MSK_FT01 0x20 /* burst lrngth selection */ +#define MSK_FT10 0x40 /* burst lrngth selection */ +#define MSK_FT11 0x60 /* burst lrngth selection */ + +/*-----RCR command bits-----*/ +#define MSK_SEP 0x01 /* save error pkts */ +#define MSK_AR 0x02 /* accept runt pkt */ +#define MSK_AB 0x04 /* 8390 RCR */ +#define MSK_AM 0x08 /* accept multicast */ +#define MSK_PRO 0x10 /* accept all pkt with physical adr */ +#define MSK_MON 0x20 /* monitor mode */ + +/*-----TCR command bits-----*/ +#define MSK_CRC 0x01 /* inhibit CRC, do not append crc */ +#define MSK_LOOP 0x02 /* set loopback mode */ +#define MSK_BCST 0x04 /* Accept broadcasts */ +#define MSK_LB01 0x06 /* encoded loopback control */ +#define MSK_ATD 0x08 /* auto tx disable */ +#define MSK_OFST 0x10 /* collision offset enable */ + +/*-----receive status bits-----*/ +#define SMK_PRX 0x01 /* rx without error */ +#define SMK_CRC 0x02 /* CRC error */ +#define SMK_FAE 0x04 /* frame alignment error */ +#define SMK_FO 0x08 /* FIFO overrun */ +#define SMK_MPA 0x10 /* missed pkt */ +#define SMK_PHY 0x20 /* physical/multicase address */ +#define SMK_DIS 0x40 /* receiver disable. set in monitor mode */ +#define SMK_DEF 0x80 /* deferring */ + +/*-----transmit status bits-----*/ +#define SMK_PTX 0x01 /* tx without error */ +#define SMK_DFR 0x02 /* non deferred tx */ +#define SMK_COL 0x04 /* tx collided */ +#define SMK_ABT 0x08 /* tx abort because of excessive collisions */ +#define SMK_CRS 0x10 /* carrier sense lost */ +#define SMK_FU 0x20 /* FIFO underrun */ +#define SMK_CDH 0x40 /* collision detect heartbeat */ +#define SMK_OWC 0x80 /* out of window collision */ + +#endif +/* end of include */ diff --git a/bsps/include/libchip/z85c30.h b/bsps/include/libchip/z85c30.h new file mode 100644 index 0000000000..656d50ea1c --- /dev/null +++ b/bsps/include/libchip/z85c30.h @@ -0,0 +1,83 @@ +/** + * @file + * + * This include file contains all console driver definitions for the + * Zilog z85c30. + */ + +/* + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __Z85C30_H +#define __Z85C30_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Driver function table + */ + +extern const console_fns z85c30_fns; +extern const console_fns z85c30_fns_polled; + +/* + * Flow control function tables + */ + +extern const console_flow z85c30_flow_RTSCTS; +extern const console_flow z85c30_flow_DTRCTS; + +/* + * Default register access routines + */ + +uint8_t z85c30_get_register( /* registers are byte-wide */ + uintptr_t ulCtrlPort, + uint8_t ucRegNum +); + +void z85c30_set_register( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint8_t ucData +); + +uint8_t z85c30_get_data( + uint32_t ulDataPort +); + +void z85c30_set_data( + uint32_t ulDataPort, + uint8_t ucData +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/mpci.h b/bsps/include/mpci.h new file mode 100644 index 0000000000..cc7c5826de --- /dev/null +++ b/bsps/include/mpci.h @@ -0,0 +1,56 @@ +/* mpci.h + * + * This include file contains all the renaming necessary to + * have an application use the Shared Memory Driver as its + * sole mechanism for MPCI. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SHM_MPCI_h +#define __SHM_MPCI_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define MPCI_Initialization( _configuration ) \ + Shm_Initialization( _configuration ) + +#define MPCI_Get_packet( _the_packet ) \ + Shm_Get_packet( _the_packet ) + +#define MPCI_Return_packet( _the_packet ) \ + Shm_Return_packet( _the_packet ) + +#define MPCI_Receive_packet( _the_packet ) \ + Shm_Receive_packet( _the_packet ) + +#define MPCI_Send_packet( _destination, _the_packet ) \ + Shm_Send_packet( _destination, _the_packet ) + +/* Unnecessary... mapped in shm_driver.h +#define MPCI_Fatal( _the_error ) \ + Shm_Fatal( _the_error ) +*/ + +#define MPCI_Enable_statistics() + +#define MPCI_Print_statistics() \ + Shm_Print_statistics() + +/* no need to rename the MPCI_Table either */ + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/include/rtems/umon.h b/bsps/include/rtems/umon.h new file mode 100644 index 0000000000..d25a7818dd --- /dev/null +++ b/bsps/include/rtems/umon.h @@ -0,0 +1,68 @@ +/* + * umon.h - RTEMS specific interface to MicroMonitor. + * + * COPYRIGHT (c) 1989-2009. + * On-Line Applications Research Corporation (OAR). + * + * Modified by Fernando Nicodemos + * from NCB - Sistemas Embarcados Ltda. (Brazil) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ + +#ifndef __rtems_umon_h +#define __rtems_umon_h + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Connect RTEMS Application to MicroMonitor + * + * RTEMS uMonitor wrapper for monConnect(). This will deal with the + * getting MONCOMPTR as well as providing the locking routines. + */ +void rtems_umon_connect(void); + +/** + * @brief Obtain BSP specific pointer to MicroMonitor + * + * BSP specific routine to help when calling monConnect(). This + * returns the value known to uMon as MONCOMPTR. + * + * @return This method returns the address of the base area of MicroMonitor. + */ +void *rtems_bsp_get_umon_monptr(void); + +/** + * @brief Initialize the TFS-RTEMS file system + * + * This method initializes and mounts the TFS-RTEMS file system. + * + * @param[in] path is the mount point + * + * @return This method returns 0 on success. + */ +int rtems_initialize_tfs_filesystem( + const char *path +); + +/** + * @brief Read from MicroMonitor Port + * + * This method reads a character from the MicroMonitor console. + * + * @return This method returns a character. + */ +int umoncons_poll_read(int minor); + +#ifdef __cplusplus +} +#endif + +#endif /* __rtems_umon_h */ diff --git a/bsps/include/rtems/zilog/z8036.h b/bsps/include/rtems/zilog/z8036.h new file mode 100644 index 0000000000..fea1493905 --- /dev/null +++ b/bsps/include/rtems/zilog/z8036.h @@ -0,0 +1,106 @@ +/** + * @file + * + * @brief Zilog Z8036 Counter/Timer/IO Chip + * + * This include file defines information related to a Zilog Z8036 + * Counter/Timer/IO Chip. It is a memory mapped part. + * + * @note This file shares as much as possible with the include file + * for the Z8536 via z8x36.h. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_ZILOG_Z8036_H +#define _RTEMS_ZILOG_Z8036_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* macros */ + +#define Z8036( ptr ) ((volatile struct z8036_map *)(ptr)) + +#define Z8x36_STATE0 ( z8036 ) \ + { /*char *garbage = *(Z8036(z8036))->???; */ } + + +#define Z8x36_WRITE( z8036, reg, data ) \ + (Z8036(z8036))->reg = (data) + + +#define Z8x36_READ( z8036, reg, data ) \ + (Z8036(z8036))->reg = (data) + +/* structures */ + +struct z8036_map { +/* MAIN CONTROL REGISTERS (0x00-0x07) */ + uint8_t MASTER_INTR; /* Master Interrupt Ctl Reg */ + uint8_t MASTER_CFG; /* Master Configuration Ctl Reg */ + uint8_t PORTA_VECTOR; /* Port A - Interrupt Vector */ + uint8_t PORTB_VECTOR; /* Port B - Interrupt Vector */ + uint8_t CNT_TMR_VECTOR; /* Counter/Timer Interrupt Vector */ + uint8_t PORTC_DATA_POLARITY; /* Port C - Data Path Polarity */ + uint8_t PORTC_DIRECTION; /* Port C - Data Direction */ + uint8_t PORTC_SPECIAL_IO_CTL; /* Port C - Special IO Control */ +/* MOST OFTEN ACCESSED REGISTERS (0x08 - 0x0f) */ + uint8_t PORTA_CMD_STATUS; /* Port A - Command Status Reg */ + uint8_t PORTB_CMD_STATUS; /* Port B - Command Status Reg */ + uint8_t CT1_CMD_STATUS; /* Ctr/Timer 1 - Command Status Reg */ + uint8_t CT2_CMD_STATUS; /* Ctr/Timer 2 - Command Status Reg */ + uint8_t CT3_CMD_STATUS; /* Ctr/Timer 3 - Command Status Reg */ + uint8_t PORTA_DATA; /* Port A - Data */ + uint8_t PORTB_DATA; /* Port B - Data */ + uint8_t PORTC_DATA; /* Port C - Data */ +/* COUNTER/TIMER RELATED REGISTERS (0x10-0x1f) */ + uint8_t CT1_CUR_CNT_MSB; /* Ctr/Timer 1 - Current Count (MSB) */ + uint8_t CT1_CUR_CNT_LSB; /* Ctr/Timer 1 - Current Count (LSB) */ + uint8_t CT2_CUR_CNT_MSB; /* Ctr/Timer 2 - Current Count (MSB) */ + uint8_t CT2_CUR_CNT_LSB; /* Ctr/Timer 2 - Current Count (LSB) */ + uint8_t CT3_CUR_CNT_MSB; /* Ctr/Timer 3 - Current Count (MSB) */ + uint8_t CT3_CUR_CNT_LSB; /* Ctr/Timer 3 - Current Count (LSB) */ + uint8_t CT1_TIME_CONST_MSB; /* Ctr/Timer 1 - Time Constant (MSB) */ + uint8_t CT1_TIME_CONST_LSB; /* Ctr/Timer 1 - Time Constant (LSB) */ + uint8_t CT2_TIME_CONST_MSB; /* Ctr/Timer 2 - Time Constant (MSB) */ + uint8_t CT2_TIME_CONST_LSB; /* Ctr/Timer 2 - Time Constant (LSB) */ + uint8_t CT3_TIME_CONST_MSB; /* Ctr/Timer 3 - Time Constant (MSB) */ + uint8_t CT3_TIME_CONST_LSB; /* Ctr/Timer 3 - Time Constant (LSB) */ + uint8_t CT1_MODE_SPEC; /* Ctr/Timer 1 - Mode Specification */ + uint8_t CT2_MODE_SPEC; /* Ctr/Timer 2 - Mode Specification */ + uint8_t CT3_MODE_SPEC; /* Ctr/Timer 3 - Mode Specification */ + uint8_t CURRENT_VECTOR; /* Current Vector */ +/* PORT A SPECIFICATION REGISTERS (0x20 -0x27) */ + uint8_t PORTA_MODE; /* Port A - Mode Specification */ + uint8_t PORTA_HANDSHAKE; /* Port A - Handshake Specification */ + uint8_t PORTA_DATA_POLARITY; /* Port A - Data Path Polarity */ + uint8_t PORTA_DIRECTION; /* Port A - Data Direction */ + uint8_t PORTA_SPECIAL_IO_CTL; /* Port A - Special IO Control */ + uint8_t PORTA_PATT_POLARITY; /* Port A - Pattern Polarity */ + uint8_t PORTA_PATT_TRANS; /* Port A - Pattern Transition */ + uint8_t PORTA_PATT_MASK; /* Port A - Pattern Mask */ +/* PORT B SPECIFICATION REGISTERS (0x28-0x2f) */ + uint8_t PORTB_MODE; /* Port B - Mode Specification */ + uint8_t PORTB_HANDSHAKE; /* Port B - Handshake Specification */ + uint8_t PORTB_DATA_POLARITY; /* Port B - Data Path Polarity */ + uint8_t PORTB_DIRECTION; /* Port B - Data Direction */ + uint8_t PORTB_SPECIAL_IO_CTL; /* Port B - Special IO Control */ + uint8_t PORTB_PATT_POLARITY; /* Port B - Pattern Polarity */ + uint8_t PORTB_PATT_TRANS; /* Port B - Pattern Transition */ + uint8_t PORTB_PATT_MASK; /* Port B - Pattern Mask */ +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/rtems/zilog/z8530.h b/bsps/include/rtems/zilog/z8530.h new file mode 100644 index 0000000000..161b9a022c --- /dev/null +++ b/bsps/include/rtems/zilog/z8530.h @@ -0,0 +1,97 @@ +/** + * @file + * + * @brief Information Related to a Zilog Z8530 SCC Chip + * + * This include file defines information related to a Zilog Z8530 + * SCC Chip. It is a IO mapped part. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_ZILOG_Z8530_H +#define _RTEMS_ZILOG_Z8530_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* macros */ + +#define VOL8( ptr ) ((volatile uint8_t *)(ptr)) + +#define Z8x30_STATE0 ( z8530 ) \ + { char *garbage; \ + (garbage) = *(VOL8(z8530)) \ + } + +#define Z8x30_WRITE_CONTROL( z8530, reg, data ) \ + *(VOL8(z8530)) = (reg); \ + *(VOL8(z8530)) = (data) + +#define Z8x30_READ_CONTROL( z8530, reg, data ) \ + *(VOL8(z8530)) = (reg); \ + (data) = *(VOL8(z8530)) + +#define Z8x30_WRITE_DATA( z8530, data ) \ + *(VOL8(z8530)) = (data); + +#define Z8x30_READ_DATA( z8530, data ) \ + (data) = *(VOL8(z8530)); + + +/* RR_0 Bit Definitions */ + +#define RR_0_TX_BUFFER_EMPTY 0x04 +#define RR_0_RX_DATA_AVAILABLE 0x01 + +/* read registers */ + +#define RR_0 0x00 +#define RR_1 0x01 +#define RR_2 0x02 +#define RR_3 0x03 +#define RR_4 0x04 +#define RR_5 0x05 +#define RR_6 0x06 +#define RR_7 0x07 +#define RR_8 0x08 +#define RR_9 0x09 +#define RR_10 0x0A +#define RR_11 0x0B +#define RR_12 0x0C +#define RR_13 0x0D +#define RR_14 0x0E +#define RR_15 0x0F + +/* write registers */ + +#define WR_0 0x00 +#define WR_1 0x01 +#define WR_2 0x02 +#define WR_3 0x03 +#define WR_4 0x04 +#define WR_5 0x05 +#define WR_6 0x06 +#define WR_7 0x07 +#define WR_8 0x08 +#define WR_9 0x09 +#define WR_10 0x0A +#define WR_11 0x0B +#define WR_12 0x0C +#define WR_13 0x0D +#define WR_14 0x0E +#define WR_15 0x0F + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/shm_driver.h b/bsps/include/shm_driver.h new file mode 100644 index 0000000000..cb94cec0cb --- /dev/null +++ b/bsps/include/shm_driver.h @@ -0,0 +1,542 @@ +/* shm_driver.h + * + * This include file contains all the constants, structures, + * and global variables for this RTEMS based shared memory + * communications interface driver. + * + * Processor board dependencies are in other files. + * + * COPYRIGHT (c) 1989-2007. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SHM_h +#define __SHM_h + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* The information contained in the Node Status, Locked Queue, and + * Envelope Control Blocks must be maintained in a NEUTRAL format. + * Currently the neutral format may be selected as big or little + * endian by simply defining either NEUTRAL_BIG or NEUTRAL_LITTLE. + * + * It is CRITICAL to note that the neutral format can ONLY be + * changed by modifying this file and recompiling the ENTIRE + * SHM driver including ALL target specific support files. + * + * The following table details the memory contents for the endian + * field of the Node Status Control Block in the various + * data format configurations (data is in hexadecimal): + * + * NEUTRAL NATIVE BYTE 0 BYTE 1 BYTE 2 BYTE 3 + * ======= ====== ====== ====== ====== ====== + * BIG BIG 00 00 00 01 + * BIG LITTLE 10 00 00 00 + * LITTLE BIG 01 00 00 00 + * LITTLE LITTLE 00 00 00 10 + * + * + * NOTE: XXX + * PORTABILITY OF LOCKING INSTRUCTIONS + * =================================== + * The locking mechanism described below is not + * general enough. Where the hardware supports + * it we should use "atomic swap" instructions + * so the values in the lock can be tailored to + * support a CPU with only weak atomic memory + * instructions. There are combinations of + * CPUs with inflexible atomic memory instructions + * which appear to be incompatible. For example, + * the SPARClite instruction uses a byte which is + * 0xFF when locked. The PA-RISC uses 1 to indicate + * locked and 0 when unlocked. These CPUs appear to + * have incompatible lock instructions. But + * they could be used in a heterogenous system + * with does not mix SPARCs and PA-RISCs. For + * example, the i386 and SPARC or i386 and SPARC + * could work together. The bottom line is that + * not every CPU will work together using this + * locking scheme. There are supposed to be + * algorithms to do this without hardware assist + * and one of these should be incorporated into + * the shared memory driver. + * + * The most flexible scheme using the instructions + * of the various CPUs for efficiency would be to use + * "atomic swaps" wherever possible. Make the lock + * and unlock configurable much like BIG vs LITTLE + * endian use of shared memory is now. The values + * of the lock could then reflect the "worst" + * CPU in a system. This still results in mixes + * of CPUs which are incompatible. + * + * The current locking mechanism is based upon the MC68020 + * "tas" instruction which is atomic. All ports to other CPUs + * comply with the restrictive placement of lock bit by this + * instruction. The lock bit is the most significant bit in a + * big-endian uint32_t . On other processors, the lock is + * typically implemented via an atomic swap or atomic modify + * bits type instruction. + */ + +#define NEUTRAL_BIG + +#ifdef NEUTRAL_BIG +#define SHM_BIG 0x00000001 +#define SHM_LITTLE 0x10000000 +#endif + +#ifdef NEUTRAL_LITTLE +#define SHM_BIG 0x01000000 +#define SHM_LITTLE 0x00000010 +#endif + +/* + * The following are the values used to fill in the lock field. Some CPUs + * are able to write only a single value into field. By making the + * lock and unlock values configurable, CPUs which support "atomic swap" + * instructions can generally be made to work in any heterogeneous + * configuration. However, it is possible for two CPUs to be incompatible + * in regards to the lock field values. This occurs when two CPUs + * which write only a single value to the field are used in a system + * but the two CPUs write different incompatible values. + * + * NOTE: The following is a first attempt at defining values which + * have a chance at working together. The m68k should use + * chk2 instead of tas to be less restrictive. Target endian + * problems (like the Force CPU386 which has (broken) big endian + * view of the VMEbus address space) are not addressed yet. + */ + +#if defined(__mc68000__) +#define SHM_LOCK_VALUE 0x80000000 +#define SHM_UNLOCK_VALUE 0 +#define SHM_LOCK_VALUE 0x80000000 +#define SHM_UNLOCK_VALUE 0 +#elif defined(__i386__) +#define SHM_LOCK_VALUE 0x80000000 +#define SHM_UNLOCK_VALUE 0 +#elif defined(__mips__) +#define SHM_LOCK_VALUE 0x80000000 +#define SHM_UNLOCK_VALUE 0 +#elif defined(__hppa__) +#define SHM_LOCK_VALUE 0 +#define SHM_UNLOCK_VALUE 1 +#elif defined(__PPC__) +#define SHM_LOCK_VALUE 1 +#define SHM_UNLOCK_VALUE 0 +#elif defined(__unix__) +#define SHM_LOCK_VALUE 0 +#define SHM_UNLOCK_VALUE 1 +#elif defined(_AM29K) +#define SHM_LOCK_VALUE 0 +#define SHM_UNLOCK_VALUE 1 +#elif defined(__nios2__) +#define SHM_LOCK_VALUE 1 +#define SHM_UNLOCK_VALUE 0 +#elif defined(__sparc__) +#define SHM_LOCK_VALUE 1 +#define SHM_UNLOCK_VALUE 0 +#elif defined(no_cpu) /* for this values are irrelevant */ +#define SHM_LOCK_VALUE 1 +#define SHM_UNLOCK_VALUE 0 +#else +#error "shm_driver.h - no SHM_LOCK_VALUE defined for this CPU architecture" +#endif + +#define Shm_Convert( value ) \ + ((Shm_Configuration->convert) ? \ + (*Shm_Configuration->convert)(value) : (value)) + +/* constants */ + +#define SHM_MASTER 1 /* master initialization node */ +#define SHM_FIRST_NODE 1 + +/* size constants */ + +#define KILOBYTE (1024) +#define MEGABYTE (1024*1024) + +/* inter-node interrupt values */ + +#define NO_INTERRUPT 0 /* used for polled nodes */ +#define BYTE 1 +#define WORD 2 +#define LONG 4 + +/* operational mode constants -- used in SHM Configuration Table */ +#define POLLED_MODE 0 +#define INTR_MODE 1 + +/* error codes */ + +#define NO_ERROR 0 +#define SHM_NO_FREE_PKTS 0xf0000 + +/* null pointers of different types */ + +#define NULL_ENV_CB ((Shm_Envelope_control *) 0) +#define NULL_CONVERT 0 + +/* + * size of stuff before preamble in envelope. + * It must be a constant since we will use it to generate MAX_PACKET_SIZE + */ + +#define SHM_ENVELOPE_PREFIX_OVERHEAD (4 * sizeof(vol_u32)) + +/* + * The following is adjusted so envelopes are MAX_ENVELOPE_SIZE bytes long. + * It must be >= RTEMS_MINIMUM_PACKET_SIZE in mppkt.h. + */ + +#ifndef MAX_ENVELOPE_SIZE +#define MAX_ENVELOPE_SIZE 0x180 +#endif + +#define MAX_PACKET_SIZE (MAX_ENVELOPE_SIZE - \ + SHM_ENVELOPE_PREFIX_OVERHEAD + \ + sizeof(Shm_Envelope_preamble) + \ + sizeof(Shm_Envelope_postamble)) + + +/* constants pertinent to Locked Queue routines */ + +#define LQ_UNLOCKED SHM_UNLOCK_VALUE +#define LQ_LOCKED SHM_LOCK_VALUE + +/* constants related to the Free Envelope Pool */ + +#define FREE_ENV_POOL 0 +#define FREE_ENV_CB (&Shm_Locked_queues[ FREE_ENV_POOL ]) + +/* The following are important when dealing with + * the shared memory communications interface area. + * + * NOTE: The starting address and length of the shared memory + * is defined in a system dependent file. + */ + +#define START_NS_CBS ((void *)Shm_Configuration->base) +#define START_LQ_CBS ((START_NS_CBS) + \ + ( (sizeof (Shm_Node_status_control)) * (SHM_MAXIMUM_NODES + 1) ) ) +#define START_ENVELOPES ( ((void *) START_LQ_CBS) + \ + ( (sizeof (Shm_Locked_queue_Control)) * (SHM_MAXIMUM_NODES + 1) ) ) +#define END_SHMCI_AREA ( (void *) START_ENVELOPES + \ + ( (sizeof (Shm_Envelope_control)) * Shm_Maximum_envelopes ) ) +#define END_SHARED_MEM (START_NS_CBS+Shm_Configuration->length) + +/* macros */ + +#define Shm_Is_master_node() \ + ( SHM_MASTER ==_Configuration_MP_table-> node ) + +#define Shm_Free_envelope( ecb ) \ + Shm_Locked_queue_Add( FREE_ENV_CB, (ecb) ) +#define Shm_Allocate_envelope() \ + Shm_Locked_queue_Get(FREE_ENV_CB) + +#define Shm_Initialize_receive_queue(node) \ + Shm_Locked_queue_Initialize( &Shm_Locked_queues[node], node ) + +#define Shm_Append_to_receive_queue(node, ecb) \ + Shm_Locked_queue_Add( &Shm_Locked_queues[node], (ecb) ) + +#define Shm_Envelope_control_to_packet_prefix_pointer(ecb) \ + ((void *)(ecb)->packet) + +#define Shm_Packet_prefix_to_envelope_control_pointer( pkt ) \ + ((Shm_Envelope_control *)((uint8_t*)(pkt) - \ + (sizeof(Shm_Envelope_preamble) + SHM_ENVELOPE_PREFIX_OVERHEAD))) + +#define Shm_Build_preamble(ecb, node) \ + (ecb)->Preamble.endian = Shm_Configuration->format + +#define Shm_Build_postamble( ecb ) + +/* volatile types */ + +typedef volatile uint8_t vol_u8; +typedef volatile uint32_t vol_u32; + +/* shm control information */ + +struct shm_info { + vol_u32 not_currently_used_0; + vol_u32 not_currently_used_1; + vol_u32 not_currently_used_2; + vol_u32 not_currently_used_3; +}; + +typedef struct { + /*byte start_of_text;*/ + vol_u32 endian; + vol_u32 not_currently_used_0; + vol_u32 not_currently_used_1; + vol_u32 not_currently_used_2; +} Shm_Envelope_preamble; + +typedef struct { +} Shm_Envelope_postamble; + +/* WARNING! If you change this structure, don't forget to change + * SHM_ENVELOPE_PREFIX_OVERHEAD and + * Shm_Packet_prefix_to_envelope_control_pointer() above. + */ + +/* This comment block describes the contents of each field + * of the Envelope Control Block: + * + * next - The index of the next envelope on this queue. + * queue - The index of the queue this envelope is on. + * index - The index of this envelope. + * Preamble - Generic packet preamble. One day this structure + * could be enhanced to contain routing information. + * packet - RTEMS MPCI packet. Untouched by SHM Driver + * other than copying and format conversion as + * documented in the RTEMS User's Guide. + * Postamble - Generic packet postamble. One day this structure + * could be enhanced to contain checksum information. + */ + +typedef struct { + vol_u32 next; /* next envelope on queue */ + vol_u32 queue; /* queue on which this resides */ + vol_u32 index; /* index into array of envelopes*/ + vol_u32 pad0; /* insure the next one is aligned */ + Shm_Envelope_preamble Preamble; /* header information */ + vol_u8 packet[MAX_PACKET_SIZE]; /* RTEMS INFO */ + Shm_Envelope_postamble Postamble;/* trailer information */ +} Shm_Envelope_control; + +/* This comment block describes the contents of each field + * of the Locked Queue Control Block: + * + * lock - Lock used to insure mutually exclusive access. + * front - Index of first envelope on queue. This field + * is used to remove head of queue (receive). + * rear - Index of last envelope on queue. This field + * is used to add evelope to queue (send). + * owner - The node number of the recipient (owning) node. + * RTEMS does not use the node number zero (0). + * The zero node is used by the SHM Driver for the + * Free Envelope Queue shared by all nodes. + */ + +typedef struct { + vol_u32 lock; /* lock field for this queue */ + vol_u32 front; /* first envelope on queue */ + vol_u32 rear; /* last envelope on queue */ + vol_u32 owner; /* receiving (i.e. owning) node */ +} Shm_Locked_queue_Control; + +/* This comment block describes the contents of each field + * of the Node Status Control Block: + * + * status - Node status. Current values are Pending Initialization, + * Initialization Complete, and Active Node. Other values + * could be added to enhance fault tolerance. + * error - Zero if the node has not failed. Otherwise, + * this field contains a status indicating the + * failure reason. + * int_address, int_value, and int_length + * - These field are the Interrupt Information table + * for this node in neutral format. This is how + * each node knows how to generate interrupts. + */ + +typedef struct { + vol_u32 status; /* node status information */ + vol_u32 error; /* fatal error code */ + vol_u32 int_address; /* write here for interrupt */ + vol_u32 int_value; /* this value causes interrupt */ + vol_u32 int_length; /* for this length (0,1,2,4) */ + vol_u32 not_currently_used_0; + vol_u32 not_currently_used_1; + vol_u32 not_currently_used_2; +} Shm_Node_status_control; + +/* This comment block describes the contents of each field + * of the Interrupt Information Table. This table describes + * how another node can generate an interrupt to this node. + * This information is target board dependent. If the + * SHM Driver is in POLLED_MODE, then all fields should + * be initialized to NO_INTERRUPT. + * + * address - The address to which another node should + * write to cause an interrupt. + * value - The value which must be written + * length - The size of the value to write. Valid + * values are BYTE, WORD, and LONG. + * + * NOTE: The Node Status Control Block contains this + * information in neutral format and not in a + * structure to avoid potential alignment problems. + */ + +typedef struct { + vol_u32 *address; /* write here for interrupt */ + vol_u32 value; /* this value causes interrupt */ + vol_u32 length; /* for this length (0,1,2,4) */ +} Shm_Interrupt_information; + +/* SHM Configuration Table + * + * This comment block describes the contents of each field + * of the SHM Configuration Table. + * + * base - The base address of the shared memory. This + * address may be specific to this node. + * length - The length of the shared memory in bytes. + * format - The natural format for uint32_t 's in the + * shared memory. Valid values are currently + * only SHM_LITTLE and SHM_BIG. + * convert - The address of the routine which converts + * between neutral and local format. + * poll_intr - The operational mode of the driver. Some + * target boards may not provide hardware for + * an interprocessor interrupt. If POLLED_MODE + * is selected, the SHM driver will use a + * Classiv API Timer instance to poll for + * incoming packets. Throughput is dependent + * on the time between clock interrupts. + * Valid values are POLLED_MODE and INTR_MODE. + * cause_intr - This is the address of the routine used to + * write to a particular address and cause an + * interrupt on another node. This routine + * may need to be target dependent if something + * other than a normal write from C does not work. + * Intr - This structure describes the operation required + * to cause an interrupt to this node. The actual + * contents of this structure are described above. + */ + +struct shm_config_info { + vol_u32 *base; /* base address of SHM */ + vol_u32 length; /* length (in bytes) of SHM */ + vol_u32 format; /* SHM is big or little endian */ + uint32_t (*convert)( uint32_t );/* neutral conversion routine */ + vol_u32 poll_intr;/* POLLED or INTR driven mode */ + void (*cause_intr)( uint32_t); + Shm_Interrupt_information Intr; /* cause intr information */ +}; + +typedef struct shm_config_info shm_config_table; + +#define SHM_MAXIMUM_NODES Multiprocessing_configuration.maximum_nodes + +/* global variables */ + +#ifdef _SHM_INIT +#define SHM_EXTERN +#else +#define SHM_EXTERN extern +#endif + +SHM_EXTERN shm_config_table *Shm_Configuration; +SHM_EXTERN Shm_Interrupt_information *Shm_Interrupt_table; +SHM_EXTERN Shm_Node_status_control *Shm_Node_statuses; +SHM_EXTERN Shm_Locked_queue_Control *Shm_Locked_queues; +SHM_EXTERN Shm_Envelope_control *Shm_Envelopes; +SHM_EXTERN uint32_t Shm_Receive_message_count; +SHM_EXTERN uint32_t Shm_Null_message_count; +SHM_EXTERN uint32_t Shm_Interrupt_count; +SHM_EXTERN Shm_Locked_queue_Control *Shm_Local_receive_queue; +SHM_EXTERN Shm_Node_status_control *Shm_Local_node_status; +SHM_EXTERN uint32_t Shm_isrstat; + /* reported by shmdr */ + +SHM_EXTERN uint32_t Shm_Pending_initialization; +SHM_EXTERN uint32_t Shm_Initialization_complete; +SHM_EXTERN uint32_t Shm_Active_node; + +SHM_EXTERN uint32_t Shm_Maximum_envelopes; + +SHM_EXTERN uint32_t Shm_Locked_queue_End_of_list; +SHM_EXTERN uint32_t Shm_Locked_queue_Not_on_list; + +/* functions */ + +/* locked queue routines */ +void Shm_Locked_queue_Add( + Shm_Locked_queue_Control *, Shm_Envelope_control * ); +Shm_Envelope_control *Shm_Locked_queue_Get( Shm_Locked_queue_Control * ); +void Shm_Locked_queue_Initialize( + Shm_Locked_queue_Control *, uint32_t); + /* Shm_Initialize_lock is CPU dependent */ + /* Shm_Lock is CPU dependent */ + /* Shm_Unlock is CPU dependent */ + +/* portable routines */ +void Init_env_pool( void ); +void Shm_Print_statistics( void ); +void MPCI_Fatal( rtems_fatal_source, bool, rtems_fatal_code ); +rtems_task Shm_Cause_interrupt( uint32_t ); +void Shm_install_timer( void ); +void Shm_Convert_packet( rtems_packet_prefix * ); + +/* CPU specific routines are inlined in shmcpu.h */ + +/* target specific routines */ +void *Shm_Convert_address( void * ); +void Shm_Get_configuration( uint32_t, shm_config_table ** ); +void Shm_isr( void ); +void Shm_setvec( void ); + +void Shm_Initialize_lock( Shm_Locked_queue_Control * ); +void Shm_Lock( Shm_Locked_queue_Control * ); +void Shm_Unlock( Shm_Locked_queue_Control * ); + +/* MPCI entry points */ +rtems_mpci_entry Shm_Get_packet( + rtems_packet_prefix ** +); + +rtems_mpci_entry Shm_Initialization( void ); + +rtems_mpci_entry Shm_Receive_packet( + rtems_packet_prefix ** +); + +rtems_mpci_entry Shm_Return_packet( + rtems_packet_prefix * +); + +rtems_mpci_entry Shm_Send_packet( + uint32_t, + rtems_packet_prefix * +); + +extern rtems_mpci_table MPCI_table; + +#ifdef _SHM_INIT + +/* multiprocessor communications interface (MPCI) table */ + +rtems_mpci_table MPCI_table = { + 100000, /* default timeout value in ticks */ + MAX_PACKET_SIZE, /* maximum packet size */ + Shm_Initialization, /* initialization procedure */ + Shm_Get_packet, /* get packet procedure */ + Shm_Return_packet, /* return packet procedure */ + Shm_Send_packet, /* packet send procedure */ + Shm_Receive_packet /* packet receive procedure */ +}; + +#endif + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/include/umon/cli.h b/bsps/include/umon/cli.h new file mode 100644 index 0000000000..0e1689db26 --- /dev/null +++ b/bsps/include/umon/cli.h @@ -0,0 +1,147 @@ +/** + * @file + * + * @ingroup shared_cli + * + * @brief Header file for Command Line Interface related stuff + */ + +/* Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ + * which includes this notice: + * + ************************************************************************** + * General notice: + * This code is part of a boot-monitor package developed as a generic base + * platform for embedded system designs. As such, it is likely to be + * distributed to various projects beyond the control of the original + * author. Please notify the author of any enhancements made or bugs found + * so that all may benefit from the changes. In addition, notification back + * to the author will allow the new user to pick up changes that may have + * been made by other users after this version of the code was distributed. + * + * Note1: the majority of this code was edited with 4-space tabs. + * Note2: as more and more contributions are accepted, the term "author" + * is becoming a mis-representation of credit. + * + * Original author: Ed Sutter + * Email: esutter@alcatel-lucent.com + * Phone: 908-582-2351 + ************************************************************************** + * + * Ed Sutter has been informed that this code is being used in RTEMS. + * + * This code was reformatted by Joel Sherrill from OAR Corporation and + * Fernando Nicodemos from NCB - Sistemas + * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding + * standards and to eliminate C++ style comments. + */ + +#ifndef _cli_h +#define _cli_h + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_cli Command table structure + * + * @ingroup shared_umon + * + * @brief Command table structure used by the monitor: + */ + +struct monCommand { + char *name; /* Name of command seen by user. */ + int (*func)(int,char **); /* Called when command is invoked. */ + char **helptxt; /* Help text (see notes below). */ + long flags; /* Single-bit flags for various uses */ + /* (see the CMDFLAG_XXX macros). */ +}; + +#ifdef __cplusplus +} +#endif + +/* Bits currently assigned to command flags used in the monCommand + * structure... + */ +#define CMDFLAG_NOMONRC 1 + +/* Maximum size of a command line: + */ +#ifndef CMDLINESIZE +#define CMDLINESIZE 128 +#endif + +/* Maximum number of arguments in a command line: + */ +#define ARGCNT 24 + +/* Definitions for docommand() return values: + * + * Note that the CMD_SUCCESS, CMD_FAILURE and CMD_PARAM_ERROR are return + * values used by the local command code also. The remaining errors + * (CMD_LINE_ERROR, CMD_ULVL_DENIED and CMD_NOT_FOUND) are used only by + # the docommand() function. + * + * CMD_SUCCESS: + * Everything worked ok. + * CMD_FAILURE: + * Command parameters were valid, but command itself failed for some other + * reason. The docommand() function does not print a message here, it + * is assumed that the error message was printed by the local function. + * CMD_PARAM_ERROR: + * Command line did not parse properly. Control was passed to a + * local command function, but argument syntax caused it to choke. + * In this case docommand() will print out the generic CLI syntax error + * message. + * CMD_LINE_ERROR: + * Command line itself was invalid. Too many args, invalid shell var + * syntax, etc.. Somekind of command line error prior to checking for + * the command name-to-function match. + * CMD_ULVL_DENIED: + * Command's user level is higher than current user level, so access + * is denied. + * CMD_NOT_FOUND: + * Since these same return values are used for each command function + * plus the docommand() function, this error indicates that docommand() + * could not even find the command in the command table. + * CMD_MONRC_DENIED: + * The command cannot execute because it is considered illegal + * when run from within the monrc file. + */ +#define CMD_SUCCESS 0 +#define CMD_FAILURE -1 +#define CMD_PARAM_ERROR -2 +#define CMD_LINE_ERROR -3 +#define CMD_ULVL_DENIED -4 +#define CMD_NOT_FOUND -5 +#define CMD_MONRC_DENIED -6 + +/* Notes on help text array: + * The monitor's CLI processor assumes that every command's help text + * array abides by a few basic rules... + * First of all, it assumes that every array has AT LEAST two strings. + * The first string in the array of strings is assumed to be a one-line + * abstract describing the command. + * The second string in the array of strings is assumed to be a usage + * message that describes the syntax of the arguments needed by the command. + * If this second string is an empty string (""), the docommand() prints out + * a generic usage string indicating that there are no options or arguements + * to apply to the command. + * All remaining lines are formatted based on the needs of the individual + * command and the final string is a null pointer to let the CLI processor + * know where the end is. + * Following is an example help text array... + * + * char *HelpHelp[] = { + * "Display command set", + * "-[d] [commandname]", + * "Options:", + * " -d list commands and descriptions", + * 0, + * }; + * + */ +#endif diff --git a/bsps/include/umon/monlib.h b/bsps/include/umon/monlib.h new file mode 100644 index 0000000000..efbfc93d59 --- /dev/null +++ b/bsps/include/umon/monlib.h @@ -0,0 +1,265 @@ +/** + * @file + * + * @ingroup shared_monlib + * + * @brief Used by both the monitor and the application that + * may reside on top of the monitor + */ + +/* Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ + * which includes this notice: + * + ************************************************************************** + * General notice: + * This code is part of a boot-monitor package developed as a generic base + * platform for embedded system designs. As such, it is likely to be + * distributed to various projects beyond the control of the original + * author. Please notify the author of any enhancements made or bugs found + * so that all may benefit from the changes. In addition, notification back + * to the author will allow the new user to pick up changes that may have + * been made by other users after this version of the code was distributed. + * + * Note1: the majority of this code was edited with 4-space tabs. + * Note2: as more and more contributions are accepted, the term "author" + * is becoming a mis-representation of credit. + * + * Original author: Ed Sutter + * Email: esutter@alcatel-lucent.com + * Phone: 908-582-2351 + ************************************************************************** + * + * Ed Sutter has been informed that this code is being used in RTEMS. + * + * This code was reformatted by Joel Sherrill from OAR Corporation and + * Fernando Nicodemos from NCB - Sistemas + * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding + * standards and to eliminate C++ style comments. + */ + +#ifndef _MONLIB_H_ +#define _MONLIB_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_monlib MONLIB Support + * + * @ingroup shared_umon + * + * @brief MONLIB Support Package + */ + +extern int monConnect(int (*monptr)(int,void *,void *,void *), + void (*lock)(void),void (*unlock)(void)); +extern void mon_getargv(int *argc,char ***argv); +extern void mon_intsrestore(unsigned long oldval); +extern void mon_appexit(int exit_value); +extern void mon_free(char *buffer); +extern void mon_profiler(void *pdata); +extern void mon_bbc(char *filename, int linenum); +extern void mon_warmstart(unsigned long mask); +extern void mon_delay(long msec); +extern void mon_printpkt(char *buf, int size, int incoming); +extern void mon_printmem(char *mem, int size, int ascii); + + +extern int mon_com(int cmd,void *arg1,void *arg2,void *arg3); +extern int mon_timer(int cmd, void * arg); +extern int mon_setenv(char *varname,char *value); +extern int mon_putchar(char c); +extern int mon_getchar(void); +extern int mon_gotachar(void); +extern int mon_getbytes(char *buf,int count,int block); +extern int mon_restart(int restart_value); +extern int mon_tfsinit(void); +extern int mon_tfsunlink(char *filename); +extern int mon_tfslink(char *source, char *target); +extern int mon_tfsrun(char **arglist,int verbosity); +extern int mon_tfsfstat(char *filename,struct tfshdr *tfp); +extern int mon_tfseof(int file_descriptor); +extern int mon_tfstruncate(int file_descriptor,long length); +extern int mon_tfsread(int file_descriptor,char *buffer,int size); +extern int mon_tfswrite(int file_descriptor,char *buffer,int size); +extern int mon_tfsopen(char *filename,long mode,char *buffer); +extern int mon_tfsclose(int file_descriptor,char *info); +extern int mon_tfsseek(int file_descriptor,int offset,int whence); +extern int mon_tfsgetline(int file_descriptor,char *buffer,int bufsize); +extern int mon_tfsipmod(char *name,char *buffer,int offset,int size); +extern int mon_addcommand(struct monCommand *command_list,char *); +extern int mon_docommand(char *cmdline,int verbosity); +extern int mon_getline(char *buffer,int max,int ledit); +extern int mon_decompress(char *src,int srcsize,char *dest); +extern int mon_heapextend(char *base,int size); +extern int mon_pcicfgwrite(int interface,int bus,int dev,int func,int reg, + unsigned long val); +extern int mon_tfsadd(char *filename, char *info, char *flags, + unsigned char *src, int size); +extern int mon_i2cwrite(int interface, int bigaddr, unsigned char *data, + int len); +extern int mon_i2cread(int interface, int bigaddr, unsigned char *data, + int len); +extern int mon_sendenetpkt(char *pkt, int len); +extern int mon_recvenetpkt(char *pkt, int len); +extern int mon_flashoverride(void *flashinfo, int get, int bank); +extern int mon_flasherase(int snum); +extern int mon_flashwrite(char *dest,char *src, int bytecnt); +extern int mon_flashinfo(int snum,int *size, char **base); +extern int mon_watchdog(void); +extern int mon_timeofday(int cmd, void *arg); + +extern char *mon_getsym(char *symname, char *buf, int bufsize); +extern char *mon_getenv(char *varname); +extern char *mon_getenvp(void); +extern char *mon_version(void); +#ifdef MALLOC_DEBUG +extern char *mon_malloc(int size,char *file, int line); +extern char *mon_realloc(char *buf,int size,char *file, int line); +#else +extern char *mon_malloc(int size); +extern char *mon_realloc(char *buf,int size); +#endif + +extern long mon_tfsctrl(int command,long arg1,long arg2); +extern long mon_tfstell(int file_descriptor); +extern long mon_portcmd(int cmd, void *arg); + +extern unsigned short mon_xcrc16(char *buffer,long length); + +extern unsigned long mon_intsoff(void); + +extern unsigned long mon_pcicfgread(int interface,int bus,int dev, + int func,int reg); + +extern unsigned long mon_pcictrl(int interface, int cmd, + unsigned long arg1, unsigned long arg2); + +extern unsigned long mon_i2cctrl(int interface, int cmd, + unsigned long arg1, unsigned long arg2); + +extern unsigned long mon_assignhandler(long hnum, + unsigned long arg1,unsigned long arg2); + +extern struct tfshdr *mon_tfsnext(struct tfshdr *tfp); +extern struct tfshdr *mon_tfsstat(char *filename); + +#if SHOWVARARGS +extern void mon_memtrace(char *fmt, ...); +extern int mon_printf(char *fmt, ...); +extern int mon_cprintf(char *fmt, ...); +extern int mon_sprintf(char *,char *fmt, ...); +#else +extern void mon_memtrace(); +extern int mon_printf(); +extern int mon_cprintf(); +extern int mon_sprintf(); +#endif + +#ifdef __cplusplus +} +#endif + + +/* defines used by monConnect(): + */ +#define GETMONFUNC_PUTCHAR 1 +#define GETMONFUNC_GETCHAR 2 +#define GETMONFUNC_GOTACHAR 3 +#define GETMONFUNC_GETBYTES 4 +#define GETMONFUNC_PRINTF 5 +#define GETMONFUNC_CPRINTF 6 +#define GETMONFUNC_SPRINTF 7 +#define GETMONFUNC_RESTART 8 +#define GETMONFUNC_GETENV 9 +#define GETMONFUNC_SETENV 10 +#define GETMONFUNC_TFSINIT 11 +#define GETMONFUNC_TFSADD 12 +#define GETMONFUNC_TFSUNLINK 13 +#define GETMONFUNC_TFSRUN 14 +#define GETMONFUNC_TFSNEXT 15 +#define GETMONFUNC_TFSSTAT 16 +#define GETMONFUNC_TFSREAD 17 +#define GETMONFUNC_TFSWRITE 18 +#define GETMONFUNC_TFSOPEN 19 +#define GETMONFUNC_TFSCLOSE 20 +#define GETMONFUNC_TFSSEEK 21 +#define GETMONFUNC_TFSGETLINE 22 +#define GETMONFUNC_TFSIPMOD 23 +#define GETMONFUNC_TFSCTRL 24 +#define GETMONFUNC_ADDCOMMAND 25 +#define GETMONFUNC_DOCOMMAND 26 +#define GETMONFUNC_GETARGV 27 +#define GETMONFUNC_CRC16 28 +#define GETMONFUNC_CRC32 29 +#define GETMONFUNC_PIOGET 30 /* NA (removed as of 1.0) */ +#define GETMONFUNC_PIOSET 31 /* NA (removed as of 1.0) */ +#define GETMONFUNC_PIOCLR 32 /* NA (removed as of 1.0) */ +#define GETMONFUNC_INTSOFF 33 +#define GETMONFUNC_INTSRESTORE 34 +#define GETMONFUNC_APPEXIT 35 +#define GETMONFUNC_MALLOC 36 +#define GETMONFUNC_FREE 37 +#define GETMONFUNC_GETLINE 38 +#define GETMONFUNC_TFSFSTAT 39 +#define GETMONFUNC_TFSEOF 40 +#define GETMONFUNC_DECOMPRESS 41 +#define GETMONFUNC_TFSTRUNCATE 42 +#define GETMONFUNC_HEAPXTEND 43 +#define GETMONFUNC_PROFILER 44 +#define GETMONFUNC_TFSLINK 45 +#define GETMONFUNC_BBC 46 +#define GETMONFUNC_MEMTRACE 47 +#define GETMONFUNC_TFSTELL 48 +#define GETMONFUNC_VERSION 49 +#define GETMONFUNC_WARMSTART 50 +#define GETMONFUNC_PCICFGREAD 51 +#define GETMONFUNC_PCICFGWRITE 52 +#define GETMONFUNC_PCICONTROL 53 +#define GETMONFUNC_I2CREAD 54 +#define GETMONFUNC_I2CWRITE 55 +#define GETMONFUNC_I2CCONTROL 56 +#define GETMONFUNC_MONDELAY 57 +#define GETMONFUNC_GETENVP 58 +#define GETMONFUNC_REALLOC 59 +#define GETMONFUNC_SENDENETPKT 60 +#define GETMONFUNC_RECVENETPKT 61 +#define GETMONFUNC_GETSYM 62 +#define GETMONFUNC_PRINTPKT 63 +#define GETMONFUNC_FLASHWRITE 64 +#define GETMONFUNC_FLASHERASE 65 +#define GETMONFUNC_FLASHINFO 66 +#define GETMONFUNC_ASSIGNHDLR 67 +#define GETMONFUNC_WATCHDOG 68 +#define GETMONFUNC_PRINTMEM 69 +#define GETMONFUNC_PORTCMD 70 +#define GETMONFUNC_TIMEOFDAY 71 +#define GETMONFUNC_TIMER 72 +#define GETMONFUNC_FLASHOVRRD 73 + +#define CACHEFTYPE_DFLUSH 200 +#define CACHEFTYPE_IINVALIDATE 201 + +#define CHARFUNC_PUTCHAR 300 +#define CHARFUNC_GETCHAR 301 +#define CHARFUNC_GOTACHAR 302 +#define CHARFUNC_RAWMODEON 303 +#define CHARFUNC_RAWMODEOFF 304 + +#define ASSIGNFUNC_GETUSERLEVEL 400 + + +/* Defines used by mon_warmstart(): + */ +#define WARMSTART_IOINIT 0x00000001 +#define WARMSTART_BSSINIT 0x00000002 +#define WARMSTART_RUNMONRC 0x00000004 +#define WARMSTART_MONHEADER 0x00000008 +#define WARMSTART_TFSAUTOBOOT 0x00000010 +#define WARMSTART_BOARDINFO 0x00000020 +#define WARMSTART_ALL 0xffffffff +#endif diff --git a/bsps/include/umon/tfs.h b/bsps/include/umon/tfs.h new file mode 100644 index 0000000000..258288bd14 --- /dev/null +++ b/bsps/include/umon/tfs.h @@ -0,0 +1,214 @@ +/** + * @file + * + * @ingroup shared_tfs + * + * @brief Header file for TFS transactions, used by both application and + * monnitor. + */ + +/* Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ + * which includes this notice: + * + ************************************************************************** + * General notice: + * This code is part of a boot-monitor package developed as a generic base + * platform for embedded system designs. As such, it is likely to be + * distributed to various projects beyond the control of the original + * author. Please notify the author of any enhancements made or bugs found + * so that all may benefit from the changes. In addition, notification back + * to the author will allow the new user to pick up changes that may have + * been made by other users after this version of the code was distributed. + * + * Note1: the majority of this code was edited with 4-space tabs. + * Note2: as more and more contributions are accepted, the term "author" + * is becoming a mis-representation of credit. + * + * Original author: Ed Sutter + * Email: esutter@alcatel-lucent.com + * Phone: 908-582-2351 + ************************************************************************** + * + * Ed Sutter has been informed that this code is being used in RTEMS. + * + * This code was reformatted by Joel Sherrill from OAR Corporation and + * Fernando Nicodemos from NCB - Sistemas + * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding + * standards and to eliminate C++ style comments. + */ + +#ifndef _tfs_h +#define _tfs_h + +/** + * @defgroup shared_tfs TFS Support + * + * @ingroup shared_umon + * + * @brief TFS Support Package + */ + +#define TFSINFOSIZE 23 /* Max size of info string (mod4-1). */ + +#ifndef TFSNAMESIZE /* This specifies the maximum size of a file */ +#define TFSNAMESIZE 23 /* name that can be used in TFS. */ +#endif /* This MUST be some value mod4 - 1. */ + +#ifndef TFS_CHANGELOG_FILE /* Information used for change-log */ +#define TFS_CHANGELOG_SIZE 0 /* facility within tfs. */ +#define TFS_CHANGELOG_FILE ".tfschlog" +#endif + +#ifndef SYMFILE /* This specifies the default filename */ +#define SYMFILE "symtbl" /* used by the monitor for the symbol */ +#endif /* table. */ + +#define MINUSRLEVEL 0 /* Minimum user level supported. */ +#define MAXUSRLEVEL 3 /* Maximum user level supported. */ + +#ifndef TFS_RESERVED +#define TFS_RESERVED 4 /* Number of "reserved" entries (ulong) */ +#endif /* in the TFS header. */ + + +/* Flags: */ +#define TFS_EXEC 0x00000001 /* 'e': Executable script. */ +#define TFS_BRUN 0x00000002 /* 'b': To be executed at boot. */ +#define TFS_QRYBRUN 0x00000004 /* 'B': To be executed at boot if */ + /* query passes. */ +#define TFS_SYMLINK 0x00000008 /* 'l': Symbolic link file. */ +#define TFS_EBIN 0x00000010 /* 'E': Executable binary (coff/elf/a.out). */ +#define TFS_CPRS 0x00000040 /* 'c': File is compressed. */ +#define TFS_IPMOD 0x00000080 /* 'i': File is in-place modifiable. */ +#define TFS_UNREAD 0x00000100 /* 'u': File is not even readable if the */ + /* user-level requirement is not met; */ + /* else, it is read-only. */ +#define TFS_ULVLMSK 0x00000600 /* User level mask defines 4 access levels: */ +#define TFS_ULVL0 0x00000000 /* '0' level 0 */ +#define TFS_ULVL1 0x00000200 /* '1' level 1 */ +#define TFS_ULVL2 0x00000400 /* '2' level 2 */ +#define TFS_ULVL3 0x00000600 /* '3' level 3 */ +#define TFS_NSTALE 0x00000800 /* File is NOT stale, invisible to user. + * When this bit is clear, the file is + * considered stale (see notes in tfsadd()). + * See notes in tfsclose() for this. + */ +#define TFS_ACTIVE 0x00008000 /* Used to indicate that file is not deleted. */ + +#define TFS_ULVLMAX TFS_ULVL3 +#define TFS_USRLVL(f) ((f->flags & TFS_ULVLMSK) >> 9) + +/* Open modes */ +#define TFS_RDONLY 0x00010000 /* File is opened for reading. */ +#define TFS_CREATE 0x00020000 /* File is to be created. Error if file */ + /* with the same name already exists. */ +#define TFS_APPEND 0x00040000 /* Append to existing file. If OR'ed */ + /* with TFS_CREATE, then create if */ + /* necessary. */ +#define TFS_ALLFFS 0x00080000 /* File is created with all FFs. */ +#define TFS_CREATERM 0x00100000 /* File is to be created. If file with */ + /* same name already exists, then allow */ + /* tfsadd() to remove it if necessary. */ + +/* The function tfsrunrc() will search through the current file set and */ +/* if the file defined by TFS_RCFILE exists, it will be executed. */ +/* If this file exists, it will NOT be run by tfsrunboot(). */ +#define TFS_RCFILE "monrc" + +/* Requests that can be made to tfsctrl(): */ +#define TFS_ERRMSG 1 +#define TFS_MEMUSE 2 +#define TFS_MEMDEAD 3 +#define TFS_DEFRAG 4 +#define TFS_TELL 5 +#define TFS_UNOPEN 7 +#define TFS_FATOB 8 +#define TFS_FBTOA 9 +#define TFS_MEMAVAIL 10 +#define TFS_TIMEFUNCS 11 +#define TFS_DOCOMMAND 12 +#define TFS_INITDEV 13 +#define TFS_CHECKDEV 14 +#define TFS_DEFRAGDEV 15 +#define TFS_DEFRAGOFF 16 +#define TFS_DEFRAGON 17 +#define TFS_HEADROOM 18 +#define TFS_FCOUNT 19 + +/* struct tfshdr: + * It is in FLASH as part of the file system to record the attributes of + * the file at the time of creation. + */ +struct tfshdr { + unsigned short hdrsize; /* Size of this header. */ + unsigned short hdrvrsn; /* Header version #. */ + long filsize; /* Size of the file. */ + long flags; /* Flags describing the file. */ + unsigned long filcrc; /* 32 bit CRC of file. */ + unsigned long hdrcrc; /* 32 bit CRC of the header. */ + unsigned long modtime; /* Time when file was last modified. */ + struct tfshdr *next; /* Pointer to next file in list. */ + char name[TFSNAMESIZE+1]; /* Name of file. */ + char info[TFSINFOSIZE+1]; /* Miscellaneous info field. */ +#if TFS_RESERVED + unsigned long rsvd[TFS_RESERVED]; +#endif +}; + +#define TFSHDRSIZ sizeof(struct tfshdr) + +/* TFS error returns. */ +#define TFS_OKAY 0 +#define TFSERR_NOFILE -1 +#define TFSERR_NOSLOT -2 +#define TFSERR_EOF -3 +#define TFSERR_BADARG -4 +#define TFSERR_NOTEXEC -5 +#define TFSERR_BADCRC -6 +#define TFSERR_FILEEXISTS -7 +#define TFSERR_FLASHFAILURE -8 +#define TFSERR_WRITEMAX -9 +#define TFSERR_RDONLY -10 +#define TFSERR_BADFD -11 +#define TFSERR_BADHDR -12 +#define TFSERR_CORRUPT -13 +#define TFSERR_MEMFAIL -14 +#define TFSERR_NOTIPMOD -16 +#define TFSERR_MUTEXFAILURE -17 +#define TFSERR_FLASHFULL -18 +#define TFSERR_USERDENIED -19 +#define TFSERR_NAMETOOBIG -20 +#define TFSERR_FILEINUSE -21 +#define TFSERR_NOTCPRS -22 +#define TFSERR_NOTAVAILABLE -23 +#define TFSERR_BADFLAG -24 +#define TFSERR_CLEANOFF -25 +#define TFSERR_FLAKEYSOURCE -26 +#define TFSERR_BADEXTENSION -27 +#define TFSERR_MIN -100 + +/* TFS seek options. */ +#define TFS_BEGIN 1 +#define TFS_CURRENT 2 +#define TFS_END 3 + +/* Macros: */ +#define TFS_DELETED(fp) (!((fp)->flags & TFS_ACTIVE)) +#define TFS_FILEEXISTS(fp) ((fp)->flags & TFS_ACTIVE) +#define TFS_ISCPRS(fp) ((fp)->flags & TFS_CPRS) +#define TFS_ISEXEC(fp) ((fp)->flags & TFS_EXEC) +#define TFS_ISBOOT(fp) ((fp)->flags & TFS_BRUN) +#define TFS_ISLINK(fp) ((fp)->flags & TFS_SYMLINK) +#define TFS_STALE(fp) (!((fp)->flags & TFS_NSTALE)) +#define TFS_FLAGS(fp) ((fp)->flags) +#define TFS_NAME(fp) ((fp)->name) +#define TFS_SIZE(fp) ((fp)->filsize) +#define TFS_TIME(fp) ((fp)->modtime) +#define TFS_INFO(fp) ((fp)->info) +#define TFS_NEXT(fp) ((fp)->next) +#define TFS_CRC(fp) ((fp)->filcrc) +#define TFS_ENTRY(fp) ((fp)->entry) +#define TFS_BASE(fp) ((char *)(fp)+(fp)->hdrsize) + +typedef struct tfshdr TFILE; +#endif diff --git a/bsps/lm32/headers.am b/bsps/lm32/headers.am new file mode 100644 index 0000000000..e44184dbea --- /dev/null +++ b/bsps/lm32/headers.am @@ -0,0 +1,18 @@ +## This file was generated by "./boostrap -H". + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_ac97.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_buttons.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_dmx.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_flash.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_gpio.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_ir.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_memcard.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_midi.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_pfpu.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_tmu.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_usbinput.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_versions.h +include_bsp_HEADERS += ../../../../../bsps/lm32/include/bsp/milkymist_video.h diff --git a/bsps/lm32/include/bsp/irq.h b/bsps/lm32/include/bsp/irq.h new file mode 100644 index 0000000000..b1ccd66339 --- /dev/null +++ b/bsps/lm32/include/bsp/irq.h @@ -0,0 +1,47 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief BSP interrupt support for LM32. + */ + +/* + * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette. + * + * Copyright (c) 2008, 2009, 2010 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_LM32_IRQ_CONFIG_H +#define LIBBSP_LM32_IRQ_CONFIG_H + +#include + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +/** + * @brief Minimum vector number. + */ +#define BSP_INTERRUPT_VECTOR_MIN 0 + +/** + * @brief Maximum vector number. + */ +#define BSP_INTERRUPT_VECTOR_MAX 31 + +/** @} */ + +#endif /* LIBBSP_LM32_IRQ_CONFIG_H */ diff --git a/bsps/lm32/include/bsp/milkymist_ac97.h b/bsps/lm32/include/bsp/milkymist_ac97.h new file mode 100644 index 0000000000..37415a1f5e --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_ac97.h @@ -0,0 +1,76 @@ +/** + * @file + * @ingroup lm32_milkymist_ac97 lm32_milkymist_shared + * @brief Milkymist AC97 driver + */ + +/* milkymist_ac97.h + * + * Milkymist AC97 driver for RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2010 Sebastien Bourdeauducq + */ + +/** + * @defgroup lm32_milkymist_ac97 Milkymist AC97 + * @ingroup lm32_milkymist_shared + * @brief Milkymist AC97 driver + * @{ + */ + +#ifndef __MILKYMIST_AC97_H_ +#define __MILKYMIST_AC97_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Ioctls. 0x41 is 'A' */ +#define SOUND_MIXER_MIC 0x0 +#define SOUND_MIXER_LINE 0x1 +#define SOUND_MIXER_READ(x) (0x4100+x) +#define SOUND_MIXER_WRITE(x) (0x4110+x) + +#define SOUND_SND_SUBMIT_PLAY 0x4120 +#define SOUND_SND_COLLECT_PLAY 0x4121 +#define SOUND_SND_SUBMIT_RECORD 0x4122 +#define SOUND_SND_COLLECT_RECORD 0x4123 + +struct snd_buffer { + unsigned int nsamples; + void *user; + unsigned int samples[]; +}; + +rtems_device_driver ac97_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver ac97_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver ac97_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define AC97_DRIVER_TABLE_ENTRY {ac97_initialize, \ +ac97_open, NULL, NULL, NULL, ac97_control} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MILKYMIST_AC97_H_ */ diff --git a/bsps/lm32/include/bsp/milkymist_buttons.h b/bsps/lm32/include/bsp/milkymist_buttons.h new file mode 100644 index 0000000000..de6ee51438 --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_buttons.h @@ -0,0 +1,59 @@ +/** + * @file + * @ingroup lm32_milkymist_buttons lm32_milkymist_shared + * @brief Milkymist buttons driver + */ + +/* milkymist_buttons.h + * + * Milkymist buttons driver for RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2011 Sebastien Bourdeauducq + */ + +/** + * @defgroup lm32_milkymist_buttons Milkymist buttons + * @ingroup lm32_milkymist_shared + * @brief Milkymist buttons driver + * @{ + */ + +#ifndef __MILKYMIST_BUTTONS_H_ +#define __MILKYMIST_BUTTONS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +rtems_device_driver buttons_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver buttons_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver buttons_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define BUTTONS_DRIVER_TABLE_ENTRY { buttons_initialize, \ +buttons_open, NULL, buttons_read, NULL, NULL} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MILKYMIST_BUTTONS_H_ */ diff --git a/bsps/lm32/include/bsp/milkymist_dmx.h b/bsps/lm32/include/bsp/milkymist_dmx.h new file mode 100644 index 0000000000..a933e3423f --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_dmx.h @@ -0,0 +1,68 @@ +/** + * @file + * @ingroup lm32_milkymist_dmx lm32_milkymist_shared + * @brief Milkymist DMX512 driver + */ + +/* milkymist_dmx.h + * + * Milkymist DMX512 driver for RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2010 Sebastien Bourdeauducq + */ + +/** + * @defgroup lm32_milkymist_dmx Milkymist DMX512 + * @ingroup lm32_milkymist_shared + * @brief Milkymist DMX512 driver + * @{ + */ + +#ifndef __MILKYMIST_DMX_H_ +#define __MILKYMIST_DMX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define DMX_SET_THRU 0x4400 +#define DMX_GET_THRU 0x4401 + +rtems_device_driver dmx_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver dmx_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver dmx_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver dmx_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define DMX_DRIVER_TABLE_ENTRY {dmx_initialize, \ +NULL, NULL, dmx_read, dmx_write, dmx_control} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MILKYMIST_DMX_H_ */ diff --git a/bsps/lm32/include/bsp/milkymist_flash.h b/bsps/lm32/include/bsp/milkymist_flash.h new file mode 100644 index 0000000000..2acf855096 --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_flash.h @@ -0,0 +1,64 @@ +/** + * @file + * @ingroup lm32_milkymist_flash lm32_milkymist_shared + * @brief Milkymist Flash + */ + +/* milkymist_flash.h + * + * Copyright (C) 2010 Sebastien Bourdeauducq + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +/** + * @defgroup lm32_milkymist_flash Milkymist Flash + * @ingroup lm32_milkymist_shared + * @brief Milkymist Flash + * @{ + */ + +#ifndef __MILKYMIST_FLASH_H_ +#define __MILKYMIST_FLASH_H_ + +/* Ioctls */ +#define FLASH_GET_SIZE 0x4600 +#define FLASH_GET_BLOCKSIZE 0x4601 +#define FLASH_ERASE_BLOCK 0x4602 + +struct flash_partition { + unsigned int start_address; + unsigned int length; +}; + +rtems_device_driver flash_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver flash_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver flash_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver flash_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define FLASH_DRIVER_TABLE_ENTRY {flash_initialize, \ +NULL, NULL, flash_read, flash_write, flash_control} + +#endif /* __MILKYMIST_FLASH_H_ */ diff --git a/bsps/lm32/include/bsp/milkymist_gpio.h b/bsps/lm32/include/bsp/milkymist_gpio.h new file mode 100644 index 0000000000..1e30b9c280 --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_gpio.h @@ -0,0 +1,59 @@ +/** + * @file + * @ingroup lm32_milkymist_gpio lm32_milkymist_shared + * @brief Milkymist GPIO driver + */ + +/* milkymist_gpio.h + * + * Milkymist GPIO driver for RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2010 Sebastien Bourdeauducq + */ + +/** + * @defgroup lm32_milkymist_gpio Milkymist GPIO + * @ingroup lm32_milkymist_shared + * @brief Milkymist GPIO driver + * @{ + */ + +#ifndef __MILKYMIST_GPIO_H_ +#define __MILKYMIST_GPIO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +rtems_device_driver gpio_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver gpio_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver gpio_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define GPIO_DRIVER_TABLE_ENTRY { gpio_initialize, \ +NULL, NULL, gpio_read, gpio_write, NULL} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MILKYMIST_GPIO_H_ */ diff --git a/bsps/lm32/include/bsp/milkymist_ir.h b/bsps/lm32/include/bsp/milkymist_ir.h new file mode 100644 index 0000000000..4df7f3550c --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_ir.h @@ -0,0 +1,59 @@ +/** + * @file + * @ingroup lm32_milkymist_ir lm32_milkymist_shared + * @brief Milkymist RC5 IR driver + */ + +/* milkymist_ir.h + * + * Milkymist RC5 IR driver for RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2010 Sebastien Bourdeauducq + */ + +/** + * @defgroup lm32_milkymist_ir Milkymist IR + * @ingroup lm32_milkymist_shared + * @brief Milkymist RC5 IR driver + * @{ + */ + +#ifndef __MILKYMIST_IR_H_ +#define __MILKYMIST_IR_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +rtems_device_driver ir_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver ir_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver ir_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define IR_DRIVER_TABLE_ENTRY {ir_initialize, \ +ir_open, NULL, ir_read, NULL, NULL} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MILKYMIST_IR_H_ */ diff --git a/bsps/lm32/include/bsp/milkymist_memcard.h b/bsps/lm32/include/bsp/milkymist_memcard.h new file mode 100644 index 0000000000..713b45be07 --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_memcard.h @@ -0,0 +1,32 @@ +/** + * @file + * @ingroup lm32_milkymist_memcard lm32_milkymist_shared + * @brief Milkymist memory card driver + */ + +/* milkymist_memcard.h + * + * Milkymist memory card driver for RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2010 Sebastien Bourdeauducq + */ + +/** + * @defgroup lm32_milkymist_memcard Milkymist memory card + * @ingroup lm32_milkymist_shared + * @brief Milkymist memory card driver + * @{ + */ + +#ifndef __MILKYMIST_MEMCARD_H_ +#define __MILKYMIST_MEMCARD_H_ + +rtems_status_code memcard_register(void); + +#endif /* __MILKYMIST_MEMCARD_H_ */ + +/** @} */ diff --git a/bsps/lm32/include/bsp/milkymist_midi.h b/bsps/lm32/include/bsp/milkymist_midi.h new file mode 100644 index 0000000000..da53de6af5 --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_midi.h @@ -0,0 +1,59 @@ +/** + * @file + * @ingroup lm32_milkymist_midi lm32_milkymist_shared + * @brief Milkymist MIDI driver + */ + +/* milkymist_midi.h + * + * Milkymist MIDI driver for RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2010 Sebastien Bourdeauducq + */ + +/** + * @defgroup lm32_milkymist_midi Milkymist MIDI + * @ingroup lm32_milkymist_shared + * @brief Milkymist MIDI driver + * @{ + */ + +#ifndef __MILKYMIST_MIDI_H_ +#define __MILKYMIST_MIDI_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +rtems_device_driver midi_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver midi_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver midi_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define MIDI_DRIVER_TABLE_ENTRY {midi_initialize, \ +midi_open, NULL, midi_read, NULL, NULL} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MILKYMIST_MIDI_H_ */ diff --git a/bsps/lm32/include/bsp/milkymist_pfpu.h b/bsps/lm32/include/bsp/milkymist_pfpu.h new file mode 100644 index 0000000000..73ea5fa28e --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_pfpu.h @@ -0,0 +1,72 @@ +/** + * @file + * @ingroup lm32_milkymist_pfpu lm32_milkymist_shared + * @brief Milkymist PFPU driver + */ + +/* milkymist_pfpu.h + * + * Milkymist PFPU driver for RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2010 Sebastien Bourdeauducq + */ + +/** + * @defgroup lm32_milkymist_pfpu Milkymist PFPU + * @ingroup lm32_milkymist_shared + * @brief Milkymist PFPU driver + * @{ + */ + +#ifndef __MILKYMIST_PFPU_H_ +#define __MILKYMIST_PFPU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Ioctls */ +#define PFPU_EXECUTE 0x4600 + +#define PFPU_PROGSIZE (2048) +#define PFPU_REG_COUNT (128) + +struct pfpu_td { + unsigned int *output; + unsigned int hmeshlast; + unsigned int vmeshlast; + unsigned int *program; + unsigned int progsize; + float *registers; + /** @brief shall we update the "registers" array after completion */ + bool update; + /** @brief shall we invalidate L1 data cache after completion */ + bool invalidate; +}; + +rtems_device_driver pfpu_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver pfpu_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define PFPU_DRIVER_TABLE_ENTRY {pfpu_initialize, \ +NULL, NULL, NULL, NULL, pfpu_control} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MILKYMIST_PFPU_H_ */ diff --git a/bsps/lm32/include/bsp/milkymist_tmu.h b/bsps/lm32/include/bsp/milkymist_tmu.h new file mode 100644 index 0000000000..94f8394ef7 --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_tmu.h @@ -0,0 +1,98 @@ +/** + * @file + * @ingroup lm32_milkymist_tmu lm32_milkymist_shared + * @brief Milkymist TMU driver + */ + +/* milkymist_tmu.h + * + * Milkymist TMU driver for RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2010 Sebastien Bourdeauducq + */ + +/** + * @defgroup lm32_milkymist_tmu Milkymist TMU + * @ingroup lm32_milkymist_shared + * @brief Milkymist TMU driver + * @{ + */ + +#ifndef __MILKYMIST_TMU_H_ +#define __MILKYMIST_TMU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Ioctls */ +#define TMU_EXECUTE 0x5400 +#define TMU_EXECUTE_NONBLOCK 0x5401 +#define TMU_EXECUTE_WAIT 0x5402 + +struct tmu_vertex { + int x; + int y; +} __attribute__((packed)); + +struct tmu_td { + unsigned int flags; + unsigned int hmeshlast; + unsigned int vmeshlast; + unsigned int brightness; + unsigned short chromakey; + struct tmu_vertex *vertices; + unsigned short *texfbuf; + unsigned int texhres; + unsigned int texvres; + unsigned int texhmask; + unsigned int texvmask; + unsigned short *dstfbuf; + unsigned int dsthres; + unsigned int dstvres; + int dsthoffset; + int dstvoffset; + unsigned int dstsquarew; + unsigned int dstsquareh; + unsigned int alpha; + + bool invalidate_before; + bool invalidate_after; +}; + +#define TMU_BRIGHTNESS_MAX (63) +#define TMU_MASK_NOFILTER (0x3ffc0) +#define TMU_MASK_FULL (0x3ffff) +#define TMU_FIXEDPOINT_SHIFT (6) +#define TMU_ALPHA_MAX (63) +#define TMU_MESH_MAXSIZE (128) + +#define TMU_FLAG_CHROMAKEY (2) +#define TMU_FLAG_ADDITIVE (4) + +rtems_device_driver tmu_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver tmu_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define TMU_DRIVER_TABLE_ENTRY {tmu_initialize, \ +NULL, NULL, NULL, NULL, tmu_control} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MILKYMIST_TMU_H_ */ diff --git a/bsps/lm32/include/bsp/milkymist_usbinput.h b/bsps/lm32/include/bsp/milkymist_usbinput.h new file mode 100644 index 0000000000..04c376fa8a --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_usbinput.h @@ -0,0 +1,71 @@ +/** + * @file + * @ingroup lm32_milkymist_usbinput lm32_milkymist_shared + * @brief Milkymist USB input devices driver + */ + +/* milkymist_usbinput.h + * + * Milkymist USB input devices driver for RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2010, 2012 Sebastien Bourdeauducq + */ + +/** + * @defgroup lm32_milkymist_usbinput Milkymist USB input devices + * @ingroup lm32_milkymist_shared + * @brief Milkymist USB input devices driver + * @{ + */ + +#ifndef __MILKYMIST_USBINPUT_H_ +#define __MILKYMIST_USBINPUT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Ioctls */ +#define USBINPUT_LOAD_FIRMWARE 0x5500 + +struct usbinput_firmware_description { + const unsigned char *data; + int length; +}; + +rtems_device_driver usbinput_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver usbinput_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver usbinput_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver usbinput_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define USBINPUT_DRIVER_TABLE_ENTRY {usbinput_initialize, \ +usbinput_open, NULL, usbinput_read, NULL, usbinput_control} + +#ifdef __cplusplus +} +#endif + +#endif /* __MILKYMIST_USBINPUT_H_ */ diff --git a/bsps/lm32/include/bsp/milkymist_versions.h b/bsps/lm32/include/bsp/milkymist_versions.h new file mode 100644 index 0000000000..3b5063f306 --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_versions.h @@ -0,0 +1,53 @@ +/** + * @file + * @ingroup lm32_milkymist_versions lm32_milkymist_shared + * @brief Milkymist versioning driver + */ + +/* milkymist_versions.h + * + * Milkymist versioning driver for RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2010 Sebastien Bourdeauducq + */ + +/** + * @defgroup lm32_milkymist_versions Milkymist versioning + * @ingroup lm32_milkymist_shared + * @brief Milkymist versioning driver + * @{ + */ + +#ifndef __MILKYMIST_VERSIONS_H_ +#define __MILKYMIST_VERSIONS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +rtems_device_driver versions_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver versions_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define VERSIONS_DRIVER_TABLE_ENTRY {versions_initialize, \ +NULL, NULL, versions_read, NULL, NULL} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MILKYMIST_VERSIONS_H_ */ diff --git a/bsps/lm32/include/bsp/milkymist_video.h b/bsps/lm32/include/bsp/milkymist_video.h new file mode 100644 index 0000000000..6ec3cc0a83 --- /dev/null +++ b/bsps/lm32/include/bsp/milkymist_video.h @@ -0,0 +1,90 @@ +/** + * @file + * @ingroup lm32_milkymist_video lm32_milkymist_shared + * @brief Milkymist video input driver + */ + +/* milkymist_video.h + * + * Milkymist video input driver for RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2010, 2011 Sebastien Bourdeauducq + */ + +/** + * @defgroup lm32_milkymist_video Milkymist Video + * @ingroup lm32_milkymist_shared + * @brief Milkymist video input driver + * @{ + */ + +#ifndef __MILKYMIST_VIDEO_H_ +#define __MILKYMIST_VIDEO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Ioctls */ +#define VIDEO_BUFFER_LOCK 0x5600 +#define VIDEO_BUFFER_UNLOCK 0x5601 + +#define VIDEO_SET_BRIGHTNESS 0x5602 +#define VIDEO_GET_BRIGHTNESS 0x5603 +#define VIDEO_SET_CONTRAST 0x5604 +#define VIDEO_GET_CONTRAST 0x5605 +#define VIDEO_SET_HUE 0x5606 +#define VIDEO_GET_HUE 0x5607 +#define VIDEO_GET_SIGNAL 0x5608 + +#define VIDEO_SET_REGISTER 0x5609 +#define VIDEO_GET_REGISTER 0x560a + +#define VIDEO_SET_FORMAT 0x560b + +enum { + VIDEO_FORMAT_CVBS6 = 0, + VIDEO_FORMAT_CVBS5, + VIDEO_FORMAT_CVBS4, + VIDEO_FORMAT_SVIDEO, + VIDEO_FORMAT_COMPONENT, +}; + +rtems_device_driver video_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver video_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver video_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver video_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define VIDEO_DRIVER_TABLE_ENTRY {video_initialize, \ +video_open, video_close, NULL, NULL, video_control} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MILKYMIST_VIDEO_H_ */ diff --git a/bsps/lm32/lm32_evr/headers.am b/bsps/lm32/lm32_evr/headers.am new file mode 100644 index 0000000000..213b66effe --- /dev/null +++ b/bsps/lm32/lm32_evr/headers.am @@ -0,0 +1,7 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/lm32/lm32_evr/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/lm32/lm32_evr/include/system_conf.h +include_HEADERS += ../../../../../../bsps/lm32/lm32_evr/include/tm27.h diff --git a/bsps/lm32/lm32_evr/include/bsp.h b/bsps/lm32/lm32_evr/include/bsp.h new file mode 100644 index 0000000000..7c3ac8400d --- /dev/null +++ b/bsps/lm32/lm32_evr/include/bsp.h @@ -0,0 +1,87 @@ +/** + * @file + * + * @ingroup lm32_evr + * + * @brief Global BSP definitions. + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Jukka Pietarinen , 2008, + * Micro-Research Finland Oy + */ + +#ifndef LIBBSP_LM32_LM32_EVR_BSP_H +#define LIBBSP_LM32_LM32_EVR_BSP_H + +#include +#include +#include + +#include + +/** + * @defgroup lm32_evr EVR Support + * + * @ingroup bsp_lm32 + * + * @brief EVR support package. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_DIRTY_MEMORY 1 + + /* + * lm32 requires certain aligment of mbuf because unaligned uint32_t + * accesses are not handled properly. + */ + +#define CPU_U32_FIX + +#if defined(RTEMS_NETWORKING) +struct rtems_bsdnet_ifconfig; + +extern int rtems_tsmac_driver_attach(struct rtems_bsdnet_ifconfig *config, + int attaching); + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "TSMAC0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_tsmac_driver_attach + + /* + * Due to a hardware design error (RJ45 connector with 10baseT magnetics) + * we are forced to use 10baseT mode. + */ + +#define TSMAC_FORCE_10BASET +#endif + +/* functions */ +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +/* + * Prototypes for BSP methods that cross file boundaries + */ +void BSP_uart_polled_write(char ch); +int BSP_uart_polled_read( void ); +char BSP_uart_is_character_ready(char *ch); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/lm32/lm32_evr/include/system_conf.h b/bsps/lm32/lm32_evr/include/system_conf.h new file mode 100644 index 0000000000..41f17e2be0 --- /dev/null +++ b/bsps/lm32/lm32_evr/include/system_conf.h @@ -0,0 +1,180 @@ +/** + * @file + * + * @ingroup lm32_evr + * + * @brief System configuration. + */ + +#ifndef __SYSTEM_CONFIG_H_ +#define __SYSTEM_CONFIG_H_ + + +#define FPGA_DEVICE_FAMILY "ECP2M" +#define PLATFORM_NAME "platform1" +#define USE_PLL (0) +#define CPU_FREQUENCY (75000000) + + +/* FOUND 1 CPU UNIT(S) */ + +/* + * CPU Instance LM32 component configuration + */ +#define CPU_NAME "LM32" +#define CPU_EBA (0x04000000) +#define CPU_DIVIDE_ENABLED (1) +#define CPU_SIGN_EXTEND_ENABLED (1) +#define CPU_MULTIPLIER_ENABLED (1) +#define CPU_SHIFT_ENABLED (1) +#define CPU_DEBUG_ENABLED (1) +#define CPU_HW_BREAKPOINTS_ENABLED (0) +#define CPU_NUM_HW_BREAKPOINTS (0) +#define CPU_NUM_WATCHPOINTS (0) +#define CPU_ICACHE_ENABLED (1) +#define CPU_ICACHE_SETS (512) +#define CPU_ICACHE_ASSOC (1) +#define CPU_ICACHE_BYTES_PER_LINE (16) +#define CPU_DCACHE_ENABLED (1) +#define CPU_DCACHE_SETS (512) +#define CPU_DCACHE_ASSOC (1) +#define CPU_DCACHE_BYTES_PER_LINE (16) +#define CPU_DEBA (0x0C000000) +#define CPU_CHARIO_IN (1) +#define CPU_CHARIO_OUT (1) +#define CPU_CHARIO_TYPE "JTAG UART" + +/* + * gpio component configuration + */ +#define GPIO_NAME "gpio" +#define GPIO_BASE_ADDRESS (0x80004000) +#define GPIO_SIZE (128) +#define GPIO_CHARIO_IN (0) +#define GPIO_CHARIO_OUT (0) +#define GPIO_ADDRESS_LOCK (1) +#define GPIO_DISABLE (0) +#define GPIO_OUTPUT_PORTS_ONLY (1) +#define GPIO_INPUT_PORTS_ONLY (0) +#define GPIO_TRISTATE_PORTS (0) +#define GPIO_BOTH_INPUT_AND_OUTPUT (0) +#define GPIO_DATA_WIDTH (4) +#define GPIO_INPUT_WIDTH (1) +#define GPIO_OUTPUT_WIDTH (1) +#define GPIO_IRQ_MODE (0) +#define GPIO_LEVEL (0) +#define GPIO_EDGE (0) +#define GPIO_EITHER_EDGE_IRQ (0) +#define GPIO_POSE_EDGE_IRQ (0) +#define GPIO_NEGE_EDGE_IRQ (0) + +/* + * uart component configuration + */ +#define UART_NAME "uart" +#define UART_BASE_ADDRESS (0x80006000) +#define UART_SIZE (128) +#define UART_IRQ (0) +#define UART_CHARIO_IN (1) +#define UART_CHARIO_OUT (1) +#define UART_CHARIO_TYPE "RS-232" +#define UART_ADDRESS_LOCK (1) +#define UART_DISABLE (0) +#define UART_MODEM (0) +#define UART_ADDRWIDTH (5) +#define UART_DATAWIDTH (8) +#define UART_BAUD_RATE (115200) +#define UART_IB_SIZE (4) +#define UART_OB_SIZE (4) +#define UART_BLOCK_WRITE (1) +#define UART_BLOCK_READ (1) +#define UART_DATA_BITS (8) +#define UART_STOP_BITS (1) +#define UART_FIFO (0) +#define UART_INTERRUPT_DRIVEN (1) + +/* + * ebr component configuration + */ +#define EBR_NAME "ebr" +#define EBR_BASE_ADDRESS (0x04000000) +#define EBR_SIZE (32768) +#define EBR_IS_READABLE (1) +#define EBR_IS_WRITABLE (1) +#define EBR_ADDRESS_LOCK (1) +#define EBR_DISABLE (0) +#define EBR_EBR_DATA_WIDTH (32) +#define EBR_INIT_FILE_NAME "none" +#define EBR_INIT_FILE_FORMAT "hex" + +/* + * ts_mac_core component configuration + */ +#define TS_MAC_CORE_NAME "ts_mac_core" +#define TS_MAC_CORE_BASE_ADDRESS (0x80008000) +#define TS_MAC_CORE_SIZE (8192) +#define TS_MAC_CORE_IRQ (2) +#define TS_MAC_CORE_CHARIO_IN (0) +#define TS_MAC_CORE_CHARIO_OUT (0) +#define TS_MAC_CORE_ADDRESS_LOCK (1) +#define TS_MAC_CORE_DISABLE (0) +#define TS_MAC_CORE_STAT_REGS (1) +#define TS_MAC_CORE_TXRX_FIFO_DEPTH (512) +#define TS_MAC_CORE_MIIM_MODULE (1) +#define TS_MAC_CORE_NGO "l:/mrf/lattice/crio-lm32/platform1/components/ts_mac_top_v27/ipexpress/ts_mac_core/ts_mac_core.ngo" +#define TS_MAC_CORE_ISPLEVER_PRJ "l:/mrf/lattice/crio-lm32/criomico.syn" + +/* + * timer0 component configuration + */ +#define TIMER0_NAME "timer0" +#define TIMER0_BASE_ADDRESS (0x80002000) +#define TIMER0_SIZE (128) +#define TIMER0_IRQ (1) +#define TIMER0_CHARIO_IN (0) +#define TIMER0_CHARIO_OUT (0) +#define TIMER0_ADDRESS_LOCK (1) +#define TIMER0_DISABLE (0) +#define TIMER0_PERIOD_NUM (20) +#define TIMER0_PERIOD_WIDTH (32) +#define TIMER0_WRITEABLE_PERIOD (1) +#define TIMER0_READABLE_SNAPSHOT (1) +#define TIMER0_START_STOP_CONTROL (1) +#define TIMER0_WATCHDOG (0) + +/* + * timer1 component configuration + */ +#define TIMER1_NAME "timer1" +#define TIMER1_BASE_ADDRESS (0x8000A000) +#define TIMER1_SIZE (128) +#define TIMER1_IRQ (3) +#define TIMER1_CHARIO_IN (0) +#define TIMER1_CHARIO_OUT (0) +#define TIMER1_ADDRESS_LOCK (1) +#define TIMER1_DISABLE (0) +#define TIMER1_PERIOD_NUM (20) +#define TIMER1_PERIOD_WIDTH (32) +#define TIMER1_WRITEABLE_PERIOD (1) +#define TIMER1_READABLE_SNAPSHOT (1) +#define TIMER1_START_STOP_CONTROL (1) +#define TIMER1_WATCHDOG (0) + +/* + * ddr2_sdram component configuration + */ +#define DDR2_SDRAM_NAME "ddr2_sdram" +#define DDR2_SDRAM_BASE_ADDRESS (0x08000000) +#define DDR2_SDRAM_SIZE (33554432) +#define DDR2_SDRAM_IS_READABLE (1) +#define DDR2_SDRAM_IS_WRITABLE (1) +#define DDR2_SDRAM_BST_CNT_READ (1) +#define DDR2_SDRAM_ADDRESS_LOCK (1) +#define DDR2_SDRAM_DISABLE (0) +#define DDR2_SDRAM_NGO "L:/mrf/lattice/cRIO-LM32/platform1/components/wb_ddr2_ctl_v65/ipexpress/ddr2_sdram/ddr2_sdram.ngo" +#define DDR2_SDRAM_ISPLEVER_PRJ "l:/mrf/lattice/crio-lm32/criomico.syn" +#define DDR2_SDRAM_PARAM_FILE "ddr_p_eval/$/src/params/ddr_sdram_mem_params.v" +#define DDR2_SDRAM_MEM_TOP "ddr_p_eval/$/src/rtl/top/@/ddr_sdram_mem_top.v" + + +#endif /* __SYSTEM_CONFIG_H_ */ diff --git a/bsps/lm32/lm32_evr/include/tm27.h b/bsps/lm32/lm32_evr/include/tm27.h new file mode 100644 index 0000000000..f62e62e73f --- /dev/null +++ b/bsps/lm32/lm32_evr/include/tm27.h @@ -0,0 +1,38 @@ +/** + * @file + * + * @ingroup lm32_evr + * + * @brief TM27 timing test routines. + */ + +/* + * tm27.h + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 ) + +#define Cause_tm27_intr() /* empty */ + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/lm32/milkymist/headers.am b/bsps/lm32/milkymist/headers.am new file mode 100644 index 0000000000..1bd114fba1 --- /dev/null +++ b/bsps/lm32/milkymist/headers.am @@ -0,0 +1,7 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/lm32/milkymist/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/lm32/milkymist/include/system_conf.h +include_HEADERS += ../../../../../../bsps/lm32/milkymist/include/tm27.h diff --git a/bsps/lm32/milkymist/include/bsp.h b/bsps/lm32/milkymist/include/bsp.h new file mode 100644 index 0000000000..d8af4a3124 --- /dev/null +++ b/bsps/lm32/milkymist/include/bsp.h @@ -0,0 +1,62 @@ +/** + * @file + * + * @ingroup lm32_milkymist + * + * @brief Global BSP definitions. + */ + +/* bsp.h + * + * This include file contains all board IO definitions. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2011 Sebastien Bourdeauducq + */ + +#ifndef LIBBSP_LM32_MILKYMIST_BSP_H +#define LIBBSP_LM32_MILKYMIST_BSP_H + +#include +#include +#include + +#include + +/** + * @defgroup lm32_milkymist Milkymist Support + * + * @ingroup bsp_lm32 + * + * @brief Milkymist support package. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_HAS_FRAME_BUFFER 1 + +/* + * lm32 requires certain aligment of mbuf because unaligned uint32_t + * accesses are not handled properly. + */ + +#define CPU_U32_FIX + +#if defined(RTEMS_NETWORKING) +struct rtems_bsdnet_ifconfig; +extern int rtems_minimac_driver_attach (struct rtems_bsdnet_ifconfig *config, + int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_minimac_driver_attach +#define RTEMS_BSP_NETWORK_DRIVER_NAME "minimac0" +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/lm32/milkymist/include/system_conf.h b/bsps/lm32/milkymist/include/system_conf.h new file mode 100644 index 0000000000..8ba4a1cf43 --- /dev/null +++ b/bsps/lm32/milkymist/include/system_conf.h @@ -0,0 +1,329 @@ +/** + * @file + * + * @ingroup lm32_milkymist + * + * @brief System configuration. + */ + +/* system_conf.h + * Global System conf + * + * Milkymist port of RTEMS + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * COPYRIGHT (c) 2010, 2011 Sebastien Bourdeauducq + */ + +#ifndef __SYSTEM_CONFIG_H_ +#define __SYSTEM_CONFIG_H_ + +#define UART_BAUD_RATE (115200) + +/* Clock frequency */ +#define MM_FREQUENCY (0xe0001074) + +/* FML bridge */ +#define FMLBRG_FLUSH_BASE (0xc8000000) +#define FMLBRG_LINE_LENGTH (32) +#define FMLBRG_LINE_COUNT (512) + +/* UART */ +#define MM_UART_RXTX (0xe0000000) +#define MM_UART_DIV (0xe0000004) +#define MM_UART_STAT (0xe0000008) +#define MM_UART_CTRL (0xe000000c) + +#define UART_STAT_THRE (0x1) +#define UART_STAT_RX_EVT (0x2) +#define UART_STAT_TX_EVT (0x4) + +#define UART_CTRL_RX_INT (0x1) +#define UART_CTRL_TX_INT (0x2) +#define UART_CTRL_THRU (0x4) + +/* Timers */ +#define MM_TIMER1_COMPARE (0xe0001024) +#define MM_TIMER1_COUNTER (0xe0001028) +#define MM_TIMER1_CONTROL (0xe0001020) + +#define MM_TIMER0_COMPARE (0xe0001014) +#define MM_TIMER0_COUNTER (0xe0001018) +#define MM_TIMER0_CONTROL (0xe0001010) + +#define TIMER_ENABLE (0x01) +#define TIMER_AUTORESTART (0x02) + +/* GPIO */ +#define MM_GPIO_IN (0xe0001000) +#define MM_GPIO_OUT (0xe0001004) +#define MM_GPIO_INTEN (0xe0001008) + +#define GPIO_BTN1 (0x00000001) +#define GPIO_BTN2 (0x00000002) +#define GPIO_BTN3 (0x00000004) +#define GPIO_PCBREV0 (0x00000008) +#define GPIO_PCBREV1 (0x00000010) +#define GPIO_PCBREV2 (0x00000020) +#define GPIO_PCBREV3 (0x00000040) +#define GPIO_LED1 (0x00000001) +#define GPIO_LED2 (0x00000002) + +/* System ID and reset */ +#define MM_SYSTEM_ID (0xe000107c) + +/* ICAP */ +#define MM_ICAP (0xe0001040) + +#define ICAP_READY (0x01) +#define ICAP_CE (0x10000) +#define ICAP_WRITE (0x20000) + +/* VGA */ +#define MM_VGA_RESET (0xe0003000) + +#define MM_VGA_HRES (0xe0003004) +#define MM_VGA_HSYNC_START (0xe0003008) +#define MM_VGA_HSYNC_END (0xe000300C) +#define MM_VGA_HSCAN (0xe0003010) + +#define MM_VGA_VRES (0xe0003014) +#define MM_VGA_VSYNC_START (0xe0003018) +#define MM_VGA_VSYNC_END (0xe000301C) +#define MM_VGA_VSCAN (0xe0003020) + +#define MM_VGA_BASEADDRESS (0xe0003024) +#define MM_VGA_BASEADDRESS_ACT (0xe0003028) + +#define MM_VGA_BURST_COUNT (0xe000302C) + +#define MM_VGA_DDC (0xe0003030) + +#define MM_VGA_CLKSEL (0xe0003034) + +#define VGA_RESET (0x01) +#define VGA_DDC_SDAIN (0x1) +#define VGA_DDC_SDAOUT (0x2) +#define VGA_DDC_SDAOE (0x4) +#define VGA_DDC_SDC (0x8) + +/* Ethernet */ +#define MM_MINIMAC_SETUP (0xe0008000) +#define MM_MINIMAC_MDIO (0xe0008004) + +#define MM_MINIMAC_STATE0 (0xe0008008) +#define MM_MINIMAC_COUNT0 (0xe000800C) +#define MM_MINIMAC_STATE1 (0xe0008010) +#define MM_MINIMAC_COUNT1 (0xe0008014) + +#define MM_MINIMAC_TXCOUNT (0xe0008018) + +#define MINIMAC_RX0_BASE (0xb0000000) +#define MINIMAC_RX1_BASE (0xb0000800) +#define MINIMAC_TX_BASE (0xb0001000) + +#define MINIMAC_SETUP_PHYRST (0x1) + +#define MINIMAC_STATE_EMPTY (0x0) +#define MINIMAC_STATE_LOADED (0x1) +#define MINIMAC_STATE_PENDING (0x2) + +/* AC97 */ +#define MM_AC97_CRCTL (0xe0005000) + +#define AC97_CRCTL_RQEN (0x01) +#define AC97_CRCTL_WRITE (0x02) + +#define MM_AC97_CRADDR (0xe0005004) +#define MM_AC97_CRDATAOUT (0xe0005008) +#define MM_AC97_CRDATAIN (0xe000500C) + +#define MM_AC97_DCTL (0xe0005010) +#define MM_AC97_DADDRESS (0xe0005014) +#define MM_AC97_DREMAINING (0xe0005018) + +#define MM_AC97_UCTL (0xe0005020) +#define MM_AC97_UADDRESS (0xe0005024) +#define MM_AC97_UREMAINING (0xe0005028) + +#define AC97_SCTL_EN (0x01) + +#define AC97_MAX_DMASIZE (0x3fffc) + +/* SoftUSB */ +#define MM_SOFTUSB_CONTROL (0xe000f000) + +#define SOFTUSB_CONTROL_RESET (0x1) + +#define MM_SOFTUSB_PMEM_BASE (0xa0000000) +#define MM_SOFTUSB_DMEM_BASE (0xa0020000) + +#define SOFTUSB_PMEM_SIZE (1 << 13) +#define SOFTUSB_DMEM_SIZE (1 << 13) + +/* PFPU */ +#define MM_PFPU_CTL (0xe0006000) +#define PFPU_CTL_START (0x01) +#define PFPU_CTL_BUSY (0x01) + +#define MM_PFPU_MESHBASE (0xe0006004) +#define MM_PFPU_HMESHLAST (0xe0006008) +#define MM_PFPU_VMESHLAST (0xe000600C) + +#define MM_PFPU_CODEPAGE (0xe0006010) + +#define MM_PFPU_DREGBASE (0xe0006400) +#define MM_PFPU_CODEBASE (0xe0006800) + +#define PFPU_PAGESIZE (512) +#define PFPU_SPREG_COUNT (2) +#define PFPU_REG_X (0) +#define PFPU_REG_Y (1) + +/* TMU */ +#define MM_TMU_CTL (0xe0007000) +#define TMU_CTL_START (0x01) +#define TMU_CTL_BUSY (0x01) +#define TMU_CTL_CHROMAKEY (0x02) + +#define MM_TMU_HMESHLAST (0xe0007004) +#define MM_TMU_VMESHLAST (0xe0007008) +#define MM_TMU_BRIGHTNESS (0xe000700C) +#define MM_TMU_CHROMAKEY (0xe0007010) + +#define MM_TMU_VERTICESADR (0xe0007014) +#define MM_TMU_TEXFBUF (0xe0007018) +#define MM_TMU_TEXHRES (0xe000701C) +#define MM_TMU_TEXVRES (0xe0007020) +#define MM_TMU_TEXHMASK (0xe0007024) +#define MM_TMU_TEXVMASK (0xe0007028) + +#define MM_TMU_DSTFBUF (0xe000702C) +#define MM_TMU_DSTHRES (0xe0007030) +#define MM_TMU_DSTVRES (0xe0007034) +#define MM_TMU_DSTHOFFSET (0xe0007038) +#define MM_TMU_DSTVOFFSET (0xe000703C) +#define MM_TMU_DSTSQUAREW (0xe0007040) +#define MM_TMU_DSTSQUAREH (0xe0007044) + +#define MM_TMU_ALPHA (0xe0007048) + +/* Memory card */ +#define MM_MEMCARD_CLK2XDIV (0xe0004000) + +#define MM_MEMCARD_ENABLE (0xe0004004) + +#define MEMCARD_ENABLE_CMD_TX (0x1) +#define MEMCARD_ENABLE_CMD_RX (0x2) +#define MEMCARD_ENABLE_DAT_TX (0x4) +#define MEMCARD_ENABLE_DAT_RX (0x8) + +#define MM_MEMCARD_PENDING (0xe0004008) + +#define MEMCARD_PENDING_CMD_TX (0x1) +#define MEMCARD_PENDING_CMD_RX (0x2) +#define MEMCARD_PENDING_DAT_TX (0x4) +#define MEMCARD_PENDING_DAT_RX (0x8) + +#define MM_MEMCARD_START (0xe000400c) + +#define MEMCARD_START_CMD_RX (0x1) +#define MEMCARD_START_DAT_RX (0x2) + +#define MM_MEMCARD_CMD (0xe0004010) +#define MM_MEMCARD_DAT (0xe0004014) + +/* DMX */ +#define MM_DMX_TX(x) (0xe000c000+4*(x)) +#define MM_DMX_THRU (0xe000c800) +#define MM_DMX_RX(x) (0xe000d000+4*(x)) + +/* MIDI */ +#define MM_MIDI_RXTX (0xe000b000) +#define MM_MIDI_DIV (0xe000b004) +#define MM_MIDI_STAT (0xe000b008) +#define MM_MIDI_CTRL (0xe000b00c) + +#define MIDI_STAT_THRE (0x1) +#define MIDI_STAT_RX_EVT (0x2) +#define MIDI_STAT_TX_EVT (0x4) + +#define MIDI_CTRL_RX_INT (0x1) +#define MIDI_CTRL_TX_INT (0x2) +#define MIDI_CTRL_THRU (0x4) + +/* IR */ +#define MM_IR_RX (0xe000e000) + +/* Video input */ +#define MM_BT656_I2C (0xe000a000) +#define MM_BT656_FILTERSTATUS (0xe000a004) +#define MM_BT656_BASE (0xe000a008) +#define MM_BT656_MAXBURSTS (0xe000a00c) +#define MM_BT656_DONEBURSTS (0xe000a010) + +#define BT656_I2C_SDAIN (0x1) +#define BT656_I2C_SDAOUT (0x2) +#define BT656_I2C_SDAOE (0x4) +#define BT656_I2C_SDC (0x8) + +#define BT656_FILTER_FIELD1 (0x1) +#define BT656_FILTER_FIELD2 (0x2) +#define BT656_FILTER_INFRAME (0x4) + +/* Interrupts */ +#define MM_IRQ_UART (0) +#define MM_IRQ_GPIO (1) +#define MM_IRQ_TIMER0 (2) +#define MM_IRQ_TIMER1 (3) +#define MM_IRQ_AC97CRREQUEST (4) +#define MM_IRQ_AC97CRREPLY (5) +#define MM_IRQ_AC97DMAR (6) +#define MM_IRQ_AC97DMAW (7) +#define MM_IRQ_PFPU (8) +#define MM_IRQ_TMU (9) +#define MM_IRQ_ETHRX (10) +#define MM_IRQ_ETHTX (11) +#define MM_IRQ_VIDEOIN (12) +#define MM_IRQ_MIDI (13) +#define MM_IRQ_IR (14) +#define MM_IRQ_USB (15) + +/* Flash layout */ +#define FLASH_BASE (0x80000000) + +#define FLASH_OFFSET_STANDBY_BITSTREAM (0x80000000) + +#define FLASH_OFFSET_RESCUE_BITSTREAM (0x800A0000) +#define FLASH_OFFSET_RESCUE_BIOS (0x80220000) +#define FLASH_OFFSET_MAC_ADDRESS (0x802200E0) +#define FLASH_OFFSET_RESCUE_SPLASH (0x80240000) +#define FLASH_OFFSET_RESCUE_APP (0x802E0000) + +#define FLASH_OFFSET_REGULAR_BITSTREAM (0x806E0000) +#define FLASH_OFFSET_REGULAR_BIOS (0x80860000) +#define FLASH_OFFSET_REGULAR_SPLASH (0x80880000) +#define FLASH_OFFSET_REGULAR_APP (0x80920000) + +/* MMIO */ +#define MM_READ(reg) (*((volatile unsigned int *)(reg))) +#define MM_WRITE(reg, val) *((volatile unsigned int *)(reg)) = val + +/* Flash partitions */ + +#define FLASH_SECTOR_SIZE (128*1024) + +#define FLASH_PARTITION_COUNT (5) + +#define FLASH_PARTITIONS { \ + { .start_address = 0x806E0000, .length = 0x0180000 }, \ + { .start_address = 0x80860000, .length = 0x0020000 }, \ + { .start_address = 0x80880000, .length = 0x00A0000 }, \ + { .start_address = 0x80920000, .length = 0x0400000 }, \ + { .start_address = 0x80D20000, .length = 0x12E0000 }, \ +} + +#endif /* __SYSTEM_CONFIG_H_ */ diff --git a/bsps/lm32/milkymist/include/tm27.h b/bsps/lm32/milkymist/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/lm32/milkymist/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/m32c/m32cbsp/headers.am b/bsps/m32c/m32cbsp/headers.am new file mode 100644 index 0000000000..463baaeb43 --- /dev/null +++ b/bsps/m32c/m32cbsp/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m32c/m32cbsp/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m32c/m32cbsp/include/tm27.h diff --git a/bsps/m32c/m32cbsp/include/bsp.h b/bsps/m32c/m32cbsp/include/bsp.h new file mode 100644 index 0000000000..b7c6891e09 --- /dev/null +++ b/bsps/m32c/m32cbsp/include/bsp.h @@ -0,0 +1,49 @@ +/** + * @file + * + * @ingroup m32c_bsp + * + * @brief m32c simulator definitions in gdb + */ + +/* bsp.h + * + * This include file contains some definitions specific to the + * h8 simulator in gdb. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M32C_M32CBSP_BSP_H +#define LIBBSP_M32C_M32CBSP_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup m32c_bsp Clock Tick Support + * + * @ingroup m32c_m32cbsp + * + * @brief Clock Tick Support Package + */ + +void *clock_driver_sim_idle_body(uintptr_t); +#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m32c/m32cbsp/include/tm27.h b/bsps/m32c/m32cbsp/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/m32c/m32cbsp/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/m68k/av5282/headers.am b/bsps/m68k/av5282/headers.am new file mode 100644 index 0000000000..a6a9154900 --- /dev/null +++ b/bsps/m68k/av5282/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/av5282/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/av5282/include/tm27.h diff --git a/bsps/m68k/av5282/include/bsp.h b/bsps/m68k/av5282/include/bsp.h new file mode 100644 index 0000000000..a8b32e745e --- /dev/null +++ b/bsps/m68k/av5282/include/bsp.h @@ -0,0 +1,97 @@ +/** + * @file + * + * @ingroup m68k_av5282 + * + * @brief Global BSP definitions. + */ + +/* + * av5282 BSP header file + */ + +/** + * @defgroup m68k_av5282 AV5282 Support + * + * @ingroup bsp_m68k + * + * @brief AV5282 support. + */ + +#ifndef LIBBSP_M68K_AV5282_BSP_H +#define LIBBSP_M68K_AV5282_BSP_H + +#ifndef ASM + +#include +#include + +#include +#include + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include /* internal MCF5282 modules */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ +/** Network driver configuration **/ +struct rtems_bsdnet_ifconfig; +extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "fs1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* externals */ + +/* constants */ + +/* miscellaneous stuff assumed to exist */ + +/* functions */ + +uint32_t get_CPU_clock_speed(void); + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ +#define FEC_IRQ_LEVEL 4 +#define FEC_IRQ_RX_PRIORITY 7 +#define FEC_IRQ_TX_PRIORITY 6 + +#define PIT3_IRQ_LEVEL 4 +#define PIT3_IRQ_PRIORITY 0 + +#define UART0_IRQ_LEVEL 3 +#define UART0_IRQ_PRIORITY 7 +#define UART1_IRQ_LEVEL 3 +#define UART1_IRQ_PRIORITY 6 +#define UART2_IRQ_LEVEL 3 +#define UART2_IRQ_PRIORITY 5 + +/* + * Prototypes for methods called from .S to alow dependency tracking + */ +void Init5282(void); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ +#endif diff --git a/bsps/m68k/av5282/include/tm27.h b/bsps/m68k/av5282/include/tm27.h new file mode 100644 index 0000000000..1e1dc77e59 --- /dev/null +++ b/bsps/m68k/av5282/include/tm27.h @@ -0,0 +1,37 @@ +/** + * @file + * + * @ingroup m68k_av5282 + * + * @brief Time Test 27 routines. + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/csb360/headers.am b/bsps/m68k/csb360/headers.am new file mode 100644 index 0000000000..5c713a234d --- /dev/null +++ b/bsps/m68k/csb360/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/csb360/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/csb360/include/tm27.h diff --git a/bsps/m68k/csb360/include/bsp.h b/bsps/m68k/csb360/include/bsp.h new file mode 100644 index 0000000000..5272e17ae2 --- /dev/null +++ b/bsps/m68k/csb360/include/bsp.h @@ -0,0 +1,189 @@ +/** + * @file + * + * @ingroup m68k_csb360 + * + * @brief Global BSP definitions. + */ + +/* + * Board Support Package for CSB360 evaluation board + * BSP definitions + * + * Copyright 2004 Cogent Computer Systems + * Author: Jay Monkman + * + * Derived from mcf5206elite BSP: + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_CSB360_BSP_H +#define LIBBSP_M68K_CSB360_BSP_H + +#include + +/** + * @defgroup m68k_csb360 CSB360 Support + * + * @ingroup bsp_m68k + * + * @brief CSB360 support. + */ + + +/*** Board resources allocation ***/ +#define BSP_MEM_ADDR_SRAM 0x20000000 +#define BSP_MEM_SIZE_SRAM 4096 + +/* Location and size of sdram. Note this includes space used by + * umon. + */ +#define BSP_MEM_ADDR_SDRAM 0x00000000 +#define BSP_MEM_MASK_SDRAM 0x01ffffff +#define BSP_MEM_SIZE_SDRAM (32 * 1024 * 1024) + +/* Address to put SIM Modules */ +#define BSP_MBAR 0x10000000 + +/* Address to put SRAM */ +#define BSP_RAMBAR BSP_MEM_ADDR_SRAM + +/* Interrupt Vectors */ +#define BSP_INTVEC_INT1 65 +#define BSP_INTVEC_INT2 66 +#define BSP_INTVEC_INT3 67 +#define BSP_INTVEC_INT4 68 +#define BSP_INTVEC_TMR0 69 +#define BSP_INTVEC_TMR1 70 +#define BSP_INTVEC_TMR2 71 +#define BSP_INTVEC_TMR3 72 +#define BSP_INTVEC_UART1 73 +#define BSP_INTVEC_UART2 74 +#define BSP_INTVEC_PLIP 75 +#define BSP_INTVEC_PLIA 76 +#define BSP_INTVEC_USB0 77 +#define BSP_INTVEC_USB1 78 +#define BSP_INTVEC_USB2 79 +#define BSP_INTVEC_USB3 80 +#define BSP_INTVEC_USB4 81 +#define BSP_INTVEC_USB5 82 +#define BSP_INTVEC_USB6 83 +#define BSP_INTVEC_USB7 84 +#define BSP_INTVEC_DMA 85 +#define BSP_INTVEC_ERX 86 +#define BSP_INTVEC_ETX 87 +#define BSP_INTVEC_ENTC 88 +#define BSP_INTVEC_QSPI 89 +#define BSP_INTVEC_INT5 90 +#define BSP_INTVEC_INT6 91 +#define BSP_INTVEC_SWTO 92 + +#define BSP_INTLVL_INT1 1 +#define BSP_INTLVL_INT2 1 +#define BSP_INTLVL_INT3 1 +#define BSP_INTLVL_INT4 1 +#define BSP_INTLVL_TMR0 1 +#define BSP_INTLVL_TMR1 1 +#define BSP_INTLVL_TMR2 1 +#define BSP_INTLVL_TMR3 1 +#define BSP_INTLVL_UART1 1 +#define BSP_INTLVL_UART2 1 +#define BSP_INTLVL_PLIP 1 +#define BSP_INTLVL_PLIA 1 +#define BSP_INTLVL_USB0 1 +#define BSP_INTLVL_USB1 1 +#define BSP_INTLVL_USB2 1 +#define BSP_INTLVL_USB3 1 +#define BSP_INTLVL_USB4 1 +#define BSP_INTLVL_USB5 1 +#define BSP_INTLVL_USB6 1 +#define BSP_INTLVL_USB7 1 +#define BSP_INTLVL_DMA 1 +#define BSP_INTLVL_ERX 1 +#define BSP_INTLVL_ETX 1 +#define BSP_INTLVL_ENTC 1 +#define BSP_INTLVL_QSPI 1 +#define BSP_INTLVL_INT5 1 +#define BSP_INTLVL_INT6 1 +#define BSP_INTLVL_SWTO 1 + + + +#ifndef ASM + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct rtems_bsdnet_ifconfig; +extern int rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_enet_driver_attach + +/* System frequency */ +#define BSP_SYSTEM_FREQUENCY (66 * 1000 * 1000) + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#define rtems_bsp_delay( microseconds ) \ + { register uint32_t _delay=(microseconds); \ + register uint32_t _tmp=123; \ + __asm__ volatile( "0: \ + nbcd %0 ; \ + nbcd %0 ; \ + dbf %1,0b" \ + : "=d" (_tmp), "=d" (_delay) \ + : "0" (_tmp), "1" (_delay) ); \ + } + +/* + * Real-Time Clock Driver Table Entry + * NOTE: put this entry to the device driver table AFTER I2C bus driver! + */ +#define RTC_DRIVER_TABLE_ENTRY \ + { rtc_initialize, NULL, NULL, NULL, NULL, NULL } +extern rtems_device_driver rtc_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +/* miscellaneous stuff assumed to exist */ + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +extern rtems_isr (*rtems_clock_hook)(rtems_vector_number); + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void init5272(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif diff --git a/bsps/m68k/csb360/include/tm27.h b/bsps/m68k/csb360/include/tm27.h new file mode 100644 index 0000000000..5f2fd8a383 --- /dev/null +++ b/bsps/m68k/csb360/include/tm27.h @@ -0,0 +1,39 @@ +/** + * @file + * + * @ingroup m68k_csb360 + * + * @brief Time Test 27 routines. + */ + +/* + * tm27.h + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 34, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #2"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/gen68340/headers.am b/bsps/m68k/gen68340/headers.am new file mode 100644 index 0000000000..ca3dba2b1e --- /dev/null +++ b/bsps/m68k/gen68340/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/m340timer.h +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/m340uart.h +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/m68340.h +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/m68340.inc +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/m68349.inc +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/tm27.h diff --git a/bsps/m68k/gen68340/include/bsp.h b/bsps/m68k/gen68340/include/bsp.h new file mode 100644 index 0000000000..28d86ff2f7 --- /dev/null +++ b/bsps/m68k/gen68340/include/bsp.h @@ -0,0 +1,81 @@ +/** + * @file + * + * @ingroup m68k_gen68340 + * + * @brief Global BSP definitions. + */ + +/* + * Board Support Package for `Generic' Motorola MC68340 + * + * Based on the `gen68360' board support package, and covered by the + * original distribution terms. + */ + +/* bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_GEN68340_BSP_H +#define LIBBSP_M68K_GEN68340_BSP_H + +#ifndef ASM + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup m68k_gen68340 Motorola MC68340 Support + * + * @ingroup bsp_m68k + * + * @brief Motorola MC68340 support. + */ + +/* Constants */ + +/* Structures */ + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Methods used across files inside the BSP + */ +int dbug_in_char( int minor ); +void dbug_out_char( int minor, int ch ); +int dbug_char_present( int minor ); +void _dbug_dumpanic(void); + +/* + * Only called from .S but prototyped here to capture the dependecy. + */ +void _Init68340 (void); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/m68k/gen68340/include/m340timer.h b/bsps/m68k/gen68340/include/m340timer.h new file mode 100644 index 0000000000..892c690e5f --- /dev/null +++ b/bsps/m68k/gen68340/include/m340timer.h @@ -0,0 +1,85 @@ +/** + * @file + * + * @ingroup m68k_gen68340 + * + * @brief Time driver definitions. + */ + +/* + * Header file for timer driver + * defines for accessing M68340 timer registers + * + * Author: + * Geoffroy Montel + * France Telecom - CNET/DSM/TAM/CAT + * 4, rue du Clos Courtel + * 35512 CESSON-SEVIGNE + * FRANCE + * + * e-mail: g_montel@yahoo.com + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __m340timer_H__ +#define __m340timer_H__ + +extern void Fifo_Full_benchmark_timer_initialize (void); + +extern void (*Restart_Fifo_Full_A_Timer)(); +extern void (*Restart_Check_A_Timer)(); +extern void (*Restart_Fifo_Full_B_Timer)(); +extern void (*Restart_Check_B_Timer)(); + +/* CR */ +#define m340_SWR (1<<15) +#define m340_Polling_Mode (0<<12) +#define m340_TC_Enabled (1<<12) +#define m340_TG_Enabled (2<<12) +#define m340_TG_TC_Enabled (3<<12) +#define m340_TO_Enabled (4<<12) +#define m340_TO_TC_Enabled (5<<12) +#define m340_TG_TG_Enabled (6<<12) +#define m340_TO_TG_TG_Enabled (7<<12) +#define m340_TGE (1<<11) +#define m340_PSE (1<<10) +#define m340_CPE (1<<9) +#define m340_CLK (1<<8) +#define m340_Divide_by_2 (1<<5) +#define m340_Divide_by_4 (2<<5) +#define m340_Divide_by_8 (3<<5) +#define m340_Divide_by_16 (4<<5) +#define m340_Divide_by_32 (5<<5) +#define m340_Divide_by_64 (6<<5) +#define m340_Divide_by_128 (7<<5) +#define m340_Divide_by_256 (0<<5) +#define m340_ICOC (0<<2) +#define m340_SWG (1<<2) +#define m340_VDCSWG (2<<2) +#define m340_VWSSPG (3<<2) +#define m340_PWM (4<<2) +#define m340_PM (5<<2) +#define m340_EC (6<<2) +#define m340_TB (7<<2) +#define m340_Disabled 0 +#define m340_Toggle_Mode 1 +#define m340_Zero_Mode 2 +#define m340_One_Mode 3 + +/* SR */ +#define m340_IRQ (1<<15) +#define m340_TO (1<<14) +#define m340_TG (1<<13) +#define m340_TC (1<<12) +#define m340_TGL (1<<11) +#define m340_ON (1<<10) +#define m340_OUT (1<<9) +#define m340_COM (1<<8) + +#endif diff --git a/bsps/m68k/gen68340/include/m340uart.h b/bsps/m68k/gen68340/include/m340uart.h new file mode 100644 index 0000000000..619a732a14 --- /dev/null +++ b/bsps/m68k/gen68340/include/m340uart.h @@ -0,0 +1,162 @@ +/** + * @file + * + * @ingroup m68k_gen68340 + * + * @brief UART console driver definitions. + */ + +/* + * Header file for console driver + * defines for accessing M68340/68349 UART registers + * + * Author: + * Geoffroy Montel + * France Telecom - CNET/DSM/TAM/CAT + * 4, rue du Clos Courtel + * 35512 CESSON-SEVIGNE + * FRANCE + * + * e-mail: g_montel@yahoo.com + * + * + * COPYRIGHT (c) 1989-2008. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __m340uart_H__ +#define __m340uart_H__ + +/* UART initialisation */ +#define UART_CHANNEL_A 0 +#define UART_CHANNEL_B 1 +#define UART_NUMBER_OF_CHANNELS 2 +#define UART_CONSOLE_NAME "/dev/console" +#define UART_RAW_IO_NAME "/dev/tty1" +#define UART_FIFO_FULL 0 +#define UART_CRR 1 +#define UART_INTERRUPTS 0 +#define UART_POLLING 1 +#define UART_TERMIOS_CONSOLE 0 +#define UART_TERMIOS_RAW 1 +#define UART_TERMIOS_MIN_DEFAULT 1 +#define UART_TERMIOS_TIME_DEFAULT 0 + +void Init_UART_Table(void); + +typedef struct { + uint8_t enable; + uint16_t rx_buffer_size; /* NOT IMPLEMENTED */ + uint16_t tx_buffer_size; /* NOT IMPLEMENTED */ + } uart_termios_config; + +typedef struct { /* for one channel */ + uint8_t enable; /* use this channel */ + char name[64]; /* use UART_CONSOLE_NAME for console purpose */ + uint8_t parity_mode; /* parity mode, see MR1 section for defines */ + uint8_t bits_per_char; /* bits per character, see MR1 section for defines */ + float rx_baudrate; /* Rx baudrate */ + float tx_baudrate; /* Tx baudrate */ + uint8_t rx_mode; /* FIFO Full (UART_FIFO_FULL) or ChannelReceiverReady (UART_CRR) */ + uint8_t mode; /* use interrupts (UART_INTERRUPTS) or polling (UART_POLLING) */ + uart_termios_config termios; + } uart_channel_config; + +extern uart_channel_config m340_uart_config[UART_NUMBER_OF_CHANNELS]; + +typedef struct { + int set; /* number of the m340 baud speed set */ + int rcs; /* RCS for the needed baud set */ + int tcs; /* TCS for the needed baud set */ + } t_baud_speed; + +typedef struct { + t_baud_speed baud_speed_table[2]; + short nb; + } t_baud_speed_table; + +extern t_baud_speed_table +Find_Right_m340_UART_Config(float ChannelA_ReceiverBaudRate, float ChannelA_TransmitterBaudRate, uint8_t enableA, + float ChannelB_ReceiverBaudRate, float ChannelB_TransmitterBaudRate, uint8_t enableB); + +extern rtems_isr InterruptHandler (rtems_vector_number v); + +extern int dbugRead (int minor); +extern ssize_t dbugWrite (int minor, const char *buf, size_t len); + +extern float m340_Baud_Rates_Table[16][2]; + +/* SR */ +#define m340_Rx_RDY 1 +#define m340_FFULL (1<<1) +#define m340_Tx_RDY (1<<2) +#define m340_TxEMP (1<<3) +#define m340_OE (1<<4) +#define m340_PE (1<<5) +#define m340_FE (1<<6) +#define m340_RB (1<<7) + +/* IER */ +#define m340_TxRDYA 1 +#define m340_RxRDYA (1<<1) +#define m340_TxRxRDYA 0x3 +#define m340_TxRDYB (1<<4) +#define m340_RxRDYB (1<<5) +#define m340_TxRxRDYB 0x30 + +/* CR */ +#define m340_Reset_Error_Status 0x40 +#define m340_Reset_Receiver 0x20 +#define m340_Reset_Transmitter 0x30 +#define m340_Transmitter_Enable (1<<2) +#define m340_Receiver_Enable 1 +#define m340_Transmitter_Disable (2<<2) +#define m340_Receiver_Disable 2 + +/* ACR */ +#define m340_BRG_Set1 0 +#define m340_BRG_Set2 (1<<7) + +/* OPCR */ +#define m340_OPCR_Gal 0x0 +#define m340_OPCR_Aux 0xFF + +/* ISR */ +#define m340_COS (1<<7) +#define m340_DBB (1<<6) +#define m340_XTAL_RDY (1<<3) +#define m340_DBA (1<<2) + +/* MR1 */ +#define m340_RxRTS (1<<7) +#define m340_R_F (1<<6) /* character or block mode */ +#define m340_ERR (1<<5) +#define m340_RxRTX (1<<7) +#define m340_Even_Parity 0 +#define m340_Odd_Parity (1<<2) +#define m340_Low_Parity (2<<2) +#define m340_High_Parity (3<<2) +#define m340_No_Parity (4<<2) +#define m340_Data_Character (6<<2) +#define m340_Address_Character (7<<2) +#define m340_5bpc 0x0 +#define m340_6bpc 0x1 +#define m340_7bpc 0x2 +#define m340_8bpc 0x3 + +/* MR2 */ +#define m340_normal (0<<6) +#define m340_automatic_echo (1<<6) +#define m340_local_loopback (2<<6) +#define m340_remote_loopback (3<<6) +#define m340_TxRTS (1<<5) +#define m340_TxCTS (1<<4) + +/* Baud rates for Transmitter/Receiver */ +#define SCLK 1 /* put your own SCLK value here */ + +#endif diff --git a/bsps/m68k/gen68340/include/m68340.h b/bsps/m68k/gen68340/include/m68340.h new file mode 100644 index 0000000000..37440f3098 --- /dev/null +++ b/bsps/m68k/gen68340/include/m68340.h @@ -0,0 +1,145 @@ +/** + * @file + * + * @ingroup m68k_gen68340 + * + * @brief MC68430 definitions. + */ + +/********************************************************************** + * MC68340 C Header File * + * * + * Developed by : Motorola * + * High Performance Embedded Systems Division * + * Austin, TX * + * Rectified by : Geoffroy Montel + * g_montel@yahoo.com * + * * + **********************************************************************/ + +typedef volatile unsigned char * portb; /* 8-bit port */ +typedef volatile unsigned short * portw; /* 16-bit port */ +typedef volatile unsigned int * portl; /* 32-bit port */ + +#define MBASE 0xEFFFF000 /* Module Base Address */ + /* not EFFFF000 due to a 68349 + hardware incompatibility */ + +#define MBAR (*(portb) 0x0003FF00) /* Module Base Addr Reg */ +#define MBAR1 (*(portb) 0x0003FF00) /* Module Base Addr Reg 1 (MSW) */ +#define MBAR2 (*(portb) 0x0003FF02) /* Module Base Addr Reg 2 (LSW) */ + +/* System Integration Module */ + +#define SIMMCR (*(portw) (MBASE+0x0000)) /* SIM Module Config Reg */ +#define SIMSYNCR (*(portw) (MBASE+0x0004)) /* SIM Clock Synth Cont Reg */ +#define SIMAVR (*(portb) (MBASE+0x0006)) /* SIM Autovector Reg */ +#define SIMRSR (*(portb) (MBASE+0x0007)) /* SIM Reset Status Reg */ +#define SIMPORTA (*(portb) (MBASE+0x0011)) /* SIM Port A Data Reg */ +#define SIMDDRA (*(portb) (MBASE+0x0013)) /* SIM Port A Data Dir Reg */ +#define SIMPPRA1 (*(portb) (MBASE+0x0015)) /* SIM Port A Pin Asm 1 Reg */ +#define SIMPPRA2 (*(portb) (MBASE+0x0017)) /* SIM Port A Pin Asm 2 Reg */ +#define SIMPORTB (*(portb) (MBASE+0x0019)) /* SIM Port B Data Reg */ +#define SIMPORTB1 (*(portb) (MBASE+0x001B)) /* SIM Port B Data Reg */ +#define SIMDDRB (*(portb) (MBASE+0x001D)) /* SIM Port B Data Dir Reg */ +#define SIMPPARB (*(portb) (MBASE+0x001F)) /* SIM Port B Pin Asm Reg */ +#define SIMSWIV (*(portb) (MBASE+0x0020)) /* SIM SW Interrupt Vector */ +#define SIMSYPCR (*(portb) (MBASE+0x0021)) /* SIM System Prot Cont Reg */ +#define SIMPICR (*(portw) (MBASE+0x0022)) /* SIM Period Intr Cont Reg */ +#define SIMPITR (*(portw) (MBASE+0x0024)) /* SIM Period Intr Tmg Reg */ +#define SIMSWSR (*(portb) (MBASE+0x0027)) /* SIM Software Service Reg */ + +#define SIMCS0AM (*(portl) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk */ +#define SIMCS0AM1 (*(portw) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk 1 */ +#define SIMCS0AM2 (*(portw) (MBASE+0x0042)) /* SIM Chp Sel 0 Addr Msk 2 */ +#define SIMCS0BA (*(portl) (MBASE+0x0044)) /* SIM Chp Sel 0 Base Addr */ +#define SIMCS0BA1 (*(portw) (MBASE+0x0044)) /* SIM Chp Sel 0 Bas Addr 1 */ +#define SIMCS0BA2 (*(portw) (MBASE+0x0046)) /* SIM Chp Sel 0 Bas Addr 2 */ +#define SIMCS1AM (*(portl) (MBASE+0x0048)) /* SIM Chp Sel 1 Adress Msk */ +#define SIMCS1AM1 (*(portw) (MBASE+0x0048)) /* SIM Chp Sel 1 Addr Msk 1 */ +#define SIMCS1AM2 (*(portw) (MBASE+0x004A)) /* SIM Chp Sel 1 Addr Msk 2 */ +#define SIMCS1BA (*(portl) (MBASE+0x004C)) /* SIM Chp Sel 1 Base Addr */ +#define SIMCS1BA1 (*(portw) (MBASE+0x004C)) /* SIM Chp Sel 1 Bas Addr 1 */ +#define SIMCS1BA2 (*(portw) (MBASE+0x004E)) /* SIM Chp Sel 1 Bas Addr 2 */ +#define SIMCS2AM (*(portl) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk */ +#define SIMCS2AM1 (*(portw) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk 1 */ +#define SIMCS2AM2 (*(portw) (MBASE+0x0052)) /* SIM Chp Sel 2 Addr Msk 2 */ +#define SIMCS2BA (*(portl) (MBASE+0x0054)) /* SIM Chp Sel 2 Base Addr */ +#define SIMCS2BA1 (*(portw) (MBASE+0x0054)) /* SIM Chp Sel 2 Bas Addr 1 */ +#define SIMCS2BA2 (*(portw) (MBASE+0x0056)) /* SIM Chp Sel 2 Bas Addr 2 */ +#define SIMCS3AM (*(portl) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk */ +#define SIMCS3AM1 (*(portw) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk 1 */ +#define SIMCS3AM2 (*(portw) (MBASE+0x005A)) /* SIM Chp Sel 3 Addr Msk 2 */ +#define SIMCS3BA (*(portl) (MBASE+0x005C)) /* SIM Chp Sel 3 Base Addr */ +#define SIMCS3BA1 (*(portw) (MBASE+0x005C)) /* SIM Chp Sel 3 Bas Addr 1 */ +#define SIMCS3BA2 (*(portw) (MBASE+0x005E)) /* SIM Chp Sel 3 Bas Addr 2 */ + +/* Dynamic Memory Access (DMA) Module */ + +#define DMAMCR1 (*(portw) (MBASE+0x0780)) /* DMA Module Config Reg 1 */ +#define DMAINTR1 (*(portw) (MBASE+0x0784)) /* DMA Interrupt Reg 1 */ +#define DMACCR1 (*(portw) (MBASE+0x0788)) /* DMA Channel Cont Reg 1 */ +#define DMACSR1 (*(portb) (MBASE+0x078A)) /* DMA Channel Status Reg 1 */ +#define DMAFCR1 (*(portb) (MBASE+0x078B)) /* DMA Function Code Reg 1 */ +#define DMASAR1 (*(portl) (MBASE+0x078C)) /* DMA DMA Src Addr Reg 1 */ +#define DMADAR1 (*(portl) (MBASE+0x0790)) /* DMA Dest Addr Reg 1 */ +#define DMABTC1 (*(portb) (MBASE+0x079l)) /* DMA Byte Trans Cnt Reg 1 */ + +#define DMAMCR2 (*(portw) (MBASE+0x07A0)) /* DMA Module Config Reg 2 */ +#define DMAINTR2 (*(portw) (MBASE+0x07A4)) /* DMA Interrupt Reg 2 */ +#define DMACCR2 (*(portw) (MBASE+0x07A8)) /* DMA Channel Cont Reg 2 */ +#define DMACSR2 (*(portb) (MBASE+0x07AA)) /* DMA Channel Status Reg 2 */ +#define DMAFCR2 (*(portb) (MBASE+0x07AB)) /* DMA Function Code Reg 1 */ +#define DMASAR2 (*(portl) (MBASE+0x07AC)) /* DMA Source Addr Reg 2 */ +#define DMADAR2 (*(portl) (MBASE+0x07B0)) /* DMA Dest Addr Reg 2 */ +#define DMABTC2 (*(portb) (MBASE+0x07B4)) /* DMA Byte Trans Cnt Reg 2 */ + +/* Dual Serial Module */ + +#define DUMCRH (*(portb) (MBASE+0x0700)) /* DUART Module Config Reg */ +#define DUMCRL (*(portb) (MBASE+0x0701)) /* DUART Module Config Reg */ +#define DUILR (*(portb) (MBASE+0x0704)) /* DUART Interrupt Level */ +#define DUIVR (*(portb) (MBASE+0x0705)) /* DUART Interrupt Vector */ +#define DUMR1A (*(portb) (MBASE+0x0710)) /* DUART Mode Reg 1A */ +#define DUSRA (*(portb) (MBASE+0x0711)) /* DUART Status Reg A */ +#define DUCSRA (*(portb) (MBASE+0x0711)) /* DUART Clock Sel Reg A */ +#define DUCRA (*(portb) (MBASE+0x0712)) /* DUART Command Reg A */ +#define DURBA (*(portb) (MBASE+0x0713)) /* DUART Receiver Buffer A */ +#define DUTBA (*(portb) (MBASE+0x0713)) /* DUART Transmitter Buff A */ +#define DUIPCR (*(portb) (MBASE+0x0714)) /* DUART Input Port Chg Reg */ +#define DUACR (*(portb) (MBASE+0x0714)) /* DUART Auxiliary Cont Reg */ +#define DUISR (*(portb) (MBASE+0x0715)) /* DUART Interrupt Stat Reg */ +#define DUIER (*(portb) (MBASE+0x0715)) /* DUART Interrupt Enb Reg */ + +#define DUMR1B (*(portb) (MBASE+0x0718)) /* DUART Mode Reg 1B */ +#define DUSRB (*(portb) (MBASE+0x0719)) /* DUART Status Reg B */ +#define DUCSRB (*(portb) (MBASE+0x0719)) /* DUART Clock Sel Reg B */ +#define DUCRB (*(portb) (MBASE+0x071A)) /* DUART Command Reg B */ +#define DURBB (*(portb) (MBASE+0x071B)) /* DUART Receiver Buffer B */ +#define DUTBB (*(portb) (MBASE+0x071B)) /* DUART Transmitter Buff B */ +#define DUIP (*(portb) (MBASE+0x071D)) /* DUART Input Port Reg */ +#define DUOPCR (*(portb) (MBASE+0x071D)) /* DUART Outp Port Cnt Reg */ +#define DUOPBS (*(portb) (MBASE+0x071E)) /* DUART Outp Port Bit Set */ +#define DUOPBR (*(portb) (MBASE+0x071F)) /* DUART Outp Port Bit Rst */ +#define DUMR2A (*(portb) (MBASE+0x0720)) /* DUART Mode Reg 2A */ +#define DUMR2B (*(portb) (MBASE+0x0721)) /* DUART Mode Reg 2B */ + +/* Dual Timer Module */ + +#define TMCR1 (*(portw) (MBASE+0x0600)) /* Timer Module Config Reg 1 */ +#define TIR1 (*(portw) (MBASE+0x0604)) /* Timer Interrupt Reg 1 */ +#define TCR1 (*(portw) (MBASE+0x0606)) /* Timer Control Reg 1 */ +#define TSR1 (*(portw) (MBASE+0x0608)) /* Timer Status Reg 1 */ +#define TCNTR1 (*(portw) (MBASE+0x060A)) /* Timer Counter Reg 1 */ +#define WPREL11 (*(portw) (MBASE+0x060C)) /* Timer Preload 1 Reg 1 */ +#define WPREL21 (*(portw) (MBASE+0x060E)) /* Timer Preload 2 Reg 1 */ +#define TCOM1 (*(portw) (MBASE+0x0610)) /* Timer Compare Reg 1 */ + +#define TMCR2 (*(portw) (MBASE+0x0640)) /* Timer Module Config Reg 2 */ +#define TIR2 (*(portw) (MBASE+0x0644)) /* Timer Interrupt Reg 2 */ +#define TCR2 (*(portw) (MBASE+0x0646)) /* Timer Control Reg 2 */ +#define TSR2 (*(portw) (MBASE+0x0648)) /* Timer Status Reg 2 */ +#define TCNTR2 (*(portw) (MBASE+0x064A)) /* Timer Counter Reg 2 */ +#define WPREL12 (*(portw) (MBASE+0x064C)) /* Timer Preload 1 Reg 2 */ +#define WPREL22 (*(portw) (MBASE+0x064E)) /* Timer Preload 2 Reg 2 */ +#define TCOM2 (*(portw) (MBASE+0x0650)) /* Timer Compare Reg 2 */ diff --git a/bsps/m68k/gen68340/include/m68340.inc b/bsps/m68k/gen68340/include/m68340.inc new file mode 100644 index 0000000000..5c1ba36799 --- /dev/null +++ b/bsps/m68k/gen68340/include/m68340.inc @@ -0,0 +1,148 @@ +/*---------------------------------------------------------------------------- +* file name: M68340.INC JC RAHUEL CNET/DSM/TAM/CAT +* +* MC68340 BCC Board Support Package +* +* date: 1/12/1993 +* +* Copyright 1989, Ready Systems FRANCE +* +* Supports: VRTX32 and RTscope +* +* Related Board: MOTOROLA BCC M68340 +* +* Description: EQUATES FOR 68340 DEVICES +* +* Changes: +* - Geoffroy Montel (g_montel@yahoo.com) : +* changed EQU syntax for GNU as +* +*----------------------------------------------------------------------------*/ + +/************************************************ + * ATTENTION: must match defs. in C header file * + ************************************************/ + +/* -- SIM equates -- system integration module */ +.equ BASE_REG, 0x3FF00 +.equ BASE_SIM, 0xEFFFF000 +.equ SIM_MCR, 0x000 /* module configuration register */ +.equ SIM_SYNCR, 0x004 /* clock synthesizer control register */ +.equ SIM_AVR, 0x006 /* autovector register */ +.equ SIM_RSR, 0x007 /* reset status register */ + +/* -- Port A -- */ +.equ SIM_PORTA, 0x011 /* port A data */ +.equ SIM_DDRA, 0x013 /* port A direction data */ +.equ SIM_PPRA1, 0x015 /* Port A pin assignement 1 */ +.equ SIM_PPRA2, 0x017 /* Port A pin assignement 2 */ + +/* -- Port B -- */ +.equ SIM_PORTB, 0x019 /* port B data */ +.equ SIM_PORTB1, 0x01B /* port B data auxiliary */ +.equ SIM_DDRB, 0x01D /* port B direction data */ +.equ SIM_PPRB, 0x01F /* Port B pin assignement */ +.equ SIM_SWIV, 0x020 /* SW interrupt vector */ +.equ SIM_SYPCR, 0x021 /* System protection control register */ +.equ SIM_PICR, 0x022 /* Periodic interrupt control register */ +.equ SIM_PITR, 0x024 /* Periodic interrupt timing register */ +.equ SIM_SWSR, 0x027 /* Sofware service */ + +/* -- Chip select -- */ +.equ SIM_MASKH0, 0x040 /* mask register CS0 */ +.equ SIM_MASKL0, 0x042 /* mask register CS0 */ +.equ SIM_ADDRH0, 0x044 /* base address CS0 */ +.equ SIM_ADDRL0, 0x046 /* base address CS0 */ +.equ SIM_MASKH1, 0x048 /* mask register CS1 */ +.equ SIM_MASKL1, 0x04A /* mask register CS1 */ +.equ SIM_ADDRH1, 0x04C /* base address CS1 */ +.equ SIM_ADDRL1, 0x04E /* base address CS1 */ +.equ SIM_MASKH2, 0x050 /* mask register CS2 */ +.equ SIM_MASKL2, 0x052 /* mask register CS2 */ +.equ SIM_ADDRH2, 0x054 /* base address CS2 */ +.equ SIM_ADDRL2, 0x056 /* base address CS2 */ +.equ SIM_MASKH3, 0x058 /* mask register CS3 */ +.equ SIM_MASKL3, 0x05A /* mask register CS3 */ +.equ SIM_ADDRH3, 0x05C /* base address CS3 */ +.equ SIM_ADDRL3, 0x05E /* base address CS3 */ + +/* -- TIMERS equates -- */ + +/* __ TIMER 0 */ +.equ TIM_MCR0, 0x600 /* Module configuration register */ +.equ TIM_IR0, 0x604 /* interrupt register */ +.equ TIM_CR0, 0x606 /* controle register */ +.equ TIM_SR0, 0x608 /* Status/prescaler register */ +.equ TIM_CNTR0, 0x60A /* counter register */ +.equ TIM_PREL10, 0x60C /* Preload register 1 */ +.equ TIM_PREL20, 0x60E /* Preload register 2 */ +.equ TIM_COM0, 0x610 /* Compare register */ + +/* __ TIMER 1 */ + +.equ TIM_MCR1, 0x640 /* Module configuration register */ +.equ TIM_IR1, 0x644 /* interrupt register */ +.equ TIM_CR1, 0x646 /* controle register */ +.equ TIM_SR1, 0x648 /* Status/prescaler register */ +.equ TIM_CNTR1, 0x64A /* counter register */ +.equ TIM_PREL11, 0x64C /* Preload register 1 */ +.equ TIM_PREL21, 0x64E /* Preload register 2 */ +.equ TIM_COM1, 0x650 /* Compare register */ + +/* -- U.A.R.T. equates -- */ + +.equ UA_MCRH, 0x700 /* module configuration register */ +.equ UA_MCRL, 0x701 /* module configuration register */ +.equ UA_ILR, 0x704 /* Interrupt level */ +.equ UA_IVR, 0x705 /* Interrupt vector */ +.equ UA_MR1A, 0x710 /* Mode register 1 A */ +.equ UA_MR2A, 0x720 /* Mode register 2 A*/ +.equ UA_CSRA, 0x711 /* Clock_select register A */ +.equ UA_SRA, 0x711 /* status register A */ +.equ UA_CRA, 0x712 /* command register A */ +.equ UA_RBA, 0x713 /* receive buffer A */ +.equ UA_TBA, 0x713 /* transmit buffer A */ +.equ UA_IPCR, 0x714 /* input port change register */ +.equ UA_ACR, 0x714 /* auxiliary control register */ +.equ UA_ISR, 0x715 /* interrupt status register */ +.equ UA_IER, 0x715 /* interrupt enable register */ +.equ UA_MR1B, 0x718 /* Mode register 1 B */ +.equ UA_MR2B, 0x721 /* Mode register 2 B */ +.equ UA_CSRB, 0x719 /* Clock_select register B */ +.equ UA_SRB, 0x719 /* status register B */ +.equ UA_CRB, 0x71A /* command register A */ +.equ UA_RBB, 0x71B /* receive buffer A */ +.equ UA_TBB, 0x71B /* transmit buffer A */ +.equ UA_IP, 0x71D /* Input port register */ +.equ UA_OPCR, 0x71D /* output port control register */ +.equ UA_OPS, 0x71E /* output port bit set */ +.equ UA_OPR, 0x71F /* output port bit reset */ +.equ TX_A_EN, 0x01 /* Tx A irq enable */ +.equ TX_B_EN, 0x10 /* Tx B irq enable */ +.equ TX_A_DIS, 0xFE /* Tx A irq enable */ +.equ TX_B_DIS, 0xEF /* Tx B irq enable */ +.equ TX_AB_DIS, 0x22 + +/* -- DMA equates -- */ +.equ DMA_MCR0, 0x780 /* module configuration register */ +.equ DMA_IR0, 0x784 /* Interrupt register */ +.equ DMA_CCR0, 0x788 /* Channel control register */ +.equ DMA_CSR0, 0x78A /* Channel status register */ +.equ DMA_FCR0, 0x78B /* Function code register */ +.equ DMA_SARH0, 0x78C /* Source adresse register */ +.equ DMA_SARL0, 0x78E /* Source adresse register */ +.equ DMA_DARH0, 0x790 /* destination adresse register */ +.equ DMA_DARL0, 0x792 /* destination adresse register */ +.equ DMA_BTCH0, 0x794 /* byte transfer register */ +.equ DMA_BTCL0, 0x796 /* byte transfer register */ +.equ DMA_MCR1, 0x7A0 /* module configuration register */ +.equ DMA_IR1, 0x7A4 /* Interrupt register */ +.equ DMA_CCR1, 0x7A8 /* Channel control register */ +.equ DMA_CSR1, 0x7AA /* Channel status register */ +.equ DMA_FCR1, 0x7AB /* Function code register */ +.equ DMA_SARH1, 0x7AC /* Source adresse register */ +.equ DMA_SARL1, 0x7AE /* Source adresse register */ +.equ DMA_DARH1, 0x7B0 /* destination adresse register */ +.equ DMA_DARL1, 0x7B2 /* destination adresse register */ +.equ DMA_BTCH1, 0x7B4 /* byte transfer register */ +.equ DMA_BTCL1, 0x7B6 /* byte transfer register */ diff --git a/bsps/m68k/gen68340/include/m68349.inc b/bsps/m68k/gen68340/include/m68349.inc new file mode 100644 index 0000000000..4e3ce53d29 --- /dev/null +++ b/bsps/m68k/gen68340/include/m68349.inc @@ -0,0 +1,410 @@ +/*---------------------------------------------------------------------------- + * file name: M68349.INC P. CADIC CNET/DSM/TAM/CAT + * + * MC68349 BCC Board Support Package + * + * date: 31/07/97 + * + * Description: EQUATES FOR 68349 DEVICES + * + * Modifications: + * - adapted for GNU CC by G.Montel 26/05/98 + *----------------------------------------------------------------------------*/ + +| -- SIM equates -- + +.equ BASE_REG, 0x3FF00 +.equ BASE_SIM, 0xEFFFF000 | pour correction du bug 68349 sur IACK + +.equ SIM_MCR, 0x000 | module configuration register +.equ SIM_IDR, 0x002 | processor identification register +.equ SIM_SYNCR, 0x004 | clock synthesizer control register +.equ SIM_AVR, 0x006 | autovector register +.equ SIM_RSR, 0x007 | reset status register + +| -- Port A +.equ SIM_PORTA, 0x011 | port A data +.equ SIM_DDRA, 0x013 | port A direction data +.equ SIM_PPRA1, 0x015 | Port A pin assignement 1 +.equ SIM_PPRA2, 0x017 | Port A pin assignement 2 + +| -- Port B +.equ SIM_PORTB, 0x019 | port B data +.equ SIM_PORTB1, 0x01B | port B data auxiliary +.equ SIM_DDRB, 0x01D | port B direction data +.equ SIM_PPRB, 0x01F | Port B pin assignement + +.equ SIM_SWIV, 0x020 | SW interrupt vector +.equ SIM_SYPCR, 0x021 | System protection control register +.equ SIM_PICR, 0x022 | Periodic interrupt control register +.equ SIM_PITR, 0x024 | Periodic interrupt timing register +.equ SIM_SWSR, 0x027 | Sofware service + +| -- Chip select +.equ SIM_MASKH0, 0x040 | mask register CS0 +.equ SIM_MASKL0, 0x042 | mask register CS0 +.equ SIM_ADDRH0, 0x044 | base address CS0 +.equ SIM_ADDRL0, 0x046 | base address CS0 + +.equ SIM_MASKH1, 0x048 | mask register CS1 +.equ SIM_MASKL1, 0x04A | mask register CS1 +.equ SIM_ADDRH1, 0x04C | base address CS1 +.equ SIM_ADDRL1, 0x04E | base address CS1 + +.equ SIM_MASKH2, 0x050 | mask register CS2 +.equ SIM_MASKL2, 0x052 | mask register CS2 +.equ SIM_ADDRH2, 0x054 | base address CS2 +.equ SIM_ADDRL2, 0x056 | base address CS2 + +.equ SIM_MASKH3, 0x058 | mask register CS3 +.equ SIM_MASKL3, 0x05A | mask register CS3 +.equ SIM_ADDRH3, 0x05C | base address CS3 +.equ SIM_ADDRL3, 0x05E | base address CS3 + +| -- TIMERS equates -- + +| __ TIMER 0 + +.equ TIM_MCR0, 0x600 | Module configuration register +.equ TIM_IR0, 0x604 | interrupt register +.equ TIM_CR0, 0x606 | controle register +.equ TIM_SR0, 0x608 | Status/prescaler register +.equ TIM_CNTR0, 0x60A | counter register +.equ TIM_PREL10, 0x60C | Preload register 1 +.equ TIM_PREL20, 0x60E | Preload register 2 +.equ TIM_COM0, 0x610 | Compare register + +| __ TIMER 1 + +.equ TIM_MCR1, 0x640 | Module configuration register +.equ TIM_IR1, 0x644 | interrupt register +.equ TIM_CR1, 0x646 | controle register +.equ TIM_SR1, 0x648 | Status/prescaler register +.equ TIM_CNTR1, 0x64A | counter register +.equ TIM_PREL11, 0x64C | Preload register 1 +.equ TIM_PREL21, 0x64E | Preload register 2 +.equ TIM_COM1, 0x650 | Compare register + +| -- U.A.R.T. equates -- + +.equ UA_MCRH, 0x700 | module configuration register +.equ UA_MCRL, 0x701 | module configuration register +.equ UA_ILR, 0x704 | Interrupt level +.equ UA_IVR, 0x705 | Interrupt vector + +.equ UA_MR1A, 0x710 | Mode register 1 A +.equ UA_MR2A, 0x720 | Mode register 2 A +.equ UA_CSRA, 0x711 | Clock_select regiter A +.equ UA_SRA, 0x711 | status register A +.equ UA_CRA, 0x712 | command register A +.equ UA_RBA, 0x713 | receive buffer A +.equ UA_TBA, 0x713 | transmit buffer A + +.equ UA_IPCR, 0x714 | input port change register +.equ UA_ACR, 0x714 | auxiliary control register +.equ UA_ISR, 0x715 | interrupt status register +.equ UA_IER, 0x715 | interrupt enable register + +.equ UA_MR1B, 0x718 | Mode register 1 B +.equ UA_MR2B, 0x721 | Mode register 2 B +.equ UA_CSRB, 0x719 | Clock_select regiter B +.equ UA_SRB, 0x719 | status register B +.equ UA_CRB, 0x71A | command register A +.equ UA_RBB, 0x71B | receive buffer A +.equ UA_TBB, 0x71B | transmit buffer A + +.equ UA_IP, 0x71D | Input port register +.equ UA_OPCR, 0x71D | output port control register +.equ UA_OPS, 0x71E | output port bit set +.equ UA_OPR, 0x71F | output port bit reset +.equ TX_A_EN, 0x01 | Tx A irq enable +.equ TX_B_EN, 0x10 | Tx B irq enable +.equ TX_A_DIS, 0xFE | Tx A irq enable +.equ TX_B_DIS, 0xEF | Tx B irq enable +.equ TX_AB_DIS, 0x22 + + +| -- DMA equates +.equ DMA_MCR0, 0x780 | module configuration register +.equ DMA_IR0, 0x784 | Interrupt register +.equ DMA_CCR0, 0x788 | Channel control register +.equ DMA_CSR0, 0x78A | Channel status register +.equ DMA_FCR0, 0x78B | Function code register +.equ DMA_SARH0, 0x78C | Source adresse register +.equ DMA_SARL0, 0x78E | Source adresse register +.equ DMA_DARH0, 0x790 | destination adresse register +.equ DMA_DARL0, 0x792 | destination adresse register +.equ DMA_BTCH0, 0x794 | byte transfer register +.equ DMA_BTCL0, 0x796 | byte transfer register + +.equ DMA_MCR1, 0x7A0 | module configuration register +.equ DMA_IR1, 0x7A4 | Interrupt register +.equ DMA_CCR1, 0x7A8 | Channel control register +.equ DMA_CSR1, 0x7AA | Channel status register +.equ DMA_FCR1, 0x7AB | Function code register +.equ DMA_SARH1, 0x7AC | Source adresse register +.equ DMA_SARL1, 0x7AE | Source adresse register +.equ DMA_DARH1, 0x7B0 | destination adresse register +.equ DMA_DARL1, 0x7B2 | destination adresse register +.equ DMA_BTCH1, 0x7B4 | byte transfer register +.equ DMA_BTCL1, 0x7B6 | byte transfer register + +| -- cache equates +.equ CACHE_MCR, 0xFC0 | cache config reg. (long) + +| -- quad data memory module (QDMM) equates +.equ QDMM_MCR, 0xC00 | QDMM config reg (long) +.equ QDMM_QBAR0, 0xC10 | QDMM base 0 (long) +.equ QDMM_QBAR1, 0xC14 | QDMM base 1 (long) +.equ QDMM_QBAR2, 0xC18 | QDMM base 2 (long) +.equ QDMM_QBAR3, 0xC1C | QDMM base 3 (long) + + + +|----------------------------------------------------- +| AST68349 internal registers +|----------------------------------------------------- +.equ EPLD_SPACE, 3 | "reserved user" space +.equ CPU_SPACE, 7 | "CPU" space + +|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| +| GLUE EPLD +|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| + +.equ GLUE_EPLD, 0xB0000000 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| configuration of /CS0 : +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |ena|val|wid| ws|b31|b30|b29|b28| +| +---+---+---+---+---+---+---+---+ +| +| b[31..28] : base address for decoding /CS[3..0] +| the decoding is as follow : +| +| +----------+------------+------+ +| | a[31..28] | a[27..26] | /CS | +| +-----------+-----------+------+ +| | b[31..28] | 00 | /CS0 | each /CS decodes 64 Mbytes +| | b[31..28] | 01 | /CS1 | +| | b[31..28] | 10 | /CS2 | +| | b[31..28] | 11 | /CS3 | +| +-----------------------+------+ +| +| after /RESET, /CS0 is validated for every cycle, until programmed +| +| ws : number of wait-states : 0 => 0 ws +| 1 => external /dsackx +| wid : width of chip-select : 0 => 16 bits +| 1 => 32 bits +| ena : enable chip-select : 0 => disabled +| 1 => enabled +| +| val : automatic validation. set after reset +| cleared when /CS0 is configured +| +.equ REG_CS0, 0 + + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| configuration of /CS1 to /CS3: +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |ena| x |wid| ws| x | x | x | x | +| +---+---+---+---+---+---+---+---+ +| +| ws : number of wait-states : 0 => 0 ws +| 1 => external /dsackx +| wid : width of chip-select : 0 => 16 bits +| 1 => 32 bits +| ena : enable chip-select : 0 => disabled +| 1 => enabled +.equ REG_CS1, 1 +.equ REG_CS2, 2 +.equ REG_CS3, 3 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| I2C register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+----+ +| | x | x | x | x | x | x |clk|data| +| +---+---+---+---+---+---+---+----+ +| bidirecionnal pin, open drain output. +| set bit to 1 to read external state of pin +| +.equ REG_I2C, 4 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| PDCS register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |s12|s11|s14|pd5|pd4|pd3|pd2|pd1| +| +---+---+---+---+---+---+---+---+ +| pd[5..1] : value read on the DRAM module +| S12, S11 and S14 : "user reserved" configuration switch +| +.equ REG_PDCS, 5 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| timer1 register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |ena| x | x | x | x | x | d1| d0| +| +---+---+---+---+---+---+---+---+ +| +| the timer clock is the 1000Hz clock of the ASTECC platform +| the timer is reloaded on each write to the register, or if the input +| TIN1 is set to 0. +| on overflow, the open drain output TOUT1 is set to 0 +| the timer must be disabled to return TOUT1 to the inactive state +| +.equ REG_TIMER1, 6 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| timer2 register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |ena| x | x | x | x | x | d1| d0| +| +---+---+---+---+---+---+---+---+ +| the timer clock is the 1000Hz clock of the ASTECC platform +| the timer is reloaded on each write to the register, or if the input +| TIN2 is set to 0. +| on overflow, the open drain output TOUT2 is set to 0 +| the timer must be disabled to return TOUT2 to the inactive state +| +.equ REG_TIMER2, 7 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| baudrate generator register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| | x | x | x | x | x | d2| d1| d0| +| +---+---+---+---+---+---+---+---+ +| +| d[2..0] : divider of a 3.6864 Mhz clock +| +| d[2..0] : 0 1 2 3 4 5 6 7 +| divides by : 2 4 6 8 10 12 14 16 +| SCLK (Mhz) : 1.8432 0.9216 0.6144 0.4608 x 0.3072 x 0.2304 +| baudrate : 115200 57600 38400 28800 x 19200 x 14400 +| +.equ REG_BAUDRATE, 8 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| IO register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| | x | x | x |io4|io3|io2|io1|io0| +| +---+---+---+---+---+---+---+---+ +| +| io[4..0] : data written to port +| +| maximum current load is about 5 mA per pin +| +.equ REG_IO, 9 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| IO port +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| | x | x | x |io4|io3|io2|io1|io0| +| +---+---+---+---+---+---+---+---+ +| +| io[4..0] : data read from port +| +.equ REG_IO_PORT, 10 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| IO direction register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| | x | x | x | x | x |dr2|dr1|dr0| +| +---+---+---+---+---+---+---+---+ +| +| dr0 : 0 => io port 0 is configured as input (default after /RESET) +| 1 => io port 0 is configured as output +| +| dr1 : 0 => io port 1 is configured as input (default after /RESET) +| 1 => io port 1 is configured as output +| +| dr2 : 0 => io ports 2 to 4 are configured as input (default after /RESET) +| 1 => io ports 2 to 4 are configured as output +| +.equ REG_DIR_IO, 11 + + + + +|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| +| DRAM EPLD +|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| + +.equ DRAM_EPLD, 0xA0000000 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| number of wait-state for DRAM +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| | x | x | x | x | x | x |ws1|ws0| +| +---+---+---+---+---+---+---+---+ +| +| ws[1..0] : 0 1 2 3 +| wait states : 0 1 2 3 +| +.equ REG_WS, 0 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| configuration of refresh for DRAM +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |ena| x | x | x | x | x |rf1|rf0| +| +---+---+---+---+---+---+---+---+ +| +| rf[1..0] : 0 1 2 3 +| refresh : 5µs 10µs 15µs 20µs +| +| ena == 0 : refresh disabled +| ena == 1 : refresh enabled +| +.equ REG_REFRESH, 1 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| configuration of DRAM module size +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| | x | x | x | x | x |sz2|sz1|sz0| +| +---+---+---+---+---+---+---+---+ +| +| sz[2..0] : 0 1 2 3 4 5 6 7 +| size (Mbytes): 4 8 16 32 64 128 0 0 +| +.equ REG_CONFIG, 2 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| bus width of /CS0 during reset bw[1..0] : 0 1 2 3 +| bus width : 32 16 8 ext. /dsackx +| +| state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) +| : sel == 1 => EPLD chip_selects (/CS[3..0]) +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |bw1|bw0| x | x | x | x | x |sel| +| +---+---+---+---+---+---+---+---+ +| +.equ REG_BUSWIDTH, 3 + diff --git a/bsps/m68k/gen68340/include/tm27.h b/bsps/m68k/gen68340/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/m68k/gen68340/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/m68k/gen68360/headers.am b/bsps/m68k/gen68360/headers.am new file mode 100644 index 0000000000..be0ec17252 --- /dev/null +++ b/bsps/m68k/gen68360/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/gen68360/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/gen68360/include/tm27.h diff --git a/bsps/m68k/gen68360/include/bsp.h b/bsps/m68k/gen68360/include/bsp.h new file mode 100644 index 0000000000..0c6a94066c --- /dev/null +++ b/bsps/m68k/gen68360/include/bsp.h @@ -0,0 +1,111 @@ +/** + * @file + * + * @ingroup gen68360_bsp + * + * @brief Board Support Package for `Generic' Motorola MC68360 + */ + +/* + * + * Based on the `gen68302' board support package, and covered by the + * original distribution terms. + * + * W. Eric Norum + * Saskatchewan Accelerator Laboratory + * University of Saskatchewan + * Saskatoon, Saskatchewan, CANADA + * eric@skatter.usask.ca + */ + +/* bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_GEN68360_BSP_H +#define LIBBSP_M68K_GEN68360_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup gen68360_bsp Network driver + * + * @ingroup m68k_gen68360 + * + * @brief Network driver configuration + */ + +struct rtems_bsdnet_ifconfig; +extern int rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "scc1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_scc1_driver_attach + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +/* functions */ + +void M360ExecuteRISC( uint16_t command ); +void *M360AllocateBufferDescriptors( int count ); +void *M360AllocateRiscTimers( int count ); +extern char M360DefaultWatchdogFeeder; + +extern int m360_clock_rate; /* BRG clock rate, defined in console.c */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Definitions for Atlas Computer Equipment Inc. High Speed Bridge (HSB) + */ +#define ATLASHSB_ESR 0x20010000L +#define ATLASHSB_USICR 0x20010001L +#define ATLASHSB_DSRR 0x20010002L +#define ATLASHSB_LED4 0x20010004L +#define ATLASHSB_ROM_U6 0xFF080000L /* U6 flash ROM socket */ + + +/* + * definitions for PGH360 board + */ +#if defined(PGH360) +/* + * logical SPI addresses of SPI slaves available + */ +#define PGH360_SPI_ADDR_EEPROM 0 +#define PGH360_SPI_ADDR_DISP4_DATA 1 +#define PGH360_SPI_ADDR_DISP4_CTRL 2 + +/* + * Port B bit locations of SPI slave selects + */ +#define PGH360_PB_SPI_DISP4_RS_MSK (1<<15) +#define PGH360_PB_SPI_DISP4_CE_MSK (1<<14) +#define PGH360_PB_SPI_EEP_CE_MSK (1<< 0) +#endif /* defined(PGH360) */ + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void _Init68360(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/gen68360/include/tm27.h b/bsps/m68k/gen68360/include/tm27.h new file mode 100644 index 0000000000..c71eed3897 --- /dev/null +++ b/bsps/m68k/gen68360/include/tm27.h @@ -0,0 +1,40 @@ +/** + * @file + * + * @ingroup m68k_tm27 + * + * @brief Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/** + * @defgroup m68k_tm27 Stuff for Time Test 27 + * + * @ingroup m68k_gen68360 + * + * @brief Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 34, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #2"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/genmcf548x/headers.am b/bsps/m68k/genmcf548x/headers.am new file mode 100644 index 0000000000..80752c512e --- /dev/null +++ b/bsps/m68k/genmcf548x/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/genmcf548x/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/genmcf548x/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/m68k/genmcf548x/include/bsp/irq.h diff --git a/bsps/m68k/genmcf548x/include/bsp.h b/bsps/m68k/genmcf548x/include/bsp.h new file mode 100644 index 0000000000..77a7bca0e8 --- /dev/null +++ b/bsps/m68k/genmcf548x/include/bsp.h @@ -0,0 +1,134 @@ +/** + * @file + * + * @ingroup m68k_genmcf548x + * + * @brief Global BSP definitions. + */ + +/*===============================================================*\ +| Project: RTEMS generic mcf548x BSP | ++-----------------------------------------------------------------+ +| File: bsp.h | ++-----------------------------------------------------------------+ +| The file contains the BSP header of generic MCF548x BSP. | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| | +| Parts of the code has been derived from the "dBUG source code" | +| package Freescale is providing for M548X EVBs. The usage of | +| the modified or unmodified code and it's integration into the | +| generic mcf548x BSP has been done according to the Freescale | +| license terms. | +| | +| The Freescale license terms can be reviewed in the file | +| | +| Freescale_license.txt | +| | ++-----------------------------------------------------------------+ +| | +| The generic mcf548x BSP has been developed on the basic | +| structures and modules of the av5282 BSP. | +| | ++-----------------------------------------------------------------+ +| | +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| | +| date history ID | +| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | +| 12.11.07 1.0 ras | +| | +\*===============================================================*/ + +#ifndef LIBBSP_M68K_GENMCF548X_BSP_H +#define LIBBSP_M68K_GENMCF548X_BSP_H + +#include +#include + +/** + * @defgroup m68k_genmcf548x MCF548X Support + * + * @ingroup bsp_m68k + * + * @brief MCT548X support. + */ + +#include +#include + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* functions */ + +uint32_t get_CPU_clock_speed(void); + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* Initial values for the interrupt level and priority registers (INTC_ICRn) */ +extern const uint8_t mcf548x_intc_icr_init_values[64]; + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_mcf548x_fec_driver_attach_detach(struct rtems_bsdnet_ifconfig *config,int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mcf548x_fec_driver_attach_detach + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "fec1" +#define RTEMS_BSP_NETWORK_DRIVER_NAME2 "fec2" + +#ifdef HAS_DBUG + typedef struct { + uint32_t console_baudrate; + uint8_t server_ip [4]; + uint8_t client_ip [4]; + uint8_t gateway_ip[4]; + uint8_t netmask [4]; + uint8_t spare[4]; + uint8_t macaddr [6]; + uint32_t ethport; /* default fec port: 1 = fec1, 2 = fec2 */ + uint32_t uartport; /* default fec port: 1 = psc0, 2 = psc1... */ + } dbug_settings_t; + +#define DBUG_SETTINGS (*(const dbug_settings_t *)0xFC020000) +#endif /* HAS_DBUG */ + +void bsp_cacr_set_flags(uint32_t flags); + +void bsp_cacr_set_self_clear_flags(uint32_t flags); + +void bsp_cacr_clear_flags(uint32_t flags); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/genmcf548x/include/bsp/irq.h b/bsps/m68k/genmcf548x/include/bsp/irq.h new file mode 100644 index 0000000000..825cc0d104 --- /dev/null +++ b/bsps/m68k/genmcf548x/include/bsp/irq.h @@ -0,0 +1,96 @@ +/** + * @file + * + * @ingroup genmcf548x_interrupt + * + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_MCF548X_IRQ_H +#define LIBBSP_M68K_MCF548X_IRQ_H + +#include +#include +#include + +/** + * @defgroup genmcf548x_interrupt Interrupt Support + * + * @ingroup m68k_genmcf548x + * + * @brief Interrupt support. + */ + + +#define MCF548X_IRQ_EPORT_EPF1 1 +#define MCF548X_IRQ_EPORT_EPF2 2 +#define MCF548X_IRQ_EPORT_EPF3 3 +#define MCF548X_IRQ_EPORT_EPF4 4 +#define MCF548X_IRQ_EPORT_EPF5 5 +#define MCF548X_IRQ_EPORT_EPF6 6 +#define MCF548X_IRQ_EPORT_EPF7 7 +#define MCF548X_IRQ_USB_EP0ISR 15 +#define MCF548X_IRQ_USB_EP1ISR 16 +#define MCF548X_IRQ_USB_EP2ISR 17 +#define MCF548X_IRQ_USB_EP3ISR 18 +#define MCF548X_IRQ_USB_EP4ISR 19 +#define MCF548X_IRQ_USB_EP5ISR 20 +#define MCF548X_IRQ_USB_EP6ISR 21 +#define MCF548X_IRQ_USB_ISR 22 +#define MCF548X_IRQ_USB_AISR 23 +#define MCF548X_IRQ_DSPI_RFOF_TFUF 25 +#define MCF548X_IRQ_DSPI_RFOF 26 +#define MCF548X_IRQ_DSPI_RFDF 27 +#define MCF548X_IRQ_DSPI_TFUF 28 +#define MCF548X_IRQ_DSPI_TCF 29 +#define MCF548X_IRQ_DSPI_TFFF 30 +#define MCF548X_IRQ_DSPI_EOQF 31 +#define MCF548X_IRQ_DSPI 25 +#define MCF548X_IRQ_PSC3 32 +#define MCF548X_IRQ_PSC2 33 +#define MCF548X_IRQ_PSC1 34 +#define MCF548X_IRQ_PSC0 35 +#define MCF548X_IRQ_PSC(i) (35 - (i)) +#define MCF548X_IRQ_COMMTIM 36 +#define MCF548X_IRQ_SEC 37 +#define MCF548X_IRQ_FEC1 38 +#define MCF548X_IRQ_FEC0 39 +#define MCF548X_IRQ_FEC(i) (39 - (i)) +#define MCF548X_IRQ_I2C 40 +#define MCF548X_IRQ_PCIARB 41 +#define MCF548X_IRQ_CBPCI 42 +#define MCF548X_IRQ_XLBPCI 43 +#define MCF548X_IRQ_XLBARB 47 +#define MCF548X_IRQ_DMA 48 +#define MCF548X_IRQ_CAN0_ERROR 49 +#define MCF548X_IRQ_CAN0_BUSOFF 50 +#define MCF548X_IRQ_CAN0_MBOR 51 +#define MCF548X_IRQ_SLT1 53 +#define MCF548X_IRQ_SLT0 54 +#define MCF548X_IRQ_CAN1_ERROR 55 +#define MCF548X_IRQ_CAN1_BUSOFF 56 +#define MCF548X_IRQ_CAN1_MBOR 57 +#define MCF548X_IRQ_GPT3 59 +#define MCF548X_IRQ_GPT2 60 +#define MCF548X_IRQ_GPT1 61 +#define MCF548X_IRQ_GPT0 62 + +#define BSP_INTERRUPT_VECTOR_MIN 1 + +#define BSP_INTERRUPT_VECTOR_MAX 63 + +#endif /* LIBBSP_M68K_MCF548X_IRQ_H */ diff --git a/bsps/m68k/genmcf548x/include/tm27.h b/bsps/m68k/genmcf548x/include/tm27.h new file mode 100644 index 0000000000..31ea8bca0c --- /dev/null +++ b/bsps/m68k/genmcf548x/include/tm27.h @@ -0,0 +1,37 @@ +/** + * @file + * + * @ingroup m68k_genmcf548x + * + * @brief Time Test 27 routines. + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/headers.am b/bsps/m68k/headers.am new file mode 100644 index 0000000000..526fa7769f --- /dev/null +++ b/bsps/m68k/headers.am @@ -0,0 +1,47 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../bsps/m68k/include/mvme16x_hw.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/m68k/include/bsp/linker-symbols.h + +include_mcf5206dir = $(includedir)/mcf5206 +include_mcf5206_HEADERS = +include_mcf5206_HEADERS += ../../../../../bsps/m68k/include/mcf5206/mcf5206e.h +include_mcf5206_HEADERS += ../../../../../bsps/m68k/include/mcf5206/mcfmbus.h +include_mcf5206_HEADERS += ../../../../../bsps/m68k/include/mcf5206/mcfuart.h + +include_mcf5223xdir = $(includedir)/mcf5223x +include_mcf5223x_HEADERS = +include_mcf5223x_HEADERS += ../../../../../bsps/m68k/include/mcf5223x/mcf5223x.h + +include_mcf5225xdir = $(includedir)/mcf5225x +include_mcf5225x_HEADERS = +include_mcf5225x_HEADERS += ../../../../../bsps/m68k/include/mcf5225x/fec.h +include_mcf5225x_HEADERS += ../../../../../bsps/m68k/include/mcf5225x/mcf5225x.h + +include_mcf5235dir = $(includedir)/mcf5235 +include_mcf5235_HEADERS = +include_mcf5235_HEADERS += ../../../../../bsps/m68k/include/mcf5235/mcf5235.h + +include_mcf5272dir = $(includedir)/mcf5272 +include_mcf5272_HEADERS = +include_mcf5272_HEADERS += ../../../../../bsps/m68k/include/mcf5272/mcf5272.h + +include_mcf5282dir = $(includedir)/mcf5282 +include_mcf5282_HEADERS = +include_mcf5282_HEADERS += ../../../../../bsps/m68k/include/mcf5282/mcf5282.h + +include_mcf532xdir = $(includedir)/mcf532x +include_mcf532x_HEADERS = +include_mcf532x_HEADERS += ../../../../../bsps/m68k/include/mcf532x/mcf532x.h + +include_mcf548xdir = $(includedir)/mcf548x +include_mcf548x_HEADERS = +include_mcf548x_HEADERS += ../../../../../bsps/m68k/include/mcf548x/MCD_dma.h +include_mcf548x_HEADERS += ../../../../../bsps/m68k/include/mcf548x/MCD_progCheck.h +include_mcf548x_HEADERS += ../../../../../bsps/m68k/include/mcf548x/MCD_tasksInit.h +include_mcf548x_HEADERS += ../../../../../bsps/m68k/include/mcf548x/mcdma_glue.h +include_mcf548x_HEADERS += ../../../../../bsps/m68k/include/mcf548x/mcf548x.h diff --git a/bsps/m68k/include/bsp/linker-symbols.h b/bsps/m68k/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..8bf5ebfa07 --- /dev/null +++ b/bsps/m68k/include/bsp/linker-symbols.h @@ -0,0 +1,84 @@ +/** + * @file + * + * @ingroup bsp_linker + * + * @brief Symbols defined in linker command base file. + */ + +/* + * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_M68K_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup bsp_linker Linker Support + * + * @ingroup bsp_kit + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM + #define LINKER_SYMBOL(sym) extern char sym []; +#else + #define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_vector0_begin) +LINKER_SYMBOL(bsp_vector0_end) +LINKER_SYMBOL(bsp_vector0_size) + +LINKER_SYMBOL(bsp_vector1_begin) +LINKER_SYMBOL(bsp_vector1_end) +LINKER_SYMBOL(bsp_vector1_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_initstack_begin) +LINKER_SYMBOL(bsp_initstack_end) +LINKER_SYMBOL(bsp_initstack_size) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_M68K_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/m68k/include/mcf5206/mcf5206e.h b/bsps/m68k/include/mcf5206/mcf5206e.h new file mode 100644 index 0000000000..06dadca9b1 --- /dev/null +++ b/bsps/m68k/include/mcf5206/mcf5206e.h @@ -0,0 +1,609 @@ +/* + * Coldfire MCF5206e on-chip peripherial definitions. + * Contents of this file based on information provided in + * Motorola MCF5206e User's Manual + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __MCF5206E_H__ +#define __MCF5206E_H__ + +#ifdef ASM +#define MCF5206E_REG8(base,ofs) (ofs+base) +#define MCF5206E_REG16(base,ofs) (ofs+base) +#define MCF5206E_REG32(base,ofs) (ofs+base) +#else +#define MCF5206E_REG8(base,ofs) \ + (volatile uint8_t*)((uint8_t*)(base) + (ofs)) +#define MCF5206E_REG16(base,ofs) \ + (volatile uint16_t*)((uint8_t*)(base) + (ofs)) +#define MCF5206E_REG32(base,ofs) \ + (volatile uint32_t*)((uint8_t*)(base) + (ofs)) +#endif + +/*** Instruction Cache -- MCF5206e User's Manual, Chapter 4 ***/ + +/* CACR - Cache Control Register */ +#define MCF5206E_CACR_CENB (0x80000000) /* Cache Enable */ +#define MCF5206E_CACR_CPDI (0x10000000) /* Disable CPUSHL Invalidation */ +#define MCF5206E_CACR_CFRZ (0x08000000) /* Cache Freeze */ +#define MCF5206E_CACR_CINV (0x01000000) /* Cache Invalidate */ +#define MCF5206E_CACR_CEIB (0x00000400) /* Cache Enable Noncacheable + instruction bursting */ +#define MCF5206E_CACR_DCM (0x00000200) /* Default cache mode - noncacheable*/ +#define MCF5206E_CACR_DBWE (0x00000100) /* Default Buffered Write Enable */ +#define MCF5206E_CACR_DWP (0x00000020) /* Default Write Protection */ +#define MCF5206E_CACR_CLNF (0x00000003) /* Cache Line Fill */ + +/* ACR0, ACR1 - Access Control Registers */ +#define MCF5206E_ACR_AB (0xff000000) /* Address Base */ +#define MCF5206E_ACR_AB_S (24) +#define MCF5206E_ACR_AM (0x00ff0000) /* Address Mask */ +#define MCF5206E_ACR_AM_S (16) +#define MCF5206E_ACR_EN (0x00008000) /* Enable ACR */ +#define MCF5206E_ACR_SM (0x00006000) /* Supervisor Mode */ +#define MCF5206E_ACR_SM_USR (0x00000000) /* Match if user mode */ +#define MCF5206E_ACR_SM_SVR (0x00002000) /* Match if supervisor mode */ +#define MCF5206E_ACR_SM_ANY (0x00004000) /* Match Always */ +#define MCF5206E_ACR_CM (0x00000040) /* Cache Mode (1 - noncacheable) */ +#define MCF5206E_ACR_BUFW (0x00000020) /* Buffered Write Enable */ +#define MCF5206E_ACR_WP (0x00000004) /* Write Protect */ +#define MCF5206E_ACR_BASE(base) ((base) & MCF5206E_ACR_AB) +#define MCF5206E_ACR_MASK(mask) (((mask) >> 8) & MCF5206E_ACR_AM) + +/*** SRAM -- MCF5206e User's Manual, Chapter 5 ***/ + +/* RAMBAR - SRAM Base Address Register */ +#define MCF5206E_RAMBAR_BA (0xffffe000) /* SRAM Base Address */ +#define MCF5206E_RAMBAR_WP (0x00000100) /* Write Protect */ +#define MCF5206E_RAMBAR_CI (0x00000020) /* CPU Space mask */ +#define MCF5206E_RAMBAR_SC (0x00000010) /* Supervisor Code Space Mask */ +#define MCF5206E_RAMBAR_SD (0x00000008) /* Supervisor Data Space Mask */ +#define MCF5206E_RAMBAR_UC (0x00000004) /* User Code Space Mask */ +#define MCF5206E_RAMBAR_UD (0x00000002) /* User Data Space Mask */ +#define MCF5206E_RAMBAR_V (0x00000001) /* Contents of RAMBAR are valid */ + +/*** DMA Controller Module -- MCF5206e User's Manual, Chapter 7 ***/ + +/* DMA Source Address Register */ +#define MCF5206E_SAR(mbar,chn) MCF5206E_REG32(mbar,0x200 + ((chn) * 0x40)) + +/* DMA Destination Address Register */ +#define MCF5206E_DAR(mbar,chn) MCF5206E_REG32(mbar,0x204 + ((chn) * 0x40)) + +/* DMA Byte Count Register */ +#define MCF5206E_BCR(mbar,chn) MCF5206E_REG16(mbar,0x20C + ((chn) * 0x40)) + +/* DMA Control Register */ +#define MCF5206E_DCR(mbar,chn) MCF5206E_REG16(mbar,0x208 + ((chn) * 0x40)) +#define MCF5206E_DCR_INT (0x8000) /* Interrupt on completion of transfer */ +#define MCF5206E_DCR_EEXT (0x4000) /* Enable External DMA Request */ +#define MCF5206E_DCR_CS (0x2000) /* Cycle Steal */ +#define MCF5206E_DCR_AA (0x1000) /* Auto Align */ +#define MCF5206E_DCR_BWC (0x0E00) /* Bandwidth Control: */ +#define MCF5206E_DCR_BWC_DISABLE (0x0000) /* Bandwidth Control Disabled */ +#define MCF5206E_DCR_BWC_512 (0x0200) /* 512 bytes */ +#define MCF5206E_DCR_BWC_1024 (0x0400) /* 1024 bytes */ +#define MCF5206E_DCR_BWC_2048 (0x0600) /* 2048 bytes */ +#define MCF5206E_DCR_BWC_4096 (0x0800) /* 4096 bytes */ +#define MCF5206E_DCR_BWC_8192 (0x0A00) /* 8192 bytes */ +#define MCF5206E_DCR_BWC_16384 (0x0C00) /* 16384 bytes */ +#define MCF5206E_DCR_BWC_32768 (0x0E00) /* 32768 bytes */ +#define MCF5206E_DCR_SAA (0x0100) /* Single Address Access */ +#define MCF5206E_DCR_S_RW (0x0080) /* Single Address Access Read/Write Val */ +#define MCF5206E_DCR_SINC (0x0040) /* Source Increment */ +#define MCF5206E_DCR_SSIZE (0x0030) /* Source Size: */ +#define MCF5206E_DCR_SSIZE_LONG (0x0000) /* Longword (4 bytes) */ +#define MCF5206E_DCR_SSIZE_BYTE (0x0010) /* Byte */ +#define MCF5206E_DCR_SSIZE_WORD (0x0020) /* Word (2 bytes) */ +#define MCF5206E_DCR_SSIZE_LINE (0x0030) /* Line (16 bytes) */ +#define MCF5206E_DCR_DINC (0x0008) /* Destination Increment */ +#define MCF5206E_DCR_DSIZE (0x0006) /* Destination Size: */ +#define MCF5206E_DCR_DSIZE_LONG (0x0000) /* Longword (4 bytes) */ +#define MCF5206E_DCR_DSIZE_BYTE (0x0002) /* Byte */ +#define MCF5206E_DCR_DSIZE_WORD (0x0004) /* Word (2 bytes) */ +#define MCF5206E_DCR_DSIZE_LINE (0x0006) /* Line (16 bytes) */ +#define MCF5206E_DCR_START (0x0001) /* Start Transfer */ + +/* DMA Status Register */ +#define MCF5206E_DSR(mbar,chn) MCF5206E_REG8(mbar,0x210 + ((chn) * 0x40)) +#define MCF5206E_DSR_CE (0x40) /* Configuration Error has occured */ +#define MCF5206E_DSR_BES (0x20) /* Bus Error on Source */ +#define MCF5206E_DSR_BED (0x10) /* Bus Error on Destination */ +#define MCF5206E_DSR_REQ (0x04) /* Request */ +#define MCF5206E_DSR_BSY (0x02) /* Busy */ +#define MCF5206E_DSR_DONE (0x01) /* Transaction Done */ + +/* DMA Interrupt Vector Register */ +#define MCF5206E_DIVR(mbar,chn) MCF5206E_REG8(mbar,0x214 + ((chn) * 0x40)) + + +/*** System Integration Module -- MCF5206e User's Manual, Chapter 8 ***/ + +/* MBAR - Module Base Address Register */ +#define MCF5206E_MBAR_BA (0xFFFFFC00) /* Base Address */ +#define MCF5206E_MBAR_SC (0x00000010) /* Supervisor Code Space Mask */ +#define MCF5206E_MBAR_SD (0x00000008) /* Supervisor Data Space Mask */ +#define MCF5206E_MBAR_UC (0x00000004) /* User Code Space Mask */ +#define MCF5206E_MBAR_UD (0x00000002) /* User Data Space Mask */ +#define MCF5206E_MBAR_V (0x00000001) /* Contents of MBAR are valid */ + +/* SIM Configuration Register */ +#define MCF5206E_SIMR(mbar) MCF5206E_REG8(mbar,0x003) +#define MCF5206E_SIMR_FRZ1 (0x80) /* Disable Soft Wdog Timer when FREEZE */ +#define MCF5206E_SIMR_FRZ0 (0x40) /* Disable Bus Timeout monitor when FREEZE*/ +#define MCF5206E_SIMR_BL (0x01) /* Bus Lock Enable */ + +/* Interrupt numbers assignment */ +#define MCF5206E_INTR_EXT_IRQ1 (1) /* External IRQ1 */ +#define MCF5206E_INTR_EXT_IPL1 (1) /* External IPL1 */ +#define MCF5206E_INTR_EXT_IPL2 (2) /* External IPL2 */ +#define MCF5206E_INTR_EXT_IPL3 (3) /* External IPL3 */ +#define MCF5206E_INTR_EXT_IRQ4 (4) /* External IRQ4 */ +#define MCF5206E_INTR_EXT_IPL4 (4) /* External IPL4 */ +#define MCF5206E_INTR_EXT_IPL5 (5) /* External IPL5 */ +#define MCF5206E_INTR_EXT_IPL6 (6) /* External IPL6 */ +#define MCF5206E_INTR_EXT_IRQ7 (7) /* External IRQ7 */ +#define MCF5206E_INTR_EXT_IPL7 (7) /* External IPL7 */ +#define MCF5206E_INTR_SWT (8) /* Software Watchdog Timer */ +#define MCF5206E_INTR_TIMER_1 (9) /* Timer 1 interrupt */ +#define MCF5206E_INTR_TIMER_2 (10) /* Timer 2 interrupt */ +#define MCF5206E_INTR_MBUS (11) /* MBUS interrupt */ +#define MCF5206E_INTR_UART_1 (12) /* UART 1 interrupt */ +#define MCF5206E_INTR_UART_2 (13) /* UART 2 interrupt */ +#define MCF5206E_INTR_DMA_0 (14) /* DMA channel 0 interrupt */ +#define MCF5206E_INTR_DMA_1 (15) /* DMA channel 1 interrupt */ + +#define MCF5206E_INTR_BIT(n) (1 << (n)) + +/* Interrupt Control Registers (ICR1 - ICR15) */ +#define MCF5206E_ICR(mbar,n) MCF5206E_REG8(mbar,0x014 + (n) - 1) + +#define MCF5206E_ICR_AVEC (0x80) /* Autovector Enable */ +#define MCF5206E_ICR_IL (0x1c) /* Interrupt Level */ +#define MCF5206E_ICR_IL_S (2) +#define MCF5206E_ICR_IP (0x03) /* Interrupt Priority */ +#define MCF5206E_ICR_IP_S (0) + +/* Interrupt Mask Register */ +#define MCF5206E_IMR(mbar) MCF5206E_REG16(mbar,0x036) + +/* Interrupt Pending Register */ +#define MCF5206E_IPR(mbar) MCF5206E_REG16(mbar,0x03a) + +/* Reset Status Register */ +#define MCF5206E_RSR(mbar) MCF5206E_REG8(mbar,0x040) +#define MCF5206E_RSR_HRST (0x80) /* Hard Reset or System Reset */ +#define MCF5206E_RSR_SWTR (0x20) /* Software Watchdog Timer Reset */ + +/* System Protection Control Register */ +#define MCF5206E_SYPCR(mbar) MCF5206E_REG8(mbar,0x041) +#define MCF5206E_SYPCR_SWE (0x80) /* Software Watchdog Enable */ +#define MCF5206E_SYPCR_SWRI (0x40) /* Software Watchdog Reset/Interrupt Sel.*/ +#define MCF5206E_SYPCR_SWP (0x20) /* Software Watchdog Prescaler */ +#define MCF5206E_SYPCR_SWT (0x18) /* Software Watchdog Timing: */ +#define MCF5206E_SYPCR_SWT_S (3) +#define MCF5206E_SYPCR_SWT_9 (0x00) /* timeout = (1<<9)/sysfreq */ +#define MCF5206E_SYPCR_SWT_11 (0x08) /* timeout = (1<<11)/sysfreq */ +#define MCF5206E_SYPCR_SWT_13 (0x10) /* timeout = (1<<13)/sysfreq */ +#define MCF5206E_SYPCR_SWT_15 (0x18) /* timeout = (1<<15)/sysfreq */ +#define MCF5206E_SYPCR_SWT_18 (0x20) /* timeout = (1<<18)/sysfreq */ +#define MCF5206E_SYPCR_SWT_20 (0x28) /* timeout = (1<<20)/sysfreq */ +#define MCF5206E_SYPCR_SWT_22 (0x30) /* timeout = (1<<22)/sysfreq */ +#define MCF5206E_SYPCR_SWT_24 (0x38) /* timeout = (1<<24)/sysfreq */ +#define MCF5206E_SYPCR_BME (0x04) /* Bus Timeout Monitor Enable */ +#define MCF5206E_SYPCR_BMT (0x03) /* Bus Monitor Timing: */ +#define MCF5206E_SYPCR_BMT_1024 (0x00) /* timeout 1024 system clocks */ +#define MCF5206E_SYPCR_BMT_512 (0x01) /* timeout 512 system clocks */ +#define MCF5206E_SYPCR_BMT_256 (0x02) /* timeout 256 system clocks */ +#define MCF5206E_SYPCR_BMT_128 (0x03) /* timeout 128 system clocks */ + +/* Software Watchdog Interrupt Vector Register */ +#define MCF5206E_SWIVR(mbar) MCF5206E_REG8(mbar,0x042) + +/* Software Watchdog Service Register */ +#define MCF5206E_SWSR(mbar) MCF5206E_REG8(mbar,0x043) +#define MCF5206E_SWSR_KEY1 (0x55) +#define MCF5206E_SWSR_KEY2 (0xAA) + +/* Pin Assignment Register */ +#define MCF5206E_PAR(mbar) MCF5206E_REG16(mbar,0x0CA) +#define MCF5206E_PAR_PAR9 (0x200) +#define MCF5206E_PAR_PAR9_TOUT (0x000) /* Timer 0 output */ +#define MCF5206E_PAR_PAR9_DREQ1 (0x200) /* DMA channel 1 request */ +#define MCF5206E_PAR_PAR8 (0x100) +#define MCF5206E_PAR_PAR8_TIN0 (0x000) /* Timer 1 input */ +#define MCF5206E_PAR_PAR8_DREQ0 (0x100) /* DMA channel 0 request */ +#define MCF5206E_PAR_PAR7 (0x080) +#define MCF5206E_PAR_PAR7_RSTO (0x000) /* Reset output */ +#define MCF5206E_PAR_PAR7_UART2 (0x080) /* UART 2 RTS output */ +#define MCF5206E_PAR_PAR6 (0x040) +#define MCF5206E_PAR_PAR6_IRQ (0x000) /* IRQ7, IRQ4, IRQ1 */ +#define MCF5206E_PAR_PAR6_IPL (0x040) /* IPL2, IPL1, IPL0 */ +#define MCF5206E_PAR_PAR5 (0x020) +#define MCF5206E_PAR_PAR5_GPIO (0x000) /* General purpose I/O PP7-PP4 */ +#define MCF5206E_PAR_PAR5_PST (0x020) /* BDM signals PST3-PST0 */ +#define MCF5206E_PAR_PAR4 (0x010) +#define MCF5206E_PAR_PAR4_GPIO (0x000) /* General purpose I/O PP3-PP0 */ +#define MCF5206E_PAR_PAR4_DDATA (0x010) /* BDM signals DDATA3-DDATA0 */ +#define MCF5206E_PAR_PAR3 (0x008) +#define MCF5206E_PAR_PAR2 (0x004) +#define MCF5206E_PAR_PAR1 (0x002) +#define MCF5206E_PAR_PAR0 (0x001) +#define MCF5206E_PAR_WE0_WE1_WE2_WE3 (0x000) +#define MCF5206E_PAR_WE0_WE1_CS5_CS4 (0x001) +#define MCF5206E_PAR_WE0_WE1_CS5_A24 (0x002) +#define MCF5206E_PAR_WE0_WE1_A25_A24 (0x003) +#define MCF5206E_PAR_WE0_CS6_CS5_CS4 (0x004) +#define MCF5206E_PAR_WE0_CS6_CS5_A24 (0x005) +#define MCF5206E_PAR_WE0_CS6_A25_A24 (0x006) +#define MCF5206E_PAR_WE0_A26_A25_A24 (0x007) +#define MCF5206E_PAR_CS7_CS6_CS5_CS4 (0x008) +#define MCF5206E_PAR_CS7_CS6_CS4_A24 (0x009) +#define MCF5206E_PAR_CS7_CS6_A25_A24 (0x00A) +#define MCF5206E_PAR_CS7_A26_A25_A24 (0x00B) +#define MCF5206E_PAR_A27_A26_A25_A24 (0x00C) + +/* Bus Master Arbitration Control */ +#define MCF5206E_MARB(mbar) MCF5206E_REG8(mbar,0x007) +#define MCF5206E_MARB_NOARB (0x08) /* Arbiter operation disable */ +#define MCF5206E_MARB_ARBCTRL (0x04) /* Arb. order: Internal DMA, Coldfire */ + +/*** Chip Select Module -- MCF5206e User's Manual, Chapter 9 ***/ + +/* Chip Select Address Register */ +#define MCF5206E_CSAR(mbar,bank) MCF5206E_REG16(mbar,0x064 + ((bank) * 12)) + +/* Chip Select Mask Register */ +#define MCF5206E_CSMR(mbar,bank) MCF5206E_REG32(mbar,0x068 + ((bank) * 12)) +#define MCF5206E_CSMR_BAM (0xffff0000) /* Base Address Mask */ +#define MCF5206E_CSMR_BAM_S (16) +#define MCF5206E_CSMR_MASK_256M (0x0FFF0000) +#define MCF5206E_CSMR_MASK_128M (0x07FF0000) +#define MCF5206E_CSMR_MASK_64M (0x03FF0000) +#define MCF5206E_CSMR_MASK_32M (0x01FF0000) +#define MCF5206E_CSMR_MASK_16M (0x00FF0000) +#define MCF5206E_CSMR_MASK_8M (0x007F0000) +#define MCF5206E_CSMR_MASK_4M (0x003F0000) +#define MCF5206E_CSMR_MASK_2M (0x001F0000) +#define MCF5206E_CSMR_MASK_1M (0x000F0000) +#define MCF5206E_CSMR_MASK_1024K (0x000F0000) +#define MCF5206E_CSMR_MASK_512K (0x00070000) +#define MCF5206E_CSMR_MASK_256K (0x00030000) +#define MCF5206E_CSMR_MASK_128K (0x00010000) +#define MCF5206E_CSMR_MASK_64K (0x00000000) +#define MCF5206E_CSMR_CI (0x00000020) /* CPU Space Mask (CSMR1 only) */ +#define MCF5206E_CSMR_SC (0x00000010) /* Supervisor Code Space Mask */ +#define MCF5206E_CSMR_SD (0x00000008) /* Supervisor Data Space Mask */ +#define MCF5206E_CSMR_UC (0x00000004) /* User Code Space Mask */ +#define MCF5206E_CSMR_UD (0x00000002) /* User Data Space Mask */ + +/* Chip Select Control Register */ +#define MCF5206E_CSCR(mbar,bank) MCF5206E_REG16(mbar,0x6E + ((bank) * 12)) +#define MCF5206E_CSCR_WS (0x3c00) /* Wait States */ +#define MCF5206E_CSCR_WS_S (10) +#define MCF5206E_CSCR_WS0 (0x0000) /* 0 Wait States */ +#define MCF5206E_CSCR_WS1 (0x0400) /* 1 Wait States */ +#define MCF5206E_CSCR_WS2 (0x0800) /* 2 Wait States */ +#define MCF5206E_CSCR_WS3 (0x0C00) /* 3 Wait States */ +#define MCF5206E_CSCR_WS4 (0x1000) /* 4 Wait States */ +#define MCF5206E_CSCR_WS5 (0x1400) /* 5 Wait States */ +#define MCF5206E_CSCR_WS6 (0x1800) /* 6 Wait States */ +#define MCF5206E_CSCR_WS7 (0x1C00) /* 7 Wait States */ +#define MCF5206E_CSCR_WS8 (0x2000) /* 8 Wait States */ +#define MCF5206E_CSCR_WS9 (0x2400) /* 9 Wait States */ +#define MCF5206E_CSCR_WS10 (0x2800) /* 10 Wait States */ +#define MCF5206E_CSCR_WS11 (0x2C00) /* 11 Wait States */ +#define MCF5206E_CSCR_WS12 (0x3000) /* 12 Wait States */ +#define MCF5206E_CSCR_WS13 (0x3400) /* 13 Wait States */ +#define MCF5206E_CSCR_WS14 (0x3800) /* 14 Wait States */ +#define MCF5206E_CSCR_WS15 (0x3C00) /* 15 Wait States */ +#define MCF5206E_CSCR_BRST (0x0200) /* Burst Enable */ +#define MCF5206E_CSCR_AA (0x0100) /* Coldfire Core Auto Acknowledge + Enable */ +#define MCF5206E_CSCR_PS (0x00C0) /* Port Size */ +#define MCF5206E_CSCR_PS_S (6) +#define MCF5206E_CSCR_PS_32 (0x0000) /* Port Size = 32 bits */ +#define MCF5206E_CSCR_PS_8 (0x0040) /* Port Size = 8 bits */ +#define MCF5206E_CSCR_PS_16 (0x0080) /* Port Size = 16 bits */ +#define MCF5206E_CSCR_EMAA (0x0020) /* External Master Automatic Acknowledge + Enable */ +#define MCF5206E_CSCR_ASET (0x0010) /* Address Setup Enable */ +#define MCF5206E_CSCR_WRAH (0x0008) /* Write Address Hold Enable */ +#define MCF5206E_CSCR_RDAH (0x0004) /* Read Address Hold Enable */ +#define MCF5206E_CSCR_WR (0x0002) /* Write Enable */ +#define MCF5206E_CSCR_RD (0x0001) /* Read Enable */ + +/* Default Memory Control Register */ +#define MCF5206E_DMCR(mbar) MCF5206E_REG16(mbar, 0x0C6) + +/*** Parallel Port (GPIO) Module -- MCF5206e User's Manual, Chapter 10 ***/ + +/* Port A Data Direction Register */ +#define MCF5206E_PPDDR(mbar) MCF5206E_REG8(mbar,0x1C5) + +/* Port A Data Register */ +#define MCF5206E_PPDAT(mbar) MCF5206E_REG8(mbar,0x1C9) + +#define MCF5206E_PP_DAT0 (0x01) +#define MCF5206E_PP_DAT1 (0x02) +#define MCF5206E_PP_DAT2 (0x04) +#define MCF5206E_PP_DAT3 (0x08) +#define MCF5206E_PP_DAT4 (0x10) +#define MCF5206E_PP_DAT5 (0x20) +#define MCF5206E_PP_DAT6 (0x40) +#define MCF5206E_PP_DAT7 (0x80) + +/*** DRAM Controller -- MCF5206e User's Manual, Chapter 11 ***/ + +/* DRAM Controller Refresh Register */ +#define MCF5206E_DCRR(mbar) MCF5206E_REG16(mbar,0x046) + +/* DRAM Controller Timing Register */ +#define MCF5206E_DCTR(mbar) MCF5206E_REG16(mbar,0x04A) +#define MCF5206E_DCTR_DAEM (0x8000) /* Drive Multiplexed Address During + External Master DRAM Transfers */ +#define MCF5206E_DCTR_EDO (0x4000) /* Extended Data-Out Enable */ +#define MCF5206E_DCTR_RCD (0x1000) /* RAS-to-CAS Delay Time */ +#define MCF5206E_DCTR_RSH (0x0600) /* RAS Hold Time */ +#define MCF5206E_DCTR_RSH_0 (0x0000) /* See User's Manual for details */ +#define MCF5206E_DCTR_RSH_1 (0x0200) +#define MCF5206E_DCTR_RSH_2 (0x0400) +#define MCF5206E_DCTR_RP (0x0060) /* RAS Precharge Time */ +#define MCF5206E_DCTR_RP_15 (0x0000) /* RAS Precharges for 1.5 system clks */ +#define MCF5206E_DCTR_RP_25 (0x0020) /* RAS Precharges for 2.5 system clks */ +#define MCF5206E_DCTR_RP_35 (0x0040) /* RAS Precharges for 3.5 system clks */ +#define MCF5206E_DCTR_CAS (0x0008) /* Column Address Strobe Time */ +#define MCF5206E_DCTR_CP (0x0002) /* CAS Precharge Time */ +#define MCF5206E_DCTR_CSR (0x0001) /* CAS Setup Time for CAS before RAS + refresh */ + +/* DRAM Controller Address Registers */ +#define MCF5206E_DCAR(mbar,bank) MCF5206E_REG16(mbar,0x4C + ((bank) * 12)) + +/* DRAM Controller Mask Registers */ +#define MCF5206E_DCMR(mbar,bank) MCF5206E_REG32(mbar,0x50 + ((bank) * 12)) +#define MCF5206E_DCMR_BAM (0xffff0000) /* Base Address Mask */ +#define MCF5206E_DCMR_BAM_S (16) +#define MCF5206E_DCMR_MASK_256M (0x0FFE0000) +#define MCF5206E_DCMR_MASK_128M (0x07FE0000) +#define MCF5206E_DCMR_MASK_64M (0x03FE0000) +#define MCF5206E_DCMR_MASK_32M (0x01FE0000) +#define MCF5206E_DCMR_MASK_16M (0x00FE0000) +#define MCF5206E_DCMR_MASK_8M (0x007E0000) +#define MCF5206E_DCMR_MASK_4M (0x003E0000) +#define MCF5206E_DCMR_MASK_2M (0x001E0000) +#define MCF5206E_DCMR_MASK_1M (0x000E0000) +#define MCF5206E_DCMR_MASK_1024K (0x000E0000) +#define MCF5206E_DCMR_MASK_512K (0x00060000) +#define MCF5206E_DCMR_MASK_256K (0x00020000) +#define MCF5206E_DCMR_MASK_128K (0x00000000) +#define MCF5206E_DCMR_SC (0x00000010) /* Supervisor Code Space Mask */ +#define MCF5206E_DCMR_SD (0x00000008) /* Supervisor Data Space Mask */ +#define MCF5206E_DCMR_UC (0x00000004) /* User Code Space Mask */ +#define MCF5206E_DCMR_UD (0x00000002) /* User Data Space Mask */ + +/* DRAM Controller Control Register */ +#define MCF5206E_DCCR(mbar,bank) MCF5206E_REG8(mbar, 0x57 + ((bank) * 12)) +#define MCF5206E_DCCR_PS (0xC0) /* Port Size */ +#define MCF5206E_DCCR_PS_32 (0x00) /* 32 bit Port Size */ +#define MCF5206E_DCCR_PS_8 (0x40) /* 8 bit Port Size */ +#define MCF5206E_DCCR_PS_16 (0x80) /* 16 bit Port Size */ +#define MCF5206E_DCCR_BPS (0x30) /* Bank Page Size */ +#define MCF5206E_DCCR_BPS_512 (0x00) /* 512 Byte Page Size */ +#define MCF5206E_DCCR_BPS_1K (0x10) /* 1 KByte Page Size */ +#define MCF5206E_DCCR_BPS_2K (0x20) /* 2 KByte Page Size */ +#define MCF5206E_DCCR_PM (0x0C) /* Page Mode Select */ +#define MCF5206E_DCCR_PM_NORMAL (0x00) /* Normal Mode */ +#define MCF5206E_DCCR_PM_BURSTP (0x04) /* Burst Page Mode */ +#define MCF5206E_DCCR_PM_FASTP (0x0C) /* Fast Page Mode */ +#define MCF5206E_DCCR_WR (0x02) /* Write Enable */ +#define MCF5206E_DCCR_RD (0x01) /* Read Enable */ + +/*** UART Module -- MCF5206e User's Manual, Chapter 12 ***/ + +#define MCF5206E_UART_CHANNELS (2) +/* UART Mode Register */ +#define MCF5206E_UMR(mbar,n) MCF5206E_REG8(mbar,0x140 + (((n)-1) * 0x40)) +#define MCF5206E_UMR1_RXRTS (0x80) /* Receiver Request-to-Send + Control */ +#define MCF5206E_UMR1_RXIRQ (0x40) /* Receiver Interrupt Select */ +#define MCF5206E_UMR1_ERR (0x20) /* Error Mode */ +#define MCF5206E_UMR1_PM (0x1C) /* Parity Mode, Parity Type */ +#define MCF5206E_UMR1_PM_EVEN (0x00) /* Even Parity */ +#define MCF5206E_UMR1_PM_ODD (0x04) /* Odd Parity */ +#define MCF5206E_UMR1_PM_FORCE_LOW (0x08) /* Force parity low */ +#define MCF5206E_UMR1_PM_FORCE_HIGH (0x0C) /* Force parity high */ +#define MCF5206E_UMR1_PM_NO_PARITY (0x10) /* No Parity */ +#define MCF5206E_UMR1_PM_MULTI_DATA (0x18) /* Multidrop mode - data char */ +#define MCF5206E_UMR1_PM_MULTI_ADDR (0x1C) /* Multidrop mode - addr char */ +#define MCF5206E_UMR1_BC (0x03) /* Bits per Character */ +#define MCF5206E_UMR1_BC_5 (0x00) /* 5 bits per character */ +#define MCF5206E_UMR1_BC_6 (0x01) /* 6 bits per character */ +#define MCF5206E_UMR1_BC_7 (0x02) /* 7 bits per character */ +#define MCF5206E_UMR1_BC_8 (0x03) /* 8 bits per character */ + +#define MCF5206E_UMR2_CM (0xC0) /* Channel Mode */ +#define MCF5206E_UMR2_CM_NORMAL (0x00) /* Normal Mode */ +#define MCF5206E_UMR2_CM_AUTO_ECHO (0x40) /* Automatic Echo Mode */ +#define MCF5206E_UMR2_CM_LOCAL_LOOP (0x80) /* Local Loopback Mode */ +#define MCF5206E_UMR2_CM_REMOTE_LOOP (0xC0) /* Remote Loopback Modde */ +#define MCF5206E_UMR2_TXRTS (0x20) /* Transmitter Ready-to-Send op */ +#define MCF5206E_UMR2_TXCTS (0x10) /* Transmitter Clear-to-Send op */ +#define MCF5206E_UMR2_SB (0x0F) /* Stop Bit Length */ +#define MCF5206E_UMR2_SB_1 (0x07) /* 1 Stop Bit for 6-8 bits char */ +#define MCF5206E_UMR2_SB_15 (0x08) /* 1.5 Stop Bits for 6-8 bits chr*/ +#define MCF5206E_UMR2_SB_2 (0x0F) /* 2 Stop Bits for 6-8 bits char */ +#define MCF5206E_UMR2_SB5_1 (0x00) /* 1 Stop Bits for 5 bit char */ +#define MCF5206E_UMR2_SB5_15 (0x07) /* 1.5 Stop Bits for 5 bit char */ +#define MCF5206E_UMR2_SB5_2 (0x0F) /* 2 Stop Bits for 5 bit char */ + +/* UART Status Register (read only) */ +#define MCF5206E_USR(mbar,n) MCF5206E_REG8(mbar,0x144 + (((n)-1) * 0x40)) +#define MCF5206E_USR_RB (0x80) /* Received Break */ +#define MCF5206E_USR_FE (0x40) /* Framing Error */ +#define MCF5206E_USR_PE (0x20) /* Parity Error */ +#define MCF5206E_USR_OE (0x10) /* Overrun Error */ +#define MCF5206E_USR_TXEMP (0x08) /* Transmitter Empty */ +#define MCF5206E_USR_TXRDY (0x04) /* Transmitter Ready */ +#define MCF5206E_USR_FFULL (0x02) /* FIFO Full */ +#define MCF5206E_USR_RXRDY (0x01) /* Receiver Ready */ + +/* UART Clock Select Register (write only) */ +#define MCF5206E_UCSR(mbar,n) MCF5206E_REG8(mbar,0x144 + (((n)-1) * 0x40)) +#define MCF5206E_UCSR_RCS (0xF0) /* Receiver Clock Select */ +#define MCF5206E_UCSR_RCS_TIMER (0xD0) /* Timer */ +#define MCF5206E_UCSR_RCS_EXT16 (0xE0) /* External clk x16 */ +#define MCF5206E_UCSR_RCS_EXT (0xF0) /* External clk x1 */ +#define MCF5206E_UCSR_TCS (0x0F) /* Transmitter Clock Select */ +#define MCF5206E_UCSR_TCS_TIMER (0x0D) /* Timer */ +#define MCF5206E_UCSR_TCS_EXT16 (0x0E) /* External clk x16 */ +#define MCF5206E_UCSR_TCS_EXT (0x0F) /* External clk x1 */ + +/* UART Command Register (write only) */ +#define MCF5206E_UCR(mbar,n) MCF5206E_REG8(mbar,0x148 + (((n)-1) * 0x40)) +#define MCF5206E_UCR_MISC (0x70) /* Miscellaneous Commands: */ +#define MCF5206E_UCR_MISC_NOP (0x00) /* No Command */ +#define MCF5206E_UCR_MISC_RESET_MR (0x10) /* Reset Mode Register Ptr */ +#define MCF5206E_UCR_MISC_RESET_RX (0x20) /* Reset Receiver */ +#define MCF5206E_UCR_MISC_RESET_TX (0x30) /* Reset Transmitter */ +#define MCF5206E_UCR_MISC_RESET_ERR (0x40) /* Reset Error Status */ +#define MCF5206E_UCR_MISC_RESET_BRK (0x50) /* Reset Break-Change Interrupt */ +#define MCF5206E_UCR_MISC_START_BRK (0x60) /* Start Break */ +#define MCF5206E_UCR_MISC_STOP_BRK (0x70) /* Stop Break */ +#define MCF5206E_UCR_TC (0x0C) /* Transmitter Commands: */ +#define MCF5206E_UCR_TC_NOP (0x00) /* No Action Taken */ +#define MCF5206E_UCR_TC_ENABLE (0x04) /* Transmitter Enable */ +#define MCF5206E_UCR_TC_DISABLE (0x08) /* Transmitter Disable */ +#define MCF5206E_UCR_RC (0x03) /* Receiver Commands: */ +#define MCF5206E_UCR_RC_NOP (0x00) /* No Action Taken */ +#define MCF5206E_UCR_RC_ENABLE (0x01) /* Receiver Enable */ +#define MCF5206E_UCR_RC_DISABLE (0x02) /* Receiver Disable */ + +/* UART Receive Buffer (read only) */ +#define MCF5206E_URB(mbar,n) MCF5206E_REG8(mbar,0x14C + (((n)-1) * 0x40)) + +/* UART Transmit Buffer (write only) */ +#define MCF5206E_UTB(mbar,n) MCF5206E_REG8(mbar,0x14C + (((n)-1) * 0x40)) + +/* UART Input Port Change Register (read only) */ +#define MCF5206E_UIPCR(mbar,n) MCF5206E_REG8(mbar,0x150 + (((n)-1) * 0x40)) +#define MCF5206E_UIPCR_COS (0x10) /* Change of State at CTS input */ +#define MCF5206E_UIPCR_CTS (0x01) /* Current State of CTS */ + +/* UART Auxiliary Control Register (write only) */ +#define MCF5206E_UACR(mbar,n) MCF5206E_REG8(mbar,0x150 + (((n)-1) * 0x40)) +#define MCF5206E_UACR_IEC (0x01) /* Input Enable Control - generate interrupt + on CTS change */ + +/* UART Interrupt Status Register (read only) */ +#define MCF5206E_UISR(mbar,n) MCF5206E_REG8(mbar,0x154 + (((n)-1) * 0x40)) +#define MCF5206E_UISR_COS (0x80) /* Change of State has occured at CTS */ +#define MCF5206E_UISR_DB (0x04) /* Delta Break */ +#define MCF5206E_UISR_RXRDY (0x02) /* Receiver Ready or FIFO Full */ +#define MCF5206E_UISR_TXRDY (0x01) /* Transmitter Ready */ + +/* UART Interrupt Mask Register (write only) */ +#define MCF5206E_UIMR(mbar,n) MCF5206E_REG8(mbar,0x154 + (((n)-1) * 0x40)) +#define MCF5206E_UIMR_COS (0x80) /* Change of State interrupt enable */ +#define MCF5206E_UIMR_DB (0x04) /* Delta Break interrupt enable */ +#define MCF5206E_UIMR_FFULL (0x02) /* FIFO Full interrupt enable */ +#define MCF5206E_UIMR_TXRDY (0x01) /* Transmitter Ready Interrupt enable */ + +/* UART Baud Rate Generator Prescale MSB Register */ +#define MCF5206E_UBG1(mbar,n) MCF5206E_REG8(mbar,0x158 + (((n)-1) * 0x40)) + +/* UART Baud Rate Generator Prescale LSB Register */ +#define MCF5206E_UBG2(mbar,n) MCF5206E_REG8(mbar,0x15C + (((n)-1) * 0x40)) + +/* UART Interrupt Vector Register */ +#define MCF5206E_UIVR(mbar,n) MCF5206E_REG8(mbar,0x170 + (((n)-1) * 0x40)) + +/* UART Input Port Register (read only) */ +#define MCF5206E_UIP(mbar,n) MCF5206E_REG8(mbar,0x174 + (((n)-1) * 0x40)) +#define MCF5206E_UIP_CTS (0x01) /* Current state of CTS input */ + +/* UART Output Port Bit Set Command (address-triggered command, write) */ +#define MCF5206E_UOP1(mbar,n) MCF5206E_REG8(mbar,0x178 + (((n)-1) * 0x40)) + +/* UART Output Port Bit Reset Command (address-triggered command, write */ +#define MCF5206E_UOP0(mbar,n) MCF5206E_REG8(mbar,0x17C + (((n)-1) * 0x40)) + +/*** M-BUS (I2C) Module -- MCF5206e User's Manual, Chapter 13 ***/ + +/* M-Bus Address Register */ +#define MCF5206E_MADR(mbar) MCF5206E_REG8(mbar, 0x1E0) + +/* M-Bus Frequency Divider Register */ +#define MCF5206E_MFDR(mbar) MCF5206E_REG8(mbar, 0x1E4) + +/* M-Bus Control Register */ +#define MCF5206E_MBCR(mbar) MCF5206E_REG8(mbar, 0x1E8) +#define MCF5206E_MBCR_MEN (0x80) /* M-Bus Enable */ +#define MCF5206E_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */ +#define MCF5206E_MBCR_MSTA (0x20) /* Master Mode Selection */ +#define MCF5206E_MBCR_MTX (0x10) /* Transmit Mode Selection */ +#define MCF5206E_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */ +#define MCF5206E_MBCR_RSTA (0x04) /* Repeat Start */ + +/* M-Bus Status Register */ +#define MCF5206E_MBSR(mbar) MCF5206E_REG8(mbar, 0x1EC) +#define MCF5206E_MBSR_MCF (0x80) /* Data Transferring Bit */ +#define MCF5206E_MBSR_MAAS (0x40) /* Addressed as a Slave Bit */ +#define MCF5206E_MBSR_MBB (0x20) /* Bus Busy Bit */ +#define MCF5206E_MBSR_MAL (0x10) /* Arbitration Lost */ +#define MCF5206E_MBSR_SRW (0x04) /* Slave Read/Write */ +#define MCF5206E_MBSR_MIF (0x02) /* MBus Interrupt pending */ +#define MCF5206E_MBSR_RXAK (0x01) /* Received Acknowledge */ + +/* M-Bus Data I/O Register */ +#define MCF5206E_MBDR(mbar) MCF5206E_REG8(mbar, 0x1F0) + +/*** Timer Module -- MCF5206e User's Manual, Chapter 14 ***/ + +/* Timer Mode Register */ +#define MCF5206E_TMR(mbar,n) MCF5206E_REG16(mbar, 0x100 + (((n)-1)*0x20)) +#define MCF5206E_TMR_PS (0xFF00) /* Prescaler Value */ +#define MCF5206E_TMR_PS_S (8) +#define MCF5206E_TMR_CE (0x00C0) /* Capture Edge and Enable + Interrupt */ +#define MCF5206E_TMR_CE_ANY (0x00C0) /* Capture on any edge */ +#define MCF5206E_TMR_CE_FALL (0x0080) /* Capture on falling edge only */ +#define MCF5206E_TMR_CE_RISE (0x0040) /* Capture on rising edge only */ +#define MCF5206E_TMR_CE_NONE (0x0000) /* Disable Interrupt on capture + event */ +#define MCF5206E_TMR_OM (0x0020) /* Output Mode - Toggle output */ +#define MCF5206E_TMR_ORI (0x0010) /* Output Reference Interrupt + Enable */ +#define MCF5206E_TMR_FRR (0x0008) /* Free Run/Restart */ +#define MCF5206E_TMR_ICLK (0x0006) /* Input Clock Source */ +#define MCF5206E_TMR_ICLK_TIN (0x0006) /* TIN pin (falling edge) */ +#define MCF5206E_TMR_ICLK_DIV16 (0x0004) /* Master system clock divided + by 16 */ +#define MCF5206E_TMR_ICLK_MSCLK (0x0002) /* Master System Clock */ +#define MCF5206E_TMR_ICLK_STOP (0x0000) /* Stops counter */ +#define MCF5206E_TMR_RST (0x0001) /* Reset/Enable Timer */ + +/* Timer Reference Register */ +#define MCF5206E_TRR(mbar,n) MCF5206E_REG16(mbar, 0x104 + (((n)-1)*0x20)) + +/* Timer Capture Register */ +#define MCF5206E_TCR(mbar,n) MCF5206E_REG16(mbar, 0x108 + (((n)-1)*0x20)) + +/* Timer Counter Register */ +#define MCF5206E_TCN(mbar,n) MCF5206E_REG16(mbar, 0x10C + (((n)-1)*0x20)) + +/* Timer Event Register */ +#define MCF5206E_TER(mbar,n) MCF5206E_REG8(mbar, 0x111 + (((n)-1)*0x20)) +#define MCF5206E_TER_REF (0x02) /* Output Reference Event */ +#define MCF5206E_TER_CAP (0x01) /* Capture Event */ + + + +#endif diff --git a/bsps/m68k/include/mcf5206/mcfmbus.h b/bsps/m68k/include/mcf5206/mcfmbus.h new file mode 100644 index 0000000000..f70a70e483 --- /dev/null +++ b/bsps/m68k/include/mcf5206/mcfmbus.h @@ -0,0 +1,129 @@ +/* + * MCF5206e MBUS module (I2C bus) driver header file + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __MCFBSP_MCFMBUS_H__ +#define __MCFBSP_MCFMBUS_H__ + +#include "mcf5206e.h" +#include "i2c.h" + +/* States of I2C machine */ +typedef enum mcfmbus_i2c_state { + STATE_IDLE, + STATE_ADDR_7, + STATE_ADDR_1_W, + STATE_ADDR_1_R, + STATE_SENDING, + STATE_RECEIVING +} mcfmbus_i2c_state; + +typedef struct mcfmbus { + uint32_t base; /* ColdFire internal peripherial base + address */ + enum mcfmbus_i2c_state state;/* State of I2C machine */ + i2c_message *msg; /* Pointer to the first message in transfer */ + int nmsg; /* Number of messages in transfer */ + i2c_message *cmsg; /* Current message */ + int byte; /* Byte number in current message */ + rtems_isr_entry oldisr; /* Old interrupt handler */ + rtems_id sema; /* MBUS semaphore */ + i2c_transfer_done done; /* Transfer done function */ + uintptr_t done_arg_ptr; /* Done function argument ptr */ +} mcfmbus; + +/* mcfmbus_initialize -- + * Initialize ColdFire MBUS I2C bus controller. + * + * PARAMETERS: + * i2c_bus - pointer to the bus descriptor structure + * base - ColdFire internal peripherial base address + * + * RETURNS: + * RTEMS_SUCCESSFUL, or RTEMS error code when initialization failed. + */ +rtems_status_code +mcfmbus_initialize(mcfmbus *i2c_bus, uint32_t base); + +/* mcfmbus_select_clock_divider -- + * Select divider for system clock which is used for I2C bus clock + * generation. Not each divider can be selected for I2C bus; this + * function select nearest larger or equal divider, or maximum + * possible divider, if passed value greater. + * + * PARAMETERS: + * i2c_bus - pointer to the bus descriptor structure + * divider - system frequency divider for I2C serial clock. + * + * RETURNS: + * RTEMS_SUCCESSFUL, if operation performed successfully, or + * RTEMS error code when failed. + */ +rtems_status_code +mcfmbus_select_clock_divider(mcfmbus *i2c_bus, int divider); + +/* mcfmbus_i2c_transfer -- + * Initiate multiple-messages transfer over I2C bus via ColdFire MBUS + * controller. + * + * PARAMETERS: + * bus - pointer to MBUS controller descriptor + * nmsg - number of messages + * msg - pointer to messages array + * done - function which is called when transfer is finished + * done_arg_ptr - arbitrary argument ptr passed to done funciton + * + * RETURNS: + * RTEMS_SUCCESSFUL if transfer initiated successfully, or error + * code when failed. + */ +rtems_status_code +mcfmbus_i2c_transfer(mcfmbus *bus, int nmsg, i2c_message *msg, + i2c_transfer_done done, void *done_arg_ptr); + +/* mcfmbus_i2c_done -- + * Close ColdFire MBUS I2C bus controller and release all resources. + * + * PARAMETERS: + * bus - pointer to MBUS controller descriptor + * + * RETURNS: + * RTEMS_SUCCESSFUL, if transfer initiated successfully, or error + * code when failed. + */ +rtems_status_code +mcfmbus_i2c_done(mcfmbus *i2c_bus); + +/* mcfmbus_i2c_interrupt_handler -- + * ColdFire MBUS I2C bus controller interrupt handler. This function + * called from real interrupt handler, and pointer to MBUS descriptor + * structure passed to this function. + * + * PARAMETERS: + * bus - pointert to the bus descriptor structure + * + * RETURNS: + * none + */ +void mcfmbus_i2c_interrupt_handler(mcfmbus *bus); + +/* mcfmbus_poll -- + * MBUS module poll routine; used to poll events when I2C driver + * operates in poll-driven mode. + * + * PARAMETERS: + * none + * + * RETURNS: + * none + */ +void mcfmbus_poll(mcfmbus *bus); + +#endif /* __MCFBSP_MCFMBUS_H__ */ diff --git a/bsps/m68k/include/mcf5206/mcfuart.h b/bsps/m68k/include/mcf5206/mcfuart.h new file mode 100644 index 0000000000..bd9df5bb56 --- /dev/null +++ b/bsps/m68k/include/mcf5206/mcfuart.h @@ -0,0 +1,109 @@ +/* + * Generic UART Serial driver for Motorola Coldfire processors definitions + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed. + * Author: Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __MCFUART_H__ +#define __MCFUART_H__ + +#include +#include "bsp.h" +#include "mcf5206e.h" + +/* + * The MCF5206e System Clock Frequency; 54MHz default + */ +#ifndef SYSTEM_CLOCK_FREQUENCY +#define SYSTEM_CLOCK_FREQUENCY BSP_SYSTEM_FREQUENCY +#endif + +/* + * The following structure is a descriptor of single UART channel. + * It contains the initialization information about channel and + * current operating values + */ +typedef struct mcfuart { + uint32_t chn; /* UART channel number */ + uint8_t intvec; /* UART interrupt vector number, or + 0 if polled I/O */ + void *tty; /* termios channel descriptor */ + + volatile const char *tx_buf; /* Transmit buffer from termios */ + volatile uint32_t tx_buf_len; /* Transmit buffer length */ + volatile uint32_t tx_ptr; /* Index of next char to transmit*/ + rtems_isr_entry old_handler; /* Saved interrupt handler */ + + tcflag_t c_iflag; /* termios input mode flags */ + bool parerr_mark_flag; /* Parity error processing + state */ +} mcfuart; + +/* mcfuart_init -- + * This function verifies the input parameters and perform initialization + * of the Motorola Coldfire on-chip UART descriptor structure. + * + */ +rtems_status_code +mcfuart_init(mcfuart *uart, void *tty, uint8_t intvec, + uint32_t chn); + +/* mcfuart_reset -- + * This function perform the hardware initialization of Motorola + * Coldfire processor on-chip UART controller using parameters + * filled by the mcfuart_init function. + */ +rtems_status_code +mcfuart_reset(mcfuart *uart); + +/* mcfuart_disable -- + * This function disable the operations on Motorola Coldfire UART + * controller + */ +rtems_status_code +mcfuart_disable(mcfuart *uart); + +/* mcfuart_set_attributes -- + * This function parse the termios attributes structure and perform + * the appropriate settings in hardware. + */ +int +mcfuart_set_attributes(mcfuart *mcf, const struct termios *t); + +/* mcfuart_poll_read -- + * This function tried to read character from MCF UART and perform + * error handling. + */ +int +mcfuart_poll_read(mcfuart *uart); + +/* mcfuart_interrupt_write -- + * This function initiate transmitting of the buffer in interrupt mode. + */ +ssize_t +mcfuart_interrupt_write(mcfuart *uart, const char *buf, size_t len); + +/* mcfuart_poll_write -- + * This function transmit buffer byte-by-byte in polling mode. + */ +ssize_t +mcfuart_poll_write(mcfuart *uart, const char *buf, size_t len); + +/* mcfuart_stop_remote_tx -- + * This function stop data flow from remote device. + */ +int +mcfuart_stop_remote_tx(mcfuart *uart); + +/* mcfuart_start_remote_tx -- + * This function resume data flow from remote device. + */ +int +mcfuart_start_remote_tx(mcfuart *uart); + +#endif diff --git a/bsps/m68k/include/mcf5223x/mcf5223x.h b/bsps/m68k/include/mcf5223x/mcf5223x.h new file mode 100644 index 0000000000..0886105b17 --- /dev/null +++ b/bsps/m68k/include/mcf5223x/mcf5223x.h @@ -0,0 +1,3362 @@ +/* + * File: mcf5223x.h + * Purpose: Register and bit definitions + */ + +#ifndef __MCF5223x_H__ +#define __MCF5223x_H__ + +typedef volatile unsigned char vuint8; +typedef volatile unsigned short vuint16; +typedef volatile unsigned long vuint32; + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x000000])) +#define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x000008])) +#define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) +#define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x000010])) +#define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x000011])) +#define MCF_SCM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) +#define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x000013])) +#define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) +#define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x00001C])) +#define MCF_SCM_MPR (*(vuint32*)(&__IPSBAR[0x000020])) +#define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x000021])) +#define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x000022])) +#define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x000023])) +#define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x000024])) +#define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x000025])) +#define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x000026])) +#define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x000027])) +#define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x000028])) +#define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x000029])) +#define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x00002A])) +#define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x00002B])) +#define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x00002C])) +#define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x000030])) +#define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x000031])) + +/* Bit definitions and macros for MCF_SCM_IPSBAR */ +#define MCF_SCM_IPSBAR_V (0x00000001) +#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000) + +/* Bit definitions and macros for MCF_SCM_RAMBAR */ +#define MCF_SCM_RAMBAR_BDE (0x00000200) +#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_SCM_CRSR */ +#define MCF_SCM_CRSR_CWDR (0x20) +#define MCF_SCM_CRSR_EXT (0x80) + +/* Bit definitions and macros for MCF_SCM_CWCR */ +#define MCF_SCM_CWCR_CWTIC (0x01) +#define MCF_SCM_CWCR_CWTAVAL (0x02) +#define MCF_SCM_CWCR_CWTA (0x04) +#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) +#define MCF_SCM_CWCR_CWRI (0x40) +#define MCF_SCM_CWCR_CWE (0x80) + +/* Bit definitions and macros for MCF_SCM_LPICR */ +#define MCF_SCM_LPICR_XIPL(x) (((x)&0x07)<<4) +#define MCF_SCM_LPICR_ENBSTOP (0x80) + +/* Bit definitions and macros for MCF_SCM_CWSR */ +#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SCM_PPMRH */ +#define MCF_SCM_PPMRH_CDPORTS (0x00000001) +#define MCF_SCM_PPMRH_CDEPORT (0x00000002) +#define MCF_SCM_PPMRH_CDPIT0 (0x00000008) +#define MCF_SCM_PPMRH_CDPIT1 (0x00000010) +#define MCF_SCM_PPMRH_CDADC (0x00000080) +#define MCF_SCM_PPMRH_CDGPT (0x00000100) +#define MCF_SCM_PPMRH_CDPWN (0x00000200) +#define MCF_SCM_PPMRH_CDFCAN (0x00000400) +#define MCF_SCM_PPMRH_CDCFM (0x00000800) + +/* Bit definitions and macros for MCF_SCM_PPMRL */ +#define MCF_SCM_PPMRL_CDG (0x00000002) +#define MCF_SCM_PPMRL_CDEIM (0x00000008) +#define MCF_SCM_PPMRL_CDDMA (0x00000010) +#define MCF_SCM_PPMRL_CDUART0 (0x00000020) +#define MCF_SCM_PPMRL_CDUART1 (0x00000040) +#define MCF_SCM_PPMRL_CDUART2 (0x00000080) +#define MCF_SCM_PPMRL_CDI2C (0x00000200) +#define MCF_SCM_PPMRL_CDQSPI (0x00000400) +#define MCF_SCM_PPMRL_CDDTIM0 (0x00002000) +#define MCF_SCM_PPMRL_CDDTIM1 (0x00004000) +#define MCF_SCM_PPMRL_CDDTIM2 (0x00008000) +#define MCF_SCM_PPMRL_CDDTIM3 (0x00010000) +#define MCF_SCM_PPMRL_CDINTC0 (0x00020000) + +/* Bit definitions and macros for MCF_SCM_MPARK */ +#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_MPARK_PRKLAST (0x00001000) +#define MCF_SCM_MPARK_TIMEOUT (0x00002000) +#define MCF_SCM_MPARK_FIXED (0x00004000) +#define MCF_SCM_MPARK_M0PRTY(x) (((x)&0x00000003)<<18) +#define MCF_SCM_MPARK_M2PRTY(x) (((x)&0x00000003)<<20) +#define MCF_SCM_MPARK_M3PRTY(x) (((x)&0x00000003)<<22) +#define MCF_SCM_MPARK_BCR24BIT (0x01000000) +#define MCF_SCM_MPARK_M2_P_EN (0x02000000) + +/* Bit definitions and macros for MCF_SCM_PPMRS */ +#define MCF_SCM_PPMRS_DISABLE_ALL (64) +#define MCF_SCM_PPMRS_DISABLE_CFM (43) +#define MCF_SCM_PPMRS_DISABLE_CAN (42) +#define MCF_SCM_PPMRS_DISABLE_PWM (41) +#define MCF_SCM_PPMRS_DISABLE_GPT (40) +#define MCF_SCM_PPMRS_DISABLE_ADC (39) +#define MCF_SCM_PPMRS_DISABLE_PIT1 (36) +#define MCF_SCM_PPMRS_DISABLE_PIT0 (35) +#define MCF_SCM_PPMRS_DISABLE_EPORT (33) +#define MCF_SCM_PPMRS_DISABLE_PORTS (32) +#define MCF_SCM_PPMRS_DISABLE_INTC (17) +#define MCF_SCM_PPMRS_DISABLE_DTIM3 (16) +#define MCF_SCM_PPMRS_DISABLE_DTIM2 (15) +#define MCF_SCM_PPMRS_DISABLE_DTIM1 (14) +#define MCF_SCM_PPMRS_DISABLE_DTIM0 (13) +#define MCF_SCM_PPMRS_DISABLE_QSPI (10) +#define MCF_SCM_PPMRS_DISABLE_I2C (9) +#define MCF_SCM_PPMRS_DISABLE_UART2 (7) +#define MCF_SCM_PPMRS_DISABLE_UART1 (6) +#define MCF_SCM_PPMRS_DISABLE_UART0 (5) +#define MCF_SCM_PPMRS_DISABLE_DMA (4) +#define MCF_SCM_PPMRS_SET_CDG (1) + +/* Bit definitions and macros for MCF_SCM_PPMRC */ +#define MCF_SCM_PPMRC_ENABLE_ALL (64) +#define MCF_SCM_PPMRC_ENABLE_CFM (43) +#define MCF_SCM_PPMRC_ENABLE_CAN (42) +#define MCF_SCM_PPMRC_ENABLE_PWM (41) +#define MCF_SCM_PPMRC_ENABLE_GPT (40) +#define MCF_SCM_PPMRC_ENABLE_ADC (39) +#define MCF_SCM_PPMRC_ENABLE_PIT1 (36) +#define MCF_SCM_PPMRC_ENABLE_PIT0 (35) +#define MCF_SCM_PPMRC_ENABLE_EPORT (33) +#define MCF_SCM_PPMRC_ENABLE_PORTS (32) +#define MCF_SCM_PPMRC_ENABLE_INTC (17) +#define MCF_SCM_PPMRC_ENABLE_DTIM3 (16) +#define MCF_SCM_PPMRC_ENABLE_DTIM2 (15) +#define MCF_SCM_PPMRC_ENABLE_DTIM1 (14) +#define MCF_SCM_PPMRC_ENABLE_DTIM0 (13) +#define MCF_SCM_PPMRC_ENABLE_QSPI (10) +#define MCF_SCM_PPMRC_ENABLE_I2C (9) +#define MCF_SCM_PPMRC_ENABLE_UART2 (7) +#define MCF_SCM_PPMRC_ENABLE_UART1 (6) +#define MCF_SCM_PPMRC_ENABLE_UART0 (5) +#define MCF_SCM_PPMRC_ENABLE_DMA (4) +#define MCF_SCM_PPMRC_CLEAR_CDG (1) + + +/********************************************************************* +* +* Power Management Module (PMM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PMM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) +#define MCF_PMM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) +#define MCF_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) +#define MCF_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) + +/* Bit definitions and macros for MCF_PMM_PPMRH */ +#define MCF_PMM_PPMRH_CDPORTS (0x00000001) +#define MCF_PMM_PPMRH_CDEPORT (0x00000002) +#define MCF_PMM_PPMRH_CDPIT0 (0x00000008) +#define MCF_PMM_PPMRH_CDPIT1 (0x00000010) +#define MCF_PMM_PPMRH_CDADC (0x00000080) +#define MCF_PMM_PPMRH_CDGPT (0x00000100) +#define MCF_PMM_PPMRH_CDPWM (0x00000200) +#define MCF_PMM_PPMRH_CDFCAN (0x00000400) +#define MCF_PMM_PPMRH_CDCFM (0x00000800) + +/* Bit definitions and macros for MCF_PMM_PPMRL */ +#define MCF_PMM_PPMRL_CDG (0x00000002) +#define MCF_PMM_PPMRL_CDEIM (0x00000008) +#define MCF_PMM_PPMRL_CDDMA (0x00000010) +#define MCF_PMM_PPMRL_CDUART0 (0x00000020) +#define MCF_PMM_PPMRL_CDUART1 (0x00000040) +#define MCF_PMM_PPMRL_CDUART2 (0x00000080) +#define MCF_PMM_PPMRL_CDI2C (0x00000200) +#define MCF_PMM_PPMRL_CDQSPI (0x00000400) +#define MCF_PMM_PPMRL_CDDTIM0 (0x00002000) +#define MCF_PMM_PPMRL_CDDTIM1 (0x00004000) +#define MCF_PMM_PPMRL_CDDTIM2 (0x00008000) +#define MCF_PMM_PPMRL_CDDTIM3 (0x00010000) +#define MCF_PMM_PPMRL_CDINTC0 (0x00020000) + +/* Bit definitions and macros for MCF_PMM_LPICR */ +#define MCF_PMM_LPICR_XIPL(x) (((x)&0x07)<<4) +#define MCF_PMM_LPICR_ENBSTOP (0x80) + +/* Bit definitions and macros for MCF_PMM_LPCR */ +#define MCF_PMM_LPCR_LVDSE (0x02) +#define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF_PMM_LPCR_LPMD_STOP (0xC0) +#define MCF_PMM_LPCR_LPMD_WAIT (0x80) +#define MCF_PMM_LPCR_LPMD_DOZE (0x40) +#define MCF_PMM_LPCR_LPMD_RUN (0x00) + + +/********************************************************************* +* +* DMA Controller Module (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DMA_DMAREQC (*(vuint32*)(&__IPSBAR[0x000014])) +#define MCF_DMA_SAR0 (*(vuint32*)(&__IPSBAR[0x000100])) +#define MCF_DMA_SAR1 (*(vuint32*)(&__IPSBAR[0x000110])) +#define MCF_DMA_SAR2 (*(vuint32*)(&__IPSBAR[0x000120])) +#define MCF_DMA_SAR3 (*(vuint32*)(&__IPSBAR[0x000130])) +#define MCF_DMA_SAR(x) (*(vuint32*)(&__IPSBAR[0x000100+((x)*0x010)])) +#define MCF_DMA_DAR0 (*(vuint32*)(&__IPSBAR[0x000104])) +#define MCF_DMA_DAR1 (*(vuint32*)(&__IPSBAR[0x000114])) +#define MCF_DMA_DAR2 (*(vuint32*)(&__IPSBAR[0x000124])) +#define MCF_DMA_DAR3 (*(vuint32*)(&__IPSBAR[0x000134])) +#define MCF_DMA_DAR(x) (*(vuint32*)(&__IPSBAR[0x000104+((x)*0x010)])) +#define MCF_DMA_DSR0 (*(vuint8 *)(&__IPSBAR[0x000108])) +#define MCF_DMA_DSR1 (*(vuint8 *)(&__IPSBAR[0x000118])) +#define MCF_DMA_DSR2 (*(vuint8 *)(&__IPSBAR[0x000128])) +#define MCF_DMA_DSR3 (*(vuint8 *)(&__IPSBAR[0x000138])) +#define MCF_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x000108+((x)*0x010)])) +#define MCF_DMA_BCR0 (*(vuint32*)(&__IPSBAR[0x000108])) +#define MCF_DMA_BCR1 (*(vuint32*)(&__IPSBAR[0x000118])) +#define MCF_DMA_BCR2 (*(vuint32*)(&__IPSBAR[0x000128])) +#define MCF_DMA_BCR3 (*(vuint32*)(&__IPSBAR[0x000138])) +#define MCF_DMA_BCR(x) (*(vuint32*)(&__IPSBAR[0x000108+((x)*0x010)])) +#define MCF_DMA_DCR0 (*(vuint32*)(&__IPSBAR[0x00010C])) +#define MCF_DMA_DCR1 (*(vuint32*)(&__IPSBAR[0x00011C])) +#define MCF_DMA_DCR2 (*(vuint32*)(&__IPSBAR[0x00012C])) +#define MCF_DMA_DCR3 (*(vuint32*)(&__IPSBAR[0x00013C])) +#define MCF_DMA_DCR(x) (*(vuint32*)(&__IPSBAR[0x00010C+((x)*0x010)])) + +/* Bit definitions and macros for MCF_DMA_DMAREQC */ +#define MCF_DMA_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) +#define MCF_DMA_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) +#define MCF_DMA_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) +#define MCF_DMA_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) +#define MCF_DMA_DMAREQC_DMAREQC_EXT(x) (((x)&0x0000000F)<<16) + +/* Bit definitions and macros for MCF_DMA_SAR */ +#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DAR */ +#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DSR */ +#define MCF_DMA_DSR_DONE (0x01) +#define MCF_DMA_DSR_BSY (0x02) +#define MCF_DMA_DSR_REQ (0x04) +#define MCF_DMA_DSR_BED (0x10) +#define MCF_DMA_DSR_BES (0x20) +#define MCF_DMA_DSR_CE (0x40) + +/* Bit definitions and macros for MCF_DMA_BCR */ +#define MCF_DMA_BCR_BCR(x) (((x)&0x00FFFFFF)<<0) +#define MCF_DMA_BCR_DSR(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_DMA_DCR */ +#define MCF_DMA_DCR_LCH2(x) (((x)&0x00000003)<<0) +#define MCF_DMA_DCR_LCH1(x) (((x)&0x00000003)<<2) +#define MCF_DMA_DCR_LINKCC(x) (((x)&0x00000003)<<4) +#define MCF_DMA_DCR_D_REQ (0x00000080) +#define MCF_DMA_DCR_DMOD(x) (((x)&0x0000000F)<<8) +#define MCF_DMA_DCR_SMOD(x) (((x)&0x0000000F)<<12) +#define MCF_DMA_DCR_START (0x00010000) +#define MCF_DMA_DCR_DSIZE(x) (((x)&0x00000003)<<17) +#define MCF_DMA_DCR_DINC (0x00080000) +#define MCF_DMA_DCR_SSIZE(x) (((x)&0x00000003)<<20) +#define MCF_DMA_DCR_SINC (0x00400000) +#define MCF_DMA_DCR_BWC(x) (((x)&0x00000007)<<25) +#define MCF_DMA_DCR_AA (0x10000000) +#define MCF_DMA_DCR_CS (0x20000000) +#define MCF_DMA_DCR_EEXT (0x40000000) +#define MCF_DMA_DCR_INT (0x80000000) +#define MCF_DMA_DCR_BWC_16K (0x1) +#define MCF_DMA_DCR_BWC_32K (0x2) +#define MCF_DMA_DCR_BWC_64K (0x3) +#define MCF_DMA_DCR_BWC_128K (0x4) +#define MCF_DMA_DCR_BWC_256K (0x5) +#define MCF_DMA_DCR_BWC_512K (0x6) +#define MCF_DMA_DCR_BWC_1024K (0x7) +#define MCF_DMA_DCR_DMOD_DIS (0x0) +#define MCF_DMA_DCR_DMOD_16 (0x1) +#define MCF_DMA_DCR_DMOD_32 (0x2) +#define MCF_DMA_DCR_DMOD_64 (0x3) +#define MCF_DMA_DCR_DMOD_128 (0x4) +#define MCF_DMA_DCR_DMOD_256 (0x5) +#define MCF_DMA_DCR_DMOD_512 (0x6) +#define MCF_DMA_DCR_DMOD_1K (0x7) +#define MCF_DMA_DCR_DMOD_2K (0x8) +#define MCF_DMA_DCR_DMOD_4K (0x9) +#define MCF_DMA_DCR_DMOD_8K (0xA) +#define MCF_DMA_DCR_DMOD_16K (0xB) +#define MCF_DMA_DCR_DMOD_32K (0xC) +#define MCF_DMA_DCR_DMOD_64K (0xD) +#define MCF_DMA_DCR_DMOD_128K (0xE) +#define MCF_DMA_DCR_DMOD_256K (0xF) +#define MCF_DMA_DCR_SMOD_DIS (0x0) +#define MCF_DMA_DCR_SMOD_16 (0x1) +#define MCF_DMA_DCR_SMOD_32 (0x2) +#define MCF_DMA_DCR_SMOD_64 (0x3) +#define MCF_DMA_DCR_SMOD_128 (0x4) +#define MCF_DMA_DCR_SMOD_256 (0x5) +#define MCF_DMA_DCR_SMOD_512 (0x6) +#define MCF_DMA_DCR_SMOD_1K (0x7) +#define MCF_DMA_DCR_SMOD_2K (0x8) +#define MCF_DMA_DCR_SMOD_4K (0x9) +#define MCF_DMA_DCR_SMOD_8K (0xA) +#define MCF_DMA_DCR_SMOD_16K (0xB) +#define MCF_DMA_DCR_SMOD_32K (0xC) +#define MCF_DMA_DCR_SMOD_64K (0xD) +#define MCF_DMA_DCR_SMOD_128K (0xE) +#define MCF_DMA_DCR_SMOD_256K (0xF) +#define MCF_DMA_DCR_SSIZE_LONG (0x0) +#define MCF_DMA_DCR_SSIZE_BYTE (0x1) +#define MCF_DMA_DCR_SSIZE_WORD (0x2) +#define MCF_DMA_DCR_SSIZE_LINE (0x3) +#define MCF_DMA_DCR_DSIZE_LONG (0x0) +#define MCF_DMA_DCR_DSIZE_BYTE (0x1) +#define MCF_DMA_DCR_DSIZE_WORD (0x2) +#define MCF_DMA_DCR_DSIZE_LINE (0x3) +#define MCF_DMA_DCR_LCH1_CH0 (0x0) +#define MCF_DMA_DCR_LCH1_CH1 (0x1) +#define MCF_DMA_DCR_LCH1_CH2 (0x2) +#define MCF_DMA_DCR_LCH1_CH3 (0x3) +#define MCF_DMA_DCR_LCH2_CH0 (0x0) +#define MCF_DMA_DCR_LCH2_CH1 (0x1) +#define MCF_DMA_DCR_LCH2_CH2 (0x2) +#define MCF_DMA_DCR_LCH2_CH3 (0x3) + + +/********************************************************************* +* +* Universal Asynchronous Receiver Transmitter (UART) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_UART0_UMR (*(vuint8 *)(&__IPSBAR[0x000200])) +#define MCF_UART0_USR (*(vuint8 *)(&__IPSBAR[0x000204])) +#define MCF_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x000204])) +#define MCF_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x000208])) +#define MCF_UART0_URB (*(vuint8 *)(&__IPSBAR[0x00020C])) +#define MCF_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x00020C])) +#define MCF_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x000210])) +#define MCF_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x000210])) +#define MCF_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x000214])) +#define MCF_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x000214])) +#define MCF_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x000218])) +#define MCF_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x00021C])) +#define MCF_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x000234])) +#define MCF_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x000238])) +#define MCF_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x00023C])) +#define MCF_UART1_UMR (*(vuint8 *)(&__IPSBAR[0x000240])) +#define MCF_UART1_USR (*(vuint8 *)(&__IPSBAR[0x000244])) +#define MCF_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x000244])) +#define MCF_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x000248])) +#define MCF_UART1_URB (*(vuint8 *)(&__IPSBAR[0x00024C])) +#define MCF_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x00024C])) +#define MCF_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x000250])) +#define MCF_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x000250])) +#define MCF_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x000254])) +#define MCF_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x000254])) +#define MCF_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x000258])) +#define MCF_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x00025C])) +#define MCF_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x000274])) +#define MCF_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x000278])) +#define MCF_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x00027C])) +#define MCF_UART2_UMR (*(vuint8 *)(&__IPSBAR[0x000280])) +#define MCF_UART2_USR (*(vuint8 *)(&__IPSBAR[0x000284])) +#define MCF_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x000284])) +#define MCF_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x000288])) +#define MCF_UART2_URB (*(vuint8 *)(&__IPSBAR[0x00028C])) +#define MCF_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x00028C])) +#define MCF_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x000290])) +#define MCF_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x000290])) +#define MCF_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x000294])) +#define MCF_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x000294])) +#define MCF_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x000298])) +#define MCF_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x00029C])) +#define MCF_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x0002B4])) +#define MCF_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x0002B8])) +#define MCF_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x0002BC])) +#define MCF_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x000200+((x)*0x040)])) +#define MCF_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) +#define MCF_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) +#define MCF_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x000208+((x)*0x040)])) +#define MCF_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) +#define MCF_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) +#define MCF_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) +#define MCF_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) +#define MCF_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) +#define MCF_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) +#define MCF_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x000218+((x)*0x040)])) +#define MCF_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x00021C+((x)*0x040)])) +#define MCF_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x000234+((x)*0x040)])) +#define MCF_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x000238+((x)*0x040)])) +#define MCF_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x00023C+((x)*0x040)])) + +/* Bit definitions and macros for MCF_UART_UMR */ +#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) +#define MCF_UART_UMR_PT (0x04) +#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) +#define MCF_UART_UMR_ERR (0x20) +#define MCF_UART_UMR_RXIRQ (0x40) +#define MCF_UART_UMR_RXRTS (0x80) +#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) +#define MCF_UART_UMR_TXCTS (0x10) +#define MCF_UART_UMR_TXRTS (0x20) +#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) +#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) +#define MCF_UART_UMR_PM_MULTI_DATA (0x18) +#define MCF_UART_UMR_PM_NONE (0x10) +#define MCF_UART_UMR_PM_FORCE_HI (0x0C) +#define MCF_UART_UMR_PM_FORCE_LO (0x08) +#define MCF_UART_UMR_PM_ODD (0x04) +#define MCF_UART_UMR_PM_EVEN (0x00) +#define MCF_UART_UMR_BC_5 (0x00) +#define MCF_UART_UMR_BC_6 (0x01) +#define MCF_UART_UMR_BC_7 (0x02) +#define MCF_UART_UMR_BC_8 (0x03) +#define MCF_UART_UMR_CM_NORMAL (0x00) +#define MCF_UART_UMR_CM_ECHO (0x40) +#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) +#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) +#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) +#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) +#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for MCF_UART_USR */ +#define MCF_UART_USR_RXRDY (0x01) +#define MCF_UART_USR_FFULL (0x02) +#define MCF_UART_USR_TXRDY (0x04) +#define MCF_UART_USR_TXEMP (0x08) +#define MCF_UART_USR_OE (0x10) +#define MCF_UART_USR_PE (0x20) +#define MCF_UART_USR_FE (0x40) +#define MCF_UART_USR_RB (0x80) + +/* Bit definitions and macros for MCF_UART_UCSR */ +#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) +#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) +#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) +#define MCF_UART_UCSR_RCS_CTM16 (0xE0) +#define MCF_UART_UCSR_RCS_CTM (0xF0) +#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) +#define MCF_UART_UCSR_TCS_CTM16 (0x0E) +#define MCF_UART_UCSR_TCS_CTM (0x0F) + +/* Bit definitions and macros for MCF_UART_UCR */ +#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) +#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) +#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) +#define MCF_UART_UCR_NONE (0x00) +#define MCF_UART_UCR_STOP_BREAK (0x70) +#define MCF_UART_UCR_START_BREAK (0x60) +#define MCF_UART_UCR_BKCHGINT (0x50) +#define MCF_UART_UCR_RESET_ERROR (0x40) +#define MCF_UART_UCR_RESET_TX (0x30) +#define MCF_UART_UCR_RESET_RX (0x20) +#define MCF_UART_UCR_RESET_MR (0x10) +#define MCF_UART_UCR_TX_DISABLED (0x08) +#define MCF_UART_UCR_TX_ENABLED (0x04) +#define MCF_UART_UCR_RX_DISABLED (0x02) +#define MCF_UART_UCR_RX_ENABLED (0x01) + +/* Bit definitions and macros for MCF_UART_UIPCR */ +#define MCF_UART_UIPCR_CTS (0x01) +#define MCF_UART_UIPCR_COS (0x10) + +/* Bit definitions and macros for MCF_UART_UACR */ +#define MCF_UART_UACR_IEC (0x01) + +/* Bit definitions and macros for MCF_UART_UISR */ +#define MCF_UART_UISR_TXRDY (0x01) +#define MCF_UART_UISR_RXRDY_FU (0x02) +#define MCF_UART_UISR_DB (0x04) +#define MCF_UART_UISR_RXFTO (0x08) +#define MCF_UART_UISR_TXFIFO (0x10) +#define MCF_UART_UISR_RXFIFO (0x20) +#define MCF_UART_UISR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UIMR */ +#define MCF_UART_UIMR_TXRDY (0x01) +#define MCF_UART_UIMR_RXRDY_FU (0x02) +#define MCF_UART_UIMR_DB (0x04) +#define MCF_UART_UIMR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UIP */ +#define MCF_UART_UIP_CTS (0x01) + +/* Bit definitions and macros for MCF_UART_UOP1 */ +#define MCF_UART_UOP1_RTS (0x01) + +/* Bit definitions and macros for MCF_UART_UOP0 */ +#define MCF_UART_UOP0_RTS (0x01) + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2AR (*(vuint8 *)(&__IPSBAR[0x000300])) +#define MCF_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x000304])) +#define MCF_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x000308])) +#define MCF_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x00030C])) +#define MCF_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x000310])) + +/* Bit definitions and macros for MCF_I2C_I2AR */ +#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x04) +#define MCF_I2C_I2CR_TXAK (0x08) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x01) +#define MCF_I2C_I2SR_IIF (0x02) +#define MCF_I2C_I2SR_SRW (0x04) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2C_I2ICR_IE (0x01) +#define MCF_I2C_I2ICR_RE (0x02) +#define MCF_I2C_I2ICR_TE (0x04) +#define MCF_I2C_I2ICR_BNBE (0x08) + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_QSPI_QMR (*(vuint16*)(&__IPSBAR[0x000340])) +#define MCF_QSPI_QDLYR (*(vuint16*)(&__IPSBAR[0x000344])) +#define MCF_QSPI_QWR (*(vuint16*)(&__IPSBAR[0x000348])) +#define MCF_QSPI_QIR (*(vuint16*)(&__IPSBAR[0x00034C])) +#define MCF_QSPI_QAR (*(vuint16*)(&__IPSBAR[0x000350])) +#define MCF_QSPI_QDR (*(vuint16*)(&__IPSBAR[0x000354])) + +/* Bit definitions and macros for MCF_QSPI_QMR */ +#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) +#define MCF_QSPI_QMR_CPHA (0x0100) +#define MCF_QSPI_QMR_CPOL (0x0200) +#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define MCF_QSPI_QMR_DOHIE (0x4000) +#define MCF_QSPI_QMR_MSTR (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QDLYR */ +#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) +#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define MCF_QSPI_QDLYR_SPE (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QWR */ +#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) +#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define MCF_QSPI_QWR_CSIV (0x1000) +#define MCF_QSPI_QWR_WRTO (0x2000) +#define MCF_QSPI_QWR_WREN (0x4000) +#define MCF_QSPI_QWR_HALT (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QIR */ +#define MCF_QSPI_QIR_SPIF (0x0001) +#define MCF_QSPI_QIR_ABRT (0x0004) +#define MCF_QSPI_QIR_WCEF (0x0008) +#define MCF_QSPI_QIR_SPIFE (0x0100) +#define MCF_QSPI_QIR_ABRTE (0x0400) +#define MCF_QSPI_QIR_WCEFE (0x0800) +#define MCF_QSPI_QIR_ABRTL (0x1000) +#define MCF_QSPI_QIR_ABRTB (0x4000) +#define MCF_QSPI_QIR_WCEFB (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QAR */ +#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) + +/* Bit definitions and macros for MCF_QSPI_QDR */ +#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0) + +/********************************************************************* +* +* DMA Timers (DTIM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x000400])) +#define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x000402])) +#define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x000403])) +#define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x000404])) +#define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x000408])) +#define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x00040C])) +#define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x000440])) +#define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x000442])) +#define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x000443])) +#define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x000444])) +#define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x000448])) +#define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x00044C])) +#define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x000480])) +#define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x000482])) +#define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x000483])) +#define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x000484])) +#define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x000488])) +#define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x00048C])) +#define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x0004C0])) +#define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x0004C2])) +#define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x0004C3])) +#define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x0004C4])) +#define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x0004C8])) +#define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x0004CC])) +#define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x000400+((x)*0x040)])) +#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x000402+((x)*0x040)])) +#define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x000403+((x)*0x040)])) +#define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x000404+((x)*0x040)])) +#define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x000408+((x)*0x040)])) +#define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x00040C+((x)*0x040)])) + +/* Bit definitions and macros for MCF_DTIM_DTMR */ +#define MCF_DTIM_DTMR_RST (0x0001) +#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) +#define MCF_DTIM_DTMR_FRR (0x0008) +#define MCF_DTIM_DTMR_ORRI (0x0010) +#define MCF_DTIM_DTMR_OM (0x0020) +#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) +#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) +#define MCF_DTIM_DTMR_CE_ANY (0x00C0) +#define MCF_DTIM_DTMR_CE_FALL (0x0080) +#define MCF_DTIM_DTMR_CE_RISE (0x0040) +#define MCF_DTIM_DTMR_CE_NONE (0x0000) +#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) +#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) +#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) +#define MCF_DTIM_DTMR_CLK_STOP (0x0000) + +/* Bit definitions and macros for MCF_DTIM_DTXMR */ +#define MCF_DTIM_DTXMR_MODE16 (0x01) +#define MCF_DTIM_DTXMR_DMAEN (0x80) + +/* Bit definitions and macros for MCF_DTIM_DTER */ +#define MCF_DTIM_DTER_CAP (0x01) +#define MCF_DTIM_DTER_REF (0x02) + +/* Bit definitions and macros for MCF_DTIM_DTRR */ +#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCR */ +#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCN */ +#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC0_IPRH (*(vuint32*)(&__IPSBAR[0x000C00])) +#define MCF_INTC0_IPRL (*(vuint32*)(&__IPSBAR[0x000C04])) +#define MCF_INTC0_IMRH (*(vuint32*)(&__IPSBAR[0x000C08])) +#define MCF_INTC0_IMRL (*(vuint32*)(&__IPSBAR[0x000C0C])) +#define MCF_INTC0_INTFRCH (*(vuint32*)(&__IPSBAR[0x000C10])) +#define MCF_INTC0_INTFRCL (*(vuint32*)(&__IPSBAR[0x000C14])) +#define MCF_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0x000C18])) +#define MCF_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000C19])) +#define MCF_INTC0_ICR1 (*(vuint8 *)(&__IPSBAR[0x000C41])) +#define MCF_INTC0_ICR2 (*(vuint8 *)(&__IPSBAR[0x000C42])) +#define MCF_INTC0_ICR3 (*(vuint8 *)(&__IPSBAR[0x000C43])) +#define MCF_INTC0_ICR4 (*(vuint8 *)(&__IPSBAR[0x000C44])) +#define MCF_INTC0_ICR5 (*(vuint8 *)(&__IPSBAR[0x000C45])) +#define MCF_INTC0_ICR6 (*(vuint8 *)(&__IPSBAR[0x000C46])) +#define MCF_INTC0_ICR7 (*(vuint8 *)(&__IPSBAR[0x000C47])) +#define MCF_INTC0_ICR8 (*(vuint8 *)(&__IPSBAR[0x000C48])) +#define MCF_INTC0_ICR9 (*(vuint8 *)(&__IPSBAR[0x000C49])) +#define MCF_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0x000C4A])) +#define MCF_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0x000C4B])) +#define MCF_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0x000C4C])) +#define MCF_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0x000C4D])) +#define MCF_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0x000C4E])) +#define MCF_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0x000C4F])) +#define MCF_INTC0_ICR16 (*(vuint8 *)(&__IPSBAR[0x000C50])) +#define MCF_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0x000C51])) +#define MCF_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0x000C52])) +#define MCF_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0x000C53])) +#define MCF_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0x000C54])) +#define MCF_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0x000C55])) +#define MCF_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0x000C56])) +#define MCF_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0x000C57])) +#define MCF_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0x000C58])) +#define MCF_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0x000C59])) +#define MCF_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0x000C5A])) +#define MCF_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0x000C5B])) +#define MCF_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0x000C5C])) +#define MCF_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0x000C5D])) +#define MCF_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0x000C5E])) +#define MCF_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0x000C5F])) +#define MCF_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0x000C60])) +#define MCF_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0x000C61])) +#define MCF_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0x000C62])) +#define MCF_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0x000C63])) +#define MCF_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0x000C64])) +#define MCF_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0x000C65])) +#define MCF_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0x000C66])) +#define MCF_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0x000C67])) +#define MCF_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0x000C68])) +#define MCF_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0x000C69])) +#define MCF_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0x000C6A])) +#define MCF_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0x000C6B])) +#define MCF_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0x000C6C])) +#define MCF_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0x000C6D])) +#define MCF_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0x000C6E])) +#define MCF_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0x000C6F])) +#define MCF_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0x000C70])) +#define MCF_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0x000C71])) +#define MCF_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0x000C72])) +#define MCF_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0x000C73])) +#define MCF_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0x000C74])) +#define MCF_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0x000C75])) +#define MCF_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0x000C76])) +#define MCF_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0x000C77])) +#define MCF_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0x000C78])) +#define MCF_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0x000C79])) +#define MCF_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0x000C7A])) +#define MCF_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0x000C7B])) +#define MCF_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0x000C7C])) +#define MCF_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0x000C7D])) +#define MCF_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0x000C7E])) +#define MCF_INTC0_ICR63 (*(vuint8 *)(&__IPSBAR[0x000C7F])) +#define MCF_INTC0_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x-1)*0x001)])) +#define MCF_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0x000CE0])) +#define MCF_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0x000CE4])) +#define MCF_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0x000CE8])) +#define MCF_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0x000CEC])) +#define MCF_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0x000CF0])) +#define MCF_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0x000CF4])) +#define MCF_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0x000CF8])) +#define MCF_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0x000CFC])) +#define MCF_INTC0_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x-1)*0x004)])) +#define MCF_INTC1_IPRH (*(vuint32*)(&__IPSBAR[0x000D00])) +#define MCF_INTC1_IPRL (*(vuint32*)(&__IPSBAR[0x000D04])) +#define MCF_INTC1_IMRH (*(vuint32*)(&__IPSBAR[0x000D08])) +#define MCF_INTC1_IMRL (*(vuint32*)(&__IPSBAR[0x000D0C])) +#define MCF_INTC1_INTFRCH (*(vuint32*)(&__IPSBAR[0x000D10])) +#define MCF_INTC1_INTFRCL (*(vuint32*)(&__IPSBAR[0x000D14])) +#define MCF_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0x000D18])) +#define MCF_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000D19])) +#define MCF_INTC1_ICR1 (*(vuint8 *)(&__IPSBAR[0x000D41])) +#define MCF_INTC1_ICR2 (*(vuint8 *)(&__IPSBAR[0x000D42])) +#define MCF_INTC1_ICR3 (*(vuint8 *)(&__IPSBAR[0x000D43])) +#define MCF_INTC1_ICR4 (*(vuint8 *)(&__IPSBAR[0x000D44])) +#define MCF_INTC1_ICR5 (*(vuint8 *)(&__IPSBAR[0x000D45])) +#define MCF_INTC1_ICR6 (*(vuint8 *)(&__IPSBAR[0x000D46])) +#define MCF_INTC1_ICR7 (*(vuint8 *)(&__IPSBAR[0x000D47])) +#define MCF_INTC1_ICR8 (*(vuint8 *)(&__IPSBAR[0x000D48])) +#define MCF_INTC1_ICR9 (*(vuint8 *)(&__IPSBAR[0x000D49])) +#define MCF_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0x000D4A])) +#define MCF_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0x000D4B])) +#define MCF_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0x000D4C])) +#define MCF_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0x000D4D])) +#define MCF_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0x000D4E])) +#define MCF_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0x000D4F])) +#define MCF_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0x000D50])) +#define MCF_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0x000D51])) +#define MCF_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0x000D52])) +#define MCF_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0x000D53])) +#define MCF_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0x000D54])) +#define MCF_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0x000D55])) +#define MCF_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0x000D56])) +#define MCF_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0x000D57])) +#define MCF_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0x000D58])) +#define MCF_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0x000D59])) +#define MCF_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0x000D5A])) +#define MCF_INTC1_ICR27 (*(vuint8 *)(&__IPSBAR[0x000D5B])) +#define MCF_INTC1_ICR28 (*(vuint8 *)(&__IPSBAR[0x000D5C])) +#define MCF_INTC1_ICR29 (*(vuint8 *)(&__IPSBAR[0x000D5D])) +#define MCF_INTC1_ICR30 (*(vuint8 *)(&__IPSBAR[0x000D5E])) +#define MCF_INTC1_ICR31 (*(vuint8 *)(&__IPSBAR[0x000D5F])) +#define MCF_INTC1_ICR32 (*(vuint8 *)(&__IPSBAR[0x000D60])) +#define MCF_INTC1_ICR33 (*(vuint8 *)(&__IPSBAR[0x000D61])) +#define MCF_INTC1_ICR34 (*(vuint8 *)(&__IPSBAR[0x000D62])) +#define MCF_INTC1_ICR35 (*(vuint8 *)(&__IPSBAR[0x000D63])) +#define MCF_INTC1_ICR36 (*(vuint8 *)(&__IPSBAR[0x000D64])) +#define MCF_INTC1_ICR37 (*(vuint8 *)(&__IPSBAR[0x000D65])) +#define MCF_INTC1_ICR38 (*(vuint8 *)(&__IPSBAR[0x000D66])) +#define MCF_INTC1_ICR39 (*(vuint8 *)(&__IPSBAR[0x000D67])) +#define MCF_INTC1_ICR40 (*(vuint8 *)(&__IPSBAR[0x000D68])) +#define MCF_INTC1_ICR41 (*(vuint8 *)(&__IPSBAR[0x000D69])) +#define MCF_INTC1_ICR42 (*(vuint8 *)(&__IPSBAR[0x000D6A])) +#define MCF_INTC1_ICR43 (*(vuint8 *)(&__IPSBAR[0x000D6B])) +#define MCF_INTC1_ICR44 (*(vuint8 *)(&__IPSBAR[0x000D6C])) +#define MCF_INTC1_ICR45 (*(vuint8 *)(&__IPSBAR[0x000D6D])) +#define MCF_INTC1_ICR46 (*(vuint8 *)(&__IPSBAR[0x000D6E])) +#define MCF_INTC1_ICR47 (*(vuint8 *)(&__IPSBAR[0x000D6F])) +#define MCF_INTC1_ICR48 (*(vuint8 *)(&__IPSBAR[0x000D70])) +#define MCF_INTC1_ICR49 (*(vuint8 *)(&__IPSBAR[0x000D71])) +#define MCF_INTC1_ICR50 (*(vuint8 *)(&__IPSBAR[0x000D72])) +#define MCF_INTC1_ICR51 (*(vuint8 *)(&__IPSBAR[0x000D73])) +#define MCF_INTC1_ICR52 (*(vuint8 *)(&__IPSBAR[0x000D74])) +#define MCF_INTC1_ICR53 (*(vuint8 *)(&__IPSBAR[0x000D75])) +#define MCF_INTC1_ICR54 (*(vuint8 *)(&__IPSBAR[0x000D76])) +#define MCF_INTC1_ICR55 (*(vuint8 *)(&__IPSBAR[0x000D77])) +#define MCF_INTC1_ICR56 (*(vuint8 *)(&__IPSBAR[0x000D78])) +#define MCF_INTC1_ICR57 (*(vuint8 *)(&__IPSBAR[0x000D79])) +#define MCF_INTC1_ICR58 (*(vuint8 *)(&__IPSBAR[0x000D7A])) +#define MCF_INTC1_ICR59 (*(vuint8 *)(&__IPSBAR[0x000D7B])) +#define MCF_INTC1_ICR60 (*(vuint8 *)(&__IPSBAR[0x000D7C])) +#define MCF_INTC1_ICR61 (*(vuint8 *)(&__IPSBAR[0x000D7D])) +#define MCF_INTC1_ICR62 (*(vuint8 *)(&__IPSBAR[0x000D7E])) +#define MCF_INTC1_ICR63 (*(vuint8 *)(&__IPSBAR[0x000D7F])) +#define MCF_INTC1_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000D41+((x-1)*0x001)])) +#define MCF_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0x000DE0])) +#define MCF_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0x000DE4])) +#define MCF_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0x000DE8])) +#define MCF_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0x000DEC])) +#define MCF_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0x000DF0])) +#define MCF_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0x000DF4])) +#define MCF_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0x000DF8])) +#define MCF_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0x000DFC])) +#define MCF_INTC1_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000DE4+((x-1)*0x004)])) +#define MCF_INTC_IPRH(x) (*(vuint32*)(&__IPSBAR[0x000C00+((x)*0x100)])) +#define MCF_INTC_IPRL(x) (*(vuint32*)(&__IPSBAR[0x000C04+((x)*0x100)])) +#define MCF_INTC_IMRH(x) (*(vuint32*)(&__IPSBAR[0x000C08+((x)*0x100)])) +#define MCF_INTC_IMRL(x) (*(vuint32*)(&__IPSBAR[0x000C0C+((x)*0x100)])) +#define MCF_INTC_INTFRCH(x) (*(vuint32*)(&__IPSBAR[0x000C10+((x)*0x100)])) +#define MCF_INTC_INTFRCL(x) (*(vuint32*)(&__IPSBAR[0x000C14+((x)*0x100)])) +#define MCF_INTC_IRLR(x) (*(vuint8 *)(&__IPSBAR[0x000C18+((x)*0x100)])) +#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(&__IPSBAR[0x000C19+((x)*0x100)])) +#define MCF_INTC_ICR1(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x)*0x100)])) +#define MCF_INTC_ICR2(x) (*(vuint8 *)(&__IPSBAR[0x000C42+((x)*0x100)])) +#define MCF_INTC_ICR3(x) (*(vuint8 *)(&__IPSBAR[0x000C43+((x)*0x100)])) +#define MCF_INTC_ICR4(x) (*(vuint8 *)(&__IPSBAR[0x000C44+((x)*0x100)])) +#define MCF_INTC_ICR5(x) (*(vuint8 *)(&__IPSBAR[0x000C45+((x)*0x100)])) +#define MCF_INTC_ICR6(x) (*(vuint8 *)(&__IPSBAR[0x000C46+((x)*0x100)])) +#define MCF_INTC_ICR7(x) (*(vuint8 *)(&__IPSBAR[0x000C47+((x)*0x100)])) +#define MCF_INTC_ICR8(x) (*(vuint8 *)(&__IPSBAR[0x000C48+((x)*0x100)])) +#define MCF_INTC_ICR9(x) (*(vuint8 *)(&__IPSBAR[0x000C49+((x)*0x100)])) +#define MCF_INTC_ICR10(x) (*(vuint8 *)(&__IPSBAR[0x000C4A+((x)*0x100)])) +#define MCF_INTC_ICR11(x) (*(vuint8 *)(&__IPSBAR[0x000C4B+((x)*0x100)])) +#define MCF_INTC_ICR12(x) (*(vuint8 *)(&__IPSBAR[0x000C4C+((x)*0x100)])) +#define MCF_INTC_ICR13(x) (*(vuint8 *)(&__IPSBAR[0x000C4D+((x)*0x100)])) +#define MCF_INTC_ICR14(x) (*(vuint8 *)(&__IPSBAR[0x000C4E+((x)*0x100)])) +#define MCF_INTC_ICR15(x) (*(vuint8 *)(&__IPSBAR[0x000C4F+((x)*0x100)])) +#define MCF_INTC_ICR16(x) (*(vuint8 *)(&__IPSBAR[0x000C50+((x)*0x100)])) +#define MCF_INTC_ICR17(x) (*(vuint8 *)(&__IPSBAR[0x000C51+((x)*0x100)])) +#define MCF_INTC_ICR18(x) (*(vuint8 *)(&__IPSBAR[0x000C52+((x)*0x100)])) +#define MCF_INTC_ICR19(x) (*(vuint8 *)(&__IPSBAR[0x000C53+((x)*0x100)])) +#define MCF_INTC_ICR20(x) (*(vuint8 *)(&__IPSBAR[0x000C54+((x)*0x100)])) +#define MCF_INTC_ICR21(x) (*(vuint8 *)(&__IPSBAR[0x000C55+((x)*0x100)])) +#define MCF_INTC_ICR22(x) (*(vuint8 *)(&__IPSBAR[0x000C56+((x)*0x100)])) +#define MCF_INTC_ICR23(x) (*(vuint8 *)(&__IPSBAR[0x000C57+((x)*0x100)])) +#define MCF_INTC_ICR24(x) (*(vuint8 *)(&__IPSBAR[0x000C58+((x)*0x100)])) +#define MCF_INTC_ICR25(x) (*(vuint8 *)(&__IPSBAR[0x000C59+((x)*0x100)])) +#define MCF_INTC_ICR26(x) (*(vuint8 *)(&__IPSBAR[0x000C5A+((x)*0x100)])) +#define MCF_INTC_ICR27(x) (*(vuint8 *)(&__IPSBAR[0x000C5B+((x)*0x100)])) +#define MCF_INTC_ICR28(x) (*(vuint8 *)(&__IPSBAR[0x000C5C+((x)*0x100)])) +#define MCF_INTC_ICR29(x) (*(vuint8 *)(&__IPSBAR[0x000C5D+((x)*0x100)])) +#define MCF_INTC_ICR30(x) (*(vuint8 *)(&__IPSBAR[0x000C5E+((x)*0x100)])) +#define MCF_INTC_ICR31(x) (*(vuint8 *)(&__IPSBAR[0x000C5F+((x)*0x100)])) +#define MCF_INTC_ICR32(x) (*(vuint8 *)(&__IPSBAR[0x000C60+((x)*0x100)])) +#define MCF_INTC_ICR33(x) (*(vuint8 *)(&__IPSBAR[0x000C61+((x)*0x100)])) +#define MCF_INTC_ICR34(x) (*(vuint8 *)(&__IPSBAR[0x000C62+((x)*0x100)])) +#define MCF_INTC_ICR35(x) (*(vuint8 *)(&__IPSBAR[0x000C63+((x)*0x100)])) +#define MCF_INTC_ICR36(x) (*(vuint8 *)(&__IPSBAR[0x000C64+((x)*0x100)])) +#define MCF_INTC_ICR37(x) (*(vuint8 *)(&__IPSBAR[0x000C65+((x)*0x100)])) +#define MCF_INTC_ICR38(x) (*(vuint8 *)(&__IPSBAR[0x000C66+((x)*0x100)])) +#define MCF_INTC_ICR39(x) (*(vuint8 *)(&__IPSBAR[0x000C67+((x)*0x100)])) +#define MCF_INTC_ICR40(x) (*(vuint8 *)(&__IPSBAR[0x000C68+((x)*0x100)])) +#define MCF_INTC_ICR41(x) (*(vuint8 *)(&__IPSBAR[0x000C69+((x)*0x100)])) +#define MCF_INTC_ICR42(x) (*(vuint8 *)(&__IPSBAR[0x000C6A+((x)*0x100)])) +#define MCF_INTC_ICR43(x) (*(vuint8 *)(&__IPSBAR[0x000C6B+((x)*0x100)])) +#define MCF_INTC_ICR44(x) (*(vuint8 *)(&__IPSBAR[0x000C6C+((x)*0x100)])) +#define MCF_INTC_ICR45(x) (*(vuint8 *)(&__IPSBAR[0x000C6D+((x)*0x100)])) +#define MCF_INTC_ICR46(x) (*(vuint8 *)(&__IPSBAR[0x000C6E+((x)*0x100)])) +#define MCF_INTC_ICR47(x) (*(vuint8 *)(&__IPSBAR[0x000C6F+((x)*0x100)])) +#define MCF_INTC_ICR48(x) (*(vuint8 *)(&__IPSBAR[0x000C70+((x)*0x100)])) +#define MCF_INTC_ICR49(x) (*(vuint8 *)(&__IPSBAR[0x000C71+((x)*0x100)])) +#define MCF_INTC_ICR50(x) (*(vuint8 *)(&__IPSBAR[0x000C72+((x)*0x100)])) +#define MCF_INTC_ICR51(x) (*(vuint8 *)(&__IPSBAR[0x000C73+((x)*0x100)])) +#define MCF_INTC_ICR52(x) (*(vuint8 *)(&__IPSBAR[0x000C74+((x)*0x100)])) +#define MCF_INTC_ICR53(x) (*(vuint8 *)(&__IPSBAR[0x000C75+((x)*0x100)])) +#define MCF_INTC_ICR54(x) (*(vuint8 *)(&__IPSBAR[0x000C76+((x)*0x100)])) +#define MCF_INTC_ICR55(x) (*(vuint8 *)(&__IPSBAR[0x000C77+((x)*0x100)])) +#define MCF_INTC_ICR56(x) (*(vuint8 *)(&__IPSBAR[0x000C78+((x)*0x100)])) +#define MCF_INTC_ICR57(x) (*(vuint8 *)(&__IPSBAR[0x000C79+((x)*0x100)])) +#define MCF_INTC_ICR58(x) (*(vuint8 *)(&__IPSBAR[0x000C7A+((x)*0x100)])) +#define MCF_INTC_ICR59(x) (*(vuint8 *)(&__IPSBAR[0x000C7B+((x)*0x100)])) +#define MCF_INTC_ICR60(x) (*(vuint8 *)(&__IPSBAR[0x000C7C+((x)*0x100)])) +#define MCF_INTC_ICR61(x) (*(vuint8 *)(&__IPSBAR[0x000C7D+((x)*0x100)])) +#define MCF_INTC_ICR62(x) (*(vuint8 *)(&__IPSBAR[0x000C7E+((x)*0x100)])) +#define MCF_INTC_ICR63(x) (*(vuint8 *)(&__IPSBAR[0x000C7F+((x)*0x100)])) +#define MCF_INTC_SWIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE0+((x)*0x100)])) +#define MCF_INTC_L1IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x)*0x100)])) +#define MCF_INTC_L2IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE8+((x)*0x100)])) +#define MCF_INTC_L3IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CEC+((x)*0x100)])) +#define MCF_INTC_L4IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF0+((x)*0x100)])) +#define MCF_INTC_L5IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF4+((x)*0x100)])) +#define MCF_INTC_L6IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF8+((x)*0x100)])) +#define MCF_INTC_L7IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CFC+((x)*0x100)])) + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x00000001) +#define MCF_INTC_IPRH_INT33 (0x00000002) +#define MCF_INTC_IPRH_INT34 (0x00000004) +#define MCF_INTC_IPRH_INT35 (0x00000008) +#define MCF_INTC_IPRH_INT36 (0x00000010) +#define MCF_INTC_IPRH_INT37 (0x00000020) +#define MCF_INTC_IPRH_INT38 (0x00000040) +#define MCF_INTC_IPRH_INT39 (0x00000080) +#define MCF_INTC_IPRH_INT40 (0x00000100) +#define MCF_INTC_IPRH_INT41 (0x00000200) +#define MCF_INTC_IPRH_INT42 (0x00000400) +#define MCF_INTC_IPRH_INT43 (0x00000800) +#define MCF_INTC_IPRH_INT44 (0x00001000) +#define MCF_INTC_IPRH_INT45 (0x00002000) +#define MCF_INTC_IPRH_INT46 (0x00004000) +#define MCF_INTC_IPRH_INT47 (0x00008000) +#define MCF_INTC_IPRH_INT48 (0x00010000) +#define MCF_INTC_IPRH_INT49 (0x00020000) +#define MCF_INTC_IPRH_INT50 (0x00040000) +#define MCF_INTC_IPRH_INT51 (0x00080000) +#define MCF_INTC_IPRH_INT52 (0x00100000) +#define MCF_INTC_IPRH_INT53 (0x00200000) +#define MCF_INTC_IPRH_INT54 (0x00400000) +#define MCF_INTC_IPRH_INT55 (0x00800000) +#define MCF_INTC_IPRH_INT56 (0x01000000) +#define MCF_INTC_IPRH_INT57 (0x02000000) +#define MCF_INTC_IPRH_INT58 (0x04000000) +#define MCF_INTC_IPRH_INT59 (0x08000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x00000002) +#define MCF_INTC_IPRL_INT2 (0x00000004) +#define MCF_INTC_IPRL_INT3 (0x00000008) +#define MCF_INTC_IPRL_INT4 (0x00000010) +#define MCF_INTC_IPRL_INT5 (0x00000020) +#define MCF_INTC_IPRL_INT6 (0x00000040) +#define MCF_INTC_IPRL_INT7 (0x00000080) +#define MCF_INTC_IPRL_INT8 (0x00000100) +#define MCF_INTC_IPRL_INT9 (0x00000200) +#define MCF_INTC_IPRL_INT10 (0x00000400) +#define MCF_INTC_IPRL_INT11 (0x00000800) +#define MCF_INTC_IPRL_INT12 (0x00001000) +#define MCF_INTC_IPRL_INT13 (0x00002000) +#define MCF_INTC_IPRL_INT14 (0x00004000) +#define MCF_INTC_IPRL_INT15 (0x00008000) +#define MCF_INTC_IPRL_INT16 (0x00010000) +#define MCF_INTC_IPRL_INT17 (0x00020000) +#define MCF_INTC_IPRL_INT18 (0x00040000) +#define MCF_INTC_IPRL_INT19 (0x00080000) +#define MCF_INTC_IPRL_INT20 (0x00100000) +#define MCF_INTC_IPRL_INT21 (0x00200000) +#define MCF_INTC_IPRL_INT22 (0x00400000) +#define MCF_INTC_IPRL_INT23 (0x00800000) +#define MCF_INTC_IPRL_INT24 (0x01000000) +#define MCF_INTC_IPRL_INT25 (0x02000000) +#define MCF_INTC_IPRL_INT26 (0x04000000) +#define MCF_INTC_IPRL_INT27 (0x08000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_MASK32 (0x00000001) +#define MCF_INTC_IMRH_MASK33 (0x00000002) +#define MCF_INTC_IMRH_MASK34 (0x00000004) +#define MCF_INTC_IMRH_MASK35 (0x00000008) +#define MCF_INTC_IMRH_MASK36 (0x00000010) +#define MCF_INTC_IMRH_MASK37 (0x00000020) +#define MCF_INTC_IMRH_MASK38 (0x00000040) +#define MCF_INTC_IMRH_MASK39 (0x00000080) +#define MCF_INTC_IMRH_MASK40 (0x00000100) +#define MCF_INTC_IMRH_MASK41 (0x00000200) +#define MCF_INTC_IMRH_MASK42 (0x00000400) +#define MCF_INTC_IMRH_MASK43 (0x00000800) +#define MCF_INTC_IMRH_MASK44 (0x00001000) +#define MCF_INTC_IMRH_MASK45 (0x00002000) +#define MCF_INTC_IMRH_MASK46 (0x00004000) +#define MCF_INTC_IMRH_MASK47 (0x00008000) +#define MCF_INTC_IMRH_MASK48 (0x00010000) +#define MCF_INTC_IMRH_MASK49 (0x00020000) +#define MCF_INTC_IMRH_MASK50 (0x00040000) +#define MCF_INTC_IMRH_MASK51 (0x00080000) +#define MCF_INTC_IMRH_MASK52 (0x00100000) +#define MCF_INTC_IMRH_MASK53 (0x00200000) +#define MCF_INTC_IMRH_MASK54 (0x00400000) +#define MCF_INTC_IMRH_MASK55 (0x00800000) +#define MCF_INTC_IMRH_MASK56 (0x01000000) +#define MCF_INTC_IMRH_MASK57 (0x02000000) +#define MCF_INTC_IMRH_MASK58 (0x04000000) +#define MCF_INTC_IMRH_MASK59 (0x08000000) +#define MCF_INTC_IMRH_MASK60 (0x10000000) +#define MCF_INTC_IMRH_MASK61 (0x20000000) +#define MCF_INTC_IMRH_MASK62 (0x40000000) +#define MCF_INTC_IMRH_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x00000001) +#define MCF_INTC_IMRL_MASK1 (0x00000002) +#define MCF_INTC_IMRL_MASK2 (0x00000004) +#define MCF_INTC_IMRL_MASK3 (0x00000008) +#define MCF_INTC_IMRL_MASK4 (0x00000010) +#define MCF_INTC_IMRL_MASK5 (0x00000020) +#define MCF_INTC_IMRL_MASK6 (0x00000040) +#define MCF_INTC_IMRL_MASK7 (0x00000080) +#define MCF_INTC_IMRL_MASK8 (0x00000100) +#define MCF_INTC_IMRL_MASK9 (0x00000200) +#define MCF_INTC_IMRL_MASK10 (0x00000400) +#define MCF_INTC_IMRL_MASK11 (0x00000800) +#define MCF_INTC_IMRL_MASK12 (0x00001000) +#define MCF_INTC_IMRL_MASK13 (0x00002000) +#define MCF_INTC_IMRL_MASK14 (0x00004000) +#define MCF_INTC_IMRL_MASK15 (0x00008000) +#define MCF_INTC_IMRL_MASK16 (0x00010000) +#define MCF_INTC_IMRL_MASK17 (0x00020000) +#define MCF_INTC_IMRL_MASK18 (0x00040000) +#define MCF_INTC_IMRL_MASK19 (0x00080000) +#define MCF_INTC_IMRL_MASK20 (0x00100000) +#define MCF_INTC_IMRL_MASK21 (0x00200000) +#define MCF_INTC_IMRL_MASK22 (0x00400000) +#define MCF_INTC_IMRL_MASK23 (0x00800000) +#define MCF_INTC_IMRL_MASK24 (0x01000000) +#define MCF_INTC_IMRL_MASK25 (0x02000000) +#define MCF_INTC_IMRL_MASK26 (0x04000000) +#define MCF_INTC_IMRL_MASK27 (0x08000000) +#define MCF_INTC_IMRL_MASK28 (0x10000000) +#define MCF_INTC_IMRL_MASK29 (0x20000000) +#define MCF_INTC_IMRL_MASK30 (0x40000000) +#define MCF_INTC_IMRL_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) +#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) +#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) +#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) +#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) +#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) +#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) +#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) +#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) +#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) +#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) +#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) +#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) +#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) +#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) +#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x07)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PORTNQ (*(vuint8 *)(&__IPSBAR[0x100008])) +#define MCF_GPIO_PORTAN (*(vuint8 *)(&__IPSBAR[0x10000A])) +#define MCF_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000B])) +#define MCF_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000C])) +#define MCF_GPIO_PORTTA (*(vuint8 *)(&__IPSBAR[0x10000E])) +#define MCF_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F])) +#define MCF_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010])) +#define MCF_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011])) +#define MCF_GPIO_PORTUB (*(vuint8 *)(&__IPSBAR[0x100012])) +#define MCF_GPIO_PORTUC (*(vuint8 *)(&__IPSBAR[0x100013])) +#define MCF_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100014])) +#define MCF_GPIO_PORTLD (*(vuint8 *)(&__IPSBAR[0x100015])) +#define MCF_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x100016])) +#define MCF_GPIO_DDRNQ (*(vuint8 *)(&__IPSBAR[0x100020])) +#define MCF_GPIO_DDRAN (*(vuint8 *)(&__IPSBAR[0x100022])) +#define MCF_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100023])) +#define MCF_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100024])) +#define MCF_GPIO_DDRTA (*(vuint8 *)(&__IPSBAR[0x100026])) +#define MCF_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100027])) +#define MCF_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100028])) +#define MCF_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100029])) +#define MCF_GPIO_DDRUB (*(vuint8 *)(&__IPSBAR[0x10002A])) +#define MCF_GPIO_DDRUC (*(vuint8 *)(&__IPSBAR[0x10002B])) +#define MCF_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10002C])) +#define MCF_GPIO_DDRLD (*(vuint8 *)(&__IPSBAR[0x10002D])) +#define MCF_GPIO_DDRGP (*(vuint8 *)(&__IPSBAR[0x10002E])) +#define MCF_GPIO_SETNQ (*(vuint8 *)(&__IPSBAR[0x100038])) +#define MCF_GPIO_SETAN (*(vuint8 *)(&__IPSBAR[0x10003A])) +#define MCF_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x10003B])) +#define MCF_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x10003C])) +#define MCF_GPIO_SETTA (*(vuint8 *)(&__IPSBAR[0x10003E])) +#define MCF_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x10003F])) +#define MCF_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100040])) +#define MCF_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100041])) +#define MCF_GPIO_SETUB (*(vuint8 *)(&__IPSBAR[0x100042])) +#define MCF_GPIO_SETUC (*(vuint8 *)(&__IPSBAR[0x100043])) +#define MCF_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100044])) +#define MCF_GPIO_SETLD (*(vuint8 *)(&__IPSBAR[0x100045])) +#define MCF_GPIO_SETGP (*(vuint8 *)(&__IPSBAR[0x100046])) +#define MCF_GPIO_CLRNQ (*(vuint8 *)(&__IPSBAR[0x100050])) +#define MCF_GPIO_CLRAN (*(vuint8 *)(&__IPSBAR[0x100052])) +#define MCF_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100053])) +#define MCF_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100054])) +#define MCF_GPIO_CLRTA (*(vuint8 *)(&__IPSBAR[0x100056])) +#define MCF_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x100057])) +#define MCF_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x100058])) +#define MCF_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x100059])) +#define MCF_GPIO_CLRUB (*(vuint8 *)(&__IPSBAR[0x10005A])) +#define MCF_GPIO_CLRUC (*(vuint8 *)(&__IPSBAR[0x10005B])) +#define MCF_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x10005C])) +#define MCF_GPIO_CLRLD (*(vuint8 *)(&__IPSBAR[0x10005D])) +#define MCF_GPIO_CLRGP (*(vuint8 *)(&__IPSBAR[0x10005E])) +#define MCF_GPIO_PNQPAR (*(vuint16*)(&__IPSBAR[0x100068])) +#define MCF_GPIO_PANPAR (*(vuint8 *)(&__IPSBAR[0x10006A])) +#define MCF_GPIO_PASPAR (*(vuint8 *)(&__IPSBAR[0x10006B])) +#define MCF_GPIO_PQSPAR (*(vuint16*)(&__IPSBAR[0x10006C])) +#define MCF_GPIO_PTAPAR (*(vuint8 *)(&__IPSBAR[0x10006E])) +#define MCF_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10006F])) +#define MCF_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x100070])) +#define MCF_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x100071])) +#define MCF_GPIO_PUBPAR (*(vuint8 *)(&__IPSBAR[0x100072])) +#define MCF_GPIO_PUCPAR (*(vuint8 *)(&__IPSBAR[0x100073])) +#define MCF_GPIO_PDDPAR (*(vuint8 *)(&__IPSBAR[0x100074])) +#define MCF_GPIO_PLDPAR (*(vuint8 *)(&__IPSBAR[0x100075])) +#define MCF_GPIO_PGPPAR (*(vuint8 *)(&__IPSBAR[0x100076])) +#define MCF_GPIO_PWOR (*(vuint16*)(&__IPSBAR[0x100078])) +#define MCF_GPIO_PDSRH (*(vuint16*)(&__IPSBAR[0x10007A])) +#define MCF_GPIO_PDSRL (*(vuint32*)(&__IPSBAR[0x10007C])) + +/* Bit definitions and macros for MCF_GPIO_PORTNQ */ +#define MCF_GPIO_PORTNQ_PORTNQ0 (0x01) +#define MCF_GPIO_PORTNQ_PORTNQ1 (0x02) +#define MCF_GPIO_PORTNQ_PORTNQ2 (0x04) +#define MCF_GPIO_PORTNQ_PORTNQ3 (0x08) +#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10) +#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20) +#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40) +#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTAN */ +#define MCF_GPIO_PORTAN_PORTAN0 (0x01) +#define MCF_GPIO_PORTAN_PORTAN1 (0x02) +#define MCF_GPIO_PORTAN_PORTAN2 (0x04) +#define MCF_GPIO_PORTAN_PORTAN3 (0x08) +#define MCF_GPIO_PORTAN_PORTAN4 (0x10) +#define MCF_GPIO_PORTAN_PORTAN5 (0x20) +#define MCF_GPIO_PORTAN_PORTAN6 (0x40) +#define MCF_GPIO_PORTAN_PORTAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTAS */ +#define MCF_GPIO_PORTAS_PORTAS0 (0x01) +#define MCF_GPIO_PORTAS_PORTAS1 (0x02) +#define MCF_GPIO_PORTAS_PORTAS2 (0x04) +#define MCF_GPIO_PORTAS_PORTAS3 (0x08) +#define MCF_GPIO_PORTAS_PORTAS4 (0x10) +#define MCF_GPIO_PORTAS_PORTAS5 (0x20) +#define MCF_GPIO_PORTAS_PORTAS6 (0x40) +#define MCF_GPIO_PORTAS_PORTAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTQS */ +#define MCF_GPIO_PORTQS_PORTQS0 (0x01) +#define MCF_GPIO_PORTQS_PORTQS1 (0x02) +#define MCF_GPIO_PORTQS_PORTQS2 (0x04) +#define MCF_GPIO_PORTQS_PORTQS3 (0x08) +#define MCF_GPIO_PORTQS_PORTQS4 (0x10) +#define MCF_GPIO_PORTQS_PORTQS5 (0x20) +#define MCF_GPIO_PORTQS_PORTQS6 (0x40) +#define MCF_GPIO_PORTQS_PORTQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTA */ +#define MCF_GPIO_PORTTA_PORTTA0 (0x01) +#define MCF_GPIO_PORTTA_PORTTA1 (0x02) +#define MCF_GPIO_PORTTA_PORTTA2 (0x04) +#define MCF_GPIO_PORTTA_PORTTA3 (0x08) +#define MCF_GPIO_PORTTA_PORTTA4 (0x10) +#define MCF_GPIO_PORTTA_PORTTA5 (0x20) +#define MCF_GPIO_PORTTA_PORTTA6 (0x40) +#define MCF_GPIO_PORTTA_PORTTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTC */ +#define MCF_GPIO_PORTTC_PORTTC0 (0x01) +#define MCF_GPIO_PORTTC_PORTTC1 (0x02) +#define MCF_GPIO_PORTTC_PORTTC2 (0x04) +#define MCF_GPIO_PORTTC_PORTTC3 (0x08) +#define MCF_GPIO_PORTTC_PORTTC4 (0x10) +#define MCF_GPIO_PORTTC_PORTTC5 (0x20) +#define MCF_GPIO_PORTTC_PORTTC6 (0x40) +#define MCF_GPIO_PORTTC_PORTTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTD */ +#define MCF_GPIO_PORTTD_PORTTD0 (0x01) +#define MCF_GPIO_PORTTD_PORTTD1 (0x02) +#define MCF_GPIO_PORTTD_PORTTD2 (0x04) +#define MCF_GPIO_PORTTD_PORTTD3 (0x08) +#define MCF_GPIO_PORTTD_PORTTD4 (0x10) +#define MCF_GPIO_PORTTD_PORTTD5 (0x20) +#define MCF_GPIO_PORTTD_PORTTD6 (0x40) +#define MCF_GPIO_PORTTD_PORTTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTUA */ +#define MCF_GPIO_PORTUA_PORTUA0 (0x01) +#define MCF_GPIO_PORTUA_PORTUA1 (0x02) +#define MCF_GPIO_PORTUA_PORTUA2 (0x04) +#define MCF_GPIO_PORTUA_PORTUA3 (0x08) +#define MCF_GPIO_PORTUA_PORTUA4 (0x10) +#define MCF_GPIO_PORTUA_PORTUA5 (0x20) +#define MCF_GPIO_PORTUA_PORTUA6 (0x40) +#define MCF_GPIO_PORTUA_PORTUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTUB */ +#define MCF_GPIO_PORTUB_PORTUB0 (0x01) +#define MCF_GPIO_PORTUB_PORTUB1 (0x02) +#define MCF_GPIO_PORTUB_PORTUB2 (0x04) +#define MCF_GPIO_PORTUB_PORTUB3 (0x08) +#define MCF_GPIO_PORTUB_PORTUB4 (0x10) +#define MCF_GPIO_PORTUB_PORTUB5 (0x20) +#define MCF_GPIO_PORTUB_PORTUB6 (0x40) +#define MCF_GPIO_PORTUB_PORTUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTUC */ +#define MCF_GPIO_PORTUC_PORTUC0 (0x01) +#define MCF_GPIO_PORTUC_PORTUC1 (0x02) +#define MCF_GPIO_PORTUC_PORTUC2 (0x04) +#define MCF_GPIO_PORTUC_PORTUC3 (0x08) +#define MCF_GPIO_PORTUC_PORTUC4 (0x10) +#define MCF_GPIO_PORTUC_PORTUC5 (0x20) +#define MCF_GPIO_PORTUC_PORTUC6 (0x40) +#define MCF_GPIO_PORTUC_PORTUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTDD */ +#define MCF_GPIO_PORTDD_PORTDD0 (0x01) +#define MCF_GPIO_PORTDD_PORTDD1 (0x02) +#define MCF_GPIO_PORTDD_PORTDD2 (0x04) +#define MCF_GPIO_PORTDD_PORTDD3 (0x08) +#define MCF_GPIO_PORTDD_PORTDD4 (0x10) +#define MCF_GPIO_PORTDD_PORTDD5 (0x20) +#define MCF_GPIO_PORTDD_PORTDD6 (0x40) +#define MCF_GPIO_PORTDD_PORTDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTLD */ +#define MCF_GPIO_PORTLD_PORTLD0 (0x01) +#define MCF_GPIO_PORTLD_PORTLD1 (0x02) +#define MCF_GPIO_PORTLD_PORTLD2 (0x04) +#define MCF_GPIO_PORTLD_PORTLD3 (0x08) +#define MCF_GPIO_PORTLD_PORTLD4 (0x10) +#define MCF_GPIO_PORTLD_PORTLD5 (0x20) +#define MCF_GPIO_PORTLD_PORTLD6 (0x40) +#define MCF_GPIO_PORTLD_PORTLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTGP */ +#define MCF_GPIO_PORTGP_PORTGP0 (0x01) +#define MCF_GPIO_PORTGP_PORTGP1 (0x02) +#define MCF_GPIO_PORTGP_PORTGP2 (0x04) +#define MCF_GPIO_PORTGP_PORTGP3 (0x08) +#define MCF_GPIO_PORTGP_PORTGP4 (0x10) +#define MCF_GPIO_PORTGP_PORTGP5 (0x20) +#define MCF_GPIO_PORTGP_PORTGP6 (0x40) +#define MCF_GPIO_PORTGP_PORTGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRNQ */ +#define MCF_GPIO_DDRNQ_DDRNQ0 (0x01) +#define MCF_GPIO_DDRNQ_DDRNQ1 (0x02) +#define MCF_GPIO_DDRNQ_DDRNQ2 (0x04) +#define MCF_GPIO_DDRNQ_DDRNQ3 (0x08) +#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10) +#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20) +#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40) +#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRAN */ +#define MCF_GPIO_DDRAN_DDRAN0 (0x01) +#define MCF_GPIO_DDRAN_DDRAN1 (0x02) +#define MCF_GPIO_DDRAN_DDRAN2 (0x04) +#define MCF_GPIO_DDRAN_DDRAN3 (0x08) +#define MCF_GPIO_DDRAN_DDRAN4 (0x10) +#define MCF_GPIO_DDRAN_DDRAN5 (0x20) +#define MCF_GPIO_DDRAN_DDRAN6 (0x40) +#define MCF_GPIO_DDRAN_DDRAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRAS */ +#define MCF_GPIO_DDRAS_DDRAS0 (0x01) +#define MCF_GPIO_DDRAS_DDRAS1 (0x02) +#define MCF_GPIO_DDRAS_DDRAS2 (0x04) +#define MCF_GPIO_DDRAS_DDRAS3 (0x08) +#define MCF_GPIO_DDRAS_DDRAS4 (0x10) +#define MCF_GPIO_DDRAS_DDRAS5 (0x20) +#define MCF_GPIO_DDRAS_DDRAS6 (0x40) +#define MCF_GPIO_DDRAS_DDRAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRQS */ +#define MCF_GPIO_DDRQS_DDRQS0 (0x01) +#define MCF_GPIO_DDRQS_DDRQS1 (0x02) +#define MCF_GPIO_DDRQS_DDRQS2 (0x04) +#define MCF_GPIO_DDRQS_DDRQS3 (0x08) +#define MCF_GPIO_DDRQS_DDRQS4 (0x10) +#define MCF_GPIO_DDRQS_DDRQS5 (0x20) +#define MCF_GPIO_DDRQS_DDRQS6 (0x40) +#define MCF_GPIO_DDRQS_DDRQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTA */ +#define MCF_GPIO_DDRTA_DDRTA0 (0x01) +#define MCF_GPIO_DDRTA_DDRTA1 (0x02) +#define MCF_GPIO_DDRTA_DDRTA2 (0x04) +#define MCF_GPIO_DDRTA_DDRTA3 (0x08) +#define MCF_GPIO_DDRTA_DDRTA4 (0x10) +#define MCF_GPIO_DDRTA_DDRTA5 (0x20) +#define MCF_GPIO_DDRTA_DDRTA6 (0x40) +#define MCF_GPIO_DDRTA_DDRTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTC */ +#define MCF_GPIO_DDRTC_DDRTC0 (0x01) +#define MCF_GPIO_DDRTC_DDRTC1 (0x02) +#define MCF_GPIO_DDRTC_DDRTC2 (0x04) +#define MCF_GPIO_DDRTC_DDRTC3 (0x08) +#define MCF_GPIO_DDRTC_DDRTC4 (0x10) +#define MCF_GPIO_DDRTC_DDRTC5 (0x20) +#define MCF_GPIO_DDRTC_DDRTC6 (0x40) +#define MCF_GPIO_DDRTC_DDRTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTD */ +#define MCF_GPIO_DDRTD_DDRTD0 (0x01) +#define MCF_GPIO_DDRTD_DDRTD1 (0x02) +#define MCF_GPIO_DDRTD_DDRTD2 (0x04) +#define MCF_GPIO_DDRTD_DDRTD3 (0x08) +#define MCF_GPIO_DDRTD_DDRTD4 (0x10) +#define MCF_GPIO_DDRTD_DDRTD5 (0x20) +#define MCF_GPIO_DDRTD_DDRTD6 (0x40) +#define MCF_GPIO_DDRTD_DDRTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRUA */ +#define MCF_GPIO_DDRUA_DDRUA0 (0x01) +#define MCF_GPIO_DDRUA_DDRUA1 (0x02) +#define MCF_GPIO_DDRUA_DDRUA2 (0x04) +#define MCF_GPIO_DDRUA_DDRUA3 (0x08) +#define MCF_GPIO_DDRUA_DDRUA4 (0x10) +#define MCF_GPIO_DDRUA_DDRUA5 (0x20) +#define MCF_GPIO_DDRUA_DDRUA6 (0x40) +#define MCF_GPIO_DDRUA_DDRUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRUB */ +#define MCF_GPIO_DDRUB_DDRUB0 (0x01) +#define MCF_GPIO_DDRUB_DDRUB1 (0x02) +#define MCF_GPIO_DDRUB_DDRUB2 (0x04) +#define MCF_GPIO_DDRUB_DDRUB3 (0x08) +#define MCF_GPIO_DDRUB_DDRUB4 (0x10) +#define MCF_GPIO_DDRUB_DDRUB5 (0x20) +#define MCF_GPIO_DDRUB_DDRUB6 (0x40) +#define MCF_GPIO_DDRUB_DDRUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRUC */ +#define MCF_GPIO_DDRUC_DDRUC0 (0x01) +#define MCF_GPIO_DDRUC_DDRUC1 (0x02) +#define MCF_GPIO_DDRUC_DDRUC2 (0x04) +#define MCF_GPIO_DDRUC_DDRUC3 (0x08) +#define MCF_GPIO_DDRUC_DDRUC4 (0x10) +#define MCF_GPIO_DDRUC_DDRUC5 (0x20) +#define MCF_GPIO_DDRUC_DDRUC6 (0x40) +#define MCF_GPIO_DDRUC_DDRUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRDD */ +#define MCF_GPIO_DDRDD_DDRDD0 (0x01) +#define MCF_GPIO_DDRDD_DDRDD1 (0x02) +#define MCF_GPIO_DDRDD_DDRDD2 (0x04) +#define MCF_GPIO_DDRDD_DDRDD3 (0x08) +#define MCF_GPIO_DDRDD_DDRDD4 (0x10) +#define MCF_GPIO_DDRDD_DDRDD5 (0x20) +#define MCF_GPIO_DDRDD_DDRDD6 (0x40) +#define MCF_GPIO_DDRDD_DDRDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRLD */ +#define MCF_GPIO_DDRLD_DDRLD0 (0x01) +#define MCF_GPIO_DDRLD_DDRLD1 (0x02) +#define MCF_GPIO_DDRLD_DDRLD2 (0x04) +#define MCF_GPIO_DDRLD_DDRLD3 (0x08) +#define MCF_GPIO_DDRLD_DDRLD4 (0x10) +#define MCF_GPIO_DDRLD_DDRLD5 (0x20) +#define MCF_GPIO_DDRLD_DDRLD6 (0x40) +#define MCF_GPIO_DDRLD_DDRLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRGP */ +#define MCF_GPIO_DDRGP_DDRGP0 (0x01) +#define MCF_GPIO_DDRGP_DDRGP1 (0x02) +#define MCF_GPIO_DDRGP_DDRGP2 (0x04) +#define MCF_GPIO_DDRGP_DDRGP3 (0x08) +#define MCF_GPIO_DDRGP_DDRGP4 (0x10) +#define MCF_GPIO_DDRGP_DDRGP5 (0x20) +#define MCF_GPIO_DDRGP_DDRGP6 (0x40) +#define MCF_GPIO_DDRGP_DDRGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETNQ */ +#define MCF_GPIO_SETNQ_SETNQ0 (0x01) +#define MCF_GPIO_SETNQ_SETNQ1 (0x02) +#define MCF_GPIO_SETNQ_SETNQ2 (0x04) +#define MCF_GPIO_SETNQ_SETNQ3 (0x08) +#define MCF_GPIO_SETNQ_SETNQ4 (0x10) +#define MCF_GPIO_SETNQ_SETNQ5 (0x20) +#define MCF_GPIO_SETNQ_SETNQ6 (0x40) +#define MCF_GPIO_SETNQ_SETNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETAN */ +#define MCF_GPIO_SETAN_SETAN0 (0x01) +#define MCF_GPIO_SETAN_SETAN1 (0x02) +#define MCF_GPIO_SETAN_SETAN2 (0x04) +#define MCF_GPIO_SETAN_SETAN3 (0x08) +#define MCF_GPIO_SETAN_SETAN4 (0x10) +#define MCF_GPIO_SETAN_SETAN5 (0x20) +#define MCF_GPIO_SETAN_SETAN6 (0x40) +#define MCF_GPIO_SETAN_SETAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETAS */ +#define MCF_GPIO_SETAS_SETAS0 (0x01) +#define MCF_GPIO_SETAS_SETAS1 (0x02) +#define MCF_GPIO_SETAS_SETAS2 (0x04) +#define MCF_GPIO_SETAS_SETAS3 (0x08) +#define MCF_GPIO_SETAS_SETAS4 (0x10) +#define MCF_GPIO_SETAS_SETAS5 (0x20) +#define MCF_GPIO_SETAS_SETAS6 (0x40) +#define MCF_GPIO_SETAS_SETAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETQS */ +#define MCF_GPIO_SETQS_SETQS0 (0x01) +#define MCF_GPIO_SETQS_SETQS1 (0x02) +#define MCF_GPIO_SETQS_SETQS2 (0x04) +#define MCF_GPIO_SETQS_SETQS3 (0x08) +#define MCF_GPIO_SETQS_SETQS4 (0x10) +#define MCF_GPIO_SETQS_SETQS5 (0x20) +#define MCF_GPIO_SETQS_SETQS6 (0x40) +#define MCF_GPIO_SETQS_SETQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETTA */ +#define MCF_GPIO_SETTA_SETTA0 (0x01) +#define MCF_GPIO_SETTA_SETTA1 (0x02) +#define MCF_GPIO_SETTA_SETTA2 (0x04) +#define MCF_GPIO_SETTA_SETTA3 (0x08) +#define MCF_GPIO_SETTA_SETTA4 (0x10) +#define MCF_GPIO_SETTA_SETTA5 (0x20) +#define MCF_GPIO_SETTA_SETTA6 (0x40) +#define MCF_GPIO_SETTA_SETTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETTC */ +#define MCF_GPIO_SETTC_SETTC0 (0x01) +#define MCF_GPIO_SETTC_SETTC1 (0x02) +#define MCF_GPIO_SETTC_SETTC2 (0x04) +#define MCF_GPIO_SETTC_SETTC3 (0x08) +#define MCF_GPIO_SETTC_SETTC4 (0x10) +#define MCF_GPIO_SETTC_SETTC5 (0x20) +#define MCF_GPIO_SETTC_SETTC6 (0x40) +#define MCF_GPIO_SETTC_SETTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETTD */ +#define MCF_GPIO_SETTD_SETTD0 (0x01) +#define MCF_GPIO_SETTD_SETTD1 (0x02) +#define MCF_GPIO_SETTD_SETTD2 (0x04) +#define MCF_GPIO_SETTD_SETTD3 (0x08) +#define MCF_GPIO_SETTD_SETTD4 (0x10) +#define MCF_GPIO_SETTD_SETTD5 (0x20) +#define MCF_GPIO_SETTD_SETTD6 (0x40) +#define MCF_GPIO_SETTD_SETTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETUA */ +#define MCF_GPIO_SETUA_SETUA0 (0x01) +#define MCF_GPIO_SETUA_SETUA1 (0x02) +#define MCF_GPIO_SETUA_SETUA2 (0x04) +#define MCF_GPIO_SETUA_SETUA3 (0x08) +#define MCF_GPIO_SETUA_SETUA4 (0x10) +#define MCF_GPIO_SETUA_SETUA5 (0x20) +#define MCF_GPIO_SETUA_SETUA6 (0x40) +#define MCF_GPIO_SETUA_SETUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETUB */ +#define MCF_GPIO_SETUB_SETUB0 (0x01) +#define MCF_GPIO_SETUB_SETUB1 (0x02) +#define MCF_GPIO_SETUB_SETUB2 (0x04) +#define MCF_GPIO_SETUB_SETUB3 (0x08) +#define MCF_GPIO_SETUB_SETUB4 (0x10) +#define MCF_GPIO_SETUB_SETUB5 (0x20) +#define MCF_GPIO_SETUB_SETUB6 (0x40) +#define MCF_GPIO_SETUB_SETUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETUC */ +#define MCF_GPIO_SETUC_SETUC0 (0x01) +#define MCF_GPIO_SETUC_SETUC1 (0x02) +#define MCF_GPIO_SETUC_SETUC2 (0x04) +#define MCF_GPIO_SETUC_SETUC3 (0x08) +#define MCF_GPIO_SETUC_SETUC4 (0x10) +#define MCF_GPIO_SETUC_SETUC5 (0x20) +#define MCF_GPIO_SETUC_SETUC6 (0x40) +#define MCF_GPIO_SETUC_SETUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETDD */ +#define MCF_GPIO_SETDD_SETDD0 (0x01) +#define MCF_GPIO_SETDD_SETDD1 (0x02) +#define MCF_GPIO_SETDD_SETDD2 (0x04) +#define MCF_GPIO_SETDD_SETDD3 (0x08) +#define MCF_GPIO_SETDD_SETDD4 (0x10) +#define MCF_GPIO_SETDD_SETDD5 (0x20) +#define MCF_GPIO_SETDD_SETDD6 (0x40) +#define MCF_GPIO_SETDD_SETDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETLD */ +#define MCF_GPIO_SETLD_SETLD0 (0x01) +#define MCF_GPIO_SETLD_SETLD1 (0x02) +#define MCF_GPIO_SETLD_SETLD2 (0x04) +#define MCF_GPIO_SETLD_SETLD3 (0x08) +#define MCF_GPIO_SETLD_SETLD4 (0x10) +#define MCF_GPIO_SETLD_SETLD5 (0x20) +#define MCF_GPIO_SETLD_SETLD6 (0x40) +#define MCF_GPIO_SETLD_SETLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETGP */ +#define MCF_GPIO_SETGP_SETGP0 (0x01) +#define MCF_GPIO_SETGP_SETGP1 (0x02) +#define MCF_GPIO_SETGP_SETGP2 (0x04) +#define MCF_GPIO_SETGP_SETGP3 (0x08) +#define MCF_GPIO_SETGP_SETGP4 (0x10) +#define MCF_GPIO_SETGP_SETGP5 (0x20) +#define MCF_GPIO_SETGP_SETGP6 (0x40) +#define MCF_GPIO_SETGP_SETGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRNQ */ +#define MCF_GPIO_CLRNQ_CLRNQ0 (0x01) +#define MCF_GPIO_CLRNQ_CLRNQ1 (0x02) +#define MCF_GPIO_CLRNQ_CLRNQ2 (0x04) +#define MCF_GPIO_CLRNQ_CLRNQ3 (0x08) +#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10) +#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20) +#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40) +#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRAN */ +#define MCF_GPIO_CLRAN_CLRAN0 (0x01) +#define MCF_GPIO_CLRAN_CLRAN1 (0x02) +#define MCF_GPIO_CLRAN_CLRAN2 (0x04) +#define MCF_GPIO_CLRAN_CLRAN3 (0x08) +#define MCF_GPIO_CLRAN_CLRAN4 (0x10) +#define MCF_GPIO_CLRAN_CLRAN5 (0x20) +#define MCF_GPIO_CLRAN_CLRAN6 (0x40) +#define MCF_GPIO_CLRAN_CLRAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRAS */ +#define MCF_GPIO_CLRAS_CLRAS0 (0x01) +#define MCF_GPIO_CLRAS_CLRAS1 (0x02) +#define MCF_GPIO_CLRAS_CLRAS2 (0x04) +#define MCF_GPIO_CLRAS_CLRAS3 (0x08) +#define MCF_GPIO_CLRAS_CLRAS4 (0x10) +#define MCF_GPIO_CLRAS_CLRAS5 (0x20) +#define MCF_GPIO_CLRAS_CLRAS6 (0x40) +#define MCF_GPIO_CLRAS_CLRAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRQS */ +#define MCF_GPIO_CLRQS_CLRQS0 (0x01) +#define MCF_GPIO_CLRQS_CLRQS1 (0x02) +#define MCF_GPIO_CLRQS_CLRQS2 (0x04) +#define MCF_GPIO_CLRQS_CLRQS3 (0x08) +#define MCF_GPIO_CLRQS_CLRQS4 (0x10) +#define MCF_GPIO_CLRQS_CLRQS5 (0x20) +#define MCF_GPIO_CLRQS_CLRQS6 (0x40) +#define MCF_GPIO_CLRQS_CLRQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRTA */ +#define MCF_GPIO_CLRTA_CLRTA0 (0x01) +#define MCF_GPIO_CLRTA_CLRTA1 (0x02) +#define MCF_GPIO_CLRTA_CLRTA2 (0x04) +#define MCF_GPIO_CLRTA_CLRTA3 (0x08) +#define MCF_GPIO_CLRTA_CLRTA4 (0x10) +#define MCF_GPIO_CLRTA_CLRTA5 (0x20) +#define MCF_GPIO_CLRTA_CLRTA6 (0x40) +#define MCF_GPIO_CLRTA_CLRTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRTC */ +#define MCF_GPIO_CLRTC_CLRTC0 (0x01) +#define MCF_GPIO_CLRTC_CLRTC1 (0x02) +#define MCF_GPIO_CLRTC_CLRTC2 (0x04) +#define MCF_GPIO_CLRTC_CLRTC3 (0x08) +#define MCF_GPIO_CLRTC_CLRTC4 (0x10) +#define MCF_GPIO_CLRTC_CLRTC5 (0x20) +#define MCF_GPIO_CLRTC_CLRTC6 (0x40) +#define MCF_GPIO_CLRTC_CLRTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRTD */ +#define MCF_GPIO_CLRTD_CLRTD0 (0x01) +#define MCF_GPIO_CLRTD_CLRTD1 (0x02) +#define MCF_GPIO_CLRTD_CLRTD2 (0x04) +#define MCF_GPIO_CLRTD_CLRTD3 (0x08) +#define MCF_GPIO_CLRTD_CLRTD4 (0x10) +#define MCF_GPIO_CLRTD_CLRTD5 (0x20) +#define MCF_GPIO_CLRTD_CLRTD6 (0x40) +#define MCF_GPIO_CLRTD_CLRTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRUA */ +#define MCF_GPIO_CLRUA_CLRUA0 (0x01) +#define MCF_GPIO_CLRUA_CLRUA1 (0x02) +#define MCF_GPIO_CLRUA_CLRUA2 (0x04) +#define MCF_GPIO_CLRUA_CLRUA3 (0x08) +#define MCF_GPIO_CLRUA_CLRUA4 (0x10) +#define MCF_GPIO_CLRUA_CLRUA5 (0x20) +#define MCF_GPIO_CLRUA_CLRUA6 (0x40) +#define MCF_GPIO_CLRUA_CLRUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRUB */ +#define MCF_GPIO_CLRUB_CLRUB0 (0x01) +#define MCF_GPIO_CLRUB_CLRUB1 (0x02) +#define MCF_GPIO_CLRUB_CLRUB2 (0x04) +#define MCF_GPIO_CLRUB_CLRUB3 (0x08) +#define MCF_GPIO_CLRUB_CLRUB4 (0x10) +#define MCF_GPIO_CLRUB_CLRUB5 (0x20) +#define MCF_GPIO_CLRUB_CLRUB6 (0x40) +#define MCF_GPIO_CLRUB_CLRUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRUC */ +#define MCF_GPIO_CLRUC_CLRUC0 (0x01) +#define MCF_GPIO_CLRUC_CLRUC1 (0x02) +#define MCF_GPIO_CLRUC_CLRUC2 (0x04) +#define MCF_GPIO_CLRUC_CLRUC3 (0x08) +#define MCF_GPIO_CLRUC_CLRUC4 (0x10) +#define MCF_GPIO_CLRUC_CLRUC5 (0x20) +#define MCF_GPIO_CLRUC_CLRUC6 (0x40) +#define MCF_GPIO_CLRUC_CLRUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRDD */ +#define MCF_GPIO_CLRDD_CLRDD0 (0x01) +#define MCF_GPIO_CLRDD_CLRDD1 (0x02) +#define MCF_GPIO_CLRDD_CLRDD2 (0x04) +#define MCF_GPIO_CLRDD_CLRDD3 (0x08) +#define MCF_GPIO_CLRDD_CLRDD4 (0x10) +#define MCF_GPIO_CLRDD_CLRDD5 (0x20) +#define MCF_GPIO_CLRDD_CLRDD6 (0x40) +#define MCF_GPIO_CLRDD_CLRDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRLD */ +#define MCF_GPIO_CLRLD_CLRLD0 (0x01) +#define MCF_GPIO_CLRLD_CLRLD1 (0x02) +#define MCF_GPIO_CLRLD_CLRLD2 (0x04) +#define MCF_GPIO_CLRLD_CLRLD3 (0x08) +#define MCF_GPIO_CLRLD_CLRLD4 (0x10) +#define MCF_GPIO_CLRLD_CLRLD5 (0x20) +#define MCF_GPIO_CLRLD_CLRLD6 (0x40) +#define MCF_GPIO_CLRLD_CLRLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRGP */ +#define MCF_GPIO_CLRGP_CLRGP0 (0x01) +#define MCF_GPIO_CLRGP_CLRGP1 (0x02) +#define MCF_GPIO_CLRGP_CLRGP2 (0x04) +#define MCF_GPIO_CLRGP_CLRGP3 (0x08) +#define MCF_GPIO_CLRGP_CLRGP4 (0x10) +#define MCF_GPIO_CLRGP_CLRGP5 (0x20) +#define MCF_GPIO_CLRGP_CLRGP6 (0x40) +#define MCF_GPIO_CLRGP_CLRGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PNQPAR */ +#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PNQPAR_PNQPAR2(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PNQPAR_PNQPAR4(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PNQPAR_PNQPAR6(x) (((x)&0x0003)<<12) +#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x0003)<<14) +#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x0004) +#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x0010) +#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x0040) +#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x0100) +#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x0400) +#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000) +#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000) +#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x0008) +#define MCF_GPIO_PNQPAR_IRQ1_PWM1 (0x000C) + +/* Bit definitions and macros for MCF_GPIO_PANPAR */ +#define MCF_GPIO_PANPAR_PANPAR0 (0x01) +#define MCF_GPIO_PANPAR_PANPAR1 (0x02) +#define MCF_GPIO_PANPAR_PANPAR2 (0x04) +#define MCF_GPIO_PANPAR_PANPAR3 (0x08) +#define MCF_GPIO_PANPAR_PANPAR4 (0x10) +#define MCF_GPIO_PANPAR_PANPAR5 (0x20) +#define MCF_GPIO_PANPAR_PANPAR6 (0x40) +#define MCF_GPIO_PANPAR_PANPAR7 (0x80) +#define MCF_GPIO_PANPAR_AN0_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN1_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN2_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN3_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN4_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN5_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN6_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN7_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN0_AN0 (0x01) +#define MCF_GPIO_PANPAR_AN1_AN1 (0x02) +#define MCF_GPIO_PANPAR_AN2_AN2 (0x04) +#define MCF_GPIO_PANPAR_AN3_AN3 (0x08) +#define MCF_GPIO_PANPAR_AN4_AN4 (0x10) +#define MCF_GPIO_PANPAR_AN5_AN5 (0x20) +#define MCF_GPIO_PANPAR_AN6_AN6 (0x40) +#define MCF_GPIO_PANPAR_AN7_AN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PASPAR */ +#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PASPAR_PASPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PASPAR_PASPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PASPAR_SCL_GPIO (0x00) +#define MCF_GPIO_PASPAR_SDA_GPIO (0x00) +#define MCF_GPIO_PASPAR_SYNCA_GPIO (0x00) +#define MCF_GPIO_PASPAR_SYNCB_GPIO (0x00) +#define MCF_GPIO_PASPAR_SCL_SCL (0x01) +#define MCF_GPIO_PASPAR_SDA_SDA (0x04) +#define MCF_GPIO_PASPAR_SYNCA_SYNCA (0x10) +#define MCF_GPIO_PASPAR_SYNCB_SYNCB (0x40) +#define MCF_GPIO_PASPAR_SCL_CANTX (0x02) +#define MCF_GPIO_PASPAR_SDA_CANRX (0x08) +#define MCF_GPIO_PASPAR_SYNCA_CANRX (0x20) +#define MCF_GPIO_PASPAR_SYNCB_CANTX (0x80) +#define MCF_GPIO_PASPAR_SCL_TXD2 (0x30) +#define MCF_GPIO_PASPAR_SDA_RXD2 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PQSPAR */ +#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x0003)<<0) +#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x0003)<<12) +#define MCF_GPIO_PQSPAR_DOUT_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_DIN_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_SCK_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS0_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS1_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS2_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS3_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_DOUT_DOUT (0x0001) +#define MCF_GPIO_PQSPAR_DIN_DIN (0x0004) +#define MCF_GPIO_PQSPAR_SCK_SCK (0x0010) +#define MCF_GPIO_PQSPAR_CS0_CS0 (0x0040) +#define MCF_GPIO_PQSPAR_CS1_CS1 (0x0100) +#define MCF_GPIO_PQSPAR_CS2_CS2 (0x0400) +#define MCF_GPIO_PQSPAR_CS3_CS3 (0x1000) +#define MCF_GPIO_PQSPAR_DOUT_CANTX (0x0002) +#define MCF_GPIO_PQSPAR_DIN_CANRX (0x0008) +#define MCF_GPIO_PQSPAR_SCK_SCL (0x0020) +#define MCF_GPIO_PQSPAR_CS0_SDA (0x0080) +#define MCF_GPIO_PQSPAR_CS3_SYNCA (0x2000) +#define MCF_GPIO_PQSPAR_DOUT_TXD1 (0x0003) +#define MCF_GPIO_PQSPAR_DIN_RXD1 (0x000C) +#define MCF_GPIO_PQSPAR_SCK_RTS1 (0x0030) +#define MCF_GPIO_PQSPAR_CS0_CTS1 (0x00C0) +#define MCF_GPIO_PQSPAR_CS3_SYNCB (0x3000) + +/* Bit definitions and macros for MCF_GPIO_PTAPAR */ +#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PTAPAR_ICOC0_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC1_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC2_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC3_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC0_ICOC0 (0x01) +#define MCF_GPIO_PTAPAR_ICOC1_ICOC1 (0x04) +#define MCF_GPIO_PTAPAR_ICOC2_ICOC2 (0x10) +#define MCF_GPIO_PTAPAR_ICOC3_ICOC3 (0x40) +#define MCF_GPIO_PTAPAR_ICOC0_PWM1 (0x02) +#define MCF_GPIO_PTAPAR_ICOC1_PWM3 (0x08) +#define MCF_GPIO_PTAPAR_ICOC2_PWM5 (0x20) +#define MCF_GPIO_PTAPAR_ICOC3_PWM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTCPAR */ +#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PTCPAR_TIN0_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN1_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN2_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN3_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN0_TIN0 (0x01) +#define MCF_GPIO_PTCPAR_TIN1_TIN1 (0x04) +#define MCF_GPIO_PTCPAR_TIN2_TIN2 (0x10) +#define MCF_GPIO_PTCPAR_TIN3_TIN3 (0x40) +#define MCF_GPIO_PTCPAR_TIN0_TOUT0 (0x02) +#define MCF_GPIO_PTCPAR_TIN1_TOUT1 (0x08) +#define MCF_GPIO_PTCPAR_TIN2_TOUT2 (0x20) +#define MCF_GPIO_PTCPAR_TIN3_TOUT3 (0x80) +#define MCF_GPIO_PTCPAR_TIN0_PWM0 (0x03) +#define MCF_GPIO_PTCPAR_TIN1_PWM2 (0x0C) +#define MCF_GPIO_PTCPAR_TIN2_PWM4 (0x30) +#define MCF_GPIO_PTCPAR_TIN3_PWM6 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PTDPAR */ +#define MCF_GPIO_PTDPAR_PTDPAR0 (0x01) +#define MCF_GPIO_PTDPAR_PTDPAR1 (0x02) +#define MCF_GPIO_PTDPAR_PTDPAR2 (0x04) +#define MCF_GPIO_PTDPAR_PTDPAR3 (0x08) +#define MCF_GPIO_PTDPAR_PWM1_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM3_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM5_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM7_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM1_PWM1 (0x01) +#define MCF_GPIO_PTDPAR_PWM3_PWM3 (0x02) +#define MCF_GPIO_PTDPAR_PWM5_PWM5 (0x04) +#define MCF_GPIO_PTDPAR_PWM7_PWM7 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PUAPAR */ +#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PUAPAR_TXD0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_RXD0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_RTS0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_CTS0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_TXD0_TXD0 (0x01) +#define MCF_GPIO_PUAPAR_RXD0_RXD0 (0x04) +#define MCF_GPIO_PUAPAR_RTS0_RTS0 (0x10) +#define MCF_GPIO_PUAPAR_CTS0_CTS0 (0x40) +#define MCF_GPIO_PUAPAR_RTS0_CANTX (0x20) +#define MCF_GPIO_PUAPAR_CTS0_CANRX (0x80) + +/* Bit definitions and macros for MCF_GPIO_PUBPAR */ +#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PUBPAR_TXD1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_RXD1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_RTS1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_CTS1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_TXD1_TXD1 (0x01) +#define MCF_GPIO_PUBPAR_RXD1_RXD1 (0x04) +#define MCF_GPIO_PUBPAR_RTS1_RTS1 (0x10) +#define MCF_GPIO_PUBPAR_CTS1_CTS1 (0x40) +#define MCF_GPIO_PUBPAR_RTS1_SYNCB (0x20) +#define MCF_GPIO_PUBPAR_CTS1_SYNCA (0x80) +#define MCF_GPIO_PUBPAR_RTS1_TXD2 (0x30) +#define MCF_GPIO_PUBPAR_CTS1_RXD2 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PUCPAR */ +#define MCF_GPIO_PUCPAR_PUCPAR0 (0x01) +#define MCF_GPIO_PUCPAR_PUCPAR1 (0x02) +#define MCF_GPIO_PUCPAR_PUCPAR2 (0x04) +#define MCF_GPIO_PUCPAR_PUCPAR3 (0x08) +#define MCF_GPIO_PUCPAR_TXD2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_RXD2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_RTS2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_CTS2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_TXD2_TXD2 (0x01) +#define MCF_GPIO_PUCPAR_RXD2_RXD2 (0x02) +#define MCF_GPIO_PUCPAR_RTS2_RTS2 (0x04) +#define MCF_GPIO_PUCPAR_CTS2_CTS2 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDPAR */ +#define MCF_GPIO_PDDPAR_PDDPAR0 (0x01) +#define MCF_GPIO_PDDPAR_PDDPAR1 (0x02) +#define MCF_GPIO_PDDPAR_PDDPAR2 (0x04) +#define MCF_GPIO_PDDPAR_PDDPAR3 (0x08) +#define MCF_GPIO_PDDPAR_PDDPAR4 (0x10) +#define MCF_GPIO_PDDPAR_PDDPAR5 (0x20) +#define MCF_GPIO_PDDPAR_PDDPAR6 (0x40) +#define MCF_GPIO_PDDPAR_PDDPAR7 (0x80) +#define MCF_GPIO_PDDPAR_PDD0_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD1_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD2_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD3_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD4_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD5_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD6_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD7_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD0_PST0 (0x01) +#define MCF_GPIO_PDDPAR_PDD1_PST1 (0x02) +#define MCF_GPIO_PDDPAR_PDD2_PST2 (0x04) +#define MCF_GPIO_PDDPAR_PDD3_PST3 (0x08) +#define MCF_GPIO_PDDPAR_PDD4_DDATA0 (0x10) +#define MCF_GPIO_PDDPAR_PDD5_DDATA1 (0x20) +#define MCF_GPIO_PDDPAR_PDD6_DDATA2 (0x40) +#define MCF_GPIO_PDDPAR_PDD7_DDATA3 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PLDPAR */ +#define MCF_GPIO_PLDPAR_PLDPAR0 (0x01) +#define MCF_GPIO_PLDPAR_PLDPAR1 (0x02) +#define MCF_GPIO_PLDPAR_PLDPAR2 (0x04) +#define MCF_GPIO_PLDPAR_PLDPAR3 (0x08) +#define MCF_GPIO_PLDPAR_PLDPAR4 (0x10) +#define MCF_GPIO_PLDPAR_PLDPAR5 (0x20) +#define MCF_GPIO_PLDPAR_PLDPAR6 (0x40) +#define MCF_GPIO_PLDPAR_ACTLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_LNKLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_SPDLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_DUPLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_COLLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_RXLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_TXLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_ACTLED_ACTLED (0x01) +#define MCF_GPIO_PLDPAR_LNKLED_LNKLED (0x02) +#define MCF_GPIO_PLDPAR_SPDLED_SPDLED (0x04) +#define MCF_GPIO_PLDPAR_DUPLED_DUPLED (0x08) +#define MCF_GPIO_PLDPAR_COLLED_COLLED (0x10) +#define MCF_GPIO_PLDPAR_RXLED_RXLED (0x20) +#define MCF_GPIO_PLDPAR_TXLED_TXLED (0x40) + +/* Bit definitions and macros for MCF_GPIO_PGPPAR */ +#define MCF_GPIO_PGPPAR_PGPPAR0 (0x01) +#define MCF_GPIO_PGPPAR_PGPPAR1 (0x02) +#define MCF_GPIO_PGPPAR_PGPPAR2 (0x04) +#define MCF_GPIO_PGPPAR_PGPPAR3 (0x08) +#define MCF_GPIO_PGPPAR_PGPPAR4 (0x10) +#define MCF_GPIO_PGPPAR_PGPPAR5 (0x20) +#define MCF_GPIO_PGPPAR_PGPPAR6 (0x40) +#define MCF_GPIO_PGPPAR_PGPPAR7 (0x80) +#define MCF_GPIO_PGPPAR_IRQ8_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ9_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ10_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ11_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ12_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ13_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ14_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ15_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ8_IRQ8 (0x01) +#define MCF_GPIO_PGPPAR_IRQ9_IRQ9 (0x02) +#define MCF_GPIO_PGPPAR_IRQ10_IRQ10 (0x04) +#define MCF_GPIO_PGPPAR_IRQ11_IRQ11 (0x08) +#define MCF_GPIO_PGPPAR_IRQ12_IRQ12 (0x10) +#define MCF_GPIO_PGPPAR_IRQ13_IRQ13 (0x30) +#define MCF_GPIO_PGPPAR_IRQ14_IRQ14 (0x40) +#define MCF_GPIO_PGPPAR_IRQ15_IRQ15 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PWOR */ +#define MCF_GPIO_PWOR_PWOR0 (0x0001) +#define MCF_GPIO_PWOR_PWOR1 (0x0002) +#define MCF_GPIO_PWOR_PWOR2 (0x0004) +#define MCF_GPIO_PWOR_PWOR3 (0x0008) +#define MCF_GPIO_PWOR_PWOR4 (0x0010) +#define MCF_GPIO_PWOR_PWOR5 (0x0020) +#define MCF_GPIO_PWOR_PWOR6 (0x0040) +#define MCF_GPIO_PWOR_PWOR7 (0x0080) +#define MCF_GPIO_PWOR_PWOR8 (0x0100) +#define MCF_GPIO_PWOR_PWOR9 (0x0200) +#define MCF_GPIO_PWOR_PWOR10 (0x0400) +#define MCF_GPIO_PWOR_PWOR11 (0x0800) +#define MCF_GPIO_PWOR_PWOR12 (0x1000) +#define MCF_GPIO_PWOR_PWOR13 (0x2000) +#define MCF_GPIO_PWOR_PWOR14 (0x4000) +#define MCF_GPIO_PWOR_PWOR15 (0x8000) + +/* Bit definitions and macros for MCF_GPIO_PDSRH */ +#define MCF_GPIO_PDSRH_PDSR32 (0x0001) +#define MCF_GPIO_PDSRH_PDSR33 (0x0002) +#define MCF_GPIO_PDSRH_PDSR34 (0x0004) +#define MCF_GPIO_PDSRH_PDSR35 (0x0008) +#define MCF_GPIO_PDSRH_PDSR36 (0x0010) +#define MCF_GPIO_PDSRH_PDSR37 (0x0020) +#define MCF_GPIO_PDSRH_PDSR38 (0x0040) +#define MCF_GPIO_PDSRH_PDSR39 (0x0080) +#define MCF_GPIO_PDSRH_PDSR40 (0x0100) +#define MCF_GPIO_PDSRH_PDSR41 (0x0200) +#define MCF_GPIO_PDSRH_PDSR42 (0x0400) +#define MCF_GPIO_PDSRH_PDSR43 (0x0800) +#define MCF_GPIO_PDSRH_PDSR44 (0x1000) +#define MCF_GPIO_PDSRH_PDSR45 (0x2000) +#define MCF_GPIO_PDSRH_PDSR46 (0x4000) +#define MCF_GPIO_PDSRH_PDSR47 (0x8000) + +/* Bit definitions and macros for MCF_GPIO_PDSRL */ +#define MCF_GPIO_PDSRL_PDSR0 (0x00000001) +#define MCF_GPIO_PDSRL_PDSR1 (0x00000002) +#define MCF_GPIO_PDSRL_PDSR2 (0x00000004) +#define MCF_GPIO_PDSRL_PDSR3 (0x00000008) +#define MCF_GPIO_PDSRL_PDSR4 (0x00000010) +#define MCF_GPIO_PDSRL_PDSR5 (0x00000020) +#define MCF_GPIO_PDSRL_PDSR6 (0x00000040) +#define MCF_GPIO_PDSRL_PDSR7 (0x00000080) +#define MCF_GPIO_PDSRL_PDSR8 (0x00000100) +#define MCF_GPIO_PDSRL_PDSR9 (0x00000200) +#define MCF_GPIO_PDSRL_PDSR10 (0x00000400) +#define MCF_GPIO_PDSRL_PDSR11 (0x00000800) +#define MCF_GPIO_PDSRL_PDSR12 (0x00001000) +#define MCF_GPIO_PDSRL_PDSR13 (0x00002000) +#define MCF_GPIO_PDSRL_PDSR14 (0x00004000) +#define MCF_GPIO_PDSRL_PDSR15 (0x00008000) +#define MCF_GPIO_PDSRL_PDSR16 (0x00010000) +#define MCF_GPIO_PDSRL_PDSR17 (0x00020000) +#define MCF_GPIO_PDSRL_PDSR18 (0x00040000) +#define MCF_GPIO_PDSRL_PDSR19 (0x00080000) +#define MCF_GPIO_PDSRL_PDSR20 (0x00100000) +#define MCF_GPIO_PDSRL_PDSR21 (0x00200000) +#define MCF_GPIO_PDSRL_PDSR22 (0x00400000) +#define MCF_GPIO_PDSRL_PDSR23 (0x00800000) +#define MCF_GPIO_PDSRL_PDSR24 (0x01000000) +#define MCF_GPIO_PDSRL_PDSR25 (0x02000000) +#define MCF_GPIO_PDSRL_PDSR26 (0x04000000) +#define MCF_GPIO_PDSRL_PDSR27 (0x08000000) +#define MCF_GPIO_PDSRL_PDSR28 (0x10000000) +#define MCF_GPIO_PDSRL_PDSR29 (0x20000000) +#define MCF_GPIO_PDSRL_PDSR30 (0x40000000) +#define MCF_GPIO_PDSRL_PDSR31 (0x80000000) + +/********************************************************************* +* +* ColdFire Integration Module (CIM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CIM_RCR (*(vuint8 *)(&__IPSBAR[0x110000])) +#define MCF_CIM_RSR (*(vuint8 *)(&__IPSBAR[0x110001])) +#define MCF_CIM_CCR (*(vuint16*)(&__IPSBAR[0x110004])) +#define MCF_CIM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) +#define MCF_CIM_RCON (*(vuint16*)(&__IPSBAR[0x110008])) +#define MCF_CIM_CIR (*(vuint16*)(&__IPSBAR[0x11000A])) + +/* Bit definitions and macros for MCF_CIM_RCR */ +#define MCF_CIM_RCR_LVDE (0x01) +#define MCF_CIM_RCR_LVDRE (0x04) +#define MCF_CIM_RCR_LVDIE (0x08) +#define MCF_CIM_RCR_LVDF (0x10) +#define MCF_CIM_RCR_FRCRSTOUT (0x40) +#define MCF_CIM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for MCF_CIM_RSR */ +#define MCF_CIM_RSR_LOL (0x01) +#define MCF_CIM_RSR_LOC (0x02) +#define MCF_CIM_RSR_EXT (0x04) +#define MCF_CIM_RSR_POR (0x08) +#define MCF_CIM_RSR_WDR (0x10) +#define MCF_CIM_RSR_SOFT (0x20) +#define MCF_CIM_RSR_LVD (0x40) + +/* Bit definitions and macros for MCF_CIM_CCR */ +#define MCF_CIM_CCR_LOAD (0x8000) + +/* Bit definitions and macros for MCF_CIM_LPCR */ +#define MCF_CIM_LPCR_LVDSE (0x02) +#define MCF_CIM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF_CIM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF_CIM_LPCR_LPMD_STOP (0xC0) +#define MCF_CIM_LPCR_LPMD_WAIT (0x80) +#define MCF_CIM_LPCR_LPMD_DOZE (0x40) +#define MCF_CIM_LPCR_LPMD_RUN (0x00) + +/* Bit definitions and macros for MCF_CIM_RCON */ +#define MCF_CIM_RCON_RLOAD (0x0020) + +/********************************************************************* +* +* Clock Module (CLOCK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CLOCK_SYNCR (*(vuint16*)(&__IPSBAR[0x120000])) +#define MCF_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002])) +#define MCF_CLOCK_LPCR (*(vuint8 *)(&__IPSBAR[0x120007])) +#define MCF_CLOCK_CCHR (*(vuint8 *)(&__IPSBAR[0x120008])) +#define MCF_CLOCK_RTCDR (*(vuint32*)(&__IPSBAR[0x12000C])) + +/* Bit definitions and macros for MCF_CLOCK_SYNCR */ +#define MCF_CLOCK_SYNCR_PLLEN (0x0001) +#define MCF_CLOCK_SYNCR_PLLMODE (0x0002) +#define MCF_CLOCK_SYNCR_CLKSRC (0x0004) +#define MCF_CLOCK_SYNCR_FWKUP (0x0020) +#define MCF_CLOCK_SYNCR_DISCLK (0x0040) +#define MCF_CLOCK_SYNCR_LOCEN (0x0080) +#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) +#define MCF_CLOCK_SYNCR_LOCRE (0x0800) +#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) +#define MCF_CLOCK_SYNCR_LOLRE (0x8000) + +/* Bit definitions and macros for MCF_CLOCK_SYNSR */ +#define MCF_CLOCK_SYNSR_LOCS (0x04) +#define MCF_CLOCK_SYNSR_LOCK (0x08) +#define MCF_CLOCK_SYNSR_LOCKS (0x10) +#define MCF_CLOCK_SYNSR_CRYOSC (0x20) +#define MCF_CLOCK_SYNSR_OCOSC (0x40) +#define MCF_CLOCK_SYNSR_EXTOSC (0x80) + +/* Bit definitions and macros for MCF_CLOCK_LPCR */ +#define MCF_CLOCK_LPCR_LPD(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_CLOCK_CCHR */ +#define MCF_CLOCK_CCHR_PFD(x) (((x)&0x07)<<0) + +/* Bit definitions and macros for MCF_CLOCK_RTCDR */ +#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR0 (*(vuint16*)(&__IPSBAR[0x130000])) +#define MCF_EPORT_EPPAR1 (*(vuint16*)(&__IPSBAR[0x140000])) +#define MCF_EPORT_EPDDR0 (*(vuint8 *)(&__IPSBAR[0x130002])) +#define MCF_EPORT_EPDDR1 (*(vuint8 *)(&__IPSBAR[0x140002])) +#define MCF_EPORT_EPIER0 (*(vuint8 *)(&__IPSBAR[0x130003])) +#define MCF_EPORT_EPIER1 (*(vuint8 *)(&__IPSBAR[0x140003])) +#define MCF_EPORT_EPDR0 (*(vuint8 *)(&__IPSBAR[0x130004])) +#define MCF_EPORT_EPDR1 (*(vuint8 *)(&__IPSBAR[0x140004])) +#define MCF_EPORT_EPPDR0 (*(vuint8 *)(&__IPSBAR[0x130005])) +#define MCF_EPORT_EPPDR1 (*(vuint8 *)(&__IPSBAR[0x140005])) +#define MCF_EPORT_EPFR0 (*(vuint8 *)(&__IPSBAR[0x130006])) +#define MCF_EPORT_EPFR1 (*(vuint8 *)(&__IPSBAR[0x140006])) + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define MCF_EPORT_EPPAR_EPPA8(x) (((x)&0x0003)<<0) +#define MCF_EPORT_EPPAR_EPPA9(x) (((x)&0x0003)<<2) +#define MCF_EPORT_EPPAR_EPPA10(x) (((x)&0x0003)<<4) +#define MCF_EPORT_EPPAR_EPPA11(x) (((x)&0x0003)<<6) +#define MCF_EPORT_EPPAR_EPPA12(x) (((x)&0x0003)<<8) +#define MCF_EPORT_EPPAR_EPPA13(x) (((x)&0x0003)<<10) +#define MCF_EPORT_EPPAR_EPPA14(x) (((x)&0x0003)<<12) +#define MCF_EPORT_EPPAR_EPPA15(x) (((x)&0x0003)<<14) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (1) +#define MCF_EPORT_EPPAR_FALLING (2) +#define MCF_EPORT_EPPAR_BOTH (3) +#define MCF_EPORT_EPPAR_EPPA15_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA15_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA15_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA15_BOTH (0xC000) +#define MCF_EPORT_EPPAR_EPPA14_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA14_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA14_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA14_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA13_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA13_RISING (0x0400) +#define MCF_EPORT_EPPAR_EPPA13_FALLING (0x0800) +#define MCF_EPORT_EPPAR_EPPA13_BOTH (0x0C00) +#define MCF_EPORT_EPPAR_EPPA12_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA12_RISING (0x0100) +#define MCF_EPORT_EPPAR_EPPA12_FALLING (0x0200) +#define MCF_EPORT_EPPAR_EPPA12_BOTH (0x0300) +#define MCF_EPORT_EPPAR_EPPA11_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA11_RISING (0x0040) +#define MCF_EPORT_EPPAR_EPPA11_FALLING (0x0080) +#define MCF_EPORT_EPPAR_EPPA11_BOTH (0x00C0) +#define MCF_EPORT_EPPAR_EPPA10_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA10_RISING (0x0010) +#define MCF_EPORT_EPPAR_EPPA10_FALLING (0x0020) +#define MCF_EPORT_EPPAR_EPPA10_BOTH (0x0030) +#define MCF_EPORT_EPPAR_EPPA9_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA9_RISING (0x0004) +#define MCF_EPORT_EPPAR_EPPA9_FALLING (0x0008) +#define MCF_EPORT_EPPAR_EPPA9_BOTH (0x000C) +#define MCF_EPORT_EPPAR_EPPA8_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA8_RISING (0x0001) +#define MCF_EPORT_EPPAR_EPPA8_FALLING (0x0002) +#define MCF_EPORT_EPPAR_EPPA8_BOTH (0x0003) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x02) +#define MCF_EPORT_EPDDR_EPDD2 (0x04) +#define MCF_EPORT_EPDDR_EPDD3 (0x08) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) +#define MCF_EPORT_EPDDR_EPDD8 (0x01) +#define MCF_EPORT_EPDDR_EPDD9 (0x02) +#define MCF_EPORT_EPDDR_EPDD10 (0x04) +#define MCF_EPORT_EPDDR_EPDD11 (0x08) +#define MCF_EPORT_EPDDR_EPDD12 (0x10) +#define MCF_EPORT_EPDDR_EPDD13 (0x20) +#define MCF_EPORT_EPDDR_EPDD14 (0x40) +#define MCF_EPORT_EPDDR_EPDD15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x02) +#define MCF_EPORT_EPIER_EPIE2 (0x04) +#define MCF_EPORT_EPIER_EPIE3 (0x08) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) +#define MCF_EPORT_EPIER_EPIE8 (0x01) +#define MCF_EPORT_EPIER_EPIE9 (0x02) +#define MCF_EPORT_EPIER_EPIE10 (0x04) +#define MCF_EPORT_EPIER_EPIE11 (0x08) +#define MCF_EPORT_EPIER_EPIE12 (0x10) +#define MCF_EPORT_EPIER_EPIE13 (0x20) +#define MCF_EPORT_EPIER_EPIE14 (0x40) +#define MCF_EPORT_EPIER_EPIE15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x02) +#define MCF_EPORT_EPDR_EPD2 (0x04) +#define MCF_EPORT_EPDR_EPD3 (0x08) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) +#define MCF_EPORT_EPDR_EPD8 (0x01) +#define MCF_EPORT_EPDR_EPD9 (0x02) +#define MCF_EPORT_EPDR_EPD10 (0x04) +#define MCF_EPORT_EPDR_EPD11 (0x08) +#define MCF_EPORT_EPDR_EPD12 (0x10) +#define MCF_EPORT_EPDR_EPD13 (0x20) +#define MCF_EPORT_EPDR_EPD14 (0x40) +#define MCF_EPORT_EPDR_EPD15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x02) +#define MCF_EPORT_EPPDR_EPPD2 (0x04) +#define MCF_EPORT_EPPDR_EPPD3 (0x08) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) +#define MCF_EPORT_EPPDR_EPPD8 (0x01) +#define MCF_EPORT_EPPDR_EPPD9 (0x02) +#define MCF_EPORT_EPPDR_EPPD10 (0x04) +#define MCF_EPORT_EPPDR_EPPD11 (0x08) +#define MCF_EPORT_EPPDR_EPPD12 (0x10) +#define MCF_EPORT_EPPDR_EPPD13 (0x20) +#define MCF_EPORT_EPPDR_EPPD14 (0x40) +#define MCF_EPORT_EPPDR_EPPD15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x02) +#define MCF_EPORT_EPFR_EPF2 (0x04) +#define MCF_EPORT_EPFR_EPF3 (0x08) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) +#define MCF_EPORT_EPFR_EPF8 (0x01) +#define MCF_EPORT_EPFR_EPF9 (0x02) +#define MCF_EPORT_EPFR_EPF10 (0x04) +#define MCF_EPORT_EPFR_EPF11 (0x08) +#define MCF_EPORT_EPFR_EPF12 (0x10) +#define MCF_EPORT_EPFR_EPF13 (0x20) +#define MCF_EPORT_EPFR_EPF14 (0x40) +#define MCF_EPORT_EPFR_EPF15 (0x80) + +/********************************************************************* +* +* Programmable Interrupt Timer Modules (PIT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000])) +#define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002])) +#define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004])) +#define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000])) +#define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002])) +#define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004])) +#define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000+((x)*0x10000)])) +#define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002+((x)*0x10000)])) +#define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004+((x)*0x10000)])) + +/* Bit definitions and macros for MCF_PIT_PCSR */ +#define MCF_PIT_PCSR_EN (0x0001) +#define MCF_PIT_PCSR_RLD (0x0002) +#define MCF_PIT_PCSR_PIF (0x0004) +#define MCF_PIT_PCSR_PIE (0x0008) +#define MCF_PIT_PCSR_OVW (0x0010) +#define MCF_PIT_PCSR_HALTED (0x0020) +#define MCF_PIT_PCSR_DOZE (0x0040) +#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) + +/* Bit definitions and macros for MCF_PIT_PMR */ +#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PIT_PCNTR */ +#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0) + +/********************************************************************* +* +* Analog-to-Digital Converter (ADC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_ADC_CTRL1 (*(vuint16*)(&__IPSBAR[0x190000])) +#define MCF_ADC_CTRL2 (*(vuint16*)(&__IPSBAR[0x190002])) +#define MCF_ADC_ADZCC (*(vuint16*)(&__IPSBAR[0x190004])) +#define MCF_ADC_ADLST1 (*(vuint16*)(&__IPSBAR[0x190006])) +#define MCF_ADC_ADLST2 (*(vuint16*)(&__IPSBAR[0x190008])) +#define MCF_ADC_ADSDIS (*(vuint16*)(&__IPSBAR[0x19000A])) +#define MCF_ADC_ADSTAT (*(vuint16*)(&__IPSBAR[0x19000C])) +#define MCF_ADC_ADLSTAT (*(vuint16*)(&__IPSBAR[0x19000E])) +#define MCF_ADC_ADZCSTAT (*(vuint16*)(&__IPSBAR[0x190010])) +#define MCF_ADC_ADRSLT0 (*(vuint16*)(&__IPSBAR[0x190012])) +#define MCF_ADC_ADRSLT1 (*(vuint16*)(&__IPSBAR[0x190014])) +#define MCF_ADC_ADRSLT2 (*(vuint16*)(&__IPSBAR[0x190016])) +#define MCF_ADC_ADRSLT3 (*(vuint16*)(&__IPSBAR[0x190018])) +#define MCF_ADC_ADRSLT4 (*(vuint16*)(&__IPSBAR[0x19001A])) +#define MCF_ADC_ADRSLT5 (*(vuint16*)(&__IPSBAR[0x19001C])) +#define MCF_ADC_ADRSLT6 (*(vuint16*)(&__IPSBAR[0x19001E])) +#define MCF_ADC_ADRSLT7 (*(vuint16*)(&__IPSBAR[0x190020])) +#define MCF_ADC_ADRSLT(x) (*(vuint16*)(&__IPSBAR[0x190012+((x)*0x002)])) +#define MCF_ADC_ADLLMT0 (*(vuint16*)(&__IPSBAR[0x190022])) +#define MCF_ADC_ADLLMT1 (*(vuint16*)(&__IPSBAR[0x190024])) +#define MCF_ADC_ADLLMT2 (*(vuint16*)(&__IPSBAR[0x190026])) +#define MCF_ADC_ADLLMT3 (*(vuint16*)(&__IPSBAR[0x190028])) +#define MCF_ADC_ADLLMT4 (*(vuint16*)(&__IPSBAR[0x19002A])) +#define MCF_ADC_ADLLMT5 (*(vuint16*)(&__IPSBAR[0x19002C])) +#define MCF_ADC_ADLLMT6 (*(vuint16*)(&__IPSBAR[0x19002E])) +#define MCF_ADC_ADLLMT7 (*(vuint16*)(&__IPSBAR[0x190030])) +#define MCF_ADC_ADLLMT(x) (*(vuint16*)(&__IPSBAR[0x190022+((x)*0x002)])) +#define MCF_ADC_ADHLMT0 (*(vuint16*)(&__IPSBAR[0x190032])) +#define MCF_ADC_ADHLMT1 (*(vuint16*)(&__IPSBAR[0x190034])) +#define MCF_ADC_ADHLMT2 (*(vuint16*)(&__IPSBAR[0x190036])) +#define MCF_ADC_ADHLMT3 (*(vuint16*)(&__IPSBAR[0x190038])) +#define MCF_ADC_ADHLMT4 (*(vuint16*)(&__IPSBAR[0x19003A])) +#define MCF_ADC_ADHLMT5 (*(vuint16*)(&__IPSBAR[0x19003C])) +#define MCF_ADC_ADHLMT6 (*(vuint16*)(&__IPSBAR[0x19003E])) +#define MCF_ADC_ADHLMT7 (*(vuint16*)(&__IPSBAR[0x190040])) +#define MCF_ADC_ADHLMT(x) (*(vuint16*)(&__IPSBAR[0x190032+((x)*0x002)])) +#define MCF_ADC_ADOFS0 (*(vuint16*)(&__IPSBAR[0x190042])) +#define MCF_ADC_ADOFS1 (*(vuint16*)(&__IPSBAR[0x190044])) +#define MCF_ADC_ADOFS2 (*(vuint16*)(&__IPSBAR[0x190046])) +#define MCF_ADC_ADOFS3 (*(vuint16*)(&__IPSBAR[0x190048])) +#define MCF_ADC_ADOFS4 (*(vuint16*)(&__IPSBAR[0x19004A])) +#define MCF_ADC_ADOFS5 (*(vuint16*)(&__IPSBAR[0x19004C])) +#define MCF_ADC_ADOFS6 (*(vuint16*)(&__IPSBAR[0x19004E])) +#define MCF_ADC_ADOFS7 (*(vuint16*)(&__IPSBAR[0x190050])) +#define MCF_ADC_ADOFS(x) (*(vuint16*)(&__IPSBAR[0x190042+((x)*0x002)])) +#define MCF_ADC_POWER (*(vuint16*)(&__IPSBAR[0x190052])) +#define MCF_ADC_CAL (*(vuint16*)(&__IPSBAR[0x190054])) + +/* Bit definitions and macros for MCF_ADC_CTRL1 */ +#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x0007)<<0) +#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0x000F)<<4) +#define MCF_ADC_CTRL1_HLMTIE (0x0100) +#define MCF_ADC_CTRL1_LLMTIE (0x0200) +#define MCF_ADC_CTRL1_ZCIE (0x0400) +#define MCF_ADC_CTRL1_EOSIE0 (0x0800) +#define MCF_ADC_CTRL1_SYNC0 (0x1000) +#define MCF_ADC_CTRL1_START0 (0x2000) +#define MCF_ADC_CTRL1_STOP0 (0x4000) + +/* Bit definitions and macros for MCF_ADC_CTRL2 */ +#define MCF_ADC_CTRL2_DIV(x) (((x)&0x001F)<<0) +#define MCF_ADC_CTRL2_SIMULT (0x0020) +#define MCF_ADC_CTRL2_EOSIE1 (0x0800) +#define MCF_ADC_CTRL2_SYNC1 (0x1000) +#define MCF_ADC_CTRL2_START1 (0x2000) +#define MCF_ADC_CTRL2_STOP1 (0x4000) + +/* Bit definitions and macros for MCF_ADC_ADZCC */ +#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x0003)<<0) +#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x0003)<<2) +#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x0003)<<4) +#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x0003)<<6) +#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x0003)<<8) +#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x0003)<<10) +#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x0003)<<12) +#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for MCF_ADC_ADLST1 */ +#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x0007)<<0) +#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x0007)<<4) +#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x0007)<<8) +#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x0007)<<12) + +/* Bit definitions and macros for MCF_ADC_ADLST2 */ +#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x0007)<<0) +#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x0007)<<4) +#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x0007)<<8) +#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x0007)<<12) + +/* Bit definitions and macros for MCF_ADC_ADSDIS */ +#define MCF_ADC_ADSDIS_DS0 (0x0001) +#define MCF_ADC_ADSDIS_DS1 (0x0002) +#define MCF_ADC_ADSDIS_DS2 (0x0004) +#define MCF_ADC_ADSDIS_DS3 (0x0008) +#define MCF_ADC_ADSDIS_DS4 (0x0010) +#define MCF_ADC_ADSDIS_DS5 (0x0020) +#define MCF_ADC_ADSDIS_DS6 (0x0040) +#define MCF_ADC_ADSDIS_DS7 (0x0080) + +/* Bit definitions and macros for MCF_ADC_ADSTAT */ +#define MCF_ADC_ADSTAT_RDY0 (0x0001) +#define MCF_ADC_ADSTAT_RDY1 (0x0002) +#define MCF_ADC_ADSTAT_RDY2 (0x0004) +#define MCF_ADC_ADSTAT_RDY3 (0x0008) +#define MCF_ADC_ADSTAT_RDY4 (0x0010) +#define MCF_ADC_ADSTAT_RDY5 (0x0020) +#define MCF_ADC_ADSTAT_RDY6 (0x0040) +#define MCF_ADC_ADSTAT_RDY7 (0x0080) +#define MCF_ADC_ADSTAT_HLMT (0x0100) +#define MCF_ADC_ADSTAT_LLMTI (0x0200) +#define MCF_ADC_ADSTAT_ZCI (0x0400) +#define MCF_ADC_ADSTAT_EOSI (0x0800) +#define MCF_ADC_ADSTAT_CIP (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADLSTAT */ +#define MCF_ADC_ADLSTAT_LLS0 (0x0001) +#define MCF_ADC_ADLSTAT_LLS1 (0x0002) +#define MCF_ADC_ADLSTAT_LLS2 (0x0004) +#define MCF_ADC_ADLSTAT_LLS3 (0x0008) +#define MCF_ADC_ADLSTAT_LLS4 (0x0010) +#define MCF_ADC_ADLSTAT_LLS5 (0x0020) +#define MCF_ADC_ADLSTAT_LLS6 (0x0040) +#define MCF_ADC_ADLSTAT_LLS7 (0x0080) +#define MCF_ADC_ADLSTAT_HLS0 (0x0100) +#define MCF_ADC_ADLSTAT_HLS1 (0x0200) +#define MCF_ADC_ADLSTAT_HLS2 (0x0400) +#define MCF_ADC_ADLSTAT_HLS3 (0x0800) +#define MCF_ADC_ADLSTAT_HLS4 (0x1000) +#define MCF_ADC_ADLSTAT_HLS5 (0x2000) +#define MCF_ADC_ADLSTAT_HLS6 (0x4000) +#define MCF_ADC_ADLSTAT_HLS7 (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADZCSTAT */ +#define MCF_ADC_ADZCSTAT_ZCS0 (0x0001) +#define MCF_ADC_ADZCSTAT_ZCS1 (0x0002) +#define MCF_ADC_ADZCSTAT_ZCS2 (0x0004) +#define MCF_ADC_ADZCSTAT_ZCS3 (0x0008) +#define MCF_ADC_ADZCSTAT_ZCS4 (0x0010) +#define MCF_ADC_ADZCSTAT_ZCS5 (0x0020) +#define MCF_ADC_ADZCSTAT_ZCS6 (0x0040) +#define MCF_ADC_ADZCSTAT_ZCS7 (0x0080) + +/* Bit definitions and macros for MCF_ADC_ADRSLT */ +#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0x0FFF)<<3) +#define MCF_ADC_ADRSLT_SEXT (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADLLMT */ +#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0x0FFF)<<3) + +/* Bit definitions and macros for MCF_ADC_ADHLMT */ +#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0x0FFF)<<3) + +/* Bit definitions and macros for MCF_ADC_ADOFS */ +#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0x0FFF)<<3) + +/* Bit definitions and macros for MCF_ADC_POWER */ +#define MCF_ADC_POWER_PD0 (0x0001) +#define MCF_ADC_POWER_PD1 (0x0002) +#define MCF_ADC_POWER_PD2 (0x0004) +#define MCF_ADC_POWER_APD (0x0008) +#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x003F)<<4) +#define MCF_ADC_POWER_PSTS0 (0x0400) +#define MCF_ADC_POWER_PSTS1 (0x0800) +#define MCF_ADC_POWER_PSTS2 (0x1000) +#define MCF_ADC_POWER_ASTBY (0x8000) + +/* Bit definitions and macros for MCF_ADC_CAL */ +#define MCF_ADC_CAL_CAL0 (0x0001) +#define MCF_ADC_CAL_CRS0 (0x0002) +#define MCF_ADC_CAL_CAL1 (0x0004) +#define MCF_ADC_CAL_CRS1 (0x0008) + +/********************************************************************* +* +* General Purpose Timer (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000])) +#define MCF_GPT_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001])) +#define MCF_GPT_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002])) +#define MCF_GPT_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003])) +#define MCF_GPT_GPTCNT (*(vuint16*)(&__IPSBAR[0x1A0004])) +#define MCF_GPT_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006])) +#define MCF_GPT_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008])) +#define MCF_GPT_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009])) +#define MCF_GPT_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B])) +#define MCF_GPT_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C])) +#define MCF_GPT_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D])) +#define MCF_GPT_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E])) +#define MCF_GPT_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F])) +#define MCF_GPT_GPTC0 (*(vuint16*)(&__IPSBAR[0x1A0010])) +#define MCF_GPT_GPTC1 (*(vuint16*)(&__IPSBAR[0x1A0012])) +#define MCF_GPT_GPTC2 (*(vuint16*)(&__IPSBAR[0x1A0014])) +#define MCF_GPT_GPTC3 (*(vuint16*)(&__IPSBAR[0x1A0016])) +#define MCF_GPT_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1A0010+((x)*0x002)])) +#define MCF_GPT_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018])) +#define MCF_GPT_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019])) +#define MCF_GPT_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1A001A])) +#define MCF_GPT_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D])) +#define MCF_GPT_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E])) + +/* Bit definitions and macros for MCF_GPT_GPTIOS */ +#define MCF_GPT_GPTIOS_IOS0 (0x01) +#define MCF_GPT_GPTIOS_IOS1 (0x02) +#define MCF_GPT_GPTIOS_IOS2 (0x04) +#define MCF_GPT_GPTIOS_IOS3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTCFORC */ +#define MCF_GPT_GPTCFORC_FOC0 (0x01) +#define MCF_GPT_GPTCFORC_FOC1 (0x02) +#define MCF_GPT_GPTCFORC_FOC2 (0x04) +#define MCF_GPT_GPTCFORC_FOC3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTOC3D */ +#define MCF_GPT_GPTOC3D_OC3D0 (0x01) +#define MCF_GPT_GPTOC3D_OC3D1 (0x02) +#define MCF_GPT_GPTOC3D_OC3D2 (0x04) +#define MCF_GPT_GPTOC3D_OC3D3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTSCR1 */ +#define MCF_GPT_GPTSCR1_TFFCA (0x10) +#define MCF_GPT_GPTSCR1_GPTEN (0x80) + +/* Bit definitions and macros for MCF_GPT_GPTTOV */ +#define MCF_GPT_GPTTOV_TOV0 (0x01) +#define MCF_GPT_GPTTOV_TOV1 (0x02) +#define MCF_GPT_GPTTOV_TOV2 (0x04) +#define MCF_GPT_GPTTOV_TOV3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTCTL1 */ +#define MCF_GPT_GPTCTL1_OL0 (0x01) +#define MCF_GPT_GPTCTL1_OM0 (0x02) +#define MCF_GPT_GPTCTL1_OL1 (0x04) +#define MCF_GPT_GPTCTL1_OM1 (0x08) +#define MCF_GPT_GPTCTL1_OL2 (0x10) +#define MCF_GPT_GPTCTL1_OM2 (0x20) +#define MCF_GPT_GPTCTL1_OL3 (0x40) +#define MCF_GPT_GPTCTL1_OM3 (0x80) +#define MCF_GPT_GPTCTL1_OUTPUT3_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT3_TOGGLE ((0x40)) +#define MCF_GPT_GPTCTL1_OUTPUT3_CLEAR ((0x80)) +#define MCF_GPT_GPTCTL1_OUTPUT3_SET ((0xC0)) +#define MCF_GPT_GPTCTL1_OUTPUT2_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT2_TOGGLE ((0x10)) +#define MCF_GPT_GPTCTL1_OUTPUT2_CLEAR ((0x20)) +#define MCF_GPT_GPTCTL1_OUTPUT2_SET ((0x30)) +#define MCF_GPT_GPTCTL1_OUTPUT1_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT1_TOGGLE ((0x04)) +#define MCF_GPT_GPTCTL1_OUTPUT1_CLEAR ((0x08)) +#define MCF_GPT_GPTCTL1_OUTPUT1_SET ((0x0C)) +#define MCF_GPT_GPTCTL1_OUTPUT0_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT0_TOGGLE ((0x01)) +#define MCF_GPT_GPTCTL1_OUTPUT0_CLEAR ((0x02)) +#define MCF_GPT_GPTCTL1_OUTPUT0_SET ((0x03)) + +/* Bit definitions and macros for MCF_GPT_GPTCTL2 */ +#define MCF_GPT_GPTCTL2_EDG0A (0x01) +#define MCF_GPT_GPTCTL2_EDG0B (0x02) +#define MCF_GPT_GPTCTL2_EDG1A (0x04) +#define MCF_GPT_GPTCTL2_EDG1B (0x08) +#define MCF_GPT_GPTCTL2_EDG2A (0x10) +#define MCF_GPT_GPTCTL2_EDG2B (0x20) +#define MCF_GPT_GPTCTL2_EDG3A (0x40) +#define MCF_GPT_GPTCTL2_EDG3B (0x80) +#define MCF_GPT_GPTCTL2_INPUT3_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT3_RISING ((0x40)) +#define MCF_GPT_GPTCTL2_INPUT3_FALLING ((0x80)) +#define MCF_GPT_GPTCTL2_INPUT3_ANY ((0xC0)) +#define MCF_GPT_GPTCTL2_INPUT2_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT2_RISING ((0x10)) +#define MCF_GPT_GPTCTL2_INPUT2_FALLING ((0x20)) +#define MCF_GPT_GPTCTL2_INPUT2_ANY ((0x30)) +#define MCF_GPT_GPTCTL2_INPUT1_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT1_RISING ((0x04)) +#define MCF_GPT_GPTCTL2_INPUT1_FALLING ((0x08)) +#define MCF_GPT_GPTCTL2_INPUT1_ANY ((0x0C)) +#define MCF_GPT_GPTCTL2_INPUT0_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT0_RISING ((0x01)) +#define MCF_GPT_GPTCTL2_INPUT0_FALLING ((0x02)) +#define MCF_GPT_GPTCTL2_INPUT0_ANY ((0x03)) + +/* Bit definitions and macros for MCF_GPT_GPTIE */ +#define MCF_GPT_GPTIE_CI0 (0x01) +#define MCF_GPT_GPTIE_CI1 (0x02) +#define MCF_GPT_GPTIE_CI2 (0x04) +#define MCF_GPT_GPTIE_CI3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTSCR2 */ +#define MCF_GPT_GPTSCR2_PR(x) (((x)&0x07)<<0) +#define MCF_GPT_GPTSCR2_TCRE (0x08) +#define MCF_GPT_GPTSCR2_RDPT (0x10) +#define MCF_GPT_GPTSCR2_PUPT (0x20) +#define MCF_GPT_GPTSCR2_TOI (0x80) +#define MCF_GPT_GPTSCR2_PR_1 ((0x00)) +#define MCF_GPT_GPTSCR2_PR_2 ((0x01)) +#define MCF_GPT_GPTSCR2_PR_4 ((0x02)) +#define MCF_GPT_GPTSCR2_PR_8 ((0x03)) +#define MCF_GPT_GPTSCR2_PR_16 ((0x04)) +#define MCF_GPT_GPTSCR2_PR_32 ((0x05)) +#define MCF_GPT_GPTSCR2_PR_64 ((0x06)) +#define MCF_GPT_GPTSCR2_PR_128 ((0x07)) + +/* Bit definitions and macros for MCF_GPT_GPTFLG1 */ +#define MCF_GPT_GPTFLG1_CF0 (0x01) +#define MCF_GPT_GPTFLG1_CF1 (0x02) +#define MCF_GPT_GPTFLG1_CF2 (0x04) +#define MCF_GPT_GPTFLG1_CF3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTFLG2 */ +#define MCF_GPT_GPTFLG2_CF0 (0x01) +#define MCF_GPT_GPTFLG2_CF1 (0x02) +#define MCF_GPT_GPTFLG2_CF2 (0x04) +#define MCF_GPT_GPTFLG2_CF3 (0x08) +#define MCF_GPT_GPTFLG2_TOF (0x80) + +/* Bit definitions and macros for MCF_GPT_GPTC */ +#define MCF_GPT_GPTC_CCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_GPT_GPTPACTL */ +#define MCF_GPT_GPTPACTL_PAI (0x01) +#define MCF_GPT_GPTPACTL_PAOVI (0x02) +#define MCF_GPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) +#define MCF_GPT_GPTPACTL_PEDGE (0x10) +#define MCF_GPT_GPTPACTL_PAMOD (0x20) +#define MCF_GPT_GPTPACTL_PAE (0x40) +#define MCF_GPT_GPTPACTL_CLK_GPTPR ((0x00)) +#define MCF_GPT_GPTPACTL_CLK_PACLK ((0x01)) +#define MCF_GPT_GPTPACTL_CLK_PACLK_256 ((0x02)) +#define MCF_GPT_GPTPACTL_CLK_PACLK_65536 ((0x03)) + +/* Bit definitions and macros for MCF_GPT_GPTPAFLG */ +#define MCF_GPT_GPTPAFLG_PAIF (0x01) +#define MCF_GPT_GPTPAFLG_PAOVF (0x02) + +/* Bit definitions and macros for MCF_GPT_GPTPACNT */ +#define MCF_GPT_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_GPT_GPTPORT */ +#define MCF_GPT_GPTPORT_PORTT(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_GPT_GPTDDR */ +#define MCF_GPT_GPTDDR_DDRT0 (0x01) +#define MCF_GPT_GPTDDR_DDRT1 (0x02) +#define MCF_GPT_GPTDDR_DDRT2 (0x04) +#define MCF_GPT_GPTDDR_DDRT3 (0x08) + +/********************************************************************* +* +* Pulse Width Modulation (PWM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PWM_PWME (*(vuint8 *)(&__IPSBAR[0x1B0000])) +#define MCF_PWM_PWMPOL (*(vuint8 *)(&__IPSBAR[0x1B0001])) +#define MCF_PWM_PWMCLK (*(vuint8 *)(&__IPSBAR[0x1B0002])) +#define MCF_PWM_PWMPRCLK (*(vuint8 *)(&__IPSBAR[0x1B0003])) +#define MCF_PWM_PWMCAE (*(vuint8 *)(&__IPSBAR[0x1B0004])) +#define MCF_PWM_PWMCTL (*(vuint8 *)(&__IPSBAR[0x1B0005])) +#define MCF_PWM_PWMSCLA (*(vuint8 *)(&__IPSBAR[0x1B0008])) +#define MCF_PWM_PWMSCLB (*(vuint8 *)(&__IPSBAR[0x1B0009])) +#define MCF_PWM_PWMCNT0 (*(vuint8 *)(&__IPSBAR[0x1B000C])) +#define MCF_PWM_PWMCNT1 (*(vuint8 *)(&__IPSBAR[0x1B000D])) +#define MCF_PWM_PWMCNT2 (*(vuint8 *)(&__IPSBAR[0x1B000E])) +#define MCF_PWM_PWMCNT3 (*(vuint8 *)(&__IPSBAR[0x1B000F])) +#define MCF_PWM_PWMCNT4 (*(vuint8 *)(&__IPSBAR[0x1B0010])) +#define MCF_PWM_PWMCNT5 (*(vuint8 *)(&__IPSBAR[0x1B0011])) +#define MCF_PWM_PWMCNT6 (*(vuint8 *)(&__IPSBAR[0x1B0012])) +#define MCF_PWM_PWMCNT7 (*(vuint8 *)(&__IPSBAR[0x1B0013])) +#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(&__IPSBAR[0x1B000C+((x)*0x001)])) +#define MCF_PWM_PWMPER0 (*(vuint8 *)(&__IPSBAR[0x1B0014])) +#define MCF_PWM_PWMPER1 (*(vuint8 *)(&__IPSBAR[0x1B0015])) +#define MCF_PWM_PWMPER2 (*(vuint8 *)(&__IPSBAR[0x1B0016])) +#define MCF_PWM_PWMPER3 (*(vuint8 *)(&__IPSBAR[0x1B0017])) +#define MCF_PWM_PWMPER4 (*(vuint8 *)(&__IPSBAR[0x1B0018])) +#define MCF_PWM_PWMPER5 (*(vuint8 *)(&__IPSBAR[0x1B0019])) +#define MCF_PWM_PWMPER6 (*(vuint8 *)(&__IPSBAR[0x1B001A])) +#define MCF_PWM_PWMPER7 (*(vuint8 *)(&__IPSBAR[0x1B001B])) +#define MCF_PWM_PWMPER(x) (*(vuint8 *)(&__IPSBAR[0x1B0014+((x)*0x001)])) +#define MCF_PWM_PWMDTY0 (*(vuint8 *)(&__IPSBAR[0x1B001C])) +#define MCF_PWM_PWMDTY1 (*(vuint8 *)(&__IPSBAR[0x1B001D])) +#define MCF_PWM_PWMDTY2 (*(vuint8 *)(&__IPSBAR[0x1B001E])) +#define MCF_PWM_PWMDTY3 (*(vuint8 *)(&__IPSBAR[0x1B001F])) +#define MCF_PWM_PWMDTY4 (*(vuint8 *)(&__IPSBAR[0x1B0020])) +#define MCF_PWM_PWMDTY5 (*(vuint8 *)(&__IPSBAR[0x1B0021])) +#define MCF_PWM_PWMDTY6 (*(vuint8 *)(&__IPSBAR[0x1B0022])) +#define MCF_PWM_PWMDTY7 (*(vuint8 *)(&__IPSBAR[0x1B0023])) +#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(&__IPSBAR[0x1B001C+((x)*0x001)])) +#define MCF_PWM_PWMSDN (*(vuint8 *)(&__IPSBAR[0x1B0024])) + +/* Bit definitions and macros for MCF_PWM_PWME */ +#define MCF_PWM_PWME_PWME0 (0x01) +#define MCF_PWM_PWME_PWME1 (0x02) +#define MCF_PWM_PWME_PWME2 (0x04) +#define MCF_PWM_PWME_PWME3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMPOL */ +#define MCF_PWM_PWMPOL_PPOL0 (0x01) +#define MCF_PWM_PWMPOL_PPOL1 (0x02) +#define MCF_PWM_PWMPOL_PPOL2 (0x04) +#define MCF_PWM_PWMPOL_PPOL3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMCLK */ +#define MCF_PWM_PWMCLK_PCLK0 (0x01) +#define MCF_PWM_PWMCLK_PCLK1 (0x02) +#define MCF_PWM_PWMCLK_PCLK2 (0x04) +#define MCF_PWM_PWMCLK_PCLK3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMPRCLK */ +#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x07)<<0) +#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF_PWM_PWMCAE */ +#define MCF_PWM_PWMCAE_CAE0 (0x01) +#define MCF_PWM_PWMCAE_CAE1 (0x02) +#define MCF_PWM_PWMCAE_CAE2 (0x04) +#define MCF_PWM_PWMCAE_CAE3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMCTL */ +#define MCF_PWM_PWMCTL_PFRZ (0x04) +#define MCF_PWM_PWMCTL_PSWAI (0x08) +#define MCF_PWM_PWMCTL_CON01 (0x10) +#define MCF_PWM_PWMCTL_CON23 (0x20) + +/* Bit definitions and macros for MCF_PWM_PWMSCLA */ +#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMSCLB */ +#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMCNT */ +#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMPER */ +#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMDTY */ +#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMSDN */ +#define MCF_PWM_PWMSDN_SDNEN (0x01) +#define MCF_PWM_PWMSDN_PWM7IL (0x02) +#define MCF_PWM_PWMSDN_PWM7IN (0x04) +#define MCF_PWM_PWMSDN_LVL (0x10) +#define MCF_PWM_PWMSDN_RESTART (0x20) +#define MCF_PWM_PWMSDN_IE (0x40) +#define MCF_PWM_PWMSDN_IF (0x80) + +/********************************************************************* +* +* FlexCAN Module (CAN) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CAN_CANMCR (*(vuint32*)(&__IPSBAR[0x1C0000])) +#define MCF_CAN_CANCTRL (*(vuint32*)(&__IPSBAR[0x1C0004])) +#define MCF_CAN_TIMER (*(vuint32*)(&__IPSBAR[0x1C0008])) +#define MCF_CAN_RXGMASK (*(vuint32*)(&__IPSBAR[0x1C0010])) +#define MCF_CAN_RX14MASK (*(vuint32*)(&__IPSBAR[0x1C0014])) +#define MCF_CAN_RX15MASK (*(vuint32*)(&__IPSBAR[0x1C0018])) +#define MCF_CAN_ERRCNT (*(vuint32*)(&__IPSBAR[0x1C001C])) +#define MCF_CAN_ERRSTAT (*(vuint32*)(&__IPSBAR[0x1C0020])) +#define MCF_CAN_IMASK (*(vuint32*)(&__IPSBAR[0x1C0028])) +#define MCF_CAN_IFLAG (*(vuint32*)(&__IPSBAR[0x1C0030])) + +/* Bit definitions and macros for MCF_CAN_CANMCR */ +#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) +#define MCF_CAN_CANMCR_SUPV (0x00800000) +#define MCF_CAN_CANMCR_FRZACK (0x01000000) +#define MCF_CAN_CANMCR_SOFTRST (0x02000000) +#define MCF_CAN_CANMCR_HALT (0x10000000) +#define MCF_CAN_CANMCR_FRZ (0x40000000) +#define MCF_CAN_CANMCR_MDIS (0x80000000) + +/* Bit definitions and macros for MCF_CAN_CANCTRL */ +#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) +#define MCF_CAN_CANCTRL_LOM (0x00000008) +#define MCF_CAN_CANCTRL_LBUF (0x00000010) +#define MCF_CAN_CANCTRL_TSYNC (0x00000020) +#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) +#define MCF_CAN_CANCTRL_SAMP (0x00000080) +#define MCF_CAN_CANCTRL_LPB (0x00001000) +#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) +#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) +#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) +#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) +#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) +#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) +#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_CAN_TIMER */ +#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RXGMASK */ +#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX14MASK */ +#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX15MASK */ +#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_ERRCNT */ +#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) +#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for MCF_CAN_ERRSTAT */ +#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) +#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) +#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) +#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) +#define MCF_CAN_ERRSTAT_TXRX (0x00000040) +#define MCF_CAN_ERRSTAT_IDLE (0x00000080) +#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) +#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) +#define MCF_CAN_ERRSTAT_STFERR (0x00000400) +#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) +#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) +#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) +#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) +#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) +#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) +#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) + +/* Bit definitions and macros for MCF_CAN_IMASK */ +#define MCF_CAN_IMASK_BUF(x) (1< +#include +#include + +struct if_config { + u8_t flags; + u8_t hwaddr_len; + u16_t mtu; + u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; + sys_thread_t net_task; + void(*phy_init)(void); + u8_t name[2]; +}; + +extern err_t mcf5225xif_init(struct netif *); +extern void handle_rx_frame(struct netif*); + +extern void smi_init(u32_t); +extern void smi_write(u8_t,u8_t,u16_t); +extern u16_t smi_read(u8_t,u8_t); + +#define MAX_FRAME_LEN 1518 +#define MTU_SIZE (MAX_FRAME_LEN-18) +#define MSCR_MII_SPEED(clk) ((clk/5000000+1)<<1) +#define PHY_ADDR 1 +#define PHY_REG_ID1 2 +#define PHY_REG_ID2 3 + +#endif /* FEC_H */ diff --git a/bsps/m68k/include/mcf5225x/mcf5225x.h b/bsps/m68k/include/mcf5225x/mcf5225x.h new file mode 100644 index 0000000000..ded447ffac --- /dev/null +++ b/bsps/m68k/include/mcf5225x/mcf5225x.h @@ -0,0 +1,3552 @@ +/* + * File: mcf5225x.h + * Purpose: Register and bit definitions + */ + +#ifndef __MCF5225x_H__ +#define __MCF5225x_H__ + +typedef volatile unsigned char vuint8; +typedef volatile unsigned short vuint16; +typedef volatile unsigned long vuint32; + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x000000])) +#define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x000008])) +#define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) +#define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x000010])) +#define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x000011])) +#define MCF_SCM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) +#define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x000013])) +#define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) +#define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x00001C])) +#define MCF_SCM_MPR (*(vuint32*)(&__IPSBAR[0x000020])) +#define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x000021])) +#define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x000022])) +#define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x000023])) +#define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x000024])) +#define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x000025])) +#define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x000026])) +#define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x000027])) +#define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x000028])) +#define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x000029])) +#define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x00002A])) +#define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x00002B])) +#define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x00002C])) +#define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x000030])) +#define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x000031])) + +/* Bit definitions and macros for MCF_SCM_IPSBAR */ +#define MCF_SCM_IPSBAR_V (0x00000001) +#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000) + +/* Bit definitions and macros for MCF_SCM_RAMBAR */ +#define MCF_SCM_RAMBAR_BDE (0x00000200) +#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_SCM_CRSR */ +#define MCF_SCM_CRSR_CWDR (0x20) +#define MCF_SCM_CRSR_EXT (0x80) + +/* Bit definitions and macros for MCF_SCM_CWCR */ +#define MCF_SCM_CWCR_CWTIC (0x01) +#define MCF_SCM_CWCR_CWTAVAL (0x02) +#define MCF_SCM_CWCR_CWTA (0x04) +#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) +#define MCF_SCM_CWCR_CWRI (0x40) +#define MCF_SCM_CWCR_CWE (0x80) + +/* Bit definitions and macros for MCF_SCM_LPICR */ +#define MCF_SCM_LPICR_XIPL(x) (((x)&0x07)<<4) +#define MCF_SCM_LPICR_ENBSTOP (0x80) + +/* Bit definitions and macros for MCF_SCM_CWSR */ +#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SCM_PPMRH */ +#define MCF_SCM_PPMRH_CDPORTS (0x00000001) +#define MCF_SCM_PPMRH_CDEPORT (0x00000002) +#define MCF_SCM_PPMRH_CDPIT0 (0x00000008) +#define MCF_SCM_PPMRH_CDPIT1 (0x00000010) +#define MCF_SCM_PPMRH_CDCAN (0x00000020) +#define MCF_SCM_PPMRH_CDADC (0x00000080) +#define MCF_SCM_PPMRH_CDGPT (0x00000100) +#define MCF_SCM_PPMRH_CDPWN (0x00000200) +#define MCF_SCM_PPMRH_CDFCAN (0x00000400) +#define MCF_SCM_PPMRH_CDCFM (0x00000800) + +/* Bit definitions and macros for MCF_SCM_PPMRL */ +#define MCF_SCM_PPMRL_CDG (0x00000002) +#define MCF_SCM_PPMRL_CDEIM (0x00000008) +#define MCF_SCM_PPMRL_CDDMA (0x00000010) +#define MCF_SCM_PPMRL_CDUART0 (0x00000020) +#define MCF_SCM_PPMRL_CDUART1 (0x00000040) +#define MCF_SCM_PPMRL_CDUART2 (0x00000080) +#define MCF_SCM_PPMRL_CDI2C0 (0x00000200) +#define MCF_SCM_PPMRL_CDI2C1 (0x00000800) +#define MCF_SCM_PPMRL_CDQSPI (0x00000400) +#define MCF_SCM_PPMRL_CDDTIM0 (0x00002000) +#define MCF_SCM_PPMRL_CDDTIM1 (0x00004000) +#define MCF_SCM_PPMRL_CDDTIM2 (0x00008000) +#define MCF_SCM_PPMRL_CDDTIM3 (0x00010000) +#define MCF_SCM_PPMRL_CDINTC0 (0x00020000) +#define MCF_SCM_PPMRL_CDINTC1 (0x00040000) +#define MCF_SCM_PPMRL_CDFEC (0x00200000) + +/* Bit definitions and macros for MCF_SCM_MPARK */ +#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_MPARK_PRKLAST (0x00001000) +#define MCF_SCM_MPARK_TIMEOUT (0x00002000) +#define MCF_SCM_MPARK_FIXED (0x00004000) +#define MCF_SCM_MPARK_M0PRTY(x) (((x)&0x00000003)<<18) +#define MCF_SCM_MPARK_M2PRTY(x) (((x)&0x00000003)<<20) +#define MCF_SCM_MPARK_M3PRTY(x) (((x)&0x00000003)<<22) +#define MCF_SCM_MPARK_BCR24BIT (0x01000000) +#define MCF_SCM_MPARK_M2_P_EN (0x02000000) + +/* Bit definitions and macros for MCF_SCM_PPMRS */ +#define MCF_SCM_PPMRS_DISABLE_ALL (64) +#define MCF_SCM_PPMRS_DISABLE_CFM (43) +#define MCF_SCM_PPMRS_DISABLE_CAN (42) +#define MCF_SCM_PPMRS_DISABLE_PWM (41) +#define MCF_SCM_PPMRS_DISABLE_GPT (40) +#define MCF_SCM_PPMRS_DISABLE_ADC (39) +#define MCF_SCM_PPMRS_DISABLE_PIT1 (36) +#define MCF_SCM_PPMRS_DISABLE_PIT0 (35) +#define MCF_SCM_PPMRS_DISABLE_EPORT (33) +#define MCF_SCM_PPMRS_DISABLE_PORTS (32) +#define MCF_SCM_PPMRS_DISABLE_INTC (17) +#define MCF_SCM_PPMRS_DISABLE_DTIM3 (16) +#define MCF_SCM_PPMRS_DISABLE_DTIM2 (15) +#define MCF_SCM_PPMRS_DISABLE_DTIM1 (14) +#define MCF_SCM_PPMRS_DISABLE_DTIM0 (13) +#define MCF_SCM_PPMRS_DISABLE_QSPI (10) +#define MCF_SCM_PPMRS_DISABLE_I2C (9) +#define MCF_SCM_PPMRS_DISABLE_UART2 (7) +#define MCF_SCM_PPMRS_DISABLE_UART1 (6) +#define MCF_SCM_PPMRS_DISABLE_UART0 (5) +#define MCF_SCM_PPMRS_DISABLE_DMA (4) +#define MCF_SCM_PPMRS_SET_CDG (1) + +/* Bit definitions and macros for MCF_SCM_PPMRC */ +#define MCF_SCM_PPMRC_ENABLE_ALL (64) +#define MCF_SCM_PPMRC_ENABLE_CFM (43) +#define MCF_SCM_PPMRC_ENABLE_CAN (42) +#define MCF_SCM_PPMRC_ENABLE_PWM (41) +#define MCF_SCM_PPMRC_ENABLE_GPT (40) +#define MCF_SCM_PPMRC_ENABLE_ADC (39) +#define MCF_SCM_PPMRC_ENABLE_PIT1 (36) +#define MCF_SCM_PPMRC_ENABLE_PIT0 (35) +#define MCF_SCM_PPMRC_ENABLE_EPORT (33) +#define MCF_SCM_PPMRC_ENABLE_PORTS (32) +#define MCF_SCM_PPMRC_ENABLE_INTC (17) +#define MCF_SCM_PPMRC_ENABLE_DTIM3 (16) +#define MCF_SCM_PPMRC_ENABLE_DTIM2 (15) +#define MCF_SCM_PPMRC_ENABLE_DTIM1 (14) +#define MCF_SCM_PPMRC_ENABLE_DTIM0 (13) +#define MCF_SCM_PPMRC_ENABLE_QSPI (10) +#define MCF_SCM_PPMRC_ENABLE_I2C (9) +#define MCF_SCM_PPMRC_ENABLE_UART2 (7) +#define MCF_SCM_PPMRC_ENABLE_UART1 (6) +#define MCF_SCM_PPMRC_ENABLE_UART0 (5) +#define MCF_SCM_PPMRC_ENABLE_DMA (4) +#define MCF_SCM_PPMRC_CLEAR_CDG (1) + + +/********************************************************************* +* +* Power Management Module (PMM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PMM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) +#define MCF_PMM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) +#define MCF_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) +#define MCF_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) + +/* Bit definitions and macros for MCF_PMM_PPMRH */ +#define MCF_PMM_PPMRH_CDPORTS (0x00000001) +#define MCF_PMM_PPMRH_CDEPORT (0x00000002) +#define MCF_PMM_PPMRH_CDPIT0 (0x00000008) +#define MCF_PMM_PPMRH_CDPIT1 (0x00000010) +#define MCF_PMM_PPMRH_CDADC (0x00000080) +#define MCF_PMM_PPMRH_CDGPT (0x00000100) +#define MCF_PMM_PPMRH_CDPWM (0x00000200) +#define MCF_PMM_PPMRH_CDFCAN (0x00000400) +#define MCF_PMM_PPMRH_CDCFM (0x00000800) + +/* Bit definitions and macros for MCF_PMM_PPMRL */ +#define MCF_PMM_PPMRL_CDG (0x00000002) +#define MCF_PMM_PPMRL_CDEIM (0x00000008) +#define MCF_PMM_PPMRL_CDDMA (0x00000010) +#define MCF_PMM_PPMRL_CDUART0 (0x00000020) +#define MCF_PMM_PPMRL_CDUART1 (0x00000040) +#define MCF_PMM_PPMRL_CDUART2 (0x00000080) +#define MCF_PMM_PPMRL_CDI2C (0x00000200) +#define MCF_PMM_PPMRL_CDQSPI (0x00000400) +#define MCF_PMM_PPMRL_CDDTIM0 (0x00002000) +#define MCF_PMM_PPMRL_CDDTIM1 (0x00004000) +#define MCF_PMM_PPMRL_CDDTIM2 (0x00008000) +#define MCF_PMM_PPMRL_CDDTIM3 (0x00010000) +#define MCF_PMM_PPMRL_CDINTC0 (0x00020000) + +/* Bit definitions and macros for MCF_PMM_LPICR */ +#define MCF_PMM_LPICR_XIPL(x) (((x)&0x07)<<4) +#define MCF_PMM_LPICR_ENBSTOP (0x80) + +/* Bit definitions and macros for MCF_PMM_LPCR */ +#define MCF_PMM_LPCR_LVDSE (0x02) +#define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF_PMM_LPCR_LPMD_STOP (0xC0) +#define MCF_PMM_LPCR_LPMD_WAIT (0x80) +#define MCF_PMM_LPCR_LPMD_DOZE (0x40) +#define MCF_PMM_LPCR_LPMD_RUN (0x00) + + +/********************************************************************* +* +* DMA Controller Module (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DMA_DMAREQC (*(vuint32*)(&__IPSBAR[0x000014])) +#define MCF_DMA_SAR0 (*(vuint32*)(&__IPSBAR[0x000100])) +#define MCF_DMA_SAR1 (*(vuint32*)(&__IPSBAR[0x000110])) +#define MCF_DMA_SAR2 (*(vuint32*)(&__IPSBAR[0x000120])) +#define MCF_DMA_SAR3 (*(vuint32*)(&__IPSBAR[0x000130])) +#define MCF_DMA_SAR(x) (*(vuint32*)(&__IPSBAR[0x000100+((x)*0x010)])) +#define MCF_DMA_DAR0 (*(vuint32*)(&__IPSBAR[0x000104])) +#define MCF_DMA_DAR1 (*(vuint32*)(&__IPSBAR[0x000114])) +#define MCF_DMA_DAR2 (*(vuint32*)(&__IPSBAR[0x000124])) +#define MCF_DMA_DAR3 (*(vuint32*)(&__IPSBAR[0x000134])) +#define MCF_DMA_DAR(x) (*(vuint32*)(&__IPSBAR[0x000104+((x)*0x010)])) +#define MCF_DMA_DSR0 (*(vuint8 *)(&__IPSBAR[0x000108])) +#define MCF_DMA_DSR1 (*(vuint8 *)(&__IPSBAR[0x000118])) +#define MCF_DMA_DSR2 (*(vuint8 *)(&__IPSBAR[0x000128])) +#define MCF_DMA_DSR3 (*(vuint8 *)(&__IPSBAR[0x000138])) +#define MCF_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x000108+((x)*0x010)])) +#define MCF_DMA_BCR0 (*(vuint32*)(&__IPSBAR[0x000108])) +#define MCF_DMA_BCR1 (*(vuint32*)(&__IPSBAR[0x000118])) +#define MCF_DMA_BCR2 (*(vuint32*)(&__IPSBAR[0x000128])) +#define MCF_DMA_BCR3 (*(vuint32*)(&__IPSBAR[0x000138])) +#define MCF_DMA_BCR(x) (*(vuint32*)(&__IPSBAR[0x000108+((x)*0x010)])) +#define MCF_DMA_DCR0 (*(vuint32*)(&__IPSBAR[0x00010C])) +#define MCF_DMA_DCR1 (*(vuint32*)(&__IPSBAR[0x00011C])) +#define MCF_DMA_DCR2 (*(vuint32*)(&__IPSBAR[0x00012C])) +#define MCF_DMA_DCR3 (*(vuint32*)(&__IPSBAR[0x00013C])) +#define MCF_DMA_DCR(x) (*(vuint32*)(&__IPSBAR[0x00010C+((x)*0x010)])) + +/* Bit definitions and macros for MCF_DMA_DMAREQC */ +#define MCF_DMA_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) +#define MCF_DMA_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) +#define MCF_DMA_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) +#define MCF_DMA_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) +#define MCF_DMA_DMAREQC_DMAREQC_EXT(x) (((x)&0x0000000F)<<16) + +/* Bit definitions and macros for MCF_DMA_SAR */ +#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DAR */ +#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DSR */ +#define MCF_DMA_DSR_DONE (0x01) +#define MCF_DMA_DSR_BSY (0x02) +#define MCF_DMA_DSR_REQ (0x04) +#define MCF_DMA_DSR_BED (0x10) +#define MCF_DMA_DSR_BES (0x20) +#define MCF_DMA_DSR_CE (0x40) + +/* Bit definitions and macros for MCF_DMA_BCR */ +#define MCF_DMA_BCR_BCR(x) (((x)&0x00FFFFFF)<<0) +#define MCF_DMA_BCR_DSR(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_DMA_DCR */ +#define MCF_DMA_DCR_LCH2(x) (((x)&0x00000003)<<0) +#define MCF_DMA_DCR_LCH1(x) (((x)&0x00000003)<<2) +#define MCF_DMA_DCR_LINKCC(x) (((x)&0x00000003)<<4) +#define MCF_DMA_DCR_D_REQ (0x00000080) +#define MCF_DMA_DCR_DMOD(x) (((x)&0x0000000F)<<8) +#define MCF_DMA_DCR_SMOD(x) (((x)&0x0000000F)<<12) +#define MCF_DMA_DCR_START (0x00010000) +#define MCF_DMA_DCR_DSIZE(x) (((x)&0x00000003)<<17) +#define MCF_DMA_DCR_DINC (0x00080000) +#define MCF_DMA_DCR_SSIZE(x) (((x)&0x00000003)<<20) +#define MCF_DMA_DCR_SINC (0x00400000) +#define MCF_DMA_DCR_BWC(x) (((x)&0x00000007)<<25) +#define MCF_DMA_DCR_AA (0x10000000) +#define MCF_DMA_DCR_CS (0x20000000) +#define MCF_DMA_DCR_EEXT (0x40000000) +#define MCF_DMA_DCR_INT (0x80000000) +#define MCF_DMA_DCR_BWC_16K (0x1) +#define MCF_DMA_DCR_BWC_32K (0x2) +#define MCF_DMA_DCR_BWC_64K (0x3) +#define MCF_DMA_DCR_BWC_128K (0x4) +#define MCF_DMA_DCR_BWC_256K (0x5) +#define MCF_DMA_DCR_BWC_512K (0x6) +#define MCF_DMA_DCR_BWC_1024K (0x7) +#define MCF_DMA_DCR_DMOD_DIS (0x0) +#define MCF_DMA_DCR_DMOD_16 (0x1) +#define MCF_DMA_DCR_DMOD_32 (0x2) +#define MCF_DMA_DCR_DMOD_64 (0x3) +#define MCF_DMA_DCR_DMOD_128 (0x4) +#define MCF_DMA_DCR_DMOD_256 (0x5) +#define MCF_DMA_DCR_DMOD_512 (0x6) +#define MCF_DMA_DCR_DMOD_1K (0x7) +#define MCF_DMA_DCR_DMOD_2K (0x8) +#define MCF_DMA_DCR_DMOD_4K (0x9) +#define MCF_DMA_DCR_DMOD_8K (0xA) +#define MCF_DMA_DCR_DMOD_16K (0xB) +#define MCF_DMA_DCR_DMOD_32K (0xC) +#define MCF_DMA_DCR_DMOD_64K (0xD) +#define MCF_DMA_DCR_DMOD_128K (0xE) +#define MCF_DMA_DCR_DMOD_256K (0xF) +#define MCF_DMA_DCR_SMOD_DIS (0x0) +#define MCF_DMA_DCR_SMOD_16 (0x1) +#define MCF_DMA_DCR_SMOD_32 (0x2) +#define MCF_DMA_DCR_SMOD_64 (0x3) +#define MCF_DMA_DCR_SMOD_128 (0x4) +#define MCF_DMA_DCR_SMOD_256 (0x5) +#define MCF_DMA_DCR_SMOD_512 (0x6) +#define MCF_DMA_DCR_SMOD_1K (0x7) +#define MCF_DMA_DCR_SMOD_2K (0x8) +#define MCF_DMA_DCR_SMOD_4K (0x9) +#define MCF_DMA_DCR_SMOD_8K (0xA) +#define MCF_DMA_DCR_SMOD_16K (0xB) +#define MCF_DMA_DCR_SMOD_32K (0xC) +#define MCF_DMA_DCR_SMOD_64K (0xD) +#define MCF_DMA_DCR_SMOD_128K (0xE) +#define MCF_DMA_DCR_SMOD_256K (0xF) +#define MCF_DMA_DCR_SSIZE_LONG (0x0) +#define MCF_DMA_DCR_SSIZE_BYTE (0x1) +#define MCF_DMA_DCR_SSIZE_WORD (0x2) +#define MCF_DMA_DCR_SSIZE_LINE (0x3) +#define MCF_DMA_DCR_DSIZE_LONG (0x0) +#define MCF_DMA_DCR_DSIZE_BYTE (0x1) +#define MCF_DMA_DCR_DSIZE_WORD (0x2) +#define MCF_DMA_DCR_DSIZE_LINE (0x3) +#define MCF_DMA_DCR_LCH1_CH0 (0x0) +#define MCF_DMA_DCR_LCH1_CH1 (0x1) +#define MCF_DMA_DCR_LCH1_CH2 (0x2) +#define MCF_DMA_DCR_LCH1_CH3 (0x3) +#define MCF_DMA_DCR_LCH2_CH0 (0x0) +#define MCF_DMA_DCR_LCH2_CH1 (0x1) +#define MCF_DMA_DCR_LCH2_CH2 (0x2) +#define MCF_DMA_DCR_LCH2_CH3 (0x3) + + +/********************************************************************* +* +* Universal Asynchronous Receiver Transmitter (UART) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_UART0_UMR (*(vuint8 *)(&__IPSBAR[0x000200])) +#define MCF_UART0_USR (*(vuint8 *)(&__IPSBAR[0x000204])) +#define MCF_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x000204])) +#define MCF_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x000208])) +#define MCF_UART0_URB (*(vuint8 *)(&__IPSBAR[0x00020C])) +#define MCF_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x00020C])) +#define MCF_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x000210])) +#define MCF_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x000210])) +#define MCF_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x000214])) +#define MCF_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x000214])) +#define MCF_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x000218])) +#define MCF_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x00021C])) +#define MCF_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x000234])) +#define MCF_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x000238])) +#define MCF_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x00023C])) +#define MCF_UART1_UMR (*(vuint8 *)(&__IPSBAR[0x000240])) +#define MCF_UART1_USR (*(vuint8 *)(&__IPSBAR[0x000244])) +#define MCF_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x000244])) +#define MCF_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x000248])) +#define MCF_UART1_URB (*(vuint8 *)(&__IPSBAR[0x00024C])) +#define MCF_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x00024C])) +#define MCF_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x000250])) +#define MCF_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x000250])) +#define MCF_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x000254])) +#define MCF_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x000254])) +#define MCF_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x000258])) +#define MCF_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x00025C])) +#define MCF_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x000274])) +#define MCF_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x000278])) +#define MCF_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x00027C])) +#define MCF_UART2_UMR (*(vuint8 *)(&__IPSBAR[0x000280])) +#define MCF_UART2_USR (*(vuint8 *)(&__IPSBAR[0x000284])) +#define MCF_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x000284])) +#define MCF_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x000288])) +#define MCF_UART2_URB (*(vuint8 *)(&__IPSBAR[0x00028C])) +#define MCF_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x00028C])) +#define MCF_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x000290])) +#define MCF_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x000290])) +#define MCF_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x000294])) +#define MCF_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x000294])) +#define MCF_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x000298])) +#define MCF_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x00029C])) +#define MCF_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x0002B4])) +#define MCF_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x0002B8])) +#define MCF_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x0002BC])) +#define MCF_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x000200+((x)*0x040)])) +#define MCF_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) +#define MCF_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) +#define MCF_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x000208+((x)*0x040)])) +#define MCF_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) +#define MCF_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) +#define MCF_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) +#define MCF_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) +#define MCF_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) +#define MCF_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) +#define MCF_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x000218+((x)*0x040)])) +#define MCF_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x00021C+((x)*0x040)])) +#define MCF_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x000234+((x)*0x040)])) +#define MCF_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x000238+((x)*0x040)])) +#define MCF_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x00023C+((x)*0x040)])) + +/* Bit definitions and macros for MCF_UART_UMR */ +#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) +#define MCF_UART_UMR_PT (0x04) +#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) +#define MCF_UART_UMR_ERR (0x20) +#define MCF_UART_UMR_RXIRQ (0x40) +#define MCF_UART_UMR_RXRTS (0x80) +#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) +#define MCF_UART_UMR_TXCTS (0x10) +#define MCF_UART_UMR_TXRTS (0x20) +#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) +#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) +#define MCF_UART_UMR_PM_MULTI_DATA (0x18) +#define MCF_UART_UMR_PM_NONE (0x10) +#define MCF_UART_UMR_PM_FORCE_HI (0x0C) +#define MCF_UART_UMR_PM_FORCE_LO (0x08) +#define MCF_UART_UMR_PM_ODD (0x04) +#define MCF_UART_UMR_PM_EVEN (0x00) +#define MCF_UART_UMR_BC_5 (0x00) +#define MCF_UART_UMR_BC_6 (0x01) +#define MCF_UART_UMR_BC_7 (0x02) +#define MCF_UART_UMR_BC_8 (0x03) +#define MCF_UART_UMR_CM_NORMAL (0x00) +#define MCF_UART_UMR_CM_ECHO (0x40) +#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) +#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) +#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) +#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) +#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for MCF_UART_USR */ +#define MCF_UART_USR_RXRDY (0x01) +#define MCF_UART_USR_FFULL (0x02) +#define MCF_UART_USR_TXRDY (0x04) +#define MCF_UART_USR_TXEMP (0x08) +#define MCF_UART_USR_OE (0x10) +#define MCF_UART_USR_PE (0x20) +#define MCF_UART_USR_FE (0x40) +#define MCF_UART_USR_RB (0x80) + +/* Bit definitions and macros for MCF_UART_UCSR */ +#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) +#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) +#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) +#define MCF_UART_UCSR_RCS_CTM16 (0xE0) +#define MCF_UART_UCSR_RCS_CTM (0xF0) +#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) +#define MCF_UART_UCSR_TCS_CTM16 (0x0E) +#define MCF_UART_UCSR_TCS_CTM (0x0F) + +/* Bit definitions and macros for MCF_UART_UCR */ +#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) +#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) +#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) +#define MCF_UART_UCR_NONE (0x00) +#define MCF_UART_UCR_STOP_BREAK (0x70) +#define MCF_UART_UCR_START_BREAK (0x60) +#define MCF_UART_UCR_BKCHGINT (0x50) +#define MCF_UART_UCR_RESET_ERROR (0x40) +#define MCF_UART_UCR_RESET_TX (0x30) +#define MCF_UART_UCR_RESET_RX (0x20) +#define MCF_UART_UCR_RESET_MR (0x10) +#define MCF_UART_UCR_TX_DISABLED (0x08) +#define MCF_UART_UCR_TX_ENABLED (0x04) +#define MCF_UART_UCR_RX_DISABLED (0x02) +#define MCF_UART_UCR_RX_ENABLED (0x01) + +/* Bit definitions and macros for MCF_UART_UIPCR */ +#define MCF_UART_UIPCR_CTS (0x01) +#define MCF_UART_UIPCR_COS (0x10) + +/* Bit definitions and macros for MCF_UART_UACR */ +#define MCF_UART_UACR_IEC (0x01) + +/* Bit definitions and macros for MCF_UART_UISR */ +#define MCF_UART_UISR_TXRDY (0x01) +#define MCF_UART_UISR_RXRDY_FU (0x02) +#define MCF_UART_UISR_DB (0x04) +#define MCF_UART_UISR_RXFTO (0x08) +#define MCF_UART_UISR_TXFIFO (0x10) +#define MCF_UART_UISR_RXFIFO (0x20) +#define MCF_UART_UISR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UIMR */ +#define MCF_UART_UIMR_TXRDY (0x01) +#define MCF_UART_UIMR_RXRDY_FU (0x02) +#define MCF_UART_UIMR_DB (0x04) +#define MCF_UART_UIMR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UIP */ +#define MCF_UART_UIP_CTS (0x01) + +/* Bit definitions and macros for MCF_UART_UOP1 */ +#define MCF_UART_UOP1_RTS (0x01) + +/* Bit definitions and macros for MCF_UART_UOP0 */ +#define MCF_UART_UOP0_RTS (0x01) + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2AR (*(vuint8 *)(&__IPSBAR[0x000300])) +#define MCF_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x000304])) +#define MCF_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x000308])) +#define MCF_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x00030C])) +#define MCF_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x000310])) + +/* Bit definitions and macros for MCF_I2C_I2AR */ +#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x04) +#define MCF_I2C_I2CR_TXAK (0x08) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x01) +#define MCF_I2C_I2SR_IIF (0x02) +#define MCF_I2C_I2SR_SRW (0x04) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2C_I2ICR_IE (0x01) +#define MCF_I2C_I2ICR_RE (0x02) +#define MCF_I2C_I2ICR_TE (0x04) +#define MCF_I2C_I2ICR_BNBE (0x08) + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_QSPI_QMR (*(vuint16*)(&__IPSBAR[0x000340])) +#define MCF_QSPI_QDLYR (*(vuint16*)(&__IPSBAR[0x000344])) +#define MCF_QSPI_QWR (*(vuint16*)(&__IPSBAR[0x000348])) +#define MCF_QSPI_QIR (*(vuint16*)(&__IPSBAR[0x00034C])) +#define MCF_QSPI_QAR (*(vuint16*)(&__IPSBAR[0x000350])) +#define MCF_QSPI_QDR (*(vuint16*)(&__IPSBAR[0x000354])) + +/* Bit definitions and macros for MCF_QSPI_QMR */ +#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) +#define MCF_QSPI_QMR_CPHA (0x0100) +#define MCF_QSPI_QMR_CPOL (0x0200) +#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define MCF_QSPI_QMR_DOHIE (0x4000) +#define MCF_QSPI_QMR_MSTR (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QDLYR */ +#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) +#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define MCF_QSPI_QDLYR_SPE (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QWR */ +#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) +#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define MCF_QSPI_QWR_CSIV (0x1000) +#define MCF_QSPI_QWR_WRTO (0x2000) +#define MCF_QSPI_QWR_WREN (0x4000) +#define MCF_QSPI_QWR_HALT (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QIR */ +#define MCF_QSPI_QIR_SPIF (0x0001) +#define MCF_QSPI_QIR_ABRT (0x0004) +#define MCF_QSPI_QIR_WCEF (0x0008) +#define MCF_QSPI_QIR_SPIFE (0x0100) +#define MCF_QSPI_QIR_ABRTE (0x0400) +#define MCF_QSPI_QIR_WCEFE (0x0800) +#define MCF_QSPI_QIR_ABRTL (0x1000) +#define MCF_QSPI_QIR_ABRTB (0x4000) +#define MCF_QSPI_QIR_WCEFB (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QAR */ +#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) + +/* Bit definitions and macros for MCF_QSPI_QDR */ +#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0) + +/********************************************************************* +* +* DMA Timers (DTIM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x000400])) +#define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x000402])) +#define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x000403])) +#define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x000404])) +#define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x000408])) +#define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x00040C])) +#define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x000440])) +#define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x000442])) +#define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x000443])) +#define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x000444])) +#define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x000448])) +#define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x00044C])) +#define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x000480])) +#define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x000482])) +#define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x000483])) +#define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x000484])) +#define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x000488])) +#define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x00048C])) +#define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x0004C0])) +#define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x0004C2])) +#define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x0004C3])) +#define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x0004C4])) +#define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x0004C8])) +#define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x0004CC])) +#define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x000400+((x)*0x040)])) +#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x000402+((x)*0x040)])) +#define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x000403+((x)*0x040)])) +#define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x000404+((x)*0x040)])) +#define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x000408+((x)*0x040)])) +#define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x00040C+((x)*0x040)])) + +/* Bit definitions and macros for MCF_DTIM_DTMR */ +#define MCF_DTIM_DTMR_RST (0x0001) +#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) +#define MCF_DTIM_DTMR_FRR (0x0008) +#define MCF_DTIM_DTMR_ORRI (0x0010) +#define MCF_DTIM_DTMR_OM (0x0020) +#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) +#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) +#define MCF_DTIM_DTMR_CE_ANY (0x00C0) +#define MCF_DTIM_DTMR_CE_FALL (0x0080) +#define MCF_DTIM_DTMR_CE_RISE (0x0040) +#define MCF_DTIM_DTMR_CE_NONE (0x0000) +#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) +#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) +#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) +#define MCF_DTIM_DTMR_CLK_STOP (0x0000) + +/* Bit definitions and macros for MCF_DTIM_DTXMR */ +#define MCF_DTIM_DTXMR_MODE16 (0x01) +#define MCF_DTIM_DTXMR_DMAEN (0x80) + +/* Bit definitions and macros for MCF_DTIM_DTER */ +#define MCF_DTIM_DTER_CAP (0x01) +#define MCF_DTIM_DTER_REF (0x02) + +/* Bit definitions and macros for MCF_DTIM_DTRR */ +#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCR */ +#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCN */ +#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC0_IPRH (*(vuint32*)(&__IPSBAR[0x000C00])) +#define MCF_INTC0_IPRL (*(vuint32*)(&__IPSBAR[0x000C04])) +#define MCF_INTC0_IMRH (*(vuint32*)(&__IPSBAR[0x000C08])) +#define MCF_INTC0_IMRL (*(vuint32*)(&__IPSBAR[0x000C0C])) +#define MCF_INTC0_INTFRCH (*(vuint32*)(&__IPSBAR[0x000C10])) +#define MCF_INTC0_INTFRCL (*(vuint32*)(&__IPSBAR[0x000C14])) +#define MCF_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0x000C18])) +#define MCF_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000C19])) +#define MCF_INTC0_ICR1 (*(vuint8 *)(&__IPSBAR[0x000C41])) +#define MCF_INTC0_ICR2 (*(vuint8 *)(&__IPSBAR[0x000C42])) +#define MCF_INTC0_ICR3 (*(vuint8 *)(&__IPSBAR[0x000C43])) +#define MCF_INTC0_ICR4 (*(vuint8 *)(&__IPSBAR[0x000C44])) +#define MCF_INTC0_ICR5 (*(vuint8 *)(&__IPSBAR[0x000C45])) +#define MCF_INTC0_ICR6 (*(vuint8 *)(&__IPSBAR[0x000C46])) +#define MCF_INTC0_ICR7 (*(vuint8 *)(&__IPSBAR[0x000C47])) +#define MCF_INTC0_ICR8 (*(vuint8 *)(&__IPSBAR[0x000C48])) +#define MCF_INTC0_ICR9 (*(vuint8 *)(&__IPSBAR[0x000C49])) +#define MCF_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0x000C4A])) +#define MCF_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0x000C4B])) +#define MCF_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0x000C4C])) +#define MCF_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0x000C4D])) +#define MCF_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0x000C4E])) +#define MCF_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0x000C4F])) +#define MCF_INTC0_ICR16 (*(vuint8 *)(&__IPSBAR[0x000C50])) +#define MCF_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0x000C51])) +#define MCF_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0x000C52])) +#define MCF_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0x000C53])) +#define MCF_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0x000C54])) +#define MCF_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0x000C55])) +#define MCF_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0x000C56])) +#define MCF_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0x000C57])) +#define MCF_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0x000C58])) +#define MCF_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0x000C59])) +#define MCF_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0x000C5A])) +#define MCF_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0x000C5B])) +#define MCF_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0x000C5C])) +#define MCF_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0x000C5D])) +#define MCF_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0x000C5E])) +#define MCF_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0x000C5F])) +#define MCF_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0x000C60])) +#define MCF_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0x000C61])) +#define MCF_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0x000C62])) +#define MCF_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0x000C63])) +#define MCF_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0x000C64])) +#define MCF_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0x000C65])) +#define MCF_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0x000C66])) +#define MCF_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0x000C67])) +#define MCF_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0x000C68])) +#define MCF_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0x000C69])) +#define MCF_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0x000C6A])) +#define MCF_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0x000C6B])) +#define MCF_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0x000C6C])) +#define MCF_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0x000C6D])) +#define MCF_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0x000C6E])) +#define MCF_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0x000C6F])) +#define MCF_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0x000C70])) +#define MCF_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0x000C71])) +#define MCF_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0x000C72])) +#define MCF_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0x000C73])) +#define MCF_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0x000C74])) +#define MCF_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0x000C75])) +#define MCF_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0x000C76])) +#define MCF_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0x000C77])) +#define MCF_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0x000C78])) +#define MCF_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0x000C79])) +#define MCF_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0x000C7A])) +#define MCF_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0x000C7B])) +#define MCF_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0x000C7C])) +#define MCF_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0x000C7D])) +#define MCF_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0x000C7E])) +#define MCF_INTC0_ICR63 (*(vuint8 *)(&__IPSBAR[0x000C7F])) +#define MCF_INTC0_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x-1)*0x001)])) +#define MCF_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0x000CE0])) +#define MCF_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0x000CE4])) +#define MCF_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0x000CE8])) +#define MCF_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0x000CEC])) +#define MCF_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0x000CF0])) +#define MCF_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0x000CF4])) +#define MCF_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0x000CF8])) +#define MCF_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0x000CFC])) +#define MCF_INTC0_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x-1)*0x004)])) +#define MCF_INTC1_IPRH (*(vuint32*)(&__IPSBAR[0x000D00])) +#define MCF_INTC1_IPRL (*(vuint32*)(&__IPSBAR[0x000D04])) +#define MCF_INTC1_IMRH (*(vuint32*)(&__IPSBAR[0x000D08])) +#define MCF_INTC1_IMRL (*(vuint32*)(&__IPSBAR[0x000D0C])) +#define MCF_INTC1_INTFRCH (*(vuint32*)(&__IPSBAR[0x000D10])) +#define MCF_INTC1_INTFRCL (*(vuint32*)(&__IPSBAR[0x000D14])) +#define MCF_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0x000D18])) +#define MCF_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000D19])) +#define MCF_INTC1_ICR1 (*(vuint8 *)(&__IPSBAR[0x000D41])) +#define MCF_INTC1_ICR2 (*(vuint8 *)(&__IPSBAR[0x000D42])) +#define MCF_INTC1_ICR3 (*(vuint8 *)(&__IPSBAR[0x000D43])) +#define MCF_INTC1_ICR4 (*(vuint8 *)(&__IPSBAR[0x000D44])) +#define MCF_INTC1_ICR5 (*(vuint8 *)(&__IPSBAR[0x000D45])) +#define MCF_INTC1_ICR6 (*(vuint8 *)(&__IPSBAR[0x000D46])) +#define MCF_INTC1_ICR7 (*(vuint8 *)(&__IPSBAR[0x000D47])) +#define MCF_INTC1_ICR8 (*(vuint8 *)(&__IPSBAR[0x000D48])) +#define MCF_INTC1_ICR9 (*(vuint8 *)(&__IPSBAR[0x000D49])) +#define MCF_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0x000D4A])) +#define MCF_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0x000D4B])) +#define MCF_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0x000D4C])) +#define MCF_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0x000D4D])) +#define MCF_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0x000D4E])) +#define MCF_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0x000D4F])) +#define MCF_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0x000D50])) +#define MCF_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0x000D51])) +#define MCF_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0x000D52])) +#define MCF_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0x000D53])) +#define MCF_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0x000D54])) +#define MCF_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0x000D55])) +#define MCF_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0x000D56])) +#define MCF_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0x000D57])) +#define MCF_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0x000D58])) +#define MCF_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0x000D59])) +#define MCF_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0x000D5A])) +#define MCF_INTC1_ICR27 (*(vuint8 *)(&__IPSBAR[0x000D5B])) +#define MCF_INTC1_ICR28 (*(vuint8 *)(&__IPSBAR[0x000D5C])) +#define MCF_INTC1_ICR29 (*(vuint8 *)(&__IPSBAR[0x000D5D])) +#define MCF_INTC1_ICR30 (*(vuint8 *)(&__IPSBAR[0x000D5E])) +#define MCF_INTC1_ICR31 (*(vuint8 *)(&__IPSBAR[0x000D5F])) +#define MCF_INTC1_ICR32 (*(vuint8 *)(&__IPSBAR[0x000D60])) +#define MCF_INTC1_ICR33 (*(vuint8 *)(&__IPSBAR[0x000D61])) +#define MCF_INTC1_ICR34 (*(vuint8 *)(&__IPSBAR[0x000D62])) +#define MCF_INTC1_ICR35 (*(vuint8 *)(&__IPSBAR[0x000D63])) +#define MCF_INTC1_ICR36 (*(vuint8 *)(&__IPSBAR[0x000D64])) +#define MCF_INTC1_ICR37 (*(vuint8 *)(&__IPSBAR[0x000D65])) +#define MCF_INTC1_ICR38 (*(vuint8 *)(&__IPSBAR[0x000D66])) +#define MCF_INTC1_ICR39 (*(vuint8 *)(&__IPSBAR[0x000D67])) +#define MCF_INTC1_ICR40 (*(vuint8 *)(&__IPSBAR[0x000D68])) +#define MCF_INTC1_ICR41 (*(vuint8 *)(&__IPSBAR[0x000D69])) +#define MCF_INTC1_ICR42 (*(vuint8 *)(&__IPSBAR[0x000D6A])) +#define MCF_INTC1_ICR43 (*(vuint8 *)(&__IPSBAR[0x000D6B])) +#define MCF_INTC1_ICR44 (*(vuint8 *)(&__IPSBAR[0x000D6C])) +#define MCF_INTC1_ICR45 (*(vuint8 *)(&__IPSBAR[0x000D6D])) +#define MCF_INTC1_ICR46 (*(vuint8 *)(&__IPSBAR[0x000D6E])) +#define MCF_INTC1_ICR47 (*(vuint8 *)(&__IPSBAR[0x000D6F])) +#define MCF_INTC1_ICR48 (*(vuint8 *)(&__IPSBAR[0x000D70])) +#define MCF_INTC1_ICR49 (*(vuint8 *)(&__IPSBAR[0x000D71])) +#define MCF_INTC1_ICR50 (*(vuint8 *)(&__IPSBAR[0x000D72])) +#define MCF_INTC1_ICR51 (*(vuint8 *)(&__IPSBAR[0x000D73])) +#define MCF_INTC1_ICR52 (*(vuint8 *)(&__IPSBAR[0x000D74])) +#define MCF_INTC1_ICR53 (*(vuint8 *)(&__IPSBAR[0x000D75])) +#define MCF_INTC1_ICR54 (*(vuint8 *)(&__IPSBAR[0x000D76])) +#define MCF_INTC1_ICR55 (*(vuint8 *)(&__IPSBAR[0x000D77])) +#define MCF_INTC1_ICR56 (*(vuint8 *)(&__IPSBAR[0x000D78])) +#define MCF_INTC1_ICR57 (*(vuint8 *)(&__IPSBAR[0x000D79])) +#define MCF_INTC1_ICR58 (*(vuint8 *)(&__IPSBAR[0x000D7A])) +#define MCF_INTC1_ICR59 (*(vuint8 *)(&__IPSBAR[0x000D7B])) +#define MCF_INTC1_ICR60 (*(vuint8 *)(&__IPSBAR[0x000D7C])) +#define MCF_INTC1_ICR61 (*(vuint8 *)(&__IPSBAR[0x000D7D])) +#define MCF_INTC1_ICR62 (*(vuint8 *)(&__IPSBAR[0x000D7E])) +#define MCF_INTC1_ICR63 (*(vuint8 *)(&__IPSBAR[0x000D7F])) +#define MCF_INTC1_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000D41+((x-1)*0x001)])) +#define MCF_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0x000DE0])) +#define MCF_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0x000DE4])) +#define MCF_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0x000DE8])) +#define MCF_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0x000DEC])) +#define MCF_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0x000DF0])) +#define MCF_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0x000DF4])) +#define MCF_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0x000DF8])) +#define MCF_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0x000DFC])) +#define MCF_INTC1_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000DE4+((x-1)*0x004)])) +#define MCF_INTC_IPRH(x) (*(vuint32*)(&__IPSBAR[0x000C00+((x)*0x100)])) +#define MCF_INTC_IPRL(x) (*(vuint32*)(&__IPSBAR[0x000C04+((x)*0x100)])) +#define MCF_INTC_IMRH(x) (*(vuint32*)(&__IPSBAR[0x000C08+((x)*0x100)])) +#define MCF_INTC_IMRL(x) (*(vuint32*)(&__IPSBAR[0x000C0C+((x)*0x100)])) +#define MCF_INTC_INTFRCH(x) (*(vuint32*)(&__IPSBAR[0x000C10+((x)*0x100)])) +#define MCF_INTC_INTFRCL(x) (*(vuint32*)(&__IPSBAR[0x000C14+((x)*0x100)])) +#define MCF_INTC_IRLR(x) (*(vuint8 *)(&__IPSBAR[0x000C18+((x)*0x100)])) +#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(&__IPSBAR[0x000C19+((x)*0x100)])) +#define MCF_INTC_ICR1(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x)*0x100)])) +#define MCF_INTC_ICR2(x) (*(vuint8 *)(&__IPSBAR[0x000C42+((x)*0x100)])) +#define MCF_INTC_ICR3(x) (*(vuint8 *)(&__IPSBAR[0x000C43+((x)*0x100)])) +#define MCF_INTC_ICR4(x) (*(vuint8 *)(&__IPSBAR[0x000C44+((x)*0x100)])) +#define MCF_INTC_ICR5(x) (*(vuint8 *)(&__IPSBAR[0x000C45+((x)*0x100)])) +#define MCF_INTC_ICR6(x) (*(vuint8 *)(&__IPSBAR[0x000C46+((x)*0x100)])) +#define MCF_INTC_ICR7(x) (*(vuint8 *)(&__IPSBAR[0x000C47+((x)*0x100)])) +#define MCF_INTC_ICR8(x) (*(vuint8 *)(&__IPSBAR[0x000C48+((x)*0x100)])) +#define MCF_INTC_ICR9(x) (*(vuint8 *)(&__IPSBAR[0x000C49+((x)*0x100)])) +#define MCF_INTC_ICR10(x) (*(vuint8 *)(&__IPSBAR[0x000C4A+((x)*0x100)])) +#define MCF_INTC_ICR11(x) (*(vuint8 *)(&__IPSBAR[0x000C4B+((x)*0x100)])) +#define MCF_INTC_ICR12(x) (*(vuint8 *)(&__IPSBAR[0x000C4C+((x)*0x100)])) +#define MCF_INTC_ICR13(x) (*(vuint8 *)(&__IPSBAR[0x000C4D+((x)*0x100)])) +#define MCF_INTC_ICR14(x) (*(vuint8 *)(&__IPSBAR[0x000C4E+((x)*0x100)])) +#define MCF_INTC_ICR15(x) (*(vuint8 *)(&__IPSBAR[0x000C4F+((x)*0x100)])) +#define MCF_INTC_ICR16(x) (*(vuint8 *)(&__IPSBAR[0x000C50+((x)*0x100)])) +#define MCF_INTC_ICR17(x) (*(vuint8 *)(&__IPSBAR[0x000C51+((x)*0x100)])) +#define MCF_INTC_ICR18(x) (*(vuint8 *)(&__IPSBAR[0x000C52+((x)*0x100)])) +#define MCF_INTC_ICR19(x) (*(vuint8 *)(&__IPSBAR[0x000C53+((x)*0x100)])) +#define MCF_INTC_ICR20(x) (*(vuint8 *)(&__IPSBAR[0x000C54+((x)*0x100)])) +#define MCF_INTC_ICR21(x) (*(vuint8 *)(&__IPSBAR[0x000C55+((x)*0x100)])) +#define MCF_INTC_ICR22(x) (*(vuint8 *)(&__IPSBAR[0x000C56+((x)*0x100)])) +#define MCF_INTC_ICR23(x) (*(vuint8 *)(&__IPSBAR[0x000C57+((x)*0x100)])) +#define MCF_INTC_ICR24(x) (*(vuint8 *)(&__IPSBAR[0x000C58+((x)*0x100)])) +#define MCF_INTC_ICR25(x) (*(vuint8 *)(&__IPSBAR[0x000C59+((x)*0x100)])) +#define MCF_INTC_ICR26(x) (*(vuint8 *)(&__IPSBAR[0x000C5A+((x)*0x100)])) +#define MCF_INTC_ICR27(x) (*(vuint8 *)(&__IPSBAR[0x000C5B+((x)*0x100)])) +#define MCF_INTC_ICR28(x) (*(vuint8 *)(&__IPSBAR[0x000C5C+((x)*0x100)])) +#define MCF_INTC_ICR29(x) (*(vuint8 *)(&__IPSBAR[0x000C5D+((x)*0x100)])) +#define MCF_INTC_ICR30(x) (*(vuint8 *)(&__IPSBAR[0x000C5E+((x)*0x100)])) +#define MCF_INTC_ICR31(x) (*(vuint8 *)(&__IPSBAR[0x000C5F+((x)*0x100)])) +#define MCF_INTC_ICR32(x) (*(vuint8 *)(&__IPSBAR[0x000C60+((x)*0x100)])) +#define MCF_INTC_ICR33(x) (*(vuint8 *)(&__IPSBAR[0x000C61+((x)*0x100)])) +#define MCF_INTC_ICR34(x) (*(vuint8 *)(&__IPSBAR[0x000C62+((x)*0x100)])) +#define MCF_INTC_ICR35(x) (*(vuint8 *)(&__IPSBAR[0x000C63+((x)*0x100)])) +#define MCF_INTC_ICR36(x) (*(vuint8 *)(&__IPSBAR[0x000C64+((x)*0x100)])) +#define MCF_INTC_ICR37(x) (*(vuint8 *)(&__IPSBAR[0x000C65+((x)*0x100)])) +#define MCF_INTC_ICR38(x) (*(vuint8 *)(&__IPSBAR[0x000C66+((x)*0x100)])) +#define MCF_INTC_ICR39(x) (*(vuint8 *)(&__IPSBAR[0x000C67+((x)*0x100)])) +#define MCF_INTC_ICR40(x) (*(vuint8 *)(&__IPSBAR[0x000C68+((x)*0x100)])) +#define MCF_INTC_ICR41(x) (*(vuint8 *)(&__IPSBAR[0x000C69+((x)*0x100)])) +#define MCF_INTC_ICR42(x) (*(vuint8 *)(&__IPSBAR[0x000C6A+((x)*0x100)])) +#define MCF_INTC_ICR43(x) (*(vuint8 *)(&__IPSBAR[0x000C6B+((x)*0x100)])) +#define MCF_INTC_ICR44(x) (*(vuint8 *)(&__IPSBAR[0x000C6C+((x)*0x100)])) +#define MCF_INTC_ICR45(x) (*(vuint8 *)(&__IPSBAR[0x000C6D+((x)*0x100)])) +#define MCF_INTC_ICR46(x) (*(vuint8 *)(&__IPSBAR[0x000C6E+((x)*0x100)])) +#define MCF_INTC_ICR47(x) (*(vuint8 *)(&__IPSBAR[0x000C6F+((x)*0x100)])) +#define MCF_INTC_ICR48(x) (*(vuint8 *)(&__IPSBAR[0x000C70+((x)*0x100)])) +#define MCF_INTC_ICR49(x) (*(vuint8 *)(&__IPSBAR[0x000C71+((x)*0x100)])) +#define MCF_INTC_ICR50(x) (*(vuint8 *)(&__IPSBAR[0x000C72+((x)*0x100)])) +#define MCF_INTC_ICR51(x) (*(vuint8 *)(&__IPSBAR[0x000C73+((x)*0x100)])) +#define MCF_INTC_ICR52(x) (*(vuint8 *)(&__IPSBAR[0x000C74+((x)*0x100)])) +#define MCF_INTC_ICR53(x) (*(vuint8 *)(&__IPSBAR[0x000C75+((x)*0x100)])) +#define MCF_INTC_ICR54(x) (*(vuint8 *)(&__IPSBAR[0x000C76+((x)*0x100)])) +#define MCF_INTC_ICR55(x) (*(vuint8 *)(&__IPSBAR[0x000C77+((x)*0x100)])) +#define MCF_INTC_ICR56(x) (*(vuint8 *)(&__IPSBAR[0x000C78+((x)*0x100)])) +#define MCF_INTC_ICR57(x) (*(vuint8 *)(&__IPSBAR[0x000C79+((x)*0x100)])) +#define MCF_INTC_ICR58(x) (*(vuint8 *)(&__IPSBAR[0x000C7A+((x)*0x100)])) +#define MCF_INTC_ICR59(x) (*(vuint8 *)(&__IPSBAR[0x000C7B+((x)*0x100)])) +#define MCF_INTC_ICR60(x) (*(vuint8 *)(&__IPSBAR[0x000C7C+((x)*0x100)])) +#define MCF_INTC_ICR61(x) (*(vuint8 *)(&__IPSBAR[0x000C7D+((x)*0x100)])) +#define MCF_INTC_ICR62(x) (*(vuint8 *)(&__IPSBAR[0x000C7E+((x)*0x100)])) +#define MCF_INTC_ICR63(x) (*(vuint8 *)(&__IPSBAR[0x000C7F+((x)*0x100)])) +#define MCF_INTC_SWIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE0+((x)*0x100)])) +#define MCF_INTC_L1IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x)*0x100)])) +#define MCF_INTC_L2IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE8+((x)*0x100)])) +#define MCF_INTC_L3IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CEC+((x)*0x100)])) +#define MCF_INTC_L4IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF0+((x)*0x100)])) +#define MCF_INTC_L5IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF4+((x)*0x100)])) +#define MCF_INTC_L6IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF8+((x)*0x100)])) +#define MCF_INTC_L7IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CFC+((x)*0x100)])) + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x00000001) +#define MCF_INTC_IPRH_INT33 (0x00000002) +#define MCF_INTC_IPRH_INT34 (0x00000004) +#define MCF_INTC_IPRH_INT35 (0x00000008) +#define MCF_INTC_IPRH_INT36 (0x00000010) +#define MCF_INTC_IPRH_INT37 (0x00000020) +#define MCF_INTC_IPRH_INT38 (0x00000040) +#define MCF_INTC_IPRH_INT39 (0x00000080) +#define MCF_INTC_IPRH_INT40 (0x00000100) +#define MCF_INTC_IPRH_INT41 (0x00000200) +#define MCF_INTC_IPRH_INT42 (0x00000400) +#define MCF_INTC_IPRH_INT43 (0x00000800) +#define MCF_INTC_IPRH_INT44 (0x00001000) +#define MCF_INTC_IPRH_INT45 (0x00002000) +#define MCF_INTC_IPRH_INT46 (0x00004000) +#define MCF_INTC_IPRH_INT47 (0x00008000) +#define MCF_INTC_IPRH_INT48 (0x00010000) +#define MCF_INTC_IPRH_INT49 (0x00020000) +#define MCF_INTC_IPRH_INT50 (0x00040000) +#define MCF_INTC_IPRH_INT51 (0x00080000) +#define MCF_INTC_IPRH_INT52 (0x00100000) +#define MCF_INTC_IPRH_INT53 (0x00200000) +#define MCF_INTC_IPRH_INT54 (0x00400000) +#define MCF_INTC_IPRH_INT55 (0x00800000) +#define MCF_INTC_IPRH_INT56 (0x01000000) +#define MCF_INTC_IPRH_INT57 (0x02000000) +#define MCF_INTC_IPRH_INT58 (0x04000000) +#define MCF_INTC_IPRH_INT59 (0x08000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x00000002) +#define MCF_INTC_IPRL_INT2 (0x00000004) +#define MCF_INTC_IPRL_INT3 (0x00000008) +#define MCF_INTC_IPRL_INT4 (0x00000010) +#define MCF_INTC_IPRL_INT5 (0x00000020) +#define MCF_INTC_IPRL_INT6 (0x00000040) +#define MCF_INTC_IPRL_INT7 (0x00000080) +#define MCF_INTC_IPRL_INT8 (0x00000100) +#define MCF_INTC_IPRL_INT9 (0x00000200) +#define MCF_INTC_IPRL_INT10 (0x00000400) +#define MCF_INTC_IPRL_INT11 (0x00000800) +#define MCF_INTC_IPRL_INT12 (0x00001000) +#define MCF_INTC_IPRL_INT13 (0x00002000) +#define MCF_INTC_IPRL_INT14 (0x00004000) +#define MCF_INTC_IPRL_INT15 (0x00008000) +#define MCF_INTC_IPRL_INT16 (0x00010000) +#define MCF_INTC_IPRL_INT17 (0x00020000) +#define MCF_INTC_IPRL_INT18 (0x00040000) +#define MCF_INTC_IPRL_INT19 (0x00080000) +#define MCF_INTC_IPRL_INT20 (0x00100000) +#define MCF_INTC_IPRL_INT21 (0x00200000) +#define MCF_INTC_IPRL_INT22 (0x00400000) +#define MCF_INTC_IPRL_INT23 (0x00800000) +#define MCF_INTC_IPRL_INT24 (0x01000000) +#define MCF_INTC_IPRL_INT25 (0x02000000) +#define MCF_INTC_IPRL_INT26 (0x04000000) +#define MCF_INTC_IPRL_INT27 (0x08000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_MASK32 (0x00000001) +#define MCF_INTC_IMRH_MASK33 (0x00000002) +#define MCF_INTC_IMRH_MASK34 (0x00000004) +#define MCF_INTC_IMRH_MASK35 (0x00000008) +#define MCF_INTC_IMRH_MASK36 (0x00000010) +#define MCF_INTC_IMRH_MASK37 (0x00000020) +#define MCF_INTC_IMRH_MASK38 (0x00000040) +#define MCF_INTC_IMRH_MASK39 (0x00000080) +#define MCF_INTC_IMRH_MASK40 (0x00000100) +#define MCF_INTC_IMRH_MASK41 (0x00000200) +#define MCF_INTC_IMRH_MASK42 (0x00000400) +#define MCF_INTC_IMRH_MASK43 (0x00000800) +#define MCF_INTC_IMRH_MASK44 (0x00001000) +#define MCF_INTC_IMRH_MASK45 (0x00002000) +#define MCF_INTC_IMRH_MASK46 (0x00004000) +#define MCF_INTC_IMRH_MASK47 (0x00008000) +#define MCF_INTC_IMRH_MASK48 (0x00010000) +#define MCF_INTC_IMRH_MASK49 (0x00020000) +#define MCF_INTC_IMRH_MASK50 (0x00040000) +#define MCF_INTC_IMRH_MASK51 (0x00080000) +#define MCF_INTC_IMRH_MASK52 (0x00100000) +#define MCF_INTC_IMRH_MASK53 (0x00200000) +#define MCF_INTC_IMRH_MASK54 (0x00400000) +#define MCF_INTC_IMRH_MASK55 (0x00800000) +#define MCF_INTC_IMRH_MASK56 (0x01000000) +#define MCF_INTC_IMRH_MASK57 (0x02000000) +#define MCF_INTC_IMRH_MASK58 (0x04000000) +#define MCF_INTC_IMRH_MASK59 (0x08000000) +#define MCF_INTC_IMRH_MASK60 (0x10000000) +#define MCF_INTC_IMRH_MASK61 (0x20000000) +#define MCF_INTC_IMRH_MASK62 (0x40000000) +#define MCF_INTC_IMRH_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x00000001) +#define MCF_INTC_IMRL_MASK1 (0x00000002) +#define MCF_INTC_IMRL_MASK2 (0x00000004) +#define MCF_INTC_IMRL_MASK3 (0x00000008) +#define MCF_INTC_IMRL_MASK4 (0x00000010) +#define MCF_INTC_IMRL_MASK5 (0x00000020) +#define MCF_INTC_IMRL_MASK6 (0x00000040) +#define MCF_INTC_IMRL_MASK7 (0x00000080) +#define MCF_INTC_IMRL_MASK8 (0x00000100) +#define MCF_INTC_IMRL_MASK9 (0x00000200) +#define MCF_INTC_IMRL_MASK10 (0x00000400) +#define MCF_INTC_IMRL_MASK11 (0x00000800) +#define MCF_INTC_IMRL_MASK12 (0x00001000) +#define MCF_INTC_IMRL_MASK13 (0x00002000) +#define MCF_INTC_IMRL_MASK14 (0x00004000) +#define MCF_INTC_IMRL_MASK15 (0x00008000) +#define MCF_INTC_IMRL_MASK16 (0x00010000) +#define MCF_INTC_IMRL_MASK17 (0x00020000) +#define MCF_INTC_IMRL_MASK18 (0x00040000) +#define MCF_INTC_IMRL_MASK19 (0x00080000) +#define MCF_INTC_IMRL_MASK20 (0x00100000) +#define MCF_INTC_IMRL_MASK21 (0x00200000) +#define MCF_INTC_IMRL_MASK22 (0x00400000) +#define MCF_INTC_IMRL_MASK23 (0x00800000) +#define MCF_INTC_IMRL_MASK24 (0x01000000) +#define MCF_INTC_IMRL_MASK25 (0x02000000) +#define MCF_INTC_IMRL_MASK26 (0x04000000) +#define MCF_INTC_IMRL_MASK27 (0x08000000) +#define MCF_INTC_IMRL_MASK28 (0x10000000) +#define MCF_INTC_IMRL_MASK29 (0x20000000) +#define MCF_INTC_IMRL_MASK30 (0x40000000) +#define MCF_INTC_IMRL_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) +#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) +#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) +#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) +#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) +#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) +#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) +#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) +#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) +#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) +#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) +#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) +#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) +#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) +#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) +#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x07)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PORTNQ (*(vuint8 *)(&__IPSBAR[0x100008])) +#define MCF_GPIO_PORTAN (*(vuint8 *)(&__IPSBAR[0x10000A])) +#define MCF_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000B])) +#define MCF_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000C])) +#define MCF_GPIO_PORTTA (*(vuint8 *)(&__IPSBAR[0x10000E])) +#define MCF_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F])) +#define MCF_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010])) +#define MCF_GPIO_PORTTE (*(vuint8 *)(&__IPSBAR[0x100000])) +#define MCF_GPIO_PORTTF (*(vuint8 *)(&__IPSBAR[0x100001])) +#define MCF_GPIO_PORTTG (*(vuint8 *)(&__IPSBAR[0x100002])) +#define MCF_GPIO_PORTTH (*(vuint8 *)(&__IPSBAR[0x100003])) +#define MCF_GPIO_PORTTI (*(vuint8 *)(&__IPSBAR[0x100004])) +#define MCF_GPIO_PORTTJ (*(vuint8 *)(&__IPSBAR[0x100006])) +#define MCF_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011])) +#define MCF_GPIO_PORTUB (*(vuint8 *)(&__IPSBAR[0x100012])) +#define MCF_GPIO_PORTUC (*(vuint8 *)(&__IPSBAR[0x100013])) +#define MCF_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100014])) +#define MCF_GPIO_PORTLD (*(vuint8 *)(&__IPSBAR[0x100015])) +#define MCF_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x100016])) +#define MCF_GPIO_DDRNQ (*(vuint8 *)(&__IPSBAR[0x100020])) +#define MCF_GPIO_DDRAN (*(vuint8 *)(&__IPSBAR[0x100022])) +#define MCF_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100023])) +#define MCF_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100024])) +#define MCF_GPIO_DDRTA (*(vuint8 *)(&__IPSBAR[0x100026])) +#define MCF_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100027])) +#define MCF_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100028])) +#define MCF_GPIO_DDRTE (*(vuint8 *)(&__IPSBAR[0x100018])) +#define MCF_GPIO_DDRTF (*(vuint8 *)(&__IPSBAR[0x100019])) +#define MCF_GPIO_DDRTG (*(vuint8 *)(&__IPSBAR[0x10001A])) +#define MCF_GPIO_DDRTH (*(vuint8 *)(&__IPSBAR[0x10001B])) +#define MCF_GPIO_DDRTI (*(vuint8 *)(&__IPSBAR[0x10001C])) +#define MCF_GPIO_DDRTJ (*(vuint8 *)(&__IPSBAR[0x10001E])) +#define MCF_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100029])) +#define MCF_GPIO_DDRUB (*(vuint8 *)(&__IPSBAR[0x10002A])) +#define MCF_GPIO_DDRUC (*(vuint8 *)(&__IPSBAR[0x10002B])) +#define MCF_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10002C])) +#define MCF_GPIO_DDRLD (*(vuint8 *)(&__IPSBAR[0x10002D])) +#define MCF_GPIO_DDRGP (*(vuint8 *)(&__IPSBAR[0x10002E])) +#define MCF_GPIO_SETNQ (*(vuint8 *)(&__IPSBAR[0x100038])) +#define MCF_GPIO_SETAN (*(vuint8 *)(&__IPSBAR[0x10003A])) +#define MCF_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x10003B])) +#define MCF_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x10003C])) +#define MCF_GPIO_SETTA (*(vuint8 *)(&__IPSBAR[0x10003E])) +#define MCF_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x10003F])) +#define MCF_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100040])) +#define MCF_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100041])) +#define MCF_GPIO_SETUB (*(vuint8 *)(&__IPSBAR[0x100042])) +#define MCF_GPIO_SETUC (*(vuint8 *)(&__IPSBAR[0x100043])) +#define MCF_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100044])) +#define MCF_GPIO_SETLD (*(vuint8 *)(&__IPSBAR[0x100045])) +#define MCF_GPIO_SETGP (*(vuint8 *)(&__IPSBAR[0x100046])) +#define MCF_GPIO_CLRNQ (*(vuint8 *)(&__IPSBAR[0x100050])) +#define MCF_GPIO_CLRAN (*(vuint8 *)(&__IPSBAR[0x100052])) +#define MCF_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100053])) +#define MCF_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100054])) +#define MCF_GPIO_CLRTA (*(vuint8 *)(&__IPSBAR[0x100056])) +#define MCF_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x100057])) +#define MCF_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x100058])) +#define MCF_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x100059])) +#define MCF_GPIO_CLRUB (*(vuint8 *)(&__IPSBAR[0x10005A])) +#define MCF_GPIO_CLRUC (*(vuint8 *)(&__IPSBAR[0x10005B])) +#define MCF_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x10005C])) +#define MCF_GPIO_CLRLD (*(vuint8 *)(&__IPSBAR[0x10005D])) +#define MCF_GPIO_CLRGP (*(vuint8 *)(&__IPSBAR[0x10005E])) +#define MCF_GPIO_PNQPAR (*(vuint16*)(&__IPSBAR[0x100068])) +#define MCF_GPIO_PANPAR (*(vuint8 *)(&__IPSBAR[0x10006A])) +#define MCF_GPIO_PASPAR (*(vuint8 *)(&__IPSBAR[0x10006B])) +#define MCF_GPIO_PQSPAR (*(vuint16*)(&__IPSBAR[0x10006C])) +#define MCF_GPIO_PTAPAR (*(vuint8 *)(&__IPSBAR[0x10006E])) +#define MCF_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10006F])) +#define MCF_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x100070])) +#define MCF_GPIO_PTEPAR (*(vuint8 *)(&__IPSBAR[0x100060])) +#define MCF_GPIO_PTFPAR (*(vuint8 *)(&__IPSBAR[0x100061])) +#define MCF_GPIO_PTGPAR (*(vuint8 *)(&__IPSBAR[0x100062])) +#define MCF_GPIO_PTHPAR (*(vuint8 *)(&__IPSBAR[0x100090])) +#define MCF_GPIO_PTIPAR (*(vuint8*)(&__IPSBAR[0x100064])) +#define MCF_GPIO_PTJPAR (*(vuint8*)(&__IPSBAR[0x100066])) +#define MCF_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x100071])) +#define MCF_GPIO_PUBPAR (*(vuint8 *)(&__IPSBAR[0x100072])) +#define MCF_GPIO_PUCPAR (*(vuint8 *)(&__IPSBAR[0x100073])) +#define MCF_GPIO_PDDPAR (*(vuint8 *)(&__IPSBAR[0x100074])) +#define MCF_GPIO_PLDPAR (*(vuint8 *)(&__IPSBAR[0x100075])) +#define MCF_GPIO_PGPPAR (*(vuint8 *)(&__IPSBAR[0x100076])) +#define MCF_GPIO_PWOR (*(vuint16*)(&__IPSBAR[0x100078])) +#define MCF_GPIO_PDSRH (*(vuint16*)(&__IPSBAR[0x10007A])) +#define MCF_GPIO_PDSRL (*(vuint32*)(&__IPSBAR[0x10007C])) + +/* Bit definitions and macros for MCF_GPIO_PORTNQ */ +#define MCF_GPIO_PORTNQ_PORTNQ0 (0x01) +#define MCF_GPIO_PORTNQ_PORTNQ1 (0x02) +#define MCF_GPIO_PORTNQ_PORTNQ2 (0x04) +#define MCF_GPIO_PORTNQ_PORTNQ3 (0x08) +#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10) +#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20) +#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40) +#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTAN */ +#define MCF_GPIO_PORTAN_PORTAN0 (0x01) +#define MCF_GPIO_PORTAN_PORTAN1 (0x02) +#define MCF_GPIO_PORTAN_PORTAN2 (0x04) +#define MCF_GPIO_PORTAN_PORTAN3 (0x08) +#define MCF_GPIO_PORTAN_PORTAN4 (0x10) +#define MCF_GPIO_PORTAN_PORTAN5 (0x20) +#define MCF_GPIO_PORTAN_PORTAN6 (0x40) +#define MCF_GPIO_PORTAN_PORTAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTAS */ +#define MCF_GPIO_PORTAS_PORTAS0 (0x01) +#define MCF_GPIO_PORTAS_PORTAS1 (0x02) +#define MCF_GPIO_PORTAS_PORTAS2 (0x04) +#define MCF_GPIO_PORTAS_PORTAS3 (0x08) +#define MCF_GPIO_PORTAS_PORTAS4 (0x10) +#define MCF_GPIO_PORTAS_PORTAS5 (0x20) +#define MCF_GPIO_PORTAS_PORTAS6 (0x40) +#define MCF_GPIO_PORTAS_PORTAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTQS */ +#define MCF_GPIO_PORTQS_PORTQS0 (0x01) +#define MCF_GPIO_PORTQS_PORTQS1 (0x02) +#define MCF_GPIO_PORTQS_PORTQS2 (0x04) +#define MCF_GPIO_PORTQS_PORTQS3 (0x08) +#define MCF_GPIO_PORTQS_PORTQS4 (0x10) +#define MCF_GPIO_PORTQS_PORTQS5 (0x20) +#define MCF_GPIO_PORTQS_PORTQS6 (0x40) +#define MCF_GPIO_PORTQS_PORTQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTA */ +#define MCF_GPIO_PORTTA_PORTTA0 (0x01) +#define MCF_GPIO_PORTTA_PORTTA1 (0x02) +#define MCF_GPIO_PORTTA_PORTTA2 (0x04) +#define MCF_GPIO_PORTTA_PORTTA3 (0x08) +#define MCF_GPIO_PORTTA_PORTTA4 (0x10) +#define MCF_GPIO_PORTTA_PORTTA5 (0x20) +#define MCF_GPIO_PORTTA_PORTTA6 (0x40) +#define MCF_GPIO_PORTTA_PORTTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTC */ +#define MCF_GPIO_PORTTC_PORTTC0 (0x01) +#define MCF_GPIO_PORTTC_PORTTC1 (0x02) +#define MCF_GPIO_PORTTC_PORTTC2 (0x04) +#define MCF_GPIO_PORTTC_PORTTC3 (0x08) +#define MCF_GPIO_PORTTC_PORTTC4 (0x10) +#define MCF_GPIO_PORTTC_PORTTC5 (0x20) +#define MCF_GPIO_PORTTC_PORTTC6 (0x40) +#define MCF_GPIO_PORTTC_PORTTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTD */ +#define MCF_GPIO_PORTTD_PORTTD0 (0x01) +#define MCF_GPIO_PORTTD_PORTTD1 (0x02) +#define MCF_GPIO_PORTTD_PORTTD2 (0x04) +#define MCF_GPIO_PORTTD_PORTTD3 (0x08) +#define MCF_GPIO_PORTTD_PORTTD4 (0x10) +#define MCF_GPIO_PORTTD_PORTTD5 (0x20) +#define MCF_GPIO_PORTTD_PORTTD6 (0x40) +#define MCF_GPIO_PORTTD_PORTTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTE */ +#define MCF_GPIO_PORTTE_PORTTE0 (0x01) +#define MCF_GPIO_PORTTE_PORTTE1 (0x02) +#define MCF_GPIO_PORTTE_PORTTE2 (0x04) +#define MCF_GPIO_PORTTE_PORTTE3 (0x08) +#define MCF_GPIO_PORTTE_PORTTE4 (0x10) +#define MCF_GPIO_PORTTE_PORTTE5 (0x20) +#define MCF_GPIO_PORTTE_PORTTE6 (0x40) +#define MCF_GPIO_PORTTE_PORTTE7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTF */ +#define MCF_GPIO_PORTTF_PORTTF0 (0x01) +#define MCF_GPIO_PORTTF_PORTTF1 (0x02) +#define MCF_GPIO_PORTTF_PORTTF2 (0x04) +#define MCF_GPIO_PORTTF_PORTTF3 (0x08) +#define MCF_GPIO_PORTTF_PORTTF4 (0x10) +#define MCF_GPIO_PORTTF_PORTTF5 (0x20) +#define MCF_GPIO_PORTTF_PORTTF6 (0x40) +#define MCF_GPIO_PORTTF_PORTTF7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTG */ +#define MCF_GPIO_PORTTG_PORTTG0 (0x01) +#define MCF_GPIO_PORTTG_PORTTG1 (0x02) +#define MCF_GPIO_PORTTG_PORTTG2 (0x04) +#define MCF_GPIO_PORTTG_PORTTG3 (0x08) +#define MCF_GPIO_PORTTG_PORTTG4 (0x10) +#define MCF_GPIO_PORTTG_PORTTG5 (0x20) +#define MCF_GPIO_PORTTG_PORTTG6 (0x40) +#define MCF_GPIO_PORTTG_PORTTG7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTH */ +#define MCF_GPIO_PORTTH_PORTTH0 (0x01) +#define MCF_GPIO_PORTTH_PORTTH1 (0x02) +#define MCF_GPIO_PORTTH_PORTTH2 (0x04) +#define MCF_GPIO_PORTTH_PORTTH3 (0x08) +#define MCF_GPIO_PORTTH_PORTTH4 (0x10) +#define MCF_GPIO_PORTTH_PORTTH5 (0x20) +#define MCF_GPIO_PORTTH_PORTTH6 (0x40) +#define MCF_GPIO_PORTTH_PORTTH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTI */ +#define MCF_GPIO_PORTTI_PORTTI0 (0x01) +#define MCF_GPIO_PORTTI_PORTTI1 (0x02) +#define MCF_GPIO_PORTTI_PORTTI2 (0x04) +#define MCF_GPIO_PORTTI_PORTTI3 (0x08) +#define MCF_GPIO_PORTTI_PORTTI4 (0x10) +#define MCF_GPIO_PORTTI_PORTTI5 (0x20) +#define MCF_GPIO_PORTTI_PORTTI6 (0x40) +#define MCF_GPIO_PORTTI_PORTTI7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTUA */ +#define MCF_GPIO_PORTUA_PORTUA0 (0x01) +#define MCF_GPIO_PORTUA_PORTUA1 (0x02) +#define MCF_GPIO_PORTUA_PORTUA2 (0x04) +#define MCF_GPIO_PORTUA_PORTUA3 (0x08) +#define MCF_GPIO_PORTUA_PORTUA4 (0x10) +#define MCF_GPIO_PORTUA_PORTUA5 (0x20) +#define MCF_GPIO_PORTUA_PORTUA6 (0x40) +#define MCF_GPIO_PORTUA_PORTUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTUB */ +#define MCF_GPIO_PORTUB_PORTUB0 (0x01) +#define MCF_GPIO_PORTUB_PORTUB1 (0x02) +#define MCF_GPIO_PORTUB_PORTUB2 (0x04) +#define MCF_GPIO_PORTUB_PORTUB3 (0x08) +#define MCF_GPIO_PORTUB_PORTUB4 (0x10) +#define MCF_GPIO_PORTUB_PORTUB5 (0x20) +#define MCF_GPIO_PORTUB_PORTUB6 (0x40) +#define MCF_GPIO_PORTUB_PORTUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTUC */ +#define MCF_GPIO_PORTUC_PORTUC0 (0x01) +#define MCF_GPIO_PORTUC_PORTUC1 (0x02) +#define MCF_GPIO_PORTUC_PORTUC2 (0x04) +#define MCF_GPIO_PORTUC_PORTUC3 (0x08) +#define MCF_GPIO_PORTUC_PORTUC4 (0x10) +#define MCF_GPIO_PORTUC_PORTUC5 (0x20) +#define MCF_GPIO_PORTUC_PORTUC6 (0x40) +#define MCF_GPIO_PORTUC_PORTUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTDD */ +#define MCF_GPIO_PORTDD_PORTDD0 (0x01) +#define MCF_GPIO_PORTDD_PORTDD1 (0x02) +#define MCF_GPIO_PORTDD_PORTDD2 (0x04) +#define MCF_GPIO_PORTDD_PORTDD3 (0x08) +#define MCF_GPIO_PORTDD_PORTDD4 (0x10) +#define MCF_GPIO_PORTDD_PORTDD5 (0x20) +#define MCF_GPIO_PORTDD_PORTDD6 (0x40) +#define MCF_GPIO_PORTDD_PORTDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTLD */ +#define MCF_GPIO_PORTLD_PORTLD0 (0x01) +#define MCF_GPIO_PORTLD_PORTLD1 (0x02) +#define MCF_GPIO_PORTLD_PORTLD2 (0x04) +#define MCF_GPIO_PORTLD_PORTLD3 (0x08) +#define MCF_GPIO_PORTLD_PORTLD4 (0x10) +#define MCF_GPIO_PORTLD_PORTLD5 (0x20) +#define MCF_GPIO_PORTLD_PORTLD6 (0x40) +#define MCF_GPIO_PORTLD_PORTLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTGP */ +#define MCF_GPIO_PORTGP_PORTGP0 (0x01) +#define MCF_GPIO_PORTGP_PORTGP1 (0x02) +#define MCF_GPIO_PORTGP_PORTGP2 (0x04) +#define MCF_GPIO_PORTGP_PORTGP3 (0x08) +#define MCF_GPIO_PORTGP_PORTGP4 (0x10) +#define MCF_GPIO_PORTGP_PORTGP5 (0x20) +#define MCF_GPIO_PORTGP_PORTGP6 (0x40) +#define MCF_GPIO_PORTGP_PORTGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRNQ */ +#define MCF_GPIO_DDRNQ_DDRNQ0 (0x01) +#define MCF_GPIO_DDRNQ_DDRNQ1 (0x02) +#define MCF_GPIO_DDRNQ_DDRNQ2 (0x04) +#define MCF_GPIO_DDRNQ_DDRNQ3 (0x08) +#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10) +#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20) +#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40) +#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRAN */ +#define MCF_GPIO_DDRAN_DDRAN0 (0x01) +#define MCF_GPIO_DDRAN_DDRAN1 (0x02) +#define MCF_GPIO_DDRAN_DDRAN2 (0x04) +#define MCF_GPIO_DDRAN_DDRAN3 (0x08) +#define MCF_GPIO_DDRAN_DDRAN4 (0x10) +#define MCF_GPIO_DDRAN_DDRAN5 (0x20) +#define MCF_GPIO_DDRAN_DDRAN6 (0x40) +#define MCF_GPIO_DDRAN_DDRAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRAS */ +#define MCF_GPIO_DDRAS_DDRAS0 (0x01) +#define MCF_GPIO_DDRAS_DDRAS1 (0x02) +#define MCF_GPIO_DDRAS_DDRAS2 (0x04) +#define MCF_GPIO_DDRAS_DDRAS3 (0x08) +#define MCF_GPIO_DDRAS_DDRAS4 (0x10) +#define MCF_GPIO_DDRAS_DDRAS5 (0x20) +#define MCF_GPIO_DDRAS_DDRAS6 (0x40) +#define MCF_GPIO_DDRAS_DDRAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRQS */ +#define MCF_GPIO_DDRQS_DDRQS0 (0x01) +#define MCF_GPIO_DDRQS_DDRQS1 (0x02) +#define MCF_GPIO_DDRQS_DDRQS2 (0x04) +#define MCF_GPIO_DDRQS_DDRQS3 (0x08) +#define MCF_GPIO_DDRQS_DDRQS4 (0x10) +#define MCF_GPIO_DDRQS_DDRQS5 (0x20) +#define MCF_GPIO_DDRQS_DDRQS6 (0x40) +#define MCF_GPIO_DDRQS_DDRQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTA */ +#define MCF_GPIO_DDRTA_DDRTA0 (0x01) +#define MCF_GPIO_DDRTA_DDRTA1 (0x02) +#define MCF_GPIO_DDRTA_DDRTA2 (0x04) +#define MCF_GPIO_DDRTA_DDRTA3 (0x08) +#define MCF_GPIO_DDRTA_DDRTA4 (0x10) +#define MCF_GPIO_DDRTA_DDRTA5 (0x20) +#define MCF_GPIO_DDRTA_DDRTA6 (0x40) +#define MCF_GPIO_DDRTA_DDRTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTC */ +#define MCF_GPIO_DDRTC_DDRTC0 (0x01) +#define MCF_GPIO_DDRTC_DDRTC1 (0x02) +#define MCF_GPIO_DDRTC_DDRTC2 (0x04) +#define MCF_GPIO_DDRTC_DDRTC3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_DDRTD */ +#define MCF_GPIO_DDRTD_DDRTD0 (0x01) +#define MCF_GPIO_DDRTD_DDRTD1 (0x02) +#define MCF_GPIO_DDRTD_DDRTD2 (0x04) +#define MCF_GPIO_DDRTD_DDRTD3 (0x08) +#define MCF_GPIO_DDRTD_DDRTD4 (0x10) +#define MCF_GPIO_DDRTD_DDRTD5 (0x20) +#define MCF_GPIO_DDRTD_DDRTD6 (0x40) +#define MCF_GPIO_DDRTD_DDRTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTE */ +#define MCF_GPIO_DDRTE_DDRTE0 (0x01) +#define MCF_GPIO_DDRTE_DDRTE1 (0x02) +#define MCF_GPIO_DDRTE_DDRTE2 (0x04) +#define MCF_GPIO_DDRTE_DDRTE3 (0x08) +#define MCF_GPIO_DDRTE_DDRTE4 (0x10) +#define MCF_GPIO_DDRTE_DDRTE5 (0x20) +#define MCF_GPIO_DDRTE_DDRTE6 (0x40) +#define MCF_GPIO_DDRTE_DDRTE7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTF */ +#define MCF_GPIO_DDRTF_DDRTF0 (0x01) +#define MCF_GPIO_DDRTF_DDRTF1 (0x02) +#define MCF_GPIO_DDRTF_DDRTF2 (0x04) +#define MCF_GPIO_DDRTF_DDRTF3 (0x08) +#define MCF_GPIO_DDRTF_DDRTF4 (0x10) +#define MCF_GPIO_DDRTF_DDRTF5 (0x20) +#define MCF_GPIO_DDRTF_DDRTF6 (0x40) +#define MCF_GPIO_DDRTF_DDRTF7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTG */ +#define MCF_GPIO_DDRTG_DDRTG0 (0x01) +#define MCF_GPIO_DDRTG_DDRTG1 (0x02) +#define MCF_GPIO_DDRTG_DDRTG2 (0x04) +#define MCF_GPIO_DDRTG_DDRTG3 (0x08) +#define MCF_GPIO_DDRTG_DDRTG4 (0x10) +#define MCF_GPIO_DDRTG_DDRTG5 (0x20) +#define MCF_GPIO_DDRTG_DDRTG6 (0x40) +#define MCF_GPIO_DDRTG_DDRTG7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTH */ +#define MCF_GPIO_DDRTH_DDRTH0 (0x01) +#define MCF_GPIO_DDRTH_DDRTH1 (0x02) +#define MCF_GPIO_DDRTH_DDRTH2 (0x04) +#define MCF_GPIO_DDRTH_DDRTH3 (0x08) +#define MCF_GPIO_DDRTH_DDRTH4 (0x10) +#define MCF_GPIO_DDRTH_DDRTH5 (0x20) +#define MCF_GPIO_DDRTH_DDRTH6 (0x40) +#define MCF_GPIO_DDRTH_DDRTH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTI */ +#define MCF_GPIO_DDRTI_DDRTI0 (0x01) +#define MCF_GPIO_DDRTI_DDRTI1 (0x02) +#define MCF_GPIO_DDRTI_DDRTI2 (0x04) +#define MCF_GPIO_DDRTI_DDRTI3 (0x08) +#define MCF_GPIO_DDRTI_DDRTI4 (0x10) +#define MCF_GPIO_DDRTI_DDRTI5 (0x20) +#define MCF_GPIO_DDRTI_DDRTI6 (0x40) +#define MCF_GPIO_DDRTI_DDRTI7 (0x80) + +/* Bit definiTJons and macros for MCF_GPIO_DDRTJ */ +#define MCF_GPIO_DDRTJ_DDRTJ0 (0x01) +#define MCF_GPIO_DDRTJ_DDRTJ1 (0x02) +#define MCF_GPIO_DDRTJ_DDRTJ2 (0x04) +#define MCF_GPIO_DDRTJ_DDRTJ3 (0x08) +#define MCF_GPIO_DDRTJ_DDRTJ4 (0x10) +#define MCF_GPIO_DDRTJ_DDRTJ5 (0x20) +#define MCF_GPIO_DDRTJ_DDRTJ6 (0x40) +#define MCF_GPIO_DDRTJ_DDRTJ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRUA */ +#define MCF_GPIO_DDRUA_DDRUA0 (0x01) +#define MCF_GPIO_DDRUA_DDRUA1 (0x02) +#define MCF_GPIO_DDRUA_DDRUA2 (0x04) +#define MCF_GPIO_DDRUA_DDRUA3 (0x08) +#define MCF_GPIO_DDRUA_DDRUA4 (0x10) +#define MCF_GPIO_DDRUA_DDRUA5 (0x20) +#define MCF_GPIO_DDRUA_DDRUA6 (0x40) +#define MCF_GPIO_DDRUA_DDRUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRUB */ +#define MCF_GPIO_DDRUB_DDRUB0 (0x01) +#define MCF_GPIO_DDRUB_DDRUB1 (0x02) +#define MCF_GPIO_DDRUB_DDRUB2 (0x04) +#define MCF_GPIO_DDRUB_DDRUB3 (0x08) +#define MCF_GPIO_DDRUB_DDRUB4 (0x10) +#define MCF_GPIO_DDRUB_DDRUB5 (0x20) +#define MCF_GPIO_DDRUB_DDRUB6 (0x40) +#define MCF_GPIO_DDRUB_DDRUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRUC */ +#define MCF_GPIO_DDRUC_DDRUC0 (0x01) +#define MCF_GPIO_DDRUC_DDRUC1 (0x02) +#define MCF_GPIO_DDRUC_DDRUC2 (0x04) +#define MCF_GPIO_DDRUC_DDRUC3 (0x08) +#define MCF_GPIO_DDRUC_DDRUC4 (0x10) +#define MCF_GPIO_DDRUC_DDRUC5 (0x20) +#define MCF_GPIO_DDRUC_DDRUC6 (0x40) +#define MCF_GPIO_DDRUC_DDRUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRDD */ +#define MCF_GPIO_DDRDD_DDRDD0 (0x01) +#define MCF_GPIO_DDRDD_DDRDD1 (0x02) +#define MCF_GPIO_DDRDD_DDRDD2 (0x04) +#define MCF_GPIO_DDRDD_DDRDD3 (0x08) +#define MCF_GPIO_DDRDD_DDRDD4 (0x10) +#define MCF_GPIO_DDRDD_DDRDD5 (0x20) +#define MCF_GPIO_DDRDD_DDRDD6 (0x40) +#define MCF_GPIO_DDRDD_DDRDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRLD */ +#define MCF_GPIO_DDRLD_DDRLD0 (0x01) +#define MCF_GPIO_DDRLD_DDRLD1 (0x02) +#define MCF_GPIO_DDRLD_DDRLD2 (0x04) +#define MCF_GPIO_DDRLD_DDRLD3 (0x08) +#define MCF_GPIO_DDRLD_DDRLD4 (0x10) +#define MCF_GPIO_DDRLD_DDRLD5 (0x20) +#define MCF_GPIO_DDRLD_DDRLD6 (0x40) +#define MCF_GPIO_DDRLD_DDRLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRGP */ +#define MCF_GPIO_DDRGP_DDRGP0 (0x01) +#define MCF_GPIO_DDRGP_DDRGP1 (0x02) +#define MCF_GPIO_DDRGP_DDRGP2 (0x04) +#define MCF_GPIO_DDRGP_DDRGP3 (0x08) +#define MCF_GPIO_DDRGP_DDRGP4 (0x10) +#define MCF_GPIO_DDRGP_DDRGP5 (0x20) +#define MCF_GPIO_DDRGP_DDRGP6 (0x40) +#define MCF_GPIO_DDRGP_DDRGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETNQ */ +#define MCF_GPIO_SETNQ_SETNQ0 (0x01) +#define MCF_GPIO_SETNQ_SETNQ1 (0x02) +#define MCF_GPIO_SETNQ_SETNQ2 (0x04) +#define MCF_GPIO_SETNQ_SETNQ3 (0x08) +#define MCF_GPIO_SETNQ_SETNQ4 (0x10) +#define MCF_GPIO_SETNQ_SETNQ5 (0x20) +#define MCF_GPIO_SETNQ_SETNQ6 (0x40) +#define MCF_GPIO_SETNQ_SETNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETAN */ +#define MCF_GPIO_SETAN_SETAN0 (0x01) +#define MCF_GPIO_SETAN_SETAN1 (0x02) +#define MCF_GPIO_SETAN_SETAN2 (0x04) +#define MCF_GPIO_SETAN_SETAN3 (0x08) +#define MCF_GPIO_SETAN_SETAN4 (0x10) +#define MCF_GPIO_SETAN_SETAN5 (0x20) +#define MCF_GPIO_SETAN_SETAN6 (0x40) +#define MCF_GPIO_SETAN_SETAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETAS */ +#define MCF_GPIO_SETAS_SETAS0 (0x01) +#define MCF_GPIO_SETAS_SETAS1 (0x02) +#define MCF_GPIO_SETAS_SETAS2 (0x04) +#define MCF_GPIO_SETAS_SETAS3 (0x08) +#define MCF_GPIO_SETAS_SETAS4 (0x10) +#define MCF_GPIO_SETAS_SETAS5 (0x20) +#define MCF_GPIO_SETAS_SETAS6 (0x40) +#define MCF_GPIO_SETAS_SETAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETQS */ +#define MCF_GPIO_SETQS_SETQS0 (0x01) +#define MCF_GPIO_SETQS_SETQS1 (0x02) +#define MCF_GPIO_SETQS_SETQS2 (0x04) +#define MCF_GPIO_SETQS_SETQS3 (0x08) +#define MCF_GPIO_SETQS_SETQS4 (0x10) +#define MCF_GPIO_SETQS_SETQS5 (0x20) +#define MCF_GPIO_SETQS_SETQS6 (0x40) +#define MCF_GPIO_SETQS_SETQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETTA */ +#define MCF_GPIO_SETTA_SETTA0 (0x01) +#define MCF_GPIO_SETTA_SETTA1 (0x02) +#define MCF_GPIO_SETTA_SETTA2 (0x04) +#define MCF_GPIO_SETTA_SETTA3 (0x08) +#define MCF_GPIO_SETTA_SETTA4 (0x10) +#define MCF_GPIO_SETTA_SETTA5 (0x20) +#define MCF_GPIO_SETTA_SETTA6 (0x40) +#define MCF_GPIO_SETTA_SETTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETTC */ +#define MCF_GPIO_SETTC_SETTC0 (0x01) +#define MCF_GPIO_SETTC_SETTC1 (0x02) +#define MCF_GPIO_SETTC_SETTC2 (0x04) +#define MCF_GPIO_SETTC_SETTC3 (0x08) +#define MCF_GPIO_SETTC_SETTC4 (0x10) +#define MCF_GPIO_SETTC_SETTC5 (0x20) +#define MCF_GPIO_SETTC_SETTC6 (0x40) +#define MCF_GPIO_SETTC_SETTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETTD */ +#define MCF_GPIO_SETTD_SETTD0 (0x01) +#define MCF_GPIO_SETTD_SETTD1 (0x02) +#define MCF_GPIO_SETTD_SETTD2 (0x04) +#define MCF_GPIO_SETTD_SETTD3 (0x08) +#define MCF_GPIO_SETTD_SETTD4 (0x10) +#define MCF_GPIO_SETTD_SETTD5 (0x20) +#define MCF_GPIO_SETTD_SETTD6 (0x40) +#define MCF_GPIO_SETTD_SETTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETUA */ +#define MCF_GPIO_SETUA_SETUA0 (0x01) +#define MCF_GPIO_SETUA_SETUA1 (0x02) +#define MCF_GPIO_SETUA_SETUA2 (0x04) +#define MCF_GPIO_SETUA_SETUA3 (0x08) +#define MCF_GPIO_SETUA_SETUA4 (0x10) +#define MCF_GPIO_SETUA_SETUA5 (0x20) +#define MCF_GPIO_SETUA_SETUA6 (0x40) +#define MCF_GPIO_SETUA_SETUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETUB */ +#define MCF_GPIO_SETUB_SETUB0 (0x01) +#define MCF_GPIO_SETUB_SETUB1 (0x02) +#define MCF_GPIO_SETUB_SETUB2 (0x04) +#define MCF_GPIO_SETUB_SETUB3 (0x08) +#define MCF_GPIO_SETUB_SETUB4 (0x10) +#define MCF_GPIO_SETUB_SETUB5 (0x20) +#define MCF_GPIO_SETUB_SETUB6 (0x40) +#define MCF_GPIO_SETUB_SETUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETUC */ +#define MCF_GPIO_SETUC_SETUC0 (0x01) +#define MCF_GPIO_SETUC_SETUC1 (0x02) +#define MCF_GPIO_SETUC_SETUC2 (0x04) +#define MCF_GPIO_SETUC_SETUC3 (0x08) +#define MCF_GPIO_SETUC_SETUC4 (0x10) +#define MCF_GPIO_SETUC_SETUC5 (0x20) +#define MCF_GPIO_SETUC_SETUC6 (0x40) +#define MCF_GPIO_SETUC_SETUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETDD */ +#define MCF_GPIO_SETDD_SETDD0 (0x01) +#define MCF_GPIO_SETDD_SETDD1 (0x02) +#define MCF_GPIO_SETDD_SETDD2 (0x04) +#define MCF_GPIO_SETDD_SETDD3 (0x08) +#define MCF_GPIO_SETDD_SETDD4 (0x10) +#define MCF_GPIO_SETDD_SETDD5 (0x20) +#define MCF_GPIO_SETDD_SETDD6 (0x40) +#define MCF_GPIO_SETDD_SETDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETLD */ +#define MCF_GPIO_SETLD_SETLD0 (0x01) +#define MCF_GPIO_SETLD_SETLD1 (0x02) +#define MCF_GPIO_SETLD_SETLD2 (0x04) +#define MCF_GPIO_SETLD_SETLD3 (0x08) +#define MCF_GPIO_SETLD_SETLD4 (0x10) +#define MCF_GPIO_SETLD_SETLD5 (0x20) +#define MCF_GPIO_SETLD_SETLD6 (0x40) +#define MCF_GPIO_SETLD_SETLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETGP */ +#define MCF_GPIO_SETGP_SETGP0 (0x01) +#define MCF_GPIO_SETGP_SETGP1 (0x02) +#define MCF_GPIO_SETGP_SETGP2 (0x04) +#define MCF_GPIO_SETGP_SETGP3 (0x08) +#define MCF_GPIO_SETGP_SETGP4 (0x10) +#define MCF_GPIO_SETGP_SETGP5 (0x20) +#define MCF_GPIO_SETGP_SETGP6 (0x40) +#define MCF_GPIO_SETGP_SETGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRNQ */ +#define MCF_GPIO_CLRNQ_CLRNQ0 (0x01) +#define MCF_GPIO_CLRNQ_CLRNQ1 (0x02) +#define MCF_GPIO_CLRNQ_CLRNQ2 (0x04) +#define MCF_GPIO_CLRNQ_CLRNQ3 (0x08) +#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10) +#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20) +#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40) +#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRAN */ +#define MCF_GPIO_CLRAN_CLRAN0 (0x01) +#define MCF_GPIO_CLRAN_CLRAN1 (0x02) +#define MCF_GPIO_CLRAN_CLRAN2 (0x04) +#define MCF_GPIO_CLRAN_CLRAN3 (0x08) +#define MCF_GPIO_CLRAN_CLRAN4 (0x10) +#define MCF_GPIO_CLRAN_CLRAN5 (0x20) +#define MCF_GPIO_CLRAN_CLRAN6 (0x40) +#define MCF_GPIO_CLRAN_CLRAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRAS */ +#define MCF_GPIO_CLRAS_CLRAS0 (0x01) +#define MCF_GPIO_CLRAS_CLRAS1 (0x02) +#define MCF_GPIO_CLRAS_CLRAS2 (0x04) +#define MCF_GPIO_CLRAS_CLRAS3 (0x08) +#define MCF_GPIO_CLRAS_CLRAS4 (0x10) +#define MCF_GPIO_CLRAS_CLRAS5 (0x20) +#define MCF_GPIO_CLRAS_CLRAS6 (0x40) +#define MCF_GPIO_CLRAS_CLRAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRQS */ +#define MCF_GPIO_CLRQS_CLRQS0 (0x01) +#define MCF_GPIO_CLRQS_CLRQS1 (0x02) +#define MCF_GPIO_CLRQS_CLRQS2 (0x04) +#define MCF_GPIO_CLRQS_CLRQS3 (0x08) +#define MCF_GPIO_CLRQS_CLRQS4 (0x10) +#define MCF_GPIO_CLRQS_CLRQS5 (0x20) +#define MCF_GPIO_CLRQS_CLRQS6 (0x40) +#define MCF_GPIO_CLRQS_CLRQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRTA */ +#define MCF_GPIO_CLRTA_CLRTA0 (0x01) +#define MCF_GPIO_CLRTA_CLRTA1 (0x02) +#define MCF_GPIO_CLRTA_CLRTA2 (0x04) +#define MCF_GPIO_CLRTA_CLRTA3 (0x08) +#define MCF_GPIO_CLRTA_CLRTA4 (0x10) +#define MCF_GPIO_CLRTA_CLRTA5 (0x20) +#define MCF_GPIO_CLRTA_CLRTA6 (0x40) +#define MCF_GPIO_CLRTA_CLRTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRTC */ +#define MCF_GPIO_CLRTC_CLRTC0 (0x01) +#define MCF_GPIO_CLRTC_CLRTC1 (0x02) +#define MCF_GPIO_CLRTC_CLRTC2 (0x04) +#define MCF_GPIO_CLRTC_CLRTC3 (0x08) +#define MCF_GPIO_CLRTC_CLRTC4 (0x10) +#define MCF_GPIO_CLRTC_CLRTC5 (0x20) +#define MCF_GPIO_CLRTC_CLRTC6 (0x40) +#define MCF_GPIO_CLRTC_CLRTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRTD */ +#define MCF_GPIO_CLRTD_CLRTD0 (0x01) +#define MCF_GPIO_CLRTD_CLRTD1 (0x02) +#define MCF_GPIO_CLRTD_CLRTD2 (0x04) +#define MCF_GPIO_CLRTD_CLRTD3 (0x08) +#define MCF_GPIO_CLRTD_CLRTD4 (0x10) +#define MCF_GPIO_CLRTD_CLRTD5 (0x20) +#define MCF_GPIO_CLRTD_CLRTD6 (0x40) +#define MCF_GPIO_CLRTD_CLRTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRUA */ +#define MCF_GPIO_CLRUA_CLRUA0 (0x01) +#define MCF_GPIO_CLRUA_CLRUA1 (0x02) +#define MCF_GPIO_CLRUA_CLRUA2 (0x04) +#define MCF_GPIO_CLRUA_CLRUA3 (0x08) +#define MCF_GPIO_CLRUA_CLRUA4 (0x10) +#define MCF_GPIO_CLRUA_CLRUA5 (0x20) +#define MCF_GPIO_CLRUA_CLRUA6 (0x40) +#define MCF_GPIO_CLRUA_CLRUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRUB */ +#define MCF_GPIO_CLRUB_CLRUB0 (0x01) +#define MCF_GPIO_CLRUB_CLRUB1 (0x02) +#define MCF_GPIO_CLRUB_CLRUB2 (0x04) +#define MCF_GPIO_CLRUB_CLRUB3 (0x08) +#define MCF_GPIO_CLRUB_CLRUB4 (0x10) +#define MCF_GPIO_CLRUB_CLRUB5 (0x20) +#define MCF_GPIO_CLRUB_CLRUB6 (0x40) +#define MCF_GPIO_CLRUB_CLRUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRUC */ +#define MCF_GPIO_CLRUC_CLRUC0 (0x01) +#define MCF_GPIO_CLRUC_CLRUC1 (0x02) +#define MCF_GPIO_CLRUC_CLRUC2 (0x04) +#define MCF_GPIO_CLRUC_CLRUC3 (0x08) +#define MCF_GPIO_CLRUC_CLRUC4 (0x10) +#define MCF_GPIO_CLRUC_CLRUC5 (0x20) +#define MCF_GPIO_CLRUC_CLRUC6 (0x40) +#define MCF_GPIO_CLRUC_CLRUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRDD */ +#define MCF_GPIO_CLRDD_CLRDD0 (0x01) +#define MCF_GPIO_CLRDD_CLRDD1 (0x02) +#define MCF_GPIO_CLRDD_CLRDD2 (0x04) +#define MCF_GPIO_CLRDD_CLRDD3 (0x08) +#define MCF_GPIO_CLRDD_CLRDD4 (0x10) +#define MCF_GPIO_CLRDD_CLRDD5 (0x20) +#define MCF_GPIO_CLRDD_CLRDD6 (0x40) +#define MCF_GPIO_CLRDD_CLRDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRLD */ +#define MCF_GPIO_CLRLD_CLRLD0 (0x01) +#define MCF_GPIO_CLRLD_CLRLD1 (0x02) +#define MCF_GPIO_CLRLD_CLRLD2 (0x04) +#define MCF_GPIO_CLRLD_CLRLD3 (0x08) +#define MCF_GPIO_CLRLD_CLRLD4 (0x10) +#define MCF_GPIO_CLRLD_CLRLD5 (0x20) +#define MCF_GPIO_CLRLD_CLRLD6 (0x40) +#define MCF_GPIO_CLRLD_CLRLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRGP */ +#define MCF_GPIO_CLRGP_CLRGP0 (0x01) +#define MCF_GPIO_CLRGP_CLRGP1 (0x02) +#define MCF_GPIO_CLRGP_CLRGP2 (0x04) +#define MCF_GPIO_CLRGP_CLRGP3 (0x08) +#define MCF_GPIO_CLRGP_CLRGP4 (0x10) +#define MCF_GPIO_CLRGP_CLRGP5 (0x20) +#define MCF_GPIO_CLRGP_CLRGP6 (0x40) +#define MCF_GPIO_CLRGP_CLRGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTIPAR */ +#define MCF_GPIO_PTIPAR_PTIPAR0 (0x01) +#define MCF_GPIO_PTIPAR_PTIPAR1 (0x02) +#define MCF_GPIO_PTIPAR_PTIPAR2 (0x04) +#define MCF_GPIO_PTIPAR_PTIPAR3 (0x08) +#define MCF_GPIO_PTIPAR_PTIPAR4 (0x10) +#define MCF_GPIO_PTIPAR_PTIPAR5 (0x20) +#define MCF_GPIO_PTIPAR_PTIPAR6 (0x40) +#define MCF_GPIO_PTIPAR_PTIPAR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTJPAR */ +#define MCF_GPIO_PTJPAR_PTJPAR0 (0x01) +#define MCF_GPIO_PTJPAR_PTJPAR1 (0x02) +#define MCF_GPIO_PTJPAR_PTJPAR2 (0x04) +#define MCF_GPIO_PTJPAR_PTJPAR3 (0x08) +#define MCF_GPIO_PTJPAR_PTJPAR4 (0x10) +#define MCF_GPIO_PTJPAR_PTJPAR5 (0x20) +#define MCF_GPIO_PTJPAR_PTJPAR6 (0x40) +#define MCF_GPIO_PTJPAR_PTJPAR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PNQPAR */ +#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x0003)<<14) +#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x0004) +#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x0010) +#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x0040) +#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x0100) +#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x0400) +#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000) +#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000) +#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x0008) +#define MCF_GPIO_PNQPAR_IRQ1_PWM1 (0x000C) + +/* Bit definitions and macros for MCF_GPIO_PANPAR */ +#define MCF_GPIO_PANPAR_PANPAR0 (0x01) +#define MCF_GPIO_PANPAR_PANPAR1 (0x02) +#define MCF_GPIO_PANPAR_PANPAR2 (0x04) +#define MCF_GPIO_PANPAR_PANPAR3 (0x08) +#define MCF_GPIO_PANPAR_PANPAR4 (0x10) +#define MCF_GPIO_PANPAR_PANPAR5 (0x20) +#define MCF_GPIO_PANPAR_PANPAR6 (0x40) +#define MCF_GPIO_PANPAR_PANPAR7 (0x80) +#define MCF_GPIO_PANPAR_AN0_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN1_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN2_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN3_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN4_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN5_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN6_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN7_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN0_AN0 (0x01) +#define MCF_GPIO_PANPAR_AN1_AN1 (0x02) +#define MCF_GPIO_PANPAR_AN2_AN2 (0x04) +#define MCF_GPIO_PANPAR_AN3_AN3 (0x08) +#define MCF_GPIO_PANPAR_AN4_AN4 (0x10) +#define MCF_GPIO_PANPAR_AN5_AN5 (0x20) +#define MCF_GPIO_PANPAR_AN6_AN6 (0x40) +#define MCF_GPIO_PANPAR_AN7_AN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PASPAR */ +#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PASPAR_PASPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PASPAR_SCL_GPIO (0x00) +#define MCF_GPIO_PASPAR_SDA_GPIO (0x00) +#define MCF_GPIO_PASPAR_SYNCA_GPIO (0x00) +#define MCF_GPIO_PASPAR_SYNCB_GPIO (0x00) +#define MCF_GPIO_PASPAR_SCL_SCL (0x01) +#define MCF_GPIO_PASPAR_SDA_SDA (0x04) +#define MCF_GPIO_PASPAR_SYNCA_SYNCA (0x10) +#define MCF_GPIO_PASPAR_SYNCB_SYNCB (0x40) +#define MCF_GPIO_PASPAR_SCL_CANTX (0x02) +#define MCF_GPIO_PASPAR_SDA_CANRX (0x08) +#define MCF_GPIO_PASPAR_SYNCA_CANRX (0x20) +#define MCF_GPIO_PASPAR_SYNCB_CANTX (0x80) +#define MCF_GPIO_PASPAR_SCL_TXD2 (0x30) +#define MCF_GPIO_PASPAR_SDA_RXD2 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PQSPAR */ +#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x0003)<<0) +#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x0003)<<12) +#define MCF_GPIO_PQSPAR_DOUT_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_DIN_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_SCK_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS0_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS1_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS2_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS3_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_DOUT_DOUT (0x0001) +#define MCF_GPIO_PQSPAR_DIN_DIN (0x0004) +#define MCF_GPIO_PQSPAR_SCK_SCK (0x0010) +#define MCF_GPIO_PQSPAR_CS0_CS0 (0x0040) +#define MCF_GPIO_PQSPAR_CS1_CS1 (0x0100) +#define MCF_GPIO_PQSPAR_CS2_CS2 (0x0400) +#define MCF_GPIO_PQSPAR_CS3_CS3 (0x1000) +#define MCF_GPIO_PQSPAR_DOUT_CANTX (0x0002) +#define MCF_GPIO_PQSPAR_DIN_CANRX (0x0008) +#define MCF_GPIO_PQSPAR_SCK_SCL (0x0020) +#define MCF_GPIO_PQSPAR_CS0_SDA (0x0080) +#define MCF_GPIO_PQSPAR_CS3_SYNCA (0x2000) +#define MCF_GPIO_PQSPAR_DOUT_TXD1 (0x0003) +#define MCF_GPIO_PQSPAR_DIN_RXD1 (0x000C) +#define MCF_GPIO_PQSPAR_SCK_RTS1 (0x0030) +#define MCF_GPIO_PQSPAR_CS0_CTS1 (0x00C0) +#define MCF_GPIO_PQSPAR_CS3_SYNCB (0x3000) + +/* Bit definitions and macros for MCF_GPIO_PTAPAR */ +#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PTAPAR_ICOC0_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC1_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC2_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC3_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC0_ICOC0 (0x01) +#define MCF_GPIO_PTAPAR_ICOC1_ICOC1 (0x04) +#define MCF_GPIO_PTAPAR_ICOC2_ICOC2 (0x10) +#define MCF_GPIO_PTAPAR_ICOC3_ICOC3 (0x40) +#define MCF_GPIO_PTAPAR_ICOC0_PWM1 (0x02) +#define MCF_GPIO_PTAPAR_ICOC1_PWM3 (0x08) +#define MCF_GPIO_PTAPAR_ICOC2_PWM5 (0x20) +#define MCF_GPIO_PTAPAR_ICOC3_PWM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTCPAR */ +#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PTCPAR_TIN0_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN1_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN2_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN3_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN0_TIN0 (0x01) +#define MCF_GPIO_PTCPAR_TIN1_TIN1 (0x04) +#define MCF_GPIO_PTCPAR_TIN2_TIN2 (0x10) +#define MCF_GPIO_PTCPAR_TIN3_TIN3 (0x40) +#define MCF_GPIO_PTCPAR_TIN0_TOUT0 (0x02) +#define MCF_GPIO_PTCPAR_TIN1_TOUT1 (0x08) +#define MCF_GPIO_PTCPAR_TIN2_TOUT2 (0x20) +#define MCF_GPIO_PTCPAR_TIN3_TOUT3 (0x80) +#define MCF_GPIO_PTCPAR_TIN0_PWM0 (0x03) +#define MCF_GPIO_PTCPAR_TIN1_PWM2 (0x0C) +#define MCF_GPIO_PTCPAR_TIN2_PWM4 (0x30) +#define MCF_GPIO_PTCPAR_TIN3_PWM6 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PTDPAR */ +#define MCF_GPIO_PTDPAR_PTDPAR0 (0x01) +#define MCF_GPIO_PTDPAR_PTDPAR1 (0x02) +#define MCF_GPIO_PTDPAR_PTDPAR2 (0x04) +#define MCF_GPIO_PTDPAR_PTDPAR3 (0x08) +#define MCF_GPIO_PTDPAR_PWM1_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM3_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM5_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM7_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM1_PWM1 (0x01) +#define MCF_GPIO_PTDPAR_PWM3_PWM3 (0x02) +#define MCF_GPIO_PTDPAR_PWM5_PWM5 (0x04) +#define MCF_GPIO_PTDPAR_PWM7_PWM7 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PTEPAR */ +#define MCF_GPIO_PTEPAR_PTEPAR0 (0x01) +#define MCF_GPIO_PTEPAR_PTEPAR1 (0x02) +#define MCF_GPIO_PTEPAR_PTEPAR2 (0x04) +#define MCF_GPIO_PTEPAR_PTEPAR3 (0x08) +#define MCF_GPIO_PTEPAR_PTEPAR4 (0x10) +#define MCF_GPIO_PTEPAR_PTEPAR5 (0x20) +#define MCF_GPIO_PTEPAR_PTEPAR6 (0x40) +#define MCF_GPIO_PTEPAR_PTEPAR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTFPAR */ +#define MCF_GPIO_PTFPAR_PTFPAR0 (0x01) +#define MCF_GPIO_PTFPAR_PTFPAR1 (0x02) +#define MCF_GPIO_PTFPAR_PTFPAR2 (0x04) +#define MCF_GPIO_PTFPAR_PTFPAR3 (0x08) +#define MCF_GPIO_PTFPAR_PTFPAR4 (0x10) +#define MCF_GPIO_PTFPAR_PTFPAR5 (0x20) +#define MCF_GPIO_PTFPAR_PTFPAR6 (0x40) +#define MCF_GPIO_PTFPAR_PTFPAR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTGPAR */ +#define MCF_GPIO_PTGPAR_PTGPAR0 (0x01) +#define MCF_GPIO_PTGPAR_PTGPAR1 (0x02) +#define MCF_GPIO_PTGPAR_PTGPAR2 (0x04) +#define MCF_GPIO_PTGPAR_PTGPAR3 (0x08) +#define MCF_GPIO_PTGPAR_PTGPAR4 (0x10) +#define MCF_GPIO_PTGPAR_PTGPAR5 (0x20) +#define MCF_GPIO_PTGPAR_PTGPAR6 (0x40) +#define MCF_GPIO_PTGPAR_PTGPAR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTHPAR */ +#define MCF_GPIO_PTHPAR_PTHPAR0(x) (((x)&0x0003)<<0) +#define MCF_GPIO_PTHPAR_PTHPAR1(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PTHPAR_PTHPAR2(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PTHPAR_PTHPAR3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PTHPAR_PTHPAR4(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PTHPAR_PTHPAR5(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PTHPAR_PTHPAR6(x) (((x)&0x0003)<<12) + + +/* Bit definitions and macros for MCF_GPIO_PUAPAR */ +#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PUAPAR_TXD0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_RXD0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_RTS0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_CTS0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_TXD0_TXD0 (0x01) +#define MCF_GPIO_PUAPAR_RXD0_RXD0 (0x04) +#define MCF_GPIO_PUAPAR_RTS0_RTS0 (0x10) +#define MCF_GPIO_PUAPAR_CTS0_CTS0 (0x40) +#define MCF_GPIO_PUAPAR_RTS0_CANTX (0x20) +#define MCF_GPIO_PUAPAR_CTS0_CANRX (0x80) + +/* Bit definitions and macros for MCF_GPIO_PUBPAR */ +#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PUBPAR_TXD1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_RXD1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_RTS1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_CTS1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_TXD1_TXD1 (0x01) +#define MCF_GPIO_PUBPAR_RXD1_RXD1 (0x04) +#define MCF_GPIO_PUBPAR_RTS1_RTS1 (0x10) +#define MCF_GPIO_PUBPAR_CTS1_CTS1 (0x40) +#define MCF_GPIO_PUBPAR_RTS1_SYNCB (0x20) +#define MCF_GPIO_PUBPAR_CTS1_SYNCA (0x80) +#define MCF_GPIO_PUBPAR_RTS1_TXD2 (0x30) +#define MCF_GPIO_PUBPAR_CTS1_RXD2 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PUCPAR */ +#define MCF_GPIO_PUCPAR_PUCPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PUCPAR_PUCPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PUCPAR_PUCPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PUCPAR_PUCPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PUCPAR_TXD2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_RXD2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_RTS2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_CTS2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_TXD2_TXD2 (0x01) +#define MCF_GPIO_PUCPAR_RXD2_RXD2 (0x02) +#define MCF_GPIO_PUCPAR_RTS2_RTS2 (0x04) +#define MCF_GPIO_PUCPAR_CTS2_CTS2 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDPAR */ +#define MCF_GPIO_PDDPAR_PDDPAR0 (0x01) +#define MCF_GPIO_PDDPAR_PDDPAR1 (0x02) +#define MCF_GPIO_PDDPAR_PDDPAR2 (0x04) +#define MCF_GPIO_PDDPAR_PDDPAR3 (0x08) +#define MCF_GPIO_PDDPAR_PDDPAR4 (0x10) +#define MCF_GPIO_PDDPAR_PDDPAR5 (0x20) +#define MCF_GPIO_PDDPAR_PDDPAR6 (0x40) +#define MCF_GPIO_PDDPAR_PDDPAR7 (0x80) +#define MCF_GPIO_PDDPAR_PDD0_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD1_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD2_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD3_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD4_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD5_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD6_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD7_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD0_PST0 (0x01) +#define MCF_GPIO_PDDPAR_PDD1_PST1 (0x02) +#define MCF_GPIO_PDDPAR_PDD2_PST2 (0x04) +#define MCF_GPIO_PDDPAR_PDD3_PST3 (0x08) +#define MCF_GPIO_PDDPAR_PDD4_DDATA0 (0x10) +#define MCF_GPIO_PDDPAR_PDD5_DDATA1 (0x20) +#define MCF_GPIO_PDDPAR_PDD6_DDATA2 (0x40) +#define MCF_GPIO_PDDPAR_PDD7_DDATA3 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PLDPAR */ +#define MCF_GPIO_PLDPAR_PLDPAR0 (0x01) +#define MCF_GPIO_PLDPAR_PLDPAR1 (0x02) +#define MCF_GPIO_PLDPAR_PLDPAR2 (0x04) +#define MCF_GPIO_PLDPAR_PLDPAR3 (0x08) +#define MCF_GPIO_PLDPAR_PLDPAR4 (0x10) +#define MCF_GPIO_PLDPAR_PLDPAR5 (0x20) +#define MCF_GPIO_PLDPAR_PLDPAR6 (0x40) +#define MCF_GPIO_PLDPAR_ACTLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_LNKLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_SPDLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_DUPLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_COLLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_RXLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_TXLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_ACTLED_ACTLED (0x01) +#define MCF_GPIO_PLDPAR_LNKLED_LNKLED (0x02) +#define MCF_GPIO_PLDPAR_SPDLED_SPDLED (0x04) +#define MCF_GPIO_PLDPAR_DUPLED_DUPLED (0x08) +#define MCF_GPIO_PLDPAR_COLLED_COLLED (0x10) +#define MCF_GPIO_PLDPAR_RXLED_RXLED (0x20) +#define MCF_GPIO_PLDPAR_TXLED_TXLED (0x40) + +/* Bit definitions and macros for MCF_GPIO_PGPPAR */ +#define MCF_GPIO_PGPPAR_PGPPAR0 (0x01) +#define MCF_GPIO_PGPPAR_PGPPAR1 (0x02) +#define MCF_GPIO_PGPPAR_PGPPAR2 (0x04) +#define MCF_GPIO_PGPPAR_PGPPAR3 (0x08) +#define MCF_GPIO_PGPPAR_PGPPAR4 (0x10) +#define MCF_GPIO_PGPPAR_PGPPAR5 (0x20) +#define MCF_GPIO_PGPPAR_PGPPAR6 (0x40) +#define MCF_GPIO_PGPPAR_PGPPAR7 (0x80) +#define MCF_GPIO_PGPPAR_IRQ8_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ9_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ10_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ11_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ12_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ13_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ14_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ15_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ8_IRQ8 (0x01) +#define MCF_GPIO_PGPPAR_IRQ9_IRQ9 (0x02) +#define MCF_GPIO_PGPPAR_IRQ10_IRQ10 (0x04) +#define MCF_GPIO_PGPPAR_IRQ11_IRQ11 (0x08) +#define MCF_GPIO_PGPPAR_IRQ12_IRQ12 (0x10) +#define MCF_GPIO_PGPPAR_IRQ13_IRQ13 (0x30) +#define MCF_GPIO_PGPPAR_IRQ14_IRQ14 (0x40) +#define MCF_GPIO_PGPPAR_IRQ15_IRQ15 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PWOR */ +#define MCF_GPIO_PWOR_PWOR0 (0x0001) +#define MCF_GPIO_PWOR_PWOR1 (0x0002) +#define MCF_GPIO_PWOR_PWOR2 (0x0004) +#define MCF_GPIO_PWOR_PWOR3 (0x0008) +#define MCF_GPIO_PWOR_PWOR4 (0x0010) +#define MCF_GPIO_PWOR_PWOR5 (0x0020) +#define MCF_GPIO_PWOR_PWOR6 (0x0040) +#define MCF_GPIO_PWOR_PWOR7 (0x0080) +#define MCF_GPIO_PWOR_PWOR8 (0x0100) +#define MCF_GPIO_PWOR_PWOR9 (0x0200) +#define MCF_GPIO_PWOR_PWOR10 (0x0400) +#define MCF_GPIO_PWOR_PWOR11 (0x0800) +#define MCF_GPIO_PWOR_PWOR12 (0x1000) +#define MCF_GPIO_PWOR_PWOR13 (0x2000) +#define MCF_GPIO_PWOR_PWOR14 (0x4000) +#define MCF_GPIO_PWOR_PWOR15 (0x8000) + +/* Bit definitions and macros for MCF_GPIO_PDSRH */ +#define MCF_GPIO_PDSRH_PDSR32 (0x0001) +#define MCF_GPIO_PDSRH_PDSR33 (0x0002) +#define MCF_GPIO_PDSRH_PDSR34 (0x0004) +#define MCF_GPIO_PDSRH_PDSR35 (0x0008) +#define MCF_GPIO_PDSRH_PDSR36 (0x0010) +#define MCF_GPIO_PDSRH_PDSR37 (0x0020) +#define MCF_GPIO_PDSRH_PDSR38 (0x0040) +#define MCF_GPIO_PDSRH_PDSR39 (0x0080) +#define MCF_GPIO_PDSRH_PDSR40 (0x0100) +#define MCF_GPIO_PDSRH_PDSR41 (0x0200) +#define MCF_GPIO_PDSRH_PDSR42 (0x0400) +#define MCF_GPIO_PDSRH_PDSR43 (0x0800) +#define MCF_GPIO_PDSRH_PDSR44 (0x1000) +#define MCF_GPIO_PDSRH_PDSR45 (0x2000) +#define MCF_GPIO_PDSRH_PDSR46 (0x4000) +#define MCF_GPIO_PDSRH_PDSR47 (0x8000) + +/* Bit definitions and macros for MCF_GPIO_PDSRL */ +#define MCF_GPIO_PDSRL_PDSR0 (0x00000001) +#define MCF_GPIO_PDSRL_PDSR1 (0x00000002) +#define MCF_GPIO_PDSRL_PDSR2 (0x00000004) +#define MCF_GPIO_PDSRL_PDSR3 (0x00000008) +#define MCF_GPIO_PDSRL_PDSR4 (0x00000010) +#define MCF_GPIO_PDSRL_PDSR5 (0x00000020) +#define MCF_GPIO_PDSRL_PDSR6 (0x00000040) +#define MCF_GPIO_PDSRL_PDSR7 (0x00000080) +#define MCF_GPIO_PDSRL_PDSR8 (0x00000100) +#define MCF_GPIO_PDSRL_PDSR9 (0x00000200) +#define MCF_GPIO_PDSRL_PDSR10 (0x00000400) +#define MCF_GPIO_PDSRL_PDSR11 (0x00000800) +#define MCF_GPIO_PDSRL_PDSR12 (0x00001000) +#define MCF_GPIO_PDSRL_PDSR13 (0x00002000) +#define MCF_GPIO_PDSRL_PDSR14 (0x00004000) +#define MCF_GPIO_PDSRL_PDSR15 (0x00008000) +#define MCF_GPIO_PDSRL_PDSR16 (0x00010000) +#define MCF_GPIO_PDSRL_PDSR17 (0x00020000) +#define MCF_GPIO_PDSRL_PDSR18 (0x00040000) +#define MCF_GPIO_PDSRL_PDSR19 (0x00080000) +#define MCF_GPIO_PDSRL_PDSR20 (0x00100000) +#define MCF_GPIO_PDSRL_PDSR21 (0x00200000) +#define MCF_GPIO_PDSRL_PDSR22 (0x00400000) +#define MCF_GPIO_PDSRL_PDSR23 (0x00800000) +#define MCF_GPIO_PDSRL_PDSR24 (0x01000000) +#define MCF_GPIO_PDSRL_PDSR25 (0x02000000) +#define MCF_GPIO_PDSRL_PDSR26 (0x04000000) +#define MCF_GPIO_PDSRL_PDSR27 (0x08000000) +#define MCF_GPIO_PDSRL_PDSR28 (0x10000000) +#define MCF_GPIO_PDSRL_PDSR29 (0x20000000) +#define MCF_GPIO_PDSRL_PDSR30 (0x40000000) +#define MCF_GPIO_PDSRL_PDSR31 (0x80000000) + +/********************************************************************* +* +* ColdFire Integration Module (CIM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CIM_RCR (*(vuint8 *)(&__IPSBAR[0x110000])) +#define MCF_CIM_RSR (*(vuint8 *)(&__IPSBAR[0x110001])) +#define MCF_CIM_CCR (*(vuint16*)(&__IPSBAR[0x110004])) +#define MCF_CIM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) +#define MCF_CIM_RCON (*(vuint16*)(&__IPSBAR[0x110008])) +#define MCF_CIM_CIR (*(vuint16*)(&__IPSBAR[0x11000A])) + +/* Bit definitions and macros for MCF_CIM_RCR */ +#define MCF_CIM_RCR_LVDE (0x01) +#define MCF_CIM_RCR_LVDRE (0x04) +#define MCF_CIM_RCR_LVDIE (0x08) +#define MCF_CIM_RCR_LVDF (0x10) +#define MCF_CIM_RCR_FRCRSTOUT (0x40) +#define MCF_CIM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for MCF_CIM_RSR */ +#define MCF_CIM_RSR_LOL (0x01) +#define MCF_CIM_RSR_LOC (0x02) +#define MCF_CIM_RSR_EXT (0x04) +#define MCF_CIM_RSR_POR (0x08) +#define MCF_CIM_RSR_WDR (0x10) +#define MCF_CIM_RSR_SOFT (0x20) +#define MCF_CIM_RSR_LVD (0x40) + +/* Bit definitions and macros for MCF_CIM_CCR */ +#define MCF_CIM_CCR_LOAD (0x8000) +#define MCF_CIM_CCR_EZPORT (0x05) +#define MCF_CIM_CCR_SCHIP (0x06) +#define MCF_CIM_CCR_MODE(x) (((x)&0x7)<<8) + +/* Bit definitions and macros for MCF_CIM_LPCR */ +#define MCF_CIM_LPCR_LVDSE (0x02) +#define MCF_CIM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF_CIM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF_CIM_LPCR_LPMD_STOP (0xC0) +#define MCF_CIM_LPCR_LPMD_WAIT (0x80) +#define MCF_CIM_LPCR_LPMD_DOZE (0x40) +#define MCF_CIM_LPCR_LPMD_RUN (0x00) + +/* Bit definitions and macros for MCF_CIM_RCON */ +#define MCF_CIM_RCON_RLOAD (0x0020) + +/********************************************************************* +* +* Clock Module (CLOCK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CLOCK_SYNCR (*(vuint16*)(&__IPSBAR[0x120000])) +#define MCF_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002])) +#define MCF_CLOCK_LPCR (*(vuint8 *)(&__IPSBAR[0x120007])) +#define MCF_CLOCK_CCHR (*(vuint8 *)(&__IPSBAR[0x120008])) +#define MCF_CLOCK_CCLR (*(vuint8 *)(&__IPSBAR[0x120009])) +#define MCF_CLOCK_RTCDR (*(vuint32*)(&__IPSBAR[0x12000C])) +#define MCF_CLOCK_RTCCR (*(vuint8*)(&__IPSBAR[0x120012])) + +/* Bit definitions and macros for MCF_CLOCK_SYNCR */ +#define MCF_CLOCK_SYNCR_PLLEN (0x0001) +#define MCF_CLOCK_SYNCR_PLLMODE (0x0002) +#define MCF_CLOCK_SYNCR_CLKSRC (0x0004) +#define MCF_CLOCK_SYNCR_FWKUP (0x0020) +#define MCF_CLOCK_SYNCR_DISCLK (0x0040) +#define MCF_CLOCK_SYNCR_LOCEN (0x0080) +#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) +#define MCF_CLOCK_SYNCR_LOCRE (0x0800) +#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) +#define MCF_CLOCK_SYNCR_LOLRE (0x8000) + +/* Bit definitions and macros for MCF_CLOCK_SYNSR */ +#define MCF_CLOCK_SYNSR_LOCS (0x04) +#define MCF_CLOCK_SYNSR_LOCK (0x08) +#define MCF_CLOCK_SYNSR_LOCKS (0x10) +#define MCF_CLOCK_SYNSR_CRYOSC (0x20) +#define MCF_CLOCK_SYNSR_OCOSC (0x40) +#define MCF_CLOCK_SYNSR_EXTOSC (0x80) + +/* Bit definitions and macros for MCF_CLOCK_LPCR */ +#define MCF_CLOCK_LPCR_LPD(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_CLOCK_CCHR */ +#define MCF_CLOCK_CCHR_PFD(x) (((x)&0x07)<<0) + +/* Bit definitions and macros for MCF_CLOCK_CCHR */ +#define MCF_CLOCK_CCLR_PRIM_OSC (0x00) +#define MCF_CLOCK_CCLR_REL_OSC (0x01) +#define MCF_CLOCK_CCLR_SEC_OSC (0x02) +#define MCF_CLOCK_CCLR_SEC1_OSC (0x03) + +/* Bit definitions and macros for MCF_CLOCK_RTCDR */ +#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CLOCK_RTCCR */ +#define MCF_CLOCK_RTCCR_RTCSEL 0x01U +#define MCF_CLOCK_RTCCR_LPEN 0x02U +#define MCF_CLOCK_RTCCR_REFS 0x04U +#define MCF_CLOCK_RTCCR_KHZEN 0x08U +#define MCF_CLOCK_RTCCR_OSCEN 0x10U +#define MCF_CLOCK_RTCCR_EXTALEN 0x40U + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR0 (*(vuint16*)(&__IPSBAR[0x130000])) +#define MCF_EPORT_EPDDR0 (*(vuint8 *)(&__IPSBAR[0x130002])) +#define MCF_EPORT_EPIER0 (*(vuint8 *)(&__IPSBAR[0x130003])) +#define MCF_EPORT_EPDR0 (*(vuint8 *)(&__IPSBAR[0x130004])) +#define MCF_EPORT_EPPDR0 (*(vuint8 *)(&__IPSBAR[0x130005])) +#define MCF_EPORT_EPFR0 (*(vuint8 *)(&__IPSBAR[0x130006])) + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define MCF_EPORT_EPPAR_EPPA8(x) (((x)&0x0003)<<0) +#define MCF_EPORT_EPPAR_EPPA9(x) (((x)&0x0003)<<2) +#define MCF_EPORT_EPPAR_EPPA10(x) (((x)&0x0003)<<4) +#define MCF_EPORT_EPPAR_EPPA11(x) (((x)&0x0003)<<6) +#define MCF_EPORT_EPPAR_EPPA12(x) (((x)&0x0003)<<8) +#define MCF_EPORT_EPPAR_EPPA13(x) (((x)&0x0003)<<10) +#define MCF_EPORT_EPPAR_EPPA14(x) (((x)&0x0003)<<12) +#define MCF_EPORT_EPPAR_EPPA15(x) (((x)&0x0003)<<14) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (1) +#define MCF_EPORT_EPPAR_FALLING (2) +#define MCF_EPORT_EPPAR_BOTH (3) +#define MCF_EPORT_EPPAR_EPPA15_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA15_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA15_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA15_BOTH (0xC000) +#define MCF_EPORT_EPPAR_EPPA14_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA14_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA14_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA14_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA13_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA13_RISING (0x0400) +#define MCF_EPORT_EPPAR_EPPA13_FALLING (0x0800) +#define MCF_EPORT_EPPAR_EPPA13_BOTH (0x0C00) +#define MCF_EPORT_EPPAR_EPPA12_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA12_RISING (0x0100) +#define MCF_EPORT_EPPAR_EPPA12_FALLING (0x0200) +#define MCF_EPORT_EPPAR_EPPA12_BOTH (0x0300) +#define MCF_EPORT_EPPAR_EPPA11_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA11_RISING (0x0040) +#define MCF_EPORT_EPPAR_EPPA11_FALLING (0x0080) +#define MCF_EPORT_EPPAR_EPPA11_BOTH (0x00C0) +#define MCF_EPORT_EPPAR_EPPA10_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA10_RISING (0x0010) +#define MCF_EPORT_EPPAR_EPPA10_FALLING (0x0020) +#define MCF_EPORT_EPPAR_EPPA10_BOTH (0x0030) +#define MCF_EPORT_EPPAR_EPPA9_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA9_RISING (0x0004) +#define MCF_EPORT_EPPAR_EPPA9_FALLING (0x0008) +#define MCF_EPORT_EPPAR_EPPA9_BOTH (0x000C) +#define MCF_EPORT_EPPAR_EPPA8_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA8_RISING (0x0001) +#define MCF_EPORT_EPPAR_EPPA8_FALLING (0x0002) +#define MCF_EPORT_EPPAR_EPPA8_BOTH (0x0003) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x02) +#define MCF_EPORT_EPDDR_EPDD2 (0x04) +#define MCF_EPORT_EPDDR_EPDD3 (0x08) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) +#define MCF_EPORT_EPDDR_EPDD8 (0x01) +#define MCF_EPORT_EPDDR_EPDD9 (0x02) +#define MCF_EPORT_EPDDR_EPDD10 (0x04) +#define MCF_EPORT_EPDDR_EPDD11 (0x08) +#define MCF_EPORT_EPDDR_EPDD12 (0x10) +#define MCF_EPORT_EPDDR_EPDD13 (0x20) +#define MCF_EPORT_EPDDR_EPDD14 (0x40) +#define MCF_EPORT_EPDDR_EPDD15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x02) +#define MCF_EPORT_EPIER_EPIE2 (0x04) +#define MCF_EPORT_EPIER_EPIE3 (0x08) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) +#define MCF_EPORT_EPIER_EPIE8 (0x01) +#define MCF_EPORT_EPIER_EPIE9 (0x02) +#define MCF_EPORT_EPIER_EPIE10 (0x04) +#define MCF_EPORT_EPIER_EPIE11 (0x08) +#define MCF_EPORT_EPIER_EPIE12 (0x10) +#define MCF_EPORT_EPIER_EPIE13 (0x20) +#define MCF_EPORT_EPIER_EPIE14 (0x40) +#define MCF_EPORT_EPIER_EPIE15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x02) +#define MCF_EPORT_EPDR_EPD2 (0x04) +#define MCF_EPORT_EPDR_EPD3 (0x08) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) +#define MCF_EPORT_EPDR_EPD8 (0x01) +#define MCF_EPORT_EPDR_EPD9 (0x02) +#define MCF_EPORT_EPDR_EPD10 (0x04) +#define MCF_EPORT_EPDR_EPD11 (0x08) +#define MCF_EPORT_EPDR_EPD12 (0x10) +#define MCF_EPORT_EPDR_EPD13 (0x20) +#define MCF_EPORT_EPDR_EPD14 (0x40) +#define MCF_EPORT_EPDR_EPD15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x02) +#define MCF_EPORT_EPPDR_EPPD2 (0x04) +#define MCF_EPORT_EPPDR_EPPD3 (0x08) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) +#define MCF_EPORT_EPPDR_EPPD8 (0x01) +#define MCF_EPORT_EPPDR_EPPD9 (0x02) +#define MCF_EPORT_EPPDR_EPPD10 (0x04) +#define MCF_EPORT_EPPDR_EPPD11 (0x08) +#define MCF_EPORT_EPPDR_EPPD12 (0x10) +#define MCF_EPORT_EPPDR_EPPD13 (0x20) +#define MCF_EPORT_EPPDR_EPPD14 (0x40) +#define MCF_EPORT_EPPDR_EPPD15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x02) +#define MCF_EPORT_EPFR_EPF2 (0x04) +#define MCF_EPORT_EPFR_EPF3 (0x08) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) +#define MCF_EPORT_EPFR_EPF8 (0x01) +#define MCF_EPORT_EPFR_EPF9 (0x02) +#define MCF_EPORT_EPFR_EPF10 (0x04) +#define MCF_EPORT_EPFR_EPF11 (0x08) +#define MCF_EPORT_EPFR_EPF12 (0x10) +#define MCF_EPORT_EPFR_EPF13 (0x20) +#define MCF_EPORT_EPFR_EPF14 (0x40) +#define MCF_EPORT_EPFR_EPF15 (0x80) + + +/********************************************************************* +* +* Backup Watchdog Timer Module (BWT) +* +*********************************************************************/ + +#define MCF_BWT_WCR (*(vuint16*)(&__IPSBAR[0x140000])) +#define MCF_BWT_WMR (*(vuint16*)(&__IPSBAR[0x140002])) +#define MCF_BWT_WCNTR (*(vuint16*)(&__IPSBAR[0x140004])) +#define MCF_BWT_WSR (*(vuint16*)(&__IPSBAR[0x140006])) + +/* Bit definitions and macros for MCF_BWT_WCR */ +#define MCF_BWT_WCR_EN 0x01 +#define MCF_BWT_WCR_DOZE 0x04 +#define MCF_BWT_WCR_WAIT 0x08 +#define MCF_BWT_WCR_STOP 0x10 + +#define MCF_BWT_WSR_SEQ1 0x5555 +#define MCF_BWT_WSR_SEQ2 0xAAAA + +//MPR: TODO this Modules is new in mcf52258 vs. mcf52235 and some macros must be written first + +/********************************************************************* +* +* Programmable Interrupt Timer Modules (PIT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000])) +#define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002])) +#define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004])) +#define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000])) +#define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002])) +#define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004])) +#define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000+((x)*0x10000)])) +#define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002+((x)*0x10000)])) +#define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004+((x)*0x10000)])) + +/* Bit definitions and macros for MCF_PIT_PCSR */ +#define MCF_PIT_PCSR_EN (0x0001) +#define MCF_PIT_PCSR_RLD (0x0002) +#define MCF_PIT_PCSR_PIF (0x0004) +#define MCF_PIT_PCSR_PIE (0x0008) +#define MCF_PIT_PCSR_OVW (0x0010) +#define MCF_PIT_PCSR_HALTED (0x0020) +#define MCF_PIT_PCSR_DOZE (0x0040) +#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) + +/* Bit definitions and macros for MCF_PIT_PMR */ +#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PIT_PCNTR */ +#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0) + +/********************************************************************* +* +* Analog-to-Digital Converter (ADC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_ADC_CTRL1 (*(vuint16*)(&__IPSBAR[0x190000])) +#define MCF_ADC_CTRL2 (*(vuint16*)(&__IPSBAR[0x190002])) +#define MCF_ADC_ADZCC (*(vuint16*)(&__IPSBAR[0x190004])) +#define MCF_ADC_ADLST1 (*(vuint16*)(&__IPSBAR[0x190006])) +#define MCF_ADC_ADLST2 (*(vuint16*)(&__IPSBAR[0x190008])) +#define MCF_ADC_ADSDIS (*(vuint16*)(&__IPSBAR[0x19000A])) +#define MCF_ADC_ADSTAT (*(vuint16*)(&__IPSBAR[0x19000C])) +#define MCF_ADC_ADLSTAT (*(vuint16*)(&__IPSBAR[0x19000E])) +#define MCF_ADC_ADZCSTAT (*(vuint16*)(&__IPSBAR[0x190010])) +#define MCF_ADC_ADRSLT0 (*(vuint16*)(&__IPSBAR[0x190012])) +#define MCF_ADC_ADRSLT1 (*(vuint16*)(&__IPSBAR[0x190014])) +#define MCF_ADC_ADRSLT2 (*(vuint16*)(&__IPSBAR[0x190016])) +#define MCF_ADC_ADRSLT3 (*(vuint16*)(&__IPSBAR[0x190018])) +#define MCF_ADC_ADRSLT4 (*(vuint16*)(&__IPSBAR[0x19001A])) +#define MCF_ADC_ADRSLT5 (*(vuint16*)(&__IPSBAR[0x19001C])) +#define MCF_ADC_ADRSLT6 (*(vuint16*)(&__IPSBAR[0x19001E])) +#define MCF_ADC_ADRSLT7 (*(vuint16*)(&__IPSBAR[0x190020])) +#define MCF_ADC_ADRSLT(x) (*(vuint16*)(&__IPSBAR[0x190012+((x)*0x002)])) +#define MCF_ADC_ADLLMT0 (*(vuint16*)(&__IPSBAR[0x190022])) +#define MCF_ADC_ADLLMT1 (*(vuint16*)(&__IPSBAR[0x190024])) +#define MCF_ADC_ADLLMT2 (*(vuint16*)(&__IPSBAR[0x190026])) +#define MCF_ADC_ADLLMT3 (*(vuint16*)(&__IPSBAR[0x190028])) +#define MCF_ADC_ADLLMT4 (*(vuint16*)(&__IPSBAR[0x19002A])) +#define MCF_ADC_ADLLMT5 (*(vuint16*)(&__IPSBAR[0x19002C])) +#define MCF_ADC_ADLLMT6 (*(vuint16*)(&__IPSBAR[0x19002E])) +#define MCF_ADC_ADLLMT7 (*(vuint16*)(&__IPSBAR[0x190030])) +#define MCF_ADC_ADLLMT(x) (*(vuint16*)(&__IPSBAR[0x190022+((x)*0x002)])) +#define MCF_ADC_ADHLMT0 (*(vuint16*)(&__IPSBAR[0x190032])) +#define MCF_ADC_ADHLMT1 (*(vuint16*)(&__IPSBAR[0x190034])) +#define MCF_ADC_ADHLMT2 (*(vuint16*)(&__IPSBAR[0x190036])) +#define MCF_ADC_ADHLMT3 (*(vuint16*)(&__IPSBAR[0x190038])) +#define MCF_ADC_ADHLMT4 (*(vuint16*)(&__IPSBAR[0x19003A])) +#define MCF_ADC_ADHLMT5 (*(vuint16*)(&__IPSBAR[0x19003C])) +#define MCF_ADC_ADHLMT6 (*(vuint16*)(&__IPSBAR[0x19003E])) +#define MCF_ADC_ADHLMT7 (*(vuint16*)(&__IPSBAR[0x190040])) +#define MCF_ADC_ADHLMT(x) (*(vuint16*)(&__IPSBAR[0x190032+((x)*0x002)])) +#define MCF_ADC_ADOFS0 (*(vuint16*)(&__IPSBAR[0x190042])) +#define MCF_ADC_ADOFS1 (*(vuint16*)(&__IPSBAR[0x190044])) +#define MCF_ADC_ADOFS2 (*(vuint16*)(&__IPSBAR[0x190046])) +#define MCF_ADC_ADOFS3 (*(vuint16*)(&__IPSBAR[0x190048])) +#define MCF_ADC_ADOFS4 (*(vuint16*)(&__IPSBAR[0x19004A])) +#define MCF_ADC_ADOFS5 (*(vuint16*)(&__IPSBAR[0x19004C])) +#define MCF_ADC_ADOFS6 (*(vuint16*)(&__IPSBAR[0x19004E])) +#define MCF_ADC_ADOFS7 (*(vuint16*)(&__IPSBAR[0x190050])) +#define MCF_ADC_ADOFS(x) (*(vuint16*)(&__IPSBAR[0x190042+((x)*0x002)])) +#define MCF_ADC_POWER (*(vuint16*)(&__IPSBAR[0x190052])) +#define MCF_ADC_CAL (*(vuint16*)(&__IPSBAR[0x190054])) + +/* Bit definitions and macros for MCF_ADC_CTRL1 */ +#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x0007)<<0) +#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0x000F)<<4) +#define MCF_ADC_CTRL1_HLMTIE (0x0100) +#define MCF_ADC_CTRL1_LLMTIE (0x0200) +#define MCF_ADC_CTRL1_ZCIE (0x0400) +#define MCF_ADC_CTRL1_EOSIE0 (0x0800) +#define MCF_ADC_CTRL1_SYNC0 (0x1000) +#define MCF_ADC_CTRL1_START0 (0x2000) +#define MCF_ADC_CTRL1_STOP0 (0x4000) + +/* Bit definitions and macros for MCF_ADC_CTRL2 */ +#define MCF_ADC_CTRL2_DIV(x) (((x)&0x001F)<<0) +#define MCF_ADC_CTRL2_SIMULT (0x0020) +#define MCF_ADC_CTRL2_EOSIE1 (0x0800) +#define MCF_ADC_CTRL2_SYNC1 (0x1000) +#define MCF_ADC_CTRL2_START1 (0x2000) +#define MCF_ADC_CTRL2_STOP1 (0x4000) + +/* Bit definitions and macros for MCF_ADC_ADZCC */ +#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x0003)<<0) +#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x0003)<<2) +#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x0003)<<4) +#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x0003)<<6) +#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x0003)<<8) +#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x0003)<<10) +#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x0003)<<12) +#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for MCF_ADC_ADLST1 */ +#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x0007)<<0) +#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x0007)<<4) +#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x0007)<<8) +#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x0007)<<12) + +/* Bit definitions and macros for MCF_ADC_ADLST2 */ +#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x0007)<<0) +#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x0007)<<4) +#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x0007)<<8) +#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x0007)<<12) + +/* Bit definitions and macros for MCF_ADC_ADSDIS */ +#define MCF_ADC_ADSDIS_DS0 (0x0001) +#define MCF_ADC_ADSDIS_DS1 (0x0002) +#define MCF_ADC_ADSDIS_DS2 (0x0004) +#define MCF_ADC_ADSDIS_DS3 (0x0008) +#define MCF_ADC_ADSDIS_DS4 (0x0010) +#define MCF_ADC_ADSDIS_DS5 (0x0020) +#define MCF_ADC_ADSDIS_DS6 (0x0040) +#define MCF_ADC_ADSDIS_DS7 (0x0080) + +/* Bit definitions and macros for MCF_ADC_ADSTAT */ +#define MCF_ADC_ADSTAT_RDY0 (0x0001) +#define MCF_ADC_ADSTAT_RDY1 (0x0002) +#define MCF_ADC_ADSTAT_RDY2 (0x0004) +#define MCF_ADC_ADSTAT_RDY3 (0x0008) +#define MCF_ADC_ADSTAT_RDY4 (0x0010) +#define MCF_ADC_ADSTAT_RDY5 (0x0020) +#define MCF_ADC_ADSTAT_RDY6 (0x0040) +#define MCF_ADC_ADSTAT_RDY7 (0x0080) +#define MCF_ADC_ADSTAT_HLMT (0x0100) +#define MCF_ADC_ADSTAT_LLMTI (0x0200) +#define MCF_ADC_ADSTAT_ZCI (0x0400) +#define MCF_ADC_ADSTAT_EOSI (0x0800) +#define MCF_ADC_ADSTAT_CIP (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADLSTAT */ +#define MCF_ADC_ADLSTAT_LLS0 (0x0001) +#define MCF_ADC_ADLSTAT_LLS1 (0x0002) +#define MCF_ADC_ADLSTAT_LLS2 (0x0004) +#define MCF_ADC_ADLSTAT_LLS3 (0x0008) +#define MCF_ADC_ADLSTAT_LLS4 (0x0010) +#define MCF_ADC_ADLSTAT_LLS5 (0x0020) +#define MCF_ADC_ADLSTAT_LLS6 (0x0040) +#define MCF_ADC_ADLSTAT_LLS7 (0x0080) +#define MCF_ADC_ADLSTAT_HLS0 (0x0100) +#define MCF_ADC_ADLSTAT_HLS1 (0x0200) +#define MCF_ADC_ADLSTAT_HLS2 (0x0400) +#define MCF_ADC_ADLSTAT_HLS3 (0x0800) +#define MCF_ADC_ADLSTAT_HLS4 (0x1000) +#define MCF_ADC_ADLSTAT_HLS5 (0x2000) +#define MCF_ADC_ADLSTAT_HLS6 (0x4000) +#define MCF_ADC_ADLSTAT_HLS7 (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADZCSTAT */ +#define MCF_ADC_ADZCSTAT_ZCS0 (0x0001) +#define MCF_ADC_ADZCSTAT_ZCS1 (0x0002) +#define MCF_ADC_ADZCSTAT_ZCS2 (0x0004) +#define MCF_ADC_ADZCSTAT_ZCS3 (0x0008) +#define MCF_ADC_ADZCSTAT_ZCS4 (0x0010) +#define MCF_ADC_ADZCSTAT_ZCS5 (0x0020) +#define MCF_ADC_ADZCSTAT_ZCS6 (0x0040) +#define MCF_ADC_ADZCSTAT_ZCS7 (0x0080) + +/* Bit definitions and macros for MCF_ADC_ADRSLT */ +#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0x0FFF)<<3) +#define MCF_ADC_ADRSLT_SEXT (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADLLMT */ +#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0x0FFF)<<3) + +/* Bit definitions and macros for MCF_ADC_ADHLMT */ +#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0x0FFF)<<3) + +/* Bit definitions and macros for MCF_ADC_ADOFS */ +#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0x0FFF)<<3) + +/* Bit definitions and macros for MCF_ADC_POWER */ +#define MCF_ADC_POWER_PD0 (0x0001) +#define MCF_ADC_POWER_PD1 (0x0002) +#define MCF_ADC_POWER_PD2 (0x0004) +#define MCF_ADC_POWER_APD (0x0008) +#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x003F)<<4) +#define MCF_ADC_POWER_PSTS0 (0x0400) +#define MCF_ADC_POWER_PSTS1 (0x0800) +#define MCF_ADC_POWER_PSTS2 (0x1000) +#define MCF_ADC_POWER_ASTBY (0x8000) + +/* Bit definitions and macros for MCF_ADC_CAL */ +#define MCF_ADC_CAL_CAL0 (0x0001) +#define MCF_ADC_CAL_CRS0 (0x0002) +#define MCF_ADC_CAL_CAL1 (0x0004) +#define MCF_ADC_CAL_CRS1 (0x0008) + +/********************************************************************* +* +* General Purpose Timer (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000])) +#define MCF_GPT_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001])) +#define MCF_GPT_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002])) +#define MCF_GPT_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003])) +#define MCF_GPT_GPTCNT (*(vuint16*)(&__IPSBAR[0x1A0004])) +#define MCF_GPT_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006])) +#define MCF_GPT_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008])) +#define MCF_GPT_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009])) +#define MCF_GPT_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B])) +#define MCF_GPT_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C])) +#define MCF_GPT_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D])) +#define MCF_GPT_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E])) +#define MCF_GPT_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F])) +#define MCF_GPT_GPTC0 (*(vuint16*)(&__IPSBAR[0x1A0010])) +#define MCF_GPT_GPTC1 (*(vuint16*)(&__IPSBAR[0x1A0012])) +#define MCF_GPT_GPTC2 (*(vuint16*)(&__IPSBAR[0x1A0014])) +#define MCF_GPT_GPTC3 (*(vuint16*)(&__IPSBAR[0x1A0016])) +#define MCF_GPT_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1A0010+((x)*0x002)])) +#define MCF_GPT_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018])) +#define MCF_GPT_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019])) +#define MCF_GPT_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1A001A])) +#define MCF_GPT_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D])) +#define MCF_GPT_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E])) + +/* Bit definitions and macros for MCF_GPT_GPTIOS */ +#define MCF_GPT_GPTIOS_IOS0 (0x01) +#define MCF_GPT_GPTIOS_IOS1 (0x02) +#define MCF_GPT_GPTIOS_IOS2 (0x04) +#define MCF_GPT_GPTIOS_IOS3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTCFORC */ +#define MCF_GPT_GPTCFORC_FOC0 (0x01) +#define MCF_GPT_GPTCFORC_FOC1 (0x02) +#define MCF_GPT_GPTCFORC_FOC2 (0x04) +#define MCF_GPT_GPTCFORC_FOC3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTOC3D */ +#define MCF_GPT_GPTOC3D_OC3D0 (0x01) +#define MCF_GPT_GPTOC3D_OC3D1 (0x02) +#define MCF_GPT_GPTOC3D_OC3D2 (0x04) +#define MCF_GPT_GPTOC3D_OC3D3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTSCR1 */ +#define MCF_GPT_GPTSCR1_TFFCA (0x10) +#define MCF_GPT_GPTSCR1_GPTEN (0x80) + +/* Bit definitions and macros for MCF_GPT_GPTTOV */ +#define MCF_GPT_GPTTOV_TOV0 (0x01) +#define MCF_GPT_GPTTOV_TOV1 (0x02) +#define MCF_GPT_GPTTOV_TOV2 (0x04) +#define MCF_GPT_GPTTOV_TOV3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTCTL1 */ +#define MCF_GPT_GPTCTL1_OL0 (0x01) +#define MCF_GPT_GPTCTL1_OM0 (0x02) +#define MCF_GPT_GPTCTL1_OL1 (0x04) +#define MCF_GPT_GPTCTL1_OM1 (0x08) +#define MCF_GPT_GPTCTL1_OL2 (0x10) +#define MCF_GPT_GPTCTL1_OM2 (0x20) +#define MCF_GPT_GPTCTL1_OL3 (0x40) +#define MCF_GPT_GPTCTL1_OM3 (0x80) +#define MCF_GPT_GPTCTL1_OUTPUT3_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT3_TOGGLE ((0x40)) +#define MCF_GPT_GPTCTL1_OUTPUT3_CLEAR ((0x80)) +#define MCF_GPT_GPTCTL1_OUTPUT3_SET ((0xC0)) +#define MCF_GPT_GPTCTL1_OUTPUT2_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT2_TOGGLE ((0x10)) +#define MCF_GPT_GPTCTL1_OUTPUT2_CLEAR ((0x20)) +#define MCF_GPT_GPTCTL1_OUTPUT2_SET ((0x30)) +#define MCF_GPT_GPTCTL1_OUTPUT1_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT1_TOGGLE ((0x04)) +#define MCF_GPT_GPTCTL1_OUTPUT1_CLEAR ((0x08)) +#define MCF_GPT_GPTCTL1_OUTPUT1_SET ((0x0C)) +#define MCF_GPT_GPTCTL1_OUTPUT0_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT0_TOGGLE ((0x01)) +#define MCF_GPT_GPTCTL1_OUTPUT0_CLEAR ((0x02)) +#define MCF_GPT_GPTCTL1_OUTPUT0_SET ((0x03)) + +/* Bit definitions and macros for MCF_GPT_GPTCTL2 */ +#define MCF_GPT_GPTCTL2_EDG0A (0x01) +#define MCF_GPT_GPTCTL2_EDG0B (0x02) +#define MCF_GPT_GPTCTL2_EDG1A (0x04) +#define MCF_GPT_GPTCTL2_EDG1B (0x08) +#define MCF_GPT_GPTCTL2_EDG2A (0x10) +#define MCF_GPT_GPTCTL2_EDG2B (0x20) +#define MCF_GPT_GPTCTL2_EDG3A (0x40) +#define MCF_GPT_GPTCTL2_EDG3B (0x80) +#define MCF_GPT_GPTCTL2_INPUT3_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT3_RISING ((0x40)) +#define MCF_GPT_GPTCTL2_INPUT3_FALLING ((0x80)) +#define MCF_GPT_GPTCTL2_INPUT3_ANY ((0xC0)) +#define MCF_GPT_GPTCTL2_INPUT2_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT2_RISING ((0x10)) +#define MCF_GPT_GPTCTL2_INPUT2_FALLING ((0x20)) +#define MCF_GPT_GPTCTL2_INPUT2_ANY ((0x30)) +#define MCF_GPT_GPTCTL2_INPUT1_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT1_RISING ((0x04)) +#define MCF_GPT_GPTCTL2_INPUT1_FALLING ((0x08)) +#define MCF_GPT_GPTCTL2_INPUT1_ANY ((0x0C)) +#define MCF_GPT_GPTCTL2_INPUT0_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT0_RISING ((0x01)) +#define MCF_GPT_GPTCTL2_INPUT0_FALLING ((0x02)) +#define MCF_GPT_GPTCTL2_INPUT0_ANY ((0x03)) + +/* Bit definitions and macros for MCF_GPT_GPTIE */ +#define MCF_GPT_GPTIE_CI0 (0x01) +#define MCF_GPT_GPTIE_CI1 (0x02) +#define MCF_GPT_GPTIE_CI2 (0x04) +#define MCF_GPT_GPTIE_CI3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTSCR2 */ +#define MCF_GPT_GPTSCR2_PR(x) (((x)&0x07)<<0) +#define MCF_GPT_GPTSCR2_TCRE (0x08) +#define MCF_GPT_GPTSCR2_RDPT (0x10) +#define MCF_GPT_GPTSCR2_PUPT (0x20) +#define MCF_GPT_GPTSCR2_TOI (0x80) +#define MCF_GPT_GPTSCR2_PR_1 ((0x00)) +#define MCF_GPT_GPTSCR2_PR_2 ((0x01)) +#define MCF_GPT_GPTSCR2_PR_4 ((0x02)) +#define MCF_GPT_GPTSCR2_PR_8 ((0x03)) +#define MCF_GPT_GPTSCR2_PR_16 ((0x04)) +#define MCF_GPT_GPTSCR2_PR_32 ((0x05)) +#define MCF_GPT_GPTSCR2_PR_64 ((0x06)) +#define MCF_GPT_GPTSCR2_PR_128 ((0x07)) + +/* Bit definitions and macros for MCF_GPT_GPTFLG1 */ +#define MCF_GPT_GPTFLG1_CF0 (0x01) +#define MCF_GPT_GPTFLG1_CF1 (0x02) +#define MCF_GPT_GPTFLG1_CF2 (0x04) +#define MCF_GPT_GPTFLG1_CF3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTFLG2 */ +#define MCF_GPT_GPTFLG2_CF0 (0x01) +#define MCF_GPT_GPTFLG2_CF1 (0x02) +#define MCF_GPT_GPTFLG2_CF2 (0x04) +#define MCF_GPT_GPTFLG2_CF3 (0x08) +#define MCF_GPT_GPTFLG2_TOF (0x80) + +/* Bit definitions and macros for MCF_GPT_GPTC */ +#define MCF_GPT_GPTC_CCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_GPT_GPTPACTL */ +#define MCF_GPT_GPTPACTL_PAI (0x01) +#define MCF_GPT_GPTPACTL_PAOVI (0x02) +#define MCF_GPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) +#define MCF_GPT_GPTPACTL_PEDGE (0x10) +#define MCF_GPT_GPTPACTL_PAMOD (0x20) +#define MCF_GPT_GPTPACTL_PAE (0x40) +#define MCF_GPT_GPTPACTL_CLK_GPTPR ((0x00)) +#define MCF_GPT_GPTPACTL_CLK_PACLK ((0x01)) +#define MCF_GPT_GPTPACTL_CLK_PACLK_256 ((0x02)) +#define MCF_GPT_GPTPACTL_CLK_PACLK_65536 ((0x03)) + +/* Bit definitions and macros for MCF_GPT_GPTPAFLG */ +#define MCF_GPT_GPTPAFLG_PAIF (0x01) +#define MCF_GPT_GPTPAFLG_PAOVF (0x02) + +/* Bit definitions and macros for MCF_GPT_GPTPACNT */ +#define MCF_GPT_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_GPT_GPTPORT */ +#define MCF_GPT_GPTPORT_PORTT(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_GPT_GPTDDR */ +#define MCF_GPT_GPTDDR_DDRT0 (0x01) +#define MCF_GPT_GPTDDR_DDRT1 (0x02) +#define MCF_GPT_GPTDDR_DDRT2 (0x04) +#define MCF_GPT_GPTDDR_DDRT3 (0x08) + +/********************************************************************* +* +* Pulse Width Modulation (PWM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PWM_PWME (*(vuint8 *)(&__IPSBAR[0x1B0000])) +#define MCF_PWM_PWMPOL (*(vuint8 *)(&__IPSBAR[0x1B0001])) +#define MCF_PWM_PWMCLK (*(vuint8 *)(&__IPSBAR[0x1B0002])) +#define MCF_PWM_PWMPRCLK (*(vuint8 *)(&__IPSBAR[0x1B0003])) +#define MCF_PWM_PWMCAE (*(vuint8 *)(&__IPSBAR[0x1B0004])) +#define MCF_PWM_PWMCTL (*(vuint8 *)(&__IPSBAR[0x1B0005])) +#define MCF_PWM_PWMSCLA (*(vuint8 *)(&__IPSBAR[0x1B0008])) +#define MCF_PWM_PWMSCLB (*(vuint8 *)(&__IPSBAR[0x1B0009])) +#define MCF_PWM_PWMCNT0 (*(vuint8 *)(&__IPSBAR[0x1B000C])) +#define MCF_PWM_PWMCNT1 (*(vuint8 *)(&__IPSBAR[0x1B000D])) +#define MCF_PWM_PWMCNT2 (*(vuint8 *)(&__IPSBAR[0x1B000E])) +#define MCF_PWM_PWMCNT3 (*(vuint8 *)(&__IPSBAR[0x1B000F])) +#define MCF_PWM_PWMCNT4 (*(vuint8 *)(&__IPSBAR[0x1B0010])) +#define MCF_PWM_PWMCNT5 (*(vuint8 *)(&__IPSBAR[0x1B0011])) +#define MCF_PWM_PWMCNT6 (*(vuint8 *)(&__IPSBAR[0x1B0012])) +#define MCF_PWM_PWMCNT7 (*(vuint8 *)(&__IPSBAR[0x1B0013])) +#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(&__IPSBAR[0x1B000C+((x)*0x001)])) +#define MCF_PWM_PWMPER0 (*(vuint8 *)(&__IPSBAR[0x1B0014])) +#define MCF_PWM_PWMPER1 (*(vuint8 *)(&__IPSBAR[0x1B0015])) +#define MCF_PWM_PWMPER2 (*(vuint8 *)(&__IPSBAR[0x1B0016])) +#define MCF_PWM_PWMPER3 (*(vuint8 *)(&__IPSBAR[0x1B0017])) +#define MCF_PWM_PWMPER4 (*(vuint8 *)(&__IPSBAR[0x1B0018])) +#define MCF_PWM_PWMPER5 (*(vuint8 *)(&__IPSBAR[0x1B0019])) +#define MCF_PWM_PWMPER6 (*(vuint8 *)(&__IPSBAR[0x1B001A])) +#define MCF_PWM_PWMPER7 (*(vuint8 *)(&__IPSBAR[0x1B001B])) +#define MCF_PWM_PWMPER(x) (*(vuint8 *)(&__IPSBAR[0x1B0014+((x)*0x001)])) +#define MCF_PWM_PWMDTY0 (*(vuint8 *)(&__IPSBAR[0x1B001C])) +#define MCF_PWM_PWMDTY1 (*(vuint8 *)(&__IPSBAR[0x1B001D])) +#define MCF_PWM_PWMDTY2 (*(vuint8 *)(&__IPSBAR[0x1B001E])) +#define MCF_PWM_PWMDTY3 (*(vuint8 *)(&__IPSBAR[0x1B001F])) +#define MCF_PWM_PWMDTY4 (*(vuint8 *)(&__IPSBAR[0x1B0020])) +#define MCF_PWM_PWMDTY5 (*(vuint8 *)(&__IPSBAR[0x1B0021])) +#define MCF_PWM_PWMDTY6 (*(vuint8 *)(&__IPSBAR[0x1B0022])) +#define MCF_PWM_PWMDTY7 (*(vuint8 *)(&__IPSBAR[0x1B0023])) +#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(&__IPSBAR[0x1B001C+((x)*0x001)])) +#define MCF_PWM_PWMSDN (*(vuint8 *)(&__IPSBAR[0x1B0024])) + +/* Bit definitions and macros for MCF_PWM_PWME */ +#define MCF_PWM_PWME_PWME0 (0x01) +#define MCF_PWM_PWME_PWME1 (0x02) +#define MCF_PWM_PWME_PWME2 (0x04) +#define MCF_PWM_PWME_PWME3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMPOL */ +#define MCF_PWM_PWMPOL_PPOL0 (0x01) +#define MCF_PWM_PWMPOL_PPOL1 (0x02) +#define MCF_PWM_PWMPOL_PPOL2 (0x04) +#define MCF_PWM_PWMPOL_PPOL3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMCLK */ +#define MCF_PWM_PWMCLK_PCLK0 (0x01) +#define MCF_PWM_PWMCLK_PCLK1 (0x02) +#define MCF_PWM_PWMCLK_PCLK2 (0x04) +#define MCF_PWM_PWMCLK_PCLK3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMPRCLK */ +#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x07)<<0) +#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF_PWM_PWMCAE */ +#define MCF_PWM_PWMCAE_CAE0 (0x01) +#define MCF_PWM_PWMCAE_CAE1 (0x02) +#define MCF_PWM_PWMCAE_CAE2 (0x04) +#define MCF_PWM_PWMCAE_CAE3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMCTL */ +#define MCF_PWM_PWMCTL_PFRZ (0x04) +#define MCF_PWM_PWMCTL_PSWAI (0x08) +#define MCF_PWM_PWMCTL_CON01 (0x10) +#define MCF_PWM_PWMCTL_CON23 (0x20) + +/* Bit definitions and macros for MCF_PWM_PWMSCLA */ +#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMSCLB */ +#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMCNT */ +#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMPER */ +#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMDTY */ +#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMSDN */ +#define MCF_PWM_PWMSDN_SDNEN (0x01) +#define MCF_PWM_PWMSDN_PWM7IL (0x02) +#define MCF_PWM_PWMSDN_PWM7IN (0x04) +#define MCF_PWM_PWMSDN_LVL (0x10) +#define MCF_PWM_PWMSDN_RESTART (0x20) +#define MCF_PWM_PWMSDN_IE (0x40) +#define MCF_PWM_PWMSDN_IF (0x80) + +/********************************************************************* +* +* FlexCAN Module (CAN) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CAN_CANMCR (*(vuint32*)(&__IPSBAR[0x1C0000])) +#define MCF_CAN_CANCTRL (*(vuint32*)(&__IPSBAR[0x1C0004])) +#define MCF_CAN_TIMER (*(vuint32*)(&__IPSBAR[0x1C0008])) +#define MCF_CAN_RXGMASK (*(vuint32*)(&__IPSBAR[0x1C0010])) +#define MCF_CAN_RX14MASK (*(vuint32*)(&__IPSBAR[0x1C0014])) +#define MCF_CAN_RX15MASK (*(vuint32*)(&__IPSBAR[0x1C0018])) +#define MCF_CAN_ERRCNT (*(vuint32*)(&__IPSBAR[0x1C001C])) +#define MCF_CAN_ERRSTAT (*(vuint32*)(&__IPSBAR[0x1C0020])) +#define MCF_CAN_IMASK (*(vuint32*)(&__IPSBAR[0x1C0028])) +#define MCF_CAN_IFLAG (*(vuint32*)(&__IPSBAR[0x1C0030])) + +/* Bit definitions and macros for MCF_CAN_CANMCR */ +#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) +#define MCF_CAN_CANMCR_SUPV (0x00800000) +#define MCF_CAN_CANMCR_FRZACK (0x01000000) +#define MCF_CAN_CANMCR_SOFTRST (0x02000000) +#define MCF_CAN_CANMCR_HALT (0x10000000) +#define MCF_CAN_CANMCR_FRZ (0x40000000) +#define MCF_CAN_CANMCR_MDIS (0x80000000) + +/* Bit definitions and macros for MCF_CAN_CANCTRL */ +#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) +#define MCF_CAN_CANCTRL_LOM (0x00000008) +#define MCF_CAN_CANCTRL_LBUF (0x00000010) +#define MCF_CAN_CANCTRL_TSYNC (0x00000020) +#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) +#define MCF_CAN_CANCTRL_SAMP (0x00000080) +#define MCF_CAN_CANCTRL_LPB (0x00001000) +#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) +#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) +#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) +#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) +#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) +#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) +#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_CAN_TIMER */ +#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RXGMASK */ +#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX14MASK */ +#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX15MASK */ +#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_ERRCNT */ +#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) +#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for MCF_CAN_ERRSTAT */ +#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) +#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) +#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) +#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) +#define MCF_CAN_ERRSTAT_TXRX (0x00000040) +#define MCF_CAN_ERRSTAT_IDLE (0x00000080) +#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) +#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) +#define MCF_CAN_ERRSTAT_STFERR (0x00000400) +#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) +#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) +#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) +#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) +#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) +#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) +#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) + +/* Bit definitions and macros for MCF_CAN_IMASK */ +#define MCF_CAN_IMASK_BUF(x) (1< + +/********************************************************************/ + +/* + * File: mcf5xxx.h + * Purpose: Definitions common to all ColdFire processors + * + * Notes: + */ + +#ifndef _CPU_MCF5XXX_H +#define _CPU_MCF5XXX_H + +/***********************************************************************/ +/* + * The basic data types + */ + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16; /* 16 bits */ +typedef unsigned long int uint32; /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16; /* 16 bits */ +typedef signed long int int32; /* 32 bits */ + +typedef volatile uint8 vuint8; /* 8 bits */ +typedef volatile uint16 vuint16; /* 16 bits */ +typedef volatile uint32 vuint32; /* 32 bits */ + +/***********************************************************************/ +/* + * Common M68K & ColdFire definitions + * + ***********************************************************************/ + +#define ADDRESS uint32 +#define INSTRUCTION uint16 +#define ILLEGAL 0x4AFC +#define CPU_WORD_SIZE 16 + +#define MCF5XXX_SR_T (0x8000) +#define MCF5XXX_SR_S (0x2000) +#define MCF5XXX_SR_M (0x1000) +#define MCF5XXX_SR_IPL (0x0700) +#define MCF5XXX_SR_IPL_0 (0x0000) +#define MCF5XXX_SR_IPL_1 (0x0100) +#define MCF5XXX_SR_IPL_2 (0x0200) +#define MCF5XXX_SR_IPL_3 (0x0300) +#define MCF5XXX_SR_IPL_4 (0x0400) +#define MCF5XXX_SR_IPL_5 (0x0500) +#define MCF5XXX_SR_IPL_6 (0x0600) +#define MCF5XXX_SR_IPL_7 (0x0700) +#define MCF5XXX_SR_X (0x0010) +#define MCF5XXX_SR_N (0x0008) +#define MCF5XXX_SR_Z (0x0004) +#define MCF5XXX_SR_V (0x0002) +#define MCF5XXX_SR_C (0x0001) + +#define MCF5XXX_CACR_CENB (0x80000000) +#define MCF5XXX_CACR_CPDI (0x10000000) +#define MCF5XXX_CACR_CPD (0x10000000) +#define MCF5XXX_CACR_CFRZ (0x08000000) +#define MCF5XXX_CACR_CINV (0x01000000) +#define MCF5XXX_CACR_DIDI (0x00800000) +#define MCF5XXX_CACR_DISD (0x00400000) +#define MCF5XXX_CACR_INVI (0x00200000) +#define MCF5XXX_CACR_INVD (0x00100000) +#define MCF5XXX_CACR_CEIB (0x00000400) +#define MCF5XXX_CACR_DCM_WR (0x00000000) +#define MCF5XXX_CACR_DCM_CB (0x00000100) +#define MCF5XXX_CACR_DCM_IP (0x00000200) +#define MCF5XXX_CACR_DCM (0x00000200) +#define MCF5XXX_CACR_DCM_II (0x00000300) +#define MCF5XXX_CACR_DBWE (0x00000100) +#define MCF5XXX_CACR_DWP (0x00000020) +#define MCF5XXX_CACR_EUST (0x00000010) +#define MCF5XXX_CACR_CLNF_00 (0x00000000) +#define MCF5XXX_CACR_CLNF_01 (0x00000002) +#define MCF5XXX_CACR_CLNF_10 (0x00000004) +#define MCF5XXX_CACR_CLNF_11 (0x00000006) + +#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) +#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) +#define MCF5XXX_ACR_EN (0x00008000) +#define MCF5XXX_ACR_SM_USER (0x00000000) +#define MCF5XXX_ACR_SM_SUPER (0x00002000) +#define MCF5XXX_ACR_SM_IGNORE (0x00006000) +#define MCF5XXX_ACR_ENIB (0x00000080) +#define MCF5XXX_ACR_CM (0x00000040) +#define MCF5XXX_ACR_DCM_WR (0x00000000) +#define MCF5XXX_ACR_DCM_CB (0x00000020) +#define MCF5XXX_ACR_DCM_IP (0x00000040) +#define MCF5XXX_ACR_DCM_II (0x00000060) +#define MCF5XXX_ACR_CM (0x00000040) +#define MCF5XXX_ACR_BWE (0x00000020) +#define MCF5XXX_ACR_WP (0x00000004) + +#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) +#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) +#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) +#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) +#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) +#define MCF5XXX_RAMBAR_WP (0x00000100) +#define MCF5XXX_RAMBAR_CI (0x00000020) +#define MCF5XXX_RAMBAR_SC (0x00000010) +#define MCF5XXX_RAMBAR_SD (0x00000008) +#define MCF5XXX_RAMBAR_UC (0x00000004) +#define MCF5XXX_RAMBAR_UD (0x00000002) +#define MCF5XXX_RAMBAR_V (0x00000001) + +/***********************************************************************/ +/* + * The ColdFire family of processors has a simplified exception stack + * frame that looks like the following: + * + * 3322222222221111 111111 + * 1098765432109876 5432109876543210 + * 8 +----------------+----------------+ + * | Program Counter | + * 4 +----------------+----------------+ + * |FS/Fmt/Vector/FS| SR | + * SP --> 0 +----------------+----------------+ + * + * The stack self-aligns to a 4-byte boundary at an exception, with + * the FS/Fmt/Vector/FS field indicating the size of the adjustment + * (SP += 0,1,2,3 bytes). + */ + +#define MCF5XXX_RD_SF_FORMAT(PTR) \ + ((*((uint16 *)(PTR)) >> 12) & 0x00FF) + +#define MCF5XXX_RD_SF_VECTOR(PTR) \ + ((*((uint16 *)(PTR)) >> 2) & 0x00FF) + +#define MCF5XXX_RD_SF_FS(PTR) \ + ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) + +#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1) +#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1) + +/********************************************************************/ +/* + * Functions provided by mcf5xxx.s + */ + +int asm_set_ipl (uint32); +void mcf5xxx_wr_cacr (uint32); +void mcf5xxx_wr_acr0 (uint32); +void mcf5xxx_wr_acr1 (uint32); +void mcf5xxx_wr_acr2 (uint32); +void mcf5xxx_wr_acr3 (uint32); +void mcf5xxx_wr_other_a7 (uint32); +void mcf5xxx_wr_other_sp (uint32); +void mcf5xxx_wr_vbr (uint32); +void mcf5xxx_wr_macsr (uint32); +void mcf5xxx_wr_mask (uint32); +void mcf5xxx_wr_acc0 (uint32); +void mcf5xxx_wr_accext01 (uint32); +void mcf5xxx_wr_accext23 (uint32); +void mcf5xxx_wr_acc1 (uint32); +void mcf5xxx_wr_acc2 (uint32); +void mcf5xxx_wr_acc3 (uint32); +void mcf5xxx_wr_sr (uint32); +void mcf5xxx_wr_rambar0 (uint32); +void mcf5xxx_wr_rambar1 (uint32); +void mcf5xxx_wr_mbar (uint32); +void mcf5xxx_wr_mbar0 (uint32); +void mcf5xxx_wr_mbar1 (uint32); + +/********************************************************************/ + +#endif /* _CPU_MCF5XXX_H */ + + +/********************************************************************/ +/* + * Memory map definitions from linker command files + */ +extern char __IPSBAR[]; + +/********************************************************************* +* +* Watchdog Timer Modules (WTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_WCR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140000))) +#define MCF5235_WMR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140002))) +#define MCF5235_WCNTR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140004))) +#define MCF5235_WSR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140006))) + +/* Bit definitions and macros for MCF5235_WTM_WCR */ +#define MCF5235_WCR_EN (0x0001) +#define MCF5235_WCR_HALTED (0x0002) +#define MCF5235_WCR_DOZE (0x0004) +#define MCF5235_WCR_WAIT (0x0008) + +/* Bit definitions and macros for MCF5235_WTM_WMR */ +#define MCF5235_WMR_WM0 (0x0001) +#define MCF5235_WMR_WM1 (0x0002) +#define MCF5235_WMR_WM2 (0x0004) +#define MCF5235_WMR_WM3 (0x0008) +#define MCF5235_WMR_WM4 (0x0010) +#define MCF5235_WMR_WM5 (0x0020) +#define MCF5235_WMR_WM6 (0x0040) +#define MCF5235_WMR_WM7 (0x0080) +#define MCF5235_WMR_WM8 (0x0100) +#define MCF5235_WMR_WM9 (0x0200) +#define MCF5235_WMR_WM10 (0x0400) +#define MCF5235_WMR_WM11 (0x0800) +#define MCF5235_WMR_WM12 (0x1000) +#define MCF5235_WMR_WM13 (0x2000) +#define MCF5235_WMR_WM14 (0x4000) +#define MCF5235_WMR_WM15 (0x8000) + +/* Bit definitions and macros for MCF5235_WTM_WCNTR */ +#define MCF5235_WCNTR_WC0 (0x0001) +#define MCF5235_WCNTR_WC1 (0x0002) +#define MCF5235_WCNTR_WC2 (0x0004) +#define MCF5235_WCNTR_WC3 (0x0008) +#define MCF5235_WCNTR_WC4 (0x0010) +#define MCF5235_WCNTR_WC5 (0x0020) +#define MCF5235_WCNTR_WC6 (0x0040) +#define MCF5235_WCNTR_WC7 (0x0080) +#define MCF5235_WCNTR_WC8 (0x0100) +#define MCF5235_WCNTR_WC9 (0x0200) +#define MCF5235_WCNTR_WC10 (0x0400) +#define MCF5235_WCNTR_WC11 (0x0800) +#define MCF5235_WCNTR_WC12 (0x1000) +#define MCF5235_WCNTR_WC13 (0x2000) +#define MCF5235_WCNTR_WC14 (0x4000) +#define MCF5235_WCNTR_WC15 (0x8000) +#define MCF5235_WSR_WS0 (0x0001) +#define MCF5235_WSR_WS1 (0x0002) +#define MCF5235_WSR_WS2 (0x0004) +#define MCF5235_WSR_WS3 (0x0008) +#define MCF5235_WSR_WS4 (0x0010) +#define MCF5235_WSR_WS5 (0x0020) +#define MCF5235_WSR_WS6 (0x0040) +#define MCF5235_WSR_WS7 (0x0080) +#define MCF5235_WSR_WS8 (0x0100) +#define MCF5235_WSR_WS9 (0x0200) +#define MCF5235_WSR_WS10 (0x0400) +#define MCF5235_WSR_WS11 (0x0800) +#define MCF5235_WSR_WS12 (0x1000) +#define MCF5235_WSR_WS13 (0x2000) +#define MCF5235_WSR_WS14 (0x4000) +#define MCF5235_WSR_WS15 (0x8000) + +/********************************************************************/ + +/********************************************************************* +* +* Universal Asynchronous Receiver Transmitter (UART) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_UART_UMR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000200))) +#define MCF5235_UART_USR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204))) +#define MCF5235_UART_UCSR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204))) +#define MCF5235_UART_UCR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000208))) +#define MCF5235_UART_URB0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C))) +#define MCF5235_UART_UTB0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C))) +#define MCF5235_UART_UIPCR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210))) +#define MCF5235_UART_UACR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210))) +#define MCF5235_UART_UISR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214))) +#define MCF5235_UART_UIMR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214))) +#define MCF5235_UART_UBG10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000218))) +#define MCF5235_UART_UBG20 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00021C))) +#define MCF5235_UART_UIP0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000234))) +#define MCF5235_UART_UOP10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000238))) +#define MCF5235_UART_UOP00 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00023C))) +#define MCF5235_UART_UMR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000240))) +#define MCF5235_UART_USR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000244))) +#define MCF5235_UART_UCSR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000244))) +#define MCF5235_UART_UCR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000248))) +#define MCF5235_UART_URB1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00024C))) +#define MCF5235_UART_UTB1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00024C))) +#define MCF5235_UART_UIPCR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000250))) +#define MCF5235_UART_UACR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000250))) +#define MCF5235_UART_UISR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000254))) +#define MCF5235_UART_UIMR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000254))) +#define MCF5235_UART_UBG11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000258))) +#define MCF5235_UART_UBG21 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00025C))) +#define MCF5235_UART_UIP1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000274))) +#define MCF5235_UART_UOP11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000278))) +#define MCF5235_UART_UOP01 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00027C))) +#define MCF5235_UART_UMR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000280))) +#define MCF5235_UART_USR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000284))) +#define MCF5235_UART_UCSR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000284))) +#define MCF5235_UART_UCR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000288))) +#define MCF5235_UART_URB2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00028C))) +#define MCF5235_UART_UTB2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00028C))) +#define MCF5235_UART_UIPCR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000290))) +#define MCF5235_UART_UACR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000290))) +#define MCF5235_UART_UISR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000294))) +#define MCF5235_UART_UIMR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000294))) +#define MCF5235_UART_UBG12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000298))) +#define MCF5235_UART_UBG22 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00029C))) +#define MCF5235_UART_UIP2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0002B4))) +#define MCF5235_UART_UOP12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0002B8))) +#define MCF5235_UART_UOP02 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0002BC))) +#define MCF5235_UART_UMR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000200+((x)*0x040)))) +#define MCF5235_UART_USR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204+((x)*0x040)))) +#define MCF5235_UART_UCSR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204+((x)*0x040)))) +#define MCF5235_UART_UCR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000208+((x)*0x040)))) +#define MCF5235_UART_URB(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C+((x)*0x040)))) +#define MCF5235_UART_UTB(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C+((x)*0x040)))) +#define MCF5235_UART_UIPCR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210+((x)*0x040)))) +#define MCF5235_UART_UACR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210+((x)*0x040)))) +#define MCF5235_UART_UISR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214+((x)*0x040)))) +#define MCF5235_UART_UIMR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214+((x)*0x040)))) +#define MCF5235_UART_UBG1(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000218+((x)*0x040)))) +#define MCF5235_UART_UBG2(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00021C+((x)*0x040)))) +#define MCF5235_UART_UIP(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000234+((x)*0x040)))) +#define MCF5235_UART_UOP1(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000238+((x)*0x040)))) +#define MCF5235_UART_UOP0(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00023C+((x)*0x040)))) + +/* Bit definitions and macros for MCF5235_UART_UMR */ +#define MCF5235_UART_UMR_BC(x) (((x)&0x03)<<0) +#define MCF5235_UART_UMR_PT (0x04) +#define MCF5235_UART_UMR_PM(x) (((x)&0x03)<<3) +#define MCF5235_UART_UMR_ERR (0x20) +#define MCF5235_UART_UMR_RXIRQ (0x40) +#define MCF5235_UART_UMR_RXRTS (0x80) +#define MCF5235_UART_UMR_SB(x) (((x)&0x0F)<<0) +#define MCF5235_UART_UMR_TXCTS (0x10) +#define MCF5235_UART_UMR_TXRTS (0x20) +#define MCF5235_UART_UMR_CM(x) (((x)&0x03)<<6) +#define MCF5235_UART_UMR_PM_MULTI_ADDR (0x1C) +#define MCF5235_UART_UMR_PM_MULTI_DATA (0x18) +#define MCF5235_UART_UMR_PM_NONE (0x10) +#define MCF5235_UART_UMR_PM_FORCE_HI (0x0C) +#define MCF5235_UART_UMR_PM_FORCE_LO (0x08) +#define MCF5235_UART_UMR_PM_ODD (0x04) +#define MCF5235_UART_UMR_PM_EVEN (0x00) +#define MCF5235_UART_UMR_BC_5 (0x00) +#define MCF5235_UART_UMR_BC_6 (0x01) +#define MCF5235_UART_UMR_BC_7 (0x02) +#define MCF5235_UART_UMR_BC_8 (0x03) +#define MCF5235_UART_UMR_CM_NORMAL (0x00) +#define MCF5235_UART_UMR_CM_ECHO (0x40) +#define MCF5235_UART_UMR_CM_LOCAL_LOOP (0x80) +#define MCF5235_UART_UMR_CM_REMOTE_LOOP (0xC0) +#define MCF5235_UART_UMR_STOP_BITS_1 (0x07) +#define MCF5235_UART_UMR_STOP_BITS_15 (0x08) +#define MCF5235_UART_UMR_STOP_BITS_2 (0x0F) +#define MCF5235_UART_USR_RXRDY (0x01) +#define MCF5235_UART_USR_FFULL (0x02) +#define MCF5235_UART_USR_TXRDY (0x04) +#define MCF5235_UART_USR_TXEMP (0x08) +#define MCF5235_UART_USR_OE (0x10) +#define MCF5235_UART_USR_PE (0x20) +#define MCF5235_UART_USR_FE (0x40) +#define MCF5235_UART_USR_RB (0x80) +#define MCF5235_UART_UCSR_TCS(x) (((x)&0x0F)<<0) +#define MCF5235_UART_UCSR_RCS(x) (((x)&0x0F)<<4) +#define MCF5235_UART_UCSR_RCS_SYS_CLK (0xD0) +#define MCF5235_UART_UCSR_RCS_CTM16 (0xE0) +#define MCF5235_UART_UCSR_RCS_CTM (0xF0) +#define MCF5235_UART_UCSR_TCS_SYS_CLK (0x0D) +#define MCF5235_UART_UCSR_TCS_CTM16 (0x0E) +#define MCF5235_UART_UCSR_TCS_CTM (0x0F) +#define MCF5235_UART_UCR_RXC(x) (((x)&0x03)<<0) +#define MCF5235_UART_UCR_TXC(x) (((x)&0x03)<<2) +#define MCF5235_UART_UCR_MISC(x) (((x)&0x07)<<4) +#define MCF5235_UART_UCR_NONE (0x00) +#define MCF5235_UART_UCR_STOP_BREAK (0x70) +#define MCF5235_UART_UCR_START_BREAK (0x60) +#define MCF5235_UART_UCR_BKCHGINT (0x50) +#define MCF5235_UART_UCR_RESET_ERROR (0x40) +#define MCF5235_UART_UCR_RESET_TX (0x30) +#define MCF5235_UART_UCR_RESET_RX (0x20) +#define MCF5235_UART_UCR_RESET_MR (0x10) +#define MCF5235_UART_UCR_TX_DISABLED (0x08) +#define MCF5235_UART_UCR_TX_ENABLED (0x04) +#define MCF5235_UART_UCR_RX_DISABLED (0x02) +#define MCF5235_UART_UCR_RX_ENABLED (0x01) +#define MCF5235_UART_UIPCR_CTS (0x01) +#define MCF5235_UART_UIPCR_COS (0x10) +#define MCF5235_UART_UACR_IEC (0x01) +#define MCF5235_UART_UISR_TXRDY (0x01) +#define MCF5235_UART_UISR_RXRDY (0x02) +#define MCF5235_UART_UISR_DB (0x04) +#define MCF5235_UART_UISR_RXFTO (0x08) +#define MCF5235_UART_UISR_TXFIFO (0x10) +#define MCF5235_UART_UISR_RXFIFO (0x20) +#define MCF5235_UART_UISR_COS (0x80) +#define MCF5235_UART_UIMR_TXRDY (0x01) +#define MCF5235_UART_UIMR_FFULL (0x02) +#define MCF5235_UART_UIMR_DB (0x04) +#define MCF5235_UART_UIMR_COS (0x80) +#define MCF5235_UART_UIP_CTS (0x01) +#define MCF5235_UART_UOP1_RTS (0x01) +#define MCF5235_UART_UOP0_RTS (0x01) + + +/********************************************************************* +* +* SDRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_SDRAMC_DCR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000040))) +#define MCF5235_SDRAMC_DACR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000048))) +#define MCF5235_SDRAMC_DMR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00004C))) +#define MCF5235_SDRAMC_DACR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000050))) +#define MCF5235_SDRAMC_DMR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000054))) + +/* Bit definitions and macros for MCF5235_SDRAMC_DCR */ +#define MCF5235_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0) +#define MCF5235_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9) +#define MCF5235_SDRAMC_DCR_IS (0x0800) +#define MCF5235_SDRAMC_DCR_COC (0x1000) +#define MCF5235_SDRAMC_DCR_NAM (0x2000) +#define MCF5235_SDRAMC_DACR0_IP (0x00000008) +#define MCF5235_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4) +#define MCF5235_SDRAMC_DACR0_MRS (0x00000040) +#define MCF5235_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8) +#define MCF5235_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12) +#define MCF5235_SDRAMC_DACR0_RE (0x00008000) +#define MCF5235_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18) +#define MCF5235_SDRAMC_DMR0_V (0x00000001) +#define MCF5235_SDRAMC_DMR0_WP (0x00000100) +#define MCF5235_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18) +#define MCF5235_SDRAMC_DACR1_IP (0x00000008) +#define MCF5235_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4) +#define MCF5235_SDRAMC_DACR1_MRS (0x00000040) +#define MCF5235_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8) +#define MCF5235_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12) +#define MCF5235_SDRAMC_DACR1_RE (0x00008000) +#define MCF5235_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18) +#define MCF5235_SDRAMC_DMR1_V (0x00000001) +#define MCF5235_SDRAMC_DMR1_WP (0x00000100) +#define MCF5235_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18) +#define MCF5235_SDRAMC_DMR_BAM_4G (0xFFFC0000) +#define MCF5235_SDRAMC_DMR_BAM_2G (0x7FFC0000) +#define MCF5235_SDRAMC_DMR_BAM_1G (0x3FFC0000) +#define MCF5235_SDRAMC_DMR_BAM_1024M (0x3FFC0000) +#define MCF5235_SDRAMC_DMR_BAM_512M (0x1FFC0000) +#define MCF5235_SDRAMC_DMR_BAM_256M (0x0FFC0000) +#define MCF5235_SDRAMC_DMR_BAM_128M (0x07FC0000) +#define MCF5235_SDRAMC_DMR_BAM_64M (0x03FC0000) +#define MCF5235_SDRAMC_DMR_BAM_32M (0x01FC0000) +#define MCF5235_SDRAMC_DMR_BAM_16M (0x00FC0000) +#define MCF5235_SDRAMC_DMR_BAM_8M (0x007C0000) +#define MCF5235_SDRAMC_DMR_BAM_4M (0x003C0000) +#define MCF5235_SDRAMC_DMR_BAM_2M (0x001C0000) +#define MCF5235_SDRAMC_DMR_BAM_1M (0x000C0000) +#define MCF5235_SDRAMC_DMR_BAM_1024K (0x000C0000) +#define MCF5235_SDRAMC_DMR_BAM_512K (0x00040000) +#define MCF5235_SDRAMC_DMR_BAM_256K (0x00000000) +#define MCF5235_SDRAMC_DMR_WP (0x00000100) +#define MCF5235_SDRAMC_DMR_CI (0x00000040) +#define MCF5235_SDRAMC_DMR_AM (0x00000020) +#define MCF5235_SDRAMC_DMR_SC (0x00000010) +#define MCF5235_SDRAMC_DMR_SD (0x00000008) +#define MCF5235_SDRAMC_DMR_UC (0x00000004) +#define MCF5235_SDRAMC_DMR_UD (0x00000002) +#define MCF5235_SDRAMC_DMR_V (0x00000001) + +/********************************************************************* +* +* DMA Timers (TIMER) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_TIMER_DTMR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000400))) +#define MCF5235_TIMER_DTXMR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000402))) +#define MCF5235_TIMER_DTER0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000403))) +#define MCF5235_TIMER_DTRR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000404))) +#define MCF5235_TIMER_DTCR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000408))) +#define MCF5235_TIMER_DTCN0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00040C))) +#define MCF5235_TIMER_DTMR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000440))) +#define MCF5235_TIMER_DTXMR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000442))) +#define MCF5235_TIMER_DTER1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000443))) +#define MCF5235_TIMER_DTRR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000444))) +#define MCF5235_TIMER_DTCR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000448))) +#define MCF5235_TIMER_DTCN1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00044C))) +#define MCF5235_TIMER_DTMR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000480))) +#define MCF5235_TIMER_DTXMR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000482))) +#define MCF5235_TIMER_DTER2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000483))) +#define MCF5235_TIMER_DTRR2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000484))) +#define MCF5235_TIMER_DTCR2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000488))) +#define MCF5235_TIMER_DTCN2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00048C))) +#define MCF5235_TIMER3_DTMR (*(vuint16*)((uintptr_t)__IPSBAR + (0x0004C0))) +#define MCF5235_TIMER_DTXMR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0004C2))) +#define MCF5235_TIMER_DTER3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0004C3))) +#define MCF5235_TIMER_DTRR3 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0004C4))) +#define MCF5235_TIMER_DTCR3 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0004C8))) +#define MCF5235_TIMER3_DTCN (*(vuint32*)((uintptr_t)__IPSBAR + (0x0004CC))) +#define MCF5235_TIMER_DTMR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x000400+((x)*0x040)))) +#define MCF5235_TIMER_DTXMR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000402+((x)*0x040)))) +#define MCF5235_TIMER_DTER(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000403+((x)*0x040)))) +#define MCF5235_TIMER_DTRR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x000404+((x)*0x040)))) +#define MCF5235_TIMER_DTCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x000408+((x)*0x040)))) +#define MCF5235_TIMER_DTCN(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x00040C+((x)*0x040)))) + +/* Bit definitions and macros for MCF5235_TIMER_DTMR */ +#define MCF5235_TIMER_DTMR_RST (0x0001) +#define MCF5235_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1) +#define MCF5235_TIMER_DTMR_FRR (0x0008) +#define MCF5235_TIMER_DTMR_ORRI (0x0010) +#define MCF5235_TIMER_DTMR_OM (0x0020) +#define MCF5235_TIMER_DTMR_CE(x) (((x)&0x0003)<<6) +#define MCF5235_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8) +#define MCF5235_TIMER_DTMR_CE_ANY (0x00C0) +#define MCF5235_TIMER_DTMR_CE_FALL (0x0080) +#define MCF5235_TIMER_DTMR_CE_RISE (0x0040) +#define MCF5235_TIMER_DTMR_CE_NONE (0x0000) +#define MCF5235_TIMER_DTMR_CLK_DTIN (0x0006) +#define MCF5235_TIMER_DTMR_CLK_DIV16 (0x0004) +#define MCF5235_TIMER_DTMR_CLK_DIV1 (0x0002) +#define MCF5235_TIMER_DTMR_CLK_STOP (0x0000) +#define MCF5235_TIMER_DTXMR_MODE16 (0x01) +#define MCF5235_TIMER_DTXMR_DMAEN (0x80) +#define MCF5235_TIMER_DTER_CAP (0x01) +#define MCF5235_TIMER_DTER_REF (0x02) + +/********************************************************************* +* +* System SRAM (SRAM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_SRAM_RAMBAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x20000000))) + +/* Bit definitions and macros for MCF5235_SRAM_RAMBAR */ +#define MCF5235_SRAM_RAMBAR_V (0x00000001) +#define MCF5235_SRAM_RAMBAR_UD (0x00000002) +#define MCF5235_SRAM_RAMBAR_UC (0x00000004) +#define MCF5235_SRAM_RAMBAR_SD (0x00000008) +#define MCF5235_SRAM_RAMBAR_SC (0x00000010) +#define MCF5235_SRAM_RAMBAR_CI (0x00000020) +#define MCF5235_SRAM_RAMBAR_WP (0x00000100) +#define MCF5235_SRAM_RAMBAR_SPV (0x00000200) +#define MCF5235_SRAM_RAMBAR_PRI2 (0x00000400) +#define MCF5235_SRAM_RAMBAR_PRI1 (0x00000800) +#define MCF5235_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_SCM_IPSBAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x000000))) +#define MCF5235_SCM_RAMBAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x000008))) +#define MCF5235_SCM_CRSR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000010))) +#define MCF5235_SCM_CWCR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000011))) +#define MCF5235_SCM_LPICR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000012))) +#define MCF5235_SCM_CWSR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000013))) +#define MCF5235_SCM_DMAREQC (*(vuint32*)((uintptr_t)__IPSBAR + (0x000014))) +#define MCF5235_SCM_MPARK (*(vuint32*)((uintptr_t)__IPSBAR + (0x00001C))) +#define MCF5235_SCM_MPR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000020))) +#define MCF5235_SCM_PACR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000024))) +#define MCF5235_SCM_PACR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000025))) +#define MCF5235_SCM_PACR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000026))) +#define MCF5235_SCM_PACR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000027))) +#define MCF5235_SCM_PACR4 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000028))) +#define MCF5235_SCM_PACR5 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002A))) +#define MCF5235_SCM_PACR6 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002B))) +#define MCF5235_SCM_PACR7 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002C))) +#define MCF5235_SCM_PACR8 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002E))) +#define MCF5235_SCM_GPACR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000030))) + +/* Bit definitions */ +#define MCF5235_SCM_IPSBAR_V (0x00000001) +#define MCF5235_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30) +#define MCF5235_SCM_RAMBAR_BDE (0x00000200) +#define MCF5235_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) +#define MCF5235_SCM_CRSR_CWDR (0x20) +#define MCF5235_SCM_CRSR_EXT (0x80) +#define MCF5235_SCM_CWCR_CWTIC (0x01) +#define MCF5235_SCM_CWCR_CWTAVAL (0x02) +#define MCF5235_SCM_CWCR_CWTA (0x04) +#define MCF5235_SCM_CWCR_CWT(x) (((x)&0x07)<<3) +#define MCF5235_SCM_CWCR_CWRI (0x40) +#define MCF5235_SCM_CWCR_CWE (0x80) +#define MCF5235_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) +#define MCF5235_SCM_LPICR_ENBSTOP (0x80) +#define MCF5235_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) +#define MCF5235_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) +#define MCF5235_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) +#define MCF5235_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) +#define MCF5235_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) +#define MCF5235_SCM_MPARK_PRKLAST (0x00001000) +#define MCF5235_SCM_MPARK_TIMEOUT (0x00002000) +#define MCF5235_SCM_MPARK_FIXED (0x00004000) +#define MCF5235_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16) +#define MCF5235_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18) +#define MCF5235_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20) +#define MCF5235_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22) +#define MCF5235_SCM_MPARK_BCR24BIT (0x01000000) +#define MCF5235_SCM_MPARK_M2_P_EN (0x02000000) +#define MCF5235_SCM_MPR_MPR(x) (((x)&0x0F)<<0) +#define MCF5235_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR0_LOCK0 (0x08) +#define MCF5235_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR0_LOCK1 (0x80) +#define MCF5235_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR1_LOCK0 (0x08) +#define MCF5235_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR1_LOCK1 (0x80) +#define MCF5235_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR2_LOCK0 (0x08) +#define MCF5235_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR2_LOCK1 (0x80) +#define MCF5235_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR3_LOCK0 (0x08) +#define MCF5235_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR3_LOCK1 (0x80) +#define MCF5235_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR4_LOCK0 (0x08) +#define MCF5235_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR4_LOCK1 (0x80) +#define MCF5235_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR5_LOCK0 (0x08) +#define MCF5235_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR5_LOCK1 (0x80) +#define MCF5235_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR6_LOCK0 (0x08) +#define MCF5235_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR6_LOCK1 (0x80) +#define MCF5235_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR7_LOCK0 (0x08) +#define MCF5235_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR7_LOCK1 (0x80) +#define MCF5235_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR8_LOCK0 (0x08) +#define MCF5235_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR8_LOCK1 (0x80) +#define MCF5235_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0) +#define MCF5235_SCM_GPACR0_LOCK (0x80) + + +/********************************************************************* +* +* FlexCAN Module (CAN) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_CAN_CANMCR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0000))) +#define MCF5235_CAN_CANCTRL0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0004))) +#define MCF5235_CAN_TIMER0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0008))) +#define MCF5235_CAN_RXGMASK0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0010))) +#define MCF5235_CAN_RX14MASK0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0014))) +#define MCF5235_CAN_RX15MASK0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0018))) +#define MCF5235_CAN_ERRCNT0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C001C))) +#define MCF5235_CAN_ERRSTAT0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0020))) +#define MCF5235_CAN_IMASK0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C002A))) +#define MCF5235_CAN_IFLAG0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C0032))) +#define MCF5235_CAN_CANMCR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0000))) +#define MCF5235_CAN_CANCTRL1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0004))) +#define MCF5235_CAN_TIMER1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0008))) +#define MCF5235_CAN_RXGMASK1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0010))) +#define MCF5235_CAN_RX14MASK1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0014))) +#define MCF5235_CAN_RX15MASK1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0018))) +#define MCF5235_CAN_ERRCNT1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F001C))) +#define MCF5235_CAN_ERRSTAT1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0020))) +#define MCF5235_CAN_IMASK1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1F002A))) +#define MCF5235_CAN_IFLAG1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1F0032))) +#define MCF5235_CAN_CANMCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0000+((x)*0x30000)))) +#define MCF5235_CAN_CANCTRL(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0004+((x)*0x30000)))) +#define MCF5235_CAN_TIMER(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0008+((x)*0x30000)))) +#define MCF5235_CAN_RXGMASK(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0010+((x)*0x30000)))) +#define MCF5235_CAN_RX14MASK(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0014+((x)*0x30000)))) +#define MCF5235_CAN_RX15MASK(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0018+((x)*0x30000)))) +#define MCF5235_CAN_ERRCNT(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C001C+((x)*0x30000)))) +#define MCF5235_CAN_ERRSTAT(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0020+((x)*0x30000)))) +#define MCF5235_CAN_IMASK(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C002A+((x)*0x30000)))) +#define MCF5235_CAN_IFLAG(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C0032+((x)*0x30000)))) + +#define MCF5235_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0080+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0082+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0084+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0088+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0089+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0090+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0092+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0094+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0098+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0099+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A0+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A4+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A9+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AA+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AB+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AC+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AD+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AE+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AF+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B0+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B4+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B9+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BA+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BB+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BC+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BD+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BE+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BF+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C0+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C4+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C9+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CA+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CB+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CC+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CD+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CE+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CF+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D0+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D4+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D9+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DA+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DB+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DC+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DD+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DE+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DF+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E0+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E4+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E9+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EA+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EB+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EC+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00ED+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EE+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EF+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F0+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F4+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F9+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FA+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FB+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FC+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FD+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FE+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FF+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0100+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0104+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0108+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0109+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0100+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0114+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0118+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0119+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0120+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0124+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0128+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0129+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0130+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0134+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0138+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0139+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0140+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0144+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0148+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0149+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0150+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0154+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0158+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0159+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0160+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0164+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0168+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0169+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0170+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0174+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0178+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0179+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0088+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C008C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0098+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C009C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AC+((x)*0x30000)))) + + +/* Bit definitions and macros for MCF5235_CAN_CANMCR */ +#define MCF5235_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) +#define MCF5235_CAN_CANMCR_SUPV (0x00800000) +#define MCF5235_CAN_CANMCR_FRZACK (0x01000000) +#define MCF5235_CAN_CANMCR_SOFTRST (0x02000000) +#define MCF5235_CAN_CANMCR_HALT (0x10000000) +#define MCF5235_CAN_CANMCR_FRZ (0x40000000) +#define MCF5235_CAN_CANMCR_MDIS (0x80000000) +#define MCF5235_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) +#define MCF5235_CAN_CANCTRL_LOM (0x00000008) +#define MCF5235_CAN_CANCTRL_LBUF (0x00000010) +#define MCF5235_CAN_CANCTRL_TSYNC (0x00000020) +#define MCF5235_CAN_CANCTRL_BOFFREC (0x00000040) +#define MCF5235_CAN_CANCTRL_SAMP (0x00000080) +#define MCF5235_CAN_CANCTRL_LPB (0x00001000) +#define MCF5235_CAN_CANCTRL_CLKSRC (0x00002000) +#define MCF5235_CAN_CANCTRL_ERRMSK (0x00004000) +#define MCF5235_CAN_CANCTRL_BOFFMSK (0x00008000) +#define MCF5235_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) +#define MCF5235_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) +#define MCF5235_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) +#define MCF5235_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) +#define MCF5235_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) +#define MCF5235_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) +#define MCF5235_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) +#define MCF5235_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) +#define MCF5235_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) +#define MCF5235_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) +#define MCF5235_CAN_ERRSTAT_WAKINT (0x00000001) +#define MCF5235_CAN_ERRSTAT_ERRINT (0x00000002) +#define MCF5235_CAN_ERRSTAT_BOFFINT (0x00000004) +#define MCF5235_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) +#define MCF5235_CAN_ERRSTAT_TXRX (0x00000040) +#define MCF5235_CAN_ERRSTAT_IDLE (0x00000080) +#define MCF5235_CAN_ERRSTAT_RXWRN (0x00000100) +#define MCF5235_CAN_ERRSTAT_TXWRN (0x00000200) +#define MCF5235_CAN_ERRSTAT_STFERR (0x00000400) +#define MCF5235_CAN_ERRSTAT_FRMERR (0x00000800) +#define MCF5235_CAN_ERRSTAT_CRCERR (0x00001000) +#define MCF5235_CAN_ERRSTAT_ACKERR (0x00002000) +#define MCF5235_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) +#define MCF5235_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) +#define MCF5235_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) +#define MCF5235_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) +#define MCF5235_CAN_IMASK_BUF0M (0x0001) +#define MCF5235_CAN_IMASK_BUF1M (0x0002) +#define MCF5235_CAN_IMASK_BUF2M (0x0004) +#define MCF5235_CAN_IMASK_BUF3M (0x0008) +#define MCF5235_CAN_IMASK_BUF4M (0x0010) +#define MCF5235_CAN_IMASK_BUF5M (0x0020) +#define MCF5235_CAN_IMASK_BUF6M (0x0040) +#define MCF5235_CAN_IMASK_BUF7M (0x0080) +#define MCF5235_CAN_IMASK_BUF8M (0x0100) +#define MCF5235_CAN_IMASK_BUF9M (0x0200) +#define MCF5235_CAN_IMASK_BUF10M (0x0400) +#define MCF5235_CAN_IMASK_BUF11M (0x0800) +#define MCF5235_CAN_IMASK_BUF12M (0x1000) +#define MCF5235_CAN_IMASK_BUF13M (0x2000) +#define MCF5235_CAN_IMASK_BUF14M (0x4000) +#define MCF5235_CAN_IMASK_BUF15M (0x8000) + +/* Bit definitions and macros for MCF5235_CAN_IFLAG */ +#define MCF5235_CAN_IFLAG_BUF0I (0x0001) +#define MCF5235_CAN_IFLAG_BUF1I (0x0002) +#define MCF5235_CAN_IFLAG_BUF2I (0x0004) +#define MCF5235_CAN_IFLAG_BUF3I (0x0008) +#define MCF5235_CAN_IFLAG_BUF4I (0x0010) +#define MCF5235_CAN_IFLAG_BUF5I (0x0020) +#define MCF5235_CAN_IFLAG_BUF6I (0x0040) +#define MCF5235_CAN_IFLAG_BUF7I (0x0080) +#define MCF5235_CAN_IFLAG_BUF8I (0x0100) +#define MCF5235_CAN_IFLAG_BUF9I (0x0200) +#define MCF5235_CAN_IFLAG_BUF10I (0x0400) +#define MCF5235_CAN_IFLAG_BUF11I (0x0800) +#define MCF5235_CAN_IFLAG_BUF12I (0x1000) +#define MCF5235_CAN_IFLAG_BUF13I (0x2000) +#define MCF5235_CAN_IFLAG_BUF14I (0x4000) +#define MCF5235_CAN_IFLAG_BUF15I (0x8000) + + +/********************************************************************* +* +* Chip Configuration Module (CCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_CCM_CCR (*(vuint16*)((uintptr_t)__IPSBAR + (0x110004))) +#define MCF5235_CCM_LPCR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x110007))) +#define MCF5235_CCM_CIR (*(vuint16*)((uintptr_t)__IPSBAR + (0x11000A))) +#define MCF5235_CCM_RCON (*(vuint16*)((uintptr_t)__IPSBAR + (0x110008))) + +/* Bit definitions and macros for MCF5235_CCM_CCR */ +#define MCF5235_CCM_CCR_BMT(x) (((x)&0x0007)<<0) +#define MCF5235_CCM_CCR_BME (0x0008) +#define MCF5235_CCM_CCR_SZEN (0x0040) +#define MCF5235_CCM_CCR_MODE(x) (((x)&0x0007)<<8) +#define MCF5235_CCM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF5235_CCM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF5235_CCM_LPCR_LPMD_STOP (0xC0) +#define MCF5235_CCM_LPCR_LPMD_WAIT (0x80) +#define MCF5235_CCM_LPCR_LPMD_DOZE (0x40) +#define MCF5235_CCM_LPCR_LPMD_RUN (0x00) +#define MCF5235_CCM_CIR_PRN(x) (((x)&0x003F)<<0) +#define MCF5235_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) +#define MCF5235_CCM_RCON_MODE (0x0001) +#define MCF5235_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) +#define MCF5235_CCM_RCON_RLOAD (0x0020) +#define MCF5235_CCM_RCON_RCSC(x) (((x)&0x0003)<<8) + +/********************************************************************* +* +* Chip Selects (CS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_CS_CSAR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000080))) +#define MCF5235_CS_CSMR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000084))) +#define MCF5235_CS_CSCR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x00008A))) +#define MCF5235_CS_CSAR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x00008C))) +#define MCF5235_CS_CSMR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000090))) +#define MCF5235_CS_CSCR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000096))) +#define MCF5235_CS_CSAR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000098))) +#define MCF5235_CS_CSMR2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00009C))) +#define MCF5235_CS_CSCR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000A2))) +#define MCF5235_CS_CSAR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000A4))) +#define MCF5235_CS_CSMR3 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000A8))) +#define MCF5235_CS_CSCR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000AE))) +#define MCF5235_CS_CSAR4 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000B0))) +#define MCF5235_CS_CSMR4 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000B4))) +#define MCF5235_CS_CSCR4 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000BA))) +#define MCF5235_CS_CSAR5 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000BC))) +#define MCF5235_CS_CSMR5 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000C0))) +#define MCF5235_CS_CSCR5 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000C6))) +#define MCF5235_CS_CSAR6 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000C8))) +#define MCF5235_CS_CSMR6 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000CC))) +#define MCF5235_CS_CSCR6 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000D2))) +#define MCF5235_CS_CSAR7 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000D4))) +#define MCF5235_CS_CSMR7 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000D8))) +#define MCF5235_CS_CSCR7 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000DE))) +#define MCF5235_CS_CSAR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x000080+((x)*0x00C)))) +#define MCF5235_CS_CSMR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x000084+((x)*0x00C)))) +#define MCF5235_CS_CSCR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x00008A+((x)*0x00C)))) + +/* Bit definitions and macros for MCF5235_CS_CSAR */ +#define MCF5235_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16)) +#define MCF5235_CS_CSMR_V (0x00000001) +#define MCF5235_CS_CSMR_UD (0x00000002) +#define MCF5235_CS_CSMR_UC (0x00000004) +#define MCF5235_CS_CSMR_SD (0x00000008) +#define MCF5235_CS_CSMR_SC (0x00000010) +#define MCF5235_CS_CSMR_CI (0x00000020) +#define MCF5235_CS_CSMR_AM (0x00000040) +#define MCF5235_CS_CSMR_WP (0x00000100) +#define MCF5235_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) +#define MCF5235_CS_CSMR_BAM_4G (0xFFFF0000) +#define MCF5235_CS_CSMR_BAM_2G (0x7FFF0000) +#define MCF5235_CS_CSMR_BAM_1G (0x3FFF0000) +#define MCF5235_CS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF5235_CS_CSMR_BAM_512M (0x1FFF0000) +#define MCF5235_CS_CSMR_BAM_256M (0x0FFF0000) +#define MCF5235_CS_CSMR_BAM_128M (0x07FF0000) +#define MCF5235_CS_CSMR_BAM_64M (0x03FF0000) +#define MCF5235_CS_CSMR_BAM_32M (0x01FF0000) +#define MCF5235_CS_CSMR_BAM_16M (0x00FF0000) +#define MCF5235_CS_CSMR_BAM_8M (0x007F0000) +#define MCF5235_CS_CSMR_BAM_4M (0x003F0000) +#define MCF5235_CS_CSMR_BAM_2M (0x001F0000) +#define MCF5235_CS_CSMR_BAM_1M (0x000F0000) +#define MCF5235_CS_CSMR_BAM_1024K (0x000F0000) +#define MCF5235_CS_CSMR_BAM_512K (0x00070000) +#define MCF5235_CS_CSMR_BAM_256K (0x00030000) +#define MCF5235_CS_CSMR_BAM_128K (0x00010000) +#define MCF5235_CS_CSMR_BAM_64K (0x00000000) +#define MCF5235_CS_CSCR_SWWS(x) (((x)&0x0007)<<0) +#define MCF5235_CS_CSCR_BSTW (0x0008) +#define MCF5235_CS_CSCR_BSTR (0x0010) +#define MCF5235_CS_CSCR_BEM (0x0020) +#define MCF5235_CS_CSCR_PS(x) (((x)&0x0003)<<6) +#define MCF5235_CS_CSCR_AA (0x0100) +#define MCF5235_CS_CSCR_IWS(x) (((x)&0x000F)<<10) +#define MCF5235_CS_CSCR_SRWS(x) (((x)&0x0003)<<14) +#define MCF5235_CS_CSCR_PS_8 (0x0040) +#define MCF5235_CS_CSCR_PS_16 (0x0080) +#define MCF5235_CS_CSCR_PS_32 (0x0000) + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_EPORT_EPPAR (*(vuint16*)((uintptr_t)__IPSBAR + (0x130000))) +#define MCF5235_EPORT_EPDDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130002))) +#define MCF5235_EPORT_EPIER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130003))) +#define MCF5235_EPORT_EPDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130004))) +#define MCF5235_EPORT_EPPDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130005))) +#define MCF5235_EPORT_EPFR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130006))) + +/* Bit definitions and macros for MCF5235_EPORT_EPPAR */ +#define MCF5235_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define MCF5235_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define MCF5235_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define MCF5235_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define MCF5235_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define MCF5235_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define MCF5235_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define MCF5235_EPORT_EPPAR_EPPAx_LEVEL (0) +#define MCF5235_EPORT_EPPAR_EPPAx_RISING (1) +#define MCF5235_EPORT_EPPAR_EPPAx_FALLING (2) +#define MCF5235_EPORT_EPPAR_EPPAx_BOTH (3) +#define MCF5235_EPORT_EPDDR_EPDD1 (0x02) +#define MCF5235_EPORT_EPDDR_EPDD2 (0x04) +#define MCF5235_EPORT_EPDDR_EPDD3 (0x08) +#define MCF5235_EPORT_EPDDR_EPDD4 (0x10) +#define MCF5235_EPORT_EPDDR_EPDD5 (0x20) +#define MCF5235_EPORT_EPDDR_EPDD6 (0x40) +#define MCF5235_EPORT_EPDDR_EPDD7 (0x80) +#define MCF5235_EPORT_EPIER_EPIE1 (0x02) +#define MCF5235_EPORT_EPIER_EPIE2 (0x04) +#define MCF5235_EPORT_EPIER_EPIE3 (0x08) +#define MCF5235_EPORT_EPIER_EPIE4 (0x10) +#define MCF5235_EPORT_EPIER_EPIE5 (0x20) +#define MCF5235_EPORT_EPIER_EPIE6 (0x40) +#define MCF5235_EPORT_EPIER_EPIE7 (0x80) +#define MCF5235_EPORT_EPDR_EPD1 (0x02) +#define MCF5235_EPORT_EPDR_EPD2 (0x04) +#define MCF5235_EPORT_EPDR_EPD3 (0x08) +#define MCF5235_EPORT_EPDR_EPD4 (0x10) +#define MCF5235_EPORT_EPDR_EPD5 (0x20) +#define MCF5235_EPORT_EPDR_EPD6 (0x40) +#define MCF5235_EPORT_EPDR_EPD7 (0x80) +#define MCF5235_EPORT_EPPDR_EPPD1 (0x02) +#define MCF5235_EPORT_EPPDR_EPPD2 (0x04) +#define MCF5235_EPORT_EPPDR_EPPD3 (0x08) +#define MCF5235_EPORT_EPPDR_EPPD4 (0x10) +#define MCF5235_EPORT_EPPDR_EPPD5 (0x20) +#define MCF5235_EPORT_EPPDR_EPPD6 (0x40) +#define MCF5235_EPORT_EPPDR_EPPD7 (0x80) +#define MCF5235_EPORT_EPFR_EPF1 (0x02) +#define MCF5235_EPORT_EPFR_EPF2 (0x04) +#define MCF5235_EPORT_EPFR_EPF3 (0x08) +#define MCF5235_EPORT_EPFR_EPF4 (0x10) +#define MCF5235_EPORT_EPFR_EPF5 (0x20) +#define MCF5235_EPORT_EPFR_EPF6 (0x40) +#define MCF5235_EPORT_EPFR_EPF7 (0x80) + + +/********************************************************************* +* +* enhanced Time Processor Unit (ETPU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_ETPU_EMCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0000))) +#define MCF5235_ETPU_ECDCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0004))) +#define MCF5235_ETPU_EMISCCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D000C))) +#define MCF5235_ETPU_ESCMODR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0010))) +#define MCF5235_ETPU_EECR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0014))) +#define MCF5235_ETPU_ETBCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0020))) +#define MCF5235_ETPU_ETB1R (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0024))) +#define MCF5235_ETPU_ETB2R (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0028))) +#define MCF5235_ETPU_EREDCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D002C))) +#define MCF5235_ETPU_ECISR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0200))) +#define MCF5235_ETPU_ECDTRSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0210))) +#define MCF5235_ETPU_ECIOSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0220))) +#define MCF5235_ETPU_ECDTROSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0230))) +#define MCF5235_ETPU_ECIER (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0240))) +#define MCF5235_ETPU_ECDTRER (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0250))) +#define MCF5235_ETPU_ECPSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0280))) +#define MCF5235_ETPU_ECSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0290))) +#define MCF5235_ETPU_EC0SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0404))) +#define MCF5235_ETPU_EC1SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0414))) +#define MCF5235_ETPU_EC2SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0424))) +#define MCF5235_ETPU_EC3SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0434))) +#define MCF5235_ETPU_EC4SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0444))) +#define MCF5235_ETPU_EC5SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0454))) +#define MCF5235_ETPU_EC6SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0464))) +#define MCF5235_ETPU_EC7SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0474))) +#define MCF5235_ETPU_EC8SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0484))) +#define MCF5235_ETPU_EC9SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0494))) +#define MCF5235_ETPU_EC10SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04A4))) +#define MCF5235_ETPU_EC11SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04B4))) +#define MCF5235_ETPU_EC12SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04C4))) +#define MCF5235_ETPU_EC13SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04D4))) +#define MCF5235_ETPU_EC14SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04E4))) +#define MCF5235_ETPU_EC15SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04F4))) +#define MCF5235_ETPU_EC16SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0504))) +#define MCF5235_ETPU_EC17SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0514))) +#define MCF5235_ETPU_EC18SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0524))) +#define MCF5235_ETPU_EC19SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0534))) +#define MCF5235_ETPU_EC20SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0544))) +#define MCF5235_ETPU_EC21SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0554))) +#define MCF5235_ETPU_EC22SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0564))) +#define MCF5235_ETPU_EC23SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0574))) +#define MCF5235_ETPU_EC24SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0584))) +#define MCF5235_ETPU_EC25SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0594))) +#define MCF5235_ETPU_EC26SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05A4))) +#define MCF5235_ETPU_EC27SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05B4))) +#define MCF5235_ETPU_EC28SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05C4))) +#define MCF5235_ETPU_EC29SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05D4))) +#define MCF5235_ETPU_EC30SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05E4))) +#define MCF5235_ETPU_EC31SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05F4))) +#define MCF5235_ETPU_ECnSCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0404+((x)*0x010)))) +#define MCF5235_ETPU_EC0CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0400))) +#define MCF5235_ETPU_EC1CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0410))) +#define MCF5235_ETPU_EC2CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0420))) +#define MCF5235_ETPU_EC3CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0430))) +#define MCF5235_ETPU_EC4CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0440))) +#define MCF5235_ETPU_EC5CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0450))) +#define MCF5235_ETPU_EC6CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0460))) +#define MCF5235_ETPU_EC7CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0470))) +#define MCF5235_ETPU_EC8CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0480))) +#define MCF5235_ETPU_EC9CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0490))) +#define MCF5235_ETPU_EC10CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04A0))) +#define MCF5235_ETPU_EC11CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04B0))) +#define MCF5235_ETPU_EC12CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04C0))) +#define MCF5235_ETPU_EC13CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04D0))) +#define MCF5235_ETPU_EC14CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04E0))) +#define MCF5235_ETPU_EC15CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04F0))) +#define MCF5235_ETPU_EC16CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0500))) +#define MCF5235_ETPU_EC17CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0510))) +#define MCF5235_ETPU_EC18CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0520))) +#define MCF5235_ETPU_EC19CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0530))) +#define MCF5235_ETPU_EC20CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0540))) +#define MCF5235_ETPU_EC21CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0550))) +#define MCF5235_ETPU_EC22CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0560))) +#define MCF5235_ETPU_EC23CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0570))) +#define MCF5235_ETPU_EC24CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0580))) +#define MCF5235_ETPU_EC25CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0590))) +#define MCF5235_ETPU_EC26CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05A0))) +#define MCF5235_ETPU_EC27CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05B0))) +#define MCF5235_ETPU_EC28CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05C0))) +#define MCF5235_ETPU_EC29CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05D0))) +#define MCF5235_ETPU_EC30CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05E0))) +#define MCF5235_ETPU_EC31CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05F0))) +#define MCF5235_ETPU_ECnCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0400+((x)*0x010)))) +#define MCF5235_ETPU_EC0HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0408))) +#define MCF5235_ETPU_EC1HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0418))) +#define MCF5235_ETPU_EC2HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0428))) +#define MCF5235_ETPU_EC3HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0438))) +#define MCF5235_ETPU_EC4HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0448))) +#define MCF5235_ETPU_EC5HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0458))) +#define MCF5235_ETPU_EC6HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0468))) +#define MCF5235_ETPU_EC7HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0478))) +#define MCF5235_ETPU_EC8HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0488))) +#define MCF5235_ETPU_EC9HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0498))) +#define MCF5235_ETPU_EC10HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04A8))) +#define MCF5235_ETPU_EC11HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04B8))) +#define MCF5235_ETPU_EC12HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04C8))) +#define MCF5235_ETPU_EC13HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04D8))) +#define MCF5235_ETPU_EC14HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04E8))) +#define MCF5235_ETPU_EC15HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04F8))) +#define MCF5235_ETPU_EC16HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0508))) +#define MCF5235_ETPU_EC17HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0518))) +#define MCF5235_ETPU_EC18HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0528))) +#define MCF5235_ETPU_EC19HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0538))) +#define MCF5235_ETPU_EC20HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0548))) +#define MCF5235_ETPU_EC21HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0558))) +#define MCF5235_ETPU_EC22HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0568))) +#define MCF5235_ETPU_EC23HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0578))) +#define MCF5235_ETPU_EC24HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0588))) +#define MCF5235_ETPU_EC25HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0598))) +#define MCF5235_ETPU_EC26HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05A8))) +#define MCF5235_ETPU_EC27HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05B8))) +#define MCF5235_ETPU_EC28HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05C8))) +#define MCF5235_ETPU_EC29HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05D8))) +#define MCF5235_ETPU_EC30HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05E8))) +#define MCF5235_ETPU_EC31HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05F8))) +#define MCF5235_ETPU_ECnHSSR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0408+((x)*0x010)))) + +/* Bit definitions and macros for MCF5235_ETPU_EMCR */ +#define MCF5235_ETPU_EMCR_GTBE (0x00000001) +#define MCF5235_ETPU_EMCR_VIS (0x00000040) +#define MCF5235_ETPU_EMCR_SCMMISEN (0x00000200) +#define MCF5235_ETPU_EMCR_SCMMISF (0x00000400) +#define MCF5235_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16) +#define MCF5235_ETPU_EMCR_ILF2 (0x01000000) +#define MCF5235_ETPU_EMCR_ILF1 (0x02000000) +#define MCF5235_ETPU_EMCR_MGE2 (0x04000000) +#define MCF5235_ETPU_EMCR_MGE1 (0x08000000) +#define MCF5235_ETPU_EMCR_GEC (0x80000000) +#define MCF5235_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0) +#define MCF5235_ETPU_ECDCR_WR (0x00000080) +#define MCF5235_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8) +#define MCF5235_ETPU_ECDCR_PWIDTH (0x00008000) +#define MCF5235_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16) +#define MCF5235_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26) +#define MCF5235_ETPU_ECDCR_STS (0x80000000) +#define MCF5235_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0) +#define MCF5235_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14) +#define MCF5235_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16) +#define MCF5235_ETPU_EECR_HLTF (0x00800000) +#define MCF5235_ETPU_EECR_STF (0x10000000) +#define MCF5235_ETPU_EECR_MDIS (0x40000000) +#define MCF5235_ETPU_EECR_FEND (0x80000000) +#define MCF5235_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0) +#define MCF5235_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14) +#define MCF5235_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16) +#define MCF5235_ETPU_ETBCR_AM (0x02000000) +#define MCF5235_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27) +#define MCF5235_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29) +#define MCF5235_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0) +#define MCF5235_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0) +#define MCF5235_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0) +#define MCF5235_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8) +#define MCF5235_ETPU_EREDCR_RSC2 (0x00004000) +#define MCF5235_ETPU_EREDCR_REN2 (0x00008000) +#define MCF5235_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16) +#define MCF5235_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24) +#define MCF5235_ETPU_EREDCR_RSC1 (0x40000000) +#define MCF5235_ETPU_EREDCR_REN1 (0x80000000) +#define MCF5235_ETPU_ECISR_CIS0 (0x00000001) +#define MCF5235_ETPU_ECISR_CIS1 (0x00000002) +#define MCF5235_ETPU_ECISR_CIS2 (0x00000004) +#define MCF5235_ETPU_ECISR_CIS3 (0x00000008) +#define MCF5235_ETPU_ECISR_CIS4 (0x00000010) +#define MCF5235_ETPU_ECISR_CIS5 (0x00000020) +#define MCF5235_ETPU_ECISR_CIS6 (0x00000040) +#define MCF5235_ETPU_ECISR_CIS7 (0x00000080) +#define MCF5235_ETPU_ECISR_CIS8 (0x00000100) +#define MCF5235_ETPU_ECISR_CIS9 (0x00000200) +#define MCF5235_ETPU_ECISR_CIS10 (0x00000400) +#define MCF5235_ETPU_ECISR_CIS11 (0x00000800) +#define MCF5235_ETPU_ECISR_CIS12 (0x00001000) +#define MCF5235_ETPU_ECISR_CIS13 (0x00002000) +#define MCF5235_ETPU_ECISR_CIS14 (0x00004000) +#define MCF5235_ETPU_ECISR_CIS15 (0x00008000) +#define MCF5235_ETPU_ECISR_CIS16 (0x00010000) +#define MCF5235_ETPU_ECISR_CIS17 (0x00020000) +#define MCF5235_ETPU_ECISR_CIS18 (0x00040000) +#define MCF5235_ETPU_ECISR_CIS19 (0x00080000) +#define MCF5235_ETPU_ECISR_CIS20 (0x00100000) +#define MCF5235_ETPU_ECISR_CIS21 (0x00200000) +#define MCF5235_ETPU_ECISR_CIS22 (0x00400000) +#define MCF5235_ETPU_ECISR_CIS23 (0x00800000) +#define MCF5235_ETPU_ECISR_CIS24 (0x01000000) +#define MCF5235_ETPU_ECISR_CIS25 (0x02000000) +#define MCF5235_ETPU_ECISR_CIS26 (0x04000000) +#define MCF5235_ETPU_ECISR_CIS27 (0x08000000) +#define MCF5235_ETPU_ECISR_CIS28 (0x10000000) +#define MCF5235_ETPU_ECISR_CIS29 (0x20000000) +#define MCF5235_ETPU_ECISR_CIS30 (0x40000000) +#define MCF5235_ETPU_ECISR_CIS31 (0x80000000) +#define MCF5235_ETPU_ECDTRSR_DTRS0 (0x00000001) +#define MCF5235_ETPU_ECDTRSR_DTRS1 (0x00000002) +#define MCF5235_ETPU_ECDTRSR_DTRS2 (0x00000004) +#define MCF5235_ETPU_ECDTRSR_DTRS3 (0x00000008) +#define MCF5235_ETPU_ECDTRSR_DTRS4 (0x00000010) +#define MCF5235_ETPU_ECDTRSR_DTRS5 (0x00000020) +#define MCF5235_ETPU_ECDTRSR_DTRS6 (0x00000040) +#define MCF5235_ETPU_ECDTRSR_DTRS7 (0x00000080) +#define MCF5235_ETPU_ECDTRSR_DTRS8 (0x00000100) +#define MCF5235_ETPU_ECDTRSR_DTRS9 (0x00000200) +#define MCF5235_ETPU_ECDTRSR_DTRS10 (0x00000400) +#define MCF5235_ETPU_ECDTRSR_DTRS11 (0x00000800) +#define MCF5235_ETPU_ECDTRSR_DTRS12 (0x00001000) +#define MCF5235_ETPU_ECDTRSR_DTRS13 (0x00002000) +#define MCF5235_ETPU_ECDTRSR_DTRS14 (0x00004000) +#define MCF5235_ETPU_ECDTRSR_DTRS15 (0x00008000) +#define MCF5235_ETPU_ECDTRSR_DTRS16 (0x00010000) +#define MCF5235_ETPU_ECDTRSR_DTRS17 (0x00020000) +#define MCF5235_ETPU_ECDTRSR_DTRS18 (0x00040000) +#define MCF5235_ETPU_ECDTRSR_DTRS19 (0x00080000) +#define MCF5235_ETPU_ECDTRSR_DTRS20 (0x00100000) +#define MCF5235_ETPU_ECDTRSR_DTRS21 (0x00200000) +#define MCF5235_ETPU_ECDTRSR_DTRS22 (0x00400000) +#define MCF5235_ETPU_ECDTRSR_DTRS23 (0x00800000) +#define MCF5235_ETPU_ECDTRSR_DTRS24 (0x01000000) +#define MCF5235_ETPU_ECDTRSR_DTRS25 (0x02000000) +#define MCF5235_ETPU_ECDTRSR_DTRS26 (0x04000000) +#define MCF5235_ETPU_ECDTRSR_DTRS27 (0x08000000) +#define MCF5235_ETPU_ECDTRSR_DTRS28 (0x10000000) +#define MCF5235_ETPU_ECDTRSR_DTRS29 (0x20000000) +#define MCF5235_ETPU_ECDTRSR_DTRS30 (0x40000000) +#define MCF5235_ETPU_ECDTRSR_DTRS31 (0x80000000) +#define MCF5235_ETPU_ECIOSR_CIOS0 (0x00000001) +#define MCF5235_ETPU_ECIOSR_CIOS1 (0x00000002) +#define MCF5235_ETPU_ECIOSR_CIOS2 (0x00000004) +#define MCF5235_ETPU_ECIOSR_CIOS3 (0x00000008) +#define MCF5235_ETPU_ECIOSR_CIOS4 (0x00000010) +#define MCF5235_ETPU_ECIOSR_CIOS5 (0x00000020) +#define MCF5235_ETPU_ECIOSR_CIOS6 (0x00000040) +#define MCF5235_ETPU_ECIOSR_CIOS7 (0x00000080) +#define MCF5235_ETPU_ECIOSR_CIOS8 (0x00000100) +#define MCF5235_ETPU_ECIOSR_CIOS9 (0x00000200) +#define MCF5235_ETPU_ECIOSR_CIOS10 (0x00000400) +#define MCF5235_ETPU_ECIOSR_CIOS11 (0x00000800) +#define MCF5235_ETPU_ECIOSR_CIOS12 (0x00001000) +#define MCF5235_ETPU_ECIOSR_CIOS13 (0x00002000) +#define MCF5235_ETPU_ECIOSR_CIOS14 (0x00004000) +#define MCF5235_ETPU_ECIOSR_CIOS15 (0x00008000) +#define MCF5235_ETPU_ECIOSR_CIOS16 (0x00010000) +#define MCF5235_ETPU_ECIOSR_CIOS17 (0x00020000) +#define MCF5235_ETPU_ECIOSR_CIOS18 (0x00040000) +#define MCF5235_ETPU_ECIOSR_CIOS19 (0x00080000) +#define MCF5235_ETPU_ECIOSR_CIOS20 (0x00100000) +#define MCF5235_ETPU_ECIOSR_CIOS21 (0x00200000) +#define MCF5235_ETPU_ECIOSR_CIOS22 (0x00400000) +#define MCF5235_ETPU_ECIOSR_CIOS23 (0x00800000) +#define MCF5235_ETPU_ECIOSR_CIOS24 (0x01000000) +#define MCF5235_ETPU_ECIOSR_CIOS25 (0x02000000) +#define MCF5235_ETPU_ECIOSR_CIOS26 (0x04000000) +#define MCF5235_ETPU_ECIOSR_CIOS27 (0x08000000) +#define MCF5235_ETPU_ECIOSR_CIOS28 (0x10000000) +#define MCF5235_ETPU_ECIOSR_CIOS29 (0x20000000) +#define MCF5235_ETPU_ECIOSR_CIOS30 (0x40000000) +#define MCF5235_ETPU_ECIOSR_CIOS31 (0x80000000) +#define MCF5235_ETPU_ECDTROSR_DTROS0 (0x00000001) +#define MCF5235_ETPU_ECDTROSR_DTROS1 (0x00000002) +#define MCF5235_ETPU_ECDTROSR_DTROS2 (0x00000004) +#define MCF5235_ETPU_ECDTROSR_DTROS3 (0x00000008) +#define MCF5235_ETPU_ECDTROSR_DTROS4 (0x00000010) +#define MCF5235_ETPU_ECDTROSR_DTROS5 (0x00000020) +#define MCF5235_ETPU_ECDTROSR_DTROS6 (0x00000040) +#define MCF5235_ETPU_ECDTROSR_DTROS7 (0x00000080) +#define MCF5235_ETPU_ECDTROSR_DTROS8 (0x00000100) +#define MCF5235_ETPU_ECDTROSR_DTROS9 (0x00000200) +#define MCF5235_ETPU_ECDTROSR_DTROS10 (0x00000400) +#define MCF5235_ETPU_ECDTROSR_DTROS11 (0x00000800) +#define MCF5235_ETPU_ECDTROSR_DTROS12 (0x00001000) +#define MCF5235_ETPU_ECDTROSR_DTROS13 (0x00002000) +#define MCF5235_ETPU_ECDTROSR_DTROS14 (0x00004000) +#define MCF5235_ETPU_ECDTROSR_DTROS15 (0x00008000) +#define MCF5235_ETPU_ECDTROSR_DTROS16 (0x00010000) +#define MCF5235_ETPU_ECDTROSR_DTROS17 (0x00020000) +#define MCF5235_ETPU_ECDTROSR_DTROS18 (0x00040000) +#define MCF5235_ETPU_ECDTROSR_DTROS19 (0x00080000) +#define MCF5235_ETPU_ECDTROSR_DTROS20 (0x00100000) +#define MCF5235_ETPU_ECDTROSR_DTROS21 (0x00200000) +#define MCF5235_ETPU_ECDTROSR_DTROS22 (0x00400000) +#define MCF5235_ETPU_ECDTROSR_DTROS23 (0x00800000) +#define MCF5235_ETPU_ECDTROSR_DTROS24 (0x01000000) +#define MCF5235_ETPU_ECDTROSR_DTROS25 (0x02000000) +#define MCF5235_ETPU_ECDTROSR_DTROS26 (0x04000000) +#define MCF5235_ETPU_ECDTROSR_DTROS27 (0x08000000) +#define MCF5235_ETPU_ECDTROSR_DTROS28 (0x10000000) +#define MCF5235_ETPU_ECDTROSR_DTROS29 (0x20000000) +#define MCF5235_ETPU_ECDTROSR_DTROS30 (0x40000000) +#define MCF5235_ETPU_ECDTROSR_DTROS31 (0x80000000) +#define MCF5235_ETPU_ECIER_CIE0 (0x00000001) +#define MCF5235_ETPU_ECIER_CIE1 (0x00000002) +#define MCF5235_ETPU_ECIER_CIE2 (0x00000004) +#define MCF5235_ETPU_ECIER_CIE3 (0x00000008) +#define MCF5235_ETPU_ECIER_CIE4 (0x00000010) +#define MCF5235_ETPU_ECIER_CIE5 (0x00000020) +#define MCF5235_ETPU_ECIER_CIE6 (0x00000040) +#define MCF5235_ETPU_ECIER_CIE7 (0x00000080) +#define MCF5235_ETPU_ECIER_CIE8 (0x00000100) +#define MCF5235_ETPU_ECIER_CIE9 (0x00000200) +#define MCF5235_ETPU_ECIER_CIE10 (0x00000400) +#define MCF5235_ETPU_ECIER_CIE11 (0x00000800) +#define MCF5235_ETPU_ECIER_CIE12 (0x00001000) +#define MCF5235_ETPU_ECIER_CIE13 (0x00002000) +#define MCF5235_ETPU_ECIER_CIE14 (0x00004000) +#define MCF5235_ETPU_ECIER_CIE15 (0x00008000) +#define MCF5235_ETPU_ECIER_CIE16 (0x00010000) +#define MCF5235_ETPU_ECIER_CIE17 (0x00020000) +#define MCF5235_ETPU_ECIER_CIE18 (0x00040000) +#define MCF5235_ETPU_ECIER_CIE19 (0x00080000) +#define MCF5235_ETPU_ECIER_CIE20 (0x00100000) +#define MCF5235_ETPU_ECIER_CIE21 (0x00200000) +#define MCF5235_ETPU_ECIER_CIE22 (0x00400000) +#define MCF5235_ETPU_ECIER_CIE23 (0x00800000) +#define MCF5235_ETPU_ECIER_CIE24 (0x01000000) +#define MCF5235_ETPU_ECIER_CIE25 (0x02000000) +#define MCF5235_ETPU_ECIER_CIE26 (0x04000000) +#define MCF5235_ETPU_ECIER_CIE27 (0x08000000) +#define MCF5235_ETPU_ECIER_CIE28 (0x10000000) +#define MCF5235_ETPU_ECIER_CIE29 (0x20000000) +#define MCF5235_ETPU_ECIER_CIE30 (0x40000000) +#define MCF5235_ETPU_ECIER_CIE31 (0x80000000) +#define MCF5235_ETPU_ECDTRER_DTRE0 (0x00000001) +#define MCF5235_ETPU_ECDTRER_DTRE1 (0x00000002) +#define MCF5235_ETPU_ECDTRER_DTRE2 (0x00000004) +#define MCF5235_ETPU_ECDTRER_DTRE3 (0x00000008) +#define MCF5235_ETPU_ECDTRER_DTRE4 (0x00000010) +#define MCF5235_ETPU_ECDTRER_DTRE5 (0x00000020) +#define MCF5235_ETPU_ECDTRER_DTRE6 (0x00000040) +#define MCF5235_ETPU_ECDTRER_DTRE7 (0x00000080) +#define MCF5235_ETPU_ECDTRER_DTRE8 (0x00000100) +#define MCF5235_ETPU_ECDTRER_DTRE9 (0x00000200) +#define MCF5235_ETPU_ECDTRER_DTRE10 (0x00000400) +#define MCF5235_ETPU_ECDTRER_DTRE11 (0x00000800) +#define MCF5235_ETPU_ECDTRER_DTRE12 (0x00001000) +#define MCF5235_ETPU_ECDTRER_DTRE13 (0x00002000) +#define MCF5235_ETPU_ECDTRER_DTRE14 (0x00004000) +#define MCF5235_ETPU_ECDTRER_DTRE15 (0x00008000) +#define MCF5235_ETPU_ECDTRER_DTRE16 (0x00010000) +#define MCF5235_ETPU_ECDTRER_DTRE17 (0x00020000) +#define MCF5235_ETPU_ECDTRER_DTRE18 (0x00040000) +#define MCF5235_ETPU_ECDTRER_DTRE19 (0x00080000) +#define MCF5235_ETPU_ECDTRER_DTRE20 (0x00100000) +#define MCF5235_ETPU_ECDTRER_DTRE21 (0x00200000) +#define MCF5235_ETPU_ECDTRER_DTRE22 (0x00400000) +#define MCF5235_ETPU_ECDTRER_DTRE23 (0x00800000) +#define MCF5235_ETPU_ECDTRER_DTRE24 (0x01000000) +#define MCF5235_ETPU_ECDTRER_DTRE25 (0x02000000) +#define MCF5235_ETPU_ECDTRER_DTRE26 (0x04000000) +#define MCF5235_ETPU_ECDTRER_DTRE27 (0x08000000) +#define MCF5235_ETPU_ECDTRER_DTRE28 (0x10000000) +#define MCF5235_ETPU_ECDTRER_DTRE29 (0x20000000) +#define MCF5235_ETPU_ECDTRER_DTRE30 (0x40000000) +#define MCF5235_ETPU_ECDTRER_DTRE31 (0x80000000) +#define MCF5235_ETPU_ECPSSR_SR0 (0x00000001) +#define MCF5235_ETPU_ECPSSR_SR1 (0x00000002) +#define MCF5235_ETPU_ECPSSR_SR2 (0x00000004) +#define MCF5235_ETPU_ECPSSR_SR3 (0x00000008) +#define MCF5235_ETPU_ECPSSR_SR4 (0x00000010) +#define MCF5235_ETPU_ECPSSR_SR5 (0x00000020) +#define MCF5235_ETPU_ECPSSR_SR6 (0x00000040) +#define MCF5235_ETPU_ECPSSR_SR7 (0x00000080) +#define MCF5235_ETPU_ECPSSR_SR8 (0x00000100) +#define MCF5235_ETPU_ECPSSR_SR9 (0x00000200) +#define MCF5235_ETPU_ECPSSR_SR10 (0x00000400) +#define MCF5235_ETPU_ECPSSR_SR11 (0x00000800) +#define MCF5235_ETPU_ECPSSR_SR12 (0x00001000) +#define MCF5235_ETPU_ECPSSR_SR13 (0x00002000) +#define MCF5235_ETPU_ECPSSR_SR14 (0x00004000) +#define MCF5235_ETPU_ECPSSR_SR15 (0x00008000) +#define MCF5235_ETPU_ECPSSR_SR16 (0x00010000) +#define MCF5235_ETPU_ECPSSR_SR17 (0x00020000) +#define MCF5235_ETPU_ECPSSR_SR18 (0x00040000) +#define MCF5235_ETPU_ECPSSR_SR19 (0x00080000) +#define MCF5235_ETPU_ECPSSR_SR20 (0x00100000) +#define MCF5235_ETPU_ECPSSR_SR21 (0x00200000) +#define MCF5235_ETPU_ECPSSR_SR22 (0x00400000) +#define MCF5235_ETPU_ECPSSR_SR23 (0x00800000) +#define MCF5235_ETPU_ECPSSR_SR24 (0x01000000) +#define MCF5235_ETPU_ECPSSR_SR25 (0x02000000) +#define MCF5235_ETPU_ECPSSR_SR26 (0x04000000) +#define MCF5235_ETPU_ECPSSR_SR27 (0x08000000) +#define MCF5235_ETPU_ECPSSR_SR28 (0x10000000) +#define MCF5235_ETPU_ECPSSR_SR29 (0x20000000) +#define MCF5235_ETPU_ECPSSR_SR30 (0x40000000) +#define MCF5235_ETPU_ECPSSR_SR31 (0x80000000) +#define MCF5235_ETPU_ECSSR_SS0 (0x00000001) +#define MCF5235_ETPU_ECSSR_SS1 (0x00000002) +#define MCF5235_ETPU_ECSSR_SS2 (0x00000004) +#define MCF5235_ETPU_ECSSR_SS3 (0x00000008) +#define MCF5235_ETPU_ECSSR_SS4 (0x00000010) +#define MCF5235_ETPU_ECSSR_SS5 (0x00000020) +#define MCF5235_ETPU_ECSSR_SS6 (0x00000040) +#define MCF5235_ETPU_ECSSR_SS7 (0x00000080) +#define MCF5235_ETPU_ECSSR_SS8 (0x00000100) +#define MCF5235_ETPU_ECSSR_SS9 (0x00000200) +#define MCF5235_ETPU_ECSSR_SS10 (0x00000400) +#define MCF5235_ETPU_ECSSR_SS11 (0x00000800) +#define MCF5235_ETPU_ECSSR_SS12 (0x00001000) +#define MCF5235_ETPU_ECSSR_SS13 (0x00002000) +#define MCF5235_ETPU_ECSSR_SS14 (0x00004000) +#define MCF5235_ETPU_ECSSR_SS15 (0x00008000) +#define MCF5235_ETPU_ECSSR_SS16 (0x00010000) +#define MCF5235_ETPU_ECSSR_SS17 (0x00020000) +#define MCF5235_ETPU_ECSSR_SS18 (0x00040000) +#define MCF5235_ETPU_ECSSR_SS19 (0x00080000) +#define MCF5235_ETPU_ECSSR_SS20 (0x00100000) +#define MCF5235_ETPU_ECSSR_SS21 (0x00200000) +#define MCF5235_ETPU_ECSSR_SS22 (0x00400000) +#define MCF5235_ETPU_ECSSR_SS23 (0x00800000) +#define MCF5235_ETPU_ECSSR_SS24 (0x01000000) +#define MCF5235_ETPU_ECSSR_SS25 (0x02000000) +#define MCF5235_ETPU_ECSSR_SS26 (0x04000000) +#define MCF5235_ETPU_ECSSR_SS27 (0x08000000) +#define MCF5235_ETPU_ECSSR_SS28 (0x10000000) +#define MCF5235_ETPU_ECSSR_SS29 (0x20000000) +#define MCF5235_ETPU_ECSSR_SS30 (0x40000000) +#define MCF5235_ETPU_ECSSR_SS31 (0x80000000) +#define MCF5235_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0) +#define MCF5235_ETPU_ECnSCR_OBE (0x00002000) +#define MCF5235_ETPU_ECnSCR_OPS (0x00004000) +#define MCF5235_ETPU_ECnSCR_IPS (0x00008000) +#define MCF5235_ETPU_ECnSCR_DTROS (0x00400000) +#define MCF5235_ETPU_ECnSCR_DTRS (0x00800000) +#define MCF5235_ETPU_ECnSCR_CIOS (0x40000000) +#define MCF5235_ETPU_ECnSCR_CIS (0x80000000) +#define MCF5235_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0) +#define MCF5235_ETPU_ECnCR_OPOL (0x00004000) +#define MCF5235_ETPU_ECnCR_ODIS (0x00008000) +#define MCF5235_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16) +#define MCF5235_ETPU_ECnCR_ETCS (0x01000000) +#define MCF5235_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28) +#define MCF5235_ETPU_ECnCR_DTRE (0x40000000) +#define MCF5235_ETPU_ECnCR_CIE (0x80000000) +#define MCF5235_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0) + + +/********************************************************************* +* +* Fast Ethernet Controller (FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_FEC_EIR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001004))) +#define MCF5235_FEC_EIMR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001008))) +#define MCF5235_FEC_RDAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001010))) +#define MCF5235_FEC_TDAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001014))) +#define MCF5235_FEC_ECR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001024))) +#define MCF5235_FEC_MMFR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001040))) +#define MCF5235_FEC_MSCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001044))) +#define MCF5235_FEC_MIBC (*(vuint32*)((uintptr_t)__IPSBAR + (0x001064))) +#define MCF5235_FEC_RCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001084))) +#define MCF5235_FEC_TCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010C4))) +#define MCF5235_FEC_PALR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010E4))) +#define MCF5235_FEC_PAUR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010E8))) +#define MCF5235_FEC_OPD (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010EC))) +#define MCF5235_FEC_IAUR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001118))) +#define MCF5235_FEC_IALR (*(vuint32*)((uintptr_t)__IPSBAR + (0x00111C))) +#define MCF5235_FEC_GAUR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001120))) +#define MCF5235_FEC_GALR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001124))) +#define MCF5235_FEC_TFWR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001144))) +#define MCF5235_FEC_FRBR (*(vuint32*)((uintptr_t)__IPSBAR + (0x00114C))) +#define MCF5235_FEC_FRSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001150))) +#define MCF5235_FEC_ERDSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001180))) +#define MCF5235_FEC_ETDSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001184))) +#define MCF5235_FEC_EMRBR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001188))) +#define MCF5235_FEC_RMON_T_DROP (*(vuint32*)((uintptr_t)__IPSBAR + (0x001200))) +#define MCF5235_FEC_RMON_T_PACKETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x001204))) +#define MCF5235_FEC_RMON_T_BC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x001208))) +#define MCF5235_FEC_RMON_T_MC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x00120C))) +#define MCF5235_FEC_RMON_T_CRC_ALIGN (*(vuint32*)((uintptr_t)__IPSBAR + (0x001210))) +#define MCF5235_FEC_RMON_T_UNDERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001214))) +#define MCF5235_FEC_RMON_T_OVERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001218))) +#define MCF5235_FEC_RMON_T_FRAG (*(vuint32*)((uintptr_t)__IPSBAR + (0x00121C))) +#define MCF5235_FEC_RMON_T_JAB (*(vuint32*)((uintptr_t)__IPSBAR + (0x001220))) +#define MCF5235_FEC_RMON_T_COL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001224))) +#define MCF5235_FEC_RMON_T_P64 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001228))) +#define MCF5235_FEC_RMON_T_P65TO127 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00122C))) +#define MCF5235_FEC_RMON_T_P128TO255 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001230))) +#define MCF5235_FEC_RMON_T_P256TO511 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001234))) +#define MCF5235_FEC_RMON_T_P512TO1023 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001238))) +#define MCF5235_FEC_RMON_T_P1024TO2047 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00123C))) +#define MCF5235_FEC_RMON_T_P_GTE2048 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001240))) +#define MCF5235_FEC_RMON_T_OCTETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x001244))) +#define MCF5235_FEC_IEEE_T_DROP (*(vuint32*)((uintptr_t)__IPSBAR + (0x001248))) +#define MCF5235_FEC_IEEE_T_FRAME_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x00124C))) +#define MCF5235_FEC_IEEE_T_1COL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001250))) +#define MCF5235_FEC_IEEE_T_MCOL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001254))) +#define MCF5235_FEC_IEEE_T_DEF (*(vuint32*)((uintptr_t)__IPSBAR + (0x001258))) +#define MCF5235_FEC_IEEE_T_LCOL (*(vuint32*)((uintptr_t)__IPSBAR + (0x00125C))) +#define MCF5235_FEC_IEEE_T_EXCOL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001260))) +#define MCF5235_FEC_IEEE_T_MACERR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001264))) +#define MCF5235_FEC_IEEE_T_CSERR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001268))) +#define MCF5235_FEC_IEEE_T_SQE (*(vuint32*)((uintptr_t)__IPSBAR + (0x00126C))) +#define MCF5235_FEC_IEEE_T_FDXFC (*(vuint32*)((uintptr_t)__IPSBAR + (0x001270))) +#define MCF5235_FEC_IEEE_T_OCTETS_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x001274))) +#define MCF5235_FEC_RMON_R_PACKETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x001284))) +#define MCF5235_FEC_RMON_R_BC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x001288))) +#define MCF5235_FEC_RMON_R_MC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x00128C))) +#define MCF5235_FEC_RMON_R_CRC_ALIGN (*(vuint32*)((uintptr_t)__IPSBAR + (0x001290))) +#define MCF5235_FEC_RMON_R_UNDERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001294))) +#define MCF5235_FEC_RMON_R_OVERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001298))) +#define MCF5235_FEC_RMON_R_FRAG (*(vuint32*)((uintptr_t)__IPSBAR + (0x00129C))) +#define MCF5235_FEC_RMON_R_JAB (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012A0))) +#define MCF5235_FEC_RMON_R_RESVD_0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012A4))) +#define MCF5235_FEC_RMON_R_P64 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012A8))) +#define MCF5235_FEC_RMON_R_P65T0127 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012AC))) +#define MCF5235_FEC_RMON_R_P128TO255 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012B0))) +#define MCF5235_FEC_RMON_R_P256TO511 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012B4))) +#define MCF5235_FEC_RMON_R_P512TO1023 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012B8))) +#define MCF5235_FEC_RMON_R_GTE2048 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012C0))) +#define MCF5235_FEC_RMON_R_P1024TO2047 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012BC))) +#define MCF5235_FEC_RMON_R_OCTETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012C4))) +#define MCF5235_FEC_IEEE_R_DROP (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012C8))) +#define MCF5235_FEC_IEEE_R_FRAME_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012CC))) +#define MCF5235_FEC_IEEE_R_CRC (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012D0))) +#define MCF5235_FEC_IEEE_R_ALIGN (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012D4))) +#define MCF5235_FEC_IEEE_R_MACERR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012D8))) +#define MCF5235_FEC_IEEE_R_FDXFC (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012DC))) +#define MCF5235_FEC_IEEE_R_OCTETS_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012E0))) + +/* Bit definitions and macros for MCF5235_FEC_EIR */ +#define MCF5235_FEC_EIR_UN (0x00080000) +#define MCF5235_FEC_EIR_RL (0x00100000) +#define MCF5235_FEC_EIR_LC (0x00200000) +#define MCF5235_FEC_EIR_EBERR (0x00400000) +#define MCF5235_FEC_EIR_MII (0x00800000) +#define MCF5235_FEC_EIR_RXB (0x01000000) +#define MCF5235_FEC_EIR_RXF (0x02000000) +#define MCF5235_FEC_EIR_TXB (0x04000000) +#define MCF5235_FEC_EIR_TXF (0x08000000) +#define MCF5235_FEC_EIR_GRA (0x10000000) +#define MCF5235_FEC_EIR_BABT (0x20000000) +#define MCF5235_FEC_EIR_BABR (0x40000000) +#define MCF5235_FEC_EIR_HBERR (0x80000000) +#define MCF5235_FEC_EIMR_UN (0x00080000) +#define MCF5235_FEC_EIMR_RL (0x00100000) +#define MCF5235_FEC_EIMR_LC (0x00200000) +#define MCF5235_FEC_EIMR_EBERR (0x00400000) +#define MCF5235_FEC_EIMR_MII (0x00800000) +#define MCF5235_FEC_EIMR_RXB (0x01000000) +#define MCF5235_FEC_EIMR_RXF (0x02000000) +#define MCF5235_FEC_EIMR_TXB (0x04000000) +#define MCF5235_FEC_EIMR_TXF (0x08000000) +#define MCF5235_FEC_EIMR_GRA (0x10000000) +#define MCF5235_FEC_EIMR_BABT (0x20000000) +#define MCF5235_FEC_EIMR_BABR (0x40000000) +#define MCF5235_FEC_EIMR_HBERR (0x80000000) +#define MCF5235_FEC_RDAR_R_DES_ACTIVE (0x01000000) +#define MCF5235_FEC_TDAR_X_DES_ACTIVE (0x01000000) +#define MCF5235_FEC_ECR_RESET (0x00000001) +#define MCF5235_FEC_ECR_ETHER_EN (0x00000002) +#define MCF5235_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) +#define MCF5235_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) +#define MCF5235_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) +#define MCF5235_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) +#define MCF5235_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) +#define MCF5235_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) +#define MCF5235_FEC_MMFR_ST_01 (0x40000000) +#define MCF5235_FEC_MMFR_OP_READ (0x20000000) +#define MCF5235_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF5235_FEC_MMFR_TA_10 (0x00020000) +#define MCF5235_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) +#define MCF5235_FEC_MSCR_DIS_PREAMBLE (0x00000080) +#define MCF5235_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF5235_FEC_MIBC_MIB_DISABLE (0x80000000) +#define MCF5235_FEC_RCR_LOOP (0x00000001) +#define MCF5235_FEC_RCR_DRT (0x00000002) +#define MCF5235_FEC_RCR_MII_MODE (0x00000004) +#define MCF5235_FEC_RCR_PROM (0x00000008) +#define MCF5235_FEC_RCR_BC_REJ (0x00000010) +#define MCF5235_FEC_RCR_FCE (0x00000020) +#define MCF5235_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) +#define MCF5235_FEC_TCR_GTS (0x00000001) +#define MCF5235_FEC_TCR_HBC (0x00000002) +#define MCF5235_FEC_TCR_FDEN (0x00000004) +#define MCF5235_FEC_TCR_TFC_PAUSE (0x00000008) +#define MCF5235_FEC_TCR_RFC_PAUSE (0x00000010) +#define MCF5235_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) +#define MCF5235_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) +#define MCF5235_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) +#define MCF5235_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) +#define MCF5235_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) +#define MCF5235_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) +#define MCF5235_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) +#define MCF5235_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) +#define MCF5235_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) +#define MCF5235_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) +#define MCF5235_FEC_TxBD_R 0x8000 +#define MCF5235_FEC_TxBD_BUSY 0x4000 +#define MCF5235_FEC_TxBD_TO1 0x4000 +#define MCF5235_FEC_TxBD_W 0x2000 +#define MCF5235_FEC_TxBD_TO2 0x1000 +#define MCF5235_FEC_TxBD_FIRST 0x1000 +#define MCF5235_FEC_TxBD_L 0x0800 +#define MCF5235_FEC_TxBD_TC 0x0400 +#define MCF5235_FEC_TxBD_DEF 0x0200 +#define MCF5235_FEC_TxBD_HB 0x0100 +#define MCF5235_FEC_TxBD_LC 0x0080 +#define MCF5235_FEC_TxBD_RL 0x0040 +#define MCF5235_FEC_TxBD_UN 0x0002 +#define MCF5235_FEC_TxBD_CSL 0x0001 +#define MCF5235_FEC_RxBD_E 0x8000 +#define MCF5235_FEC_RxBD_INUSE 0x4000 +#define MCF5235_FEC_RxBD_R01 0x4000 +#define MCF5235_FEC_RxBD_W 0x2000 +#define MCF5235_FEC_RxBD_R02 0x1000 +#define MCF5235_FEC_RxBD_L 0x0800 +#define MCF5235_FEC_RxBD_M 0x0100 +#define MCF5235_FEC_RxBD_BC 0x0080 +#define MCF5235_FEC_RxBD_MC 0x0040 +#define MCF5235_FEC_RxBD_LG 0x0020 +#define MCF5235_FEC_RxBD_NO 0x0010 +#define MCF5235_FEC_RxBD_CR 0x0004 +#define MCF5235_FEC_RxBD_OV 0x0002 +#define MCF5235_FEC_RxBD_TR 0x0001 + +/************************************************************ +* +* Clock +*************************************************************/ +/* Register read/write macros */ +#define MCF5235_FMPLL_SYNCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x120000))) +#define MCF5235_FMPLL_SYNSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x120004))) + +/* Bit definitions and macros for MCF5235_FMPLL_SYNCR */ +#define MCF5235_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0) +#define MCF5235_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10) +#define MCF5235_FMPLL_SYNCR_RATE (0x00001000) +#define MCF5235_FMPLL_SYNCR_LOCIRQ (0x00002000) +#define MCF5235_FMPLL_SYNCR_LOLIRQ (0x00004000) +#define MCF5235_FMPLL_SYNCR_DISCLK (0x00008000) +#define MCF5235_FMPLL_SYNCR_LOCRE (0x00010000) +#define MCF5235_FMPLL_SYNCR_LOLRE (0x00020000) +#define MCF5235_FMPLL_SYNCR_LOCEN (0x00040000) +#define MCF5235_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19) +#define MCF5235_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24) +#define MCF5235_FMPLL_SYNSR_CALPASS (0x00000001) +#define MCF5235_FMPLL_SYNSR_CALDONE (0x00000002) +#define MCF5235_FMPLL_SYNSR_LOCF (0x00000004) +#define MCF5235_FMPLL_SYNSR_LOCK (0x00000008) +#define MCF5235_FMPLL_SYNSR_LOCKS (0x00000010) +#define MCF5235_FMPLL_SYNSR_PLLREF (0x00000020) +#define MCF5235_FMPLL_SYNSR_PLLSEL (0x00000040) +#define MCF5235_FMPLL_SYNSR_MODE (0x00000080) +#define MCF5235_FMPLL_SYNSR_LOC (0x00000100) +#define MCF5235_FMPLL_SYNSR_LOLF (0x00000200) + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_GPIO_PODR_ADDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100000))) +#define MCF5235_GPIO_PODR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100001))) +#define MCF5235_GPIO_PODR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100002))) +#define MCF5235_GPIO_PODR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100003))) +#define MCF5235_GPIO_PODR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100004))) +#define MCF5235_GPIO_PODR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100005))) +#define MCF5235_GPIO_PODR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100006))) +#define MCF5235_GPIO_PODR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100007))) +#define MCF5235_GPIO_PODR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100008))) +#define MCF5235_GPIO_PODR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100009))) +#define MCF5235_GPIO_PODR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10000A))) +#define MCF5235_GPIO_PODR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10000B))) +#define MCF5235_GPIO_PODR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10000C))) +#define MCF5235_GPIO_PDDR_APDDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100010))) +#define MCF5235_GPIO_PDDR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100011))) +#define MCF5235_GPIO_PDDR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100012))) +#define MCF5235_GPIO_PDDR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100013))) +#define MCF5235_GPIO_PDDR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100014))) +#define MCF5235_GPIO_PDDR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100015))) +#define MCF5235_GPIO_PDDR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100016))) +#define MCF5235_GPIO_PDDR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100017))) +#define MCF5235_GPIO_PDDR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100018))) +#define MCF5235_GPIO_PDDR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100019))) +#define MCF5235_GPIO_PDDR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10001A))) +#define MCF5235_GPIO_PDDR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10001B))) +#define MCF5235_GPIO_PDDR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10001C))) +#define MCF5235_GPIO_PPDSDR_ADDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100020))) +#define MCF5235_GPIO_PPDSDR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100021))) +#define MCF5235_GPIO_PPDSDR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100022))) +#define MCF5235_GPIO_PPDSDR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100023))) +#define MCF5235_GPIO_PPDSDR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100024))) +#define MCF5235_GPIO_PPDSDR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100027))) +#define MCF5235_GPIO_PPDSDR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100025))) +#define MCF5235_GPIO_PPDSDR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100026))) +#define MCF5235_GPIO_PPDSDR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100028))) +#define MCF5235_GPIO_PPDSDR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100029))) +#define MCF5235_GPIO_PPDSDR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10002A))) +#define MCF5235_GPIO_PPDSDR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10002B))) +#define MCF5235_GPIO_PPDSDR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10002C))) +#define MCF5235_GPIO_PCLRR_ADDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100030))) +#define MCF5235_GPIO_PCLRR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100031))) +#define MCF5235_GPIO_PCLRR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100032))) +#define MCF5235_GPIO_PCLRR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100033))) +#define MCF5235_GPIO_PCLRR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100034))) +#define MCF5235_GPIO_PCLRR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100035))) +#define MCF5235_GPIO_PCLRR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100036))) +#define MCF5235_GPIO_PCLRR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100037))) +#define MCF5235_GPIO_PCLRR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100038))) +#define MCF5235_GPIO_PCLRR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100039))) +#define MCF5235_GPIO_PCLRR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10003A))) +#define MCF5235_GPIO_PCLRR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10003B))) +#define MCF5235_GPIO_PCLRR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10003C))) +#define MCF5235_GPIO_PAR_AD (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100040))) +#define MCF5235_GPIO_PAR_BUSCTL (*(vuint16*)((uintptr_t)__IPSBAR + (0x100042))) +#define MCF5235_GPIO_PAR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100044))) +#define MCF5235_GPIO_PAR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100045))) +#define MCF5235_GPIO_PAR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100046))) +#define MCF5235_GPIO_PAR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100047))) +#define MCF5235_GPIO_UART (*(vuint16*)((uintptr_t)__IPSBAR + (0x100048))) +#define MCF5235_GPIO_PAR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10004A))) +#define MCF5235_GPIO_PAR_TIMER (*(vuint16*)((uintptr_t)__IPSBAR + (0x10004C))) +#define MCF5235_GPIO_PAR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10004E))) +#define MCF5235_GPIO_DSCR_EIM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100050))) +#define MCF5235_GPIO_DSCR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100051))) +#define MCF5235_GPIO_DSCR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100052))) +#define MCF5235_GPIO_DSCR_UART (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100053))) +#define MCF5235_GPIO_DSCR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100054))) +#define MCF5235_GPIO_DSCR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100055))) + +/* Bit definitions and macros for MCF5235_GPIO_PODR_ADDR */ +#define MCF5235_GPIO_PODR_ADDR_PODR_ADDR5 (0x20) +#define MCF5235_GPIO_PODR_ADDR_PODR_ADDR6 (0x40) +#define MCF5235_GPIO_PODR_ADDR_PODR_ADDR7 (0x80) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH0 (0x01) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH1 (0x02) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH2 (0x04) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH3 (0x08) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH4 (0x10) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH5 (0x20) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH6 (0x40) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH7 (0x80) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL0 (0x01) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL1 (0x02) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL2 (0x04) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL3 (0x08) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL4 (0x10) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL5 (0x20) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL6 (0x40) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL7 (0x80) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL4 (0x10) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL5 (0x20) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL6 (0x40) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL7 (0x80) +#define MCF5235_GPIO_PODR_BS_PODR_BS0 (0x01) +#define MCF5235_GPIO_PODR_BS_PODR_BS1 (0x02) +#define MCF5235_GPIO_PODR_BS_PODR_BS2 (0x04) +#define MCF5235_GPIO_PODR_BS_PODR_BS3 (0x08) +#define MCF5235_GPIO_PODR_CS_PODR_CS1 (0x02) +#define MCF5235_GPIO_PODR_CS_PODR_CS2 (0x04) +#define MCF5235_GPIO_PODR_CS_PODR_CS3 (0x08) +#define MCF5235_GPIO_PODR_CS_PODR_CS4 (0x10) +#define MCF5235_GPIO_PODR_CS_PODR_CS5 (0x20) +#define MCF5235_GPIO_PODR_CS_PODR_CS6 (0x40) +#define MCF5235_GPIO_PODR_CS_PODR_CS7 (0x80) +#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM0 (0x01) +#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM1 (0x02) +#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM2 (0x04) +#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM3 (0x08) +#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM4 (0x10) +#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM5 (0x20) +#define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) +#define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) +#define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) +#define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) +#define MCF5235_GPIO_PODR_UARTH_PODR_UARTH0 (0x01) +#define MCF5235_GPIO_PODR_UARTH_PODR_UARTH1 (0x02) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL0 (0x01) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL1 (0x02) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL2 (0x04) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL3 (0x08) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL4 (0x10) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL5 (0x20) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL6 (0x40) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL7 (0x80) +#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) +#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) +#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) +#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) +#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER4 (0x10) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER5 (0x20) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER6 (0x40) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER7 (0x80) +#define MCF5235_GPIO_PODR_ETPU_PODR_ETPU0 (0x01) +#define MCF5235_GPIO_PODR_ETPU_PODR_ETPU1 (0x02) +#define MCF5235_GPIO_PODR_ETPU_PODR_ETPU2 (0x04) +#define MCF5235_GPIO_PDDR_APDDR_PDDR_APDDR5 (0x20) +#define MCF5235_GPIO_PDDR_APDDR_PDDR_APDDR6 (0x40) +#define MCF5235_GPIO_PDDR_APDDR_PDDR_APDDR7 (0x80) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH0 (0x01) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH1 (0x02) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH2 (0x04) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH3 (0x08) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH4 (0x10) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH5 (0x20) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH6 (0x40) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH7 (0x80) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL0 (0x01) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL1 (0x02) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL2 (0x04) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL3 (0x08) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL4 (0x10) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL5 (0x20) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL6 (0x40) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL7 (0x80) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4 (0x10) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5 (0x20) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6 (0x40) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7 (0x80) +#define MCF5235_GPIO_PDDR_BS_PDDR_BS0 (0x01) +#define MCF5235_GPIO_PDDR_BS_PDDR_BS3(x) (((x)&0x07)<<1) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS1 (0x02) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS2 (0x04) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS3 (0x08) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS4 (0x10) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS5 (0x20) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS6 (0x40) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS7 (0x80) +#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM0 (0x01) +#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM1 (0x02) +#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM2 (0x04) +#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM3 (0x08) +#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM4 (0x10) +#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM5 (0x20) +#define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) +#define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) +#define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) +#define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) +#define MCF5235_GPIO_PDDR_UARTH_PDDR_UARTH0 (0x01) +#define MCF5235_GPIO_PDDR_UARTH_PDDR_UARTH1 (0x02) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL0 (0x01) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL1 (0x02) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL2 (0x04) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL3 (0x08) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL4 (0x10) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL5 (0x20) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL6 (0x40) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL7 (0x80) +#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) +#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) +#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) +#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) +#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER4 (0x10) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER5 (0x20) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER6 (0x40) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER7 (0x80) +#define MCF5235_GPIO_PDDR_ETPU_PDDR_ETPU0 (0x01) +#define MCF5235_GPIO_PDDR_ETPU_PDDR_ETPU1 (0x02) +#define MCF5235_GPIO_PDDR_ETPU_PDDR_ETPU2 (0x04) +#define MCF5235_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5 (0x20) +#define MCF5235_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6 (0x40) +#define MCF5235_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7 (0x80) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0 (0x01) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1 (0x02) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2 (0x04) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3 (0x08) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4 (0x10) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5 (0x20) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6 (0x40) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7 (0x80) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0 (0x01) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1 (0x02) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2 (0x04) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3 (0x08) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4 (0x10) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5 (0x20) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6 (0x40) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7 (0x80) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4 (0x10) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5 (0x20) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6 (0x40) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7 (0x80) +#define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS0 (0x01) +#define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS1 (0x02) +#define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS2 (0x04) +#define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS3 (0x08) +#define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) +#define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) +#define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) +#define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS6 (0x40) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS7 (0x80) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0 (0x01) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1 (0x02) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2 (0x04) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3 (0x08) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4 (0x10) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5 (0x20) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6 (0x40) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7 (0x80) +#define MCF5235_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0 (0x01) +#define MCF5235_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1 (0x02) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0 (0x01) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1 (0x02) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2 (0x04) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3 (0x08) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4 (0x10) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5 (0x20) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6 (0x40) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7 (0x80) +#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) +#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) +#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) +#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) +#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4 (0x10) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5 (0x20) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6 (0x40) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7 (0x80) +#define MCF5235_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0 (0x01) +#define MCF5235_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1 (0x02) +#define MCF5235_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2 (0x04) +#define MCF5235_GPIO_PCLRR_ADDR_PCLRR_ADDR5 (0x20) +#define MCF5235_GPIO_PCLRR_ADDR_PCLRR_ADDR6 (0x40) +#define MCF5235_GPIO_PCLRR_ADDR_PCLRR_ADDR7 (0x80) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH0 (0x01) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH1 (0x02) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH2 (0x04) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH3 (0x08) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH4 (0x10) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH5 (0x20) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH6 (0x40) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH7 (0x80) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL0 (0x01) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL1 (0x02) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL2 (0x04) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL3 (0x08) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL4 (0x10) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL5 (0x20) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL6 (0x40) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL7 (0x80) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4 (0x10) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5 (0x20) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6 (0x40) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7 (0x80) +#define MCF5235_GPIO_PCLRR_BS_PCLRR_BS0 (0x01) +#define MCF5235_GPIO_PCLRR_BS_PCLRR_BS1 (0x02) +#define MCF5235_GPIO_PCLRR_BS_PCLRR_BS2 (0x04) +#define MCF5235_GPIO_PCLRR_BS_PCLRR_BS3 (0x08) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS6 (0x40) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS7 (0x80)*/ +#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0 (0x01) +#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1 (0x02) +#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2 (0x04) +#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3 (0x08) +#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4 (0x10) +#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5 (0x20) +#define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) +#define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) +#define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) +#define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) +#define MCF5235_GPIO_PCLRR_UARTH_PCLRR_UARTH0 (0x01) +#define MCF5235_GPIO_PCLRR_UARTH_PCLRR_UARTH1 (0x02) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL0 (0x01) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL1 (0x02) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL2 (0x04) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL3 (0x08) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL4 (0x10) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL5 (0x20) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL6 (0x40) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL7 (0x80) +#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) +#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) +#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) +#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) +#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER4 (0x10) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER5 (0x20) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER6 (0x40) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER7 (0x80) +#define MCF5235_GPIO_PCLRR_ETPU_PCLRR_ETPU0 (0x01) +#define MCF5235_GPIO_PCLRR_ETPU_PCLRR_ETPU1 (0x02) +#define MCF5235_GPIO_PCLRR_ETPU_PCLRR_ETPU2 (0x04) +#define MCF5235_GPIO_PAR_AD_PAR_DATAL (0x01) +#define MCF5235_GPIO_PAR_AD_PAR_ADDR21 (0x20) +#define MCF5235_GPIO_PAR_AD_PAR_ADDR22 (0x40) +#define MCF5235_GPIO_PAR_AD_PAR_ADDR23 (0x80) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP(x) (((x)&0x0003)<<0) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x0003)<<2) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TSIZ0 (0x0010) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TSIZ1 (0x0040) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_RWB (0x0100) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA(x) (((x)&0x0003)<<10) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TA (0x1000) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_OE (0x4000) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA_GPIO (0x0000) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA_DMA (0x0800) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA_TEA (0x0C00) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x0000) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TS_DMA (0x0080) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TS_TS (0x00C0) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP_GPIO (0x0000) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP_DMA (0x0002) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP_TEA (0x0003) +#define MCF5235_GPIO_PAR_BS_PAR_BS0 (0x01) +#define MCF5235_GPIO_PAR_BS_PAR_BS1 (0x02) +#define MCF5235_GPIO_PAR_BS_PAR_BS2 (0x04) +#define MCF5235_GPIO_PAR_BS_PAR_BS3 (0x08) +#define MCF5235_GPIO_PAR_CS_PAR_CS1 (0x02) +#define MCF5235_GPIO_PAR_CS_PAR_CS2 (0x04) +#define MCF5235_GPIO_PAR_CS_PAR_CS3 (0x08) +#define MCF5235_GPIO_PAR_CS_PAR_CS4 (0x10) +#define MCF5235_GPIO_PAR_CS_PAR_CS5 (0x20) +#define MCF5235_GPIO_PAR_CS_PAR_CS6 (0x40) +#define MCF5235_GPIO_PAR_CS_PAR_CS7 (0x80) +#define MCF5235_GPIO_PAR_SDRAM_PAR_SDCS0 (0x01) +#define MCF5235_GPIO_PAR_SDRAM_PAR_SDCS1 (0x02) +#define MCF5235_GPIO_PAR_SDRAM_PAR_SCKE (0x04) +#define MCF5235_GPIO_PAR_SDRAM_PAR_SRAS (0x08) +#define MCF5235_GPIO_PAR_SDRAM_PAR_SCAS (0x10) +#define MCF5235_GPIO_PAR_SDRAM_PAR_SDWE (0x20) +#define MCF5235_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO(x) (((x)&0x03)<<4) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC(x) (((x)&0x03)<<6) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_GPIO (0x00) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_UART2 (0x40) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_I2C (0x80) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_FEC (0xC0) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO (0x00) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_UART2 (0x10) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_I2C (0x20) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_FEC (0x30) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SCL_FLEX (0x08) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SCL_I2C (0x0C) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SDA_FLEX (0x02) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SDA_I2C (0x03) +#define MCF5235_GPIO_PAR_UART_PAR_U0RTS (0x0001) +#define MCF5235_GPIO_PAR_UART_PAR_U0CTS (0x0002) +#define MCF5235_GPIO_PAR_UART_PAR_U0TXD (0x0004) +#define MCF5235_GPIO_PAR_UART_PAR_U0RXD (0x0008) +#define MCF5235_GPIO_PAR_UART_PAR_U1RTS(x) (((x)&0x0003)<<4) +#define MCF5235_GPIO_PAR_UART_PAR_U1CTS(x) (((x)&0x0003)<<6) +#define MCF5235_GPIO_PAR_UART_PAR_U1TXD(x) (((x)&0x0003)<<8) +#define MCF5235_GPIO_PAR_UART_PAR_U1RXD(x) (((x)&0x0003)<<10) +#define MCF5235_GPIO_PAR_UART_PAR_U2TXD (0x1000) +#define MCF5235_GPIO_PAR_UART_PAR_U2RXD (0x2000) +#define MCF5235_GPIO_PAR_UART_PAR_CAN1EN (0x4000) +#define MCF5235_GPIO_PAR_UART_PAR_DREQ2 (0x8000) +#define MCF5235_GPIO_PAR_UART_PAR_U1RXD_GPIO (0x0000) +#define MCF5235_GPIO_PAR_UART_PAR_U1RXD_FLEX (0x0800) +#define MCF5235_GPIO_PAR_UART_PAR_U1RXD_UART1 (0x0C00) +#define MCF5235_GPIO_PAR_UART_PAR_U1TXD_GPIO (0x0000) +#define MCF5235_GPIO_PAR_UART_PAR_U1TXD_FLEX (0x0200) +#define MCF5235_GPIO_PAR_UART_PAR_U1TXD_UART1 (0x0300) +#define MCF5235_GPIO_PAR_UART_PAR_U1CTS_GPIO (0x0000) +#define MCF5235_GPIO_PAR_UART_PAR_U1CTS_UART2 (0x0080) +#define MCF5235_GPIO_PAR_UART_PAR_U1CTS_UART1 (0x00C0) +#define MCF5235_GPIO_PAR_UART_PAR_U1RTS_GPIO (0x0000) +#define MCF5235_GPIO_PAR_UART_PAR_U1RTS_UART2 (0x0020) +#define MCF5235_GPIO_PAR_UART_PAR_U1RTS_UART1 (0x0030) +#define MCF5235_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x03)<<0) +#define MCF5235_GPIO_PAR_QSPI_PAR_DOUT (0x04) +#define MCF5235_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x03)<<3) +#define MCF5235_GPIO_PAR_QSPI_PAR_PCS0 (0x20) +#define MCF5235_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x03)<<6) +#define MCF5235_GPIO_PAR_QSPI_PAR_PCS1_GPIO (0x00) +#define MCF5235_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC (0x80) +#define MCF5235_GPIO_PAR_QSPI_PAR_PCS1_QSPI (0xC0) +#define MCF5235_GPIO_PAR_QSPI_PAR_DIN_GPIO (0x00) +#define MCF5235_GPIO_PAR_QSPI_PAR_DIN_I2C (0x10) +#define MCF5235_GPIO_PAR_QSPI_PAR_DIN_QSPI (0x1C) +#define MCF5235_GPIO_PAR_QSPI_PAR_SCK_GPIO (0x00) +#define MCF5235_GPIO_PAR_QSPI_PAR_SCK_I2C (0x02) +#define MCF5235_GPIO_PAR_QSPI_PAR_SCK_QSPI (0x03) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT(x) (((x)&0x0003)<<0) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT(x) (((x)&0x0003)<<2) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT(x) (((x)&0x0003)<<4) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT(x) (((x)&0x0003)<<6) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0IN(x) (((x)&0x0003)<<8) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN(x) (((x)&0x0003)<<10) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN(x) (((x)&0x0003)<<12) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN(x) (((x)&0x0003)<<14) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_QSPI (0x4000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_UART2 (0x8000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_T3IN (0xC000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_T2OUT (0x1000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_DMA (0x2000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_T2IN (0x3000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_T1OUT (0x0400) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_DMA (0x0800) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_T1IN (0x0C00) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0IN_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0IN_DMA (0x0200) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0IN_T0IN (0x0300) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_QSPI (0x0040) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_UART2 (0x0080) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT (0x00C0) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT_DMA (0x0020) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT (0x0030) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT_DMA (0x0008) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT (0x000C) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT_DMA (0x0002) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT (0x0003) +#define MCF5235_GPIO_PAR_ETPU_PAR_LTPU_ODIS (0x01) +#define MCF5235_GPIO_PAR_ETPU_PAR_UTPU_ODIS (0x02) +#define MCF5235_GPIO_PAR_ETPU_PAR_TCRCLK (0x04) +#define MCF5235_GPIO_DSCR_EIM_DSCR_EIM0 (0x01) +#define MCF5235_GPIO_DSCR_EIM_DSCR_EIM1 (0x10) +#define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_7_0 (0x01) +#define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_15_8 (0x04) +#define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_23_16 (0x10) +#define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_31_24 (0x40) +#define MCF5235_GPIO_DSCR_FECI2C_DSCR_I2C (0x01) +#define MCF5235_GPIO_DSCR_FECI2C_DSCR_FEC (0x10) +#define MCF5235_GPIO_DSCR_UART_DSCR_UART0 (0x01) +#define MCF5235_GPIO_DSCR_UART_DSCR_UART1 (0x04) +#define MCF5235_GPIO_DSCR_UART_DSCR_UART2 (0x10) +#define MCF5235_GPIO_DSCR_UART_DSCR_IRQ (0x40) +#define MCF5235_GPIO_DSCR_QSPI_DSCR_QSPI (0x01)*/ +#define MCF5235_GPIO_DSCR_TIMER_DSCR_TIMER (0x01) + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_I2C_I2AR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000300))) +#define MCF5235_I2C_I2FDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000304))) +#define MCF5235_I2C_I2CR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000308))) +#define MCF5235_I2C_I2SR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00030C))) +#define MCF5235_I2C_I2DR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000310))) +#define MCF5235_I2C_I2ICR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000320))) + +/* Bit definitions and macros for MCF5235_I2C_I2AR */ +#define MCF5235_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) +#define MCF5235_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) +#define MCF5235_I2C_I2CR_RSTA (0x04) +#define MCF5235_I2C_I2CR_TXAK (0x08) +#define MCF5235_I2C_I2CR_MTX (0x10) +#define MCF5235_I2C_I2CR_MSTA (0x20) +#define MCF5235_I2C_I2CR_IIEN (0x40) +#define MCF5235_I2C_I2CR_IEN (0x80) +#define MCF5235_I2C_I2SR_RXAK (0x01) +#define MCF5235_I2C_I2SR_IIF (0x02) +#define MCF5235_I2C_I2SR_SRW (0x04) +#define MCF5235_I2C_I2SR_IAL (0x10) +#define MCF5235_I2C_I2SR_IBB (0x20) +#define MCF5235_I2C_I2SR_IAAS (0x40) +#define MCF5235_I2C_I2SR_ICF (0x80) +#define MCF5235_I2C_I2ICR_IE (0x01) +#define MCF5235_I2C_I2ICR_RE (0x02) +#define MCF5235_I2C_I2ICR_TE (0x04) +#define MCF5235_I2C_I2ICR_BNBE (0x08) + +/********************************************************************* +* +* Interrupt Controller 0 (INTC0) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_INTC0_IPRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C00))) +#define MCF5235_INTC0_IPRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C04))) +#define MCF5235_INTC0_IMRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C08))) +#define MCF5235_INTC0_IMRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C0C))) +#define MCF5235_INTC0_INTFRCH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C10))) +#define MCF5235_INTC0_INTFRCL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C14))) +#define MCF5235_INTC0_IRLR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C18))) +#define MCF5235_INTC0_IACKLPR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C19))) +#define MCF5235_INTC0_ICR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C40))) +#define MCF5235_INTC0_ICR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C41))) +#define MCF5235_INTC0_ICR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C42))) +#define MCF5235_INTC0_ICR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C43))) +#define MCF5235_INTC0_ICR4 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C44))) +#define MCF5235_INTC0_ICR5 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C45))) +#define MCF5235_INTC0_ICR6 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C46))) +#define MCF5235_INTC0_ICR7 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C47))) +#define MCF5235_INTC0_ICR8 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C48))) +#define MCF5235_INTC0_ICR9 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C49))) +#define MCF5235_INTC0_ICR10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4A))) +#define MCF5235_INTC0_ICR11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4B))) +#define MCF5235_INTC0_ICR12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4C))) +#define MCF5235_INTC0_ICR13 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4D))) +#define MCF5235_INTC0_ICR14 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4E))) +#define MCF5235_INTC0_ICR15 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4F))) +#define MCF5235_INTC0_ICR16 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C50))) +#define MCF5235_INTC0_ICR17 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C51))) +#define MCF5235_INTC0_ICR18 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C52))) +#define MCF5235_INTC0_ICR19 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C53))) +#define MCF5235_INTC0_ICR20 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C54))) +#define MCF5235_INTC0_ICR21 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C55))) +#define MCF5235_INTC0_ICR22 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C56))) +#define MCF5235_INTC0_ICR23 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C57))) +#define MCF5235_INTC0_ICR24 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C58))) +#define MCF5235_INTC0_ICR25 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C59))) +#define MCF5235_INTC0_ICR26 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5A))) +#define MCF5235_INTC0_ICR27 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5B))) +#define MCF5235_INTC0_ICR28 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5C))) +#define MCF5235_INTC0_ICR29 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5D))) +#define MCF5235_INTC0_ICR30 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5E))) +#define MCF5235_INTC0_ICR31 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5F))) +#define MCF5235_INTC0_ICR32 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C60))) +#define MCF5235_INTC0_ICR33 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C61))) +#define MCF5235_INTC0_ICR34 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C62))) +#define MCF5235_INTC0_ICR35 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C63))) +#define MCF5235_INTC0_ICR36 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C64))) +#define MCF5235_INTC0_ICR37 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C65))) +#define MCF5235_INTC0_ICR38 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C66))) +#define MCF5235_INTC0_ICR39 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C67))) +#define MCF5235_INTC0_ICR40 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C68))) +#define MCF5235_INTC0_ICR41 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C69))) +#define MCF5235_INTC0_ICR42 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6A))) +#define MCF5235_INTC0_ICR43 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6B))) +#define MCF5235_INTC0_ICR44 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6C))) +#define MCF5235_INTC0_ICR45 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6D))) +#define MCF5235_INTC0_ICR46 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6E))) +#define MCF5235_INTC0_ICR47 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6F))) +#define MCF5235_INTC0_ICR48 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C70))) +#define MCF5235_INTC0_ICR49 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C71))) +#define MCF5235_INTC0_ICR50 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C72))) +#define MCF5235_INTC0_ICR51 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C73))) +#define MCF5235_INTC0_ICR52 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C74))) +#define MCF5235_INTC0_ICR53 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C75))) +#define MCF5235_INTC0_ICR54 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C76))) +#define MCF5235_INTC0_ICR55 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C77))) +#define MCF5235_INTC0_ICR56 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C78))) +#define MCF5235_INTC0_ICR57 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C79))) +#define MCF5235_INTC0_ICR58 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7A))) +#define MCF5235_INTC0_ICR59 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7B))) +#define MCF5235_INTC0_ICR60 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7C))) +#define MCF5235_INTC0_ICR61 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7D))) +#define MCF5235_INTC0_ICR62 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7E))) +#define MCF5235_INTC0_ICR63 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7F))) +#define MCF5235_INTC0_ICRn(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C40+((x)*0x001)))) +#define MCF5235_INTC0_SWIACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE0))) +#define MCF5235_INTC0_L1IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE4))) +#define MCF5235_INTC0_L2IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE8))) +#define MCF5235_INTC0_L3IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CEC))) +#define MCF5235_INTC0_L4IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CF0))) +#define MCF5235_INTC0_L5IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CF4))) +#define MCF5235_INTC0_L6IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CF8))) +#define MCF5235_INTC0_L7IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CFC))) +#define MCF5235_INTC0_LnIACK(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE4+((x)*0x004)))) +#define MCF5235_INTC1_IPRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D00))) +#define MCF5235_INTC1_IPRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D04))) +#define MCF5235_INTC1_IMRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D08))) +#define MCF5235_INTC1_IMRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D0C))) +#define MCF5235_INTC1_INTFRCH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D10))) +#define MCF5235_INTC1_INTFRCL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D14))) +#define MCF5235_INTC1_IRLR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D18))) +#define MCF5235_INTC1_IACKLPR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D19))) +#define MCF5235_INTC1_ICR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D40))) +#define MCF5235_INTC1_ICR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D41))) +#define MCF5235_INTC1_ICR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D42))) +#define MCF5235_INTC1_ICR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D43))) +#define MCF5235_INTC1_ICR4 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D44))) +#define MCF5235_INTC1_ICR5 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D45))) +#define MCF5235_INTC1_ICR6 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D46))) +#define MCF5235_INTC1_ICR7 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D47))) +#define MCF5235_INTC1_ICR8 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D48))) +#define MCF5235_INTC1_ICR9 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D49))) +#define MCF5235_INTC1_ICR10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4A))) +#define MCF5235_INTC1_ICR11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4B))) +#define MCF5235_INTC1_ICR12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4C))) +#define MCF5235_INTC1_ICR13 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4D))) +#define MCF5235_INTC1_ICR14 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4E))) +#define MCF5235_INTC1_ICR15 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4F))) +#define MCF5235_INTC1_ICR16 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D50))) +#define MCF5235_INTC1_ICR17 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D51))) +#define MCF5235_INTC1_ICR18 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D52))) +#define MCF5235_INTC1_ICR19 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D53))) +#define MCF5235_INTC1_ICR20 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D54))) +#define MCF5235_INTC1_ICR21 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D55))) +#define MCF5235_INTC1_ICR22 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D56))) +#define MCF5235_INTC1_ICR23 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D57))) +#define MCF5235_INTC1_ICR24 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D58))) +#define MCF5235_INTC1_ICR25 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D59))) +#define MCF5235_INTC1_ICR26 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5A))) +#define MCF5235_INTC1_ICR27 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5B))) +#define MCF5235_INTC1_ICR28 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5C))) +#define MCF5235_INTC1_ICR29 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5D))) +#define MCF5235_INTC1_ICR30 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5E))) +#define MCF5235_INTC1_ICR31 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5F))) +#define MCF5235_INTC1_ICR32 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D60))) +#define MCF5235_INTC1_ICR33 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D61))) +#define MCF5235_INTC1_ICR34 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D62))) +#define MCF5235_INTC1_ICR35 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D63))) +#define MCF5235_INTC1_ICR36 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D64))) +#define MCF5235_INTC1_ICR37 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D65))) +#define MCF5235_INTC1_ICR38 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D66))) +#define MCF5235_INTC1_ICR39 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D67))) +#define MCF5235_INTC1_ICR40 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D68))) +#define MCF5235_INTC1_ICR41 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D69))) +#define MCF5235_INTC1_ICR42 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6A))) +#define MCF5235_INTC1_ICR43 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6B))) +#define MCF5235_INTC1_ICR44 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6C))) +#define MCF5235_INTC1_ICR45 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6D))) +#define MCF5235_INTC1_ICR46 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6E))) +#define MCF5235_INTC1_ICR47 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6F))) +#define MCF5235_INTC1_ICR48 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D70))) +#define MCF5235_INTC1_ICR49 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D71))) +#define MCF5235_INTC1_ICR50 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D72))) +#define MCF5235_INTC1_ICR51 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D73))) +#define MCF5235_INTC1_ICR52 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D74))) +#define MCF5235_INTC1_ICR53 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D75))) +#define MCF5235_INTC1_ICR54 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D76))) +#define MCF5235_INTC1_ICR55 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D77))) +#define MCF5235_INTC1_ICR56 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D78))) +#define MCF5235_INTC1_ICR57 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D79))) +#define MCF5235_INTC1_ICR58 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7A))) +#define MCF5235_INTC1_ICR59 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7B))) +#define MCF5235_INTC1_ICR60 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7C))) +#define MCF5235_INTC1_ICR61 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7D))) +#define MCF5235_INTC1_ICR62 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7E))) +#define MCF5235_INTC1_ICR63 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7F))) +#define MCF5235_INTC1_ICRn(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D40+((x)*0x001)))) +#define MCF5235_INTC1_SWIACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE0))) +#define MCF5235_INTC1_L1IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE4))) +#define MCF5235_INTC1_L2IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE8))) +#define MCF5235_INTC1_L3IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DEC))) +#define MCF5235_INTC1_L4IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DF0))) +#define MCF5235_INTC1_L5IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DF4))) +#define MCF5235_INTC1_L6IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DF8))) +#define MCF5235_INTC1_L7IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DFC))) +#define MCF5235_INTC1_LnIACK(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE4+((x)*0x004)))) + +/* Bit definitions and macros for MCF5235_INTC0_IPRH */ +#define MCF5235_INTC0_IPRH_INT32 (0x00000001) +#define MCF5235_INTC0_IPRH_INT33 (0x00000002) +#define MCF5235_INTC0_IPRH_INT34 (0x00000004) +#define MCF5235_INTC0_IPRH_INT35 (0x00000008) +#define MCF5235_INTC0_IPRH_INT36 (0x00000010) +#define MCF5235_INTC0_IPRH_INT37 (0x00000020) +#define MCF5235_INTC0_IPRH_INT38 (0x00000040) +#define MCF5235_INTC0_IPRH_INT39 (0x00000080) +#define MCF5235_INTC0_IPRH_INT40 (0x00000100) +#define MCF5235_INTC0_IPRH_INT41 (0x00000200) +#define MCF5235_INTC0_IPRH_INT42 (0x00000400) +#define MCF5235_INTC0_IPRH_INT43 (0x00000800) +#define MCF5235_INTC0_IPRH_INT44 (0x00001000) +#define MCF5235_INTC0_IPRH_INT45 (0x00002000) +#define MCF5235_INTC0_IPRH_INT46 (0x00004000) +#define MCF5235_INTC0_IPRH_INT47 (0x00008000) +#define MCF5235_INTC0_IPRH_INT48 (0x00010000) +#define MCF5235_INTC0_IPRH_INT49 (0x00020000) +#define MCF5235_INTC0_IPRH_INT50 (0x00040000) +#define MCF5235_INTC0_IPRH_INT51 (0x00080000) +#define MCF5235_INTC0_IPRH_INT52 (0x00100000) +#define MCF5235_INTC0_IPRH_INT53 (0x00200000) +#define MCF5235_INTC0_IPRH_INT54 (0x00400000) +#define MCF5235_INTC0_IPRH_INT55 (0x00800000) +#define MCF5235_INTC0_IPRH_INT56 (0x01000000) +#define MCF5235_INTC0_IPRH_INT57 (0x02000000) +#define MCF5235_INTC0_IPRH_INT58 (0x04000000) +#define MCF5235_INTC0_IPRH_INT59 (0x08000000) +#define MCF5235_INTC0_IPRH_INT60 (0x10000000) +#define MCF5235_INTC0_IPRH_INT61 (0x20000000) +#define MCF5235_INTC0_IPRH_INT62 (0x40000000) +#define MCF5235_INTC0_IPRH_INT63 (0x80000000) +#define MCF5235_INTC0_IPRL_INT1 (0x00000002) +#define MCF5235_INTC0_IPRL_INT2 (0x00000004) +#define MCF5235_INTC0_IPRL_INT3 (0x00000008) +#define MCF5235_INTC0_IPRL_INT4 (0x00000010) +#define MCF5235_INTC0_IPRL_INT5 (0x00000020) +#define MCF5235_INTC0_IPRL_INT6 (0x00000040) +#define MCF5235_INTC0_IPRL_INT7 (0x00000080) +#define MCF5235_INTC0_IPRL_INT8 (0x00000100) +#define MCF5235_INTC0_IPRL_INT9 (0x00000200) +#define MCF5235_INTC0_IPRL_INT10 (0x00000400) +#define MCF5235_INTC0_IPRL_INT11 (0x00000800) +#define MCF5235_INTC0_IPRL_INT12 (0x00001000) +#define MCF5235_INTC0_IPRL_INT13 (0x00002000) +#define MCF5235_INTC0_IPRL_INT14 (0x00004000) +#define MCF5235_INTC0_IPRL_INT15 (0x00008000) +#define MCF5235_INTC0_IPRL_INT16 (0x00010000) +#define MCF5235_INTC0_IPRL_INT17 (0x00020000) +#define MCF5235_INTC0_IPRL_INT18 (0x00040000) +#define MCF5235_INTC0_IPRL_INT19 (0x00080000) +#define MCF5235_INTC0_IPRL_INT20 (0x00100000) +#define MCF5235_INTC0_IPRL_INT21 (0x00200000) +#define MCF5235_INTC0_IPRL_INT22 (0x00400000) +#define MCF5235_INTC0_IPRL_INT23 (0x00800000) +#define MCF5235_INTC0_IPRL_INT24 (0x01000000) +#define MCF5235_INTC0_IPRL_INT25 (0x02000000) +#define MCF5235_INTC0_IPRL_INT26 (0x04000000) +#define MCF5235_INTC0_IPRL_INT27 (0x08000000) +#define MCF5235_INTC0_IPRL_INT28 (0x10000000) +#define MCF5235_INTC0_IPRL_INT29 (0x20000000) +#define MCF5235_INTC0_IPRL_INT30 (0x40000000) +#define MCF5235_INTC0_IPRL_INT31 (0x80000000) +#define MCF5235_INTC0_IMRH_INT32 (0x00000001) +#define MCF5235_INTC0_IMRH_INT33 (0x00000002) +#define MCF5235_INTC0_IMRH_INT34 (0x00000004) +#define MCF5235_INTC0_IMRH_INT35 (0x00000008) +#define MCF5235_INTC0_IMRH_INT36 (0x00000010) +#define MCF5235_INTC0_IMRH_INT37 (0x00000020) +#define MCF5235_INTC0_IMRH_INT38 (0x00000040) +#define MCF5235_INTC0_IMRH_INT39 (0x00000080) +#define MCF5235_INTC0_IMRH_INT40 (0x00000100) +#define MCF5235_INTC0_IMRH_INT41 (0x00000200) +#define MCF5235_INTC0_IMRH_INT42 (0x00000400) +#define MCF5235_INTC0_IMRH_INT43 (0x00000800) +#define MCF5235_INTC0_IMRH_INT44 (0x00001000) +#define MCF5235_INTC0_IMRH_INT45 (0x00002000) +#define MCF5235_INTC0_IMRH_INT46 (0x00004000) +#define MCF5235_INTC0_IMRH_INT47 (0x00008000) +#define MCF5235_INTC0_IMRH_INT48 (0x00010000) +#define MCF5235_INTC0_IMRH_INT49 (0x00020000) +#define MCF5235_INTC0_IMRH_INT50 (0x00040000) +#define MCF5235_INTC0_IMRH_INT51 (0x00080000) +#define MCF5235_INTC0_IMRH_INT52 (0x00100000) +#define MCF5235_INTC0_IMRH_INT53 (0x00200000) +#define MCF5235_INTC0_IMRH_INT54 (0x00400000) +#define MCF5235_INTC0_IMRH_INT55 (0x00800000) +#define MCF5235_INTC0_IMRH_INT56 (0x01000000) +#define MCF5235_INTC0_IMRH_INT57 (0x02000000) +#define MCF5235_INTC0_IMRH_INT58 (0x04000000) +#define MCF5235_INTC0_IMRH_INT59 (0x08000000) +#define MCF5235_INTC0_IMRH_INT60 (0x10000000) +#define MCF5235_INTC0_IMRH_INT61 (0x20000000) +#define MCF5235_INTC0_IMRH_INT62 (0x40000000) +#define MCF5235_INTC0_IMRH_INT63 (0x80000000) +#define MCF5235_INTC0_IMRL_MASKALL (0x00000001) +#define MCF5235_INTC0_IMRL_INT1 (0x00000002) +#define MCF5235_INTC0_IMRL_INT2 (0x00000004) +#define MCF5235_INTC0_IMRL_INT3 (0x00000008) +#define MCF5235_INTC0_IMRL_INT4 (0x00000010) +#define MCF5235_INTC0_IMRL_INT5 (0x00000020) +#define MCF5235_INTC0_IMRL_INT6 (0x00000040) +#define MCF5235_INTC0_IMRL_INT7 (0x00000080) +#define MCF5235_INTC0_IMRL_INT8 (0x00000100) +#define MCF5235_INTC0_IMRL_INT9 (0x00000200) +#define MCF5235_INTC0_IMRL_INT10 (0x00000400) +#define MCF5235_INTC0_IMRL_INT11 (0x00000800) +#define MCF5235_INTC0_IMRL_INT12 (0x00001000) +#define MCF5235_INTC0_IMRL_INT13 (0x00002000) +#define MCF5235_INTC0_IMRL_INT14 (0x00004000) +#define MCF5235_INTC0_IMRL_INT15 (0x00008000) +#define MCF5235_INTC0_IMRL_INT16 (0x00010000) +#define MCF5235_INTC0_IMRL_INT17 (0x00020000) +#define MCF5235_INTC0_IMRL_INT18 (0x00040000) +#define MCF5235_INTC0_IMRL_INT19 (0x00080000) +#define MCF5235_INTC0_IMRL_INT20 (0x00100000) +#define MCF5235_INTC0_IMRL_INT21 (0x00200000) +#define MCF5235_INTC0_IMRL_INT22 (0x00400000) +#define MCF5235_INTC0_IMRL_INT23 (0x00800000) +#define MCF5235_INTC0_IMRL_INT24 (0x01000000) +#define MCF5235_INTC0_IMRL_INT25 (0x02000000) +#define MCF5235_INTC0_IMRL_INT26 (0x04000000) +#define MCF5235_INTC0_IMRL_INT27 (0x08000000) +#define MCF5235_INTC0_IMRL_INT28 (0x10000000) +#define MCF5235_INTC0_IMRL_INT29 (0x20000000) +#define MCF5235_INTC0_IMRL_INT30 (0x40000000) +#define MCF5235_INTC0_IMRL_INT31 (0x80000000) +#define MCF5235_INTC0_INTFRCH_INTFRC32 (0x00000001) +#define MCF5235_INTC0_INTFRCH_INTFRC33 (0x00000002) +#define MCF5235_INTC0_INTFRCH_INTFRC34 (0x00000004) +#define MCF5235_INTC0_INTFRCH_INTFRC35 (0x00000008) +#define MCF5235_INTC0_INTFRCH_INTFRC36 (0x00000010) +#define MCF5235_INTC0_INTFRCH_INTFRC37 (0x00000020) +#define MCF5235_INTC0_INTFRCH_INTFRC38 (0x00000040) +#define MCF5235_INTC0_INTFRCH_INTFRC39 (0x00000080) +#define MCF5235_INTC0_INTFRCH_INTFRC40 (0x00000100) +#define MCF5235_INTC0_INTFRCH_INTFRC41 (0x00000200) +#define MCF5235_INTC0_INTFRCH_INTFRC42 (0x00000400) +#define MCF5235_INTC0_INTFRCH_INTFRC43 (0x00000800) +#define MCF5235_INTC0_INTFRCH_INTFRC44 (0x00001000) +#define MCF5235_INTC0_INTFRCH_INTFRC45 (0x00002000) +#define MCF5235_INTC0_INTFRCH_INTFRC46 (0x00004000) +#define MCF5235_INTC0_INTFRCH_INTFRC47 (0x00008000) +#define MCF5235_INTC0_INTFRCH_INTFRC48 (0x00010000) +#define MCF5235_INTC0_INTFRCH_INTFRC49 (0x00020000) +#define MCF5235_INTC0_INTFRCH_INTFRC50 (0x00040000) +#define MCF5235_INTC0_INTFRCH_INTFRC51 (0x00080000) +#define MCF5235_INTC0_INTFRCH_INTFRC52 (0x00100000) +#define MCF5235_INTC0_INTFRCH_INTFRC53 (0x00200000) +#define MCF5235_INTC0_INTFRCH_INTFRC54 (0x00400000) +#define MCF5235_INTC0_INTFRCH_INTFRC55 (0x00800000) +#define MCF5235_INTC0_INTFRCH_INTFRC56 (0x01000000) +#define MCF5235_INTC0_INTFRCH_INTFRC57 (0x02000000) +#define MCF5235_INTC0_INTFRCH_INTFRC58 (0x04000000) +#define MCF5235_INTC0_INTFRCH_INTFRC59 (0x08000000) +#define MCF5235_INTC0_INTFRCH_INTFRC60 (0x10000000) +#define MCF5235_INTC0_INTFRCH_INTFRC61 (0x20000000) +#define MCF5235_INTC0_INTFRCH_INTFRC62 (0x40000000) +#define MCF5235_INTC0_INTFRCH_INTFRC63 (0x80000000) +#define MCF5235_INTC0_INTFRCL_INTFRC1 (0x00000002) +#define MCF5235_INTC0_INTFRCL_INTFRC2 (0x00000004) +#define MCF5235_INTC0_INTFRCL_INTFRC3 (0x00000008) +#define MCF5235_INTC0_INTFRCL_INTFRC4 (0x00000010) +#define MCF5235_INTC0_INTFRCL_INTFRC5 (0x00000020) +#define MCF5235_INTC0_INTFRCL_INT6 (0x00000040) +#define MCF5235_INTC0_INTFRCL_INT7 (0x00000080) +#define MCF5235_INTC0_INTFRCL_INT8 (0x00000100) +#define MCF5235_INTC0_INTFRCL_INT9 (0x00000200) +#define MCF5235_INTC0_INTFRCL_INT10 (0x00000400) +#define MCF5235_INTC0_INTFRCL_INTFRC11 (0x00000800) +#define MCF5235_INTC0_INTFRCL_INTFRC12 (0x00001000) +#define MCF5235_INTC0_INTFRCL_INTFRC13 (0x00002000) +#define MCF5235_INTC0_INTFRCL_INTFRC14 (0x00004000) +#define MCF5235_INTC0_INTFRCL_INT15 (0x00008000) +#define MCF5235_INTC0_INTFRCL_INTFRC16 (0x00010000) +#define MCF5235_INTC0_INTFRCL_INTFRC17 (0x00020000) +#define MCF5235_INTC0_INTFRCL_INTFRC18 (0x00040000) +#define MCF5235_INTC0_INTFRCL_INTFRC19 (0x00080000) +#define MCF5235_INTC0_INTFRCL_INTFRC20 (0x00100000) +#define MCF5235_INTC0_INTFRCL_INTFRC21 (0x00200000) +#define MCF5235_INTC0_INTFRCL_INTFRC22 (0x00400000) +#define MCF5235_INTC0_INTFRCL_INTFRC23 (0x00800000) +#define MCF5235_INTC0_INTFRCL_INTFRC24 (0x01000000) +#define MCF5235_INTC0_INTFRCL_INTFRC25 (0x02000000) +#define MCF5235_INTC0_INTFRCL_INTFRC26 (0x04000000) +#define MCF5235_INTC0_INTFRCL_INTFRC27 (0x08000000) +#define MCF5235_INTC0_INTFRCL_INTFRC28 (0x10000000) +#define MCF5235_INTC0_INTFRCL_INTFRC29 (0x20000000) +#define MCF5235_INTC0_INTFRCL_INTFRC30 (0x40000000) +#define MCF5235_INTC0_INTFRCL_INTFRC31 (0x80000000) +#define MCF5235_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1) +#define MCF5235_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF5235_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4) +#define MCF5235_INTC_ICR_IP(x) (((x)&0x07)<<0) +#define MCF5235_INTC_ICR_IL(x) (((x)&0x07)<<3) +#define MCF5235_INTC1_IPRH_INT32 (0x00000001) +#define MCF5235_INTC1_IPRH_INT33 (0x00000002) +#define MCF5235_INTC1_IPRH_INT34 (0x00000004) +#define MCF5235_INTC1_IPRH_INT35 (0x00000008) +#define MCF5235_INTC1_IPRH_INT36 (0x00000010) +#define MCF5235_INTC1_IPRH_INT37 (0x00000020) +#define MCF5235_INTC1_IPRH_INT38 (0x00000040) +#define MCF5235_INTC1_IPRH_INT39 (0x00000080) +#define MCF5235_INTC1_IPRH_INT40 (0x00000100) +#define MCF5235_INTC1_IPRH_INT41 (0x00000200) +#define MCF5235_INTC1_IPRH_INT42 (0x00000400) +#define MCF5235_INTC1_IPRH_INT43 (0x00000800) +#define MCF5235_INTC1_IPRH_INT44 (0x00001000) +#define MCF5235_INTC1_IPRH_INT45 (0x00002000) +#define MCF5235_INTC1_IPRH_INT46 (0x00004000) +#define MCF5235_INTC1_IPRH_INT47 (0x00008000) +#define MCF5235_INTC1_IPRH_INT48 (0x00010000) +#define MCF5235_INTC1_IPRH_INT49 (0x00020000) +#define MCF5235_INTC1_IPRH_INT50 (0x00040000) +#define MCF5235_INTC1_IPRH_INT51 (0x00080000) +#define MCF5235_INTC1_IPRH_INT52 (0x00100000) +#define MCF5235_INTC1_IPRH_INT53 (0x00200000) +#define MCF5235_INTC1_IPRH_INT54 (0x00400000) +#define MCF5235_INTC1_IPRH_INT55 (0x00800000) +#define MCF5235_INTC1_IPRH_INT56 (0x01000000) +#define MCF5235_INTC1_IPRH_INT57 (0x02000000) +#define MCF5235_INTC1_IPRH_INT58 (0x04000000) +#define MCF5235_INTC1_IPRH_INT59 (0x08000000) +#define MCF5235_INTC1_IPRH_INT60 (0x10000000) +#define MCF5235_INTC1_IPRH_INT61 (0x20000000) +#define MCF5235_INTC1_IPRH_INT62 (0x40000000) +#define MCF5235_INTC1_IPRH_INT63 (0x80000000) +#define MCF5235_INTC1_IPRL_INT1 (0x00000002) +#define MCF5235_INTC1_IPRL_INT2 (0x00000004) +#define MCF5235_INTC1_IPRL_INT3 (0x00000008) +#define MCF5235_INTC1_IPRL_INT4 (0x00000010) +#define MCF5235_INTC1_IPRL_INT5 (0x00000020) +#define MCF5235_INTC1_IPRL_INT6 (0x00000040) +#define MCF5235_INTC1_IPRL_INT7 (0x00000080) +#define MCF5235_INTC1_IPRL_INT8 (0x00000100) +#define MCF5235_INTC1_IPRL_INT9 (0x00000200) +#define MCF5235_INTC1_IPRL_INT10 (0x00000400) +#define MCF5235_INTC1_IPRL_INT11 (0x00000800) +#define MCF5235_INTC1_IPRL_INT12 (0x00001000) +#define MCF5235_INTC1_IPRL_INT13 (0x00002000) +#define MCF5235_INTC1_IPRL_INT14 (0x00004000) +#define MCF5235_INTC1_IPRL_INT15 (0x00008000) +#define MCF5235_INTC1_IPRL_INT16 (0x00010000) +#define MCF5235_INTC1_IPRL_INT17 (0x00020000) +#define MCF5235_INTC1_IPRL_INT18 (0x00040000) +#define MCF5235_INTC1_IPRL_INT19 (0x00080000) +#define MCF5235_INTC1_IPRL_INT20 (0x00100000) +#define MCF5235_INTC1_IPRL_INT21 (0x00200000) +#define MCF5235_INTC1_IPRL_INT22 (0x00400000) +#define MCF5235_INTC1_IPRL_INT23 (0x00800000) +#define MCF5235_INTC1_IPRL_INT24 (0x01000000) +#define MCF5235_INTC1_IPRL_INT25 (0x02000000) +#define MCF5235_INTC1_IPRL_INT26 (0x04000000) +#define MCF5235_INTC1_IPRL_INT27 (0x08000000) +#define MCF5235_INTC1_IPRL_INT28 (0x10000000) +#define MCF5235_INTC1_IPRL_INT29 (0x20000000) +#define MCF5235_INTC1_IPRL_INT30 (0x40000000) +#define MCF5235_INTC1_IPRL_INT31 (0x80000000) +#define MCF5235_INTC1_IMRH_INT_MASK32 (0x00000001) +#define MCF5235_INTC1_IMRH_INT_MASK33 (0x00000002) +#define MCF5235_INTC1_IMRH_INT_MASK34 (0x00000004) +#define MCF5235_INTC1_IMRH_INT_MASK35 (0x00000008) +#define MCF5235_INTC1_IMRH_INT_MASK36 (0x00000010) +#define MCF5235_INTC1_IMRH_INT_MASK37 (0x00000020) +#define MCF5235_INTC1_IMRH_INT_MASK38 (0x00000040) +#define MCF5235_INTC1_IMRH_INT_MASK39 (0x00000080) +#define MCF5235_INTC1_IMRH_INT_MASK40 (0x00000100) +#define MCF5235_INTC1_IMRH_INT_MASK41 (0x00000200) +#define MCF5235_INTC1_IMRH_INT_MASK42 (0x00000400) +#define MCF5235_INTC1_IMRH_INT_MASK43 (0x00000800) +#define MCF5235_INTC1_IMRH_INT_MASK44 (0x00001000) +#define MCF5235_INTC1_IMRH_INT_MASK45 (0x00002000) +#define MCF5235_INTC1_IMRH_INT_MASK46 (0x00004000) +#define MCF5235_INTC1_IMRH_INT_MASK47 (0x00008000) +#define MCF5235_INTC1_IMRH_INT_MASK48 (0x00010000) +#define MCF5235_INTC1_IMRH_INT_MASK49 (0x00020000) +#define MCF5235_INTC1_IMRH_INT_MASK50 (0x00040000) +#define MCF5235_INTC1_IMRH_INT_MASK51 (0x00080000) +#define MCF5235_INTC1_IMRH_INT_MASK52 (0x00100000) +#define MCF5235_INTC1_IMRH_INT_MASK53 (0x00200000) +#define MCF5235_INTC1_IMRH_INT_MASK54 (0x00400000) +#define MCF5235_INTC1_IMRH_INT_MASK55 (0x00800000) +#define MCF5235_INTC1_IMRH_INT_MASK56 (0x01000000) +#define MCF5235_INTC1_IMRH_INT_MASK57 (0x02000000) +#define MCF5235_INTC1_IMRH_INT_MASK58 (0x04000000) +#define MCF5235_INTC1_IMRH_INT_MASK59 (0x08000000) +#define MCF5235_INTC1_IMRH_INT_MASK60 (0x10000000) +#define MCF5235_INTC1_IMRH_INT_MASK61 (0x20000000) +#define MCF5235_INTC1_IMRH_INT_MASK62 (0x40000000) +#define MCF5235_INTC1_IMRH_INT_MASK63 (0x80000000) +#define MCF5235_INTC1_IMRL_MASKALL (0x00000001) +#define MCF5235_INTC1_IMRL_INT_MASK1 (0x00000002) +#define MCF5235_INTC1_IMRL_INT_MASK2 (0x00000004) +#define MCF5235_INTC1_IMRL_INT_MASK3 (0x00000008) +#define MCF5235_INTC1_IMRL_INT_MASK4 (0x00000010) +#define MCF5235_INTC1_IMRL_INT_MASK5 (0x00000020) +#define MCF5235_INTC1_IMRL_INT_MASK6 (0x00000040) +#define MCF5235_INTC1_IMRL_INT_MASK7 (0x00000080) +#define MCF5235_INTC1_IMRL_INT_MASK8 (0x00000100) +#define MCF5235_INTC1_IMRL_INT_MASK9 (0x00000200) +#define MCF5235_INTC1_IMRL_INT_MASK10 (0x00000400) +#define MCF5235_INTC1_IMRL_INT_MASK11 (0x00000800) +#define MCF5235_INTC1_IMRL_INT_MASK12 (0x00001000) +#define MCF5235_INTC1_IMRL_INT_MASK13 (0x00002000) +#define MCF5235_INTC1_IMRL_INT_MASK14 (0x00004000) +#define MCF5235_INTC1_IMRL_INT_MASK15 (0x00008000) +#define MCF5235_INTC1_IMRL_INT_MASK16 (0x00010000) +#define MCF5235_INTC1_IMRL_INT_MASK17 (0x00020000) +#define MCF5235_INTC1_IMRL_INT_MASK18 (0x00040000) +#define MCF5235_INTC1_IMRL_INT_MASK19 (0x00080000) +#define MCF5235_INTC1_IMRL_INT_MASK20 (0x00100000) +#define MCF5235_INTC1_IMRL_INT_MASK21 (0x00200000) +#define MCF5235_INTC1_IMRL_INT_MASK22 (0x00400000) +#define MCF5235_INTC1_IMRL_INT_MASK23 (0x00800000) +#define MCF5235_INTC1_IMRL_INT_MASK24 (0x01000000) +#define MCF5235_INTC1_IMRL_INT_MASK25 (0x02000000) +#define MCF5235_INTC1_IMRL_INT_MASK26 (0x04000000) +#define MCF5235_INTC1_IMRL_INT_MASK27 (0x08000000) +#define MCF5235_INTC1_IMRL_INT_MASK28 (0x10000000) +#define MCF5235_INTC1_IMRL_INT_MASK29 (0x20000000) +#define MCF5235_INTC1_IMRL_INT_MASK30 (0x40000000) +#define MCF5235_INTC1_IMRL_INT_MASK31 (0x80000000) +#define MCF5235_INTC1_INTFRCH_INTFRC32 (0x00000001) +#define MCF5235_INTC1_INTFRCH_INTFRC33 (0x00000002) +#define MCF5235_INTC1_INTFRCH_INTFRC34 (0x00000004) +#define MCF5235_INTC1_INTFRCH_INTFRC35 (0x00000008) +#define MCF5235_INTC1_INTFRCH_INTFRC36 (0x00000010) +#define MCF5235_INTC1_INTFRCH_INTFRC37 (0x00000020) +#define MCF5235_INTC1_INTFRCH_INTFRC38 (0x00000040) +#define MCF5235_INTC1_INTFRCH_INTFRC39 (0x00000080) +#define MCF5235_INTC1_INTFRCH_INTFRC40 (0x00000100) +#define MCF5235_INTC1_INTFRCH_INTFRC41 (0x00000200) +#define MCF5235_INTC1_INTFRCH_INTFRC42 (0x00000400) +#define MCF5235_INTC1_INTFRCH_INTFRC43 (0x00000800) +#define MCF5235_INTC1_INTFRCH_INTFRC44 (0x00001000) +#define MCF5235_INTC1_INTFRCH_INTFRC45 (0x00002000) +#define MCF5235_INTC1_INTFRCH_INTFRC46 (0x00004000) +#define MCF5235_INTC1_INTFRCH_INTFRC47 (0x00008000) +#define MCF5235_INTC1_INTFRCH_INTFRC48 (0x00010000) +#define MCF5235_INTC1_INTFRCH_INTFRC49 (0x00020000) +#define MCF5235_INTC1_INTFRCH_INTFRC50 (0x00040000) +#define MCF5235_INTC1_INTFRCH_INTFRC51 (0x00080000) +#define MCF5235_INTC1_INTFRCH_INTFRC52 (0x00100000) +#define MCF5235_INTC1_INTFRCH_INTFRC53 (0x00200000) +#define MCF5235_INTC1_INTFRCH_INTFRC54 (0x00400000) +#define MCF5235_INTC1_INTFRCH_INTFRC55 (0x00800000) +#define MCF5235_INTC1_INTFRCH_INTFRC56 (0x01000000) +#define MCF5235_INTC1_INTFRCH_INTFRC57 (0x02000000) +#define MCF5235_INTC1_INTFRCH_INTFRC58 (0x04000000) +#define MCF5235_INTC1_INTFRCH_INTFRC59 (0x08000000) +#define MCF5235_INTC1_INTFRCH_INTFRC60 (0x10000000) +#define MCF5235_INTC1_INTFRCH_INTFRC61 (0x20000000) +#define MCF5235_INTC1_INTFRCH_INTFRC62 (0x40000000) +#define MCF5235_INTC1_INTFRCH_INTFRC63 (0x80000000) +#define MCF5235_INTC1_INTFRCL_INTFRC1 (0x00000002) +#define MCF5235_INTC1_INTFRCL_INTFRC2 (0x00000004) +#define MCF5235_INTC1_INTFRCL_INTFRC3 (0x00000008) +#define MCF5235_INTC1_INTFRCL_INTFRC4 (0x00000010) +#define MCF5235_INTC1_INTFRCL_INTFRC5 (0x00000020) +#define MCF5235_INTC1_INTFRCL_INT6 (0x00000040) +#define MCF5235_INTC1_INTFRCL_INT7 (0x00000080) +#define MCF5235_INTC1_INTFRCL_INT8 (0x00000100) +#define MCF5235_INTC1_INTFRCL_INT9 (0x00000200) +#define MCF5235_INTC1_INTFRCL_INT10 (0x00000400) +#define MCF5235_INTC1_INTFRCL_INTFRC11 (0x00000800) +#define MCF5235_INTC1_INTFRCL_INTFRC12 (0x00001000) +#define MCF5235_INTC1_INTFRCL_INTFRC13 (0x00002000) +#define MCF5235_INTC1_INTFRCL_INTFRC14 (0x00004000) +#define MCF5235_INTC1_INTFRCL_INT15 (0x00008000) +#define MCF5235_INTC1_INTFRCL_INTFRC16 (0x00010000) +#define MCF5235_INTC1_INTFRCL_INTFRC17 (0x00020000) +#define MCF5235_INTC1_INTFRCL_INTFRC18 (0x00040000) +#define MCF5235_INTC1_INTFRCL_INTFRC19 (0x00080000) +#define MCF5235_INTC1_INTFRCL_INTFRC20 (0x00100000) +#define MCF5235_INTC1_INTFRCL_INTFRC21 (0x00200000) +#define MCF5235_INTC1_INTFRCL_INTFRC22 (0x00400000) +#define MCF5235_INTC1_INTFRCL_INTFRC23 (0x00800000) +#define MCF5235_INTC1_INTFRCL_INTFRC24 (0x01000000) +#define MCF5235_INTC1_INTFRCL_INTFRC25 (0x02000000) +#define MCF5235_INTC1_INTFRCL_INTFRC26 (0x04000000) +#define MCF5235_INTC1_INTFRCL_INTFRC27 (0x08000000) +#define MCF5235_INTC1_INTFRCL_INTFRC28 (0x10000000) +#define MCF5235_INTC1_INTFRCL_INTFRC29 (0x20000000) +#define MCF5235_INTC1_INTFRCL_INTFRC30 (0x40000000) +#define MCF5235_INTC1_INTFRCL_INTFRC31 (0x80000000) +#define MCF5235_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1) +#define MCF5235_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF5235_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4) + +/********************************************************************* +* +* Programmable Interrupt Timer Modules (PIT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_PIT_PCSR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x150000))) +#define MCF5235_PIT_PMR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x150002))) +#define MCF5235_PIT_PCNTR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x150004))) +#define MCF5235_PIT_PCSR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x160000))) +#define MCF5235_PIT_PMR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x160002))) +#define MCF5235_PIT_PCNTR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x160004))) +#define MCF5235_PIT_PCSR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x170000))) +#define MCF5235_PIT_PMR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x170002))) +#define MCF5235_PIT_PCNTR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x170004))) +#define MCF5235_PIT_PCSR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x180000))) +#define MCF5235_PIT_PMR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x180002))) +#define MCF5235_PIT_PCNTR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x180004))) +#define MCF5235_PIT_PCSR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x150000+((x)*0x10000)))) +#define MCF5235_PIT_PMR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x150002+((x)*0x10000)))) +#define MCF5235_PIT_PCNTR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x150004+((x)*0x10000)))) +#define MCF5235_PIT_PCSR_EN (0x0001) +#define MCF5235_PIT_PCSR_RLD (0x0002) +#define MCF5235_PIT_PCSR_PIF (0x0004) +#define MCF5235_PIT_PCSR_PIE (0x0008) +#define MCF5235_PIT_PCSR_OVW (0x0010) +#define MCF5235_PIT_PCSR_HALTED (0x0020) +#define MCF5235_PIT_PCSR_DOZE (0x0040) +#define MCF5235_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) +#define MCF5235_PIT_PMR_PM0 (0x0001) +#define MCF5235_PIT_PMR_PM1 (0x0002) +#define MCF5235_PIT_PMR_PM2 (0x0004) +#define MCF5235_PIT_PMR_PM3 (0x0008) +#define MCF5235_PIT_PMR_PM4 (0x0010) +#define MCF5235_PIT_PMR_PM5 (0x0020) +#define MCF5235_PIT_PMR_PM6 (0x0040) +#define MCF5235_PIT_PMR_PM7 (0x0080) +#define MCF5235_PIT_PMR_PM8 (0x0100) +#define MCF5235_PIT_PMR_PM9 (0x0200) +#define MCF5235_PIT_PMR_PM10 (0x0400) +#define MCF5235_PIT_PMR_PM11 (0x0800) +#define MCF5235_PIT_PMR_PM12 (0x1000) +#define MCF5235_PIT_PMR_PM13 (0x2000) +#define MCF5235_PIT_PMR_PM14 (0x4000) +#define MCF5235_PIT_PMR_PM15 (0x8000) +#define MCF5235_PIT_PCNTR_PC0 (0x0001) +#define MCF5235_PIT_PCNTR_PC1 (0x0002) +#define MCF5235_PIT_PCNTR_PC2 (0x0004) +#define MCF5235_PIT_PCNTR_PC3 (0x0008) +#define MCF5235_PIT_PCNTR_PC4 (0x0010) +#define MCF5235_PIT_PCNTR_PC5 (0x0020) +#define MCF5235_PIT_PCNTR_PC6 (0x0040) +#define MCF5235_PIT_PCNTR_PC7 (0x0080) +#define MCF5235_PIT_PCNTR_PC8 (0x0100) +#define MCF5235_PIT_PCNTR_PC9 (0x0200) +#define MCF5235_PIT_PCNTR_PC10 (0x0400) +#define MCF5235_PIT_PCNTR_PC11 (0x0800) +#define MCF5235_PIT_PCNTR_PC12 (0x1000) +#define MCF5235_PIT_PCNTR_PC13 (0x2000) +#define MCF5235_PIT_PCNTR_PC14 (0x4000) +#define MCF5235_PIT_PCNTR_PC15 (0x8000) + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_QSPI_QMR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000340))) +#define MCF5235_QSPI_QDLYR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000344))) +#define MCF5235_QSPI_QWR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000348))) +#define MCF5235_QSPI_QIR (*(vuint16*)((uintptr_t)__IPSBAR + (0x00034C))) +#define MCF5235_QSPI_QAR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000350))) +#define MCF5235_QSPI_QDR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000354))) + +/* Bit definitions and macros for MCF5235_QSPI_QMR */ +#define MCF5235_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) +#define MCF5235_QSPI_QMR_CPHA (0x0100) +#define MCF5235_QSPI_QMR_CPOL (0x0200) +#define MCF5235_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define MCF5235_QSPI_QMR_DOHIE (0x4000) +#define MCF5235_QSPI_QMR_MSTR (0x8000) +#define MCF5235_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) +#define MCF5235_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define MCF5235_QSPI_QDLYR_SPE (0x8000) +#define MCF5235_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) +#define MCF5235_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define MCF5235_QSPI_QWR_CSIV (0x1000) +#define MCF5235_QSPI_QWR_WRTO (0x2000) +#define MCF5235_QSPI_QWR_WREN (0x4000) +#define MCF5235_QSPI_QWR_HALT (0x8000) +#define MCF5235_QSPI_QIR_SPIF (0x0001) +#define MCF5235_QSPI_QIR_ABRT (0x0004) +#define MCF5235_QSPI_QIR_WCEF (0x0008) +#define MCF5235_QSPI_QIR_SPIFE (0x0100) +#define MCF5235_QSPI_QIR_ABRTE (0x0400) +#define MCF5235_QSPI_QIR_WCEFE (0x0800) +#define MCF5235_QSPI_QIR_ABRTL (0x1000) +#define MCF5235_QSPI_QIR_ABRTB (0x4000) +#define MCF5235_QSPI_QIR_WCEFB (0x8000) +#define MCF5235_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) + +/********************************************************************/ + + +#endif /* _CPU_MCF5235_H */ diff --git a/bsps/m68k/include/mcf5272/mcf5272.h b/bsps/m68k/include/mcf5272/mcf5272.h new file mode 100644 index 0000000000..37dae92d98 --- /dev/null +++ b/bsps/m68k/include/mcf5272/mcf5272.h @@ -0,0 +1,699 @@ +/* + * Coldfire MCF5272 definitions. + * Contents of this file based on information provided in + * Motorola MCF5272 User's Manual. + * + * Copyright (C) 2004 Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __MCF5272_H__ +#define __MCF5272_H__ + +#ifndef ASM +#include +#endif + +#define bit(x) (1 << (x)) + +#define MCF5272_SIM_BASE(mbar) ((mbar) + 0x0000) +#define MCF5272_INT_BASE(mbar) ((mbar) + 0x0020) +#define MCF5272_CS_BASE(mbar) ((mbar) + 0x0040) +#define MCF5272_GPIO_BASE(mbar) ((mbar) + 0x0080) +#define MCF5272_QSPI_BASE(mbar) ((mbar) + 0x00A0) +#define MCF5272_PWM_BASE(mbar) ((mbar) + 0x00C0) +#define MCF5272_DMAC_BASE(mbar) ((mbar) + 0x00E0) +#define MCF5272_UART0_BASE(mbar) ((mbar) + 0x0100) +#define MCF5272_UART1_BASE(mbar) ((mbar) + 0x0140) +#define MCF5272_SDRAMC_BASE(mbar) ((mbar) + 0x0180) +#define MCF5272_TIMER_BASE(mbar) ((mbar) + 0x0200) +#define MCF5272_PLIC_BASE(mbar) ((mbar) + 0x0300) +#define MCF5272_ENET_BASE(mbar) ((mbar) + 0x0840) +#define MCF5272_USB_BASE(mbar) ((mbar) + 0x1000) + + +/* RAMBAR - SRAM Base Address Register */ +#define MCF5272_RAMBAR_BA (0xfffff000) /* SRAM Base Address */ +#define MCF5272_RAMBAR_WP (0x00000100) /* Write Protect */ +#define MCF5272_RAMBAR_CI (0x00000020) /* CPU Space mask */ +#define MCF5272_RAMBAR_SC (0x00000010) /* Supervisor Code Space Mask */ +#define MCF5272_RAMBAR_SD (0x00000008) /* Supervisor Data Space Mask */ +#define MCF5272_RAMBAR_UC (0x00000004) /* User Code Space Mask */ +#define MCF5272_RAMBAR_UD (0x00000002) /* User Data Space Mask */ +#define MCF5272_RAMBAR_V (0x00000001) /* Contents of RAMBAR are valid */ + +/* MBAR - Module Base Address Register */ +#define MCF5272_MBAR_BA (0xffff0000) /* Base Address */ +#define MCF5272_MBAR_SC (0x00000010) /* Supervisor Code Space Mask */ +#define MCF5272_MBAR_SD (0x00000008) /* Supervisor Data Space Mask */ +#define MCF5272_MBAR_UC (0x00000004) /* User Code Space Mask */ +#define MCF5272_MBAR_UD (0x00000002) /* User Data Space Mask */ +#define MCF5272_MBAR_V (0x00000001) /* Contents of MBAR are valid */ + +/* CACR - Cache Control Register */ +#define MCF5272_CACR_CENB (0x80000000) /* Cache Enable */ +#define MCF5272_CACR_CPDI (0x10000000) /* Disable CPUSHL Invalidation */ +#define MCF5272_CACR_CFRZ (0x08000000) /* Cache Freeze */ +#define MCF5272_CACR_CINV (0x01000000) /* Cache Invalidate */ +#define MCF5272_CACR_CEIB (0x00000400) /* Cache Enable Noncacheable + instruction bursting */ +#define MCF5272_CACR_DCM (0x00000200) /* Default cache mode - noncacheable*/ +#define MCF5272_CACR_DBWE (0x00000100) /* Default Buffered Write Enable */ +#define MCF5272_CACR_DWP (0x00000020) /* Default Write Protection */ +#define MCF5272_CACR_CLNF (0x00000003) /* Cache Line Fill */ + +/* ACRx - Cache Access Control Registers */ +#define MCF5272_ACR_BA (0xff000000) /* Address Base */ +#define MCF5272_ACR_BAM (0x00ff0000) /* Address Mask */ +#define MCF5272_ACR_EN (0x00008000) /* Enable */ +#define MCF5272_ACR_SM_USR (0x00000000) /* Match if user mode */ +#define MCF5272_ACR_SM_SVR (0x00002000) /* Match if supervisor mode */ +#define MCF5272_ACR_SM_ANY (0x00004000) /* Match Always */ +#define MCF527_ACR_CM (0x00000040) /* Cache Mode (1 - noncacheable) */ +#define MCF5272_ACR_BWE (0x00000020) /* Buffered Write Enable */ +#define MCF5272_ACR_WP (0x00000004) /* Write Protect */ +#define MCF5272_ACR_BASE(base) ((base) & MCF5272_ACR_BA) +#define MCF5272_ACR_MASK(mask) (((mask) >> 8) & MCF5272_ACR_BAM) + + +#define MCF5272_ICR1_INT1_PI (bit(31)) +#define MCF5272_ICR1_INT1_IPL(x) ((x) << 28) +#define MCF5272_ICR1_INT1_MASK ((7) << 28) +#define MCF5272_ICR1_INT2_PI (bit(27)) +#define MCF5272_ICR1_INT2_IPL(x) ((x) << 24) +#define MCF5272_ICR1_INT2_MASK ((7) << 24) +#define MCF5272_ICR1_INT3_PI (bit(23)) +#define MCF5272_ICR1_INT3_IPL(x) ((x) << 20) +#define MCF5272_ICR1_INT3_MASK ((7) << 20) +#define MCF5272_ICR1_INT3_PI (bit(19)) +#define MCF5272_ICR1_INT3_IPL(x) ((x) << 16) +#define MCF5272_ICR1_INT3_MASK ((7) << 16) +#define MCF5272_ICR1_TMR0_PI (bit(15)) +#define MCF5272_ICR1_TMR0_IPL(x) ((x) << 12) +#define MCF5272_ICR1_TMR0_MASK ((7) << 12) +#define MCF5272_ICR1_TMR1_PI (bit(11)) +#define MCF5272_ICR1_TMR1_IPL(x) ((x) << 8) +#define MCF5272_ICR1_TMR1_MASK ((7) << 8) +#define MCF5272_ICR1_TMR2_PI (bit(7)) +#define MCF5272_ICR1_TMR2_IPL(x) ((x) << 4) +#define MCF5272_ICR1_TMR2_MASK ((7) << 4) +#define MCF5272_ICR1_TMR3_PI (bit(3)) +#define MCF5272_ICR1_TMR3_IPL(x) ((x) << 0) +#define MCF5272_ICR1_TMR3_MASK ((7) << 0) + +#define MCF5272_ICR3_USB4_PI (bit(31)) +#define MCF5272_ICR3_USB4_IPL(x) ((x) << 28) +#define MCF5272_ICR3_USB4_MASK ((7) << 28) +#define MCF5272_ICR3_USB5_PI (bit(27)) +#define MCF5272_ICR3_USB5_IPL(x) ((x) << 24) +#define MCF5272_ICR3_USB5_MASK ((7) << 24) +#define MCF5272_ICR3_USB6_PI (bit(23)) +#define MCF5272_ICR3_USB6_IPL(x) ((x) << 20) +#define MCF5272_ICR3_USB6_MASK ((7) << 20) +#define MCF5272_ICR3_USB7_PI (bit(19)) +#define MCF5272_ICR3_USB7_IPL(x) ((x) << 16) +#define MCF5272_ICR3_USB7_MASK ((7) << 16) +#define MCF5272_ICR3_DMA_PI (bit(15)) +#define MCF5272_ICR3_DMA_IPL(x) ((x) << 12) +#define MCF5272_ICR3_DMA_MASK ((7) << 12) +#define MCF5272_ICR3_ERX_PI (bit(11)) +#define MCF5272_ICR3_ERX_IPL(x) ((x) << 8) +#define MCF5272_ICR3_ERX_MASK ((7) << 8) +#define MCF5272_ICR3_ETX_PI (bit(7)) +#define MCF5272_ICR3_ETX_IPL(x) ((x) << 4) +#define MCF5272_ICR3_ETX_MASK ((7) << 4) +#define MCF5272_ICR3_ENTC_PI (bit(3)) +#define MCF5272_ICR3_ENTC_IPL(x) ((x) << 0) +#define MCF5272_ICR3_ENTC_MASK ((7) << 0) + + +#define MCF5272_USR_RB (bit(7)) +#define MCF5272_USR_FE (bit(6)) +#define MCF5272_USR_PE (bit(5)) +#define MCF5272_USR_OE (bit(4)) +#define MCF5272_USR_TXEMP (bit(3)) +#define MCF5272_USR_TXRDY (bit(2)) +#define MCF5272_USR_FFULL (bit(1)) +#define MCF5272_USR_RXRDY (bit(0)) + +#define MCF5272_TMR_PS_MASK 0xff00 +#define MCF5272_TMR_PS_SHIFT 8 +#define MCF5272_TMR_CE_DISABLE (0 << 6) +#define MCF5272_TMR_CE_RISING (1 << 6) +#define MCF5272_TMR_CE_FALLING (2 << 6) +#define MCF5272_TMR_CE_ANY (3 << 6) +#define MCF5272_TMR_OM (bit(5)) +#define MCF5272_TMR_ORI (bit(4)) +#define MCF5272_TMR_FRR (bit(3)) +#define MCF5272_TMR_CLK_STOP (0 << 1) +#define MCF5272_TMR_CLK_MSTR (1 << 1) +#define MCF5272_TMR_CLK_MSTR16 (2 << 1) +#define MCF5272_TMR_CLK_TIN (3 << 1) +#define MCF5272_TMR_RST (bit(0)) +#define MCF5272_TER_REF (bit(1)) +#define MCF5272_TER_CAP (bit(0)) + +#define MCF5272_SCR_PRI (bit(8)) +#define MCF5272_SCR_AR (bit(7)) +#define MCF5272_SCR_SRST (bit(6)) +#define MCF5272_SCR_BUSLOCK (bit(3)) +#define MCF5272_SCR_HWR_128 (0) +#define MCF5272_SCR_HWR_256 (1) +#define MCF5272_SCR_HWR_512 (2) +#define MCF5272_SCR_HWR_1024 (3) +#define MCF5272_SCR_HWR_2048 (4) +#define MCF5272_SCR_HWR_4096 (5) +#define MCF5272_SCR_HWR_8192 (6) +#define MCF5272_SCR_HWR_16384 (7) + +#define MCF5272_SPR_ADC (bit(15)) +#define MCF5272_SPR_WPV (bit(15)) +#define MCF5272_SPR_SMV (bit(15)) +#define MCF5272_SPR_PE (bit(15)) +#define MCF5272_SPR_HWT (bit(15)) +#define MCF5272_SPR_RPV (bit(15)) +#define MCF5272_SPR_EXT (bit(15)) +#define MCF5272_SPR_SUV (bit(15)) +#define MCF5272_SPR_ADCEN (bit(15)) +#define MCF5272_SPR_WPVEN (bit(15)) +#define MCF5272_SPR_SMVEN (bit(15)) +#define MCF5272_SPR_PEEN (bit(15)) +#define MCF5272_SPR_HWTEN (bit(15)) +#define MCF5272_SPR_RPVEN (bit(15)) +#define MCF5272_SPR_EXTEN (bit(15)) +#define MCF5272_SPR_SUVEN (bit(15)) + +#define MCF5272_ENET_TX_RT (bit(25)) +#define MCF5272_ENET_ETHERN_EN (bit(1)) +#define MCF5272_ENET_RESET (bit(0)) + +#define MCF5272_ENET_EIR_HBERR (bit(31)) +#define MCF5272_ENET_EIR_BABR (bit(30)) +#define MCF5272_ENET_EIR_BABT (bit(29)) +#define MCF5272_ENET_EIR_GRA (bit(28)) +#define MCF5272_ENET_EIR_TXF (bit(27)) +#define MCF5272_ENET_EIR_TXB (bit(26)) +#define MCF5272_ENET_EIR_RXF (bit(25)) +#define MCF5272_ENET_EIR_RXB (bit(24)) +#define MCF5272_ENET_EIR_MII (bit(23)) +#define MCF5272_ENET_EIR_EBERR (bit(22)) +#define MCF5272_ENET_EIR_UMINT (bit(21)) + +#define MCF5272_ENET_RCR_PROM (bit(3)) +#define MCF5272_ENET_RCR_MII (bit(2)) +#define MCF5272_ENET_RCR_DRT (bit(1)) +#define MCF5272_ENET_RCR_LOOP (bit(0)) + +#define MCF5272_ENET_TCR_FDEN (bit(2)) +#define MCF5272_ENET_TCR_HBC (bit(1)) +#define MCF5272_ENET_TCR_GTS (bit(0)) + + +#ifndef ASM +typedef struct { + volatile uint32_t mbar; /* READ ONLY!! */ + + volatile uint16_t scr; + volatile uint16_t _res0; + + volatile uint16_t _res1; + volatile uint16_t spr; + + volatile uint32_t pmr; + + volatile uint16_t _res2; + volatile uint16_t alpr; + + volatile uint32_t dir; +} sim_regs_t; + +typedef struct { + volatile uint32_t icr1; + volatile uint32_t icr2; + volatile uint32_t icr3; + volatile uint32_t icr4; + volatile uint32_t isr; + volatile uint32_t pitr; + volatile uint32_t piwr; + volatile uint8_t _res0[3]; + volatile uint8_t pivr; +} intctrl_regs_t; + +typedef struct { + volatile uint32_t csbr0; + volatile uint32_t csor0; + volatile uint32_t csbr1; + volatile uint32_t csor1; + volatile uint32_t csbr2; + volatile uint32_t csor2; + volatile uint32_t csbr3; + volatile uint32_t csor3; + volatile uint32_t csbr4; + volatile uint32_t csor4; + volatile uint32_t csbr5; + volatile uint32_t csor5; + volatile uint32_t csbr6; + volatile uint32_t csor6; + volatile uint32_t csbr7; + volatile uint32_t csor7; +} chipsel_regs_t; + +typedef struct { + volatile uint32_t pacnt; + + volatile uint16_t paddr; + volatile uint16_t _res0; + + volatile uint16_t _res1; + volatile uint16_t padat; + + volatile uint32_t pbcnt; + + volatile uint16_t pbddr; + volatile uint16_t _res2; + + volatile uint16_t _res3; + volatile uint16_t pbdat; + + volatile uint16_t pcddr; + volatile uint16_t _res4; + + volatile uint16_t _res5; + volatile uint16_t pcdat; + + volatile uint32_t pdcnt; +} gpio_regs_t; + +typedef struct { + volatile uint32_t qmr; + volatile uint32_t qdlyr; + volatile uint32_t qwr; + volatile uint32_t qir; + volatile uint32_t qar; + volatile uint32_t qdr; +} qspi_regs_t; + +typedef struct { + volatile uint8_t pwcr1; + volatile uint8_t _res0[3]; + + volatile uint8_t pwcr2; + volatile uint8_t _res1[3]; + + volatile uint8_t pwcr3; + volatile uint8_t _res2[3]; + + volatile uint8_t pwwd1; + volatile uint8_t _res3[3]; + + volatile uint8_t pwwd2; + volatile uint8_t _res4[3]; + + volatile uint8_t pwwd3; + volatile uint8_t _res5[3]; +} pwm_regs_t; + +typedef struct { + volatile uint32_t dcmr; + + volatile uint16_t _res0; + volatile uint16_t dcir; + + volatile uint32_t dbcr; + + volatile uint32_t dsar; + + volatile uint32_t ddar; +} dma_regs_t; + +typedef struct { + volatile uint8_t umr; /* 0x000 */ + volatile uint8_t _res0[3]; + + volatile uint8_t ucsr; /* 0x004 */ + volatile uint8_t _res2[3]; + + volatile uint8_t ucr; /* 0x008 */ + volatile uint8_t _res3[3]; + + volatile uint8_t udata; /* 0x00c */ + volatile uint8_t _res4[3]; + + volatile uint8_t uccr; /* 0x010 */ + volatile uint8_t _res6[3]; + + volatile uint8_t uisr; /* 0x014 */ + volatile uint8_t _res8[3]; + + volatile uint8_t ubg1; /* 0x018 */ + volatile uint8_t _res10[3]; + + volatile uint8_t ubg2; /* 0x01c */ + volatile uint8_t _res11[3]; + + volatile uint8_t uabr1; /* 0x020 */ + volatile uint8_t _res12[3]; + + volatile uint8_t uabr2; /* 0x024 */ + volatile uint8_t _res13[3]; + + volatile uint8_t utxfcsr; /* 0x028 */ + volatile uint8_t _res14[3]; + + volatile uint8_t urxfcsr; /* 0x02c */ + volatile uint8_t _res15[3]; + + volatile uint8_t ufpdn; /* 0x030 */ + volatile uint8_t _res16[3]; + + volatile uint8_t uip; /* 0x034 */ + volatile uint8_t _res17[3]; + + volatile uint8_t uop1; /* 0x038 */ + volatile uint8_t _res18[3]; + + volatile uint8_t uop0; /* 0x03c */ + volatile uint8_t _res19[3]; +} uart_regs_t; + +typedef struct { + volatile uint16_t tmr0; + volatile uint16_t _res0; + + volatile uint16_t trr0; + volatile uint16_t _res1; + + volatile uint16_t tcap0; + volatile uint16_t _res2; + + volatile uint16_t tcn0; + volatile uint16_t _res3; + + volatile uint16_t ter0; + volatile uint16_t _res4; + + volatile uint8_t _res40[12]; + + volatile uint16_t tmr1; + volatile uint16_t _res5; + + volatile uint16_t trr1; + volatile uint16_t _res6; + + volatile uint16_t tcap1; + volatile uint16_t _res7; + + volatile uint16_t tcn1; + volatile uint16_t _res8; + + volatile uint16_t ter1; + volatile uint16_t _res9; + + volatile uint8_t _res91[12]; + + volatile uint16_t tmr2; + volatile uint16_t _res10; + + volatile uint16_t trr2; + volatile uint16_t _res11; + + volatile uint16_t tcap2; + volatile uint16_t _res12; + + volatile uint16_t tcn2; + volatile uint16_t _res13; + + volatile uint16_t ter2; + volatile uint16_t _res14; + + volatile uint8_t _res140[12]; + + volatile uint16_t tmr3; + volatile uint16_t _res15; + + volatile uint16_t trr3; + volatile uint16_t _res16; + + volatile uint16_t tcap3; + volatile uint16_t _res17; + + volatile uint16_t tcn3; + volatile uint16_t _res18; + + volatile uint16_t ter3; + volatile uint16_t _res19; + + volatile uint8_t _res190[12]; + + volatile uint16_t wrrr; + volatile uint16_t _res20; + + volatile uint16_t wirr; + volatile uint16_t _res21; + + volatile uint16_t wcr; + volatile uint16_t _res22; + + volatile uint16_t wer; + volatile uint16_t _res23; +} timer_regs_t; + +typedef struct { + volatile uint32_t p0b1rr; + volatile uint32_t p1b1rr; + volatile uint32_t p2b1rr; + volatile uint32_t p3b1rr; + volatile uint32_t p0b2rr; + volatile uint32_t p1b2rr; + volatile uint32_t p2b2rr; + volatile uint32_t p3b2rr; + + volatile uint8_t p0drr; + volatile uint8_t p1drr; + volatile uint8_t p2drr; + volatile uint8_t p3drr; + + volatile uint32_t p0b1tr; + volatile uint32_t p1b1tr; + volatile uint32_t p2b1tr; + volatile uint32_t p3b1tr; + volatile uint32_t p0b2tr; + volatile uint32_t p1b2tr; + volatile uint32_t p2b2tr; + volatile uint32_t p3b2tr; + + volatile uint8_t p0dtr; + volatile uint8_t p1dtr; + volatile uint8_t p2dtr; + volatile uint8_t p3dtr; + + volatile uint16_t p0cr; + volatile uint16_t p1cr; + volatile uint16_t p2cr; + volatile uint16_t p3cr; + volatile uint16_t p0icr; + volatile uint16_t p1icr; + volatile uint16_t p2icr; + volatile uint16_t p3icr; + volatile uint16_t p0gmr; + volatile uint16_t p1gmr; + volatile uint16_t p2gmr; + volatile uint16_t p3gmr; + volatile uint16_t p0gmt; + volatile uint16_t p1gmt; + volatile uint16_t p2gmt; + volatile uint16_t p3gmt; + + volatile uint8_t _res0; + volatile uint8_t pgmts; + volatile uint8_t pgmta; + volatile uint8_t _res1; + volatile uint8_t p0gcir; + volatile uint8_t p1gcir; + volatile uint8_t p2gcir; + volatile uint8_t p3gcir; + volatile uint8_t p0gcit; + volatile uint8_t p1gcit; + volatile uint8_t p2gcit; + volatile uint8_t p3gcit; + volatile uint8_t _res3[3]; + volatile uint8_t pgcitsr; + volatile uint8_t _res4[3]; + volatile uint8_t pdcsr; + + volatile uint16_t p0psr; + volatile uint16_t p1psr; + volatile uint16_t p2psr; + volatile uint16_t p3psr; + volatile uint16_t pasr; + volatile uint8_t _res5; + volatile uint8_t plcr; + volatile uint16_t _res6; + volatile uint16_t pdrqr; + volatile uint16_t p0sdr; + volatile uint16_t p1sdr; + volatile uint16_t p2sdr; + volatile uint16_t p3sdr; + volatile uint16_t _res7; + volatile uint16_t pcsr; +} plic_regs_t; + +typedef struct { + volatile uint32_t ecr; + volatile uint32_t eir; + volatile uint32_t eimr; + volatile uint32_t ivsr; + volatile uint32_t rdar; + volatile uint32_t tdar; + volatile uint32_t _res0[10]; + volatile uint32_t mmfr; + volatile uint32_t mscr; + volatile uint32_t _res1[17]; + volatile uint32_t frbr; + volatile uint32_t frsr; + volatile uint32_t _res2[4]; + volatile uint32_t tfwr; + volatile uint32_t _res3[1]; + volatile uint32_t tfsr; + volatile uint32_t _res4[21]; + volatile uint32_t rcr; + volatile uint32_t mflr; + volatile uint32_t _res5[14]; + volatile uint32_t tcr; + volatile uint32_t _res6[158]; + volatile uint32_t malr; + volatile uint32_t maur; + volatile uint32_t htur; + volatile uint32_t htlr; + volatile uint32_t erdsr; + volatile uint32_t etdsr; + volatile uint32_t emrbr; +/* volatile uint8_t fifo[448]; */ +} enet_regs_t; + +typedef struct { + volatile uint16_t _res0; + volatile uint16_t fnr; + volatile uint16_t _res1; + volatile uint16_t fnmr; + volatile uint16_t _res2; + volatile uint16_t rfmr; + volatile uint16_t _res3; + volatile uint16_t rfmmr; + volatile uint8_t _res4[3]; + volatile uint8_t far; + volatile uint32_t asr; + volatile uint32_t drr1; + volatile uint32_t drr2; + volatile uint16_t _res5; + volatile uint16_t specr; + volatile uint16_t _res6; + volatile uint16_t ep0sr; + + volatile uint32_t iep0cfg; + volatile uint32_t oep0cfg; + volatile uint32_t ep1cfg; + volatile uint32_t ep2cfg; + volatile uint32_t ep3cfg; + volatile uint32_t ep4cfg; + volatile uint32_t ep5cfg; + volatile uint32_t ep6cfg; + volatile uint32_t ep7cfg; + volatile uint32_t ep0ctl; + + volatile uint16_t _res7; + volatile uint16_t ep1ctl; + volatile uint16_t _res8; + volatile uint16_t ep2ctl; + volatile uint16_t _res9; + volatile uint16_t ep3ctl; + volatile uint16_t _res10; + volatile uint16_t ep4ctl; + volatile uint16_t _res11; + volatile uint16_t ep5ctl; + volatile uint16_t _res12; + volatile uint16_t ep6ctl; + volatile uint16_t _res13; + volatile uint16_t ep7ctl; + + volatile uint32_t ep0isr; + + volatile uint16_t _res14; + volatile uint16_t ep1isr; + volatile uint16_t _res15; + volatile uint16_t ep2isr; + volatile uint16_t _res16; + volatile uint16_t ep3isr; + volatile uint16_t _res17; + volatile uint16_t ep4isr; + volatile uint16_t _res18; + volatile uint16_t ep5isr; + volatile uint16_t _res19; + volatile uint16_t ep6isr; + volatile uint16_t _res20; + volatile uint16_t ep7isr; + + volatile uint32_t ep0imr; + + volatile uint16_t _res21; + volatile uint16_t ep1imr; + volatile uint16_t _res22; + volatile uint16_t ep2imr; + volatile uint16_t _res23; + volatile uint16_t ep3imr; + volatile uint16_t _res24; + volatile uint16_t ep4imr; + volatile uint16_t _res25; + volatile uint16_t ep5imr; + volatile uint16_t _res26; + volatile uint16_t ep6imr; + volatile uint16_t _res27; + volatile uint16_t ep7imr; + + volatile uint32_t ep0dr; + volatile uint32_t ep1dr; + volatile uint32_t ep2dr; + volatile uint32_t ep3dr; + volatile uint32_t ep4dr; + volatile uint32_t ep5dr; + volatile uint32_t ep6dr; + volatile uint32_t ep7dr; + + volatile uint16_t _res28; + volatile uint16_t ep0dpr; + volatile uint16_t _res29; + volatile uint16_t ep1dpr; + volatile uint16_t _res30; + volatile uint16_t ep2dpr; + volatile uint16_t _res31; + volatile uint16_t ep3dpr; + volatile uint16_t _res32; + volatile uint16_t ep4dpr; + volatile uint16_t _res33; + volatile uint16_t ep5dpr; + volatile uint16_t _res34; + volatile uint16_t ep6dpr; + volatile uint16_t _res35; + volatile uint16_t ep7dpr; +/* uint8_t ram[1024]; */ +} usb_regs_t; + +extern intctrl_regs_t *g_intctrl_regs; +extern chipsel_regs_t *g_chipsel_regs; +extern gpio_regs_t *g_gpio_regs; +extern qspi_regs_t *g_qspi_regs; +extern pwm_regs_t *g_pwm_regs; +extern dma_regs_t *g_dma_regs; +extern uart_regs_t *g_uart0_regs; +extern uart_regs_t *g_uart1_regs; +extern timer_regs_t *g_timer_regs; +extern plic_regs_t *g_plic_regs; +extern enet_regs_t *g_enet_regs; +extern usb_regs_t *g_usb_regs; + +#endif /* ASM */ + +#endif /* __MCF5272_H__ */ diff --git a/bsps/m68k/include/mcf5282/mcf5282.h b/bsps/m68k/include/mcf5282/mcf5282.h new file mode 100644 index 0000000000..3724f489de --- /dev/null +++ b/bsps/m68k/include/mcf5282/mcf5282.h @@ -0,0 +1,2407 @@ +/* + ******************************************* + * Definitions from Motorola/FreeScale * + ******************************************* + */ + +/* + * File: mcf5282.h + * Purpose: MCF5282 definitions + * + * Notes: + */ + +#ifndef _CPU_MCF5282_H +#define _CPU_MCF5282_H + +/********************************************************************/ + +/* + * File: mcf5xxx.h + * Purpose: Definitions common to all ColdFire processors + * + * Notes: + */ + +#ifndef _CPU_MCF5XXX_H +#define _CPU_MCF5XXX_H + +/***********************************************************************/ +/* + * The basic data types + * + * Those are low-level so we mark them so that they may alias anything + */ + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16 __attribute__((__may_alias__)); /* 16 bits */ +typedef unsigned long int uint32 __attribute__((__may_alias__)); /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16 __attribute__((__may_alias__)); /* 16 bits */ +typedef signed long int int32 __attribute__((__may_alias__)); /* 32 bits */ + +typedef volatile uint8 vuint8 __attribute__((__may_alias__)); /* 8 bits */ +typedef volatile uint16 vuint16 __attribute__((__may_alias__)); /* 16 bits */ +typedef volatile uint32 vuint32 __attribute__((__may_alias__)); /* 32 bits */ + +/***********************************************************************/ +/* + * Common M68K & ColdFire definitions + */ + +#define ADDRESS uint32 +#define INSTRUCTION uint16 +#define ILLEGAL 0x4AFC +#define CPU_WORD_SIZE 16 + +#define MCF5XXX_SR_T (0x8000) +#define MCF5XXX_SR_S (0x2000) +#define MCF5XXX_SR_M (0x1000) +#define MCF5XXX_SR_IPL (0x0700) +#define MCF5XXX_SR_IPL_0 (0x0000) +#define MCF5XXX_SR_IPL_1 (0x0100) +#define MCF5XXX_SR_IPL_2 (0x0200) +#define MCF5XXX_SR_IPL_3 (0x0300) +#define MCF5XXX_SR_IPL_4 (0x0400) +#define MCF5XXX_SR_IPL_5 (0x0500) +#define MCF5XXX_SR_IPL_6 (0x0600) +#define MCF5XXX_SR_IPL_7 (0x0700) +#define MCF5XXX_SR_X (0x0010) +#define MCF5XXX_SR_N (0x0008) +#define MCF5XXX_SR_Z (0x0004) +#define MCF5XXX_SR_V (0x0002) +#define MCF5XXX_SR_C (0x0001) + +/* + * Used to set the initialize the cacr register to the BSP's desired + * starting value. + */ +void mcf5xxx_initialize_cacr(uint32_t); + +#define MCF5XXX_CACR_CENB (0x80000000) +#define MCF5XXX_CACR_CPDI (0x10000000) +#define MCF5XXX_CACR_CPD (0x10000000) +#define MCF5XXX_CACR_CFRZ (0x08000000) +#define MCF5XXX_CACR_CINV (0x01000000) +#define MCF5XXX_CACR_DIDI (0x00800000) +#define MCF5XXX_CACR_DISD (0x00400000) +#define MCF5XXX_CACR_INVI (0x00200000) +#define MCF5XXX_CACR_INVD (0x00100000) +#define MCF5XXX_CACR_CEIB (0x00000400) +#define MCF5XXX_CACR_DCM_WR (0x00000000) +#define MCF5XXX_CACR_DCM_CB (0x00000100) +#define MCF5XXX_CACR_DCM_IP (0x00000200) +#define MCF5XXX_CACR_DCM (0x00000200) +#define MCF5XXX_CACR_DCM_II (0x00000300) +#define MCF5XXX_CACR_DBWE (0x00000100) +#define MCF5XXX_CACR_DWP (0x00000020) +#define MCF5XXX_CACR_EUST (0x00000010) +#define MCF5XXX_CACR_CLNF_00 (0x00000000) +#define MCF5XXX_CACR_CLNF_01 (0x00000002) +#define MCF5XXX_CACR_CLNF_10 (0x00000004) +#define MCF5XXX_CACR_CLNF_11 (0x00000006) + +#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) +#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) +#define MCF5XXX_ACR_EN (0x00008000) +#define MCF5XXX_ACR_SM_USER (0x00000000) +#define MCF5XXX_ACR_SM_SUPER (0x00002000) +#define MCF5XXX_ACR_SM_IGNORE (0x00006000) +#define MCF5XXX_ACR_ENIB (0x00000080) +#define MCF5XXX_ACR_CM (0x00000040) +#define MCF5XXX_ACR_DCM_WR (0x00000000) +#define MCF5XXX_ACR_DCM_CB (0x00000020) +#define MCF5XXX_ACR_DCM_IP (0x00000040) +#define MCF5XXX_ACR_DCM_II (0x00000060) +#define MCF5XXX_ACR_CM (0x00000040) +#define MCF5XXX_ACR_BWE (0x00000020) +#define MCF5XXX_ACR_WP (0x00000004) + +#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) +#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) +#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) +#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) +#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) +#define MCF5XXX_RAMBAR_WP (0x00000100) +#define MCF5XXX_RAMBAR_CI (0x00000020) +#define MCF5XXX_RAMBAR_SC (0x00000010) +#define MCF5XXX_RAMBAR_SD (0x00000008) +#define MCF5XXX_RAMBAR_UC (0x00000004) +#define MCF5XXX_RAMBAR_UD (0x00000002) +#define MCF5XXX_RAMBAR_V (0x00000001) + +/***********************************************************************/ +/* + * The ColdFire family of processors has a simplified exception stack + * frame that looks like the following: + * + * 3322222222221111 111111 + * 1098765432109876 5432109876543210 + * 8 +----------------+----------------+ + * | Program Counter | + * 4 +----------------+----------------+ + * |FS/Fmt/Vector/FS| SR | + * SP --> 0 +----------------+----------------+ + * + * The stack self-aligns to a 4-byte boundary at an exception, with + * the FS/Fmt/Vector/FS field indicating the size of the adjustment + * (SP += 0,1,2,3 bytes). + */ + +#define MCF5XXX_RD_SF_FORMAT(PTR) \ + ((*((uint16 *)(PTR)) >> 12) & 0x00FF) + +#define MCF5XXX_RD_SF_VECTOR(PTR) \ + ((*((uint16 *)(PTR)) >> 2) & 0x00FF) + +#define MCF5XXX_RD_SF_FS(PTR) \ + ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) + +#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1) +#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1) + +/********************************************************************/ +/* + * Functions provided by mcf5xxx.s + */ + +int asm_set_ipl (uint32); +void mcf5xxx_wr_cacr (uint32); +void mcf5xxx_wr_acr0 (uint32); +void mcf5xxx_wr_acr1 (uint32); +void mcf5xxx_wr_acr2 (uint32); +void mcf5xxx_wr_acr3 (uint32); +void mcf5xxx_wr_other_a7 (uint32); +void mcf5xxx_wr_other_sp (uint32); +void mcf5xxx_wr_vbr (uint32); +void mcf5xxx_wr_macsr (uint32); +void mcf5xxx_wr_mask (uint32); +void mcf5xxx_wr_acc0 (uint32); +void mcf5xxx_wr_accext01 (uint32); +void mcf5xxx_wr_accext23 (uint32); +void mcf5xxx_wr_acc1 (uint32); +void mcf5xxx_wr_acc2 (uint32); +void mcf5xxx_wr_acc3 (uint32); +void mcf5xxx_wr_sr (uint32); +void mcf5xxx_wr_rambar0 (uint32); +void mcf5xxx_wr_rambar1 (uint32); +void mcf5xxx_wr_mbar (uint32); +void mcf5xxx_wr_mbar0 (uint32); +void mcf5xxx_wr_mbar1 (uint32); + +/********************************************************************/ + +#endif /* _CPU_MCF5XXX_H */ + + +/********************************************************************/ +/* + * Memory map definitions from linker command files + */ +extern uint8 __IPSBAR[]; + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_SCM_IPSBAR (*(vuint32 *)(&__IPSBAR[0x0000])) +#define MCF5282_SCM_RAMBAR (*(vuint32 *)(&__IPSBAR[0x0008])) +#define MCF5282_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x0010])) +#define MCF5282_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x0011])) +#define MCF5282_SCM_LPICR (*(vuint8 *)(&__IPSBAR[0x0012])) +#define MCF5282_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x0013])) +#define MCF5282_SCM_DMAREQC (*(vuint32 *)(&__IPSBAR[0x0014])) +#define MCF5282_SCM_MPARK (*(vuint32 *)(&__IPSBAR[0x001C])) +#define MCF5282_SCM_MPR (*(vuint8 *)(&__IPSBAR[0x0020])) +#define MCF5282_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x0024])) +#define MCF5282_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x0025])) +#define MCF5282_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x0026])) +#define MCF5282_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x0027])) +#define MCF5282_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x0028])) +#define MCF5282_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x002A])) +#define MCF5282_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x002B])) +#define MCF5282_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x002C])) +#define MCF5282_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x002E])) +#define MCF5282_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x0030])) +#define MCF5282_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x0031])) + +/* Bit level definitions and macros */ +#define MCF5282_SCM_IPSBAR_BA(x) ((x)&0xC0000000) +#define MCF5282_SCM_IPSBAR_V (0x00000001) + +#define MCF5282_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) +#define MCF5282_SCM_RAMBAR_BDE (0x00000200) + +#define MCF5282_SCM_CRSR_EXT (0x80) +#define MCF5282_SCM_CRSR_CWDR (0x20) + +#define MCF5282_SCM_CWCR_CWE (0x80) +#define MCF5282_SCM_CWCR_CWRI (0x40) +#define MCF5282_SCM_CWCR_CWT(x) (((x)&0x03)<<3) +#define MCF5282_SCM_CWCR_CWTA (0x04) +#define MCF5282_SCM_CWCR_CWTAVAL (0x02) +#define MCF5282_SCM_CWCR_CWTIC (0x01) + +#define MCF5282_SCM_LPICR_ENBSTOP (0x80) +#define MCF5282_SCM_LPICR_XSTOP_IPL(x) (((x)&0x07)<<4) + +#define MCF5282_SCM_CWSR_SEQ1 (0x55) +#define MCF5282_SCM_CWSR_SEQ2 (0xAA) + +#define MCF5282_SCM_DMAREQC_DMAC3(x) (((x)&0x000F)<<12) +#define MCF5282_SCM_DMAREQC_DMAC2(x) (((x)&0x000F)<<8) +#define MCF5282_SCM_DMAREQC_DMAC1(x) (((x)&0x000F)<<4) +#define MCF5282_SCM_DMAREQC_DMAC0(x) (((x)&0x000F)) +#define MCF5282_SCM_DMAREQC_DMATIMER0 (0x4) +#define MCF5282_SCM_DMAREQC_DMATIMER1 (0x5) +#define MCF5282_SCM_DMAREQC_DMATIMER2 (0x6) +#define MCF5282_SCM_DMAREQC_DMATIMER3 (0x7) +#define MCF5282_SCM_DMAREQC_UART0 (0x8) +#define MCF5282_SCM_DMAREQC_UART1 (0x9) +#define MCF5282_SCM_DMAREQC_UART2 (0xA) + +#define MCF5282_SCM_MPARK_M2_P_EN (0x02000000) +#define MCF5282_SCM_MPARK_BCR24BIT (0x01000000) +#define MCF5282_SCM_MPARK_M3_PRTY(x) (((x)&0x03)<<22) +#define MCF5282_SCM_MPARK_M2_PRTY(x) (((x)&0x03)<<20) +#define MCF5282_SCM_MPARK_M0_PRTY(x) (((x)&0x03)<<18) +#define MCF5282_SCM_MPARK_M1_PRTY(x) (((x)&0x03)<<16) +#define MCF5282_SCM_MPARK_FIXED (0x00040000) +#define MCF5282_SCM_MPARK_TIMEOUT (0x00020000) +#define MCF5282_SCM_MPARK_PRK_LAST (0x00010000) +#define MCF5282_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x000F)<<8) + +#define MCF5282_SCM_MPARK_MX_PRTY_FIRST (0x3) +#define MCF5282_SCM_MPARK_MX_PRTY_SECOND (0x2) +#define MCF5282_SCM_MPARK_MX_PRTY_THIRD (0x1) +#define MCF5282_SCM_MPARK_MX_PRTY_FOURTH (0x0) + +#define MCF5282_SCM_MPR_MPR(x) (((x)&0x0F)) + +#define MCF5282_SCM_PACR_LOCK1 (0x80) +#define MCF5282_SCM_PACR_ACCESSCTRL1(x) (((x)&0x07)<<4) +#define MCF5282_SCM_PACR_LOCK0 (0x08) +#define MCF5282_SCM_PACR_ACCESSCTRL0(x) (((x)&0x07)) +#define MCF5282_SCM_PACR_RW_NA (0x0) +#define MCF5282_SCM_PACR_R_NA (0x1) +#define MCF5282_SCM_PACR_R_R (0x2) +#define MCF5282_SCM_PACR_RW_RW (0x4) +#define MCF5282_SCM_PACR_RW_R (0x5) +#define MCF5282_SCM_PACR_NA_NA (0x7) + +#define MCF5282_SCM_GPACR_LOCK (0x80) +#define MCF5282_SCM_GPACR_ACCESSCTRL(x) (((x)&0x0F)) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RW_NA (0x0) +#define MCF5282_SCM_GPACR_ACCESSCTRL_R_NA (0x1) +#define MCF5282_SCM_GPACR_ACCESSCTRL_R_R (0x2) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RW_RW (0x4) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RW_R (0x5) +#define MCF5282_SCM_GPACR_ACCESSCTRL_NA_NA (0x7) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_NA (0x8) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RE_NA (0x9) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RE_RE (0xA) +#define MCF5282_SCM_GPACR_ACCESSCTRL_E_NA (0xB) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_RWE (0xC) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_RE (0xD) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_E (0xF) + +/********************************************************************* +* +* SDRAM Controller Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_SDRAMC_DCR (*(vuint16 *)(&__IPSBAR[0x0040])) +#define MCF5282_SDRAMC_DACR0 (*(vuint32 *)(&__IPSBAR[0x0048])) +#define MCF5282_SDRAMC_DMR0 (*(vuint32 *)(&__IPSBAR[0x004C])) +#define MCF5282_SDRAMC_DACR1 (*(vuint32 *)(&__IPSBAR[0x0050])) +#define MCF5282_SDRAMC_DMR1 (*(vuint32 *)(&__IPSBAR[0x0054])) + +/* Bit level definitions and macros */ +#define MCF5282_SDRAMC_DCR_NAM (0x2000) +#define MCF5282_SDRAMC_DCR_COC (0x1000) +#define MCF5282_SDRAMC_DCR_IS (0x0800) +#define MCF5282_SDRAMC_DCR_RTIM_3 (0x0000) +#define MCF5282_SDRAMC_DCR_RTIM_6 (0x0200) +#define MCF5282_SDRAMC_DCR_RTIM_9 (0x0400) +#define MCF5282_SDRAMC_DCR_RC(x) ((x)&0x01FF) + +#define MCF5282_SDRAMC_DACR_BASE(x) ((x)&0xFFFC0000) +#define MCF5282_SDRAMC_DACR_RE (0x00008000) +#define MCF5282_SDRAMC_DACR_CASL(x) (((x)&0x03)<<12) +#define MCF5282_SDRAMC_DACR_CBM(x) (((x)&0x07)<<8) +#define MCF5282_SDRAMC_DACR_PS_32 (0x00000000) +#define MCF5282_SDRAMC_DACR_PS_8 (0x00000010) +#define MCF5282_SDRAMC_DACR_PS_16 (0x00000020) +#define MCF5282_SDRAMC_DACR_IMRS (0x00000040) +#define MCF5282_SDRAMC_DACR_IP (0x00000008) + +#define MCF5282_SDRAMC_DMR_BAM_4G (0xFFFC0000) +#define MCF5282_SDRAMC_DMR_BAM_2G (0x7FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_1G (0x3FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_1024M (0x3FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_512M (0x1FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_256M (0x0FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_128M (0x07FC0000) +#define MCF5282_SDRAMC_DMR_BAM_64M (0x03FC0000) +#define MCF5282_SDRAMC_DMR_BAM_32M (0x01FC0000) +#define MCF5282_SDRAMC_DMR_BAM_16M (0x00FC0000) +#define MCF5282_SDRAMC_DMR_BAM_8M (0x007C0000) +#define MCF5282_SDRAMC_DMR_BAM_4M (0x003C0000) +#define MCF5282_SDRAMC_DMR_BAM_2M (0x001C0000) +#define MCF5282_SDRAMC_DMR_BAM_1M (0x000C0000) +#define MCF5282_SDRAMC_DMR_BAM_1024K (0x000C0000) +#define MCF5282_SDRAMC_DMR_BAM_512K (0x00040000) +#define MCF5282_SDRAMC_DMR_BAM_256K (0x00000000) +#define MCF5282_SDRAMC_DMR_WP (0x00000100) +#define MCF5282_SDRAMC_DMR_CI (0x00000040) +#define MCF5282_SDRAMC_DMR_AM (0x00000020) +#define MCF5282_SDRAMC_DMR_SC (0x00000010) +#define MCF5282_SDRAMC_DMR_SD (0x00000008) +#define MCF5282_SDRAMC_DMR_UC (0x00000004) +#define MCF5282_SDRAMC_DMR_UD (0x00000002) +#define MCF5282_SDRAMC_DMR_V (0x00000001) + +/********************************************************************* +* +* Chip Select Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_CS0_CSAR (*(vuint16 *)(&__IPSBAR[0x0080])) +#define MCF5282_CS0_CSMR (*(vuint32 *)(&__IPSBAR[0x0084])) +#define MCF5282_CS0_CSCR (*(vuint16 *)(&__IPSBAR[0x008A])) + +#define MCF5282_CS1_CSAR (*(vuint16 *)(&__IPSBAR[0x008C])) +#define MCF5282_CS1_CSMR (*(vuint32 *)(&__IPSBAR[0x0090])) +#define MCF5282_CS1_CSCR (*(vuint16 *)(&__IPSBAR[0x0096])) + +#define MCF5282_CS2_CSAR (*(vuint16 *)(&__IPSBAR[0x0098])) +#define MCF5282_CS2_CSMR (*(vuint32 *)(&__IPSBAR[0x009C])) +#define MCF5282_CS2_CSCR (*(vuint16 *)(&__IPSBAR[0x00A2])) + +#define MCF5282_CS3_CSAR (*(vuint16 *)(&__IPSBAR[0x00A4])) +#define MCF5282_CS3_CSMR (*(vuint32 *)(&__IPSBAR[0x00A8])) +#define MCF5282_CS3_CSCR (*(vuint16 *)(&__IPSBAR[0x00AE])) + +#define MCF5282_CS4_CSAR (*(vuint16 *)(&__IPSBAR[0x00B0])) +#define MCF5282_CS4_CSMR (*(vuint32 *)(&__IPSBAR[0x00B4])) +#define MCF5282_CS4_CSCR (*(vuint16 *)(&__IPSBAR[0x00BA])) + +#define MCF5282_CS5_CSAR (*(vuint16 *)(&__IPSBAR[0x00BC])) +#define MCF5282_CS5_CSMR (*(vuint32 *)(&__IPSBAR[0x00C0])) +#define MCF5282_CS5_CSCR (*(vuint16 *)(&__IPSBAR[0x00C6])) + +#define MCF5282_CS6_CSAR (*(vuint16 *)(&__IPSBAR[0x00C8])) +#define MCF5282_CS6_CSMR (*(vuint32 *)(&__IPSBAR[0x00CC])) +#define MCF5282_CS6_CSCR (*(vuint16 *)(&__IPSBAR[0x00D2])) + +#define MCF5282_CS_CSAR(x) (*(vuint16 *)(&__IPSBAR[0x0080+((x)*0x0C)])) +#define MCF5282_CS_CSMR(x) (*(vuint32 *)(&__IPSBAR[0x0084+((x)*0x0C)])) +#define MCF5282_CS_CSCR(x) (*(vuint16 *)(&__IPSBAR[0x008A+((x)*0x0C)])) + +/* Bit level definitions and macros */ +#define MCF5282_CS_CSAR_BA(a) (uint16)(((a)&0xFFFF0000)>>16) + +#define MCF5282_CS_CSMR_BAM_4G (0xFFFF0000) +#define MCF5282_CS_CSMR_BAM_2G (0x7FFF0000) +#define MCF5282_CS_CSMR_BAM_1G (0x3FFF0000) +#define MCF5282_CS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF5282_CS_CSMR_BAM_512M (0x1FFF0000) +#define MCF5282_CS_CSMR_BAM_256M (0x0FFF0000) +#define MCF5282_CS_CSMR_BAM_128M (0x07FF0000) +#define MCF5282_CS_CSMR_BAM_64M (0x03FF0000) +#define MCF5282_CS_CSMR_BAM_32M (0x01FF0000) +#define MCF5282_CS_CSMR_BAM_16M (0x00FF0000) +#define MCF5282_CS_CSMR_BAM_8M (0x007F0000) +#define MCF5282_CS_CSMR_BAM_4M (0x003F0000) +#define MCF5282_CS_CSMR_BAM_2M (0x001F0000) +#define MCF5282_CS_CSMR_BAM_1M (0x000F0000) +#define MCF5282_CS_CSMR_BAM_1024K (0x000F0000) +#define MCF5282_CS_CSMR_BAM_512K (0x00070000) +#define MCF5282_CS_CSMR_BAM_256K (0x00030000) +#define MCF5282_CS_CSMR_BAM_128K (0x00010000) +#define MCF5282_CS_CSMR_BAM_64K (0x00000000) +#define MCF5282_CS_CSMR_WP (0x00000100) +#define MCF5282_CS_CSMR_AM (0x00000040) +#define MCF5282_CS_CSMR_CI (0x00000020) +#define MCF5282_CS_CSMR_SC (0x00000010) +#define MCF5282_CS_CSMR_SD (0x00000008) +#define MCF5282_CS_CSMR_UC (0x00000004) +#define MCF5282_CS_CSMR_UD (0x00000002) +#define MCF5282_CS_CSMR_V (0x00000001) + +#define MCF5282_CS_CSCR_WS(x) (((x)&0x0F)<<10) +#define MCF5282_CS_CSCR_AA (0x0100) +#define MCF5282_CS_CSCR_PS_8 (0x0040) +#define MCF5282_CS_CSCR_PS_16 (0x0080) +#define MCF5282_CS_CSCR_PS_32 (0x0000) +#define MCF5282_CS_CSCR_BEM (0x0020) +#define MCF5282_CS_CSCR_BSTR (0x0010) +#define MCF5282_CS_CSCR_BSTW (0x0008) + +/********************************************************************* +* +* Direct Memory Access (DMA) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_DMA0_SAR (*(vuint32 *)(&__IPSBAR[0x0100])) +#define MCF5282_DMA0_DAR (*(vuint32 *)(&__IPSBAR[0x0104])) +#define MCF5282_DMA0_DCR (*(vuint32 *)(&__IPSBAR[0x0108])) +#define MCF5282_DMA0_BCR (*(vuint32 *)(&__IPSBAR[0x010C])) +#define MCF5282_DMA0_DSR (*(vuint8 *)(&__IPSBAR[0x0110])) + +#define MCF5282_DMA1_SAR (*(vuint32 *)(&__IPSBAR[0x0140])) +#define MCF5282_DMA1_DAR (*(vuint32 *)(&__IPSBAR[0x0144])) +#define MCF5282_DMA1_DCR (*(vuint32 *)(&__IPSBAR[0x0148])) +#define MCF5282_DMA1_BCR (*(vuint32 *)(&__IPSBAR[0x014C])) +#define MCF5282_DMA1_DSR (*(vuint8 *)(&__IPSBAR[0x0150])) + +#define MCF5282_DMA2_SAR (*(vuint32 *)(&__IPSBAR[0x0180])) +#define MCF5282_DMA2_DAR (*(vuint32 *)(&__IPSBAR[0x0184])) +#define MCF5282_DMA2_DCR (*(vuint32 *)(&__IPSBAR[0x0188])) +#define MCF5282_DMA2_BCR (*(vuint32 *)(&__IPSBAR[0x018C])) +#define MCF5282_DMA2_DSR (*(vuint8 *)(&__IPSBAR[0x0190])) + +#define MCF5282_DMA3_SAR (*(vuint32 *)(&__IPSBAR[0x01C0])) +#define MCF5282_DMA3_DAR (*(vuint32 *)(&__IPSBAR[0x01C4])) +#define MCF5282_DMA3_DCR (*(vuint32 *)(&__IPSBAR[0x01C8])) +#define MCF5282_DMA3_BCR (*(vuint32 *)(&__IPSBAR[0x01CC])) +#define MCF5282_DMA3_DSR (*(vuint8 *)(&__IPSBAR[0x01D0])) + +#define MCF5282_DMA_SAR(x) (*(vuint32 *)(&__IPSBAR[0x0100+((x)*0x40)])) +#define MCF5282_DMA_DAR(x) (*(vuint32 *)(&__IPSBAR[0x0104+((x)*0x40)])) +#define MCF5282_DMA_DCR(x) (*(vuint32 *)(&__IPSBAR[0x0108+((x)*0x40)])) +#define MCF5282_DMA_BCR(x) (*(vuint32 *)(&__IPSBAR[0x010C+((x)*0x40)])) +#define MCF5282_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x0110+((x)*0x40)])) + +/* Bit level definitions and macros */ +#define MCF5282_DMA_DCR_INT (0x80000000) +#define MCF5282_DMA_DCR_EEXT (0x40000000) +#define MCF5282_DMA_DCR_CS (0x20000000) +#define MCF5282_DMA_DCR_AA (0x10000000) +#define MCF5282_DMA_DCR_BWC_DMA (0x00000000) +#define MCF5282_DMA_DCR_BWC_512 (0x02000000) +#define MCF5282_DMA_DCR_BWC_1024 (0x04000000) +#define MCF5282_DMA_DCR_BWC_2048 (0x06000000) +#define MCF5282_DMA_DCR_BWC_4096 (0x08000000) +#define MCF5282_DMA_DCR_BWC_8192 (0x0A000000) +#define MCF5282_DMA_DCR_BWC_16384 (0x0C000000) +#define MCF5282_DMA_DCR_BWC_32768 (0x0E000000) +#define MCF5282_DMA_DCR_SINC (0x00400000) +#define MCF5282_DMA_DCR_SSIZE_LONG (0x00000000) +#define MCF5282_DMA_DCR_SSIZE_BYTE (0x00100000) +#define MCF5282_DMA_DCR_SSIZE_WORD (0x00200000) +#define MCF5282_DMA_DCR_SSIZE_LINE (0x00300000) +#define MCF5282_DMA_DCR_DINC (0x00080000) +#define MCF5282_DMA_DCR_DSIZE_LONG (0x00000000) +#define MCF5282_DMA_DCR_DSIZE_BYTE (0x00020000) +#define MCF5282_DMA_DCR_DSIZE_WORD (0x00040000) +#define MCF5282_DMA_DCR_START (0x00010000) +#define MCF5282_DMA_DCR_AT (0x00008000) + +#define MCF5282_DMA_DSR_CE (0x40) +#define MCF5282_DMA_DSR_BES (0x20) +#define MCF5282_DMA_DSR_BED (0x10) +#define MCF5282_DMA_DSR_REQ (0x04) +#define MCF5282_DMA_DSR_BSY (0x02) +#define MCF5282_DMA_DSR_DONE (0x01) + +/********************************************************************* +* +* Universal Asychronous Receiver/Transmitter (UART) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_UART0_UMR (*(vuint8 *)(&__IPSBAR[0x0200])) +#define MCF5282_UART0_USR (*(vuint8 *)(&__IPSBAR[0x0204])) +#define MCF5282_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x0204])) +#define MCF5282_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x0208])) +#define MCF5282_UART0_URB (*(vuint8 *)(&__IPSBAR[0x020C])) +#define MCF5282_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x020C])) +#define MCF5282_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x0210])) +#define MCF5282_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x0210])) +#define MCF5282_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x0214])) +#define MCF5282_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x0214])) +#define MCF5282_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x0218])) +#define MCF5282_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x021C])) +#define MCF5282_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x0234])) +#define MCF5282_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x0238])) +#define MCF5282_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x023C])) + +#define MCF5282_UART1_UMR (*(vuint8 *)(&__IPSBAR[0x0240])) +#define MCF5282_UART1_USR (*(vuint8 *)(&__IPSBAR[0x0244])) +#define MCF5282_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x0244])) +#define MCF5282_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x0248])) +#define MCF5282_UART1_URB (*(vuint8 *)(&__IPSBAR[0x024C])) +#define MCF5282_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x024C])) +#define MCF5282_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x0250])) +#define MCF5282_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x0250])) +#define MCF5282_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x0254])) +#define MCF5282_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x0254])) +#define MCF5282_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x0258])) +#define MCF5282_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x025C])) +#define MCF5282_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x0274])) +#define MCF5282_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x0278])) +#define MCF5282_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x027C])) + +#define MCF5282_UART2_UMR (*(vuint8 *)(&__IPSBAR[0x0280])) +#define MCF5282_UART2_USR (*(vuint8 *)(&__IPSBAR[0x0284])) +#define MCF5282_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x0284])) +#define MCF5282_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x0288])) +#define MCF5282_UART2_URB (*(vuint8 *)(&__IPSBAR[0x028C])) +#define MCF5282_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x028C])) +#define MCF5282_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x0290])) +#define MCF5282_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x0290])) +#define MCF5282_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x0294])) +#define MCF5282_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x0294])) +#define MCF5282_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x0298])) +#define MCF5282_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x029C])) +#define MCF5282_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x02B4])) +#define MCF5282_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x02B8])) +#define MCF5282_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x02BC])) + +#define MCF5282_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x0200+((x)*0x40)])) +#define MCF5282_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x0204+((x)*0x40)])) +#define MCF5282_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x0204+((x)*0x40)])) +#define MCF5282_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x0208+((x)*0x40)])) +#define MCF5282_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x020C+((x)*0x40)])) +#define MCF5282_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x020C+((x)*0x40)])) +#define MCF5282_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x0210+((x)*0x40)])) +#define MCF5282_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x0210+((x)*0x40)])) +#define MCF5282_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x0214+((x)*0x40)])) +#define MCF5282_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x0214+((x)*0x40)])) +#define MCF5282_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x0218+((x)*0x40)])) +#define MCF5282_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x021C+((x)*0x40)])) +#define MCF5282_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x0234+((x)*0x40)])) +#define MCF5282_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x0238+((x)*0x40)])) +#define MCF5282_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x023C+((x)*0x40)])) + +/* Bit level definitions and macros */ +#define MCF5282_UART_UMR1_RXRTS (0x80) +#define MCF5282_UART_UMR1_RXIRQ (0x40) +#define MCF5282_UART_UMR1_ERR (0x20) +#define MCF5282_UART_UMR1_PM_MULTI_ADDR (0x1C) +#define MCF5282_UART_UMR1_PM_MULTI_DATA (0x18) +#define MCF5282_UART_UMR1_PM_NONE (0x10) +#define MCF5282_UART_UMR1_PM_FORCE_HI (0x0C) +#define MCF5282_UART_UMR1_PM_FORCE_LO (0x08) +#define MCF5282_UART_UMR1_PM_ODD (0x04) +#define MCF5282_UART_UMR1_PM_EVEN (0x00) +#define MCF5282_UART_UMR1_BC_5 (0x00) +#define MCF5282_UART_UMR1_BC_6 (0x01) +#define MCF5282_UART_UMR1_BC_7 (0x02) +#define MCF5282_UART_UMR1_BC_8 (0x03) + +#define MCF5282_UART_UMR2_CM_NORMAL (0x00) +#define MCF5282_UART_UMR2_CM_ECHO (0x40) +#define MCF5282_UART_UMR2_CM_LOCAL_LOOP (0x80) +#define MCF5282_UART_UMR2_CM_REMOTE_LOOP (0xC0) +#define MCF5282_UART_UMR2_TXRTS (0x20) +#define MCF5282_UART_UMR2_TXCTS (0x10) +#define MCF5282_UART_UMR2_STOP_BITS_1 (0x07) +#define MCF5282_UART_UMR2_STOP_BITS_15 (0x08) +#define MCF5282_UART_UMR2_STOP_BITS_2 (0x0F) +#define MCF5282_UART_UMR2_STOP_BITS(a) ((a)&0x0f) + +#define MCF5282_UART_USR_RB (0x80) +#define MCF5282_UART_USR_FE (0x40) +#define MCF5282_UART_USR_PE (0x20) +#define MCF5282_UART_USR_OE (0x10) +#define MCF5282_UART_USR_TXEMP (0x08) +#define MCF5282_UART_USR_TXRDY (0x04) +#define MCF5282_UART_USR_FFULL (0x02) +#define MCF5282_UART_USR_RXRDY (0x01) + +#define MCF5282_UART_UCSR_RCS_SYS_CLK (0xD0) +#define MCF5282_UART_UCSR_RCS_DTIN16 (0xE0) +#define MCF5282_UART_UCSR_RCS_DTIN (0xF0) +#define MCF5282_UART_UCSR_TCS_SYS_CLK (0x0D) +#define MCF5282_UART_UCSR_TCS_DTIN16 (0x0E) +#define MCF5282_UART_UCSR_TCS_DTIN (0x0F) + +#define MCF5282_UART_UCR_NONE (0x00) +#define MCF5282_UART_UCR_STOP_BREAK (0x70) +#define MCF5282_UART_UCR_START_BREAK (0x60) +#define MCF5282_UART_UCR_RESET_BKCHGINT (0x50) +#define MCF5282_UART_UCR_RESET_ERROR (0x40) +#define MCF5282_UART_UCR_RESET_TX (0x30) +#define MCF5282_UART_UCR_RESET_RX (0x20) +#define MCF5282_UART_UCR_RESET_MR (0x10) +#define MCF5282_UART_UCR_TX_DISABLED (0x08) +#define MCF5282_UART_UCR_TX_ENABLED (0x04) +#define MCF5282_UART_UCR_RX_DISABLED (0x02) +#define MCF5282_UART_UCR_RX_ENABLED (0x01) + +#define MCF5282_UART_UIPCR_COS (0x10) +#define MCF5282_UART_UIPCR_CTS (0x01) + +#define MCF5282_UART_UACR_IEC (0x01) + +#define MCF5282_UART_UISR_COS (0x80) +#define MCF5282_UART_UISR_ABC (0x40) +#define MCF5282_UART_UISR_RXFIFO (0x20) +#define MCF5282_UART_UISR_TXFIFO (0x10) +#define MCF5282_UART_UISR_RXFTO (0x08) +#define MCF5282_UART_UISR_DB (0x04) +#define MCF5282_UART_UISR_RXRDY (0x02) +#define MCF5282_UART_UISR_TXRDY (0x01) + +#define MCF5282_UART_UIMR_COS (0x80) +#define MCF5282_UART_UIMR_DB (0x04) +#define MCF5282_UART_UIMR_FFULL (0x02) +#define MCF5282_UART_UIMR_TXRDY (0x01) + +#define MCF5282_UART_UIP_CTS (0x01) + +#define MCF5282_UART_UOP_RTS (0x01) + +/********************************************************************* +* +* Inter-IC (I2C) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_I2C_I2ADR (*(vuint8 *)(&__IPSBAR[0x0300])) +#define MCF5282_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x0304])) +#define MCF5282_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x0308])) +#define MCF5282_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x030C])) +#define MCF5282_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x0310])) + +/* Bit level definitions and macros */ +#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) + +#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F)) + +#define MCF5282_I2C_I2CR_IEN (0x80) +#define MCF5282_I2C_I2CR_IIEN (0x40) +#define MCF5282_I2C_I2CR_MSTA (0x20) +#define MCF5282_I2C_I2CR_MTX (0x10) +#define MCF5282_I2C_I2CR_TXAK (0x08) +#define MCF5282_I2C_I2CR_RSTA (0x04) + +#define MCF5282_I2C_I2SR_ICF (0x80) +#define MCF5282_I2C_I2SR_IAAS (0x40) +#define MCF5282_I2C_I2SR_IBB (0x20) +#define MCF5282_I2C_I2SR_IAL (0x10) +#define MCF5282_I2C_I2SR_SRW (0x04) +#define MCF5282_I2C_I2SR_IIF (0x02) +#define MCF5282_I2C_I2SR_RXAK (0x01) + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_QSPI_QMR (*(vuint16 *)(&__IPSBAR[0x0340])) +#define MCF5282_QSPI_QDLYR (*(vuint16 *)(&__IPSBAR[0x0344])) +#define MCF5282_QSPI_QWR (*(vuint16 *)(&__IPSBAR[0x0348])) +#define MCF5282_QSPI_QIR (*(vuint16 *)(&__IPSBAR[0x034C])) +#define MCF5282_QSPI_QAR (*(vuint16 *)(&__IPSBAR[0x0350])) +#define MCF5282_QSPI_QDR (*(vuint16 *)(&__IPSBAR[0x0354])) +#define MCF5282_QSPI_QCR (*(vuint16 *)(&__IPSBAR[0x0354])) + +/* Bit level definitions and macros */ +#define MCF5282_QSPI_QMR_MSTR (0x8000) +#define MCF5282_QSPI_QMR_DOHIE (0x4000) +#define MCF5282_QSPI_QMR_BITS_16 (0x0000) +#define MCF5282_QSPI_QMR_BITS_8 (0x2000) +#define MCF5282_QSPI_QMR_BITS_9 (0x2400) +#define MCF5282_QSPI_QMR_BITS_10 (0x2800) +#define MCF5282_QSPI_QMR_BITS_11 (0x2C00) +#define MCF5282_QSPI_QMR_BITS_12 (0x3000) +#define MCF5282_QSPI_QMR_BITS_13 (0x3400) +#define MCF5282_QSPI_QMR_BITS_14 (0x3800) +#define MCF5282_QSPI_QMR_BITS_15 (0x3C00) +#define MCF5282_QSPI_QMR_CPOL (0x0200) +#define MCF5282_QSPI_QMR_CPHA (0x0100) +#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF)) + +#define MCF5282_QSPI_QDLYR_SPE (0x8000) +#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF)) + +#define MCF5282_QSPI_QWR_HALT (0x8000) +#define MCF5282_QSPI_QWR_WREN (0x4000) +#define MCF5282_QSPI_QWR_WRTO (0x2000) +#define MCF5282_QSPI_QWR_CSIV (0x1000) +#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4) +#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F)) + +#define MCF5282_QSPI_QIR_WCEFB (0x8000) +#define MCF5282_QSPI_QIR_ABRTB (0x4000) +#define MCF5282_QSPI_QIR_ABRTL (0x1000) +#define MCF5282_QSPI_QIR_WCEFE (0x0800) +#define MCF5282_QSPI_QIR_ABRTE (0x0400) +#define MCF5282_QSPI_QIR_SPIFE (0x0100) +#define MCF5282_QSPI_QIR_WCEF (0x0008) +#define MCF5282_QSPI_QIR_ABRT (0x0004) +#define MCF5282_QSPI_QIR_SPIF (0x0001) + +#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F)) + +#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00)) + +#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8) +#define MCF5282_QSPI_QCR_CONT (0x8000) +#define MCF5282_QSPI_QCR_BITSE (0x4000) +#define MCF5282_QSPI_QCR_DT (0x2000) +#define MCF5282_QSPI_QCR_DSCK (0x1000) +#define MCF5282_QSPI_QCR_CS(x) (((x)&0x000F)<<8) + +/********************************************************************* +* +* DMA Timer Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_TIMER0_DTMR (*(vuint16 *)(&__IPSBAR[0x0400])) +#define MCF5282_TIMER0_DTXMR (*(vuint8 *)(&__IPSBAR[0x0402])) +#define MCF5282_TIMER0_DTER (*(vuint8 *)(&__IPSBAR[0x0403])) +#define MCF5282_TIMER0_DTRR (*(vuint32 *)(&__IPSBAR[0x0404])) +#define MCF5282_TIMER0_DTCR (*(vuint32 *)(&__IPSBAR[0x0408])) +#define MCF5282_TIMER0_DTCN (*(vuint32 *)(&__IPSBAR[0x040C])) + +#define MCF5282_TIMER1_DTMR (*(vuint16 *)(&__IPSBAR[0x0440])) +#define MCF5282_TIMER1_DTXMR (*(vuint8 *)(&__IPSBAR[0x0442])) +#define MCF5282_TIMER1_DTER (*(vuint8 *)(&__IPSBAR[0x0443])) +#define MCF5282_TIMER1_DTRR (*(vuint32 *)(&__IPSBAR[0x0444])) +#define MCF5282_TIMER1_DTCR (*(vuint32 *)(&__IPSBAR[0x0448])) +#define MCF5282_TIMER1_DTCN (*(vuint32 *)(&__IPSBAR[0x044C])) + +#define MCF5282_TIMER2_DTMR (*(vuint16 *)(&__IPSBAR[0x0480])) +#define MCF5282_TIMER2_DTXMR (*(vuint8 *)(&__IPSBAR[0x0482])) +#define MCF5282_TIMER2_DTER (*(vuint8 *)(&__IPSBAR[0x0483])) +#define MCF5282_TIMER2_DTRR (*(vuint32 *)(&__IPSBAR[0x0484])) +#define MCF5282_TIMER2_DTCR (*(vuint32 *)(&__IPSBAR[0x0488])) +#define MCF5282_TIMER2_DTCN (*(vuint32 *)(&__IPSBAR[0x048C])) + +#define MCF5282_TIMER3_DTMR (*(vuint16 *)(&__IPSBAR[0x04C0])) +#define MCF5282_TIMER3_DTXMR (*(vuint8 *)(&__IPSBAR[0x04C2])) +#define MCF5282_TIMER3_DTER (*(vuint8 *)(&__IPSBAR[0x04C3])) +#define MCF5282_TIMER3_DTRR (*(vuint32 *)(&__IPSBAR[0x04C4])) +#define MCF5282_TIMER3_DTCR (*(vuint32 *)(&__IPSBAR[0x04C8])) +#define MCF5282_TIMER3_DTCN (*(vuint32 *)(&__IPSBAR[0x04CC])) + +#define MCF5282_TIMER_DTMR(x) (*(vuint16 *)(&__IPSBAR[0x0400+((x)*0x40)])) +#define MCF5282_TIMER_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x0402+((x)*0x40)])) +#define MCF5282_TIMER_DTER(x) (*(vuint8 *)(&__IPSBAR[0x0403+((x)*0x40)])) +#define MCF5282_TIMER_DTRR(x) (*(vuint32 *)(&__IPSBAR[0x0404+((x)*0x40)])) +#define MCF5282_TIMER_DTCR(x) (*(vuint32 *)(&__IPSBAR[0x0408+((x)*0x40)])) +#define MCF5282_TIMER_DTCN(x) (*(vuint32 *)(&__IPSBAR[0x040C+((x)*0x40)])) + +/* Bit level definitions and macros */ +#define MCF5282_TIMER_DTMR_PS(a) (((a)&0x00FF)<<8) +#define MCF5282_TIMER_DTMR_CE_ANY (0x00C0) +#define MCF5282_TIMER_DTMR_CE_FALL (0x0080) +#define MCF5282_TIMER_DTMR_CE_RISE (0x0040) +#define MCF5282_TIMER_DTMR_CE_NONE (0x0000) +#define MCF5282_TIMER_DTMR_OM (0x0020) +#define MCF5282_TIMER_DTMR_ORRI (0x0010) +#define MCF5282_TIMER_DTMR_FRR (0x0008) +#define MCF5282_TIMER_DTMR_CLK_DTIN (0x0006) +#define MCF5282_TIMER_DTMR_CLK_DIV16 (0x0004) +#define MCF5282_TIMER_DTMR_CLK_DIV1 (0x0002) +#define MCF5282_TIMER_DTMR_CLK_STOP (0x0000) +#define MCF5282_TIMER_DTMR_RST (0x0001) + +#define MCF5282_TIMER_DTXMR_DMAEN (0x80) +#define MCF5282_TIMER_DTXMR_MODE16 (0x01) + +#define MCF5282_TIMER_DTER_REF (0x02) +#define MCF5282_TIMER_DTER_CAP (0x01) + +/********************************************************************* +* +* Interrupt Controller (INTC) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_INTC0_IPRH (*(vuint32 *)(&__IPSBAR[0x0C00])) +#define MCF5282_INTC0_IPRL (*(vuint32 *)(&__IPSBAR[0x0C04])) +#define MCF5282_INTC0_IMRH (*(vuint32 *)(&__IPSBAR[0x0C08])) +#define MCF5282_INTC0_IMRL (*(vuint32 *)(&__IPSBAR[0x0C0C])) +#define MCF5282_INTC0_INTFRCH (*(vuint32 *)(&__IPSBAR[0x0C10])) +#define MCF5282_INTC0_INTFRCL (*(vuint32 *)(&__IPSBAR[0x0C14])) +#define MCF5282_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0x0C18])) +#define MCF5282_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0x0C19])) +#define MCF5282_INTC0_ICR1 (*(vuint8 *)(&__IPSBAR[0x0C41])) +#define MCF5282_INTC0_ICR2 (*(vuint8 *)(&__IPSBAR[0x0C42])) +#define MCF5282_INTC0_ICR3 (*(vuint8 *)(&__IPSBAR[0x0C43])) +#define MCF5282_INTC0_ICR4 (*(vuint8 *)(&__IPSBAR[0x0C44])) +#define MCF5282_INTC0_ICR5 (*(vuint8 *)(&__IPSBAR[0x0C45])) +#define MCF5282_INTC0_ICR6 (*(vuint8 *)(&__IPSBAR[0x0C46])) +#define MCF5282_INTC0_ICR7 (*(vuint8 *)(&__IPSBAR[0x0C47])) +#define MCF5282_INTC0_ICR8 (*(vuint8 *)(&__IPSBAR[0x0C48])) +#define MCF5282_INTC0_ICR9 (*(vuint8 *)(&__IPSBAR[0x0C49])) +#define MCF5282_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0x0C4A])) +#define MCF5282_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0x0C4B])) +#define MCF5282_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0x0C4C])) +#define MCF5282_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0x0C4D])) +#define MCF5282_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0x0C4E])) +#define MCF5282_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0x0C4F])) +#define MCF5282_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0x0C51])) +#define MCF5282_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0x0C52])) +#define MCF5282_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0x0C53])) +#define MCF5282_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0x0C54])) +#define MCF5282_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0x0C55])) +#define MCF5282_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0x0C56])) +#define MCF5282_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0x0C57])) +#define MCF5282_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0x0C58])) +#define MCF5282_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0x0C59])) +#define MCF5282_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0x0C5A])) +#define MCF5282_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0x0C5B])) +#define MCF5282_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0x0C5C])) +#define MCF5282_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0x0C5D])) +#define MCF5282_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0x0C5E])) +#define MCF5282_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0x0C5F])) +#define MCF5282_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0x0C60])) +#define MCF5282_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0x0C61])) +#define MCF5282_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0x0C62])) +#define MCF5282_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0x0C63])) +#define MCF5282_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0x0C64])) +#define MCF5282_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0x0C65])) +#define MCF5282_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0x0C66])) +#define MCF5282_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0x0C67])) +#define MCF5282_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0x0C68])) +#define MCF5282_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0x0C69])) +#define MCF5282_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0x0C6A])) +#define MCF5282_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0x0C6B])) +#define MCF5282_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0x0C6C])) +#define MCF5282_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0x0C6D])) +#define MCF5282_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0x0C6E])) +#define MCF5282_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0x0C6F])) +#define MCF5282_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0x0C70])) +#define MCF5282_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0x0C71])) +#define MCF5282_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0x0C72])) +#define MCF5282_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0x0C73])) +#define MCF5282_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0x0C74])) +#define MCF5282_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0x0C75])) +#define MCF5282_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0x0C76])) +#define MCF5282_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0x0C77])) +#define MCF5282_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0x0C78])) +#define MCF5282_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0x0C79])) +#define MCF5282_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0x0C7A])) +#define MCF5282_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0x0C7B])) +#define MCF5282_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0x0C7C])) +#define MCF5282_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0x0C7D])) +#define MCF5282_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0x0C7E])) +#define MCF5282_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0x0CE0])) +#define MCF5282_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0x0CE4])) +#define MCF5282_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0x0CE8])) +#define MCF5282_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0x0CEC])) +#define MCF5282_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0x0CF0])) +#define MCF5282_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0x0CF4])) +#define MCF5282_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0x0CF8])) +#define MCF5282_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0x0CFC])) + +#define MCF5282_INTC1_IPRH (*(vuint32 *)(&__IPSBAR[0x0D00])) +#define MCF5282_INTC1_IPRL (*(vuint32 *)(&__IPSBAR[0x0D04])) +#define MCF5282_INTC1_IMRH (*(vuint32 *)(&__IPSBAR[0x0D08])) +#define MCF5282_INTC1_IMRL (*(vuint32 *)(&__IPSBAR[0x0D0C])) +#define MCF5282_INTC1_INTFRCH (*(vuint32 *)(&__IPSBAR[0x0D10])) +#define MCF5282_INTC1_INTFRCL (*(vuint32 *)(&__IPSBAR[0x0D14])) +#define MCF5282_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0x0D18])) +#define MCF5282_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0x0D19])) +#define MCF5282_INTC1_ICR08 (*(vuint8 *)(&__IPSBAR[0x0D48])) +#define MCF5282_INTC1_ICR09 (*(vuint8 *)(&__IPSBAR[0x0D49])) +#define MCF5282_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0x0D4A])) +#define MCF5282_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0x0D4B])) +#define MCF5282_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0x0D4C])) +#define MCF5282_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0x0D4D])) +#define MCF5282_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0x0D4E])) +#define MCF5282_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0x0D4F])) +#define MCF5282_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0x0D50])) +#define MCF5282_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0x0D51])) +#define MCF5282_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0x0D52])) +#define MCF5282_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0x0D53])) +#define MCF5282_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0x0D54])) +#define MCF5282_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0x0D55])) +#define MCF5282_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0x0D56])) +#define MCF5282_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0x0D57])) +#define MCF5282_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0x0D58])) +#define MCF5282_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0x0D59])) +#define MCF5282_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0x0D5A])) +#define MCF5282_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0x0DE0])) +#define MCF5282_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0x0DE4])) +#define MCF5282_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0x0DE8])) +#define MCF5282_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0x0DEC])) +#define MCF5282_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0x0DF0])) +#define MCF5282_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0x0DF4])) +#define MCF5282_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0x0DF8])) +#define MCF5282_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0x0DFC])) + +/* Bit level definitions and macros */ +#define MCF5282_INTC_IPRH_INT63 (0x80000000) +#define MCF5282_INTC_IPRH_INT62 (0x40000000) +#define MCF5282_INTC_IPRH_INT61 (0x20000000) +#define MCF5282_INTC_IPRH_INT60 (0x10000000) +#define MCF5282_INTC_IPRH_INT59 (0x08000000) +#define MCF5282_INTC_IPRH_INT58 (0x04000000) +#define MCF5282_INTC_IPRH_INT57 (0x02000000) +#define MCF5282_INTC_IPRH_INT56 (0x01000000) +#define MCF5282_INTC_IPRH_INT55 (0x00800000) +#define MCF5282_INTC_IPRH_INT54 (0x00400000) +#define MCF5282_INTC_IPRH_INT53 (0x00200000) +#define MCF5282_INTC_IPRH_INT52 (0x00100000) +#define MCF5282_INTC_IPRH_INT51 (0x00080000) +#define MCF5282_INTC_IPRH_INT50 (0x00040000) +#define MCF5282_INTC_IPRH_INT49 (0x00020000) +#define MCF5282_INTC_IPRH_INT48 (0x00010000) +#define MCF5282_INTC_IPRH_INT47 (0x00008000) +#define MCF5282_INTC_IPRH_INT46 (0x00004000) +#define MCF5282_INTC_IPRH_INT45 (0x00002000) +#define MCF5282_INTC_IPRH_INT44 (0x00001000) +#define MCF5282_INTC_IPRH_INT43 (0x00000800) +#define MCF5282_INTC_IPRH_INT42 (0x00000400) +#define MCF5282_INTC_IPRH_INT41 (0x00000200) +#define MCF5282_INTC_IPRH_INT40 (0x00000100) +#define MCF5282_INTC_IPRH_INT39 (0x00000080) +#define MCF5282_INTC_IPRH_INT38 (0x00000040) +#define MCF5282_INTC_IPRH_INT37 (0x00000020) +#define MCF5282_INTC_IPRH_INT36 (0x00000010) +#define MCF5282_INTC_IPRH_INT35 (0x00000008) +#define MCF5282_INTC_IPRH_INT34 (0x00000004) +#define MCF5282_INTC_IPRH_INT33 (0x00000002) +#define MCF5282_INTC_IPRH_INT32 (0x00000001) + +#define MCF5282_INTC_IPRL_INT31 (0x80000000) +#define MCF5282_INTC_IPRL_INT30 (0x40000000) +#define MCF5282_INTC_IPRL_INT29 (0x20000000) +#define MCF5282_INTC_IPRL_INT28 (0x10000000) +#define MCF5282_INTC_IPRL_INT27 (0x08000000) +#define MCF5282_INTC_IPRL_INT26 (0x04000000) +#define MCF5282_INTC_IPRL_INT25 (0x02000000) +#define MCF5282_INTC_IPRL_INT24 (0x01000000) +#define MCF5282_INTC_IPRL_INT23 (0x00800000) +#define MCF5282_INTC_IPRL_INT22 (0x00400000) +#define MCF5282_INTC_IPRL_INT21 (0x00200000) +#define MCF5282_INTC_IPRL_INT20 (0x00100000) +#define MCF5282_INTC_IPRL_INT19 (0x00080000) +#define MCF5282_INTC_IPRL_INT18 (0x00040000) +#define MCF5282_INTC_IPRL_INT17 (0x00020000) +#define MCF5282_INTC_IPRL_INT16 (0x00010000) +#define MCF5282_INTC_IPRL_INT15 (0x00008000) +#define MCF5282_INTC_IPRL_INT14 (0x00004000) +#define MCF5282_INTC_IPRL_INT13 (0x00002000) +#define MCF5282_INTC_IPRL_INT12 (0x00001000) +#define MCF5282_INTC_IPRL_INT11 (0x00000800) +#define MCF5282_INTC_IPRL_INT10 (0x00000400) +#define MCF5282_INTC_IPRL_INT9 (0x00000200) +#define MCF5282_INTC_IPRL_INT8 (0x00000100) +#define MCF5282_INTC_IPRL_INT7 (0x00000080) +#define MCF5282_INTC_IPRL_INT6 (0x00000040) +#define MCF5282_INTC_IPRL_INT5 (0x00000020) +#define MCF5282_INTC_IPRL_INT4 (0x00000010) +#define MCF5282_INTC_IPRL_INT3 (0x00000008) +#define MCF5282_INTC_IPRL_INT2 (0x00000004) +#define MCF5282_INTC_IPRL_INT1 (0x00000002) + +#define MCF5282_INTC_IMRH_INT63 (0x80000000) +#define MCF5282_INTC_IMRH_INT62 (0x40000000) +#define MCF5282_INTC_IMRH_INT61 (0x20000000) +#define MCF5282_INTC_IMRH_INT60 (0x10000000) +#define MCF5282_INTC_IMRH_INT59 (0x08000000) +#define MCF5282_INTC_IMRH_INT58 (0x04000000) +#define MCF5282_INTC_IMRH_INT57 (0x02000000) +#define MCF5282_INTC_IMRH_INT56 (0x01000000) +#define MCF5282_INTC_IMRH_INT55 (0x00800000) +#define MCF5282_INTC_IMRH_INT54 (0x00400000) +#define MCF5282_INTC_IMRH_INT53 (0x00200000) +#define MCF5282_INTC_IMRH_INT52 (0x00100000) +#define MCF5282_INTC_IMRH_INT51 (0x00080000) +#define MCF5282_INTC_IMRH_INT50 (0x00040000) +#define MCF5282_INTC_IMRH_INT49 (0x00020000) +#define MCF5282_INTC_IMRH_INT48 (0x00010000) +#define MCF5282_INTC_IMRH_INT47 (0x00008000) +#define MCF5282_INTC_IMRH_INT46 (0x00004000) +#define MCF5282_INTC_IMRH_INT45 (0x00002000) +#define MCF5282_INTC_IMRH_INT44 (0x00001000) +#define MCF5282_INTC_IMRH_INT43 (0x00000800) +#define MCF5282_INTC_IMRH_INT42 (0x00000400) +#define MCF5282_INTC_IMRH_INT41 (0x00000200) +#define MCF5282_INTC_IMRH_INT40 (0x00000100) +#define MCF5282_INTC_IMRH_INT39 (0x00000080) +#define MCF5282_INTC_IMRH_INT38 (0x00000040) +#define MCF5282_INTC_IMRH_INT37 (0x00000020) +#define MCF5282_INTC_IMRH_INT36 (0x00000010) +#define MCF5282_INTC_IMRH_INT35 (0x00000008) +#define MCF5282_INTC_IMRH_INT34 (0x00000004) +#define MCF5282_INTC_IMRH_INT33 (0x00000002) +#define MCF5282_INTC_IMRH_INT32 (0x00000001) + +#define MCF5282_INTC_IMRL_INT31 (0x80000000) +#define MCF5282_INTC_IMRL_INT30 (0x40000000) +#define MCF5282_INTC_IMRL_INT29 (0x20000000) +#define MCF5282_INTC_IMRL_INT28 (0x10000000) +#define MCF5282_INTC_IMRL_INT27 (0x08000000) +#define MCF5282_INTC_IMRL_INT26 (0x04000000) +#define MCF5282_INTC_IMRL_INT25 (0x02000000) +#define MCF5282_INTC_IMRL_INT24 (0x01000000) +#define MCF5282_INTC_IMRL_INT23 (0x00800000) +#define MCF5282_INTC_IMRL_INT22 (0x00400000) +#define MCF5282_INTC_IMRL_INT21 (0x00200000) +#define MCF5282_INTC_IMRL_INT20 (0x00100000) +#define MCF5282_INTC_IMRL_INT19 (0x00080000) +#define MCF5282_INTC_IMRL_INT18 (0x00040000) +#define MCF5282_INTC_IMRL_INT17 (0x00020000) +#define MCF5282_INTC_IMRL_INT16 (0x00010000) +#define MCF5282_INTC_IMRL_INT15 (0x00008000) +#define MCF5282_INTC_IMRL_INT14 (0x00004000) +#define MCF5282_INTC_IMRL_INT13 (0x00002000) +#define MCF5282_INTC_IMRL_INT12 (0x00001000) +#define MCF5282_INTC_IMRL_INT11 (0x00000800) +#define MCF5282_INTC_IMRL_INT10 (0x00000400) +#define MCF5282_INTC_IMRL_INT9 (0x00000200) +#define MCF5282_INTC_IMRL_INT8 (0x00000100) +#define MCF5282_INTC_IMRL_INT7 (0x00000080) +#define MCF5282_INTC_IMRL_INT6 (0x00000040) +#define MCF5282_INTC_IMRL_INT5 (0x00000020) +#define MCF5282_INTC_IMRL_INT4 (0x00000010) +#define MCF5282_INTC_IMRL_INT3 (0x00000008) +#define MCF5282_INTC_IMRL_INT2 (0x00000004) +#define MCF5282_INTC_IMRL_INT1 (0x00000002) +#define MCF5282_INTC_IMRL_MASKALL (0x00000001) + +#define MCF5282_INTC_INTFRCH_INT63 (0x80000000) +#define MCF5282_INTC_INTFRCH_INT62 (0x40000000) +#define MCF5282_INTC_INTFRCH_INT61 (0x20000000) +#define MCF5282_INTC_INTFRCH_INT60 (0x10000000) +#define MCF5282_INTC_INTFRCH_INT59 (0x08000000) +#define MCF5282_INTC_INTFRCH_INT58 (0x04000000) +#define MCF5282_INTC_INTFRCH_INT57 (0x02000000) +#define MCF5282_INTC_INTFRCH_INT56 (0x01000000) +#define MCF5282_INTC_INTFRCH_INT55 (0x00800000) +#define MCF5282_INTC_INTFRCH_INT54 (0x00400000) +#define MCF5282_INTC_INTFRCH_INT53 (0x00200000) +#define MCF5282_INTC_INTFRCH_INT52 (0x00100000) +#define MCF5282_INTC_INTFRCH_INT51 (0x00080000) +#define MCF5282_INTC_INTFRCH_INT50 (0x00040000) +#define MCF5282_INTC_INTFRCH_INT49 (0x00020000) +#define MCF5282_INTC_INTFRCH_INT48 (0x00010000) +#define MCF5282_INTC_INTFRCH_INT47 (0x00008000) +#define MCF5282_INTC_INTFRCH_INT46 (0x00004000) +#define MCF5282_INTC_INTFRCH_INT45 (0x00002000) +#define MCF5282_INTC_INTFRCH_INT44 (0x00001000) +#define MCF5282_INTC_INTFRCH_INT43 (0x00000800) +#define MCF5282_INTC_INTFRCH_INT42 (0x00000400) +#define MCF5282_INTC_INTFRCH_INT41 (0x00000200) +#define MCF5282_INTC_INTFRCH_INT40 (0x00000100) +#define MCF5282_INTC_INTFRCH_INT39 (0x00000080) +#define MCF5282_INTC_INTFRCH_INT38 (0x00000040) +#define MCF5282_INTC_INTFRCH_INT37 (0x00000020) +#define MCF5282_INTC_INTFRCH_INT36 (0x00000010) +#define MCF5282_INTC_INTFRCH_INT35 (0x00000008) +#define MCF5282_INTC_INTFRCH_INT34 (0x00000004) +#define MCF5282_INTC_INTFRCH_INT33 (0x00000002) +#define MCF5282_INTC_INTFRCH_INT32 (0x00000001) + +#define MCF5282_INTC_INTFRCL_INT31 (0x80000000) +#define MCF5282_INTC_INTFRCL_INT30 (0x40000000) +#define MCF5282_INTC_INTFRCL_INT29 (0x20000000) +#define MCF5282_INTC_INTFRCL_INT28 (0x10000000) +#define MCF5282_INTC_INTFRCL_INT27 (0x08000000) +#define MCF5282_INTC_INTFRCL_INT26 (0x04000000) +#define MCF5282_INTC_INTFRCL_INT25 (0x02000000) +#define MCF5282_INTC_INTFRCL_INT24 (0x01000000) +#define MCF5282_INTC_INTFRCL_INT23 (0x00800000) +#define MCF5282_INTC_INTFRCL_INT22 (0x00400000) +#define MCF5282_INTC_INTFRCL_INT21 (0x00200000) +#define MCF5282_INTC_INTFRCL_INT20 (0x00100000) +#define MCF5282_INTC_INTFRCL_INT19 (0x00080000) +#define MCF5282_INTC_INTFRCL_INT18 (0x00040000) +#define MCF5282_INTC_INTFRCL_INT17 (0x00020000) +#define MCF5282_INTC_INTFRCL_INT16 (0x00010000) +#define MCF5282_INTC_INTFRCL_INT15 (0x00008000) +#define MCF5282_INTC_INTFRCL_INT14 (0x00004000) +#define MCF5282_INTC_INTFRCL_INT13 (0x00002000) +#define MCF5282_INTC_INTFRCL_INT12 (0x00001000) +#define MCF5282_INTC_INTFRCL_INT11 (0x00000800) +#define MCF5282_INTC_INTFRCL_INT10 (0x00000400) +#define MCF5282_INTC_INTFRCL_INT9 (0x00000200) +#define MCF5282_INTC_INTFRCL_INT8 (0x00000100) +#define MCF5282_INTC_INTFRCL_INT7 (0x00000080) +#define MCF5282_INTC_INTFRCL_INT6 (0x00000040) +#define MCF5282_INTC_INTFRCL_INT5 (0x00000020) +#define MCF5282_INTC_INTFRCL_INT4 (0x00000010) +#define MCF5282_INTC_INTFRCL_INT3 (0x00000008) +#define MCF5282_INTC_INTFRCL_INT2 (0x00000004) +#define MCF5282_INTC_INTFRCL_INT1 (0x00000002) + +#define MCF5282_INTC_IRLR_IRQ7 (0x80) +#define MCF5282_INTC_IRLR_IRQ6 (0x40) +#define MCF5282_INTC_IRLR_IRQ5 (0x20) +#define MCF5282_INTC_IRLR_IRQ4 (0x10) +#define MCF5282_INTC_IRLR_IRQ3 (0x08) +#define MCF5282_INTC_IRLR_IRQ2 (0x04) +#define MCF5282_INTC_IRLR_IRQ1 (0x02) + +#define MCF5282_INTC_ICR_IL(x) (((x)&0x07)<<3) +#define MCF5282_INTC_ICR_IP(x) (((x)&0x07)<<0) + +/********************************************************************* +* +* Global Interrupt Acknowledge Cycle (GIAC) Registers +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_GIAC_GSWIACK (*(vuint8 *)(&__IPSBAR[0x0FE0])) +#define MCF5282_GIAC_GL1IACK (*(vuint8 *)(&__IPSBAR[0x0FE4])) +#define MCF5282_GIAC_GL2IACK (*(vuint8 *)(&__IPSBAR[0x0FE8])) +#define MCF5282_GIAC_GL3IACK (*(vuint8 *)(&__IPSBAR[0x0FEC])) +#define MCF5282_GIAC_GL4IACK (*(vuint8 *)(&__IPSBAR[0x0FF0])) +#define MCF5282_GIAC_GL5IACK (*(vuint8 *)(&__IPSBAR[0x0FF4])) +#define MCF5282_GIAC_GL6IACK (*(vuint8 *)(&__IPSBAR[0x0FF8])) +#define MCF5282_GIAC_GL7IACK (*(vuint8 *)(&__IPSBAR[0x0FFC])) + +/* Bit level definitions and macros */ + +/* To do - add bit level definintions */ + +/********************************************************************* +* +* Fast Ethernet Controller (FEC) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_FEC_EIR (*(vuint32 *)(&__IPSBAR[0x1004])) +#define MCF5282_FEC_EIMR (*(vuint32 *)(&__IPSBAR[0x1008])) +#define MCF5282_FEC_RDAR (*(vuint32 *)(&__IPSBAR[0x1010])) +#define MCF5282_FEC_TDAR (*(vuint32 *)(&__IPSBAR[0x1014])) +#define MCF5282_FEC_ECR (*(vuint32 *)(&__IPSBAR[0x1024])) +#define MCF5282_FEC_MMFR (*(vuint32 *)(&__IPSBAR[0x1040])) +#define MCF5282_FEC_MSCR (*(vuint32 *)(&__IPSBAR[0x1044])) +#define MCF5282_FEC_MIBC (*(vuint32 *)(&__IPSBAR[0x1064])) +#define MCF5282_FEC_RCR (*(vuint32 *)(&__IPSBAR[0x1084])) +#define MCF5282_FEC_TCR (*(vuint32 *)(&__IPSBAR[0x10C4])) +#define MCF5282_FEC_PALR (*(vuint32 *)(&__IPSBAR[0x10E4])) +#define MCF5282_FEC_PAUR (*(vuint32 *)(&__IPSBAR[0x10E8])) +#define MCF5282_FEC_OPD (*(vuint32 *)(&__IPSBAR[0x10EC])) +#define MCF5282_FEC_IAUR (*(vuint32 *)(&__IPSBAR[0x1118])) +#define MCF5282_FEC_IALR (*(vuint32 *)(&__IPSBAR[0x111C])) +#define MCF5282_FEC_GAUR (*(vuint32 *)(&__IPSBAR[0x1120])) +#define MCF5282_FEC_GALR (*(vuint32 *)(&__IPSBAR[0x1124])) +#define MCF5282_FEC_TFWR (*(vuint32 *)(&__IPSBAR[0x1144])) +#define MCF5282_FEC_FRBR (*(vuint32 *)(&__IPSBAR[0x114C])) +#define MCF5282_FEC_FRSR (*(vuint32 *)(&__IPSBAR[0x1150])) +#define MCF5282_FEC_ERDSR (*(vuint32 *)(&__IPSBAR[0x1180])) +#define MCF5282_FEC_ETDSR (*(vuint32 *)(&__IPSBAR[0x1184])) +#define MCF5282_FEC_EMRBR (*(vuint32 *)(&__IPSBAR[0x1188])) + +#define MCF5282_FEC_RMON_T_DROP (*(vuint32 *)(&__IPSBAR[0x1200])) +#define MCF5282_FEC_RMON_T_PACKETS (*(vuint32 *)(&__IPSBAR[0x1204])) +#define MCF5282_FEC_RMON_T_BC_PKT (*(vuint32 *)(&__IPSBAR[0x1208])) +#define MCF5282_FEC_RMON_T_MC_PKT (*(vuint32 *)(&__IPSBAR[0x120C])) +#define MCF5282_FEC_RMON_T_CRC_ALIGN (*(vuint32 *)(&__IPSBAR[0x1210])) +#define MCF5282_FEC_RMON_T_UNDERSIZE (*(vuint32 *)(&__IPSBAR[0x1214])) +#define MCF5282_FEC_RMON_T_OVERSIZE (*(vuint32 *)(&__IPSBAR[0x1218])) +#define MCF5282_FEC_RMON_T_FRAG (*(vuint32 *)(&__IPSBAR[0x121C])) +#define MCF5282_FEC_RMON_T_JAB (*(vuint32 *)(&__IPSBAR[0x1220])) +#define MCF5282_FEC_RMON_T_COL (*(vuint32 *)(&__IPSBAR[0x1224])) +#define MCF5282_FEC_RMON_T_P64 (*(vuint32 *)(&__IPSBAR[0x1228])) +#define MCF5282_FEC_RMON_T_P65TO127 (*(vuint32 *)(&__IPSBAR[0x122C])) +#define MCF5282_FEC_RMON_T_P128TO255 (*(vuint32 *)(&__IPSBAR[0x1230])) +#define MCF5282_FEC_RMON_T_P256TO511 (*(vuint32 *)(&__IPSBAR[0x1234])) +#define MCF5282_FEC_RMON_T_P512TO1023 (*(vuint32 *)(&__IPSBAR[0x1238])) +#define MCF5282_FEC_RMON_T_P1024TO2047 (*(vuint32 *)(&__IPSBAR[0x123C])) +#define MCF5282_FEC_RMON_T_P_GTE2048 (*(vuint32 *)(&__IPSBAR[0x1240])) +#define MCF5282_FEC_RMON_T_OCTETS (*(vuint32 *)(&__IPSBAR[0x1244])) +#define MCF5282_FEC_IEEE_T_DROP (*(vuint32 *)(&__IPSBAR[0x1248])) +#define MCF5282_FEC_IEEE_T_FRAME_OK (*(vuint32 *)(&__IPSBAR[0x124C])) +#define MCF5282_FEC_IEEE_T_1COL (*(vuint32 *)(&__IPSBAR[0x1250])) +#define MCF5282_FEC_IEEE_T_MCOL (*(vuint32 *)(&__IPSBAR[0x1254])) +#define MCF5282_FEC_IEEE_T_DEF (*(vuint32 *)(&__IPSBAR[0x1258])) +#define MCF5282_FEC_IEEE_T_LCOL (*(vuint32 *)(&__IPSBAR[0x125C])) +#define MCF5282_FEC_IEEE_T_EXCOL (*(vuint32 *)(&__IPSBAR[0x1260])) +#define MCF5282_FEC_IEEE_T_MACERR (*(vuint32 *)(&__IPSBAR[0x1264])) +#define MCF5282_FEC_IEEE_T_CSERR (*(vuint32 *)(&__IPSBAR[0x1268])) +#define MCF5282_FEC_IEEE_T_SQE (*(vuint32 *)(&__IPSBAR[0x126C])) +#define MCF5282_FEC_IEEE_T_FDXFC (*(vuint32 *)(&__IPSBAR[0x1270])) +#define MCF5282_FEC_IEEE_T_OCTETS_OK (*(vuint32 *)(&__IPSBAR[0x1274])) +#define MCF5282_FEC_RMON_R_PACKETS (*(vuint32 *)(&__IPSBAR[0x1284])) +#define MCF5282_FEC_RMON_R_BC_PKT (*(vuint32 *)(&__IPSBAR[0x1288])) +#define MCF5282_FEC_RMON_R_MC_PKT (*(vuint32 *)(&__IPSBAR[0x128C])) +#define MCF5282_FEC_RMON_R_CRC_ALIGN (*(vuint32 *)(&__IPSBAR[0x1290])) +#define MCF5282_FEC_RMON_R_UNDERSIZE (*(vuint32 *)(&__IPSBAR[0x1294])) +#define MCF5282_FEC_RMON_R_OVERSIZE (*(vuint32 *)(&__IPSBAR[0x1298])) +#define MCF5282_FEC_RMON_R_FRAG (*(vuint32 *)(&__IPSBAR[0x129C])) +#define MCF5282_FEC_RMON_R_JAB (*(vuint32 *)(&__IPSBAR[0x12A0])) +#define MCF5282_FEC_RMON_R_RESVD_0 (*(vuint32 *)(&__IPSBAR[0x12A4])) +#define MCF5282_FEC_RMON_R_P64 (*(vuint32 *)(&__IPSBAR[0x12A8])) +#define MCF5282_FEC_RMON_R_P65T0127 (*(vuint32 *)(&__IPSBAR[0x12AC])) +#define MCF5282_FEC_RMON_R_P128TO255 (*(vuint32 *)(&__IPSBAR[0x12B0])) +#define MCF5282_FEC_RMON_R_P256TO511 (*(vuint32 *)(&__IPSBAR[0x12B4])) +#define MCF5282_FEC_RMON_R_P512TO1023 (*(vuint32 *)(&__IPSBAR[0x12B8])) +#define MCF5282_FEC_RMON_R_P1024TO2047 (*(vuint32 *)(&__IPSBAR[0x12BC])) +#define MCF5282_FEC_RMON_R_GTE2048 (*(vuint32 *)(&__IPSBAR[0x12C0])) +#define MCF5282_FEC_RMON_R_OCTETS (*(vuint32 *)(&__IPSBAR[0x12C4])) +#define MCF5282_FEC_IEEE_R_DROP (*(vuint32 *)(&__IPSBAR[0x12C8])) +#define MCF5282_FEC_IEEE_R_FRAME_OK (*(vuint32 *)(&__IPSBAR[0x12CC])) +#define MCF5282_FEC_IEEE_R_CRC (*(vuint32 *)(&__IPSBAR[0x12D0])) +#define MCF5282_FEC_IEEE_R_ALIGN (*(vuint32 *)(&__IPSBAR[0x12D4])) +#define MCF5282_FEC_IEEE_R_MACERR (*(vuint32 *)(&__IPSBAR[0x12D8])) +#define MCF5282_FEC_IEEE_R_FDXFC (*(vuint32 *)(&__IPSBAR[0x12DC])) +#define MCF5282_FEC_IEEE_R_OCTETS_OK (*(vuint32 *)(&__IPSBAR[0x12E0])) + +/* Bit level definitions and macros */ +#define MCF5282_FEC_EIR_HBERR (0x80000000) +#define MCF5282_FEC_EIR_BABR (0x40000000) +#define MCF5282_FEC_EIR_BABT (0x20000000) +#define MCF5282_FEC_EIR_GRA (0x10000000) +#define MCF5282_FEC_EIR_TXF (0x08000000) +#define MCF5282_FEC_EIR_TXB (0x04000000) +#define MCF5282_FEC_EIR_RXF (0x02000000) +#define MCF5282_FEC_EIR_RXB (0x01000000) +#define MCF5282_FEC_EIR_MII (0x00800000) +#define MCF5282_FEC_EIR_EBERR (0x00400000) +#define MCF5282_FEC_EIR_LC (0x00200000) +#define MCF5282_FEC_EIR_RL (0x00100000) +#define MCF5282_FEC_EIR_UN (0x00080000) + +#define MCF5282_FEC_EIMR_HBERR (0x80000000) +#define MCF5282_FEC_EIMR_BABR (0x40000000) +#define MCF5282_FEC_EIMR_BABT (0x20000000) +#define MCF5282_FEC_EIMR_GRA (0x10000000) +#define MCF5282_FEC_EIMR_TXF (0x08000000) +#define MCF5282_FEC_EIMR_TXB (0x04000000) +#define MCF5282_FEC_EIMR_RXF (0x02000000) +#define MCF5282_FEC_EIMR_RXB (0x01000000) +#define MCF5282_FEC_EIMR_MII (0x00800000) +#define MCF5282_FEC_EIMR_EBERR (0x00400000) +#define MCF5282_FEC_EIMR_LC (0x00200000) +#define MCF5282_FEC_EIMR_RL (0x00100000) +#define MCF5282_FEC_EIMR_UN (0x00080000) + +#define MCF5282_FEC_RDAR_R_DES_ACTIVE (0x01000000) + +#define MCF5282_FEC_TDAR_X_DES_ACTIVE (0x01000000) + +#define MCF5282_FEC_ECR_ETHER_EN (0x00000002) +#define MCF5282_FEC_ECR_RESET (0x00000001) + +#define MCF5282_FEC_MMFR_ST (0x40000000) +#define MCF5282_FEC_MMFR_OP_RD (0x20000000) +#define MCF5282_FEC_MMFR_OP_WR (0x10000000) +#define MCF5282_FEC_MMFR_PA(x) (((x)&0x1F)<<23) +#define MCF5282_FEC_MMFR_RA(x) (((x)&0x1F)<<18) +#define MCF5282_FEC_MMFR_TA (0x00020000) +#define MCF5282_FEC_MMFR_DATA(x) (((x)&0xFFFF)) + +#define MCF5282_FEC_MSCR_DIS_PREAMBLE (0x00000008) +#define MCF5282_FEC_MSCR_MII_SPEED(x) (((x)&0x1F)<<1) + +#define MCF5282_FEC_MIBC_MIB_DISABLE (0x80000000) +#define MCF5282_FEC_MIBC_MIB_IDLE (0x40000000) + +#define MCF5282_FEC_RCR_MAX_FL(x) (((x)&0x07FF)<<16) +#define MCF5282_FEC_RCR_FCE (0x00000020) +#define MCF5282_FEC_RCR_BC_REJ (0x00000010) +#define MCF5282_FEC_RCR_PROM (0x00000008) +#define MCF5282_FEC_RCR_MII_MODE (0x00000004) +#define MCF5282_FEC_RCR_DRT (0x00000002) +#define MCF5282_FEC_RCR_LOOP (0x00000001) + +#define MCF5282_FEC_TCR_RFC_PAUSE (0x00000010) +#define MCF5282_FEC_TCR_TFC_PAUSE (0x00000008) +#define MCF5282_FEC_TCR_FDEN (0x00000004) +#define MCF5282_FEC_TCR_HBC (0x00000002) +#define MCF5282_FEC_TCR_GTS (0x00000001) + +#define MCF5282_FEC_PALR_BYTE0(x) (((x)&0xFF)<<24) +#define MCF5282_FEC_PALR_BYTE1(x) (((x)&0xFF)<<16) +#define MCF5282_FEC_PALR_BYTE2(x) (((x)&0xFF)<<8) +#define MCF5282_FEC_PALR_BYTE3(x) (((x)&0xFF)) + +#define MCF5282_FEC_PAUR_BYTE4(x) (((x)&0xFF)<<24) +#define MCF5282_FEC_PAUR_BYTE5(x) (((x)&0xFF)<<16) + +#define MCF5282_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)) + +#define MCF5282_FEC_TFWR_X_WMRK_64 (0x00000001) +#define MCF5282_FEC_TFWR_X_WMRK_128 (0x00000002) +#define MCF5282_FEC_TFWR_X_WMRK_192 (0x00000003) + +#define MCF5282_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4) + +#define MCF5282_FEC_TxBD_R 0x8000 +#define MCF5282_FEC_TxBD_BUSY 0x4000 +#define MCF5282_FEC_TxBD_TO1 0x4000 +#define MCF5282_FEC_TxBD_W 0x2000 +#define MCF5282_FEC_TxBD_TO2 0x1000 +#define MCF5282_FEC_TxBD_FIRST 0x1000 +#define MCF5282_FEC_TxBD_L 0x0800 +#define MCF5282_FEC_TxBD_TC 0x0400 +#define MCF5282_FEC_TxBD_DEF 0x0200 +#define MCF5282_FEC_TxBD_HB 0x0100 +#define MCF5282_FEC_TxBD_LC 0x0080 +#define MCF5282_FEC_TxBD_RL 0x0040 +#define MCF5282_FEC_TxBD_UN 0x0002 +#define MCF5282_FEC_TxBD_CSL 0x0001 + +#define MCF5282_FEC_RxBD_E 0x8000 +#define MCF5282_FEC_RxBD_INUSE 0x4000 +#define MCF5282_FEC_RxBD_R01 0x4000 +#define MCF5282_FEC_RxBD_W 0x2000 +#define MCF5282_FEC_RxBD_R02 0x1000 +#define MCF5282_FEC_RxBD_L 0x0800 +#define MCF5282_FEC_RxBD_M 0x0100 +#define MCF5282_FEC_RxBD_BC 0x0080 +#define MCF5282_FEC_RxBD_MC 0x0040 +#define MCF5282_FEC_RxBD_LG 0x0020 +#define MCF5282_FEC_RxBD_NO 0x0010 +#define MCF5282_FEC_RxBD_CR 0x0004 +#define MCF5282_FEC_RxBD_OV 0x0002 +#define MCF5282_FEC_RxBD_TR 0x0001 + +/********************************************************************* +* +* General Purpose I/O (GPIO) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_GPIO_PORTA (*(vuint8 *)(&__IPSBAR[0x100000])) +#define MCF5282_GPIO_PORTB (*(vuint8 *)(&__IPSBAR[0x100001])) +#define MCF5282_GPIO_PORTC (*(vuint8 *)(&__IPSBAR[0x100002])) +#define MCF5282_GPIO_PORTD (*(vuint8 *)(&__IPSBAR[0x100003])) +#define MCF5282_GPIO_PORTE (*(vuint8 *)(&__IPSBAR[0x100004])) +#define MCF5282_GPIO_PORTF (*(vuint8 *)(&__IPSBAR[0x100005])) +#define MCF5282_GPIO_PORTG (*(vuint8 *)(&__IPSBAR[0x100006])) +#define MCF5282_GPIO_PORTH (*(vuint8 *)(&__IPSBAR[0x100007])) +#define MCF5282_GPIO_PORTJ (*(vuint8 *)(&__IPSBAR[0x100008])) +#define MCF5282_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100009])) +#define MCF5282_GPIO_PORTEH (*(vuint8 *)(&__IPSBAR[0x10000A])) +#define MCF5282_GPIO_PORTEL (*(vuint8 *)(&__IPSBAR[0x10000B])) +#define MCF5282_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000C])) +#define MCF5282_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000D])) +#define MCF5282_GPIO_PORTSD (*(vuint8 *)(&__IPSBAR[0x10000E])) +#define MCF5282_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F])) +#define MCF5282_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010])) +#define MCF5282_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011])) + +#define MCF5282_GPIO_DDRA (*(vuint8 *)(&__IPSBAR[0x100014])) +#define MCF5282_GPIO_DDRB (*(vuint8 *)(&__IPSBAR[0x100015])) +#define MCF5282_GPIO_DDRC (*(vuint8 *)(&__IPSBAR[0x100016])) +#define MCF5282_GPIO_DDRD (*(vuint8 *)(&__IPSBAR[0x100017])) +#define MCF5282_GPIO_DDRE (*(vuint8 *)(&__IPSBAR[0x100018])) +#define MCF5282_GPIO_DDRF (*(vuint8 *)(&__IPSBAR[0x100019])) +#define MCF5282_GPIO_DDRG (*(vuint8 *)(&__IPSBAR[0x10001A])) +#define MCF5282_GPIO_DDRH (*(vuint8 *)(&__IPSBAR[0x10001B])) +#define MCF5282_GPIO_DDRJ (*(vuint8 *)(&__IPSBAR[0x10001C])) +#define MCF5282_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10001D])) +#define MCF5282_GPIO_DDREH (*(vuint8 *)(&__IPSBAR[0x10001E])) +#define MCF5282_GPIO_DDREL (*(vuint8 *)(&__IPSBAR[0x10001F])) +#define MCF5282_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100020])) +#define MCF5282_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100021])) +#define MCF5282_GPIO_DDRSD (*(vuint8 *)(&__IPSBAR[0x100022])) +#define MCF5282_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100023])) +#define MCF5282_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100024])) +#define MCF5282_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100025])) + +#define MCF5282_GPIO_PORTAP (*(vuint8 *)(&__IPSBAR[0x100028])) +#define MCF5282_GPIO_PORTBP (*(vuint8 *)(&__IPSBAR[0x100029])) +#define MCF5282_GPIO_PORTCP (*(vuint8 *)(&__IPSBAR[0x10002A])) +#define MCF5282_GPIO_PORTDP (*(vuint8 *)(&__IPSBAR[0x10002B])) +#define MCF5282_GPIO_PORTEP (*(vuint8 *)(&__IPSBAR[0x10002C])) +#define MCF5282_GPIO_PORTFP (*(vuint8 *)(&__IPSBAR[0x10002D])) +#define MCF5282_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x10002E])) +#define MCF5282_GPIO_PORTHP (*(vuint8 *)(&__IPSBAR[0x10002F])) +#define MCF5282_GPIO_PORTJP (*(vuint8 *)(&__IPSBAR[0x100030])) +#define MCF5282_GPIO_PORTDDP (*(vuint8 *)(&__IPSBAR[0x100031])) +#define MCF5282_GPIO_PORTEHP (*(vuint8 *)(&__IPSBAR[0x100032])) +#define MCF5282_GPIO_PORTELP (*(vuint8 *)(&__IPSBAR[0x100033])) +#define MCF5282_GPIO_PORTASP (*(vuint8 *)(&__IPSBAR[0x100034])) +#define MCF5282_GPIO_PORTQSP (*(vuint8 *)(&__IPSBAR[0x100035])) +#define MCF5282_GPIO_PORTSDP (*(vuint8 *)(&__IPSBAR[0x100036])) +#define MCF5282_GPIO_PORTTCP (*(vuint8 *)(&__IPSBAR[0x100037])) +#define MCF5282_GPIO_PORTTDP (*(vuint8 *)(&__IPSBAR[0x100038])) +#define MCF5282_GPIO_PORTUAP (*(vuint8 *)(&__IPSBAR[0x100039])) + +#define MCF5282_GPIO_SETA (*(vuint8 *)(&__IPSBAR[0x100028])) +#define MCF5282_GPIO_SETB (*(vuint8 *)(&__IPSBAR[0x100029])) +#define MCF5282_GPIO_SETC (*(vuint8 *)(&__IPSBAR[0x10002A])) +#define MCF5282_GPIO_SETD (*(vuint8 *)(&__IPSBAR[0x10002B])) +#define MCF5282_GPIO_SETE (*(vuint8 *)(&__IPSBAR[0x10002C])) +#define MCF5282_GPIO_SETF (*(vuint8 *)(&__IPSBAR[0x10002D])) +#define MCF5282_GPIO_SETG (*(vuint8 *)(&__IPSBAR[0x10002E])) +#define MCF5282_GPIO_SETH (*(vuint8 *)(&__IPSBAR[0x10002F])) +#define MCF5282_GPIO_SETJ (*(vuint8 *)(&__IPSBAR[0x100030])) +#define MCF5282_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100031])) +#define MCF5282_GPIO_SETEH (*(vuint8 *)(&__IPSBAR[0x100032])) +#define MCF5282_GPIO_SETEL (*(vuint8 *)(&__IPSBAR[0x100033])) +#define MCF5282_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x100034])) +#define MCF5282_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x100035])) +#define MCF5282_GPIO_SETSD (*(vuint8 *)(&__IPSBAR[0x100036])) +#define MCF5282_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x100037])) +#define MCF5282_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100038])) +#define MCF5282_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100039])) + +#define MCF5282_GPIO_CLRA (*(vuint8 *)(&__IPSBAR[0x10003C])) +#define MCF5282_GPIO_CLRB (*(vuint8 *)(&__IPSBAR[0x10003D])) +#define MCF5282_GPIO_CLRC (*(vuint8 *)(&__IPSBAR[0x10003E])) +#define MCF5282_GPIO_CLRD (*(vuint8 *)(&__IPSBAR[0x10003F])) +#define MCF5282_GPIO_CLRE (*(vuint8 *)(&__IPSBAR[0x100040])) +#define MCF5282_GPIO_CLRF (*(vuint8 *)(&__IPSBAR[0x100041])) +#define MCF5282_GPIO_CLRG (*(vuint8 *)(&__IPSBAR[0x100042])) +#define MCF5282_GPIO_CLRH (*(vuint8 *)(&__IPSBAR[0x100043])) +#define MCF5282_GPIO_CLRJ (*(vuint8 *)(&__IPSBAR[0x100044])) +#define MCF5282_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x100045])) +#define MCF5282_GPIO_CLREH (*(vuint8 *)(&__IPSBAR[0x100046])) +#define MCF5282_GPIO_CLREL (*(vuint8 *)(&__IPSBAR[0x100047])) +#define MCF5282_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100048])) +#define MCF5282_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100049])) +#define MCF5282_GPIO_CLRSD (*(vuint8 *)(&__IPSBAR[0x10004A])) +#define MCF5282_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x10004B])) +#define MCF5282_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x10004C])) +#define MCF5282_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x10004D])) + +#define MCF5282_GPIO_PBCDPAR (*(vuint8 *)(&__IPSBAR[0x100050])) +#define MCF5282_GPIO_PFPAR (*(vuint8 *)(&__IPSBAR[0x100051])) +#define MCF5282_GPIO_PEPAR (*(vuint16 *)(&__IPSBAR[0x100052])) +#define MCF5282_GPIO_PJPAR (*(vuint8 *)(&__IPSBAR[0x100054])) +#define MCF5282_GPIO_PSDPAR (*(vuint8 *)(&__IPSBAR[0x100055])) +#define MCF5282_GPIO_PASPAR (*(vuint16 *)(&__IPSBAR[0x100056])) +#define MCF5282_GPIO_PEHLPAR (*(vuint8 *)(&__IPSBAR[0x100058])) +#define MCF5282_GPIO_PQSPAR (*(vuint8 *)(&__IPSBAR[0x100059])) +#define MCF5282_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10005A])) +#define MCF5282_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x10005B])) +#define MCF5282_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x10005C])) + +/* Bit level definitions and macros */ +#define MCF5282_GPIO_PORTx7 (0x80) +#define MCF5282_GPIO_PORTx6 (0x40) +#define MCF5282_GPIO_PORTx5 (0x20) +#define MCF5282_GPIO_PORTx4 (0x10) +#define MCF5282_GPIO_PORTx3 (0x08) +#define MCF5282_GPIO_PORTx2 (0x04) +#define MCF5282_GPIO_PORTx1 (0x02) +#define MCF5282_GPIO_PORTx0 (0x01) +#define MCF5282_GPIO_PORTx(x) (0x01<<(x)) + +#define MCF5282_GPIO_DDRx7 (0x80) +#define MCF5282_GPIO_DDRx6 (0x40) +#define MCF5282_GPIO_DDRx5 (0x20) +#define MCF5282_GPIO_DDRx4 (0x10) +#define MCF5282_GPIO_DDRx3 (0x08) +#define MCF5282_GPIO_DDRx2 (0x04) +#define MCF5282_GPIO_DDRx1 (0x02) +#define MCF5282_GPIO_DDRx0 (0x01) +#define MCF5282_GPIO_DDRx(x) (0x01<<(x)) + +#define MCF5282_GPIO_PORTxP7 (0x80) +#define MCF5282_GPIO_PORTxP6 (0x40) +#define MCF5282_GPIO_PORTxP5 (0x20) +#define MCF5282_GPIO_PORTxP4 (0x10) +#define MCF5282_GPIO_PORTxP3 (0x08) +#define MCF5282_GPIO_PORTxP2 (0x04) +#define MCF5282_GPIO_PORTxP1 (0x02) +#define MCF5282_GPIO_PORTxP0 (0x01) +#define MCF5282_GPIO_PORTxP(x) (0x01<<(x)) + +#define MCF5282_GPIO_SETx7 (0x80) +#define MCF5282_GPIO_SETx6 (0x40) +#define MCF5282_GPIO_SETx5 (0x20) +#define MCF5282_GPIO_SETx4 (0x10) +#define MCF5282_GPIO_SETx3 (0x08) +#define MCF5282_GPIO_SETx2 (0x04) +#define MCF5282_GPIO_SETx1 (0x02) +#define MCF5282_GPIO_SETx0 (0x01) +#define MCF5282_GPIO_SETx(x) (0x01<<(x)) + +#define MCF5282_GPIO_CLRx7 (0x80) +#define MCF5282_GPIO_CLRx6 (0x40) +#define MCF5282_GPIO_CLRx5 (0x20) +#define MCF5282_GPIO_CLRx4 (0x10) +#define MCF5282_GPIO_CLRx3 (0x08) +#define MCF5282_GPIO_CLRx2 (0x04) +#define MCF5282_GPIO_CLRx1 (0x02) +#define MCF5282_GPIO_CLRx0 (0x01) +#define MCF5282_GPIO_CLRx(x) (0x01<<(x)) + +#define MCF5282_GPIO_PBCDPAR_PBPA (0x80) +#define MCF5282_GPIO_PBCDPAR_PCDPA (0x40) + +#define MCF5282_GPIO_PEPAR_PEPA7 (0x4000) +#define MCF5282_GPIO_PEPAR_PEPA6 (0x1000) +#define MCF5282_GPIO_PEPAR_PEPA5 (0x0400) +#define MCF5282_GPIO_PEPAR_PEPA4 (0x0100) +#define MCF5282_GPIO_PEPAR_PEPA3 (0x0040) +#define MCF5282_GPIO_PEPAR_PEPA2 (0x0010) +#define MCF5282_GPIO_PEPAR_PEPA1(x) (((x)&0x3)<<2) +#define MCF5282_GPIO_PEPAR_PEPA0(x) (((x)&0x3)) + +#define MCF5282_GPIO_PFPAR_PFPA7 (0x80) +#define MCF5282_GPIO_PFPAR_PFPA6 (0x40) +#define MCF5282_GPIO_PFPAR_PFPA5 (0x20) + +#define MCF5282_GPIO_PJPAR_PJPA7 (0x80) +#define MCF5282_GPIO_PJPAR_PJPA6 (0x40) +#define MCF5282_GPIO_PJPAR_PJPA5 (0x20) +#define MCF5282_GPIO_PJPAR_PJPA4 (0x10) +#define MCF5282_GPIO_PJPAR_PJPA3 (0x08) +#define MCF5282_GPIO_PJPAR_PJPA2 (0x04) +#define MCF5282_GPIO_PJPAR_PJPA1 (0x02) +#define MCF5282_GPIO_PJPAR_PJPA0 (0x01) +#define MCF5282_GPIO_PJPAR_PJPA(x) (0x01<<(x)) + +#define MCF5282_GPIO_PSDPAR_PSDPA (0x80) + +#define MCF5282_GPIO_PASPAR_PASPA5(x) (((x)&0x3)<<10) +#define MCF5282_GPIO_PASPAR_PASPA4(x) (((x)&0x3)<<8) +#define MCF5282_GPIO_PASPAR_PASPA3(x) (((x)&0x3)<<6) +#define MCF5282_GPIO_PASPAR_PASPA2(x) (((x)&0x3)<<4) +#define MCF5282_GPIO_PASPAR_PASPA1(x) (((x)&0x3)<<2) +#define MCF5282_GPIO_PASPAR_PASPA0(x) (((x)&0x3)) + +#define MCF5282_GPIO_PEHLPAR_PEHPA (0x80) +#define MCF5282_GPIO_PEHLPAR_PELPA (0x40) + +#define MCF5282_GPIO_PQSPAR_PQSPA6 (0x40) +#define MCF5282_GPIO_PQSPAR_PQSPA5 (0x20) +#define MCF5282_GPIO_PQSPAR_PQSPA4 (0x10) +#define MCF5282_GPIO_PQSPAR_PQSPA3 (0x08) +#define MCF5282_GPIO_PQSPAR_PQSPA2 (0x04) +#define MCF5282_GPIO_PQSPAR_PQSPA1 (0x02) +#define MCF5282_GPIO_PQSPAR_PQSPA0 (0x01) +#define MCF5282_GPIO_PQSPAR_PQSPA(x) (0x01<<(x)) + +#define MCF5282_GPIO_PTCPAR_PTCPA3(x) (((x)&0x3)<<6) +#define MCF5282_GPIO_PTCPAR_PTCPA2(x) (((x)&0x3)<<4) +#define MCF5282_GPIO_PTCPAR_PTCPA1(x) (((x)&0x3)<<2) +#define MCF5282_GPIO_PTCPAR_PTCPA0(x) (((x)&0x3)) + +#define MCF5282_GPIO_PTDPAR_PTDPA3(x) (((x)&0x3)<<6) +#define MCF5282_GPIO_PTDPAR_PTDPA2(x) (((x)&0x3)<<4) +#define MCF5282_GPIO_PTDPAR_PTDPA1(x) (((x)&0x3)<<2) +#define MCF5282_GPIO_PTDPAR_PTDPA0(x) (((x)&0x3)) + +#define MCF5282_GPIO_PUAPAR_PUAPA3 (0x08) +#define MCF5282_GPIO_PUAPAR_PUAPA2 (0x04) +#define MCF5282_GPIO_PUAPAR_PUAPA1 (0x02) +#define MCF5282_GPIO_PUAPAR_PUAPA0 (0x01) + +/********************************************************************* +* +* Reset Controller Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_RESET_RCR (*(vuint8 *)(&__IPSBAR[0x110000])) +#define MCF5282_RESET_RSR (*(vuint8 *)(&__IPSBAR[0x110001])) + +/* Bit level definitions and macros */ +#define MCF5282_RESET_RCR_SOFTRST (0x80) +#define MCF5282_RESET_RCR_FRCRSTOUT (0x40) +#define MCF5282_RESET_RCR_LVDF (0x10) +#define MCF5282_RESET_RCR_LVDIE (0x08) +#define MCF5282_RESET_RCR_LVDRE (0x04) +#define MCF5282_RESET_RCR_LVDE (0x01) + +#define MCF5282_RESET_RSR_LVD (0x40) +#define MCF5282_RESET_RSR_SOFT (0x20) +#define MCF5282_RESET_RSR_WDR (0x10) +#define MCF5282_RESET_RSR_POR (0x08) +#define MCF5282_RESET_RSR_EXT (0x04) +#define MCF5282_RESET_RSR_LOC (0x02) +#define MCF5282_RESET_RSR_LOL (0x01) + +/********************************************************************* +* +* Chip Configuration Module (CCM) +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_CCM_CCR (*(vuint16 *)(&__IPSBAR[0x110004])) +#define MCF5282_CCM_RCON (*(vuint16 *)(&__IPSBAR[0x110008])) +#define MCF5282_CCM_CIR (*(vuint16 *)(&__IPSBAR[0x11000A])) + +/* Bit level definitions and macros */ +#define MCF5282_CCM_CCR_LOAD (0x8000) +#define MCF5282_CCM_CCR_MODE(x) (((x)&0x0007)<<8) +#define MCF5282_CCM_CCR_SZEN (0x0040) +#define MCF5282_CCM_CCR_PSTEN (0x0020) +#define MCF5282_CCM_CCR_BME (0x0008) +#define MCF5282_CCM_CCR_BMT(x) (((x)&0x0007)) + +/********************************************************************* +* +* Power Management Module (PMM) +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) +#define MCF5282_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) + +/* Bit level definitions and macros */ +#define MCF5282_PMM_LPICR_ENBSTOP (0x80) +#define MCF5282_PMM_LPICR_XLMP_IPL(x) (((x)&0x07)<<4) + +#define MCF5282_PMM_LPCR_LPMD_STOP (0xC0) +#define MCF5282_PMM_LPCR_LPMD_WAIT (0x80) +#define MCF5282_PMM_LPCR_LPMD_DOZE (0x40) +#define MCF5282_PMM_LPCR_LPMD_RUN (0x00) +#define MCF5282_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF5282_PMM_LPCR_LVDSE (0x02) + +/********************************************************************* +* +* Clock Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_CLOCK_SYNCR (*(vuint16 *)(&__IPSBAR[0x120000])) +#define MCF5282_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002])) + +/* Bit level definitions and macros */ +#define MCF5282_CLOCK_SYNCR_LOLRE (0x8000) +#define MCF5282_CLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) +#define MCF5282_CLOCK_SYNCR_LOCRE (0x0800) +#define MCF5282_CLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) +#define MCF5282_CLOCK_SYNCR_LOCEN (0x0080) +#define MCF5282_CLOCK_SYNCR_DISCLK (0x0040) +#define MCF5282_CLOCK_SYNCR_FWKUP (0x0020) +#define MCF5282_CLOCK_SYNCR_STPMD(x) (((x)&0x0003)<<2) + +#define MCF5282_CLOCK_SYNSR_PLLMODE (0x80) +#define MCF5282_CLOCK_SYNSR_PLLSEL (0x40) +#define MCF5282_CLOCK_SYNSR_PLLREF (0x20) +#define MCF5282_CLOCK_SYNSR_LOCKS (0x10) +#define MCF5282_CLOCK_SYNSR_LOCK (0x08) +#define MCF5282_CLOCK_SYNSR_LOCS (0x04) + +/********************************************************************* +* +* Edge Port (EPORT) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_EPORT_EPPAR (*(vuint16 *)(&__IPSBAR[0x130000])) +#define MCF5282_EPORT_EPDDR (*(vuint8 *)(&__IPSBAR[0x130002])) +#define MCF5282_EPORT_EPIER (*(vuint8 *)(&__IPSBAR[0x130003])) +#define MCF5282_EPORT_EPDR (*(vuint8 *)(&__IPSBAR[0x130004])) +#define MCF5282_EPORT_EPPDR (*(vuint8 *)(&__IPSBAR[0x130005])) +#define MCF5282_EPORT_EPFR (*(vuint8 *)(&__IPSBAR[0x130006])) + +/* Bit level definitions and macros */ +#define MCF5282_EPORT_EPPAR_EPPA7_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF5282_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF5282_EPORT_EPPAR_EPPA7_BOTHEDGE (0xC000) +#define MCF5282_EPORT_EPPAR_EPPA6_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF5282_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF5282_EPORT_EPPAR_EPPA6_BOTHEDGE (0x3000) +#define MCF5282_EPORT_EPPAR_EPPA5_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA5_RISING (0x0400) +#define MCF5282_EPORT_EPPAR_EPPA5_FALLING (0x0800) +#define MCF5282_EPORT_EPPAR_EPPA5_BOTHEDGE (0x0C00) +#define MCF5282_EPORT_EPPAR_EPPA4_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA4_RISING (0x0100) +#define MCF5282_EPORT_EPPAR_EPPA4_FALLING (0x0200) +#define MCF5282_EPORT_EPPAR_EPPA4_BOTHEDGE (0x0300) +#define MCF5282_EPORT_EPPAR_EPPA3_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA3_RISING (0x0040) +#define MCF5282_EPORT_EPPAR_EPPA3_FALLING (0x0080) +#define MCF5282_EPORT_EPPAR_EPPA3_BOTHEDGE (0x00C0) +#define MCF5282_EPORT_EPPAR_EPPA2_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA2_RISING (0x0010) +#define MCF5282_EPORT_EPPAR_EPPA2_FALLING (0x0020) +#define MCF5282_EPORT_EPPAR_EPPA2_BOTHEDGE (0x0030) +#define MCF5282_EPORT_EPPAR_EPPA1_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA1_RISING (0x0004) +#define MCF5282_EPORT_EPPAR_EPPA1_FALLING (0x0008) +#define MCF5282_EPORT_EPPAR_EPPA1_BOTHEDGE (0x000C) + + +#define MCF5282_EPORT_EPDDR_EPDD7 (0x80) +#define MCF5282_EPORT_EPDDR_EPDD6 (0x40) +#define MCF5282_EPORT_EPDDR_EPDD5 (0x20) +#define MCF5282_EPORT_EPDDR_EPDD4 (0x10) +#define MCF5282_EPORT_EPDDR_EPDD3 (0x08) +#define MCF5282_EPORT_EPDDR_EPDD2 (0x04) +#define MCF5282_EPORT_EPDDR_EPDD1 (0x02) +#define MCF5282_EPORT_EPDDR_EPDD(x) (0x01<<(x)) + +#define MCF5282_EPORT_EPIER_EPIE7 (0x80) +#define MCF5282_EPORT_EPIER_EPIE6 (0x40) +#define MCF5282_EPORT_EPIER_EPIE5 (0x20) +#define MCF5282_EPORT_EPIER_EPIE4 (0x10) +#define MCF5282_EPORT_EPIER_EPIE3 (0x08) +#define MCF5282_EPORT_EPIER_EPIE2 (0x04) +#define MCF5282_EPORT_EPIER_EPIE1 (0x02) +#define MCF5282_EPORT_EPIER_EPIE(x) (0x01<<(x)) + +#define MCF5282_EPORT_EPDR_EPD7 (0x80) +#define MCF5282_EPORT_EPDR_EPD6 (0x40) +#define MCF5282_EPORT_EPDR_EPD5 (0x20) +#define MCF5282_EPORT_EPDR_EPD4 (0x10) +#define MCF5282_EPORT_EPDR_EPD3 (0x08) +#define MCF5282_EPORT_EPDR_EPD2 (0x04) +#define MCF5282_EPORT_EPDR_EPD1 (0x02) +#define MCF5282_EPORT_EPDR_EPD(x) (0x01<<(x)) + +#define MCF5282_EPORT_EPPDR_EPPD7 (0x80) +#define MCF5282_EPORT_EPPDR_EPPD6 (0x40) +#define MCF5282_EPORT_EPPDR_EPPD5 (0x20) +#define MCF5282_EPORT_EPPDR_EPPD4 (0x10) +#define MCF5282_EPORT_EPPDR_EPPD3 (0x08) +#define MCF5282_EPORT_EPPDR_EPPD2 (0x04) +#define MCF5282_EPORT_EPPDR_EPPD1 (0x02) +#define MCF5282_EPORT_EPPDR_EPPD(x) (0x01<<(x)) + +#define MCF5282_EPORT_EPFR_EPF7 (0x80) +#define MCF5282_EPORT_EPFR_EPF6 (0x40) +#define MCF5282_EPORT_EPFR_EPF5 (0x20) +#define MCF5282_EPORT_EPFR_EPF4 (0x10) +#define MCF5282_EPORT_EPFR_EPF3 (0x08) +#define MCF5282_EPORT_EPFR_EPF2 (0x04) +#define MCF5282_EPORT_EPFR_EPF1 (0x02) +#define MCF5282_EPORT_EPFR_EPF(x) (0x01<<(x)) + +/********************************************************************* +* +* Watchdog Timer Module (WTM) +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_WTM_WCR (*(vuint16 *)(&__IPSBAR[0x140000])) +#define MCF5282_WTM_WMR (*(vuint16 *)(&__IPSBAR[0x140002])) +#define MCF5282_WTM_WCNTR (*(vuint16 *)(&__IPSBAR[0x140004])) +#define MCF5282_WTM_WSR (*(vuint16 *)(&__IPSBAR[0x140006])) + +/* Bit level definitions and macros */ +#define MCF5282_WTM_WCR_WAIT (0x0008) +#define MCF5282_WTM_WCR_DOZE (0x0004) +#define MCF5282_WTM_WCR_HALTED (0x0002) +#define MCF5282_WTM_WCR_EN (0x0001) + +#define MCF5282_WTM_WSR_SEQ1 (0x5555) +#define MCF5282_WTM_WSR_SEQ2 (0xAAAA) + +/********************************************************************* +* +* Programmable Interrupt Timer (PIT) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_PIT0_PCSR (*(vuint16 *)(&__IPSBAR[0x150000])) +#define MCF5282_PIT0_PMR (*(vuint16 *)(&__IPSBAR[0x150002])) +#define MCF5282_PIT0_PCNTR (*(vuint16 *)(&__IPSBAR[0x150004])) + +#define MCF5282_PIT1_PCSR (*(vuint16 *)(&__IPSBAR[0x160000])) +#define MCF5282_PIT1_PMR (*(vuint16 *)(&__IPSBAR[0x160002])) +#define MCF5282_PIT1_PCNTR (*(vuint16 *)(&__IPSBAR[0x160004])) + +#define MCF5282_PIT2_PCSR (*(vuint16 *)(&__IPSBAR[0x170000])) +#define MCF5282_PIT2_PMR (*(vuint16 *)(&__IPSBAR[0x170002])) +#define MCF5282_PIT2_PCNTR (*(vuint16 *)(&__IPSBAR[0x170004])) + +#define MCF5282_PIT3_PCSR (*(vuint16 *)(&__IPSBAR[0x180000])) +#define MCF5282_PIT3_PMR (*(vuint16 *)(&__IPSBAR[0x180002])) +#define MCF5282_PIT3_PCNTR (*(vuint16 *)(&__IPSBAR[0x180004])) + +#define MCF5282_PIT_PCSR(x) (*(vuint16 *)(&__IPSBAR[0x150000+(0x1000*(x))])) +#define MCF5282_PIT_PMR(x) (*(vuint16 *)(&__IPSBAR[0x150002+(0x1000*(x))])) +#define MCF5282_PIT_PCNTR(x) (*(vuint16 *)(&__IPSBAR[0x150004+(0x1000*(x))])) + +/* Bit level definitions and macros */ +#define MCF5282_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) +#define MCF5282_PIT_PCSR_DOZE (0x0040) +#define MCF5282_PIT_PCSR_HALTED (0x0020) +#define MCF5282_PIT_PCSR_OVW (0x0010) +#define MCF5282_PIT_PCSR_PIE (0x0008) +#define MCF5282_PIT_PCSR_PIF (0x0004) +#define MCF5282_PIT_PCSR_RLD (0x0002) +#define MCF5282_PIT_PCSR_EN (0x0001) + +/********************************************************************* +* +* Queued Analog to Digital Converter (QADC) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_QADC_QADCMCR (*(vuint16 *)(&__IPSBAR[0x190000])) +#define MCF5282_QADC_PORTQA (*(vuint8 *)(&__IPSBAR[0x190006])) +#define MCF5282_QADC_PORTQB (*(vuint8 *)(&__IPSBAR[0x190007])) +#define MCF5282_QADC_DDRQA (*(vuint8 *)(&__IPSBAR[0x190008])) +#define MCF5282_QADC_DDRQB (*(vuint8 *)(&__IPSBAR[0x190009])) +#define MCF5282_QADC_QACR0 (*(vuint16 *)(&__IPSBAR[0x19000A])) +#define MCF5282_QADC_QACR1 (*(vuint16 *)(&__IPSBAR[0x19000C])) +#define MCF5282_QADC_QACR2 (*(vuint16 *)(&__IPSBAR[0x19000E])) +#define MCF5282_QADC_QASR0 (*(vuint16 *)(&__IPSBAR[0x190010])) +#define MCF5282_QADC_QASR1 (*(vuint16 *)(&__IPSBAR[0x190012])) +#define MCF5282_QADC_CCW(x) (*(vuint16 *)(&__IPSBAR[0x190200+((x)*2)])) +#define MCF5282_QADC_RJURR(x) (*(vuint16 *)(&__IPSBAR[0x190280+((x)*2)])) +#define MCF5282_QADC_LJSRR(x) (*(vuint16 *)(&__IPSBAR[0x190300+((x)*2)])) +#define MCF5282_QADC_LJURR(x) (*(vuint16 *)(&__IPSBAR[0x190380+((x)*2)])) + +/* Bit level definitions and macros */ +#define MCF5282_QADC_QADCMCR_QSTOP (0x8000) +#define MCF5282_QADC_QADCMCR_QDBG (0x4000) +#define MCF5282_QADC_QADCMCR_SUPV (0x0080) + +#define MCF5282_QADC_PORTQA_PQA4 (0x10) +#define MCF5282_QADC_PORTQA_PQA3 (0x08) +#define MCF5282_QADC_PORTQA_PQA1 (0x02) +#define MCF5282_QADC_PORTQA_PQA0 (0x01) +#define MCF5282_QADC_PORTQA_AN56 (0x10) +#define MCF5282_QADC_PORTQA_AN55 (0x08) +#define MCF5282_QADC_PORTQA_ETRIG2 (0x10) +#define MCF5282_QADC_PORTQA_ETRIG1 (0x08) +#define MCF5282_QADC_PORTQA_AN53 (0x02) +#define MCF5282_QADC_PORTQA_AN52 (0x01) +#define MCF5282_QADC_PORTQA_MA1 (0x02) +#define MCF5282_QADC_PORTQA_MA0 (0x01) + +#define MCF5282_QADC_PORTQB_PQB3 (0x08) +#define MCF5282_QADC_PORTQB_PQB2 (0x04) +#define MCF5282_QADC_PORTQB_PQB1 (0x02) +#define MCF5282_QADC_PORTQB_PQB0 (0x01) +#define MCF5282_QADC_PORTQB_AN3 (0x08) +#define MCF5282_QADC_PORTQB_AN2 (0x04) +#define MCF5282_QADC_PORTQB_AN1 (0x02) +#define MCF5282_QADC_PORTQB_AN0 (0x01) +#define MCF5282_QADC_PORTQB_ANZ (0x08) +#define MCF5282_QADC_PORTQB_ANY (0x04) +#define MCF5282_QADC_PORTQB_ANX (0x02) +#define MCF5282_QADC_PORTQB_ANW (0x01) + +#define MCF5282_QADC_DDRQA_DDQA4 (0x10) +#define MCF5282_QADC_DDRQA_DDQA3 (0x08) +#define MCF5282_QADC_DDRQA_DDQA1 (0x02) +#define MCF5282_QADC_DDRQA_DDQA0 (0x01) + +#define MCF5282_QADC_DDRQB_DDQB3 (0x08) +#define MCF5282_QADC_DDRQB_DDQB2 (0x04) +#define MCF5282_QADC_DDRQB_DDQB1 (0x02) +#define MCF5282_QADC_DDRQB_DDQB0 (0x01) + +#define MCF5282_QADC_QACR0_MUX (0x8000) +#define MCF5282_QADC_QACR0_TRG (0x1000) +#define MCF5282_QADC_QACR0_QPR(x) (((x)&0x007F)) + +#define MCF5282_QADC_QACRx_CIE (0x8000) +#define MCF5282_QADC_QACRx_PIE (0x4000) +#define MCF5282_QADC_QACRx_SSE (0x2000) +#define MCF5282_QADC_QACRx_MQ(x) (((x)&0x001F)<<8) +#define MCF5282_QADC_QACRx_RESUME (0x0080) +#define MCF5282_QADC_QACRx_BQ(x) (((x)&0x007F)) + +#define MCF5282_QADC_QASR0_CF1 (0x8000) +#define MCF5282_QADC_QASR0_PF1 (0x4000) +#define MCF5282_QADC_QASR0_CF2 (0x2000) +#define MCF5282_QADC_QASR0_PF2 (0x1000) +#define MCF5282_QADC_QASR0_TOR1 (0x0800) +#define MCF5282_QADC_QASR0_TOR2 (0x0400) + +#define MCF5282_QADC_CCW_P (0x0200) +#define MCF5282_QADC_CCW_BYP (0x0100) +#define MCF5282_QADC_CCW_IST(x) (((x)&0x0003)<<14) +#define MCF5282_QADC_CCW_CHAN(x) (((x)&0x003F)) + +/********************************************************************* +* +* General Purpose Timer (GPT) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_GPTA_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000])) +#define MCF5282_GPTA_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001])) +#define MCF5282_GPTA_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002])) +#define MCF5282_GPTA_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003])) +#define MCF5282_GPTA_GPTCNT (*(vuint16 *)(&__IPSBAR[0x1A0004])) +#define MCF5282_GPTA_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006])) +#define MCF5282_GPTA_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008])) +#define MCF5282_GPTA_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009])) +#define MCF5282_GPTA_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B])) +#define MCF5282_GPTA_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C])) +#define MCF5282_GPTA_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D])) +#define MCF5282_GPTA_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E])) +#define MCF5282_GPTA_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F])) +#define MCF5282_GPTA_GPTC0 (*(vuint16 *)(&__IPSBAR[0x1A0010])) +#define MCF5282_GPTA_GPTC1 (*(vuint16 *)(&__IPSBAR[0x1A0012])) +#define MCF5282_GPTA_GPTC2 (*(vuint16 *)(&__IPSBAR[0x1A0014])) +#define MCF5282_GPTA_GPTC3 (*(vuint16 *)(&__IPSBAR[0x1A0016])) +#define MCF5282_GPTA_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018])) +#define MCF5282_GPTA_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019])) +#define MCF5282_GPTA_GPTPACNT (*(vuint16 *)(&__IPSBAR[0x1A001A])) +#define MCF5282_GPTA_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D])) +#define MCF5282_GPTA_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E])) + +#define MCF5282_GPTB_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1B0000])) +#define MCF5282_GPTB_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1B0001])) +#define MCF5282_GPTB_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1B0002])) +#define MCF5282_GPTB_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1B0003])) +#define MCF5282_GPTB_GPTCNT (*(vuint16 *)(&__IPSBAR[0x1B0004])) +#define MCF5282_GPTB_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1B0006])) +#define MCF5282_GPTB_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1B0008])) +#define MCF5282_GPTB_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1B0009])) +#define MCF5282_GPTB_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1B000B])) +#define MCF5282_GPTB_GPTIE (*(vuint8 *)(&__IPSBAR[0x1B000C])) +#define MCF5282_GPTB_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1B000D])) +#define MCF5282_GPTB_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1B000E])) +#define MCF5282_GPTB_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1B000F])) +#define MCF5282_GPTB_GPTC0 (*(vuint16 *)(&__IPSBAR[0x1B0010])) +#define MCF5282_GPTB_GPTC1 (*(vuint16 *)(&__IPSBAR[0x1B0012])) +#define MCF5282_GPTB_GPTC2 (*(vuint16 *)(&__IPSBAR[0x1B0014])) +#define MCF5282_GPTB_GPTC3 (*(vuint16 *)(&__IPSBAR[0x1B0016])) +#define MCF5282_GPTB_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1B0018])) +#define MCF5282_GPTB_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1B0019])) +#define MCF5282_GPTB_GPTPACNT (*(vuint16 *)(&__IPSBAR[0x1B001A])) +#define MCF5282_GPTB_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1B001D])) +#define MCF5282_GPTB_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1B001E])) + +/* Bit level definitions and macros */ +#define MCF5282_GPT_GPTIOS_IOS3 (0x08) +#define MCF5282_GPT_GPTIOS_IOS2 (0x04) +#define MCF5282_GPT_GPTIOS_IOS1 (0x02) +#define MCF5282_GPT_GPTIOS_IOS0 (0x01) + +#define MCF5282_GPT_GPTCFORC_FOC3 (0x08) +#define MCF5282_GPT_GPTCFORC_FOC2 (0x04) +#define MCF5282_GPT_GPTCFORC_FOC1 (0x02) +#define MCF5282_GPT_GPTCFORC_FOC0 (0x01) + +#define MCF5282_GPT_GPTOC3M_OC3M3 (0x08) +#define MCF5282_GPT_GPTOC3M_OC3M2 (0x04) +#define MCF5282_GPT_GPTOC3M_OC3M1 (0x02) +#define MCF5282_GPT_GPTOC3M_OC3M0 (0x01) + +#define MCF5282_GPT_GPTOC3M_OC3D(x) (((x)&0x04)) + +#define MCF5282_GPT_GPTSCR1_GPTEN (0x80) +#define MCF5282_GPT_GPTSCR1_TFFCA (0x10) + +#define MCF5282_GPT_GPTTOV3 (0x08) +#define MCF5282_GPT_GPTTOV2 (0x04) +#define MCF5282_GPT_GPTTOV1 (0x02) +#define MCF5282_GPT_GPTTOV0 (0x01) + +#define MCF5282_GPT_GPTCTL_OMOL3(x) (((x)&0x03)<<6) +#define MCF5282_GPT_GPTCTL_OMOL2(x) (((x)&0x03)<<4) +#define MCF5282_GPT_GPTCTL_OMOL1(x) (((x)&0x03)<<2) +#define MCF5282_GPT_GPTCTL_OMOL0(x) (((x)&0x03)) + +#define MCF5282_GPT_GPTCTL2_EDG3(x) (((x)&0x03)<<6) +#define MCF5282_GPT_GPTCTL2_EDG2(x) (((x)&0x03)<<4) +#define MCF5282_GPT_GPTCTL2_EDG1(x) (((x)&0x03)<<2) +#define MCF5282_GPT_GPTCTL2_EDG0(x) (((x)&0x03)) + +#define MCF5282_GPT_GPTIE_C3I (0x08) +#define MCF5282_GPT_GPTIE_C2I (0x04) +#define MCF5282_GPT_GPTIE_C1I (0x02) +#define MCF5282_GPT_GPTIE_C0I (0x01) + +#define MCF5282_GPT_GPTSCR2_TOI (0x80) +#define MCF5282_GPT_GPTSCR2_PUPT (0x20) +#define MCF5282_GPT_GPTSCR2_RDPT (0x10) +#define MCF5282_GPT_GPTSCR2_TCRE (0x08) +#define MCF5282_GPT_GPTSCR2_PR(x) (((x)&0x07)) + +#define MCF5282_GPT_GPTFLG1_C3F (0x08) +#define MCF5282_GPT_GPTFLG1_C2F (0x04) +#define MCF5282_GPT_GPTFLG1_C1F (0x02) +#define MCF5282_GPT_GPTFLG1_C0F (0x01) + +#define MCF5282_GPT_GPTFLG2_TOF (0x80) +#define MCF5282_GPT_GPTFLG2_C3F (0x08) +#define MCF5282_GPT_GPTFLG2_C2F (0x04) +#define MCF5282_GPT_GPTFLG2_C1F (0x02) +#define MCF5282_GPT_GPTFLG2_C0F (0x01) + +#define MCF5282_GPT_GPTPACTL_PAE (0x40) +#define MCF5282_GPT_GPTPACTL_PAMOD (0x20) +#define MCF5282_GPT_GPTPACTL_PEDGE (0x10) +#define MCF5282_GPT_GPTPACTL_CLK_PACLK (0x04) +#define MCF5282_GPT_GPTPACTL_CLK_PACLK256 (0x08) +#define MCF5282_GPT_GPTPACTL_CLK_PACLK65536 (0x0C) +#define MCF5282_GPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) +#define MCF5282_GPT_GPTPACTL_PAOVI (0x02) +#define MCF5282_GPT_GPTPACTL_PAI (0x01) + +#define MCF5282_GPT_GPTPAFLG_PAOVF (0x02) +#define MCF5282_GPT_GPTPAFLG_PAIF (0x01) + +#define MCF5282_GPT_GPTPORT_PORTT3 (0x08) +#define MCF5282_GPT_GPTPORT_PORTT2 (0x04) +#define MCF5282_GPT_GPTPORT_PORTT1 (0x02) +#define MCF5282_GPT_GPTPORT_PORTT0 (0x01) + +#define MCF5282_GPT_GPTDDR_DDRT3 (0x08) +#define MCF5282_GPT_GPTDDR_DDRT2 (0x04) +#define MCF5282_GPT_GPTDDR_DDRT1 (0x02) +#define MCF5282_GPT_GPTDDR_DDRT0 (0x01) + +/********************************************************************* +* +* FlexCAN Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_FLEXCAN_CANMCR (*(vuint16 *)(&__IPSBAR[0x1C0000])) +#define MCF5282_FLEXCAN_CANCTRL0 (*(vuint8 *)(&__IPSBAR[0x1C0006])) +#define MCF5282_FLEXCAN_CANCTRL1 (*(vuint8 *)(&__IPSBAR[0x1C0007])) +#define MCF5282_FLEXCAN_PRESDIV (*(vuint8 *)(&__IPSBAR[0x1C0008])) +#define MCF5282_FLEXCAN_CANCTRL2 (*(vuint8 *)(&__IPSBAR[0x1C0009])) +#define MCF5282_FLEXCAN_TIMER (*(vuint16 *)(&__IPSBAR[0x1C000A])) +#define MCF5282_FLEXCAN_RXGMASK (*(vuint32 *)(&__IPSBAR[0x1C0010])) +#define MCF5282_FLEXCAN_RX14MASK (*(vuint32 *)(&__IPSBAR[0x1C0014])) +#define MCF5282_FLEXCAN_RX15MASK (*(vuint32 *)(&__IPSBAR[0x1C0018])) +#define MCF5282_FLEXCAN_ESTAT (*(vuint16 *)(&__IPSBAR[0x1C0020])) +#define MCF5282_FLEXCAN_IMASK (*(vuint16 *)(&__IPSBAR[0x1C0022])) +#define MCF5282_FLEXCAN_IFLAG (*(vuint16 *)(&__IPSBAR[0x1C0024])) +#define MCF5282_FLEXCAN_RXECTR (*(vuint8 *)(&__IPSBAR[0x1C0026])) +#define MCF5282_FLEXCAN_TXECTR (*(vuint8 *)(&__IPSBAR[0x1C0027])) +#define MCF5282_FLEXCAN_MBUF0_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0081])) +#define MCF5282_FLEXCAN_MBUF0_IDH (*(vuint16 *)(&__IPSBAR[0x1C0082])) +#define MCF5282_FLEXCAN_MBUF0_IDL (*(vuint16 *)(&__IPSBAR[0x1C0084])) +#define MCF5282_FLEXCAN_MBUF0_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0086])) +#define MCF5282_FLEXCAN_MBUF0_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0087])) +#define MCF5282_FLEXCAN_MBUF0_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0088])) +#define MCF5282_FLEXCAN_MBUF0_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0089])) +#define MCF5282_FLEXCAN_MBUF0_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C008A])) +#define MCF5282_FLEXCAN_MBUF0_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C008B])) +#define MCF5282_FLEXCAN_MBUF0_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C008C])) +#define MCF5282_FLEXCAN_MBUF0_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C008D])) +#define MCF5282_FLEXCAN_MBUF1_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0091])) +#define MCF5282_FLEXCAN_MBUF1_IDH (*(vuint16 *)(&__IPSBAR[0x1C0092])) +#define MCF5282_FLEXCAN_MBUF1_IDL (*(vuint16 *)(&__IPSBAR[0x1C0094])) +#define MCF5282_FLEXCAN_MBUF1_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0096])) +#define MCF5282_FLEXCAN_MBUF1_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0097])) +#define MCF5282_FLEXCAN_MBUF1_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0098])) +#define MCF5282_FLEXCAN_MBUF1_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0099])) +#define MCF5282_FLEXCAN_MBUF1_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C009A])) +#define MCF5282_FLEXCAN_MBUF1_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C009B])) +#define MCF5282_FLEXCAN_MBUF1_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C009C])) +#define MCF5282_FLEXCAN_MBUF1_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C009D])) +#define MCF5282_FLEXCAN_MBUF2_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00A1])) +#define MCF5282_FLEXCAN_MBUF2_IDH (*(vuint16 *)(&__IPSBAR[0x1C00A2])) +#define MCF5282_FLEXCAN_MBUF2_IDL (*(vuint16 *)(&__IPSBAR[0x1C00A4])) +#define MCF5282_FLEXCAN_MBUF2_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00A6])) +#define MCF5282_FLEXCAN_MBUF2_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00A7])) +#define MCF5282_FLEXCAN_MBUF2_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00A8])) +#define MCF5282_FLEXCAN_MBUF2_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00A9])) +#define MCF5282_FLEXCAN_MBUF2_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00AA])) +#define MCF5282_FLEXCAN_MBUF2_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00AB])) +#define MCF5282_FLEXCAN_MBUF2_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00AC])) +#define MCF5282_FLEXCAN_MBUF2_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00AD])) +#define MCF5282_FLEXCAN_MBUF3_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00B1])) +#define MCF5282_FLEXCAN_MBUF3_IDH (*(vuint16 *)(&__IPSBAR[0x1C00B2])) +#define MCF5282_FLEXCAN_MBUF3_IDL (*(vuint16 *)(&__IPSBAR[0x1C00B4])) +#define MCF5282_FLEXCAN_MBUF3_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00B6])) +#define MCF5282_FLEXCAN_MBUF3_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00B7])) +#define MCF5282_FLEXCAN_MBUF3_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00B8])) +#define MCF5282_FLEXCAN_MBUF3_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00B9])) +#define MCF5282_FLEXCAN_MBUF3_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00BA])) +#define MCF5282_FLEXCAN_MBUF3_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00BB])) +#define MCF5282_FLEXCAN_MBUF3_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00BC])) +#define MCF5282_FLEXCAN_MBUF3_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00BD])) +#define MCF5282_FLEXCAN_MBUF4_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00C1])) +#define MCF5282_FLEXCAN_MBUF4_IDH (*(vuint16 *)(&__IPSBAR[0x1C00C2])) +#define MCF5282_FLEXCAN_MBUF4_IDL (*(vuint16 *)(&__IPSBAR[0x1C00C4])) +#define MCF5282_FLEXCAN_MBUF4_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00C6])) +#define MCF5282_FLEXCAN_MBUF4_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00C7])) +#define MCF5282_FLEXCAN_MBUF4_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00C8])) +#define MCF5282_FLEXCAN_MBUF4_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00C9])) +#define MCF5282_FLEXCAN_MBUF4_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00CA])) +#define MCF5282_FLEXCAN_MBUF4_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00CB])) +#define MCF5282_FLEXCAN_MBUF4_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00CC])) +#define MCF5282_FLEXCAN_MBUF4_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00CD])) +#define MCF5282_FLEXCAN_MBUF5_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00D1])) +#define MCF5282_FLEXCAN_MBUF5_IDH (*(vuint16 *)(&__IPSBAR[0x1C00D2])) +#define MCF5282_FLEXCAN_MBUF5_IDL (*(vuint16 *)(&__IPSBAR[0x1C00D4])) +#define MCF5282_FLEXCAN_MBUF5_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00D6])) +#define MCF5282_FLEXCAN_MBUF5_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00D7])) +#define MCF5282_FLEXCAN_MBUF5_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00D8])) +#define MCF5282_FLEXCAN_MBUF5_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00D9])) +#define MCF5282_FLEXCAN_MBUF5_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00DA])) +#define MCF5282_FLEXCAN_MBUF5_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00DB])) +#define MCF5282_FLEXCAN_MBUF5_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00DC])) +#define MCF5282_FLEXCAN_MBUF5_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00DD])) +#define MCF5282_FLEXCAN_MBUF6_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00E1])) +#define MCF5282_FLEXCAN_MBUF6_IDH (*(vuint16 *)(&__IPSBAR[0x1C00E2])) +#define MCF5282_FLEXCAN_MBUF6_IDL (*(vuint16 *)(&__IPSBAR[0x1C00E4])) +#define MCF5282_FLEXCAN_MBUF6_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00E6])) +#define MCF5282_FLEXCAN_MBUF6_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00E7])) +#define MCF5282_FLEXCAN_MBUF6_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00E8])) +#define MCF5282_FLEXCAN_MBUF6_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00E9])) +#define MCF5282_FLEXCAN_MBUF6_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00EA])) +#define MCF5282_FLEXCAN_MBUF6_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00EB])) +#define MCF5282_FLEXCAN_MBUF6_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00EC])) +#define MCF5282_FLEXCAN_MBUF6_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00ED])) +#define MCF5282_FLEXCAN_MBUF7_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00F1])) +#define MCF5282_FLEXCAN_MBUF7_IDH (*(vuint16 *)(&__IPSBAR[0x1C00F2])) +#define MCF5282_FLEXCAN_MBUF7_IDL (*(vuint16 *)(&__IPSBAR[0x1C00F4])) +#define MCF5282_FLEXCAN_MBUF7_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00F6])) +#define MCF5282_FLEXCAN_MBUF7_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00F7])) +#define MCF5282_FLEXCAN_MBUF7_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00F8])) +#define MCF5282_FLEXCAN_MBUF7_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00F9])) +#define MCF5282_FLEXCAN_MBUF7_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00FA])) +#define MCF5282_FLEXCAN_MBUF7_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00FB])) +#define MCF5282_FLEXCAN_MBUF7_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00FC])) +#define MCF5282_FLEXCAN_MBUF7_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00FD])) +#define MCF5282_FLEXCAN_MBUF8_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0101])) +#define MCF5282_FLEXCAN_MBUF8_IDH (*(vuint16 *)(&__IPSBAR[0x1C0102])) +#define MCF5282_FLEXCAN_MBUF8_IDL (*(vuint16 *)(&__IPSBAR[0x1C0104])) +#define MCF5282_FLEXCAN_MBUF8_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0106])) +#define MCF5282_FLEXCAN_MBUF8_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0107])) +#define MCF5282_FLEXCAN_MBUF8_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0108])) +#define MCF5282_FLEXCAN_MBUF8_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0109])) +#define MCF5282_FLEXCAN_MBUF8_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C010A])) +#define MCF5282_FLEXCAN_MBUF8_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C010B])) +#define MCF5282_FLEXCAN_MBUF8_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C010C])) +#define MCF5282_FLEXCAN_MBUF8_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C010D])) +#define MCF5282_FLEXCAN_MBUF9_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0111])) +#define MCF5282_FLEXCAN_MBUF9_IDH (*(vuint16 *)(&__IPSBAR[0x1C0112])) +#define MCF5282_FLEXCAN_MBUF9_IDL (*(vuint16 *)(&__IPSBAR[0x1C0114])) +#define MCF5282_FLEXCAN_MBUF9_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0116])) +#define MCF5282_FLEXCAN_MBUF9_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0117])) +#define MCF5282_FLEXCAN_MBUF9_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0118])) +#define MCF5282_FLEXCAN_MBUF9_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0119])) +#define MCF5282_FLEXCAN_MBUF9_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C011A])) +#define MCF5282_FLEXCAN_MBUF9_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C011B])) +#define MCF5282_FLEXCAN_MBUF9_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C011C])) +#define MCF5282_FLEXCAN_MBUF9_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C011D])) +#define MCF5282_FLEXCAN_MBUF10_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0121])) +#define MCF5282_FLEXCAN_MBUF10_IDH (*(vuint16 *)(&__IPSBAR[0x1C0122])) +#define MCF5282_FLEXCAN_MBUF10_IDL (*(vuint16 *)(&__IPSBAR[0x1C0124])) +#define MCF5282_FLEXCAN_MBUF10_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0126])) +#define MCF5282_FLEXCAN_MBUF10_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0127])) +#define MCF5282_FLEXCAN_MBUF10_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0128])) +#define MCF5282_FLEXCAN_MBUF10_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0129])) +#define MCF5282_FLEXCAN_MBUF10_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C012A])) +#define MCF5282_FLEXCAN_MBUF10_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C012B])) +#define MCF5282_FLEXCAN_MBUF10_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C012C])) +#define MCF5282_FLEXCAN_MBUF10_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C012D])) +#define MCF5282_FLEXCAN_MBUF11_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0131])) +#define MCF5282_FLEXCAN_MBUF11_IDH (*(vuint16 *)(&__IPSBAR[0x1C0132])) +#define MCF5282_FLEXCAN_MBUF11_IDL (*(vuint16 *)(&__IPSBAR[0x1C0134])) +#define MCF5282_FLEXCAN_MBUF11_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0136])) +#define MCF5282_FLEXCAN_MBUF11_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0137])) +#define MCF5282_FLEXCAN_MBUF11_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0138])) +#define MCF5282_FLEXCAN_MBUF11_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0139])) +#define MCF5282_FLEXCAN_MBUF11_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C013A])) +#define MCF5282_FLEXCAN_MBUF11_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C013B])) +#define MCF5282_FLEXCAN_MBUF11_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C013C])) +#define MCF5282_FLEXCAN_MBUF11_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C013D])) +#define MCF5282_FLEXCAN_MBUF12_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0141])) +#define MCF5282_FLEXCAN_MBUF12_IDH (*(vuint16 *)(&__IPSBAR[0x1C0142])) +#define MCF5282_FLEXCAN_MBUF12_IDL (*(vuint16 *)(&__IPSBAR[0x1C0144])) +#define MCF5282_FLEXCAN_MBUF12_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0146])) +#define MCF5282_FLEXCAN_MBUF12_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0147])) +#define MCF5282_FLEXCAN_MBUF12_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0148])) +#define MCF5282_FLEXCAN_MBUF12_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0149])) +#define MCF5282_FLEXCAN_MBUF12_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C014A])) +#define MCF5282_FLEXCAN_MBUF12_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C014B])) +#define MCF5282_FLEXCAN_MBUF12_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C014C])) +#define MCF5282_FLEXCAN_MBUF12_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C014D])) +#define MCF5282_FLEXCAN_MBUF13_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0151])) +#define MCF5282_FLEXCAN_MBUF13_IDH (*(vuint16 *)(&__IPSBAR[0x1C0152])) +#define MCF5282_FLEXCAN_MBUF13_IDL (*(vuint16 *)(&__IPSBAR[0x1C0154])) +#define MCF5282_FLEXCAN_MBUF13_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0156])) +#define MCF5282_FLEXCAN_MBUF13_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0157])) +#define MCF5282_FLEXCAN_MBUF13_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0158])) +#define MCF5282_FLEXCAN_MBUF13_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0159])) +#define MCF5282_FLEXCAN_MBUF13_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C015A])) +#define MCF5282_FLEXCAN_MBUF13_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C015B])) +#define MCF5282_FLEXCAN_MBUF13_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C015C])) +#define MCF5282_FLEXCAN_MBUF13_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C015D])) +#define MCF5282_FLEXCAN_MBUF14_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0161])) +#define MCF5282_FLEXCAN_MBUF14_IDH (*(vuint16 *)(&__IPSBAR[0x1C0162])) +#define MCF5282_FLEXCAN_MBUF14_IDL (*(vuint16 *)(&__IPSBAR[0x1C0164])) +#define MCF5282_FLEXCAN_MBUF14_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0166])) +#define MCF5282_FLEXCAN_MBUF14_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0167])) +#define MCF5282_FLEXCAN_MBUF14_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0168])) +#define MCF5282_FLEXCAN_MBUF14_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0169])) +#define MCF5282_FLEXCAN_MBUF14_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C016A])) +#define MCF5282_FLEXCAN_MBUF14_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C016B])) +#define MCF5282_FLEXCAN_MBUF14_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C016C])) +#define MCF5282_FLEXCAN_MBUF14_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C016D])) +#define MCF5282_FLEXCAN_MBUF15_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0171])) +#define MCF5282_FLEXCAN_MBUF15_IDH (*(vuint16 *)(&__IPSBAR[0x1C0172])) +#define MCF5282_FLEXCAN_MBUF15_IDL (*(vuint16 *)(&__IPSBAR[0x1C0174])) +#define MCF5282_FLEXCAN_MBUF15_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0176])) +#define MCF5282_FLEXCAN_MBUF15_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0177])) +#define MCF5282_FLEXCAN_MBUF15_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0178])) +#define MCF5282_FLEXCAN_MBUF15_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0179])) +#define MCF5282_FLEXCAN_MBUF15_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C017A])) +#define MCF5282_FLEXCAN_MBUF15_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C017B])) +#define MCF5282_FLEXCAN_MBUF15_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C017C])) +#define MCF5282_FLEXCAN_MBUF15_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C017D])) + +#define MCF5282_FLEXCAN_MBUF0_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0086+(x))])) +#define MCF5282_FLEXCAN_MBUF1_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0096+(x))])) +#define MCF5282_FLEXCAN_MBUF2_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00A6+(x))])) +#define MCF5282_FLEXCAN_MBUF3_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00B6+(x))])) +#define MCF5282_FLEXCAN_MBUF4_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00C6+(x))])) +#define MCF5282_FLEXCAN_MBUF5_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00D6+(x))])) +#define MCF5282_FLEXCAN_MBUF6_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00E6+(x))])) +#define MCF5282_FLEXCAN_MBUF7_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00F6+(x))])) +#define MCF5282_FLEXCAN_MBUF8_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0106+(x))])) +#define MCF5282_FLEXCAN_MBUF9_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0116+(x))])) +#define MCF5282_FLEXCAN_MBUF10_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0126+(x))])) +#define MCF5282_FLEXCAN_MBUF11_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0136+(x))])) +#define MCF5282_FLEXCAN_MBUF12_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0146+(x))])) +#define MCF5282_FLEXCAN_MBUF13_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0156+(x))])) +#define MCF5282_FLEXCAN_MBUF14_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0166+(x))])) +#define MCF5282_FLEXCAN_MBUF15_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0176+(x))])) + +#define MCF5282_FLEXCAN_MBUF_BYTE(x,y) (*(vuint8 *)(&__IPSBAR[((0x1C0086+(0x10*(x))+(y))])) + +/* Bit level definitions and macros */ +#define MCF5282_FLEXCAN_CANMCR_STOP (0x8000) +#define MCF5282_FLEXCAN_CANMCR_FRZ (0x4000) +#define MCF5282_FLEXCAN_CANMCR_HALT (0x1000) +#define MCF5282_FLEXCAN_CANMCR_NOTRDY (0x0800) +#define MCF5282_FLEXCAN_CANMCR_WAKEMSK (0x0400) +#define MCF5282_FLEXCAN_CANMCR_SOFTRST (0x0200) +#define MCF5282_FLEXCAN_CANMCR_FRZACK (0x0100) +#define MCF5282_FLEXCAN_CANMCR_SUPV (0x0080) +#define MCF5282_FLEXCAN_CANMCR_SELFWAKE (0x0040) +#define MCF5282_FLEXCAN_CANMCR_APS (0x0020) + +#define MCF5282_FLEXCAN_CANCTRL0_BOFFMSK (0x80) +#define MCF5282_FLEXCAN_CANCTRL0_ERRMSK (0x40) +#define MCF5282_FLEXCAN_CANCTRL0_RXMODE (0x04) +#define MCF5282_FLEXCAN_CANCTRL0_TXMODE_CMOSPOS (0x00) +#define MCF5282_FLEXCAN_CANCTRL0_TXMODE_CMOSNEG (0x01) +#define MCF5282_FLEXCAN_CANCTRL0_TXMODE_OPENDRAIN (0x02) + +#define MCF5282_FLEXCAN_CANCTRL1_SAMP (0x80) +#define MCF5282_FLEXCAN_CANCTRL1_TSYNC (0x20) +#define MCF5282_FLEXCAN_CANCTRL1_LBUF (0x10) +#define MCF5282_FLEXCAN_CANCTRL1_LOM (0x08) +#define MCF5282_FLEXCAN_CANCTRL1_PROPSEG(x) (((x)&0x07)) + +#define MCF5282_FLEXCAN_CANCTRL2_RJW(x) (((x)&0x03)<<6) +#define MCF5282_FLEXCAN_CANCTRL2_PSEG1(x) (((x)&0x07)<<3) +#define MCF5282_FLEXCAN_CANCTRL2_PSEG2(x) (((x)&0x07)<<0) + +#define MCF5282_FLEXCAN_ESTAT_BITERR(x) (((x)&0x03)<<14) +#define MCF5282_FLEXCAN_ESTAT_ACKERR (0x2000) +#define MCF5282_FLEXCAN_ESTAT_CRCERR (0x1000) +#define MCF5282_FLEXCAN_ESTAT_FORMERR (0x0800) +#define MCF5282_FLEXCAN_ESTAT_STUFFERR (0x0400) +#define MCF5282_FLEXCAN_ESTAT_TXWARN (0x0200) +#define MCF5282_FLEXCAN_ESTAT_RXWARN (0x0100) +#define MCF5282_FLEXCAN_ESTAT_IDLE (0x0080) +#define MCF5282_FLEXCAN_ESTAT_TXRX (0x0040) +#define MCF5282_FLEXCAN_ESTAT_FCS(x) (((x)&0x03)<<4) +#define MCF5282_FLEXCAN_ESTAT_BOFFINT (0x0004) +#define MCF5282_FLEXCAN_ESTAT_ERRINT (0x0002) +#define MCF5282_FLEXCAN_ESTAT_WAKEINT (0x0001) + +#define MCF5282_FLEXCAN_IMASK_BUF15M (0x8000) +#define MCF5282_FLEXCAN_IMASK_BUF14M (0x4000) +#define MCF5282_FLEXCAN_IMASK_BUF13M (0x2000) +#define MCF5282_FLEXCAN_IMASK_BUF12M (0x1000) +#define MCF5282_FLEXCAN_IMASK_BUF11M (0x0800) +#define MCF5282_FLEXCAN_IMASK_BUF10M (0x0400) +#define MCF5282_FLEXCAN_IMASK_BUF9M (0x0200) +#define MCF5282_FLEXCAN_IMASK_BUF8M (0x0100) +#define MCF5282_FLEXCAN_IMASK_BUF7M (0x0080) +#define MCF5282_FLEXCAN_IMASK_BUF6M (0x0040) +#define MCF5282_FLEXCAN_IMASK_BUF5M (0x0020) +#define MCF5282_FLEXCAN_IMASK_BUF4M (0x0010) +#define MCF5282_FLEXCAN_IMASK_BUF3M (0x0008) +#define MCF5282_FLEXCAN_IMASK_BUF2M (0x0004) +#define MCF5282_FLEXCAN_IMASK_BUF1M (0x0002) +#define MCF5282_FLEXCAN_IMASK_BUF0M (0x0001) + +#define MCF5282_FLEXCAN_IFLAG_BUF15I (0x8000) +#define MCF5282_FLEXCAN_IFLAG_BUF14I (0x4000) +#define MCF5282_FLEXCAN_IFLAG_BUF13I (0x2000) +#define MCF5282_FLEXCAN_IFLAG_BUF12I (0x1000) +#define MCF5282_FLEXCAN_IFLAG_BUF11I (0x0800) +#define MCF5282_FLEXCAN_IFLAG_BUF10I (0x0400) +#define MCF5282_FLEXCAN_IFLAG_BUF9I (0x0200) +#define MCF5282_FLEXCAN_IFLAG_BUF8I (0x0100) +#define MCF5282_FLEXCAN_IFLAG_BUF7I (0x0080) +#define MCF5282_FLEXCAN_IFLAG_BUF6I (0x0040) +#define MCF5282_FLEXCAN_IFLAG_BUF5I (0x0020) +#define MCF5282_FLEXCAN_IFLAG_BUF4I (0x0010) +#define MCF5282_FLEXCAN_IFLAG_BUF3I (0x0008) +#define MCF5282_FLEXCAN_IFLAG_BUF2I (0x0004) +#define MCF5282_FLEXCAN_IFLAG_BUF1I (0x0002) +#define MCF5282_FLEXCAN_IFLAG_BUF0I (0x0001) + +/********************************************************************* +* +* ColdFire Flash Module (CFM) +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_CFM_CFMMCR (*(vuint16 *)(&__IPSBAR[0x1D0000])) +#define MCF5282_CFM_CFMCLKD (*(vuint8 *)(&__IPSBAR[0x1D0002])) +#define MCF5282_CFM_CFMSEC (*(vuint32 *)(&__IPSBAR[0x1D0008])) +#define MCF5282_CFM_CFMPROT (*(vuint32 *)(&__IPSBAR[0x1D0010])) +#define MCF5282_CFM_CFMSACC (*(vuint32 *)(&__IPSBAR[0x1D0014])) +#define MCF5282_CFM_CFMDACC (*(vuint32 *)(&__IPSBAR[0x1D0018])) +#define MCF5282_CFM_CFMUSTAT (*(vuint8 *)(&__IPSBAR[0x1D0020])) +#define MCF5282_CFM_CFMCMD (*(vuint8 *)(&__IPSBAR[0x1D0024])) +#define MCF5282_CFM_CFMDISU (*(vuint16 *)(&__IPSBAR[0x1D0042])) + +/* Bit level definitions and macros */ +#define MCF5282_CFM_FLASHBAR_BA(a) ((a)&0xFFF8000) +#define MCF5282_CFM_FLASHBAR_WP (0x00000100) +#define MCF5282_CFM_FLASHBAR_CI (0x00000020) +#define MCF5282_CFM_FLASHBAR_SC (0x00000010) +#define MCF5282_CFM_FLASHBAR_SD (0x00000008) +#define MCF5282_CFM_FLASHBAR_UC (0x00000004) +#define MCF5282_CFM_FLASHBAR_UD (0x00000002) +#define MCF5282_CFM_FLASHBAR_V (0x00000001) + +#define MCF5282_CFM_CFMMCR_LOCK (0x0400) +#define MCF5282_CFM_CFMMCR_PVIE (0x0200) +#define MCF5282_CFM_CFMMCR_AEIE (0x0100) +#define MCF5282_CFM_CFMMCR_CBEIE (0x0080) +#define MCF5282_CFM_CFMMCR_CCIE (0x0040) +#define MCF5282_CFM_CFMMCR_KEYACC (0x0020) + +#define MCF5282_CFM_CFMCLKD_DIVLD (0x80) +#define MCF5282_CFM_CFMCLKD_PRDIV8 (0x40) +#define MCF5282_CFM_CFMCLKD_DIV(x) (((x)&0x3F)) + +#define MCF5282_CFM_CFMSEC_KEYEN (0x80000000) +#define MCF5282_CFM_CFMSEC_SECSTAT (0x40000000) +#define MCF5282_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)) + +#define MCF5282_CFM_CFMUSTAT_CBEIF (0x80) +#define MCF5282_CFM_CFMUSTAT_CCIF (0x40) +#define MCF5282_CFM_CFMUSTAT_PVIOL (0x20) +#define MCF5282_CFM_CFMUSTAT_ACCERR (0x10) +#define MCF5282_CFM_CFMUSTAT_BLANK (0x04) + +#define MCF5282_CFM_CFMCMD_CMD(x) (((x)&0x7F)) + +/********************************************************************/ + +#endif /* _CPU_MCF5282_H */ diff --git a/bsps/m68k/include/mcf532x/mcf532x.h b/bsps/m68k/include/mcf532x/mcf532x.h new file mode 100644 index 0000000000..798fb1175b --- /dev/null +++ b/bsps/m68k/include/mcf532x/mcf532x.h @@ -0,0 +1,4483 @@ +/* + * File: mcf532x.h + * Purpose: Register and bit definitions + */ + +#ifndef __MCF532X_H__ +#define __MCF532X_H__ + +/********************************************************************* +* +* Cache +* +*********************************************************************/ + +#define MCF_CACR_CENB (1 << 31) +#define MCF_CACR_ESB (1 << 29) +#define MCF_CACR_DPI (1 << 28) +#define MCF_CACR_HLCK (1 << 27) +#define MCF_CACR_CINVA (1 << 24) +#define MCF_CACR_DNFB (1 << 10) +#define MCF_CACR_DCM(A) (((A) & 0x3) << 8) +#define MCF_CACR_DW (1 << 5) +#define MCF_CACR_EUSP (1 << 4) + +#define MCF_ACR_ADDR_BASE(A) (((A) & 0xFF) << 24) +#define MCF_ACR_ADDR_MASK(A) (((A) & 0xFF) << 16) +#define MCF_ACR_E (1 << 15) +#define MCF_ACR_S(A) (((A) & 0x3) << 13) +#define MCF_ACR_CM(A) (((A) & 0x3) << 5) +#define MCF_ACR_W (1 << 2) + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SCM_MPR0 (*(vuint32*)(0xEC000000)) +#define MCF_SCM_MPR1 (*(vuint32*)(0xFC000000)) +#define MCF_SCM_BMT0 (*(vuint32*)(0xEC000054)) +#define MCF_SCM_BMT1 (*(vuint32*)(0xFC000054)) +#define MCF_SCM_PACRA (*(vuint32*)(0xFC000020)) +#define MCF_SCM_PACRB (*(vuint32*)(0xFC000024)) +#define MCF_SCM_PACRC (*(vuint32*)(0xFC000028)) +#define MCF_SCM_PACRD (*(vuint32*)(0xFC00002C)) +#define MCF_SCM_PACRE (*(vuint32*)(0xFC000040)) +#define MCF_SCM_PACRF (*(vuint32*)(0xFC000044)) +#define MCF_SCM_PACRG (*(vuint32*)(0xEC000048)) +#define MCF_SCM_PACRH (*(vuint32*)(0xEC000040)) +#define MCF_SCM_CWCR (*(vuint16*)(0xFC040016)) +#define MCF_SCM_CWSR (*(vuint8 *)(0xFC04001B)) +#define MCF_SCM_CWIR (*(vuint8 *)(0xFC04001F)) +#define MCF_SCM_BCR (*(vuint32*)(0xFC040024)) +#define MCF_SCM_CFADR (*(vuint32*)(0xFC040070)) +#define MCF_SCM_CFIER (*(vuint8 *)(0xFC040075)) +#define MCF_SCM_CFLOC (*(vuint8 *)(0xFC040076)) +#define MCF_SCM_CFATR (*(vuint8 *)(0xFC040077)) +#define MCF_SCM_CFDTR (*(vuint32*)(0xFC04007C)) + +/* Bit definitions and macros for MCF_SCM_MPR */ +#define MCF_SCM_MPR_MPROT6(x) (((x)&0x0000000F)<<4) +#define MCF_SCM_MPR_MPROT5(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_MPR_MPROT4(x) (((x)&0x0000000F)<<12) +#define MCF_SCM_MPR_MPROT2(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_MPR_MPROT1(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_MPR_MPROT0(x) (((x)&0x0000000F)<<28) +#define MCF_SCM_MPR_MPROT_MTR (0x4) +#define MCF_SCM_MPR_MPROT_MTW (0x2) +#define MCF_SCM_MPR_MPROT_MPL (0x1) + +/* Bit definitions and macros for MCF_SCM_BMT */ +#define MCF_SCM_BMT_BMT(x) (((x)&0x00000007)<<0) +#define MCF_SCM_BMT_BME (0x00000008) +#define MCF_SCM_BMT_BMT_1024 (0x00000000) +#define MCF_SCM_BMT_BMT_512 (0x00000001) +#define MCF_SCM_BMT_BMT_256 (0x00000002) +#define MCF_SCM_BMT_BMT_128 (0x00000003) +#define MCF_SCM_BMT_BMT_64 (0x00000004) +#define MCF_SCM_BMT_BMT_32 (0x00000005) +#define MCF_SCM_BMT_BMT_16 (0x00000006) +#define MCF_SCM_BMT_BMT_8 (0x00000007) + +/* Bit definitions and macros for MCF_SCM_PACRA */ +#define MCF_SCM_PACRA_PACR2(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_PACRA_PACR1(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_PACRA_PACR0(x) (((x)&0x0000000F)<<28) +#define MCF_SCM_PACRA_PACR_SP (0x4) +#define MCF_SCM_PACRA_PACR_WP (0x2) +#define MCF_SCM_PACRA_PACR_TP (0x1) + +/* Bit definitions and macros for MCF_SCM_PACRB */ +#define MCF_SCM_PACRB_PACR12(x) (((x)&0x0000000F)<<12) +#define MCF_SCM_PACRB_PACR8(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_PACRC */ +#define MCF_SCM_PACRC_PACR23(x) (((x)&0x0000000F)<<0) +#define MCF_SCM_PACRC_PACR22(x) (((x)&0x0000000F)<<4) +#define MCF_SCM_PACRC_PACR21(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_PACRC_PACR19(x) (((x)&0x0000000F)<<16) +#define MCF_SCM_PACRC_PACR18(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_PACRC_PACR17(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_PACRC_PACR16(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_PACRD */ +#define MCF_SCM_PACRD_PACR31(x) (((x)&0x0000000F)<<0) +#define MCF_SCM_PACRD_PACR30(x) (((x)&0x0000000F)<<4) +#define MCF_SCM_PACRD_PACR29(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_PACRD_PACR28(x) (((x)&0x0000000F)<<12) +#define MCF_SCM_PACRD_PACR26(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_PACRD_PACR25(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_PACRD_PACR24(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_PACRE */ +#define MCF_SCM_PACRE_PACR38(x) (((x)&0x0000000F)<<4) +#define MCF_SCM_PACRE_PACR37(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_PACRE_PACR36(x) (((x)&0x0000000F)<<12) +#define MCF_SCM_PACRE_PACR35(x) (((x)&0x0000000F)<<16) +#define MCF_SCM_PACRE_PACR34(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_PACRE_PACR33(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_PACRE_PACR32(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_PACRF */ +#define MCF_SCM_PACRF_PACR47(x) (((x)&0x0000000F)<<0) +#define MCF_SCM_PACRF_PACR46(x) (((x)&0x0000000F)<<4) +#define MCF_SCM_PACRF_PACR45(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_PACRF_PACR44(x) (((x)&0x0000000F)<<12) +#define MCF_SCM_PACRF_PACR43(x) (((x)&0x0000000F)<<16) +#define MCF_SCM_PACRF_PACR42(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_PACRF_PACR41(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_PACRF_PACR40(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_PACRG */ +#define MCF_SCM_PACRG_PACR48(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_PACRH */ +#define MCF_SCM_PACRH_PACR58(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_PACRH_PACR57(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_PACRH_PACR56(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_CWCR */ +#define MCF_SCM_CWCR_CWT(x) (((x)&0x001F)<<0) +#define MCF_SCM_CWCR_CWRI(x) (((x)&0x0003)<<5) +#define MCF_SCM_CWCR_CWE (0x0080) +#define MCF_SCM_CWCR_CWR_WH (0x0100) +#define MCF_SCM_CWCR_RO (0x8000) +#define MCF_SCM_CWCR_CWRI_INT (0x0000) +#define MCF_SCM_CWCR_CWRI_INT_THEN_RESET (0x0020) +#define MCF_SCM_CWCR_CWRI_RESET (0x0040) +#define MCF_SCM_CWCR_CWRI_WINDOW (0x0060) + +/* Bit definitions and macros for MCF_SCM_CWSR */ +#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SCM_CWIR */ +#define MCF_SCM_CWIR_CWIC (0x01) +#define MCF_SCM_CWIR_CFEI (0x02) + +/* Bit definitions and macros for MCF_SCM_BCR */ +#define MCF_SCM_BCR_S1 (0x00000002) +#define MCF_SCM_BCR_S4 (0x00000010) +#define MCF_SCM_BCR_S6 (0x00000040) +#define MCF_SCM_BCR_S7 (0x00000080) +#define MCF_SCM_BCR_GBW (0x00000100) +#define MCF_SCM_BCR_GBR (0x00000200) + +/* Bit definitions and macros for MCF_SCM_CFADR */ +#define MCF_SCM_CFADR_ADDR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SCM_CFIER */ +#define MCF_SCM_CFIER_ECFEI (0x01) + +/* Bit definitions and macros for MCF_SCM_CFLOC */ +#define MCF_SCM_CFLOC_LOC (0x80) + +/* Bit definitions and macros for MCF_SCM_CFATR */ +#define MCF_SCM_CFATR_TYPE (0x01) +#define MCF_SCM_CFATR_MODE (0x02) +#define MCF_SCM_CFATR_CACHE (0x08) +#define MCF_SCM_CFATR_SIZE(x) (((x)&0x07)<<4) +#define MCF_SCM_CFATR_WRITE (0x80) + +/* Bit definitions and macros for MCF_SCM_CFDTR */ +#define MCF_SCM_CFDTR_CFDTR(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Message Digest Hardware Accelerator (MDHA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_MDHA_MDMR (*(vuint32*)(0xEC080000)) +#define MCF_MDHA_MDCR (*(vuint32*)(0xEC080004)) +#define MCF_MDHA_MDCMR (*(vuint32*)(0xEC080008)) +#define MCF_MDHA_MDSR (*(vuint32*)(0xEC08000C)) +#define MCF_MDHA_MDISR (*(vuint32*)(0xEC080010)) +#define MCF_MDHA_MDIMR (*(vuint32*)(0xEC080014)) +#define MCF_MDHA_MDDSR (*(vuint32*)(0xEC08001C)) +#define MCF_MDHA_MDIN (*(vuint32*)(0xEC080020)) +#define MCF_MDHA_MDA0 (*(vuint32*)(0xEC080030)) +#define MCF_MDHA_MDB0 (*(vuint32*)(0xEC080034)) +#define MCF_MDHA_MDC0 (*(vuint32*)(0xEC080038)) +#define MCF_MDHA_MDD0 (*(vuint32*)(0xEC08003C)) +#define MCF_MDHA_MDE0 (*(vuint32*)(0xEC080040)) +#define MCF_MDHA_MDMDS (*(vuint32*)(0xEC080044)) +#define MCF_MDHA_MDA1 (*(vuint32*)(0xEC080070)) +#define MCF_MDHA_MDB1 (*(vuint32*)(0xEC080074)) +#define MCF_MDHA_MDC1 (*(vuint32*)(0xEC080078)) +#define MCF_MDHA_MDD1 (*(vuint32*)(0xEC08007C)) +#define MCF_MDHA_MDE1 (*(vuint32*)(0xEC080080)) + +/* Bit definitions and macros for MCF_MDHA_MDMR */ +#define MCF_MDHA_MDMR_ALG (0x00000001) +#define MCF_MDHA_MDMR_PDATA (0x00000004) +#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3) +#define MCF_MDHA_MDMR_INIT (0x00000020) +#define MCF_MDHA_MDMR_IPAD (0x00000040) +#define MCF_MDHA_MDMR_OPAD (0x00000080) +#define MCF_MDHA_MDMR_SWAP (0x00000100) +#define MCF_MDHA_MDMR_MACFULL (0x00000200) +#define MCF_MDHA_MDMR_SSL (0x00000400) + +/* Bit definitions and macros for MCF_MDHA_MDCR */ +#define MCF_MDHA_MDCR_IE (0x00000001) +#define MCF_MDHA_MDCR_DMA (0x00000002) +#define MCF_MDHA_MDCR_ENDIAN (0x00000004) +#define MCF_MDHA_MDCR_DMAL(x) (((x)&0x0000001F)<<16) + +/* Bit definitions and macros for MCF_MDHA_MDCMR */ +#define MCF_MDHA_MDCMR_SWR (0x00000001) +#define MCF_MDHA_MDCMR_RI (0x00000002) +#define MCF_MDHA_MDCMR_CI (0x00000004) +#define MCF_MDHA_MDCMR_GO (0x00000008) + +/* Bit definitions and macros for MCF_MDHA_MDSR */ +#define MCF_MDHA_MDSR_INT (0x00000001) +#define MCF_MDHA_MDSR_DONE (0x00000002) +#define MCF_MDHA_MDSR_ERR (0x00000004) +#define MCF_MDHA_MDSR_RD (0x00000008) +#define MCF_MDHA_MDSR_BUSY (0x00000010) +#define MCF_MDHA_MDSR_END (0x00000020) +#define MCF_MDHA_MDSR_HSH (0x00000040) +#define MCF_MDHA_MDSR_GNW (0x00000080) +#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8) +#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13) +#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16) + +/* Bit definitions and macros for MCF_MDHA_MDISR */ +#define MCF_MDHA_MDISR_IFO (0x00000001) +#define MCF_MDHA_MDISR_NON (0x00000004) +#define MCF_MDHA_MDISR_IME (0x00000010) +#define MCF_MDHA_MDISR_IDS (0x00000020) +#define MCF_MDHA_MDISR_RMDP (0x00000080) +#define MCF_MDHA_MDISR_ERE (0x00000100) +#define MCF_MDHA_MDISR_GTDS (0x00000200) + +/* Bit definitions and macros for MCF_MDHA_MDIMR */ +#define MCF_MDHA_MDIMR_IFO (0x00000001) +#define MCF_MDHA_MDIMR_NON (0x00000004) +#define MCF_MDHA_MDIMR_IME (0x00000010) +#define MCF_MDHA_MDIMR_IDS (0x00000020) +#define MCF_MDHA_MDIMR_RMDP (0x00000080) +#define MCF_MDHA_MDIMR_ERE (0x00000100) +#define MCF_MDHA_MDIMR_GTDS (0x00000200) + +/* Bit definitions and macros for MCF_MDHA_MDDSR */ +#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDIN */ +#define MCF_MDHA_MDIN_DATAIN(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDA0 */ +#define MCF_MDHA_MDA0_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDB0 */ +#define MCF_MDHA_MDB0_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDC0 */ +#define MCF_MDHA_MDC0_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDD0 */ +#define MCF_MDHA_MDD0_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDE0 */ +#define MCF_MDHA_MDE0_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDMDS */ +#define MCF_MDHA_MDMDS_DATASIZE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDA1 */ +#define MCF_MDHA_MDA1_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDB1 */ +#define MCF_MDHA_MDB1_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDC1 */ +#define MCF_MDHA_MDC1_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDD1 */ +#define MCF_MDHA_MDD1_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDE1 */ +#define MCF_MDHA_MDE1_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Symmetric Key Hardware Accelerator (SKHA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SKHA_SKMR (*(vuint32*)(0xEC084000)) +#define MCF_SKHA_SKCR (*(vuint32*)(0xEC084004)) +#define MCF_SKHA_SKCMR (*(vuint32*)(0xEC084008)) +#define MCF_SKHA_SKSR (*(vuint32*)(0xEC08400C)) +#define MCF_SKHA_SKISR (*(vuint32*)(0xEC084010)) +#define MCF_SKHA_SKIMR (*(vuint32*)(0xEC084014)) +#define MCF_SKHA_SKKSR (*(vuint32*)(0xEC084018)) +#define MCF_SKHA_SKDSR (*(vuint32*)(0xEC08401C)) +#define MCF_SKHA_SKIN (*(vuint32*)(0xEC084020)) +#define MCF_SKHA_SKOUT (*(vuint32*)(0xEC084024)) +#define MCF_SKHA_SKK0 (*(vuint32*)(0xEC084030)) +#define MCF_SKHA_SKK1 (*(vuint32*)(0xEC084034)) +#define MCF_SKHA_SKK2 (*(vuint32*)(0xEC084038)) +#define MCF_SKHA_SKK3 (*(vuint32*)(0xEC08403C)) +#define MCF_SKHA_SKK4 (*(vuint32*)(0xEC084040)) +#define MCF_SKHA_SKK5 (*(vuint32*)(0xEC084044)) +#define MCF_SKHA_SKK(x) (*(vuint32*)(0xEC084030+((x)*0x004))) +#define MCF_SKHA_SKC0 (*(vuint32*)(0xEC084070)) +#define MCF_SKHA_SKC1 (*(vuint32*)(0xEC084074)) +#define MCF_SKHA_SKC2 (*(vuint32*)(0xEC084078)) +#define MCF_SKHA_SKC3 (*(vuint32*)(0xEC08407C)) +#define MCF_SKHA_SKC4 (*(vuint32*)(0xEC084080)) +#define MCF_SKHA_SKC5 (*(vuint32*)(0xEC084084)) +#define MCF_SKHA_SKC6 (*(vuint32*)(0xEC084088)) +#define MCF_SKHA_SKC7 (*(vuint32*)(0xEC08408C)) +#define MCF_SKHA_SKC8 (*(vuint32*)(0xEC084090)) +#define MCF_SKHA_SKC9 (*(vuint32*)(0xEC084094)) +#define MCF_SKHA_SKC10 (*(vuint32*)(0xEC084098)) +#define MCF_SKHA_SKC11 (*(vuint32*)(0xEC08409C)) +#define MCF_SKHA_SKC(x) (*(vuint32*)(0xEC084070+((x)*0x004))) + +/* Bit definitions and macros for MCF_SKHA_SKMR */ +#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0) +#define MCF_SKHA_SKMR_DIR (0x00000004) +#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3) +#define MCF_SKHA_SKMR_DKP (0x00000100) +#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9) +#define MCF_SKHA_SKMR_CM_ECB (0x00000000) +#define MCF_SKHA_SKMR_CM_CBC (0x00000008) +#define MCF_SKHA_SKMR_CM_CTR (0x00000018) +#define MCF_SKHA_SKMR_DIR_DEC (0x00000000) +#define MCF_SKHA_SKMR_DIR_ENC (0x00000004) +#define MCF_SKHA_SKMR_ALG_AES (0x00000000) +#define MCF_SKHA_SKMR_ALG_DES (0x00000001) +#define MCF_SKHA_SKMR_ALG_TDES (0x00000002) + +/* Bit definitions and macros for MCF_SKHA_SKCR */ +#define MCF_SKHA_SKCR_IE (0x00000001) +#define MCF_SKHA_SKCR_IDMA (0x00000002) +#define MCF_SKHA_SKCR_ODMA (0x00000004) +#define MCF_SKHA_SKCR_ENDIAN (0x00000008) +#define MCF_SKHA_SKCR_IDMAL(x) (((x)&0x0000003F)<<16) +#define MCF_SKHA_SKCR_ODMAL(x) (((x)&0x0000003F)<<24) + +/* Bit definitions and macros for MCF_SKHA_SKCMR */ +#define MCF_SKHA_SKCMR_SWR (0x00000001) +#define MCF_SKHA_SKCMR_RI (0x00000002) +#define MCF_SKHA_SKCMR_CI (0x00000004) +#define MCF_SKHA_SKCMR_GO (0x00000008) + +/* Bit definitions and macros for MCF_SKHA_SKSR */ +#define MCF_SKHA_SKSR_INT (0x00000001) +#define MCF_SKHA_SKSR_DONE (0x00000002) +#define MCF_SKHA_SKSR_ERR (0x00000004) +#define MCF_SKHA_SKSR_RD (0x00000008) +#define MCF_SKHA_SKSR_BUSY (0x00000010) +#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16) +#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_SKHA_SKISR */ +#define MCF_SKHA_SKISR_IFO (0x00000001) +#define MCF_SKHA_SKISR_OFU (0x00000002) +#define MCF_SKHA_SKISR_NEIF (0x00000004) +#define MCF_SKHA_SKISR_NEOF (0x00000008) +#define MCF_SKHA_SKISR_IME (0x00000010) +#define MCF_SKHA_SKISR_DSE (0x00000020) +#define MCF_SKHA_SKISR_KSE (0x00000040) +#define MCF_SKHA_SKISR_RMDP (0x00000080) +#define MCF_SKHA_SKISR_ERE (0x00000100) +#define MCF_SKHA_SKISR_KPE (0x00000200) +#define MCF_SKHA_SKISR_KRE (0x00000400) +#define MCF_SKHA_SKISR_DRL (0x00000800) + +/* Bit definitions and macros for MCF_SKHA_SKIMR */ +#define MCF_SKHA_SKIMR_IFO (0x00000001) +#define MCF_SKHA_SKIMR_OFU (0x00000002) +#define MCF_SKHA_SKIMR_NEIF (0x00000004) +#define MCF_SKHA_SKIMR_NEOF (0x00000008) +#define MCF_SKHA_SKIMR_IME (0x00000010) +#define MCF_SKHA_SKIMR_DSE (0x00000020) +#define MCF_SKHA_SKIMR_KSE (0x00000040) +#define MCF_SKHA_SKIMR_RMDP (0x00000080) +#define MCF_SKHA_SKIMR_ERE (0x00000100) +#define MCF_SKHA_SKIMR_KPE (0x00000200) +#define MCF_SKHA_SKIMR_KRE (0x00000400) +#define MCF_SKHA_SKIMR_DRL (0x00000800) + +/* Bit definitions and macros for MCF_SKHA_SKKSR */ +#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for MCF_SKHA_SKDSR */ +#define MCF_SKHA_SKDSR_DATASIZE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SKHA_SKIN */ +#define MCF_SKHA_SKIN_DATAIN(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SKHA_SKOUT */ +#define MCF_SKHA_SKOUT_DATAOUT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SKHA_SKK */ +#define MCF_SKHA_SKK_KEY(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SKHA_SKC */ +#define MCF_SKHA_SKC_CONTEXT(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Random Number Generator (RNG) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_RNG_RNGCR (*(vuint32*)(0xEC088000)) +#define MCF_RNG_RNGSR (*(vuint32*)(0xEC088004)) +#define MCF_RNG_RNGER (*(vuint32*)(0xEC088008)) +#define MCF_RNG_RNGOUT (*(vuint32*)(0xEC08800C)) + +/* Bit definitions and macros for MCF_RNG_RNGCR */ +#define MCF_RNG_RNGCR_GO (0x00000001) +#define MCF_RNG_RNGCR_HA (0x00000002) +#define MCF_RNG_RNGCR_IM (0x00000004) +#define MCF_RNG_RNGCR_CI (0x00000008) + +/* Bit definitions and macros for MCF_RNG_RNGSR */ +#define MCF_RNG_RNGSR_SV (0x00000001) +#define MCF_RNG_RNGSR_LRS (0x00000002) +#define MCF_RNG_RNGSR_FUF (0x00000004) +#define MCF_RNG_RNGSR_EI (0x00000008) +#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) +#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) + +/* Bit definitions and macros for MCF_RNG_RNGER */ +#define MCF_RNG_RNGER_ENTROPY(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_RNG_RNGOUT */ +#define MCF_RNG_RNGOUT_OUTPUT(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Power Management Module (PMM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PMM_WCR (*(vuint8 *)(0xFC040013)) +#define MCF_PMM_PPMSR0 (*(vuint8 *)(0xFC04002C)) +#define MCF_PMM_PPMSR1 (*(vuint8 *)(0xFC04002E)) +#define MCF_PMM_PPMCR0 (*(vuint8 *)(0xFC04002D)) +#define MCF_PMM_PPMCR1 (*(vuint8 *)(0xFC04002F)) +#define MCF_PMM_PPMHR0 (*(vuint32*)(0xFC040030)) +#define MCF_PMM_PPMLR0 (*(vuint32*)(0xFC040034)) +#define MCF_PMM_PPMHR1 (*(vuint32*)(0xFC040038)) +#define MCF_PMM_LPCR (*(vuint8 *)(0xFC0A0007)) + +/* Bit definitions and macros for MCF_PMM_WCR */ +#define MCF_PMM_WCR_PRILVL(x) (((x)&0x07)<<0) +#define MCF_PMM_WCR_ENBWCR (0x80) + +/* Bit definitions and macros for MCF_PMM_PPMSR */ +#define MCF_PMM_PPMSR_SMCD(x) (((x)&0x3F)<<0) +#define MCF_PMM_PPMSR_SAMCD (0x40) + +/* Bit definitions and macros for MCF_PMM_PPMCR */ +#define MCF_PMM_PPMCR_CMCD(x) (((x)&0x3F)<<0) +#define MCF_PMM_PPMCR_CAMCD (0x40) + +/* Bit definitions and macros for MCF_PMM_PPMHR0 */ +#define MCF_PMM_PPMHR0_CD32 (0x00000001) +#define MCF_PMM_PPMHR0_CD33 (0x00000002) +#define MCF_PMM_PPMHR0_CD34 (0x00000004) +#define MCF_PMM_PPMHR0_CD35 (0x00000008) +#define MCF_PMM_PPMHR0_CD36 (0x00000010) +#define MCF_PMM_PPMHR0_CD37 (0x00000020) +#define MCF_PMM_PPMHR0_CD38 (0x00000040) +#define MCF_PMM_PPMHR0_CD40 (0x00000100) +#define MCF_PMM_PPMHR0_CD41 (0x00000200) +#define MCF_PMM_PPMHR0_CD42 (0x00000400) +#define MCF_PMM_PPMHR0_CD43 (0x00000800) +#define MCF_PMM_PPMHR0_CD44 (0x00001000) +#define MCF_PMM_PPMHR0_CD45 (0x00002000) +#define MCF_PMM_PPMHR0_CD46 (0x00004000) +#define MCF_PMM_PPMHR0_CD47 (0x00008000) +#define MCF_PMM_PPMHR0_CD48 (0x00010000) + +/* Bit definitions and macros for MCF_PMM_PPMLR0 */ +#define MCF_PMM_PPMLR0_CD2 (0x00000004) +#define MCF_PMM_PPMLR0_CD8 (0x00000100) +#define MCF_PMM_PPMLR0_CD12 (0x00001000) +#define MCF_PMM_PPMLR0_CD17 (0x00020000) +#define MCF_PMM_PPMLR0_CD18 (0x00040000) +#define MCF_PMM_PPMLR0_CD19 (0x00080000) +#define MCF_PMM_PPMLR0_CD21 (0x00200000) +#define MCF_PMM_PPMLR0_CD22 (0x00400000) +#define MCF_PMM_PPMLR0_CD23 (0x00800000) +#define MCF_PMM_PPMLR0_CD24 (0x01000000) +#define MCF_PMM_PPMLR0_CD25 (0x02000000) +#define MCF_PMM_PPMLR0_CD26 (0x04000000) +#define MCF_PMM_PPMLR0_CD28 (0x10000000) +#define MCF_PMM_PPMLR0_CD29 (0x20000000) +#define MCF_PMM_PPMLR0_CD30 (0x40000000) +#define MCF_PMM_PPMLR0_CD31 (0x80000000) + +/* Bit definitions and macros for MCF_PMM_PPMHR1 */ +#define MCF_PMM_PPMHR1_CD32 (0x00000001) +#define MCF_PMM_PPMHR1_CD33 (0x00000002) +#define MCF_PMM_PPMHR1_CD34 (0x00000004) + +/* Bit definitions and macros for MCF_PMM_LPCR */ +#define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF_PMM_LPCR_FWKUP (0x20) +#define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF_PMM_LPCR_LPMD_RUN (0x00) +#define MCF_PMM_LPCR_LPMD_DOZE (0x40) +#define MCF_PMM_LPCR_LPMD_WAIT (0x80) +#define MCF_PMM_LPCR_LPMD_STOP (0xC0) +#define MCF_PMM_LPCR_STPMD_SYS_DISABLED (0x00) +#define MCF_PMM_LPCR_STPMD_SYS_BUSCLK_DISABLED (0x04) +#define MCF_PMM_LPCR_STPMD_ONLY_OSC_ENABLED (0x08) +#define MCF_PMM_LPCR_STPMD_ALL_DISABLED (0x0C) + +/********************************************************************* +* +* Cross-bar switch (XBS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_XBS_PRS1 (*(vuint32*)(0xFC004100)) +#define MCF_XBS_PRS2 (*(vuint32*)(0xFC004200)) +#define MCF_XBS_PRS3 (*(vuint32*)(0xFC004300)) +#define MCF_XBS_PRS4 (*(vuint32*)(0xFC004400)) +#define MCF_XBS_PRS5 (*(vuint32*)(0xFC004500)) +#define MCF_XBS_PRS6 (*(vuint32*)(0xFC004600)) +#define MCF_XBS_PRS7 (*(vuint32*)(0xFC004700)) +#define MCF_XBS_PRS(x) (*(vuint32*)(0xFC004100+((x-1)*0x100))) +#define MCF_XBS_CRS1 (*(vuint32*)(0xFC004110)) +#define MCF_XBS_CRS2 (*(vuint32*)(0xFC004210)) +#define MCF_XBS_CRS3 (*(vuint32*)(0xFC004310)) +#define MCF_XBS_CRS4 (*(vuint32*)(0xFC004410)) +#define MCF_XBS_CRS5 (*(vuint32*)(0xFC004510)) +#define MCF_XBS_CRS6 (*(vuint32*)(0xFC004610)) +#define MCF_XBS_CRS7 (*(vuint32*)(0xFC004710)) +#define MCF_XBS_CRS(x) (*(vuint32*)(0xFC004110+((x-1)*0x100))) + +/* Bit definitions and macros for MCF_XBS_PRS */ +#define MCF_XBS_PRS_M0(x) (((x)&0x00000007)<<0) +#define MCF_XBS_PRS_M1(x) (((x)&0x00000007)<<4) +#define MCF_XBS_PRS_M2(x) (((x)&0x00000007)<<8) +#define MCF_XBS_PRS_M4(x) (((x)&0x00000007)<<16) +#define MCF_XBS_PRS_M5(x) (((x)&0x00000007)<<20) +#define MCF_XBS_PRS_M6(x) (((x)&0x00000007)<<24) + +/* Bit definitions and macros for MCF_XBS_CRS */ +#define MCF_XBS_CRS_PARK(x) (((x)&0x00000007)<<0) +#define MCF_XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) +#define MCF_XBS_CRS_ARB (0x00000100) +#define MCF_XBS_CRS_RO (0x80000000) +#define MCF_XBS_CRS_PCTL_PARK_FIELD (0x00000000) +#define MCF_XBS_CRS_PCTL_PARK_ON_LAST (0x00000010) +#define MCF_XBS_CRS_PCTL_PARK_NO_MASTER (0x00000020) +#define MCF_XBS_CRS_PCTL_PARK_CORE (0x00000000) +#define MCF_XBS_CRS_PCTL_PARK_EDMA (0x00000001) +#define MCF_XBS_CRS_PCTL_PARK_FEC (0x00000002) + +/********************************************************************* +* +* FlexBus Chip Selects (FBCS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FBCS0_CSAR (*(vuint32*)(0xFC008000)) +#define MCF_FBCS0_CSMR (*(vuint32*)(0xFC008004)) +#define MCF_FBCS0_CSCR (*(vuint32*)(0xFC008008)) +#define MCF_FBCS1_CSAR (*(vuint32*)(0xFC00800C)) +#define MCF_FBCS1_CSMR (*(vuint32*)(0xFC008010)) +#define MCF_FBCS1_CSCR (*(vuint32*)(0xFC008014)) +#define MCF_FBCS2_CSAR (*(vuint32*)(0xFC008018)) +#define MCF_FBCS2_CSMR (*(vuint32*)(0xFC00801C)) +#define MCF_FBCS2_CSCR (*(vuint32*)(0xFC008020)) +#define MCF_FBCS3_CSAR (*(vuint32*)(0xFC008024)) +#define MCF_FBCS3_CSMR (*(vuint32*)(0xFC008028)) +#define MCF_FBCS3_CSCR (*(vuint32*)(0xFC00802C)) +#define MCF_FBCS4_CSAR (*(vuint32*)(0xFC008030)) +#define MCF_FBCS4_CSMR (*(vuint32*)(0xFC008034)) +#define MCF_FBCS4_CSCR (*(vuint32*)(0xFC008038)) +#define MCF_FBCS5_CSAR (*(vuint32*)(0xFC00803C)) +#define MCF_FBCS5_CSMR (*(vuint32*)(0xFC008040)) +#define MCF_FBCS5_CSCR (*(vuint32*)(0xFC008044)) +#define MCF_FBCS_CSAR(x) (*(vuint32*)(0xFC008000+((x)*0x00C))) +#define MCF_FBCS_CSMR(x) (*(vuint32*)(0xFC008004+((x)*0x00C))) +#define MCF_FBCS_CSCR(x) (*(vuint32*)(0xFC008008+((x)*0x00C))) + +/* Bit definitions and macros for MCF_FBCS_CSAR */ +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_FBCS_CSMR */ +#define MCF_FBCS_CSMR_V (0x00000001) +#define MCF_FBCS_CSMR_WP (0x00000100) +#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) +#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) +#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) +#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) +#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) +#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) +#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) +#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) +#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) +#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) +#define MCF_FBCS_CSMR_BAM_512K (0x00070000) +#define MCF_FBCS_CSMR_BAM_256K (0x00030000) +#define MCF_FBCS_CSMR_BAM_128K (0x00010000) +#define MCF_FBCS_CSMR_BAM_64K (0x00000000) + +/* Bit definitions and macros for MCF_FBCS_CSCR */ +#define MCF_FBCS_CSCR_BSTW (0x00000008) +#define MCF_FBCS_CSCR_BSTR (0x00000010) +#define MCF_FBCS_CSCR_BEM (0x00000020) +#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) +#define MCF_FBCS_CSCR_AA (0x00000100) +#define MCF_FBCS_CSCR_SBM (0x00000200) +#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) +#define MCF_FBCS_CSCR_SWSEN (0x00800000) +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) +#define MCF_FBCS_CSCR_PS_8 (0x00000040) +#define MCF_FBCS_CSCR_PS_16 (0x00000080) +#define MCF_FBCS_CSCR_PS_32 (0x00000000) + +/********************************************************************* +* +* FlexCAN Module (CAN) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CAN_CANMCR (*(vuint32*)(0xFC020000)) +#define MCF_CAN_CANCTRL (*(vuint32*)(0xFC020004)) +#define MCF_CAN_TIMER (*(vuint32*)(0xFC020008)) +#define MCF_CAN_RXGMASK (*(vuint32*)(0xFC020010)) +#define MCF_CAN_RX14MASK (*(vuint32*)(0xFC020014)) +#define MCF_CAN_RX15MASK (*(vuint32*)(0xFC020018)) +#define MCF_CAN_ERRCNT (*(vuint32*)(0xFC02001C)) +#define MCF_CAN_ERRSTAT (*(vuint32*)(0xFC020020)) +#define MCF_CAN_IMASK (*(vuint32*)(0xFC020028)) +#define MCF_CAN_IFLAG (*(vuint32*)(0xFC020030)) + +/* Bit definitions and macros for MCF_CAN_CANMCR */ +#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) +#define MCF_CAN_CANMCR_LPMACK (0x00100000) +#define MCF_CAN_CANMCR_SUPV (0x00800000) +#define MCF_CAN_CANMCR_FRZACK (0x01000000) +#define MCF_CAN_CANMCR_SOFTRST (0x02000000) +#define MCF_CAN_CANMCR_NOTRDY (0x08000000) +#define MCF_CAN_CANMCR_HALT (0x10000000) +#define MCF_CAN_CANMCR_FRZ (0x40000000) +#define MCF_CAN_CANMCR_MDIS (0x80000000) + +/* Bit definitions and macros for MCF_CAN_CANCTRL */ +#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) +#define MCF_CAN_CANCTRL_LOM (0x00000008) +#define MCF_CAN_CANCTRL_LBUF (0x00000010) +#define MCF_CAN_CANCTRL_TSYNC (0x00000020) +#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) +#define MCF_CAN_CANCTRL_SAMP (0x00000080) +#define MCF_CAN_CANCTRL_LPB (0x00001000) +#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) +#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) +#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) +#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) +#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) +#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) +#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_CAN_TIMER */ +#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RXGMASK */ +#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX14MASK */ +#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX15MASK */ +#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_ERRCNT */ +#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) +#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for MCF_CAN_ERRSTAT */ +#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) +#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) +#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) +#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) +#define MCF_CAN_ERRSTAT_TXRX (0x00000040) +#define MCF_CAN_ERRSTAT_IDLE (0x00000080) +#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) +#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) +#define MCF_CAN_ERRSTAT_STFERR (0x00000400) +#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) +#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) +#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) +#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) +#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) +#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) +#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) + +/* Bit definitions and macros for MCF_CAN_IMASK */ +#define MCF_CAN_IMASK_BUF0M (0x00000001) +#define MCF_CAN_IMASK_BUF1M (0x00000002) +#define MCF_CAN_IMASK_BUF2M (0x00000004) +#define MCF_CAN_IMASK_BUF3M (0x00000008) +#define MCF_CAN_IMASK_BUF4M (0x00000010) +#define MCF_CAN_IMASK_BUF5M (0x00000020) +#define MCF_CAN_IMASK_BUF6M (0x00000040) +#define MCF_CAN_IMASK_BUF7M (0x00000080) +#define MCF_CAN_IMASK_BUF8M (0x00000100) +#define MCF_CAN_IMASK_BUF9M (0x00000200) +#define MCF_CAN_IMASK_BUF10M (0x00000400) +#define MCF_CAN_IMASK_BUF11M (0x00000800) +#define MCF_CAN_IMASK_BUF12M (0x00001000) +#define MCF_CAN_IMASK_BUF13M (0x00002000) +#define MCF_CAN_IMASK_BUF14M (0x00004000) +#define MCF_CAN_IMASK_BUF15M (0x00008000) +#define MCF_CAN_IMASK_BUF(x) (1<varTab)[idx] = value + /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, + so I'm avoiding surrounding it with "do {} while(0)" */ + +#endif /* DEFINESONLY */ + +#endif /* _MCD_API_H */ diff --git a/bsps/m68k/include/mcf548x/MCD_progCheck.h b/bsps/m68k/include/mcf548x/MCD_progCheck.h new file mode 100644 index 0000000000..e0f578fdaf --- /dev/null +++ b/bsps/m68k/include/mcf548x/MCD_progCheck.h @@ -0,0 +1,5 @@ + /* This file is autogenerated. Do not change */ +#define CURRBD 4 +#define DCOUNT 6 +#define DESTPTR 5 +#define SRCPTR 7 diff --git a/bsps/m68k/include/mcf548x/MCD_tasksInit.h b/bsps/m68k/include/mcf548x/MCD_tasksInit.h new file mode 100644 index 0000000000..daf871cd6d --- /dev/null +++ b/bsps/m68k/include/mcf548x/MCD_tasksInit.h @@ -0,0 +1,44 @@ +#ifndef MCD_TSK_INIT_H +#define MCD_TSK_INIT_H 1 + +/* + * Do not edit! + */ + + +/* + * Task 0 + */ +void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel); + + +/* + * Task 1 + */ +void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); + + +/* + * Task 2 + */ +void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel); + + +/* + * Task 3 + */ +void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); + + +/* + * Task 4 + */ +void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel); + + +/* + * Task 5 + */ +void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel); + +#endif /* MCD_TSK_INIT_H */ diff --git a/bsps/m68k/include/mcf548x/mcdma_glue.h b/bsps/m68k/include/mcf548x/mcdma_glue.h new file mode 100644 index 0000000000..de0621120f --- /dev/null +++ b/bsps/m68k/include/mcf548x/mcdma_glue.h @@ -0,0 +1,106 @@ +/*===============================================================*\ +| Project: RTEMS generic MFC548x BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2004-2009 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares glue functions to the Freescale Mcdma API | +\*===============================================================*/ +#ifndef _MCDMA_GLUE_H +#define _MCDMA_GLUE_H + +#include +#include + +#define MCDMA_CLR_PENDING(chan) (MCF548X_DMA_DIPR = (1 << (chan))) +#define MCDMA_GET_PENDING(chan) (MCF548X_DMA_DIPR & (1 << (chan))) + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void mcdma_glue_irq_enable +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| enable interrupt for given task number | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int mcdma_taskno /* task number to enable */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void mcdma_glue_irq_disable +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| disable interrupt for given task number | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int mcdma_taskno /* task number to disable */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void mcdma_glue_irq_install +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| install given function as mcdma interrupt handler | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int mcdma_taskno, /* task number for handler */ + void (*the_handler)(rtems_irq_hdl_param), /* function to call */ + void *the_param + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void mcdma_glue_init +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| initialize the mcdma module (if not yet done): | +| - load code | +| - initialize registers | +| - initialize bus arbiter | +| - initialize interrupt control | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + void *sram_base /* base address for SRAM, to be used for DMA task */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +#endif /* _MCDMA_GLUE_H */ diff --git a/bsps/m68k/include/mcf548x/mcf548x.h b/bsps/m68k/include/mcf548x/mcf548x.h new file mode 100644 index 0000000000..7a9dc73698 --- /dev/null +++ b/bsps/m68k/include/mcf548x/mcf548x.h @@ -0,0 +1,4056 @@ +/*===============================================================*\ +| Project: RTEMS generic mcf548x BSP | ++-----------------------------------------------------------------+ +| File: mcf548x.h | ++-----------------------------------------------------------------+ +| The file contains all register an bit definitions of the | +| generic MCF548x BSP. | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| | +| Parts of the code has been derived from the "dBUG source code" | +| package Freescale is providing for M548X EVBs. The usage of | +| the modified or unmodified code and it's integration into the | +| generic mcf548x BSP has been done according to the Freescale | +| license terms. | +| | +| The Freescale license terms can be reviewed in the file | +| | +| Freescale_license.txt | +| | ++-----------------------------------------------------------------+ +| | +| The generic mcf548x BSP has been developed on the basic | +| structures and modules of the av5282 BSP. | +| | ++-----------------------------------------------------------------+ +| | +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| | +| date history ID | +| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | +| 12.11.07 1.0 ras | +| | +\*===============================================================*/ + +#ifndef __MCF548X_H__ +#define __MCF548X_H__ + +#include + +/*********************************************************************/ +extern char __MBAR[]; + +/********************************************************************* +* +* Cache Control Register (CACR) +* +*********************************************************************/ + +/* Bit definitions and macros for MCF548X_CACR */ +#define MCF548X_CACR_DEC (0x80000000) +#define MCF548X_CACR_DW (0x40000000) +#define MCF548X_CACR_DESB (0x20000000) +#define MCF548X_CACR_DDPI (0x10000000) +#define MCF548X_CACR_DHLCK (0x08000000) +#define MCF548X_CACR_DDCM(x) (((x)<<25)&0x06000000) +#define MCF548X_CACR_DCINVA (0x01000000) +#define MCF548X_CACR_DDSP (0x00800000) +#define MCF548X_CACR_BEC (0x00080000) +#define MCF548X_CACR_BCINVA (0x00040000) +#define MCF548X_CACR_IEC (0x00008000) +#define MCF548X_CACR_DNFB (0x00002000) +#define MCF548X_CACR_IDPI (0x00001000) +#define MCF548X_CACR_IHLCK (0x00000800) +#define MCF548X_CACR_IDCM (0x00000400) +#define MCF548X_CACR_ICINVA (0x00000100) +#define MCF548X_CACR_IDSP (0x00000080) +#define MCF548X_CACR_EUSP (0x00000020) +#define MCF548X_CACR_DF (0x00000010) + +/* Bit definitions and macros for MCF548X_CACR_DDCM (data cache mode) */ +#define DCACHE_ON_WRIGHTTHROUGH 0 +#define DCACHE_ON_COPYBACK 1 +#define DCACHE_OFF_PRECISE 2 +#define DCACHE_OFF_IMPRECISE 3 + +/********************************************************************* +* +* Access Control Registers (ACR0-3) +* +*********************************************************************/ + +/* Bit definitions and macros for MCF548X_ACRn */ +#define MCF548X_ACR_BA(x) ((x)&0xFF000000) +#define MCF548X_ACR_ADMSK_AMM(x) (((x)>=0x1000000) ? (((x)&0xFF000000)>>8) : (((x)&0x00FF0000)|0x00000400)) +#define MCF548X_ACR_E (0x00008000) +#define MCF548X_ACR_S(x) (((x)<<13)&0x00006000) +#define MCF548X_ACR_CM(x) (((x)<<5)&0x00000060) +#define MCF548X_ACR_SP (0x00000008) +#define MCF548X_ACR_W (0x00000004) + +/* Bit definitions and macros for MCF548X_ACR_S (supervisor/user access) */ +#define S_ACCESS_USER 0 +#define S_ACCESS_SUPV 1 +#define S_ACCESS_BOTH 2 + +/* Bit definitions and macros for MCF548X_ACR_CM (cache mode) */ +#define CM_ON_WRIGHTTHROUGH 0 +#define CM_ON_COPYBACK 1 +#define CM_OFF_PRECISE 2 +#define CM_OFF_IMPRECISE 3 + +/********************************************************************* +* +* System PLL Control Register (SPCR) +* +*********************************************************************/ + +/* Register read/write macro */ +#define MCF548X_PLL_SPCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000300))) + +/* Bit definitions and macros for MCF548X_PLL_SPCR (supervisor/user access) */ +#define MCF548X_PLL_SPCR_PLLK 0x80000000 +#define MCF548X_PLL_SPCR_COREN 0x00004000 +#define MCF548X_PLL_SPCR_CRYENB 0x00002000 +#define MCF548X_PLL_SPCR_CRYENA 0x00001000 +#define MCF548X_PLL_SPCR_CAN1EN 0x00000800 +#define MCF548X_PLL_SPCR_PSCEN 0x00000200 +#define MCF548X_PLL_SPCR_USBEN 0x00000080 +#define MCF548X_PLL_SPCR_FEC1EN 0x00000040 +#define MCF548X_PLL_SPCR_FEC0EN 0x00000020 +#define MCF548X_PLL_SPCR_DMAEN 0x00000010 +#define MCF548X_PLL_SPCR_CAN0EN 0x00000008 +#define MCF548X_PLL_SPCR_FBEN 0x00000004 +#define MCF548X_PLL_SPCR_PCIEN 0x00000002 +#define MCF548X_PLL_SPCR_MEMEN 0x00000001 + +/********************************************************************* +* +* XLB Arbiter Control (XLB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_XLB_CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000240))) +#define MCF548X_XLB_ADRTO (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000258))) +#define MCF548X_XLB_DATTO (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00025C))) +#define MCF548X_XLB_BUSTO (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000260))) + +/********************************************************************* +* +* Fast Ethernet Controller (FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_FEC_EIR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009004))) +#define MCF548X_FEC_EIMR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009008))) +#define MCF548X_FEC_ECR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009024))) +#define MCF548X_FEC_MMFR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009040))) +#define MCF548X_FEC_MSCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009044))) +#define MCF548X_FEC_MIBC0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009064))) +#define MCF548X_FEC_RCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009084))) +#define MCF548X_FEC_R_HASH0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009088))) +#define MCF548X_FEC_TCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090C4))) +#define MCF548X_FEC_PALR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090E4))) +#define MCF548X_FEC_PAUR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090E8))) +#define MCF548X_FEC_OPD0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090EC))) +#define MCF548X_FEC_IAUR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009118))) +#define MCF548X_FEC_IALR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00911C))) +#define MCF548X_FEC_GAUR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009120))) +#define MCF548X_FEC_GALR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009124))) +#define MCF548X_FEC_FECTFWR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009144))) +#define MCF548X_FEC_FECRFDR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009184))) +#define MCF548X_FEC_FECRFSR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009188))) +#define MCF548X_FEC_FECRFCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00918C))) +#define MCF548X_FEC_FECRLRFP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009190))) +#define MCF548X_FEC_FECRLWFP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009194))) +#define MCF548X_FEC_FECRFAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009198))) +#define MCF548X_FEC_FECRFRP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00919C))) +#define MCF548X_FEC_FECRFWP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A0))) +#define MCF548X_FEC_FECTFDR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A4))) +#define MCF548X_FEC_FECTFSR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A8))) +#define MCF548X_FEC_FECTFCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091AC))) +#define MCF548X_FEC_FECTLRFP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B0))) +#define MCF548X_FEC_FECTLWFP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B4))) +#define MCF548X_FEC_FECTFAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B8))) +#define MCF548X_FEC_FECTFRP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091BC))) +#define MCF548X_FEC_FECTFWP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C0))) +#define MCF548X_FEC_FRST0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C4))) +#define MCF548X_FEC_CTCWR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C8))) +#define MCF548X_FEC_RMON_T_DROP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009200))) +#define MCF548X_FEC_RMON_T_PACKETS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009204))) +#define MCF548X_FEC_RMON_T_BC_PKT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009208))) +#define MCF548X_FEC_RMON_T_MC_PKT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00920C))) +#define MCF548X_FEC_RMON_T_CRC_ALIGN0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009210))) +#define MCF548X_FEC_RMON_T_UNDERSIZE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009214))) +#define MCF548X_FEC_RMON_T_OVERSIZE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009218))) +#define MCF548X_FEC_RMON_T_FRAG0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00921C))) +#define MCF548X_FEC_RMON_T_JAB0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009220))) +#define MCF548X_FEC_RMON_T_COL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009224))) +#define MCF548X_FEC_RMON_T_P640 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009228))) +#define MCF548X_FEC_RMON_T_P65TO1270 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00922C))) +#define MCF548X_FEC_RMON_T_P128TO2550 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009230))) +#define MCF548X_FEC_RMON_T_P256TO5110 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009234))) +#define MCF548X_FEC_RMON_T_P512TO10230 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009238))) +#define MCF548X_FEC_RMON_T_P1024TO20470 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00923C))) +#define MCF548X_FEC_RMON_T_P_GTE20480 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009240))) +#define MCF548X_FEC_RMON_T_OCTETS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009244))) +#define MCF548X_FEC_IEEE_T_DROP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009248))) +#define MCF548X_FEC_IEEE_T_FRAME_OK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00924C))) +#define MCF548X_FEC_IEEE_T_1COL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009250))) +#define MCF548X_FEC_IEEE_T_MCOL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009254))) +#define MCF548X_FEC_IEEE_T_DEF0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009258))) +#define MCF548X_FEC_IEEE_T_LCOL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00925C))) +#define MCF548X_FEC_IEEE_T_EXCOL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009260))) +#define MCF548X_FEC_IEEE_T_MACERR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009264))) +#define MCF548X_FEC_IEEE_T_CSERR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009268))) +#define MCF548X_FEC_IEEE_T_SQE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00926C))) +#define MCF548X_FEC_IEEE_T_FDXFC0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009270))) +#define MCF548X_FEC_IEEE_T_OCTETS_OK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009274))) +#define MCF548X_FEC_RMON_R_PACKETS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009284))) +#define MCF548X_FEC_RMON_R_BC_PKT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009288))) +#define MCF548X_FEC_RMON_R_MC_PKT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00928C))) +#define MCF548X_FEC_RMON_R_CRC_ALIGN0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009290))) +#define MCF548X_FEC_RMON_R_UNDERSIZE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009294))) +#define MCF548X_FEC_RMON_R_OVERSIZE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009298))) +#define MCF548X_FEC_RMON_R_FRAG0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00929C))) +#define MCF548X_FEC_RMON_R_JAB0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A0))) +#define MCF548X_FEC_RMON_R_RESVD_00 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A4))) +#define MCF548X_FEC_RMON_R_P640 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A8))) +#define MCF548X_FEC_RMON_R_P65TO1270 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092AC))) +#define MCF548X_FEC_RMON_R_P128TO2550 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B0))) +#define MCF548X_FEC_RMON_R_P256TO5110 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B4))) +#define MCF548X_FEC_RMON_R_512TO10230 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B8))) +#define MCF548X_FEC_RMON_R_1024TO20470 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092BC))) +#define MCF548X_FEC_RMON_R_P_GTE20480 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C0))) +#define MCF548X_FEC_RMON_R_OCTETS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C4))) +#define MCF548X_FEC_IEEE_R_DROP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C8))) +#define MCF548X_FEC_IEEE_R_FRAME_OK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092CC))) +#define MCF548X_FEC_IEEE_R_CRC0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D0))) +#define MCF548X_FEC_IEEE_R_ALIGN0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D4))) +#define MCF548X_FEC_IEEE_R_MACERR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D8))) +#define MCF548X_FEC_IEEE_R_FDXFC0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092DC))) +#define MCF548X_FEC_IEEE_R_OCTETS_OK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092E0))) +#define MCF548X_FEC_EIR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009804))) +#define MCF548X_FEC_EIMR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009808))) +#define MCF548X_FEC_ECR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009824))) +#define MCF548X_FEC_MMFR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009840))) +#define MCF548X_FEC_MSCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009844))) +#define MCF548X_FEC_MIBC1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009864))) +#define MCF548X_FEC_RCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009884))) +#define MCF548X_FEC_R_HASH1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009888))) +#define MCF548X_FEC_TCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0098C4))) +#define MCF548X_FEC_PALR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0098E4))) +#define MCF548X_FEC_PAUR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0098E8))) +#define MCF548X_FEC_OPD1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0098EC))) +#define MCF548X_FEC_IAUR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009918))) +#define MCF548X_FEC_IALR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00991C))) +#define MCF548X_FEC_GAUR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009920))) +#define MCF548X_FEC_GALR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009924))) +#define MCF548X_FEC_FECTFWR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009944))) +#define MCF548X_FEC_FECRFDR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009984))) +#define MCF548X_FEC_FECRFSR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009988))) +#define MCF548X_FEC_FECRFCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00998C))) +#define MCF548X_FEC_FECRLRFP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009990))) +#define MCF548X_FEC_FECRLWFP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009994))) +#define MCF548X_FEC_FECRFAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009998))) +#define MCF548X_FEC_FECRFRP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00999C))) +#define MCF548X_FEC_FECRFWP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099A0))) +#define MCF548X_FEC_FECTFDR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099A4))) +#define MCF548X_FEC_FECTFSR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099A8))) +#define MCF548X_FEC_FECTFCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099AC))) +#define MCF548X_FEC_FECTLRFP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099B0))) +#define MCF548X_FEC_FECTLWFP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099B4))) +#define MCF548X_FEC_FECTFAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099B8))) +#define MCF548X_FEC_FECTFRP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099BC))) +#define MCF548X_FEC_FECTFWP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099C0))) +#define MCF548X_FEC_FRST1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099C4))) +#define MCF548X_FEC_CTCWR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099C8))) +#define MCF548X_FEC_RMON_T_DROP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A00))) +#define MCF548X_FEC_RMON_T_PACKETS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A04))) +#define MCF548X_FEC_RMON_T_BC_PKT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A08))) +#define MCF548X_FEC_RMON_T_MC_PKT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A0C))) +#define MCF548X_FEC_RMON_T_CRC_ALIGN1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A10))) +#define MCF548X_FEC_RMON_T_UNDERSIZE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A14))) +#define MCF548X_FEC_RMON_T_OVERSIZE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A18))) +#define MCF548X_FEC_RMON_T_FRAG1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A1C))) +#define MCF548X_FEC_RMON_T_JAB1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A20))) +#define MCF548X_FEC_RMON_T_COL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A24))) +#define MCF548X_FEC_RMON_T_P641 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A28))) +#define MCF548X_FEC_RMON_T_P65TO1271 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A2C))) +#define MCF548X_FEC_RMON_T_P128TO2551 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A30))) +#define MCF548X_FEC_RMON_T_P256TO5111 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A34))) +#define MCF548X_FEC_RMON_T_P512TO10231 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A38))) +#define MCF548X_FEC_RMON_T_P1024TO20471 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A3C))) +#define MCF548X_FEC_RMON_T_P_GTE20481 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A40))) +#define MCF548X_FEC_RMON_T_OCTETS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A44))) +#define MCF548X_FEC_IEEE_T_DROP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A48))) +#define MCF548X_FEC_IEEE_T_FRAME_OK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A4C))) +#define MCF548X_FEC_IEEE_T_1COL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A50))) +#define MCF548X_FEC_IEEE_T_MCOL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A54))) +#define MCF548X_FEC_IEEE_T_DEF1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A58))) +#define MCF548X_FEC_IEEE_T_LCOL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A5C))) +#define MCF548X_FEC_IEEE_T_EXCOL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A60))) +#define MCF548X_FEC_IEEE_T_MACERR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A64))) +#define MCF548X_FEC_IEEE_T_CSERR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A68))) +#define MCF548X_FEC_IEEE_T_SQE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A6C))) +#define MCF548X_FEC_IEEE_T_FDXFC1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A70))) +#define MCF548X_FEC_IEEE_T_OCTETS_OK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A74))) +#define MCF548X_FEC_RMON_R_PACKETS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A84))) +#define MCF548X_FEC_RMON_R_BC_PKT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A88))) +#define MCF548X_FEC_RMON_R_MC_PKT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A8C))) +#define MCF548X_FEC_RMON_R_CRC_ALIGN1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A90))) +#define MCF548X_FEC_RMON_R_UNDERSIZE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A94))) +#define MCF548X_FEC_RMON_R_OVERSIZE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A98))) +#define MCF548X_FEC_RMON_R_FRAG1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A9C))) +#define MCF548X_FEC_RMON_R_JAB1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AA0))) +#define MCF548X_FEC_RMON_R_RESVD_01 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AA4))) +#define MCF548X_FEC_RMON_R_P641 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AA8))) +#define MCF548X_FEC_RMON_R_P65TO1271 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AAC))) +#define MCF548X_FEC_RMON_R_P128TO2551 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AB0))) +#define MCF548X_FEC_RMON_R_P256TO5111 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AB4))) +#define MCF548X_FEC_RMON_R_512TO10231 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AB8))) +#define MCF548X_FEC_RMON_R_1024TO20471 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009ABC))) +#define MCF548X_FEC_RMON_R_P_GTE20481 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AC0))) +#define MCF548X_FEC_RMON_R_OCTETS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AC4))) +#define MCF548X_FEC_IEEE_R_DROP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AC8))) +#define MCF548X_FEC_IEEE_R_FRAME_OK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009ACC))) +#define MCF548X_FEC_IEEE_R_CRC1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AD0))) +#define MCF548X_FEC_IEEE_R_ALIGN1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AD4))) +#define MCF548X_FEC_IEEE_R_MACERR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AD8))) +#define MCF548X_FEC_IEEE_R_FDXFC1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009ADC))) +#define MCF548X_FEC_IEEE_R_OCTETS_OK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AE0))) +#define MCF548X_FEC_EIR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009004U+((x)*0x800)))) +#define MCF548X_FEC_EIMR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009008U+((x)*0x800)))) +#define MCF548X_FEC_ECR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009024U+((x)*0x800)))) +#define MCF548X_FEC_MMFR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009040U+((x)*0x800)))) +#define MCF548X_FEC_MSCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009044U+((x)*0x800)))) +#define MCF548X_FEC_MIBC(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009064U+((x)*0x800)))) +#define MCF548X_FEC_RCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009084U+((x)*0x800)))) +#define MCF548X_FEC_R_HASH(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009088U+((x)*0x800)))) +#define MCF548X_FEC_TCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090C4U+((x)*0x800)))) +#define MCF548X_FEC_PALR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090E4U+((x)*0x800)))) +#define MCF548X_FEC_PAUR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090E8U+((x)*0x800)))) +#define MCF548X_FEC_OPD(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090ECU+((x)*0x800)))) +#define MCF548X_FEC_IAUR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009118U+((x)*0x800)))) +#define MCF548X_FEC_IALR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00911CU+((x)*0x800)))) +#define MCF548X_FEC_GAUR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009120U+((x)*0x800)))) +#define MCF548X_FEC_GALR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009124U+((x)*0x800)))) +#define MCF548X_FEC_FECTFWR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009144U+((x)*0x800)))) +#define MCF548X_FEC_FECRFDR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009184U+((x)*0x800)))) +#define MCF548X_FEC_FECRFSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009188U+((x)*0x800)))) +#define MCF548X_FEC_FECRFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00918CU+((x)*0x800)))) +#define MCF548X_FEC_FECRLRFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009190U+((x)*0x800)))) +#define MCF548X_FEC_FECRLWFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009194U+((x)*0x800)))) +#define MCF548X_FEC_FECRFAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009198U+((x)*0x800)))) +#define MCF548X_FEC_FECRFRP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00919CU+((x)*0x800)))) +#define MCF548X_FEC_FECRFWP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A0U+((x)*0x800)))) +#define MCF548X_FEC_FECTFDR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A4U+((x)*0x800)))) +#define MCF548X_FEC_FECTFSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A8U+((x)*0x800)))) +#define MCF548X_FEC_FECTFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091ACU+((x)*0x800)))) +#define MCF548X_FEC_FECTLRFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B0U+((x)*0x800)))) +#define MCF548X_FEC_FECTLWFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B4U+((x)*0x800)))) +#define MCF548X_FEC_FECTFAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B8U+((x)*0x800)))) +#define MCF548X_FEC_FECTFRP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091BCU+((x)*0x800)))) +#define MCF548X_FEC_FECTFWP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C0U+((x)*0x800)))) +#define MCF548X_FEC_FRST(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C4U+((x)*0x800)))) +#define MCF548X_FEC_CTCWR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C8U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009200U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009204U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009208U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00920CU+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009210U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009214U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009218U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00921CU+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009220U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_COL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009224U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P64(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009228U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00922CU+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009230U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009234U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009238U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00923CU+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009240U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009244U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009248U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00924CU+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009250U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009254U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009258U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00925CU+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009260U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009264U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009268U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00926CU+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009270U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009274U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009284U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009288U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00928CU+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009290U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009294U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009298U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00929CU+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A0U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A4U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_P64(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A8U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092ACU+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B0U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B4U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_512TO1023(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B8U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_1024TO2047(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092BCU+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C0U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C4U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C8U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092CCU+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D0U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D4U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D8U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092DCU+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092E0U+((x)*0x800)))) + +/* Bit definitions and macros for MCF548X_FEC_EIR */ +#define MCF548X_FEC_EIR_RFERR (0x00020000) +#define MCF548X_FEC_EIR_XFERR (0x00040000) +#define MCF548X_FEC_EIR_XFUN (0x00080000) +#define MCF548X_FEC_EIR_RL (0x00100000) +#define MCF548X_FEC_EIR_LC (0x00200000) +#define MCF548X_FEC_EIR_MII (0x00800000) +#define MCF548X_FEC_EIR_TXF (0x08000000) +#define MCF548X_FEC_EIR_GRA (0x10000000) +#define MCF548X_FEC_EIR_BABT (0x20000000) +#define MCF548X_FEC_EIR_BABR (0x40000000) +#define MCF548X_FEC_EIR_HBERR (0x80000000) +#define MCF548X_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF548X_FEC_EIMR */ +#define MCF548X_FEC_EIMR_RFERR (0x00020000) +#define MCF548X_FEC_EIMR_XFERR (0x00040000) +#define MCF548X_FEC_EIMR_XFUN (0x00080000) +#define MCF548X_FEC_EIMR_RL (0x00100000) +#define MCF548X_FEC_EIMR_LC (0x00200000) +#define MCF548X_FEC_EIMR_MII (0x00800000) +#define MCF548X_FEC_EIMR_TXF (0x08000000) +#define MCF548X_FEC_EIMR_GRA (0x10000000) +#define MCF548X_FEC_EIMR_BABT (0x20000000) +#define MCF548X_FEC_EIMR_BABR (0x40000000) +#define MCF548X_FEC_EIMR_HBERR (0x80000000) +#define MCF548X_FEC_EIMR_MASK_ALL (0x00000000) +#define MCF548X_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF548X_FEC_ECR */ +#define MCF548X_FEC_ECR_RESET (0x00000001) +#define MCF548X_FEC_ECR_ETHER_EN (0x00000002) + +/* Bit definitions and macros for MCF548X_FEC_MMFR */ +#define MCF548X_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) +#define MCF548X_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) +#define MCF548X_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) +#define MCF548X_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) +#define MCF548X_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) +#define MCF548X_FEC_MMFR_ST_01 (0x40000000) +#define MCF548X_FEC_MMFR_OP_READ (0x20000000) +#define MCF548X_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF548X_FEC_MMFR_TA_10 (0x00020000) + +/* Bit definitions and macros for MCF548X_FEC_MSCR */ +#define MCF548X_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) +#define MCF548X_FEC_MSCR_DIS_PREAMBLE (0x00000080) +#define MCF548X_FEC_MSCR_MII_SPEED_133 (0x1B<<1) +#define MCF548X_FEC_MSCR_MII_SPEED_120 (0x18<<1) +#define MCF548X_FEC_MSCR_MII_SPEED_66 (0xE<<1) +#define MCF548X_FEC_MSCR_MII_SPEED_60 (0xC<<1) + +/* Bit definitions and macros for MCF548X_FEC_MIBC */ +#define MCF548X_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF548X_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF548X_FEC_RCR */ +#define MCF548X_FEC_RCR_LOOP (0x00000001) +#define MCF548X_FEC_RCR_DRT (0x00000002) +#define MCF548X_FEC_RCR_MII_MODE (0x00000004) +#define MCF548X_FEC_RCR_PROM (0x00000008) +#define MCF548X_FEC_RCR_BC_REJ (0x00000010) +#define MCF548X_FEC_RCR_FCE (0x00000020) +#define MCF548X_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) + +/* Bit definitions and macros for MCF548X_FEC_R_HASH */ +#define MCF548X_FEC_R_HASH_HASH(x) (((x)&0x0000003F)<<24) +#define MCF548X_FEC_R_HASH_MULTCAST (0x40000000) +#define MCF548X_FEC_R_HASH_FCE_DC (0x80000000) + +/* Bit definitions and macros for MCF548X_FEC_TCR */ +#define MCF548X_FEC_TCR_GTS (0x00000001) +#define MCF548X_FEC_TCR_HBC (0x00000002) +#define MCF548X_FEC_TCR_FDEN (0x00000004) +#define MCF548X_FEC_TCR_TFC_PAUSE (0x00000008) +#define MCF548X_FEC_TCR_RFC_PAUSE (0x00000010) + +/* Bit definitions and macros for MCF548X_FEC_PAUR */ +#define MCF548X_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_FEC_OPD */ +#define MCF548X_FEC_OPD_OP_PAUSE(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_FEC_FECTFWR */ +#define MCF548X_FEC_FECTFWR_X_WMRK(x) (((x)&0x0000000F)<<0) +#define MCF548X_FEC_FECTFWR_X_WMRK_64 (0x00000000) +#define MCF548X_FEC_FECTFWR_X_WMRK_128 (0x00000001) +#define MCF548X_FEC_FECTFWR_X_WMRK_192 (0x00000002) +#define MCF548X_FEC_FECTFWR_X_WMRK_256 (0x00000003) +#define MCF548X_FEC_FECTFWR_X_WMRK_320 (0x00000004) +#define MCF548X_FEC_FECTFWR_X_WMRK_384 (0x00000005) +#define MCF548X_FEC_FECTFWR_X_WMRK_448 (0x00000006) +#define MCF548X_FEC_FECTFWR_X_WMRK_512 (0x00000007) +#define MCF548X_FEC_FECTFWR_X_WMRK_576 (0x00000008) +#define MCF548X_FEC_FECTFWR_X_WMRK_640 (0x00000009) +#define MCF548X_FEC_FECTFWR_X_WMRK_704 (0x0000000A) +#define MCF548X_FEC_FECTFWR_X_WMRK_768 (0x0000000B) +#define MCF548X_FEC_FECTFWR_X_WMRK_832 (0x0000000C) +#define MCF548X_FEC_FECTFWR_X_WMRK_896 (0x0000000D) +#define MCF548X_FEC_FECTFWR_X_WMRK_960 (0x0000000E) +#define MCF548X_FEC_FECTFWR_X_WMRK_1024 (0x0000000F) + +/* Bit definitions and macros for MCF548X_FEC_FECRFDR */ +#define MCF548X_FEC_FECRFDR_ADDR0 (((uintptr_t)__MBAR + (0x009184))) +#define MCF548X_FEC_FECRFDR_ADDR1 (((uintptr_t)__MBAR + (0x009984))) +#define MCF548X_FEC_FECRFDR_ADDR(x) (((uintptr_t)__MBAR + (0x009184U+(0x800*x)))) + +/* Bit definitions and macros for MCF548X_FEC_FECRFSR */ +#define MCF548X_FEC_FECRFSR_EMT (0x00010000) +#define MCF548X_FEC_FECRFSR_ALARM (0x00020000) +#define MCF548X_FEC_FECRFSR_FU (0x00040000) +#define MCF548X_FEC_FECRFSR_FR (0x00080000) +#define MCF548X_FEC_FECRFSR_OF (0x00100000) +#define MCF548X_FEC_FECRFSR_UF (0x00200000) +#define MCF548X_FEC_FECRFSR_RXW (0x00400000) +#define MCF548X_FEC_FECRFSR_FAE (0x00800000) +#define MCF548X_FEC_FECRFSR_FRM(x) (((x)&0x0000000F)<<24) +#define MCF548X_FEC_FECRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF548X_FEC_FECRFCR */ +#define MCF548X_FEC_FECRFCR_COUNTER(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_FEC_FECRFCR_OF_MSK (0x00080000) +#define MCF548X_FEC_FECRFCR_UF_MSK (0x00100000) +#define MCF548X_FEC_FECRFCR_RXW_MSK (0x00200000) +#define MCF548X_FEC_FECRFCR_FAE_MSK (0x00400000) +#define MCF548X_FEC_FECRFCR_IP_MSK (0x00800000) +#define MCF548X_FEC_FECRFCR_GR(x) (((x)&0x00000007)<<24) +#define MCF548X_FEC_FECRFCR_FRM (0x08000000) +#define MCF548X_FEC_FECRFCR_TIMER (0x10000000) +#define MCF548X_FEC_FECRFCR_WFR (0x20000000) +#define MCF548X_FEC_FECRFCR_WCTL (0x40000000) + +/* Bit definitions and macros for MCF548X_FEC_FECRLRFP */ +#define MCF548X_FEC_FECRLRFP_LRFP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECRLWFP */ +#define MCF548X_FEC_FECRLWFP_LWFP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECRFAR */ +#define MCF548X_FEC_FECRFAR_ALARM(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECRFRP */ +#define MCF548X_FEC_FECRFRP_READ(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECRFWP */ +#define MCF548X_FEC_FECRFWP_WRITE(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECTFDR */ +#define MCF548X_FEC_FECTFDR_TFCW_TC (0x04000000) +#define MCF548X_FEC_FECTFDR_TFCW_ABC (0x02000000) +#define MCF548X_FEC_FECTFDR_ADDR0 (((uintptr_t)__MBAR + (0x0091A4))) +#define MCF548X_FEC_FECTFDR_ADDR1 (((uintptr_t)__MBAR + (0x0099A4))) +#define MCF548X_FEC_FECTFDR_ADDR(x) (((uintptr_t)__MBAR + (0x0091A4U+(0x800*x)))) + +/* Bit definitions and macros for MCF548X_FEC_FECTFSR */ +#define MCF548X_FEC_FECTFSR_EMT (0x00010000) +#define MCF548X_FEC_FECTFSR_ALARM (0x00020000) +#define MCF548X_FEC_FECTFSR_FU (0x00040000) +#define MCF548X_FEC_FECTFSR_FR (0x00080000) +#define MCF548X_FEC_FECTFSR_OF (0x00100000) +#define MCF548X_FEC_FECTFSR_UP (0x00200000) +#define MCF548X_FEC_FECTFSR_FAE (0x00800000) +#define MCF548X_FEC_FECTFSR_FRM(x) (((x)&0x0000000F)<<24) +#define MCF548X_FEC_FECTFSR_TXW (0x40000000) +#define MCF548X_FEC_FECTFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF548X_FEC_FECTFCR */ +#define MCF548X_FEC_FECTFCR_RESERVED (0x00200000) +#define MCF548X_FEC_FECTFCR_COUNTER(x) (((x)&0x0000FFFF)<<0|0x00200000) +#define MCF548X_FEC_FECTFCR_TXW_MSK (0x00240000) +#define MCF548X_FEC_FECTFCR_OF_MSK (0x00280000) +#define MCF548X_FEC_FECTFCR_UF_MSK (0x00300000) +#define MCF548X_FEC_FECTFCR_FAE_MSK (0x00600000) +#define MCF548X_FEC_FECTFCR_IP_MSK (0x00A00000) +#define MCF548X_FEC_FECTFCR_GR(x) (((x)&0x00000007)<<24|0x00200000) +#define MCF548X_FEC_FECTFCR_FRM (0x08200000) +#define MCF548X_FEC_FECTFCR_TIMER (0x10200000) +#define MCF548X_FEC_FECTFCR_WFR (0x20200000) +#define MCF548X_FEC_FECTFCR_WCTL (0x40200000) + +/* Bit definitions and macros for MCF548X_FEC_FECTLRFP */ +#define MCF548X_FEC_FECTLRFP_LRFP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECTLWFP */ +#define MCF548X_FEC_FECTLWFP_LWFP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECTFAR */ +#define MCF548X_FEC_FECTFAR_ALARM(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECTFRP */ +#define MCF548X_FEC_FECTFRP_READ(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECTFWP */ +#define MCF548X_FEC_FECTFWP_WRITE(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FRST */ +#define MCF548X_FEC_FRST_RST_CTL (0x01000000) +#define MCF548X_FEC_FRST_SW_RST (0x02000000) + +/* Bit definitions and macros for MCF548X_FEC_CTCWR */ +#define MCF548X_FEC_CTCWR_TFCW (0x01000000) +#define MCF548X_FEC_CTCWR_CRC (0x02000000) + + +/********************************************************************* +* +* System Integration Unit (SIU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_SIU_SBCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000010))) +#define MCF548X_SIU_SECSACR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000038))) +#define MCF548X_SIU_RSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000044))) +#define MCF548X_SIU_JTAGID (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000050))) + +/* Bit definitions and macros for MCF548X_SIU_SBCR */ +#define MCF548X_SIU_SBCR_PIN2DSPI (0x08000000) +#define MCF548X_SIU_SBCR_DMA2CPU (0x10000000) +#define MCF548X_SIU_SBCR_CPU2DMA (0x20000000) +#define MCF548X_SIU_SBCR_PIN2DMA (0x40000000) +#define MCF548X_SIU_SBCR_PIN2CPU (0x80000000) + +/* Bit definitions and macros for MCF548X_SIU_SECSACR */ +#define MCF548X_SIU_SECSACR_SEQEN (0x00000001) + +/* Bit definitions and macros for MCF548X_SIU_RSR */ +#define MCF548X_SIU_RSR_RST (0x00000001) +#define MCF548X_SIU_RSR_RSTWD (0x00000002) +#define MCF548X_SIU_RSR_RSTJTG (0x00000008) + +/* Bit definitions and macros for MCF548X_SIU_JTAGID */ +#define MCF548X_SIU_JTAGID_REV (0xF0000000) +#define MCF548X_SIU_JTAGID_PROCESSOR (0x0FFFFFFF) +#define MCF548X_SIU_JTAGID_MCF5485 (0x0800C01D) +#define MCF548X_SIU_JTAGID_MCF5484 (0x0800D01D) +#define MCF548X_SIU_JTAGID_MCF5483 (0x0800E01D) +#define MCF548X_SIU_JTAGID_MCF5482 (0x0800F01D) +#define MCF548X_SIU_JTAGID_MCF5481 (0x0801001D) +#define MCF548X_SIU_JTAGID_MCF5480 (0x0801101D) +#define MCF548X_SIU_JTAGID_MCF5475 (0x0801201D) +#define MCF548X_SIU_JTAGID_MCF5474 (0x0801301D) +#define MCF548X_SIU_JTAGID_MCF5473 (0x0801401D) +#define MCF548X_SIU_JTAGID_MCF5472 (0x0801501D) +#define MCF548X_SIU_JTAGID_MCF5471 (0x0801601D) +#define MCF548X_SIU_JTAGID_MCF5470 (0x0801701D) + +/********************************************************************* +* +* Comm Timer Module (CTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_CTM_CTCRF0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F00))) +#define MCF548X_CTM_CTCRF1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F04))) +#define MCF548X_CTM_CTCRF2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F08))) +#define MCF548X_CTM_CTCRF3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F0C))) +#define MCF548X_CTM_CTCRFn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F00U+((x)*0x004)))) +#define MCF548X_CTM_CTCRV4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F10))) +#define MCF548X_CTM_CTCRV5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F14))) +#define MCF548X_CTM_CTCRV6 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F18))) +#define MCF548X_CTM_CTCRV7 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F1C))) +#define MCF548X_CTM_CTCRVn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F10U+((x)*0x004)))) + +/* Bit definitions and macros for MCF548X_CTM_CTCRFn */ +#define MCF548X_CTM_CTCRFn_CRV(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_CTM_CTCRFn_S(x) (((x)&0x0000000F)<<16) +#define MCF548X_CTM_CTCRFn_PCT(x) (((x)&0x00000007)<<20) +#define MCF548X_CTM_CTCRFn_M (0x00800000) +#define MCF548X_CTM_CTCRFn_IM (0x01000000) +#define MCF548X_CTM_CTCRFn_I (0x80000000) +#define MCF548X_CTM_CTCRFn_PCT_100 (0x00000000) +#define MCF548X_CTM_CTCRFn_PCT_50 (0x00100000) +#define MCF548X_CTM_CTCRFn_PCT_25 (0x00200000) +#define MCF548X_CTM_CTCRFn_PCT_12p5 (0x00300000) +#define MCF548X_CTM_CTCRFn_PCT_6p25 (0x00400000) +#define MCF548X_CTM_CTCRFn_PCT_OFF (0x00500000) +#define MCF548X_CTM_CTCRFn_S_CLK_1 (0x00000000) +#define MCF548X_CTM_CTCRFn_S_CLK_2 (0x00010000) +#define MCF548X_CTM_CTCRFn_S_CLK_4 (0x00020000) +#define MCF548X_CTM_CTCRFn_S_CLK_8 (0x00030000) +#define MCF548X_CTM_CTCRFn_S_CLK_16 (0x00040000) +#define MCF548X_CTM_CTCRFn_S_CLK_32 (0x00050000) +#define MCF548X_CTM_CTCRFn_S_CLK_64 (0x00060000) +#define MCF548X_CTM_CTCRFn_S_CLK_128 (0x00070000) +#define MCF548X_CTM_CTCRFn_S_CLK_256 (0x00080000) + +/* Bit definitions and macros for MCF548X_CTM_CTCRVn */ +#define MCF548X_CTM_CTCRVn_CRV(x) (((x)&0x00FFFFFF)<<0) +#define MCF548X_CTM_CTCRVn_PCT(x) (((x)&0x00000007)<<24) +#define MCF548X_CTM_CTCRVn_M (0x08000000) +#define MCF548X_CTM_CTCRVn_S(x) (((x)&0x0000000F)<<28) +#define MCF548X_CTM_CTCRVn_S_CLK_1 (0x00000000) +#define MCF548X_CTM_CTCRVn_S_CLK_2 (0x10000000) +#define MCF548X_CTM_CTCRVn_S_CLK_4 (0x20000000) +#define MCF548X_CTM_CTCRVn_S_CLK_8 (0x30000000) +#define MCF548X_CTM_CTCRVn_S_CLK_16 (0x40000000) +#define MCF548X_CTM_CTCRVn_S_CLK_32 (0x50000000) +#define MCF548X_CTM_CTCRVn_S_CLK_64 (0x60000000) +#define MCF548X_CTM_CTCRVn_S_CLK_128 (0x70000000) +#define MCF548X_CTM_CTCRVn_S_CLK_256 (0x80000000) +#define MCF548X_CTM_CTCRVn_PCT_100 (0x00000000) +#define MCF548X_CTM_CTCRVn_PCT_50 (0x01000000) +#define MCF548X_CTM_CTCRVn_PCT_25 (0x02000000) +#define MCF548X_CTM_CTCRVn_PCT_12p5 (0x03000000) +#define MCF548X_CTM_CTCRVn_PCT_6p25 (0x04000000) +#define MCF548X_CTM_CTCRVn_PCT_OFF (0x05000000) + +/********************************************************************* +* +* DMA Serial Peripheral Interface (DSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_DSPI_DMCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A00))) +#define MCF548X_DSPI_DTCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A08))) +#define MCF548X_DSPI_DCTAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A0C))) +#define MCF548X_DSPI_DCTAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A10))) +#define MCF548X_DSPI_DCTAR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A14))) +#define MCF548X_DSPI_DCTAR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A18))) +#define MCF548X_DSPI_DCTAR4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A1C))) +#define MCF548X_DSPI_DCTAR5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A20))) +#define MCF548X_DSPI_DCTAR6 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A24))) +#define MCF548X_DSPI_DCTAR7 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A28))) +#define MCF548X_DSPI_DCTARn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A0CU+((x)*0x004)))) +#define MCF548X_DSPI_DSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A2C))) +#define MCF548X_DSPI_DIRSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A30))) +#define MCF548X_DSPI_DTFR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A34))) +#define MCF548X_DSPI_DRFR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A38))) +#define MCF548X_DSPI_DTFDR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A3C))) +#define MCF548X_DSPI_DTFDR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A40))) +#define MCF548X_DSPI_DTFDR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A44))) +#define MCF548X_DSPI_DTFDR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A48))) +#define MCF548X_DSPI_DTFDRn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A3CU+((x)*0x004)))) +#define MCF548X_DSPI_DRFDR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A7C))) +#define MCF548X_DSPI_DRFDR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A80))) +#define MCF548X_DSPI_DRFDR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A84))) +#define MCF548X_DSPI_DRFDR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A88))) +#define MCF548X_DSPI_DRFDRn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A7CU+((x)*0x004)))) + +/* Bit definitions and macros for MCF548X_DSPI_DMCR */ +#define MCF548X_DSPI_DMCR_HALT (0x00000001) +#define MCF548X_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) +#define MCF548X_DSPI_DMCR_CRXF (0x00000400) +#define MCF548X_DSPI_DMCR_CTXF (0x00000800) +#define MCF548X_DSPI_DMCR_DRXF (0x00001000) +#define MCF548X_DSPI_DMCR_DTXF (0x00002000) +#define MCF548X_DSPI_DMCR_CSIS0 (0x00010000) +#define MCF548X_DSPI_DMCR_CSIS2 (0x00040000) +#define MCF548X_DSPI_DMCR_CSIS3 (0x00080000) +#define MCF548X_DSPI_DMCR_CSIS5 (0x00200000) +#define MCF548X_DSPI_DMCR_ROOE (0x01000000) +#define MCF548X_DSPI_DMCR_PCSSE (0x02000000) +#define MCF548X_DSPI_DMCR_MTFE (0x04000000) +#define MCF548X_DSPI_DMCR_FRZ (0x08000000) +#define MCF548X_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) +#define MCF548X_DSPI_DMCR_CSCK (0x40000000) +#define MCF548X_DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for MCF548X_DSPI_DTCR */ +#define MCF548X_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_DSPI_DCTARn */ +#define MCF548X_DSPI_DCTARn_BR(x) (((x)&0x0000000F)<<0) +#define MCF548X_DSPI_DCTARn_DT(x) (((x)&0x0000000F)<<4) +#define MCF548X_DSPI_DCTARn_ASC(x) (((x)&0x0000000F)<<8) +#define MCF548X_DSPI_DCTARn_CSSCK(x) (((x)&0x0000000F)<<12) +#define MCF548X_DSPI_DCTARn_PBR(x) (((x)&0x00000003)<<16) +#define MCF548X_DSPI_DCTARn_PDT(x) (((x)&0x00000003)<<18) +#define MCF548X_DSPI_DCTARn_PASC(x) (((x)&0x00000003)<<20) +#define MCF548X_DSPI_DCTARn_PCSSCK(x) (((x)&0x00000003)<<22) +#define MCF548X_DSPI_DCTARn_LSBFE (0x01000000) +#define MCF548X_DSPI_DCTARn_CPHA (0x02000000) +#define MCF548X_DSPI_DCTARn_CPOL (0x04000000) +#define MCF548X_DSPI_DCTARn_TRSZ(x) (((x)&0x0000000F)<<27) +#define MCF548X_DSPI_DCTARn_PCSSCK_1CLK (0x00000000) +#define MCF548X_DSPI_DCTARn_PCSSCK_3CLK (0x00400000) +#define MCF548X_DSPI_DCTARn_PCSSCK_5CLK (0x00800000) +#define MCF548X_DSPI_DCTARn_PCSSCK_7CLK (0x00A00000) +#define MCF548X_DSPI_DCTARn_PASC_1CLK (0x00000000) +#define MCF548X_DSPI_DCTARn_PASC_3CLK (0x00100000) +#define MCF548X_DSPI_DCTARn_PASC_5CLK (0x00200000) +#define MCF548X_DSPI_DCTARn_PASC_7CLK (0x00300000) +#define MCF548X_DSPI_DCTARn_PDT_1CLK (0x00000000) +#define MCF548X_DSPI_DCTARn_PDT_3CLK (0x00040000) +#define MCF548X_DSPI_DCTARn_PDT_5CLK (0x00080000) +#define MCF548X_DSPI_DCTARn_PDT_7CLK (0x000A0000) +#define MCF548X_DSPI_DCTARn_PBR_1CLK (0x00000000) +#define MCF548X_DSPI_DCTARn_PBR_3CLK (0x00010000) +#define MCF548X_DSPI_DCTARn_PBR_5CLK (0x00020000) +#define MCF548X_DSPI_DCTARn_PBR_7CLK (0x00030000) + +/* Bit definitions and macros for MCF548X_DSPI_DSR */ +#define MCF548X_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0) +#define MCF548X_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) +#define MCF548X_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) +#define MCF548X_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) +#define MCF548X_DSPI_DSR_RFDF (0x00020000) +#define MCF548X_DSPI_DSR_RFOF (0x00080000) +#define MCF548X_DSPI_DSR_TFFF (0x02000000) +#define MCF548X_DSPI_DSR_TFUF (0x08000000) +#define MCF548X_DSPI_DSR_EOQF (0x10000000) +#define MCF548X_DSPI_DSR_TXRXS (0x40000000) +#define MCF548X_DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for MCF548X_DSPI_DIRSR */ +#define MCF548X_DSPI_DIRSR_RFDFS (0x00010000) +#define MCF548X_DSPI_DIRSR_RFDFE (0x00020000) +#define MCF548X_DSPI_DIRSR_RFOFE (0x00080000) +#define MCF548X_DSPI_DIRSR_TFFFS (0x01000000) +#define MCF548X_DSPI_DIRSR_TFFFE (0x02000000) +#define MCF548X_DSPI_DIRSR_TFUFE (0x08000000) +#define MCF548X_DSPI_DIRSR_EOQFE (0x10000000) +#define MCF548X_DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for MCF548X_DSPI_DTFR */ +#define MCF548X_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_DSPI_DTFR_CS0 (0x00010000) +#define MCF548X_DSPI_DTFR_CS2 (0x00040000) +#define MCF548X_DSPI_DTFR_CS3 (0x00080000) +#define MCF548X_DSPI_DTFR_CS5 (0x00200000) +#define MCF548X_DSPI_DTFR_CTCNT (0x04000000) +#define MCF548X_DSPI_DTFR_EOQ (0x08000000) +#define MCF548X_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) +#define MCF548X_DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for MCF548X_DSPI_DRFR */ +#define MCF548X_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF548X_DSPI_DTFDRn */ +#define MCF548X_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_DSPI_DRFDRn */ +#define MCF548X_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0) + + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_EPORT_EPPAR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000F00))) +#define MCF548X_EPORT_EPDDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F04))) +#define MCF548X_EPORT_EPIER (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F05))) +#define MCF548X_EPORT_EPDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F08))) +#define MCF548X_EPORT_EPPDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F09))) +#define MCF548X_EPORT_EPFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F0C))) + +/* Bit definitions and macros for MCF548X_EPORT_EPPAR */ +#define MCF548X_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define MCF548X_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define MCF548X_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define MCF548X_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define MCF548X_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define MCF548X_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define MCF548X_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define MCF548X_EPORT_EPPAR_EPPAx_LEVEL (0) +#define MCF548X_EPORT_EPPAR_EPPAx_RISING (1) +#define MCF548X_EPORT_EPPAR_EPPAx_FALLING (2) +#define MCF548X_EPORT_EPPAR_EPPAx_BOTH (3) + +/* Bit definitions and macros for MCF548X_EPORT_EPDDR */ +#define MCF548X_EPORT_EPDDR_EPDD1 (0x02) +#define MCF548X_EPORT_EPDDR_EPDD2 (0x04) +#define MCF548X_EPORT_EPDDR_EPDD3 (0x08) +#define MCF548X_EPORT_EPDDR_EPDD4 (0x10) +#define MCF548X_EPORT_EPDDR_EPDD5 (0x20) +#define MCF548X_EPORT_EPDDR_EPDD6 (0x40) +#define MCF548X_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF548X_EPORT_EPIER */ +#define MCF548X_EPORT_EPIER_EPIE1 (0x02) +#define MCF548X_EPORT_EPIER_EPIE2 (0x04) +#define MCF548X_EPORT_EPIER_EPIE3 (0x08) +#define MCF548X_EPORT_EPIER_EPIE4 (0x10) +#define MCF548X_EPORT_EPIER_EPIE5 (0x20) +#define MCF548X_EPORT_EPIER_EPIE6 (0x40) +#define MCF548X_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF548X_EPORT_EPDR */ +#define MCF548X_EPORT_EPDR_EPD1 (0x02) +#define MCF548X_EPORT_EPDR_EPD2 (0x04) +#define MCF548X_EPORT_EPDR_EPD3 (0x08) +#define MCF548X_EPORT_EPDR_EPD4 (0x10) +#define MCF548X_EPORT_EPDR_EPD5 (0x20) +#define MCF548X_EPORT_EPDR_EPD6 (0x40) +#define MCF548X_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF548X_EPORT_EPPDR */ +#define MCF548X_EPORT_EPPDR_EPPD1 (0x02) +#define MCF548X_EPORT_EPPDR_EPPD2 (0x04) +#define MCF548X_EPORT_EPPDR_EPPD3 (0x08) +#define MCF548X_EPORT_EPPDR_EPPD4 (0x10) +#define MCF548X_EPORT_EPPDR_EPPD5 (0x20) +#define MCF548X_EPORT_EPPDR_EPPD6 (0x40) +#define MCF548X_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF548X_EPORT_EPFR */ +#define MCF548X_EPORT_EPFR_EPF1 (0x02) +#define MCF548X_EPORT_EPFR_EPF2 (0x04) +#define MCF548X_EPORT_EPFR_EPF3 (0x08) +#define MCF548X_EPORT_EPFR_EPF4 (0x10) +#define MCF548X_EPORT_EPFR_EPF5 (0x20) +#define MCF548X_EPORT_EPFR_EPF6 (0x40) +#define MCF548X_EPORT_EPFR_EPF7 (0x80) + +/********************************************************************* +* +* FlexBus Chip Selects (FBCS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_FBCS_CSAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000500))) +#define MCF548X_FBCS_CSMR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000504))) +#define MCF548X_FBCS_CSCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000508))) +#define MCF548X_FBCS_CSAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00050C))) +#define MCF548X_FBCS_CSMR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000510))) +#define MCF548X_FBCS_CSCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000514))) +#define MCF548X_FBCS_CSAR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000518))) +#define MCF548X_FBCS_CSMR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00051C))) +#define MCF548X_FBCS_CSCR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000520))) +#define MCF548X_FBCS_CSAR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000524))) +#define MCF548X_FBCS_CSMR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000528))) +#define MCF548X_FBCS_CSCR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00052C))) +#define MCF548X_FBCS_CSAR4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000530))) +#define MCF548X_FBCS_CSMR4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000534))) +#define MCF548X_FBCS_CSCR4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000538))) +#define MCF548X_FBCS_CSAR5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00053C))) +#define MCF548X_FBCS_CSMR5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000540))) +#define MCF548X_FBCS_CSCR5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000544))) +#define MCF548X_FBCS_CSAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000500U+((x)*0x00C)))) +#define MCF548X_FBCS_CSMR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000504U+((x)*0x00C)))) +#define MCF548X_FBCS_CSCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000508U+((x)*0x00C)))) + +/* Bit definitions and macros for MCF548X_FBCS_CSAR */ +#define MCF548X_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF548X_FBCS_CSMR */ +#define MCF548X_FBCS_CSMR_V (0x00000001) +#define MCF548X_FBCS_CSMR_WP (0x00000100) +#define MCF548X_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) +#define MCF548X_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF548X_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF548X_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF548X_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF548X_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF548X_FBCS_CSMR_BAM_256M (0x0FFF0000) +#define MCF548X_FBCS_CSMR_BAM_128M (0x07FF0000) +#define MCF548X_FBCS_CSMR_BAM_64M (0x03FF0000) +#define MCF548X_FBCS_CSMR_BAM_32M (0x01FF0000) +#define MCF548X_FBCS_CSMR_BAM_16M (0x00FF0000) +#define MCF548X_FBCS_CSMR_BAM_8M (0x007F0000) +#define MCF548X_FBCS_CSMR_BAM_4M (0x003F0000) +#define MCF548X_FBCS_CSMR_BAM_2M (0x001F0000) +#define MCF548X_FBCS_CSMR_BAM_1M (0x000F0000) +#define MCF548X_FBCS_CSMR_BAM_1024K (0x000F0000) +#define MCF548X_FBCS_CSMR_BAM_512K (0x00070000) +#define MCF548X_FBCS_CSMR_BAM_256K (0x00030000) +#define MCF548X_FBCS_CSMR_BAM_128K (0x00010000) +#define MCF548X_FBCS_CSMR_BAM_64K (0x00000000) + +/* Bit definitions and macros for MCF548X_FBCS_CSCR */ +#define MCF548X_FBCS_CSCR_BSTW (0x00000008) +#define MCF548X_FBCS_CSCR_BSTR (0x00000010) +#define MCF548X_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) +#define MCF548X_FBCS_CSCR_AA (0x00000100) +#define MCF548X_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) +#define MCF548X_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) +#define MCF548X_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) +#define MCF548X_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) +#define MCF548X_FBCS_CSCR_SWSEN (0x00800000) +#define MCF548X_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) +#define MCF548X_FBCS_CSCR_PS_8 (0x00000040) +#define MCF548X_FBCS_CSCR_PS_16 (0x00000080) +#define MCF548X_FBCS_CSCR_PS_32 (0x00000000) + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_GPIO_PODR_FBCTL (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A00))) +#define MCF548X_GPIO_PODR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A01))) +#define MCF548X_GPIO_PODR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A02))) +#define MCF548X_GPIO_PODR_FEC0H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A04))) +#define MCF548X_GPIO_PODR_FEC0L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A05))) +#define MCF548X_GPIO_PODR_FEC1H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A06))) +#define MCF548X_GPIO_PODR_FEC1L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A07))) +#define MCF548X_GPIO_PODR_FECI2C (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A08))) +#define MCF548X_GPIO_PODR_PCIBG (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A09))) +#define MCF548X_GPIO_PODR_PCIBR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A0A))) +#define MCF548X_GPIO_PODR_PSC3PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A0C))) +#define MCF548X_GPIO_PODR_PSC1PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A0D))) +#define MCF548X_GPIO_PODR_DSPI (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A0E))) +#define MCF548X_GPIO_PDDR_FBCTL (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A10))) +#define MCF548X_GPIO_PDDR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A11))) +#define MCF548X_GPIO_PDDR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A12))) +#define MCF548X_GPIO_PDDR_FEC0H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A14))) +#define MCF548X_GPIO_PDDR_FEC0L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A15))) +#define MCF548X_GPIO_PDDR_FEC1H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A16))) +#define MCF548X_GPIO_PDDR_FEC1L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A17))) +#define MCF548X_GPIO_PDDR_FECI2C (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A18))) +#define MCF548X_GPIO_PDDR_PCIBG (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A19))) +#define MCF548X_GPIO_PDDR_PCIBR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A1A))) +#define MCF548X_GPIO_PDDR_PSC3PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A1C))) +#define MCF548X_GPIO_PDDR_PSC1PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A1D))) +#define MCF548X_GPIO_PDDR_DSPI (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A1E))) +#define MCF548X_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A20))) +#define MCF548X_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A21))) +#define MCF548X_GPIO_PPDSDR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A22))) +#define MCF548X_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A24))) +#define MCF548X_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A25))) +#define MCF548X_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A26))) +#define MCF548X_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A27))) +#define MCF548X_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A28))) +#define MCF548X_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A29))) +#define MCF548X_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A2A))) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A2C))) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A2D))) +#define MCF548X_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A2E))) +#define MCF548X_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A30))) +#define MCF548X_GPIO_PCLRR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A31))) +#define MCF548X_GPIO_PCLRR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A32))) +#define MCF548X_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A34))) +#define MCF548X_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A35))) +#define MCF548X_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A36))) +#define MCF548X_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A37))) +#define MCF548X_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A38))) +#define MCF548X_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A39))) +#define MCF548X_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A3A))) +#define MCF548X_GPIO_PCLRR_PSC3PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A3C))) +#define MCF548X_GPIO_PCLRR_PSC1PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A3D))) +#define MCF548X_GPIO_PCLRR_DSPI (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A3E))) +#define MCF548X_GPIO_PAR_FBCTL (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A40))) +#define MCF548X_GPIO_PAR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A42))) +#define MCF548X_GPIO_PAR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A43))) +#define MCF548X_GPIO_PAR_FECI2CIRQ (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A44))) +#define MCF548X_GPIO_PAR_PCIBG (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A48))) +#define MCF548X_GPIO_PAR_PCIBR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A4A))) +#define MCF548X_GPIO_PAR_PSC3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A4C))) +#define MCF548X_GPIO_PAR_PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A4D))) +#define MCF548X_GPIO_PAR_PSC1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A4E))) +#define MCF548X_GPIO_PAR_PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A4F))) +#define MCF548X_GPIO_PAR_DSPI (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A50))) +#define MCF548X_GPIO_PAR_TIMER (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A52))) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FBCTL */ +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x01) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x02) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x04) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x08) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FBCS */ +#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS1 (0x02) +#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS2 (0x04) +#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS3 (0x08) +#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) +#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_DMA */ +#define MCF548X_GPIO_PODR_DMA_PODR_DMA0 (0x01) +#define MCF548X_GPIO_PODR_DMA_PODR_DMA1 (0x02) +#define MCF548X_GPIO_PODR_DMA_PODR_DMA2 (0x04) +#define MCF548X_GPIO_PODR_DMA_PODR_DMA3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FEC0H */ +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x01) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x02) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x04) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x08) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FEC0L */ +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x01) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x02) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x04) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x08) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FEC1H */ +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x01) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x02) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x04) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x08) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FEC1L */ +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x01) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x02) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x04) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x08) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FECI2C */ +#define MCF548X_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) +#define MCF548X_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) +#define MCF548X_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) +#define MCF548X_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_PCIBG */ +#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x01) +#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x02) +#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x04) +#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x08) +#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_PCIBR */ +#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x01) +#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x02) +#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x04) +#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x08) +#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_PSC3PSC2 */ +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC20 (0x01) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC21 (0x02) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC22 (0x04) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC23 (0x08) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC24 (0x10) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC25 (0x20) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC26 (0x40) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_PSC1PSC0 */ +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC00 (0x01) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC01 (0x02) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC02 (0x04) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC03 (0x08) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC04 (0x10) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC05 (0x20) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC06 (0x40) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_DSPI */ +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI0 (0x01) +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI1 (0x02) +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI2 (0x04) +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI3 (0x08) +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FBCTL */ +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x01) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x02) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x04) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x08) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FBCS */ +#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x02) +#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x04) +#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x08) +#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) +#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_DMA */ +#define MCF548X_GPIO_PDDR_DMA_PDDR_DMA0 (0x01) +#define MCF548X_GPIO_PDDR_DMA_PDDR_DMA1 (0x02) +#define MCF548X_GPIO_PDDR_DMA_PDDR_DMA2 (0x04) +#define MCF548X_GPIO_PDDR_DMA_PDDR_DMA3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FEC0H */ +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x01) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x02) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x04) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x08) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FEC0L */ +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x01) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x02) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x04) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x08) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FEC1H */ +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x01) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x02) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x04) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x08) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FEC1L */ +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x01) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x02) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x04) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x08) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FECI2C */ +#define MCF548X_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) +#define MCF548X_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) +#define MCF548X_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) +#define MCF548X_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_PCIBG */ +#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x01) +#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x02) +#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x04) +#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x08) +#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_PCIBR */ +#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x01) +#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x02) +#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x04) +#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x08) +#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_PSC3PSC2 */ +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC20 (0x01) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC21 (0x02) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC22 (0x04) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC23 (0x08) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC26 (0x40) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_PSC1PSC0 */ +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC00 (0x01) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC02 (0x04) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC04 (0x10) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC05 (0x20) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC06 (0x40) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_DSPI */ +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x01) +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x02) +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x04) +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x08) +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FBCTL */ +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x01) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x02) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x04) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x08) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FBCS */ +#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x02) +#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x04) +#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x08) +#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) +#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_DMA */ +#define MCF548X_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x01) +#define MCF548X_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x02) +#define MCF548X_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x04) +#define MCF548X_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FEC0H */ +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x01) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x02) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x04) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x08) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FEC0L */ +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x01) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x02) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x04) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x08) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FEC1H */ +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x01) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x02) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x04) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x08) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FEC1L */ +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x01) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x02) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x04) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x08) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FECI2C */ +#define MCF548X_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) +#define MCF548X_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) +#define MCF548X_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) +#define MCF548X_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_PCIBG */ +#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x01) +#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x02) +#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x04) +#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x08) +#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_PCIBR */ +#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x01) +#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x02) +#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x04) +#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x08) +#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_PSC3PSC2 */ +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC20 (0x01) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC21 (0x02) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC22 (0x04) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC23 (0x08) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC26 (0x40) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_PSC1PSC0 */ +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC00 (0x01) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC02 (0x04) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC04 (0x10) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC05 (0x20) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC06 (0x40) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_DSPI */ +#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x01) +#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x02) +#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x04) +#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x08) +#define MCF548X_GPIO_PPDSDR_DSPI_PDDR_DSPI4 (0x10) +#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) +#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FBCTL */ +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x01) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x02) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x04) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x08) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FBCS */ +#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x02) +#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x04) +#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x08) +#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) +#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_DMA */ +#define MCF548X_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x01) +#define MCF548X_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x02) +#define MCF548X_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x04) +#define MCF548X_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FEC0H */ +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x01) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x02) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x04) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x08) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FEC0L */ +#define MCF548X_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x01) +#define MCF548X_GPIO_PCLRR_FEC0L_PODR_FEC0L1 (0x02) +#define MCF548X_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x04) +#define MCF548X_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x08) +#define MCF548X_GPIO_PCLRR_FEC0L_PODR_FEC0L4 (0x10) +#define MCF548X_GPIO_PCLRR_FEC0L_PODR_FEC0L5 (0x20) +#define MCF548X_GPIO_PCLRR_FEC0L_PODR_FEC0L6 (0x40) +#define MCF548X_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FEC1H */ +#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x01) +#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x02) +#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x04) +#define MCF548X_GPIO_PCLRR_FEC1H_PODR_FEC1H3 (0x08) +#define MCF548X_GPIO_PCLRR_FEC1H_PODR_FEC1H4 (0x10) +#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) +#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) +#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FEC1L */ +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x01) +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x02) +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x04) +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x08) +#define MCF548X_GPIO_PCLRR_FEC1L_PODR_FEC1L4 (0x10) +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FECI2C */ +#define MCF548X_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) +#define MCF548X_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) +#define MCF548X_GPIO_PCLRR_FECI2C_PODR_FECI2C2 (0x04) +#define MCF548X_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_PCIBG */ +#define MCF548X_GPIO_PCLRR_PCIBG_PODR_PCIBG0 (0x01) +#define MCF548X_GPIO_PCLRR_PCIBG_PODR_PCIBG1 (0x02) +#define MCF548X_GPIO_PCLRR_PCIBG_PODR_PCIBG2 (0x04) +#define MCF548X_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x08) +#define MCF548X_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_PCIBR */ +#define MCF548X_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x01) +#define MCF548X_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x02) +#define MCF548X_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x04) +#define MCF548X_GPIO_PCLRR_PCIBR_PODR_PCIBR3 (0x08) +#define MCF548X_GPIO_PCLRR_PCIBR_PODR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_PSC3PSC2 */ +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC20 (0x01) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC21 (0x02) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC22 (0x04) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC23 (0x08) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC24 (0x10) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC25 (0x20) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC26 (0x40) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_PSC1PSC0 */ +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC00 (0x01) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC01 (0x02) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC02 (0x04) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC03 (0x08) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC04 (0x10) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC05 (0x20) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PODR_PSC1PSC06 (0x40) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_DSPI */ +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x01) +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x02) +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x04) +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x08) +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_FBCTL */ +#define MCF548X_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0) +#define MCF548X_GPIO_PAR_FBCTL_PAR_TA (0x0004) +#define MCF548X_GPIO_PAR_FBCTL_PAR_RWB(x) (((x)&0x0003)<<4) +#define MCF548X_GPIO_PAR_FBCTL_PAR_OE (0x0040) +#define MCF548X_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100) +#define MCF548X_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400) +#define MCF548X_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000) +#define MCF548X_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000) +#define MCF548X_GPIO_PAR_FBCTL_PAR_TS_GPIO (0) +#define MCF548X_GPIO_PAR_FBCTL_PAR_TS_TBST (2) +#define MCF548X_GPIO_PAR_FBCTL_PAR_TS_TS (3) +#define MCF548X_GPIO_PAR_FBCTL_PAR_RWB_GPIO (0x0000) +#define MCF548X_GPIO_PAR_FBCTL_PAR_RWB_TBST (0x0020) +#define MCF548X_GPIO_PAR_FBCTL_PAR_RWB_RWB (0x0030) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_FBCS */ +#define MCF548X_GPIO_PAR_FBCS_PAR_CS1 (0x02) +#define MCF548X_GPIO_PAR_FBCS_PAR_CS2 (0x04) +#define MCF548X_GPIO_PAR_FBCS_PAR_CS3 (0x08) +#define MCF548X_GPIO_PAR_FBCS_PAR_CS4 (0x10) +#define MCF548X_GPIO_PAR_FBCS_PAR_CS5 (0x20) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_DMA */ +#define MCF548X_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0) +#define MCF548X_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2) +#define MCF548X_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4) +#define MCF548X_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6) +#define MCF548X_GPIO_PAR_DMA_PAR_DACKx_GPIO (0) +#define MCF548X_GPIO_PAR_DMA_PAR_DACKx_TOUT (2) +#define MCF548X_GPIO_PAR_DMA_PAR_DACKx_DACK (3) +#define MCF548X_GPIO_PAR_DMA_PAR_DREQx_GPIO (0) +#define MCF548X_GPIO_PAR_DMA_PAR_DREQx_TIN (2) +#define MCF548X_GPIO_PAR_DMA_PAR_DREQx_DREQ (3) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_FECI2CIRQ */ +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_PCIBG */ +#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0) +#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2) +#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4) +#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6) +#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_PCIBR */ +#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBG0(x) (((x)&0x0003)<<0) +#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBG1(x) (((x)&0x0003)<<2) +#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBG2(x) (((x)&0x0003)<<4) +#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBG3(x) (((x)&0x0003)<<6) +#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_PSC3 */ +#define MCF548X_GPIO_PAR_PSC3_PAR_TXD3 (0x04) +#define MCF548X_GPIO_PAR_PSC3_PAR_RXD3 (0x08) +#define MCF548X_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4) +#define MCF548X_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6) +#define MCF548X_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80) +#define MCF548X_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0) +#define MCF548X_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20) +#define MCF548X_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30) +#define MCF548X_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_PSC2 */ +#define MCF548X_GPIO_PAR_PSC2_PAR_TXD2 (0x04) +#define MCF548X_GPIO_PAR_PSC2_PAR_RXD2 (0x08) +#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4) +#define MCF548X_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6) +#define MCF548X_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80) +#define MCF548X_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0) +#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10) +#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20) +#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_PSC1 */ +#define MCF548X_GPIO_PAR_PSC1_PAR_TXD1 (0x04) +#define MCF548X_GPIO_PAR_PSC1_PAR_RXD1 (0x08) +#define MCF548X_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4) +#define MCF548X_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6) +#define MCF548X_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80) +#define MCF548X_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0) +#define MCF548X_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20) +#define MCF548X_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_PSC0 */ +#define MCF548X_GPIO_PAR_PSC0_PAR_TXD0 (0x04) +#define MCF548X_GPIO_PAR_PSC0_PAR_RXD0 (0x08) +#define MCF548X_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4) +#define MCF548X_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6) +#define MCF548X_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80) +#define MCF548X_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0) +#define MCF548X_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20) +#define MCF548X_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_DSPI */ +#define MCF548X_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0) +#define MCF548X_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2) +#define MCF548X_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS5 (0x1000) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0) +#define MCF548X_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000) +#define MCF548X_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010) +#define MCF548X_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020) +#define MCF548X_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030) +#define MCF548X_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000) +#define MCF548X_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008) +#define MCF548X_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C) +#define MCF548X_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000) +#define MCF548X_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002) +#define MCF548X_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_TIMER */ +#define MCF548X_GPIO_PAR_TIMER_PAR_TOUT2 (0x01) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1) +#define MCF548X_GPIO_PAR_TIMER_PAR_TOUT3 (0x08) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06) + +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_GPT_GMS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000800))) +#define MCF548X_GPT_GCIR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000804))) +#define MCF548X_GPT_GPWM0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000808))) +#define MCF548X_GPT_GSR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00080C))) +#define MCF548X_GPT_GMS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000810))) +#define MCF548X_GPT_GCIR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000814))) +#define MCF548X_GPT_GPWM1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000818))) +#define MCF548X_GPT_GSR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00081C))) +#define MCF548X_GPT_GMS2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000820))) +#define MCF548X_GPT_GCIR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000824))) +#define MCF548X_GPT_GPWM2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000828))) +#define MCF548X_GPT_GSR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00082C))) +#define MCF548X_GPT_GMS3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000830))) +#define MCF548X_GPT_GCIR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000834))) +#define MCF548X_GPT_GPWM3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000838))) +#define MCF548X_GPT_GSR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00083C))) +#define MCF548X_GPT_GMS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000800U+((x)*0x010)))) +#define MCF548X_GPT_GCIR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000804U+((x)*0x010)))) +#define MCF548X_GPT_GPWM(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000808U+((x)*0x010)))) +#define MCF548X_GPT_GSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00080CU+((x)*0x010)))) + +/* Bit definitions and macros for MCF548X_GPT_GMS */ +#define MCF548X_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) +#define MCF548X_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) +#define MCF548X_GPT_GMS_IEN (0x00000100) +#define MCF548X_GPT_GMS_OD (0x00000200) +#define MCF548X_GPT_GMS_SC (0x00000400) +#define MCF548X_GPT_GMS_CE (0x00001000) +#define MCF548X_GPT_GMS_WDEN (0x00008000) +#define MCF548X_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) +#define MCF548X_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) +#define MCF548X_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) +#define MCF548X_GPT_GMS_OCT_FRCLOW (0x00000000) +#define MCF548X_GPT_GMS_OCT_PULSEHI (0x00100000) +#define MCF548X_GPT_GMS_OCT_PULSELO (0x00200000) +#define MCF548X_GPT_GMS_OCT_TOGGLE (0x00300000) +#define MCF548X_GPT_GMS_ICT_ANY (0x00000000) +#define MCF548X_GPT_GMS_ICT_RISE (0x00010000) +#define MCF548X_GPT_GMS_ICT_FALL (0x00020000) +#define MCF548X_GPT_GMS_ICT_PULSE (0x00030000) +#define MCF548X_GPT_GMS_GPIO_INPUT (0x00000000) +#define MCF548X_GPT_GMS_GPIO_OUTLO (0x00000020) +#define MCF548X_GPT_GMS_GPIO_OUTHI (0x00000030) +#define MCF548X_GPT_GMS_TMS_DISABLE (0x00000000) +#define MCF548X_GPT_GMS_TMS_INCAPT (0x00000001) +#define MCF548X_GPT_GMS_TMS_OUTCAPT (0x00000002) +#define MCF548X_GPT_GMS_TMS_PWM (0x00000003) +#define MCF548X_GPT_GMS_TMS_GPIO (0x00000004) + +/* Bit definitions and macros for MCF548X_GPT_GCIR */ +#define MCF548X_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_GPT_GPWM */ +#define MCF548X_GPT_GPWM_LOAD (0x00000001) +#define MCF548X_GPT_GPWM_PWMOP (0x00000100) +#define MCF548X_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_GPT_GSR */ +#define MCF548X_GPT_GSR_CAPT (0x00000001) +#define MCF548X_GPT_GSR_COMP (0x00000002) +#define MCF548X_GPT_GSR_PWMP (0x00000004) +#define MCF548X_GPT_GSR_TEXP (0x00000008) +#define MCF548X_GPT_GSR_PIN (0x00000100) +#define MCF548X_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) +#define MCF548X_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) + + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_I2C_I2AR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F00))) +#define MCF548X_I2C_I2FDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F04))) +#define MCF548X_I2C_I2CR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F08))) +#define MCF548X_I2C_I2SR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F0C))) +#define MCF548X_I2C_I2DR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F10))) +#define MCF548X_I2C_I2ICR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F20))) + +/* Bit definitions and macros for MCF548X_I2C_I2AR */ +#define MCF548X_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF548X_I2C_I2FDR */ +#define MCF548X_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF548X_I2C_I2CR */ +#define MCF548X_I2C_I2CR_RSTA (0x04) +#define MCF548X_I2C_I2CR_TXAK (0x08) +#define MCF548X_I2C_I2CR_MTX (0x10) +#define MCF548X_I2C_I2CR_MSTA (0x20) +#define MCF548X_I2C_I2CR_IIEN (0x40) +#define MCF548X_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF548X_I2C_I2SR */ +#define MCF548X_I2C_I2SR_RXAK (0x01) +#define MCF548X_I2C_I2SR_IIF (0x02) +#define MCF548X_I2C_I2SR_SRW (0x04) +#define MCF548X_I2C_I2SR_IAL (0x10) +#define MCF548X_I2C_I2SR_IBB (0x20) +#define MCF548X_I2C_I2SR_IAAS (0x40) +#define MCF548X_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF548X_I2C_I2ICR */ +#define MCF548X_I2C_I2ICR_IE (0x01) +#define MCF548X_I2C_I2ICR_RE (0x02) +#define MCF548X_I2C_I2ICR_TE (0x04) +#define MCF548X_I2C_I2ICR_BNBE (0x08) + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_INTC_IPRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000700))) +#define MCF548X_INTC_IPRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000704))) +#define MCF548X_INTC_IMRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000708))) +#define MCF548X_INTC_IMRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00070C))) +#define MCF548X_INTC_INTFRCH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000710))) +#define MCF548X_INTC_INTFRCL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000714))) +#define MCF548X_INTC_IRLR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000718))) +#define MCF548X_INTC_IACKLPR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000719))) +#define MCF548X_INTC_ICR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000740))) +#define MCF548X_INTC_ICR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000741))) +#define MCF548X_INTC_ICR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000742))) +#define MCF548X_INTC_ICR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000743))) +#define MCF548X_INTC_ICR4 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000744))) +#define MCF548X_INTC_ICR5 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000745))) +#define MCF548X_INTC_ICR6 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000746))) +#define MCF548X_INTC_ICR7 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000747))) +#define MCF548X_INTC_ICR8 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000748))) +#define MCF548X_INTC_ICR9 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000749))) +#define MCF548X_INTC_ICR10 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074A))) +#define MCF548X_INTC_ICR11 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074B))) +#define MCF548X_INTC_ICR12 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074C))) +#define MCF548X_INTC_ICR13 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074D))) +#define MCF548X_INTC_ICR14 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074E))) +#define MCF548X_INTC_ICR15 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074F))) +#define MCF548X_INTC_ICR16 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000750))) +#define MCF548X_INTC_ICR17 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000751))) +#define MCF548X_INTC_ICR18 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000752))) +#define MCF548X_INTC_ICR19 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000753))) +#define MCF548X_INTC_ICR20 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000754))) +#define MCF548X_INTC_ICR21 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000755))) +#define MCF548X_INTC_ICR22 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000756))) +#define MCF548X_INTC_ICR23 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000757))) +#define MCF548X_INTC_ICR24 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000758))) +#define MCF548X_INTC_ICR25 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000759))) +#define MCF548X_INTC_ICR26 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075A))) +#define MCF548X_INTC_ICR27 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075B))) +#define MCF548X_INTC_ICR28 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075C))) +#define MCF548X_INTC_ICR29 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075D))) +#define MCF548X_INTC_ICR30 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075E))) +#define MCF548X_INTC_ICR31 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075F))) +#define MCF548X_INTC_ICR32 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000760))) +#define MCF548X_INTC_ICR33 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000761))) +#define MCF548X_INTC_ICR34 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000762))) +#define MCF548X_INTC_ICR35 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000763))) +#define MCF548X_INTC_ICR36 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000764))) +#define MCF548X_INTC_ICR37 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000765))) +#define MCF548X_INTC_ICR38 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000766))) +#define MCF548X_INTC_ICR39 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000767))) +#define MCF548X_INTC_ICR40 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000768))) +#define MCF548X_INTC_ICR41 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000769))) +#define MCF548X_INTC_ICR42 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076A))) +#define MCF548X_INTC_ICR43 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076B))) +#define MCF548X_INTC_ICR44 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076C))) +#define MCF548X_INTC_ICR45 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076D))) +#define MCF548X_INTC_ICR46 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076E))) +#define MCF548X_INTC_ICR47 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076F))) +#define MCF548X_INTC_ICR48 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000770))) +#define MCF548X_INTC_ICR49 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000771))) +#define MCF548X_INTC_ICR50 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000772))) +#define MCF548X_INTC_ICR51 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000773))) +#define MCF548X_INTC_ICR52 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000774))) +#define MCF548X_INTC_ICR53 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000775))) +#define MCF548X_INTC_ICR54 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000776))) +#define MCF548X_INTC_ICR55 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000777))) +#define MCF548X_INTC_ICR56 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000778))) +#define MCF548X_INTC_ICR57 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000779))) +#define MCF548X_INTC_ICR58 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077A))) +#define MCF548X_INTC_ICR59 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077B))) +#define MCF548X_INTC_ICR60 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077C))) +#define MCF548X_INTC_ICR61 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077D))) +#define MCF548X_INTC_ICR62 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077E))) +#define MCF548X_INTC_ICR63 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077F))) +#define MCF548X_INTC_ICRn(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000740U+((x)*0x001)))) +#define MCF548X_INTC_SWIACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007E0))) +#define MCF548X_INTC_L1IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007E4))) +#define MCF548X_INTC_L2IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007E8))) +#define MCF548X_INTC_L3IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007EC))) +#define MCF548X_INTC_L4IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007F0))) +#define MCF548X_INTC_L5IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007F4))) +#define MCF548X_INTC_L6IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007F8))) +#define MCF548X_INTC_L7IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007FC))) +#define MCF548X_INTC_LnIACK(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007E4U+((x)*0x004)))) + +/* Bit definitions and macros for MCF548X_INTC_IPRH */ +#define MCF548X_INTC_IPRH_INT32 (0x00000001) +#define MCF548X_INTC_IPRH_INT33 (0x00000002) +#define MCF548X_INTC_IPRH_INT34 (0x00000004) +#define MCF548X_INTC_IPRH_INT35 (0x00000008) +#define MCF548X_INTC_IPRH_INT36 (0x00000010) +#define MCF548X_INTC_IPRH_INT37 (0x00000020) +#define MCF548X_INTC_IPRH_INT38 (0x00000040) +#define MCF548X_INTC_IPRH_INT39 (0x00000080) +#define MCF548X_INTC_IPRH_INT40 (0x00000100) +#define MCF548X_INTC_IPRH_INT41 (0x00000200) +#define MCF548X_INTC_IPRH_INT42 (0x00000400) +#define MCF548X_INTC_IPRH_INT43 (0x00000800) +#define MCF548X_INTC_IPRH_INT44 (0x00001000) +#define MCF548X_INTC_IPRH_INT45 (0x00002000) +#define MCF548X_INTC_IPRH_INT46 (0x00004000) +#define MCF548X_INTC_IPRH_INT47 (0x00008000) +#define MCF548X_INTC_IPRH_INT48 (0x00010000) +#define MCF548X_INTC_IPRH_INT49 (0x00020000) +#define MCF548X_INTC_IPRH_INT50 (0x00040000) +#define MCF548X_INTC_IPRH_INT51 (0x00080000) +#define MCF548X_INTC_IPRH_INT52 (0x00100000) +#define MCF548X_INTC_IPRH_INT53 (0x00200000) +#define MCF548X_INTC_IPRH_INT54 (0x00400000) +#define MCF548X_INTC_IPRH_INT55 (0x00800000) +#define MCF548X_INTC_IPRH_INT56 (0x01000000) +#define MCF548X_INTC_IPRH_INT57 (0x02000000) +#define MCF548X_INTC_IPRH_INT58 (0x04000000) +#define MCF548X_INTC_IPRH_INT59 (0x08000000) +#define MCF548X_INTC_IPRH_INT60 (0x10000000) +#define MCF548X_INTC_IPRH_INT61 (0x20000000) +#define MCF548X_INTC_IPRH_INT62 (0x40000000) +#define MCF548X_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF548X_INTC_IPRL */ +#define MCF548X_INTC_IPRL_INT1 (0x00000002) +#define MCF548X_INTC_IPRL_INT2 (0x00000004) +#define MCF548X_INTC_IPRL_INT3 (0x00000008) +#define MCF548X_INTC_IPRL_INT4 (0x00000010) +#define MCF548X_INTC_IPRL_INT5 (0x00000020) +#define MCF548X_INTC_IPRL_INT6 (0x00000040) +#define MCF548X_INTC_IPRL_INT7 (0x00000080) +#define MCF548X_INTC_IPRL_INT8 (0x00000100) +#define MCF548X_INTC_IPRL_INT9 (0x00000200) +#define MCF548X_INTC_IPRL_INT10 (0x00000400) +#define MCF548X_INTC_IPRL_INT11 (0x00000800) +#define MCF548X_INTC_IPRL_INT12 (0x00001000) +#define MCF548X_INTC_IPRL_INT13 (0x00002000) +#define MCF548X_INTC_IPRL_INT14 (0x00004000) +#define MCF548X_INTC_IPRL_INT15 (0x00008000) +#define MCF548X_INTC_IPRL_INT16 (0x00010000) +#define MCF548X_INTC_IPRL_INT17 (0x00020000) +#define MCF548X_INTC_IPRL_INT18 (0x00040000) +#define MCF548X_INTC_IPRL_INT19 (0x00080000) +#define MCF548X_INTC_IPRL_INT20 (0x00100000) +#define MCF548X_INTC_IPRL_INT21 (0x00200000) +#define MCF548X_INTC_IPRL_INT22 (0x00400000) +#define MCF548X_INTC_IPRL_INT23 (0x00800000) +#define MCF548X_INTC_IPRL_INT24 (0x01000000) +#define MCF548X_INTC_IPRL_INT25 (0x02000000) +#define MCF548X_INTC_IPRL_INT26 (0x04000000) +#define MCF548X_INTC_IPRL_INT27 (0x08000000) +#define MCF548X_INTC_IPRL_INT28 (0x10000000) +#define MCF548X_INTC_IPRL_INT29 (0x20000000) +#define MCF548X_INTC_IPRL_INT30 (0x40000000) +#define MCF548X_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF548X_INTC_IMRH */ +#define MCF548X_INTC_IMRH_INT_MASK32 (0x00000001) +#define MCF548X_INTC_IMRH_INT_MASK33 (0x00000002) +#define MCF548X_INTC_IMRH_INT_MASK34 (0x00000004) +#define MCF548X_INTC_IMRH_INT_MASK35 (0x00000008) +#define MCF548X_INTC_IMRH_INT_MASK36 (0x00000010) +#define MCF548X_INTC_IMRH_INT_MASK37 (0x00000020) +#define MCF548X_INTC_IMRH_INT_MASK38 (0x00000040) +#define MCF548X_INTC_IMRH_INT_MASK39 (0x00000080) +#define MCF548X_INTC_IMRH_INT_MASK40 (0x00000100) +#define MCF548X_INTC_IMRH_INT_MASK41 (0x00000200) +#define MCF548X_INTC_IMRH_INT_MASK42 (0x00000400) +#define MCF548X_INTC_IMRH_INT_MASK43 (0x00000800) +#define MCF548X_INTC_IMRH_INT_MASK44 (0x00001000) +#define MCF548X_INTC_IMRH_INT_MASK45 (0x00002000) +#define MCF548X_INTC_IMRH_INT_MASK46 (0x00004000) +#define MCF548X_INTC_IMRH_INT_MASK47 (0x00008000) +#define MCF548X_INTC_IMRH_INT_MASK48 (0x00010000) +#define MCF548X_INTC_IMRH_INT_MASK49 (0x00020000) +#define MCF548X_INTC_IMRH_INT_MASK50 (0x00040000) +#define MCF548X_INTC_IMRH_INT_MASK51 (0x00080000) +#define MCF548X_INTC_IMRH_INT_MASK52 (0x00100000) +#define MCF548X_INTC_IMRH_INT_MASK53 (0x00200000) +#define MCF548X_INTC_IMRH_INT_MASK54 (0x00400000) +#define MCF548X_INTC_IMRH_INT_MASK55 (0x00800000) +#define MCF548X_INTC_IMRH_INT_MASK56 (0x01000000) +#define MCF548X_INTC_IMRH_INT_MASK57 (0x02000000) +#define MCF548X_INTC_IMRH_INT_MASK58 (0x04000000) +#define MCF548X_INTC_IMRH_INT_MASK59 (0x08000000) +#define MCF548X_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF548X_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF548X_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF548X_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF548X_INTC_IMRL */ +#define MCF548X_INTC_IMRL_MASKALL (0x00000001) +#define MCF548X_INTC_IMRL_INT_MASK1 (0x00000002) +#define MCF548X_INTC_IMRL_INT_MASK2 (0x00000004) +#define MCF548X_INTC_IMRL_INT_MASK3 (0x00000008) +#define MCF548X_INTC_IMRL_INT_MASK4 (0x00000010) +#define MCF548X_INTC_IMRL_INT_MASK5 (0x00000020) +#define MCF548X_INTC_IMRL_INT_MASK6 (0x00000040) +#define MCF548X_INTC_IMRL_INT_MASK7 (0x00000080) +#define MCF548X_INTC_IMRL_INT_MASK8 (0x00000100) +#define MCF548X_INTC_IMRL_INT_MASK9 (0x00000200) +#define MCF548X_INTC_IMRL_INT_MASK10 (0x00000400) +#define MCF548X_INTC_IMRL_INT_MASK11 (0x00000800) +#define MCF548X_INTC_IMRL_INT_MASK12 (0x00001000) +#define MCF548X_INTC_IMRL_INT_MASK13 (0x00002000) +#define MCF548X_INTC_IMRL_INT_MASK14 (0x00004000) +#define MCF548X_INTC_IMRL_INT_MASK15 (0x00008000) +#define MCF548X_INTC_IMRL_INT_MASK16 (0x00010000) +#define MCF548X_INTC_IMRL_INT_MASK17 (0x00020000) +#define MCF548X_INTC_IMRL_INT_MASK18 (0x00040000) +#define MCF548X_INTC_IMRL_INT_MASK19 (0x00080000) +#define MCF548X_INTC_IMRL_INT_MASK20 (0x00100000) +#define MCF548X_INTC_IMRL_INT_MASK21 (0x00200000) +#define MCF548X_INTC_IMRL_INT_MASK22 (0x00400000) +#define MCF548X_INTC_IMRL_INT_MASK23 (0x00800000) +#define MCF548X_INTC_IMRL_INT_MASK24 (0x01000000) +#define MCF548X_INTC_IMRL_INT_MASK25 (0x02000000) +#define MCF548X_INTC_IMRL_INT_MASK26 (0x04000000) +#define MCF548X_INTC_IMRL_INT_MASK27 (0x08000000) +#define MCF548X_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF548X_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF548X_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF548X_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF548X_INTC_INTFRCH */ +#define MCF548X_INTC_INTFRCH_INTFRC32 (0x00000001) +#define MCF548X_INTC_INTFRCH_INTFRC33 (0x00000002) +#define MCF548X_INTC_INTFRCH_INTFRC34 (0x00000004) +#define MCF548X_INTC_INTFRCH_INTFRC35 (0x00000008) +#define MCF548X_INTC_INTFRCH_INTFRC36 (0x00000010) +#define MCF548X_INTC_INTFRCH_INTFRC37 (0x00000020) +#define MCF548X_INTC_INTFRCH_INTFRC38 (0x00000040) +#define MCF548X_INTC_INTFRCH_INTFRC39 (0x00000080) +#define MCF548X_INTC_INTFRCH_INTFRC40 (0x00000100) +#define MCF548X_INTC_INTFRCH_INTFRC41 (0x00000200) +#define MCF548X_INTC_INTFRCH_INTFRC42 (0x00000400) +#define MCF548X_INTC_INTFRCH_INTFRC43 (0x00000800) +#define MCF548X_INTC_INTFRCH_INTFRC44 (0x00001000) +#define MCF548X_INTC_INTFRCH_INTFRC45 (0x00002000) +#define MCF548X_INTC_INTFRCH_INTFRC46 (0x00004000) +#define MCF548X_INTC_INTFRCH_INTFRC47 (0x00008000) +#define MCF548X_INTC_INTFRCH_INTFRC48 (0x00010000) +#define MCF548X_INTC_INTFRCH_INTFRC49 (0x00020000) +#define MCF548X_INTC_INTFRCH_INTFRC50 (0x00040000) +#define MCF548X_INTC_INTFRCH_INTFRC51 (0x00080000) +#define MCF548X_INTC_INTFRCH_INTFRC52 (0x00100000) +#define MCF548X_INTC_INTFRCH_INTFRC53 (0x00200000) +#define MCF548X_INTC_INTFRCH_INTFRC54 (0x00400000) +#define MCF548X_INTC_INTFRCH_INTFRC55 (0x00800000) +#define MCF548X_INTC_INTFRCH_INTFRC56 (0x01000000) +#define MCF548X_INTC_INTFRCH_INTFRC57 (0x02000000) +#define MCF548X_INTC_INTFRCH_INTFRC58 (0x04000000) +#define MCF548X_INTC_INTFRCH_INTFRC59 (0x08000000) +#define MCF548X_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF548X_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF548X_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF548X_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF548X_INTC_INTFRCL */ +#define MCF548X_INTC_INTFRCL_INTFRC1 (0x00000002) +#define MCF548X_INTC_INTFRCL_INTFRC2 (0x00000004) +#define MCF548X_INTC_INTFRCL_INTFRC3 (0x00000008) +#define MCF548X_INTC_INTFRCL_INTFRC4 (0x00000010) +#define MCF548X_INTC_INTFRCL_INTFRC5 (0x00000020) +#define MCF548X_INTC_INTFRCL_INT6 (0x00000040) +#define MCF548X_INTC_INTFRCL_INT7 (0x00000080) +#define MCF548X_INTC_INTFRCL_INT8 (0x00000100) +#define MCF548X_INTC_INTFRCL_INT9 (0x00000200) +#define MCF548X_INTC_INTFRCL_INT10 (0x00000400) +#define MCF548X_INTC_INTFRCL_INTFRC11 (0x00000800) +#define MCF548X_INTC_INTFRCL_INTFRC12 (0x00001000) +#define MCF548X_INTC_INTFRCL_INTFRC13 (0x00002000) +#define MCF548X_INTC_INTFRCL_INTFRC14 (0x00004000) +#define MCF548X_INTC_INTFRCL_INT15 (0x00008000) +#define MCF548X_INTC_INTFRCL_INTFRC16 (0x00010000) +#define MCF548X_INTC_INTFRCL_INTFRC17 (0x00020000) +#define MCF548X_INTC_INTFRCL_INTFRC18 (0x00040000) +#define MCF548X_INTC_INTFRCL_INTFRC19 (0x00080000) +#define MCF548X_INTC_INTFRCL_INTFRC20 (0x00100000) +#define MCF548X_INTC_INTFRCL_INTFRC21 (0x00200000) +#define MCF548X_INTC_INTFRCL_INTFRC22 (0x00400000) +#define MCF548X_INTC_INTFRCL_INTFRC23 (0x00800000) +#define MCF548X_INTC_INTFRCL_INTFRC24 (0x01000000) +#define MCF548X_INTC_INTFRCL_INTFRC25 (0x02000000) +#define MCF548X_INTC_INTFRCL_INTFRC26 (0x04000000) +#define MCF548X_INTC_INTFRCL_INTFRC27 (0x08000000) +#define MCF548X_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF548X_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF548X_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF548X_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF548X_INTC_IRLR */ +#define MCF548X_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF548X_INTC_IACKLPR */ +#define MCF548X_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF548X_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF548X_INTC_ICRn */ +#define MCF548X_INTC_ICRn_IP(x) (((x)&0x07)<<0) +#define MCF548X_INTC_ICRn_IL(x) (((x)&0x07)<<3) + + +/********************************************************************* +* +* SDRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_SDRAMC_SDRAMDS (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000004))) +#define MCF548X_SDRAMC_CS0CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000020))) +#define MCF548X_SDRAMC_CS1CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000024))) +#define MCF548X_SDRAMC_CS2CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000028))) +#define MCF548X_SDRAMC_CS3CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00002C))) +#define MCF548X_SDRAMC_CSnCFG(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000020U+((x)*0x004)))) +#define MCF548X_SDRAMC_SDMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000100))) +#define MCF548X_SDRAMC_SDCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000104))) +#define MCF548X_SDRAMC_SDCFG1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000108))) +#define MCF548X_SDRAMC_SDCFG2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00010C))) + +/* Bit definitions and macros for MCF548X_SDRAMC_SDRAMDS */ +#define MCF548X_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x00000003)<<0) +#define MCF548X_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x00000003)<<2) +#define MCF548X_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x00000003)<<4) +#define MCF548X_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x00000003)<<6) +#define MCF548X_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x00000003)<<8) +#define MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA (0x02) +#define MCF548X_SDRAMC_SDRAMDS_DRIVE_16MA (0x01) +#define MCF548X_SDRAMC_SDRAMDS_DRIVE_24MA (0x00) +#define MCF548X_SDRAMC_SDRAMDS_DRIVE_NONE (0x03) + +/* Bit definitions and macros for MCF548X_SDRAMC_CSnCFG */ +#define MCF548X_SDRAMC_CSnCFG_CSSZ(x) (((x)&0x0000001F)<<0) +#define MCF548X_SDRAMC_CSnCFG_CSBA(x) (((x)&0x00000FFF)<<20) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_DIABLE (0x00000000) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_1MBYTE (0x00000013) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_2MBYTE (0x00000014) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_4MBYTE (0x00000015) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_8MBYTE (0x00000016) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_16MBYTE (0x00000017) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_32MBYTE (0x00000018) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_64MBYTE (0x00000019) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_128MBYTE (0x0000001A) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_256MBYTE (0x0000001B) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_512MBYTE (0x0000001C) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_1GBYTE (0x0000001D) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_2GBYTE (0x0000001E) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_4GBYTE (0x0000001F) + +/* Bit definitions and macros for MCF548X_SDRAMC_SDMR */ +#define MCF548X_SDRAMC_SDMR_CMD (0x00010000) +#define MCF548X_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) +#define MCF548X_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) +#define MCF548X_SDRAMC_SDMR_BNKAD_LMR (0x00000000) +#define MCF548X_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) + +/* Bit definitions and macros for MCF548X_SDRAMC_SDCR */ +#define MCF548X_SDRAMC_SDCR_IPALL (0x00000002) +#define MCF548X_SDRAMC_SDCR_IREF (0x00000004) +#define MCF548X_SDRAMC_SDCR_BUFF (0x00000010) +#define MCF548X_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) +#define MCF548X_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) +#define MCF548X_SDRAMC_SDCR_DRIVE (0x00400000) +#define MCF548X_SDRAMC_SDCR_AP (0x00800000) +#define MCF548X_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) +#define MCF548X_SDRAMC_SDCR_REF (0x10000000) +#define MCF548X_SDRAMC_SDCR_DDR (0x20000000) +#define MCF548X_SDRAMC_SDCR_CKE (0x40000000) +#define MCF548X_SDRAMC_SDCR_MODE_EN (0x80000000) + +/* Bit definitions and macros for MCF548X_SDRAMC_SDCFG1 */ +#define MCF548X_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) +#define MCF548X_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) +#define MCF548X_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) +#define MCF548X_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) +#define MCF548X_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) +#define MCF548X_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) +#define MCF548X_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF548X_SDRAMC_SDCFG2 */ +#define MCF548X_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) +#define MCF548X_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) +#define MCF548X_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) +#define MCF548X_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) + +/********************************************************************* +* +* Integrated Security Engine (SEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_SEC_EUACRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021000))) +#define MCF548X_SEC_EUACRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021004))) +#define MCF548X_SEC_EUASRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021028))) +#define MCF548X_SEC_EUASRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02102C))) +#define MCF548X_SEC_SIMRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021008))) +#define MCF548X_SEC_SIMRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02100C))) +#define MCF548X_SEC_SISRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021010))) +#define MCF548X_SEC_SISRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021014))) +#define MCF548X_SEC_SICRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021018))) +#define MCF548X_SEC_SICRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02101C))) +#define MCF548X_SEC_SIDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021020))) +#define MCF548X_SEC_SMCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021030))) +#define MCF548X_SEC_MEAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021038))) +#define MCF548X_SEC_CCCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02200C))) +#define MCF548X_SEC_CCCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02300C))) +#define MCF548X_SEC_CCPSRH0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x022010))) +#define MCF548X_SEC_CCPSRH1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x023010))) +#define MCF548X_SEC_CCPSRL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x022014))) +#define MCF548X_SEC_CCPSRL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x023014))) +#define MCF548X_SEC_CDPR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x022044))) +#define MCF548X_SEC_CDPR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x023044))) +#define MCF548X_SEC_FR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02204C))) +#define MCF548X_SEC_FR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02304C))) +#define MCF548X_SEC_AFRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x028018))) +#define MCF548X_SEC_AFSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x028028))) +#define MCF548X_SEC_AFISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x028030))) +#define MCF548X_SEC_AFIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x028038))) +#define MCF548X_SEC_DRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02A018))) +#define MCF548X_SEC_DSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02A028))) +#define MCF548X_SEC_DISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02A030))) +#define MCF548X_SEC_DIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02A038))) +#define MCF548X_SEC_MDRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02C018))) +#define MCF548X_SEC_MDSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02C028))) +#define MCF548X_SEC_MDISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02C030))) +#define MCF548X_SEC_MDIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02C038))) +#define MCF548X_SEC_RNGRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02E018))) +#define MCF548X_SEC_RNGSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02E028))) +#define MCF548X_SEC_RNGISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02E030))) +#define MCF548X_SEC_RNGIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02E038))) +#define MCF548X_SEC_AESRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x032018))) +#define MCF548X_SEC_AESSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x032028))) +#define MCF548X_SEC_AESISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x032030))) +#define MCF548X_SEC_AESIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x032038))) + +/* Bit definitions and macros for MCF548X_SEC_EUACRH */ +#define MCF548X_SEC_EUACRH_AFEU(x) (((x)&0x0000000F)<<0) +#define MCF548X_SEC_EUACRH_MDEU(x) (((x)&0x0000000F)<<8) +#define MCF548X_SEC_EUACRH_RNG(x) (((x)&0x0000000F)<<24) +#define MCF548X_SEC_EUACRH_RNG_NOASSIGN (0x00000000) +#define MCF548X_SEC_EUACRH_RNG_CHA0 (0x01000000) +#define MCF548X_SEC_EUACRH_RNG_CHA1 (0x02000000) +#define MCF548X_SEC_EUACRH_MDEU_NOASSIGN (0x00000000) +#define MCF548X_SEC_EUACRH_MDEU_CHA0 (0x00000100) +#define MCF548X_SEC_EUACRH_MDEU_CHA1 (0x00000200) +#define MCF548X_SEC_EUACRH_AFEU_NOASSIGN (0x00000000) +#define MCF548X_SEC_EUACRH_AFEU_CHA0 (0x00000001) +#define MCF548X_SEC_EUACRH_AFEU_CHA1 (0x00000002) + +/* Bit definitions and macros for MCF548X_SEC_EUACRL */ +#define MCF548X_SEC_EUACRL_AESU(x) (((x)&0x0000000F)<<16) +#define MCF548X_SEC_EUACRL_DEU(x) (((x)&0x0000000F)<<24) +#define MCF548X_SEC_EUACRL_DEU_NOASSIGN (0x00000000) +#define MCF548X_SEC_EUACRL_DEU_CHA0 (0x01000000) +#define MCF548X_SEC_EUACRL_DEU_CHA1 (0x02000000) +#define MCF548X_SEC_EUACRL_AESU_NOASSIGN (0x00000000) +#define MCF548X_SEC_EUACRL_AESU_CHA0 (0x00010000) +#define MCF548X_SEC_EUACRL_AESU_CHA1 (0x00020000) + +/* Bit definitions and macros for MCF548X_SEC_EUASRH */ +#define MCF548X_SEC_EUASRH_AFEU(x) (((x)&0x0000000F)<<0) +#define MCF548X_SEC_EUASRH_MDEU(x) (((x)&0x0000000F)<<8) +#define MCF548X_SEC_EUASRH_RNG(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_SEC_EUASRL */ +#define MCF548X_SEC_EUASRL_AESU(x) (((x)&0x0000000F)<<16) +#define MCF548X_SEC_EUASRL_DEU(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_SEC_SIMRH */ +#define MCF548X_SEC_SIMRH_AERR (0x08000000) +#define MCF548X_SEC_SIMRH_CHA0DN (0x10000000) +#define MCF548X_SEC_SIMRH_CHA0ERR (0x20000000) +#define MCF548X_SEC_SIMRH_CHA1DN (0x40000000) +#define MCF548X_SEC_SIMRH_CHA1ERR (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_SIMRL */ +#define MCF548X_SEC_SIMRL_TEA (0x00000040) +#define MCF548X_SEC_SIMRL_DEUDN (0x00000100) +#define MCF548X_SEC_SIMRL_DEUERR (0x00000200) +#define MCF548X_SEC_SIMRL_AESUDN (0x00001000) +#define MCF548X_SEC_SIMRL_AESUERR (0x00002000) +#define MCF548X_SEC_SIMRL_MDEUDN (0x00010000) +#define MCF548X_SEC_SIMRL_MDEUERR (0x00020000) +#define MCF548X_SEC_SIMRL_AFEUDN (0x00100000) +#define MCF548X_SEC_SIMRL_AFEUERR (0x00200000) +#define MCF548X_SEC_SIMRL_RNGDN (0x01000000) +#define MCF548X_SEC_SIMRL_RNGERR (0x02000000) + +/* Bit definitions and macros for MCF548X_SEC_SISRH */ +#define MCF548X_SEC_SISRH_AERR (0x08000000) +#define MCF548X_SEC_SISRH_CHA0DN (0x10000000) +#define MCF548X_SEC_SISRH_CHA0ERR (0x20000000) +#define MCF548X_SEC_SISRH_CHA1DN (0x40000000) +#define MCF548X_SEC_SISRH_CHA1ERR (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_SISRL */ +#define MCF548X_SEC_SISRL_TEA (0x00000040) +#define MCF548X_SEC_SISRL_DEUDN (0x00000100) +#define MCF548X_SEC_SISRL_DEUERR (0x00000200) +#define MCF548X_SEC_SISRL_AESUDN (0x00001000) +#define MCF548X_SEC_SISRL_AESUERR (0x00002000) +#define MCF548X_SEC_SISRL_MDEUDN (0x00010000) +#define MCF548X_SEC_SISRL_MDEUERR (0x00020000) +#define MCF548X_SEC_SISRL_AFEUDN (0x00100000) +#define MCF548X_SEC_SISRL_AFEUERR (0x00200000) +#define MCF548X_SEC_SISRL_RNGDN (0x01000000) +#define MCF548X_SEC_SISRL_RNGERR (0x02000000) + +/* Bit definitions and macros for MCF548X_SEC_SICRH */ +#define MCF548X_SEC_SICRH_AERR (0x08000000) +#define MCF548X_SEC_SICRH_CHA0DN (0x10000000) +#define MCF548X_SEC_SICRH_CHA0ERR (0x20000000) +#define MCF548X_SEC_SICRH_CHA1DN (0x40000000) +#define MCF548X_SEC_SICRH_CHA1ERR (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_SICRL */ +#define MCF548X_SEC_SICRL_TEA (0x00000040) +#define MCF548X_SEC_SICRL_DEUDN (0x00000100) +#define MCF548X_SEC_SICRL_DEUERR (0x00000200) +#define MCF548X_SEC_SICRL_AESUDN (0x00001000) +#define MCF548X_SEC_SICRL_AESUERR (0x00002000) +#define MCF548X_SEC_SICRL_MDEUDN (0x00010000) +#define MCF548X_SEC_SICRL_MDEUERR (0x00020000) +#define MCF548X_SEC_SICRL_AFEUDN (0x00100000) +#define MCF548X_SEC_SICRL_AFEUERR (0x00200000) +#define MCF548X_SEC_SICRL_RNGDN (0x01000000) +#define MCF548X_SEC_SICRL_RNGERR (0x02000000) + +/* Bit definitions and macros for MCF548X_SEC_SMCR */ +#define MCF548X_SEC_SMCR_CURR_CHAN(x) (((x)&0x0000000F)<<4) +#define MCF548X_SEC_SMCR_SWR (0x01000000) +#define MCF548X_SEC_SMCR_CURR_CHAN_1 (0x00000010) +#define MCF548X_SEC_SMCR_CURR_CHAN_2 (0x00000020) + +/* Bit definitions and macros for MCF548X_SEC_CCCRn */ +#define MCF548X_SEC_CCCRn_RST (0x00000001) +#define MCF548X_SEC_CCCRn_CDIE (0x00000002) +#define MCF548X_SEC_CCCRn_NT (0x00000004) +#define MCF548X_SEC_CCCRn_NE (0x00000008) +#define MCF548X_SEC_CCCRn_WE (0x00000010) +#define MCF548X_SEC_CCCRn_BURST_SIZE(x) (((x)&0x00000007)<<8) +#define MCF548X_SEC_CCCRn_BURST_SIZE_2 (0x00000000) +#define MCF548X_SEC_CCCRn_BURST_SIZE_8 (0x00000100) +#define MCF548X_SEC_CCCRn_BURST_SIZE_16 (0x00000200) +#define MCF548X_SEC_CCCRn_BURST_SIZE_24 (0x00000300) +#define MCF548X_SEC_CCCRn_BURST_SIZE_32 (0x00000400) +#define MCF548X_SEC_CCCRn_BURST_SIZE_40 (0x00000500) +#define MCF548X_SEC_CCCRn_BURST_SIZE_48 (0x00000600) +#define MCF548X_SEC_CCCRn_BURST_SIZE_56 (0x00000700) + +/* Bit definitions and macros for MCF548X_SEC_CCPSRHn */ +#define MCF548X_SEC_CCPSRHn_STATE(x) (((x)&0x000000FF)<<0) + +/* Bit definitions and macros for MCF548X_SEC_CCPSRLn */ +#define MCF548X_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0x000000FF)<<0) +#define MCF548X_SEC_CCPSRLn_EUERR (0x00000100) +#define MCF548X_SEC_CCPSRLn_SERR (0x00000200) +#define MCF548X_SEC_CCPSRLn_DERR (0x00000400) +#define MCF548X_SEC_CCPSRLn_PERR (0x00001000) +#define MCF548X_SEC_CCPSRLn_TEA (0x00002000) +#define MCF548X_SEC_CCPSRLn_SD (0x00010000) +#define MCF548X_SEC_CCPSRLn_PD (0x00020000) +#define MCF548X_SEC_CCPSRLn_SRD (0x00040000) +#define MCF548X_SEC_CCPSRLn_PRD (0x00080000) +#define MCF548X_SEC_CCPSRLn_SG (0x00100000) +#define MCF548X_SEC_CCPSRLn_PG (0x00200000) +#define MCF548X_SEC_CCPSRLn_SR (0x00400000) +#define MCF548X_SEC_CCPSRLn_PR (0x00800000) +#define MCF548X_SEC_CCPSRLn_MO (0x01000000) +#define MCF548X_SEC_CCPSRLn_MI (0x02000000) +#define MCF548X_SEC_CCPSRLn_STAT (0x04000000) + +/* Bit definitions and macros for MCF548X_SEC_AFRCR */ +#define MCF548X_SEC_AFRCR_SR (0x01000000) +#define MCF548X_SEC_AFRCR_MI (0x02000000) +#define MCF548X_SEC_AFRCR_RI (0x04000000) + +/* Bit definitions and macros for MCF548X_SEC_AFSR */ +#define MCF548X_SEC_AFSR_RD (0x01000000) +#define MCF548X_SEC_AFSR_ID (0x02000000) +#define MCF548X_SEC_AFSR_IE (0x04000000) +#define MCF548X_SEC_AFSR_OFE (0x08000000) +#define MCF548X_SEC_AFSR_IFW (0x10000000) +#define MCF548X_SEC_AFSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF548X_SEC_AFISR */ +#define MCF548X_SEC_AFISR_DSE (0x00010000) +#define MCF548X_SEC_AFISR_KSE (0x00020000) +#define MCF548X_SEC_AFISR_CE (0x00040000) +#define MCF548X_SEC_AFISR_ERE (0x00080000) +#define MCF548X_SEC_AFISR_IE (0x00100000) +#define MCF548X_SEC_AFISR_OFU (0x02000000) +#define MCF548X_SEC_AFISR_IFO (0x04000000) +#define MCF548X_SEC_AFISR_IFE (0x10000000) +#define MCF548X_SEC_AFISR_OFE (0x20000000) +#define MCF548X_SEC_AFISR_AE (0x40000000) +#define MCF548X_SEC_AFISR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_AFIMR */ +#define MCF548X_SEC_AFIMR_DSE (0x00010000) +#define MCF548X_SEC_AFIMR_KSE (0x00020000) +#define MCF548X_SEC_AFIMR_CE (0x00040000) +#define MCF548X_SEC_AFIMR_ERE (0x00080000) +#define MCF548X_SEC_AFIMR_IE (0x00100000) +#define MCF548X_SEC_AFIMR_OFU (0x02000000) +#define MCF548X_SEC_AFIMR_IFO (0x04000000) +#define MCF548X_SEC_AFIMR_IFE (0x10000000) +#define MCF548X_SEC_AFIMR_OFE (0x20000000) +#define MCF548X_SEC_AFIMR_AE (0x40000000) +#define MCF548X_SEC_AFIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_DRCR */ +#define MCF548X_SEC_DRCR_SR (0x01000000) +#define MCF548X_SEC_DRCR_MI (0x02000000) +#define MCF548X_SEC_DRCR_RI (0x04000000) + +/* Bit definitions and macros for MCF548X_SEC_DSR */ +#define MCF548X_SEC_DSR_RD (0x01000000) +#define MCF548X_SEC_DSR_ID (0x02000000) +#define MCF548X_SEC_DSR_IE (0x04000000) +#define MCF548X_SEC_DSR_OFR (0x08000000) +#define MCF548X_SEC_DSR_IFW (0x10000000) +#define MCF548X_SEC_DSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF548X_SEC_DISR */ +#define MCF548X_SEC_DISR_DSE (0x00010000) +#define MCF548X_SEC_DISR_KSE (0x00020000) +#define MCF548X_SEC_DISR_CE (0x00040000) +#define MCF548X_SEC_DISR_ERE (0x00080000) +#define MCF548X_SEC_DISR_IE (0x00100000) +#define MCF548X_SEC_DISR_KPE (0x00200000) +#define MCF548X_SEC_DISR_OFU (0x02000000) +#define MCF548X_SEC_DISR_IFO (0x04000000) +#define MCF548X_SEC_DISR_IFE (0x10000000) +#define MCF548X_SEC_DISR_OFE (0x20000000) +#define MCF548X_SEC_DISR_AE (0x40000000) +#define MCF548X_SEC_DISR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_DIMR */ +#define MCF548X_SEC_DIMR_DSE (0x00010000) +#define MCF548X_SEC_DIMR_KSE (0x00020000) +#define MCF548X_SEC_DIMR_CE (0x00040000) +#define MCF548X_SEC_DIMR_ERE (0x00080000) +#define MCF548X_SEC_DIMR_IE (0x00100000) +#define MCF548X_SEC_DIMR_KPE (0x00200000) +#define MCF548X_SEC_DIMR_OFU (0x02000000) +#define MCF548X_SEC_DIMR_IFO (0x04000000) +#define MCF548X_SEC_DIMR_IFE (0x10000000) +#define MCF548X_SEC_DIMR_OFE (0x20000000) +#define MCF548X_SEC_DIMR_AE (0x40000000) +#define MCF548X_SEC_DIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_MDRCR */ +#define MCF548X_SEC_MDRCR_SR (0x01000000) +#define MCF548X_SEC_MDRCR_MI (0x02000000) +#define MCF548X_SEC_MDRCR_RI (0x04000000) + +/* Bit definitions and macros for MCF548X_SEC_MDSR */ +#define MCF548X_SEC_MDSR_RD (0x01000000) +#define MCF548X_SEC_MDSR_ID (0x02000000) +#define MCF548X_SEC_MDSR_IE (0x04000000) +#define MCF548X_SEC_MDSR_IFW (0x10000000) +#define MCF548X_SEC_MDSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF548X_SEC_MDISR */ +#define MCF548X_SEC_MDISR_DSE (0x00010000) +#define MCF548X_SEC_MDISR_KSE (0x00020000) +#define MCF548X_SEC_MDISR_CE (0x00040000) +#define MCF548X_SEC_MDISR_ERE (0x00080000) +#define MCF548X_SEC_MDISR_IE (0x00100000) +#define MCF548X_SEC_MDISR_IFO (0x04000000) +#define MCF548X_SEC_MDISR_AE (0x40000000) +#define MCF548X_SEC_MDISR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_MDIMR */ +#define MCF548X_SEC_MDIMR_DSE (0x00010000) +#define MCF548X_SEC_MDIMR_KSE (0x00020000) +#define MCF548X_SEC_MDIMR_CE (0x00040000) +#define MCF548X_SEC_MDIMR_ERE (0x00080000) +#define MCF548X_SEC_MDIMR_IE (0x00100000) +#define MCF548X_SEC_MDIMR_IFO (0x04000000) +#define MCF548X_SEC_MDIMR_AE (0x40000000) +#define MCF548X_SEC_MDIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_RNGRCR */ +#define MCF548X_SEC_RNGRCR_SR (0x01000000) +#define MCF548X_SEC_RNGRCR_MI (0x02000000) +#define MCF548X_SEC_RNGRCR_RI (0x04000000) + +/* Bit definitions and macros for MCF548X_SEC_RNGSR */ +#define MCF548X_SEC_RNGSR_RD (0x01000000) +#define MCF548X_SEC_RNGSR_O (0x02000000) +#define MCF548X_SEC_RNGSR_IE (0x04000000) +#define MCF548X_SEC_RNGSR_OFR (0x08000000) +#define MCF548X_SEC_RNGSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF548X_SEC_RNGISR */ +#define MCF548X_SEC_RNGISR_IE (0x00100000) +#define MCF548X_SEC_RNGISR_OFU (0x02000000) +#define MCF548X_SEC_RNGISR_AE (0x40000000) +#define MCF548X_SEC_RNGISR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_RNGIMR */ +#define MCF548X_SEC_RNGIMR_IE (0x00100000) +#define MCF548X_SEC_RNGIMR_OFU (0x02000000) +#define MCF548X_SEC_RNGIMR_AE (0x40000000) +#define MCF548X_SEC_RNGIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_AESRCR */ +#define MCF548X_SEC_AESRCR_SR (0x01000000) +#define MCF548X_SEC_AESRCR_MI (0x02000000) +#define MCF548X_SEC_AESRCR_RI (0x04000000) + +/* Bit definitions and macros for MCF548X_SEC_AESSR */ +#define MCF548X_SEC_AESSR_RD (0x01000000) +#define MCF548X_SEC_AESSR_ID (0x02000000) +#define MCF548X_SEC_AESSR_IE (0x04000000) +#define MCF548X_SEC_AESSR_OFR (0x08000000) +#define MCF548X_SEC_AESSR_IFW (0x10000000) +#define MCF548X_SEC_AESSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF548X_SEC_AESISR */ +#define MCF548X_SEC_AESISR_DSE (0x00010000) +#define MCF548X_SEC_AESISR_KSE (0x00020000) +#define MCF548X_SEC_AESISR_CE (0x00040000) +#define MCF548X_SEC_AESISR_ERE (0x00080000) +#define MCF548X_SEC_AESISR_IE (0x00100000) +#define MCF548X_SEC_AESISR_OFU (0x02000000) +#define MCF548X_SEC_AESISR_IFO (0x04000000) +#define MCF548X_SEC_AESISR_IFE (0x10000000) +#define MCF548X_SEC_AESISR_OFE (0x20000000) +#define MCF548X_SEC_AESISR_AE (0x40000000) +#define MCF548X_SEC_AESISR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_AESIMR */ +#define MCF548X_SEC_AESIMR_DSE (0x00010000) +#define MCF548X_SEC_AESIMR_KSE (0x00020000) +#define MCF548X_SEC_AESIMR_CE (0x00040000) +#define MCF548X_SEC_AESIMR_ERE (0x00080000) +#define MCF548X_SEC_AESIMR_IE (0x00100000) +#define MCF548X_SEC_AESIMR_OFU (0x02000000) +#define MCF548X_SEC_AESIMR_IFO (0x04000000) +#define MCF548X_SEC_AESIMR_IFE (0x10000000) +#define MCF548X_SEC_AESIMR_OFE (0x20000000) +#define MCF548X_SEC_AESIMR_AE (0x40000000) +#define MCF548X_SEC_AESIMR_ME (0x80000000) + + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_SLT_SLTCNT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000900))) +#define MCF548X_SLT_SCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000904))) +#define MCF548X_SLT_SCNT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000908))) +#define MCF548X_SLT_SSR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00090C))) +#define MCF548X_SLT_SLTCNT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000910))) +#define MCF548X_SLT_SCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000914))) +#define MCF548X_SLT_SCNT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000918))) +#define MCF548X_SLT_SSR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00091C))) +#define MCF548X_SLT_SLTCNT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000900U+((x)*0x010)))) +#define MCF548X_SLT_SCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000904U+((x)*0x010)))) +#define MCF548X_SLT_SCNT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000908U+((x)*0x010)))) +#define MCF548X_SLT_SSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00090CU+((x)*0x010)))) + +/* Bit definitions and macros for MCF548X_SLT_SCR */ +#define MCF548X_SLT_SCR_TEN (0x01000000) +#define MCF548X_SLT_SCR_IEN (0x02000000) +#define MCF548X_SLT_SCR_RUN (0x04000000) + +/* Bit definitions and macros for MCF548X_SLT_SSR */ +#define MCF548X_SLT_SSR_ST (0x01000000) +#define MCF548X_SLT_SSR_BE (0x02000000) + + +/********************************************************************* +* +* Universal Serial Bus (USB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_USB_USBAISR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B000))) +#define MCF548X_USB_USBAIMR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B001))) +#define MCF548X_USB_EPINFO (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B003))) +#define MCF548X_USB_CFGR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B004))) +#define MCF548X_USB_CFGAR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B005))) +#define MCF548X_USB_SPEEDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B006))) +#define MCF548X_USB_FRMNUMR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B00E))) +#define MCF548X_USB_EPTNR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B010))) +#define MCF548X_USB_IFUR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B014))) +#define MCF548X_USB_IFR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B040))) +#define MCF548X_USB_IFR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B042))) +#define MCF548X_USB_IFR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B044))) +#define MCF548X_USB_IFR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B046))) +#define MCF548X_USB_IFR4 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B048))) +#define MCF548X_USB_IFR5 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B04A))) +#define MCF548X_USB_IFR6 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B04C))) +#define MCF548X_USB_IFR7 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B04E))) +#define MCF548X_USB_IFR8 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B050))) +#define MCF548X_USB_IFR9 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B052))) +#define MCF548X_USB_IFR10 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B054))) +#define MCF548X_USB_IFR11 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B056))) +#define MCF548X_USB_IFR12 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B058))) +#define MCF548X_USB_IFR13 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B05A))) +#define MCF548X_USB_IFR14 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B05C))) +#define MCF548X_USB_IFR15 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B05E))) +#define MCF548X_USB_IFR16 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B060))) +#define MCF548X_USB_IFR17 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B062))) +#define MCF548X_USB_IFR18 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B064))) +#define MCF548X_USB_IFR19 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B066))) +#define MCF548X_USB_IFR20 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B068))) +#define MCF548X_USB_IFR21 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B06A))) +#define MCF548X_USB_IFR22 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B06C))) +#define MCF548X_USB_IFR23 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B06E))) +#define MCF548X_USB_IFR24 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B070))) +#define MCF548X_USB_IFR25 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B072))) +#define MCF548X_USB_IFR26 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B074))) +#define MCF548X_USB_IFR27 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B076))) +#define MCF548X_USB_IFR28 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B078))) +#define MCF548X_USB_IFR29 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B07A))) +#define MCF548X_USB_IFR30 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B07C))) +#define MCF548X_USB_IFR31 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B07E))) +#define MCF548X_USB_IFRn(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B040U+((x)*0x002)))) +#define MCF548X_USB_PPCNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B080))) +#define MCF548X_USB_DPCNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B082))) +#define MCF548X_USB_CRCECNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B084))) +#define MCF548X_USB_BSECNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B086))) +#define MCF548X_USB_PIDECNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B088))) +#define MCF548X_USB_FRMECNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B08A))) +#define MCF548X_USB_TXPCNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B08C))) +#define MCF548X_USB_CNTOVR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B08E))) +#define MCF548X_USB_EP0ACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B101))) +#define MCF548X_USB_EP0MPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B102))) +#define MCF548X_USB_EP0IFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B104))) +#define MCF548X_USB_EP0SR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B105))) +#define MCF548X_USB_BMRTR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B106))) +#define MCF548X_USB_BRTR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B107))) +#define MCF548X_USB_WVALUER (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B108))) +#define MCF548X_USB_WINDEXR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B10A))) +#define MCF548X_USB_WLENGTH (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B10C))) +#define MCF548X_USB_EP1OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B131))) +#define MCF548X_USB_EP2OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B161))) +#define MCF548X_USB_EP3OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B191))) +#define MCF548X_USB_EP4OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1C1))) +#define MCF548X_USB_EP5OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1F1))) +#define MCF548X_USB_EP6OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B221))) +#define MCF548X_USB_EPnOUTACR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B131U+((x)*0x030)))) +#define MCF548X_USB_EP1OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B132))) +#define MCF548X_USB_EP2OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B162))) +#define MCF548X_USB_EP3OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B192))) +#define MCF548X_USB_EP4OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1C2))) +#define MCF548X_USB_EP5OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1F2))) +#define MCF548X_USB_EP6OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B222))) +#define MCF548X_USB_EPnOUTMPSR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B132U+((x)*0x030)))) +#define MCF548X_USB_EP1OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B134))) +#define MCF548X_USB_EP2OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B164))) +#define MCF548X_USB_EP3OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B194))) +#define MCF548X_USB_EP4OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1C4))) +#define MCF548X_USB_EP5OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1F4))) +#define MCF548X_USB_EP6OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B224))) +#define MCF548X_USB_EPnOUTIFR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B134U+((x)*0x030)))) +#define MCF548X_USB_EP1OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B135))) +#define MCF548X_USB_EP2OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B165))) +#define MCF548X_USB_EP3OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B195))) +#define MCF548X_USB_EP4OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1C5))) +#define MCF548X_USB_EP5OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1F5))) +#define MCF548X_USB_EP6OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B225))) +#define MCF548X_USB_EPnOUTSR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B135U+((x)*0x030)))) +#define MCF548X_USB_EP1OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B13E))) +#define MCF548X_USB_EP2OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B16E))) +#define MCF548X_USB_EP3OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B19E))) +#define MCF548X_USB_EP4OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1CE))) +#define MCF548X_USB_EP5OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1FE))) +#define MCF548X_USB_EP6OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B22E))) +#define MCF548X_USB_EPnOUTSFR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B13EU+((x)*0x030)))) +#define MCF548X_USB_EP1INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B149))) +#define MCF548X_USB_EP2INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B179))) +#define MCF548X_USB_EP3INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1A9))) +#define MCF548X_USB_EP4INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1D9))) +#define MCF548X_USB_EP5INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B209))) +#define MCF548X_USB_EP6INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B239))) +#define MCF548X_USB_EPnINACR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B149U+((x)*0x030)))) +#define MCF548X_USB_EP1INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B14A))) +#define MCF548X_USB_EP2INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B17A))) +#define MCF548X_USB_EP3INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1AA))) +#define MCF548X_USB_EP4INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1DA))) +#define MCF548X_USB_EP5INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B20A))) +#define MCF548X_USB_EP6INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B23A))) +#define MCF548X_USB_EPnINMPSR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B14AU+((x)*0x030)))) +#define MCF548X_USB_EP1INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B14C))) +#define MCF548X_USB_EP2INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B17C))) +#define MCF548X_USB_EP3INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1AC))) +#define MCF548X_USB_EP4INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1DC))) +#define MCF548X_USB_EP5INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B20C))) +#define MCF548X_USB_EP6INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B23C))) +#define MCF548X_USB_EPnINIFR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B14CU+((x)*0x030)))) +#define MCF548X_USB_EP1INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B14D))) +#define MCF548X_USB_EP2INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B17D))) +#define MCF548X_USB_EP3INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1AD))) +#define MCF548X_USB_EP4INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1DD))) +#define MCF548X_USB_EP5INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B20D))) +#define MCF548X_USB_EP6INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B23D))) +#define MCF548X_USB_EPnINSR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B14DU+((x)*0x030)))) +#define MCF548X_USB_EP1INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B15A))) +#define MCF548X_USB_EP2INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B18A))) +#define MCF548X_USB_EP3INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1BA))) +#define MCF548X_USB_EP4INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1EA))) +#define MCF548X_USB_EP5INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B21A))) +#define MCF548X_USB_EP6INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B24A))) +#define MCF548X_USB_EPnINSFR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B15AU+((x)*0x030)))) +#define MCF548X_USB_USBSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B400))) +#define MCF548X_USB_USBCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B404))) +#define MCF548X_USB_DRAMCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B408))) +#define MCF548X_USB_DRAMDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B40C))) +#define MCF548X_USB_USBISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B410))) +#define MCF548X_USB_USBIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B414))) +#define MCF548X_USB_EP0STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B440))) +#define MCF548X_USB_EP1STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B470))) +#define MCF548X_USB_EP2STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4A0))) +#define MCF548X_USB_EP3STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4D0))) +#define MCF548X_USB_EP4STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B500))) +#define MCF548X_USB_EP5STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B530))) +#define MCF548X_USB_EP6STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B560))) +#define MCF548X_USB_EPnSTAT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B440U+((x)*0x030)))) +#define MCF548X_USB_EP0ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B444))) +#define MCF548X_USB_EP1ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B474))) +#define MCF548X_USB_EP2ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4A4))) +#define MCF548X_USB_EP3ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4D4))) +#define MCF548X_USB_EP4ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B504))) +#define MCF548X_USB_EP5ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B534))) +#define MCF548X_USB_EP6ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B564))) +#define MCF548X_USB_EPnISR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B444U+((x)*0x030)))) +#define MCF548X_USB_EP0IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B448))) +#define MCF548X_USB_EP1IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B478))) +#define MCF548X_USB_EP2IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4A8))) +#define MCF548X_USB_EP3IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4D8))) +#define MCF548X_USB_EP4IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B508))) +#define MCF548X_USB_EP5IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B538))) +#define MCF548X_USB_EP6IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B568))) +#define MCF548X_USB_EPnIMR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B448U+((x)*0x030)))) +#define MCF548X_USB_EP0FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B44C))) +#define MCF548X_USB_EP1FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B47C))) +#define MCF548X_USB_EP2FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4AC))) +#define MCF548X_USB_EP3FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4DC))) +#define MCF548X_USB_EP4FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B50C))) +#define MCF548X_USB_EP5FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B53C))) +#define MCF548X_USB_EP6FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B56C))) +#define MCF548X_USB_EPnFRCFGR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B44CU+((x)*0x030)))) +#define MCF548X_USB_EP0FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B450))) +#define MCF548X_USB_EP1FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B480))) +#define MCF548X_USB_EP2FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4B0))) +#define MCF548X_USB_EP3FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4E0))) +#define MCF548X_USB_EP4FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B510))) +#define MCF548X_USB_EP5FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B540))) +#define MCF548X_USB_EP6FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B570))) +#define MCF548X_USB_EPnFDR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B450U+((x)*0x030)))) +#define MCF548X_USB_EP0FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B454))) +#define MCF548X_USB_EP1FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B484))) +#define MCF548X_USB_EP2FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4B4))) +#define MCF548X_USB_EP3FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4E4))) +#define MCF548X_USB_EP4FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B514))) +#define MCF548X_USB_EP5FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B544))) +#define MCF548X_USB_EP6FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B574))) +#define MCF548X_USB_EPnFSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B454U+((x)*0x030)))) +#define MCF548X_USB_EP0FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B458))) +#define MCF548X_USB_EP1FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B488))) +#define MCF548X_USB_EP2FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4B8))) +#define MCF548X_USB_EP3FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4E8))) +#define MCF548X_USB_EP4FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B518))) +#define MCF548X_USB_EP5FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B548))) +#define MCF548X_USB_EP6FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B578))) +#define MCF548X_USB_EPnFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B458U+((x)*0x030)))) +#define MCF548X_USB_EP0FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B45C))) +#define MCF548X_USB_EP1FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B48C))) +#define MCF548X_USB_EP2FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4BC))) +#define MCF548X_USB_EP3FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4EC))) +#define MCF548X_USB_EP4FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B51C))) +#define MCF548X_USB_EP5FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B54C))) +#define MCF548X_USB_EP6FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B57C))) +#define MCF548X_USB_EPnFAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B45CU+((x)*0x030)))) +#define MCF548X_USB_EP0FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B460))) +#define MCF548X_USB_EP1FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B490))) +#define MCF548X_USB_EP2FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4C0))) +#define MCF548X_USB_EP3FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4F0))) +#define MCF548X_USB_EP4FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B520))) +#define MCF548X_USB_EP5FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B550))) +#define MCF548X_USB_EP6FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B580))) +#define MCF548X_USB_EPnFRP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B460U+((x)*0x030)))) +#define MCF548X_USB_EP0FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B464))) +#define MCF548X_USB_EP1FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B494))) +#define MCF548X_USB_EP2FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4C4))) +#define MCF548X_USB_EP3FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4F4))) +#define MCF548X_USB_EP4FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B524))) +#define MCF548X_USB_EP5FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B554))) +#define MCF548X_USB_EP6FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B584))) +#define MCF548X_USB_EPnFWP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B464U+((x)*0x030)))) +#define MCF548X_USB_EP0LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B468))) +#define MCF548X_USB_EP1LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B498))) +#define MCF548X_USB_EP2LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4C8))) +#define MCF548X_USB_EP3LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4F8))) +#define MCF548X_USB_EP4LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B528))) +#define MCF548X_USB_EP5LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B558))) +#define MCF548X_USB_EP6LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B588))) +#define MCF548X_USB_EPnLRFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B468U+((x)*0x030)))) +#define MCF548X_USB_EP0LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B46C))) +#define MCF548X_USB_EP1LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B49C))) +#define MCF548X_USB_EP2LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4CC))) +#define MCF548X_USB_EP3LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4FC))) +#define MCF548X_USB_EP4LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B52C))) +#define MCF548X_USB_EP5LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B55C))) +#define MCF548X_USB_EP6LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B58C))) +#define MCF548X_USB_EPnLWFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B46CU+((x)*0x030)))) + +/* Bit definitions and macros for MCF548X_USB_USBAISR */ +#define MCF548X_USB_USBAISR_SETUP (0x01) +#define MCF548X_USB_USBAISR_IN (0x02) +#define MCF548X_USB_USBAISR_OUT (0x04) +#define MCF548X_USB_USBAISR_EPHALT (0x08) +#define MCF548X_USB_USBAISR_TRANSERR (0x10) +#define MCF548X_USB_USBAISR_ACK (0x20) +#define MCF548X_USB_USBAISR_CTROVFL (0x40) +#define MCF548X_USB_USBAISR_EPSTALL (0x80) + +/* Bit definitions and macros for MCF548X_USB_USBAIMR */ +#define MCF548X_USB_USBAIMR_SETUPEN (0x01) +#define MCF548X_USB_USBAIMR_INEN (0x02) +#define MCF548X_USB_USBAIMR_OUTEN (0x04) +#define MCF548X_USB_USBAIMR_EPHALTEN (0x08) +#define MCF548X_USB_USBAIMR_TRANSERREN (0x10) +#define MCF548X_USB_USBAIMR_ACKEN (0x20) +#define MCF548X_USB_USBAIMR_CTROVFLEN (0x40) +#define MCF548X_USB_USBAIMR_EPSTALLEN (0x80) + +/* Bit definitions and macros for MCF548X_USB_EPINFO */ +#define MCF548X_USB_EPINFO_EPDIR (0x01) +#define MCF548X_USB_EPINFO_EPNUM(x) (((x)&0x07)<<1) + +/* Bit definitions and macros for MCF548X_USB_CFGAR */ +#define MCF548X_USB_CFGAR_RESERVED (0xA0) +#define MCF548X_USB_CFGAR_RMTWKEUP (0xE0) + +/* Bit definitions and macros for MCF548X_USB_SPEEDR */ +#define MCF548X_USB_SPEEDR_HS (0x01) +#define MCF548X_USB_SPEEDR_FS (0x02) + +/* Bit definitions and macros for MCF548X_USB_FRMNUMR */ +#define MCF548X_USB_FRMNUMR_FRMNUM(x) (((x)&0x0FFF)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPTNR */ +#define MCF548X_USB_EPTNR_EP1T(x) (((x)&0x0003)<<0) +#define MCF548X_USB_EPTNR_EP2T(x) (((x)&0x0003)<<2) +#define MCF548X_USB_EPTNR_EP3T(x) (((x)&0x0003)<<4) +#define MCF548X_USB_EPTNR_EP4T(x) (((x)&0x0003)<<6) +#define MCF548X_USB_EPTNR_EP5T(x) (((x)&0x0003)<<8) +#define MCF548X_USB_EPTNR_EP6T(x) (((x)&0x0003)<<10) +#define MCF548X_USB_EPTNR_EPnT1 (0) +#define MCF548X_USB_EPTNR_EPnT2 (1) +#define MCF548X_USB_EPTNR_EPnT3 (2) + +/* Bit definitions and macros for MCF548X_USB_IFUR */ +#define MCF548X_USB_IFUR_ALTSET(x) (((x)&0x00FF)<<0) +#define MCF548X_USB_IFUR_IFNUM(x) (((x)&0x00FF)<<8) + +/* Bit definitions and macros for MCF548X_USB_IFRn */ +#define MCF548X_USB_IFRn_ALTSET(x) (((x)&0x00FF)<<0) +#define MCF548X_USB_IFRn_IFNUM(x) (((x)&0x00FF)<<8) + +/* Bit definitions and macros for MCF548X_USB_CNTOVR */ +#define MCF548X_USB_CNTOVR_PPCNT (0x01) +#define MCF548X_USB_CNTOVR_DPCNT (0x02) +#define MCF548X_USB_CNTOVR_CRCECNT (0x04) +#define MCF548X_USB_CNTOVR_BSECNT (0x08) +#define MCF548X_USB_CNTOVR_PIDECNT (0x10) +#define MCF548X_USB_CNTOVR_FRMECNT (0x20) +#define MCF548X_USB_CNTOVR_TXPCNT (0x40) + +/* Bit definitions and macros for MCF548X_USB_EP0ACR */ +#define MCF548X_USB_EP0ACR_TTYPE(x) (((x)&0x03)<<0) +#define MCF548X_USB_EP0ACR_TTYPE_CTRL (0) +#define MCF548X_USB_EP0ACR_TTYPE_ISOC (1) +#define MCF548X_USB_EP0ACR_TTYPE_BULK (2) +#define MCF548X_USB_EP0ACR_TTYPE_INT (3) + +/* Bit definitions and macros for MCF548X_USB_EP0MPSR */ +#define MCF548X_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) +#define MCF548X_USB_EP0MPSR_ADDTRANS(x) (((x)&0x0003)<<11) + +/* Bit definitions and macros for MCF548X_USB_EP0SR */ +#define MCF548X_USB_EP0SR_HALT (0x01) +#define MCF548X_USB_EP0SR_ACTIVE (0x02) +#define MCF548X_USB_EP0SR_PSTALL (0x04) +#define MCF548X_USB_EP0SR_CCOMP (0x08) +#define MCF548X_USB_EP0SR_TXZERO (0x20) +#define MCF548X_USB_EP0SR_INT (0x80) + +/* Bit definitions and macros for MCF548X_USB_BMRTR */ +#define MCF548X_USB_BMRTR_DIR (0x80) +#define MCF548X_USB_BMRTR_TYPE_STANDARD (0x00) +#define MCF548X_USB_BMRTR_TYPE_CLASS (0x20) +#define MCF548X_USB_BMRTR_TYPE_VENDOR (0x40) +#define MCF548X_USB_BMRTR_REC_DEVICE (0x00) +#define MCF548X_USB_BMRTR_REC_INTERFACE (0x01) +#define MCF548X_USB_BMRTR_REC_ENDPOINT (0x02) +#define MCF548X_USB_BMRTR_REC_OTHER (0x03) + +/* Bit definitions and macros for MCF548X_USB_EPnOUTACR */ +#define MCF548X_USB_EPnOUTACR_TTYPE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnOUTMPSR */ +#define MCF548X_USB_EPnOUTMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) +#define MCF548X_USB_EPnOUTMPSR_ADDTRANS(x) (((x)&0x0003)<<11) + +/* Bit definitions and macros for MCF548X_USB_EPnOUTSR */ +#define MCF548X_USB_EPnOUTSR_HALT (0x01) +#define MCF548X_USB_EPnOUTSR_ACTIVE (0x02) +#define MCF548X_USB_EPnOUTSR_PSTALL (0x04) +#define MCF548X_USB_EPnOUTSR_CCOMP (0x08) +#define MCF548X_USB_EPnOUTSR_TXZERO (0x20) +#define MCF548X_USB_EPnOUTSR_INT (0x80) + +/* Bit definitions and macros for MCF548X_USB_EPnOUTSFR */ +#define MCF548X_USB_EPnOUTSFR_FRMNUM(x) (((x)&0x07FF)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnINACR */ +#define MCF548X_USB_EPnINACR_TTYPE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnINMPSR */ +#define MCF548X_USB_EPnINMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) +#define MCF548X_USB_EPnINMPSR_ADDTRANS(x) (((x)&0x0003)<<11) + +/* Bit definitions and macros for MCF548X_USB_EPnINSR */ +#define MCF548X_USB_EPnINSR_HALT (0x01) +#define MCF548X_USB_EPnINSR_ACTIVE (0x02) +#define MCF548X_USB_EPnINSR_PSTALL (0x04) +#define MCF548X_USB_EPnINSR_CCOMP (0x08) +#define MCF548X_USB_EPnINSR_TXZERO (0x20) +#define MCF548X_USB_EPnINSR_INT (0x80) + +/* Bit definitions and macros for MCF548X_USB_EPnINSFR */ +#define MCF548X_USB_EPnINSFR_FRMNUM(x) (((x)&0x07FF)<<0) + +/* Bit definitions and macros for MCF548X_USB_USBSR */ +#define MCF548X_USB_USBSR_SUSP (0x00000080) +#define MCF548X_USB_USBSR_ISOERREP (0x0000000F) + +/* Bit definitions and macros for MCF548X_USB_USBCR */ +#define MCF548X_USB_USBCR_RESUME (0x00000001) +#define MCF548X_USB_USBCR_APPLOCK (0x00000002) +#define MCF548X_USB_USBCR_RST (0x00000004) +#define MCF548X_USB_USBCR_RAMEN (0x00000008) +#define MCF548X_USB_USBCR_RAMSPLIT (0x00000020) + +/* Bit definitions and macros for MCF548X_USB_DRAMCR */ +#define MCF548X_USB_DRAMCR_DADR(x) (((x)&0x000003FF)<<0) +#define MCF548X_USB_DRAMCR_DSIZE(x) (((x)&0x000007FF)<<16) +#define MCF548X_USB_DRAMCR_BSY (0x40000000) +#define MCF548X_USB_DRAMCR_START (0x80000000) + +/* Bit definitions and macros for MCF548X_USB_DRAMDR */ +#define MCF548X_USB_DRAMDR_DDAT(x) (((x)&0x000000FF)<<0) + +/* Bit definitions and macros for MCF548X_USB_USBISR */ +#define MCF548X_USB_USBISR_ISOERR (0x00000001) +#define MCF548X_USB_USBISR_FTUNLCK (0x00000002) +#define MCF548X_USB_USBISR_SUSP (0x00000004) +#define MCF548X_USB_USBISR_RES (0x00000008) +#define MCF548X_USB_USBISR_UPDSOF (0x00000010) +#define MCF548X_USB_USBISR_RSTSTOP (0x00000020) +#define MCF548X_USB_USBISR_SOF (0x00000040) +#define MCF548X_USB_USBISR_MSOF (0x00000080) + +/* Bit definitions and macros for MCF548X_USB_USBIMR */ +#define MCF548X_USB_USBIMR_ISOERR (0x00000001) +#define MCF548X_USB_USBIMR_FTUNLCK (0x00000002) +#define MCF548X_USB_USBIMR_SUSP (0x00000004) +#define MCF548X_USB_USBIMR_RES (0x00000008) +#define MCF548X_USB_USBIMR_UPDSOF (0x00000010) +#define MCF548X_USB_USBIMR_RSTSTOP (0x00000020) +#define MCF548X_USB_USBIMR_SOF (0x00000040) +#define MCF548X_USB_USBIMR_MSOF (0x00000080) + +/* Bit definitions and macros for MCF548X_USB_EPnSTAT */ +#define MCF548X_USB_EPnSTAT_RST (0x00000001) +#define MCF548X_USB_EPnSTAT_FLUSH (0x00000002) +#define MCF548X_USB_EPnSTAT_DIR (0x00000080) +#define MCF548X_USB_EPnSTAT_BYTECNT(x) (((x)&0x00000FFF)<<16) + +/* Bit definitions and macros for MCF548X_USB_EPnISR */ +#define MCF548X_USB_EPnISR_EOF (0x00000001) +#define MCF548X_USB_EPnISR_EOT (0x00000004) +#define MCF548X_USB_EPnISR_FIFOLO (0x00000010) +#define MCF548X_USB_EPnISR_FIFOHI (0x00000020) +#define MCF548X_USB_EPnISR_ERR (0x00000040) +#define MCF548X_USB_EPnISR_EMT (0x00000080) +#define MCF548X_USB_EPnISR_FU (0x00000100) + +/* Bit definitions and macros for MCF548X_USB_EPnIMR */ +#define MCF548X_USB_EPnIMR_EOF (0x00000001) +#define MCF548X_USB_EPnIMR_EOT (0x00000004) +#define MCF548X_USB_EPnIMR_FIFOLO (0x00000010) +#define MCF548X_USB_EPnIMR_FIFOHI (0x00000020) +#define MCF548X_USB_EPnIMR_ERR (0x00000040) +#define MCF548X_USB_EPnIMR_EMT (0x00000080) +#define MCF548X_USB_EPnIMR_FU (0x00000100) + +/* Bit definitions and macros for MCF548X_USB_EPnFRCFGR */ +#define MCF548X_USB_EPnFRCFGR_DEPTH(x) (((x)&0x00001FFF)<<0) +#define MCF548X_USB_EPnFRCFGR_BASE(x) (((x)&0x00000FFF)<<16) + +/* Bit definitions and macros for MCF548X_USB_EPnFSR */ +#define MCF548X_USB_EPnFSR_EMT (0x00010000) +#define MCF548X_USB_EPnFSR_ALRM (0x00020000) +#define MCF548X_USB_EPnFSR_FR (0x00040000) +#define MCF548X_USB_EPnFSR_FU (0x00080000) +#define MCF548X_USB_EPnFSR_OF (0x00100000) +#define MCF548X_USB_EPnFSR_UF (0x00200000) +#define MCF548X_USB_EPnFSR_RXW (0x00400000) +#define MCF548X_USB_EPnFSR_FAE (0x00800000) +#define MCF548X_USB_EPnFSR_FRM(x) (((x)&0x0000000F)<<24) +#define MCF548X_USB_EPnFSR_TXW (0x40000000) +#define MCF548X_USB_EPnFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF548X_USB_EPnFCR */ +#define MCF548X_USB_EPnFCR_COUNTER(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_USB_EPnFCR_TXWMSK (0x00040000) +#define MCF548X_USB_EPnFCR_OFMSK (0x00080000) +#define MCF548X_USB_EPnFCR_UFMSK (0x00100000) +#define MCF548X_USB_EPnFCR_RXWMSK (0x00200000) +#define MCF548X_USB_EPnFCR_FAEMSK (0x00400000) +#define MCF548X_USB_EPnFCR_IPMSK (0x00800000) +#define MCF548X_USB_EPnFCR_GR(x) (((x)&0x00000007)<<24) +#define MCF548X_USB_EPnFCR_FRM (0x08000000) +#define MCF548X_USB_EPnFCR_TMR (0x10000000) +#define MCF548X_USB_EPnFCR_WFR (0x20000000) +#define MCF548X_USB_EPnFCR_SHAD (0x80000000) + +/* Bit definitions and macros for MCF548X_USB_EPnFAR */ +#define MCF548X_USB_EPnFAR_ALRMP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnFRP */ +#define MCF548X_USB_EPnFRP_RP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnFWP */ +#define MCF548X_USB_EPnFWP_WP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnLRFP */ +#define MCF548X_USB_EPnLRFP_LRFP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnLWFP */ +#define MCF548X_USB_EPnLWFP_LWFP(x) (((x)&0x00000FFF)<<0) + + +/********************************************************************* +* +* Programmable Serial Controller (PSC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_PSC_MR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008600))) +#define MCF548X_PSC_SR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008604))) +#define MCF548X_PSC_CSR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008604))) +#define MCF548X_PSC_CR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008608))) +#define MCF548X_PSC_RB0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) +#define MCF548X_PSC_TB0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) +#define MCF548X_PSC_TB_8BIT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) +#define MCF548X_PSC_TB_16BIT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) +#define MCF548X_PSC_TB_AC970 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) +#define MCF548X_PSC_IPCR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008610))) +#define MCF548X_PSC_ACR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008610))) +#define MCF548X_PSC_ISR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008614))) +#define MCF548X_PSC_IMR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008614))) +#define MCF548X_PSC_CTUR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008618))) +#define MCF548X_PSC_CTLR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00861C))) +#define MCF548X_PSC_IP0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008634))) +#define MCF548X_PSC_OPSET0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008638))) +#define MCF548X_PSC_OPRESET0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00863C))) +#define MCF548X_PSC_SICR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008640))) +#define MCF548X_PSC_IRCR10 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008644))) +#define MCF548X_PSC_IRCR20 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008648))) +#define MCF548X_PSC_IRSDR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00864C))) +#define MCF548X_PSC_IRMDR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008650))) +#define MCF548X_PSC_IRFDR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008654))) +#define MCF548X_PSC_RFCNT0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008658))) +#define MCF548X_PSC_TFCNT0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00865C))) +#define MCF548X_PSC_RFSR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008664))) +#define MCF548X_PSC_TFSR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008684))) +#define MCF548X_PSC_RFCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008668))) +#define MCF548X_PSC_TFCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008688))) +#define MCF548X_PSC_RFAR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00866E))) +#define MCF548X_PSC_TFAR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00868E))) +#define MCF548X_PSC_RFRP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008672))) +#define MCF548X_PSC_TFRP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008692))) +#define MCF548X_PSC_RFWP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008676))) +#define MCF548X_PSC_TFWP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008696))) +#define MCF548X_PSC_RLRFP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00867A))) +#define MCF548X_PSC_TLRFP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00869A))) +#define MCF548X_PSC_RLWFP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00867E))) +#define MCF548X_PSC_TLWFP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00869E))) +#define MCF548X_PSC_MR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008700))) +#define MCF548X_PSC_SR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008704))) +#define MCF548X_PSC_CSR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008704))) +#define MCF548X_PSC_CR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008708))) +#define MCF548X_PSC_RB1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) +#define MCF548X_PSC_TB1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) +#define MCF548X_PSC_TB_8BIT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) +#define MCF548X_PSC_TB_16BIT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) +#define MCF548X_PSC_TB_AC971 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) +#define MCF548X_PSC_IPCR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008710))) +#define MCF548X_PSC_ACR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008710))) +#define MCF548X_PSC_ISR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008714))) +#define MCF548X_PSC_IMR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008714))) +#define MCF548X_PSC_CTUR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008718))) +#define MCF548X_PSC_CTLR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00871C))) +#define MCF548X_PSC_IP1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008734))) +#define MCF548X_PSC_OPSET1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008738))) +#define MCF548X_PSC_OPRESET1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00873C))) +#define MCF548X_PSC_SICR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008740))) +#define MCF548X_PSC_IRCR11 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008744))) +#define MCF548X_PSC_IRCR21 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008748))) +#define MCF548X_PSC_IRSDR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00874C))) +#define MCF548X_PSC_IRMDR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008750))) +#define MCF548X_PSC_IRFDR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008754))) +#define MCF548X_PSC_RFCNT1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008758))) +#define MCF548X_PSC_TFCNT1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00875C))) +#define MCF548X_PSC_RFSR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008764))) +#define MCF548X_PSC_TFSR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008784))) +#define MCF548X_PSC_RFCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008768))) +#define MCF548X_PSC_TFCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008788))) +#define MCF548X_PSC_RFAR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00876E))) +#define MCF548X_PSC_TFAR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00878E))) +#define MCF548X_PSC_RFRP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008772))) +#define MCF548X_PSC_TFRP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008792))) +#define MCF548X_PSC_RFWP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008776))) +#define MCF548X_PSC_TFWP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008796))) +#define MCF548X_PSC_RLRFP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00877A))) +#define MCF548X_PSC_TLRFP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00879A))) +#define MCF548X_PSC_RLWFP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00877E))) +#define MCF548X_PSC_TLWFP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00879E))) +#define MCF548X_PSC_MR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008800))) +#define MCF548X_PSC_SR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008804))) +#define MCF548X_PSC_CSR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008804))) +#define MCF548X_PSC_CR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008808))) +#define MCF548X_PSC_RB2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) +#define MCF548X_PSC_TB2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) +#define MCF548X_PSC_TB_8BIT2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) +#define MCF548X_PSC_TB_16BIT2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) +#define MCF548X_PSC_TB_AC972 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) +#define MCF548X_PSC_IPCR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008810))) +#define MCF548X_PSC_ACR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008810))) +#define MCF548X_PSC_ISR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008814))) +#define MCF548X_PSC_IMR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008814))) +#define MCF548X_PSC_CTUR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008818))) +#define MCF548X_PSC_CTLR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00881C))) +#define MCF548X_PSC_IP2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008834))) +#define MCF548X_PSC_OPSET2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008838))) +#define MCF548X_PSC_OPRESET2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00883C))) +#define MCF548X_PSC_SICR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008840))) +#define MCF548X_PSC_IRCR12 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008844))) +#define MCF548X_PSC_IRCR22 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008848))) +#define MCF548X_PSC_IRSDR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00884C))) +#define MCF548X_PSC_IRMDR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008850))) +#define MCF548X_PSC_IRFDR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008854))) +#define MCF548X_PSC_RFCNT2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008858))) +#define MCF548X_PSC_TFCNT2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00885C))) +#define MCF548X_PSC_RFSR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008864))) +#define MCF548X_PSC_TFSR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008884))) +#define MCF548X_PSC_RFCR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008868))) +#define MCF548X_PSC_TFCR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008888))) +#define MCF548X_PSC_RFAR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00886E))) +#define MCF548X_PSC_TFAR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00888E))) +#define MCF548X_PSC_RFRP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008872))) +#define MCF548X_PSC_TFRP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008892))) +#define MCF548X_PSC_RFWP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008876))) +#define MCF548X_PSC_TFWP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008896))) +#define MCF548X_PSC_RLRFP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00887A))) +#define MCF548X_PSC_TLRFP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00889A))) +#define MCF548X_PSC_RLWFP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00887E))) +#define MCF548X_PSC_TLWFP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00889E))) +#define MCF548X_PSC_MR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008900))) +#define MCF548X_PSC_SR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008904))) +#define MCF548X_PSC_CSR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008904))) +#define MCF548X_PSC_CR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008908))) +#define MCF548X_PSC_RB3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) +#define MCF548X_PSC_TB3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) +#define MCF548X_PSC_TB_8BIT3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) +#define MCF548X_PSC_TB_16BIT3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) +#define MCF548X_PSC_TB_AC973 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) +#define MCF548X_PSC_IPCR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008910))) +#define MCF548X_PSC_ACR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008910))) +#define MCF548X_PSC_ISR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008914))) +#define MCF548X_PSC_IMR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008914))) +#define MCF548X_PSC_CTUR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008918))) +#define MCF548X_PSC_CTLR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00891C))) +#define MCF548X_PSC_IP3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008934))) +#define MCF548X_PSC_OPSET3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008938))) +#define MCF548X_PSC_OPRESET3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00893C))) +#define MCF548X_PSC_SICR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008940))) +#define MCF548X_PSC_IRCR13 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008944))) +#define MCF548X_PSC_IRCR23 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008948))) +#define MCF548X_PSC_IRSDR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00894C))) +#define MCF548X_PSC_IRMDR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008950))) +#define MCF548X_PSC_IRFDR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008954))) +#define MCF548X_PSC_RFCNT3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008958))) +#define MCF548X_PSC_TFCNT3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00895C))) +#define MCF548X_PSC_RFSR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008964))) +#define MCF548X_PSC_TFSR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008984))) +#define MCF548X_PSC_RFCR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008968))) +#define MCF548X_PSC_TFCR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008988))) +#define MCF548X_PSC_RFAR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00896E))) +#define MCF548X_PSC_TFAR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00898E))) +#define MCF548X_PSC_RFRP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008972))) +#define MCF548X_PSC_TFRP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008992))) +#define MCF548X_PSC_RFWP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008976))) +#define MCF548X_PSC_TFWP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008996))) +#define MCF548X_PSC_RLRFP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00897A))) +#define MCF548X_PSC_TLRFP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00899A))) +#define MCF548X_PSC_RLWFP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00897E))) +#define MCF548X_PSC_TLWFP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00899E))) +#define MCF548X_PSC_MR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008600U+((x)*0x100)))) +#define MCF548X_PSC_SR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008604U+((x)*0x100)))) +#define MCF548X_PSC_CSR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008604U+((x)*0x100)))) +#define MCF548X_PSC_CR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008608U+((x)*0x100)))) +#define MCF548X_PSC_RB(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) +#define MCF548X_PSC_TB(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) +#define MCF548X_PSC_TB_8BIT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) +#define MCF548X_PSC_TB_16BIT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) +#define MCF548X_PSC_TB_AC97(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) +#define MCF548X_PSC_IPCR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008610U+((x)*0x100)))) +#define MCF548X_PSC_ACR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008610U+((x)*0x100)))) +#define MCF548X_PSC_ISR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008614U+((x)*0x100)))) +#define MCF548X_PSC_IMR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008614U+((x)*0x100)))) +#define MCF548X_PSC_CTUR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008618U+((x)*0x100)))) +#define MCF548X_PSC_CTLR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00861CU+((x)*0x100)))) +#define MCF548X_PSC_IP(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008634U+((x)*0x100)))) +#define MCF548X_PSC_OPSET(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008638U+((x)*0x100)))) +#define MCF548X_PSC_OPRESET(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00863CU+((x)*0x100)))) +#define MCF548X_PSC_SICR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008640U+((x)*0x100)))) +#define MCF548X_PSC_IRCR1(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008644U+((x)*0x100)))) +#define MCF548X_PSC_IRCR2(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008648U+((x)*0x100)))) +#define MCF548X_PSC_IRSDR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00864CU+((x)*0x100)))) +#define MCF548X_PSC_IRMDR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008650U+((x)*0x100)))) +#define MCF548X_PSC_IRFDR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008654U+((x)*0x100)))) +#define MCF548X_PSC_RFCNT(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008658U+((x)*0x100)))) +#define MCF548X_PSC_TFCNT(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00865CU+((x)*0x100)))) +#define MCF548X_PSC_RFSR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008664U+((x)*0x100)))) +#define MCF548X_PSC_TFSR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008684U+((x)*0x100)))) +#define MCF548X_PSC_RFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008668U+((x)*0x100)))) +#define MCF548X_PSC_TFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008688U+((x)*0x100)))) +#define MCF548X_PSC_RFAR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00866EU+((x)*0x100)))) +#define MCF548X_PSC_TFAR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00868EU+((x)*0x100)))) +#define MCF548X_PSC_RFRP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008672U+((x)*0x100)))) +#define MCF548X_PSC_TFRP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008692U+((x)*0x100)))) +#define MCF548X_PSC_RFWP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008676U+((x)*0x100)))) +#define MCF548X_PSC_TFWP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008696U+((x)*0x100)))) +#define MCF548X_PSC_RLRFP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00867AU+((x)*0x100)))) +#define MCF548X_PSC_TLRFP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00869AU+((x)*0x100)))) +#define MCF548X_PSC_RLWFP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00867EU+((x)*0x100)))) +#define MCF548X_PSC_TLWFP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00869EU+((x)*0x100)))) + +/* Bit definitions and macros for MCF548X_PSC_MR */ +#define MCF548X_PSC_MR_BC(x) (((x)&0x03)<<0) +#define MCF548X_PSC_MR_PT (0x04) +#define MCF548X_PSC_MR_PM(x) (((x)&0x03)<<3) +#define MCF548X_PSC_MR_ERR (0x20) +#define MCF548X_PSC_MR_RXIRQ (0x40) +#define MCF548X_PSC_MR_RXRTS (0x80) +#define MCF548X_PSC_MR_SB(x) (((x)&0x0F)<<0) +#define MCF548X_PSC_MR_TXCTS (0x10) +#define MCF548X_PSC_MR_TXRTS (0x20) +#define MCF548X_PSC_MR_CM(x) (((x)&0x03)<<6) +#define MCF548X_PSC_MR_PM_MULTI_ADDR (0x1C) +#define MCF548X_PSC_MR_PM_MULTI_DATA (0x18) +#define MCF548X_PSC_MR_PM_NONE (0x10) +#define MCF548X_PSC_MR_PM_FORCE_HI (0x0C) +#define MCF548X_PSC_MR_PM_FORCE_LO (0x08) +#define MCF548X_PSC_MR_PM_ODD (0x04) +#define MCF548X_PSC_MR_PM_EVEN (0x00) +#define MCF548X_PSC_MR_BC_5 (0x00) +#define MCF548X_PSC_MR_BC_6 (0x01) +#define MCF548X_PSC_MR_BC_7 (0x02) +#define MCF548X_PSC_MR_BC_8 (0x03) +#define MCF548X_PSC_MR_CM_NORMAL (0x00) +#define MCF548X_PSC_MR_CM_ECHO (0x40) +#define MCF548X_PSC_MR_CM_LOCAL_LOOP (0x80) +#define MCF548X_PSC_MR_CM_REMOTE_LOOP (0xC0) +#define MCF548X_PSC_MR_SB_STOP_BITS_1 (0x07) +#define MCF548X_PSC_MR_SB_STOP_BITS_15 (0x08) +#define MCF548X_PSC_MR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for MCF548X_PSC_SR */ +#define MCF548X_PSC_SR_ERR (0x0040) +#define MCF548X_PSC_SR_CDE_DEOF (0x0080) +#define MCF548X_PSC_SR_RXRDY (0x0100) +#define MCF548X_PSC_SR_FU (0x0200) +#define MCF548X_PSC_SR_TXRDY (0x0400) +#define MCF548X_PSC_SR_TXEMP_URERR (0x0800) +#define MCF548X_PSC_SR_OE (0x1000) +#define MCF548X_PSC_SR_PE_CRCERR (0x2000) +#define MCF548X_PSC_SR_FE_PHYERR (0x4000) +#define MCF548X_PSC_SR_RB_NEOF (0x8000) + +/* Bit definitions and macros for MCF548X_PSC_CSR */ +#define MCF548X_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0) +#define MCF548X_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4) +#define MCF548X_PSC_CSR_RCSEL_SYS_CLK (0xD0) +#define MCF548X_PSC_CSR_RCSEL_CTM16 (0xE0) +#define MCF548X_PSC_CSR_RCSEL_CTM (0xF0) +#define MCF548X_PSC_CSR_TCSEL_SYS_CLK (0x0D) +#define MCF548X_PSC_CSR_TCSEL_CTM16 (0x0E) +#define MCF548X_PSC_CSR_TCSEL_CTM (0x0F) + +/* Bit definitions and macros for MCF548X_PSC_CR */ +#define MCF548X_PSC_CR_RXC(x) (((x)&0x03)<<0) +#define MCF548X_PSC_CR_TXC(x) (((x)&0x03)<<2) +#define MCF548X_PSC_CR_MISC(x) (((x)&0x07)<<4) +#define MCF548X_PSC_CR_NONE (0x00) +#define MCF548X_PSC_CR_STOP_BREAK (0x70) +#define MCF548X_PSC_CR_START_BREAK (0x60) +#define MCF548X_PSC_CR_BKCHGINT (0x50) +#define MCF548X_PSC_CR_RESET_ERROR (0x40) +#define MCF548X_PSC_CR_RESET_TX (0x30) +#define MCF548X_PSC_CR_RESET_RX (0x20) +#define MCF548X_PSC_CR_RESET_MR (0x10) +#define MCF548X_PSC_CR_TX_DISABLED (0x08) +#define MCF548X_PSC_CR_TX_ENABLED (0x04) +#define MCF548X_PSC_CR_RX_DISABLED (0x02) +#define MCF548X_PSC_CR_RX_ENABLED (0x01) + +/* Bit definitions and macros for MCF548X_PSC_TB_8BIT */ +#define MCF548X_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0) +#define MCF548X_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8) +#define MCF548X_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16) +#define MCF548X_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF548X_PSC_TB_16BIT */ +#define MCF548X_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_PSC_TB_AC97 */ +#define MCF548X_PSC_TB_AC97_SOF (0x00000800) +#define MCF548X_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12) + +/* Bit definitions and macros for MCF548X_PSC_IPCR */ +#define MCF548X_PSC_IPCR_RESERVED (0x0C) +#define MCF548X_PSC_IPCR_CTS (0x0D) +#define MCF548X_PSC_IPCR_D_CTS (0x1C) +#define MCF548X_PSC_IPCR_SYNC (0x8C) + +/* Bit definitions and macros for MCF548X_PSC_ACR */ +#define MCF548X_PSC_ACR_IEC0 (0x01) +#define MCF548X_PSC_ACR_CTMS(x) (((x)&0x07)<<4) +#define MCF548X_PSC_ACR_BRG (0x80) + +/* Bit definitions and macros for MCF548X_PSC_ISR */ +#define MCF548X_PSC_ISR_ERR (0x0040) +#define MCF548X_PSC_ISR_DEOF (0x0080) +#define MCF548X_PSC_ISR_TXRDY (0x0100) +#define MCF548X_PSC_ISR_RXRDY_FU (0x0200) +#define MCF548X_PSC_ISR_DB (0x0400) +#define MCF548X_PSC_ISR_IPC (0x8000) + +/* Bit definitions and macros for MCF548X_PSC_IMR */ +#define MCF548X_PSC_IMR_ERR (0x0040) +#define MCF548X_PSC_IMR_DEOF (0x0080) +#define MCF548X_PSC_IMR_TXRDY (0x0100) +#define MCF548X_PSC_IMR_RXRDY_FU (0x0200) +#define MCF548X_PSC_IMR_DB (0x0400) +#define MCF548X_PSC_IMR_IPC (0x8000) + +/* Bit definitions and macros for MCF548X_PSC_IP */ +#define MCF548X_PSC_IP_CTS (0x01) +#define MCF548X_PSC_IP_TGL (0x40) +#define MCF548X_PSC_IP_LWPR_B (0x80) + +/* Bit definitions and macros for MCF548X_PSC_OPSET */ +#define MCF548X_PSC_OPSET_RTS (0x01) + +/* Bit definitions and macros for MCF548X_PSC_OPRESET */ +#define MCF548X_PSC_OPRESET_RTS (0x01) + +/* Bit definitions and macros for MCF548X_PSC_SICR */ +#define MCF548X_PSC_SICR_SIM(x) (((x)&0x07)<<0) +#define MCF548X_PSC_SICR_SHDIR (0x10) +#define MCF548X_PSC_SICR_DTS (0x20) +#define MCF548X_PSC_SICR_AWR (0x40) +#define MCF548X_PSC_SICR_ACRB (0x80) +#define MCF548X_PSC_SICR_SIM_UART (0x00) +#define MCF548X_PSC_SICR_SIM_MODEM8 (0x01) +#define MCF548X_PSC_SICR_SIM_MODEM16 (0x02) +#define MCF548X_PSC_SICR_SIM_AC97 (0x03) +#define MCF548X_PSC_SICR_SIM_SIR (0x04) +#define MCF548X_PSC_SICR_SIM_MIR (0x05) +#define MCF548X_PSC_SICR_SIM_FIR (0x06) + +/* Bit definitions and macros for MCF548X_PSC_IRCR1 */ +#define MCF548X_PSC_IRCR1_SPUL (0x01) +#define MCF548X_PSC_IRCR1_SIPEN (0x02) +#define MCF548X_PSC_IRCR1_FD (0x04) + +/* Bit definitions and macros for MCF548X_PSC_IRCR2 */ +#define MCF548X_PSC_IRCR2_NXTEOF (0x01) +#define MCF548X_PSC_IRCR2_ABORT (0x02) +#define MCF548X_PSC_IRCR2_SIPREQ (0x04) + +/* Bit definitions and macros for MCF548X_PSC_IRMDR */ +#define MCF548X_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0) +#define MCF548X_PSC_IRMDR_FREQ (0x80) + +/* Bit definitions and macros for MCF548X_PSC_IRFDR */ +#define MCF548X_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF548X_PSC_RFCNT */ +#define MCF548X_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_TFCNT */ +#define MCF548X_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_RFSR */ +#define MCF548X_PSC_RFSR_EMT (0x0001) +#define MCF548X_PSC_RFSR_ALARM (0x0002) +#define MCF548X_PSC_RFSR_FU (0x0004) +#define MCF548X_PSC_RFSR_FRMRY (0x0008) +#define MCF548X_PSC_RFSR_OF (0x0010) +#define MCF548X_PSC_RFSR_UF (0x0020) +#define MCF548X_PSC_RFSR_RXW (0x0040) +#define MCF548X_PSC_RFSR_FAE (0x0080) +#define MCF548X_PSC_RFSR_FRM(x) (((x)&0x000F)<<8) +#define MCF548X_PSC_RFSR_TAG (0x1000) +#define MCF548X_PSC_RFSR_TXW (0x4000) +#define MCF548X_PSC_RFSR_IP (0x8000) +#define MCF548X_PSC_RFSR_FRM_BYTE0 (0x0800) +#define MCF548X_PSC_RFSR_FRM_BYTE1 (0x0400) +#define MCF548X_PSC_RFSR_FRM_BYTE2 (0x0200) +#define MCF548X_PSC_RFSR_FRM_BYTE3 (0x0100) + +/* Bit definitions and macros for MCF548X_PSC_TFSR */ +#define MCF548X_PSC_TFSR_EMT (0x0001) +#define MCF548X_PSC_TFSR_ALARM (0x0002) +#define MCF548X_PSC_TFSR_FU (0x0004) +#define MCF548X_PSC_TFSR_FRMRY (0x0008) +#define MCF548X_PSC_TFSR_OF (0x0010) +#define MCF548X_PSC_TFSR_UF (0x0020) +#define MCF548X_PSC_TFSR_RXW (0x0040) +#define MCF548X_PSC_TFSR_FAE (0x0080) +#define MCF548X_PSC_TFSR_FRM(x) (((x)&0x000F)<<8) +#define MCF548X_PSC_TFSR_TAG (0x1000) +#define MCF548X_PSC_TFSR_TXW (0x4000) +#define MCF548X_PSC_TFSR_IP (0x8000) +#define MCF548X_PSC_TFSR_FRM_BYTE0 (0x0800) +#define MCF548X_PSC_TFSR_FRM_BYTE1 (0x0400) +#define MCF548X_PSC_TFSR_FRM_BYTE2 (0x0200) +#define MCF548X_PSC_TFSR_FRM_BYTE3 (0x0100) + +/* Bit definitions and macros for MCF548X_PSC_RFCR */ +#define MCF548X_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_PSC_RFCR_TXW_MSK (0x00040000) +#define MCF548X_PSC_RFCR_OF_MSK (0x00080000) +#define MCF548X_PSC_RFCR_UF_MSK (0x00100000) +#define MCF548X_PSC_RFCR_RXW_MSK (0x00200000) +#define MCF548X_PSC_RFCR_FAE_MSK (0x00400000) +#define MCF548X_PSC_RFCR_IP_MSK (0x00800000) +#define MCF548X_PSC_RFCR_GR(x) (((x)&0x00000007)<<24) +#define MCF548X_PSC_RFCR_FRMEN (0x08000000) +#define MCF548X_PSC_RFCR_TIMER (0x10000000) +#define MCF548X_PSC_RFCR_WRITETAG (0x20000000) +#define MCF548X_PSC_RFCR_SHADOW (0x80000000) + +/* Bit definitions and macros for MCF548X_PSC_TFCR */ +#define MCF548X_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_PSC_TFCR_TXW_MSK (0x00040000) +#define MCF548X_PSC_TFCR_OF_MSK (0x00080000) +#define MCF548X_PSC_TFCR_UF_MSK (0x00100000) +#define MCF548X_PSC_TFCR_RXW_MSK (0x00200000) +#define MCF548X_PSC_TFCR_FAE_MSK (0x00400000) +#define MCF548X_PSC_TFCR_IP_MSK (0x00800000) +#define MCF548X_PSC_TFCR_GR(x) (((x)&0x00000007)<<24) +#define MCF548X_PSC_TFCR_FRMEN (0x08000000) +#define MCF548X_PSC_TFCR_TIMER (0x10000000) +#define MCF548X_PSC_TFCR_WRITETAG (0x20000000) +#define MCF548X_PSC_TFCR_SHADOW (0x80000000) + +/* Bit definitions and macros for MCF548X_PSC_RFAR */ +#define MCF548X_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_TFAR */ +#define MCF548X_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_RFRP */ +#define MCF548X_PSC_RFRP_READ(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_TFRP */ +#define MCF548X_PSC_TFRP_READ(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_RFWP */ +#define MCF548X_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_TFWP */ +#define MCF548X_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_RLRFP */ +#define MCF548X_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_TLRFP */ +#define MCF548X_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_RLWFP */ +#define MCF548X_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_TLWFP */ +#define MCF548X_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0) + + +/********************************************************************* +* +* 32KByte System SRAM (SRAM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_SRAM_SSCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFC0))) +#define MCF548X_SRAM_TCCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFC4))) +#define MCF548X_SRAM_TCCRDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFC8))) +#define MCF548X_SRAM_TCCRDW (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFCC))) +#define MCF548X_SRAM_TCCRSEC (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFD0))) + +/* Bit definitions and macros for MCF548X_SRAM_SSCR */ +#define MCF548X_SRAM_SSCR_INLV (0x00010000) + +/* Bit definitions and macros for MCF548X_SRAM_TCCR */ +#define MCF548X_SRAM_TCCR_BANK0_TC(x) (((x)&0x0000000F)<<0) +#define MCF548X_SRAM_TCCR_BANK1_TC(x) (((x)&0x0000000F)<<8) +#define MCF548X_SRAM_TCCR_BANK2_TC(x) (((x)&0x0000000F)<<16) +#define MCF548X_SRAM_TCCR_BANK3_TC(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_SRAM_TCCRDR */ +#define MCF548X_SRAM_TCCRDR_BANK0_TC(x) (((x)&0x0000000F)<<0) +#define MCF548X_SRAM_TCCRDR_BANK1_TC(x) (((x)&0x0000000F)<<8) +#define MCF548X_SRAM_TCCRDR_BANK2_TC(x) (((x)&0x0000000F)<<16) +#define MCF548X_SRAM_TCCRDR_BANK3_TC(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_SRAM_TCCRDW */ +#define MCF548X_SRAM_TCCRDW_BANK0_TC(x) (((x)&0x0000000F)<<0) +#define MCF548X_SRAM_TCCRDW_BANK1_TC(x) (((x)&0x0000000F)<<8) +#define MCF548X_SRAM_TCCRDW_BANK2_TC(x) (((x)&0x0000000F)<<16) +#define MCF548X_SRAM_TCCRDW_BANK3_TC(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_SRAM_TCCRSEC */ +#define MCF548X_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0x0000000F)<<0) +#define MCF548X_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0x0000000F)<<8) +#define MCF548X_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0x0000000F)<<16) +#define MCF548X_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0x0000000F)<<24) + + +/********************************************************************* +* +* PCI Bus Controller (PCI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_PCI_PCIIDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B00))) +#define MCF548X_PCI_PCISCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B04))) +#define MCF548X_PCI_PCICCRIR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B08))) +#define MCF548X_PCI_PCICR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B0C))) +#define MCF548X_PCI_PCIBAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B10))) +#define MCF548X_PCI_PCIBAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B14))) +#define MCF548X_PCI_PCICR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B3C))) +#define MCF548X_PCI_PCIGSCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B60))) +#define MCF548X_PCI_PCITBATR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B64))) +#define MCF548X_PCI_PCITBATR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B68))) +#define MCF548X_PCI_PCITCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B6C))) +#define MCF548X_PCI_PCIIW0BTAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B70))) +#define MCF548X_PCI_PCIIW1BTAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B74))) +#define MCF548X_PCI_PCIIW2BTAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B78))) +#define MCF548X_PCI_PCIIWCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B80))) +#define MCF548X_PCI_PCIICR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B84))) +#define MCF548X_PCI_PCIISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B88))) +#define MCF548X_PCI_PCICAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000BF8))) +#define MCF548X_PCI_PCITPSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008400))) +#define MCF548X_PCI_PCITSAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008404))) +#define MCF548X_PCI_PCITTCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008408))) +#define MCF548X_PCI_PCITER (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00840C))) +#define MCF548X_PCI_PCITNAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008410))) +#define MCF548X_PCI_PCITLWR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008414))) +#define MCF548X_PCI_PCITDCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008418))) +#define MCF548X_PCI_PCITSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00841C))) +#define MCF548X_PCI_PCITFDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008440))) +#define MCF548X_PCI_PCITFSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008444))) +#define MCF548X_PCI_PCITFCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008448))) +#define MCF548X_PCI_PCITFAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00844C))) +#define MCF548X_PCI_PCITFRPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008450))) +#define MCF548X_PCI_PCITFWPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008454))) +#define MCF548X_PCI_PCIRPSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008480))) +#define MCF548X_PCI_PCIRSAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008484))) +#define MCF548X_PCI_PCIRTCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008488))) +#define MCF548X_PCI_PCIRER (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00848C))) +#define MCF548X_PCI_PCIRNAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008490))) +#define MCF548X_PCI_PCIRDCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008498))) +#define MCF548X_PCI_PCIRSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00849C))) +#define MCF548X_PCI_PCIRFDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084C0))) +#define MCF548X_PCI_PCIRFSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084C4))) +#define MCF548X_PCI_PCIRFCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084C8))) +#define MCF548X_PCI_PCIRFAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084CC))) +#define MCF548X_PCI_PCIRFRPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084D0))) +#define MCF548X_PCI_PCIRFWPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084D4))) + +/* Bit definitions and macros for MCF548X_PCI_PCIIDR */ +#define MCF548X_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_PCI_PCISCR */ +#define MCF548X_PCI_PCISCR_M (0x00000002) +#define MCF548X_PCI_PCISCR_B (0x00000004) +#define MCF548X_PCI_PCISCR_SP (0x00000008) +#define MCF548X_PCI_PCISCR_MW (0x00000010) +#define MCF548X_PCI_PCISCR_PER (0x00000040) +#define MCF548X_PCI_PCISCR_S (0x00000100) +#define MCF548X_PCI_PCISCR_F (0x00000200) +#define MCF548X_PCI_PCISCR_C (0x00100000) +#define MCF548X_PCI_PCISCR_66M (0x00200000) +#define MCF548X_PCI_PCISCR_R (0x00400000) +#define MCF548X_PCI_PCISCR_FC (0x00800000) +#define MCF548X_PCI_PCISCR_DP (0x01000000) +#define MCF548X_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25) +#define MCF548X_PCI_PCISCR_TS (0x08000000) +#define MCF548X_PCI_PCISCR_TR (0x10000000) +#define MCF548X_PCI_PCISCR_MA (0x20000000) +#define MCF548X_PCI_PCISCR_SE (0x40000000) +#define MCF548X_PCI_PCISCR_PE (0x80000000) + +/* Bit definitions and macros for MCF548X_PCI_PCICCRIR */ +#define MCF548X_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0) +#define MCF548X_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8) + +/* Bit definitions and macros for MCF548X_PCI_PCICR1 */ +#define MCF548X_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0) +#define MCF548X_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8) +#define MCF548X_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIBAR0 */ +#define MCF548X_PCI_PCIBAR0_IO (0x00000001) +#define MCF548X_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1) +#define MCF548X_PCI_PCIBAR0_PREF (0x00000008) +#define MCF548X_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18) + +/* Bit definitions and macros for MCF548X_PCI_PCIBAR1 */ +#define MCF548X_PCI_PCIBAR1_IO (0x00000001) +#define MCF548X_PCI_PCIBAR1_PREF (0x00000008) +#define MCF548X_PCI_PCIBAR1_BAR1(x) (((x)&0x00000003)<<30) + +/* Bit definitions and macros for MCF548X_PCI_PCICR2 */ +#define MCF548X_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0) +#define MCF548X_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8) +#define MCF548X_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIGSCR */ +#define MCF548X_PCI_PCIGSCR_PR (0x00000001) +#define MCF548X_PCI_PCIGSCR_SEE (0x00001000) +#define MCF548X_PCI_PCIGSCR_PEE (0x00002000) +#define MCF548X_PCI_PCIGSCR_SE (0x10000000) +#define MCF548X_PCI_PCIGSCR_PE (0x20000000) + +/* Bit definitions and macros for MCF548X_PCI_PCITBATR0 */ +#define MCF548X_PCI_PCITBATR0_EN (0x00000001) +#define MCF548X_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18) + +/* Bit definitions and macros for MCF548X_PCI_PCITBATR1 */ +#define MCF548X_PCI_PCITBATR1_EN (0x00000001) +#define MCF548X_PCI_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30) + +/* Bit definitions and macros for MCF548X_PCI_PCITCR */ +#define MCF548X_PCI_PCITCR_P (0x00010000) +#define MCF548X_PCI_PCITCR_LD (0x01000000) + +/* Bit definitions and macros for MCF548X_PCI_PCIIW0BTAR */ +#define MCF548X_PCI_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8) +#define MCF548X_PCI_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIIW1BTAR */ +#define MCF548X_PCI_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8) +#define MCF548X_PCI_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIIW2BTAR */ +#define MCF548X_PCI_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8) +#define MCF548X_PCI_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIIWCR */ +#define MCF548X_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8) +#define MCF548X_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16) +#define MCF548X_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24) +#define MCF548X_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000) +#define MCF548X_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000) +#define MCF548X_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000) +#define MCF548X_PCI_PCIIWCR_WINCTRL0_IO (0x09000000) +#define MCF548X_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000) +#define MCF548X_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000) +#define MCF548X_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000) +#define MCF548X_PCI_PCIIWCR_WINCTRL1_IO (0x00090000) +#define MCF548X_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100) +#define MCF548X_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300) +#define MCF548X_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500) +#define MCF548X_PCI_PCIIWCR_WINCTRL2_IO (0x00000900) + +/* Bit definitions and macros for MCF548X_PCI_PCIICR */ +#define MCF548X_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0) +#define MCF548X_PCI_PCIICR_TAE (0x01000000) +#define MCF548X_PCI_PCIICR_IAE (0x02000000) +#define MCF548X_PCI_PCIICR_REE (0x04000000) + +/* Bit definitions and macros for MCF548X_PCI_PCIISR */ +#define MCF548X_PCI_PCIISR_TA (0x01000000) +#define MCF548X_PCI_PCIISR_IA (0x02000000) +#define MCF548X_PCI_PCIISR_RE (0x04000000) + +/* Bit definitions and macros for MCF548X_PCI_PCICAR */ +#define MCF548X_PCI_PCICAR_DWORD(x) (((x)&0x0000003F)<<2) +#define MCF548X_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8) +#define MCF548X_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11) +#define MCF548X_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCICAR_E (0x80000000) + +/* Bit definitions and macros for MCF548X_PCI_PCITPSR */ +#define MCF548X_PCI_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_PCI_PCITTCR */ +#define MCF548X_PCI_PCITTCR_DI (0x00000001) +#define MCF548X_PCI_PCITTCR_W (0x00000010) +#define MCF548X_PCI_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8) +#define MCF548X_PCI_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCITER */ +#define MCF548X_PCI_PCITER_NE (0x00010000) +#define MCF548X_PCI_PCITER_IAE (0x00020000) +#define MCF548X_PCI_PCITER_TAE (0x00040000) +#define MCF548X_PCI_PCITER_RE (0x00080000) +#define MCF548X_PCI_PCITER_SE (0x00100000) +#define MCF548X_PCI_PCITER_FEE (0x00200000) +#define MCF548X_PCI_PCITER_ME (0x01000000) +#define MCF548X_PCI_PCITER_BE (0x08000000) +#define MCF548X_PCI_PCITER_CM (0x10000000) +#define MCF548X_PCI_PCITER_RF (0x40000000) +#define MCF548X_PCI_PCITER_RC (0x80000000) + +/* Bit definitions and macros for MCF548X_PCI_PCITDCR */ +#define MCF548X_PCI_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_PCI_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_PCI_PCITSR */ +#define MCF548X_PCI_PCITSR_IA (0x00010000) +#define MCF548X_PCI_PCITSR_TA (0x00020000) +#define MCF548X_PCI_PCITSR_RE (0x00040000) +#define MCF548X_PCI_PCITSR_SE (0x00080000) +#define MCF548X_PCI_PCITSR_FE (0x00100000) +#define MCF548X_PCI_PCITSR_BE1 (0x00200000) +#define MCF548X_PCI_PCITSR_BE2 (0x00400000) +#define MCF548X_PCI_PCITSR_BE3 (0x00800000) +#define MCF548X_PCI_PCITSR_NT (0x01000000) + +/* Bit definitions and macros for MCF548X_PCI_PCITFSR */ +#define MCF548X_PCI_PCITFSR_EMT (0x00010000) +#define MCF548X_PCI_PCITFSR_ALARM (0x00020000) +#define MCF548X_PCI_PCITFSR_FU (0x00040000) +#define MCF548X_PCI_PCITFSR_FR (0x00080000) +#define MCF548X_PCI_PCITFSR_OF (0x00100000) +#define MCF548X_PCI_PCITFSR_UF (0x00200000) +#define MCF548X_PCI_PCITFSR_RXW (0x00400000) + +/* Bit definitions and macros for MCF548X_PCI_PCITFCR */ +#define MCF548X_PCI_PCITFCR_OF_MSK (0x00080000) +#define MCF548X_PCI_PCITFCR_UF_MSK (0x00100000) +#define MCF548X_PCI_PCITFCR_RXW_MSK (0x00200000) +#define MCF548X_PCI_PCITFCR_FAE_MSK (0x00400000) +#define MCF548X_PCI_PCITFCR_IP_MSK (0x00800000) +#define MCF548X_PCI_PCITFCR_GR(x) (((x)&0x00000007)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCITFAR */ +#define MCF548X_PCI_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0) + +/* Bit definitions and macros for MCF548X_PCI_PCITFRPR */ +#define MCF548X_PCI_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_PCI_PCITFWPR */ +#define MCF548X_PCI_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_PCI_PCIRPSR */ +#define MCF548X_PCI_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_PCI_PCIRTCR */ +#define MCF548X_PCI_PCIRTCR_DI (0x00000001) +#define MCF548X_PCI_PCIRTCR_W (0x00000010) +#define MCF548X_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8) +#define MCF548X_PCI_PCIRTCR_FB (0x00001000) +#define MCF548X_PCI_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIRER */ +#define MCF548X_PCI_PCIRER_NE (0x00010000) +#define MCF548X_PCI_PCIRER_IAE (0x00020000) +#define MCF548X_PCI_PCIRER_TAE (0x00040000) +#define MCF548X_PCI_PCIRER_RE (0x00080000) +#define MCF548X_PCI_PCIRER_SE (0x00100000) +#define MCF548X_PCI_PCIRER_FEE (0x00200000) +#define MCF548X_PCI_PCIRER_ME (0x01000000) +#define MCF548X_PCI_PCIRER_BE (0x08000000) +#define MCF548X_PCI_PCIRER_CM (0x10000000) +#define MCF548X_PCI_PCIRER_FE (0x20000000) +#define MCF548X_PCI_PCIRER_RF (0x40000000) +#define MCF548X_PCI_PCIRER_RC (0x80000000) + +/* Bit definitions and macros for MCF548X_PCI_PCIRDCR */ +#define MCF548X_PCI_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_PCI_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_PCI_PCIRSR */ +#define MCF548X_PCI_PCIRSR_IA (0x00010000) +#define MCF548X_PCI_PCIRSR_TA (0x00020000) +#define MCF548X_PCI_PCIRSR_RE (0x00040000) +#define MCF548X_PCI_PCIRSR_SE (0x00080000) +#define MCF548X_PCI_PCIRSR_FE (0x00100000) +#define MCF548X_PCI_PCIRSR_BE1 (0x00200000) +#define MCF548X_PCI_PCIRSR_BE2 (0x00400000) +#define MCF548X_PCI_PCIRSR_BE3 (0x00800000) +#define MCF548X_PCI_PCIRSR_NT (0x01000000) + +/* Bit definitions and macros for MCF548X_PCI_PCIRFSR */ +#define MCF548X_PCI_PCIRFSR_EMT (0x00010000) +#define MCF548X_PCI_PCIRFSR_ALARM (0x00020000) +#define MCF548X_PCI_PCIRFSR_FU (0x00040000) +#define MCF548X_PCI_PCIRFSR_FR (0x00080000) +#define MCF548X_PCI_PCIRFSR_OF (0x00100000) +#define MCF548X_PCI_PCIRFSR_UF (0x00200000) +#define MCF548X_PCI_PCIRFSR_RXW (0x00400000) + +/* Bit definitions and macros for MCF548X_PCI_PCIRFCR */ +#define MCF548X_PCI_PCIRFCR_OF_MSK (0x00080000) +#define MCF548X_PCI_PCIRFCR_UF_MSK (0x00100000) +#define MCF548X_PCI_PCIRFCR_RXW_MSK (0x00200000) +#define MCF548X_PCI_PCIRFCR_FAE_MSK (0x00400000) +#define MCF548X_PCI_PCIRFCR_IP_MSK (0x00800000) +#define MCF548X_PCI_PCIRFCR_GR(x) (((x)&0x00000007)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIRFAR */ +#define MCF548X_PCI_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0) + +/* Bit definitions and macros for MCF548X_PCI_PCIRFRPR */ +#define MCF548X_PCI_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_PCI_PCIRFWPR */ +#define MCF548X_PCI_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0) + + +/********************************************************************* +* +* PCI Arbiter Module (PCIARB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_PCIARB_PACR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000C00))) +#define MCF548X_PCIARB_PASR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000C04))) + +/* Bit definitions and macros for MCF548X_PCIARB_PACR */ +#define MCF548X_PCIARB_PACR_INTMPRI (0x00000001) +#define MCF548X_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1) +#define MCF548X_PCIARB_PACR_INTMINTEN (0x00010000) +#define MCF548X_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17) +#define MCF548X_PCIARB_PACR_PKMD (0x40000000) +#define MCF548X_PCIARB_PACR_DS (0x80000000) + +/* Bit definitions and macros for MCF548X_PCIARB_PASR */ +#define MCF548X_PCIARB_PASR_ITLMBK (0x00010000) +#define MCF548X_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17) + + +/********************************************************************* +* +* Multi-Channel DMA (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_DMA_TASKBAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008000))) +#define MCF548X_DMA_CP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008004))) +#define MCF548X_DMA_EP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008008))) +#define MCF548X_DMA_VP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00800C))) +#define MCF548X_DMA_DIPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008014))) +#define MCF548X_DMA_DIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008018))) +#define MCF548X_DMA_TCR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00801C))) +#define MCF548X_DMA_TCR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00801E))) +#define MCF548X_DMA_TCR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008020))) +#define MCF548X_DMA_TCR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008022))) +#define MCF548X_DMA_TCR4 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008024))) +#define MCF548X_DMA_TCR5 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008026))) +#define MCF548X_DMA_TCR6 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008028))) +#define MCF548X_DMA_TCR7 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00802A))) +#define MCF548X_DMA_TCR8 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00802C))) +#define MCF548X_DMA_TCR9 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00802E))) +#define MCF548X_DMA_TCR10 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008030))) +#define MCF548X_DMA_TCR11 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008032))) +#define MCF548X_DMA_TCR12 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008034))) +#define MCF548X_DMA_TCR13 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008036))) +#define MCF548X_DMA_TCR14 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008038))) +#define MCF548X_DMA_TCR15 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00803A))) +#define MCF548X_DMA_TCRn(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00801CU+((x)*0x002)))) +#define MCF548X_DMA_IMCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00805C))) +#define MCF548X_DMA_PTDDBG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008080))) + +/* Bit definitions and macros for MCF548X_DMA_DIPR */ +#define MCF548X_DMA_DIPR_TASK0 (0x00000001) +#define MCF548X_DMA_DIPR_TASK1 (0x00000002) +#define MCF548X_DMA_DIPR_TASK2 (0x00000004) +#define MCF548X_DMA_DIPR_TASK3 (0x00000008) +#define MCF548X_DMA_DIPR_TASK4 (0x00000010) +#define MCF548X_DMA_DIPR_TASK5 (0x00000020) +#define MCF548X_DMA_DIPR_TASK6 (0x00000040) +#define MCF548X_DMA_DIPR_TASK7 (0x00000080) +#define MCF548X_DMA_DIPR_TASK8 (0x00000100) +#define MCF548X_DMA_DIPR_TASK9 (0x00000200) +#define MCF548X_DMA_DIPR_TASK10 (0x00000400) +#define MCF548X_DMA_DIPR_TASK11 (0x00000800) +#define MCF548X_DMA_DIPR_TASK12 (0x00001000) +#define MCF548X_DMA_DIPR_TASK13 (0x00002000) +#define MCF548X_DMA_DIPR_TASK14 (0x00004000) +#define MCF548X_DMA_DIPR_TASK15 (0x00008000) + +/* Bit definitions and macros for MCF548X_DMA_DIMR */ +#define MCF548X_DMA_DIMR_TASK0 (0x00000001) +#define MCF548X_DMA_DIMR_TASK1 (0x00000002) +#define MCF548X_DMA_DIMR_TASK2 (0x00000004) +#define MCF548X_DMA_DIMR_TASK3 (0x00000008) +#define MCF548X_DMA_DIMR_TASK4 (0x00000010) +#define MCF548X_DMA_DIMR_TASK5 (0x00000020) +#define MCF548X_DMA_DIMR_TASK6 (0x00000040) +#define MCF548X_DMA_DIMR_TASK7 (0x00000080) +#define MCF548X_DMA_DIMR_TASK8 (0x00000100) +#define MCF548X_DMA_DIMR_TASK9 (0x00000200) +#define MCF548X_DMA_DIMR_TASK10 (0x00000400) +#define MCF548X_DMA_DIMR_TASK11 (0x00000800) +#define MCF548X_DMA_DIMR_TASK12 (0x00001000) +#define MCF548X_DMA_DIMR_TASK13 (0x00002000) +#define MCF548X_DMA_DIMR_TASK14 (0x00004000) +#define MCF548X_DMA_DIMR_TASK15 (0x00008000) + +/* Bit definitions and macros for MCF548X_DMA_IMCR */ +#define MCF548X_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0) +#define MCF548X_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2) +#define MCF548X_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4) +#define MCF548X_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6) +#define MCF548X_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8) +#define MCF548X_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10) +#define MCF548X_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12) +#define MCF548X_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14) +#define MCF548X_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16) +#define MCF548X_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18) +#define MCF548X_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20) +#define MCF548X_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22) +#define MCF548X_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24) +#define MCF548X_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26) +#define MCF548X_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28) +#define MCF548X_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30) +#define MCF548X_DMA_IMCR_SRC16_FEC0RX (0x00000000) +#define MCF548X_DMA_IMCR_SRC17_FEC0TX (0x00000000) +#define MCF548X_DMA_IMCR_SRC18_FEC0RX (0x00000020) +#define MCF548X_DMA_IMCR_SRC19_FEC0TX (0x00000080) +#define MCF548X_DMA_IMCR_SRC20_FEC1RX (0x00000100) +#define MCF548X_DMA_IMCR_SRC21_DREQ1 (0x00000000) +#define MCF548X_DMA_IMCR_SRC21_FEC1TX (0x00000400) +#define MCF548X_DMA_IMCR_SRC22_FEC0RX (0x00001000) +#define MCF548X_DMA_IMCR_SRC23_FEC0TX (0x00004000) +#define MCF548X_DMA_IMCR_SRC24_CTM0 (0x00010000) +#define MCF548X_DMA_IMCR_SRC24_FEC1RX (0x00020000) +#define MCF548X_DMA_IMCR_SRC25_CTM1 (0x00040000) +#define MCF548X_DMA_IMCR_SRC25_FEC1TX (0x00080000) +#define MCF548X_DMA_IMCR_SRC26_USBEP4 (0x00000000) +#define MCF548X_DMA_IMCR_SRC26_CTM2 (0x00200000) +#define MCF548X_DMA_IMCR_SRC27_USBEP5 (0x00000000) +#define MCF548X_DMA_IMCR_SRC27_CTM3 (0x00800000) +#define MCF548X_DMA_IMCR_SRC28_USBEP6 (0x00000000) +#define MCF548X_DMA_IMCR_SRC28_CTM4 (0x01000000) +#define MCF548X_DMA_IMCR_SRC28_DREQ1 (0x02000000) +#define MCF548X_DMA_IMCR_SRC28_PSC2RX (0x03000000) +#define MCF548X_DMA_IMCR_SRC29_DREQ1 (0x04000000) +#define MCF548X_DMA_IMCR_SRC29_CTM5 (0x08000000) +#define MCF548X_DMA_IMCR_SRC29_PSC2TX (0x0C000000) +#define MCF548X_DMA_IMCR_SRC30_FEC1RX (0x00000000) +#define MCF548X_DMA_IMCR_SRC30_CTM6 (0x10000000) +#define MCF548X_DMA_IMCR_SRC30_PSC3RX (0x30000000) +#define MCF548X_DMA_IMCR_SRC31_FEC1TX (0x00000000) +#define MCF548X_DMA_IMCR_SRC31_CTM7 (0x80000000) +#define MCF548X_DMA_IMCR_SRC31_PSC3TX (0xC0000000) + + +/********************************************************************* +* +* Multi-Channel DMA External Requests (DMA_EREQ) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_DMA_EREQ_EREQBAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D00))) +#define MCF548X_DMA_EREQ_EREQMASK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D04))) +#define MCF548X_DMA_EREQ_EREQCTRL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D08))) +#define MCF548X_DMA_EREQ_EREQBAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D10))) +#define MCF548X_DMA_EREQ_EREQMASK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D14))) +#define MCF548X_DMA_EREQ_EREQCTRL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D18))) +#define MCF548X_DMA_EREQ_EREQBAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D00U+((x)*0x010)))) +#define MCF548X_DMA_EREQ_EREQMASK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D04U+((x)*0x010)))) +#define MCF548X_DMA_EREQ_EREQCTRL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D08U+((x)*0x010)))) + +/* Bit definitions and macros for MCF548X_DMA_EREQ_EREQCTRL */ +#define MCF548X_DMA_EREQ_EREQCTRL_EN (0x00000001) +#define MCF548X_DMA_EREQ_EREQCTRL_SYNC (0x00000002) +#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID(x) (((x)&0x00000003)<<2) +#define MCF548X_DMA_EREQ_EREQCTRL_BSEL(x) (((x)&0x00000003)<<4) +#define MCF548X_DMA_EREQ_EREQCTRL_MD(x) (((x)&0x00000003)<<6) +#define MCF548X_DMA_EREQ_EREQCTRL_MD_IDLE (0x00000000) +#define MCF548X_DMA_EREQ_EREQCTRL_MD_LEVEL (0x00000040) +#define MCF548X_DMA_EREQ_EREQCTRL_MD_EDGE (0x00000080) +#define MCF548X_DMA_EREQ_EREQCTRL_MD_PIPED (0x000000C0) +#define MCF548X_DMA_EREQ_EREQCTRL_BSEL_MEM_WRITE (0x00000000) +#define MCF548X_DMA_EREQ_EREQCTRL_BSEL_MEM_READ (0x00000010) +#define MCF548X_DMA_EREQ_EREQCTRL_BSEL_PERIPH_WRITE (0x00000020) +#define MCF548X_DMA_EREQ_EREQCTRL_BSEL_PERIPH_READ (0x00000030) +#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID_ONE (0x00000000) +#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID_TWO (0x00000004) +#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID_THREE (0x00000008) +#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID_FOUR (0x0000000C) + +/*********************************************************************/ + +#endif /* __MCF548X_H__ */ diff --git a/bsps/m68k/include/mvme16x_hw.h b/bsps/m68k/include/mvme16x_hw.h new file mode 100644 index 0000000000..2ac595a0fa --- /dev/null +++ b/bsps/m68k/include/mvme16x_hw.h @@ -0,0 +1,274 @@ +/** + * @file + * + * @ingroup m68k_mvme + * + * @brief MVME16x IO definitions + */ + +/* mvme16x_hw.h + * + * This include file contains all MVME16x board IO definitions + * and was derived by combining the common items in the + * mvme162 and mvme167 BSPs. + * + * COPYRIGHT (c) 1989-2000. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __MVME16xHW_h +#define __MVME16xHW_h + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup m68k_mvme MVME16X IO Support + * + * @ingroup m68k_shared + * + * @brief IO Support Package + */ + +struct rtems_bsdnet_ifconfig; +int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching ); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "uti1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach + +/* + * This is NOT the base address of local RAM! + * This is the base local address of the VMEbus short I/O space. A local + * access to this space results in a A16 VMEbus I/O cycle. This base address + * is NOT configurable on the MVME167, although the types of VMEbus short I/O + * cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address + * range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The + * GCSRs of other boards are accessible only through the VMEbus short I/O + * space. See pages 2-45 and 2-7. + */ +#define BOARD_BASE_ADDRESS 0xFFFF0000 + +/* + * This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of + * other MVMEs in the group, i.e. it represents the offset of the GCSRs in the + * VMEbus short I/O space. It also should represent the group address of this + * MVME167! The group address is configurable, and must match the address + * programmed into the MVME167 through the 167Bug monitor. 0xCC is the address + * recommended by Motorola. It is arbitrary. + * See pages 2-42 and 2-97 to 2-104. + */ +#define GROUP_BASE_ADDRESS 0x0000CC00 + +/* + * Representation of the VMEchip2 LCSR. + * Could be made more detailed. + */ + +typedef volatile struct { + unsigned long slave_adr[2]; + unsigned long slave_trn[2]; + unsigned long slave_ctl; + unsigned long mastr_adr[4]; + unsigned long mastr_trn; + unsigned long mastr_att; + unsigned long mastr_ctl; + unsigned long dma_ctl_1; + unsigned long dma_ctl_2; + unsigned long dma_loc_cnt; + unsigned long dma_vme_cnt; + unsigned long dma_byte_cnt; + unsigned long dma_adr_cnt; + unsigned long dma_status; + unsigned long to_ctl; + unsigned long timer_cmp_1; + unsigned long timer_cnt_1; + unsigned long timer_cmp_2; + unsigned long timer_cnt_2; + unsigned long board_ctl; + unsigned long prescaler_cnt; + unsigned long intr_stat; + unsigned long intr_ena; + unsigned long intr_soft_set; + unsigned long intr_clear; + unsigned long intr_level[4]; + unsigned long vector_base; +} lcsr_regs; + +/* + * Base address of VMEchip2 LCSR + * Not configurable on the MVME167. + * XXX what about 162? + */ +#define lcsr ((lcsr_regs * const) 0xFFF40000) + +/* + * Vector numbers for the interrupts from the VMEchip2. Use the values + * "recommended" by Motorola. + * See pages 2-70 to 2-92, and table 2-3. + */ + +/* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */ +#define MASK_INT 0x00800000 + +/* The content of VBR0 corresponds to "X" in table 2-3 */ +#define VBR0 0x6 + +/* The content of VBR1 corresponds to "Y" in table 2-3 */ +#define VBR1 0x7 + +/* + * Representation of the PCCchip2 + */ +typedef volatile struct pccchip2_regs_ { + unsigned char chip_id; /* 0xFFF42000 */ + unsigned char chip_revision; /* 0xFFF42001 */ + unsigned char gen_control; /* 0xFFF42002 */ + unsigned char vector_base; /* 0xFFF42003 */ + unsigned long timer_cmp_1; /* 0xFFF42004 */ + unsigned long timer_cnt_1; /* 0xFFF42008 */ + unsigned long timer_cmp_2; /* 0xFFF4200C */ + unsigned long timer_cnt_2; /* 0xFFF42010 */ + unsigned char LSB_prescaler_count;/* 0xFFF42014 */ + unsigned char prescaler_clock_adjust; /* 0xFFF42015 */ + unsigned char timer_ctl_2; /* 0xFFF42016 */ + unsigned char timer_ctl_1; /* 0xFFF42017 */ + unsigned char gpi_int_ctl; /* 0xFFF42018 */ + unsigned char gpio_ctl; /* 0xFFF42019 */ + unsigned char timer_int_ctl_2; /* 0xFFF4201A */ + unsigned char timer_int_ctl_1; /* 0xFFF4201B */ + unsigned char SCC_error; /* 0xFFF4201C */ + unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */ + unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */ + unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */ + unsigned char reserved1[3]; + unsigned char modem_piack; /* 0xFFF42023 */ + unsigned char reserved2; + unsigned char tx_piack; /* 0xFFF42025 */ + unsigned char reserved3; + unsigned char rx_piack; /* 0xFFF42027 */ + unsigned char LANC_error; /* 0xFFF42028 */ + unsigned char reserved4; + unsigned char LANC_int_ctl; /* 0xFFF4202A */ + unsigned char LANC_berr_ctl; /* 0xFFF4202B */ + unsigned char SCSI_error; /* 0xFFF4202C */ + unsigned char reserved5[2]; + unsigned char SCSI_int_ctl; /* 0xFFF4202F */ + unsigned char print_ack_int_ctl; /* 0xFFF42030 */ + unsigned char print_fault_int_ctl;/* 0xFFF42031 */ + unsigned char print_sel_int_ctl; /* 0xFFF42032 */ + unsigned char print_pe_int_ctl; /* 0xFFF42033 */ + unsigned char print_busy_int_ctl; /* 0xFFF42034 */ + unsigned char reserved6; + unsigned char print_input_status; /* 0xFFF42036 */ + unsigned char print_ctl; /* 0xFFF42037 */ + unsigned char chip_speed; /* 0xFFF42038 */ + unsigned char reserved7; + unsigned char print_data; /* 0xFFF4203A */ + unsigned char reserved8[3]; + unsigned char int_level; /* 0xFFF4203E */ + unsigned char int_mask; /* 0xFFF4203F */ +} pccchip2_regs; + +/* + * Base address of the PCCchip2. + * This is not configurable in the MVME167. + */ +#define pccchip2 ((pccchip2_regs * const) 0xFFF42000) + +/* + * On the MVME162, we have the mcchip and the pccchip2 on + * the 167. They are similar but different enough where + * we have to reconcile them later. + */ + +/* + * Vector numbers for the interrupts from the PCCchip2. Use the values + * "recommended" by Motorola. + * See page 3-15. + */ +#define PCCCHIP2_VBR 0x5 + +/* + * The following registers are located in the VMEbus short + * IO space and respond to address modifier codes $29 and $2D. + * On FORCE CPU use address gcsr_vme and device /dev/vme16d32. + */ + +typedef volatile struct { + unsigned char chip_revision; + unsigned char chip_id; + unsigned char lmsig; + unsigned char board_scr; + unsigned short gpr[6]; +} gcsr_regs; + +#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS)) +#define gcsr ((gcsr_regs * const) 0xFFF40100) + +/* + * Representation of 82596CA LAN controller: Memory Map + */ +typedef volatile struct i82596_regs_ { + unsigned short port_lower; /* 0xFFF46000 */ + unsigned short port_upper; /* 0xFFF46002 */ + unsigned long chan_attn; /* 0xFFF46004 */ +} i82596_regs; + +/* + * Base address of the 82596. + */ + +#define i82596 ((i82596_regs * const) 0xFFF46000) + +/* + * Representation of initialization data in NVRAM + */ + +#if defined(mvme167) +typedef volatile struct nvram_config_ { + unsigned char cache_mode; /* 0xFFFC0000 */ + unsigned char console_mode; /* 0xFFFC0001 */ + unsigned char console_printk_port; /* 0xFFFC0002 */ + unsigned char pad1; /* 0xFFFC0003 */ + unsigned long ipaddr; /* 0xFFFC0004 */ + unsigned long netmask; /* 0xFFFC0008 */ + unsigned char enaddr[6]; /* 0xFFFC000C */ + unsigned short processor_id; /* 0xFFFC0012 */ + unsigned long rma_start; /* 0xFFFC0014 */ + unsigned long vma_start; /* 0xFFFC0018 */ + unsigned long ramsize; /* 0xFFFC001C */ +} nvram_config; + +/* + * Pointer to the base of User Area NVRAM + */ + +#define nvram ((nvram_config * const) 0xFFFC0000) + +#endif + +/* + * Flag to indicate if J1-4 is on (and parameters should be + * sought in User Area NVRAM) + * + * NOTE: If NVRAM has bad settings, the you want to disable this + * on the MVME167. + */ +#if defined(mvme167) + #define NVRAM_CONFIGURE \ + ( !( ( (unsigned char)(lcsr->vector_base & 0xFF) ) & 0x10 ) ) +#else + #define NVRAM_CONFIGURE 0 +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mcf5206elite/headers.am b/bsps/m68k/mcf5206elite/headers.am new file mode 100644 index 0000000000..1faf6942f8 --- /dev/null +++ b/bsps/m68k/mcf5206elite/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/ds1307.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/i2c.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/i2cdrv.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/nvram.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/tm27.h diff --git a/bsps/m68k/mcf5206elite/include/bsp.h b/bsps/m68k/mcf5206elite/include/bsp.h new file mode 100644 index 0000000000..47c7e8c745 --- /dev/null +++ b/bsps/m68k/mcf5206elite/include/bsp.h @@ -0,0 +1,181 @@ +/* + * Board Support Package for MCF5206eLITE evaluation board + * BSP definitions + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_MCF5206ELITE_BSP_H +#define LIBBSP_M68K_MCF5206ELITE_BSP_H + +#include "mcf5206/mcf5206e.h" + +/*** Board resources allocation ***/ + +/* + * To achieve some compatibility with dBUG monitor, we use the same + * memory resources allocation as it is used in dBUG. + * + * If this definitions will be changed, change the linker script also. + */ + +/* Memory mapping */ +/* CS0: Boot Flash */ +#define BSP_MEM_ADDR_FLASH (0xFFE00000) +#define BSP_MEM_SIZE_FLASH (1*1024*1024) +#define BSP_MEM_MASK_FLASH (MCF5206E_CSMR_MASK_1M) + +/* CS2: External SRAM */ +#define BSP_MEM_ADDR_ESRAM (0x30000000) +#define BSP_MEM_SIZE_ESRAM (1*1024*1024) +#define BSP_MEM_MASK_ESRAM (MCF5206E_CSMR_MASK_1M) + +/* CS3: General-Purpose I/O register */ +#define BSP_MEM_ADDR_GPIO (0x40000000) +#define BSP_MEM_SIZE_GPIO (64*1024) +#define BSP_MEM_MASK_GPIO (MCF5206E_CSMR_MASK_64K) + +/* DRAM0: Dynamic RAM */ +#define BSP_MEM_ADDR_DRAM (0x00000000) +#define BSP_MEM_SIZE_DRAM (16*1024*1024) +#define BSP_MEM_MASK_DRAM (MCF5206E_DCMR_MASK_16M) + +/* On-chip SRAM */ +#define BSP_MEM_ADDR_SRAM (0x20000000) +#define BSP_MEM_SIZE_SRAM (8*1024) + +/* On-chip peripherial registers */ +#define BSP_MEM_ADDR_IMM (0x10000000) +#define BSP_MEM_SIZE_IMM (1*1024) +#define MBAR BSP_MEM_ADDR_IMM + +/* Interrupt vector assignment */ +#define BSP_INTVEC_AVEC1 (25) +#define BSP_INTLVL_AVEC1 (1) +#define BSP_INTPRIO_AVEC1 (3) + +#define BSP_INTVEC_AVEC2 (26) +#define BSP_INTLVL_AVEC2 (2) +#define BSP_INTPRIO_AVEC2 (3) + +#define BSP_INTVEC_AVEC3 (27) +#define BSP_INTLVL_AVEC3 (3) +#define BSP_INTPRIO_AVEC3 (3) + +#define BSP_INTVEC_AVEC4 (28) +#define BSP_INTLVL_AVEC4 (4) +#define BSP_INTPRIO_AVEC4 (3) + +#define BSP_INTVEC_AVEC5 (29) +#define BSP_INTLVL_AVEC5 (5) +#define BSP_INTPRIO_AVEC5 (3) + +#define BSP_INTVEC_AVEC6 (30) +#define BSP_INTLVL_AVEC6 (6) +#define BSP_INTPRIO_AVEC6 (3) + +#define BSP_INTVEC_AVEC7 (31) +#define BSP_INTLVL_AVEC7 (7) +#define BSP_INTPRIO_AVEC7 (3) + +#define BSP_INTVEC_TIMER1 (BSP_INTVEC_AVEC5) +#define BSP_INTLVL_TIMER1 (BSP_INTLVL_AVEC5) +#define BSP_INTPRIO_TIMER1 (2) + +#define BSP_INTVEC_TIMER2 (BSP_INTVEC_AVEC6) +#define BSP_INTLVL_TIMER2 (BSP_INTLVL_AVEC6) +#define BSP_INTPRIO_TIMER2 (2) + +#define BSP_INTVEC_MBUS (BSP_INTVEC_AVEC4) +#define BSP_INTLVL_MBUS (BSP_INTLVL_AVEC4) +#define BSP_INTPRIO_MBUS (2) + +#define BSP_INTVEC_UART1 (64) +#define BSP_INTLVL_UART1 (4) +#define BSP_INTPRIO_UART1 (0) + +#define BSP_INTVEC_UART2 (65) +#define BSP_INTLVL_UART2 (4) +#define BSP_INTPRIO_UART2 (1) + +#define BSP_INTVEC_DMA0 (66) +#define BSP_INTLVL_DMA0 (3) +#define BSP_INTPRIO_DMA0 (1) + +#define BSP_INTVEC_DMA1 (67) +#define BSP_INTLVL_DMA1 (3) +#define BSP_INTPRIO_DMA1 (2) + +/* Location of DS1307 Real-Time Clock/NVRAM chip */ +#define DS1307_I2C_BUS_NUMBER (0) + +#ifndef ASM + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* System frequency */ +#define BSP_SYSTEM_FREQUENCY ((unsigned int)&_SYS_CLOCK_FREQUENCY) +extern char _SYS_CLOCK_FREQUENCY; /* Don't use this variable directly!!! */ + +/* MBUS I2C bus clock default frequency */ +#define BSP_MBUS_FREQUENCY (16000) + +/* Number of I2C buses supported in this board */ +#define I2C_NUMBER_OF_BUSES (1) + +/* I2C bus selection */ +#define I2C_SELECT_BUS(bus) + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#define rtems_bsp_delay( microseconds ) \ + { register uint32_t _delay=(microseconds); \ + register uint32_t _tmp=123; \ + __asm__ volatile( "0: \ + nbcd %0 ; \ + nbcd %0 ; \ + dbf %1,0b" \ + : "=d" (_tmp), "=d" (_delay) \ + : "0" (_tmp), "1" (_delay) ); \ + } + + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +extern rtems_isr (*rtems_clock_hook)(rtems_vector_number); + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Prototypes for BSP methods that cross file boundaries + */ +void Init5206e(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif diff --git a/bsps/m68k/mcf5206elite/include/ds1307.h b/bsps/m68k/mcf5206elite/include/ds1307.h new file mode 100644 index 0000000000..8e5636a0c8 --- /dev/null +++ b/bsps/m68k/mcf5206elite/include/ds1307.h @@ -0,0 +1,41 @@ +/* + * This file contains the definitions for Dallas Semiconductor + * DS1307/DS1308 serial real-time clock/NVRAM. + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __RTC_DS1307__ +#define __RTC_DS1307__ + +#define DS1307_I2C_ADDRESS (0xD0) /* I2C bus address assigned to DS1307 */ + +#define DS1307_SECOND (0x00) +#define DS1307_SECOND_HALT (0x80) /* High bit is a Clock Halt bit */ +#define DS1307_MINUTE (0x01) +#define DS1307_HOUR (0x02) +#define DS1307_HOUR_12 (0x40) /* 12-hour mode */ +#define DS1307_HOUR_PM (0x20) /* PM in 12-hour mode */ +#define DS1307_DAY_OF_WEEK (0x03) +#define DS1307_DAY (0x04) +#define DS1307_MONTH (0x05) +#define DS1307_YEAR (0x06) +#define DS1307_CONTROL (0x07) +#define DS1307_CONTROL_OUT (0x80) /* Output control */ +#define DS1307_CONTROL_SQWE (0x10) /* Sqware Wave Enable */ +#define DS1307_CONTROL_RS_1 (0x00) /* Rate select: 1 Hz */ +#define DS1307_CONTROL_RS_4096 (0x01) /* Rate select: 4096 Hz */ +#define DS1307_CONTROL_RS_8192 (0x02) /* Rate select: 8192 Hz */ +#define DS1307_CONTROL_RS_32768 (0x03) /* Rate select; 32768 Hz */ + +#define DS1307_NVRAM_START (0x08) /* Start location of non-volatile memory */ +#define DS1307_NVRAM_END (0x3F) /* End location of non-volatile memory */ +#define DS1307_NVRAM_SIZE (56) /* Size of non-volatile memory */ + +#endif __RTC_DS1307__ diff --git a/bsps/m68k/mcf5206elite/include/i2c.h b/bsps/m68k/mcf5206elite/include/i2c.h new file mode 100644 index 0000000000..8bec067a3a --- /dev/null +++ b/bsps/m68k/mcf5206elite/include/i2c.h @@ -0,0 +1,243 @@ +/* + * Generic I2C bus interface for RTEMS + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __RTEMS__I2C_H__ +#define __RTEMS__I2C_H__ + +#include +#include +/* This header file define the generic interface to i2c buses available in + * system. This interface may be used by user applications or i2c-device + * drivers (like RTC, NVRAM, etc). + * + * Functions i2c_initialize and i2c_transfer declared in this header usually + * implemented in particular board support package. Usually this + * implementation is a simple wrapper or multiplexor to I2C controller + * driver which is available in system. It may be generic "software + * controller" I2C driver which control SDA and SCL signals directly (if SDA + * and SCL is general-purpose I/O pins), or driver for hardware I2C + * controller (standalone or integrated with processors: MBus controller in + * ColdFire processors, I2C controller in PowerQUICC and so on). + * + * i2c_transfer is a very generic low-level function. Higher-level function + * i2c_write, i2c_read, i2c_wrrd, i2c_wbrd is defined here too. + */ + +/* I2C Bus Number type */ +typedef uint32_t i2c_bus_number; + +/* I2C device address */ +typedef uint16_t i2c_address; + +/* I2C error codes generated during message transfer */ +typedef enum i2c_message_status { + I2C_SUCCESSFUL = 0, + I2C_TIMEOUT, + I2C_NO_DEVICE, + I2C_ARBITRATION_LOST, + I2C_NO_ACKNOWLEDGE, + I2C_NO_DATA, + I2C_RESOURCE_NOT_AVAILABLE +} i2c_message_status; + +/* I2C Message */ +typedef struct i2c_message { + i2c_address addr; /* I2C slave device address */ + uint16_t flags; /* message flags (see below) */ + i2c_message_status status; /* message transfer status code */ + uint16_t len; /* Number of bytes to read or write */ + uint8_t *buf; /* pointer to data array */ +} i2c_message; + +/* I2C message flag */ +#define I2C_MSG_ADDR_10 (0x01) /* 10-bit address */ +#define I2C_MSG_WR (0x02) /* transfer direction for this message + from master to slave */ +#define I2C_MSG_ERRSKIP (0x04) /* Skip message if last transfered message + is failed */ +/* Type for function which is called when transfer over I2C bus is finished */ +typedef void (*i2c_transfer_done) (void *arg); + +/* i2c_initialize -- + * I2C driver initialization. This function usually called on device + * driver initialization state, before initialization task. All I2C + * buses are initialized; reasonable slow data transfer rate is + * selected for each bus. + * + * PARAMETERS: + * major - I2C device major number + * minor - I2C device minor number + * arg - RTEMS driver initialization argument + * + * RETURNS: + * RTEMS status code + */ +rtems_device_driver +i2c_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* i2c_select_clock_rate -- + * select I2C bus clock rate for specified bus. Some bus controller do not + * allow to select arbitrary clock rate; in this case nearest possible + * slower clock rate is selected. + * + * PARAMETERS: + * bus - I2C bus number + * bps - data transfer rate for this bytes in bits per second + * + * RETURNS: + * RTEMS_SUCCESSFUL, if operation performed successfully, + * RTEMS_INVALID_NUMBER, if wrong bus number is specified, + * RTEMS_UNSATISFIED, if bus do not support data transfer rate selection + * or specified data transfer rate could not be used. + */ +rtems_status_code +i2c_select_clock_rate(i2c_bus_number bus, int bps); + +/* i2c_transfer -- + * Initiate multiple-messages transfer over specified I2C bus or + * put request into queue if bus or some other resource is busy. (This + * is non-blocking function). + * + * PARAMETERS: + * bus - I2C bus number + * nmsg - number of messages + * msg - pointer to messages array + * done - function which is called when transfer is finished + * done_arg_ptr - arbitrary argument ptr passed to done funciton + * + * RETURNS: + * RTEMS_SUCCESSFUL if transfer initiated successfully, or error + * code if something failed. + */ +rtems_status_code +i2c_transfer(i2c_bus_number bus, int nmsg, i2c_message *msg, + i2c_transfer_done done, void * done_arg_ptr); + +/* i2c_transfer_wait -- + * Initiate I2C bus transfer and block until this transfer will be + * finished. This function wait the semaphore if system in + * SYSTEM_STATE_UP state, or poll done flag in other states. + * + * PARAMETERS: + * bus - I2C bus number + * msg - pointer to transfer messages array + * nmsg - number of messages in transfer + * + * RETURNS: + * I2C_SUCCESSFUL, if transfer finished successfully, + * I2C_RESOURCE_NOT_AVAILABLE, if semaphore operations has failed, + * value of status field of first error-finished message in transfer, + * if something wrong. + */ +i2c_message_status +i2c_transfer_wait(i2c_bus_number bus, i2c_message *msg, int nmsg); + +/* i2c_poll -- + * Poll I2C bus controller for events and hanle it. This function is + * used when I2C driver operates in poll-driven mode. + * + * PARAMETERS: + * bus - bus number to be polled + * + * RETURNS: + * none + */ +void +i2c_poll(i2c_bus_number bus); + +/* i2c_write -- + * Send single message over specified I2C bus to addressed device and + * wait while transfer is finished. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * buf - data to be sent to device + * size - data buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_write(i2c_bus_number bus, i2c_address addr, void *buf, int size); + +/* i2c_wrbyte -- + * Send single one-byte long message over specified I2C bus to + * addressed device and wait while transfer is finished. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * cmd - byte message to be sent to device + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_wrbyte(i2c_bus_number bus, i2c_address addr, uint8_t cmd); + +/* i2c_read -- + * receive single message over specified I2C bus from addressed device. + * This call will wait while transfer is finished. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * buf - buffer for received message + * size - receive buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_read(i2c_bus_number bus, i2c_address addr, void *buf, int size); + +/* i2c_wrrd -- + * Send message over I2C bus to specified device and receive message + * from the same device during single transfer. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * bufw - data to be sent to device + * sizew - send data buffer size + * bufr - buffer for received message + * sizer - receive buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_wrrd(i2c_bus_number bus, i2c_address addr, void *bufw, int sizew, + void *bufr, int sizer); + +/* i2c_wbrd -- + * Send one-byte message over I2C bus to specified device and receive + * message from the same device during single transfer. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * cmd - one-byte message to be sent over I2C bus + * bufr - buffer for received message + * sizer - receive buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_wbrd(i2c_bus_number bus, i2c_address addr, uint8_t cmd, + void *bufr, int sizer); + +#endif diff --git a/bsps/m68k/mcf5206elite/include/i2cdrv.h b/bsps/m68k/mcf5206elite/include/i2cdrv.h new file mode 100644 index 0000000000..4b4a1ec141 --- /dev/null +++ b/bsps/m68k/mcf5206elite/include/i2cdrv.h @@ -0,0 +1,35 @@ +/* + * i2cdrv.h -- I2C bus driver prototype and definitions + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __I2CDRV_H__ +#define __I2CDRV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2C_DRIVER_TABLE_ENTRY \ + { i2cdrv_initialize, NULL, NULL, NULL, NULL, NULL } + +/* i2cdrv_initialize -- + * I2C driver initialization (rtems I/O driver primitive) + */ +rtems_device_driver +i2cdrv_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __I2CDRV_H__ */ diff --git a/bsps/m68k/mcf5206elite/include/nvram.h b/bsps/m68k/mcf5206elite/include/nvram.h new file mode 100644 index 0000000000..fd75db2363 --- /dev/null +++ b/bsps/m68k/mcf5206elite/include/nvram.h @@ -0,0 +1,71 @@ +/* + * nvram.h -- DS1307-based non-volatile memory device driver. + * + * This driver support file-like operations to 56-bytes long non-volatile + * memory of DS1307 I2C real-time clock chip. + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __DRIVER__NVRAM_H__ +#define __DRIVER__NVRAM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVRAM_DRIVER_TABLE_ENTRY \ + { nvram_driver_initialize, nvram_driver_open, nvram_driver_close, \ + nvram_driver_read, nvram_driver_write, NULL } + +/* nvram_driver_initialize -- + * Non-volatile memory device driver initialization. + */ +rtems_device_driver +nvram_driver_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_open -- + * Non-volatile memory device driver open primitive. + */ +rtems_device_driver +nvram_driver_open(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_close -- + * Non-volatile memory device driver close primitive. + */ +rtems_device_driver +nvram_driver_close(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_read -- + * Non-volatile memory device driver read primitive. + */ +rtems_device_driver +nvram_driver_read(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_write -- + * Non-volatile memory device driver write primitive. + */ +rtems_device_driver +nvram_driver_write(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __VFDDRV_H__ */ diff --git a/bsps/m68k/mcf5206elite/include/tm27.h b/bsps/m68k/mcf5206elite/include/tm27.h new file mode 100644 index 0000000000..2abef68311 --- /dev/null +++ b/bsps/m68k/mcf5206elite/include/tm27.h @@ -0,0 +1,35 @@ +/* + * @file + * @ingroup m68k_mcf5206elite + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 34, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #2"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mcf52235/headers.am b/bsps/m68k/mcf52235/headers.am new file mode 100644 index 0000000000..b536b21164 --- /dev/null +++ b/bsps/m68k/mcf52235/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mcf52235/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mcf52235/include/tm27.h diff --git a/bsps/m68k/mcf52235/include/bsp.h b/bsps/m68k/mcf52235/include/bsp.h new file mode 100644 index 0000000000..ef3b928a24 --- /dev/null +++ b/bsps/m68k/mcf52235/include/bsp.h @@ -0,0 +1,87 @@ +/** + * @file + * + * @ingroup m68k_mcf52235 + * + * @brief Global BSP definitions + */ + +/* + * mcf52235 BSP header file + */ + +#ifndef LIBBSP_M68K_MCF52235_BSP_H +#define LIBBSP_M68K_MCF52235_BSP_H + +#include +#include +#include +#include + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Declare base address of peripherals area */ +#define __IPSBAR ((vuint8 *) 0x40000000) + +/***************************************************************************/ +/** Network driver configuration **/ + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* externals */ + +/* constants */ + +/* functions */ + +uint32_t bsp_get_CPU_clock_speed(void); + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ + +#define PIT3_IRQ_LEVEL 4 +#define PIT3_IRQ_PRIORITY 0 + +#define UART0_IRQ_LEVEL 3 +#define UART0_IRQ_PRIORITY 7 +#define UART1_IRQ_LEVEL 3 +#define UART1_IRQ_PRIORITY 6 +#define UART2_IRQ_LEVEL 3 +#define UART2_IRQ_PRIORITY 5 + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void Init52235(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/** + * @defgroup m68k_mcf52235 MCF52235 Support + * + * @ingroup bsp_m68k + * + * @brief MCF52235 Support Package + */ diff --git a/bsps/m68k/mcf52235/include/tm27.h b/bsps/m68k/mcf52235/include/tm27.h new file mode 100644 index 0000000000..b4b62ef721 --- /dev/null +++ b/bsps/m68k/mcf52235/include/tm27.h @@ -0,0 +1,35 @@ +/* + * @file + * @ingroup m68k_mcf52235 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mcf5225x/headers.am b/bsps/m68k/mcf5225x/headers.am new file mode 100644 index 0000000000..200bebf9b5 --- /dev/null +++ b/bsps/m68k/mcf5225x/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mcf5225x/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5225x/include/tm27.h diff --git a/bsps/m68k/mcf5225x/include/bsp.h b/bsps/m68k/mcf5225x/include/bsp.h new file mode 100644 index 0000000000..8b8d40f485 --- /dev/null +++ b/bsps/m68k/mcf5225x/include/bsp.h @@ -0,0 +1,90 @@ +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_MCF5225X_BSP_H +#define LIBBSP_M68K_MCF5225X_BSP_H + +#include +#include +#include +#include + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Declare base address of peripherals area */ +#define __IPSBAR ((vuint8 *) 0x40000000) + +/***************************************************************************/ +/** Network driver configuration **/ + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define ports for console and DPU specific for BLUETOOTH and STATIONS */ +#define STATIONS_PORT 0 +#define CONSOLE_PORT 1 +#define BLUETOOTH_PORT 2 + +/* externals */ + +/* constants */ + +/* miscellaneous stuff assumed to exist */ + +/* + * Device Driver Table Entries + */ + +/* + * NOTE: Use the standard Console driver entry + */ + +/* + * NOTE: Use the standard Clock driver entry + */ + + +/* functions */ + +uint32_t bsp_get_CPU_clock_speed(void); + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ + +#define PIT3_IRQ_LEVEL 4 +#define PIT3_IRQ_PRIORITY 0 + +#define UART0_IRQ_LEVEL 3 +#define UART0_IRQ_PRIORITY 7 +#define UART1_IRQ_LEVEL 3 +#define UART1_IRQ_PRIORITY 6 +#define UART2_IRQ_LEVEL 3 +#define UART2_IRQ_PRIORITY 5 + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void Init5225x(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mcf5225x/include/tm27.h b/bsps/m68k/mcf5225x/include/tm27.h new file mode 100644 index 0000000000..fcf1c4f8aa --- /dev/null +++ b/bsps/m68k/mcf5225x/include/tm27.h @@ -0,0 +1,35 @@ +/* + * @file + * @ingroup m68k_mcf5225x + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mcf5235/headers.am b/bsps/m68k/mcf5235/headers.am new file mode 100644 index 0000000000..e00b25f46c --- /dev/null +++ b/bsps/m68k/mcf5235/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mcf5235/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5235/include/tm27.h diff --git a/bsps/m68k/mcf5235/include/bsp.h b/bsps/m68k/mcf5235/include/bsp.h new file mode 100644 index 0000000000..14a6b04034 --- /dev/null +++ b/bsps/m68k/mcf5235/include/bsp.h @@ -0,0 +1,70 @@ +/* + * mcf5235 BSP header file + */ + +#ifndef LIBBSP_M68K_MCF5235_BSP_H +#define LIBBSP_M68K_MCF5235_BSP_H + +#include +#include +#include +#include + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include /* internal MCF5235 modules */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ +/** Network driver configuration **/ +struct rtems_bsdnet_ifconfig; +extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "fec0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* functions */ + +uint32_t get_CPU_clock_speed(void); +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ +#define FEC_IRQ_LEVEL 4 +#define FEC_IRQ_RX_PRIORITY 7 +#define FEC_IRQ_TX_PRIORITY 6 + +#define PIT3_IRQ_LEVEL 4 +#define PIT3_IRQ_PRIORITY 0 + +#define UART0_IRQ_LEVEL 3 +#define UART0_IRQ_PRIORITY 7 +#define UART1_IRQ_LEVEL 3 +#define UART1_IRQ_PRIORITY 6 +#define UART2_IRQ_LEVEL 3 +#define UART2_IRQ_PRIORITY 5 + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void Init5235(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mcf5235/include/tm27.h b/bsps/m68k/mcf5235/include/tm27.h new file mode 100644 index 0000000000..92a85c789a --- /dev/null +++ b/bsps/m68k/mcf5235/include/tm27.h @@ -0,0 +1,35 @@ +/* + * @file + * @ingroup m68k_mcf5235 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mcf5329/headers.am b/bsps/m68k/mcf5329/headers.am new file mode 100644 index 0000000000..c1ee57ae55 --- /dev/null +++ b/bsps/m68k/mcf5329/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mcf5329/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5329/include/tm27.h diff --git a/bsps/m68k/mcf5329/include/bsp.h b/bsps/m68k/mcf5329/include/bsp.h new file mode 100644 index 0000000000..7670e7a2d9 --- /dev/null +++ b/bsps/m68k/mcf5329/include/bsp.h @@ -0,0 +1,70 @@ +/* + * mcf52235 BSP header file + */ + +#ifndef LIBBSP_M68K_MCF5329_BSP_H +#define LIBBSP_M68K_MCF5329_BSP_H + +#include +#include +#include +#include + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile unsigned char vuint8; +typedef volatile unsigned short vuint16; +typedef volatile unsigned long vuint32; + +/***************************************************************************/ +/** Network driver configuration **/ +struct rtems_bsdnet_ifconfig; +extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "fec0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* functions */ + +uint32_t bsp_get_CPU_clock_speed(void); +uint32_t bsp_get_BUS_clock_speed(void); + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ +#define FEC_IRQ_LEVEL 4 + +#define PIT3_IRQ_LEVEL 4 + +#define UART0_IRQ_LEVEL 3 +#define UART1_IRQ_LEVEL 3 +#define UART2_IRQ_LEVEL 3 + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void Init5329(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mcf5329/include/tm27.h b/bsps/m68k/mcf5329/include/tm27.h new file mode 100644 index 0000000000..33376540ac --- /dev/null +++ b/bsps/m68k/mcf5329/include/tm27.h @@ -0,0 +1,35 @@ +/* + * @file + * @ingroup m68k_mcf5329 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mrm332/headers.am b/bsps/m68k/mrm332/headers.am new file mode 100644 index 0000000000..84ad4ec522 --- /dev/null +++ b/bsps/m68k/mrm332/headers.am @@ -0,0 +1,7 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mrm332/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mrm332/include/mrm332.h +include_HEADERS += ../../../../../../bsps/m68k/mrm332/include/tm27.h diff --git a/bsps/m68k/mrm332/include/bsp.h b/bsps/m68k/mrm332/include/bsp.h new file mode 100644 index 0000000000..6d4f7b8eb2 --- /dev/null +++ b/bsps/m68k/mrm332/include/bsp.h @@ -0,0 +1,90 @@ +/* bsp.h + * + * This include file contains all mrm board IO definitions. + */ + +/* + * COPYRIGHT (c) 1989-2009. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_MRM332_BSP_H +#define LIBBSP_M68K_MRM332_BSP_H + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define CONSOLE_SCI + +/* externals */ + +extern char _etext[]; +extern char _copy_start[]; +extern char _edata[]; +extern char _clear_start[]; +extern char end[]; +extern bool _copy_data_from_rom; + +/* constants */ + +#ifdef __START_C__ +#define STACK_SIZE "#0x800" +#else +#define STACK_SIZE 0x800 +#endif + +/* macros */ + +#define RAW_PUTS(str) \ + { register char *ptr = str; \ + while (*ptr) SCI_output_char(*ptr++); \ + } + +#define RAW_PUTI(n) { \ + register int i, j; \ + \ + RAW_PUTS("0x"); \ + for (i=28;i>=0;i -= 4) { \ + j = (n>>i) & 0xf; \ + SCI_output_char( (j>9 ? j-10+'a' : j+'0') ); \ + } \ + } + +/* miscellaneous stuff assumed to exist */ + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +extern int stack_size; +extern int stack_start; + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +void Spurious_Initialize(void); + +void _UART_flush(void); + +void outbyte(char); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mrm332/include/mrm332.h b/bsps/m68k/mrm332/include/mrm332.h new file mode 100644 index 0000000000..1b8672752d --- /dev/null +++ b/bsps/m68k/mrm332/include/mrm332.h @@ -0,0 +1,71 @@ +/* mrm332.h + */ + +#ifndef _MRM332_H_ +#define _MRM332_H_ + +/* SIM_MM (SIM Module Mapping) determines the location of the control + register block. When MM=0, register addresses range fom 0x7ff000 to + 0x7FFFFF. When MM=1, register addresses range from 0xfff000 to + 0xffffff. */ +#define SIM_MM 1 + +/* Interrupt related definitions */ +#define SIM_IARB 15 +#define QSM_IARB 10 + +#define MRM_PIV 64 +#define ISRL_PIT 4 /* zero disables PIT */ + +#define EFI_QIVR 66 /* 66=>SCI and 67=>QSPI interrupt */ +#define ISRL_QSPI 0 + +#define EFI_SPINT 24 /* spurious interrupt */ +#define EFI_INT1 25 /* CTS interrupt */ +#define ISRL_SCI 6 + +/* System Clock definitions */ +#define XTAL 32768.0 /* crystal frequency in Hz */ + +/* Specify the CPU frequency. Do not specify a faster clock than your */ +/* CPU is rated for! */ +#if 0 +/* Default MRM clock rate (8.388688 MHz) set by CPU32: */ +#define MRM_W 0 /* system clock parameters */ +#define MRM_X 0 +#define MRM_Y 0x3f +#endif + +#if 0 +/* 16.77722 MHz: */ +#define MRM_W 1 /* system clock parameters */ +#define MRM_X 1 +#define MRM_Y 0x0f +#endif + +#if 1 +/* 25.16582 MHz: */ +#define MRM_W 1 /* system clock parameters */ +#define MRM_X 1 +#define MRM_Y 0x17 +#define SET_EDIV +#endif + +#define SYS_CLOCK (XTAL*4.0*(MRM_Y+1)*(1 << (2*MRM_W+MRM_X))) +#define SCI_BAUD 19200 /* RS232 Baud Rate */ + +/* macros/functions */ + +#ifndef ASM + +/* + * This prototype really should have the noreturn attribute but + * that causes a warning. Not sure how to fix that. + */ +/* static void reboot(void) __attribute__ ((noreturn)); */ +static void reboot(void); +__inline__ static void reboot() {__asm__ ("trap #15; .word 0x0063");} + +#endif /* ASM */ + +#endif /* _MRM_H_ */ diff --git a/bsps/m68k/mrm332/include/tm27.h b/bsps/m68k/mrm332/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/m68k/mrm332/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/m68k/mvme147/headers.am b/bsps/m68k/mvme147/headers.am new file mode 100644 index 0000000000..c6b61dd0e1 --- /dev/null +++ b/bsps/m68k/mvme147/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mvme147/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mvme147/include/tm27.h diff --git a/bsps/m68k/mvme147/include/bsp.h b/bsps/m68k/mvme147/include/bsp.h new file mode 100644 index 0000000000..9cf3fbf5a8 --- /dev/null +++ b/bsps/m68k/mvme147/include/bsp.h @@ -0,0 +1,117 @@ +/* bsp.h + * + * This include file contains all MVME147 board IO definitions. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * MVME147 port for TNI - Telecom Bretagne + * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) + * May 1996 + */ + +#ifndef LIBBSP_M68K_MVME147_BSP_H +#define LIBBSP_M68K_MVME147_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Constants */ + +#define RAM_START 0x00005000 +#define RAM_END 0x00400000 + + /* MVME 147 Peripheral controller chip + see MVME147/D1, 3.4 */ + +struct pcc_map { + /* 32 bit registers */ + uint32_t dma_table_address; /* 0xfffe1000 */ + uint32_t dma_data_address; /* 0xfffe1004 */ + uint32_t dma_bytecount; /* 0xfffe1008 */ + uint32_t dma_data_holding; /* 0xfffe100c */ + + /* 16 bit registers */ + uint16_t timer1_preload; /* 0xfffe1010 */ + uint16_t timer1_count; /* 0xfffe1012 */ + uint16_t timer2_preload; /* 0xfffe1014 */ + uint16_t timer2_count; /* 0xfffe1016 */ + + /* 8 bit registers */ + uint8_t timer1_int_control; /* 0xfffe1018 */ + uint8_t timer1_control; /* 0xfffe1019 */ + uint8_t timer2_int_control; /* 0xfffe101a */ + uint8_t timer2_control; /* 0xfffe101b */ + + uint8_t acfail_int_control; /* 0xfffe101c */ + uint8_t watchdog_control; /* 0xfffe101d */ + + uint8_t printer_int_control; /* 0xfffe101e */ + uint8_t printer_control; /* 0xfffe102f */ + + uint8_t dma_int_control; /* 0xfffe1020 */ + uint8_t dma_control; /* 0xfffe1021 */ + uint8_t bus_error_int_control; /* 0xfffe1022 */ + uint8_t dma_status; /* 0xfffe1023 */ + uint8_t abort_int_control; /* 0xfffe1024 */ + uint8_t table_address_function_code; /* 0xfffe1025 */ + uint8_t serial_port_int_control; /* 0xfffe1026 */ + uint8_t general_purpose_control; /* 0xfffe1027 */ + uint8_t lan_int_control; /* 0xfffe1028 */ + uint8_t general_purpose_status; /* 0xfffe1029 */ + uint8_t scsi_port_int_control; /* 0xfffe102a */ + uint8_t slave_base_address; /* 0xfffe102b */ + uint8_t software_int_1_control; /* 0xfffe102c */ + uint8_t int_base_vector; /* 0xfffe102d */ + uint8_t software_int_2_control; /* 0xfffe102e */ + uint8_t revision_level; /* 0xfffe102f */ +}; + +#define pcc ((volatile struct pcc_map * const) 0xfffe1000) + +#define z8530 0xfffe3001 + +/* interrupt vectors - see MVME146/D1 4.14 */ +#define PCC_BASE_VECTOR 0x40 /* First user int */ +#define SCC_VECTOR PCC_BASE_VECTOR+3 +#define TIMER_1_VECTOR PCC_BASE_VECTOR+8 +#define TIMER_2_VECTOR PCC_BASE_VECTOR+9 +#define SOFT_1_VECTOR PCC_BASE_VECTOR+10 +#define SOFT_2_VECTOR PCC_BASE_VECTOR+11 + +#define USE_CHANNEL_A 1 /* 1 = use channel A for console */ +#define USE_CHANNEL_B 0 /* 1 = use channel B for console */ + +#if (USE_CHANNEL_A == 1) +#define CONSOLE_CONTROL 0xfffe3002 +#define CONSOLE_DATA 0xfffe3003 +#elif (USE_CHANNEL_B == 1) +#define CONSOLE_CONTROL 0xfffe3000 +#define CONSOLE_DATA 0xfffe3001 +#endif + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mvme147/include/tm27.h b/bsps/m68k/mvme147/include/tm27.h new file mode 100644 index 0000000000..5b548a888a --- /dev/null +++ b/bsps/m68k/mvme147/include/tm27.h @@ -0,0 +1,38 @@ +/* + * @file + * @ingroup m68k_mvme147 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: Use the MPCSR vector for the MVME147 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), \ + SOFT_1_VECTOR, 1 ) + +#define Cause_tm27_intr() pcc->software_int_1_control = 0x0c + /* generate level 4 sotware int. */ + +#define Clear_tm27_intr() pcc->software_int_1_control = 0x00 + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mvme147s/headers.am b/bsps/m68k/mvme147s/headers.am new file mode 100644 index 0000000000..d42fd64a42 --- /dev/null +++ b/bsps/m68k/mvme147s/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mvme147s/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mvme147s/include/tm27.h diff --git a/bsps/m68k/mvme147s/include/bsp.h b/bsps/m68k/mvme147s/include/bsp.h new file mode 100644 index 0000000000..3a4803fec2 --- /dev/null +++ b/bsps/m68k/mvme147s/include/bsp.h @@ -0,0 +1,192 @@ +/* bsp.h + * + * This include file contains all MVME147 board IO definitions. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * MVME147 port for TNI - Telecom Bretagne + * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) + * May 1996 + */ + +#ifndef LIBBSP_M68K_MVME147S_BSP_H +#define LIBBSP_M68K_MVME147S_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Constants */ + +#define RAM_START 0x00007000 +#define RAM_END 0x003e0000 +#define DRAM_END 0x00400000 + /* We leave 128k for the shared memory */ + + /* MVME 147 Peripheral controller chip + see MVME147/D1, 3.4 */ + +struct pcc_map { + /* 32 bit registers */ + uint32_t dma_table_address; /* 0xfffe1000 */ + uint32_t dma_data_address; /* 0xfffe1004 */ + uint32_t dma_bytecount; /* 0xfffe1008 */ + uint32_t dma_data_holding; /* 0xfffe100c */ + + /* 16 bit registers */ + uint16_t timer1_preload; /* 0xfffe1010 */ + uint16_t timer1_count; /* 0xfffe1012 */ + uint16_t timer2_preload; /* 0xfffe1014 */ + uint16_t timer2_count; /* 0xfffe1016 */ + + /* 8 bit registers */ + uint8_t timer1_int_control; /* 0xfffe1018 */ + uint8_t timer1_control; /* 0xfffe1019 */ + uint8_t timer2_int_control; /* 0xfffe101a */ + uint8_t timer2_control; /* 0xfffe101b */ + + uint8_t acfail_int_control; /* 0xfffe101c */ + uint8_t watchdog_control; /* 0xfffe101d */ + + uint8_t printer_int_control; /* 0xfffe101e */ + uint8_t printer_control; /* 0xfffe102f */ + + uint8_t dma_int_control; /* 0xfffe1020 */ + uint8_t dma_control; /* 0xfffe1021 */ + uint8_t bus_error_int_control; /* 0xfffe1022 */ + uint8_t dma_status; /* 0xfffe1023 */ + uint8_t abort_int_control; /* 0xfffe1024 */ + uint8_t table_address_function_code; /* 0xfffe1025 */ + uint8_t serial_port_int_control; /* 0xfffe1026 */ + uint8_t general_purpose_control; /* 0xfffe1027 */ + uint8_t lan_int_control; /* 0xfffe1028 */ + uint8_t general_purpose_status; /* 0xfffe1029 */ + uint8_t scsi_port_int_control; /* 0xfffe102a */ + uint8_t slave_base_address; /* 0xfffe102b */ + uint8_t software_int_1_control; /* 0xfffe102c */ + uint8_t int_base_vector; /* 0xfffe102d */ + uint8_t software_int_2_control; /* 0xfffe102e */ + uint8_t revision_level; /* 0xfffe102f */ +}; + +#define pcc ((volatile struct pcc_map * const) 0xfffe1000) + +/* VME chip configuration registers */ + +struct vme_lcsr_map { + uint8_t unused_1; + uint8_t system_controller; /* 0xfffe2001 */ + uint8_t unused_2; + uint8_t vme_bus_requester; /* 0xfffe2003 */ + uint8_t unused_3; + uint8_t master_configuration; /* 0xfffe2005 */ + uint8_t unused_4; + uint8_t slave_configuration; /* 0xfffe2007 */ + uint8_t unused_5; + uint8_t timer_configuration; /* 0xfffe2009 */ + uint8_t unused_6; + uint8_t slave_address_modifier; /* 0xfffe200b */ + uint8_t unused_7; + uint8_t master_address_modifier; /* 0xfffe200d */ + uint8_t unused_8; + uint8_t interrupt_handler_mask; /* 0xfffe200f */ + uint8_t unused_9; + uint8_t utility_interrupt_mask; /* 0xfffe2011 */ + uint8_t unused_10; + uint8_t utility_interrupt_vector; /* 0xfffe2013 */ + uint8_t unused_11; + uint8_t interrupt_request; /* 0xfffe2015 */ + uint8_t unused_12; + uint8_t vme_bus_status_id; /* 0xfffe2017 */ + uint8_t unused_13; + uint8_t bus_error_status; /* 0xfffe2019 */ + uint8_t unused_14; + uint8_t gcsr_base_address; /* 0xfffe201b */ +}; + +#define vme_lcsr ((volatile struct vme_lcsr_map * const) 0xfffe2000) + +struct vme_gcsr_map { + uint8_t unused_1; + uint8_t global_0; /* 0xfffe2021 */ + uint8_t unused_2; + uint8_t global_1; /* 0xfffe2023 */ + uint8_t unused_3; + uint8_t board_identification; /* 0xfffe2025 */ + uint8_t unused_4; + uint8_t general_purpose_0; /* 0xfffe2027 */ + uint8_t unused_5; + uint8_t general_purpose_1; /* 0xfffe2029 */ + uint8_t unused_6; + uint8_t general_purpose_2; /* 0xfffe202b */ + uint8_t unused_7; + uint8_t general_purpose_3; /* 0xfffe202d */ + uint8_t unused_8; + uint8_t general_purpose_4; /* 0xfffe202f */ +}; + +#define vme_gcsr ((volatile struct vme_gcsr_map * const) 0xfffe2020) + +#define z8530 0xfffe3001 + +/* interrupt vectors - see MVME147/D1 4.14 */ +#define PCC_BASE_VECTOR 0x40 /* First user int */ +#define SCC_VECTOR PCC_BASE_VECTOR+3 +#define TIMER_1_VECTOR PCC_BASE_VECTOR+8 +#define TIMER_2_VECTOR PCC_BASE_VECTOR+9 +#define SOFT_1_VECTOR PCC_BASE_VECTOR+10 +#define SOFT_2_VECTOR PCC_BASE_VECTOR+11 + +#define VME_BASE_VECTOR 0x50 +#define VME_SIGLP_VECTOR VME_BASE_VECTOR+1 + +#define USE_CHANNEL_A 1 /* 1 = use channel A for console */ +#define USE_CHANNEL_B 0 /* 1 = use channel B for console */ + +#if (USE_CHANNEL_A == 1) +#define CONSOLE_CONTROL 0xfffe3002 +#define CONSOLE_DATA 0xfffe3003 +#elif (USE_CHANNEL_B == 1) +#define CONSOLE_CONTROL 0xfffe3000 +#define CONSOLE_DATA 0xfffe3001 +#endif + +#define FOREVER 1 /* infinite loop */ + +#ifdef M147_INIT +#undef EXTERN +#define EXTERN +#else +#undef EXTERN +#define EXTERN extern +#endif + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +/* + * NOTE: Use the standard Clock driver entry + */ + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mvme147s/include/tm27.h b/bsps/m68k/mvme147s/include/tm27.h new file mode 100644 index 0000000000..48ae0f459a --- /dev/null +++ b/bsps/m68k/mvme147s/include/tm27.h @@ -0,0 +1,38 @@ +/* + * @file + * @ingroup m68k_mvme147s + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: Use the MPCSR vector for the MVME147 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), \ + SOFT_1_VECTOR, 1 ) + +#define Cause_tm27_intr() pcc->software_int_1_control = 0x0c + /* generate level 4 sotware int. */ + +#define Clear_tm27_intr() pcc->software_int_1_control = 0x00 + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mvme162/headers.am b/bsps/m68k/mvme162/headers.am new file mode 100644 index 0000000000..5456150cf5 --- /dev/null +++ b/bsps/m68k/mvme162/headers.am @@ -0,0 +1,7 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mvme162/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mvme162/include/page_table.h +include_HEADERS += ../../../../../../bsps/m68k/mvme162/include/tm27.h diff --git a/bsps/m68k/mvme162/include/bsp.h b/bsps/m68k/mvme162/include/bsp.h new file mode 100644 index 0000000000..3645a31086 --- /dev/null +++ b/bsps/m68k/mvme162/include/bsp.h @@ -0,0 +1,204 @@ +/* + * This include file contains all MVME162fx board IO definitions. + */ + +/* + * COPYRIGHT (c) 1989-2014. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. + * EISCAT Scientific Association. M.Savitski + * + * This material is a part of the MVME162 Board Support Package + * for the RTEMS executive. Its licensing policies are those of the + * RTEMS above. + */ + +#ifndef LIBBSP_M68K_MVME162_BSP_H +#define LIBBSP_M68K_MVME162_BSP_H + +#include +#include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------------*/ + +typedef volatile struct { + + unsigned char chipID; + unsigned char chipREV; + unsigned char gen_control; + unsigned char vector_base; + + unsigned long timer_cmp_1; + unsigned long timer_cnt_1; + unsigned long timer_cmp_2; + unsigned long timer_cnt_2; + + unsigned char LSB_prescaler_count; + unsigned char prescaler_clock_adjust; + unsigned char time_ctl_2; + unsigned char time_ctl_1; + + unsigned char time_int_ctl_4; + unsigned char time_int_ctl_3; + unsigned char time_int_ctl_2; + unsigned char time_int_ctl_1; + + unsigned char dram_err_int_ctl; + unsigned char SCC_int_ctl; + unsigned char time_ctl_4; + unsigned char time_ctl_3; + + unsigned short DRAM_space_base; + unsigned short SRAM_space_base; + + unsigned char DRAM_size; + unsigned char DRAM_SRAM_opt; + unsigned char SRAM_size; + unsigned char reserved; + + unsigned char LANC_error; + unsigned char reserved1; + unsigned char LANC_int_ctl; + unsigned char LANC_berr_ctl; + + unsigned char SCSI_error; + unsigned char general_inputs; + unsigned char MVME_162_version; + unsigned char SCSI_int_ctl; + + unsigned long timer_cmp_3; + unsigned long timer_cnt_3; + unsigned long timer_cmp_4; + unsigned long timer_cnt_4; + + unsigned char bus_clk; + unsigned char PROM_acc_time_ctl; + unsigned char FLASH_acc_time_ctl; + unsigned char ABORT_int_ctl; + + unsigned char RESET_ctl; + unsigned char watchdog_timer_ctl; + unsigned char acc_watchdog_time_base_sel; + unsigned char reserved2; + + unsigned char DRAM_ctl; + unsigned char reserved4; + unsigned char MPU_status; + unsigned char reserved3; + + unsigned long prescaler_count; + +} mcchip_regs; + +#define mcchip ((mcchip_regs * const) 0xFFF42000) + +/*----------------------------------------------------------------*/ + +/* + * SCC Z8523(0) defines and macros + * ------------------------------- + * Prototypes for the low-level serial io are also included here, + * because such stuff is bsp-specific (yet). The function bodies + * are in console.c + * + * NOTE from Eric Vaitl : + * + * I dropped RTEMS into a 162FX today (the MVME162-513). The 162FX has a + * bug in the MC2 chip (revision 1) such that the SCC data register is + * not accessible, it has to be accessed indirectly through the SCC + * control register. + */ + +enum {portB, portA}; + +extern bool char_ready(int port, char *ch); +extern char char_wait(int port); +extern void char_put(int port, char ch); + +#define TX_BUFFER_EMPTY 0x04 +#define RX_DATA_AVAILABLE 0x01 +#define SCC_VECTOR 0x40 + +typedef volatile struct { + unsigned char pad1; + volatile unsigned char csr; + unsigned char pad2; + volatile unsigned char buf; +} scc_regs; + +#define scc ((scc_regs * const) 0xFFF45000) + +#define ZWRITE0(port, v) (scc[port].csr = (unsigned char)(v)) +#define ZREAD0(port) (scc[port].csr) + +#define ZREAD(port, n) (ZWRITE0(port, n), (scc[port].csr)) +#define ZREADD(port) (scc[port].csr=0x08, scc[port].csr ) + +#define ZWRITE(port, n, v) (ZWRITE0(port, n), ZWRITE0(port, v)) +#define ZWRITED(port, v) (scc[port].csr = 0x08, \ + scc[port].csr = (unsigned char)(v)) +/*----------------------------------------------------------------*/ + +#ifdef M162_INIT +#undef EXTERN +#define EXTERN +#else +#undef EXTERN +#define EXTERN extern +#endif + +/* + * This value is the default address location of the 162Bug vector table + * and is also the default start address of the boards DRAM. This value + * may be different for your specific board based on a number of factors: + * + * Default DRAM address: 0x00000000 + * Default SRAM address: 0xFFE00000 + * + * o If no DRAM can be found by the 162Bug program, it will use SRAM. + * o The default SRAM address may be different if SRAM mezzanine boards + * are installed on the main board. + * o Both the DRAM and SRAM addresses can be modified by changing the + * appropriate values in NVRAM using the ENV command at the 162Bug + * prompt. + * + * If your board has different values than the defaults, change the value + * of the following define. + * + */ +#define MOT_162BUG_VEC_ADDRESS 0x00000000 + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Prototypes for methods in the BSP that cross file boundaries. + */ +bool char_ready(int port, char *ch); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mvme162/include/page_table.h b/bsps/m68k/mvme162/include/page_table.h new file mode 100644 index 0000000000..09b93a49bd --- /dev/null +++ b/bsps/m68k/mvme162/include/page_table.h @@ -0,0 +1,27 @@ +/* + * This file was submitted by Eric Vaitl and + * supports page table initialization. + */ + +#ifndef PAGE_TABLE_H +#define PAGE_TABLE_H + +extern void page_table_teardown(void); +extern void page_table_init(void); +extern int page_table_map(void *addr, unsigned long size, int cache_type); + +enum { + CACHE_WRITE_THROUGH, + CACHE_COPYBACK, + CACHE_NONE_SERIALIZED, + CACHE_NONE +}; +enum { + PTM_SUCCESS, + PTM_BAD_ADDR, + PTM_BAD_SIZE, + PTM_BAD_CACHE, + PTM_NO_TABLE_SPACE +}; + +#endif diff --git a/bsps/m68k/mvme162/include/tm27.h b/bsps/m68k/mvme162/include/tm27.h new file mode 100644 index 0000000000..750408d009 --- /dev/null +++ b/bsps/m68k/mvme162/include/tm27.h @@ -0,0 +1,39 @@ +/* + * @file + * @ingroup m68k_mvme162 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: We use software interrupt 0 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \ + lcsr->intr_level[2] |= 3; \ + lcsr->intr_ena |= 0x100; + +#define Cause_tm27_intr() lcsr->intr_soft_set |= 0x100 + +#define Clear_tm27_intr() lcsr->intr_clear |= 0x100 + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mvme167/headers.am b/bsps/m68k/mvme167/headers.am new file mode 100644 index 0000000000..23b9370680 --- /dev/null +++ b/bsps/m68k/mvme167/headers.am @@ -0,0 +1,7 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mvme167/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mvme167/include/page_table.h +include_HEADERS += ../../../../../../bsps/m68k/mvme167/include/tm27.h diff --git a/bsps/m68k/mvme167/include/bsp.h b/bsps/m68k/mvme167/include/bsp.h new file mode 100644 index 0000000000..d04b4f3952 --- /dev/null +++ b/bsps/m68k/mvme167/include/bsp.h @@ -0,0 +1,318 @@ +/** + * @file + * + * Following defines must reflect the setup of the particular MVME167. + * All page references are to the MVME166/MVME167/MVME187 Single Board + * Computer Programmer's Reference Guide (MVME187PG/D2) with the April + * 1993 supplements/addenda (MVME187PG/D2A1). + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modifications of respective RTEMS file: + * Copyright (c) 1998, National Research Council of Canada + */ + +#ifndef LIBBSP_M68K_MVME167_BSP_H +#define LIBBSP_M68K_MVME167_BSP_H + +#include +#include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* GCSR is in mvme16x_hw.h */ +/* LCSR is in mvme16x_hw.h */ +/* i82596 is in mvme16x_hw.h */ +/* NVRAM is in mvme16x_hw.h */ + +#if 0 +/* + * Representation of the PCCchip2 + */ +typedef volatile struct pccchip2_regs_ { + unsigned char chip_id; /* 0xFFF42000 */ + unsigned char chip_revision; /* 0xFFF42001 */ + unsigned char gen_control; /* 0xFFF42002 */ + unsigned char vector_base; /* 0xFFF42003 */ + unsigned long timer_cmp_1; /* 0xFFF42004 */ + unsigned long timer_cnt_1; /* 0xFFF42008 */ + unsigned long timer_cmp_2; /* 0xFFF4200C */ + unsigned long timer_cnt_2; /* 0xFFF42010 */ + unsigned char LSB_prescaler_count;/* 0xFFF42014 */ + unsigned char prescaler_clock_adjust; /* 0xFFF42015 */ + unsigned char timer_ctl_2; /* 0xFFF42016 */ + unsigned char timer_ctl_1; /* 0xFFF42017 */ + unsigned char gpi_int_ctl; /* 0xFFF42018 */ + unsigned char gpio_ctl; /* 0xFFF42019 */ + unsigned char timer_int_ctl_2; /* 0xFFF4201A */ + unsigned char timer_int_ctl_1; /* 0xFFF4201B */ + unsigned char SCC_error; /* 0xFFF4201C */ + unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */ + unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */ + unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */ + unsigned char reserved1[3]; + unsigned char modem_piack; /* 0xFFF42023 */ + unsigned char reserved2; + unsigned char tx_piack; /* 0xFFF42025 */ + unsigned char reserved3; + unsigned char rx_piack; /* 0xFFF42027 */ + unsigned char LANC_error; /* 0xFFF42028 */ + unsigned char reserved4; + unsigned char LANC_int_ctl; /* 0xFFF4202A */ + unsigned char LANC_berr_ctl; /* 0xFFF4202B */ + unsigned char SCSI_error; /* 0xFFF4202C */ + unsigned char reserved5[2]; + unsigned char SCSI_int_ctl; /* 0xFFF4202F */ + unsigned char print_ack_int_ctl; /* 0xFFF42030 */ + unsigned char print_fault_int_ctl;/* 0xFFF42031 */ + unsigned char print_sel_int_ctl; /* 0xFFF42032 */ + unsigned char print_pe_int_ctl; /* 0xFFF42033 */ + unsigned char print_busy_int_ctl; /* 0xFFF42034 */ + unsigned char reserved6; + unsigned char print_input_status; /* 0xFFF42036 */ + unsigned char print_ctl; /* 0xFFF42037 */ + unsigned char chip_speed; /* 0xFFF42038 */ + unsigned char reserved7; + unsigned char print_data; /* 0xFFF4203A */ + unsigned char reserved8[3]; + unsigned char int_level; /* 0xFFF4203E */ + unsigned char int_mask; /* 0xFFF4203F */ +} pccchip2_regs; + +/* + * Base address of the PCCchip2. + * This is not configurable in the MVME167. + */ +#define pccchip2 ((pccchip2_regs * const) 0xFFF42000) + +#endif +/* + * The MVME167 is equiped with one or two MEMC040 memory controllers at + * 0xFFF43000 and 0xFFF43100. This port assumes that the controllers + * were initialized by 167Bug. + */ +typedef volatile struct memc040_regs_ { + unsigned char chip_id; /* 0xFFF43000/0xFFF43100 */ + unsigned char reserved1[3]; + unsigned char chip_revision; /* 0xFFF43004/0xFFF43104 */ + unsigned char reserved2[3]; + unsigned char mem_config; /* 0xFFF43008/0xFFF43108 */ + unsigned char reserved3[3]; + unsigned char alt_status; /* 0xFFF4300C/0xFFF4310C */ + unsigned char reserved4[3]; + unsigned char alt_ctl; /* 0xFFF43010/0xFFF43110 */ + unsigned char reserved5[3]; + unsigned char base_addr; /* 0xFFF43014/0xFFF43114 */ + unsigned char reserved6[3]; + unsigned char ram_ctl; /* 0xFFF43018/0xFFF43118 */ + unsigned char reserved7[3]; + unsigned char bus_clk; /* 0xFFF4301C/0xFFF4311C */ +} memc040_regs; + +/* + * Base address of the MEMC040s. + * This is not configurable in the MVME167. + */ +#define memc040_1 ((memc040_regs * const) 0xFFF43000) +#define memc040_2 ((memc040_regs * const) 0xFFF43100) + +/* + * The MVME167 may be equiped with error-correcting RAM cards. In this case, + * each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port + * assumes that these controllers, if present, are initialized by 167Bug. + * They do not appear to hold information of interest at this time, so they + * are not described. However, each MCECC pair lives at the same address as + * the MEMC040 is replaces. The first eight registers of the MCECC are + * nearly identical to the ones of the MEMC040, and the memc040_X structures + * can be used to read those first eight registers. + */ + +/* + * Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller + */ +typedef volatile struct cd2401_regs_ { + unsigned char reserved1[7]; + unsigned char cor7; /* 0xFFF45007 - Channel Option 7 */ + unsigned char reserved2; + unsigned char livr; /* 0xFFF45009 - Local Interrupt Vector */ + unsigned char reserved3[6]; + unsigned char cor1; /* 0xFFF45010 - Channel Option 1 */ + unsigned char ier; /* 0xFFF45011 - Interrupt Enable */ + unsigned char stcr; /* 0xFFF45012 - Special Transmit Command */ + unsigned char ccr; /* 0xFFF45013 - Channel Command */ + unsigned char cor5; /* 0xFFF45014 - Channel Option 5 */ + unsigned char cor4; /* 0xFFF45015 - Channel Option 4 */ + unsigned char cor3; /* 0xFFF45016 - Channel Option 3 */ + unsigned char cor2; /* 0xFFF45017 - Channel Option 2 */ + unsigned char cor6; /* 0xFFF45018 - Channel Option 6 */ + unsigned char dmabsts; /* 0xFFF45019 - DMA Buffer Status */ + unsigned char csr; /* 0xFFF4501A - Channel Status */ + unsigned char cmr; /* 0xFFF4501B - Channel Mode */ + union { + struct { + unsigned char schr4; /* 0xFFF4501C - Special Character 4 */ + unsigned char schr3; /* 0xFFF4501D - Special Character 3 */ + unsigned char schr2; /* 0xFFF4501E - Special Character 2 */ + unsigned char schr1; /* 0xFFF4501F - Special Character 1 */ + } async; + struct { + unsigned char rfar4; /* 0xFFF4501C - Receive Frame Address 4 */ + unsigned char rfar3; /* 0xFFF4501D - Receive Frame Address 3 */ + unsigned char rfar2; /* 0xFFF4501E - Receive Frame Address 2 */ + unsigned char rfar1; /* 0xFFF4501F - Receive Frame Address 1 */ + } sync; + } u1; + unsigned char reserved4[2]; + unsigned char scrh; /* 0xFFF45022 - Special Character Range High */ + unsigned char scrl; /* 0xFFF45023 - Special Character Range Low */ + union { + struct { + unsigned short rtpr; /* 0xFFF45024 - Receive Timeout Period */ + } w; + struct { + unsigned char rtprh; /* 0xFFF45024 - Receive Timeout Period High */ + unsigned char rtprl; /* 0xFFF45025 - Receive Timeout Period Low */ + } b; + } u2; + unsigned char licr; /* 0xFFF45026 - Local Interrupt Channel */ + unsigned char reserved5[2]; + union { + struct { + unsigned char ttr; /* 0xFFF45029 - Transmit Timer */ + } async; + struct { + unsigned char gt2; /* 0xFFF45029 - General Timer 2 */ + } sync; + } u3; + union { + struct { + unsigned short gt1; /* 0xFFF4502A - General Timer 1 */ + } w; + struct { + unsigned char gt1h; /* 0xFFF4502A - General Timer 2 High */ + unsigned char gt1l; /* 0xFFF4502B - General Timer 1 Low */ + } b; + } u4; + unsigned char reserved6[2]; + unsigned char lnxt; /* 0xFF4502E - LNext Character */ + unsigned char reserved7; + unsigned char rfoc; /* 0xFFF45030 - Receive FIFO Output Count */ + unsigned char reserved8[7]; + unsigned short tcbadru; /* 0xFF45038 - Transmit Current Buffer Address Upper */ + unsigned short tcbadrl; /* 0xFF4503A - Transmit Current Buffer Address Lower */ + unsigned short rcbadru; /* 0xFF4503C - Receive Current Buffer Address Upper */ + unsigned short rcbadrl; /* 0xFF4503E - Receive Current Buffer Address Lower */ + unsigned short arbadru; /* 0xFF45040 - A Receive Buffer Address Upper */ + unsigned short arbardl; /* 0xFF45042 - A Receive Buffer Address Lower */ + unsigned short brbadru; /* 0xFF45044 - B Receive Buffer Address Upper */ + unsigned short brbadrl; /* 0xFF45046 - B Receive Buffer Address Lower */ + unsigned short brbcnt; /* 0xFF45048 - B Receive Buffer Byte Count */ + unsigned short arbcnt; /* 0xFF4504A - A Receive Buffer Byte Count */ + unsigned short reserved9; + unsigned char brbsts; /* 0xFF4504E - B Receive Buffer Status */ + unsigned char arbsts; /* 0xFF4504F - A Receive Buffer Status */ + unsigned short atbadru; /* 0xFF45050 - A Transmit Buffer Address Upper */ + unsigned short atbadrl; /* 0xFF45052 - A Transmit Buffer Address Lower */ + unsigned short btbadru; /* 0xFF45054 - B Transmit Buffer Address Upper */ + unsigned short btbadrl; /* 0xFF45056 - B Transmit Buffer Address Lower */ + unsigned short btbcnt; /* 0xFF45058 - B Transmit Buffer Byte Count */ + unsigned short atbcnt; /* 0xFF4505A - A Transmit Buffer Byte Count */ + unsigned short reserved10; + unsigned char btbsts; /* 0xFF4505E - B Transmit Buffer Status */ + unsigned char atbsts; /* 0xFF4505F - A Transmit Buffer Status */ + unsigned char reserved11[32]; + unsigned char tftc; /* 0xFFF45080 - Transmit FIFO Transfer Count */ + unsigned char gfrcr; /* 0xFFF45081 - Global Firmware Revision Code */ + unsigned char reserved12[2]; + unsigned char reoir; /* 0xFFF45084 - Receive End Of Interrupt */ + unsigned char teoir; /* 0xFFF45085 - Transmit End Of Interrupt */ + unsigned char meoir; /* 0xFFF45086 - Modem End Of Interrupt */ + union { + struct { + unsigned short risr; /* 0xFFF45088 - Receive Interrupt Status */ + } w; + struct { + unsigned char risrh; /* 0xFFF45088 - Receive Interrupt Status High */ + unsigned char risrl; /* 0xFFF45089 - Receive Interrupt Status Low */ + } b; + } u5; + unsigned char tisr; /* 0xFFF4508A - Transmit Interrupt Status */ + unsigned char misr; /* 0xFFF4508B - Modem/Timer Interrupt Status */ + unsigned char reserved13[2]; + unsigned char bercnt; /* 0xFFF4508E - Bus Error Retry Count */ + unsigned char reserved14[49]; + unsigned char tcor; /* 0xFFF450C0 - Transmit Clock Option */ + unsigned char reserved15[2]; + unsigned char tbpr; /* 0xFFF450C3 - Transmit Baud Rate Period */ + unsigned char reserved16[4]; + unsigned char rcor; /* 0xFFF450C8 - Receive Clock Option */ + unsigned char reserved17[2]; + unsigned char rbpr; /* 0xFFF450CB - Receive Baud Rate Period */ + unsigned char reserved18[10]; + unsigned char cpsr; /* 0xFFF450D6 - CRC Polynomial Select */ + unsigned char reserved19[3]; + unsigned char tpr; /* 0xFFF450DA - Timer Period */ + unsigned char reserved20[3]; + unsigned char msvr_rts; /* 0xFFF450DE - Modem Signal Value - RTS */ + unsigned char msvr_dtr; /* 0xFFF450DF - Modem Signal Value - DTR */ + unsigned char tpilr; /* 0xFFF450E0 - Transmit Priority Interrupt Level */ + unsigned char rpilr; /* 0xFFF450E1 - Receive Priority Interrupt Level */ + unsigned char stk; /* 0xFFF450E2 - Stack */ + unsigned char mpilr; /* 0xFFF450E3 - Modem Priority Interrupt Level */ + unsigned char reserved21[8]; + unsigned char tir; /* 0xFFF450EC - Transmit Interrupt */ + unsigned char rir; /* 0xFFF450ED - Receive Interrupt */ + unsigned char car; /* 0xFFF450EE - Channel Access */ + unsigned char mir; /* 0xFFF450EF - Model Interrupt */ + unsigned char reserved22[6]; + unsigned char dmr; /* 0xFFF450F6 - DMA Mode */ + unsigned char reserved23; + unsigned char dr; /* 0xFFF450F8 - Receive/Transmit Data */ +} cd2401_regs; + +/* + * Base address of the CD2401. + * This is not configurable in the MVME167. + */ +#define cd2401 ((cd2401_regs * const) 0xFFF45000) + +/* CD2401 is clocked at 20 MHz */ +#define CD2401_CLK_RATE 20000000 + +/* BSP-wide functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +#ifdef M167_INIT +#undef EXTERN +#define EXTERN +#else +#undef EXTERN +#define EXTERN extern +#endif + +extern void *M68Kvec[]; /* vector table address */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mvme167/include/page_table.h b/bsps/m68k/mvme167/include/page_table.h new file mode 100644 index 0000000000..2db5591729 --- /dev/null +++ b/bsps/m68k/mvme167/include/page_table.h @@ -0,0 +1,43 @@ +/* page_table.h + * + * This file was submitted by Eric Vaitl and + * supports page table initialization. + * + * For now, we only use the transparent translation registers. Page tables + * may be set up in the future. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modifications of respective RTEMS files: + * Copyright (c) 1998, National Research Council of Canada + */ + +#ifndef __PAGE_TABLE_H +#define __PAGE_TABLE_H + +#include + +void page_table_teardown( void ); +void page_table_init( void ); + +enum { + CACHE_WRITE_THROUGH, + CACHE_COPYBACK, + CACHE_NONE_SERIALIZED, + CACHE_NONE +}; + +enum { + PTM_SUCCESS, + PTM_BAD_ADDR, + PTM_BAD_SIZE, + PTM_BAD_CACHE, + PTM_NO_TABLE_SPACE +}; + +#endif diff --git a/bsps/m68k/mvme167/include/tm27.h b/bsps/m68k/mvme167/include/tm27.h new file mode 100644 index 0000000000..5b65311794 --- /dev/null +++ b/bsps/m68k/mvme167/include/tm27.h @@ -0,0 +1,38 @@ +/* + * @file + * @ingroup m68k_mvme167 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: We use software interrupt 0 + */ +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \ + lcsr->intr_level[2] |= 3; \ + lcsr->intr_ena |= 0x100 + +#define Cause_tm27_intr() lcsr->intr_soft_set |= 0x100 + +#define Clear_tm27_intr() lcsr->intr_clear |= 0x100 + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/uC5282/headers.am b/bsps/m68k/uC5282/headers.am new file mode 100644 index 0000000000..5757c0d98e --- /dev/null +++ b/bsps/m68k/uC5282/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/uC5282/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/uC5282/include/tm27.h diff --git a/bsps/m68k/uC5282/include/bsp.h b/bsps/m68k/uC5282/include/bsp.h new file mode 100644 index 0000000000..a887cc0385 --- /dev/null +++ b/bsps/m68k/uC5282/include/bsp.h @@ -0,0 +1,175 @@ +/* + * uC5282 BSP header file + * + * Author: W. Eric Norum + * + * COPYRIGHT (c) 2005. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_UC5282_BSP_H +#define LIBBSP_M68K_UC5282_BSP_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ +/** BSP Configuration **/ +/* + * Uncomment to use instruction/data cache + * Leave commented to use instruction-only cache + */ +#define RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include /* internal MCF5282 modules */ + +/***************************************************************************/ +/** Network driver configuration **/ +struct rtems_bsdnet_ifconfig; +extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "fs1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* functions */ + +typedef struct { + unsigned int l; + void *v; +} bsp_mnode_t; + +#define RTEMS_BSP_PGM_ERASE_FIRST 0x1 +#define RTEMS_BSP_PGM_RESET_AFTER 0x2 +#define RTEMS_BSP_PGM_EXEC_AFTER 0x4 +#define RTEMS_BSP_PGM_HALT_AFTER 0x8 + +uint32_t bsp_get_CPU_clock_speed(void); +rtems_status_code bsp_allocate_interrupt(int level, int priority); +int bsp_sysReset(int flags); +int bsp_program(bsp_mnode_t *chain, int flags); +unsigned const char *bsp_gethwaddr(int a); +const char *bsp_getbenv(const char *a); +int bsp_flash_erase_range(volatile unsigned short *flashptr, int start, int end); +int bsp_flash_write_range(volatile unsigned short *flashptr, bsp_mnode_t *chain, int offset); + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ +#define FEC_IRQ_LEVEL 4 +#define FEC_IRQ_RX_PRIORITY 7 +#define FEC_IRQ_TX_PRIORITY 6 + +#define PIT3_IRQ_LEVEL 4 +#define PIT3_IRQ_PRIORITY 0 + +#define UART0_IRQ_LEVEL 3 +#define UART0_IRQ_PRIORITY 7 +#define UART1_IRQ_LEVEL 3 +#define UART1_IRQ_PRIORITY 6 +#define UART2_IRQ_LEVEL 3 +#define UART2_IRQ_PRIORITY 5 + +/* + * Fake VME support + * This makes it easier to use EPICS driver support on this BSP. + */ +#define VME_AM_STD_SUP_ASCENDING 0x3f +#define VME_AM_STD_SUP_PGM 0x3e +#define VME_AM_STD_USR_ASCENDING 0x3b +#define VME_AM_STD_USR_PGM 0x3a +#define VME_AM_STD_SUP_DATA 0x3d +#define VME_AM_STD_USR_DATA 0x39 +#define VME_AM_EXT_SUP_ASCENDING 0x0f +#define VME_AM_EXT_SUP_PGM 0x0e +#define VME_AM_EXT_USR_ASCENDING 0x0b +#define VME_AM_EXT_USR_PGM 0x0a +#define VME_AM_EXT_SUP_DATA 0x0d +#define VME_AM_EXT_USR_DATA 0x09 +#define VME_AM_SUP_SHORT_IO 0x2d +#define VME_AM_USR_SHORT_IO 0x29 + +/* + * 'Extended' BSP support + */ +rtems_status_code bspExtInit(void); +typedef void (*BSP_VME_ISR_t)(void *usrArg, unsigned long vector); +BSP_VME_ISR_t BSP_getVME_isr(unsigned long vector, void **parg); +int BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg); +int BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg); +int BSP_enableVME_int_lvl(unsigned int level); +int BSP_disableVME_int_lvl(unsigned int level); +int BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr); + +/* + * This BSP provides its own IDLE task to override the RTEMS one. + * So we prototype it and define the constant confdefs.h expects + * to configure a BSP specific one. + */ +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +/* + * The custom IDLE task keeps some idle statistics. + */ +int bsp_cpu_load_percentage(void); + +/* + * This is a helper method to determine the cause of a reset. + */ +void bsp_reset_cause(char *buf, size_t capacity); + +/* + * SRAM. The BSP uses SRAM for maintaining some clock-driver data + * and for ethernet descriptors (and the initial stack during + * early boot). + */ + +typedef struct mcf5282BufferDescriptor_ { + volatile uint16_t status; + uint16_t length; + volatile void *buffer; +} mcf5282BufferDescriptor_t; + +extern struct { + uint32_t idle_counter; + uint32_t filtered_idle; + uint32_t max_idle_count; + uint32_t pitc_per_tick; + uint32_t nsec_per_pitc; + uint32_t pad[3]; /* align to 16-bytes for descriptors */ + mcf5282BufferDescriptor_t fec_descriptors[]; + /* buffer descriptors are allocated from here */ + + /* initial stack is at top of SRAM (start.S) */ +} __SRAMBASE; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/uC5282/include/tm27.h b/bsps/m68k/uC5282/include/tm27.h new file mode 100644 index 0000000000..9a24da3755 --- /dev/null +++ b/bsps/m68k/uC5282/include/tm27.h @@ -0,0 +1,40 @@ +/* + * @file + * @ingroup m68k_uC5282 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * Author: W. Eric Norum + * + * COPYRIGHT (c) 2005-2014. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/mips/csb350/headers.am b/bsps/mips/csb350/headers.am new file mode 100644 index 0000000000..47c143ca0c --- /dev/null +++ b/bsps/mips/csb350/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/mips/csb350/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/mips/csb350/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/mips/csb350/include/bsp/irq.h diff --git a/bsps/mips/csb350/include/bsp.h b/bsps/mips/csb350/include/bsp.h new file mode 100644 index 0000000000..ed503a1faa --- /dev/null +++ b/bsps/mips/csb350/include/bsp.h @@ -0,0 +1,47 @@ +/** + * @file + * + * This include file contains some definitions specific to the + * Cogent CSB350 Board. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_CSB350_BSP_H +#define LIBBSP_MIPS_CSB350_BSP_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION +#define BSP_SHARED_HANDLER_SUPPORT 1 + +/* + * Network driver configuration + */ +extern struct rtems_bsdnet_ifconfig *config; + +int rtems_au1x00_emac_attach(struct rtems_bsdnet_ifconfig *config, + int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_au1x00_emac_attach + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/mips/csb350/include/bsp/irq.h b/bsps/mips/csb350/include/bsp/irq.h new file mode 100644 index 0000000000..4f006fdd5f --- /dev/null +++ b/bsps/mips/csb350/include/bsp/irq.h @@ -0,0 +1,123 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief interrupt definitions. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_AU1X00_IRQ_H +#define LIBBSP_MIPS_AU1X00_IRQ_H + +#ifndef ASM + #include + #include + #include + #include +#endif + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +/* + * Interrupt Vector Numbers + * + */ +/* MIPS_INTERRUPT_BASE should be 32 (0x20) */ +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define AU1X00_IRQ_SW0 (MIPS_INTERRUPT_BASE + 0) +#define AU1X00_IRQ_SW1 (MIPS_INTERRUPT_BASE + 1) +#define AU1X00_IRQ_IC0_REQ0 (MIPS_INTERRUPT_BASE + 2) +#define AU1X00_IRQ_IC0_REQ1 (MIPS_INTERRUPT_BASE + 3) +#define AU1X00_IRQ_IC1_REQ0 (MIPS_INTERRUPT_BASE + 4) +#define AU1X00_IRQ_IC1_REQ1 (MIPS_INTERRUPT_BASE + 5) +#define AU1X00_IRQ_PERF (MIPS_INTERRUPT_BASE + 6) +#define AU1X00_IRQ_CNT (MIPS_INTERRUPT_BASE + 7) + +#define AU1X00_IRQ_IC0_BASE (MIPS_INTERRUPT_BASE + 8) +#define AU1X00_IRQ_UART0 (MIPS_INTERRUPT_BASE + 8) +#define AU1X00_IRQ_INTA (MIPS_INTERRUPT_BASE + 9) +#define AU1X00_IRQ_INTB (MIPS_INTERRUPT_BASE + 10) +#define AU1X00_IRQ_UART3 (MIPS_INTERRUPT_BASE + 11) +#define AU1X00_IRQ_INTC (MIPS_INTERRUPT_BASE + 12) +#define AU1X00_IRQ_INTD (MIPS_INTERRUPT_BASE + 13) +#define AU1X00_IRQ_DMA0 (MIPS_INTERRUPT_BASE + 14) +#define AU1X00_IRQ_DMA1 (MIPS_INTERRUPT_BASE + 15) +#define AU1X00_IRQ_DMA2 (MIPS_INTERRUPT_BASE + 16) +#define AU1X00_IRQ_DMA3 (MIPS_INTERRUPT_BASE + 17) +#define AU1X00_IRQ_DMA4 (MIPS_INTERRUPT_BASE + 18) +#define AU1X00_IRQ_DMA5 (MIPS_INTERRUPT_BASE + 19) +#define AU1X00_IRQ_DMA6 (MIPS_INTERRUPT_BASE + 20) +#define AU1X00_IRQ_DMA7 (MIPS_INTERRUPT_BASE + 21) +#define AU1X00_IRQ_TOY_TICK (MIPS_INTERRUPT_BASE + 22) +#define AU1X00_IRQ_TOY_MATCH0 (MIPS_INTERRUPT_BASE + 23) +#define AU1X00_IRQ_TOY_MATCH1 (MIPS_INTERRUPT_BASE + 24) +#define AU1X00_IRQ_TOY_MATCH2 (MIPS_INTERRUPT_BASE + 25) +#define AU1X00_IRQ_RTC_TICK (MIPS_INTERRUPT_BASE + 26) +#define AU1X00_IRQ_RTC_MATCH0 (MIPS_INTERRUPT_BASE + 27) +#define AU1X00_IRQ_RTC_MATCH1 (MIPS_INTERRUPT_BASE + 28) +#define AU1X00_IRQ_RTC_MATCH2 (MIPS_INTERRUPT_BASE + 29) +#define AU1X00_IRQ_PCI_ERR (MIPS_INTERRUPT_BASE + 30) +#define AU1X00_IRQ_RSV0 (MIPS_INTERRUPT_BASE + 31) +#define AU1X00_IRQ_USB_DEV (MIPS_INTERRUPT_BASE + 32) +#define AU1X00_IRQ_USB_SUSPEND (MIPS_INTERRUPT_BASE + 33) +#define AU1X00_IRQ_USB_HOST (MIPS_INTERRUPT_BASE + 34) +#define AU1X00_IRQ_AC97_ACSYNC (MIPS_INTERRUPT_BASE + 35) +#define AU1X00_IRQ_MAC0 (MIPS_INTERRUPT_BASE + 36) +#define AU1X00_IRQ_MAC1 (MIPS_INTERRUPT_BASE + 37) +#define AU1X00_IRQ_RSV1 (MIPS_INTERRUPT_BASE + 38) +#define AU1X00_IRQ_AC97_CMD (MIPS_INTERRUPT_BASE + 39) + +#define AU1X00_IRQ_IC1_BASE (MIPS_INTERRUPT_BASE + 40) +#define AU1X00_IRQ_GPIO0 (MIPS_INTERRUPT_BASE + 40) +#define AU1X00_IRQ_GPIO1 (MIPS_INTERRUPT_BASE + 41) +#define AU1X00_IRQ_GPIO2 (MIPS_INTERRUPT_BASE + 42) +#define AU1X00_IRQ_GPIO3 (MIPS_INTERRUPT_BASE + 43) +#define AU1X00_IRQ_GPIO4 (MIPS_INTERRUPT_BASE + 44) +#define AU1X00_IRQ_GPIO5 (MIPS_INTERRUPT_BASE + 45) +#define AU1X00_IRQ_GPIO6 (MIPS_INTERRUPT_BASE + 46) +#define AU1X00_IRQ_GPIO7 (MIPS_INTERRUPT_BASE + 47) +#define AU1X00_IRQ_GPIO8 (MIPS_INTERRUPT_BASE + 48) +#define AU1X00_IRQ_GPIO9 (MIPS_INTERRUPT_BASE + 49) +#define AU1X00_IRQ_GPIO10 (MIPS_INTERRUPT_BASE + 50) +#define AU1X00_IRQ_GPIO11 (MIPS_INTERRUPT_BASE + 51) +#define AU1X00_IRQ_GPIO12 (MIPS_INTERRUPT_BASE + 52) +#define AU1X00_IRQ_GPIO13 (MIPS_INTERRUPT_BASE + 53) +#define AU1X00_IRQ_GPIO14 (MIPS_INTERRUPT_BASE + 54) +#define AU1X00_IRQ_GPIO15 (MIPS_INTERRUPT_BASE + 55) +#define AU1X00_IRQ_GPIO200 (MIPS_INTERRUPT_BASE + 56) +#define AU1X00_IRQ_GPIO201 (MIPS_INTERRUPT_BASE + 57) +#define AU1X00_IRQ_GPIO202 (MIPS_INTERRUPT_BASE + 58) +#define AU1X00_IRQ_GPIO203 (MIPS_INTERRUPT_BASE + 59) +#define AU1X00_IRQ_GPIO20 (MIPS_INTERRUPT_BASE + 60) +#define AU1X00_IRQ_GPIO204 (MIPS_INTERRUPT_BASE + 61) +#define AU1X00_IRQ_GPIO205 (MIPS_INTERRUPT_BASE + 62) +#define AU1X00_IRQ_GPIO23 (MIPS_INTERRUPT_BASE + 63) +#define AU1X00_IRQ_GPIO24 (MIPS_INTERRUPT_BASE + 64) +#define AU1X00_IRQ_GPIO25 (MIPS_INTERRUPT_BASE + 65) +#define AU1X00_IRQ_GPIO26 (MIPS_INTERRUPT_BASE + 66) +#define AU1X00_IRQ_GPIO27 (MIPS_INTERRUPT_BASE + 67) +#define AU1X00_IRQ_GPIO28 (MIPS_INTERRUPT_BASE + 68) +#define AU1X00_IRQ_GPIO206 (MIPS_INTERRUPT_BASE + 69) +#define AU1X00_IRQ_GPIO207 (MIPS_INTERRUPT_BASE + 70) +#define AU1X00_IRQ_GPIO208_215 (MIPS_INTERRUPT_BASE + 71) + +#define AU1X00_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE + 72) + +#define BSP_INTERRUPT_VECTOR_MAX AU1X00_MAXIMUM_VECTORS + +/** @} */ + +#endif /* LIBBSP_MIPS_AU1X00_IRQ_H */ diff --git a/bsps/mips/csb350/include/tm27.h b/bsps/mips/csb350/include/tm27.h new file mode 100644 index 0000000000..3a8957d698 --- /dev/null +++ b/bsps/mips/csb350/include/tm27.h @@ -0,0 +1,48 @@ +/** + * @file + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +/* + * Define the interrupt mechanism for Time Test 27 + */ + +int assert_sw_irw(uint32_t irqnum); +int negate_sw_irw(uint32_t irqnum); + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) \ + rtems_interrupt_handler_install( \ + AU1X00_IRQ_SW0, "benchmark", 0, (rtems_interrupt_handler)handler, NULL ); + +#define Cause_tm27_intr() \ + do { \ + assert_sw_irq(0); \ + } while(0) + +#define Clear_tm27_intr() \ + do { \ + negate_sw_irq(0); \ + } while(0) + +#define Lower_tm27_intr() \ + do { \ + continue;\ + } while(0) + +#endif diff --git a/bsps/mips/headers.am b/bsps/mips/headers.am new file mode 100644 index 0000000000..c9aece50dc --- /dev/null +++ b/bsps/mips/headers.am @@ -0,0 +1,15 @@ +## This file was generated by "./boostrap -H". + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/mips/include/bsp/i8259.h +include_bsp_HEADERS += ../../../../../bsps/mips/include/bsp/regs.h + +include_libcpudir = $(includedir)/libcpu +include_libcpu_HEADERS = +include_libcpu_HEADERS += ../../../../../bsps/mips/include/libcpu/au1x00.h +include_libcpu_HEADERS += ../../../../../bsps/mips/include/libcpu/isr_entries.h +include_libcpu_HEADERS += ../../../../../bsps/mips/include/libcpu/rm5231.h +include_libcpu_HEADERS += ../../../../../bsps/mips/include/libcpu/tx3904.h +include_libcpu_HEADERS += ../../../../../bsps/mips/include/libcpu/tx4925.h +include_libcpu_HEADERS += ../../../../../bsps/mips/include/libcpu/tx4938.h diff --git a/bsps/mips/hurricane/headers.am b/bsps/mips/hurricane/headers.am new file mode 100644 index 0000000000..d9713d1b90 --- /dev/null +++ b/bsps/mips/hurricane/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/mips/hurricane/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/mips/hurricane/include/tm27.h +include_HEADERS += ../../../../../../bsps/mips/hurricane/include/usc.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/mips/hurricane/include/bsp/irq.h diff --git a/bsps/mips/hurricane/include/bsp.h b/bsps/mips/hurricane/include/bsp.h new file mode 100644 index 0000000000..1c9dc652f0 --- /dev/null +++ b/bsps/mips/hurricane/include/bsp.h @@ -0,0 +1,79 @@ +/** + * @file + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_HURRICANE_BSP_H +#define LIBBSP_MIPS_HURRICANE_BSP_H + +#ifndef ASM + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void WriteDisplay( char * string ); + +extern uint32_t mips_get_timer( void ); + +#define BSP_FEATURE_IRQ_EXTENSION +#define BSP_SHARED_HANDLER_SUPPORT 1 + +#define CPU_CLOCK_RATE_MHZ (200) +#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */ + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + * + * NOTE: This macro generates a warning like "integer constant out + * of range" which is safe to ignore. In 64 bit mode, unsigned32 + * types are actually 64 bits long so that comparisons between + * unsigned32 types and pointers are valid. The warning is caused + * by code in the delay macro that is necessary for 64 bit mode. + */ + +#define rtems_bsp_delay( microseconds ) \ + { \ + uint32_t _end_clock = \ + mips_get_timer() + microseconds * CLOCKS_PER_MICROSECOND; \ + _end_clock %= 0x100000000; /* make sure result is 32 bits */ \ + \ + /* handle timer overflow, if necessary */ \ + while ( _end_clock < mips_get_timer() ); \ + \ + while ( _end_clock > mips_get_timer() ); \ + } + +/* Constants */ + +#define RAM_START 0 +#define RAM_END 0x100000 + +/* + * Prototypes for methods called from .S for dependency tracking + */ +void init_tlb(void); +void resettlb(int i); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif /* __HURRICANE_BSP_h */ diff --git a/bsps/mips/hurricane/include/bsp/irq.h b/bsps/mips/hurricane/include/bsp/irq.h new file mode 100644 index 0000000000..3347ecb2a6 --- /dev/null +++ b/bsps/mips/hurricane/include/bsp/irq.h @@ -0,0 +1,40 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief interrupt definitions. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_XXX_IRQ_H +#define LIBBSP_MIPS_XXX_IRQ_H + +#ifndef ASM + #include + #include + #include + #include +#endif + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define RM5231_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE+8) +#define BSP_INTERRUPT_VECTOR_MAX RM5231_MAXIMUM_VECTORS + +/** @} */ + +#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */ diff --git a/bsps/mips/hurricane/include/tm27.h b/bsps/mips/hurricane/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/mips/hurricane/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/mips/hurricane/include/usc.h b/bsps/mips/hurricane/include/usc.h new file mode 100644 index 0000000000..167eff0949 --- /dev/null +++ b/bsps/mips/hurricane/include/usc.h @@ -0,0 +1,32 @@ +/* USC constants */ + +#ifndef _USC_H__ +#define _USC_H__ + + +#define USC_REG_BASE (0x1D000000 | 0xA0000000) + +/* Internal register addresses */ +#define SYSTEM (USC_REG_BASE + 0x73) + +#define INT_CFG0 (USC_REG_BASE + 0xE0) +#define INT_CFG1 (USC_REG_BASE + 0xE4) +#define INT_CFG2 (USC_REG_BASE + 0xE8) +#define INT_STAT (USC_REG_BASE + 0xEC) + +#define WD_HBI (USC_REG_BASE + 0xF4) + +#define INT_CFG3 (USC_REG_BASE + 0x158) + +/* INT_CFGx register masks */ +#define HBI_MASK 0x00200000 /* Heartbeat timer interrupt mask */ +#define WDI_MASK 0x00400000 /* Watchdog timer interrupt mask */ +#define MODE_TOTEM_POLE 0x20000000 /* Totem Pole Output Mode */ + +/* WD_HBI register bits */ +#define WD_EN 0x00800000 /* Watchdog enable */ +#define HBI_4000_PS 0x00200000 /* Heartbeat timer prescaler = 4000 */ +#define WD_INIT 0x10 /* Watchdog reset pattern (written to byte 2 in WD_HBI register) */ + + +#endif /* _USC_H__ */ diff --git a/bsps/mips/include/bsp/i8259.h b/bsps/mips/include/bsp/i8259.h new file mode 100644 index 0000000000..8d10523b40 --- /dev/null +++ b/bsps/mips/include/bsp/i8259.h @@ -0,0 +1,269 @@ +/** + * @file + * @ingroup mips_i8259_irq + * @brief Data structure and functions used to control i8259 chip. + */ + +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by RTEMS to control the i8259 chip. + * + * Copyright (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef I8259_H +#define I8259_H + +/** + * @defgroup mips_i8259_irq i8259 Chip Support + * @ingroup mips_shared + * @brief i8259 Chip Support + * @{ + */ + +/** + * @name 8259 edge/level control definitions at VIA + * @{ + */ + +#if 1 +#define ISA8259_M_ELCR 0x4d0 +#define ISA8259_S_ELCR 0x4d1 +#endif + +#define ELCRS_INT15_LVL 0x80 +#define ELCRS_INT14_LVL 0x40 +#define ELCRS_INT13_LVL 0x20 +#define ELCRS_INT12_LVL 0x10 +#define ELCRS_INT11_LVL 0x08 +#define ELCRS_INT10_LVL 0x04 +#define ELCRS_INT9_LVL 0x02 +#define ELCRS_INT8_LVL 0x01 +#define ELCRM_INT7_LVL 0x80 +#define ELCRM_INT6_LVL 0x40 +#define ELCRM_INT5_LVL 0x20 +#define ELCRM_INT4_LVL 0x10 +#define ELCRM_INT3_LVL 0x8 +#define ELCRM_INT2_LVL 0x4 +#define ELCRM_INT1_LVL 0x2 +#define ELCRM_INT0_LVL 0x1 + +/** @} */ + +/** + * @name PIC's command and mask registers + * @{ + */ + +#define PIC_MASTER_COMMAND_IO_PORT 0x20 ///< @brief Master PIC command register */ +#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 ///< @brief Slave PIC command register */ +#define PIC_MASTER_IMR_IO_PORT 0x21 ///< @brief Master PIC Interrupt Mask Register */ +#define PIC_SLAVE_IMR_IO_PORT 0xa1 ///< @brief Slave PIC Interrupt Mask Register */ + +/** @} */ + +/** + * @name Command for specific EOI (End Of Interrupt): Interrupt acknowledge + * @{ + */ + +#define PIC_EOSI 0x60 ///< @brief End of Specific Interrupt (EOSI) */ +#define SLAVE_PIC_EOSI 0x62 ///< @brief End of Specific Interrupt (EOSI) for cascade */ +#define PIC_EOI 0x20 ///< @brief Generic End of Interrupt (EOI) */ + +/** @} */ + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * rtems_irq_number Definitions + */ +#if 0 + +/** + * @name ISA IRQ handler related definitions + * @{ + */ + +#define BSP_ISA_IRQ_NUMBER (16) +#define BSP_ISA_IRQ_LOWEST_OFFSET (0) +#define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1) + +/** @} */ + +#ifndef qemu +#define BSP_PCI_IRQ_NUMBER (16) +#else +#define BSP_PCI_IRQ_NUMBER (0) +#endif +#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER) +#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) + +/* + * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt + * handler might be connected + */ +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) +/* Misc vectors for OPENPIC irqs (IPI, timers) + */ +#ifndef qemu +#define BSP_MISC_IRQ_NUMBER (8) +#else +#define BSP_MISC_IRQ_NUMBER (0) +#endif + +#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) + +/** + * @name Summary + * @{ + */ + +#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) +#define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) + +/** @} */ + +/** + * @name Some ISA IRQ symbolic name definition + * @{ + */ + +#define BSP_ISA_PERIODIC_TIMER (0) +#define BSP_ISA_KEYBOARD (1) +#define BSP_ISA_UART_COM2_IRQ (3) +#define BSP_ISA_UART_COM1_IRQ (4) +#define BSP_ISA_RT_TIMER1 (8) +#define BSP_ISA_RT_TIMER3 (10) + +/** @} */ + +/** + * @name Some PCI IRQ symbolic name definition + * @{ + */ + +#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET) +#if BSP_PCI_IRQ_NUMBER > 0 +#define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0) +#endif + +/** @} */ + +#if defined(mvme2100) +#define BSP_DEC21143_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1) +#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2) +#define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3) +#define BSP_PCMIP_TYPE2_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 4) +#define BSP_PCMIP_TYPE2_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 5) +#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7) +#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8) +#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9) +#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10) +#define BSP_UART_COM1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 13) +#define BSP_FRONT_PANEL_ABORT_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 14) +#define BSP_RTC_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 15) +#else +#define BSP_UART_COM1_IRQ BSP_ISA_UART_COM1_IRQ +#define BSP_UART_COM2_IRQ BSP_ISA_UART_COM2_IRQ +#endif + +/** + * @brief Some Processor execption handled as RTEMS IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) +#endif + +/** + * @name Type definition for RTEMS managed interrupts + * @{ + */ + +typedef unsigned short rtems_i8259_masks; +extern volatile rtems_i8259_masks i8259s_cache; + +/** @} */ + +/*-------------------------------------------------------------------------+ +| Function Prototypes. ++--------------------------------------------------------------------------*/ +/* + * ------------------------ Intel 8259 (or emulation) Mngt Routines ------- + */ + +/** + * @name Function Prototypes + * @{ + */ + +void BSP_i8259s_init(void); + +/** + * @brief function to disable a particular irq at 8259 level. + * + * After calling this function, even if the device asserts the interrupt + * line it will not be propagated further to the processor. + * + * @retval 1 the interrupt was enabled originally + * @retval 0 the interrupt was disabled originally + * @retval <0 error + */ +int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine); + +/** + * @brief function to enable a particular irq at 8259 level. + * + * After calling this function, if the device asserts the interrupt line + * it will be propagated further to the processor. + */ +int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine); + +/** + * @brief function to acknowledge a particular irq at 8259 level. + * + * After calling this function, if a device asserts an enabled interrupt + * line it will be propagated further to the processor. Mainly useful for + * people writing raw handlers as this is automagically done for RTEMS managed + * handlers. + */ +int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine); + +/** + * @brief function to check if a particular irq is enabled at 8259 level. + */ +int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine); + +int BSP_i8259s_int_process(void); + +extern void BSP_rtems_irq_mng_init(unsigned cpuId); +extern void BSP_i8259s_init(void); + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +}; +#endif + +#endif +#endif diff --git a/bsps/mips/include/bsp/regs.h b/bsps/mips/include/bsp/regs.h new file mode 100644 index 0000000000..5cc9fac745 --- /dev/null +++ b/bsps/mips/include/bsp/regs.h @@ -0,0 +1,187 @@ +/** + * @file + * @ingroup mips_regs + * @brief Standard MIPS register names. + */ + +/* + * regs.S -- standard MIPS register names. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/** + * @defgroup mips_regs MIPS Registers + * @ingroup mips_shared + * @brief MIPS Registers + * @{ + */ + +/** + * @name Standard MIPS register names: + * @{ + */ + +#define zero $0 +#define z0 $0 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 ///< @brief kernel private register 0 */ +#define k1 $27 ///< @brief kernel private register 1 */ +#define gp $28 ///< @brief global data pointer */ +#define sp $29 ///< @brief stack-pointer */ +#define fp $30 ///< @brief frame-pointer */ +#define ra $31 ///< @brief return address */ +#define pc $pc ///< @brief pc, used on mips16 */ + +#define fp0 $f0 +#define fp1 $f1 + +/** @} */ + +/** + * @name Useful memory constants: + * @{ + */ + +#define K0BASE 0x80000000 +#ifndef __mips64 +#define K1BASE 0xA0000000 +#else +#define K1BASE 0xFFFFFFFFA0000000LL +#endif + +/** @} */ + +#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE) + +/** + * @name Standard Co-Processor 0 register numbers: + * @{ + */ + +#define C0_COUNT $9 ///< @brief Count Register */ +#define C0_SR $12 ///< @brief Status Register */ +#define C0_CAUSE $13 ///< @brief last exception description */ +#define C0_EPC $14 ///< @brief Exception error address */ +#define C0_CONFIG $16 ///< @brief CPU configuration */ + +/** @} */ + +/** + * @name Standard Status Register bitmasks: + * @{ + */ + +#define SR_CU1 0x20000000 ///< @brief Mark CP1 as usable */ +#define SR_FR 0x04000000 ///< @brief Enable MIPS III FP registers */ +#define SR_BEV 0x00400000 ///< @brief Controls location of exception vectors */ +#define SR_PE 0x00100000 ///< @brief Mark soft reset (clear parity error) */ + +#define SR_KX 0x00000080 ///< @brief Kernel extended addressing enabled */ +#define SR_SX 0x00000040 ///< @brief Supervisor extended addressing enabled */ +#define SR_UX 0x00000020 ///< @brief User extended addressing enabled */ + +/** @} */ + +/** + * @name Standard (R4000) cache operations. + * @brief Taken from "MIPS R4000 Microprocessor User's Manual" 2nd edition: + * @{ + */ + +#define CACHE_I (0) ///< @brief primary instruction */ +#define CACHE_D (1) ///< @brief primary data */ +#define CACHE_SI (2) ///< @brief secondary instruction */ +#define CACHE_SD (3) ///< @brief secondary data (or combined instruction/data) */ + +#define INDEX_INVALIDATE (0) ///< @brief also encodes WRITEBACK if CACHE_D or CACHE_SD */ +#define INDEX_LOAD_TAG (1) +#define INDEX_STORE_TAG (2) +#define CREATE_DIRTY_EXCLUSIVE (3) ///< @brief CACHE_D and CACHE_SD only */ +#define HIT_INVALIDATE (4) +#define CACHE_FILL (5) ///< @brief CACHE_I only */ +#define HIT_WRITEBACK_INVALIDATE (5) ///< @brief CACHE_D and CACHE_SD only */ +#define HIT_WRITEBACK (6) ///< @brief CACHE_I, CACHE_D and CACHE_SD only */ +#define HIT_SET_VIRTUAL (7) ///< @brief CACHE_SI and CACHE_SD only */ + +#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c)) + +/** @} */ + +/** + * @name Individual cache operations: + * @{ + */ + +#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) +#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) +#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) +#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) + +#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) +#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) +#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) +#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) + +#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) +#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) +#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) +#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) + +#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) +#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) + +#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) +#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) +#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) +#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) + +#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) +#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) +#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) + +#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) +#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) +#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) + +#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) +#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) + +/** @} */ + +/** @} */ + +/*> EOF regs.S <*/ diff --git a/bsps/mips/include/libcpu/au1x00.h b/bsps/mips/include/libcpu/au1x00.h new file mode 100644 index 0000000000..a85a39ed48 --- /dev/null +++ b/bsps/mips/include/libcpu/au1x00.h @@ -0,0 +1,445 @@ +/** + * @file + * + * AMD AU1X00 specific information + */ + +/* + * Copyright (c) 2005 by Cogent Computer Systems + * Written by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __AU1X00_H__ +#define __AU1X00_H__ + +#define bit(x) (1 << (x)) + +/* Au1x00 CP0 registers + */ +#define CP0_Index $0 +#define CP0_Random $1 +#define CP0_EntryLo0 $2 +#define CP0_EntryLo1 $3 +#define CP0_Context $4 +#define CP0_PageMask $5 +#define CP0_Wired $6 +#define CP0_BadVAddr $8 +#define CP0_Count $9 +#define CP0_EntryHi $10 +#define CP0_Compare $11 +#define CP0_Status $12 +#define CP0_Cause $13 +#define CP0_EPC $14 +#define CP0_PRId $15 +#define CP0_Config $16 +#define CP0_Config0 $16 +#define CP0_Config1 $16,1 +#define CP0_LLAddr $17 +#define CP0_WatchLo $18 +#define CP0_IWatchLo $18,1 +#define CP0_WatchHi $19 +#define CP0_IWatchHi $19,1 +#define CP0_Scratch $22 +#define CP0_Debug $23 +#define CP0_DEPC $24 +#define CP0_PerfCnt $25 +#define CP0_PerfCtrl $25,1 +#define CP0_DTag $28 +#define CP0_DData $28,1 +#define CP0_ITag $29 +#define CP0_IData $29,1 +#define CP0_ErrorEPC $30 +#define CP0_DESave $31 + +/* Addresses common to all AU1x00 CPUs */ +#define AU1X00_MEM_ADDR 0xB4000000 +#define AU1X00_AC97_ADDR 0xB0000000 +#define AU1X00_USBH_ADDR 0xB0100000 +#define AU1X00_USBD_ADDR 0xB0200000 +#define AU1X00_MACDMA0_ADDR 0xB4004000 +#define AU1X00_MACDMA1_ADDR 0xB4004200 +#define AU1X00_UART0_ADDR 0xB1100000 +#define AU1X00_UART3_ADDR 0xB1400000 +#define AU1X00_SYS_ADDR 0xB1900000 +#define AU1X00_GPIO2_ADDR 0xB1700000 +#define AU1X00_IC0_ADDR 0xB0400000 +#define AU1X00_IC1_ADDR 0xB1800000 + +/* Au1100 base addresses (in KSEG1 region) */ +#define AU1100_MAC0_ADDR 0xB0500000 +#define AU1100_MACEN_ADDR 0xB0520000 + +/* Au1500 base addresses (in KSEG1 region) */ +#define AU1500_MAC0_ADDR 0xB1500000 +#define AU1500_MAC1_ADDR 0xB1510000 +#define AU1500_MACEN_ADDR 0xB1520000 +#define AU1500_PCI_ADDR 0xB4005000 + +/* Au1x00 gpio2 register offsets + */ +#define gpio2_dir 0x0000 +#define gpio2_output 0x0008 +#define gpio2_pinstate 0x000c +#define gpio2_inten 0x0010 +#define gpio2_enable 0x0014 + +/* Au1x00 memory controller register offsets + */ +#define mem_sdmode0 0x0000 +#define mem_sdmode1 0x0004 +#define mem_sdmode2 0x0008 +#define mem_sdaddr0 0x000C +#define mem_sdaddr1 0x0010 +#define mem_sdaddr2 0x0014 +#define mem_sdrefcfg 0x0018 +#define mem_sdprecmd 0x001C +#define mem_sdautoref 0x0020 +#define mem_sdwrmd0 0x0024 +#define mem_sdwrmd1 0x0028 +#define mem_sdwrmd2 0x002C +#define mem_sdsleep 0x0030 +#define mem_sdsmcke 0x0034 + +#define mem_stcfg0 0x1000 +#define mem_sttime0 0x1004 +#define mem_staddr0 0x1008 +#define mem_stcfg1 0x1010 +#define mem_sttime1 0x1014 +#define mem_staddr1 0x1018 +#define mem_stcfg2 0x1020 +#define mem_sttime2 0x1024 +#define mem_staddr2 0x1028 +#define mem_stcfg3 0x1030 +#define mem_sttime3 0x1034 +#define mem_staddr3 0x1038 + +/* + * Au1x00 peripheral register offsets + */ +#define ac97_enable 0x0010 +#define usbh_enable 0x0007FFFC +#define usbd_enable 0x0058 +#define irda_enable 0x0040 +#define macen_mac0 0x0000 +#define macen_mac1 0x0004 +#define i2s_enable 0x0008 +#define uart_enable 0x0100 +#define ssi_enable 0x0100 + +#define sys_scratch0 0x0018 +#define sys_scratch1 0x001c +#define sys_cntctrl 0x0014 +#define sys_freqctrl0 0x0020 +#define sys_freqctrl1 0x0024 +#define sys_clksrc 0x0028 +#define sys_pinfunc 0x002C +#define sys_powerctrl 0x003C +#define sys_endian 0x0038 +#define sys_wakesrc 0x005C +#define sys_cpupll 0x0060 +#define sys_auxpll 0x0064 +#define sys_pininputen 0x0110 + +#define pci_cmem 0x0000 +#define pci_config 0x0004 +#define pci_b2bmask_cch 0x0008 +#define pci_b2bbase0_venid 0x000C +#define pci_b2bbase1_id 0x0010 +#define pci_mwmask_dev 0x0014 +#define pci_mwbase_rev_ccl 0x0018 +#define pci_err_addr 0x001C +#define pci_spec_intack 0x0020 +#define pci_id 0x0100 +#define pci_statcmd 0x0104 +#define pci_classrev 0x0108 +#define pci_hdrtype 0x010C +#define pci_mbar 0x0110 + +/* + * CSB250-specific values + */ + +#define SYS_CPUPLL 33 +#define SYS_POWERCTRL 1 +#define SYS_AUXPLL 8 +#define SYS_CNTCTRL 256 + +/* RCE0: */ +#define MEM_STCFG0 0x00000203 +#define MEM_STTIME0 0x22080b20 +#define MEM_STADDR0 0x11f03fc0 + +/* RCE1: */ +#define MEM_STCFG1 0x00000203 +#define MEM_STTIME1 0x22080b20 +#define MEM_STADDR1 0x11e03fc0 + +/* RCE2: */ +#define MEM_STCFG2 0x00000244 +#define MEM_STTIME2 0x22080a20 +#define MEM_STADDR2 0x11803f00 + +/* RCE3: */ +#define MEM_STCFG3 0x00000201 +#define MEM_STTIME3 0x22080b20 +#define MEM_STADDR3 0x11003f00 + +/* + * SDCS0 - + * SDCS1 - + * SDCS2 - + */ +#define MEM_SDMODE0 0x00552229 +#define MEM_SDMODE1 0x00552229 +#define MEM_SDMODE2 0x00552229 + +#define MEM_SDADDR0 0x001003F8 +#define MEM_SDADDR1 0x001023F8 +#define MEM_SDADDR2 0x001043F8 + +#define MEM_SDREFCFG_D 0x74000c30 /* disable */ +#define MEM_SDREFCFG_E 0x76000c30 /* enable */ +#define MEM_SDWRMD0 0x00000023 +#define MEM_SDWRMD1 0x00000023 +#define MEM_SDWRMD2 0x00000023 + +#define MEM_1MS ((396000000/1000000) * 1000) + +#define AU1X00_IC_CFG0RD(x) (*(volatile uint32_t*)(x + 0x40)) +#define AU1X00_IC_CFG0SET(x) (*(volatile uint32_t*)(x + 0x40)) +#define AU1X00_IC_CFG0CLR(x) (*(volatile uint32_t*)(x + 0x44)) +#define AU1X00_IC_CFG1RD(x) (*(volatile uint32_t*)(x + 0x48)) +#define AU1X00_IC_CFG1SET(x) (*(volatile uint32_t*)(x + 0x48)) +#define AU1X00_IC_CFG1CLR(x) (*(volatile uint32_t*)(x + 0x4c)) +#define AU1X00_IC_CFG2RD(x) (*(volatile uint32_t*)(x + 0x50)) +#define AU1X00_IC_CFG2SET(x) (*(volatile uint32_t*)(x + 0x50)) +#define AU1X00_IC_CFG2CLR(x) (*(volatile uint32_t*)(x + 0x54)) +#define AU1X00_IC_REQ0INT(x) (*(volatile uint32_t*)(x + 0x54)) +#define AU1X00_IC_SRCRD(x) (*(volatile uint32_t*)(x + 0x58)) +#define AU1X00_IC_SRCSET(x) (*(volatile uint32_t*)(x + 0x58)) +#define AU1X00_IC_SRCCLR(x) (*(volatile uint32_t*)(x + 0x5c)) +#define AU1X00_IC_REQ1INT(x) (*(volatile uint32_t*)(x + 0x5c)) +#define AU1X00_IC_ASSIGNRD(x) (*(volatile uint32_t*)(x + 0x60)) +#define AU1X00_IC_ASSIGNSET(x) (*(volatile uint32_t*)(x + 0x60)) +#define AU1X00_IC_ASSIGNCLR(x) (*(volatile uint32_t*)(x + 0x64)) +#define AU1X00_IC_WAKERD(x) (*(volatile uint32_t*)(x + 0x68)) +#define AU1X00_IC_WAKESET(x) (*(volatile uint32_t*)(x + 0x68)) +#define AU1X00_IC_WAKECLR(x) (*(volatile uint32_t*)(x + 0x6c)) +#define AU1X00_IC_MASKRD(x) (*(volatile uint32_t*)(x + 0x70)) +#define AU1X00_IC_MASKSET(x) (*(volatile uint32_t*)(x + 0x70)) +#define AU1X00_IC_MASKCLR(x) (*(volatile uint32_t*)(x + 0x74)) +#define AU1X00_IC_RISINGRD(x) (*(volatile uint32_t*)(x + 0x78)) +#define AU1X00_IC_RISINGCLR(x) (*(volatile uint32_t*)(x + 0x78)) +#define AU1X00_IC_FALLINGRD(x) (*(volatile uint32_t*)(x + 0x7c)) +#define AU1X00_IC_FALLINGCLR(x) (*(volatile uint32_t*)(x + 0x7c)) +#define AU1X00_IC_TESTBIT(x) (*(volatile uint32_t*)(x + 0x80)) +#define AU1X00_IC_IRQ_MAC0 (bit(28)) +#define AU1X00_IC_IRQ_MAC1 (bit(29)) +#define AU1X00_IC_IRQ_TOY_MATCH0 (bit(15)) +#define AU1X00_IC_IRQ_TOY_MATCH1 (bit(16)) +#define AU1X00_IC_IRQ_TOY_MATCH2 (bit(17)) + + + +#define AU1X00_SYS_TOYTRIM(x) (*(volatile uint32_t*)(x + 0x00)) +#define AU1X00_SYS_TOYWRITE(x) (*(volatile uint32_t*)(x + 0x04)) +#define AU1X00_SYS_TOYMATCH0(x) (*(volatile uint32_t*)(x + 0x08)) +#define AU1X00_SYS_TOYMATCH1(x) (*(volatile uint32_t*)(x + 0x0c)) +#define AU1X00_SYS_TOYMATCH2(x) (*(volatile uint32_t*)(x + 0x10)) +#define AU1X00_SYS_CNTCTRL(x) (*(volatile uint32_t*)(x + 0x14)) +#define AU1X00_SYS_SCRATCH0(x) (*(volatile uint32_t*)(x + 0x18)) +#define AU1X00_SYS_SCRATCH1(x) (*(volatile uint32_t*)(x + 0x1c)) +#define AU1X00_SYS_WAKEMSK(x) (*(volatile uint32_t*)(x + 0x34)) +#define AU1X00_SYS_ENDIAN(x) (*(volatile uint32_t*)(x + 0x38)) +#define AU1X00_SYS_POWERCTRL(x) (*(volatile uint32_t*)(x + 0x3c)) +#define AU1X00_SYS_TOYREAD(x) (*(volatile uint32_t*)(x + 0x40)) +#define AU1X00_SYS_RTCTRIM(x) (*(volatile uint32_t*)(x + 0x44)) +#define AU1X00_SYS_RTCWRITE(x) (*(volatile uint32_t*)(x + 0x48)) +#define AU1X00_SYS_RTCMATCH0(x) (*(volatile uint32_t*)(x + 0x4c)) +#define AU1X00_SYS_RTCMATCH1(x) (*(volatile uint32_t*)(x + 0x50)) +#define AU1X00_SYS_RTCMATCH2(x) (*(volatile uint32_t*)(x + 0x54)) +#define AU1X00_SYS_RTCREAD(x) (*(volatile uint32_t*)(x + 0x58)) +#define AU1X00_SYS_WAKESRC(x) (*(volatile uint32_t*)(x + 0x5c)) +#define AU1X00_SYS_SLPPWR(x) (*(volatile uint32_t*)(x + 0x78)) +#define AU1X00_SYS_SLEEP(x) (*(volatile uint32_t*)(x + 0x7c)) + +#define AU1X00_SYS_CNTCTRL_ERS (bit(23)) +#define AU1X00_SYS_CNTCTRL_RTS (bit(20)) +#define AU1X00_SYS_CNTCTRL_RM2 (bit(19)) +#define AU1X00_SYS_CNTCTRL_RM1 (bit(18)) +#define AU1X00_SYS_CNTCTRL_RM0 (bit(17)) +#define AU1X00_SYS_CNTCTRL_RS (bit(16)) +#define AU1X00_SYS_CNTCTRL_BP (bit(14)) +#define AU1X00_SYS_CNTCTRL_REN (bit(13)) +#define AU1X00_SYS_CNTCTRL_BRT (bit(12)) +#define AU1X00_SYS_CNTCTRL_TEN (bit(11)) +#define AU1X00_SYS_CNTCTRL_BTT (bit(10)) +#define AU1X00_SYS_CNTCTRL_E0 (bit(8)) +#define AU1X00_SYS_CNTCTRL_ETS (bit(7)) +#define AU1X00_SYS_CNTCTRL_32S (bit(5)) +#define AU1X00_SYS_CNTCTRL_TTS (bit(4)) +#define AU1X00_SYS_CNTCTRL_TM2 (bit(3)) +#define AU1X00_SYS_CNTCTRL_TM1 (bit(2)) +#define AU1X00_SYS_CNTCTRL_TM0 (bit(1)) +#define AU1X00_SYS_CNTCTRL_TS (bit(0)) +#define AU1X00_SYS_WAKEMSK_M20 (bit(8)) + +#define AU1X00_MAC_CONTROL(x) (*(volatile uint32_t*)(x + 0x00)) +#define AU1X00_MAC_ADDRHIGH(x) (*(volatile uint32_t*)(x + 0x04)) +#define AU1X00_MAC_ADDRLOW(x) (*(volatile uint32_t*)(x + 0x08)) +#define AU1X00_MAC_HASHHIGH(x) (*(volatile uint32_t*)(x + 0x0c)) +#define AU1X00_MAC_HASHLOW(x) (*(volatile uint32_t*)(x + 0x10)) +#define AU1X00_MAC_MIICTRL(x) (*(volatile uint32_t*)(x + 0x14)) +#define AU1X00_MAC_MIIDATA(x) (*(volatile uint32_t*)(x + 0x18)) +#define AU1X00_MAC_FLOWCTRL(x) (*(volatile uint32_t*)(x + 0x1c)) +#define AU1X00_MAC_VLAN1(x) (*(volatile uint32_t*)(x + 0x20)) +#define AU1X00_MAC_VLAN2(x) (*(volatile uint32_t*)(x + 0x24)) +#define AU1X00_MAC_EN0 (*(volatile uint32_t*)(AU1X00_MACEN_ADDR + 0x0)) +#define AU1X00_MAC_EN1 (*(volatile uint32_t*)(AU1X00_MACEN_ADDR + 0x4)) +#define AU1X00_MAC_DMA_TX0_ADDR(x) (*(volatile uint32_t*)(x + 0x000)) +#define AU1X00_MAC_DMA_TX1_ADDR(x) (*(volatile uint32_t*)(x + 0x010)) +#define AU1X00_MAC_DMA_TX2_ADDR(x) (*(volatile uint32_t*)(x + 0x020)) +#define AU1X00_MAC_DMA_TX3_ADDR(x) (*(volatile uint32_t*)(x + 0x030)) +#define AU1X00_MAC_DMA_RX0_ADDR(x) (*(volatile uint32_t*)(x + 0x100)) +#define AU1X00_MAC_DMA_RX1_ADDR(x) (*(volatile uint32_t*)(x + 0x110)) +#define AU1X00_MAC_DMA_RX2_ADDR(x) (*(volatile uint32_t*)(x + 0x120)) +#define AU1X00_MAC_DMA_RX3_ADDR(x) (*(volatile uint32_t*)(x + 0x130)) + +typedef struct { + volatile uint32_t stat; + volatile uint32_t addr; + uint32_t _rsv0; + uint32_t _rsv1; +} au1x00_macdma_rx_t; + + +typedef struct { + volatile uint32_t stat; + volatile uint32_t addr; + volatile uint32_t len; + uint32_t _rsv0; +} au1x00_macdma_tx_t; + +#define AU1X00_MAC_CTRL_RA (bit(31)) +#define AU1X00_MAC_CTRL_EM (bit(30)) +#define AU1X00_MAC_CTRL_DO (bit(23)) +#define AU1X00_MAC_CTRL_LM(x) ((x) << 21) +#define AU1X00_MAC_CTRL_LM_NORMAL ((0) << 21) +#define AU1X00_MAC_CTRL_LM_INTERNAL ((1) << 21) +#define AU1X00_MAC_CTRL_LM_EXTERNAL ((2) << 21) +#define AU1X00_MAC_CTRL_F (bit(20)) +#define AU1X00_MAC_CTRL_PM (bit(19)) +#define AU1X00_MAC_CTRL_PR (bit(18)) +#define AU1X00_MAC_CTRL_IF (bit(17)) +#define AU1X00_MAC_CTRL_PB (bit(16)) +#define AU1X00_MAC_CTRL_HO (bit(15)) +#define AU1X00_MAC_CTRL_HP (bit(13)) +#define AU1X00_MAC_CTRL_LC (bit(12)) +#define AU1X00_MAC_CTRL_DB (bit(11)) +#define AU1X00_MAC_CTRL_DR (bit(10)) +#define AU1X00_MAC_CTRL_AP (bit(8)) +#define AU1X00_MAC_CTRL_BL(x) ((x) << 6) +#define AU1X00_MAC_CTRL_DC (bit(5)) +#define AU1X00_MAC_CTRL_TE (bit(3)) +#define AU1X00_MAC_CTRL_RE (bit(2)) + +#define AU1X00_MAC_EN_JP (bit(6)) +#define AU1X00_MAC_EN_E2 (bit(5)) +#define AU1X00_MAC_EN_E1 (bit(4)) +#define AU1X00_MAC_EN_C (bit(3)) +#define AU1X00_MAC_EN_TS (bit(2)) +#define AU1X00_MAC_EN_E0 (bit(1)) +#define AU1X00_MAC_EN_CE (bit(0)) + +#define AU1X00_MAC_ADDRHIGH_MASK (0xffff)_ +#define AU1X00_MAC_MIICTRL_PHYADDR(x) ((x & 0x1f) << 11) +#define AU1X00_MAC_MIICTRL_MIIREG(x) ((x & 0x1f) << 6) +#define AU1X00_MAC_MIICTRL_MW (bit(1)) +#define AU1X00_MAC_MIICTRL_MB (bit(0)) +#define AU1X00_MAC_MIIDATA_MASK (0xffff) +#define AU1X00_MAC_FLOWCTRL_PT(x) (((x) & 0xffff) << 16) +#define AU1X00_MAC_FLOWCTRL_PC (bit(2)) +#define AU1X00_MAC_FLOWCTRL_FE (bit(1)) +#define AU1X00_MAC_FLOWCTRL_FB (bit(0)) + +#define AU1X00_MAC_DMA_RXSTAT_MI (bit(31)) +#define AU1X00_MAC_DMA_RXSTAT_PF (bit(30)) +#define AU1X00_MAC_DMA_RXSTAT_FF (bit(29)) +#define AU1X00_MAC_DMA_RXSTAT_BF (bit(28)) +#define AU1X00_MAC_DMA_RXSTAT_MF (bit(27)) +#define AU1X00_MAC_DMA_RXSTAT_UC (bit(26)) +#define AU1X00_MAC_DMA_RXSTAT_CF (bit(25)) +#define AU1X00_MAC_DMA_RXSTAT_LE (bit(24)) +#define AU1X00_MAC_DMA_RXSTAT_V2 (bit(23)) +#define AU1X00_MAC_DMA_RXSTAT_V1 (bit(22)) +#define AU1X00_MAC_DMA_RXSTAT_CR (bit(21)) +#define AU1X00_MAC_DMA_RXSTAT_DB (bit(20)) +#define AU1X00_MAC_DMA_RXSTAT_ME (bit(19)) +#define AU1X00_MAC_DMA_RXSTAT_FT (bit(18)) +#define AU1X00_MAC_DMA_RXSTAT_CS (bit(17)) +#define AU1X00_MAC_DMA_RXSTAT_FL (bit(16)) +#define AU1X00_MAC_DMA_RXSTAT_RF (bit(15)) +#define AU1X00_MAC_DMA_RXSTAT_WT (bit(14)) +#define AU1X00_MAC_DMA_RXSTAT_LEN(x) ((x) & 0x3fff) +#define AU1X00_MAC_DMA_RXADDR_ADDR(x) ((x) & ~0x1f) +#define AU1X00_MAC_DMA_RXADDR_CB_MASK (0x3 << 0x2) +#define AU1X00_MAC_DMA_RXADDR_DN (bit(1)) +#define AU1X00_MAC_DMA_RXADDR_EN (bit(0)) + + +#define AU1X00_MAC_DMA_TXSTAT_PR (bit(31)) +#define AU1X00_MAC_DMA_TXSTAT_CC_MASK (0xf << 10) +#define AU1X00_MAC_DMA_TXSTAT_LO (bit(9)) +#define AU1X00_MAC_DMA_TXSTAT_DF (bit(8)) +#define AU1X00_MAC_DMA_TXSTAT_UR (bit(7)) +#define AU1X00_MAC_DMA_TXSTAT_EC (bit(6)) +#define AU1X00_MAC_DMA_TXSTAT_LC (bit(5)) +#define AU1X00_MAC_DMA_TXSTAT_ED (bit(4)) +#define AU1X00_MAC_DMA_TXSTAT_LS (bit(3)) +#define AU1X00_MAC_DMA_TXSTAT_NC (bit(2)) +#define AU1X00_MAC_DMA_TXSTAT_JT (bit(1)) +#define AU1X00_MAC_DMA_TXSTAT_FA (bit(0)) +#define AU1X00_MAC_DMA_TXADDR_ADDR(x) ((x) & ~0x1f) +#define AU1X00_MAC_DMA_TXADDR_CB_MASK (0x3 << 0x2) +#define AU1X00_MAC_DMA_TXADDR_DN (bit(1)) +#define AU1X00_MAC_DMA_TXADDR_EN (bit(0)) + + + +typedef struct { + volatile uint32_t rxdata; + volatile uint32_t txdata; + volatile uint32_t inten; + volatile uint32_t intcause; + volatile uint32_t fifoctrl; + volatile uint32_t linectrl; + volatile uint32_t mdmctrl; + volatile uint32_t linestat; + volatile uint32_t mdmstat; + volatile uint32_t clkdiv; + volatile uint32_t _resv[54]; + volatile uint32_t enable; +} au1x00_uart_t; + +extern au1x00_uart_t *uart0; +extern au1x00_uart_t *uart3; + +void static inline au_sync(void) +{ + __asm__ volatile ("sync"); +} + + +extern void mips_default_isr( int vector ); + +/* Generate a software interrupt */ +extern int assert_sw_irq(uint32_t irqnum); + +/* Clear a software interrupt */ +extern int negate_sw_irq(uint32_t irqnum); + +#endif diff --git a/bsps/mips/include/libcpu/isr_entries.h b/bsps/mips/include/libcpu/isr_entries.h new file mode 100644 index 0000000000..e142018be7 --- /dev/null +++ b/bsps/mips/include/libcpu/isr_entries.h @@ -0,0 +1,39 @@ +/** + * @file + * + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _ISR_ENTRIES_H +#define _ISR_ENTRIES_H 1 + +#include + +extern void mips_install_isr_entries( void ); +extern void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ); + +#if __mips == 1 +extern void exc_utlb_code(void); +extern void exc_dbg_code(void); +extern void exc_norm_code(void); +#elif __mips == 32 +extern void exc_tlb_code(void); +extern void exc_xtlb_code(void); +extern void exc_cache_code(void); +extern void exc_norm_code(void); +#elif __mips == 3 +extern void exc_tlb_code(void); +extern void exc_xtlb_code(void); +extern void exc_cache_code(void); +extern void exc_norm_code(void); +#endif + +#endif diff --git a/bsps/mips/include/libcpu/rm5231.h b/bsps/mips/include/libcpu/rm5231.h new file mode 100644 index 0000000000..c9ad3f9861 --- /dev/null +++ b/bsps/mips/include/libcpu/rm5231.h @@ -0,0 +1,19 @@ +/** + * @file + * + * MIPS RM5231 specific information + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __RM5231_h +#define __RM5231_h + +#endif diff --git a/bsps/mips/include/libcpu/tx3904.h b/bsps/mips/include/libcpu/tx3904.h new file mode 100644 index 0000000000..b573d3c7d9 --- /dev/null +++ b/bsps/mips/include/libcpu/tx3904.h @@ -0,0 +1,45 @@ +/** + * @file + * + * MIPS Tx3904 specific information + * + * NOTE: This is far from complete. --joel (13 Dec 2000) + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __TX3904_h +#define __TX3904_h + +/* + * Timer Base Addresses and Offsets + */ + +#define TX3904_TIMER0_BASE 0xFFFFF000 +#define TX3904_TIMER1_BASE 0xFFFFF100 +#define TX3904_TIMER2_BASE 0xFFFFF200 + +#define TX3904_TIMER_TCR 0x00 +#define TX3904_TIMER_TISR 0x04 +#define TX3904_TIMER_CPRA 0x08 +#define TX3904_TIMER_CPRB 0x0C +#define TX3904_TIMER_ITMR 0x10 +#define TX3904_TIMER_CCDR 0x20 +#define TX3904_TIMER_PGMR 0x30 +#define TX3904_TIMER_WTMR 0x40 +#define TX3904_TIMER_TRR 0xF0 + +#define TX3904_TIMER_READ( _base, _register ) \ + *((volatile uint32_t*)((_base) + (_register))) + +#define TX3904_TIMER_WRITE( _base, _register, _value ) \ + *((volatile uint32_t*)((_base) + (_register))) = (_value) + +#endif diff --git a/bsps/mips/include/libcpu/tx4925.h b/bsps/mips/include/libcpu/tx4925.h new file mode 100644 index 0000000000..56f58d9bf3 --- /dev/null +++ b/bsps/mips/include/libcpu/tx4925.h @@ -0,0 +1,107 @@ +/** + * @file + * + * MIPS Tx4925 specific information + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __TX4925_h +#define __TX4925_h + +#define TX4925_REG_BASE 0xFF1F0000 + + +/* + * Configuration Registers + */ +#define TX4925_CFG_CCFG 0xE000 /* Chip Configuration Register */ +#define TX4925_CFG_REVID 0xE004 /* Chip Revision ID Register */ +#define TX4925_CFG_PCFG 0xE008 /* Pin Configuration Register */ +#define TX4925_CFG_TOEA 0xE00C /* TimeOut Error Access Address Register */ +#define TX4925_CFG_PDNCTR 0xE010 /* Power Down Control Register */ +#define TX4925_CFG_GARBP 0xE018 /* GBUS Arbiter Priority Register */ +#define TX4925_CFG_TOCNT 0xE020 /* Timeout Count Register */ +#define TX4925_CFG_DRQCTR 0xE024 /* DMA Request Control Register */ +#define TX4925_CFG_CLKCTR 0xE028 /* Clock Control Register */ +#define TX4925_CFG_GARBC 0xE02C /* GBUS Arbiter Control Register */ +#define TX4925_CFG_RAMP 0xE030 /* Register Address Mapping Register */ + +/* Pin Configuration register bits */ +#define SELCHI 0x00100000 +#define SELTMR0 0x00000200 + + +/* + * Timer Registers + */ + +#define TX4925_TIMER0_BASE 0xF000 +#define TX4925_TIMER1_BASE 0xF100 +#define TX4925_TIMER2_BASE 0xF200 + +#define TX4925_TIMER_TCR 0x00 /* Timer Control Register */ +#define TX4925_TIMER_TISR 0x04 /* Timer Interrupt Status Register */ +#define TX4925_TIMER_CPRA 0x08 /* Compare Register A */ +#define TX4925_TIMER_CPRB 0x0C /* Compare Register B */ +#define TX4925_TIMER_ITMR 0x10 /* Interval Timer Mode Register */ +#define TX4925_TIMER_CCDR 0x20 /* Divide Cycle Register */ +#define TX4925_TIMER_PGMR 0x30 /* Pulse Generator Mode Register */ +#define TX4925_TIMER_WTMR 0x40 /* Reserved Register */ +#define TX4925_TIMER_TRR 0xF0 /* Timer Read Register */ + +/* ITMR register bits */ +#define TIMER_CLEAR_ENABLE_MASK 0x1 +#define TIMER_INT_ENABLE_MASK 0x8000 + +/* PGMR register bits */ +#define FFI 0x1 +#define TPIAE 0x4000 +#define TPIBE 0x8000 + +/* TISR register bits */ +#define TIIS 0x1 +#define TPIAS 0x2 +#define TPIBS 0x4 +#define TWIS 0x8 + + +/* + * Interrupt Controller Registers + */ +#define TX4925_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */ +#define TX4925_IRQCTL_DM0 0xF604 /* Interrupt Detection Mode Register 0 */ +#define TX4925_IRQCTL_DM1 0xF608 /* Interrupt Detection Mode Register 1 */ +#define TX4925_IRQCTL_LVL0 0xF610 /* Interrupt Level Register 0 */ +#define TX4925_IRQCTL_LVL1 0xF614 /* Interrupt Level Register 1 */ +#define TX4925_IRQCTL_LVL2 0xF618 /* Interrupt Level Register 2 */ +#define TX4925_IRQCTL_LVL3 0xF61C /* Interrupt Level Register 3 */ +#define TX4925_IRQCTL_LVL4 0xF620 /* Interrupt Level Register 4 */ +#define TX4925_IRQCTL_LVL5 0xF624 /* Interrupt Level Register 5 */ +#define TX4925_IRQCTL_LVL6 0xF628 /* Interrupt Level Register 6 */ +#define TX4925_IRQCTL_LVL7 0xF62C /* Interrupt Level Register 7 */ +#define TX4925_IRQCTL_MSK 0xF640 /* Interrupt Mask Register */ +#define TX4925_IRQCTL_EDC 0xF660 /* Interrupt Edge Detection Clear Register */ +#define TX4925_IRQCTL_PND 0xF680 /* Interrupt Pending Register */ +#define TX4925_IRQCTL_CS 0xF6A0 /* Interrupt Current Status Register */ +#define TX4925_IRQCTL_FLAG0 0xF510 /* Interrupt Request Flag Register 0 */ +#define TX4925_IRQCTL_FLAG1 0xF514 /* Interrupt Request Flag Register 1 */ +#define TX4925_IRQCTL_POL 0xF518 /* Interrupt Request Polarity Control Register */ +#define TX4925_IRQCTL_RCNT 0xF51C /* Interrupt Request Control Register */ +#define TX4925_IRQCTL_MASKINT 0xF520 /* Interrupt Request Internal Interrupt Mask Register */ +#define TX4925_IRQCTL_MASKEXT 0xF524 /* Interrupt Request External Interrupt Mask Register */ + +#define TX4925_REG_READ( _base, _register ) \ + *((volatile uint32_t *)((_base) + (_register))) + +#define TX4925_REG_WRITE( _base, _register, _value ) \ + *((volatile uint32_t *)((_base) + (_register))) = (_value) + +#endif diff --git a/bsps/mips/include/libcpu/tx4938.h b/bsps/mips/include/libcpu/tx4938.h new file mode 100644 index 0000000000..5005cc4149 --- /dev/null +++ b/bsps/mips/include/libcpu/tx4938.h @@ -0,0 +1,191 @@ +/** + * @file + * + * MIPS Tx4938 specific information + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __TX4938_h +#define __TX4938_h + +#define TX4938_REG_BASE 0xFF1F0000 + +/* PCI1 Registers */ +#define TX4938_PCI1_PCIID 0x7000 +#define TX4938_PCI1_PCISTATUS 0x7004 +#define TX4938_PCI1_PCICFG1 0x700c +#define TX4938_PCI1_P2GM1PLBASE 0x7018 +#define TX4938_PCI1_P2GCFG 0x7090 +#define TX4938_PCI1_PBAREQPORT 0x7100 +#define TX4938_PCI1_PBACFG 0x7104 +#define TX4938_PCI1_G2PM0GBASE 0x7120 +#define TX4938_PCI1_G2PIOGBASE 0x7138 +#define TX4938_PCI1_G2PM0MASK 0x7140 +#define TX4938_PCI1_G2PIOMASK 0x714c +#define TX4938_PCI1_G2PM0PBASE 0x7150 +#define TX4938_PCI1_G2PIOPBASE 0x7168 +#define TX4938_PCI1_PCICCFG 0x7170 +#define TX4938_PCI1_PCICSTATUS 0x7174 +#define TX4938_PCI1_P2GM1GBASE 0x7188 +#define TX4938_PCI1_G2PCFGADRS 0x71a0 +#define TX4938_PCI1_G2PCFGDATA 0x71a4 + +/* + * Configuration Registers + */ +#define TX4938_CFG_CCFG 0xE000 /* Chip Configuration Register */ +#define TX4938_CFG_REVID 0xE008 /* Chip Revision ID Register */ +#define TX4938_CFG_PCFG 0xE010 /* Pin Configuration Register */ +#define TX4938_CFG_TOEA 0xE018 /* TimeOut Error Access Address Register */ +#define TX4938_CFG_CLKCTR 0xE020 /* Clock Control Register */ +#define TX4938_CFG_GARBC 0xE030 /* GBUS Arbiter Control Register */ +#define TX4938_CFG_RAMP 0xE048 /* Register Address Mapping Register */ + +/* Pin Configuration register bits */ +#define SELCHI 0x00100000 +#define SELTMR0 0x00000200 + + +/* + * Timer Registers + */ + +#define TX4938_TIMER0_BASE 0xF000 +#define TX4938_TIMER1_BASE 0xF100 +#define TX4938_TIMER2_BASE 0xF200 + +#define TX4938_TIMER_TCR 0x00 /* Timer Control Register */ +#define TX4938_TIMER_TISR 0x04 /* Timer Interrupt Status Register */ +#define TX4938_TIMER_CPRA 0x08 /* Compare Register A */ +#define TX4938_TIMER_CPRB 0x0C /* Compare Register B */ +#define TX4938_TIMER_ITMR 0x10 /* Interval Timer Mode Register */ +#define TX4938_TIMER_CCDR 0x20 /* Divide Cycle Register */ +#define TX4938_TIMER_PGMR 0x30 /* Pulse Generator Mode Register */ +#define TX4938_TIMER_WTMR 0x40 /* Reserved Register */ +#define TX4938_TIMER_TRR 0xF0 /* Timer Read Register */ + +/* ITMR register bits */ +#define TIMER_CLEAR_ENABLE_MASK 0x1 +#define TIMER_INT_ENABLE_MASK 0x8000 + +/* PGMR register bits */ +#define FFI 0x1 +#define TPIAE 0x4000 +#define TPIBE 0x8000 + +/* TISR register bits */ +#define TIIS 0x1 +#define TPIAS 0x2 +#define TPIBS 0x4 +#define TWIS 0x8 + + +/* + * Interrupt Controller Registers + */ +#define TX4938_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */ +#define TX4938_IRQCTL_DM0 0xF604 /* Interrupt Detection Mode Register 0 */ +#define TX4938_IRQCTL_DM1 0xF608 /* Interrupt Detection Mode Register 1 */ +#define TX4938_IRQCTL_LVL0 0xF610 /* Interrupt Level Register 0 */ +#define TX4938_IRQCTL_LVL1 0xF614 /* Interrupt Level Register 1 */ +#define TX4938_IRQCTL_LVL2 0xF618 /* Interrupt Level Register 2 */ +#define TX4938_IRQCTL_LVL3 0xF61C /* Interrupt Level Register 3 */ +#define TX4938_IRQCTL_LVL4 0xF620 /* Interrupt Level Register 4 */ +#define TX4938_IRQCTL_LVL5 0xF624 /* Interrupt Level Register 5 */ +#define TX4938_IRQCTL_LVL6 0xF628 /* Interrupt Level Register 6 */ +#define TX4938_IRQCTL_LVL7 0xF62C /* Interrupt Level Register 7 */ +#define TX4938_IRQCTL_MSK 0xF640 /* Interrupt Mask Register */ +#define TX4938_IRQCTL_EDC 0xF660 /* Interrupt Edge Detection Clear Register */ +#define TX4938_IRQCTL_PND 0xF680 /* Interrupt Pending Register */ +#define TX4938_IRQCTL_CS 0xF6A0 /* Interrupt Current Status Register */ +#define TX4938_IRQCTL_FLAG0 0xF510 /* Interrupt Request Flag Register 0 */ +#define TX4938_IRQCTL_FLAG1 0xF514 /* Interrupt Request Flag Register 1 */ +#define TX4938_IRQCTL_POL 0xF518 /* Interrupt Request Polarity Control Register */ +#define TX4938_IRQCTL_RCNT 0xF51C /* Interrupt Request Control Register */ +#define TX4938_IRQCTL_MASKINT 0xF520 /* Interrupt Request Internal Interrupt Mask Register */ +#define TX4938_IRQCTL_MASKEXT 0xF524 /* Interrupt Request External Interrupt Mask Register */ + +#define TX4938_REG_READ( _base, _register ) \ + *((volatile uint32_t *)((_base) + (_register))) + +#define TX4938_REG_WRITE( _base, _register, _value ) \ + *((volatile uint32_t *)((_base) + (_register))) = (_value) + +/************************************************************************ + * TX49 Register field encodings +*************************************************************************/ +/******** reg: CCFG ********/ +/* field: PCIDIVMODE */ +#define TX4938_CCFG_SYSSP_SHF 6 +#define TX4938_CCFG_SYSSP_MSK (MSK(2) << TX4938_CCFG_SYSSP_SHF) + +/* field: PCI1DMD */ +#define TX4938_CCFG_PCI1DMD_SHF 8 +#define TX4938_CCFG_PCI1DMD_MSK (MSK(1) << TX4938_CCFG_PCI1DMD_SHF) + +/* field: PCIDIVMODE */ +#define TX4938_CCFG_PCIDIVMODE_SHF 10 +#define TX4938_CCFG_PCIDIVMODE_MSK (MSK(3) << TX4938_CCFG_PCIDIVMODE_SHF) + +/* field: PCI1-66 */ +#define TX4938_CCFG_PCI166_SHF 21 +#define TX4938_CCFG_PCI166_MSK ((UINT64)MSK(1) << TX4938_CCFG_PCI166_SHF) + +/* field: PCIMODE */ +#define TX4938_CCFG_PCIMODE_SHF 22 +#define TX4938_CCFG_PCIMODE_MSK ((UINT64)MSK(1) << TX4938_CCFG_PCIMODE_SHF) + +/* field: BRDTY */ +#define TX4938_CCFG_BRDTY_SHF 36 +#define TX4938_CCFG_RRDTY_MSK ((UINT64)MSK(4) << TX4938_CCFG_BRDTY_SHF) + +/* field: BRDRV */ +#define TX4938_CCFG_BRDRV_SHF 32 +#define TX4938_CCFG_BRDRV_MSK ((UINT64)MSK(4) << TX4938_CCFG_BRDRV_SHF) + +/******** reg: CLKCTR ********/ +/* field: PCIC1RST */ +#define TX4938_CLKCTR_PCIC1RST_SHF 11 +#define TX4938_CLKCTR_PCIC1RST_MSK (MSK(1) << TX4938_CLKCTR_PCIC1RST_SHF) + +/******** reg: PCISTATUS ********/ +/* field: MEMSP */ +#define TX4938_PCI_PCISTATUS_MEMSP_SHF 1 +#define TX4938_PCI_PCISTATUS_MEMSP_MSK (MSK(1) << TX4938_PCI_PCISTATUS_MEMSP_SHF) + +/* field: BM */ +#define TX4938_PCI_PCISTATUS_BM_SHF 2 +#define TX4938_PCI_PCISTATUS_BM_MSK (MSK(1) << TX4938_PCI_PCISTATUS_BM_SHF) + +/******** reg: PBACFG ********/ +/* field: RPBA */ +#define TX4938_PCI_PBACFG_RPBA_SHF 2 +#define TX4938_PCI_PBACFG_RPBA_MSK (MSK(1) << TX4938_PCI_PBACFG_RPBA_SHF) + +/* field: PBAEN */ +#define TX4938_PCI_PBACFG_PBAEN_SHF 1 +#define TX4938_PCI_PBACFG_PBAEN_MSK (MSK(1) << TX4938_PCI_PBACFG_PBAEN_SHF) + +/******** reg: PCICFG ********/ +/* field: G2PM0EN */ +#define TX4938_PCI_PCICFG_G2PM0EN_SHF 6 +#define TX4938_PCI_PCICFG_G2PM0EN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PM0EN_SHF) + +/* field: G2PIOEN */ +#define TX4938_PCI_PCICFG_G2PIOEN_SHF 5 +#define TX4938_PCI_PCICFG_G2PIOEN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PIOEN_SHF) + +/* field: TCAR */ +#define TX4938_PCI_PCICFG_TCAR_SHF 4 +#define TX4938_PCI_PCICFG_TCAR_MSK (MSK(1) << TX4938_PCI_PCICFG_TCAR_SHF) + + +#endif diff --git a/bsps/mips/jmr3904/headers.am b/bsps/mips/jmr3904/headers.am new file mode 100644 index 0000000000..b7adec7f52 --- /dev/null +++ b/bsps/mips/jmr3904/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/mips/jmr3904/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/mips/jmr3904/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/mips/jmr3904/include/bsp/irq.h diff --git a/bsps/mips/jmr3904/include/bsp.h b/bsps/mips/jmr3904/include/bsp.h new file mode 100644 index 0000000000..52696b3987 --- /dev/null +++ b/bsps/mips/jmr3904/include/bsp.h @@ -0,0 +1,37 @@ +/** + * @file + * + * This include file contains some definitions specific to the + * JMR3904 simulator in gdb. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_JMR3904_BSP_H +#define LIBBSP_MIPS_JMR3904_BSP_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION +#define BSP_SHARED_HANDLER_SUPPORT 1 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/mips/jmr3904/include/bsp/irq.h b/bsps/mips/jmr3904/include/bsp/irq.h new file mode 100644 index 0000000000..cdb50e244e --- /dev/null +++ b/bsps/mips/jmr3904/include/bsp/irq.h @@ -0,0 +1,68 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief jmr3904 interrupt definitions. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_JMR3904_IRQ_H +#define LIBBSP_MIPS_JMR3904_IRQ_H + +#ifndef ASM + #include + #include + #include + #include +#endif + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +/* + * Interrupt Vector Numbers + * + * NOTE: Numbers 0-15 directly map to levels on the IRC. + * Number 16 is "1xxxx" per p. 164 of the TX3904 manual. + */ + + #define TX3904_IRQ_INT1 MIPS_INTERRUPT_BASE+0 + #define TX3904_IRQ_INT2 MIPS_INTERRUPT_BASE+1 + #define TX3904_IRQ_INT3 MIPS_INTERRUPT_BASE+2 + #define TX3904_IRQ_INT4 MIPS_INTERRUPT_BASE+3 + #define TX3904_IRQ_INT5 MIPS_INTERRUPT_BASE+4 + #define TX3904_IRQ_INT6 MIPS_INTERRUPT_BASE+5 + #define TX3904_IRQ_INT7 MIPS_INTERRUPT_BASE+6 + #define TX3904_IRQ_DMAC3 MIPS_INTERRUPT_BASE+7 + #define TX3904_IRQ_DMAC2 MIPS_INTERRUPT_BASE+8 + #define TX3904_IRQ_DMAC1 MIPS_INTERRUPT_BASE+9 + #define TX3904_IRQ_DMAC0 MIPS_INTERRUPT_BASE+10 + #define TX3904_IRQ_SIO0 MIPS_INTERRUPT_BASE+11 + #define TX3904_IRQ_SIO1 MIPS_INTERRUPT_BASE+12 + #define TX3904_IRQ_TMR0 MIPS_INTERRUPT_BASE+13 + #define TX3904_IRQ_TMR1 MIPS_INTERRUPT_BASE+14 + #define TX3904_IRQ_TMR2 MIPS_INTERRUPT_BASE+15 + #define TX3904_IRQ_INT0 MIPS_INTERRUPT_BASE+16 + #define TX3904_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+17 + #define TX3904_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+18 + #define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19 + +#define BSP_INTERRUPT_VECTOR_MAX TX3904_MAXIMUM_VECTORS + +/** @} */ + +#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */ diff --git a/bsps/mips/jmr3904/include/tm27.h b/bsps/mips/jmr3904/include/tm27.h new file mode 100644 index 0000000000..f73ccdea40 --- /dev/null +++ b/bsps/mips/jmr3904/include/tm27.h @@ -0,0 +1,52 @@ +/** + * @file + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + */ + +#include + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + rtems_interrupt_handler_install( \ + TX3904_IRQ_TMR0, "benchmark", 0, \ + (rtems_interrupt_handler)handler, NULL ); + +#define Cause_tm27_intr() \ + do { \ + uint32_t _clicks = 20; \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR, 0xC0 ); \ + *((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \ + } while(0) + +#define Clear_tm27_intr() \ + do { \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \ + } while(0) + +#define Lower_tm27_intr() \ + mips_enable_in_interrupt_mask( 0xff01 ); + +#endif diff --git a/bsps/mips/malta/headers.am b/bsps/mips/malta/headers.am new file mode 100644 index 0000000000..35d8bb70d0 --- /dev/null +++ b/bsps/mips/malta/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/mips/malta/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/mips/malta/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/mips/malta/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/mips/malta/include/bsp/pci.h diff --git a/bsps/mips/malta/include/bsp.h b/bsps/mips/malta/include/bsp.h new file mode 100644 index 0000000000..c1169cd0a4 --- /dev/null +++ b/bsps/mips/malta/include/bsp.h @@ -0,0 +1,113 @@ +/** + * @file + * + * This include file contains some definitions specific to the + * MIPS Malta Board. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_MALTA_BSP_H +#define LIBBSP_MIPS_MALTA_BSP_H + +#ifndef ASM + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION +#define BSP_SHARED_HANDLER_SUPPORT 1 + +#define REVISION_REGISTER_ADDRESS 0x1fc00010 +#define PRORV_MASK 0x0000000f /* 4 bit Product Revision */ +#define PROID_MASK 0x000000f0 /* 4 bit Product ID */ +#define CORRV_MASK 0x00000300 /* 2 bit Core Board Revision */ +#define CORID_MASK 0x0000fc00 /* 6 bit Core Board ID */ +#define FPGRV_MASK 0x00ff0000 /* 8 bit CBUS FPGA Revision */ +#define BSP_8259_BASE_ADDRESS (0x18000000UL | 0xa0000000UL) +#define BSP_PCI_BASE_ADDRESS (0x1be00000UL | 0xa0000000UL) +#define BSP_NIC_IO_BASE (0x10000000UL | 0xa0000000UL) +#define PCI0_IO_BASE (0x18000000UL | 0xa0000000UL) +#define BSP_NIC_MEM_BASE (0x00000000UL | 0xa0000000UL) + +/* functions */ +#define WRITE_PROTECTED_UINT8( _addr, _value ) \ + do { \ + volatile uint8_t *_ptr = _addr | 0x80000000; \ + *_ptr = _value; \ + } +#define WRITE_PROTECTED_UINT16( _addr, _value ) \ + do { \ + volatile uint16_t *_ptr = _addr | 0x80000000; \ + *_ptr = _value; \ + } +#define WRITE_PROTECTED_UINT32( _addr, _value ) \ + do { \ + volatile uint32_t *_ptr = _addr | 0x80000000; \ + *_ptr = _value; \ + } +#define READ_PROTECTED_UINT8( _addr, _value ) \ + do { \ + volatile uint8_t *_ptr = _addr | 0x80000000; \ + _value = *_ptr; \ + } +#define READ_PROTECTED_UINT16( _addr, _value ) \ + do { \ + volatile uint16_t *_ptr = _addr | 0x80000000; \ + _value = *_ptr; \ + } +#define READ_PROTECTED_UINT32( _addr, _value ) \ + do { \ + volatile uint32_t *_ptr = _addr | 0x80000000; \ + _value = *_ptr; \ + } + +#define READ_UINT8( _register_, _value_ ) \ + ((_value_) = *((volatile unsigned char *)(_register_))) + +#define WRITE_UINT8( _register_, _value_ ) \ + (*((volatile unsigned char *)(_register_)) = (_value_)) + +#define READ_UINT16( _register_, _value_ ) \ + ((_value_) = *((volatile unsigned short *)(_register_))) + +#define WRITE_UINT16( _register_, _value_ ) \ + (*((volatile unsigned short *)(_register_)) = (_value_)) + +void simple_out_32(uint32_t base, uint32_t addr, uint32_t val); +void simple_out_le32(uint32_t base, uint32_t addr, uint32_t val); +uint8_t simple_in_8( uint32_t base, uint32_t addr ); +void simple_out_8( uint32_t base, uint32_t addr, uint8_t val ); +int16_t simple_in_le16( uint32_t base, uint32_t addr ); +int16_t simple_in_16( uint32_t base, uint32_t addr ); +uint32_t simple_in_le32( uint32_t base, uint32_t addr ); +uint32_t simple_in_32( uint32_t base, uint32_t addr ); +void simple_out_le16( uint32_t base, uint32_t addr, uint16_t val ); +void simple_out_16( uint32_t base, uint32_t addr, uint16_t val ); + +/* + * Prototypes for methods called from .S for dependency tracking + */ +void init_tlb(void); +void resettlb(int i); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/mips/malta/include/bsp/irq.h b/bsps/mips/malta/include/bsp/irq.h new file mode 100644 index 0000000000..3ca6f964a9 --- /dev/null +++ b/bsps/mips/malta/include/bsp/irq.h @@ -0,0 +1,131 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief Malta Interrupt Definitions + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_MALTA_IRQ_H +#define LIBBSP_MIPS_MALTA_IRQ_H + +#ifndef ASM + #include + #include + #include + #include +#endif + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +/* + * Interrupt Vector Numbers + * + * NOTE: Numbers 0-15 directly map to levels on the IRC. + * Number 16 is "1xxxx" per p. 164 of the TX3904 manual. + */ +#define MALTA_CPU_INT_START MIPS_INTERRUPT_BASE+0 +#define MALTA_CPU_INT_SW0 MALTA_CPU_INT_START+0 +#define MALTA_CPU_INT_SW2 MALTA_CPU_INT_START+1 +#define MALTA_CPU_INT0 MALTA_CPU_INT_START+2 +#define MALTA_CPU_INT1 MALTA_CPU_INT_START+3 +#define MALTA_CPU_INT2 MALTA_CPU_INT_START+4 +#define MALTA_CPU_INT3 MALTA_CPU_INT_START+5 +#define MALTA_CPU_INT4 MALTA_CPU_INT_START+6 +#define MALTA_CPU_INT5 MALTA_CPU_INT_START+7 +#define MALTA_CPU_INT_LAST MALTA_CPU_INT5 + +#define MALTA_SB_IRQ_START MALTA_CPU_INT_LAST+1 +#define MALTA_SB_IRQ_0 MALTA_SB_IRQ_START+0 +#define MALTA_SB_IRQ_1 MALTA_SB_IRQ_START+1 +#define MALTA_SB_IRQ_2 MALTA_SB_IRQ_START+2 +#define MALTA_SB_IRQ_3 MALTA_SB_IRQ_START+3 +#define MALTA_SB_IRQ_4 MALTA_SB_IRQ_START+4 +#define MALTA_SB_IRQ_5 MALTA_SB_IRQ_START+5 +#define MALTA_SB_IRQ_6 MALTA_SB_IRQ_START+6 +#define MALTA_SB_IRQ_7 MALTA_SB_IRQ_START+7 +#define MALTA_SB_IRQ_8 MALTA_SB_IRQ_START+8 +#define MALTA_SB_IRQ_9 MALTA_SB_IRQ_START+9 +#define MALTA_SB_IRQ_10 MALTA_SB_IRQ_START+10 +#define MALTA_SB_IRQ_11 MALTA_SB_IRQ_START+11 +#define MALTA_SB_IRQ_12 MALTA_SB_IRQ_START+12 +#define MALTA_SB_IRQ_13 MALTA_SB_IRQ_START+13 +#define MALTA_SB_IRQ_14 MALTA_SB_IRQ_START+14 +#define MALTA_SB_IRQ_15 MALTA_SB_IRQ_START+15 +#define MALTA_SB_IRQ_LAST MALTA_SB_IRQ_15 + +#define MALTA_PCI_ADP_START MALTA_SB_IRQ_LAST+1 +#define MALTA_PCI_ADP20 MALTA_PCI_ADP_START+0 +#define MALTA_PCI_ADP21 MALTA_PCI_ADP_START+1 +#define MALTA_PCI_ADP22 MALTA_PCI_ADP_START+2 +#define MALTA_PCI_ADP27 MALTA_PCI_ADP_START+3 +#define MALTA_PCI_ADP28 MALTA_PCI_ADP_START+4 +#define MALTA_PCI_ADP29 MALTA_PCI_ADP_START+5 +#define MALTA_PCI_ADP30 MALTA_PCI_ADP_START+6 +#define MALTA_PCI_ADP31 MALTA_PCI_ADP_START+7 +#define MALTA_PCI_ADP_LAST MALTA_PCI_ADP31 +# + +#define BSP_INTERRUPT_VECTOR_MAX MALTA_PCI_ADP_LAST + +/* + * Redefine interrupts with more descriptive names. + * The Generic ones above match the hardware name, + * where these match the device name. + */ +#define MALTA_INT_SOUTHBRIDGE_INTR MALTA_CPU_INT0 +#define MALTA_INT_SOUTHBRIDGE_SMI MALTA_CPU_INT1 +#define MALTA_INT_TTY2 MALTA_CPU_INT2 +#define MALTA_INT_COREHI MALTA_CPU_INT3 +#define MALTA_INT_CORELO MALTA_CPU_INT4 +#define MALTA_INT_TICKER MALTA_CPU_INT5 + +#define MALTA_IRQ_TIMER_SOUTH_BRIDGE MALTA_SB_IRQ_0 +#define MALTA_IRQ_KEYBOARD_SUPERIO MALTA_SB_IRQ_1 +#define MALTA_IRQ_RESERVED1_SOUTH_BRIDGE MALTA_SB_IRQ_2 +#define MALTA_IRQ_TTY1 MALTA_SB_IRQ_3 +#define MALTA_IRQ_TTY0 MALTA_SB_IRQ_4 +#define MALTA_IRQ_NOT_USED MALTA_SB_IRQ_5 +#define MALTA_IRQ_FLOPPY_SUPERIO MALTA_SB_IRQ_6 +#define MALTA_IRQ_PARALLEL_PORT_SUPERIO MALTA_SB_IRQ_7 +#define MALTA_IRQ_REALTIME_CLOCK_SOUTH_BRIDGE MALTA_SB_IRQ_8 +#define MALTA_IRQ_I2C_SOUTH_BRIDGE MALTA_SB_IRQ_9 +/* PCI A, PCI B (including Ethernet) PCI slot 1..4, Ethernet */ +#define MALTA_IRQ_PCI_A_B MALTA_SB_IRQ_10 +/* PCI slot 1..4 (audio, USB) */ +#define MALTA_IRQ_PCI_C_D MALTA_SB_IRQ_11 +#define MALTA_IRQ_MOUSE_SUPERIO MALTA_SB_IRQ_12 +#define MALTA_IRQ_RESERVED2_SOUTH_BRIDGE MALTA_SB_IRQ_13 +#define MALTA_IRQ_PRIMARY_IDE MALTA_SB_IRQ_14 +#define MALTA_IRQ_SECONDARY_IDE MALTA_SB_IRQ_15 +#define MALTA_IRQ_SOUTH_BRIDGE MALTA_PCI_ADP20 +#define MALTA_IRQ_ETHERNET MALTA_IRQ_PCI_A_B +#define MALTA_IRQ_AUDIO MALTA_PCI_ADP22 +#define MALTA_IRQ_CORE_CARD MALTA_PCI_ADP27 +#define MALTA_IRQ_PCI_CONNECTOR_1 MALTA_PCI_ADP28 +#define MALTA_IRQ_PCI_CONNECTOR_2 MALTA_PCI_ADP29 +#define MALTA_IRQ_PCI_CONNECTOR_3 MALTA_PCI_ADP30 +#define MALTA_IRQ_PCI_CONNECTOR_4 MALTA_PCI_ADP31 + +#ifndef ASM + +#endif /* ASM */ + +/** @} */ + +#endif /* LIBBSP_MIPS_MALTA_IRQ_H */ diff --git a/bsps/mips/malta/include/bsp/pci.h b/bsps/mips/malta/include/bsp/pci.h new file mode 100644 index 0000000000..c5944da548 --- /dev/null +++ b/bsps/mips/malta/include/bsp/pci.h @@ -0,0 +1,139 @@ +/** + * @file + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* + * + * PCI defines and function prototypes + * Copyright 1994, Drew Eckhardt + * Copyright 1997, 1998 Martin Mares + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI BIOS Specification + * PCI Local Bus Specification + * PCI to PCI Bridge Specification + * PCI System Design Guide + */ + +#ifndef BSP_PCI_H +#define BSP_PCI_H + +#include +#include +#include + +struct _pin_routes +{ + int pin, int_name[4]; +}; +struct _int_map +{ + int bus, slot, opts; + struct _pin_routes pin_route[5]; +}; +struct pcibridge +{ + int bus; + int slot; +}; + +/* If there's a conflict between a name in the routing table and + * what's already set on the device, reprogram the device setting + * to reflect int_name[0] for the routing table entry + */ +#define PCI_FIXUP_OPT_OVERRIDE_NAME (1<<0) + +void FixupPCI( const struct _int_map *, int (*swizzler)(int,int) ); + +/* FIXME: This probably belongs into rtems/pci.h */ +extern unsigned char pci_bus_count(); + +int indirect_pci_read_config_byte( + unsigned char bus, + unsigned char slot, + unsigned char function, + unsigned char offset, + uint8_t *val +); + +int indirect_pci_read_config_word( + unsigned char bus, + unsigned char slot, + unsigned char function, + unsigned char offset, + uint16_t *val +); + +int indirect_pci_read_config_dword( + unsigned char bus, + unsigned char slot, + unsigned char function, + unsigned char offset, + uint32_t *val +); + +int indirect_pci_write_config_byte( + unsigned char bus, + unsigned char slot, + unsigned char function, + unsigned char offset, + uint8_t val +); + +int indirect_pci_write_config_word( + unsigned char bus, + unsigned char slot, + unsigned char function, + unsigned char offset, + uint16_t val +); + +int indirect_pci_write_config_dword( + unsigned char bus, + unsigned char slot, + unsigned char function, + unsigned char offset, + uint32_t val +); + +/* Can these be moved to the rtems pci.h? */ +int FindPCIbridge( int mybus, struct pcibridge *pb ); + +const pci_config_access_functions pci_indirect_functions; + +void pci_out_le32( uint32_t base, uint32_t addr, uint32_t val); +void pci_out_32( uint32_t base, uint32_t addr, uint32_t val); +uint8_t pci_in_8 ( uint32_t base, uint32_t addr ); +int16_t pci_in_le16 ( uint32_t base, uint32_t addr ); +uint32_t pci_in_le32 ( uint32_t base, uint32_t addr ); +int16_t pci_in_16 ( uint32_t base, uint32_t addr ); +uint32_t pci_in_32 ( uint32_t base, uint32_t addr ); +void pci_out_8 ( uint32_t base, uint32_t addr, uint8_t val ); +void pci_out_le16( uint32_t base, uint32_t addr, uint16_t val ); +void pci_out_16( uint32_t base, uint32_t addr, uint16_t val ); +void pci_out_32 ( uint32_t base, uint32_t addr, uint32_t val); + +#define out_32(_addr, _val) pci_out_32(BSP_PCI_BASE_ADDRESS, _addr, _val) +#define out_le32(_addr, _val) pci_out_le32(BSP_PCI_BASE_ADDRESS, _addr, _val) +#define out_32(_addr, _val) pci_out_32(BSP_PCI_BASE_ADDRESS, _addr, _val) +#define in_8(_addr) pci_in_8( BSP_PCI_BASE_ADDRESS, _addr ) +#define in_le16(_addr) pci_in_le16( BSP_PCI_BASE_ADDRESS, _addr ) +#define in_le32(_addr) pci_in_le32( BSP_PCI_BASE_ADDRESS, _addr ) +#define in_16(_addr) pci_in_16( BSP_PCI_BASE_ADDRESS, _addr ) +#define in_32(_addr) pci_in_32( BSP_PCI_BASE_ADDRESS, _addr ) +#define out_8(_addr,_val) pci_out_8( BSP_PCI_BASE_ADDRESS, _addr, _val ) +#define out_le16(_addr,_val) pci_out_le16( BSP_PCI_BASE_ADDRESS, _addr, _val ) +#define out_16(_addr,_val) pci_out_16( BSP_PCI_BASE_ADDRESS, _addr, _val ) + +#endif /* BSP_PCI_H */ diff --git a/bsps/mips/malta/include/tm27.h b/bsps/mips/malta/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/mips/malta/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/mips/rbtx4925/headers.am b/bsps/mips/rbtx4925/headers.am new file mode 100644 index 0000000000..eaffa3e5d8 --- /dev/null +++ b/bsps/mips/rbtx4925/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/mips/rbtx4925/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/mips/rbtx4925/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/mips/rbtx4925/include/bsp/irq.h diff --git a/bsps/mips/rbtx4925/include/bsp.h b/bsps/mips/rbtx4925/include/bsp.h new file mode 100644 index 0000000000..ef5d6ef07f --- /dev/null +++ b/bsps/mips/rbtx4925/include/bsp.h @@ -0,0 +1,46 @@ +/** + * @file + * + * This include file contains some definitions specific to the RBTX4925. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_RBTX4925_BSP_H +#define LIBBSP_MIPS_RBTX4925_BSP_H + +#ifndef ASM + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION +#define BSP_SHARED_HANDLER_SUPPORT 1 + +/* + * Prototypes for methods called from .S for dependency tracking + */ +void init_tlb(void); +void resettlb(int i); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/mips/rbtx4925/include/bsp/irq.h b/bsps/mips/rbtx4925/include/bsp/irq.h new file mode 100644 index 0000000000..d3987b2d39 --- /dev/null +++ b/bsps/mips/rbtx4925/include/bsp/irq.h @@ -0,0 +1,80 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief interrupt definitions. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_TX4925_IRQ_H +#define LIBBSP_MIPS_TX4925_IRQ_H + +#ifndef ASM + #include + #include + #include + #include +#endif + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +/* + * Interrupt Vector Numbers + * + */ +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define TX4925_IRQ_RSV1 MIPS_INTERRUPT_BASE+0 +#define TX4925_IRQ_WTE MIPS_INTERRUPT_BASE+1 +#define TX4925_IRQ_INT0 MIPS_INTERRUPT_BASE+2 +#define TX4925_IRQ_INT1 MIPS_INTERRUPT_BASE+3 +#define TX4925_IRQ_INT2 MIPS_INTERRUPT_BASE+4 +#define TX4925_IRQ_INT3 MIPS_INTERRUPT_BASE+5 +#define TX4925_IRQ_INT4 MIPS_INTERRUPT_BASE+6 +#define TX4925_IRQ_INT5 MIPS_INTERRUPT_BASE+7 +#define TX4925_IRQ_INT6 MIPS_INTERRUPT_BASE+8 +#define TX4925_IRQ_INT7 MIPS_INTERRUPT_BASE+9 +#define TX4925_IRQ_RSV2 MIPS_INTERRUPT_BASE+10 +#define TX4925_IRQ_NAND MIPS_INTERRUPT_BASE+11 +#define TX4925_IRQ_SIO0 MIPS_INTERRUPT_BASE+12 +#define TX4925_IRQ_SIO1 MIPS_INTERRUPT_BASE+13 +#define TX4925_IRQ_DMAC0 MIPS_INTERRUPT_BASE+14 +#define TX4925_IRQ_DMAC1 MIPS_INTERRUPT_BASE+15 +#define TX4925_IRQ_DMAC2 MIPS_INTERRUPT_BASE+16 +#define TX4925_IRQ_DMAC3 MIPS_INTERRUPT_BASE+17 +#define TX4925_IRQ_IRC MIPS_INTERRUPT_BASE+18 +#define TX4925_IRQ_PDMAC MIPS_INTERRUPT_BASE+19 +#define TX4925_IRQ_PCIC MIPS_INTERRUPT_BASE+20 +#define TX4925_IRQ_TMR0 MIPS_INTERRUPT_BASE+21 +#define TX4925_IRQ_TMR1 MIPS_INTERRUPT_BASE+22 +#define TX4925_IRQ_TMR2 MIPS_INTERRUPT_BASE+23 +#define TX4925_IRQ_SPI MIPS_INTERRUPT_BASE+24 +#define TX4925_IRQ_RTC MIPS_INTERRUPT_BASE+25 +#define TX4925_IRQ_ACLC MIPS_INTERRUPT_BASE+26 +#define TX4925_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27 +#define TX4925_IRQ_CHI MIPS_INTERRUPT_BASE+28 +#define TX4925_IRQ_PCIERR MIPS_INTERRUPT_BASE+29 +#define TX4925_IRQ_PCIPME MIPS_INTERRUPT_BASE+30 +#define TX4925_IRQ_RSV3 MIPS_INTERRUPT_BASE+31 + +#define TX4925_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32 +#define TX4925_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33 +#define TX4925_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34 + +#define BSP_INTERRUPT_VECTOR_MAX TX4925_MAXIMUM_VECTORS + +/** @} */ + +#endif /* LIBBSP_MIPS_ TX4925_IRQ_H */ diff --git a/bsps/mips/rbtx4925/include/tm27.h b/bsps/mips/rbtx4925/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/mips/rbtx4925/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/mips/rbtx4938/headers.am b/bsps/mips/rbtx4938/headers.am new file mode 100644 index 0000000000..51360cf6ae --- /dev/null +++ b/bsps/mips/rbtx4938/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/mips/rbtx4938/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/mips/rbtx4938/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/mips/rbtx4938/include/bsp/irq.h diff --git a/bsps/mips/rbtx4938/include/bsp.h b/bsps/mips/rbtx4938/include/bsp.h new file mode 100644 index 0000000000..b57a60f2df --- /dev/null +++ b/bsps/mips/rbtx4938/include/bsp.h @@ -0,0 +1,46 @@ +/** + * @file + * + * This include file contains some definitions specific to the RBTX4938. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_RBTX4938_BSP_H +#define LIBBSP_MIPS_RBTX4938_BSP_H + +#ifndef ASM + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION +#define BSP_SHARED_HANDLER_SUPPORT 1 + +/* + * Prototypes for methods called from .S for dependency tracking + */ +void init_tlb(void); +void resettlb(int i); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/mips/rbtx4938/include/bsp/irq.h b/bsps/mips/rbtx4938/include/bsp/irq.h new file mode 100644 index 0000000000..bb18dcf86d --- /dev/null +++ b/bsps/mips/rbtx4938/include/bsp/irq.h @@ -0,0 +1,80 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief interrupt definitions. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_TX4938_IRQ_H +#define LIBBSP_MIPS_TX4938_IRQ_H + +#ifndef ASM + #include + #include + #include + #include +#endif + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +/* + * Interrupt Vector Numbers + * + */ +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define TX4938_IRQ_ECC MIPS_INTERRUPT_BASE+0 +#define TX4938_IRQ_WTE MIPS_INTERRUPT_BASE+1 +#define TX4938_IRQ_INT0 MIPS_INTERRUPT_BASE+2 +#define TX4938_IRQ_INT1 MIPS_INTERRUPT_BASE+3 +#define TX4938_IRQ_INT2 MIPS_INTERRUPT_BASE+4 +#define TX4938_IRQ_INT3 MIPS_INTERRUPT_BASE+5 +#define TX4938_IRQ_INT4 MIPS_INTERRUPT_BASE+6 +#define TX4938_IRQ_INT5 MIPS_INTERRUPT_BASE+7 +#define TX4938_IRQ_SIO0 MIPS_INTERRUPT_BASE+8 +#define TX4938_IRQ_SIO1 MIPS_INTERRUPT_BASE+9 +#define TX4938_IRQ_DMAC00 MIPS_INTERRUPT_BASE+10 +#define TX4938_IRQ_DMAC01 MIPS_INTERRUPT_BASE+11 +#define TX4938_IRQ_DMAC02 MIPS_INTERRUPT_BASE+12 +#define TX4938_IRQ_DMAC03 MIPS_INTERRUPT_BASE+13 +#define TX4938_IRQ_IRC MIPS_INTERRUPT_BASE+14 +#define TX4938_IRQ_PDMAC MIPS_INTERRUPT_BASE+15 +#define TX4938_IRQ_PCIC MIPS_INTERRUPT_BASE+16 +#define TX4938_IRQ_TMR0 MIPS_INTERRUPT_BASE+17 +#define TX4938_IRQ_TMR1 MIPS_INTERRUPT_BASE+18 +#define TX4938_IRQ_TMR2 MIPS_INTERRUPT_BASE+19 +#define TX4938_IRQ_RSV1 MIPS_INTERRUPT_BASE+20 +#define TX4938_IRQ_NDFMC MIPS_INTERRUPT_BASE+21 +#define TX4938_IRQ_PCIERR MIPS_INTERRUPT_BASE+22 +#define TX4938_IRQ_PCIPMC MIPS_INTERRUPT_BASE+23 +#define TX4938_IRQ_ACLC MIPS_INTERRUPT_BASE+24 +#define TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+25 +#define TX4938_IRQ_PCIC1NT MIPS_INTERRUPT_BASE+26 +#define TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27 +#define TX4938_IRQ_DMAC10 MIPS_INTERRUPT_BASE+28 +#define TX4938_IRQ_DMAC11 MIPS_INTERRUPT_BASE+29 +#define TX4938_IRQ_DMAC12 MIPS_INTERRUPT_BASE+30 +#define TX4938_IRQ_DMAC13 MIPS_INTERRUPT_BASE+31 + +#define TX4938_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32 +#define TX4938_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33 +#define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34 + +#define BSP_INTERRUPT_VECTOR_MAX TX4938_MAXIMUM_VECTORS + +/** @} */ + +#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */ diff --git a/bsps/mips/rbtx4938/include/tm27.h b/bsps/mips/rbtx4938/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/mips/rbtx4938/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/moxie/moxiesim/headers.am b/bsps/moxie/moxiesim/headers.am new file mode 100644 index 0000000000..5f900bdcc3 --- /dev/null +++ b/bsps/moxie/moxiesim/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/moxie/moxiesim/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/moxie/moxiesim/include/tm27.h diff --git a/bsps/moxie/moxiesim/include/bsp.h b/bsps/moxie/moxiesim/include/bsp.h new file mode 100644 index 0000000000..276693c97a --- /dev/null +++ b/bsps/moxie/moxiesim/include/bsp.h @@ -0,0 +1,35 @@ +/* + * This include file contains some definitions specific to the + * moxie simulator in gdb. + */ + +/* + * COPYRIGHT (c) 1989-1999, 2010, 2014. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MOXIE_MOXIESIM_BSP_H +#define LIBBSP_MOXIE_MOXIESIM_BSP_H + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* support for simulated clock tick */ +void *clock_driver_sim_idle_body(uintptr_t); +#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/moxie/moxiesim/include/tm27.h b/bsps/moxie/moxiesim/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/moxie/moxiesim/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/nios2/nios2_iss/headers.am b/bsps/nios2/nios2_iss/headers.am new file mode 100644 index 0000000000..522f74c0a9 --- /dev/null +++ b/bsps/nios2/nios2_iss/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/nios2/nios2_iss/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/nios2/nios2_iss/include/tm27.h diff --git a/bsps/nios2/nios2_iss/include/bsp.h b/bsps/nios2/nios2_iss/include/bsp.h new file mode 100644 index 0000000000..3883e39ab6 --- /dev/null +++ b/bsps/nios2/nios2_iss/include/bsp.h @@ -0,0 +1,130 @@ +/* bsp.h + * + * This include file contains all board IO definitions. + * + * XXX : put yours in here + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_NIOS2_NIOS2_ISS_BSP_H +#define LIBBSP_NIOS2_NIOS2_ISS_BSP_H + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* ============================================ */ + +/* SOPC-specific Constants */ + +#define SYSTEM_BUS_WIDTH 32 + +#define JTAG_UART_BASE 0x08000000 +#define JTAG_UART_IRQ 2 + +#define CLOCK_BASE 0x08001000 +#define CLOCK_FREQ 50000000 +#define CLOCK_VECTOR 1 + +#define TIMER_BASE 0x08002000 +#define TIMER_FREQ 50000000 +#define TIMER_VECTOR 3 + +/* ============================================ */ + +#define NIOS2_BYPASS_CACHE ((uint32_t)0x80000000ul) +#define NIOS2_IO_BASE(x) ( (void*) ((uint32_t)x | NIOS2_BYPASS_CACHE ) ) +#define NIOS2_IENABLE(x) do{ __builtin_wrctl(3,__builtin_rdctl(3)|x);}while(0) +#define NIOS2_IRQ_ENABLE(x) do {__builtin_wrctl(3,__builtin_rdctl(3)|x);} while(0) + +/* ============================================ */ +/* TODO: Put this in an external header file */ + +#ifndef SYSTEM_BUS_WIDTH +#error SYSTEM_BUS_WIDTH is undefined +#endif + +#if SYSTEM_BUS_WIDTH != 32 +#error Only SYSTEM_BUS_WIDTH 32 is supported +#endif + +typedef struct +{ + volatile uint32_t status; + volatile uint32_t control; + volatile uint32_t period_lo; + volatile uint32_t period_hi; + volatile uint32_t snap_lo; + volatile uint32_t snap_hi; +} +altera_avalon_timer_regs; + +#define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1) +#define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0) +#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2) +#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1) + +#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1) +#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0) +#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2) +#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1) +#define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4) +#define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2) +#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8) +#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3) + +typedef struct +{ + volatile uint32_t data; + volatile uint32_t control; +} +altera_avalon_jtag_uart_regs; + +#define ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK (0x000000FFu) +#define ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST (0) +#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK (0x00008000u) +#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_OFST (15) +#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK (0xFFFF0000u) +#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST (16) + +#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK (0x00000001u) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST (0) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK (0x00000002u) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST (1) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK (0x00000100u) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST (8) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK (0x00000200u) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST (9) +#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK (0x00000400u) +#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST (10) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK (0xFFFF0000u) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST (16) + +/* ============================================ */ + +/* functions */ + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/nios2/nios2_iss/include/tm27.h b/bsps/nios2/nios2_iss/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/nios2/nios2_iss/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/no_cpu/no_bsp/headers.am b/bsps/no_cpu/no_bsp/headers.am new file mode 100644 index 0000000000..33b3f811ac --- /dev/null +++ b/bsps/no_cpu/no_bsp/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/no_cpu/no_bsp/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/no_cpu/no_bsp/include/tm27.h diff --git a/bsps/no_cpu/no_bsp/include/bsp.h b/bsps/no_cpu/no_bsp/include/bsp.h new file mode 100644 index 0000000000..97064425d7 --- /dev/null +++ b/bsps/no_cpu/no_bsp/include/bsp.h @@ -0,0 +1,41 @@ +/* bsp.h + * + * This include file contains all board IO definitions. + * + * XXX : put yours in here + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_NO_CPU_NO_BSP_BSP_H +#define LIBBSP_NO_CPU_NO_BSP_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* functions */ + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/no_cpu/no_bsp/include/tm27.h b/bsps/no_cpu/no_bsp/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/no_cpu/no_bsp/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/or1k/generic_or1k/headers.am b/bsps/or1k/generic_or1k/headers.am new file mode 100644 index 0000000000..3576c64a9c --- /dev/null +++ b/bsps/or1k/generic_or1k/headers.am @@ -0,0 +1,12 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/or1k/generic_or1k/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/or1k/generic_or1k/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/or1k/generic_or1k/include/bsp/generic_or1k.h +include_bsp_HEADERS += ../../../../../../bsps/or1k/generic_or1k/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/or1k/generic_or1k/include/bsp/uart.h diff --git a/bsps/or1k/generic_or1k/include/bsp.h b/bsps/or1k/generic_or1k/include/bsp.h new file mode 100644 index 0000000000..16839930a4 --- /dev/null +++ b/bsps/or1k/generic_or1k/include/bsp.h @@ -0,0 +1,45 @@ +/** + * @file + * + * @ingroup generic_or1k + * + * @brief Global BSP definitions. + */ + +/* + * COPYRIGHT (c) 2014-2015 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#ifndef LIBBSP_GENERIC_OR1K_H +#define LIBBSP_GENERIC_OR1K_H + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_GENERIC_OR1K_H */ + +/** + * @defgroup generic_or1k support + * + * @ingroup bsp_or1k + * + * @brief generic_or1k support package + * + */ diff --git a/bsps/or1k/generic_or1k/include/bsp/generic_or1k.h b/bsps/or1k/generic_or1k/include/bsp/generic_or1k.h new file mode 100644 index 0000000000..e4d9760640 --- /dev/null +++ b/bsps/or1k/generic_or1k/include/bsp/generic_or1k.h @@ -0,0 +1,118 @@ +/** + * @file + * + * @ingroup generic_or1k_reg + * + * @brief Register definitions. + */ + +/* + * COPYRIGHT (c) 2014-2015 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#ifndef LIBBSP_GENERIC_OR1K_H +#define LIBBSP_GENERIC_OR1K_H + +#include + +/** + * @defgroup generic_or1k_reg Register Definitions + * + * @ingroup generic_or1k + * + * @brief Shared register definitions for or1k systems. + * + * @{ + */ + +/** + * @name Register Macros + * + * @{ + */ + + #define OR1K_REG(x) (*((volatile unsigned char *) (x))) + #define OR1K_BIT(n) (1 << (n)) + +/** @} */ + +/** + * @name Internal OR1K UART Registers + * + * @{ + */ +#define OR1K_BSP_CLOCK_FREQ 50000000UL +#define OR1K_BSP_UART_BASE 0x90000000 + +#define OR1K_BSP_UART_REG_TX (OR1K_BSP_UART_BASE+0) +#define OR1K_BSP_UART_REG_RX (OR1K_BSP_UART_BASE+0) +#define OR1K_BSP_UART_REG_DEV_LATCH_LOW (OR1K_BSP_UART_BASE+0) +#define OR1K_BSP_UART_REG_DEV_LATCH_HIGH (OR1K_BSP_UART_BASE+1) +#define OR1K_BSP_UART_REG_INT_ENABLE (OR1K_BSP_UART_BASE+1) +#define OR1K_BSP_UART_REG_INT_ID (OR1K_BSP_UART_BASE+2) +#define OR1K_BSP_UART_REG_FIFO_CTRL (OR1K_BSP_UART_BASE+2) +#define OR1K_BSP_UART_REG_LINE_CTRL (OR1K_BSP_UART_BASE+3) +#define OR1K_BSP_UART_REG_MODEM_CTRL (OR1K_BSP_UART_BASE+4) +#define OR1K_BSP_UART_REG_LINE_STATUS (OR1K_BSP_UART_BASE+5) +#define OR1K_BSP_UART_REG_MODEM_STATUS (OR1K_BSP_UART_BASE+6) +#define OR1K_BSP_UART_REG_SCRATCH (OR1K_BSP_UART_BASE+7) + +/* FIFO Control Register */ +#define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_1 (0x00) +#define OR1K_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO (0x01) +#define OR1K_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR (0x02) +#define OR1K_BSP_UART_REG_FIFO_CTRL_CLEAR_XMIT (0x03) +#define OR1K_BSP_UART_REG_FIFO_CTRL_DMA_SELECT (0x08) +#define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_4 (0x40) +#define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_8 (0x80) +#define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_14 (0xC0) +#define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_MASK (0xC0) + +/* Line Control Register */ +#define OR1K_BSP_UART_REG_LINE_CTRL_WLEN5 (0x00) +#define OR1K_BSP_UART_REG_LINE_CTRL_WLEN6 (0x01) +#define OR1K_BSP_UART_REG_LINE_CTRL_WLEN7 (0x02) +#define OR1K_BSP_UART_REG_LINE_CTRL_WLEN8 (0x03) +#define OR1K_BSP_UART_REG_LINE_CTRL_STOP (0x04) +#define OR1K_BSP_UART_REG_LINE_CTRL_PARITY (0x08) +#define OR1K_BSP_UART_REG_LINE_CTRL_EPAR (0x10) +#define OR1K_BSP_UART_REG_LINE_CTRL_SPAR (0x20) +#define OR1K_BSP_UART_REG_LINE_CTRL_SBC (0x40) +#define OR1K_BSP_UART_REG_LINE_CTRL_DLAB (0x80) + +/* Line Status Register */ +#define OR1K_BSP_UART_REG_LINE_STATUS_DR (0x01) +#define OR1K_BSP_UART_REG_LINE_STATUS_OE (0x02) +#define OR1K_BSP_UART_REG_LINE_STATUS_PE (0x04) +#define OR1K_BSP_UART_REG_LINE_STATUS_FE (0x08) +#define OR1K_BSP_UART_REG_LINE_STATUS_BI (0x10) +#define OR1K_BSP_UART_REG_LINE_STATUS_THRE (0x20) +#define OR1K_BSP_UART_REG_LINE_STATUS_TEMT (0x40) + +/* Modem Control Register */ +#define OR1K_BSP_UART_REG_MODEM_CTRL_DTR (0x01) +#define OR1K_BSP_UART_REG_MODEM_CTRL_RTS (0x02) +#define OR1K_BSP_UART_REG_MODEM_CTRL_OUT1 (0x04) +#define OR1K_BSP_UART_REG_MODEM_CTRL_OUT2 (0x08) +#define OR1K_BSP_UART_REG_MODEM_CTRL_LOOP (0x10) + +/* Modem Status Register */ +#define OR1K_BSP_UART_REG_MODEM_STATUS_DCTS (0x01) +#define OR1K_BSP_UART_REG_MODEM_STATUS_DDSR (0x02) +#define OR1K_BSP_UART_REG_MODEM_STATUS_TERI (0x04) +#define OR1K_BSP_UART_REG_MODEM_STATUS_DDCD (0x08) +#define OR1K_BSP_UART_REG_MODEM_STATUS_CTS (0x10) +#define OR1K_BSP_UART_REG_MODEM_STATUS_DSR (0x20) +#define OR1K_BSP_UART_REG_MODEM_STATUS_RI (0x40) +#define OR1K_BSP_UART_REG_MODEM_STATUS_DCD (0x80) +#define OR1K_BSP_UART_REG_MODEM_STATUS_ANY_DELTA (0x0F) + +/** @} */ + +/** @} */ + +#endif /* LIBBSP_GENERIC_OR1K_H */ diff --git a/bsps/or1k/generic_or1k/include/bsp/irq.h b/bsps/or1k/generic_or1k/include/bsp/irq.h new file mode 100644 index 0000000000..791aefcae0 --- /dev/null +++ b/bsps/or1k/generic_or1k/include/bsp/irq.h @@ -0,0 +1,45 @@ +/** + * @file + * + * @ingroup OR1K_IRQ + * + * @brief Interrupt definitions. + */ + +/** + * COPYRIGHT (c) 2014-2015 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#ifndef LIBBSP_GENERIC_OR1K_IRQ_H +#define LIBBSP_GENERIC_OR1K_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#define BSP_INTERRUPT_VECTOR_MIN 0x100 +#define BSP_INTERRUPT_VECTOR_MAX 0x1F00 + +/* Interrupt Identification Register */ +#define OR1K_BSP_UART_REG_INT_ID_MSI (0x00) +#define OR1K_BSP_UART_REG_INT_ID_NO_INT (0x01) +#define OR1K_BSP_UART_REG_INT_ID_THRI (0x02) +#define OR1K_BSP_UART_REG_INT_ID_RDI (0x04) +#define OR1K_BSP_UART_REG_INT_ID_ID (0x06) +#define OR1K_BSP_UART_REG_INT_ID_RLSI (0x06) +#define OR1K_BSP_UART_REG_INT_ID_TOI (0x0c) + +/* Interrupt Enable Register */ +#define OR1K_BSP_UART_REG_INT_ENABLE_RDI (0x01) +#define OR1K_BSP_UART_REG_INT_ENABLE_THRI (0x02) +#define OR1K_BSP_UART_REG_INT_ENABLE_RLSI (0x04) +#define OR1K_BSP_UART_REG_INT_ENABLE_MSI (0x08) + +#endif /* ASM */ +#endif /* LIBBSP_GENERIC_OR1K_IRQ_H */ diff --git a/bsps/or1k/generic_or1k/include/bsp/uart.h b/bsps/or1k/generic_or1k/include/bsp/uart.h new file mode 100644 index 0000000000..dbf3bbf9ef --- /dev/null +++ b/bsps/or1k/generic_or1k/include/bsp/uart.h @@ -0,0 +1,42 @@ +/** + * @file + * + * @ingroup generic_or1k_uart + * + * @brief UART support. + */ + +/* + * COPYRIGHT (c) 2014-2015 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +/** + * @defgroup generic_or1k_uart UART Support + * + * @ingroup generic_or1k + * + * @brief Universal Asynchronous Receiver/Transmitter (UART) Support + */ + +#ifndef LIBBSP_GENERIC_OR1K_UART_H +#define LIBBSP_GENERIC_OR1K_UART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define OR1K_UART_DEFAULT_BAUD 115200 +#define OR1K_BSP_UART_IRQ 2 +extern const console_fns generic_or1k_uart_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_GENERIC_OR1K_UART_H */ diff --git a/bsps/or1k/generic_or1k/include/tm27.h b/bsps/or1k/generic_or1k/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/or1k/generic_or1k/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/or1k/headers.am b/bsps/or1k/headers.am new file mode 100644 index 0000000000..7729a76231 --- /dev/null +++ b/bsps/or1k/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/or1k/include/bsp/cache_.h +include_bsp_HEADERS += ../../../../../bsps/or1k/include/bsp/linker-symbols.h diff --git a/bsps/or1k/include/bsp/cache_.h b/bsps/or1k/include/bsp/cache_.h new file mode 100644 index 0000000000..ed2053858e --- /dev/null +++ b/bsps/or1k/include/bsp/cache_.h @@ -0,0 +1,43 @@ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_OR1K_SHARED_CACHE_H +#define LIBBSP_OR1K_SHARED_CACHE_H + +#include +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* These two defines also ensure that the rtems_cache_* functions have bodies */ +#define CPU_DATA_CACHE_ALIGNMENT 32 +#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 + +#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS 1 + +static inline size_t +_CPU_cache_get_data_cache_size( const uint32_t level ) +{ + return (level == 0 || level == 1)? 8192 : 0; +} + +static inline size_t +_CPU_cache_get_instruction_cache_size( const uint32_t level ) +{ + return (level == 0 || level == 1)? 8192 : 0; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_OR1K_SHARED_CACHE_H */ diff --git a/bsps/or1k/include/bsp/linker-symbols.h b/bsps/or1k/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..f0f8377892 --- /dev/null +++ b/bsps/or1k/include/bsp/linker-symbols.h @@ -0,0 +1,79 @@ +#ifndef LIBBSP_OR1k_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_OR1k_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup or1k_linker Linker Support + * + * @ingroup or1k_shared + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM + #define LINKER_SYMBOL(sym) extern char sym []; +#else + #define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_vector_begin) +LINKER_SYMBOL(bsp_section_vector_end) +LINKER_SYMBOL(bsp_section_vector_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_vector_table_begin) +LINKER_SYMBOL(bsp_vector_table_end) +LINKER_SYMBOL(bsp_vector_table_size) + +LINKER_SYMBOL(bsp_start_vector_table_begin) +LINKER_SYMBOL(bsp_start_vector_table_end) +LINKER_SYMBOL(bsp_start_vector_table_size) + +LINKER_SYMBOL(bsp_translation_table_base) +LINKER_SYMBOL(bsp_translation_table_end) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_OR1K_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/powerpc/beatnik/headers.am b/bsps/powerpc/beatnik/headers.am new file mode 100644 index 0000000000..36df3cd759 --- /dev/null +++ b/bsps/powerpc/beatnik/headers.am @@ -0,0 +1,22 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/VMEConfig.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gt_timer.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gti2creg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gtintrreg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gtpcireg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gtreg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/if_em_pub.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/if_mve_pub.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/irq.h diff --git a/bsps/powerpc/beatnik/include/bsp.h b/bsps/powerpc/beatnik/include/bsp.h new file mode 100644 index 0000000000..e980f1a056 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp.h @@ -0,0 +1,297 @@ +/* + * bsp.h -- contain BSP API definition. + */ + +/* + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP. + * + * Modified for the 'beatnik' BSP by T. Straumann, 2005-2007. + */ + +#ifndef LIBBSP_BEATNIK_BSP_H +#define LIBBSP_BEATNIK_BSP_H + +#ifndef ASM + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Board type */ +typedef enum { + Unknown = 0, + MVME5500, + MVME6100 +} BSP_BoardType; + +BSP_BoardType BSP_getBoardType(void); + +/* Discovery Version */ + +typedef enum { + unknown = 0, + GT_64260_A, /* Revision 0x10 */ + GT_64260_B, /* Revision 0x20 */ + MV_64360, +} DiscoveryVersion; + +/* Determine the type of discovery chip on this board; info + * is cached and repeated calls just return the cached value. + * + * If a non-zero argument is passed, the routine panics + * (rtems_panic) if no recognized bridge is found; + */ +DiscoveryVersion BSP_getDiscoveryVersion(int assertion); + +/* + * confdefs.h overrides for this BSP: + * - Interrupt stack space is not minimum if defined. + */ +#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) + +/* + * base address definitions for several devices + */ +#define BSP_MV64x60_BASE (0xf1000000) +#define BSP_MV64x60_DEV1_BASE (0xf1100000) +#define BSP_UART_IOBASE_COM1 ((BSP_MV64x60_DEV1_BASE)+0x20000) +#define BSP_UART_IOBASE_COM2 ((BSP_MV64x60_DEV1_BASE)+0x21000) +#define BSP_UART_USE_SHARED_IRQS + +#define BSP_NVRAM_BASE_ADDR (0xf1110000) +#define BSP_NVRAM_END_ADDR (0xf1117fff) +#define BSP_NVRAM_RTC_START (0xf1117ff8) + +#define BSP_NVRAM_BOOTPARMS_START (0xf1111000) +#define BSP_NVRAM_BOOTPARMS_END (0xf1111fff) + + +/* This is only active/used during early init. It defines + * the hose0 base for the shared/generic pci code. + * Our own BSP specific pci initialization will then + * override the PCI configuration (see gt_pci_init.c:BSP_pci_initialize) + */ + +#define PCI_CONFIG_ADDR (BSP_MV64x60_BASE + 0xcf8) +#define PCI_CONFIG_DATA (BSP_MV64x60_BASE + 0xcfc) + +/* our wonderful PCI initialization remaps everything to CPU addresses + * - before calling BSP_pci_initialize() this is NOT VALID, however + * and the deprecated inl()/outl() etc won't work! + */ +#define _IO_BASE 0x00000000 +/* wonderful MotLoad has the base address as seen from the + * CPU programmed into config space :-) + */ +#define PCI_MEM_BASE 0 +#define PCI_MEM_BASE_ADJUSTMENT 0 +#define PCI_DRAM_OFFSET 0 + +extern void BSP_motload_pci_fixup(void); + +/* PCI <-> local address mapping - no sophisticated windows + * (i.e., no support for cached regions etc. you read a BAR + * from config space and that's 1:1 where the CPU sees it). + * Our memory is mapped 1:1 to PCI also. + */ +#define BSP_PCI2LOCAL_ADDR(a) ((uint32_t)(a)) +#define BSP_LOCAL2PCI_ADDR(a) ((uint32_t)(a)) + +#define BSP_CONFIG_NUM_PCI_CACHE_SLOTS 32 + +#define BSP_CONSOLE_PORT BSP_UART_COM1 +#define BSP_UART_BAUD_BASE 115200 + +/* I2C Devices */ +/* Note that the i2c addresses stated in the manual are + * left-shifted by one bit. + */ +#define BSP_VPD_I2C_ADDR (0xA8>>1) /* the VPD EEPROM */ +#define BSP_USR_I2C_ADDR (0xAA>>1) /* the user EEPROM */ +#define BSP_THM_I2C_ADDR (0x90>>1) /* the DS1621 temperature sensor & thermostat */ + +#define BSP_I2C_BUS_DESCRIPTOR gt64260_i2c_bus_descriptor + +#define BSP_I2C_BUS0_NAME "/dev/i2c0" + +#define BSP_I2C_VPD_EEPROM_NAME "vpd-eeprom" +#define BSP_I2C_USR_EEPROM_NAME "usr-eeprom" +#define BSP_I2C_DS1621_NAME "ds1621" +#define BSP_I2C_THM_NAME BSP_I2C_DS1621_NAME +#define BSP_I2C_DS1621_RAW_NAME "ds1621-raw" + +#define BSP_I2C_VPD_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_VPD_EEPROM_NAME) +#define BSP_I2C_USR_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR_EEPROM_NAME) +#define BSP_I2C_DS1621_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_NAME) +#define BSP_I2C_THM_DEV_NAME BSP_I2C_DS1621_DEV_NAME +#define BSP_I2C_DS1621_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_RAW_NAME) + + +/* Initialize the I2C driver and register all devices + * RETURNS 0 on success, -1 on error. + * + * Access to the VPD and user EEPROMS as well + * as the ds1621 temperature sensor is possible + * by means of file nodes + * + * /dev/i2c0.vpd-eeprom (read-only) + * /dev/i2c0.usr-eeprom (read-write) + * /dev/i2c0.ds1621 (read-only; one byte: board-temp in degC) + * /dev/i2c0.ds1621-raw (read-write; transfer bytes to/from the ds1621) + */ +int BSP_i2c_initialize(void); + +/* Networking; */ +#if defined(RTEMS_NETWORKING) +#include +#endif + +/* NOT FOR PUBLIC USE BELOW HERE */ +#define BSP_PCI_HOSE0_MEM_BASE 0x80000000 /* must be aligned to size */ +#define BSP_PCI_HOSE0_MEM_SIZE 0x20000000 + +#define BSP_PCI_HOSE1_MEM_BASE 0xe0000000 + +#define BSP_DEV_AND_PCI_IO_BASE 0xf0000000 +#define BSP_DEV_AND_PCI_IO_SIZE 0x10000000 + +/* maintain coherency between CPU and GT64340 Ethernet + * (andpossibly other Discovery components). + */ +#define BSP_RW_PAGE_ATTRIBUTES TRIV121_ATTR_M + +extern unsigned BSP_pci_hose1_bus_base; + +void BSP_pci_initialize(void); + +/* Exception Handling */ + +/* Use a task notepad to attach user exception handler info; + * may be changed by application startup code (EPICS uses 11) + */ +#define BSP_EXCEPTION_NOTEPAD 14 + +#ifndef ASM + +#define outport_byte(port,value) outb(value,port) +#define outport_word(port,value) outw(value,port) +#define outport_long(port,value) outl(value,port) + +#define inport_byte(port,value) (value = inb(port)) +#define inport_word(port,value) (value = inw(port)) +#define inport_long(port,value) (value = inl(port)) +/* + * Vital Board data Start using DATA RESIDUAL + */ +/* + * Total memory using RESIDUAL DATA + */ +extern unsigned int BSP_mem_size; +/* + * Start of the heap + */ +extern unsigned int BSP_heap_start; +/* + * PCI Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * processor clock frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; + +extern char BSP_productIdent[20]; +extern char BSP_serialNumber[20]; + +extern char BSP_enetAddr0[7]; +extern char BSP_enetAddr1[7]; + +/* + * The commandline as passed from the bootloader. + */ +extern char *BSP_commandline_string; + + +#define BSP_Convert_decrementer( _value ) \ + ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) + +extern rtems_configuration_table BSP_Configuration; +extern void bsp_reset(void); +extern int BSP_disconnect_clock_handler (void); +extern int BSP_connect_clock_handler (void); + +/* clear hostbridge errors + * + * enableMCP: whether to enable MCP checkstop / machine check interrupts + * on the hostbridge and in HID0. + * + * NOTE: The 5500 and 6100 boards have NO PHYSICAL CONNECTION + * to MCP so 'enableMCP' will always fail! + * + * quiet : be silent + * + * RETURNS : PCI status (hose 0 in byte 0, host 1 in byte 1) and + * VME bridge status (upper 16 bits). + * Zero if no errors were found. + */ +extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); + +/* clear vme bridge errors and return (bridge-dependent) 16-bit status + * + * quiet : be silent + * + * RETURNS : 0 if there were no errors, non-zero, bridge-dependent + * 16-bit error status on error. + * + */ +extern unsigned short (*_BSP_clear_vmebridge_errors)(int); + +/* + * Prototypes for debug helpers + */ +void discovery_pic_set_debug_irq(int on); +void discovery_pic_install_debug_irq(void); + +/* + * Prototypes for methods called only from .S for dependency tracking + */ +char *save_boot_params( + void *r3, + void *r4, + void *r5, + char *cmdline_start, + char *cmdline_end +); +void zero_bss(void); + +/* + * Prototypes for methods in the BSP that cross file boundaries + */ +uint32_t probeMemoryEnd(void); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/VMEConfig.h b/bsps/powerpc/beatnik/include/bsp/VMEConfig.h new file mode 100644 index 0000000000..986a01674e --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/VMEConfig.h @@ -0,0 +1,114 @@ +#ifndef RTEMS_BSP_VME_CONFIG_H +#define RTEMS_BSP_VME_CONFIG_H + +/* BSP specific address space configuration parameters */ + +/* + * Authorship + * ---------- + * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was + * created by Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'beatnik' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#define _VME_DRIVER_TSI148 +#define _VME_DRIVER_UNIVERSE + +/* + * NOTE: the BSP (startup/bspstart.c) uses + * hardcoded window lengths that match this + * layout when setting BATs: + */ +#define _VME_A32_WIN0_ON_PCI 0x90000000 +/* If _VME_CSR_ON_PCI is defined then the A32 window is reduced to accommodate + * CSR for space. + */ +#define _VME_CSR_ON_PCI 0x9e000000 +#define _VME_A24_ON_PCI 0x9f000000 +#define _VME_A16_ON_PCI 0x9fff0000 + +/* start of the A32 window on the VME bus + * TODO: this should perhaps be a configuration option + */ +#define _VME_A32_WIN0_ON_VME 0x20000000 + +/* if _VME_DRAM_OFFSET is defined, the BSP + * will map our RAM onto the VME bus, starting + * at _VME_DRAM_OFFSET + */ +#define _VME_DRAM_OFFSET 0x90000000 + +extern int BSP_VMEInit(void); +extern int BSP_VMEIrqMgrInstall(void); + +#define BSP_VME_INSTALL_IRQ_MGR(err) \ + do { \ + err = -1; \ + switch (BSP_getBoardType()) { \ + case MVME6100: \ + err = theOps->install_irq_mgr( \ + VMETSI148_IRQ_MGR_FLAG_SHARED, \ + 0, BSP_IRQ_GPP_0 + 20, \ + 1, BSP_IRQ_GPP_0 + 21, \ + 2, BSP_IRQ_GPP_0 + 22, \ + 3, BSP_IRQ_GPP_0 + 23, \ + -1); \ + break; \ +\ + case MVME5500: \ + err = theOps->install_irq_mgr( \ + VMEUNIVERSE_IRQ_MGR_FLAG_SHARED | \ + VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND, \ + 0, BSP_IRQ_GPP_0 + 12, \ + 1, BSP_IRQ_GPP_0 + 13, \ + 2, BSP_IRQ_GPP_0 + 14, \ + 3, BSP_IRQ_GPP_0 + 15, \ + -1); \ + break; \ +\ + default: \ + printk("WARNING: unknown board; "); \ + break; \ + } \ + if ( err ) \ + printk("VME interrupt manager NOT INSTALLED (error: %i)\n", err); \ + } while (0) + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h b/bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h new file mode 100644 index 0000000000..a12e9e2c86 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h @@ -0,0 +1,79 @@ +#ifndef BSP_BSDNET_ATTACH_INFO_H +#define BSP_BSDNET_ATTACH_INFO_H + +/* Author: Till Straumann, 2005; see ../../LICENSE */ + +/* Rationale: traditionally, BSPs only supported a single networking interface + * the BSP defined RTEMS_NETWORK_DRIVER_NAME & friends macros + * for applications to use. + * If more than one interface is present, this simple approach is + * not enough. + * Hence, this BSP exports a routine declaring all available interfaces + * so the application can make a choice. + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Fwd. decl just in case */ +struct rtems_bsdnet_ifconfig; + +typedef struct { + /* name of the interface */ + const char *name; + /* optional description (to be used by chooser 'help' function etc.) */ + const char *description; + /* driver 'attach' function */ + int (*attach_fn)(struct rtems_bsdnet_ifconfig*, int); +} BSP_NetIFDescRec, *BSP_NetIFDesc; + +/* Return a pointer to the (static) list of network interface descriptions + * of this board. + * + * NOTES: A NULL value is returned if e.g., the board type cannot be determined + * or for other reasons. + * The 'description' field is optional, i.e., may be NULL. + * The list is terminated by an element with a NULL name field. + * The interfaces are listed in the order they are labelled. + */ + +BSP_NetIFDesc +BSP_availableNetIFs(); + +/* Define this macro so applications can conditionally compile this API */ +#define BSP_HAS_MULTIPLE_NETIFS(x) BSP_availableNetIFs() + +/* Legacy macro; applications should use BSP_Available_NetIfs() to choose + * an interface and attach function. + */ +extern char BSP_auto_network_driver_name[20]; +#define RTEMS_BSP_NETWORK_DRIVER_NAME BSP_auto_network_driver_name + +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_auto_enet_attach + +/* This routine checks the name field passed in the 'ifconfig'. + * If the name is NULL or points to the BSP_auto_network_driver_name + * array, the routine checks all interfaces for an active link and + * attaches the first alive one. + * It also updates 'ifconfig' to reflect the chosen interface's name + * and attach function. + * + * If another name is passed in, the routine scans + * the available interfaces for that name and uses it, if found. + * Eventually, a default interface is chosen (provided that + * the board type is successfully detected). + * + * Note that only ONE interface chained into rtems_bsdnet_config + * may use the "auto" name. + * + */ + +int +BSP_auto_enet_attach(struct rtems_bsdnet_ifconfig *ifconfig, int attaching); + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h b/bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h new file mode 100644 index 0000000000..74160a3b84 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h @@ -0,0 +1,30 @@ +#ifndef BSP_EARLY_ENET_LINK_STATUS_H +#define BSP_EARLY_ENET_LINK_STATUS_H + +/* Determine link status of ethernet device before network is initialized */ + +/* T. Straumann, 2005; see ../../LICENSE */ + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +typedef struct { + int (*init)(int idx); /* perform enough initialization to access (default) phy */ + int (*read_phy)(int idx, unsigned reg); + int (*write_phy)(int idx, unsigned reg, unsigned val); + const char *name; /* driver name */ + unsigned char num_slots; /* max number of supported devices */ + unsigned char initialized; /* must be initialized to 0; */ +} rtems_bsdnet_early_link_check_ops; + +int +BSP_early_check_link_status(int unit, rtems_bsdnet_early_link_check_ops *ops); + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/gt_timer.h b/bsps/powerpc/beatnik/include/bsp/gt_timer.h new file mode 100644 index 0000000000..4a68971d13 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/gt_timer.h @@ -0,0 +1,133 @@ +#ifndef BSP_GT_TIMER_H +#define BSP_GT_TIMER_H + +/* Support for hardware timers in the discovery bridge */ + +/* + * Authorship + * ---------- + * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was + * created by Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'beatnik' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/* Obtain the number of hardware timers present + * The 'timer' argument in the routines below addresses + * one of 0..(BSP_timer_instances()-1) + */ +int BSP_timer_instances(void); + +/* Setup timer but don't start yet; interrupts are enabled if an isr argument is passed + * no interrupts are generated otherwise. + * + * If 'reload' is nonzero then the period is automatically restarted. + * + * RETURNS: 0 on success, nonzero on error (argument error) + * + * NOTE: If an ISR is already connected, it must be removed by passing a NULL isr first. + */ +int BSP_timer_setup(uint32_t timer, void (*isr)(void *arg), void *arg, int reload); + +/* Stop timer; + * + * RETURNS: 0 on success, nonzero on argument error + */ +int BSP_timer_stop(uint32_t timer); + +/* Start timer with 'period' (in ticks) + * + * RETURNS: 0 on success, nonzero on argument error + */ +int BSP_timer_start(uint32_t timer, uint32_t period); + +/* read decrementing timer on the fly + * + * RETURNS: current count in ticks + */ +uint32_t BSP_timer_read(uint32_t timer); + +/* get clock rate in Hz */ +uint32_t BSP_timer_clock_get(uint32_t timer); + +/* Initialize timer facility -- to be used by BSP implementors only + * + * RETURNS: 0 on success, nonzero if ISR wrapper couldn't be installed + */ +int BSP_timers_initialize(void); + +/* WATCHDOG TIMER (resets board if enabled and not 'petted' for + * some time). + */ + +/* Enable watchdog and set a timeout (in us) + * RETURNS 0 on success + */ +int BSP_watchdog_enable(uint32_t timeout_us); + +/* Disable watchdog + * RETURNS 0 on success + */ +int BSP_watchdog_disable(void); + +/* Check status -- unfortunately there seems to be no way + * to read the running value... + * + * RETURNS nonzero if enabled/running, zero if disabled/stopped + */ +int BSP_watchdog_status(void); + +/* Pet the watchdog (rearm to configured timeout) + * RETURNS: 0 on success, nonzero on failure (watchdog + * currently not running). + */ +int BSP_watchdog_pet(void); + + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h b/bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h new file mode 100644 index 0000000000..b75e16cdf8 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h @@ -0,0 +1,62 @@ +#ifndef GT_64260_BUS_DRIVER_H +#define GT_64260_BUS_DRIVER_H +/* + * Authorship + * ---------- + * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was + * created by Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'beatnik' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#include +#include + +/* for registration with libi2c */ +extern rtems_libi2c_bus_t *gt64260_i2c_bus_descriptor; + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/gti2creg.h b/bsps/powerpc/beatnik/include/bsp/gti2creg.h new file mode 100644 index 0000000000..33e566f5bc --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/gti2creg.h @@ -0,0 +1,83 @@ +/* $NetBSD: gti2creg.h,v 1.2 2005/02/27 00:27:21 perry Exp $ */ + +/* + * Copyright (c) 2005 Brocade Communcations, inc. + * All rights reserved. + * + * Written by Matt Thomas for Brocade Communcations, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of Brocade Communications, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_MARVELL_GTI2CREG_H_ +#define _DEV_MARVELL_GTI2CREG_H_ + +#define I2C_REG_SlaveAddr 0xc000 +#define I2C_REG_ExtSlaveAddr 0xc010 +#define I2C_REG_Data 0xc004 +#define I2C_REG_Control 0xc008 +#define I2C_REG_Status 0xc00c +#define I2C_REG_BaudRate 0xc00c +#define I2C_REG_SoftReset 0xc01c + +#define I2C_SlaveAddr_GCE 0x0001 /* Act as Slave */ +#define I2C_SlaveAddr_SAddr 0x7E + +#define I2C_Control_ACK 0x04 +#define I2C_Control_IFlg 0x08 +#define I2C_Control_Stop 0x10 +#define I2C_Control_Start 0x20 +#define I2C_Control_TWSIEn 0x40 +#define I2C_Control_IntEn 0x80 + +/* + * F(I2C) = F(Tclk) / ( 10 * (M + 1) * (2^(N+1))) + * For Tclk = 100MHz, M = 4, N = 4: F = 62.5KHz + * For Tclk = 100MHz, M = 13, N = 3: F = 96.2KHz + */ +#define I2C_BaudRate(M, N) (((M) << 3) | (N)) +#define I2C_BaudRate_62_5K I2C_BaudRate(4, 4) +#define I2C_BaudRate_96_2K I2C_BaudRate(13, 3) + +#define I2C_Status_BusError 0x00 /* Bus error */ +#define I2C_Status_Started 0x08 /* Start condition xmitted */ +#define I2C_Status_ReStarted 0x10 /* Repeated start condition xmitted */ +#define I2C_Status_AddrWriteAck 0x18 /* Adr + wr bit xmtd, ack rcvd */ +#define I2C_Status_AddrWriteNoAck 0x20 /* Adr + wr bit xmtd, NO ack rcvd */ +#define I2C_Status_MasterWriteAck 0x28 /* Master xmtd data byte, ack rcvd */ +#define I2C_Status_MasterWriteNoAck 0x30 /* Master xmtd data byte, NO ack rcvd*/ +#define I2C_Status_MasterLostArb 0x38 /* Master lost arbitration during + address or data transfer */ +#define I2C_Status_AddrReadAck 0x40 /* Adr + rd bit xmtd, ack rcvd */ +#define I2C_Status_AddrReadNoAck 0x48 /* Adr + rd bit xmtd, NO ack rcvd */ +#define I2C_Status_MasterReadAck 0x50 /* Master rcvd data bye, ack rcvd */ +#define I2C_Status_MasterReadNoAck 0x58 /* Master rcvd data bye, NO ack rcvd */ +#define I2C_Status_2ndAddrWriteAck 0xd0 /* 2nd adr + wr bit xmid, ack rcvd */ +#define I2C_Status_2ndAddrWriteNoAck 0xd8 /* 2nd adr + wr bit xmid, NO ack rcvd */ +#define I2C_Status_2ndAddrReadAck 0xe0 /* 2nd adr + rd bit xmid, ack rcvd */ +#define I2C_Status_2ndAddrReadNoAck 0xe8 /* 2nd adr + rd bit xmtd, NO ack rcvd */ +#define I2C_Status_Idle 0xf8 /* Idle */ + +#endif /* _DEV_MARVELL_GTI2CREG_H_ */ diff --git a/bsps/powerpc/beatnik/include/bsp/gtintrreg.h b/bsps/powerpc/beatnik/include/bsp/gtintrreg.h new file mode 100644 index 0000000000..bd3f69514e --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/gtintrreg.h @@ -0,0 +1,257 @@ +/* $NetBSD: gtintrreg.h,v 1.3 2005/02/27 00:27:21 perry Exp $ */ + +/* + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * gt64260intr.h: defines for GT-64260 system controller interrupts + * + * creation Sun Jan 7 18:05:59 PST 2001 cliff + * + * NOTE: + * Galileo GT-64260 manual bit defines assume Little Endian + * ordering of bits within bytes, i.e. + * bit #0 --> 0x01 + * vs. Motorola Big Endian bit numbering where + * bit #0 --> 0x80 + * Consequently we define bits in Little Endian format and plan + * to swizzle bytes during programmed I/O by using lwbrx/swbrx + * to load/store GT-64260 registers. + */ + + +#ifndef _DISCOVERY_GT64260INTR_H +#define _DISCOVERY_GT64260INTR_H + +#define BIT(n) (1<<(n)) + + +/* + * GT-64260 Interrupt Controller Register Map + */ +#define ICR_260_MIC_LO 0xc18 /* main interrupt cause low */ +#define ICR_260_MIC_HI 0xc68 /* main interrupt cause high */ +#define ICR_260_CIM_LO 0xc1c /* CPU interrupt mask low */ +#define ICR_260_CIM_HI 0xc6c /* CPU interrupt mask high */ +#define ICR_260_CSC 0xc70 /* CPU select cause */ +#define ICR_260_P0IM_LO 0xc24 /* PCI_0 interrupt mask low */ +#define ICR_260_P0IM_HI 0xc64 /* PCI_0 interrupt mask high */ +#define ICR_260_P0SC 0xc74 /* PCI_0 select cause */ +#define ICR_260_P1IM_LO 0xca4 /* PCI_1 interrupt mask low */ +#define ICR_260_P1IM_HI 0xce4 /* PCI_1 interrupt mask high */ +#define ICR_260_P1SC 0xcf4 /* PCI_1 select cause */ +#define ICR_260_CI0M 0xe60 /* CPU int[0] mask */ +#define ICR_260_CI1M 0xe64 /* CPU int[1] mask */ +#define ICR_260_CI2M 0xe68 /* CPU int[2] mask */ +#define ICR_260_CI3M 0xe6c /* CPU int[3] mask */ + +/* + * MV64360 Interrupt Controller Register Map + */ +#define ICR_360_MIC_LO 0x004 /* main interrupt cause low */ +#define ICR_360_MIC_HI 0x00c /* main interrupt cause high */ +#define ICR_360_C0IM_LO 0x014 /* CPU 0 interrupt mask low */ +#define ICR_360_C0IM_HI 0x01c /* CPU 0 interrupt mask high */ +#define ICR_360_C0SC 0x024 /* CPU 0 select cause */ +#define ICR_360_C1IM_LO 0x034 /* CPU 1 interrupt mask low */ +#define ICR_360_C1IM_HI 0x03c /* CPU 1 interrupt mask high */ +#define ICR_360_C1SC 0x044 /* CPU 1 select cause */ +#define ICR_360_I0M_LO 0x014 /* Int 0 mask low */ +#define ICR_360_I0M_HI 0x01c /* Int 0 mask high */ +#define ICR_360_I0SC 0x024 /* Int 0 select cause */ +#define ICR_360_I1M_LO 0x034 /* Int 1 mask low */ +#define ICR_360_I1M_HI 0x03c /* Int 1 mask high */ +#define ICR_360_C1SC 0x044 /* Int 1 select cause */ + + +/* + * IRQs: + * we define IRQs based on bit number in the + * ICU_LEN dimensioned hardware portion of the imask_t bit vector + * which consists of 64 bits of Main Cause and Mask register pairs + * (ICR_MIC_LO, ICR_MIC_HI and ICR_CIM_LO, ICR_CIM_HI) + * as well as 32 bits in GPP registers (see intr.h): + * + * IRQs: + * 31.............................0 63.............................32 + * | | | + * imask_t index: | | | + * | | | | + * ^--------- IM_PIC_LO ----------^ ^------ IM_PIC_HI ------------^ + * | | | + * Bitmasks: | | | + * | | | | + * ^--------- IML_* --------------^ ^------ IMH_* ----------------^ + * | | | + * Registers: | | | + * | | | | + * ^--------- ICR_MIC_LO ---------^ ^------ ICR_MIC_HI -----------^ + * ^--------- ICR_CIM_LO ---------^ ^------ ICR_CIM_HI -----------^ + * + * IRQs: + * 95............................64 127............................96 + * | | | + * imask_t index: | | | + * | | | | + * ^-------- IMASK_GPP ----------^ ^----- IMASK_SOFTINT --------^ + * | | | + * Bitmasks: | | | + * | | | | + * ^--------- GPP_* --------------^ ^------ SIBIT(irq) -----------^ + * | | | + * Registers: | | | + * | | | | + * ^--- GT_GPP_Interrupt_Cause ---^ ^------- (none) -----------^ + * ^--- GT_GPP_Interrupt_Mask ---^ + * + * + * Note that GPP interrupts are summarized in the Main Cause Register. + * + * Some IRQs are "resvered" undefined due to gaps in HW register utilization. + */ +#define IRQ_DEV 1 /* device interface interrupt */ +#define IRQ_DMA 2 /* DMA addres error interrupt */ +#define IRQ_CPU 3 /* CPU interface interrupt */ +#define IRQ_IDMA0_1 4 /* IDMA ch. 0..1 complete interrupt */ +#define IRQ_IDMA2_3 5 /* IDMA ch. 2..3 complete interrupt */ +#define IRQ_IDMA4_5 6 /* IDMA ch. 4..5 complete interrupt */ +#define IRQ_IDMA6_7 7 /* IDMA ch. 6..7 complete interrupt */ +#define IRQ_TIME0_1 8 /* Timer 0..1 interrupt */ +#define IRQ_TIME2_3 9 /* Timer 2..3 interrupt */ +#define IRQ_TIME4_5 10 /* Timer 4..5 interrupt */ +#define IRQ_TIME6_7 11 /* Timer 6..7 interrupt */ +#define IRQ_PCI0_0 12 /* PCI 0 interrupt 0 summary */ +#define IRQ_PCI0_1 13 /* PCI 0 interrupt 1 summary */ +#define IRQ_PCI0_2 14 /* PCI 0 interrupt 2 summary */ +#define IRQ_PCI0_3 15 /* PCI 0 interrupt 3 summary */ +#define IRQ_PCI1_0 16 /* PCI 1 interrupt 0 summary */ +#define IRQ_ECC 17 /* ECC error interrupt */ +#define IRQ_PCI1_1 18 /* PCI 1 interrupt 1 summary */ +#define IRQ_PCI1_2 19 /* PCI 1 interrupt 2 summary */ +#define IRQ_PCI1_3 20 /* PCI 1 interrupt 3 summary */ +#define IRQ_PCI0OUT_LO 21 /* PCI 0 outbound interrupt summary */ +#define IRQ_PCI0OUT_HI 22 /* PCI 0 outbound interrupt summary */ +#define IRQ_PCI1OUT_LO 23 /* PCI 1 outbound interrupt summary */ +#define IRQ_PCI1OUT_HI 24 /* PCI 1 outbound interrupt summary */ +#define IRQ_PCI0IN_LO 26 /* PCI 0 inbound interrupt summary */ +#define IRQ_PCI0IN_HI 27 /* PCI 0 inbound interrupt summary */ +#define IRQ_PCI1IN_LO 28 /* PCI 1 inbound interrupt summary */ +#define IRQ_PCI1IN_HI 29 /* PCI 1 inbound interrupt summary */ +#define IRQ_ETH0 (32+0) /* Ethernet controller 0 interrupt */ +#define IRQ_ETH1 (32+1) /* Ethernet controller 1 interrupt */ +#define IRQ_ETH2 (32+2) /* Ethernet controller 2 interrupt */ +#define IRQ_SDMA (32+4) /* SDMA interrupt */ +#define IRQ_I2C (32+5) /* I2C interrupt */ +#define IRQ_BRG (32+7) /* Baud Rate Generator interrupt */ +#define IRQ_MPSC0 (32+8) /* MPSC 0 interrupt */ +#define IRQ_MPSC1 (32+10) /* MPSC 1 interrupt */ +#define IRQ_COMM (32+11) /* Comm unit interrupt */ +#define IRQ_GPP7_0 (32+24) /* GPP[7..0] interrupt */ +#define IRQ_GPP15_8 (32+25) /* GPP[15..8] interrupt */ +#define IRQ_GPP23_16 (32+26) /* GPP[23..16] interrupt */ +#define IRQ_GPP31_24 (32+27) /* GPP[31..24] interrupt */ + +/* + * low word interrupt mask register bits + */ +#define IML_SUM BIT(0) +#define IML_DEV BIT(IRQ_DEV) +#define IML_DMA BIT(IRQ_DMA) +#define IML_CPU BIT(IRQ_CPU) +#define IML_IDMA0_1 BIT(IRQ_IDMA0_1) +#define IML_IDMA2_3 BIT(IRQ_IDMA2_3) +#define IML_IDMA4_5 BIT(IRQ_IDMA4_5) +#define IML_IDMA6_7 BIT(IRQ_IDMA6_7) +#define IML_TIME0_1 BIT(IRQ_TIME0_1) +#define IML_TIME2_3 BIT(IRQ_TIME2_3) +#define IML_TIME4_5 BIT(IRQ_TIME4_5) +#define IML_TIME6_7 BIT(IRQ_TIME6_7) +#define IML_PCI0_0 BIT(IRQ_PCI0_0) +#define IML_PCI0_1 BIT(IRQ_PCI0_1) +#define IML_PCI0_2 BIT(IRQ_PCI0_2) +#define IML_PCI0_3 BIT(IRQ_PCI0_3) +#define IML_PCI1_0 BIT(IRQ_PCI1_0) +#define IML_ECC BIT(IRQ_ECC) +#define IML_PCI1_1 BIT(IRQ_PCI1_1) +#define IML_PCI1_2 BIT(IRQ_PCI1_2) +#define IML_PCI1_3 BIT(IRQ_PCI1_3) +#define IML_PCI0OUT_LO BIT(IRQ_PCI0OUT_LO) +#define IML_PCI0OUT_HI BIT(IRQ_PCI0OUT_HI) +#define IML_PCI1OUT_LO BIT(IRQ_PCI1OUT_LO) +#define IML_PCI1OUT_HI BIT(IRQ_PCI1OUT_HI) +#define IML_PCI0IN_LO BIT(IRQ_PCI0IN_LO) +#define IML_PCI0IN_HI BIT(IRQ_PCI0IN_HI) +#define IML_PCI1IN_LO BIT(IRQ_PCI1IN_LO) +#define IML_PCI1IN_HI BIT(IRQ_PCI1IN_HI) +#define IML_RES (BIT(25)|BIT(30)|BIT(31)) + +/* + * high word interrupt mask register bits + */ +#define IMH_ETH0 BIT(IRQ_ETH0-32) +#define IMH_ETH1 BIT(IRQ_ETH1-32) +#define IMH_ETH2 BIT(IRQ_ETH2-32) +#define IMH_SDMA BIT(IRQ_SDMA-32) +#define IMH_I2C BIT(IRQ_I2C-32) +#define IMH_BRG BIT(IRQ_BRG-32) +#define IMH_MPSC0 BIT(IRQ_MPSC0-32) +#define IMH_MPSC1 BIT(IRQ_MPSC1-32) +#define IMH_COMM BIT(IRQ_COMM-32) +#define IMH_GPP7_0 BIT(IRQ_GPP7_0-32) +#define IMH_GPP15_8 BIT(IRQ_GPP15_8-32) +#define IMH_GPP23_16 BIT(IRQ_GPP23_16-32) +#define IMH_GPP31_24 BIT(IRQ_GPP31_24-32) +#define IMH_GPP_SUM (IMH_GPP7_0|IMH_GPP15_8|IMH_GPP23_16|IMH_GPP31_24) +#define IMH_RES (BIT(3) |BIT(6) |BIT(9) |BIT(12)|BIT(13)|BIT(14) \ + |BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20) \ + |BIT(21)|BIT(22)|BIT(23)|BIT(28)|BIT(29)|BIT(30) \ + |BIT(31)) + +/* + * ICR_CSC "Select Cause" register bits + */ +#define CSC_SEL BIT(30) /* HI/LO select */ +#define CSC_STAT BIT(31) /* ? "irq active" : "irq none" */ +#define CSC_CAUSE ~(CSC_SEL|CSC_STAT) + + +/* + * CPU Int[n] Mask bit(s) + */ +#define CPUINT_SEL 0x80000000 /* HI/LO select */ + +#endif /* _DISCOVERY_GT64260INTR_H */ diff --git a/bsps/powerpc/beatnik/include/bsp/gtpcireg.h b/bsps/powerpc/beatnik/include/bsp/gtpcireg.h new file mode 100644 index 0000000000..d01fc702ac --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/gtpcireg.h @@ -0,0 +1,964 @@ +/* $NetBSD: gtpcireg.h,v 1.4 2005/12/11 12:22:16 christos Exp $ */ + +/* + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_GTPCIREG_H +#define _DEV_GTPCIREG_H + +#define PCI__BIT(bit) (1U << (bit)) +#define PCI__MASK(bit) (PCI__BIT(bit) - 1) +#define PCI__GEN(bus, off, num) (((off)^((bus) << 7))+((num) << 4)) +#define PCI__EXT(data, bit, len) (((data) >> (bit)) & PCI__MASK(len)) +#define PCI__CLR(data, bit, len) ((data) &= ~(PCI__MASK(len) << (bit))) +#define PCI__INS(bit, new) ((new) << (bit)) + +#define PCI_SYNC_REG(bus) (0xc0 | ((bus) << 3)) + +/* + * Table 185: PCI Slave ADDRess Decoding Register Map + */ +#define PCI_SCS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0c08, 0) +#define PCI_SCS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0c0c, 0) +#define PCI_CS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0c10, 0) +#define PCI_CS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0c14, 0) +#define PCI_SCS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0d08, 0) +#define PCI_SCS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0d0c, 0) +#define PCI_CS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0d10, 0) +#define PCI_BOOTCS_BAR_SIZE(bus) PCI__GEN(bus, 0x0d14, 0) +#define PCI_CS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0d18, 0) +#define PCI_P2P_MEM0_BAR_SIZE(bus) PCI__GEN(bus, 0x0d1c, 0) +#define PCI_P2P_MEM1_BAR_SIZE(bus) PCI__GEN(bus, 0x0d20, 0) +#define PCI_P2P_IO_BAR_SIZE(bus) PCI__GEN(bus, 0x0d24, 0) +#define PCI_CPU_BAR_SIZE(bus) PCI__GEN(bus, 0x0d28, 0) +#define PCI_EXPANSION_ROM_BAR_SIZE(bus) PCI__GEN(bus, 0x0d2c, 0) +#define PCI_DAC_SCS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0e00, 0) +#define PCI_DAC_SCS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0e04, 0) +#define PCI_DAC_SCS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0e08, 0) +#define PCI_DAC_SCS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0e0c, 0) +#define PCI_DAC_CS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0e10, 0) +#define PCI_DAC_CS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0e14, 0) +#define PCI_DAC_CS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0e18, 0) +#define PCI_DAC_CS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0e1c, 0) +#define PCI_DAC_BOOTCS_BAR_SIZE(bus) PCI__GEN(bus, 0x0e20, 0) +#define PCI_DAC_P2P_MEM0_BAR_SIZE(bus) PCI__GEN(bus, 0x0e24, 0) +#define PCI_DAC_P2P_MEM1_BAR_SIZE(bus) PCI__GEN(bus, 0x0e28, 0) +#define PCI_DAC_CPU_BAR_SIZE(bus) PCI__GEN(bus, 0x0e2c, 0) +#define PCI_BASE_ADDR_REGISTERS_ENABLE(bus) PCI__GEN(bus, 0x0c3c, 0) +#define PCI_SCS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c48, 0) +#define PCI_SCS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d48, 0) +#define PCI_SCS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c4c, 0) +#define PCI_SCS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d4c, 0) +#define PCI_CS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c50, 0) +#define PCI_CS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d50, 0) +#define PCI_CS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d58, 0) +#define PCI_CS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c54, 0) +#define PCI_ADDR_DECODE_CONTROL(bus) PCI__GEN(bus, 0x0d3c, 0) +#define PCI_BOOTCS_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d54, 0) +#define PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0d5c, 0) +#define PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0d60, 0) +#define PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0d64, 0) +#define PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0d68, 0) +#define PCI_P2P_IO_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d6c, 0) +#define PCI_CPU_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d70, 0) +#define PCI_DAC_SCS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f00, 0) +#define PCI_DAC_SCS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f04, 0) +#define PCI_DAC_SCS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f08, 0) +#define PCI_DAC_SCS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f0c, 0) +#define PCI_DAC_CS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f10, 0) +#define PCI_DAC_CS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f14, 0) +#define PCI_DAC_CS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f18, 0) +#define PCI_DAC_CS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f1c, 0) +#define PCI_DAC_BOOTCS_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f20, 0) +#define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0f24, 0) +#define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0f28, 0) +#define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0f2c, 0) +#define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0f30, 0) +#define PCI_DAC_CPU_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f34, 0) +#define PCI_EXPANSION_ROM_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f38, 0) + +/* + * Table 186: PCI Control Register Map + */ +#define PCI_COMMAND(bus) PCI__GEN(bus, 0x0c00, 0) +#define PCI_MODE(bus) PCI__GEN(bus, 0x0d00, 0) +#define PCI_TIMEOUT_RETRY(bus) PCI__GEN(bus, 0x0c04, 0) +#define PCI_READ_BUFFER_DISCARD_TIMER(bus) PCI__GEN(bus, 0x0d04, 0) +#define PCI_MSI_TRIGGER_TIMER(bus) PCI__GEN(bus, 0x0c38, 0) +#define PCI_ARBITER_CONTROL(bus) PCI__GEN(bus, 0x1d00, 0) +#define PCI_INTERFACE_XBAR_CONTROL_LOW(bus) PCI__GEN(bus, 0x1d08, 0) +#define PCI_INTERFACE_XBAR_CONTROL_HIGH(bus) PCI__GEN(bus, 0x1d0c, 0) +#define PCI_INTERFACE_XBAR_TIMEOUT(bus) PCI__GEN(bus, 0x1d04, 0) +#define PCI_READ_RESPONSE_XBAR_CONTROL_LOW(bus) PCI__GEN(bus, 0x1d18, 0) +#define PCI_READ_RESPONSE_XBAR_CONTROL_HIGH(bus) PCI__GEN(bus, 0x1d1c, 0) +#define PCI_SYNC_BARRIER(bus) PCI__GEN(bus, 0x1d10, 0) +#define PCI_P2P_CONFIGURATION(bus) PCI__GEN(bus, 0x1d14, 0) +#define PCI_P2P_SWAP_CONTROL(bus) PCI__GEN(bus, 0x1d54, 0) +#define PCI_ACCESS_CONTROL_BASE_LOW(bus, n) PCI__GEN(bus, 0x1e00, n) +#define PCI_ACCESS_CONTROL_BASE_HIGH(bus, n) PCI__GEN(bus, 0x1e04, n) +#define PCI_ACCESS_CONTROL_TOP(bus, n) PCI__GEN(bus, 0x1e08, n) + + +/* + * Table 187: PCI Snoop Control Register Map + */ +#define PCI_SNOOP_CONTROL_BASE_LOW(bus, n) PCI__GEN(bus, 0x1f00, n) +#define PCI_SNOOP_CONTROL_BASE_HIGH(bus, n) PCI__GEN(bus, 0x1f04, n) +#define PCI_SNOOP_CONTROL_TOP(bus, n) PCI__GEN(bus, 0x1f08, n) + +/* + * Table 188: PCI Configuration ACCESS_Register Map + */ +#define PCI_CONFIG_ADDR(bus) PCI__GEN(bus, 0x0cf8, 0) +#define PCI_CONFIG_DATA(bus) PCI__GEN(bus, 0x0cfc, 0) +#define PCI_INTR_ACK(bus) PCI__GEN(bus, 0x0c34, 0) + +/* + * Table 189: PCI ERROR Report Register Map + */ +#define PCI_SERR_MASK(bus) PCI__GEN(bus, 0x0c28, 0) +#define PCI_ERROR_ADDRESS_LOW(bus) PCI__GEN(bus, 0x1d40, 0) +#define PCI_ERROR_ADDRESS_HIGH(bus) PCI__GEN(bus, 0x1d44, 0) +#define PCI_ERROR_DATA_LOW(bus) PCI__GEN(bus, 0x1d48, 0) +#define PCI_ERROR_DATA_HIGH(bus) PCI__GEN(bus, 0x1d4c, 0) +#define PCI_ERROR_COMMAND(bus) PCI__GEN(bus, 0x1d50, 0) +#define PCI_ERROR_CAUSE(bus) PCI__GEN(bus, 0x1d58, 0) +#define PCI_ERROR_MASK(bus) PCI__GEN(bus, 0x1d5c, 0) + + + +/* + * Table 223: PCI Base Address Registers Enable + * If a bit is clear, the BAR is enabled. If set, disabled. The GT64260] + * prevents disabling both memory mapped and I/O mapped BARs (bits 9 and 10 + * cannot simultaneously be set to 1). + */ +#define PCI_BARE_SCS0En PCI__BIT(0) /* SCS[0]* BAR Enable */ +#define PCI_BARE_SCS1En PCI__BIT(1) /* SCS[1]* BAR Enable */ +#define PCI_BARE_SCS2En PCI__BIT(2) /* SCS[2]* BAR Enable */ +#define PCI_BARE_SCS3En PCI__BIT(3) /* SCS[3]* BAR Enable */ +#define PCI_BARE_CS0En PCI__BIT(4) /* CS[0]* BAR Enable */ +#define PCI_BARE_CS1En PCI__BIT(5) /* CS[1]* BAR Enable */ +#define PCI_BARE_CS2En PCI__BIT(6) /* CS[2]* BAR Enable */ +#define PCI_BARE_CS3En PCI__BIT(7) /* CS[3]* BAR Enable */ +#define PCI_BARE_BootCSEn PCI__BIT(8) /* BootCS* BAR Enable */ +#define PCI_BARE_IntMemEn PCI__BIT(9) /* Memory Mapped Internal + * Registers BAR Enable */ +#define PCI_BARE_IntIOEn PCI__BIT(10) /* I/O Mapped Internal + * Registers BAR Enable */ +#define PCI_BARE_P2PMem0En PCI__BIT(11) /* P2P Mem0 BAR Enable */ +#define PCI_BARE_P2PMem1En PCI__BIT(12) /* P2P Mem1 BAR Enable */ +#define PCI_BARE_P2PIOEn PCI__BIT(13) /* P2P IO BAR Enable */ +#define PCI_BARE_CPUEn PCI__BIT(14) /* CPU BAR Enable */ +#define PCI_BARE_DSCS0En PCI__BIT(15) /* DAC SCS[0]* BAR Enable */ +#define PCI_BARE_DSCS1En PCI__BIT(16) /* DAC SCS[1]* BAR Enable */ +#define PCI_BARE_DSCS2En PCI__BIT(17) /* DAC SCS[2]* BAR Enable */ +#define PCI_BARE_DSCS3En PCI__BIT(18) /* DAC SCS[3]* BAR Enable */ +#define PCI_BARE_DCS0En PCI__BIT(19) /* DAC CS[0]* BAR Enable */ +#define PCI_BARE_DCS1En PCI__BIT(20) /* DAC CS[1]* BAR Enable */ +#define PCI_BARE_DCS2En PCI__BIT(21) /* DAC CS[2]* BAR Enable */ +#define PCI_BARE_DCS3En PCI__BIT(22) /* DAC CS[3]* BAR Enable */ +#define PCI_BARE_DBootCSEn PCI__BIT(23) /* DAC BootCS* BAR Enable */ +#define PCI_BARE_DP2PMem0En PCI__BIT(24) /* DAC P2P Mem0 BAR Enable */ +#define PCI_BARE_DP2PMem1En PCI__BIT(25) /* DAC P2P Mem1 BAR Enable */ +#define PCI_BARE_DCPUEn PCI__BIT(26) /* DAC CPU BAR Enable */ + +/* + * Table 254: PCI Address Decode Control + * Bits 7:4 and 31:25 are reserved + * 00:00 RemapWrDis Address Remap Registers Write Disable + * 0: Writes to a BAR result in updating the + * corresponding remap register with the BAR's + * new value. + * 1: Writes to a BAR have no affect on the + * corresponding Remap register value. + * 01:01 ExpRomDev Expansion ROM Device (0: CS[3]; 1: BootCS) + * 02:02 VPDDev VPD Device (0: CS[3]; 1: BootCS) + * 03:03 MsgAcc Messaging registers access + * 0: Messaging unit registers are accessible on + * lowest 4Kbyte of SCS[0] BAR space. + * 1: Messaging unit registers are only accessible + * as part of the GT64260 internal space. + * 07:04 Reserved + * 24:08 VPDHighAddr VPD High Address bits + * [31:15] of VPD the address. + * 31:25 Reserved + */ +#define PCI_ADC_RemapWrDis PCI__BIT(0) +#define PCI_ADC_ExpRomDev PCI__BIT(1) +#define PCI_ADC_VPDDev PCI__BIT(2) +#define PCI_ADC_MsgAcc PCI__BIT(3) +#define PCI_ADC_VPDHighAddr_GET(v) PCI__EXT(v, 8, 16) + + +/* + * Table 255: PCI Command + * 00:00 MByteSwap PCI Master Byte Swap + * NOTE: GT-64120 and GT-64130 compatible. + * When set to 0, the GTO64260 PCI master swaps the bytes + * of the incoming and outgoing PCI data (swap the 8 bytes + * of a longword). + * 01:01 Reserved + * 02:02 Reserved Must be 0. + * 03:03 Reserved + * 04:04 MWrCom PCI Master Write Combine Enable + * When set to 1, write combining is enabled. + * 05:05 MRdCom PCI Master Read Combine Enable + * When set to 1, read combining is enabled. + * 06:06 MWrTrig PCI Master Write Trigger + * 0: Accesses the PCI bus only when the whole burst is + * written into the master write buffer. + * 1: Accesses the PCI bus when the first data is written + * into the master write buffer. + * 07:07 MRdTrig PCI Master Read Trigger + * 0: Returns read data to the initiating unit only when + * the whole burst is written into master read buffer. + * 1: Returns read data to the initiating unit when the + * first read data is written into master read buffer. + * 08:08 MRdLine PCI Master Memory Read Line Enable + * (0: Disable; 1: Enable) + * 09:09 MRdMul PCI Master Memory Read Multiple Enable + * (0: Disable; 1: Enable) + * 10:10 MWordSwap PCI Master Word Swap + * NOTE: GT-64120 and GT-64130 compatible. + * When set to 1, the GT64260 PCI master swaps the 32-bit + * words of the incoming and outgoing PCI data. + * 11:11 SWordSwap PCI Slave Word Swap + * NOTE: GT-64120 and GT-64130 compatible. + * When set to 1, the GT64260 PCI slave swaps the 32-bit + * words of the incoming and outgoing PCI data. + * 12:12 IntBusCtl PCI Interface Unit Internal Bus Control + * NOTE: Reserved for Galileo Technology usage + * 0: Enable internal bus sharing between master and + * slave interfaces. + * 1: Disable internal bus sharing between master and + * slave interfaces. + * 13:13 SBDis PCI Slave Sync Barrier Disable + * When set to 1, the PCI configuration read transaction + * will stop act as sync barrier transaction. + * 14:14 Reserved Must be 0 + * 15:15 MReq64 PCI Master REQ64* Enable (0: Disable; 1: Enable) + * 16:16 SByteSwap PCI Slave Byte Swap + * NOTE: GT-64120 and GT-64130 compatible. + * When set to 0, the GT64260 PCI slave swaps the bytes of + * the incoming and outgoing PCI data (swap the 8 bytes of + * a long-word). + * 17:17 MDACEn PCI Master DAC Enable + * 0: Disable (The PCI master never drives the DAC cycle) + * 1: Enable (In case the upper 32-bit address is not 0, + * the PCI master drives the DAC cycle) + * 18:18 M64Allign PCI Master REQ64* assertion on non-aligned + * 0: Disable (The master asserts REQ64* only if + * the address is 64-bit aligned) + * 1: Enable (The master asserts REQ64* even if + * the address is not 64-bit aligned) + * 19:19 PErrProp Parity/ECC Errors Propagation Enable + * 0: Disable (The PCI interface always drives + * correct parity on the PAR signal) + * 1: Enable (In case of slave read bad ECC from + * SDRAM, or master write with bad parity/ECC + * indication from the initiator, the PCI interface + * drives bad parity on the PAR signal) + * 20:20 SSwapEn PCI Slave Swap Enable + * NOTE: Even if the SSwapEn bit is set to 1 and + * the PCI address does not match any of the + * Access Control registers, slave data swapping + * works according to SByteSwap and SWordSwap bits. + * 0: PCI slave data swapping is determined via + * SByteSwap and SWordSwap bits (bits 16 and 11), + * as in the GT-64120/130. + * 1: PCI slave data swapping is determined via PCISwap + * bits [25:24] in the PCI Access Control registers. + * 21:21 MSwapEn PCI Master Swap Enable + * 0: PCI master data swapping is determined via + * MByteSwap and MWordSwap bits (bits 0 and 10), + * as in the GT-64120/130. + * 1: PCI master data swapping is determined via + * PCISwap bits in CPU to PCI Address Decoding + * registers. + * 22:22 MIntSwapEn PCI Master Configuration Transactions Data Swap Enable + * NOTE: Reserved for Galileo Technology usage. + * 0: Disable (The PCI master configuration transaction + * to the PCI bus is always in Little Endian convention) + * 1: Enable (The PCI master configuration transaction to + * the PCI bus is determined according to the setting + * of MSwapEn bit) + * 23:23 LBEn PCI Loop Back Enable + * NOTE: Reserved for Galileo Technology usage. + * 0: Disable (The PCI slave does not respond to + * transactions initiated by the PCI master) + * 1: Enable (The PCI slave does respond to + * transactions initiated by the PCI master, + * if targeted to the slave (address match) + * 26:24 SIntSwap PCI Slave data swap control on PCI accesses to the + * GT64260 internal and configuration registers. + * Bits encoding are the same as bits[26:24] in PCI Access + * Control registers. + * 27:27 Reserved Must be 0. + * 31:28 Reserved Read only. + */ +#define PCI_CMD_MByteSwap PCI__BIT(0) +#define PCI_CMD_MBZ0_2 PCI__BIT(2) +#define PCI_CMD_MWrCom PCI__BIT(4) +#define PCI_CMD_MRdCom PCI__BIT(5) +#define PCI_CMD_MWrTrig PCI__BIT(6) +#define PCI_CMD_MRdTrig PCI__BIT(7) +#define PCI_CMD_MRdLine PCI__BIT(8) +#define PCI_CMD_MRdMul PCI__BIT(9) +#define PCI_CMD_MWordSwap PCI__BIT(10) +#define PCI_CMD_SWordSwap PCI__BIT(11) +#define PCI_CMD_IntBusCtl PCI__BIT(12) +#define PCI_CMD_SBDis PCI__BIT(13) +#define PCI_CMD_MBZ0_14 PCI__BIT(14) +#define PCI_CMD_MReq64 PCI__BIT(15) +#define PCI_CMD_SByteSwap PCI__BIT(16) +#define PCI_CMD_MDCAEn PCI__BIT(17) +#define PCI_CMD_M64Allign PCI__BIT(18) +#define PCI_CMD_PErrProp PCI__BIT(19) +#define PCI_CMD_SSwapEn PCI__BIT(20) +#define PCI_CMD_MSwapEn PCI__BIT(21) +#define PCI_CMD_MIntSwapEn PCI__BIT(22) +#define PCI_CMD_LBEn PCI__BIT(23) +#define PCI_CMD_SIntSwap_GET(v) PCI__EXT(v, 24, 3) +#define PCI_CMD_MBZ0_27 PCI__BIT(27) + + +/* + * Table 256: PCI Mode + * 00:00 PciID PCI Interface ID -- Read Only (PCI_0: 0x0; PCI_1: 0x1) + * 01:01 Reserved + * 02:02 Pci64 64-bit PCI Interface -- Read Only + * When set to 1, the PCI interface is configured to a + * 64 bit interface. + * 07:03 Reserved + * 08:08 ExpRom Expansion ROM Enable -- Read Only from PCI + * When set to 1, the expansion ROM BAR is enabled. + * 09:09 VPD VPD Enable -- Read Only from PCI + * When set to 1, VPD is supported. + * 10:10 MSI MSI Enable -- Read Only from PCI + * When set to 1, MSI is supported. + * 11:11 PMG Power Management Enable -- Read Only from PCI + * When set to 1, PMG is supported. + * 12:12 HotSwap CompactPCI Hot Swap Enable -- Read Only from PCI + * When set to 1, HotSwap is supported. + * 13:13 BIST BIST Enable -- Read only from PCI + * If set to 1, BIST is enabled. + * 30:14 Reserved + * 31:31 PRst PCI Interface Reset Indication -- Read Only + * Set to 0 as long as the RST* pin is asserted. + */ +#define PCI_MODE_PciID_GET(v) PCI__EXT(v, 0, 1) +#define PCI_MODE_Pci64 PCI__BIT(2) +#define PCI_MODE_ExpRom PCI__BIT(8) +#define PCI_MODE_VPD PCI__BIT(9) +#define PCI_MODE_MSI PCI__BIT(10) +#define PCI_MODE_PMG PCI__BIT(11) +#define PCI_MODE_HotSwap PCI__BIT(12) +#define PCI_MODE_BIST PCI__BIT(13) +#define PCI_MODE_PRst PCI__BIT(31) + +/* + * Table 257: PCI Timeout and Retry + * 07:00 Timeout0 Specifies the number of PClk cycles the GT64260 slave + * holds the PCI bus before terminating a transaction + * with RETRY. + * 15:08 Timeout1 Specifies the number of PClk cycles the GT64260 slave + * holds the PCI bus before terminating a transaction + * with DISCONNECT. + * 23:16 RetryCtr Retry Counter + * Specifies the number of retries of the GT64260 Master. + * The GT64260 generates an interrupt when this timer + * expires. A 0x00 value means a retry forever. + * 31:24 Reserved + */ +#define PCI_TMORTRY_Timeout0_GET(v) PCI__EXT(v, 0, 8) +#define PCI_TMORTRY_Timeout1_GET(v) PCI__EXT(v, 8, 8) +#define PCI_TMORTRY_RetryCtr_GET(v) PCI__EXT(v, 16, 8) + + +/* + * Table 258: PCI Read Buffer Discard Timer + * 15:00 Timer Specifies the number of PClk cycles the GT64260 + * slave keeps an non-accessed read buffers (non com- + * pleted delayed read) before invalidating the buffer. + * 23:16 RdBufEn Slave Read Buffers Enable + * Each bit corresponds to one of the eight read buffers. + * If set to 1, buffer is enabled. + * 31:24 Reserved + */ +#define PCI_RdBufDisTmr_Timer_GET(v) PCI__EXT(v, 0, 16) +#define PCI_RdBufDisTmr_RdBufEn_GET(v) PCI__EXT(v, 16, 8) +#define PCI_RdBufDisTmr_RdBufEn0(v) PCI__BIT(16) +#define PCI_RdBufDisTmr_RdBufEn1(v) PCI__BIT(17) +#define PCI_RdBufDisTmr_RdBufEn2(v) PCI__BIT(18) +#define PCI_RdBufDisTmr_RdBufEn3(v) PCI__BIT(19) +#define PCI_RdBufDisTmr_RdBufEn4(v) PCI__BIT(20) +#define PCI_RdBufDisTmr_RdBufEn5(v) PCI__BIT(21) +#define PCI_RdBufDisTmr_RdBufEn6(v) PCI__BIT(22) +#define PCI_RdBufDisTmr_RdBufEn7(v) PCI__BIT(23) + +/* + * Table 259: MSI Trigger Timer + * 15:00 Timer Specifies the number of TClk cycles between consecutive + * MSI requests. + * 31:16 Reserved + */ +#define PCI_MSITrigger_Timer_GET(v) PCI__EXT(v, 0, 16) + +/* + * Table 260: PCI Arbiter Control + * NOTE: If HPPV (bits [28:21]) is set to 0 and PAEn is set to 1, + * priority scheme is reversed. This means that high priority + * requests are granted if no low priority request is pending. + * 00:00 Reserved Must be 0. 0x0 + * 01:01 BDEn Broken Detection Enable + * If set to 1, broken master detection is enabled. A mas- + * ter is said to be broken if it fails to respond to grant + * assertion within a window specified in BV (bits [6:3]). + * 02:02 PAEn Priority Arbitration Enable + * 0: Low priority requests are granted only when no high + * priority request is pending + * 1: Weighted round robin arbitration is performed + * between high priority and low priority groups. + * 06:03 BV Broken Value + * This value sets the maximum number of cycles that the + * arbiter waits for a PCI master to respond to its grant + * assertion. If a PCI master fails to assert FRAME* within + * this time, the PCI arbiter aborts the transaction and + * performs a new arbitration cycle and a maskable + * interrupt is generated. Must be greater than 0. + * NOTE: The PCI arbiter waits for the current + * transaction to end before starting to + * count the wait-for-broken cycles. + * Must be greater than 1 for masters that performs address + * stepping (such as the GTO 64260 PCI master), since they + * require GNT* assertion for two cycles. + * 13:07 P[6:0] Priority + * These bits assign priority levels to the requests + * connected to the PCI arbiter. When a PM bit is set to + * 1, priority of the associated request is high. The + * mapping between P[6:0] bits and the request/grant pairs + * are as follows: + * P[0]: internal PCI master P[1]: external REQ0/GNT0 + * P[2]: external REQ1/GNT1 P[3]: external REQ2/GNT2 + * P[4]: external REQ3/GNT3 P[5]: external REQ4/GNT4 + * P[6]: external REQ5/GNT5 + * 20:14 PD[6:0] Parking Disable + * Use these bits to disable parking on any of the PCI + * masters. When a PD bit is set to 1, parking on the + * associated PCI master is disabled. + * NOTE: The arbiter parks on the last master granted + * unless disabled through the PD bit. Also, if + * PD bits are all 1, the PCI arbiter parks on + * the internal PCI master. + * 28:21 HPPV High Priority Preset Value + * This is the preset value of the high priority counter + * (High_cnt). This counter decrements each time a high + * priority request is granted. When the counter reaches + * zero, it reloads with this preset value. The counter + * reloads when a low priority request is granted. + * 30:29 Reserved + * 31:31 EN Enable + * Setting this bit to 1 enables operation of the arbiter. + */ +#define PCI_ARBCTL_MBZ0_0 PCI__BIT(0) +#define PCI_ARBCTL_BDEn PCI__BIT(1) +#define PCI_ARBCTL_PAEn PCI__BIT(2) +#define PCI_ARBCTL_BV_GET(v) PCI__EXT(v, 3, 4) +#define PCI_ARBCTL_P_GET(v) PCI__EXT(v, 7, 7) +#define PCI_ARBCTL_PD_GET(v) PCI__EXT(v, 14, 7) +#define PCI_ARBCTL_HPPV_GET(v) PCI__EXT(v, 21, 7) +#define PCI_ARBCTL_EN PCI__BIT(31) + +#define PCI_ARBPRI_IntPci PCI__BIT(0) +#define PCI_ARBPRI_ExtReqGnt0 PCI__BIT(1) +#define PCI_ARBPRI_ExtReqGnt1 PCI__BIT(2) +#define PCI_ARBPRI_EXtReqGnt2 PCI__BIT(3) +#define PCI_ARBPRI_EXtReqGnt3 PCI__BIT(4) +#define PCI_ARBPRI_EXtReqGnt4 PCI__BIT(5) +#define PCI_ARBPRI_EXtReqGnt5 PCI__BIT(6) + +/* + * Table 261: PCI Interface Crossbar Control (Low) + * 03:00 Arb0 Slice 0 of PCI master pizza arbiter. + * 07:04 Arb1 Slice 1 of PCI master pizza arbiter. + * 11:08 Arb2 Slice 2 of PCI master pizza arbiter. + * 15:12 Arb3 Slice 3 of PCI master pizza arbiter. + * 19:16 Arb4 Slice 4 of PCI master pizza arbiter. + * 23:20 Arb5 Slice 5 of PCI master pizza arbiter. + * 27:24 Arb6 Slice 6 of PCI master pizza arbiter. + * 31:28 Arb7 Slice 7 of PCI master pizza arbiter. + */ +#define PCI_IFXBRCTL_GET_SLICE(v, n) PCI__EXT(v, (n) * 4, 4) +#define PCI_IFXBRCTL_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, (n)*4, 4),\ + (v) |= PCI__INS((n)*4, s))) + +/* + * Table 262: PCI Interface Crossbar Control (High) + * 03:00 Arb8 Slice 8 of PCI master pizza arbiter. + * 07:04 Arb9 Slice 9 of PCI master pizza arbiter. + * 11:08 Arb10 Slice 10 of PCI master pizza arbiter. + * 15:12 Arb11 Slice 11 of PCI master pizza arbiter. + * 19:16 Arb12 Slice 12 of PCI master pizza arbiter. + * 23:20 Arb13 Slice 13 of PCI master pizza arbiter. + * 27:24 Arb14 Slice 14 of PCI master pizza arbiter. + * 31:28 Arb15 Slice 15 of PCI master pizza arbiter. + */ +#define PCI_IFXBRCH_GET_SLICE(v, n) PCI__EXT(v, ((n) - 8) * 4, 4) +#define PCI_IFXBRCH_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, ((n)*-8)4, 4),\ + (v) |= PCI__INS(((n)-8)*4, s))) + +/* + * Table 263: PCI Interface Crossbar Timeout + (NOTE: Reserved for Galileo Technology usage.) + * 07:00 Timeout Crossbar Arbiter Timeout Preset Value + * 15:08 Reserved + * 16:16 TimeoutEn Crossbar Arbiter Timer Enable (1: Disable) + * 31:17 Reserved + */ +#define PCI_IFXBRTMO_Timeout_GET(v) PCI__EXT(v, 0, 8) +#define PCI_IFXBRTMO_TimeoutEn PCI__BIT(16) + +/* + * Table 264: PCI Read Response Crossbar Control (Low) + * 03:00 Arb0 Slice 0 of PCI slave pizza arbiter. + * 07:04 Arb1 Slice 1 of PCI slave pizza arbiter. + * 11:08 Arb2 Slice 2 of PCI slave pizza arbiter. + * 15:12 Arb3 Slice 3 of PCI slave pizza arbiter. + * 19:16 Arb4 Slice 4 of PCI slave pizza arbiter. + * 23:20 Arb5 Slice 5 of PCI slave pizza arbiter. + * 27:24 Arb6 Slice 6 of PCI slave pizza arbiter. + * 31:28 Arb7 Slice 7 of PCI slave pizza arbiter. + */ +#define PCI_RRXBRCL_GET_SLICE(v, n) PCI__EXT(v, (n) * 4, 4) +#define PCI_RRXBRCL_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, (n)*4, 4),\ + (v) |= PCI__INS((n)*4, s))) + + +/* + * Table 265: PCI Read Response Crossbar Control (High) + * 03:00 Arb8 Slice 8 of PCI slave pizza arbiter. + * 07:04 Arb9 Slice 9 of PCI slave pizza arbiter. + * 11:08 Arb10 Slice 10 of PCI slave pizza arbiter. + * 15:12 Arb11 Slice 11 of PCI slave pizza arbiter. + * 19:16 Arb12 Slice 12 of PCI slave pizza arbiter. + * 23:20 Arb13 Slice 13 of PCI slave pizza arbiter. + * 27:24 Arb14 Slice 14 of PCI slave pizza arbiter. + * 31:28 Arb15 Slice 15 of PCI slave pizza arbiter. + */ +#define PCI_RRXBRCH_GET_SLICE(v, n) PCI__EXT(v, ((n) - 8) * 4, 4) +#define PCI_RRXBRCH_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, ((n)*-8)4, 4),\ + (v) |= PCI__INS(((n)-8)*4, s))) + +/* + * Table 266: PCI Sync Barrier Virtual Register + * 31:0 SyncReg Sync Barrier Virtual Register + * PCI read from this register results in PCI slave sync barrier + * action. The returned data is un-deterministic. Read Only. + */ + +/* + * Table 267: PCI P2P Configuration + * 07:00 2ndBusL Secondary PCI Interface Bus Range Lower Boundary + * 15:08 2ndBusH Secondary PCI Interface Bus Range Upper Boundary + * 23:16 BusNum The PCI bus number to which the PCI interface + * is connected. + * 28:24 DevNum The PCI interface's device number. + * 31:29 Reserved Reserved. + */ +#define PCI_P2PCFG_2ndBusL_GET(v) PCI__EXT(v, 0, 8) +#define PCI_P2PCFG_2ndBusH_GET(v) PCI__EXT(v, 8, 8) +#define PCI_P2PCFG_BusNum_GET(v) PCI__EXT(v, 16, 8) +#define PCI_P2PCFG_DevNum_GET(v) PCI__EXT(v, 24, 5) + +/* + * Table 268: PCI P2P Swap Control + * 02:00 M0Sw P2P Mem0 BAR Swap Control + * 03:03 M0Req64 P2P Mem0 BAR Force REQ64 + * 06:04 M1Sw P2P Mem1 BAR Swap Control + * 07:07 M1Req64 P2P Mem1 BAR Force REQ64 + * 10:08 DM0Sw P2P DAC Mem0 BAR Swap Control + * 11:11 DM0Req64 P2P DAC Mem0 BAR Force REQ64 + * 14:12 DM1Sw P2P DAC Mem1 BAR Swap Control + * 15:15 DM1Req64 P2P DAC Mem1 BAR Force REQ64 + * 18:16 IOSw P2P I/O BAR Swap Control + * 19:19 Reserved + * 22:20 CfgSw P2P Configuration Swap Control + * 31:19 Reserved + */ +#define PCI_P2PSWAP_M0Sw_GET(v) PCI__EXT(v, 0, 3) +#define PCI_P2PSWAP_M0Req64 PCI__BIT(3) +#define PCI_P2PSWAP_M1Sw_GET(v) PCI__EXT(v, 4, 3) +#define PCI_P2PSWAP_M1Req64 PCI__BIT(7) +#define PCI_P2PSWAP_DM0Sw_GET(v) PCI__EXT(v, 8, 3) +#define PCI_P2PSWAP_DM0Req64 PCI__BIT(11) +#define PCI_P2PSWAP_DM1Sw_GET(v) PCI__EXT(v, 12, 3) +#define PCI_P2PSWAP_DM1Req64 PCI__BIT(15) +#define PCI_P2PSWAP_CfgSw_GET(v) PCI__EXT(v, 20, 3) + + + +/* + * Table 269: PCI Access Control Base (Low) + * 11:00 Addr Base Address Corresponds to address bits[31:20]. + * 12:12 PrefetchEn Read Prefetch Enable + * 0: Prefetch disabled (The PCI slave reads single words) + * 1: Prefetch enabled. + * 14:14 Reserved Must be 0 + * 15:15 Reserved + * 16:16 RdPrefetch PCI Read Aggressive Prefetch Enable; 0: Disable; + * 1: Enable (The PCI slave prefetches two + * bursts in advance) + * 17:17 RdLinePrefetch PCI Read Line Aggressive Prefetch Enable; 0: Disable; + * 1: Enable (PCI slave prefetch two bursts in advance) + * 18:18 RdMulPrefetch PCI Read Multiple Aggressive Prefetch Enable + * 0: Disable; 1: Enable (PCI slave prefetch two bursts in + * advance) + * 19:19 Reserved + * 21:20 MBurst PCI Max Burst + * Specifies the maximum burst size for a single transac- + * tion between a PCI slave and the other interfaces + * 00 - 4 64-bit words + * 01 - 8 64-bit words + * 10 - 16 64-bit words + * 11 - Reserved + * 23:22 Reserved + * 25:24 PCISwap Data Swap Control + * 00 - Byte Swap + * 01 - No swapping + * 10 - Both byte and word swap + * 11 - Word swap + * 26:26 Reserved Must be 0 + * 27:27 Reserved + * 28:28 AccProt Access Protect (0: PCI access is allowed; 1; Region is + not accessible from PCI) + * 29:29 WrProt Write Protect (0: PCI write is allowed; 1: Region is + * not writeable from PCI) + * 31:30 Reserved + */ +#define PCI_ACCCTLBASEL_Addr_GET(v) PCI__EXT(v, 0, 12) +#define PCI_ACCCTLBASEL_PrefetchEn PCI__BIT(12) +#define PCI_ACCCTLBASEL_MBZ0_14 PCI__BIT(14) +#define PCI_ACCCTLBASEL_RdPrefetch PCI__BIT(16) +#define PCI_ACCCTLBASEL_RdLinePrefetch PCI__BIT(17) +#define PCI_ACCCTLBASEL_RdMulPrefetch PCI__BIT(18) +#define PCI_ACCCTLBASEL_WBurst PCI__EXT(v, 20, 2) +#define PCI_ACCCTLBASEL_WBurst_8_QW PCI__INS(20, PCI_WBURST_8_QW) +#define PCI_ACCCTLBASEL_PCISwap PCI__EXT(v, 24, 2) +#define PCI_ACCCTLBASEL_PCISwap_NoSwap PCI__INS(24, PCI_PCISWAP_NoSwap) +#define PCI_ACCCTLBASEL_MBZ0_26 PCI__BIT(26) +#define PCI_ACCCTLBASEL_AccProt PCI__BIT(28) +#define PCI_ACCCTLBASEL_WrProt PCI__BIT(29) + +#define PCI_WBURST_4_QW 0x00 +#define PCI_WBURST_8_QW 0x01 +#define PCI_WBURST_16_QW 0x02 +#define PCI_WBURST_Reserved 0x04 + +#define PCI_PCISWAP_ByteSwap 0x00 +#define PCI_PCISWAP_NoSwap 0x01 +#define PCI_PCISWAP_ByteWordSwap 0x02 +#define PCI_PCISWAP_WordSwap 0x04 + +/* + * Table 293: PCI Snoop Control Base (Low) + * 11:00 Addr Base Address Corresponds to address bits[31:20]. + * 13:12 Snoop Snoop Type + * 31:14 Reserved + */ +#define PCI_SNOOPCTL_ADDR(v) PCI__EXT(v, 0, 12) +#define PCI_SNOOPCTL_TYPE(v) PCI__EXT(v, 12, 2) + +#define PCI_SNOOP_None 0 /* no snoop */ +#define PCI_SNOOP_WT 1 /* Snoop to WT region */ +#define PCI_SNOOP_WB 2 /* Snoop to WB region */ + + +/* + * Table 305: PCI Configuration Address + * + * 07:02 RegNum Register number. + * 10:08 FunctNum Function number. + * 15:11 DevNum Device number. + * 23:16 BusNum Bus number. + * 31:31 ConfigEn When set, an access to the Configuration Data + * register is translated into a Configuration + * or Special cycle on the PCI bus. + */ +#define PCI_CFG_MAKE_TAG(bus, dev, fun, reg) (PCI__BIT(31)|\ + PCI__INS(16, (bus))|\ + PCI__INS(11, (dev))|\ + PCI__INS( 8, (fun))|\ + PCI__INS( 0, (reg))) +#define PCI_CFG_GET_BUSNO(tag) PCI__EXT(tag, 16, 8) +#define PCI_CFG_GET_DEVNO(tag) PCI__EXT(tag, 11, 5) +#define PCI_CFG_GET_FUNCNO(tag) PCI__EXT(tag, 8, 3) +#define PCI_CFG_GET_REGNO(tag) PCI__EXT(tag, 0, 8) + +/* + * Table 306: PCI Configuration Data + * + * 31:00 ConfigData The data is transferred to/from the PCI bus when + * the CPU accesses this register and the ConfigEn + * bit in the Configuration Address register is set + * + * A CPU access to this register causes the GT64260 to perform a Configuration + * or Special cycle on the PCI bus. + */ + + +/* + * Table 307: PCI Interrupt Acknowledge (This register is READ ONLY) + * 31:00 IntAck A CPU read access to this register forces an + * interrupt acknowledge cycle on the PCI bus. + */ + + +/* + * Table 308: PCI SERR* Mask + * + * NOTE: The GT64260 asserts SERR* only if SERR* is enabled via the PCI Status + * and Command register. + * If the corresponding bit is set, then asserts SERR* upon ... + */ +#define PCI_SERRMSK_SAPerr PCI__BIT(0) /* PCI slave detection of bad + * address parity. */ +#define PCI_SERRMSK_SWrPerr PCI__BIT(1) /* PCI slave detection of bad + * write data parity. */ +#define PCI_SERRMSK_SRdPerr PCI__BIT(2) /* a PERR* response to read + * data driven by the PCI + * slave. */ +#define PCI_SERRMSK_MAPerr PCI__BIT(4) /* a PERR* response to an + * address driven by the PCI + * master. */ +#define PCI_SERRMSK_MWrPerr PCI__BIT(5) /* a PERR* response to write + * data driven by the PCI + * master. */ +#define PCI_SERRMSK_MRdPerr PCI__BIT(6) /* bad data parity detection + * during a PCI master read + * transaction. */ +#define PCI_SERRMSK_MMabort PCI__BIT(8) /* a PCI master generation of + * master abort. */ +#define PCI_SERRMSK_MTabort PCI__BIT(9) /* a PCI master detection of + * target abort. */ +#define PCI_SERRMSK_MRetry PCI__BIT(11) /* a PCI master reaching retry + * counter limit. */ +#define PCI_SERRMSK_SMabort PCI__BIT(16) /* a PCI slave detection of + * master abort. */ +#define PCI_SERRMSK_STabort PCI__BIT(17) /* a PCI slave termination of + * a transaction with Target + * Abort. */ +#define PCI_SERRMSK_SAccProt PCI__BIT(18) /* a PCI slave access protect + * violation. */ +#define PCI_SERRMSK_SWrProt PCI__BIT(19) /* a PCI slave write protect + * violation. */ +#define PCI_SERRMSK_SRdBuf PCI__BIT(20) /* the PCI slave's read buffer, + * discard timer expires */ +#define PCI_SERRMSK_Arb PCI__BIT(21) /* the internal PCI arbiter + * detection of a broken PCI + * master. */ + +#define PCI_SERRMSK_ALL_ERRS \ + (PCI_SERRMSK_SAPerr|PCI_SERRMSK_SWrPerr|PCI_SERRMSK_SRdPerr \ + |PCI_SERRMSK_MAPerr|PCI_SERRMSK_MWrPerr|PCI_SERRMSK_MRdPerr \ + |PCI_SERRMSK_MMabort|PCI_SERRMSK_MTabort|PCI_SERRMSK_MRetry \ + |PCI_SERRMSK_SMabort|PCI_SERRMSK_STabort|PCI_SERRMSK_SAccProt \ + |PCI_SERRMSK_SWrProt|PCI_SERRMSK_SRdBuf|PCI_SERRMSK_Arb) + + + +/* + * Table 309: PCI Error Address (Low) -- Read Only. + * 31:00 ErrAddr PCI address bits [31:0] are latched upon an error + * condition. Upon address latch, no new addresses can + * be registered (due to additional error condition) until + * the register is being read. + */ + + + +/* + * Table 310: PCI Error Address (High) Applicable only when running DAC cycles. + * 31:00 ErrAddr PCI address bits [63:32] are latched upon + * error condition. + * + * NOTE: Upon data sample, no new data is latched until the PCI Error Low + * Address register is read. This means that PCI Error Low Address + * register must bethe last register read by the interrupt handler. + */ + +/* + * Table 311: PCI Error Data (Low) + * 31:00 ErrData PCI data bits [31:00] are latched upon error condition. + */ + +/* + * Table 312: PCI Error Data (High) Applicable only when running + * 64-bit cycles. + * 31:00 ErrData PCI data bits [63:32] are latched upon error condition. + */ + +/* + * Table 313: PCI Error Command + * 03:00 ErrCmd PCI command is latched upon error condition. + * 07:04 Reserved + * 15:08 ErrBE PCI byte enable is latched upon error condition. + * 16:16 ErrPAR PCI PAR is latched upon error condition. + * 17:17 ErrPAR64 PCI PAR64 is latched upon error condition. + * Applicable only when running 64-bit cycles. + * 31:18 Reserved + * NOTE: Upon data sample, no new data is latched until the PCI Error Low + * Address register is read. This means that PCI Error Low Address register + * must be the last register read by the interrupt handler. + */ +#define PCI_ERRCMD_Cmd_GET(v) PCI__EXT(v, 0, 4) +#define PCI_ERRCMD_ByteEn_GET(v) PCI__EXT(v, 8, 8) +#define PCI_ERRCMD_PAR PCI__BIT(16) +#define PCI_ERRCMD_PAR64 PCI__BIT(17) + +/* + * Table 314: PCI Interrupt Cause + * 1. All bits are Clear Only. A cause bit set upon error event occurrence. + * A write of 0 clears the bit. A write of 1 has no affect. + * 2. PCI Interrupt bits are organized in four groups: + * bits[ 7: 0] for address and data parity errors, + * bits[15: 8] for PCI master transaction failure (possible external + * target problem), + * bits[23:16] for slave response failure (possible external master problem), + * bits[26:24] for external PCI events that require CPU handle. + */ +#define PCI_IC_SAPerr PCI__BIT(0) /* The PCI slave detected + * bad address parity. */ +#define PCI_IC_SWrPerr PCI__BIT(1) /* The PCI slave detected + * bad write data parity. */ +#define PCI_IC_SRdPerr PCI__BIT(2) /* PERR* response to read + * data driven by PCI slave. */ +#define PCI_IC_MAPerr PCI__BIT(4) /* PERR* response to address + * driven by the PCI master. */ +#define PCI_IC_MWrPerr PCI__BIT(5) /* PERR* response to write data + * driven by the PCI master. */ +#define PCI_IC_MRdPerr PCI__BIT(6) /* Bad data parity detected + * during the PCI master read + * transaction. */ +#define PCI_IC_MMabort PCI__BIT(8) /* The PCI master generated + * master abort. */ +#define PCI_IC_MTabort PCI__BIT(9) /* The PCI master detected + * target abort. */ +#define PCI_IC_MMasterEn PCI__BIT(10) /* An attempt to generate a PCI + * transaction while master is + * not enabled. */ +#define PCI_IC_MRetry PCI__BIT(11) /* The PCI master reached + * retry counter limit. */ +#define PCI_IC_SMabort PCI__BIT(16) /* The PCI slave detects an il- + * legal master termination. */ +#define PCI_IC_STabort PCI__BIT(17) /* The PCI slave terminates a + * transaction with Target + * Abort. */ +#define PCI_IC_SAccProt PCI__BIT(18) /* A PCI slave access protect + * violation. */ +#define PCI_IC_SWrProt PCI__BIT(19) /* A PCI slave write protect + * violation. */ +#define PCI_IC_SRdBuf PCI__BIT(20) /* A PCI slave read buffer + * discard timer expired. */ +#define PCI_IC_Arb PCI__BIT(21) /* Internal PCI arbiter detec- + * tion of a broken master. */ +#define PCI_IC_BIST PCI__BIT(24) /* PCI BIST Interrupt */ +#define PCI_IC_PMG PCI__BIT(25) /* PCI Power Management + * Interrupt */ +#define PCI_IC_PRST PCI__BIT(26) /* PCI Reset Assert */ + +/* +31:27 Sel Specifies the error event currently being reported in the +Error Address, Error Data, and Error Command registers. +*/ +#define PCI_IC_SEL_GET(v) PCI__EXT((v), 27, 5) +#define PCI_IC_SEL_SAPerr 0x00 +#define PCI_IC_SEL_SWrPerr 0x01 +#define PCI_IC_SEL_SRdPerr 0x02 +#define PCI_IC_SEL_MAPerr 0x04 +#define PCI_IC_SEL_MWrPerr 0x05 +#define PCI_IC_SEL_MRdPerr 0x06 +#define PCI_IC_SEL_MMabort 0x08 +#define PCI_IC_SEL_MTabort 0x09 +#define PCI_IC_SEL_MMasterEn 0x0a +#define PCI_IC_SEL_MRetry 0x0b +#define PCI_IC_SEL_SMabort 0x10 +#define PCI_IC_SEL_STabort 0x11 +#define PCI_IC_SEL_SAccProt 0x12 +#define PCI_IC_SEL_SWrProt 0x13 +#define PCI_IC_SEL_SRdBuf 0x14 +#define PCI_IC_SEL_Arb 0x15 +#define PCI_IC_SEL_BIST 0x18 +#define PCI_IC_SEL_PMG 0x19 +#define PCI_IC_SEL_PRST 0x1a + +#define PCI_IC_SEL_Strings { \ + "SAPerr", "SWrPerr", "SRdPerr", "Rsvd#03", \ + "MAPerr", "MWrPerr", "MRdPerr", "Rsvd#07", \ + "MMabort", "MTabort", "MMasterEn", "MRetry", \ + "Rsvd#0c", "Rsvd#0d", "Rsvd#0e", "Rsvd#0f", \ + "SMabort", "STabort", "SAccProt", "SWrProt", \ + "SRdBuf", "Arb", "Rsvd#16", "Rsvd#17", \ + "BIST", "PMG", "PRST", "Rsvd#1b", \ + "Rsvd#1c", "Rsvd#1d", "Rsvd#1e", "Rsvd#1f" } + +/* + * Table 315: PCI Error Mask + * If the corresponding bit is 1, that interrupt is enabled + * Bits 3, 7, 12:15, 22:23, 27:31 are reserved. + */ +#define PCI_ERRMASK_SAPErr PCI__BIT(0) +#define PCI_ERRMASK_SWrPErr PCI__BIT(1) +#define PCI_ERRMASK_SRdPErr PCI__BIT(2) +#define PCI_ERRMASK_MAPErr PCI__BIT(4) +#define PCI_ERRMASK_MWRPErr PCI__BIT(5) +#define PCI_ERRMASK_MRDPErr PCI__BIT(6) +#define PCI_ERRMASK_MMAbort PCI__BIT(8) +#define PCI_ERRMASK_MTAbort PCI__BIT(9) +#define PCI_ERRMASK_MMasterEn PCI__BIT(10) +#define PCI_ERRMASK_MRetry PCI__BIT(11) +#define PCI_ERRMASK_SMAbort PCI__BIT(16) +#define PCI_ERRMASK_STAbort PCI__BIT(17) +#define PCI_ERRMASK_SAccProt PCI__BIT(18) +#define PCI_ERRMASK_SWrProt PCI__BIT(19) +#define PCI_ERRMASK_SRdBuf PCI__BIT(20) +#define PCI_ERRMASK_Arb PCI__BIT(21) +#define PCI_ERRMASK_BIST PCI__BIT(24) +#define PCI_ERRMASK_PMG PCI__BIT(25) +#define PCI_ERRMASK_PRST PCI__BIT(26) + +#endif /* _DEV_GTPCIREG_H_ */ diff --git a/bsps/powerpc/beatnik/include/bsp/gtreg.h b/bsps/powerpc/beatnik/include/bsp/gtreg.h new file mode 100644 index 0000000000..a6c87e2047 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/gtreg.h @@ -0,0 +1,854 @@ +/* $NetBSD: gtreg.h,v 1.2 2005/02/27 00:27:21 perry Exp $ */ + +/* + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DISCOVERY_DEV_GTREG_H_ +#define _DISCOVERY_DEV_GTREG_H_ + + +#define GT__BIT(bit) (1U << (bit)) +#define GT__MASK(bit) (GT__BIT(bit) - 1) +#define GT__EXT(data, bit, len) (((data) >> (bit)) & GT__MASK(len)) +#define GT__CLR(data, bit, len) ((data) &= ~(GT__MASK(len) << (bit))) +#define GT__INS(new, bit) ((new) << (bit)) + + +/* + * Table 30: CPU Address Decode Register Map + */ +#define GT_SCS0_Low_Decode 0x0008 +#define GT_SCS0_High_Decode 0x0010 +#define GT_SCS1_Low_Decode 0x0208 +#define GT_SCS1_High_Decode 0x0210 +#define GT_SCS2_Low_Decode 0x0018 +#define GT_SCS2_High_Decode 0x0020 +#define GT_SCS3_Low_Decode 0x0218 +#define GT_SCS3_High_Decode 0x0220 +#define GT_CS0_Low_Decode 0x0028 +#define GT_CS0_High_Decode 0x0030 +#define GT_CS1_Low_Decode 0x0228 +#define GT_CS1_High_Decode 0x0230 +#define GT_CS2_Low_Decode 0x0248 +#define GT_CS2_High_Decode 0x0250 +#define GT_CS3_Low_Decode 0x0038 +#define GT_CS3_High_Decode 0x0040 +#define GT_BootCS_Low_Decode 0x0238 +#define GT_BootCS_High_Decode 0x0240 +#define GT_PCI0_IO_Low_Decode 0x0048 +#define GT_PCI0_IO_High_Decode 0x0050 +#define GT_PCI0_Mem0_Low_Decode 0x0058 +#define GT_PCI0_Mem0_High_Decode 0x0060 +#define GT_PCI0_Mem1_Low_Decode 0x0080 +#define GT_PCI0_Mem1_High_Decode 0x0088 +#define GT_PCI0_Mem2_Low_Decode 0x0258 +#define GT_PCI0_Mem2_High_Decode 0x0260 +#define GT_PCI0_Mem3_Low_Decode 0x0280 +#define GT_PCI0_Mem3_High_Decode 0x0288 +#define GT_PCI1_IO_Low_Decode 0x0090 +#define GT_PCI1_IO_High_Decode 0x0098 +#define GT_PCI1_Mem0_Low_Decode 0x00a0 +#define GT_PCI1_Mem0_High_Decode 0x00a8 +#define GT_PCI1_Mem1_Low_Decode 0x00b0 +#define GT_PCI1_Mem1_High_Decode 0x00b8 +#define GT_PCI1_Mem2_Low_Decode 0x02a0 +#define GT_PCI1_Mem2_High_Decode 0x02a8 +#define GT_PCI1_Mem3_Low_Decode 0x02b0 +#define GT_PCI1_Mem3_High_Decode 0x02b8 +#define GT_Internal_Decode 0x0068 +#define GT_CPU0_Low_Decode 0x0290 +#define GT_CPU0_High_Decode 0x0298 +#define GT_CPU1_Low_Decode 0x02c0 +#define GT_CPU1_High_Decode 0x02c8 +/* ts, 2005/8: it seems that these are implicitely written + * when setting the 'Low_Decode' regs... + */ +#define GT_PCI0_IO_Remap 0x00f0 +#define GT_PCI0_Mem0_Remap_Low 0x00f8 +#define GT_PCI0_Mem0_Remap_High 0x0320 +#define GT_PCI0_Mem1_Remap_Low 0x0100 +#define GT_PCI0_Mem1_Remap_High 0x0328 +#define GT_PCI0_Mem2_Remap_Low 0x02f8 +#define GT_PCI0_Mem2_Remap_High 0x0330 +#define GT_PCI0_Mem3_Remap_Low 0x0300 +#define GT_PCI0_Mem3_Remap_High 0x0338 +#define GT_PCI1_IO_Remap 0x0108 +#define GT_PCI1_Mem0_Remap_Low 0x0110 +#define GT_PCI1_Mem0_Remap_High 0x0340 +#define GT_PCI1_Mem1_Remap_Low 0x0118 +#define GT_PCI1_Mem1_Remap_High 0x0348 +#define GT_PCI1_Mem2_Remap_Low 0x0310 +#define GT_PCI1_Mem2_Remap_High 0x0350 +#define GT_PCI1_Mem3_Remap_Low 0x0318 +#define GT_PCI1_Mem3_Remap_High 0x0358 + + +/* + * Table 31: CPU Control Register Map + */ +#define GT_CPU_Cfg 0x0000 +#define GT_CPU_Mode 0x0120 +#define GT_CPU_Master_Ctl 0x0160 +#define GT_CPU_If_Xbar_Ctl_Low 0x0150 +#define GT_CPU_If_Xbar_Ctl_High 0x0158 +#define GT_CPU_If_Xbar_Timeout 0x0168 +#define GT_260_CPU_Rd_Rsp_Xbar_Ctl_Low 0x0170 +#define GT_260_CPU_Rd_Rsp_Xbar_Ctl_High 0x0178 + +/* + * Table 32: CPU Sync Barrier Register Map + */ +#define GT_260_PCI_Sync_Barrier(bus) (0x00c0 | ((bus) << 3)) +#define GT_260_PCI0_Sync_Barrier 0x00c0 +#define GT_260_PCI1_Sync_Barrier 0x00c8 + +/* + * Table 33: CPU Access Protection Register Map + */ +#define GT_Protect_Low_0 0x0180 +#define GT_Protect_High_0 0x0188 +#define GT_Protect_Low_1 0x0190 +#define GT_Protect_High_1 0x0198 +#define GT_Protect_Low_2 0x01a0 +#define GT_Protect_High_2 0x01a8 +#define GT_Protect_Low_3 0x01b0 +#define GT_Protect_High_3 0x01b8 +#define GT_260_Protect_Low_4 0x01c0 +#define GT_260_Protect_High_4 0x01c8 +#define GT_260_Protect_Low_5 0x01d0 +#define GT_260_Protect_High_5 0x01d8 +#define GT_260_Protect_Low_6 0x01e0 +#define GT_260_Protect_High_6 0x01e8 +#define GT_260_Protect_Low_7 0x01f0 +#define GT_260_Protect_High_7 0x01f8 + +/* + * Table 34: Snoop Control Register Map + */ +#define GT_260_Snoop_Base_0 0x0380 +#define GT_260_Snoop_Top_0 0x0388 +#define GT_260_Snoop_Base_1 0x0390 +#define GT_260_Snoop_Top_1 0x0398 +#define GT_260_Snoop_Base_2 0x03a0 +#define GT_260_Snoop_Top_2 0x03a8 +#define GT_260_Snoop_Base_3 0x03b0 +#define GT_260_Snoop_Top_3 0x03b8 + +/* + * Table 35: CPU Error Report Register Map + */ +#define GT_CPU_Error_Address_Low 0x0070 +#define GT_CPU_Error_Address_High 0x0078 +#define GT_CPU_Error_Data_Low 0x0128 +#define GT_CPU_Error_Data_High 0x0130 +#define GT_CPU_Error_Parity 0x0138 +#define GT_CPU_Error_Cause 0x0140 +#define GT_CPU_Error_Mask 0x0148 + +#define GT_DecodeAddr_SET(g, r, v) \ + do { \ + gt_read((g), GT_Internal_Decode); \ + gt_write((g), (r), ((v) & 0xfff00000) >> 20); \ + while ((gt_read((g), (r)) & 0xfff) != ((v) >> 20)); \ + } while (0) + +#define GT_LowAddr_GET(v) (GT__EXT((v), 0, 12) << 20) +#define GT_HighAddr_GET(v) ((GT__EXT((v), 0, 12) << 20) | 0xfffff) + +#define GT_MPP_Control0 0xf000 +#define GT_MPP_Control1 0xf004 +#define GT_MPP_Control2 0xf008 +#define GT_MPP_Control3 0xf00c + +#define GT_GPP_IO_Control 0xf100 +#define GT_GPP_Level_Control 0xf110 +#define GT_GPP_Value 0xf104 +#define GT_GPP_Interrupt_Cause 0xf108 +#define GT_GPP_Interrupt_Mask 0xf10c +/* + * Table 36: SCS[0]* Low Decode Address, Offset: 0x008 + * Table 38: SCS[1]* Low Decode Address, Offset: 0x208 + * Table 40: SCS[2]* Low Decode Address, Offset: 0x018 + * Table 42: SCS[3]* Low Decode Address, Offset: 0x218 + * Table 44: CS[0]* Low Decode Address, Offset: 0x028 + * Table 46: CS[1]* Low Decode Address, Offset: 0x228 + * Table 48: CS[2]* Low Decode Address, Offset: 0x248 + * Table 50: CS[3]* Low Decode Address, Offset: 0x038 + * Table 52: BootCS* Low Decode Address, Offset: 0x238 + * Table 75: CPU 0 Low Decode Address, Offset: 0x290 + * Table 77: CPU 1 Low Decode Address, Offset: 0x2c0 + * + * 11:00 LowAddr SCS[0] Base Address + * 31:12 Reserved Must be 0. + */ + +/* + * Table 37: SCS[0]* High Decode Address, Offset: 0x010 + * Table 39: SCS[1]* High Decode Address, Offset: 0x210 + * Table 41: SCS[2]* High Decode Address, Offset: 0x020 + * Table 43: SCS[3]* High Decode Address, Offset: 0x220 + * Table 45: CS[0]* High Decode Address, Offset: 0x030 + * Table 47: CS[1]* High Decode Address, Offset: 0x230 + * Table 49: CS[2]* High Decode Address, Offset: 0x250 + * Table 51: CS[3]* High Decode Address, Offset: 0x040 + * Table 53: BootCS* High Decode Address, Offset: 0x240 + * Table 76: CPU 0 High Decode Address, Offset: 0x298 + * Table 78: CPU 1 High Decode Address, Offset: 0x2c8 + * + * 11:00 HighAddr SCS[0] Top Address + * 31:12 Reserved + */ + +/* + * Table 54: PCI_0 I/O Low Decode Address, Offset: 0x048 + * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058 + * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080 + * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258 + * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280 + * Table 64: PCI_1 I/O Low Decode Address, Offset: 0x090 + * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0 + * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0 + * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0 + * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0 + * + * 11:00 LowAddr PCI IO/Memory Space Base Address + * 23:12 Reserved + * 26:24 PCISwap PCI Master Data Swap Control (0: Byte Swap; + * 1: No swapping; 2: Both byte and word swap; + * 3: Word swap; 4..7: Reserved) + * 27:27 PCIReq64 PCI master REQ64* policy (Relevant only when + * configured to 64-bit PCI bus and not I/O) + * 0: Assert s REQ64* only when transaction + * is longer than 64-bits. + * 1: Always assert REQ64*. + * 31:28 Reserved + */ +#define GT_PCISwap_GET(v) GT__EXT((v), 24, 3) +#define GT_PCISwap_ByteSwap 0 +#define GT_PCISwap_NoSwap 1 +#define GT_PCISwap_ByteWordSwap 2 +#define GT_PCISwap_WordSwap 3 +#define GT_PCI_LowDecode_PCIReq64 GT__BIT(27) + +/* + * Table 55: PCI_0 I/O High Decode Address, Offset: 0x050 + * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060 + * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088 + * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260 + * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288 + * Table 65: PCI_1 I/O High Decode Address, Offset: 0x098 + * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8 + * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8 + * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8 + * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8 + * + * 11:00 HighAddr PCI_0 I/O Space Top Address + * 31:12 Reserved + */ + +/* + * Table 74: Internal Space Decode, Offset: 0x068 + * 15:00 IntDecode GT64260 Internal Space Base Address + * 23:16 Reserved + * 26:24 PCISwap Same as PCI_0 Memory 0 Low Decode Address. + * NOTE: Reserved for Galileo Technology usage. + * Relevant only for PCI master configuration + * transactions on the PCI bus. + * 31:27 Reserved + */ + +/* + * Table 79: PCI_0 I/O Address Remap, Offset: 0x0f0 + * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8 + * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100 + * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8 + * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300 + * Table 88: PCI_1 I/O Address Remap, Offset: 0x108 + * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110 + * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118 + * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310 + * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318 + * + * 11:00 Remap PCI IO/Memory Space Address Remap (31:20) + * 31:12 Reserved + */ + +/* + * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320 + * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328 + * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330 + * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338 + * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340 + * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348 + * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350 + * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358 + * + * 31:00 Remap PCI Memory Address Remap (high 32 bits) + */ + +/* + * Table 97: CPU Configuration, Offset: 0x000 + * 07:00 NoMatchCnt CPU Address Miss Counter + * 08:08 NoMatchCntEn CPU Address Miss Counter Enable + * NOTE: Relevant only if multi-GT is enabled. + * (0: Disabled; 1: Enabled) + * 09:09 NoMatchCntExt CPU address miss counter MSB + * 10:10 Reserved + * 11:11 AACKDelay Address Acknowledge Delay + * 0: AACK* is asserted one cycle after TS*. + * 1: AACK* is asserted two cycles after TS*. + * 12:12 Endianess Must be 0 + * NOTE: The GT64260 does not support the PowerPC + * Little Endian convention + * 13:13 Pipeline Pipeline Enable + * 0: Disabled. The GT64260 will not respond with + * AACK* to a new CPU transaction, before the + * previous transaction data phase completes. + * 1: Enabled. + * 14:14 Reserved + * 15:15 TADelay Transfer Acknowledge Delay + * 0: TA* is asserted one cycle after AACK* + * 1: TA* is asserted two cycles after AACK* + * 16:16 RdOOO Read Out of Order Completion + * 0: Not Supported, Data is always returned in + * order (DTI[0-2] is always driven + * 1: Supported + * 17:17 StopRetry Relevant only if PCI Retry is enabled + * 0: Keep Retry all PCI transactions targeted + * to the GT64260. + * 1: Stop Retry of PCI transactions. + * 18:18 MultiGTDec Multi-GT Address Decode + * 0: Normal address decoding + * 1: Multi-GT address decoding + * 19:19 DPValid CPU DP[0-7] Connection. CPU write parity ... + * 0: is not checked. (Not connected) + * 1: is checked (Connected) + * 21:20 Reserved + * 22:22 PErrProp Parity Error Propagation + * 0: GT64260 always drives good parity on + * DP[0-7] during CPU reads. + * 1: GT64260 drives bad parity on DP[0-7] in case + * the read response from the target interface + * comes with erroneous data indication + * (e.g. ECC error from SDRAM interface). + * 25:23 Reserved + * 26:26 APValid CPU AP[0-3] Connection. CPU address parity ... + * 0: is not checked. (Not connected) + * 1: is checked (Connected) + * 27:27 RemapWrDis Address Remap Registers Write Control + * 0: Write to Low Address decode register. + * Results in writing of the corresponding + * Remap register. + * 1: Write to Low Address decode register. No + * affect on the corresponding Remap register. + * 28:28 ConfSBDis Configuration Read Sync Barrier Disable + * 0: enabled; 1: disabled + * 29:29 IOSBDis I/O Read Sync Barrier Disable + * 0: enabled; 1: disabled + * 30:30 ClkSync Clocks Synchronization + * 0: The CPU interface is running with SysClk, + * which is asynchronous to TClk. + * 1: The CPU interface is running with TClk. + * 31:31 Reserved + */ +#define GT_CPUCfg_NoMatchCnt_GET(v) GT__EXT((v), 0, 8) +#define GT_CPUCfg_NoMatchCntEn GT__BIT( 9) +#define GT_CPUCfg_NoMatchCntExt GT__BIT(10) +#define GT_CPUCfg_AACKDelay GT__BIT(11) +#define GT_CPUCfg_Endianess GT__BIT(12) +#define GT_CPUCfg_Pipeline GT__BIT(13) +#define GT_CPUCfg_TADelay GT__BIT(15) +#define GT_CPUCfg_RdOOO GT__BIT(16) +#define GT_CPUCfg_StopRetry GT__BIT(17) +#define GT_CPUCfg_MultiGTDec GT__BIT(18) +#define GT_CPUCfg_DPValid GT__BIT(19) +#define GT_CPUCfg_PErrProp GT__BIT(22) +#define GT_CPUCfg_APValid GT__BIT(26) +#define GT_CPUCfg_RemapWrDis GT__BIT(27) +#define GT_CPUCfg_ConfSBDis GT__BIT(28) +#define GT_CPUCfg_IOSBDis GT__BIT(29) +#define GT_CPUCfg_ClkSync GT__BIT(30) + +/* + * Table 98: CPU Mode, Offset: 0x120, Read only + * 01:00 MultiGTID Multi-GT ID + * Represents the ID to which the GT64260 responds + * to during a multi-GT address decoding period. + * 02:02 MultiGT (0: Single; 1: Multiple) GT configuration + * 03:03 RetryEn (0: Don't; 1: Do) Retry PCI transactions + * 07:04 CPUType + * 0x0-0x3: Reserved + * 0x4: 64-bit PowerPC CPU, 60x bus + * 0x5: 64-bit PowerPC CPU, MPX bus + * 0x6-0xf: Reserved + * 31:08 Reserved + */ +#define GT_CPUMode_MultiGTID_GET(v) GT__EXT(v, 0, 2) +#define GT_CPUMode_MultiGT GT__BIT(2) +#define GT_CPUMode_RetryEn GT__BIT(3) +#define GT_CPUMode_CPUType_GET(v) GT__EXT(v, 4, 4) + +/* + * Table 99: CPU Master Control, Offset: 0x160 + * 07:00 Reserved + * 08:08 IntArb CPU Bus Internal Arbiter Enable + * NOTE: Only relevant to 60x bus mode. When + * running MPX bus, the GT64260 internal + * arbiter must be used. + * 0: Disabled. External arbiter is required. + * 1: Enabled. Use the GT64260 CPU bus arbiter. + * 09:09 IntBusCtl CPU Interface Unit Internal Bus Control + * NOTE: This bit must be set to 1. It is reserved + * for Galileo Technology usage. + * 0: Enable internal bus sharing between master + * and slave interfaces. + * 1: Disable internal bus sharing between master + * and slave interfaces. + * 10:10 MWrTrig Master Write Transaction Trigger + * 0: With first valid write data + * 1: With last valid write data + * 11:11 MRdTrig Master Read Response Trigger + * 0: With first valid read data + * 1: With last valid read data + * 12:12 CleanBlock Clean Block Snoop Transaction Support + * 0: CPU does not support clean block (603e,750) + * 1: CPU supports clean block (604e,G4) + * 13:13 FlushBlock Flush Block Snoop Transaction Support + * 0: CPU does not support flush block (603e,750) + * 1: CPU supports flush block (604e,G4) + * 31:14 Reserved + */ +#define GT_CPUMstrCtl_IntArb GT__BIT(8) +#define GT_CPUMstrCtl_IntBusCtl GT__BIT(9) +#define GT_CPUMstrCtl_MWrTrig GT__BIT(10) +#define GT_CPUMstrCtl_MRdTrig GT__BIT(11) +#define GT_CPUMstrCtl_CleanBlock GT__BIT(12) +#define GT_CPUMstrCtl_FlushBlock GT__BIT(13) + +#define GT_ArbSlice_SDRAM 0x0 /* SDRAM interface snoop request */ +#define GT_ArbSlice_DEVICE 0x1 /* Device request */ +#define GT_ArbSlice_NULL 0x2 /* NULL request */ +#define GT_ArbSlice_PCI0 0x3 /* PCI_0 access */ +#define GT_ArbSlice_PCI1 0x4 /* PCI_1 access */ +#define GT_ArbSlice_COMM 0x5 /* Comm unit access */ +#define GT_ArbSlice_IDMA0123 0x6 /* IDMA channels 0/1/2/3 access */ +#define GT_ArbSlice_IDMA4567 0x7 /* IDMA channels 4/5/6/7 access */ + /* 0x8-0xf: Reserved */ + +/* Pass in the slice number (from 0..16) as 'n' + */ +#define GT_XbarCtl_GET_ArbSlice(v, n) GT__EXT((v), (((n) & 7)*4, 4) + +/* + * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150 + * 03:00 Arb0 Slice 0 of CPU Master pizza Arbiter + * 07:04 Arb1 Slice 1 of CPU Master pizza Arbiter + * 11:08 Arb2 Slice 2 of CPU Master pizza Arbiter + * 15:12 Arb3 Slice 3 of CPU Master pizza Arbiter + * 19:16 Arb4 Slice 4 of CPU Master pizza Arbiter + * 23:20 Arb5 Slice 5 of CPU Master pizza Arbiter + * 27:24 Arb6 Slice 6 of CPU Master pizza Arbiter + * 31:28 Arb7 Slice 7 of CPU Master pizza Arbiter + */ + +/* + * Table 101: CPU Interface Crossbar Control High, Offset: 0x158 + * 03:00 Arb8 Slice 8 of CPU Master pizza Arbiter + * 07:04 Arb9 Slice 9 of CPU Master pizza Arbiter + * 11:08 Arb10 Slice 10 of CPU Master pizza Arbiter + * 15:12 Arb11 Slice 11 of CPU Master pizza Arbiter + * 19:16 Arb12 Slice 12 of CPU Master pizza Arbiter + * 23:20 Arb13 Slice 13 of CPU Master pizza Arbiter + * 27:24 Arb14 Slice 14 of CPU Master pizza Arbiter + * 31:28 Arb15 Slice 15 of CPU Master pizza Arbiter + */ + +/* + * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168 + * NOTE: Reserved for Galileo Technology usage. + * 07:00 Timeout Crossbar Arbiter Timeout Preset Value + * 15:08 Reserved + * 16:16 TimeoutEn Crossbar Arbiter Timer Enable + * (0: Enable; 1: Disable) + * 31:17 Reserved + */ + +/* + * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170 + * 03:00 Arb0 Slice 0 of CPU Slave pizza Arbiter + * 07:04 Arb1 Slice 1 of CPU Slave pizza Arbiter + * 11:08 Arb2 Slice 2 of CPU Slave pizza Arbiter + * 15:12 Arb3 Slice 3 of CPU Slave pizza Arbiter + * 19:16 Arb4 Slice 4 of CPU Slave pizza Arbiter + * 23:20 Arb5 Slice 5 of CPU Slave pizza Arbiter + * 27:24 Arb6 Slice 6 of CPU Slave pizza Arbiter + * 31:28 Arb7 Slice 7 of CPU Slave pizza Arbiter + */ +/* + * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178 + * 03:00 Arb8 Slice 8 of CPU Slave pizza Arbiter + * 07:04 Arb9 Slice 9 of CPU Slave pizza Arbiter + * 11:08 Arb10 Slice 10 of CPU Slave pizza Arbiter + * 15:12 Arb11 Slice 11 of CPU Slave pizza Arbiter + * 19:16 Arb12 Slice 12 of CPU Slave pizza Arbiter + * 23:20 Arb13 Slice 13 of CPU Slave pizza Arbiter + * 27:24 Arb14 Slice 14 of CPU Slave pizza Arbiter + * 31:28 Arb15 Slice 15 of CPU Slave pizza Arbiter + */ + +/* + * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0 + * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8 + * NOTE: The read data is random and should be ignored. + * 31:00 SyncBarrier A CPU read from this register creates a + * synchronization barrier cycle. + */ + +/* + * Table 107: CPU Protect Address 0 Low, Offset: 0x180 + * Table 109: CPU Protect Address 1 Low, Offset: 0x190 + * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0 + * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0 + * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0 + * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0 + * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0 + * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0 + * + * 11:00 LowAddr CPU Protect Region Base Address + * Corresponds to address bits[31:20]. + * 15:12 Reserved. Must be 0 + * 16:16 AccProtect CPU Access Protect + * Access is (0: allowed; 1: forbidden) + * 17:17 WrProtect CPU Write Protect + * Writes are (0: allowed; 1: forbidden) + * 18:18 CacheProtect CPU caching protect. Caching (block read) + * is (0: allowed; 1: forbidden) + * 31:19 Reserved + */ +#define GT_CPU_AccProtect GT__BIT(16) +#define GT_CPU_WrProtect GT__BIT(17) +#define GT_CPU_CacheProtect GT__BIT(18) + +/* + * Table 108: CPU Protect Address 0 High, Offset: 0x188 + * Table 110: CPU Protect Address 1 High, Offset: 0x198 + * Table 112: CPU Protect Address 2 High, Offset: 0x1a8 + * Table 114: CPU Protect Address 3 High, Offset: 0x1b8 + * Table 116: CPU Protect Address 4 High, Offset: 0x1c8 + * Table 118: CPU Protect Address 5 High, Offset: 0x1d8 + * Table 120: CPU Protect Address 6 High, Offset: 0x1e8 + * Table 122: CPU Protect Address 7 High, Offset: 0x1f8 + * + * 11:00 HighAddr CPU Protect Region Top Address + * Corresponds to address bits[31:20] + * 31:12 Reserved + */ + +/* + * Table 123: Snoop Base Address 0, Offset: 0x380 + * Table 125: Snoop Base Address 1, Offset: 0x390 + * Table 127: Snoop Base Address 2, Offset: 0x3a0 + * Table 129: Snoop Base Address 3, Offset: 0x3b0 + * + * 11:00 LowAddr Snoop Region Base Address [31:20] + * 15:12 Reserved Must be 0. + * 17:16 Snoop Snoop Type + * 0x0: No Snoop + * 0x1: Snoop to WT region + * 0x2: Snoop to WB region + * 0x3: Reserved + * 31:18 Reserved + */ +#define GT_Snoop_GET(v) GT__EXT((v), 16, 2) +#define GT_Snoop_INS(v) GT__INS((v), 16) +#define GT_Snoop_None 0 +#define GT_Snoop_WT 1 +#define GT_Snoop_WB 2 + + +/* + * Table 124: Snoop Top Address 0, Offset: 0x388 + * Table 126: Snoop Top Address 1, Offset: 0x398 + * Table 128: Snoop Top Address 2, Offset: 0x3a8 + * Table 130: Snoop Top Address 3, Offset: 0x3b8 + * 11:00 HighAddr Snoop Region Top Address [31:20] + * 31:12 Reserved + */ + + +/* + * Table 131: CPU Error Address Low, Offset: 0x070, Read Only. + * In case of multiple errors, only the first one is latched. New error + * report latching is enabled only after the CPU Error Address Low register + * is being read. + * 31:00 ErrAddr Latched address bits [31:0] of a CPU + * transaction in case of: + * o illegal address (failed address decoding) + * o access protection violation + * o bad data parity + * o bad address parity + * Upon address latch, no new address are + * registered (due to additional error condition), + * until the register is being read. + */ + +/* + * Table 132: CPU Error Address High, Offset: 0x078, Read Only. + * Once data is latched, no new data can be registered (due to additional + * error condition), until CPU Error Low Address is being read (which + * implies, it should be the last being read by the interrupt handler). + * 03:00 Reserved + * 07:04 ErrPar Latched address parity bits in case + * of bad CPU address parity detection. + * 31:08 Reserved + */ +#define GT_CPUErrorAddrHigh_ErrPar_GET(v) GT__EXT((v), 4, 4) + +/* + * Table 133: CPU Error Data Low, Offset: 0x128, Read only. + * 31:00 PErrData Latched data bits [31:0] in case of bad data + * parity sampled on write transactions or on + * master read transactions. + */ + +/* + * Table 134: CPU Error Data High, Offset: 0x130, Read only. + * 31:00 PErrData Latched data bits [63:32] in case of bad data + * parity sampled on write transactions or on + * master read transactions. + */ + +/* + * Table 135: CPU Error Parity, Offset: 0x138, Read only. + * 07:00 PErrPar Latched data parity bus in case of bad data + * parity sampled on write transactions or on + * master read transactions. + * 31:10 Reserved + */ +#define GT_CPUErrorParity_PErrPar_GET(v) GT__EXT((v), 0, 8) + +/* + * Table 136: CPU Error Cause, Offset: 0x140 + * Bits[7:0] are clear only. A cause bit is set upon an error condition + * occurrence. Write a 0 value to clear the bit. Writing a 1 value has + * no affect. + * 00:00 AddrOut CPU Address Out of Range + * 01:01 AddrPErr Bad Address Parity Detected + * 02:02 TTErr Transfer Type Violation. + * The CPU attempts to burst (read or write) to an + * internal register. + * 03:03 AccErr Access to a Protected Region + * 04:04 WrErr Write to a Write Protected Region + * 05:05 CacheErr Read from a Caching protected region + * 06:06 WrDataPErr Bad Write Data Parity Detected + * 07:07 RdDataPErr Bad Read Data Parity Detected + * 26:08 Reserved + * 31:27 Sel Specifies the error event currently being + * reported in Error Address, Error Data, and + * Error Parity registers. + * 0x0: AddrOut + * 0x1: AddrPErr + * 0x2: TTErr + * 0x3: AccErr + * 0x4: WrErr + * 0x5: CacheErr + * 0x6: WrDataPErr + * 0x7: RdDataPErr + * 0x8-0x1f: Reserved + */ +#define GT_CPUError_AddrOut GT__BIT(GT_CPUError_Sel_AddrOut) +#define GT_CPUError_AddrPErr GT__BIT(GT_CPUError_Sel_AddrPErr) +#define GT_CPUError_TTErr GT__BIT(GT_CPUError_Sel_TTErr) +#define GT_CPUError_AccErr GT__BIT(GT_CPUError_Sel_AccErr) +#define GT_CPUError_WrErr GT__BIT(GT_CPUError_Sel_WrPErr) +#define GT_CPUError_CacheErr GT__BIT(GT_CPUError_Sel_CachePErr) +#define GT_CPUError_WrDataPErr GT__BIT(GT_CPUError_Sel_WrDataPErr) +#define GT_CPUError_RdDataPErr GT__BIT(GT_CPUError_Sel_RdDataPErr) + +#define GT_CPUError_Sel_AddrOut 0 +#define GT_CPUError_Sel_AddrPErr 1 +#define GT_CPUError_Sel_TTErr 2 +#define GT_CPUError_Sel_AccErr 3 +#define GT_CPUError_Sel_WrErr 4 +#define GT_CPUError_Sel_CacheErr 5 +#define GT_CPUError_Sel_WrDataPErr 6 +#define GT_CPUError_Sel_RdDataPErr 7 + +#define GT_CPUError_Sel_GET(v) GT__EXT((v), 27, 5) + +/* + * Table 137: CPU Error Mask, Offset: 0x148 + * 00:00 AddrOut If set to 1, enables AddrOut interrupt. + * 01:01 AddrPErr If set to 1, enables AddrPErr interrupt. + * 02:02 TTErr If set to 1, enables TTErr interrupt. + * 03:03 AccErr If set to 1, enables AccErr interrupt. + * 04:04 WrErr If set to 1, enables WrErr interrupt. + * 05:05 CacheErr If set to 1, enables CacheErr interrupt. + * 06:06 WrDataPErr If set to 1, enables WrDataPErr interrupt. + * 07:07 RdDataPErr If set to 1, enables RdDataPErr interrupt. + * 31:08 Reserved + */ + +/* + * Comm Unit Interrupt registers + */ + +/* Comm Unit Arbiter Control */ +#define GT_CommUnitArb_Ctrl 0xf300 +/* GPP IRQs level vs. edge sensitivity */ +#define GT_CommUnitArb_Ctrl_GPP_Ints_Level_Sensitive (1<<10) + +#define GT_CommUnitIntr_Cause 0xf310 +#define GT_CommUnitIntr_Mask 0xf314 +#define GT_CommUnitIntr_ErrAddr 0xf318 + +#define GT_CommUnitIntr_E0 0x00000007 +#define GT_CommUnitIntr_E1 0x00000070 +#define GT_CommUnitIntr_E2 0x00000700 +#define GT_CommUnitIntr_S0 0x00070000 +#define GT_CommUnitIntr_S1 0x00700000 +#define GT_CommUnitIntr_Sel 0x70000000 + +/* + * SDRAM Error Report (ECC) Registers + */ +#define GT_260_ECC_Data_Lo 0x484 /* latched Error Data (low) */ +#define GT_260_ECC_Data_Hi 0x480 /* latched Error Data (high) */ +#define GT_260_ECC_Addr 0x490 /* latched Error Address */ +#define GT_260_ECC_Rec 0x488 /* latched ECC code from SDRAM */ +#define GT_260_ECC_Calc 0x48c /* latched ECC code from SDRAM */ +#define GT_260_ECC_Ctl 0x494 /* ECC Control */ +#define GT_260_ECC_Count 0x498 /* ECC 1-bit error count */ + +/* Timer/Counter Registers (t. straumann) + */ +#define GT_TIMER_0 0x0850 /* preset / running value */ +#define GT_TIMER_1 0x0854 +#define GT_TIMER_2 0x0858 +#define GT_TIMER_3 0x085c + +#define GT_TIMER_0_3_Ctl 0x0864 + +#define GT_TIMER_0_Ctl_Enb 0x00000001 /* enable timer */ +#define GT_TIMER_0_Ctl_Rld 0x00000002 /* reload after expiration */ +#define GT_TIMER_1_Ctl_Enb 0x00000100 /* enable timer */ +#define GT_TIMER_1_Ctl_Rld 0x00000200 /* reload after expiration */ +#define GT_TIMER_2_Ctl_Enb 0x00010000 /* enable timer */ +#define GT_TIMER_2_Ctl_Rld 0x00020000 /* reload after expiration */ +#define GT_TIMER_3_Ctl_Enb 0x01000000 /* enable timer */ +#define GT_TIMER_3_Ctl_Rld 0x02000000 /* reload after expiration */ + +#define GT_TIMER_0_3_Intr_Cse 0x0868 +#define GT_TIMER_0_Intr 0x00000001 +#define GT_TIMER_1_Intr 0x00000002 +#define GT_TIMER_2_Intr 0x00000004 +#define GT_TIMER_3_Intr 0x00000008 +#define GT_TIMER_Intr_Smry 0x80000000 /* Interrupt Summary */ + +#define GT_TIMER_0_3_Intr_Msk 0x086c + +/* + * Watchdog Registers + */ +#define GT_WDOG_Config 0xb410 +#define GT_WDOG_Value 0xb414 +#define GT_WDOG_Value_NMI GT__MASK(24) +#define GT_WDOG_Config_Preset GT__MASK(24) +#define GT_WDOG_Config_Ctl1a GT__BIT(24) +#define GT_WDOG_Config_Ctl1b GT__BIT(25) +#define GT_WDOG_Config_Ctl2a GT__BIT(26) +#define GT_WDOG_Config_Ctl2b GT__BIT(27) +#define GT_WDOG_Config_Enb GT__BIT(31) + +#define GT_WDOG_NMI_DFLT (GT__MASK(24) & GT_WDOG_Value_NMI) +#define GT_WDOG_Preset_DFLT (GT__MASK(22) & GT_WDOG_Config_Preset) + +/* + * Device Bus Interrupts + */ +#define GT_DEVBUS_ICAUSE 0x4d0 /* Device Interrupt Cause */ +#define GT_DEVBUS_IMASK 0x4d4 /* Device Interrupt Mask */ +#define GT_DEVBUS_ERR_ADDR 0x4d8 /* Device Error Address */ + +/* + * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK + */ +#define GT_DEVBUS_DBurstErr GT__BIT(0) +#define GT_DEVBUS_DRdyErr GT__BIT(1) +#define GT_DEVBUS_Sel GT__BIT(27) +#define GT_DEVBUS_RES ~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel) + +/* MV64360 */ +/* Enable individual CPU windows by *clearing* respective bits + * in MV_64360_BASE_ADDR_DISBL + * + * Bit ordering is: + * + * SDRAM_CS_0..3 (1<<0..3) + * DEV_CS_0..3 (1<<4..7) + * BOOT_CS_0..3 (1<<8) + * PCI_0_IO (1<<9) + * PCI_0_MEM_0..3 (1<<10..13) + * PCI_1_IO (1<<14) + * PCI_1_MEM_0..3 (1<<15..18) + * INTERNAL_SRAM (1<<19) + * MV64x60_REGS (1<<20) + */ +#define MV_64360_BASE_ADDR_DISBL (0x278) + +/* Internal SRAM */ +#define MV_64360_SRAM_BASE (0x268) +#define MV_64360_SRAM_CTRL (0x380) +/* Control register bits */ +#define MV_64360_SRAM_CacheWb GT__BIT(1) +/* default setup used by linux, motload (uses 90 instead of b0), ... + * Comments say: + * - parity enabled, + * - parity error propagation + * - arbitration not parked for CPU only + * - other bits are reserved + */ +#define MV_64360_SRAM_Ctl_Setup (0x001600b0) + +#define MV_64360_SRAM_TEST_MODE (0x3f4) +#define MV_64340_SRAM_ERR_CAUSE (0x388) +#define MV_64340_SRAM_ERR_ADDR (0x390) +#define MV_64340_SRAM_ERR_ADDR_HI (0X3f8) +#define MV_64340_SRAM_ERR_DATA_LO (0x398) +#define MV_64340_SRAM_ERR_DATA_HI (0x3a0) +#define MV_64340_SRAM_ERR_DATA_PARITY (0x3a8) + +#endif /* !_DISCOVERY_DEV_GTREG_H */ diff --git a/bsps/powerpc/beatnik/include/bsp/if_em_pub.h b/bsps/powerpc/beatnik/include/bsp/if_em_pub.h new file mode 100644 index 0000000000..eb970e465b --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/if_em_pub.h @@ -0,0 +1,22 @@ +#ifndef RTEMS_BSDNET_IF_EM_PUBLIC_SYMBOLS_H +#define RTEMS_BSDNET_IF_EM_PUBLIC_SYMBOLS_H + +#include +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +extern int rtems_em_attach(struct rtems_bsdnet_ifconfig *, int); +extern int rtems_em_pci_setup(int); +extern rtems_bsdnet_early_link_check_ops rtems_em_early_link_check_ops; + +#ifdef __cplusplus + } +#endif + +#endif + + diff --git a/bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h b/bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h new file mode 100644 index 0000000000..8ea849efb1 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h @@ -0,0 +1,30 @@ +#ifndef RTEMS_BSDNET_IF_GFE_PUBLIC_SYMBOLS_H +#define RTEMS_BSDNET_IF_GFE_PUBLIC_SYMBOLS_H + +#include +#include +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +extern int +rtems_gfe_attach(struct rtems_bsdnet_ifconfig *, int); + + +/* enet_addr must be 6 bytes long */ +int +rtems_gfe_setup(int unit, char *enet_addr, uint32_t base_addr); + +extern rtems_bsdnet_early_link_check_ops +rtems_gfe_early_link_check_ops; + +#ifdef __cplusplus + } +#endif + +#endif + + diff --git a/bsps/powerpc/beatnik/include/bsp/if_mve_pub.h b/bsps/powerpc/beatnik/include/bsp/if_mve_pub.h new file mode 100644 index 0000000000..0a84310d72 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/if_mve_pub.h @@ -0,0 +1,422 @@ +#ifndef RTEMS_BSDNET_IF_MVE_PUBLIC_SYMBOLS_H +#define RTEMS_BSDNET_IF_MVE_PUBLIC_SYMBOLS_H + +/* + * Authorship + * ---------- + * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was + * created by Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'beatnik' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ +#include +#include +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +extern int rtems_mve_attach(struct rtems_bsdnet_ifconfig *, int); +extern rtems_bsdnet_early_link_check_ops rtems_mve_early_link_check_ops; + +/* Low-level Driver API. + * This provides driver access to applications that want to use e.g., the second + * ethernet interface w/o running the BSD TCP/IP stack. + */ + +/* Opaque handle */ +struct mveth_private; + +/* Direct assignment of MVE flags to user API relies on irqs and x-irqs not overlapping */ +#define BSP_MVE_IRQ_RX (1<<2) +#define BSP_MVE_IRQ_TX (1<<0) +#define BSP_MVE_IRQ_LINK (1<<16) + +/* Setup an interface. + * Allocates resources for descriptor rings and sets up the driver software structure. + * + * Arguments: + * unit: + * interface # (1..2). The interface must not be attached to BSD. + * + * driver_tid: + * ISR posts RTEMS event # ('unit' - 1) to task with ID 'driver_tid' and disables interrupts + * from this interface. + * + * void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred): + * Pointer to user-supplied callback to release a buffer that had been sent + * by BSP_mve_send_buf() earlier. The callback is passed 'cleanup_txbuf_arg' + * and a flag indicating whether the send had been successful. + * The driver no longer accesses 'user_buf' after invoking this callback. + * CONTEXT: This callback is executed either by BSP_mve_swipe_tx() or + * BSP_mve_send_buf(), BSP_mve_init_hw(), BSP_mve_stop_hw() (the latter + * ones calling BSP_mve_swipe_tx()). + * void *cleanup_txbuf_arg: + * Closure argument that is passed on to 'cleanup_txbuf()' callback; + * + * void *(*alloc_rxbuf)(int *p_size, unsigned long *p_data_addr), + * Pointer to user-supplied callback to allocate a buffer for subsequent + * insertion into the RX ring by the driver. + * RETURNS: opaque handle to the buffer (which may be a more complex object + * such as an 'mbuf'). The handle is not used by the driver directly + * but passed back to the 'consume_rxbuf()' callback. + * Size of the available data area and pointer to buffer's data area + * in '*psize' and '*p_data_area', respectively. + * If no buffer is available, this routine should return NULL in which + * case the driver drops the last packet and re-uses the last buffer + * instead of handing it out to 'consume_rxbuf()'. + * CONTEXT: Called when initializing the RX ring (BSP_mve_init_hw()) or when + * swiping it (BSP_mve_swipe_rx()). + * + * + * void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len); + * Pointer to user-supplied callback to pass a received buffer back to + * the user. The driver no longer accesses the buffer after invoking this + * callback (with 'len'>0, see below). 'user_buf' is the buffer handle + * previously generated by 'alloc_rxbuf()'. + * The callback is passed 'cleanup_rxbuf_arg' and a 'len' + * argument giving the number of bytes that were received. + * 'len' may be <=0 in which case the 'user_buf' argument is NULL. + * 'len' == 0 means that the last 'alloc_rxbuf()' had failed, + * 'len' < 0 indicates a receiver error. In both cases, the last packet + * was dropped/missed and the last buffer will be re-used by the driver. + * NOTE: the data are 'prefixed' with two bytes, i.e., the ethernet packet header + * is stored at offset 2 in the buffer's data area. Also, the FCS (4 bytes) + * is appended. 'len' accounts for both. + * CONTEXT: Called from BSP_mve_swipe_rx(). + * void *cleanup_rxbuf_arg: + * Closure argument that is passed on to 'consume_rxbuf()' callback; + * + * rx_ring_size, tx_ring_size: + * How many big to make the RX and TX descriptor rings. Note that the sizes + * may be 0 in which case a reasonable default will be used. + * If either ring size is < 0 then the RX or TX will be disabled. + * Note that it is illegal in this case to use BSP_mve_swipe_rx() or + * BSP_mve_swipe_tx(), respectively. + * + * irq_mask: + * Interrupts to enable. OR of flags from above. + * + */ +struct mveth_private * +BSP_mve_setup( + int unit, + rtems_id driver_tid, + void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred), + void *cleanup_txbuf_arg, + void *(*alloc_rxbuf)(int *p_size, uintptr_t *p_data_addr), + void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len), + void *consume_rxbuf_arg, + int rx_ring_size, + int tx_ring_size, + int irq_mask +); + +/* + * Alternate 'setup' routine allowing the user to install an ISR rather + * than a task ID. + * All parameters (other than 'isr' / 'isr_arg') and the return value + * are identical to the BSP_mve_setup() entry point. + */ +struct mveth_private * +BSP_mve_setup_1( + int unit, + void (*isr)(void *isr_arg), + void *isr_arg, + void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred), + void *cleanup_txbuf_arg, + void *(*alloc_rxbuf)(int *p_size, uintptr_t *p_data_addr), + void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len), + void *consume_rxbuf_arg, + int rx_ring_size, + int tx_ring_size, + int irq_mask +); + + +/* + * Initialize interface hardware + * + * 'mp' handle obtained by from BSP_mve_setup(). + * 'promisc' whether to set promiscuous flag. + * 'enaddr' pointer to six bytes with MAC address. Read + * from the device if NULL. + * + * Note: Multicast filters are cleared by this routine. + * However, in promiscuous mode the mcast filters + * are programmed to accept all multicast frames. + */ +void +BSP_mve_init_hw(struct mveth_private *mp, int promisc, unsigned char *enaddr); + +/* + * Clear multicast hash filter. No multicast frames are accepted + * after executing this routine (unless the hardware was initialized + * in 'promiscuous' mode). + */ +void +BSP_mve_mcast_filter_clear(struct mveth_private *mp); + +/* + * Program multicast filter to accept all multicast frames + */ +void +BSP_mve_mcast_filter_accept_all(struct mveth_private *mp); + +/* + * Add a MAC address to the multicast filter. + * Existing entries are not changed but note that + * the filter is imperfect, i.e., multiple MAC addresses + * may alias to a single filter entry. Hence software + * filtering must still be performed. + * + * If a higher-level driver implements IP multicasting + * then multiple IP addresses may alias to the same MAC + * address. This driver maintains a 'reference-count' + * which is incremented every time the same MAC-address + * is passed to this routine; the address is only removed + * from the filter if BSP_mve_mcast_filter_accept_del() + * is called the same number of times (or by BSP_mve_mcast_filter_clear). + */ +void +BSP_mve_mcast_filter_accept_add(struct mveth_private *mp, unsigned char *enaddr); + +/* + * Remove a MAC address from the multicast filter. + * This routine decrements the reference count of the given + * MAC-address and removes it from the filter once the + * count reaches zero. + */ +void +BSP_mve_mcast_filter_accept_del(struct mveth_private *mp, unsigned char *enaddr); + +/* + * Shutdown hardware and clean out the rings + */ +void +BSP_mve_stop_hw(struct mveth_private *mp); + +/* calls BSP_mve_stop_hw(), releases all resources and marks the interface + * as unused. + * RETURNS 0 on success, nonzero on failure. + * NOTE: the handle MUST NOT be used after successful execution of this + * routine. + */ +int +BSP_mve_detach(struct mveth_private *mp); + +/* + * Enqueue a mbuf chain or a raw data buffer for transmission; + * RETURN: #bytes sent or -1 if there are not enough free descriptors + * + * If 'len' is <=0 then 'm_head' is assumed to point to a mbuf chain. + * OTOH, a raw data packet (or a different type of buffer) + * may be send (non-BSD driver) by pointing data_p to the start of + * the data and passing 'len' > 0. + * 'm_head' is passed back to the 'cleanup_txbuf()' callback. + * + * Comments: software cache-flushing incurs a penalty if the + * packet cannot be queued since it is flushed anyways. + * The algorithm is slightly more efficient in the normal + * case, though. + * + * RETURNS: # bytes enqueued to device for transmission or -1 if no + * space in the TX ring was available. + */ +int +BSP_mve_send_buf(struct mveth_private *mp, void *m_head, void *data_p, int len); + +/* Descriptor scavenger; cleanup the TX ring, passing all buffers + * that have been sent to the cleanup_tx() callback. + * This routine is called from BSP_mve_send_buf(), BSP_mve_init_hw(), + * BSP_mve_stop_hw(). + * + * RETURNS: number of buffers processed. + */ +int +BSP_mve_swipe_tx(struct mveth_private *mp); + +/* Retrieve all received buffers from the RX ring, replacing them + * by fresh ones (obtained from the alloc_rxbuf() callback). The + * received buffers are passed to consume_rxbuf(). + * + * RETURNS: number of buffers processed. + */ +int +BSP_mve_swipe_rx(struct mveth_private *mp); + +/* read ethernet address from hw to buffer */ +void +BSP_mve_read_eaddr(struct mveth_private *mp, unsigned char *eaddr); + +/* read/write media word. + * 'cmd': can be SIOCGIFMEDIA, SIOCSIFMEDIA, 0 or 1. The latter + * are aliased to the former for convenience. + * 'parg': pointer to media word. + * + * RETURNS: 0 on success, nonzero on error + * + * NOTE: This routine is thread-safe. + */ +int +BSP_mve_media_ioctl(struct mveth_private *mp, int cmd, int *parg); + +/* Interrupt related routines */ + +/* Note: the BSP_mve_enable/disable/ack_irqs() entry points + * are deprecated. + * The newer API where the user passes a mask allows + * for more selective control. + */ + +/* Enable all supported interrupts at device */ +void +BSP_mve_enable_irqs(struct mveth_private *mp); + +/* Disable all supported interrupts at device */ +void +BSP_mve_disable_irqs(struct mveth_private *mp); + +/* Acknowledge (and clear) all supported interrupts. + * RETURNS: interrupts that were raised. + */ +uint32_t +BSP_mve_ack_irqs(struct mveth_private *mp); + +/* Enable interrupts included in 'mask' (leaving + * already enabled interrupts on). If the mask + * includes bits that were not passed to the 'setup' + * routine then the behavior is undefined. + */ +void +BSP_mve_enable_irq_mask(struct mveth_private *mp, uint32_t irq_mask); + +/* Disable interrupts included in 'mask' (leaving + * other ones that are currently enabled on). If the + * mask includes bits that were not passed to the 'setup' + * routine then the behavior is undefined. + * + * RETURNS: Bitmask of interrupts that were enabled upon entry + * into this routine. This can be used to restore the + * previous state. + */ +uint32_t +BSP_mve_disable_irq_mask(struct mveth_private *mp, uint32_t irq_mask); + +/* Acknowledge and clear selected interrupts. + * + * RETURNS: All pending interrupts. + * + * NOTE: Only pending interrupts contained in 'mask' + * are cleared. Others are left pending. + * + * This routine can be used to check for pending + * interrupts (pass mask == 0) or to clear all + * interrupts (pass mask == -1). + */ +uint32_t +BSP_mve_ack_irq_mask(struct mveth_private *mp, uint32_t mask); + +/* If the PHY link status changes then some + * internal settings in the ethernet controller's + * serial port need to be updated to match the + * PHY settings. Use this routine to perform the + * necessary steps after a link change has been + * detected. + * + * RETURNS: 0 on success, -1 if the PHY state + * could not be determined. + * + * The current state of the media as read + * by BSP_mve_media_ioctl() is returned in + * *pmedia. + * + * NOTE: This routine calls BSP_mve_media_ioctl(). + */ +int +BSP_mve_ack_link_chg(struct mveth_private *mp, int *pmedia); + +/* Retrieve the driver daemon TID that was passed to + * BSP_mve_setup(). + */ + +rtems_id +BSP_mve_get_tid(struct mveth_private *mp); + +/* Dump statistics to file (stdout if NULL) + * + * NOTE: this routine is not thread safe + */ +void +BSP_mve_dump_stats(struct mveth_private *mp, FILE *f); + +/* + * + * Example driver task loop (note: no synchronization of + * buffer access shown!). + * RTEMS_EVENTx = 0,1 or 2 depending on IF unit. + * + * / * setup (obtain handle) and initialize hw here * / + * + * do { + * / * ISR disables IRQs and posts event * / + * rtems_event_receive( RTEMS_EVENTx, RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &evs ); + * irqs = BSP_mve_ack_irqs(handle); + * if ( irqs & BSP_MVE_IRQ_TX ) { + * BSP_mve_swipe_tx(handle); / * cleanup_txbuf() callback executed * / + * } + * if ( irqs & BSP_MVE_IRQ_RX ) { + * BSP_mve_swipe_rx(handle); / * alloc_rxbuf() and consume_rxbuf() executed * / + * } + * if ( irqs & BSP_MVE_IRQ_LINK ) { + * / * update serial port settings from current link status * / + * BSP_mve_ack_link_chg(handle, 0); + * } + * BSP_mve_enable_irqs(handle); + * } while (1); + * + */ + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/irq.h b/bsps/powerpc/beatnik/include/bsp/irq.h new file mode 100644 index 0000000000..e5f9558ecf --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/irq.h @@ -0,0 +1,133 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified by T. Straumann for the beatnik BSP, 2005-2007 + * Some information may be based on mvme5500/irq/irq.h by K. Feng. + */ + +#ifndef LIBBSP_POWERPC_MOT_PPC_NEW_IRQ_IRQ_H +#define LIBBSP_POWERPC_MOT_PPC_NEW_IRQ_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 +#include +#include + +/* This BSP also passes a pointer to the interrupt frame to the handler. + * The PPC ABI guarantees that this will not mess up handlers written + * without knowledge of this feature. + */ + +typedef void (*BSP_rtems_irq_hdl)(rtems_irq_hdl_param,BSP_Exception_frame*); + + +/* legal priorities are 0 <= priority <= MAX_PRIO; 0 effectively disables the interrupt */ +#define BSP_IRQ_MAX_PRIO 4 +#define BSP_IRQ_MIN_PRIO 1 + +/* Note that priorites are only honoured for 'PCI' interrupt numbers. + * The discovery pic has no support for hardware priorites; hence they + * are handled in software + */ +#define BSP_IRQ_DEFAULT_PRIORITY 2 + + +#define BSP_PCI_IRQ_LOWEST_OFFSET 0 /* IMPLEMENTATION RELIES ON discovery pic INTERRUPTS HAVING NUMBERS 0..95 */ +#define BSP_IRQ_DEV 1 /* device interface interrupt */ +#define BSP_IRQ_DMA 2 /* DMA addres error interrupt (260) */ +#define BSP_IRQ_CPU 3 /* CPU interface interrupt */ +#define BSP_IRQ_IDMA0_1 4 /* IDMA ch. 0..1 complete interrupt (260) */ +#define BSP_IRQ_IDMA2_3 5 /* IDMA ch. 2..3 complete interrupt (260) */ +#define BSP_IRQ_IDMA4_5 6 /* IDMA ch. 4..5 complete interrupt (260) */ +#define BSP_IRQ_IDMA6_7 7 /* IDMA ch. 6..7 complete interrupt (260) */ +#define BSP_IRQ_TIME0_1 8 /* Timer 0..1 interrupt; Timer 0 on 64360 */ +#define BSP_IRQ_TIME2_3 9 /* Timer 2..3 interrupt; Timer 1 on 64360 */ +#define BSP_IRQ_TIME4_5 10 /* Timer 4..5 interrupt; Timer 2 on 64360 */ +#define BSP_IRQ_TIME6_7 11 /* Timer 6..7 interrupt; Timer 3 on 64360 */ +#define BSP_IRQ_PCI0_0 12 /* PCI 0 interrupt 0 summary (PCI 0 interrupt summary on 64360) */ +#define BSP_IRQ_PCI0_1 13 /* PCI 0 interrupt 1 summary (SRAM PAR ERROR on 64360) */ +#define BSP_IRQ_PCI0_2 14 /* PCI 0 interrupt 2 summary */ +#define BSP_IRQ_PCI0_3 15 /* PCI 0 interrupt 3 summary */ +#define BSP_IRQ_PCI1_0 16 /* PCI 1 interrupt 0 summary (PCI 1 interrupt summary on 64360) */ +#define BSP_IRQ_ECC 17 /* ECC error interrupt */ +#define BSP_IRQ_PCI1_1 18 /* PCI 1 interrupt 1 summary */ +#define BSP_IRQ_PCI1_2 19 /* PCI 1 interrupt 2 summary */ +#define BSP_IRQ_PCI1_3 20 /* PCI 1 interrupt 3 summary */ +#define BSP_IRQ_PCI0OUT_LO 21 /* PCI 0 outbound interrupt summary */ +#define BSP_IRQ_PCI0OUT_HI 22 /* PCI 0 outbound interrupt summary */ +#define BSP_IRQ_PCI1OUT_LO 23 /* PCI 1 outbound interrupt summary */ +#define BSP_IRQ_PCI1OUT_HI 24 /* PCI 1 outbound interrupt summary */ +#define BSP_IRQ_PCI0IN_LO 26 /* PCI 0 inbound interrupt summary */ +#define BSP_IRQ_PCI0IN_HI 27 /* PCI 0 inbound interrupt summary */ +#define BSP_IRQ_PCI1IN_LO 28 /* PCI 1 inbound interrupt summary */ +#define BSP_IRQ_PCI1IN_HI 29 /* PCI 1 inbound interrupt summary */ +#define BSP_IRQ_ETH0 (32+0) /* Ethernet controller 0 interrupt */ +#define BSP_IRQ_ETH1 (32+1) /* Ethernet controller 1 interrupt */ +#define BSP_IRQ_ETH2 (32+2) /* Ethernet controller 2 interrupt */ +#define BSP_IRQ_SDMA (32+4) /* SDMA interrupt */ +#define BSP_IRQ_I2C (32+5) /* I2C interrupt */ +#define BSP_IRQ_BRG (32+7) /* Baud Rate Generator interrupt */ +#define BSP_IRQ_MPSC0 (32+8) /* MPSC 0 interrupt */ +#define BSP_IRQ_MPSC1 (32+10) /* MPSC 1 interrupt */ +#define BSP_IRQ_COMM (32+11) /* Comm unit interrupt */ +#define BSP_IRQ_GPP7_0 (32+24) /* GPP[7..0] interrupt summary */ +#define BSP_IRQ_GPP15_8 (32+25) /* GPP[15..8] interrupt summary */ +#define BSP_IRQ_GPP23_16 (32+26) /* GPP[23..16] interrupt summary */ +#define BSP_IRQ_GPP31_24 (32+27) /* GPP[31..24] interrupt summary */ +#define BSP_IRQ_GPP_0 64 + +#define BSP_PCI_IRQ_NUMBER (64+32) +#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) + +#define BSP_PROCESSOR_IRQ_NUMBER 1 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET+1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) + +/* summary */ + +#define BSP_IRQ_NUMBER (BSP_PCI_IRQ_NUMBER + BSP_PROCESSOR_IRQ_NUMBER) +#define BSP_LOWEST_OFFSET 0 +#define BSP_MAX_OFFSET (BSP_LOWEST_OFFSET + BSP_IRQ_NUMBER - 1) +#define BSP_DECREMENTER BSP_PROCESSOR_IRQ_LOWEST_OFFSET + +#define BSP_UART_COM1_IRQ BSP_IRQ_GPP_0 +#define BSP_UART_COM2_IRQ BSP_IRQ_GPP_0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + + +#include + +int BSP_irq_is_enabled_at_pic(rtems_irq_number irq); + +/* set priority of an interrupt; must not be called from ISR level */ +int BSP_irq_set_priority(rtems_irq_number irq, rtems_irq_prio pri); + +/* Not for public use */ +void BSP_rtems_irq_mng_init(unsigned cpuId); + +#ifdef __cplusplus +} +#endif + + +#endif + +#endif diff --git a/bsps/powerpc/beatnik/include/tm27.h b/bsps/powerpc/beatnik/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/beatnik/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/powerpc/gen5200/headers.am b/bsps/powerpc/gen5200/headers.am new file mode 100644 index 0000000000..7a98ad9ec4 --- /dev/null +++ b/bsps/powerpc/gen5200/headers.am @@ -0,0 +1,45 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/ata.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/i2cdrv.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/mpc5200.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/mscan-base.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/mscan.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/nvram.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/slicetimer.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/u-boot-config.h + +include_bsp_bestcommdir = $(includedir)/bsp/bestcomm +include_bsp_bestcomm_HEADERS = +include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h +include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h +include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h +include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h +include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h + +include_bsp_bestcomm_includedir = $(includedir)/bsp/bestcomm/include +include_bsp_bestcomm_include_HEADERS = +include_bsp_bestcomm_include_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h + +include_bsp_bestcomm_include_mgt5200dir = $(includedir)/bsp/bestcomm/include/mgt5200 +include_bsp_bestcomm_include_mgt5200_HEADERS = +include_bsp_bestcomm_include_mgt5200_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h +include_bsp_bestcomm_include_mgt5200_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h + +include_bsp_bestcomm_task_apidir = $(includedir)/bsp/bestcomm/task_api +include_bsp_bestcomm_task_api_HEADERS = +include_bsp_bestcomm_task_api_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h +include_bsp_bestcomm_task_api_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h +include_bsp_bestcomm_task_api_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h +include_bsp_bestcomm_task_api_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h diff --git a/bsps/powerpc/gen5200/include/bsp.h b/bsps/powerpc/gen5200/include/bsp.h new file mode 100644 index 0000000000..40ac1116c5 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp.h @@ -0,0 +1,266 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2005 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains board specific definitions | +\*===============================================================*/ + +#ifndef LIBBSP_POWERPC_GEN5200_BSP_H +#define LIBBSP_POWERPC_GEN5200_BSP_H + +#include + +#include + +/* + * Some symbols defined in the linker command file. + */ + +LINKER_SYMBOL(bsp_ram_start); +LINKER_SYMBOL(bsp_ram_end); +LINKER_SYMBOL(bsp_ram_size); + +LINKER_SYMBOL(bsp_rom_start); +LINKER_SYMBOL(bsp_rom_end); +LINKER_SYMBOL(bsp_rom_size); + +LINKER_SYMBOL(bsp_dpram_start); +LINKER_SYMBOL(bsp_dpram_end); +LINKER_SYMBOL(bsp_dpram_size); + +LINKER_SYMBOL(bsp_section_text_start); +LINKER_SYMBOL(bsp_section_text_end); +LINKER_SYMBOL(bsp_section_text_size); + +LINKER_SYMBOL(bsp_section_data_start); +LINKER_SYMBOL(bsp_section_data_end); +LINKER_SYMBOL(bsp_section_data_size); + +LINKER_SYMBOL(bsp_section_bss_start); +LINKER_SYMBOL(bsp_section_bss_end); +LINKER_SYMBOL(bsp_section_bss_size); + +LINKER_SYMBOL(bsp_interrupt_stack_start); +LINKER_SYMBOL(bsp_interrupt_stack_end); +LINKER_SYMBOL(bsp_interrupt_stack_size); + +LINKER_SYMBOL(bsp_work_area_start); + +LINKER_SYMBOL(MBAR); + +/* Provide legacy defines */ + +#ifdef MPC5200_BOARD_PM520_ZE30 +#define PM520_ZE30 +#endif + +#ifdef MPC5200_BOARD_PM520_CR825 +#define PM520_CR825 +#endif + +#ifdef MPC5200_BOARD_ICECUBE +#define icecube +#endif + +#ifdef MPC5200_BOARD_BRS5L +#define BRS5L +#endif + +/* + * distinguish board characteristics + */ +/* + * for PM520 mdule on a ZE30 carrier + */ +#if defined(MPC5200_BOARD_PM520_ZE30) +#define PM520 +#endif +/* + * for PM520 mdule on a CR825 carrier + */ +#if defined(MPC5200_BOARD_PM520_CR825) +#define PM520 +#endif + +#if !defined(HAS_UBOOT) + /* we need the low level initialization in start.S*/ + #define NEED_LOW_LEVEL_INIT +#endif + +#if defined(MPC5200_BOARD_BRS5L) +/* + * IMD Custom Board BRS5L + */ + +#define HAS_NVRAM_93CXX + +#elif defined(MPC5200_BOARD_BRS6L) + #define MPC5200_BRS6L_FPGA_BEGIN 0x800000 + #define MPC5200_BRS6L_FPGA_SIZE (64 * 1024) + #define MPC5200_BRS6L_FPGA_END \ + (MPC5200_BRS6L_FPGA_BEGIN + MPC5200_BRS6L_FPGA_SIZE) + + #define MPC5200_BRS6L_MRAM_BEGIN 0xff000000 + #define MPC5200_BRS6L_MRAM_SIZE (4 * 1024 * 1024) + #define MPC5200_BRS6L_MRAM_END \ + (MPC5200_BRS6L_MRAM_BEGIN + MPC5200_BRS6L_MRAM_SIZE) +#elif defined (PM520) + +/* Nothing special */ + +#elif defined (MPC5200_BOARD_ICECUBE) +/* + * Codename: IceCube + * Compatible Boards: + * Freescape MPC5200LITE + * Embedded Planet EP5200 + */ + +#elif defined (MPC5200_BOARD_DP2) + +/* Nothing special */ + +#else +#error "board type not defined" +#endif + +#ifndef ASM + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_mpc5200_fec_driver_attach_detach (struct rtems_bsdnet_ifconfig *config, int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mpc5200_fec_driver_attach_detach + +/* miscellaneous stuff assumed to exist */ + +/* + * We need to decide how much memory will be non-cacheable. This + * will mainly be memory that will be used in DMA (network and serial + * buffers). + */ +/* +#define NOCACHE_MEM_SIZE 512*1024 +*/ + +/* + * Device Driver Table Entries + */ + +#ifdef HAS_NVRAM_93CXX +#define NVRAM_DRIVER_TABLE_ENTRY \ + { nvram_driver_initialize, nvram_driver_open, nvram_driver_close, \ + nvram_driver_read, nvram_driver_write, NULL } +#endif + +/* + * indicate, that BSP has IDE driver + */ +#define RTEMS_BSP_HAS_IDE_DRIVER + +/* functions */ + +/* #define SHOW_MORE_INIT_SETTINGS 1 */ + +/* ata modes */ +/* #undef ATA_USE_INT */ +#define ATA_USE_INT + +/* clock settings */ +#if defined(HAS_UBOOT) +#define IPB_CLOCK (bsp_uboot_board_info.bi_ipbfreq) +#define XLB_CLOCK (bsp_uboot_board_info.bi_busfreq) +#define G2_CLOCK (bsp_uboot_board_info.bi_intfreq) +#elif defined(MPC5200_BOARD_BRS5L) || defined(MPC5200_BOARD_BRS6L) +#define IPB_CLOCK 66000000 /* 66 MHz */ +#define XLB_CLOCK 132000000 /* 132 MHz */ +#define G2_CLOCK 396000000 /* 396 MHz */ +#else +#define IPB_CLOCK 33000000 /* 33 MHz */ +#define XLB_CLOCK 66000000 /* 66 MHz */ +#define G2_CLOCK 231000000 /* 231 MHz */ +#endif + +#if defined(HAS_UBOOT) +#define GEN5200_CONSOLE_BAUD (bsp_uboot_board_info.bi_baudrate) +#else +#define GEN5200_CONSOLE_BAUD 115200 +#endif + +/* + * Convert decrement value to tenths of microsecnds (used by + * shared timer driver). + * + * + CPU has a XLB_CLOCK bus, + * + There are 4 bus cycles per click + * + We return value in 1/10 microsecond units. + * Modified following equation to integer equation to remove + * floating point math. + * (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0)) + */ + +#define BSP_Convert_decrementer( _value ) \ + (int) (((_value) * 4000) / (XLB_CLOCK/10000)) + +/* slicetimer settings */ +#define USE_SLICETIMER_0 TRUE +#define USE_SLICETIMER_1 FALSE + +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +/* BSP specific IRQ Benchmarking support */ +void BSP_IRQ_Benchmarking_Reset(void); +void BSP_IRQ_Benchmarking_Report(void); + +#if defined(HAS_UBOOT) + /* Routine to obtain U-Boot environment variables */ + const char *bsp_uboot_getenv( + const char *name + ); +#endif + +void cpu_init(void); + +int mpc5200_eth_mii_read( + int phyAddr, + void *arg, + unsigned regAddr, + uint32_t *retVal +); + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* GEN5200 */ diff --git a/bsps/powerpc/gen5200/include/bsp/ata.h b/bsps/powerpc/gen5200/include/bsp/ata.h new file mode 100644 index 0000000000..3d8ccfc49a --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/ata.h @@ -0,0 +1,338 @@ +/* + * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef GEN5200_ATA_H +#define GEN5200_ATA_H + +#include "bestcomm.h" + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define DCTRL_SRST BSP_BBIT8(5) +#define DCTRL_NIEN BSP_BBIT8(6) + +#define DAST_BSY BSP_BBIT8(0) +#define DAST_DRDY BSP_BBIT8(1) +#define DAST_DRQ BSP_BBIT8(4) +#define DAST_ERR BSP_BBIT8(7) + +#define DST_BSY BSP_BBIT16(0) +#define DST_DRDY BSP_BBIT16(1) +#define DST_DRQ BSP_BBIT16(4) +#define DST_ERR BSP_BBIT16(7) + +#define DDMA_HUT BSP_BBIT8(1) +#define DDMA_FR BSP_BBIT8(2) +#define DDMA_FE BSP_BBIT8(3) +#define DDMA_IE BSP_BBIT8(4) +#define DDMA_UDMA BSP_BBIT8(5) +#define DDMA_READ BSP_BBIT8(6) +#define DDMA_WRITE BSP_BBIT8(7) + +#define ATA_SECTOR_SHIFT 9 + +#define ATA_PER_TRANSFER_SECTOR_COUNT_MAX 256 + +typedef union { + struct { + uint8_t alternate_status; + uint8_t reserved_0[3]; + uint16_t data; + uint8_t reserved_1[2]; + uint8_t error; + uint8_t reserved_2[3]; + uint8_t sector_count; + uint8_t reserved_3[3]; + uint8_t sector; + uint8_t reserved_4[3]; + uint8_t cylinder_low; + uint8_t reserved_5[3]; + uint8_t cylinder_high; + uint8_t reserved_6[3]; + uint8_t head; + uint8_t reserved_7[3]; + uint16_t status; + uint8_t reserved_8[2]; + } read; + + struct { + uint8_t control; + uint8_t reserved_0[3]; + uint16_t data; + uint8_t reserved_1[2]; + uint8_t feature; + uint8_t reserved_2[3]; + uint8_t sector_count; + uint8_t reserved_3[3]; + uint8_t sector; + uint8_t reserved_4[3]; + uint8_t cylinder_low; + uint8_t reserved_5[3]; + uint8_t cylinder_high; + uint8_t reserved_6[3]; + uint8_t head; + uint8_t reserved_7[3]; + uint8_t command; + uint8_t dma_control; + uint8_t reserved_8[2]; + } write; +} ata_drive_registers; + +#define ATA ((volatile ata_drive_registers *) 0xf0003a5c) + +static inline bool ata_is_data_request(void) +{ + return (ATA->read.alternate_status & DAST_DRQ) != 0; +} + +static inline bool ata_is_drive_ready_for_selection(void) +{ + return (ATA->read.alternate_status & (DAST_BSY | DAST_DRQ)) == 0; +} + +static inline void ata_wait_400_nano_seconds(void) +{ + ATA->read.alternate_status; +} + +static inline void ata_wait_for_drive_ready(void) +{ + while ((ATA->read.alternate_status & (DAST_BSY | DAST_DRQ | DAST_DRDY)) != DAST_DRDY) { + /* Wait */ + } +} + +static inline void ata_wait_for_not_busy(void) +{ + ata_wait_400_nano_seconds(); + + while ((ATA->read.alternate_status & DAST_BSY) != 0) { + /* Wait */ + } +} + +static inline bool ata_wait_for_data_request(void) +{ + ata_wait_400_nano_seconds(); + + uint8_t alternate_status; + do { + alternate_status = ATA->read.alternate_status; + } while ((alternate_status & DAST_BSY) == DAST_BSY); + + return (alternate_status & (DAST_ERR | DAST_DRQ)) == DAST_DRQ; +} + +static inline bool ata_check_status(void) +{ + return (ATA->read.status & (DST_BSY | DST_ERR)) == 0; +} + +static inline void ata_clear_interrupts(void) +{ + ATA->read.status; +} + +static inline uint8_t ata_read_or_write_sectors_command(bool read) +{ + return read ? 0x20 : 0x30; +} + +static inline rtems_blkdev_bnum ata_max_transfer_count(rtems_blkdev_bnum sector_count) +{ + return sector_count > ATA_PER_TRANSFER_SECTOR_COUNT_MAX ? + ATA_PER_TRANSFER_SECTOR_COUNT_MAX + : sector_count; +} + +static inline void ata_flush_sector(uint16_t *begin) +{ + /* XXX: The dcbi operation does not work properly */ + rtems_cache_flush_multiple_data_lines(begin, ATA_SECTOR_SIZE); +} + +void ata_reset_device(void); + +bool ata_set_transfer_mode(uint8_t mode); + +bool ata_execute_io_command(uint8_t command, uint32_t lba, uint32_t sector_count); + +static inline bool ata_execute_io_command_with_sg(uint8_t command, const rtems_blkdev_sg_buffer *sg) +{ + uint32_t lba = sg->block; + uint32_t sector_count = sg->length / ATA_SECTOR_SIZE; + return ata_execute_io_command(command, lba, sector_count); +} + +typedef struct { + const rtems_blkdev_sg_buffer *sg; + + size_t sg_count; + + rtems_blkdev_bnum sg_buffer_offset_mask; + + int sg_index_shift; +} ata_sg_context; + +static inline void ata_sg_reset(ata_sg_context *self, const rtems_blkdev_sg_buffer *sg, size_t sg_count) +{ + self->sg = sg; + self->sg_count = sg_count; + uint32_t sectors_per_buffer = self->sg[0].length >> ATA_SECTOR_SHIFT; + self->sg_buffer_offset_mask = sectors_per_buffer - 1; + self->sg_index_shift = __builtin_ffs((int) sectors_per_buffer) - 1; +} + +static inline void ata_sg_create_default(ata_sg_context *self) +{ + ata_sg_reset(self, NULL, 0); +} + +static inline void ata_sg_create(ata_sg_context *self, const rtems_blkdev_sg_buffer *sg, size_t sg_count) +{ + ata_sg_reset(self, sg, sg_count); +} + +static inline rtems_blkdev_bnum ata_sg_get_start_sector(const ata_sg_context *self) +{ + return self->sg[0].block; +} + +static inline rtems_blkdev_bnum ata_sg_get_sector_count(const ata_sg_context *self) +{ + return (self->sg_buffer_offset_mask + 1) * self->sg_count; +} + +static inline uint16_t *ata_sg_get_sector_data_begin(const ata_sg_context *self, rtems_blkdev_bnum relative_sector) +{ + uint16_t *begin = (uint16_t *)(self->sg[relative_sector >> self->sg_index_shift].buffer); + + return begin + ((relative_sector & self->sg_buffer_offset_mask) << (ATA_SECTOR_SHIFT - 1)); +} + +static inline uint16_t *ata_sg_get_sector_data_end(const ata_sg_context *self, uint16_t *begin) +{ + return begin + ATA_SECTOR_SIZE / 2; +} + +typedef struct { + rtems_id lock; + + bool card_present; +} ata_driver; + +void ata_driver_create(ata_driver *self, const char *device_file_path, rtems_block_device_ioctl io_control); + +void ata_driver_destroy(ata_driver *self); + +static inline void ata_driver_lock(const ata_driver *self) +{ + rtems_status_code sc = rtems_semaphore_obtain(self->lock, RTEMS_WAIT, RTEMS_NO_TIMEOUT); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline void ata_driver_unlock(const ata_driver *self) +{ + rtems_status_code sc = rtems_semaphore_release(self->lock); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline bool ata_driver_is_card_present(const ata_driver *self) +{ + return self->card_present; +} + +static inline void ata_driver_io_request( + ata_driver *self, + rtems_blkdev_request *request, + bool (*transfer)(ata_driver *, bool, rtems_blkdev_sg_buffer *, size_t) +) +{ + assert(request->req == RTEMS_BLKDEV_REQ_READ || request->req == RTEMS_BLKDEV_REQ_WRITE); + bool read = request->req != RTEMS_BLKDEV_REQ_WRITE; + rtems_blkdev_sg_buffer *sg = &request->bufs[0]; + uint32_t sg_count = request->bufnum; + ata_driver_lock(self); + bool ok = (*transfer)(self, read, sg, sg_count); + ata_driver_unlock(self); + rtems_status_code sc = ok ? RTEMS_SUCCESSFUL : RTEMS_IO_ERROR; + rtems_blkdev_request_done(request, sc); +} + +static inline int ata_driver_io_control( + rtems_disk_device *dd, + uint32_t cmd, + void *arg, + bool (*transfer)(ata_driver *, bool, rtems_blkdev_sg_buffer *, size_t) +) +{ + ata_driver *self = (ata_driver *) rtems_disk_get_driver_data(dd); + + switch (cmd) { + case RTEMS_BLKIO_REQUEST: + ata_driver_io_request(self, (rtems_blkdev_request *) arg, transfer); + return 0; + case RTEMS_BLKIO_CAPABILITIES: + *(uint32_t *) arg = RTEMS_BLKDEV_CAP_MULTISECTOR_CONT; + return 0; + default: + return rtems_blkdev_ioctl(dd, cmd, arg); + } +} + +int ata_driver_io_control_pio_polled( + rtems_disk_device *dd, + uint32_t cmd, + void *arg +); + +typedef struct { + ata_driver super; + + bestcomm_task task; + + bool read; + + ata_sg_context sg_context; + + rtems_blkdev_bnum transfer_current; + + rtems_blkdev_bnum transfer_end; +} ata_driver_dma_pio_single; + +void ata_driver_dma_pio_single_create( + ata_driver_dma_pio_single *self, + const char *device_file_path, + TaskId task_index +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* GEN5200_ATA_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm.h b/bsps/powerpc/gen5200/include/bsp/bestcomm.h new file mode 100644 index 0000000000..366465565a --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm.h @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef GEN5200_BESTCOMM_H +#define GEN5200_BESTCOMM_H + +#include "bestcomm_ops.h" + +#include + +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup BestComm BestComm Support + * + * @ingroup BestCommm + * + * @brief BestComm support. + * + * @{ + */ + +typedef struct { + uint32_t *tdt_begin; + uint32_t *tdt_last; + volatile uint32_t (*var_table)[32]; + uint32_t fdt_and_pragmas; + uint32_t reserved_0; + uint32_t reserved_1; + uint32_t *context_begin; + uint32_t reserved_2; +} bestcomm_task_entry; + +#define BESTCOMM_TASK_ENTRY_TABLE ((volatile bestcomm_task_entry *) 0xf0008000) + +#define BESTCOMM_IRQ_EVENT RTEMS_EVENT_13 + +typedef struct { + int task_index; + rtems_id event_task_id; +} bestcomm_irq; + +void bestcomm_irq_create(bestcomm_irq *self, int task_index); + +void bestcomm_irq_destroy(const bestcomm_irq *self); + +static inline void bestcomm_irq_enable(const bestcomm_irq *self) +{ + bestcomm_glue_irq_enable(self->task_index); +} + +static inline void bestcomm_irq_disable(const bestcomm_irq *self) +{ + bestcomm_glue_irq_disable(self->task_index); +} + +static inline void bestcomm_irq_clear(const bestcomm_irq *self) +{ + SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend, self->task_index); +} + +static inline int bestcomm_irq_get_task_index(const bestcomm_irq *self) +{ + return self->task_index; +} + +static inline rtems_id bestcomm_irq_get_event_task_id(const bestcomm_irq *self) +{ + return self->event_task_id; +} + +static inline void bestcomm_irq_set_event_task_id(bestcomm_irq *self, rtems_id id) +{ + self->event_task_id = id; +} + +static inline void bestcomm_irq_wakeup_event_task(const bestcomm_irq *self) +{ + rtems_status_code sc = rtems_event_send(self->event_task_id, BESTCOMM_IRQ_EVENT); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline void bestcomm_irq_wait(const bestcomm_irq *self) +{ + rtems_event_set events; + rtems_status_code sc = rtems_event_receive( + BESTCOMM_IRQ_EVENT, + RTEMS_EVENT_ALL | RTEMS_WAIT, + RTEMS_NO_TIMEOUT, + &events + ); + assert(sc == RTEMS_SUCCESSFUL); + assert(events == BESTCOMM_IRQ_EVENT); +} + +static inline bool bestcomm_irq_peek(const bestcomm_irq *self) +{ + rtems_event_set events; + rtems_status_code sc = rtems_event_receive(0, 0, 0, &events); + assert(sc == RTEMS_SUCCESSFUL); + + return (events & BESTCOMM_IRQ_EVENT) != 0; +} + +typedef struct { + volatile uint16_t *task_control_register; + + volatile uint32_t (*variable_table)[32]; + + TaskId task_index; + + bestcomm_irq irq; + + uint32_t *tdt_begin; + + size_t tdt_opcode_count; +} bestcomm_task; + +void bestcomm_task_create(bestcomm_task *self, TaskId task_index); + +void bestcomm_task_create_and_load( + bestcomm_task *self, + TaskId task_index, + const uint32_t *tdt_source_begin, + size_t tdt_size +); + +void bestcomm_task_destroy(bestcomm_task *self); + +void bestcomm_task_load(bestcomm_task *self, const uint32_t *tdt_source_begin, size_t tdt_size); + +static inline void bestcomm_task_set_priority(bestcomm_task *self, int priority) +{ + /* Allow higher priority initiator to block current initiator */ + mpc5200.sdma.ipr[self->task_index] = SDMA_IPR_PRIOR(priority); +} + +static inline void bestcomm_task_irq_enable(const bestcomm_task *self) +{ + bestcomm_irq_enable(&self->irq); +} + +static inline void bestcomm_task_irq_disable(const bestcomm_task *self) +{ + bestcomm_irq_disable(&self->irq); +} + +static inline void bestcomm_task_irq_clear(const bestcomm_task *self) +{ + bestcomm_irq_clear(&self->irq); +} + +static inline rtems_id bestcomm_task_get_event_task_id(const bestcomm_task *self) +{ + return bestcomm_irq_get_event_task_id(&self->irq); +} + +static inline void bestcomm_task_set_event_task_id(bestcomm_task *self, rtems_id id) +{ + bestcomm_irq_set_event_task_id(&self->irq, id); +} + +static inline void bestcomm_task_associate_with_current_task(bestcomm_task *self) +{ + bestcomm_task_set_event_task_id(self, rtems_task_self()); +} + +static inline void bestcomm_task_start(const bestcomm_task *self) +{ + *self->task_control_register = SDMA_TCR_EN | SDMA_TCR_HIGH_EN; +} + +static inline void bestcomm_task_start_with_autostart(const bestcomm_task *self) +{ + *self->task_control_register = (uint16_t) + (SDMA_TCR_EN | SDMA_TCR_HIGH_EN | SDMA_TCR_AUTO_START | SDMA_TCR_AS(self->task_index)); +} + +static inline void bestcomm_task_stop(const bestcomm_task *self) +{ + *self->task_control_register = 0; +} + +static inline void bestcomm_task_wakeup_event_task(const bestcomm_task *self) +{ + bestcomm_irq_wakeup_event_task(&self->irq); +} + +static inline void bestcomm_task_wait(const bestcomm_task *self) +{ + bestcomm_irq_wait(&self->irq); +} + +static inline bool bestcomm_task_peek(const bestcomm_task *self) +{ + return bestcomm_irq_peek(&self->irq); +} + +static inline bool bestcomm_task_is_running(const bestcomm_task *self) +{ + return (*self->task_control_register & SDMA_TCR_EN) != 0; +} + +static inline uint32_t bestcomm_get_task_variable(const bestcomm_task *self, size_t index) +{ + assert(index < VAR_COUNT); + return (*self->variable_table)[index]; +} + +static inline volatile uint32_t *bestcomm_task_get_address_of_variable(const bestcomm_task *self, size_t index) +{ + assert(index < VAR_COUNT); + return &(*self->variable_table)[index]; +} + +static inline void bestcomm_task_set_variable(const bestcomm_task *self, size_t index, uint32_t value) +{ + assert(index < VAR_COUNT); + (*self->variable_table)[index] = value; +} + +static inline uint32_t bestcomm_task_get_increment_and_condition(const bestcomm_task *self, size_t index) +{ + assert(index < INC_COUNT); + return (*self->variable_table)[INC(index)]; +} + +static inline void bestcomm_task_set_increment_and_condition_32( + const bestcomm_task *self, + size_t index, + uint32_t inc_and_cond +) +{ + assert(index < INC_COUNT); + (*self->variable_table)[INC(index)] = inc_and_cond; +} + +static inline void bestcomm_task_set_increment_and_condition( + const bestcomm_task *self, + size_t index, + int16_t inc, + int cond +) +{ + bestcomm_task_set_increment_and_condition_32(self, index, INC_INIT(cond, inc)); +} + +static inline void bestcomm_task_set_increment(const bestcomm_task *self, size_t index, int16_t inc) +{ + bestcomm_task_set_increment_and_condition_32(self, index, INC_INIT(0, inc)); +} + +void bestcomm_task_clear_variables(const bestcomm_task *self); + +static inline uint32_t bestcomm_task_get_opcode(const bestcomm_task *self, size_t index) +{ + assert(index < self->tdt_opcode_count); + return self->tdt_begin[index]; +} + +static inline void bestcomm_task_set_opcode(bestcomm_task *self, size_t index, uint32_t opcode) +{ + assert(index < self->tdt_opcode_count); + self->tdt_begin[index] = opcode; +} + +static inline void bestcomm_task_set_initiator(const bestcomm_task *self, int initiator) +{ + rtems_interrupt_level level; + rtems_interrupt_disable(level); + *self->task_control_register = BSP_BFLD16SET(*self->task_control_register, initiator, 3, 7); + rtems_interrupt_enable(level); +} + +static inline volatile bestcomm_task_entry *bestcomm_task_get_task_entry(const bestcomm_task *self) +{ + return &BESTCOMM_TASK_ENTRY_TABLE[self->task_index]; +} + +static inline void bestcomm_task_set_pragma(const bestcomm_task *self, int bit_pos, bool enable) +{ + volatile bestcomm_task_entry *entry = bestcomm_task_get_task_entry(self); + uint32_t mask = BSP_BIT32(bit_pos); + uint32_t bit = enable ? mask : 0; + entry->fdt_and_pragmas = (entry->fdt_and_pragmas & ~mask) | bit; +} + +static inline void bestcomm_task_enable_precise_increment(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_PRECISE_INC, enable); +} + +static inline void bestcomm_task_enable_error_reset(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_RST_ERROR_NO, !enable); +} + +static inline void bestcomm_task_enable_pack_data(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_PACK, enable); +} + +static inline void bestcomm_task_enable_integer_mode(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_INTEGER, enable); +} + +static inline void bestcomm_task_enable_speculative_read(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_SPECREAD, enable); +} + +static inline void bestcomm_task_enable_combined_write(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_CW, enable); +} + +static inline void bestcomm_task_enable_read_buffer(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_RL, enable); +} + +static inline volatile uint16_t *bestcomm_task_get_task_control_register(const bestcomm_task *self) +{ + return self->task_control_register; +} + +static inline int bestcomm_task_get_task_index(const bestcomm_task *self) +{ + return self->task_index; +} + +static inline void bestcomm_task_free_tdt(bestcomm_task *self) +{ + bestcomm_free(self->tdt_begin); + self->tdt_begin = NULL; +} + +static inline void bestcomm_task_clear_pragmas(const bestcomm_task *self) +{ + volatile bestcomm_task_entry *entry = bestcomm_task_get_task_entry(self); + entry->fdt_and_pragmas &= ~0xffU; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* GEN5200_BESTCOMM_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h new file mode 100644 index 0000000000..f1fa22d1d5 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h @@ -0,0 +1,460 @@ +#ifndef __BESTCOMM_API_H +#define __BESTCOMM_API_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +/*! + * \file bestcomm_api.h + * + * Bestcomm_api.h is the only header necessary for inclusion by user + * code. The include path the C compiler searches to find .h files + * should contain bestcomm/capi and one of bestcomm/code_dma/image_*. + * This second entry selects which set of BestComm tasks will be used. + * Of course the appropriate files in image_* must also be compiled and + * linked. + */ + +#include + +#include "include/ppctypes.h" +#include "include/mgt5200/sdma.h" +#include "task_api/tasksetup_bdtable.h" +#include "task_api/bestcomm_cntrl.h" +#include "task_api/bestcomm_api_mem.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! + * \brief TaskSetup() debugging + * + * Define this macro as follows for debugging printf()s to see + * what the API receives and sets from the TaskSetupParamSet_t + * struct. Implemented in capi/task_api/tasksetup_general.h. + * + * \verbatim + * >0 : print basic debug messages + * >=10: also print C-API interface variables + * >=20: also print task API interface variables + * else: do nothing + * \endverbatim + */ +#define DEBUG_BESTCOMM_API 0 + +/*! + * \brief Maximum number of tasks in the system. + * This number is hardware-dependent and not user configuration. + */ +#define MAX_TASKS 16 + +/* + * This may need to be removed in certain implementations. + */ +#ifndef NULL +# define NULL ((void *)0) +#endif /* NULL */ + +typedef sint8 TaskId; +typedef sint32 BDIdx; + +/* + * Special "task IDs" for interrupt handling API functions + */ +/*! \brief Debug interrupt "task ID" */ +#define DEBUG_INTR_ID SDMA_INT_BIT_DBG + +/*! \brief TEA interrupt "task ID" */ +#define TEA_INTR_ID SDMA_INT_BIT_TEA + +/*! \brief Task start autostart enable */ +#define TASK_AUTOSTART_ENABLE 1 + +/*! \brief Task start autostart disable */ +#define TASK_AUTOSTART_DISABLE 0 + +/*! \brief Task start interrupt enable */ +#define TASK_INTERRUPT_ENABLE 1 + +/*! \brief Task start interrupt disable */ +#define TASK_INTERRUPT_DISABLE 0 + +/* + * Buffer descriptor flags to pass to TaskBDAssign(). + */ +/*! \brief Transmit frame done */ +#define TASK_BD_TFD (1 << SDMA_DRD_BIT_TFD) + +/*! \brief Interrupt on frame done */ +#define TASK_BD_INT (1 << SDMA_DRD_BIT_INT) + +/*! + * \brief Data transfer size + */ +typedef enum { + SZ_FLEX = 3, /*!< invalid for TaskSetupParamSet_t */ + SZ_UINT8 = 1, /*!< 1-byte */ + SZ_UINT16 = 2, /*!< 2-byte */ + SZ_UINT32 = 4 /*!< 4-byte */ +} Sz_t; + +/*! + * \brief API error codes + */ +typedef enum { + TASK_ERR_NO_ERR = -1, /*!< No error */ + TASK_ERR_NO_INTR = TASK_ERR_NO_ERR, + /*!< No interrupt */ + TASK_ERR_INVALID_ARG = -2, /*!< Invalid function argument */ + TASK_ERR_BD_RING_FULL = -3, /*!< Buffer descriptor ring full*/ + TASK_ERR_API_ALREADY_INITIALIZED + = -4, /*!< API has already been initialized */ + TASK_ERR_SIZE_TOO_LARGE = -5, /*!< Buffer descriptor cannot support size parameter */ + TASK_ERR_BD_RING_EMPTY = -6, /*!< Buffer descriptor ring is empty*/ + TASK_ERR_BD_BUSY = -7, /*!< The buffer descriptor is in use + by the BestComm */ + TASK_ERR_TASK_RUNNING = -8 /*!< The task is running. */ + +} TaskErr_t; + +/*! + * \brief BestComm initiators + * + * These are assigned by TaskSetup(). + */ +typedef enum { + + INITIATOR_ALWAYS = 0, + INITIATOR_SCTMR_0 = 1, + INITIATOR_SCTMR_1 = 2, + INITIATOR_FEC_RX = 3, + INITIATOR_FEC_TX = 4, + INITIATOR_ATA_RX = 5, + INITIATOR_ATA_TX = 6, + INITIATOR_SCPCI_RX = 7, + INITIATOR_SCPCI_TX = 8, + INITIATOR_PSC3_RX = 9, + INITIATOR_PSC3_TX = 10, + INITIATOR_PSC2_RX = 11, + INITIATOR_PSC2_TX = 12, + INITIATOR_PSC1_RX = 13, + INITIATOR_PSC1_TX = 14, + INITIATOR_SCTMR_2 = 15, + + INITIATOR_SCLPC = 16, + INITIATOR_PSC5_RX = 17, + INITIATOR_PSC5_TX = 18, + INITIATOR_PSC4_RX = 19, + INITIATOR_PSC4_TX = 20, + INITIATOR_I2C2_RX = 21, + INITIATOR_I2C2_TX = 22, + INITIATOR_I2C1_RX = 23, + INITIATOR_I2C1_TX = 24, + INITIATOR_PSC6_RX = 25, + INITIATOR_PSC6_TX = 26, + INITIATOR_IRDA_RX = 25, + INITIATOR_IRDA_TX = 26, + INITIATOR_SCTMR_3 = 27, + INITIATOR_SCTMR_4 = 28, + INITIATOR_SCTMR_5 = 29, + INITIATOR_SCTMR_6 = 30, + INITIATOR_SCTMR_7 = 31 + +} MPC5200Initiator_t; + +/*! + * \brief Parameters for TaskSetup() + * + * All parameters can be hard-coded by the task API. Hard-coded values + * will be changed in the struct passed to TaskSetup() for the user to + * examine later. + */ +typedef struct { + uint32 NumBD; /*!< Number of buffer descriptors */ + + union { + uint32 MaxBuf; /*!< Maximum buffer size */ + uint32 NumBytes; /*!< Number of bytes to transfer */ + } Size; /*!< Buffer size union for BD and non-BD tasks */ + + MPC5200Initiator_t + Initiator; /*!< BestComm initiator (ignored if hard-wired) */ + uint32 StartAddrSrc; /*!< Address of the DMA source (e.g. a FIFO) */ + sint16 IncrSrc; /*!< Amount to increment source pointer */ + Sz_t SzSrc; /*!< Size of source data access */ + uint32 StartAddrDst; /*!< Address of the DMA destination (e.g. a FIFO) */ + sint16 IncrDst; /*!< Amount to increment data pointer */ + Sz_t SzDst; /*!< Size of destination data access */ +} TaskSetupParamSet_t; + +/*! + * \brief Parameters for TaskDebug() + * + * TaskDebug() and the contents of this data structure are yet to be + * determined. + */ +typedef struct { + int dummy; /* Some compilers don't like empty struct typedefs */ +} TaskDebugParamSet_t; + +/*! + * \brief Generic buffer descriptor. + * + * It is generally used as a pointer which should be cast to one of the + * other BD types based on the number of buffers per descriptor. + */ +typedef struct { + uint32 Status; /*!< Status and length bits */ +} TaskBD_t; + +/*! + * \brief Single buffer descriptor. + */ +typedef struct { + uint32 Status; /*!< Status and length bits */ + uint32 DataPtr[1]; /*!< Pointer to data buffer */ +} TaskBD1_t; + +/*! + * \brief Dual buffer descriptor. + */ +typedef struct { + uint32 Status; /*!< Status and length bits */ + uint32 DataPtr[2]; /*!< Pointer to data buffers */ +} TaskBD2_t; + + + +/*************************** + * Start of API Prototypes + ***************************/ + +#include "bestcomm_priv.h" +#include "dma_image.capi.h" + +/*! + * \brief Initialize a single task. + * \param TaskName Type of task to initialize. E.g. PCI transmit, + * ethernet receive, general purpose dual-pointer. + * Values expected can be found in the TaskName_t + * enum defined in dma_image.capi.h. + * \param TaskSetupParams Task-specific parameters. The user must fill out + * the pertinent parts of a TaskSetupParamSet_t + * data structure. + * \returns TaskId task identification token which is a required + * parameter for most other API functions. + * + * This function returns a task identification token which is a required + * parameter for most other API functions. + * + * Certain values of the structure pointed to by TaskParams are set + * as a side-effect based on task type. These may be examined after + * a successful call to TaskSetup(). User-specified values may be + * overridden. + * + * TaskId TaskSetup( TaskName_t TaskName, + * TaskSetupParamSet_t *TaskSetupParams ); + */ +#define TaskSetupHelper(TaskName, TaskSetupParams) \ + TaskSetup_ ## TaskName (TaskName ## _api, TaskSetupParams) +#define TaskSetup(TaskName, TaskSetupParams) \ + TaskSetupHelper(TaskName, TaskSetupParams) + +const char *TaskVersion(void); + +int TasksInitAPI(uint8 *MBarRef); + +int TasksInitAPI_VM(uint8 *MBarRef, uint8 *MBarPhys); + +void TasksLoadImage(sdma_regs *sdma); +int TasksAttachImage(sdma_regs *sdma); + +int TaskStart(TaskId taskId, uint32 autoStartEnable, + TaskId autoStartTask, uint32 intrEnable); +int TaskStop(TaskId taskId); +static int TaskStatus(TaskId taskId); +BDIdx TaskBDAssign(TaskId taskId, void *buffer0, void *buffer1, + int size, uint32 bdFlags); +BDIdx TaskBDRelease(TaskId taskId); +BDIdx TaskBDReset(TaskId taskId); +static TaskBD_t *TaskGetBD(TaskId taskId, BDIdx bd); +static TaskBD_t *TaskGetBDRing(TaskId taskId); +int TaskDebug(TaskId taskId, TaskDebugParamSet_t *paramSet); +static int TaskIntClear(TaskId taskId); +static TaskId TaskIntStatus(TaskId taskId); +static int TaskIntPending(TaskId taskId); +static TaskId TaskIntSource(void); +static uint16 TaskBDInUse(TaskId taskId); + + +/*! + * \brief Get the enable/disable status of a task. + * \param taskId Task handle passed back from a successful TaskSetup() + * \returns Boolean true indicates enabled or false indicates disabled + * or invalid taskId. + */ +static inline int TaskStatus(TaskId taskId) +{ + return SDMA_TASK_STATUS(SDMA_TCR, taskId) & 0x8000; +} + +/*! + * \brief Return a pointer to a buffer descriptor at index BDIdx + * \param taskId Task handle passed back from a successful TaskSetup() + * \param bd Buffer descriptor handle returned by + * TaskBDAssign() or TaskBDRelease(). + * \returns Pointer to the requested buffer descriptor or NULL on error. + * + * The returned pointer should be cast to the appropriate buffer + * descriptor type, TaskBD1_t or TaskBD2_t. + */ +static inline TaskBD_t *TaskGetBD(TaskId taskId, BDIdx bd) +{ + void *bdTab; + + bdTab = TaskBDIdxTable[taskId].BDTablePtr; + if (TaskBDIdxTable[taskId].numPtr == 1) { + return (TaskBD_t *)&(((TaskBD1_t *)bdTab)[bd]); + } else { + return (TaskBD_t *)&(((TaskBD2_t *)bdTab)[bd]); + } +} + +/*! + * \brief Return a pointer to the first buffer descriptor in the ring. + * \param taskId Task handle passed back from a successful TaskSetup() + * \returns Pointer to the array of buffer descriptors making up the + * ring or NULL on error. + * + * A device driver author may choose to use this in lieu of + * TaskBDAssign()/TaskBDRelease() to get direct access to the + * BD ring with the warning that the underlying data structure may change. + * Use at one's own discretion. + */ +static inline TaskBD_t *TaskGetBDRing(TaskId taskId) +{ + return (TaskBD_t *) TaskBDIdxTable[taskId].BDTablePtr; +} + +/*! + * \brief Clear the interrupt for a given BestComm task. + * \param taskId Task handle passed back from a successful TaskSetup() + * \returns TASK_ERR_NO_ERR (which is not really an error) for success + */ +static inline int TaskIntClear(TaskId taskId) +{ + SDMA_CLEAR_IEVENT(SDMA_INT_PEND, taskId); + return TASK_ERR_NO_ERR; /* success */ +} + +/*! + * \brief Get the interrupt status for a given task. + * \param taskId Task handle passed back from a successful TaskSetup() + * \returns TASK_ERR_NO_INTR (which is not really an error) for no interrupt + * pending, taskId for a regular interrupt, DEBUG_INTR_ID for + * a debug interrupt and TEA_INTR_ID for a TEA interrupt. + * \b Note: TaskIntStatus() may return 0, but this means that that + * taskId 0 is interrupt pending. + */ +static inline TaskId TaskIntStatus(TaskId taskId) +{ + uint32 pending; + + pending = SDMA_INT_PENDING(SDMA_INT_PEND, SDMA_INT_MASK); + + if (SDMA_INT_TEST(pending, taskId)) { + return taskId; + } else if (SDMA_INT_TEST(pending, DEBUG_INTR_ID)) { + return DEBUG_INTR_ID; + } else if (SDMA_INT_TEST(pending, TEA_INTR_ID)) { + return TEA_INTR_ID; + } + + return TASK_ERR_NO_INTR; +} + +/*! + * \brief Get the interrupt pending status for a given task. + * \param taskId Task handle passed back from a successful TaskSetup() + * \returns 0 if task does not have a pending interrupt. 1 if the task + * has an interrupt pending. + */ +static inline int TaskIntPending(TaskId taskId) +{ + uint32 pending; + + pending = SDMA_INT_PENDING(SDMA_INT_PEND, SDMA_INT_MASK); + if (SDMA_INT_TEST(pending, taskId)) { + return 1; + } else { + return 0; + } +} + +/*! + * \brief Returns the task ID of an interrupting BestComm task. + * \returns TASK_ERR_NO_INTR (which is not really an error) for no interrupt + * pending or the taskId of the interrupting task. + * + * The user must query TaskIntStatus() to discover if this is a debug + * or TEA interrupt. This function is designed for use by an operating + * system interrupt handler. + */ +static inline TaskId TaskIntSource(void) +{ + uint32 pending; + uint32 mask = 1 << (MAX_TASKS - 1); + TaskId i; + + pending = SDMA_INT_PENDING(SDMA_INT_PEND, SDMA_INT_MASK); + + if (SDMA_INT_TEST(pending, SDMA_INT_BIT_TEA)) { + return (TaskId)SDMA_TEA_SOURCE(SDMA_INT_PEND); + } + + for (i = (MAX_TASKS - 1); i >= 0; --i, mask >>= 1) { + if (pending & mask) { + return i; + } + } + + return TASK_ERR_NO_INTR; +} + +/*! + * \brief Get a count of in-use buffer descriptors. + * \param taskId Task handle passed back from a successful TaskSetup() + * \returns Count of the current number of BDs in use by the given task. + */ +static inline uint16 TaskBDInUse(TaskId taskId) +{ + return TaskBDIdxTable[taskId].currBDInUse; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __BESTCOMM_API_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h new file mode 100644 index 0000000000..18827b77c7 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h @@ -0,0 +1,114 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2004-2005 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares glue functions to the Freescale BestComm API | +\*===============================================================*/ +#ifndef _BESTCOMM_GLUE_H +#define _BESTCOMM_GLUE_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void bestcomm_glue_irq_enable +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| enable interrupt for given task number | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int bestcomm_taskno /* task number to enable */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void bestcomm_glue_irq_disable +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| disable interrupt for given task number | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int bestcomm_taskno /* task number to disable */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void bestcomm_glue_irq_install +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| install given function as bestcomm interrupt handler | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int bestcomm_taskno, /* task number for handler */ + rtems_interrupt_handler handler, /* function to call */ + void *arg + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void bestcomm_glue_init +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| initialize the bestcomm module (if not yet done): | +| - load code | +| - initialize registers | +| - initialize bus arbiter | +| - initialize interrupt control | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + void /* none */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +void *bestcomm_malloc(size_t size); + +void bestcomm_free(void *ptr); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _BESTCOMM_GLUE_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h new file mode 100644 index 0000000000..102fc082cb --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h @@ -0,0 +1,38 @@ +#ifndef __BESTCOMM_PRIV_H +#define __BESTCOMM_PRIV_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +/* + * Global variables necessitated by the TaskSetup_*() location in + * separate files from the main code and the inline functions. These are + * private data structures that should not be manipulated by API users. + */ + +extern TaskBDIdxTable_t TaskBDIdxTable[MAX_TASKS]; +extern int TaskRunning[MAX_TASKS]; +extern sint64 MBarPhysOffsetGlobal; + +#endif /* __BESTCOMM_PRIV_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h new file mode 100644 index 0000000000..6b07cbcb2a --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h @@ -0,0 +1,84 @@ +#ifndef __DMA_IMAGE_CAPI_H +#define __DMA_IMAGE_CAPI_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + + +#include "dma_image.h" + +typedef enum { + TASK_PCI_TX, + TASK_PCI_RX, + TASK_FEC_TX, + TASK_FEC_RX, + TASK_LPC, + TASK_ATA, + TASK_CRC16_DP_0, + TASK_CRC16_DP_1, + TASK_GEN_DP_0, + TASK_GEN_DP_1, + TASK_GEN_DP_2, + TASK_GEN_DP_3, + TASK_GEN_TX_BD, + TASK_GEN_RX_BD, + TASK_GEN_DP_BD_0, + TASK_GEN_DP_BD_1 +} TaskName_t; + +TaskId TaskSetup_TASK_PCI_TX (TASK_PCI_TX_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_PCI_RX (TASK_PCI_RX_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_FEC_TX (TASK_FEC_TX_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_FEC_RX (TASK_FEC_RX_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_LPC (TASK_LPC_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_ATA (TASK_ATA_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_CRC16_DP_0(TASK_CRC16_DP_0_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_CRC16_DP_1(TASK_CRC16_DP_1_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_DP_0 (TASK_GEN_DP_0_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_DP_1 (TASK_GEN_DP_1_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_DP_2 (TASK_GEN_DP_2_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_DP_3 (TASK_GEN_DP_3_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_TX_BD (TASK_GEN_TX_BD_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_RX_BD (TASK_GEN_RX_BD_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_DP_BD_0(TASK_GEN_DP_BD_0_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_DP_BD_1(TASK_GEN_DP_BD_1_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); + +#endif /* __DMA_IMAGE_CAPI_H */ + diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h new file mode 100644 index 0000000000..1f8b86cded --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h @@ -0,0 +1,472 @@ +#ifndef __DMA_IMAGE_H +#define __DMA_IMAGE_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + + +#include "include/ppctypes.h" + +void init_dma_image_TASK_PCI_TX(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_PCI_RX(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_FEC_TX(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_FEC_RX(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_LPC(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_ATA(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_CRC16_DP_0(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_CRC16_DP_1(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_DP_0(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_DP_1(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_DP_2(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_DP_3(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_TX_BD(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_RX_BD(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_DP_BD_0(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_DP_BD_1(uint8 *vMem_taskBar, sint64 vMemOffset); + +/* MBAR_TASK_TABLE is the first address of task table */ +#ifndef MBAR_TASK_TABLE +#define MBAR_TASK_TABLE 0xf0008000UL +#endif + +/* MBAR_DMA_FREE is the first free address after task table */ +#define MBAR_DMA_FREE MBAR_TASK_TABLE + 0x00001500UL + +/* TASK_BAR is the first address of the Entry table */ +#define TASK_BAR MBAR_TASK_TABLE + 0x00000000UL +#define TASK_BAR_OFFSET 0x00000000UL + +typedef struct task_info0 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[7]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrDstFIFO; + volatile sint16 *IncrBytes; + volatile uint32 *AddrPktSizeReg; + volatile sint16 *IncrSrc; + volatile uint32 *AddrSCStatusReg; + volatile uint32 *Bytes; + volatile uint32 *IterExtra; + volatile uint32 *StartAddrSrc; +} TASK_PCI_TX_api_t; +extern TASK_PCI_TX_api_t *TASK_PCI_TX_api; + +typedef struct task_info1 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[5]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrPktSizeReg; + volatile sint16 *IncrBytes; + volatile uint32 *AddrSrcFIFO; + volatile sint16 *IncrDst; + volatile uint32 *Bytes; + volatile uint32 *IterExtra; + volatile uint32 *StartAddrDst; +} TASK_PCI_RX_api_t; +extern TASK_PCI_RX_api_t *TASK_PCI_RX_api; + +typedef struct task_info2 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[22]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrDRD; + volatile uint32 AddrDRDIdx; + volatile sint16 *IncrBytes; + volatile uint32 *AddrDstFIFO; + volatile sint16 *IncrSrc; + volatile uint32 *AddrEnable; + volatile sint16 *IncrSrcMA; + volatile uint32 *BDTableBase; + volatile uint32 *BDTableLast; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_FEC_TX_api_t; +extern TASK_FEC_TX_api_t *TASK_FEC_TX_api; + +typedef struct task_info3 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[13]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrEnable; + volatile sint16 *IncrBytes; + volatile uint32 *AddrSrcFIFO; + volatile sint16 *IncrDst; + volatile uint32 *BDTableBase; + volatile sint16 *IncrDstMA; + volatile uint32 *BDTableLast; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_FEC_RX_api_t; +extern TASK_FEC_RX_api_t *TASK_FEC_RX_api; + +typedef struct task_info4 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[4]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_LPC_api_t; +extern TASK_LPC_api_t *TASK_LPC_api; + +typedef struct task_info5 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[7]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrEnable; + volatile sint16 *IncrBytes; + volatile uint32 *BDTableBase; + volatile sint16 *IncrDst; + volatile uint32 *BDTableLast; + volatile sint16 *IncrSrc; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_ATA_api_t; +extern TASK_ATA_api_t *TASK_ATA_api; + +typedef struct task_info6 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[9]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_CRC16_DP_0_api_t; +extern TASK_CRC16_DP_0_api_t *TASK_CRC16_DP_0_api; + +typedef struct task_info7 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[9]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_CRC16_DP_1_api_t; +extern TASK_CRC16_DP_1_api_t *TASK_CRC16_DP_1_api; + +typedef struct task_info8 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[4]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_GEN_DP_0_api_t; +extern TASK_GEN_DP_0_api_t *TASK_GEN_DP_0_api; + +typedef struct task_info9 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[4]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_GEN_DP_1_api_t; +extern TASK_GEN_DP_1_api_t *TASK_GEN_DP_1_api; + +typedef struct task_info10 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[4]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_GEN_DP_2_api_t; +extern TASK_GEN_DP_2_api_t *TASK_GEN_DP_2_api; + +typedef struct task_info11 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[4]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_GEN_DP_3_api_t; +extern TASK_GEN_DP_3_api_t *TASK_GEN_DP_3_api; + +typedef struct task_info12 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[8]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrDstFIFO; + volatile sint16 *IncrBytes; + volatile uint32 *AddrEnable; + volatile sint16 *IncrSrc; + volatile uint32 *BDTableBase; + volatile sint16 *IncrSrcMA; + volatile uint32 *BDTableLast; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_GEN_TX_BD_api_t; +extern TASK_GEN_TX_BD_api_t *TASK_GEN_TX_BD_api; + +typedef struct task_info13 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[7]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrEnable; + volatile sint16 *IncrBytes; + volatile uint32 *AddrSrcFIFO; + volatile sint16 *IncrDst; + volatile uint32 *BDTableBase; + volatile uint32 *BDTableLast; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_GEN_RX_BD_api_t; +extern TASK_GEN_RX_BD_api_t *TASK_GEN_RX_BD_api; + +typedef struct task_info14 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[7]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrEnable; + volatile sint16 *IncrBytes; + volatile uint32 *BDTableBase; + volatile sint16 *IncrDst; + volatile uint32 *BDTableLast; + volatile sint16 *IncrSrc; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_GEN_DP_BD_0_api_t; +extern TASK_GEN_DP_BD_0_api_t *TASK_GEN_DP_BD_0_api; + +typedef struct task_info15 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[7]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrEnable; + volatile sint16 *IncrBytes; + volatile uint32 *BDTableBase; + volatile sint16 *IncrDst; + volatile uint32 *BDTableLast; + volatile sint16 *IncrSrc; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_GEN_DP_BD_1_api_t; +extern TASK_GEN_DP_BD_1_api_t *TASK_GEN_DP_BD_1_api; + + +#endif /* __DMA_IMAGE_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h new file mode 100644 index 0000000000..9e4b94cd10 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h @@ -0,0 +1,61 @@ +#ifndef __MGT5200_MGT5200_H +#define __MGT5200_MGT5200_H + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +#define MBAR_CS 0x0000 +#define MBAR_SDRAM 0x0100 +#define MBAR_CDM 0x0200 +#define MBAR_LPC 0x0300 +#define MBAR_SCTMR 0x0400 +#define MBAR_INT_CTRL 0x0500 +#define MBAR_GPTIMER 0x0600 +#define MBAR_SLTIMER 0x0700 +#define MBAR_RTCLOCK 0x0800 +#define MBAR_MSCAN 0x0900 +#define MBAR_GPIO_STD 0x0B00 +#define MBAR_GPIO_WKUP 0x0C00 +#define MBAR_XCPCI 0x0D00 +#define MBAR_SPI 0x0F00 +#define MBAR_USB 0x1000 +#define MBAR_SDMA 0x1200 +#define MBAR_BDLC 0x1300 +#define MBAR_IR 0x1400 +#define MBAR_XLB_ARB 0x1F00 +#define MBAR_PSC1 0x2000 +#define MBAR_PSC2 0x2200 +#define MBAR_PSC3 0x2400 +#define MBAR_PSC4 0x2600 +#define MBAR_PSC5 0x2800 +#define MBAR_PSC6 0x2C00 +#define MBAR_IRDA 0x2C00 +#define MBAR_ETHERNET 0x3000 +#define MBAR_SCPCI 0x3800 +#define MBAR_ATA 0x3A00 +#define MBAR_SCLPC 0x3C00 +#define MBAR_I2C 0x3D00 +#define MBAR_SRAM 0x8000 + +#endif /* __MGT5200_MGT5200_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h new file mode 100644 index 0000000000..52d84777ad --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h @@ -0,0 +1,153 @@ +#ifndef __MGT5200_SDMA_H +#define __MGT5200_SDMA_H + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +typedef struct sdma_register_set { + volatile uint32 taskBar; /* MBAR_SDMA + 0x00 sdTpb */ + volatile uint32 currentPointer; /* MBAR_SDMA + 0x04 sdMdeComplex */ + volatile uint32 endPointer; /* MBAR_SDMA + 0x08 sdMdeComplex */ + volatile uint32 variablePointer; /* MBAR_SDMA + 0x0c sdMdeComplex */ + + volatile uint8 IntVect1; /* MBAR_SDMA + 0x10 sdPtd */ + volatile uint8 IntVect2; /* MBAR_SDMA + 0x11 sdPtd */ + volatile uint16 PtdCntrl; /* MBAR_SDMA + 0x12 sdPtd */ + + volatile uint32 IntPend; /* MBAR_SDMA + 0x14 sdPtd */ + volatile uint32 IntMask; /* MBAR_SDMA + 0x18 sdPtd */ + + volatile uint32 TCR01; /* MBAR_SDMA + 0x1c sdPtd */ + volatile uint32 TCR23; /* MBAR_SDMA + 0x20 sdPtd */ + volatile uint32 TCR45; /* MBAR_SDMA + 0x24 sdPtd */ + volatile uint32 TCR67; /* MBAR_SDMA + 0x28 sdPtd */ + volatile uint32 TCR89; /* MBAR_SDMA + 0x2c sdPtd */ + volatile uint32 TCRAB; /* MBAR_SDMA + 0x30 sdPtd */ + volatile uint32 TCRCD; /* MBAR_SDMA + 0x34 sdPtd */ + volatile uint32 TCREF; /* MBAR_SDMA + 0x38 sdPtd */ + + volatile uint8 IPR0; /* MBAR_SDMA + 0x3c sdPtd */ + volatile uint8 IPR1; /* MBAR_SDMA + 0x3d sdPtd */ + volatile uint8 IPR2; /* MBAR_SDMA + 0x3e sdPtd */ + volatile uint8 IPR3; /* MBAR_SDMA + 0x3f sdPtd */ + volatile uint8 IPR4; /* MBAR_SDMA + 0x40 sdPtd */ + volatile uint8 IPR5; /* MBAR_SDMA + 0x41 sdPtd */ + volatile uint8 IPR6; /* MBAR_SDMA + 0x42 sdPtd */ + volatile uint8 IPR7; /* MBAR_SDMA + 0x43 sdPtd */ + volatile uint8 IPR8; /* MBAR_SDMA + 0x44 sdPtd */ + volatile uint8 IPR9; /* MBAR_SDMA + 0x45 sdPtd */ + volatile uint8 IPR10; /* MBAR_SDMA + 0x46 sdPtd */ + volatile uint8 IPR11; /* MBAR_SDMA + 0x47 sdPtd */ + volatile uint8 IPR12; /* MBAR_SDMA + 0x48 sdPtd */ + volatile uint8 IPR13; /* MBAR_SDMA + 0x49 sdPtd */ + volatile uint8 IPR14; /* MBAR_SDMA + 0x4a sdPtd */ + volatile uint8 IPR15; /* MBAR_SDMA + 0x4b sdPtd */ + volatile uint8 IPR16; /* MBAR_SDMA + 0x4c sdPtd */ + volatile uint8 IPR17; /* MBAR_SDMA + 0x4d sdPtd */ + volatile uint8 IPR18; /* MBAR_SDMA + 0x4e sdPtd */ + volatile uint8 IPR19; /* MBAR_SDMA + 0x4f sdPtd */ + volatile uint8 IPR20; /* MBAR_SDMA + 0x50 sdPtd */ + volatile uint8 IPR21; /* MBAR_SDMA + 0x51 sdPtd */ + volatile uint8 IPR22; /* MBAR_SDMA + 0x52 sdPtd */ + volatile uint8 IPR23; /* MBAR_SDMA + 0x53 sdPtd */ + volatile uint8 IPR24; /* MBAR_SDMA + 0x54 sdPtd */ + volatile uint8 IPR25; /* MBAR_SDMA + 0x55 sdPtd */ + volatile uint8 IPR26; /* MBAR_SDMA + 0x56 sdPtd */ + volatile uint8 IPR27; /* MBAR_SDMA + 0x57 sdPtd */ + volatile uint8 IPR28; /* MBAR_SDMA + 0x58 sdPtd */ + volatile uint8 IPR29; /* MBAR_SDMA + 0x59 sdPtd */ + volatile uint8 IPR30; /* MBAR_SDMA + 0x5a sdPtd */ + volatile uint8 IPR31; /* MBAR_SDMA + 0x5b sdPtd */ + + volatile uint32 cReqSelect; /* MBAR_SDMA + 0x5c sdPtd */ + volatile uint32 taskSize0; /* MBAR_SDMA + 0x60 sdPtd */ + volatile uint32 taskSize1; /* MBAR_SDMA + 0x64 sdPtd */ + volatile uint32 MDEDebug; /* MBAR_SDMA + 0x68 sdMdeComplex */ + volatile uint32 ADSDebug; /* MBAR_SDMA + 0x6c sdAdsTop */ + volatile uint32 Value1; /* MBAR_SDMA + 0x70 sdDbg */ + volatile uint32 Value2; /* MBAR_SDMA + 0x74 sdDbg */ + volatile uint32 Control; /* MBAR_SDMA + 0x78 sdDbg */ + volatile uint32 Status; /* MBAR_SDMA + 0x7c sdDbg */ + volatile uint32 PTDDebug; /* MBAR_SDMA + 0x80 sdPtd */ +} sdma_regs; + +#define SDMA_PTDCNTRL_TI 0x8000 +#define SDMA_PTDCNTRL_TEA 0x4000 +#define SDMA_PTDCNTRL_HE 0x2000 +#define SDMA_PTDCNTRL_PE 0x0001 + +#define SDMA_CREQSELECT_REQ31_MASK (~0xC0000000UL) +#define SDMA_CREQSELECT_REQ30_MASK (~0x30000000UL) +#define SDMA_CREQSELECT_REQ29_MASK (~0x0C000000UL) +#define SDMA_CREQSELECT_REQ28_MASK (~0x03000000UL) +#define SDMA_CREQSELECT_REQ27_MASK (~0x00C00000UL) +#define SDMA_CREQSELECT_REQ26_MASK (~0x00300000UL) +#define SDMA_CREQSELECT_REQ25_MASK (~0x000C0000UL) +#define SDMA_CREQSELECT_REQ24_MASK (~0x00030000UL) +#define SDMA_CREQSELECT_REQ23_MASK (~0x0000C000UL) +#define SDMA_CREQSELECT_REQ22_MASK (~0x00003000UL) +#define SDMA_CREQSELECT_REQ21_MASK (~0x00000C00UL) +#define SDMA_CREQSELECT_REQ20_MASK (~0x00000300UL) +#define SDMA_CREQSELECT_REQ19_MASK (~0x000000C0UL) +#define SDMA_CREQSELECT_REQ18_MASK (~0x00000030UL) +#define SDMA_CREQSELECT_REQ17_MASK (~0x0000000CUL) +#define SDMA_CREQSELECT_REQ16_MASK (~0x00000003UL) + +#define SDMA_CREQSELECT_REQ31_ALWAYS31 0xC0000000UL +#define SDMA_CREQSELECT_REQ30_ALWAYS30 0x30000000UL +#define SDMA_CREQSELECT_REQ29_ALWAYS29 0x0C000000UL +#define SDMA_CREQSELECT_REQ28_ALWAYS28 0x03000000UL +#define SDMA_CREQSELECT_REQ27_ALWAYS27 0x00C00000UL +#define SDMA_CREQSELECT_REQ26_ALWAYS26 0x00300000UL +#define SDMA_CREQSELECT_REQ25_ALWAYS25 0x000C0000UL +#define SDMA_CREQSELECT_REQ24_ALWAYS24 0x00030000UL +#define SDMA_CREQSELECT_REQ23_ALWAYS23 0x0000C000UL +#define SDMA_CREQSELECT_REQ22_ALWAYS22 0x00003000UL +#define SDMA_CREQSELECT_REQ21_ALWAYS21 0x00000C00UL +#define SDMA_CREQSELECT_REQ20_ALWAYS20 0x00000300UL +#define SDMA_CREQSELECT_REQ19_ALWAYS19 0x000000C0UL +#define SDMA_CREQSELECT_REQ18_ALWAYS18 0x00000030UL +#define SDMA_CREQSELECT_REQ17_ALWAYS17 0x0000000CUL +#define SDMA_CREQSELECT_REQ16_ALWAYS16 0x00000003UL + +#define SDMA_CREQSELECT_REQ31_SCTIMER7 0x00000000UL +#define SDMA_CREQSELECT_REQ30_SCTIMER6 0x00000000UL +#define SDMA_CREQSELECT_REQ29_SCTIMER5 0x00000000UL +#define SDMA_CREQSELECT_REQ28_SCTIMER4 0x00000000UL +#define SDMA_CREQSELECT_REQ27_SCTIMER3 0x00000000UL +#define SDMA_CREQSELECT_REQ26_PSC6_TX 0x00000000UL +#define SDMA_CREQSELECT_REQ25_PSC6_RX 0x00000000UL +#define SDMA_CREQSELECT_REQ24_I2C1_TX 0x00000000UL +#define SDMA_CREQSELECT_REQ23_I2C1_RX 0x00000000UL +#define SDMA_CREQSELECT_REQ22_I2C2_TX 0x00000000UL +#define SDMA_CREQSELECT_REQ21_I2C2_RX 0x00000000UL +#define SDMA_CREQSELECT_REQ20_PSC4_TX 0x00000000UL +#define SDMA_CREQSELECT_REQ19_PSC4_RX 0x00000000UL +#define SDMA_CREQSELECT_REQ18_PSC5_TX 0x00000000UL +#define SDMA_CREQSELECT_REQ17_PSC5_RX 0x00000000UL +#define SDMA_CREQSELECT_REQ16_LP 0x00000000UL + +#define SDMA_CREQSELECT_ALWAYS30 0xC0000000UL + +#endif /* __MGT5200_SDMA_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h new file mode 100644 index 0000000000..ff2aed1997 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h @@ -0,0 +1,43 @@ +#ifndef __PPCTYPES_H +#define __PPCTYPES_H + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef unsigned long long uint64; + +typedef signed char sint8; +typedef signed short sint16; +typedef signed long sint32; +typedef signed long long sint64; + +typedef volatile unsigned char reg8; +typedef volatile unsigned short reg16; +typedef volatile unsigned long reg32; +typedef volatile unsigned long long reg64; + +#endif /* __PPCTYPES_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h new file mode 100644 index 0000000000..dc529d6a22 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h @@ -0,0 +1,67 @@ +#ifndef __TASK_API_BESTCOMM_API_MEM_H +#define __TASK_API_BESTCOMM_API_MEM_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +#include "../include/mgt5200/mgt5200.h" + +/* + * An extern global variable is used here for the MBAR since it must + * be passed into the API for processes that use virtual memory. + */ +extern uint8 *MBarGlobal; + +#define SDMA_TASK_BAR (MBarGlobal+MBAR_SDMA+0x000) +#define SDMA_INT_PEND (MBarGlobal+MBAR_SDMA+0x014) +#define SDMA_INT_MASK (MBarGlobal+MBAR_SDMA+0x018) +#define SDMA_TCR (MBarGlobal+MBAR_SDMA+0x01C) +#define SDMA_TASK_SIZE (MBarGlobal+MBAR_SDMA+0x060) + +#define PCI_TX_PKT_SIZE (MBarGlobal+MBAR_SCPCI+0x000) +#define PCI_TX_NTBIT (MBarGlobal+MBAR_SCPCI+0x01C) +#define PCI_TX_FIFO (MBarGlobal+MBAR_SCPCI+0x040) +#define PCI_TX_FIFO_STAT (MBarGlobal+MBAR_SCPCI+0x045) +#define PCI_TX_FIFO_GRAN (MBarGlobal+MBAR_SCPCI+0x048) +#define PCI_TX_FIFO_ALARM (MBarGlobal+MBAR_SCPCI+0x04E) + +#define PCI_RX_PKT_SIZE (MBarGlobal+MBAR_SCPCI+0x080) +#define PCI_RX_NTBIT (MBarGlobal+MBAR_SCPCI+0x09C) +#define PCI_RX_FIFO (MBarGlobal+MBAR_SCPCI+0x0C0) +#define PCI_RX_FIFO_STAT (MBarGlobal+MBAR_SCPCI+0x0C5) +#define PCI_RX_FIFO_GRAN (MBarGlobal+MBAR_SCPCI+0x0C8) +#define PCI_RX_FIFO_ALARM (MBarGlobal+MBAR_SCPCI+0x0CE) + + +#define FEC_RX_FIFO (MBarGlobal+MBAR_ETHERNET+0x184) +#define FEC_RX_FIFO_STAT (MBarGlobal+MBAR_ETHERNET+0x188) +#define FEC_RX_FIFO_GRAN (MBarGlobal+MBAR_ETHERNET+0x18C) +#define FEC_RX_FIFO_ALARM (MBarGlobal+MBAR_ETHERNET+0x198) + +#define FEC_TX_FIFO (MBarGlobal+MBAR_ETHERNET+0x1A4) +#define FEC_TX_FIFO_STAT (MBarGlobal+MBAR_ETHERNET+0x1A8) +#define FEC_TX_FIFO_GRAN (MBarGlobal+MBAR_ETHERNET+0x1AC) +#define FEC_TX_FIFO_ALARM (MBarGlobal+MBAR_ETHERNET+0x1B8) + +#endif /* __TASK_API_BESTCOMM_API_MEM_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h new file mode 100644 index 0000000000..3712bae3d0 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h @@ -0,0 +1,282 @@ +#ifndef __TASK_API_BESTCOMM_CNTRL_H +#define __TASK_API_BESTCOMM_CNTRL_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +/******************************************************************************* + * Defines to control SmartDMA and its tasks. These defines are used for the + * task build process to minimize disconnects at the task/driver interface. + ******************************************************************************/ + +#define SDMA_INT_BIT_DBG 31 /* debug interrupt bit */ +#define SDMA_INT_BIT_TEA 28 /* TEA interrupt bit */ +#define SDMA_INT_BIT_TEA_TASK 24 /* lsb for TEA task number */ +#define SDMA_INT_BIT_IMPL 0x9000FFFF + +#define SDMA_PTDCTRL_BIT_TEA 14 /* TEA detection enable bit */ + +#define SDMA_TCR_BIT_AUTO 15 /* auto start bit */ +#define SDMA_TCR_BIT_HOLD 5 /* hold initiator bit */ + +#define SDMA_STAT_BIT_ALARM 17 +#define SDMA_FIFO_ALARM_MASK 0x0020000 + +#define SDMA_DRD_BIT_TFD 27 /* mark last buffer of frame */ +#define SDMA_DRD_BIT_INT 26 /* interrupt after buffer processed */ +#define SDMA_DRD_BIT_INIT 21 /* lsb position of initiator */ +#define SDMA_DRD_MASK_FLAGS 0x0C000000 /* BD_FLAGS flag bits */ +#define SDMA_DRD_MASK_LENGTH 0x03FFFFFF /* BD_FLAGS length mask */ +#define SDMA_BD_BIT_READY 30 /* Status BD ready bit */ +#ifdef SAS_COMPILE + #define SDMA_BD_MASK_READY constant(1<0 */ + +#define SDMA_PRAGMA_BIT_RSV 7 /* reserved pragma bit */ +#define SDMA_PRAGMA_BIT_PRECISE_INC 6 /* increment 0=when possible, 1=iter end */ +#define SDMA_PRAGMA_BIT_RST_ERROR_NO 5 /* don't reset errors on task enable */ +#define SDMA_PRAGMA_BIT_PACK 4 /* pack data enable */ +#define SDMA_PRAGMA_BIT_INTEGER 3 /* data alignment 0=frac(msb), 1=int(lsb) */ +#define SDMA_PRAGMA_BIT_SPECREAD 2 /* XLB speculative read enable */ +#define SDMA_PRAGMA_BIT_CW 1 /* write line buffer enable */ +#define SDMA_PRAGMA_BIT_RL 0 /* read line buffer enable */ + +#define SDMA_TASK_ENTRY_BYTES 32 /* Bytes per task in entry table */ +#define SDMA_TASK_GROUP_NUM 16 /* Number of tasks per task group */ +#define SDMA_TASK_GROUP_BYTES (SDMA_TASK_ENTRY_BYTES*SDMA_TASK_GROUP_NUM) + + +/******************************************************************************* + * Task group control macros, use when TaskNum > 15 + ******************************************************************************/ +#define SDMA_TASKNUM_EXT(OldTaskNum) (OldTaskNum%16) + +#define SDMA_TASKBAR_CHANGE(sdma, OldTaskNum) { \ + sdma->taskBar += (((int)(OldTaskNum/SDMA_TASK_GROUP_NUM))*SDMA_TASK_GROUP_BYTES); \ +} + +#define SDMA_TASKBAR_RESTORE(sdma, OldTaskNum) { \ + sdma->taskBar -= (((int)(OldTaskNum/SDMA_TASK_GROUP_NUM))*SDMA_TASK_GROUP_BYTES); \ +} + + +/******************************************************************************* + * Task control macros + ******************************************************************************/ +#define SDMA_TASK_CFG(RegAddr, TaskNum, AutoStart, AutoStartNum) { \ + *(((volatile uint16 *)RegAddr)+TaskNum) = (uint16)(0x0000 | \ + ((AutoStart!=0)<<7) | \ + (AutoStartNum&0xF) ); \ +} + +#define SDMA_TASK_AUTO_START(RegAddr, TaskNum, AutoStart, AutoStartNum) { \ + *(((volatile uint16 *)RegAddr)+TaskNum) = (uint16)((*(((volatile uint16 *)RegAddr)+TaskNum) & \ + (uint16) 0xff30) | ((uint16)(0x0000 | \ + ((AutoStart!=0)<<7) | \ + (AutoStartNum&0xF)) )); \ +} + +#define SDMA_TASK_ENABLE(RegAddr, TaskNum) { \ + *(((volatile uint16 *)RegAddr)+TaskNum) |= (uint16)0x8000; \ +} + +#define SDMA_TASK_DISABLE(RegAddr, TaskNum) { \ + *(((volatile uint16 *)RegAddr)+TaskNum) &= ~(uint16)0x8000; \ +} + +#define SDMA_TASK_STATUS(RegAddr, TaskNum) \ + *(((volatile uint16 *)RegAddr)+TaskNum) + + +/******************************************************************************* + * Interrupt control macros + ******************************************************************************/ +#define SDMA_INT_ENABLE(RegAddr, Bit) \ + do { \ + rtems_interrupt_level level; \ + rtems_interrupt_disable(level); \ + *((volatile uint32 *) RegAddr) &= ~((uint32) (1 << Bit)); \ + rtems_interrupt_enable(level); \ + } while (0) + +#define SDMA_INT_DISABLE(RegAddr, Bit) \ + do { \ + rtems_interrupt_level level; \ + rtems_interrupt_disable(level); \ + *((volatile uint32 *) (RegAddr)) |= ((uint32)(1 << Bit)); \ + rtems_interrupt_enable(level); \ + } while (0) + +#define SDMA_INT_SOURCE(RegPend, RegMask) \ + (*((volatile uint32 *)(RegPend)) & (~*((volatile uint32 *)(RegMask))) & (uint32)SDMA_INT_BIT_IMPL) + +#define SDMA_INT_PENDING(RegPend, RegMask) \ + (*((volatile uint32 *)(RegPend)) & (~*((volatile uint32 *)(RegMask)))) + +#define SDMA_INT_TEST(IntSource, Bit) \ + (((uint32)IntSource) & ((uint32)(1<IntPend & (uint32)(1<IntMask & (uint32)(1<PtdCntrl &= ~((uint32)(1<PtdCntrl |= ((uint32)(1<IntPend = ((uint32)(0x1F<>SDMA_INT_BIT_TEA_TASK) & 0xF) + + +/******************************************************************************* + * SmartDMA debug control macros + ******************************************************************************/ +/* Enable the SmartDMA debug unit and DBG interrupt */ +/* add sdma->dbg_regs setup? */ +#define SDMA_DBG_ENABLE(sdma) { \ + SDMA_INT_ENABLE(sdma, SDMA_INT_BIT_DBG); \ +} + +#define SDMA_DBG_DISABLE(sdma) { \ + SDMA_INT_DISABLE(sdma, SDMA_INT_BIT_DBG); \ +} + +/* Clear the debug interrupt */ +#define SDMA_DBG_CLEAR(sdma) { \ + SDMA_CLEAR_IEVENT(sdma, SDMA_INT_BIT_DBG); \ +} + +#define SDMA_DBG_MDE(dst, sdma, addr) { \ + sdma->MDEDebug = addr; \ + dst = sdma->MDEDebug; \ +} + +#define SDMA_DBG_ADS(dst, sdma, addr) { \ + sdma->ADSDebug = addr; \ + dst = sdma->ADSDebug; \ +} + +#define SDMA_DBG_PTD(dst, sdma, addr) { \ + sdma->PTDDebug = addr; \ + dst = sdma->PTDDebug; \ +} + + +/******************************************************************************* + * Initiator control macros + ******************************************************************************/ + +/* This macro may not work, getting compile errors */ +/* Set the Transfer Size */ +/* Note that masking the size w/ 0x3 gives the desired value for uint32 */ +/* (expressed as 4), namely 0. */ +#define SDMA_SET_SIZE(RegAddr, TaskNum, SrcSize, DstSize) \ + *(((volatile uint8 *)RegAddr)+((uint32)(TaskNum/2))) = \ + (uint8)((*(((volatile uint8 *)RegAddr)+((uint32)(TaskNum/2))) & \ + ((TaskNum%2) ? 0xf0 : 0x0f)) | \ + ((uint8)(((SrcSize & 0x3)<<2) | \ + ( DstSize & 0x3 ) ) <<(4*((int)(1-(TaskNum%2)))))); + +/* This macro may not work */ +/* Set the Initiator in TCR */ +#define SDMA_SET_INIT(RegAddr, TaskNum, Initiator) \ +{ \ + *(((volatile uint16 *)RegAddr)+TaskNum) &= (uint16)0xE0FF; \ + *(((volatile uint16 *)RegAddr)+TaskNum) |= (((0x01F & Initiator)<<8) | \ + (0<NumDRD; i++) { \ + if (SDMA_INIT_READ(task->DRD[i]) == (uint32)oldInitiator) { \ + SDMA_INIT_WRITE(task->DRD[i],newInitiator); \ + } \ + } \ +} + +/* Set the Initiator Priority */ +#define SDMA_SET_INITIATOR_PRIORITY(sdma, initiator, priority) \ + *(((volatile uint8 *)&sdma->IPR0)+initiator) = priority; + + +/* Read DRD initiator number */ +#define SDMA_INIT_READ(PtrDRD) \ + (((*(volatile uint32 *)PtrDRD)>>SDMA_DRD_BIT_INIT) & (uint32)0x1F) + +/* Write DRD initiator number */ +#define SDMA_INIT_WRITE(PtrDRD, Initiator) { \ + *(volatile uint32 *)PtrDRD = ((*(volatile uint32 *)PtrDRD) & 0xFC1FFFFF) | \ + (Initiator<NumDRD; i++) { \ + if (SDMA_INIT_READ(task->DRD[i]) == (uint32)oldInitiator) { \ + SDMA_INIT_WRITE(task->DRD[i],newInitiator); \ + } \ + } \ +} + +#endif /* __TASK_API_BESTCOMM_CNTRL_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h new file mode 100644 index 0000000000..7f261d21ee --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h @@ -0,0 +1,86 @@ +#ifndef __TASK_API_TASKSETUP_BDTABLE_H +#define __TASK_API_TASKSETUP_BDTABLE_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +/* + * Table of BD rings for all BestComm tasks indexed by task ID. + * + * +-----+------+--------------+ +------+-------+ + * 0: |numBD|numPtr|BDTablePtr ---|--->|status|dataPtr| + * +-----+------+--------------+ +------+-------+ + * 1: |numBD|numPtr|BDTablePtr | |status|dataPtr| + * +-----+------+--------------+ . . . + * 2: |numBD|numPtr|BDTablePtr ---|-+ . . . + * . . . | . . . + * . . . | |status|dataPtr| + * . . . | +------+-------+ + * 15:|numBD|numPtr|BDTablePtr | | + * +-----+------+--------------+ | + * | + * V + * +------+--------+--------+ + * |status|dataPtr0|dataPtr1| + * +------+--------+--------+ + * |status|dataPtr0|dataPtr1| + * . . . . + * . . . . + * . . . . + * |status|dataPtr0|dataPtr1| + * +------+--------+--------+ + */ +typedef struct { + uint16 numBD; /* Size of BD ring */ + uint8 numPtr; /* Number of data buffer pointers per BD */ + uint8 apiConfig; /* API configuration flags */ + void *BDTablePtr; /* Pointer to BD tables, must be cast to TaskBD1_t */ + /* or TaskBD2_t */ + volatile uint32 + *BDStartPtr; /* Task's current BD pointer. This pointer is + * used to set a task's BD pointer upon startup. + * It is only valid for BD tasks and only after + * TaskSetup() or TaskBDReset() are called. You + * cannot use this to track a task's BD pointer. + */ + uint16 currBDInUse; /* Current number of buffer descriptors assigned but*/ + /* not released yet. */ +} TaskBDIdxTable_t; + +typedef enum { + API_CONFIG_NONE = 0x00, + API_CONFIG_BD_FLAG = 0x01 +} ApiConfig_t; + +/* + * Allocates BD table if needed and updates the BD index table. + * Do we want to hide this from the C API since it operates on task API? + */ +void TaskSetup_BDTable(volatile uint32 *BasePtr, + volatile uint32 *LastPtr, + volatile uint32 *StartPtr, + int TaskNum, uint32 NumBD, uint16 MaxBD, + uint8 NumPtr, ApiConfig_t ApiConfig, uint32 Status ); + +#endif /* __TASK_API_TASKSETUP_BDTABLE_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h new file mode 100644 index 0000000000..be7bb9d7b0 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h @@ -0,0 +1,624 @@ +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +/* + * Task builder generates a set #defines per configured task to + * condition this templete file. + */ + +/********************************************************** + * + * Required #defines: + * ------------------ + * TASKSETUP_NAME: + * TaskSetup function name, set to TaskSetup_ + * TASK_API: + * task API defined in dma_image.h + * MAX_BD: + * <=0 : non-BD task + * else: number of BD in BD table + * BD_FLAG: + * 0 : no flag implemented for BD + * else: flags can be passed on a per BD basis + * MISALIGNED: + * 0 : task API supports Bytes%IncrBytes==0 + * else: task API supports any parameter settings + * AUTO_START: + * <-1 : do not start a task after task completion + * -1 : auto start the task after task completion + * 0 + * else: 16 + * ITERATIONS: + * 1 : #define ITERATIONS>0 + * else: 1 + * INCR_BYTES: + * This macro is defined based on following priority: + * 1 : INCR_SRC != 0 + * 2 : DST_TYPE != 0 + * 3 : #defined INCR_BYTES<0 + * else: -4 (SZ_UINT32) + * DEBUG_BESTCOMM_API: + * >0 : print basic debug messages + * >=10: also print C-API interface variables + * >=20: also print task API interface variables + * else: do nothing + * + **********************************************************/ + +#if defined(__rtems__) || defined(MPC5200_BAPI_LIBC_HEADERS) +#include +#endif + +#include "../dma_image.h" + +#include "../bestcomm_api.h" +#include "tasksetup_bdtable.h" + +#include "bestcomm_api_mem.h" +#include "bestcomm_cntrl.h" + +#ifndef DEBUG_BESTCOMM_API + #define DEBUG_BESTCOMM_API 0 +#endif + +#ifdef FLEX_T + #undef FLEX_T +#endif +#define FLEX_T SZ_FLEX + +#ifdef UINT8_T + #undef UINT8_T +#endif +#define UINT8_T SZ_UINT8 + +#ifdef UINT16_T + #undef UINT16_T +#endif +#define UINT16_T SZ_UINT16 + +#ifdef UINT32_T + #undef UINT32_T +#endif +#define UINT32_T SZ_UINT32 + +#if (INCR_TYPE_SRC==0) /* FIFO address, no data pointer */ + #undef INCR_SRC + #define INCR_SRC 0 +#endif + +#if (INCR_TYPE_DST==0) /* FIFO address, no data pointer */ + #undef INCR_DST + #define INCR_DST 0 +#endif + +#ifndef MAX_TASKS + #define MAX_TASKS 16 +#else + #if (MAX_TASKS<=0) + #undef MAX_TASKS + #define MAX_TASKS 16 + #endif +#endif + +#ifndef ITERATIONS + #define ITERATIONS 1 +#else + #if (ITERATIONS<=0) + #undef ITERATIONS + #define ITERATIONS 1 + #endif +#endif + +#ifndef INCR_BYTES + #define INCR_BYTES -4 +#else + #if (INCR_BYTES>=0) + #undef INCR_BYTES + #define INCR_BYTES -4 + #endif +#endif + +/* + * These ifndefs will go away when support in task_capi wrappers + * in the image directories + */ +#ifndef PRECISE_INCREMENT + #define PRECISE_INCREMENT 0 /* bit=6 SAS->1, increment 0=when possible, 1=at the end of interation */ +#endif +#ifndef NO_ERROR_RESET + #define NO_ERROR_RESET 0 /* bit=5 SAS->0, do not reset error codes on task enable */ +#endif +#ifndef PACK_DATA + #define PACK_DATA 0 /* bit=4 SAS->0, pack data enable */ +#endif +#ifndef INTEGER_MODE + #define INTEGER_MODE 0 /* bit=3 SAS->0, 0=fractional(msb aligned), 1=integer(lsb aligned) */ +#endif +#ifndef SPEC_READS + #define SPEC_READS 1 /* bit=2 SAS->0, XLB speculative read enable */ +#endif +#ifndef WRITE_LINE_BUFFER + #define WRITE_LINE_BUFFER 1 /* bit=1 SAS->0, write line buffer enable */ +#endif +#ifndef READ_LINE_BUFFER + #define READ_LINE_BUFFER 1 /* bit=0 SAS->0, read line buffer enable */ +#endif +#define SDMA_PRAGMA (0 <0)||(DEBUG_BESTCOMM_API>0)) + uint32 Status = 0; +#endif +#if ((MAX_BD>0)&&((INCR_TYPE_SRC!=0)||(INCR_TYPE_DST!=0))||(DEBUG_BESTCOMM_API>0)) + uint8 NumPtr = 0; +#endif +#if (INITIATOR_DATA<0) /* runtime configurable */ + uint32 i, ext; +#endif + + INIT_DMA_IMAGE((uint8 *)(((sdma_regs *)(SDMA_TASK_BAR))->taskBar), MBarPhysOffsetGlobal); + + TaskNum = (TaskId)SDMA_TASKNUM_EXT(TaskAPI->TaskNum); + + TaskRunning[TaskNum] = 0; + +#if (DEBUG_BESTCOMM_API>0) + printf("\nBestComm API Debug Display Mode Enabled\n\n"); + printf("TaskSetup: TaskID=%d\n", TaskNum); + if (Status!=0) { + printf("TaskSetup: Rx task\n"); + } else { + printf("TaskSetup: Tx or DP task\n"); + } +#endif + + /* Set the task pragma settings */ + *(TaskAPI->TaskPragma)= (uint8) SDMA_PRAGMA; + +#if (MAX_BD>0) /* Buffer Descriptors */ + + #if (INCR_TYPE_SRC!=0) + ++NumPtr; + #endif + #if (INCR_TYPE_DST!=0) + ++NumPtr; + #endif + + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Using %d buffer descriptors, each with %d data pointers\n", MAX_BD, NumPtr); + #endif + + /* Allocate BD table SRAM storage, + * and pass addresses to task API */ + + TaskSetup_BDTable(TaskAPI->BDTableBase, + TaskAPI->BDTableLast, + TaskAPI->BDTableStart, + TaskNum, + TaskSetupParams->NumBD, + MAX_BD, NumPtr, + BD_FLAG, Status); + + *TaskAPI->AddrEnable = (uint32)((uint32)(((uint16 *)SDMA_TCR)+TaskNum) + MBarPhysOffsetGlobal); + + #if BD_FLAG + + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Buffer descriptor flags are enabled\n"); + #endif + + /* always assume 2nd to last DRD */ + *((TaskAPI->AddrDRD)) = (uint32)((uint32)TaskAPI->DRD[TaskAPI->AddrDRDIdx] + MBarPhysOffsetGlobal); + #endif /* #if BD_FLAG */ + +#else /* No Buffer Descriptors */ + +/* #error ATA should not be non-BD */ + + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Task will complete %d iterations before disabling\n"); + #endif + + *((TaskAPI->IterExtra)) = (uint32)(ITERATIONS-1); +#endif /* #if (MAX_BD>0) */ + +/* Setup auto start */ +#if (AUTO_START <= -2 ) /* do not start a task */ + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Auto task start disabled\n"); + #endif + SDMA_TASK_CFG(SDMA_TCR, TaskNum, 0, TaskNum); +#elif (AUTO_START <= -1 ) /* restart task */ + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Auto start task\n"); + #endif + SDMA_TASK_CFG(SDMA_TCR, TaskNum, 1, TaskNum); +#elif (AUTO_START < MAX_TASKS) /* start specific task */ + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Auto start task with TaskID=%d\n", AUTO_START); + #endif + SDMA_TASK_CFG(SDMA_TCR, TaskNum, 1, AUTO_START); +#else /* do not start a task */ + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Auto task start disabled\n"); + #endif + SDMA_TASK_CFG(SDMA_TCR, TaskNum, 0, TaskNum); +#endif + +#if (INITIATOR_DATA<0) /* runtime configurable */ + SDMA_SET_INIT(SDMA_TCR, TaskNum, TaskSetupParams->Initiator); + + /* + * Hard-code the task initiator in the DRD to avoid a problem w/ the + * hold initiator bit in the TCR. + */ + ext = 0; + for (i = 0; i < TaskAPI->NumDRD; i++) { + if (ext == 0) + { +#if (DEBUG_BESTCOMM_API>=10) + printf("TaskSetup: DRD[%d] initiator = %d\n", i, ((*(TaskAPI->DRD[i]) & ~DRD_INIT_MASK) >> DRD_INIT_OFFSET)); +#endif + if (((*(TaskAPI->DRD[i]) & ~DRD_INIT_MASK) >> DRD_INIT_OFFSET) != INITIATOR_ALWAYS) { +#if (DEBUG_BESTCOMM_API>=10) + printf("TaskSetup: Replacing DRD[%d] initiator with %d\n", i, TaskSetupParams->Initiator); +#endif + *(TaskAPI->DRD[i]) = (*(TaskAPI->DRD[i]) & DRD_INIT_MASK) + | (TaskSetupParams->Initiator << DRD_INIT_OFFSET); + } + + if ((*(TaskAPI->DRD[i]) & DRD_EXT_FLAG) != 0) + { + ext = 1; + } + } + else + { + if ((*(TaskAPI->DRD[i]) & DRD_EXT_FLAG) == 0) + { + ext = 0; + } + } + } + +#else /* INITIATOR_DATA >= 0 */ + TaskSetupParams->Initiator = INITIATOR_DATA; +#endif + +#if (DEBUG_BESTCOMM_API>=10) + printf("\nTaskSetup: C-API Parameter Settings Passed to TaskSetup:\n"); + printf("TaskSetup: NumBD = %d\n", TaskSetupParams->NumBD); + #if (MAX_BD>0) + printf("TaskSetup: MaxBuf = %d\n", TaskSetupParams->Size.MaxBuf); + #else + printf("TaskSetup: NumBytes = %d\n", TaskSetupParams->Size.NumBytes); + #endif + printf("TaskSetup: Initiator = %d\n", TaskSetupParams->Initiator); + printf("TaskSetup: StartAddrSrc = 0x%08X\n", TaskSetupParams->StartAddrSrc); + printf("TaskSetup: IncrSrc = %d\n", TaskSetupParams->IncrSrc); + printf("TaskSetup: SzSrc = %d\n", TaskSetupParams->SzSrc); + printf("TaskSetup: StartAddrDst = 0x%08X\n", TaskSetupParams->StartAddrDst); + printf("TaskSetup: IncrDst = %d\n", TaskSetupParams->IncrDst); + printf("TaskSetup: SzDst = %d\n", TaskSetupParams->SzDst); +#endif + +#if (DEBUG_BESTCOMM_API>=20) + printf("\nTaskSetup: Task-API Parameter Settings Before TaskSetup Initialization:\n"); + printf("TaskSetup: TaskNum = %d\n", (TaskAPI->TaskNum)); + printf("TaskSetup: TaskPragma = 0x%02X\n", *((TaskAPI->TaskPragma))); + printf("TaskSetup: TCR = 0x%04x\n", SDMA_TASK_STATUS(SDMA_TCR, TaskNum)); + + #if (MAX_BD>0) + printf("TaskSetup: BDTableBase = 0x%08X\n", *((TaskAPI->BDTableBase))); + printf("TaskSetup: BDTableLast = 0x%08X\n", *((TaskAPI->BDTableLast))); + printf("TaskSetup: BDTableStart = 0x%08X\n", *((TaskAPI->BDTableStart))); + printf("TaskSetup: AddrEnable = 0x%08X\n", *((TaskAPI->AddrEnable))); + #if (INCR_TYPE_SRC==0) + printf("TaskSetup: AddrSrcFIFO = 0x%08X\n", *((TaskAPI->AddrSrcFIFO))); + #endif + #if (INCR_TYPE_DST==0) + printf("TaskSetup: AddrDstFIFO = 0x%08X\n", *((TaskAPI->AddrDstFIFO))); + #endif + #if (BD_FLAG) + printf("TaskSetup: AddrDRD = 0x%08X\n", *((TaskAPI->AddrDRD))); + printf("TaskSetup: AddrDRDIdx = %d\n", ((TaskAPI->AddrDRDIdx))); + #endif + #else + printf("TaskSetup: IterExtra = %d\n", *((TaskAPI->IterExtra))); + #if (INCR_TYPE_SRC==0) + printf("TaskSetup: AddrSrcFIFO = 0x%08X\n", *((TaskAPI->AddrSrcFIFO))); + #else + printf("TaskSetup: StartAddrSrc = 0x%08X\n", *((TaskAPI->StartAddrSrc))); + #endif + #if (INCR_TYPE_DST==0) + printf("TaskSetup: AddrDstFIFO = 0x%08X\n", *((TaskAPI->AddrDstFIFO))); + #else + printf("TaskSetup: StartAddrDst = 0x%08X\n", *((TaskAPI->StartAddrDst))); + #endif + #endif + #if (INCR_TYPE_SRC!=0) + printf("TaskSetup: IncrSrc = 0x%04X\n", *((TaskAPI->IncrSrc))); + #if (MISALIGNED | MISALIGNED_START) + printf("TaskSetup: IncrSrcMA = 0x%04X\n", *((TaskAPI->IncrSrcMA))); + #endif + #endif + #if (INCR_TYPE_DST!=0) + printf("TaskSetup: IncrDst = 0x%04X\n", *((TaskAPI->IncrDst))); + #if (MISALIGNED | MISALIGNED_START) + printf("TaskSetup: IncrDstMA = 0x%04X\n", *((TaskAPI->IncrDstMA))); + #endif + #endif + printf("TaskSetup: Bytes = %d\n", *((TaskAPI->Bytes))); + printf("TaskSetup: IncrBytes = %d\n", *((TaskAPI->IncrBytes))); +#endif + + + *((TaskAPI->Bytes)) = (uint32)TaskSetupParams->Size.MaxBuf; + + +#if (TYPE_SRC!=FLEX_T) /* size fixed in task code */ + TaskSetupParams->SzSrc = TYPE_SRC; +#endif + +#if (INCR_TYPE_SRC==0) /* no data pointer */ + TaskSetupParams->IncrSrc = (sint16)0; + *((TaskAPI->AddrSrcFIFO)) = (uint32)TaskSetupParams->StartAddrSrc; +#else + + #if (INCR_TYPE_SRC==1) /* automatic */ + if (TaskSetupParams->IncrSrc!=0) { + TaskSetupParams->IncrSrc = (sint16)+TaskSetupParams->SzSrc; + } else { + TaskSetupParams->IncrSrc = (sint16)+TaskSetupParams->IncrSrc; + } + #elif (INCR_TYPE_SRC!=2) /* hard-coded */ + TaskSetupParams->IncrSrc = (sint16)INCR_SRC; + #endif + *((TaskAPI->IncrSrc)) = (sint16)TaskSetupParams->IncrSrc; + + #if (MAX_BD>0) /* pointer in BD Table */ + /* pass back address of first BD */ + TaskSetupParams->StartAddrSrc = (uint32)TaskGetBDRing(TaskNum); + #else + *((TaskAPI->StartAddrSrc)) = (uint32)TaskSetupParams->StartAddrSrc; + #endif + + #if MISALIGNED | MISALIGNED_START + if (TaskSetupParams->IncrSrc < 0) { + *((TaskAPI->IncrSrcMA)) = (sint16)-1; + } else if (TaskSetupParams->IncrSrc > 0) { + *((TaskAPI->IncrSrcMA)) = (sint16)+1; + } else { + *((TaskAPI->IncrSrcMA)) = (sint16)0; + } + #endif +#endif + + +#if (TYPE_DST!=FLEX_T) /* size fixed in task code */ + TaskSetupParams->SzDst = TYPE_DST; +#endif + +#if (INCR_TYPE_DST==0) /* no data pointer */ + TaskSetupParams->IncrDst = (sint16)0; + *((TaskAPI->AddrDstFIFO)) = (uint32)TaskSetupParams->StartAddrDst; +#else + #if (INCR_TYPE_DST==1) /* automatic */ + if (TaskSetupParams->IncrDst!=0) { + TaskSetupParams->IncrDst = (sint16)+TaskSetupParams->SzDst; + } else { + TaskSetupParams->IncrDst = (sint16)+TaskSetupParams->IncrDst; + } + #elif (INCR_TYPE_DST!=2) /* hard-coded */ + TaskSetupParams->IncrDst = (sint16)INCR_DST; + #endif + *((TaskAPI->IncrDst)) = (sint16)TaskSetupParams->IncrDst; + + #if (MAX_BD>0) + /* pass back address of first BD */ + TaskSetupParams->StartAddrDst = (uint32)TaskGetBDRing(TaskNum); + #else + *((TaskAPI->StartAddrDst)) = (uint32)TaskSetupParams->StartAddrDst; + #endif + + #if MISALIGNED | MISALIGNED_START + if (TaskSetupParams->IncrDst < 0) { + *((TaskAPI->IncrDstMA)) = (sint16)-1; + } else if (TaskSetupParams->IncrDst > 0) { + *((TaskAPI->IncrDstMA)) = (sint16)+1; + } else { + *((TaskAPI->IncrDstMA)) = (sint16)0; + } + #endif +#endif + +/* always use macro, only affect code with #define TYPE_? flex */ + SDMA_SET_SIZE(SDMA_TASK_SIZE, TaskNum, TaskSetupParams->SzSrc, TaskSetupParams->SzDst); + + + if (TaskSetupParams->IncrSrc != 0) { + *((TaskAPI->IncrBytes)) = (sint16)-abs(TaskSetupParams->IncrSrc); + } else if (TaskSetupParams->IncrDst != 0) { + *((TaskAPI->IncrBytes)) = (sint16)-abs(TaskSetupParams->IncrDst); + } else { + *((TaskAPI->IncrBytes)) = (sint16)-abs(INCR_BYTES); + } + + +#if (DEBUG_BESTCOMM_API>=10) + printf("\nTaskSetup: C-API Parameter Settings Returned from TaskSetup:\n"); + printf("TaskSetup: NumBD = %d\n", TaskSetupParams->NumBD); + #if (MAX_BD>0) + printf("TaskSetup: MaxBuf = %d\n", TaskSetupParams->Size.MaxBuf); + #else + printf("TaskSetup: NumBytes = %d\n", TaskSetupParams->Size.NumBytes); + #endif + printf("TaskSetup: Initiator = %d\n", TaskSetupParams->Initiator); + printf("TaskSetup: StartAddrSrc = 0x%08X\n", TaskSetupParams->StartAddrSrc); + printf("TaskSetup: IncrSrc = %d\n", TaskSetupParams->IncrSrc); + printf("TaskSetup: SzSrc = %d\n", TaskSetupParams->SzSrc); + printf("TaskSetup: StartAddrDst = 0x%08X\n", TaskSetupParams->StartAddrDst); + printf("TaskSetup: IncrDst = %d\n", TaskSetupParams->IncrDst); + printf("TaskSetup: SzDst = %d\n", TaskSetupParams->SzDst); +#endif + +#if (DEBUG_BESTCOMM_API>=20) + printf("\nTaskSetup: Task-API Parameter Settings After TaskSetup Initialization:\n"); + printf("TaskSetup: TaskNum = %d\n", ((TaskAPI->TaskNum))); + printf("TaskSetup: TaskPragma = 0x%02X\n", *((TaskAPI->TaskPragma))); + + #if (MAX_BD>0) + printf("TaskSetup: BDTableBase = 0x%08X\n", *((TaskAPI->BDTableBase))); + printf("TaskSetup: BDTableLast = 0x%08X\n", *((TaskAPI->BDTableLast))); + printf("TaskSetup: BDTableStart = 0x%08X\n", *((TaskAPI->BDTableStart))); + printf("TaskSetup: AddrEnable = 0x%08X\n", *((TaskAPI->AddrEnable))); + #if (INCR_TYPE_SRC==0) + printf("TaskSetup: AddrSrcFIFO = 0x%08X\n", *((TaskAPI->AddrSrcFIFO))); + #endif + #if (INCR_TYPE_DST==0) + printf("TaskSetup: AddrDstFIFO = 0x%08X\n", *((TaskAPI->AddrDstFIFO))); + #endif + #if (BD_FLAG) + printf("TaskSetup: AddrDRD = 0x%08X\n", *((TaskAPI->AddrDRD))); + printf("TaskSetup: AddrDRDIdx = %d\n", ((TaskAPI->AddrDRDIdx))); + #endif + #else + printf("TaskSetup: IterExtra = %d\n", *((TaskAPI->IterExtra))); + #if (INCR_TYPE_SRC==0) + printf("TaskSetup: AddrSrcFIFO = 0x%08X\n", *((TaskAPI->AddrSrcFIFO))); + #else + printf("TaskSetup: StartAddrSrc = 0x%08X\n", *((TaskAPI->StartAddrSrc))); + #endif + #if (INCR_TYPE_DST==0) + printf("TaskSetup: AddrDstFIFO = 0x%08X\n", *((TaskAPI->AddrDstFIFO))); + #else + printf("TaskSetup: StartAddrDst = 0x%08X\n", *((TaskAPI->StartAddrDst))); + #endif + #endif + #if (INCR_TYPE_SRC!=0) + printf("TaskSetup: IncrSrc = 0x%04X\n", *((TaskAPI->IncrSrc))); + #if (MISALIGNED | MISALIGNED_START) + printf("TaskSetup: IncrSrcMA = 0x%04X\n", *((TaskAPI->IncrSrcMA))); + #endif + #endif + #if (INCR_TYPE_DST!=0) + printf("TaskSetup: IncrDst = 0x%04X\n", *((TaskAPI->IncrDst))); + #if (MISALIGNED | MISALIGNED_START) + printf("TaskSetup: IncrDstMA = 0x%04X\n", *((TaskAPI->IncrDstMA))); + #endif + #endif + printf("TaskSetup: Bytes = %d\n", *((TaskAPI->Bytes))); + printf("TaskSetup: IncrBytes = %d\n", *((TaskAPI->IncrBytes))); +#endif + + return TaskNum; +} diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h b/bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h new file mode 100644 index 0000000000..2b74adf366 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef BESTCOMM_OPS_H +#define BESTCOMM_OPS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup BestCommOps BestComm Ops + * + * @ingroup BestComm + * + * @brief BestComm ops. + * + * @{ + */ + +#define VAR(i) (i) +#define VAR_COUNT 24 +#define INC(i) (24 + (i)) +#define INC_COUNT 8 +#define IDX(i) (48 + (i)) +#define IDX_COUNT 8 + +#define COND_ONCE 0 +#define COND_LT 1 +#define COND_GT 2 +#define COND_NE 3 +#define COND_EQ 4 +#define COND_LE 5 +#define COND_GE 6 +#define COND_FOREVER 7 + +#define INC_INIT(cond, val) \ + (BSP_FLD32(cond, 29, 31) \ + | BSP_FLD32((int16_t) (val), 0, 15)) + +#define TERM_FIRST 0 +#define TERM_SECOND 1 +#define TERM_INIT 2 +#define TERM_UNUSED 3 + +#define DEREF 1 + +#define LCD_TERM(val) BSP_FLD32(val, 13, 14) + +#define LCD(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1) \ + (BSP_BIT32(31) \ + | BSP_FLD32(deref0, 29, 29) \ + | BSP_FLD32(iniidx0, 23, 28) \ + | BSP_FLD32(deref1, 21, 21) \ + | BSP_FLD32(iniidx1, 15, 20) \ + | LCD_TERM(term) \ + | BSP_FLD32(termop, 6, 11) \ + | BSP_FLD32(inc0, 3, 5) \ + | BSP_FLD32(inc1, 0, 2)) + +#define LCDEXT(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1) \ + (BSP_BIT32(30) \ + | LCD(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1)) + +#define LCDPLUS(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1) \ + (BSP_BIT32(22) \ + | LCD(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1)) + +#define LCDINIT(val) \ + (BSP_BIT32(31) \ + | BSP_FLD32((val) >> 13, 15, 29) \ + | LCD_TERM(TERM_INIT) \ + | BSP_FLD32(val, 0, 12)) + +#define MORE 0x4 + +#define TFD 0x2 + +#define INT 0x1 + +#define DRD_FLAGS(val) BSP_FLD32(val, 26, 28) + +#define INIT_ALWAYS 0 +#define INIT_SCTMR_0 1 +#define INIT_SCTMR_1 2 +#define INIT_FEC_RX 3 +#define INIT_FEC_TX 4 +#define INIT_ATA_RX 5 +#define INIT_ATA_TX 6 +#define INIT_SCPCI_RX 7 +#define INIT_SCPCI_TX 8 +#define INIT_PSC3_RX 9 +#define INIT_PSC3_TX 10 +#define INIT_PSC2_RX 11 +#define INIT_PSC2_TX 12 +#define INIT_PSC1_RX 13 +#define INIT_PSC1_TX 14 +#define INIT_SCTMR_2 15 +#define INIT_SCLPC 16 +#define INIT_PSC5_RX 17 +#define INIT_PSC5_TX 18 +#define INIT_PSC4_RX 19 +#define INIT_PSC4_TX 20 +#define INIT_I2C2_RX 21 +#define INIT_I2C2_TX 22 +#define INIT_I2C1_RX 23 +#define INIT_I2C1_TX 24 +#define INIT_PSC6_RX 25 +#define INIT_PSC6_TX 26 +#define INIT_IRDA_RX 25 +#define INIT_IRDA_TX 26 +#define INIT_SCTMR_3 27 +#define INIT_SCTMR_4 28 +#define INIT_SCTMR_5 29 +#define INIT_SCTMR_6 30 +#define INIT_SCTMR_7 31 + +#define DRD_INIT(val) BSP_FLD32(val, 21, 25) + +#define SZ_8 1 +#define SZ_16 2 +#define SZ_32 0 +#define SZ_DYN 3 + +#define DRD_RS(val) BSP_FLD32(val, 19, 20) + +#define DRD_WS(val) BSP_FLD32(val, 17, 18) + +#define DEST_VAR(val) (val) +#define DEST_IDX(val) (BSP_BIT32(5) | (val)) +#define DEST_DEREF_IDX(val) (BSP_BIT32(5) | BSP_BIT32(4) | (val)) + +#define SRC_VAR(val) (val) +#define SRC_INC(val) (BSP_BIT32(5) | (val)) +#define SRC_EU_RESULT (BSP_BIT32(5) | BSP_BIT32(4) | BSP_BIT32(1) | BSP_BIT32(0)) +#define SRC_DEREF_EU_RESULT (BSP_BIT32(6) | BSP_BIT32(4) | BSP_BIT32(1) | BSP_BIT32(0)) +#define SRC_IDX(val) (BSP_BIT32(6) | BSP_BIT32(5) | (val)) +#define SRC_DEREF_IDX(val) (BSP_BIT32(6) | BSP_BIT32(5) | BSP_BIT32(4) | (val)) +#define SRC_NONE (BSP_BIT32(5) | BSP_BIT32(4) | BSP_BIT32(3) | BSP_BIT32(2) | BSP_BIT32(1) | BSP_BIT32(0)) + +#define DRD1A(flags, init, dest, ws, src, rs) \ + (DRD_FLAGS(flags) \ + | DRD_INIT(init) \ + | DRD_RS(rs) \ + | DRD_WS(ws) \ + | BSP_FLD32(dest, 10, 15) \ + | BSP_FLD32(src, 3, 9)) + +#define DRD1AEURESULT(flags, init, dest, ws, rs) \ + (DRD1A(flags, init, rs, ws, dest, SRC_EU_RESULT) \ + | BSP_FLD32(1, 0, 3)) + +#define FUNC_LOAD_ACC 0 +#define FUNC_UNLOAD_ACC 1 +#define FUNC_AND 2 +#define FUNC_OR 3 +#define FUNC_XOR 4 +#define FUNC_ANDN 5 +#define FUNC_NOT 6 +#define FUNC_ADD 7 +#define FUNC_SUB 8 +#define FUNC_LSH 9 +#define FUNC_RSH 10 +#define FUNC_CRC8 11 +#define FUNC_CRC16 12 +#define FUNC_CRC32 13 +#define FUNC_ENDIAN32 14 +#define FUNC_ENDIAN16 15 + +#define DRD2A(flags, func) \ + (BSP_BIT32(30) | BSP_BIT32(29) \ + | DRD_FLAGS(flags) \ + | BSP_FLD32(func, 0, 3)) + +#define DRD2A5(flags, init, func, ws, rs) \ + (DRD2A(flags, func) \ + | DRD_RS(rs) \ + | DRD_WS(ws) \ + | DRD_INIT(init)) + +#define OP_VAR(val) (val) +#define OP_EU_RESULT (BSP_BIT32(4) | BSP_BIT32(3) | BSP_BIT32(1) | BSP_BIT32(0)) +#define OP_NONE (BSP_BIT32(4) | BSP_BIT32(3) | BSP_BIT32(2) | BSP_BIT32(1) | BSP_BIT32(0)) +#define OP_IDX(val) (BSP_BIT32(5) | (val)) +#define OP_DEREF_IDX(val) (BSP_BIT32(5) | BSP_BIT32(4) | (val)) + +#define DRD2B1(dest, op0, op1) \ + (BSP_FLD32(dest, 22, 27) \ + | BSP_FLD32(SRC_EU_RESULT, 14, 20) \ + | BSP_FLD32(3, 12, 13) \ + | BSP_FLD32(op0, 6, 11) \ + | BSP_FLD32(op1, 0, 5)) + +#define DRD2B2(op0, op1) \ + (BSP_BIT32(29) \ + | BSP_FLD32(3, 26, 27) \ + | BSP_FLD32(op0, 20, 25) \ + | BSP_FLD32(op1, 14, 19) \ + | BSP_FLD32(0, 12, 13) \ + | BSP_FLD32(OP_NONE, 6, 11) \ + | BSP_FLD32(OP_NONE, 0, 5)) + +#define NOP 0x1f8 + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* BESTCOMM_OPS_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/i2c.h b/bsps/powerpc/gen5200/include/bsp/i2c.h new file mode 100644 index 0000000000..e5d7d472dd --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/i2c.h @@ -0,0 +1,243 @@ +/* + * Generic I2C bus interface for RTEMS + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __RTEMS__I2C_H__ +#define __RTEMS__I2C_H__ + +#include +#include +/* This header file define the generic interface to i2c buses available in + * system. This interface may be used by user applications or i2c-device + * drivers (like RTC, NVRAM, etc). + * + * Functions i2c_initialize and i2c_transfer declared in this header usually + * implemented in particular board support package. Usually this + * implementation is a simple wrapper or multiplexor to I2C controller + * driver which is available in system. It may be generic "software + * controller" I2C driver which control SDA and SCL signals directly (if SDA + * and SCL is general-purpose I/O pins), or driver for hardware I2C + * controller (standalone or integrated with processors: MBus controller in + * ColdFire processors, I2C controller in PowerQUICC and so on). + * + * i2c_transfer is a very generic low-level function. Higher-level function + * i2c_write, i2c_read, i2c_wrrd, i2c_wbrd is defined here too. + */ + +/* I2C Bus Number type */ +typedef uint32_t i2c_bus_number; + +/* I2C device address */ +typedef uint16_t i2c_address; + +/* I2C error codes generated during message transfer */ +typedef enum i2c_message_status { + I2C_SUCCESSFUL = 0, + I2C_TIMEOUT, + I2C_NO_DEVICE, + I2C_ARBITRATION_LOST, + I2C_NO_ACKNOWLEDGE, + I2C_NO_DATA, + I2C_RESOURCE_NOT_AVAILABLE +} i2c_message_status; + +/* I2C Message */ +typedef struct i2c_message { + i2c_address addr; /* I2C slave device address */ + uint16_t flags; /* message flags (see below) */ + i2c_message_status status; /* message transfer status code */ + uint16_t len; /* Number of bytes to read or write */ + uint8_t *buf; /* pointer to data array */ +} i2c_message; + +/* I2C message flag */ +#define I2C_MSG_ADDR_10 (0x01) /* 10-bit address */ +#define I2C_MSG_WR (0x02) /* transfer direction for this message + from master to slave */ +#define I2C_MSG_ERRSKIP (0x04) /* Skip message if last transfered message + is failed */ +/* Type for function which is called when transfer over I2C bus is finished */ +typedef void (*i2c_transfer_done) (void * arg); + +/* i2c_initialize -- + * I2C driver initialization. This function usually called on device + * driver initialization state, before initialization task. All I2C + * buses are initialized; reasonable slow data transfer rate is + * selected for each bus. + * + * PARAMETERS: + * major - I2C device major number + * minor - I2C device minor number + * arg - RTEMS driver initialization argument + * + * RETURNS: + * RTEMS status code + */ +rtems_device_driver +i2c_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* i2c_select_clock_rate -- + * select I2C bus clock rate for specified bus. Some bus controller do not + * allow to select arbitrary clock rate; in this case nearest possible + * slower clock rate is selected. + * + * PARAMETERS: + * bus - I2C bus number + * bps - data transfer rate for this bytes in bits per second + * + * RETURNS: + * RTEMS_SUCCESSFUL, if operation performed successfully, + * RTEMS_INVALID_NUMBER, if wrong bus number is specified, + * RTEMS_UNSATISFIED, if bus do not support data transfer rate selection + * or specified data transfer rate could not be used. + */ +rtems_status_code +i2c_select_clock_rate(i2c_bus_number bus, int bps); + +/* i2c_transfer -- + * Initiate multiple-messages transfer over specified I2C bus or + * put request into queue if bus or some other resource is busy. (This + * is non-blocking function). + * + * PARAMETERS: + * bus - I2C bus number + * nmsg - number of messages + * msg - pointer to messages array + * done - function which is called when transfer is finished + * done_arg_ptr - arbitrary argument ptr passed to done funciton + * + * RETURNS: + * RTEMS_SUCCESSFUL if transfer initiated successfully, or error + * code if something failed. + */ +rtems_status_code +i2c_transfer(i2c_bus_number bus, int nmsg, i2c_message *msg, + i2c_transfer_done done, void *done_arg); + +/* i2c_transfer_wait -- + * Initiate I2C bus transfer and block until this transfer will be + * finished. This function wait the semaphore if system in + * SYSTEM_STATE_UP state, or poll done flag in other states. + * + * PARAMETERS: + * bus - I2C bus number + * msg - pointer to transfer messages array + * nmsg - number of messages in transfer + * + * RETURNS: + * I2C_SUCCESSFUL, if tranfer finished successfully, + * I2C_RESOURCE_NOT_AVAILABLE, if semaphore operations has failed, + * value of status field of first error-finished message in transfer, + * if something wrong. + */ +i2c_message_status +i2c_transfer_wait(i2c_bus_number bus, i2c_message *msg, int nmsg); + +/* i2c_poll -- + * Poll I2C bus controller for events and hanle it. This function is + * used when I2C driver operates in poll-driven mode. + * + * PARAMETERS: + * bus - bus number to be polled + * + * RETURNS: + * none + */ +void +i2c_poll(i2c_bus_number bus); + +/* i2c_write -- + * Send single message over specified I2C bus to addressed device and + * wait while transfer is finished. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * buf - data to be sent to device + * size - data buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_write(i2c_bus_number bus, i2c_address addr, void *buf, int size); + +/* i2c_wrbyte -- + * Send single one-byte long message over specified I2C bus to + * addressed device and wait while transfer is finished. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * cmd - byte message to be sent to device + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_wrbyte(i2c_bus_number bus, i2c_address addr, uint8_t cmd); + +/* i2c_read -- + * receive single message over specified I2C bus from addressed device. + * This call will wait while transfer is finished. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * buf - buffer for received message + * size - receive buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_read(i2c_bus_number bus, i2c_address addr, void *buf, int size); + +/* i2c_wrrd -- + * Send message over I2C bus to specified device and receive message + * from the same device during single transfer. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * bufw - data to be sent to device + * sizew - send data buffer size + * bufr - buffer for received message + * sizer - receive buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_wrrd(i2c_bus_number bus, i2c_address addr, void *bufw, int sizew, + void *bufr, int sizer); + +/* i2c_wbrd -- + * Send one-byte message over I2C bus to specified device and receive + * message from the same device during single transfer. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * cmd - one-byte message to be sent over I2C bus + * bufr - buffer for received message + * sizer - receive buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_wbrd(i2c_bus_number bus, i2c_address addr, uint8_t cmd, + void *bufr, int sizer); + +#endif diff --git a/bsps/powerpc/gen5200/include/bsp/i2cdrv.h b/bsps/powerpc/gen5200/include/bsp/i2cdrv.h new file mode 100644 index 0000000000..4b4a1ec141 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/i2cdrv.h @@ -0,0 +1,35 @@ +/* + * i2cdrv.h -- I2C bus driver prototype and definitions + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __I2CDRV_H__ +#define __I2CDRV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2C_DRIVER_TABLE_ENTRY \ + { i2cdrv_initialize, NULL, NULL, NULL, NULL, NULL } + +/* i2cdrv_initialize -- + * I2C driver initialization (rtems I/O driver primitive) + */ +rtems_device_driver +i2cdrv_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __I2CDRV_H__ */ diff --git a/bsps/powerpc/gen5200/include/bsp/irq.h b/bsps/powerpc/gen5200/include/bsp/irq.h new file mode 100644 index 0000000000..5a0b3bd29e --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/irq.h @@ -0,0 +1,212 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2005, 2010 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains declarations for the irq controller handler | +\*===============================================================*/ +/***********************************************************************/ +/* */ +/* Module: irq.h */ +/* Date: 07/17/2003 */ +/* Purpose: RTEMS MPC5x00 CPU interrupt header file */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Description: This include file describe the data structure and */ +/* the functions implemented by rtems to write */ +/* interrupt handlers. */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Code */ +/* References: MPC8260ads CPU interrupt header file */ +/* Module: irq.h */ +/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ +/* Version 1.1 */ +/* Date: 10/10/2002 */ +/* */ +/* Author(s) / Copyright(s): */ +/* */ +/* Copyright (C) 1999 valette@crf.canon.fr */ +/* */ +/* This code is heavilly inspired by the public specification of */ +/* STREAM V2 that can be found at: */ +/* */ +/* by following */ +/* the STREAM API Specification Document link. */ +/* */ +/* Modified for mpc8260 by Andy Dachs */ +/* Surrey Satellite Technology Limited */ +/* The interrupt handling on the mpc8260 seems quite different from */ +/* the 860 (I don't know the 860 well). Although some interrupts */ +/* are routed via the CPM irq and some are direct to the SIU they */ +/* all appear logically the same.Therefore I removed the distinction */ +/* between SIU and CPM interrupts. */ +/* */ +/* The license and distribution terms for this file may be */ +/* found in the file LICENSE in this distribution or at */ +/* http://www.rtems.org/license/LICENSE. */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Partially based on the code references which are named above. */ +/* Adaptions, modifications, enhancements and any recent parts of */ +/* the code are under the right of */ +/* */ +/* IPR Engineering, Dachauer Straße 38, D-80335 München */ +/* Copyright(C) 2003 */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* IPR Engineering makes no representation or warranties with */ +/* respect to the performance of this computer program, and */ +/* specifically disclaims any responsibility for any damages, */ +/* special or consequential, connected with the use of this program. */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Version history: 1.0 */ +/* */ +/***********************************************************************/ + +#ifndef LIBBSP_POWERPC_GEN5200_IRQ_H +#define LIBBSP_POWERPC_GEN5200_IRQ_H + +#define PMCE_CE_SHADOW (1U << (31 - 31)) +#define PMCE_CSE_STICKY (1U << (31 - 21)) +#define PMCE_MSE_STICKY (1U << (31 - 10)) +#define PMCE_PSE_STICKY (1U << (31 - 2)) +#define PMCE_CSE_SOURCE(_pmce) (((_pmce) >> 8) & 0x3U) +#define PMCE_MSE_SOURCE(_pmce) (((_pmce) >> 16) & 0x1fU) +#define PMCE_PSE_SOURCE(_pmce) (((_pmce) >> 24) & 0x1fU) + +/* + * Peripheral IRQ handlers related definitions + */ +#define BSP_PER_IRQ_NUMBER 22 +#define BSP_PER_IRQ_LOWEST_OFFSET 0 +#define BSP_PER_IRQ_MAX_OFFSET \ + (BSP_PER_IRQ_LOWEST_OFFSET + BSP_PER_IRQ_NUMBER - 1) /* 21 */ +/* + * Main IRQ handlers related definitions + */ +#define BSP_MAIN_IRQ_NUMBER 17 +#define BSP_MAIN_IRQ_LOWEST_OFFSET BSP_PER_IRQ_MAX_OFFSET + 1 /* 22 */ +#define BSP_MAIN_IRQ_MAX_OFFSET \ + (BSP_MAIN_IRQ_LOWEST_OFFSET + BSP_MAIN_IRQ_NUMBER - 1) /* 38 */ +/* + * Critical IRQ handlers related definitions + */ +#define BSP_CRIT_IRQ_NUMBER 4 +#define BSP_CRIT_IRQ_LOWEST_OFFSET BSP_MAIN_IRQ_MAX_OFFSET + 1 /* 39 */ +#define BSP_CRIT_IRQ_MAX_OFFSET \ + (BSP_CRIT_IRQ_LOWEST_OFFSET + BSP_CRIT_IRQ_NUMBER - 1) /* 42 */ +/* + * Summary of SIU interrupts + */ +#define BSP_SIU_IRQ_NUMBER BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 43 */ +#define BSP_SIU_IRQ_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */ +#define BSP_SIU_IRQ_MAX_OFFSET BSP_CRIT_IRQ_MAX_OFFSET /* 42 */ +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 3 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 44 */ +#define BSP_PROCESSOR_IRQ_MAX_OFFSET \ + (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) /* 46 */ +/* + * Summary + */ +#define BSP_IRQ_NUMBER BSP_PROCESSOR_IRQ_MAX_OFFSET + 1 /* 47 */ +#define BSP_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */ +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET /* 46 */ + +#ifndef ASM + +#include +#include +#include + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ +typedef enum { + BSP_SIU_IRQ_SMARTCOMM = BSP_PER_IRQ_LOWEST_OFFSET + 0, + BSP_SIU_IRQ_PSC1 = BSP_PER_IRQ_LOWEST_OFFSET + 1, + BSP_SIU_IRQ_PSC2 = BSP_PER_IRQ_LOWEST_OFFSET + 2, + BSP_SIU_IRQ_PSC3 = BSP_PER_IRQ_LOWEST_OFFSET + 3, + BSP_SIU_IRQ_PSC6 = BSP_PER_IRQ_LOWEST_OFFSET + 4, + BSP_SIU_IRQ_ETH = BSP_PER_IRQ_LOWEST_OFFSET + 5, + BSP_SIU_IRQ_USB = BSP_PER_IRQ_LOWEST_OFFSET + 6, + BSP_SIU_IRQ_ATA = BSP_PER_IRQ_LOWEST_OFFSET + 7, + BSP_SIU_IRQ_PCI_CRT = BSP_PER_IRQ_LOWEST_OFFSET + 8, + BSP_SIU_IRQ_PCI_SC_RX = BSP_PER_IRQ_LOWEST_OFFSET + 9, + BSP_SIU_IRQ_PCI_SC_TX = BSP_PER_IRQ_LOWEST_OFFSET + 10, + BSP_SIU_IRQ_PSC4 = BSP_PER_IRQ_LOWEST_OFFSET + 11, + BSP_SIU_IRQ_PSC5 = BSP_PER_IRQ_LOWEST_OFFSET + 12, + BSP_SIU_IRQ_SPI_MODF = BSP_PER_IRQ_LOWEST_OFFSET + 13, + BSP_SIU_IRQ_SPI_SPIF = BSP_PER_IRQ_LOWEST_OFFSET + 14, + BSP_SIU_IRQ_I2C1 = BSP_PER_IRQ_LOWEST_OFFSET + 15, + BSP_SIU_IRQ_I2C2 = BSP_PER_IRQ_LOWEST_OFFSET + 16, + BSP_SIU_IRQ_MSCAN1 = BSP_PER_IRQ_LOWEST_OFFSET + 17, + BSP_SIU_IRQ_MSCAN2 = BSP_PER_IRQ_LOWEST_OFFSET + 18, + BSP_SIU_IRQ_IR_RX = BSP_PER_IRQ_LOWEST_OFFSET + 19, + BSP_SIU_IRQ_IR_TX = BSP_PER_IRQ_LOWEST_OFFSET + 20, + BSP_SIU_IRQ_XLB_ARB = BSP_PER_IRQ_LOWEST_OFFSET + 21, + + /* SL_TIMER1 -- handler entry only used in case of SMI */ + BSP_SIU_IRQ_SL_TIMER1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 0, + BSP_SIU_IRQ_IRQ1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1, + BSP_SIU_IRQ_IRQ2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 2, + BSP_SIU_IRQ_IRQ3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 3, + /* LO_INT -- handler entry never used (only placeholder) */ + BSP_SIU_IRQ_LO_INT = BSP_MAIN_IRQ_LOWEST_OFFSET + 4, + BSP_SIU_IRQ_RTC_PER = BSP_MAIN_IRQ_LOWEST_OFFSET + 5, + BSP_SIU_IRQ_RTC_STW = BSP_MAIN_IRQ_LOWEST_OFFSET + 6, + BSP_SIU_IRQ_GPIO_STD = BSP_MAIN_IRQ_LOWEST_OFFSET + 7, + BSP_SIU_IRQ_GPIO_WKUP = BSP_MAIN_IRQ_LOWEST_OFFSET + 8, + BSP_SIU_IRQ_TMR0 = BSP_MAIN_IRQ_LOWEST_OFFSET + 9, + BSP_SIU_IRQ_TMR1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 10, + BSP_SIU_IRQ_TMR2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1, + BSP_SIU_IRQ_TMR3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 12, + BSP_SIU_IRQ_TMR4 = BSP_MAIN_IRQ_LOWEST_OFFSET + 13, + BSP_SIU_IRQ_TMR5 = BSP_MAIN_IRQ_LOWEST_OFFSET + 14, + BSP_SIU_IRQ_TMR6 = BSP_MAIN_IRQ_LOWEST_OFFSET + 15, + BSP_SIU_IRQ_TMR7 = BSP_MAIN_IRQ_LOWEST_OFFSET + 16, + + BSP_SIU_IRQ_IRQ0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 0, + BSP_SIU_IRQ_SL_TIMER0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 1, + /* HI_INT -- handler entry never used (only placeholder) */ + BSP_SIU_IRQ_HI_INT = BSP_CRIT_IRQ_LOWEST_OFFSET + 2, + BSP_SIU_IRQ_CSS_WKUP = BSP_CRIT_IRQ_LOWEST_OFFSET + 3, + + BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, + BSP_SYSMGMT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, + BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 +} rtems_irq_symbolic_name; + +#define BSP_CRIT_IRQ_PRIO_LEVELS 4 +#define BSP_PERIODIC_TIMER BSP_SIU_IRQ_TMR6 + +#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET + +#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET + +#endif + +#endif /* LIBBSP_POWERPC_GEN5200_IRQ_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/mpc5200.h b/bsps/powerpc/gen5200/include/bsp/mpc5200.h new file mode 100644 index 0000000000..263e66fb9e --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/mpc5200.h @@ -0,0 +1,1369 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2005 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains definitions for the mpc5200 hw registers | +\*===============================================================*/ + +#ifndef __MPC5200_h__ +#define __MPC5200_h__ + +/* Additional Harpo Core SPR definitions (603le only) */ +#define CSRR0 58 /* Critical Interrupt SRR0 */ +#define CSRR1 59 /* Critical Interrupt SRR1 */ +#define DABR2 1000 /* Data Address Breakpoint #2 */ +#define DBCR 1001 /* Data Address Breakpoint Control */ +#define IBCR 1002 /* Instruction Breakpoint Control */ +#define IABR2 1018 /* Instruction Breakpoint #2 */ + +/* + * Initial post-reset location of MGT5100 module base address register (MBAR) + */ +#define MBAR_RESET 0x80000000 + +/* + * Location and size of onchip SRAM (relative to MBAR) + */ +#define ONCHIP_SRAM_OFFSET 0x8000 +#define ONCHIP_SRAM_SIZE 0x4000 + +#ifndef ASM +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define MPC5200_CAN_NO 2 +#define MPC5200_PSC_NO 6 + /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap + * from PSC5, therefore we instantiate seven(!) PSC register sets + */ +#define MPC5200_PSC_REG_SETS 7 + +#define MPC5200_GPT_NO 8 +#define MPC5200_SLT_NO 2 + +/* + * Bit fields for FEC interrupts, ievent and imask above. + */ +#define FEC_INTR_HBERR 0x80000000 /* heartbeat error */ +#define FEC_INTR_BABR 0x40000000 /* babbling receive error */ +#define FEC_INTR_BABT 0x20000000 /* babbling transmit error */ +#define FEC_INTR_GRA 0x10000000 /* graceful stop complete */ +#define FEC_INTR_TFINT 0x08000000 /* transmit frame interrupt */ +/* 0x04000000 reserved */ +/* 0x02000000 reserved */ +/* 0x01000000 reserved */ +#define FEC_INTR_MII 0x00800000 /* MII interrupt */ +/* 0x00400000 reserved */ +#define FEC_INTR_LATE_COL 0x00200000 /* late collision */ +#define FEC_INTR_COL_RETRY 0x00100000 /* collision retry limit */ +#define FEC_INTR_XFIFO_UN 0x00080000 /* transmit FIFO error */ +#define FEC_INTR_XFIFO_ERR 0x00040000 /* transmit FIFO error */ +#define FEC_INTR_RFIFO_ERR 0x00020000 /* receive FIFO error */ +/* 0x00010000 reserved */ +/* 0x0000ffff reserved */ +#define FEC_INTR_HBEEN FEC_INTR_HBERR +#define FEC_INTR_BREN FEC_INTR_BABR +#define FEC_INTR_BTEN FEC_INTR_BABT +#define FEC_INTR_GRAEN FEC_INTR_GRA +#define FEC_INTR_TFINTEN FEC_INTR_TFINT +#define FEC_INTR_MIIEN FEC_INTR_MII +#define FEC_INTR_LCEN FEC_INTR_LATE_COL +#define FEC_INTR_CRLEN FEC_INTR_COL_RETRY +#define FEC_INTR_XFUNEN FEC_INTR_XFIFO_UN +#define FEC_INTR_XFERREN FEC_INTR_XFIFO_ERR +#define FEC_INTR_RFERREN FEC_INTR_RFIFO_ERR +#define FEC_INTR_CLEAR_ALL 0xffffffff /* clear all interrupt events */ +#define FEC_INTR_MASK_ALL 0x00000000 /* mask all interrupt events */ + +/* + * Bit fields for FEC ethernet control, ecntrl above. + */ +#define FEC_ECNTRL_TAG 0xf0000000 /* TBUS tag bits */ +/* 0x08000000 reserved */ +#define FEC_ECNTRL_TESTMD 0x04000000 /* test mode */ +/* 0x03fffff8 reserved */ +#define FEC_ECNTRL_OE 0x00000004 /* FEC output enable */ +#define FEC_ECNTRL_EN 0x00000002 /* ethernet enable */ +#define FEC_ECNTRL_RESET 0x00000001 /* ethernet controller reset */ + +/* + * Bit fields for FEC receive control, r_cntrl above. + */ +/* 0xf1000000 reserved */ +#define FEC_RCNTRL_MAX_FL 0x07ff0000 /* maximum frame length */ +#define FEC_RCNTRL_MAX_FL_SHIFT 16 +/* 0x0000ffc0 reserved */ +#define FEC_RCNTRL_FCE 0x00000020 /* flow control enable */ +#define FEC_RCNTRL_BC_REJ 0x00000010 /* broadcast frame reject */ +#define FEC_RCNTRL_PROM 0x00000008 /* promiscuous mode */ +#define FEC_RCNTRL_MII_MODE 0x00000004 /* select 18-wire (MII) mode */ +#define FEC_RCNTRL_DRT 0x00000002 /* disable receive on transmit */ +#define FEC_RCNTRL_LOOP 0x00000001 /* internal loopback */ + +/* + * Bit fields for FEC transmit control, x_cntrl above. + */ +/* 0xffffffe0 reserved */ +#define FEC_XCNTRL_RFC_PAUS 0x00000010 /* FDX flow control pause rx */ +#define FEC_XCNTRL_TFC_PAUS 0x00000008 /* assert a PAUSE frame */ +#define FEC_XCNTRL_FDEN 0x00000004 /* full duplex enable */ +#define FEC_XCNTRL_HBC 0x00000002 /* heartbeat control */ +#define FEC_XCNTRL_GTS 0x00000001 /* graceful transmit stop */ + +/* + * Bit fields for FEC transmit status, x_status above. + */ +/* 0xfc000000 reserved */ +#define FEC_XSTAT_DEF 0x02000000 /* defer */ +#define FEC_XSTAT_HB 0x01000000 /* heartbeat error */ +#define FEC_XSTAT_LC 0x00800000 /* late collision */ +#define FEC_XSTAT_RL 0x00400000 /* retry limit */ +#define FEC_XSTAT_RC 0x003c0000 /* retry count */ +#define FEC_XSTAT_UN 0x00020000 /* underrun */ +#define FEX_XSTAT_CSL 0x00010000 /* carrier sense lost */ +/* 0x0000ffff reserved */ + +/* + * Bit fields for FEC transmit FIFO watermark, x_wmrk above. + */ +#define FEC_XWMRK_64 0x00000000 /* 64 bytes written to TxFIFO */ +#define FEC_XWMRK_128 0x00000001 /* 128 bytes written to TxFIFO */ +#define FEC_XWMRK_192 0x00000002 /* 192 bytes written to TxFIFO */ +#define FEC_XWMRK_256 0x00000003 /* 256 bytes written to TxFIFO */ +#define FEC_XWMRK_320 0x00000004 /* 320 bytes written to TxFIFO */ +#define FEC_XWMRK_384 0x00000005 /* 384 bytes written to TxFIFO */ +#define FEC_XWMRK_448 0x00000006 /* 448 bytes written to TxFIFO */ +#define FEC_XWMRK_512 0x00000007 /* 512 bytes written to TxFIFO */ +#define FEC_XWMRK_576 0x00000008 /* 576 bytes written to TxFIFO */ +#define FEC_XWMRK_640 0x00000009 /* 640 bytes written to TxFIFO */ +#define FEC_XWMRK_704 0x0000000a /* 704 bytes written to TxFIFO */ +#define FEC_XWMRK_768 0x0000000b /* 768 bytes written to TxFIFO */ +#define FEC_XWMRK_832 0x0000000c /* 832 bytes written to TxFIFO */ +#define FEC_XWMRK_896 0x0000000d /* 896 bytes written to TxFIFO */ +#define FEC_XWMRK_960 0x0000000e /* 960 bytes written to TxFIFO */ +#define FEC_XWMRK_1024 0x0000000f /* 1024 bytes written to TxFIFO */ + +/* + * Bit fields for FEC transmit finite state machine. + */ +/* 0xfc000000 reserved */ +#define FEC_FSM_CRC 0x02000000 /* append CRC (typical use) */ +#define FEC_FSM_ENFSM 0x01000000 /* enable CRC FSM (typical use) */ +/* 0x00ffffff reserved */ + +/* + * Bit fields for FEC FIFOs, rfifo_status, rfifo_cntrl, tfifo_status + * and tfifo_cntrl. + */ +#define FEC_FIFO_STAT_IP 0x80000000 /* illegal pointer, sticky */ +/* 0x70000000 reserved */ +#define FEC_FIFO_STAT_FRAME 0x0f000000 /* frame indicator */ +#define FEC_FIFO_STAT_FAE 0x00800000 /* frame accept error */ +#define FEC_FIFO_STAT_RXW 0x00400000 /* receive wait condition */ +#define FEC_FIFO_STAT_UF 0x00200000 /* underflow */ +#define FEC_FIFO_STAT_OF 0x00100000 /* overflow */ +#define FEC_FIFO_STAT_FR 0x00080000 /* frame ready, read-only */ +#define FEC_FIFO_STAT_FULL 0x00040000 /* full alarm, read-only */ +#define FEC_FIFO_STAT_ALARM 0x00020000 /* fifo alarm */ +#define FEC_FIFO_STAT_EMPTY 0x00010000 /* empty, read-only */ +/* 0x0000ffff reserved */ +#define FEC_FIFO_STAT_ERROR ( FEC_FIFO_STAT_IP \ + | FEC_FIFO_STAT_FAE \ + | FEC_FIFO_STAT_RXW \ + | FEC_FIFO_STAT_UF \ + | FEC_FIFO_STAT_OF \ + ) + +/* 0x80000000 reserved */ +#define FEC_FIFO_CNTRL_WCTL 0x40000000 /* write control */ +#define FEC_FIFO_CNTRL_WFR 0x20000000 /* write frame */ +/* 0x10000000 reserved */ +#define FEC_FIFO_CNTRL_FRAME 0x08000000 /* frame mode enable */ +#define FEC_FIFO_CNTRL_GR 0x07000000 /* last transfer granularity */ +#define FEC_FIFO_CNTRL_GR_SHIFT 24 +#define FEC_FIFO_CNTRL_IP_MASK 0x00800000 /* illegal pointer mask */ +#define FEC_FIFO_CNTRL_FAE_MASK 0x00400000 /* frame accept mask */ +#define FEC_FIFO_CNTRL_RXW_MASK 0x00200000 /* receive wait mask */ +#define FEC_FIFO_CNTRL_UF_MASK 0x00100000 /* underflow mask */ +#define FEC_FIFO_CNTRL_OF_MASK 0x00080000 /* overflow mask */ +/* 0x0007ffff reserved */ + +#define SDMA_TCR_EN BSP_BBIT16(0) +#define SDMA_TCR_VAL BSP_BBIT16(1) +#define SDMA_TCR_ALW_INIT BSP_BBIT16(2) +#define SDMA_TCR_IN(val) BSP_BFLD16(val, 3, 7) +#define SDMA_TCR_AUTO_START BSP_BBIT16(8) +#define SDMA_TCR_HIGH_EN BSP_BBIT16(9) +#define SDMA_TCR_HOLD BSP_BBIT16(10) +#define SDMA_TCR_AS(val) BSP_BFLD16(val, 12, 15) + +#define SDMA_IPR_HOLD BSP_BBIT8(0) +#define SDMA_IPR_PRIOR(val) BSP_BFLD8(val, 5, 7) + +#define SDMA_REQMUX_SET_31(reg, val) BSP_BFLD32SET(reg, val, 0, 1) +#define SDMA_REQMUX_SET_30(reg, val) BSP_BFLD32SET(reg, val, 2, 3) +#define SDMA_REQMUX_SET_29(reg, val) BSP_BFLD32SET(reg, val, 4, 5) +#define SDMA_REQMUX_SET_28(reg, val) BSP_BFLD32SET(reg, val, 6, 7) +#define SDMA_REQMUX_SET_27(reg, val) BSP_BFLD32SET(reg, val, 8, 9) +#define SDMA_REQMUX_SET_26(reg, val) BSP_BFLD32SET(reg, val, 10, 11) +#define SDMA_REQMUX_SET_25(reg, val) BSP_BFLD32SET(reg, val, 12, 13) +#define SDMA_REQMUX_SET_24(reg, val) BSP_BFLD32SET(reg, val, 14, 15) +#define SDMA_REQMUX_SET_23(reg, val) BSP_BFLD32SET(reg, val, 16, 17) +#define SDMA_REQMUX_SET_22(reg, val) BSP_BFLD32SET(reg, val, 18, 19) +#define SDMA_REQMUX_SET_21(reg, val) BSP_BFLD32SET(reg, val, 20, 21) +#define SDMA_REQMUX_SET_20(reg, val) BSP_BFLD32SET(reg, val, 22, 23) +#define SDMA_REQMUX_SET_19(reg, val) BSP_BFLD32SET(reg, val, 24, 25) +#define SDMA_REQMUX_SET_18(reg, val) BSP_BFLD32SET(reg, val, 26, 27) +#define SDMA_REQMUX_SET_17(reg, val) BSP_BFLD32SET(reg, val, 28, 29) +#define SDMA_REQMUX_SET_16(reg, val) BSP_BFLD32SET(reg, val, 30, 31) + +/* SDMA / BestComm */ +typedef struct { + uint32_t taskBar; + uint32_t currentPointer; + uint32_t endPointer; + uint32_t variablePointer; + uint8_t IntVect1; + uint8_t IntVect2; + uint16_t PtdCntrl; + uint32_t IntPend; + uint32_t IntMask; + uint16_t tcr [16]; + uint8_t ipr [32]; + uint32_t cReqSelect; + uint32_t task_size0; + uint32_t task_size1; + uint32_t reserved_0; + uint32_t reserved_1; + uint32_t Value1; + uint32_t Value2; + uint32_t Control; + uint32_t Status; +} mpc5200_sdma; + +typedef struct { +#define CSC_CFG_WAITP(val) BSP_BFLD32(val, 0, 7) +#define CSC_CFG_WAITX(val) BSP_BFLD32(val, 8, 15) +#define CSC_CFG_MX BSP_BBIT32(16) +#define CSC_CFG_AA BSP_BBIT32(18) +#define CSC_CFG_CE BSP_BBIT32(19) +#define CSC_CFG_AS(val) BSP_BFLD32(val, 20, 21) +#define CSC_CFG_DS(val) BSP_BFLD32(val, 22, 23) +#define CSC_CFG_BANK(val) BSP_BFLD32(val, 24, 25) +#define CSC_CFG_WTYP(val) BSP_BFLD32(val, 26, 27) +#define CSC_CFG_WS BSP_BBIT32(28) +#define CSC_CFG_RS BSP_BBIT32(29) +#define CSC_CFG_WO BSP_BBIT32(30) +#define CSC_CFG_RO BSP_BBIT32(31) + uint32_t config_0; + uint32_t config_1; + uint32_t config_2; + uint32_t config_3; + uint32_t config_4; + uint32_t config_5; + +#define CSC_CTRL_ME BSP_BBIT32(7) + uint32_t control; + +#define CSC_STAT_WOERR BSP_BBIT32(2) +#define CSC_STAT_ROERR BSP_BBIT32(3) +#define CSC_STAT_GET_CSXERR(reg) BSP_BFLD32GET(reg, 5, 7) + uint32_t status; + + uint32_t config_6; + uint32_t config_7; + +#define CSC_BST_CTRL_CW7 BSP_BBIT32(0) +#define CSC_BST_CTRL_SLB7 BSP_BBIT32(1) +#define CSC_BST_CTRL_BRE7 BSP_BBIT32(3) +#define CSC_BST_CTRL_CW6 BSP_BBIT32(4) +#define CSC_BST_CTRL_SLB6 BSP_BBIT32(5) +#define CSC_BST_CTRL_BRE6 BSP_BBIT32(7) +#define CSC_BST_CTRL_CW5 BSP_BBIT32(8) +#define CSC_BST_CTRL_SLB5 BSP_BBIT32(9) +#define CSC_BST_CTRL_BRE5 BSP_BBIT32(11) +#define CSC_BST_CTRL_CW4 BSP_BBIT32(12) +#define CSC_BST_CTRL_SLB4 BSP_BBIT32(13) +#define CSC_BST_CTRL_BRE4 BSP_BBIT32(15) +#define CSC_BST_CTRL_CW3 BSP_BBIT32(16) +#define CSC_BST_CTRL_SLB3 BSP_BBIT32(17) +#define CSC_BST_CTRL_BRE3 BSP_BBIT32(19) +#define CSC_BST_CTRL_CW2 BSP_BBIT32(20) +#define CSC_BST_CTRL_SLB2 BSP_BBIT32(21) +#define CSC_BST_CTRL_BRE2 BSP_BBIT32(23) +#define CSC_BST_CTRL_CW1 BSP_BBIT32(24) +#define CSC_BST_CTRL_SLB1 BSP_BBIT32(25) +#define CSC_BST_CTRL_BRE1 BSP_BBIT32(27) +#define CSC_BST_CTRL_CW0 BSP_BBIT32(28) +#define CSC_BST_CTRL_SLB0 BSP_BBIT32(29) +#define CSC_BST_CTRL_BRE0 BSP_BBIT32(31) + uint32_t burst_control; + +#define CSC_DCYC_CTRL_DC7(val) BSP_BFLD32(val, 2, 3) +#define CSC_DCYC_CTRL_SET_DC7(reg, val) BSP_BFLD32SET(reg, val, 2, 3) +#define CSC_DCYC_CTRL_DC6(val) BSP_BFLD32(val, 6, 7) +#define CSC_DCYC_CTRL_SET_DC6(reg, val) BSP_BFLD32SET(reg, val, 6, 7) +#define CSC_DCYC_CTRL_DC5(val) BSP_BFLD32(val, 10, 11) +#define CSC_DCYC_CTRL_SET_DC5(reg, val) BSP_BFLD32SET(reg, val, 10, 11) +#define CSC_DCYC_CTRL_DC4(val) BSP_BFLD32(val, 14, 15) +#define CSC_DCYC_CTRL_SET_DC4(reg, val) BSP_BFLD32SET(reg, val, 14, 15) +#define CSC_DCYC_CTRL_DC3(val) BSP_BFLD32(val, 18, 19) +#define CSC_DCYC_CTRL_SET_DC3(reg, val) BSP_BFLD32SET(reg, val, 18, 19) +#define CSC_DCYC_CTRL_DC2(val) BSP_BFLD32(val, 22, 23) +#define CSC_DCYC_CTRL_SET_DC2(reg, val) BSP_BFLD32SET(reg, val, 22, 23) +#define CSC_DCYC_CTRL_DC1(val) BSP_BFLD32(val, 26, 27) +#define CSC_DCYC_CTRL_SET_DC1(reg, val) BSP_BFLD32SET(reg, val, 26, 27) +#define CSC_DCYC_CTRL_DC0(val) BSP_BFLD32(val, 30, 31) +#define CSC_DCYC_CTRL_SET_DC0(reg, val) BSP_BFLD32SET(reg, val, 30, 31) + uint32_t deadcycle_control; + + uint8_t reserved [208]; +} mpc5200_csc; + +typedef struct { + uint32_t memory_address_base; + uint32_t cs0_start_address; + uint32_t cs0_stop_address; + uint32_t cs1_start_address; + uint32_t cs1_stop_address; + uint32_t cs2_start_address; + uint32_t cs2_stop_address; + uint32_t cs3_start_address; + uint32_t cs3_stop_address; + uint32_t cs4_start_address; + uint32_t cs4_stop_address; + uint32_t cs5_start_address; + uint32_t cs5_stop_address; + uint32_t sdram_chip_select_0; + uint32_t sdram_chip_select_1; + uint8_t reserved_0 [16]; + uint32_t boot_start_address; + uint32_t boot_stop_address; + +#define MM_IPBI_CTRL_CS7ENA BSP_BBIT16(4) +#define MM_IPBI_CTRL_CS6ENA BSP_BBIT16(5) +#define MM_IPBI_CTRL_BOOTENA BSP_BBIT16(6) +#define MM_IPBI_CTRL_CS5ENA BSP_BBIT16(10) +#define MM_IPBI_CTRL_CS4ENA BSP_BBIT16(11) +#define MM_IPBI_CTRL_CS3ENA BSP_BBIT16(12) +#define MM_IPBI_CTRL_CS2ENA BSP_BBIT16(13) +#define MM_IPBI_CTRL_CS1ENA BSP_BBIT16(14) +#define MM_IPBI_CTRL_CS0ENA BSP_BBIT16(15) + uint16_t ipbi_control; + + uint16_t wait_state_enable; + uint32_t cs6_start_address; + uint32_t cs6_stop_address; + uint32_t cs7_start_address; + uint32_t cs7_stop_address; + uint8_t reserved_1 [152]; +} mpc5200_mm; + +/* +************************************************************************* +* MPC5x00 internal register memory map * +************************************************************************* +*/ +typedef struct mpc5200_ { + /* + * memory map registers (MBAR + 0) + */ + volatile mpc5200_mm mm; + + /* + * SDRAM memory controller registers (MBAR + 0x100) + */ + volatile uint8_t mc[0x100]; + + /* + * clock distribution module registers (MBAR + 0x200) + */ + volatile uint8_t cdm[0x100]; + + /* + * chip selct controller registers(MBAR + 0x300) + */ + volatile mpc5200_csc csc; + + /* + * SmartComm timer registers (MBAR + 0x400) + */ + volatile uint8_t sct[0x100]; + + /* + * interrupt controller registers (MBAR + 0x500) + */ + volatile uint32_t per_mask; /* + 0x00 */ + volatile uint32_t per_pri_1; /* + 0x04 */ + volatile uint32_t per_pri_2; /* + 0x08 */ + volatile uint32_t per_pri_3; /* + 0x0C */ + +#define ICTL_EET_ECLR0 BSP_BBIT32(4) +#define ICTL_EET_ECLR1 BSP_BBIT32(5) +#define ICTL_EET_ECLR2 BSP_BBIT32(6) +#define ICTL_EET_ECLR3 BSP_BBIT32(7) +#define ICTL_EET_ETYPE0(val) BSP_BFLD32(val, 8, 9) +#define ICTL_EET_ETYPE1(val) BSP_BFLD32(val, 10, 11) +#define ICTL_EET_ETYPE2(val) BSP_BFLD32(val, 12, 13) +#define ICTL_EET_ETYPE3(val) BSP_BFLD32(val, 14, 15) +#define ICTL_EET_SET_ETYPE0(reg, val) BSP_BFLD32SET(reg, val, 8, 9) +#define ICTL_EET_SET_ETYPE1(reg, val) BSP_BFLD32SET(reg, val, 10, 11) +#define ICTL_EET_SET_ETYPE2(reg, val) BSP_BFLD32SET(reg, val, 12, 13) +#define ICTL_EET_SET_ETYPE3(reg, val) BSP_BFLD32SET(reg, val, 14, 15) +#define ICTL_EET_MEE BSP_BBIT32(19) +#define ICTL_EET_EENA0 BSP_BBIT32(20) +#define ICTL_EET_EENA1 BSP_BBIT32(21) +#define ICTL_EET_EENA2 BSP_BBIT32(22) +#define ICTL_EET_EENA3 BSP_BBIT32(23) +#define ICTL_EET_CEB BSP_BBIT32(31) + + volatile uint32_t ext_en_type; /* + 0x10 */ + volatile uint32_t crit_pri_main_mask;/* + 0x14 */ + volatile uint32_t main_pri_1; /* + 0x18 */ + volatile uint32_t main_pri_2; /* + 0x1C */ + volatile uint32_t res1; /* + 0x20 */ + volatile uint32_t pmce; /* + 0x24 */ + volatile uint32_t csa; /* + 0x28 */ + volatile uint32_t msa; /* + 0x2C */ + volatile uint32_t psa; /* + 0x30 */ + volatile uint32_t res2; /* + 0x34 */ + volatile uint32_t psa_be; /* + 0x38 */ + volatile uint8_t res3[0xC4]; /* + 0x3C */ + + /* + * general pupose timer registers (MBAR + 0x600/+ 0x610/+ 0x620/+ 0x630/+ 0x640/+ 0x650/+ 0x660/+ 0x670) + */ + struct mpc5200_gpt { + volatile uint32_t emsel; /* + 0x00 */ + volatile uint32_t count_in; /* + 0x04 */ + volatile uint32_t pwm_conf; /* + 0x08 */ + volatile uint32_t status; /* + 0x0C */ + } gpt[MPC5200_GPT_NO]; + +#define GPT_STATUS_RESET 0x0000000F +#define GPT_STATUS_TEXP (1 << 3) +#define GPT_STATUS_PIN (1 << 8) +#define GPT_EMSEL_GPIO_DIR (2 << 4) +#define GPT_EMSEL_GPIO_OUT (1 << 4) +#define GPT_EMSEL_GPIO_OUT_HIGH (3 << 4) +#define GPT_EMSEL_TIMER_MS_GPIO (4 << 0) +#define GPT_EMSEL_GPIO_IN (0 << 0) +#define GPT_EMSEL_CE (1 << 12) +#define GPT_EMSEL_ST_CONT (1 << 10) +#define GPT_EMSEL_INTEN (1 << 8) +#define GPT_EMSEL_WDEN (1 << 15) + +#define GPT0 0 +#define GPT1 1 +#define GPT2 2 +#define GPT3 3 +#define GPT4 4 +#define GPT5 5 +#define GPT6 6 +#define GPT7 7 + + volatile uint8_t gpt_res[0x80]; + + /* + * slice time registers (MBAR + 0x700/+ 0x710) + */ + struct mpc5200_slt { + volatile uint32_t tcr; /* + 0x00 */ + volatile uint32_t cntrl; /* + 0x04 */ + volatile uint32_t cvr; /* + 0x08 */ + volatile uint32_t tsr; /* + 0x0C */ + } slt[MPC5200_SLT_NO]; + + volatile uint8_t slt_res[0xE0]; + + /* + * real time clock registers (MBAR + 0x800) + */ + volatile uint8_t rtc[0x100]; + + + /* + * MSCAN registers (MBAR + 0x900 /+ 0x980) + */ + struct mpc5200_mscan { + volatile uint8_t ctl0; /* + 0x0 */ + volatile uint8_t ctl1; /* + 0x1 */ + volatile uint8_t res1; /* + 0x2 */ + volatile uint8_t res2; /* + 0x3 */ + volatile uint8_t btr0; /* + 0x4 */ + volatile uint8_t btr1; /* + 0x5 */ + volatile uint8_t res3; /* + 0x6 */ + volatile uint8_t res4; /* + 0x7 */ + volatile uint8_t rflg; /* + 0x8 */ + volatile uint8_t rier; /* + 0x9 */ + volatile uint8_t res5; /* + 0xA */ + volatile uint8_t res6; /* + 0xB */ + volatile uint8_t tflg; /* + 0xC */ + volatile uint8_t tier; /* + 0xD */ + volatile uint8_t res7; /* + 0xE */ + volatile uint8_t res8; /* + 0xF */ + volatile uint8_t tarq; /* + 0x10 */ + volatile uint8_t taak; /* + 0x11 */ + volatile uint8_t res9; /* + 0x12 */ + volatile uint8_t res10; /* + 0x13 */ + volatile uint8_t bsel; /* + 0x14 */ + volatile uint8_t idac; /* + 0x15 */ + volatile uint8_t res11; /* + 0x16 */ + volatile uint8_t res12; /* + 0x17 */ + volatile uint8_t res13; /* + 0x18 */ + volatile uint8_t res14; /* + 0x19 */ + volatile uint8_t res15; /* + 0x1A */ + volatile uint8_t res16; /* + 0x1B */ + volatile uint8_t rxerr; /* + 0x1C */ + volatile uint8_t txerr; /* + 0x1D */ + volatile uint8_t res17; /* + 0x1E */ + volatile uint8_t res18; /* + 0x1F */ + volatile uint8_t idar0; /* + 0x20 */ + volatile uint8_t idar1; /* + 0x21 */ + volatile uint8_t res19; /* + 0x22 */ + volatile uint8_t res20; /* + 0x23 */ + volatile uint8_t idar2; /* + 0x24 */ + volatile uint8_t idar3; /* + 0x25 */ + volatile uint8_t res21; /* + 0x26 */ + volatile uint8_t res22; /* + 0x27 */ + volatile uint8_t idmr0; /* + 0x28 */ + volatile uint8_t idmr1; /* + 0x29 */ + volatile uint8_t res23; /* + 0x2A */ + volatile uint8_t res24; /* + 0x2B */ + volatile uint8_t idmr2; /* + 0x2C */ + volatile uint8_t idmr3; /* + 0x2D */ + volatile uint8_t res25; /* + 0x2E */ + volatile uint8_t res26; /* + 0x2F */ + volatile uint8_t idar4; /* + 0x30 */ + volatile uint8_t idar5; /* + 0x31 */ + volatile uint8_t res27; /* + 0x32 */ + volatile uint8_t res28; /* + 0x33 */ + volatile uint8_t idar6; /* + 0x34 */ + volatile uint8_t idar7; /* + 0x35 */ + volatile uint8_t res29; /* + 0x36 */ + volatile uint8_t res30; /* + 0x37 */ + volatile uint8_t idmr4; /* + 0x38 */ + volatile uint8_t idmr5; /* + 0x39 */ + volatile uint8_t res31; /* + 0x3A */ + volatile uint8_t res32; /* + 0x3B */ + volatile uint8_t idmr6; /* + 0x3C */ + volatile uint8_t idmr7; /* + 0x3D */ + volatile uint8_t res33; /* + 0x3E */ + volatile uint8_t res34; /* + 0x3F */ + volatile uint8_t rxidr0; /* + 0x40 */ + volatile uint8_t rxidr1; /* + 0x41 */ + volatile uint8_t res35; /* + 0x42 */ + volatile uint8_t res36; /* + 0x43 */ + volatile uint8_t rxidr2; /* + 0x44 */ + volatile uint8_t rxidr3; /* + 0x45 */ + volatile uint8_t res37; /* + 0x46 */ + volatile uint8_t res38; /* + 0x47 */ + volatile uint8_t rxdsr0; /* + 0x48 */ + volatile uint8_t rxdsr1; /* + 0x49 */ + volatile uint8_t res39; /* + 0x4A */ + volatile uint8_t res40; /* + 0x4B */ + volatile uint8_t rxdsr2; /* + 0x4C */ + volatile uint8_t rxdsr3; /* + 0x4D */ + volatile uint8_t res41; /* + 0x4E */ + volatile uint8_t res42; /* + 0x4F */ + volatile uint8_t rxdsr4; /* + 0x50 */ + volatile uint8_t rxdsr5; /* + 0x51 */ + volatile uint8_t res43; /* + 0x52 */ + volatile uint8_t res44; /* + 0x53 */ + volatile uint8_t rxdsr6; /* + 0x54 */ + volatile uint8_t rxdsr7; /* + 0x55 */ + volatile uint8_t res45; /* + 0x56 */ + volatile uint8_t res46; /* + 0x57 */ + volatile uint8_t rxdlr; /* + 0x58 */ + volatile uint8_t res47; /* + 0x59 */ + volatile uint8_t res48; /* + 0x5A */ + volatile uint8_t res49; /* + 0x5B */ + volatile uint8_t rxtimh; /* + 0x5C */ + volatile uint8_t rxtiml; /* + 0x5D */ + volatile uint8_t res50; /* + 0x5E */ + volatile uint8_t res51; /* + 0x5F */ + volatile uint8_t txidr0; /* + 0x60 */ + volatile uint8_t txidr1; /* + 0x61 */ + volatile uint8_t res52; /* + 0x62 */ + volatile uint8_t res53; /* + 0x63 */ + volatile uint8_t txidr2; /* + 0x64 */ + volatile uint8_t txidr3; /* + 0x65 */ + volatile uint8_t res54; /* + 0x66 */ + volatile uint8_t res55; /* + 0x67 */ + volatile uint8_t txdsr0; /* + 0x68 */ + volatile uint8_t txdsr1; /* + 0x69 */ + volatile uint8_t res56; /* + 0x6A */ + volatile uint8_t res57; /* + 0x6B */ + volatile uint8_t txdsr2; /* + 0x6C */ + volatile uint8_t txdsr3; /* + 0x6D */ + volatile uint8_t res58; /* + 0x6E */ + volatile uint8_t res59; /* + 0x6F */ + volatile uint8_t txdsr4; /* + 0x70 */ + volatile uint8_t txdsr5; /* + 0x71 */ + volatile uint8_t res60; /* + 0x72 */ + volatile uint8_t res61; /* + 0x73 */ + volatile uint8_t txdsr6; /* + 0x74 */ + volatile uint8_t txdsr7; /* + 0x75 */ + volatile uint8_t res62; /* + 0x76 */ + volatile uint8_t res63; /* + 0x77 */ + volatile uint8_t txdlr; /* + 0x78 */ + volatile uint8_t txtbpr; /* + 0x79 */ + volatile uint8_t res64; /* + 0x7A */ + volatile uint8_t res65; /* + 0x7B */ + volatile uint8_t txtimh; /* + 0x7C */ + volatile uint8_t txtiml; /* + 0x7D */ + volatile uint8_t res66; /* + 0x7E */ + volatile uint8_t res67; /* + 0x7F */ + } mscan[MPC5200_CAN_NO]; + + volatile uint8_t res[0x100]; + + /* + * GPIO standard registers (MBAR + 0xB00) + */ + volatile uint32_t gpiopcr; /* + 0x00 */ + #define GPIO_PCR_CHIP_SELECT_1 0x80000000 + #define GPIO_PCR_CHIP_ALTS 0x30000000 + #define GPIO_PCR_CHIP_ALTS_NONE 0x00000000 + #define GPIO_PCR_CHIP_ALTS_CAN 0x10000000 + #define GPIO_PCR_CHIP_ALTS_SPI 0x20000000 + #define GPIO_PCR_CHIP_ALTS_BOTH 0x30000000 + #define GPIO_PCR_CHIP_SELECT_7 0x08000000 + #define GPIO_PCR_CHIP_SELECT_6 0x04000000 + #define GPIO_PCR_CHIP_SELECT_ATA 0x03000000 + #define GPIO_PCR_CHIP_SELECT_IR_USB_CLK 0x00800000 + #define GPIO_PCR_IRDA 0x00700000 + #define GPIO_PCR_ETHERNET 0x000F0000 + #define GPIO_PCR_PCI_DIS 0x00008000 + #define GPIO_PCR_USB_SE 0x00004000 + #define GPIO_PCR_USB_GPIO 0x00003000 + #define GPIO_PCR_PSC3 0x00000F00 + #define GPIO_PCR_PSC2 0x00000070 + #define GPIO_PCR_PSC1 0x00000007 + + #define GPIO_S_PIN_IR_USB_CLK BSP_BBIT32(2) + #define GPIO_S_PIN_IRDA_TX BSP_BBIT32(3) + #define GPIO_S_PIN_ETH_11 BSP_BBIT32(4) + #define GPIO_S_PIN_ETH_10 BSP_BBIT32(5) + #define GPIO_S_PIN_ETH_9 BSP_BBIT32(6) + #define GPIO_S_PIN_ETH_8 BSP_BBIT32(7) + #define GPIO_S_PIN_USB1_8 BSP_BBIT32(12) + #define GPIO_S_PIN_USB1_7 BSP_BBIT32(13) + #define GPIO_S_PIN_USB1_6 BSP_BBIT32(14) + #define GPIO_S_PIN_USB1_0 BSP_BBIT32(15) + #define GPIO_S_PIN_PSC3_7 BSP_BBIT32(18) + #define GPIO_S_PIN_PSC3_6 BSP_BBIT32(19) + #define GPIO_S_PIN_PSC3_3 BSP_BBIT32(20) + #define GPIO_S_PIN_PSC3_2 BSP_BBIT32(21) + #define GPIO_S_PIN_PSC3_1 BSP_BBIT32(22) + #define GPIO_S_PIN_PSC3_0 BSP_BBIT32(23) + #define GPIO_S_PIN_PSC2_3 BSP_BBIT32(24) + #define GPIO_S_PIN_PSC2_2 BSP_BBIT32(25) + #define GPIO_S_PIN_PSC2_1 BSP_BBIT32(26) + #define GPIO_S_PIN_PSC2_0 BSP_BBIT32(27) + #define GPIO_S_PIN_PSC1_3 BSP_BBIT32(28) + #define GPIO_S_PIN_PSC1_2 BSP_BBIT32(29) + #define GPIO_S_PIN_PSC1_1 BSP_BBIT32(30) + #define GPIO_S_PIN_PSC1_0 BSP_BBIT32(31) + + volatile uint32_t gpiosen; /* + 0x04 */ + volatile uint32_t gpiosod; /* + 0x08 */ + volatile uint32_t gpiosdd; /* + 0x0C */ + volatile uint32_t gpiosdo; /* + 0x10 */ + volatile uint32_t gpiosdi; /* + 0x14 */ + + #define GPIO_O_PIN_ETH_7 BSP_BBIT32(0) + #define GPIO_O_PIN_ETH_6 BSP_BBIT32(1) + #define GPIO_O_PIN_ETH_5 BSP_BBIT32(2) + #define GPIO_O_PIN_ETH_4 BSP_BBIT32(3) + #define GPIO_O_PIN_ETH_3 BSP_BBIT32(4) + #define GPIO_O_PIN_ETH_2 BSP_BBIT32(5) + #define GPIO_O_PIN_ETH_1 BSP_BBIT32(6) + #define GPIO_O_PIN_ETH_0 BSP_BBIT32(7) + #define GPIO_O_PIN_I2C_3 BSP_BBIT32(13) + #define GPIO_O_PIN_I2C_0 BSP_BBIT32(14) + #define GPIO_O_PIN_I2C_1 BSP_BBIT32(15) + + volatile uint32_t gpiooe; /* + 0x18 */ + volatile uint32_t gpioodo; /* + 0x1C */ + + #define GPIO_I_PIN_ETH_16 BSP_BBIT32(0) + #define GPIO_I_PIN_ETH_15 BSP_BBIT32(1) + #define GPIO_I_PIN_ETH_14 BSP_BBIT32(2) + #define GPIO_I_PIN_ETH_13 BSP_BBIT32(3) + #define GPIO_I_PIN_USB1_9 BSP_BBIT32(4) + #define GPIO_I_PIN_PSC3_8 BSP_BBIT32(5) + #define GPIO_I_PIN_PSC3_5 BSP_BBIT32(6) + #define GPIO_I_PIN_PSC3_4 BSP_BBIT32(7) + + volatile uint32_t gpiosie; /* + 0x20 */ + #define GPIO_SIE_SINT_7_ETH_16_PIN 0x80000000 + #define GPIO_SIE_SINT_6_ETH_15_PIN 0x40000000 + #define GPIO_SIE_SINT_5_ETH_14_PIN 0x20000000 + #define GPIO_SIE_SINT_4_ETH_13_PIN 0x10000000 + #define GPIO_SIE_SINT_3_USB1_9_PIN 0x08000000 + #define GPIO_SIE_SINT_2_PSC3_8_PIN 0x04000000 + #define GPIO_SIE_SINT_1_PSC3_5_PIN 0x02000000 + #define GPIO_SIE_SINT_0_PSC3_4_PIN 0x01000000 + + volatile uint32_t gpiosiod; /* + 0x24 */ + + volatile uint32_t gpiosidd; /* + 0x28 */ + #define GPIO_SIDD_SINT_7_ETH_16_PIN 0x80000000 + #define GPIO_SIDD_SINT_6_ETH_15_PIN 0x40000000 + #define GPIO_SIDD_SINT_5_ETH_14_PIN 0x20000000 + #define GPIO_SIDD_SINT_4_ETH_13_PIN 0x10000000 + #define GPIO_SIDD_SINT_3_USB1_9_PIN 0x08000000 + #define GPIO_SIDD_SINT_2_PSC3_8_PIN 0x04000000 + #define GPIO_SIDD_SINT_1_PSC3_5_PIN 0x02000000 + #define GPIO_SIDD_SINT_0_PSC3_4_PIN 0x01000000 + + volatile uint32_t gpiosido; /* + 0x2C */ + + volatile uint32_t gpiosiie; /* + 0x30 */ + #define GPIO_SIIE_SINT_7_ETH_16_PIN 0x80000000 + #define GPIO_SIIE_SINT_6_ETH_15_PIN 0x40000000 + #define GPIO_SIIE_SINT_5_ETH_14_PIN 0x20000000 + #define GPIO_SIIE_SINT_4_ETH_13_PIN 0x10000000 + #define GPIO_SIIE_SINT_3_USB1_9_PIN 0x08000000 + #define GPIO_SIIE_SINT_2_PSC3_8_PIN 0x04000000 + #define GPIO_SIIE_SINT_1_PSC3_5_PIN 0x02000000 + #define GPIO_SIIE_SINT_0_PSC3_4_PIN 0x01000000 + + volatile uint32_t gpiosiit; /* + 0x34 */ + #define GPIO_SIIT_SET_ETH_16_PIN(reg, val) BSP_BFLD32SET(reg, val, 0, 1) + #define GPIO_SIIT_SET_ETH_15_PIN(reg, val) BSP_BFLD32SET(reg, val, 2, 3) + #define GPIO_SIIT_SET_ETH_14_PIN(reg, val) BSP_BFLD32SET(reg, val, 4, 5) + #define GPIO_SIIT_SET_ETH_13_PIN(reg, val) BSP_BFLD32SET(reg, val, 6, 7) + #define GPIO_SIIT_SET_USB1_9_PIN(reg, val) BSP_BFLD32SET(reg, val, 8, 9) + #define GPIO_SIIT_SET_PSC3_8_PIN(reg, val) BSP_BFLD32SET(reg, val, 10, 11) + #define GPIO_SIIT_SET_PSC3_5_PIN(reg, val) BSP_BFLD32SET(reg, val, 12, 13) + #define GPIO_SIIT_SET_PSC3_4_PIN(reg, val) BSP_BFLD32SET(reg, val, 14, 15) + + #define GPIO_SIIT_SINT_7_ETH_16_PIN_MASK 0xc0000000 + #define GPIO_SIIT_SINT_6_ETH_15_PIN_MASK 0x30000000 + #define GPIO_SIIT_SINT_5_ETH_14_PIN_MASK 0x0c000000 + #define GPIO_SIIT_SINT_4_ETH_13_PIN_MASK 0x03000000 + #define GPIO_SIIT_SINT_3_USB1_9_PIN_MASK 0x00c00000 + #define GPIO_SIIT_SINT_2_PSC3_8_PIN_MASK 0x00300000 + #define GPIO_SIIT_SINT_1_PSC3_5_PIN_MASK 0x000c0000 + #define GPIO_SIIT_SINT_0_PSC3_4_PIN_MASK 0x00030000 + + #define GPIO_SIIT_ON_ANY_TRANSITION 0x00000000 + #define GPIO_SIIT_ON_RISING_EDGE 0x00000001 + #define GPIO_SIIT_ON_FALLING_EDGE 0x00000002 + #define GPIO_SIIT_ON_PULSE 0x00000003 + + #define GPIO_SIIT_SINT_7_ETH_16_PIN_SHIFT 16 + #define GPIO_SIIT_SINT_6_ETH_15_PIN_SHIFT 18 + #define GPIO_SIIT_SINT_5_ETH_14_PIN_SHIFT 20 + #define GPIO_SIIT_SINT_4_ETH_13_PIN_SHIFT 22 + #define GPIO_SIIT_SINT_3_USB1_9_PIN_SHIFT 24 + #define GPIO_SIIT_SINT_2_PSC3_8_PIN_SHIFT 26 + #define GPIO_SIIT_SINT_1_PSC3_5_PIN_SHIFT 28 + #define GPIO_SIIT_SINT_0_PSC3_4_PIN_SHIFT 30 + + volatile uint32_t gpiosime; /* + 0x38 */ + #define GPIO_SIME_MASTER_ENABLE 0x10000000 + + volatile uint32_t gpiosist; /* + 0x3C */ + #define GPIO_SIST_SINT_7_ETH_16_PIN_STATUS 0x80000000 + #define GPIO_SIST_SINT_6_ETH_15_PIN_STATUS 0x40000000 + #define GPIO_SIST_SINT_5_ETH_14_PIN_STATUS 0x20000000 + #define GPIO_SIST_SINT_4_ETH_13_PIN_STATUS 0x10000000 + #define GPIO_SIST_SINT_3_USB1_9_PIN_STATUS 0x08000000 + #define GPIO_SIST_SINT_2_PSC3_8_PIN_STATUS 0x04000000 + #define GPIO_SIST_SINT_1_PSC3_5_PIN_STATUS 0x02000000 + #define GPIO_SIST_SINT_0_PSC3_4_PIN_STATUS 0x01000000 + #define GPIO_SIST_SINT_7_ETH_16_PIN_VALUE 0x00800000 + #define GPIO_SIST_SINT_6_ETH_15_PIN_VALUE 0x00400000 + #define GPIO_SIST_SINT_5_ETH_14_PIN_VALUE 0x00200000 + #define GPIO_SIST_SINT_4_ETH_13_PIN_VALUE 0x00100000 + #define GPIO_SIST_SINT_3_USB1_9_PIN_VALUE 0x00080000 + #define GPIO_SIST_SINT_2_PSC3_8_PIN_VALUE 0x00040000 + #define GPIO_SIST_SINT_1_PSC3_5_PIN_VALUE 0x00020000 + #define GPIO_SIST_SINT_0_PSC3_4_PIN_VALUE 0x00010000 + + #define GPIO_SIST_SINT_CLEAR_ALL 0xff000000 + + volatile uint8_t res4[0xC0]; + + /* + * GPIO wakeup registers (MBAR + 0xC00) + */ + + #define GPIO_W_PIN_GPIO_WKUP_7 BSP_BBIT32(0) + #define GPIO_W_PIN_GPIO_WKUP_6 BSP_BBIT32(1) + #define GPIO_W_PIN_PSC6_1 BSP_BBIT32(2) + #define GPIO_W_PIN_PSC6_0 BSP_BBIT32(3) + #define GPIO_W_PIN_ETH_17 BSP_BBIT32(4) + #define GPIO_W_PIN_PSC3_9 BSP_BBIT32(5) + #define GPIO_W_PIN_PSC2_4 BSP_BBIT32(6) + #define GPIO_W_PIN_PSC1_4 BSP_BBIT32(7) + + volatile uint32_t gpiowe; /* + 0x00 */ + volatile uint32_t gpiowod; /* + 0x04 */ + volatile uint32_t gpiowdd; /* + 0x08 */ + volatile uint32_t gpiowdo; /* + 0x0C */ + volatile uint32_t gpiowue; /* + 0x10 */ + volatile uint32_t gpiowsie; /* + 0x14 */ + volatile uint32_t gpiowt; /* + 0x18 */ + volatile uint32_t gpiowme; /* + 0x1C */ + volatile uint32_t gpiowi; /* + 0x20 */ + volatile uint32_t gpiows; /* + 0x24 */ + volatile uint8_t gpiow_res[0xD8]; + + /* + * PPC PCI registers (MBAR + 0xD00) + */ + volatile uint8_t ppci[0x100]; + + /* + * consumer infrared registers (MBAR + 0xE00) + */ + volatile uint8_t ir[0x100]; + + /* + * serial peripheral interface registers (MBAR + 0xF00) + */ + volatile uint8_t spi[0x100]; + + /* + * universal serial bus registers (MBAR + 0x1000) + */ + volatile uint8_t usb[0x200]; + + /* + * SmartComm DMA registers (MBAR + 0x1200) + */ + volatile mpc5200_sdma sdma; + + volatile uint32_t EU00; /* + 0x80 sdMac macer reg */ + volatile uint32_t EU01; /* + 0x84 sdMac macemr reg */ + volatile uint32_t EU02; /* + 0x88 unused */ + volatile uint32_t EU03; /* + 0x8c unused */ + volatile uint32_t EU04; /* + 0x90 unused */ + volatile uint32_t EU05; /* + 0x94 unused */ + volatile uint32_t EU06; /* + 0x98 unused */ + volatile uint32_t EU07; /* + 0x9c unused */ + volatile uint32_t EU10; /* + 0xa0 unused */ + volatile uint32_t EU11; /* + 0xa4 unused */ + volatile uint32_t EU12; /* + 0xa8 unused */ + volatile uint32_t EU13; /* + 0xac unused */ + volatile uint32_t EU14; /* + 0xb0 unused */ + volatile uint32_t EU15; /* + 0xb4 unused */ + volatile uint32_t EU16; /* + 0xb8 unused */ + volatile uint32_t EU17; /* + 0xbc unused */ + volatile uint32_t EU20; /* + 0xc0 unused */ + volatile uint32_t EU21; /* + 0xc4 unused */ + volatile uint32_t EU22; /* + 0xc8 unused */ + volatile uint32_t EU23; /* + 0xcc unused */ + volatile uint32_t EU24; /* + 0xd0 unused */ + volatile uint32_t EU25; /* + 0xd4 unused */ + volatile uint32_t EU26; /* + 0xd8 unused */ + volatile uint32_t EU27; /* + 0xdc unused */ + volatile uint32_t EU30; /* + 0xe0 unused */ + volatile uint32_t EU31; /* + 0xe4 unused */ + volatile uint32_t EU32; /* + 0xe8 unused */ + volatile uint32_t EU33; /* + 0xec unused */ + volatile uint32_t EU34; /* + 0xf0 unused */ + volatile uint32_t EU35; /* + 0xf4 unused */ + volatile uint32_t EU36; /* + 0xf8 unused */ + volatile uint32_t EU37; /* + 0xfc unused */ +#if 0 + volatile uint32_t res8[0x340]; +#else + volatile uint8_t res_1300[0xc00]; + + volatile uint32_t reserved0; /* MBAR_XLB_ARB + 0x0000 reserved */ + volatile uint32_t reserved1; /* MBAR_XLB_ARB + 0x0004 reserved */ + volatile uint32_t reserved2; /* MBAR_XLB_ARB + 0x0008 reserved */ + volatile uint32_t reserved3; /* MBAR_XLB_ARB + 0x000c reserved */ + volatile uint32_t reserved4; /* MBAR_XLB_ARB + 0x0010 reserved */ + volatile uint32_t reserved5; /* MBAR_XLB_ARB + 0x0014 reserved */ + volatile uint32_t reserved6; /* MBAR_XLB_ARB + 0x0018 reserved */ + volatile uint32_t reserved7; /* MBAR_XLB_ARB + 0x001c reserved */ + volatile uint32_t reserved8; /* MBAR_XLB_ARB + 0x0020 reserved */ + volatile uint32_t reserved9; /* MBAR_XLB_ARB + 0x0024 reserved */ + volatile uint32_t reserved10; /* MBAR_XLB_ARB + 0x0028 reserved */ + volatile uint32_t reserved11; /* MBAR_XLB_ARB + 0x002c reserved */ + volatile uint32_t reserved12; /* MBAR_XLB_ARB + 0x0030 reserved */ + volatile uint32_t reserved13; /* MBAR_XLB_ARB + 0x0034 reserved */ + volatile uint32_t reserved14; /* MBAR_XLB_ARB + 0x0038 reserved */ + volatile uint32_t reserved15; /* MBAR_XLB_ARB + 0x003c reserved */ + +#define XLB_CFG_PLDIS BSP_BBIT32(0) +#define XLB_CFG_BSDIS BSP_BBIT32(15) +#define XLB_CFG_SE BSP_BBIT32(16) +#define XLB_CFG_USE_WWF BSP_BBIT32(17) +#define XLB_CFG_TBEN BSP_BBIT32(18) +#define XLB_CFG_WS BSP_BBIT32(20) +#define XLB_CFG_SP(val) BSP_BFLD32(val, 21, 23) +#define XLB_CFG_SET_SP(reg, val) BSP_BFLD32SET(reg, val, 21, 23) +#define XLB_CFG_PM(val) BSP_BFLD32(val, 25, 26) +#define XLB_CFG_SET_PM(reg, val) BSP_BFLD32SET(reg, val, 25, 26) +#define XLB_CFG_BA BSP_BBIT32(28) +#define XLB_CFG_DT BSP_BBIT32(29) +#define XLB_CFG_AT BSP_BBIT32(30) + + volatile uint32_t config; /* MBAR_XLB_ARB + 0x0040 */ + volatile uint32_t version; /* MBAR_XLB_ARB + 0x0044 */ + +#define XLB_ST_SEA BSP_BBIT32(23) +#define XLB_ST_MM BSP_BBIT32(24) +#define XLB_ST_TTA BSP_BBIT32(25) +#define XLB_ST_TTR BSP_BBIT32(26) +#define XLB_ST_ECW BSP_BBIT32(27) +#define XLB_ST_TTM BSP_BBIT32(28) +#define XLB_ST_BA BSP_BBIT32(29) +#define XLB_ST_DT BSP_BBIT32(30) +#define XLB_ST_AT BSP_BBIT32(31) + /* read only = 0x0001 */ + volatile uint32_t xlb_status; /* MBAR_XLB_ARB + 0x0048 */ + volatile uint32_t int_enable; /* MBAR_XLB_ARB + 0x004c */ + volatile uint32_t add_capture; /* MBAR_XLB_ARB + 0x0050 read only */ + volatile uint32_t bus_sig_capture; /* MBAR_XLB_ARB + 0x0054 read only */ + volatile uint32_t add_time_out; /* MBAR_XLB_ARB + 0x0058 */ + volatile uint32_t data_time_out; /* MBAR_XLB_ARB + 0x005c */ + volatile uint32_t bus_time_out; /* MBAR_XLB_ARB + 0x0060 */ + volatile uint32_t priority_enable; /* MBAR_XLB_ARB + 0x0064 */ + volatile uint32_t priority; /* MBAR_XLB_ARB + 0x0068 */ + volatile uint32_t arb_base_addr2; /* MBAR_XLB_ARB + 0x006c */ + volatile uint32_t snoop_window; /* MBAR_XLB_ARB + 0x0070 */ + + volatile uint32_t reserved16; /* MBAR_XLB_ARB + 0x0074 reserved */ + volatile uint32_t reserved17; /* MBAR_XLB_ARB + 0x0078 reserved */ + volatile uint32_t reserved18; /* MBAR_XLB_ARB + 0x007c reserved */ + + volatile uint32_t control; /* MBAR_XLB_ARB + 0x0080 */ + volatile uint32_t init_total_count; /* MBAR_XLB_ARB + 0x0084 */ + volatile uint32_t int_total_count; /* MBAR_XLB_ARB + 0x0088 */ + + volatile uint32_t reserved19; /* MBAR_XLB_ARB + 0x008c reserved */ + + volatile uint32_t lower_address; /* MBAR_XLB_ARB + 0x0090 */ + volatile uint32_t higher_address; /* MBAR_XLB_ARB + 0x0094 */ + volatile uint32_t int_window_count; /* MBAR_XLB_ARB + 0x0098 */ + volatile uint32_t window_ter_count; /* MBAR_XLB_ARB + 0x009c */ + volatile uint8_t res_0x1fa0[0x60]; + + +#endif + /* + * programmable serial controller 1 (MBAR + 0x2000) + */ + + struct mpc5200_psc { + volatile uint8_t mr; /* + 0x00 */ + volatile uint8_t res1[3]; + volatile uint16_t sr_csr; /* + 0x04 */ + volatile uint16_t res2[1]; + volatile uint16_t cr; /* + 0x08 */ + volatile uint16_t res3[1]; + volatile uint32_t rb_tb; /* + 0x0c */ + volatile uint16_t ipcr_acr; /* + 0x10 */ + volatile uint16_t res4[1]; + volatile uint16_t isr_imr; /* + 0x14 */ +#define ISR_TX_RDY (1 << 8) +#define ISR_RX_RDY_FULL (1 << 9) +#define ISR_RB (1 << 15) +#define ISR_FE (1 << 14) +#define ISR_PE (1 << 13) +#define ISR_OE (1 << 12) +#define ISR_ERROR (ISR_FE | ISR_PE | ISR_OE) + +#define IMR_TX_RDY (1 << 8) +#define IMR_RX_RDY_FULL (1 << 9) + volatile uint16_t res5[1]; + volatile uint8_t ctur; /* + 0x18 */ + volatile uint8_t res6[3]; + volatile uint8_t ctlr; /* + 0x1C */ + volatile uint8_t res7[0x13]; + volatile uint8_t ivr; /* + 0x30 */ + volatile uint8_t res8[3]; + volatile uint8_t ip; /* + 0x34 */ + volatile uint8_t res9[3]; + volatile uint8_t op1; /* + 0x38 */ + volatile uint8_t res10[3]; + volatile uint8_t op0; /* + 0x3C */ + volatile uint8_t res11[3]; + volatile uint8_t sicr; /* + 0x40 */ + volatile uint8_t res12[0x17]; + volatile uint16_t rfnum; /* + 0x58 */ + volatile uint16_t res13[1]; + volatile uint16_t tfnum; /* + 0x5C */ + volatile uint16_t res14[1]; + volatile uint16_t rfdata; /* + 0x60 */ + volatile uint16_t res15[1]; + volatile uint16_t rfstat; /* + 0x64 */ + volatile uint16_t res16[1]; + volatile uint8_t rfcntl; /* + 0x68 */ + volatile uint8_t res17[5]; + volatile uint16_t rfalarm; /* + 0x6E */ + volatile uint8_t res18[2]; + volatile uint16_t rfrptr; /* + 0x72 */ + volatile uint16_t res19[1]; + volatile uint16_t rfwptr; /* + 0x76 */ + volatile uint16_t res20[1]; + volatile uint16_t rflrfptr; /* + 0x7A */ + volatile uint16_t rflwfptr; /* + 0x7C */ + volatile uint16_t res21[1]; + volatile uint16_t tfdata; /* + 0x80 */ + volatile uint16_t res22[1]; + volatile uint16_t tfstat; /* + 0x84 */ + volatile uint16_t res23[1]; + volatile uint8_t tfcntl; /* + 0x88 */ + volatile uint8_t res24[5]; + volatile uint16_t tfalarm; /* + 0x8E */ + volatile uint8_t res25[2]; + volatile uint16_t tfrptr; /* + 0x92 */ + volatile uint16_t res26[1]; + volatile uint16_t tfwptr; /* + 0x96 */ + volatile uint16_t res27[1]; + volatile uint16_t tflrfptr; /* + 0x96 */ + volatile uint16_t tflwfptr; /* + 0x9C */ + volatile uint16_t res28[1]; /* end at offset 0x9F */ + volatile uint8_t res29[0x160]; + } psc[MPC5200_PSC_REG_SETS]; + /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap + * from PSC5, therefore we instantiate seven(!) PSC register sets + */ + +#define TX_FIFO_SIZE 256 +#define RX_FIFO_SIZE 512 + + + volatile uint8_t irda[0x200]; + + /* + * ethernet registers (MBAR + 0x3000) + */ + + /* Control and status Registers (offset 000-1FF) */ + + volatile uint32_t fec_id; /* + 0x000 */ + volatile uint32_t ievent; /* + 0x004 */ + volatile uint32_t imask; /* + 0x008 */ + + volatile uint32_t res9[1]; /* + 0x00C */ + volatile uint32_t r_des_active; /* + 0x010 */ + volatile uint32_t x_des_active; /* + 0x014 */ + volatile uint32_t r_des_active_cl; /* + 0x018 */ + volatile uint32_t x_des_active_cl; /* + 0x01C */ + volatile uint32_t ivent_set; /* + 0x020 */ + volatile uint32_t ecntrl; /* + 0x024 */ + + volatile uint32_t res10[6]; /* + 0x028-03C */ + volatile uint32_t mii_data; /* + 0x040 */ + volatile uint32_t mii_speed; /* + 0x044 */ + volatile uint32_t mii_status; /* + 0x048 */ + + volatile uint32_t res11[5]; /* + 0x04C-05C */ + volatile uint32_t mib_data; /* + 0x060 */ + volatile uint32_t mib_control; /* + 0x064 */ + + volatile uint32_t res12[6]; /* + 0x068-7C */ + volatile uint32_t r_activate; /* + 0x080 */ + volatile uint32_t r_cntrl; /* + 0x084 */ + volatile uint32_t r_hash; /* + 0x088 */ + volatile uint32_t r_data; /* + 0x08C */ + volatile uint32_t ar_done; /* + 0x090 */ + volatile uint32_t r_test; /* + 0x094 */ + volatile uint32_t r_mib; /* + 0x098 */ + volatile uint32_t r_da_low; /* + 0x09C */ + volatile uint32_t r_da_high; /* + 0x0A0 */ + + volatile uint32_t res13[7]; /* + 0x0A4-0BC */ + volatile uint32_t x_activate; /* + 0x0C0 */ + volatile uint32_t x_cntrl; /* + 0x0C4 */ + volatile uint32_t backoff; /* + 0x0C8 */ + volatile uint32_t x_data; /* + 0x0CC */ + volatile uint32_t x_status; /* + 0x0D0 */ + volatile uint32_t x_mib; /* + 0x0D4 */ + volatile uint32_t x_test; /* + 0x0D8 */ + volatile uint32_t fdxfc_da1; /* + 0x0DC */ + volatile uint32_t fdxfc_da2; /* + 0x0E0 */ + volatile uint32_t paddr1; /* + 0x0E4 */ + volatile uint32_t paddr2; /* + 0x0E8 */ + volatile uint32_t op_pause; /* + 0x0EC */ + + volatile uint32_t res14[4]; /* + 0x0F0-0FC */ + volatile uint32_t instr_reg; /* + 0x100 */ + volatile uint32_t context_reg; /* + 0x104 */ + volatile uint32_t test_cntrl; /* + 0x108 */ + volatile uint32_t acc_reg; /* + 0x10C */ + volatile uint32_t ones; /* + 0x110 */ + volatile uint32_t zeros; /* + 0x114 */ + volatile uint32_t iaddr1; /* + 0x118 */ + volatile uint32_t iaddr2; /* + 0x11C */ + volatile uint32_t gaddr1; /* + 0x120 */ + volatile uint32_t gaddr2; /* + 0x124 */ + volatile uint32_t random; /* + 0x128 */ + volatile uint32_t rand1; /* + 0x12C */ + volatile uint32_t tmp; /* + 0x130 */ + + volatile uint32_t res15[3]; /* + 0x134-13C */ + volatile uint32_t fifo_id; /* + 0x140 */ + volatile uint32_t x_wmrk; /* + 0x144 */ + volatile uint32_t fcntrl; /* + 0x148 */ + volatile uint32_t r_bound; /* + 0x14C */ + volatile uint32_t r_fstart; /* + 0x150 */ + volatile uint32_t r_count; /* + 0x154 */ + volatile uint32_t r_lag; /* + 0x158 */ + volatile uint32_t r_read; /* + 0x15C */ + volatile uint32_t r_write; /* + 0x160 */ + volatile uint32_t x_count; /* + 0x164 */ + volatile uint32_t x_lag; /* + 0x168 */ + volatile uint32_t x_retry; /* + 0x16C */ + volatile uint32_t x_write; /* + 0x170 */ + volatile uint32_t x_read; /* + 0x174 */ + + volatile uint32_t res16[2]; /* + 0x178-17C */ + volatile uint32_t fm_cntrl; /* + 0x180 */ + volatile uint32_t rfifo_data; /* + 0x184 */ + volatile uint32_t rfifo_status; /* + 0x188 */ + volatile uint32_t rfifo_cntrl; /* + 0x18C */ + volatile uint32_t rfifo_lrf_ptr; /* + 0x190 */ + volatile uint32_t rfifo_lwf_ptr; /* + 0x194 */ + volatile uint32_t rfifo_alarm; /* + 0x198 */ + volatile uint32_t rfifo_rdptr; /* + 0x19C */ + volatile uint32_t rfifo_wrptr; /* + 0x1A0 */ + volatile uint32_t tfifo_data; /* + 0x1A4 */ + volatile uint32_t tfifo_status; /* + 0x1A8 */ + volatile uint32_t tfifo_cntrl; /* + 0x1AC */ + volatile uint32_t tfifo_lrf_ptr; /* + 0x1B0 */ + volatile uint32_t tfifo_lwf_ptr; /* + 0x1B4 */ + volatile uint32_t tfifo_alarm; /* + 0x1B8 */ + volatile uint32_t tfifo_rdptr; /* + 0x1BC */ + volatile uint32_t tfifo_wrptr; /* + 0x1C0 */ + + volatile uint32_t reset_cntrl; /* + 0x1C4 */ + volatile uint32_t xmit_fsm; /* + 0x1C8 */ + + volatile uint32_t res17[3]; /* + 0x1CC-1D4 */ + volatile uint32_t rdes_data0; /* + 0x1D8 */ + volatile uint32_t rdes_data1; /* + 0x1DC */ + volatile uint32_t r_length; /* + 0x1E0 */ + volatile uint32_t x_length; /* + 0x1E4 */ + volatile uint32_t x_addr; /* + 0x1E8 */ + volatile uint32_t cdes_data; /* + 0x1EC */ + volatile uint32_t status; /* + 0x1F0 */ + volatile uint32_t dma_control; /* + 0x1F4 */ + volatile uint32_t des_cmnd; /* + 0x1F8 */ + volatile uint32_t data; /* + 0x1FC */ + + volatile uint8_t RES[0x600]; + + +#if 0 + /* MIB COUNTERS (Offset 200-2FF) */ + + volatile uint32_t rmon_t_drop; /* + 0x200 */ + volatile uint32_t rmon_t_packets; /* + 0x204 */ + volatile uint32_t rmon_t_bc_pkt; /* + 0x208 */ + volatile uint32_t rmon_t_mc_pkt; /* + 0x20C */ + volatile uint32_t rmon_t_crc_align; /* + 0x210 */ + volatile uint32_t rmon_t_undersize; /* + 0x214 */ + volatile uint32_t rmon_t_oversize; /* + 0x218 */ + volatile uint32_t rmon_t_frag; /* + 0x21C */ + volatile uint32_t rmon_t_jab; /* + 0x220 */ + volatile uint32_t rmon_t_col; /* + 0x224 */ + volatile uint32_t rmon_t_p64; /* + 0x228 */ + volatile uint32_t rmon_t_p65to127; /* + 0x22C */ + volatile uint32_t rmon_t_p128to255; /* + 0x230 */ + volatile uint32_t rmon_t_p256to511; /* + 0x234 */ + volatile uint32_t rmon_t_p512to1023; /* + 0x238 */ + volatile uint32_t rmon_t_p1024to2047; /* + 0x23C */ + volatile uint32_t rmon_t_p_gte2048; /* + 0x240 */ + volatile uint32_t rmon_t_octets; /* + 0x244 */ + volatile uint32_t ieee_t_drop; /* + 0x248 */ + volatile uint32_t ieee_t_frame_ok; /* + 0x24C */ + volatile uint32_t ieee_t_1col; /* + 0x250 */ + volatile uint32_t ieee_t_mcol; /* + 0x254 */ + volatile uint32_t ieee_t_def; /* + 0x258 */ + volatile uint32_t ieee_t_lcol; /* + 0x25C */ + volatile uint32_t ieee_t_excol; /* + 0x260 */ + volatile uint32_t ieee_t_macerr; /* + 0x264 */ + volatile uint32_t ieee_t_cserr; /* + 0x268 */ + volatile uint32_t ieee_t_sqe; /* + 0x26C */ + volatile uint32_t t_fdxfc; /* + 0x270 */ + volatile uint32_t ieee_t_octets_ok; /* + 0x274 */ + + volatile uint32_t res18[2]; /* + 0x278-27C */ + volatile uint32_t rmon_r_drop; /* + 0x280 */ + volatile uint32_t rmon_r_packets; /* + 0x284 */ + volatile uint32_t rmon_r_bc_pkt; /* + 0x288 */ + volatile uint32_t rmon_r_mc_pkt; /* + 0x28C */ + volatile uint32_t rmon_r_crc_align; /* + 0x290 */ + volatile uint32_t rmon_r_undersize; /* + 0x294 */ + volatile uint32_t rmon_r_oversize; /* + 0x298 */ + volatile uint32_t rmon_r_frag; /* + 0x29C */ + volatile uint32_t rmon_r_jab; /* + 0x2A0 */ + + volatile uint32_t rmon_r_resvd_0; /* + 0x2A4 */ + + volatile uint32_t rmon_r_p64; /* + 0x2A8 */ + volatile uint32_t rmon_r_p65to127; /* + 0x2AC */ + volatile uint32_t rmon_r_p128to255; /* + 0x2B0 */ + volatile uint32_t rmon_r_p256to511; /* + 0x2B4 */ + volatile uint32_t rmon_r_p512to1023; /* + 0x2B8 */ + volatile uint32_t rmon_r_p1024to2047; /* + 0x2BC */ + volatile uint32_t rmon_r_p_gte2048; /* + 0x2C0 */ + volatile uint32_t rmon_r_octets; /* + 0x2C4 */ + volatile uint32_t ieee_r_drop; /* + 0x2C8 */ + volatile uint32_t ieee_r_frame_ok; /* + 0x2CC */ + volatile uint32_t ieee_r_crc; /* + 0x2D0 */ + volatile uint32_t ieee_r_align; /* + 0x2D4 */ + volatile uint32_t r_macerr; /* + 0x2D8 */ + volatile uint32_t r_fdxfc; /* + 0x2DC */ + volatile uint32_t ieee_r_octets_ok; /* + 0x2E0 */ + + volatile uint32_t res19[6]; /* + 0x2E4-2FC */ + + volatile uint32_t res20[64]; /* + 0x300-3FF */ + + volatile uint32_t res21[256]; /* + 0x400-800 */ +#endif + + /* + * SmartComm DMA PCI registers (MBAR + 0x3800) + */ + volatile uint8_t pci[0x200]; + + /* + * advanced technology attachment registers (MBAR + 0x3A00) + */ + + /* ATA host registers (offset 0x00-0x28) */ + volatile uint32_t ata_hcfg; /* + 0x00 */ + volatile uint32_t ata_hsr; /* + 0x04 */ + volatile uint32_t ata_pio1; /* + 0x08 */ + volatile uint32_t ata_pio2; /* + 0x0C */ + volatile uint32_t ata_dma1; /* + 0x10 */ + volatile uint32_t ata_dma2; /* + 0x14 */ + volatile uint32_t ata_udma1; /* + 0x18 */ + volatile uint32_t ata_udma2; /* + 0x1C */ + volatile uint32_t ata_udma3; /* + 0x20 */ + volatile uint32_t ata_udma4; /* + 0x24 */ + volatile uint32_t ata_udma5; /* + 0x28 */ + volatile uint32_t ata_res1[4]; /* + 0x2C-0x3C */ + + /* ATA FIFO registers (offset 0x3C-0x50) */ + volatile uint32_t ata_rtfdwr; /* + 0x3C */ + +#define ATA_RTFSR_ERR BSP_BBIT32(9) +#define ATA_RTFSR_UF BSP_BBIT32(10) +#define ATA_RTFSR_OF BSP_BBIT32(11) +#define ATA_RTFSR_FULL BSP_BBIT32(12) +#define ATA_RTFSR_HI BSP_BBIT32(13) +#define ATA_RTFSR_LO BSP_BBIT32(14) +#define ATA_RTFSR_EMPTY BSP_BBIT32(15) + + volatile uint32_t ata_rtfsr; /* + 0x40 */ + +#define ATA_RTFCR_WFR BSP_BBIT32(2) +#define ATA_RTFCR_GR(val) BSP_BFLD32(val, 5, 7) + + volatile uint32_t ata_rtfcr; /* + 0x44 */ + volatile uint32_t ata_rtfar; /* + 0x48 */ + volatile uint32_t ata_rtfrpr; /* + 0x4C */ + volatile uint32_t ata_rtfwpr; /* + 0x50 */ + volatile uint32_t ata_res2[2]; /* + 0x54-0x5C */ + + /* ATA drive registers (offset 0x5C-0x80) */ + volatile uint32_t ata_dctr_dasr; /* + 0x5C */ + volatile uint32_t ata_ddr; /* + 0x60 */ + volatile uint32_t ata_dfr_der; /* + 0x64 */ + volatile uint32_t ata_dscr; /* + 0x68 */ + volatile uint32_t ata_dsnr; /* + 0x6C */ + volatile uint32_t ata_dclr; /* + 0x70 */ + volatile uint32_t ata_dchr; /* + 0x74 */ + volatile uint32_t ata_ddhr; /* + 0x78 */ + volatile uint32_t ata_dcr_dsr; /* + 0x7C */ + volatile uint32_t ata_res3[0xA0]; /* + 0x80-0x200 */ + + /* + * inter-integrated circuit registers (MBAR + 0x3D00) + */ + struct mpc5200_i2c_regs_s { + volatile uint8_t madr; /* i2c address reg. + 0x00 */ + volatile uint8_t res_1[3]; + volatile uint8_t mfdr; /* i2c freq. divider reg. + 0x04 */ + volatile uint8_t res_5[3]; + volatile uint8_t mcr; /* i2c control reg. + 0x08 */ + volatile uint8_t res_9[3]; + +#define MPC5200_I2C_MCR_MEN (1 << (7-0)) +#define MPC5200_I2C_MCR_MIEN (1 << (7-1)) +#define MPC5200_I2C_MCR_MSTA (1 << (7-2)) +#define MPC5200_I2C_MCR_MTX (1 << (7-3)) +#define MPC5200_I2C_MCR_TXAK (1 << (7-4)) +#define MPC5200_I2C_MCR_RSTA (1 << (7-5)) + + volatile uint8_t msr; /* i2c status reg. + 0x0C */ + volatile uint8_t res_d[3]; +#define MPC5200_I2C_MSR_CF (1 << (7-0)) +#define MPC5200_I2C_MSR_MAAS (1 << (7-1)) +#define MPC5200_I2C_MSR_BB (1 << (7-2)) +#define MPC5200_I2C_MSR_MAL (1 << (7-3)) +#define MPC5200_I2C_MSR_SRW (1 << (7-5)) +#define MPC5200_I2C_MSR_MIF (1 << (7-6)) +#define MPC5200_I2C_MSR_RXAK (1 << (7-7)) + volatile uint8_t mdr; /* i2c data I/O reg. + 0x10 */ + volatile uint8_t res_11[3]; + volatile uint8_t res_14[12]; /* reserved + 0x14 */ + volatile uint8_t icr; /* i2c irq ctrl reg. + 0x20 */ +#define MPC5200_I2C_ICR_BNBE2 (1 << (7-0)) +#define MPC5200_I2C_ICR_TE2 (1 << (7-1)) +#define MPC5200_I2C_ICR_RE2 (1 << (7-2)) +#define MPC5200_I2C_ICR_IE2 (1 << (7-3)) +#define MPC5200_I2C_ICR_MASK2 (MPC5200_I2C_ICR_BNBE2|MPC5200_I2C_ICR_TE2\ + |MPC5200_I2C_ICR_RE2|MPC5200_I2C_ICR_IE2) +#define MPC5200_I2C_ICR_BNBE1 (1 << (7-4)) +#define MPC5200_I2C_ICR_TE1 (1 << (7-5)) +#define MPC5200_I2C_ICR_RE1 (1 << (7-6)) +#define MPC5200_I2C_ICR_IE1 (1 << (7-7)) +#define MPC5200_I2C_ICR_MASK1 (MPC5200_I2C_ICR_BNBE1|MPC5200_I2C_ICR_TE1\ + |MPC5200_I2C_ICR_RE1|MPC5200_I2C_ICR_IE1) + volatile uint8_t res_21[3]; + volatile uint32_t res_24[7]; /* reserved + 0x24 */ + } i2c_regs[2]; + volatile uint8_t res_3d80[0x280]; + + /* + * on-chip static RAM memory locations (MBAR + 0x4000) + */ + volatile uint8_t sram_res0x4000[0x4000]; + volatile uint8_t sram[0x4000]; + +} mpc5200_t; + +extern volatile mpc5200_t mpc5200; + +#ifdef __cplusplus +} +#endif + +#endif /*ASM*/ + +#endif /* __MPC5200_h__ */ diff --git a/bsps/powerpc/gen5200/include/bsp/mscan-base.h b/bsps/powerpc/gen5200/include/bsp/mscan-base.h new file mode 100644 index 0000000000..a2b8737d8e --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/mscan-base.h @@ -0,0 +1,284 @@ +/** + * @file + * + * @ingroup m + * + * @brief MSCAN register definitions and support functions. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MSCAN_BASE_H +#define LIBBSP_MSCAN_BASE_H + +#include + +#include + +/** + * @defgroup m MSCAN + * + * @{ + */ + +#define MSCAN_BIT_RATE_MIN 10000 + +#define MSCAN_BIT_RATE_MAX 1000000 + +#define MSCAN_BIT_RATE_DEFAULT 125000 + +#define MSCAN_FILTER_NUMBER_MIN 0 + +#define MSCAN_FILTER_NUMBER_2 2 + +#define MSCAN_FILTER_NUMBER_4 4 + +#define MSCAN_FILTER_NUMBER_MAX 8 + +#define MSCAN_FILTER_ID_DEFAULT 0U + +#define MSCAN_FILTER_MASK_DEFAULT 0xffffffffU + +#define MSCAN_TRANSMIT_BUFFER_NUMBER 3 + +/** + * @name MSCAN Control Register 0 (CANCTL0) + * + * @{ + */ + +#define CTL0_RXFRM (1 << 7) +#define CTL0_RXACT (1 << 6) +#define CTL0_CSWAI (1 << 5) +#define CTL0_SYNCH (1 << 4) +#define CTL0_TIME (1 << 3) +#define CTL0_WUPE (1 << 2) +#define CTL0_SLPRQ (1 << 1) +#define CTL0_INITRQ (1 << 0) + +/** @} */ + +/** + * @name MSCAN Control Register 1 (CANCTL1) + * + * @{ + */ + +#define CTL1_CANE (1 << 7) +#define CTL1_CLKSRC (1 << 6) +#define CTL1_LOOPB (1 << 5) +#define CTL1_LISTEN (1 << 4) +#define CTL1_WUPM (1 << 2) +#define CTL1_SLPAK (1 << 1) +#define CTL1_INITAK (1 << 0) + +/** @} */ + +/** + * @name MSCAN Bus Timing Register 0 (CANBTR0) + * + * @{ + */ + +#define BTR0_SJW_MASK 0xc0 +#define BTR0_BRP_MASK 0x3f + +#define BTR0_SJW( btr0) ((btr0) << 6) +#define BTR0_BRP( btr0) ((btr0) << 0) + +#define BTR0_GET_SJW( btr0) (((btr0) & BTR0_SJW_MASK) >> 6) +#define BTR0_GET_BRP( btr0) (((btr0) & BTR0_BRP_MASK) >> 0) + +/** @} */ + +/** + * @name MSCAN Bus Timing Register 1 (CANBTR1) + * + * @{ + */ + +#define BTR1_SAMP_MASK 0x80 +#define BTR1_TSEG1_MASK 0x0f +#define BTR1_TSEG2_MASK 0x70 + +#define BTR1_SAMP (1 << 7) +#define BTR1_TSEG1( btr1) ((btr1) << 0) +#define BTR1_TSEG2( btr1) ((btr1) << 4) + +#define BTR1_GET_TSEG1( btr0) (((btr0) & BTR1_TSEG1_MASK) >> 0) +#define BTR1_GET_TSEG2( btr0) (((btr0) & BTR1_TSEG2_MASK) >> 4) + +/** @} */ + +/** + * @name MSCAN Receiver Flag Register (CANRFLG) + * + * @{ + */ + +#define RFLG_WUPIF (1 << 7) +#define RFLG_CSCIF (1 << 6) +#define RFLG_RSTAT_MASK (3 << 4) +#define RFLG_RSTAT_OK (0 << 4) +#define RFLG_RSTAT_WRN (1 << 4) +#define RFLG_RSTAT_ERR (2 << 4) +#define RFLG_RSTAT_OFF (3 << 4) +#define RFLG_TSTAT_MASK (3 << 2) +#define RFLG_TSTAT_OK (0 << 2) +#define RFLG_TSTAT_WRN (1 << 2) +#define RFLG_TSTAT_ERR (2 << 2) +#define RFLG_TSTAT_OFF (3 << 2) +#define RFLG_OVRIF (1 << 1) +#define RFLG_RXF (1 << 0) +#define RFLG_GET_RX_STATE(rflg) (((rflg) >> 4) & 0x03) +#define RFLG_GET_TX_STATE(rflg) (((rflg) >> 2) & 0x03) + +/** @} */ + +/** + * @name MSCAN Receiver Interrupt Enable Register (CANRIER) + * + * @{ + */ + +#define RIER_WUPIE (1 << 7) +#define RIER_CSCIE (1 << 6) +#define RIER_RSTAT(rier) ((rier) << 4) +#define RIER_TSTAT(rier) ((rier) << 2) +#define RIER_OVRIE (1 << 1) +#define RIER_RXFIE (1 << 0) + +/** @} */ + +/** + * @name MSCAN Transmitter Flag Register (CANTFLG) + * + * @{ + */ + +#define TFLG_TXE2 (1 << 2) +#define TFLG_TXE1 (1 << 1) +#define TFLG_TXE0 (1 << 0) + +/** @} */ + +/** + * @name MSCAN Transmitter Interrupt Enable Register (CANTIER) + * + * @{ + */ + +#define TIER_TXEI2 (1 << 2) +#define TIER_TXEI1 (1 << 1) +#define TIER_TXEI0 (1 << 0) + +/** @} */ + +/** + * @name MSCAN Transmitter Message Abort Request (CANTARQ) + * + * @{ + */ + +#define TARQ_ABTRQ2 (1 << 2) +#define TARQ_ABTRQ1 (1 << 1) +#define TARQ_ABTRQ0 (1 << 0) + +/** @} */ + +/** + * @name MSCAN Transmitter Message Abort Acknoledge (CANTAAK) + * + * @{ + */ + +#define TAAK_ABTRQ2 (1 << 2) +#define TAAK_ABTRQ1 (1 << 1) +#define TAAK_ABTRQ0 (1 << 0) + +/** @} */ + +/** + * @name MSCAN Transmit Buffer Selection (CANBSEL) + * + * @{ + */ + +#define BSEL_TX2 (1 << 2) +#define BSEL_TX1 (1 << 1) +#define BSEL_TX0 (1 << 0) + +/** @} */ + +/** + * @name MSCAN ID Acceptance Control Register (CANIDAC) + * + * @{ + */ + +#define IDAC_IDAM1 (1 << 5) +#define IDAC_IDAM0 (1 << 4) +#define IDAC_IDAM (IDAC_IDAM1 | IDAC_IDAM0) +#define IDAC_IDHIT( idac) ((idac) & 0x7) + +/** @} */ + +/** + * @brief MSCAN registers. + */ +typedef struct mpc5200_mscan mscan; + +/** + * @brief MSCAN context that has to be saved throughout the initialization + * mode. + */ +typedef struct { + uint8_t ctl0; + uint8_t rier; + uint8_t tier; +} mscan_context; + +bool mscan_enable( volatile mscan *m, unsigned bit_rate); + +void mscan_disable( volatile mscan *m); + +void mscan_interrupts_disable( volatile mscan *m); + +bool mscan_set_bit_rate( volatile mscan *m, unsigned bit_rate); + +void mscan_initialization_mode_enter( volatile mscan *m, mscan_context *context); + +void mscan_initialization_mode_leave( volatile mscan *m, const mscan_context *context); + +void mscan_sleep_mode_enter( volatile mscan *m); + +void mscan_sleep_mode_leave( volatile mscan *m); + +volatile uint8_t *mscan_id_acceptance_register( volatile mscan *m, unsigned i); + +volatile uint8_t *mscan_id_mask_register( volatile mscan *m, unsigned i); + +unsigned mscan_filter_number( volatile mscan *m); + +bool mscan_set_filter_number( volatile mscan *m, unsigned number); + +bool mscan_filter_operation( volatile mscan *m, bool set, unsigned index, uint32_t *id, uint32_t *mask); + +void mscan_filter_clear( volatile mscan *m); + +void mscan_get_error_counters( volatile mscan *m, unsigned *rec, unsigned *tec); + +/** @} */ + +#endif /* LIBBSP_MSCAN_BASE_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/mscan.h b/bsps/powerpc/gen5200/include/bsp/mscan.h new file mode 100644 index 0000000000..9cb7fd44e7 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/mscan.h @@ -0,0 +1,127 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2005 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file has to be included by application when using mscan | +\*===============================================================*/ +#ifndef __MSCAN_H__ +#define __MSCAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MSCAN_A_DEV_NAME "/dev/mscana" +#define MSCAN_B_DEV_NAME "/dev/mscanb" +#define MSCAN_0_DEV_NAME "/dev/mscan0" +#define MSCAN_1_DEV_NAME "/dev/mscan1" +#define MSCAN_A 0 +#define MSCAN_B 1 + +#define MSCAN_MAX_DATA_BYTES 8 + +#define MSCAN_MESS_ID_RTR (1 << 15) +#define MSCAN_MESS_ID_RTR_MASK (1 << 15) +#define MSCAN_MESS_ID_ID_MASK ((1 << 11)-1) +#define MSCAN_MESS_ID_HAS_RTR(id) (((id)&MSCAN_MESS_ID_RTR_MASK)==MSCAN_MESS_ID_RTR) + +#define MSCAN_SET_RX_ID 1 +#define MSCAN_GET_RX_ID 2 +#define MSCAN_SET_RX_ID_MASK 3 +#define MSCAN_GET_RX_ID_MASK 4 +#define MSCAN_SET_TX_ID 5 +#define MSCAN_GET_TX_ID 6 +#define TOUCAN_MSCAN_INIT 7 +#define MSCAN_SET_BAUDRATE 8 +#define SET_TX_BUF_NO 9 + +struct can_message + { + /* uint16_t mess_len; */ + uint16_t mess_id; + uint16_t mess_time_stamp; + uint8_t mess_data[MSCAN_MAX_DATA_BYTES]; + uint8_t mess_len; + uint8_t mess_rtr; + uint32_t toucan_tx_idx; + }; + +struct mscan_rx_parms + { + struct can_message *rx_mess; + uint32_t rx_timeout; + uint8_t rx_flags; + }; + +struct mscan_tx_parms + { + struct can_message *tx_mess; + uint32_t tx_idx; + }; + +struct mscan_ctrl_parms + { + uint32_t ctrl_id; + uint32_t ctrl_id_mask; + uint8_t ctrl_reg_no; + uint8_t ctrl_tx_buf_no; + uint32_t ctrl_can_bitrate; + void (*toucan_cb_fnc)(int16_t); + }; + + +rtems_device_driver mscan_initialize( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + +rtems_device_driver mscan_open( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + +rtems_device_driver mscan_close( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + +rtems_device_driver mscan_read( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + +rtems_device_driver mscan_write( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + +rtems_device_driver mscan_control( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + + +#define MSCAN_DRIVER_TABLE_ENTRY \ + { mscan_initialize, mscan_open, mscan_close, \ + mscan_read, mscan_write, mscan_control } + +#ifdef __cplusplus +} +#endif + +#endif /* __MSCAN_H__ */ diff --git a/bsps/powerpc/gen5200/include/bsp/nvram.h b/bsps/powerpc/gen5200/include/bsp/nvram.h new file mode 100644 index 0000000000..b05c35986f --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/nvram.h @@ -0,0 +1,141 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2005 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains the nvram declarations | +\*===============================================================*/ +/***********************************************************************/ +/* */ +/* Module: nvram.h */ +/* Date: 07/17/2003 */ +/* Purpose: RTEMS M93C64-based header file */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Description: M93C46 is a serial microwire EEPROM which contains */ +/* 1Kbit (128 bytes/64 words) of non-volatile memory. */ +/* The device can be configured for byte- or word- */ +/* access. The driver provides a file-like interface */ +/* to this memory. */ +/* */ +/* MPC5x00 PIN settings: */ +/* */ +/* PSC3_6 (output) -> MC93C46 serial data in (D) */ +/* PSC3_7 (input) -> MC93C46 serial data out (Q) */ +/* PSC3_8 (output) -> MC93C46 chip select input (S) */ +/* PSC3_9 (output) -> MC93C46 serial clock (C) */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Code */ +/* References: DS1307-based Non-Volatile memory device driver */ +/* Module: nvram.h */ +/* Project: RTEMS 4.6.0pre1 / MCF5206Elite BSP */ +/* Version 1.1 */ +/* Date: 10/26/2001 */ +/* Author: Victor V. Vengerov */ +/* Copyright: Copyright (C) 2000 OKTET Ltd.,St.-Petersburg,Russia */ +/* */ +/* The license and distribution terms for this file may be */ +/* found in the file LICENSE in this distribution or at */ +/* http://www.rtems.org/license/LICENSE. */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Partially based on the code references which are named above. */ +/* Adaptions, modifications, enhancements and any recent parts of */ +/* the code are under the right of */ +/* */ +/* IPR Engineering, Dachauer Straße 38, D-80335 München */ +/* Copyright(C) 2003 */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* IPR Engineering makes no representation or warranties with */ +/* respect to the performance of this computer program, and */ +/* specifically disclaims any responsibility for any damages, */ +/* special or consequential, connected with the use of this program. */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Version history: 1.0 */ +/* */ +/***********************************************************************/ + +#ifndef __NVRAM_H__ +#define __NVRAM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* include */ +#include + +/* Macros for TBL read access */ +#define TBL_READ(count) __asm__ volatile ("mftb %0\n" : "=r" (count) : "0" (count)) +#define TMBASE_CLOCK (G2_CLOCK/4) + +/* Simple usec delay function prototype */ +void wait_usec(unsigned long); + +/* nvram_driver_initialize -- + * Non-volatile memory device driver initialization. + */ +rtems_device_driver +nvram_driver_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_open -- + * Non-volatile memory device driver open primitive. + */ +rtems_device_driver +nvram_driver_open(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_close -- + * Non-volatile memory device driver close primitive. + */ +rtems_device_driver +nvram_driver_close(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_read -- + * Non-volatile memory device driver read primitive. + */ +rtems_device_driver +nvram_driver_read(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_write -- + * Non-volatile memory device driver write primitive. + */ +rtems_device_driver +nvram_driver_write(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __NVRAM_H__ */ diff --git a/bsps/powerpc/gen5200/include/bsp/slicetimer.h b/bsps/powerpc/gen5200/include/bsp/slicetimer.h new file mode 100644 index 0000000000..e089dbc8ad --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/slicetimer.h @@ -0,0 +1,69 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2005 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares functions to use the slice timer module +\*===============================================================*/ +#ifndef __SLICETIMER_H__ +#define __SLICETIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define SLT0 0 +#define SLT1 1 + +#define SLT0_INT_FREQUENCY 10000 +#define SLT1_INT_FREQUENCY 0 + +#define SLT_CNTRL_RW (1 << 26) +#define SLT_CNTRL_INTEN (1 << 25) +#define SLT_CNTRL_TIMEN (1 << 24) + +#define SLT_TSR_ST (1 << 24) + +#define SLT_TSR_COUNT(freq) ((freq) ? ((IPB_CLOCK)/(freq)) : (0xFFFFFF)) + +rtems_device_driver slt_initialize( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + +#define SLTIME_DRIVER_TABLE_ENTRY \ + { slt_initialize, NULL, NULL, \ + NULL, NULL, NULL } + +void mpc5200_slt_isr(uint32_t); +rtems_isr mpc5200_slt0_isr(rtems_irq_hdl_param); +rtems_isr mpc5200_slt1_isr(rtems_irq_hdl_param); +void mpc5200_init_slt(uint32_t); +void mpc5200_set_slt_count(uint32_t); +void mpc5200_enable_slt_int(uint32_t); +void mpc5200_disable_slt_int(uint32_t); +uint32_t mpc5200_check_slt_status(uint32_t); +/*void sltOn(const rtems_irq_connect_data *); +void sltOff(const rtems_irq_connect_data *); +int sltIsOn(const rtems_irq_connect_data *);*/ +void Install_slt(rtems_device_minor_number); + +#ifdef __cplusplus +} +#endif + +#endif /* __SLICETIMER_H__ */ diff --git a/bsps/powerpc/gen5200/include/bsp/u-boot-config.h b/bsps/powerpc/gen5200/include/bsp/u-boot-config.h new file mode 100644 index 0000000000..2fee83bce9 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/u-boot-config.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_GEN52XX_U_BOOT_CONFIG_H +#define LIBBSP_POWERPC_GEN52XX_U_BOOT_CONFIG_H + +#define CONFIG_MPC5xxx + +#endif /* LIBBSP_POWERPC_GEN52XX_U_BOOT_CONFIG_H */ diff --git a/bsps/powerpc/gen5200/include/tm27.h b/bsps/powerpc/gen5200/include/tm27.h new file mode 100644 index 0000000000..ff43cc9ab6 --- /dev/null +++ b/bsps/powerpc/gen5200/include/tm27.h @@ -0,0 +1,66 @@ +/* + * @file + * @ingroup powerpc_gen5200 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include +#include + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 1 + +void nullFunc() {} + +static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, + 0, + (rtems_irq_enable)nullFunc, + (rtems_irq_disable)nullFunc, + (rtems_irq_is_enabled) nullFunc}; +void Install_tm27_vector(void (*_handler)()) +{ + clockIrqData.hdl = _handler; + if (!BSP_install_rtems_irq_handler (&clockIrqData)) { + printk("Error installing clock interrupt handler!\n"); + bsp_fatal(MPC5200_FATAL_TM27_IRQ_INSTALL); + } +} + +#define Cause_tm27_intr() \ + do { \ + uint32_t _clicks = 8; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Clear_tm27_intr() \ + do { \ + uint32_t _clicks = 0xffffffff; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Lower_tm27_intr() \ + do { \ + uint32_t _msr = 0; \ + _ISR_Set_level( 0 ); \ + __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + _msr |= 0x8002; \ + __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + } while (0) + +#endif diff --git a/bsps/powerpc/gen83xx/headers.am b/bsps/powerpc/gen83xx/headers.am new file mode 100644 index 0000000000..39d4333934 --- /dev/null +++ b/bsps/powerpc/gen83xx/headers.am @@ -0,0 +1,13 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/gen83xx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/gen83xx/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen83xx/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen83xx/include/bsp/tsec-config.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen83xx/include/bsp/u-boot-config.h diff --git a/bsps/powerpc/gen83xx/include/bsp.h b/bsps/powerpc/gen83xx/include/bsp.h new file mode 100644 index 0000000000..59fd20de54 --- /dev/null +++ b/bsps/powerpc/gen83xx/include/bsp.h @@ -0,0 +1,163 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC83xx BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains board specific definitions | +\*===============================================================*/ + + +#ifndef LIBBSP_POWERPC_GEN83XX_BSP_H +#define LIBBSP_POWERPC_GEN83XX_BSP_H + +#define BSP_FEATURE_IRQ_EXTENSION + +#include + +#include + +#include + +/* + * Some symbols defined in the linker command file. + */ + +LINKER_SYMBOL(bsp_ram_start); +LINKER_SYMBOL(bsp_ram_end); +LINKER_SYMBOL(bsp_ram_size); + +LINKER_SYMBOL(bsp_rom_start); +LINKER_SYMBOL(bsp_rom_end); +LINKER_SYMBOL(bsp_rom_size); + +LINKER_SYMBOL(bsp_section_text_start); +LINKER_SYMBOL(bsp_section_text_end); +LINKER_SYMBOL(bsp_section_text_size); + +LINKER_SYMBOL(bsp_section_data_start); +LINKER_SYMBOL(bsp_section_data_end); +LINKER_SYMBOL(bsp_section_data_size); + +LINKER_SYMBOL(bsp_section_bss_start); +LINKER_SYMBOL(bsp_section_bss_end); +LINKER_SYMBOL(bsp_section_bss_size); + +LINKER_SYMBOL(bsp_interrupt_stack_start); +LINKER_SYMBOL(bsp_interrupt_stack_end); +LINKER_SYMBOL(bsp_interrupt_stack_size); + +LINKER_SYMBOL(bsp_work_area_start); + +LINKER_SYMBOL(IMMRBAR); + +#ifndef ASM + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * indicate, that BSP has no IDE driver + */ +#undef RTEMS_BSP_HAS_IDE_DRIVER + +/* misc macros */ +#define BSP_ARRAY_CNT(arr) (sizeof(arr)/sizeof(arr[0])) + +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +/* functions */ +rtems_status_code bsp_register_i2c(void); +rtems_status_code bsp_register_spi(void); + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_tsec_attach + +#ifdef MPC83XX_BOARD_MPC8313ERDB + #define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec2" + #define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec1" +#else + #define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec1" + #define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2" +#endif + +#if defined(MPC83XX_BOARD_MPC8349EAMDS) +/* + * i2c EEPROM device name + */ +#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom" +#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom" + +/* + * SPI Flash device name + */ +#define RTEMS_BSP_SPI_FLASH_DEVICE_NAME "flash" +#define RTEMS_BSP_SPI_FLASH_DEVICE_PATH "/dev/spi.flash" +#endif /* defined(MPC83XX_BOARD_MPC8349EAMDS) */ + +#if defined(MPC83XX_BOARD_HSC_CM01) +/* + * i2c EEPROM device name + */ +#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom" +#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom" + +/* + * SPI FRAM device name + */ +#define RTEMS_BSP_SPI_FRAM_DEVICE_NAME "fram" +#define RTEMS_BSP_SPI_FRAM_DEVICE_PATH "/dev/spi.fram" +#endif /* defined(MPC83XX_BOARD_HSC_CM01) */ + +extern unsigned int BSP_bus_frequency; + +extern uint32_t bsp_clicks_per_usec; + +/* + * Convert decrementer value to tenths of microseconds (used by shared timer + * driver). + */ +#define BSP_Convert_decrementer( _value ) \ + ((int) (((_value) * 10) / bsp_clicks_per_usec)) + +void mpc83xx_zero_4( void *dest, size_t n); + +void cpu_init( void); + +void bsp_restart(void *addr); + +#if defined(HAS_UBOOT) + /* Routine to obtain U-Boot environment variables */ + const char *bsp_uboot_getenv( + const char *name + ); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* GEN83xx */ diff --git a/bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h b/bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h new file mode 100644 index 0000000000..c7a5bac9c2 --- /dev/null +++ b/bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h @@ -0,0 +1,381 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC83xx BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains board specific definitions | +\*===============================================================*/ + + +#ifndef __GEN83xx_HWREG_VALS_h +#define __GEN83xx_HWREG_VALS_h + +#include +#include + +#ifdef MPC83XX_HAS_NAND_LP_FLASH_ON_CS0 + #define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB08 | RCWHR_RLEXT_NAND) +#else + #define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB16 | RCWHR_RLEXT_LGCY) +#endif + +/* + * distinguish board characteristics + */ +#if defined(MPC83XX_BOARD_MPC8349EAMDS) +/* + * for Freescale MPC8349 EAMDS + */ +/* + * two DUART channels supported + */ +#define GEN83xx_DUART_AVAIL_MASK 0x03 + +/* we need the low level initialization in start.S*/ +#define NEED_LOW_LEVEL_INIT +/* + * clocking infos + */ +#define BSP_CLKIN_FRQ 66000000L +#define RCFG_SYSPLL_MF 4 +#define RCFG_COREPLL_MF 4 + +/* + * Reset configuration words + */ +#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ + RCWLR_DDRCM_1_1 | \ + RCWLR_SPMF(RCFG_SYSPLL_MF) | \ + RCWLR_COREPLL(RCFG_COREPLL_MF)) + +#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ + RCWHR_PCI_32 | \ + RCWHR_PCI1ARB_EN | \ + RCWHR_PCI2ARB_EN | \ + RCWHR_CORE_EN | \ + RCWHR_BMS_LOW | \ + RCWHR_BOOTSEQ_NONE | \ + RCWHR_SW_DIS | \ + MPC83XX_RCWHR_BOOT_DEVICE | \ + RCWHR_TSEC1M_GMII | \ + RCWHR_TSEC2M_GMII | \ + RCWHR_ENDIAN_BIG | \ + RCWHR_LALE_NORM | \ + RCWHR_LDP_PAR) +#elif defined(MPC83XX_BOARD_HSC_CM01) +/* + * for JPK HSC_CM01 + */ +/* + * one DUART channel (UART1) supported + */ +#define GEN83xx_DUART_AVAIL_MASK 0x01 + +/* we need the low level initialization in start.S*/ +#define NEED_LOW_LEVEL_INIT +/* + * clocking infos + */ +#define BSP_CLKIN_FRQ 30000000L +#define RCFG_SYSPLL_MF 11 +#define RCFG_COREPLL_MF 4 +/* + * Reset configuration words + */ +#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ + RCWLR_DDRCM_1_1 | \ + RCWLR_SPMF(RCFG_SYSPLL_MF) | \ + RCWLR_COREPLL(RCFG_COREPLL_MF)) + +#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ + RCWHR_PCI_32 | \ + RCWHR_PCI1ARB_DIS | \ + RCWHR_PCI2ARB_DIS | \ + RCWHR_CORE_EN | \ + RCWHR_BMS_LOW | \ + RCWHR_BOOTSEQ_NONE | \ + RCWHR_SW_DIS | \ + MPC83XX_RCWHR_BOOT_DEVICE | \ + RCWHR_TSEC1M_RGMII | \ + RCWHR_TSEC2M_GMII | \ + RCWHR_ENDIAN_BIG | \ + RCWHR_LALE_EARLY | \ + RCWHR_LDP_SPC) + +#elif defined(MPC83XX_BOARD_BR_UID) +/* + * for BR UID + */ +/* + * one DUART channel (UART1) supported + */ +#define GEN83xx_DUART_AVAIL_MASK 0x01 + +/* we need the low level initialization in start.S*/ +#define NEED_LOW_LEVEL_INIT +/* + * clocking infos + */ +#define BSP_CLKIN_FRQ 25000000L +#define RCFG_SYSPLL_MF 5 +#define RCFG_COREPLL_MF 5 +/* + * Reset configuration words + */ +#define RESET_CONF_WRD_L \ + (RCWLR_LBIUCM_1_1 \ + | RCWLR_DDRCM_2_1 \ + | RCWLR_SPMF(RCFG_SYSPLL_MF) \ + | RCWLR_COREPLL(RCFG_COREPLL_MF) \ + | RCWLR_CEVCOD_1_2 \ + | RCWLR_CEPMF(8) \ + ) + +#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ + RCWHR_PCI_32 | \ + RCWHR_PCI1ARB_DIS | \ + RCWHR_CORE_EN | \ + RCWHR_BMS_LOW | \ + RCWHR_BOOTSEQ_NONE | \ + RCWHR_SW_DIS | \ + MPC83XX_RCWHR_BOOT_DEVICE | \ + RCWHR_ENDIAN_BIG) + +#elif defined( HAS_UBOOT) + +/* TODO */ + +#else + +#error "board type not defined" + +#endif + +#if defined(MPC83XX_BOARD_MPC8349EAMDS) +/************************** + * for Freescale MPC83XX_BOARD_MPC8349EAMDS + */ + +/* + * working values for various registers, used in start/start.S + */ + +/* + * Local Access Windows + * FIXME: decode bit settings + */ +#define LBLAWBAR0_VAL 0xFE000000 +#define LBLAWAR0_VAL 0x80000016 +#define LBLAWBAR1_VAL 0xF8000000 +#define LBLAWAR1_VAL 0x8000000E +#define LBLAWBAR2_VAL 0xF0000000 +#define LBLAWAR2_VAL 0x80000019 +#define DDRLAWBAR0_VAL 0x00000000 +#define DDRLAWAR0_VAL 0x8000001B +/* + * Local Bus (Memory) Controller + * FIXME: decode bit settings + */ +#define BR0_VAL 0xFE001001 +#define OR0_VAL 0xFF806FF7 +#define BR1_VAL 0xF8000801 +#define OR1_VAL 0xFFFFE8F0 +#define BR2_VAL 0xF0001861 +#define OR2_VAL 0xFC006901 +/* + * SDRAM registers + * FIXME: decode bit settings + */ +#define MRPTR_VAL 0x20000000 +#define LSRT_VAL 0x32000000 +#define LSDMR_VAL 0x4062D733 +#define LCRR_VAL 0x80000004 + +/* + * DDR-SDRAM registers + * FIXME: decode bit settings + */ +#define CS2_BNDS_VAL 0x00000007 +#define CS3_BNDS_VAL 0x0008000F +#define CS2_CONFIG_VAL 0x80000101 +#define CS3_CONFIG_VAL 0x80000101 +#define TIMING_CFG_1_VAL 0x36333321 +#define TIMING_CFG_2_VAL 0x00000800 +#define DDR_SDRAM_CFG_VAL 0xC2000000 +#define DDR_SDRAM_MODE_VAL 0x00000022 +#define DDR_SDRAM_INTTVL_VAL 0x045B0100 +#define DDR_SDRAM_CLK_CNTL_VAL 0x00000000 + +#elif defined(MPC83XX_BOARD_HSC_CM01) +/************************** + * for JPK HSC_CM01 + */ + +/* fpga BCSR register */ +#define FPGA_START 0xF8000000 +#define FPGA_SIZE 0x8000 +#define FPGA_END (FPGA_START+FPGA_SIZE-1) + +/* + * working values for various registers, used in start/start.S + */ + +/* fpga config 16 MB size */ +#define FPGA_CONFIG_START 0xF8000000 +#define FPGA_CONFIG_SIZE 0x01000000 +/* fpga register 8 MB size */ +#define FPGA_REGISTER_START 0xF9000000 +#define FPGA_REGISTER_SIZE 0x00800000 +/* fpga fifo 8 MB size */ +#define FPGA_FIFO_START 0xF9800000 +#define FPGA_FIFO_SIZE 0x00800000 + +#define FPGA_START (FPGA_CONFIG_START) +// fpga window size 32 MByte +#define FPGA_SIZE (0x02000000) +#define FPGA_END (FPGA_START+FPGA_SIZE-1) + +/* + * Local Access Windows + * FIXME: decode bit settings + */ + +#define LBLAWBAR0_VAL bsp_rom_start +#define LBLAWAR0_VAL 0x80000018 +#define LBLAWBAR1_VAL (FPGA_CONFIG_START) +#define LBLAWAR1_VAL 0x80000018 +#define DDRLAWBAR0_VAL bsp_ram_start +#define DDRLAWAR0_VAL 0x8000001B +/* + * Local Bus (Memory) Controller + * FIXME: decode bit settings + */ +#define BR0_VAL (0xFE000000 | 0x01001) +#define OR0_VAL 0xFE000E54 +// fpga config access range (UPM_A) (32 kByte) +#define BR2_VAL (FPGA_CONFIG_START | 0x01881) +#define OR2_VAL 0xFFFF9100 + +// fpga register access range (UPM_B) (8 MByte) +#define BR3_VAL (FPGA_REGISTER_START | 0x018A1) +#define OR3_VAL 0xFF801100 + +// fpga fifo access range (UPM_C) (8 MByte) +#define BR4_VAL (FPGA_FIFO_START | 0x018C1) +#define OR4_VAL 0xFF801100 + +/* + * SDRAM registers + */ +#define MRPTR_VAL 0x20000000 +#define LSRT_VAL 0x32000000 +#define LSDMR_VAL 0x4062D733 +#define LCRR_VAL 0x80010004 + +/* + * DDR-SDRAM registers + * FIXME: decode bit settings + */ +#define DDRCDR_VAL 0x00000001 +#define CS0_BNDS_VAL 0x0000000F +#define CS0_CONFIG_VAL 0x80810102 +#define TIMING_CFG_0_VAL 0x00420802 +#define TIMING_CFG_1_VAL 0x3735A322 +#define TIMING_CFG_2_VAL 0x2F9044C7 +#define DDR_SDRAM_CFG_2_VAL 0x00401000 +#define DDR_SDRAM_MODE_VAL 0x44521632 +#define DDR_SDRAM_CLK_CNTL_VAL 0x01800000 +#define DDR_SDRAM_CFG_VAL 0x63000008 + +#define DDR_ERR_DISABLE_VAL 0x0000008D +#define DDR_ERR_DISABLE_VAL2 0x00000089 +#define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE +#define DDR_SDRAM_INIT_ADDR_VAL 0 +#define DDR_SDRAM_INTERVAL_VAL 0x05080000 + +#elif defined(MPC83XX_BOARD_BR_UID) +/************************** + * for BR UID + */ + +/* + * working values for various registers, used in start/start.S + */ + +/* + * Local Access Windows + * FIXME: decode bit settings + */ + +#define LBLAWBAR0_VAL bsp_rom_start +#define LBLAWAR0_VAL 0x80000018 +#define DDRLAWBAR0_VAL bsp_ram_start +#define DDRLAWAR0_VAL 0x8000001B + + +/* + * clocking for local bus: + * ALE active for 1 clock + * local bus clock = 1/2 csb clock + */ +#define LCRR_VAL 0x80010002 + +/* + * DDR-SDRAM registers + * FIXME: decode bit settings + */ +#define DDRCDR_VAL 0x00000001 +#define CS0_BNDS_VAL 0x0000000F +#define CS0_CONFIG_VAL 0x80014202 +#define TIMING_CFG_0_VAL 0x00220802 +#define TIMING_CFG_1_VAL 0x26259222 +#define TIMING_CFG_2_VAL 0x111048C7 +#define DDR_SDRAM_CFG_2_VAL 0x00401000 +#define DDR_SDRAM_MODE_VAL 0x200F1632 +#define DDR_SDRAM_MODE_2_VAL 0x40006000 +#define DDR_SDRAM_CLK_CNTL_VAL 0x01800000 +#define DDR_SDRAM_CFG_VAL 0x43100008 + +#define DDR_ERR_DISABLE_VAL 0x0000008D +#define DDR_ERR_DISABLE_VAL2 0x00000089 +#define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE +#define DDR_SDRAM_INIT_ADDR_VAL 0 +#define DDR_SDRAM_INTERVAL_VAL 0x01E8222E + +#elif defined( HAS_UBOOT) + +/* TODO */ + +#else + +#error "board type not defined" + +#endif + +/************************** + * derived values for all boards + */ +/* value of input clock divider (derived from pll mode reg) */ +#if MPC83XX_CHIP_TYPE != 8309 + #define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1) +#else + /* On the MPC8309 this bit is reserved */ + #define BSP_SYSPLL_CKID 1 +#endif +/* value of system pll (derived from pll mode reg) */ +#define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f) +/* value of system pll (derived from pll mode reg) */ +#define BSP_COREPLL_MF ((mpc83xx.clk.spmr>>(31-15))&0x7f) + +#endif /* __GEN83xx_HWREG_VALS_h */ diff --git a/bsps/powerpc/gen83xx/include/bsp/irq.h b/bsps/powerpc/gen83xx/include/bsp/irq.h new file mode 100644 index 0000000000..dc084ed2a2 --- /dev/null +++ b/bsps/powerpc/gen83xx/include/bsp/irq.h @@ -0,0 +1,184 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC83xx BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007, 2010 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares constants of the interrupt controller | +\*===============================================================*/ + + +#ifndef GEN83xx_IRQ_IRQ_H +#define GEN83xx_IRQ_IRQ_H + +#include +#include +#include + +#include + +/* + * the following definitions specify the indices used + * to interface the interrupt handler API + */ + +/* + * Peripheral IRQ handlers related definitions + */ +#define BSP_IPIC_PER_IRQ_NUMBER 128 +#define BSP_IPIC_IRQ_LOWEST_OFFSET 0 +#define BSP_IPIC_IRQ_MAX_OFFSET (BSP_IPIC_IRQ_LOWEST_OFFSET\ + +BSP_IPIC_PER_IRQ_NUMBER-1) + +#define BSP_IS_IPIC_IRQ(irqnum) \ + (((irqnum) >= BSP_IPIC_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_IPIC_IRQ_MAX_OFFSET)) +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 1 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_IPIC_IRQ_MAX_OFFSET+1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ + +BSP_PROCESSOR_IRQ_NUMBER-1) + +#define BSP_IS_PROCESSOR_IRQ(irqnum) \ + (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) +#define BSP_LOWEST_OFFSET BSP_IPIC_IRQ_LOWEST_OFFSET +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET + +#define BSP_IS_VALID_IRQ(irqnum) \ + (BSP_IS_PROCESSOR_IRQ(irqnum) \ + || BSP_IS_IPIC_IRQ(irqnum)) + +#ifndef ASM +#ifdef __cplusplus +extern "C" { +#endif + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ + typedef enum { + BSP_IPIC_IRQ_FIRST = BSP_IPIC_IRQ_LOWEST_OFFSET, + BSP_IPIC_IRQ_ERROR = BSP_IPIC_IRQ_LOWEST_OFFSET + 0, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_DMA1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 3, + BSP_IPIC_IRQ_UART = BSP_IPIC_IRQ_LOWEST_OFFSET + 9, + BSP_IPIC_IRQ_FLEXCAN = BSP_IPIC_IRQ_LOWEST_OFFSET + 10, +#else + BSP_IPIC_IRQ_UART1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 9, + BSP_IPIC_IRQ_UART2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 10, + BSP_IPIC_IRQ_SEC = BSP_IPIC_IRQ_LOWEST_OFFSET + 11, +#endif + BSP_IPIC_IRQ_I2C1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 14, + BSP_IPIC_IRQ_I2C2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 15, + BSP_IPIC_IRQ_SPI = BSP_IPIC_IRQ_LOWEST_OFFSET + 16, + BSP_IPIC_IRQ_IRQ1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 17, + BSP_IPIC_IRQ_IRQ2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 18, + BSP_IPIC_IRQ_IRQ3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 19, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_QUICC_HI = BSP_IPIC_IRQ_LOWEST_OFFSET + 32, + BSP_IPIC_IRQ_QUICC_LO = BSP_IPIC_IRQ_LOWEST_OFFSET + 33, +#else + BSP_IPIC_IRQ_IRQ4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 20, + BSP_IPIC_IRQ_IRQ5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 21, + BSP_IPIC_IRQ_IRQ6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 22, + BSP_IPIC_IRQ_IRQ7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 23, + BSP_IPIC_IRQ_TSEC1_TX = BSP_IPIC_IRQ_LOWEST_OFFSET + 32, + BSP_IPIC_IRQ_TSEC1_RX = BSP_IPIC_IRQ_LOWEST_OFFSET + 33, + BSP_IPIC_IRQ_TSEC1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 34, + BSP_IPIC_IRQ_TSEC2_TX = BSP_IPIC_IRQ_LOWEST_OFFSET + 35, + BSP_IPIC_IRQ_TSEC2_RX = BSP_IPIC_IRQ_LOWEST_OFFSET + 36, + BSP_IPIC_IRQ_TSEC2_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 37, +#endif + BSP_IPIC_IRQ_USB_DR = BSP_IPIC_IRQ_LOWEST_OFFSET + 38, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_ESDHC = BSP_IPIC_IRQ_LOWEST_OFFSET + 42, +#else + BSP_IPIC_IRQ_USB_MPH = BSP_IPIC_IRQ_LOWEST_OFFSET + 39, +#endif + BSP_IPIC_IRQ_IRQ0 = BSP_IPIC_IRQ_LOWEST_OFFSET + 48, + BSP_IPIC_IRQ_RTC_SEC = BSP_IPIC_IRQ_LOWEST_OFFSET + 64, + BSP_IPIC_IRQ_PIT = BSP_IPIC_IRQ_LOWEST_OFFSET + 65, + BSP_IPIC_IRQ_PCI1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 66, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_MSIR1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 67, +#else + BSP_IPIC_IRQ_PCI2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 67, +#endif + BSP_IPIC_IRQ_RTC_ALR = BSP_IPIC_IRQ_LOWEST_OFFSET + 68, + BSP_IPIC_IRQ_MU = BSP_IPIC_IRQ_LOWEST_OFFSET + 69, + BSP_IPIC_IRQ_SBA = BSP_IPIC_IRQ_LOWEST_OFFSET + 70, + BSP_IPIC_IRQ_DMA = BSP_IPIC_IRQ_LOWEST_OFFSET + 71, + BSP_IPIC_IRQ_GTM4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 72, + BSP_IPIC_IRQ_GTM8 = BSP_IPIC_IRQ_LOWEST_OFFSET + 73, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_QUICC_PORTS = BSP_IPIC_IRQ_LOWEST_OFFSET + 74, + BSP_IPIC_IRQ_GPIO = BSP_IPIC_IRQ_LOWEST_OFFSET + 75, +#else + BSP_IPIC_IRQ_GPIO1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 74, + BSP_IPIC_IRQ_GPIO2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 75, +#endif + BSP_IPIC_IRQ_DDR = BSP_IPIC_IRQ_LOWEST_OFFSET + 76, + BSP_IPIC_IRQ_LBC = BSP_IPIC_IRQ_LOWEST_OFFSET + 77, + BSP_IPIC_IRQ_GTM2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 78, + BSP_IPIC_IRQ_GTM6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 79, + BSP_IPIC_IRQ_PMC = BSP_IPIC_IRQ_LOWEST_OFFSET + 80, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_MSIR2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 81, + BSP_IPIC_IRQ_MSIR3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 82, +#else + BSP_IPIC_IRQ_GTM3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 84, + BSP_IPIC_IRQ_GTM7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 85, +#endif +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_MSIR4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 86, + BSP_IPIC_IRQ_MSIR5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 87, + BSP_IPIC_IRQ_MSIR6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 88, + BSP_IPIC_IRQ_MSIR7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 89, +#endif + BSP_IPIC_IRQ_GTM1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 90, + BSP_IPIC_IRQ_GTM5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 91, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_DMA1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 94, + BSP_IPIC_IRQ_DPTC = BSP_IPIC_IRQ_LOWEST_OFFSET + 95, +#endif + + BSP_IPIC_IRQ_LAST = BSP_IPIC_IRQ_MAX_OFFSET, + } rtems_irq_symbolic_name; + +#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET + +#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET + +rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask); + +#define MPC83XX_IPIC_INTERRUPT_NORMAL 0 + +#define MPC83XX_IPIC_INTERRUPT_SYSTEM 1 + +#define MPC83XX_IPIC_INTERRUPT_CRITICAL 2 + +rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type); + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ + +#endif /* GEN83XX_IRQ_IRQ_H */ diff --git a/bsps/powerpc/gen83xx/include/bsp/tsec-config.h b/bsps/powerpc/gen83xx/include/bsp/tsec-config.h new file mode 100644 index 0000000000..5ec0ccbad1 --- /dev/null +++ b/bsps/powerpc/gen83xx/include/bsp/tsec-config.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_GEN83XX_TSEC_CONFIG_H +#define LIBBSP_POWERPC_GEN83XX_TSEC_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define TSEC_COUNT 2 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_GEN83XX_TSEC_CONFIG_H */ diff --git a/bsps/powerpc/gen83xx/include/bsp/u-boot-config.h b/bsps/powerpc/gen83xx/include/bsp/u-boot-config.h new file mode 100644 index 0000000000..c2271c965b --- /dev/null +++ b/bsps/powerpc/gen83xx/include/bsp/u-boot-config.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_GEN83XX_U_BOOT_CONFIG_H +#define LIBBSP_POWERPC_GEN83XX_U_BOOT_CONFIG_H + +#define CONFIG_MPC83xx +#define CONFIG_HAS_ETH1 + +#endif /* LIBBSP_POWERPC_GEN83XX_U_BOOT_CONFIG_H */ diff --git a/bsps/powerpc/gen83xx/include/tm27.h b/bsps/powerpc/gen83xx/include/tm27.h new file mode 100644 index 0000000000..22787473a5 --- /dev/null +++ b/bsps/powerpc/gen83xx/include/tm27.h @@ -0,0 +1,62 @@ +/** + * @file + * + * @brief Support file for Timer Test 27. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 + #error "This is an RTEMS internal file you must not include directly." +#endif /* _RTEMS_TMTEST27 */ + +#ifndef TMTESTS_TM27_H +#define TMTESTS_TM27_H + +#include +#include + +#define MUST_WAIT_FOR_INTERRUPT 1 + +static void (*tm27_interrupt_handler)(rtems_vector_number); + +static int tm27_exception_handler( BSP_Exception_frame *frame, unsigned number) +{ + (*tm27_interrupt_handler)( 0); + + return 0; +} + +void Install_tm27_vector( void (*handler)(rtems_vector_number)) +{ + int rv = 0; + + tm27_interrupt_handler = handler; + + rv = ppc_exc_set_handler( ASM_DEC_VECTOR, tm27_exception_handler); + if (rv < 0) { + printk( "Error installing clock interrupt handler!\n"); + } +} + +#define Cause_tm27_intr() \ + ppc_set_decrementer_register( 8) + +#define Clear_tm27_intr() \ + ppc_set_decrementer_register( UINT32_MAX) + +#define Lower_tm27_intr() \ + (void) ppc_external_exceptions_enable() + +#endif /* TMTESTS_TM27_H */ diff --git a/bsps/powerpc/haleakala/headers.am b/bsps/powerpc/haleakala/headers.am new file mode 100644 index 0000000000..ed8becdf81 --- /dev/null +++ b/bsps/powerpc/haleakala/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/haleakala/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/haleakala/include/mmu_405.h +include_HEADERS += ../../../../../../bsps/powerpc/haleakala/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/haleakala/include/bsp/irq.h diff --git a/bsps/powerpc/haleakala/include/bsp.h b/bsps/powerpc/haleakala/include/bsp.h new file mode 100644 index 0000000000..b26e739e60 --- /dev/null +++ b/bsps/powerpc/haleakala/include/bsp.h @@ -0,0 +1,87 @@ +/* bsp.h + * + * Generic 405EX bsp.h + * derived from virtex/include/bsp.h + * by Michael Hamel ADInstruments Ltd 2008 + * + * derived from helas403/include/bsp.h: + * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp + * Author: Thomas Doerfler + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * + * + */ + +#ifndef LIBBSP_POWERPC_HALEAKALA_BSP_H +#define LIBBSP_POWERPC_HALEAKALA_BSP_H + +#include + +#ifdef ASM + + + /* Definition of where to store registers in alignment handler */ + #define ALIGN_REGS 0x0140 + +#else + + #include + #include + #include + #include + #include + + #ifdef __cplusplus + extern "C" { + #endif + + /* Network Defines */ + #define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" + + struct rtems_bsdnet_ifconfig; + int rtems_emac_driver_attach(struct rtems_bsdnet_ifconfig* config, int attaching); + #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_emac_driver_attach + + #define BSP_UART_IOBASE_COM1 0xEF600200 /* PPC405EX */ + #define BSP_UART_IOBASE_COM2 0xEF600300 + + #define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ + + #define BSP_UART_BAUD_BASE (11059200 / 16) /* Kilauea ext clock, max speed */ + + #ifdef __cplusplus + } + #endif +#endif /* ASM */ + +#endif /* BSP_H */ diff --git a/bsps/powerpc/haleakala/include/bsp/irq.h b/bsps/powerpc/haleakala/include/bsp/irq.h new file mode 100644 index 0000000000..c413ec3172 --- /dev/null +++ b/bsps/powerpc/haleakala/include/bsp/irq.h @@ -0,0 +1,166 @@ +/*===============================================================*\ +| Project: RTEMS Haleakala BSP | +| by Michael Hamel ADInstruments Ltd 2008 | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | +\*===============================================================*/ + + +#ifndef Haleakala_IRQ_IRQ_H +#define Haleakala_IRQ_IRQ_H + +/* Implemented for us in bsp_irq_dispatch_list */ +#define BSP_SHARED_HANDLER_SUPPORT 1 + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + + /* Define UIC interrupt numbers; IRQs that cause an external interrupt that needs further decode. + These are arbitrary but it makes things easier if they match the CPU interrupt numbers */ + + /* + + #define BSP_UIC_UART0_GP (BSP_UIC_IRQ_LOWEST_OFFSET + 0) + #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_ExtMaster (BSP_UIC_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_PCI (BSP_UIC_IRQ_LOWEST_OFFSET + 4) + #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 5) + #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 6) + #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 7) + #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 8) + #define BSP_UIC_ENetWU (BSP_UIC_IRQ_LOWEST_OFFSET + 9) + #define BSP_UIC_MALSERR (BSP_UIC_IRQ_LOWEST_OFFSET + 10) + #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11) + #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 12) + #define BSP_UIC_MALTXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 13) + #define BSP_UIC_MALRXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 14) + #define BSP_UIC_ENet (BSP_UIC_IRQ_LOWEST_OFFSET + 15) + #define BSP_UIC_PCISERR (BSP_UIC_IRQ_LOWEST_OFFSET + 16) + #define BSP_UIC_ECCERR (BSP_UIC_IRQ_LOWEST_OFFSET + 17) + #define BSP_UIC_PCIPower (BSP_UIC_IRQ_LOWEST_OFFSET + 18) + #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 25) + #define BSP_UIC_IRQ1 (BSP_UIC_IRQ_LOWEST_OFFSET + 26) + #define BSP_UIC_IRQ2 (BSP_UIC_IRQ_LOWEST_OFFSET + 27) + #define BSP_UIC_IRQ3 (BSP_UIC_IRQ_LOWEST_OFFSET + 28) + #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 29) + #define BSP_UIC_IRQ5 (BSP_UIC_IRQ_LOWEST_OFFSET + 30) + #define BSP_UIC_IRQ6 (BSP_UIC_IRQ_LOWEST_OFFSET + 31) + + #define BSP_UIC_IRQ_NUMBER (32) + + */ + /* PPC405EX interrupt vectors */ + #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_EIPPKP_READY (BSP_UIC_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_EIPPKP_TRNG (BSP_UIC_IRQ_LOWEST_OFFSET + 4) + #define BSP_UIC_EBM (BSP_UIC_IRQ_LOWEST_OFFSET + 5) + #define BSP_UIC_OPBtoPLB (BSP_UIC_IRQ_LOWEST_OFFSET + 6) + #define BSP_UIC_IIC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 7) + #define BSP_UIC_SPI (BSP_UIC_IRQ_LOWEST_OFFSET + 8) + #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 9) + #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 10) + #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11) + #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 12) + #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 13) + #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 14) + #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 15) + #define BSP_UIC_PCIe0AL (BSP_UIC_IRQ_LOWEST_OFFSET + 16) + #define BSP_UIC_PCIe0VPD (BSP_UIC_IRQ_LOWEST_OFFSET + 17) + #define BSP_UIC_PCIe0HRst (BSP_UIC_IRQ_LOWEST_OFFSET + 18) + #define BSP_UIC_EIPPKP_PKA (BSP_UIC_IRQ_LOWEST_OFFSET + 19) + #define BSP_UIC_PCIe0TCR (BSP_UIC_IRQ_LOWEST_OFFSET + 20) + #define BSP_UIC_PCIe0VCO (BSP_UIC_IRQ_LOWEST_OFFSET + 21) + #define BSP_UIC_EIPPKP_TRNG_AL (BSP_UIC_IRQ_LOWEST_OFFSET + 22) + #define BSP_UIC_EIP94 (BSP_UIC_IRQ_LOWEST_OFFSET + 23) + #define BSP_UIC_EMAC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 24) + #define BSP_UIC_EMAC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 25) + #define BSP_UIC_UART0 (BSP_UIC_IRQ_LOWEST_OFFSET + 26) + #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 27) + #define BSP_UIC_UIC2_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 28) + #define BSP_UIC_UIC2_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 29) + #define BSP_UIC_UIC1_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 30) + #define BSP_UIC_UIC1_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 31) + + #define BSP_UIC1_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 32) + #define BSP_UIC_MALSERR (BSP_UIC1_IRQ_LOWEST_OFFSET + 0) + #define BSP_UIC_MALTXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_MALRXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_PCIe0DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_PCIe1DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 4) + #define BSP_UIC_ExtBus (BSP_UIC1_IRQ_LOWEST_OFFSET + 5) + #define BSP_UIC_NDFC (BSP_UIC1_IRQ_LOWEST_OFFSET + 6) + #define BSP_UIC_EIPKP_SLAVE (BSP_UIC1_IRQ_LOWEST_OFFSET + 7) + #define BSP_UIC_GPT_TIMER5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 8) + #define BSP_UIC_GPT_TIMER6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 9) + + #define BSP_UIC_GPT_TIMER0 (BSP_UIC1_IRQ_LOWEST_OFFSET + 16) + #define BSP_UIC_GPT_TIMER1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 17) + #define BSP_UIC_IRQ7 (BSP_UIC1_IRQ_LOWEST_OFFSET + 18) + #define BSP_UIC_IRQ8 (BSP_UIC1_IRQ_LOWEST_OFFSET + 19) + #define BSP_UIC_IRQ9 (BSP_UIC1_IRQ_LOWEST_OFFSET + 20) + #define BSP_UIC_GPT_TIMER2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 21) + #define BSP_UIC_GPT_TIMER3 (BSP_UIC1_IRQ_LOWEST_OFFSET + 22) + #define BSP_UIC_GPT_TIMER4 (BSP_UIC1_IRQ_LOWEST_OFFSET + 23) + #define BSP_UIC_SERIAL_ROM (BSP_UIC1_IRQ_LOWEST_OFFSET + 24) + #define BSP_UIC_GPT_DEC (BSP_UIC1_IRQ_LOWEST_OFFSET + 25) + #define BSP_UIC_IRQ2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 26) + #define BSP_UIC_IRQ5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 27) + #define BSP_UIC_IRQ6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 28) + #define BSP_UIC_EMAC0WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 29) + #define BSP_UIC_IRQ1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 30) + #define BSP_UIC_EMAC1WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 31) + + #define BSP_UIC2_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 64) + #define BSP_UIC_PCIe0INTA (BSP_UIC2_IRQ_LOWEST_OFFSET + 0) + #define BSP_UIC_PCIe0INTB (BSP_UIC2_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_PCIe0INTC (BSP_UIC2_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_PCIe0INTD (BSP_UIC2_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_IRQ3 (BSP_UIC2_IRQ_LOWEST_OFFSET + 4) + + #define BSP_UIC_USBOTG (BSP_UIC2_IRQ_LOWEST_OFFSET + 30) + + #define BSP_UIC_IRQ_NUMBER (95) + + + #define BSP_UIC_IRQ_LOWEST_OFFSET 0 + #define BSP_UIC_IRQ_MAX_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + BSP_UIC_IRQ_NUMBER - 1) + + #define BSP_UART_COM1_IRQ BSP_UIC_UART0 /* Required by shared/console/uart.c */ + #define BSP_UART_COM2_IRQ BSP_UIC_UART1 + + /* Define processor IRQ numbers; IRQs that are handled by the exception vectors */ + + #define BSP_PIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET /* Required by ppc403/clock.c */ + #define BSP_FIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1 + #define BSP_WDOG BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 + + #define BSP_PROCESSOR_IRQ_NUMBER (3) + #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_MAX_OFFSET + 1) + #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) + + /* Summary and totals */ + + #define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) + #define BSP_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET) + #define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) + + extern void BSP_rtems_irq_mng_init(unsigned cpuId); // Implemented in irq_init.c + #include + + #ifdef __cplusplus + } + #endif +#endif /* ASM */ + +#endif /* Haleakala_IRQ_IRQ_H */ diff --git a/bsps/powerpc/haleakala/include/mmu_405.h b/bsps/powerpc/haleakala/include/mmu_405.h new file mode 100644 index 0000000000..e11cfa7738 --- /dev/null +++ b/bsps/powerpc/haleakala/include/mmu_405.h @@ -0,0 +1,77 @@ +#ifndef _mmu_405_h +#define _mmu_405_h + +/* + Simple interface to the PowerPC 405 MMU + + The intention here is just to allow the MMU to be used to define cacheability and + read/write/execute permissions in a simple enough way to fit entirely into the + 64-entry TLB cache. + + This code does not do address relocation and does not generate any MMU-related interrupts. + + The process ID support is there for a possible future extension where RTEMS supports + setting the process ID on task switches, which allows per-process stack protection + + This code will call fatal_error() if your add_space() calls overrun the 64 entries + + Michael Hamel ADInstruments 2008 + +*/ + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stdint.h" + +enum { + kAllProcessIDs = 0 +}; + +typedef enum MMUAccessType { + executable, + readOnlyData, + readOnlyNoCache, + readWriteData, + readWriteNoCache, + readWriteExecutable +} MMUAccessType; + +/* Initialise and clear the MMU */ +void mmu_initialise(); + +/* Turn on/off data access translation */ +bool mmu_enable_data(bool enable); + +/* Turn on instruction translation */ +bool mmu_enable_code(bool enable); + +/* Define properties for an area of memory (must be 1K-aligned) */ +void mmu_add_space(uint32_t startAddr, uint32_t endAddr, MMUAccessType permissions, uint8_t processID); + +/* Delete a memory property definition */ +void mmu_remove_space(uint32_t startAddr, uint32_t endAddr); + +/* Return number of TLB entries out of total in use */ +int mmu_get_tlb_count(); + +/* Allocate a new process ID and return it */ +uint8_t mmu_new_processID(); + +/* Free a process ID that has been in use */ +void mmu_free_processID(uint8_t freeThis); + +/* Return the current process ID */ +uint8_t mmu_current_processID(); + +/* Change the process ID to ID and return the old value */ +uint8_t mmu_set_processID(uint8_t toID); + + +#ifdef __cplusplus +} +#endif + +#endif //_mmu_405.h \ No newline at end of file diff --git a/bsps/powerpc/haleakala/include/tm27.h b/bsps/powerpc/haleakala/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/haleakala/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/powerpc/headers.am b/bsps/powerpc/headers.am new file mode 100644 index 0000000000..5033d8ae5a --- /dev/null +++ b/bsps/powerpc/headers.am @@ -0,0 +1,101 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../bsps/powerpc/include/ictrl.h +include_HEADERS += ../../../../../bsps/powerpc/include/mpc5xx.h +include_HEADERS += ../../../../../bsps/powerpc/include/mpc8260.h +include_HEADERS += ../../../../../bsps/powerpc/include/mpc8xx.h +include_HEADERS += ../../../../../bsps/powerpc/include/nvram.h +include_HEADERS += ../../../../../bsps/powerpc/include/tty_drv.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/consoleIo.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/flashPgm.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/flashPgmPvt.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/irq_supp.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/linker-symbols.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/motorola.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/openpic.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/pci.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/pnp.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/residual.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/start.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/tictac.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/tsec.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/u-boot-board-info.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/uart.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/vectors.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/vpd.h + +include_libcpudir = $(includedir)/libcpu +include_libcpu_HEADERS = +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/bat.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/byteorder.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/c_clock.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/cpuIdent.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/e500_mmu.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/io.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/irq.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/mmu.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/page.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/pgtable.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/powerpc-utility.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/pte121.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/raw_exception.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/spr.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/stackTrace.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/vectors.h + +include_mpc55xxdir = $(includedir)/mpc55xx +include_mpc55xx_HEADERS = +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/dspi.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/edma.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/emios.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/fsl-mpc551x.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/fsl-mpc555x.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/fsl-mpc556x.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/fsl-mpc564xL.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/fsl-mpc5668.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/fsl-mpc567x.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/mpc55xx.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/reg-defs.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/regs-edma.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/regs-mmu.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/regs.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/siu.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/watchdog.h + +include_mpc5xxdir = $(includedir)/mpc5xx +include_mpc5xx_HEADERS = +include_mpc5xx_HEADERS += ../../../../../bsps/powerpc/include/mpc5xx/console.h + +include_mpc8260dir = $(includedir)/mpc8260 +include_mpc8260_HEADERS = +include_mpc8260_HEADERS += ../../../../../bsps/powerpc/include/mpc8260/console.h +include_mpc8260_HEADERS += ../../../../../bsps/powerpc/include/mpc8260/cpm.h +include_mpc8260_HEADERS += ../../../../../bsps/powerpc/include/mpc8260/mmu.h + +include_mpc83xxdir = $(includedir)/mpc83xx +include_mpc83xx_HEADERS = +include_mpc83xx_HEADERS += ../../../../../bsps/powerpc/include/mpc83xx/gtm.h +include_mpc83xx_HEADERS += ../../../../../bsps/powerpc/include/mpc83xx/mpc83xx.h +include_mpc83xx_HEADERS += ../../../../../bsps/powerpc/include/mpc83xx/mpc83xx_i2cdrv.h +include_mpc83xx_HEADERS += ../../../../../bsps/powerpc/include/mpc83xx/mpc83xx_spidrv.h + +include_mpc8xxdir = $(includedir)/mpc8xx +include_mpc8xx_HEADERS = +include_mpc8xx_HEADERS += ../../../../../bsps/powerpc/include/mpc8xx/console.h +include_mpc8xx_HEADERS += ../../../../../bsps/powerpc/include/mpc8xx/cpm.h +include_mpc8xx_HEADERS += ../../../../../bsps/powerpc/include/mpc8xx/mmu.h + +include_ppc4xxdir = $(includedir)/ppc4xx +include_ppc4xx_HEADERS = +include_ppc4xx_HEADERS += ../../../../../bsps/powerpc/include/ppc4xx/ppc405ex.h +include_ppc4xx_HEADERS += ../../../../../bsps/powerpc/include/ppc4xx/ppc405gp.h + +include_rtems_powerpcdir = $(includedir)/rtems/powerpc +include_rtems_powerpc_HEADERS = +include_rtems_powerpc_HEADERS += ../../../../../bsps/powerpc/include/rtems/powerpc/cache.h +include_rtems_powerpc_HEADERS += ../../../../../bsps/powerpc/include/rtems/powerpc/debugmod.h +include_rtems_powerpc_HEADERS += ../../../../../bsps/powerpc/include/rtems/powerpc/powerpc.h diff --git a/bsps/powerpc/include/bsp/consoleIo.h b/bsps/powerpc/include/bsp/consoleIo.h new file mode 100644 index 0000000000..e62c9d143c --- /dev/null +++ b/bsps/powerpc/include/bsp/consoleIo.h @@ -0,0 +1,38 @@ +/* + * consoleIo.h -- console I/O package interface + * + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __CONSOLE_IO_H +#define __CONSOLE_IO_H + +typedef enum { + CONSOLE_LOG = 1, + CONSOLE_SERIAL = 2, + CONSOLE_VGA = 3, + CONSOLE_VACUUM = 4 +}ioType; + +typedef volatile unsigned char * __io_ptr; + +typedef struct { + __io_ptr io_base; + __io_ptr isa_mem_base; +} board_memory_map; + +extern board_memory_map *ptr_mem_map; + +extern int select_console(ioType t); +/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ +extern void debug_putc(const unsigned char c); +extern void debug_putc_onlcr(const char c); +extern int debug_getc(void); +extern int debug_tstc(void); +int kbdreset(void); + +#endif diff --git a/bsps/powerpc/include/bsp/flashPgm.h b/bsps/powerpc/include/bsp/flashPgm.h new file mode 100644 index 0000000000..19f2c4708e --- /dev/null +++ b/bsps/powerpc/include/bsp/flashPgm.h @@ -0,0 +1,209 @@ +#ifndef BSP_FLASH_PGM_API_H +#define BSP_FLASH_PGM_API_H + +/* Trivial Flash Programmer */ + +/* Author: Till Straumann , 2006 + * NOTE: copyright info at the bottom of this file + */ + +/* IMPORTANT NOTE + * + * The flash API is NOT THREAD SAFE. During the execution of any of the + * BSP_flashXXX() routines, flash (residing in the same device) + * MUST NOT be accessed by other threads in ANY way (NOT EVEN READ!). + * Read operations may return internal device register contents + * instead of memory array data when issued while a flash device + * is erased, written or queried by the library. + * + * The routines are intended for occasional maintenance use only + * (i.e., not for implementing a file system or similar). + * + * While polling for the completion of block erase operations the + * CPU is yielded to other threads. Busy waiting (interrupts and + * thread dispatching remain enabled) on write operations is employed. + */ + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/* Disengage flash write protection. Write protection is implemented + * at the board or chipset level by disabling all write operations/bus cycles + * to the flash device(s). + * With write protection enabled, nothing but 'ordinary' (array) read operations + * are possible. + * Write protection must be disabled not only to erase and write contents + * but also in order to read ID, size, status etc. + * None of the operations (except for BSP_flashWriteEnable()) are possible + * on a write-protected device. + * + * 'bank': flash bank # (usually 0) + * RETURNS: 0 on success, nonzero on error (printing message to stderr). + * + * NOTES: - some boards (MVME5500) don't support 'bank' granularity but + * enable/disable write protection for all devices at once. + * - a jumper-based protection mechanism might be in place + * in addition to the software-based one. Consult the user's + * manual of your board for more information. + */ +int +BSP_flashWriteEnable(int bank); + +/* Engage flash write protection (see above) + */ +int +BSP_flashWriteDisable(int bank); + +/* Erase a region of flash memory. + * 'bank': flash bank # (usually 0). + * 'offset': destination address offset (from start of bank). + * 'size': number of bytes to erase. + * 'quiet': if non-zero, suppress confirmation message / prompt + * if > 1 also suppress the progress indicator. + * + * RETURNS: 0 on success, nonzero on error (printing messages to stderr). + * + * NOTES: - 'offset' and 'size' must be block-aligned. Common 16-bit devices + * have a block size of 0x20000 bytes. If two such devices are + * operated in parallel to form a 32-bit word then the 'effective' + * block size is 0x40000 bytes. The block size can be queried by + * BSP_flashBlockSize(int bank); + * + * - erase operation is verified. + */ +int +BSP_flashErase(int bank, uint32_t offset, uint32_t size, int quiet); + +/* Write data from a buffer to flash. The target area is erased if necessary. + * + * 'bank': flash bank # (usually 0). + * 'offset': destination address offset (from start of bank). + * 'src': data source block address (in memory). + *'n_bytes': number of bytes to copy. + * 'quiet': if non-zero, suppress confirmation message / prompt + * if > 1 also suppress the progress indicator. + * + * NOTES: - Erase operations are only performed where necessary. I.e., + * if one or both of the boundaries of the destination region is/are + * not block-aligned then adjacent data are preserved provided that + * the relevant chunks of the destination are blank (erased). + * + * | fffffff | + * ^--- destination ----- ^ + * | : block boundary + * f : blank/erased pieces + * + * (If the start of the destination region up to the next block boundary + * is blank then ''-data is preserved. The end of the + * destination is treated the same way.) + * + * - user confirmation is requested before changes are made + * + * - 'src' must not point into the destination bank (no copy + * within a flash bank). + * + * - erase and write operations are verified. + * + * RETURNS: 0 on success, nonzero on error (message printed to stderr). + */ +int +BSP_flashWrite(int bank, uint32_t offset, const char *src, uint32_t n_bytes, int quiet); + +/* Copy contents of a file to flash. + * + * 'fname': Path of a file. + * 'quiet': if non-zero, suppress confirmation message / prompt + * if > 1 also suppress the progress indicator. + * + * NOTES: Convenience wrapper around BSP_flashWrite(); see above for + * args and return value. + */ +int +BSP_flashWriteFile(int bank, uint32_t offset, const char *path, int quiet); + +/* Dump info about available flash to file + * (stdout is used if f==NULL). + * + * RETURNS: 0 + * NOTES: Write protection must be disengaged (see above); + */ +int +BSP_flashDumpInfo(FILE *f); + +/* + * Obtain starting-address of flash bank (as seen from CPU) + * (returns ((uint32_t) -1) if the bank argument is invalid). + */ + +uint32_t +BSP_flashStart(int bank); + +/* + * Obtain size of flash bank (returns ((uint32_t) -1) if the + * bank argument is invalid). + */ +uint32_t +BSP_flashSize(int bank); + +/* + * Obtain block size of flash bank (sector size times + * number of devices in parallel; the block size determines + * alignment and granularity accepted by BSP_flashErase() + * (returns ((uint32_t) -1) if the bank argument is invalid). + */ +uint32_t +BSP_flashBlockSize(int bank); + +#ifdef __cplusplus + } +#endif + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#endif diff --git a/bsps/powerpc/include/bsp/flashPgmPvt.h b/bsps/powerpc/include/bsp/flashPgmPvt.h new file mode 100644 index 0000000000..c26b8ed01d --- /dev/null +++ b/bsps/powerpc/include/bsp/flashPgmPvt.h @@ -0,0 +1,274 @@ +#ifndef FLASH_GLUE_INTERFACE_H +#define FLASH_GLUE_INTERFACE_H + + +/* Trivial flash programmer (for restrictions see below) */ + +/* Author: Till Straumann , 2006 */ + +/* DO NOT INCLUDE THIS HEADER FROM APPLICATION CODE */ + +/* + * Glue interface -- to be used only internally by BSP + * and chip drivers: + * - BSP provides info about what chip drivers to use + * as well as 'wiring' info (how many devices are + * operated in parallel etc). + * - Chip drivers provide low-level 'methods' / 'ops' + * for performing basic operations which are used + * by the code in 'flash.c'. + */ + +/* To keep things simple, this API makes a few assumptions about the + * hardware: + * + * - devices operate with 16-bit data width + * - two devices are used in parallel (stride 4) to + * provide 32-bit data. I.e., the devices are + * organized like this: + * unsigned short flash[FLASH_SIZE][2]; + * - no endianness issues (i.e., flash endianness == CPU endianness) + * - fixed block size + * - fixed buffer size + * - all devices in a bank are identical + * - NOT THREAD SAFE; no locking scheme is implemented. + * - cannot copy within same flash bank. + * - write-timeout uses polling/busy-wait + * + * FIXME: code should be revised to remove assumptions on stride and 16-bit + * width to make it more generic. + */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include + +#define NumberOf(arr) (sizeof(arr)/sizeof(arr[0])) + +#define FLASH_STRIDE(b) 4 /* bytes; currently fixed */ +#define FLASH_WIDTH(b) ((b)->width) +#define FLASH_NDEVS(b) (FLASH_STRIDE(b)/FLASH_WIDTH(b)) + +/* Type declarations */ + +/* Registers */ +typedef uint8_t _u8_a_t __attribute__((may_alias)); +typedef uint16_t _u16_a_t __attribute__((may_alias)); +typedef uint32_t _u32_a_t __attribute__((may_alias)); + +/* Register addresses */ +typedef volatile _u8_a_t *A8; +typedef volatile _u16_a_t *A16; +typedef volatile _u32_a_t *A32; + +struct flash_bank_ops; + +/* + * Description of a flash bank. Multiple + * devices that are used in parallel to + * make up words of FLASH_STRIDE bytes + * are a 'physical' bank. + * + * A bank can even be a 'logical' bank + * if it includes chip-select logic, i.e., + * int can contain multiple adjacent + * 'physical' banks + * + * The BSP must provide an array of 'bankdesc' + * structs and it must initialize the fields + * + * 'start' + * size of bank; may be set to zero to instruct + * the driver to scan a bank of 'max_size' for + * devices (i.e., bank may not be fully populated) + * 'max_size' + * size of fully populated bank (defines address range + * that is scanned for devices). + * If 'max_size' is negative then scanning starts from + * the top rather than from the bottom. + * 'width' + * width of a single device (in bytes). E.g., if + * 2 16-bit devices are used to form a (ATM fixed) + * stride of 4 then 'width = 2'. If four 8-bit + * devices are employed then 'width=1'. + * 'knownVendors' + * array of vendors descriptions to use for scanning + * the bank. + * + */ +struct bankdesc { + uint32_t start; /* start of bank (CPU address) */ + uint32_t size; /* in bytes (figured out automatically) */ + int max_size; /* in case multiple banks are adjacent; + * if max_size < 0 then the bank is scanned + * backwards (from top->bottom) for devices + */ + int width; /* FIXME there might be implicit assumptions still + * that width == 2 + */ + struct vendesc *knownVendors; + /* TODO: we assume identical devices within a bank... */ + + /* The next three variables cache information obtained + * from the applicable vendor and device descriptions. + * They are written by BSP_flashCheckId(). + */ + uint32_t fblksz; /* block size in bytes; includes counting + * parallel 16-bit devices, i.e., if a + * single device has a block-size of xxx + * then fblksz = xxx*ndevs. + */ + struct devdesc *dd; + struct flash_bank_ops *ops; +}; + +struct devdesc { + uint32_t id; /* numerical ID (matched against + * ID read from device). + */ + char *name; /* informational name */ + uint32_t size; /* bytes */ + uint32_t bufsz; /* size of write buffer (bytes) */ + uint32_t fblksz; /* sector/block size (bytes) */ +}; + +struct vendesc { + uint32_t id; /* numerical ID (matched against + * ID read from device). + */ + char *name; /* informational name */ + + /* array of supported devices; + * the 'ops' specified below + * are used to access these devices + */ + struct devdesc *known_devs; + /* access methods for talking to + * devices associated with this + * vendor description. + */ + struct flash_bank_ops *ops; +}; + +/* Device Access Methods ('ops'); these must be + * implemented by low-level chip drivers + */ + +struct flash_bank_ops { +/* Read vendor/device ID; Return 0 on success, nonzero if unable to read id */ + int (*get_id)(struct bankdesc *b, uint32_t addr, uint32_t *pVendorId, uint32_t *pDeviceId); +/* Unlock block holding 'addr'ess + * + * NOTES: - device switched back to array mode on exit. + * - 'addr' must be 32-bit aligned. + */ + + void (*unlock_block)(struct bankdesc *b, uint32_t addr); +/* Lock block holding 'addr'ess + * + * NOTES: - device switched back to array mode on exit. + * - 'addr' must be 32-bit aligned. + */ + + void (*lock_block)(struct bankdesc *b, uint32_t addr); +/* Erase single block holding 'addr'ess. The routine may + * assume that the address is block/sector aligned. + * + * RETURNS: zero on error, device status on failure. + * + * NOTES: - device switched back to array mode on exit. + * - 'addr' must be 32-bit aligned. + */ + int (*erase_block)(struct bankdesc *b, uint32_t addr); +/* Query the status of the device and assert it's readiness + * leave off in array-reading mode. + * + * RETURNS: 0 on success, error status (result of status query) on error. + * + * NOTES: - error message is printed to stderr. + * - device switched back to array mode on exit. + * - 'addr' must be 32-bit aligned. + */ + uint32_t (*check_ready)(struct bankdesc *b, uint32_t addr); +/* Dump status bits (F_CMD_RD_STA results); + * 'verbose' prints non-error bits, too + */ + void (*print_stat)(struct bankdesc *b, uint32_t sta, int verbose); +/* Switch to array mode; 'addr' can be assumed to be stride-aligned */ + void (*array_mode)(struct bankdesc *b, uint32_t addr); +/* Write N bytes from 'src' to flash: + * 'src[0] .. src[N-1]' -> addr[0]..addr[N-1]. + * N may be assumed to be a multiple of 'stride' + * RETURNS: failure status or zero on success. + */ + uint32_t (*write_line)(struct bankdesc *b, uint32_t addr, const char *src, uint32_t N); +}; + +/* BSP ops (detect banks, handle write-protection on board); + * these must be implemented by the BSP. + */ + +struct flash_bsp_ops { +/* Return descriptor for bank # 'bank' or NULL (invalid arg) */ + struct bankdesc *(*bankcheck)(int bank, int quiet); +/* set (enbl:1), clear (enbl:0) or query (enbl:-1) + * on-board write protection. + * + * RETURNS 0 on success, nonzero on error. + */ + int (*flash_wp)(int bank, int enbl); +/* read a running us clock (for polling timeout) */ + uint32_t (*read_us_timer)(); +}; + +/* This must be provided by the BSP */ +extern struct flash_bsp_ops BSP_flashBspOps; + +/* Available low-level flash drivers, so far */ +extern struct vendesc BSP_flash_vendor_intel[]; +extern struct vendesc BSP_flash_vendor_spansion[]; + +#endif diff --git a/bsps/powerpc/include/bsp/irq_supp.h b/bsps/powerpc/include/bsp/irq_supp.h new file mode 100644 index 0000000000..65af48c87f --- /dev/null +++ b/bsps/powerpc/include/bsp/irq_supp.h @@ -0,0 +1,124 @@ +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IRQ_SHARED_IRQ_C_GLUE_H +#define IRQ_SHARED_IRQ_C_GLUE_H +/* + * This header describes the routines that are needed by the shared + * version of 'irq.c' (implementing the RTEMS irq API). They + * must be provided by the BSP. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef BSP_SHARED_HANDLER_SUPPORT +#define BSP_SHARED_HANDLER_SUPPORT 1 +#endif + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * PIC-independent functions to enable/disable interrupt lines at + * the pic. + * + * NOTE: the routines must ignore requests for enabling/disabling + * interrupts that are outside of the range handled by the + * PIC(s). + */ +extern void BSP_enable_irq_at_pic(const rtems_irq_number irqLine); +/* + * RETURNS: nonzero (> 0 ) if irq was enabled originally, zero if irq + * was off and negative value if there was an error. + */ +extern int BSP_disable_irq_at_pic(const rtems_irq_number irqLine); + +/* + * Initialize the PIC. + */ +extern int BSP_setup_the_pic(rtems_irq_global_settings* config); + +/* IRQ dispatcher to be defined by the PIC driver; note that it MUST + * implement shared interrupts. + * Note also that the exception frame passed to this handler is not very + * meaningful. Only the volatile registers and vector info are stored. + * + ******************************************************************* + * The routine must return zero if the interrupt was handled. If a + * nonzero value is returned the dispatcher may panic and flag an + * uncaught exception. + ******************************************************************* + */ +int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum); + +/* + * Snippet to be used by PIC drivers and by bsp_irq_dispatch_list + * traverses list of shared handlers for a given interrupt + * + */ + +static inline void +bsp_irq_dispatch_list_base( + rtems_irq_connect_data *tbl, + unsigned irq, + rtems_irq_hdl sentinel +) +{ + rtems_irq_connect_data* vchain; + for( vchain = &tbl[irq]; + ((intptr_t)vchain != -1 && vchain->hdl != sentinel); + vchain = (rtems_irq_connect_data*)vchain->next_handler ) + { + vchain->hdl(vchain->handle); + } +} + + +/* + * Snippet to be used by PIC drivers; + * enables interrupts, traverses list of + * shared handlers for a given interrupt + * and restores original irq level + * + * Note that _ISR_Get_level() & friends are preferable to + * manipulating MSR directly. + */ + +static inline void +bsp_irq_dispatch_list( + rtems_irq_connect_data *tbl, + unsigned irq, + rtems_irq_hdl sentinel +) +{ + register uint32_t l_orig; + + l_orig = _ISR_Get_level(); + + /* Enable all interrupts */ + _ISR_Set_level(0); + + + bsp_irq_dispatch_list_base( tbl, irq, sentinel ); + + /* Restore original level */ + _ISR_Set_level(l_orig); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/include/bsp/linker-symbols.h b/bsps/powerpc/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..de7a6c483d --- /dev/null +++ b/bsps/powerpc/include/bsp/linker-symbols.h @@ -0,0 +1,139 @@ +/** + * @file + * + * @ingroup powerpc_linker + * + * @brief Symbols defined in linker command base file. + */ + +/* + * Copyright (c) 2010, 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_POWERPC_SHARED_LINKER_SYMBOLS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup powerpc_linker Linker Support + * + * @ingroup powerpc_shared + * + * @brief Linker support. + * + * @{ + */ + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_fast_text_begin) +LINKER_SYMBOL(bsp_section_fast_text_end) +LINKER_SYMBOL(bsp_section_fast_text_size) +LINKER_SYMBOL(bsp_section_fast_text_load_begin) +LINKER_SYMBOL(bsp_section_fast_text_load_end) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_fast_data_begin) +LINKER_SYMBOL(bsp_section_fast_data_end) +LINKER_SYMBOL(bsp_section_fast_data_size) +LINKER_SYMBOL(bsp_section_fast_data_load_begin) +LINKER_SYMBOL(bsp_section_fast_data_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_sbss_begin) +LINKER_SYMBOL(bsp_section_sbss_end) +LINKER_SYMBOL(bsp_section_sbss_size) + +LINKER_SYMBOL(bsp_section_rwextra_begin) +LINKER_SYMBOL(bsp_section_rwextra_end) +LINKER_SYMBOL(bsp_section_rwextra_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_section_nocache_begin) +LINKER_SYMBOL(bsp_section_nocache_end) +LINKER_SYMBOL(bsp_section_nocache_size) +LINKER_SYMBOL(bsp_section_nocache_load_begin) +LINKER_SYMBOL(bsp_section_nocache_load_end) + +LINKER_SYMBOL(bsp_section_nocachenoload_begin) +LINKER_SYMBOL(bsp_section_nocachenoload_end) +LINKER_SYMBOL(bsp_section_nocachenoload_size) + +LINKER_SYMBOL(bsp_section_nocacheheap_begin) +LINKER_SYMBOL(bsp_section_nocacheheap_end) +LINKER_SYMBOL(bsp_section_nocacheheap_size) + +LINKER_SYMBOL(bsp_section_nvram_begin) +LINKER_SYMBOL(bsp_section_nvram_end) +LINKER_SYMBOL(bsp_section_nvram_size) + +#define BSP_FAST_TEXT_SECTION __attribute__((section(".bsp_fast_text"))) + +#define BSP_FAST_DATA_SECTION __attribute__((section(".bsp_fast_data"))) + +#define BSP_NOCACHE_SECTION __attribute__((section(".bsp_nocache"))) + +#define BSP_NOCACHE_SUBSECTION(subsection) \ + __attribute__((section(".bsp_nocache." # subsection))) + +#define BSP_NOCACHENOLOAD_SECTION __attribute__((section(".bsp_noload_nocache"))) + +#define BSP_NOCACHENOLOAD_SUBSECTION(subsection) \ + __attribute__((section(".bsp_noload_nocache." # subsection))) + +#define BSP_NVRAM_SECTION __attribute__((section(".bsp_nvram"))) + +#define BSP_NVRAM_SUBSECTION(subsection) \ + __attribute__((section(".bsp_nvram." # subsection))) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/powerpc/include/bsp/motorola.h b/bsps/powerpc/include/bsp/motorola.h new file mode 100644 index 0000000000..14360d56d1 --- /dev/null +++ b/bsps/powerpc/include/bsp/motorola.h @@ -0,0 +1,69 @@ +/* motorola.h + * + * This include file describe the data structure and the functions implemented + * by rtems to identify motorola boards. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SHARED_MOTOROLA_MOTOROLA_H +#define LIBBSP_POWERPC_SHARED_MOTOROLA_MOTOROLA_H + +#include +#include + +typedef enum { + PREP_IBM = 0, + PREP_Radstone = 1, + PREP_Motorola = 2 +} prep_t; + +typedef enum { + MVME_2400 = 0, + MVME_2400_750 = 1, + GENESIS = 2, + POWERSTACK_E = 3, + BLACKAWK = 4, + OMAHA = 5, + UTAH = 6, + POWERSTACK_EX = 7, + MESQUITE = 8, + SITKA = 9, + MESQUITE_W_HAC = 10, + MTX_PLUS = 11, + MTX_WO_PP = 12, + MTX_W_PP = 13, + MVME_2300 = 14, + MVME_2300SC_2600 = 15, + MVME_2600_W_MVME712M = 16, + MVME_2600_2700_W_MVME761 = 17, + MVME_3600_W_MVME712M = 18, + MVME_3600_W_MVME761 = 19, + MVME_1600 = 20, + /* In the table, slot 21 is the marker for end of automatic probe and scan */ + MVME_2100 = 22, + MOTOROLA_UNKNOWN = 255 +} motorolaBoard; + +typedef enum { + HOST_BRIDGE_RAVEN = 0, + HOST_BRIDGE_HAWK = 1, + HOST_BRIDGE_UNKNOWN = 255 +} motorolaHostBridge; + +#define MOTOROLA_CPUTYPE_REG 0x800 +#define MOTOROLA_BASETYPE_REG 0x803 + +extern prep_t checkPrepBoardType(RESIDUAL *res); +extern prep_t currentPrepType; +extern motorolaBoard getMotorolaBoard(void); +extern motorolaBoard currentBoard; +extern const char* motorolaBoardToString(motorolaBoard); +extern const struct _int_map *motorolaIntMap(motorolaBoard board); +extern const void *motorolaIntSwizzle(motorolaBoard board); + +#endif /* LIBBSP_POWERPC_SHARED_MOTOROLA_MOTOROLA_H */ diff --git a/bsps/powerpc/include/bsp/openpic.h b/bsps/powerpc/include/bsp/openpic.h new file mode 100644 index 0000000000..df782596b5 --- /dev/null +++ b/bsps/powerpc/include/bsp/openpic.h @@ -0,0 +1,378 @@ +/* + * openpic.h -- OpenPIC definitions + * + * Copyright (C) 1997 Geert Uytterhoeven + * + * This file is based on the following documentation: + * + * The Open Programmable Interrupt Controller (PIC) + * Register Interface Specification Revision 1.2 + * + * Issue Date: October 1995 + * + * Issued jointly by Advanced Micro Devices and Cyrix Corporation + * + * AMD is a registered trademark of Advanced Micro Devices, Inc. + * Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc. + * All Rights Reserved. + * + * To receive a copy of this documentation, send an email to openpic@amd.com. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * Modified to compile in RTEMS development environment + * by Eric Valette + * + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_OPENPIC_H +#define _RTEMS_OPENPIC_H + + /* + * OpenPIC supports up to 2048 interrupt sources and up to 32 processors + */ +#define OPENPIC_MAX_SOURCES 2048 +#define OPENPIC_MAX_PROCESSORS 32 + +#define OPENPIC_NUM_TIMERS 4 +#define OPENPIC_NUM_IPI 4 +#define OPENPIC_NUM_PRI 16 +#define OPENPIC_NUM_VECTORS 256 + + /* + * Vector numbers + */ + +#define OPENPIC_VEC_SOURCE 0x10 /* and up */ +#define OPENPIC_VEC_TIMER 0x40 /* and up */ +#define OPENPIC_VEC_IPI 0x50 /* and up */ +#define OPENPIC_VEC_SPURIOUS 99 + + /* + * OpenPIC Registers are 32 bits and aligned on 128 bit boundaries + */ + +typedef struct _OpenPIC_Reg { + unsigned int Reg; /* Little endian! */ + char Pad[0xc]; +} OpenPIC_Reg; + + /* + * Per Processor Registers + */ + +typedef struct _OpenPIC_Processor { + /* + * Private Shadow Registers (for SLiC backwards compatibility) + */ + unsigned int IPI0_Dispatch_Shadow; /* Write Only */ + char Pad1[0x4]; + unsigned int IPI0_Vector_Priority_Shadow; /* Read/Write */ + char Pad2[0x34]; + /* + * Interprocessor Interrupt Command Ports + */ + OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */ + /* + * Current Task Priority Register + */ + OpenPIC_Reg _Current_Task_Priority; /* Read/Write */ + char Pad3[0x10]; + /* + * Interrupt Acknowledge Register + */ + OpenPIC_Reg _Interrupt_Acknowledge; /* Read Only */ + /* + * End of Interrupt (EOI) Register + */ + OpenPIC_Reg _EOI; /* Read/Write */ + char Pad5[0xf40]; +} OpenPIC_Processor; + + /* + * Timer Registers + */ + +typedef struct _OpenPIC_Timer { + OpenPIC_Reg _Current_Count; /* Read Only */ + OpenPIC_Reg _Base_Count; /* Read/Write */ + OpenPIC_Reg _Vector_Priority; /* Read/Write */ + OpenPIC_Reg _Destination; /* Read/Write */ +} OpenPIC_Timer; + + /* + * Global Registers + */ + +typedef struct _OpenPIC_Global { + /* + * Feature Reporting Registers + */ + OpenPIC_Reg _Feature_Reporting0; /* Read Only */ + OpenPIC_Reg _Feature_Reporting1; /* Future Expansion */ + /* + * Global Configuration Registers + */ + OpenPIC_Reg _Global_Configuration0; /* Read/Write */ + OpenPIC_Reg _Global_Configuration1; /* Future Expansion */ + /* + * Vendor Specific Registers + */ + OpenPIC_Reg _Vendor_Specific[4]; + /* + * Vendor Identification Register + */ + OpenPIC_Reg _Vendor_Identification; /* Read Only */ + /* + * Processor Initialization Register + */ + OpenPIC_Reg _Processor_Initialization; /* Read/Write */ + /* + * IPI Vector/Priority Registers + */ + OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI]; /* Read/Write */ + /* + * Spurious Vector Register + */ + OpenPIC_Reg _Spurious_Vector; /* Read/Write */ + /* + * Global Timer Registers + */ + OpenPIC_Reg _Timer_Frequency; /* Read/Write */ + OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS]; + char Pad1[0xee00]; +} OpenPIC_Global; + + /* + * Interrupt Source Registers + */ + +typedef struct _OpenPIC_Source { + OpenPIC_Reg _Vector_Priority; /* Read/Write */ + OpenPIC_Reg _Destination; /* Read/Write */ +} OpenPIC_Source; + + /* + * OpenPIC Register Map + */ + +struct OpenPIC { + char Pad1[0x1000]; + /* + * Global Registers + */ + OpenPIC_Global Global; + /* + * Interrupt Source Configuration Registers + */ + OpenPIC_Source Source[OPENPIC_MAX_SOURCES]; + /* + * Per Processor Registers + */ + OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS]; +}; + +extern volatile struct OpenPIC *OpenPIC; + + /* + * Current Task Priority Register + */ + +#define OPENPIC_CURRENT_TASK_PRIORITY_MASK 0x0000000f + + /* + * Who Am I Register + */ + +#define OPENPIC_WHO_AM_I_ID_MASK 0x0000001f + + /* + * Feature Reporting Register 0 + */ + +#define OPENPIC_FEATURE_LAST_SOURCE_MASK 0x07ff0000 +#define OPENPIC_FEATURE_LAST_SOURCE_SHIFT 16 +#define OPENPIC_FEATURE_LAST_PROCESSOR_MASK 0x00001f00 +#define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT 8 +#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff + + /* + * Global Configuration Register 0 + */ + +#define OPENPIC_CONFIG_RESET 0x80000000 +#define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000 +#define OPENPIC_CONFIG_BASE_MASK 0x000fffff + + /* + * Vendor Identification Register + */ + +#define OPENPIC_VENDOR_ID_STEPPING_MASK 0x00ff0000 +#define OPENPIC_VENDOR_ID_STEPPING_SHIFT 16 +#define OPENPIC_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00 +#define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT 8 +#define OPENPIC_VENDOR_ID_VENDOR_ID_MASK 0x000000ff + + /* + * Vector/Priority Registers + */ + +#define OPENPIC_MASK 0x80000000 +#define OPENPIC_ACTIVITY 0x40000000 /* Read Only */ +#define OPENPIC_PRIORITY_MASK 0x000f0000 +#define OPENPIC_PRIORITY_SHIFT 16 +#define OPENPIC_VECTOR_MASK 0x000000ff + + /* + * Interrupt Source Registers + */ + +#define OPENPIC_SENSE_POLARITY 0x00800000 /* Undoc'd */ +#define OPENPIC_SENSE_LEVEL 0x00400000 + + /* + * Timer Registers + */ + +#define OPENPIC_COUNT_MASK 0x7fffffff +#define OPENPIC_TIMER_TOGGLE 0x80000000 +#define OPENPIC_TIMER_COUNT_INHIBIT 0x80000000 + + /* + * Aliases to make life simpler + */ + +/* Per Processor Registers */ +#define IPI_Dispatch(i) _IPI_Dispatch[i].Reg +#define Current_Task_Priority _Current_Task_Priority.Reg +#define Interrupt_Acknowledge _Interrupt_Acknowledge.Reg +#define EOI _EOI.Reg + +/* Global Registers */ +#define Feature_Reporting0 _Feature_Reporting0.Reg +#define Feature_Reporting1 _Feature_Reporting1.Reg +#define Global_Configuration0 _Global_Configuration0.Reg +#define Global_Configuration1 _Global_Configuration1.Reg +#define Vendor_Specific(i) _Vendor_Specific[i].Reg +#define Vendor_Identification _Vendor_Identification.Reg +#define Processor_Initialization _Processor_Initialization.Reg +#define IPI_Vector_Priority(i) _IPI_Vector_Priority[i].Reg +#define Spurious_Vector _Spurious_Vector.Reg +#define Timer_Frequency _Timer_Frequency.Reg + +/* Timer Registers */ +#define Current_Count _Current_Count.Reg +#define Base_Count _Base_Count.Reg +#define Vector_Priority _Vector_Priority.Reg +#define Destination _Destination.Reg + +/* Interrupt Source Registers */ +#define Vector_Priority _Vector_Priority.Reg +#define Destination _Destination.Reg + + /* + * Vendor and Device IDs + */ + +#define OPENPIC_VENDOR_ID_APPLE 0x14 +#define OPENPIC_DEVICE_ID_APPLE_HYDRA 0x46 + + /* + * OpenPIC Operations + */ + +/* + * Handle EPIC differences. Unfortunately, I don't know of an easy + * way to tell an EPIC from a normal PIC at run-time. Therefore, + * the BSP must enable a few quirks if it knows that an EPIC is being + * used: + * - If the BSP uses the serial interrupt mode / 'multiplexer' then + * EOI must be delayed by at least 16 SRAM_CLK cycles to avoid + * spurious interrupts. + * It is the BSP's responsibility to set up an appropriate delay + * (in timebase-clock cycles) at init time using + * 'openpic_set_eoi_delay()'. This is ONLY necessary when using + * an EPIC in serial mode. + * - The EPIC sources start at an offset of 16 in the register + * map, i.e., on an EPIC you'd say Sources[ x + 16 ] where + * on a PIC you would say Sources[ x ]. + * Again, the BSP can set an offset that is used by the + * calls dealing with 'Interrupt Sources' + * openpic_enable_irq() + * openpic_disable_irq() + * openpic_initirq() + * openpic_mapirq() + * openpic_set_sense() + * openpic_get_source_priority() + * openpic_set_source_priority() + * the desired source offset parameter is passed to openpic_init(). + * + * The routine 'openpic_set_eoi_delay()' returns the previous/old + * value of the delay parameter. + */ +extern unsigned openpic_set_eoi_delay(unsigned tb_cycles); + + +/* Global Operations */ + +/* num_sources: number of sources to use; if zero this value + * is read from the device, if nonzero the value read from + * the device is overridden. + * 'polarities' and 'senses' are arrays defining the desired + * polarities (active hi [nonzero]/lo [zero]) and + * senses (level [nonzero]/edge [zero]). + * Either of the two array pointers may be NULL resulting + * in the driver choosing default values of: 'active low' + * and 'level sensitive', respectively. + * NOTE: if you do pass arrays then their size must either + * match the number of sources read from the device or + * that value must be overridden by specifying + * a non-zero 'num_sources' parameter. + * + * Nonzero 'epic_freq' activates the EOI delay if the EPIC is + * configured in serial mode (driver assumes firmware performs initial + * EPIC setup). The BSP must pass the clock frequency of the EPIC + * serial interface here. + */ +extern void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses, int num_sources, int source_offset, unsigned long epic_freq); + +extern void openpic_reset(void); +extern void openpic_enable_8259_pass_through(void); +extern void openpic_disable_8259_pass_through(void); +extern unsigned int openpic_irq(unsigned int cpu); +extern void openpic_eoi(unsigned int cpu); +extern unsigned int openpic_get_priority(unsigned int cpu); +extern void openpic_set_priority(unsigned int cpu, unsigned int pri); +extern unsigned int openpic_get_spurious(void); +extern void openpic_set_spurious(unsigned int vector); +extern void openpic_init_processor(unsigned int cpumask); + +/* Interprocessor Interrupts */ +extern void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vector); +extern void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask); + +/* Timer Interrupts */ +extern void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vector); +extern void openpic_settimer(unsigned int timer, unsigned int base_count, int irq_enable); +extern unsigned int openpic_gettimer(unsigned int timer); +extern void openpic_maptimer(unsigned int timer, unsigned int cpumask); + +/* Interrupt Sources */ +extern void openpic_enable_irq(unsigned int irq); +extern int openpic_disable_irq(unsigned int irq); +extern void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vector, int polarity, + int is_level); +extern void openpic_mapirq(unsigned int irq, unsigned int cpumask); +extern void openpic_set_sense(unsigned int irq, int sense); +extern unsigned int openpic_get_source_priority(unsigned int irq); +extern void openpic_set_source_priority(unsigned int irq, unsigned int pri); + +#endif /* RTEMS_OPENPIC_H */ diff --git a/bsps/powerpc/include/bsp/pci.h b/bsps/powerpc/include/bsp/pci.h new file mode 100644 index 0000000000..42dc43875b --- /dev/null +++ b/bsps/powerpc/include/bsp/pci.h @@ -0,0 +1,84 @@ +/* + * PCI defines and function prototypes + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI BIOS Specification + * PCI Local Bus Specification + * PCI to PCI Bridge Specification + * PCI System Design Guide + */ + +/* + * Copyright 1994, Drew Eckhardt + * Copyright 1997, 1998 Martin Mares + */ + +#ifndef BSP_POWERPC_PCI_H +#define BSP_POWERPC_PCI_H + +#include +#include + +struct _pin_routes +{ + int pin; + int int_name[4]; +}; +struct _int_map +{ + int bus; + int slot; + int opts; + struct _pin_routes pin_route[5]; +}; + +/* If there's a conflict between a name in the routing table and + * what's already set on the device, reprogram the device setting + * to reflect int_name[0] for the routing table entry + */ +#define PCI_FIXUP_OPT_OVERRIDE_NAME (1<<0) + +/* + * This is assumed to be provided by the BSP. + */ +void detect_host_bridge(void); + +void FixupPCI( const struct _int_map *, int (*swizzler)(int,int) ); + +/* FIXME: This probably belongs into rtems/pci.h */ +extern unsigned char pci_bus_count(); + +/* FIXME: This also is generic and could go into rtems/pci.h */ + +/* Scan pci config space and run a user callback on each + * device present; the user callback may return 0 to + * continue the scan or a value > 0 to abort the scan. + * Return values < 0 are reserved and must not be used. + * + * RETURNS: a (opaque) handle pointing to the bus/slot/fn-triple + * just after where the scan was aborted by a callback + * returning 1 (see above) or NULL if all devices were + * scanned. + * The handle may be passed to this routine to resume the + * scan continuing with the device after the one causing the + * abort. + * Pass a NULL 'handle' argument to start scanning from + * the beginning (bus/slot/fn = 0/0/0). + */ +typedef void *BSP_PciScanHandle; +typedef int (*BSP_PciScannerCb)(int bus, int slot, int fun, void *uarg); + +BSP_PciScanHandle +BSP_pciScan(BSP_PciScanHandle handle, BSP_PciScannerCb cb, void *uarg); + +/* Dump basic config. space info to a file. The argument may + * be NULL in which case 'stdout' is used. + * NOTE: the C-library must be functional before you can use + * this routine. + */ +void +BSP_pciConfigDump(FILE *fp); + +#endif /* BSP_POWERPC_PCI_H */ diff --git a/bsps/powerpc/include/bsp/pnp.h b/bsps/powerpc/include/bsp/pnp.h new file mode 100644 index 0000000000..203a1a46d3 --- /dev/null +++ b/bsps/powerpc/include/bsp/pnp.h @@ -0,0 +1,644 @@ +/* 11/02/95 */ +/*----------------------------------------------------------------------------*/ +/* Plug and Play header definitions */ +/*----------------------------------------------------------------------------*/ + +/* Structure map for PnP on PowerPC Reference Platform */ +/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */ +/* (or later versions) is available on Compuserve in the PLUGPLAY area. */ +/* This code has extensions to that specification, namely new short and */ +/* long tag types for platform dependent information */ + +/* Warning: LE notation used throughout this file */ + +/* For enum's: if given in hex then they are bit significant, i.e. */ +/* only one bit is on for each enum */ + + +#ifndef _PNP_ +#define _PNP_ + +#ifndef ASM +#define MAX_MEM_REGISTERS 9 +#define MAX_IO_PORTS 20 +#define MAX_IRQS 7 +/*#define MAX_DMA_CHANNELS 7*/ + +/* Interrupt controllers */ + +#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */ +#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */ +#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */ +#define PNPinterrupt3 "PNP0003" /* APIC */ +#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */ + +/* Timers */ + +#define PNPtimer0 "PNP0100" /* AT Timer */ +#define PNPtimer1 "PNP0101" /* EISA Timer */ +#define PNPtimer2 "PNP0102" /* MCA Timer */ + +/* DMA controllers */ + +#define PNPdma0 "PNP0200" /* AT DMA Controller */ +#define PNPdma1 "PNP0201" /* EISA DMA Controller */ +#define PNPdma2 "PNP0202" /* MCA DMA Controller */ + +/* start of August 15, 1994 additions */ +/* CMOS */ +#define PNPCMOS "IBM0009" /* CMOS */ + +/* L2 Cache */ +#define PNPL2 "IBM0007" /* L2 Cache */ + +/* NVRAM */ +#define PNPNVRAM "IBM0008" /* NVRAM */ + +/* Power Management */ +#define PNPPM "IBM0005" /* Power Management */ +/* end of August 15, 1994 additions */ + +/* Keyboards */ + +#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */ +#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */ +#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */ +#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */ +#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */ +#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */ +#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */ +#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */ + +/* Parallel port controllers */ + +#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */ +#define PNPparallel1 "PNP0401" /* ECP Parallel Port */ +#define PNPepp "IBM001C" /* EPP Parallel Port */ + +/* Serial port controllers */ + +#define PNPserial0 "PNP0500" /* Standard PC Serial port */ +#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */ + +/* Disk controllers */ + +#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */ +#define PNPdisk1 "PNP0601" /* Plus Hardcard II */ +#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */ + +/* Diskette controllers */ + +#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */ + +/* Display controllers */ + +#define PNPdisplay0 "PNP0900" /* VGA Compatible */ +#define PNPdisplay1 "PNP0901" /* Video Seven VGA */ +#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */ +#define PNPdisplay3 "PNP0903" /* Trident VGA */ +#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */ +#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */ +#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */ +#define PNPdisplay7 "PNP0907" /* Western Digital VGA */ +#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */ +#define PNPdisplay9 "PNP0909" /* S3 */ +#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */ +#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */ +#define PNPdisplayC "PNP090C" /* XGA Compatible */ +#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */ +#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */ +#define PNPdisplayF "PNP090F" /* Oak Technology VGA */ + +/* Peripheral busses */ + +#define PNPbuses0 "PNP0A00" /* ISA Bus */ +#define PNPbuses1 "PNP0A01" /* EISA Bus */ +#define PNPbuses2 "PNP0A02" /* MCA Bus */ +#define PNPbuses3 "PNP0A03" /* PCI Bus */ +#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */ + +/* RTC, BIOS, planar devices */ + +#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */ +#define PNPrtc0 "PNP0B00" /* AT RTC */ +#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */ +#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */ +#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */ +#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */ + +/* PCMCIA controller */ + +#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */ + +/* Mice */ + +#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */ +#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */ +#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */ +#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */ +#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */ +#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */ +#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */ +#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */ +#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */ +#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */ +#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */ +#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */ + +/* Modems */ + +#define PNPmodem0 "PNP9000" /* Specific IDs TBD */ + +/* Network controllers */ + +#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */ +#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */ +#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */ +#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */ +#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */ +#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */ +#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */ +#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */ + +/* SCSI controllers */ + +#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */ +#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */ +#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/ +#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */ +#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */ +#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */ +#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */ + +/* Sound/Video, Multimedia */ + +#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */ +#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */ +#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */ +#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */ +#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */ +#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */ +#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */ +#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */ + +/* Operator Panel */ +#define PNPopctl "IBM000B" /* Operator's panel */ + +/* Service Processor */ +#define PNPsp "IBM0011" /* IBM Service Processor */ +#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */ +#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */ + +/* Memory Controller */ +#define PNPmemctl "IBM000A" /* Memory controller */ + +/* Graphics Assist */ +#define PNPg_assist "IBM0014" /* Graphics Assist */ + +/* Miscellaneous Device Controllers */ +#define PNPtablet "IBM0019" /* IBM Tablet Controller */ + +/* PNP Packet Handles */ + +#define S1_Packet 0x0A /* Version resource */ +#define S2_Packet 0x15 /* Logical DEVID (without flags) */ +#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */ +#define S3_Packet 0x1C /* Compatible device ID */ +#define S4_Packet 0x22 /* IRQ resource (without flags) */ +#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */ +#define S5_Packet 0x2A /* DMA resource */ +#define S6_Packet 0x30 /* Depend funct start (w/o priority) */ +#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */ +#define S7_Packet 0x38 /* Depend funct end */ +#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */ +#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */ +#define S14_Packet 0x71 /* Vendor defined */ +#define S15_Packet 0x78 /* End of resource (w/o checksum) */ +#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */ +#define L1_Packet 0x81 /* Memory range */ +#define L1_Shadow 0x20 /* Memory is shadowable */ +#define L1_32bit_mem 0x18 /* 32-bit memory only */ +#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */ +#define L1_Decode_Hi 0x04 /* decode supports high address */ +#define L1_Cache 0x02 /* read cacheable, write-through */ +#define L1_Writeable 0x01 /* Memory is writeable */ +#define L2_Packet 0x82 /* ANSI ID string */ +#define L3_Packet 0x83 /* Unicode ID string */ +#define L4_Packet 0x84 /* Vendor defined */ +#define L5_Packet 0x85 /* Large I/O */ +#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */ +#define END_TAG 0x78 /* End of resource */ +#define DF_START_TAG 0x30 /* Dependent function start */ +#define DF_START_TAG_priority 0x31 /* Dependent function start */ +#define DF_END_TAG 0x38 /* Dependent function end */ +#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */ + +/* Device Base Type Codes */ + +typedef enum _PnP_BASE_TYPE { + Reserved = 0, + MassStorageDevice = 1, + NetworkInterfaceController = 2, + DisplayController = 3, + MultimediaController = 4, + MemoryController = 5, + BridgeController = 6, + CommunicationsDevice = 7, + SystemPeripheral = 8, + InputDevice = 9, + ServiceProcessor = 0x0A, /* 11/2/95 */ + } PnP_BASE_TYPE; + +/* Device Sub Type Codes */ + +typedef enum _PnP_SUB_TYPE { + SCSIController = 0, + IDEController = 1, + FloppyController = 2, + IPIController = 3, + OtherMassStorageController = 0x80, + + EthernetController = 0, + TokenRingController = 1, + FDDIController = 2, + OtherNetworkController = 0x80, + + VGAController= 0, + SVGAController= 1, + XGAController= 2, + OtherDisplayController = 0x80, + + VideoController = 0, + AudioController = 1, + OtherMultimediaController = 0x80, + + RAM = 0, + FLASH = 1, + OtherMemoryDevice = 0x80, + + HostProcessorBridge = 0, + ISABridge = 1, + EISABridge = 2, + MicroChannelBridge = 3, + PCIBridge = 4, + PCMCIABridge = 5, + VMEBridge = 6, + OtherBridgeDevice = 0x80, + + RS232Device = 0, + ATCompatibleParallelPort = 1, + OtherCommunicationsDevice = 0x80, + + ProgrammableInterruptController = 0, + DMAController = 1, + SystemTimer = 2, + RealTimeClock = 3, + L2Cache = 4, + NVRAM = 5, + PowerManagement = 6, + CMOS = 7, + OperatorPanel = 8, + ServiceProcessorClass1 = 9, + ServiceProcessorClass2 = 0xA, + ServiceProcessorClass3 = 0xB, + GraphicAssist = 0xC, + SystemPlanar = 0xF, /* 10/5/95 */ + OtherSystemPeripheral = 0x80, + + KeyboardController = 0, + Digitizer = 1, + MouseController = 2, + TabletController = 3, /* 10/27/95 */ + OtherInputController = 0x80, + + GeneralMemoryController = 0, + } PnP_SUB_TYPE; + +/* Device Interface Type Codes */ + +typedef enum _PnP_INTERFACE { + General = 0, + GeneralSCSI = 0, + GeneralIDE = 0, + ATACompatible = 1, + + GeneralFloppy = 0, + Compatible765 = 1, + NS398_Floppy = 2, /* NS Super I/O wired to use index + register at port 398 and data + register at port 399 */ + NS26E_Floppy = 3, /* Ports 26E and 26F */ + NS15C_Floppy = 4, /* Ports 15C and 15D */ + NS2E_Floppy = 5, /* Ports 2E and 2F */ + CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */ + + GeneralIPI = 0, + + GeneralEther = 0, + GeneralToken = 0, + GeneralFDDI = 0, + + GeneralVGA = 0, + GeneralSVGA = 0, + GeneralXGA = 0, + + GeneralVideo = 0, + GeneralAudio = 0, + CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */ + + GeneralRAM = 0, + GeneralFLASH = 0, + PCIMemoryController = 0, /* PCI Config Method */ + RS6KMemoryController = 1, /* RS6K Config Method */ + + GeneralHostBridge = 0, + GeneralISABridge = 0, + GeneralEISABridge = 0, + GeneralMCABridge = 0, + GeneralPCIBridge = 0, + PCIBridgeDirect = 0, + PCIBridgeIndirect = 1, + PCIBridgeRS6K = 2, + GeneralPCMCIABridge = 0, + GeneralVMEBridge = 0, + + GeneralRS232 = 0, + COMx = 1, + Compatible16450 = 2, + Compatible16550 = 3, + NS398SerPort = 4, /* NS Super I/O wired to use index + register at port 398 and data + register at port 399 */ + NS26ESerPort = 5, /* Ports 26E and 26F */ + NS15CSerPort = 6, /* Ports 15C and 15D */ + NS2ESerPort = 7, /* Ports 2E and 2F */ + + GeneralParPort = 0, + LPTx = 1, + NS398ParPort = 2, /* NS Super I/O wired to use index + register at port 398 and data + register at port 399 */ + NS26EParPort = 3, /* Ports 26E and 26F */ + NS15CParPort = 4, /* Ports 15C and 15D */ + NS2EParPort = 5, /* Ports 2E and 2F */ + + GeneralPIC = 0, + ISA_PIC = 1, + EISA_PIC = 2, + MPIC = 3, + RS6K_PIC = 4, + + GeneralDMA = 0, + ISA_DMA = 1, + EISA_DMA = 2, + + GeneralTimer = 0, + ISA_Timer = 1, + EISA_Timer = 2, + GeneralRTC = 0, + ISA_RTC = 1, + + StoreThruOnly = 1, + StoreInEnabled = 2, + RS6KL2Cache = 3, + + IndirectNVRAM = 0, /* Indirectly addressed */ + DirectNVRAM = 1, /* Memory Mapped */ + IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */ + + GeneralPowerManagement = 0, + EPOWPowerManagement = 1, + PowerControl = 2, /* d1378 */ + + GeneralCMOS = 0, + + GeneralOPPanel = 0, + HarddiskLight = 1, + CDROMLight = 2, + PowerLight = 3, + KeyLock = 4, + ANDisplay = 5, /* AlphaNumeric Display */ + SystemStatusLED = 6, /* 3 digit 7 segment LED */ + CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */ + + GeneralServiceProcessor = 0, + + TransferData = 1, + IGMC32 = 2, + IGMC64 = 3, + + GeneralSystemPlanar = 0, /* 10/5/95 */ + + } PnP_INTERFACE; + +/* PnP resources */ + +/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */ + +typedef struct _SERIAL_ID { + unsigned char VendorID0; /* Bit(7)=0 */ + /* Bits(6:2)=1st character in */ + /* compressed ASCII */ + /* Bits(1:0)=2nd character in */ + /* compressed ASCII bits(4:3) */ + unsigned char VendorID1; /* Bits(7:5)=2nd character in */ + /* compressed ASCII bits(2:0) */ + /* Bits(4:0)=3rd character in */ + /* compressed ASCII */ + unsigned char VendorID2; /* Product number - vendor assigned */ + unsigned char VendorID3; /* Product number - vendor assigned */ + +/* Serial number is to provide uniqueness if more than one board of same */ +/* type is in system. Must be "FFFFFFFF" if feature not supported. */ + + unsigned char Serial0; /* Unique serial number bits (7:0) */ + unsigned char Serial1; /* Unique serial number bits (15:8) */ + unsigned char Serial2; /* Unique serial number bits (23:16) */ + unsigned char Serial3; /* Unique serial number bits (31:24) */ + unsigned char Checksum; + } SERIAL_ID; + +typedef enum _PnPItemName { + Unused = 0, + PnPVersion = 1, + LogicalDevice = 2, + CompatibleDevice = 3, + IRQFormat = 4, + DMAFormat = 5, + StartDepFunc = 6, + EndDepFunc = 7, + IOPort = 8, + FixedIOPort = 9, + Res1 = 10, + Res2 = 11, + Res3 = 12, + SmallVendorItem = 14, + EndTag = 15, + MemoryRange = 1, + ANSIIdentifier = 2, + UnicodeIdentifier = 3, + LargeVendorItem = 4, + MemoryRange32 = 5, + MemoryRangeFixed32 = 6, + } PnPItemName; + +/* Define a bunch of access functions for the bits in the tag field */ + +/* Tag type - 0 = small; 1 = large */ +#define tag_type(t) (((t) & 0x80)>>7) +#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7)) + +/* Small item name is 4 bits - one of PnPItemName enum above */ +#define tag_small_item_name(t) (((t) & 0x78)>>3) +#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3)) + +/* Small item count is 3 bits - count of further bytes in packet */ +#define tag_small_count(t) ((t) & 0x07) +#define set_tag_count(t,v) (t = (t & 0x78) | (v)) + +/* Large item name is 7 bits - one of PnPItemName enum above */ +#define tag_large_item_name(t) ((t) & 0x7f) +#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v)) + +/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */ + +typedef union _PnP_TAG_PACKET { + struct _S1_Pack{ /* VERSION PACKET */ + unsigned char Tag; /* small tag = 0x0a */ + unsigned char Version[2]; /* PnP version, Vendor version */ + } S1_Pack; + + struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */ + unsigned char Tag; /* small tag = 0x15 or 0x16 */ + unsigned char DevId[4]; /* Logical device id */ + unsigned char Flags[2]; /* bit(0) boot device; */ + /* bit(7:1) cmd in range x31-x37 */ + /* bit(7:0) cmd in range x28-x3f (opt)*/ + } S2_Pack; + + struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ + unsigned char Tag; /* small tag = 0x1c */ + unsigned char CompatId[4]; /* Compatible device id */ + } S3_Pack; + + struct _S4_Pack{ /* IRQ PACKET */ + unsigned char Tag; /* small tag = 0x22 or 0x23 */ + unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ + /* bit(0) is IRQ8 ... */ + unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ + /* bit(0) - high true edge sensitive */ + /* bit(1) - low true edge sensitive */ + /* bit(2) - high true level sensitive*/ + /* bit(3) - low true level sensitive */ + /* bit(7:4) - must be 0 */ + } S4_Pack; + + struct _S5_Pack{ /* DMA PACKET */ + unsigned char Tag; /* small tag = 0x2a */ + unsigned char DMAMask; /* bit(0) is channel 0 ... */ + unsigned char DMAInfo; + } S5_Pack; + + struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ + unsigned char Tag; /* small tag = 0x30 or 0x31 */ + unsigned char Priority; /* Optional; if missing then x01; else*/ + /* x00 = best possible */ + /* x01 = acceptible */ + /* x02 = sub-optimal but functional */ + } S6_Pack; + + struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ + unsigned char Tag; /* small tag = 0x38 */ + } S7_Pack; + + struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */ + unsigned char Tag; /* small tag x47 */ + unsigned char IOInfo; /* x0 = decode only bits(9:0); */ +#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */ + unsigned char RangeMin[2]; /* Min base address */ + unsigned char RangeMax[2]; /* Max base address */ + unsigned char IOAlign; /* base alignmt, incr in 1B blocks */ + unsigned char IONum; /* number of contiguous I/O ports */ + } S8_Pack; + + struct _S9_Pack{ /* FIXED I/O PORT PACKET */ + unsigned char Tag; /* small tag = 0x4b */ + unsigned char Range[2]; /* base address 10 bits */ + unsigned char IONum; /* number of contiguous I/O ports */ + } S9_Pack; + + struct _S14_Pack{ /* VENDOR DEFINED PACKET */ + unsigned char Tag; /* small tag = 0x7m m = 1-7 */ + union _S14_Data{ + unsigned char Data[7]; /* Vendor defined */ + struct _S14_PPCPack{ /* Pr*p s14 pack */ + unsigned char Type; /* 00=non-IBM */ + unsigned char PPCData[6]; /* Vendor defined */ + } S14_PPCPack; + } S14_Data; + } S14_Pack; + + struct _S15_Pack{ /* END PACKET */ + unsigned char Tag; /* small tag = 0x78 or 0x79 */ + unsigned char Check; /* optional - checksum */ + } S15_Pack; + + struct _L1_Pack{ /* MEMORY RANGE PACKET */ + unsigned char Tag; /* large tag = 0x81 */ + unsigned char Count0; /* x09 */ + unsigned char Count1; /* x00 */ + unsigned char Data[9]; /* a variable array of bytes, */ + /* count in tag */ + } L1_Pack; + + struct _L2_Pack{ /* ANSI ID STRING PACKET */ + unsigned char Tag; /* large tag = 0x82 */ + unsigned char Count0; /* Length of string */ + unsigned char Count1; + unsigned char Identifier[1]; /* a variable array of bytes, */ + /* count in tag */ + } L2_Pack; + + struct _L3_Pack{ /* UNICODE ID STRING PACKET */ + unsigned char Tag; /* large tag = 0x83 */ + unsigned char Count0; /* Length + 2 of string */ + unsigned char Count1; + unsigned char Country0; /* TBD */ + unsigned char Country1; /* TBD */ + unsigned char Identifier[1]; /* a variable array of bytes, */ + /* count in tag */ + } L3_Pack; + + struct _L4_Pack{ /* VENDOR DEFINED PACKET */ + unsigned char Tag; /* large tag = 0x84 */ + unsigned char Count0; + unsigned char Count1; + union _L4_Data{ + unsigned char Data[1]; /* a variable array of bytes, */ + /* count in tag */ + struct _L4_PPCPack{ /* Pr*p L4 packet */ + unsigned char Type; /* 00=non-IBM */ + unsigned char PPCData[1]; /* a variable array of bytes, */ + /* count in tag */ + } L4_PPCPack; + } L4_Data; + } L4_Pack; + + struct _L5_Pack{ + unsigned char Tag; /* large tag = 0x85 */ + unsigned char Count0; /* Count = 17 */ + unsigned char Count1; + unsigned char Data[17]; + } L5_Pack; + + struct _L6_Pack{ + unsigned char Tag; /* large tag = 0x86 */ + unsigned char Count0; /* Count = 9 */ + unsigned char Count1; + unsigned char Data[9]; + } L6_Pack; + + } PnP_TAG_PACKET; + +#endif /* ASM */ +#endif /* ndef _PNP_ */ diff --git a/bsps/powerpc/include/bsp/residual.h b/bsps/powerpc/include/bsp/residual.h new file mode 100644 index 0000000000..1bf1a34e20 --- /dev/null +++ b/bsps/powerpc/include/bsp/residual.h @@ -0,0 +1,356 @@ +/* 7/18/95 */ +/*----------------------------------------------------------------------------*/ +/* Residual Data header definitions and prototypes */ +/*----------------------------------------------------------------------------*/ + +/* Structure map for RESIDUAL on PowerPC Reference Platform */ +/* residual.h - Residual data structure passed in r3. */ +/* Load point passed in r4 to boot image. */ +/* For enum's: if given in hex then they are bit significant, */ +/* i.e. only one bit is on for each enum */ +/* Reserved fields must be filled with zeros. */ + + +#ifndef _RESIDUAL_ +#define _RESIDUAL_ + +#ifndef ASM + +#include + +#define MAX_CPUS 32 /* These should be set to the maximum */ +#define MAX_MEMS 64 /* number possible for this system. */ +#define MAX_DEVICES 256 /* Changing these will change the */ +#define AVE_PNP_SIZE 32 /* structure, hence the version of */ +#define MAX_MEM_SEGS 64 /* this header file. */ + +/*----------------------------------------------------------------------------*/ +/* Public structures... */ +/*----------------------------------------------------------------------------*/ + +#include + +typedef enum _L1CACHE_TYPE { + NoneCAC = 0, + SplitCAC = 1, + CombinedCAC = 2 + } L1CACHE_TYPE; + +typedef enum _TLB_TYPE { + NoneTLB = 0, + SplitTLB = 1, + CombinedTLB = 2 + } TLB_TYPE; + +typedef enum _FIRMWARE_SUPPORT { + Conventional = 0x01, + OpenFirmware = 0x02, + Diagnostics = 0x04, + LowDebug = 0x08, + Multiboot = 0x10, + LowClient = 0x20, + Hex41 = 0x40, + FAT = 0x80, + ISO9660 = 0x0100, + SCSI_InitiatorID_Override = 0x0200, + Tape_Boot = 0x0400, + FW_Boot_Path = 0x0800 + } FIRMWARE_SUPPORT; + +typedef enum _FIRMWARE_SUPPLIERS { + IBMFirmware = 0x00, + MotoFirmware = 0x01, /* 7/18/95 */ + FirmWorks = 0x02, /* 10/5/95 */ + Bull = 0x03, /* 04/03/96 */ + QEMU = ('q'<<24) | ('e'<<16) | ('m'<<8) | ('u'<<0), + } FIRMWARE_SUPPLIERS; + +typedef enum _ENDIAN_SWITCH_METHODS { + UsePort92 = 0x01, + UsePCIConfigA8 = 0x02, + UseFF001030 = 0x03, + } ENDIAN_SWITCH_METHODS; + +typedef enum _SPREAD_IO_METHODS { + UsePort850 = 0x00, +/*UsePCIConfigA8 = 0x02,*/ + } SPREAD_IO_METHODS; + +typedef struct _VPD { + + /* Box dependent stuff */ + unsigned char PrintableModel[32]; /* Null terminated string. + Must be of the form: + vvv,<20h>,,<0x0> + where vvv is the vendor ID + e.g. IBM PPS MODEL 6015<0x0> */ + unsigned char Serial[16]; /* 12/94: + Serial Number; must be of the form: + vvv where vvv is the + vendor ID. + e.g. IBM60151234567<20h><20h> */ + unsigned char Reserved[48]; + unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */ + unsigned long FirmwareSupports; /* See FirmwareSupport enum */ + unsigned long NvramSize; /* Size of nvram in bytes */ + unsigned long NumSIMMSlots; + unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */ + unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */ + unsigned long SmpIar; + unsigned long RAMErrLogOffset; /* Heap offset to error log */ + unsigned long Reserved5; + unsigned long Reserved6; + unsigned long ProcessorHz; /* Processor clock frequency in Hertz */ + unsigned long ProcessorBusHz; /* Processor bus clock frequency */ + unsigned long Reserved7; + unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */ + unsigned long WordWidth; /* Word width in bits */ + unsigned long PageSize; /* Page size in bytes */ + unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache + for which coherency is maintained; + normally <= CacheLineSize. */ + unsigned long GranuleSize; /* Unit of lock allocation to avoid */ + /* false sharing of locks. */ + + /* L1 Cache variables */ + unsigned long CacheSize; /* L1 Cache size in KB. This is the */ + /* total size of the L1, whether */ + /* combined or split */ + unsigned long CacheAttrib; /* L1CACHE_TYPE */ + unsigned long CacheAssoc; /* L1 Cache associativity. Use this + for combined cache. If split, put + zeros here. */ + unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use + for combined cache. If split, put + zeros here. */ + /* For split L1 Cache: (= combined if combined cache) */ + unsigned long I_CacheSize; + unsigned long I_CacheAssoc; + unsigned long I_CacheLineSize; + unsigned long D_CacheSize; + unsigned long D_CacheAssoc; + unsigned long D_CacheLineSize; + + /* Translation Lookaside Buffer variables */ + unsigned long TLBSize; /* Total number of TLBs on the system */ + unsigned long TLBAttrib; /* Combined I+D or split TLB */ + unsigned long TLBAssoc; /* TLB Associativity. Use this for + combined TLB. If split, put zeros + here. */ + /* For split TLB: (= combined if combined TLB) */ + unsigned long I_TLBSize; + unsigned long I_TLBAssoc; + unsigned long D_TLBSize; + unsigned long D_TLBAssoc; + + unsigned long ExtendedVPD; /* Offset to extended VPD area; + null if unused */ + } VPD; + +typedef enum _DEVICE_FLAGS { + Enabled = 0x4000, /* 1 - PCI device is enabled */ + Integrated = 0x2000, + Failed = 0x1000, /* 1 - device failed POST code tests */ + Static = 0x0800, /* 0 - dynamically configurable + 1 - static */ + Dock = 0x0400, /* 0 - not a docking station device + 1 - is a docking station device */ + Boot = 0x0200, /* 0 - device cannot be used for BOOT + 1 - can be a BOOT device */ + Configurable = 0x0100, /* 1 - device is configurable */ + Disableable = 0x80, /* 1 - device can be disabled */ + PowerManaged = 0x40, /* 0 - not managed; 1 - managed */ + ReadOnly = 0x20, /* 1 - device is read only */ + Removable = 0x10, /* 1 - device is removable */ + ConsoleIn = 0x08, + ConsoleOut = 0x04, + Input = 0x02, + Output = 0x01 + } DEVICE_FLAGS; + +typedef enum _BUS_ID { + ISADEVICE = 0x01, + EISADEVICE = 0x02, + PCIDEVICE = 0x04, + PCMCIADEVICE = 0x08, + PNPISADEVICE = 0x10, + MCADEVICE = 0x20, + MXDEVICE = 0x40, /* Devices on mezzanine bus */ + PROCESSORDEVICE = 0x80, /* Devices on processor bus */ + VMEDEVICE = 0x100, + } BUS_ID; + +typedef struct _DEVICE_ID { + unsigned long BusId; /* See BUS_ID enum above */ + unsigned long DevId; /* Big Endian format */ + unsigned long SerialNum; /* For multiple usage of a single + DevId */ + unsigned long Flags; /* See DEVICE_FLAGS enum above */ + unsigned char BaseType; /* See pnp.h for bit definitions */ + unsigned char SubType; /* See pnp.h for bit definitions */ + unsigned char Interface; /* See pnp.h for bit definitions */ + unsigned char Spare; + } DEVICE_ID; + +typedef union _BUS_ACCESS { + struct _PnPAccess{ + unsigned char CSN; + unsigned char LogicalDevNumber; + unsigned short ReadDataPort; + } PnPAccess; + struct _ISAAccess{ + unsigned char SlotNumber; /* ISA Slot Number generally not + available; 0 if unknown */ + unsigned char LogicalDevNumber; + unsigned short ISAReserved; + } ISAAccess; + struct _MCAAccess{ + unsigned char SlotNumber; + unsigned char LogicalDevNumber; + unsigned short MCAReserved; + } MCAAccess; + struct _PCMCIAAccess{ + unsigned char SlotNumber; + unsigned char LogicalDevNumber; + unsigned short PCMCIAReserved; + } PCMCIAAccess; + struct _EISAAccess{ + unsigned char SlotNumber; + unsigned char FunctionNumber; + unsigned short EISAReserved; + } EISAAccess; + struct _PCIAccess{ + unsigned char BusNumber; + unsigned char DevFuncNumber; + unsigned short PCIReserved; + } PCIAccess; + struct _ProcBusAccess{ + unsigned char BusNumber; + unsigned char BUID; + unsigned short ProcBusReserved; + } ProcBusAccess; + } BUS_ACCESS; + +/* Per logical device information */ +typedef struct _PPC_DEVICE { + DEVICE_ID DeviceId; + BUS_ACCESS BusAccess; + + /* The following three are offsets into the DevicePnPHeap */ + /* All are in PnP compressed format */ + unsigned long AllocatedOffset; /* Allocated resource description */ + unsigned long PossibleOffset; /* Possible resource description */ + unsigned long CompatibleOffset; /* Compatible device identifiers */ + } PPC_DEVICE; + +typedef enum _CPU_STATE { + CPU_GOOD = 0, /* CPU is present, and active */ + CPU_GOOD_FW = 1, /* CPU is present, and in firmware */ + CPU_OFF = 2, /* CPU is present, but inactive */ + CPU_FAILED = 3, /* CPU is present, but failed POST */ + CPU_NOT_PRESENT = 255 /* CPU not present */ + } CPU_STATE; + +typedef struct _PPC_CPU { + unsigned long CpuType; /* Result of mfspr from Processor + Version Register (PVR). + PVR(0-15) = Version (e.g. 601) + PVR(16-31 = EC Level */ + unsigned char CpuNumber; /* CPU Number for this processor */ + unsigned char CpuState; /* CPU State, see CPU_STATE enum */ + unsigned short Reserved; + } PPC_CPU; + +typedef struct _PPC_MEM { + unsigned long SIMMSize; /* 0 - absent or bad + 8M, 32M (in MB) */ + } PPC_MEM; + +typedef enum _MEM_USAGE { + Other = 0x8000, + ResumeBlock = 0x4000, /* for use by power management */ + SystemROM = 0x2000, /* Flash memory (populated) */ + UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */ + IOMemory = 0x0800, + SystemIO = 0x0400, + SystemRegs = 0x0200, + PCIAddr = 0x0100, + PCIConfig = 0x80, + ISAAddr = 0x40, + Unpopulated = 0x20, /* Unpopulated part of System Memory */ + Free = 0x10, /* Free part of System Memory */ + BootImage = 0x08, /* BootImage part of System Memory */ + FirmwareCode = 0x04, /* FirmwareCode part of System Memory */ + FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */ + FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/ + } MEM_USAGE; + +typedef struct _MEM_MAP { + unsigned long Usage; /* See MEM_USAGE above */ + unsigned long BasePage; /* Page number measured in 4KB pages */ + unsigned long PageCount; /* Page count measured in 4KB pages */ + } MEM_MAP; + +typedef struct _RESIDUAL { + unsigned long ResidualLength; /* Length of Residual */ + unsigned char Version; /* of this data structure */ + unsigned char Revision; /* of this data structure */ + unsigned short EC; /* of this data structure */ + /* VPD */ + VPD VitalProductData; + /* CPU */ + unsigned short MaxNumCpus; /* Max CPUs in this system */ + unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */ + /* that there are unpopulated or */ + /* otherwise unusable cpu locations */ + PPC_CPU Cpus[MAX_CPUS]; + /* Memory */ + unsigned long TotalMemory; /* Total amount of memory installed */ + unsigned long GoodMemory; /* Total amount of good memory */ + unsigned long ActualNumMemSegs; + MEM_MAP Segs[MAX_MEM_SEGS]; + unsigned long ActualNumMemories; + PPC_MEM Memories[MAX_MEMS]; + /* Devices */ + unsigned long ActualNumDevices; + PPC_DEVICE Devices[MAX_DEVICES]; + unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE]; + } RESIDUAL; + +#ifndef NULL +#define NULL 0 +#endif + +static inline int +residual_fw_is_qemu(RESIDUAL *r) +{ + return QEMU == r->VitalProductData.FirmwareSupplier; +} + +extern RESIDUAL residualCopy; + +extern void print_residual_device_info(void); +#ifndef __BOOT__ +extern PPC_DEVICE *residual_find_device(RESIDUAL *res, unsigned long BusMask, + unsigned char * DevID, int BaseType, + int SubType, int Interface, int n); +#else +extern PPC_DEVICE *residual_find_device(unsigned long BusMask, + unsigned char * DevID, int BaseType, + int SubType, int Interface, int n); +#endif +extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag, + int n); +extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, + unsigned packet_type, + int n); +extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, + unsigned packet_type, + int n); +/* + * Prototypes for methods called only from .S for dependency tracking + */ +uint32_t res_copy(void); + +#endif /* ASM */ +#endif /* ndef _RESIDUAL_ */ diff --git a/bsps/powerpc/include/bsp/start.h b/bsps/powerpc/include/bsp/start.h new file mode 100644 index 0000000000..ab718a87ee --- /dev/null +++ b/bsps/powerpc/include/bsp/start.h @@ -0,0 +1,84 @@ +/** + * @file + * + * @ingroup powerpc_start + * + * @brief System low level start. + */ + +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SHARED_START_H +#define LIBBSP_POWERPC_SHARED_START_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup powerpc_start PowerPC System Start + * + * @ingroup powerpc_shared + * + * @brief PowerPC low level start. + * + * @{ + */ + +#define BSP_START_TEXT_SECTION __attribute__((section(".bsp_start_text"))) + +#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data"))) + +/** +* @brief System start entry. +*/ +void _start(void); + +/** + * Zeros @a byte_count bytes starting at @a begin. + * + * It wraps around in case of an address overflow. The stack will not be used. + * The code is position independent. It uses the data cache block zero + * instruction in case the data cache is enabled. There are no alignment + * constains for @a begin and @a byte_count. + * + * @see bsp_start_zero_begin, bsp_start_zero_end, and bsp_start_zero_size. + */ +void BSP_START_TEXT_SECTION bsp_start_zero(void *begin, size_t byte_count); + +/** + * @brief Symbol which equals the bsp_start_zero() code begin. + */ +extern char bsp_start_zero_begin []; + +/** + * @brief Symbol which equals the bsp_start_zero() code end. + */ +extern char bsp_start_zero_end []; + +/** + * @brief Symbol which equals the bsp_start_zero() code size. + */ +extern char bsp_start_zero_size []; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_SHARED_START_H */ diff --git a/bsps/powerpc/include/bsp/tictac.h b/bsps/powerpc/include/bsp/tictac.h new file mode 100644 index 0000000000..31c7386943 --- /dev/null +++ b/bsps/powerpc/include/bsp/tictac.h @@ -0,0 +1,78 @@ +/** + * @file + * + * @ingroup powerpc_shared + * + * @brief Header file for tic-tac code. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @brief Reset reference ticks for tac(). + */ +static inline void tic() +{ + uint32_t tmp; + asm volatile ( + "mftb 0;" + "stw 0, ppc_tic_tac@sdarel(13);" + : "=r" (tmp) + ); +} + +/** + * @brief Returns number of ticks since last tic(). + */ +static inline uint32_t tac() +{ + uint32_t ticks; + uint32_t tmp; + asm volatile ( + "mftb %0;" + "lwz %1, ppc_tic_tac@sdarel(13);" + "subf %0, %1, %0;" + : "=r" (ticks), "=r" (tmp) + ); + return ticks; +} + +/** + * @brief Reset reference ticks for bam(). + */ +static inline void boom() +{ + uint32_t tmp; + asm volatile ( + "mftb 0;" + "stw 0, ppc_boom_bam@sdarel(13);" + : "=r" (tmp) + ); +} + +/** + * @brief Returns number of ticks since last boom(). + */ +static inline uint32_t bam() +{ + uint32_t ticks; + uint32_t tmp; + asm volatile ( + "mftb %0;" + "lwz %1, ppc_boom_bam@sdarel(13);" + "subf %0, %1, %0;" + : "=r" (ticks), "=r" (tmp) + ); + return ticks; +} diff --git a/bsps/powerpc/include/bsp/tsec.h b/bsps/powerpc/include/bsp/tsec.h new file mode 100644 index 0000000000..4efbfa2ab0 --- /dev/null +++ b/bsps/powerpc/include/bsp/tsec.h @@ -0,0 +1,380 @@ +/*===============================================================*\ +| Project: RTEMS support for MPC83xx | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares the MPC83xx TSEC networking driver | +\*===============================================================*/ + +#ifndef LIBCPU_POWERPC_TSEC_H +#define LIBCPU_POWERPC_TSEC_H + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + /* + * this enumeration defines the index + * of a given rmon mib counter + * in the tsec_rmon_mib array + */ +typedef enum { + /* TSEC1 Transmit and Receive Counters */ + TSEC_RMON_TR64, /* 0x2_4680 Transmit and receive 64-byte frame counter register R/W 0x0000_0000 15.5.3.7.1/15-60 */ + TSEC_RMON_TR127, /* 0x2_4684 Transmit and receive 65- to 127-byte frame counter register R/W 0x0000_0000 15.5.3.7.2/15-61 */ + TSEC_RMON_TR255, /* 0x2_4688 Transmit and receive 128- to 255-byte frame counter register R/W 0x0000_0000 15.5.3.7.3/15-61 */ + TSEC_RMON_TR511, /* 0x2_468C Transmit and receive 256- to 511-byte frame counter register R/W 0x0000_0000 15.5.3.7.4/15-62 */ + TSEC_RMON_TR1K, /* 0x2_4690 Transmit and receive 512- to 1023-byte frame counter register R/W 0x0000_0000 15.5.3.7.5/15-62 */ + TSEC_RMON_TRMAX, /* 0x2_4694 Transmit and receive 1024- to 1518-byte frame counter register R/W 0x0000_0000 15.5.3.7.6/15-63 */ + TSEC_RMON_TRMGV, /* 0x2_4698 Transmit and receive 1519- to 1522-byte good VLAN frame count register R/W 0x0000_0000 15.5.3.7.7/15-63 */ + /* TSEC1 Receive Counters */ + TSEC_RMON_RBYT, /* 0x2_469C Receive byte counter register R/W 0x0000_0000 15.5.3.7.8/15-64 */ + TSEC_RMON_RPKT, /* 0x2_46A0 Receive packet counter register R/W 0x0000_0000 15.5.3.7.9/15-64 */ + TSEC_RMON_RFCS, /* 0x2_46A4 Receive FCS error counter register R/W 0x0000_0000 15.5.3.7.10/15-65 */ + TSEC_RMON_RMCA, /* 0x2_46A8 Receive multicast packet counter register R/W 0x0000_0000 15.5.3.7.11/15-65 */ + TSEC_RMON_RBCA, /* 0x2_46AC Receive broadcast packet counter register R/W 0x0000_0000 15.5.3.7.12/15-66 */ + TSEC_RMON_RXCF, /* 0x2_46B0 Receive control frame packet counter register R/W 0x0000_0000 15.5.3.7.13/15-66 */ + TSEC_RMON_RXPF, /* 0x2_46B4 Receive PAUSE frame packet counter register R/W 0x0000_0000 15.5.3.7.14/15-67 */ + TSEC_RMON_RXUO, /* 0x2_46B8 Receive unknown OP code counter register R/W 0x0000_0000 15.5.3.7.15/15-67 */ + TSEC_RMON_RALN, /* 0x2_46BC Receive alignment error counter register R/W 0x0000_0000 15.5.3.7.16/15-68 */ + TSEC_RMON_RFLR, /* 0x2_46C0 Receive frame length error counter register R/W 0x0000_0000 15.5.3.7.17/15-68 */ + TSEC_RMON_RCDE, /* 0x2_46C4 Receive code error counter register R/W 0x0000_0000 15.5.3.7.18/15-69 */ + TSEC_RMON_RCSE, /* 0x2_46C8 Receive carrier sense error counter register R/W 0x0000_0000 15.5.3.7.19/15-69 */ + TSEC_RMON_RUND, /* 0x2_46CC Receive undersize packet counter register R/W 0x0000_0000 15.5.3.7.20/15-70 */ + TSEC_RMON_ROVR, /* 0x2_46D0 Receive oversize packet counter register R/W 0x0000_0000 15.5.3.7.21/15-70 */ + TSEC_RMON_RFRG, /* 0x2_46D4 Receive fragments counter register R/W 0x0000_0000 15.5.3.7.22/15-71 */ + TSEC_RMON_RJBR, /* 0x2_46D8 Receive jabber counter register R/W 0x0000_0000 15.5.3.7.23/15-71 */ + TSEC_RMON_RDRP, /* 0x2_46DC Receive drop register R/W 0x0000_0000 15.5.3.7.24/15-72 */ + /* TSEC1 Transmit Counters */ + TSEC_RMON_TBYT, /* 0x2_46E0 Transmit byte counter register R/W 0x0000_0000 15.5.3.7.25/15-72 */ + TSEC_RMON_TPKT, /* 0x2_46E4 Transmit packet counter register R/W 0x0000_0000 15.5.3.7.26/15-73 */ + TSEC_RMON_TMCA, /* 0x2_46E8 Transmit multicast packet counter register R/W 0x0000_0000 15.5.3.7.27/15-73 */ + TSEC_RMON_TBCA, /* 0x2_46EC Transmit broadcast packet counter register R/W 0x0000_0000 15.5.3.7.28/15-74 */ + TSEC_RMON_TXPF, /* 0x2_46F0 Transmit PAUSE control frame counter register R/W 0x0000_0000 15.5.3.7.29/15-74 */ + TSEC_RMON_TDFR, /* 0x2_46F4 Transmit deferral packet counter register R/W 0x0000_0000 15.5.3.7.30/15-75 */ + TSEC_RMON_TEDF, /* 0x2_46F8 Transmit excessive deferral packet counter register R/W 0x0000_0000 15.5.3.7.31/15-75 */ + TSEC_RMON_TSCL, /* 0x2_46FC Transmit single collision packet counter register R/W 0x0000_0000 15.5.3.7.32/15-76 */ + TSEC_RMON_TMCL, /* 0x2_4700 Transmit multiple collision packet counter register R/W 0x0000_0000 15.5.3.7.33/15-76 */ + TSEC_RMON_TLCL, /* 0x2_4704 Transmit late collision packet counter register R/W 0x0000_0000 15.5.3.7.34/15-77 */ + TSEC_RMON_TXCL, /* 0x2_4708 Transmit excessive collision packet counter register R/W 0x0000_0000 15.5.3.7.35/15-77 */ + TSEC_RMON_TNCL, /* 0x2_470C Transmit total collision counter register R/W 0x0000_0000 15.5.3.7.36/15-78 */ + TSEC_RESERVED1, /* 0x2_4710 Reserved, should be cleared R 0x0000_0000 */ + TSEC_RMON_TDRP, /* 0x2_4714 Transmit drop frame counter register R/W 0x0000_0000 15.5.3.7.37/15-78 */ + TSEC_RMON_TJBR, /* 0x2_4718 Transmit jabber frame counter register R/W 0x0000_0000 15.5.3.7.38/15-79 */ + TSEC_RMON_TFCS, /* 0x2_471C Transmit FCS error counter register R/W 0x0000_0000 15.5.3.7.39/15-79 */ + TSEC_RMON_TXCF, /* 0x2_4720 Transmit control frame counter register R/W 0x0000_0000 15.5.3.7.40/15-80 */ + TSEC_RMON_TOVR, /* 0x2_4724 Transmit oversize frame counter register R/W 0x0000_0000 15.5.3.7.41/15-80 */ + TSEC_RMON_TUND, /* 0x2_4728 Transmit undersize frame counter register R/W 0x0000_0000 15.5.3.7.42/15-81 */ + TSEC_RMON_TFRG, /* 0x2_472C Transmit fragments frame counter register R/W 0x0000_0000 15.5.3.7.43/15-81 */ + TSEC_RMON_CNT +} tsec_rmon_idx; + + /* TSEC1/2 General Control and Status Registers */ +typedef struct { + uint8_t reserved0x2_4000[0x24010-0x24000]; /* 0x2_4000--0x2_400F Reserved, should be cleared */ + uint32_t ievent; /* 0x2_4010 Interrupt event register R/W 0x0000_0000 15.5.3.1.1/15-19 */ + uint32_t imask; /* 0x2_4014 Interrupt mask register R/W 0x0000_0000 15.5.3.1.2/15-22 */ + uint32_t edis; /* 0x2_4018 Error disabled register R/W 0x0000_0000 15.5.3.1.3/15-24 */ + uint8_t reserved0x2_401c[0x24020-0x2401c]; /* 0x2_401c--0x2_401f Reserved, should be cleared */ + uint32_t ecntrl; /* 0x2_4020 Ethernet control register R/W 0x0000_0000 15.5.3.1.4/15-25 */ + uint32_t minflr; /* 0x2_4024 Minimum frame length register R/W 0x0000_0040 15.5.3.1.5/15-26 */ + uint32_t ptv; /* 0x2_4028 Pause time value register R/W 0x0000_0000 15.5.3.1.6/15-27 */ + uint32_t dmactrl; /* 0x2_402C DMA control register R/W 0x0000_0000 15.5.3.1.7/15-28 */ + uint32_t tbipa; /* 0x2_4030 TBI PHY address register R/W 0x0000_0000 15.5.3.1.8/15-29 */ + uint8_t reserved0x2_4034[0x2408c-0x24034]; /* 0x2_4034--0x2_408b Reserved, should be cleared */ + /* TSEC1 FIFO Control and Status Registers */ + uint32_t fifo_tx_thr; /* 0x2_408C FIFO transmit threshold register R/W 0x0000_0100 15.5.3.2.1/15-30 */ + uint8_t reserved0x2_4090[0x24094-0x24090]; /* 0x2_4090--0x2_4093 Reserved, should be cleared */ + uint32_t fifo_tx_sp; /* 0x2_4094 FIFO transmit space available register R/W 0x0000_0010 15.5.3.2.2/15-31 */ + uint32_t fifo_tx_starve; /* 0x2_4098 FIFO transmit starve register R/W 0x0000_0080 15.5.3.2.3/15-31 */ + uint32_t fifo_tx_starve_shutoff; /* 0x2_409C FIFO transmit starve shutoff register R/W 0x0000_0100 15.5.3.2.4/15-32 */ + uint8_t reserved0x2_40A0[0x24100-0x240A0]; /* 0x2_40A0--0x2_40ff Reserved, should be cleared */ + /* TSEC1 Transmit Control and Status Registers */ + uint32_t tctrl; /* 0x2_4100 Transmit control register R/W 0x0000_0000 15.5.3.3.1/15-33 */ + uint32_t tstat; /* 0x2_4104 Transmit status register R/W 0x0000_0000 15.5.3.3.2/15-34 */ + uint8_t reserved0x2_4108[0x24110-0x24108]; /* 0x2_4108 Reserved, should be cleared R 0x0000_0000 */ + uint32_t txic; /* 0x2_4110 Transmit interrupt coalescing configuration register R/W 0x0000_0000 */ + uint8_t reserved0x2_4114[0x24124-0x24114]; /* 0x2_4114--0x2_4120 Reserved, should be cleared */ + uint32_t ctbptr; /* 0x2_4124 Current TxBD pointer register R 0x0000_0000 15.5.3.3.5/15-36 */ + uint8_t reserved0x2_4128[0x24184-0x24128]; /* 0x2_4128--0x2_4180 Reserved, should be cleared */ + uint32_t tbptr; /* 0x2_4184 TxBD pointer register R/W 0x0000_0000 15.5.3.3.6/15-36 */ + uint8_t reserved0x2_4188[0x24204-0x24188]; /* 0x2_4188--0x2_4200 Reserved, should be cleared */ + uint32_t tbase; /* 0x2_4204 TxBD base address register R/W 0x0000_0000 15.5.3.3.7/15-37 */ + uint8_t reserved0x2_4208[0x242B0-0x24208]; /* 0x2_4208--0x2_42AC Reserved, should be cleared */ + uint32_t ostbd; /* 0x2_42B0 Out-of-sequence TxBD register R/W 0x0800_0000 15.5.3.3.8/15-37 */ + uint32_t ostbdp; /* 0x2_42B4 Out-of-sequence Tx data buffer pointer register R/W 0x0000_0000 15.5.3.3.9/15-39 */ + uint8_t reserved0x2_42B8[0x24300-0x242B8]; /* 0x2_42B8--0x2_42FC Reserved, should be cleared */ + /* TSEC1 Receive Control and Status Registers */ + uint32_t rctrl; /* 0x2_4300 Receive control register R/W 0x0000_0000 15.5.3.4.1/15-40 */ + uint32_t rstat; /* 0x2_4304 Receive status register R/W 0x0000_0000 15.5.3.4.2/15-41 */ + uint8_t reserved0x2_4308[0x2430C-0x24308]; /* 0x2_4308 Reserved, should be cleared R 0x0000_0000 */ + uint32_t rbdlen; /* 0x2_430C RxBD data length register R 0x0000_0000 15.5.3.4.3/15-41 */ + uint32_t rxic; /* 0x2_4310 Receive interrupt coalescing configuration register R/W 0x0000_0000 15.5.3.4.4/15-42 */ + uint8_t reserved0x2_4314[0x24324-0x24314]; /* 0x2_4314--0x2_4320 Reserved, should be cleared */ + uint32_t crbptr; /* 0x2_4324 Current RxBD pointer register R 0x0000_0000 15.5.3.4.5/15-43 */ + uint8_t reserved0x2_4328[0x24340-0x24328]; /* 0x2_4328--0x2_433C Reserved, should be cleared */ + uint32_t mrblr; /* 0x2_4340 Maximum receive buffer length register R/W 0x0000_0000 15.5.3.4.6/15-43 */ + uint8_t reserved0x2_4344[0x24384-0x24344]; /* 0x2_4344--0x2_4380 Reserved, should be cleared */ + uint32_t rbptr; /* 0x2_4384 RxBD pointer register R/W 0x0000_0000 15.5.3.4.7/15-44 */ + uint8_t reserved0x2_4388[0x24404-0x24388]; /* 0x2_4388--0x2_4400 Reserved, should be cleared */ + uint32_t rbase; /* 0x2_4404 RxBD base address register R/W 0x0000_0000 15.5.3.4.8/15-44 */ + uint8_t reserved0x2_4408[0x24500-0x24408]; /* 0x2_4408--0x2_44FC Reserved, should be cleared */ + /* TSEC1 MAC Registers */ + uint32_t maccfg1; /* 0x2_4500 MAC configuration register 1 R/W, R 0x0000_0000 15.5.3.6.1/15-48 */ + uint32_t maccfg2; /* 0x2_4504 MAC configuration register 2 R/W 0x0000_7000 15.5.3.6.2/15-49 */ + uint32_t ipgifg; /* 0x2_4508 Inter-packet gap/inter-frame gap register R/W 0x4060_5060 15.5.3.6.3/15-51 */ + uint32_t hafdup; /* 0x2_450C Half-duplex register R/W 0x00A1_F037 15.5.3.6.4/15-52 */ + uint32_t maxfrm; /* 0x2_4510 Maximum frame length register R/W 0x0000_0600 15.5.3.6.5/15-53 */ + uint8_t reserved0x2_4514[0x24520-0x24514]; /* 0x2_4514--0x2_451C Reserved, should be cleared */ + uint32_t miimcfg; /* 0x2_4520 MII management configuration register R/W 0x0000_0000 15.5.3.6.6/15-53 */ + uint32_t miimcom; /* 0x2_4524 MII management command register R/W 0x0000_0000 15.5.3.6.7/15-54 */ + uint32_t miimadd; /* 0x2_4528 MII management address register R/W 0x0000_0000 15.5.3.6.8/15-55 */ + uint32_t miimcon; /* 0x2_452C MII management control register W 0x0000_0000 15.5.3.6.9/15-56 */ + uint32_t miimstat; /* 0x2_4530 MII management status register R 0x0000_0000 15.5.3.6.10/15-56 */ + uint32_t miimind; /* 0x2_4534 MII management indicator register R 0x0000_0000 15.5.3.6.11/15-57 */ + uint8_t reserved0x2_4538[0x2453c-0x24538]; /* 0x2_4538 Reserved, should be cleared $ $ */ + uint32_t ifstat; /* 0x2_453C Interface status register Special 0x0000_0001 15.5.3.6.12/15-58 */ + uint32_t macstnaddr[2]; /* 0x2_4540 Station address register, part 1/2 R/W 0x0000_0000 15.5.3.6.13/15-58 */ + uint8_t reserved0x2_4548[0x24680-0x24548]; /* 0x2_4548--0x2_467C Reserved, should be cleared */ + + /* TSEC1 RMON MIB Registers */ + uint32_t rmon_mib[TSEC_RMON_CNT]; + + /* TSEC1 General Registers */ + uint32_t car[2]; /* 0x2_4730 Carry register one/two register R 0x0000_0000 15.5.3.7.44/15-82 */ + uint32_t cam[2]; /* 0x2_4738 Carry register one/two mask register R/W 0xFE01_FFFF 15.5.3.7.46/15-85 */ + uint8_t reserved0x2_4740[0x24800-0x24740]; /* 0x2_4740--0x2_47FC Reserved, should be cleared */ + + /* TSEC1 Hash Function Registers */ + uint32_t iaddr[8]; /* 0x2_4800 Individual address register 0-7 R/W 0x0000_0000 15.5.3.8.1/15-87 */ + uint8_t reserved0x2_4820[0x24880-0x24820]; /* 0x2_4820--0x2_487C Reserved, should be cleared */ + uint32_t gaddr[8]; /* 0x2_4880 Group address register 0-7 R/W 0x0000_0000 15.5.3.8.2/15-88 */ + uint8_t reserved0x2_48A0[0x24B00-0x248A0]; /* 0x2_48A0--0x2_4AFF Reserved, should be cleared */ + + /* TSEC1 Attribute Registers */ + uint8_t reserved0x2_4B00[0x24BF8-0x24B00]; /* 0x2_4B00--0x2_4BF4 Reserved, should be cleared */ + uint32_t attr; /* 0x2_4BF8 Attribute register R 0x0000_0000 */ + uint32_t attreli; /* 0x2_4BFC Attribute extract length and extract index register R/W 0x0000_0000 */ + uint8_t reserved0x2_4C00[0x25000-0x24C00]; /* 0x2_4C00--0x2_4FFF Reserved, should be cleared */ +} tsec_registers; + +/* + * TSEC IEVENT/IMASK bit definitions + */ +#define TSEC_IEVENT_BABR (1<<(31- 0)) +#define TSEC_IEVENT_RXC (1<<(31- 1)) +#define TSEC_IEVENT_BSY (1<<(31- 2)) +#define TSEC_IEVENT_EBERR (1<<(31- 3)) +#define TSEC_IEVENT_MSRO (1<<(31- 5)) +#define TSEC_IEVENT_GTSC (1<<(31- 6)) +#define TSEC_IEVENT_BABT (1<<(31- 7)) +#define TSEC_IEVENT_TXC (1<<(31- 8)) +#define TSEC_IEVENT_TXE (1<<(31- 9)) +#define TSEC_IEVENT_TXB (1<<(31-10)) +#define TSEC_IEVENT_TXF (1<<(31-11)) +#define TSEC_IEVENT_LC (1<<(31-13)) +#define TSEC_IEVENT_CRL_XDA (1<<(31-14)) +#define TSEC_IEVENT_XFUN (1<<(31-15)) +#define TSEC_IEVENT_RXB (1<<(31-16)) +#define TSEC_IEVENT_MMRD (1<<(31-21)) +#define TSEC_IEVENT_MMWR (1<<(31-22)) +#define TSEC_IEVENT_GRSC (1<<(31-23)) +#define TSEC_IEVENT_RXF (1<<(31-24)) + +/* + * TSEC DMACTRL bit definitions + */ +#define TSEC_DMACTL_TDSEN (1<<(31-24)) +#define TSEC_DMACTL_TBDSEN (1<<(31-25)) +#define TSEC_DMACTL_GRS (1<<(31-27)) +#define TSEC_DMACTL_GTS (1<<(31-28)) +#define TSEC_DMACTL_WWR (1<<(31-30)) +#define TSEC_DMACTL_WOP (1<<(31-31)) + +/* + * TSEC TSTAT bit definitions + */ +#define TSEC_TSTAT_THLT (1<<(31-0)) + +/* + * TSEC RSTAT bit definitions + */ +#define TSEC_RSTAT_QHLT (1<<(31-8)) + /* + * TSEC ECNTRL bit positions + */ +#define TSEC_ECNTRL_CLRCNT (1 << (31-17)) /* Clear stat counters */ +#define TSEC_ECNTRL_AUTOZ (1 << (31-18)) /* auto-zero read counters */ +#define TSEC_ECNTRL_STEN (1 << (31-19)) /* enable statistics */ +#define TSEC_ECNTRL_TBIM (1 << (31-26)) /* ten-bit-interface */ +#define TSEC_ECNTRL_RPM (1 << (31-27)) /* reduced signal mode */ +#define TSEC_ECNTRL_R100M (1 << (31-28)) /* RGMII100 mode */ + /* + * TSEC EDIS bit positions + */ +#define TSEC_EDIS_BSYDIS (1 << (31- 2)) /* Busy disable */ +#define TSEC_EDIS_EBERRDIS (1 << (31- 3)) /* bus error disable */ +#define TSEC_EDIS_TXEDIS (1 << (31- 9)) /* Tx error disable */ +#define TSEC_EDIS_LCDIS (1 << (31-13)) /* Late collision disable */ +#define TSEC_EDIS_CRLXDADIS (1 << (31-14)) /* Collision Retry disable */ +#define TSEC_EDIS_FUNDIS (1 << (31-15)) /* Tx FIFO underrun disable*/ + + /* + * TSEC RCTRL bit positions + */ +#define TSEC_RCTRL_BC_REJ (1 << (31-27)) /* Broadcast Reject */ +#define TSEC_RCTRL_PROM (1 << (31-28)) /* Promiscuous */ +#define TSEC_RCTRL_RSF (1 << (31-29)) /* Receive short frames */ + + /* + * TSEC TXIC bit positions + */ +#define TSEC_TXIC_ICEN (1 << (31- 0)) /* Irq coalescing enable */ +#define TSEC_TXIC_ICFCT(n) (((n)&0xff) << (31-10)) /* Frame coal. cnt */ +#define TSEC_TXIC_ICTT(n) (((n)&0xffff) << (31-31)) /* Buf. coal. cnt */ + + /* + * TSEC RXIC bit positions + */ +#define TSEC_RXIC_ICEN (1 << (31- 0)) /* Irq coalescing enable */ +#define TSEC_RXIC_ICFCT(n) (((n)&0xff) << (31-10)) /* Frame coal. cnt */ +#define TSEC_RXIC_ICTT(n) (((n)&0xffff) << (31-31)) /* Buf. coal. cnt */ + + /* + * TSEC MACCFG1 bit positions + */ +#define TSEC_MACCFG1_SOFTRST (1 << (31- 0)) /* Soft Reset */ +#define TSEC_MACCFG1_RES_RXMC (1 << (31-12)) /* Reset Rx MAC block */ +#define TSEC_MACCFG1_RES_TXMC (1 << (31-13)) /* Reset Tx MAC block */ +#define TSEC_MACCFG1_RES_RXFUN (1 << (31-14)) /* Reset Rx function blk*/ +#define TSEC_MACCFG1_RES_TXFUN (1 << (31-15)) /* Reset Tx function blk*/ +#define TSEC_MACCFG1_LOOPBACK (1 << (31-23)) /* Loopback mode */ +#define TSEC_MACCFG1_RX_FLOW (1 << (31-26)) /* Receive Flow Ctrl */ +#define TSEC_MACCFG1_TX_FLOW (1 << (31-27)) /* Transmit Flow Ctrl */ +#define TSEC_MACCFG1_SYNVRXEN (1 << (31-28)) /* Sync Receive Enable */ +#define TSEC_MACCFG1_RXEN (1 << (31-29)) /* Receive Enable */ +#define TSEC_MACCFG1_SYNVTXEN (1 << (31-30)) /* Sync Transmit Enable */ +#define TSEC_MACCFG1_TXEN (1 << (31-31)) /* Transmit Enable */ + + /* + * TSEC MACCFG2 bit positions + */ +#define TSEC_MACCFG2_PRELEN(n) (((n)&0x0f) << (31-19)) /* Preamble len*/ + +#define TSEC_MACCFG2_IFMODE_MSK (3 << (31-23)) /* mode mask */ +#define TSEC_MACCFG2_IFMODE_NIB (1 << (31-23)) /* nibble mode */ +#define TSEC_MACCFG2_IFMODE_BYT (2 << (31-23)) /* byte mode */ + +#define TSEC_MACCFG2_HUGE_FRAME (1 << (31-26)) /* Huge Frame */ +#define TSEC_MACCFG2_LENGTH_CHK (1 << (31-27)) /* Length Check */ +#define TSEC_MACCFG2_PAD_CRC (1 << (31-29)) /* MAC adds PAD/CRC */ +#define TSEC_MACCFG2_CRC_EN (1 << (31-30)) /* CRC enable */ +#define TSEC_MACCFG2_FULLDUPLEX (1 << (31-31)) /* Full Duplex Mode */ + + /* + * TSEC MIIMADD bit positions + */ +#define TSEC_MIIMADD_PHY(n) (((n) & 0x3f)<<(31- 23)) /* PHY addr */ +#define TSEC_MIIMADD_REGADDR(n) (((n) & 0x3f)<<(31- 31)) /* PHY addr */ + + /* + * TSEC MIIMCOM bit positions + */ +#define TSEC_MIIMCOM_SCAN (1 << (31-30)) /* Scan command */ +#define TSEC_MIIMCOM_READ (1 << (31-31)) /* Read command */ + + /* + * TSEC MIIMIND bit positions + */ +#define TSEC_MIIMIND_NVAL (1 << (31-29)) /* not valid */ +#define TSEC_MIIMIND_SCAN (1 << (31-30)) /* Scan in progress */ +#define TSEC_MIIMIND_BUSY (1 << (31-31)) /* Acc. in progress */ + + /* + * TSEC ATTR bit positions + */ +#define TSEC_ATTR_RDSEN (1 << (31-24)) /* read data snoop */ +#define TSEC_ATTR_RBDSEN (1 << (31-25)) /* read BD snoop */ + +typedef struct { + volatile uint16_t status; + volatile uint16_t length; + volatile void *buffer; +} PQBufferDescriptor_t; + +/* + * Bits in receive buffer descriptor status word + */ +#define BD_EMPTY (1<<15) +#define BD_RO1 (1<<14) +#define BD_WRAP (1<<13) +#define BD_INTERRUPT (1<<12) +#define BD_LAST (1<<11) +#define BD_CONTROL_CHAR (1<<11) +#define BD_FIRST_IN_FRAME (1<<10) +#define BD_MISS (1<<8) +#define BD_BROADCAST (1<<7) +#define BD_MULTICAST (1<<6) +#define BD_LONG (1<<5) +#define BD_NONALIGNED (1<<4) +#define BD_SHORT (1<<3) +#define BD_CRC_ERROR (1<<2) +#define BD_OVERRUN (1<<1) +#define BD_COLLISION (1<<0) + +/* + * Bits in transmit buffer descriptor status word + * Many bits have the same meaning as those in receiver buffer descriptors. + */ +#define BD_READY (1<<15) +#define BD_PAD_CRC (1<<14) +/* WRAP/Interrupt as in Rx BDs */ +#define BD_TX_CRC (1<<10) +#define BD_DEFER (1<<9) +#define BD_TO1 (1<<8) +#define BD_HFE_ (1<<7) +#define BD_LATE_COLLISION (1<<7) +#define BD_RETRY_LIMIT (1<<6) +#define BD_RETRY_COUNT(x) (((x)&0x3C)>>2) +#define BD_UNDERRUN (1<<1) +#define BD_TXTRUNC (1<<0) + +struct rtems_bsdnet_ifconfig; + +typedef struct { + int unit_number; + char *unit_name; + volatile tsec_registers *reg_ptr; + volatile tsec_registers *mdio_ptr; + rtems_irq_number irq_num_tx; + rtems_irq_number irq_num_rx; + rtems_irq_number irq_num_err; + int phy_default; +} tsec_config; + +int tsec_driver_attach_detach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_TSEC_H */ diff --git a/bsps/powerpc/include/bsp/u-boot-board-info.h b/bsps/powerpc/include/bsp/u-boot-board-info.h new file mode 100644 index 0000000000..b377705687 --- /dev/null +++ b/bsps/powerpc/include/bsp/u-boot-board-info.h @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2000 - 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __U_BOOT_H__ +#define __U_BOOT_H__ + +/* + * Board information passed to Linux kernel from U-Boot + * + * include/asm-ppc/u-boot.h + */ + +#ifndef __ASSEMBLY__ + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ + || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) + unsigned long bi_immr_base; /* base of IMMR register */ +#endif +#if defined(CONFIG_MPC5xxx) + unsigned long bi_mbar_base; /* base of internal registers */ +#endif +#if defined(CONFIG_MPC83xx) + unsigned long bi_immrbar; +#endif +#if defined(CONFIG_MPC8220) + unsigned long bi_mbar_base; /* base of internal registers */ + unsigned long bi_inpfreq; /* Input Freq, In MHz */ + unsigned long bi_pcifreq; /* PCI Freq, in MHz */ + unsigned long bi_pevfreq; /* PEV Freq, in MHz */ + unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */ + unsigned long bi_vcofreq; /* VCO Freq, in MHz */ +#endif + unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ + unsigned long bi_intfreq; /* Internal Freq, in MHz */ + unsigned long bi_busfreq; /* Bus Freq, in MHz */ +#if defined(CONFIG_CPM2) + unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ + unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ + unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ + unsigned long bi_vco; /* VCO Out from PLL, in MHz */ +#endif +#if defined(CONFIG_MPC512X) + unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ +#endif /* CONFIG_MPC512X */ +#if defined(CONFIG_MPC5xxx) + unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ + unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ +#endif + unsigned long bi_baudrate; /* Console Baudrate */ +#if defined(CONFIG_405) || \ + defined(CONFIG_405GP) || \ + defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) || \ + defined(CONFIG_440) + unsigned char bi_s_version[4]; /* Version of this structure */ + unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ + unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ + unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ + unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ + unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ +#endif +#if defined(CONFIG_HYMOD) + hymod_conf_t bi_hymod_conf; /* hymod configuration information */ +#endif + +#ifdef CONFIG_HAS_ETH1 + unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH2 + unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH3 + unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH4 + unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH5 + unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */ +#endif + +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) + unsigned int bi_opbfreq; /* OPB clock in Hz */ + int bi_iic_fast[2]; /* Use fast i2c mode */ +#endif +#if defined(CONFIG_NX823) + unsigned char bi_sernum[8]; +#endif +#if defined(CONFIG_4xx) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) + int bi_phynum[4]; /* Determines phy mapping */ + int bi_phymode[4]; /* Determines phy mode */ +#elif defined(CONFIG_405EP) || defined(CONFIG_440) + int bi_phynum[2]; /* Determines phy mapping */ + int bi_phymode[2]; /* Determines phy mode */ +#else + int bi_phynum[1]; /* Determines phy mapping */ + int bi_phymode[1]; /* Determines phy mode */ +#endif +#endif /* defined(CONFIG_4xx) */ +} bd_t; + +#endif /* __ASSEMBLY__ */ +#endif /* __U_BOOT_H__ */ diff --git a/bsps/powerpc/include/bsp/uart.h b/bsps/powerpc/include/bsp/uart.h new file mode 100644 index 0000000000..b7539b5b7b --- /dev/null +++ b/bsps/powerpc/include/bsp/uart.h @@ -0,0 +1,190 @@ + +/* + * This software is Copyright (C) 1998 by T.sqware - all rights limited + * It is provided in to the public domain "as is", can be freely modified + * as far as this copyight notice is kept unchanged, but does not imply + * an endorsement by T.sqware of the product in which it is included. + */ + +#ifndef _BSPUART_H +#define _BSPUART_H + +#include + +#include +#include + +void BSP_uart_init(int uart, int baud, int hwFlow); +void BSP_uart_set_baud(int uart, int baud); +void BSP_uart_intr_ctrl(int uart, int cmd); +void BSP_uart_throttle(int uart); +void BSP_uart_unthrottle(int uart); +int BSP_uart_polled_status(int uart); +void BSP_uart_polled_write(int uart, int val); +int BSP_uart_polled_read(int uart); +void BSP_uart_termios_set(int uart, void *ttyp); +ssize_t BSP_uart_termios_write_com(int minor, const char *buf, size_t len); +int BSP_uart_termios_read_com (int minor); +void BSP_uart_termios_isr_com1(void *unused); +void BSP_uart_termios_isr_com2(void *unused); +void BSP_uart_dbgisr_com1(void); +void BSP_uart_dbgisr_com2(void); +int BSP_uart_install_isr(int uart, rtems_irq_hdl handler); +int BSP_uart_remove_isr(int uart, rtems_irq_hdl handler); +ssize_t BSP_uart_termios_write_polled(int minor, const char *buf, size_t len); +int BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg); +int BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg); + +extern unsigned BSP_poll_char_via_serial(void); +extern void BSP_output_char_via_serial(const char val); +extern int BSPConsolePort; +extern int BSPBaseBaud; + +/* Special IOCTLS to install a lowlevel 'BREAK' handler */ + +/* pass a BSP_UartBreakCb pointer to ioctl when retrieving + * or installing break callback + */ +typedef void (*BSP_UartBreakCbProc)( + int uartMinor, + unsigned uartRBRLSRStatus, + void *termiosPrivatePtr, + void *private +); + +typedef struct BSP_UartBreakCbRec_ { + BSP_UartBreakCbProc handler; /* NOTE: handler runs in INTERRUPT CONTEXT */ + void *private; /* closure pointer which is passed to the callback */ +} BSP_UartBreakCbRec, *BSP_UartBreakCb; + +#define BIOCGETBREAKCB _IOR('b',1,sizeof(BSP_UartBreakCbRec)) +#define BIOCSETBREAKCB _IOW('b',2,sizeof(BSP_UartBreakCbRec)) + +/* + * Command values for BSP_uart_intr_ctrl(), + * values are strange in order to catch errors + * with assert + */ +#define BSP_UART_INTR_CTRL_DISABLE (0) +#define BSP_UART_INTR_CTRL_GDB (0xaa) /* RX only */ +#define BSP_UART_INTR_CTRL_ENABLE (0xbb) /* Normal operations */ +#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) /* RX & line status */ + +/* Return values for uart_polled_status() */ +#define BSP_UART_STATUS_ERROR (-1) /* No character */ +#define BSP_UART_STATUS_NOCHAR (0) /* No character */ +#define BSP_UART_STATUS_CHAR (1) /* Character present */ +#define BSP_UART_STATUS_BREAK (2) /* Break point is detected */ + +/* PC UART definitions */ +#define BSP_UART_COM1 (0) +#define BSP_UART_COM2 (1) + +/* + * Offsets from base + */ + +/* DLAB 0 */ +#define RBR (0) /* Rx Buffer Register (read) */ +#define THR (0) /* Tx Buffer Register (write) */ +#define IER (1) /* Interrupt Enable Register */ + +/* DLAB X */ +#define IIR (2) /* Interrupt Ident Register (read) */ +#define FCR (2) /* FIFO Control Register (write) */ +#define LCR (3) /* Line Control Register */ +#define MCR (4) /* Modem Control Register */ +#define LSR (5) /* Line Status Register */ +#define MSR (6) /* Modem Status Register */ +#define SCR (7) /* Scratch register */ + +/* DLAB 1 */ +#define DLL (0) /* Divisor Latch, LSB */ +#define DLM (1) /* Divisor Latch, MSB */ +#define AFR (2) /* Alternate Function register */ + +/* + * Interrupt source definition via IIR + */ +#define MODEM_STATUS 0 +#define NO_MORE_INTR 1 +#define TRANSMITTER_HODING_REGISTER_EMPTY 2 +#define RECEIVER_DATA_AVAIL 4 +#define RECEIVER_ERROR 6 +#define CHARACTER_TIMEOUT_INDICATION 12 + +/* + * Bits definition of IER + */ +#define RECEIVE_ENABLE 0x1 +#define TRANSMIT_ENABLE 0x2 +#define RECEIVER_LINE_ST_ENABLE 0x4 +#define MODEM_ENABLE 0x8 +#define INTERRUPT_DISABLE 0x0 + +/* + * Bits definition of the Line Status Register (LSR) + */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* Transmitter Holding Register Empty */ +#define TEMT 0x40 /* Transmitter Empty */ +#define ERFIFO 0x80 /* Error receive Fifo */ + +/* + * Bits definition of the MODEM Control Register (MCR) + */ +#define DTR 0x01 /* Data Terminal Ready */ +#define RTS 0x02 /* Request To Send */ +#define OUT_1 0x04 /* Output 1, (reserved on COMPAQ I/O Board) */ +#define OUT_2 0x08 /* Output 2, Enable Asynchronous Port Interrupts */ +#define LB 0x10 /* Enable Internal Loop Back */ + +/* + * Bits definition of the Line Control Register (LCR) + */ +#define CHR_5_BITS 0 +#define CHR_6_BITS 1 +#define CHR_7_BITS 2 +#define CHR_8_BITS 3 + +#define WL 0x03 /* Word length mask */ +#define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */ +#define PEN 0x08 /* Parity Enabled */ +#define EPS 0x10 /* Even Parity Select, otherwise Odd */ +#define SP 0x20 /* Stick Parity */ +#define BCB 0x40 /* Break Control Bit */ +#define DLAB 0x80 /* Enable Divisor Latch Access */ + +/* + * Bits definition of the MODEM Status Register (MSR) + */ +#define DCTS 0x01 /* Delta Clear To Send */ +#define DDSR 0x02 /* Delta Data Set Ready */ +#define TERI 0x04 /* Trailing Edge Ring Indicator */ +#define DDCD 0x08 /* Delta Carrier Detect Indicator */ +#define CTS 0x10 /* Clear To Send (when loop back is active) */ +#define DSR 0x20 /* Data Set Ready (when loop back is active) */ +#define RI 0x40 /* Ring Indicator (when loop back is active) */ +#define DCD 0x80 /* Data Carrier Detect (when loop back is active) */ + +/* + * Bits definition of the FIFO Control Register : WD16C552 or NS16550 + */ + +#define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */ +#define FIFO_EN 0x01 /* Enable the FIFO */ +#define XMIT_RESET 0x02 /* Transmit FIFO Reset */ +#define RCV_RESET 0x04 /* Receive FIFO Reset */ +#define FCR3 0x08 /* do not understand manual! */ + +#define RECEIVE_FIFO_TRIGGER1 0x00 /* trigger RX interrupt after 1 byte */ +#define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger RX interrupt after 4 bytes */ +#define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger RX interrupt after 8 bytes */ +#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger RX interrupt after 12 bytes */ +#define TRIG_LEVEL 0xc0 /* Mask for the trigger level */ + +#endif /* _BSPUART_H */ diff --git a/bsps/powerpc/include/bsp/vectors.h b/bsps/powerpc/include/bsp/vectors.h new file mode 100644 index 0000000000..81526eb4b0 --- /dev/null +++ b/bsps/powerpc/include/bsp/vectors.h @@ -0,0 +1,493 @@ +/** + * @file + * + * @ingroup ppc_exc + * @ingroup ppc_exc_frame + * + * @brief PowerPC Exceptions API. + */ + +/* + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * Copyright (C) 2007 Till Straumann + * + * Copyright (C) 2009 embedded brains GmbH. + * + * Enhanced by Jay Kulpinski + * to support 603, 603e, 604, 604e exceptions + * + * Moved to "libcpu/powerpc/new-exceptions" and consolidated + * by Thomas Doerfler + * to be common for all PPCs with new exceptions. + * + * Derived from file "libcpu/powerpc/new-exceptions/raw_exception.h". + * Derived from file "libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h". + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* DO NOT INTRODUCE #ifdef in this file */ + +#ifndef LIBCPU_VECTORS_H +#define LIBCPU_VECTORS_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup ppc_exc PowerPC Exceptions + * + * @brief XXX + * + * @{ + */ + +#define ASM_RESET_VECTOR 0x01 +#define ASM_MACH_VECTOR 0x02 +#define ASM_PROT_VECTOR 0x03 +#define ASM_ISI_VECTOR 0x04 +#define ASM_EXT_VECTOR 0x05 +#define ASM_ALIGN_VECTOR 0x06 +#define ASM_PROG_VECTOR 0x07 +#define ASM_FLOAT_VECTOR 0x08 +#define ASM_DEC_VECTOR 0x09 +#define ASM_SYS_VECTOR 0x0C +#define ASM_TRACE_VECTOR 0x0D + +#define ASM_PPC405_APU_UNAVAIL_VECTOR ASM_60X_VEC_ASSIST_VECTOR + +#define ASM_8XX_FLOATASSIST_VECTOR 0x0E +#define ASM_8XX_SOFTEMUL_VECTOR 0x10 +#define ASM_8XX_ITLBMISS_VECTOR 0x11 +#define ASM_8XX_DTLBMISS_VECTOR 0x12 +#define ASM_8XX_ITLBERROR_VECTOR 0x13 +#define ASM_8XX_DTLBERROR_VECTOR 0x14 +#define ASM_8XX_DBREAK_VECTOR 0x1C +#define ASM_8XX_IBREAK_VECTOR 0x1D +#define ASM_8XX_PERIFBREAK_VECTOR 0x1E +#define ASM_8XX_DEVPORT_VECTOR 0x1F + +#define ASM_5XX_FLOATASSIST_VECTOR 0x0E +#define ASM_5XX_SOFTEMUL_VECTOR 0x10 +#define ASM_5XX_IPROT_VECTOR 0x13 +#define ASM_5XX_DPROT_VECTOR 0x14 +#define ASM_5XX_DBREAK_VECTOR 0x1C +#define ASM_5XX_IBREAK_VECTOR 0x1D +#define ASM_5XX_MEBREAK_VECTOR 0x1E +#define ASM_5XX_NMEBREAK_VECTOR 0x1F + +#define ASM_60X_VEC_VECTOR 0x0A +#define ASM_60X_PERFMON_VECTOR 0x0F +#define ASM_60X_IMISS_VECTOR 0x10 +#define ASM_60X_DLMISS_VECTOR 0x11 +#define ASM_60X_DSMISS_VECTOR 0x12 +#define ASM_60X_ADDR_VECTOR 0x13 +#define ASM_60X_SYSMGMT_VECTOR 0x14 +#define ASM_60X_VEC_ASSIST_VECTOR 0x16 +#define ASM_60X_ITM_VECTOR 0x17 + +/* Book E */ +#define ASM_BOOKE_CRIT_VECTOR 0x01 +/* We could use the std. decrementer vector # on bookE, too, + * but the bookE decrementer has slightly different semantics + * so we use a different vector (which happens to be + * the PIT vector on the 405 which is like the booke decrementer) + */ +#define ASM_BOOKE_DEC_VECTOR 0x10 +#define ASM_BOOKE_ITLBMISS_VECTOR 0x11 +#define ASM_BOOKE_DTLBMISS_VECTOR 0x12 +#define ASM_BOOKE_FIT_VECTOR 0x13 +#define ASM_BOOKE_WDOG_VECTOR 0x14 +#define ASM_BOOKE_APU_VECTOR 0x18 +#define ASM_BOOKE_DEBUG_VECTOR ASM_TRACE_VECTOR + +/* e200 and e500 */ +#define ASM_E500_SPE_UNAVAILABLE_VECTOR ASM_60X_VEC_VECTOR +#define ASM_E500_EMB_FP_DATA_VECTOR 0x19 +#define ASM_E500_EMB_FP_ROUND_VECTOR 0x1A +#define ASM_E500_PERFMON_VECTOR ASM_60X_PERFMON_VECTOR + +/* e300 */ +#define ASM_E300_CRIT_VECTOR 0x0A +#define ASM_E300_PERFMON_VECTOR ASM_60X_PERFMON_VECTOR +#define ASM_E300_IMISS_VECTOR ASM_60X_IMISS_VECTOR /* Special case: Shadowed GPRs */ +#define ASM_E300_DLMISS_VECTOR ASM_60X_DLMISS_VECTOR /* Special case: Shadowed GPRs */ +#define ASM_E300_DSMISS_VECTOR ASM_60X_DSMISS_VECTOR /* Special case: Shadowed GPRs */ +#define ASM_E300_ADDR_VECTOR ASM_60X_ADDR_VECTOR +#define ASM_E300_SYSMGMT_VECTOR ASM_60X_SYSMGMT_VECTOR + +/* + * If you change that number make sure to adjust the wrapper code in ppc_exc.S + * and that ppc_exc_handler_table will be correctly initialized. + */ +#define LAST_VALID_EXC 0x1F + +/* DO NOT USE -- this symbol is DEPRECATED + * (only used by libbsp/shared/vectors/vectors.S + * which should not be used by new BSPs). + */ +#define ASM_60X_VEC_VECTOR_OFFSET 0xf20 + +#define ASM_PPC405_FIT_VECTOR_OFFSET 0x1010 +#define ASM_PPC405_WDOG_VECTOR_OFFSET 0x1020 +#define ASM_PPC405_TRACE_VECTOR_OFFSET 0x2000 + +/** @} */ + +/** + * @defgroup ppc_exc_frame PowerPC Exception Frame + * + * @brief XXX + * + * @{ + */ + +/* + * The callee (high level exception code written in C) + * will store the Link Registers (return address) at entry r1 + 4 !!!. + * So let room for it!!!. + */ +#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 + +#define EXC_GENERIC_SIZE (PPC_EXC_FRAME_SIZE + PPC_STACK_RED_ZONE_SIZE) + +#define PPC_EXC_INTERRUPT_FRAME_SIZE CPU_INTERRUPT_FRAME_SIZE + +#if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC) +#define EXC_VEC_OFFSET EXC_GENERIC_SIZE +#ifndef PPC_CACHE_ALIGNMENT +#error "Missing include file!" +#endif +/* 20 volatile registers + * + cache-aligned area for vcsr, vrsave + * + area for alignment + */ +#define EXC_VEC_SIZE (16*20 + 2*PPC_CACHE_ALIGNMENT) +#else +#define EXC_VEC_SIZE (0) +#endif + +/* + * maintain the EABI requested 8 bytes aligment + * As SVR4 ABI requires 16, make it 16 (as some + * exception may need more registers to be processed...) + */ +#define EXCEPTION_FRAME_END (EXC_GENERIC_SIZE + EXC_VEC_SIZE) + +/** @} */ + +#ifndef ASM + +/** + * @ingroup ppc_exc_frame + * + * @{ + */ + +typedef CPU_Exception_frame BSP_Exception_frame; + +/** @} */ + +/** + * @ingroup ppc_exc + * + * @{ + */ + +/** + * @brief Global exception handler type. + */ +typedef void (*exception_handler_t)(BSP_Exception_frame*); + +/** + * @brief Default global exception handler. + */ +void C_exception_handler(BSP_Exception_frame* excPtr); + +void BSP_printStackTrace(const BSP_Exception_frame *excPtr); + +/** + * @brief Exception categories. + * + * Exceptions of different categories use different SRR registers to save the + * machine state and do different things in the prologue and epilogue. + * + * For now, the CPU descriptions assume this fits into 8 bits. + */ +typedef enum { + PPC_EXC_INVALID = 0, + PPC_EXC_ASYNC = 1, + PPC_EXC_CLASSIC = 2, + PPC_EXC_CLASSIC_ASYNC = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, + PPC_EXC_405_CRITICAL = 4, + PPC_EXC_405_CRITICAL_ASYNC = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC, + PPC_EXC_BOOKE_CRITICAL = 6, + PPC_EXC_BOOKE_CRITICAL_ASYNC = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC, + PPC_EXC_E500_MACHCHK = 8, + PPC_EXC_E500_MACHCHK_ASYNC = PPC_EXC_E500_MACHCHK | PPC_EXC_ASYNC, + PPC_EXC_NAKED = 10 +} ppc_exc_category; + +/** + * @brief Categorie set type. + */ +typedef uint8_t ppc_exc_categories [LAST_VALID_EXC + 1]; + +static inline bool ppc_exc_is_valid_category(ppc_exc_category category) +{ + return (unsigned) category <= (unsigned) PPC_EXC_NAKED; +} + +/** + * @brief Returns the entry address of the vector. + * + * @param[in] vector The vector number. + * @param[in] vector_base The vector table base address. + */ +void *ppc_exc_vector_address(unsigned vector, void *vector_base); + +/** + * @brief Returns the category set for a CPU of type @a cpu, or @c NULL if + * there is no category set available for this CPU. + */ +const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu); + +/** + * @brief Returns the category set for the current CPU, or @c NULL if there is + * no category set available for this CPU. + */ +static inline const ppc_exc_categories *ppc_exc_current_categories(void) +{ + return ppc_exc_categories_for_cpu(ppc_cpu_current()); +} + +/** + * @brief Returns the category for the vector @a vector using the category set + * @a categories. + */ +ppc_exc_category ppc_exc_category_for_vector( + const ppc_exc_categories *categories, + unsigned vector +); + +/** + * @brief Makes a minimal prologue for the vector @a vector with the category + * @a category. + * + * The minimal prologue will be copied to @a prologue. Not more than + * @a prologue_size bytes will be copied. Returns the actual minimal prologue + * size in bytes in @a prologue_size. + * + * @retval RTEMS_SUCCESSFUL Minimal prologue successfully made. + * @retval RTEMS_INVALID_ID Invalid vector number. + * @retval RTEMS_INVALID_NUMBER Invalid category. + * @retval RTEMS_INVALID_SIZE Prologue size to small. + */ +rtems_status_code ppc_exc_make_prologue( + unsigned vector, + void *vector_base, + ppc_exc_category category, + uint32_t *prologue, + size_t *prologue_size +); + +static inline void ppc_exc_initialize_interrupt_stack( + uintptr_t stack_begin, + uintptr_t stack_size +) +{ + uintptr_t stack_end = stack_begin + stack_size; + uintptr_t stack_pointer = stack_end - PPC_MINIMUM_STACK_FRAME_SIZE; + + /* Ensure proper interrupt stack alignment */ + stack_pointer &= ~((uintptr_t) CPU_STACK_ALIGNMENT - 1); + + /* Tag interrupt stack bottom */ + *(uint32_t *) stack_pointer = 0; + + /* Move interrupt stack values to special purpose registers */ + PPC_SET_SPECIAL_PURPOSE_REGISTER(SPRG1, stack_pointer); + PPC_SET_SPECIAL_PURPOSE_REGISTER(SPRG2, stack_begin); +} + +/** + * @brief Initializes the exception handling. + * + * @see ppc_exc_initialize(). + */ +void ppc_exc_initialize_with_vector_base( + uintptr_t interrupt_stack_begin, + uintptr_t interrupt_stack_size, + void *vector_base +); + +/** + * @brief Initializes the exception handling. + * + * If the initialization fails, then this is a fatal error. The fatal error + * source is RTEMS_FATAL_SOURCE_BSP and the fatal error code is + * PPC_FATAL_EXCEPTION_INITIALIZATION. + * + * Possible error reasons are + * - no category set available for the current CPU, + * - the register r13 does not point to the small data area anchor required by + * SVR4/EABI, or + * - the minimal prologue creation failed. + */ +static inline void ppc_exc_initialize( + uintptr_t interrupt_stack_begin, + uintptr_t interrupt_stack_size +) +{ + ppc_exc_initialize_with_vector_base( + interrupt_stack_begin, + interrupt_stack_size, + NULL + ); +} + +/** + * @brief High-level exception handler type. + * + * @retval 0 The exception was handled and normal execution may resume. + * @retval -1 Reject the exception resulting in a call of the global exception + * handler. + * @retval other Reserved, do not use. + */ +typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned vector); + +/** + * @brief Default high-level exception handler. + * + * @retval -1 Always. + */ +int ppc_exc_handler_default(BSP_Exception_frame *f, unsigned int vector); + +#ifndef PPC_EXC_CONFIG_BOOKE_ONLY + +/** + * @brief Bits for MSR update. + * + * Bits in MSR that are enabled during execution of exception handlers / ISRs + * (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should + * be set to 0 during initialization) + * + * By default, the setting of these bits that is in effect when exception + * handling is initialized is used. + */ +extern uint32_t ppc_exc_msr_bits; + +#endif /* PPC_EXC_CONFIG_BOOKE_ONLY */ + +/** + * @brief Cache write back check flag. + * + * (See README under CAVEATS). During initialization + * a check is performed to assert that write-back + * caching is enabled for memory accesses. If a BSP + * runs entirely without any caching then it should + * set this variable to zero prior to initializing + * exceptions in order to skip the test. + * NOTE: The code does NOT support mapping memory + * with cache-attributes other than write-back + * (unless the entire cache is physically disabled) + */ +extern uint32_t ppc_exc_cache_wb_check; + +#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER + /** + * @brief High-level exception handler table. + */ + extern ppc_exc_handler_t ppc_exc_handler_table [LAST_VALID_EXC + 1]; + + /** + * @brief Global exception handler. + */ + extern exception_handler_t globalExceptHdl; +#else /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ + /** + * @brief High-level exception handler table. + */ + extern const ppc_exc_handler_t ppc_exc_handler_table [LAST_VALID_EXC + 1]; + + /** + * @brief Interrupt dispatch routine provided by BSP. + */ + void bsp_interrupt_dispatch(uintptr_t exception_number); +#endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ + +/** + * @brief Set high-level exception handler. + * + * Hook C exception handlers. + * - handlers for asynchronous exceptions run on the ISR stack + * with thread-dispatching disabled. + * - handlers for synchronous exceptions run on the task stack + * with thread-dispatching enabled. + * + * If a particular slot is NULL then the traditional 'globalExcHdl' is used. + * + * ppc_exc_set_handler() registers a handler (returning 0 on success, + * -1 if the vector argument is too big). + * + * It is legal to set a NULL handler. This leads to the globalExcHdl + * being called if an exception for 'vector' occurs. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid vector number. + * @retval RTEMS_RESOURCE_IN_USE Handler table is read-only and handler does + * not match. + */ +rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t hdl); + +/** + * @brief Returns the currently active high-level exception handler. + */ +ppc_exc_handler_t ppc_exc_get_handler(unsigned vector); + +/** + * @brief Function for DAR access. + * + * CPU support may store the address of a function here + * that can be used by the default exception handler to + * obtain fault-address info which is helpful. Unfortunately, + * the SPR holding this information is not uniform + * across PPC families so we need assistance from + * CPU support + */ +extern uint32_t (*ppc_exc_get_DAR)(void); + +void +ppc_exc_wrapup(BSP_Exception_frame *f); + +/** + * @brief Standard aligment handler. + * + * @retval 0 Performed a dcbz instruction. + * @retval -1 Otherwise. + */ +int ppc_exc_alignment_handler(BSP_Exception_frame *frame, unsigned excNum); + +/** @} */ + +/* + * Compatibility with pc386 + */ +typedef exception_handler_t cpuExcHandlerType; + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIBCPU_VECTORS_H */ diff --git a/bsps/powerpc/include/bsp/vpd.h b/bsps/powerpc/include/bsp/vpd.h new file mode 100644 index 0000000000..23e49ac9f0 --- /dev/null +++ b/bsps/powerpc/include/bsp/vpd.h @@ -0,0 +1,143 @@ +#ifndef PPC_MOTLOAD_VPD_H +#define PPC_MOTLOAD_VPD_H + +/* MotLoad VPD format */ + +/* Till Straumann, 2005; see copyright notice at the end of this file */ + +#ifdef __cplusplus + extern "C" { +#endif + +/* +VPD = "MOTOROLA" , { field } + +field = type_byte, length_byte, { data } +*/ + +/* Known fields so far */ +typedef enum { + ProductIdent = 0x01, /* String */ + AssemblyNumber = 0x02, /* String */ + SerialNumber = 0x03, /* String */ + CpuClockHz = 0x05, /* binary (5bytes), 0x01 byte appended to unsigned int */ + BusClockHz = 0x06, /* binary (5bytes), 0x01 byte appended to unsigned int */ + EthernetAddr = 0x08, /* binary (7bytes), 0x00 byte appended, 2nd has 0x01 appended */ + CpuType = 0x09, /* String */ + EEpromCrc = 0x0a, /* binary (4bytes) */ + FlashConfig = 0x0b, /* binary */ + L2CacheConfig = 0x0e, /* binary */ + VPDRevision = 0x0f, /* binary (4bytes) */ + L3CacheConfig = 0x19, /* binary */ + End = 0xff +} VpdKey; + +typedef struct { + VpdKey key; /* key for the data item to be read into 'buf' */ + char instance; /* instance # (starting with 0) - some keys are present more than one time */ + void *buf; /* pointer to area where the data item is to be stored */ + int buflen; /* available space in the buffer */ + char found; /* set by BSP_vpdRetrieveFields() to the original length as found in the PROM */ +} VpdBufRec, *VpdBuf; + + +#define VPD_END { key:End, } + + +/* Scan the VPD EEPROM for a number of fields + * + * Pass an array of VpdBufRec items. The routine + * fills the 'buf'fers for all keys that are found + * and sets the 'found' field to the original length + * of the data (i.e., as found in the PROM) so that + * the routine could be called again with a larger + * buffer. + * + * NOTE: - the array must be terminated by a VPD_END record! + * - no CRC check is performed. + * - INTERRUPT MANAGEMENT MUST BE FUNCTIONAL + * + * RETURNS: 0 on success, -1 if any read errors were + * encountered or if the "MOTOROLA" header + * was not found. + */ +int +BSP_vpdRetrieveFields(VpdBuf data); + +/* Example: + * Read 2nd ethernet address: + * + * char enet_addr_2[6]; + * + * VpdBufRec enetVpd [] = { + * { key: EthernetAddr, instance: 1, buf: enet_addr_2, buflen: 2}, + * VPD_END + * }; + * + * if ( BSP_vpdRetrieveFields(enetVpd) ) { + * error("ethernet address couldn't be read\n"); + * } else if ( enetVpd[0].found < 6 ) { + * error("2nd ethernet address not found in VPD\n"); + * } else { + * use_it(enet_addr_2); + * } + */ + + +/* Simple wrapper if only one field is needed + * + * RETURNS: original length if key is found, -1 on error or if key is not found + */ +int +BSP_vpdRetrieveKey(VpdKey k, void *buf, int buflen, int instance); + +#ifdef __cplusplus + } +#endif + +/* + * Authorship + * ---------- + * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was + * created by Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'beatnik' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#endif diff --git a/bsps/powerpc/include/ictrl.h b/bsps/powerpc/include/ictrl.h new file mode 100644 index 0000000000..303ece825d --- /dev/null +++ b/bsps/powerpc/include/ictrl.h @@ -0,0 +1,75 @@ +#ifndef _ICTRL_H +#define _ICTRL_H + +/* + * mpc505/509 external interrupt controller management. + * + * FIXME: should be somehow merged into general RTEMS interrupt + * management code. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define _SIU_IRQENABLE ((unsigned long volatile *const)0x8007EFA8) +#define _SIU_IRQPEND ((unsigned long volatile *const)0x8007EFA0) + +/* Interrupt masks. */ +enum { + IMASK_EXT0 = 0x80000000, + IMASK_EXT1 = 0x20000000, + IMASK_EXT2 = 0x08000000, + IMASK_EXT3 = 0x02000000, + IMASK_EXT4 = 0x00800000, + IMASK_EXT5 = 0x00200000, + IMASK_EXT6 = 0x00080000, + IMASK_ALL = IMASK_EXT0 | IMASK_EXT1 | IMASK_EXT2 | IMASK_EXT3 | + IMASK_EXT4 | IMASK_EXT5 | IMASK_EXT6 +}; + +/* Interrupt numbers. */ +typedef enum { + IRQ_EXT0, + IRQ_EXT1, + IRQ_EXT2, + IRQ_EXT3, + IRQ_EXT4, + IRQ_EXT5, + IRQ_EXT6, + NUM_IRQS +} ExtInt; + +/* Type of external interrupt handlers */ +typedef void (*ExtIsrHandler) (void); + +/* Initialization. Must be called once after RTEMS interrupts sybsystem + is initiailized. 'predriver_hook' is one of such places. */ +extern void extIsrInit( void ); + +/* Set interrupt handler 'handler' for external interrupt number + 'interrupt'. */ +extern void extIrqSetHandler(ExtInt interrupt, ExtIsrHandler handler); + +/* Check is external interrupt 'irq' (IMASK_XXXX) is pended. */ +#define extIrqIsSet(irq) \ + (*_SIU_IRQPEND & (irq)) + +/* Enable external interrupt 'irq' (IMASK_XXXX) processing. */ +#define extIrqEnable(irq) \ + (*_SIU_IRQENABLE |= (irq)) + +/* Disable external interrupt 'irq' (IMASK_XXXX) processing. */ +#define extIrqDisable(irq) \ + (*_SIU_IRQENABLE &= ~(irq)) + +/* Check if external interrupt 'irq' (IMASK_XXXX) processing is + enabled. */ +#define extIrqGetEnable \ + (*_SIU_IRQENABLE) + +#ifdef __cplusplus +} +#endif + +#endif /* _ICTRL_H */ diff --git a/bsps/powerpc/include/libcpu/bat.h b/bsps/powerpc/include/libcpu/bat.h new file mode 100644 index 0000000000..2a27e810ee --- /dev/null +++ b/bsps/powerpc/include/libcpu/bat.h @@ -0,0 +1,85 @@ +/* + * bat.h + * + * This file contains declaration of C function to + * Instantiate 60x/7xx ppc Block Address Translation (BAT) registers. + * More detailed information can be found on motorola + * site and more precisely in the following book : + * + * MPC750 + * Risc Microporcessor User's Manual + * Motorola REF : MPC750UM/AD 8/97 + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_BAT_H +#define _LIBCPU_BAT_H + +#include +#include + +#define IO_PAGE (_PAGE_NO_CACHE | _PAGE_GUARDED | _PAGE_RW) + +#ifndef ASM +/* Take no risks -- the essential parts of this routine run with + * interrupts disabled! + * + * The routine does basic parameter checks: + * - Index must be 0..3 (0..7 on 7455, 7457). + * If an index > 3 is requested the 745x is + * programmed to enable the higher BATs. + * - Size must be a power of two and <= 1<<28 + * (<=1<<31 on 7455, 7457. Also, on these processors + * the special value 0xffffffff is allowed which stands + * for 1<<32). + * If a size > 1<<28 is requested, the 745x is + * programmed to enable the larger block sizes. + * - Bat ranges must not overlap. + * - Physical & virtual addresses must be aligned + * to the size. + * + * RETURNS: zero on success, nonzero on failure. + */ +extern int setdbat(int bat_index, unsigned long virt, unsigned long phys, + unsigned int size, int flags); + +/* Same as setdbat but sets IBAT */ +extern int setibat(int bat_index, unsigned long virt, unsigned long phys, + unsigned int size, int flags); + +/* read DBAT # 'idx' into *pu / *pl. NULL pointers may be passed. + * If pu and pl are NULL, the bat contents are dumped to the console (printk). + * + * RETURNS: upper BAT contents or (-1) if index is invalid + */ +extern int getdbat(int bat_index, unsigned long *pu, unsigned long *pl); + +/* Same as getdbat but reads IBAT */ +extern int getibat(int bat_index, unsigned long *pu, unsigned long *pl); + +/* Do not use the asm-routines; they are obsolete; use setdbat() instead */ +extern void asm_setdbat0(unsigned int uperPart, unsigned int lowerPart); +extern void asm_setdbat1(unsigned int uperPart, unsigned int lowerPart); +extern void asm_setdbat2(unsigned int uperPart, unsigned int lowerPart); +extern void asm_setdbat3(unsigned int uperPart, unsigned int lowerPart); +#else + +/* Initialize all bats (upper and lower) to zero. This routine should *only* + * be called during early BSP initialization when no C-ABI is available + * yet. + * This routine clobbers r3 and r4. + * NOTE: on 7450 CPUs all 8 dbat/ibat units are cleared. On 601 CPUs only + * 4 ibats. + */ + .globl CPU_clear_bats_early + .type CPU_clear_bats_early,@function + +#endif + +#endif /* _LIBCPU_BAT_H */ diff --git a/bsps/powerpc/include/libcpu/byteorder.h b/bsps/powerpc/include/libcpu/byteorder.h new file mode 100644 index 0000000000..0654fefb58 --- /dev/null +++ b/bsps/powerpc/include/libcpu/byteorder.h @@ -0,0 +1,54 @@ +/* + * byteorder.h + * + * This file contains inline implementation of function to + * deal with endian conversion. + * + * It is a stripped down version of linux ppc file... + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_BYTEORDER_H +#define _LIBCPU_BYTEORDER_H + +#ifdef __cplusplus +extern "C" { +#endif + +static inline unsigned ld_le16(volatile uint16_t *addr) +{ + unsigned val; + + __asm__ volatile ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); + return val; +} + +static inline void st_le16(volatile uint16_t *addr, unsigned val) +{ + __asm__ volatile ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); +} + +static inline unsigned ld_le32(volatile uint32_t *addr) +{ + unsigned val; + + __asm__ volatile ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); + return val; +} + +static inline void st_le32(volatile uint32_t *addr, unsigned val) +{ + __asm__ volatile ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _LIBCPU_BYTEORDER_H */ diff --git a/bsps/powerpc/include/libcpu/c_clock.h b/bsps/powerpc/include/libcpu/c_clock.h new file mode 100644 index 0000000000..bd4918fb44 --- /dev/null +++ b/bsps/powerpc/include/libcpu/c_clock.h @@ -0,0 +1,56 @@ +/* + * Clock Tick Device Driver + * + * This routine utilizes the Decrementer Register common to the PPC family. + * + * The tick frequency is directly programmed to the configured number of + * microseconds per tick. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified to support the MPC750. + * Modifications Copyright (c) 1999 Eric Valette valette@crf.canon.fr + */ + +#ifndef _LIBCPU_C_CLOCK_H +#define _LIBCPU_C_CLOCK_H + +#include + +/* + * These functions and variables represent the API exported by the + * CPU to the BSP. + */ + +extern void clockOff (void* unused); +extern void clockOn (void* unused); +extern void clockIsr (void* unused); +/* bookE decrementer is slightly different */ +extern void clockIsrBookE (void *unused); +extern int clockIsOn (void* unused); + +/* + * These functions and variables represent the assumptions of this + * driver on the BSP. + */ + +extern int BSP_disconnect_clock_handler (void); +/* + * PCI Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * processor clock frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; + +#endif diff --git a/bsps/powerpc/include/libcpu/cpuIdent.h b/bsps/powerpc/include/libcpu/cpuIdent.h new file mode 100755 index 0000000000..e051deba92 --- /dev/null +++ b/bsps/powerpc/include/libcpu/cpuIdent.h @@ -0,0 +1,158 @@ +/* + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * Added MPC8260 Andy Dachs + * Surrey Satellite Technology Limited + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_CPUIDENT_H +#define _LIBCPU_CPUIDENT_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ASM +typedef enum +{ + PPC_601 = 0x1, + PPC_5XX = 0x2, + PPC_603 = 0x3, + PPC_604 = 0x4, + PPC_603e = 0x6, + PPC_603ev = 0x7, + PPC_750 = 0x8, + PPC_750_IBM = 0x7000, + PPC_604e = 0x9, + PPC_604r = 0xA, + PPC_7400 = 0xC, + PPC_405 = 0x2001, /* Xilinx Virtex-II Pro or -4 */ + PPC_405EX = 0x1291, /* + 405EXr */ + PPC_405GP = 0x4011, /* + 405CR */ + PPC_405GPr = 0x5091, + PPC_405EZ = 0x4151, + PPC_405EP = 0x5121, + PPC_440 = 0x7ff2, /* Xilinx Virtex-5*/ + PPC_7455 = 0x8001, /* Kate Feng */ + PPC_7457 = 0x8002, + PPC_620 = 0x16, + PPC_860 = 0x50, + PPC_821 = PPC_860, + PPC_823 = PPC_860, + PPC_8260 = 0x81, + PPC_8240 = PPC_8260, + PPC_8245 = 0x8081, + PPC_8540 = 0x8020, + PPC_e500v2 = 0x8021, + PPC_e6500 = 0x8040, + PPC_603le = 0x8082, /* 603le core, in MGT5100 and MPC5200 */ + PPC_e300c1 = 0x8083, /* e300c1 core, in MPC83xx*/ + PPC_e300c2 = 0x8084, /* e300c2 core */ + PPC_e300c3 = 0x8085, /* e300c3 core */ + PPC_e200z0 = 0x8170, + PPC_e200z1 = 0x8140, + PPC_e200z4 = 0x8150, + PPC_e200z6 = 0x8110, + PPC_e200z7 = 0x8160, + PPC_PSIM = 0xfffe, /* GDB PowerPC simulator -- fake version */ + PPC_UNKNOWN = 0xffff +} ppc_cpu_id_t; + +/* Bitfield of for identifying features or groups of cpu flavors. + * DO NOT USE DIRECTLY (as implementation may change) + * only use the 'ppc_is_xxx() / ppc_has_xxx()' macros/inlines + * below. + */ + +typedef struct { + unsigned has_altivec : 1; + unsigned has_fpu : 1; + unsigned has_hw_ptbl_lkup : 1; +#define PPC_BOOKE_405 1 /* almost like booke but with some significant differences */ +#define PPC_BOOKE_STD 2 +#define PPC_BOOKE_E500 3 /* bookE with extensions */ + unsigned is_bookE : 2; + unsigned has_16byte_clne : 1; + unsigned is_60x : 1; + unsigned has_8_bats : 1; + unsigned has_epic : 1; + unsigned has_shadowed_gprs : 1; +} ppc_feature_t; + +extern ppc_feature_t current_ppc_features; +extern ppc_cpu_id_t current_ppc_cpu; + +typedef unsigned short ppc_cpu_revision_t; + +extern ppc_cpu_id_t get_ppc_cpu_type (void); +extern const char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu); +extern ppc_cpu_revision_t get_ppc_cpu_revision (void); +extern ppc_cpu_revision_t current_ppc_revision; + +/* PUBLIC ACCESS ROUTINES */ +#define _PPC_FEAT_DECL(x) \ +static inline unsigned ppc_cpu_##x(void) { \ + if ( PPC_UNKNOWN == current_ppc_cpu ) \ + get_ppc_cpu_type(); \ + return current_ppc_features.x; \ +} + +_PPC_FEAT_DECL(has_altivec) +/* has_fpu not implemented yet */ +_PPC_FEAT_DECL(has_hw_ptbl_lkup) +_PPC_FEAT_DECL(is_bookE) +_PPC_FEAT_DECL(is_60x) +_PPC_FEAT_DECL(has_8_bats) +_PPC_FEAT_DECL(has_epic) +_PPC_FEAT_DECL(has_shadowed_gprs) + +#undef _PPC_FEAT_DECL + +static inline ppc_cpu_id_t ppc_cpu_current(void) +{ + return current_ppc_cpu; +} + +static inline bool ppc_cpu_is_e200(void) +{ + return (ppc_cpu_current() & 0xff80) == 0x8100; +} + +static inline bool ppc_cpu_is_specific_e200(ppc_cpu_id_t id) +{ + return (ppc_cpu_current() & 0xfff0) == id; +} + +static inline bool ppc_cpu_is_e300(void) +{ + return ppc_cpu_current() == PPC_e300c1 + || ppc_cpu_current() == PPC_e300c2 + || ppc_cpu_current() == PPC_e300c3; +} + +static inline bool ppc_cpu_is_e500(void) +{ + return ppc_cpu_current() == PPC_8540 + || ppc_cpu_current() == PPC_e500v2; +} + +static inline bool ppc_cpu_is(ppc_cpu_id_t cpu) +{ + return ppc_cpu_current() == cpu; +} + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/include/libcpu/e500_mmu.h b/bsps/powerpc/include/libcpu/e500_mmu.h new file mode 100644 index 0000000000..84920e0d14 --- /dev/null +++ b/bsps/powerpc/include/libcpu/e500_mmu.h @@ -0,0 +1,230 @@ +#ifndef RTEMS_E500_MMU_DRIVER_H +#define RTEMS_E500_MMU_DRIVER_H + +/* + * Routines to manipulate e500 TLBs; TLB0 (fixed 4k page size) + * is not very useful so we mostly focus on TLB1 (variable page size) + */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Some routines require or return a index 'key'. This + * is simply the TLB entry # ORed with E500_SELTLB_0 + * or E500_SELTLB_1 specifying an entry in TLB0 or TLB1, + * respectively. + */ +typedef int rtems_e500_tlb_idx; +#define E500_SELTLB_0 0x0000 +#define E500_SELTLB_1 0x1000 + +/* Cache the relevant TLB1 entries so that we can + * make sure the user cannot create conflicting + * (overlapping) entries. + * Keep them public for informational purposes. + */ +typedef struct { + struct { + uint32_t va_epn: 20; + uint32_t va_tid: 12; + } va; + uint32_t rpn; + struct { + uint32_t sz: 4; + uint32_t ts: 1; + uint32_t v: 1; + uint32_t perm: 10; + uint32_t wimge: 7; + } att; +} E500_tlb_va_cache_t; + +extern E500_tlb_va_cache_t rtems_e500_tlb_va_cache[16]; + +/* + * Dump (cleartext) content info from cached TLB entries + * to a file (stdout if f==NULL). + */ +void +rtems_e500_dmptlbc(FILE *f); + +/* + * Read a TLB entry from the hardware; if it is a TLB1 entry + * then the current settings are stored in the + * rtems_e500_tlb_va_cache[] structure. + * + * The routine can perform this operation quietly or + * print information to a file. + * + * 'key': TLB entry index ORed with selector bit + * (E500_SELTLB_0 for TLB0, E500_SELTLB_1 for TLB1). + * 'quiet': perform operation silently (no info printed) + * if nonzero. + * 'f': open FILE where to print information. May be + * NULL in which case 'stdout' is used. + * + * RETURNS: + * 0: success; TLB entry is VALID + * +1: success but TLB entry is INVALID + * < 0: error (-1: invalid argument) + */ +int +rtems_e500_prtlb(rtems_e500_tlb_idx key, int quiet, FILE *f); + +/* Initialize cache; verify that TLB0 is unused; + * + * RETURNS: zero on success, nonzero on error (TLB0 + * seems to be in use); in this case the + * driver will refuse to change TLB1 entries + * (other than disabling them). + */ +int +rtems_e500_initlb(void); + +/* + * Write TLB1 entry (can also be used to disable an entry). + * + * The routine checks against the cached data in + * rtems_e500_tlb_va[] to prevent the user from generating + * overlapping entries. + * + * 'idx': TLB 1 entry # to manipulate + * 'ea': Effective address (must be page aligned) + * 'pa': Physical address (must be page aligned) + * 'sz': Page size selector; page size is + * 1024 * 2^(2*sz) bytes. + * 'sz' may also be one of the following: + * - page size in bytes ( >= 1024 ); the selector + * value is then computed by this routine. + * However, 'sz' must be a valid page size + * or -1 will be returned. + * - a value < 0 to invalidate/disable the + * TLB entry. + * 'attr': Page attributes; ORed combination of WIMGE, + * PERMissions, TID and TS. Use ATTR_xxx macros + * + * RETURNS: 0 on success, nonzero on error: + * + * >0: requested mapping would overlap with + * existing mapping in other entry. Return + * value gives conflicting entry + 1; i.e., + * if a value of 4 is returned then the request + * conflicts with existing mapping in entry 3. + * -1: invalid argument + * -3: driver not initialized (or initialization + * failed because TLB0 is in use). + * <0: other error + * + */ +#define E500_TLB_ATTR_WIMGE(x) ((x)&0x7f) /* includes user bits */ +#define E500_TLB_ATTR_WIMGE_GET(x) ((x)&0x7f) +#define E500_TLB_ATTR_TS (1<<7) +#define E500_TLB_ATTR_PERM(x) (((x)&0x3ff)<<8) +#define E500_TLB_ATTR_PERM_GET(x) (((x)>>8)&0x3ff) +#define E500_TLB_ATTR_TID(x) (((x)&0xfff)<<20) +#define E500_TLB_ATTR_TID_GET(x) (((x)>>20)&0xfff) + +int +rtems_e500_wrtlb(int idx, uint32_t ea, uint32_t pa, int sz, uint32_t attr); + +/* + * Check if a ts/tid/ea/sz mapping overlaps + * with an existing entry. + * + * ASSUMPTION: all TLB0 (fixed 4k pages) are invalid and always unused. + * + * NOTE: 'sz' is the 'logarithmic' size selector; the page size + * is 1024*2^(2*sz). + * + * RETURNS: + * >= 0: index of TLB1 entry that already provides a mapping + * which overlaps within the ea range. + * -1: SUCCESS (no conflicting entry found) + * <=-2: ERROR (invalid input) + */ +int +rtems_e500_matchtlb(uint32_t ea, uint32_t tid, int ts, int sz); + +/* Find TLB index that maps 'ea/as' combination + * + * RETURNS: index 'key'; i.e., the index number plus + * a bit (E500_SELTLB_1) which indicates whether + * the mapping was found in TLB0 (4k fixed page + * size) or in TLB1 (variable page size). + * + * On error (no mapping) -1 is returned. + */ +rtems_e500_tlb_idx +rtems_e500_ftlb(uint32_t ea, int as); + +/* Mark TLB entry as invalid ('disabled'). Unlike + * rtems_e500_wrtlb() with a negative size argument + * this routine also can disable TLB0 entries. + * + * 'key': TLB entry index ORed with selector bit + * (E500_SELTLB_0 for TLB0, E500_SELTLB_1 for TLB1). + * + * RETURNS: zero on success, nonzero on error (TLB + * unchanged). + * + * NOTE: If a TLB1 entry is disabled the associated + * entry in rtems_e500_va_cache[] is also + * marked as disabled. + */ +int +rtems_e500_clrtlb(rtems_e500_tlb_idx key); + +#ifdef __cplusplus +}; +#endif + +#endif diff --git a/bsps/powerpc/include/libcpu/io.h b/bsps/powerpc/include/libcpu/io.h new file mode 100644 index 0000000000..841df81f47 --- /dev/null +++ b/bsps/powerpc/include/libcpu/io.h @@ -0,0 +1,139 @@ +/* + * io.h + * + * This file contains inline implementation of function to + * deal with IO. + * + * It is a stripped down version of linux ppc file... + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef _LIBCPU_IO_H +#define _LIBCPU_IO_H + + +#define PREP_ISA_IO_BASE 0x80000000 +#define PREP_ISA_MEM_BASE 0xc0000000 +#define PREP_PCI_DRAM_OFFSET 0x80000000 + +#define CHRP_ISA_IO_BASE 0xfe000000 +#define CHRP_ISA_MEM_BASE 0xfd000000 +#define CHRP_PCI_DRAM_OFFSET 0x00000000 + +/* _IO_BASE, _ISA_MEM_BASE, PCI_DRAM_OFFSET are now defined by bsp.h */ + +#ifndef ASM + +#include /* for _IO_BASE & friends */ +#include + +/* NOTE: The use of these macros is DISCOURAGED. + * you should consider e.g. using in_xxx / out_xxx + * with a device specific base address that is + * defined by the BSP. This makes drivers easier + * to port. + */ +#define inb(port) in_8((uint8_t *)((port)+_IO_BASE)) +#define outb(val, port) out_8((uint8_t *)((port)+_IO_BASE), (val)) +#define inw(port) in_le16((uint16_t *)((port)+_IO_BASE)) +#define outw(val, port) out_le16((uint16_t *)((port)+_IO_BASE), (val)) +#define inl(port) in_le32((uint32_t *)((port)+_IO_BASE)) +#define outl(val, port) out_le32((uint32_t *)((port)+_IO_BASE), (val)) + +/* + * Enforce In-order Execution of I/O: + * Acts as a barrier to ensure all previous I/O accesses have + * completed before any further ones are issued. + */ +static inline void eieio(void) +{ + __asm__ __volatile__ ("eieio"); +} + + +/* Enforce in-order execution of data I/O. + * No distinction between read/write on PPC; use eieio for all three. + */ +#define iobarrier_rw() eieio() +#define iobarrier_r() eieio() +#define iobarrier_w() eieio() + +/* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + */ +static inline uint8_t in_8(const volatile uint8_t *addr) +{ + uint8_t ret; + + __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +static inline void out_8(volatile uint8_t *addr, uint8_t val) +{ + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +static inline uint16_t in_le16(const volatile uint16_t *addr) +{ + uint16_t ret; + + __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +static inline uint16_t in_be16(const volatile uint16_t *addr) +{ + uint16_t ret; + + __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +static inline void out_le16(volatile uint16_t *addr, uint16_t val) +{ + __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +static inline void out_be16(volatile uint16_t *addr, uint16_t val) +{ + __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +static inline uint32_t in_le32(const volatile uint32_t *addr) +{ + uint32_t ret; + + __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +static inline uint32_t in_be32(const volatile uint32_t *addr) +{ + uint32_t ret; + + __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +static inline void out_le32(volatile uint32_t *addr, uint32_t val) +{ + __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +static inline void out_be32(volatile uint32_t *addr, uint32_t val) +{ + __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +#endif /* ASM */ +#endif /* _LIBCPU_IO_H */ diff --git a/bsps/powerpc/include/libcpu/irq.h b/bsps/powerpc/include/libcpu/irq.h new file mode 100644 index 0000000000..ab06041d24 --- /dev/null +++ b/bsps/powerpc/include/libcpu/irq.h @@ -0,0 +1,199 @@ +/* + * irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * + * MPC5xx port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from libbsp/powerpc/mbx8xx/irq/irq.h: + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_IRQ_H +#define _LIBCPU_IRQ_H + +#include + +#define CPU_ASM_IRQ_VECTOR_BASE 0x0 + +#ifndef ASM + +extern volatile unsigned int ppc_cached_irq_mask; + +/* + * Symblolic IRQ names and related definitions. + */ + + /* + * Base vector for our USIU IRQ handlers. + */ +#define CPU_USIU_VECTOR_BASE (CPU_ASM_IRQ_VECTOR_BASE) + /* + * USIU IRQ handler related definitions + */ +#define CPU_USIU_IRQ_COUNT (16) /* 16 reserved but in the future... */ +#define CPU_USIU_IRQ_MIN_OFFSET (0) +#define CPU_USIU_IRQ_MAX_OFFSET (CPU_USIU_IRQ_MIN_OFFSET + CPU_USIU_IRQ_COUNT - 1) + /* + * UIMB IRQ handlers related definitions + */ +#define CPU_UIMB_IRQ_COUNT (32 - 8) /* first 8 overlap USIU */ +#define CPU_UIMB_IRQ_MIN_OFFSET (CPU_USIU_IRQ_COUNT + CPU_USIU_VECTOR_BASE) +#define CPU_UIMB_IRQ_MAX_OFFSET (CPU_UIMB_IRQ_MIN_OFFSET + CPU_UIMB_IRQ_COUNT - 1) + /* + * PowerPc exceptions handled as interrupt where a rtems managed interrupt + * handler might be connected + */ +#define CPU_PROC_IRQ_COUNT (1) +#define CPU_PROC_IRQ_MIN_OFFSET (CPU_UIMB_IRQ_MAX_OFFSET + 1) +#define CPU_PROC_IRQ_MAX_OFFSET (CPU_PROC_IRQ_MIN_OFFSET + CPU_PROC_IRQ_COUNT - 1) + /* + * Summary + */ +#define CPU_IRQ_COUNT (CPU_PROC_IRQ_MAX_OFFSET + 1) +#define CPU_MIN_OFFSET (CPU_USIU_IRQ_MIN_OFFSET) +#define CPU_MAX_OFFSET (CPU_PROC_IRQ_MAX_OFFSET) + /* + * USIU IRQ symbolic name definitions. + */ +#define CPU_USIU_EXT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 0) +#define CPU_USIU_INT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 1) + +#define CPU_USIU_EXT_IRQ_1 (CPU_USIU_IRQ_MIN_OFFSET + 2) +#define CPU_USIU_INT_IRQ_1 (CPU_USIU_IRQ_MIN_OFFSET + 3) + +#define CPU_USIU_EXT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 4) +#define CPU_USIU_INT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 5) + +#define CPU_USIU_EXT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 6) +#define CPU_USIU_INT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 7) + +#define CPU_USIU_EXT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 8) +#define CPU_USIU_INT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 9) + +#define CPU_USIU_EXT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 10) +#define CPU_USIU_INT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 11) + +#define CPU_USIU_EXT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 12) +#define CPU_USIU_INT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 13) + +#define CPU_USIU_EXT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 14) +#define CPU_USIU_INT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 15) + + /* + * Symbolic names for UISU interrupt sources. + */ +#define CPU_PERIODIC_TIMER (CPU_USIU_INT_IRQ_6) +#define CPU_UIMB_INTERRUPT (CPU_USIU_INT_IRQ_7) + + /* + * UIMB IRQ symbolic name definitions. The first 8 sources are aliases to + * the USIU interrupts of the same number, because they are detected in + * the USIU pending register rather than the UIMB pending register. + */ +#define CPU_UIMB_IRQ_0 (CPU_USIU_INT_IRQ_0) +#define CPU_UIMB_IRQ_1 (CPU_USIU_INT_IRQ_1) +#define CPU_UIMB_IRQ_2 (CPU_USIU_INT_IRQ_2) +#define CPU_UIMB_IRQ_3 (CPU_USIU_INT_IRQ_3) +#define CPU_UIMB_IRQ_4 (CPU_USIU_INT_IRQ_4) +#define CPU_UIMB_IRQ_5 (CPU_USIU_INT_IRQ_5) +#define CPU_UIMB_IRQ_6 (CPU_USIU_INT_IRQ_6) +#define CPU_UIMB_IRQ_7 (CPU_USIU_INT_IRQ_7) + +#define CPU_UIMB_IRQ_8 (CPU_UIMB_IRQ_MIN_OFFSET+ 0) +#define CPU_UIMB_IRQ_9 (CPU_UIMB_IRQ_MIN_OFFSET+ 1) +#define CPU_UIMB_IRQ_10 (CPU_UIMB_IRQ_MIN_OFFSET+ 2) +#define CPU_UIMB_IRQ_11 (CPU_UIMB_IRQ_MIN_OFFSET+ 3) +#define CPU_UIMB_IRQ_12 (CPU_UIMB_IRQ_MIN_OFFSET+ 4) +#define CPU_UIMB_IRQ_13 (CPU_UIMB_IRQ_MIN_OFFSET+ 5) +#define CPU_UIMB_IRQ_14 (CPU_UIMB_IRQ_MIN_OFFSET+ 6) +#define CPU_UIMB_IRQ_15 (CPU_UIMB_IRQ_MIN_OFFSET+ 7) +#define CPU_UIMB_IRQ_16 (CPU_UIMB_IRQ_MIN_OFFSET+ 8) +#define CPU_UIMB_IRQ_17 (CPU_UIMB_IRQ_MIN_OFFSET+ 9) +#define CPU_UIMB_IRQ_18 (CPU_UIMB_IRQ_MIN_OFFSET+ 0) +#define CPU_UIMB_IRQ_19 (CPU_UIMB_IRQ_MIN_OFFSET+11) +#define CPU_UIMB_IRQ_20 (CPU_UIMB_IRQ_MIN_OFFSET+12) +#define CPU_UIMB_IRQ_21 (CPU_UIMB_IRQ_MIN_OFFSET+13) +#define CPU_UIMB_IRQ_22 (CPU_UIMB_IRQ_MIN_OFFSET+14) +#define CPU_UIMB_IRQ_23 (CPU_UIMB_IRQ_MIN_OFFSET+15) +#define CPU_UIMB_IRQ_24 (CPU_UIMB_IRQ_MIN_OFFSET+16) +#define CPU_UIMB_IRQ_25 (CPU_UIMB_IRQ_MIN_OFFSET+17) +#define CPU_UIMB_IRQ_26 (CPU_UIMB_IRQ_MIN_OFFSET+18) +#define CPU_UIMB_IRQ_27 (CPU_UIMB_IRQ_MIN_OFFSET+19) +#define CPU_UIMB_IRQ_28 (CPU_UIMB_IRQ_MIN_OFFSET+20) +#define CPU_UIMB_IRQ_29 (CPU_UIMB_IRQ_MIN_OFFSET+21) +#define CPU_UIMB_IRQ_30 (CPU_UIMB_IRQ_MIN_OFFSET+22) +#define CPU_UIMB_IRQ_31 (CPU_UIMB_IRQ_MIN_OFFSET+23) + + /* + * Symbolic names for UIMB interrupt sources. + */ +#define CPU_IRQ_SCI (CPU_UIMB_IRQ_5) + + /* + * Processor exceptions handled as rtems IRQ symbolic name definitions. + */ +#define CPU_DECREMENTER (CPU_PROC_IRQ_MIN_OFFSET) + +/* + * Convert an rtems_irq_number constant to an interrupt level + * suitable for programming into an I/O device's interrupt level field. + */ +int CPU_irq_level_from_symbolic_name(const rtems_irq_number name); + +/*-------------------------------------------------------------------------+ +| Function Prototypes. ++--------------------------------------------------------------------------*/ + +extern void CPU_rtems_irq_mng_init(unsigned cpuId); + +typedef struct MPC5XX_Interrupt_frame { + uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ + uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ + + /* This is what is left out of the primary contexts */ + uint32_t gpr0; + uint32_t gpr2; /* play safe */ + uint32_t gpr3; + uint32_t gpr4; + uint32_t gpr5; + uint32_t gpr6; + uint32_t gpr7; + uint32_t gpr8; + uint32_t gpr9; + uint32_t gpr10; + uint32_t gpr11; + uint32_t gpr12; + uint32_t gpr13; /* Play safe */ + uint32_t gpr28; /* For internal use by the IRQ handler */ + uint32_t gpr29; /* For internal use by the IRQ handler */ + uint32_t gpr30; /* For internal use by the IRQ handler */ + uint32_t gpr31; /* For internal use by the IRQ handler */ + uint32_t cr; /* Bits of this are volatile, so no-one may save */ + uint32_t ctr; + uint32_t xer; + uint32_t lr; + uint32_t pc; + uint32_t msr; + uint32_t pad[3]; +} MPC5XX_Interrupt_frame; + +void C_dispatch_irq_handler(MPC5XX_Interrupt_frame *frame, unsigned int excNum); + +#endif + +#endif diff --git a/bsps/powerpc/include/libcpu/mmu.h b/bsps/powerpc/include/libcpu/mmu.h new file mode 100644 index 0000000000..d3081316eb --- /dev/null +++ b/bsps/powerpc/include/libcpu/mmu.h @@ -0,0 +1,304 @@ +/* + * mmu.h + * + * PowerPC memory management structures + * + * It is a stripped down version of linux ppc file... + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_MMU_H +#define _LIBCPU_MMU_H + +#ifndef ASM +/* Hardware Page Table Entry */ +typedef struct _PTE { + unsigned long v:1; /* Entry is valid */ + unsigned long vsid:24; /* Virtual segment identifier */ + unsigned long h:1; /* Hash algorithm indicator */ + unsigned long api:6; /* Abbreviated page index */ + unsigned long rpn:20; /* Real (physical) page number */ + unsigned long :3; /* Unused */ + unsigned long r:1; /* Referenced */ + unsigned long c:1; /* Changed */ + unsigned long w:1; /* Write-thru cache mode */ + unsigned long i:1; /* Cache inhibited */ + unsigned long m:1; /* Memory coherence */ + unsigned long g:1; /* Guarded */ + unsigned long :1; /* Unused */ + unsigned long pp:2; /* Page protection */ +} PTE; + +/* Values for PP (assumes Ks=0, Kp=1) */ +#define PP_RWXX 0 /* Supervisor read/write, User none */ +#define PP_RWRX 1 /* Supervisor read/write, User read */ +#define PP_RWRW 2 /* Supervisor read/write, User read/write */ +#define PP_RXRX 3 /* Supervisor read, User read */ + +/* Segment Register */ +typedef struct _SEGREG { + unsigned long t:1; /* Normal or I/O type */ + unsigned long ks:1; /* Supervisor 'key' (normally 0) */ + unsigned long kp:1; /* User 'key' (normally 1) */ + unsigned long n:1; /* No-execute */ + unsigned long :4; /* Unused */ + unsigned long vsid:24; /* Virtual Segment Identifier */ +} SEGREG; + +/* Block Address Translation (BAT) Registers */ +typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ + unsigned long bepi:15; /* Effective page index (virtual address) */ + unsigned long :8; /* unused */ + unsigned long w:1; + unsigned long i:1; /* Cache inhibit */ + unsigned long m:1; /* Memory coherence */ + unsigned long ks:1; /* Supervisor key (normally 0) */ + unsigned long kp:1; /* User key (normally 1) */ + unsigned long pp:2; /* Page access protections */ +} P601_BATU; + +typedef struct _BATU { /* Upper part of BAT (all except 601) */ + unsigned long bepi:15; /* Effective page index (virtual address) */ + unsigned long :4; /* Unused */ + unsigned long bl:11; /* Block size mask */ + unsigned long vs:1; /* Supervisor valid */ + unsigned long vp:1; /* User valid */ +} BATU; + +typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ + unsigned long brpn:15; /* Real page index (physical address) */ + unsigned long :10; /* Unused */ + unsigned long v:1; /* Valid bit */ + unsigned long bl:6; /* Block size mask */ +} P601_BATL; + +typedef struct _BATL { /* Lower part of BAT (all except 601) */ + unsigned long brpn:15; /* Real page index (physical address) */ + unsigned long :10; /* Unused */ + unsigned long w:1; /* Write-thru cache */ + unsigned long i:1; /* Cache inhibit */ + unsigned long m:1; /* Memory coherence */ + unsigned long g:1; /* Guarded (MBZ in IBAT) */ + unsigned long :1; /* Unused */ + unsigned long pp:2; /* Page access protections */ +} BATL; + +typedef struct _BAT { + BATU batu; /* Upper register */ + BATL batl; /* Lower register */ +} BAT; + +typedef struct _P601_BAT { + P601_BATU batu; /* Upper register */ + P601_BATL batl; /* Lower register */ +} P601_BAT; + +/* Block size masks */ +#define BL_128K 0x000 +#define BL_256K 0x001 +#define BL_512K 0x003 +#define BL_1M 0x007 +#define BL_2M 0x00F +#define BL_4M 0x01F +#define BL_8M 0x03F +#define BL_16M 0x07F +#define BL_32M 0x0FF +#define BL_64M 0x1FF +#define BL_128M 0x3FF +#define BL_256M 0x7FF + +/* BAT Access Protection */ +#define BPP_XX 0x00 /* No access */ +#define BPP_RX 0x01 /* Read only */ +#define BPP_RW 0x02 /* Read/write */ + +/* + * Simulated two-level MMU. This structure is used by the kernel + * to keep track of MMU mappings and is used to update/maintain + * the hardware HASH table which is really a cache of mappings. + * + * The simulated structures mimic the hardware available on other + * platforms, notably the 80x86 and 680x0. + */ + +typedef struct _pte { + unsigned long page_num:20; + unsigned long flags:12; /* Page flags (some unused bits) */ +} pte; + +#define PD_SHIFT (10+12) /* Page directory */ +#define PD_MASK 0x03FF +#define PT_SHIFT (12) /* Page Table */ +#define PT_MASK 0x03FF +#define PG_SHIFT (12) /* Page Entry */ + + +/* MMU context */ + +typedef struct _MMU_context { + SEGREG segs[16]; /* Segment registers */ + pte **pmap; /* Two-level page-map structure */ +} MMU_context; + +/* Used to set up SDR1 register */ +#define HASH_TABLE_SIZE_64K 0x00010000 +#define HASH_TABLE_SIZE_128K 0x00020000 +#define HASH_TABLE_SIZE_256K 0x00040000 +#define HASH_TABLE_SIZE_512K 0x00080000 +#define HASH_TABLE_SIZE_1M 0x00100000 +#define HASH_TABLE_SIZE_2M 0x00200000 +#define HASH_TABLE_SIZE_4M 0x00400000 +#define HASH_TABLE_MASK_64K 0x000 +#define HASH_TABLE_MASK_128K 0x001 +#define HASH_TABLE_MASK_256K 0x003 +#define HASH_TABLE_MASK_512K 0x007 +#define HASH_TABLE_MASK_1M 0x00F +#define HASH_TABLE_MASK_2M 0x01F +#define HASH_TABLE_MASK_4M 0x03F + +/* invalidate a TLB entry */ +static inline void _tlbie(unsigned long va) +{ + asm volatile ("tlbie %0" : : "r"(va)); +} + +extern void _tlbia(void); /* invalidate all TLB entries */ +#endif /* ASM */ + +/* Control/status registers for the MPC8xx. + * A write operation to these registers causes serialized access. + * During software tablewalk, the registers used perform mask/shift-add + * operations when written/read. A TLB entry is created when the Mx_RPN + * is written, and the contents of several registers are used to + * create the entry. + */ +#define MI_CTR 784 /* Instruction TLB control register */ +#define MI_GPM 0x80000000 /* Set domain manager mode */ +#define MI_PPM 0x40000000 /* Set subpage protection */ +#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ +#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ +#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ +#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ +#define MI_RESETVAL 0x00000000 /* Value of register at reset */ + +/* These are the Ks and Kp from the PowerPC books. For proper operation, + * Ks = 0, Kp = 1. + */ +#define MI_AP 786 +#define MI_Ks 0x80000000 /* Should not be set */ +#define MI_Kp 0x40000000 /* Should always be set */ + +/* The effective page number register. When read, contains the information + * about the last instruction TLB miss. When MI_RPN is written, bits in + * this register are used to create the TLB entry. + */ +#define MI_EPN 787 +#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ +#define MI_EVALID 0x00000200 /* Entry is valid */ +#define MI_ASIDMASK 0x0000000f /* ASID match value */ + /* Reset value is undefined */ + +/* A "level 1" or "segment" or whatever you want to call it register. + * For the instruction TLB, it contains bits that get loaded into the + * TLB entry when the MI_RPN is written. + */ +#define MI_TWC 789 +#define MI_APG 0x000001e0 /* Access protection group (0) */ +#define MI_GUARDED 0x00000010 /* Guarded storage */ +#define MI_PSMASK 0x0000000c /* Mask of page size bits */ +#define MI_PS8MEG 0x0000000c /* 8M page size */ +#define MI_PS512K 0x00000004 /* 512K page size */ +#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ +#define MI_SVALID 0x00000001 /* Segment entry is valid */ + /* Reset value is undefined */ + +/* Real page number. Defined by the pte. Writing this register + * causes a TLB entry to be created for the instruction TLB, using + * additional information from the MI_EPN, and MI_TWC registers. + */ +#define MI_RPN 790 + +/* Define an RPN value for mapping kernel memory to large virtual + * pages for boot initialization. This has real page number of 0, + * large page size, shared page, cache enabled, and valid. + * Also mark all subpages valid and write access. + */ +#define MI_BOOTINIT 0x000001fd + +#define MD_CTR 792 /* Data TLB control register */ +#define MD_GPM 0x80000000 /* Set domain manager mode */ +#define MD_PPM 0x40000000 /* Set subpage protection */ +#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ +#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ +#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ +#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ +#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ +#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ +#define MD_RESETVAL 0x04000000 /* Value of register at reset */ + +#define M_CASID 793 /* Address space ID (context) to match */ +#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ + + +/* These are the Ks and Kp from the PowerPC books. For proper operation, + * Ks = 0, Kp = 1. + */ +#define MD_AP 794 +#define MD_Ks 0x80000000 /* Should not be set */ +#define MD_Kp 0x40000000 /* Should always be set */ + +/* The effective page number register. When read, contains the information + * about the last instruction TLB miss. When MD_RPN is written, bits in + * this register are used to create the TLB entry. + */ +#define MD_EPN 795 +#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ +#define MD_EVALID 0x00000200 /* Entry is valid */ +#define MD_ASIDMASK 0x0000000f /* ASID match value */ + /* Reset value is undefined */ + +/* The pointer to the base address of the first level page table. + * During a software tablewalk, reading this register provides the address + * of the entry associated with MD_EPN. + */ +#define M_TWB 796 +#define M_L1TB 0xfffff000 /* Level 1 table base address */ +#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ + /* Reset value is undefined */ + +/* A "level 1" or "segment" or whatever you want to call it register. + * For the data TLB, it contains bits that get loaded into the TLB entry + * when the MD_RPN is written. It is also provides the hardware assist + * for finding the PTE address during software tablewalk. + */ +#define MD_TWC 797 +#define MD_L2TB 0xfffff000 /* Level 2 table base address */ +#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ +#define MD_APG 0x000001e0 /* Access protection group (0) */ +#define MD_GUARDED 0x00000010 /* Guarded storage */ +#define MD_PSMASK 0x0000000c /* Mask of page size bits */ +#define MD_PS8MEG 0x0000000c /* 8M page size */ +#define MD_PS512K 0x00000004 /* 512K page size */ +#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ +#define MD_WT 0x00000002 /* Use writethrough page attribute */ +#define MD_SVALID 0x00000001 /* Segment entry is valid */ + /* Reset value is undefined */ + + +/* Real page number. Defined by the pte. Writing this register + * causes a TLB entry to be created for the data TLB, using + * additional information from the MD_EPN, and MD_TWC registers. + */ +#define MD_RPN 798 + +/* This is a temporary storage register that could be used to save + * a processor working register during a tablewalk. + */ +#define M_TW 799 +#endif /* _LIBCPU_MMU_H */ diff --git a/bsps/powerpc/include/libcpu/page.h b/bsps/powerpc/include/libcpu/page.h new file mode 100644 index 0000000000..3efbdef5bc --- /dev/null +++ b/bsps/powerpc/include/libcpu/page.h @@ -0,0 +1,66 @@ +/* + * page.h + * + * PowerPC memory management structures + * + * It is a stripped down version of linux ppc file... + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_PAGE_H +#define _LIBCPU_PAGE_H + +/* PAGE_SHIFT determines the page size */ +#define PAGE_SHIFT 12 +#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +#define PAGE_OFFSET 0xc0000000 + + +#ifndef ASM +/* + * .. while these make it easier on the compiler + */ +typedef unsigned long pte_t; +typedef unsigned long pmd_t; +typedef unsigned long pgd_t; +typedef unsigned long pgprot_t; + +#define pte_val(x) (x) +#define pmd_val(x) (x) +#define pgd_val(x) (x) +#define pgprot_val(x) (x) + +#define __pte(x) (x) +#define __pmd(x) (x) +#define __pgd(x) (x) +#define __pgprot(x) (x) + + +/* align addr on a size boundry - adjust address up if needed -- Cort */ +#define _ALIGN(addr,size) (((addr)+size-1)&(~(size-1))) + +/* to align the pointer to the (next) page boundary */ +#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) + + +#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) +#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) +/* map phys->virtual and virtual->phys for RAM pages */ + +#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET) +#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET)) + +#define MAP_NR(addr) (((unsigned long)addr-PAGE_OFFSET) >> PAGE_SHIFT) +#define MAP_PAGE_RESERVED (1<<15) + +extern unsigned long get_zero_page_fast(void); +#endif /* ASM */ +#endif /* _LIBCPU_PAGE_H */ diff --git a/bsps/powerpc/include/libcpu/pgtable.h b/bsps/powerpc/include/libcpu/pgtable.h new file mode 100644 index 0000000000..5be5874b4f --- /dev/null +++ b/bsps/powerpc/include/libcpu/pgtable.h @@ -0,0 +1,144 @@ +/* + * pgtable.h + * + * PowerPC memory management structures + * + * It is a stripped down version of linux ppc file... + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_PGTABLE_H +#define _LIBCPU_PGTABLE_H + +/* + * The PowerPC MMU uses a hash table containing PTEs, together with + * a set of 16 segment registers (on 32-bit implementations), to define + * the virtual to physical address mapping. + * + * We use the hash table as an extended TLB, i.e. a cache of currently + * active mappings. We maintain a two-level page table tree, much like + * that used by the i386, for the sake of the Linux memory management code. + * Low-level assembler code in head.S (procedure hash_page) is responsible + * for extracting ptes from the tree and putting them into the hash table + * when necessary, and updating the accessed and modified bits in the + * page table tree. + * + * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk. + * We also use the two level tables, but we can put the real bits in them + * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0, + * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has + * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit + * based upon user/super access. The TLB does not have accessed nor write + * protect. We assume that if the TLB get loaded with an entry it is + * accessed, and overload the changed bit for write protect. We use + * two bits in the software pte that are supposed to be set to zero in + * the TLB entry (24 and 25) for these indicators. Although the level 1 + * descriptor contains the guarded and writethrough/copyback bits, we can + * set these at the page level since they get copied from the Mx_TWC + * register when the TLB entry is loaded. We will use bit 27 for guard, since + * that is where it exists in the MD_TWC, and bit 26 for writethrough. + * These will get masked from the level 2 descriptor at TLB load time, and + * copied to the MD_TWC before it gets loaded. + */ + +/* PMD_SHIFT determines the size of the area mapped by the second-level page tables */ +#define PMD_SHIFT 22 +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE-1)) + +/* PGDIR_SHIFT determines what a third-level page table entry can map */ +#define PGDIR_SHIFT 22 +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +/* + * entries per page directory level: our page-table tree is two-level, so + * we don't really have any PMD directory. + */ +#define PTRS_PER_PTE 1024 +#define PTRS_PER_PMD 1 +#define PTRS_PER_PGD 1024 +#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) + +/* Just any arbitrary offset to the start of the vmalloc VM area: the + * current 64MB value just means that there will be a 64MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + * + * We no longer map larger than phys RAM with the BATs so we don't have + * to worry about the VMALLOC_OFFSET causing problems. We do have to worry + * about clashes between our early calls to ioremap() that start growing down + * from ioremap_base being run into the VM area allocations (growing upwards + * from VMALLOC_START). For this reason we have ioremap_bot to check when + * we actually run into our mappings setup in the early boot with the VM + * system. This really does become a problem for machines with good amounts + * of RAM. -- Cort + */ +#define VMALLOC_OFFSET (0x4000000) /* 64M */ +#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END ioremap_bot + +/* + * Bits in a linux-style PTE. These match the bits in the + * (hardware-defined) PowerPC PTE as closely as possible. + */ +#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ +#define _PAGE_USER 0x002 /* matches one of the PP bits */ +#define _PAGE_RW 0x004 /* software: user write access allowed */ +#define _PAGE_GUARDED 0x008 +#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ +#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ +#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ +#define _PAGE_DIRTY 0x080 /* C: page changed */ +#define _PAGE_ACCESSED 0x100 /* R: page referenced */ +#define _PAGE_HWWRITE 0x200 /* software: _PAGE_RW & _PAGE_DIRTY */ +#define _PAGE_SHARED 0 + +#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) + +#define _PAGE_BASE _PAGE_PRESENT | _PAGE_ACCESSED +#define _PAGE_WRENABLE _PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE + +#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) + +#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | \ + _PAGE_SHARED) +#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) +#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) +#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED) +#define PAGE_KERNEL_CI __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | \ + _PAGE_NO_CACHE ) + +/* + * The PowerPC can only do execute protection on a segment (256MB) basis, + * not on a page basis. So we consider execute permission the same as read. + * Also, write permissions imply read permissions. + * This is the closest we can get.. + */ +#define __P000 PAGE_NONE +#define __P001 PAGE_READONLY +#define __P010 PAGE_COPY +#define __P011 PAGE_COPY +#define __P100 PAGE_READONLY +#define __P101 PAGE_READONLY +#define __P110 PAGE_COPY +#define __P111 PAGE_COPY + +#define __S000 PAGE_NONE +#define __S001 PAGE_READONLY +#define __S010 PAGE_SHARED +#define __S011 PAGE_SHARED +#define __S100 PAGE_READONLY +#define __S101 PAGE_READONLY +#define __S110 PAGE_SHARED +#define __S111 PAGE_SHARED +#endif /* _LIBCPU_PGTABLE_H */ diff --git a/bsps/powerpc/include/libcpu/powerpc-utility.h b/bsps/powerpc/include/libcpu/powerpc-utility.h new file mode 100644 index 0000000000..4d6af38485 --- /dev/null +++ b/bsps/powerpc/include/libcpu/powerpc-utility.h @@ -0,0 +1,985 @@ +/** + * @file + * + * @ingroup powerpc_shared + * + * @brief General purpose assembler macros, linker command file support and + * some inline functions for direct register access. + */ + +/* + * Copyright (c) 2008-2015 embedded brains GmbH. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * access function for Device Control Registers inspired by "ppc405common.h" + * from Michael Hamel ADInstruments May 2008 + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup powerpc_shared Shared PowerPC Code + */ + +#ifndef __LIBCPU_POWERPC_UTILITY_H +#define __LIBCPU_POWERPC_UTILITY_H + +#if !defined(ASM) + #include +#endif + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(ASM) + +#include +#include + +#include + +#define LINKER_SYMBOL(sym) extern char sym []; + +/** + * @brief Read one byte from @a src. + */ +static inline uint8_t ppc_read_byte(const volatile void *src) +{ + uint8_t value; + + __asm__ volatile ( + "lbz %0, 0(%1)" + : "=r" (value) + : "b" (src) + ); + + return value; +} + +/** + * @brief Read one half word from @a src. + */ +static inline uint16_t ppc_read_half_word(const volatile void *src) +{ + uint16_t value; + + __asm__ volatile ( + "lhz %0, 0(%1)" + : "=r" (value) + : "b" (src) + ); + + return value; +} + +/** + * @brief Read one word from @a src. + */ +static inline uint32_t ppc_read_word(const volatile void *src) +{ + uint32_t value; + + __asm__ volatile ( + "lwz %0, 0(%1)" + : "=r" (value) + : "b" (src) + ); + + return value; +} + +/** + * @brief Write one byte @a value to @a dest. + */ +static inline void ppc_write_byte(uint8_t value, volatile void *dest) +{ + __asm__ volatile ( + "stb %0, 0(%1)" + : + : "r" (value), "b" (dest) + ); +} + +/** + * @brief Write one half word @a value to @a dest. + */ +static inline void ppc_write_half_word(uint16_t value, volatile void *dest) +{ + __asm__ volatile ( + "sth %0, 0(%1)" + : + : "r" (value), "b" (dest) + ); +} + +/** + * @brief Write one word @a value to @a dest. + */ +static inline void ppc_write_word(uint32_t value, volatile void *dest) +{ + __asm__ volatile ( + "stw %0, 0(%1)" : + : "r" (value), "b" (dest) + ); +} + + +static inline void *ppc_stack_pointer(void) +{ + void *sp; + + __asm__ volatile ( + "mr %0, 1" + : "=r" (sp) + ); + + return sp; +} + +static inline void ppc_set_stack_pointer(void *sp) +{ + __asm__ volatile ( + "mr 1, %0" + : + : "r" (sp) + ); +} + +static inline void *ppc_link_register(void) +{ + void *lr; + + __asm__ volatile ( + "mflr %0" + : "=r" (lr) + ); + + return lr; +} + +static inline void ppc_set_link_register(void *lr) +{ + __asm__ volatile ( + "mtlr %0" + : + : "r" (lr) + ); +} + +static inline uint32_t ppc_machine_state_register(void) +{ + uint32_t msr; + + __asm__ volatile ( + "mfmsr %0" + : "=r" (msr) + ); + + return msr; +} + +static inline void ppc_set_machine_state_register(uint32_t msr) +{ + __asm__ volatile ( + "mtmsr %0" + : + : "r" (msr) + ); +} + +static inline void ppc_synchronize_data(void) +{ + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ("sync"); +} + +static inline void ppc_light_weight_synchronize(void) +{ + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ("lwsync"); +} + +static inline void ppc_synchronize_instructions(void) +{ + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ("isync"); +} + +static inline void ppc_enforce_in_order_execution_of_io(void) +{ + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ("eieio"); +} + +static inline void ppc_data_cache_block_flush(void *addr) +{ + __asm__ volatile ( + "dcbf 0, %0" + : + : "r" (addr) + : "memory" + ); +} + +static inline void ppc_data_cache_block_flush_2( + void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "dcbf %0, %1" + : + : "b" (base), "r" (offset) + : "memory" + ); +} + +static inline void ppc_data_cache_block_invalidate(void *addr) +{ + __asm__ volatile ( + "dcbi 0, %0" + : + : "r" (addr) + : "memory" + ); +} + +static inline void ppc_data_cache_block_invalidate_2( + void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "dcbi %0, %1" + : + : "b" (base), "r" (offset) + : "memory" + ); +} + +static inline void ppc_data_cache_block_store(const void *addr) +{ + __asm__ volatile ( + "dcbst 0, %0" + : + : "r" (addr) + ); +} + +static inline void ppc_data_cache_block_store_2( + const void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "dcbst %0, %1" + : + : "b" (base), "r" (offset) + ); +} + +static inline void ppc_data_cache_block_touch(const void *addr) +{ + __asm__ volatile ( + "dcbt 0, %0" + : + : "r" (addr) + ); +} + +static inline void ppc_data_cache_block_touch_2( + const void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "dcbt %0, %1" + : + : "b" (base), "r" (offset) + ); +} + +static inline void ppc_data_cache_block_touch_for_store(const void *addr) +{ + __asm__ volatile ( + "dcbtst 0, %0" + : + : "r" (addr) + ); +} + +static inline void ppc_data_cache_block_touch_for_store_2( + const void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "dcbtst %0, %1" + : + : "b" (base), "r" (offset) + ); +} + +static inline void ppc_data_cache_block_clear_to_zero(void *addr) +{ + __asm__ volatile ( + "dcbz 0, %0" + : + : "r" (addr) + : "memory" + ); +} + +static inline void ppc_data_cache_block_clear_to_zero_2( + void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "dcbz %0, %1" + : + : "b" (base), "r" (offset) + : "memory" + ); +} + +static inline void ppc_instruction_cache_block_invalidate(void *addr) +{ + __asm__ volatile ( + "icbi 0, %0" + : + : "r" (addr) + ); +} + +static inline void ppc_instruction_cache_block_invalidate_2( + void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "icbi %0, %1" + : + : "b" (base), "r" (offset) + ); +} + +/** + * @brief Enables external exceptions. + * + * You can use this function to enable the external exceptions and restore the + * machine state with ppc_external_exceptions_disable() later. + */ +static inline uint32_t ppc_external_exceptions_enable(void) +{ + uint32_t current_msr; + uint32_t new_msr; + + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ( + "mfmsr %0;" + "ori %1, %0, 0x8000;" + "mtmsr %1" + : "=r" (current_msr), "=r" (new_msr) + ); + + return current_msr; +} + +/** + * @brief Restores machine state. + * + * @see ppc_external_exceptions_enable() + */ +static inline void ppc_external_exceptions_disable(uint32_t msr) +{ + ppc_set_machine_state_register(msr); + + RTEMS_COMPILER_MEMORY_BARRIER(); +} + +static inline uint32_t ppc_count_leading_zeros(uint32_t value) +{ + uint32_t count; + + __asm__ ( + "cntlzw %0, %1;" + : "=r" (count) + : "r" (value) + ); + + return count; +} + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#if defined(mpx8xx) || defined(mpc860) || defined(mpc821) +/* Wonderful bookE doesn't have mftb/mftbu; they only + * define the TBRU/TBRL SPRs so we use these. Luckily, + * we run in supervisory mode so that should work on + * all CPUs. In user mode we'd have a problem... + * 2007/11/30, T.S. + * + * OTOH, PSIM currently lacks support for reading + * SPRs 268/269. You need GDB patch sim/2376 to avoid + * a crash... + * OTOH, the MPC8xx do not allow to read the timebase registers via mfspr. + * we NEED a mftb to access the time base. + * 2009/10/30 Th. D. + */ +#define CPU_Get_timebase_low( _value ) \ + __asm__ volatile( "mftb %0" : "=r" (_value) ) +#else +#define CPU_Get_timebase_low( _value ) \ + __asm__ volatile( "mfspr %0,268" : "=r" (_value) ) +#endif + +/* Must be provided for rtems_bsp_delay to work */ +extern uint32_t bsp_clicks_per_usec; + +#define rtems_bsp_delay( _microseconds ) \ + do { \ + uint32_t start, ticks, now; \ + CPU_Get_timebase_low( start ) ; \ + ticks = (_microseconds) * bsp_clicks_per_usec; \ + do \ + CPU_Get_timebase_low( now ) ; \ + while (now - start < ticks); \ + } while (0) + +#define rtems_bsp_delay_in_bus_cycles( _cycles ) \ + do { \ + uint32_t start, now; \ + CPU_Get_timebase_low( start ); \ + do \ + CPU_Get_timebase_low( now ); \ + while (now - start < (_cycles)); \ + } while (0) + +/* + * Routines to access the decrementer register + */ + +#define PPC_Set_decrementer( _clicks ) \ + do { \ + __asm__ volatile( "mtdec %0" : : "r" ((_clicks)) ); \ + } while (0) + +#define PPC_Get_decrementer( _clicks ) \ + __asm__ volatile( "mfdec %0" : "=r" (_clicks) ) + +/* + * Routines to access the time base register + */ + +static inline uint64_t PPC_Get_timebase_register( void ) +{ + uint32_t tbr_low; + uint32_t tbr_high; + uint32_t tbr_high_old; + uint64_t tbr; + + do { +#if defined(mpx8xx) || defined(mpc860) || defined(mpc821) +/* See comment above (CPU_Get_timebase_low) */ + __asm__ volatile( "mftbu %0" : "=r" (tbr_high_old)); + __asm__ volatile( "mftb %0" : "=r" (tbr_low)); + __asm__ volatile( "mftbu %0" : "=r" (tbr_high)); +#else + __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high_old)); + __asm__ volatile( "mfspr %0, 268" : "=r" (tbr_low)); + __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high)); +#endif + } while ( tbr_high_old != tbr_high ); + + tbr = tbr_high; + tbr <<= 32; + tbr |= tbr_low; + return tbr; +} + +static inline void PPC_Set_timebase_register (uint64_t tbr) +{ + uint32_t tbr_low; + uint32_t tbr_high; + + tbr_low = (uint32_t) tbr; + tbr_high = (uint32_t) (tbr >> 32); + __asm__ volatile( "mtspr 284, %0" : : "r" (tbr_low)); + __asm__ volatile( "mtspr 285, %0" : : "r" (tbr_high)); + +} + +static inline uint32_t ppc_decrementer_register(void) +{ + uint32_t dec; + + PPC_Get_decrementer(dec); + + return dec; +} + +static inline void ppc_set_decrementer_register(uint32_t dec) +{ + PPC_Set_decrementer(dec); +} + +/** + * @brief Preprocessor magic for stringification of @a x. + */ +#define PPC_STRINGOF(x) #x + +/** + * @brief Returns the value of the Special Purpose Register with number @a spr. + * + * @note This macro uses a GNU C extension. + */ +#define PPC_SPECIAL_PURPOSE_REGISTER(spr) \ + ({ \ + uint32_t val; \ + __asm__ volatile (\ + "mfspr %0, " PPC_STRINGOF(spr) \ + : "=r" (val) \ + ); \ + val;\ + } ) + +/** + * @brief Sets the Special Purpose Register with number @a spr to the value in + * @a val. + */ +#define PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val) \ + do { \ + __asm__ volatile (\ + "mtspr " PPC_STRINGOF(spr) ", %0" \ + : \ + : "r" (val) \ + ); \ + } while (0) + +/** + * @brief Sets in the Special Purpose Register with number @a spr all bits + * which are set in @a bits. + * + * Interrupts are disabled throughout this operation. + */ +#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \ + do { \ + ISR_Level level; \ + uint32_t val; \ + uint32_t mybits = bits; \ + _ISR_Local_disable(level); \ + val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ + val |= mybits; \ + PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ + _ISR_Local_enable(level); \ + } while (0) + +/** + * @brief Sets in the Special Purpose Register with number @a spr all bits + * which are set in @a bits. The previous register value will be masked with + * @a mask. + * + * Interrupts are disabled throughout this operation. + */ +#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED(spr, bits, mask) \ + do { \ + ISR_Level level; \ + uint32_t val; \ + uint32_t mybits = bits; \ + uint32_t mymask = mask; \ + _ISR_Local_disable(level); \ + val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ + val &= ~mymask; \ + val |= mybits; \ + PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ + _ISR_Local_enable(level); \ + } while (0) + +/** + * @brief Clears in the Special Purpose Register with number @a spr all bits + * which are set in @a bits. + * + * Interrupts are disabled throughout this operation. + */ +#define PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \ + do { \ + ISR_Level level; \ + uint32_t val; \ + uint32_t mybits = bits; \ + _ISR_Local_disable(level); \ + val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ + val &= ~mybits; \ + PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ + _ISR_Local_enable(level); \ + } while (0) + +/** + * @brief Returns the value of the Thread Management Register with number @a tmr. + * + * @note This macro uses a GNU C extension. + */ +#define PPC_THREAD_MGMT_REGISTER(tmr) \ + ({ \ + uint32_t val; \ + __asm__ volatile (\ + "mftmr %0, " PPC_STRINGOF(tmr) \ + : "=r" (val) \ + ); \ + val;\ + } ) + +/** + * @brief Sets the Thread Management Register with number @a tmr to the value in + * @a val. + */ +#define PPC_SET_THREAD_MGMT_REGISTER(tmr, val) \ + do { \ + __asm__ volatile (\ + "mttmr " PPC_STRINGOF(tmr) ", %0" \ + : \ + : "r" (val) \ + ); \ + } while (0) + +/** + * @brief Returns the value of the Device Control Register with number @a dcr. + * + * The PowerPC 4XX family has Device Control Registers. + * + * @note This macro uses a GNU C extension. + */ +#define PPC_DEVICE_CONTROL_REGISTER(dcr) \ + ({ \ + uint32_t val; \ + __asm__ volatile (\ + "mfdcr %0, " PPC_STRINGOF(dcr) \ + : "=r" (val) \ + ); \ + val;\ + } ) + +/** + * @brief Sets the Device Control Register with number @a dcr to the value in + * @a val. + * + * The PowerPC 4XX family has Device Control Registers. + */ +#define PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val) \ + do { \ + __asm__ volatile (\ + "mtdcr " PPC_STRINGOF(dcr) ", %0" \ + : \ + : "r" (val) \ + ); \ + } while (0) + +/** + * @brief Sets in the Device Control Register with number @a dcr all bits + * which are set in @a bits. + * + * Interrupts are disabled throughout this operation. + */ +#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \ + do { \ + ISR_Level level; \ + uint32_t val; \ + uint32_t mybits = bits; \ + _ISR_Local_disable(level); \ + val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ + val |= mybits; \ + PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ + _ISR_Local_enable(level); \ + } while (0) + +/** + * @brief Sets in the Device Control Register with number @a dcr all bits + * which are set in @a bits. The previous register value will be masked with + * @a mask. + * + * Interrupts are disabled throughout this operation. + */ +#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS_MASKED(dcr, bits, mask) \ + do { \ + ISR_Level level; \ + uint32_t val; \ + uint32_t mybits = bits; \ + uint32_t mymask = mask; \ + _ISR_Local_disable(level); \ + val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ + val &= ~mymask; \ + val |= mybits; \ + PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ + _ISR_Local_enable(level); \ + } while (0) + +/** + * @brief Clears in the Device Control Register with number @a dcr all bits + * which are set in @a bits. + * + * Interrupts are disabled throughout this operation. + */ +#define PPC_CLEAR_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \ + do { \ + ISR_Level level; \ + uint32_t val; \ + uint32_t mybits = bits; \ + _ISR_Local_disable(level); \ + val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ + val &= ~mybits; \ + PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ + _ISR_Local_enable(level); \ + } while (0) + +static inline uint32_t ppc_time_base(void) +{ + uint32_t val; + + CPU_Get_timebase_low(val); + + return val; +} + +static inline void ppc_set_time_base(uint32_t val) +{ + PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWL, val); +} + +static inline uint32_t ppc_time_base_upper(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(TBRU); +} + +static inline void ppc_set_time_base_upper(uint32_t val) +{ + PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWU, val); +} + +static inline uint64_t ppc_time_base_64(void) +{ + return PPC_Get_timebase_register(); +} + +static inline void ppc_set_time_base_64(uint64_t val) +{ + PPC_Set_timebase_register(val); +} + +static inline uint32_t ppc_alternate_time_base(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBL); +} + +static inline uint32_t ppc_alternate_time_base_upper(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBU); +} + +static inline uint64_t ppc_alternate_time_base_64(void) +{ + uint32_t atbl; + uint32_t atbu_0; + uint32_t atbu_1; + + do { + atbu_0 = ppc_alternate_time_base_upper(); + atbl = ppc_alternate_time_base(); + atbu_1 = ppc_alternate_time_base_upper(); + } while (atbu_0 != atbu_1); + + return (((uint64_t) atbu_1) << 32) | ((uint64_t) atbl); +} + +static inline uint32_t ppc_processor_id(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR); +} + +static inline void ppc_set_processor_id(uint32_t val) +{ + PPC_SET_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR, val); +} + +static inline uint32_t ppc_fsl_system_version(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_SVR); +} + +static inline uint32_t ppc_fsl_system_version_cid(uint32_t svr) +{ + return (svr >> 28) & 0xf; +} + +static inline uint32_t ppc_fsl_system_version_sid(uint32_t svr) +{ + return (svr >> 16) & 0xfff; +} + +static inline uint32_t ppc_fsl_system_version_proc(uint32_t svr) +{ + return (svr >> 12) & 0xf; +} + +static inline uint32_t ppc_fsl_system_version_mfg(uint32_t svr) +{ + return (svr >> 8) & 0xf; +} + +static inline uint32_t ppc_fsl_system_version_mjrev(uint32_t svr) +{ + return (svr >> 4) & 0xf; +} + +static inline uint32_t ppc_fsl_system_version_mnrev(uint32_t svr) +{ + return (svr >> 0) & 0xf; +} + +void ppc_code_copy(void *dest, const void *src, size_t n); + +/* FIXME: Do not use this function */ +void printBAT(int bat, uint32_t upper, uint32_t lower); + +/* FIXME: Do not use this function */ +void ShowBATS(void); + +#endif /* ifndef ASM */ + +#if defined(ASM) +#include + +.macro LA reg, addr +#if defined(__powerpc64__) + lis \reg, (\addr)@highest + ori \reg, \reg, (\addr)@higher + rldicr \reg, \reg, 32, 31 + oris \reg, \reg, (\addr)@h + ori \reg, \reg, (\addr)@l +#else + lis \reg, (\addr)@h + ori \reg, \reg, (\addr)@l +#endif +.endm + +.macro LA32 reg, addr + lis \reg, (\addr)@h + ori \reg, \reg, (\addr)@l +.endm + +.macro LWI reg, value + lis \reg, (\value)@h + ori \reg, \reg, (\value)@l +.endm + +.macro LW reg, addr + lis \reg, \addr@ha + lwz \reg, \addr@l(\reg) +.endm + +/* + * Tests the bits in reg1 against the bits set in mask. A match is indicated + * by EQ = 0 in CR0. A mismatch is indicated by EQ = 1 in CR0. The register + * reg2 is used to load the mask. + */ +.macro TSTBITS reg1, reg2, mask + LWI \reg2, \mask + and \reg1, \reg1, \reg2 + cmplw \reg1, \reg2 +.endm + +.macro SETBITS reg1, reg2, mask + LWI \reg2, \mask + or \reg1, \reg1, \reg2 +.endm + +.macro CLRBITS reg1, reg2, mask + LWI \reg2, \mask + andc \reg1, \reg1, \reg2 +.endm + +.macro GLOBAL_FUNCTION name + .global \name + .type \name, @function +\name: +.endm + +/* + * Obtain interrupt mask + */ +.macro GET_INTERRUPT_MASK mask + lis \mask, _PPC_INTERRUPT_DISABLE_MASK@h + ori \mask, \mask, _PPC_INTERRUPT_DISABLE_MASK@l +.endm + +/* + * Disables all asynchronous exeptions (interrupts) which may cause a context + * switch. + */ +.macro INTERRUPT_DISABLE level, mask + mfmsr \level + GET_INTERRUPT_MASK mask=\mask + andc \mask, \level, \mask + mtmsr \mask +.endm + +/* + * Restore previous machine state. + */ +.macro INTERRUPT_ENABLE level + mtmsr \level +.endm + +.macro SET_SELF_CPU_CONTROL reg_0, reg_1 +#if defined(RTEMS_SMP) + /* Use Book E Processor ID Register (PIR) */ + mfspr \reg_0, 286 + slwi \reg_0, \reg_0, PER_CPU_CONTROL_SIZE_LOG2 +#if defined(__powerpc64__) + LA \reg_1, _Per_CPU_Information + add \reg_0, \reg_0, \reg_1 +#else + addis \reg_0, \reg_0, _Per_CPU_Information@ha + addi \reg_0, \reg_0, _Per_CPU_Information@l +#endif + mtspr PPC_PER_CPU_CONTROL_REGISTER, \reg_0 +#endif +.endm + +.macro GET_SELF_CPU_CONTROL reg +#if defined(RTEMS_SMP) + mfspr \reg, PPC_PER_CPU_CONTROL_REGISTER +#else + lis \reg, _Per_CPU_Information@h + ori \reg, \reg, _Per_CPU_Information@l +#endif +.endm + +#define LINKER_SYMBOL(sym) .extern sym + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LIBCPU_POWERPC_UTILITY_H */ diff --git a/bsps/powerpc/include/libcpu/pte121.h b/bsps/powerpc/include/libcpu/pte121.h new file mode 100644 index 0000000000..a07e063f03 --- /dev/null +++ b/bsps/powerpc/include/libcpu/pte121.h @@ -0,0 +1,265 @@ +#ifndef _LIBCPU_PTE121_H +#define _LIBCPU_PTE121_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 4/2002, 2003, 2004, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +/* Rudimentary page/hash table support for Powerpc + * + * A simple, static (i.e. no 'per-process' virtual + * address space etc.) page table providing + * one-to-one effective <-> virtual <-> physical + * address mapping. + * + * PURPOSE: + * 1) allow write-protection of text/read-only data areas + * 2) provide more effective-address space in case + * the BATs are not enough + * 3) allow 'alias' mappings. Such aliases can only use + * the upper bits of the VSID since VSID & 0xf and the + * PI are always mapped 1:1 to the RPN. + * LIMITATIONS: + * - no PTE replacement (makes no sense in a real-time + * environment, anyway) -> the page table just MUST + * be big enough!. + * - only one page table supported. + * - no locking implemented. If multiple threads modify + * the page table, it is the user's responsibility to + * implement exclusive access. + */ + + +/* I don't include mmu.h here because it says it's derived from linux + * and I want to avoid licensing problems + */ + +/* Abstract handle for a page table */ +typedef struct Triv121PgTblRec_ *Triv121PgTbl; + +/* A PTE entry */ +typedef struct PTERec_ { + volatile unsigned long v:1, vsid:24, h:1, api: 6; + volatile unsigned long rpn:20, pad: 3, r:1, c:1, wimg:4, marked:1, pp:2; +} PTERec, *APte; + +/* Initialize a trivial page table + * using 2^ldSize bytes of memory starting at + * 'base'. + * + * RETURNS: a handle to the internal data structure + * used to manage the page table. NULL on + * error. + * + * NOTES: - 'base' must be aligned to the size + * - minimal ldSize is 16 (== 64k) + * - this routine maps the page table itself + * with read-only access. While this prevents + * the CPU from overwriting the page table, + * it can still be corrupted by PCI bus masters + * (like DMA engines, [VME] bridges etc.) and + * even by this CPU if either the MMU is off + * or if there is a DBAT mapping granting write + * access... + */ +Triv121PgTbl +triv121PgTblInit(unsigned long base, unsigned ldSize); + +/* get the log2 of the minimal page table size needed + * for mapping 'size' bytes. + * + * EXAMPLE: create a page table which maps the entire + * physical memory. The page table itself shall + * be allocated at the top of the available + * memory (assuming 'memsize' is a power of two): + * + * ldSize = triv121PgTblLdMinSize(memsize); + * memsize -= (1<virtual address mapping */ +#define TRIV121_SEG_VSID (-2) /* lookup VSID in the segment register */ + +#define TRIV121_MAP_SUCCESS (-1) /* triv121PgTblMap() returns this on SUCCESS */ + +/* get a handle to the one and only page table + * (must have been initialized/allocated) + * + * RETURNS: NULL if the page table has not been initialized/allocated. + */ +Triv121PgTbl +triv121PgTblGet(void); + +/* + * compute the SDR1 register value for the page table + */ + +unsigned long +triv121PgTblSDR1(Triv121PgTbl pgTbl); + +/* + * Activate the page table: + * - set up the segment registers for a 1:1 effective <-> virtual address mapping, + * give user and supervisor keys. + * - set up the SDR1 register + * - flush all tlbs + * - 'lock' pgTbl, i.e. prevent all further modifications. + * + * NOTE: This routine does not change any BATs. Since these + * have priority over the page table, the user + * may have to switch overlapping BATs OFF in order + * for the page table mappings to take effect. + */ +void triv121PgTblActivate(Triv121PgTbl pgTbl); + +/* Find the PTE for a EA and print its contents to stdout + * RETURNS: pte for EA or NULL if no entry was found. + */ +APte triv121DumpEa(unsigned long ea); + +/* Find and return a PTE for a vsid/pi combination + * RETURNS: pte or NULL if no entry was found + */ +APte triv121FindPte(unsigned long vsid, unsigned long pi); + +/* + * Unmap an effective address + * + * RETURNS: pte that mapped the ea or NULL if no + * mapping existed. + */ +APte triv121UnmapEa(unsigned long ea); + +/* + * Change the WIMG and PP attributes of the page containing 'ea' + * + * NOTES: The 'wimg' and 'pp' may be <0 to indicate that no + * change is desired. + * + * RETURNS: Pointer to modified PTE or NULL if 'ea' is not mapped. + */ +APte triv121ChangeEaAttributes(unsigned long ea, int wimg, int pp); + +/* Make the whole page table writable + * NOTES: If the page table has not been initialized yet, + * this routine has no effect (i.e., after + * initialization the page table will still be read-only). + */ +void triv121MakePgTblRW(void); + +/* Make the whole page table read-only + */ +void triv121MakePgTblRO(void); + +/* Dump a pte to stdout */ +long triv121DumpPte(APte pte); + +#endif diff --git a/bsps/powerpc/include/libcpu/raw_exception.h b/bsps/powerpc/include/libcpu/raw_exception.h new file mode 100644 index 0000000000..dd0c483b0d --- /dev/null +++ b/bsps/powerpc/include/libcpu/raw_exception.h @@ -0,0 +1,161 @@ +/* + * raw_execption.h + * + * This file contains implementation of C function to + * Instantiate mpc5xx primary exception entries. + * More detailled information can be found on the Motorola + * site and more precisely in the following book: + * + * MPC555/MPC556 User's Manual + * Motorola REF : MPC555UM/D Rev. 3, 2000 October 15 + * + * + * MPC5xx port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from libcpu/powerpc/mpc8xx/exceptions/raw_exception.h: + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_RAW_EXCEPTION_H +#define _LIBCPU_RAW_EXCEPTION_H + +#include + +/* + * Exception Vectors as defined in the MPC555 User's Manual + */ + +#define ASM_RESET_VECTOR 0x01 +#define ASM_MACH_VECTOR 0x02 + +#define ASM_EXT_VECTOR 0x05 +#define ASM_ALIGN_VECTOR 0x06 +#define ASM_PROG_VECTOR 0x07 +#define ASM_FLOAT_VECTOR 0x08 +#define ASM_DEC_VECTOR 0x09 + +#define ASM_SYS_VECTOR 0x0C +#define ASM_TRACE_VECTOR 0x0D +#define ASM_FLOATASSIST_VECTOR 0x0E + +#define ASM_SOFTEMUL_VECTOR 0x10 + +#define ASM_IPROT_VECTOR 0x13 +#define ASM_DPROT_VECTOR 0x14 + +#define ASM_DBREAK_VECTOR 0x1C +#define ASM_IBREAK_VECTOR 0x1D +#define ASM_MEBREAK_VECTOR 0x1E +#define ASM_NMEBREAK_VECTOR 0x1F + +#define LAST_VALID_EXC ASM_NMEBREAK_VECTOR + +#ifndef ASM + +/* + * Type definition for raw exceptions. + */ + +typedef unsigned char rtems_vector; +struct __rtems_raw_except_connect_data__; +typedef unsigned char rtems_raw_except_hdl_size; + +typedef struct { + rtems_vector vector; + rtems_exception_handler_t* raw_hdl; +}rtems_raw_except_hdl; + +typedef void (*rtems_raw_except_enable) (const struct __rtems_raw_except_connect_data__*); +typedef void (*rtems_raw_except_disable) (const struct __rtems_raw_except_connect_data__*); +typedef int (*rtems_raw_except_is_enabled) (const struct __rtems_raw_except_connect_data__*); + +typedef struct __rtems_raw_except_connect_data__{ + /* + * Exception vector (As defined in the manual) + */ + rtems_vector exceptIndex; + /* + * Exception raw handler. See comment on handler properties below in function prototype. + */ + rtems_raw_except_hdl hdl; + /* + * function for enabling raw exceptions. In order to be consistent + * with the fact that the raw connexion can defined in the + * libcpu library, this library should have no knowledge of + * board specific hardware to manage exceptions and thus the + * "on" routine must enable the except at processor level only. + * + */ + rtems_raw_except_enable on; + /* + * function for disabling raw exceptions. In order to be consistent + * with the fact that the raw connexion can defined in the + * libcpu library, this library should have no knowledge of + * board specific hardware to manage exceptions and thus the + * "on" routine must disable the except both at device and PIC level. + * + */ + rtems_raw_except_disable off; + /* + * function enabling to know what exception may currently occur + */ + rtems_raw_except_is_enabled isOn; +}rtems_raw_except_connect_data; + +typedef struct { + /* + * size of all the table fields (*Tbl) described below. + */ + unsigned int exceptSize; + /* + * Default handler used when disconnecting exceptions. + */ + rtems_raw_except_connect_data defaultRawEntry; + /* + * Table containing initials/current value. + */ + rtems_raw_except_connect_data* rawExceptHdlTbl; +}rtems_raw_except_global_settings; + +/* + * C callable function enabling to set up one raw idt entry + */ +extern int mpc5xx_set_exception (const rtems_raw_except_connect_data*); + +/* + * C callable function enabling to get one current raw idt entry + */ +extern int mpc5xx_get_current_exception (rtems_raw_except_connect_data*); + +/* + * C callable function enabling to remove one current raw idt entry + */ +extern int mpc5xx_delete_exception (const rtems_raw_except_connect_data*); + +/* + * C callable function enabling to check if vector is valid + */ +extern int mpc5xx_vector_is_valid(rtems_vector vector); + +inline static void* mpc5xx_get_vector_addr(rtems_vector vector) +{ + return ((void*) (((unsigned) vector) << 8)); +} +/* + * Exception global init. + */ +extern int mpc5xx_init_exceptions (rtems_raw_except_global_settings* config); +extern int mpc5xx_get_exception_config (rtems_raw_except_global_settings** config); + +# endif /* ASM */ + +#define SIZEOF_ + +#endif diff --git a/bsps/powerpc/include/libcpu/spr.h b/bsps/powerpc/include/libcpu/spr.h new file mode 100644 index 0000000000..6c81d0ee91 --- /dev/null +++ b/bsps/powerpc/include/libcpu/spr.h @@ -0,0 +1,78 @@ +/* + * spr.h -- Access to special purpose registers. + * + * Copyright (C) 1998 Gabriel Paubert, paubert@iram.es + * + * Modified to compile in RTEMS development environment + * by Eric Valette + * + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + + +#ifndef _LIBCPU_SPR_H +#define _LIBCPU_SPR_H + +#include + +#define __MFSPR(reg, val) \ + __asm__ __volatile__("mfspr %0,"#reg : "=r" (val)) + +#define __MTSPR(val, reg) \ + __asm__ __volatile__("mtspr "#reg",%0" : : "r" (val)) + + +#define SPR_RW(reg) \ +static inline unsigned long _read_##reg(void) \ +{\ + unsigned long val;\ + __MFSPR(reg, val);\ + return val;\ +}\ +static inline void _write_##reg(unsigned long val)\ +{\ + __MTSPR(val,reg);\ + return;\ +} + +#define SPR_RO(reg) \ +static inline unsigned long _read_##reg(void) \ +{\ + unsigned long val;\ + __MFSPR(reg,val);\ + return val;\ +} + +static inline unsigned long _read_MSR(void) +{ + unsigned long val; + asm volatile("mfmsr %0" : "=r" (val)); + return val; +} + +static inline void _write_MSR(unsigned long val) +{ + asm volatile("mtmsr %0" : : "r" (val)); + return; +} + +static inline unsigned long _read_SR(void * va) +{ + unsigned long val; + asm volatile("mfsrin %0,%1" : "=r" (val): "r" (va)); + return val; +} + +static inline void _write_SR(unsigned long val, void * va) +{ + asm volatile("mtsrin %0,%1" : : "r"(val), "r" (va): "memory"); + return; +} + + +#endif diff --git a/bsps/powerpc/include/libcpu/stackTrace.h b/bsps/powerpc/include/libcpu/stackTrace.h new file mode 100644 index 0000000000..f73dc2eff2 --- /dev/null +++ b/bsps/powerpc/include/libcpu/stackTrace.h @@ -0,0 +1,8 @@ +#ifndef _LIBCPU_STACKTRACE_H +#define _LIBCPU_STACKTRACE_H + +void CPU_stack_take_snapshot(void **stack, int size, void *pc, void *lr, void *r1); + +void CPU_print_stack(void); + +#endif diff --git a/bsps/powerpc/include/libcpu/vectors.h b/bsps/powerpc/include/libcpu/vectors.h new file mode 100644 index 0000000000..2c8914e2a4 --- /dev/null +++ b/bsps/powerpc/include/libcpu/vectors.h @@ -0,0 +1,115 @@ +/* + * vectors.h Exception frame related contant and API. + * + * This include file describe the data structure and the functions implemented + * by rtems to handle exceptions. + * + * + * MPC5xx port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from libbsp/powerpc/mbx8xx/vectors/vectors.h: + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef _LIBCPU_VECTORS_H +#define _LIBCPU_VECTORS_H + + +/* + * Size of hardware vector table. + */ +#define NUM_EXCEPTIONS 0x20 + +/* + * The callee (high level exception code written in C) + * will store the Link Registers (return address) at entry r1 + 4 !!!. + * So let room for it!!!. + */ +#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 +#define SRR0_FRAME_OFFSET 8 +#define SRR1_FRAME_OFFSET 12 +#define EXCEPTION_NUMBER_OFFSET 16 +#define EXC_CR_OFFSET 20 +#define EXC_CTR_OFFSET 24 +#define EXC_XER_OFFSET 28 +#define EXC_LR_OFFSET 32 +#define GPR0_OFFSET 36 +#define GPR1_OFFSET 40 +#define GPR2_OFFSET 44 +#define GPR3_OFFSET 48 +#define GPR4_OFFSET 52 +#define GPR5_OFFSET 56 +#define GPR6_OFFSET 60 +#define GPR7_OFFSET 64 +#define GPR8_OFFSET 68 +#define GPR9_OFFSET 72 +#define GPR10_OFFSET 76 +#define GPR11_OFFSET 80 +#define GPR12_OFFSET 84 +#define GPR13_OFFSET 88 +#define GPR14_OFFSET 92 +#define GPR15_OFFSET 96 +#define GPR16_OFFSET 100 +#define GPR17_OFFSET 104 +#define GPR18_OFFSET 108 +#define GPR19_OFFSET 112 +#define GPR20_OFFSET 116 +#define GPR21_OFFSET 120 +#define GPR22_OFFSET 124 +#define GPR23_OFFSET 128 +#define GPR24_OFFSET 132 +#define GPR25_OFFSET 136 +#define GPR26_OFFSET 140 +#define GPR27_OFFSET 144 +#define GPR28_OFFSET 148 +#define GPR29_OFFSET 152 +#define GPR30_OFFSET 156 +#define GPR31_OFFSET 160 +/* + * maintain the EABI requested 8 bytes aligment + * As SVR4 ABI requires 16, make it 16 (as some + * exception may need more registers to be processed...) + */ +#define EXCEPTION_FRAME_END 176 + +#ifndef ASM + +#include + +/* + * default raw exception handlers + */ + +extern void default_exception_vector_code_prolog(void); +extern int default_exception_vector_code_prolog_size; +extern void initialize_exceptions(void); + +typedef void rtems_exception_handler_t (CPU_Exception_frame* excPtr); +/*DEBUG typedef rtems_exception_handler_t cpuExcHandlerType; */ + +/* + * Exception handler table. + * + * This table contains pointers to assembly-language exception handlers. + * The common exception prologue in vectors.S looks up an entry in this + * table and jumps to it. No return address is saved, so the handlers in + * this table must return directly to the interrupted code. + * + * On entry to an exception handler, R1 points to a new exception stack + * frame in which R3, R4, and LR have been saved. R4 holds the exception + * number. + */ +extern rtems_exception_handler_t* exception_handler_table[NUM_EXCEPTIONS]; + +/* for compatability -- XXX remove */ +typedef rtems_exception_handler_t *cpuExcHandlerType; +extern cpuExcHandlerType *globalExceptHdl; + +#endif /* ASM */ + +#endif /* _LIBCPU_VECTORS_H */ diff --git a/bsps/powerpc/include/mpc55xx/dspi.h b/bsps/powerpc/include/mpc55xx/dspi.h new file mode 100644 index 0000000000..8ad98274ef --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/dspi.h @@ -0,0 +1,128 @@ +/** + * @file + * + * @ingroup mpc55xx_dspi + * + * @brief Header file for the LibI2C bus driver for the Deserial Serial Peripheral Interface (DSPI). + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup mpc55xx_dspi Deserial Serial Peripheral Interface (DSPI) + * + * @ingroup mpc55xx + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_DSPI_H +#define LIBCPU_POWERPC_MPC55XX_DSPI_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct DSPI_tag; + +typedef struct { + edma_channel_context edma; + rtems_id id; +} mpc55xx_dspi_edma_entry; + +/** + * @brief LibI2C bus driver entry. + */ +typedef struct { + /** + * @brief Standard bus driver fields. + */ + rtems_libi2c_bus_t bus; + + /** + * @brief Index in the bus table: @ref mpc55xx_dspi_bus_table. + */ + unsigned table_index; + + /** + * @brief Bus number (available after rtems_libi2c_register_bus()). + * + * @note You must set it in the initialization code after the bus registration. + */ + unsigned bus_number; + + /** + * @brief Hardware registers. + */ + volatile struct DSPI_tag *regs; + + /** + * @brief Selects SPI master or slave mode. + */ + bool master; + + /** + * @brief Data for the Push Register. + */ + union DSPI_PUSHR_tag push_data; + + /** + * @brief eDMA entry for transmission. + * + * The channel is fixed to a particular DSPI. + */ + mpc55xx_dspi_edma_entry edma_transmit; + + /** + * @brief eDMA entry for push data generation. + * + * You can choose every available channel. + */ + mpc55xx_dspi_edma_entry edma_push; + + /** + * @brief eDMA entry for receiving. + * + * The channel is fixed to a particular DSPI. + */ + mpc55xx_dspi_edma_entry edma_receive; + + /** + * @brief Idle character transmitted in read only mode. + */ + uint32_t idle_char; + + /** + * @brief Current baud. + */ + uint32_t baud; +} mpc55xx_dspi_bus_entry; + +/** + * @brief Number of DSPIs. + */ +#define MPC55XX_DSPI_NUMBER 4 + +/** + * @brief Table with bus driver entries. + */ +extern mpc55xx_dspi_bus_entry mpc55xx_dspi_bus_table [ /* MPC55XX_DSPI_NUMBER */ ]; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_DSPI_H */ diff --git a/bsps/powerpc/include/mpc55xx/edma.h b/bsps/powerpc/include/mpc55xx/edma.h new file mode 100644 index 0000000000..281cdf1c28 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/edma.h @@ -0,0 +1,329 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Enhanced Direct Memory Access (eDMA). + */ + +/* + * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_EDMA_H +#define LIBCPU_POWERPC_MPC55XX_EDMA_H + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if MPC55XX_CHIP_FAMILY == 551 + #define EDMA_CHANNEL_COUNT 16U +#elif MPC55XX_CHIP_FAMILY == 564 + #define EDMA_CHANNEL_COUNT 16U +#elif MPC55XX_CHIP_FAMILY == 567 + #define EDMA_CHANNEL_COUNT 96U +#else + #define EDMA_CHANNEL_COUNT 64U +#endif + +#define EDMA_MODULE_COUNT ((EDMA_CHANNEL_COUNT + 63U) / 64U) + +#define EDMA_CHANNELS_PER_MODULE 64U + +#if EDMA_MODULE_COUNT == 1 + #define EDMA_TCD_BY_CHANNEL_INDEX(channel_index) \ + (&EDMA.TCD[(channel_index)]) +#elif EDMA_MODULE_COUNT == 2 + #define EDMA_TCD_BY_CHANNEL_INDEX(channel_index) \ + ((channel_index) < EDMA_CHANNELS_PER_MODULE ? \ + &EDMA_A.TCD[(channel_index)] \ + : &EDMA_B.TCD[(channel_index) - EDMA_CHANNELS_PER_MODULE]) +#else + #error "unsupported module count" +#endif + +/* FIXME: These values are only valid for the MPC5566 and MPC5674F */ +typedef enum { + EDMA_EQADC_A_FISR0_CFFF0 = 0, + EDMA_EQADC_A_FISR0_RFDF0 = 1, + EDMA_EQADC_A_FISR1_CFFF1 = 2, + EDMA_EQADC_A_FISR1_RFDF1 = 3, + EDMA_EQADC_A_FISR2_CFFF2 = 4, + EDMA_EQADC_A_FISR2_RFDF2 = 5, + EDMA_EQADC_A_FISR3_CFFF3 = 6, + EDMA_EQADC_A_FISR3_RFDF3 = 7, + EDMA_EQADC_A_FISR4_CFFF4 = 8, + EDMA_EQADC_A_FISR4_RFDF4 = 9, + EDMA_EQADC_A_FISR5_CFFF5 = 10, + EDMA_EQADC_A_FISR5_RFDF5 = 11, + EDMA_DSPI_B_SR_TFFF = 12, + EDMA_DSPI_B_SR_RFDF = 13, + EDMA_DSPI_C_SR_TFFF = 14, + EDMA_DSPI_C_SR_RFDF = 15, + EDMA_DSPI_D_SR_TFFF = 16, + EDMA_DSPI_D_SR_RFDF = 17, + EDMA_ESCI_A_COMBTX = 18, + EDMA_ESCI_A_COMBRX = 19, + EDMA_EMIOS_GFR_F0 = 20, + EDMA_EMIOS_GFR_F1 = 21, + EDMA_EMIOS_GFR_F2 = 22, + EDMA_EMIOS_GFR_F3 = 23, + EDMA_EMIOS_GFR_F4 = 24, + EDMA_EMIOS_GFR_F8 = 25, + EDMA_EMIOS_GFR_F9 = 26, + EDMA_ETPU_CDTRSR_A_DTRS0 = 27, + EDMA_ETPU_CDTRSR_A_DTRS1 = 28, + EDMA_ETPU_CDTRSR_A_DTRS2 = 29, + EDMA_ETPU_CDTRSR_A_DTRS14 = 30, + EDMA_ETPU_CDTRSR_A_DTRS15 = 31, + EDMA_DSPI_A_SR_TFFF = 32, + EDMA_DSPI_A_SR_RFDF = 33, + EDMA_ESCI_B_COMBTX = 34, + EDMA_ESCI_B_COMBRX = 35, + EDMA_EMIOS_GFR_F6 = 36, + EDMA_EMIOS_GFR_F7 = 37, + EDMA_EMIOS_GFR_F10 = 38, + EDMA_EMIOS_GFR_F11 = 39, + EDMA_EMIOS_GFR_F16 = 40, + EDMA_EMIOS_GFR_F17 = 41, + EDMA_EMIOS_GFR_F18 = 42, + EDMA_EMIOS_GFR_F19 = 43, + EDMA_ETPU_CDTRSR_A_DTRS12 = 44, + EDMA_ETPU_CDTRSR_A_DTRS13 = 45, + EDMA_ETPU_CDTRSR_A_DTRS28 = 46, + EDMA_ETPU_CDTRSR_A_DTRS29 = 47, + EDMA_SIU_EISR_EIF0 = 48, + EDMA_SIU_EISR_EIF1 = 49, + EDMA_SIU_EISR_EIF2 = 50, + EDMA_SIU_EISR_EIF3 = 51, + EDMA_ETPU_CDTRSR_B_DTRS0 = 52, + EDMA_ETPU_CDTRSR_B_DTRS1 = 53, + EDMA_ETPU_CDTRSR_B_DTRS2 = 54, + EDMA_ETPU_CDTRSR_B_DTRS3 = 55, + EDMA_ETPU_CDTRSR_B_DTRS12 = 56, + EDMA_ETPU_CDTRSR_B_DTRS13 = 57, + EDMA_ETPU_CDTRSR_B_DTRS14 = 58, + EDMA_ETPU_CDTRSR_B_DTRS15 = 59, + EDMA_ETPU_CDTRSR_B_DTRS28 = 60, + EDMA_ETPU_CDTRSR_B_DTRS29 = 61, + EDMA_ETPU_CDTRSR_B_DTRS30 = 62, + EDMA_ETPU_CDTRSR_B_DTRS31 = 63 + #if MPC55XX_CHIP_FAMILY == 567 + , + EDMA_EQADC_B_FISR0_CFFF0 = 64 + 0, + EDMA_EQADC_B_FISR0_RFDF0 = 64 + 1, + EDMA_EQADC_B_FISR1_CFFF1 = 64 + 2, + EDMA_EQADC_B_FISR1_RFDF1 = 64 + 3, + EDMA_EQADC_B_FISR2_CFFF2 = 64 + 4, + EDMA_EQADC_B_FISR2_RFDF2 = 64 + 5, + EDMA_EQADC_B_FISR3_CFFF3 = 64 + 6, + EDMA_EQADC_B_FISR3_RFDF3 = 64 + 7, + EDMA_EQADC_B_FISR4_CFFF4 = 64 + 8, + EDMA_EQADC_B_FISR4_RFDF4 = 64 + 9, + EDMA_EQADC_B_FISR5_CFFF5 = 64 + 10, + EDMA_EQADC_B_FISR5_RFDF5 = 64 + 11, + EDMA_DECFILTER_A_IB = 64 + 12, + EDMA_DECFILTER_A_OB = 64 + 13, + EDMA_DECFILTER_B_IB = 64 + 14, + EDMA_DECFILTER_B_OB = 64 + 15, + EDMA_DECFILTER_C_IB = 64 + 16, + EDMA_DECFILTER_C_OB = 64 + 17, + EDMA_DECFILTER_D_IB = 64 + 18, + EDMA_DECFILTER_D_OB = 64 + 19, + EDMA_DECFILTER_E_IB = 64 + 20, + EDMA_DECFILTER_E_OB = 64 + 21, + EDMA_DECFILTER_F_IB = 64 + 22, + EDMA_DECFILTER_F_OB = 64 + 23, + EDMA_DECFILTER_G_IB = 64 + 24, + EDMA_DECFILTER_G_OB = 64 + 25, + EDMA_DECFILTER_H_IB = 64 + 26, + EDMA_DECFILTER_H_OB = 64 + 27 + #endif +} edma_channel; + +typedef struct edma_channel_context { + rtems_chain_node node; + volatile struct tcd_t *edma_tcd; + void (*done)(struct edma_channel_context *, uint32_t); +} edma_channel_context; + +void mpc55xx_edma_init(void); + +/** + * @brief Obtains an eDMA channel. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_RESOURCE_IN_USE The channel is already in use. + */ +rtems_status_code mpc55xx_edma_obtain_channel_by_tcd( + volatile struct tcd_t *edma_tcd +); + +void mpc55xx_edma_release_channel_by_tcd(volatile struct tcd_t *edma_tcd); + +/** + * @brief Obtains an eDMA channel and registers the channel context. + * + * The done handler of the channel context will be called + * - during minor or major loop completions if interrupts are enabled in the + * corresponding TCD, or + * - in case a channel error occurs. + * + * An error status value not equal to zero indicates an error. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_RESOURCE_IN_USE The channel is already in use. + * @retval RTEMS_IO_ERROR Unable to install interrupt handler for this channel. + */ +rtems_status_code mpc55xx_edma_obtain_channel( + edma_channel_context *ctx, + unsigned irq_priority +); + +void mpc55xx_edma_release_channel(edma_channel_context *ctx); + +/** + * @brief Copies a source TCD to an eDMA TCD. + * + * The DONE flag of the eDMA TCD is cleared before the actual copy operation. + * This enables the setting of channel link or scatter/gather options. + * + * This function can be used to start the channel if the START flags is + * set in the source TCD. + */ +void mpc55xx_edma_copy( + volatile struct tcd_t *edma_tcd, + const struct tcd_t *source_tcd +); + +/** + * @brief Copies a source TCD to an eDMA TCD and enables hardware requests. + * + * The DONE flag of the eDMA TCD is cleared before the actual copy operation. + * This enables the setting of channel link or scatter/gather options. + */ +void mpc55xx_edma_copy_and_enable_hardware_requests( + volatile struct tcd_t *edma_tcd, + const struct tcd_t *source_tcd +); + +void mpc55xx_edma_sg_link( + volatile struct tcd_t *edma_tcd, + const struct tcd_t *source_tcd +); + +static inline volatile struct EDMA_tag *mpc55xx_edma_by_tcd( + volatile struct tcd_t *edma_tcd +) +{ + return (volatile struct EDMA_tag *) + ((uintptr_t) edma_tcd & ~(uintptr_t) 0x1fff); +} + +static inline unsigned mpc55xx_edma_channel_by_tcd( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + + return edma_tcd - &edma->TCD[0]; +} + +static inline void mpc55xx_edma_enable_hardware_requests( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->SERQR.R = (uint8_t) channel; +} + +static inline void mpc55xx_edma_disable_hardware_requests( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->CERQR.R = (uint8_t) channel; +} + +static inline void mpc55xx_edma_enable_error_interrupts( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->SEEIR.R = (uint8_t) channel; +} + +static inline void mpc55xx_edma_disable_error_interrupts( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->CEEIR.R = (uint8_t) channel; +} + +static inline void mpc55xx_edma_set_start( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->SSBR.R = (uint8_t) channel; +} + +static inline void mpc55xx_edma_clear_done( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->CDSBR.R = (uint8_t) channel; +} + +static inline void mpc55xx_edma_clear_interrupts( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->CIRQR.R = (uint8_t) channel; +} + +static inline bool mpc55xx_edma_is_done( + volatile struct tcd_t *edma_tcd +) +{ + return edma_tcd->BMF.B.DONE; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_EDMA_H */ diff --git a/bsps/powerpc/include/mpc55xx/emios.h b/bsps/powerpc/include/mpc55xx/emios.h new file mode 100644 index 0000000000..d6ccadc07b --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/emios.h @@ -0,0 +1,197 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Enhanced Modular Input Output Subsystem (eMIOS). + */ + +/* + * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_EMIOS_H +#define LIBCPU_POWERPC_MPC55XX_EMIOS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef MPC55XX_HAS_EMIOS + +/** + * @name eMIOS - Modes + * + * @{ + */ + +#define MPC55XX_EMIOS_MODE_GPIO_INPUT 0U +#define MPC55XX_EMIOS_MODE_GPIO_OUTPUT 1U +#define MPC55XX_EMIOS_MODE_SAIC 2U +#define MPC55XX_EMIOS_MODE_SAOC 3U +#define MPC55XX_EMIOS_MODE_IPWM 4U +#define MPC55XX_EMIOS_MODE_IPM 5U +#define MPC55XX_EMIOS_MODE_DAOC_SECOND 6U +#define MPC55XX_EMIOS_MODE_DAOC_BOTH 7U +#define MPC55XX_EMIOS_MODE_PEA_ACCU_CONT 8U +#define MPC55XX_EMIOS_MODE_PEA_ACCU_SINGLE 9U +#define MPC55XX_EMIOS_MODE_PEA_COUNT_CONT 10U +#define MPC55XX_EMIOS_MODE_PEA_COUNT_SINGLE 11U +#define MPC55XX_EMIOS_MODE_QDEC_COUNT_DIR 12U +#define MPC55XX_EMIOS_MODE_QDEC_PHASE 13U +#define MPC55XX_EMIOS_MODE_WPTA 14U +#define MPC55XX_EMIOS_MODE_RESERVED_15 15U +#define MPC55XX_EMIOS_MODE_MC_UP_INT_CLK 16U +#define MPC55XX_EMIOS_MODE_MC_UP_EXT_CLK 17U +#define MPC55XX_EMIOS_MODE_RESERVED_18 18U +#define MPC55XX_EMIOS_MODE_RESERVED_19 19U +#define MPC55XX_EMIOS_MODE_MC_UP_DOWN_INT_CLK 20U +#define MPC55XX_EMIOS_MODE_MC_UP_DOWN_EXT_CLK 21U +#define MPC55XX_EMIOS_MODE_MC_UP_DOWN_CHANGE_INT_CLK 22U +#define MPC55XX_EMIOS_MODE_MC_UP_DOWN_CHANGE_EXT_CLK 23U +#define MPC55XX_EMIOS_MODE_OPWFM_B_IMMEDIATE 24U +#define MPC55XX_EMIOS_MODE_OPWFM_B_NEXT_PERIOD 25U +#define MPC55XX_EMIOS_MODE_OPWFM_AB_IMMEDIATE 26U +#define MPC55XX_EMIOS_MODE_OPWFM_AB_NEXT_PERIOD 27U +#define MPC55XX_EMIOS_MODE_OPWMC_TRAIL_TRAIL 28U +#define MPC55XX_EMIOS_MODE_OPWMC_TRAIL_LEAD 29U +#define MPC55XX_EMIOS_MODE_OPWMC_BOTH_TRAIL 30U +#define MPC55XX_EMIOS_MODE_OPWMC_BOTH_LEAD 31U +#define MPC55XX_EMIOS_MODE_OPWM_B_IMMEDIATE 32U +#define MPC55XX_EMIOS_MODE_OPWM_B_NEXT_PERIOD 33U +#define MPC55XX_EMIOS_MODE_OPWM_AB_IMMEDIATE 34U +#define MPC55XX_EMIOS_MODE_OPWM_AB_NEXT_PERIOD 35U +#define MPC55XX_EMIOS_MODE_RESERVED_36 36U +#define MPC55XX_EMIOS_MODE_RESERVED_37 37U +#define MPC55XX_EMIOS_MODE_RESERVED_38 38U +#define MPC55XX_EMIOS_MODE_RESERVED_39 39U +#define MPC55XX_EMIOS_MODE_RESERVED_40 40U +#define MPC55XX_EMIOS_MODE_RESERVED_41 41U +#define MPC55XX_EMIOS_MODE_RESERVED_42 42U +#define MPC55XX_EMIOS_MODE_RESERVED_43 43U +#define MPC55XX_EMIOS_MODE_RESERVED_44 44U +#define MPC55XX_EMIOS_MODE_RESERVED_45 45U +#define MPC55XX_EMIOS_MODE_RESERVED_46 46U +#define MPC55XX_EMIOS_MODE_RESERVED_47 47U +#define MPC55XX_EMIOS_MODE_RESERVED_48 48U +#define MPC55XX_EMIOS_MODE_RESERVED_49 49U +#define MPC55XX_EMIOS_MODE_RESERVED_50 50U +#define MPC55XX_EMIOS_MODE_RESERVED_51 51U +#define MPC55XX_EMIOS_MODE_RESERVED_52 52U +#define MPC55XX_EMIOS_MODE_RESERVED_53 53U +#define MPC55XX_EMIOS_MODE_RESERVED_54 54U +#define MPC55XX_EMIOS_MODE_RESERVED_55 55U +#define MPC55XX_EMIOS_MODE_RESERVED_56 56U +#define MPC55XX_EMIOS_MODE_RESERVED_57 57U +#define MPC55XX_EMIOS_MODE_RESERVED_58 58U +#define MPC55XX_EMIOS_MODE_RESERVED_59 59U +#define MPC55XX_EMIOS_MODE_RESERVED_60 60U +#define MPC55XX_EMIOS_MODE_RESERVED_61 61U +#define MPC55XX_EMIOS_MODE_RESERVED_62 62U +#define MPC55XX_EMIOS_MODE_RESERVED_63 63U +#define MPC55XX_EMIOS_MODE_RESERVED_64 64U +#define MPC55XX_EMIOS_MODE_RESERVED_65 65U +#define MPC55XX_EMIOS_MODE_RESERVED_66 66U +#define MPC55XX_EMIOS_MODE_RESERVED_67 67U +#define MPC55XX_EMIOS_MODE_RESERVED_68 68U +#define MPC55XX_EMIOS_MODE_RESERVED_69 69U +#define MPC55XX_EMIOS_MODE_RESERVED_70 70U +#define MPC55XX_EMIOS_MODE_RESERVED_71 71U +#define MPC55XX_EMIOS_MODE_RESERVED_72 72U +#define MPC55XX_EMIOS_MODE_RESERVED_73 73U +#define MPC55XX_EMIOS_MODE_RESERVED_74 74U +#define MPC55XX_EMIOS_MODE_RESERVED_75 75U +#define MPC55XX_EMIOS_MODE_RESERVED_76 76U +#define MPC55XX_EMIOS_MODE_RESERVED_77 77U +#define MPC55XX_EMIOS_MODE_RESERVED_78 78U +#define MPC55XX_EMIOS_MODE_RESERVED_79 79U +#define MPC55XX_EMIOS_MODE_MCB_UP_INT_CLK 80U +#define MPC55XX_EMIOS_MODE_MCB_UP_EXT_CLK 81U +#define MPC55XX_EMIOS_MODE_RESERVED_82 82U +#define MPC55XX_EMIOS_MODE_RESERVED_83 83U +#define MPC55XX_EMIOS_MODE_MCB_UP_DOWN_ONE_INT_CLK 84U +#define MPC55XX_EMIOS_MODE_MCB_UP_DOWN_ONE_EXT_CLK 85U +#define MPC55XX_EMIOS_MODE_MCB_UP_DOWN_BOTH_INT_CLK 86U +#define MPC55XX_EMIOS_MODE_MCB_UP_DOWN_BOTH_EXT_CLK 87U +#define MPC55XX_EMIOS_MODE_OPWFMB_B 88U +#define MPC55XX_EMIOS_MODE_RESERVED_89 89U +#define MPC55XX_EMIOS_MODE_OPWFMB_AB 90U +#define MPC55XX_EMIOS_MODE_RESERVED_91 91U +#define MPC55XX_EMIOS_MODE_OPWMCB_TRAIL_TRAIL 92U +#define MPC55XX_EMIOS_MODE_OPWMCB_TRAIL_LEAD 93U +#define MPC55XX_EMIOS_MODE_OPWMCB_BOTH_TRAIL 94U +#define MPC55XX_EMIOS_MODE_OPWMCB_BOTH_LEAD 95U +#define MPC55XX_EMIOS_MODE_OPWMB_SECOND 96U +#define MPC55XX_EMIOS_MODE_RESERVED_97 97U +#define MPC55XX_EMIOS_MODE_OPWMB_BOTH 98U +#define MPC55XX_EMIOS_MODE_RESERVED_99 99U +#define MPC55XX_EMIOS_MODE_RESERVED_100 100U +#define MPC55XX_EMIOS_MODE_RESERVED_101 101U +#define MPC55XX_EMIOS_MODE_RESERVED_102 102U +#define MPC55XX_EMIOS_MODE_RESERVED_103 103U +#define MPC55XX_EMIOS_MODE_RESERVED_104 104U +#define MPC55XX_EMIOS_MODE_RESERVED_105 105U +#define MPC55XX_EMIOS_MODE_RESERVED_106 106U +#define MPC55XX_EMIOS_MODE_RESERVED_107 107U +#define MPC55XX_EMIOS_MODE_RESERVED_108 108U +#define MPC55XX_EMIOS_MODE_RESERVED_109 109U +#define MPC55XX_EMIOS_MODE_RESERVED_110 110U +#define MPC55XX_EMIOS_MODE_RESERVED_111 111U +#define MPC55XX_EMIOS_MODE_RESERVED_112 112U +#define MPC55XX_EMIOS_MODE_RESERVED_113 113U +#define MPC55XX_EMIOS_MODE_RESERVED_114 114U +#define MPC55XX_EMIOS_MODE_RESERVED_115 115U +#define MPC55XX_EMIOS_MODE_RESERVED_116 116U +#define MPC55XX_EMIOS_MODE_RESERVED_117 117U +#define MPC55XX_EMIOS_MODE_RESERVED_118 118U +#define MPC55XX_EMIOS_MODE_RESERVED_119 119U +#define MPC55XX_EMIOS_MODE_RESERVED_120 120U +#define MPC55XX_EMIOS_MODE_RESERVED_121 121U +#define MPC55XX_EMIOS_MODE_RESERVED_122 122U +#define MPC55XX_EMIOS_MODE_RESERVED_123 123U +#define MPC55XX_EMIOS_MODE_RESERVED_124 124U +#define MPC55XX_EMIOS_MODE_RESERVED_125 125U +#define MPC55XX_EMIOS_MODE_RESERVED_126 126U +#define MPC55XX_EMIOS_MODE_RESERVED_127 127U + +/** @} */ + +#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 + #define MPC55XX_EMIOS_CHANNEL_NUMBER 32U +#else + #define MPC55XX_EMIOS_CHANNEL_NUMBER 24U +#endif + +#define MPC55XX_EMIOS_VALUE_MAX 0x00ffffffU + +#define MPC55XX_EMIOS_IS_CHANNEL_VALID( c) \ + ((unsigned) (c) < MPC55XX_EMIOS_CHANNEL_NUMBER) + +#define MPC55XX_EMIOS_IS_CHANNEL_INVALID( c) \ + (!MPC55XX_EMIOS_IS_CHANNEL_VALID( c)) + +void mpc55xx_emios_initialize( unsigned prescaler); + +unsigned mpc55xx_emios_global_prescaler( void); + +void mpc55xx_emios_set_global_prescaler( unsigned prescaler); + +#endif /* MPC55XX_HAS_EMIOS */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_EMIOS_H */ diff --git a/bsps/powerpc/include/mpc55xx/fsl-mpc551x.h b/bsps/powerpc/include/mpc55xx/fsl-mpc551x.h new file mode 100644 index 0000000000..dec0b4cf73 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/fsl-mpc551x.h @@ -0,0 +1,4005 @@ +/* + * Modifications of the original file provided by Freescale are: + * + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/**************************************************************************/ +/* FILE NAME: mpc5510.h COPYRIGHT (c) Freescale 2008 */ +/* REVISION: 2.2 All Rights Reserved */ +/* */ +/* DESCRIPTION: */ +/* This file contain all of the register and bit field definitions for */ +/* MPC5510. */ +/**************************************************************************/ +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +/*************************************************/ +/* Example register & bit field write: */ +/* */ +/* ..B. = 1; */ +/* ..R = 0x10000000; */ +/* */ +/*************************************************/ + +#ifndef _MPC5510_H_ +#define _MPC5510_H_ + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/****************************************************************************/ +/* MODULE : CRP */ +/****************************************************************************/ + struct CRP_tag { + + union { + uint32_t R; + struct { + uint32_t:12; + uint32_t IRC32KEN:1; + uint32_t XOSCEN:1; + uint32_t:1; + uint32_t OSC32KEN:1; + uint32_t TRIM32IRC:8; + uint32_t TRIMIRC:8; + } B; + } CLKSRC; /* Clock Source Register */ + + uint32_t crp_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t CNTEN:1; + uint32_t RTCIE:1; + uint32_t RTCF:1; + uint32_t ROVRF:1; + uint32_t RTCVAL:12; + uint32_t APIEN:1; + uint32_t APIIE:1; + uint32_t APIF:1; + uint32_t CLKSEL:2; + uint32_t ROVREN:1; + uint32_t APIVAL:10; + } B; + } RTCSC; /* RTC Status and Control Register */ + + union { + uint32_t R; + struct { + uint32_t RTCCNT:32; + } B; + } RTCCNT; /* RTC Counter Register */ + + uint32_t crp_reserved2[10]; + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t WKPSEL7:3; + uint32_t:1; + uint32_t WKPSEL6:3; + uint32_t:1; + uint32_t WKPSEL5:3; + uint32_t:1; + uint32_t WKPSEL4:3; + uint32_t:1; + uint32_t WKPSEL3:3; + uint32_t:1; + uint32_t WKPSEL2:3; + uint32_t:1; + uint32_t WKPSEL1:3; + uint32_t:1; + uint32_t WKPSEL0:3; + } B; + } WKPINSEL; /* Wakeup Pin Source Select Register */ + + union { + uint32_t R; + struct { + uint32_t WKPDET7:2; + uint32_t WKPDET6:2; + uint32_t WKPDET5:2; + uint32_t WKPDET4:2; + uint32_t WKPDET3:2; + uint32_t WKPDET2:2; + uint32_t WKPDET1:2; + uint32_t WKPDET0:2; + uint32_t:5; + uint32_t RTCOVREN:1; + uint32_t RTCWKEN:1; + uint32_t APIWKEN:1; + uint32_t:7; + uint32_t WKCLKSEL:1; + } B; + } WKSE; /* Wakeup Source Enable Register */ + + uint32_t crp_reserved3[2]; + + union { + uint32_t R; + struct { + uint32_t Z1VEC:30; + uint32_t Z1RST:1; + uint32_t VLE:1; + } B; + } Z1VEC; /* Z1 Reset Vector Register */ + + union { + uint32_t R; + struct { + uint32_t Z0VEC:30; + uint32_t Z0RST:1; + uint32_t:1; + } B; + } Z0VEC; /* Z0 Reset Vector Register */ + + union { + uint32_t R; + struct { + uint32_t RECPTR:30; + uint32_t FASTREC:1; + uint32_t:1; + } B; + } RECPTR; /* Reset Recovery Pointer Register */ + + uint32_t crp_reserved4; + + union { + uint32_t R; + struct { + uint32_t SLEEPF:1; + uint32_t STOPF:1; + uint32_t:3; + uint32_t WKRLLOVRF:1; + uint32_t WKAPIF:1; + uint32_t WKRTCF:1; + uint32_t PWKSCRF:8; + uint32_t SLEEP:1; + uint32_t STOP:1; + uint32_t:1; + uint32_t PKREL:1; + uint32_t SLP12EN:1; + uint32_t RAMSEL:3; + uint32_t PWKSRIE:8; + } B; + } PSCR; /* Power Status and Control Register */ + + uint32_t crp_reserved5[3]; + + union { + uint32_t R; + struct { + uint32_t LVI5IE:1; + uint32_t LVI5HIE:1; + uint32_t LVI5F:1; + uint32_t LVI5HF:1; + uint32_t LVI5LOCK:1; + uint32_t LVI5RE:1; + uint32_t:9; + uint32_t BYPDIS:1; + uint32_t:16; + } B; + } SOCSC; /* LVI Status and Control Register */ + + }; +/****************************************************************************/ +/* MODULE : DMAMUX */ +/****************************************************************************/ + struct DMAMUX_tag { + union { + uint8_t R; + struct { + uint8_t ENBL:1; + uint8_t TRIG:1; + uint8_t SOURCE:6; + } B; + } CHCONFIG[16]; /* DMA Channel Configuration Register */ + + }; +/****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + struct DSPI_tag { + union DSPI_MCR_tag { + uint32_t R; + struct { + uint32_t MSTR:1; + uint32_t CONT_SCKE:1; + uint32_t DCONF:2; + uint32_t FRZ:1; + uint32_t MTFE:1; + uint32_t PCSSE:1; + uint32_t ROOE:1; + uint32_t:2; + uint32_t PCSIS5:1; + uint32_t PCSIS4:1; + uint32_t PCSIS3:1; + uint32_t PCSIS2:1; + uint32_t PCSIS1:1; + uint32_t PCSIS0:1; + uint32_t:1; + uint32_t MDIS:1; + uint32_t DIS_TXF:1; + uint32_t DIS_RXF:1; + uint32_t CLR_TXF:1; + uint32_t CLR_RXF:1; + uint32_t SMPL_PT:2; + uint32_t:7; + uint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t dspi_reserved1; + + union { + uint32_t R; + struct { + uint32_t SPI_TCNT:16; + uint32_t:16; + } B; + } TCR; + + union DSPI_CTAR_tag { + uint32_t R; + struct { + uint32_t DBR:1; + uint32_t FMSZ:4; + uint32_t CPOL:1; + uint32_t CPHA:1; + uint32_t LSBFE:1; + uint32_t PCSSCK:2; + uint32_t PASC:2; + uint32_t PDT:2; + uint32_t PBR:2; + uint32_t CSSCK:4; + uint32_t ASC:4; + uint32_t DT:4; + uint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers */ + + union DSPI_SR_tag { + uint32_t R; + struct { + uint32_t TCF:1; + uint32_t TXRXS:1; + uint32_t:1; + uint32_t EOQF:1; + uint32_t TFUF:1; + uint32_t:1; + uint32_t TFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t TXCTR:4; + uint32_t TXNXTPTR:4; + uint32_t RXCTR:4; + uint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register */ + + union DSPI_RSER_tag { + uint32_t R; + struct { + uint32_t TCF_RE:1; + uint32_t:2; + uint32_t EOQFRE:1; + uint32_t TFUFRE:1; + uint32_t:1; + uint32_t TFFFRE:1; + uint32_t TFFFDIRS:1; + uint32_t:4; + uint32_t RFOFRE:1; + uint32_t:1; + uint32_t RFDFRE:1; + uint32_t RFDFDIRS:1; + uint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register */ + + union DSPI_PUSHR_tag { + uint32_t R; + struct { + uint32_t CONT:1; + uint32_t CTAS:3; + uint32_t EOQ:1; + uint32_t CTCNT:1; + uint32_t:4; + uint32_t PCS5:1; + uint32_t PCS4:1; + uint32_t PCS3:1; + uint32_t PCS2:1; + uint32_t PCS1:1; + uint32_t PCS0:1; + uint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register */ + + union DSPI_POPR_tag { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register */ + + union { + uint32_t R; + struct { + uint32_t TXCMD:16; + uint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_txf[12]; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_rxf[12]; + + union { + uint32_t R; + struct { + uint32_t:12; + uint32_t TXSS:1; + uint32_t:2; + uint32_t CID:1; + uint32_t DCONT:1; + uint32_t DSICTAS:3; + uint32_t:6; + uint32_t DPCS5:1; + uint32_t DPCS4:1; + uint32_t DPCS3:1; + uint32_t DPCS2:1; + uint32_t DPCS1:1; + uint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t SER_DATA:16; + } B; + } SDR; /* DSI Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t ASER_DATA:16; + } B; + } ASDR; /* DSI Alternate Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t COMP_DATA:16; + } B; + } COMPR; /* DSI Transmit Comparison Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t DESER_DATA:16; + } B; + } DDR; /* DSI deserialization Data Register */ + + }; +/****************************************************************************/ +/* MODULE : External Bus Interface (EBI) */ +/****************************************************************************/ + +/* CS_tag instantiated within EBI_tag */ + struct EBI_CS_tag { + union { /* Base Register Bank */ + uint32_t R; + struct { + uint32_t BA:17; + uint32_t:3; + uint32_t PS:1; + uint32_t:3; + uint32_t AD_MUX:1; + uint32_t BL:1; + uint32_t WEBS:1; + uint32_t TBDIP:1; + uint32_t:1; + uint32_t SETA:1; + uint32_t BI:1; + uint32_t V:1; + } B; + } BR; + + union { /* Option Register Bank */ + uint32_t R; + struct { + uint32_t AM:17; + uint32_t:7; + uint32_t SCY:4; + uint32_t:1; + uint32_t BSCY:2; + uint32_t:1; + } B; + } OR; + }; + + struct EBI_CAL_CS_tag { + uint32_t ebi_cal_cs_reserved [2]; + }; + + struct EBI_tag { + union EBI_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ACGE:1; + uint32_t EXTM:1; + uint32_t EARB:1; + uint32_t:6; + uint32_t MDIS:1; + uint32_t:3; + uint32_t D16_31:1; + uint32_t AD_MUX:1; + uint32_t DBM:1; + } B; + } MCR; + + uint32_t EBI_reserved1; + + union { /* Transfer Error Status Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t TEAF:1; + uint32_t BMTF:1; + } B; + } TESR; + + union { /* Bus Monitor Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t BMT:8; + uint32_t BME:1; + uint32_t:7; + } B; + } BMCR; + + /* Roll in 3x CS registers */ + struct EBI_CS_tag CS[4]; + + uint32_t EBI_reserved2[4]; + + struct EBI_CAL_CS_tag CAL_CS[4]; + }; +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + struct EMIOS_tag { + union EMIOS_MCR_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t GTBE:1; + uint32_t:1; + uint32_t GPREN:1; + uint32_t:10; + uint32_t GPRE:8; + uint32_t:8; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t F23:1; + uint32_t F22:1; + uint32_t F21:1; + uint32_t F20:1; + uint32_t F19:1; + uint32_t F18:1; + uint32_t F17:1; + uint32_t F16:1; + uint32_t F15:1; + uint32_t F14:1; + uint32_t F13:1; + uint32_t F12:1; + uint32_t F11:1; + uint32_t F10:1; + uint32_t F9:1; + uint32_t F8:1; + uint32_t F7:1; + uint32_t F6:1; + uint32_t F5:1; + uint32_t F4:1; + uint32_t F3:1; + uint32_t F2:1; + uint32_t F1:1; + uint32_t F0:1; + } B; + } GFG; /* Global FLAG Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t OU23:1; + uint32_t OU22:1; + uint32_t OU21:1; + uint32_t OU20:1; + uint32_t OU19:1; + uint32_t OU18:1; + uint32_t OU17:1; + uint32_t OU16:1; + uint32_t OU15:1; + uint32_t OU14:1; + uint32_t OU13:1; + uint32_t OU12:1; + uint32_t OU11:1; + uint32_t OU10:1; + uint32_t OU9:1; + uint32_t OU8:1; + uint32_t OU7:1; + uint32_t OU6:1; + uint32_t OU5:1; + uint32_t OU4:1; + uint32_t OU3:1; + uint32_t OU2:1; + uint32_t OU1:1; + uint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t UC23:1; + uint32_t UC22:1; + uint32_t UC21:1; + uint32_t UC20:1; + uint32_t UC19:1; + uint32_t UC18:1; + uint32_t UC17:1; + uint32_t UC16:1; + uint32_t UC15:1; + uint32_t UC14:1; + uint32_t UC13:1; + uint32_t UC12:1; + uint32_t UC11:1; + uint32_t UC10:1; + uint32_t UC9:1; + uint32_t UC8:1; + uint32_t UC7:1; + uint32_t UC6:1; + uint32_t UC5:1; + uint32_t UC4:1; + uint32_t UC3:1; + uint32_t UC2:1; + uint32_t UC1:1; + uint32_t UC0:1; + } B; + } UCDIS; /* Disable Channel Register */ + + uint32_t emios_reserved1[4]; + + struct EMIOS_CH_tag { + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t A:16; /* Channel A Data Register */ + } B; + } CADR; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t B:16; /* Channel B Data Register */ + } B; + } CBDR; + + union { + uint32_t R; /* Channel Counter Register */ + struct { + uint32_t:16; + uint32_t C:16; /* Channel C Data Register */ + } B; + } CCNTR; + + union EMIOS_CCR_tag { + uint32_t R; + struct { + uint32_t FREN:1; + uint32_t ODIS:1; + uint32_t ODISSL:2; + uint32_t UCPRE:2; + uint32_t UCPREN:1; + uint32_t DMA:1; + uint32_t:1; + uint32_t IF:4; + uint32_t FCK:1; + uint32_t FEN:1; + uint32_t:3; + uint32_t FORCMA:1; + uint32_t FORCMB:1; + uint32_t:1; + uint32_t BSL:2; + uint32_t EDSEL:1; + uint32_t EDPOL:1; + uint32_t MODE:7; + } B; + } CCR; /* Channel Control Register */ + + union EMIOS_CSR_tag { + uint32_t R; + struct { + uint32_t OVR:1; + uint32_t:15; + uint32_t OVFL:1; + uint32_t:12; + uint32_t UCIN:1; + uint32_t UCOUT:1; + uint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register */ + + union { + uint32_t R; /* Alternate Channel A Data Register */ + } ALTA; + + uint32_t emios_channel_reserved[2]; + + } CH[24]; + + }; +/****************************************************************************/ +/* MODULE : EQADC */ +/****************************************************************************/ + struct EQADC_tag { + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t DBG:2; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t eqadc_reserved0; + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t NMF:26; + } B; + } NMSFR; /* Null Message Send Format Register */ + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } ETDFR; /* External Trigger Digital Filter Register */ + + union { + uint32_t R; + struct { + uint32_t CF_PUSH:32; + } B; + } CFPR[6]; /* CFIFO Push Registers */ + + uint32_t eqadc_reserved1; + + uint32_t eqadc_reserved2; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RF_POP:16; + } B; + } RFPR[6]; /* Result FIFO Pop Registers */ + + uint32_t eqadc_reserved3; + + uint32_t eqadc_reserved4; + + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t SSE:1; + uint16_t CFINV:1; + uint16_t:1; + uint16_t MODE:4; + uint16_t:4; + } B; + } CFCR[6]; /* CFIFO Control Registers */ + + uint32_t eqadc_reserved5; + + union { + uint16_t R; + struct { + uint16_t NCIE:1; + uint16_t TORIE:1; + uint16_t PIE:1; + uint16_t EOQIE:1; + uint16_t CFUIE:1; + uint16_t:1; + uint16_t CFFE:1; + uint16_t CFFS:1; + uint16_t:4; + uint16_t RFOIE:1; + uint16_t:1; + uint16_t RFDE:1; + uint16_t RFDS:1; + } B; + } IDCR[6]; /* Interrupt and DMA Control Registers */ + + uint32_t eqadc_reserved6; + + union { + uint32_t R; + struct { + uint32_t NCF:1; + uint32_t TORF:1; + uint32_t PF:1; + uint32_t EOQF:1; + uint32_t CFUF:1; + uint32_t SSS:1; + uint32_t CFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t CFCTR:4; + uint32_t TNXTPTR:4; + uint32_t RFCTR:4; + uint32_t POPNXTPTR:4; + } B; + } FISR[6]; /* FIFO and Interrupt Status Registers */ + + uint32_t eqadc_reserved7; + + uint32_t eqadc_reserved8; + + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t TC_CF:11; + } B; + } CFTCR[6]; /* CFIFO Transfer Counter Registers */ + + uint32_t eqadc_reserved9; + + union { + uint32_t R; + struct { + uint32_t CFS0_T0:2; + uint32_t CFS1_T0:2; + uint32_t CFS2_T0:2; + uint32_t CFS3_T0:2; + uint32_t CFS4_T0:2; + uint32_t CFS5_T0:2; + uint32_t:5; + uint32_t LCFT0:4; + uint32_t TC_LCFT0:11; + } B; + } CFSSR0; /* CFIFO Status Register 0 */ + + uint32_t eqadc_reserved10[2]; + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:20; + } B; + } CFSR; + + uint32_t eqadc_reserved11[20]; + + struct { + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved12[12]; + + } CF[6]; + + uint32_t eqadc_reserved13[32]; + + struct { + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved14[12]; + + } RF[6]; + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_tag { + union ESCI_CR1_tag { + uint32_t R; + struct { + uint32_t:3; + uint32_t SBR:13; + uint32_t LOOPS:1; + uint32_t:1; + uint32_t RSRC:1; + uint32_t M:1; + uint32_t WAKE:1; + uint32_t ILT:1; + uint32_t PE:1; + uint32_t PT:1; + uint32_t TIE:1; + uint32_t TCIE:1; + uint32_t RIE:1; + uint32_t ILIE:1; + uint32_t TE:1; + uint32_t RE:1; + uint32_t RWU:1; + uint32_t SBK:1; + } B; + } CR1; /* Control Register 1 */ + + union ESCI_CR2_tag { + uint16_t R; + struct { + uint16_t MDIS:1; + uint16_t FBR:1; + uint16_t BSTP:1; + uint16_t IEBERR:1; + uint16_t RXDMA:1; + uint16_t TXDMA:1; + uint16_t BRK13:1; + uint16_t TXDIR:1; + uint16_t BESM13:1; + uint16_t SBSTP:1; + uint16_t:1; + uint16_t PMSK:1; + uint16_t ORIE:1; + uint16_t NFIE:1; + uint16_t FEIE:1; + uint16_t PFIE:1; + } B; + } CR2; /* Control Register 2 */ + + union ESCI_DR_tag { + uint16_t R; + struct { + uint16_t R8:1; + uint16_t T8:1; + uint16_t:6; + uint8_t D; + } B; + } DR; /* Data Register */ + + union ESCI_SR_tag { + uint32_t R; + struct { + uint32_t TDRE:1; + uint32_t TC:1; + uint32_t RDRF:1; + uint32_t IDLE:1; + uint32_t OR:1; + uint32_t NF:1; + uint32_t FE:1; + uint32_t PF:1; + uint32_t:3; + uint32_t BERR:1; + uint32_t:3; + uint32_t RAF:1; + uint32_t RXRDY:1; + uint32_t TXRDY:1; + uint32_t LWAKE:1; + uint32_t STO:1; + uint32_t PBERR:1; + uint32_t CERR:1; + uint32_t CKERR:1; + uint32_t FRC:1; + uint32_t:6; + uint32_t UREQ:1; + uint32_t OVFL:1; + } B; + } SR; /* Status Register */ + + union { + uint32_t R; + struct { + uint32_t LRES:1; + uint32_t WU:1; + uint32_t WUD0:1; + uint32_t WUD1:1; + uint32_t LDBG:1; + uint32_t DSF:1; + uint32_t PRTY:1; + uint32_t LIN:1; + uint32_t RXIE:1; + uint32_t TXIE:1; + uint32_t WUIE:1; + uint32_t STIE:1; + uint32_t PBIE:1; + uint32_t CIE:1; + uint32_t CKIE:1; + uint32_t FCIE:1; + uint32_t:6; + uint32_t UQIE:1; + uint32_t OFIE:1; + uint32_t:8; + } B; + } LCR; /* LIN Control Register */ + + union { + uint32_t R; + } LTR; /* LIN Transmit Register */ + + union { + uint32_t R; + } LRR; /* LIN Recieve Register */ + + union { + uint32_t R; + } LPR; /* LIN CRC Polynom Register */ + + }; +/****************************************************************************/ +/* MODULE : FLASH */ +/****************************************************************************/ + struct FLASH_tag { + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:3; + uint32_t SFS:1; + uint32_t SIZE:4; + uint32_t:1; + uint32_t LAS:3; + uint32_t:3; + uint32_t MAS:1; + uint32_t EER:1; + uint32_t RWE:1; + uint32_t BBEPE:1; + uint32_t EPE:1; + uint32_t PEAS:1; + uint32_t DONE:1; + uint32_t PEG:1; + uint32_t:1; + uint32_t PRD:1; + uint32_t STOP:1; + uint32_t:1; + uint32_t PGM:1; + uint32_t PSUS:1; + uint32_t ERS:1; + uint32_t ESUS:1; + uint32_t EHV:1; + } B; + } MCR; + + union LMLR_tag { /* Low/Mid Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t LME:1; + uint32_t:10; + uint32_t SLOCK:1; + uint32_t:2; + uint32_t MLOCK:2; + uint32_t:6; + uint32_t LLOCK:10; + } B; + } LMLR; /* Legacy naming - refer to LML in Reference Manual */ + + union HLR_tag { /* High Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t HBE:1; + uint32_t:23; + uint32_t HBLOCK:8; + } B; + } HLR; /* Legacy naming - refer to HBL in Reference Manual */ + + union SLMLR_tag { /* Secondary Low/Mid Block Locking Register */ + uint32_t R; + struct { + uint32_t SLE:1; + uint32_t:10; + uint32_t SSLOCK:1; + uint32_t:2; + uint32_t SMLOCK:2; + uint32_t:6; + uint32_t SLLOCK:10; + } B; + } SLMLR; /* Legacy naming - refer to SLL in Reference Manual */ + + union { /* Low/Mid Address Space Block Select Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MSEL:2; + uint32_t:6; + uint32_t LSEL:10; + } B; + } LMSR; /* Legacy naming - refer to LMS in Reference Manual */ + + union { /* High Address Space Block Select Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t HBSEL:4; + } B; + } HSR; /* Legacy naming - refer to HBS in Reference Manual */ + + union { /* Address Register */ + uint32_t R; + struct { + uint32_t:10; + uint32_t ADDR:19; + uint32_t:3; + } B; + } AR; /* Legacy naming - refer to ADR in Reference Manual */ + + union { /* Platform Flash Configuration Register for Port 0 */ + uint32_t R; + struct { + uint32_t LBCFG:4; + uint32_t ARB:1; + uint32_t PRI:1; + uint32_t:5; + uint32_t M4PFE:1; + uint32_t M3PFE:1; + uint32_t M2PFE:1; + uint32_t M1PFE:1; + uint32_t M0PFE:1; + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + uint32_t:1; + uint32_t DPFEN:1; + uint32_t:1; + uint32_t IPFEN:1; + uint32_t:1; + uint32_t PFLIM:2; + uint32_t BFEN:1; + } B; + } PFCRP0; + + union { /* Platform Flash Configuration Register for Port 1 */ + uint32_t R; + struct { + uint32_t LBCFG:4; + uint32_t:7; + uint32_t M4PFE:1; + uint32_t M3PFE:1; + uint32_t M2PFE:1; + uint32_t M1PFE:1; + uint32_t M0PFE:1; + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + uint32_t:1; + uint32_t DPFEN:1; + uint32_t:1; + uint32_t IPFEN:1; + uint32_t:1; + uint32_t PFLIM:2; + uint32_t BFEN:1; + } B; + } PFCRP1; + + }; +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + struct FLEXCAN_tag { + union { + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t FEN:1; + uint32_t HALT:1; + uint32_t NOTRDY:1; + uint32_t WAKMSK:1; + uint32_t SOFTRST:1; + uint32_t FRZACK:1; + uint32_t SUPV:1; + uint32_t SLFWAK:1; + uint32_t WRNEN:1; + uint32_t LPMACK:1; + uint32_t WAKSRC:1; + uint32_t DOZE:1; + uint32_t SRXDIS:1; + uint32_t BCC:1; + uint32_t:2; + uint32_t LPRIO_EN:1; + uint32_t AEN:1; + uint32_t:2; + uint32_t IDAM:2; + uint32_t:2; + uint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t PRESDIV:8; + uint32_t RJW:2; + uint32_t PSEG1:3; + uint32_t PSEG2:3; + uint32_t BOFFMSK:1; + uint32_t ERRMSK:1; + uint32_t CLKSRC:1; + uint32_t LPB:1; + uint32_t TWRNMSK:1; + uint32_t RWRNMSK:1; + uint32_t:2; + uint32_t SMP:1; + uint32_t BOFFREC:1; + uint32_t TSYN:1; + uint32_t LBUF:1; + uint32_t LOM:1; + uint32_t PROPSEG:3; + } B; + } CTRL; /* Control Register */ + + union { + uint32_t R; + } TIMER; /* Free Running Timer */ + + uint32_t FLEXCAN_reserved1; + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXECNT:8; + uint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + uint32_t R; + struct { + uint32_t:14; + uint32_t TWRNINT:1; + uint32_t RWRNINT:1; + uint32_t BIT1ERR:1; + uint32_t BIT0ERR:1; + uint32_t ACKERR:1; + uint32_t CRCERR:1; + uint32_t FRMERR:1; + uint32_t STFERR:1; + uint32_t TXWRN:1; + uint32_t RXWRN:1; + uint32_t IDLE:1; + uint32_t TXRX:1; + uint32_t FLTCONF:2; + uint32_t:1; + uint32_t BOFFINT:1; + uint32_t ERRINT:1; + uint32_t WAKINT:1; + } B; + } ESR; /* Error and Status Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63M:1; + uint32_t BUF62M:1; + uint32_t BUF61M:1; + uint32_t BUF60M:1; + uint32_t BUF59M:1; + uint32_t BUF58M:1; + uint32_t BUF57M:1; + uint32_t BUF56M:1; + uint32_t BUF55M:1; + uint32_t BUF54M:1; + uint32_t BUF53M:1; + uint32_t BUF52M:1; + uint32_t BUF51M:1; + uint32_t BUF50M:1; + uint32_t BUF49M:1; + uint32_t BUF48M:1; + uint32_t BUF47M:1; + uint32_t BUF46M:1; + uint32_t BUF45M:1; + uint32_t BUF44M:1; + uint32_t BUF43M:1; + uint32_t BUF42M:1; + uint32_t BUF41M:1; + uint32_t BUF40M:1; + uint32_t BUF39M:1; + uint32_t BUF38M:1; + uint32_t BUF37M:1; + uint32_t BUF36M:1; + uint32_t BUF35M:1; + uint32_t BUF34M:1; + uint32_t BUF33M:1; + uint32_t BUF32M:1; + } B; + } IMASK2; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31M:1; + uint32_t BUF30M:1; + uint32_t BUF29M:1; + uint32_t BUF28M:1; + uint32_t BUF27M:1; + uint32_t BUF26M:1; + uint32_t BUF25M:1; + uint32_t BUF24M:1; + uint32_t BUF23M:1; + uint32_t BUF22M:1; + uint32_t BUF21M:1; + uint32_t BUF20M:1; + uint32_t BUF19M:1; + uint32_t BUF18M:1; + uint32_t BUF17M:1; + uint32_t BUF16M:1; + uint32_t BUF15M:1; + uint32_t BUF14M:1; + uint32_t BUF13M:1; + uint32_t BUF12M:1; + uint32_t BUF11M:1; + uint32_t BUF10M:1; + uint32_t BUF09M:1; + uint32_t BUF08M:1; + uint32_t BUF07M:1; + uint32_t BUF06M:1; + uint32_t BUF05M:1; + uint32_t BUF04M:1; + uint32_t BUF03M:1; + uint32_t BUF02M:1; + uint32_t BUF01M:1; + uint32_t BUF00M:1; + } B; + } IMASK1; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63I:1; + uint32_t BUF62I:1; + uint32_t BUF61I:1; + uint32_t BUF60I:1; + uint32_t BUF59I:1; + uint32_t BUF58I:1; + uint32_t BUF57I:1; + uint32_t BUF56I:1; + uint32_t BUF55I:1; + uint32_t BUF54I:1; + uint32_t BUF53I:1; + uint32_t BUF52I:1; + uint32_t BUF51I:1; + uint32_t BUF50I:1; + uint32_t BUF49I:1; + uint32_t BUF48I:1; + uint32_t BUF47I:1; + uint32_t BUF46I:1; + uint32_t BUF45I:1; + uint32_t BUF44I:1; + uint32_t BUF43I:1; + uint32_t BUF42I:1; + uint32_t BUF41I:1; + uint32_t BUF40I:1; + uint32_t BUF39I:1; + uint32_t BUF38I:1; + uint32_t BUF37I:1; + uint32_t BUF36I:1; + uint32_t BUF35I:1; + uint32_t BUF34I:1; + uint32_t BUF33I:1; + uint32_t BUF32I:1; + } B; + } IFLAG2; /* Interruput Flag Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31I:1; + uint32_t BUF30I:1; + uint32_t BUF29I:1; + uint32_t BUF28I:1; + uint32_t BUF27I:1; + uint32_t BUF26I:1; + uint32_t BUF25I:1; + uint32_t BUF24I:1; + uint32_t BUF23I:1; + uint32_t BUF22I:1; + uint32_t BUF21I:1; + uint32_t BUF20I:1; + uint32_t BUF19I:1; + uint32_t BUF18I:1; + uint32_t BUF17I:1; + uint32_t BUF16I:1; + uint32_t BUF15I:1; + uint32_t BUF14I:1; + uint32_t BUF13I:1; + uint32_t BUF12I:1; + uint32_t BUF11I:1; + uint32_t BUF10I:1; + uint32_t BUF09I:1; + uint32_t BUF08I:1; + uint32_t BUF07I:1; + uint32_t BUF06I:1; + uint32_t BUF05I:1; + uint32_t BUF04I:1; + uint32_t BUF03I:1; + uint32_t BUF02I:1; + uint32_t BUF01I:1; + uint32_t BUF00I:1; + } B; + } IFLAG1; /* Interruput Flag Register */ + + uint32_t FLEXCAN_reserved2[19]; + + struct canbuf_t { + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t CODE:4; + uint32_t:1; + uint32_t SRR:1; + uint32_t IDE:1; + uint32_t RTR:1; + uint32_t LENGTH:4; + uint32_t TIMESTAMP:16; + } B; + } CS; + + union { + uint32_t R; + struct { + uint32_t PRIO:3; + uint32_t STD_ID:11; + uint32_t EXT_ID:18; + } B; + } ID; + + union { + uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + uint32_t W[2]; /* Data buffer in words (32 bits) */ + uint32_t R[2]; /* Data buffer in words (32 bits) */ + } DATA; + + } BUF[64]; + + uint32_t FLEXCAN_reserved3[256]; + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RXIMR[64]; /* RX Individual Mask Registers */ + + }; +/****************************************************************************/ +/* MODULE : FMPLL */ +/****************************************************************************/ + struct FMPLL_tag { + + uint32_t FMPLL_reserved0; + + union FMPLL_SYNSR_tag { /* Synthesiser Status Register */ + uint32_t R; + struct { + uint32_t:22; + uint32_t LOLF:1; + uint32_t LOC:1; + uint32_t MODE:1; + uint32_t PLLSEL:1; + uint32_t PLLREF:1; + uint32_t LOCKS:1; + uint32_t LOCK:1; + uint32_t LOCF:1; + uint32_t CALDONE:1; + uint32_t CALPASS:1; + } B; + } SYNSR; + + union FMPLL_ESYNCR1_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t CLKCFG:3; + uint32_t:8; + uint32_t EPREDIV:4; + uint32_t:8; + uint32_t EMFD:8; + } B; + } ESYNCR1; + + union FMPLL_ESYNCR2_tag { + uint32_t R; + struct { + uint32_t:8; + uint32_t LOCEN:1; + uint32_t LOLRE:1; + uint32_t LOCRE:1; + uint32_t LOLIRQ:1; + uint32_t LOCIRQ:1; + uint32_t:1; + uint32_t ERATE:2; + uint32_t:5; + uint32_t EDEPTH:3; + uint32_t:2; + uint32_t ERFD:6; + } B; + } ESYNCR2; + + }; +/****************************************************************************/ +/* MODULE : i2c */ +/****************************************************************************/ + struct I2C_tag { + union { + uint8_t R; + struct { + uint8_t AD:7; + uint8_t:1; + } B; + } IBAD; /* Module Bus Address Register */ + + union { + uint8_t R; + struct { + uint8_t MULT:2; + uint8_t ICR:6; + } B; + } IBFD; /* Module Bus Frequency Register */ + + union { + uint8_t R; + struct { + uint8_t MDIS:1; + uint8_t IBIE:1; + uint8_t MS:1; + uint8_t TX:1; + uint8_t NOACK:1; + uint8_t RSTA:1; + uint8_t DMAEN:1; + uint8_t:1; + } B; + } IBCR; /* Module Bus Control Register */ + + union { + uint8_t R; + struct { + uint8_t TCF:1; + uint8_t IAAS:1; + uint8_t IBB:1; + uint8_t IBAL:1; + uint8_t:1; + uint8_t SRW:1; + uint8_t IBIF:1; + uint8_t RXAK:1; + } B; + } IBSR; /* Module Status Register */ + + union { + uint8_t R; + struct { + uint8_t DATA:8; + } B; + } IBDR; /* Module Data Register */ + + union { + uint8_t R; + struct { + uint8_t BIIE:1; + uint8_t:7; + } B; + } IBIC; /* Module Interrupt Configuration Register */ + + }; +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + struct INTC_tag { + union { + uint32_t R; + struct { + uint32_t:18; + uint32_t VTES_PRC1:1; + uint32_t:4; + uint32_t HVEN_PRC1:1; + uint32_t:2; + uint32_t VTES:1; + uint32_t:4; + uint32_t HVEN:1; + } B; + } MCR; /* Module Configuration Register */ + + int32_t INTC_reserved1; + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR; /* Processor 0 Current Priority Register */ + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR_PRC1; /* Processor 1 Current Priority Register */ + + union { + uint32_t R; + struct { + uint32_t VTBA:21; + uint32_t INTVEC:9; + uint32_t:2; + } B; + } IACKR; /* Processor 0 Interrupt Acknowledge Register */ + + union { + uint32_t R; + struct { + uint32_t VTBA_PRC1:21; + uint32_t INTVEC_PRC1:9; + uint32_t:2; + } B; + } IACKR_PRC1; /* Processor 1 Interrupt Acknowledge Register */ + + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } EOIR; /* Processor 0 End of Interrupt Register */ + + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } EOIR_PRC1; /* Processor 1 End of Interrupt Register */ + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t SET:1; + uint8_t CLR:1; + } B; + } SSCIR[8]; /* Software Set/Clear Interruput Register */ + + uint32_t intc_reserved2[6]; + + union { + uint8_t R; + struct { + uint8_t PRC_SEL:2; + uint8_t:2; + uint8_t PRI:4; + } B; + } PSR[294]; /* Software Set/Clear Interrupt Register */ + + }; +/****************************************************************************/ +/* MODULE : MCM */ +/****************************************************************************/ + struct MCM_tag { + + uint32_t mcm_reserved1[5]; + + uint16_t mcm_reserved2; + + union { + uint16_t R; + struct { + uint16_t RO:1; + uint16_t:6; + uint16_t SWRWH:1; + uint16_t SWE:1; + uint16_t SWRI:2; + uint16_t SWT:5; + } B; + } SWTCR; /* Software Watchdog Timer Control */ + + uint8_t mcm_reserved3[3]; + + union { + uint8_t R; + } SWTSR; /* SWT Service Register */ + + uint8_t mcm_reserved4[3]; + + union { + uint8_t R; + struct { + uint8_t:7; + uint8_t SWTIC:1; + } B; + } SWTIR; /* SWT Interrupt Register */ + + uint32_t mcm_reserved5[1]; + + union { + uint32_t R; + struct { + uint32_t PRI:1; + uint32_t:31; + } B; + } MUDCR; /* Misc. User Defined Control Register */ + + uint32_t mcm_reserved6[6]; + uint8_t mcm_reserved7[3]; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t ERNCR:1; + uint8_t EFNCR:1; + } B; + } ECR; /* ECC Configuration Register */ + + uint8_t mcm_reserved8[3]; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t RNCE:1; + uint8_t FNCE:1; + } B; + } ESR; /* ECC Status Register */ + + uint16_t mcm_reserved9; + + union { + uint16_t R; + struct { + uint16_t:6; + uint16_t FRCNCI:1; + uint16_t FR1NCI:1; + uint16_t:1; + uint16_t ERRBIT:7; + } B; + } EEGR; /* ECC Error Generation Register */ + + uint32_t mcm_reserved10; + + union { + uint32_t R; + } FEAR; /* Flash ECC Address Register */ + + uint16_t mcm_reserved11; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t FEMR:4; + } B; + } FEMR; /* Flash ECC Master Register */ + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROTECTION:4; + } B; + } FEAT; /* Flash ECC Attributes Register */ + + union { + uint32_t R; + } FEDRH; /* Flash ECC Data High Register */ + + union { + uint32_t R; + } FEDRL; /* Flash ECC Data Low Register */ + + union { + uint32_t R; + struct { + uint32_t REAR:32; + } B; + } REAR; /* RAM ECC Address */ + + uint16_t mcm_reserved12; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t REMR:4; + } B; + } REMR; /* RAM ECC Master */ + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROTECTION:4; + } B; + } REAT; /* RAM ECC Attributes Register */ + + union { + uint32_t R; + } REDRH; /* RAM ECC Data High Register */ + + union { + uint32_t R; + } REDRL; /* RAMECC Data Low Register */ + + }; +/****************************************************************************/ +/* MODULE : MPU */ +/****************************************************************************/ + struct MPU_tag { + union { + uint32_t R; + struct { + uint32_t SPERR:8; + uint32_t:4; + uint32_t HRL:4; + uint32_t NSP:4; + uint32_t NGRD:4; + uint32_t:7; + uint32_t VLD:1; + } B; + } CESR; /* Module Control/Error Status Register */ + + uint32_t mpu_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR0; + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR0; + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR1; + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR1; + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR2; + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR2; + + uint32_t mpu_reserved2[246]; + + struct { + union { + uint32_t R; + struct { + uint32_t SRTADDR:27; + uint32_t:5; + } B; + } WORD0; /* Region Descriptor n Word 0 */ + + union { + uint32_t R; + struct { + uint32_t ENDADDR:27; + uint32_t:5; + } B; + } WORD1; /* Region Descriptor n Word 1 */ + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t M4RE0:1; + uint32_t M4WE:1; + uint32_t M3PE:1; + uint32_t M3SM:2; + uint32_t M3UM:3; + uint32_t M2PE:1; + uint32_t M2SM:2; + uint32_t M2UM:3; + uint32_t M1PE:1; + uint32_t M1SM:2; + uint32_t M1UM:3; + uint32_t M0PE:1; + uint32_t M0SM:2; + uint32_t M0UM:3; + } B; + } WORD2; /* Region Descriptor n Word 2 */ + + union { + uint32_t R; + struct { + uint32_t PID:8; + uint32_t PIDMASK:8; + uint32_t:15; + uint32_t VLD:1; + } B; + } WORD3; /* Region Descriptor n Word 3 */ + + } RGD[16]; + + uint32_t mpu_reserved3[192]; + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t M4RE:1; + uint32_t M4WE:1; + uint32_t M3PE:1; + uint32_t M3SM:2; + uint32_t M3UM:3; + uint32_t M2PE:1; + uint32_t M2SM:2; + uint32_t M2UM:3; + uint32_t M1PE:1; + uint32_t M1SM:2; + uint32_t M1UM:3; + uint32_t M0PE:1; + uint32_t M0SM:2; + uint32_t M0UM:3; + } B; + } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */ + }; +/****************************************************************************/ +/* MODULE : pit */ +/****************************************************************************/ + struct PIT_tag { + union { + uint32_t R; + struct { + uint32_t TSV:32; + } B; + } TLVAL[9]; + + uint32_t pit_reserved1[23]; + + union { + uint32_t R; + struct { + uint32_t TVL:32; + } B; + } TVAL[9]; + + uint32_t pit_reserved2[23]; + + union { + uint32_t R; + struct { + uint32_t:23; + uint32_t TIF8:1; + uint32_t TIF7:1; + uint32_t TIF6:1; + uint32_t TIF5:1; + uint32_t TIF4:1; + uint32_t TIF3:1; + uint32_t TIF2:1; + uint32_t TIF1:1; + uint32_t RTIF:1; + } B; + } PITFLG; + + union { + uint32_t R; + struct { + uint32_t:23; + uint32_t TIE8:1; + uint32_t TIE7:1; + uint32_t TIE6:1; + uint32_t TIE5:1; + uint32_t TIE4:1; + uint32_t TIE3:1; + uint32_t TIE2:1; + uint32_t TIE1:1; + uint32_t RTIE:1; + } B; + } PITINTEN; + + union { + uint32_t R; + struct { + uint32_t:23; + uint32_t ISEL8:1; + uint32_t ISEL7:1; + uint32_t ISEL6:1; + uint32_t ISEL5:1; + uint32_t ISEL4:1; + uint32_t ISEL3:1; + uint32_t ISEL2:1; + uint32_t ISEL1:1; + uint32_t:1; + } B; + } PITINTSEL; + + union { + uint32_t R; + struct { + uint32_t:23; + uint32_t PEN8:1; + uint32_t PEN7:1; + uint32_t PEN6:1; + uint32_t PEN5:1; + uint32_t PEN4:1; + uint32_t PEN3:1; + uint32_t PEN2:1; + uint32_t PEN1:1; + uint32_t PEN0:1; + } B; + } PITEN; + + union { + uint32_t R; + struct { + uint32_t:7; + uint32_t MDIS:1; + uint32_t:24; + } B; + } PITCTRL; + + }; +/****************************************************************************/ +/* MODULE : sem4 */ +/****************************************************************************/ + struct SEMA4_tag { + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t GTFSM:2; + } B; + } GATE[16]; /* Gate n Register */ + + uint32_t sema4_reserved1[12]; /* {0x40-0x10}/4 = 0x0C */ + + union { + uint16_t R; + struct { + uint16_t INE0:1; + uint16_t INE1:1; + uint16_t INE2:1; + uint16_t INE3:1; + uint16_t INE4:1; + uint16_t INE5:1; + uint16_t INE6:1; + uint16_t INE7:1; + uint16_t INE8:1; + uint16_t INE9:1; + uint16_t INE10:1; + uint16_t INE11:1; + uint16_t INE12:1; + uint16_t INE13:1; + uint16_t INE14:1; + uint16_t INE15:1; + } B; + } CP0INE; + + uint16_t sema4_reserved2[3]; /* {0x48-0x42}/2 = 0x03 */ + + union { + uint16_t R; + struct { + uint16_t INE0:1; + uint16_t INE1:1; + uint16_t INE2:1; + uint16_t INE3:1; + uint16_t INE4:1; + uint16_t INE5:1; + uint16_t INE6:1; + uint16_t INE7:1; + uint16_t INE8:1; + uint16_t INE9:1; + uint16_t INE10:1; + uint16_t INE11:1; + uint16_t INE12:1; + uint16_t INE13:1; + uint16_t INE14:1; + uint16_t INE15:1; + } B; + } CP1INE; + + uint16_t sema4_reserved3[27]; /* {0x80-0x4A}/2 = 0x1B */ + + union { + uint16_t R; + struct { + uint16_t GN0:1; + uint16_t GN1:1; + uint16_t GN2:1; + uint16_t GN3:1; + uint16_t GN4:1; + uint16_t GN5:1; + uint16_t GN6:1; + uint16_t GN7:1; + uint16_t GN8:1; + uint16_t GN9:1; + uint16_t GN10:1; + uint16_t GN11:1; + uint16_t GN12:1; + uint16_t GN13:1; + uint16_t GN14:1; + uint16_t GN15:1; + } B; + } CP0NTF; + + uint16_t sema4_reserved4[3]; /* {0x88-0x82}/2 = 0x03 */ + + union { + uint16_t R; + struct { + uint16_t GN0:1; + uint16_t GN1:1; + uint16_t GN2:1; + uint16_t GN3:1; + uint16_t GN4:1; + uint16_t GN5:1; + uint16_t GN6:1; + uint16_t GN7:1; + uint16_t GN8:1; + uint16_t GN9:1; + uint16_t GN10:1; + uint16_t GN11:1; + uint16_t GN12:1; + uint16_t GN13:1; + uint16_t GN14:1; + uint16_t GN15:1; + } B; + } CP1NTF; + + uint16_t sema4_reserved5[59]; /* {0x100-0x8A}/2 = 0x3B */ + + union { + uint16_t R; + struct { + uint16_t:2; + uint16_t RSTGSM:2; + uint16_t:1; + uint16_t RSTGMS:3; + uint16_t RSTGTN:8; + } B; + } RSTGT; + + uint16_t sema4_reserved6; + + union { + uint16_t R; + struct { + uint16_t:2; + uint16_t RSTNSM:2; + uint16_t:1; + uint16_t RSTNMS:3; + uint16_t RSTNTN:8; + } B; + } RSTNTF; + }; +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + + int32_t SIU_reserved0; + + union { /* MCU ID Register */ + uint32_t R; + struct { + uint32_t PARTNUM:16; + uint32_t CSP:1; + uint32_t PKG:5; + uint32_t:2; + uint32_t MASKNUM_MAJOR:4; + uint32_t MASKNUM_MINOR:4; + } B; + } MIDR; + + int32_t SIU_reserved1; + + union { /* Reset Status Register */ + uint32_t R; + struct { + uint32_t PORS:1; + uint32_t ERS:1; + uint32_t LLRS:1; + uint32_t LCRS:1; + uint32_t WDRS:1; + uint32_t CRS:1; + uint32_t:8; + uint32_t SSRS:1; + uint32_t:15; + uint32_t BOOTCFG:1; + uint32_t:1; + } B; + } RSR; + + union { /* System Reset Control Register */ + uint32_t R; + struct { + uint32_t SSR:1; + uint32_t:15; + uint32_t CRE0:1; + uint32_t CRE1:1; + uint32_t:6; + uint32_t SSRL:1; + uint32_t:7; + } B; + } SRCR; + + union SIU_EISR_tag { /* External Interrupt Status Register */ + uint32_t R; + struct { + uint32_t NMI0:1; + uint32_t NMI1:1; + uint32_t:14; + uint32_t EIF15:1; + uint32_t EIF14:1; + uint32_t EIF13:1; + uint32_t EIF12:1; + uint32_t EIF11:1; + uint32_t EIF10:1; + uint32_t EIF9:1; + uint32_t EIF8:1; + uint32_t EIF7:1; + uint32_t EIF6:1; + uint32_t EIF5:1; + uint32_t EIF4:1; + uint32_t EIF3:1; + uint32_t EIF2:1; + uint32_t EIF1:1; + uint32_t EIF0:1; + } B; + } EISR; + + union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t EIRE15:1; + uint32_t EIRE14:1; + uint32_t EIRE13:1; + uint32_t EIRE12:1; + uint32_t EIRE11:1; + uint32_t EIRE10:1; + uint32_t EIRE9:1; + uint32_t EIRE8:1; + uint32_t EIRE7:1; + uint32_t EIRE6:1; + uint32_t EIRE5:1; + uint32_t EIRE4:1; + uint32_t EIRE3:1; + uint32_t EIRE2:1; + uint32_t EIRE1:1; + uint32_t EIRE0:1; + } B; + } DIRER; + + union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */ + uint32_t R; + struct { + uint32_t:27; + uint32_t DIRS4:1; + uint32_t DIRS3:1; + uint32_t DIRS2:1; + uint32_t DIRS1:1; + uint32_t:1; + } B; + } DIRSR; + + union { /* Overrun Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t OVF15:1; + uint32_t OVF14:1; + uint32_t OVF13:1; + uint32_t OVF12:1; + uint32_t OVF11:1; + uint32_t OVF10:1; + uint32_t OVF9:1; + uint32_t OVF8:1; + uint32_t OVF7:1; + uint32_t OVF6:1; + uint32_t OVF5:1; + uint32_t OVF4:1; + uint32_t OVF3:1; + uint32_t OVF2:1; + uint32_t OVF1:1; + uint32_t OVF0:1; + } B; + } OSR; + + union SIU_ORER_tag { /* Overrun Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ORE15:1; + uint32_t ORE14:1; + uint32_t ORE13:1; + uint32_t ORE12:1; + uint32_t ORE11:1; + uint32_t ORE10:1; + uint32_t ORE9:1; + uint32_t ORE8:1; + uint32_t ORE7:1; + uint32_t ORE6:1; + uint32_t ORE5:1; + uint32_t ORE4:1; + uint32_t ORE3:1; + uint32_t ORE2:1; + uint32_t ORE1:1; + uint32_t ORE0:1; + } B; + } ORER; + + union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t NREE0:1; + uint32_t NREE1:1; + uint32_t:14; + uint32_t IREE15:1; + uint32_t IREE14:1; + uint32_t IREE13:1; + uint32_t IREE12:1; + uint32_t IREE11:1; + uint32_t IREE10:1; + uint32_t IREE9:1; + uint32_t IREE8:1; + uint32_t IREE7:1; + uint32_t IREE6:1; + uint32_t IREE5:1; + uint32_t IREE4:1; + uint32_t IREE3:1; + uint32_t IREE2:1; + uint32_t IREE1:1; + uint32_t IREE0:1; + } B; + } IREER; + + union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t NFEE0:1; + uint32_t NFEE1:1; + uint32_t:14; + uint32_t IFEE15:1; + uint32_t IFEE14:1; + uint32_t IFEE13:1; + uint32_t IFEE12:1; + uint32_t IFEE11:1; + uint32_t IFEE10:1; + uint32_t IFEE9:1; + uint32_t IFEE8:1; + uint32_t IFEE7:1; + uint32_t IFEE6:1; + uint32_t IFEE5:1; + uint32_t IFEE4:1; + uint32_t IFEE3:1; + uint32_t IFEE2:1; + uint32_t IFEE1:1; + uint32_t IFEE0:1; + } B; + } IFEER; + + union SIU_IDFR_tag { /* External IRQ Digital Filter Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } IDFR; + + union { /* External IRQ Filtered Input Register */ + uint32_t R; + struct { + uint32_t FNMI0:1; + uint32_t FNMI1:1; + uint32_t:14; + uint32_t FI15:1; + uint32_t FI14:1; + uint32_t FI13:1; + uint32_t FI12:1; + uint32_t FI11:1; + uint32_t FI10:1; + uint32_t FI9:1; + uint32_t FI8:1; + uint32_t FI7:1; + uint32_t FI6:1; + uint32_t FI5:1; + uint32_t FI4:1; + uint32_t FI3:1; + uint32_t FI2:1; + uint32_t FI1:1; + uint32_t FI0:1; + } B; + } IFIR; + + int32_t SIU_reserved2[2]; + + union SIU_PCR_tag { /* Pad Configuration Registers */ + uint16_t R; + struct { + uint16_t:4; + uint16_t PA:2; + uint16_t OBE:1; + uint16_t IBE:1; + uint16_t:2; + uint16_t ODE:1; + uint16_t HYS:1; + uint16_t SRC:2; + uint16_t WPE:1; + uint16_t WPS:1; + } B; + } PCR[146]; + + int32_t SIU_reserved3[295]; + + union { /* GPIO Pin Data Output Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDO:1; + } B; + } GPDO[146]; + + int32_t SIU_reserved4[91]; + + union { /* GPIO Pin Data Input Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; + } B; + } GPDI[146]; + + int32_t SIU_reserved5[27]; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t TSEL3:2; + uint32_t TSEL2:2; + uint32_t TSEL1:2; + uint32_t TSEL0:2; + uint32_t:24; + } B; + } ISEL0; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } ISEL1; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t SELEMIOS15:2; + uint32_t SELEMIOS14:2; + uint32_t SELEMIOS13:2; + uint32_t SELEMIOS12:2; + uint32_t SELEMIOS11:2; + uint32_t SELEMIOS10:2; + uint32_t SELEMIOS9:2; + uint32_t SELEMIOS8:2; + uint32_t SELEMIOS7:2; + uint32_t SELEMIOS6:2; + uint32_t SELEMIOS5:2; + uint32_t SELEMIOS4:2; + uint32_t SELEMIOS3:2; + uint32_t SELEMIOS2:2; + uint32_t SELEMIOS1:2; + uint32_t SELEMIOS0:2; + } B; + } ISEL2; + + int32_t SIU_reserved6[29]; + + union { /* Chip Configuration Register Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MATCH:1; + uint32_t DISNEX:1; + uint32_t:16; + } B; + } CCR; + + union { /* External Clock Configuration Register Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t EBDF:2; + } B; + } ECCR; + + union { /* Compare A High Register */ + uint32_t R; + } CMPAH; + + union { /* Compare A Low Register */ + uint32_t R; + } CMPAL; + + union { /* Compare B High Register */ + uint32_t R; + } CMPBH; + + union { /* Compare B Low Register */ + uint32_t R; + } CMPBL; + + int32_t SIU_reserved7[2]; + + union { /* System CLock Register */ + uint32_t R; + struct { + uint32_t SYSCLKSEL:2; + uint32_t SYSCLKDIV:2; + uint32_t SWTCLKSEL:1; + uint32_t:11; + uint32_t LPCLKDIV7:2; + uint32_t LPCLKDIV6:2; + uint32_t LPCLKDIV5:2; + uint32_t LPCLKDIV4:2; + uint32_t LPCLKDIV3:2; + uint32_t LPCLKDIV2:2; + uint32_t LPCLKDIV1:2; + uint32_t LPCLKDIV0:2; + } B; + } SYSCLK; + + union { /* Halt Register */ + uint32_t R; + } HLT; + + union { /* Halt Acknowledge Register */ + uint32_t R; + } HLTACK; + + int32_t SIU_reserved8[149]; + + union { /* Parallel GPIO Pin Data Output Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t PB:16; + } B; + } PGPDO0; + + union { /* Parallel GPIO Pin Data Output Register */ + uint32_t R; + struct { + uint32_t PC:16; + uint32_t PD:16; + } B; + } PGPDO1; + + union { /* Parallel GPIO Pin Data Output Register */ + uint32_t R; + struct { + uint32_t PE:16; + uint32_t PF:16; + } B; + } PGPDO2; + + union { /* Parallel GPIO Pin Data Output Register */ + uint32_t R; + struct { + uint32_t PG:16; + uint32_t PH:16; + } B; + } PGPDO3; + + union { /* Parallel GPIO Pin Data Output Register */ + uint32_t R; + struct { + uint32_t PJ:16; + uint32_t:16; + } B; + } PGPDO4; + + int32_t SIU_reserved9[11]; + + union { /* Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PA:16; + uint32_t PB:16; + } B; + } PGPDI0; + + union { /* Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PC:16; + uint32_t PD:16; + } B; + } PGPDI1; + + union { /* Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PE:16; + uint32_t PF:16; + } B; + } PGPDI2; + + union { /* Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PG:16; + uint32_t PH:16; + } B; + } PGPDI3; + + union { /* Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PJ:16; + uint32_t PK:2; + uint32_t:14; + } B; + } PGPDI4; + + int32_t SIU_reserved10[12]; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PB_MASK:16; + uint32_t PB:16; + } B; + } MPGPDO1; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PC_MASK:16; + uint32_t PC:16; + } B; + } MPGPDO2; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PD_MASK:16; + uint32_t PD:16; + } B; + } MPGPDO3; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PE_MASK:16; + uint32_t PE:16; + } B; + } MPGPDO4; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PF_MASK:16; + uint32_t PF:16; + } B; + } MPGPDO5; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PG_MASK:16; + uint32_t PG:16; + } B; + } MPGPDO6; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PH_MASK:16; + uint32_t PH:16; + } B; + } MPGPDO7; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PJ_MASK:16; + uint32_t PJ:16; + } B; + } MPGPDO8; + + }; +/****************************************************************************/ +/* MODULE : FlexRay */ +/****************************************************************************/ + + typedef union uMVR { + uint16_t R; + struct { + uint16_t CHIVER:8; /* CHI Version Number */ + uint16_t PEVER:8; /* PE Version Number */ + } B; + } MVR_t; + + typedef union uMCR { + uint16_t R; + struct { + uint16_t MEN:1; /* module enable */ + uint16_t:1; + uint16_t SCMD:1; /* single channel mode */ + uint16_t CHB:1; /* channel B enable */ + uint16_t CHA:1; /* channel A enable */ + uint16_t SFFE:1; /* synchronization frame filter enable */ + uint16_t:5; + uint16_t CLKSEL:1; /* protocol engine clock source select */ + uint16_t PRESCALE:3; /* protocol engine clock prescaler */ + uint16_t:1; + } B; + } MCR_t; + typedef union uSTBSCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t STBSSEL:7; /* strobe signal select */ + uint16_t:3; + uint16_t ENB:1; /* strobe signal enable */ + uint16_t:2; + uint16_t STBPSEL:2; /* strobe port select */ + } B; + } STBSCR_t; + typedef union uMBDSR { + uint16_t R; + struct { + uint16_t:1; + uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ + uint16_t:1; + uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ + } B; + } MBDSR_t; + + typedef union uMBSSUTR { + uint16_t R; + struct { + + uint16_t:2; + uint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */ + uint16_t:2; + uint16_t LAST_MB_UTIL:6; /* last message buffer utilized */ + } B; + } MBSSUTR_t; + + typedef union uPOCR { + uint16_t R; + uint8_t byte[2]; + struct { + uint16_t WME:1; /* write mode external correction command */ + uint16_t:3; + uint16_t EOC_AP:2; /* external offset correction application */ + uint16_t ERC_AP:2; /* external rate correction application */ + uint16_t BSY:1; /* command write busy / write mode command */ + uint16_t:3; + uint16_t POCCMD:4; /* protocol command */ + } B; + } POCR_t; +/* protocol commands */ + typedef union uGIFER { + uint16_t R; + struct { + uint16_t MIF:1; /* module interrupt flag */ + uint16_t PRIF:1; /* protocol interrupt flag */ + uint16_t CHIF:1; /* CHI interrupt flag */ + uint16_t WKUPIF:1; /* wakeup interrupt flag */ + uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ + uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ + uint16_t RBIF:1; /* receive message buffer interrupt flag */ + uint16_t TBIF:1; /* transmit buffer interrupt flag */ + uint16_t MIE:1; /* module interrupt enable */ + uint16_t PRIE:1; /* protocol interrupt enable */ + uint16_t CHIE:1; /* CHI interrupt enable */ + uint16_t WKUPIE:1; /* wakeup interrupt enable */ + uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ + uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ + uint16_t RBIE:1; /* receive message buffer interrupt enable */ + uint16_t TBIE:1; /* transmit buffer interrupt enable */ + } B; + } GIFER_t; + typedef union uPIFR0 { + uint16_t R; + struct { + uint16_t FATLIF:1; /* fatal protocol error interrupt flag */ + uint16_t INTLIF:1; /* internal protocol error interrupt flag */ + uint16_t ILCFIF:1; /* illegal protocol configuration flag */ + uint16_t CSAIF:1; /* cold start abort interrupt flag */ + uint16_t MRCIF:1; /* missing rate correctio interrupt flag */ + uint16_t MOCIF:1; /* missing offset correctio interrupt flag */ + uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ + uint16_t MXSIF:1; /* max sync frames detected interrupt flag */ + uint16_t MTXIF:1; /* media access test symbol received flag */ + uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ + uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ + uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ + uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ + uint16_t TI2IF:1; /* timer 2 expired interrupt flag */ + uint16_t TI1IF:1; /* timer 1 expired interrupt flag */ + uint16_t CYSIF:1; /* cycle start interrupt flag */ + } B; + } PIFR0_t; + typedef union uPIFR1 { + uint16_t R; + struct { + uint16_t EMCIF:1; /* error mode changed interrupt flag */ + uint16_t IPCIF:1; /* illegal protocol command interrupt flag */ + uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ + uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ + uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ + uint16_t:2; + uint16_t EVTIF:1; /* even cycle table written interrupt flag */ + uint16_t ODTIF:1; /* odd cycle table written interrupt flag */ + uint16_t:4; + } B; + } PIFR1_t; + typedef union uPIER0 { + uint16_t R; + struct { + uint16_t FATLIE:1; /* fatal protocol error interrupt enable */ + uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ + uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ + uint16_t CSAIE:1; /* cold start abort interrupt enable */ + uint16_t MRCIE:1; /* missing rate correctio interrupt enable */ + uint16_t MOCIE:1; /* missing offset correctio interrupt enable */ + uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ + uint16_t MXSIE:1; /* max sync frames detected interrupt enable */ + uint16_t MTXIE:1; /* media access test symbol received interrupt enable */ + uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ + uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ + uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ + uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ + uint16_t TI2IE:1; /* timer 2 expired interrupt enable */ + uint16_t TI1IE:1; /* timer 1 expired interrupt enable */ + uint16_t CYSIE:1; /* cycle start interrupt enable */ + } B; + } PIER0_t; + typedef union uPIER1 { + uint16_t R; + struct { + uint16_t EMCIE:1; /* error mode changed interrupt enable */ + uint16_t IPCIE:1; /* illegal protocol command interrupt enable */ + uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ + uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ + uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ + uint16_t:2; + uint16_t EVTIE:1; /* even cycle table written interrupt enable */ + uint16_t ODTIE:1; /* odd cycle table written interrupt enable */ + uint16_t:4; + } B; + } PIER1_t; + typedef union uCHIERFR { + uint16_t R; + struct { + uint16_t FRLBEF:1; /* flame lost channel B error flag */ + uint16_t FRLAEF:1; /* frame lost channel A error flag */ + uint16_t PCMIEF:1; /* command ignored error flag */ + uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ + uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ + uint16_t MSBEF:1; /* message buffer search error flag */ + uint16_t MBUEF:1; /* message buffer utilization error flag */ + uint16_t LCKEF:1; /* lock error flag */ + uint16_t DBLEF:1; /* double transmit message buffer lock error flag */ + uint16_t SBCFEF:1; /* system bus communication failure error flag */ + uint16_t FIDEF:1; /* frame ID error flag */ + uint16_t DPLEF:1; /* dynamic payload length error flag */ + uint16_t SPLEF:1; /* static payload length error flag */ + uint16_t NMLEF:1; /* network management length error flag */ + uint16_t NMFEF:1; /* network management frame error flag */ + uint16_t ILSAEF:1; /* illegal access error flag */ + } B; + } CHIERFR_t; + typedef union uMBIVEC { + uint16_t R; + struct { + + uint16_t:2; + uint16_t TBIVEC:6; /* transmit buffer interrupt vector */ + uint16_t:2; + uint16_t RBIVEC:6; /* receive buffer interrupt vector */ + } B; + } MBIVEC_t; + + typedef union uPSR0 { + uint16_t R; + struct { + uint16_t ERRMODE:2; /* error mode */ + uint16_t SLOTMODE:2; /* slot mode */ + uint16_t:1; + uint16_t PROTSTATE:3; /* protocol state */ + uint16_t SUBSTATE:4; /* protocol sub state */ + uint16_t:1; + uint16_t WAKEUPSTATUS:3; /* wakeup status */ + } B; + } PSR0_t; + +/* protocol states */ +/* protocol sub-states */ +/* wakeup status */ + typedef union uPSR1 { + uint16_t R; + struct { + uint16_t CSAA:1; /* cold start attempt abort flag */ + uint16_t SCP:1; /* cold start path */ + uint16_t:1; + uint16_t REMCSAT:5; /* remanining coldstart attempts */ + uint16_t CPN:1; /* cold start noise path */ + uint16_t HHR:1; /* host halt request pending */ + uint16_t FRZ:1; /* freeze occured */ + uint16_t APTAC:5; /* allow passive to active counter */ + } B; + } PSR1_t; + typedef union uPSR2 { + uint16_t R; + struct { + uint16_t NBVB:1; /* NIT boundary violation on channel B */ + uint16_t NSEB:1; /* NIT syntax error on channel B */ + uint16_t STCB:1; /* symbol window transmit conflict on channel B */ + uint16_t SBVB:1; /* symbol window boundary violation on channel B */ + uint16_t SSEB:1; /* symbol window syntax error on channel B */ + uint16_t MTB:1; /* media access test symbol MTS received on channel B */ + uint16_t NBVA:1; /* NIT boundary violation on channel A */ + uint16_t NSEA:1; /* NIT syntax error on channel A */ + uint16_t STCA:1; /* symbol window transmit conflict on channel A */ + uint16_t SBVA:1; /* symbol window boundary violation on channel A */ + uint16_t SSEA:1; /* symbol window syntax error on channel A */ + uint16_t MTA:1; /* media access test symbol MTS received on channel A */ + uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ + } B; + } PSR2_t; + typedef union uPSR3 { + uint16_t R; + struct { + uint16_t:2; + uint16_t WUB:1; /* wakeup symbol received on channel B */ + uint16_t ABVB:1; /* aggregated boundary violation on channel B */ + uint16_t AACB:1; /* aggregated additional communication on channel B */ + uint16_t ACEB:1; /* aggregated content error on channel B */ + uint16_t ASEB:1; /* aggregated syntax error on channel B */ + uint16_t AVFB:1; /* aggregated valid frame on channel B */ + uint16_t:2; + uint16_t WUA:1; /* wakeup symbol received on channel A */ + uint16_t ABVA:1; /* aggregated boundary violation on channel A */ + uint16_t AACA:1; /* aggregated additional communication on channel A */ + uint16_t ACEA:1; /* aggregated content error on channel A */ + uint16_t ASEA:1; /* aggregated syntax error on channel A */ + uint16_t AVFA:1; /* aggregated valid frame on channel A */ + } B; + } PSR3_t; + typedef union uCIFRR { + uint16_t R; + struct { + uint16_t:8; + uint16_t MIFR:1; /* module interrupt flag */ + uint16_t PRIFR:1; /* protocol interrupt flag */ + uint16_t CHIFR:1; /* CHI interrupt flag */ + uint16_t WUPIFR:1; /* wakeup interrupt flag */ + uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ + uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ + uint16_t RBIFR:1; /* receive message buffer interrupt flag */ + uint16_t TBIFR:1; /* transmit buffer interrupt flag */ + } B; + } CIFRR_t; + typedef union uSYMATOR { + uint16_t R; + struct { + uint16_t:11; + uint16_t TIMEOUT:5; /* system memory time out value */ + } B; + } SYMATOR_t; + + typedef union uSFCNTR { + uint16_t R; + struct { + uint16_t SFEVB:4; /* sync frames channel B, even cycle */ + uint16_t SFEVA:4; /* sync frames channel A, even cycle */ + uint16_t SFODB:4; /* sync frames channel B, odd cycle */ + uint16_t SFODA:4; /* sync frames channel A, odd cycle */ + } B; + } SFCNTR_t; + + typedef union uSFTCCSR { + uint16_t R; + struct { + uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ + uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ + uint16_t CYCNUM:6; /* cycle number */ + uint16_t ELKS:1; /* even cycle tables lock status */ + uint16_t OLKS:1; /* odd cycle tables lock status */ + uint16_t EVAL:1; /* even cycle tables valid */ + uint16_t OVAL:1; /* odd cycle tables valid */ + uint16_t:1; + uint16_t OPT:1; /*one pair trigger */ + uint16_t SDVEN:1; /* sync frame deviation table enable */ + uint16_t SIDEN:1; /* sync frame ID table enable */ + } B; + } SFTCCSR_t; + typedef union uSFIDRFR { + uint16_t R; + struct { + uint16_t:6; + uint16_t SYNFRID:10; /* sync frame rejection ID */ + } B; + } SFIDRFR_t; + + typedef union uTICCR { + uint16_t R; + struct { + uint16_t:2; + uint16_t T2CFG:1; /* timer 2 configuration */ + uint16_t T2REP:1; /* timer 2 repetitive mode */ + uint16_t:1; + uint16_t T2SP:1; /* timer 2 stop */ + uint16_t T2TR:1; /* timer 2 trigger */ + uint16_t T2ST:1; /* timer 2 state */ + uint16_t:3; + uint16_t T1REP:1; /* timer 1 repetitive mode */ + uint16_t:1; + uint16_t T1SP:1; /* timer 1 stop */ + uint16_t T1TR:1; /* timer 1 trigger */ + uint16_t T1ST:1; /* timer 1 state */ + + } B; + } TICCR_t; + typedef union uTI1CYSR { + uint16_t R; + struct { + uint16_t:2; + uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ + uint16_t:2; + uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ + + } B; + } TI1CYSR_t; + + typedef union uSSSR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* static slot number */ + uint16_t:1; + uint16_t SLOTNUMBER:11; /* selector */ + } B; + } SSSR_t; + + typedef union uSSCCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:1; + uint16_t CNTCFG:2; /* counter configuration */ + uint16_t MCY:1; /* multi cycle selection */ + uint16_t VFR:1; /* valid frame selection */ + uint16_t SYF:1; /* sync frame selection */ + uint16_t NUF:1; /* null frame selection */ + uint16_t SUF:1; /* startup frame selection */ + uint16_t STATUSMASK:4; /* slot status mask */ + } B; + } SSCCR_t; + typedef union uSSR { + uint16_t R; + struct { + uint16_t VFB:1; /* valid frame on channel B */ + uint16_t SYB:1; /* valid sync frame on channel B */ + uint16_t NFB:1; /* valid null frame on channel B */ + uint16_t SUB:1; /* valid startup frame on channel B */ + uint16_t SEB:1; /* syntax error on channel B */ + uint16_t CEB:1; /* content error on channel B */ + uint16_t BVB:1; /* boundary violation on channel B */ + uint16_t TCB:1; /* tx conflict on channel B */ + uint16_t VFA:1; /* valid frame on channel A */ + uint16_t SYA:1; /* valid sync frame on channel A */ + uint16_t NFA:1; /* valid null frame on channel A */ + uint16_t SUA:1; /* valid startup frame on channel A */ + uint16_t SEA:1; /* syntax error on channel A */ + uint16_t CEA:1; /* content error on channel A */ + uint16_t BVA:1; /* boundary violation on channel A */ + uint16_t TCA:1; /* tx conflict on channel A */ + } B; + } SSR_t; + typedef union uMTSCFR { + uint16_t R; + struct { + uint16_t MTE:1; /* media access test symbol transmission enable */ + uint16_t:1; + uint16_t CYCCNTMSK:6; /* cycle counter mask */ + uint16_t:2; + uint16_t CYCCNTVAL:6; /* cycle counter value */ + } B; + } MTSCFR_t; + + typedef union uRSBIR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:5; + uint16_t RSBIDX:7; /* receive shadow buffer index */ + } B; + } RSBIR_t; + + typedef union uRFDSR { + uint16_t R; + struct { + uint16_t FIFODEPTH:8; /* fifo depth */ + uint16_t:1; + uint16_t ENTRYSIZE:7; /* entry size */ + } B; + } RFDSR_t; + + typedef union uRFRFCFR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t IBD:1; /* interval boundary */ + uint16_t SEL:2; /* filter number */ + uint16_t:1; + uint16_t SID:11; /* slot ID */ + } B; + } RFRFCFR_t; + + typedef union uRFRFCTR { + uint16_t R; + struct { + uint16_t:4; + uint16_t F3MD:1; /* filter mode */ + uint16_t F2MD:1; /* filter mode */ + uint16_t F1MD:1; /* filter mode */ + uint16_t F0MD:1; /* filter mode */ + uint16_t:4; + uint16_t F3EN:1; /* filter enable */ + uint16_t F2EN:1; /* filter enable */ + uint16_t F1EN:1; /* filter enable */ + uint16_t F0EN:1; /* filter enable */ + } B; + } RFRFCTR_t; + typedef union uPCR0 { + uint16_t R; + struct { + uint16_t ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_LENGTH:10; + } B; + } PCR0_t; + + typedef union uPCR1 { + uint16_t R; + struct { + uint16_t:2; + uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; + } B; + } PCR1_t; + + typedef union uPCR2 { + uint16_t R; + struct { + uint16_t MINISLOT_AFTER_ACTION_POINT:6; + uint16_t NUMBER_OF_STATIC_SLOTS:10; + } B; + } PCR2_t; + + typedef union uPCR3 { + uint16_t R; + struct { + uint16_t WAKEUP_SYMBOL_RX_LOW:6; + uint16_t MINISLOT_ACTION_POINT_OFFSET:5; + uint16_t COLDSTART_ATTEMPTS:5; + } B; + } PCR3_t; + + typedef union uPCR4 { + uint16_t R; + struct { + uint16_t CAS_RX_LOW_MAX:7; + uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; + } B; + } PCR4_t; + + typedef union uPCR5 { + uint16_t R; + struct { + uint16_t TSS_TRANSMITTER:4; + uint16_t WAKEUP_SYMBOL_TX_LOW:6; + uint16_t WAKEUP_SYMBOL_RX_IDLE:6; + } B; + } PCR5_t; + + typedef union uPCR6 { + uint16_t R; + struct { + uint16_t:1; + uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; + uint16_t MACRO_INITIAL_OFFSET_A:7; + } B; + } PCR6_t; + + typedef union uPCR7 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_B:9; + uint16_t MICRO_PER_MACRO_NOM_HALF:7; + } B; + } PCR7_t; + + typedef union uPCR8 { + uint16_t R; + struct { + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; + uint16_t WAKEUP_SYMBOL_TX_IDLE:8; + } B; + } PCR8_t; + + typedef union uPCR9 { + uint16_t R; + struct { + uint16_t MINISLOT_EXISTS:1; + uint16_t SYMBOL_WINDOW_EXISTS:1; + uint16_t OFFSET_CORRECTION_OUT:14; + } B; + } PCR9_t; + + typedef union uPCR10 { + uint16_t R; + struct { + uint16_t SINGLE_SLOT_ENABLED:1; + uint16_t WAKEUP_CHANNEL:1; + uint16_t MACRO_PER_CYCLE:14; + } B; + } PCR10_t; + + typedef union uPCR11 { + uint16_t R; + struct { + uint16_t KEY_SLOT_USED_FOR_STARTUP:1; + uint16_t KEY_SLOT_USED_FOR_SYNC:1; + uint16_t OFFSET_CORRECTION_START:14; + } B; + } PCR11_t; + + typedef union uPCR12 { + uint16_t R; + struct { + uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; + uint16_t KEY_SLOT_HEADER_CRC:11; + } B; + } PCR12_t; + + typedef union uPCR13 { + uint16_t R; + struct { + uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; + } B; + } PCR13_t; + + typedef union uPCR14 { + uint16_t R; + struct { + uint16_t RATE_CORRECTION_OUT:11; + uint16_t LISTEN_TIMEOUT_H:5; + } B; + } PCR14_t; + + typedef union uPCR15 { + uint16_t R; + struct { + uint16_t LISTEN_TIMEOUT_L:16; + } B; + } PCR15_t; + + typedef union uPCR16 { + uint16_t R; + struct { + uint16_t MACRO_INITIAL_OFFSET_B:7; + uint16_t NOISE_LISTEN_TIMEOUT_H:9; + } B; + } PCR16_t; + + typedef union uPCR17 { + uint16_t R; + struct { + uint16_t NOISE_LISTEN_TIMEOUT_L:16; + } B; + } PCR17_t; + + typedef union uPCR18 { + uint16_t R; + struct { + uint16_t WAKEUP_PATTERN:6; + uint16_t KEY_SLOT_ID:10; + } B; + } PCR18_t; + + typedef union uPCR19 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_A:9; + uint16_t PAYLOAD_LENGTH_STATIC:7; + } B; + } PCR19_t; + + typedef union uPCR20 { + uint16_t R; + struct { + uint16_t MICRO_INITIAL_OFFSET_B:8; + uint16_t MICRO_INITIAL_OFFSET_A:8; + } B; + } PCR20_t; + + typedef union uPCR21 { + uint16_t R; + struct { + uint16_t EXTERN_RATE_CORRECTION:3; + uint16_t LATEST_TX:13; + } B; + } PCR21_t; + + typedef union uPCR22 { + uint16_t R; + struct { + uint16_t:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; + uint16_t MICRO_PER_CYCLE_H:4; + } B; + } PCR22_t; + + typedef union uPCR23 { + uint16_t R; + struct { + uint16_t micro_per_cycle_l:16; + } B; + } PCR23_t; + + typedef union uPCR24 { + uint16_t R; + struct { + uint16_t CLUSTER_DRIFT_DAMPING:5; + uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; + uint16_t MICRO_PER_CYCLE_MIN_H:4; + } B; + } PCR24_t; + + typedef union uPCR25 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MIN_L:16; + } B; + } PCR25_t; + + typedef union uPCR26 { + uint16_t R; + struct { + uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; + uint16_t MICRO_PER_CYCLE_MAX_H:4; + } B; + } PCR26_t; + + typedef union uPCR27 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MAX_L:16; + } B; + } PCR27_t; + + typedef union uPCR28 { + uint16_t R; + struct { + uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; + uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; + } B; + } PCR28_t; + + typedef union uPCR29 { + uint16_t R; + struct { + uint16_t EXTERN_OFFSET_CORRECTION:3; + uint16_t MINISLOTS_MAX:13; + } B; + } PCR29_t; + + typedef union uPCR30 { + uint16_t R; + struct { + uint16_t:12; + uint16_t SYNC_NODE_MAX:4; + } B; + } PCR30_t; + + typedef struct uMSG_BUFF_CCS { + union { + uint16_t R; + struct { + uint16_t:1; + uint16_t MCM:1; /* message buffer commit mode */ + uint16_t MBT:1; /* message buffer type */ + uint16_t MTD:1; /* message buffer direction */ + uint16_t CMT:1; /* commit for transmission */ + uint16_t EDT:1; /* enable / disable trigger */ + uint16_t LCKT:1; /* lock request trigger */ + uint16_t MBIE:1; /* message buffer interrupt enable */ + uint16_t:3; + uint16_t DUP:1; /* data updated */ + uint16_t DVAL:1; /* data valid */ + uint16_t EDS:1; /* lock status */ + uint16_t LCKS:1; /* enable / disable status */ + uint16_t MBIF:1; /* message buffer interrupt flag */ + } B; + } MBCCSR; + union { + uint16_t R; + struct { + uint16_t MTM:1; /* message buffer transmission mode */ + uint16_t CHNLA:1; /* channel assignement */ + uint16_t CHNLB:1; /* channel assignement */ + uint16_t CCFE:1; /* cycle counter filter enable */ + uint16_t CCFMSK:6; /* cycle counter filter mask */ + uint16_t CCFVAL:6; /* cycle counter filter value */ + } B; + } MBCCFR; + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t FID:11; /* frame ID */ + } B; + } MBFIDR; + + union { + uint16_t R; + struct { + uint16_t:9; + uint16_t MBIDX:7; /* message buffer index */ + } B; + } MBIDXR; + } MSG_BUFF_CCS_t; + typedef union uSYSBADHR { + uint16_t R; + } SYSBADHR_t; + typedef union uSYSBADLR { + uint16_t R; + } SYSBADLR_t; + typedef union uPADR { + uint16_t R; + } PADR_t; + typedef union uPDAR { + uint16_t R; + } PDAR_t; + typedef union uCASERCR { + uint16_t R; + } CASERCR_t; + typedef union uCBSERCR { + uint16_t R; + } CBSERCR_t; + typedef union uCYCTR { + uint16_t R; + } CYCTR_t; + typedef union uMTCTR { + uint16_t R; + } MTCTR_t; + typedef union uSLTCTAR { + uint16_t R; + } SLTCTAR_t; + typedef union uSLTCTBR { + uint16_t R; + } SLTCTBR_t; + typedef union uRTCORVR { + uint16_t R; + } RTCORVR_t; + typedef union uOFCORVR { + uint16_t R; + } OFCORVR_t; + typedef union uSFTOR { + uint16_t R; + } SFTOR_t; + typedef union uSFIDAFVR { + uint16_t R; + } SFIDAFVR_t; + typedef union uSFIDAFMR { + uint16_t R; + } SFIDAFMR_t; + typedef union uNMVR { + uint16_t R; + } NMVR_t; + typedef union uNMVLR { + uint16_t R; + } NMVLR_t; + typedef union uT1MTOR { + uint16_t R; + } T1MTOR_t; + typedef union uTI2CR0 { + uint16_t R; + } TI2CR0_t; + typedef union uTI2CR1 { + uint16_t R; + } TI2CR1_t; + typedef union uSSCR { + uint16_t R; + } SSCR_t; + typedef union uRFSR { + uint16_t R; + } RFSR_t; + typedef union uRFSIR { + uint16_t R; + } RFSIR_t; + typedef union uRFARIR { + uint16_t R; + } RFARIR_t; + typedef union uRFBRIR { + uint16_t R; + } RFBRIR_t; + typedef union uRFMIDAFVR { + uint16_t R; + } RFMIDAFVR_t; + typedef union uRFMIAFMR { + uint16_t R; + } RFMIAFMR_t; + typedef union uRFFIDRFVR { + uint16_t R; + } RFFIDRFVR_t; + typedef union uRFFIDRFMR { + uint16_t R; + } RFFIDRFMR_t; + typedef union uLDTXSLAR { + uint16_t R; + } LDTXSLAR_t; + typedef union uLDTXSLBR { + uint16_t R; + } LDTXSLBR_t; + + typedef struct FR_tag { + volatile MVR_t MVR; /*module version register *//*0 */ + volatile MCR_t MCR; /*module configuration register *//*2 */ + volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ + volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ + volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ + uint16_t reserved0[1]; /*A */ + volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ + volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ + uint16_t reserved1[1]; /*10 */ + uint16_t reserved2[1]; /*12 */ + volatile POCR_t POCR; /*Protocol operation control register *//*14 */ + volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ + volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ + volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ + volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ + volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ + volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ + volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ + volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ + volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ + volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ + volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ + volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ + volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ + volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ + volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ + volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ + volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ + volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ + volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ + volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ + volatile SYMATOR_t SYMATOR; /*system memory acess time-out register *//*3E */ + volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ + volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ + volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ + volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ + volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ + volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ + volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ + volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ + volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ + volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ + volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ + volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ + volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ + volatile SSSR_t SSSR; /*slot status selection register *//*64 */ + volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ + volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ + volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ + volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ + volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ + volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ + volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ + volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ + volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ + volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ + volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ + volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ + volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ + volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ + volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ + volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ + volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ + volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ + volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ + volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ + volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ + volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ + volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ + volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ + volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ + volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ + volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ + volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ + volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ + volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ + volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ + volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ + volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ + volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ + volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ + volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ + volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ + volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ + volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ + volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ + volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ + volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ + volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ + volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ + volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ + volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ + volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ + volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ + volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ + volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ + uint16_t reserved3[17]; + volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ + } FR_tag_t; + + typedef union uF_HEADER /* frame header */ + { + struct { + uint16_t:5; + uint16_t HDCRC:11; /* Header CRC */ + uint16_t:2; + uint16_t CYCCNT:6; /* Cycle Count */ + uint16_t:1; + uint16_t PLDLEN:7; /* Payload Length */ + uint16_t:1; + uint16_t PPI:1; /* Payload Preamble Indicator */ + uint16_t NUF:1; /* Null Frame Indicator */ + uint16_t SYF:1; /* Sync Frame Indicator */ + uint16_t SUF:1; /* Startup Frame Indicator */ + uint16_t FID:11; /* Frame ID */ + } B; + uint16_t WORDS[3]; + } F_HEADER_t; + typedef union uS_STSTUS /* slot status */ + { + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t CH:1; /* Channel */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t:1; + } RX; + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t TCB:1; /* Tx Conflict on channel B */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t TCA:1; /* Tx Conflict on channel A */ + } TX; + uint16_t R; + } S_STATUS_t; + + typedef struct uMB_HEADER /* message buffer header */ + { + F_HEADER_t FRAME_HEADER; + uint16_t DATA_OFFSET; + S_STATUS_t SLOT_STATUS; + } MB_HEADER_t; +/****************************************************************************/ +/* MODULE : MLB */ +/****************************************************************************/ + struct MLB_tag { + + union { /* MLB Module Configuration Register */ + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t:15; + uint32_t MDATOBSE:1; + uint32_t MSIGOBS:1; + uint32_t MSLOTE:1; + uint32_t:2; + uint32_t MSVRQIE:1; + uint32_t MDATRQE:1; + uint32_t:2; + uint32_t MSVRQDL:3; + uint32_t MSVRQCIE:1; + uint32_t MIFSEL:1; + uint32_t MSBFEPOL:1; + uint32_t MDBFEPOL:1; + } B; + } MCR; + + union { /* MLB Blank Register */ + uint32_t R; + struct { + uint32_t:31; + uint32_t BLANK:1; + } B; + } MBR; + + union { /* MLB Status Register */ + uint32_t R; + struct { + uint32_t:29; + uint32_t MDATRQS:1; + uint32_t MSYSS:1; + uint32_t MSVRQS:1; + } B; + } MSR; + + union { /* RX Control Channel Address Register */ + uint32_t R; + struct { + uint32_t RXCCHA_ACEN:1; + uint32_t:25; + uint32_t RXCCHA:5; + uint32_t:1; + } B; + } RXCCHAR; + + union { /* RX Async Channel Address Register */ + uint32_t R; + struct { + uint32_t RXACHA_ACEN:1; + uint32_t:25; + uint32_t RXACHA:5; + uint32_t:1; + } B; + } RXACHAR; + + union { /* TX Control Channel Address Register */ + uint32_t R; + struct { + uint32_t TXCCHA_ACEN:1; + uint32_t:25; + uint32_t TXCCHA:5; + uint32_t:1; + } B; + } TXCCHAR; + + union { /* TX Async Channel Address Register */ + uint32_t R; + struct { + uint32_t TXACHA_ACEN:1; + uint32_t:25; + uint32_t TXACHA:5; + uint32_t:1; + } B; + } TXACHAR; + + union { /* TX Sync Channel Address Register */ + uint32_t R; + struct { + uint32_t TXSCHA_ACEN:1; + uint32_t:25; + uint32_t TXSCHA:5; + uint32_t:1; + } B; + } TXSCHAR; + + union { /* TX Sync Channel Address Mask Register */ + uint32_t R; + struct { + uint32_t:26; + uint32_t TXSCHAM:5; + uint32_t:1; + } B; + } TXSCHAMR; + + union { /* Clock Adjust Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t PDLY:16; + } B; + } CLKACR; + + union { /* RX Isochronous Channel Address Register */ + uint32_t R; + struct { + uint32_t RXICHA_ACEN:1; + uint32_t:25; + uint32_t RXICHA:5; + uint32_t:1; + } B; + } RXICHAR; + + union { /* TX Isochronous Channel Address Register */ + uint32_t R; + struct { + uint32_t TXICHA_ACEN:1; + uint32_t:25; + uint32_t TXICHA:5; + uint32_t:1; + } B; + } TXICHAR; + + }; + +/* Define memories */ + +#define SRAM_START 0x40000000UL +#define SRAM_SIZE 0x14000UL +#define SRAM_END 0x40013FFFUL + +#define FLASH_START 0x0UL +#define FLASH_SIZE 0x180000UL +#define FLASH_END 0x17FFFFUL + +/* Define instances of modules */ +#define SEMA4 (*(volatile struct SEMA4_tag *) 0xFFF10000UL) +#define MPU (*(volatile struct MPU_tag *) 0xFFF14000UL) +#define MCM (*(volatile struct MCM_tag *) 0xFFF40000UL) +#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) +#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL) +#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000UL) +#define MLB (*(volatile struct MLB_tag *) 0xFFF84000UL) +#define I2C (*(volatile struct I2C_tag *) 0xFFF88000UL) +#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000UL) +#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000UL) +#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000UL) +#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000UL) +#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFA0000UL) +#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFA4000UL) +#define ESCI_C (*(volatile struct ESCI_tag *) 0xFFFA8000UL) +#define ESCI_D (*(volatile struct ESCI_tag *) 0xFFFAC000UL) +#define ESCI_E (*(volatile struct ESCI_tag *) 0xFFFB0000UL) +#define ESCI_F (*(volatile struct ESCI_tag *) 0xFFFB4000UL) +#define ESCI_G (*(volatile struct ESCI_tag *) 0xFFFB8000UL) +#define ESCI_H (*(volatile struct ESCI_tag *) 0xFFFBC000UL) +#define CAN_A (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL) +#define CAN_B (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL) +#define CAN_C (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL) +#define CAN_D (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL) +#define CAN_E (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL) +#define CAN_F (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL) +#define FR (*(volatile struct FR_tag *) 0xFFFD8000UL) +#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL) +#define PIT (*(volatile struct PIT_tag *) 0xFFFE0000UL) +#define EMIOS (*(volatile struct EMIOS_tag *) 0xFFFE4000UL) +#define SIU (*(volatile struct SIU_tag *) 0xFFFE8000UL) +#define CRP (*(volatile struct CRP_tag *) 0xFFFEC000UL) +#define FMPLL (*(volatile struct FMPLL_tag *) 0xFFFF0000UL) +#define EBI (*(volatile struct EBI_tag *) 0xFFFF4000UL) +#define FLASH (*(volatile struct FLASH_tag *) 0xFFFF8000UL) + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ +#endif /* ifdef _MPC5510_H */ +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ diff --git a/bsps/powerpc/include/mpc55xx/fsl-mpc555x.h b/bsps/powerpc/include/mpc55xx/fsl-mpc555x.h new file mode 100644 index 0000000000..0dea1957cf --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/fsl-mpc555x.h @@ -0,0 +1,3383 @@ +/* + * Modifications of the original file provided by Freescale are: + * + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/**************************************************************************/ +/* FILE NAME: mpc5554.h COPYRIGHT (c) Freescale 2007 */ +/* VERSION: 1.7 All Rights Reserved */ +/* */ +/* DESCRIPTION: */ +/* This file contain all of the register and bit field definitions for */ +/* MPC5554. */ +/*========================================================================*/ +/* UPDATE HISTORY */ +/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ +/* --- ----------- --------- --------------------- */ +/* 0.01 J. Loeliger 03/Mar/03 Initial version of file for MPC5554. */ +/* Based on SoC version 0.7. */ +/* 0.02 J. Loeliger 05/Mar/03 All registers and bit fields now */ +/* defined. */ +/* 0.03 J. Loeliger 05/May/03 Updated to current spec., fixed several*/ +/* bugs and naming/formating issues. */ +/* 0.04 J. Loeliger 16/May/03 More fixes and naming/formating issues.*/ +/* 0.05 J. Loeliger 19/Aug/03 Updated for latest documentation. */ +/* 0.06 J. Loeliger 03/Sep/03 Changed to include motint.h */ +/* Updated many register names. */ +/* 0.07 J. Loeliger 04/Nov/03 Changed to include typedefs.h and more */ +/* register name updates. */ +/* 0.08 J. Loeliger 25/Feb/04 Added MetroWerks #pragmas. */ +/* Updated for user manual 1.0 */ +/* 0.09 J. Loeliger 27/Feb/04 Updated eDMA tcd section and some more */ +/* bit field names to match user's man. */ +/* 0.10 J. Loeliger 01/Apr/04 Fixed register spacing in ADC and eTPU */ +/* 0.11 J. Loeliger 16/Jun/04 Many fixes and updated to user's */ +/* manual, also some testing done. */ +/* 0.12 J. Loeliger 25/Jun/04 Fixed problems in edma and eTPU. */ +/* 0.13 J. Loeliger 16/Jul/04 Fixed mistake in FlexCAN TIMER size and*/ +/* changed eTPU memory defs to start with*/ +/* ETPU_ */ +/* 0.14 J. Loeliger 17/Nov/04 Added ETPU_CODE_RAM definition. */ +/* All code moved to CVS repository. */ +/* Updated copyright to Freescale. */ +/* Added new SCMOFFDATAR register to eTPU*/ +/* Fixed REDCR_A&B bit fields in eTPU. */ +/* Added new DBR bit in CTAR for DSPI. */ +/* 0.15 J. Loeliger 29/Nov/04 Added support for new eTPU util funcs. */ +/* Added bit fields for FlexCAN buffer ID*/ +/* 0.16 J. Loeliger 01/Dec/04 Corrected comments in release 0.16. */ +/* 0.17 J. Loeliger 02/Dec/04 Moved eTPU variable definitions to a */ +/* seperate new file. */ +/* Removed SIU variable the GPIO */ +/* routines do not need it. */ +/* 1.0 G.Emerson 22/Feb/05 No real changes to this file. */ +/* Joint generation with mpc5553.h */ +/* 1.1 G. Emerson 6/Jun/05 Changes to SIU to allow for upward */ +/* expansion of PCR/GPDI/GPDO */ +/* Added #defines for memory sizes etc */ +/* 1.2 G. Emerson 21/Sep/05 PBRIDGES fixes */ +/* 1.3 G. Emerson 03/Jan/06 Pbridge MPCR/PACR/OPACR now generic */ +/* XBAR MPR now generic */ +/* ECSM has FSBMCR on all integrations */ +/* 1.4 G. Emerson 24/Jan/06 Make Pbridges, XBAR, Flash BIU */ +/* integration specific */ +/* 1.5 S. Mathieson 28/Jul/06 Split out unused bit to support build */ +/* process. No real change. */ +/* 1.6 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */ +/* to DPB to align with documentation. */ +/* 1.7 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */ +/* alternate configuration. INTC, */ +/* correction to the number of PSR */ +/* registers. */ +/**************************************************************************/ +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +#ifndef _MPC5554_H_ +#define _MPC5554_H_ + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/****************************************************************************/ +/* MODULE : PBRIDGE_A Peripheral Bridge */ +/****************************************************************************/ + struct PBRIDGE_A_tag { + union { + uint32_t R; + struct { + uint32_t MBW0:1; + uint32_t MTR0:1; + uint32_t MTW0:1; + uint32_t MPL0:1; + uint32_t MBW1:1; + uint32_t MTR1:1; + uint32_t MTW1:1; + uint32_t MPL1:1; + uint32_t MBW2:1; + uint32_t MTR2:1; + uint32_t MTW2:1; + uint32_t MPL2:1; + uint32_t MBW3:1; + uint32_t MTR3:1; + uint32_t MTW3:1; + uint32_t MPL3:1; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + } B; + } MPCR; /* Master Privilege Control Register */ + + uint32_t pbridge_a_reserved2[7]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:28; + } B; + } PACR0; + + uint32_t pbridge_a_reserved3[7]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t:4; + uint32_t BW4:1; + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:12; + } B; + } OPACR0; + + union { + uint32_t R; + struct { + + uint32_t BW0:1; /* EMIOS */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + + uint32_t:28; + } B; + } OPACR1; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:4; + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t BW3:1; + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + uint32_t BW4:1; + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:12; + } B; + } OPACR2; + + }; + +/****************************************************************************/ +/* MODULE : PBRIDGE_B Peripheral Bridge */ +/****************************************************************************/ + struct PBRIDGE_B_tag { + union { + uint32_t R; + struct { + uint32_t MBW0:1; + uint32_t MTR0:1; + uint32_t MTW0:1; + uint32_t MPL0:1; + uint32_t MBW1:1; + uint32_t MTR1:1; + uint32_t MTW1:1; + uint32_t MPL1:1; + uint32_t MBW2:1; + uint32_t MTR2:1; + uint32_t MTW2:1; + uint32_t MPL2:1; + uint32_t MBW3:1; + uint32_t MTR3:1; + uint32_t MTW3:1; + uint32_t MPL3:1; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + } B; + } MPCR; /* Master Privilege Control Register */ + + uint32_t pbridge_b_reserved2[7]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t:24; + } B; + } PACR0; + + uint32_t pbridge_b_reserved3; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + + uint32_t:4; + + uint32_t:16; + + } B; + } PACR2; + + uint32_t pbridge_b_reserved4[5]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:12; + + uint32_t BW4:1; /* DSPI_A */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + + uint32_t BW5:1; /* DSPI_B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + + uint32_t BW6:1; + uint32_t SP6:1; + uint32_t WP6:1; + uint32_t TP6:1; + uint32_t BW7:1; + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR0; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t BW4:1; + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + + uint32_t BW5:1; /* ESCI_B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + + uint32_t:8; + } B; + } OPACR1; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + + uint32_t BW1:1; /* CAN_B */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + + uint32_t:4; + + uint32_t:4; + + uint32_t:12; + } B; + } OPACR2; + + union { + uint32_t R; + struct { + + uint32_t:4; + + uint32_t:24; + uint32_t BW7:1; + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR3; + + }; +/****************************************************************************/ +/* MODULE : FMPLL */ +/****************************************************************************/ + struct FMPLL_tag { + union FMPLL_SYNCR_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t PREDIV:3; + uint32_t MFD:5; + uint32_t:1; + uint32_t RFD:3; + uint32_t LOCEN:1; + uint32_t LOLRE:1; + uint32_t LOCRE:1; + uint32_t DISCLK:1; + uint32_t LOLIRQ:1; + uint32_t LOCIRQ:1; + uint32_t RATE:1; + uint32_t DEPTH:2; + uint32_t EXP:10; + } B; + } SYNCR; + + union FMPLL_SYNSR_tag { + uint32_t R; + struct { + uint32_t:22; + uint32_t LOLF:1; + uint32_t LOC:1; + uint32_t MODE:1; + uint32_t PLLSEL:1; + uint32_t PLLREF:1; + uint32_t LOCKS:1; + uint32_t LOCK:1; + uint32_t LOCF:1; + uint32_t CALDONE:1; + uint32_t CALPASS:1; + } B; + } SYNSR; + + }; +/****************************************************************************/ +/* MODULE : External Bus Interface (EBI) */ +/****************************************************************************/ + struct EBI_CS_tag { + union { /* Base Register Bank */ + uint32_t R; + struct { + uint32_t BA:17; + uint32_t:3; + uint32_t PS:1; + uint32_t:4; + uint32_t BL:1; + uint32_t WEBS:1; + uint32_t TBDIP:1; + uint32_t:2; + uint32_t BI:1; + uint32_t V:1; + } B; + } BR; + + union { /* Option Register Bank */ + uint32_t R; + struct { + uint32_t AM:17; + uint32_t:7; + uint32_t SCY:4; + uint32_t:1; + uint32_t BSCY:2; + uint32_t:1; + } B; + } OR; + }; + + struct EBI_CAL_CS_tag { + uint32_t ebi_cal_cs_reserved [2]; + }; + + struct EBI_tag { + union EBI_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:5; + uint32_t SIZEEN:1; + uint32_t SIZE:2; + uint32_t:8; + uint32_t ACGE:1; + uint32_t EXTM:1; + uint32_t EARB:1; + uint32_t EARP:2; + uint32_t:4; + uint32_t MDIS:1; + uint32_t:5; + uint32_t DBM:1; + } B; + } MCR; + + uint32_t EBI_reserved1; + + union { /* Transfer Error Status Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t TEAF:1; + uint32_t BMTF:1; + } B; + } TESR; + + union { /* Bus Monitor Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t BMT:8; + uint32_t BME:1; + uint32_t:7; + } B; + } BMCR; + + struct EBI_CS_tag CS[4]; + + uint32_t EBI_reserved2[4]; + + struct EBI_CAL_CS_tag CAL_CS[4]; + }; +/****************************************************************************/ +/* MODULE : FLASH */ +/****************************************************************************/ + struct FLASH_tag { + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:4; + uint32_t SIZE:4; + uint32_t:1; + uint32_t LAS:3; + uint32_t:3; + uint32_t MAS:1; + uint32_t EER:1; + uint32_t RWE:1; + uint32_t BBEPE:1; + uint32_t EPE:1; + uint32_t PEAS:1; + uint32_t DONE:1; + uint32_t PEG:1; + + uint32_t:2; + + uint32_t STOP:1; + uint32_t:1; + uint32_t PGM:1; + uint32_t PSUS:1; + uint32_t ERS:1; + uint32_t ESUS:1; + uint32_t EHV:1; + } B; + } MCR; + + union LMLR_tag { /* LML Register */ + uint32_t R; + struct { + uint32_t LME:1; + uint32_t:10; + uint32_t SLOCK:1; + uint32_t MLOCK:4; + uint32_t LLOCK:16; + } B; + } LMLR; + + union HLR_tag { /* HL Register */ + uint32_t R; + struct { + uint32_t HBE:1; + uint32_t:3; + uint32_t HBLOCK:28; + } B; + } HLR; + + union SLMLR_tag { /* SLML Register */ + uint32_t R; + struct { + uint32_t SLE:1; + uint32_t:10; + uint32_t SSLOCK:1; + uint32_t SMLOCK:4; + uint32_t SLLOCK:16; + } B; + } SLMLR; + + union { /* LMS Register */ + uint32_t R; + struct { + uint32_t:12; + uint32_t MSEL:4; + uint32_t LSEL:16; + } B; + } LMSR; + + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t HBSEL:28; + } B; + } HSR; + + union { + uint32_t R; + struct { + uint32_t:10; + uint32_t ADDR:19; + uint32_t:3; + } B; + } AR; + + union { + uint32_t R; + struct { + + uint32_t:11; + + uint32_t:1; + + uint32_t M3PFE:1; + uint32_t M2PFE:1; + uint32_t M1PFE:1; + uint32_t M0PFE:1; + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + + uint32_t DPFEN:2; + uint32_t IPFEN:2; + + uint32_t PFLIM:3; + uint32_t BFEN:1; + } B; + } BIUCR; + + union { + uint32_t R; + struct { + + uint32_t:22; + + uint32_t:2; + + uint32_t M3AP:2; + uint32_t M2AP:2; + uint32_t M1AP:2; + uint32_t M0AP:2; + } B; + } BIUAPR; + }; +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + int32_t SIU_reserved0; + + union { /* MCU ID Register */ + uint32_t R; + struct { + uint32_t PARTNUM:16; + uint32_t MASKNUM:16; + } B; + } MIDR; + int32_t SIU_reserved00; + + union { /* Reset Status Register */ + uint32_t R; + struct { + uint32_t PORS:1; + uint32_t ERS:1; + uint32_t LLRS:1; + uint32_t LCRS:1; + uint32_t WDRS:1; + uint32_t CRS:1; + uint32_t:8; + uint32_t SSRS:1; + uint32_t SERF:1; + uint32_t WKPCFG:1; + uint32_t:12; + uint32_t BOOTCFG:2; + uint32_t RGF:1; + } B; + } RSR; + + union { /* System Reset Control Register */ + uint32_t R; + struct { + uint32_t SSR:1; + uint32_t SER:1; + uint32_t:14; + uint32_t CRE:1; + uint32_t:15; + } B; + } SRCR; + + union SIU_EISR_tag { /* External Interrupt Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t EIF15:1; + uint32_t EIF14:1; + uint32_t EIF13:1; + uint32_t EIF12:1; + uint32_t EIF11:1; + uint32_t EIF10:1; + uint32_t EIF9:1; + uint32_t EIF8:1; + uint32_t EIF7:1; + uint32_t EIF6:1; + uint32_t EIF5:1; + uint32_t EIF4:1; + uint32_t EIF3:1; + uint32_t EIF2:1; + uint32_t EIF1:1; + uint32_t EIF0:1; + } B; + } EISR; + + union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t EIRE15:1; + uint32_t EIRE14:1; + uint32_t EIRE13:1; + uint32_t EIRE12:1; + uint32_t EIRE11:1; + uint32_t EIRE10:1; + uint32_t EIRE9:1; + uint32_t EIRE8:1; + uint32_t EIRE7:1; + uint32_t EIRE6:1; + uint32_t EIRE5:1; + uint32_t EIRE4:1; + uint32_t EIRE3:1; + uint32_t EIRE2:1; + uint32_t EIRE1:1; + uint32_t EIRE0:1; + } B; + } DIRER; + + union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DIRS3:1; + uint32_t DIRS2:1; + uint32_t DIRS1:1; + uint32_t DIRS0:1; + } B; + } DIRSR; + + union { /* Overrun Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t OVF15:1; + uint32_t OVF14:1; + uint32_t OVF13:1; + uint32_t OVF12:1; + uint32_t OVF11:1; + uint32_t OVF10:1; + uint32_t OVF9:1; + uint32_t OVF8:1; + uint32_t OVF7:1; + uint32_t OVF6:1; + uint32_t OVF5:1; + uint32_t OVF4:1; + uint32_t OVF3:1; + uint32_t OVF2:1; + uint32_t OVF1:1; + uint32_t OVF0:1; + } B; + } OSR; + + union SIU_ORER_tag { /* Overrun Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ORE15:1; + uint32_t ORE14:1; + uint32_t ORE13:1; + uint32_t ORE12:1; + uint32_t ORE11:1; + uint32_t ORE10:1; + uint32_t ORE9:1; + uint32_t ORE8:1; + uint32_t ORE7:1; + uint32_t ORE6:1; + uint32_t ORE5:1; + uint32_t ORE4:1; + uint32_t ORE3:1; + uint32_t ORE2:1; + uint32_t ORE1:1; + uint32_t ORE0:1; + } B; + } ORER; + + union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t IREE15:1; + uint32_t IREE14:1; + uint32_t IREE13:1; + uint32_t IREE12:1; + uint32_t IREE11:1; + uint32_t IREE10:1; + uint32_t IREE9:1; + uint32_t IREE8:1; + uint32_t IREE7:1; + uint32_t IREE6:1; + uint32_t IREE5:1; + uint32_t IREE4:1; + uint32_t IREE3:1; + uint32_t IREE2:1; + uint32_t IREE1:1; + uint32_t IREE0:1; + } B; + } IREER; + + union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t IFEE15:1; + uint32_t IFEE14:1; + uint32_t IFEE13:1; + uint32_t IFEE12:1; + uint32_t IFEE11:1; + uint32_t IFEE10:1; + uint32_t IFEE9:1; + uint32_t IFEE8:1; + uint32_t IFEE7:1; + uint32_t IFEE6:1; + uint32_t IFEE5:1; + uint32_t IFEE4:1; + uint32_t IFEE3:1; + uint32_t IFEE2:1; + uint32_t IFEE1:1; + uint32_t IFEE0:1; + } B; + } IFEER; + + union SIU_IDFR_tag { /* External IRQ Digital Filter Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } IDFR; + + int32_t SIU_reserved1[3]; + + union SIU_PCR_tag { /* Pad Configuration Registers */ + uint16_t R; + struct { + uint16_t:3; + uint16_t PA:3; + uint16_t OBE:1; + uint16_t IBE:1; + uint16_t DSC:2; + uint16_t ODE:1; + uint16_t HYS:1; + uint16_t SRC:2; + uint16_t WPE:1; + uint16_t WPS:1; + } B; + } PCR[512]; + + int16_t SIU_reserved_0[224]; + + union { /* GPIO Pin Data Output Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDO:1; + } B; + } GPDO[256]; + + int32_t SIU_reserved_3[64]; + + union { /* GPIO Pin Data Input Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; + } B; + } GPDI[256]; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t TSEL5:2; + uint32_t TSEL4:2; + uint32_t TSEL3:2; + uint32_t TSEL2:2; + uint32_t TSEL1:2; + uint32_t TSEL0:2; + uint32_t:20; + } B; + } ETISR; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } EIISR; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t SINSELA:2; + uint32_t SSSELA:2; + uint32_t SCKSELA:2; + uint32_t TRIGSELA:2; + uint32_t SINSELB:2; + uint32_t SSSELB:2; + uint32_t SCKSELB:2; + uint32_t TRIGSELB:2; + uint32_t SINSELC:2; + uint32_t SSSELC:2; + uint32_t SCKSELC:2; + uint32_t TRIGSELC:2; + uint32_t SINSELD:2; + uint32_t SSSELD:2; + uint32_t SCKSELD:2; + uint32_t TRIGSELD:2; + } B; + } DISR; + + int32_t SIU_reserved2[29]; + + union { /* Chip Configuration Register Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MATCH:1; + uint32_t DISNEX:1; + uint32_t:16; + } B; + } CCR; + + union { /* External Clock Configuration Register Register */ + uint32_t R; + struct { + uint32_t:18; + uint32_t ENGDIV:6; + uint32_t:4; + uint32_t EBTS:1; + uint32_t:1; + uint32_t EBDF:2; + } B; + } ECCR; + + union { + uint32_t R; + } CARH; + + union { + uint32_t R; + } CARL; + + union { + uint32_t R; + } CBRH; + + union { + uint32_t R; + } CBRL; + + }; +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + struct EMIOS_tag { + union EMIOS_MCR_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t GTBE:1; + uint32_t ETB:1; + uint32_t GPREN:1; + uint32_t:6; + uint32_t SRV:4; + uint32_t GPRE:8; + uint32_t:8; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t F23:1; + uint32_t F22:1; + uint32_t F21:1; + uint32_t F20:1; + uint32_t F19:1; + uint32_t F18:1; + uint32_t F17:1; + uint32_t F16:1; + uint32_t F15:1; + uint32_t F14:1; + uint32_t F13:1; + uint32_t F12:1; + uint32_t F11:1; + uint32_t F10:1; + uint32_t F9:1; + uint32_t F8:1; + uint32_t F7:1; + uint32_t F6:1; + uint32_t F5:1; + uint32_t F4:1; + uint32_t F3:1; + uint32_t F2:1; + uint32_t F1:1; + uint32_t F0:1; + } B; + } GFR; /* Global FLAG Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t OU23:1; + uint32_t OU22:1; + uint32_t OU21:1; + uint32_t OU20:1; + uint32_t OU19:1; + uint32_t OU18:1; + uint32_t OU17:1; + uint32_t OU16:1; + uint32_t OU15:1; + uint32_t OU14:1; + uint32_t OU13:1; + uint32_t OU12:1; + uint32_t OU11:1; + uint32_t OU10:1; + uint32_t OU9:1; + uint32_t OU8:1; + uint32_t OU7:1; + uint32_t OU6:1; + uint32_t OU5:1; + uint32_t OU4:1; + uint32_t OU3:1; + uint32_t OU2:1; + uint32_t OU1:1; + uint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register */ + + uint32_t emios_reserved[5]; + + struct EMIOS_CH_tag { + union { + uint32_t R; /* Channel A Data Register */ + } CADR; + + union { + uint32_t R; /* Channel B Data Register */ + } CBDR; + + union { + uint32_t R; /* Channel Counter Register */ + } CCNTR; + + union EMIOS_CCR_tag { + uint32_t R; + struct { + uint32_t FREN:1; + uint32_t ODIS:1; + uint32_t ODISSL:2; + uint32_t UCPRE:2; + uint32_t UCPREN:1; + uint32_t DMA:1; + uint32_t:1; + uint32_t IF:4; + uint32_t FCK:1; + uint32_t FEN:1; + uint32_t:3; + uint32_t FORCMA:1; + uint32_t FORCMB:1; + uint32_t:1; + uint32_t BSL:2; + uint32_t EDSEL:1; + uint32_t EDPOL:1; + uint32_t MODE:7; + } B; + } CCR; /* Channel Control Register */ + + union EMIOS_CSR_tag { + uint32_t R; + struct { + uint32_t OVR:1; + uint32_t:15; + uint32_t OVFL:1; + uint32_t:12; + uint32_t UCIN:1; + uint32_t UCOUT:1; + uint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register */ + uint32_t emios_channel_reserved[3]; + + } CH[24]; + + }; +/****************************************************************************/ +/* MODULE :ETPU */ +/****************************************************************************/ + +/***************************Configuration Registers**************************/ + + struct ETPU_tag { + union { /* MODULE CONFIGURATION REGISTER */ + uint32_t R; + struct { + uint32_t GEC:1; /* Global Exception Clear */ + uint32_t:3; + uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */ + + uint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */ + + uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */ + + uint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */ + + uint32_t:3; + uint32_t SCMSIZE:5; /* Shared Code Memory size */ + uint32_t:5; + uint32_t SCMMISF:1; /* SCM MISC Flag */ + uint32_t SCMMISEN:1; /* SCM MISC Enable */ + uint32_t:2; + uint32_t VIS:1; /* SCM Visability */ + uint32_t:5; + uint32_t GTBE:1; /* Global Time Base Enable */ + } B; + } MCR; + + union { /* COHERENT DUAL-PARAMETER CONTROL */ + uint32_t R; + struct { + uint32_t STS:1; /* Start Status bit */ + uint32_t CTBASE:5; /* Channel Transfer Base */ + uint32_t PBASE:10; /* Parameter Buffer Base Address */ + uint32_t PWIDTH:1; /* Parameter Width */ + uint32_t PARAM0:7; /* Channel Parameter 0 */ + uint32_t WR:1; + uint32_t PARAM1:7; /* Channel Parameter 1 */ + } B; + } CDCR; + + uint32_t etpu_reserved1; + + union { /* MISC Compare Register */ + uint32_t R; + } MISCCMPR; + + union { /* SCM off-range Date Register */ + uint32_t R; + } SCMOFFDATAR; + + union { /* ETPU_A Configuration Register */ + uint32_t R; + struct { + uint32_t FEND:1; /* Force END */ + uint32_t MDIS:1; /* Low power Stop */ + uint32_t:1; + uint32_t STF:1; /* Stop Flag */ + uint32_t:4; + uint32_t HLTF:1; /* Halt Mode Flag */ + uint32_t:4; + uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + uint32_t CDFC:2; + uint32_t:9; + uint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_A; + + union { /* ETPU_B Configuration Register */ + uint32_t R; + struct { + uint32_t FEND:1; /* Force END */ + uint32_t MDIS:1; /* Low power Stop */ + uint32_t:1; + uint32_t STF:1; /* Stop Flag */ + uint32_t:4; + uint32_t HLTF:1; /* Halt Mode Flag */ + uint32_t:4; + uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + uint32_t CDFC:2; + uint32_t:9; + uint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_B; + + uint32_t etpu_reserved4; + + union { /* ETPU_A Timebase Configuration Register */ + uint32_t R; + struct { + uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + uint32_t:1; + uint32_t AM:1; /* Angle Mode */ + uint32_t:3; + uint32_t TCR2P:6; /* TCR2 Prescaler Control */ + uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + uint32_t:6; + uint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_A; + + union { /* ETPU_A TCR1 Visibility Register */ + uint32_t R; + } TB1R_A; + + union { /* ETPU_A TCR2 Visibility Register */ + uint32_t R; + } TB2R_A; + + union { /* ETPU_A STAC Configuration Register */ + uint32_t R; + struct { + uint32_t REN1:1; /* Resource Enable TCR1 */ + uint32_t RSC1:1; /* Resource Control TCR1 */ + uint32_t:2; + uint32_t SERVER_ID1:4; + uint32_t:4; + uint32_t SRV1:4; /* Resource Server Slot */ + uint32_t REN2:1; /* Resource Enable TCR2 */ + uint32_t RSC2:1; /* Resource Control TCR2 */ + uint32_t:2; + uint32_t SERVER_ID2:4; + uint32_t:4; + uint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_A; + + uint32_t etpu_reserved5[4]; + + union { /* ETPU_B Timebase Configuration Register */ + uint32_t R; + struct { + uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + uint32_t:1; + uint32_t AM:1; /* Angle Mode */ + uint32_t:3; + uint32_t TCR2P:6; /* TCR2 Prescaler Control */ + uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + uint32_t:6; + uint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_B; + + union { /* ETPU_B TCR1 Visibility Register */ + uint32_t R; + } TB1R_B; + + union { /* ETPU_B TCR2 Visibility Register */ + uint32_t R; + } TB2R_B; + + union { /* ETPU_B STAC Configuration Register */ + uint32_t R; + struct { + uint32_t REN1:1; /* Resource Enable TCR1 */ + uint32_t RSC1:1; /* Resource Control TCR1 */ + uint32_t:2; + uint32_t SERVER_ID1:4; + uint32_t:4; + uint32_t SRV1:4; /* Resource Server Slot */ + uint32_t REN2:1; /* Resource Enable TCR2 */ + uint32_t RSC2:1; /* Resource Control TCR2 */ + uint32_t:2; + uint32_t SERVER_ID2:4; + uint32_t:4; + uint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_B; + + uint32_t etpu_reserved7[108]; + +/*****************************Status and Control Registers**************************/ + + union { /* ETPU_A Channel Interrut Status */ + uint32_t R; + struct { + uint32_t CIS31:1; /* Channel 31 Interrut Status */ + uint32_t CIS30:1; /* Channel 30 Interrut Status */ + uint32_t CIS29:1; /* Channel 29 Interrut Status */ + uint32_t CIS28:1; /* Channel 28 Interrut Status */ + uint32_t CIS27:1; /* Channel 27 Interrut Status */ + uint32_t CIS26:1; /* Channel 26 Interrut Status */ + uint32_t CIS25:1; /* Channel 25 Interrut Status */ + uint32_t CIS24:1; /* Channel 24 Interrut Status */ + uint32_t CIS23:1; /* Channel 23 Interrut Status */ + uint32_t CIS22:1; /* Channel 22 Interrut Status */ + uint32_t CIS21:1; /* Channel 21 Interrut Status */ + uint32_t CIS20:1; /* Channel 20 Interrut Status */ + uint32_t CIS19:1; /* Channel 19 Interrut Status */ + uint32_t CIS18:1; /* Channel 18 Interrut Status */ + uint32_t CIS17:1; /* Channel 17 Interrut Status */ + uint32_t CIS16:1; /* Channel 16 Interrut Status */ + uint32_t CIS15:1; /* Channel 15 Interrut Status */ + uint32_t CIS14:1; /* Channel 14 Interrut Status */ + uint32_t CIS13:1; /* Channel 13 Interrut Status */ + uint32_t CIS12:1; /* Channel 12 Interrut Status */ + uint32_t CIS11:1; /* Channel 11 Interrut Status */ + uint32_t CIS10:1; /* Channel 10 Interrut Status */ + uint32_t CIS9:1; /* Channel 9 Interrut Status */ + uint32_t CIS8:1; /* Channel 8 Interrut Status */ + uint32_t CIS7:1; /* Channel 7 Interrut Status */ + uint32_t CIS6:1; /* Channel 6 Interrut Status */ + uint32_t CIS5:1; /* Channel 5 Interrut Status */ + uint32_t CIS4:1; /* Channel 4 Interrut Status */ + uint32_t CIS3:1; /* Channel 3 Interrut Status */ + uint32_t CIS2:1; /* Channel 2 Interrut Status */ + uint32_t CIS1:1; /* Channel 1 Interrut Status */ + uint32_t CIS0:1; /* Channel 0 Interrut Status */ + } B; + } CISR_A; + + union { /* ETPU_B Channel Interruput Status */ + uint32_t R; + struct { + uint32_t CIS31:1; /* Channel 31 Interrut Status */ + uint32_t CIS30:1; /* Channel 30 Interrut Status */ + uint32_t CIS29:1; /* Channel 29 Interrut Status */ + uint32_t CIS28:1; /* Channel 28 Interrut Status */ + uint32_t CIS27:1; /* Channel 27 Interrut Status */ + uint32_t CIS26:1; /* Channel 26 Interrut Status */ + uint32_t CIS25:1; /* Channel 25 Interrut Status */ + uint32_t CIS24:1; /* Channel 24 Interrut Status */ + uint32_t CIS23:1; /* Channel 23 Interrut Status */ + uint32_t CIS22:1; /* Channel 22 Interrut Status */ + uint32_t CIS21:1; /* Channel 21 Interrut Status */ + uint32_t CIS20:1; /* Channel 20 Interrut Status */ + uint32_t CIS19:1; /* Channel 19 Interrut Status */ + uint32_t CIS18:1; /* Channel 18 Interrut Status */ + uint32_t CIS17:1; /* Channel 17 Interrut Status */ + uint32_t CIS16:1; /* Channel 16 Interrut Status */ + uint32_t CIS15:1; /* Channel 15 Interrut Status */ + uint32_t CIS14:1; /* Channel 14 Interrut Status */ + uint32_t CIS13:1; /* Channel 13 Interrut Status */ + uint32_t CIS12:1; /* Channel 12 Interrut Status */ + uint32_t CIS11:1; /* Channel 11 Interrut Status */ + uint32_t CIS10:1; /* Channel 10 Interrut Status */ + uint32_t CIS9:1; /* Channel 9 Interrut Status */ + uint32_t CIS8:1; /* Channel 8 Interrut Status */ + uint32_t CIS7:1; /* Channel 7 Interrut Status */ + uint32_t CIS6:1; /* Channel 6 Interrut Status */ + uint32_t CIS5:1; /* Channel 5 Interrut Status */ + uint32_t CIS4:1; /* Channel 4 Interrut Status */ + uint32_t CIS3:1; /* Channel 3 Interrut Status */ + uint32_t CIS2:1; /* Channel 2 Interrut Status */ + uint32_t CIS1:1; /* Channel 1 Interrupt Status */ + uint32_t CIS0:1; /* Channel 0 Interrupt Status */ + } B; + } CISR_B; + + uint32_t etpu_reserved9[2]; + + union { /* ETPU_A Data Transfer Request Status */ + uint32_t R; + struct { + uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_A; + + union { /* ETPU_B Data Transfer Request Status */ + uint32_t R; + struct { + uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_B; + + uint32_t etpu_reserved11[2]; + + union { /* ETPU_A Interruput Overflow Status */ + uint32_t R; + struct { + uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_A; + + union { /* ETPU_B Interruput Overflow Status */ + uint32_t R; + struct { + uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_B; + + uint32_t etpu_reserved13[2]; + + union { /* ETPU_A Data Transfer Overflow Status */ + uint32_t R; + struct { + uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_A; + + union { /* ETPU_B Data Transfer Overflow Status */ + uint32_t R; + struct { + uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_B; + + uint32_t etpu_reserved15[2]; + + union { /* ETPU_A Channel Interruput Enable */ + uint32_t R; + struct { + uint32_t CIE31:1; /* Channel 31 Interruput Enable */ + uint32_t CIE30:1; /* Channel 30 Interruput Enable */ + uint32_t CIE29:1; /* Channel 29 Interruput Enable */ + uint32_t CIE28:1; /* Channel 28 Interruput Enable */ + uint32_t CIE27:1; /* Channel 27 Interruput Enable */ + uint32_t CIE26:1; /* Channel 26 Interruput Enable */ + uint32_t CIE25:1; /* Channel 25 Interruput Enable */ + uint32_t CIE24:1; /* Channel 24 Interruput Enable */ + uint32_t CIE23:1; /* Channel 23 Interruput Enable */ + uint32_t CIE22:1; /* Channel 22 Interruput Enable */ + uint32_t CIE21:1; /* Channel 21 Interruput Enable */ + uint32_t CIE20:1; /* Channel 20 Interruput Enable */ + uint32_t CIE19:1; /* Channel 19 Interruput Enable */ + uint32_t CIE18:1; /* Channel 18 Interruput Enable */ + uint32_t CIE17:1; /* Channel 17 Interruput Enable */ + uint32_t CIE16:1; /* Channel 16 Interruput Enable */ + uint32_t CIE15:1; /* Channel 15 Interruput Enable */ + uint32_t CIE14:1; /* Channel 14 Interruput Enable */ + uint32_t CIE13:1; /* Channel 13 Interruput Enable */ + uint32_t CIE12:1; /* Channel 12 Interruput Enable */ + uint32_t CIE11:1; /* Channel 11 Interruput Enable */ + uint32_t CIE10:1; /* Channel 10 Interruput Enable */ + uint32_t CIE9:1; /* Channel 9 Interruput Enable */ + uint32_t CIE8:1; /* Channel 8 Interruput Enable */ + uint32_t CIE7:1; /* Channel 7 Interruput Enable */ + uint32_t CIE6:1; /* Channel 6 Interruput Enable */ + uint32_t CIE5:1; /* Channel 5 Interruput Enable */ + uint32_t CIE4:1; /* Channel 4 Interruput Enable */ + uint32_t CIE3:1; /* Channel 3 Interruput Enable */ + uint32_t CIE2:1; /* Channel 2 Interruput Enable */ + uint32_t CIE1:1; /* Channel 1 Interruput Enable */ + uint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_A; + + union { /* ETPU_B Channel Interruput Enable */ + uint32_t R; + struct { + uint32_t CIE31:1; /* Channel 31 Interruput Enable */ + uint32_t CIE30:1; /* Channel 30 Interruput Enable */ + uint32_t CIE29:1; /* Channel 29 Interruput Enable */ + uint32_t CIE28:1; /* Channel 28 Interruput Enable */ + uint32_t CIE27:1; /* Channel 27 Interruput Enable */ + uint32_t CIE26:1; /* Channel 26 Interruput Enable */ + uint32_t CIE25:1; /* Channel 25 Interruput Enable */ + uint32_t CIE24:1; /* Channel 24 Interruput Enable */ + uint32_t CIE23:1; /* Channel 23 Interruput Enable */ + uint32_t CIE22:1; /* Channel 22 Interruput Enable */ + uint32_t CIE21:1; /* Channel 21 Interruput Enable */ + uint32_t CIE20:1; /* Channel 20 Interruput Enable */ + uint32_t CIE19:1; /* Channel 19 Interruput Enable */ + uint32_t CIE18:1; /* Channel 18 Interruput Enable */ + uint32_t CIE17:1; /* Channel 17 Interruput Enable */ + uint32_t CIE16:1; /* Channel 16 Interruput Enable */ + uint32_t CIE15:1; /* Channel 15 Interruput Enable */ + uint32_t CIE14:1; /* Channel 14 Interruput Enable */ + uint32_t CIE13:1; /* Channel 13 Interruput Enable */ + uint32_t CIE12:1; /* Channel 12 Interruput Enable */ + uint32_t CIE11:1; /* Channel 11 Interruput Enable */ + uint32_t CIE10:1; /* Channel 10 Interruput Enable */ + uint32_t CIE9:1; /* Channel 9 Interruput Enable */ + uint32_t CIE8:1; /* Channel 8 Interruput Enable */ + uint32_t CIE7:1; /* Channel 7 Interruput Enable */ + uint32_t CIE6:1; /* Channel 6 Interruput Enable */ + uint32_t CIE5:1; /* Channel 5 Interruput Enable */ + uint32_t CIE4:1; /* Channel 4 Interruput Enable */ + uint32_t CIE3:1; /* Channel 3 Interruput Enable */ + uint32_t CIE2:1; /* Channel 2 Interruput Enable */ + uint32_t CIE1:1; /* Channel 1 Interruput Enable */ + uint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_B; + + uint32_t etpu_reserved17[2]; + + union { /* ETPU_A Channel Data Transfer Request Enable */ + uint32_t R; + struct { + uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_A; + + union { /* ETPU_B Channel Data Transfer Request Enable */ + uint32_t R; + struct { + uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_B; + + uint32_t etpu_reserved20[10]; + union { /* ETPU_A Channel Pending Service Status */ + uint32_t R; + struct { + uint32_t SR31:1; /* Channel 31 Pending Service Status */ + uint32_t SR30:1; /* Channel 30 Pending Service Status */ + uint32_t SR29:1; /* Channel 29 Pending Service Status */ + uint32_t SR28:1; /* Channel 28 Pending Service Status */ + uint32_t SR27:1; /* Channel 27 Pending Service Status */ + uint32_t SR26:1; /* Channel 26 Pending Service Status */ + uint32_t SR25:1; /* Channel 25 Pending Service Status */ + uint32_t SR24:1; /* Channel 24 Pending Service Status */ + uint32_t SR23:1; /* Channel 23 Pending Service Status */ + uint32_t SR22:1; /* Channel 22 Pending Service Status */ + uint32_t SR21:1; /* Channel 21 Pending Service Status */ + uint32_t SR20:1; /* Channel 20 Pending Service Status */ + uint32_t SR19:1; /* Channel 19 Pending Service Status */ + uint32_t SR18:1; /* Channel 18 Pending Service Status */ + uint32_t SR17:1; /* Channel 17 Pending Service Status */ + uint32_t SR16:1; /* Channel 16 Pending Service Status */ + uint32_t SR15:1; /* Channel 15 Pending Service Status */ + uint32_t SR14:1; /* Channel 14 Pending Service Status */ + uint32_t SR13:1; /* Channel 13 Pending Service Status */ + uint32_t SR12:1; /* Channel 12 Pending Service Status */ + uint32_t SR11:1; /* Channel 11 Pending Service Status */ + uint32_t SR10:1; /* Channel 10 Pending Service Status */ + uint32_t SR9:1; /* Channel 9 Pending Service Status */ + uint32_t SR8:1; /* Channel 8 Pending Service Status */ + uint32_t SR7:1; /* Channel 7 Pending Service Status */ + uint32_t SR6:1; /* Channel 6 Pending Service Status */ + uint32_t SR5:1; /* Channel 5 Pending Service Status */ + uint32_t SR4:1; /* Channel 4 Pending Service Status */ + uint32_t SR3:1; /* Channel 3 Pending Service Status */ + uint32_t SR2:1; /* Channel 2 Pending Service Status */ + uint32_t SR1:1; /* Channel 1 Pending Service Status */ + uint32_t SR0:1; /* Channel 0 Pending Service Status */ + } B; + } CPSSR_A; + + union { /* ETPU_B Channel Pending Service Status */ + uint32_t R; + struct { + uint32_t SR31:1; /* Channel 31 Pending Service Status */ + uint32_t SR30:1; /* Channel 30 Pending Service Status */ + uint32_t SR29:1; /* Channel 29 Pending Service Status */ + uint32_t SR28:1; /* Channel 28 Pending Service Status */ + uint32_t SR27:1; /* Channel 27 Pending Service Status */ + uint32_t SR26:1; /* Channel 26 Pending Service Status */ + uint32_t SR25:1; /* Channel 25 Pending Service Status */ + uint32_t SR24:1; /* Channel 24 Pending Service Status */ + uint32_t SR23:1; /* Channel 23 Pending Service Status */ + uint32_t SR22:1; /* Channel 22 Pending Service Status */ + uint32_t SR21:1; /* Channel 21 Pending Service Status */ + uint32_t SR20:1; /* Channel 20 Pending Service Status */ + uint32_t SR19:1; /* Channel 19 Pending Service Status */ + uint32_t SR18:1; /* Channel 18 Pending Service Status */ + uint32_t SR17:1; /* Channel 17 Pending Service Status */ + uint32_t SR16:1; /* Channel 16 Pending Service Status */ + uint32_t SR15:1; /* Channel 15 Pending Service Status */ + uint32_t SR14:1; /* Channel 14 Pending Service Status */ + uint32_t SR13:1; /* Channel 13 Pending Service Status */ + uint32_t SR12:1; /* Channel 12 Pending Service Status */ + uint32_t SR11:1; /* Channel 11 Pending Service Status */ + uint32_t SR10:1; /* Channel 10 Pending Service Status */ + uint32_t SR9:1; /* Channel 9 Pending Service Status */ + uint32_t SR8:1; /* Channel 8 Pending Service Status */ + uint32_t SR7:1; /* Channel 7 Pending Service Status */ + uint32_t SR6:1; /* Channel 6 Pending Service Status */ + uint32_t SR5:1; /* Channel 5 Pending Service Status */ + uint32_t SR4:1; /* Channel 4 Pending Service Status */ + uint32_t SR3:1; /* Channel 3 Pending Service Status */ + uint32_t SR2:1; /* Channel 2 Pending Service Status */ + uint32_t SR1:1; /* Channel 1 Pending Service Status */ + uint32_t SR0:1; /* Channel 0 Pending Service Status */ + } B; + } CPSSR_B; + + uint32_t etpu_reserved20a[2]; + + union { /* ETPU_A Channel Service Status */ + uint32_t R; + struct { + uint32_t SS31:1; /* Channel 31 Service Status */ + uint32_t SS30:1; /* Channel 30 Service Status */ + uint32_t SS29:1; /* Channel 29 Service Status */ + uint32_t SS28:1; /* Channel 28 Service Status */ + uint32_t SS27:1; /* Channel 27 Service Status */ + uint32_t SS26:1; /* Channel 26 Service Status */ + uint32_t SS25:1; /* Channel 25 Service Status */ + uint32_t SS24:1; /* Channel 24 Service Status */ + uint32_t SS23:1; /* Channel 23 Service Status */ + uint32_t SS22:1; /* Channel 22 Service Status */ + uint32_t SS21:1; /* Channel 21 Service Status */ + uint32_t SS20:1; /* Channel 20 Service Status */ + uint32_t SS19:1; /* Channel 19 Service Status */ + uint32_t SS18:1; /* Channel 18 Service Status */ + uint32_t SS17:1; /* Channel 17 Service Status */ + uint32_t SS16:1; /* Channel 16 Service Status */ + uint32_t SS15:1; /* Channel 15 Service Status */ + uint32_t SS14:1; /* Channel 14 Service Status */ + uint32_t SS13:1; /* Channel 13 Service Status */ + uint32_t SS12:1; /* Channel 12 Service Status */ + uint32_t SS11:1; /* Channel 11 Service Status */ + uint32_t SS10:1; /* Channel 10 Service Status */ + uint32_t SS9:1; /* Channel 9 Service Status */ + uint32_t SS8:1; /* Channel 8 Service Status */ + uint32_t SS7:1; /* Channel 7 Service Status */ + uint32_t SS6:1; /* Channel 6 Service Status */ + uint32_t SS5:1; /* Channel 5 Service Status */ + uint32_t SS4:1; /* Channel 4 Service Status */ + uint32_t SS3:1; /* Channel 3 Service Status */ + uint32_t SS2:1; /* Channel 2 Service Status */ + uint32_t SS1:1; /* Channel 1 Service Status */ + uint32_t SS0:1; /* Channel 0 Service Status */ + } B; + } CSSR_A; + + union { /* ETPU_B Channel Service Status */ + uint32_t R; + struct { + uint32_t SS31:1; /* Channel 31 Service Status */ + uint32_t SS30:1; /* Channel 30 Service Status */ + uint32_t SS29:1; /* Channel 29 Service Status */ + uint32_t SS28:1; /* Channel 28 Service Status */ + uint32_t SS27:1; /* Channel 27 Service Status */ + uint32_t SS26:1; /* Channel 26 Service Status */ + uint32_t SS25:1; /* Channel 25 Service Status */ + uint32_t SS24:1; /* Channel 24 Service Status */ + uint32_t SS23:1; /* Channel 23 Service Status */ + uint32_t SS22:1; /* Channel 22 Service Status */ + uint32_t SS21:1; /* Channel 21 Service Status */ + uint32_t SS20:1; /* Channel 20 Service Status */ + uint32_t SS19:1; /* Channel 19 Service Status */ + uint32_t SS18:1; /* Channel 18 Service Status */ + uint32_t SS17:1; /* Channel 17 Service Status */ + uint32_t SS16:1; /* Channel 16 Service Status */ + uint32_t SS15:1; /* Channel 15 Service Status */ + uint32_t SS14:1; /* Channel 14 Service Status */ + uint32_t SS13:1; /* Channel 13 Service Status */ + uint32_t SS12:1; /* Channel 12 Service Status */ + uint32_t SS11:1; /* Channel 11 Service Status */ + uint32_t SS10:1; /* Channel 10 Service Status */ + uint32_t SS9:1; /* Channel 9 Service Status */ + uint32_t SS8:1; /* Channel 8 Service Status */ + uint32_t SS7:1; /* Channel 7 Service Status */ + uint32_t SS6:1; /* Channel 6 Service Status */ + uint32_t SS5:1; /* Channel 5 Service Status */ + uint32_t SS4:1; /* Channel 4 Service Status */ + uint32_t SS3:1; /* Channel 3 Service Status */ + uint32_t SS2:1; /* Channel 2 Service Status */ + uint32_t SS1:1; /* Channel 1 Service Status */ + uint32_t SS0:1; /* Channel 0 Service Status */ + } B; + } CSSR_B; + + uint32_t etpu_reserved23[90]; + +/*****************************Channels********************************/ + + struct { + union { + uint32_t R; /* Channel Configuration Register */ + struct { + uint32_t CIE:1; /* Channel Interruput Enable */ + uint32_t DTRE:1; /* Data Transfer Request Enable */ + uint32_t CPR:2; /* Channel Priority */ + uint32_t:3; + uint32_t ETCS:1; /* Entry Table Condition Select */ + uint32_t:3; + uint32_t CFS:5; /* Channel Function Select */ + uint32_t ODIS:1; /* Output disable */ + uint32_t OPOL:1; /* output polarity */ + uint32_t:3; + uint32_t CPBA:11; /* Channel Parameter Base Address */ + } B; + } CR; + union { + uint32_t R; /* Channel Status Control Register */ + struct { + uint32_t CIS:1; /* Channel Interruput Status */ + uint32_t CIOS:1; /* Channel Interruput Overflow Status */ + uint32_t:6; + uint32_t DTRS:1; /* Data Transfer Status */ + uint32_t DTROS:1; /* Data Transfer Overflow Status */ + uint32_t:6; + uint32_t IPS:1; /* Input Pin State */ + uint32_t OPS:1; /* Output Pin State */ + uint32_t OBE:1; /* Output Buffer Enable */ + uint32_t:11; + uint32_t FM1:1; /* Function mode */ + uint32_t FM0:1; /* Function mode */ + } B; + } SCR; + union { + uint32_t R; /* Channel Host Service Request Register */ + struct { + uint32_t:29; /* Host Service Request */ + uint32_t HSR:3; + } B; + } HSRR; + uint32_t etpu_reserved23; + } CHAN[127]; + + }; +/****************************************************************************/ +/* MODULE : XBAR CrossBar */ +/****************************************************************************/ + struct XBAR_tag { + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR0; /* Master Priority Register for Slave Port 0 */ + + uint32_t xbar_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR0; /* General Purpose Control Register for Slave Port 0 */ + + uint32_t xbar_reserved2[59]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR1; /* Master Priority Register for Slave Port 1 */ + + uint32_t xbar_reserved3[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR1; /* General Purpose Control Register for Slave Port 1 */ + + uint32_t xbar_reserved4[123]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR3; /* Master Priority Register for Slave Port 3 */ + + uint32_t xbar_reserved5[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR3; /* General Purpose Control Register for Slave Port 3 */ + uint32_t xbar_reserved6[187]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR6; /* Master Priority Register for Slave Port 6 */ + + uint32_t xbar_reserved7[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR6; /* General Purpose Control Register for Slave Port 6 */ + + uint32_t xbar_reserved8[59]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR7; /* Master Priority Register for Slave Port 7 */ + + uint32_t xbar_reserved9[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR7; /* General Purpose Control Register for Slave Port 7 */ + + }; +/****************************************************************************/ +/* MODULE : ECSM */ +/****************************************************************************/ + struct ECSM_tag { + + uint32_t ecsm_reserved1[5]; + + uint16_t ecsm_reserved2; + + union { + uint16_t R; + } SWTCR; //Software Watchdog Timer Control + + uint8_t ecsm_reserved3[3]; + + union { + uint8_t R; + } SWTSR; //SWT Service Register + + uint8_t ecsm_reserved4[3]; + + union { + uint8_t R; + } SWTIR; //SWT Interrupt Register + + uint32_t ecsm_reserved5a[1]; + uint32_t ecsm_reserved5b[1]; + + uint32_t ecsm_reserved5c[6]; + + uint8_t ecsm_reserved6[3]; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t ERNCR:1; + uint8_t EFNCR:1; + } B; + } ECR; //ECC Configuration Register + + uint8_t mcm_reserved8[3]; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t RNCE:1; + uint8_t FNCE:1; + } B; + } ESR; //ECC Status Register + + uint16_t ecsm_reserved9; + + union { + uint16_t R; + struct { + uint16_t:6; + uint16_t FRCNCI:1; + uint16_t FR1NCI:1; + uint16_t:1; + uint16_t ERRBIT:7; + } B; + } EEGR; //ECC Error Generation Register + + uint32_t ecsm_reserved10; + + union { + uint32_t R; + struct { + uint32_t FEAR:32; + } B; + } FEAR; //Flash ECC Address Register + + uint16_t ecsm_reserved11; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t FEMR:4; + } B; + } FEMR; //Flash ECC Master Register + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROT0:1; + uint8_t PROT1:1; + uint8_t PROT2:1; + uint8_t PROT3:1; + } B; + } FEAT; //Flash ECC Attributes Register + + union { + uint32_t R; + struct { + uint32_t FEDH:32; + } B; + } FEDRH; //Flash ECC Data High Register + + union { + uint32_t R; + struct { + uint32_t FEDL:32; + } B; + } FEDRL; //Flash ECC Data Low Register + + union { + uint32_t R; + struct { + uint32_t REAR:32; + } B; + } REAR; //RAM ECC Address + + uint8_t ecsm_reserved12[2]; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t REMR:4; + } B; + } REMR; //RAM ECC Master + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROT0:1; + uint8_t PROT1:1; + uint8_t PROT2:1; + uint8_t PROT3:1; + } B; + } REAT; // RAM ECC Attributes Register + + union { + uint32_t R; + struct { + uint32_t REDH:32; + } B; + } REDRH; //RAM ECC Data High Register + + union { + uint32_t R; + struct { + uint32_t REDL:32; + } B; + } REDRL; //RAMECC Data Low Register + + }; +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + struct INTC_tag { + union { + uint32_t R; + struct { + uint32_t:26; + uint32_t VTES:1; + uint32_t:4; + uint32_t HVEN:1; + } B; + } MCR; /* Module Configuration Register */ + + int32_t INTC_reserved00; + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR; /* Current Priority Register */ + + uint32_t intc_reserved1; + + union { + uint32_t R; + struct { + uint32_t VTBA:21; + uint32_t INTVEC:9; + uint32_t:2; + } B; + } IACKR; /* Interrupt Acknowledge Register */ + + uint32_t intc_reserved2; + + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } EOIR; /* End of Interrupt Register */ + + uint32_t intc_reserved3; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t SET:1; + uint8_t CLR:1; + } B; + } SSCIR[8]; /* Software Set/Clear Interruput Register */ + + uint32_t intc_reserved4[6]; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t PRI:4; + } B; + } PSR[358]; /* Software Set/Clear Interrupt Register */ + + }; +/****************************************************************************/ +/* MODULE : EQADC */ +/****************************************************************************/ + struct EQADC_tag { + union { + uint32_t R; + struct { + uint32_t:27; + uint32_t ESSIE:2; + uint32_t:1; + uint32_t DBG:2; + } B; + } MCR; /* Module Configuration Register */ + + int32_t EQADC_reserved00; + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t NMF:26; + } B; + } NMSFR; /* Null Message Send Format Register */ + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } ETDFR; /* External Trigger Digital Filter Register */ + + union { + uint32_t R; + struct { + uint32_t CFPUSH:32; + } B; + } CFPR[6]; /* CFIFO Push Registers */ + + uint32_t eqadc_reserved1; + + uint32_t eqadc_reserved2; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RFPOP:16; + } B; + } RFPR[6]; /* Result FIFO Pop Registers */ + + uint32_t eqadc_reserved3; + + uint32_t eqadc_reserved4; + + union EQADC_CFCR_tag { + uint16_t R; + struct { + uint16_t:5; + uint16_t SSE:1; + uint16_t CFINV:1; + uint16_t:1; + uint16_t MODE:4; + uint16_t:4; + } B; + } CFCR[6]; /* CFIFO Control Registers */ + + uint32_t eqadc_reserved5; + + union EQADC_IDCR_tag { + uint16_t R; + struct { + uint16_t NCIE:1; + uint16_t TORIE:1; + uint16_t PIE:1; + uint16_t EOQIE:1; + uint16_t CFUIE:1; + uint16_t:1; + uint16_t CFFE:1; + uint16_t CFFS:1; + uint16_t:4; + uint16_t RFOIE:1; + uint16_t:1; + uint16_t RFDE:1; + uint16_t RFDS:1; + } B; + } IDCR[6]; /* Interrupt and DMA Control Registers */ + + uint32_t eqadc_reserved6; + + union EQADC_FISR_tag { + uint32_t R; + struct { + uint32_t NCF:1; + uint32_t TORF:1; + uint32_t PF:1; + uint32_t EOQF:1; + uint32_t CFUF:1; + uint32_t SSS:1; + uint32_t CFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t CFCTR:4; + uint32_t TNXTPTR:4; + uint32_t RFCTR:4; + uint32_t POPNXTPTR:4; + } B; + } FISR[6]; /* FIFO and Interrupt Status Registers */ + + uint32_t eqadc_reserved7; + + uint32_t eqadc_reserved8; + + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t TCCF:11; + } B; + } CFTCR[6]; /* CFIFO Transfer Counter Registers */ + + uint32_t eqadc_reserved9; + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:5; + uint32_t LCFTCB0:4; + uint32_t TC_LCFTCB0:11; + } B; + } CFSSR0; /* CFIFO Status Register 0 */ + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:5; + uint32_t LCFTCB1:4; + uint32_t TC_LCFTCB1:11; + } B; + } CFSSR1; /* CFIFO Status Register 1 */ + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:4; + uint32_t ECBNI:1; + uint32_t LCFTSSI:4; + uint32_t TC_LCFTSSI:11; + } B; + } CFSSR2; /* CFIFO Status Register 2 */ + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:20; + } B; + } CFSR; + + uint32_t eqadc_reserved11; + + union { + uint32_t R; + struct { + uint32_t:21; + uint32_t MDT:3; + uint32_t:4; + uint32_t BR:4; + } B; + } SSICR; /* SSI Control Register */ + + union { + uint32_t R; + struct { + uint32_t RDV:1; + uint32_t:5; + uint32_t RDATA:26; + } B; + } SSIRDR; /* SSI Recieve Data Register */ + + uint32_t eqadc_reserved12[17]; + + struct { + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved13[12]; + + } CF[6]; + + uint32_t eqadc_reserved14[32]; + + struct { + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved15[12]; + + } RF[6]; + + }; + +/* Message Formats for On-Chip ADC Operation + */ +union EQADC_CONVERSION_COMMAND_tag { + uint32_t R; + struct { + uint32_t EOQ:1; + uint32_t PAUSE:1; + uint32_t:3; + uint32_t EB:1; + uint32_t BN:1; + uint32_t CAL:1; + uint32_t MESSAGE_TAG:4; + uint32_t LST:2; + uint32_t TSR:1; + uint32_t FMT:1; + uint32_t CHANNEL_NUMBER:8; + uint32_t:8; + } B; +}; /* Conversion command */ + +union EQADC_WRITE_CONFIGURATION_COMMAND_tag { + uint32_t R; + struct { + uint32_t EOQ:1; + uint32_t PAUSE:1; + uint32_t:3; + uint32_t EB:1; + uint32_t BN:1; + uint32_t RW:1; + uint32_t VALUE:16; + uint32_t ADDR:8; + } B; +}; /* Write configuration command */ + +/****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + struct DSPI_tag { + union DSPI_MCR_tag { + uint32_t R; + struct { + uint32_t MSTR:1; + uint32_t CONT_SCKE:1; + uint32_t DCONF:2; + uint32_t FRZ:1; + uint32_t MTFE:1; + uint32_t PCSSE:1; + uint32_t ROOE:1; + uint32_t:2; + uint32_t PCSIS5:1; + uint32_t PCSIS4:1; + uint32_t PCSIS3:1; + uint32_t PCSIS2:1; + uint32_t PCSIS1:1; + uint32_t PCSIS0:1; + uint32_t DOZE:1; + uint32_t MDIS:1; + uint32_t DIS_TXF:1; + uint32_t DIS_RXF:1; + uint32_t CLR_TXF:1; + uint32_t CLR_RXF:1; + uint32_t SMPL_PT:2; + uint32_t:7; + uint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t dspi_reserved1; + + union { + uint32_t R; + struct { + uint32_t TCNT:16; + uint32_t:16; + } B; + } TCR; + + union DSPI_CTAR_tag { + uint32_t R; + struct { + uint32_t DBR:1; + uint32_t FMSZ:4; + uint32_t CPOL:1; + uint32_t CPHA:1; + uint32_t LSBFE:1; + uint32_t PCSSCK:2; + uint32_t PASC:2; + uint32_t PDT:2; + uint32_t PBR:2; + uint32_t CSSCK:4; + uint32_t ASC:4; + uint32_t DT:4; + uint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers */ + + union DSPI_SR_tag { + uint32_t R; + struct { + uint32_t TCF:1; + uint32_t TXRXS:1; + uint32_t:1; + uint32_t EOQF:1; + uint32_t TFUF:1; + uint32_t:1; + uint32_t TFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t TXCTR:4; + uint32_t TXNXTPTR:4; + uint32_t RXCTR:4; + uint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register */ + + union DSPI_RSER_tag { + uint32_t R; + struct { + uint32_t TCFRE:1; + uint32_t:2; + uint32_t EOQFRE:1; + uint32_t TFUFRE:1; + uint32_t:1; + uint32_t TFFFRE:1; + uint32_t TFFFDIRS:1; + uint32_t:4; + uint32_t RFOFRE:1; + uint32_t:1; + uint32_t RFDFRE:1; + uint32_t RFDFDIRS:1; + uint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register */ + + union DSPI_PUSHR_tag { + uint32_t R; + struct { + uint32_t CONT:1; + uint32_t CTAS:3; + uint32_t EOQ:1; + uint32_t CTCNT:1; + uint32_t:4; + uint32_t PCS5:1; + uint32_t PCS4:1; + uint32_t PCS3:1; + uint32_t PCS2:1; + uint32_t PCS1:1; + uint32_t PCS0:1; + uint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register */ + + union DSPI_POPR_tag { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register */ + + union { + uint32_t R; + struct { + uint32_t TXCMD:16; + uint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_txf[12]; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_rxf[12]; + + union { + uint32_t R; + struct { + uint32_t MTOE:1; + uint32_t:1; + uint32_t MTOCNT:6; + uint32_t:4; + uint32_t TXSS:1; + uint32_t TPOL:1; + uint32_t TRRE:1; + uint32_t CID:1; + uint32_t DCONT:1; + uint32_t DSICTAS:3; + uint32_t:6; + uint32_t DPCS5:1; + uint32_t DPCS4:1; + uint32_t DPCS3:1; + uint32_t DPCS2:1; + uint32_t DPCS1:1; + uint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t SER_DATA:16; + } B; + } SDR; /* DSI Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t ASER_DATA:16; + } B; + } ASDR; /* DSI Alternate Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t COMP_DATA:16; + } B; + } COMPR; /* DSI Transmit Comparison Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t DESER_DATA:16; + } B; + } DDR; /* DSI deserialization Data Register */ + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_tag { + union ESCI_CR1_tag { + uint32_t R; + struct { + uint32_t:3; + uint32_t SBR:13; + uint32_t LOOPS:1; + uint32_t SCISDOZ:1; + uint32_t RSRC:1; + uint32_t M:1; + uint32_t WAKE:1; + uint32_t ILT:1; + uint32_t PE:1; + uint32_t PT:1; + uint32_t TIE:1; + uint32_t TCIE:1; + uint32_t RIE:1; + uint32_t ILIE:1; + uint32_t TE:1; + uint32_t RE:1; + uint32_t RWU:1; + uint32_t SBK:1; + } B; + } CR1; /* Control Register 1 */ + + union ESCI_CR2_tag { + uint16_t R; + struct { + uint16_t MDIS:1; + uint16_t FBR:1; + uint16_t BSTP:1; + uint16_t IEBERR:1; + uint16_t RXDMA:1; + uint16_t TXDMA:1; + uint16_t BRK13:1; + uint16_t:1; + uint16_t BESM13:1; + uint16_t SBSTP:1; + uint16_t:2; + uint16_t ORIE:1; + uint16_t NFIE:1; + uint16_t FEIE:1; + uint16_t PFIE:1; + } B; + } CR2; /* Control Register 2 */ + + union ESCI_DR_tag { + uint16_t R; + struct { + uint16_t R8:1; + uint16_t T8:1; + uint16_t:6; + uint8_t D; + } B; + } DR; /* Data Register */ + + union ESCI_SR_tag { + uint32_t R; + struct { + uint32_t TDRE:1; + uint32_t TC:1; + uint32_t RDRF:1; + uint32_t IDLE:1; + uint32_t OR:1; + uint32_t NF:1; + uint32_t FE:1; + uint32_t PF:1; + uint32_t:3; + uint32_t BERR:1; + uint32_t:3; + uint32_t RAF:1; + uint32_t RXRDY:1; + uint32_t TXRDY:1; + uint32_t LWAKE:1; + uint32_t STO:1; + uint32_t PBERR:1; + uint32_t CERR:1; + uint32_t CKERR:1; + uint32_t FRC:1; + uint32_t:7; + uint32_t OVFL:1; + } B; + } SR; /* Status Register */ + + union { + uint32_t R; + struct { + uint32_t LRES:1; + uint32_t WU:1; + uint32_t WUD0:1; + uint32_t WUD1:1; + uint32_t LDBG:1; + uint32_t DSF:1; + uint32_t PRTY:1; + uint32_t LIN:1; + uint32_t RXIE:1; + uint32_t TXIE:1; + uint32_t WUIE:1; + uint32_t STIE:1; + uint32_t PBIE:1; + uint32_t CIE:1; + uint32_t CKIE:1; + uint32_t FCIE:1; + uint32_t:7; + uint32_t OFIE:1; + uint32_t:8; + } B; + } LCR; /* LIN Control Register */ + + union { + uint32_t R; + } LTR; /* LIN Transmit Register */ + + union { + uint32_t R; + } LRR; /* LIN Recieve Register */ + + union { + uint32_t R; + } LPR; /* LIN CRC Polynom Register */ + + }; +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + struct FLEXCAN2_tag { + union { + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t:1; + uint32_t HALT:1; + uint32_t NOTRDY:1; + uint32_t:1; + uint32_t SOFTRST:1; + uint32_t FRZACK:1; + uint32_t:1; + uint32_t:1; + + uint32_t:1; + + uint32_t MDISACK:1; + uint32_t:1; + uint32_t:1; + + uint32_t:12; + + uint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t PRESDIV:8; + uint32_t RJW:2; + uint32_t PSEG1:3; + uint32_t PSEG2:3; + uint32_t BOFFMSK:1; + uint32_t ERRMSK:1; + uint32_t CLKSRC:1; + uint32_t LPB:1; + + uint32_t:4; + + uint32_t SMP:1; + uint32_t BOFFREC:1; + uint32_t TSYN:1; + uint32_t LBUF:1; + uint32_t LOM:1; + uint32_t PROPSEG:3; + } B; + } CR; /* Control Register */ + + union { + uint32_t R; + } TIMER; /* Free Running Timer */ + int32_t FLEXCAN_reserved00; + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXECNT:8; + uint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + uint32_t R; + struct { + uint32_t:14; + + uint32_t:2; + + uint32_t BIT1ERR:1; + uint32_t BIT0ERR:1; + uint32_t ACKERR:1; + uint32_t CRCERR:1; + uint32_t FRMERR:1; + uint32_t STFERR:1; + uint32_t TXWRN:1; + uint32_t RXWRN:1; + uint32_t IDLE:1; + uint32_t TXRX:1; + uint32_t FLTCONF:2; + uint32_t:1; + uint32_t BOFFINT:1; + uint32_t ERRINT:1; + uint32_t:1; + } B; + } ESR; /* Error and Status Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63M:1; + uint32_t BUF62M:1; + uint32_t BUF61M:1; + uint32_t BUF60M:1; + uint32_t BUF59M:1; + uint32_t BUF58M:1; + uint32_t BUF57M:1; + uint32_t BUF56M:1; + uint32_t BUF55M:1; + uint32_t BUF54M:1; + uint32_t BUF53M:1; + uint32_t BUF52M:1; + uint32_t BUF51M:1; + uint32_t BUF50M:1; + uint32_t BUF49M:1; + uint32_t BUF48M:1; + uint32_t BUF47M:1; + uint32_t BUF46M:1; + uint32_t BUF45M:1; + uint32_t BUF44M:1; + uint32_t BUF43M:1; + uint32_t BUF42M:1; + uint32_t BUF41M:1; + uint32_t BUF40M:1; + uint32_t BUF39M:1; + uint32_t BUF38M:1; + uint32_t BUF37M:1; + uint32_t BUF36M:1; + uint32_t BUF35M:1; + uint32_t BUF34M:1; + uint32_t BUF33M:1; + uint32_t BUF32M:1; + } B; + } IMRH; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31M:1; + uint32_t BUF30M:1; + uint32_t BUF29M:1; + uint32_t BUF28M:1; + uint32_t BUF27M:1; + uint32_t BUF26M:1; + uint32_t BUF25M:1; + uint32_t BUF24M:1; + uint32_t BUF23M:1; + uint32_t BUF22M:1; + uint32_t BUF21M:1; + uint32_t BUF20M:1; + uint32_t BUF19M:1; + uint32_t BUF18M:1; + uint32_t BUF17M:1; + uint32_t BUF16M:1; + uint32_t BUF15M:1; + uint32_t BUF14M:1; + uint32_t BUF13M:1; + uint32_t BUF12M:1; + uint32_t BUF11M:1; + uint32_t BUF10M:1; + uint32_t BUF09M:1; + uint32_t BUF08M:1; + uint32_t BUF07M:1; + uint32_t BUF06M:1; + uint32_t BUF05M:1; + uint32_t BUF04M:1; + uint32_t BUF03M:1; + uint32_t BUF02M:1; + uint32_t BUF01M:1; + uint32_t BUF00M:1; + } B; + } IMRL; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63I:1; + uint32_t BUF62I:1; + uint32_t BUF61I:1; + uint32_t BUF60I:1; + uint32_t BUF59I:1; + uint32_t BUF58I:1; + uint32_t BUF57I:1; + uint32_t BUF56I:1; + uint32_t BUF55I:1; + uint32_t BUF54I:1; + uint32_t BUF53I:1; + uint32_t BUF52I:1; + uint32_t BUF51I:1; + uint32_t BUF50I:1; + uint32_t BUF49I:1; + uint32_t BUF48I:1; + uint32_t BUF47I:1; + uint32_t BUF46I:1; + uint32_t BUF45I:1; + uint32_t BUF44I:1; + uint32_t BUF43I:1; + uint32_t BUF42I:1; + uint32_t BUF41I:1; + uint32_t BUF40I:1; + uint32_t BUF39I:1; + uint32_t BUF38I:1; + uint32_t BUF37I:1; + uint32_t BUF36I:1; + uint32_t BUF35I:1; + uint32_t BUF34I:1; + uint32_t BUF33I:1; + uint32_t BUF32I:1; + } B; + } IFRH; /* Interruput Flag Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31I:1; + uint32_t BUF30I:1; + uint32_t BUF29I:1; + uint32_t BUF28I:1; + uint32_t BUF27I:1; + uint32_t BUF26I:1; + uint32_t BUF25I:1; + uint32_t BUF24I:1; + uint32_t BUF23I:1; + uint32_t BUF22I:1; + uint32_t BUF21I:1; + uint32_t BUF20I:1; + uint32_t BUF19I:1; + uint32_t BUF18I:1; + uint32_t BUF17I:1; + uint32_t BUF16I:1; + uint32_t BUF15I:1; + uint32_t BUF14I:1; + uint32_t BUF13I:1; + uint32_t BUF12I:1; + uint32_t BUF11I:1; + uint32_t BUF10I:1; + uint32_t BUF09I:1; + uint32_t BUF08I:1; + uint32_t BUF07I:1; + uint32_t BUF06I:1; + uint32_t BUF05I:1; + uint32_t BUF04I:1; + uint32_t BUF03I:1; + uint32_t BUF02I:1; + uint32_t BUF01I:1; + uint32_t BUF00I:1; + } B; + } IFRL; /* Interruput Flag Register */ + + uint32_t flexcan2_reserved2[19]; + + struct canbuf_t { + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t CODE:4; + uint32_t:1; + uint32_t SRR:1; + uint32_t IDE:1; + uint32_t RTR:1; + uint32_t LENGTH:4; + uint32_t TIMESTAMP:16; + } B; + } CS; + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t STD_ID:11; + uint32_t EXT_ID:18; + } B; + } ID; + + union { + uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + uint32_t W[2]; /* Data buffer in words (32 bits) */ + uint32_t R[2]; /* Data buffer in words (32 bits) */ + } DATA; + + } BUF[64]; + }; + +/* Define memories */ + +#define SRAM_START 0x40000000 +#define SRAM_SIZE 0x10000 +#define SRAM_END 0x4000FFFF + +#define FLASH_START 0x0 +#define FLASH_SIZE 0x200000 +#define FLASH_END 0x1FFFFF + +/* Define instances of modules */ +#define PBRIDGE_A (*(volatile struct PBRIDGE_A_tag *) 0xC3F00000) +#define FMPLL (*(volatile struct FMPLL_tag *) 0xC3F80000) +#define EBI (*(volatile struct EBI_tag *) 0xC3F84000) +#define FLASH (*(volatile struct FLASH_tag *) 0xC3F88000) +#define SIU (*(volatile struct SIU_tag *) 0xC3F90000) + +#define EMIOS (*(volatile struct EMIOS_tag *) 0xC3FA0000) +#define ETPU (*(volatile struct ETPU_tag *) 0xC3FC0000) +#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) +#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) +#define ETPU_DATA_RAM_END 0xC3FC8BFC +#define CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) + +#define PBRIDGE_B (*(volatile struct PBRIDGE_B_tag *) 0xFFF00000) +#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000) +#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000) +#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000) +#define INTC (*(volatile struct INTC_tag *) 0xFFF48000) + +#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000) + +#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000) +#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000) +#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000) +#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000) + +#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFB0000) +#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFB4000) + +#define CAN_A (*(volatile struct FLEXCAN2_tag *) 0xFFFC0000) +#define CAN_B (*(volatile struct FLEXCAN2_tag *) 0xFFFC4000) +#define CAN_C (*(volatile struct FLEXCAN2_tag *) 0xFFFC8000) + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ +#endif /* ifdef _MPC5554_H */ +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ diff --git a/bsps/powerpc/include/mpc55xx/fsl-mpc556x.h b/bsps/powerpc/include/mpc55xx/fsl-mpc556x.h new file mode 100644 index 0000000000..41ad83729a --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/fsl-mpc556x.h @@ -0,0 +1,4563 @@ +/* + * Modifications of the original file provided by Freescale are: + * + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/**************************************************************************/ +/* FILE NAME: mpc5567.h COPYRIGHT (c) Freescale 2007 */ +/* VERSION: 1.5 All Rights Reserved */ +/* */ +/* DESCRIPTION: */ +/* This file contain all of the register and bit field definitions for */ +/* MPC5567. */ +/*========================================================================*/ +/* UPDATE HISTORY */ +/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ +/* --- ----------- --------- --------------------- */ +/* 1.0 G. Emerson 03/Jan/06 Initial version. */ +/* 1.1 G. Emerson 27/Mar/06 Fix issue with Flexcan BCC field. */ +/* 1.2 S. Mathieson 28/Jul/06 Change Flexcan BCC bit to MBFEN */ +/* Add Flexcan bits WRNEN, SRXDIS, */ +/* TWRNMSK, RWRNMSK,TWRNINT,RWRNINT */ +/* 1.3 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */ +/* to DPB to align with documentation. */ +/* 1.4 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */ +/* alternate configuration. */ +/* INTC, correction to the number of PSR */ +/* registers. */ +/* Updates to bitfield sizes in MBSSUTR, */ +/* MBIVEC, MBIDX & RSBIR. RSBIR, SELEC */ +/* changed to SEL & RFRFCFR, FNUM changed */ +/* to SEL to align with documentation. */ +/* Various register/ bitfield updates to */ +/* correct errors (MCR, TMODE bit removed.*/ +/* PADR register removed. PIER1, DRDIE bit*/ +/* removed & PIFR1, DRDIF removed. PCR1, */ +/* Filter bypass bit removed). */ +/* 1.5 S. Mathieson 25/Apr/07 SRAM size changed from 64K to 80K. */ +/* */ +/**************************************************************************/ +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +#ifndef _MPC5567_H_ +#define _MPC5567_H_ + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/****************************************************************************/ +/* MODULE : PBRIDGE_A Peripheral Bridge */ +/****************************************************************************/ + struct PBRIDGE_A_tag { + union { + uint32_t R; + struct { + uint32_t MBW0:1; + uint32_t MTR0:1; + uint32_t MTW0:1; + uint32_t MPL0:1; + uint32_t MBW1:1; + uint32_t MTR1:1; + uint32_t MTW1:1; + uint32_t MPL1:1; + uint32_t MBW2:1; + uint32_t MTR2:1; + uint32_t MTW2:1; + uint32_t MPL2:1; + uint32_t MBW3:1; + uint32_t MTR3:1; + uint32_t MTW3:1; + uint32_t MPL3:1; + + uint32_t MBW4:1; /* FEC */ + uint32_t MTR4:1; + uint32_t MTW4:1; + uint32_t MPL4:1; + + uint32_t:4; + + uint32_t MBW6:1; /* FLEXRAY */ + uint32_t MTR6:1; + uint32_t MTW6:1; + uint32_t MPL6:1; + + uint32_t:4; + } B; + } MPCR; /* Master Privilege Control Register */ + + uint32_t pbridge_a_reserved2[7]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:28; + } B; + } PACR0; + + uint32_t pbridge_a_reserved3[7]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t:4; + uint32_t BW4:1; + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:12; + } B; + } OPACR0; + + union { + uint32_t R; + struct { + + uint32_t BW0:1; /* EMIOS */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + + uint32_t:28; + } B; + } OPACR1; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:4; + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t BW3:1; + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + uint32_t BW4:1; + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:12; + } B; + } OPACR2; + + }; + +/****************************************************************************/ +/* MODULE : PBRIDGE_B Peripheral Bridge */ +/****************************************************************************/ + struct PBRIDGE_B_tag { + union { + uint32_t R; + struct { + uint32_t MBW0:1; + uint32_t MTR0:1; + uint32_t MTW0:1; + uint32_t MPL0:1; + uint32_t MBW1:1; + uint32_t MTR1:1; + uint32_t MTW1:1; + uint32_t MPL1:1; + uint32_t MBW2:1; + uint32_t MTR2:1; + uint32_t MTW2:1; + uint32_t MPL2:1; + uint32_t MBW3:1; + uint32_t MTR3:1; + uint32_t MTW3:1; + uint32_t MPL3:1; + + uint32_t MBW4:1; /* FEC */ + uint32_t MTR4:1; + uint32_t MTW4:1; + uint32_t MPL4:1; + + uint32_t:4; + + uint32_t MBW6:1; /* FLEXRAY */ + uint32_t MTR6:1; + uint32_t MTW6:1; + uint32_t MPL6:1; + + uint32_t:4; + } B; + } MPCR; /* Master Privilege Control Register */ + + uint32_t pbridge_b_reserved2[7]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t:24; + } B; + } PACR0; + + uint32_t pbridge_b_reserved3; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + + uint32_t BW3:1; /* FEC */ + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + + uint32_t:16; + + } B; + } PACR2; + + uint32_t pbridge_b_reserved4[5]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:12; + + uint32_t:4; + + uint32_t BW5:1; /* DSPI_B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + + uint32_t BW6:1; + uint32_t SP6:1; + uint32_t WP6:1; + uint32_t TP6:1; + uint32_t BW7:1; + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR0; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t BW4:1; + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + + uint32_t BW5:1; /* ESCI_B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + + uint32_t:8; + } B; + } OPACR1; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + + uint32_t BW1:1; /* CAN_B */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + + uint32_t BW3:1; /* CAN_D */ + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + + uint32_t BW4:1; /* CAN_E */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + + uint32_t:12; + } B; + } OPACR2; + + union { + uint32_t R; + struct { + + uint32_t BW0:1; /* FLEXRAY */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + + uint32_t:24; + uint32_t BW7:1; + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR3; + + }; +/****************************************************************************/ +/* MODULE : FMPLL */ +/****************************************************************************/ + struct FMPLL_tag { + union FMPLL_SYNCR_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t PREDIV:3; + uint32_t MFD:5; + uint32_t:1; + uint32_t RFD:3; + uint32_t LOCEN:1; + uint32_t LOLRE:1; + uint32_t LOCRE:1; + uint32_t DISCLK:1; + uint32_t LOLIRQ:1; + uint32_t LOCIRQ:1; + uint32_t RATE:1; + uint32_t DEPTH:2; + uint32_t EXP:10; + } B; + } SYNCR; + + union FMPLL_SYNSR_tag { + uint32_t R; + struct { + uint32_t:22; + uint32_t LOLF:1; + uint32_t LOC:1; + uint32_t MODE:1; + uint32_t PLLSEL:1; + uint32_t PLLREF:1; + uint32_t LOCKS:1; + uint32_t LOCK:1; + uint32_t LOCF:1; + uint32_t CALDONE:1; + uint32_t CALPASS:1; + } B; + } SYNSR; + + }; +/****************************************************************************/ +/* MODULE : External Bus Interface (EBI) */ +/****************************************************************************/ + struct EBI_CS_tag { + union { /* Base Register Bank */ + uint32_t R; + struct { + uint32_t BA:17; + uint32_t:3; + uint32_t PS:1; + uint32_t:4; + uint32_t BL:1; + uint32_t WEBS:1; + uint32_t TBDIP:1; + uint32_t:2; + uint32_t BI:1; + uint32_t V:1; + } B; + } BR; + + union { /* Option Register Bank */ + uint32_t R; + struct { + uint32_t AM:17; + uint32_t:7; + uint32_t SCY:4; + uint32_t:1; + uint32_t BSCY:2; + uint32_t:1; + } B; + } OR; + }; + + struct EBI_CAL_CS_tag { + union { /* Calibration Base Register Bank */ + uint32_t R; + struct { + uint32_t BA:17; + uint32_t:3; + uint32_t PS:1; + uint32_t:4; + uint32_t BL:1; + uint32_t WEBS:1; + uint32_t TBDIP:1; + uint32_t:2; + uint32_t BI:1; + uint32_t V:1; + } B; + } BR; + + union { /* Calibration Option Register Bank */ + uint32_t R; + struct { + uint32_t AM:17; + uint32_t:7; + uint32_t SCY:4; + uint32_t:1; + uint32_t BSCY:2; + uint32_t:1; + } B; + } OR; + }; + + struct EBI_tag { + union EBI_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:5; + uint32_t SIZEEN:1; + uint32_t SIZE:2; + uint32_t:8; + uint32_t ACGE:1; + uint32_t EXTM:1; + uint32_t EARB:1; + uint32_t EARP:2; + uint32_t:4; + uint32_t MDIS:1; + uint32_t:5; + uint32_t DBM:1; + } B; + } MCR; + + uint32_t EBI_reserved1; + + union { /* Transfer Error Status Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t TEAF:1; + uint32_t BMTF:1; + } B; + } TESR; + + union { /* Bus Monitor Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t BMT:8; + uint32_t BME:1; + uint32_t:7; + } B; + } BMCR; + + struct EBI_CS_tag CS[4]; + +/* Calibration registers */ + uint32_t EBI_reserved2[4]; + struct EBI_CAL_CS_tag CAL_CS[4]; + + }; +/****************************************************************************/ +/* MODULE : FLASH */ +/****************************************************************************/ + struct FLASH_tag { + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:4; + uint32_t SIZE:4; + uint32_t:1; + uint32_t LAS:3; + uint32_t:3; + uint32_t MAS:1; + uint32_t EER:1; + uint32_t RWE:1; + uint32_t BBEPE:1; + uint32_t EPE:1; + uint32_t PEAS:1; + uint32_t DONE:1; + uint32_t PEG:1; + + uint32_t:2; + + uint32_t STOP:1; + uint32_t:1; + uint32_t PGM:1; + uint32_t PSUS:1; + uint32_t ERS:1; + uint32_t ESUS:1; + uint32_t EHV:1; + } B; + } MCR; + + union LMLR_tag { /* LML Register */ + uint32_t R; + struct { + uint32_t LME:1; + uint32_t:10; + uint32_t SLOCK:1; + uint32_t MLOCK:4; + uint32_t LLOCK:16; + } B; + } LMLR; + + union HLR_tag { /* HL Register */ + uint32_t R; + struct { + uint32_t HBE:1; + uint32_t:3; + uint32_t HBLOCK:28; + } B; + } HLR; + + union SLMLR_tag { /* SLML Register */ + uint32_t R; + struct { + uint32_t SLE:1; + uint32_t:10; + uint32_t SSLOCK:1; + uint32_t SMLOCK:4; + uint32_t SLLOCK:16; + } B; + } SLMLR; + + union { /* LMS Register */ + uint32_t R; + struct { + uint32_t:12; + uint32_t MSEL:4; + uint32_t LSEL:16; + } B; + } LMSR; + + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t HBSEL:28; + } B; + } HSR; + + union { + uint32_t R; + struct { + uint32_t:10; + uint32_t ADDR:19; + uint32_t:3; + } B; + } AR; + + union { + uint32_t R; + struct { + + uint32_t:9; + uint32_t M6PFE:1; /* Flexray */ + uint32_t:1; + + uint32_t M4PFE:1; /* FEC */ + + uint32_t M3PFE:1; + uint32_t M2PFE:1; + uint32_t M1PFE:1; + uint32_t M0PFE:1; + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + + uint32_t DPFEN:2; + uint32_t IPFEN:2; + + uint32_t PFLIM:3; + uint32_t BFEN:1; + } B; + } BIUCR; + + union { + uint32_t R; + struct { + + uint32_t:18; + uint32_t M6AP:2; /* Flexray */ + uint32_t:2; + + uint32_t M4AP:2; /* FEC */ + + uint32_t M3AP:2; + uint32_t M2AP:2; + uint32_t M1AP:2; + uint32_t M0AP:2; + } B; + } BIUAPR; + }; +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + int32_t SIU_reserved0; + + union { /* MCU ID Register */ + uint32_t R; + struct { + uint32_t PARTNUM:16; + uint32_t MASKNUM:16; + } B; + } MIDR; + int32_t SIU_reserved00; + + union { /* Reset Status Register */ + uint32_t R; + struct { + uint32_t PORS:1; + uint32_t ERS:1; + uint32_t LLRS:1; + uint32_t LCRS:1; + uint32_t WDRS:1; + uint32_t CRS:1; + uint32_t:8; + uint32_t SSRS:1; + uint32_t SERF:1; + uint32_t WKPCFG:1; + uint32_t:12; + uint32_t BOOTCFG:2; + uint32_t RGF:1; + } B; + } RSR; + + union { /* System Reset Control Register */ + uint32_t R; + struct { + uint32_t SSR:1; + uint32_t SER:1; + uint32_t:14; + uint32_t CRE:1; + uint32_t:15; + } B; + } SRCR; + + union SIU_EISR_tag { /* External Interrupt Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t EIF15:1; + uint32_t EIF14:1; + uint32_t EIF13:1; + uint32_t EIF12:1; + uint32_t EIF11:1; + uint32_t EIF10:1; + uint32_t EIF9:1; + uint32_t EIF8:1; + uint32_t EIF7:1; + uint32_t EIF6:1; + uint32_t EIF5:1; + uint32_t EIF4:1; + uint32_t EIF3:1; + uint32_t EIF2:1; + uint32_t EIF1:1; + uint32_t EIF0:1; + } B; + } EISR; + + union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t EIRE15:1; + uint32_t EIRE14:1; + uint32_t EIRE13:1; + uint32_t EIRE12:1; + uint32_t EIRE11:1; + uint32_t EIRE10:1; + uint32_t EIRE9:1; + uint32_t EIRE8:1; + uint32_t EIRE7:1; + uint32_t EIRE6:1; + uint32_t EIRE5:1; + uint32_t EIRE4:1; + uint32_t EIRE3:1; + uint32_t EIRE2:1; + uint32_t EIRE1:1; + uint32_t EIRE0:1; + } B; + } DIRER; + + union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DIRS3:1; + uint32_t DIRS2:1; + uint32_t DIRS1:1; + uint32_t DIRS0:1; + } B; + } DIRSR; + + union { /* Overrun Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t OVF15:1; + uint32_t OVF14:1; + uint32_t OVF13:1; + uint32_t OVF12:1; + uint32_t OVF11:1; + uint32_t OVF10:1; + uint32_t OVF9:1; + uint32_t OVF8:1; + uint32_t OVF7:1; + uint32_t OVF6:1; + uint32_t OVF5:1; + uint32_t OVF4:1; + uint32_t OVF3:1; + uint32_t OVF2:1; + uint32_t OVF1:1; + uint32_t OVF0:1; + } B; + } OSR; + + union SIU_ORER_tag { /* Overrun Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ORE15:1; + uint32_t ORE14:1; + uint32_t ORE13:1; + uint32_t ORE12:1; + uint32_t ORE11:1; + uint32_t ORE10:1; + uint32_t ORE9:1; + uint32_t ORE8:1; + uint32_t ORE7:1; + uint32_t ORE6:1; + uint32_t ORE5:1; + uint32_t ORE4:1; + uint32_t ORE3:1; + uint32_t ORE2:1; + uint32_t ORE1:1; + uint32_t ORE0:1; + } B; + } ORER; + + union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t IREE15:1; + uint32_t IREE14:1; + uint32_t IREE13:1; + uint32_t IREE12:1; + uint32_t IREE11:1; + uint32_t IREE10:1; + uint32_t IREE9:1; + uint32_t IREE8:1; + uint32_t IREE7:1; + uint32_t IREE6:1; + uint32_t IREE5:1; + uint32_t IREE4:1; + uint32_t IREE3:1; + uint32_t IREE2:1; + uint32_t IREE1:1; + uint32_t IREE0:1; + } B; + } IREER; + + union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t IFEE15:1; + uint32_t IFEE14:1; + uint32_t IFEE13:1; + uint32_t IFEE12:1; + uint32_t IFEE11:1; + uint32_t IFEE10:1; + uint32_t IFEE9:1; + uint32_t IFEE8:1; + uint32_t IFEE7:1; + uint32_t IFEE6:1; + uint32_t IFEE5:1; + uint32_t IFEE4:1; + uint32_t IFEE3:1; + uint32_t IFEE2:1; + uint32_t IFEE1:1; + uint32_t IFEE0:1; + } B; + } IFEER; + + union SIU_IDFR_tag { /* External IRQ Digital Filter Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } IDFR; + + int32_t SIU_reserved1[3]; + + union SIU_PCR_tag { /* Pad Configuration Registers */ + uint16_t R; + struct { + uint16_t:3; + uint16_t PA:3; + uint16_t OBE:1; + uint16_t IBE:1; + uint16_t DSC:2; + uint16_t ODE:1; + uint16_t HYS:1; + uint16_t SRC:2; + uint16_t WPE:1; + uint16_t WPS:1; + } B; + } PCR[512]; + + int16_t SIU_reserved_0[224]; + + union { /* GPIO Pin Data Output Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDO:1; + } B; + } GPDO[256]; + + int32_t SIU_reserved_3[64]; + + union { /* GPIO Pin Data Input Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; + } B; + } GPDI[256]; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t TSEL5:2; + uint32_t TSEL4:2; + uint32_t TSEL3:2; + uint32_t TSEL2:2; + uint32_t TSEL1:2; + uint32_t TSEL0:2; + uint32_t:20; + } B; + } ETISR; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } EIISR; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t SINSELA:2; + uint32_t SSSELA:2; + uint32_t SCKSELA:2; + uint32_t TRIGSELA:2; + uint32_t SINSELB:2; + uint32_t SSSELB:2; + uint32_t SCKSELB:2; + uint32_t TRIGSELB:2; + uint32_t SINSELC:2; + uint32_t SSSELC:2; + uint32_t SCKSELC:2; + uint32_t TRIGSELC:2; + uint32_t SINSELD:2; + uint32_t SSSELD:2; + uint32_t SCKSELD:2; + uint32_t TRIGSELD:2; + } B; + } DISR; + + int32_t SIU_reserved2[29]; + + union { /* Chip Configuration Register Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MATCH:1; + uint32_t DISNEX:1; + uint32_t:16; + } B; + } CCR; + + union { /* External Clock Configuration Register Register */ + uint32_t R; + struct { + uint32_t:18; + uint32_t ENGDIV:6; + uint32_t:4; + uint32_t EBTS:1; + uint32_t:1; + uint32_t EBDF:2; + } B; + } ECCR; + + union { + uint32_t R; + } CARH; + + union { + uint32_t R; + } CARL; + + union { + uint32_t R; + } CBRH; + + union { + uint32_t R; + } CBRL; + + }; +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + struct EMIOS_tag { + union EMIOS_MCR_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t GTBE:1; + uint32_t ETB:1; + uint32_t GPREN:1; + uint32_t:6; + uint32_t SRV:4; + uint32_t GPRE:8; + uint32_t:8; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t F23:1; + uint32_t F22:1; + uint32_t F21:1; + uint32_t F20:1; + uint32_t F19:1; + uint32_t F18:1; + uint32_t F17:1; + uint32_t F16:1; + uint32_t F15:1; + uint32_t F14:1; + uint32_t F13:1; + uint32_t F12:1; + uint32_t F11:1; + uint32_t F10:1; + uint32_t F9:1; + uint32_t F8:1; + uint32_t F7:1; + uint32_t F6:1; + uint32_t F5:1; + uint32_t F4:1; + uint32_t F3:1; + uint32_t F2:1; + uint32_t F1:1; + uint32_t F0:1; + } B; + } GFR; /* Global FLAG Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t OU23:1; + uint32_t OU22:1; + uint32_t OU21:1; + uint32_t OU20:1; + uint32_t OU19:1; + uint32_t OU18:1; + uint32_t OU17:1; + uint32_t OU16:1; + uint32_t OU15:1; + uint32_t OU14:1; + uint32_t OU13:1; + uint32_t OU12:1; + uint32_t OU11:1; + uint32_t OU10:1; + uint32_t OU9:1; + uint32_t OU8:1; + uint32_t OU7:1; + uint32_t OU6:1; + uint32_t OU5:1; + uint32_t OU4:1; + uint32_t OU3:1; + uint32_t OU2:1; + uint32_t OU1:1; + uint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register */ + + uint32_t emios_reserved[5]; + + struct EMIOS_CH_tag { + union { + uint32_t R; /* Channel A Data Register */ + } CADR; + + union { + uint32_t R; /* Channel B Data Register */ + } CBDR; + + union { + uint32_t R; /* Channel Counter Register */ + } CCNTR; + + union EMIOS_CCR_tag { + uint32_t R; + struct { + uint32_t FREN:1; + uint32_t ODIS:1; + uint32_t ODISSL:2; + uint32_t UCPRE:2; + uint32_t UCPREN:1; + uint32_t DMA:1; + uint32_t:1; + uint32_t IF:4; + uint32_t FCK:1; + uint32_t FEN:1; + uint32_t:3; + uint32_t FORCMA:1; + uint32_t FORCMB:1; + uint32_t:1; + uint32_t BSL:2; + uint32_t EDSEL:1; + uint32_t EDPOL:1; + uint32_t MODE:7; + } B; + } CCR; /* Channel Control Register */ + + union EMIOS_CSR_tag { + uint32_t R; + struct { + uint32_t OVR:1; + uint32_t:15; + uint32_t OVFL:1; + uint32_t:12; + uint32_t UCIN:1; + uint32_t UCOUT:1; + uint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register */ + + union { + uint32_t R; /* Alternate Channel A Data Register */ + } ALTCADR; + + uint32_t emios_channel_reserved[2]; + + } CH[24]; + + }; +/****************************************************************************/ +/* MODULE :ETPU */ +/****************************************************************************/ + +/***************************Configuration Registers**************************/ + + struct ETPU_tag { + union { /* MODULE CONFIGURATION REGISTER */ + uint32_t R; + struct { + uint32_t GEC:1; /* Global Exception Clear */ + uint32_t:3; + uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */ + + uint32_t:1; /* For single ETPU implementations */ + + uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */ + + uint32_t:1; /* For single ETPU implementations */ + + uint32_t:3; + uint32_t SCMSIZE:5; /* Shared Code Memory size */ + uint32_t:5; + uint32_t SCMMISF:1; /* SCM MISC Flag */ + uint32_t SCMMISEN:1; /* SCM MISC Enable */ + uint32_t:2; + uint32_t VIS:1; /* SCM Visability */ + uint32_t:5; + uint32_t GTBE:1; /* Global Time Base Enable */ + } B; + } MCR; + + union { /* COHERENT DUAL-PARAMETER CONTROL */ + uint32_t R; + struct { + uint32_t STS:1; /* Start Status bit */ + uint32_t CTBASE:5; /* Channel Transfer Base */ + uint32_t PBASE:10; /* Parameter Buffer Base Address */ + uint32_t PWIDTH:1; /* Parameter Width */ + uint32_t PARAM0:7; /* Channel Parameter 0 */ + uint32_t WR:1; + uint32_t PARAM1:7; /* Channel Parameter 1 */ + } B; + } CDCR; + + uint32_t etpu_reserved1; + + union { /* MISC Compare Register */ + uint32_t R; + } MISCCMPR; + + union { /* SCM off-range Date Register */ + uint32_t R; + } SCMOFFDATAR; + + union { /* ETPU_A Configuration Register */ + uint32_t R; + struct { + uint32_t FEND:1; /* Force END */ + uint32_t MDIS:1; /* Low power Stop */ + uint32_t:1; + uint32_t STF:1; /* Stop Flag */ + uint32_t:4; + uint32_t HLTF:1; /* Halt Mode Flag */ + uint32_t:4; + uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + uint32_t CDFC:2; + uint32_t:9; + uint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_A; + uint32_t etpu_reserved3; /* For single ETPU implementations */ + + uint32_t etpu_reserved4; + + union { /* ETPU_A Timebase Configuration Register */ + uint32_t R; + struct { + uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + uint32_t:1; + uint32_t AM:1; /* Angle Mode */ + uint32_t:3; + uint32_t TCR2P:6; /* TCR2 Prescaler Control */ + uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + uint32_t:6; + uint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_A; + + union { /* ETPU_A TCR1 Visibility Register */ + uint32_t R; + } TB1R_A; + + union { /* ETPU_A TCR2 Visibility Register */ + uint32_t R; + } TB2R_A; + + union { /* ETPU_A STAC Configuration Register */ + uint32_t R; + struct { + uint32_t REN1:1; /* Resource Enable TCR1 */ + uint32_t RSC1:1; /* Resource Control TCR1 */ + uint32_t:2; + uint32_t SERVER_ID1:4; + uint32_t:4; + uint32_t SRV1:4; /* Resource Server Slot */ + uint32_t REN2:1; /* Resource Enable TCR2 */ + uint32_t RSC2:1; /* Resource Control TCR2 */ + uint32_t:2; + uint32_t SERVER_ID2:4; + uint32_t:4; + uint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_A; + + uint32_t etpu_reserved5[4]; + uint32_t etpu_reserved6[4]; /* For single ETPU implementations */ + + uint32_t etpu_reserved7[108]; + +/*****************************Status and Control Registers**************************/ + + union { /* ETPU_A Channel Interrut Status */ + uint32_t R; + struct { + uint32_t CIS31:1; /* Channel 31 Interrut Status */ + uint32_t CIS30:1; /* Channel 30 Interrut Status */ + uint32_t CIS29:1; /* Channel 29 Interrut Status */ + uint32_t CIS28:1; /* Channel 28 Interrut Status */ + uint32_t CIS27:1; /* Channel 27 Interrut Status */ + uint32_t CIS26:1; /* Channel 26 Interrut Status */ + uint32_t CIS25:1; /* Channel 25 Interrut Status */ + uint32_t CIS24:1; /* Channel 24 Interrut Status */ + uint32_t CIS23:1; /* Channel 23 Interrut Status */ + uint32_t CIS22:1; /* Channel 22 Interrut Status */ + uint32_t CIS21:1; /* Channel 21 Interrut Status */ + uint32_t CIS20:1; /* Channel 20 Interrut Status */ + uint32_t CIS19:1; /* Channel 19 Interrut Status */ + uint32_t CIS18:1; /* Channel 18 Interrut Status */ + uint32_t CIS17:1; /* Channel 17 Interrut Status */ + uint32_t CIS16:1; /* Channel 16 Interrut Status */ + uint32_t CIS15:1; /* Channel 15 Interrut Status */ + uint32_t CIS14:1; /* Channel 14 Interrut Status */ + uint32_t CIS13:1; /* Channel 13 Interrut Status */ + uint32_t CIS12:1; /* Channel 12 Interrut Status */ + uint32_t CIS11:1; /* Channel 11 Interrut Status */ + uint32_t CIS10:1; /* Channel 10 Interrut Status */ + uint32_t CIS9:1; /* Channel 9 Interrut Status */ + uint32_t CIS8:1; /* Channel 8 Interrut Status */ + uint32_t CIS7:1; /* Channel 7 Interrut Status */ + uint32_t CIS6:1; /* Channel 6 Interrut Status */ + uint32_t CIS5:1; /* Channel 5 Interrut Status */ + uint32_t CIS4:1; /* Channel 4 Interrut Status */ + uint32_t CIS3:1; /* Channel 3 Interrut Status */ + uint32_t CIS2:1; /* Channel 2 Interrut Status */ + uint32_t CIS1:1; /* Channel 1 Interrut Status */ + uint32_t CIS0:1; /* Channel 0 Interrut Status */ + } B; + } CISR_A; + uint32_t etpu_reserved8; /* For single ETPU implementations */ + + uint32_t etpu_reserved9[2]; + + union { /* ETPU_A Data Transfer Request Status */ + uint32_t R; + struct { + uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_A; + uint32_t etpu_reserved10; /* For single ETPU implementations */ + + uint32_t etpu_reserved11[2]; + + union { /* ETPU_A Interruput Overflow Status */ + uint32_t R; + struct { + uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_A; + uint32_t etpu_reserved12; /* For single ETPU implementations */ + + uint32_t etpu_reserved13[2]; + + union { /* ETPU_A Data Transfer Overflow Status */ + uint32_t R; + struct { + uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_A; + uint32_t etpu_reserved14; /* For single ETPU implementations */ + + uint32_t etpu_reserved15[2]; + + union { /* ETPU_A Channel Interruput Enable */ + uint32_t R; + struct { + uint32_t CIE31:1; /* Channel 31 Interruput Enable */ + uint32_t CIE30:1; /* Channel 30 Interruput Enable */ + uint32_t CIE29:1; /* Channel 29 Interruput Enable */ + uint32_t CIE28:1; /* Channel 28 Interruput Enable */ + uint32_t CIE27:1; /* Channel 27 Interruput Enable */ + uint32_t CIE26:1; /* Channel 26 Interruput Enable */ + uint32_t CIE25:1; /* Channel 25 Interruput Enable */ + uint32_t CIE24:1; /* Channel 24 Interruput Enable */ + uint32_t CIE23:1; /* Channel 23 Interruput Enable */ + uint32_t CIE22:1; /* Channel 22 Interruput Enable */ + uint32_t CIE21:1; /* Channel 21 Interruput Enable */ + uint32_t CIE20:1; /* Channel 20 Interruput Enable */ + uint32_t CIE19:1; /* Channel 19 Interruput Enable */ + uint32_t CIE18:1; /* Channel 18 Interruput Enable */ + uint32_t CIE17:1; /* Channel 17 Interruput Enable */ + uint32_t CIE16:1; /* Channel 16 Interruput Enable */ + uint32_t CIE15:1; /* Channel 15 Interruput Enable */ + uint32_t CIE14:1; /* Channel 14 Interruput Enable */ + uint32_t CIE13:1; /* Channel 13 Interruput Enable */ + uint32_t CIE12:1; /* Channel 12 Interruput Enable */ + uint32_t CIE11:1; /* Channel 11 Interruput Enable */ + uint32_t CIE10:1; /* Channel 10 Interruput Enable */ + uint32_t CIE9:1; /* Channel 9 Interruput Enable */ + uint32_t CIE8:1; /* Channel 8 Interruput Enable */ + uint32_t CIE7:1; /* Channel 7 Interruput Enable */ + uint32_t CIE6:1; /* Channel 6 Interruput Enable */ + uint32_t CIE5:1; /* Channel 5 Interruput Enable */ + uint32_t CIE4:1; /* Channel 4 Interruput Enable */ + uint32_t CIE3:1; /* Channel 3 Interruput Enable */ + uint32_t CIE2:1; /* Channel 2 Interruput Enable */ + uint32_t CIE1:1; /* Channel 1 Interruput Enable */ + uint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_A; + uint32_t etpu_reserved16; /* For single ETPU implementations */ + + uint32_t etpu_reserved17[2]; + + union { /* ETPU_A Channel Data Transfer Request Enable */ + uint32_t R; + struct { + uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_A; + uint32_t etpu_reserved19; /* For single ETPU implementations */ + + uint32_t etpu_reserved20[10]; + union { /* ETPU_A Channel Pending Service Status */ + uint32_t R; + struct { + uint32_t SR31:1; /* Channel 31 Pending Service Status */ + uint32_t SR30:1; /* Channel 30 Pending Service Status */ + uint32_t SR29:1; /* Channel 29 Pending Service Status */ + uint32_t SR28:1; /* Channel 28 Pending Service Status */ + uint32_t SR27:1; /* Channel 27 Pending Service Status */ + uint32_t SR26:1; /* Channel 26 Pending Service Status */ + uint32_t SR25:1; /* Channel 25 Pending Service Status */ + uint32_t SR24:1; /* Channel 24 Pending Service Status */ + uint32_t SR23:1; /* Channel 23 Pending Service Status */ + uint32_t SR22:1; /* Channel 22 Pending Service Status */ + uint32_t SR21:1; /* Channel 21 Pending Service Status */ + uint32_t SR20:1; /* Channel 20 Pending Service Status */ + uint32_t SR19:1; /* Channel 19 Pending Service Status */ + uint32_t SR18:1; /* Channel 18 Pending Service Status */ + uint32_t SR17:1; /* Channel 17 Pending Service Status */ + uint32_t SR16:1; /* Channel 16 Pending Service Status */ + uint32_t SR15:1; /* Channel 15 Pending Service Status */ + uint32_t SR14:1; /* Channel 14 Pending Service Status */ + uint32_t SR13:1; /* Channel 13 Pending Service Status */ + uint32_t SR12:1; /* Channel 12 Pending Service Status */ + uint32_t SR11:1; /* Channel 11 Pending Service Status */ + uint32_t SR10:1; /* Channel 10 Pending Service Status */ + uint32_t SR9:1; /* Channel 9 Pending Service Status */ + uint32_t SR8:1; /* Channel 8 Pending Service Status */ + uint32_t SR7:1; /* Channel 7 Pending Service Status */ + uint32_t SR6:1; /* Channel 6 Pending Service Status */ + uint32_t SR5:1; /* Channel 5 Pending Service Status */ + uint32_t SR4:1; /* Channel 4 Pending Service Status */ + uint32_t SR3:1; /* Channel 3 Pending Service Status */ + uint32_t SR2:1; /* Channel 2 Pending Service Status */ + uint32_t SR1:1; /* Channel 1 Pending Service Status */ + uint32_t SR0:1; /* Channel 0 Pending Service Status */ + } B; + } CPSSR_A; + uint32_t etpu_reserved22; /* For single ETPU implementations */ + + uint32_t etpu_reserved20a[2]; + + union { /* ETPU_A Channel Service Status */ + uint32_t R; + struct { + uint32_t SS31:1; /* Channel 31 Service Status */ + uint32_t SS30:1; /* Channel 30 Service Status */ + uint32_t SS29:1; /* Channel 29 Service Status */ + uint32_t SS28:1; /* Channel 28 Service Status */ + uint32_t SS27:1; /* Channel 27 Service Status */ + uint32_t SS26:1; /* Channel 26 Service Status */ + uint32_t SS25:1; /* Channel 25 Service Status */ + uint32_t SS24:1; /* Channel 24 Service Status */ + uint32_t SS23:1; /* Channel 23 Service Status */ + uint32_t SS22:1; /* Channel 22 Service Status */ + uint32_t SS21:1; /* Channel 21 Service Status */ + uint32_t SS20:1; /* Channel 20 Service Status */ + uint32_t SS19:1; /* Channel 19 Service Status */ + uint32_t SS18:1; /* Channel 18 Service Status */ + uint32_t SS17:1; /* Channel 17 Service Status */ + uint32_t SS16:1; /* Channel 16 Service Status */ + uint32_t SS15:1; /* Channel 15 Service Status */ + uint32_t SS14:1; /* Channel 14 Service Status */ + uint32_t SS13:1; /* Channel 13 Service Status */ + uint32_t SS12:1; /* Channel 12 Service Status */ + uint32_t SS11:1; /* Channel 11 Service Status */ + uint32_t SS10:1; /* Channel 10 Service Status */ + uint32_t SS9:1; /* Channel 9 Service Status */ + uint32_t SS8:1; /* Channel 8 Service Status */ + uint32_t SS7:1; /* Channel 7 Service Status */ + uint32_t SS6:1; /* Channel 6 Service Status */ + uint32_t SS5:1; /* Channel 5 Service Status */ + uint32_t SS4:1; /* Channel 4 Service Status */ + uint32_t SS3:1; /* Channel 3 Service Status */ + uint32_t SS2:1; /* Channel 2 Service Status */ + uint32_t SS1:1; /* Channel 1 Service Status */ + uint32_t SS0:1; /* Channel 0 Service Status */ + } B; + } CSSR_A; + uint32_t etpu_reserved22a; /* For single ETPU implementations */ + + uint32_t etpu_reserved23[90]; + +/*****************************Channels********************************/ + + struct { + union { + uint32_t R; /* Channel Configuration Register */ + struct { + uint32_t CIE:1; /* Channel Interruput Enable */ + uint32_t DTRE:1; /* Data Transfer Request Enable */ + uint32_t CPR:2; /* Channel Priority */ + uint32_t:3; + uint32_t ETCS:1; /* Entry Table Condition Select */ + uint32_t:3; + uint32_t CFS:5; /* Channel Function Select */ + uint32_t ODIS:1; /* Output disable */ + uint32_t OPOL:1; /* output polarity */ + uint32_t:3; + uint32_t CPBA:11; /* Channel Parameter Base Address */ + } B; + } CR; + union { + uint32_t R; /* Channel Status Control Register */ + struct { + uint32_t CIS:1; /* Channel Interruput Status */ + uint32_t CIOS:1; /* Channel Interruput Overflow Status */ + uint32_t:6; + uint32_t DTRS:1; /* Data Transfer Status */ + uint32_t DTROS:1; /* Data Transfer Overflow Status */ + uint32_t:6; + uint32_t IPS:1; /* Input Pin State */ + uint32_t OPS:1; /* Output Pin State */ + uint32_t OBE:1; /* Output Buffer Enable */ + uint32_t:11; + uint32_t FM1:1; /* Function mode */ + uint32_t FM0:1; /* Function mode */ + } B; + } SCR; + union { + uint32_t R; /* Channel Host Service Request Register */ + struct { + uint32_t:29; /* Host Service Request */ + uint32_t HSR:3; + } B; + } HSRR; + uint32_t etpu_reserved23; + } CHAN[127]; + + }; +/****************************************************************************/ +/* MODULE : XBAR CrossBar */ +/****************************************************************************/ + struct XBAR_tag { + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:1; + uint32_t MSTR6:3; /* FLEXRAY */ + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR3:3; /* FEC */ + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR0; /* Master Priority Register for Slave Port 0 */ + + uint32_t xbar_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR0; /* General Purpose Control Register for Slave Port 0 */ + + uint32_t xbar_reserved2[59]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:1; + uint32_t MSTR6:3; /* FLEXRAY */ + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR3:3; /* FEC */ + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR1; /* Master Priority Register for Slave Port 1 */ + + uint32_t xbar_reserved3[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR1; /* General Purpose Control Register for Slave Port 1 */ + + uint32_t xbar_reserved4[123]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:1; + uint32_t MSTR6:3; /* FLEXRAY */ + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR3:3; /* FEC */ + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR3; /* Master Priority Register for Slave Port 3 */ + + uint32_t xbar_reserved5[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR3; /* General Purpose Control Register for Slave Port 3 */ + uint32_t xbar_reserved6[187]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:1; + uint32_t MSTR6:3; /* FLEXRAY */ + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR3:3; /* FEC */ + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR6; /* Master Priority Register for Slave Port 6 */ + + uint32_t xbar_reserved7[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR6; /* General Purpose Control Register for Slave Port 6 */ + + uint32_t xbar_reserved8[59]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:1; + uint32_t MSTR6:3; /* FLEXRAY */ + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR3:3; /* FEC */ + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR7; /* Master Priority Register for Slave Port 7 */ + + uint32_t xbar_reserved9[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR7; /* General Purpose Control Register for Slave Port 7 */ + + }; +/****************************************************************************/ +/* MODULE : ECSM */ +/****************************************************************************/ + struct ECSM_tag { + + uint32_t ecsm_reserved1[5]; + + uint16_t ecsm_reserved2; + + union { + uint16_t R; + } SWTCR; //Software Watchdog Timer Control + + uint8_t ecsm_reserved3[3]; + + union { + uint8_t R; + } SWTSR; //SWT Service Register + + uint8_t ecsm_reserved4[3]; + + union { + uint8_t R; + } SWTIR; //SWT Interrupt Register + + uint32_t ecsm_reserved5a[1]; + + union { + uint32_t R; + struct { + uint32_t FSBCR0:1; + uint32_t FSBCR1:1; + uint32_t FSBCR2:1; + uint32_t FSBCR3:1; + uint32_t FSBCR4:1; + uint32_t FSBCR5:1; + uint32_t FSBCR6:1; + uint32_t FSBCR7:1; + uint32_t RBEN:1; + uint32_t WBEN:1; + uint32_t ACCERR:1; + uint32_t:21; + } B; + } FSBMCR; /* FEC System Bus Master Control Register */ + + uint32_t ecsm_reserved5c[6]; + + uint8_t ecsm_reserved6[3]; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t ERNCR:1; + uint8_t EFNCR:1; + } B; + } ECR; //ECC Configuration Register + + uint8_t mcm_reserved8[3]; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t RNCE:1; + uint8_t FNCE:1; + } B; + } ESR; //ECC Status Register + + uint16_t ecsm_reserved9; + + union { + uint16_t R; + struct { + uint16_t:6; + uint16_t FRCNCI:1; + uint16_t FR1NCI:1; + uint16_t:1; + uint16_t ERRBIT:7; + } B; + } EEGR; //ECC Error Generation Register + + uint32_t ecsm_reserved10; + + union { + uint32_t R; + struct { + uint32_t FEAR:32; + } B; + } FEAR; //Flash ECC Address Register + + uint16_t ecsm_reserved11; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t FEMR:4; + } B; + } FEMR; //Flash ECC Master Register + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROT0:1; + uint8_t PROT1:1; + uint8_t PROT2:1; + uint8_t PROT3:1; + } B; + } FEAT; //Flash ECC Attributes Register + + union { + uint32_t R; + struct { + uint32_t FEDH:32; + } B; + } FEDRH; //Flash ECC Data High Register + + union { + uint32_t R; + struct { + uint32_t FEDL:32; + } B; + } FEDRL; //Flash ECC Data Low Register + + union { + uint32_t R; + struct { + uint32_t REAR:32; + } B; + } REAR; //RAM ECC Address + + uint8_t ecsm_reserved12[2]; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t REMR:4; + } B; + } REMR; //RAM ECC Master + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROT0:1; + uint8_t PROT1:1; + uint8_t PROT2:1; + uint8_t PROT3:1; + } B; + } REAT; // RAM ECC Attributes Register + + union { + uint32_t R; + struct { + uint32_t REDH:32; + } B; + } REDRH; //RAM ECC Data High Register + + union { + uint32_t R; + struct { + uint32_t REDL:32; + } B; + } REDRL; //RAMECC Data Low Register + + }; +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + struct INTC_tag { + union { + uint32_t R; + struct { + uint32_t:26; + uint32_t VTES:1; + uint32_t:4; + uint32_t HVEN:1; + } B; + } MCR; /* Module Configuration Register */ + + int32_t INTC_reserved00; + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR; /* Current Priority Register */ + + uint32_t intc_reserved1; + + union { + uint32_t R; + struct { + uint32_t VTBA:21; + uint32_t INTVEC:9; + uint32_t:2; + } B; + } IACKR; /* Interrupt Acknowledge Register */ + + uint32_t intc_reserved2; + + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } EOIR; /* End of Interrupt Register */ + + uint32_t intc_reserved3; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t SET:1; + uint8_t CLR:1; + } B; + } SSCIR[8]; /* Software Set/Clear Interruput Register */ + + uint32_t intc_reserved4[6]; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t PRI:4; + } B; + } PSR[358]; /* Software Set/Clear Interrupt Register */ + + }; +/****************************************************************************/ +/* MODULE : EQADC */ +/****************************************************************************/ + struct EQADC_tag { + union { + uint32_t R; + struct { + uint32_t:27; + uint32_t ESSIE:2; + uint32_t:1; + uint32_t DBG:2; + } B; + } MCR; /* Module Configuration Register */ + + int32_t EQADC_reserved00; + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t NMF:26; + } B; + } NMSFR; /* Null Message Send Format Register */ + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } ETDFR; /* External Trigger Digital Filter Register */ + + union { + uint32_t R; + struct { + uint32_t CFPUSH:32; + } B; + } CFPR[6]; /* CFIFO Push Registers */ + + uint32_t eqadc_reserved1; + + uint32_t eqadc_reserved2; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RFPOP:16; + } B; + } RFPR[6]; /* Result FIFO Pop Registers */ + + uint32_t eqadc_reserved3; + + uint32_t eqadc_reserved4; + + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t SSE:1; + uint16_t CFINV:1; + uint16_t:1; + uint16_t MODE:4; + uint16_t:4; + } B; + } CFCR[6]; /* CFIFO Control Registers */ + + uint32_t eqadc_reserved5; + + union { + uint16_t R; + struct { + uint16_t NCIE:1; + uint16_t TORIE:1; + uint16_t PIE:1; + uint16_t EOQIE:1; + uint16_t CFUIE:1; + uint16_t:1; + uint16_t CFFE:1; + uint16_t CFFS:1; + uint16_t:4; + uint16_t RFOIE:1; + uint16_t:1; + uint16_t RFDE:1; + uint16_t RFDS:1; + } B; + } IDCR[6]; /* Interrupt and DMA Control Registers */ + + uint32_t eqadc_reserved6; + + union { + uint32_t R; + struct { + uint32_t NCF:1; + uint32_t TORF:1; + uint32_t PF:1; + uint32_t EOQF:1; + uint32_t CFUF:1; + uint32_t SSS:1; + uint32_t CFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t CFCTR:4; + uint32_t TNXTPTR:4; + uint32_t RFCTR:4; + uint32_t POPNXTPTR:4; + } B; + } FISR[6]; /* FIFO and Interrupt Status Registers */ + + uint32_t eqadc_reserved7; + + uint32_t eqadc_reserved8; + + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t TCCF:11; + } B; + } CFTCR[6]; /* CFIFO Transfer Counter Registers */ + + uint32_t eqadc_reserved9; + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:5; + uint32_t LCFTCB0:4; + uint32_t TC_LCFTCB0:11; + } B; + } CFSSR0; /* CFIFO Status Register 0 */ + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:5; + uint32_t LCFTCB1:4; + uint32_t TC_LCFTCB1:11; + } B; + } CFSSR1; /* CFIFO Status Register 1 */ + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:4; + uint32_t ECBNI:1; + uint32_t LCFTSSI:4; + uint32_t TC_LCFTSSI:11; + } B; + } CFSSR2; /* CFIFO Status Register 2 */ + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:20; + } B; + } CFSR; + + uint32_t eqadc_reserved11; + + union { + uint32_t R; + struct { + uint32_t:21; + uint32_t MDT:3; + uint32_t:4; + uint32_t BR:4; + } B; + } SSICR; /* SSI Control Register */ + + union { + uint32_t R; + struct { + uint32_t RDV:1; + uint32_t:5; + uint32_t RDATA:26; + } B; + } SSIRDR; /* SSI Recieve Data Register */ + + uint32_t eqadc_reserved12[17]; + + struct { + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved13[12]; + + } CF[6]; + + uint32_t eqadc_reserved14[32]; + + struct { + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved15[12]; + + } RF[6]; + + }; +/****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + struct DSPI_tag { + union DSPI_MCR_tag { + uint32_t R; + struct { + uint32_t MSTR:1; + uint32_t CONT_SCKE:1; + uint32_t DCONF:2; + uint32_t FRZ:1; + uint32_t MTFE:1; + uint32_t PCSSE:1; + uint32_t ROOE:1; + uint32_t:2; + uint32_t PCSIS5:1; + uint32_t PCSIS4:1; + uint32_t PCSIS3:1; + uint32_t PCSIS2:1; + uint32_t PCSIS1:1; + uint32_t PCSIS0:1; + uint32_t DOZE:1; + uint32_t MDIS:1; + uint32_t DIS_TXF:1; + uint32_t DIS_RXF:1; + uint32_t CLR_TXF:1; + uint32_t CLR_RXF:1; + uint32_t SMPL_PT:2; + uint32_t:7; + uint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t dspi_reserved1; + + union { + uint32_t R; + struct { + uint32_t TCNT:16; + uint32_t:16; + } B; + } TCR; + + union DSPI_CTAR_tag { + uint32_t R; + struct { + uint32_t DBR:1; + uint32_t FMSZ:4; + uint32_t CPOL:1; + uint32_t CPHA:1; + uint32_t LSBFE:1; + uint32_t PCSSCK:2; + uint32_t PASC:2; + uint32_t PDT:2; + uint32_t PBR:2; + uint32_t CSSCK:4; + uint32_t ASC:4; + uint32_t DT:4; + uint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers */ + + union DSPI_SR_tag { + uint32_t R; + struct { + uint32_t TCF:1; + uint32_t TXRXS:1; + uint32_t:1; + uint32_t EOQF:1; + uint32_t TFUF:1; + uint32_t:1; + uint32_t TFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t TXCTR:4; + uint32_t TXNXTPTR:4; + uint32_t RXCTR:4; + uint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register */ + + union DSPI_RSER_tag { + uint32_t R; + struct { + uint32_t TCFRE:1; + uint32_t:2; + uint32_t EOQFRE:1; + uint32_t TFUFRE:1; + uint32_t:1; + uint32_t TFFFRE:1; + uint32_t TFFFDIRS:1; + uint32_t:4; + uint32_t RFOFRE:1; + uint32_t:1; + uint32_t RFDFRE:1; + uint32_t RFDFDIRS:1; + uint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register */ + + union DSPI_PUSHR_tag { + uint32_t R; + struct { + uint32_t CONT:1; + uint32_t CTAS:3; + uint32_t EOQ:1; + uint32_t CTCNT:1; + uint32_t:4; + uint32_t PCS5:1; + uint32_t PCS4:1; + uint32_t PCS3:1; + uint32_t PCS2:1; + uint32_t PCS1:1; + uint32_t PCS0:1; + uint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register */ + + union DSPI_POPR_tag { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register */ + + union { + uint32_t R; + struct { + uint32_t TXCMD:16; + uint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_txf[12]; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_rxf[12]; + + union { + uint32_t R; + struct { + uint32_t MTOE:1; + uint32_t:1; + uint32_t MTOCNT:6; + uint32_t:4; + uint32_t TXSS:1; + uint32_t TPOL:1; + uint32_t TRRE:1; + uint32_t CID:1; + uint32_t DCONT:1; + uint32_t DSICTAS:3; + uint32_t:6; + uint32_t DPCS5:1; + uint32_t DPCS4:1; + uint32_t DPCS3:1; + uint32_t DPCS2:1; + uint32_t DPCS1:1; + uint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t SER_DATA:16; + } B; + } SDR; /* DSI Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t ASER_DATA:16; + } B; + } ASDR; /* DSI Alternate Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t COMP_DATA:16; + } B; + } COMPR; /* DSI Transmit Comparison Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t DESER_DATA:16; + } B; + } DDR; /* DSI deserialization Data Register */ + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_tag { + union ESCI_CR1_tag { + uint32_t R; + struct { + uint32_t:3; + uint32_t SBR:13; + uint32_t LOOPS:1; + uint32_t SCISDOZ:1; + uint32_t RSRC:1; + uint32_t M:1; + uint32_t WAKE:1; + uint32_t ILT:1; + uint32_t PE:1; + uint32_t PT:1; + uint32_t TIE:1; + uint32_t TCIE:1; + uint32_t RIE:1; + uint32_t ILIE:1; + uint32_t TE:1; + uint32_t RE:1; + uint32_t RWU:1; + uint32_t SBK:1; + } B; + } CR1; /* Control Register 1 */ + + union ESCI_CR2_tag { + uint16_t R; + struct { + uint16_t MDIS:1; + uint16_t FBR:1; + uint16_t BSTP:1; + uint16_t IEBERR:1; + uint16_t RXDMA:1; + uint16_t TXDMA:1; + uint16_t BRK13:1; + uint16_t:1; + uint16_t BESM13:1; + uint16_t SBSTP:1; + uint16_t:2; + uint16_t ORIE:1; + uint16_t NFIE:1; + uint16_t FEIE:1; + uint16_t PFIE:1; + } B; + } CR2; /* Control Register 2 */ + + union ESCI_DR_tag { + uint16_t R; + struct { + uint16_t R8:1; + uint16_t T8:1; + uint16_t:6; + uint8_t D; + } B; + } DR; /* Data Register */ + + union ESCI_SR_tag { + uint32_t R; + struct { + uint32_t TDRE:1; + uint32_t TC:1; + uint32_t RDRF:1; + uint32_t IDLE:1; + uint32_t OR:1; + uint32_t NF:1; + uint32_t FE:1; + uint32_t PF:1; + uint32_t:3; + uint32_t BERR:1; + uint32_t:3; + uint32_t RAF:1; + uint32_t RXRDY:1; + uint32_t TXRDY:1; + uint32_t LWAKE:1; + uint32_t STO:1; + uint32_t PBERR:1; + uint32_t CERR:1; + uint32_t CKERR:1; + uint32_t FRC:1; + uint32_t:7; + uint32_t OVFL:1; + } B; + } SR; /* Status Register */ + + union { + uint32_t R; + struct { + uint32_t LRES:1; + uint32_t WU:1; + uint32_t WUD0:1; + uint32_t WUD1:1; + uint32_t LDBG:1; + uint32_t DSF:1; + uint32_t PRTY:1; + uint32_t LIN:1; + uint32_t RXIE:1; + uint32_t TXIE:1; + uint32_t WUIE:1; + uint32_t STIE:1; + uint32_t PBIE:1; + uint32_t CIE:1; + uint32_t CKIE:1; + uint32_t FCIE:1; + uint32_t:7; + uint32_t OFIE:1; + uint32_t:8; + } B; + } LCR; /* LIN Control Register */ + + union { + uint32_t R; + } LTR; /* LIN Transmit Register */ + + union { + uint32_t R; + } LRR; /* LIN Recieve Register */ + + union { + uint32_t R; + } LPR; /* LIN CRC Polynom Register */ + + }; +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + struct FLEXCAN2_tag { + union { + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t:1; + uint32_t HALT:1; + uint32_t NOTRDY:1; + uint32_t:1; + uint32_t SOFTRST:1; + uint32_t FRZACK:1; + uint32_t:1; + uint32_t:1; + + uint32_t WRNEN:1; + + uint32_t MDISACK:1; + uint32_t:1; + uint32_t:1; + + uint32_t SRXDIS:1; + uint32_t MBFEN:1; + uint32_t:10; + + uint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t PRESDIV:8; + uint32_t RJW:2; + uint32_t PSEG1:3; + uint32_t PSEG2:3; + uint32_t BOFFMSK:1; + uint32_t ERRMSK:1; + uint32_t CLKSRC:1; + uint32_t LPB:1; + + uint32_t TWRNMSK:1; + uint32_t RWRNMSK:1; + uint32_t:2; + + uint32_t SMP:1; + uint32_t BOFFREC:1; + uint32_t TSYN:1; + uint32_t LBUF:1; + uint32_t LOM:1; + uint32_t PROPSEG:3; + } B; + } CR; /* Control Register */ + + union { + uint32_t R; + } TIMER; /* Free Running Timer */ + int32_t FLEXCAN_reserved00; + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXECNT:8; + uint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + uint32_t R; + struct { + uint32_t:14; + + uint32_t TWRNINT:1; + uint32_t RWRNINT:1; + + uint32_t BIT1ERR:1; + uint32_t BIT0ERR:1; + uint32_t ACKERR:1; + uint32_t CRCERR:1; + uint32_t FRMERR:1; + uint32_t STFERR:1; + uint32_t TXWRN:1; + uint32_t RXWRN:1; + uint32_t IDLE:1; + uint32_t TXRX:1; + uint32_t FLTCONF:2; + uint32_t:1; + uint32_t BOFFINT:1; + uint32_t ERRINT:1; + uint32_t:1; + } B; + } ESR; /* Error and Status Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63M:1; + uint32_t BUF62M:1; + uint32_t BUF61M:1; + uint32_t BUF60M:1; + uint32_t BUF59M:1; + uint32_t BUF58M:1; + uint32_t BUF57M:1; + uint32_t BUF56M:1; + uint32_t BUF55M:1; + uint32_t BUF54M:1; + uint32_t BUF53M:1; + uint32_t BUF52M:1; + uint32_t BUF51M:1; + uint32_t BUF50M:1; + uint32_t BUF49M:1; + uint32_t BUF48M:1; + uint32_t BUF47M:1; + uint32_t BUF46M:1; + uint32_t BUF45M:1; + uint32_t BUF44M:1; + uint32_t BUF43M:1; + uint32_t BUF42M:1; + uint32_t BUF41M:1; + uint32_t BUF40M:1; + uint32_t BUF39M:1; + uint32_t BUF38M:1; + uint32_t BUF37M:1; + uint32_t BUF36M:1; + uint32_t BUF35M:1; + uint32_t BUF34M:1; + uint32_t BUF33M:1; + uint32_t BUF32M:1; + } B; + } IMRH; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31M:1; + uint32_t BUF30M:1; + uint32_t BUF29M:1; + uint32_t BUF28M:1; + uint32_t BUF27M:1; + uint32_t BUF26M:1; + uint32_t BUF25M:1; + uint32_t BUF24M:1; + uint32_t BUF23M:1; + uint32_t BUF22M:1; + uint32_t BUF21M:1; + uint32_t BUF20M:1; + uint32_t BUF19M:1; + uint32_t BUF18M:1; + uint32_t BUF17M:1; + uint32_t BUF16M:1; + uint32_t BUF15M:1; + uint32_t BUF14M:1; + uint32_t BUF13M:1; + uint32_t BUF12M:1; + uint32_t BUF11M:1; + uint32_t BUF10M:1; + uint32_t BUF09M:1; + uint32_t BUF08M:1; + uint32_t BUF07M:1; + uint32_t BUF06M:1; + uint32_t BUF05M:1; + uint32_t BUF04M:1; + uint32_t BUF03M:1; + uint32_t BUF02M:1; + uint32_t BUF01M:1; + uint32_t BUF00M:1; + } B; + } IMRL; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63I:1; + uint32_t BUF62I:1; + uint32_t BUF61I:1; + uint32_t BUF60I:1; + uint32_t BUF59I:1; + uint32_t BUF58I:1; + uint32_t BUF57I:1; + uint32_t BUF56I:1; + uint32_t BUF55I:1; + uint32_t BUF54I:1; + uint32_t BUF53I:1; + uint32_t BUF52I:1; + uint32_t BUF51I:1; + uint32_t BUF50I:1; + uint32_t BUF49I:1; + uint32_t BUF48I:1; + uint32_t BUF47I:1; + uint32_t BUF46I:1; + uint32_t BUF45I:1; + uint32_t BUF44I:1; + uint32_t BUF43I:1; + uint32_t BUF42I:1; + uint32_t BUF41I:1; + uint32_t BUF40I:1; + uint32_t BUF39I:1; + uint32_t BUF38I:1; + uint32_t BUF37I:1; + uint32_t BUF36I:1; + uint32_t BUF35I:1; + uint32_t BUF34I:1; + uint32_t BUF33I:1; + uint32_t BUF32I:1; + } B; + } IFRH; /* Interruput Flag Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31I:1; + uint32_t BUF30I:1; + uint32_t BUF29I:1; + uint32_t BUF28I:1; + uint32_t BUF27I:1; + uint32_t BUF26I:1; + uint32_t BUF25I:1; + uint32_t BUF24I:1; + uint32_t BUF23I:1; + uint32_t BUF22I:1; + uint32_t BUF21I:1; + uint32_t BUF20I:1; + uint32_t BUF19I:1; + uint32_t BUF18I:1; + uint32_t BUF17I:1; + uint32_t BUF16I:1; + uint32_t BUF15I:1; + uint32_t BUF14I:1; + uint32_t BUF13I:1; + uint32_t BUF12I:1; + uint32_t BUF11I:1; + uint32_t BUF10I:1; + uint32_t BUF09I:1; + uint32_t BUF08I:1; + uint32_t BUF07I:1; + uint32_t BUF06I:1; + uint32_t BUF05I:1; + uint32_t BUF04I:1; + uint32_t BUF03I:1; + uint32_t BUF02I:1; + uint32_t BUF01I:1; + uint32_t BUF00I:1; + } B; + } IFRL; /* Interruput Flag Register */ + + uint32_t flexcan2_reserved2[19]; + + struct canbuf_t { + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t CODE:4; + uint32_t:1; + uint32_t SRR:1; + uint32_t IDE:1; + uint32_t RTR:1; + uint32_t LENGTH:4; + uint32_t TIMESTAMP:16; + } B; + } CS; + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t STD_ID:11; + uint32_t EXT_ID:18; + } B; + } ID; + + union { + uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + uint32_t W[2]; /* Data buffer in words (32 bits) */ + uint32_t R[2]; /* Data buffer in words (32 bits) */ + } DATA; + + } BUF[64]; + + uint32_t flexcan2_reserved3[256]; + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RXIMR[64]; /* RX Individual Mask Registers */ + + }; +/****************************************************************************/ +/* MODULE : FEC */ +/****************************************************************************/ + struct FEC_tag { + + uint32_t fec_reserved_start[0x1]; + + union { + uint32_t R; + struct { + uint32_t HBERR:1; + uint32_t BABR:1; + uint32_t BABT:1; + uint32_t GRA:1; + uint32_t TXF:1; + uint32_t TXB:1; + uint32_t RXF:1; + uint32_t RXB:1; + uint32_t MII:1; + uint32_t EBERR:1; + uint32_t LC:1; + uint32_t RL:1; + uint32_t UN:1; + uint32_t:19; + } B; + } EIR; /* Interrupt Event Register */ + + union { + uint32_t R; + struct { + uint32_t HBERRM:1; + uint32_t BABRM:1; + uint32_t BABTM:1; + uint32_t GRAM:1; + uint32_t TXFM:1; + uint32_t TXBM:1; + uint32_t RXFM:1; + uint32_t RXBM:1; + uint32_t MIIM:1; + uint32_t EBERRM:1; + uint32_t LCM:1; + uint32_t RLM:1; + uint32_t UNM:1; + uint32_t:19; + } B; + } EIMR; /* Interrupt Mask Register */ + + uint32_t fec_reserved_eimr; + + union { + uint32_t R; + struct { + uint32_t:7; + uint32_t R_DES_ACTIVE:1; + uint32_t:24; + } B; + } RDAR; /* Receive Descriptor Active Register */ + + union { + uint32_t R; + struct { + uint32_t:7; + uint32_t X_DES_ACTIVE:1; + uint32_t:24; + } B; + } TDAR; /* Transmit Descriptor Active Register */ + + uint32_t fec_reserved_tdar[3]; + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t ETHER_EN:1; + uint32_t RESET:1; + } B; + } ECR; /* Ethernet Control Register */ + + uint32_t fec_reserved_ecr[6]; + + union { + uint32_t R; + struct { + uint32_t ST:2; + uint32_t CP:2; + uint32_t PA:5; + uint32_t RA:5; + uint32_t TA:2; + uint32_t DATA:16; + } B; + } MDATA; /* MII Data Register */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t DIS_PREAMBLE:1; + uint32_t MII_SPEED:6; + uint32_t:1; + } B; + } MSCR; /* MII Speed Control Register */ + + uint32_t fec_reserved_mscr[7]; + + union { + uint32_t R; + struct { + uint32_t MIB_DISABLE:1; + uint32_t MIB_IDLE:1; + uint32_t:30; + } B; + } MIBC; /* MIB Control Register */ + + uint32_t fec_reserved_mibc[7]; + + union { + uint32_t R; + struct { + uint32_t:5; + uint32_t MAX_FL:11; + uint32_t:10; + uint32_t FCE:1; + uint32_t BC_REJ:1; + uint32_t PROM:1; + uint32_t MII_MODE:1; + uint32_t DRT:1; + uint32_t LOOP:1; + } B; + } RCR; /* Receive Control Register */ + + uint32_t fec_reserved_rcr[15]; + + union { + uint32_t R; + struct { + uint32_t:27; + uint32_t RFC_PAUSE:1; + uint32_t TFC_PAUSE:1; + uint32_t FDEN:1; + uint32_t HBC:1; + uint32_t GTS:1; + } B; + } TCR; /* Transmit Control Register */ + + uint32_t fec_reserved_tcr[7]; + + union { + uint32_t R; + struct { + uint32_t PADDR1:32; + } B; + } PALR; /* Physical Address Low Register */ + + union { + uint32_t R; + struct { + uint32_t PADDR2:16; + uint32_t TYPE:16; + } B; + } PAUR; /* Physical Address High + Type Register */ + + union { + uint32_t R; + struct { + uint32_t OPCODE:16; + uint32_t PAUSE_DUR:16; + } B; + } OPD; /* Opcode/Pause Duration Register */ + + uint32_t fec_reserved_opd[10]; + + union { + uint32_t R; + struct { + uint32_t IADDR1:32; + } B; + } IAUR; /* Descriptor Individual Upper Address Register */ + + union { + uint32_t R; + struct { + uint32_t IADDR2:32; + } B; + } IALR; /* Descriptor Individual Lower Address Register */ + + union { + uint32_t R; + struct { + uint32_t GADDR1:32; + } B; + } GAUR; /* Descriptor Group Upper Address Register */ + + union { + uint32_t R; + struct { + uint32_t GADDR2:32; + } B; + } GALR; /* Descriptor Group Lower Address Register */ + + uint32_t fec_reserved_galr[7]; + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t X_WMRK:2; + } B; + } TFWR; /* FIFO Transmit FIFO Watermark Register */ + + uint32_t fec_reserved_tfwr; + + union { + uint32_t R; + struct { + uint32_t:22; + uint32_t R_BOUND:8; + uint32_t:2; + } B; + } FRBR; /* FIFO Receive Bound Register */ + + union { + uint32_t R; + struct { + uint32_t:22; + uint32_t R_FSTART:8; + uint32_t:2; + } B; + } FRSR; /* FIFO Receive Start Register */ + + uint32_t fec_reserved_frsr[11]; + + union { + uint32_t R; + struct { + uint32_t R_DES_START:30; + uint32_t:2; + } B; + } ERDSR; /* Receive Descriptor Ring Start Register */ + + union { + uint32_t R; + struct { + uint32_t X_DES_START:30; + uint32_t:2; + } B; + } ETDSR; /* Transmit Descriptor Ring Start Register */ + + union { + uint32_t R; + struct { + uint32_t:21; + uint32_t R_BUF_SIZE:7; + uint32_t:4; + } B; + } EMRBR; /* Receive Buffer Size Register */ + + uint32_t fec_reserved_emrbr[29]; + + union { + uint32_t R; + } RMON_T_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } RMON_T_PACKETS; /* RMON Tx packet count */ + + union { + uint32_t R; + } RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */ + + union { + uint32_t R; + } RMON_T_MC_PKT; /* RMON Tx Multicast Packets */ + + union { + uint32_t R; + } RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */ + + union { + uint32_t R; + } RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */ + + union { + uint32_t R; + } RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */ + + union { + uint32_t R; + } RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */ + + union { + uint32_t R; + } RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */ + + union { + uint32_t R; + } RMON_T_COL; /* RMON Tx collision count */ + + union { + uint32_t R; + } RMON_T_P64; /* RMON Tx 64 byte packets */ + + union { + uint32_t R; + } RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */ + + union { + uint32_t R; + } RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */ + + union { + uint32_t R; + } RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */ + + union { + uint32_t R; + } RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */ + + union { + uint32_t R; + } RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */ + + union { + uint32_t R; + } RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */ + + union { + uint32_t R; + } RMON_T_OCTETS; /* RMON Tx Octets */ + + union { + uint32_t R; + } IEEE_T_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } IEEE_T_FRAME_OK; /* Frames Transmitted OK */ + + union { + uint32_t R; + } IEEE_T_1COL; /* Frames Transmitted with Single Collision */ + + union { + uint32_t R; + } IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */ + + union { + uint32_t R; + } IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */ + + union { + uint32_t R; + } IEEE_T_LCOL; /* Frames Transmitted with Late Collision */ + + union { + uint32_t R; + } IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */ + + union { + uint32_t R; + } IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */ + + union { + uint32_t R; + } IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */ + + union { + uint32_t R; + } IEEE_T_SQE; /* Frames Transmitted with SQE Error */ + + union { + uint32_t R; + } IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */ + + union { + uint32_t R; + } IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */ + + uint32_t fec_reserved_rmon_t_octets_ok[2]; + + union { + uint32_t R; + } RMON_R_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } RMON_R_PACKETS; /* RMON Rx packet count */ + + union { + uint32_t R; + } RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */ + + union { + uint32_t R; + } RMON_R_MC_PKT; /* RMON Rx Multicast Packets */ + + union { + uint32_t R; + } RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */ + + union { + uint32_t R; + } RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */ + + union { + uint32_t R; + } RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */ + + union { + uint32_t R; + } RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */ + + union { + uint32_t R; + } RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */ + + uint32_t fec_reserved_rmon_r_jab; + + union { + uint32_t R; + } RMON_R_P64; /* RMON Rx 64 byte packets */ + + union { + uint32_t R; + } RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */ + + union { + uint32_t R; + } RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */ + + union { + uint32_t R; + } RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */ + + union { + uint32_t R; + } RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */ + + union { + uint32_t R; + } RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */ + + union { + uint32_t R; + } RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */ + + union { + uint32_t R; + } RMON_R_OCTETS; /* RMON Rx Octets */ + + union { + uint32_t R; + } IEEE_R_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } IEEE_R_FRAME_OK; /* Frames Received OK */ + + union { + uint32_t R; + } IEEE_R_CRC; /* Frames Received with CRC Error */ + + union { + uint32_t R; + } IEEE_R_ALIGN; /* Frames Received with Alignment Error */ + + union { + uint32_t R; + } IEEE_R_MACERR; /* Receive Fifo Overflow count */ + + union { + uint32_t R; + } IEEE_R_FDXFC; /* Flow Control Pause frames received */ + + union { + uint32_t R; + } IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */ + + }; +/****************************************************************************/ +/* MODULE : FlexRay */ +/****************************************************************************/ + + typedef union uMVR { + uint16_t R; + struct { + uint16_t CHIVER:8; /* CHI Version Number */ + uint16_t PEVER:8; /* PE Version Number */ + } B; + } MVR_t; + + typedef union uMCR { + uint16_t R; + struct { + uint16_t MEN:1; /* module enable */ + uint16_t:1; + uint16_t SCMD:1; /* single channel mode */ + uint16_t CHB:1; /* channel B enable */ + uint16_t CHA:1; /* channel A enable */ + uint16_t SFFE:1; /* synchronization frame filter enable */ + uint16_t:5; + uint16_t CLKSEL:1; /* protocol engine clock source select */ + uint16_t PRESCALE:3; /* protocol engine clock prescaler */ + uint16_t:1; + } B; + } MCR_t; + typedef union uSTBSCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t STBSSEL:7; /* strobe signal select */ + uint16_t:3; + uint16_t ENB:1; /* strobe signal enable */ + uint16_t:2; + uint16_t STBPSEL:2; /* strobe port select */ + } B; + } STBSCR_t; + typedef union uSTBPCR { + uint16_t R; + struct { + uint16_t:12; + uint16_t STB3EN:1; /* strobe port enable */ + uint16_t STB2EN:1; /* strobe port enable */ + uint16_t STB1EN:1; /* strobe port enable */ + uint16_t STB0EN:1; /* strobe port enable */ + } B; + } STBPCR_t; + + typedef union uMBDSR { + uint16_t R; + struct { + uint16_t:1; + uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ + uint16_t:1; + uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ + } B; + } MBDSR_t; + typedef union uMBSSUTR { + uint16_t R; + struct { + + uint16_t:1; + uint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */ + uint16_t:1; + uint16_t LAST_MB_UTIL:7; /* last message buffer utilized */ + } B; + } MBSSUTR_t; + + typedef union uPOCR { + uint16_t R; + uint8_t byte[2]; + struct { + uint16_t WME:1; /* write mode external correction command */ + uint16_t:3; + uint16_t EOC_AP:2; /* external offset correction application */ + uint16_t ERC_AP:2; /* external rate correction application */ + uint16_t BSY:1; /* command write busy / write mode command */ + uint16_t:3; + uint16_t POCCMD:4; /* protocol command */ + } B; + } POCR_t; +/* protocol commands */ + typedef union uGIFER { + uint16_t R; + struct { + uint16_t MIF:1; /* module interrupt flag */ + uint16_t PRIF:1; /* protocol interrupt flag */ + uint16_t CHIF:1; /* CHI interrupt flag */ + uint16_t WKUPIF:1; /* wakeup interrupt flag */ + uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ + uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ + uint16_t RBIF:1; /* receive message buffer interrupt flag */ + uint16_t TBIF:1; /* transmit buffer interrupt flag */ + uint16_t MIE:1; /* module interrupt enable */ + uint16_t PRIE:1; /* protocol interrupt enable */ + uint16_t CHIE:1; /* CHI interrupt enable */ + uint16_t WKUPIE:1; /* wakeup interrupt enable */ + uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ + uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ + uint16_t RBIE:1; /* receive message buffer interrupt enable */ + uint16_t TBIE:1; /* transmit buffer interrupt enable */ + } B; + } GIFER_t; + typedef union uPIFR0 { + uint16_t R; + struct { + uint16_t FATLIF:1; /* fatal protocol error interrupt flag */ + uint16_t INTLIF:1; /* internal protocol error interrupt flag */ + uint16_t ILCFIF:1; /* illegal protocol configuration flag */ + uint16_t CSAIF:1; /* cold start abort interrupt flag */ + uint16_t MRCIF:1; /* missing rate correctio interrupt flag */ + uint16_t MOCIF:1; /* missing offset correctio interrupt flag */ + uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ + uint16_t MXSIF:1; /* max sync frames detected interrupt flag */ + uint16_t MTXIF:1; /* media access test symbol received flag */ + uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ + uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ + uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ + uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ + uint16_t TI2IF:1; /* timer 2 expired interrupt flag */ + uint16_t TI1IF:1; /* timer 1 expired interrupt flag */ + uint16_t CYSIF:1; /* cycle start interrupt flag */ + } B; + } PIFR0_t; + typedef union uPIFR1 { + uint16_t R; + struct { + uint16_t EMCIF:1; /* error mode changed interrupt flag */ + uint16_t IPCIF:1; /* illegal protocol command interrupt flag */ + uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ + uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ + uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ + uint16_t:2; + uint16_t EVTIF:1; /* even cycle table written interrupt flag */ + uint16_t ODTIF:1; /* odd cycle table written interrupt flag */ + uint16_t:4; + } B; + } PIFR1_t; + typedef union uPIER0 { + uint16_t R; + struct { + uint16_t FATLIE:1; /* fatal protocol error interrupt enable */ + uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ + uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ + uint16_t CSAIE:1; /* cold start abort interrupt enable */ + uint16_t MRCIE:1; /* missing rate correctio interrupt enable */ + uint16_t MOCIE:1; /* missing offset correctio interrupt enable */ + uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ + uint16_t MXSIE:1; /* max sync frames detected interrupt enable */ + uint16_t MTXIE:1; /* media access test symbol received interrupt enable */ + uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ + uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ + uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ + uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ + uint16_t TI2IE:1; /* timer 2 expired interrupt enable */ + uint16_t TI1IE:1; /* timer 1 expired interrupt enable */ + uint16_t CYSIE:1; /* cycle start interrupt enable */ + } B; + } PIER0_t; + typedef union uPIER1 { + uint16_t R; + struct { + uint16_t EMCIE:1; /* error mode changed interrupt enable */ + uint16_t IPCIE:1; /* illegal protocol command interrupt enable */ + uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ + uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ + uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ + uint16_t:2; + uint16_t EVTIE:1; /* even cycle table written interrupt enable */ + uint16_t ODTIE:1; /* odd cycle table written interrupt enable */ + uint16_t:4; + } B; + } PIER1_t; + typedef union uCHIERFR { + uint16_t R; + struct { + uint16_t FRLBEF:1; /* flame lost channel B error flag */ + uint16_t FRLAEF:1; /* frame lost channel A error flag */ + uint16_t PCMIEF:1; /* command ignored error flag */ + uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ + uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ + uint16_t MSBEF:1; /* message buffer search error flag */ + uint16_t MBUEF:1; /* message buffer utilization error flag */ + uint16_t LCKEF:1; /* lock error flag */ + uint16_t DBLEF:1; /* double transmit message buffer lock error flag */ + uint16_t SBCFEF:1; /* system bus communication failure error flag */ + uint16_t FIDEF:1; /* frame ID error flag */ + uint16_t DPLEF:1; /* dynamic payload length error flag */ + uint16_t SPLEF:1; /* static payload length error flag */ + uint16_t NMLEF:1; /* network management length error flag */ + uint16_t NMFEF:1; /* network management frame error flag */ + uint16_t ILSAEF:1; /* illegal access error flag */ + } B; + } CHIERFR_t; + typedef union uMBIVEC { + uint16_t R; + struct { + + uint16_t:1; + uint16_t TBIVEC:7; /* transmit buffer interrupt vector */ + uint16_t:1; + uint16_t RBIVEC:7; /* receive buffer interrupt vector */ + } B; + } MBIVEC_t; + + typedef union uPSR0 { + uint16_t R; + struct { + uint16_t ERRMODE:2; /* error mode */ + uint16_t SLOTMODE:2; /* slot mode */ + uint16_t:1; + uint16_t PROTSTATE:3; /* protocol state */ + uint16_t SUBSTATE:4; /* protocol sub state */ + uint16_t:1; + uint16_t WAKEUPSTATUS:3; /* wakeup status */ + } B; + } PSR0_t; + +/* protocol states */ +/* protocol sub-states */ +/* wakeup status */ + typedef union uPSR1 { + uint16_t R; + struct { + uint16_t CSAA:1; /* cold start attempt abort flag */ + uint16_t SCP:1; /* cold start path */ + uint16_t:1; + uint16_t REMCSAT:5; /* remanining coldstart attempts */ + uint16_t CPN:1; /* cold start noise path */ + uint16_t HHR:1; /* host halt request pending */ + uint16_t FRZ:1; /* freeze occured */ + uint16_t APTAC:5; /* allow passive to active counter */ + } B; + } PSR1_t; + typedef union uPSR2 { + uint16_t R; + struct { + uint16_t NBVB:1; /* NIT boundary violation on channel B */ + uint16_t NSEB:1; /* NIT syntax error on channel B */ + uint16_t STCB:1; /* symbol window transmit conflict on channel B */ + uint16_t SBVB:1; /* symbol window boundary violation on channel B */ + uint16_t SSEB:1; /* symbol window syntax error on channel B */ + uint16_t MTB:1; /* media access test symbol MTS received on channel B */ + uint16_t NBVA:1; /* NIT boundary violation on channel A */ + uint16_t NSEA:1; /* NIT syntax error on channel A */ + uint16_t STCA:1; /* symbol window transmit conflict on channel A */ + uint16_t SBVA:1; /* symbol window boundary violation on channel A */ + uint16_t SSEA:1; /* symbol window syntax error on channel A */ + uint16_t MTA:1; /* media access test symbol MTS received on channel A */ + uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ + } B; + } PSR2_t; + typedef union uPSR3 { + uint16_t R; + struct { + uint16_t:2; + uint16_t WUB:1; /* wakeup symbol received on channel B */ + uint16_t ABVB:1; /* aggregated boundary violation on channel B */ + uint16_t AACB:1; /* aggregated additional communication on channel B */ + uint16_t ACEB:1; /* aggregated content error on channel B */ + uint16_t ASEB:1; /* aggregated syntax error on channel B */ + uint16_t AVFB:1; /* aggregated valid frame on channel B */ + uint16_t:2; + uint16_t WUA:1; /* wakeup symbol received on channel A */ + uint16_t ABVA:1; /* aggregated boundary violation on channel A */ + uint16_t AACA:1; /* aggregated additional communication on channel A */ + uint16_t ACEA:1; /* aggregated content error on channel A */ + uint16_t ASEA:1; /* aggregated syntax error on channel A */ + uint16_t AVFA:1; /* aggregated valid frame on channel A */ + } B; + } PSR3_t; + typedef union uCIFRR { + uint16_t R; + struct { + uint16_t:8; + uint16_t MIFR:1; /* module interrupt flag */ + uint16_t PRIFR:1; /* protocol interrupt flag */ + uint16_t CHIFR:1; /* CHI interrupt flag */ + uint16_t WUPIFR:1; /* wakeup interrupt flag */ + uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ + uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ + uint16_t RBIFR:1; /* receive message buffer interrupt flag */ + uint16_t TBIFR:1; /* transmit buffer interrupt flag */ + } B; + } CIFRR_t; + typedef union uSFCNTR { + uint16_t R; + struct { + uint16_t SFEVB:4; /* sync frames channel B, even cycle */ + uint16_t SFEVA:4; /* sync frames channel A, even cycle */ + uint16_t SFODB:4; /* sync frames channel B, odd cycle */ + uint16_t SFODA:4; /* sync frames channel A, odd cycle */ + } B; + } SFCNTR_t; + + typedef union uSFTCCSR { + uint16_t R; + struct { + uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ + uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ + uint16_t CYCNUM:6; /* cycle number */ + uint16_t ELKS:1; /* even cycle tables lock status */ + uint16_t OLKS:1; /* odd cycle tables lock status */ + uint16_t EVAL:1; /* even cycle tables valid */ + uint16_t OVAL:1; /* odd cycle tables valid */ + uint16_t:1; + uint16_t OPT:1; /*one pair trigger */ + uint16_t SDVEN:1; /* sync frame deviation table enable */ + uint16_t SIDEN:1; /* sync frame ID table enable */ + } B; + } SFTCCSR_t; + typedef union uSFIDRFR { + uint16_t R; + struct { + uint16_t:6; + uint16_t SYNFRID:10; /* sync frame rejection ID */ + } B; + } SFIDRFR_t; + + typedef union uTICCR { + uint16_t R; + struct { + uint16_t:2; + uint16_t T2CFG:1; /* timer 2 configuration */ + uint16_t T2REP:1; /* timer 2 repetitive mode */ + uint16_t:1; + uint16_t T2SP:1; /* timer 2 stop */ + uint16_t T2TR:1; /* timer 2 trigger */ + uint16_t T2ST:1; /* timer 2 state */ + uint16_t:3; + uint16_t T1REP:1; /* timer 1 repetitive mode */ + uint16_t:1; + uint16_t T1SP:1; /* timer 1 stop */ + uint16_t T1TR:1; /* timer 1 trigger */ + uint16_t T1ST:1; /* timer 1 state */ + + } B; + } TICCR_t; + typedef union uTI1CYSR { + uint16_t R; + struct { + uint16_t:2; + uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ + uint16_t:2; + uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ + + } B; + } TI1CYSR_t; + + typedef union uSSSR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* static slot number */ + uint16_t:1; + uint16_t SLOTNUMBER:11; /* selector */ + } B; + } SSSR_t; + + typedef union uSSCCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:1; + uint16_t CNTCFG:2; /* counter configuration */ + uint16_t MCY:1; /* multi cycle selection */ + uint16_t VFR:1; /* valid frame selection */ + uint16_t SYF:1; /* sync frame selection */ + uint16_t NUF:1; /* null frame selection */ + uint16_t SUF:1; /* startup frame selection */ + uint16_t STATUSMASK:4; /* slot status mask */ + } B; + } SSCCR_t; + typedef union uSSR { + uint16_t R; + struct { + uint16_t VFB:1; /* valid frame on channel B */ + uint16_t SYB:1; /* valid sync frame on channel B */ + uint16_t NFB:1; /* valid null frame on channel B */ + uint16_t SUB:1; /* valid startup frame on channel B */ + uint16_t SEB:1; /* syntax error on channel B */ + uint16_t CEB:1; /* content error on channel B */ + uint16_t BVB:1; /* boundary violation on channel B */ + uint16_t TCB:1; /* tx conflict on channel B */ + uint16_t VFA:1; /* valid frame on channel A */ + uint16_t SYA:1; /* valid sync frame on channel A */ + uint16_t NFA:1; /* valid null frame on channel A */ + uint16_t SUA:1; /* valid startup frame on channel A */ + uint16_t SEA:1; /* syntax error on channel A */ + uint16_t CEA:1; /* content error on channel A */ + uint16_t BVA:1; /* boundary violation on channel A */ + uint16_t TCA:1; /* tx conflict on channel A */ + } B; + } SSR_t; + typedef union uMTSCFR { + uint16_t R; + struct { + uint16_t MTE:1; /* media access test symbol transmission enable */ + uint16_t:1; + uint16_t CYCCNTMSK:6; /* cycle counter mask */ + uint16_t:2; + uint16_t CYCCNTVAL:6; /* cycle counter value */ + } B; + } MTSCFR_t; + typedef union uRSBIR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:4; + uint16_t RSBIDX:8; /* receive shadow buffer index */ + } B; + } RSBIR_t; + typedef union uRFDSR { + uint16_t R; + struct { + uint16_t FIFODEPTH:8; /* fifo depth */ + uint16_t:1; + uint16_t ENTRYSIZE:7; /* entry size */ + } B; + } RFDSR_t; + + typedef union uRFRFCFR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t IBD:1; /* interval boundary */ + uint16_t SEL:2; /* filter number */ + uint16_t:1; + uint16_t SID:11; /* slot ID */ + } B; + } RFRFCFR_t; + + typedef union uRFRFCTR { + uint16_t R; + struct { + uint16_t:4; + uint16_t F3MD:1; /* filter mode */ + uint16_t F2MD:1; /* filter mode */ + uint16_t F1MD:1; /* filter mode */ + uint16_t F0MD:1; /* filter mode */ + uint16_t:4; + uint16_t F3EN:1; /* filter enable */ + uint16_t F2EN:1; /* filter enable */ + uint16_t F1EN:1; /* filter enable */ + uint16_t F0EN:1; /* filter enable */ + } B; + } RFRFCTR_t; + typedef union uPCR0 { + uint16_t R; + struct { + uint16_t ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_LENGTH:10; + } B; + } PCR0_t; + + typedef union uPCR1 { + uint16_t R; + struct { + uint16_t:2; + uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; + } B; + } PCR1_t; + + typedef union uPCR2 { + uint16_t R; + struct { + uint16_t MINISLOT_AFTER_ACTION_POINT:6; + uint16_t NUMBER_OF_STATIC_SLOTS:10; + } B; + } PCR2_t; + + typedef union uPCR3 { + uint16_t R; + struct { + uint16_t WAKEUP_SYMBOL_RX_LOW:6; + uint16_t MINISLOT_ACTION_POINT_OFFSET:5; + uint16_t COLDSTART_ATTEMPTS:5; + } B; + } PCR3_t; + + typedef union uPCR4 { + uint16_t R; + struct { + uint16_t CAS_RX_LOW_MAX:7; + uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; + } B; + } PCR4_t; + + typedef union uPCR5 { + uint16_t R; + struct { + uint16_t TSS_TRANSMITTER:4; + uint16_t WAKEUP_SYMBOL_TX_LOW:6; + uint16_t WAKEUP_SYMBOL_RX_IDLE:6; + } B; + } PCR5_t; + + typedef union uPCR6 { + uint16_t R; + struct { + uint16_t:1; + uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; + uint16_t MACRO_INITIAL_OFFSET_A:7; + } B; + } PCR6_t; + + typedef union uPCR7 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_B:9; + uint16_t MICRO_PER_MACRO_NOM_HALF:7; + } B; + } PCR7_t; + + typedef union uPCR8 { + uint16_t R; + struct { + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; + uint16_t WAKEUP_SYMBOL_TX_IDLE:8; + } B; + } PCR8_t; + + typedef union uPCR9 { + uint16_t R; + struct { + uint16_t MINISLOT_EXISTS:1; + uint16_t SYMBOL_WINDOW_EXISTS:1; + uint16_t OFFSET_CORRECTION_OUT:14; + } B; + } PCR9_t; + + typedef union uPCR10 { + uint16_t R; + struct { + uint16_t SINGLE_SLOT_ENABLED:1; + uint16_t WAKEUP_CHANNEL:1; + uint16_t MACRO_PER_CYCLE:14; + } B; + } PCR10_t; + + typedef union uPCR11 { + uint16_t R; + struct { + uint16_t KEY_SLOT_USED_FOR_STARTUP:1; + uint16_t KEY_SLOT_USED_FOR_SYNC:1; + uint16_t OFFSET_CORRECTION_START:14; + } B; + } PCR11_t; + + typedef union uPCR12 { + uint16_t R; + struct { + uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; + uint16_t KEY_SLOT_HEADER_CRC:11; + } B; + } PCR12_t; + + typedef union uPCR13 { + uint16_t R; + struct { + uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; + } B; + } PCR13_t; + + typedef union uPCR14 { + uint16_t R; + struct { + uint16_t RATE_CORRECTION_OUT:11; + uint16_t LISTEN_TIMEOUT_H:5; + } B; + } PCR14_t; + + typedef union uPCR15 { + uint16_t R; + struct { + uint16_t LISTEN_TIMEOUT_L:16; + } B; + } PCR15_t; + + typedef union uPCR16 { + uint16_t R; + struct { + uint16_t MACRO_INITIAL_OFFSET_B:7; + uint16_t NOISE_LISTEN_TIMEOUT_H:9; + } B; + } PCR16_t; + + typedef union uPCR17 { + uint16_t R; + struct { + uint16_t NOISE_LISTEN_TIMEOUT_L:16; + } B; + } PCR17_t; + + typedef union uPCR18 { + uint16_t R; + struct { + uint16_t WAKEUP_PATTERN:6; + uint16_t KEY_SLOT_ID:10; + } B; + } PCR18_t; + + typedef union uPCR19 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_A:9; + uint16_t PAYLOAD_LENGTH_STATIC:7; + } B; + } PCR19_t; + + typedef union uPCR20 { + uint16_t R; + struct { + uint16_t MICRO_INITIAL_OFFSET_B:8; + uint16_t MICRO_INITIAL_OFFSET_A:8; + } B; + } PCR20_t; + + typedef union uPCR21 { + uint16_t R; + struct { + uint16_t EXTERN_RATE_CORRECTION:3; + uint16_t LATEST_TX:13; + } B; + } PCR21_t; + + typedef union uPCR22 { + uint16_t R; + struct { + uint16_t:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; + uint16_t MICRO_PER_CYCLE_H:4; + } B; + } PCR22_t; + + typedef union uPCR23 { + uint16_t R; + struct { + uint16_t micro_per_cycle_l:16; + } B; + } PCR23_t; + + typedef union uPCR24 { + uint16_t R; + struct { + uint16_t CLUSTER_DRIFT_DAMPING:5; + uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; + uint16_t MICRO_PER_CYCLE_MIN_H:4; + } B; + } PCR24_t; + + typedef union uPCR25 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MIN_L:16; + } B; + } PCR25_t; + + typedef union uPCR26 { + uint16_t R; + struct { + uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; + uint16_t MICRO_PER_CYCLE_MAX_H:4; + } B; + } PCR26_t; + + typedef union uPCR27 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MAX_L:16; + } B; + } PCR27_t; + + typedef union uPCR28 { + uint16_t R; + struct { + uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; + uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; + } B; + } PCR28_t; + + typedef union uPCR29 { + uint16_t R; + struct { + uint16_t EXTERN_OFFSET_CORRECTION:3; + uint16_t MINISLOTS_MAX:13; + } B; + } PCR29_t; + + typedef union uPCR30 { + uint16_t R; + struct { + uint16_t:12; + uint16_t SYNC_NODE_MAX:4; + } B; + } PCR30_t; + + typedef struct uMSG_BUFF_CCS { + union { + uint16_t R; + struct { + uint16_t:1; + uint16_t MCM:1; /* message buffer commit mode */ + uint16_t MBT:1; /* message buffer type */ + uint16_t MTD:1; /* message buffer direction */ + uint16_t CMT:1; /* commit for transmission */ + uint16_t EDT:1; /* enable / disable trigger */ + uint16_t LCKT:1; /* lock request trigger */ + uint16_t MBIE:1; /* message buffer interrupt enable */ + uint16_t:3; + uint16_t DUP:1; /* data updated */ + uint16_t DVAL:1; /* data valid */ + uint16_t EDS:1; /* lock status */ + uint16_t LCKS:1; /* enable / disable status */ + uint16_t MBIF:1; /* message buffer interrupt flag */ + } B; + } MBCCSR; + union { + uint16_t R; + struct { + uint16_t MTM:1; /* message buffer transmission mode */ + uint16_t CHNLA:1; /* channel assignement */ + uint16_t CHNLB:1; /* channel assignement */ + uint16_t CCFE:1; /* cycle counter filter enable */ + uint16_t CCFMSK:6; /* cycle counter filter mask */ + uint16_t CCFVAL:6; /* cycle counter filter value */ + } B; + } MBCCFR; + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t FID:11; /* frame ID */ + } B; + } MBFIDR; + union { + uint16_t R; + struct { + uint16_t:8; + uint16_t MBIDX:8; /* message buffer index */ + } B; + } MBIDXR; + } MSG_BUFF_CCS_t; + typedef union uSYSBADHR { + uint16_t R; + } SYSBADHR_t; + typedef union uSYSBADLR { + uint16_t R; + } SYSBADLR_t; + typedef union uPDAR { + uint16_t R; + } PDAR_t; + typedef union uCASERCR { + uint16_t R; + } CASERCR_t; + typedef union uCBSERCR { + uint16_t R; + } CBSERCR_t; + typedef union uCYCTR { + uint16_t R; + } CYCTR_t; + typedef union uMTCTR { + uint16_t R; + } MTCTR_t; + typedef union uSLTCTAR { + uint16_t R; + } SLTCTAR_t; + typedef union uSLTCTBR { + uint16_t R; + } SLTCTBR_t; + typedef union uRTCORVR { + uint16_t R; + } RTCORVR_t; + typedef union uOFCORVR { + uint16_t R; + } OFCORVR_t; + typedef union uSFTOR { + uint16_t R; + } SFTOR_t; + typedef union uSFIDAFVR { + uint16_t R; + } SFIDAFVR_t; + typedef union uSFIDAFMR { + uint16_t R; + } SFIDAFMR_t; + typedef union uNMVR { + uint16_t R; + } NMVR_t; + typedef union uNMVLR { + uint16_t R; + } NMVLR_t; + typedef union uT1MTOR { + uint16_t R; + } T1MTOR_t; + typedef union uTI2CR0 { + uint16_t R; + } TI2CR0_t; + typedef union uTI2CR1 { + uint16_t R; + } TI2CR1_t; + typedef union uSSCR { + uint16_t R; + } SSCR_t; + typedef union uRFSR { + uint16_t R; + } RFSR_t; + typedef union uRFSIR { + uint16_t R; + } RFSIR_t; + typedef union uRFARIR { + uint16_t R; + } RFARIR_t; + typedef union uRFBRIR { + uint16_t R; + } RFBRIR_t; + typedef union uRFMIDAFVR { + uint16_t R; + } RFMIDAFVR_t; + typedef union uRFMIAFMR { + uint16_t R; + } RFMIAFMR_t; + typedef union uRFFIDRFVR { + uint16_t R; + } RFFIDRFVR_t; + typedef union uRFFIDRFMR { + uint16_t R; + } RFFIDRFMR_t; + typedef union uLDTXSLAR { + uint16_t R; + } LDTXSLAR_t; + typedef union uLDTXSLBR { + uint16_t R; + } LDTXSLBR_t; + + typedef struct FR_tag { + volatile MVR_t MVR; /*module version register *//*0 */ + volatile MCR_t MCR; /*module configuration register *//*2 */ + volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ + volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ + volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ + volatile STBPCR_t STBPCR; /*strobe port control register *//*A */ + volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ + volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ + uint16_t reserved3a[1]; /*10 */ + volatile PDAR_t PDAR; /*PE data register *//*12 */ + volatile POCR_t POCR; /*Protocol operation control register *//*14 */ + volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ + volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ + volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ + volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ + volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ + volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ + volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ + volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ + volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ + volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ + volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ + volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ + volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ + volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ + volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ + volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ + volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ + volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ + volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ + volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ + uint16_t reserved3[1]; /*3E */ + volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ + volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ + volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ + volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ + volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ + volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ + volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ + volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ + volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ + volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ + volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ + volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ + volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ + volatile SSSR_t SSSR; /*slot status selection register *//*64 */ + volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ + volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ + volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ + volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ + volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ + volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ + volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ + volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ + volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ + volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ + volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ + volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ + volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ + volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ + volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ + volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ + volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ + volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ + volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ + volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ + volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ + volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ + volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ + volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ + volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ + volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ + volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ + volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ + volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ + volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ + volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ + volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ + volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ + volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ + volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ + volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ + volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ + volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ + volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ + volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ + volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ + volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ + volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ + volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ + volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ + volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ + volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ + volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ + volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ + volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ + uint16_t reserved2[17]; + volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ + } FR_tag_t; + + typedef union uF_HEADER /* frame header */ + { + struct { + uint16_t:5; + uint16_t HDCRC:11; /* Header CRC */ + uint16_t:2; + uint16_t CYCCNT:6; /* Cycle Count */ + uint16_t:1; + uint16_t PLDLEN:7; /* Payload Length */ + uint16_t:1; + uint16_t PPI:1; /* Payload Preamble Indicator */ + uint16_t NUF:1; /* Null Frame Indicator */ + uint16_t SYF:1; /* Sync Frame Indicator */ + uint16_t SUF:1; /* Startup Frame Indicator */ + uint16_t FID:11; /* Frame ID */ + } B; + uint16_t WORDS[3]; + } F_HEADER_t; + typedef union uS_STSTUS /* slot status */ + { + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t CH:1; /* Channel */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t:1; + } RX; + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t TCB:1; /* Tx Conflict on channel B */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t TCA:1; /* Tx Conflict on channel A */ + } TX; + uint16_t R; + } S_STATUS_t; + + typedef struct uMB_HEADER /* message buffer header */ + { + F_HEADER_t FRAME_HEADER; + uint16_t DATA_OFFSET; + S_STATUS_t SLOT_STATUS; + } MB_HEADER_t; + +/* Define memories */ + +#define SRAM_START 0x40000000 +#define SRAM_SIZE 0x14000 +#define SRAM_END 0x40013FFF + +#define FLASH_START 0x0 +#define FLASH_SIZE 0x200000 +#define FLASH_END 0x1FFFFF + +/* Define instances of modules */ +#define PBRIDGE_A (*(volatile struct PBRIDGE_A_tag *) 0xC3F00000) +#define FMPLL (*(volatile struct FMPLL_tag *) 0xC3F80000) +#define EBI (*(volatile struct EBI_tag *) 0xC3F84000) +#define FLASH (*(volatile struct FLASH_tag *) 0xC3F88000) +#define SIU (*(volatile struct SIU_tag *) 0xC3F90000) + +#define EMIOS (*(volatile struct EMIOS_tag *) 0xC3FA0000) +#define ETPU (*(volatile struct ETPU_tag *) 0xC3FC0000) +#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) +#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) +#define ETPU_DATA_RAM_END 0xC3FC89FC +#define CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) + +#define PBRIDGE_B (*(volatile struct PBRIDGE_B_tag *) 0xFFF00000) +#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000) +#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000) +#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000) +#define INTC (*(volatile struct INTC_tag *) 0xFFF48000) + +#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000) + +#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000) +#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000) +#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000) +#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000) + +#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFB0000) +#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFB4000) + +#define CAN_A (*(volatile struct FLEXCAN2_tag *) 0xFFFC0000) +#define CAN_B (*(volatile struct FLEXCAN2_tag *) 0xFFFC4000) +#define CAN_C (*(volatile struct FLEXCAN2_tag *) 0xFFFC8000) +#define CAN_D (*(volatile struct FLEXCAN2_tag *) 0xFFFCC000) +#define CAN_E (*(volatile struct FLEXCAN2_tag *) 0xFFFD0000) + +#define FEC (*(volatile struct FEC_tag *) 0xFFF4C000) + +#define FR (*(volatile struct FR_tag *) 0xFFFE0000) + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ +#endif /* ifdef _MPC5567_H */ +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ diff --git a/bsps/powerpc/include/mpc55xx/fsl-mpc564xL.h b/bsps/powerpc/include/mpc55xx/fsl-mpc564xL.h new file mode 100644 index 0000000000..61217ac656 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/fsl-mpc564xL.h @@ -0,0 +1,20666 @@ +/* + * Modifications of the original file provided by Freescale Semiconductor and + * ST Microelectronics are: + * + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/****************************************************************************\ + * PROJECT : MPC5643L + * FILE : mpc5643l.h + * + * DESCRIPTION : This is the header file describing the register + * set for the named projects. + * + * COPYRIGHT : (c) 2009, Freescale Semiconductor & ST Microelectronics + * + * VERSION : 1.04 + * RELEASE DATE : Tue Dec 1 2009 + * CREATION DATE : Thu Oct 8 13:53:51 CEST 2009 + * AUTHOR : generated from IP-XACT database + * HISTORY : Preliminary release. +\****************************************************************************/ + +/* >>>> NOTE! this file is auto-generated please do not edit it! <<<< */ + +/****************************************************************************\ + * Example instantiation and use: + * + * ..B. = 1; + * ..R = 0x10000000; + * +\****************************************************************************/ + +/* + * LICENSE: + * Copyright (c) 2006 Freescale Semiconductor + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice + * shall be included in all copies or substantial portions + * of the Software. + * + * THIS SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _leopard_H_ /* prevents multiple inclusions of this file */ +#define _leopard_H_ + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +//#define USE_FIELD_ALIASES_CFLASH +//#define USE_FIELD_ALIASES_SIUL +//#define USE_FIELD_ALIASES_SSCM +//#define USE_FIELD_ALIASES_ME +//#define USE_FIELD_ALIASES_RGM +//#define USE_FIELD_ALIASES_ADC +//#define USE_FIELD_ALIASES_CTU +//#define USE_FIELD_ALIASES_mcTIMER +//#define USE_FIELD_ALIASES_mcPWM +//#define USE_FIELD_ALIASES_LINFLEX +//#define USE_FIELD_ALIASES_SPP_MCM +#define USE_FIELD_ALIASES_INTC +#define USE_FIELD_ALIASES_DSPI +//#define USE_FIELD_ALIASES_FLEXCAN +//#define USE_FIELD_ALIASES_FR +//#define USE_FIELD_ALIASES_CMU +//#define USE_FIELD_ALIASES_PLLD +//#define USE_FIELD_ALIASES_SPP_DMA2 + +/* Define memories */ + +#define SRAM_START 0x40000000 +#define SRAM_SIZE 0x20000 +#define SRAM_END 0x4001FFFF + +#define FLASH_START 0x0 +#define FLASH_SIZE 0xC0000 +#define FLASH_END 0xBFFFF + +/****************************************************************/ +/* */ +/* Global definitions and aliases */ +/* */ +/****************************************************************/ + +/* + Platform blocks that are only accessible by the second core (core 1) when + the device is in DPM mode. The block definition is equivalent to the one + for the first core (core 0) and reuses the related block structure. + + NOTE: the _1 defines are the preferred method for programming + */ +#define PBRIDGE_1 (*(volatile PBRIDGE_tag*) 0x8FF00000UL) +#define MAX_1 (*(volatile MAX_tag*) 0x8FF04000UL) +#define MPU_1 (*(volatile MPU_tag*) 0x8FF10000UL) +#define SEMA4_1 (*(volatile SEMA4_tag*) 0x8FF24000UL) +#define SWT_1 (*(volatile SWT_tag*) 0x8FF38000UL) +#define STM_1 (*(volatile STM_tag*) 0x8FF3C000UL) +#define SPP_MCM_1 (*(volatile SPP_MCM_tag*) 0x8FF40000UL) +#define SPP_DMA2_1 (*(volatile SPP_DMA2_tag*) 0x8FF44000UL) +#define INTC_1 (*(volatile INTC_tag*) 0x8FF48000UL) + +/* + Platform blocks that are only accessible by the second core (core 1) when + the device is in DPM mode. The block definition is equivalent to the one + for the first core (core 0) and reuses the related block structure. + + NOTE: the _DPM defines are deprecated, use _1 for + programming the corresponding blocks for new code instead. + */ +#define PBRIDGE_DPM PBRIDGE_1 +#define MAX_DPM MAX_1 +#define MPU_DPM MPU_1 +#define SEMA4_DPM SEMA4_1 +#define SWT_DPM SWT_1 +#define STM_DPM STM_1 +#define SPP_MCM_DPM SPP_MCM_1 +#define SPP_DMA2_DPM SPP_DMA2_1 +#define INTC_DPM INTC_1 + +/* Aliases for Pictus Module names */ +#define CAN_0 FLEXCAN_A +#define CAN_1 FLEXCAN_B +#define CTU_0 CTU +#define DFLASH CRC +#define DMAMUX DMA_CH_MUX +#define DSPI_0 DSPI_A +#define DSPI_1 DSPI_B +#define DSPI_2 DSPI_C +#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) +#define ETIMER_0 mcTIMER0 +#define ETIMER_1 mcTIMER1 +#define FLEXPWM_0 mcPWM_A +#define FLEXPWM_1 mcPWM_B +#define LINFLEX_0 LINFLEX0 +#define LINFLEX_1 LINFLEX1 +#define MCM_ SPP_MCM +#define PIT PIT_RTI +#define SIU SIUL +#define WKUP WKPU +#define ADC_0 ADC0 +#define ADC_1 ADC1 + +/* Other Aliases */ +#define AIPS_DPM PBRIDGE_1 +#define AIPS_1 PBRIDGE_1 +#define AIPS PBRIDGE + +/****************************************************************/ +/* */ +/* Module: CFLASH_SHADOW */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers NVPWD... */ + + typedef union { /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ + uint32_t R; + struct { + uint32_t PWD:32; /* PassWorD */ + } B; + } CFLASH_SHADOW_NVPWD_32B_tag; + + + /* Register layout for all registers NVSCI... */ + + typedef union { /* NVSCI - Non Volatile System Censoring Information Register */ + uint32_t R; + struct { + uint32_t SC:16; /* Serial Censorship Control Word */ + uint32_t CW:16; /* Censorship Control Word */ + } B; + } CFLASH_SHADOW_NVSCI_32B_tag; + + typedef union { /* Non Volatile LML Default Value */ + uint32_t R; + } CFLASH_SHADOW_NVLML_32B_tag; + + typedef union { /* Non Volatile HBL Default Value */ + uint32_t R; + } CFLASH_SHADOW_NVHBL_32B_tag; + + typedef union { /* Non Volatile SLL Default Value */ + uint32_t R; + } CFLASH_SHADOW_NVSLL_32B_tag; + + + /* Register layout for all registers NVBIU... */ + + typedef union { /* Non Volatile Bus Interface Unit Register */ + uint32_t R; + struct { + uint32_t BI:32; /* Bus interface Unit */ + } B; + } CFLASH_SHADOW_NVBIU_32B_tag; + + typedef union { /* NVUSRO - Non Volatile USeR Options Register */ + uint32_t R; + struct { + uint32_t UO:32; /* User Options */ + } B; + } CFLASH_SHADOW_NVUSRO_32B_tag; + + + typedef struct CFLASH_SHADOW_BIU_DEFAULTS_struct_tag { + + /* Non Volatile Bus Interface Unit Register */ + CFLASH_SHADOW_NVBIU_32B_tag NVBIU; /* relative offset: 0x0000 */ + int8_t CFLASH_SHADOW_BIU_DEFAULTS_reserved_0004[4]; + + } CFLASH_SHADOW_BIU_DEFAULTS_tag; + + + typedef struct CFLASH_SHADOW_struct_tag { /* start of CFLASH_SHADOW_tag */ + int8_t CFLASH_SHADOW_reserved_0000_C[15832]; + union { + /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ + CFLASH_SHADOW_NVPWD_32B_tag NVPWD[2]; /* offset: 0x3DD8 (0x0004 x 2) */ + + struct { + /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ + CFLASH_SHADOW_NVPWD_32B_tag NVPWD0; /* offset: 0x3DD8 size: 32 bit */ + CFLASH_SHADOW_NVPWD_32B_tag NVPWD1; /* offset: 0x3DDC size: 32 bit */ + }; + + }; + union { + /* NVSCI - Non Volatile System Censoring Information Register */ + CFLASH_SHADOW_NVSCI_32B_tag NVSCI[2]; /* offset: 0x3DE0 (0x0004 x 2) */ + + struct { + /* NVSCI - Non Volatile System Censoring Information Register */ + CFLASH_SHADOW_NVSCI_32B_tag NVSCI0; /* offset: 0x3DE0 size: 32 bit */ + CFLASH_SHADOW_NVSCI_32B_tag NVSCI1; /* offset: 0x3DE4 size: 32 bit */ + }; + + }; + /* Non Volatile LML Default Value */ + CFLASH_SHADOW_NVLML_32B_tag NVLML; /* offset: 0x3DE8 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3DEC[4]; + /* Non Volatile HBL Default Value */ + CFLASH_SHADOW_NVHBL_32B_tag NVHBL; /* offset: 0x3DF0 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3DF4[4]; + /* Non Volatile SLL Default Value */ + CFLASH_SHADOW_NVSLL_32B_tag NVSLL; /* offset: 0x3DF8 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3DFC_C[4]; + union { + /* Register set BIU_DEFAULTS */ + CFLASH_SHADOW_BIU_DEFAULTS_tag BIU_DEFAULTS[3]; /* offset: 0x3E00 (0x0008 x 3) */ + + struct { + /* Non Volatile Bus Interface Unit Register */ + CFLASH_SHADOW_NVBIU_32B_tag NVBIU2; /* offset: 0x3E00 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3E04_I1[4]; + CFLASH_SHADOW_NVBIU_32B_tag NVBIU3; /* offset: 0x3E08 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3E0C_I1[4]; + CFLASH_SHADOW_NVBIU_32B_tag NVBIU4; /* offset: 0x3E10 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3E14_E1[4]; + }; + + }; + /* NVUSRO - Non Volatile USeR Options Register */ + CFLASH_SHADOW_NVUSRO_32B_tag NVUSRO; /* offset: 0x3E18 size: 32 bit */ + } CFLASH_SHADOW_tag; + + +#define CFLASH_SHADOW (*(volatile CFLASH_SHADOW_tag *) 0x00F00000UL) + + + +/****************************************************************/ +/* */ +/* Module: CFLASH */ +/* */ +/****************************************************************/ + + typedef union { /* MCR - Module Configuration Register */ + uint32_t R; + struct { + uint32_t:5; + uint32_t SIZE:3; /* Array Space Size */ + uint32_t:1; + uint32_t LAS:3; /* Low Address Space */ + uint32_t:3; + uint32_t MAS:1; /* Mid Address Space Configuration */ + uint32_t EER:1; /* ECC Event Error */ + uint32_t RWE:1; /* Read-while-Write Event Error */ + uint32_t SBC:1; /* Single Bit Correction */ + uint32_t:1; + uint32_t PEAS:1; /* Program/Erase Access Space */ + uint32_t DONE:1; /* modify operation DONE */ + uint32_t PEG:1; /* Program/Erase Good */ + uint32_t:4; + uint32_t PGM:1; /* Program Bit */ + uint32_t PSUS:1; /* Program Suspend */ + uint32_t ERS:1; /* Erase Bit */ + uint32_t ESUS:1; /* Erase Suspend */ + uint32_t EHV:1; /* Enable High Voltage */ + } B; + } CFLASH_MCR_32B_tag; + + typedef union { /* LML - Low/Mid Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t LME:1; /* Low/Mid Address Space Block Enable */ + uint32_t:10; +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t SLOCK:1; /* Shadow Address Space Block Lock */ +#else + uint32_t TSLK:1; /* deprecated name - please avoid */ +#endif + uint32_t:2; +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t MLOCK:2; /* Mid Address Space Block Lock */ +#else + uint32_t MLK:2; /* deprecated name - please avoid */ +#endif + uint32_t:6; + uint32_t LLOCK:10; /* Low Address Space Block Lock */ + } B; + } CFLASH_LML_32B_tag; + + typedef union { /* HBL - High Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t HBE:1; /* High Address Space Block Enable */ + uint32_t:25; + uint32_t HLOCK:6; /* High Address Space Block Lock */ + } B; + } CFLASH_HBL_32B_tag; + + typedef union { /* SLL - Secondary Low/Mid Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t SLE:1; /* Secondary Low/Mid Address Space Block Enable */ + uint32_t:10; +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t SSLOCK:1; /* Secondary Shadow Address Space Block Lock */ +#else + uint32_t STSLK:1; /* deprecated name - please avoid */ +#endif + uint32_t:2; +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t SMLOCK:2; /* Secondary Mid Address Space Block Lock */ +#else + uint32_t SMK:2; /* deprecated name - please avoid */ +#endif + uint32_t:6; + uint32_t SLLOCK:10; /* Secondary Low Address Space Block Lock */ + } B; + } CFLASH_SLL_32B_tag; + + typedef union { /* LMS - Low/Mid Address Space Block Select Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MSL:2; /* Mid Address Space Block Select */ + uint32_t:6; + uint32_t LSL:10; /* Low Address Space Block Select */ + } B; + } CFLASH_LMS_32B_tag; + + typedef union { /* HBS - High Address Space Block Select Register */ + uint32_t R; + struct { + uint32_t:26; + uint32_t HSL:6; /* High Address Space Block Select */ + } B; + } CFLASH_HBS_32B_tag; + + typedef union { /* ADR - Address Register */ + uint32_t R; + struct { + uint32_t SAD:1; /* Shadow Address */ + uint32_t:10; + uint32_t ADDR:18; /* Address */ + uint32_t:3; + } B; + } CFLASH_ADR_32B_tag; + + typedef union { /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_APC:5; /* Bank0+2 Address Pipelining Control */ +#else + uint32_t BK0_APC:5; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_WWSC:5; /* Bank0+2 Write Wait State Control */ +#else + uint32_t BK0_WWSC:5; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_RWSC:5; /* Bank0+2 Read Wait State Control */ +#else + uint32_t BK0_RWSC:5; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_RWWC2:1; /* Bank 0+2 Read While Write Control, bit 2 */ +#else + uint32_t BK0_RWWC2:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_RWWC1:1; /* Bank 0+2 Read While Write Control, bit 1 */ +#else + uint32_t BK0_RWWC1:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P1_BCFG:2; /* Bank0+2 Port 1 Page Buffer Configuration */ +#else + uint32_t B0_P1_BCFG:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P1_DPFE:1; /* Bank0+2 Port 1 Data Prefetch Enable */ +#else + uint32_t B0_P1_DPFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P1_IPFE:1; /* Bank0+2 Port 1 Inst Prefetch Enable */ +#else + uint32_t B0_P1_IPFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P1_PFLM:2; /* Bank0+2 Port 1 Prefetch Limit */ +#else + uint32_t B0_P1_PFLM:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P1_BFE:1; /* Bank0+2 Port 1 Buffer Enable */ +#else + uint32_t B0_P1_BFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_RWWC0:1; /* Bank 0+2 Read While Write Control, bit 0 */ +#else + uint32_t BK0_RWWC0:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P0_BCFG:2; /* Bank0+2 Port 0 Page Buffer Configuration */ +#else + uint32_t B0_P0_BCFG:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P0_DPFE:1; /* Bank0+2 Port 0 Data Prefetch Enable */ +#else + uint32_t B0_P0_DPFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P0_IPFE:1; /* Bank0+2 Port 0 Inst Prefetch Enable */ +#else + uint32_t B0_P0_IPFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P0_PFLM:2; /* Bank0+2 Port 0 Prefetch Limit */ +#else + uint32_t B0_P0_PFLM:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P0_BFE:1; /* Bank0+2 Port 0 Buffer Enable */ +#else + uint32_t B0_P0_BFE:1; /* deprecated name - please avoid */ +#endif + } B; + } CFLASH_PFCR0_32B_tag; + + + /* Register layout for all registers BIU... */ + + typedef union { /* Bus Interface Unit Register */ + uint32_t R; + } CFLASH_BIU_32B_tag; + + typedef union { /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B1_APC:5; /* Bank 1 Address Pipelining Control */ + uint32_t B1_WWSC:5; /* Bank 1 Write Wait State Control */ + uint32_t B1_RWSC:5; /* Bank 1 Read Wait State Control */ + uint32_t B1_RWWC2:1; /* Bank1 Read While Write Control, bit 2 */ + uint32_t B1_RWWC1:1; /* Bank1 Read While Write Control, bit 1 */ + uint32_t:6; + uint32_t B1_P1_BFE:1; /* Bank 1 Port 1 Buffer Enable */ + uint32_t B1_RWWC0:1; /* Bank1 Read While Write Control, bit 0 */ + uint32_t:6; + uint32_t B1_P0_BFE:1; /* Bank 1 Port 0 Buffer Enable */ +#else + uint32_t BK1_APC:5; + uint32_t BK1_WWSC:5; + uint32_t BK1_RWSC:5; + uint32_t BK1_RWWC2:1; + uint32_t BK1_RWWC1:1; + uint32_t:6; + uint32_t B0_P1_BFE:1; + uint32_t BK1_RWWC0:1; + uint32_t:6; + uint32_t B1_P0_BFE:1; +#endif + } B; + } CFLASH_PFCR1_32B_tag; + + typedef union { /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */ + uint32_t R; + struct { + uint32_t:6; + uint32_t ARBM:2; /* Arbitration Mode */ + uint32_t M7PFD:1; /* Master x Prefetch Disable */ + uint32_t M6PFD:1; /* Master x Prefetch Disable */ + uint32_t M5PFD:1; /* Master x Prefetch Disable */ + uint32_t M4PFD:1; /* Master x Prefetch Disable */ + uint32_t M3PFD:1; /* Master x Prefetch Disable */ + uint32_t M2PFD:1; /* Master x Prefetch Disable */ + uint32_t M1PFD:1; /* Master x Prefetch Disable */ + uint32_t M0PFD:1; /* Master x Prefetch Disable */ + uint32_t M7AP:2; /* Master 7 Access Protection */ + uint32_t M6AP:2; /* Master 6 Access Protection */ + uint32_t M5AP:2; /* Master 5 Access Protection */ + uint32_t M4AP:2; /* Master 4 Access Protection */ + uint32_t M3AP:2; /* Master 3 Access Protection */ + uint32_t M2AP:2; /* Master 2 Access Protection */ + uint32_t M1AP:2; /* Master 1 Access Protection */ + uint32_t M0AP:2; /* Master 0 Access Protection */ + } B; + } CFLASH_PFAPR_32B_tag; + + typedef union { /* UT0 - User Test Register */ + uint32_t R; + struct { + uint32_t UTE:1; /* User Test Enable */ + uint32_t SBCE:1; /* Single Bit Correction Enable */ + uint32_t:6; + uint32_t DSI:8; /* Data Syndrome Input */ + uint32_t:10; + uint32_t MRE:1; /* Margin Read Enable */ + uint32_t MRV:1; /* Margin Read Value */ + uint32_t EIE:1; /* ECC Data Input Enable */ + uint32_t AIS:1; /* Array Integrity Sequence */ + uint32_t AIE:1; /* Array Integrity Enable */ + uint32_t AID:1; /* Array Integrity Done */ + } B; + } CFLASH_UT0_32B_tag; + + typedef union { /* UT1 - User Test Register */ + uint32_t R; + } CFLASH_UT1_32B_tag; + + typedef union { /* UT2 - User Test Register */ + uint32_t R; + } CFLASH_UT2_32B_tag; + + + /* Register layout for all registers UM... */ + + typedef union { /* UM - User Multiple Input Signature Register */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t MISR:32; /* Multiple Input Signature */ +#else + uint32_t MS:32; /* deprecated - please avoid */ +#endif + } B; + } CFLASH_UM_32B_tag; + + + /* Register layout for generated register(s) UT... */ + + typedef union { /* */ + uint32_t R; + } CFLASH_UT_32B_tag; + + + /* Register layout for generated register(s) PFCR... */ + + typedef union { /* */ + uint32_t R; + } CFLASH_PFCR_32B_tag; + + + + typedef struct CFLASH_struct_tag { /* start of CFLASH_tag */ + /* MCR - Module Configuration Register */ + CFLASH_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ + /* LML - Low/Mid Address Space Block Locking Register */ + CFLASH_LML_32B_tag LML; /* offset: 0x0004 size: 32 bit */ + /* HBL - High Address Space Block Locking Register */ + CFLASH_HBL_32B_tag HBL; /* offset: 0x0008 size: 32 bit */ + /* SLL - Secondary Low/Mid Address Space Block Locking Register */ + CFLASH_SLL_32B_tag SLL; /* offset: 0x000C size: 32 bit */ + /* LMS - Low/Mid Address Space Block Select Register */ + CFLASH_LMS_32B_tag LMS; /* offset: 0x0010 size: 32 bit */ + /* HBS - High Address Space Block Select Register */ + CFLASH_HBS_32B_tag HBS; /* offset: 0x0014 size: 32 bit */ + /* ADR - Address Register */ + CFLASH_ADR_32B_tag ADR; /* offset: 0x0018 size: 32 bit */ + union { + struct { + /* */ + CFLASH_PFCR_32B_tag PFCR[2]; /* offset: 0x001C (0x0004 x 2) */ + int8_t CFLASH_reserved_0024_E0[12]; + }; + + /* Bus Interface Unit Register */ + CFLASH_BIU_32B_tag BIU[5]; /* offset: 0x001C (0x0004 x 5) */ + + struct { + /* Bus Interface Unit Register */ + CFLASH_BIU_32B_tag BIU0; /* offset: 0x001C size: 32 bit */ + CFLASH_BIU_32B_tag BIU1; /* offset: 0x0020 size: 32 bit */ + CFLASH_BIU_32B_tag BIU2; /* offset: 0x0024 size: 32 bit */ + CFLASH_BIU_32B_tag BIU3; /* offset: 0x0028 size: 32 bit */ + CFLASH_BIU_32B_tag BIU4; /* offset: 0x002C size: 32 bit */ + }; + + struct { + int8_t CFLASH_reserved_001C_I3[8]; + CFLASH_PFAPR_32B_tag FAPR; /* deprecated - please avoid */ + int8_t CFLASH_reserved_0028_E3[8]; + }; + + struct { + /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */ + CFLASH_PFCR0_32B_tag PFCR0; /* offset: 0x001C size: 32 bit */ + /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */ + CFLASH_PFCR1_32B_tag PFCR1; /* offset: 0x0020 size: 32 bit */ + /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */ + CFLASH_PFAPR_32B_tag PFAPR; /* offset: 0x0024 size: 32 bit */ + int8_t CFLASH_reserved_0028_E4[8]; + }; + + }; + int8_t CFLASH_reserved_0030_C[12]; + union { + CFLASH_UT_32B_tag UT[3]; /* offset: 0x003C (0x0004 x 3) */ + + struct { + /* UT0 - User Test Register */ + CFLASH_UT0_32B_tag UT0; /* offset: 0x003C size: 32 bit */ + /* UT1 - User Test Register */ + CFLASH_UT1_32B_tag UT1; /* offset: 0x0040 size: 32 bit */ + /* UT2 - User Test Register */ + CFLASH_UT2_32B_tag UT2; /* offset: 0x0044 size: 32 bit */ + }; + + }; + union { + CFLASH_UM_32B_tag UMISR[5]; /* offset: 0x0048 (0x0004 x 5) */ + + /* UM - User Multiple Input Signature Register */ + CFLASH_UM_32B_tag UM[5]; /* offset: 0x0048 (0x0004 x 5) */ + + struct { + /* UM - User Multiple Input Signature Register */ + CFLASH_UM_32B_tag UM0; /* offset: 0x0048 size: 32 bit */ + CFLASH_UM_32B_tag UM1; /* offset: 0x004C size: 32 bit */ + CFLASH_UM_32B_tag UM2; /* offset: 0x0050 size: 32 bit */ + CFLASH_UM_32B_tag UM3; /* offset: 0x0054 size: 32 bit */ + CFLASH_UM_32B_tag UM4; /* offset: 0x0058 size: 32 bit */ + }; + + }; + } CFLASH_tag; + + +#define CFLASH (*(volatile CFLASH_tag *) 0xC3F88000UL) + + + +/****************************************************************/ +/* */ +/* Module: SIUL */ +/* */ +/****************************************************************/ + + typedef union { /* MIDR1 - MCU ID Register #1 */ + uint32_t R; + struct { + uint32_t PARTNUM:16; /* MCU Part Number */ + uint32_t CSP:1; /* CSP Package */ + uint32_t PKG:5; /* Package Settings */ + uint32_t:2; +#ifndef USE_FIELD_ALIASES_SIUL + uint32_t MAJOR_MASK:4; /* Major Mask Revision */ +#else + uint32_t MAJORMASK:4; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SIUL + uint32_t MINOR_MASK:4; /* Minor Mask Revision */ +#else + uint32_t MINORMASK:4; /* deprecated name - please avoid */ +#endif + } B; + } SIUL_MIDR1_32B_tag; + + typedef union { /* MIDR2 - MCU ID Register #2 */ + uint32_t R; + struct { + uint32_t SF:1; /* Manufacturer */ + uint32_t FLASH_SIZE_1:4; /* Coarse Flash Memory Size */ + uint32_t FLASH_SIZE_2:4; /* Fine Flash Memory Size */ + uint32_t:7; +#ifndef USE_FIELD_ALIASES_SIUL + uint32_t PARTNUM2:8; /* MCU Part Number */ +#else + uint32_t PARTNUM:8; /* deprecated name - please avoid */ +#endif + uint32_t TBD:1; /* Optional Bit */ + uint32_t:2; + uint32_t EE:1; /* Data Flash Present */ + uint32_t:3; + uint32_t FR:1; /* Flexray Present */ + } B; + } SIUL_MIDR2_32B_tag; + + typedef union { /* ISR - Interrupt Status Flag Register */ + uint32_t R; + struct { + uint32_t EIF31:1; /* External Interrupt Status Flag */ + uint32_t EIF30:1; /* External Interrupt Status Flag */ + uint32_t EIF29:1; /* External Interrupt Status Flag */ + uint32_t EIF28:1; /* External Interrupt Status Flag */ + uint32_t EIF27:1; /* External Interrupt Status Flag */ + uint32_t EIF26:1; /* External Interrupt Status Flag */ + uint32_t EIF25:1; /* External Interrupt Status Flag */ + uint32_t EIF24:1; /* External Interrupt Status Flag */ + uint32_t EIF23:1; /* External Interrupt Status Flag */ + uint32_t EIF22:1; /* External Interrupt Status Flag */ + uint32_t EIF21:1; /* External Interrupt Status Flag */ + uint32_t EIF20:1; /* External Interrupt Status Flag */ + uint32_t EIF19:1; /* External Interrupt Status Flag */ + uint32_t EIF18:1; /* External Interrupt Status Flag */ + uint32_t EIF17:1; /* External Interrupt Status Flag */ + uint32_t EIF16:1; /* External Interrupt Status Flag */ + uint32_t EIF15:1; /* External Interrupt Status Flag */ + uint32_t EIF14:1; /* External Interrupt Status Flag */ + uint32_t EIF13:1; /* External Interrupt Status Flag */ + uint32_t EIF12:1; /* External Interrupt Status Flag */ + uint32_t EIF11:1; /* External Interrupt Status Flag */ + uint32_t EIF10:1; /* External Interrupt Status Flag */ + uint32_t EIF9:1; /* External Interrupt Status Flag */ + uint32_t EIF8:1; /* External Interrupt Status Flag */ + uint32_t EIF7:1; /* External Interrupt Status Flag */ + uint32_t EIF6:1; /* External Interrupt Status Flag */ + uint32_t EIF5:1; /* External Interrupt Status Flag */ + uint32_t EIF4:1; /* External Interrupt Status Flag */ + uint32_t EIF3:1; /* External Interrupt Status Flag */ + uint32_t EIF2:1; /* External Interrupt Status Flag */ + uint32_t EIF1:1; /* External Interrupt Status Flag */ + uint32_t EIF0:1; /* External Interrupt Status Flag */ + } B; + } SIUL_ISR_32B_tag; + + typedef union { /* IRER - Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t EIRE31:1; /* Enable External Interrupt Requests */ + uint32_t EIRE30:1; /* Enable External Interrupt Requests */ + uint32_t EIRE29:1; /* Enable External Interrupt Requests */ + uint32_t EIRE28:1; /* Enable External Interrupt Requests */ + uint32_t EIRE27:1; /* Enable External Interrupt Requests */ + uint32_t EIRE26:1; /* Enable External Interrupt Requests */ + uint32_t EIRE25:1; /* Enable External Interrupt Requests */ + uint32_t EIRE24:1; /* Enable External Interrupt Requests */ + uint32_t EIRE23:1; /* Enable External Interrupt Requests */ + uint32_t EIRE22:1; /* Enable External Interrupt Requests */ + uint32_t EIRE21:1; /* Enable External Interrupt Requests */ + uint32_t EIRE20:1; /* Enable External Interrupt Requests */ + uint32_t EIRE19:1; /* Enable External Interrupt Requests */ + uint32_t EIRE18:1; /* Enable External Interrupt Requests */ + uint32_t EIRE17:1; /* Enable External Interrupt Requests */ + uint32_t EIRE16:1; /* Enable External Interrupt Requests */ + uint32_t EIRE15:1; /* Enable External Interrupt Requests */ + uint32_t EIRE14:1; /* Enable External Interrupt Requests */ + uint32_t EIRE13:1; /* Enable External Interrupt Requests */ + uint32_t EIRE12:1; /* Enable External Interrupt Requests */ + uint32_t EIRE11:1; /* Enable External Interrupt Requests */ + uint32_t EIRE10:1; /* Enable External Interrupt Requests */ + uint32_t EIRE9:1; /* Enable External Interrupt Requests */ + uint32_t EIRE8:1; /* Enable External Interrupt Requests */ + uint32_t EIRE7:1; /* Enable External Interrupt Requests */ + uint32_t EIRE6:1; /* Enable External Interrupt Requests */ + uint32_t EIRE5:1; /* Enable External Interrupt Requests */ + uint32_t EIRE4:1; /* Enable External Interrupt Requests */ + uint32_t EIRE3:1; /* Enable External Interrupt Requests */ + uint32_t EIRE2:1; /* Enable External Interrupt Requests */ + uint32_t EIRE1:1; /* Enable External Interrupt Requests */ + uint32_t EIRE0:1; /* Enable External Interrupt Requests */ + } B; + } SIUL_IRER_32B_tag; + + typedef union { /* IREER - Interrupt Rising Edge Event Enable */ + uint32_t R; + struct { + uint32_t IREE31:1; /* Enable rising-edge events */ + uint32_t IREE30:1; /* Enable rising-edge events */ + uint32_t IREE29:1; /* Enable rising-edge events */ + uint32_t IREE28:1; /* Enable rising-edge events */ + uint32_t IREE27:1; /* Enable rising-edge events */ + uint32_t IREE26:1; /* Enable rising-edge events */ + uint32_t IREE25:1; /* Enable rising-edge events */ + uint32_t IREE24:1; /* Enable rising-edge events */ + uint32_t IREE23:1; /* Enable rising-edge events */ + uint32_t IREE22:1; /* Enable rising-edge events */ + uint32_t IREE21:1; /* Enable rising-edge events */ + uint32_t IREE20:1; /* Enable rising-edge events */ + uint32_t IREE19:1; /* Enable rising-edge events */ + uint32_t IREE18:1; /* Enable rising-edge events */ + uint32_t IREE17:1; /* Enable rising-edge events */ + uint32_t IREE16:1; /* Enable rising-edge events */ + uint32_t IREE15:1; /* Enable rising-edge events */ + uint32_t IREE14:1; /* Enable rising-edge events */ + uint32_t IREE13:1; /* Enable rising-edge events */ + uint32_t IREE12:1; /* Enable rising-edge events */ + uint32_t IREE11:1; /* Enable rising-edge events */ + uint32_t IREE10:1; /* Enable rising-edge events */ + uint32_t IREE9:1; /* Enable rising-edge events */ + uint32_t IREE8:1; /* Enable rising-edge events */ + uint32_t IREE7:1; /* Enable rising-edge events */ + uint32_t IREE6:1; /* Enable rising-edge events */ + uint32_t IREE5:1; /* Enable rising-edge events */ + uint32_t IREE4:1; /* Enable rising-edge events */ + uint32_t IREE3:1; /* Enable rising-edge events */ + uint32_t IREE2:1; /* Enable rising-edge events */ + uint32_t IREE1:1; /* Enable rising-edge events */ + uint32_t IREE0:1; /* Enable rising-edge events */ + } B; + } SIUL_IREER_32B_tag; + + typedef union { /* IFEER - Interrupt Falling-Edge Event Enable */ + uint32_t R; + struct { + uint32_t IFEE31:1; /* Enable Falling Edge Events */ + uint32_t IFEE30:1; /* Enable Falling Edge Events */ + uint32_t IFEE29:1; /* Enable Falling Edge Events */ + uint32_t IFEE28:1; /* Enable Falling Edge Events */ + uint32_t IFEE27:1; /* Enable Falling Edge Events */ + uint32_t IFEE26:1; /* Enable Falling Edge Events */ + uint32_t IFEE25:1; /* Enable Falling Edge Events */ + uint32_t IFEE24:1; /* Enable Falling Edge Events */ + uint32_t IFEE23:1; /* Enable Falling Edge Events */ + uint32_t IFEE22:1; /* Enable Falling Edge Events */ + uint32_t IFEE21:1; /* Enable Falling Edge Events */ + uint32_t IFEE20:1; /* Enable Falling Edge Events */ + uint32_t IFEE19:1; /* Enable Falling Edge Events */ + uint32_t IFEE18:1; /* Enable Falling Edge Events */ + uint32_t IFEE17:1; /* Enable Falling Edge Events */ + uint32_t IFEE16:1; /* Enable Falling Edge Events */ + uint32_t IFEE15:1; /* Enable Falling Edge Events */ + uint32_t IFEE14:1; /* Enable Falling Edge Events */ + uint32_t IFEE13:1; /* Enable Falling Edge Events */ + uint32_t IFEE12:1; /* Enable Falling Edge Events */ + uint32_t IFEE11:1; /* Enable Falling Edge Events */ + uint32_t IFEE10:1; /* Enable Falling Edge Events */ + uint32_t IFEE9:1; /* Enable Falling Edge Events */ + uint32_t IFEE8:1; /* Enable Falling Edge Events */ + uint32_t IFEE7:1; /* Enable Falling Edge Events */ + uint32_t IFEE6:1; /* Enable Falling Edge Events */ + uint32_t IFEE5:1; /* Enable Falling Edge Events */ + uint32_t IFEE4:1; /* Enable Falling Edge Events */ + uint32_t IFEE3:1; /* Enable Falling Edge Events */ + uint32_t IFEE2:1; /* Enable Falling Edge Events */ + uint32_t IFEE1:1; /* Enable Falling Edge Events */ + uint32_t IFEE0:1; /* Enable Falling Edge Events */ + } B; + } SIUL_IFEER_32B_tag; + + typedef union { /* IFER Interrupt Filter Enable Register */ + uint32_t R; + struct { + uint32_t IFE31:1; /* Enable Digital Glitch Filter */ + uint32_t IFE30:1; /* Enable Digital Glitch Filter */ + uint32_t IFE29:1; /* Enable Digital Glitch Filter */ + uint32_t IFE28:1; /* Enable Digital Glitch Filter */ + uint32_t IFE27:1; /* Enable Digital Glitch Filter */ + uint32_t IFE26:1; /* Enable Digital Glitch Filter */ + uint32_t IFE25:1; /* Enable Digital Glitch Filter */ + uint32_t IFE24:1; /* Enable Digital Glitch Filter */ + uint32_t IFE23:1; /* Enable Digital Glitch Filter */ + uint32_t IFE22:1; /* Enable Digital Glitch Filter */ + uint32_t IFE21:1; /* Enable Digital Glitch Filter */ + uint32_t IFE20:1; /* Enable Digital Glitch Filter */ + uint32_t IFE19:1; /* Enable Digital Glitch Filter */ + uint32_t IFE18:1; /* Enable Digital Glitch Filter */ + uint32_t IFE17:1; /* Enable Digital Glitch Filter */ + uint32_t IFE16:1; /* Enable Digital Glitch Filter */ + uint32_t IFE15:1; /* Enable Digital Glitch Filter */ + uint32_t IFE14:1; /* Enable Digital Glitch Filter */ + uint32_t IFE13:1; /* Enable Digital Glitch Filter */ + uint32_t IFE12:1; /* Enable Digital Glitch Filter */ + uint32_t IFE11:1; /* Enable Digital Glitch Filter */ + uint32_t IFE10:1; /* Enable Digital Glitch Filter */ + uint32_t IFE9:1; /* Enable Digital Glitch Filter */ + uint32_t IFE8:1; /* Enable Digital Glitch Filter */ + uint32_t IFE7:1; /* Enable Digital Glitch Filter */ + uint32_t IFE6:1; /* Enable Digital Glitch Filter */ + uint32_t IFE5:1; /* Enable Digital Glitch Filter */ + uint32_t IFE4:1; /* Enable Digital Glitch Filter */ + uint32_t IFE3:1; /* Enable Digital Glitch Filter */ + uint32_t IFE2:1; /* Enable Digital Glitch Filter */ + uint32_t IFE1:1; /* Enable Digital Glitch Filter */ + uint32_t IFE0:1; /* Enable Digital Glitch Filter */ + } B; + } SIUL_IFER_32B_tag; + + + /* Register layout for all registers PCR... */ + + typedef union SIU_PCR_tag { /* PCR - Pad Configuration Register */ + uint16_t R; + struct { + uint16_t:1; +#ifndef USE_FIELD_ALIASES_SIUL + uint16_t SMC:1; /* Safe Mode Control */ +#else + uint16_t SME:1; /* deprecated name - please avoid */ +#endif + uint16_t APC:1; /* Analog Pad Control */ + uint16_t:1; + uint16_t PA:2; /* Pad Output Assignment */ + uint16_t OBE:1; /* Output Buffer Enable */ + uint16_t IBE:1; /* Input Buffer Enable */ +#ifndef USE_FIELD_ALIASES_SIUL + uint16_t DSC:2; /* Drive Strength Control */ +#else + uint16_t DCS:2; /* deprecated name - please avoid */ +#endif + uint16_t ODE:1; /* Open Drain Output Enable */ + uint16_t HYS:1; /* Input Hysteresis */ + uint16_t SRC:2; /* Slew Rate Control */ + uint16_t WPE:1; /* Weak Pull Up/Down Enable */ + uint16_t WPS:1; /* Weak Pull Up/Down Select */ + } B; + } SIU_PCR_tag; + + + /* Register layout for all registers PSMI... */ + + typedef union SIUL_PSMI_8B_tag { /* PSMI - Pad Selection for Multiplexed Inputs */ + uint8_t R; + struct { + uint8_t:4; + uint8_t PADSEL:4; /* Pad selection for pin */ + } B; + } SIUL_PSMI_8B_tag; + + + /* Register layout for all registers PSMI... */ + + typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */ + uint32_t R; + struct { + uint32_t:4; + uint32_t PADSEL0:4; /* Pad selection for pin */ + uint32_t:4; + uint32_t PADSEL1:4; /* Pad selection for pin */ + uint32_t:4; + uint32_t PADSEL2:4; /* Pad selection for pin */ + uint32_t:4; + uint32_t PADSEL3:4; /* Pad selection for pin */ + } B; + } SIUL_PSMI_32B_tag; + + + /* Register layout for all registers GPDO... */ + + typedef union { /* GPDO - GPIO Pad Data Output Register */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDO:1; /* Pad Data Out */ + } B; + } SIUL_GPDO_8B_tag; + + + /* Register layout for all registers GPDO... */ + + typedef union { /* GPDO - GPIO Pad Data Output Register */ + uint32_t R; + struct { + uint32_t:7; + uint32_t PDO0:1; /* Pad Data Out */ + uint32_t:7; + uint32_t PDO1:1; /* Pad Data Out */ + uint32_t:7; + uint32_t PDO2:1; /* Pad Data Out */ + uint32_t:7; + uint32_t PDO3:1; /* Pad Data Out */ + } B; + } SIUL_GPDO_32B_tag; + + + /* Register layout for all registers GPDI... */ + + typedef union { /* GPDI - GPIO Pad Data Input Register */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; /* Pad Data In */ + } B; + } SIUL_GPDI_8B_tag; + + + /* Register layout for all registers GPDI... */ + + typedef union { /* GPDI - GPIO Pad Data Input Register */ + uint32_t R; + struct { + uint32_t:7; + uint32_t PDI0:1; /* Pad Data In */ + uint32_t:7; + uint32_t PDI1:1; /* Pad Data In */ + uint32_t:7; + uint32_t PDI2:1; /* Pad Data In */ + uint32_t:7; + uint32_t PDI3:1; /* Pad Data In */ + } B; + } SIUL_GPDI_32B_tag; + + + /* Register layout for all registers PGPDO... */ + + typedef union { /* PGPDO - Parallel GPIO Pad Data Out Register */ + uint16_t R; + } SIUL_PGPDO_16B_tag; + + + /* Register layout for all registers PGPDI... */ + + typedef union { /* PGPDI - Parallel GPIO Pad Data In Register */ + uint16_t R; + } SIUL_PGPDI_16B_tag; + + + /* Register layout for all registers MPGPDO... */ + + typedef union { /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ + uint32_t R; + struct { + uint32_t MASK:16; /* Mask Field */ + uint32_t MPPDO:16; /* Masked Parallel Pad Data Out */ + } B; + } SIUL_MPGPDO_32B_tag; + + + /* Register layout for all registers IFMC... */ + + typedef union { /* IFMC - Interrupt Filter Maximum Counter Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t MAXCNT:4; /* Maximum Interrupt Filter Counter Setting */ + } B; + } SIUL_IFMC_32B_tag; + + typedef union { /* IFCPR - Inerrupt Filter Clock Prescaler Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t IFCP:4; /* Interrupt Filter Clock Prescaler Setting */ + } B; + } SIUL_IFCPR_32B_tag; + + + + typedef struct SIU_tag { /* start of SIUL_tag */ + int8_t SIUL_reserved_0000_C[4]; + union { + SIUL_MIDR1_32B_tag MIDR; /* deprecated - please avoid */ + + /* MIDR1 - MCU ID Register #1 */ + SIUL_MIDR1_32B_tag MIDR1; /* offset: 0x0004 size: 32 bit */ + + }; + /* MIDR2 - MCU ID Register #2 */ + SIUL_MIDR2_32B_tag MIDR2; /* offset: 0x0008 size: 32 bit */ + int8_t SIUL_reserved_000C[8]; + /* ISR - Interrupt Status Flag Register */ + SIUL_ISR_32B_tag ISR; /* offset: 0x0014 size: 32 bit */ + /* IRER - Interrupt Request Enable Register */ + SIUL_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */ + int8_t SIUL_reserved_001C[12]; + /* IREER - Interrupt Rising Edge Event Enable */ + SIUL_IREER_32B_tag IREER; /* offset: 0x0028 size: 32 bit */ + /* IFEER - Interrupt Falling-Edge Event Enable */ + SIUL_IFEER_32B_tag IFEER; /* offset: 0x002C size: 32 bit */ + /* IFER Interrupt Filter Enable Register */ + SIUL_IFER_32B_tag IFER; /* offset: 0x0030 size: 32 bit */ + int8_t SIUL_reserved_0034_C[12]; + union { + /* PCR - Pad Configuration Register */ + SIU_PCR_tag PCR[512]; /* offset: 0x0040 (0x0002 x 512) */ + + struct { + /* PCR - Pad Configuration Register */ + SIU_PCR_tag PCR0; /* offset: 0x0040 size: 16 bit */ + SIU_PCR_tag PCR1; /* offset: 0x0042 size: 16 bit */ + SIU_PCR_tag PCR2; /* offset: 0x0044 size: 16 bit */ + SIU_PCR_tag PCR3; /* offset: 0x0046 size: 16 bit */ + SIU_PCR_tag PCR4; /* offset: 0x0048 size: 16 bit */ + SIU_PCR_tag PCR5; /* offset: 0x004A size: 16 bit */ + SIU_PCR_tag PCR6; /* offset: 0x004C size: 16 bit */ + SIU_PCR_tag PCR7; /* offset: 0x004E size: 16 bit */ + SIU_PCR_tag PCR8; /* offset: 0x0050 size: 16 bit */ + SIU_PCR_tag PCR9; /* offset: 0x0052 size: 16 bit */ + SIU_PCR_tag PCR10; /* offset: 0x0054 size: 16 bit */ + SIU_PCR_tag PCR11; /* offset: 0x0056 size: 16 bit */ + SIU_PCR_tag PCR12; /* offset: 0x0058 size: 16 bit */ + SIU_PCR_tag PCR13; /* offset: 0x005A size: 16 bit */ + SIU_PCR_tag PCR14; /* offset: 0x005C size: 16 bit */ + SIU_PCR_tag PCR15; /* offset: 0x005E size: 16 bit */ + SIU_PCR_tag PCR16; /* offset: 0x0060 size: 16 bit */ + SIU_PCR_tag PCR17; /* offset: 0x0062 size: 16 bit */ + SIU_PCR_tag PCR18; /* offset: 0x0064 size: 16 bit */ + SIU_PCR_tag PCR19; /* offset: 0x0066 size: 16 bit */ + SIU_PCR_tag PCR20; /* offset: 0x0068 size: 16 bit */ + SIU_PCR_tag PCR21; /* offset: 0x006A size: 16 bit */ + SIU_PCR_tag PCR22; /* offset: 0x006C size: 16 bit */ + SIU_PCR_tag PCR23; /* offset: 0x006E size: 16 bit */ + SIU_PCR_tag PCR24; /* offset: 0x0070 size: 16 bit */ + SIU_PCR_tag PCR25; /* offset: 0x0072 size: 16 bit */ + SIU_PCR_tag PCR26; /* offset: 0x0074 size: 16 bit */ + SIU_PCR_tag PCR27; /* offset: 0x0076 size: 16 bit */ + SIU_PCR_tag PCR28; /* offset: 0x0078 size: 16 bit */ + SIU_PCR_tag PCR29; /* offset: 0x007A size: 16 bit */ + SIU_PCR_tag PCR30; /* offset: 0x007C size: 16 bit */ + SIU_PCR_tag PCR31; /* offset: 0x007E size: 16 bit */ + SIU_PCR_tag PCR32; /* offset: 0x0080 size: 16 bit */ + SIU_PCR_tag PCR33; /* offset: 0x0082 size: 16 bit */ + SIU_PCR_tag PCR34; /* offset: 0x0084 size: 16 bit */ + SIU_PCR_tag PCR35; /* offset: 0x0086 size: 16 bit */ + SIU_PCR_tag PCR36; /* offset: 0x0088 size: 16 bit */ + SIU_PCR_tag PCR37; /* offset: 0x008A size: 16 bit */ + SIU_PCR_tag PCR38; /* offset: 0x008C size: 16 bit */ + SIU_PCR_tag PCR39; /* offset: 0x008E size: 16 bit */ + SIU_PCR_tag PCR40; /* offset: 0x0090 size: 16 bit */ + SIU_PCR_tag PCR41; /* offset: 0x0092 size: 16 bit */ + SIU_PCR_tag PCR42; /* offset: 0x0094 size: 16 bit */ + SIU_PCR_tag PCR43; /* offset: 0x0096 size: 16 bit */ + SIU_PCR_tag PCR44; /* offset: 0x0098 size: 16 bit */ + SIU_PCR_tag PCR45; /* offset: 0x009A size: 16 bit */ + SIU_PCR_tag PCR46; /* offset: 0x009C size: 16 bit */ + SIU_PCR_tag PCR47; /* offset: 0x009E size: 16 bit */ + SIU_PCR_tag PCR48; /* offset: 0x00A0 size: 16 bit */ + SIU_PCR_tag PCR49; /* offset: 0x00A2 size: 16 bit */ + SIU_PCR_tag PCR50; /* offset: 0x00A4 size: 16 bit */ + SIU_PCR_tag PCR51; /* offset: 0x00A6 size: 16 bit */ + SIU_PCR_tag PCR52; /* offset: 0x00A8 size: 16 bit */ + SIU_PCR_tag PCR53; /* offset: 0x00AA size: 16 bit */ + SIU_PCR_tag PCR54; /* offset: 0x00AC size: 16 bit */ + SIU_PCR_tag PCR55; /* offset: 0x00AE size: 16 bit */ + SIU_PCR_tag PCR56; /* offset: 0x00B0 size: 16 bit */ + SIU_PCR_tag PCR57; /* offset: 0x00B2 size: 16 bit */ + SIU_PCR_tag PCR58; /* offset: 0x00B4 size: 16 bit */ + SIU_PCR_tag PCR59; /* offset: 0x00B6 size: 16 bit */ + SIU_PCR_tag PCR60; /* offset: 0x00B8 size: 16 bit */ + SIU_PCR_tag PCR61; /* offset: 0x00BA size: 16 bit */ + SIU_PCR_tag PCR62; /* offset: 0x00BC size: 16 bit */ + SIU_PCR_tag PCR63; /* offset: 0x00BE size: 16 bit */ + SIU_PCR_tag PCR64; /* offset: 0x00C0 size: 16 bit */ + SIU_PCR_tag PCR65; /* offset: 0x00C2 size: 16 bit */ + SIU_PCR_tag PCR66; /* offset: 0x00C4 size: 16 bit */ + SIU_PCR_tag PCR67; /* offset: 0x00C6 size: 16 bit */ + SIU_PCR_tag PCR68; /* offset: 0x00C8 size: 16 bit */ + SIU_PCR_tag PCR69; /* offset: 0x00CA size: 16 bit */ + SIU_PCR_tag PCR70; /* offset: 0x00CC size: 16 bit */ + SIU_PCR_tag PCR71; /* offset: 0x00CE size: 16 bit */ + SIU_PCR_tag PCR72; /* offset: 0x00D0 size: 16 bit */ + SIU_PCR_tag PCR73; /* offset: 0x00D2 size: 16 bit */ + SIU_PCR_tag PCR74; /* offset: 0x00D4 size: 16 bit */ + SIU_PCR_tag PCR75; /* offset: 0x00D6 size: 16 bit */ + SIU_PCR_tag PCR76; /* offset: 0x00D8 size: 16 bit */ + SIU_PCR_tag PCR77; /* offset: 0x00DA size: 16 bit */ + SIU_PCR_tag PCR78; /* offset: 0x00DC size: 16 bit */ + SIU_PCR_tag PCR79; /* offset: 0x00DE size: 16 bit */ + SIU_PCR_tag PCR80; /* offset: 0x00E0 size: 16 bit */ + SIU_PCR_tag PCR81; /* offset: 0x00E2 size: 16 bit */ + SIU_PCR_tag PCR82; /* offset: 0x00E4 size: 16 bit */ + SIU_PCR_tag PCR83; /* offset: 0x00E6 size: 16 bit */ + SIU_PCR_tag PCR84; /* offset: 0x00E8 size: 16 bit */ + SIU_PCR_tag PCR85; /* offset: 0x00EA size: 16 bit */ + SIU_PCR_tag PCR86; /* offset: 0x00EC size: 16 bit */ + SIU_PCR_tag PCR87; /* offset: 0x00EE size: 16 bit */ + SIU_PCR_tag PCR88; /* offset: 0x00F0 size: 16 bit */ + SIU_PCR_tag PCR89; /* offset: 0x00F2 size: 16 bit */ + SIU_PCR_tag PCR90; /* offset: 0x00F4 size: 16 bit */ + SIU_PCR_tag PCR91; /* offset: 0x00F6 size: 16 bit */ + SIU_PCR_tag PCR92; /* offset: 0x00F8 size: 16 bit */ + SIU_PCR_tag PCR93; /* offset: 0x00FA size: 16 bit */ + SIU_PCR_tag PCR94; /* offset: 0x00FC size: 16 bit */ + SIU_PCR_tag PCR95; /* offset: 0x00FE size: 16 bit */ + SIU_PCR_tag PCR96; /* offset: 0x0100 size: 16 bit */ + SIU_PCR_tag PCR97; /* offset: 0x0102 size: 16 bit */ + SIU_PCR_tag PCR98; /* offset: 0x0104 size: 16 bit */ + SIU_PCR_tag PCR99; /* offset: 0x0106 size: 16 bit */ + SIU_PCR_tag PCR100; /* offset: 0x0108 size: 16 bit */ + SIU_PCR_tag PCR101; /* offset: 0x010A size: 16 bit */ + SIU_PCR_tag PCR102; /* offset: 0x010C size: 16 bit */ + SIU_PCR_tag PCR103; /* offset: 0x010E size: 16 bit */ + SIU_PCR_tag PCR104; /* offset: 0x0110 size: 16 bit */ + SIU_PCR_tag PCR105; /* offset: 0x0112 size: 16 bit */ + SIU_PCR_tag PCR106; /* offset: 0x0114 size: 16 bit */ + SIU_PCR_tag PCR107; /* offset: 0x0116 size: 16 bit */ + SIU_PCR_tag PCR108; /* offset: 0x0118 size: 16 bit */ + SIU_PCR_tag PCR109; /* offset: 0x011A size: 16 bit */ + SIU_PCR_tag PCR110; /* offset: 0x011C size: 16 bit */ + SIU_PCR_tag PCR111; /* offset: 0x011E size: 16 bit */ + SIU_PCR_tag PCR112; /* offset: 0x0120 size: 16 bit */ + SIU_PCR_tag PCR113; /* offset: 0x0122 size: 16 bit */ + SIU_PCR_tag PCR114; /* offset: 0x0124 size: 16 bit */ + SIU_PCR_tag PCR115; /* offset: 0x0126 size: 16 bit */ + SIU_PCR_tag PCR116; /* offset: 0x0128 size: 16 bit */ + SIU_PCR_tag PCR117; /* offset: 0x012A size: 16 bit */ + SIU_PCR_tag PCR118; /* offset: 0x012C size: 16 bit */ + SIU_PCR_tag PCR119; /* offset: 0x012E size: 16 bit */ + SIU_PCR_tag PCR120; /* offset: 0x0130 size: 16 bit */ + SIU_PCR_tag PCR121; /* offset: 0x0132 size: 16 bit */ + SIU_PCR_tag PCR122; /* offset: 0x0134 size: 16 bit */ + SIU_PCR_tag PCR123; /* offset: 0x0136 size: 16 bit */ + SIU_PCR_tag PCR124; /* offset: 0x0138 size: 16 bit */ + SIU_PCR_tag PCR125; /* offset: 0x013A size: 16 bit */ + SIU_PCR_tag PCR126; /* offset: 0x013C size: 16 bit */ + SIU_PCR_tag PCR127; /* offset: 0x013E size: 16 bit */ + SIU_PCR_tag PCR128; /* offset: 0x0140 size: 16 bit */ + SIU_PCR_tag PCR129; /* offset: 0x0142 size: 16 bit */ + SIU_PCR_tag PCR130; /* offset: 0x0144 size: 16 bit */ + SIU_PCR_tag PCR131; /* offset: 0x0146 size: 16 bit */ + SIU_PCR_tag PCR132; /* offset: 0x0148 size: 16 bit */ + SIU_PCR_tag PCR133; /* offset: 0x014A size: 16 bit */ + SIU_PCR_tag PCR134; /* offset: 0x014C size: 16 bit */ + SIU_PCR_tag PCR135; /* offset: 0x014E size: 16 bit */ + SIU_PCR_tag PCR136; /* offset: 0x0150 size: 16 bit */ + SIU_PCR_tag PCR137; /* offset: 0x0152 size: 16 bit */ + SIU_PCR_tag PCR138; /* offset: 0x0154 size: 16 bit */ + SIU_PCR_tag PCR139; /* offset: 0x0156 size: 16 bit */ + SIU_PCR_tag PCR140; /* offset: 0x0158 size: 16 bit */ + SIU_PCR_tag PCR141; /* offset: 0x015A size: 16 bit */ + SIU_PCR_tag PCR142; /* offset: 0x015C size: 16 bit */ + SIU_PCR_tag PCR143; /* offset: 0x015E size: 16 bit */ + SIU_PCR_tag PCR144; /* offset: 0x0160 size: 16 bit */ + SIU_PCR_tag PCR145; /* offset: 0x0162 size: 16 bit */ + SIU_PCR_tag PCR146; /* offset: 0x0164 size: 16 bit */ + SIU_PCR_tag PCR147; /* offset: 0x0166 size: 16 bit */ + SIU_PCR_tag PCR148; /* offset: 0x0168 size: 16 bit */ + SIU_PCR_tag PCR149; /* offset: 0x016A size: 16 bit */ + SIU_PCR_tag PCR150; /* offset: 0x016C size: 16 bit */ + SIU_PCR_tag PCR151; /* offset: 0x016E size: 16 bit */ + SIU_PCR_tag PCR152; /* offset: 0x0170 size: 16 bit */ + SIU_PCR_tag PCR153; /* offset: 0x0172 size: 16 bit */ + SIU_PCR_tag PCR154; /* offset: 0x0174 size: 16 bit */ + SIU_PCR_tag PCR155; /* offset: 0x0176 size: 16 bit */ + SIU_PCR_tag PCR156; /* offset: 0x0178 size: 16 bit */ + SIU_PCR_tag PCR157; /* offset: 0x017A size: 16 bit */ + SIU_PCR_tag PCR158; /* offset: 0x017C size: 16 bit */ + SIU_PCR_tag PCR159; /* offset: 0x017E size: 16 bit */ + SIU_PCR_tag PCR160; /* offset: 0x0180 size: 16 bit */ + SIU_PCR_tag PCR161; /* offset: 0x0182 size: 16 bit */ + SIU_PCR_tag PCR162; /* offset: 0x0184 size: 16 bit */ + SIU_PCR_tag PCR163; /* offset: 0x0186 size: 16 bit */ + SIU_PCR_tag PCR164; /* offset: 0x0188 size: 16 bit */ + SIU_PCR_tag PCR165; /* offset: 0x018A size: 16 bit */ + SIU_PCR_tag PCR166; /* offset: 0x018C size: 16 bit */ + SIU_PCR_tag PCR167; /* offset: 0x018E size: 16 bit */ + SIU_PCR_tag PCR168; /* offset: 0x0190 size: 16 bit */ + SIU_PCR_tag PCR169; /* offset: 0x0192 size: 16 bit */ + SIU_PCR_tag PCR170; /* offset: 0x0194 size: 16 bit */ + SIU_PCR_tag PCR171; /* offset: 0x0196 size: 16 bit */ + SIU_PCR_tag PCR172; /* offset: 0x0198 size: 16 bit */ + SIU_PCR_tag PCR173; /* offset: 0x019A size: 16 bit */ + SIU_PCR_tag PCR174; /* offset: 0x019C size: 16 bit */ + SIU_PCR_tag PCR175; /* offset: 0x019E size: 16 bit */ + SIU_PCR_tag PCR176; /* offset: 0x01A0 size: 16 bit */ + SIU_PCR_tag PCR177; /* offset: 0x01A2 size: 16 bit */ + SIU_PCR_tag PCR178; /* offset: 0x01A4 size: 16 bit */ + SIU_PCR_tag PCR179; /* offset: 0x01A6 size: 16 bit */ + SIU_PCR_tag PCR180; /* offset: 0x01A8 size: 16 bit */ + SIU_PCR_tag PCR181; /* offset: 0x01AA size: 16 bit */ + SIU_PCR_tag PCR182; /* offset: 0x01AC size: 16 bit */ + SIU_PCR_tag PCR183; /* offset: 0x01AE size: 16 bit */ + SIU_PCR_tag PCR184; /* offset: 0x01B0 size: 16 bit */ + SIU_PCR_tag PCR185; /* offset: 0x01B2 size: 16 bit */ + SIU_PCR_tag PCR186; /* offset: 0x01B4 size: 16 bit */ + SIU_PCR_tag PCR187; /* offset: 0x01B6 size: 16 bit */ + SIU_PCR_tag PCR188; /* offset: 0x01B8 size: 16 bit */ + SIU_PCR_tag PCR189; /* offset: 0x01BA size: 16 bit */ + SIU_PCR_tag PCR190; /* offset: 0x01BC size: 16 bit */ + SIU_PCR_tag PCR191; /* offset: 0x01BE size: 16 bit */ + SIU_PCR_tag PCR192; /* offset: 0x01C0 size: 16 bit */ + SIU_PCR_tag PCR193; /* offset: 0x01C2 size: 16 bit */ + SIU_PCR_tag PCR194; /* offset: 0x01C4 size: 16 bit */ + SIU_PCR_tag PCR195; /* offset: 0x01C6 size: 16 bit */ + SIU_PCR_tag PCR196; /* offset: 0x01C8 size: 16 bit */ + SIU_PCR_tag PCR197; /* offset: 0x01CA size: 16 bit */ + SIU_PCR_tag PCR198; /* offset: 0x01CC size: 16 bit */ + SIU_PCR_tag PCR199; /* offset: 0x01CE size: 16 bit */ + SIU_PCR_tag PCR200; /* offset: 0x01D0 size: 16 bit */ + SIU_PCR_tag PCR201; /* offset: 0x01D2 size: 16 bit */ + SIU_PCR_tag PCR202; /* offset: 0x01D4 size: 16 bit */ + SIU_PCR_tag PCR203; /* offset: 0x01D6 size: 16 bit */ + SIU_PCR_tag PCR204; /* offset: 0x01D8 size: 16 bit */ + SIU_PCR_tag PCR205; /* offset: 0x01DA size: 16 bit */ + SIU_PCR_tag PCR206; /* offset: 0x01DC size: 16 bit */ + SIU_PCR_tag PCR207; /* offset: 0x01DE size: 16 bit */ + SIU_PCR_tag PCR208; /* offset: 0x01E0 size: 16 bit */ + SIU_PCR_tag PCR209; /* offset: 0x01E2 size: 16 bit */ + SIU_PCR_tag PCR210; /* offset: 0x01E4 size: 16 bit */ + SIU_PCR_tag PCR211; /* offset: 0x01E6 size: 16 bit */ + SIU_PCR_tag PCR212; /* offset: 0x01E8 size: 16 bit */ + SIU_PCR_tag PCR213; /* offset: 0x01EA size: 16 bit */ + SIU_PCR_tag PCR214; /* offset: 0x01EC size: 16 bit */ + SIU_PCR_tag PCR215; /* offset: 0x01EE size: 16 bit */ + SIU_PCR_tag PCR216; /* offset: 0x01F0 size: 16 bit */ + SIU_PCR_tag PCR217; /* offset: 0x01F2 size: 16 bit */ + SIU_PCR_tag PCR218; /* offset: 0x01F4 size: 16 bit */ + SIU_PCR_tag PCR219; /* offset: 0x01F6 size: 16 bit */ + SIU_PCR_tag PCR220; /* offset: 0x01F8 size: 16 bit */ + SIU_PCR_tag PCR221; /* offset: 0x01FA size: 16 bit */ + SIU_PCR_tag PCR222; /* offset: 0x01FC size: 16 bit */ + SIU_PCR_tag PCR223; /* offset: 0x01FE size: 16 bit */ + SIU_PCR_tag PCR224; /* offset: 0x0200 size: 16 bit */ + SIU_PCR_tag PCR225; /* offset: 0x0202 size: 16 bit */ + SIU_PCR_tag PCR226; /* offset: 0x0204 size: 16 bit */ + SIU_PCR_tag PCR227; /* offset: 0x0206 size: 16 bit */ + SIU_PCR_tag PCR228; /* offset: 0x0208 size: 16 bit */ + SIU_PCR_tag PCR229; /* offset: 0x020A size: 16 bit */ + SIU_PCR_tag PCR230; /* offset: 0x020C size: 16 bit */ + SIU_PCR_tag PCR231; /* offset: 0x020E size: 16 bit */ + SIU_PCR_tag PCR232; /* offset: 0x0210 size: 16 bit */ + SIU_PCR_tag PCR233; /* offset: 0x0212 size: 16 bit */ + SIU_PCR_tag PCR234; /* offset: 0x0214 size: 16 bit */ + SIU_PCR_tag PCR235; /* offset: 0x0216 size: 16 bit */ + SIU_PCR_tag PCR236; /* offset: 0x0218 size: 16 bit */ + SIU_PCR_tag PCR237; /* offset: 0x021A size: 16 bit */ + SIU_PCR_tag PCR238; /* offset: 0x021C size: 16 bit */ + SIU_PCR_tag PCR239; /* offset: 0x021E size: 16 bit */ + SIU_PCR_tag PCR240; /* offset: 0x0220 size: 16 bit */ + SIU_PCR_tag PCR241; /* offset: 0x0222 size: 16 bit */ + SIU_PCR_tag PCR242; /* offset: 0x0224 size: 16 bit */ + SIU_PCR_tag PCR243; /* offset: 0x0226 size: 16 bit */ + SIU_PCR_tag PCR244; /* offset: 0x0228 size: 16 bit */ + SIU_PCR_tag PCR245; /* offset: 0x022A size: 16 bit */ + SIU_PCR_tag PCR246; /* offset: 0x022C size: 16 bit */ + SIU_PCR_tag PCR247; /* offset: 0x022E size: 16 bit */ + SIU_PCR_tag PCR248; /* offset: 0x0230 size: 16 bit */ + SIU_PCR_tag PCR249; /* offset: 0x0232 size: 16 bit */ + SIU_PCR_tag PCR250; /* offset: 0x0234 size: 16 bit */ + SIU_PCR_tag PCR251; /* offset: 0x0236 size: 16 bit */ + SIU_PCR_tag PCR252; /* offset: 0x0238 size: 16 bit */ + SIU_PCR_tag PCR253; /* offset: 0x023A size: 16 bit */ + SIU_PCR_tag PCR254; /* offset: 0x023C size: 16 bit */ + SIU_PCR_tag PCR255; /* offset: 0x023E size: 16 bit */ + SIU_PCR_tag PCR256; /* offset: 0x0240 size: 16 bit */ + SIU_PCR_tag PCR257; /* offset: 0x0242 size: 16 bit */ + SIU_PCR_tag PCR258; /* offset: 0x0244 size: 16 bit */ + SIU_PCR_tag PCR259; /* offset: 0x0246 size: 16 bit */ + SIU_PCR_tag PCR260; /* offset: 0x0248 size: 16 bit */ + SIU_PCR_tag PCR261; /* offset: 0x024A size: 16 bit */ + SIU_PCR_tag PCR262; /* offset: 0x024C size: 16 bit */ + SIU_PCR_tag PCR263; /* offset: 0x024E size: 16 bit */ + SIU_PCR_tag PCR264; /* offset: 0x0250 size: 16 bit */ + SIU_PCR_tag PCR265; /* offset: 0x0252 size: 16 bit */ + SIU_PCR_tag PCR266; /* offset: 0x0254 size: 16 bit */ + SIU_PCR_tag PCR267; /* offset: 0x0256 size: 16 bit */ + SIU_PCR_tag PCR268; /* offset: 0x0258 size: 16 bit */ + SIU_PCR_tag PCR269; /* offset: 0x025A size: 16 bit */ + SIU_PCR_tag PCR270; /* offset: 0x025C size: 16 bit */ + SIU_PCR_tag PCR271; /* offset: 0x025E size: 16 bit */ + SIU_PCR_tag PCR272; /* offset: 0x0260 size: 16 bit */ + SIU_PCR_tag PCR273; /* offset: 0x0262 size: 16 bit */ + SIU_PCR_tag PCR274; /* offset: 0x0264 size: 16 bit */ + SIU_PCR_tag PCR275; /* offset: 0x0266 size: 16 bit */ + SIU_PCR_tag PCR276; /* offset: 0x0268 size: 16 bit */ + SIU_PCR_tag PCR277; /* offset: 0x026A size: 16 bit */ + SIU_PCR_tag PCR278; /* offset: 0x026C size: 16 bit */ + SIU_PCR_tag PCR279; /* offset: 0x026E size: 16 bit */ + SIU_PCR_tag PCR280; /* offset: 0x0270 size: 16 bit */ + SIU_PCR_tag PCR281; /* offset: 0x0272 size: 16 bit */ + SIU_PCR_tag PCR282; /* offset: 0x0274 size: 16 bit */ + SIU_PCR_tag PCR283; /* offset: 0x0276 size: 16 bit */ + SIU_PCR_tag PCR284; /* offset: 0x0278 size: 16 bit */ + SIU_PCR_tag PCR285; /* offset: 0x027A size: 16 bit */ + SIU_PCR_tag PCR286; /* offset: 0x027C size: 16 bit */ + SIU_PCR_tag PCR287; /* offset: 0x027E size: 16 bit */ + SIU_PCR_tag PCR288; /* offset: 0x0280 size: 16 bit */ + SIU_PCR_tag PCR289; /* offset: 0x0282 size: 16 bit */ + SIU_PCR_tag PCR290; /* offset: 0x0284 size: 16 bit */ + SIU_PCR_tag PCR291; /* offset: 0x0286 size: 16 bit */ + SIU_PCR_tag PCR292; /* offset: 0x0288 size: 16 bit */ + SIU_PCR_tag PCR293; /* offset: 0x028A size: 16 bit */ + SIU_PCR_tag PCR294; /* offset: 0x028C size: 16 bit */ + SIU_PCR_tag PCR295; /* offset: 0x028E size: 16 bit */ + SIU_PCR_tag PCR296; /* offset: 0x0290 size: 16 bit */ + SIU_PCR_tag PCR297; /* offset: 0x0292 size: 16 bit */ + SIU_PCR_tag PCR298; /* offset: 0x0294 size: 16 bit */ + SIU_PCR_tag PCR299; /* offset: 0x0296 size: 16 bit */ + SIU_PCR_tag PCR300; /* offset: 0x0298 size: 16 bit */ + SIU_PCR_tag PCR301; /* offset: 0x029A size: 16 bit */ + SIU_PCR_tag PCR302; /* offset: 0x029C size: 16 bit */ + SIU_PCR_tag PCR303; /* offset: 0x029E size: 16 bit */ + SIU_PCR_tag PCR304; /* offset: 0x02A0 size: 16 bit */ + SIU_PCR_tag PCR305; /* offset: 0x02A2 size: 16 bit */ + SIU_PCR_tag PCR306; /* offset: 0x02A4 size: 16 bit */ + SIU_PCR_tag PCR307; /* offset: 0x02A6 size: 16 bit */ + SIU_PCR_tag PCR308; /* offset: 0x02A8 size: 16 bit */ + SIU_PCR_tag PCR309; /* offset: 0x02AA size: 16 bit */ + SIU_PCR_tag PCR310; /* offset: 0x02AC size: 16 bit */ + SIU_PCR_tag PCR311; /* offset: 0x02AE size: 16 bit */ + SIU_PCR_tag PCR312; /* offset: 0x02B0 size: 16 bit */ + SIU_PCR_tag PCR313; /* offset: 0x02B2 size: 16 bit */ + SIU_PCR_tag PCR314; /* offset: 0x02B4 size: 16 bit */ + SIU_PCR_tag PCR315; /* offset: 0x02B6 size: 16 bit */ + SIU_PCR_tag PCR316; /* offset: 0x02B8 size: 16 bit */ + SIU_PCR_tag PCR317; /* offset: 0x02BA size: 16 bit */ + SIU_PCR_tag PCR318; /* offset: 0x02BC size: 16 bit */ + SIU_PCR_tag PCR319; /* offset: 0x02BE size: 16 bit */ + SIU_PCR_tag PCR320; /* offset: 0x02C0 size: 16 bit */ + SIU_PCR_tag PCR321; /* offset: 0x02C2 size: 16 bit */ + SIU_PCR_tag PCR322; /* offset: 0x02C4 size: 16 bit */ + SIU_PCR_tag PCR323; /* offset: 0x02C6 size: 16 bit */ + SIU_PCR_tag PCR324; /* offset: 0x02C8 size: 16 bit */ + SIU_PCR_tag PCR325; /* offset: 0x02CA size: 16 bit */ + SIU_PCR_tag PCR326; /* offset: 0x02CC size: 16 bit */ + SIU_PCR_tag PCR327; /* offset: 0x02CE size: 16 bit */ + SIU_PCR_tag PCR328; /* offset: 0x02D0 size: 16 bit */ + SIU_PCR_tag PCR329; /* offset: 0x02D2 size: 16 bit */ + SIU_PCR_tag PCR330; /* offset: 0x02D4 size: 16 bit */ + SIU_PCR_tag PCR331; /* offset: 0x02D6 size: 16 bit */ + SIU_PCR_tag PCR332; /* offset: 0x02D8 size: 16 bit */ + SIU_PCR_tag PCR333; /* offset: 0x02DA size: 16 bit */ + SIU_PCR_tag PCR334; /* offset: 0x02DC size: 16 bit */ + SIU_PCR_tag PCR335; /* offset: 0x02DE size: 16 bit */ + SIU_PCR_tag PCR336; /* offset: 0x02E0 size: 16 bit */ + SIU_PCR_tag PCR337; /* offset: 0x02E2 size: 16 bit */ + SIU_PCR_tag PCR338; /* offset: 0x02E4 size: 16 bit */ + SIU_PCR_tag PCR339; /* offset: 0x02E6 size: 16 bit */ + SIU_PCR_tag PCR340; /* offset: 0x02E8 size: 16 bit */ + SIU_PCR_tag PCR341; /* offset: 0x02EA size: 16 bit */ + SIU_PCR_tag PCR342; /* offset: 0x02EC size: 16 bit */ + SIU_PCR_tag PCR343; /* offset: 0x02EE size: 16 bit */ + SIU_PCR_tag PCR344; /* offset: 0x02F0 size: 16 bit */ + SIU_PCR_tag PCR345; /* offset: 0x02F2 size: 16 bit */ + SIU_PCR_tag PCR346; /* offset: 0x02F4 size: 16 bit */ + SIU_PCR_tag PCR347; /* offset: 0x02F6 size: 16 bit */ + SIU_PCR_tag PCR348; /* offset: 0x02F8 size: 16 bit */ + SIU_PCR_tag PCR349; /* offset: 0x02FA size: 16 bit */ + SIU_PCR_tag PCR350; /* offset: 0x02FC size: 16 bit */ + SIU_PCR_tag PCR351; /* offset: 0x02FE size: 16 bit */ + SIU_PCR_tag PCR352; /* offset: 0x0300 size: 16 bit */ + SIU_PCR_tag PCR353; /* offset: 0x0302 size: 16 bit */ + SIU_PCR_tag PCR354; /* offset: 0x0304 size: 16 bit */ + SIU_PCR_tag PCR355; /* offset: 0x0306 size: 16 bit */ + SIU_PCR_tag PCR356; /* offset: 0x0308 size: 16 bit */ + SIU_PCR_tag PCR357; /* offset: 0x030A size: 16 bit */ + SIU_PCR_tag PCR358; /* offset: 0x030C size: 16 bit */ + SIU_PCR_tag PCR359; /* offset: 0x030E size: 16 bit */ + SIU_PCR_tag PCR360; /* offset: 0x0310 size: 16 bit */ + SIU_PCR_tag PCR361; /* offset: 0x0312 size: 16 bit */ + SIU_PCR_tag PCR362; /* offset: 0x0314 size: 16 bit */ + SIU_PCR_tag PCR363; /* offset: 0x0316 size: 16 bit */ + SIU_PCR_tag PCR364; /* offset: 0x0318 size: 16 bit */ + SIU_PCR_tag PCR365; /* offset: 0x031A size: 16 bit */ + SIU_PCR_tag PCR366; /* offset: 0x031C size: 16 bit */ + SIU_PCR_tag PCR367; /* offset: 0x031E size: 16 bit */ + SIU_PCR_tag PCR368; /* offset: 0x0320 size: 16 bit */ + SIU_PCR_tag PCR369; /* offset: 0x0322 size: 16 bit */ + SIU_PCR_tag PCR370; /* offset: 0x0324 size: 16 bit */ + SIU_PCR_tag PCR371; /* offset: 0x0326 size: 16 bit */ + SIU_PCR_tag PCR372; /* offset: 0x0328 size: 16 bit */ + SIU_PCR_tag PCR373; /* offset: 0x032A size: 16 bit */ + SIU_PCR_tag PCR374; /* offset: 0x032C size: 16 bit */ + SIU_PCR_tag PCR375; /* offset: 0x032E size: 16 bit */ + SIU_PCR_tag PCR376; /* offset: 0x0330 size: 16 bit */ + SIU_PCR_tag PCR377; /* offset: 0x0332 size: 16 bit */ + SIU_PCR_tag PCR378; /* offset: 0x0334 size: 16 bit */ + SIU_PCR_tag PCR379; /* offset: 0x0336 size: 16 bit */ + SIU_PCR_tag PCR380; /* offset: 0x0338 size: 16 bit */ + SIU_PCR_tag PCR381; /* offset: 0x033A size: 16 bit */ + SIU_PCR_tag PCR382; /* offset: 0x033C size: 16 bit */ + SIU_PCR_tag PCR383; /* offset: 0x033E size: 16 bit */ + SIU_PCR_tag PCR384; /* offset: 0x0340 size: 16 bit */ + SIU_PCR_tag PCR385; /* offset: 0x0342 size: 16 bit */ + SIU_PCR_tag PCR386; /* offset: 0x0344 size: 16 bit */ + SIU_PCR_tag PCR387; /* offset: 0x0346 size: 16 bit */ + SIU_PCR_tag PCR388; /* offset: 0x0348 size: 16 bit */ + SIU_PCR_tag PCR389; /* offset: 0x034A size: 16 bit */ + SIU_PCR_tag PCR390; /* offset: 0x034C size: 16 bit */ + SIU_PCR_tag PCR391; /* offset: 0x034E size: 16 bit */ + SIU_PCR_tag PCR392; /* offset: 0x0350 size: 16 bit */ + SIU_PCR_tag PCR393; /* offset: 0x0352 size: 16 bit */ + SIU_PCR_tag PCR394; /* offset: 0x0354 size: 16 bit */ + SIU_PCR_tag PCR395; /* offset: 0x0356 size: 16 bit */ + SIU_PCR_tag PCR396; /* offset: 0x0358 size: 16 bit */ + SIU_PCR_tag PCR397; /* offset: 0x035A size: 16 bit */ + SIU_PCR_tag PCR398; /* offset: 0x035C size: 16 bit */ + SIU_PCR_tag PCR399; /* offset: 0x035E size: 16 bit */ + SIU_PCR_tag PCR400; /* offset: 0x0360 size: 16 bit */ + SIU_PCR_tag PCR401; /* offset: 0x0362 size: 16 bit */ + SIU_PCR_tag PCR402; /* offset: 0x0364 size: 16 bit */ + SIU_PCR_tag PCR403; /* offset: 0x0366 size: 16 bit */ + SIU_PCR_tag PCR404; /* offset: 0x0368 size: 16 bit */ + SIU_PCR_tag PCR405; /* offset: 0x036A size: 16 bit */ + SIU_PCR_tag PCR406; /* offset: 0x036C size: 16 bit */ + SIU_PCR_tag PCR407; /* offset: 0x036E size: 16 bit */ + SIU_PCR_tag PCR408; /* offset: 0x0370 size: 16 bit */ + SIU_PCR_tag PCR409; /* offset: 0x0372 size: 16 bit */ + SIU_PCR_tag PCR410; /* offset: 0x0374 size: 16 bit */ + SIU_PCR_tag PCR411; /* offset: 0x0376 size: 16 bit */ + SIU_PCR_tag PCR412; /* offset: 0x0378 size: 16 bit */ + SIU_PCR_tag PCR413; /* offset: 0x037A size: 16 bit */ + SIU_PCR_tag PCR414; /* offset: 0x037C size: 16 bit */ + SIU_PCR_tag PCR415; /* offset: 0x037E size: 16 bit */ + SIU_PCR_tag PCR416; /* offset: 0x0380 size: 16 bit */ + SIU_PCR_tag PCR417; /* offset: 0x0382 size: 16 bit */ + SIU_PCR_tag PCR418; /* offset: 0x0384 size: 16 bit */ + SIU_PCR_tag PCR419; /* offset: 0x0386 size: 16 bit */ + SIU_PCR_tag PCR420; /* offset: 0x0388 size: 16 bit */ + SIU_PCR_tag PCR421; /* offset: 0x038A size: 16 bit */ + SIU_PCR_tag PCR422; /* offset: 0x038C size: 16 bit */ + SIU_PCR_tag PCR423; /* offset: 0x038E size: 16 bit */ + SIU_PCR_tag PCR424; /* offset: 0x0390 size: 16 bit */ + SIU_PCR_tag PCR425; /* offset: 0x0392 size: 16 bit */ + SIU_PCR_tag PCR426; /* offset: 0x0394 size: 16 bit */ + SIU_PCR_tag PCR427; /* offset: 0x0396 size: 16 bit */ + SIU_PCR_tag PCR428; /* offset: 0x0398 size: 16 bit */ + SIU_PCR_tag PCR429; /* offset: 0x039A size: 16 bit */ + SIU_PCR_tag PCR430; /* offset: 0x039C size: 16 bit */ + SIU_PCR_tag PCR431; /* offset: 0x039E size: 16 bit */ + SIU_PCR_tag PCR432; /* offset: 0x03A0 size: 16 bit */ + SIU_PCR_tag PCR433; /* offset: 0x03A2 size: 16 bit */ + SIU_PCR_tag PCR434; /* offset: 0x03A4 size: 16 bit */ + SIU_PCR_tag PCR435; /* offset: 0x03A6 size: 16 bit */ + SIU_PCR_tag PCR436; /* offset: 0x03A8 size: 16 bit */ + SIU_PCR_tag PCR437; /* offset: 0x03AA size: 16 bit */ + SIU_PCR_tag PCR438; /* offset: 0x03AC size: 16 bit */ + SIU_PCR_tag PCR439; /* offset: 0x03AE size: 16 bit */ + SIU_PCR_tag PCR440; /* offset: 0x03B0 size: 16 bit */ + SIU_PCR_tag PCR441; /* offset: 0x03B2 size: 16 bit */ + SIU_PCR_tag PCR442; /* offset: 0x03B4 size: 16 bit */ + SIU_PCR_tag PCR443; /* offset: 0x03B6 size: 16 bit */ + SIU_PCR_tag PCR444; /* offset: 0x03B8 size: 16 bit */ + SIU_PCR_tag PCR445; /* offset: 0x03BA size: 16 bit */ + SIU_PCR_tag PCR446; /* offset: 0x03BC size: 16 bit */ + SIU_PCR_tag PCR447; /* offset: 0x03BE size: 16 bit */ + SIU_PCR_tag PCR448; /* offset: 0x03C0 size: 16 bit */ + SIU_PCR_tag PCR449; /* offset: 0x03C2 size: 16 bit */ + SIU_PCR_tag PCR450; /* offset: 0x03C4 size: 16 bit */ + SIU_PCR_tag PCR451; /* offset: 0x03C6 size: 16 bit */ + SIU_PCR_tag PCR452; /* offset: 0x03C8 size: 16 bit */ + SIU_PCR_tag PCR453; /* offset: 0x03CA size: 16 bit */ + SIU_PCR_tag PCR454; /* offset: 0x03CC size: 16 bit */ + SIU_PCR_tag PCR455; /* offset: 0x03CE size: 16 bit */ + SIU_PCR_tag PCR456; /* offset: 0x03D0 size: 16 bit */ + SIU_PCR_tag PCR457; /* offset: 0x03D2 size: 16 bit */ + SIU_PCR_tag PCR458; /* offset: 0x03D4 size: 16 bit */ + SIU_PCR_tag PCR459; /* offset: 0x03D6 size: 16 bit */ + SIU_PCR_tag PCR460; /* offset: 0x03D8 size: 16 bit */ + SIU_PCR_tag PCR461; /* offset: 0x03DA size: 16 bit */ + SIU_PCR_tag PCR462; /* offset: 0x03DC size: 16 bit */ + SIU_PCR_tag PCR463; /* offset: 0x03DE size: 16 bit */ + SIU_PCR_tag PCR464; /* offset: 0x03E0 size: 16 bit */ + SIU_PCR_tag PCR465; /* offset: 0x03E2 size: 16 bit */ + SIU_PCR_tag PCR466; /* offset: 0x03E4 size: 16 bit */ + SIU_PCR_tag PCR467; /* offset: 0x03E6 size: 16 bit */ + SIU_PCR_tag PCR468; /* offset: 0x03E8 size: 16 bit */ + SIU_PCR_tag PCR469; /* offset: 0x03EA size: 16 bit */ + SIU_PCR_tag PCR470; /* offset: 0x03EC size: 16 bit */ + SIU_PCR_tag PCR471; /* offset: 0x03EE size: 16 bit */ + SIU_PCR_tag PCR472; /* offset: 0x03F0 size: 16 bit */ + SIU_PCR_tag PCR473; /* offset: 0x03F2 size: 16 bit */ + SIU_PCR_tag PCR474; /* offset: 0x03F4 size: 16 bit */ + SIU_PCR_tag PCR475; /* offset: 0x03F6 size: 16 bit */ + SIU_PCR_tag PCR476; /* offset: 0x03F8 size: 16 bit */ + SIU_PCR_tag PCR477; /* offset: 0x03FA size: 16 bit */ + SIU_PCR_tag PCR478; /* offset: 0x03FC size: 16 bit */ + SIU_PCR_tag PCR479; /* offset: 0x03FE size: 16 bit */ + SIU_PCR_tag PCR480; /* offset: 0x0400 size: 16 bit */ + SIU_PCR_tag PCR481; /* offset: 0x0402 size: 16 bit */ + SIU_PCR_tag PCR482; /* offset: 0x0404 size: 16 bit */ + SIU_PCR_tag PCR483; /* offset: 0x0406 size: 16 bit */ + SIU_PCR_tag PCR484; /* offset: 0x0408 size: 16 bit */ + SIU_PCR_tag PCR485; /* offset: 0x040A size: 16 bit */ + SIU_PCR_tag PCR486; /* offset: 0x040C size: 16 bit */ + SIU_PCR_tag PCR487; /* offset: 0x040E size: 16 bit */ + SIU_PCR_tag PCR488; /* offset: 0x0410 size: 16 bit */ + SIU_PCR_tag PCR489; /* offset: 0x0412 size: 16 bit */ + SIU_PCR_tag PCR490; /* offset: 0x0414 size: 16 bit */ + SIU_PCR_tag PCR491; /* offset: 0x0416 size: 16 bit */ + SIU_PCR_tag PCR492; /* offset: 0x0418 size: 16 bit */ + SIU_PCR_tag PCR493; /* offset: 0x041A size: 16 bit */ + SIU_PCR_tag PCR494; /* offset: 0x041C size: 16 bit */ + SIU_PCR_tag PCR495; /* offset: 0x041E size: 16 bit */ + SIU_PCR_tag PCR496; /* offset: 0x0420 size: 16 bit */ + SIU_PCR_tag PCR497; /* offset: 0x0422 size: 16 bit */ + SIU_PCR_tag PCR498; /* offset: 0x0424 size: 16 bit */ + SIU_PCR_tag PCR499; /* offset: 0x0426 size: 16 bit */ + SIU_PCR_tag PCR500; /* offset: 0x0428 size: 16 bit */ + SIU_PCR_tag PCR501; /* offset: 0x042A size: 16 bit */ + SIU_PCR_tag PCR502; /* offset: 0x042C size: 16 bit */ + SIU_PCR_tag PCR503; /* offset: 0x042E size: 16 bit */ + SIU_PCR_tag PCR504; /* offset: 0x0430 size: 16 bit */ + SIU_PCR_tag PCR505; /* offset: 0x0432 size: 16 bit */ + SIU_PCR_tag PCR506; /* offset: 0x0434 size: 16 bit */ + SIU_PCR_tag PCR507; /* offset: 0x0436 size: 16 bit */ + SIU_PCR_tag PCR508; /* offset: 0x0438 size: 16 bit */ + SIU_PCR_tag PCR509; /* offset: 0x043A size: 16 bit */ + SIU_PCR_tag PCR510; /* offset: 0x043C size: 16 bit */ + SIU_PCR_tag PCR511; /* offset: 0x043E size: 16 bit */ + }; + + }; + int8_t SIUL_reserved_0440_C[192]; + union { + /* PSMI - Pad Selection for Multiplexed Inputs */ + SIUL_PSMI_32B_tag PSMI_32B[64]; /* offset: 0x0500 (0x0004 x 64) */ + + /* PSMI - Pad Selection for Multiplexed Inputs */ + SIUL_PSMI_8B_tag PSMI[256]; /* offset: 0x0500 (0x0001 x 256) */ + + struct { + /* PSMI - Pad Selection for Multiplexed Inputs */ + SIUL_PSMI_32B_tag PSMI0_3; /* offset: 0x0500 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI4_7; /* offset: 0x0504 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI8_11; /* offset: 0x0508 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI12_15; /* offset: 0x050C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI16_19; /* offset: 0x0510 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI20_23; /* offset: 0x0514 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI24_27; /* offset: 0x0518 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI28_31; /* offset: 0x051C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI32_35; /* offset: 0x0520 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI36_39; /* offset: 0x0524 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI40_43; /* offset: 0x0528 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI44_47; /* offset: 0x052C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI48_51; /* offset: 0x0530 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI52_55; /* offset: 0x0534 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI56_59; /* offset: 0x0538 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI60_63; /* offset: 0x053C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI64_67; /* offset: 0x0540 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI68_71; /* offset: 0x0544 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI72_75; /* offset: 0x0548 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI76_79; /* offset: 0x054C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI80_83; /* offset: 0x0550 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI84_87; /* offset: 0x0554 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI88_91; /* offset: 0x0558 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI92_95; /* offset: 0x055C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI96_99; /* offset: 0x0560 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI100_103; /* offset: 0x0564 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI104_107; /* offset: 0x0568 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI108_111; /* offset: 0x056C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI112_115; /* offset: 0x0570 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI116_119; /* offset: 0x0574 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI120_123; /* offset: 0x0578 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI124_127; /* offset: 0x057C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI128_131; /* offset: 0x0580 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI132_135; /* offset: 0x0584 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI136_139; /* offset: 0x0588 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI140_143; /* offset: 0x058C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI144_147; /* offset: 0x0590 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI148_151; /* offset: 0x0594 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI152_155; /* offset: 0x0598 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI156_159; /* offset: 0x059C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI160_163; /* offset: 0x05A0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI164_167; /* offset: 0x05A4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI168_171; /* offset: 0x05A8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI172_175; /* offset: 0x05AC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI176_179; /* offset: 0x05B0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI180_183; /* offset: 0x05B4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI184_187; /* offset: 0x05B8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI188_191; /* offset: 0x05BC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI192_195; /* offset: 0x05C0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI196_199; /* offset: 0x05C4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI200_203; /* offset: 0x05C8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI204_207; /* offset: 0x05CC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI208_211; /* offset: 0x05D0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI212_215; /* offset: 0x05D4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI216_219; /* offset: 0x05D8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI220_223; /* offset: 0x05DC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI224_227; /* offset: 0x05E0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI228_231; /* offset: 0x05E4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI232_235; /* offset: 0x05E8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI236_239; /* offset: 0x05EC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI240_243; /* offset: 0x05F0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI244_247; /* offset: 0x05F4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI248_251; /* offset: 0x05F8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI252_255; /* offset: 0x05FC size: 32 bit */ + }; + + struct { + /* PSMI - Pad Selection for Multiplexed Inputs */ + SIUL_PSMI_8B_tag PSMI0; /* offset: 0x0500 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI1; /* offset: 0x0501 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI2; /* offset: 0x0502 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI3; /* offset: 0x0503 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI4; /* offset: 0x0504 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI5; /* offset: 0x0505 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI6; /* offset: 0x0506 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI7; /* offset: 0x0507 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI8; /* offset: 0x0508 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI9; /* offset: 0x0509 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI10; /* offset: 0x050A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI11; /* offset: 0x050B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI12; /* offset: 0x050C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI13; /* offset: 0x050D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI14; /* offset: 0x050E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI15; /* offset: 0x050F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI16; /* offset: 0x0510 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI17; /* offset: 0x0511 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI18; /* offset: 0x0512 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI19; /* offset: 0x0513 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI20; /* offset: 0x0514 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI21; /* offset: 0x0515 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI22; /* offset: 0x0516 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI23; /* offset: 0x0517 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI24; /* offset: 0x0518 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI25; /* offset: 0x0519 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI26; /* offset: 0x051A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI27; /* offset: 0x051B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI28; /* offset: 0x051C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI29; /* offset: 0x051D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI30; /* offset: 0x051E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI31; /* offset: 0x051F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI32; /* offset: 0x0520 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI33; /* offset: 0x0521 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI34; /* offset: 0x0522 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI35; /* offset: 0x0523 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI36; /* offset: 0x0524 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI37; /* offset: 0x0525 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI38; /* offset: 0x0526 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI39; /* offset: 0x0527 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI40; /* offset: 0x0528 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI41; /* offset: 0x0529 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI42; /* offset: 0x052A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI43; /* offset: 0x052B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI44; /* offset: 0x052C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI45; /* offset: 0x052D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI46; /* offset: 0x052E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI47; /* offset: 0x052F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI48; /* offset: 0x0530 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI49; /* offset: 0x0531 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI50; /* offset: 0x0532 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI51; /* offset: 0x0533 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI52; /* offset: 0x0534 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI53; /* offset: 0x0535 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI54; /* offset: 0x0536 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI55; /* offset: 0x0537 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI56; /* offset: 0x0538 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI57; /* offset: 0x0539 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI58; /* offset: 0x053A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI59; /* offset: 0x053B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI60; /* offset: 0x053C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI61; /* offset: 0x053D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI62; /* offset: 0x053E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI63; /* offset: 0x053F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI64; /* offset: 0x0540 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI65; /* offset: 0x0541 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI66; /* offset: 0x0542 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI67; /* offset: 0x0543 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI68; /* offset: 0x0544 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI69; /* offset: 0x0545 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI70; /* offset: 0x0546 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI71; /* offset: 0x0547 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI72; /* offset: 0x0548 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI73; /* offset: 0x0549 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI74; /* offset: 0x054A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI75; /* offset: 0x054B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI76; /* offset: 0x054C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI77; /* offset: 0x054D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI78; /* offset: 0x054E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI79; /* offset: 0x054F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI80; /* offset: 0x0550 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI81; /* offset: 0x0551 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI82; /* offset: 0x0552 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI83; /* offset: 0x0553 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI84; /* offset: 0x0554 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI85; /* offset: 0x0555 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI86; /* offset: 0x0556 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI87; /* offset: 0x0557 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI88; /* offset: 0x0558 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI89; /* offset: 0x0559 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI90; /* offset: 0x055A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI91; /* offset: 0x055B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI92; /* offset: 0x055C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI93; /* offset: 0x055D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI94; /* offset: 0x055E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI95; /* offset: 0x055F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI96; /* offset: 0x0560 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI97; /* offset: 0x0561 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI98; /* offset: 0x0562 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI99; /* offset: 0x0563 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI100; /* offset: 0x0564 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI101; /* offset: 0x0565 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI102; /* offset: 0x0566 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI103; /* offset: 0x0567 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI104; /* offset: 0x0568 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI105; /* offset: 0x0569 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI106; /* offset: 0x056A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI107; /* offset: 0x056B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI108; /* offset: 0x056C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI109; /* offset: 0x056D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI110; /* offset: 0x056E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI111; /* offset: 0x056F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI112; /* offset: 0x0570 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI113; /* offset: 0x0571 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI114; /* offset: 0x0572 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI115; /* offset: 0x0573 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI116; /* offset: 0x0574 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI117; /* offset: 0x0575 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI118; /* offset: 0x0576 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI119; /* offset: 0x0577 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI120; /* offset: 0x0578 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI121; /* offset: 0x0579 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI122; /* offset: 0x057A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI123; /* offset: 0x057B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI124; /* offset: 0x057C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI125; /* offset: 0x057D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI126; /* offset: 0x057E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI127; /* offset: 0x057F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI128; /* offset: 0x0580 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI129; /* offset: 0x0581 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI130; /* offset: 0x0582 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI131; /* offset: 0x0583 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI132; /* offset: 0x0584 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI133; /* offset: 0x0585 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI134; /* offset: 0x0586 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI135; /* offset: 0x0587 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI136; /* offset: 0x0588 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI137; /* offset: 0x0589 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI138; /* offset: 0x058A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI139; /* offset: 0x058B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI140; /* offset: 0x058C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI141; /* offset: 0x058D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI142; /* offset: 0x058E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI143; /* offset: 0x058F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI144; /* offset: 0x0590 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI145; /* offset: 0x0591 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI146; /* offset: 0x0592 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI147; /* offset: 0x0593 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI148; /* offset: 0x0594 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI149; /* offset: 0x0595 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI150; /* offset: 0x0596 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI151; /* offset: 0x0597 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI152; /* offset: 0x0598 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI153; /* offset: 0x0599 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI154; /* offset: 0x059A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI155; /* offset: 0x059B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI156; /* offset: 0x059C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI157; /* offset: 0x059D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI158; /* offset: 0x059E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI159; /* offset: 0x059F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI160; /* offset: 0x05A0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI161; /* offset: 0x05A1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI162; /* offset: 0x05A2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI163; /* offset: 0x05A3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI164; /* offset: 0x05A4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI165; /* offset: 0x05A5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI166; /* offset: 0x05A6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI167; /* offset: 0x05A7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI168; /* offset: 0x05A8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI169; /* offset: 0x05A9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI170; /* offset: 0x05AA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI171; /* offset: 0x05AB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI172; /* offset: 0x05AC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI173; /* offset: 0x05AD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI174; /* offset: 0x05AE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI175; /* offset: 0x05AF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI176; /* offset: 0x05B0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI177; /* offset: 0x05B1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI178; /* offset: 0x05B2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI179; /* offset: 0x05B3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI180; /* offset: 0x05B4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI181; /* offset: 0x05B5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI182; /* offset: 0x05B6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI183; /* offset: 0x05B7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI184; /* offset: 0x05B8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI185; /* offset: 0x05B9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI186; /* offset: 0x05BA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI187; /* offset: 0x05BB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI188; /* offset: 0x05BC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI189; /* offset: 0x05BD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI190; /* offset: 0x05BE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI191; /* offset: 0x05BF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI192; /* offset: 0x05C0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI193; /* offset: 0x05C1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI194; /* offset: 0x05C2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI195; /* offset: 0x05C3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI196; /* offset: 0x05C4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI197; /* offset: 0x05C5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI198; /* offset: 0x05C6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI199; /* offset: 0x05C7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI200; /* offset: 0x05C8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI201; /* offset: 0x05C9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI202; /* offset: 0x05CA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI203; /* offset: 0x05CB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI204; /* offset: 0x05CC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI205; /* offset: 0x05CD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI206; /* offset: 0x05CE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI207; /* offset: 0x05CF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI208; /* offset: 0x05D0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI209; /* offset: 0x05D1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI210; /* offset: 0x05D2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI211; /* offset: 0x05D3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI212; /* offset: 0x05D4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI213; /* offset: 0x05D5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI214; /* offset: 0x05D6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI215; /* offset: 0x05D7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI216; /* offset: 0x05D8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI217; /* offset: 0x05D9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI218; /* offset: 0x05DA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI219; /* offset: 0x05DB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI220; /* offset: 0x05DC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI221; /* offset: 0x05DD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI222; /* offset: 0x05DE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI223; /* offset: 0x05DF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI224; /* offset: 0x05E0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI225; /* offset: 0x05E1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI226; /* offset: 0x05E2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI227; /* offset: 0x05E3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI228; /* offset: 0x05E4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI229; /* offset: 0x05E5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI230; /* offset: 0x05E6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI231; /* offset: 0x05E7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI232; /* offset: 0x05E8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI233; /* offset: 0x05E9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI234; /* offset: 0x05EA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI235; /* offset: 0x05EB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI236; /* offset: 0x05EC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI237; /* offset: 0x05ED size: 8 bit */ + SIUL_PSMI_8B_tag PSMI238; /* offset: 0x05EE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI239; /* offset: 0x05EF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI240; /* offset: 0x05F0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI241; /* offset: 0x05F1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI242; /* offset: 0x05F2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI243; /* offset: 0x05F3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI244; /* offset: 0x05F4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI245; /* offset: 0x05F5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI246; /* offset: 0x05F6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI247; /* offset: 0x05F7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI248; /* offset: 0x05F8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI249; /* offset: 0x05F9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI250; /* offset: 0x05FA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI251; /* offset: 0x05FB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI252; /* offset: 0x05FC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI253; /* offset: 0x05FD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI254; /* offset: 0x05FE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI255; /* offset: 0x05FF size: 8 bit */ + }; + + }; + union { + /* GPDO - GPIO Pad Data Output Register */ + SIUL_GPDO_32B_tag GPDO_32B[128]; /* offset: 0x0600 (0x0004 x 128) */ + + /* GPDO - GPIO Pad Data Output Register */ + SIUL_GPDO_8B_tag GPDO[512]; /* offset: 0x0600 (0x0001 x 512) */ + + struct { + /* GPDO - GPIO Pad Data Output Register */ + SIUL_GPDO_32B_tag GPDO0_3; /* offset: 0x0600 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO4_7; /* offset: 0x0604 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO8_11; /* offset: 0x0608 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO12_15; /* offset: 0x060C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO16_19; /* offset: 0x0610 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO20_23; /* offset: 0x0614 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO24_27; /* offset: 0x0618 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO28_31; /* offset: 0x061C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO32_35; /* offset: 0x0620 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO36_39; /* offset: 0x0624 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO40_43; /* offset: 0x0628 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO44_47; /* offset: 0x062C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO48_51; /* offset: 0x0630 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO52_55; /* offset: 0x0634 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO56_59; /* offset: 0x0638 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO60_63; /* offset: 0x063C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO64_67; /* offset: 0x0640 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO68_71; /* offset: 0x0644 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO72_75; /* offset: 0x0648 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO76_79; /* offset: 0x064C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO80_83; /* offset: 0x0650 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO84_87; /* offset: 0x0654 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO88_91; /* offset: 0x0658 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO92_95; /* offset: 0x065C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO96_99; /* offset: 0x0660 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO100_103; /* offset: 0x0664 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO104_107; /* offset: 0x0668 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO108_111; /* offset: 0x066C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO112_115; /* offset: 0x0670 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO116_119; /* offset: 0x0674 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO120_123; /* offset: 0x0678 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO124_127; /* offset: 0x067C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO128_131; /* offset: 0x0680 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO132_135; /* offset: 0x0684 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO136_139; /* offset: 0x0688 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO140_143; /* offset: 0x068C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO144_147; /* offset: 0x0690 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO148_151; /* offset: 0x0694 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO152_155; /* offset: 0x0698 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO156_159; /* offset: 0x069C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO160_163; /* offset: 0x06A0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO164_167; /* offset: 0x06A4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO168_171; /* offset: 0x06A8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO172_175; /* offset: 0x06AC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO176_179; /* offset: 0x06B0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO180_183; /* offset: 0x06B4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO184_187; /* offset: 0x06B8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO188_191; /* offset: 0x06BC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO192_195; /* offset: 0x06C0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO196_199; /* offset: 0x06C4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO200_203; /* offset: 0x06C8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO204_207; /* offset: 0x06CC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO208_211; /* offset: 0x06D0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO212_215; /* offset: 0x06D4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO216_219; /* offset: 0x06D8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO220_223; /* offset: 0x06DC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO224_227; /* offset: 0x06E0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO228_231; /* offset: 0x06E4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO232_235; /* offset: 0x06E8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO236_239; /* offset: 0x06EC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO240_243; /* offset: 0x06F0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO244_247; /* offset: 0x06F4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO248_251; /* offset: 0x06F8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO252_255; /* offset: 0x06FC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO256_259; /* offset: 0x0700 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO260_263; /* offset: 0x0704 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO264_267; /* offset: 0x0708 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO268_271; /* offset: 0x070C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO272_275; /* offset: 0x0710 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO276_279; /* offset: 0x0714 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO280_283; /* offset: 0x0718 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO284_287; /* offset: 0x071C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO288_291; /* offset: 0x0720 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO292_295; /* offset: 0x0724 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO296_299; /* offset: 0x0728 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO300_303; /* offset: 0x072C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO304_307; /* offset: 0x0730 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO308_311; /* offset: 0x0734 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO312_315; /* offset: 0x0738 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO316_319; /* offset: 0x073C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO320_323; /* offset: 0x0740 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO324_327; /* offset: 0x0744 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO328_331; /* offset: 0x0748 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO332_335; /* offset: 0x074C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO336_339; /* offset: 0x0750 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO340_343; /* offset: 0x0754 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO344_347; /* offset: 0x0758 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO348_351; /* offset: 0x075C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO352_355; /* offset: 0x0760 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO356_359; /* offset: 0x0764 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO360_363; /* offset: 0x0768 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO364_367; /* offset: 0x076C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO368_371; /* offset: 0x0770 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO372_375; /* offset: 0x0774 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO376_379; /* offset: 0x0778 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO380_383; /* offset: 0x077C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO384_387; /* offset: 0x0780 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO388_391; /* offset: 0x0784 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO392_395; /* offset: 0x0788 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO396_399; /* offset: 0x078C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO400_403; /* offset: 0x0790 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO404_407; /* offset: 0x0794 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO408_411; /* offset: 0x0798 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO412_415; /* offset: 0x079C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO416_419; /* offset: 0x07A0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO420_423; /* offset: 0x07A4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO424_427; /* offset: 0x07A8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO428_431; /* offset: 0x07AC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO432_435; /* offset: 0x07B0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO436_439; /* offset: 0x07B4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO440_443; /* offset: 0x07B8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO444_447; /* offset: 0x07BC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO448_451; /* offset: 0x07C0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO452_455; /* offset: 0x07C4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO456_459; /* offset: 0x07C8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO460_463; /* offset: 0x07CC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO464_467; /* offset: 0x07D0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO468_471; /* offset: 0x07D4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO472_475; /* offset: 0x07D8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO476_479; /* offset: 0x07DC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO480_483; /* offset: 0x07E0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO484_487; /* offset: 0x07E4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO488_491; /* offset: 0x07E8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO492_495; /* offset: 0x07EC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO496_499; /* offset: 0x07F0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO500_503; /* offset: 0x07F4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO504_507; /* offset: 0x07F8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO508_511; /* offset: 0x07FC size: 32 bit */ + }; + + struct { + /* GPDO - GPIO Pad Data Output Register */ + SIUL_GPDO_8B_tag GPDO0; /* offset: 0x0600 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO1; /* offset: 0x0601 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO2; /* offset: 0x0602 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO3; /* offset: 0x0603 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO4; /* offset: 0x0604 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO5; /* offset: 0x0605 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO6; /* offset: 0x0606 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO7; /* offset: 0x0607 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO8; /* offset: 0x0608 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO9; /* offset: 0x0609 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO10; /* offset: 0x060A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO11; /* offset: 0x060B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO12; /* offset: 0x060C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO13; /* offset: 0x060D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO14; /* offset: 0x060E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO15; /* offset: 0x060F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO16; /* offset: 0x0610 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO17; /* offset: 0x0611 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO18; /* offset: 0x0612 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO19; /* offset: 0x0613 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO20; /* offset: 0x0614 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO21; /* offset: 0x0615 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO22; /* offset: 0x0616 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO23; /* offset: 0x0617 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO24; /* offset: 0x0618 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO25; /* offset: 0x0619 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO26; /* offset: 0x061A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO27; /* offset: 0x061B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO28; /* offset: 0x061C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO29; /* offset: 0x061D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO30; /* offset: 0x061E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO31; /* offset: 0x061F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO32; /* offset: 0x0620 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO33; /* offset: 0x0621 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO34; /* offset: 0x0622 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO35; /* offset: 0x0623 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO36; /* offset: 0x0624 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO37; /* offset: 0x0625 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO38; /* offset: 0x0626 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO39; /* offset: 0x0627 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO40; /* offset: 0x0628 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO41; /* offset: 0x0629 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO42; /* offset: 0x062A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO43; /* offset: 0x062B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO44; /* offset: 0x062C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO45; /* offset: 0x062D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO46; /* offset: 0x062E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO47; /* offset: 0x062F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO48; /* offset: 0x0630 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO49; /* offset: 0x0631 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO50; /* offset: 0x0632 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO51; /* offset: 0x0633 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO52; /* offset: 0x0634 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO53; /* offset: 0x0635 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO54; /* offset: 0x0636 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO55; /* offset: 0x0637 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO56; /* offset: 0x0638 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO57; /* offset: 0x0639 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO58; /* offset: 0x063A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO59; /* offset: 0x063B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO60; /* offset: 0x063C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO61; /* offset: 0x063D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO62; /* offset: 0x063E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO63; /* offset: 0x063F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO64; /* offset: 0x0640 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO65; /* offset: 0x0641 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO66; /* offset: 0x0642 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO67; /* offset: 0x0643 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO68; /* offset: 0x0644 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO69; /* offset: 0x0645 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO70; /* offset: 0x0646 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO71; /* offset: 0x0647 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO72; /* offset: 0x0648 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO73; /* offset: 0x0649 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO74; /* offset: 0x064A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO75; /* offset: 0x064B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO76; /* offset: 0x064C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO77; /* offset: 0x064D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO78; /* offset: 0x064E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO79; /* offset: 0x064F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO80; /* offset: 0x0650 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO81; /* offset: 0x0651 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO82; /* offset: 0x0652 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO83; /* offset: 0x0653 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO84; /* offset: 0x0654 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO85; /* offset: 0x0655 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO86; /* offset: 0x0656 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO87; /* offset: 0x0657 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO88; /* offset: 0x0658 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO89; /* offset: 0x0659 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO90; /* offset: 0x065A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO91; /* offset: 0x065B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO92; /* offset: 0x065C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO93; /* offset: 0x065D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO94; /* offset: 0x065E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO95; /* offset: 0x065F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO96; /* offset: 0x0660 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO97; /* offset: 0x0661 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO98; /* offset: 0x0662 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO99; /* offset: 0x0663 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO100; /* offset: 0x0664 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO101; /* offset: 0x0665 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO102; /* offset: 0x0666 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO103; /* offset: 0x0667 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO104; /* offset: 0x0668 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO105; /* offset: 0x0669 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO106; /* offset: 0x066A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO107; /* offset: 0x066B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO108; /* offset: 0x066C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO109; /* offset: 0x066D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO110; /* offset: 0x066E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO111; /* offset: 0x066F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO112; /* offset: 0x0670 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO113; /* offset: 0x0671 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO114; /* offset: 0x0672 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO115; /* offset: 0x0673 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO116; /* offset: 0x0674 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO117; /* offset: 0x0675 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO118; /* offset: 0x0676 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO119; /* offset: 0x0677 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO120; /* offset: 0x0678 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO121; /* offset: 0x0679 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO122; /* offset: 0x067A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO123; /* offset: 0x067B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO124; /* offset: 0x067C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO125; /* offset: 0x067D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO126; /* offset: 0x067E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO127; /* offset: 0x067F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO128; /* offset: 0x0680 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO129; /* offset: 0x0681 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO130; /* offset: 0x0682 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO131; /* offset: 0x0683 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO132; /* offset: 0x0684 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO133; /* offset: 0x0685 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO134; /* offset: 0x0686 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO135; /* offset: 0x0687 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO136; /* offset: 0x0688 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO137; /* offset: 0x0689 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO138; /* offset: 0x068A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO139; /* offset: 0x068B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO140; /* offset: 0x068C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO141; /* offset: 0x068D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO142; /* offset: 0x068E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO143; /* offset: 0x068F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO144; /* offset: 0x0690 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO145; /* offset: 0x0691 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO146; /* offset: 0x0692 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO147; /* offset: 0x0693 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO148; /* offset: 0x0694 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO149; /* offset: 0x0695 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO150; /* offset: 0x0696 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO151; /* offset: 0x0697 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO152; /* offset: 0x0698 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO153; /* offset: 0x0699 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO154; /* offset: 0x069A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO155; /* offset: 0x069B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO156; /* offset: 0x069C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO157; /* offset: 0x069D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO158; /* offset: 0x069E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO159; /* offset: 0x069F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO160; /* offset: 0x06A0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO161; /* offset: 0x06A1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO162; /* offset: 0x06A2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO163; /* offset: 0x06A3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO164; /* offset: 0x06A4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO165; /* offset: 0x06A5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO166; /* offset: 0x06A6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO167; /* offset: 0x06A7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO168; /* offset: 0x06A8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO169; /* offset: 0x06A9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO170; /* offset: 0x06AA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO171; /* offset: 0x06AB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO172; /* offset: 0x06AC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO173; /* offset: 0x06AD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO174; /* offset: 0x06AE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO175; /* offset: 0x06AF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO176; /* offset: 0x06B0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO177; /* offset: 0x06B1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO178; /* offset: 0x06B2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO179; /* offset: 0x06B3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO180; /* offset: 0x06B4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO181; /* offset: 0x06B5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO182; /* offset: 0x06B6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO183; /* offset: 0x06B7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO184; /* offset: 0x06B8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO185; /* offset: 0x06B9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO186; /* offset: 0x06BA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO187; /* offset: 0x06BB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO188; /* offset: 0x06BC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO189; /* offset: 0x06BD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO190; /* offset: 0x06BE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO191; /* offset: 0x06BF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO192; /* offset: 0x06C0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO193; /* offset: 0x06C1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO194; /* offset: 0x06C2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO195; /* offset: 0x06C3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO196; /* offset: 0x06C4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO197; /* offset: 0x06C5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO198; /* offset: 0x06C6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO199; /* offset: 0x06C7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO200; /* offset: 0x06C8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO201; /* offset: 0x06C9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO202; /* offset: 0x06CA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO203; /* offset: 0x06CB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO204; /* offset: 0x06CC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO205; /* offset: 0x06CD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO206; /* offset: 0x06CE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO207; /* offset: 0x06CF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO208; /* offset: 0x06D0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO209; /* offset: 0x06D1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO210; /* offset: 0x06D2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO211; /* offset: 0x06D3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO212; /* offset: 0x06D4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO213; /* offset: 0x06D5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO214; /* offset: 0x06D6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO215; /* offset: 0x06D7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO216; /* offset: 0x06D8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO217; /* offset: 0x06D9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO218; /* offset: 0x06DA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO219; /* offset: 0x06DB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO220; /* offset: 0x06DC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO221; /* offset: 0x06DD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO222; /* offset: 0x06DE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO223; /* offset: 0x06DF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO224; /* offset: 0x06E0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO225; /* offset: 0x06E1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO226; /* offset: 0x06E2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO227; /* offset: 0x06E3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO228; /* offset: 0x06E4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO229; /* offset: 0x06E5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO230; /* offset: 0x06E6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO231; /* offset: 0x06E7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO232; /* offset: 0x06E8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO233; /* offset: 0x06E9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO234; /* offset: 0x06EA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO235; /* offset: 0x06EB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO236; /* offset: 0x06EC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO237; /* offset: 0x06ED size: 8 bit */ + SIUL_GPDO_8B_tag GPDO238; /* offset: 0x06EE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO239; /* offset: 0x06EF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO240; /* offset: 0x06F0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO241; /* offset: 0x06F1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO242; /* offset: 0x06F2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO243; /* offset: 0x06F3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO244; /* offset: 0x06F4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO245; /* offset: 0x06F5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO246; /* offset: 0x06F6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO247; /* offset: 0x06F7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO248; /* offset: 0x06F8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO249; /* offset: 0x06F9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO250; /* offset: 0x06FA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO251; /* offset: 0x06FB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO252; /* offset: 0x06FC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO253; /* offset: 0x06FD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO254; /* offset: 0x06FE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO255; /* offset: 0x06FF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO256; /* offset: 0x0700 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO257; /* offset: 0x0701 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO258; /* offset: 0x0702 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO259; /* offset: 0x0703 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO260; /* offset: 0x0704 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO261; /* offset: 0x0705 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO262; /* offset: 0x0706 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO263; /* offset: 0x0707 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO264; /* offset: 0x0708 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO265; /* offset: 0x0709 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO266; /* offset: 0x070A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO267; /* offset: 0x070B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO268; /* offset: 0x070C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO269; /* offset: 0x070D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO270; /* offset: 0x070E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO271; /* offset: 0x070F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO272; /* offset: 0x0710 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO273; /* offset: 0x0711 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO274; /* offset: 0x0712 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO275; /* offset: 0x0713 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO276; /* offset: 0x0714 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO277; /* offset: 0x0715 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO278; /* offset: 0x0716 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO279; /* offset: 0x0717 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO280; /* offset: 0x0718 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO281; /* offset: 0x0719 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO282; /* offset: 0x071A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO283; /* offset: 0x071B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO284; /* offset: 0x071C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO285; /* offset: 0x071D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO286; /* offset: 0x071E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO287; /* offset: 0x071F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO288; /* offset: 0x0720 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO289; /* offset: 0x0721 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO290; /* offset: 0x0722 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO291; /* offset: 0x0723 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO292; /* offset: 0x0724 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO293; /* offset: 0x0725 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO294; /* offset: 0x0726 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO295; /* offset: 0x0727 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO296; /* offset: 0x0728 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO297; /* offset: 0x0729 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO298; /* offset: 0x072A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO299; /* offset: 0x072B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO300; /* offset: 0x072C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO301; /* offset: 0x072D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO302; /* offset: 0x072E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO303; /* offset: 0x072F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO304; /* offset: 0x0730 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO305; /* offset: 0x0731 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO306; /* offset: 0x0732 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO307; /* offset: 0x0733 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO308; /* offset: 0x0734 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO309; /* offset: 0x0735 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO310; /* offset: 0x0736 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO311; /* offset: 0x0737 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO312; /* offset: 0x0738 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO313; /* offset: 0x0739 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO314; /* offset: 0x073A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO315; /* offset: 0x073B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO316; /* offset: 0x073C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO317; /* offset: 0x073D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO318; /* offset: 0x073E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO319; /* offset: 0x073F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO320; /* offset: 0x0740 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO321; /* offset: 0x0741 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO322; /* offset: 0x0742 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO323; /* offset: 0x0743 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO324; /* offset: 0x0744 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO325; /* offset: 0x0745 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO326; /* offset: 0x0746 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO327; /* offset: 0x0747 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO328; /* offset: 0x0748 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO329; /* offset: 0x0749 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO330; /* offset: 0x074A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO331; /* offset: 0x074B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO332; /* offset: 0x074C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO333; /* offset: 0x074D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO334; /* offset: 0x074E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO335; /* offset: 0x074F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO336; /* offset: 0x0750 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO337; /* offset: 0x0751 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO338; /* offset: 0x0752 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO339; /* offset: 0x0753 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO340; /* offset: 0x0754 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO341; /* offset: 0x0755 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO342; /* offset: 0x0756 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO343; /* offset: 0x0757 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO344; /* offset: 0x0758 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO345; /* offset: 0x0759 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO346; /* offset: 0x075A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO347; /* offset: 0x075B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO348; /* offset: 0x075C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO349; /* offset: 0x075D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO350; /* offset: 0x075E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO351; /* offset: 0x075F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO352; /* offset: 0x0760 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO353; /* offset: 0x0761 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO354; /* offset: 0x0762 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO355; /* offset: 0x0763 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO356; /* offset: 0x0764 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO357; /* offset: 0x0765 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO358; /* offset: 0x0766 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO359; /* offset: 0x0767 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO360; /* offset: 0x0768 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO361; /* offset: 0x0769 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO362; /* offset: 0x076A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO363; /* offset: 0x076B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO364; /* offset: 0x076C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO365; /* offset: 0x076D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO366; /* offset: 0x076E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO367; /* offset: 0x076F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO368; /* offset: 0x0770 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO369; /* offset: 0x0771 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO370; /* offset: 0x0772 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO371; /* offset: 0x0773 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO372; /* offset: 0x0774 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO373; /* offset: 0x0775 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO374; /* offset: 0x0776 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO375; /* offset: 0x0777 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO376; /* offset: 0x0778 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO377; /* offset: 0x0779 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO378; /* offset: 0x077A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO379; /* offset: 0x077B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO380; /* offset: 0x077C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO381; /* offset: 0x077D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO382; /* offset: 0x077E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO383; /* offset: 0x077F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO384; /* offset: 0x0780 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO385; /* offset: 0x0781 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO386; /* offset: 0x0782 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO387; /* offset: 0x0783 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO388; /* offset: 0x0784 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO389; /* offset: 0x0785 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO390; /* offset: 0x0786 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO391; /* offset: 0x0787 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO392; /* offset: 0x0788 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO393; /* offset: 0x0789 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO394; /* offset: 0x078A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO395; /* offset: 0x078B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO396; /* offset: 0x078C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO397; /* offset: 0x078D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO398; /* offset: 0x078E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO399; /* offset: 0x078F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO400; /* offset: 0x0790 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO401; /* offset: 0x0791 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO402; /* offset: 0x0792 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO403; /* offset: 0x0793 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO404; /* offset: 0x0794 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO405; /* offset: 0x0795 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO406; /* offset: 0x0796 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO407; /* offset: 0x0797 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO408; /* offset: 0x0798 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO409; /* offset: 0x0799 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO410; /* offset: 0x079A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO411; /* offset: 0x079B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO412; /* offset: 0x079C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO413; /* offset: 0x079D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO414; /* offset: 0x079E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO415; /* offset: 0x079F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO416; /* offset: 0x07A0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO417; /* offset: 0x07A1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO418; /* offset: 0x07A2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO419; /* offset: 0x07A3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO420; /* offset: 0x07A4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO421; /* offset: 0x07A5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO422; /* offset: 0x07A6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO423; /* offset: 0x07A7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO424; /* offset: 0x07A8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO425; /* offset: 0x07A9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO426; /* offset: 0x07AA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO427; /* offset: 0x07AB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO428; /* offset: 0x07AC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO429; /* offset: 0x07AD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO430; /* offset: 0x07AE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO431; /* offset: 0x07AF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO432; /* offset: 0x07B0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO433; /* offset: 0x07B1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO434; /* offset: 0x07B2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO435; /* offset: 0x07B3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO436; /* offset: 0x07B4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO437; /* offset: 0x07B5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO438; /* offset: 0x07B6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO439; /* offset: 0x07B7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO440; /* offset: 0x07B8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO441; /* offset: 0x07B9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO442; /* offset: 0x07BA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO443; /* offset: 0x07BB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO444; /* offset: 0x07BC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO445; /* offset: 0x07BD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO446; /* offset: 0x07BE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO447; /* offset: 0x07BF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO448; /* offset: 0x07C0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO449; /* offset: 0x07C1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO450; /* offset: 0x07C2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO451; /* offset: 0x07C3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO452; /* offset: 0x07C4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO453; /* offset: 0x07C5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO454; /* offset: 0x07C6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO455; /* offset: 0x07C7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO456; /* offset: 0x07C8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO457; /* offset: 0x07C9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO458; /* offset: 0x07CA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO459; /* offset: 0x07CB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO460; /* offset: 0x07CC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO461; /* offset: 0x07CD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO462; /* offset: 0x07CE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO463; /* offset: 0x07CF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO464; /* offset: 0x07D0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO465; /* offset: 0x07D1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO466; /* offset: 0x07D2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO467; /* offset: 0x07D3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO468; /* offset: 0x07D4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO469; /* offset: 0x07D5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO470; /* offset: 0x07D6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO471; /* offset: 0x07D7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO472; /* offset: 0x07D8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO473; /* offset: 0x07D9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO474; /* offset: 0x07DA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO475; /* offset: 0x07DB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO476; /* offset: 0x07DC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO477; /* offset: 0x07DD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO478; /* offset: 0x07DE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO479; /* offset: 0x07DF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO480; /* offset: 0x07E0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO481; /* offset: 0x07E1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO482; /* offset: 0x07E2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO483; /* offset: 0x07E3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO484; /* offset: 0x07E4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO485; /* offset: 0x07E5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO486; /* offset: 0x07E6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO487; /* offset: 0x07E7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO488; /* offset: 0x07E8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO489; /* offset: 0x07E9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO490; /* offset: 0x07EA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO491; /* offset: 0x07EB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO492; /* offset: 0x07EC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO493; /* offset: 0x07ED size: 8 bit */ + SIUL_GPDO_8B_tag GPDO494; /* offset: 0x07EE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO495; /* offset: 0x07EF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO496; /* offset: 0x07F0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO497; /* offset: 0x07F1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO498; /* offset: 0x07F2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO499; /* offset: 0x07F3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO500; /* offset: 0x07F4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO501; /* offset: 0x07F5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO502; /* offset: 0x07F6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO503; /* offset: 0x07F7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO504; /* offset: 0x07F8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO505; /* offset: 0x07F9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO506; /* offset: 0x07FA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO507; /* offset: 0x07FB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO508; /* offset: 0x07FC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO509; /* offset: 0x07FD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO510; /* offset: 0x07FE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO511; /* offset: 0x07FF size: 8 bit */ + }; + + }; + union { + /* GPDI - GPIO Pad Data Input Register */ + SIUL_GPDI_32B_tag GPDI_32B[128]; /* offset: 0x0800 (0x0004 x 128) */ + + /* GPDI - GPIO Pad Data Input Register */ + SIUL_GPDI_8B_tag GPDI[512]; /* offset: 0x0800 (0x0001 x 512) */ + + struct { + /* GPDI - GPIO Pad Data Input Register */ + SIUL_GPDI_32B_tag GPDI0_3; /* offset: 0x0800 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI4_7; /* offset: 0x0804 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI8_11; /* offset: 0x0808 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI12_15; /* offset: 0x080C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI16_19; /* offset: 0x0810 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI20_23; /* offset: 0x0814 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI24_27; /* offset: 0x0818 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI28_31; /* offset: 0x081C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI32_35; /* offset: 0x0820 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI36_39; /* offset: 0x0824 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI40_43; /* offset: 0x0828 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI44_47; /* offset: 0x082C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI48_51; /* offset: 0x0830 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI52_55; /* offset: 0x0834 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI56_59; /* offset: 0x0838 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI60_63; /* offset: 0x083C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI64_67; /* offset: 0x0840 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI68_71; /* offset: 0x0844 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI72_75; /* offset: 0x0848 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI76_79; /* offset: 0x084C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI80_83; /* offset: 0x0850 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI84_87; /* offset: 0x0854 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI88_91; /* offset: 0x0858 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI92_95; /* offset: 0x085C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI96_99; /* offset: 0x0860 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI100_103; /* offset: 0x0864 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI104_107; /* offset: 0x0868 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI108_111; /* offset: 0x086C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI112_115; /* offset: 0x0870 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI116_119; /* offset: 0x0874 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI120_123; /* offset: 0x0878 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI124_127; /* offset: 0x087C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI128_131; /* offset: 0x0880 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI132_135; /* offset: 0x0884 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI136_139; /* offset: 0x0888 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI140_143; /* offset: 0x088C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI144_147; /* offset: 0x0890 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI148_151; /* offset: 0x0894 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI152_155; /* offset: 0x0898 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI156_159; /* offset: 0x089C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI160_163; /* offset: 0x08A0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI164_167; /* offset: 0x08A4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI168_171; /* offset: 0x08A8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI172_175; /* offset: 0x08AC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI176_179; /* offset: 0x08B0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI180_183; /* offset: 0x08B4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI184_187; /* offset: 0x08B8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI188_191; /* offset: 0x08BC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI192_195; /* offset: 0x08C0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI196_199; /* offset: 0x08C4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI200_203; /* offset: 0x08C8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI204_207; /* offset: 0x08CC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI208_211; /* offset: 0x08D0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI212_215; /* offset: 0x08D4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI216_219; /* offset: 0x08D8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI220_223; /* offset: 0x08DC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI224_227; /* offset: 0x08E0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI228_231; /* offset: 0x08E4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI232_235; /* offset: 0x08E8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI236_239; /* offset: 0x08EC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI240_243; /* offset: 0x08F0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI244_247; /* offset: 0x08F4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI248_251; /* offset: 0x08F8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI252_255; /* offset: 0x08FC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI256_259; /* offset: 0x0900 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI260_263; /* offset: 0x0904 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI264_267; /* offset: 0x0908 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI268_271; /* offset: 0x090C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI272_275; /* offset: 0x0910 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI276_279; /* offset: 0x0914 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI280_283; /* offset: 0x0918 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI284_287; /* offset: 0x091C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI288_291; /* offset: 0x0920 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI292_295; /* offset: 0x0924 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI296_299; /* offset: 0x0928 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI300_303; /* offset: 0x092C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI304_307; /* offset: 0x0930 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI308_311; /* offset: 0x0934 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI312_315; /* offset: 0x0938 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI316_319; /* offset: 0x093C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI320_323; /* offset: 0x0940 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI324_327; /* offset: 0x0944 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI328_331; /* offset: 0x0948 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI332_335; /* offset: 0x094C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI336_339; /* offset: 0x0950 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI340_343; /* offset: 0x0954 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI344_347; /* offset: 0x0958 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI348_351; /* offset: 0x095C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI352_355; /* offset: 0x0960 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI356_359; /* offset: 0x0964 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI360_363; /* offset: 0x0968 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI364_367; /* offset: 0x096C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI368_371; /* offset: 0x0970 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI372_375; /* offset: 0x0974 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI376_379; /* offset: 0x0978 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI380_383; /* offset: 0x097C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI384_387; /* offset: 0x0980 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI388_391; /* offset: 0x0984 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI392_395; /* offset: 0x0988 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI396_399; /* offset: 0x098C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI400_403; /* offset: 0x0990 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI404_407; /* offset: 0x0994 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI408_411; /* offset: 0x0998 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI412_415; /* offset: 0x099C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI416_419; /* offset: 0x09A0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI420_423; /* offset: 0x09A4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI424_427; /* offset: 0x09A8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI428_431; /* offset: 0x09AC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI432_435; /* offset: 0x09B0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI436_439; /* offset: 0x09B4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI440_443; /* offset: 0x09B8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI444_447; /* offset: 0x09BC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI448_451; /* offset: 0x09C0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI452_455; /* offset: 0x09C4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI456_459; /* offset: 0x09C8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI460_463; /* offset: 0x09CC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI464_467; /* offset: 0x09D0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI468_471; /* offset: 0x09D4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI472_475; /* offset: 0x09D8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI476_479; /* offset: 0x09DC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI480_483; /* offset: 0x09E0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI484_487; /* offset: 0x09E4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI488_491; /* offset: 0x09E8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI492_495; /* offset: 0x09EC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI496_499; /* offset: 0x09F0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI500_503; /* offset: 0x09F4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI504_507; /* offset: 0x09F8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI508_511; /* offset: 0x09FC size: 32 bit */ + }; + + struct { + /* GPDI - GPIO Pad Data Input Register */ + SIUL_GPDI_8B_tag GPDI0; /* offset: 0x0800 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI1; /* offset: 0x0801 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI2; /* offset: 0x0802 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI3; /* offset: 0x0803 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI4; /* offset: 0x0804 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI5; /* offset: 0x0805 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI6; /* offset: 0x0806 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI7; /* offset: 0x0807 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI8; /* offset: 0x0808 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI9; /* offset: 0x0809 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI10; /* offset: 0x080A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI11; /* offset: 0x080B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI12; /* offset: 0x080C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI13; /* offset: 0x080D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI14; /* offset: 0x080E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI15; /* offset: 0x080F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI16; /* offset: 0x0810 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI17; /* offset: 0x0811 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI18; /* offset: 0x0812 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI19; /* offset: 0x0813 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI20; /* offset: 0x0814 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI21; /* offset: 0x0815 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI22; /* offset: 0x0816 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI23; /* offset: 0x0817 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI24; /* offset: 0x0818 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI25; /* offset: 0x0819 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI26; /* offset: 0x081A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI27; /* offset: 0x081B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI28; /* offset: 0x081C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI29; /* offset: 0x081D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI30; /* offset: 0x081E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI31; /* offset: 0x081F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI32; /* offset: 0x0820 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI33; /* offset: 0x0821 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI34; /* offset: 0x0822 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI35; /* offset: 0x0823 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI36; /* offset: 0x0824 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI37; /* offset: 0x0825 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI38; /* offset: 0x0826 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI39; /* offset: 0x0827 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI40; /* offset: 0x0828 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI41; /* offset: 0x0829 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI42; /* offset: 0x082A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI43; /* offset: 0x082B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI44; /* offset: 0x082C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI45; /* offset: 0x082D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI46; /* offset: 0x082E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI47; /* offset: 0x082F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI48; /* offset: 0x0830 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI49; /* offset: 0x0831 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI50; /* offset: 0x0832 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI51; /* offset: 0x0833 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI52; /* offset: 0x0834 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI53; /* offset: 0x0835 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI54; /* offset: 0x0836 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI55; /* offset: 0x0837 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI56; /* offset: 0x0838 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI57; /* offset: 0x0839 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI58; /* offset: 0x083A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI59; /* offset: 0x083B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI60; /* offset: 0x083C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI61; /* offset: 0x083D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI62; /* offset: 0x083E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI63; /* offset: 0x083F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI64; /* offset: 0x0840 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI65; /* offset: 0x0841 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI66; /* offset: 0x0842 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI67; /* offset: 0x0843 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI68; /* offset: 0x0844 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI69; /* offset: 0x0845 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI70; /* offset: 0x0846 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI71; /* offset: 0x0847 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI72; /* offset: 0x0848 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI73; /* offset: 0x0849 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI74; /* offset: 0x084A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI75; /* offset: 0x084B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI76; /* offset: 0x084C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI77; /* offset: 0x084D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI78; /* offset: 0x084E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI79; /* offset: 0x084F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI80; /* offset: 0x0850 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI81; /* offset: 0x0851 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI82; /* offset: 0x0852 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI83; /* offset: 0x0853 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI84; /* offset: 0x0854 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI85; /* offset: 0x0855 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI86; /* offset: 0x0856 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI87; /* offset: 0x0857 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI88; /* offset: 0x0858 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI89; /* offset: 0x0859 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI90; /* offset: 0x085A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI91; /* offset: 0x085B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI92; /* offset: 0x085C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI93; /* offset: 0x085D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI94; /* offset: 0x085E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI95; /* offset: 0x085F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI96; /* offset: 0x0860 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI97; /* offset: 0x0861 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI98; /* offset: 0x0862 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI99; /* offset: 0x0863 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI100; /* offset: 0x0864 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI101; /* offset: 0x0865 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI102; /* offset: 0x0866 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI103; /* offset: 0x0867 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI104; /* offset: 0x0868 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI105; /* offset: 0x0869 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI106; /* offset: 0x086A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI107; /* offset: 0x086B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI108; /* offset: 0x086C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI109; /* offset: 0x086D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI110; /* offset: 0x086E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI111; /* offset: 0x086F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI112; /* offset: 0x0870 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI113; /* offset: 0x0871 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI114; /* offset: 0x0872 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI115; /* offset: 0x0873 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI116; /* offset: 0x0874 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI117; /* offset: 0x0875 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI118; /* offset: 0x0876 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI119; /* offset: 0x0877 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI120; /* offset: 0x0878 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI121; /* offset: 0x0879 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI122; /* offset: 0x087A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI123; /* offset: 0x087B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI124; /* offset: 0x087C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI125; /* offset: 0x087D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI126; /* offset: 0x087E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI127; /* offset: 0x087F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI128; /* offset: 0x0880 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI129; /* offset: 0x0881 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI130; /* offset: 0x0882 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI131; /* offset: 0x0883 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI132; /* offset: 0x0884 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI133; /* offset: 0x0885 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI134; /* offset: 0x0886 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI135; /* offset: 0x0887 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI136; /* offset: 0x0888 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI137; /* offset: 0x0889 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI138; /* offset: 0x088A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI139; /* offset: 0x088B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI140; /* offset: 0x088C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI141; /* offset: 0x088D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI142; /* offset: 0x088E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI143; /* offset: 0x088F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI144; /* offset: 0x0890 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI145; /* offset: 0x0891 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI146; /* offset: 0x0892 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI147; /* offset: 0x0893 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI148; /* offset: 0x0894 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI149; /* offset: 0x0895 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI150; /* offset: 0x0896 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI151; /* offset: 0x0897 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI152; /* offset: 0x0898 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI153; /* offset: 0x0899 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI154; /* offset: 0x089A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI155; /* offset: 0x089B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI156; /* offset: 0x089C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI157; /* offset: 0x089D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI158; /* offset: 0x089E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI159; /* offset: 0x089F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI160; /* offset: 0x08A0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI161; /* offset: 0x08A1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI162; /* offset: 0x08A2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI163; /* offset: 0x08A3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI164; /* offset: 0x08A4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI165; /* offset: 0x08A5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI166; /* offset: 0x08A6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI167; /* offset: 0x08A7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI168; /* offset: 0x08A8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI169; /* offset: 0x08A9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI170; /* offset: 0x08AA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI171; /* offset: 0x08AB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI172; /* offset: 0x08AC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI173; /* offset: 0x08AD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI174; /* offset: 0x08AE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI175; /* offset: 0x08AF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI176; /* offset: 0x08B0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI177; /* offset: 0x08B1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI178; /* offset: 0x08B2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI179; /* offset: 0x08B3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI180; /* offset: 0x08B4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI181; /* offset: 0x08B5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI182; /* offset: 0x08B6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI183; /* offset: 0x08B7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI184; /* offset: 0x08B8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI185; /* offset: 0x08B9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI186; /* offset: 0x08BA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI187; /* offset: 0x08BB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI188; /* offset: 0x08BC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI189; /* offset: 0x08BD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI190; /* offset: 0x08BE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI191; /* offset: 0x08BF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI192; /* offset: 0x08C0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI193; /* offset: 0x08C1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI194; /* offset: 0x08C2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI195; /* offset: 0x08C3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI196; /* offset: 0x08C4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI197; /* offset: 0x08C5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI198; /* offset: 0x08C6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI199; /* offset: 0x08C7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI200; /* offset: 0x08C8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI201; /* offset: 0x08C9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI202; /* offset: 0x08CA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI203; /* offset: 0x08CB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI204; /* offset: 0x08CC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI205; /* offset: 0x08CD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI206; /* offset: 0x08CE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI207; /* offset: 0x08CF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI208; /* offset: 0x08D0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI209; /* offset: 0x08D1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI210; /* offset: 0x08D2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI211; /* offset: 0x08D3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI212; /* offset: 0x08D4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI213; /* offset: 0x08D5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI214; /* offset: 0x08D6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI215; /* offset: 0x08D7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI216; /* offset: 0x08D8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI217; /* offset: 0x08D9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI218; /* offset: 0x08DA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI219; /* offset: 0x08DB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI220; /* offset: 0x08DC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI221; /* offset: 0x08DD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI222; /* offset: 0x08DE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI223; /* offset: 0x08DF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI224; /* offset: 0x08E0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI225; /* offset: 0x08E1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI226; /* offset: 0x08E2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI227; /* offset: 0x08E3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI228; /* offset: 0x08E4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI229; /* offset: 0x08E5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI230; /* offset: 0x08E6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI231; /* offset: 0x08E7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI232; /* offset: 0x08E8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI233; /* offset: 0x08E9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI234; /* offset: 0x08EA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI235; /* offset: 0x08EB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI236; /* offset: 0x08EC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI237; /* offset: 0x08ED size: 8 bit */ + SIUL_GPDI_8B_tag GPDI238; /* offset: 0x08EE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI239; /* offset: 0x08EF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI240; /* offset: 0x08F0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI241; /* offset: 0x08F1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI242; /* offset: 0x08F2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI243; /* offset: 0x08F3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI244; /* offset: 0x08F4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI245; /* offset: 0x08F5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI246; /* offset: 0x08F6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI247; /* offset: 0x08F7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI248; /* offset: 0x08F8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI249; /* offset: 0x08F9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI250; /* offset: 0x08FA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI251; /* offset: 0x08FB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI252; /* offset: 0x08FC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI253; /* offset: 0x08FD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI254; /* offset: 0x08FE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI255; /* offset: 0x08FF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI256; /* offset: 0x0900 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI257; /* offset: 0x0901 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI258; /* offset: 0x0902 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI259; /* offset: 0x0903 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI260; /* offset: 0x0904 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI261; /* offset: 0x0905 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI262; /* offset: 0x0906 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI263; /* offset: 0x0907 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI264; /* offset: 0x0908 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI265; /* offset: 0x0909 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI266; /* offset: 0x090A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI267; /* offset: 0x090B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI268; /* offset: 0x090C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI269; /* offset: 0x090D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI270; /* offset: 0x090E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI271; /* offset: 0x090F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI272; /* offset: 0x0910 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI273; /* offset: 0x0911 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI274; /* offset: 0x0912 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI275; /* offset: 0x0913 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI276; /* offset: 0x0914 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI277; /* offset: 0x0915 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI278; /* offset: 0x0916 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI279; /* offset: 0x0917 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI280; /* offset: 0x0918 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI281; /* offset: 0x0919 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI282; /* offset: 0x091A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI283; /* offset: 0x091B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI284; /* offset: 0x091C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI285; /* offset: 0x091D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI286; /* offset: 0x091E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI287; /* offset: 0x091F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI288; /* offset: 0x0920 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI289; /* offset: 0x0921 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI290; /* offset: 0x0922 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI291; /* offset: 0x0923 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI292; /* offset: 0x0924 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI293; /* offset: 0x0925 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI294; /* offset: 0x0926 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI295; /* offset: 0x0927 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI296; /* offset: 0x0928 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI297; /* offset: 0x0929 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI298; /* offset: 0x092A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI299; /* offset: 0x092B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI300; /* offset: 0x092C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI301; /* offset: 0x092D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI302; /* offset: 0x092E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI303; /* offset: 0x092F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI304; /* offset: 0x0930 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI305; /* offset: 0x0931 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI306; /* offset: 0x0932 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI307; /* offset: 0x0933 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI308; /* offset: 0x0934 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI309; /* offset: 0x0935 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI310; /* offset: 0x0936 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI311; /* offset: 0x0937 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI312; /* offset: 0x0938 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI313; /* offset: 0x0939 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI314; /* offset: 0x093A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI315; /* offset: 0x093B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI316; /* offset: 0x093C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI317; /* offset: 0x093D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI318; /* offset: 0x093E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI319; /* offset: 0x093F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI320; /* offset: 0x0940 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI321; /* offset: 0x0941 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI322; /* offset: 0x0942 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI323; /* offset: 0x0943 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI324; /* offset: 0x0944 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI325; /* offset: 0x0945 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI326; /* offset: 0x0946 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI327; /* offset: 0x0947 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI328; /* offset: 0x0948 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI329; /* offset: 0x0949 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI330; /* offset: 0x094A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI331; /* offset: 0x094B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI332; /* offset: 0x094C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI333; /* offset: 0x094D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI334; /* offset: 0x094E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI335; /* offset: 0x094F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI336; /* offset: 0x0950 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI337; /* offset: 0x0951 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI338; /* offset: 0x0952 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI339; /* offset: 0x0953 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI340; /* offset: 0x0954 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI341; /* offset: 0x0955 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI342; /* offset: 0x0956 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI343; /* offset: 0x0957 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI344; /* offset: 0x0958 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI345; /* offset: 0x0959 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI346; /* offset: 0x095A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI347; /* offset: 0x095B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI348; /* offset: 0x095C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI349; /* offset: 0x095D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI350; /* offset: 0x095E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI351; /* offset: 0x095F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI352; /* offset: 0x0960 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI353; /* offset: 0x0961 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI354; /* offset: 0x0962 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI355; /* offset: 0x0963 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI356; /* offset: 0x0964 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI357; /* offset: 0x0965 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI358; /* offset: 0x0966 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI359; /* offset: 0x0967 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI360; /* offset: 0x0968 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI361; /* offset: 0x0969 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI362; /* offset: 0x096A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI363; /* offset: 0x096B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI364; /* offset: 0x096C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI365; /* offset: 0x096D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI366; /* offset: 0x096E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI367; /* offset: 0x096F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI368; /* offset: 0x0970 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI369; /* offset: 0x0971 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI370; /* offset: 0x0972 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI371; /* offset: 0x0973 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI372; /* offset: 0x0974 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI373; /* offset: 0x0975 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI374; /* offset: 0x0976 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI375; /* offset: 0x0977 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI376; /* offset: 0x0978 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI377; /* offset: 0x0979 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI378; /* offset: 0x097A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI379; /* offset: 0x097B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI380; /* offset: 0x097C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI381; /* offset: 0x097D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI382; /* offset: 0x097E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI383; /* offset: 0x097F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI384; /* offset: 0x0980 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI385; /* offset: 0x0981 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI386; /* offset: 0x0982 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI387; /* offset: 0x0983 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI388; /* offset: 0x0984 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI389; /* offset: 0x0985 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI390; /* offset: 0x0986 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI391; /* offset: 0x0987 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI392; /* offset: 0x0988 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI393; /* offset: 0x0989 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI394; /* offset: 0x098A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI395; /* offset: 0x098B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI396; /* offset: 0x098C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI397; /* offset: 0x098D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI398; /* offset: 0x098E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI399; /* offset: 0x098F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI400; /* offset: 0x0990 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI401; /* offset: 0x0991 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI402; /* offset: 0x0992 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI403; /* offset: 0x0993 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI404; /* offset: 0x0994 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI405; /* offset: 0x0995 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI406; /* offset: 0x0996 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI407; /* offset: 0x0997 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI408; /* offset: 0x0998 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI409; /* offset: 0x0999 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI410; /* offset: 0x099A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI411; /* offset: 0x099B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI412; /* offset: 0x099C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI413; /* offset: 0x099D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI414; /* offset: 0x099E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI415; /* offset: 0x099F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI416; /* offset: 0x09A0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI417; /* offset: 0x09A1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI418; /* offset: 0x09A2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI419; /* offset: 0x09A3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI420; /* offset: 0x09A4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI421; /* offset: 0x09A5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI422; /* offset: 0x09A6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI423; /* offset: 0x09A7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI424; /* offset: 0x09A8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI425; /* offset: 0x09A9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI426; /* offset: 0x09AA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI427; /* offset: 0x09AB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI428; /* offset: 0x09AC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI429; /* offset: 0x09AD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI430; /* offset: 0x09AE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI431; /* offset: 0x09AF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI432; /* offset: 0x09B0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI433; /* offset: 0x09B1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI434; /* offset: 0x09B2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI435; /* offset: 0x09B3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI436; /* offset: 0x09B4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI437; /* offset: 0x09B5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI438; /* offset: 0x09B6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI439; /* offset: 0x09B7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI440; /* offset: 0x09B8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI441; /* offset: 0x09B9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI442; /* offset: 0x09BA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI443; /* offset: 0x09BB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI444; /* offset: 0x09BC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI445; /* offset: 0x09BD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI446; /* offset: 0x09BE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI447; /* offset: 0x09BF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI448; /* offset: 0x09C0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI449; /* offset: 0x09C1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI450; /* offset: 0x09C2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI451; /* offset: 0x09C3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI452; /* offset: 0x09C4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI453; /* offset: 0x09C5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI454; /* offset: 0x09C6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI455; /* offset: 0x09C7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI456; /* offset: 0x09C8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI457; /* offset: 0x09C9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI458; /* offset: 0x09CA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI459; /* offset: 0x09CB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI460; /* offset: 0x09CC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI461; /* offset: 0x09CD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI462; /* offset: 0x09CE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI463; /* offset: 0x09CF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI464; /* offset: 0x09D0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI465; /* offset: 0x09D1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI466; /* offset: 0x09D2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI467; /* offset: 0x09D3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI468; /* offset: 0x09D4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI469; /* offset: 0x09D5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI470; /* offset: 0x09D6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI471; /* offset: 0x09D7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI472; /* offset: 0x09D8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI473; /* offset: 0x09D9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI474; /* offset: 0x09DA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI475; /* offset: 0x09DB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI476; /* offset: 0x09DC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI477; /* offset: 0x09DD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI478; /* offset: 0x09DE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI479; /* offset: 0x09DF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI480; /* offset: 0x09E0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI481; /* offset: 0x09E1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI482; /* offset: 0x09E2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI483; /* offset: 0x09E3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI484; /* offset: 0x09E4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI485; /* offset: 0x09E5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI486; /* offset: 0x09E6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI487; /* offset: 0x09E7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI488; /* offset: 0x09E8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI489; /* offset: 0x09E9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI490; /* offset: 0x09EA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI491; /* offset: 0x09EB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI492; /* offset: 0x09EC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI493; /* offset: 0x09ED size: 8 bit */ + SIUL_GPDI_8B_tag GPDI494; /* offset: 0x09EE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI495; /* offset: 0x09EF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI496; /* offset: 0x09F0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI497; /* offset: 0x09F1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI498; /* offset: 0x09F2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI499; /* offset: 0x09F3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI500; /* offset: 0x09F4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI501; /* offset: 0x09F5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI502; /* offset: 0x09F6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI503; /* offset: 0x09F7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI504; /* offset: 0x09F8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI505; /* offset: 0x09F9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI506; /* offset: 0x09FA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI507; /* offset: 0x09FB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI508; /* offset: 0x09FC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI509; /* offset: 0x09FD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI510; /* offset: 0x09FE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI511; /* offset: 0x09FF size: 8 bit */ + }; + + }; + int8_t SIUL_reserved_0A00_C[512]; + union { + /* PGPDO - Parallel GPIO Pad Data Out Register */ + SIUL_PGPDO_16B_tag PGPDO[32]; /* offset: 0x0C00 (0x0002 x 32) */ + + struct { + /* PGPDO - Parallel GPIO Pad Data Out Register */ + SIUL_PGPDO_16B_tag PGPDO0; /* offset: 0x0C00 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO1; /* offset: 0x0C02 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO2; /* offset: 0x0C04 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO3; /* offset: 0x0C06 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO4; /* offset: 0x0C08 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO5; /* offset: 0x0C0A size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO6; /* offset: 0x0C0C size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO7; /* offset: 0x0C0E size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO8; /* offset: 0x0C10 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO9; /* offset: 0x0C12 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO10; /* offset: 0x0C14 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO11; /* offset: 0x0C16 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO12; /* offset: 0x0C18 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO13; /* offset: 0x0C1A size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO14; /* offset: 0x0C1C size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO15; /* offset: 0x0C1E size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO16; /* offset: 0x0C20 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO17; /* offset: 0x0C22 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO18; /* offset: 0x0C24 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO19; /* offset: 0x0C26 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO20; /* offset: 0x0C28 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO21; /* offset: 0x0C2A size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO22; /* offset: 0x0C2C size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO23; /* offset: 0x0C2E size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO24; /* offset: 0x0C30 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO25; /* offset: 0x0C32 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO26; /* offset: 0x0C34 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO27; /* offset: 0x0C36 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO28; /* offset: 0x0C38 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO29; /* offset: 0x0C3A size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO30; /* offset: 0x0C3C size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO31; /* offset: 0x0C3E size: 16 bit */ + }; + + }; + union { + /* PGPDI - Parallel GPIO Pad Data In Register */ + SIUL_PGPDI_16B_tag PGPDI[32]; /* offset: 0x0C40 (0x0002 x 32) */ + + struct { + /* PGPDI - Parallel GPIO Pad Data In Register */ + SIUL_PGPDI_16B_tag PGPDI0; /* offset: 0x0C40 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI1; /* offset: 0x0C42 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI2; /* offset: 0x0C44 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI3; /* offset: 0x0C46 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI4; /* offset: 0x0C48 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI5; /* offset: 0x0C4A size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI6; /* offset: 0x0C4C size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI7; /* offset: 0x0C4E size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI8; /* offset: 0x0C50 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI9; /* offset: 0x0C52 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI10; /* offset: 0x0C54 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI11; /* offset: 0x0C56 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI12; /* offset: 0x0C58 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI13; /* offset: 0x0C5A size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI14; /* offset: 0x0C5C size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI15; /* offset: 0x0C5E size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI16; /* offset: 0x0C60 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI17; /* offset: 0x0C62 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI18; /* offset: 0x0C64 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI19; /* offset: 0x0C66 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI20; /* offset: 0x0C68 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI21; /* offset: 0x0C6A size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI22; /* offset: 0x0C6C size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI23; /* offset: 0x0C6E size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI24; /* offset: 0x0C70 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI25; /* offset: 0x0C72 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI26; /* offset: 0x0C74 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI27; /* offset: 0x0C76 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI28; /* offset: 0x0C78 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI29; /* offset: 0x0C7A size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI30; /* offset: 0x0C7C size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI31; /* offset: 0x0C7E size: 16 bit */ + }; + + }; + union { + /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ + SIUL_MPGPDO_32B_tag MPGPDO[32]; /* offset: 0x0C80 (0x0004 x 32) */ + + struct { + /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ + SIUL_MPGPDO_32B_tag MPGPDO0; /* offset: 0x0C80 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO1; /* offset: 0x0C84 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO2; /* offset: 0x0C88 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO3; /* offset: 0x0C8C size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO4; /* offset: 0x0C90 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO5; /* offset: 0x0C94 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO6; /* offset: 0x0C98 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO7; /* offset: 0x0C9C size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO8; /* offset: 0x0CA0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO9; /* offset: 0x0CA4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO10; /* offset: 0x0CA8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO11; /* offset: 0x0CAC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO12; /* offset: 0x0CB0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO13; /* offset: 0x0CB4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO14; /* offset: 0x0CB8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO15; /* offset: 0x0CBC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO16; /* offset: 0x0CC0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO17; /* offset: 0x0CC4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO18; /* offset: 0x0CC8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO19; /* offset: 0x0CCC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO20; /* offset: 0x0CD0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO21; /* offset: 0x0CD4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO22; /* offset: 0x0CD8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO23; /* offset: 0x0CDC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO24; /* offset: 0x0CE0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO25; /* offset: 0x0CE4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO26; /* offset: 0x0CE8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO27; /* offset: 0x0CEC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO28; /* offset: 0x0CF0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO29; /* offset: 0x0CF4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO30; /* offset: 0x0CF8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO31; /* offset: 0x0CFC size: 32 bit */ + }; + + }; + int8_t SIUL_reserved_0D00_C[768]; + union { + /* IFMC - Interrupt Filter Maximum Counter Register */ + SIUL_IFMC_32B_tag IFMC[32]; /* offset: 0x1000 (0x0004 x 32) */ + + struct { + /* IFMC - Interrupt Filter Maximum Counter Register */ + SIUL_IFMC_32B_tag IFMC0; /* offset: 0x1000 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC1; /* offset: 0x1004 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC2; /* offset: 0x1008 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC3; /* offset: 0x100C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC4; /* offset: 0x1010 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC5; /* offset: 0x1014 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC6; /* offset: 0x1018 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC7; /* offset: 0x101C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC8; /* offset: 0x1020 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC9; /* offset: 0x1024 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC10; /* offset: 0x1028 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC11; /* offset: 0x102C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC12; /* offset: 0x1030 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC13; /* offset: 0x1034 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC14; /* offset: 0x1038 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC15; /* offset: 0x103C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC16; /* offset: 0x1040 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC17; /* offset: 0x1044 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC18; /* offset: 0x1048 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC19; /* offset: 0x104C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC20; /* offset: 0x1050 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC21; /* offset: 0x1054 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC22; /* offset: 0x1058 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC23; /* offset: 0x105C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC24; /* offset: 0x1060 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC25; /* offset: 0x1064 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC26; /* offset: 0x1068 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC27; /* offset: 0x106C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC28; /* offset: 0x1070 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC29; /* offset: 0x1074 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC30; /* offset: 0x1078 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC31; /* offset: 0x107C size: 32 bit */ + }; + + }; + /* IFCPR - Inerrupt Filter Clock Prescaler Register */ + SIUL_IFCPR_32B_tag IFCPR; /* offset: 0x1080 size: 32 bit */ + } SIU_tag; + + +#define SIUL (*(volatile SIU_tag *) 0xC3F90000UL) + + + +/****************************************************************/ +/* */ +/* Module: WKPU */ +/* */ +/****************************************************************/ + + typedef union { /* WKPU_NSR - NMI Status Flag Register */ + uint32_t R; + struct { + uint32_t NIF0:1; /* NMI Status Flag 0 */ + uint32_t NOVF0:1; /* NMI Overrun Status Flag 0 */ + uint32_t:6; + uint32_t NIF1:1; /* NMI Status Flag 1 */ + uint32_t NOVF1:1; /* NMI Overrun Status Flag 1 */ + uint32_t:6; + uint32_t NIF2:1; /* NMI Status Flag 2 */ + uint32_t NOVF2:1; /* NMI Overrun Status Flag 2 */ + uint32_t:6; + uint32_t NIF3:1; /* NMI Status Flag 3 */ + uint32_t NOVF3:1; /* NMI Overrun Status Flag 3 */ + uint32_t:6; + } B; + } WKPU_NSR_32B_tag; + + typedef union { /* WKPU_NCR - NMI Configuration Register */ + uint32_t R; + struct { + uint32_t NLOCK0:1; /* NMI Configuration Lock Register 0 */ + uint32_t NDSS0:2; /* NMI Desination Source Select 0 */ + uint32_t NWRE0:1; /* NMI Wakeup Request Enable 0 */ + uint32_t:1; + uint32_t NREE0:1; /* NMI Rising Edge Events Enable 0 */ + uint32_t NFEE0:1; /* NMI Falling Edge Events Enable 0 */ + uint32_t NFE0:1; /* NMI Filter Enable 0 */ + uint32_t NLOCK1:1; /* NMI Configuration Lock Register 1 */ + uint32_t NDSS1:2; /* NMI Desination Source Select 1 */ + uint32_t NWRE1:1; /* NMI Wakeup Request Enable 1 */ + uint32_t:1; + uint32_t NREE1:1; /* NMI Rising Edge Events Enable 1 */ + uint32_t NFEE1:1; /* NMI Falling Edge Events Enable 1 */ + uint32_t NFE1:1; /* NMI Filter Enable 1 */ + uint32_t NLOCK2:1; /* NMI Configuration Lock Register 2 */ + uint32_t NDSS2:2; /* NMI Desination Source Select 2 */ + uint32_t NWRE2:1; /* NMI Wakeup Request Enable 2 */ + uint32_t:1; + uint32_t NREE2:1; /* NMI Rising Edge Events Enable 2 */ + uint32_t NFEE2:1; /* NMI Falling Edge Events Enable 2 */ + uint32_t NFE2:1; /* NMI Filter Enable 2 */ + uint32_t NLOCK3:1; /* NMI Configuration Lock Register 3 */ + uint32_t NDSS3:2; /* NMI Desination Source Select 3 */ + uint32_t NWRE3:1; /* NMI Wakeup Request Enable 3 */ + uint32_t:1; + uint32_t NREE3:1; /* NMI Rising Edge Events Enable 3 */ + uint32_t NFEE3:1; /* NMI Falling Edge Events Enable 3 */ + uint32_t NFE3:1; /* NMI Filter Enable 3 */ + } B; + } WKPU_NCR_32B_tag; + + typedef union { /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */ + uint32_t R; + struct { + uint32_t EIF:32; /* External Wakeup/Interrupt Status Flag */ + } B; + } WKPU_WISR_32B_tag; + + typedef union { /* WKPU_IRER - Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t EIRE:32; /* Enable External Interrupt Requests */ + } B; + } WKPU_IRER_32B_tag; + + typedef union { /* WKPU_WRER - Wakeup Request Enable Register */ + uint32_t R; + struct { + uint32_t WRE:32; /* Enable Wakeup requests to the mode entry module */ + } B; + } WKPU_WRER_32B_tag; + + typedef union { /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t IREE:32; /* Enable rising-edge events to cause EIF[x] to be set */ + } B; + } WKPU_WIREER_32B_tag; + + typedef union { /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t IFEE:32; /* Enable Falling-edge events to cause EIF[x] to be set */ + } B; + } WKPU_WIFEER_32B_tag; + + typedef union { /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */ + uint32_t R; + struct { + uint32_t IFE:32; /* Enable Digital glitch filter on the interrupt pad input */ + } B; + } WKPU_WIFER_32B_tag; + + typedef union { /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */ + uint32_t R; + struct { + uint32_t IPUE:32; /* Enable a pullup on the interrupt pad input */ + } B; + } WKPU_WIPUER_32B_tag; + + + + typedef struct WKPU_struct_tag { /* start of WKPU_tag */ + /* WKPU_NSR - NMI Status Flag Register */ + WKPU_NSR_32B_tag NSR; /* offset: 0x0000 size: 32 bit */ + int8_t WKPU_reserved_0004[4]; + /* WKPU_NCR - NMI Configuration Register */ + WKPU_NCR_32B_tag NCR; /* offset: 0x0008 size: 32 bit */ + int8_t WKPU_reserved_000C[8]; + /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */ + WKPU_WISR_32B_tag WISR; /* offset: 0x0014 size: 32 bit */ + /* WKPU_IRER - Interrupt Request Enable Register */ + WKPU_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */ + /* WKPU_WRER - Wakeup Request Enable Register */ + WKPU_WRER_32B_tag WRER; /* offset: 0x001C size: 32 bit */ + int8_t WKPU_reserved_0020[8]; + /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */ + WKPU_WIREER_32B_tag WIREER; /* offset: 0x0028 size: 32 bit */ + /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */ + WKPU_WIFEER_32B_tag WIFEER; /* offset: 0x002C size: 32 bit */ + /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */ + WKPU_WIFER_32B_tag WIFER; /* offset: 0x0030 size: 32 bit */ + /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */ + WKPU_WIPUER_32B_tag WIPUER; /* offset: 0x0034 size: 32 bit */ + } WKPU_tag; + + +#define WKPU (*(volatile WKPU_tag *) 0xC3F94000UL) + + + +/****************************************************************/ +/* */ +/* Module: SSCM */ +/* */ +/****************************************************************/ + + typedef union { /* SSCM_STATUS - System Status Register */ + uint16_t R; + struct { + uint16_t LSM:1; /* Lock Step Mode */ + uint16_t:2; + uint16_t NXEN1:1; /* Processor 1 Nexus enabled */ + uint16_t NXEN:1; /* Processor 0 Nexus enabled */ + uint16_t PUB:1; /* Public Serial Access Status */ + uint16_t SEC:1; /* Security Status */ + uint16_t:1; + uint16_t BMODE:3; /* Device Boot Mode */ + uint16_t VLE:1; /* Variable Length Instruction Mode */ + uint16_t ABD:1; /* Autobaud detection */ + uint16_t:3; + } B; + } SSCM_STATUS_16B_tag; + + typedef union { /* SSCM_MEMCONFIG - System Memory Configuration Register */ + uint16_t R; + struct { + uint16_t JPIN:10; /* JTAG Part ID Number */ + uint16_t IVLD:1; /* Instruction Flash Valid */ + uint16_t MREV:4; /* Minor Mask Revision */ + uint16_t DVLD:1; /* Data Flash Valid */ + } B; + } SSCM_MEMCONFIG_16B_tag; + + typedef union { /* SSCM_ERROR - Error Configuration */ + uint16_t R; + struct { + uint16_t:14; + uint16_t PAE:1; /* Peripheral Bus Abort Enable */ + uint16_t RAE:1; /* Register Bus Abort Enable */ + } B; + } SSCM_ERROR_16B_tag; + + typedef union { /* SSCM_DEBUGPORT - Debug Status Port Register */ + uint16_t R; + struct { + uint16_t:13; + uint16_t DEBUG_MODE:3; /* Debug Status Port Mode */ + } B; + } SSCM_DEBUGPORT_16B_tag; + + typedef union { /* SSCM_PWCMPH - Password Comparison Register High */ + uint32_t R; + struct { + uint32_t PWD_HI:32; /* Password High */ + } B; + } SSCM_PWCMPH_32B_tag; + + typedef union { /* SSCM_PWCMPL - Password Comparison Register Low */ + uint32_t R; + struct { + uint32_t PWD_LO:32; /* Password Low */ + } B; + } SSCM_PWCMPL_32B_tag; + + typedef union { /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */ + uint32_t R; + struct { + uint32_t P2BOOT:30; /* boot location 2nd processor */ + uint32_t DVLE:1; /* VLE mode for 2nd processor */ + uint32_t:1; + } B; + } SSCM_DPMBOOT_32B_tag; + + typedef union { /* SSCM_DPMKEY - Boot Key Register */ + uint32_t R; + struct { + uint32_t KEY:32; /* Boot Control Key */ + } B; + } SSCM_DPMKEY_32B_tag; + + typedef union { /* SSCM_UOPS - User Option Status Register */ + uint32_t R; + struct { + uint32_t UOPT:32; /* User Option Bits */ + } B; + } SSCM_UOPS_32B_tag; + + typedef union { /* SSCM_SCTR - SSCM Control Register */ + uint32_t R; + struct { + uint32_t:29; + uint32_t TFE:1; /* Test Flash Enable */ + uint32_t DSL:1; /* Disable Software-Controlled MBIST */ + uint32_t DSM:1; /* Disable Software-Controlled LBIST */ + } B; + } SSCM_SCTR_32B_tag; + + typedef union { /* SSCM_TF_INFO0 - TestFlash Information Register 0 */ + uint32_t R; + struct { + uint32_t TINFO0:32; /* General purpose TestFlash word 0 */ + } B; + } SSCM_TF_INFO0_32B_tag; + + typedef union { /* SSCM_TF_INFO1 - TestFlash Information Register 1 */ + uint32_t R; + struct { + uint32_t TINFO1:32; /* General purpose TestFlash word 1 */ + } B; + } SSCM_TF_INFO1_32B_tag; + + typedef union { /* SSCM_TF_INFO2 - TestFlash Information Register 2 */ + uint32_t R; + struct { + uint32_t TINFO2:32; /* General purpose TestFlash word 2 */ + } B; + } SSCM_TF_INFO2_32B_tag; + + typedef union { /* SSCM_TF_INFO3 - TestFlash Information Register 3 */ + uint32_t R; + struct { + uint32_t TINFO3:32; /* General purpose TestFlash word */ + } B; + } SSCM_TF_INFO3_32B_tag; + + + + typedef struct SSCM_struct_tag { /* start of SSCM_tag */ + /* SSCM_STATUS - System Status Register */ + SSCM_STATUS_16B_tag STATUS; /* offset: 0x0000 size: 16 bit */ + /* SSCM_MEMCONFIG - System Memory Configuration Register */ + SSCM_MEMCONFIG_16B_tag MEMCONFIG; /* offset: 0x0002 size: 16 bit */ + int8_t SSCM_reserved_0004[2]; + /* SSCM_ERROR - Error Configuration */ + SSCM_ERROR_16B_tag ERROR; /* offset: 0x0006 size: 16 bit */ + /* SSCM_DEBUGPORT - Debug Status Port Register */ + SSCM_DEBUGPORT_16B_tag DEBUGPORT; /* offset: 0x0008 size: 16 bit */ + int8_t SSCM_reserved_000A[2]; + /* SSCM_PWCMPH - Password Comparison Register High */ + SSCM_PWCMPH_32B_tag PWCMPH; /* offset: 0x000C size: 32 bit */ + /* SSCM_PWCMPL - Password Comparison Register Low */ + SSCM_PWCMPL_32B_tag PWCMPL; /* offset: 0x0010 size: 32 bit */ + int8_t SSCM_reserved_0014[4]; + /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */ + SSCM_DPMBOOT_32B_tag DPMBOOT; /* offset: 0x0018 size: 32 bit */ + /* SSCM_DPMKEY - Boot Key Register */ + SSCM_DPMKEY_32B_tag DPMKEY; /* offset: 0x001C size: 32 bit */ + /* SSCM_UOPS - User Option Status Register */ + SSCM_UOPS_32B_tag UOPS; /* offset: 0x0020 size: 32 bit */ + /* SSCM_SCTR - SSCM Control Register */ + SSCM_SCTR_32B_tag SCTR; /* offset: 0x0024 size: 32 bit */ + /* SSCM_TF_INFO0 - TestFlash Information Register 0 */ + SSCM_TF_INFO0_32B_tag TF_INFO0; /* offset: 0x0028 size: 32 bit */ + /* SSCM_TF_INFO1 - TestFlash Information Register 1 */ + SSCM_TF_INFO1_32B_tag TF_INFO1; /* offset: 0x002C size: 32 bit */ + /* SSCM_TF_INFO2 - TestFlash Information Register 2 */ + SSCM_TF_INFO2_32B_tag TF_INFO2; /* offset: 0x0030 size: 32 bit */ + /* SSCM_TF_INFO3 - TestFlash Information Register 3 */ + SSCM_TF_INFO3_32B_tag TF_INFO3; /* offset: 0x0034 size: 32 bit */ + } SSCM_tag; + + +#define SSCM (*(volatile SSCM_tag *) 0xC3FD8000UL) + + + +/****************************************************************/ +/* */ +/* Module: ME */ +/* */ +/****************************************************************/ + + typedef union { /* ME_GS - Global Status Register */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_ME + uint32_t S_CURRENT_MODE:4; /* Current device mode status */ +#else + uint32_t S_CURRENTMODE:4; /* deprecated name - please avoid */ +#endif + uint32_t S_MTRANS:1; /* Mode transition status */ + uint32_t:3; + uint32_t S_PDO:1; /* Output power-down status */ + uint32_t:2; + uint32_t S_MVR:1; /* Main voltage regulator status */ + uint32_t:2; +#ifndef USE_FIELD_ALIASES_ME + uint32_t S_FLA:2; /* Flash availability status */ +#else + uint32_t S_CFLA:2; /* deprecated name - please avoid */ +#endif + uint32_t:8; + uint32_t S_PLL1:1; /* Secondary PLL status */ + uint32_t S_PLL0:1; /* System PLL status */ +#ifndef USE_FIELD_ALIASES_ME + uint32_t S_XOSC:1; /* System crystal oscillator status */ +#else + uint32_t S_OSC:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t S_IRCOSC:1; /* System RC oscillator status */ +#else + uint32_t S_RC:1; /* deprecated name - please avoid */ +#endif + uint32_t S_SYSCLK:4; /* System clock switch status */ + } B; + } ME_GS_32B_tag; + + typedef union { /* ME_MCTL - Mode Control Register */ + uint32_t R; + struct { + uint32_t TARGET_MODE:4; /* Target device mode */ + uint32_t:12; + uint32_t KEY:16; /* Control key */ + } B; + } ME_MCTL_32B_tag; + + typedef union { /* ME_MEN - Mode Enable Register */ + uint32_t R; + struct { + uint32_t:21; + uint32_t STOP0:1; /* STOP0 mode enable */ + uint32_t:1; + uint32_t HALT0:1; /* HALT0 mode enable */ + uint32_t RUN3:1; /* RUN3 mode enable */ + uint32_t RUN2:1; /* RUN2 mode enable */ + uint32_t RUN1:1; /* RUN1 mode enable */ + uint32_t RUN0:1; /* RUN0 mode enable */ + uint32_t DRUN:1; /* DRUN mode enable */ + uint32_t SAFE:1; /* SAFE mode enable */ + uint32_t:1; + uint32_t RESET:1; /* RESET mode enable */ + } B; + } ME_MEN_32B_tag; + + typedef union { /* ME_IS - Interrupt Status Register */ + uint32_t R; + struct { + uint32_t:28; +#ifndef USE_FIELD_ALIASES_ME + uint32_t I_ICONF:1; /* Invalid mode config interrupt */ +#else + uint32_t I_CONF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t I_IMODE:1; /* Invalid mode interrupt */ +#else + uint32_t I_MODE:1; /* deprecated name - please avoid */ +#endif + uint32_t I_SAFE:1; /* SAFE mode interrupt */ +#ifndef USE_FIELD_ALIASES_ME + uint32_t I_MTC:1; /* Mode transition complete interrupt */ +#else + uint32_t I_TC:1; /* deprecated name - please avoid */ +#endif + } B; + } ME_IS_32B_tag; + + typedef union { /* ME_IM - Interrupt Mask Register */ + uint32_t R; + struct { + uint32_t:28; +#ifndef USE_FIELD_ALIASES_ME + uint32_t M_ICONF:1; /* Invalid mode config interrupt mask */ +#else + uint32_t M_CONF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t M_IMODE:1; /* Invalid mode interrupt mask */ +#else + uint32_t M_MODE:1; /* deprecated name - please avoid */ +#endif + uint32_t M_SAFE:1; /* SAFE mode interrupt mask */ +#ifndef USE_FIELD_ALIASES_ME + uint32_t M_MTC:1; /* Mode transition complete interrupt mask */ +#else + uint32_t M_TC:1; /* deprecated name - please avoid */ +#endif + } B; + } ME_IM_32B_tag; + + typedef union { /* ME_IMTS - Invalid Mode Transition Status Register */ + uint32_t R; + struct { + uint32_t:27; + uint32_t S_MTI:1; /* Mode Transition Illegal status */ + uint32_t S_MRI:1; /* Mode Request Illegal status */ + uint32_t S_DMA:1; /* Disabled Mode Access status */ + uint32_t S_NMA:1; /* Non-existing Mode Access status */ + uint32_t S_SEA:1; /* Safe Event Active status */ + } B; + } ME_IMTS_32B_tag; + + typedef union { /* ME_DMTS - Debug Mode Transition Status Register */ + uint32_t R; + struct { + uint32_t PREVIOUS_MODE:4; /* Previous Device Mode */ + uint32_t:4; + uint32_t MPH_BUSY:1; /* MC_ME/MC_PCU Handshake Busy Indicator */ + uint32_t:2; + uint32_t PMC_PROG:1; /* MC_PCU Mode Change in Process Indicator */ + uint32_t CORE_DBG:1; /* Processor is in Debug Mode Indicator */ + uint32_t:2; + uint32_t SMR:1; /* SAFE Mode Request */ + uint32_t:1; + uint32_t VREG_CSRC_SC:1; /* Main VREG Clock Source State Change Indicator */ + uint32_t CSRC_CSRC_SC:1; /* Other Clock Source State Change Indicator */ + uint32_t IRCOSC_SC:1; /* IRCOSC State Change Indicator */ + uint32_t SCSRC_SC:1; /* Secondary System Clock Sources State Change Indicator */ + uint32_t SYSCLK_SW:1; /* System Clock Switching pending Status Indicator */ + uint32_t:1; + uint32_t FLASH_SC:1; /* FLASH State Change Indicator */ + uint32_t CDP_PRPH_0_143:1; /* Clock Disable Process Pending Status for Periph. 0-143 */ + uint32_t:4; + uint32_t CDP_PRPH_64_95:1; /* Clock Disable Process Pending Status for Periph. 64-95 */ + uint32_t CDP_PRPH_32_63:1; /* Clock Disable Process Pending Status for Periph. 32-63 */ + uint32_t CDP_PRPH_0_31:1; /* Clock Disable Process Pending Status for Periph. 0-31 */ + } B; + } ME_DMTS_32B_tag; + + typedef union { /* ME_RESET_MC - RESET Mode Configuration Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_RESET_MC_32B_tag; + + typedef union { /* ME_SAFE_MC - Mode Configuration Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_SAFE_MC_32B_tag; + + typedef union { /* ME_DRUN_MC - DRUN Mode Configuration Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_DRUN_MC_32B_tag; + + + /* Register layout for all registers RUN_MC... */ + + typedef union { /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_RUN_MC_32B_tag; + + typedef union { /* ME_HALT0_MC - HALT0 Mode Configuration Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_HALT0_MC_32B_tag; + + typedef union { /* ME_STOP0_MC - STOP0 Mode Configration Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_STOP0_MC_32B_tag; + + typedef union { /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_STANDBY0_MC_32B_tag; + + typedef union { /* ME_PS0 - Peripheral Status Register 0 */ + uint32_t R; + struct { + uint32_t:7; + uint32_t S_FLEXRAY:1; /* FlexRay status */ + uint32_t:6; + uint32_t S_FLEXCAN1:1; /* FlexCAN1 status */ + uint32_t S_FLEXCAN0:1; /* FlexCAN0 status */ + uint32_t:9; + uint32_t S_DSPI2:1; /* DSPI2 status */ + uint32_t S_DSPI1:1; /* DSPI1 status */ + uint32_t S_DSPI0:1; /* DSPI0 status */ + uint32_t:4; + } B; + } ME_PS0_32B_tag; + + typedef union { /* ME_PS1 - Peripheral Status Register 1 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t S_SWG:1; /* SWG status */ + uint32_t:3; + uint32_t S_CRC:1; /* CRC status */ + uint32_t:8; + uint32_t S_LIN_FLEX1:1; /* LinFlex1 status */ + uint32_t S_LIN_FLEX0:1; /* LinFlex0 status */ + uint32_t:5; + uint32_t S_FLEXPWM1:1; /* FlexPWM1 status */ + uint32_t S_FLEXPWM0:1; /* FlexPWM0 status */ + uint32_t S_ETIMER2:1; /* eTimer2 status */ + uint32_t S_ETIMER1:1; /* eTimer1 status */ + uint32_t S_ETIMER0:1; /* eTimer0 status */ + uint32_t:2; + uint32_t S_CTU:1; /* CTU status */ + uint32_t:1; + uint32_t S_ADC1:1; /* ADC1 status */ + uint32_t S_ADC0:1; /* ADC0 status */ + } B; + } ME_PS1_32B_tag; + + typedef union { /* ME_PS2 - Peripheral Status Register 2 */ + uint32_t R; + struct { + uint32_t:3; + uint32_t S_PIT:1; /* PIT status */ + uint32_t:28; + } B; + } ME_PS2_32B_tag; + + + /* Register layout for all registers RUN_PC... */ + + typedef union { /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ + uint32_t R; + struct { + uint32_t:24; + uint32_t RUN3:1; /* Peripheral control during RUN3 */ + uint32_t RUN2:1; /* Peripheral control during RUN2 */ + uint32_t RUN1:1; /* Peripheral control during RUN1 */ + uint32_t RUN0:1; /* Peripheral control during RUN0 */ + uint32_t DRUN:1; /* Peripheral control during DRUN */ + uint32_t SAFE:1; /* Peripheral control during SAFE */ + uint32_t TEST:1; /* Peripheral control during TEST */ + uint32_t RESET:1; /* Peripheral control during RESET */ + } B; + } ME_RUN_PC_32B_tag; + + + /* Register layout for all registers LP_PC... */ + + typedef union { /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ + uint32_t R; + struct { + uint32_t:21; + uint32_t STOP0:1; /* Peripheral control during STOP0 */ + uint32_t:1; + uint32_t HALT0:1; /* Peripheral control during HALT0 */ + uint32_t:8; + } B; + } ME_LP_PC_32B_tag; + + + /* Register layout for all registers PCTL... */ + + typedef union { /* ME_PCTL[0...143] - Peripheral Control Registers */ + uint8_t R; + struct { + uint8_t:1; + uint8_t DBG_F:1; /* Peripheral control in debug mode */ + uint8_t LP_CFG:3; /* Peripheral configuration select for non-RUN modes */ + uint8_t RUN_CFG:3; /* Peripheral configuration select for RUN modes */ + } B; + } ME_PCTL_8B_tag; + + + + + /* Register layout for generated register(s) PS... */ + + typedef union { /* */ + uint32_t R; + } ME_PS_32B_tag; + + + + + + + typedef struct ME_struct_tag { /* start of ME_tag */ + /* ME_GS - Global Status Register */ + ME_GS_32B_tag GS; /* offset: 0x0000 size: 32 bit */ + /* ME_MCTL - Mode Control Register */ + ME_MCTL_32B_tag MCTL; /* offset: 0x0004 size: 32 bit */ + union { + ME_MEN_32B_tag MER; /* deprecated - please avoid */ + + /* ME_MEN - Mode Enable Register */ + ME_MEN_32B_tag MEN; /* offset: 0x0008 size: 32 bit */ + + }; + /* ME_IS - Interrupt Status Register */ + ME_IS_32B_tag IS; /* offset: 0x000C size: 32 bit */ + /* ME_IM - Interrupt Mask Register */ + ME_IM_32B_tag IM; /* offset: 0x0010 size: 32 bit */ + /* ME_IMTS - Invalid Mode Transition Status Register */ + ME_IMTS_32B_tag IMTS; /* offset: 0x0014 size: 32 bit */ + /* ME_DMTS - Debug Mode Transition Status Register */ + ME_DMTS_32B_tag DMTS; /* offset: 0x0018 size: 32 bit */ + int8_t ME_reserved_001C_C[4]; + union { + /* ME_RESET_MC - RESET Mode Configuration Register */ + ME_RESET_MC_32B_tag RESET_MC; /* offset: 0x0020 size: 32 bit */ + + ME_RESET_MC_32B_tag RESET; /* deprecated - please avoid */ + + }; + int8_t ME_reserved_0024_C[4]; + union { + /* ME_SAFE_MC - Mode Configuration Register */ + ME_SAFE_MC_32B_tag SAFE_MC; /* offset: 0x0028 size: 32 bit */ + + ME_SAFE_MC_32B_tag SAFE; /* deprecated - please avoid */ + + }; + union { + /* ME_DRUN_MC - DRUN Mode Configuration Register */ + ME_DRUN_MC_32B_tag DRUN_MC; /* offset: 0x002C size: 32 bit */ + + ME_DRUN_MC_32B_tag DRUN; /* deprecated - please avoid */ + + }; + union { + /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ + ME_RUN_MC_32B_tag RUN_MC[4]; /* offset: 0x0030 (0x0004 x 4) */ + + ME_RUN_MC_32B_tag RUN[4]; /* offset: 0x0030 (0x0004 x 4) */ /* deprecated - please avoid */ + + struct { + /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ + ME_RUN_MC_32B_tag RUN0_MC; /* offset: 0x0030 size: 32 bit */ + ME_RUN_MC_32B_tag RUN1_MC; /* offset: 0x0034 size: 32 bit */ + ME_RUN_MC_32B_tag RUN2_MC; /* offset: 0x0038 size: 32 bit */ + ME_RUN_MC_32B_tag RUN3_MC; /* offset: 0x003C size: 32 bit */ + }; + + }; + union { + /* ME_HALT0_MC - HALT0 Mode Configuration Register */ + ME_HALT0_MC_32B_tag HALT0_MC; /* offset: 0x0040 size: 32 bit */ + + ME_HALT0_MC_32B_tag HALT0; /* deprecated - please avoid */ + + }; + int8_t ME_reserved_0044_C[4]; + union { + /* ME_STOP0_MC - STOP0 Mode Configration Register */ + ME_STOP0_MC_32B_tag STOP0_MC; /* offset: 0x0048 size: 32 bit */ + + ME_STOP0_MC_32B_tag STOP0; /* deprecated - please avoid */ + + }; + int8_t ME_reserved_004C_C[8]; + union { + /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */ + ME_STANDBY0_MC_32B_tag STANDBY0_MC; /* offset: 0x0054 size: 32 bit */ + + ME_STANDBY0_MC_32B_tag STANDBY0; /* deprecated - please avoid */ + + }; + int8_t ME_reserved_0058_C[8]; + union { + ME_PS_32B_tag PS[3]; /* offset: 0x0060 (0x0004 x 3) */ + + struct { + /* ME_PS0 - Peripheral Status Register 0 */ + ME_PS0_32B_tag PS0; /* offset: 0x0060 size: 32 bit */ + /* ME_PS1 - Peripheral Status Register 1 */ + ME_PS1_32B_tag PS1; /* offset: 0x0064 size: 32 bit */ + /* ME_PS2 - Peripheral Status Register 2 */ + ME_PS2_32B_tag PS2; /* offset: 0x0068 size: 32 bit */ + }; + + }; + int8_t ME_reserved_006C_C[20]; + union { + ME_RUN_PC_32B_tag RUNPC[8]; /* offset: 0x0080 (0x0004 x 8) */ + + /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ + ME_RUN_PC_32B_tag RUN_PC[8]; /* offset: 0x0080 (0x0004 x 8) */ + + struct { + /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ + ME_RUN_PC_32B_tag RUN_PC0; /* offset: 0x0080 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC1; /* offset: 0x0084 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC2; /* offset: 0x0088 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC3; /* offset: 0x008C size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC4; /* offset: 0x0090 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC5; /* offset: 0x0094 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC6; /* offset: 0x0098 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC7; /* offset: 0x009C size: 32 bit */ + }; + + }; + union { + ME_LP_PC_32B_tag LPPC[8]; /* offset: 0x00A0 (0x0004 x 8) */ + + /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ + ME_LP_PC_32B_tag LP_PC[8]; /* offset: 0x00A0 (0x0004 x 8) */ + + struct { + /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ + ME_LP_PC_32B_tag LP_PC0; /* offset: 0x00A0 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC1; /* offset: 0x00A4 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC2; /* offset: 0x00A8 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC3; /* offset: 0x00AC size: 32 bit */ + ME_LP_PC_32B_tag LP_PC4; /* offset: 0x00B0 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC5; /* offset: 0x00B4 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC6; /* offset: 0x00B8 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC7; /* offset: 0x00BC size: 32 bit */ + }; + + }; + union { + /* ME_PCTL[0...143] - Peripheral Control Registers */ + ME_PCTL_8B_tag PCTL[144]; /* offset: 0x00C0 (0x0001 x 144) */ + + struct { + /* ME_PCTL[0...143] - Peripheral Control Registers */ + ME_PCTL_8B_tag PCTL0; /* offset: 0x00C0 size: 8 bit */ + ME_PCTL_8B_tag PCTL1; /* offset: 0x00C1 size: 8 bit */ + ME_PCTL_8B_tag PCTL2; /* offset: 0x00C2 size: 8 bit */ + ME_PCTL_8B_tag PCTL3; /* offset: 0x00C3 size: 8 bit */ + ME_PCTL_8B_tag PCTL4; /* offset: 0x00C4 size: 8 bit */ + ME_PCTL_8B_tag PCTL5; /* offset: 0x00C5 size: 8 bit */ + ME_PCTL_8B_tag PCTL6; /* offset: 0x00C6 size: 8 bit */ + ME_PCTL_8B_tag PCTL7; /* offset: 0x00C7 size: 8 bit */ + ME_PCTL_8B_tag PCTL8; /* offset: 0x00C8 size: 8 bit */ + ME_PCTL_8B_tag PCTL9; /* offset: 0x00C9 size: 8 bit */ + ME_PCTL_8B_tag PCTL10; /* offset: 0x00CA size: 8 bit */ + ME_PCTL_8B_tag PCTL11; /* offset: 0x00CB size: 8 bit */ + ME_PCTL_8B_tag PCTL12; /* offset: 0x00CC size: 8 bit */ + ME_PCTL_8B_tag PCTL13; /* offset: 0x00CD size: 8 bit */ + ME_PCTL_8B_tag PCTL14; /* offset: 0x00CE size: 8 bit */ + ME_PCTL_8B_tag PCTL15; /* offset: 0x00CF size: 8 bit */ + ME_PCTL_8B_tag PCTL16; /* offset: 0x00D0 size: 8 bit */ + ME_PCTL_8B_tag PCTL17; /* offset: 0x00D1 size: 8 bit */ + ME_PCTL_8B_tag PCTL18; /* offset: 0x00D2 size: 8 bit */ + ME_PCTL_8B_tag PCTL19; /* offset: 0x00D3 size: 8 bit */ + ME_PCTL_8B_tag PCTL20; /* offset: 0x00D4 size: 8 bit */ + ME_PCTL_8B_tag PCTL21; /* offset: 0x00D5 size: 8 bit */ + ME_PCTL_8B_tag PCTL22; /* offset: 0x00D6 size: 8 bit */ + ME_PCTL_8B_tag PCTL23; /* offset: 0x00D7 size: 8 bit */ + ME_PCTL_8B_tag PCTL24; /* offset: 0x00D8 size: 8 bit */ + ME_PCTL_8B_tag PCTL25; /* offset: 0x00D9 size: 8 bit */ + ME_PCTL_8B_tag PCTL26; /* offset: 0x00DA size: 8 bit */ + ME_PCTL_8B_tag PCTL27; /* offset: 0x00DB size: 8 bit */ + ME_PCTL_8B_tag PCTL28; /* offset: 0x00DC size: 8 bit */ + ME_PCTL_8B_tag PCTL29; /* offset: 0x00DD size: 8 bit */ + ME_PCTL_8B_tag PCTL30; /* offset: 0x00DE size: 8 bit */ + ME_PCTL_8B_tag PCTL31; /* offset: 0x00DF size: 8 bit */ + ME_PCTL_8B_tag PCTL32; /* offset: 0x00E0 size: 8 bit */ + ME_PCTL_8B_tag PCTL33; /* offset: 0x00E1 size: 8 bit */ + ME_PCTL_8B_tag PCTL34; /* offset: 0x00E2 size: 8 bit */ + ME_PCTL_8B_tag PCTL35; /* offset: 0x00E3 size: 8 bit */ + ME_PCTL_8B_tag PCTL36; /* offset: 0x00E4 size: 8 bit */ + ME_PCTL_8B_tag PCTL37; /* offset: 0x00E5 size: 8 bit */ + ME_PCTL_8B_tag PCTL38; /* offset: 0x00E6 size: 8 bit */ + ME_PCTL_8B_tag PCTL39; /* offset: 0x00E7 size: 8 bit */ + ME_PCTL_8B_tag PCTL40; /* offset: 0x00E8 size: 8 bit */ + ME_PCTL_8B_tag PCTL41; /* offset: 0x00E9 size: 8 bit */ + ME_PCTL_8B_tag PCTL42; /* offset: 0x00EA size: 8 bit */ + ME_PCTL_8B_tag PCTL43; /* offset: 0x00EB size: 8 bit */ + ME_PCTL_8B_tag PCTL44; /* offset: 0x00EC size: 8 bit */ + ME_PCTL_8B_tag PCTL45; /* offset: 0x00ED size: 8 bit */ + ME_PCTL_8B_tag PCTL46; /* offset: 0x00EE size: 8 bit */ + ME_PCTL_8B_tag PCTL47; /* offset: 0x00EF size: 8 bit */ + ME_PCTL_8B_tag PCTL48; /* offset: 0x00F0 size: 8 bit */ + ME_PCTL_8B_tag PCTL49; /* offset: 0x00F1 size: 8 bit */ + ME_PCTL_8B_tag PCTL50; /* offset: 0x00F2 size: 8 bit */ + ME_PCTL_8B_tag PCTL51; /* offset: 0x00F3 size: 8 bit */ + ME_PCTL_8B_tag PCTL52; /* offset: 0x00F4 size: 8 bit */ + ME_PCTL_8B_tag PCTL53; /* offset: 0x00F5 size: 8 bit */ + ME_PCTL_8B_tag PCTL54; /* offset: 0x00F6 size: 8 bit */ + ME_PCTL_8B_tag PCTL55; /* offset: 0x00F7 size: 8 bit */ + ME_PCTL_8B_tag PCTL56; /* offset: 0x00F8 size: 8 bit */ + ME_PCTL_8B_tag PCTL57; /* offset: 0x00F9 size: 8 bit */ + ME_PCTL_8B_tag PCTL58; /* offset: 0x00FA size: 8 bit */ + ME_PCTL_8B_tag PCTL59; /* offset: 0x00FB size: 8 bit */ + ME_PCTL_8B_tag PCTL60; /* offset: 0x00FC size: 8 bit */ + ME_PCTL_8B_tag PCTL61; /* offset: 0x00FD size: 8 bit */ + ME_PCTL_8B_tag PCTL62; /* offset: 0x00FE size: 8 bit */ + ME_PCTL_8B_tag PCTL63; /* offset: 0x00FF size: 8 bit */ + ME_PCTL_8B_tag PCTL64; /* offset: 0x0100 size: 8 bit */ + ME_PCTL_8B_tag PCTL65; /* offset: 0x0101 size: 8 bit */ + ME_PCTL_8B_tag PCTL66; /* offset: 0x0102 size: 8 bit */ + ME_PCTL_8B_tag PCTL67; /* offset: 0x0103 size: 8 bit */ + ME_PCTL_8B_tag PCTL68; /* offset: 0x0104 size: 8 bit */ + ME_PCTL_8B_tag PCTL69; /* offset: 0x0105 size: 8 bit */ + ME_PCTL_8B_tag PCTL70; /* offset: 0x0106 size: 8 bit */ + ME_PCTL_8B_tag PCTL71; /* offset: 0x0107 size: 8 bit */ + ME_PCTL_8B_tag PCTL72; /* offset: 0x0108 size: 8 bit */ + ME_PCTL_8B_tag PCTL73; /* offset: 0x0109 size: 8 bit */ + ME_PCTL_8B_tag PCTL74; /* offset: 0x010A size: 8 bit */ + ME_PCTL_8B_tag PCTL75; /* offset: 0x010B size: 8 bit */ + ME_PCTL_8B_tag PCTL76; /* offset: 0x010C size: 8 bit */ + ME_PCTL_8B_tag PCTL77; /* offset: 0x010D size: 8 bit */ + ME_PCTL_8B_tag PCTL78; /* offset: 0x010E size: 8 bit */ + ME_PCTL_8B_tag PCTL79; /* offset: 0x010F size: 8 bit */ + ME_PCTL_8B_tag PCTL80; /* offset: 0x0110 size: 8 bit */ + ME_PCTL_8B_tag PCTL81; /* offset: 0x0111 size: 8 bit */ + ME_PCTL_8B_tag PCTL82; /* offset: 0x0112 size: 8 bit */ + ME_PCTL_8B_tag PCTL83; /* offset: 0x0113 size: 8 bit */ + ME_PCTL_8B_tag PCTL84; /* offset: 0x0114 size: 8 bit */ + ME_PCTL_8B_tag PCTL85; /* offset: 0x0115 size: 8 bit */ + ME_PCTL_8B_tag PCTL86; /* offset: 0x0116 size: 8 bit */ + ME_PCTL_8B_tag PCTL87; /* offset: 0x0117 size: 8 bit */ + ME_PCTL_8B_tag PCTL88; /* offset: 0x0118 size: 8 bit */ + ME_PCTL_8B_tag PCTL89; /* offset: 0x0119 size: 8 bit */ + ME_PCTL_8B_tag PCTL90; /* offset: 0x011A size: 8 bit */ + ME_PCTL_8B_tag PCTL91; /* offset: 0x011B size: 8 bit */ + ME_PCTL_8B_tag PCTL92; /* offset: 0x011C size: 8 bit */ + ME_PCTL_8B_tag PCTL93; /* offset: 0x011D size: 8 bit */ + ME_PCTL_8B_tag PCTL94; /* offset: 0x011E size: 8 bit */ + ME_PCTL_8B_tag PCTL95; /* offset: 0x011F size: 8 bit */ + ME_PCTL_8B_tag PCTL96; /* offset: 0x0120 size: 8 bit */ + ME_PCTL_8B_tag PCTL97; /* offset: 0x0121 size: 8 bit */ + ME_PCTL_8B_tag PCTL98; /* offset: 0x0122 size: 8 bit */ + ME_PCTL_8B_tag PCTL99; /* offset: 0x0123 size: 8 bit */ + ME_PCTL_8B_tag PCTL100; /* offset: 0x0124 size: 8 bit */ + ME_PCTL_8B_tag PCTL101; /* offset: 0x0125 size: 8 bit */ + ME_PCTL_8B_tag PCTL102; /* offset: 0x0126 size: 8 bit */ + ME_PCTL_8B_tag PCTL103; /* offset: 0x0127 size: 8 bit */ + ME_PCTL_8B_tag PCTL104; /* offset: 0x0128 size: 8 bit */ + ME_PCTL_8B_tag PCTL105; /* offset: 0x0129 size: 8 bit */ + ME_PCTL_8B_tag PCTL106; /* offset: 0x012A size: 8 bit */ + ME_PCTL_8B_tag PCTL107; /* offset: 0x012B size: 8 bit */ + ME_PCTL_8B_tag PCTL108; /* offset: 0x012C size: 8 bit */ + ME_PCTL_8B_tag PCTL109; /* offset: 0x012D size: 8 bit */ + ME_PCTL_8B_tag PCTL110; /* offset: 0x012E size: 8 bit */ + ME_PCTL_8B_tag PCTL111; /* offset: 0x012F size: 8 bit */ + ME_PCTL_8B_tag PCTL112; /* offset: 0x0130 size: 8 bit */ + ME_PCTL_8B_tag PCTL113; /* offset: 0x0131 size: 8 bit */ + ME_PCTL_8B_tag PCTL114; /* offset: 0x0132 size: 8 bit */ + ME_PCTL_8B_tag PCTL115; /* offset: 0x0133 size: 8 bit */ + ME_PCTL_8B_tag PCTL116; /* offset: 0x0134 size: 8 bit */ + ME_PCTL_8B_tag PCTL117; /* offset: 0x0135 size: 8 bit */ + ME_PCTL_8B_tag PCTL118; /* offset: 0x0136 size: 8 bit */ + ME_PCTL_8B_tag PCTL119; /* offset: 0x0137 size: 8 bit */ + ME_PCTL_8B_tag PCTL120; /* offset: 0x0138 size: 8 bit */ + ME_PCTL_8B_tag PCTL121; /* offset: 0x0139 size: 8 bit */ + ME_PCTL_8B_tag PCTL122; /* offset: 0x013A size: 8 bit */ + ME_PCTL_8B_tag PCTL123; /* offset: 0x013B size: 8 bit */ + ME_PCTL_8B_tag PCTL124; /* offset: 0x013C size: 8 bit */ + ME_PCTL_8B_tag PCTL125; /* offset: 0x013D size: 8 bit */ + ME_PCTL_8B_tag PCTL126; /* offset: 0x013E size: 8 bit */ + ME_PCTL_8B_tag PCTL127; /* offset: 0x013F size: 8 bit */ + ME_PCTL_8B_tag PCTL128; /* offset: 0x0140 size: 8 bit */ + ME_PCTL_8B_tag PCTL129; /* offset: 0x0141 size: 8 bit */ + ME_PCTL_8B_tag PCTL130; /* offset: 0x0142 size: 8 bit */ + ME_PCTL_8B_tag PCTL131; /* offset: 0x0143 size: 8 bit */ + ME_PCTL_8B_tag PCTL132; /* offset: 0x0144 size: 8 bit */ + ME_PCTL_8B_tag PCTL133; /* offset: 0x0145 size: 8 bit */ + ME_PCTL_8B_tag PCTL134; /* offset: 0x0146 size: 8 bit */ + ME_PCTL_8B_tag PCTL135; /* offset: 0x0147 size: 8 bit */ + ME_PCTL_8B_tag PCTL136; /* offset: 0x0148 size: 8 bit */ + ME_PCTL_8B_tag PCTL137; /* offset: 0x0149 size: 8 bit */ + ME_PCTL_8B_tag PCTL138; /* offset: 0x014A size: 8 bit */ + ME_PCTL_8B_tag PCTL139; /* offset: 0x014B size: 8 bit */ + ME_PCTL_8B_tag PCTL140; /* offset: 0x014C size: 8 bit */ + ME_PCTL_8B_tag PCTL141; /* offset: 0x014D size: 8 bit */ + ME_PCTL_8B_tag PCTL142; /* offset: 0x014E size: 8 bit */ + ME_PCTL_8B_tag PCTL143; /* offset: 0x014F size: 8 bit */ + }; + + }; + } ME_tag; + + +#define ME (*(volatile ME_tag *) 0xC3FDC000UL) + + + +/****************************************************************/ +/* */ +/* Module: OSC */ +/* */ +/****************************************************************/ + + typedef union { /* OSC_CTL - Control Register */ + uint32_t R; + struct { + uint32_t OSCBYP:1; /* High Frequency Oscillator Bypass */ + uint32_t:7; + uint32_t EOCV:8; /* End of Count Value */ + uint32_t M_OSC:1; /* High Frequency Oscillator Clock Interrupt Mask */ + uint32_t:2; + uint32_t OSCDIV:5; /* High Frequency Oscillator Division Factor */ + uint32_t I_OSC:1; /* High Frequency Oscillator Clock Interrupt */ + uint32_t:5; + uint32_t S_OSC:1; + uint32_t OSCON:1; } B; + } OSC_CTL_32B_tag; + + + + typedef struct OSC_struct_tag { /* start of OSC_tag */ + /* OSC_CTL - Control Register */ + OSC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */ + } OSC_tag; + + +#define OSC (*(volatile OSC_tag *) 0xC3FE0000UL) + + + +/****************************************************************/ +/* */ +/* Module: RC */ +/* */ +/****************************************************************/ + + typedef union { /* RC_CTL - Control Register */ + uint32_t R; + struct { + uint32_t:10; + uint32_t RCTRIM:6; /* Main RC Trimming Bits */ + uint32_t:3; + uint32_t RCDIV:5; /* Main RC Clock Division Factor */ + uint32_t:2; + uint32_t S_RC_STDBY:1; /* MRC Oscillator Powerdown Status */ + uint32_t:5; + } B; + } RC_CTL_32B_tag; + + + + typedef struct RC_struct_tag { /* start of RC_tag */ + /* RC_CTL - Control Register */ + RC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */ + } RC_tag; + + +#define RC (*(volatile RC_tag *) 0xC3FE0060UL) + + + +/****************************************************************/ +/* */ +/* Module: PLLD */ +/* */ +/****************************************************************/ + + typedef union { /* PLLD_CR - Control Register */ + uint32_t R; + struct { + uint32_t:2; + uint32_t IDF:4; /* PLL Input Division Factor */ + uint32_t ODF:2; /* PLL Output Division Factor */ + uint32_t:1; + uint32_t NDIV:7; /* PLL Loop Division Factor */ + uint32_t:7; + uint32_t EN_PLL_SW:1; /* Enable Progressive Clock Switching */ + uint32_t MODE:1; /* Activate 1:1 Mode */ + uint32_t UNLOCK_ONCE:1; /* PLL Loss of Lock */ + uint32_t M_LOCK:1; /* Mask for the i_lock Output Interrupt */ + uint32_t I_LOCK:1; /* PLL Lock Signal Toggle Indicator */ + uint32_t S_LOCK:1; /* PLL has Aquired Lock */ + uint32_t PLL_FAIL_MASK:1; /* PLL Fail Mask */ + uint32_t PLL_FAIL_FLAG:1; /* PLL Fail Flag */ + uint32_t PLL_ON:1; /* PLL ON Bit */ + } B; + } PLLD_CR_32B_tag; + + typedef union { /* PLLD_MR - PLLD Modulation Register */ + uint32_t R; + struct { + uint32_t STRB_BYPASS:1; /* Strobe Bypass */ + uint32_t:1; + uint32_t SPRD_SEL:1; /* Spread Type Selection */ + uint32_t MOD_PERIOD:13; /* Modulation Period */ +#ifndef USE_FIELD_ALIASES_PLLD + uint32_t SSCG_EN:1; /* Spread Spectrum Clock Generation Enable */ +#else + uint32_t FM_EN:1; /* deprecated name - please avoid */ +#endif + uint32_t INC_STEP:15; /* Increment Step */ + } B; + } PLLD_MR_32B_tag; + + + + typedef struct PLLD_struct_tag { /* start of PLLD_tag */ + /* PLLD_CR - Control Register */ + PLLD_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ + /* PLLD_MR - PLLD Modulation Register */ + PLLD_MR_32B_tag MR; /* offset: 0x0004 size: 32 bit */ + + uint32_t plld_reserved[6]; + } PLLD_tag; + + +#define PLLD0 (*(volatile PLLD_tag *) 0xC3FE00A0UL) +#define PLLD1 (*(volatile PLLD_tag *) 0xC3FE00C0UL) + + + +/****************************************************************/ +/* */ +/* Module: CMU */ +/* */ +/****************************************************************/ + + typedef union { /* CMU_CSR - Control Status Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t SFM:1; /* Start Frequency Measure */ + uint32_t:13; +#ifndef USE_FIELD_ALIASES_RGM + uint32_t CKSEL1:2; /* RC Oscillator(s) Selection Bit */ +#else + uint32_t CLKSEL1:2; /* deprecated name - please avoid */ +#endif + uint32_t:5; + uint32_t RCDIV:2; /* RCfast Clock Division Factor */ + uint32_t CME_A:1; /* PLL_A Clock Monitor Enable */ + } B; + } CMU_CSR_32B_tag; + + typedef union { /* CMU_FDR - Frequency Display Register */ + uint32_t R; + struct { + uint32_t:12; + uint32_t FD:20; /* Measured Frequency Bits */ + } B; + } CMU_FDR_32B_tag; + + typedef union { /* CMU_HFREFR_A - High Frequency Reference Register */ + uint32_t R; + struct { + uint32_t:20; + uint32_t HFREF_A:12; /* High Frequency Reference Value */ + } B; + } CMU_HFREFR_A_32B_tag; + + typedef union { /* CMU_LFREFR_A - Low Frequency Reference Register */ + uint32_t R; + struct { + uint32_t:20; + uint32_t LFREF_A:12; /* Low Frequency Reference Value */ + } B; + } CMU_LFREFR_A_32B_tag; + + typedef union { /* CMU_ISR - Interrupt Status Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t FLCI_A:1; /* PLL_A Clock Frequency less than Reference Clock Interrupt */ +#ifndef USE_FIELD_ALIASES_RGM + uint32_t FHH_AI:1; /* PLL_A Clock Frequency higher than high Reference Interrupt */ +#else + uint32_t FHHI_A:1; /* deprecated name - please avoid */ +#endif + uint32_t FLLI_A:1; /* PLL_A Clock Frequency less than low Reference Interrupt */ + uint32_t OLRI:1; /* Oscillator Frequency less than RC Frequency Interrupt */ + } B; + } CMU_ISR_32B_tag; + + typedef union { /* CMU_IMR - Interrupt Mask Register */ + uint32_t R; + } CMU_IMR_32B_tag; + + typedef union { /* CMU_MDR - Measurement Duration Register */ + uint32_t R; + struct { + uint32_t:12; + uint32_t MD:20; /* Measurment Duration Bits */ + } B; + } CMU_MDR_32B_tag; + + + + typedef struct CMU_struct_tag { /* start of CMU_tag */ + /* CMU_CSR - Control Status Register */ + CMU_CSR_32B_tag CSR; /* offset: 0x0000 size: 32 bit */ + /* CMU_FDR - Frequency Display Register */ + CMU_FDR_32B_tag FDR; /* offset: 0x0004 size: 32 bit */ + /* CMU_HFREFR_A - High Frequency Reference Register */ + CMU_HFREFR_A_32B_tag HFREFR_A; /* offset: 0x0008 size: 32 bit */ + /* CMU_LFREFR_A - Low Frequency Reference Register */ + CMU_LFREFR_A_32B_tag LFREFR_A; /* offset: 0x000C size: 32 bit */ + /* CMU_ISR - Interrupt Status Register */ + CMU_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */ + /* CMU_IMR - Interrupt Mask Register */ + CMU_IMR_32B_tag IMR; /* offset: 0x0014 size: 32 bit */ + /* CMU_MDR - Measurement Duration Register */ + CMU_MDR_32B_tag MDR; /* offset: 0x0018 size: 32 bit */ + } CMU_tag; + + +#define CMU0 (*(volatile CMU_tag *) 0xC3FE0100UL) +#define CMU1 (*(volatile CMU_tag *) 0xC3FE0120UL) +#define CMU2 (*(volatile CMU_tag *) 0xC3FE0140UL) + + + +/****************************************************************/ +/* */ +/* Module: CGM */ +/* */ +/****************************************************************/ + + typedef union { /* Output Clock Enable Register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + struct { + uint32_t:31; + uint32_t EN:1; /* Clock Enable Bit */ + } B; + } CGM_OC_EN_32B_tag; + + typedef union { /* Output Clock Division Select Register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + struct { + uint32_t:2; + uint32_t SELDIV:2; /* Output Clock Division Select */ + uint32_t SELCTL:4; /* Output Clock Source Selection Control */ + uint32_t:24; + } B; + } CGM_OCDS_SC_32B_tag; + + typedef union { /* System Clock Select Status Register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + struct { + uint32_t:4; + uint32_t SELSTAT:4; /* System Clock Source Selection Status */ + uint32_t:24; + } B; + } CGM_SC_SS_32B_tag; + + typedef union { /* System Clock Divider Configuration Register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + struct { + uint32_t DE0:1; /* Divider 0 Enable */ + uint32_t:3; + uint32_t DIV0:4; /* Divider 0 Value */ + uint32_t:24; + } B; + } CGM_SC_DC0_3_32B_tag; + + + /* Register layout for all registers SC_DC... */ + + typedef union { /* System Clock Divider Configuration Register */ + uint8_t R; + struct { + uint8_t DE:1; /* Divider Enable */ + uint8_t:3; + uint8_t DIV:4; /* Divider Division Value */ + } B; + } CGM_SC_DC_8B_tag; + + + /* Register layout for all registers AC_SC... */ + + typedef union { /* Auxiliary Clock Select Control Registers */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + struct { + uint32_t:4; + uint32_t SELCTL:4; /* Auxliary Clock Source Selection Control */ + uint32_t:24; + } B; + } CGM_AC_SC_32B_tag; + + + /* Register layout for all registers AC_DC0_3... */ + + typedef union { /* Auxiliary Clock Divider Configuration Registers */ + uint32_t R; + struct { + uint32_t DE0:1; /* Divider 0 Enable */ + uint32_t:3; + uint32_t DIV0:4; /* Divider 0 Value */ + uint32_t DE1:1; /* Divider 1 Enable */ + uint32_t:3; + uint32_t DIV1:4; /* Divider 1 Value */ + uint32_t:16; + } B; + } CGM_AC_DC0_3_32B_tag; + + + typedef struct CGM_AUXCLK_struct_tag { + + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC_SC; /* relative offset: 0x0000 */ + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC_DC0_3; /* relative offset: 0x0004 */ + + } CGM_AUXCLK_tag; + + + typedef struct CGM_struct_tag { /* start of CGM_tag */ + OSC_CTL_32B_tag OSC_CTL; /* offset: 0x0000 size: 32 bit */ + int8_t CGM_reserved_0004[92]; + RC_CTL_32B_tag RC_CTL; /* offset: 0x0060 size: 32 bit */ + int8_t CGM_reserved_0064[60]; + PLLD_tag FMPLL[2]; /* offset: 0x00A0 (0x0020 x 2) */ + int8_t CGM_reserved_00E0[32]; + CMU_CSR_32B_tag CMU_0_CSR; /* offset: 0x0100 size: 32 bit */ + CMU_FDR_32B_tag CMU_0_FDR; /* offset: 0x0104 size: 32 bit */ + CMU_HFREFR_A_32B_tag CMU_0_HFREFR_A; /* offset: 0x0108 size: 32 bit */ + CMU_LFREFR_A_32B_tag CMU_0_LFREFR_A; /* offset: 0x010C size: 32 bit */ + CMU_ISR_32B_tag CMU_0_ISR; /* offset: 0x0110 size: 32 bit */ + CMU_IMR_32B_tag CMU_0_IMR; /* offset: 0x0114 size: 32 bit */ + CMU_MDR_32B_tag CMU_0_MDR; /* offset: 0x0118 size: 32 bit */ + int8_t CGM_reserved_011C[4]; + CMU_CSR_32B_tag CMU_1_CSR; /* offset: 0x0120 size: 32 bit */ + int8_t CGM_reserved_0124[4]; + CMU_HFREFR_A_32B_tag CMU_1_HFREFR_A; /* offset: 0x0128 size: 32 bit */ + CMU_LFREFR_A_32B_tag CMU_1_LFREFR_A; /* offset: 0x012C size: 32 bit */ + CMU_ISR_32B_tag CMU_1_ISR; /* offset: 0x0130 size: 32 bit */ + int8_t CGM_reserved_0134[572]; + union { + /* Output Clock Enable Register */ + CGM_OC_EN_32B_tag OC_EN; /* offset: 0x0370 size: 32 bit */ + + CGM_OC_EN_32B_tag OCEN; /* deprecated - please avoid */ + + }; + union { + /* Output Clock Division Select Register */ + CGM_OCDS_SC_32B_tag OCDS_SC; /* offset: 0x0374 size: 32 bit */ + + CGM_OCDS_SC_32B_tag OCDSSC; /* deprecated - please avoid */ + + }; + union { + /* Output Clock Division Select Register */ + CGM_SC_SS_32B_tag SC_SS; /* offset: 0x0378 size: 32 bit */ + + CGM_SC_SS_32B_tag SCSS; /* deprecated - please avoid */ + + }; /* System Clock Select Status Register */ + union { + struct { + /* System Clock Divider Configuration Register */ + CGM_SC_DC_8B_tag SC_DC[2]; /* offset: 0x037C (0x0001 x 2) */ + int8_t CGM_reserved_037E_E0[2]; + }; + + struct { + /* System Clock Divider Configuration Register */ + CGM_SC_DC_8B_tag SC_DC0; /* offset: 0x037C size: 8 bit */ + CGM_SC_DC_8B_tag SC_DC1; /* offset: 0x037D size: 8 bit */ + int8_t CGM_reserved_037E_E1[2]; + }; + + /* System Clock Divider Configuration Register */ + union { + CGM_SC_DC0_3_32B_tag SC_DC0_3; /* offset: 0x037C size: 32 bit */ + CGM_SC_DC0_3_32B_tag SCDC; /* deprecated - please avoid */ + }; + }; + union { + /* Register set AUXCLK */ + CGM_AUXCLK_tag AUXCLK[6]; /* offset: 0x0380 (0x0008 x 6) */ + + struct { + union { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC0_SC; /* offset: 0x0380 size: 32 bit */ + + CGM_AC_SC_32B_tag AC0SC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC0_DC0_3; /* offset: 0x0384 size: 32 bit */ + + CGM_AC_DC0_3_32B_tag AC0DC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC1_SC; /* offset: 0x0388 size: 32 bit */ + + CGM_AC_SC_32B_tag AC1SC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC1_DC0_3; /* offset: 0x038C size: 32 bit */ + + CGM_AC_DC0_3_32B_tag AC1DC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC2_SC; /* offset: 0x0390 size: 32 bit */ + + CGM_AC_SC_32B_tag AC2SC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC2_DC0_3; /* offset: 0x0394 size: 32 bit */ + + CGM_AC_DC0_3_32B_tag AC2DC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC3_SC; /* offset: 0x0398 size: 32 bit */ + + CGM_AC_SC_32B_tag AC3SC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC3_DC0_3; /* offset: 0x039C size: 32 bit */ + + CGM_AC_DC0_3_32B_tag AC3DC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC4_SC; /* offset: 0x03A0 size: 32 bit */ + + CGM_AC_SC_32B_tag AC4SC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC4_DC0_3; /* offset: 0x03A4 size: 32 bit */ + + CGM_AC_DC0_3_32B_tag AC4DC; /* deprecated - please avoid */ + }; + union { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC5_SC; /* offset: 0x03A8 size: 32 bit */ + + CGM_AC_SC_32B_tag AC5SC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC5_DC0_3; /* offset: 0x03AC size: 32 bit */ + + CGM_AC_DC0_3_32B_tag AC5DC; /* deprecated - please avoid */ + + }; + }; + + }; + } CGM_tag; + + +#define CGM (*(volatile CGM_tag *) 0xC3FE0000UL) + + + +/****************************************************************/ +/* */ +/* Module: RGM */ +/* */ +/****************************************************************/ + + typedef union { /* Functional Event Status Register */ + uint16_t R; + struct { + uint16_t F_EXR:1; /* Flag for External Reset */ + uint16_t F_FCCU_HARD:1; /* Flag for FCCU hard reaction request */ + uint16_t F_FCCU_SOFT:1; /* Flag for FCCU soft reaction request */ + uint16_t F_ST_DONE:1; /* Flag for self-test completed */ +#ifndef USE_FIELD_ALIASES_RGM + uint16_t F_CMU12_FHL:1; /* Flag for CMU 1/2 clock freq. too high/low */ +#else + uint16_t F_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + uint16_t F_FL_ECC_RCC:1; /* Flag for Flash, ECC, or lock-step error */ + uint16_t F_PLL1:1; /* Flag for PLL1 fail */ + uint16_t F_SWT:1; /* Flag for Software Watchdog Timer */ + uint16_t F_FCCU_SAFE:1; /* Flag for FCCU SAFE mode request */ + uint16_t F_CMU0_FHL:1; /* Flag for CMU 0 clock freq. too high/low */ + uint16_t F_CMU0_OLR:1; /* Flag for oscillator freq. too low */ + uint16_t F_PLL0:1; /* Flag for PLL0 fail */ + uint16_t F_CWD:1; /* Flag for Core Watchdog Reset */ + uint16_t F_SOFT:1; /* Flag for software reset */ + uint16_t F_CORE:1; /* Flag for core reset */ + uint16_t F_JTAG:1; /* Flag for JTAG initiated reset */ + } B; + } RGM_FES_16B_tag; + + typedef union { /* Destructive Event Status Register */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_RGM + uint16_t F_POR:1; /* Flag for Power on Reset */ +#else + uint16_t POR:1; /* deprecated name - please avoid */ +#endif + uint16_t:7; + uint16_t F_COMP:1; /* Flag for comparator error */ + uint16_t F_LVD27_IO:1; /* Flag for 2.7V low-voltage detected (I/O) */ + uint16_t F_LVD27_FLASH:1; /* Flag for 2.7V low-voltage detected (Flash) */ + uint16_t F_LVD27_VREG:1; /* Flag for 2.7V low-voltage detected (VREG) */ + uint16_t:2; + uint16_t F_HVD12:1; /* Flag for 1.2V high-voltage detected */ +#ifndef USE_FIELD_ALIASES_RGM + uint16_t F_LVD12:1; /* Flag for 1.2V low-voltage detected */ +#else + uint16_t F_LVD12_PD0:1; /* deprecated name - please avoid */ +#endif + } B; + } RGM_DES_16B_tag; + + typedef union { /* Functional Event Reset Disable Register */ + uint16_t R; + struct { + uint16_t D_EXR:1; /* Disable External Pad Event Reset */ + uint16_t D_FCCU_HARD:1; /* Disable FCCU hard reaction request */ + uint16_t D_FCCU_SOFT:1; /* Disable FCCU soft reaction request */ + uint16_t D_ST_DONE:1; /* Disable self-test completed */ +#ifndef USE_FIELD_ALIASES_RGM + uint16_t D_CMU12_FHL:1; /* Disable CMU 1/2 clock freq. too high/low */ +#else + uint16_t D_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + uint16_t D_FL_ECC_RCC:1; /* Disable Flash, ECC, or lock-step error */ + uint16_t D_PLL1:1; /* Disable PLL1 fail */ + uint16_t D_SWT:1; /* Disable Software Watchdog Timer */ + uint16_t D_FCCU_SAFE:1; /* Disable FCCU SAFE mode request */ + uint16_t D_CMU0_FHL:1; /* Disable CMU 0 clock freq. too high/low */ + uint16_t D_CMU0_OLR:1; /* Disable oscillator freq. too low */ + uint16_t D_PLL0:1; /* Disable PLL0 fail */ + uint16_t D_CWD:1; /* Disable Core Watchdog Reset */ + uint16_t D_SOFT:1; /* Disable software reset */ + uint16_t D_CORE:1; /* Disable core reset */ + uint16_t D_JTAG:1; /* Disable JTAG initiated reset */ + } B; + } RGM_FERD_16B_tag; + + typedef union { /* Destructive Event Reset Disable Register */ + uint16_t R; + struct { + uint16_t:8; + uint16_t D_COMP:1; /* Disable comparator error */ + uint16_t D_LVD27_IO:1; /* Disable 2.7V low-voltage detected (I/O) */ + uint16_t D_LVD27_FLASH:1; /* Disable 2.7V low-voltage detected (Flash) */ + uint16_t D_LVD27_VREG:1; /* Disable 2.7V low-voltage detected (VREG) */ + uint16_t:2; + uint16_t D_HVD12:1; /* Disable 1.2V high-voltage detected */ +#ifndef USE_FIELD_ALIASES_RGM + uint16_t D_LVD12:1; /* Disable 1.2V low-voltage detected */ +#else + uint16_t D_LVD12_PD0:1; /* deprecated name - please avoid */ +#endif + } B; + } RGM_DERD_16B_tag; + + typedef union { /* Functional Event Alternate Request Register */ + uint16_t R; + struct { + uint16_t:4; +#ifndef USE_FIELD_ALIASES_RGM + uint16_t AR_CMU12_FHL:1; /* Alternate Request for CMU1/2 clock freq. too high/low */ +#else + uint16_t AR_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + uint16_t:1; + uint16_t AR_PLL1:1; /* Alternate Request for PLL1 fail */ + uint16_t:1; + uint16_t AR_FCCU_SAVE:1; /* Alternate Request for FCCU SAFE mode request */ + uint16_t AR_CMU0_FHL:1; /* Alternate Request for CMU0 clock freq. + too high/low */ + uint16_t AR_CMU0_OLR:1; /* Alternate Request for oscillator freq. too low */ + uint16_t AR_PLL0:1; /* Alternate Request for PLL0 fail */ + uint16_t AR_CWD:1; /* Alternate Request for core watchdog reset */ + uint16_t:3; + } B; + } RGM_FEAR_16B_tag; + + typedef union { /* Functional Event Short Sequence Register */ + uint16_t R; + struct { + uint16_t SS_EXR:1; /* Short Sequence for External Reset */ + uint16_t SS_FCCU_HARD:1; /* Short Sequence for FCCU hard reaction request */ + uint16_t SS_FCCU_SOFT:1; /* Short Sequence for FCCU soft reaction request */ + uint16_t SS_ST_DONE:1; /* Short Sequence for self-test completed */ +#ifndef USE_FIELD_ALIASES_RGM + uint16_t SS_CMU12_FHL:1; /* Short Sequence for CMU 1/2 clock freq. too high/low */ +#else + uint16_t SS_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + uint16_t SS_FL_ECC_RCC:1; /* Short Sequence for Flash, ECC, or lock-step error */ + uint16_t SS_PLL1:1; /* Short Sequence for PLL1 fail */ + uint16_t SS_SWT:1; /* Short Sequence for Software Watchdog Timer */ + uint16_t:1; + uint16_t SS_CMU0_FHL:1; /* Short Sequence for CMU 0 clock freq. too high/low */ + uint16_t SS_CMU0_OLR:1; /* Short Sequence for oscillator freq. too low */ + uint16_t SS_PLL0:1; /* Short Sequence for PLL0 fail */ + uint16_t SS_CWD:1; /* Short Sequence for Core Watchdog Reset */ + uint16_t SS_SOFT:1; /* Short Sequence for software reset */ + uint16_t SS_CORE:1; /* Short Sequence for core reset */ + uint16_t SS_JTAG:1; /* Short Sequence for JTAG initiated reset */ + } B; + } RGM_FESS_16B_tag; + + typedef union { /* Functional Bidirectional Reset Enable Register */ + uint16_t R; + struct { + uint16_t BE_EXR:1; /* Bidirectional Reset Enable for External Reset */ + uint16_t BE_FCCU_HARD:1; /* Bidirectional Reset Enable for FCCU hard reaction request */ + uint16_t BE_FCCU_SOFT:1; /* Bidirectional Reset Enable for FCCU soft reaction request */ + uint16_t BE_ST_DONE:1; /* Bidirectional Reset Enable for self-test completed */ +#ifndef USE_FIELD_ALIASES_RGM + uint16_t BE_CMU12_FHL:1; /* Bidirectional Reset Enable for CMU 1/2 clock freq. too high/low */ +#else + uint16_t BE_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + uint16_t BE_FL_ECC_RCC:1; /* Bidirectional Reset Enable for Flash, ECC, or lock-step error */ + uint16_t BE_PLL1:1; /* Bidirectional Reset Enable for PLL1 fail */ + uint16_t BE_SWT:1; /* Bidirectional Reset Enable for Software Watchdog Timer */ + uint16_t:1; + uint16_t BE_CMU0_FHL:1; /* Bidirectional Reset Enable for CMU 0 clock freq. too high/low */ + uint16_t BE_CMU0_OLR:1; /* Bidirectional Reset Enable for oscillator freq. too low */ + uint16_t BE_PLL0:1; /* Bidirectional Reset Enable for PLL0 fail */ + uint16_t BE_CWD:1; /* Bidirectional Reset Enable for Core Watchdog Reset */ + uint16_t BE_SOFT:1; /* Bidirectional Reset Enable for software reset */ + uint16_t BE_CORE:1; /* Bidirectional Reset Enable for core reset */ + uint16_t BE_JTAG:1; /* Bidirectional Reset Enable for JTAG initiated reset */ + } B; + } RGM_FBRE_16B_tag; + + + + typedef struct RGM_struct_tag { /* start of RGM_tag */ + /* Functional Event Status Register */ + RGM_FES_16B_tag FES; /* offset: 0x0000 size: 16 bit */ + /* Destructive Event Status Register */ + RGM_DES_16B_tag DES; /* offset: 0x0002 size: 16 bit */ + /* Functional Event Reset Disable Register */ + RGM_FERD_16B_tag FERD; /* offset: 0x0004 size: 16 bit */ + /* Destructive Event Reset Disable Register */ + RGM_DERD_16B_tag DERD; /* offset: 0x0006 size: 16 bit */ + int8_t RGM_reserved_0008[8]; + /* Functional Event Alternate Request Register */ + RGM_FEAR_16B_tag FEAR; /* offset: 0x0010 size: 16 bit */ + int8_t RGM_reserved_0012[6]; + /* Functional Event Short Sequence Register */ + RGM_FESS_16B_tag FESS; /* offset: 0x0018 size: 16 bit */ + int8_t RGM_reserved_001A[2]; + /* Functional Bidirectional Reset Enable Register */ + RGM_FBRE_16B_tag FBRE; /* offset: 0x001C size: 16 bit */ + } RGM_tag; + + +#define RGM (*(volatile RGM_tag *) 0xC3FE4000UL) + + + +/****************************************************************/ +/* */ +/* Module: PCU */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers PCONF... */ + + typedef union { /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ + uint32_t R; + struct { + uint32_t:18; + uint32_t STBY0:1; /* Power domain control during STBY0 */ + uint32_t:2; + uint32_t STOP0:1; /* Power domain control during STOP0 */ + uint32_t:1; + uint32_t HALT0:1; /* Power domain control during HALT0 */ + uint32_t RUN3:1; /* Power domain control during RUN3 */ + uint32_t RUN2:1; /* Power domain control during RUN2 */ + uint32_t RUN1:1; /* Power domain control during RUN1 */ + uint32_t RUN0:1; /* Power domain control during RUN0 */ + uint32_t DRUN:1; /* Power domain control during DRUN */ + uint32_t SAFE:1; /* Power domain control during SAFE */ + uint32_t TEST:1; /* Power domain control during TEST */ + uint32_t RST:1; /* Power domain control during RST */ + } B; + } PCU_PCONF_32B_tag; + + typedef union { /* PCU_PSTAT - Power Domain Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t PD15:1; /* Power Status for Power Domain 15 */ + uint32_t PD14:1; /* Power Status for Power Domain 14 */ + uint32_t PD13:1; /* Power Status for Power Domain 13 */ + uint32_t PD12:1; /* Power Status for Power Domain 12 */ + uint32_t PD11:1; /* Power Status for Power Domain 11 */ + uint32_t PD10:1; /* Power Status for Power Domain 10 */ + uint32_t PD9:1; /* Power Status for Power Domain 9 */ + uint32_t PD8:1; /* Power Status for Power Domain 8 */ + uint32_t PD7:1; /* Power Status for Power Domain 7 */ + uint32_t PD6:1; /* Power Status for Power Domain 6 */ + uint32_t PD5:1; /* Power Status for Power Domain 5 */ + uint32_t PD4:1; /* Power Status for Power Domain 4 */ + uint32_t PD3:1; /* Power Status for Power Domain 3 */ + uint32_t PD2:1; /* Power Status for Power Domain 2 */ + uint32_t PD1:1; /* Power Status for Power Domain 1 */ + uint32_t PD0:1; /* Power Status for Power Domain 0 */ + } B; + } PCU_PSTAT_32B_tag; + + + + typedef struct PCU_struct_tag { /* start of PCU_tag */ + union { + /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ + PCU_PCONF_32B_tag PCONF[16]; /* offset: 0x0000 (0x0004 x 16) */ + + struct { + /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ + PCU_PCONF_32B_tag PCONF0; /* offset: 0x0000 size: 32 bit */ + PCU_PCONF_32B_tag PCONF1; /* offset: 0x0004 size: 32 bit */ + PCU_PCONF_32B_tag PCONF2; /* offset: 0x0008 size: 32 bit */ + PCU_PCONF_32B_tag PCONF3; /* offset: 0x000C size: 32 bit */ + PCU_PCONF_32B_tag PCONF4; /* offset: 0x0010 size: 32 bit */ + PCU_PCONF_32B_tag PCONF5; /* offset: 0x0014 size: 32 bit */ + PCU_PCONF_32B_tag PCONF6; /* offset: 0x0018 size: 32 bit */ + PCU_PCONF_32B_tag PCONF7; /* offset: 0x001C size: 32 bit */ + PCU_PCONF_32B_tag PCONF8; /* offset: 0x0020 size: 32 bit */ + PCU_PCONF_32B_tag PCONF9; /* offset: 0x0024 size: 32 bit */ + PCU_PCONF_32B_tag PCONF10; /* offset: 0x0028 size: 32 bit */ + PCU_PCONF_32B_tag PCONF11; /* offset: 0x002C size: 32 bit */ + PCU_PCONF_32B_tag PCONF12; /* offset: 0x0030 size: 32 bit */ + PCU_PCONF_32B_tag PCONF13; /* offset: 0x0034 size: 32 bit */ + PCU_PCONF_32B_tag PCONF14; /* offset: 0x0038 size: 32 bit */ + PCU_PCONF_32B_tag PCONF15; /* offset: 0x003C size: 32 bit */ + }; + + }; + /* PCU_PSTAT - Power Domain Status Register */ + PCU_PSTAT_32B_tag PSTAT; /* offset: 0x0040 size: 32 bit */ + } PCU_tag; + + +#define PCU (*(volatile PCU_tag *) 0xC3FE8000UL) + + + +/****************************************************************/ +/* */ +/* Module: PMUCTRL */ +/* */ +/****************************************************************/ + + typedef union { /* PMUCTRL_STATHVD - PMU Status Register HVD */ + uint32_t R; + struct { + uint32_t:11; + uint32_t HVDT_LPB:5; /* High Voltage Detector trimming bits LPB bus */ + uint32_t:6; + uint32_t HVD_M:1; /* High Voltage Detector Main */ + uint32_t HVD_B:1; /* High Voltage Detector Backup */ + uint32_t:4; + uint32_t HVD_LP:4; /* High Voltage Detector trimming bits LP bus */ + } B; + } PMUCTRL_STATHVD_32B_tag; + + typedef union { /* PMUCTRL_STATLVD - PMU Status Register LVD */ + uint32_t R; + struct { + uint32_t:11; + uint32_t LVDT_LPB:5; /* Ligh Voltage Detector trimming bits LPB bus */ + uint32_t:6; + uint32_t LVD_M:1; /* Ligh Voltage Detector Main */ + uint32_t LVD_B:1; /* Ligh Voltage Detector Backup */ + uint32_t:4; + uint32_t LVD_LP:4; /* Ligh Voltage Detector trimming bits LP bus */ + } B; + } PMUCTRL_STATLVD_32B_tag; + + typedef union { /* PMUCTRL_STATIREG - PMU Status Register IREG */ + uint32_t R; + struct { + uint32_t:28; + uint32_t IIREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */ + } B; + } PMUCTRL_STATIREG_32B_tag; + + typedef union { /* PMUCTRL_STATEREG - PMU Status Register EREG */ + uint32_t R; + struct { + uint32_t:28; + uint32_t EEREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */ + } B; + } PMUCTRL_STATEREG_32B_tag; + + typedef union { /* PMUCTRL_STATUS - PMU Status Register STATUS */ + uint32_t R; + struct { + uint32_t EBMM:1; /* External Ballast Management Mode */ + uint32_t AEBD:1; /* Automatic External Ballast Detection */ + uint32_t ENPN:1; /* External NPN status flag */ + uint32_t:13; + uint32_t CTB:2; /* Configuration Trace Bits */ + uint32_t:6; + uint32_t CBS:4; /* Current BIST Status */ + uint32_t CPCS:4; /* Current Pmu Configuration Status */ + } B; + } PMUCTRL_STATUS_32B_tag; + + typedef union { /* PMUCTRL_CTRL - PMU Control Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t SILHT:2; /* Start Idle or LVD or HVD BIST Test */ + } B; + } PMUCTRL_CTRL_32B_tag; + + typedef union { /* PMUCTRL_MASKF - PMU Mask Fault Register */ + uint32_t R; + struct { + uint32_t MF_BB:4; /* Mask Fault Bypass Balast */ + uint32_t:28; + } B; + } PMUCTRL_MASKF_32B_tag; + + typedef union { /* PMUCTRL_FAULT - PMU Fault Monitor Register */ + uint32_t R; + struct { + uint32_t BB_LV:4; /* Bypass Ballast Low Voltage */ + uint32_t:9; + uint32_t FLNCF:1; /* FLash voltage monitor Non Critical Fault */ + uint32_t IONCF:1; /* IO voltage monitor Non Critical Fault */ + uint32_t RENCF:1; /* REgulator voltage monitor Non Critical Fault */ + uint32_t:13; + uint32_t LHCF:1; /* Low High voltage detector Critical Fault */ + uint32_t LNCF:1; /* Low voltage detector Non Critical Fault */ + uint32_t HNCF:1; /* High voltage detector Non Critical Fault */ + } B; + } PMUCTRL_FAULT_32B_tag; + + typedef union { /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */ + uint32_t R; + struct { + uint32_t:10; + uint32_t MFVMP:1; /* Main Flash Voltage Monitor interrupt Pending */ + uint32_t BFVMP:1; /* Backup Flash Voltage Monitor interrupt Pending */ + uint32_t MIVMP:1; /* MAin IO Voltage Monitor interrupt Pending */ + uint32_t BIVMP:1; /* Backup IO Voltage Monitor interrupt Pending */ + uint32_t MRVMP:1; /* Main Regulator Voltage Monitor interrupt Pending */ + uint32_t BRVMP:1; /* Backup Regulator Voltage Monitor interrupt Pending */ + uint32_t:12; + uint32_t MLVDP:1; /* Main Low Voltage Detector error interrupt Pending */ + uint32_t BLVDP:1; /* Backup Low Voltage Detector error interrupt Pending */ + uint32_t MHVDP:1; /* Main High Voltage Detector error interrupt Pending */ + uint32_t BHVDP:1; /* Backup High Voltage Detector error interrupt Pending */ + } B; + } PMUCTRL_IRQS_32B_tag; + + typedef union { /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t:10; + uint32_t MFVME:1; /* Main Flash Voltage Monitor interrupt Enable */ + uint32_t BFVME:1; /* Backup Flash Voltage Monitor interrupt Enable */ + uint32_t MIVME:1; /* MAin IO Voltage Monitor interrupt Enable */ + uint32_t BIVME:1; /* Backup IO Voltage Monitor interrupt Enable */ + uint32_t MRVME:1; /* Main Regulator Voltage Monitor interrupt Enable */ + uint32_t BRVME:1; /* Backup Regulator Voltage Monitor interrupt Enable */ + uint32_t:12; + uint32_t MLVDE:1; /* Main Low Voltage Detector error interrupt Enable */ + uint32_t BLVDE:1; /* Backup Low Voltage Detector error interrupt Enable */ + uint32_t MHVDE:1; /* Main High Voltage Detector error interrupt Enable */ + uint32_t BHVDE:1; /* Backup High Voltage Detector error interrupt Enable */ + } B; + } PMUCTRL_IRQE_32B_tag; + + + + typedef struct PMUCTRL_struct_tag { /* start of PMUCTRL_tag */ + int8_t PMUCTRL_reserved_0000[4]; + /* PMUCTRL_STATHVD - PMU Status Register HVD */ + PMUCTRL_STATHVD_32B_tag STATHVD; /* offset: 0x0004 size: 32 bit */ + /* PMUCTRL_STATLVD - PMU Status Register LVD */ + PMUCTRL_STATLVD_32B_tag STATLVD; /* offset: 0x0008 size: 32 bit */ + int8_t PMUCTRL_reserved_000C[20]; + /* PMUCTRL_STATIREG - PMU Status Register IREG */ + PMUCTRL_STATIREG_32B_tag STATIREG; /* offset: 0x0020 size: 32 bit */ + /* PMUCTRL_STATEREG - PMU Status Register EREG */ + PMUCTRL_STATEREG_32B_tag STATEREG; /* offset: 0x0024 size: 32 bit */ + int8_t PMUCTRL_reserved_0028[24]; + /* PMUCTRL_STATUS - PMU Status Register STATUS */ + PMUCTRL_STATUS_32B_tag STATUS; /* offset: 0x0040 size: 32 bit */ + /* PMUCTRL_CTRL - PMU Control Register */ + PMUCTRL_CTRL_32B_tag CTRL; /* offset: 0x0044 size: 32 bit */ + int8_t PMUCTRL_reserved_0048[40]; + /* PMUCTRL_MASKF - PMU Mask Fault Register */ + PMUCTRL_MASKF_32B_tag MASKF; /* offset: 0x0070 size: 32 bit */ + /* PMUCTRL_FAULT - PMU Fault Monitor Register */ + PMUCTRL_FAULT_32B_tag FAULT; /* offset: 0x0074 size: 32 bit */ + /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */ + PMUCTRL_IRQS_32B_tag IRQS; /* offset: 0x0078 size: 32 bit */ + /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */ + PMUCTRL_IRQE_32B_tag IRQE; /* offset: 0x007C size: 32 bit */ + } PMUCTRL_tag; + + +#define PMUCTRL (*(volatile PMUCTRL_tag *) 0xC3FE8080UL) + + + +/****************************************************************/ +/* */ +/* Module: PIT_RTI */ +/* */ +/****************************************************************/ + + typedef union { /* PIT_RTI_PITMCR - PIT Module Control Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t MDIS:1; /* Module Disable. Disable the module clock */ + uint32_t FRZ:1; /* Freeze. Allows the timers to be stoppedwhen the device enters debug mode */ + } B; + } PIT_RTI_PITMCR_32B_tag; + + + /* Register layout for all registers LDVAL... */ + + typedef union { /* PIT_RTI_LDVAL - Timer Load Value Register */ + uint32_t R; + struct { + uint32_t TSV:32; /* Time Start Value Bits */ + } B; + } PIT_RTI_LDVAL_32B_tag; + + + /* Register layout for all registers CVAL... */ + + typedef union { /* PIT_RTI_CVAL - Current Timer Value Register */ + uint32_t R; + struct { + uint32_t TVL:32; /* Current Timer Value Bits */ + } B; + } PIT_RTI_CVAL_32B_tag; + + + /* Register layout for all registers TCTRL... */ + + typedef union { /* PIT_RTI_TCTRL - Timer Control Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t TIE:1; /* Timer Interrupt Enable Bit */ + uint32_t TEN:1; /* Timer Enable Bit */ + } B; + } PIT_RTI_TCTRL_32B_tag; + + + /* Register layout for all registers TFLG... */ + + typedef union { /* PIT_RTI_TFLG - Timer Flag Register */ + uint32_t R; + struct { + uint32_t:31; + uint32_t TIF:1; /* Timer Interrupt Flag Bit */ + } B; + } PIT_RTI_TFLG_32B_tag; + + + typedef struct PIT_RTI_CHANNEL_struct_tag { + + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL; /* relative offset: 0x0000 */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL; /* relative offset: 0x0004 */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL; /* relative offset: 0x0008 */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG; /* relative offset: 0x000C */ + + } PIT_RTI_CHANNEL_tag; + + + typedef struct PIT_RTI_struct_tag { /* start of PIT_RTI_tag */ + /* PIT_RTI_PITMCR - PIT Module Control Register */ + PIT_RTI_PITMCR_32B_tag PITMCR; /* offset: 0x0000 size: 32 bit */ + int8_t PIT_RTI_reserved_0004_C[252]; + union { + /* Register set CHANNEL */ + PIT_RTI_CHANNEL_tag CHANNEL[4]; /* offset: 0x0100 (0x0010 x 4) */ + + PIT_RTI_CHANNEL_tag CH[4]; /* offset: 0x0100 (0x0010 x 4) */ + + struct { + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL0; /* offset: 0x0100 size: 32 bit */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL0; /* offset: 0x0104 size: 32 bit */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL0; /* offset: 0x0108 size: 32 bit */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG0; /* offset: 0x010C size: 32 bit */ + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL1; /* offset: 0x0110 size: 32 bit */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL1; /* offset: 0x0114 size: 32 bit */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL1; /* offset: 0x0118 size: 32 bit */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG1; /* offset: 0x011C size: 32 bit */ + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL2; /* offset: 0x0120 size: 32 bit */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL2; /* offset: 0x0124 size: 32 bit */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL2; /* offset: 0x0128 size: 32 bit */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG2; /* offset: 0x012C size: 32 bit */ + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL3; /* offset: 0x0130 size: 32 bit */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL3; /* offset: 0x0134 size: 32 bit */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL3; /* offset: 0x0138 size: 32 bit */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG3; /* offset: 0x013C size: 32 bit */ + }; + + }; + } PIT_RTI_tag; + + +#define PIT_RTI (*(volatile PIT_RTI_tag *) 0xC3FF0000UL) + + + +/****************************************************************/ +/* */ +/* Module: ADC */ +/* */ +/****************************************************************/ + + typedef union { /* module configuration register */ + uint32_t R; + struct { + uint32_t OWREN:1; /* Overwrite enable */ + uint32_t WLSIDE:1; /* Write Left/right Alligned */ + uint32_t MODE:1; /* One Shot/Scan Mode Selectiom */ + uint32_t EDGLEV:1; /* edge or level selection for external start trigger */ + uint32_t TRGEN:1; /* external trigger enable */ + uint32_t EDGE:1; /* start trigger egde /level detection */ + uint32_t XSTRTEN:1; /* EXTERNAL START ENABLE */ + uint32_t NSTART:1; /* start normal conversion */ + uint32_t:1; + uint32_t JTRGEN:1; /* Injectin External Trigger Enable */ + uint32_t JEDGE:1; /* start trigger egde /level detection for injected */ + uint32_t JSTART:1; /* injected conversion start */ + uint32_t:2; + uint32_t CTUEN:1; /* CTU enabaled */ + uint32_t:8; + uint32_t ADCLKSEL:1; /* Select which clock for device */ + uint32_t ABORTCHAIN:1; /* abort chain conversion */ + uint32_t ABORT:1; /* abort current conversion */ +#ifndef USE_FIELD_ALIASES_ADC + uint32_t ACKO:1; /* Auto Clock Off Enable */ +#else + uint32_t ACK0:1; /* deprecated name - please avoid */ +#endif + uint32_t OFFREFRESH:1; /* offset phase selection */ + uint32_t OFFCANC:1; /* offset phase cancellation selection */ + uint32_t:2; + uint32_t PWDN:1; /* Power Down Enable */ + } B; + } ADC_MCR_32B_tag; + + typedef union { /* module status register */ + uint32_t R; + struct { + uint32_t:7; + uint32_t NSTART:1; /* normal conversion status */ + uint32_t JABORT:1; /* Injection chain abort status */ + uint32_t:2; + uint32_t JSTART:1; /* Injection Start status */ + uint32_t:3; + uint32_t CTUSTART:1; /* ctu start status */ + uint32_t CHADDR:7; /* which address conv is goin on */ + uint32_t:3; +#ifndef USE_FIELD_ALIASES_ADC + uint32_t ACKO:1; /* Auto Clock Off Enable status */ +#else + uint32_t ACK0:1; /* deprecated name - please avoid */ +#endif + uint32_t OFFREFRESH:1; /* offset refresh status */ + uint32_t OFFCANC:1; /* offset phase cancellation status */ + uint32_t ADCSTATUS:3; /* status of ADC FSM */ + } B; + } ADC_MSR_32B_tag; + + typedef union { /* Interrupt status register */ + uint32_t R; + struct { + uint32_t:25; + uint32_t OFFCANCOVR:1; /* Offset cancellation phase over */ + uint32_t EOFFSET:1; /* error in offset refresh */ + uint32_t EOCTU:1; /* end of CTU channel conversion */ + uint32_t JEOC:1; /* end of injected channel conversion */ + uint32_t JECH:1; /* end ofinjected chain conversion */ + uint32_t EOC:1; /* end of channel conversion */ + uint32_t ECH:1; /* end of chain conversion */ + } B; + } ADC_ISR_32B_tag; + + typedef union { /* CHANNEL PENDING REGISTER 0 */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH31:1; /* Channel 31 conversion over */ +#else + uint32_t EOC31:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH30:1; /* Channel 30 conversion over */ +#else + uint32_t EOC30:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH29:1; /* Channel 29 conversion over */ +#else + uint32_t EOC29:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH28:1; /* Channel 28 conversion over */ +#else + uint32_t EOC28:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH27:1; /* Channel 27 conversion over */ +#else + uint32_t EOC27:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH26:1; /* Channel 26 conversion over */ +#else + uint32_t EOC26:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH25:1; /* Channel 25 conversion over */ +#else + uint32_t EOC25:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH24:1; /* Channel 24 conversion over */ +#else + uint32_t EOC24:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH23:1; /* Channel 23 conversion over */ +#else + uint32_t EOC23:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH22:1; /* Channel 22 conversion over */ +#else + uint32_t EOC22:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH21:1; /* Channel 21 conversion over */ +#else + uint32_t EOC21:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH20:1; /* Channel 20 conversion over */ +#else + uint32_t EOC20:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH19:1; /* Channel 19 conversion over */ +#else + uint32_t EOC19:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH18:1; /* Channel 18 conversion over */ +#else + uint32_t EOC18:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH17:1; /* Channel 17 conversion over */ +#else + uint32_t EOC17:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH16:1; /* Channel 16 conversion over */ +#else + uint32_t EOC16:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH15:1; /* Channel 15 conversion over */ +#else + uint32_t EOC15:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH14:1; /* Channel 14 conversion over */ +#else + uint32_t EOC14:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH13:1; /* Channel 13 conversion over */ +#else + uint32_t EOC13:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH12:1; /* Channel 12 conversion over */ +#else + uint32_t EOC12:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH11:1; /* Channel 11 conversion over */ +#else + uint32_t EOC11:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH10:1; /* Channel 10 conversion over */ +#else + uint32_t EOC10:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH9:1; /* Channel 9 conversion over */ +#else + uint32_t EOC9:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH8:1; /* Channel 8 conversion over */ +#else + uint32_t EOC8:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH7:1; /* Channel 7 conversion over */ +#else + uint32_t EOC7:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH6:1; /* Channel 6 conversion over */ +#else + uint32_t EOC6:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH5:1; /* Channel 5 conversion over */ +#else + uint32_t EOC5:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH4:1; /* Channel 4 conversion over */ +#else + uint32_t EOC4:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH3:1; /* Channel 3 conversion over */ +#else + uint32_t EOC3:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH2:1; /* Channel 2 conversion over */ +#else + uint32_t EOC2:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH1:1; /* Channel 1 conversion over */ +#else + uint32_t EOC1:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH0:1; /* Channel 0 conversion over */ +#else + uint32_t EOC0:1; /* deprecated name - please avoid */ +#endif + } B; + } ADC_CEOCFR0_32B_tag; + + typedef union { /* CHANNEL PENDING REGISTER 1 */ + uint32_t R; + struct { + uint32_t EOC_CH63:1; /* Channel 63 conversion over */ + uint32_t EOC_CH62:1; /* Channel 62 conversion over */ + uint32_t EOC_CH61:1; /* Channel 61 conversion over */ + uint32_t EOC_CH60:1; /* Channel 60 conversion over */ + uint32_t EOC_CH59:1; /* Channel 59 conversion over */ + uint32_t EOC_CH58:1; /* Channel 58 conversion over */ + uint32_t EOC_CH57:1; /* Channel 57 conversion over */ + uint32_t EOC_CH56:1; /* Channel 56 conversion over */ + uint32_t EOC_CH55:1; /* Channel 55 conversion over */ + uint32_t EOC_CH54:1; /* Channel 54 conversion over */ + uint32_t EOC_CH53:1; /* Channel 53 conversion over */ + uint32_t EOC_CH52:1; /* Channel 52 conversion over */ + uint32_t EOC_CH51:1; /* Channel 51 conversion over */ + uint32_t EOC_CH50:1; /* Channel 50 conversion over */ + uint32_t EOC_CH49:1; /* Channel 49 conversion over */ + uint32_t EOC_CH48:1; /* Channel 48 conversion over */ + uint32_t EOC_CH47:1; /* Channel 47 conversion over */ + uint32_t EOC_CH46:1; /* Channel 46 conversion over */ + uint32_t EOC_CH45:1; /* Channel 45 conversion over */ + uint32_t EOC_CH44:1; /* Channel 44 conversion over */ + uint32_t EOC_CH43:1; /* Channel 43 conversion over */ + uint32_t EOC_CH42:1; /* Channel 42 conversion over */ + uint32_t EOC_CH41:1; /* Channel 41 conversion over */ + uint32_t EOC_CH40:1; /* Channel 40 conversion over */ + uint32_t EOC_CH39:1; /* Channel 39 conversion over */ + uint32_t EOC_CH38:1; /* Channel 38 conversion over */ + uint32_t EOC_CH37:1; /* Channel 37 conversion over */ + uint32_t EOC_CH36:1; /* Channel 36 conversion over */ + uint32_t EOC_CH35:1; /* Channel 35 conversion over */ + uint32_t EOC_CH34:1; /* Channel 34 conversion over */ + uint32_t EOC_CH33:1; /* Channel 33 conversion over */ + uint32_t EOC_CH32:1; /* Channel 32 conversion over */ + } B; + } ADC_CEOCFR1_32B_tag; + + typedef union { /* CHANNEL PENDING REGISTER 2 */ + uint32_t R; + struct { + uint32_t EOC_CH95:1; /* Channel 95 conversion over */ + uint32_t EOC_CH94:1; /* Channel 94 conversion over */ + uint32_t EOC_CH93:1; /* Channel 93 conversion over */ + uint32_t EOC_CH92:1; /* Channel 92 conversion over */ + uint32_t EOC_CH91:1; /* Channel 91 conversion over */ + uint32_t EOC_CH90:1; /* Channel 90 conversion over */ + uint32_t EOC_CH89:1; /* Channel 89 conversion over */ + uint32_t EOC_CH88:1; /* Channel 88 conversion over */ + uint32_t EOC_CH87:1; /* Channel 87 conversion over */ + uint32_t EOC_CH86:1; /* Channel 86 conversion over */ + uint32_t EOC_CH85:1; /* Channel 85 conversion over */ + uint32_t EOC_CH84:1; /* Channel 84 conversion over */ + uint32_t EOC_CH83:1; /* Channel 83 conversion over */ + uint32_t EOC_CH82:1; /* Channel 82 conversion over */ + uint32_t EOC_CH81:1; /* Channel 81 conversion over */ + uint32_t EOC_CH80:1; /* Channel 80 conversion over */ + uint32_t EOC_CH79:1; /* Channel 79 conversion over */ + uint32_t EOC_CH78:1; /* Channel 78 conversion over */ + uint32_t EOC_CH77:1; /* Channel 77 conversion over */ + uint32_t EOC_CH76:1; /* Channel 76 conversion over */ + uint32_t EOC_CH75:1; /* Channel 75 conversion over */ + uint32_t EOC_CH74:1; /* Channel 74 conversion over */ + uint32_t EOC_CH73:1; /* Channel 73 conversion over */ + uint32_t EOC_CH72:1; /* Channel 72 conversion over */ + uint32_t EOC_CH71:1; /* Channel 71 conversion over */ + uint32_t EOC_CH70:1; /* Channel 70 conversion over */ + uint32_t EOC_CH69:1; /* Channel 69 conversion over */ + uint32_t EOC_CH68:1; /* Channel 68 conversion over */ + uint32_t EOC_CH67:1; /* Channel 67 conversion over */ + uint32_t EOC_CH66:1; /* Channel 66 conversion over */ + uint32_t EOC_CH65:1; /* Channel 65 conversion over */ + uint32_t EOC_CH64:1; /* Channel 64 conversion over */ + } B; + } ADC_CEOCFR2_32B_tag; + + typedef union { /* interrupt mask register */ + uint32_t R; + struct { + uint32_t:25; + uint32_t MSKOFFCANCOVR:1; /* mask bit for Calibration over */ + uint32_t MSKEOFFSET:1; /* mask bit for Error in offset refresh */ + uint32_t MSKEOCTU:1; /* mask bit for EOCTU */ + uint32_t MSKJEOC:1; /* mask bit for JEOC */ + uint32_t MSKJECH:1; /* mask bit for JECH */ + uint32_t MSKEOC:1; /* mask bit for EOC */ + uint32_t MSKECH:1; /* mask bit for ECH */ + } B; + } ADC_IMR_32B_tag; + + typedef union { /* CHANNEL INTERRUPT MASK REGISTER 0 */ + uint32_t R; + struct { + uint32_t CIM31:1; /* Channel 31 mask register */ + uint32_t CIM30:1; /* Channel 30 mask register */ + uint32_t CIM29:1; /* Channel 29 mask register */ + uint32_t CIM28:1; /* Channel 28 mask register */ + uint32_t CIM27:1; /* Channel 27 mask register */ + uint32_t CIM26:1; /* Channel 26 mask register */ + uint32_t CIM25:1; /* Channel 25 mask register */ + uint32_t CIM24:1; /* Channel 24 mask register */ + uint32_t CIM23:1; /* Channel 23 mask register */ + uint32_t CIM22:1; /* Channel 22 mask register */ + uint32_t CIM21:1; /* Channel 21 mask register */ + uint32_t CIM20:1; /* Channel 20 mask register */ + uint32_t CIM19:1; /* Channel 19 mask register */ + uint32_t CIM18:1; /* Channel 18 mask register */ + uint32_t CIM17:1; /* Channel 17 mask register */ + uint32_t CIM16:1; /* Channel 16 mask register */ + uint32_t CIM15:1; /* Channel 15 mask register */ + uint32_t CIM14:1; /* Channel 14 mask register */ + uint32_t CIM13:1; /* Channel 13 mask register */ + uint32_t CIM12:1; /* Channel 12 mask register */ + uint32_t CIM11:1; /* Channel 11 mask register */ + uint32_t CIM10:1; /* Channel 10 mask register */ + uint32_t CIM9:1; /* Channel 9 mask register */ + uint32_t CIM8:1; /* Channel 8 mask register */ + uint32_t CIM7:1; /* Channel 7 mask register */ + uint32_t CIM6:1; /* Channel 6 mask register */ + uint32_t CIM5:1; /* Channel 5 mask register */ + uint32_t CIM4:1; /* Channel 4 mask register */ + uint32_t CIM3:1; /* Channel 3 mask register */ + uint32_t CIM2:1; /* Channel 2 mask register */ + uint32_t CIM1:1; /* Channel 1 mask register */ + uint32_t CIM0:1; /* Channel 0 mask register */ + } B; + } ADC_CIMR0_32B_tag; + + typedef union { /* CHANNEL INTERRUPT MASK REGISTER 1 */ + uint32_t R; + struct { + uint32_t CIM63:1; /* Channel 63 mask register */ + uint32_t CIM62:1; /* Channel 62 mask register */ + uint32_t CIM61:1; /* Channel 61 mask register */ + uint32_t CIM60:1; /* Channel 60 mask register */ + uint32_t CIM59:1; /* Channel 59 mask register */ + uint32_t CIM58:1; /* Channel 58 mask register */ + uint32_t CIM57:1; /* Channel 57 mask register */ + uint32_t CIM56:1; /* Channel 56 mask register */ + uint32_t CIM55:1; /* Channel 55 mask register */ + uint32_t CIM54:1; /* Channel 54 mask register */ + uint32_t CIM53:1; /* Channel 53 mask register */ + uint32_t CIM52:1; /* Channel 52 mask register */ + uint32_t CIM51:1; /* Channel 51 mask register */ + uint32_t CIM50:1; /* Channel 50 mask register */ + uint32_t CIM49:1; /* Channel 49 mask register */ + uint32_t CIM48:1; /* Channel 48 mask register */ + uint32_t CIM47:1; /* Channel 47 mask register */ + uint32_t CIM46:1; /* Channel 46 mask register */ + uint32_t CIM45:1; /* Channel 45 mask register */ + uint32_t CIM44:1; /* Channel 44 mask register */ + uint32_t CIM43:1; /* Channel 43 mask register */ + uint32_t CIM42:1; /* Channel 42 mask register */ + uint32_t CIM41:1; /* Channel 41 mask register */ + uint32_t CIM40:1; /* Channel 40 mask register */ + uint32_t CIM39:1; /* Channel 39 mask register */ + uint32_t CIM38:1; /* Channel 38 mask register */ + uint32_t CIM37:1; /* Channel 37 mask register */ + uint32_t CIM36:1; /* Channel 36 mask register */ + uint32_t CIM35:1; /* Channel 35 mask register */ + uint32_t CIM34:1; /* Channel 34 mask register */ + uint32_t CIM33:1; /* Channel 33 mask register */ + uint32_t CIM32:1; /* Channel 32 mask register */ + } B; + } ADC_CIMR1_32B_tag; + + typedef union { /* CHANNEL INTERRUPT MASK REGISTER 2 */ + uint32_t R; + struct { + uint32_t CIM95:1; /* Channel 95 mask register */ + uint32_t CIM94:1; /* Channel 94 mask register */ + uint32_t CIM93:1; /* Channel 93 mask register */ + uint32_t CIM92:1; /* Channel 92 mask register */ + uint32_t CIM91:1; /* Channel 91 mask register */ + uint32_t CIM90:1; /* Channel 90 mask register */ + uint32_t CIM89:1; /* Channel 89 mask register */ + uint32_t CIM88:1; /* Channel 88 mask register */ + uint32_t CIM87:1; /* Channel 87 mask register */ + uint32_t CIM86:1; /* Channel 86 mask register */ + uint32_t CIM85:1; /* Channel 85 mask register */ + uint32_t CIM84:1; /* Channel 84 mask register */ + uint32_t CIM83:1; /* Channel 83 mask register */ + uint32_t CIM82:1; /* Channel 82 mask register */ + uint32_t CIM81:1; /* Channel 81 mask register */ + uint32_t CIM80:1; /* Channel 80 mask register */ + uint32_t CIM79:1; /* Channel 79 mask register */ + uint32_t CIM78:1; /* Channel 78 mask register */ + uint32_t CIM77:1; /* Channel 77 mask register */ + uint32_t CIM76:1; /* Channel 76 mask register */ + uint32_t CIM75:1; /* Channel 75 mask register */ + uint32_t CIM74:1; /* Channel 74 mask register */ + uint32_t CIM73:1; /* Channel 73 mask register */ + uint32_t CIM72:1; /* Channel 72 mask register */ + uint32_t CIM71:1; /* Channel 71 mask register */ + uint32_t CIM70:1; /* Channel 70 mask register */ + uint32_t CIM69:1; /* Channel 69 mask register */ + uint32_t CIM68:1; /* Channel 68 mask register */ + uint32_t CIM67:1; /* Channel 67 mask register */ + uint32_t CIM66:1; /* Channel 66 mask register */ + uint32_t CIM65:1; /* Channel 65 mask register */ + uint32_t CIM64:1; /* Channel 64 mask register */ + } B; + } ADC_CIMR2_32B_tag; + + typedef union { /* Watchdog Threshold interrupt status register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t WDG3H:1; /* Interrupt generated on the value being higher than the HTHV 3 */ + uint32_t WDG2H:1; /* Interrupt generated on the value being higher than the HTHV 2 */ + uint32_t WDG1H:1; /* Interrupt generated on the value being higher than the HTHV 1 */ + uint32_t WDG0H:1; /* Interrupt generated on the value being higher than the HTHV 0 */ + uint32_t WDG3L:1; /* Interrupt generated on the value being lower than the LTHV 3 */ + uint32_t WDG2L:1; /* Interrupt generated on the value being lower than the LTHV 2 */ + uint32_t WDG1L:1; /* Interrupt generated on the value being lower than the LTHV 1 */ + uint32_t WDG0L:1; /* Interrupt generated on the value being lower than the LTHV 0 */ + } B; + } ADC_WTISR_32B_tag; + + typedef union { /* Watchdog interrupt MASK register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t MSKWDG3H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 3 */ + uint32_t MSKWDG2H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 2 */ + uint32_t MSKWDG1H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 1 */ + uint32_t MSKWDG0H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 0 */ + uint32_t MSKWDG3L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 3 */ + uint32_t MSKWDG2L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 2 */ + uint32_t MSKWDG1L:1; /* MAsk enable for Interrupt generated on the value being lower than the LTHV 1 */ + uint32_t MSKWDG0L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 0 */ + } B; + } ADC_WTIMR_32B_tag; + + typedef union { /* DMAE register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t DCLR:1; /* DMA clear sequence enable */ + uint32_t DMAEN:1; /* DMA global enable */ + } B; + } ADC_DMAE_32B_tag; + + typedef union { /* DMA REGISTER 0 */ + uint32_t R; + struct { + uint32_t DMA31:1; /* Channel 31 DMA Enable */ + uint32_t DMA30:1; /* Channel 30 DMA Enable */ + uint32_t DMA29:1; /* Channel 29 DMA Enable */ + uint32_t DMA28:1; /* Channel 28 DMA Enable */ + uint32_t DMA27:1; /* Channel 27 DMA Enable */ + uint32_t DMA26:1; /* Channel 26 DMA Enable */ + uint32_t DMA25:1; /* Channel 25 DMA Enable */ + uint32_t DMA24:1; /* Channel 24 DMA Enable */ + uint32_t DMA23:1; /* Channel 23 DMA Enable */ + uint32_t DMA22:1; /* Channel 22 DMA Enable */ + uint32_t DMA21:1; /* Channel 21 DMA Enable */ + uint32_t DMA20:1; /* Channel 20 DMA Enable */ + uint32_t DMA19:1; /* Channel 19 DMA Enable */ + uint32_t DMA18:1; /* Channel 18 DMA Enable */ + uint32_t DMA17:1; /* Channel 17 DMA Enable */ + uint32_t DMA16:1; /* Channel 16 DMA Enable */ + uint32_t DMA15:1; /* Channel 15 DMA Enable */ + uint32_t DMA14:1; /* Channel 14 DMA Enable */ + uint32_t DMA13:1; /* Channel 13 DMA Enable */ + uint32_t DMA12:1; /* Channel 12 DMA Enable */ + uint32_t DMA11:1; /* Channel 11 DMA Enable */ + uint32_t DMA10:1; /* Channel 10 DMA Enable */ + uint32_t DMA9:1; /* Channel 9 DMA Enable */ + uint32_t DMA8:1; /* Channel 8 DMA Enable */ + uint32_t DMA7:1; /* Channel 7 DMA Enable */ + uint32_t DMA6:1; /* Channel 6 DMA Enable */ + uint32_t DMA5:1; /* Channel 5 DMA Enable */ + uint32_t DMA4:1; /* Channel 4 DMA Enable */ + uint32_t DMA3:1; /* Channel 3 DMA Enable */ + uint32_t DMA2:1; /* Channel 2 DMA Enable */ + uint32_t DMA1:1; /* Channel 1 DMA Enable */ + uint32_t DMA0:1; /* Channel 0 DMA Enable */ + } B; + } ADC_DMAR0_32B_tag; + + typedef union { /* DMA REGISTER 1 */ + uint32_t R; + struct { + uint32_t DMA63:1; /* Channel 63 DMA Enable */ + uint32_t DMA62:1; /* Channel 62 DMA Enable */ + uint32_t DMA61:1; /* Channel 61 DMA Enable */ + uint32_t DMA60:1; /* Channel 60 DMA Enable */ + uint32_t DMA59:1; /* Channel 59 DMA Enable */ + uint32_t DMA58:1; /* Channel 58 DMA Enable */ + uint32_t DMA57:1; /* Channel 57 DMA Enable */ + uint32_t DMA56:1; /* Channel 56 DMA Enable */ + uint32_t DMA55:1; /* Channel 55 DMA Enable */ + uint32_t DMA54:1; /* Channel 54 DMA Enable */ + uint32_t DMA53:1; /* Channel 53 DMA Enable */ + uint32_t DMA52:1; /* Channel 52 DMA Enable */ + uint32_t DMA51:1; /* Channel 51 DMA Enable */ + uint32_t DMA50:1; /* Channel 50 DMA Enable */ + uint32_t DMA49:1; /* Channel 49 DMA Enable */ + uint32_t DMA48:1; /* Channel 48 DMA Enable */ + uint32_t DMA47:1; /* Channel 47 DMA Enable */ + uint32_t DMA46:1; /* Channel 46 DMA Enable */ + uint32_t DMA45:1; /* Channel 45 DMA Enable */ + uint32_t DMA44:1; /* Channel 44 DMA Enable */ + uint32_t DMA43:1; /* Channel 43 DMA Enable */ + uint32_t DMA42:1; /* Channel 42 DMA Enable */ + uint32_t DMA41:1; /* Channel 41 DMA Enable */ + uint32_t DMA40:1; /* Channel 40 DMA Enable */ + uint32_t DMA39:1; /* Channel 39 DMA Enable */ + uint32_t DMA38:1; /* Channel 38 DMA Enable */ + uint32_t DMA37:1; /* Channel 37 DMA Enable */ + uint32_t DMA36:1; /* Channel 36 DMA Enable */ + uint32_t DMA35:1; /* Channel 35 DMA Enable */ + uint32_t DMA34:1; /* Channel 34 DMA Enable */ + uint32_t DMA33:1; /* Channel 33 DMA Enable */ + uint32_t DMA32:1; /* Channel 32 DMA Enable */ + } B; + } ADC_DMAR1_32B_tag; + + typedef union { /* DMA REGISTER 2 */ + uint32_t R; + struct { + uint32_t DMA95:1; /* Channel 95 DMA Enable */ + uint32_t DMA94:1; /* Channel 94 DMA Enable */ + uint32_t DMA93:1; /* Channel 93 DMA Enable */ + uint32_t DMA92:1; /* Channel 92 DMA Enable */ + uint32_t DMA91:1; /* Channel 91 DMA Enable */ + uint32_t DMA90:1; /* Channel 90 DMA Enable */ + uint32_t DMA89:1; /* Channel 89 DMA Enable */ + uint32_t DMA88:1; /* Channel 88 DMA Enable */ + uint32_t DMA87:1; /* Channel 87 DMA Enable */ + uint32_t DMA86:1; /* Channel 86 DMA Enable */ + uint32_t DMA85:1; /* Channel 85 DMA Enable */ + uint32_t DMA84:1; /* Channel 84 DMA Enable */ + uint32_t DMA83:1; /* Channel 83 DMA Enable */ + uint32_t DMA82:1; /* Channel 82 DMA Enable */ + uint32_t DMA81:1; /* Channel 81 DMA Enable */ + uint32_t DMA80:1; /* Channel 80 DMA Enable */ + uint32_t DMA79:1; /* Channel 79 DMA Enable */ + uint32_t DMA78:1; /* Channel 78 DMA Enable */ + uint32_t DMA77:1; /* Channel 77 DMA Enable */ + uint32_t DMA76:1; /* Channel 76 DMA Enable */ + uint32_t DMA75:1; /* Channel 75 DMA Enable */ + uint32_t DMA74:1; /* Channel 74 DMA Enable */ + uint32_t DMA73:1; /* Channel 73 DMA Enable */ + uint32_t DMA72:1; /* Channel 72 DMA Enable */ + uint32_t DMA71:1; /* Channel 71 DMA Enable */ + uint32_t DMA70:1; /* Channel 70 DMA Enable */ + uint32_t DMA69:1; /* Channel 69 DMA Enable */ + uint32_t DMA68:1; /* Channel 68 DMA Enable */ + uint32_t DMA67:1; /* Channel 67 DMA Enable */ + uint32_t DMA66:1; /* Channel 66 DMA Enable */ + uint32_t DMA65:1; /* Channel 65 DMA Enable */ + uint32_t DMA64:1; /* Channel 64 DMA Enable */ + } B; + } ADC_DMAR2_32B_tag; + + + /* Register layout for all registers TRC... */ + + typedef union { /* Threshold Control register C */ + uint32_t R; + struct { + uint32_t:16; + uint32_t THREN:1; /* Threshold enable */ + uint32_t THRINV:1; /* invert the output pin */ + uint32_t THROP:1; /* output pin register */ + uint32_t:6; + uint32_t THRCH:7; /* Choose channel for threshold register */ + } B; + } ADC_TRC_32B_tag; + + + /* Register layout for all registers THRHLR... */ + + typedef union { /* Upper Threshold register */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR_32B_tag; + + + /* Register layout for all registers THRALT... */ + + typedef union { /* alternate Upper Threshold register */ + uint32_t R; + struct { + uint32_t:6; + uint32_t THRH:10; /* high threshold value s */ + uint32_t:6; + uint32_t THRL:10; /* low threshold value s */ + } B; + } ADC_THRALT_32B_tag; + + typedef union { /* PRESAMPLING CONTROL REGISTER */ + uint32_t R; + struct { + uint32_t:25; + uint32_t PREVAL2:2; /* INternal Voltage selection for Presampling */ + uint32_t PREVAL1:2; /* INternal Voltage selection for Presampling */ + uint32_t PREVAL0:2; /* INternal Voltage selection for Presampling */ +#ifndef USE_FIELD_ALIASES_ADC + uint32_t PRECONV:1; /* Presampled value */ +#else + uint32_t PREONCE:1; /* deprecated name - please avoid */ +#endif + } B; + } ADC_PSCR_32B_tag; + + typedef union { /* Presampling Register 0 */ + uint32_t R; + struct { + uint32_t PRES31:1; /* Channel 31 Presampling Enable */ + uint32_t PRES30:1; /* Channel 30 Presampling Enable */ + uint32_t PRES29:1; /* Channel 29 Presampling Enable */ + uint32_t PRES28:1; /* Channel 28 Presampling Enable */ + uint32_t PRES27:1; /* Channel 27 Presampling Enable */ + uint32_t PRES26:1; /* Channel 26 Presampling Enable */ + uint32_t PRES25:1; /* Channel 25 Presampling Enable */ + uint32_t PRES24:1; /* Channel 24 Presampling Enable */ + uint32_t PRES23:1; /* Channel 23 Presampling Enable */ + uint32_t PRES22:1; /* Channel 22 Presampling Enable */ + uint32_t PRES21:1; /* Channel 21 Presampling Enable */ + uint32_t PRES20:1; /* Channel 20 Presampling Enable */ + uint32_t PRES19:1; /* Channel 19 Presampling Enable */ + uint32_t PRES18:1; /* Channel 18 Presampling Enable */ + uint32_t PRES17:1; /* Channel 17 Presampling Enable */ + uint32_t PRES16:1; /* Channel 16 Presampling Enable */ + uint32_t PRES15:1; /* Channel 15 Presampling Enable */ + uint32_t PRES14:1; /* Channel 14 Presampling Enable */ + uint32_t PRES13:1; /* Channel 13 Presampling Enable */ + uint32_t PRES12:1; /* Channel 12 Presampling Enable */ + uint32_t PRES11:1; /* Channel 11 Presampling Enable */ + uint32_t PRES10:1; /* Channel 10 Presampling Enable */ + uint32_t PRES9:1; /* Channel 9 Presampling Enable */ + uint32_t PRES8:1; /* Channel 8 Presampling Enable */ + uint32_t PRES7:1; /* Channel 7 Presampling Enable */ + uint32_t PRES6:1; /* Channel 6 Presampling Enable */ + uint32_t PRES5:1; /* Channel 5 Presampling Enable */ + uint32_t PRES4:1; /* Channel 4 Presampling Enable */ + uint32_t PRES3:1; /* Channel 3 Presampling Enable */ + uint32_t PRES2:1; /* Channel 2 Presampling Enable */ + uint32_t PRES1:1; /* Channel 1presampling Enable */ + uint32_t PRES0:1; /* Channel 0 Presampling Enable */ + } B; + } ADC_PSR0_32B_tag; + + typedef union { /* Presampling REGISTER 1 */ + uint32_t R; + struct { + uint32_t PRES63:1; /* Channel 63 Presampling Enable */ + uint32_t PRES62:1; /* Channel 62 Presampling Enable */ + uint32_t PRES61:1; /* Channel 61 Presampling Enable */ + uint32_t PRES60:1; /* Channel 60 Presampling Enable */ + uint32_t PRES59:1; /* Channel 59 Presampling Enable */ + uint32_t PRES58:1; /* Channel 58 Presampling Enable */ + uint32_t PRES57:1; /* Channel 57 Presampling Enable */ + uint32_t PRES56:1; /* Channel 56 Presampling Enable */ + uint32_t PRES55:1; /* Channel 55 Presampling Enable */ + uint32_t PRES54:1; /* Channel 54 Presampling Enable */ + uint32_t PRES53:1; /* Channel 53 Presampling Enable */ + uint32_t PRES52:1; /* Channel 52 Presampling Enable */ + uint32_t PRES51:1; /* Channel 51 Presampling Enable */ + uint32_t PRES50:1; /* Channel 50 Presampling Enable */ + uint32_t PRES49:1; /* Channel 49 Presampling Enable */ + uint32_t PRES48:1; /* Channel 48 Presampling Enable */ + uint32_t PRES47:1; /* Channel 47 Presampling Enable */ + uint32_t PRES46:1; /* Channel 46 Presampling Enable */ + uint32_t PRES45:1; /* Channel 45 Presampling Enable */ + uint32_t PRES44:1; /* Channel 44 Presampling Enable */ + uint32_t PRES43:1; /* Channel 43 Presampling Enable */ + uint32_t PRES42:1; /* Channel 42 Presampling Enable */ + uint32_t PRES41:1; /* Channel 41 Presampling Enable */ + uint32_t PRES40:1; /* Channel 40 Presampling Enable */ + uint32_t PRES39:1; /* Channel 39 Presampling Enable */ + uint32_t PRES38:1; /* Channel 38 Presampling Enable */ + uint32_t PRES37:1; /* Channel 37 Presampling Enable */ + uint32_t PRES36:1; /* Channel 36 Presampling Enable */ + uint32_t PRES35:1; /* Channel 35 Presampling Enable */ + uint32_t PRES34:1; /* Channel 34 Presampling Enable */ + uint32_t PRES33:1; /* Channel 33 Presampling Enable */ + uint32_t PRES32:1; /* Channel 32 Presampling Enable */ + } B; + } ADC_PSR1_32B_tag; + + typedef union { /* Presampling REGISTER 2 */ + uint32_t R; + struct { + uint32_t PRES95:1; /* Channel 95 Presampling Enable */ + uint32_t PRES94:1; /* Channel 94 Presampling Enable */ + uint32_t PRES93:1; /* Channel 93 Presampling Enable */ + uint32_t PRES92:1; /* Channel 92 Presampling Enable */ + uint32_t PRES91:1; /* Channel 91 Presampling Enable */ + uint32_t PRES90:1; /* Channel 90 Presampling Enable */ + uint32_t PRES89:1; /* Channel 89 Presampling Enable */ + uint32_t PRES88:1; /* Channel 88 Presampling Enable */ + uint32_t PRES87:1; /* Channel 87 Presampling Enable */ + uint32_t PRES86:1; /* Channel 86 Presampling Enable */ + uint32_t PRES85:1; /* Channel 85 Presampling Enable */ + uint32_t PRES84:1; /* Channel 84 Presampling Enable */ + uint32_t PRES83:1; /* Channel 83 Presampling Enable */ + uint32_t PRES82:1; /* Channel 82 Presampling Enable */ + uint32_t PRES81:1; /* Channel 81 Presampling Enable */ + uint32_t PRES80:1; /* Channel 80 Presampling Enable */ + uint32_t PRES79:1; /* Channel 79 Presampling Enable */ + uint32_t PRES78:1; /* Channel 78 Presampling Enable */ + uint32_t PRES77:1; /* Channel 77 Presampling Enable */ + uint32_t PRES76:1; /* Channel 76 Presampling Enable */ + uint32_t PRES75:1; /* Channel 75 Presampling Enable */ + uint32_t PRES74:1; /* Channel 74 Presampling Enable */ + uint32_t PRES73:1; /* Channel 73 Presampling Enable */ + uint32_t PRES72:1; /* Channel 72 Presampling Enable */ + uint32_t PRES71:1; /* Channel 71 Presampling Enable */ + uint32_t PRES70:1; /* Channel 70 Presampling Enable */ + uint32_t PRES69:1; /* Channel 69 Presampling Enable */ + uint32_t PRES68:1; /* Channel 68 Presampling Enable */ + uint32_t PRES67:1; /* Channel 67 Presampling Enable */ + uint32_t PRES66:1; /* Channel 66 Presampling Enable */ + uint32_t PRES65:1; /* Channel 65 Presampling Enable */ + uint32_t PRES64:1; /* Channel 64 Presampling Enable */ + } B; + } ADC_PSR2_32B_tag; + + + /* Register layout for all registers CTR... */ + + typedef union { /* conversion timing register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t INPLATCH:1; /* configuration bits for the LATCHING PHASE duration */ + uint32_t:1; + uint32_t OFFSHIFT:2; /* configuration for offset shift characteristics */ + uint32_t:1; + uint32_t INPCMP:2; /* configuration bits for the COMPARISON duration */ + uint32_t:1; +#ifndef USE_FIELD_ALIASES_ADC + uint32_t INSAMP:8; /* configuration bits for the SAMPLING PHASE duration */ +#else + uint32_t INPSAMP:8; +#endif + } B; + } ADC_CTR_32B_tag; + + typedef union { /* NORMAL CONVERSION MASK REGISTER 0 */ + uint32_t R; + struct { + uint32_t CH31:1; /* Channel 31 Normal Sampling Enable */ + uint32_t CH30:1; /* Channel 30 Normal Sampling Enable */ + uint32_t CH29:1; /* Channel 29 Normal Sampling Enable */ + uint32_t CH28:1; /* Channel 28 Normal Sampling Enable */ + uint32_t CH27:1; /* Channel 27 Normal Sampling Enable */ + uint32_t CH26:1; /* Channel 26 Normal Sampling Enable */ + uint32_t CH25:1; /* Channel 25 Normal Sampling Enable */ + uint32_t CH24:1; /* Channel 24 Normal Sampling Enable */ + uint32_t CH23:1; /* Channel 23 Normal Sampling Enable */ + uint32_t CH22:1; /* Channel 22 Normal Sampling Enable */ + uint32_t CH21:1; /* Channel 21 Normal Sampling Enable */ + uint32_t CH20:1; /* Channel 20 Normal Sampling Enable */ + uint32_t CH19:1; /* Channel 19 Normal Sampling Enable */ + uint32_t CH18:1; /* Channel 18 Normal Sampling Enable */ + uint32_t CH17:1; /* Channel 17 Normal Sampling Enable */ + uint32_t CH16:1; /* Channel 16 Normal Sampling Enable */ + uint32_t CH15:1; /* Channel 15 Normal Sampling Enable */ + uint32_t CH14:1; /* Channel 14 Normal Sampling Enable */ + uint32_t CH13:1; /* Channel 13 Normal Sampling Enable */ + uint32_t CH12:1; /* Channel 12 Normal Sampling Enable */ + uint32_t CH11:1; /* Channel 11 Normal Sampling Enable */ + uint32_t CH10:1; /* Channel 10 Normal Sampling Enable */ + uint32_t CH9:1; /* Channel 9 Normal Sampling Enable */ + uint32_t CH8:1; /* Channel 8 Normal Sampling Enable */ + uint32_t CH7:1; /* Channel 7 Normal Sampling Enable */ + uint32_t CH6:1; /* Channel 6 Normal Sampling Enable */ + uint32_t CH5:1; /* Channel 5 Normal Sampling Enable */ + uint32_t CH4:1; /* Channel 4 Normal Sampling Enable */ + uint32_t CH3:1; /* Channel 3 Normal Sampling Enable */ + uint32_t CH2:1; /* Channel 2 Normal Sampling Enable */ + uint32_t CH1:1; /* Channel 1 Normal Sampling Enable */ + uint32_t CH0:1; /* Channel 0 Normal Sampling Enable */ + } B; + } ADC_NCMR0_32B_tag; + + typedef union { /* NORMAL CONVERSION MASK REGISTER 1 */ + uint32_t R; + struct { + uint32_t CH63:1; /* Channel 63 Normal Sampling Enable */ + uint32_t CH62:1; /* Channel 62 Normal Sampling Enable */ + uint32_t CH61:1; /* Channel 61 Normal Sampling Enable */ + uint32_t CH60:1; /* Channel 60 Normal Sampling Enable */ + uint32_t CH59:1; /* Channel 59 Normal Sampling Enable */ + uint32_t CH58:1; /* Channel 58 Normal Sampling Enable */ + uint32_t CH57:1; /* Channel 57 Normal Sampling Enable */ + uint32_t CH56:1; /* Channel 56 Normal Sampling Enable */ + uint32_t CH55:1; /* Channel 55 Normal Sampling Enable */ + uint32_t CH54:1; /* Channel 54 Normal Sampling Enable */ + uint32_t CH53:1; /* Channel 53 Normal Sampling Enable */ + uint32_t CH52:1; /* Channel 52 Normal Sampling Enable */ + uint32_t CH51:1; /* Channel 51 Normal Sampling Enable */ + uint32_t CH50:1; /* Channel 50 Normal Sampling Enable */ + uint32_t CH49:1; /* Channel 49 Normal Sampling Enable */ + uint32_t CH48:1; /* Channel 48 Normal Sampling Enable */ + uint32_t CH47:1; /* Channel 47 Normal Sampling Enable */ + uint32_t CH46:1; /* Channel 46 Normal Sampling Enable */ + uint32_t CH45:1; /* Channel 45 Normal Sampling Enable */ + uint32_t CH44:1; /* Channel 44 Normal Sampling Enable */ + uint32_t CH43:1; /* Channel 43 Normal Sampling Enable */ + uint32_t CH42:1; /* Channel 42 Normal Sampling Enable */ + uint32_t CH41:1; /* Channel 41 Normal Sampling Enable */ + uint32_t CH40:1; /* Channel 40 Normal Sampling Enable */ + uint32_t CH39:1; /* Channel 39 Normal Sampling Enable */ + uint32_t CH38:1; /* Channel 38 Normal Sampling Enable */ + uint32_t CH37:1; /* Channel 37 Normal Sampling Enable */ + uint32_t CH36:1; /* Channel 36 Normal Sampling Enable */ + uint32_t CH35:1; /* Channel 35 Normal Sampling Enable */ + uint32_t CH34:1; /* Channel 34 Normal Sampling Enable */ + uint32_t CH33:1; /* Channel 33 Normal Sampling Enable */ + uint32_t CH32:1; /* Channel 32 Normal Sampling Enable */ + } B; + } ADC_NCMR1_32B_tag; + + typedef union { /* NORMAL CONVERSION MASK REGISTER 2 */ + uint32_t R; + struct { + uint32_t CH95:1; /* Channel 95 Normal Sampling Enable */ + uint32_t CH94:1; /* Channel 94 Normal Sampling Enable */ + uint32_t CH93:1; /* Channel 93 Normal Sampling Enable */ + uint32_t CH92:1; /* Channel 92 Normal Sampling Enable */ + uint32_t CH91:1; /* Channel 91 Normal Sampling Enable */ + uint32_t CH90:1; /* Channel 90 Normal Sampling Enable */ + uint32_t CH89:1; /* Channel 89 Normal Sampling Enable */ + uint32_t CH88:1; /* Channel 88 Normal Sampling Enable */ + uint32_t CH87:1; /* Channel 87 Normal Sampling Enable */ + uint32_t CH86:1; /* Channel 86 Normal Sampling Enable */ + uint32_t CH85:1; /* Channel 85 Normal Sampling Enable */ + uint32_t CH84:1; /* Channel 84 Normal Sampling Enable */ + uint32_t CH83:1; /* Channel 83 Normal Sampling Enable */ + uint32_t CH82:1; /* Channel 82 Normal Sampling Enable */ + uint32_t CH81:1; /* Channel 81 Normal Sampling Enable */ + uint32_t CH80:1; /* Channel 80 Normal Sampling Enable */ + uint32_t CH79:1; /* Channel 79 Normal Sampling Enable */ + uint32_t CH78:1; /* Channel 78 Normal Sampling Enable */ + uint32_t CH77:1; /* Channel 77 Normal Sampling Enable */ + uint32_t CH76:1; /* Channel 76 Normal Sampling Enable */ + uint32_t CH75:1; /* Channel 75 Normal Sampling Enable */ + uint32_t CH74:1; /* Channel 74 Normal Sampling Enable */ + uint32_t CH73:1; /* Channel 73 Normal Sampling Enable */ + uint32_t CH72:1; /* Channel 72 Normal Sampling Enable */ + uint32_t CH71:1; /* Channel 71 Normal Sampling Enable */ + uint32_t CH70:1; /* Channel 70 Normal Sampling Enable */ + uint32_t CH69:1; /* Channel 69 Normal Sampling Enable */ + uint32_t CH68:1; /* Channel 68 Normal Sampling Enable */ + uint32_t CH67:1; /* Channel 67 Normal Sampling Enable */ + uint32_t CH66:1; /* Channel 66 Normal Sampling Enable */ + uint32_t CH65:1; /* Channel 65 Normal Sampling Enable */ + uint32_t CH64:1; /* Channel 64 Normal Sampling Enable */ + } B; + } ADC_NCMR2_32B_tag; + + typedef union { /* Injected Conversion Mask Register 0 */ + uint32_t R; + struct { + uint32_t CH31:1; /* Channel 31 Injected Sampling Enable */ + uint32_t CH30:1; /* Channel 30 Injected Sampling Enable */ + uint32_t CH29:1; /* Channel 29 Injected Sampling Enable */ + uint32_t CH28:1; /* Channel 28 Injected Sampling Enable */ + uint32_t CH27:1; /* Channel 27 Injected Sampling Enable */ + uint32_t CH26:1; /* Channel 26 Injected Sampling Enable */ + uint32_t CH25:1; /* Channel 25 Injected Sampling Enable */ + uint32_t CH24:1; /* Channel 24 Injected Sampling Enable */ + uint32_t CH23:1; /* Channel 23 Injected Sampling Enable */ + uint32_t CH22:1; /* Channel 22 Injected Sampling Enable */ + uint32_t CH21:1; /* Channel 21 Injected Sampling Enable */ + uint32_t CH20:1; /* Channel 20 Injected Sampling Enable */ + uint32_t CH19:1; /* Channel 19 Injected Sampling Enable */ + uint32_t CH18:1; /* Channel 18 Injected Sampling Enable */ + uint32_t CH17:1; /* Channel 17 Injected Sampling Enable */ + uint32_t CH16:1; /* Channel 16 Injected Sampling Enable */ + uint32_t CH15:1; /* Channel 15 Injected Sampling Enable */ + uint32_t CH14:1; /* Channel 14 Injected Sampling Enable */ + uint32_t CH13:1; /* Channel 13 Injected Sampling Enable */ + uint32_t CH12:1; /* Channel 12 Injected Sampling Enable */ + uint32_t CH11:1; /* Channel 11 Injected Sampling Enable */ + uint32_t CH10:1; /* Channel 10 Injected Sampling Enable */ + uint32_t CH9:1; /* Channel 9 Injected Sampling Enable */ + uint32_t CH8:1; /* Channel 8 Injected Sampling Enable */ + uint32_t CH7:1; /* Channel 7 Injected Sampling Enable */ + uint32_t CH6:1; /* Channel 6 Injected Sampling Enable */ + uint32_t CH5:1; /* Channel 5 Injected Sampling Enable */ + uint32_t CH4:1; /* Channel 4 Injected Sampling Enable */ + uint32_t CH3:1; /* Channel 3 Injected Sampling Enable */ + uint32_t CH2:1; /* Channel 2 Injected Sampling Enable */ + uint32_t CH1:1; /* Channel 1 injected Sampling Enable */ + uint32_t CH0:1; /* Channel 0 injected Sampling Enable */ + } B; + } ADC_JCMR0_32B_tag; + + typedef union { /* INJECTED CONVERSION MASK REGISTER 1 */ + uint32_t R; + struct { + uint32_t CH63:1; /* Channel 63 Injected Sampling Enable */ + uint32_t CH62:1; /* Channel 62 Injected Sampling Enable */ + uint32_t CH61:1; /* Channel 61 Injected Sampling Enable */ + uint32_t CH60:1; /* Channel 60 Injected Sampling Enable */ + uint32_t CH59:1; /* Channel 59 Injected Sampling Enable */ + uint32_t CH58:1; /* Channel 58 Injected Sampling Enable */ + uint32_t CH57:1; /* Channel 57 Injected Sampling Enable */ + uint32_t CH56:1; /* Channel 56 Injected Sampling Enable */ + uint32_t CH55:1; /* Channel 55 Injected Sampling Enable */ + uint32_t CH54:1; /* Channel 54 Injected Sampling Enable */ + uint32_t CH53:1; /* Channel 53 Injected Sampling Enable */ + uint32_t CH52:1; /* Channel 52 Injected Sampling Enable */ + uint32_t CH51:1; /* Channel 51 Injected Sampling Enable */ + uint32_t CH50:1; /* Channel 50 Injected Sampling Enable */ + uint32_t CH49:1; /* Channel 49 Injected Sampling Enable */ + uint32_t CH48:1; /* Channel 48 Injected Sampling Enable */ + uint32_t CH47:1; /* Channel 47 Injected Sampling Enable */ + uint32_t CH46:1; /* Channel 46 Injected Sampling Enable */ + uint32_t CH45:1; /* Channel 45 Injected Sampling Enable */ + uint32_t CH44:1; /* Channel 44 Injected Sampling Enable */ + uint32_t CH43:1; /* Channel 43 Injected Sampling Enable */ + uint32_t CH42:1; /* Channel 42 Injected Sampling Enable */ + uint32_t CH41:1; /* Channel 41 Injected Sampling Enable */ + uint32_t CH40:1; /* Channel 40 Injected Sampling Enable */ + uint32_t CH39:1; /* Channel 39 Injected Sampling Enable */ + uint32_t CH38:1; /* Channel 38 Injected Sampling Enable */ + uint32_t CH37:1; /* Channel 37 Injected Sampling Enable */ + uint32_t CH36:1; /* Channel 36 Injected Sampling Enable */ + uint32_t CH35:1; /* Channel 35 Injected Sampling Enable */ + uint32_t CH34:1; /* Channel 34 Injected Sampling Enable */ + uint32_t CH33:1; /* Channel 33 Injected Sampling Enable */ + uint32_t CH32:1; /* Channel 32 Injected Sampling Enable */ + } B; + } ADC_JCMR1_32B_tag; + + typedef union { /* INJECTED CONVERSION MASK REGISTER 2 */ + uint32_t R; + struct { + uint32_t CH95:1; /* Channel 95 Injected Sampling Enable */ + uint32_t CH94:1; /* Channel 94 Injected Sampling Enable */ + uint32_t CH93:1; /* Channel 93 Injected Sampling Enable */ + uint32_t CH92:1; /* Channel 92 Injected Sampling Enable */ + uint32_t CH91:1; /* Channel 91 Injected Sampling Enable */ + uint32_t CH90:1; /* Channel 90 Injected Sampling Enable */ + uint32_t CH89:1; /* Channel 89 Injected Sampling Enable */ + uint32_t CH88:1; /* Channel 88 Injected Sampling Enable */ + uint32_t CH87:1; /* Channel 87 Injected Sampling Enable */ + uint32_t CH86:1; /* Channel 86 Injected Sampling Enable */ + uint32_t CH85:1; /* Channel 85 Injected Sampling Enable */ + uint32_t CH84:1; /* Channel 84 Injected Sampling Enable */ + uint32_t CH83:1; /* Channel 83 Injected Sampling Enable */ + uint32_t CH82:1; /* Channel 82 Injected Sampling Enable */ + uint32_t CH81:1; /* Channel 81 Injected Sampling Enable */ + uint32_t CH80:1; /* Channel 80 Injected Sampling Enable */ + uint32_t CH79:1; /* Channel 79 Injected Sampling Enable */ + uint32_t CH78:1; /* Channel 78 Injected Sampling Enable */ + uint32_t CH77:1; /* Channel 77 Injected Sampling Enable */ + uint32_t CH76:1; /* Channel 76 Injected Sampling Enable */ + uint32_t CH75:1; /* Channel 75 Injected Sampling Enable */ + uint32_t CH74:1; /* Channel 74 Injected Sampling Enable */ + uint32_t CH73:1; /* Channel 73 Injected Sampling Enable */ + uint32_t CH72:1; /* Channel 72 Injected Sampling Enable */ + uint32_t CH71:1; /* Channel 71 Injected Sampling Enable */ + uint32_t CH70:1; /* Channel 70 Injected Sampling Enable */ + uint32_t CH69:1; /* Channel 69 Injected Sampling Enable */ + uint32_t CH68:1; /* Channel 68 Injected Sampling Enable */ + uint32_t CH67:1; /* Channel 67 Injected Sampling Enable */ + uint32_t CH66:1; /* Channel 66 Injected Sampling Enable */ + uint32_t CH65:1; /* Channel 65 Injected Sampling Enable */ + uint32_t CH64:1; /* Channel 64 Injected Sampling Enable */ + } B; + } ADC_JCMR2_32B_tag; + + typedef union { /* Offset Word Regsiter */ + uint32_t R; + struct { + uint32_t:15; + uint32_t OFFSETLOAD:1; /* load_offset */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ADC + uint32_t OFFSET_WORD:8; /* OFFSET word coeff.generated at the end of offset cancellation is lathed int o this register */ +#else + uint32_t OFFSETWORD:8; +#endif + } B; + } ADC_OFFWR_32B_tag; + + typedef union { /* Decode Signal Delay Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t DSD:8; /* take into account the settling time of the external mux */ + } B; + } ADC_DSDR_32B_tag; + + typedef union { /* Power Down Dealy Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t PDED:8; /* The delay between the power down bit reset and the starting of conversion */ + } B; + } ADC_PDEDR_32B_tag; + + + /* Register layout for all registers CDR... */ + + typedef union { /* CHANNEL DATA REGS */ + uint32_t R; + struct { + uint32_t:12; + uint32_t VALID:1; /* validity of data */ + uint32_t OVERW:1; /* overwrite data */ + uint32_t RESULT:2; /* reflects mode conversion */ + uint32_t:6; + uint32_t CDATA:10; /* Channel 0 converted data */ + } B; + } ADC_CDR_32B_tag; + + typedef union { /* Upper Threshold register 4 is not contiguous to 3 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR4_32B_tag; + + typedef union { /* Upper Threshold register 5 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR5_32B_tag; + + typedef union { /* Upper Threshold register 6 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR6_32B_tag; + + typedef union { /* Upper Threshold register 7 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR7_32B_tag; + + typedef union { /* Upper Threshold register 8 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR8_32B_tag; + + typedef union { /* Upper Threshold register 9 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR9_32B_tag; + + typedef union { /* Upper Threshold register 10 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR10_32B_tag; + + typedef union { /* Upper Threshold register 11 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR11_32B_tag; + + typedef union { /* Upper Threshold register 12 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR12_32B_tag; + + typedef union { /* Upper Threshold register 13 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR13_32B_tag; + + typedef union { /* Upper Threshold register 14 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR14_32B_tag; + + typedef union { /* Upper Threshold register 15 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR15_32B_tag; + + + /* Register layout for all registers CWSELR... */ + + typedef union { /* Channel Watchdog Select register */ + uint32_t R; + struct { + uint32_t WSEL_CH7:4; /* Channel Watchdog select for channel 7+R*8 */ + uint32_t WSEL_CH6:4; /* Channel Watchdog select for channel 6+R*8 */ + uint32_t WSEL_CH5:4; /* Channel Watchdog select for channel 5+R*8 */ + uint32_t WSEL_CH4:4; /* Channel Watchdog select for channel 4+R*8 */ + uint32_t WSEL_CH3:4; /* Channel Watchdog select for channel 3+R*8 */ + uint32_t WSEL_CH2:4; /* Channel Watchdog select for channel 2+R*8 */ + uint32_t WSEL_CH1:4; /* Channel Watchdog select for channel 1+R*8 */ + uint32_t WSEL_CH0:4; /* Channel Watchdog select for channel 0+R*8 */ + } B; + } ADC_CWSELR_32B_tag; + + + /* Register layout for all registers CWENR... */ + + typedef union { /* Channel Watchdog Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t CWEN15PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN14PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN13PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN12PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN11PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN10PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN09PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN08PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN07PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN06PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN05PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN04PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN03PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN02PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN01PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN00PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + } B; + } ADC_CWENR_32B_tag; + + + /* Register layout for all registers AWORR... */ + + typedef union { /* Analog Watchdog Out of Range Register */ + uint32_t R; + struct { + uint32_t AWOR_CH31:1; /* Channel 31+R*32 converted data out of range */ + uint32_t AWOR_CH30:1; /* Channel 30+R*32 converted data out of range */ + uint32_t AWOR_CH29:1; /* Channel 29+R*32 converted data out of range */ + uint32_t AWOR_CH28:1; /* Channel 28+R*32 converted data out of range */ + uint32_t AWOR_CH27:1; /* Channel 27+R*32 converted data out of range */ + uint32_t AWOR_CH26:1; /* Channel 26+R*32 converted data out of range */ + uint32_t AWOR_CH25:1; /* Channel 25+R*32 converted data out of range */ + uint32_t AWOR_CH24:1; /* Channel 24+R*32 converted data out of range */ + uint32_t AWOR_CH23:1; /* Channel 23+R*32 converted data out of range */ + uint32_t AWOR_CH22:1; /* Channel 22+R*32 converted data out of range */ + uint32_t AWOR_CH21:1; /* Channel 21+R*32 converted data out of range */ + uint32_t AWOR_CH20:1; /* Channel 20+R*32 converted data out of range */ + uint32_t AWOR_CH19:1; /* Channel 19+R*32 converted data out of range */ + uint32_t AWOR_CH18:1; /* Channel 18+R*32 converted data out of range */ + uint32_t AWOR_CH17:1; /* Channel 17+R*32 converted data out of range */ + uint32_t AWOR_CH16:1; /* Channel 16+R*32 converted data out of range */ + uint32_t AWOR_CH15:1; /* Channel 15+R*32 converted data out of range */ + uint32_t AWOR_CH14:1; /* Channel 14+R*32 converted data out of range */ + uint32_t AWOR_CH13:1; /* Channel 13+R*32 converted data out of range */ + uint32_t AWOR_CH12:1; /* Channel 12+R*32 converted data out of range */ + uint32_t AWOR_CH11:1; /* Channel 11+R*32 converted data out of range */ + uint32_t AWOR_CH10:1; /* Channel 10+R*32 converted data out of range */ + uint32_t AWOR_CH9:1; /* Channel 9+R*32 converted data out of range */ + uint32_t AWOR_CH8:1; /* Channel 8+R*32 converted data out of range */ + uint32_t AWOR_CH7:1; /* Channel 7+R*32 converted data out of range */ + uint32_t AWOR_CH6:1; /* Channel 6+R*32 converted data out of range */ + uint32_t AWOR_CH5:1; /* Channel 5+R*32 converted data out of range */ + uint32_t AWOR_CH4:1; /* Channel 4+R*32 converted data out of range */ + uint32_t AWOR_CH3:1; /* Channel 3+R*32 converted data out of range */ + uint32_t AWOR_CH2:1; /* Channel 2+R*32 converted data out of range */ + uint32_t AWOR_CH1:1; /* Channel 1+R*32 converted data out of range */ + uint32_t AWOR_CH0:1; /* Channel 0+R*32 converted data out of range */ + } B; + } ADC_AWORR_32B_tag; + + typedef union { /* SELF TEST CONFIGURATION REGISTER 1 */ + uint32_t R; + struct { + uint32_t INPSAMP_C:8; /* Sampling phase duration for the test conversions - algorithm C */ + uint32_t INPSAMP_RC:8; /* Sampling phase duration for the test conversions - algorithm RC */ + uint32_t INPSAMP_S:8; /* Sampling phase duration for the test conversions - algorithm S */ + uint32_t:5; + uint32_t ST_INPCMP:2; /* Configuration bit for comparison phase duration for self test channel */ + uint32_t ST_INPLATCH:1; /* Configuration bit for Latching phase duration for self test channel */ + } B; + } ADC_STCR1_32B_tag; + + typedef union { /* SELF TEST CONFIGURATION REGISTER 2 */ + uint32_t R; + struct { + uint32_t:5; + uint32_t SERR:1; /* Error fault injection bit (write only) */ + uint32_t MSKSTWDTERR:1; /* Interrupt enable (STSR2.WDTERR status bit) */ + uint32_t:1; + uint32_t MSKST_EOC:1; /* Interrupt enable bit for STSR2.ST_EOC */ + uint32_t:4; + uint32_t MSKWDG_EOA_C:1; /* Interrupt enable (WDG_EOA_C status bit) */ + uint32_t MSKWDG_EOA_RC:1; /* Interrupt enable (WDG_EOA_RC status bit) */ + uint32_t MSKWDG_EOA_S:1; /* Interrupt enable (WDG_EOA_S status bit) */ + uint32_t MSKERR_C:1; /* Interrupt enable (ERR_C status bit) */ + uint32_t MSKERR_RC:1; /* Interrupt enable (ERR_RC status bit) */ + uint32_t MSKERR_S2:1; /* Interrupt enable (ERR_S2 status bit) */ + uint32_t MSKERR_S1:1; /* Interrupt enable (ERR_S1 status bit) */ + uint32_t MSKERR_S0:1; /* Interrupt enable (ERR_S0 status bit) */ + uint32_t:3; + uint32_t EN:1; /* Self testing channel enable */ + uint32_t:4; + uint32_t FMA_C:1; /* Fault mapping for the algorithm C */ + uint32_t FMAR_C:1; /* Fault mapping for the algorithm RC */ + uint32_t FMA_S:1; /* Fault mapping for the algorithm BGAP */ + } B; + } ADC_STCR2_32B_tag; + + typedef union { /* SELF TEST CONFIGURATION REGISTER 3 */ + uint32_t R; + struct { + uint32_t:22; + uint32_t ALG:2; /* Algorithm scheduling */ + uint32_t:8; + } B; + } ADC_STCR3_32B_tag; + + typedef union { /* SELF TEST BAUD RATE REGISTER */ + uint32_t R; + struct { + uint32_t:13; + uint32_t WDT:3; /* Watchdog timer value */ + uint32_t:8; + uint32_t BR:8; /* Baud rate for the selected algorithm in SCAN mode */ + } B; + } ADC_STBRR_32B_tag; + + typedef union { /* SELF TEST STATUS REGISTER 1 */ + uint32_t R; + struct { + uint32_t:6; + uint32_t WDTERR:1; /* Watchdog timer error */ + uint32_t OVERWR:1; /* Overwrite error */ + uint32_t ST_EOC:1; /* Self test EOC bit */ + uint32_t:4; + uint32_t WDG_EOA_C:1; /* Algorithm C completed without error */ + uint32_t WDG_EOA_RC:1; /* Algorithm RC completed without error */ + uint32_t WDG_EOA_S:1; /* Algorithm S completed without error */ + uint32_t ERR_C:1; /* Error on the self testing channel (algorithm C) */ + uint32_t ERR_RC:1; /* Error on the self testing channel (algorithm RC) */ + uint32_t ERR_S2:1; /* Error on the self testing channel (algorithm SUPPLY, step 2) */ + uint32_t ERR_S1:1; /* Error on the self testing channel (algorithm SUPPLY, step 1) */ + uint32_t ERR_S0:1; /* Error on the self testing channel (algorithm SUPPLY, step 0) */ + uint32_t:1; + uint32_t STEP_C:5; /* Step of algorithm C when ERR_C has occurred */ + uint32_t STEP_RC:5; /* Step of algorithm RC when ERR_RC has occurred */ + } B; + } ADC_STSR1_32B_tag; + + typedef union { /* SELF TEST STATUS REGISTER 2 */ + uint32_t R; + struct { + uint32_t OVFL:1; /* Overflow bit */ + uint32_t:3; + uint32_t DATA1:12; /* Test channel converted data when ERR_S1 has occurred */ + uint32_t:4; + uint32_t DATA0:12; /* Test channel converted data when ERR_S1 has occurred */ + } B; + } ADC_STSR2_32B_tag; + + typedef union { /* SELF TEST STATUS REGISTER 3 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t DATA1:12; /* Test channel converted data when ERR_S0 has occurred */ + uint32_t:4; + uint32_t DATA0:12; /* Test channel converted data when ERR_S0 has occurred */ + } B; + } ADC_STSR3_32B_tag; + + typedef union { /* SELF TEST STATUS REGISTER 4 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t DATA1:12; /* Test channel converted data when ERR_C has occurred */ + uint32_t:4; + uint32_t DATA0:12; /* Test channel converted data when ERR_C has occurred */ + } B; + } ADC_STSR4_32B_tag; + + typedef union { /* SELF TEST DATA REGISTER 1 */ + uint32_t R; + struct { + uint32_t:12; + uint32_t VALID:1; /* Valid data */ + uint32_t OVERWR:1; /* Overwrite data */ + uint32_t:6; + uint32_t TCDATA:12; /* Test channel converted data */ + } B; + } ADC_STDR1_32B_tag; + + typedef union { /* SELF TEST DATA REGISTER 2 */ + uint32_t R; + struct { + uint32_t FDATA:12; /* Fractional part of the ratio TEST for algorithm S */ + uint32_t VALID:1; /* Valid data */ + uint32_t OVERWR:1; /* Overwrite data */ + uint32_t:6; + uint32_t IDATA:12; /* Integer part of the ratio TEST for algorithm S */ + } B; + } ADC_STDR2_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 0 */ + uint32_t R; + struct { + uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ + uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm S */ + uint32_t:2; + uint32_t THRH:12; /* High threshold value for channel 0 */ + uint32_t:4; + uint32_t THRL:12; /* Low threshold value for channel 0 */ + } B; + } ADC_STAW0R_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1A */ + uint32_t R; + struct { + uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ + uint32_t:3; + uint32_t THRH:12; /* High threshold value for test channel - algorithm S */ + uint32_t:4; + uint32_t THRL:12; /* Low threshold value for test channel - algorithm S */ + } B; + } ADC_STAW1AR_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1B */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* High threshold value for test channel - algorithm S */ + uint32_t:4; + uint32_t THRL:12; /* Low threshold value for test channel - algorithm S */ + } B; + } ADC_STAW1BR_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 2 */ + uint32_t R; + struct { + uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ + uint32_t:19; + uint32_t THRL:12; /* Low threshold value for channel */ + } B; + } ADC_STAW2R_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 3 */ + uint32_t R; + struct { + uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm RC */ + uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm RC */ + uint32_t:2; + uint32_t THRH:12; /* High threshold value for channel 3 */ + uint32_t:4; + uint32_t THRL:12; /* Low threshold value for channel 3 */ + } B; + } ADC_STAW3R_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 4 */ + uint32_t R; + struct { + uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm C */ + uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm C */ + uint32_t:2; + uint32_t THRH:12; /* High threshold value for channel 4 */ + uint32_t:4; + uint32_t THRL:12; /* Low threshold value for channel 4 */ + } B; + } ADC_STAW4R_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 5 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* High threshold value for algorithm C */ + uint32_t:4; + uint32_t THRL:12; /* Low threshold value for algorithm C */ + } B; + } ADC_STAW5R_32B_tag; + + + + typedef struct ADC_struct_tag { /* start of ADC_tag */ + /* module configuration register */ + ADC_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ + /* module status register */ + ADC_MSR_32B_tag MSR; /* offset: 0x0004 size: 32 bit */ + int8_t ADC_reserved_0008[8]; + /* Interrupt status register */ + ADC_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */ + union { + ADC_CEOCFR0_32B_tag CEOCFR[3]; /* offset: 0x0014 (0x0004 x 3) */ + + struct { + /* CHANNEL PENDING REGISTER 0 */ + ADC_CEOCFR0_32B_tag CEOCFR0; /* offset: 0x0014 size: 32 bit */ + /* CHANNEL PENDING REGISTER 1 */ + ADC_CEOCFR1_32B_tag CEOCFR1; /* offset: 0x0018 size: 32 bit */ + /* CHANNEL PENDING REGISTER 2 */ + ADC_CEOCFR2_32B_tag CEOCFR2; /* offset: 0x001C size: 32 bit */ + }; + + }; + /* interrupt mask register */ + ADC_IMR_32B_tag IMR; /* offset: 0x0020 size: 32 bit */ + union { + ADC_CIMR0_32B_tag CIMR[3]; /* offset: 0x0024 (0x0004 x 3) */ + + struct { + /* CHANNEL INTERRUPT MASK REGISTER 0 */ + ADC_CIMR0_32B_tag CIMR0; /* offset: 0x0024 size: 32 bit */ + /* CHANNEL INTERRUPT MASK REGISTER 1 */ + ADC_CIMR1_32B_tag CIMR1; /* offset: 0x0028 size: 32 bit */ + /* CHANNEL INTERRUPT MASK REGISTER 2 */ + ADC_CIMR2_32B_tag CIMR2; /* offset: 0x002C size: 32 bit */ + }; + + }; + /* Watchdog Threshold interrupt status register */ + ADC_WTISR_32B_tag WTISR; /* offset: 0x0030 size: 32 bit */ + /* Watchdog interrupt MASK register */ + ADC_WTIMR_32B_tag WTIMR; /* offset: 0x0034 size: 32 bit */ + int8_t ADC_reserved_0038[8]; + /* DMAE register */ + ADC_DMAE_32B_tag DMAE; /* offset: 0x0040 size: 32 bit */ + union { + ADC_DMAR0_32B_tag DMAR[3]; /* offset: 0x0044 (0x0004 x 3) */ + + struct { + /* DMA REGISTER 0 */ + ADC_DMAR0_32B_tag DMAR0; /* offset: 0x0044 size: 32 bit */ + /* DMA REGISTER 1 */ + ADC_DMAR1_32B_tag DMAR1; /* offset: 0x0048 size: 32 bit */ + /* DMA REGISTER 2 */ + ADC_DMAR2_32B_tag DMAR2; /* offset: 0x004C size: 32 bit */ + }; + + }; + union { + /* Threshold Control register C */ + ADC_TRC_32B_tag TRC[4]; /* offset: 0x0050 (0x0004 x 4) */ + + struct { + /* Threshold Control register C */ + ADC_TRC_32B_tag TRC0; /* offset: 0x0050 size: 32 bit */ + ADC_TRC_32B_tag TRC1; /* offset: 0x0054 size: 32 bit */ + ADC_TRC_32B_tag TRC2; /* offset: 0x0058 size: 32 bit */ + ADC_TRC_32B_tag TRC3; /* offset: 0x005C size: 32 bit */ + }; + + }; + union { + /* Upper Threshold register */ + ADC_THRHLR_32B_tag THRHLR[4]; /* offset: 0x0060 (0x0004 x 4) */ + + struct { + /* Upper Threshold register */ + ADC_THRHLR_32B_tag THRHLR0; /* offset: 0x0060 size: 32 bit */ + ADC_THRHLR_32B_tag THRHLR1; /* offset: 0x0064 size: 32 bit */ + ADC_THRHLR_32B_tag THRHLR2; /* offset: 0x0068 size: 32 bit */ + ADC_THRHLR_32B_tag THRHLR3; /* offset: 0x006C size: 32 bit */ + }; + + }; + union { + /* alternate Upper Threshold register */ + ADC_THRALT_32B_tag THRALT[4]; /* offset: 0x0070 (0x0004 x 4) */ + + struct { + /* alternate Upper Threshold register */ + ADC_THRALT_32B_tag THRALT0; /* offset: 0x0070 size: 32 bit */ + ADC_THRALT_32B_tag THRALT1; /* offset: 0x0074 size: 32 bit */ + ADC_THRALT_32B_tag THRALT2; /* offset: 0x0078 size: 32 bit */ + ADC_THRALT_32B_tag THRALT3; /* offset: 0x007C size: 32 bit */ + }; + + }; + /* PRESAMPLING CONTROL REGISTER */ + ADC_PSCR_32B_tag PSCR; /* offset: 0x0080 size: 32 bit */ + union { + ADC_PSR0_32B_tag PSR[3]; /* offset: 0x0084 (0x0004 x 3) */ + + struct { + /* Presampling Register 0 */ + ADC_PSR0_32B_tag PSR0; /* offset: 0x0084 size: 32 bit */ + /* Presampling REGISTER 1 */ + ADC_PSR1_32B_tag PSR1; /* offset: 0x0088 size: 32 bit */ + /* Presampling REGISTER 2 */ + ADC_PSR2_32B_tag PSR2; /* offset: 0x008C size: 32 bit */ + }; + + }; + int8_t ADC_reserved_0090_C[4]; + union { + /* conversion timing register */ + ADC_CTR_32B_tag CTR[3]; /* offset: 0x0094 (0x0004 x 3) */ + + struct { + /* conversion timing register */ + ADC_CTR_32B_tag CTR0; /* offset: 0x0094 size: 32 bit */ + ADC_CTR_32B_tag CTR1; /* offset: 0x0098 size: 32 bit */ + ADC_CTR_32B_tag CTR2; /* offset: 0x009C size: 32 bit */ + }; + + }; + int8_t ADC_reserved_00A0_C[4]; + union { + ADC_NCMR0_32B_tag NCMR[3]; /* offset: 0x00A4 (0x0004 x 3) */ + + struct { + /* NORMAL CONVERSION MASK REGISTER 0 */ + ADC_NCMR0_32B_tag NCMR0; /* offset: 0x00A4 size: 32 bit */ + /* NORMAL CONVERSION MASK REGISTER 1 */ + ADC_NCMR1_32B_tag NCMR1; /* offset: 0x00A8 size: 32 bit */ + /* NORMAL CONVERSION MASK REGISTER 2 */ + ADC_NCMR2_32B_tag NCMR2; /* offset: 0x00AC size: 32 bit */ + }; + + }; + int8_t ADC_reserved_00B0_C[4]; + union { + ADC_JCMR0_32B_tag JCMR[3]; /* offset: 0x00B4 (0x0004 x 3) */ + + struct { + /* Injected Conversion Mask Register 0 */ + ADC_JCMR0_32B_tag JCMR0; /* offset: 0x00B4 size: 32 bit */ + /* INJECTED CONVERSION MASK REGISTER 1 */ + ADC_JCMR1_32B_tag JCMR1; /* offset: 0x00B8 size: 32 bit */ + /* INJECTED CONVERSION MASK REGISTER 2 */ + ADC_JCMR2_32B_tag JCMR2; /* offset: 0x00BC size: 32 bit */ + }; + + }; + /* Offset Word Regsiter */ + ADC_OFFWR_32B_tag OFFWR; /* offset: 0x00C0 size: 32 bit */ + /* Decode Signal Delay Register */ + ADC_DSDR_32B_tag DSDR; /* offset: 0x00C4 size: 32 bit */ + /* Power Down Dealy Register */ + ADC_PDEDR_32B_tag PDEDR; /* offset: 0x00C8 size: 32 bit */ + int8_t ADC_reserved_00CC_C[52]; + union { + /* CHANNEL DATA REGS */ + ADC_CDR_32B_tag CDR[96]; /* offset: 0x0100 (0x0004 x 96) */ + + struct { + /* CHANNEL DATA REGS */ + ADC_CDR_32B_tag CDR0; /* offset: 0x0100 size: 32 bit */ + ADC_CDR_32B_tag CDR1; /* offset: 0x0104 size: 32 bit */ + ADC_CDR_32B_tag CDR2; /* offset: 0x0108 size: 32 bit */ + ADC_CDR_32B_tag CDR3; /* offset: 0x010C size: 32 bit */ + ADC_CDR_32B_tag CDR4; /* offset: 0x0110 size: 32 bit */ + ADC_CDR_32B_tag CDR5; /* offset: 0x0114 size: 32 bit */ + ADC_CDR_32B_tag CDR6; /* offset: 0x0118 size: 32 bit */ + ADC_CDR_32B_tag CDR7; /* offset: 0x011C size: 32 bit */ + ADC_CDR_32B_tag CDR8; /* offset: 0x0120 size: 32 bit */ + ADC_CDR_32B_tag CDR9; /* offset: 0x0124 size: 32 bit */ + ADC_CDR_32B_tag CDR10; /* offset: 0x0128 size: 32 bit */ + ADC_CDR_32B_tag CDR11; /* offset: 0x012C size: 32 bit */ + ADC_CDR_32B_tag CDR12; /* offset: 0x0130 size: 32 bit */ + ADC_CDR_32B_tag CDR13; /* offset: 0x0134 size: 32 bit */ + ADC_CDR_32B_tag CDR14; /* offset: 0x0138 size: 32 bit */ + ADC_CDR_32B_tag CDR15; /* offset: 0x013C size: 32 bit */ + ADC_CDR_32B_tag CDR16; /* offset: 0x0140 size: 32 bit */ + ADC_CDR_32B_tag CDR17; /* offset: 0x0144 size: 32 bit */ + ADC_CDR_32B_tag CDR18; /* offset: 0x0148 size: 32 bit */ + ADC_CDR_32B_tag CDR19; /* offset: 0x014C size: 32 bit */ + ADC_CDR_32B_tag CDR20; /* offset: 0x0150 size: 32 bit */ + ADC_CDR_32B_tag CDR21; /* offset: 0x0154 size: 32 bit */ + ADC_CDR_32B_tag CDR22; /* offset: 0x0158 size: 32 bit */ + ADC_CDR_32B_tag CDR23; /* offset: 0x015C size: 32 bit */ + ADC_CDR_32B_tag CDR24; /* offset: 0x0160 size: 32 bit */ + ADC_CDR_32B_tag CDR25; /* offset: 0x0164 size: 32 bit */ + ADC_CDR_32B_tag CDR26; /* offset: 0x0168 size: 32 bit */ + ADC_CDR_32B_tag CDR27; /* offset: 0x016C size: 32 bit */ + ADC_CDR_32B_tag CDR28; /* offset: 0x0170 size: 32 bit */ + ADC_CDR_32B_tag CDR29; /* offset: 0x0174 size: 32 bit */ + ADC_CDR_32B_tag CDR30; /* offset: 0x0178 size: 32 bit */ + ADC_CDR_32B_tag CDR31; /* offset: 0x017C size: 32 bit */ + ADC_CDR_32B_tag CDR32; /* offset: 0x0180 size: 32 bit */ + ADC_CDR_32B_tag CDR33; /* offset: 0x0184 size: 32 bit */ + ADC_CDR_32B_tag CDR34; /* offset: 0x0188 size: 32 bit */ + ADC_CDR_32B_tag CDR35; /* offset: 0x018C size: 32 bit */ + ADC_CDR_32B_tag CDR36; /* offset: 0x0190 size: 32 bit */ + ADC_CDR_32B_tag CDR37; /* offset: 0x0194 size: 32 bit */ + ADC_CDR_32B_tag CDR38; /* offset: 0x0198 size: 32 bit */ + ADC_CDR_32B_tag CDR39; /* offset: 0x019C size: 32 bit */ + ADC_CDR_32B_tag CDR40; /* offset: 0x01A0 size: 32 bit */ + ADC_CDR_32B_tag CDR41; /* offset: 0x01A4 size: 32 bit */ + ADC_CDR_32B_tag CDR42; /* offset: 0x01A8 size: 32 bit */ + ADC_CDR_32B_tag CDR43; /* offset: 0x01AC size: 32 bit */ + ADC_CDR_32B_tag CDR44; /* offset: 0x01B0 size: 32 bit */ + ADC_CDR_32B_tag CDR45; /* offset: 0x01B4 size: 32 bit */ + ADC_CDR_32B_tag CDR46; /* offset: 0x01B8 size: 32 bit */ + ADC_CDR_32B_tag CDR47; /* offset: 0x01BC size: 32 bit */ + ADC_CDR_32B_tag CDR48; /* offset: 0x01C0 size: 32 bit */ + ADC_CDR_32B_tag CDR49; /* offset: 0x01C4 size: 32 bit */ + ADC_CDR_32B_tag CDR50; /* offset: 0x01C8 size: 32 bit */ + ADC_CDR_32B_tag CDR51; /* offset: 0x01CC size: 32 bit */ + ADC_CDR_32B_tag CDR52; /* offset: 0x01D0 size: 32 bit */ + ADC_CDR_32B_tag CDR53; /* offset: 0x01D4 size: 32 bit */ + ADC_CDR_32B_tag CDR54; /* offset: 0x01D8 size: 32 bit */ + ADC_CDR_32B_tag CDR55; /* offset: 0x01DC size: 32 bit */ + ADC_CDR_32B_tag CDR56; /* offset: 0x01E0 size: 32 bit */ + ADC_CDR_32B_tag CDR57; /* offset: 0x01E4 size: 32 bit */ + ADC_CDR_32B_tag CDR58; /* offset: 0x01E8 size: 32 bit */ + ADC_CDR_32B_tag CDR59; /* offset: 0x01EC size: 32 bit */ + ADC_CDR_32B_tag CDR60; /* offset: 0x01F0 size: 32 bit */ + ADC_CDR_32B_tag CDR61; /* offset: 0x01F4 size: 32 bit */ + ADC_CDR_32B_tag CDR62; /* offset: 0x01F8 size: 32 bit */ + ADC_CDR_32B_tag CDR63; /* offset: 0x01FC size: 32 bit */ + ADC_CDR_32B_tag CDR64; /* offset: 0x0200 size: 32 bit */ + ADC_CDR_32B_tag CDR65; /* offset: 0x0204 size: 32 bit */ + ADC_CDR_32B_tag CDR66; /* offset: 0x0208 size: 32 bit */ + ADC_CDR_32B_tag CDR67; /* offset: 0x020C size: 32 bit */ + ADC_CDR_32B_tag CDR68; /* offset: 0x0210 size: 32 bit */ + ADC_CDR_32B_tag CDR69; /* offset: 0x0214 size: 32 bit */ + ADC_CDR_32B_tag CDR70; /* offset: 0x0218 size: 32 bit */ + ADC_CDR_32B_tag CDR71; /* offset: 0x021C size: 32 bit */ + ADC_CDR_32B_tag CDR72; /* offset: 0x0220 size: 32 bit */ + ADC_CDR_32B_tag CDR73; /* offset: 0x0224 size: 32 bit */ + ADC_CDR_32B_tag CDR74; /* offset: 0x0228 size: 32 bit */ + ADC_CDR_32B_tag CDR75; /* offset: 0x022C size: 32 bit */ + ADC_CDR_32B_tag CDR76; /* offset: 0x0230 size: 32 bit */ + ADC_CDR_32B_tag CDR77; /* offset: 0x0234 size: 32 bit */ + ADC_CDR_32B_tag CDR78; /* offset: 0x0238 size: 32 bit */ + ADC_CDR_32B_tag CDR79; /* offset: 0x023C size: 32 bit */ + ADC_CDR_32B_tag CDR80; /* offset: 0x0240 size: 32 bit */ + ADC_CDR_32B_tag CDR81; /* offset: 0x0244 size: 32 bit */ + ADC_CDR_32B_tag CDR82; /* offset: 0x0248 size: 32 bit */ + ADC_CDR_32B_tag CDR83; /* offset: 0x024C size: 32 bit */ + ADC_CDR_32B_tag CDR84; /* offset: 0x0250 size: 32 bit */ + ADC_CDR_32B_tag CDR85; /* offset: 0x0254 size: 32 bit */ + ADC_CDR_32B_tag CDR86; /* offset: 0x0258 size: 32 bit */ + ADC_CDR_32B_tag CDR87; /* offset: 0x025C size: 32 bit */ + ADC_CDR_32B_tag CDR88; /* offset: 0x0260 size: 32 bit */ + ADC_CDR_32B_tag CDR89; /* offset: 0x0264 size: 32 bit */ + ADC_CDR_32B_tag CDR90; /* offset: 0x0268 size: 32 bit */ + ADC_CDR_32B_tag CDR91; /* offset: 0x026C size: 32 bit */ + ADC_CDR_32B_tag CDR92; /* offset: 0x0270 size: 32 bit */ + ADC_CDR_32B_tag CDR93; /* offset: 0x0274 size: 32 bit */ + ADC_CDR_32B_tag CDR94; /* offset: 0x0278 size: 32 bit */ + ADC_CDR_32B_tag CDR95; /* offset: 0x027C size: 32 bit */ + }; + + }; + /* Upper Threshold register 4 is not contiguous to 3 */ + ADC_THRHLR4_32B_tag THRHLR4; /* offset: 0x0280 size: 32 bit */ + /* Upper Threshold register 5 */ + ADC_THRHLR5_32B_tag THRHLR5; /* offset: 0x0284 size: 32 bit */ + /* Upper Threshold register 6 */ + ADC_THRHLR6_32B_tag THRHLR6; /* offset: 0x0288 size: 32 bit */ + /* Upper Threshold register 7 */ + ADC_THRHLR7_32B_tag THRHLR7; /* offset: 0x028C size: 32 bit */ + /* Upper Threshold register 8 */ + ADC_THRHLR8_32B_tag THRHLR8; /* offset: 0x0290 size: 32 bit */ + /* Upper Threshold register 9 */ + ADC_THRHLR9_32B_tag THRHLR9; /* offset: 0x0294 size: 32 bit */ + /* Upper Threshold register 10 */ + ADC_THRHLR10_32B_tag THRHLR10; /* offset: 0x0298 size: 32 bit */ + /* Upper Threshold register 11 */ + ADC_THRHLR11_32B_tag THRHLR11; /* offset: 0x029C size: 32 bit */ + /* Upper Threshold register 12 */ + ADC_THRHLR12_32B_tag THRHLR12; /* offset: 0x02A0 size: 32 bit */ + /* Upper Threshold register 13 */ + ADC_THRHLR13_32B_tag THRHLR13; /* offset: 0x02A4 size: 32 bit */ + /* Upper Threshold register 14 */ + ADC_THRHLR14_32B_tag THRHLR14; /* offset: 0x02A8 size: 32 bit */ + /* Upper Threshold register 15 */ + ADC_THRHLR15_32B_tag THRHLR15; /* offset: 0x02AC size: 32 bit */ + union { + /* Channel Watchdog Select register */ + ADC_CWSELR_32B_tag CWSELR[12]; /* offset: 0x02B0 (0x0004 x 12) */ + + struct { + /* Channel Watchdog Select register */ + ADC_CWSELR_32B_tag CWSELR0; /* offset: 0x02B0 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR1; /* offset: 0x02B4 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR2; /* offset: 0x02B8 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR3; /* offset: 0x02BC size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR4; /* offset: 0x02C0 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR5; /* offset: 0x02C4 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR6; /* offset: 0x02C8 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR7; /* offset: 0x02CC size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR8; /* offset: 0x02D0 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR9; /* offset: 0x02D4 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR10; /* offset: 0x02D8 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR11; /* offset: 0x02DC size: 32 bit */ + }; + + }; + union { + /* Channel Watchdog Enable Register */ + ADC_CWENR_32B_tag CWENR[3]; /* offset: 0x02E0 (0x0004 x 3) */ + + struct { + /* Channel Watchdog Enable Register */ + ADC_CWENR_32B_tag CWENR0; /* offset: 0x02E0 size: 32 bit */ + ADC_CWENR_32B_tag CWENR1; /* offset: 0x02E4 size: 32 bit */ + ADC_CWENR_32B_tag CWENR2; /* offset: 0x02E8 size: 32 bit */ + }; + + }; + int8_t ADC_reserved_02EC_C[4]; + union { + /* Analog Watchdog Out of Range Register */ + ADC_AWORR_32B_tag AWORR[3]; /* offset: 0x02F0 (0x0004 x 3) */ + + struct { + /* Analog Watchdog Out of Range Register */ + ADC_AWORR_32B_tag AWORR0; /* offset: 0x02F0 size: 32 bit */ + ADC_AWORR_32B_tag AWORR1; /* offset: 0x02F4 size: 32 bit */ + ADC_AWORR_32B_tag AWORR2; /* offset: 0x02F8 size: 32 bit */ + }; + + }; + int8_t ADC_reserved_02FC[68]; + /* SELF TEST CONFIGURATION REGISTER 1 */ + ADC_STCR1_32B_tag STCR1; /* offset: 0x0340 size: 32 bit */ + /* SELF TEST CONFIGURATION REGISTER 2 */ + ADC_STCR2_32B_tag STCR2; /* offset: 0x0344 size: 32 bit */ + /* SELF TEST CONFIGURATION REGISTER 3 */ + ADC_STCR3_32B_tag STCR3; /* offset: 0x0348 size: 32 bit */ + /* SELF TEST BAUD RATE REGISTER */ + ADC_STBRR_32B_tag STBRR; /* offset: 0x034C size: 32 bit */ + /* SELF TEST STATUS REGISTER 1 */ + ADC_STSR1_32B_tag STSR1; /* offset: 0x0350 size: 32 bit */ + /* SELF TEST STATUS REGISTER 2 */ + ADC_STSR2_32B_tag STSR2; /* offset: 0x0354 size: 32 bit */ + /* SELF TEST STATUS REGISTER 3 */ + ADC_STSR3_32B_tag STSR3; /* offset: 0x0358 size: 32 bit */ + /* SELF TEST STATUS REGISTER 4 */ + ADC_STSR4_32B_tag STSR4; /* offset: 0x035C size: 32 bit */ + int8_t ADC_reserved_0360[16]; + /* SELF TEST DATA REGISTER 1 */ + ADC_STDR1_32B_tag STDR1; /* offset: 0x0370 size: 32 bit */ + /* SELF TEST DATA REGISTER 2 */ + ADC_STDR2_32B_tag STDR2; /* offset: 0x0374 size: 32 bit */ + int8_t ADC_reserved_0378[8]; + /* SELF TEST ANALOG WATCHDOG REGISTER 0 */ + ADC_STAW0R_32B_tag STAW0R; /* offset: 0x0380 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 1A */ + ADC_STAW1AR_32B_tag STAW1AR; /* offset: 0x0384 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 1B */ + ADC_STAW1BR_32B_tag STAW1BR; /* offset: 0x0388 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 2 */ + ADC_STAW2R_32B_tag STAW2R; /* offset: 0x038C size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 3 */ + ADC_STAW3R_32B_tag STAW3R; /* offset: 0x0390 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 4 */ + ADC_STAW4R_32B_tag STAW4R; /* offset: 0x0394 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 5 */ + ADC_STAW5R_32B_tag STAW5R; /* offset: 0x0398 size: 32 bit */ + } ADC_tag; + + +#define ADC0 (*(volatile ADC_tag *) 0xFFE00000UL) +#define ADC1 (*(volatile ADC_tag *) 0xFFE04000UL) + + + +/****************************************************************/ +/* */ +/* Module: CTU */ +/* */ +/****************************************************************/ + + typedef union { /* Trigger Generator Subunit Input Selection register */ + uint32_t R; + struct { + uint32_t I15_FE:1; /* ext_signal Falling Edge */ + uint32_t I15_RE:1; /* ext_signal Rising Edge */ + uint32_t I14_FE:1; /* eTimer2 Falling Edge Enable */ + uint32_t I14_RE:1; /* eTimer2 Rising Edge Enable */ + uint32_t I13_FE:1; /* eTimer1 Falling Edge Enable */ + uint32_t I13_RE:1; /* eTimer1 Rising Edge Enable */ + uint32_t I12_FE:1; /* RPWM ch3 Falling Edge Enable */ + uint32_t I12_RE:1; /* RPWM ch3 Rising Edge Enable */ + uint32_t I11_FE:1; /* RPWM ch2 Falling Edge Enable */ + uint32_t I11_RE:1; /* RPWM ch2 Rising Edge Enable */ + uint32_t I10_FE:1; /* RPWM ch1 Falling Edge Enable */ + uint32_t I10_RE:1; /* RPWM ch1 Rising Edge Enable */ + uint32_t I9_FE:1; /* RPWM ch0 Falling Edge Enable */ + uint32_t I9_RE:1; /* RPWM ch0 Rising Edge Enable */ + uint32_t I8_FE:1; /* PWM ch3 even trig Falling edge Enable */ + uint32_t I8_RE:1; /* PWM ch3 even trig Rising edge Enable */ + uint32_t I7_FE:1; /* PWM ch2 even trig Falling edge Enable */ + uint32_t I7_RE:1; /* PWM ch2 even trig Rising edge Enable */ + uint32_t I6_FE:1; /* PWM ch1 even trig Falling edge Enable */ + uint32_t I6_RE:1; /* PWM ch1 even trig Rising edge Enable */ + uint32_t I5_FE:1; /* PWM ch0 even trig Falling edge Enable */ + uint32_t I5_RE:1; /* PWM ch0 even trig Rising edge Enable */ + uint32_t I4_FE:1; /* PWM ch3 odd trig Falling edge Enable */ + uint32_t I4_RE:1; /* PWM ch3 odd trig Rising edge Enable */ + uint32_t I3_FE:1; /* PWM ch2 odd trig Falling edge Enable */ + uint32_t I3_RE:1; /* PWM ch2 odd trig Rising edge Enable */ + uint32_t I2_FE:1; /* PWM ch1 odd trig Falling edge Enable */ + uint32_t I2_RE:1; /* PWM ch1 odd trig Rising edge Enable */ + uint32_t I1_FE:1; /* PWM ch0 odd trig Falling edge Enable */ + uint32_t I1_RE:1; /* PWM ch0 odd trig Rising edge Enable */ + uint32_t I0_FE:1; /* PWM Reload Falling Edge Enable */ + uint32_t I0_RE:1; /* PWM Reload Rising Edge Enable */ + } B; + } CTU_TGSISR_32B_tag; + + typedef union { /* Trigger Generator Subunit Control Register */ + uint16_t R; + struct { + uint16_t:7; +#ifndef USE_FIELD_ALIASES_CTU + uint16_t ET_TM:1; /* Toggle Mode Enable */ +#else + uint16_t ETTM:1; /* deprecated name - please avoid */ +#endif + uint16_t PRES:2; /* TGS Prescaler Selection */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_SM:5; /* MRS Selection in Sequential Mode */ +#else + uint16_t MRSSM:5; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t TGS_M:1; /* Trigger Generator Subunit Mode */ +#else + uint16_t TGSM:1; /* deprecated name - please avoid */ +#endif + } B; + } CTU_TGSCR_16B_tag; + + typedef union { /* */ + uint16_t R; + } CTU_TCR_16B_tag; + + typedef union { /* TGS Counter Compare Register */ + uint16_t R; +#ifndef USE_FIELD_ALIASES_CTU + struct { + uint16_t TGSCCV:16; /* deprecated field -- do not use */ + } B; +#endif + } CTU_TGSCCR_16B_tag; + + typedef union { /* TGS Counter Reload Register */ + uint16_t R; +#ifndef USE_FIELD_ALIASES_CTU + struct { + uint16_t TGSCRV:16; /* deprecated field -- do not use */ + } B; +#endif + } CTU_TGSCRR_16B_tag; + + typedef union { /* Commands List Control Register 1 */ + uint32_t R; + struct { + uint32_t:3; + uint32_t T3INDEX:5; /* Trigger 3 First Command address */ + uint32_t:3; + uint32_t T2INDEX:5; /* Trigger 2 First Command address */ + uint32_t:3; + uint32_t T1INDEX:5; /* Trigger 1 First Command address */ + uint32_t:3; + uint32_t T0INDEX:5; /* Trigger 0 First Command address */ + } B; + } CTU_CLCR1_32B_tag; + + typedef union { /* Commands List Control Register 2 */ + uint32_t R; + struct { + uint32_t:3; + uint32_t T7INDEX:5; /* Trigger 7 First Command address */ + uint32_t:3; + uint32_t T6INDEX:5; /* Trigger 6 First Command address */ + uint32_t:3; + uint32_t T5INDEX:5; /* Trigger 5 First Command address */ + uint32_t:3; + uint32_t T4INDEX:5; /* Trigger 4 First Command address */ + } B; + } CTU_CLCR2_32B_tag; + + typedef union { /* Trigger Handler Control Register 1 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t T3_E:1; /* Trigger 3 enable */ + uint32_t T3_ETE:1; /* Trigger 3 Ext Trigger output enable */ + uint32_t T3_T4E:1; /* Trigger 3 Timer4 output enable */ + uint32_t T3_T3E:1; /* Trigger 3 Timer3 output enable */ + uint32_t T3_T2E:1; /* Trigger 3 Timer2 output enable */ + uint32_t T3_T1E:1; /* Trigger 3 Timer1 output enable */ + uint32_t T3_ADCE:1; /* Trigger 3 ADC Command output enable */ + uint32_t:1; + uint32_t T2_E:1; /* Trigger 2 enable */ + uint32_t T2_ETE:1; /* Trigger 2 Ext Trigger output enable */ + uint32_t T2_T4E:1; /* Trigger 2 Timer4 output enable */ + uint32_t T2_T3E:1; /* Trigger 2 Timer3 output enable */ + uint32_t T2_T2E:1; /* Trigger 2 Timer2 output enable */ + uint32_t T2_T1E:1; /* Trigger 2 Timer1 output enable */ + uint32_t T2_ADCE:1; /* Trigger 2 ADC Command output enable */ + uint32_t:1; + uint32_t T1_E:1; /* Trigger 1 enable */ + uint32_t T1_ETE:1; /* Trigger 1 Ext Trigger output enable */ + uint32_t T1_T4E:1; /* Trigger 1 Timer4 output enable */ + uint32_t T1_T3E:1; /* Trigger 1 Timer3 output enable */ + uint32_t T1_T2E:1; /* Trigger 1 Timer2 output enable */ + uint32_t T1_T1E:1; /* Trigger 1 Timer1 output enable */ + uint32_t T1_ADCE:1; /* Trigger 1 ADC Command output enable */ + uint32_t:1; + uint32_t T0_E:1; /* Trigger 0 enable */ + uint32_t T0_ETE:1; /* Trigger 0 Ext Trigger output enable */ + uint32_t T0_T4E:1; /* Trigger 0 Timer4 output enable */ + uint32_t T0_T3E:1; /* Trigger 0 Timer3 output enable */ + uint32_t T0_T2E:1; /* Trigger 0 Timer2 output enable */ + uint32_t T0_T1E:1; /* Trigger 0 Timer1 output enable */ + uint32_t T0_ADCE:1; /* Trigger 0 ADC Command output enable */ + } B; + } CTU_THCR1_32B_tag; + + typedef union { /* Trigger Handler Control Register 2 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t T7_E:1; /* Trigger 7 enable */ + uint32_t T7_ETE:1; /* Trigger 7 Ext Trigger output enable */ + uint32_t T7_T4E:1; /* Trigger 7 Timer4 output enable */ + uint32_t T7_T3E:1; /* Trigger 7 Timer3 output enable */ + uint32_t T7_T2E:1; /* Trigger 7 Timer2 output enable */ + uint32_t T7_T1E:1; /* Trigger 7 Timer1 output enable */ + uint32_t T7_ADCE:1; /* Trigger 7 ADC Command output enable */ + uint32_t:1; + uint32_t T6_E:1; /* Trigger 6 enable */ + uint32_t T6_ETE:1; /* Trigger 6 Ext Trigger output enable */ + uint32_t T6_T4E:1; /* Trigger 6 Timer4 output enable */ + uint32_t T6_T3E:1; /* Trigger 6 Timer3 output enable */ + uint32_t T6_T2E:1; /* Trigger 6 Timer2 output enable */ + uint32_t T6_T1E:1; /* Trigger 6 Timer1 output enable */ + uint32_t T6_ADCE:1; /* Trigger 6 ADC Command output enable */ + uint32_t:1; + uint32_t T5_E:1; /* Trigger 5 enable */ + uint32_t T5_ETE:1; /* Trigger 5 Ext Trigger output enable */ + uint32_t T5_T4E:1; /* Trigger 5 Timer4 output enable */ + uint32_t T5_T3E:1; /* Trigger 5 Timer3 output enable */ + uint32_t T5_T2E:1; /* Trigger 5 Timer2 output enable */ + uint32_t T5_T1E:1; /* Trigger 5 Timer1 output enable */ + uint32_t T5_ADCE:1; /* Trigger 5 ADC Command output enable */ + uint32_t:1; + uint32_t T4_E:1; /* Trigger 4 enable */ + uint32_t T4_ETE:1; /* Trigger 4 Ext Trigger output enable */ + uint32_t T4_T4E:1; /* Trigger 4 Timer4 output enable */ + uint32_t T4_T3E:1; /* Trigger 4 Timer3 output enable */ + uint32_t T4_T2E:1; /* Trigger 4 Timer2 output enable */ + uint32_t T4_T1E:1; /* Trigger 4 Timer1 output enable */ + uint32_t T4_ADCE:1; /* Trigger 4 ADC Command output enable */ + } B; + } CTU_THCR2_32B_tag; + + + /* Register layout for all registers CLR_DCM... */ + + typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ + uint16_t R; + struct { + uint16_t CIR:1; /* Command Interrupt Request */ + uint16_t LC:1; /* Last Command */ + uint16_t CMS:1; /* Conversion Mode Selection */ + uint16_t FIFO:3; /* FIFO for ADC A/B */ + uint16_t:1; + uint16_t CHB:4; /* ADC unit B channel number */ + uint16_t:1; + uint16_t CHA:4; /* ADC unit A channel number */ + } B; + } CTU_CLR_DCM_16B_tag; + + + /* Register layout for all registers CLR_SCM... */ + + typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ + uint16_t R; + struct { + uint16_t CIR:1; /* Command Interrupt Request */ + uint16_t LC:1; /* Last Command */ + uint16_t CMS:1; /* Conversion Mode Selection */ + uint16_t FIFO:3; /* FIFO for ADC A/B */ + uint16_t:4; + uint16_t SU:1; /* Selection ADC Unit */ + uint16_t:1; + uint16_t CH:4; /* ADC unit channel number */ + } B; + } CTU_CLR_SCM_16B_tag; + + + /* Register layout for all registers CLR... */ + + + typedef union { /* Control Register */ + uint16_t R; + struct { + uint16_t EMPTY_CLR7:1; /* Empty Clear 7 */ + uint16_t EMPTY_CLR6:1; /* Empty Clear 6 */ + uint16_t EMPTY_CLR5:1; /* Empty Clear 5 */ + uint16_t EMPTY_CLR4:1; /* Empty Clear 4 */ + uint16_t EMPTY_CLR3:1; /* Empty Clear 3 */ + uint16_t EMPTY_CLR2:1; /* Empty Clear 2 */ + uint16_t EMPTY_CLR1:1; /* Empty Clear 1 */ + uint16_t EMPTY_CLR0:1; /* Empty Clear 0 */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN7:1; /* Enable DMA interface for FIFO 7 */ +#else + uint16_t DMAEN7:1; /* Enable DMA interface for FIFO 7 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN6:1; /* Enable DMA interface for FIFO 6 */ +#else + uint16_t DMAEN6:1; /* Enable DMA interface for FIFO 6 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN5:1; /* Enable DMA interface for FIFO 5 */ +#else + uint16_t DMAEN5:1; /* Enable DMA interface for FIFO 5 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN4:1; /* Enable DMA interface for FIFO 4 */ +#else + uint16_t DMAEN4:1; /* Enable DMA interface for FIFO 4 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN3:1; /* Enable DMA interface for FIFO 3 */ +#else + uint16_t DMAEN3:1; /* Enable DMA interface for FIFO 3 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN2:1; /* Enable DMA interface for FIFO 2 */ +#else + uint16_t DMAEN2:1; /* Enable DMA interface for FIFO 2 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN1:1; /* Enable DMA interface for FIFO 1 */ +#else + uint16_t DMAEN1:1; /* Enable DMA interface for FIFO 1 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN0:1; /* Enable DMA interface for FIFO 0 */ +#else + uint16_t DMAEN0:1; /* Enable DMA interface for FIFO 0 */ +#endif + } B; + } CTU_CR_16B_tag; + + typedef union { /* Control Register FIFO */ + uint32_t R; + struct { + uint32_t FIFO_OVERRUN_EN7:1; /* FIFO 7 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN7:1; /* FIFO 7 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN7:1; /* FIFO 7 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN7:1; /* FIFO 7 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN6:1; /* FIFO 6 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN6:1; /* FIFO 6 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN6:1; /* FIFO 6 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN6:1; /* FIFO 6 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN5:1; /* FIFO 5 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN5:1; /* FIFO 5 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN5:1; /* FIFO 5 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN5:1; /* FIFO 5 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN4:1; /* FIFO 4 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN4:1; /* FIFO 4 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN4:1; /* FIFO 4 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN4:1; /* FIFO 4 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN3:1; /* FIFO 3 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN3:1; /* FIFO 3 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN3:1; /* FIFO 3 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN3:1; /* FIFO 3 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN2:1; /* FIFO 2 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN2:1; /* FIFO 2 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN2:1; /* FIFO 2 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN2:1; /* FIFO 2 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN1:1; /* FIFO 1 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN1:1; /* FIFO 1 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN1:1; /* FIFO 1 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN1:1; /* FIFO 1 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN0:1; /* FIFO 0 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN0:1; /* FIFO 0 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN0:1; /* FIFO 0 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN0:1; /* FIFO 0 FULL Enable Interrupt */ + } B; + } CTU_FCR_32B_tag; + + typedef union { /* Threshold 1 Register */ + uint32_t R; + struct { + uint32_t THRESHOLD3:8; /* Threshlod FIFO 3 */ + uint32_t THRESHOLD2:8; /* Threshlod FIFO 2 */ + uint32_t THRESHOLD1:8; /* Threshlod FIFO 1 */ + uint32_t THRESHOLD0:8; /* Threshlod FIFO 0 */ + } B; + } CTU_TH1_32B_tag; + + typedef union { /* Threshold 2 Register */ + uint32_t R; + struct { + uint32_t THRESHOLD7:8; /* Threshlod FIFO 7 */ + uint32_t THRESHOLD6:8; /* Threshlod FIFO 6 */ + uint32_t THRESHOLD5:8; /* Threshlod FIFO 5 */ + uint32_t THRESHOLD4:8; /* Threshlod FIFO 4 */ + } B; + } CTU_TH2_32B_tag; + + typedef union { /* Status Register */ + uint32_t R; + struct { + uint32_t FIFO_OVERRUN7:1; /* FIFO 7 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW7:1; /* FIFO 7 OVERFLOW Flag */ + uint32_t FIFO_EMPTY7:1; /* FIFO 7 EMPTY Flag */ + uint32_t FIFO_FULL7:1; /* FIFO 7 FULL Flag */ + uint32_t FIFO_OVERRUN6:1; /* FIFO 6 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW6:1; /* FIFO 6 OVERFLOW Flag */ + uint32_t FIFO_EMPTY6:1; /* FIFO 6 EMPTY Flag */ + uint32_t FIFO_FULL6:1; /* FIFO 6 FULL Flag */ + uint32_t FIFO_OVERRUN5:1; /* FIFO 5 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW5:1; /* FIFO 5 OVERFLOW Flag */ + uint32_t FIFO_EMPTY5:1; /* FIFO 5 EMPTY Flag */ + uint32_t FIFO_FULL5:1; /* FIFO 5 FULL Flag */ + uint32_t FIFO_OVERRUN4:1; /* FIFO 4 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW4:1; /* FIFO 4 OVERFLOW Flag */ + uint32_t FIFO_EMPTY4:1; /* FIFO 4 EMPTY Flag */ + uint32_t FIFO_FULL4:1; /* FIFO 4 FULL Flag */ + uint32_t FIFO_OVERRUN3:1; /* FIFO 3 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW3:1; /* FIFO 3 OVERFLOW Flag */ + uint32_t FIFO_EMPTY3:1; /* FIFO 3 EMPTY Flag */ + uint32_t FIFO_FULL3:1; /* FIFO 3 FULL Flag */ + uint32_t FIFO_OVERRUN2:1; /* FIFO 2 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW2:1; /* FIFO 2 OVERFLOW Flag */ + uint32_t FIFO_EMPTY2:1; /* FIFO 2 EMPTY Flag */ + uint32_t FIFO_FULL2:1; /* FIFO 2 FULL Flag */ + uint32_t FIFO_OVERRUN1:1; /* FIFO 1 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW1:1; /* FIFO 1 OVERFLOW Flag */ + uint32_t FIFO_EMPTY1:1; /* FIFO 1 EMPTY Flag */ + uint32_t FIFO_FULL1:1; /* FIFO 1 FULL Flag */ + uint32_t FIFO_OVERRUN0:1; /* FIFO 0 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW0:1; /* FIFO 0 OVERFLOW Flag */ + uint32_t FIFO_EMPTY0:1; /* FIFO 0 EMPTY Flag */ + uint32_t FIFO_FULL0:1; /* FIFO 0 FULL Flag */ + } B; + } CTU_STS_32B_tag; + + + /* Register layout for all registers FR... */ + + typedef union { /* FIFO Right Aligned register */ + uint32_t R; + struct { + uint32_t:11; + uint32_t ADC:1; /* ADC Unit */ + uint32_t N_CH:4; /* Number Channel */ + uint32_t:4; + uint32_t DATA:12; /* Data Fifo */ + } B; + } CTU_FR_32B_tag; + + + /* Register layout for all registers FL... */ + + typedef union { /* FIFO Left Aligned register */ + uint32_t R; + struct { + uint32_t:11; + uint32_t ADC:1; /* ADC Unit */ + uint32_t N_CH:4; /* Number Channel */ + uint32_t:1; + uint32_t DATA:12; /* Data Fifo */ + uint32_t:3; + } B; + } CTU_FL_32B_tag; + + typedef union { /* CTU Error Flag Register */ + uint16_t R; + struct { + uint16_t:3; + uint16_t CS:1; /* Counter Status */ + uint16_t ET_OE:1; /* ExtTrigger Generation Overrun */ + uint16_t ERR_CMP:1; /* Set if counter reaches TGSCCR register */ + uint16_t T4_OE:1; /* Timer4 Generation Overrun */ + uint16_t T3_OE:1; /* Timer3 Generation Overrun */ + uint16_t T2_OE:1; /* Timer2 Generation Overrun */ + uint16_t T1_OE:1; /* Timer1 Generation Overrun */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t ADC_OE:1; /* ADC Command Generation Overrun */ +#else + uint16_t ADCOE:1; /* ADC Command Generation Overrun */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t TGS_OSM:1; /* TGS Overrun */ +#else + uint16_t TGSOSM:1; /* TGS Overrun */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_O:1; /* MRS Overrun */ +#else + uint16_t MRSO:1; /* TGS Overrun */ +#endif + uint16_t ICE:1; /* Invalid Command Error */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t SM_TO:1; /* Trigger Overrun */ +#else + uint16_t SMTO:1; /* Trigger Overrun */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_RE:1; /* MRS Reload Error */ +#else + uint16_t MRSRE:1; /* MRS Reload Error */ +#endif + } B; + } CTU_CTUEFR_16B_tag; + + typedef union { /* CTU Interrupt Flag Register */ + uint16_t R; + struct { + uint16_t:4; + uint16_t S_E_B:1; /* Slice time OK */ + uint16_t S_E_A:1; /* Slice time OK */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t ADC_I:1; /* ADC Command Interrupt Flag */ +#else + uint16_t ADC:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T7_I:1; /* Trigger 7 Interrupt Flag */ +#else + uint16_t T7:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T6_I:1; /* Trigger 6 Interrupt Flag */ +#else + uint16_t T6:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T5_I:1; /* Trigger 5 Interrupt Flag */ +#else + uint16_t T5:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T4_I:1; /* Trigger 4 Interrupt Flag */ +#else + uint16_t T4:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T3_I:1; /* Trigger 3 Interrupt Flag */ +#else + uint16_t T3:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T2_I:1; /* Trigger 2 Interrupt Flag */ +#else + uint16_t T2:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T1_I:1; /* Trigger 1 Interrupt Flag */ +#else + uint16_t T1:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T0_I:1; /* Trigger 0 Interrupt Flag */ +#else + uint16_t T0:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_I:1; /* MRS Interrupt Flag */ +#else + uint16_t MRS:1; +#endif + } B; + } CTU_CTUIFR_16B_tag; + + typedef union { /* CTU Interrupt/DMA Register */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T7_I:1; /* Trigger 7 Interrupt Enable */ +#else + uint16_t T7IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T6_I:1; /* Trigger 6 Interrupt Enable */ +#else + uint16_t T6IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T5_I:1; /* Trigger 5 Interrupt Enable */ +#else + uint16_t T5IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T4_I:1; /* Trigger 4 Interrupt Enable */ +#else + uint16_t T4IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T3_I:1; /* Trigger 3 Interrupt Enable */ +#else + uint16_t T3IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T2_I:1; /* Trigger 2 Interrupt Enable */ +#else + uint16_t T2IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T1_I:1; /* Trigger 1 Interrupt Enable */ +#else + uint16_t T1IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T0_I:1; /* Trigger 0 Interrupt Enable */ +#else + uint16_t T0IE:1; +#endif + uint16_t:2; + uint16_t SAF_CNT_B_EN:1; /* Conversion time counter enabled */ + uint16_t SAF_CNT_A_EN:1; /* Conversion time counter enabled */ + uint16_t DMA_DE:1; /* DMA and gre bit */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_DMAE:1; /* DMA Transfer Enable */ +#else + uint16_t MRSDMAE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_IE:1; /* MRS Interrupt Enable */ +#else + uint16_t MRSIE:1; +#endif + uint16_t IEE:1; /* Interrupt Error Enable */ + } B; + } CTU_CTUIR_16B_tag; + + typedef union { /* Control On-Time Register */ + uint16_t R; + struct { + uint16_t:8; +#ifndef USE_FIELD_ALIASES_CTU + uint16_t COTR_COTR:8; /* Control On-Time Register and Guard Time */ +#else + uint16_t COTR:8; +#endif + } B; + } CTU_COTR_16B_tag; + + typedef union { /* CTU Control Register */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T7_SG:1; /* Trigger 7 Software Generated */ +#else + uint16_t T7SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T6_SG:1; /* Trigger 6 Software Generated */ +#else + uint16_t T6SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T5_SG:1; /* Trigger 5 Software Generated */ +#else + uint16_t T5SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T4_SG:1; /* Trigger 4 Software Generated */ +#else + uint16_t T4SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T3_SG:1; /* Trigger 3 Software Generated */ +#else + uint16_t T3SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T2_SG:1; /* Trigger 2 Software Generated */ +#else + uint16_t T2SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T1_SG:1; /* Trigger 1 Software Generated */ +#else + uint16_t T1SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T0_SG:1; /* Trigger 0 Software Generated */ +#else + uint16_t T0SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t CTU_ADC_RESET:1; /* CTU ADC State Machine Reset */ +#else + uint16_t CTUADCRESET:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t CTU_ODIS:1; /* CTU Output Disable */ +#else + uint16_t CTUODIS:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t FILTER_EN:1; /* Synchronize Filter Register value */ +#else + uint16_t FILTERENABLE:1; +#endif + uint16_t CGRE:1; /* Clear GRE */ + uint16_t FGRE:1; /* GRE Flag */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_SG:1; /* MRS Software Generated */ +#else + uint16_t MRSSG:1; +#endif + uint16_t GRE:1; /* General Reload Enable */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t TGSISR_RE:1; /* TGSISR Reload Enable */ +#else + uint16_t TGSISRRE:1; +#endif + } B; + } CTU_CTUCR_16B_tag; + + typedef union { /* CTU Digital Filter Register */ + uint16_t R; + struct { + uint16_t:8; +#ifndef USE_FIELD_ALIASES_CTU + uint16_t FILTER_VALUE:8; /* Filter Value */ +#else + uint16_t FILTERVALUE:8; /* deprecated name - please avoid */ +#endif + } B; + } CTU_FILTER_16B_tag; + + typedef union { /* CTU Expected A Value Register */ + uint16_t R; + struct { + uint16_t EXPECTED_A_VALUE:16; /* Expected A Value */ + } B; + } CTU_EXPECTED_A_16B_tag; + + typedef union { /* CTU Expected B Value Register */ + uint16_t R; + struct { + uint16_t EXPECTED_B_VALUE:16; /* Expected B Value */ + } B; + } CTU_EXPECTED_B_16B_tag; + + typedef union { /* CTU Counter Range Register */ + uint16_t R; + struct { + uint16_t:8; + uint16_t CNT_RANGE_VALUE:8; /* Counter Range Value */ + } B; + } CTU_CNT_RANGE_16B_tag; + + + /* Register layout for generated register(s) FRA... */ + + typedef union { /* */ + uint32_t R; + } CTU_FRA_32B_tag; + + + /* Register layout for generated register(s) FLA... */ + + typedef union { /* */ + uint32_t R; + } CTU_FLA_32B_tag; + + + + typedef struct CTU_struct_tag { /* start of CTU_tag */ + /* Trigger Generator Subunit Input Selection register */ + CTU_TGSISR_32B_tag TGSISR; /* offset: 0x0000 size: 32 bit */ + /* Trigger Generator Subunit Control Register */ + CTU_TGSCR_16B_tag TGSCR; /* offset: 0x0004 size: 16 bit */ + union { + CTU_TCR_16B_tag TCR[8]; /* offset: 0x0006 (0x0002 x 8) */ + + struct { + CTU_TCR_16B_tag T0CR; /* offset: 0x0006 size: 16 bit */ + CTU_TCR_16B_tag T1CR; /* offset: 0x0008 size: 16 bit */ + CTU_TCR_16B_tag T2CR; /* offset: 0x000A size: 16 bit */ + CTU_TCR_16B_tag T3CR; /* offset: 0x000C size: 16 bit */ + CTU_TCR_16B_tag T4CR; /* offset: 0x000E size: 16 bit */ + CTU_TCR_16B_tag T5CR; /* offset: 0x0010 size: 16 bit */ + CTU_TCR_16B_tag T6CR; /* offset: 0x0012 size: 16 bit */ + CTU_TCR_16B_tag T7CR; /* offset: 0x0014 size: 16 bit */ + }; + + }; + /* TGS Counter Compare Register */ + CTU_TGSCCR_16B_tag TGSCCR; /* offset: 0x0016 size: 16 bit */ + /* TGS Counter Reload Register */ + CTU_TGSCRR_16B_tag TGSCRR; /* offset: 0x0018 size: 16 bit */ + int8_t CTU_reserved_001A[2]; + /* Commands List Control Register 1 */ + CTU_CLCR1_32B_tag CLCR1; /* offset: 0x001C size: 32 bit */ + /* Commands List Control Register 2 */ + CTU_CLCR2_32B_tag CLCR2; /* offset: 0x0020 size: 32 bit */ + /* Trigger Handler Control Register 1 */ + CTU_THCR1_32B_tag THCR1; /* offset: 0x0024 size: 32 bit */ + /* Trigger Handler Control Register 2 */ + CTU_THCR2_32B_tag THCR2; /* offset: 0x0028 size: 32 bit */ + union { + /* Command List Register. View: BIT13, BIT9 */ + CTU_CLR_SCM_16B_tag CLR[24]; /* offset: 0x002C (0x0002 x 24) */ /* deprecated name - please avoid */ + + /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ + CTU_CLR_SCM_16B_tag CLR_SCM[24]; /* offset: 0x002C (0x0002 x 24) */ + + /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ + CTU_CLR_DCM_16B_tag CLR_DCM[24]; /* offset: 0x002C (0x0002 x 24) */ + + struct { + /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ + CTU_CLR_SCM_16B_tag CLR_SCM1; /* offset: 0x002C size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM2; /* offset: 0x002E size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM3; /* offset: 0x0030 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM4; /* offset: 0x0032 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM5; /* offset: 0x0034 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM6; /* offset: 0x0036 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM7; /* offset: 0x0038 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM8; /* offset: 0x003A size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM9; /* offset: 0x003C size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM10; /* offset: 0x003E size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM11; /* offset: 0x0040 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM12; /* offset: 0x0042 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM13; /* offset: 0x0044 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM14; /* offset: 0x0046 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM15; /* offset: 0x0048 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM16; /* offset: 0x004A size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM17; /* offset: 0x004C size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM18; /* offset: 0x004E size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM19; /* offset: 0x0050 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM20; /* offset: 0x0052 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM21; /* offset: 0x0054 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM22; /* offset: 0x0056 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM23; /* offset: 0x0058 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM24; /* offset: 0x005A size: 16 bit */ + }; + + struct { + /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ + CTU_CLR_DCM_16B_tag CLR_DCM1; /* offset: 0x002C size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM2; /* offset: 0x002E size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM3; /* offset: 0x0030 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM4; /* offset: 0x0032 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM5; /* offset: 0x0034 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM6; /* offset: 0x0036 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM7; /* offset: 0x0038 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM8; /* offset: 0x003A size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM9; /* offset: 0x003C size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM10; /* offset: 0x003E size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM11; /* offset: 0x0040 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM12; /* offset: 0x0042 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM13; /* offset: 0x0044 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM14; /* offset: 0x0046 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM15; /* offset: 0x0048 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM16; /* offset: 0x004A size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM17; /* offset: 0x004C size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM18; /* offset: 0x004E size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM19; /* offset: 0x0050 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM20; /* offset: 0x0052 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM21; /* offset: 0x0054 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM22; /* offset: 0x0056 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM23; /* offset: 0x0058 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM24; /* offset: 0x005A size: 16 bit */ + }; + + }; + int8_t CTU_reserved_005C[16]; + /* Control Register */ + CTU_CR_16B_tag CR; /* offset: 0x006C size: 16 bit */ + int8_t CTU_reserved_006E[2]; + /* Control Register FIFO */ + CTU_FCR_32B_tag FCR; /* offset: 0x0070 size: 32 bit */ + /* Threshold 1 Register */ + CTU_TH1_32B_tag TH1; /* offset: 0x0074 size: 32 bit */ + /* Threshold 2 Register */ + CTU_TH2_32B_tag TH2; /* offset: 0x0078 size: 32 bit */ + union { + /* Status Register */ + CTU_STS_32B_tag STS; /* offset: 0x007C size: 32 bit */ + + CTU_STS_32B_tag STATUS; /* deprecated - please avoid */ + + }; + union { + CTU_FRA_32B_tag FRA[8]; /* offset: 0x0080 (0x0004 x 8) */ + + /* FIFO Right Aligned register */ + CTU_FR_32B_tag FR[8]; /* offset: 0x0080 (0x0004 x 8) */ + + struct { + /* FIFO Right Aligned register */ + CTU_FR_32B_tag FR0; /* offset: 0x0080 size: 32 bit */ + CTU_FR_32B_tag FR1; /* offset: 0x0084 size: 32 bit */ + CTU_FR_32B_tag FR2; /* offset: 0x0088 size: 32 bit */ + CTU_FR_32B_tag FR3; /* offset: 0x008C size: 32 bit */ + CTU_FR_32B_tag FR4; /* offset: 0x0090 size: 32 bit */ + CTU_FR_32B_tag FR5; /* offset: 0x0094 size: 32 bit */ + CTU_FR_32B_tag FR6; /* offset: 0x0098 size: 32 bit */ + CTU_FR_32B_tag FR7; /* offset: 0x009C size: 32 bit */ + }; + + }; + union { + CTU_FLA_32B_tag FLA[8]; /* offset: 0x00A0 (0x0004 x 8) */ + + /* FIFO Left Aligned register */ + CTU_FL_32B_tag FL[8]; /* offset: 0x00A0 (0x0004 x 8) */ + + struct { + /* FIFO Left Aligned register */ + CTU_FL_32B_tag FL0; /* offset: 0x00A0 size: 32 bit */ + CTU_FL_32B_tag FL1; /* offset: 0x00A4 size: 32 bit */ + CTU_FL_32B_tag FL2; /* offset: 0x00A8 size: 32 bit */ + CTU_FL_32B_tag FL3; /* offset: 0x00AC size: 32 bit */ + CTU_FL_32B_tag FL4; /* offset: 0x00B0 size: 32 bit */ + CTU_FL_32B_tag FL5; /* offset: 0x00B4 size: 32 bit */ + CTU_FL_32B_tag FL6; /* offset: 0x00B8 size: 32 bit */ + CTU_FL_32B_tag FL7; /* offset: 0x00BC size: 32 bit */ + }; + + }; + /* CTU Error Flag Register */ + CTU_CTUEFR_16B_tag CTUEFR; /* offset: 0x00C0 size: 16 bit */ + /* CTU Interrupt Flag Register */ + CTU_CTUIFR_16B_tag CTUIFR; /* offset: 0x00C2 size: 16 bit */ + /* CTU Interrupt/DMA Register */ + CTU_CTUIR_16B_tag CTUIR; /* offset: 0x00C4 size: 16 bit */ + /* Control On-Time Register */ + CTU_COTR_16B_tag COTR; /* offset: 0x00C6 size: 16 bit */ + /* CTU Control Register */ + CTU_CTUCR_16B_tag CTUCR; /* offset: 0x00C8 size: 16 bit */ + union { + /* CTU Digital Filter Register */ + CTU_FILTER_16B_tag FILTER; /* offset: 0x00CA size: 16 bit */ + + CTU_FILTER_16B_tag CTUFILTER; /* deprecated - please avoid */ + + }; + /* CTU Expected A Value Register */ + CTU_EXPECTED_A_16B_tag EXPECTED_A; /* offset: 0x00CC size: 16 bit */ + + /* CTU Expected B Value Register */ + CTU_EXPECTED_B_16B_tag EXPECTED_B; /* offset: 0x00CE size: 16 bit */ + /* CTU Counter Range Register */ + CTU_CNT_RANGE_16B_tag CNT_RANGE; /* offset: 0x00D0 size: 16 bit */ + } CTU_tag; + + +#define CTU (*(volatile CTU_tag *) 0xFFE0C000UL) + + + +/****************************************************************/ +/* */ +/* Module: mcTIMER */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers COMP1... */ + + typedef union { /* Compare Register 1 */ + uint16_t R; + struct { + uint16_t COMP1:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_COMP1_16B_tag; + + + /* Register layout for all registers COMP2... */ + + typedef union { /* Compare Register 2 */ + uint16_t R; + struct { + uint16_t COMP2:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_COMP2_16B_tag; + + + /* Register layout for all registers CAPT1... */ + + typedef union { /* Capture Register 1 */ + uint16_t R; + struct { + uint16_t CAPT1:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CAPT1_16B_tag; + + + /* Register layout for all registers CAPT2... */ + + typedef union { /* Capture Register 2 */ + uint16_t R; + struct { + uint16_t CAPT2:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CAPT2_16B_tag; + + + /* Register layout for all registers LOAD... */ + + typedef union { /* Load Register */ + uint16_t R; + struct { + uint16_t LOAD:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_LOAD_16B_tag; + + + /* Register layout for all registers HOLD... */ + + typedef union { /* Hold Register */ + uint16_t R; + struct { + uint16_t HOLD:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_HOLD_16B_tag; + + + /* Register layout for all registers CNTR... */ + + typedef union { /* Counter Register */ + uint16_t R; + struct { + uint16_t CNTR:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CNTR_16B_tag; + + + /* Register layout for all registers CTRL1... */ + + typedef union { /* Control Register */ + uint16_t R; + struct { + uint16_t CNTMODE:3; /* Count Mode */ + uint16_t PRISRC:5; /* Primary Count Source */ + uint16_t ONCE:1; /* Count Once */ + uint16_t LENGTH:1; /* Count Length */ + uint16_t DIR:1; /* Count Direction */ + uint16_t SECSRC:5; /* Secondary Count Source */ + } B; + } mcTIMER_CTRL1_16B_tag; + + + /* Register layout for all registers CTRL2... */ + + typedef union { /* Control Register 2 */ + uint16_t R; + struct { + uint16_t OEN:1; /* Output Enable */ + uint16_t RDNT:1; /* Redundant Channel Enable */ + uint16_t INPUT:1; /* External Input Signal */ + uint16_t VAL:1; /* Forced OFLAG Value */ + uint16_t FORCE:1; /* Force the OFLAG output */ + uint16_t COFRC:1; /* Co-channel OFLAG Force */ + uint16_t COINIT:2; /* Co-channel Initialization */ + uint16_t SIPS:1; /* Secondary Source Input Polarity Select */ + uint16_t PIPS:1; /* Primary Source Input Polarity Select */ + uint16_t OPS:1; /* Output Polarity Select */ + uint16_t MSTR:1; /* Master Mode */ + uint16_t OUTMODE:4; /* Output Mode */ + } B; + } mcTIMER_CTRL2_16B_tag; + + + /* Register layout for all registers CTRL3... */ + + typedef union { /* Control Register 3 */ + uint16_t R; + struct { + uint16_t STPEN:1; /* Stop Action Enable */ + uint16_t ROC:2; /* Reload On Capture */ + uint16_t FMODE:1; /* Fault Safing Mode */ + uint16_t FDIS:4; /* Fault Disable Mask */ + uint16_t C2FCNT:3; /* CAPT2 FIFO Word Count */ + uint16_t C1FCNT:3; /* CAPT1 FIFO Word Count */ + uint16_t DBGEN:2; /* Debug Actions Enable */ + } B; + } mcTIMER_CTRL3_16B_tag; + + + /* Register layout for all registers STS... */ + + typedef union { /* Status Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t WDF:1; /* Watchdog Time-out Flag */ + uint16_t RCF:1; /* Redundant Channel Flag */ + uint16_t ICF2:1; /* Input Capture 2 Flag */ + uint16_t ICF1:1; /* Input Capture 1 Flag */ + uint16_t IEHF:1; /* Input Edge High Flag */ + uint16_t IELF:1; /* Input Edge Low Flag */ + uint16_t TOF:1; /* Timer Overflow Flag */ + uint16_t TCF2:1; /* Timer Compare 2 Flag */ + uint16_t TCF1:1; /* Timer Compare 1 Flag */ + uint16_t TCF:1; /* Timer Compare Flag */ + } B; + } mcTIMER_STS_16B_tag; + + + /* Register layout for all registers INTDMA... */ + + typedef union { /* Interrupt and DMA Enable Register */ + uint16_t R; + struct { + uint16_t ICF2DE:1; /* Input Capture 2 Flag DMA Enable */ + uint16_t ICF1DE:1; /* Input Capture 1 Flag DMA Enable */ + uint16_t CMPLD2DE:1; /* Comparator Load Register 2 Flag DMA Enable */ + uint16_t CMPLD1DE:1; /* Comparator Load Register 1 Flag DMA Enable */ + uint16_t:2; + uint16_t WDFIE:1; /* Watchdog Flag Interrupt Enable */ + uint16_t RCFIE:1; /* Redundant Channel Flag Interrupt Enable */ + uint16_t ICF2IE:1; /* Input Capture 2 Flag Interrupt Enable */ + uint16_t ICF1IE:1; /* Input Capture 1 Flag Interrupt Enable */ + uint16_t IEHFIE:1; /* Input Edge High Flag Interrupt Enable */ + uint16_t IELFIE:1; /* Input Edge Low Flag Interrupt Enable */ + uint16_t TOFIE:1; /* Timer Overflow Flag Interrupt Enable */ + uint16_t TCF2IE:1; /* Timer Compare 2 Flag Interrupt Enable */ + uint16_t TCF1IE:1; /* Timer Compare 1 Flag Interrupt Enable */ + uint16_t TCFIE:1; /* Timer Compare Flag Interrupt Enable */ + } B; + } mcTIMER_INTDMA_16B_tag; + + + /* Register layout for all registers CMPLD1... */ + + typedef union { /* Comparator Load Register 1 */ + uint16_t R; + struct { + uint16_t CMPLD1:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CMPLD1_16B_tag; + + + /* Register layout for all registers CMPLD2... */ + + typedef union { /* Comparator Load Register 2 */ + uint16_t R; + struct { + uint16_t CMPLD2:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CMPLD2_16B_tag; + + + /* Register layout for all registers CCCTRL... */ + + typedef union { /* Compare and Capture Control Register */ + uint16_t R; + struct { + uint16_t CLC2:3; /* Compare Load Control 2 */ + uint16_t CLC1:3; /* Compare Load Control 1 */ + uint16_t CMPMODE:2; /* Compare Mode */ + uint16_t CPT2MODE:2; /* Capture 2 Mode Control */ + uint16_t CPT1MODE:2; /* Capture 1 Mode Control */ + uint16_t CFWM:2; /* Capture FIFO Water Mark */ + uint16_t ONESHOT:1; /* One Shot Capture Mode */ + uint16_t ARM:1; /* Arm Capture */ + } B; + } mcTIMER_CCCTRL_16B_tag; + + + /* Register layout for all registers FILT... */ + + typedef union { /* Input Filter Register */ + uint16_t R; + struct { + uint16_t:5; +#ifndef USE_FIELD_ALIASES_mcTIMER + uint16_t FILT_CNT:3; /* Input Filter Sample Count */ +#else + uint16_t FILTCNT:3; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcTIMER + uint16_t FILT_PER:8; /* Input Filter Sample Period */ +#else + uint16_t FILTPER:8; /* deprecated name - please avoid */ +#endif + } B; + } mcTIMER_FILT_16B_tag; + + typedef union { /* Watchdog Time-out Register */ + uint16_t R; + struct { + uint16_t WDTOL:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_WDTOL_16B_tag; + + typedef union { /* Watchdog Time-out Register */ + uint16_t R; + struct { + uint16_t WDTOH:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_WDTOH_16B_tag; + + typedef union { /* Fault Control Register */ + uint16_t R; + struct { + uint16_t:3; + uint16_t FTEST:1; /* Fault Test */ + uint16_t FIE:4; /* Fault Interrupt Enable */ + uint16_t:4; + uint16_t FLVL:4; /* Fault Active Logic Level */ + } B; + } mcTIMER_FCTRL_16B_tag; + + typedef union { /* Fault Status Register */ + uint16_t R; + struct { + uint16_t:4; + uint16_t FFPIN:4; /* Filtered Fault Pin */ + uint16_t:4; + uint16_t FFLAG:4; /* Fault Flag */ + } B; + } mcTIMER_FSTS_16B_tag; + + typedef union { /* Fault Filter Registers */ + uint16_t R; + struct { + uint16_t:5; +#ifndef USE_FIELD_ALIASES_mcTIMER + uint16_t FFPIN:3; /* Fault Filter Sample Count */ +#else + uint16_t FFILTCNT:3; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcTIMER + uint16_t FFILT_PER:8; /* Fault Filter Sample Period */ +#else + uint16_t FFILTPER:8; /* deprecated name - please avoid */ +#endif + } B; + } mcTIMER_FFILT_16B_tag; + + typedef union { /* Channel Enable Registers */ + uint16_t R; + struct { + uint16_t:8; + uint16_t ENBL:8; /* Timer Channel Enable */ + } B; + } mcTIMER_ENBL_16B_tag; + + typedef union { /* DMA Request 0 Select Registers */ + uint16_t R; + struct { + uint16_t:11; + uint16_t DREQ0V:5; /* DMA Request Select */ + } B; + } mcTIMER_DREQ0_16B_tag; + + typedef union { /* DMA Request 1 Select Registers */ + uint16_t R; + struct { + uint16_t:11; + uint16_t DREQ1V:5; /* DMA Request Select */ + } B; + } mcTIMER_DREQ1_16B_tag; + + typedef union { /* DMA Request 2 Select Registers */ + uint16_t R; + struct { + uint16_t:11; + uint16_t DREQ2V:5; /* DMA Request Select */ + } B; + } mcTIMER_DREQ2_16B_tag; + + typedef union { /* DMA Request 3 Select Registers */ + uint16_t R; + struct { + uint16_t:11; + uint16_t DREQ3V:5; /* DMA Request Select */ + } B; + } mcTIMER_DREQ3_16B_tag; + + + /* Register layout for generated register(s) DREQ... */ + + typedef union { /* */ + uint16_t R; + } mcTIMER_DREQ_16B_tag; + + + typedef struct mcTIMER_CHANNEL_struct_tag { + + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP1; /* relative offset: 0x0000 */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP2; /* relative offset: 0x0002 */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT1; /* relative offset: 0x0004 */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT2; /* relative offset: 0x0006 */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD; /* relative offset: 0x0008 */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD; /* relative offset: 0x000A */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR; /* relative offset: 0x000C */ + union { + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL1; /* relative offset: 0x000E */ + mcTIMER_CTRL1_16B_tag CTRL; /* deprecated - please avoid */ + }; + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL2; /* relative offset: 0x0010 */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL3; /* relative offset: 0x0012 */ + /* Status Register */ + mcTIMER_STS_16B_tag STS; /* relative offset: 0x0014 */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA; /* relative offset: 0x0016 */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD1; /* relative offset: 0x0018 */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD2; /* relative offset: 0x001A */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL; /* relative offset: 0x001C */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT; /* relative offset: 0x001E */ + + } mcTIMER_CHANNEL_tag; + + + typedef struct mcTIMER_struct_tag { /* start of mcTIMER_tag */ + union { + /* Register set CHANNEL */ + mcTIMER_CHANNEL_tag CHANNEL[6]; /* offset: 0x0000 (0x0020 x 6) */ + + struct { + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP10; /* offset: 0x0000 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP20; /* offset: 0x0002 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT10; /* offset: 0x0004 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT20; /* offset: 0x0006 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD0; /* offset: 0x0008 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD0; /* offset: 0x000A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR0; /* offset: 0x000C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL10; /* offset: 0x000E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL20; /* offset: 0x0010 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL30; /* offset: 0x0012 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS0; /* offset: 0x0014 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA0; /* offset: 0x0016 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD10; /* offset: 0x0018 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD20; /* offset: 0x001A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL0; /* offset: 0x001C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT0; /* offset: 0x001E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP11; /* offset: 0x0020 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP21; /* offset: 0x0022 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT11; /* offset: 0x0024 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT21; /* offset: 0x0026 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD1; /* offset: 0x0028 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD1; /* offset: 0x002A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR1; /* offset: 0x002C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL11; /* offset: 0x002E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL21; /* offset: 0x0030 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL31; /* offset: 0x0032 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS1; /* offset: 0x0034 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA1; /* offset: 0x0036 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD11; /* offset: 0x0038 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD21; /* offset: 0x003A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL1; /* offset: 0x003C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT1; /* offset: 0x003E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP12; /* offset: 0x0040 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP22; /* offset: 0x0042 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT12; /* offset: 0x0044 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT22; /* offset: 0x0046 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD2; /* offset: 0x0048 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD2; /* offset: 0x004A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR2; /* offset: 0x004C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL12; /* offset: 0x004E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL22; /* offset: 0x0050 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL32; /* offset: 0x0052 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS2; /* offset: 0x0054 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA2; /* offset: 0x0056 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD12; /* offset: 0x0058 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD22; /* offset: 0x005A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL2; /* offset: 0x005C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT2; /* offset: 0x005E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP13; /* offset: 0x0060 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP23; /* offset: 0x0062 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT13; /* offset: 0x0064 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT23; /* offset: 0x0066 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD3; /* offset: 0x0068 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD3; /* offset: 0x006A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR3; /* offset: 0x006C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL13; /* offset: 0x006E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL23; /* offset: 0x0070 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL33; /* offset: 0x0072 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS3; /* offset: 0x0074 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA3; /* offset: 0x0076 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD13; /* offset: 0x0078 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD23; /* offset: 0x007A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL3; /* offset: 0x007C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT3; /* offset: 0x007E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP14; /* offset: 0x0080 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP24; /* offset: 0x0082 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT14; /* offset: 0x0084 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT24; /* offset: 0x0086 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD4; /* offset: 0x0088 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD4; /* offset: 0x008A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR4; /* offset: 0x008C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL14; /* offset: 0x008E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL24; /* offset: 0x0090 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL34; /* offset: 0x0092 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS4; /* offset: 0x0094 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA4; /* offset: 0x0096 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD14; /* offset: 0x0098 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD24; /* offset: 0x009A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL4; /* offset: 0x009C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT4; /* offset: 0x009E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP15; /* offset: 0x00A0 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP25; /* offset: 0x00A2 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT15; /* offset: 0x00A4 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT25; /* offset: 0x00A6 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD5; /* offset: 0x00A8 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD5; /* offset: 0x00AA size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR5; /* offset: 0x00AC size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL15; /* offset: 0x00AE size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL25; /* offset: 0x00B0 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL35; /* offset: 0x00B2 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS5; /* offset: 0x00B4 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA5; /* offset: 0x00B6 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD15; /* offset: 0x00B8 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD25; /* offset: 0x00BA size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL5; /* offset: 0x00BC size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT5; /* offset: 0x00BE size: 16 bit */ + }; + + }; + int8_t mcTIMER_reserved_00C0[64]; + /* Watchdog Time-out Register */ + mcTIMER_WDTOL_16B_tag WDTOL; /* offset: 0x0100 size: 16 bit */ + /* Watchdog Time-out Register */ + mcTIMER_WDTOH_16B_tag WDTOH; /* offset: 0x0102 size: 16 bit */ + /* Fault Control Register */ + mcTIMER_FCTRL_16B_tag FCTRL; /* offset: 0x0104 size: 16 bit */ + /* Fault Status Register */ + mcTIMER_FSTS_16B_tag FSTS; /* offset: 0x0106 size: 16 bit */ + /* Fault Filter Registers */ + mcTIMER_FFILT_16B_tag FFILT; /* offset: 0x0108 size: 16 bit */ + int8_t mcTIMER_reserved_010A[2]; + /* Channel Enable Registers */ + mcTIMER_ENBL_16B_tag ENBL; /* offset: 0x010C size: 16 bit */ + int8_t mcTIMER_reserved_010E_C[2]; + union { + mcTIMER_DREQ_16B_tag DREQ[4]; /* offset: 0x0110 (0x0002 x 4) */ + + struct { + /* DMA Request 0 Select Registers */ + mcTIMER_DREQ0_16B_tag DREQ0; /* offset: 0x0110 size: 16 bit */ + /* DMA Request 1 Select Registers */ + mcTIMER_DREQ1_16B_tag DREQ1; /* offset: 0x0112 size: 16 bit */ + /* DMA Request 2 Select Registers */ + mcTIMER_DREQ2_16B_tag DREQ2; /* offset: 0x0114 size: 16 bit */ + /* DMA Request 3 Select Registers */ + mcTIMER_DREQ3_16B_tag DREQ3; /* offset: 0x0116 size: 16 bit */ + }; + + }; + } mcTIMER_tag; + + +#define mcTIMER0 (*(volatile mcTIMER_tag *) 0xFFE18000UL) +#define mcTIMER1 (*(volatile mcTIMER_tag *) 0xFFE1C000UL) +#define mcTIMER2 (*(volatile mcTIMER_tag *) 0xFFE20000UL) + + + +/****************************************************************/ +/* */ +/* Module: mcPWM */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers CNT... */ + + typedef union { /* Counter Register */ + uint16_t R; + } mcPWM_CNT_16B_tag; + + + /* Register layout for all registers INIT... */ + + typedef union { /* Initial Counter Register */ + uint16_t R; + } mcPWM_INIT_16B_tag; + + + /* Register layout for all registers CTRL2... */ + + typedef union { /* Control 2 Register */ + uint16_t R; + struct { + uint16_t DBGEN:1; /* Debug Enable */ + uint16_t WAITEN:1; /* Wait Enable */ + uint16_t INDEP:1; /* Independent or Complementary Pair Operation */ +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t PWM23_INIT:1; /* PWM23 Initial Value */ +#else + uint16_t PWMA_INIT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t PWM45_INIT:1; /* PWM23 Initial Value */ +#else + uint16_t PWMB_INIT:1; /* deprecated name - please avoid */ +#endif + uint16_t PWMX_INIT:1; /* PWMX Initial Value */ + uint16_t INIT_SEL:2; /* Initialization Control Select */ + uint16_t FRCEN:1; /* Force Initialization enable */ + uint16_t FORCE:1; /* Force Initialization */ + uint16_t FORCE_SEL:3; /* Force Source Select */ + uint16_t RELOAD_SEL:1; /* Reload Source Select */ + uint16_t CLK_SEL:2; /* Clock Source Select */ + } B; + } mcPWM_CTRL2_16B_tag; + + + /* Register layout for all registers CTRL1... */ + + typedef union { /* Control Register */ + uint16_t R; + struct { + uint16_t LDFQ:4; /* Load Frequency */ + uint16_t HALF:1; /* Half Cycle Reload */ + uint16_t FULL:1; /* Full Cycle Reload */ + uint16_t DT:2; /* Deadtime */ + uint16_t:1; + uint16_t PRSC:3; /* Prescaler */ + uint16_t:1; + uint16_t LDMOD:1; /* Load Mode Select */ + uint16_t:1; +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t DBL_EN:1; /* Double Switching Enable */ +#else + uint16_t DBLEN:1; /* deprecated name - please avoid */ +#endif + } B; + } mcPWM_CTRL1_16B_tag; + + + /* Register layout for all registers VAL_0... */ + + typedef union { /* Value Register 0 */ + uint16_t R; + } mcPWM_VAL_0_16B_tag; + + + /* Register layout for all registers VAL_1... */ + + typedef union { /* Value Register 1 */ + uint16_t R; + } mcPWM_VAL_1_16B_tag; + + + /* Register layout for all registers VAL_2... */ + + typedef union { /* Value Register 2 */ + uint16_t R; + } mcPWM_VAL_2_16B_tag; + + + /* Register layout for all registers VAL_3... */ + + typedef union { /* Value Register 3 */ + uint16_t R; + } mcPWM_VAL_3_16B_tag; + + + /* Register layout for all registers VAL_4... */ + + typedef union { /* Value Register 4 */ + uint16_t R; + } mcPWM_VAL_4_16B_tag; + + + /* Register layout for all registers VAL_5... */ + + typedef union { /* Value Register 5 */ + uint16_t R; + } mcPWM_VAL_5_16B_tag; + + /* Register layout for all registers OCTRL... */ + + typedef union { /* Output Control Register */ + uint16_t R; + struct { + uint16_t PWMA_IN:1; /* PWMA Input */ + uint16_t PWMB_IN:1; /* PWMB Input */ + uint16_t PWMX_IN:1; /* PWMX Input */ + uint16_t:2; + uint16_t POLA:1; /* PWMA Output Polarity */ + uint16_t POLB:1; /* PWMB Output Polarity */ + uint16_t POLX:1; /* PWMX Output Polarity */ + uint16_t:2; + uint16_t PWMAFS:2; /* PWMA Fault State */ + uint16_t PWMBFS:2; /* PWMB Fault State */ + uint16_t PWMXFS:2; /* PWMX Fault State */ + } B; + } mcPWM_OCTRL_16B_tag; + + + /* Register layout for all registers STS... */ + + typedef union { /* Status Register */ + uint16_t R; + struct { + uint16_t:1; + uint16_t RUF:1; /* Registers Updated Flag */ + uint16_t REF:1; /* Reload Error Flag */ + uint16_t RF:1; /* Reload Flag */ + uint16_t CFA1:1; /* Capture Flag A1 */ + uint16_t CFA0:1; /* Capture Flag A0 */ + uint16_t CFB1:1; /* Capture Flag B1 */ + uint16_t CFB0:1; /* Capture Flag B0 */ + uint16_t CFX1:1; /* Capture Flag X1 */ + uint16_t CFX0:1; /* Capture Flag X0 */ + uint16_t CMPF:6; /* Compare Flags */ + } B; + } mcPWM_STS_16B_tag; + + + /* Register layout for all registers INTEN... */ + + typedef union { /* Interrupt Enable Registers */ + uint16_t R; + struct { + uint16_t:2; + uint16_t REIE:1; /* Reload Error Interrupt Enable */ + uint16_t RIE:1; /* Reload Interrupt Enable */ + uint16_t CA1IE:1; /* Capture A1 Interrupt Enable */ + uint16_t CA0IE:1; /* Capture A0 Interrupt Enable */ + uint16_t CB1IE:1; /* Capture B1 Interrupt Enable */ + uint16_t CB0IE:1; /* Capture B0 Interrupt Enable */ + uint16_t CX1IE:1; /* Capture X1 Interrupt Enable */ + uint16_t CX0IE:1; /* Capture X0 Interrupt Enable */ + uint16_t CMPIE:6; /* Compare Interrupt Enables */ + } B; + } mcPWM_INTEN_16B_tag; + + + /* Register layout for all registers DMAEN... */ + + typedef union { /* DMA Enable Registers */ + uint16_t R; + struct { + uint16_t:6; + uint16_t VALDE:1; /* Value Register DMA Enable */ + uint16_t FAND:1; /* FIFO Watermark AND Control */ + uint16_t CAPTDE:2; /* Capture DMA Enable Source Select */ + uint16_t CA1DE:1; /* Capture A1 FIFO DMA Enable */ + uint16_t CA0DE:1; /* Capture A0 FIFO DMA Enable */ + uint16_t CB1DE:1; /* Capture B1 FIFO DMA Enable */ + uint16_t CB0DE:1; /* Capture B0 FIFO DMA Enable */ + uint16_t CX1DE:1; /* Capture X1 FIFO DMA Enable */ + uint16_t CX0DE:1; /* Capture X0 FIFO DMA Enable */ + } B; + } mcPWM_DMAEN_16B_tag; + + + /* Register layout for all registers TCTRL... */ + + typedef union { /* Output Trigger Control Registers */ + uint16_t R; + struct { + uint16_t:10; + uint16_t OUT_TRIG_EN:6; /* Output Trigger Enables */ + } B; + } mcPWM_TCTRL_16B_tag; + + + /* Register layout for all registers DISMAP... */ + + typedef union { /* Fault Disable Mapping Registers */ + uint16_t R; + struct { + uint16_t:4; + uint16_t DISX:4; /* PWMX Fault Disable Mask */ + uint16_t DISB:4; /* PWMB Fault Disable Mask */ + uint16_t DISA:4; /* PWMA Fault Disable Mask */ + } B; + } mcPWM_DISMAP_16B_tag; + + + /* Register layout for all registers DTCNT0... */ + + typedef union { /* Deadtime Count Register 0 */ + uint16_t R; + struct { + uint16_t:5; + uint16_t DTCNT0:11; /* Deadtime Count Register 0 */ + } B; + } mcPWM_DTCNT0_16B_tag; + + + /* Register layout for all registers DTCNT1... */ + + typedef union { /* Deadtime Count Register 1 */ + uint16_t R; + struct { + uint16_t:5; + uint16_t DTCNT1:11; /* Deadtime Count Register 1 */ + } B; + } mcPWM_DTCNT1_16B_tag; + + /* Register layout for all registers CAPTCTRLX... */ + + typedef union { /* Capture Control X Register */ + uint16_t R; + struct { + uint16_t CX1CNT:3; /* Capture X1 FIFO Word Count */ + uint16_t CX0CNT:3; /* Capture X0 FIFO Word Count */ + uint16_t CFXWM:2; /* Capture X FIFOs Water Mark */ +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t EDGCNTXEN:1; /* Edge Counter X Enable */ +#else + uint16_t EDGCNTX_EN:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t INPSELX:1; /* Input Select X */ +#else + uint16_t INP_SELX:1; /* deprecated name - please avoid */ +#endif + uint16_t EDGX1:2; /* Edge X 1 */ + uint16_t EDGX0:2; /* Edge X 0 */ + uint16_t ONESHOTX:1; /* One Shot Mode X */ + uint16_t ARMX:1; /* Arm X */ + } B; + } mcPWM_CAPTCTRLX_16B_tag; + + + /* Register layout for all registers CAPTCMPX... */ + + typedef union { /* Capture Compare X Register */ + uint16_t R; + struct { + uint16_t EDGCNTX:8; /* Edge Counter X */ + uint16_t EDGCMPX:8; /* Edge Compare X */ + } B; + } mcPWM_CAPTCMPX_16B_tag; + + + /* Register layout for all registers CVAL0... */ + + typedef union { /* Capture Value 0 Register */ + uint16_t R; + struct { + uint16_t CAPTVAL0:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL0_16B_tag; + + + /* Register layout for all registers CVAL0CYC... */ + + typedef union { /* Capture Value 0 Cycle Register */ + uint16_t R; + struct { + uint16_t:12; + uint16_t CVAL0CYC:4; /* Capture Value 0 Cycle */ + } B; + } mcPWM_CVAL0CYC_16B_tag; + + + /* Register layout for all registers CVAL1... */ + + typedef union { /* Capture Value 1 Register */ + uint16_t R; + struct { + uint16_t CAPTVAL1:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL1_16B_tag; + + + /* Register layout for all registers CVAL1CYC... */ + + typedef union { /* Capture Value 1 Cycle Register */ + uint16_t R; + struct { + uint16_t:12; + uint16_t CVAL1CYC:4; /* Capture Value 1 Cycle */ + } B; + } mcPWM_CVAL1CYC_16B_tag; + + + /* Register layout for all registers CVAL3... */ + + typedef union { /* Capture Value 3 Register */ + uint16_t R; + struct { + uint16_t CAPTVAL3:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL3_16B_tag; + + + /* Register layout for all registers CVAL3CYC... */ + + typedef union { /* Capture Value 3 Cycle Register */ + uint16_t R; + struct { + uint16_t:12; + uint16_t CVAL3CYC:4; /* Capture Value 3 Cycle */ + } B; + } mcPWM_CVAL3CYC_16B_tag; + + + /* Register layout for all registers CVAL4... */ + + typedef union { /* Capture Value 4 Register */ + uint16_t R; + struct { + uint16_t CAPTVAL4:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL4_16B_tag; + + + /* Register layout for all registers CVAL4CYC... */ + + typedef union { /* Capture Value 4 Cycle Register */ + uint16_t R; + struct { + uint16_t:12; + uint16_t CVAL4CYC:4; /* Capture Value 4 Cycle */ + } B; + } mcPWM_CVAL4CYC_16B_tag; + + + /* Register layout for all registers CVAL5... */ + + typedef union { /* Capture Value 5 Register */ + uint16_t R; + struct { + uint16_t CAPTVAL5:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL5_16B_tag; + + + /* Register layout for all registers CVAL5CYC... */ + + typedef union { /* Capture Value 5 Cycle Register */ + uint16_t R; + struct { + uint16_t:12; + uint16_t CVAL5CYC:4; /* Capture Value 5 Cycle */ + } B; + } mcPWM_CVAL5CYC_16B_tag; + + typedef union { /* Output Enable Register */ + uint16_t R; + struct { + uint16_t:4; + uint16_t PWMA_EN:4; /* PWMA Output Enables */ + uint16_t PWMB_EN:4; /* PWMB Output Enables */ + uint16_t PWMX_EN:4; /* PWMX Output Enables */ + } B; + } mcPWM_OUTEN_16B_tag; + + typedef union { /* Mask Register */ + uint16_t R; + struct { + uint16_t:4; + uint16_t MASKA:4; /* PWMA Masks */ + uint16_t MASKB:4; /* PWMB Masks */ + uint16_t MASKX:4; /* PWMX Masks */ + } B; + } mcPWM_MASK_16B_tag; + + typedef union { /* Software Controlled Output Register */ + uint16_t R; + struct { + uint16_t:8; +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT23_3:1; /* Software Controlled Output 23_3 */ +#else + uint16_t OUTA_3:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT45_3:1; /* Software Controlled Output 45_3 */ +#else + uint16_t OUTB_3:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT23_2:1; /* Software Controlled Output 23_2 */ +#else + uint16_t OUTA_2:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT45_2:1; /* Software Controlled Output 45_2 */ +#else + uint16_t OUTB_2:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT23_1:1; /* Software Controlled Output 23_1 */ +#else + uint16_t OUTA_1:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT45_1:1; /* Software Controlled Output 45_1 */ +#else + uint16_t OUTB_1:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT23_0:1; /* Software Controlled Output 23_0 */ +#else + uint16_t OUTA_0:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT45_0:1; /* Software Controlled Output 45_0 */ +#else + uint16_t OUTB_0:1; /* deprecated name - please avoid */ +#endif + } B; + } mcPWM_SWCOUT_16B_tag; + + typedef union { /* Deadtime Source Select Register */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL23_3:2; /* PWM23_3 Control Select */ +#else + uint16_t SELA_3:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL45_3:2; /* PWM45_3 Control Select */ +#else + uint16_t SELB_3:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL23_2:2; /* PWM23_2 Control Select */ +#else + uint16_t SELA_2:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL45_2:2; /* PWM45_2 Control Select */ +#else + uint16_t SELB_2:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL23_1:2; /* PWM23_1 Control Select */ +#else + uint16_t SELA_1:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL45_1:2; /* PWM45_1 Control Select */ +#else + uint16_t SELB_1:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL23_0:2; /* PWM23_0 Control Select */ +#else + uint16_t SELA_0:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL45_0:2; /* PWM45_0 Control Select */ +#else + uint16_t SELB_0:2; /* deprecated name - please avoid */ +#endif + } B; + } mcPWM_DTSRCSEL_16B_tag; + + typedef union { /* Master Control Register */ + uint16_t R; + struct { + uint16_t IPOL:4; /* Current Polarity */ + uint16_t RUN:4; /* Run */ +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t CLOK:4; /* Clear Load Okay */ +#else + uint16_t CLDOK:4; /* deprecated name - please avoid */ +#endif + uint16_t LDOK:4; /* Load Okay */ + } B; + } mcPWM_MCTRL_16B_tag; + + typedef union { /* Fault Control Register */ + uint16_t R; + struct { + uint16_t FLVL:4; /* Fault Level */ + uint16_t FAUTO:4; /* Automatic Fault Clearing */ + uint16_t FSAFE:4; /* Fault Safety Mode */ + uint16_t FIE:4; /* Fault Interrupt Enables */ + } B; + } mcPWM_FCTRL_16B_tag; + + typedef union { /* Fault Status Register */ + uint16_t R; + struct { + uint16_t:3; + uint16_t FTEST:1; /* Fault Test */ + uint16_t FFPIN:4; /* Filtered Fault Pins */ + uint16_t:4; + uint16_t FFLAG:4; /* Fault Flags */ + } B; + } mcPWM_FSTS_16B_tag; + + typedef union { /* Fault Filter Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t FILT_CNT:3; /* Fault Filter Count */ + uint16_t FILT_PER:8; /* Fault Filter Period */ + } B; + } mcPWM_FFILT_16B_tag; + + + /* Register layout for generated register(s) VAL... */ + + typedef union { /* */ + uint16_t R; + } mcPWM_VAL_16B_tag; + + + typedef struct mcPWM_SUBMOD_struct_tag { + + /* Counter Register */ + mcPWM_CNT_16B_tag CNT; /* relative offset: 0x0000 */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT; /* relative offset: 0x0002 */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL2; /* relative offset: 0x0004 */ + union { + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL1; /* relative offset: 0x0006 */ + mcPWM_CTRL1_16B_tag CTRL; /* deprecated - please avoid */ + }; + /* Value Register 0 */ + + union { + + struct { + + mcPWM_VAL_0_16B_tag VAL_0; /* relative offset: 0x0008 */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_1; /* relative offset: 0x000A */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_2; /* relative offset: 0x000C */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_3; /* relative offset: 0x000E */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_4; /* relative offset: 0x0010 */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_5; /* relative offset: 0x0012 */ + + }; + + mcPWM_VAL_0_16B_tag VAL[6]; /* offset: 0x0008 size: 16 bit */ + + }; + int8_t mcPWM_reserved_0014[4]; + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL; /* relative offset: 0x0018 */ + /* Status Register */ + mcPWM_STS_16B_tag STS; /* relative offset: 0x001A */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN; /* relative offset: 0x001C */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN; /* relative offset: 0x001E */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL; /* relative offset: 0x0020 */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP; /* relative offset: 0x0022 */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT0; /* relative offset: 0x0024 */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT1; /* relative offset: 0x0026 */ + /* Capture Control A Register */ + int8_t mcPWM_reserved_0028[8]; + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX; /* relative offset: 0x0030 */ + union { + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX; /* relative offset: 0x0032 */ + mcPWM_CAPTCMPX_16B_tag CAPTCOMPX; /* deprecated - please avoid */ + }; + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL0; /* relative offset: 0x0034 */ + union { + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC; /* relative offset: 0x0036 */ + mcPWM_CVAL0CYC_16B_tag CVAL0C; /* deprecated - please avoid */ + }; + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL1; /* relative offset: 0x0038 */ + union { + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC; /* relative offset: 0x003A */ + mcPWM_CVAL1CYC_16B_tag CVAL1C; /* deprecated - please avoid */ + }; + /* Capture Value 2 Register */ + int8_t mcPWM_SUBMOD_reserved_003C[16]; + int8_t mcPWM_SUBMOD_reserved_004C[4]; + + } mcPWM_SUBMOD_tag; + + + typedef struct mcPWM_struct_tag { /* start of mcPWM_tag */ + union { + /* Register set SUBMOD */ + mcPWM_SUBMOD_tag SUBMOD[4]; /* offset: 0x0000 (0x0050 x 4) */ + + mcPWM_SUBMOD_tag SUB[4]; /* offset: 0x0000 (0x0050 x 4) */ + + struct { + /* Counter Register */ + mcPWM_CNT_16B_tag CNT0; /* offset: 0x0000 size: 16 bit */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT0; /* offset: 0x0002 size: 16 bit */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL20; /* offset: 0x0004 size: 16 bit */ + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL10; /* offset: 0x0006 size: 16 bit */ + /* Value Register 0 */ + mcPWM_VAL_0_16B_tag VAL_00; /* offset: 0x0008 size: 16 bit */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_10; /* offset: 0x000A size: 16 bit */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_20; /* offset: 0x000C size: 16 bit */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_30; /* offset: 0x000E size: 16 bit */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_40; /* offset: 0x0010 size: 16 bit */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_50; /* offset: 0x0012 size: 16 bit */ + int8_t mcPWM_reserved_0014[4]; + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL0; /* offset: 0x0018 size: 16 bit */ + /* Status Register */ + mcPWM_STS_16B_tag STS0; /* offset: 0x001A size: 16 bit */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN0; /* offset: 0x001C size: 16 bit */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN0; /* offset: 0x001E size: 16 bit */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL0; /* offset: 0x0020 size: 16 bit */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP0; /* offset: 0x0022 size: 16 bit */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT00; /* offset: 0x0024 size: 16 bit */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT10; /* offset: 0x0026 size: 16 bit */ + int8_t mcPWM_reserved_0028[8]; + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX0; /* offset: 0x0030 size: 16 bit */ + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX0; /* offset: 0x0032 size: 16 bit */ + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL00; /* offset: 0x0034 size: 16 bit */ + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC0; /* offset: 0x0036 size: 16 bit */ + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL10; /* offset: 0x0038 size: 16 bit */ + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC0; /* offset: 0x003A size: 16 bit */ + int8_t mcPWM_reserved_003c[16]; + int8_t mcPWM_reserved_004C_I2[4]; + /* Counter Register */ + mcPWM_CNT_16B_tag CNT1; /* offset: 0x0050 size: 16 bit */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT1; /* offset: 0x0052 size: 16 bit */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL21; /* offset: 0x0054 size: 16 bit */ + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL11; /* offset: 0x0056 size: 16 bit */ + /* Value Register 0 */ + mcPWM_VAL_0_16B_tag VAL_01; /* offset: 0x0058 size: 16 bit */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_11; /* offset: 0x005A size: 16 bit */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_21; /* offset: 0x005C size: 16 bit */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_31; /* offset: 0x005E size: 16 bit */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_41; /* offset: 0x0060 size: 16 bit */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_51; /* offset: 0x0062 size: 16 bit */ + int8_t mcPWM_reserved_0064[4]; + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL1; /* offset: 0x0068 size: 16 bit */ + /* Status Register */ + mcPWM_STS_16B_tag STS1; /* offset: 0x006A size: 16 bit */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN1; /* offset: 0x006C size: 16 bit */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN1; /* offset: 0x006E size: 16 bit */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL1; /* offset: 0x0070 size: 16 bit */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP1; /* offset: 0x0072 size: 16 bit */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT01; /* offset: 0x0074 size: 16 bit */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT11; /* offset: 0x0076 size: 16 bit */ + /* Capture Control A Register */ + int8_t mcPWM_reserved_0078[8]; + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX1; /* offset: 0x0080 size: 16 bit */ + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX1; /* offset: 0x0082 size: 16 bit */ + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL01; /* offset: 0x0084 size: 16 bit */ + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC1; /* offset: 0x0086 size: 16 bit */ + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL11; /* offset: 0x0088 size: 16 bit */ + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC1; /* offset: 0x008A size: 16 bit */ + int8_t mcPWM_reserved_008c[16]; + int8_t mcPWM_reserved_009C_I2[4]; + /* Counter Register */ + mcPWM_CNT_16B_tag CNT2; /* offset: 0x00A0 size: 16 bit */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT2; /* offset: 0x00A2 size: 16 bit */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL22; /* offset: 0x00A4 size: 16 bit */ + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL12; /* offset: 0x00A6 size: 16 bit */ + /* Value Register 0 */ + mcPWM_VAL_0_16B_tag VAL_02; /* offset: 0x00A8 size: 16 bit */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_12; /* offset: 0x00AA size: 16 bit */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_22; /* offset: 0x00AC size: 16 bit */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_32; /* offset: 0x00AE size: 16 bit */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_42; /* offset: 0x00B0 size: 16 bit */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_52; /* offset: 0x00B2 size: 16 bit */ + int8_t mcPWM_reserved_00b4[4]; + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL2; /* offset: 0x00B8 size: 16 bit */ + /* Status Register */ + mcPWM_STS_16B_tag STS2; /* offset: 0x00BA size: 16 bit */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN2; /* offset: 0x00BC size: 16 bit */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN2; /* offset: 0x00BE size: 16 bit */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL2; /* offset: 0x00C0 size: 16 bit */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP2; /* offset: 0x00C2 size: 16 bit */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT02; /* offset: 0x00C4 size: 16 bit */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT12; /* offset: 0x00C6 size: 16 bit */ + /* Capture Control A Register */ + int8_t mcPWM_reserved_00c8[8]; + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX2; /* offset: 0x00D0 size: 16 bit */ + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX2; /* offset: 0x00D2 size: 16 bit */ + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL02; /* offset: 0x00D4 size: 16 bit */ + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC2; /* offset: 0x00D6 size: 16 bit */ + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL12; /* offset: 0x00D8 size: 16 bit */ + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC2; /* offset: 0x00DA size: 16 bit */ + int8_t mcPWM_reserved_00dc[16]; + int8_t mcPWM_reserved_00EC_I2[4]; + /* Counter Register */ + mcPWM_CNT_16B_tag CNT3; /* offset: 0x00F0 size: 16 bit */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT3; /* offset: 0x00F2 size: 16 bit */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL23; /* offset: 0x00F4 size: 16 bit */ + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL13; /* offset: 0x00F6 size: 16 bit */ + /* Value Register 0 */ + mcPWM_VAL_0_16B_tag VAL_03; /* offset: 0x00F8 size: 16 bit */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_13; /* offset: 0x00FA size: 16 bit */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_23; /* offset: 0x00FC size: 16 bit */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_33; /* offset: 0x00FE size: 16 bit */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_43; /* offset: 0x0100 size: 16 bit */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_53; /* offset: 0x0102 size: 16 bit */ + int8_t mcPWM_reserved_00104[4]; + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL3; /* offset: 0x0108 size: 16 bit */ + /* Status Register */ + mcPWM_STS_16B_tag STS3; /* offset: 0x010A size: 16 bit */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN3; /* offset: 0x010C size: 16 bit */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN3; /* offset: 0x010E size: 16 bit */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL3; /* offset: 0x0110 size: 16 bit */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP3; /* offset: 0x0112 size: 16 bit */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT03; /* offset: 0x0114 size: 16 bit */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT13; /* offset: 0x0116 size: 16 bit */ + /* Capture Control A Register */ + int8_t mcPWM_reserved_00118[8]; + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX3; /* offset: 0x0120 size: 16 bit */ + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX3; /* offset: 0x0122 size: 16 bit */ + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL03; /* offset: 0x0124 size: 16 bit */ + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC3; /* offset: 0x0126 size: 16 bit */ + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL13; /* offset: 0x0128 size: 16 bit */ + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC3; /* offset: 0x012A size: 16 bit */ + int8_t mcPWM_reserved_0012c[16]; + int8_t mcPWM_reserved_013C_E2[4]; + }; + + }; + /* Output Enable Register */ + mcPWM_OUTEN_16B_tag OUTEN; /* offset: 0x0140 size: 16 bit */ + /* Mask Register */ + mcPWM_MASK_16B_tag MASK; /* offset: 0x0142 size: 16 bit */ + /* Software Controlled Output Register */ + mcPWM_SWCOUT_16B_tag SWCOUT; /* offset: 0x0144 size: 16 bit */ + /* Deadtime Source Select Register */ + mcPWM_DTSRCSEL_16B_tag DTSRCSEL; /* offset: 0x0146 size: 16 bit */ + /* Master Control Register */ + mcPWM_MCTRL_16B_tag MCTRL; /* offset: 0x0148 size: 16 bit */ + int8_t mcPWM_reserved_014A[2]; + /* Fault Control Register */ + mcPWM_FCTRL_16B_tag FCTRL; /* offset: 0x014C size: 16 bit */ + /* Fault Status Register */ + mcPWM_FSTS_16B_tag FSTS; /* offset: 0x014E size: 16 bit */ + /* Fault Filter Register */ + mcPWM_FFILT_16B_tag FFILT; /* offset: 0x0150 size: 16 bit */ + } mcPWM_tag; + + +#define mcPWM_A (*(volatile mcPWM_tag *) 0xFFE24000UL) +#define mcPWM_B (*(volatile mcPWM_tag *) 0xFFE28000UL) + + + +/****************************************************************/ +/* */ +/* Module: LINFLEX */ +/* */ +/****************************************************************/ + + typedef union { /* LIN Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t CCD:1; /* Checksum Calculation Disable */ + uint32_t CFD:1; /* Checksum Field Disable */ + uint32_t LASE:1; /* LIN Auto Synchronization Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t AUTOWU:1; /* Auto Wake Up */ +#else + uint32_t AWUM:1; /* deprecated name - please avoid */ +#endif + uint32_t MBL:4; /* Master Break Length */ + uint32_t BF:1; /* By-Pass Filter */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t SLFM:1; /* Selftest Mode */ +#else + uint32_t SFTM:1; /* deprecated name - please avoid */ +#endif + uint32_t LBKM:1; /* Loopback Mode */ + uint32_t MME:1; /* Master Mode Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t SSBL:1; /* Slave Mode Synch Break Length */ +#else + uint32_t SSDT:1; /* deprecated name - please avoid */ +#endif + uint32_t RBLM:1; /* Receiver Buffer Locked Mode */ + uint32_t SLEEP:1; /* Sleep Mode Request */ + uint32_t INIT:1; /* Initialization Mode Request */ + } B; + } LINFLEX_LINCR1_32B_tag; + + typedef union { /* LIN Interrupt Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t SZIE:1; /* Stuck at Zero Interrupt Enable */ + uint32_t OCIE:1; /* Output Compare Interrupt Enable */ + uint32_t BEIE:1; /* Bit Error Interrupt Enable */ + uint32_t CEIE:1; /* Checksum Error Interrupt Enable */ + uint32_t HEIE:1; /* Header Error Interrupt Enable */ + uint32_t:2; + uint32_t FEIE:1; /* Frame Error Interrupt Enable */ + uint32_t BOIE:1; /* Buffer Overrun Error Interrupt Enable */ + uint32_t LSIE:1; /* LIN State Interrupt Enable */ + uint32_t WUIE:1; /* Wakeup Interrupt Enable */ + uint32_t DBFIE:1; /* Data Buffer Full Interrupt Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t DBEIE_TOIE:1; /* Data Buffer Empty Interrupt Enable */ +#else + uint32_t DBEIE:1; /* deprecated name - please avoid */ +#endif + uint32_t DRIE:1; /* Data Reception complete Interrupt Enable */ + uint32_t DTIE:1; /* Data Transmitted Interrupt Enable */ + uint32_t HRIE:1; /* Header Received Interrupt Enable */ + } B; + } LINFLEX_LINIER_32B_tag; + + typedef union { /* LIN Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t LINS:4; /* LIN State */ + uint32_t:2; + uint32_t RMB:1; /* Release Message Buffer */ + uint32_t:1; +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t RXBUSY:1; /* Receiver Busy Flag */ +#else + uint32_t RBSY:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t RDI:1; /* LIN Receive Signal */ +#else + uint32_t RPS:1; /* deprecated name - please avoid */ +#endif + uint32_t WUF:1; /* Wake Up Flag */ + uint32_t DBFF:1; /* Data Buffer Full Flag */ + uint32_t DBEF:1; /* Data Buffer Empty Flag */ + uint32_t DRF:1; /* Data Reception Completed Flag */ + uint32_t DTF:1; /* Data Transmission Completed Flag */ + uint32_t HRF:1; /* Header Received Flag */ + } B; + } LINFLEX_LINSR_32B_tag; + + typedef union { /* LIN Error Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t SZF:1; /* Stuck at Zero Flag */ + uint32_t OCF:1; /* Output Compare Flag */ + uint32_t BEF:1; /* Bit Error Flag */ + uint32_t CEF:1; /* Checksum Error Flag */ + uint32_t SFEF:1; /* Sync Field Error Flag */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t SDEF:1; /* Sync Delimiter Error Flag */ +#else + uint32_t BDEF:1; /* deprecated name - please avoid */ +#endif + uint32_t IDPEF:1; /* ID Parity Error Flag */ + uint32_t FEF:1; /* Framing Error Flag */ + uint32_t BOF:1; /* Buffer Overrun Flag */ + uint32_t:6; + uint32_t NF:1; /* Noise Flag */ + } B; + } LINFLEX_LINESR_32B_tag; + + typedef union { /* UART Mode Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t TDFL_TFC:3; /* Transmitter Data Field Length/TX FIFO Counter */ + uint32_t RDFL_RFC0:3; /* Reception Data Field Length/RX FIFO Counter */ + uint32_t RFBM:1; /* RX FIFO/ Buffer Mode */ + uint32_t TFBM:1; /* TX FIFO/ Buffer Mode */ + uint32_t WL1:1; /* Word Length in UART mode - bit 1 */ + uint32_t PC1:1; /* Parity Check - bit 1 */ + uint32_t RXEN:1; /* Receiver Enable */ + uint32_t TXEN:1; /* Transmitter Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t PC0:1; /* Parity Check - bit 0 */ +#else + uint32_t OP:1; /* deprecated name - please avoid */ +#endif + uint32_t PCE:1; /* Parity Control Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t WL0:1; /* Word Length in UART Mode - bit 0 */ +#else + uint32_t WL:1; /* deprecated name - please avoid */ +#endif + uint32_t UART:1; /* UART Mode */ + } B; + } LINFLEX_UARTCR_32B_tag; + + typedef union { /* UART Mode Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t SZF:1; /* Stuck at Zero Flag */ + uint32_t OCF:1; /* Output Compare Flag */ + uint32_t PE:4; /* Parity Error Flag */ + uint32_t RMB:1; /* Release Message Buffer */ + uint32_t FEF:1; /* Framing Error Flag */ + uint32_t BOF:1; /* Buffer Overrun Flag */ + uint32_t RDI:1; /* Receiver Data Input Signal */ + uint32_t WUF:1; /* Wakeup Flag */ + uint32_t:1; + uint32_t TO:1; /* Time Out */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t DRF_RFE:1; /* Data Reception Completed Flag/RX FIFO Empty Flag */ +#else + uint32_t DRF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t DTF_TFF:1; /* Data Transmission Completed Flag/TX FIFO Full Flag */ +#else + uint32_t DTF:1; /* deprecated name - please avoid */ +#endif + uint32_t NF:1; /* Noise Flag */ + } B; + } LINFLEX_UARTSR_32B_tag; + + typedef union { /* LIN Time-Out Control Status Register */ + uint32_t R; + struct { + uint32_t:21; +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t MODE:1; /* Time-out Counter Mode */ +#else + uint32_t LTOM:1; /* deprecated name - please avoid */ +#endif + uint32_t IOT:1; /* Idle on Timeout */ + uint32_t TOCE:1; /* Time-Out Counter Enable */ + uint32_t CNT:8; /* Counter Value */ + } B; + } LINFLEX_LINTCSR_32B_tag; + + typedef union { /* LIN Output Compare Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t OC2:8; /* Output Compare Value 2 */ + uint32_t OC1:8; /* Output Compare Value 1 */ + } B; + } LINFLEX_LINOCR_32B_tag; + + typedef union { /* LIN Time-Out Control Register */ + uint32_t R; + struct { + uint32_t:20; + uint32_t RTO:4; /* Response Time-Out Value */ + uint32_t:1; + uint32_t HTO:7; /* Header Time-Out Value */ + } B; + } LINFLEX_LINTOCR_32B_tag; + + typedef union { /* LIN Fractional Baud Rate Register */ + uint32_t R; + struct { + uint32_t:28; +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t FBR:4; /* Fractional Baud Rates */ +#else + uint32_t DIV_F:4; /* deprecated name - please avoid */ +#endif + } B; + } LINFLEX_LINFBRR_32B_tag; + + typedef union { /* LIN Integer Baud Rate Register */ + uint32_t R; + struct { + uint32_t:13; +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t IBR:19; /* Integer Baud Rates */ +#else + uint32_t DIV_M:19; /* deprecated name - please avoid */ +#endif + } B; + } LINFLEX_LINIBRR_32B_tag; + + typedef union { /* LIN Checksum Field Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t CF:8; /* Checksum Bits */ + } B; + } LINFLEX_LINCFR_32B_tag; + + typedef union { /* LIN Control Register 2 */ + uint32_t R; + struct { + uint32_t:17; + uint32_t IOBE:1; /* Idle on Bit Error */ + uint32_t IOPE:1; /* Idle on Identifier Parity Error */ + uint32_t WURQ:1; /* Wakeup Generate Request */ + uint32_t DDRQ:1; /* Data Discard Request */ + uint32_t DTRQ:1; /* Data Transmission Request */ + uint32_t ABRQ:1; /* Abort Request */ + uint32_t HTRQ:1; /* Header Transmission Request */ + uint32_t:8; + } B; + } LINFLEX_LINCR2_32B_tag; + + typedef union { /* Buffer Identifier Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t DFL:6; /* Data Field Length */ + uint32_t DIR:1; /* Direction */ + uint32_t CCS:1; /* Classic Checksum */ + uint32_t:2; + uint32_t ID:6; /* Identifier */ + } B; + } LINFLEX_BIDR_32B_tag; + + typedef union { /* Buffer Data Register Least Significant */ + uint32_t R; + struct { + uint32_t DATA3:8; /* Data3 */ + uint32_t DATA2:8; /* Data2 */ + uint32_t DATA1:8; /* Data1 */ + uint32_t DATA0:8; /* Data0 */ + } B; + } LINFLEX_BDRL_32B_tag; + + typedef union { /* Buffer Data Register Most Significant */ + uint32_t R; + struct { + uint32_t DATA7:8; /* Data7 */ + uint32_t DATA6:8; /* Data6 */ + uint32_t DATA5:8; /* Data5 */ + uint32_t DATA4:8; /* Data4 */ + } B; + } LINFLEX_BDRM_32B_tag; + + typedef union { /* Identifier Filter Enable Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t FACT:8; /* Filter Active */ + } B; + } LINFLEX_IFER_32B_tag; + + typedef union { /* Identifier Filter Match Index */ + uint32_t R; + struct { + uint32_t:28; + uint32_t IFMI_IFMI:4; /* Filter Match Index */ + } B; + } LINFLEX_IFMI_32B_tag; + + typedef union { /* Identifier Filter Mode Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t IFM:4; /* Filter Mode */ + } B; + } LINFLEX_IFMR_32B_tag; + + + /* Register layout for all registers IFCR... */ + + typedef union { /* Identifier Filter Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t DFL:6; /* Data Field Length */ + uint32_t DIR:1; /* Direction */ + uint32_t CCS:1; /* Classic Checksum */ + uint32_t:2; + uint32_t ID:6; /* Identifier */ + } B; + } LINFLEX_IFCR_32B_tag; + + typedef union { /* Global Control Register */ + uint32_t R; + struct { + uint32_t:26; + uint32_t TDFBM:1; /* Transmit Data First Bit MSB */ + uint32_t RDFBM:1; /* Received Data First Bit MSB */ + uint32_t TDLIS:1; /* Transmit Data Level Inversion Selection */ + uint32_t RDLIS:1; /* Received Data Level Inversion Selection */ + uint32_t STOP:1; /* 1/2 stop bit configuration */ + uint32_t SR:1; /* Soft Reset */ + } B; + } LINFLEX_GCR_32B_tag; + + typedef union { /* UART Preset Time Out Register */ + uint32_t R; + struct { + uint32_t:20; + uint32_t PTO:12; /* Preset Time Out */ + } B; + } LINFLEX_UARTPTO_32B_tag; + + typedef union { /* UART Current Time Out Register */ + uint32_t R; + struct { + uint32_t:20; + uint32_t CTO:12; /* Current Time Out */ + } B; + } LINFLEX_UARTCTO_32B_tag; + + typedef union { /* DMA TX Enable Register */ + uint32_t R; + struct { + uint32_t:17; + uint32_t DTE:15; /* DMA Tx channel Enable */ + } B; + } LINFLEX_DMATXE_32B_tag; + + typedef union { /* DMA RX Enable Register */ + uint32_t R; + struct { + uint32_t:17; + uint32_t DRE:15; /* DMA Rx channel Enable */ + } B; + } LINFLEX_DMARXE_32B_tag; + + + + typedef struct LINFLEX_struct_tag { /* start of LINFLEX_tag */ + /* LIN Control Register */ + LINFLEX_LINCR1_32B_tag LINCR1; /* offset: 0x0000 size: 32 bit */ + /* LIN Interrupt Enable Register */ + LINFLEX_LINIER_32B_tag LINIER; /* offset: 0x0004 size: 32 bit */ + /* LIN Status Register */ + LINFLEX_LINSR_32B_tag LINSR; /* offset: 0x0008 size: 32 bit */ + /* LIN Error Status Register */ + LINFLEX_LINESR_32B_tag LINESR; /* offset: 0x000C size: 32 bit */ + /* UART Mode Control Register */ + LINFLEX_UARTCR_32B_tag UARTCR; /* offset: 0x0010 size: 32 bit */ + /* UART Mode Status Register */ + LINFLEX_UARTSR_32B_tag UARTSR; /* offset: 0x0014 size: 32 bit */ + /* LIN Time-Out Control Status Register */ + LINFLEX_LINTCSR_32B_tag LINTCSR; /* offset: 0x0018 size: 32 bit */ + /* LIN Output Compare Register */ + LINFLEX_LINOCR_32B_tag LINOCR; /* offset: 0x001C size: 32 bit */ + /* LIN Time-Out Control Register */ + LINFLEX_LINTOCR_32B_tag LINTOCR; /* offset: 0x0020 size: 32 bit */ + /* LIN Fractional Baud Rate Register */ + LINFLEX_LINFBRR_32B_tag LINFBRR; /* offset: 0x0024 size: 32 bit */ + /* LIN Integer Baud Rate Register */ + LINFLEX_LINIBRR_32B_tag LINIBRR; /* offset: 0x0028 size: 32 bit */ + /* LIN Checksum Field Register */ + LINFLEX_LINCFR_32B_tag LINCFR; /* offset: 0x002C size: 32 bit */ + /* LIN Control Register 2 */ + LINFLEX_LINCR2_32B_tag LINCR2; /* offset: 0x0030 size: 32 bit */ + /* Buffer Identifier Register */ + LINFLEX_BIDR_32B_tag BIDR; /* offset: 0x0034 size: 32 bit */ + /* Buffer Data Register Least Significant */ + LINFLEX_BDRL_32B_tag BDRL; /* offset: 0x0038 size: 32 bit */ + /* Buffer Data Register Most Significant */ + LINFLEX_BDRM_32B_tag BDRM; /* offset: 0x003C size: 32 bit */ + /* Identifier Filter Enable Register */ + LINFLEX_IFER_32B_tag IFER; /* offset: 0x0040 size: 32 bit */ + /* Identifier Filter Match Index */ + LINFLEX_IFMI_32B_tag IFMI; /* offset: 0x0044 size: 32 bit */ + /* Identifier Filter Mode Register */ + LINFLEX_IFMR_32B_tag IFMR; /* offset: 0x0048 size: 32 bit */ + union { + /* Identifier Filter Control Register */ + LINFLEX_IFCR_32B_tag IFCR[8]; /* offset: 0x004C (0x0004 x 8) */ + + struct { + /* Identifier Filter Control Register */ + LINFLEX_IFCR_32B_tag IFCR0; /* offset: 0x004C size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR1; /* offset: 0x0050 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR2; /* offset: 0x0054 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR3; /* offset: 0x0058 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR4; /* offset: 0x005C size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR5; /* offset: 0x0060 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR6; /* offset: 0x0064 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR7; /* offset: 0x0068 size: 32 bit */ + }; + + }; + int8_t LINFLEX_reserved_006C[32]; + /* Global Control Register */ + LINFLEX_GCR_32B_tag GCR; /* offset: 0x008C size: 32 bit */ + /* UART Preset Time Out Register */ + LINFLEX_UARTPTO_32B_tag UARTPTO; /* offset: 0x0090 size: 32 bit */ + /* UART Current Time Out Register */ + LINFLEX_UARTCTO_32B_tag UARTCTO; /* offset: 0x0094 size: 32 bit */ + /* DMA TX Enable Register */ + LINFLEX_DMATXE_32B_tag DMATXE; /* offset: 0x0098 size: 32 bit */ + /* DMA RX Enable Register */ + LINFLEX_DMARXE_32B_tag DMARXE; /* offset: 0x009C size: 32 bit */ + } LINFLEX_tag; + + +#define LINFLEX0 (*(volatile LINFLEX_tag *) 0xFFE40000UL) +#define LINFLEX1 (*(volatile LINFLEX_tag *) 0xFFE44000UL) + + + +/****************************************************************/ +/* */ +/* Module: CRC */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers CFG... */ + + typedef union { /* CRC_CFG - CRC Configuration register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + struct { + uint32_t:29; + uint32_t POLYG:1; /* Polynomal selection 0- CRC-CCITT, 1- CRC-CRC-32 INV selection */ + uint32_t SWAP:1; /* SWAP selection */ + uint32_t INV:1; /* INV selection */ + } B; + } CRC_CFG_32B_tag; + + + /* Register layout for all registers INP... */ + + typedef union { /* CRC_INP - CRC Input register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + } CRC_INP_32B_tag; + + + /* Register layout for all registers CSTAT... */ + + typedef union { /* CRC_STATUS - CRC Status register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + } CRC_CSTAT_32B_tag; + + + /* Register layout for all registers OUTP... */ + + typedef union { /* CRC_STATUS - CRC OUTPUT register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + } CRC_OUTP_32B_tag; + + + typedef struct CRC_CNTX_struct_tag { + + /* CRC_CFG - CRC Configuration register */ + CRC_CFG_32B_tag CFG; /* relative offset: 0x0000 */ + /* CRC_INP - CRC Input register */ + CRC_INP_32B_tag INP; /* relative offset: 0x0004 */ + /* CRC_STATUS - CRC Status register */ + CRC_CSTAT_32B_tag CSTAT; /* relative offset: 0x0008 */ + /* CRC_STATUS - CRC OUTPUT register */ + CRC_OUTP_32B_tag OUTP; /* relative offset: 0x000C */ + + } CRC_CNTX_tag; + + + typedef struct CRC_struct_tag { /* start of CRC_tag */ + union { + /* Register set CNTX */ + CRC_CNTX_tag CNTX[3]; /* offset: 0x0000 (0x0010 x 3) */ + + struct { + /* CRC_CFG - CRC Configuration register */ + CRC_CFG_32B_tag CFG0; /* offset: 0x0000 size: 32 bit */ + /* CRC_INP - CRC Input register */ + CRC_INP_32B_tag INP0; /* offset: 0x0004 size: 32 bit */ + /* CRC_STATUS - CRC Status register */ + CRC_CSTAT_32B_tag CSTAT0; /* offset: 0x0008 size: 32 bit */ + /* CRC_STATUS - CRC OUTPUT register */ + CRC_OUTP_32B_tag OUTP0; /* offset: 0x000C size: 32 bit */ + /* CRC_CFG - CRC Configuration register */ + CRC_CFG_32B_tag CFG1; /* offset: 0x0010 size: 32 bit */ + /* CRC_INP - CRC Input register */ + CRC_INP_32B_tag INP1; /* offset: 0x0014 size: 32 bit */ + /* CRC_STATUS - CRC Status register */ + CRC_CSTAT_32B_tag CSTAT1; /* offset: 0x0018 size: 32 bit */ + /* CRC_STATUS - CRC OUTPUT register */ + CRC_OUTP_32B_tag OUTP1; /* offset: 0x001C size: 32 bit */ + /* CRC_CFG - CRC Configuration register */ + CRC_CFG_32B_tag CFG2; /* offset: 0x0020 size: 32 bit */ + /* CRC_INP - CRC Input register */ + CRC_INP_32B_tag INP2; /* offset: 0x0024 size: 32 bit */ + /* CRC_STATUS - CRC Status register */ + CRC_CSTAT_32B_tag CSTAT2; /* offset: 0x0028 size: 32 bit */ + /* CRC_STATUS - CRC OUTPUT register */ + CRC_OUTP_32B_tag OUTP2; /* offset: 0x002C size: 32 bit */ + }; + + }; + } CRC_tag; + + +#define CRC (*(volatile CRC_tag *) 0xFFE68000UL) + + + +/****************************************************************/ +/* */ +/* Module: FCCU */ +/* */ +/****************************************************************/ + + typedef union { /* FCCU Control Register */ + uint32_t R; + struct { + uint32_t:23; + uint32_t NVML:1; /* NVM configuration loaded */ + uint32_t OPS:2; /* Operation status */ + uint32_t:1; + uint32_t OPR:5; /* Operation run */ + } B; + } FCCU_CTRL_32B_tag; + + typedef union { /* FCCU CTRL Key Register */ + uint32_t R; + } FCCU_CTRLK_32B_tag; + + typedef union { /* FCCU Configuration Register */ + uint32_t R; + struct { + uint32_t:10; + uint32_t RCCE1:1; /* RCC1 enable */ + uint32_t RCCE0:1; /* RCC0 enable */ + uint32_t SMRT:4; /* Safe Mode Request Timer */ + uint32_t:4; + uint32_t CM:1; /* Config mode */ + uint32_t SM:1; /* Switching mode */ + uint32_t PS:1; /* Polarity Selection */ + uint32_t FOM:3; /* Fault Output Mode Selection */ + uint32_t FOP:6; /* Fault Output Prescaler */ + } B; + } FCCU_CFG_32B_tag; + + typedef union { /* FCCU CF Configuration Register 0 */ + uint32_t R; + struct { + uint32_t CFC31:1; /* CF 31 configuration */ + uint32_t CFC30:1; /* CF 30 configuration */ + uint32_t CFC29:1; /* CF 29 configuration */ + uint32_t CFC28:1; /* CF 28 configuration */ + uint32_t CFC27:1; /* CF 27 configuration */ + uint32_t CFC26:1; /* CF 26 configuration */ + uint32_t CFC25:1; /* CF 25 configuration */ + uint32_t CFC24:1; /* CF 24 configuration */ + uint32_t CFC23:1; /* CF 23 configuration */ + uint32_t CFC22:1; /* CF 22 configuration */ + uint32_t CFC21:1; /* CF 21 configuration */ + uint32_t CFC20:1; /* CF 20 configuration */ + uint32_t CFC19:1; /* CF 19 configuration */ + uint32_t CFC18:1; /* CF 18 configuration */ + uint32_t CFC17:1; /* CF 17 configuration */ + uint32_t CFC16:1; /* CF 16 configuration */ + uint32_t CFC15:1; /* CF 15 configuration */ + uint32_t CFC14:1; /* CF 14 configuration */ + uint32_t CFC13:1; /* CF 13 configuration */ + uint32_t CFC12:1; /* CF 12 configuration */ + uint32_t CFC11:1; /* CF 11 configuration */ + uint32_t CFC10:1; /* CF 10 configuration */ + uint32_t CFC9:1; /* CF 9 configuration */ + uint32_t CFC8:1; /* CF 8 configuration */ + uint32_t CFC7:1; /* CF 7 configuration */ + uint32_t CFC6:1; /* CF 6 configuration */ + uint32_t CFC5:1; /* CF 5 configuration */ + uint32_t CFC4:1; /* CF 4 configuration */ + uint32_t CFC3:1; /* CF 3 configuration */ + uint32_t CFC2:1; /* CF 2 configuration */ + uint32_t CFC1:1; /* CF 1 configuration */ + uint32_t CFC0:1; /* CF 0 configuration */ + } B; + } FCCU_CF_CFG0_32B_tag; + + typedef union { /* FCCU CF Configuration Register 1 */ + uint32_t R; + struct { + uint32_t CFC63:1; /* CF 63 configuration */ + uint32_t CFC62:1; /* CF 62 configuration */ + uint32_t CFC61:1; /* CF 61 configuration */ + uint32_t CFC60:1; /* CF 60 configuration */ + uint32_t CFC59:1; /* CF 59 configuration */ + uint32_t CFC58:1; /* CF 58 configuration */ + uint32_t CFC57:1; /* CF 57 configuration */ + uint32_t CFC56:1; /* CF 56 configuration */ + uint32_t CFC55:1; /* CF 55 configuration */ + uint32_t CFC54:1; /* CF 54 configuration */ + uint32_t CFC53:1; /* CF 53 configuration */ + uint32_t CFC52:1; /* CF 52 configuration */ + uint32_t CFC51:1; /* CF 51 configuration */ + uint32_t CFC50:1; /* CF 50 configuration */ + uint32_t CFC49:1; /* CF 49 configuration */ + uint32_t CFC48:1; /* CF 48 configuration */ + uint32_t CFC47:1; /* CF 47 configuration */ + uint32_t CFC46:1; /* CF 46 configuration */ + uint32_t CFC45:1; /* CF 45 configuration */ + uint32_t CFC44:1; /* CF 44 configuration */ + uint32_t CFC43:1; /* CF 43 configuration */ + uint32_t CFC42:1; /* CF 42 configuration */ + uint32_t CFC41:1; /* CF 41 configuration */ + uint32_t CFC40:1; /* CF 40 configuration */ + uint32_t CFC39:1; /* CF 39 configuration */ + uint32_t CFC38:1; /* CF 38 configuration */ + uint32_t CFC37:1; /* CF 37 configuration */ + uint32_t CFC36:1; /* CF 36 configuration */ + uint32_t CFC35:1; /* CF 35 configuration */ + uint32_t CFC34:1; /* CF 34 configuration */ + uint32_t CFC33:1; /* CF 33 configuration */ + uint32_t CFC32:1; /* CF 32 configuration */ + } B; + } FCCU_CF_CFG1_32B_tag; + + typedef union { /* FCCU CF Configuration Register 2 */ + uint32_t R; + struct { + uint32_t CFC95:1; /* CF 95 configuration */ + uint32_t CFC94:1; /* CF 94 configuration */ + uint32_t CFC93:1; /* CF 93 configuration */ + uint32_t CFC92:1; /* CF 92 configuration */ + uint32_t CFC91:1; /* CF 91 configuration */ + uint32_t CFC90:1; /* CF 90 configuration */ + uint32_t CFC89:1; /* CF 89 configuration */ + uint32_t CFC88:1; /* CF 88 configuration */ + uint32_t CFC87:1; /* CF 87 configuration */ + uint32_t CFC86:1; /* CF 86 configuration */ + uint32_t CFC85:1; /* CF 85 configuration */ + uint32_t CFC84:1; /* CF 84 configuration */ + uint32_t CFC83:1; /* CF 83 configuration */ + uint32_t CFC82:1; /* CF 82 configuration */ + uint32_t CFC81:1; /* CF 81 configuration */ + uint32_t CFC80:1; /* CF 80 configuration */ + uint32_t CFC79:1; /* CF 79 configuration */ + uint32_t CFC78:1; /* CF 78 configuration */ + uint32_t CFC77:1; /* CF 77 configuration */ + uint32_t CFC76:1; /* CF 76 configuration */ + uint32_t CFC75:1; /* CF 75 configuration */ + uint32_t CFC74:1; /* CF 74 configuration */ + uint32_t CFC73:1; /* CF 73 configuration */ + uint32_t CFC72:1; /* CF 72 configuration */ + uint32_t CFC71:1; /* CF 71 configuration */ + uint32_t CFC70:1; /* CF 70 configuration */ + uint32_t CFC69:1; /* CF 69 configuration */ + uint32_t CFC68:1; /* CF 68 configuration */ + uint32_t CFC67:1; /* CF 67 configuration */ + uint32_t CFC66:1; /* CF 66 configuration */ + uint32_t CFC65:1; /* CF 65 configuration */ + uint32_t CFC64:1; /* CF 64 configuration */ + } B; + } FCCU_CF_CFG2_32B_tag; + + typedef union { /* FCCU CF Configuration Register 3 */ + uint32_t R; + struct { + uint32_t CFC127:1; /* CF 127 configuration */ + uint32_t CFC126:1; /* CF 126 configuration */ + uint32_t CFC125:1; /* CF 125 configuration */ + uint32_t CFC124:1; /* CF 124 configuration */ + uint32_t CFC123:1; /* CF 123 configuration */ + uint32_t CFC122:1; /* CF 122 configuration */ + uint32_t CFC121:1; /* CF 121 configuration */ + uint32_t CFC120:1; /* CF 120 configuration */ + uint32_t CFC119:1; /* CF 119 configuration */ + uint32_t CFC118:1; /* CF 118 configuration */ + uint32_t CFC117:1; /* CF 117 configuration */ + uint32_t CFC116:1; /* CF 116 configuration */ + uint32_t CFC115:1; /* CF 115 configuration */ + uint32_t CFC114:1; /* CF 114 configuration */ + uint32_t CFC113:1; /* CF 113 configuration */ + uint32_t CFC112:1; /* CF 112 configuration */ + uint32_t CFC111:1; /* CF 111 configuration */ + uint32_t CFC110:1; /* CF 110 configuration */ + uint32_t CFC109:1; /* CF 109 configuration */ + uint32_t CFC108:1; /* CF 108 configuration */ + uint32_t CFC107:1; /* CF 107 configuration */ + uint32_t CFC106:1; /* CF 106 configuration */ + uint32_t CFC105:1; /* CF 105 configuration */ + uint32_t CFC104:1; /* CF 104 configuration */ + uint32_t CFC103:1; /* CF 103 configuration */ + uint32_t CFC102:1; /* CF 102 configuration */ + uint32_t CFC101:1; /* CF 101 configuration */ + uint32_t CFC100:1; /* CF 100 configuration */ + uint32_t CFC99:1; /* CF 99 configuration */ + uint32_t CFC98:1; /* CF 98 configuration */ + uint32_t CFC97:1; /* CF 97 configuration */ + uint32_t CFC96:1; /* CF 96 configuration */ + } B; + } FCCU_CF_CFG3_32B_tag; + + typedef union { /* FCCU NCF Configuration Register 0 */ + uint32_t R; + struct { + uint32_t NCFC31:1; /* NCF 31 configuration */ + uint32_t NCFC30:1; /* NCF 30 configuration */ + uint32_t NCFC29:1; /* NCF 29 configuration */ + uint32_t NCFC28:1; /* NCF 28 configuration */ + uint32_t NCFC27:1; /* NCF 27 configuration */ + uint32_t NCFC26:1; /* NCF 26 configuration */ + uint32_t NCFC25:1; /* NCF 25 configuration */ + uint32_t NCFC24:1; /* NCF 24 configuration */ + uint32_t NCFC23:1; /* NCF 23 configuration */ + uint32_t NCFC22:1; /* NCF 22 configuration */ + uint32_t NCFC21:1; /* NCF 21 configuration */ + uint32_t NCFC20:1; /* NCF 20 configuration */ + uint32_t NCFC19:1; /* NCF 19 configuration */ + uint32_t NCFC18:1; /* NCF 18 configuration */ + uint32_t NCFC17:1; /* NCF 17 configuration */ + uint32_t NCFC16:1; /* NCF 16 configuration */ + uint32_t NCFC15:1; /* NCF 15 configuration */ + uint32_t NCFC14:1; /* NCF 14 configuration */ + uint32_t NCFC13:1; /* NCF 13 configuration */ + uint32_t NCFC12:1; /* NCF 12 configuration */ + uint32_t NCFC11:1; /* NCF 11 configuration */ + uint32_t NCFC10:1; /* NCF 10 configuration */ + uint32_t NCFC9:1; /* NCF 9 configuration */ + uint32_t NCFC8:1; /* NCF 8 configuration */ + uint32_t NCFC7:1; /* NCF 7 configuration */ + uint32_t NCFC6:1; /* NCF 6 configuration */ + uint32_t NCFC5:1; /* NCF 5 configuration */ + uint32_t NCFC4:1; /* NCF 4 configuration */ + uint32_t NCFC3:1; /* NCF 3 configuration */ + uint32_t NCFC2:1; /* NCF 2 configuration */ + uint32_t NCFC1:1; /* NCF 1 configuration */ + uint32_t NCFC0:1; /* NCF 0 configuration */ + } B; + } FCCU_NCF_CFG0_32B_tag; + + typedef union { /* FCCU NCF Configuration Register 1 */ + uint32_t R; + struct { + uint32_t NCFC63:1; /* NCF 63 configuration */ + uint32_t NCFC62:1; /* NCF 62 configuration */ + uint32_t NCFC61:1; /* NCF 61 configuration */ + uint32_t NCFC60:1; /* NCF 60 configuration */ + uint32_t NCFC59:1; /* NCF 59 configuration */ + uint32_t NCFC58:1; /* NCF 58 configuration */ + uint32_t NCFC57:1; /* NCF 57 configuration */ + uint32_t NCFC56:1; /* NCF 56 configuration */ + uint32_t NCFC55:1; /* NCF 55 configuration */ + uint32_t NCFC54:1; /* NCF 54 configuration */ + uint32_t NCFC53:1; /* NCF 53 configuration */ + uint32_t NCFC52:1; /* NCF 52 configuration */ + uint32_t NCFC51:1; /* NCF 51 configuration */ + uint32_t NCFC50:1; /* NCF 50 configuration */ + uint32_t NCFC49:1; /* NCF 49 configuration */ + uint32_t NCFC48:1; /* NCF 48 configuration */ + uint32_t NCFC47:1; /* NCF 47 configuration */ + uint32_t NCFC46:1; /* NCF 46 configuration */ + uint32_t NCFC45:1; /* NCF 45 configuration */ + uint32_t NCFC44:1; /* NCF 44 configuration */ + uint32_t NCFC43:1; /* NCF 43 configuration */ + uint32_t NCFC42:1; /* NCF 42 configuration */ + uint32_t NCFC41:1; /* NCF 41 configuration */ + uint32_t NCFC40:1; /* NCF 40 configuration */ + uint32_t NCFC39:1; /* NCF 39 configuration */ + uint32_t NCFC38:1; /* NCF 38 configuration */ + uint32_t NCFC37:1; /* NCF 37 configuration */ + uint32_t NCFC36:1; /* NCF 36 configuration */ + uint32_t NCFC35:1; /* NCF 35 configuration */ + uint32_t NCFC34:1; /* NCF 34 configuration */ + uint32_t NCFC33:1; /* NCF 33 configuration */ + uint32_t NCFC32:1; /* NCF 32 configuration */ + } B; + } FCCU_NCF_CFG1_32B_tag; + + typedef union { /* FCCU NCF Configuration Register 2 */ + uint32_t R; + struct { + uint32_t NCFC95:1; /* NCF 95 configuration */ + uint32_t NCFC94:1; /* NCF 94 configuration */ + uint32_t NCFC93:1; /* NCF 93 configuration */ + uint32_t NCFC92:1; /* NCF 92 configuration */ + uint32_t NCFC91:1; /* NCF 91 configuration */ + uint32_t NCFC90:1; /* NCF 90 configuration */ + uint32_t NCFC89:1; /* NCF 89 configuration */ + uint32_t NCFC88:1; /* NCF 88 configuration */ + uint32_t NCFC87:1; /* NCF 87 configuration */ + uint32_t NCFC86:1; /* NCF 86 configuration */ + uint32_t NCFC85:1; /* NCF 85 configuration */ + uint32_t NCFC84:1; /* NCF 84 configuration */ + uint32_t NCFC83:1; /* NCF 83 configuration */ + uint32_t NCFC82:1; /* NCF 82 configuration */ + uint32_t NCFC81:1; /* NCF 81 configuration */ + uint32_t NCFC80:1; /* NCF 80 configuration */ + uint32_t NCFC79:1; /* NCF 79 configuration */ + uint32_t NCFC78:1; /* NCF 78 configuration */ + uint32_t NCFC77:1; /* NCF 77 configuration */ + uint32_t NCFC76:1; /* NCF 76 configuration */ + uint32_t NCFC75:1; /* NCF 75 configuration */ + uint32_t NCFC74:1; /* NCF 74 configuration */ + uint32_t NCFC73:1; /* NCF 73 configuration */ + uint32_t NCFC72:1; /* NCF 72 configuration */ + uint32_t NCFC71:1; /* NCF 71 configuration */ + uint32_t NCFC70:1; /* NCF 70 configuration */ + uint32_t NCFC69:1; /* NCF 69 configuration */ + uint32_t NCFC68:1; /* NCF 68 configuration */ + uint32_t NCFC67:1; /* NCF 67 configuration */ + uint32_t NCFC66:1; /* NCF 66 configuration */ + uint32_t NCFC65:1; /* NCF 65 configuration */ + uint32_t NCFC64:1; /* NCF 64 configuration */ + } B; + } FCCU_NCF_CFG2_32B_tag; + + typedef union { /* FCCU NCF Configuration Register 3 */ + uint32_t R; + struct { + uint32_t NCFC127:1; /* NCF 127 configuration */ + uint32_t NCFC126:1; /* NCF 126 configuration */ + uint32_t NCFC125:1; /* NCF 125 configuration */ + uint32_t NCFC124:1; /* NCF 124 configuration */ + uint32_t NCFC123:1; /* NCF 123 configuration */ + uint32_t NCFC122:1; /* NCF 122 configuration */ + uint32_t NCFC121:1; /* NCF 121 configuration */ + uint32_t NCFC120:1; /* NCF 120 configuration */ + uint32_t NCFC119:1; /* NCF 119 configuration */ + uint32_t NCFC118:1; /* NCF 118 configuration */ + uint32_t NCFC117:1; /* NCF 117 configuration */ + uint32_t NCFC116:1; /* NCF 116 configuration */ + uint32_t NCFC115:1; /* NCF 115 configuration */ + uint32_t NCFC114:1; /* NCF 114 configuration */ + uint32_t NCFC113:1; /* NCF 113 configuration */ + uint32_t NCFC112:1; /* NCF 112 configuration */ + uint32_t NCFC111:1; /* NCF 111 configuration */ + uint32_t NCFC110:1; /* NCF 110 configuration */ + uint32_t NCFC109:1; /* NCF 109 configuration */ + uint32_t NCFC108:1; /* NCF 108 configuration */ + uint32_t NCFC107:1; /* NCF 107 configuration */ + uint32_t NCFC106:1; /* NCF 106 configuration */ + uint32_t NCFC105:1; /* NCF 105 configuration */ + uint32_t NCFC104:1; /* NCF 104 configuration */ + uint32_t NCFC103:1; /* NCF 103 configuration */ + uint32_t NCFC102:1; /* NCF 102 configuration */ + uint32_t NCFC101:1; /* NCF 101 configuration */ + uint32_t NCFC100:1; /* NCF 100 configuration */ + uint32_t NCFC99:1; /* NCF 99 configuration */ + uint32_t NCFC98:1; /* NCF 98 configuration */ + uint32_t NCFC97:1; /* NCF 97 configuration */ + uint32_t NCFC96:1; /* NCF 96 configuration */ + } B; + } FCCU_NCF_CFG3_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 0 */ + uint32_t R; + struct { + uint32_t CFSC15:2; /* CF 15 state configuration */ + uint32_t CFSC14:2; /* CF 14 state configuration */ + uint32_t CFSC13:2; /* CF 13 state configuration */ + uint32_t CFSC12:2; /* CF 12 state configuration */ + uint32_t CFSC11:2; /* CF 11 state configuration */ + uint32_t CFSC10:2; /* CF 10 state configuration */ + uint32_t CFSC9:2; /* CF 9 state configuration */ + uint32_t CFSC8:2; /* CF 8 state configuration */ + uint32_t CFSC7:2; /* CF 7 state configuration */ + uint32_t CFSC6:2; /* CF 6 state configuration */ + uint32_t CFSC5:2; /* CF 5 state configuration */ + uint32_t CFSC4:2; /* CF 4 state configuration */ + uint32_t CFSC3:2; /* CF 3 state configuration */ + uint32_t CFSC2:2; /* CF 2 state configuration */ + uint32_t CFSC1:2; /* CF 1 state configuration */ + uint32_t CFSC0:2; /* CF 0 state configuration */ + } B; + } FCCU_CFS_CFG0_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 1 */ + uint32_t R; + struct { + uint32_t CFSC31:2; /* CF 31 state configuration */ + uint32_t CFSC30:2; /* CF 30 state configuration */ + uint32_t CFSC29:2; /* CF 29 state configuration */ + uint32_t CFSC28:2; /* CF 28 state configuration */ + uint32_t CFSC27:2; /* CF 27 state configuration */ + uint32_t CFSC26:2; /* CF 26 state configuration */ + uint32_t CFSC25:2; /* CF 25 state configuration */ + uint32_t CFSC24:2; /* CF 24 state configuration */ + uint32_t CFSC23:2; /* CF 23 state configuration */ + uint32_t CFSC22:2; /* CF 22 state configuration */ + uint32_t CFSC21:2; /* CF 21 state configuration */ + uint32_t CFSC20:2; /* CF 20 state configuration */ + uint32_t CFSC19:2; /* CF 19 state configuration */ + uint32_t CFSC18:2; /* CF 18 state configuration */ + uint32_t CFSC17:2; /* CF 17 state configuration */ + uint32_t CFSC16:2; /* CF 16 state configuration */ + } B; + } FCCU_CFS_CFG1_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 2 */ + uint32_t R; + struct { + uint32_t CFSC47:2; /* CF 47 state configuration */ + uint32_t CFSC46:2; /* CF 46 state configuration */ + uint32_t CFSC45:2; /* CF 45 state configuration */ + uint32_t CFSC44:2; /* CF 44 state configuration */ + uint32_t CFSC43:2; /* CF 43 state configuration */ + uint32_t CFSC42:2; /* CF 42 state configuration */ + uint32_t CFSC41:2; /* CF 41 state configuration */ + uint32_t CFSC40:2; /* CF 40 state configuration */ + uint32_t CFSC39:2; /* CF 39 state configuration */ + uint32_t CFSC38:2; /* CF 38 state configuration */ + uint32_t CFSC37:2; /* CF 37 state configuration */ + uint32_t CFSC36:2; /* CF 36 state configuration */ + uint32_t CFSC35:2; /* CF 35 state configuration */ + uint32_t CFSC34:2; /* CF 34 state configuration */ + uint32_t CFSC33:2; /* CF 33 state configuration */ + uint32_t CFSC32:2; /* CF 32 state configuration */ + } B; + } FCCU_CFS_CFG2_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 3 */ + uint32_t R; + struct { + uint32_t CFSC63:2; /* CF 63 state configuration */ + uint32_t CFSC62:2; /* CF 62 state configuration */ + uint32_t CFSC61:2; /* CF 61 state configuration */ + uint32_t CFSC60:2; /* CF 60 state configuration */ + uint32_t CFSC59:2; /* CF 59 state configuration */ + uint32_t CFSC58:2; /* CF 58 state configuration */ + uint32_t CFSC57:2; /* CF 57 state configuration */ + uint32_t CFSC56:2; /* CF 56 state configuration */ + uint32_t CFSC55:2; /* CF 55 state configuration */ + uint32_t CFSC54:2; /* CF 54 state configuration */ + uint32_t CFSC53:2; /* CF 53 state configuration */ + uint32_t CFSC52:2; /* CF 52 state configuration */ + uint32_t CFSC51:2; /* CF 51 state configuration */ + uint32_t CFSC50:2; /* CF 50 state configuration */ + uint32_t CFSC49:2; /* CF 49 state configuration */ + uint32_t CFSC48:2; /* CF 48 state configuration */ + } B; + } FCCU_CFS_CFG3_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 4 */ + uint32_t R; + struct { + uint32_t CFSC79:2; /* CF 79 state configuration */ + uint32_t CFSC78:2; /* CF 78 state configuration */ + uint32_t CFSC77:2; /* CF 77 state configuration */ + uint32_t CFSC76:2; /* CF 76 state configuration */ + uint32_t CFSC75:2; /* CF 75 state configuration */ + uint32_t CFSC74:2; /* CF 74 state configuration */ + uint32_t CFSC73:2; /* CF 73 state configuration */ + uint32_t CFSC72:2; /* CF 72 state configuration */ + uint32_t CFSC71:2; /* CF 71 state configuration */ + uint32_t CFSC70:2; /* CF 70 state configuration */ + uint32_t CFSC69:2; /* CF 69 state configuration */ + uint32_t CFSC68:2; /* CF 68 state configuration */ + uint32_t CFSC67:2; /* CF 67 state configuration */ + uint32_t CFSC66:2; /* CF 66 state configuration */ + uint32_t CFSC65:2; /* CF 65 state configuration */ + uint32_t CFSC64:2; /* CF 64 state configuration */ + } B; + } FCCU_CFS_CFG4_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 5 */ + uint32_t R; + struct { + uint32_t CFSC95:2; /* CF 95 state configuration */ + uint32_t CFSC94:2; /* CF 94 state configuration */ + uint32_t CFSC93:2; /* CF 93 state configuration */ + uint32_t CFSC92:2; /* CF 92 state configuration */ + uint32_t CFSC91:2; /* CF 91 state configuration */ + uint32_t CFSC90:2; /* CF 90 state configuration */ + uint32_t CFSC89:2; /* CF 89 state configuration */ + uint32_t CFSC88:2; /* CF 88 state configuration */ + uint32_t CFSC87:2; /* CF 87 state configuration */ + uint32_t CFSC86:2; /* CF 86 state configuration */ + uint32_t CFSC85:2; /* CF 85 state configuration */ + uint32_t CFSC84:2; /* CF 84 state configuration */ + uint32_t CFSC83:2; /* CF 83 state configuration */ + uint32_t CFSC82:2; /* CF 82 state configuration */ + uint32_t CFSC81:2; /* CF 81 state configuration */ + uint32_t CFSC80:2; /* CF 80 state configuration */ + } B; + } FCCU_CFS_CFG5_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 6 */ + uint32_t R; + struct { + uint32_t CFSC111:2; /* CF 111 state configuration */ + uint32_t CFSC110:2; /* CF 110 state configuration */ + uint32_t CFSC109:2; /* CF 109 state configuration */ + uint32_t CFSC108:2; /* CF 108 state configuration */ + uint32_t CFSC107:2; /* CF 107 state configuration */ + uint32_t CFSC106:2; /* CF 106 state configuration */ + uint32_t CFSC105:2; /* CF 105 state configuration */ + uint32_t CFSC104:2; /* CF 104 state configuration */ + uint32_t CFSC103:2; /* CF 103 state configuration */ + uint32_t CFSC102:2; /* CF 102 state configuration */ + uint32_t CFSC101:2; /* CF 101 state configuration */ + uint32_t CFSC100:2; /* CF 100 state configuration */ + uint32_t CFSC99:2; /* CF 99 state configuration */ + uint32_t CFSC98:2; /* CF 98 state configuration */ + uint32_t CFSC97:2; /* CF 97 state configuration */ + uint32_t CFSC96:2; /* CF 96 state configuration */ + } B; + } FCCU_CFS_CFG6_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 7 */ + uint32_t R; + struct { + uint32_t CFSC127:2; /* CF 127 state configuration */ + uint32_t CFSC126:2; /* CF 126 state configuration */ + uint32_t CFSC125:2; /* CF 125 state configuration */ + uint32_t CFSC124:2; /* CF 124 state configuration */ + uint32_t CFSC123:2; /* CF 123 state configuration */ + uint32_t CFSC122:2; /* CF 122 state configuration */ + uint32_t CFSC121:2; /* CF 121 state configuration */ + uint32_t CFSC120:2; /* CF 120 state configuration */ + uint32_t CFSC119:2; /* CF 119 state configuration */ + uint32_t CFSC118:2; /* CF 118 state configuration */ + uint32_t CFSC117:2; /* CF 117 state configuration */ + uint32_t CFSC116:2; /* CF 116 state configuration */ + uint32_t CFSC115:2; /* CF 115 state configuration */ + uint32_t CFSC114:2; /* CF 114 state configuration */ + uint32_t CFSC113:2; /* CF 113 state configuration */ + uint32_t CFSC112:2; /* CF 112 state configuration */ + } B; + } FCCU_CFS_CFG7_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 0 */ + uint32_t R; + struct { + uint32_t NCFSC15:2; /* NCF 15 state configuration */ + uint32_t NCFSC14:2; /* NCF 14 state configuration */ + uint32_t NCFSC13:2; /* NCF 13 state configuration */ + uint32_t NCFSC12:2; /* NCF 12 state configuration */ + uint32_t NCFSC11:2; /* NCF 11 state configuration */ + uint32_t NCFSC10:2; /* NCF 10 state configuration */ + uint32_t NCFSC9:2; /* NCF 9 state configuration */ + uint32_t NCFSC8:2; /* NCF 8 state configuration */ + uint32_t NCFSC7:2; /* NCF 7 state configuration */ + uint32_t NCFSC6:2; /* NCF 6 state configuration */ + uint32_t NCFSC5:2; /* NCF 5 state configuration */ + uint32_t NCFSC4:2; /* NCF 4 state configuration */ + uint32_t NCFSC3:2; /* NCF 3 state configuration */ + uint32_t NCFSC2:2; /* NCF 2 state configuration */ + uint32_t NCFSC1:2; /* NCF 1 state configuration */ + uint32_t NCFSC0:2; /* NCF 0 state configuration */ + } B; + } FCCU_NCFS_CFG0_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 1 */ + uint32_t R; + struct { + uint32_t NCFSC31:2; /* NCF 31 state configuration */ + uint32_t NCFSC30:2; /* NCF 30 state configuration */ + uint32_t NCFSC29:2; /* NCF 29 state configuration */ + uint32_t NCFSC28:2; /* NCF 28 state configuration */ + uint32_t NCFSC27:2; /* NCF 27 state configuration */ + uint32_t NCFSC26:2; /* NCF 26 state configuration */ + uint32_t NCFSC25:2; /* NCF 25 state configuration */ + uint32_t NCFSC24:2; /* NCF 24 state configuration */ + uint32_t NCFSC23:2; /* NCF 23 state configuration */ + uint32_t NCFSC22:2; /* NCF 22 state configuration */ + uint32_t NCFSC21:2; /* NCF 21 state configuration */ + uint32_t NCFSC20:2; /* NCF 20 state configuration */ + uint32_t NCFSC19:2; /* NCF 19 state configuration */ + uint32_t NCFSC18:2; /* NCF 18 state configuration */ + uint32_t NCFSC17:2; /* NCF 17 state configuration */ + uint32_t NCFSC16:2; /* NCF 16 state configuration */ + } B; + } FCCU_NCFS_CFG1_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 2 */ + uint32_t R; + struct { + uint32_t NCFSC47:2; /* NCF 47 state configuration */ + uint32_t NCFSC46:2; /* NCF 46 state configuration */ + uint32_t NCFSC45:2; /* NCF 45 state configuration */ + uint32_t NCFSC44:2; /* NCF 44 state configuration */ + uint32_t NCFSC43:2; /* NCF 43 state configuration */ + uint32_t NCFSC42:2; /* NCF 42 state configuration */ + uint32_t NCFSC41:2; /* NCF 41 state configuration */ + uint32_t NCFSC40:2; /* NCF 40 state configuration */ + uint32_t NCFSC39:2; /* NCF 39 state configuration */ + uint32_t NCFSC38:2; /* NCF 38 state configuration */ + uint32_t NCFSC37:2; /* NCF 37 state configuration */ + uint32_t NCFSC36:2; /* NCF 36 state configuration */ + uint32_t NCFSC35:2; /* NCF 35 state configuration */ + uint32_t NCFSC34:2; /* NCF 34 state configuration */ + uint32_t NCFSC33:2; /* NCF 33 state configuration */ + uint32_t NCFSC32:2; /* NCF 32 state configuration */ + } B; + } FCCU_NCFS_CFG2_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 3 */ + uint32_t R; + struct { + uint32_t NCFSC63:2; /* NCF 63 state configuration */ + uint32_t NCFSC62:2; /* NCF 62 state configuration */ + uint32_t NCFSC61:2; /* NCF 61 state configuration */ + uint32_t NCFSC60:2; /* NCF 60 state configuration */ + uint32_t NCFSC59:2; /* NCF 59 state configuration */ + uint32_t NCFSC58:2; /* NCF 58 state configuration */ + uint32_t NCFSC57:2; /* NCF 57 state configuration */ + uint32_t NCFSC56:2; /* NCF 56 state configuration */ + uint32_t NCFSC55:2; /* NCF 55 state configuration */ + uint32_t NCFSC54:2; /* NCF 54 state configuration */ + uint32_t NCFSC53:2; /* NCF 53 state configuration */ + uint32_t NCFSC52:2; /* NCF 52 state configuration */ + uint32_t NCFSC51:2; /* NCF 51 state configuration */ + uint32_t NCFSC50:2; /* NCF 50 state configuration */ + uint32_t NCFSC49:2; /* NCF 49 state configuration */ + uint32_t NCFSC48:2; /* NCF 48 state configuration */ + } B; + } FCCU_NCFS_CFG3_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 4 */ + uint32_t R; + struct { + uint32_t NCFSC79:2; /* NCF 79 state configuration */ + uint32_t NCFSC78:2; /* NCF 78 state configuration */ + uint32_t NCFSC77:2; /* NCF 77 state configuration */ + uint32_t NCFSC76:2; /* NCF 76 state configuration */ + uint32_t NCFSC75:2; /* NCF 75 state configuration */ + uint32_t NCFSC74:2; /* NCF 74 state configuration */ + uint32_t NCFSC73:2; /* NCF 73 state configuration */ + uint32_t NCFSC72:2; /* NCF 72 state configuration */ + uint32_t NCFSC71:2; /* NCF 71 state configuration */ + uint32_t NCFSC70:2; /* NCF 70 state configuration */ + uint32_t NCFSC69:2; /* NCF 69 state configuration */ + uint32_t NCFSC68:2; /* NCF 68 state configuration */ + uint32_t NCFSC67:2; /* NCF 67 state configuration */ + uint32_t NCFSC66:2; /* NCF 66 state configuration */ + uint32_t NCFSC65:2; /* NCF 65 state configuration */ + uint32_t NCFSC64:2; /* NCF 64 state configuration */ + } B; + } FCCU_NCFS_CFG4_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 5 */ + uint32_t R; + struct { + uint32_t NCFSC95:2; /* NCF 95 state configuration */ + uint32_t NCFSC94:2; /* NCF 94 state configuration */ + uint32_t NCFSC93:2; /* NCF 93 state configuration */ + uint32_t NCFSC92:2; /* NCF 92 state configuration */ + uint32_t NCFSC91:2; /* NCF 91 state configuration */ + uint32_t NCFSC90:2; /* NCF 90 state configuration */ + uint32_t NCFSC89:2; /* NCF 89 state configuration */ + uint32_t NCFSC88:2; /* NCF 88 state configuration */ + uint32_t NCFSC87:2; /* NCF 87 state configuration */ + uint32_t NCFSC86:2; /* NCF 86 state configuration */ + uint32_t NCFSC85:2; /* NCF 85 state configuration */ + uint32_t NCFSC84:2; /* NCF 84 state configuration */ + uint32_t NCFSC83:2; /* NCF 83 state configuration */ + uint32_t NCFSC82:2; /* NCF 82 state configuration */ + uint32_t NCFSC81:2; /* NCF 81 state configuration */ + uint32_t NCFSC80:2; /* NCF 80 state configuration */ + } B; + } FCCU_NCFS_CFG5_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 6 */ + uint32_t R; + struct { + uint32_t NCFSC111:2; /* NCF 111 state configuration */ + uint32_t NCFSC110:2; /* NCF 110 state configuration */ + uint32_t NCFSC109:2; /* NCF 109 state configuration */ + uint32_t NCFSC108:2; /* NCF 108 state configuration */ + uint32_t NCFSC107:2; /* NCF 107 state configuration */ + uint32_t NCFSC106:2; /* NCF 106 state configuration */ + uint32_t NCFSC105:2; /* NCF 105 state configuration */ + uint32_t NCFSC104:2; /* NCF 104 state configuration */ + uint32_t NCFSC103:2; /* NCF 103 state configuration */ + uint32_t NCFSC102:2; /* NCF 102 state configuration */ + uint32_t NCFSC101:2; /* NCF 101 state configuration */ + uint32_t NCFSC100:2; /* NCF 100 state configuration */ + uint32_t NCFSC99:2; /* NCF 99 state configuration */ + uint32_t NCFSC98:2; /* NCF 98 state configuration */ + uint32_t NCFSC97:2; /* NCF 97 state configuration */ + uint32_t NCFSC96:2; /* NCF 96 state configuration */ + } B; + } FCCU_NCFS_CFG6_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 7 */ + uint32_t R; + struct { + uint32_t NCFSC127:2; /* NCF 127 state configuration */ + uint32_t NCFSC126:2; /* NCF 126 state configuration */ + uint32_t NCFSC125:2; /* NCF 125 state configuration */ + uint32_t NCFSC124:2; /* NCF 124 state configuration */ + uint32_t NCFSC123:2; /* NCF 123 state configuration */ + uint32_t NCFSC122:2; /* NCF 122 state configuration */ + uint32_t NCFSC121:2; /* NCF 121 state configuration */ + uint32_t NCFSC120:2; /* NCF 120 state configuration */ + uint32_t NCFSC119:2; /* NCF 119 state configuration */ + uint32_t NCFSC118:2; /* NCF 118 state configuration */ + uint32_t NCFSC117:2; /* NCF 117 state configuration */ + uint32_t NCFSC116:2; /* NCF 116 state configuration */ + uint32_t NCFSC115:2; /* NCF 115 state configuration */ + uint32_t NCFSC114:2; /* NCF 114 state configuration */ + uint32_t NCFSC113:2; /* NCF 113 state configuration */ + uint32_t NCFSC112:2; /* NCF 112 state configuration */ + } B; + } FCCU_NCFS_CFG7_32B_tag; + + typedef union { /* FCCU CF Status Register 0 */ + uint32_t R; + struct { + uint32_t CFS31:1; /* CF 31 status */ + uint32_t CFS30:1; /* CF 30 status */ + uint32_t CFS29:1; /* CF 29 status */ + uint32_t CFS28:1; /* CF 28 status */ + uint32_t CFS27:1; /* CF 27 status */ + uint32_t CFS26:1; /* CF 26 status */ + uint32_t CFS25:1; /* CF 25 status */ + uint32_t CFS24:1; /* CF 24 status */ + uint32_t CFS23:1; /* CF 23 status */ + uint32_t CFS22:1; /* CF 22 status */ + uint32_t CFS21:1; /* CF 21 status */ + uint32_t CFS20:1; /* CF 20 status */ + uint32_t CFS19:1; /* CF 19 status */ + uint32_t CFS18:1; /* CF 18 status */ + uint32_t CFS17:1; /* CF 17 status */ + uint32_t CFS16:1; /* CF 16 status */ + uint32_t CFS15:1; /* CF 15 status */ + uint32_t CFS14:1; /* CF 14 status */ + uint32_t CFS13:1; /* CF 13 status */ + uint32_t CFS12:1; /* CF 12 status */ + uint32_t CFS11:1; /* CF 11 status */ + uint32_t CFS10:1; /* CF 10 status */ + uint32_t CFS9:1; /* CF 9 status */ + uint32_t CFS8:1; /* CF 8 status */ + uint32_t CFS7:1; /* CF 7 status */ + uint32_t CFS6:1; /* CF 6 status */ + uint32_t CFS5:1; /* CF 5 status */ + uint32_t CFS4:1; /* CF 4 status */ + uint32_t CFS3:1; /* CF 3 status */ + uint32_t CFS2:1; /* CF 2 status */ + uint32_t CFS1:1; /* CF 1 status */ + uint32_t CFS0:1; /* CF 0 status */ + } B; + } FCCU_CFS0_32B_tag; + + typedef union { /* FCCU CF Status Register 1 */ + uint32_t R; + struct { + uint32_t CFS63:1; /* CF 63 status */ + uint32_t CFS62:1; /* CF 62 status */ + uint32_t CFS61:1; /* CF 61 status */ + uint32_t CFS60:1; /* CF 60 status */ + uint32_t CFS59:1; /* CF 59 status */ + uint32_t CFS58:1; /* CF 58 status */ + uint32_t CFS57:1; /* CF 57 status */ + uint32_t CFS56:1; /* CF 56 status */ + uint32_t CFS55:1; /* CF 55 status */ + uint32_t CFS54:1; /* CF 54 status */ + uint32_t CFS53:1; /* CF 53 status */ + uint32_t CFS52:1; /* CF 52 status */ + uint32_t CFS51:1; /* CF 51 status */ + uint32_t CFS50:1; /* CF 50 status */ + uint32_t CFS49:1; /* CF 49 status */ + uint32_t CFS48:1; /* CF 48 status */ + uint32_t CFS47:1; /* CF 47 status */ + uint32_t CFS46:1; /* CF 46 status */ + uint32_t CFS45:1; /* CF 45 status */ + uint32_t CFS44:1; /* CF 44 status */ + uint32_t CFS43:1; /* CF 43 status */ + uint32_t CFS42:1; /* CF 42 status */ + uint32_t CFS41:1; /* CF 41 status */ + uint32_t CFS40:1; /* CF 40 status */ + uint32_t CFS39:1; /* CF 39 status */ + uint32_t CFS38:1; /* CF 38 status */ + uint32_t CFS37:1; /* CF 37 status */ + uint32_t CFS36:1; /* CF 36 status */ + uint32_t CFS35:1; /* CF 35 status */ + uint32_t CFS34:1; /* CF 34 status */ + uint32_t CFS33:1; /* CF 33 status */ + uint32_t CFS32:1; /* CF 32 status */ + } B; + } FCCU_CFS1_32B_tag; + + typedef union { /* FCCU CF Status Register 2 */ + uint32_t R; + struct { + uint32_t CFS95:1; /* CF 95 status */ + uint32_t CFS94:1; /* CF 94 status */ + uint32_t CFS93:1; /* CF 93 status */ + uint32_t CFS92:1; /* CF 92 status */ + uint32_t CFS91:1; /* CF 91 status */ + uint32_t CFS90:1; /* CF 90 status */ + uint32_t CFS89:1; /* CF 89 status */ + uint32_t CFS88:1; /* CF 88 status */ + uint32_t CFS87:1; /* CF 87 status */ + uint32_t CFS86:1; /* CF 86 status */ + uint32_t CFS85:1; /* CF 85 status */ + uint32_t CFS84:1; /* CF 84 status */ + uint32_t CFS83:1; /* CF 83 status */ + uint32_t CFS82:1; /* CF 82 status */ + uint32_t CFS81:1; /* CF 81 status */ + uint32_t CFS80:1; /* CF 80 status */ + uint32_t CFS79:1; /* CF 79 status */ + uint32_t CFS78:1; /* CF 78 status */ + uint32_t CFS77:1; /* CF 77 status */ + uint32_t CFS76:1; /* CF 76 status */ + uint32_t CFS75:1; /* CF 75 status */ + uint32_t CFS74:1; /* CF 74 status */ + uint32_t CFS73:1; /* CF 73 status */ + uint32_t CFS72:1; /* CF 72 status */ + uint32_t CFS71:1; /* CF 71 status */ + uint32_t CFS70:1; /* CF 70 status */ + uint32_t CFS69:1; /* CF 69 status */ + uint32_t CFS68:1; /* CF 68 status */ + uint32_t CFS67:1; /* CF 67 status */ + uint32_t CFS66:1; /* CF 66 status */ + uint32_t CFS65:1; /* CF 65 status */ + uint32_t CFS64:1; /* CF 64 status */ + } B; + } FCCU_CFS2_32B_tag; + + typedef union { /* FCCU CF Status Register 3 */ + uint32_t R; + struct { + uint32_t CFS127:1; /* CF 127 status */ + uint32_t CFS126:1; /* CF 126 status */ + uint32_t CFS125:1; /* CF 125 status */ + uint32_t CFS124:1; /* CF 124 status */ + uint32_t CFS123:1; /* CF 123 status */ + uint32_t CFS122:1; /* CF 122 status */ + uint32_t CFS121:1; /* CF 121 status */ + uint32_t CFS120:1; /* CF 120 status */ + uint32_t CFS119:1; /* CF 119 status */ + uint32_t CFS118:1; /* CF 118 status */ + uint32_t CFS117:1; /* CF 117 status */ + uint32_t CFS116:1; /* CF 116 status */ + uint32_t CFS115:1; /* CF 115 status */ + uint32_t CFS114:1; /* CF 114 status */ + uint32_t CFS113:1; /* CF 113 status */ + uint32_t CFS112:1; /* CF 112 status */ + uint32_t CFS111:1; /* CF 111 status */ + uint32_t CFS110:1; /* CF 110 status */ + uint32_t CFS109:1; /* CF 109 status */ + uint32_t CFS108:1; /* CF 108 status */ + uint32_t CFS107:1; /* CF 107 status */ + uint32_t CFS106:1; /* CF 106 status */ + uint32_t CFS105:1; /* CF 105 status */ + uint32_t CFS104:1; /* CF 104 status */ + uint32_t CFS103:1; /* CF 103 status */ + uint32_t CFS102:1; /* CF 102 status */ + uint32_t CFS101:1; /* CF 101 status */ + uint32_t CFS100:1; /* CF 100 status */ + uint32_t CFS99:1; /* CF 99 status */ + uint32_t CFS98:1; /* CF 98 status */ + uint32_t CFS97:1; /* CF 97 status */ + uint32_t CFS96:1; /* CF 96 status */ + } B; + } FCCU_CFS3_32B_tag; + + typedef union { /* FCCU_CFK - FCCU CF Key Register */ + uint32_t R; + } FCCU_CFK_32B_tag; + + typedef union { /* FCCU NCF Status Register 0 */ + uint32_t R; + struct { + uint32_t NCFS31:1; /* NCF 31 status */ + uint32_t NCFS30:1; /* NCF 30 status */ + uint32_t NCFS29:1; /* NCF 29 status */ + uint32_t NCFS28:1; /* NCF 28 status */ + uint32_t NCFS27:1; /* NCF 27 status */ + uint32_t NCFS26:1; /* NCF 26 status */ + uint32_t NCFS25:1; /* NCF 25 status */ + uint32_t NCFS24:1; /* NCF 24 status */ + uint32_t NCFS23:1; /* NCF 23 status */ + uint32_t NCFS22:1; /* NCF 22 status */ + uint32_t NCFS21:1; /* NCF 21 status */ + uint32_t NCFS20:1; /* NCF 20 status */ + uint32_t NCFS19:1; /* NCF 19 status */ + uint32_t NCFS18:1; /* NCF 18 status */ + uint32_t NCFS17:1; /* NCF 17 status */ + uint32_t NCFS16:1; /* NCF 16 status */ + uint32_t NCFS15:1; /* NCF 15 status */ + uint32_t NCFS14:1; /* NCF 14 status */ + uint32_t NCFS13:1; /* NCF 13 status */ + uint32_t NCFS12:1; /* NCF 12 status */ + uint32_t NCFS11:1; /* NCF 11 status */ + uint32_t NCFS10:1; /* NCF 10 status */ + uint32_t NCFS9:1; /* NCF 9 status */ + uint32_t NCFS8:1; /* NCF 8 status */ + uint32_t NCFS7:1; /* NCF 7 status */ + uint32_t NCFS6:1; /* NCF 6 status */ + uint32_t NCFS5:1; /* NCF 5 status */ + uint32_t NCFS4:1; /* NCF 4 status */ + uint32_t NCFS3:1; /* NCF 3 status */ + uint32_t NCFS2:1; /* NCF 2 status */ + uint32_t NCFS1:1; /* NCF 1 status */ + uint32_t NCFS0:1; /* NCF 0 status */ + } B; + } FCCU_NCFS0_32B_tag; + + typedef union { /* FCCU NCF Status Register 1 */ + uint32_t R; + struct { + uint32_t NCFS63:1; /* NCF 63 status */ + uint32_t NCFS62:1; /* NCF 62 status */ + uint32_t NCFS61:1; /* NCF 61 status */ + uint32_t NCFS60:1; /* NCF 60 status */ + uint32_t NCFS59:1; /* NCF 59 status */ + uint32_t NCFS58:1; /* NCF 58 status */ + uint32_t NCFS57:1; /* NCF 57 status */ + uint32_t NCFS56:1; /* NCF 56 status */ + uint32_t NCFS55:1; /* NCF 55 status */ + uint32_t NCFS54:1; /* NCF 54 status */ + uint32_t NCFS53:1; /* NCF 53 status */ + uint32_t NCFS52:1; /* NCF 52 status */ + uint32_t NCFS51:1; /* NCF 51 status */ + uint32_t NCFS50:1; /* NCF 50 status */ + uint32_t NCFS49:1; /* NCF 49 status */ + uint32_t NCFS48:1; /* NCF 48 status */ + uint32_t NCFS47:1; /* NCF 47 status */ + uint32_t NCFS46:1; /* NCF 46 status */ + uint32_t NCFS45:1; /* NCF 45 status */ + uint32_t NCFS44:1; /* NCF 44 status */ + uint32_t NCFS43:1; /* NCF 43 status */ + uint32_t NCFS42:1; /* NCF 42 status */ + uint32_t NCFS41:1; /* NCF 41 status */ + uint32_t NCFS40:1; /* NCF 40 status */ + uint32_t NCFS39:1; /* NCF 39 status */ + uint32_t NCFS38:1; /* NCF 38 status */ + uint32_t NCFS37:1; /* NCF 37 status */ + uint32_t NCFS36:1; /* NCF 36 status */ + uint32_t NCFS35:1; /* NCF 35 status */ + uint32_t NCFS34:1; /* NCF 34 status */ + uint32_t NCFS33:1; /* NCF 33 status */ + uint32_t NCFS32:1; /* NCF 32 status */ + } B; + } FCCU_NCFS1_32B_tag; + + typedef union { /* FCCU NCF Status Register 2 */ + uint32_t R; + struct { + uint32_t NCFS95:1; /* NCF 95 status */ + uint32_t NCFS94:1; /* NCF 94 status */ + uint32_t NCFS93:1; /* NCF 93 status */ + uint32_t NCFS92:1; /* NCF 92 status */ + uint32_t NCFS91:1; /* NCF 91 status */ + uint32_t NCFS90:1; /* NCF 90 status */ + uint32_t NCFS89:1; /* NCF 89 status */ + uint32_t NCFS88:1; /* NCF 88 status */ + uint32_t NCFS87:1; /* NCF 87 status */ + uint32_t NCFS86:1; /* NCF 86 status */ + uint32_t NCFS85:1; /* NCF 85 status */ + uint32_t NCFS84:1; /* NCF 84 status */ + uint32_t NCFS83:1; /* NCF 83 status */ + uint32_t NCFS82:1; /* NCF 82 status */ + uint32_t NCFS81:1; /* NCF 81 status */ + uint32_t NCFS80:1; /* NCF 80 status */ + uint32_t NCFS79:1; /* NCF 79 status */ + uint32_t NCFS78:1; /* NCF 78 status */ + uint32_t NCFS77:1; /* NCF 77 status */ + uint32_t NCFS76:1; /* NCF 76 status */ + uint32_t NCFS75:1; /* NCF 75 status */ + uint32_t NCFS74:1; /* NCF 74 status */ + uint32_t NCFS73:1; /* NCF 73 status */ + uint32_t NCFS72:1; /* NCF 72 status */ + uint32_t NCFS71:1; /* NCF 71 status */ + uint32_t NCFS70:1; /* NCF 70 status */ + uint32_t NCFS69:1; /* NCF 69 status */ + uint32_t NCFS68:1; /* NCF 68 status */ + uint32_t NCFS67:1; /* NCF 67 status */ + uint32_t NCFS66:1; /* NCF 66 status */ + uint32_t NCFS65:1; /* NCF 65 status */ + uint32_t NCFS64:1; /* NCF 64 status */ + } B; + } FCCU_NCFS2_32B_tag; + + typedef union { /* FCCU NCF Status Register 3 */ + uint32_t R; + struct { + uint32_t NCFS127:1; /* NCF 127 status */ + uint32_t NCFS126:1; /* NCF 126 status */ + uint32_t NCFS125:1; /* NCF 125 status */ + uint32_t NCFS124:1; /* NCF 124 status */ + uint32_t NCFS123:1; /* NCF 123 status */ + uint32_t NCFS122:1; /* NCF 122 status */ + uint32_t NCFS121:1; /* NCF 121 status */ + uint32_t NCFS120:1; /* NCF 120 status */ + uint32_t NCFS119:1; /* NCF 119 status */ + uint32_t NCFS118:1; /* NCF 118 status */ + uint32_t NCFS117:1; /* NCF 117 status */ + uint32_t NCFS116:1; /* NCF 116 status */ + uint32_t NCFS115:1; /* NCF 115 status */ + uint32_t NCFS114:1; /* NCF 114 status */ + uint32_t NCFS113:1; /* NCF 113 status */ + uint32_t NCFS112:1; /* NCF 112 status */ + uint32_t NCFS111:1; /* NCF 111 status */ + uint32_t NCFS110:1; /* NCF 110 status */ + uint32_t NCFS109:1; /* NCF 109 status */ + uint32_t NCFS108:1; /* NCF 108 status */ + uint32_t NCFS107:1; /* NCF 107 status */ + uint32_t NCFS106:1; /* NCF 106 status */ + uint32_t NCFS105:1; /* NCF 105 status */ + uint32_t NCFS104:1; /* NCF 104 status */ + uint32_t NCFS103:1; /* NCF 103 status */ + uint32_t NCFS102:1; /* NCF 102 status */ + uint32_t NCFS101:1; /* NCF 101 status */ + uint32_t NCFS100:1; /* NCF 100 status */ + uint32_t NCFS99:1; /* NCF 99 status */ + uint32_t NCFS98:1; /* NCF 98 status */ + uint32_t NCFS97:1; /* NCF 97 status */ + uint32_t NCFS96:1; /* NCF 96 status */ + } B; + } FCCU_NCFS3_32B_tag; + + typedef union { /* FCCU_NCFK - FCCU NCF Key Register */ + uint32_t R; + } FCCU_NCFK_32B_tag; + + typedef union { /* FCCU NCF Enable Register 0 */ + uint32_t R; + struct { + uint32_t NCFE31:1; /* NCF 31 enable */ + uint32_t NCFE30:1; /* NCF 30 enable */ + uint32_t NCFE29:1; /* NCF 29 enable */ + uint32_t NCFE28:1; /* NCF 28 enable */ + uint32_t NCFE27:1; /* NCF 27 enable */ + uint32_t NCFE26:1; /* NCF 26 enable */ + uint32_t NCFE25:1; /* NCF 25 enable */ + uint32_t NCFE24:1; /* NCF 24 enable */ + uint32_t NCFE23:1; /* NCF 23 enable */ + uint32_t NCFE22:1; /* NCF 22 enable */ + uint32_t NCFE21:1; /* NCF 21 enable */ + uint32_t NCFE20:1; /* NCF 20 enable */ + uint32_t NCFE19:1; /* NCF 19 enable */ + uint32_t NCFE18:1; /* NCF 18 enable */ + uint32_t NCFE17:1; /* NCF 17 enable */ + uint32_t NCFE16:1; /* NCF 16 enable */ + uint32_t NCFE15:1; /* NCF 15 enable */ + uint32_t NCFE14:1; /* NCF 14 enable */ + uint32_t NCFE13:1; /* NCF 13 enable */ + uint32_t NCFE12:1; /* NCF 12 enable */ + uint32_t NCFE11:1; /* NCF 11 enable */ + uint32_t NCFE10:1; /* NCF 10 enable */ + uint32_t NCFE9:1; /* NCF 9 enable */ + uint32_t NCFE8:1; /* NCF 8 enable */ + uint32_t NCFE7:1; /* NCF 7 enable */ + uint32_t NCFE6:1; /* NCF 6 enable */ + uint32_t NCFE5:1; /* NCF 5 enable */ + uint32_t NCFE4:1; /* NCF 4 enable */ + uint32_t NCFE3:1; /* NCF 3 enable */ + uint32_t NCFE2:1; /* NCF 2 enable */ + uint32_t NCFE1:1; /* NCF 1 enable */ + uint32_t NCFE0:1; /* NCF 0 enable */ + } B; + } FCCU_NCFE0_32B_tag; + + typedef union { /* FCCU NCF Enable Register 1 */ + uint32_t R; + struct { + uint32_t NCFE63:1; /* NCF 63 enable */ + uint32_t NCFE62:1; /* NCF 62 enable */ + uint32_t NCFE61:1; /* NCF 61 enable */ + uint32_t NCFE60:1; /* NCF 60 enable */ + uint32_t NCFE59:1; /* NCF 59 enable */ + uint32_t NCFE58:1; /* NCF 58 enable */ + uint32_t NCFE57:1; /* NCF 57 enable */ + uint32_t NCFE56:1; /* NCF 56 enable */ + uint32_t NCFE55:1; /* NCF 55 enable */ + uint32_t NCFE54:1; /* NCF 54 enable */ + uint32_t NCFE53:1; /* NCF 53 enable */ + uint32_t NCFE52:1; /* NCF 52 enable */ + uint32_t NCFE51:1; /* NCF 51 enable */ + uint32_t NCFE50:1; /* NCF 50 enable */ + uint32_t NCFE49:1; /* NCF 49 enable */ + uint32_t NCFE48:1; /* NCF 48 enable */ + uint32_t NCFE47:1; /* NCF 47 enable */ + uint32_t NCFE46:1; /* NCF 46 enable */ + uint32_t NCFE45:1; /* NCF 45 enable */ + uint32_t NCFE44:1; /* NCF 44 enable */ + uint32_t NCFE43:1; /* NCF 43 enable */ + uint32_t NCFE42:1; /* NCF 42 enable */ + uint32_t NCFE41:1; /* NCF 41 enable */ + uint32_t NCFE40:1; /* NCF 40 enable */ + uint32_t NCFE39:1; /* NCF 39 enable */ + uint32_t NCFE38:1; /* NCF 38 enable */ + uint32_t NCFE37:1; /* NCF 37 enable */ + uint32_t NCFE36:1; /* NCF 36 enable */ + uint32_t NCFE35:1; /* NCF 35 enable */ + uint32_t NCFE34:1; /* NCF 34 enable */ + uint32_t NCFE33:1; /* NCF 33 enable */ + uint32_t NCFE32:1; /* NCF 32 enable */ + } B; + } FCCU_NCFE1_32B_tag; + + typedef union { /* FCCU NCF Enable Register 2 */ + uint32_t R; + struct { + uint32_t NCFE95:1; /* NCF 95 enable */ + uint32_t NCFE94:1; /* NCF 94 enable */ + uint32_t NCFE93:1; /* NCF 93 enable */ + uint32_t NCFE92:1; /* NCF 92 enable */ + uint32_t NCFE91:1; /* NCF 91 enable */ + uint32_t NCFE90:1; /* NCF 90 enable */ + uint32_t NCFE89:1; /* NCF 89 enable */ + uint32_t NCFE88:1; /* NCF 88 enable */ + uint32_t NCFE87:1; /* NCF 87 enable */ + uint32_t NCFE86:1; /* NCF 86 enable */ + uint32_t NCFE85:1; /* NCF 85 enable */ + uint32_t NCFE84:1; /* NCF 84 enable */ + uint32_t NCFE83:1; /* NCF 83 enable */ + uint32_t NCFE82:1; /* NCF 82 enable */ + uint32_t NCFE81:1; /* NCF 81 enable */ + uint32_t NCFE80:1; /* NCF 80 enable */ + uint32_t NCFE79:1; /* NCF 79 enable */ + uint32_t NCFE78:1; /* NCF 78 enable */ + uint32_t NCFE77:1; /* NCF 77 enable */ + uint32_t NCFE76:1; /* NCF 76 enable */ + uint32_t NCFE75:1; /* NCF 75 enable */ + uint32_t NCFE74:1; /* NCF 74 enable */ + uint32_t NCFE73:1; /* NCF 73 enable */ + uint32_t NCFE72:1; /* NCF 72 enable */ + uint32_t NCFE71:1; /* NCF 71 enable */ + uint32_t NCFE70:1; /* NCF 70 enable */ + uint32_t NCFE69:1; /* NCF 69 enable */ + uint32_t NCFE68:1; /* NCF 68 enable */ + uint32_t NCFE67:1; /* NCF 67 enable */ + uint32_t NCFE66:1; /* NCF 66 enable */ + uint32_t NCFE65:1; /* NCF 65 enable */ + uint32_t NCFE64:1; /* NCF 64 enable */ + } B; + } FCCU_NCFE2_32B_tag; + + typedef union { /* FCCU NCF Enable Register 3 */ + uint32_t R; + struct { + uint32_t NCFE127:1; /* NCF 127 enable */ + uint32_t NCFE126:1; /* NCF 126 enable */ + uint32_t NCFE125:1; /* NCF 125 enable */ + uint32_t NCFE124:1; /* NCF 124 enable */ + uint32_t NCFE123:1; /* NCF 123 enable */ + uint32_t NCFE122:1; /* NCF 122 enable */ + uint32_t NCFE121:1; /* NCF 121 enable */ + uint32_t NCFE120:1; /* NCF 120 enable */ + uint32_t NCFE119:1; /* NCF 119 enable */ + uint32_t NCFE118:1; /* NCF 118 enable */ + uint32_t NCFE117:1; /* NCF 117 enable */ + uint32_t NCFE116:1; /* NCF 116 enable */ + uint32_t NCFE115:1; /* NCF 115 enable */ + uint32_t NCFE114:1; /* NCF 114 enable */ + uint32_t NCFE113:1; /* NCF 113 enable */ + uint32_t NCFE112:1; /* NCF 112 enable */ + uint32_t NCFE111:1; /* NCF 111 enable */ + uint32_t NCFE110:1; /* NCF 110 enable */ + uint32_t NCFE109:1; /* NCF 109 enable */ + uint32_t NCFE108:1; /* NCF 108 enable */ + uint32_t NCFE107:1; /* NCF 107 enable */ + uint32_t NCFE106:1; /* NCF 106 enable */ + uint32_t NCFE105:1; /* NCF 105 enable */ + uint32_t NCFE104:1; /* NCF 104 enable */ + uint32_t NCFE103:1; /* NCF 103 enable */ + uint32_t NCFE102:1; /* NCF 102 enable */ + uint32_t NCFE101:1; /* NCF 101 enable */ + uint32_t NCFE100:1; /* NCF 100 enable */ + uint32_t NCFE99:1; /* NCF 99 enable */ + uint32_t NCFE98:1; /* NCF 98 enable */ + uint32_t NCFE97:1; /* NCF 97 enable */ + uint32_t NCFE96:1; /* NCF 96 enable */ + } B; + } FCCU_NCFE3_32B_tag; + + typedef union { /* FCCU NCF Time-out Enable Register 0 */ + uint32_t R; + struct { + uint32_t NCFTOE31:1; /* NCF 31 time-out enable */ + uint32_t NCFTOE30:1; /* NCF 30 time-out enable */ + uint32_t NCFTOE29:1; /* NCF 29 time-out enable */ + uint32_t NCFTOE28:1; /* NCF 28 time-out enable */ + uint32_t NCFTOE27:1; /* NCF 27 time-out enable */ + uint32_t NCFTOE26:1; /* NCF 26 time-out enable */ + uint32_t NCFTOE25:1; /* NCF 25 time-out enable */ + uint32_t NCFTOE24:1; /* NCF 24 time-out enable */ + uint32_t NCFTOE23:1; /* NCF 23 time-out enable */ + uint32_t NCFTOE22:1; /* NCF 22 time-out enable */ + uint32_t NCFTOE21:1; /* NCF 21 time-out enable */ + uint32_t NCFTOE20:1; /* NCF 20 time-out enable */ + uint32_t NCFTOE19:1; /* NCF 19 time-out enable */ + uint32_t NCFTOE18:1; /* NCF 18 time-out enable */ + uint32_t NCFTOE17:1; /* NCF 17 time-out enable */ + uint32_t NCFTOE16:1; /* NCF 16 time-out enable */ + uint32_t NCFTOE15:1; /* NCF 15 time-out enable */ + uint32_t NCFTOE14:1; /* NCF 14 time-out enable */ + uint32_t NCFTOE13:1; /* NCF 13 time-out enable */ + uint32_t NCFTOE12:1; /* NCF 12 time-out enable */ + uint32_t NCFTOE11:1; /* NCF 11 time-out enable */ + uint32_t NCFTOE10:1; /* NCF 10 time-out enable */ + uint32_t NCFTOE9:1; /* NCF 9 time-out enable */ + uint32_t NCFTOE8:1; /* NCF 8 time-out enable */ + uint32_t NCFTOE7:1; /* NCF 7 time-out enable */ + uint32_t NCFTOE6:1; /* NCF 6 time-out enable */ + uint32_t NCFTOE5:1; /* NCF 5 time-out enable */ + uint32_t NCFTOE4:1; /* NCF 4 time-out enable */ + uint32_t NCFTOE3:1; /* NCF 3 time-out enable */ + uint32_t NCFTOE2:1; /* NCF 2 time-out enable */ + uint32_t NCFTOE1:1; /* NCF 1 time-out enable */ + uint32_t NCFTOE0:1; /* NCF 0 time-out enable */ + } B; + } FCCU_NCF_TOE0_32B_tag; + + typedef union { /* FCCU NCF Time-out Enable Register 1 */ + uint32_t R; + struct { + uint32_t NCFTOE63:1; /* NCF 63 time-out enable */ + uint32_t NCFTOE62:1; /* NCF 62 time-out enable */ + uint32_t NCFTOE61:1; /* NCF 61 time-out enable */ + uint32_t NCFTOE60:1; /* NCF 60 time-out enable */ + uint32_t NCFTOE59:1; /* NCF 59 time-out enable */ + uint32_t NCFTOE58:1; /* NCF 58 time-out enable */ + uint32_t NCFTOE57:1; /* NCF 57 time-out enable */ + uint32_t NCFTOE56:1; /* NCF 56 time-out enable */ + uint32_t NCFTOE55:1; /* NCF 55 time-out enable */ + uint32_t NCFTOE54:1; /* NCF 54 time-out enable */ + uint32_t NCFTOE53:1; /* NCF 53 time-out enable */ + uint32_t NCFTOE52:1; /* NCF 52 time-out enable */ + uint32_t NCFTOE51:1; /* NCF 51 time-out enable */ + uint32_t NCFTOE50:1; /* NCF 50 time-out enable */ + uint32_t NCFTOE49:1; /* NCF 49 time-out enable */ + uint32_t NCFTOE48:1; /* NCF 48 time-out enable */ + uint32_t NCFTOE47:1; /* NCF 47 time-out enable */ + uint32_t NCFTOE46:1; /* NCF 46 time-out enable */ + uint32_t NCFTOE45:1; /* NCF 45 time-out enable */ + uint32_t NCFTOE44:1; /* NCF 44 time-out enable */ + uint32_t NCFTOE43:1; /* NCF 43 time-out enable */ + uint32_t NCFTOE42:1; /* NCF 42 time-out enable */ + uint32_t NCFTOE41:1; /* NCF 41 time-out enable */ + uint32_t NCFTOE40:1; /* NCF 40 time-out enable */ + uint32_t NCFTOE39:1; /* NCF 39 time-out enable */ + uint32_t NCFTOE38:1; /* NCF 38 time-out enable */ + uint32_t NCFTOE37:1; /* NCF 37 time-out enable */ + uint32_t NCFTOE36:1; /* NCF 36 time-out enable */ + uint32_t NCFTOE35:1; /* NCF 35 time-out enable */ + uint32_t NCFTOE34:1; /* NCF 34 time-out enable */ + uint32_t NCFTOE33:1; /* NCF 33 time-out enable */ + uint32_t NCFTOE32:1; /* NCF 32 time-out enable */ + } B; + } FCCU_NCF_TOE1_32B_tag; + + typedef union { /* FCCU NCF Time-out Enable Register 2 */ + uint32_t R; + struct { + uint32_t NCFTOE95:1; /* NCF 95 time-out enable */ + uint32_t NCFTOE94:1; /* NCF 94 time-out enable */ + uint32_t NCFTOE93:1; /* NCF 93 time-out enable */ + uint32_t NCFTOE92:1; /* NCF 92 time-out enable */ + uint32_t NCFTOE91:1; /* NCF 91 time-out enable */ + uint32_t NCFTOE90:1; /* NCF 90 time-out enable */ + uint32_t NCFTOE89:1; /* NCF 89 time-out enable */ + uint32_t NCFTOE88:1; /* NCF 88 time-out enable */ + uint32_t NCFTOE87:1; /* NCF 87 time-out enable */ + uint32_t NCFTOE86:1; /* NCF 86 time-out enable */ + uint32_t NCFTOE85:1; /* NCF 85 time-out enable */ + uint32_t NCFTOE84:1; /* NCF 84 time-out enable */ + uint32_t NCFTOE83:1; /* NCF 83 time-out enable */ + uint32_t NCFTOE82:1; /* NCF 82 time-out enable */ + uint32_t NCFTOE81:1; /* NCF 81 time-out enable */ + uint32_t NCFTOE80:1; /* NCF 80 time-out enable */ + uint32_t NCFTOE79:1; /* NCF 79 time-out enable */ + uint32_t NCFTOE78:1; /* NCF 78 time-out enable */ + uint32_t NCFTOE77:1; /* NCF 77 time-out enable */ + uint32_t NCFTOE76:1; /* NCF 76 time-out enable */ + uint32_t NCFTOE75:1; /* NCF 75 time-out enable */ + uint32_t NCFTOE74:1; /* NCF 74 time-out enable */ + uint32_t NCFTOE73:1; /* NCF 73 time-out enable */ + uint32_t NCFTOE72:1; /* NCF 72 time-out enable */ + uint32_t NCFTOE71:1; /* NCF 71 time-out enable */ + uint32_t NCFTOE70:1; /* NCF 70 time-out enable */ + uint32_t NCFTOE69:1; /* NCF 69 time-out enable */ + uint32_t NCFTOE68:1; /* NCF 68 time-out enable */ + uint32_t NCFTOE67:1; /* NCF 67 time-out enable */ + uint32_t NCFTOE66:1; /* NCF 66 time-out enable */ + uint32_t NCFTOE65:1; /* NCF 65 time-out enable */ + uint32_t NCFTOE64:1; /* NCF 64 time-out enable */ + } B; + } FCCU_NCF_TOE2_32B_tag; + + typedef union { /* FCCU NCF Time-out Enable Register 3 */ + uint32_t R; + struct { + uint32_t NCFTOE127:1; /* NCF 127 time-out enable */ + uint32_t NCFTOE126:1; /* NCF 126 time-out enable */ + uint32_t NCFTOE125:1; /* NCF 125 time-out enable */ + uint32_t NCFTOE124:1; /* NCF 124 time-out enable */ + uint32_t NCFTOE123:1; /* NCF 123 time-out enable */ + uint32_t NCFTOE122:1; /* NCF 122 time-out enable */ + uint32_t NCFTOE121:1; /* NCF 121 time-out enable */ + uint32_t NCFTOE120:1; /* NCF 120 time-out enable */ + uint32_t NCFTOE119:1; /* NCF 119 time-out enable */ + uint32_t NCFTOE118:1; /* NCF 118 time-out enable */ + uint32_t NCFTOE117:1; /* NCF 117 time-out enable */ + uint32_t NCFTOE116:1; /* NCF 116 time-out enable */ + uint32_t NCFTOE115:1; /* NCF 115 time-out enable */ + uint32_t NCFTOE114:1; /* NCF 114 time-out enable */ + uint32_t NCFTOE113:1; /* NCF 113 time-out enable */ + uint32_t NCFTOE112:1; /* NCF 112 time-out enable */ + uint32_t NCFTOE111:1; /* NCF 111 time-out enable */ + uint32_t NCFTOE110:1; /* NCF 110 time-out enable */ + uint32_t NCFTOE109:1; /* NCF 109 time-out enable */ + uint32_t NCFTOE108:1; /* NCF 108 time-out enable */ + uint32_t NCFTOE107:1; /* NCF 107 time-out enable */ + uint32_t NCFTOE106:1; /* NCF 106 time-out enable */ + uint32_t NCFTOE105:1; /* NCF 105 time-out enable */ + uint32_t NCFTOE104:1; /* NCF 104 time-out enable */ + uint32_t NCFTOE103:1; /* NCF 103 time-out enable */ + uint32_t NCFTOE102:1; /* NCF 102 time-out enable */ + uint32_t NCFTOE101:1; /* NCF 101 time-out enable */ + uint32_t NCFTOE100:1; /* NCF 100 time-out enable */ + uint32_t NCFTOE99:1; /* NCF 99 time-out enable */ + uint32_t NCFTOE98:1; /* NCF 98 time-out enable */ + uint32_t NCFTOE97:1; /* NCF 97 time-out enable */ + uint32_t NCFTOE96:1; /* NCF 96 time-out enable */ + } B; + } FCCU_NCF_TOE3_32B_tag; + + typedef union { /* FCCU_NCF_TO - FCCU NCF Time-out Register */ + uint32_t R; + } FCCU_NCF_TO_32B_tag; + + typedef union { /* FCCU_CFG_TO - FCCU CFG Timeout Register */ + uint32_t R; + struct { + uint32_t:29; + uint32_t TO:3; /* Configuration time-out */ + } B; + } FCCU_CFG_TO_32B_tag; + + typedef union { /* FCCU_EINOUT - FCCU IO Control Register */ + uint32_t R; + struct { + uint32_t:26; + uint32_t EIN1:1; /* Error input 1 */ + uint32_t EIN0:1; /* Error input 0 */ + uint32_t:2; + uint32_t EOUT1:1; /* Error out 1 */ + uint32_t EOUT0:1; /* Error out 0 */ + } B; + } FCCU_EINOUT_32B_tag; + + typedef union { /* FCCU_STAT - FCCU Status Register */ + uint32_t R; + struct { + uint32_t:29; + uint32_t STATUS:3; /* FCCU status */ + } B; + } FCCU_STAT_32B_tag; + + typedef union { /* FCCU_NAFS - FCCU NA Freeze Status Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t N2AFSTATUS:8; /* Normal to Alarm Frozen Status */ + } B; + } FCCU_NAFS_32B_tag; + + typedef union { /* FCCU_AFFS - FCCU AF Freeze Status Register */ + uint32_t R; + struct { + uint32_t:22; + uint32_t AFFS_SRC:2; /* Fault source */ + uint32_t A2AFSTATUS:8; /* Alarm to Fault Frozen Status */ + } B; + } FCCU_AFFS_32B_tag; + + typedef union { /* FCCU_NFFS - FCCU NF Freeze Status Register */ + uint32_t R; + struct { + uint32_t:22; + uint32_t NFFS_SRC:2; /* Fault source */ + uint32_t NFFS_NFFS:8; /* Normal to Fault Frozen Status */ + } B; + } FCCU_NFFS_32B_tag; + + typedef union { /* FCCU_FAFS - FCCU FA Freeze Status Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t FAFS_FAFS:8; /* Fault to Normal Frozen Status */ + } B; + } FCCU_FAFS_32B_tag; + + typedef union { /* FCCU_SCFS - FCCU SC Freeze Status Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t RCCS1:1; /* RCC1 Status */ + uint32_t RCCS0:1; /* RCC0 Status */ + } B; + } FCCU_SCFS_32B_tag; + + typedef union { /* FCCU_CFF - FCCU CF Fake Register */ + uint32_t R; + struct { + uint32_t:25; + uint32_t FCFC:7; /* Fake critical fault code */ + } B; + } FCCU_CFF_32B_tag; + + typedef union { /* FCCU_NCFF - FCCU NCF Fake Register */ + uint32_t R; + struct { + uint32_t:25; + uint32_t FNCFC:7; /* Fake non-critical fault code */ + } B; + } FCCU_NCFF_32B_tag; + + typedef union { /* FCCU_IRQ_STAT - FCCU IRQ Status Register */ + uint32_t R; + struct { + uint32_t:29; + uint32_t NMI_STAT:1; /* NMI Interrupt Status */ + uint32_t ALRM_STAT:1; /* Alarm Interrupt Status */ + uint32_t CFG_TO_STAT:1; /* Configuration Time-out Status */ + } B; + } FCCU_IRQ_STAT_32B_tag; + + typedef union { /* FCCU_IRQ_EN - FCCU IRQ Enable Register */ + uint32_t R; + struct { + uint32_t:31; + uint32_t CFG_TO_IEN:1; /* Configuration Time-out Interrupt Enable */ + } B; + } FCCU_IRQ_EN_32B_tag; + + typedef union { /* FCCU_XTMR - FCCU XTMR Register */ + uint32_t R; + struct { + uint32_t XTMR_XTMR:32; /* Alarm/Watchdog/safe request timer */ + } B; + } FCCU_XTMR_32B_tag; + + typedef union { /* FCCU_MCS - FCCU MCS Register */ + uint32_t R; + struct { + uint32_t VL3:1; /* Valid */ + uint32_t FS3:1; /* Fault Status */ + uint32_t:2; + uint32_t MCS3:4; /* Magic Carpet oldest state */ + uint32_t VL2:1; /* Valid */ + uint32_t FS2:1; /* Fault Status */ + uint32_t:2; + uint32_t MCS2:4; /* Magic Carpet previous-previous state */ + uint32_t VL1:1; /* Valid */ + uint32_t FS1:1; /* Fault Status */ + uint32_t:2; + uint32_t MCS1:4; /* Magic Carpet previous state */ + uint32_t VL0:1; /* Valid */ + uint32_t FS0:1; /* Fault Status */ + uint32_t:2; + uint32_t MCS0:4; /* Magic Carpet latest state */ + } B; + } FCCU_MCS_32B_tag; + + + /* Register layout for generated register(s) CF_CFG... */ + + typedef union { /* */ + uint32_t R; + } FCCU_CF_CFG_32B_tag; + + + /* Register layout for generated register(s) NCF_CFG... */ + + typedef union { /* */ + uint32_t R; + } FCCU_NCF_CFG_32B_tag; + + + /* Register layout for generated register(s) CFS_CFG... */ + + typedef union { /* */ + uint32_t R; + } FCCU_CFS_CFG_32B_tag; + + + /* Register layout for generated register(s) NCFS_CFG... */ + + typedef union { /* */ + uint32_t R; + } FCCU_NCFS_CFG_32B_tag; + + + /* Register layout for generated register(s) CFS... */ + + typedef union { /* */ + uint32_t R; + } FCCU_CFS_32B_tag; + + + /* Register layout for generated register(s) NCFS... */ + + typedef union { /* */ + uint32_t R; + } FCCU_NCFS_32B_tag; + + + /* Register layout for generated register(s) NCFE... */ + + typedef union { /* */ + uint32_t R; + } FCCU_NCFE_32B_tag; + + + /* Register layout for generated register(s) NCF_TOE... */ + + typedef union { /* */ + uint32_t R; + } FCCU_NCF_TOE_32B_tag; + + + + typedef struct FCCU_struct_tag { /* start of FCCU_tag */ + /* FCCU Control Register */ + FCCU_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */ + /* FCCU CTRL Key Register */ + FCCU_CTRLK_32B_tag CTRLK; /* offset: 0x0004 size: 32 bit */ + /* FCCU Configuration Register */ + FCCU_CFG_32B_tag CFG; /* offset: 0x0008 size: 32 bit */ + union { + FCCU_CF_CFG_32B_tag CF_CFG[4]; /* offset: 0x000C (0x0004 x 4) */ + + struct { + /* FCCU CF Configuration Register 0 */ + FCCU_CF_CFG0_32B_tag CF_CFG0; /* offset: 0x000C size: 32 bit */ + /* FCCU CF Configuration Register 1 */ + FCCU_CF_CFG1_32B_tag CF_CFG1; /* offset: 0x0010 size: 32 bit */ + /* FCCU CF Configuration Register 2 */ + FCCU_CF_CFG2_32B_tag CF_CFG2; /* offset: 0x0014 size: 32 bit */ + /* FCCU CF Configuration Register 3 */ + FCCU_CF_CFG3_32B_tag CF_CFG3; /* offset: 0x0018 size: 32 bit */ + }; + + }; + union { + FCCU_NCF_CFG_32B_tag NCF_CFG[4]; /* offset: 0x001C (0x0004 x 4) */ + + struct { + /* FCCU NCF Configuration Register 0 */ + FCCU_NCF_CFG0_32B_tag NCF_CFG0; /* offset: 0x001C size: 32 bit */ + /* FCCU NCF Configuration Register 1 */ + FCCU_NCF_CFG1_32B_tag NCF_CFG1; /* offset: 0x0020 size: 32 bit */ + /* FCCU NCF Configuration Register 2 */ + FCCU_NCF_CFG2_32B_tag NCF_CFG2; /* offset: 0x0024 size: 32 bit */ + /* FCCU NCF Configuration Register 3 */ + FCCU_NCF_CFG3_32B_tag NCF_CFG3; /* offset: 0x0028 size: 32 bit */ + }; + + }; + union { + FCCU_CFS_CFG_32B_tag CFS_CFG[8]; /* offset: 0x002C (0x0004 x 8) */ + + struct { + /* FCCU CFS Configuration Register 0 */ + FCCU_CFS_CFG0_32B_tag CFS_CFG0; /* offset: 0x002C size: 32 bit */ + /* FCCU CFS Configuration Register 1 */ + FCCU_CFS_CFG1_32B_tag CFS_CFG1; /* offset: 0x0030 size: 32 bit */ + /* FCCU CFS Configuration Register 2 */ + FCCU_CFS_CFG2_32B_tag CFS_CFG2; /* offset: 0x0034 size: 32 bit */ + /* FCCU CFS Configuration Register 3 */ + FCCU_CFS_CFG3_32B_tag CFS_CFG3; /* offset: 0x0038 size: 32 bit */ + /* FCCU CFS Configuration Register 4 */ + FCCU_CFS_CFG4_32B_tag CFS_CFG4; /* offset: 0x003C size: 32 bit */ + /* FCCU CFS Configuration Register 5 */ + FCCU_CFS_CFG5_32B_tag CFS_CFG5; /* offset: 0x0040 size: 32 bit */ + /* FCCU CFS Configuration Register 6 */ + FCCU_CFS_CFG6_32B_tag CFS_CFG6; /* offset: 0x0044 size: 32 bit */ + /* FCCU CFS Configuration Register 7 */ + FCCU_CFS_CFG7_32B_tag CFS_CFG7; /* offset: 0x0048 size: 32 bit */ + }; + + }; + union { + FCCU_NCFS_CFG_32B_tag NCFS_CFG[8]; /* offset: 0x004C (0x0004 x 8) */ + + struct { + /* FCCU NCFS Configuration Register 0 */ + FCCU_NCFS_CFG0_32B_tag NCFS_CFG0; /* offset: 0x004C size: 32 bit */ + /* FCCU NCFS Configuration Register 1 */ + FCCU_NCFS_CFG1_32B_tag NCFS_CFG1; /* offset: 0x0050 size: 32 bit */ + /* FCCU NCFS Configuration Register 2 */ + FCCU_NCFS_CFG2_32B_tag NCFS_CFG2; /* offset: 0x0054 size: 32 bit */ + /* FCCU NCFS Configuration Register 3 */ + FCCU_NCFS_CFG3_32B_tag NCFS_CFG3; /* offset: 0x0058 size: 32 bit */ + /* FCCU NCFS Configuration Register 4 */ + FCCU_NCFS_CFG4_32B_tag NCFS_CFG4; /* offset: 0x005C size: 32 bit */ + /* FCCU NCFS Configuration Register 5 */ + FCCU_NCFS_CFG5_32B_tag NCFS_CFG5; /* offset: 0x0060 size: 32 bit */ + /* FCCU NCFS Configuration Register 6 */ + FCCU_NCFS_CFG6_32B_tag NCFS_CFG6; /* offset: 0x0064 size: 32 bit */ + /* FCCU NCFS Configuration Register 7 */ + FCCU_NCFS_CFG7_32B_tag NCFS_CFG7; /* offset: 0x0068 size: 32 bit */ + }; + + }; + union { + FCCU_CFS_32B_tag CFS[4]; /* offset: 0x006C (0x0004 x 4) */ + + struct { + /* FCCU CF Status Register 0 */ + FCCU_CFS0_32B_tag CFS0; /* offset: 0x006C size: 32 bit */ + /* FCCU CF Status Register 1 */ + FCCU_CFS1_32B_tag CFS1; /* offset: 0x0070 size: 32 bit */ + /* FCCU CF Status Register 2 */ + FCCU_CFS2_32B_tag CFS2; /* offset: 0x0074 size: 32 bit */ + /* FCCU CF Status Register 3 */ + FCCU_CFS3_32B_tag CFS3; /* offset: 0x0078 size: 32 bit */ + }; + + }; + /* FCCU_CFK - FCCU CF Key Register */ + FCCU_CFK_32B_tag CFK; /* offset: 0x007C size: 32 bit */ + union { + FCCU_NCFS_32B_tag NCFS[4]; /* offset: 0x0080 (0x0004 x 4) */ + + struct { + /* FCCU NCF Status Register 0 */ + FCCU_NCFS0_32B_tag NCFS0; /* offset: 0x0080 size: 32 bit */ + /* FCCU NCF Status Register 1 */ + FCCU_NCFS1_32B_tag NCFS1; /* offset: 0x0084 size: 32 bit */ + /* FCCU NCF Status Register 2 */ + FCCU_NCFS2_32B_tag NCFS2; /* offset: 0x0088 size: 32 bit */ + /* FCCU NCF Status Register 3 */ + FCCU_NCFS3_32B_tag NCFS3; /* offset: 0x008C size: 32 bit */ + }; + + }; + /* FCCU_NCFK - FCCU NCF Key Register */ + FCCU_NCFK_32B_tag NCFK; /* offset: 0x0090 size: 32 bit */ + union { + FCCU_NCFE_32B_tag NCFE[4]; /* offset: 0x0094 (0x0004 x 4) */ + + struct { + /* FCCU NCF Enable Register 0 */ + FCCU_NCFE0_32B_tag NCFE0; /* offset: 0x0094 size: 32 bit */ + /* FCCU NCF Enable Register 1 */ + FCCU_NCFE1_32B_tag NCFE1; /* offset: 0x0098 size: 32 bit */ + /* FCCU NCF Enable Register 2 */ + FCCU_NCFE2_32B_tag NCFE2; /* offset: 0x009C size: 32 bit */ + /* FCCU NCF Enable Register 3 */ + FCCU_NCFE3_32B_tag NCFE3; /* offset: 0x00A0 size: 32 bit */ + }; + + }; + union { + FCCU_NCF_TOE_32B_tag NCF_TOE[4]; /* offset: 0x00A4 (0x0004 x 4) */ + + struct { + /* FCCU NCF Time-out Enable Register 0 */ + FCCU_NCF_TOE0_32B_tag NCF_TOE0; /* offset: 0x00A4 size: 32 bit */ + /* FCCU NCF Time-out Enable Register 1 */ + FCCU_NCF_TOE1_32B_tag NCF_TOE1; /* offset: 0x00A8 size: 32 bit */ + /* FCCU NCF Time-out Enable Register 2 */ + FCCU_NCF_TOE2_32B_tag NCF_TOE2; /* offset: 0x00AC size: 32 bit */ + /* FCCU NCF Time-out Enable Register 3 */ + FCCU_NCF_TOE3_32B_tag NCF_TOE3; /* offset: 0x00B0 size: 32 bit */ + }; + + }; + /* FCCU_NCF_TO - FCCU NCF Time-out Register */ + FCCU_NCF_TO_32B_tag NCF_TO; /* offset: 0x00B4 size: 32 bit */ + /* FCCU_CFG_TO - FCCU CFG Timeout Register */ + FCCU_CFG_TO_32B_tag CFG_TO; /* offset: 0x00B8 size: 32 bit */ + /* FCCU_EINOUT - FCCU IO Control Register */ + FCCU_EINOUT_32B_tag EINOUT; /* offset: 0x00BC size: 32 bit */ + /* FCCU_STAT - FCCU Status Register */ + FCCU_STAT_32B_tag STAT; /* offset: 0x00C0 size: 32 bit */ + /* FCCU_NAFS - FCCU NA Freeze Status Register */ + FCCU_NAFS_32B_tag NAFS; /* offset: 0x00C4 size: 32 bit */ + /* FCCU_AFFS - FCCU AF Freeze Status Register */ + FCCU_AFFS_32B_tag AFFS; /* offset: 0x00C8 size: 32 bit */ + /* FCCU_NFFS - FCCU NF Freeze Status Register */ + FCCU_NFFS_32B_tag NFFS; /* offset: 0x00CC size: 32 bit */ + /* FCCU_FAFS - FCCU FA Freeze Status Register */ + FCCU_FAFS_32B_tag FAFS; /* offset: 0x00D0 size: 32 bit */ + /* FCCU_SCFS - FCCU SC Freeze Status Register */ + FCCU_SCFS_32B_tag SCFS; /* offset: 0x00D4 size: 32 bit */ + /* FCCU_CFF - FCCU CF Fake Register */ + FCCU_CFF_32B_tag CFF; /* offset: 0x00D8 size: 32 bit */ + /* FCCU_NCFF - FCCU NCF Fake Register */ + FCCU_NCFF_32B_tag NCFF; /* offset: 0x00DC size: 32 bit */ + /* FCCU_IRQ_STAT - FCCU IRQ Status Register */ + FCCU_IRQ_STAT_32B_tag IRQ_STAT; /* offset: 0x00E0 size: 32 bit */ + /* FCCU_IRQ_EN - FCCU IRQ Enable Register */ + FCCU_IRQ_EN_32B_tag IRQ_EN; /* offset: 0x00E4 size: 32 bit */ + /* FCCU_XTMR - FCCU XTMR Register */ + FCCU_XTMR_32B_tag XTMR; /* offset: 0x00E8 size: 32 bit */ + /* FCCU_MCS - FCCU MCS Register */ + FCCU_MCS_32B_tag MCS; /* offset: 0x00EC size: 32 bit */ + } FCCU_tag; + + +#define FCCU (*(volatile FCCU_tag *) 0xFFE6C000UL) + + + +/****************************************************************/ +/* */ +/* Module: SGENDIG */ +/* */ +/****************************************************************/ + + typedef union { /* SGENDIG_CTRL - SGENDIG Control Register */ + uint32_t R; + struct { + uint32_t LDOS:1; /* Operation Status */ + uint32_t IOAMPL:5; /* Define the AMPLitude value on I/O pad */ + uint32_t:2; + uint32_t SEMASK:1; /* Sine wave generator Error MASK interrupt register */ + uint32_t:5; + uint32_t S0H1:1; /* Operation Status */ + uint32_t PDS:1; /* Operation Status */ + uint32_t IOFREQ:16; /* Define the FREQuency value on I/O pad */ + } B; + } SGENDIG_CTRL_32B_tag; + + typedef union { /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t SERR:1; /* Sine wave generator Error bit */ + uint32_t:3; + uint32_t FERR:1; /* Sine wave generator Force Error bit */ + uint32_t:19; + } B; + } SGENDIG_IRQE_32B_tag; + + + + typedef struct SGENDIG_struct_tag { /* start of SGENDIG_tag */ + /* SGENDIG_CTRL - SGENDIG Control Register */ + SGENDIG_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */ + /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */ + SGENDIG_IRQE_32B_tag IRQE; /* offset: 0x0004 size: 32 bit */ + } SGENDIG_tag; + + +#define SGENDIG (*(volatile SGENDIG_tag *) 0xFFE78000UL) + + + +/****************************************************************/ +/* */ +/* Module: PBRIDGE */ +/* */ +/****************************************************************/ + + typedef union { /* MPROT - Master Privilege Registers */ + uint32_t R; + struct { + uint32_t MPROT0_MBW:1; /* Master 0 Buffer Writes */ + uint32_t MPROT0_MTR:1; /* Master 0 Trusted for Reads */ + uint32_t MPROT0_MTW:1; /* Master 0 Trusted for Writes */ + uint32_t MPROT0_MPL:1; /* Master 0 Priviledge Level */ + uint32_t MPROT1_MBW:1; /* Master 1 Buffer Writes */ + uint32_t MPROT1_MTR:1; /* Master 1 Trusted for Reads */ + uint32_t MPROT1_MTW:1; /* Master 1 Trusted for Writes */ + uint32_t MPROT1_MPL:1; /* Master 1 Priviledge Level */ + uint32_t MPROT2_MBW:1; /* Master 2 Buffer Writes */ + uint32_t MPROT2_MTR:1; /* Master 2 Trusted for Reads */ + uint32_t MPROT2_MTW:1; /* Master 2 Trusted for Writes */ + uint32_t MPROT2_MPL:1; /* Master 2 Priviledge Level */ + uint32_t MPROT3_MBW:1; /* Master 3 Buffer Writes */ + uint32_t MPROT3_MTR:1; /* Master 3 Trusted for Reads */ + uint32_t MPROT3_MTW:1; /* Master 3 Trusted for Writes */ + uint32_t MPROT3_MPL:1; /* Master 3 Priviledge Level */ + uint32_t MPROT4_MBW:1; /* Master 4 Buffer Writes */ + uint32_t MPROT4_MTR:1; /* Master 4 Trusted for Reads */ + uint32_t MPROT4_MTW:1; /* Master 4 Trusted for Writes */ + uint32_t MPROT4_MPL:1; /* Master 4 Priviledge Level */ + uint32_t MPROT5_MBW:1; /* Master 5 Buffer Writes */ + uint32_t MPROT5_MTR:1; /* Master 5 Trusted for Reads */ + uint32_t MPROT5_MTW:1; /* Master 5 Trusted for Writes */ + uint32_t MPROT5_MPL:1; /* Master 5 Priviledge Level */ + uint32_t MPROT6_MBW:1; /* Master 6 Buffer Writes */ + uint32_t MPROT6_MTR:1; /* Master 6 Trusted for Reads */ + uint32_t MPROT6_MTW:1; /* Master 6 Trusted for Writes */ + uint32_t MPROT6_MPL:1; /* Master 6 Priviledge Level */ + uint32_t MPROT7_MBW:1; /* Master 7 Buffer Writes */ + uint32_t MPROT7_MTR:1; /* Master 7 Trusted for Reads */ + uint32_t MPROT7_MTW:1; /* Master 7 Trusted for Writes */ + uint32_t MPROT7_MPL:1; /* Master 7 Priviledge Level */ + } B; + } PBRIDGE_MPROT_32B_tag; + + typedef union { /* PACR0_7 - Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t PACR0_BW:1; /* Buffer Writes */ + uint32_t PACR0_SP:1; /* Supervisor Protect */ + uint32_t PACR0_WP:1; /* Write Protect */ + uint32_t PACR0_TP:1; /* Trusted Protect */ + uint32_t PACR1_BW:1; /* Buffer Writes */ + uint32_t PACR1_SP:1; /* Supervisor Protect */ + uint32_t PACR1_WP:1; /* Write Protect */ + uint32_t PACR1_TP:1; /* Trusted Protect */ + uint32_t PACR2_BW:1; /* Buffer Writes */ + uint32_t PACR2_SP:1; /* Supervisor Protect */ + uint32_t PACR2_WP:1; /* Write Protect */ + uint32_t PACR2_TP:1; /* Trusted Protect */ + uint32_t PACR3_BW:1; /* Buffer Writes */ + uint32_t PACR3_SP:1; /* Supervisor Protect */ + uint32_t PACR3_WP:1; /* Write Protect */ + uint32_t PACR3_TP:1; /* Trusted Protect */ + uint32_t PACR4_BW:1; /* Buffer Writes */ + uint32_t PACR4_SP:1; /* Supervisor Protect */ + uint32_t PACR4_WP:1; /* Write Protect */ + uint32_t PACR4_TP:1; /* Trusted Protect */ + uint32_t PACR5_BW:1; /* Buffer Writes */ + uint32_t PACR5_SP:1; /* Supervisor Protect */ + uint32_t PACR5_WP:1; /* Write Protect */ + uint32_t PACR5_TP:1; /* Trusted Protect */ + uint32_t PACR6_BW:1; /* Buffer Writes */ + uint32_t PACR6_SP:1; /* Supervisor Protect */ + uint32_t PACR6_WP:1; /* Write Protect */ + uint32_t PACR6_TP:1; /* Trusted Protect */ + uint32_t PACR7_BW:1; /* Buffer Writes */ + uint32_t PACR7_SP:1; /* Supervisor Protect */ + uint32_t PACR7_WP:1; /* Write Protect */ + uint32_t PACR7_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_PACR0_7_32B_tag; + + typedef union { /* PACR8_15 - Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t PACR8_BW:1; /* Buffer Writes */ + uint32_t PACR8_SP:1; /* Supervisor Protect */ + uint32_t PACR8_WP:1; /* Write Protect */ + uint32_t PACR8_TP:1; /* Trusted Protect */ + uint32_t PACR9_BW:1; /* Buffer Writes */ + uint32_t PACR9_SP:1; /* Supervisor Protect */ + uint32_t PACR9_WP:1; /* Write Protect */ + uint32_t PACR9_TP:1; /* Trusted Protect */ + uint32_t PACR10_BW:1; /* Buffer Writes */ + uint32_t PACR10_SP:1; /* Supervisor Protect */ + uint32_t PACR10_WP:1; /* Write Protect */ + uint32_t PACR10_TP:1; /* Trusted Protect */ + uint32_t PACR11_BW:1; /* Buffer Writes */ + uint32_t PACR11_SP:1; /* Supervisor Protect */ + uint32_t PACR11_WP:1; /* Write Protect */ + uint32_t PACR11_TP:1; /* Trusted Protect */ + uint32_t PACR12_BW:1; /* Buffer Writes */ + uint32_t PACR12_SP:1; /* Supervisor Protect */ + uint32_t PACR12_WP:1; /* Write Protect */ + uint32_t PACR12_TP:1; /* Trusted Protect */ + uint32_t PACR13_BW:1; /* Buffer Writes */ + uint32_t PACR13_SP:1; /* Supervisor Protect */ + uint32_t PACR13_WP:1; /* Write Protect */ + uint32_t PACR13_TP:1; /* Trusted Protect */ + uint32_t PACR14_BW:1; /* Buffer Writes */ + uint32_t PACR14_SP:1; /* Supervisor Protect */ + uint32_t PACR14_WP:1; /* Write Protect */ + uint32_t PACR14_TP:1; /* Trusted Protect */ + uint32_t PACR15_BW:1; /* Buffer Writes */ + uint32_t PACR15_SP:1; /* Supervisor Protect */ + uint32_t PACR15_WP:1; /* Write Protect */ + uint32_t PACR15_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_PACR8_15_32B_tag; + + typedef union { /* PACR16_23 - Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t PACR16_BW:1; /* Buffer Writes */ + uint32_t PACR16_SP:1; /* Supervisor Protect */ + uint32_t PACR16_WP:1; /* Write Protect */ + uint32_t PACR16_TP:1; /* Trusted Protect */ + uint32_t PACR17_BW:1; /* Buffer Writes */ + uint32_t PACR17_SP:1; /* Supervisor Protect */ + uint32_t PACR17_WP:1; /* Write Protect */ + uint32_t PACR17_TP:1; /* Trusted Protect */ + uint32_t PACR18_BW:1; /* Buffer Writes */ + uint32_t PACR18_SP:1; /* Supervisor Protect */ + uint32_t PACR18_WP:1; /* Write Protect */ + uint32_t PACR18_TP:1; /* Trusted Protect */ + uint32_t PACR19_BW:1; /* Buffer Writes */ + uint32_t PACR19_SP:1; /* Supervisor Protect */ + uint32_t PACR19_WP:1; /* Write Protect */ + uint32_t PACR19_TP:1; /* Trusted Protect */ + uint32_t PACR20_BW:1; /* Buffer Writes */ + uint32_t PACR20_SP:1; /* Supervisor Protect */ + uint32_t PACR20_WP:1; /* Write Protect */ + uint32_t PACR20_TP:1; /* Trusted Protect */ + uint32_t PACR21_BW:1; /* Buffer Writes */ + uint32_t PACR21_SP:1; /* Supervisor Protect */ + uint32_t PACR21_WP:1; /* Write Protect */ + uint32_t PACR21_TP:1; /* Trusted Protect */ + uint32_t PACR22_BW:1; /* Buffer Writes */ + uint32_t PACR22_SP:1; /* Supervisor Protect */ + uint32_t PACR22_WP:1; /* Write Protect */ + uint32_t PACR22_TP:1; /* Trusted Protect */ + uint32_t PACR23_BW:1; /* Buffer Writes */ + uint32_t PACR23_SP:1; /* Supervisor Protect */ + uint32_t PACR23_WP:1; /* Write Protect */ + uint32_t PACR23_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_PACR16_23_32B_tag; + + typedef union { /* PACR24_31 - Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t PACR24_BW:1; /* Buffer Writes */ + uint32_t PACR24_SP:1; /* Supervisor Protect */ + uint32_t PACR24_WP:1; /* Write Protect */ + uint32_t PACR24_TP:1; /* Trusted Protect */ + uint32_t PACR25_BW:1; /* Buffer Writes */ + uint32_t PACR25_SP:1; /* Supervisor Protect */ + uint32_t PACR25_WP:1; /* Write Protect */ + uint32_t PACR25_TP:1; /* Trusted Protect */ + uint32_t PACR26_BW:1; /* Buffer Writes */ + uint32_t PACR26_SP:1; /* Supervisor Protect */ + uint32_t PACR26_WP:1; /* Write Protect */ + uint32_t PACR26_TP:1; /* Trusted Protect */ + uint32_t PACR27_BW:1; /* Buffer Writes */ + uint32_t PACR27_SP:1; /* Supervisor Protect */ + uint32_t PACR27_WP:1; /* Write Protect */ + uint32_t PACR27_TP:1; /* Trusted Protect */ + uint32_t PACR28_BW:1; /* Buffer Writes */ + uint32_t PACR28_SP:1; /* Supervisor Protect */ + uint32_t PACR28_WP:1; /* Write Protect */ + uint32_t PACR28_TP:1; /* Trusted Protect */ + uint32_t PACR29_BW:1; /* Buffer Writes */ + uint32_t PACR29_SP:1; /* Supervisor Protect */ + uint32_t PACR29_WP:1; /* Write Protect */ + uint32_t PACR29_TP:1; /* Trusted Protect */ + uint32_t PACR30_BW:1; /* Buffer Writes */ + uint32_t PACR30_SP:1; /* Supervisor Protect */ + uint32_t PACR30_WP:1; /* Write Protect */ + uint32_t PACR30_TP:1; /* Trusted Protect */ + uint32_t PACR31_BW:1; /* Buffer Writes */ + uint32_t PACR31_SP:1; /* Supervisor Protect */ + uint32_t PACR31_WP:1; /* Write Protect */ + uint32_t PACR31_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_PACR24_31_32B_tag; + + typedef union { /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR0_BW:1; /* Buffer Writes */ + uint32_t OPACR0_SP:1; /* Supervisor Protect */ + uint32_t OPACR0_WP:1; /* Write Protect */ + uint32_t OPACR0_TP:1; /* Trusted Protect */ + uint32_t OPACR1_BW:1; /* Buffer Writes */ + uint32_t OPACR1_SP:1; /* Supervisor Protect */ + uint32_t OPACR1_WP:1; /* Write Protect */ + uint32_t OPACR1_TP:1; /* Trusted Protect */ + uint32_t OPACR2_BW:1; /* Buffer Writes */ + uint32_t OPACR2_SP:1; /* Supervisor Protect */ + uint32_t OPACR2_WP:1; /* Write Protect */ + uint32_t OPACR2_TP:1; /* Trusted Protect */ + uint32_t OPACR3_BW:1; /* Buffer Writes */ + uint32_t OPACR3_SP:1; /* Supervisor Protect */ + uint32_t OPACR3_WP:1; /* Write Protect */ + uint32_t OPACR3_TP:1; /* Trusted Protect */ + uint32_t OPACR4_BW:1; /* Buffer Writes */ + uint32_t OPACR4_SP:1; /* Supervisor Protect */ + uint32_t OPACR4_WP:1; /* Write Protect */ + uint32_t OPACR4_TP:1; /* Trusted Protect */ + uint32_t OPACR5_BW:1; /* Buffer Writes */ + uint32_t OPACR5_SP:1; /* Supervisor Protect */ + uint32_t OPACR5_WP:1; /* Write Protect */ + uint32_t OPACR5_TP:1; /* Trusted Protect */ + uint32_t OPACR6_BW:1; /* Buffer Writes */ + uint32_t OPACR6_SP:1; /* Supervisor Protect */ + uint32_t OPACR6_WP:1; /* Write Protect */ + uint32_t OPACR6_TP:1; /* Trusted Protect */ + uint32_t OPACR7_BW:1; /* Buffer Writes */ + uint32_t OPACR7_SP:1; /* Supervisor Protect */ + uint32_t OPACR7_WP:1; /* Write Protect */ + uint32_t OPACR7_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR0_7_32B_tag; + + typedef union { /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR8_BW:1; /* Buffer Writes */ + uint32_t OPACR8_SP:1; /* Supervisor Protect */ + uint32_t OPACR8_WP:1; /* Write Protect */ + uint32_t OPACR8_TP:1; /* Trusted Protect */ + uint32_t OPACR9_BW:1; /* Buffer Writes */ + uint32_t OPACR9_SP:1; /* Supervisor Protect */ + uint32_t OPACR9_WP:1; /* Write Protect */ + uint32_t OPACR9_TP:1; /* Trusted Protect */ + uint32_t OPACR10_BW:1; /* Buffer Writes */ + uint32_t OPACR10_SP:1; /* Supervisor Protect */ + uint32_t OPACR10_WP:1; /* Write Protect */ + uint32_t OPACR10_TP:1; /* Trusted Protect */ + uint32_t OPACR11_BW:1; /* Buffer Writes */ + uint32_t OPACR11_SP:1; /* Supervisor Protect */ + uint32_t OPACR11_WP:1; /* Write Protect */ + uint32_t OPACR11_TP:1; /* Trusted Protect */ + uint32_t OPACR12_BW:1; /* Buffer Writes */ + uint32_t OPACR12_SP:1; /* Supervisor Protect */ + uint32_t OPACR12_WP:1; /* Write Protect */ + uint32_t OPACR12_TP:1; /* Trusted Protect */ + uint32_t OPACR13_BW:1; /* Buffer Writes */ + uint32_t OPACR13_SP:1; /* Supervisor Protect */ + uint32_t OPACR13_WP:1; /* Write Protect */ + uint32_t OPACR13_TP:1; /* Trusted Protect */ + uint32_t OPACR14_BW:1; /* Buffer Writes */ + uint32_t OPACR14_SP:1; /* Supervisor Protect */ + uint32_t OPACR14_WP:1; /* Write Protect */ + uint32_t OPACR14_TP:1; /* Trusted Protect */ + uint32_t OPACR15_BW:1; /* Buffer Writes */ + uint32_t OPACR15_SP:1; /* Supervisor Protect */ + uint32_t OPACR15_WP:1; /* Write Protect */ + uint32_t OPACR15_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR8_15_32B_tag; + + typedef union { /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR16_BW:1; /* Buffer Writes */ + uint32_t OPACR16_SP:1; /* Supervisor Protect */ + uint32_t OPACR16_WP:1; /* Write Protect */ + uint32_t OPACR16_TP:1; /* Trusted Protect */ + uint32_t OPACR17_BW:1; /* Buffer Writes */ + uint32_t OPACR17_SP:1; /* Supervisor Protect */ + uint32_t OPACR17_WP:1; /* Write Protect */ + uint32_t OPACR17_TP:1; /* Trusted Protect */ + uint32_t OPACR18_BW:1; /* Buffer Writes */ + uint32_t OPACR18_SP:1; /* Supervisor Protect */ + uint32_t OPACR18_WP:1; /* Write Protect */ + uint32_t OPACR18_TP:1; /* Trusted Protect */ + uint32_t OPACR19_BW:1; /* Buffer Writes */ + uint32_t OPACR19_SP:1; /* Supervisor Protect */ + uint32_t OPACR19_WP:1; /* Write Protect */ + uint32_t OPACR19_TP:1; /* Trusted Protect */ + uint32_t OPACR20_BW:1; /* Buffer Writes */ + uint32_t OPACR20_SP:1; /* Supervisor Protect */ + uint32_t OPACR20_WP:1; /* Write Protect */ + uint32_t OPACR20_TP:1; /* Trusted Protect */ + uint32_t OPACR21_BW:1; /* Buffer Writes */ + uint32_t OPACR21_SP:1; /* Supervisor Protect */ + uint32_t OPACR21_WP:1; /* Write Protect */ + uint32_t OPACR21_TP:1; /* Trusted Protect */ + uint32_t OPACR22_BW:1; /* Buffer Writes */ + uint32_t OPACR22_SP:1; /* Supervisor Protect */ + uint32_t OPACR22_WP:1; /* Write Protect */ + uint32_t OPACR22_TP:1; /* Trusted Protect */ + uint32_t OPACR23_BW:1; /* Buffer Writes */ + uint32_t OPACR23_SP:1; /* Supervisor Protect */ + uint32_t OPACR23_WP:1; /* Write Protect */ + uint32_t OPACR23_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR16_23_32B_tag; + + typedef union { /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR24_BW:1; /* Buffer Writes */ + uint32_t OPACR24_SP:1; /* Supervisor Protect */ + uint32_t OPACR24_WP:1; /* Write Protect */ + uint32_t OPACR24_TP:1; /* Trusted Protect */ + uint32_t OPACR25_BW:1; /* Buffer Writes */ + uint32_t OPACR25_SP:1; /* Supervisor Protect */ + uint32_t OPACR25_WP:1; /* Write Protect */ + uint32_t OPACR25_TP:1; /* Trusted Protect */ + uint32_t OPACR26_BW:1; /* Buffer Writes */ + uint32_t OPACR26_SP:1; /* Supervisor Protect */ + uint32_t OPACR26_WP:1; /* Write Protect */ + uint32_t OPACR26_TP:1; /* Trusted Protect */ + uint32_t OPACR27_BW:1; /* Buffer Writes */ + uint32_t OPACR27_SP:1; /* Supervisor Protect */ + uint32_t OPACR27_WP:1; /* Write Protect */ + uint32_t OPACR27_TP:1; /* Trusted Protect */ + uint32_t OPACR28_BW:1; /* Buffer Writes */ + uint32_t OPACR28_SP:1; /* Supervisor Protect */ + uint32_t OPACR28_WP:1; /* Write Protect */ + uint32_t OPACR28_TP:1; /* Trusted Protect */ + uint32_t OPACR29_BW:1; /* Buffer Writes */ + uint32_t OPACR29_SP:1; /* Supervisor Protect */ + uint32_t OPACR29_WP:1; /* Write Protect */ + uint32_t OPACR29_TP:1; /* Trusted Protect */ + uint32_t OPACR30_BW:1; /* Buffer Writes */ + uint32_t OPACR30_SP:1; /* Supervisor Protect */ + uint32_t OPACR30_WP:1; /* Write Protect */ + uint32_t OPACR30_TP:1; /* Trusted Protect */ + uint32_t OPACR31_BW:1; /* Buffer Writes */ + uint32_t OPACR31_SP:1; /* Supervisor Protect */ + uint32_t OPACR31_WP:1; /* Write Protect */ + uint32_t OPACR31_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR24_31_32B_tag; + + typedef union { /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR32_BW:1; /* Buffer Writes */ + uint32_t OPACR32_SP:1; /* Supervisor Protect */ + uint32_t OPACR32_WP:1; /* Write Protect */ + uint32_t OPACR32_TP:1; /* Trusted Protect */ + uint32_t OPACR33_BW:1; /* Buffer Writes */ + uint32_t OPACR33_SP:1; /* Supervisor Protect */ + uint32_t OPACR33_WP:1; /* Write Protect */ + uint32_t OPACR33_TP:1; /* Trusted Protect */ + uint32_t OPACR34_BW:1; /* Buffer Writes */ + uint32_t OPACR34_SP:1; /* Supervisor Protect */ + uint32_t OPACR34_WP:1; /* Write Protect */ + uint32_t OPACR34_TP:1; /* Trusted Protect */ + uint32_t OPACR35_BW:1; /* Buffer Writes */ + uint32_t OPACR35_SP:1; /* Supervisor Protect */ + uint32_t OPACR35_WP:1; /* Write Protect */ + uint32_t OPACR35_TP:1; /* Trusted Protect */ + uint32_t OPACR36_BW:1; /* Buffer Writes */ + uint32_t OPACR36_SP:1; /* Supervisor Protect */ + uint32_t OPACR36_WP:1; /* Write Protect */ + uint32_t OPACR36_TP:1; /* Trusted Protect */ + uint32_t OPACR37_BW:1; /* Buffer Writes */ + uint32_t OPACR37_SP:1; /* Supervisor Protect */ + uint32_t OPACR37_WP:1; /* Write Protect */ + uint32_t OPACR37_TP:1; /* Trusted Protect */ + uint32_t OPACR38_BW:1; /* Buffer Writes */ + uint32_t OPACR38_SP:1; /* Supervisor Protect */ + uint32_t OPACR38_WP:1; /* Write Protect */ + uint32_t OPACR38_TP:1; /* Trusted Protect */ + uint32_t OPACR39_BW:1; /* Buffer Writes */ + uint32_t OPACR39_SP:1; /* Supervisor Protect */ + uint32_t OPACR39_WP:1; /* Write Protect */ + uint32_t OPACR39_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR32_39_32B_tag; + + typedef union { /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR40_BW:1; /* Buffer Writes */ + uint32_t OPACR40_SP:1; /* Supervisor Protect */ + uint32_t OPACR40_WP:1; /* Write Protect */ + uint32_t OPACR40_TP:1; /* Trusted Protect */ + uint32_t OPACR41_BW:1; /* Buffer Writes */ + uint32_t OPACR41_SP:1; /* Supervisor Protect */ + uint32_t OPACR41_WP:1; /* Write Protect */ + uint32_t OPACR41_TP:1; /* Trusted Protect */ + uint32_t OPACR42_BW:1; /* Buffer Writes */ + uint32_t OPACR42_SP:1; /* Supervisor Protect */ + uint32_t OPACR42_WP:1; /* Write Protect */ + uint32_t OPACR42_TP:1; /* Trusted Protect */ + uint32_t OPACR43_BW:1; /* Buffer Writes */ + uint32_t OPACR43_SP:1; /* Supervisor Protect */ + uint32_t OPACR43_WP:1; /* Write Protect */ + uint32_t OPACR43_TP:1; /* Trusted Protect */ + uint32_t OPACR44_BW:1; /* Buffer Writes */ + uint32_t OPACR44_SP:1; /* Supervisor Protect */ + uint32_t OPACR44_WP:1; /* Write Protect */ + uint32_t OPACR44_TP:1; /* Trusted Protect */ + uint32_t OPACR45_BW:1; /* Buffer Writes */ + uint32_t OPACR45_SP:1; /* Supervisor Protect */ + uint32_t OPACR45_WP:1; /* Write Protect */ + uint32_t OPACR45_TP:1; /* Trusted Protect */ + uint32_t OPACR46_BW:1; /* Buffer Writes */ + uint32_t OPACR46_SP:1; /* Supervisor Protect */ + uint32_t OPACR46_WP:1; /* Write Protect */ + uint32_t OPACR46_TP:1; /* Trusted Protect */ + uint32_t OPACR47_BW:1; /* Buffer Writes */ + uint32_t OPACR47_SP:1; /* Supervisor Protect */ + uint32_t OPACR47_WP:1; /* Write Protect */ + uint32_t OPACR47_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR40_47_32B_tag; + + typedef union { /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR48_BW:1; /* Buffer Writes */ + uint32_t OPACR48_SP:1; /* Supervisor Protect */ + uint32_t OPACR48_WP:1; /* Write Protect */ + uint32_t OPACR48_TP:1; /* Trusted Protect */ + uint32_t OPACR49_BW:1; /* Buffer Writes */ + uint32_t OPACR49_SP:1; /* Supervisor Protect */ + uint32_t OPACR49_WP:1; /* Write Protect */ + uint32_t OPACR49_TP:1; /* Trusted Protect */ + uint32_t OPACR50_BW:1; /* Buffer Writes */ + uint32_t OPACR50_SP:1; /* Supervisor Protect */ + uint32_t OPACR50_WP:1; /* Write Protect */ + uint32_t OPACR50_TP:1; /* Trusted Protect */ + uint32_t OPACR51_BW:1; /* Buffer Writes */ + uint32_t OPACR51_SP:1; /* Supervisor Protect */ + uint32_t OPACR51_WP:1; /* Write Protect */ + uint32_t OPACR51_TP:1; /* Trusted Protect */ + uint32_t OPACR52_BW:1; /* Buffer Writes */ + uint32_t OPACR52_SP:1; /* Supervisor Protect */ + uint32_t OPACR52_WP:1; /* Write Protect */ + uint32_t OPACR52_TP:1; /* Trusted Protect */ + uint32_t OPACR53_BW:1; /* Buffer Writes */ + uint32_t OPACR53_SP:1; /* Supervisor Protect */ + uint32_t OPACR53_WP:1; /* Write Protect */ + uint32_t OPACR53_TP:1; /* Trusted Protect */ + uint32_t OPACR54_BW:1; /* Buffer Writes */ + uint32_t OPACR54_SP:1; /* Supervisor Protect */ + uint32_t OPACR54_WP:1; /* Write Protect */ + uint32_t OPACR54_TP:1; /* Trusted Protect */ + uint32_t OPACR55_BW:1; /* Buffer Writes */ + uint32_t OPACR55_SP:1; /* Supervisor Protect */ + uint32_t OPACR55_WP:1; /* Write Protect */ + uint32_t OPACR55_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR48_55_32B_tag; + + typedef union { /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR56_BW:1; /* Buffer Writes */ + uint32_t OPACR56_SP:1; /* Supervisor Protect */ + uint32_t OPACR56_WP:1; /* Write Protect */ + uint32_t OPACR56_TP:1; /* Trusted Protect */ + uint32_t OPACR57_BW:1; /* Buffer Writes */ + uint32_t OPACR57_SP:1; /* Supervisor Protect */ + uint32_t OPACR57_WP:1; /* Write Protect */ + uint32_t OPACR57_TP:1; /* Trusted Protect */ + uint32_t OPACR58_BW:1; /* Buffer Writes */ + uint32_t OPACR58_SP:1; /* Supervisor Protect */ + uint32_t OPACR58_WP:1; /* Write Protect */ + uint32_t OPACR58_TP:1; /* Trusted Protect */ + uint32_t OPACR59_BW:1; /* Buffer Writes */ + uint32_t OPACR59_SP:1; /* Supervisor Protect */ + uint32_t OPACR59_WP:1; /* Write Protect */ + uint32_t OPACR59_TP:1; /* Trusted Protect */ + uint32_t OPACR60_BW:1; /* Buffer Writes */ + uint32_t OPACR60_SP:1; /* Supervisor Protect */ + uint32_t OPACR60_WP:1; /* Write Protect */ + uint32_t OPACR60_TP:1; /* Trusted Protect */ + uint32_t OPACR61_BW:1; /* Buffer Writes */ + uint32_t OPACR61_SP:1; /* Supervisor Protect */ + uint32_t OPACR61_WP:1; /* Write Protect */ + uint32_t OPACR61_TP:1; /* Trusted Protect */ + uint32_t OPACR62_BW:1; /* Buffer Writes */ + uint32_t OPACR62_SP:1; /* Supervisor Protect */ + uint32_t OPACR62_WP:1; /* Write Protect */ + uint32_t OPACR62_TP:1; /* Trusted Protect */ + uint32_t OPACR63_BW:1; /* Buffer Writes */ + uint32_t OPACR63_SP:1; /* Supervisor Protect */ + uint32_t OPACR63_WP:1; /* Write Protect */ + uint32_t OPACR63_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR56_63_32B_tag; + + typedef union { /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR64_BW:1; /* Buffer Writes */ + uint32_t OPACR64_SP:1; /* Supervisor Protect */ + uint32_t OPACR64_WP:1; /* Write Protect */ + uint32_t OPACR64_TP:1; /* Trusted Protect */ + uint32_t OPACR65_BW:1; /* Buffer Writes */ + uint32_t OPACR65_SP:1; /* Supervisor Protect */ + uint32_t OPACR65_WP:1; /* Write Protect */ + uint32_t OPACR65_TP:1; /* Trusted Protect */ + uint32_t OPACR66_BW:1; /* Buffer Writes */ + uint32_t OPACR66_SP:1; /* Supervisor Protect */ + uint32_t OPACR66_WP:1; /* Write Protect */ + uint32_t OPACR66_TP:1; /* Trusted Protect */ + uint32_t OPACR67_BW:1; /* Buffer Writes */ + uint32_t OPACR67_SP:1; /* Supervisor Protect */ + uint32_t OPACR67_WP:1; /* Write Protect */ + uint32_t OPACR67_TP:1; /* Trusted Protect */ + uint32_t OPACR68_BW:1; /* Buffer Writes */ + uint32_t OPACR68_SP:1; /* Supervisor Protect */ + uint32_t OPACR68_WP:1; /* Write Protect */ + uint32_t OPACR68_TP:1; /* Trusted Protect */ + uint32_t OPACR69_BW:1; /* Buffer Writes */ + uint32_t OPACR69_SP:1; /* Supervisor Protect */ + uint32_t OPACR69_WP:1; /* Write Protect */ + uint32_t OPACR69_TP:1; /* Trusted Protect */ + uint32_t OPACR70_BW:1; /* Buffer Writes */ + uint32_t OPACR70_SP:1; /* Supervisor Protect */ + uint32_t OPACR70_WP:1; /* Write Protect */ + uint32_t OPACR70_TP:1; /* Trusted Protect */ + uint32_t OPACR71_BW:1; /* Buffer Writes */ + uint32_t OPACR71_SP:1; /* Supervisor Protect */ + uint32_t OPACR71_WP:1; /* Write Protect */ + uint32_t OPACR71_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR64_71_32B_tag; + + typedef union { /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR72_BW:1; /* Buffer Writes */ + uint32_t OPACR72_SP:1; /* Supervisor Protect */ + uint32_t OPACR72_WP:1; /* Write Protect */ + uint32_t OPACR72_TP:1; /* Trusted Protect */ + uint32_t OPACR73_BW:1; /* Buffer Writes */ + uint32_t OPACR73_SP:1; /* Supervisor Protect */ + uint32_t OPACR73_WP:1; /* Write Protect */ + uint32_t OPACR73_TP:1; /* Trusted Protect */ + uint32_t OPACR74_BW:1; /* Buffer Writes */ + uint32_t OPACR74_SP:1; /* Supervisor Protect */ + uint32_t OPACR74_WP:1; /* Write Protect */ + uint32_t OPACR74_TP:1; /* Trusted Protect */ + uint32_t OPACR75_BW:1; /* Buffer Writes */ + uint32_t OPACR75_SP:1; /* Supervisor Protect */ + uint32_t OPACR75_WP:1; /* Write Protect */ + uint32_t OPACR75_TP:1; /* Trusted Protect */ + uint32_t OPACR76_BW:1; /* Buffer Writes */ + uint32_t OPACR76_SP:1; /* Supervisor Protect */ + uint32_t OPACR76_WP:1; /* Write Protect */ + uint32_t OPACR76_TP:1; /* Trusted Protect */ + uint32_t OPACR77_BW:1; /* Buffer Writes */ + uint32_t OPACR77_SP:1; /* Supervisor Protect */ + uint32_t OPACR77_WP:1; /* Write Protect */ + uint32_t OPACR77_TP:1; /* Trusted Protect */ + uint32_t OPACR78_BW:1; /* Buffer Writes */ + uint32_t OPACR78_SP:1; /* Supervisor Protect */ + uint32_t OPACR78_WP:1; /* Write Protect */ + uint32_t OPACR78_TP:1; /* Trusted Protect */ + uint32_t OPACR79_BW:1; /* Buffer Writes */ + uint32_t OPACR79_SP:1; /* Supervisor Protect */ + uint32_t OPACR79_WP:1; /* Write Protect */ + uint32_t OPACR79_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR72_79_32B_tag; + + typedef union { /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR80_BW:1; /* Buffer Writes */ + uint32_t OPACR80_SP:1; /* Supervisor Protect */ + uint32_t OPACR80_WP:1; /* Write Protect */ + uint32_t OPACR80_TP:1; /* Trusted Protect */ + uint32_t OPACR81_BW:1; /* Buffer Writes */ + uint32_t OPACR81_SP:1; /* Supervisor Protect */ + uint32_t OPACR81_WP:1; /* Write Protect */ + uint32_t OPACR81_TP:1; /* Trusted Protect */ + uint32_t OPACR82_BW:1; /* Buffer Writes */ + uint32_t OPACR82_SP:1; /* Supervisor Protect */ + uint32_t OPACR82_WP:1; /* Write Protect */ + uint32_t OPACR82_TP:1; /* Trusted Protect */ + uint32_t OPACR83_BW:1; /* Buffer Writes */ + uint32_t OPACR83_SP:1; /* Supervisor Protect */ + uint32_t OPACR83_WP:1; /* Write Protect */ + uint32_t OPACR83_TP:1; /* Trusted Protect */ + uint32_t OPACR84_BW:1; /* Buffer Writes */ + uint32_t OPACR84_SP:1; /* Supervisor Protect */ + uint32_t OPACR84_WP:1; /* Write Protect */ + uint32_t OPACR84_TP:1; /* Trusted Protect */ + uint32_t OPACR85_BW:1; /* Buffer Writes */ + uint32_t OPACR85_SP:1; /* Supervisor Protect */ + uint32_t OPACR85_WP:1; /* Write Protect */ + uint32_t OPACR85_TP:1; /* Trusted Protect */ + uint32_t OPACR86_BW:1; /* Buffer Writes */ + uint32_t OPACR86_SP:1; /* Supervisor Protect */ + uint32_t OPACR86_WP:1; /* Write Protect */ + uint32_t OPACR86_TP:1; /* Trusted Protect */ + uint32_t OPACR87_BW:1; /* Buffer Writes */ + uint32_t OPACR87_SP:1; /* Supervisor Protect */ + uint32_t OPACR87_WP:1; /* Write Protect */ + uint32_t OPACR87_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR80_87_32B_tag; + + typedef union { /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR88_BW:1; /* Buffer Writes */ + uint32_t OPACR88_SP:1; /* Supervisor Protect */ + uint32_t OPACR88_WP:1; /* Write Protect */ + uint32_t OPACR88_TP:1; /* Trusted Protect */ + uint32_t OPACR89_BW:1; /* Buffer Writes */ + uint32_t OPACR89_SP:1; /* Supervisor Protect */ + uint32_t OPACR89_WP:1; /* Write Protect */ + uint32_t OPACR89_TP:1; /* Trusted Protect */ + uint32_t OPACR90_BW:1; /* Buffer Writes */ + uint32_t OPACR90_SP:1; /* Supervisor Protect */ + uint32_t OPACR90_WP:1; /* Write Protect */ + uint32_t OPACR90_TP:1; /* Trusted Protect */ + uint32_t OPACR91_BW:1; /* Buffer Writes */ + uint32_t OPACR91_SP:1; /* Supervisor Protect */ + uint32_t OPACR91_WP:1; /* Write Protect */ + uint32_t OPACR91_TP:1; /* Trusted Protect */ + uint32_t OPACR92_BW:1; /* Buffer Writes */ + uint32_t OPACR92_SP:1; /* Supervisor Protect */ + uint32_t OPACR92_WP:1; /* Write Protect */ + uint32_t OPACR92_TP:1; /* Trusted Protect */ + uint32_t OPACR93_BW:1; /* Buffer Writes */ + uint32_t OPACR93_SP:1; /* Supervisor Protect */ + uint32_t OPACR93_WP:1; /* Write Protect */ + uint32_t OPACR93_TP:1; /* Trusted Protect */ + uint32_t OPACR94_BW:1; /* Buffer Writes */ + uint32_t OPACR94_SP:1; /* Supervisor Protect */ + uint32_t OPACR94_WP:1; /* Write Protect */ + uint32_t OPACR94_TP:1; /* Trusted Protect */ + uint32_t OPACR95_BW:1; /* Buffer Writes */ + uint32_t OPACR95_SP:1; /* Supervisor Protect */ + uint32_t OPACR95_WP:1; /* Write Protect */ + uint32_t OPACR95_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR88_95_32B_tag; + + + + typedef struct PBRIDGE_struct_tag { /* start of PBRIDGE_tag */ + /* MPROT - Master Privilege Registers */ + PBRIDGE_MPROT_32B_tag MPROT; /* offset: 0x0000 size: 32 bit */ + int8_t PBRIDGE_reserved_0004[28]; + /* PACR0_7 - Peripheral Access Control Registers */ + PBRIDGE_PACR0_7_32B_tag PACR0_7; /* offset: 0x0020 size: 32 bit */ + /* PACR8_15 - Peripheral Access Control Registers */ + PBRIDGE_PACR8_15_32B_tag PACR8_15; /* offset: 0x0024 size: 32 bit */ + /* PACR16_23 - Peripheral Access Control Registers */ + PBRIDGE_PACR16_23_32B_tag PACR16_23; /* offset: 0x0028 size: 32 bit */ + /* PACR24_31 - Peripheral Access Control Registers */ + PBRIDGE_PACR24_31_32B_tag PACR24_31; /* offset: 0x002C size: 32 bit */ + int8_t PBRIDGE_reserved_0030[16]; + /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR0_7_32B_tag OPACR0_7; /* offset: 0x0040 size: 32 bit */ + /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR8_15_32B_tag OPACR8_15; /* offset: 0x0044 size: 32 bit */ + /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR16_23_32B_tag OPACR16_23; /* offset: 0x0048 size: 32 bit */ + /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR24_31_32B_tag OPACR24_31; /* offset: 0x004C size: 32 bit */ + /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR32_39_32B_tag OPACR32_39; /* offset: 0x0050 size: 32 bit */ + /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR40_47_32B_tag OPACR40_47; /* offset: 0x0054 size: 32 bit */ + /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR48_55_32B_tag OPACR48_55; /* offset: 0x0058 size: 32 bit */ + /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR56_63_32B_tag OPACR56_63; /* offset: 0x005C size: 32 bit */ + /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR64_71_32B_tag OPACR64_71; /* offset: 0x0060 size: 32 bit */ + /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR72_79_32B_tag OPACR72_79; /* offset: 0x0064 size: 32 bit */ + /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR80_87_32B_tag OPACR80_87; /* offset: 0x0068 size: 32 bit */ + /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR88_95_32B_tag OPACR88_95; /* offset: 0x006C size: 32 bit */ + } PBRIDGE_tag; + + +#define PBRIDGE (*(volatile PBRIDGE_tag *) 0xFFF00000UL) + + + +/****************************************************************/ +/* */ +/* Module: MAX */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers MPR... */ + + typedef union { /* Master Priority Register for slave port n */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR_7:3; /* Master 7 Priority */ + uint32_t:1; + uint32_t MSTR_6:3; /* Master 6 Priority */ + uint32_t:1; + uint32_t MSTR_5:3; /* Master 5 Priority */ + uint32_t:1; + uint32_t MSTR_4:3; /* Master 4 Priority */ + uint32_t:1; + uint32_t MSTR_3:3; /* Master 3 Priority */ + uint32_t:1; + uint32_t MSTR_2:3; /* Master 2 Priority */ + uint32_t:1; + uint32_t MSTR_1:3; /* Master 1 Priority */ + uint32_t:1; + uint32_t MSTR_0:3; /* Master 0 Priority */ + } B; + } MAX_MPR_32B_tag; + + + /* Register layout for all registers AMPR matches xxx */ + + + /* Register layout for all registers SGPCR... */ + + typedef union { /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + uint32_t R; + struct { + uint32_t RO:1; /* Read Only */ + uint32_t HLP:1; /* Halt Low Priority */ + uint32_t:6; + uint32_t HPE7:1; /* High Priority Enable */ + uint32_t HPE6:1; /* High Priority Enable */ + uint32_t HPE5:1; /* High Priority Enable */ + uint32_t HPE4:1; /* High Priority Enable */ + uint32_t HPE3:1; /* High Priority Enable */ + uint32_t HPE2:1; /* High Priority Enable */ + uint32_t HPE1:1; /* High Priority Enable */ + uint32_t HPE0:1; /* High Priority Enable */ + uint32_t:6; + uint32_t ARB:2; /* Arbitration Mode */ + uint32_t:2; + uint32_t PCTL:2; /* Parking Control */ + uint32_t:1; + uint32_t PARK:3; /* Park */ + } B; + } MAX_SGPCR_32B_tag; + + + /* Register layout for all registers ASGPCR... */ + + typedef union { /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + uint32_t R; + struct { + uint32_t:1; + uint32_t HLP:1; /* Halt Low Priority */ + uint32_t:6; + uint32_t HPE7:1; /* High Priority Enable */ + uint32_t HPE6:1; /* High Priority Enable */ + uint32_t HPE5:1; /* High Priority Enable */ + uint32_t HPE4:1; /* High Priority Enable */ + uint32_t HPE3:1; /* High Priority Enable */ + uint32_t HPE2:1; /* High Priority Enable */ + uint32_t HPE1:1; /* High Priority Enable */ + uint32_t HPE0:1; /* High Priority Enable */ + uint32_t:6; + uint32_t ARB:2; /* Arbitration Mode */ + uint32_t:2; + uint32_t PCTL:2; /* Parking Control */ + uint32_t:1; + uint32_t PARK:3; /* Park */ + } B; + } MAX_ASGPCR_32B_tag; + + + /* Register layout for all registers MGPCR... */ + + typedef union { /* MAX_MGPCRn - Master General Purpose Control Register n */ + uint32_t R; + struct { + uint32_t:29; + uint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MAX_MGPCR_32B_tag; + + + typedef struct MAX_SLAVE_PORT_struct_tag { + + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR; /* relative offset: 0x0000 */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR; /* relative offset: 0x0004 */ + int8_t MAX_SLAVE_PORT_reserved_0008[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR; /* relative offset: 0x0010 */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR; /* relative offset: 0x0014 */ + int8_t MAX_SLAVE_PORT_reserved_0018[232]; + + } MAX_SLAVE_PORT_tag; + + typedef struct MAX_MASTER_PORT_struct_tag { + + /* MAX_MGPCRn - Master General Purpose Control Register n */ + MAX_MGPCR_32B_tag MGPCR; /* relative offset: 0x0000 */ + int8_t MAX_MASTER_PORT_reserved_0004[252]; + + } MAX_MASTER_PORT_tag; + + + typedef struct MAX_struct_tag { /* start of MAX_tag */ + union { + /* Register set SLAVE_PORT */ + MAX_SLAVE_PORT_tag SLAVE_PORT[8]; /* offset: 0x0000 (0x0100 x 8) */ + + struct { + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR0; /* offset: 0x0000 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR0; /* offset: 0x0004 size: 32 bit */ + int8_t MAX_reserved_0008_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR0; /* offset: 0x0010 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR0; /* offset: 0x0014 size: 32 bit */ + int8_t MAX_reserved_0018_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR1; /* offset: 0x0100 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR1; /* offset: 0x0104 size: 32 bit */ + int8_t MAX_reserved_0108_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR1; /* offset: 0x0110 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR1; /* offset: 0x0114 size: 32 bit */ + int8_t MAX_reserved_0118_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR2; /* offset: 0x0200 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR2; /* offset: 0x0204 size: 32 bit */ + int8_t MAX_reserved_0208_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR2; /* offset: 0x0210 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR2; /* offset: 0x0214 size: 32 bit */ + int8_t MAX_reserved_0218_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR3; /* offset: 0x0300 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR3; /* offset: 0x0304 size: 32 bit */ + int8_t MAX_reserved_0308_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR3; /* offset: 0x0310 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR3; /* offset: 0x0314 size: 32 bit */ + int8_t MAX_reserved_0318_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR4; /* offset: 0x0400 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR4; /* offset: 0x0404 size: 32 bit */ + int8_t MAX_reserved_0408_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR4; /* offset: 0x0410 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR4; /* offset: 0x0414 size: 32 bit */ + int8_t MAX_reserved_0418_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR5; /* offset: 0x0500 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR5; /* offset: 0x0504 size: 32 bit */ + int8_t MAX_reserved_0508_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR5; /* offset: 0x0510 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR5; /* offset: 0x0514 size: 32 bit */ + int8_t MAX_reserved_0518_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR6; /* offset: 0x0600 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR6; /* offset: 0x0604 size: 32 bit */ + int8_t MAX_reserved_0608_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR6; /* offset: 0x0610 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR6; /* offset: 0x0614 size: 32 bit */ + int8_t MAX_reserved_0618_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR7; /* offset: 0x0700 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR7; /* offset: 0x0704 size: 32 bit */ + int8_t MAX_reserved_0708_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR7; /* offset: 0x0710 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR7; /* offset: 0x0714 size: 32 bit */ + int8_t MAX_reserved_0718_E1[232]; + }; + + }; + union { + /* Register set MASTER_PORT */ + MAX_MASTER_PORT_tag MASTER_PORT[8]; /* offset: 0x0800 (0x0100 x 8) */ + + struct { + /* MAX_MGPCRn - Master General Purpose Control Register n */ + MAX_MGPCR_32B_tag MGPCR0; /* offset: 0x0800 size: 32 bit */ + int8_t MAX_reserved_0804_I1[252]; + MAX_MGPCR_32B_tag MGPCR1; /* offset: 0x0900 size: 32 bit */ + int8_t MAX_reserved_0904_I1[252]; + MAX_MGPCR_32B_tag MGPCR2; /* offset: 0x0A00 size: 32 bit */ + int8_t MAX_reserved_0A04_I1[252]; + MAX_MGPCR_32B_tag MGPCR3; /* offset: 0x0B00 size: 32 bit */ + int8_t MAX_reserved_0B04_I1[252]; + MAX_MGPCR_32B_tag MGPCR4; /* offset: 0x0C00 size: 32 bit */ + int8_t MAX_reserved_0C04_I1[252]; + MAX_MGPCR_32B_tag MGPCR5; /* offset: 0x0D00 size: 32 bit */ + int8_t MAX_reserved_0D04_I1[252]; + MAX_MGPCR_32B_tag MGPCR6; /* offset: 0x0E00 size: 32 bit */ + int8_t MAX_reserved_0E04_I1[252]; + MAX_MGPCR_32B_tag MGPCR7; /* offset: 0x0F00 size: 32 bit */ + int8_t MAX_reserved_0F04_E1[252]; + }; + + }; + } MAX_tag; + + +#define MAX (*(volatile MAX_tag *) 0xFFF04000UL) + + + +/****************************************************************/ +/* */ +/* Module: MPU */ +/* */ +/****************************************************************/ + + typedef union { /* MPU_CESR - MPU Control/Error Status Register */ + uint32_t R; + struct { + uint32_t SPERR:8; /* Slave Port n Error */ + uint32_t:4; + uint32_t HRL:4; /* Hardware Revision Level */ + uint32_t NSP:4; /* Number of Slave Ports */ + uint32_t NRGD:4; /* Number of Region Descriptors */ + uint32_t:7; + uint32_t VLD:1; /* Valid bit */ + } B; + } MPU_CESR_32B_tag; + + + /* Register layout for all registers EAR... */ + + typedef union { /* MPU_EARn - MPU Error Address Register, Slave Port n */ + uint32_t R; + struct { + uint32_t EADDR:32; /* Error Address */ + } B; + } MPU_EAR_32B_tag; + + + /* Register layout for all registers EDR... */ + + typedef union { /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + uint32_t R; + struct { + uint32_t EACD:16; /* Error Access Control Detail */ + uint32_t EPID:8; /* Error Process Identification */ + uint32_t EMN:4; /* Error Master Number */ + uint32_t EATTR:3; /* Error Attributes */ + uint32_t ERW:1; /* Error Read/Write */ + } B; + } MPU_EDR_32B_tag; + + + /* Register layout for all registers RGD_WORD0... */ + + typedef union { /* MPU_RGDn_Word0 - MPU Region Descriptor */ + uint32_t R; + struct { + uint32_t SRTADDR:27; /* Start Address */ + uint32_t:5; + } B; + } MPU_RGD_WORD0_32B_tag; + + + /* Register layout for all registers RGD_WORD1... */ + + typedef union { /* MPU_RGDn_Word1 - MPU Region Descriptor */ + uint32_t R; + struct { + uint32_t ENDADDR:27; /* End Address */ + uint32_t:5; + } B; + } MPU_RGD_WORD1_32B_tag; + + + /* Register layout for all registers RGD_WORD2... */ + + typedef union { /* MPU_RGDn_Word2 - MPU Region Descriptor */ + uint32_t R; + struct { + uint32_t M7RE:1; /* Bus Master 7 Read Enable */ + uint32_t M7WE:1; /* Bus Master 7 Write Enable */ + uint32_t M6RE:1; /* Bus Master 6 Read Enable */ + uint32_t M6WE:1; /* Bus Master 7 Write Enable */ + uint32_t M5RE:1; /* Bus Master 5 Read Enable */ + uint32_t M5WE:1; /* Bus Master 5 Write Enable */ + uint32_t M4RE:1; /* Bus Master 4 Read Enable */ + uint32_t M4WE:1; /* Bus Master 4 Write Enable */ + uint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */ + uint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */ + uint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */ + uint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */ + uint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */ + uint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */ + uint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */ + uint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */ + uint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */ + uint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */ + uint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */ + uint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */ + } B; + } MPU_RGD_WORD2_32B_tag; + + + /* Register layout for all registers RGD_WORD3... */ + + typedef union { /* MPU_RGDn_Word3 - MPU Region Descriptor */ + uint32_t R; + struct { + uint32_t PID:8; /* Process Identifier */ + uint32_t PIDMASK:8; /* Process Identifier Mask */ + uint32_t:15; + uint32_t VLD:1; /* Valid */ + } B; + } MPU_RGD_WORD3_32B_tag; + + + /* Register layout for all registers RGDAAC... */ + + typedef union { /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ + uint32_t R; + struct { + uint32_t M7RE:1; /* Bus Master 7 Read Enable */ + uint32_t M7WE:1; /* Bus Master 7 Write Enable */ + uint32_t M6RE:1; /* Bus Master 6 Read Enable */ + uint32_t M6WE:1; /* Bus Master 7 Write Enable */ + uint32_t M5RE:1; /* Bus Master 5 Read Enable */ + uint32_t M5WE:1; /* Bus Master 5 Write Enable */ + uint32_t M4RE:1; /* Bus Master 4 Read Enable */ + uint32_t M4WE:1; /* Bus Master 4 Write Enable */ + uint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */ + uint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */ + uint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */ + uint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */ + uint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */ + uint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */ + uint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */ + uint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */ + uint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */ + uint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */ + uint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */ + uint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */ + } B; + } MPU_RGDAAC_32B_tag; + + + typedef struct MPU_SLAVE_PORT_struct_tag { + + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR; /* relative offset: 0x0000 */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR; /* relative offset: 0x0004 */ + + } MPU_SLAVE_PORT_tag; + + typedef struct MPU_REGION_struct_tag { + + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD_WORD0; /* relative offset: 0x0000 */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD_WORD1; /* relative offset: 0x0004 */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD_WORD2; /* relative offset: 0x0008 */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD_WORD3; /* relative offset: 0x000C */ + + } MPU_REGION_tag; + + + typedef struct MPU_struct_tag { /* start of MPU_tag */ + /* MPU_CESR - MPU Control/Error Status Register */ + MPU_CESR_32B_tag CESR; /* offset: 0x0000 size: 32 bit */ + int8_t MPU_reserved_0004_C[12]; + union { + /* Register set SLAVE_PORT */ + MPU_SLAVE_PORT_tag SLAVE_PORT[4]; /* offset: 0x0010 (0x0008 x 4) */ + + struct { + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR0; /* offset: 0x0010 size: 32 bit */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR0; /* offset: 0x0014 size: 32 bit */ + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR1; /* offset: 0x0018 size: 32 bit */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR1; /* offset: 0x001C size: 32 bit */ + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR2; /* offset: 0x0020 size: 32 bit */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR2; /* offset: 0x0024 size: 32 bit */ + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR3; /* offset: 0x0028 size: 32 bit */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR3; /* offset: 0x002C size: 32 bit */ + }; + + }; + int8_t MPU_reserved_0030_C[976]; + union { + /* Register set REGION */ + MPU_REGION_tag REGION[16]; /* offset: 0x0400 (0x0010 x 16) */ + + struct { + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD0_WORD0; /* offset: 0x0400 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD0_WORD1; /* offset: 0x0404 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD0_WORD2; /* offset: 0x0408 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD0_WORD3; /* offset: 0x040C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD1_WORD0; /* offset: 0x0410 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD1_WORD1; /* offset: 0x0414 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD1_WORD2; /* offset: 0x0418 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD1_WORD3; /* offset: 0x041C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD2_WORD0; /* offset: 0x0420 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD2_WORD1; /* offset: 0x0424 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD2_WORD2; /* offset: 0x0428 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD2_WORD3; /* offset: 0x042C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD3_WORD0; /* offset: 0x0430 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD3_WORD1; /* offset: 0x0434 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD3_WORD2; /* offset: 0x0438 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD3_WORD3; /* offset: 0x043C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD4_WORD0; /* offset: 0x0440 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD4_WORD1; /* offset: 0x0444 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD4_WORD2; /* offset: 0x0448 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD4_WORD3; /* offset: 0x044C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD5_WORD0; /* offset: 0x0450 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD5_WORD1; /* offset: 0x0454 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD5_WORD2; /* offset: 0x0458 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD5_WORD3; /* offset: 0x045C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD6_WORD0; /* offset: 0x0460 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD6_WORD1; /* offset: 0x0464 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD6_WORD2; /* offset: 0x0468 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD6_WORD3; /* offset: 0x046C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD7_WORD0; /* offset: 0x0470 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD7_WORD1; /* offset: 0x0474 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD7_WORD2; /* offset: 0x0478 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD7_WORD3; /* offset: 0x047C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD8_WORD0; /* offset: 0x0480 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD8_WORD1; /* offset: 0x0484 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD8_WORD2; /* offset: 0x0488 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD8_WORD3; /* offset: 0x048C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD9_WORD0; /* offset: 0x0490 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD9_WORD1; /* offset: 0x0494 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD9_WORD2; /* offset: 0x0498 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD9_WORD3; /* offset: 0x049C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD10_WORD0; /* offset: 0x04A0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD10_WORD1; /* offset: 0x04A4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD10_WORD2; /* offset: 0x04A8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD10_WORD3; /* offset: 0x04AC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD11_WORD0; /* offset: 0x04B0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD11_WORD1; /* offset: 0x04B4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD11_WORD2; /* offset: 0x04B8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD11_WORD3; /* offset: 0x04BC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD12_WORD0; /* offset: 0x04C0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD12_WORD1; /* offset: 0x04C4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD12_WORD2; /* offset: 0x04C8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD12_WORD3; /* offset: 0x04CC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD13_WORD0; /* offset: 0x04D0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD13_WORD1; /* offset: 0x04D4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD13_WORD2; /* offset: 0x04D8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD13_WORD3; /* offset: 0x04DC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD14_WORD0; /* offset: 0x04E0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD14_WORD1; /* offset: 0x04E4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD14_WORD2; /* offset: 0x04E8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD14_WORD3; /* offset: 0x04EC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD15_WORD0; /* offset: 0x04F0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD15_WORD1; /* offset: 0x04F4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD15_WORD2; /* offset: 0x04F8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD15_WORD3; /* offset: 0x04FC size: 32 bit */ + }; + + }; + int8_t MPU_reserved_0500_C[768]; + union { + /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ + MPU_RGDAAC_32B_tag RGDAAC[16]; /* offset: 0x0800 (0x0004 x 16) */ + + struct { + /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ + MPU_RGDAAC_32B_tag RGDAAC0; /* offset: 0x0800 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC1; /* offset: 0x0804 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC2; /* offset: 0x0808 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC3; /* offset: 0x080C size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC4; /* offset: 0x0810 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC5; /* offset: 0x0814 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC6; /* offset: 0x0818 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC7; /* offset: 0x081C size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC8; /* offset: 0x0820 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC9; /* offset: 0x0824 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC10; /* offset: 0x0828 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC11; /* offset: 0x082C size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC12; /* offset: 0x0830 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC13; /* offset: 0x0834 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC14; /* offset: 0x0838 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC15; /* offset: 0x083C size: 32 bit */ + }; + + }; + } MPU_tag; + + +#define MPU (*(volatile MPU_tag *) 0xFFF10000UL) + + + +/****************************************************************/ +/* */ +/* Module: SEMA4 */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers GATE... */ + + typedef union { /* SEMA4_GATEn - Semephores Gate Register */ + uint8_t R; + struct { + uint8_t:6; + uint8_t GTFSM:2; /* Gate Finite State machine */ + } B; + } SEMA4_GATE_8B_tag; + + typedef union { /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */ + uint16_t R; + struct { + uint16_t INE:16; /* Interrupt Request Notification Enable */ + } B; + } SEMA4_CP0INE_16B_tag; + + typedef union { /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */ + uint16_t R; + struct { + uint16_t INE:16; /* Interrupt Request Notification Enable */ + } B; + } SEMA4_CP1INE_16B_tag; + + typedef union { /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */ + uint16_t R; + struct { + uint16_t GN:16; /* Gate 0 Notification */ + } B; + } SEMA4_CP0NTF_16B_tag; + + typedef union { /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */ + uint16_t R; + struct { + uint16_t GN:16; /* Gate 1 Notification */ + } B; + } SEMA4_CP1NTF_16B_tag; + + typedef union { /* SEMA4_RSTGT - Semaphores Reset Gate */ + uint16_t R; + struct { + uint16_t:2; + uint16_t RSTGSM:2; /* Reset Gate Finite State Machine */ + uint16_t RSTGDP:7; /* Reset Gate Data Pattern */ + uint16_t RSTGMS:3; /* Reset Gate Bus Master */ + uint16_t RSTGTN:8; /* Reset Gate Number */ + } B; + } SEMA4_RSTGT_16B_tag; + + typedef union { /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */ + uint16_t R; + struct { + uint16_t:2; + uint16_t RSTNSM:2; /* Reset Gate Finite State Machine */ + uint16_t RSTNDP:7; /* Reset Gate Data Pattern */ + uint16_t RSTNMS:3; /* Reset Gate Bus Master */ + uint16_t RSTNTN:8; /* Reset Gate Number */ + } B; + } SEMA4_RSTNTF_16B_tag; + + + + typedef struct SEMA4_struct_tag { /* start of SEMA4_tag */ + union { + /* SEMA4_GATEn - Semephores Gate Register */ + SEMA4_GATE_8B_tag GATE[16]; /* offset: 0x0000 (0x0001 x 16) */ + + struct { + /* SEMA4_GATEn - Semephores Gate Register */ + SEMA4_GATE_8B_tag GATE0; /* offset: 0x0000 size: 8 bit */ + SEMA4_GATE_8B_tag GATE1; /* offset: 0x0001 size: 8 bit */ + SEMA4_GATE_8B_tag GATE2; /* offset: 0x0002 size: 8 bit */ + SEMA4_GATE_8B_tag GATE3; /* offset: 0x0003 size: 8 bit */ + SEMA4_GATE_8B_tag GATE4; /* offset: 0x0004 size: 8 bit */ + SEMA4_GATE_8B_tag GATE5; /* offset: 0x0005 size: 8 bit */ + SEMA4_GATE_8B_tag GATE6; /* offset: 0x0006 size: 8 bit */ + SEMA4_GATE_8B_tag GATE7; /* offset: 0x0007 size: 8 bit */ + SEMA4_GATE_8B_tag GATE8; /* offset: 0x0008 size: 8 bit */ + SEMA4_GATE_8B_tag GATE9; /* offset: 0x0009 size: 8 bit */ + SEMA4_GATE_8B_tag GATE10; /* offset: 0x000A size: 8 bit */ + SEMA4_GATE_8B_tag GATE11; /* offset: 0x000B size: 8 bit */ + SEMA4_GATE_8B_tag GATE12; /* offset: 0x000C size: 8 bit */ + SEMA4_GATE_8B_tag GATE13; /* offset: 0x000D size: 8 bit */ + SEMA4_GATE_8B_tag GATE14; /* offset: 0x000E size: 8 bit */ + SEMA4_GATE_8B_tag GATE15; /* offset: 0x000F size: 8 bit */ + }; + + }; + int8_t SEMA4_reserved_0010[48]; + /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */ + SEMA4_CP0INE_16B_tag CP0INE; /* offset: 0x0040 size: 16 bit */ + int8_t SEMA4_reserved_0042[6]; + /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */ + SEMA4_CP1INE_16B_tag CP1INE; /* offset: 0x0048 size: 16 bit */ + int8_t SEMA4_reserved_004A[54]; + /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */ + SEMA4_CP0NTF_16B_tag CP0NTF; /* offset: 0x0080 size: 16 bit */ + int8_t SEMA4_reserved_0082[6]; + /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */ + SEMA4_CP1NTF_16B_tag CP1NTF; /* offset: 0x0088 size: 16 bit */ + int8_t SEMA4_reserved_008A[118]; + /* SEMA4_RSTGT - Semaphores Reset Gate */ + SEMA4_RSTGT_16B_tag RSTGT; /* offset: 0x0100 size: 16 bit */ + int8_t SEMA4_reserved_0102[2]; + /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */ + SEMA4_RSTNTF_16B_tag RSTNTF; /* offset: 0x0104 size: 16 bit */ + } SEMA4_tag; + + +#define SEMA4 (*(volatile SEMA4_tag *) 0xFFF24000UL) + + + +/****************************************************************/ +/* */ +/* Module: SWT */ +/* */ +/****************************************************************/ + + typedef union { /* SWT_CR - Control Register */ + uint32_t R; + struct { + uint32_t MAP0:1; /* Master Acces Protection for Master 0 */ + uint32_t MAP1:1; /* Master Acces Protection for Master 1 */ + uint32_t MAP2:1; /* Master Acces Protection for Master 2 */ + uint32_t MAP3:1; /* Master Acces Protection for Master 3 */ + uint32_t MAP4:1; /* Master Acces Protection for Master 4 */ + uint32_t MAP5:1; /* Master Acces Protection for Master 5 */ + uint32_t MAP6:1; /* Master Acces Protection for Master 6 */ + uint32_t MAP7:1; /* Master Acces Protection for Master 7 */ + uint32_t:14; + uint32_t KEY:1; /* Keyed Service Mode */ + uint32_t RIA:1; /* Reset on Invalid Access */ + uint32_t WND:1; /* Window Mode */ + uint32_t ITR:1; /* Interrupt Then Reset */ + uint32_t HLK:1; /* Hard Lock */ + uint32_t SLK:1; /* Soft Lock */ + uint32_t:1; + uint32_t STP:1; /* Stop Mode Control */ + uint32_t FRZ:1; /* Debug Mode Control */ + uint32_t WEN:1; /* Watchdog Enabled */ + } B; + } SWT_CR_32B_tag; + + typedef union { /* SWT_IR - SWT Interrupt Register */ + uint32_t R; + struct { + uint32_t:31; + uint32_t TIF:1; /* Time Out Interrupt Flag */ + } B; + } SWT_IR_32B_tag; + + typedef union { /* SWT_TO - SWT Time-Out Register */ + uint32_t R; + struct { + uint32_t WTO:32; /* Watchdog Time Out Period */ + } B; + } SWT_TO_32B_tag; + + typedef union { /* SWT_WN - SWT Window Register */ + uint32_t R; + struct { + uint32_t WST:32; /* Watchdog Time Out Period */ + } B; + } SWT_WN_32B_tag; + + typedef union { /* SWT_SR - SWT Service Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t WSC:16; /* Watchdog Service Code */ + } B; + } SWT_SR_32B_tag; + + typedef union { /* SWT_CO - SWT Counter Output Register */ + uint32_t R; + struct { + uint32_t CNT:32; /* Watchdog Count */ + } B; + } SWT_CO_32B_tag; + + typedef union { /* SWT_SK - SWT Service Key Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t SERVICEKEY:16; /* Service Key */ + } B; + } SWT_SK_32B_tag; + + + + typedef struct SWT_struct_tag { /* start of SWT_tag */ + /* SWT_CR - Control Register */ + SWT_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ + /* SWT_IR - SWT Interrupt Register */ + SWT_IR_32B_tag IR; /* offset: 0x0004 size: 32 bit */ + /* SWT_TO - SWT Time-Out Register */ + SWT_TO_32B_tag TO; /* offset: 0x0008 size: 32 bit */ + /* SWT_WN - SWT Window Register */ + SWT_WN_32B_tag WN; /* offset: 0x000C size: 32 bit */ + /* SWT_SR - SWT Service Register */ + SWT_SR_32B_tag SR; /* offset: 0x0010 size: 32 bit */ + /* SWT_CO - SWT Counter Output Register */ + SWT_CO_32B_tag CO; /* offset: 0x0014 size: 32 bit */ + /* SWT_SK - SWT Service Key Register */ + SWT_SK_32B_tag SK; /* offset: 0x0018 size: 32 bit */ + } SWT_tag; + + +#define SWT (*(volatile SWT_tag *) 0xFFF38000UL) + + + +/****************************************************************/ +/* */ +/* Module: STM */ +/* */ +/****************************************************************/ + + typedef union { /* STM_CR - Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t CPS:8; /* Counter Prescaler */ + uint32_t:6; + uint32_t FRZ:1; /* Freeze Control */ + uint32_t TEN:1; /* Timer Counter Enabled */ + } B; + } STM_CR_32B_tag; + + typedef union { /* STM_CNT - STM Count Register */ + uint32_t R; + } STM_CNT_32B_tag; + + + /* Register layout for all registers CCR... */ + + typedef union { /* STM_CCRn - STM Channel Control Register */ + uint32_t R; + struct { + uint32_t:31; + uint32_t CEN:1; /* Channel Enable */ + } B; + } STM_CCR_32B_tag; + + + /* Register layout for all registers CIR... */ + + typedef union { /* STM_CIRn - STM Channel Interrupt Register */ + uint32_t R; + struct { + uint32_t:31; + uint32_t CIF:1; /* Channel Interrupt Flag */ + } B; + } STM_CIR_32B_tag; + + + /* Register layout for all registers CMP... */ + + typedef union { /* STM_CMPn - STM Channel Compare Register */ + uint32_t R; + } STM_CMP_32B_tag; + + + typedef struct STM_CHANNEL_struct_tag { + + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR; /* relative offset: 0x0000 */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR; /* relative offset: 0x0004 */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP; /* relative offset: 0x0008 */ + int8_t STM_CHANNEL_reserved_000C[4]; + + } STM_CHANNEL_tag; + + + typedef struct STM_struct_tag { /* start of STM_tag */ + union { + STM_CR_32B_tag CR0; /* deprecated - please avoid */ + + /* STM_CR - Control Register */ + STM_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ + + }; + union { + STM_CNT_32B_tag CNT0; /* deprecated - please avoid */ + + /* STM_CNT - STM Count Register */ + STM_CNT_32B_tag CNT; /* offset: 0x0004 size: 32 bit */ + + }; + int8_t STM_reserved_0008_C[8]; + union { + /* Register set CHANNEL */ + STM_CHANNEL_tag CHANNEL[4]; /* offset: 0x0010 (0x0010 x 4) */ + + struct { + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR0; /* offset: 0x0010 size: 32 bit */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR0; /* offset: 0x0014 size: 32 bit */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP0; /* offset: 0x0018 size: 32 bit */ + int8_t STM_reserved_001C_I1[4]; + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR1; /* offset: 0x0020 size: 32 bit */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR1; /* offset: 0x0024 size: 32 bit */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP1; /* offset: 0x0028 size: 32 bit */ + int8_t STM_reserved_002C_I1[4]; + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR2; /* offset: 0x0030 size: 32 bit */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR2; /* offset: 0x0034 size: 32 bit */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP2; /* offset: 0x0038 size: 32 bit */ + int8_t STM_reserved_003C_I1[4]; + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR3; /* offset: 0x0040 size: 32 bit */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR3; /* offset: 0x0044 size: 32 bit */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP3; /* offset: 0x0048 size: 32 bit */ + int8_t STM_reserved_004C_E1[4]; + }; + + }; + } STM_tag; + + +#define STM (*(volatile STM_tag *) 0xFFF3C000UL) + + + +/****************************************************************/ +/* */ +/* Module: SPP_MCM */ +/* */ +/****************************************************************/ + + typedef union { /* SPP_MCM_PCT - Processor Core Type */ + uint16_t R; + struct { + uint16_t PCTYPE:16; /* Processor Core Type */ + } B; + } SPP_MCM_PCT_16B_tag; + + typedef union { /* SPP_MCM_PLREV - SOC-Defined Platform Revision */ + uint16_t R; + struct { + uint16_t PLREVISION:16; /* Platform Revision */ + } B; + } SPP_MCM_PLREV_16B_tag; + + typedef union { /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */ + uint32_t R; + struct { + uint32_t PMC:32; /* IPS Module Configuration */ + } B; + } SPP_MCM_IOPMC_32B_tag; + + typedef union { /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */ + uint8_t R; + struct { + uint8_t POR:1; /* Power on Reset */ +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t OFPLR:1; /* Off-Platform Reset */ +#else + uint8_t DIR:1; /* deprecated name - please avoid */ +#endif + uint8_t:6; + } B; + } SPP_MCM_MRSR_8B_tag; + + typedef union { /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */ + uint8_t R; + struct { + uint8_t ENBWCR:1; /* Enable WCR */ + uint8_t:3; + uint8_t PRILVL:4; /* Interrupt Priority Level */ + } B; + } SPP_MCM_MWCR_8B_tag; + + typedef union { /* SPP_MCM_MIR - Miscellaneous Interrupt Register */ + uint8_t R; + struct { + uint8_t FB0AI:1; /* Flash Bank 0 Abort Interrupt */ + uint8_t FB0SI:1; /* Flash Bank 0 Stall Interrupt */ + uint8_t FB1AI:1; /* Flash Bank 1 Abort Interrupt */ + uint8_t FB1SI:1; /* Flash Bank 1 Stall Interrupt */ + uint8_t FB2AI:1; /* Flash Bank 2 Abort Interrupt */ + uint8_t FB2SI:1; /* Flash Bank 2 Stall Interrupt */ + uint8_t:2; + } B; + } SPP_MCM_MIR_8B_tag; + + typedef union { /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */ + uint32_t R; + struct { + uint32_t MUSERDCR:32; /* User Defined Control Register */ + } B; + } SPP_MCM_MUDCR_32B_tag; + + typedef union { /* SPP_MCM_ECR - ECC Configuration Register */ + uint8_t R; + struct { + uint8_t:2; +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t EPR1BR:1; /* Enable Platform RAM 1-bit Reporting */ +#else + uint8_t ER1BR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t EPF1BR:1; /* Enable Platform FLASH 1-bit Reporting */ +#else + uint8_t EF1BR:1; /* deprecated name - please avoid */ +#endif + uint8_t:2; +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t EPRNCR:1; /* Enable Platform RAM Non-Correctable Reporting */ +#else + uint8_t ERNCR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t EPFNCR:1; /* Enable Platform FLASH Non-Correctable Reporting */ +#else + uint8_t EFNCR:1; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_ECR_8B_tag; + + typedef union { /* SPP_MCM_ESR - ECC Status Register */ + uint8_t R; + struct { + uint8_t:2; +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t PR1BC:1; /* Platform RAM 1-bit Correction */ +#else + uint8_t R1BC:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t PF1BC:1; /* Platform FLASH 1-bit Correction */ +#else + uint8_t F1BC:1; /* deprecated name - please avoid */ +#endif + uint8_t:2; +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t PRNCE:1; /* Platform RAM Non-Correctable Error */ +#else + uint8_t RNCE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t PFNCE:1; /* Platform FLASH Non-Correctable Error */ +#else + uint8_t FNCE:1; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_ESR_8B_tag; + + typedef union { /* SPP_MCM_EEGR - ECC Error Generation Register */ + uint16_t R; + struct { + uint16_t FRCAP:1; /* Force Platform RAM Error Injection Access Protection */ + uint16_t:1; + uint16_t FRC1BI:1; /* Force Platform RAM Continuous 1-Bit Data Inversions */ + uint16_t FR11BI:1; /* Force Platform RAM One 1-Bit Data Inversion */ + uint16_t:2; + uint16_t FRCNCI:1; /* Force Platform RAM Continuous Noncorrectable Data Inversions */ + uint16_t FR1NCI:1; /* Force Platform RAM One Noncorrectable Data Inversions */ + uint16_t:1; + uint16_t ERRBIT:7; /* Error Bit Position */ + } B; + } SPP_MCM_EEGR_16B_tag; + + typedef union { /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */ + uint32_t R; + } SPP_MCM_PFEAR_32B_tag; + + typedef union { /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */ + uint8_t R; + } SPP_MCM_PFEMR_8B_tag; + + typedef union { /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */ + uint8_t R; + struct { +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t F_WRITE:1; /* AMBA-AHBH Write */ +#else + uint8_t WRITE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t F_SIZE:3; /* AMBA-AHBH Size */ +#else + uint8_t SIZE:3; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t F_PROTECT:4; /* AMBA-AHBH PROT */ +#else + uint8_t PROTECTION:4; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_PFEAT_8B_tag; + + typedef union { /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */ + uint32_t R; + } SPP_MCM_PFEDRH_32B_tag; + + typedef union { /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */ + uint32_t R; + } SPP_MCM_PFEDR_32B_tag; + + typedef union { /* SPP_MCM_PREAR - Platform RAM ECC Address Register */ + uint32_t R; + } SPP_MCM_PREAR_32B_tag; + + typedef union { /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */ + uint8_t R; + } SPP_MCM_PRESR_8B_tag; + + typedef union { /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */ + uint8_t R; + struct { + uint8_t:4; +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t PR_EMR:4; /* Platform RAM ECC Master Number */ +#else + uint8_t REMR:4; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_PREMR_8B_tag; + + typedef union { /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */ + uint8_t R; + struct { +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t R_WRITE:1; /* AMBA-AHBH Write */ +#else + uint8_t WRITE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t R_SIZE:3; /* AMBA-AHBH Size */ +#else + uint8_t SIZE:3; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t R_PROTECT:4; /* AMBA-AHBH PROT */ +#else + uint8_t PROTECTION:4; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_PREAT_8B_tag; + + typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */ + uint32_t R; + } SPP_MCM_PREDRH_32B_tag; + + typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register */ + uint32_t R; + } SPP_MCM_PREDR_32B_tag; + + + + typedef struct SPP_MCM_struct_tag { /* start of SPP_MCM_tag */ + /* SPP_MCM_PCT - Processor Core Type */ + SPP_MCM_PCT_16B_tag PCT; /* offset: 0x0000 size: 16 bit */ + union { + SPP_MCM_PLREV_16B_tag REV; /* deprecated - please avoid */ + + /* SPP_MCM_PLREV - SOC-Defined Platform Revision */ + SPP_MCM_PLREV_16B_tag PLREV; /* offset: 0x0002 size: 16 bit */ + + }; + int8_t SPP_MCM_reserved_0004_C[4]; + union { + SPP_MCM_IOPMC_32B_tag MC; /* deprecated - please avoid */ + + /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */ + SPP_MCM_IOPMC_32B_tag IOPMC; /* offset: 0x0008 size: 32 bit */ + + }; + int8_t SPP_MCM_reserved_000C[3]; + /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */ + SPP_MCM_MRSR_8B_tag MRSR; /* offset: 0x000F size: 8 bit */ + int8_t SPP_MCM_reserved_0010[3]; + /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */ + SPP_MCM_MWCR_8B_tag MWCR; /* offset: 0x0013 size: 8 bit */ + int8_t SPP_MCM_reserved_0014[11]; + /* SPP_MCM_MIR - Miscellaneous Interrupt Register */ + SPP_MCM_MIR_8B_tag MIR; /* offset: 0x001F size: 8 bit */ + int8_t SPP_MCM_reserved_0020[4]; + /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */ + SPP_MCM_MUDCR_32B_tag MUDCR; /* offset: 0x0024 size: 32 bit */ + int8_t SPP_MCM_reserved_0028[27]; + /* SPP_MCM_ECR - ECC Configuration Register */ + SPP_MCM_ECR_8B_tag ECR; /* offset: 0x0043 size: 8 bit */ + int8_t SPP_MCM_reserved_0044[3]; + /* SPP_MCM_ESR - ECC Status Register */ + SPP_MCM_ESR_8B_tag ESR; /* offset: 0x0047 size: 8 bit */ + int8_t SPP_MCM_reserved_0048[2]; + /* SPP_MCM_EEGR - ECC Error Generation Register */ + SPP_MCM_EEGR_16B_tag EEGR; /* offset: 0x004A size: 16 bit */ + int8_t SPP_MCM_reserved_004C_C[4]; + union { + /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */ + SPP_MCM_PFEAR_32B_tag PFEAR; /* offset: 0x0050 size: 32 bit */ + + SPP_MCM_PFEAR_32B_tag FEAR; /* deprecated - please avoid */ + + }; + int8_t SPP_MCM_reserved_0054_C[2]; + union { + /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */ + SPP_MCM_PFEMR_8B_tag PFEMR; /* offset: 0x0056 size: 8 bit */ + + SPP_MCM_PFEMR_8B_tag FEMR; /* deprecated - please avoid */ + + }; + union { + /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */ + SPP_MCM_PFEAT_8B_tag PFEAT; /* offset: 0x0057 size: 8 bit */ + + SPP_MCM_PFEAT_8B_tag FEAT; /* deprecated - please avoid */ + + }; + /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */ + SPP_MCM_PFEDRH_32B_tag PFEDRH; /* offset: 0x0058 size: 32 bit */ + union { + /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */ + SPP_MCM_PFEDR_32B_tag PFEDR; /* offset: 0x005C size: 32 bit */ + + SPP_MCM_PFEDR_32B_tag FEDR; /* deprecated - please avoid */ + + }; + union { + SPP_MCM_PREAR_32B_tag REAR; /* deprecated - please avoid */ + + /* SPP_MCM_PREAR - Platform RAM ECC Address Register */ + SPP_MCM_PREAR_32B_tag PREAR; /* offset: 0x0060 size: 32 bit */ + + }; + int8_t SPP_MCM_reserved_0064_C; + union { + SPP_MCM_PRESR_8B_tag RESR; /* deprecated - please avoid */ + + /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */ + SPP_MCM_PRESR_8B_tag PRESR; /* offset: 0x0065 size: 8 bit */ + + }; + union { + SPP_MCM_PREMR_8B_tag REMR; /* deprecated - please avoid */ + + /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */ + SPP_MCM_PREMR_8B_tag PREMR; /* offset: 0x0066 size: 8 bit */ + + }; + union { + SPP_MCM_PREAT_8B_tag REAT; /* deprecated - please avoid */ + + /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */ + SPP_MCM_PREAT_8B_tag PREAT; /* offset: 0x0067 size: 8 bit */ + + }; + /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */ + SPP_MCM_PREDRH_32B_tag PREDRH; /* offset: 0x0068 size: 32 bit */ + union { + SPP_MCM_PREDR_32B_tag REDR; /* deprecated - please avoid */ + + /* SPP_MCM_PREDR - Platform RAM ECC Data Register */ + SPP_MCM_PREDR_32B_tag PREDR; /* offset: 0x006C size: 32 bit */ + + }; + } SPP_MCM_tag; + + +#define SPP_MCM (*(volatile SPP_MCM_tag *) 0xFFF40000UL) + + + +/****************************************************************/ +/* */ +/* Module: SPP_DMA2 */ +/* */ +/****************************************************************/ + + typedef union { /* SPP_DMA2_DMACR - DMA Control Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t CX:1; /* Cancel Transfer */ + uint32_t ECX:1; /* Error Cancel Transfer */ + uint32_t GRP3PRI:2; /* Channel Group 3 Priority */ + uint32_t GRP2PRI:2; /* Channel Group 2 Priority */ + uint32_t GRP1PRI:2; /* Channel Group 1 Priority */ + uint32_t GRP0PRI:2; /* Channel Group 0 Priority */ + uint32_t EMLM:1; /* Enable Minor Loop Mapping */ + uint32_t CLM:1; /* Continuous Link Mode */ + uint32_t HALT:1; /* Halt DMA Operations */ + uint32_t HOE:1; /* Halt on Error */ + uint32_t ERGA:1; /* Enable Round Robin Group Arbitration */ + uint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */ + uint32_t EDBG:1; /* Enable Debug */ + uint32_t EBW:1; /* Enable Buffered Writes */ + } B; + } SPP_DMA2_DMACR_32B_tag; + + typedef union { /* SPP_DMA2_DMAES - DMA Error Status Register */ + uint32_t R; + struct { + uint32_t VLD:1; /* Logical OR of DMAERRH and DMAERRL status bits */ + uint32_t:14; + uint32_t ECX:1; /* Transfer Cancelled */ + uint32_t GPE:1; /* Group Priority Error */ + uint32_t CPE:1; /* Channel Priority Error */ + uint32_t ERRCHN:6; /* Error Channel Number or Cancelled Channel Number */ + uint32_t SAE:1; /* Source Address Error */ + uint32_t SOE:1; /* Source Offset Error */ + uint32_t DAE:1; /* Destination Address Error */ + uint32_t DOE:1; /* Destination Offset Error */ + uint32_t NCE:1; /* Nbytes/Citer Configuration Error */ + uint32_t SGE:1; /* Scatter/Gather Configuration Error */ + uint32_t SBE:1; /* Source Bus Error */ + uint32_t DBE:1; /* Destination Bus Error */ + } B; + } SPP_DMA2_DMAES_32B_tag; + + typedef union { /* SPP_DMA2_DMAERQH - DMA Enable Request Register */ + uint32_t R; + struct { + uint32_t ERQ:32; /* DMA Enable Request */ + } B; + } SPP_DMA2_DMAERQH_32B_tag; + + typedef union { /* SPP_DMA2_DMAERQL - DMA Enable Request Register */ + uint32_t R; + struct { + uint32_t ERQ:32; /* DMA Enable Request */ + } B; + } SPP_DMA2_DMAERQL_32B_tag; + + typedef union { /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */ + uint32_t R; + struct { + uint32_t EEI:32; /* DMA Enable Error Interrupt */ + } B; + } SPP_DMA2_DMAEEIH_32B_tag; + + typedef union { /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */ + uint32_t R; + struct { + uint32_t EEI:32; /* DMA Enable Error Interrupt */ + } B; + } SPP_DMA2_DMAEEIL_32B_tag; + + typedef union { /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */ + uint8_t R; + struct { + uint8_t:1; + uint8_t SERQ:7; /* Set Enable Request */ + } B; + } SPP_DMA2_DMASERQ_8B_tag; + + typedef union { /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */ + uint8_t R; + struct { + uint8_t:1; + uint8_t CERQ:7; /* Clear Enable Request */ + } B; + } SPP_DMA2_DMACERQ_8B_tag; + + typedef union { /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */ + uint8_t R; + struct { + uint8_t:1; + uint8_t SEEI:7; /* Set Enable Error Interrupt */ + } B; + } SPP_DMA2_DMASEEI_8B_tag; + + typedef union { /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */ + uint8_t R; + struct { + uint8_t:1; + uint8_t CEEI:7; /* Clear Enable Error Interrupt */ + } B; + } SPP_DMA2_DMACEEI_8B_tag; + + typedef union { /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */ + uint8_t R; + struct { + uint8_t:1; + uint8_t CINT:7; /* Clear Interrupt Request */ + } B; + } SPP_DMA2_DMACINT_8B_tag; + + typedef union { /* SPP_DMA2_DMACERR - DMA Clear Error */ + uint8_t R; + struct { + uint8_t:1; + uint8_t CERR:7; /* Clear Error Indicator */ + } B; + } SPP_DMA2_DMACERR_8B_tag; + + typedef union { /* SPP_DMA2_DMASSRT - DMA Set START Bit */ + uint8_t R; + struct { + uint8_t:1; + uint8_t SSRT:7; /* Set START Bit */ + } B; + } SPP_DMA2_DMASSRT_8B_tag; + + typedef union { /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */ + uint8_t R; + struct { + uint8_t:1; + uint8_t CDNE:7; /* Clear DONE Status Bit */ + } B; + } SPP_DMA2_DMACDNE_8B_tag; + + typedef union { /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */ + uint32_t R; + struct { + uint32_t INT:32; /* DMA Interrupt Request */ + } B; + } SPP_DMA2_DMAINTH_32B_tag; + + typedef union { /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */ + uint32_t R; + struct { + uint32_t INT:32; /* DMA Interrupt Request */ + } B; + } SPP_DMA2_DMAINTL_32B_tag; + + typedef union { /* SPP_DMA2_DMAERRH - DMA Error Register */ + uint32_t R; + struct { + uint32_t ERR:32; /* DMA Error n */ + } B; + } SPP_DMA2_DMAERRH_32B_tag; + + typedef union { /* SPP_DMA2_DMAERRL - DMA Error Register */ + uint32_t R; + struct { + uint32_t ERR:32; /* DMA Error n */ + } B; + } SPP_DMA2_DMAERRL_32B_tag; + + typedef union { /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */ + uint32_t R; + struct { + uint32_t HRS:32; /* DMA Hardware Request Status */ + } B; + } SPP_DMA2_DMAHRSH_32B_tag; + + typedef union { /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */ + uint32_t R; + struct { + uint32_t HRS:32; /* DMA Hardware Request Status */ + } B; + } SPP_DMA2_DMAHRSL_32B_tag; + + typedef union { /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */ + uint32_t R; + struct { + uint32_t GPOR:32; /* DMA General Purpose Output */ + } B; + } SPP_DMA2_DMAGPOR_32B_tag; + + + /* Register layout for all registers DCHPRI... */ + + typedef union { /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ + uint8_t R; + struct { + uint8_t ECP:1; /* Enable Channel Preemption */ + uint8_t DPA:1; /* Disable Preempt Ability */ + uint8_t GRPPRI:2; /* Channel n Current Group Priority */ + uint8_t CHPRI:4; /* Channel n Arbitration Priority */ + } B; + } SPP_DMA2_DCHPRI_8B_tag; + + + /* Register layout for all registers TCDWORD0_... */ + + typedef union { /* SPP_DMA2_TCDn Word0 - Source Address */ + uint32_t R; + struct { + uint32_t SADDR:32; /* Source Address */ + } B; + } SPP_DMA2_TCDWORD0__32B_tag; + + + /* Register layout for all registers TCDWORD4_... */ + + typedef union { /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + uint32_t R; + struct { + uint32_t SMOD:5; /* Source Address Modulo */ + uint32_t SSIZE:3; /* Source Data Transfer Size */ + uint32_t DMOD:5; /* Destination Address Module */ + uint32_t DSIZE:3; /* Destination Data Transfer Size */ + uint32_t SOFF:16; /* Source Address Signed Offset */ + } B; + } SPP_DMA2_TCDWORD4__32B_tag; + + + /* Register layout for all registers TCDWORD8_... */ + + typedef union { /* SPP_DMA2_TCDn Word2 - nbytes */ + uint32_t R; + struct { + uint32_t SMLOE:1; /* Source Minor Loop Offset Enable */ + uint32_t DMLOE:1; /* Destination Minor Loop Offset Enable */ + uint32_t MLOFF:20; /* Minor Loop Offset */ + uint32_t NBYTES:10; /* Inner Minor byte transfer Count */ + } B; + } SPP_DMA2_TCDWORD8__32B_tag; + + + /* Register layout for all registers TCDWORD12_... */ + + typedef union { /* SPP_DMA2_TCDn Word3 - slast */ + uint32_t R; + struct { + uint32_t SLAST:32; /* Last Source Address Adjustment */ + } B; + } SPP_DMA2_TCDWORD12__32B_tag; + + + /* Register layout for all registers TCDWORD16_... */ + + typedef union { /* SPP_DMA2_TCDn Word4 - daddr */ + uint32_t R; + struct { + uint32_t DADDR:32; /* Destination Address */ + } B; + } SPP_DMA2_TCDWORD16__32B_tag; + + + /* Register layout for all registers TCDWORD20_... */ + + typedef union { /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + uint32_t R; + struct { + uint32_t CITER_E_LINK:1; /* Enable Channel to channel linking on minor loop complete */ + uint32_t CITER_LINKCH:6; /* Link Channel Number */ + uint32_t CITER:9; /* Current Major Iteration Count */ + uint32_t DOFF:16; /* Destination Address Signed Offset */ + } B; + } SPP_DMA2_TCDWORD20__32B_tag; + + + /* Register layout for all registers TCDWORD24_... */ + + typedef union { /* SPP_DMA2_TCDn Word6 - dlast_sga */ + uint32_t R; + struct { + uint32_t DLAST_SGA:32; /* Last destination address adjustment */ + } B; + } SPP_DMA2_TCDWORD24__32B_tag; + + + /* Register layout for all registers TCDWORD28_... */ + + typedef union { /* SPP_DMA2_TCDn Word7 - biter, etc. */ + uint32_t R; + struct { + +#ifndef USE_FIELD_ALIASES_SPP_DMA2 + uint32_t BITER_E_LINK:1; /* beginning ("major") iteration count */ +#else + uint32_t BITERE_LINK:1; /* deprecated name - please avoid */ +#endif + uint32_t BITER:15; /* Enable Channel to Channel linking on minor loop complete */ + uint32_t BWC:2; /* Bandwidth Control */ + uint32_t MAJOR_LINKCH:6; /* Link Channel Number */ + uint32_t DONE:1; /* channel done */ + uint32_t ACTIVE:1; /* Channel Active */ + uint32_t MAJOR_E_LINK:1; /* Enable Channel to Channel Linking on major loop complete */ + uint32_t E_SG:1; /* Enable Scatter/Gather Processing */ + uint32_t D_REQ:1; /* Disable Request */ + uint32_t INT_HALF:1; /* Enable an Interrupt when Major Counter is half complete */ + uint32_t INT_MAJ:1; /* Enable an Interrupt when Major Iteration count completes */ + uint32_t START:1; /* Channel Start */ + } B; + } SPP_DMA2_TCDWORD28__32B_tag; + + + typedef struct SPP_DMA2_CHANNEL_struct_tag { + + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_; /* relative offset: 0x0000 */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_; /* relative offset: 0x0004 */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_; /* relative offset: 0x0008 */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_; /* relative offset: 0x000C */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_; /* relative offset: 0x0010 */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_; /* relative offset: 0x0014 */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_; /* relative offset: 0x0018 */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_; /* relative offset: 0x001C */ + + } SPP_DMA2_CHANNEL_tag; + + + typedef struct SPP_DMA2_struct_tag { /* start of SPP_DMA2_tag */ + /* SPP_DMA2_DMACR - DMA Control Register */ + SPP_DMA2_DMACR_32B_tag DMACR; /* offset: 0x0000 size: 32 bit */ + /* SPP_DMA2_DMAES - DMA Error Status Register */ + SPP_DMA2_DMAES_32B_tag DMAES; /* offset: 0x0004 size: 32 bit */ + /* SPP_DMA2_DMAERQH - DMA Enable Request Register */ + SPP_DMA2_DMAERQH_32B_tag DMAERQH; /* offset: 0x0008 size: 32 bit */ + /* SPP_DMA2_DMAERQL - DMA Enable Request Register */ + SPP_DMA2_DMAERQL_32B_tag DMAERQL; /* offset: 0x000C size: 32 bit */ + /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */ + SPP_DMA2_DMAEEIH_32B_tag DMAEEIH; /* offset: 0x0010 size: 32 bit */ + /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */ + SPP_DMA2_DMAEEIL_32B_tag DMAEEIL; /* offset: 0x0014 size: 32 bit */ + /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */ + SPP_DMA2_DMASERQ_8B_tag DMASERQ; /* offset: 0x0018 size: 8 bit */ + /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */ + SPP_DMA2_DMACERQ_8B_tag DMACERQ; /* offset: 0x0019 size: 8 bit */ + /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */ + SPP_DMA2_DMASEEI_8B_tag DMASEEI; /* offset: 0x001A size: 8 bit */ + /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */ + SPP_DMA2_DMACEEI_8B_tag DMACEEI; /* offset: 0x001B size: 8 bit */ + /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */ + SPP_DMA2_DMACINT_8B_tag DMACINT; /* offset: 0x001C size: 8 bit */ + /* SPP_DMA2_DMACERR - DMA Clear Error */ + SPP_DMA2_DMACERR_8B_tag DMACERR; /* offset: 0x001D size: 8 bit */ + /* SPP_DMA2_DMASSRT - DMA Set START Bit */ + SPP_DMA2_DMASSRT_8B_tag DMASSRT; /* offset: 0x001E size: 8 bit */ + /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */ + SPP_DMA2_DMACDNE_8B_tag DMACDNE; /* offset: 0x001F size: 8 bit */ + /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */ + SPP_DMA2_DMAINTH_32B_tag DMAINTH; /* offset: 0x0020 size: 32 bit */ + /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */ + SPP_DMA2_DMAINTL_32B_tag DMAINTL; /* offset: 0x0024 size: 32 bit */ + /* SPP_DMA2_DMAERRH - DMA Error Register */ + SPP_DMA2_DMAERRH_32B_tag DMAERRH; /* offset: 0x0028 size: 32 bit */ + /* SPP_DMA2_DMAERRL - DMA Error Register */ + SPP_DMA2_DMAERRL_32B_tag DMAERRL; /* offset: 0x002C size: 32 bit */ + /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */ + SPP_DMA2_DMAHRSH_32B_tag DMAHRSH; /* offset: 0x0030 size: 32 bit */ + /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */ + SPP_DMA2_DMAHRSL_32B_tag DMAHRSL; /* offset: 0x0034 size: 32 bit */ + /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */ + SPP_DMA2_DMAGPOR_32B_tag DMAGPOR; /* offset: 0x0038 size: 32 bit */ + int8_t SPP_DMA2_reserved_003C_C[196]; + union { + /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI[64]; /* offset: 0x0100 (0x0001 x 64) */ + + struct { + /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI0; /* offset: 0x0100 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI1; /* offset: 0x0101 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI2; /* offset: 0x0102 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI3; /* offset: 0x0103 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI4; /* offset: 0x0104 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI5; /* offset: 0x0105 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI6; /* offset: 0x0106 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI7; /* offset: 0x0107 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI8; /* offset: 0x0108 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI9; /* offset: 0x0109 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI10; /* offset: 0x010A size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI11; /* offset: 0x010B size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI12; /* offset: 0x010C size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI13; /* offset: 0x010D size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI14; /* offset: 0x010E size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI15; /* offset: 0x010F size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI16; /* offset: 0x0110 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI17; /* offset: 0x0111 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI18; /* offset: 0x0112 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI19; /* offset: 0x0113 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI20; /* offset: 0x0114 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI21; /* offset: 0x0115 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI22; /* offset: 0x0116 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI23; /* offset: 0x0117 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI24; /* offset: 0x0118 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI25; /* offset: 0x0119 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI26; /* offset: 0x011A size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI27; /* offset: 0x011B size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI28; /* offset: 0x011C size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI29; /* offset: 0x011D size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI30; /* offset: 0x011E size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI31; /* offset: 0x011F size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI32; /* offset: 0x0120 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI33; /* offset: 0x0121 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI34; /* offset: 0x0122 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI35; /* offset: 0x0123 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI36; /* offset: 0x0124 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI37; /* offset: 0x0125 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI38; /* offset: 0x0126 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI39; /* offset: 0x0127 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI40; /* offset: 0x0128 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI41; /* offset: 0x0129 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI42; /* offset: 0x012A size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI43; /* offset: 0x012B size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI44; /* offset: 0x012C size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI45; /* offset: 0x012D size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI46; /* offset: 0x012E size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI47; /* offset: 0x012F size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI48; /* offset: 0x0130 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI49; /* offset: 0x0131 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI50; /* offset: 0x0132 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI51; /* offset: 0x0133 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI52; /* offset: 0x0134 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI53; /* offset: 0x0135 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI54; /* offset: 0x0136 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI55; /* offset: 0x0137 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI56; /* offset: 0x0138 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI57; /* offset: 0x0139 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI58; /* offset: 0x013A size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI59; /* offset: 0x013B size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI60; /* offset: 0x013C size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI61; /* offset: 0x013D size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI62; /* offset: 0x013E size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI63; /* offset: 0x013F size: 8 bit */ + }; + + }; + int8_t SPP_DMA2_reserved_0140_C[3776]; + union { + /* Register set CHANNEL */ + SPP_DMA2_CHANNEL_tag CHANNEL[64]; /* offset: 0x1000 (0x0020 x 64) */ + + struct { + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_0; /* offset: 0x1000 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_0; /* offset: 0x1004 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_0; /* offset: 0x1008 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_0; /* offset: 0x100C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_0; /* offset: 0x1010 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_0; /* offset: 0x1014 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_0; /* offset: 0x1018 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_0; /* offset: 0x101C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_1; /* offset: 0x1020 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_1; /* offset: 0x1024 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_1; /* offset: 0x1028 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_1; /* offset: 0x102C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_1; /* offset: 0x1030 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_1; /* offset: 0x1034 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_1; /* offset: 0x1038 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_1; /* offset: 0x103C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_2; /* offset: 0x1040 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_2; /* offset: 0x1044 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_2; /* offset: 0x1048 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_2; /* offset: 0x104C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_2; /* offset: 0x1050 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_2; /* offset: 0x1054 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_2; /* offset: 0x1058 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_2; /* offset: 0x105C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_3; /* offset: 0x1060 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_3; /* offset: 0x1064 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_3; /* offset: 0x1068 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_3; /* offset: 0x106C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_3; /* offset: 0x1070 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_3; /* offset: 0x1074 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_3; /* offset: 0x1078 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_3; /* offset: 0x107C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_4; /* offset: 0x1080 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_4; /* offset: 0x1084 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_4; /* offset: 0x1088 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_4; /* offset: 0x108C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_4; /* offset: 0x1090 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_4; /* offset: 0x1094 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_4; /* offset: 0x1098 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_4; /* offset: 0x109C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_5; /* offset: 0x10A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_5; /* offset: 0x10A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_5; /* offset: 0x10A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_5; /* offset: 0x10AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_5; /* offset: 0x10B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_5; /* offset: 0x10B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_5; /* offset: 0x10B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_5; /* offset: 0x10BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_6; /* offset: 0x10C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_6; /* offset: 0x10C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_6; /* offset: 0x10C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_6; /* offset: 0x10CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_6; /* offset: 0x10D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_6; /* offset: 0x10D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_6; /* offset: 0x10D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_6; /* offset: 0x10DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_7; /* offset: 0x10E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_7; /* offset: 0x10E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_7; /* offset: 0x10E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_7; /* offset: 0x10EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_7; /* offset: 0x10F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_7; /* offset: 0x10F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_7; /* offset: 0x10F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_7; /* offset: 0x10FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_8; /* offset: 0x1100 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_8; /* offset: 0x1104 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_8; /* offset: 0x1108 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_8; /* offset: 0x110C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_8; /* offset: 0x1110 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_8; /* offset: 0x1114 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_8; /* offset: 0x1118 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_8; /* offset: 0x111C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_9; /* offset: 0x1120 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_9; /* offset: 0x1124 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_9; /* offset: 0x1128 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_9; /* offset: 0x112C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_9; /* offset: 0x1130 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_9; /* offset: 0x1134 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_9; /* offset: 0x1138 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_9; /* offset: 0x113C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_10; /* offset: 0x1140 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_10; /* offset: 0x1144 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_10; /* offset: 0x1148 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_10; /* offset: 0x114C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_10; /* offset: 0x1150 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_10; /* offset: 0x1154 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_10; /* offset: 0x1158 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_10; /* offset: 0x115C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_11; /* offset: 0x1160 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_11; /* offset: 0x1164 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_11; /* offset: 0x1168 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_11; /* offset: 0x116C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_11; /* offset: 0x1170 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_11; /* offset: 0x1174 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_11; /* offset: 0x1178 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_11; /* offset: 0x117C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_12; /* offset: 0x1180 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_12; /* offset: 0x1184 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_12; /* offset: 0x1188 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_12; /* offset: 0x118C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_12; /* offset: 0x1190 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_12; /* offset: 0x1194 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_12; /* offset: 0x1198 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_12; /* offset: 0x119C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_13; /* offset: 0x11A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_13; /* offset: 0x11A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_13; /* offset: 0x11A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_13; /* offset: 0x11AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_13; /* offset: 0x11B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_13; /* offset: 0x11B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_13; /* offset: 0x11B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_13; /* offset: 0x11BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_14; /* offset: 0x11C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_14; /* offset: 0x11C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_14; /* offset: 0x11C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_14; /* offset: 0x11CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_14; /* offset: 0x11D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_14; /* offset: 0x11D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_14; /* offset: 0x11D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_14; /* offset: 0x11DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_15; /* offset: 0x11E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_15; /* offset: 0x11E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_15; /* offset: 0x11E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_15; /* offset: 0x11EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_15; /* offset: 0x11F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_15; /* offset: 0x11F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_15; /* offset: 0x11F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_15; /* offset: 0x11FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_16; /* offset: 0x1200 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_16; /* offset: 0x1204 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_16; /* offset: 0x1208 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_16; /* offset: 0x120C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_16; /* offset: 0x1210 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_16; /* offset: 0x1214 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_16; /* offset: 0x1218 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_16; /* offset: 0x121C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_17; /* offset: 0x1220 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_17; /* offset: 0x1224 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_17; /* offset: 0x1228 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_17; /* offset: 0x122C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_17; /* offset: 0x1230 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_17; /* offset: 0x1234 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_17; /* offset: 0x1238 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_17; /* offset: 0x123C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_18; /* offset: 0x1240 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_18; /* offset: 0x1244 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_18; /* offset: 0x1248 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_18; /* offset: 0x124C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_18; /* offset: 0x1250 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_18; /* offset: 0x1254 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_18; /* offset: 0x1258 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_18; /* offset: 0x125C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_19; /* offset: 0x1260 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_19; /* offset: 0x1264 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_19; /* offset: 0x1268 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_19; /* offset: 0x126C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_19; /* offset: 0x1270 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_19; /* offset: 0x1274 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_19; /* offset: 0x1278 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_19; /* offset: 0x127C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_20; /* offset: 0x1280 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_20; /* offset: 0x1284 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_20; /* offset: 0x1288 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_20; /* offset: 0x128C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_20; /* offset: 0x1290 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_20; /* offset: 0x1294 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_20; /* offset: 0x1298 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_20; /* offset: 0x129C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_21; /* offset: 0x12A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_21; /* offset: 0x12A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_21; /* offset: 0x12A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_21; /* offset: 0x12AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_21; /* offset: 0x12B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_21; /* offset: 0x12B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_21; /* offset: 0x12B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_21; /* offset: 0x12BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_22; /* offset: 0x12C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_22; /* offset: 0x12C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_22; /* offset: 0x12C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_22; /* offset: 0x12CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_22; /* offset: 0x12D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_22; /* offset: 0x12D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_22; /* offset: 0x12D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_22; /* offset: 0x12DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_23; /* offset: 0x12E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_23; /* offset: 0x12E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_23; /* offset: 0x12E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_23; /* offset: 0x12EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_23; /* offset: 0x12F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_23; /* offset: 0x12F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_23; /* offset: 0x12F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_23; /* offset: 0x12FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_24; /* offset: 0x1300 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_24; /* offset: 0x1304 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_24; /* offset: 0x1308 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_24; /* offset: 0x130C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_24; /* offset: 0x1310 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_24; /* offset: 0x1314 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_24; /* offset: 0x1318 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_24; /* offset: 0x131C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_25; /* offset: 0x1320 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_25; /* offset: 0x1324 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_25; /* offset: 0x1328 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_25; /* offset: 0x132C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_25; /* offset: 0x1330 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_25; /* offset: 0x1334 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_25; /* offset: 0x1338 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_25; /* offset: 0x133C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_26; /* offset: 0x1340 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_26; /* offset: 0x1344 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_26; /* offset: 0x1348 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_26; /* offset: 0x134C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_26; /* offset: 0x1350 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_26; /* offset: 0x1354 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_26; /* offset: 0x1358 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_26; /* offset: 0x135C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_27; /* offset: 0x1360 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_27; /* offset: 0x1364 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_27; /* offset: 0x1368 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_27; /* offset: 0x136C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_27; /* offset: 0x1370 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_27; /* offset: 0x1374 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_27; /* offset: 0x1378 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_27; /* offset: 0x137C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_28; /* offset: 0x1380 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_28; /* offset: 0x1384 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_28; /* offset: 0x1388 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_28; /* offset: 0x138C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_28; /* offset: 0x1390 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_28; /* offset: 0x1394 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_28; /* offset: 0x1398 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_28; /* offset: 0x139C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_29; /* offset: 0x13A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_29; /* offset: 0x13A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_29; /* offset: 0x13A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_29; /* offset: 0x13AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_29; /* offset: 0x13B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_29; /* offset: 0x13B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_29; /* offset: 0x13B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_29; /* offset: 0x13BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_30; /* offset: 0x13C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_30; /* offset: 0x13C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_30; /* offset: 0x13C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_30; /* offset: 0x13CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_30; /* offset: 0x13D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_30; /* offset: 0x13D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_30; /* offset: 0x13D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_30; /* offset: 0x13DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_31; /* offset: 0x13E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_31; /* offset: 0x13E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_31; /* offset: 0x13E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_31; /* offset: 0x13EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_31; /* offset: 0x13F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_31; /* offset: 0x13F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_31; /* offset: 0x13F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_31; /* offset: 0x13FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_32; /* offset: 0x1400 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_32; /* offset: 0x1404 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_32; /* offset: 0x1408 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_32; /* offset: 0x140C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_32; /* offset: 0x1410 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_32; /* offset: 0x1414 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_32; /* offset: 0x1418 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_32; /* offset: 0x141C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_33; /* offset: 0x1420 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_33; /* offset: 0x1424 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_33; /* offset: 0x1428 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_33; /* offset: 0x142C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_33; /* offset: 0x1430 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_33; /* offset: 0x1434 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_33; /* offset: 0x1438 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_33; /* offset: 0x143C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_34; /* offset: 0x1440 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_34; /* offset: 0x1444 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_34; /* offset: 0x1448 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_34; /* offset: 0x144C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_34; /* offset: 0x1450 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_34; /* offset: 0x1454 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_34; /* offset: 0x1458 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_34; /* offset: 0x145C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_35; /* offset: 0x1460 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_35; /* offset: 0x1464 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_35; /* offset: 0x1468 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_35; /* offset: 0x146C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_35; /* offset: 0x1470 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_35; /* offset: 0x1474 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_35; /* offset: 0x1478 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_35; /* offset: 0x147C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_36; /* offset: 0x1480 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_36; /* offset: 0x1484 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_36; /* offset: 0x1488 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_36; /* offset: 0x148C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_36; /* offset: 0x1490 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_36; /* offset: 0x1494 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_36; /* offset: 0x1498 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_36; /* offset: 0x149C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_37; /* offset: 0x14A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_37; /* offset: 0x14A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_37; /* offset: 0x14A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_37; /* offset: 0x14AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_37; /* offset: 0x14B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_37; /* offset: 0x14B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_37; /* offset: 0x14B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_37; /* offset: 0x14BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_38; /* offset: 0x14C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_38; /* offset: 0x14C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_38; /* offset: 0x14C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_38; /* offset: 0x14CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_38; /* offset: 0x14D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_38; /* offset: 0x14D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_38; /* offset: 0x14D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_38; /* offset: 0x14DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_39; /* offset: 0x14E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_39; /* offset: 0x14E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_39; /* offset: 0x14E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_39; /* offset: 0x14EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_39; /* offset: 0x14F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_39; /* offset: 0x14F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_39; /* offset: 0x14F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_39; /* offset: 0x14FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_40; /* offset: 0x1500 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_40; /* offset: 0x1504 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_40; /* offset: 0x1508 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_40; /* offset: 0x150C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_40; /* offset: 0x1510 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_40; /* offset: 0x1514 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_40; /* offset: 0x1518 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_40; /* offset: 0x151C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_41; /* offset: 0x1520 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_41; /* offset: 0x1524 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_41; /* offset: 0x1528 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_41; /* offset: 0x152C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_41; /* offset: 0x1530 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_41; /* offset: 0x1534 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_41; /* offset: 0x1538 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_41; /* offset: 0x153C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_42; /* offset: 0x1540 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_42; /* offset: 0x1544 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_42; /* offset: 0x1548 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_42; /* offset: 0x154C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_42; /* offset: 0x1550 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_42; /* offset: 0x1554 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_42; /* offset: 0x1558 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_42; /* offset: 0x155C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_43; /* offset: 0x1560 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_43; /* offset: 0x1564 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_43; /* offset: 0x1568 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_43; /* offset: 0x156C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_43; /* offset: 0x1570 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_43; /* offset: 0x1574 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_43; /* offset: 0x1578 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_43; /* offset: 0x157C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_44; /* offset: 0x1580 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_44; /* offset: 0x1584 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_44; /* offset: 0x1588 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_44; /* offset: 0x158C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_44; /* offset: 0x1590 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_44; /* offset: 0x1594 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_44; /* offset: 0x1598 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_44; /* offset: 0x159C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_45; /* offset: 0x15A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_45; /* offset: 0x15A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_45; /* offset: 0x15A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_45; /* offset: 0x15AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_45; /* offset: 0x15B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_45; /* offset: 0x15B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_45; /* offset: 0x15B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_45; /* offset: 0x15BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_46; /* offset: 0x15C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_46; /* offset: 0x15C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_46; /* offset: 0x15C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_46; /* offset: 0x15CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_46; /* offset: 0x15D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_46; /* offset: 0x15D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_46; /* offset: 0x15D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_46; /* offset: 0x15DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_47; /* offset: 0x15E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_47; /* offset: 0x15E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_47; /* offset: 0x15E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_47; /* offset: 0x15EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_47; /* offset: 0x15F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_47; /* offset: 0x15F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_47; /* offset: 0x15F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_47; /* offset: 0x15FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_48; /* offset: 0x1600 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_48; /* offset: 0x1604 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_48; /* offset: 0x1608 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_48; /* offset: 0x160C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_48; /* offset: 0x1610 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_48; /* offset: 0x1614 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_48; /* offset: 0x1618 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_48; /* offset: 0x161C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_49; /* offset: 0x1620 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_49; /* offset: 0x1624 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_49; /* offset: 0x1628 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_49; /* offset: 0x162C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_49; /* offset: 0x1630 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_49; /* offset: 0x1634 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_49; /* offset: 0x1638 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_49; /* offset: 0x163C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_50; /* offset: 0x1640 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_50; /* offset: 0x1644 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_50; /* offset: 0x1648 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_50; /* offset: 0x164C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_50; /* offset: 0x1650 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_50; /* offset: 0x1654 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_50; /* offset: 0x1658 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_50; /* offset: 0x165C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_51; /* offset: 0x1660 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_51; /* offset: 0x1664 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_51; /* offset: 0x1668 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_51; /* offset: 0x166C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_51; /* offset: 0x1670 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_51; /* offset: 0x1674 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_51; /* offset: 0x1678 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_51; /* offset: 0x167C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_52; /* offset: 0x1680 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_52; /* offset: 0x1684 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_52; /* offset: 0x1688 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_52; /* offset: 0x168C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_52; /* offset: 0x1690 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_52; /* offset: 0x1694 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_52; /* offset: 0x1698 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_52; /* offset: 0x169C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_53; /* offset: 0x16A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_53; /* offset: 0x16A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_53; /* offset: 0x16A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_53; /* offset: 0x16AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_53; /* offset: 0x16B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_53; /* offset: 0x16B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_53; /* offset: 0x16B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_53; /* offset: 0x16BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_54; /* offset: 0x16C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_54; /* offset: 0x16C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_54; /* offset: 0x16C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_54; /* offset: 0x16CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_54; /* offset: 0x16D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_54; /* offset: 0x16D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_54; /* offset: 0x16D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_54; /* offset: 0x16DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_55; /* offset: 0x16E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_55; /* offset: 0x16E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_55; /* offset: 0x16E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_55; /* offset: 0x16EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_55; /* offset: 0x16F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_55; /* offset: 0x16F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_55; /* offset: 0x16F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_55; /* offset: 0x16FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_56; /* offset: 0x1700 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_56; /* offset: 0x1704 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_56; /* offset: 0x1708 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_56; /* offset: 0x170C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_56; /* offset: 0x1710 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_56; /* offset: 0x1714 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_56; /* offset: 0x1718 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_56; /* offset: 0x171C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_57; /* offset: 0x1720 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_57; /* offset: 0x1724 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_57; /* offset: 0x1728 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_57; /* offset: 0x172C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_57; /* offset: 0x1730 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_57; /* offset: 0x1734 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_57; /* offset: 0x1738 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_57; /* offset: 0x173C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_58; /* offset: 0x1740 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_58; /* offset: 0x1744 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_58; /* offset: 0x1748 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_58; /* offset: 0x174C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_58; /* offset: 0x1750 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_58; /* offset: 0x1754 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_58; /* offset: 0x1758 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_58; /* offset: 0x175C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_59; /* offset: 0x1760 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_59; /* offset: 0x1764 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_59; /* offset: 0x1768 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_59; /* offset: 0x176C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_59; /* offset: 0x1770 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_59; /* offset: 0x1774 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_59; /* offset: 0x1778 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_59; /* offset: 0x177C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_60; /* offset: 0x1780 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_60; /* offset: 0x1784 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_60; /* offset: 0x1788 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_60; /* offset: 0x178C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_60; /* offset: 0x1790 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_60; /* offset: 0x1794 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_60; /* offset: 0x1798 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_60; /* offset: 0x179C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_61; /* offset: 0x17A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_61; /* offset: 0x17A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_61; /* offset: 0x17A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_61; /* offset: 0x17AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_61; /* offset: 0x17B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_61; /* offset: 0x17B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_61; /* offset: 0x17B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_61; /* offset: 0x17BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_62; /* offset: 0x17C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_62; /* offset: 0x17C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_62; /* offset: 0x17C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_62; /* offset: 0x17CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_62; /* offset: 0x17D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_62; /* offset: 0x17D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_62; /* offset: 0x17D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_62; /* offset: 0x17DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_63; /* offset: 0x17E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_63; /* offset: 0x17E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_63; /* offset: 0x17E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_63; /* offset: 0x17EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_63; /* offset: 0x17F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_63; /* offset: 0x17F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_63; /* offset: 0x17F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_63; /* offset: 0x17FC size: 32 bit */ + }; + + }; + } SPP_DMA2_tag; + + +#define SPP_DMA2 (*(volatile SPP_DMA2_tag *) 0xFFF44000UL) + + + +/****************************************************************/ +/* */ +/* Module: INTC */ +/* */ +/****************************************************************/ + + typedef union { /* BCR - Block Configuration Register */ + uint32_t R; + struct { + uint32_t:18; + uint32_t VTES_PRC1:1; /* Vector Table Entry Size - Processor 1 */ + uint32_t:4; + uint32_t HVEN_PRC1:1; /* Hardware Vector Enable - Processor 1 */ + uint32_t:2; +#ifndef USE_FIELD_ALIASES_INTC + uint32_t VTES_PRC0:1; /* Vector Table Entry Size - Processor 0 */ +#else + uint32_t VTES:1; /* deprecated name - please avoid */ +#endif + uint32_t:4; +#ifndef USE_FIELD_ALIASES_INTC + uint32_t HVEN_PRC0:1; /* Hardware Vector Enable - Processor 0 */ +#else + uint32_t HVEN:1; /* deprecated name - please avoid */ +#endif + } B; + } INTC_BCR_32B_tag; + + typedef union { /* CPR - Current Priority Register - Processor 0 */ + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; /* Priority Bits */ + } B; + } INTC_CPR_PRC0_32B_tag; + + typedef union { /* CPR - Current Priority Register - Processor 1 */ + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; /* Priority Bits */ + } B; + } INTC_CPR_PRC1_32B_tag; + + typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 0 */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_INTC + uint32_t VTBA_PRC0:21; /* Vector Table Base Address - Processor 0 */ +#else + uint32_t VTBA:21; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_INTC + uint32_t INTEC_PRC0:9; /* Interrupt Vector - Processor 0 */ +#else + uint32_t INTVEC:9; /* deprecated name - please avoid */ +#endif + uint32_t:2; + } B; + } INTC_IACKR_PRC0_32B_tag; + + typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 1 */ + uint32_t R; + struct { + uint32_t VTBA_PRC1:21; /* Vector Table Base Address - Processor 1 */ + uint32_t INTEC_PRC1:9; /* Interrupt Vector - Processor 1 */ + uint32_t:2; + } B; + } INTC_IACKR_PRC1_32B_tag; + + typedef union { /* EOIR- End of Interrupt Register - Processor 0 */ + uint32_t R; + } INTC_EOIR_PRC0_32B_tag; + + typedef union { /* EOIR- End of Interrupt Register - Processor 1 */ + uint32_t R; + } INTC_EOIR_PRC1_32B_tag; + + + /* Register layout for all registers SSCIR... */ + + typedef union { /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ + uint8_t R; + struct { + uint8_t:6; + uint8_t SET:1; /* Set Flag bit */ + uint8_t CLR:1; /* Clear Flag bit */ + } B; + } INTC_SSCIR_8B_tag; + + typedef union { /* SSCIR0_3 - Software Set/Clear Interrupt Registers */ + uint32_t R; + struct { + uint32_t:6; + uint32_t SET0:1; /* Set Flag 0 bit */ + uint32_t CLR0:1; /* Clear Flag 0 bit */ + uint32_t:6; + uint32_t SET1:1; /* Set Flag 1 bit */ + uint32_t CLR1:1; /* Clear Flag 1 bit */ + uint32_t:6; + uint32_t SET2:1; /* Set Flag 2 bit */ + uint32_t CLR2:1; /* Clear Flag 2 bit */ + uint32_t:6; + uint32_t SET3:1; /* Set Flag 3 bit */ + uint32_t CLR3:1; /* Clear Flag 3 bit */ + } B; + } INTC_SSCIR0_3_32B_tag; + + typedef union { /* SSCIR4_7 - Software Set/Clear Interrupt Registers */ + uint32_t R; + struct { + uint32_t:6; + uint32_t SET4:1; /* Set Flag 4 bit */ + uint32_t CLR4:1; /* Clear Flag 4 bit */ + uint32_t:6; + uint32_t SET5:1; /* Set Flag 5 bit */ + uint32_t CLR5:1; /* Clear Flag 5 bit */ + uint32_t:6; + uint32_t SET6:1; /* Set Flag 6 bit */ + uint32_t CLR6:1; /* Clear Flag 6 bit */ + uint32_t:6; + uint32_t SET7:1; /* Set Flag 7 bit */ + uint32_t CLR7:1; /* Clear Flag 7 bit */ + } B; + } INTC_SSCIR4_7_32B_tag; + + + /* Register layout for all registers PSR... */ + + typedef union { /* PSR0-511 - Priority Select Registers */ + uint8_t R; + struct { + uint8_t PRC_SEL:2; /* Processor Select */ + uint8_t:2; + uint8_t PRI:4; /* Priority Select */ + } B; + } INTC_PSR_8B_tag; + + + /* Register layout for all registers PSR... */ + + typedef union { /* PSR0_3 - 508_511 - Priority Select Registers */ + uint32_t R; + struct { + uint32_t PRC_SEL0:2; /* Processor Select - Entry 0 */ + uint32_t:2; + uint32_t PRI0:4; /* Priority Select - Entry 0 */ + uint32_t PRC_SEL1:2; /* Processor Select - Entry 1 */ + uint32_t:2; + uint32_t PRI1:4; /* Priority Select - Entry 1 */ + uint32_t PRC_SEL2:2; /* Processor Select - Entry 2 */ + uint32_t:2; + uint32_t PRI2:4; /* Priority Select - Entry 2 */ + uint32_t PRC_SEL3:2; /* Processor Select - Entry 3 */ + uint32_t:2; + uint32_t PRI3:4; /* Priority Select - Entry 3 */ + } B; + } INTC_PSR_32B_tag; + + + + typedef struct INTC_struct_tag { /* start of INTC_tag */ + union { + INTC_BCR_32B_tag MCR; /* deprecated - please avoid */ + + /* BCR - Block Configuration Register */ + INTC_BCR_32B_tag BCR; /* offset: 0x0000 size: 32 bit */ + + }; + int8_t INTC_reserved_0004_C[4]; + union { + /* CPR - Current Priority Register - Processor 0 */ + INTC_CPR_PRC0_32B_tag CPR_PRC0; /* offset: 0x0008 size: 32 bit */ + + INTC_CPR_PRC0_32B_tag CPR; /* deprecated - please avoid */ + + }; + /* CPR - Current Priority Register - Processor 1 */ + INTC_CPR_PRC1_32B_tag CPR_PRC1; /* offset: 0x000C size: 32 bit */ + union { + /* IACKR- Interrupt Acknowledge Register - Processor 0 */ + INTC_IACKR_PRC0_32B_tag IACKR_PRC0; /* offset: 0x0010 size: 32 bit */ + + INTC_IACKR_PRC0_32B_tag IACKR; /* deprecated - please avoid */ + + }; + /* IACKR- Interrupt Acknowledge Register - Processor 1 */ + INTC_IACKR_PRC1_32B_tag IACKR_PRC1; /* offset: 0x0014 size: 32 bit */ + union { + /* EOIR- End of Interrupt Register - Processor 0 */ + INTC_EOIR_PRC0_32B_tag EOIR_PRC0; /* offset: 0x0018 size: 32 bit */ + + INTC_EOIR_PRC0_32B_tag EOIR; /* deprecated - please avoid */ + + }; + /* EOIR- End of Interrupt Register - Processor 1 */ + INTC_EOIR_PRC1_32B_tag EOIR_PRC1; /* offset: 0x001C size: 32 bit */ + union { + /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ + INTC_SSCIR_8B_tag SSCIR[8]; /* offset: 0x0020 (0x0001 x 8) */ + + struct { + /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ + INTC_SSCIR_8B_tag SSCIR0; /* offset: 0x0020 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR1; /* offset: 0x0021 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR2; /* offset: 0x0022 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR3; /* offset: 0x0023 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR4; /* offset: 0x0024 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR5; /* offset: 0x0025 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR6; /* offset: 0x0026 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR7; /* offset: 0x0027 size: 8 bit */ + }; + + struct { + /* SSCIR0_3 - Software Set/Clear Interrupt Registers */ + INTC_SSCIR0_3_32B_tag SSCIR0_3; /* offset: 0x0020 size: 32 bit */ + /* SSCIR4_7 - Software Set/Clear Interrupt Registers */ + INTC_SSCIR4_7_32B_tag SSCIR4_7; /* offset: 0x0024 size: 32 bit */ + }; + + }; + int8_t INTC_reserved_0028_C[24]; + union { + /* PSR0_3 - 508_511 - Priority Select Registers */ + INTC_PSR_32B_tag PSR_32B[128]; /* offset: 0x0040 (0x0004 x 128) */ + + /* PSR0-511 - Priority Select Registers */ + INTC_PSR_8B_tag PSR[512]; /* offset: 0x0040 (0x0001 x 512) */ + + struct { + /* PSR0_3 - 508_511 - Priority Select Registers */ + INTC_PSR_32B_tag PSR0_3; /* offset: 0x0040 size: 32 bit */ + INTC_PSR_32B_tag PSR4_7; /* offset: 0x0044 size: 32 bit */ + INTC_PSR_32B_tag PSR8_11; /* offset: 0x0048 size: 32 bit */ + INTC_PSR_32B_tag PSR12_15; /* offset: 0x004C size: 32 bit */ + INTC_PSR_32B_tag PSR16_19; /* offset: 0x0050 size: 32 bit */ + INTC_PSR_32B_tag PSR20_23; /* offset: 0x0054 size: 32 bit */ + INTC_PSR_32B_tag PSR24_27; /* offset: 0x0058 size: 32 bit */ + INTC_PSR_32B_tag PSR28_31; /* offset: 0x005C size: 32 bit */ + INTC_PSR_32B_tag PSR32_35; /* offset: 0x0060 size: 32 bit */ + INTC_PSR_32B_tag PSR36_39; /* offset: 0x0064 size: 32 bit */ + INTC_PSR_32B_tag PSR40_43; /* offset: 0x0068 size: 32 bit */ + INTC_PSR_32B_tag PSR44_47; /* offset: 0x006C size: 32 bit */ + INTC_PSR_32B_tag PSR48_51; /* offset: 0x0070 size: 32 bit */ + INTC_PSR_32B_tag PSR52_55; /* offset: 0x0074 size: 32 bit */ + INTC_PSR_32B_tag PSR56_59; /* offset: 0x0078 size: 32 bit */ + INTC_PSR_32B_tag PSR60_63; /* offset: 0x007C size: 32 bit */ + INTC_PSR_32B_tag PSR64_67; /* offset: 0x0080 size: 32 bit */ + INTC_PSR_32B_tag PSR68_71; /* offset: 0x0084 size: 32 bit */ + INTC_PSR_32B_tag PSR72_75; /* offset: 0x0088 size: 32 bit */ + INTC_PSR_32B_tag PSR76_79; /* offset: 0x008C size: 32 bit */ + INTC_PSR_32B_tag PSR80_83; /* offset: 0x0090 size: 32 bit */ + INTC_PSR_32B_tag PSR84_87; /* offset: 0x0094 size: 32 bit */ + INTC_PSR_32B_tag PSR88_91; /* offset: 0x0098 size: 32 bit */ + INTC_PSR_32B_tag PSR92_95; /* offset: 0x009C size: 32 bit */ + INTC_PSR_32B_tag PSR96_99; /* offset: 0x00A0 size: 32 bit */ + INTC_PSR_32B_tag PSR100_103; /* offset: 0x00A4 size: 32 bit */ + INTC_PSR_32B_tag PSR104_107; /* offset: 0x00A8 size: 32 bit */ + INTC_PSR_32B_tag PSR108_111; /* offset: 0x00AC size: 32 bit */ + INTC_PSR_32B_tag PSR112_115; /* offset: 0x00B0 size: 32 bit */ + INTC_PSR_32B_tag PSR116_119; /* offset: 0x00B4 size: 32 bit */ + INTC_PSR_32B_tag PSR120_123; /* offset: 0x00B8 size: 32 bit */ + INTC_PSR_32B_tag PSR124_127; /* offset: 0x00BC size: 32 bit */ + INTC_PSR_32B_tag PSR128_131; /* offset: 0x00C0 size: 32 bit */ + INTC_PSR_32B_tag PSR132_135; /* offset: 0x00C4 size: 32 bit */ + INTC_PSR_32B_tag PSR136_139; /* offset: 0x00C8 size: 32 bit */ + INTC_PSR_32B_tag PSR140_143; /* offset: 0x00CC size: 32 bit */ + INTC_PSR_32B_tag PSR144_147; /* offset: 0x00D0 size: 32 bit */ + INTC_PSR_32B_tag PSR148_151; /* offset: 0x00D4 size: 32 bit */ + INTC_PSR_32B_tag PSR152_155; /* offset: 0x00D8 size: 32 bit */ + INTC_PSR_32B_tag PSR156_159; /* offset: 0x00DC size: 32 bit */ + INTC_PSR_32B_tag PSR160_163; /* offset: 0x00E0 size: 32 bit */ + INTC_PSR_32B_tag PSR164_167; /* offset: 0x00E4 size: 32 bit */ + INTC_PSR_32B_tag PSR168_171; /* offset: 0x00E8 size: 32 bit */ + INTC_PSR_32B_tag PSR172_175; /* offset: 0x00EC size: 32 bit */ + INTC_PSR_32B_tag PSR176_179; /* offset: 0x00F0 size: 32 bit */ + INTC_PSR_32B_tag PSR180_183; /* offset: 0x00F4 size: 32 bit */ + INTC_PSR_32B_tag PSR184_187; /* offset: 0x00F8 size: 32 bit */ + INTC_PSR_32B_tag PSR188_191; /* offset: 0x00FC size: 32 bit */ + INTC_PSR_32B_tag PSR192_195; /* offset: 0x0100 size: 32 bit */ + INTC_PSR_32B_tag PSR196_199; /* offset: 0x0104 size: 32 bit */ + INTC_PSR_32B_tag PSR200_203; /* offset: 0x0108 size: 32 bit */ + INTC_PSR_32B_tag PSR204_207; /* offset: 0x010C size: 32 bit */ + INTC_PSR_32B_tag PSR208_211; /* offset: 0x0110 size: 32 bit */ + INTC_PSR_32B_tag PSR212_215; /* offset: 0x0114 size: 32 bit */ + INTC_PSR_32B_tag PSR216_219; /* offset: 0x0118 size: 32 bit */ + INTC_PSR_32B_tag PSR220_223; /* offset: 0x011C size: 32 bit */ + INTC_PSR_32B_tag PSR224_227; /* offset: 0x0120 size: 32 bit */ + INTC_PSR_32B_tag PSR228_231; /* offset: 0x0124 size: 32 bit */ + INTC_PSR_32B_tag PSR232_235; /* offset: 0x0128 size: 32 bit */ + INTC_PSR_32B_tag PSR236_239; /* offset: 0x012C size: 32 bit */ + INTC_PSR_32B_tag PSR240_243; /* offset: 0x0130 size: 32 bit */ + INTC_PSR_32B_tag PSR244_247; /* offset: 0x0134 size: 32 bit */ + INTC_PSR_32B_tag PSR248_251; /* offset: 0x0138 size: 32 bit */ + INTC_PSR_32B_tag PSR252_255; /* offset: 0x013C size: 32 bit */ + INTC_PSR_32B_tag PSR256_259; /* offset: 0x0140 size: 32 bit */ + INTC_PSR_32B_tag PSR260_263; /* offset: 0x0144 size: 32 bit */ + INTC_PSR_32B_tag PSR264_267; /* offset: 0x0148 size: 32 bit */ + INTC_PSR_32B_tag PSR268_271; /* offset: 0x014C size: 32 bit */ + INTC_PSR_32B_tag PSR272_275; /* offset: 0x0150 size: 32 bit */ + INTC_PSR_32B_tag PSR276_279; /* offset: 0x0154 size: 32 bit */ + INTC_PSR_32B_tag PSR280_283; /* offset: 0x0158 size: 32 bit */ + INTC_PSR_32B_tag PSR284_287; /* offset: 0x015C size: 32 bit */ + INTC_PSR_32B_tag PSR288_291; /* offset: 0x0160 size: 32 bit */ + INTC_PSR_32B_tag PSR292_295; /* offset: 0x0164 size: 32 bit */ + INTC_PSR_32B_tag PSR296_299; /* offset: 0x0168 size: 32 bit */ + INTC_PSR_32B_tag PSR300_303; /* offset: 0x016C size: 32 bit */ + INTC_PSR_32B_tag PSR304_307; /* offset: 0x0170 size: 32 bit */ + INTC_PSR_32B_tag PSR308_311; /* offset: 0x0174 size: 32 bit */ + INTC_PSR_32B_tag PSR312_315; /* offset: 0x0178 size: 32 bit */ + INTC_PSR_32B_tag PSR316_319; /* offset: 0x017C size: 32 bit */ + INTC_PSR_32B_tag PSR320_323; /* offset: 0x0180 size: 32 bit */ + INTC_PSR_32B_tag PSR324_327; /* offset: 0x0184 size: 32 bit */ + INTC_PSR_32B_tag PSR328_331; /* offset: 0x0188 size: 32 bit */ + INTC_PSR_32B_tag PSR332_335; /* offset: 0x018C size: 32 bit */ + INTC_PSR_32B_tag PSR336_339; /* offset: 0x0190 size: 32 bit */ + INTC_PSR_32B_tag PSR340_343; /* offset: 0x0194 size: 32 bit */ + INTC_PSR_32B_tag PSR344_347; /* offset: 0x0198 size: 32 bit */ + INTC_PSR_32B_tag PSR348_351; /* offset: 0x019C size: 32 bit */ + INTC_PSR_32B_tag PSR352_355; /* offset: 0x01A0 size: 32 bit */ + INTC_PSR_32B_tag PSR356_359; /* offset: 0x01A4 size: 32 bit */ + INTC_PSR_32B_tag PSR360_363; /* offset: 0x01A8 size: 32 bit */ + INTC_PSR_32B_tag PSR364_367; /* offset: 0x01AC size: 32 bit */ + INTC_PSR_32B_tag PSR368_371; /* offset: 0x01B0 size: 32 bit */ + INTC_PSR_32B_tag PSR372_375; /* offset: 0x01B4 size: 32 bit */ + INTC_PSR_32B_tag PSR376_379; /* offset: 0x01B8 size: 32 bit */ + INTC_PSR_32B_tag PSR380_383; /* offset: 0x01BC size: 32 bit */ + INTC_PSR_32B_tag PSR384_387; /* offset: 0x01C0 size: 32 bit */ + INTC_PSR_32B_tag PSR388_391; /* offset: 0x01C4 size: 32 bit */ + INTC_PSR_32B_tag PSR392_395; /* offset: 0x01C8 size: 32 bit */ + INTC_PSR_32B_tag PSR396_399; /* offset: 0x01CC size: 32 bit */ + INTC_PSR_32B_tag PSR400_403; /* offset: 0x01D0 size: 32 bit */ + INTC_PSR_32B_tag PSR404_407; /* offset: 0x01D4 size: 32 bit */ + INTC_PSR_32B_tag PSR408_411; /* offset: 0x01D8 size: 32 bit */ + INTC_PSR_32B_tag PSR412_415; /* offset: 0x01DC size: 32 bit */ + INTC_PSR_32B_tag PSR416_419; /* offset: 0x01E0 size: 32 bit */ + INTC_PSR_32B_tag PSR420_423; /* offset: 0x01E4 size: 32 bit */ + INTC_PSR_32B_tag PSR424_427; /* offset: 0x01E8 size: 32 bit */ + INTC_PSR_32B_tag PSR428_431; /* offset: 0x01EC size: 32 bit */ + INTC_PSR_32B_tag PSR432_435; /* offset: 0x01F0 size: 32 bit */ + INTC_PSR_32B_tag PSR436_439; /* offset: 0x01F4 size: 32 bit */ + INTC_PSR_32B_tag PSR440_443; /* offset: 0x01F8 size: 32 bit */ + INTC_PSR_32B_tag PSR444_447; /* offset: 0x01FC size: 32 bit */ + INTC_PSR_32B_tag PSR448_451; /* offset: 0x0200 size: 32 bit */ + INTC_PSR_32B_tag PSR452_455; /* offset: 0x0204 size: 32 bit */ + INTC_PSR_32B_tag PSR456_459; /* offset: 0x0208 size: 32 bit */ + INTC_PSR_32B_tag PSR460_463; /* offset: 0x020C size: 32 bit */ + INTC_PSR_32B_tag PSR464_467; /* offset: 0x0210 size: 32 bit */ + INTC_PSR_32B_tag PSR468_471; /* offset: 0x0214 size: 32 bit */ + INTC_PSR_32B_tag PSR472_475; /* offset: 0x0218 size: 32 bit */ + INTC_PSR_32B_tag PSR476_479; /* offset: 0x021C size: 32 bit */ + INTC_PSR_32B_tag PSR480_483; /* offset: 0x0220 size: 32 bit */ + INTC_PSR_32B_tag PSR484_487; /* offset: 0x0224 size: 32 bit */ + INTC_PSR_32B_tag PSR488_491; /* offset: 0x0228 size: 32 bit */ + INTC_PSR_32B_tag PSR492_495; /* offset: 0x022C size: 32 bit */ + INTC_PSR_32B_tag PSR496_499; /* offset: 0x0230 size: 32 bit */ + INTC_PSR_32B_tag PSR500_503; /* offset: 0x0234 size: 32 bit */ + INTC_PSR_32B_tag PSR504_507; /* offset: 0x0238 size: 32 bit */ + INTC_PSR_32B_tag PSR508_511; /* offset: 0x023C size: 32 bit */ + }; + + struct { + /* PSR0-511 - Priority Select Registers */ + INTC_PSR_8B_tag PSR0; /* offset: 0x0040 size: 8 bit */ + INTC_PSR_8B_tag PSR1; /* offset: 0x0041 size: 8 bit */ + INTC_PSR_8B_tag PSR2; /* offset: 0x0042 size: 8 bit */ + INTC_PSR_8B_tag PSR3; /* offset: 0x0043 size: 8 bit */ + INTC_PSR_8B_tag PSR4; /* offset: 0x0044 size: 8 bit */ + INTC_PSR_8B_tag PSR5; /* offset: 0x0045 size: 8 bit */ + INTC_PSR_8B_tag PSR6; /* offset: 0x0046 size: 8 bit */ + INTC_PSR_8B_tag PSR7; /* offset: 0x0047 size: 8 bit */ + INTC_PSR_8B_tag PSR8; /* offset: 0x0048 size: 8 bit */ + INTC_PSR_8B_tag PSR9; /* offset: 0x0049 size: 8 bit */ + INTC_PSR_8B_tag PSR10; /* offset: 0x004A size: 8 bit */ + INTC_PSR_8B_tag PSR11; /* offset: 0x004B size: 8 bit */ + INTC_PSR_8B_tag PSR12; /* offset: 0x004C size: 8 bit */ + INTC_PSR_8B_tag PSR13; /* offset: 0x004D size: 8 bit */ + INTC_PSR_8B_tag PSR14; /* offset: 0x004E size: 8 bit */ + INTC_PSR_8B_tag PSR15; /* offset: 0x004F size: 8 bit */ + INTC_PSR_8B_tag PSR16; /* offset: 0x0050 size: 8 bit */ + INTC_PSR_8B_tag PSR17; /* offset: 0x0051 size: 8 bit */ + INTC_PSR_8B_tag PSR18; /* offset: 0x0052 size: 8 bit */ + INTC_PSR_8B_tag PSR19; /* offset: 0x0053 size: 8 bit */ + INTC_PSR_8B_tag PSR20; /* offset: 0x0054 size: 8 bit */ + INTC_PSR_8B_tag PSR21; /* offset: 0x0055 size: 8 bit */ + INTC_PSR_8B_tag PSR22; /* offset: 0x0056 size: 8 bit */ + INTC_PSR_8B_tag PSR23; /* offset: 0x0057 size: 8 bit */ + INTC_PSR_8B_tag PSR24; /* offset: 0x0058 size: 8 bit */ + INTC_PSR_8B_tag PSR25; /* offset: 0x0059 size: 8 bit */ + INTC_PSR_8B_tag PSR26; /* offset: 0x005A size: 8 bit */ + INTC_PSR_8B_tag PSR27; /* offset: 0x005B size: 8 bit */ + INTC_PSR_8B_tag PSR28; /* offset: 0x005C size: 8 bit */ + INTC_PSR_8B_tag PSR29; /* offset: 0x005D size: 8 bit */ + INTC_PSR_8B_tag PSR30; /* offset: 0x005E size: 8 bit */ + INTC_PSR_8B_tag PSR31; /* offset: 0x005F size: 8 bit */ + INTC_PSR_8B_tag PSR32; /* offset: 0x0060 size: 8 bit */ + INTC_PSR_8B_tag PSR33; /* offset: 0x0061 size: 8 bit */ + INTC_PSR_8B_tag PSR34; /* offset: 0x0062 size: 8 bit */ + INTC_PSR_8B_tag PSR35; /* offset: 0x0063 size: 8 bit */ + INTC_PSR_8B_tag PSR36; /* offset: 0x0064 size: 8 bit */ + INTC_PSR_8B_tag PSR37; /* offset: 0x0065 size: 8 bit */ + INTC_PSR_8B_tag PSR38; /* offset: 0x0066 size: 8 bit */ + INTC_PSR_8B_tag PSR39; /* offset: 0x0067 size: 8 bit */ + INTC_PSR_8B_tag PSR40; /* offset: 0x0068 size: 8 bit */ + INTC_PSR_8B_tag PSR41; /* offset: 0x0069 size: 8 bit */ + INTC_PSR_8B_tag PSR42; /* offset: 0x006A size: 8 bit */ + INTC_PSR_8B_tag PSR43; /* offset: 0x006B size: 8 bit */ + INTC_PSR_8B_tag PSR44; /* offset: 0x006C size: 8 bit */ + INTC_PSR_8B_tag PSR45; /* offset: 0x006D size: 8 bit */ + INTC_PSR_8B_tag PSR46; /* offset: 0x006E size: 8 bit */ + INTC_PSR_8B_tag PSR47; /* offset: 0x006F size: 8 bit */ + INTC_PSR_8B_tag PSR48; /* offset: 0x0070 size: 8 bit */ + INTC_PSR_8B_tag PSR49; /* offset: 0x0071 size: 8 bit */ + INTC_PSR_8B_tag PSR50; /* offset: 0x0072 size: 8 bit */ + INTC_PSR_8B_tag PSR51; /* offset: 0x0073 size: 8 bit */ + INTC_PSR_8B_tag PSR52; /* offset: 0x0074 size: 8 bit */ + INTC_PSR_8B_tag PSR53; /* offset: 0x0075 size: 8 bit */ + INTC_PSR_8B_tag PSR54; /* offset: 0x0076 size: 8 bit */ + INTC_PSR_8B_tag PSR55; /* offset: 0x0077 size: 8 bit */ + INTC_PSR_8B_tag PSR56; /* offset: 0x0078 size: 8 bit */ + INTC_PSR_8B_tag PSR57; /* offset: 0x0079 size: 8 bit */ + INTC_PSR_8B_tag PSR58; /* offset: 0x007A size: 8 bit */ + INTC_PSR_8B_tag PSR59; /* offset: 0x007B size: 8 bit */ + INTC_PSR_8B_tag PSR60; /* offset: 0x007C size: 8 bit */ + INTC_PSR_8B_tag PSR61; /* offset: 0x007D size: 8 bit */ + INTC_PSR_8B_tag PSR62; /* offset: 0x007E size: 8 bit */ + INTC_PSR_8B_tag PSR63; /* offset: 0x007F size: 8 bit */ + INTC_PSR_8B_tag PSR64; /* offset: 0x0080 size: 8 bit */ + INTC_PSR_8B_tag PSR65; /* offset: 0x0081 size: 8 bit */ + INTC_PSR_8B_tag PSR66; /* offset: 0x0082 size: 8 bit */ + INTC_PSR_8B_tag PSR67; /* offset: 0x0083 size: 8 bit */ + INTC_PSR_8B_tag PSR68; /* offset: 0x0084 size: 8 bit */ + INTC_PSR_8B_tag PSR69; /* offset: 0x0085 size: 8 bit */ + INTC_PSR_8B_tag PSR70; /* offset: 0x0086 size: 8 bit */ + INTC_PSR_8B_tag PSR71; /* offset: 0x0087 size: 8 bit */ + INTC_PSR_8B_tag PSR72; /* offset: 0x0088 size: 8 bit */ + INTC_PSR_8B_tag PSR73; /* offset: 0x0089 size: 8 bit */ + INTC_PSR_8B_tag PSR74; /* offset: 0x008A size: 8 bit */ + INTC_PSR_8B_tag PSR75; /* offset: 0x008B size: 8 bit */ + INTC_PSR_8B_tag PSR76; /* offset: 0x008C size: 8 bit */ + INTC_PSR_8B_tag PSR77; /* offset: 0x008D size: 8 bit */ + INTC_PSR_8B_tag PSR78; /* offset: 0x008E size: 8 bit */ + INTC_PSR_8B_tag PSR79; /* offset: 0x008F size: 8 bit */ + INTC_PSR_8B_tag PSR80; /* offset: 0x0090 size: 8 bit */ + INTC_PSR_8B_tag PSR81; /* offset: 0x0091 size: 8 bit */ + INTC_PSR_8B_tag PSR82; /* offset: 0x0092 size: 8 bit */ + INTC_PSR_8B_tag PSR83; /* offset: 0x0093 size: 8 bit */ + INTC_PSR_8B_tag PSR84; /* offset: 0x0094 size: 8 bit */ + INTC_PSR_8B_tag PSR85; /* offset: 0x0095 size: 8 bit */ + INTC_PSR_8B_tag PSR86; /* offset: 0x0096 size: 8 bit */ + INTC_PSR_8B_tag PSR87; /* offset: 0x0097 size: 8 bit */ + INTC_PSR_8B_tag PSR88; /* offset: 0x0098 size: 8 bit */ + INTC_PSR_8B_tag PSR89; /* offset: 0x0099 size: 8 bit */ + INTC_PSR_8B_tag PSR90; /* offset: 0x009A size: 8 bit */ + INTC_PSR_8B_tag PSR91; /* offset: 0x009B size: 8 bit */ + INTC_PSR_8B_tag PSR92; /* offset: 0x009C size: 8 bit */ + INTC_PSR_8B_tag PSR93; /* offset: 0x009D size: 8 bit */ + INTC_PSR_8B_tag PSR94; /* offset: 0x009E size: 8 bit */ + INTC_PSR_8B_tag PSR95; /* offset: 0x009F size: 8 bit */ + INTC_PSR_8B_tag PSR96; /* offset: 0x00A0 size: 8 bit */ + INTC_PSR_8B_tag PSR97; /* offset: 0x00A1 size: 8 bit */ + INTC_PSR_8B_tag PSR98; /* offset: 0x00A2 size: 8 bit */ + INTC_PSR_8B_tag PSR99; /* offset: 0x00A3 size: 8 bit */ + INTC_PSR_8B_tag PSR100; /* offset: 0x00A4 size: 8 bit */ + INTC_PSR_8B_tag PSR101; /* offset: 0x00A5 size: 8 bit */ + INTC_PSR_8B_tag PSR102; /* offset: 0x00A6 size: 8 bit */ + INTC_PSR_8B_tag PSR103; /* offset: 0x00A7 size: 8 bit */ + INTC_PSR_8B_tag PSR104; /* offset: 0x00A8 size: 8 bit */ + INTC_PSR_8B_tag PSR105; /* offset: 0x00A9 size: 8 bit */ + INTC_PSR_8B_tag PSR106; /* offset: 0x00AA size: 8 bit */ + INTC_PSR_8B_tag PSR107; /* offset: 0x00AB size: 8 bit */ + INTC_PSR_8B_tag PSR108; /* offset: 0x00AC size: 8 bit */ + INTC_PSR_8B_tag PSR109; /* offset: 0x00AD size: 8 bit */ + INTC_PSR_8B_tag PSR110; /* offset: 0x00AE size: 8 bit */ + INTC_PSR_8B_tag PSR111; /* offset: 0x00AF size: 8 bit */ + INTC_PSR_8B_tag PSR112; /* offset: 0x00B0 size: 8 bit */ + INTC_PSR_8B_tag PSR113; /* offset: 0x00B1 size: 8 bit */ + INTC_PSR_8B_tag PSR114; /* offset: 0x00B2 size: 8 bit */ + INTC_PSR_8B_tag PSR115; /* offset: 0x00B3 size: 8 bit */ + INTC_PSR_8B_tag PSR116; /* offset: 0x00B4 size: 8 bit */ + INTC_PSR_8B_tag PSR117; /* offset: 0x00B5 size: 8 bit */ + INTC_PSR_8B_tag PSR118; /* offset: 0x00B6 size: 8 bit */ + INTC_PSR_8B_tag PSR119; /* offset: 0x00B7 size: 8 bit */ + INTC_PSR_8B_tag PSR120; /* offset: 0x00B8 size: 8 bit */ + INTC_PSR_8B_tag PSR121; /* offset: 0x00B9 size: 8 bit */ + INTC_PSR_8B_tag PSR122; /* offset: 0x00BA size: 8 bit */ + INTC_PSR_8B_tag PSR123; /* offset: 0x00BB size: 8 bit */ + INTC_PSR_8B_tag PSR124; /* offset: 0x00BC size: 8 bit */ + INTC_PSR_8B_tag PSR125; /* offset: 0x00BD size: 8 bit */ + INTC_PSR_8B_tag PSR126; /* offset: 0x00BE size: 8 bit */ + INTC_PSR_8B_tag PSR127; /* offset: 0x00BF size: 8 bit */ + INTC_PSR_8B_tag PSR128; /* offset: 0x00C0 size: 8 bit */ + INTC_PSR_8B_tag PSR129; /* offset: 0x00C1 size: 8 bit */ + INTC_PSR_8B_tag PSR130; /* offset: 0x00C2 size: 8 bit */ + INTC_PSR_8B_tag PSR131; /* offset: 0x00C3 size: 8 bit */ + INTC_PSR_8B_tag PSR132; /* offset: 0x00C4 size: 8 bit */ + INTC_PSR_8B_tag PSR133; /* offset: 0x00C5 size: 8 bit */ + INTC_PSR_8B_tag PSR134; /* offset: 0x00C6 size: 8 bit */ + INTC_PSR_8B_tag PSR135; /* offset: 0x00C7 size: 8 bit */ + INTC_PSR_8B_tag PSR136; /* offset: 0x00C8 size: 8 bit */ + INTC_PSR_8B_tag PSR137; /* offset: 0x00C9 size: 8 bit */ + INTC_PSR_8B_tag PSR138; /* offset: 0x00CA size: 8 bit */ + INTC_PSR_8B_tag PSR139; /* offset: 0x00CB size: 8 bit */ + INTC_PSR_8B_tag PSR140; /* offset: 0x00CC size: 8 bit */ + INTC_PSR_8B_tag PSR141; /* offset: 0x00CD size: 8 bit */ + INTC_PSR_8B_tag PSR142; /* offset: 0x00CE size: 8 bit */ + INTC_PSR_8B_tag PSR143; /* offset: 0x00CF size: 8 bit */ + INTC_PSR_8B_tag PSR144; /* offset: 0x00D0 size: 8 bit */ + INTC_PSR_8B_tag PSR145; /* offset: 0x00D1 size: 8 bit */ + INTC_PSR_8B_tag PSR146; /* offset: 0x00D2 size: 8 bit */ + INTC_PSR_8B_tag PSR147; /* offset: 0x00D3 size: 8 bit */ + INTC_PSR_8B_tag PSR148; /* offset: 0x00D4 size: 8 bit */ + INTC_PSR_8B_tag PSR149; /* offset: 0x00D5 size: 8 bit */ + INTC_PSR_8B_tag PSR150; /* offset: 0x00D6 size: 8 bit */ + INTC_PSR_8B_tag PSR151; /* offset: 0x00D7 size: 8 bit */ + INTC_PSR_8B_tag PSR152; /* offset: 0x00D8 size: 8 bit */ + INTC_PSR_8B_tag PSR153; /* offset: 0x00D9 size: 8 bit */ + INTC_PSR_8B_tag PSR154; /* offset: 0x00DA size: 8 bit */ + INTC_PSR_8B_tag PSR155; /* offset: 0x00DB size: 8 bit */ + INTC_PSR_8B_tag PSR156; /* offset: 0x00DC size: 8 bit */ + INTC_PSR_8B_tag PSR157; /* offset: 0x00DD size: 8 bit */ + INTC_PSR_8B_tag PSR158; /* offset: 0x00DE size: 8 bit */ + INTC_PSR_8B_tag PSR159; /* offset: 0x00DF size: 8 bit */ + INTC_PSR_8B_tag PSR160; /* offset: 0x00E0 size: 8 bit */ + INTC_PSR_8B_tag PSR161; /* offset: 0x00E1 size: 8 bit */ + INTC_PSR_8B_tag PSR162; /* offset: 0x00E2 size: 8 bit */ + INTC_PSR_8B_tag PSR163; /* offset: 0x00E3 size: 8 bit */ + INTC_PSR_8B_tag PSR164; /* offset: 0x00E4 size: 8 bit */ + INTC_PSR_8B_tag PSR165; /* offset: 0x00E5 size: 8 bit */ + INTC_PSR_8B_tag PSR166; /* offset: 0x00E6 size: 8 bit */ + INTC_PSR_8B_tag PSR167; /* offset: 0x00E7 size: 8 bit */ + INTC_PSR_8B_tag PSR168; /* offset: 0x00E8 size: 8 bit */ + INTC_PSR_8B_tag PSR169; /* offset: 0x00E9 size: 8 bit */ + INTC_PSR_8B_tag PSR170; /* offset: 0x00EA size: 8 bit */ + INTC_PSR_8B_tag PSR171; /* offset: 0x00EB size: 8 bit */ + INTC_PSR_8B_tag PSR172; /* offset: 0x00EC size: 8 bit */ + INTC_PSR_8B_tag PSR173; /* offset: 0x00ED size: 8 bit */ + INTC_PSR_8B_tag PSR174; /* offset: 0x00EE size: 8 bit */ + INTC_PSR_8B_tag PSR175; /* offset: 0x00EF size: 8 bit */ + INTC_PSR_8B_tag PSR176; /* offset: 0x00F0 size: 8 bit */ + INTC_PSR_8B_tag PSR177; /* offset: 0x00F1 size: 8 bit */ + INTC_PSR_8B_tag PSR178; /* offset: 0x00F2 size: 8 bit */ + INTC_PSR_8B_tag PSR179; /* offset: 0x00F3 size: 8 bit */ + INTC_PSR_8B_tag PSR180; /* offset: 0x00F4 size: 8 bit */ + INTC_PSR_8B_tag PSR181; /* offset: 0x00F5 size: 8 bit */ + INTC_PSR_8B_tag PSR182; /* offset: 0x00F6 size: 8 bit */ + INTC_PSR_8B_tag PSR183; /* offset: 0x00F7 size: 8 bit */ + INTC_PSR_8B_tag PSR184; /* offset: 0x00F8 size: 8 bit */ + INTC_PSR_8B_tag PSR185; /* offset: 0x00F9 size: 8 bit */ + INTC_PSR_8B_tag PSR186; /* offset: 0x00FA size: 8 bit */ + INTC_PSR_8B_tag PSR187; /* offset: 0x00FB size: 8 bit */ + INTC_PSR_8B_tag PSR188; /* offset: 0x00FC size: 8 bit */ + INTC_PSR_8B_tag PSR189; /* offset: 0x00FD size: 8 bit */ + INTC_PSR_8B_tag PSR190; /* offset: 0x00FE size: 8 bit */ + INTC_PSR_8B_tag PSR191; /* offset: 0x00FF size: 8 bit */ + INTC_PSR_8B_tag PSR192; /* offset: 0x0100 size: 8 bit */ + INTC_PSR_8B_tag PSR193; /* offset: 0x0101 size: 8 bit */ + INTC_PSR_8B_tag PSR194; /* offset: 0x0102 size: 8 bit */ + INTC_PSR_8B_tag PSR195; /* offset: 0x0103 size: 8 bit */ + INTC_PSR_8B_tag PSR196; /* offset: 0x0104 size: 8 bit */ + INTC_PSR_8B_tag PSR197; /* offset: 0x0105 size: 8 bit */ + INTC_PSR_8B_tag PSR198; /* offset: 0x0106 size: 8 bit */ + INTC_PSR_8B_tag PSR199; /* offset: 0x0107 size: 8 bit */ + INTC_PSR_8B_tag PSR200; /* offset: 0x0108 size: 8 bit */ + INTC_PSR_8B_tag PSR201; /* offset: 0x0109 size: 8 bit */ + INTC_PSR_8B_tag PSR202; /* offset: 0x010A size: 8 bit */ + INTC_PSR_8B_tag PSR203; /* offset: 0x010B size: 8 bit */ + INTC_PSR_8B_tag PSR204; /* offset: 0x010C size: 8 bit */ + INTC_PSR_8B_tag PSR205; /* offset: 0x010D size: 8 bit */ + INTC_PSR_8B_tag PSR206; /* offset: 0x010E size: 8 bit */ + INTC_PSR_8B_tag PSR207; /* offset: 0x010F size: 8 bit */ + INTC_PSR_8B_tag PSR208; /* offset: 0x0110 size: 8 bit */ + INTC_PSR_8B_tag PSR209; /* offset: 0x0111 size: 8 bit */ + INTC_PSR_8B_tag PSR210; /* offset: 0x0112 size: 8 bit */ + INTC_PSR_8B_tag PSR211; /* offset: 0x0113 size: 8 bit */ + INTC_PSR_8B_tag PSR212; /* offset: 0x0114 size: 8 bit */ + INTC_PSR_8B_tag PSR213; /* offset: 0x0115 size: 8 bit */ + INTC_PSR_8B_tag PSR214; /* offset: 0x0116 size: 8 bit */ + INTC_PSR_8B_tag PSR215; /* offset: 0x0117 size: 8 bit */ + INTC_PSR_8B_tag PSR216; /* offset: 0x0118 size: 8 bit */ + INTC_PSR_8B_tag PSR217; /* offset: 0x0119 size: 8 bit */ + INTC_PSR_8B_tag PSR218; /* offset: 0x011A size: 8 bit */ + INTC_PSR_8B_tag PSR219; /* offset: 0x011B size: 8 bit */ + INTC_PSR_8B_tag PSR220; /* offset: 0x011C size: 8 bit */ + INTC_PSR_8B_tag PSR221; /* offset: 0x011D size: 8 bit */ + INTC_PSR_8B_tag PSR222; /* offset: 0x011E size: 8 bit */ + INTC_PSR_8B_tag PSR223; /* offset: 0x011F size: 8 bit */ + INTC_PSR_8B_tag PSR224; /* offset: 0x0120 size: 8 bit */ + INTC_PSR_8B_tag PSR225; /* offset: 0x0121 size: 8 bit */ + INTC_PSR_8B_tag PSR226; /* offset: 0x0122 size: 8 bit */ + INTC_PSR_8B_tag PSR227; /* offset: 0x0123 size: 8 bit */ + INTC_PSR_8B_tag PSR228; /* offset: 0x0124 size: 8 bit */ + INTC_PSR_8B_tag PSR229; /* offset: 0x0125 size: 8 bit */ + INTC_PSR_8B_tag PSR230; /* offset: 0x0126 size: 8 bit */ + INTC_PSR_8B_tag PSR231; /* offset: 0x0127 size: 8 bit */ + INTC_PSR_8B_tag PSR232; /* offset: 0x0128 size: 8 bit */ + INTC_PSR_8B_tag PSR233; /* offset: 0x0129 size: 8 bit */ + INTC_PSR_8B_tag PSR234; /* offset: 0x012A size: 8 bit */ + INTC_PSR_8B_tag PSR235; /* offset: 0x012B size: 8 bit */ + INTC_PSR_8B_tag PSR236; /* offset: 0x012C size: 8 bit */ + INTC_PSR_8B_tag PSR237; /* offset: 0x012D size: 8 bit */ + INTC_PSR_8B_tag PSR238; /* offset: 0x012E size: 8 bit */ + INTC_PSR_8B_tag PSR239; /* offset: 0x012F size: 8 bit */ + INTC_PSR_8B_tag PSR240; /* offset: 0x0130 size: 8 bit */ + INTC_PSR_8B_tag PSR241; /* offset: 0x0131 size: 8 bit */ + INTC_PSR_8B_tag PSR242; /* offset: 0x0132 size: 8 bit */ + INTC_PSR_8B_tag PSR243; /* offset: 0x0133 size: 8 bit */ + INTC_PSR_8B_tag PSR244; /* offset: 0x0134 size: 8 bit */ + INTC_PSR_8B_tag PSR245; /* offset: 0x0135 size: 8 bit */ + INTC_PSR_8B_tag PSR246; /* offset: 0x0136 size: 8 bit */ + INTC_PSR_8B_tag PSR247; /* offset: 0x0137 size: 8 bit */ + INTC_PSR_8B_tag PSR248; /* offset: 0x0138 size: 8 bit */ + INTC_PSR_8B_tag PSR249; /* offset: 0x0139 size: 8 bit */ + INTC_PSR_8B_tag PSR250; /* offset: 0x013A size: 8 bit */ + INTC_PSR_8B_tag PSR251; /* offset: 0x013B size: 8 bit */ + INTC_PSR_8B_tag PSR252; /* offset: 0x013C size: 8 bit */ + INTC_PSR_8B_tag PSR253; /* offset: 0x013D size: 8 bit */ + INTC_PSR_8B_tag PSR254; /* offset: 0x013E size: 8 bit */ + INTC_PSR_8B_tag PSR255; /* offset: 0x013F size: 8 bit */ + INTC_PSR_8B_tag PSR256; /* offset: 0x0140 size: 8 bit */ + INTC_PSR_8B_tag PSR257; /* offset: 0x0141 size: 8 bit */ + INTC_PSR_8B_tag PSR258; /* offset: 0x0142 size: 8 bit */ + INTC_PSR_8B_tag PSR259; /* offset: 0x0143 size: 8 bit */ + INTC_PSR_8B_tag PSR260; /* offset: 0x0144 size: 8 bit */ + INTC_PSR_8B_tag PSR261; /* offset: 0x0145 size: 8 bit */ + INTC_PSR_8B_tag PSR262; /* offset: 0x0146 size: 8 bit */ + INTC_PSR_8B_tag PSR263; /* offset: 0x0147 size: 8 bit */ + INTC_PSR_8B_tag PSR264; /* offset: 0x0148 size: 8 bit */ + INTC_PSR_8B_tag PSR265; /* offset: 0x0149 size: 8 bit */ + INTC_PSR_8B_tag PSR266; /* offset: 0x014A size: 8 bit */ + INTC_PSR_8B_tag PSR267; /* offset: 0x014B size: 8 bit */ + INTC_PSR_8B_tag PSR268; /* offset: 0x014C size: 8 bit */ + INTC_PSR_8B_tag PSR269; /* offset: 0x014D size: 8 bit */ + INTC_PSR_8B_tag PSR270; /* offset: 0x014E size: 8 bit */ + INTC_PSR_8B_tag PSR271; /* offset: 0x014F size: 8 bit */ + INTC_PSR_8B_tag PSR272; /* offset: 0x0150 size: 8 bit */ + INTC_PSR_8B_tag PSR273; /* offset: 0x0151 size: 8 bit */ + INTC_PSR_8B_tag PSR274; /* offset: 0x0152 size: 8 bit */ + INTC_PSR_8B_tag PSR275; /* offset: 0x0153 size: 8 bit */ + INTC_PSR_8B_tag PSR276; /* offset: 0x0154 size: 8 bit */ + INTC_PSR_8B_tag PSR277; /* offset: 0x0155 size: 8 bit */ + INTC_PSR_8B_tag PSR278; /* offset: 0x0156 size: 8 bit */ + INTC_PSR_8B_tag PSR279; /* offset: 0x0157 size: 8 bit */ + INTC_PSR_8B_tag PSR280; /* offset: 0x0158 size: 8 bit */ + INTC_PSR_8B_tag PSR281; /* offset: 0x0159 size: 8 bit */ + INTC_PSR_8B_tag PSR282; /* offset: 0x015A size: 8 bit */ + INTC_PSR_8B_tag PSR283; /* offset: 0x015B size: 8 bit */ + INTC_PSR_8B_tag PSR284; /* offset: 0x015C size: 8 bit */ + INTC_PSR_8B_tag PSR285; /* offset: 0x015D size: 8 bit */ + INTC_PSR_8B_tag PSR286; /* offset: 0x015E size: 8 bit */ + INTC_PSR_8B_tag PSR287; /* offset: 0x015F size: 8 bit */ + INTC_PSR_8B_tag PSR288; /* offset: 0x0160 size: 8 bit */ + INTC_PSR_8B_tag PSR289; /* offset: 0x0161 size: 8 bit */ + INTC_PSR_8B_tag PSR290; /* offset: 0x0162 size: 8 bit */ + INTC_PSR_8B_tag PSR291; /* offset: 0x0163 size: 8 bit */ + INTC_PSR_8B_tag PSR292; /* offset: 0x0164 size: 8 bit */ + INTC_PSR_8B_tag PSR293; /* offset: 0x0165 size: 8 bit */ + INTC_PSR_8B_tag PSR294; /* offset: 0x0166 size: 8 bit */ + INTC_PSR_8B_tag PSR295; /* offset: 0x0167 size: 8 bit */ + INTC_PSR_8B_tag PSR296; /* offset: 0x0168 size: 8 bit */ + INTC_PSR_8B_tag PSR297; /* offset: 0x0169 size: 8 bit */ + INTC_PSR_8B_tag PSR298; /* offset: 0x016A size: 8 bit */ + INTC_PSR_8B_tag PSR299; /* offset: 0x016B size: 8 bit */ + INTC_PSR_8B_tag PSR300; /* offset: 0x016C size: 8 bit */ + INTC_PSR_8B_tag PSR301; /* offset: 0x016D size: 8 bit */ + INTC_PSR_8B_tag PSR302; /* offset: 0x016E size: 8 bit */ + INTC_PSR_8B_tag PSR303; /* offset: 0x016F size: 8 bit */ + INTC_PSR_8B_tag PSR304; /* offset: 0x0170 size: 8 bit */ + INTC_PSR_8B_tag PSR305; /* offset: 0x0171 size: 8 bit */ + INTC_PSR_8B_tag PSR306; /* offset: 0x0172 size: 8 bit */ + INTC_PSR_8B_tag PSR307; /* offset: 0x0173 size: 8 bit */ + INTC_PSR_8B_tag PSR308; /* offset: 0x0174 size: 8 bit */ + INTC_PSR_8B_tag PSR309; /* offset: 0x0175 size: 8 bit */ + INTC_PSR_8B_tag PSR310; /* offset: 0x0176 size: 8 bit */ + INTC_PSR_8B_tag PSR311; /* offset: 0x0177 size: 8 bit */ + INTC_PSR_8B_tag PSR312; /* offset: 0x0178 size: 8 bit */ + INTC_PSR_8B_tag PSR313; /* offset: 0x0179 size: 8 bit */ + INTC_PSR_8B_tag PSR314; /* offset: 0x017A size: 8 bit */ + INTC_PSR_8B_tag PSR315; /* offset: 0x017B size: 8 bit */ + INTC_PSR_8B_tag PSR316; /* offset: 0x017C size: 8 bit */ + INTC_PSR_8B_tag PSR317; /* offset: 0x017D size: 8 bit */ + INTC_PSR_8B_tag PSR318; /* offset: 0x017E size: 8 bit */ + INTC_PSR_8B_tag PSR319; /* offset: 0x017F size: 8 bit */ + INTC_PSR_8B_tag PSR320; /* offset: 0x0180 size: 8 bit */ + INTC_PSR_8B_tag PSR321; /* offset: 0x0181 size: 8 bit */ + INTC_PSR_8B_tag PSR322; /* offset: 0x0182 size: 8 bit */ + INTC_PSR_8B_tag PSR323; /* offset: 0x0183 size: 8 bit */ + INTC_PSR_8B_tag PSR324; /* offset: 0x0184 size: 8 bit */ + INTC_PSR_8B_tag PSR325; /* offset: 0x0185 size: 8 bit */ + INTC_PSR_8B_tag PSR326; /* offset: 0x0186 size: 8 bit */ + INTC_PSR_8B_tag PSR327; /* offset: 0x0187 size: 8 bit */ + INTC_PSR_8B_tag PSR328; /* offset: 0x0188 size: 8 bit */ + INTC_PSR_8B_tag PSR329; /* offset: 0x0189 size: 8 bit */ + INTC_PSR_8B_tag PSR330; /* offset: 0x018A size: 8 bit */ + INTC_PSR_8B_tag PSR331; /* offset: 0x018B size: 8 bit */ + INTC_PSR_8B_tag PSR332; /* offset: 0x018C size: 8 bit */ + INTC_PSR_8B_tag PSR333; /* offset: 0x018D size: 8 bit */ + INTC_PSR_8B_tag PSR334; /* offset: 0x018E size: 8 bit */ + INTC_PSR_8B_tag PSR335; /* offset: 0x018F size: 8 bit */ + INTC_PSR_8B_tag PSR336; /* offset: 0x0190 size: 8 bit */ + INTC_PSR_8B_tag PSR337; /* offset: 0x0191 size: 8 bit */ + INTC_PSR_8B_tag PSR338; /* offset: 0x0192 size: 8 bit */ + INTC_PSR_8B_tag PSR339; /* offset: 0x0193 size: 8 bit */ + INTC_PSR_8B_tag PSR340; /* offset: 0x0194 size: 8 bit */ + INTC_PSR_8B_tag PSR341; /* offset: 0x0195 size: 8 bit */ + INTC_PSR_8B_tag PSR342; /* offset: 0x0196 size: 8 bit */ + INTC_PSR_8B_tag PSR343; /* offset: 0x0197 size: 8 bit */ + INTC_PSR_8B_tag PSR344; /* offset: 0x0198 size: 8 bit */ + INTC_PSR_8B_tag PSR345; /* offset: 0x0199 size: 8 bit */ + INTC_PSR_8B_tag PSR346; /* offset: 0x019A size: 8 bit */ + INTC_PSR_8B_tag PSR347; /* offset: 0x019B size: 8 bit */ + INTC_PSR_8B_tag PSR348; /* offset: 0x019C size: 8 bit */ + INTC_PSR_8B_tag PSR349; /* offset: 0x019D size: 8 bit */ + INTC_PSR_8B_tag PSR350; /* offset: 0x019E size: 8 bit */ + INTC_PSR_8B_tag PSR351; /* offset: 0x019F size: 8 bit */ + INTC_PSR_8B_tag PSR352; /* offset: 0x01A0 size: 8 bit */ + INTC_PSR_8B_tag PSR353; /* offset: 0x01A1 size: 8 bit */ + INTC_PSR_8B_tag PSR354; /* offset: 0x01A2 size: 8 bit */ + INTC_PSR_8B_tag PSR355; /* offset: 0x01A3 size: 8 bit */ + INTC_PSR_8B_tag PSR356; /* offset: 0x01A4 size: 8 bit */ + INTC_PSR_8B_tag PSR357; /* offset: 0x01A5 size: 8 bit */ + INTC_PSR_8B_tag PSR358; /* offset: 0x01A6 size: 8 bit */ + INTC_PSR_8B_tag PSR359; /* offset: 0x01A7 size: 8 bit */ + INTC_PSR_8B_tag PSR360; /* offset: 0x01A8 size: 8 bit */ + INTC_PSR_8B_tag PSR361; /* offset: 0x01A9 size: 8 bit */ + INTC_PSR_8B_tag PSR362; /* offset: 0x01AA size: 8 bit */ + INTC_PSR_8B_tag PSR363; /* offset: 0x01AB size: 8 bit */ + INTC_PSR_8B_tag PSR364; /* offset: 0x01AC size: 8 bit */ + INTC_PSR_8B_tag PSR365; /* offset: 0x01AD size: 8 bit */ + INTC_PSR_8B_tag PSR366; /* offset: 0x01AE size: 8 bit */ + INTC_PSR_8B_tag PSR367; /* offset: 0x01AF size: 8 bit */ + INTC_PSR_8B_tag PSR368; /* offset: 0x01B0 size: 8 bit */ + INTC_PSR_8B_tag PSR369; /* offset: 0x01B1 size: 8 bit */ + INTC_PSR_8B_tag PSR370; /* offset: 0x01B2 size: 8 bit */ + INTC_PSR_8B_tag PSR371; /* offset: 0x01B3 size: 8 bit */ + INTC_PSR_8B_tag PSR372; /* offset: 0x01B4 size: 8 bit */ + INTC_PSR_8B_tag PSR373; /* offset: 0x01B5 size: 8 bit */ + INTC_PSR_8B_tag PSR374; /* offset: 0x01B6 size: 8 bit */ + INTC_PSR_8B_tag PSR375; /* offset: 0x01B7 size: 8 bit */ + INTC_PSR_8B_tag PSR376; /* offset: 0x01B8 size: 8 bit */ + INTC_PSR_8B_tag PSR377; /* offset: 0x01B9 size: 8 bit */ + INTC_PSR_8B_tag PSR378; /* offset: 0x01BA size: 8 bit */ + INTC_PSR_8B_tag PSR379; /* offset: 0x01BB size: 8 bit */ + INTC_PSR_8B_tag PSR380; /* offset: 0x01BC size: 8 bit */ + INTC_PSR_8B_tag PSR381; /* offset: 0x01BD size: 8 bit */ + INTC_PSR_8B_tag PSR382; /* offset: 0x01BE size: 8 bit */ + INTC_PSR_8B_tag PSR383; /* offset: 0x01BF size: 8 bit */ + INTC_PSR_8B_tag PSR384; /* offset: 0x01C0 size: 8 bit */ + INTC_PSR_8B_tag PSR385; /* offset: 0x01C1 size: 8 bit */ + INTC_PSR_8B_tag PSR386; /* offset: 0x01C2 size: 8 bit */ + INTC_PSR_8B_tag PSR387; /* offset: 0x01C3 size: 8 bit */ + INTC_PSR_8B_tag PSR388; /* offset: 0x01C4 size: 8 bit */ + INTC_PSR_8B_tag PSR389; /* offset: 0x01C5 size: 8 bit */ + INTC_PSR_8B_tag PSR390; /* offset: 0x01C6 size: 8 bit */ + INTC_PSR_8B_tag PSR391; /* offset: 0x01C7 size: 8 bit */ + INTC_PSR_8B_tag PSR392; /* offset: 0x01C8 size: 8 bit */ + INTC_PSR_8B_tag PSR393; /* offset: 0x01C9 size: 8 bit */ + INTC_PSR_8B_tag PSR394; /* offset: 0x01CA size: 8 bit */ + INTC_PSR_8B_tag PSR395; /* offset: 0x01CB size: 8 bit */ + INTC_PSR_8B_tag PSR396; /* offset: 0x01CC size: 8 bit */ + INTC_PSR_8B_tag PSR397; /* offset: 0x01CD size: 8 bit */ + INTC_PSR_8B_tag PSR398; /* offset: 0x01CE size: 8 bit */ + INTC_PSR_8B_tag PSR399; /* offset: 0x01CF size: 8 bit */ + INTC_PSR_8B_tag PSR400; /* offset: 0x01D0 size: 8 bit */ + INTC_PSR_8B_tag PSR401; /* offset: 0x01D1 size: 8 bit */ + INTC_PSR_8B_tag PSR402; /* offset: 0x01D2 size: 8 bit */ + INTC_PSR_8B_tag PSR403; /* offset: 0x01D3 size: 8 bit */ + INTC_PSR_8B_tag PSR404; /* offset: 0x01D4 size: 8 bit */ + INTC_PSR_8B_tag PSR405; /* offset: 0x01D5 size: 8 bit */ + INTC_PSR_8B_tag PSR406; /* offset: 0x01D6 size: 8 bit */ + INTC_PSR_8B_tag PSR407; /* offset: 0x01D7 size: 8 bit */ + INTC_PSR_8B_tag PSR408; /* offset: 0x01D8 size: 8 bit */ + INTC_PSR_8B_tag PSR409; /* offset: 0x01D9 size: 8 bit */ + INTC_PSR_8B_tag PSR410; /* offset: 0x01DA size: 8 bit */ + INTC_PSR_8B_tag PSR411; /* offset: 0x01DB size: 8 bit */ + INTC_PSR_8B_tag PSR412; /* offset: 0x01DC size: 8 bit */ + INTC_PSR_8B_tag PSR413; /* offset: 0x01DD size: 8 bit */ + INTC_PSR_8B_tag PSR414; /* offset: 0x01DE size: 8 bit */ + INTC_PSR_8B_tag PSR415; /* offset: 0x01DF size: 8 bit */ + INTC_PSR_8B_tag PSR416; /* offset: 0x01E0 size: 8 bit */ + INTC_PSR_8B_tag PSR417; /* offset: 0x01E1 size: 8 bit */ + INTC_PSR_8B_tag PSR418; /* offset: 0x01E2 size: 8 bit */ + INTC_PSR_8B_tag PSR419; /* offset: 0x01E3 size: 8 bit */ + INTC_PSR_8B_tag PSR420; /* offset: 0x01E4 size: 8 bit */ + INTC_PSR_8B_tag PSR421; /* offset: 0x01E5 size: 8 bit */ + INTC_PSR_8B_tag PSR422; /* offset: 0x01E6 size: 8 bit */ + INTC_PSR_8B_tag PSR423; /* offset: 0x01E7 size: 8 bit */ + INTC_PSR_8B_tag PSR424; /* offset: 0x01E8 size: 8 bit */ + INTC_PSR_8B_tag PSR425; /* offset: 0x01E9 size: 8 bit */ + INTC_PSR_8B_tag PSR426; /* offset: 0x01EA size: 8 bit */ + INTC_PSR_8B_tag PSR427; /* offset: 0x01EB size: 8 bit */ + INTC_PSR_8B_tag PSR428; /* offset: 0x01EC size: 8 bit */ + INTC_PSR_8B_tag PSR429; /* offset: 0x01ED size: 8 bit */ + INTC_PSR_8B_tag PSR430; /* offset: 0x01EE size: 8 bit */ + INTC_PSR_8B_tag PSR431; /* offset: 0x01EF size: 8 bit */ + INTC_PSR_8B_tag PSR432; /* offset: 0x01F0 size: 8 bit */ + INTC_PSR_8B_tag PSR433; /* offset: 0x01F1 size: 8 bit */ + INTC_PSR_8B_tag PSR434; /* offset: 0x01F2 size: 8 bit */ + INTC_PSR_8B_tag PSR435; /* offset: 0x01F3 size: 8 bit */ + INTC_PSR_8B_tag PSR436; /* offset: 0x01F4 size: 8 bit */ + INTC_PSR_8B_tag PSR437; /* offset: 0x01F5 size: 8 bit */ + INTC_PSR_8B_tag PSR438; /* offset: 0x01F6 size: 8 bit */ + INTC_PSR_8B_tag PSR439; /* offset: 0x01F7 size: 8 bit */ + INTC_PSR_8B_tag PSR440; /* offset: 0x01F8 size: 8 bit */ + INTC_PSR_8B_tag PSR441; /* offset: 0x01F9 size: 8 bit */ + INTC_PSR_8B_tag PSR442; /* offset: 0x01FA size: 8 bit */ + INTC_PSR_8B_tag PSR443; /* offset: 0x01FB size: 8 bit */ + INTC_PSR_8B_tag PSR444; /* offset: 0x01FC size: 8 bit */ + INTC_PSR_8B_tag PSR445; /* offset: 0x01FD size: 8 bit */ + INTC_PSR_8B_tag PSR446; /* offset: 0x01FE size: 8 bit */ + INTC_PSR_8B_tag PSR447; /* offset: 0x01FF size: 8 bit */ + INTC_PSR_8B_tag PSR448; /* offset: 0x0200 size: 8 bit */ + INTC_PSR_8B_tag PSR449; /* offset: 0x0201 size: 8 bit */ + INTC_PSR_8B_tag PSR450; /* offset: 0x0202 size: 8 bit */ + INTC_PSR_8B_tag PSR451; /* offset: 0x0203 size: 8 bit */ + INTC_PSR_8B_tag PSR452; /* offset: 0x0204 size: 8 bit */ + INTC_PSR_8B_tag PSR453; /* offset: 0x0205 size: 8 bit */ + INTC_PSR_8B_tag PSR454; /* offset: 0x0206 size: 8 bit */ + INTC_PSR_8B_tag PSR455; /* offset: 0x0207 size: 8 bit */ + INTC_PSR_8B_tag PSR456; /* offset: 0x0208 size: 8 bit */ + INTC_PSR_8B_tag PSR457; /* offset: 0x0209 size: 8 bit */ + INTC_PSR_8B_tag PSR458; /* offset: 0x020A size: 8 bit */ + INTC_PSR_8B_tag PSR459; /* offset: 0x020B size: 8 bit */ + INTC_PSR_8B_tag PSR460; /* offset: 0x020C size: 8 bit */ + INTC_PSR_8B_tag PSR461; /* offset: 0x020D size: 8 bit */ + INTC_PSR_8B_tag PSR462; /* offset: 0x020E size: 8 bit */ + INTC_PSR_8B_tag PSR463; /* offset: 0x020F size: 8 bit */ + INTC_PSR_8B_tag PSR464; /* offset: 0x0210 size: 8 bit */ + INTC_PSR_8B_tag PSR465; /* offset: 0x0211 size: 8 bit */ + INTC_PSR_8B_tag PSR466; /* offset: 0x0212 size: 8 bit */ + INTC_PSR_8B_tag PSR467; /* offset: 0x0213 size: 8 bit */ + INTC_PSR_8B_tag PSR468; /* offset: 0x0214 size: 8 bit */ + INTC_PSR_8B_tag PSR469; /* offset: 0x0215 size: 8 bit */ + INTC_PSR_8B_tag PSR470; /* offset: 0x0216 size: 8 bit */ + INTC_PSR_8B_tag PSR471; /* offset: 0x0217 size: 8 bit */ + INTC_PSR_8B_tag PSR472; /* offset: 0x0218 size: 8 bit */ + INTC_PSR_8B_tag PSR473; /* offset: 0x0219 size: 8 bit */ + INTC_PSR_8B_tag PSR474; /* offset: 0x021A size: 8 bit */ + INTC_PSR_8B_tag PSR475; /* offset: 0x021B size: 8 bit */ + INTC_PSR_8B_tag PSR476; /* offset: 0x021C size: 8 bit */ + INTC_PSR_8B_tag PSR477; /* offset: 0x021D size: 8 bit */ + INTC_PSR_8B_tag PSR478; /* offset: 0x021E size: 8 bit */ + INTC_PSR_8B_tag PSR479; /* offset: 0x021F size: 8 bit */ + INTC_PSR_8B_tag PSR480; /* offset: 0x0220 size: 8 bit */ + INTC_PSR_8B_tag PSR481; /* offset: 0x0221 size: 8 bit */ + INTC_PSR_8B_tag PSR482; /* offset: 0x0222 size: 8 bit */ + INTC_PSR_8B_tag PSR483; /* offset: 0x0223 size: 8 bit */ + INTC_PSR_8B_tag PSR484; /* offset: 0x0224 size: 8 bit */ + INTC_PSR_8B_tag PSR485; /* offset: 0x0225 size: 8 bit */ + INTC_PSR_8B_tag PSR486; /* offset: 0x0226 size: 8 bit */ + INTC_PSR_8B_tag PSR487; /* offset: 0x0227 size: 8 bit */ + INTC_PSR_8B_tag PSR488; /* offset: 0x0228 size: 8 bit */ + INTC_PSR_8B_tag PSR489; /* offset: 0x0229 size: 8 bit */ + INTC_PSR_8B_tag PSR490; /* offset: 0x022A size: 8 bit */ + INTC_PSR_8B_tag PSR491; /* offset: 0x022B size: 8 bit */ + INTC_PSR_8B_tag PSR492; /* offset: 0x022C size: 8 bit */ + INTC_PSR_8B_tag PSR493; /* offset: 0x022D size: 8 bit */ + INTC_PSR_8B_tag PSR494; /* offset: 0x022E size: 8 bit */ + INTC_PSR_8B_tag PSR495; /* offset: 0x022F size: 8 bit */ + INTC_PSR_8B_tag PSR496; /* offset: 0x0230 size: 8 bit */ + INTC_PSR_8B_tag PSR497; /* offset: 0x0231 size: 8 bit */ + INTC_PSR_8B_tag PSR498; /* offset: 0x0232 size: 8 bit */ + INTC_PSR_8B_tag PSR499; /* offset: 0x0233 size: 8 bit */ + INTC_PSR_8B_tag PSR500; /* offset: 0x0234 size: 8 bit */ + INTC_PSR_8B_tag PSR501; /* offset: 0x0235 size: 8 bit */ + INTC_PSR_8B_tag PSR502; /* offset: 0x0236 size: 8 bit */ + INTC_PSR_8B_tag PSR503; /* offset: 0x0237 size: 8 bit */ + INTC_PSR_8B_tag PSR504; /* offset: 0x0238 size: 8 bit */ + INTC_PSR_8B_tag PSR505; /* offset: 0x0239 size: 8 bit */ + INTC_PSR_8B_tag PSR506; /* offset: 0x023A size: 8 bit */ + INTC_PSR_8B_tag PSR507; /* offset: 0x023B size: 8 bit */ + INTC_PSR_8B_tag PSR508; /* offset: 0x023C size: 8 bit */ + INTC_PSR_8B_tag PSR509; /* offset: 0x023D size: 8 bit */ + INTC_PSR_8B_tag PSR510; /* offset: 0x023E size: 8 bit */ + INTC_PSR_8B_tag PSR511; /* offset: 0x023F size: 8 bit */ + }; + + }; + } INTC_tag; + + +#define INTC (*(volatile INTC_tag *) 0xFFF48000UL) + + + +/****************************************************************/ +/* */ +/* Module: DSPI */ +/* */ +/****************************************************************/ + + typedef union DSPI_MCR_tag { /* MCR - Module Configuration Register */ + uint32_t R; + struct { + uint32_t MSTR:1; /* Master/Slave mode select */ + uint32_t CONT_SCKE:1; /* Continuous SCK Enable */ + uint32_t DCONF:2; /* DSPI Configuration */ + uint32_t FRZ:1; /* Freeze */ + uint32_t MTFE:1; /* Modified Timing Format Enable */ + uint32_t PCSSE:1; /* Peripheral Chip Select Strobe Enable */ + uint32_t ROOE:1; /* Receive FIFO Overflow Overwrite Enable */ + uint32_t PCSIS7:1; /* Peripheral Chip Select 7 Inactive State */ + uint32_t PCSIS6:1; /* Peripheral Chip Select 6 Inactive State */ + uint32_t PCSIS5:1; /* Peripheral Chip Select 5 Inactive State */ + uint32_t PCSIS4:1; /* Peripheral Chip Select 4 Inactive State */ + uint32_t PCSIS3:1; /* Peripheral Chip Select 3 Inactive State */ + uint32_t PCSIS2:1; /* Peripheral Chip Select 2 Inactive State */ + uint32_t PCSIS1:1; /* Peripheral Chip Select 1 Inactive State */ + uint32_t PCSIS0:1; /* Peripheral Chip Select 0 Inactive State */ + uint32_t DOZE:1; /* Doze Enable */ + uint32_t MDIS:1; /* Module Disable */ + uint32_t DIS_TXF:1; /* Disable Transmit FIFO */ + uint32_t DIS_RXF:1; /* Disable Receive FIFO */ + uint32_t CLR_TXF:1; /* Clear TX FIFO */ + uint32_t CLR_RXF:1; /* Clear RX FIFO */ + uint32_t SMPL_PT:2; /* Sample Point */ + uint32_t:7; + uint32_t HALT:1; /* Halt */ + } B; + } DSPI_MCR_32B_tag; + + typedef union { /* TCR - Transfer Count Register */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t SPI_TCNT:16; /* SPI Transfer Counter */ +#else + uint32_t TCNT:16; /* deprecated name - please avoid */ +#endif + uint32_t:16; + } B; + } DSPI_TCR_32B_tag; + + + /* Register layout for all registers CTAR... */ + + typedef union DSPI_CTAR_tag { /* CTAR0-7 - Clock and Transfer Attribute Registers */ + uint32_t R; + struct { + uint32_t DBR:1; /* Double Baud Rate */ + uint32_t FMSZ:4; /* Frame Size */ + uint32_t CPOL:1; /* Clock Polarity */ + uint32_t CPHA:1; /* Clock Phase */ + uint32_t LSBFE:1; /* LSB First Enable */ + uint32_t PCSSCK:2; /* PCS to SCK Delay Prescaler */ + uint32_t PASC:2; /* After SCK Delay Prescaler */ + uint32_t PDT:2; /* Delay after Transfer Prescaler */ + uint32_t PBR:2; /* Baud Rate Prescaler */ + uint32_t CSSCK:4; /* PCS to SCK Delay Scaler */ + uint32_t ASC:4; /* After SCK Delay Scaler */ + uint32_t DT:4; /* Delay after Transfer Scaler */ + uint32_t BR:4; /* Baud Rate Scaler */ + } B; + } DSPI_CTAR_32B_tag; + + typedef union DSPI_SR_tag { /* SR - Status Register */ + uint32_t R; + struct { + uint32_t TCF:1; /* Transfer Complete Flag */ + uint32_t TXRXS:1; /* TX & RX Status */ + uint32_t:1; + uint32_t EOQF:1; /* End of queue Flag */ + uint32_t TFUF:1; /* Transmit FIFO Underflow Flag */ + uint32_t:1; + uint32_t TFFF:1; /* Transmit FIFO FIll Flag */ + uint32_t:5; + uint32_t RFOF:1; /* Receive FIFO Overflow Flag */ + uint32_t:1; + uint32_t RFDF:1; /* Receive FIFO Drain Flag */ + uint32_t:1; + uint32_t TXCTR:4; /* TX FIFO Counter */ + uint32_t TXNXTPTR:4; /* Transmit Next Pointer */ + uint32_t RXCTR:4; /* RX FIFO Counter */ + uint32_t POPNXTPTR:4; /* Pop Next Pointer */ + } B; + } DSPI_SR_32B_tag; + + typedef union DSPI_RSER_tag { /* RSER - DMA/Interrupt Request Register */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t TCF_RE:1; /* Transmission Complete Request Enable */ +#else + uint32_t TCFRE:1; /* deprecated name - please avoid */ +#endif + uint32_t:2; +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t EOQF_RE:1; /* DSPI Finished Request Enable */ +#else + uint32_t EOQFRE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t TFUF_RE:1; /* Transmit FIFO Underflow Request Enable */ +#else + uint32_t TFUFRE:1; /* deprecated name - please avoid */ +#endif + uint32_t:1; +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t TFFF_RE:1; /* Transmit FIFO Fill Request Enable */ +#else + uint32_t TFFFRE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t TFFF_DIRS:1; /* Transmit FIFO Fill DMA or Interrupt Request Select */ +#else + uint32_t TFFFDIRS:1; /* deprecated name - please avoid */ +#endif + uint32_t:4; +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t RFOF_RE:1; /* Receive FIFO overflow Request Enable */ +#else + uint32_t RFOFRE:1; /* deprecated name - please avoid */ +#endif + uint32_t:1; +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t RFDF_RE:1; /* Receive FIFO Drain Request Enable */ +#else + uint32_t RFDFRE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t RFDF_DIRS:1; /* Receive FIFO Drain DMA or Interrupt Request Select */ +#else + uint32_t RFDFDIRS:1; /* deprecated name - please avoid */ +#endif + uint32_t:16; + } B; + } DSPI_RSER_32B_tag; + + typedef union DSPI_PUSHR_tag { /* PUSHR - PUSH TX FIFO Register */ + uint32_t R; + struct { + uint32_t CONT:1; /* Continuous Peripheral Chip Select Enable */ + uint32_t CTAS:3; /* Clock and Transfer Attributes Select */ + uint32_t EOQ:1; /* End of Queue */ + uint32_t CTCNT:1; /* Clear SPI_TCNT */ + uint32_t:2; + uint32_t PCS7:1; /* Peripheral Chip Select 7 */ + uint32_t PCS6:1; /* Peripheral Chip Select 6 */ + uint32_t PCS5:1; /* Peripheral Chip Select 5 */ + uint32_t PCS4:1; /* Peripheral Chip Select 4 */ + uint32_t PCS3:1; /* Peripheral Chip Select 3 */ + uint32_t PCS2:1; /* Peripheral Chip Select 2 */ + uint32_t PCS1:1; /* Peripheral Chip Select 1 */ + uint32_t PCS0:1; /* Peripheral Chip Select 0 */ + uint32_t TXDATA:16; /* Transmit Data */ + } B; + } DSPI_PUSHR_32B_tag; + + typedef union DSPI_POPR_tag { /* POPR - POP RX FIFO Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; /* Receive Data */ + } B; + } DSPI_POPR_32B_tag; + + + /* Register layout for all registers TXFR... */ + + typedef union { /* Transmit FIFO Registers */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t FIFO_TXCMD:16; /* Transmit Command */ +#else + uint32_t TXCMD:16; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t FIFO_TXDATA:16; /* Transmit Data */ +#else + uint32_t TXDATA:16; /* deprecated name - please avoid */ +#endif + } B; + } DSPI_TXFR_32B_tag; + + + /* Register layout for all registers RXFR... */ + + typedef union { /* Receive FIFO Registers */ + uint32_t R; + struct { + uint32_t:16; +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t FIFO_RXDATA:16; /* Transmit Data */ +#else + uint32_t RXDATA:16; /* deprecated name - please avoid */ +#endif + } B; + } DSPI_RXFR_32B_tag; + + typedef union { /* DSICR - DSI Configuration Register */ + uint32_t R; + struct { + uint32_t MTOE:1; /* Multiple Transfer Operation Enable */ + uint32_t:1; + uint32_t MTOCNT:6; /* Multiple Transfer Operation Count */ + uint32_t:4; + uint32_t TXSS:1; /* Transmit Data Source Select */ + uint32_t TPOL:1; /* Trigger Polarity */ + uint32_t TRRE:1; /* Trigger Reception Enable */ + uint32_t CID:1; /* Change in Data Transfer Enable */ + uint32_t DCONT:1; /* DSI Continuous Peripheral Chip Select Enable */ + uint32_t DSICTAS:3; /* DSI CLock and Transfer Attributes Select */ + uint32_t:4; + uint32_t DPCS7:1; /* DSI Peripheral Chip Select 7 */ + uint32_t DPCS6:1; /* DSI Peripheral Chip Select 6 */ + uint32_t DPCS5:1; /* DSI Peripheral Chip Select 5 */ + uint32_t DPCS4:1; /* DSI Peripheral Chip Select 4 */ + uint32_t DPCS3:1; /* DSI Peripheral Chip Select 3 */ + uint32_t DPCS2:1; /* DSI Peripheral Chip Select 2 */ + uint32_t DPCS1:1; /* DSI Peripheral Chip Select 1 */ + uint32_t DPCS0:1; /* DSI Peripheral Chip Select 0 */ + } B; + } DSPI_DSICR_32B_tag; + + typedef union { /* SDR - DSI Serialization Data Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t SER_DATA:16; /* Serialized Data */ + } B; + } DSPI_SDR_32B_tag; + + typedef union { /* ASDR - DSI Alternate Serialization Data Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ASER_DATA:16; /* Alternate Serialized Data */ + } B; + } DSPI_ASDR_32B_tag; + + typedef union { /* COMPR - DSI Transmit Comparison Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t COMP_DATA:16; /* Compare Data */ + } B; + } DSPI_COMPR_32B_tag; + + typedef union { /* DDR - DSI Deserialization Data Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t DESER_DATA:16; /* Deserialized Data */ + } B; + } DSPI_DDR_32B_tag; + + typedef union { /* DSICR1 - DSI Configuration Register 1 */ + uint32_t R; + } DSPI_DSICR1_32B_tag; + + + + typedef struct DSPI_tag { /* start of DSPI_tag */ + /* MCR - Module Configuration Register */ + DSPI_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ + int8_t DSPI_reserved_0004[4]; + /* TCR - Transfer Count Register */ + DSPI_TCR_32B_tag TCR; /* offset: 0x0008 size: 32 bit */ + union { + /* CTAR0-7 - Clock and Transfer Attribute Registers */ + DSPI_CTAR_32B_tag CTAR[8]; /* offset: 0x000C (0x0004 x 8) */ + + struct { + /* CTAR0-7 - Clock and Transfer Attribute Registers */ + DSPI_CTAR_32B_tag CTAR0; /* offset: 0x000C size: 32 bit */ + DSPI_CTAR_32B_tag CTAR1; /* offset: 0x0010 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR2; /* offset: 0x0014 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR3; /* offset: 0x0018 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR4; /* offset: 0x001C size: 32 bit */ + DSPI_CTAR_32B_tag CTAR5; /* offset: 0x0020 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR6; /* offset: 0x0024 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR7; /* offset: 0x0028 size: 32 bit */ + }; + + }; + /* SR - Status Register */ + DSPI_SR_32B_tag SR; /* offset: 0x002C size: 32 bit */ + /* RSER - DMA/Interrupt Request Register */ + DSPI_RSER_32B_tag RSER; /* offset: 0x0030 size: 32 bit */ + /* PUSHR - PUSH TX FIFO Register */ + DSPI_PUSHR_32B_tag PUSHR; /* offset: 0x0034 size: 32 bit */ + /* POPR - POP RX FIFO Register */ + DSPI_POPR_32B_tag POPR; /* offset: 0x0038 size: 32 bit */ + union { + /* Transmit FIFO Registers */ + DSPI_TXFR_32B_tag TXFR[5]; /* offset: 0x003C (0x0004 x 5) */ + + struct { + /* Transmit FIFO Registers */ + DSPI_TXFR_32B_tag TXFR0; /* offset: 0x003C size: 32 bit */ + DSPI_TXFR_32B_tag TXFR1; /* offset: 0x0040 size: 32 bit */ + DSPI_TXFR_32B_tag TXFR2; /* offset: 0x0044 size: 32 bit */ + DSPI_TXFR_32B_tag TXFR3; /* offset: 0x0048 size: 32 bit */ + DSPI_TXFR_32B_tag TXFR4; /* offset: 0x004C size: 32 bit */ + }; + + }; + int8_t DSPI_reserved_0050_C[44]; + union { + /* Receive FIFO Registers */ + DSPI_RXFR_32B_tag RXFR[5]; /* offset: 0x007C (0x0004 x 5) */ + + struct { + /* Receive FIFO Registers */ + DSPI_RXFR_32B_tag RXFR0; /* offset: 0x007C size: 32 bit */ + DSPI_RXFR_32B_tag RXFR1; /* offset: 0x0080 size: 32 bit */ + DSPI_RXFR_32B_tag RXFR2; /* offset: 0x0084 size: 32 bit */ + DSPI_RXFR_32B_tag RXFR3; /* offset: 0x0088 size: 32 bit */ + DSPI_RXFR_32B_tag RXFR4; /* offset: 0x008C size: 32 bit */ + }; + + }; + int8_t DSPI_reserved_0090[44]; + /* DSICR - DSI Configuration Register */ + DSPI_DSICR_32B_tag DSICR; /* offset: 0x00BC size: 32 bit */ + /* SDR - DSI Serialization Data Register */ + DSPI_SDR_32B_tag SDR; /* offset: 0x00C0 size: 32 bit */ + /* ASDR - DSI Alternate Serialization Data Register */ + DSPI_ASDR_32B_tag ASDR; /* offset: 0x00C4 size: 32 bit */ + /* COMPR - DSI Transmit Comparison Register */ + DSPI_COMPR_32B_tag COMPR; /* offset: 0x00C8 size: 32 bit */ + /* DDR - DSI Deserialization Data Register */ + DSPI_DDR_32B_tag DDR; /* offset: 0x00CC size: 32 bit */ + /* DSICR1 - DSI Configuration Register 1 */ + DSPI_DSICR1_32B_tag DSICR1; /* offset: 0x00D0 size: 32 bit */ + } DSPI_tag; + + +#define DSPI_A (*(volatile DSPI_tag *) 0xFFF90000UL) +#define DSPI_B (*(volatile DSPI_tag *) 0xFFF94000UL) +#define DSPI_C (*(volatile DSPI_tag *) 0xFFF98000UL) + + + +/****************************************************************/ +/* */ +/* Module: FLEXCAN */ +/* */ +/****************************************************************/ + + typedef union { /* MCR - Module Configuration Register */ + uint32_t R; + struct { + uint32_t MDIS:1; /* Module Disable */ + uint32_t FRZ:1; /* Freeze Enable */ + uint32_t FEN:1; /* FIFO Enable */ + uint32_t HALT:1; /* Halt Flexcan */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t NOT_RDY:1; /* Flexcan Not Ready */ +#else + uint32_t NOTRDY:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t WAK_MSK:1; /* Wake Up Interrupt Mask */ +#else + uint32_t WAKMSK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t SOFT_RST:1; /* Soft Reset */ +#else + uint32_t SOFTRST:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t FRZ_ACK:1; /* Freeze Mode Acknowledge */ +#else + uint32_t FRZACK:1; /* deprecated name - please avoid */ +#endif + uint32_t SUPV:1; /* Supervisor Mode */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t SLF_WAK:1; /* Self Wake Up */ +#else + uint32_t SLFWAK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t WRN_EN:1; /* Warning Interrupt Enable */ +#else + uint32_t WRNEN:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t LPM_ACK:1; /* Low Power Mode Acknowledge */ +#else + uint32_t LPMACK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t WAK_SRC:1; /* Wake Up Source */ +#else + uint32_t WAKSRC:1; /* deprecated name - please avoid */ +#endif + uint32_t DOZE:1; /* Doze Mode Enable */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t SRX_DIS:1; /* Self Reception Disable */ +#else + uint32_t SRXDIS:1; /* deprecated name - please avoid */ +#endif + uint32_t BCC:1; /* Backwards Compatibility Configuration */ + uint32_t:2; + uint32_t LPRIO_EN:1; /* Local Priority Enable */ + uint32_t AEN:1; /* Abort Enable */ + uint32_t:2; + uint32_t IDAM:2; /* ID Acceptance Mode */ + uint32_t:2; + uint32_t MAXMB:6; /* Maximum Number of Message Buffers */ + } B; + } FLEXCAN_MCR_32B_tag; + + typedef union { /* CTRL - Control Register */ + uint32_t R; + struct { + uint32_t PRESDIV:8; /* Prescaler Divsion Factor */ + uint32_t RJW:2; /* Resync Jump Width */ + uint32_t PSEG1:3; /* Phase Segment 1 */ + uint32_t PSEG2:3; /* Phase Segment 2 */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BOFF_MSK:1; /* Bus Off Mask */ +#else + uint32_t BOFFMSK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t ERR_MSK:1; /* Error Mask */ +#else + uint32_t ERRMSK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t CLK_SRC:1; /* CAN Engine Clock Source */ +#else + uint32_t CLKSRC:1; /* deprecated name - please avoid */ +#endif + uint32_t LPB:1; /* Loop Back */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t TWRN_MSK:1; /* Tx Warning Interrupt Mask */ +#else + uint32_t TWRNMSK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t RWRN_MSK:1; /* Rx Warning Interrupt Mask */ +#else + uint32_t RWRNMSK:1; /* deprecated name - please avoid */ +#endif + uint32_t:2; + uint32_t SMP:1; /* Sampling Mode */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BOFF_REC:1; /* Bus Off Recovery Mode */ +#else + uint32_t BOFFREC:1; /* deprecated name - please avoid */ +#endif + uint32_t TSYN:1; /* Timer Sync Mode */ + uint32_t LBUF:1; /* Lowest Buffer Transmitted First */ + uint32_t LOM:1; /* Listen-Only Mode */ + uint32_t PROPSEG:3; /* Propagation Segment */ + } B; + } FLEXCAN_CTRL_32B_tag; + + typedef union { /* TIMER - Free Running Timer */ + uint32_t R; + } FLEXCAN_TIMER_32B_tag; + + typedef union { /* RXGMASK - Rx Global Mask Register */ + uint32_t R; +#ifndef USE_FIELD_ALIASES_FLEXCAN + struct { + uint32_t MI:32; /* deprecated field -- do not use */ + } B; +#endif + } FLEXCAN_RXGMASK_32B_tag; + + typedef union { /* RX14MASK - Rx 14 Mask Register */ + uint32_t R; +#ifndef USE_FIELD_ALIASES_FLEXCAN + struct { + uint32_t MI:32; /* deprecated field -- do not use */ + } B; +#endif + } FLEXCAN_RX14MASK_32B_tag; + + typedef union { /* RX15MASK - Rx 15 Mask Register */ + uint32_t R; +#ifndef USE_FIELD_ALIASES_FLEXCAN + struct { + uint32_t MI:32; /* deprecated field -- do not use */ + } B; +#endif + } FLEXCAN_RX15MASK_32B_tag; + + typedef union { /* ECR - Error Counter Register */ + uint32_t R; + struct { + uint32_t:16; +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t RX_ERR_COUNTER:8; /* Rx Error Counter */ +#else + uint32_t RXECNT:8; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t TX_ERR_COUNTER:8; /* Tx Error Counter */ +#else + uint32_t TXECNT:8; /* deprecated name - please avoid */ +#endif + } B; + } FLEXCAN_ECR_32B_tag; + + typedef union { /* ESR - Error and Status Register */ + uint32_t R; + struct { + uint32_t:14; +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t TWRN_INT:1; /* Tx Warning Interrupt Flag */ +#else + uint32_t TWRNINT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t RWRN_INT:1; /* Rx Warning Interrupt Flag */ +#else + uint32_t RWRNINT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BIT1_ERR:1; /* Bit 1 Error */ +#else + uint32_t BIT1ERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BIT0_ERR:1; /* Bit 0 Error */ +#else + uint32_t BIT0ERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t ACK_ERR:1; /* Acknowledge Error */ +#else + uint32_t ACKERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t CRC_ERR:1; /* Cyclic Redundancy Check Error */ +#else + uint32_t CRCERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t FRM_ERR:1; /* Form Error */ +#else + uint32_t FRMERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t STF_ERR:1; /* Stuffing Error */ +#else + uint32_t STFERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t TX_WRN:1; /* Tx Error Counter */ +#else + uint32_t TXWRN:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t RX_WRN:1; /* Rx Error Counter */ +#else + uint32_t RXWRN:1; /* deprecated name - please avoid */ +#endif + uint32_t IDLE:1; /* CAN bus Idle State */ + uint32_t TXRX:1; /* Current Flexcan Status */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t FLT_CONF:2; /* Fault Confinement State */ +#else + uint32_t FLTCONF:2; /* deprecated name - please avoid */ +#endif + uint32_t:1; +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BOFF_INT:1; /* Bus Off Interrupt */ +#else + uint32_t BOFFINT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t ERR_INT:1; /* Error Interrupt */ +#else + uint32_t ERRINT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t WAK_INT:1; /* Wake-Up Interrupt */ +#else + uint32_t WAKINT:1; /* deprecated name - please avoid */ +#endif + } B; + } FLEXCAN_ESR_32B_tag; + + typedef union { /* IMASK2 - Interrupt Masks 2 Register */ + uint32_t R; + struct { + uint32_t BUF63M:1; /* Buffer MB Mask 63 Bit */ + uint32_t BUF62M:1; /* Buffer MB Mask 62 Bit */ + uint32_t BUF61M:1; /* Buffer MB Mask 61 Bit */ + uint32_t BUF60M:1; /* Buffer MB Mask 60 Bit */ + uint32_t BUF59M:1; /* Buffer MB Mask 59 Bit */ + uint32_t BUF58M:1; /* Buffer MB Mask 58 Bit */ + uint32_t BUF57M:1; /* Buffer MB Mask 57 Bit */ + uint32_t BUF56M:1; /* Buffer MB Mask 56 Bit */ + uint32_t BUF55M:1; /* Buffer MB Mask 55 Bit */ + uint32_t BUF54M:1; /* Buffer MB Mask 54 Bit */ + uint32_t BUF53M:1; /* Buffer MB Mask 53 Bit */ + uint32_t BUF52M:1; /* Buffer MB Mask 52 Bit */ + uint32_t BUF51M:1; /* Buffer MB Mask 51 Bit */ + uint32_t BUF50M:1; /* Buffer MB Mask 50 Bit */ + uint32_t BUF49M:1; /* Buffer MB Mask 49 Bit */ + uint32_t BUF48M:1; /* Buffer MB Mask 48 Bit */ + uint32_t BUF47M:1; /* Buffer MB Mask 47 Bit */ + uint32_t BUF46M:1; /* Buffer MB Mask 46 Bit */ + uint32_t BUF45M:1; /* Buffer MB Mask 45 Bit */ + uint32_t BUF44M:1; /* Buffer MB Mask 44 Bit */ + uint32_t BUF43M:1; /* Buffer MB Mask 43 Bit */ + uint32_t BUF42M:1; /* Buffer MB Mask 42 Bit */ + uint32_t BUF41M:1; /* Buffer MB Mask 41 Bit */ + uint32_t BUF40M:1; /* Buffer MB Mask 40 Bit */ + uint32_t BUF39M:1; /* Buffer MB Mask 39 Bit */ + uint32_t BUF38M:1; /* Buffer MB Mask 38 Bit */ + uint32_t BUF37M:1; /* Buffer MB Mask 37 Bit */ + uint32_t BUF36M:1; /* Buffer MB Mask 36 Bit */ + uint32_t BUF35M:1; /* Buffer MB Mask 35 Bit */ + uint32_t BUF34M:1; /* Buffer MB Mask 34 Bit */ + uint32_t BUF33M:1; /* Buffer MB Mask 33 Bit */ + uint32_t BUF32M:1; /* Buffer MB Mask 32 Bit */ + } B; + } FLEXCAN_IMASK2_32B_tag; + + typedef union { /* IMASK1 - Interrupt Masks 1 Register */ + uint32_t R; + struct { + uint32_t BUF31M:1; /* Buffer MB Mask 31 Bit */ + uint32_t BUF30M:1; /* Buffer MB Mask 30 Bit */ + uint32_t BUF29M:1; /* Buffer MB Mask 29 Bit */ + uint32_t BUF28M:1; /* Buffer MB Mask 28 Bit */ + uint32_t BUF27M:1; /* Buffer MB Mask 27 Bit */ + uint32_t BUF26M:1; /* Buffer MB Mask 26 Bit */ + uint32_t BUF25M:1; /* Buffer MB Mask 25 Bit */ + uint32_t BUF24M:1; /* Buffer MB Mask 24 Bit */ + uint32_t BUF23M:1; /* Buffer MB Mask 23 Bit */ + uint32_t BUF22M:1; /* Buffer MB Mask 22 Bit */ + uint32_t BUF21M:1; /* Buffer MB Mask 21 Bit */ + uint32_t BUF20M:1; /* Buffer MB Mask 20 Bit */ + uint32_t BUF19M:1; /* Buffer MB Mask 19 Bit */ + uint32_t BUF18M:1; /* Buffer MB Mask 18 Bit */ + uint32_t BUF17M:1; /* Buffer MB Mask 17 Bit */ + uint32_t BUF16M:1; /* Buffer MB Mask 16 Bit */ + uint32_t BUF15M:1; /* Buffer MB Mask 15 Bit */ + uint32_t BUF14M:1; /* Buffer MB Mask 14 Bit */ + uint32_t BUF13M:1; /* Buffer MB Mask 13 Bit */ + uint32_t BUF12M:1; /* Buffer MB Mask 12 Bit */ + uint32_t BUF11M:1; /* Buffer MB Mask 11 Bit */ + uint32_t BUF10M:1; /* Buffer MB Mask 10 Bit */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF9M:1; /* Buffer MB Mask 9 Bit */ +#else + uint32_t BUF09M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF8M:1; /* Buffer MB Mask 8 Bit */ +#else + uint32_t BUF08M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF7M:1; /* Buffer MB Mask 7 Bit */ +#else + uint32_t BUF07M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF6M:1; /* Buffer MB Mask 6 Bit */ +#else + uint32_t BUF06M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF5M:1; /* Buffer MB Mask 5 Bit */ +#else + uint32_t BUF05M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF4M:1; /* Buffer MB Mask 4 Bit */ +#else + uint32_t BUF04M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF3M:1; /* Buffer MB Mask 3 Bit */ +#else + uint32_t BUF03M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF2M:1; /* Buffer MB Mask 2 Bit */ +#else + uint32_t BUF02M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF1M:1; /* Buffer MB Mask 1 Bit */ +#else + uint32_t BUF01M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF0M:1; /* Buffer MB Mask 0 Bit */ +#else + uint32_t BUF00M:1; /* deprecated name - please avoid */ +#endif + } B; + } FLEXCAN_IMASK1_32B_tag; + + typedef union { /* IFLAG2 - Interrupt Flags 2 Register */ + uint32_t R; + struct { + uint32_t BUF63I:1; /* Buffer MB Interrupt 63 Bit */ + uint32_t BUF62I:1; /* Buffer MB Interrupt 62 Bit */ + uint32_t BUF61I:1; /* Buffer MB Interrupt 61 Bit */ + uint32_t BUF60I:1; /* Buffer MB Interrupt 60 Bit */ + uint32_t BUF59I:1; /* Buffer MB Interrupt 59 Bit */ + uint32_t BUF58I:1; /* Buffer MB Interrupt 58 Bit */ + uint32_t BUF57I:1; /* Buffer MB Interrupt 57 Bit */ + uint32_t BUF56I:1; /* Buffer MB Interrupt 56 Bit */ + uint32_t BUF55I:1; /* Buffer MB Interrupt 55 Bit */ + uint32_t BUF54I:1; /* Buffer MB Interrupt 54 Bit */ + uint32_t BUF53I:1; /* Buffer MB Interrupt 53 Bit */ + uint32_t BUF52I:1; /* Buffer MB Interrupt 52 Bit */ + uint32_t BUF51I:1; /* Buffer MB Interrupt 51 Bit */ + uint32_t BUF50I:1; /* Buffer MB Interrupt 50 Bit */ + uint32_t BUF49I:1; /* Buffer MB Interrupt 49 Bit */ + uint32_t BUF48I:1; /* Buffer MB Interrupt 48 Bit */ + uint32_t BUF47I:1; /* Buffer MB Interrupt 47 Bit */ + uint32_t BUF46I:1; /* Buffer MB Interrupt 46 Bit */ + uint32_t BUF45I:1; /* Buffer MB Interrupt 45 Bit */ + uint32_t BUF44I:1; /* Buffer MB Interrupt 44 Bit */ + uint32_t BUF43I:1; /* Buffer MB Interrupt 43 Bit */ + uint32_t BUF42I:1; /* Buffer MB Interrupt 42 Bit */ + uint32_t BUF41I:1; /* Buffer MB Interrupt 41 Bit */ + uint32_t BUF40I:1; /* Buffer MB Interrupt 40 Bit */ + uint32_t BUF39I:1; /* Buffer MB Interrupt 39 Bit */ + uint32_t BUF38I:1; /* Buffer MB Interrupt 38 Bit */ + uint32_t BUF37I:1; /* Buffer MB Interrupt 37 Bit */ + uint32_t BUF36I:1; /* Buffer MB Interrupt 36 Bit */ + uint32_t BUF35I:1; /* Buffer MB Interrupt 35 Bit */ + uint32_t BUF34I:1; /* Buffer MB Interrupt 34 Bit */ + uint32_t BUF33I:1; /* Buffer MB Interrupt 33 Bit */ + uint32_t BUF32I:1; /* Buffer MB Interrupt 32 Bit */ + } B; + } FLEXCAN_IFLAG2_32B_tag; + + typedef union { /* IFLAG1 - Interrupt Flags 1 Register */ + uint32_t R; + struct { + uint32_t BUF31I:1; /* Buffer MB Interrupt 31 Bit */ + uint32_t BUF30I:1; /* Buffer MB Interrupt 30 Bit */ + uint32_t BUF29I:1; /* Buffer MB Interrupt 29 Bit */ + uint32_t BUF28I:1; /* Buffer MB Interrupt 28 Bit */ + uint32_t BUF27I:1; /* Buffer MB Interrupt 27 Bit */ + uint32_t BUF26I:1; /* Buffer MB Interrupt 26 Bit */ + uint32_t BUF25I:1; /* Buffer MB Interrupt 25 Bit */ + uint32_t BUF24I:1; /* Buffer MB Interrupt 24 Bit */ + uint32_t BUF23I:1; /* Buffer MB Interrupt 23 Bit */ + uint32_t BUF22I:1; /* Buffer MB Interrupt 22 Bit */ + uint32_t BUF21I:1; /* Buffer MB Interrupt 21 Bit */ + uint32_t BUF20I:1; /* Buffer MB Interrupt 20 Bit */ + uint32_t BUF19I:1; /* Buffer MB Interrupt 19 Bit */ + uint32_t BUF18I:1; /* Buffer MB Interrupt 18 Bit */ + uint32_t BUF17I:1; /* Buffer MB Interrupt 17 Bit */ + uint32_t BUF16I:1; /* Buffer MB Interrupt 16 Bit */ + uint32_t BUF15I:1; /* Buffer MB Interrupt 15 Bit */ + uint32_t BUF14I:1; /* Buffer MB Interrupt 14 Bit */ + uint32_t BUF13I:1; /* Buffer MB Interrupt 13 Bit */ + uint32_t BUF12I:1; /* Buffer MB Interrupt 12 Bit */ + uint32_t BUF11I:1; /* Buffer MB Interrupt 11 Bit */ + uint32_t BUF10I:1; /* Buffer MB Interrupt 10 Bit */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF9I:1; /* Buffer MB Interrupt 9 Bit */ +#else + uint32_t BUF09I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF8I:1; /* Buffer MB Interrupt 8 Bit */ +#else + uint32_t BUF08I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF7I:1; /* Buffer MB Interrupt 7 Bit */ +#else + uint32_t BUF07I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF6I:1; /* Buffer MB Interrupt 6 Bit */ +#else + uint32_t BUF06I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF5I:1; /* Buffer MB Interrupt 5 Bit */ +#else + uint32_t BUF05I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF4I:1; /* Buffer MB Interrupt 4 Bit */ +#else + uint32_t BUF04I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF3I:1; /* Buffer MB Interrupt 3 Bit */ +#else + uint32_t BUF03I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF2I:1; /* Buffer MB Interrupt 2 Bit */ +#else + uint32_t BUF02I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF1I:1; /* Buffer MB Interrupt 1 Bit */ +#else + uint32_t BUF01I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF0I:1; /* Buffer MB Interrupt 0 Bit */ +#else + uint32_t BUF00I:1; /* deprecated name - please avoid */ +#endif + } B; + } FLEXCAN_IFLAG1_32B_tag; + + + /* Register layout for all registers MSG_CS... */ + + typedef union { /* Message Buffer Control and Status */ + uint32_t R; + struct { + uint32_t:4; + uint32_t CODE:4; /* Message Buffer Code */ + uint32_t:1; + uint32_t SRR:1; /* Substitute Remote Request */ + uint32_t IDE:1; /* ID Extended Bit */ + uint32_t RTR:1; /* Remote Transmission Request */ + uint32_t LENGTH:4; /* Length of Data in Bytes */ + uint32_t TIMESTAMP:16; /* Free-Running Counter Time Stamp */ + } B; + } FLEXCAN_MSG_CS_32B_tag; + + + /* Register layout for all registers MSG_ID... */ + + typedef union { /* Message Buffer Identifier Field */ + uint32_t R; + struct { + uint32_t PRIO:3; /* Local Priority */ + uint32_t STD_ID:11; + uint32_t EXT_ID:18; + } B; + } FLEXCAN_MSG_ID_32B_tag; + + + /* Register layout for all registers MSG_BYTE0_3... */ + + typedef union { /* Message Buffer Data Register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + } FLEXCAN_MSG_DATA_32B_tag; + + typedef union { + uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + uint32_t W[2]; /* Data buffer in words (32 bits) */ + uint32_t R[2]; /* Data buffer in words (32 bits) */ + } FLEXCAN_MSG_DATA2_32B_tag; + + /* Register layout for all registers MSG_BYTE4_7 matches xxx */ + + + /* Register layout for all registers RXIMR... */ + + typedef union { /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ + uint32_t R; + } FLEXCAN_RXIMR_32B_tag; + + + typedef struct FLEXCAN_MB_struct_tag { + + union { + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG_CS; /* relative offset: 0x0000 */ + FLEXCAN_MSG_CS_32B_tag CS; /* deprecated - please avoid */ + }; + union { + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG_ID; /* relative offset: 0x0004 */ + FLEXCAN_MSG_ID_32B_tag ID; /* deprecated - please avoid */ + }; + union { /* Message Buffer Data Register */ + + struct { + FLEXCAN_MSG_DATA_32B_tag MSG_BYTE0_3; /* relative offset: 0x0008 */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG_BYTE4_7; /* relative offset: 0x000C */ + }; + + FLEXCAN_MSG_DATA2_32B_tag DATA; /* relative offset: 0x000C */ + + }; + + } FLEXCAN_MB_tag; + + + typedef struct FLEXCAN_struct_tag { /* start of FLEXCAN_tag */ + /* MCR - Module Configuration Register */ + FLEXCAN_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ + union { + /* CTRL - Control Register */ + FLEXCAN_CTRL_32B_tag CTRL; /* offset: 0x0004 size: 32 bit */ + + FLEXCAN_CTRL_32B_tag CR; /* deprecated - please avoid */ + + }; + /* TIMER - Free Running Timer */ + FLEXCAN_TIMER_32B_tag TIMER; /* offset: 0x0008 size: 32 bit */ + int8_t FLEXCAN_reserved_000C[4]; + /* RXGMASK - Rx Global Mask Register */ + FLEXCAN_RXGMASK_32B_tag RXGMASK; /* offset: 0x0010 size: 32 bit */ + /* RX14MASK - Rx 14 Mask Register */ + FLEXCAN_RX14MASK_32B_tag RX14MASK; /* offset: 0x0014 size: 32 bit */ + /* RX15MASK - Rx 15 Mask Register */ + FLEXCAN_RX15MASK_32B_tag RX15MASK; /* offset: 0x0018 size: 32 bit */ + /* ECR - Error Counter Register */ + FLEXCAN_ECR_32B_tag ECR; /* offset: 0x001C size: 32 bit */ + /* ESR - Error and Status Register */ + FLEXCAN_ESR_32B_tag ESR; /* offset: 0x0020 size: 32 bit */ + union { + FLEXCAN_IMASK2_32B_tag IMRH; /* deprecated - please avoid */ + + /* IMASK2 - Interrupt Masks 2 Register */ + FLEXCAN_IMASK2_32B_tag IMASK2; /* offset: 0x0024 size: 32 bit */ + + }; + union { + FLEXCAN_IMASK1_32B_tag IMRL; /* deprecated - please avoid */ + + /* IMASK1 - Interrupt Masks 1 Register */ + FLEXCAN_IMASK1_32B_tag IMASK1; /* offset: 0x0028 size: 32 bit */ + + }; + union { + FLEXCAN_IFLAG2_32B_tag IFRH; /* deprecated - please avoid */ + + /* IFLAG2 - Interrupt Flags 2 Register */ + FLEXCAN_IFLAG2_32B_tag IFLAG2; /* offset: 0x002C size: 32 bit */ + + }; + union { + FLEXCAN_IFLAG1_32B_tag IFRL; /* deprecated - please avoid */ + + /* IFLAG1 - Interrupt Flags 1 Register */ + FLEXCAN_IFLAG1_32B_tag IFLAG1; /* offset: 0x0030 size: 32 bit */ + + }; + int8_t FLEXCAN_reserved_0034_C[76]; + union { + /* Register set MB */ + FLEXCAN_MB_tag MB[64]; /* offset: 0x0080 (0x0010 x 64) */ + + /* Alias name for MB */ + FLEXCAN_MB_tag BUF[64]; /* deprecated - please avoid */ + + struct { + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG0_CS; /* offset: 0x0080 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG0_ID; /* offset: 0x0084 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE0_3; /* offset: 0x0088 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE4_7; /* offset: 0x008C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG1_CS; /* offset: 0x0090 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG1_ID; /* offset: 0x0094 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE0_3; /* offset: 0x0098 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE4_7; /* offset: 0x009C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG2_CS; /* offset: 0x00A0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG2_ID; /* offset: 0x00A4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE0_3; /* offset: 0x00A8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE4_7; /* offset: 0x00AC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG3_CS; /* offset: 0x00B0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG3_ID; /* offset: 0x00B4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE0_3; /* offset: 0x00B8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE4_7; /* offset: 0x00BC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG4_CS; /* offset: 0x00C0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG4_ID; /* offset: 0x00C4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE0_3; /* offset: 0x00C8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE4_7; /* offset: 0x00CC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG5_CS; /* offset: 0x00D0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG5_ID; /* offset: 0x00D4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE0_3; /* offset: 0x00D8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE4_7; /* offset: 0x00DC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG6_CS; /* offset: 0x00E0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG6_ID; /* offset: 0x00E4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE0_3; /* offset: 0x00E8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE4_7; /* offset: 0x00EC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG7_CS; /* offset: 0x00F0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG7_ID; /* offset: 0x00F4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE0_3; /* offset: 0x00F8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE4_7; /* offset: 0x00FC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG8_CS; /* offset: 0x0100 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG8_ID; /* offset: 0x0104 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE0_3; /* offset: 0x0108 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE4_7; /* offset: 0x010C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG9_CS; /* offset: 0x0110 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG9_ID; /* offset: 0x0114 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE0_3; /* offset: 0x0118 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE4_7; /* offset: 0x011C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG10_CS; /* offset: 0x0120 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG10_ID; /* offset: 0x0124 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE0_3; /* offset: 0x0128 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE4_7; /* offset: 0x012C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG11_CS; /* offset: 0x0130 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG11_ID; /* offset: 0x0134 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE0_3; /* offset: 0x0138 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE4_7; /* offset: 0x013C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG12_CS; /* offset: 0x0140 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG12_ID; /* offset: 0x0144 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE0_3; /* offset: 0x0148 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE4_7; /* offset: 0x014C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG13_CS; /* offset: 0x0150 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG13_ID; /* offset: 0x0154 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE0_3; /* offset: 0x0158 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE4_7; /* offset: 0x015C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG14_CS; /* offset: 0x0160 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG14_ID; /* offset: 0x0164 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE0_3; /* offset: 0x0168 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE4_7; /* offset: 0x016C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG15_CS; /* offset: 0x0170 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG15_ID; /* offset: 0x0174 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE0_3; /* offset: 0x0178 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE4_7; /* offset: 0x017C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG16_CS; /* offset: 0x0180 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG16_ID; /* offset: 0x0184 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE0_3; /* offset: 0x0188 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE4_7; /* offset: 0x018C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG17_CS; /* offset: 0x0190 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG17_ID; /* offset: 0x0194 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE0_3; /* offset: 0x0198 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE4_7; /* offset: 0x019C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG18_CS; /* offset: 0x01A0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG18_ID; /* offset: 0x01A4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE0_3; /* offset: 0x01A8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE4_7; /* offset: 0x01AC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG19_CS; /* offset: 0x01B0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG19_ID; /* offset: 0x01B4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE0_3; /* offset: 0x01B8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE4_7; /* offset: 0x01BC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG20_CS; /* offset: 0x01C0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG20_ID; /* offset: 0x01C4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE0_3; /* offset: 0x01C8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE4_7; /* offset: 0x01CC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG21_CS; /* offset: 0x01D0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG21_ID; /* offset: 0x01D4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE0_3; /* offset: 0x01D8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE4_7; /* offset: 0x01DC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG22_CS; /* offset: 0x01E0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG22_ID; /* offset: 0x01E4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE0_3; /* offset: 0x01E8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE4_7; /* offset: 0x01EC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG23_CS; /* offset: 0x01F0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG23_ID; /* offset: 0x01F4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE0_3; /* offset: 0x01F8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE4_7; /* offset: 0x01FC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG24_CS; /* offset: 0x0200 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG24_ID; /* offset: 0x0204 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE0_3; /* offset: 0x0208 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE4_7; /* offset: 0x020C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG25_CS; /* offset: 0x0210 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG25_ID; /* offset: 0x0214 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE0_3; /* offset: 0x0218 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE4_7; /* offset: 0x021C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG26_CS; /* offset: 0x0220 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG26_ID; /* offset: 0x0224 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE0_3; /* offset: 0x0228 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE4_7; /* offset: 0x022C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG27_CS; /* offset: 0x0230 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG27_ID; /* offset: 0x0234 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE0_3; /* offset: 0x0238 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE4_7; /* offset: 0x023C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG28_CS; /* offset: 0x0240 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG28_ID; /* offset: 0x0244 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE0_3; /* offset: 0x0248 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE4_7; /* offset: 0x024C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG29_CS; /* offset: 0x0250 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG29_ID; /* offset: 0x0254 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE0_3; /* offset: 0x0258 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE4_7; /* offset: 0x025C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG30_CS; /* offset: 0x0260 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG30_ID; /* offset: 0x0264 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE0_3; /* offset: 0x0268 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE4_7; /* offset: 0x026C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG31_CS; /* offset: 0x0270 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG31_ID; /* offset: 0x0274 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE0_3; /* offset: 0x0278 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE4_7; /* offset: 0x027C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG32_CS; /* offset: 0x0280 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG32_ID; /* offset: 0x0284 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE0_3; /* offset: 0x0288 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE4_7; /* offset: 0x028C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG33_CS; /* offset: 0x0290 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG33_ID; /* offset: 0x0294 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE0_3; /* offset: 0x0298 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE4_7; /* offset: 0x029C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG34_CS; /* offset: 0x02A0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG34_ID; /* offset: 0x02A4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE0_3; /* offset: 0x02A8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE4_7; /* offset: 0x02AC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG35_CS; /* offset: 0x02B0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG35_ID; /* offset: 0x02B4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE0_3; /* offset: 0x02B8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE4_7; /* offset: 0x02BC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG36_CS; /* offset: 0x02C0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG36_ID; /* offset: 0x02C4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE0_3; /* offset: 0x02C8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE4_7; /* offset: 0x02CC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG37_CS; /* offset: 0x02D0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG37_ID; /* offset: 0x02D4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE0_3; /* offset: 0x02D8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE4_7; /* offset: 0x02DC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG38_CS; /* offset: 0x02E0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG38_ID; /* offset: 0x02E4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE0_3; /* offset: 0x02E8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE4_7; /* offset: 0x02EC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG39_CS; /* offset: 0x02F0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG39_ID; /* offset: 0x02F4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE0_3; /* offset: 0x02F8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE4_7; /* offset: 0x02FC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG40_CS; /* offset: 0x0300 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG40_ID; /* offset: 0x0304 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE0_3; /* offset: 0x0308 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE4_7; /* offset: 0x030C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG41_CS; /* offset: 0x0310 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG41_ID; /* offset: 0x0314 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE0_3; /* offset: 0x0318 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE4_7; /* offset: 0x031C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG42_CS; /* offset: 0x0320 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG42_ID; /* offset: 0x0324 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE0_3; /* offset: 0x0328 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE4_7; /* offset: 0x032C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG43_CS; /* offset: 0x0330 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG43_ID; /* offset: 0x0334 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE0_3; /* offset: 0x0338 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE4_7; /* offset: 0x033C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG44_CS; /* offset: 0x0340 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG44_ID; /* offset: 0x0344 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE0_3; /* offset: 0x0348 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE4_7; /* offset: 0x034C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG45_CS; /* offset: 0x0350 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG45_ID; /* offset: 0x0354 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE0_3; /* offset: 0x0358 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE4_7; /* offset: 0x035C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG46_CS; /* offset: 0x0360 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG46_ID; /* offset: 0x0364 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE0_3; /* offset: 0x0368 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE4_7; /* offset: 0x036C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG47_CS; /* offset: 0x0370 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG47_ID; /* offset: 0x0374 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE0_3; /* offset: 0x0378 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE4_7; /* offset: 0x037C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG48_CS; /* offset: 0x0380 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG48_ID; /* offset: 0x0384 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE0_3; /* offset: 0x0388 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE4_7; /* offset: 0x038C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG49_CS; /* offset: 0x0390 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG49_ID; /* offset: 0x0394 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE0_3; /* offset: 0x0398 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE4_7; /* offset: 0x039C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG50_CS; /* offset: 0x03A0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG50_ID; /* offset: 0x03A4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE0_3; /* offset: 0x03A8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE4_7; /* offset: 0x03AC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG51_CS; /* offset: 0x03B0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG51_ID; /* offset: 0x03B4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE0_3; /* offset: 0x03B8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE4_7; /* offset: 0x03BC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG52_CS; /* offset: 0x03C0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG52_ID; /* offset: 0x03C4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE0_3; /* offset: 0x03C8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE4_7; /* offset: 0x03CC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG53_CS; /* offset: 0x03D0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG53_ID; /* offset: 0x03D4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE0_3; /* offset: 0x03D8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE4_7; /* offset: 0x03DC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG54_CS; /* offset: 0x03E0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG54_ID; /* offset: 0x03E4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE0_3; /* offset: 0x03E8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE4_7; /* offset: 0x03EC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG55_CS; /* offset: 0x03F0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG55_ID; /* offset: 0x03F4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE0_3; /* offset: 0x03F8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE4_7; /* offset: 0x03FC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG56_CS; /* offset: 0x0400 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG56_ID; /* offset: 0x0404 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE0_3; /* offset: 0x0408 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE4_7; /* offset: 0x040C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG57_CS; /* offset: 0x0410 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG57_ID; /* offset: 0x0414 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE0_3; /* offset: 0x0418 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE4_7; /* offset: 0x041C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG58_CS; /* offset: 0x0420 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG58_ID; /* offset: 0x0424 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE0_3; /* offset: 0x0428 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE4_7; /* offset: 0x042C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG59_CS; /* offset: 0x0430 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG59_ID; /* offset: 0x0434 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE0_3; /* offset: 0x0438 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE4_7; /* offset: 0x043C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG60_CS; /* offset: 0x0440 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG60_ID; /* offset: 0x0444 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE0_3; /* offset: 0x0448 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE4_7; /* offset: 0x044C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG61_CS; /* offset: 0x0450 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG61_ID; /* offset: 0x0454 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE0_3; /* offset: 0x0458 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE4_7; /* offset: 0x045C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG62_CS; /* offset: 0x0460 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG62_ID; /* offset: 0x0464 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE0_3; /* offset: 0x0468 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE4_7; /* offset: 0x046C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG63_CS; /* offset: 0x0470 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG63_ID; /* offset: 0x0474 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE0_3; /* offset: 0x0478 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE4_7; /* offset: 0x047C size: 32 bit */ + }; + + }; + int8_t FLEXCAN_reserved_0480_C[1024]; + union { + /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ + FLEXCAN_RXIMR_32B_tag RXIMR[64]; /* offset: 0x0880 (0x0004 x 64) */ + + struct { + /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ + FLEXCAN_RXIMR_32B_tag RXIMR0; /* offset: 0x0880 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR1; /* offset: 0x0884 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR2; /* offset: 0x0888 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR3; /* offset: 0x088C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR4; /* offset: 0x0890 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR5; /* offset: 0x0894 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR6; /* offset: 0x0898 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR7; /* offset: 0x089C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR8; /* offset: 0x08A0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR9; /* offset: 0x08A4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR10; /* offset: 0x08A8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR11; /* offset: 0x08AC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR12; /* offset: 0x08B0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR13; /* offset: 0x08B4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR14; /* offset: 0x08B8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR15; /* offset: 0x08BC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR16; /* offset: 0x08C0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR17; /* offset: 0x08C4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR18; /* offset: 0x08C8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR19; /* offset: 0x08CC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR20; /* offset: 0x08D0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR21; /* offset: 0x08D4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR22; /* offset: 0x08D8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR23; /* offset: 0x08DC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR24; /* offset: 0x08E0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR25; /* offset: 0x08E4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR26; /* offset: 0x08E8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR27; /* offset: 0x08EC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR28; /* offset: 0x08F0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR29; /* offset: 0x08F4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR30; /* offset: 0x08F8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR31; /* offset: 0x08FC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR32; /* offset: 0x0900 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR33; /* offset: 0x0904 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR34; /* offset: 0x0908 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR35; /* offset: 0x090C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR36; /* offset: 0x0910 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR37; /* offset: 0x0914 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR38; /* offset: 0x0918 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR39; /* offset: 0x091C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR40; /* offset: 0x0920 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR41; /* offset: 0x0924 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR42; /* offset: 0x0928 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR43; /* offset: 0x092C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR44; /* offset: 0x0930 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR45; /* offset: 0x0934 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR46; /* offset: 0x0938 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR47; /* offset: 0x093C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR48; /* offset: 0x0940 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR49; /* offset: 0x0944 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR50; /* offset: 0x0948 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR51; /* offset: 0x094C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR52; /* offset: 0x0950 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR53; /* offset: 0x0954 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR54; /* offset: 0x0958 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR55; /* offset: 0x095C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR56; /* offset: 0x0960 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR57; /* offset: 0x0964 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR58; /* offset: 0x0968 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR59; /* offset: 0x096C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR60; /* offset: 0x0970 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR61; /* offset: 0x0974 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR62; /* offset: 0x0978 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR63; /* offset: 0x097C size: 32 bit */ + }; + + }; + } FLEXCAN_tag; + + +#define FLEXCAN_A (*(volatile FLEXCAN_tag *) 0xFFFC0000UL) +#define FLEXCAN_B (*(volatile FLEXCAN_tag *) 0xFFFC4000UL) + + + +/****************************************************************/ +/* */ +/* Module: DMA_CH_MUX */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers CHCONFIG... */ + + typedef union { /* CHCONFIG[0-15] - Channel Configuration Registers */ + uint8_t R; + struct { + uint8_t ENBL:1; /* DMA Channel Enable */ + uint8_t TRIG:1; /* DMA Channel Trigger Enable */ + uint8_t SOURCE:6; /* DMA Channel Source */ + } B; + } DMA_CH_MUX_CHCONFIG_8B_tag; + + + + typedef struct DMA_CH_MUX_struct_tag { /* start of DMA_CH_MUX_tag */ + union { + /* CHCONFIG[0-15] - Channel Configuration Registers */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG[16]; /* offset: 0x0000 (0x0001 x 16) */ + + struct { + /* CHCONFIG[0-15] - Channel Configuration Registers */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG0; /* offset: 0x0000 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG1; /* offset: 0x0001 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG2; /* offset: 0x0002 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG3; /* offset: 0x0003 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG4; /* offset: 0x0004 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG5; /* offset: 0x0005 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG6; /* offset: 0x0006 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG7; /* offset: 0x0007 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG8; /* offset: 0x0008 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG9; /* offset: 0x0009 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG10; /* offset: 0x000A size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG11; /* offset: 0x000B size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG12; /* offset: 0x000C size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG13; /* offset: 0x000D size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG14; /* offset: 0x000E size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG15; /* offset: 0x000F size: 8 bit */ + }; + + }; + } DMA_CH_MUX_tag; + + +#define DMA_CH_MUX (*(volatile DMA_CH_MUX_tag *) 0xFFFDC000UL) + + + +/****************************************************************/ +/* */ +/* Module: FR */ +/* */ +/****************************************************************/ + + typedef union { /* Module Version Number */ + uint16_t R; + struct { + uint16_t CHIVER:8; /* VERSION NUMBER OF CHI */ + uint16_t PEVER:8; /* VERSION NUMBER OF PE */ + } B; + } FR_MVR_16B_tag; + + typedef union { /* Module Configuration Register */ + uint16_t R; + struct { + uint16_t MEN:1; /* Module Enable */ + uint16_t SBFF:1; /* System Bus Failure Freeze */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t SCM:1; /* single channel device mode */ +#else + uint16_t SCMD:1; /* deprecated name - please avoid */ +#endif + uint16_t CHB:1; /* Channel B enable */ + uint16_t CHA:1; /* channel A enable */ + uint16_t SFFE:1; /* Sync. frame filter Enable */ + uint16_t ECCE:1; /* ECC Functionlity Enable */ + uint16_t TMODER:1; /* Functional Test mode */ + uint16_t FUM:1; /* FIFO Update Mode */ + uint16_t FAM:1; /* FIFO Address Mode */ + uint16_t:1; + uint16_t CLKSEL:1; /* Protocol Engine clock source select */ + uint16_t BITRATE:3; /* Bus bit rate */ + uint16_t:1; + } B; + } FR_MCR_16B_tag; + + typedef union { /* SYSTEM MEMORY BASE ADD HIGH REG */ + uint16_t R; + struct { + uint16_t SMBA_31_16:16; /* SYS_MEM_BASE_ADDR[31:16] */ + } B; + } FR_SYMBADHR_16B_tag; + + typedef union { /* SYSTEM MEMORY BASE ADD LOW REG */ + uint16_t R; + struct { + uint16_t SMBA_15_4:12; /* SYS_MEM_BASE_ADDR[15:4] */ + uint16_t:4; + } B; + } FR_SYMBADLR_16B_tag; + + typedef union { /* STROBE SIGNAL CONTROL REGISTER */ + uint16_t R; + struct { + uint16_t WMD:1; /* DEFINES WRITE MODE OF REG */ + uint16_t:3; + uint16_t SEL:4; /* STROBE SIGNSL SELECT */ + uint16_t:3; + uint16_t ENB:1; /* STROBE SIGNAL ENABLE */ + uint16_t:2; + uint16_t STBPSEL:2; /* STROBE PORT SELECT */ + } B; + } FR_STBSCR_16B_tag; + + typedef union { /* MESSAGE BUFFER DATA SIZE REGISTER */ + uint16_t R; + struct { + uint16_t:1; + uint16_t MBSEG2DS:7; /* MESSAGE BUFFER SEGMENT 2 DATA SIZE */ + uint16_t:1; + uint16_t MBSEG1DS:7; /* MESSAGE BUFFER SEGMENT 1 DATA SIZE */ + } B; + } FR_MBDSR_16B_tag; + + typedef union { /* MESS. BUFFER SEG. SIZE & UTILISATION REG */ + uint16_t R; + struct { + uint16_t:2; + uint16_t LAST_MB_SEG1:6; /* LAST MESS BUFFER IN SEG 1 */ + uint16_t:2; + uint16_t LAST_MB_UTIL:6; /* LAST MESSAGE BUFFER UTILISED */ + } B; + } FR_MBSSUTR_16B_tag; + + typedef union { /* PE DRAM ACCESS REGISTER */ + uint16_t R; + struct { + uint16_t INST:4; /* PE DRAM ACCESS INSTRUCTION */ + uint16_t ADDR:11; /* PE DRAM ACCESS ADDRESS */ + uint16_t DAD:1; /* PE DRAM ACCESS DONE */ + } B; + } FR_PEDRAR_16B_tag; + + typedef union { /* PE DRAM DATA REGISTER */ + uint16_t R; + struct { + uint16_t DATA:16; /* DATA TO BE READ OR WRITTEN */ + } B; + } FR_PEDRDR_16B_tag; + + typedef union { /* PROTOCOL OPERATION CONTROL REG */ + uint16_t R; + struct { + uint16_t WME:1; /* WRITE MODE EXTERNAL CORRECTION */ + uint16_t:3; + uint16_t EOC_AP:2; /* EXTERNAL OFFSET CORRECTION APPLICATION */ + uint16_t ERC_AP:2; /* EXTERNAL RATE CORRECTION APPLICATION */ + uint16_t BSY:1; /* PROTOCOL CONTROL COMMAND WRITE BUSY */ + uint16_t:3; + uint16_t POCCMD:4; /* PROTOCOL CONTROL COMMAND */ + } B; + } FR_POCR_16B_tag; + + typedef union { /* GLOBAL INTERRUPT FLAG & ENABLE REG */ + uint16_t R; + struct { + uint16_t MIF:1; /* MODULE INTERRUPT FLAG */ + uint16_t PRIF:1; /* PROTOCOL INTERRUPT FLAG */ + uint16_t CHIF:1; /* CHI INTERRUPT FLAG */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t WUPIF:1; /* WAKEUP INTERRUPT FLAG */ +#else + uint16_t WKUPIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FAFBIF:1; /* RECEIVE FIFO CHANNEL B ALMOST FULL INTERRUPT FLAG */ +#else + uint16_t FNEBIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FAFAIF:1; /* RECEIVE FIFO CHANNEL A ALMOST FULL INTERRUPT FLAG */ +#else + uint16_t FNEAIF:1; /* deprecated name - please avoid */ +#endif + uint16_t RBIF:1; /* RECEIVE MESSAGE BUFFER INTERRUPT FLAG */ + uint16_t TBIF:1; /* TRANSMIT BUFFER INTERRUPT FLAG */ + uint16_t MIE:1; /* MODULE INTERRUPT ENABLE */ + uint16_t PRIE:1; /* PROTOCOL INTERRUPT ENABLE */ + uint16_t CHIE:1; /* CHI INTERRUPT ENABLE */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t WUPIE:1; /* WAKEUP INTERRUPT ENABLE */ +#else + uint16_t WKUPIE:1; /* deprecated name - please avoid */ +#endif + uint16_t FNEBIE:1; /* RECEIVE FIFO CHANNEL B NOT EMPTY INTERRUPT ENABLE */ + uint16_t FNEAIE:1; /* RECEIVE FIFO CHANNEL A NOT EMPTY INTERRUPT ENABLE */ + uint16_t RBIE:1; /* RECEIVE BUFFER INTERRUPT ENABLE */ + uint16_t TBIE:1; /* TRANSMIT BUFFER INTERRUPT ENABLE */ + } B; + } FR_GIFER_16B_tag; + + typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 0 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t FATL_IF:1; /* FATAL PROTOCOL ERROR INTERRUPT FLAG */ +#else + uint16_t FATLIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t INTL_IF:1; /* INTERNAL PROTOCOL ERROR INTERRUPT FLAG */ +#else + uint16_t INTLIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t ILCF_IF:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT FLAG */ +#else + uint16_t ILCFIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CSA_IF:1; /* COLDSTART ABORT INTERRUPT FLAG */ +#else + uint16_t CSAIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MRC_IF:1; /* MISSING RATE CORRECTION INTERRUPT FLAG */ +#else + uint16_t MRCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MOC_IF:1; /* MISSING OFFSET CORRECTION INTERRUPT FLAG */ +#else + uint16_t MOCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CCL_IF:1; /* CLOCK CORRECTION LIMIT REACHED INTERRUPT FLAG */ +#else + uint16_t CCLIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MXS_IF:1; /* MAX SYNC FRAMES DETECTED INTERRUPT FLAG */ +#else + uint16_t MXSIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MTX_IF:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT FLAG */ +#else + uint16_t MTXIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t LTXB_IF:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT FLAG */ +#else + uint16_t LTXBIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t LTXA_IF:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT FLAG */ +#else + uint16_t LTXAIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TBVB_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT FLAG */ +#else + uint16_t TBVBIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TBVA_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT FLAG */ +#else + uint16_t TBVAIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TI2_IF:1; /* TIMER 2 EXPIRED INTERRUPT FLAG */ +#else + uint16_t TI2IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TI1_IF:1; /* TIMER 1 EXPIRED INTERRUPT FLAG */ +#else + uint16_t TI1IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CYS_IF:1; /* CYCLE START INTERRUPT FLAG */ +#else + uint16_t CYSIF:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_PIFR0_16B_tag; + + typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 1 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t EMC_IF:1; /* ERROR MODE CHANGED INTERRUPT FLAG */ +#else + uint16_t EMCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t IPC_IF:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT FLAG */ +#else + uint16_t IPCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t PECF_IF:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT FLAG */ +#else + uint16_t PECFIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t PSC_IF:1; /* PROTOCOL STATE CHANGED INTERRUPT FLAG */ +#else + uint16_t PSCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SSI3_IF:1; /* SLOT STATUS COUNTER 3 INCREMENTED INTERRUPT FLAG */ +#else + uint16_t SSI3IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SSI2_IF:1; /* SLOT STATUS COUNTER 2 INCREMENTED INTERRUPT FLAG */ +#else + uint16_t SSI2IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SSI1_IF:1; /* SLOT STATUS COUNTER 1 INCREMENTED INTERRUPT FLAG */ +#else + uint16_t SSI1IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SSI0_IF:1; /* SLOT STATUS COUNTER 0 INCREMENTED INTERRUPT FLAG */ +#else + uint16_t SSI0IF:1; /* deprecated name - please avoid */ +#endif + uint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + uint16_t EVT_IF:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT FLAG */ +#else + uint16_t EVTIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t ODT_IF:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT FLAG */ +#else + uint16_t ODTIF:1; /* deprecated name - please avoid */ +#endif + uint16_t:4; + } B; + } FR_PIFR1_16B_tag; + + typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t FATL_IE:1; /* FATAL PROTOCOL ERROR INTERRUPT ENABLE */ +#else + uint16_t FATLIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t INTL_IE:1; /* INTERNAL PROTOCOL ERROR INTERRUPT ENABLE */ +#else + uint16_t INTLIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t ILCF_IE:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT ENABLE */ +#else + uint16_t ILCFIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CSA_IE:1; /* COLDSTART ABORT INTERRUPT ENABLE */ +#else + uint16_t CSAIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MRC_IE:1; /* MISSING RATE CORRECTION INTERRUPT ENABLE */ +#else + uint16_t MRCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MOC_IE:1; /* MISSING OFFSET CORRECTION INTERRUPT ENABLE */ +#else + uint16_t MOCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CCL_IE:1; /* CLOCK CORRECTION LIMIT REACHED */ +#else + uint16_t CCLIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MXS_IE:1; /* MAX SYNC FRAMES DETECTED INTERRUPT ENABLE */ +#else + uint16_t MXSIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MTX_IE:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT ENABLE */ +#else + uint16_t MTXIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t LTXB_IE:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT ENABLE */ +#else + uint16_t LTXBIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t LTXA_IE:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT ENABLE */ +#else + uint16_t LTXAIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TBVB_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT ENABLE */ +#else + uint16_t TBVBIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TBVA_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT ENABLE */ +#else + uint16_t TBVAIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TI2_IE:1; /* TIMER 2 EXPIRED INTERRUPT ENABLE */ +#else + uint16_t TI2IE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TI1_IE:1; /* TIMER 1 EXPIRED INTERRUPT ENABLE */ +#else + uint16_t TI1IE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CYS_IE:1; /* CYCLE START INTERRUPT ENABLE */ +#else + uint16_t CYSIE:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_PIER0_16B_tag; + + typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t EMC_IE:1; /* ERROR MODE CHANGED INTERRUPT Enable */ +#else + uint16_t EMCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t IPC_IE:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT Enable */ +#else + uint16_t IPCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t PECF_IE:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT Enable */ +#else + uint16_t PECFIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t PSC_IE:1; /* PROTOCOL STATE CHANGED INTERRUPT Enable */ +#else + uint16_t PSCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SSI_3_0_IE:4; /* SLOT STATUS COUNTER INCREMENTED INTERRUPT Enable */ +#else + uint16_t SSI3IE:1; + uint16_t SSI2IE:1; + uint16_t SSI1IE:1; + uint16_t SSI0IE:1; +#endif + + uint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + uint16_t EVT_IE:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT Enable */ +#else + uint16_t EVTIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t ODT_IE:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT Enable */ +#else + uint16_t ODTIE:1; /* deprecated name - please avoid */ +#endif + uint16_t:4; + } B; + } FR_PIER1_16B_tag; + + typedef union { /* CHI ERROR FLAG REGISTER */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t FRLB_EF:1; /* FRAME LOST CHANNEL B ERROR FLAG */ +#else + uint16_t FRLBEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FRLA_EF:1; /* FRAME LOST CHANNEL A ERROR FLAG */ +#else + uint16_t FRLAEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t PCMI_EF:1; /* PROTOCOL COMMAND IGNORED ERROR FLAG */ +#else + uint16_t PCMIEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FOVB_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL B ERROR FLAG */ +#else + uint16_t FOVBEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FOVA_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL A ERROR FLAG */ +#else + uint16_t FOVAEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MBS_EF:1; /* MESSAGE BUFFER SEARCH ERROR FLAG */ +#else + uint16_t MSBEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MBU_EF:1; /* MESSAGE BUFFER UTILIZATION ERROR FLAG */ +#else + uint16_t MBUEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t LCK_EF:1; /* LOCK ERROR FLAG */ +#else + uint16_t LCKEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t DBL_EF:1; /* DOUBLE TRANSMIT MESSAGE BUFFER LOCK ERROR FLAG */ +#else + uint16_t DBLEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SBCF_EF:1; /* SYSTEM BUS COMMUNICATION FAILURE ERROR FLAG */ +#else + uint16_t SBCFEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FID_EF:1; /* FRAME ID ERROR FLAG */ +#else + uint16_t FIDEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t DPL_EF:1; /* DYNAMIC PAYLOAD LENGTH ERROR FLAG */ +#else + uint16_t DPLEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SPL_EF:1; /* STATIC PAYLOAD LENGTH ERROR FLAG */ +#else + uint16_t SPLEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t NML_EF:1; /* NETWORK MANAGEMENT LENGTH ERROR FLAG */ +#else + uint16_t NMLEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t NMF_EF:1; /* NETWORK MANAGEMENT FRAME ERROR FLAG */ +#else + uint16_t NMFEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t ILSA_EF:1; /* ILLEGAL SYSTEM MEMORY ACCESS ERROR FLAG */ +#else + uint16_t ILSAEF:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_CHIERFR_16B_tag; + + typedef union { /* Message Buffer Interrupt Vector Register */ + uint16_t R; + struct { + uint16_t:2; + uint16_t TBIVEC:6; /* Transmit Buffer Interrupt Vector */ + uint16_t:2; + uint16_t RBIVEC:6; /* Receive Buffer Interrupt Vector */ + } B; + } FR_MBIVEC_16B_tag; + + typedef union { /* Channel A Status Error Counter Register */ + uint16_t R; + struct { + uint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */ + } B; + } FR_CASERCR_16B_tag; + + typedef union { /* Channel B Status Error Counter Register */ + uint16_t R; + struct { + uint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */ + } B; + } FR_CBSERCR_16B_tag; + + typedef union { /* Protocol Status Register 0 */ + uint16_t R; + struct { + uint16_t ERRMODE:2; /* Error Mode */ + uint16_t SLOTMODE:2; /* Slot Mode */ + uint16_t:1; + uint16_t PROTSTATE:3; /* Protocol State */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t STARTUPSTATE:4; /* Startup State */ +#else + uint16_t SUBSTATE:4; /* deprecated name - please avoid */ +#endif + uint16_t WAKEUPSTATE:4; /* Wakeup Status */ + } B; + } FR_PSR0_16B_tag; + + typedef union { /* Protocol Status Register 1 */ + uint16_t R; + struct { + uint16_t CSAA:1; /* Coldstart Attempt Aborted Flag */ + uint16_t CSP:1; /* Leading Coldstart Path */ + uint16_t:1; + uint16_t REMCSAT:5; /* Remaining Coldstart Attempts */ + uint16_t CPN:1; /* Leading Coldstart Path Noise */ + uint16_t HHR:1; /* Host Halt Request Pending */ + uint16_t FRZ:1; /* Freeze Occurred */ + uint16_t APTAC:5; /* Allow Passive to Active Counter */ + } B; + } FR_PSR1_16B_tag; + + typedef union { /* Protocol Status Register 2 */ + uint16_t R; + struct { + uint16_t NBVB:1; /* NIT Boundary Violation on Channel B */ + uint16_t NSEB:1; /* NIT Syntax Error on Channel B */ + uint16_t STCB:1; /* Symbol Window Transmit Conflict on Channel B */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t SSVB:1; /* Symbol Window Boundary Violation on Channel B */ +#else + uint16_t SBVB:1; /* deprecated name - please avoid */ +#endif + uint16_t SSEB:1; /* Symbol Window Syntax Error on Channel B */ + uint16_t MTB:1; /* Media Access Test Symbol MTS Received on Channel B */ + uint16_t NBVA:1; /* NIT Boundary Violation on Channel A */ + uint16_t NSEA:1; /* NIT Syntax Error on Channel A */ + uint16_t STCA:1; /* Symbol Window Transmit Conflict on Channel A */ + uint16_t SBVA:1; /* Symbol Window Boundary Violation on Channel A */ + uint16_t SSEA:1; /* Symbol Window Syntax Error on Channel A */ + uint16_t MTA:1; /* Media Access Test Symbol MTS Received on Channel A */ + uint16_t CLKCORRFAILCNT:4; /* Clock Correction Failed Counter */ + } B; + } FR_PSR2_16B_tag; + + typedef union { /* Protocol Status Register 3 */ + uint16_t R; + struct { + uint16_t:2; + uint16_t WUB:1; /* Wakeup Symbol Received on Channel B */ + uint16_t ABVB:1; /* Aggregated Boundary Violation on Channel B */ + uint16_t AACB:1; /* Aggregated Additional Communication on Channel B */ + uint16_t ACEB:1; /* Aggregated Content Error on Channel B */ + uint16_t ASEB:1; /* Aggregated Syntax Error on Channel B */ + uint16_t AVFB:1; /* Aggregated Valid Frame on Channel B */ + uint16_t:2; + uint16_t WUA:1; /* Wakeup Symbol Received on Channel A */ + uint16_t ABVA:1; /* Aggregated Boundary Violation on Channel A */ + uint16_t AACA:1; /* Aggregated Additional Communication on Channel A */ + uint16_t ACEA:1; /* Aggregated Content Error on Channel A */ + uint16_t ASEA:1; /* Aggregated Syntax Error on Channel A */ + uint16_t AVFA:1; /* Aggregated Valid Frame on Channel A */ + } B; + } FR_PSR3_16B_tag; + + typedef union { /* Macrotick Counter Register */ + uint16_t R; + struct { + uint16_t:2; + uint16_t MTCT:14; /* Macrotick Counter */ + } B; + } FR_MTCTR_16B_tag; + + typedef union { /* Cycle Counter Register */ + uint16_t R; + struct { + uint16_t:10; + uint16_t CYCCNT:6; /* Cycle Counter */ + } B; + } FR_CYCTR_16B_tag; + + typedef union { /* Slot Counter Channel A Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t SLOTCNTA:11; /* Slot Counter Value for Channel A */ + } B; + } FR_SLTCTAR_16B_tag; + + typedef union { /* Slot Counter Channel B Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t SLOTCNTB:11; /* Slot Counter Value for Channel B */ + } B; + } FR_SLTCTBR_16B_tag; + + typedef union { /* Rate Correction Value Register */ + uint16_t R; + struct { + uint16_t RATECORR:16; /* Rate Correction Value */ + } B; + } FR_RTCORVR_16B_tag; + + typedef union { /* Offset Correction Value Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t OFFSETCORR:10; /* Offset Correction Value */ + } B; + } FR_OFCORVR_16B_tag; + + typedef union { /* Combined Interrupt Flag Register */ + uint16_t R; + struct { + uint16_t:8; +#ifndef USE_FIELD_ALIASES_FR + uint16_t MIF:1; /* Module Interrupt Flag */ +#else + uint16_t MIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t PRIF:1; /* Protocol Interrupt Flag */ +#else + uint16_t PRIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CHIF:1; /* CHI Interrupt Flag */ +#else + uint16_t CHIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t WUPIF:1; /* Wakeup Interrupt Flag */ +#else + uint16_t WUPIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FAFBIF:1; /* Receive FIFO channel B Almost Full Interrupt Flag */ +#else + uint16_t FNEBIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FAFAIF:1; /* Receive FIFO channel A Almost Full Interrupt Flag */ +#else + uint16_t FNEAIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t RBIF:1; /* Receive Message Buffer Interrupt Flag */ +#else + uint16_t RBIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TBIF:1; /* Transmit Message Buffer Interrupt Flag */ +#else + uint16_t TBIFR:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_CIFR_16B_tag; + + typedef union { /* System Memory Access Time-Out Register */ + uint16_t R; + struct { + uint16_t:8; + uint16_t TIMEOUT:8; /* Time-Out */ + } B; + } FR_SYMATOR_16B_tag; + + typedef union { /* Sync Frame Counter Register */ + uint16_t R; + struct { + uint16_t SFEVB:4; /* Sync Frames Channel B, even cycle */ + uint16_t SFEVA:4; /* Sync Frames Channel A, even cycle */ + uint16_t SFODB:4; /* Sync Frames Channel B, odd cycle */ + uint16_t SFODA:4; /* Sync Frames Channel A, odd cycle */ + } B; + } FR_SFCNTR_16B_tag; + + typedef union { /* Sync Frame Table Offset Register */ + uint16_t R; + struct { + uint16_t SFT_OFFSET_15_1:15; /* Sync Frame Table Offset */ + uint16_t:1; + } B; + } FR_SFTOR_16B_tag; + + typedef union { /* Sync Frame Table Configuration, Control, Status Register */ + uint16_t R; + struct { + uint16_t ELKT:1; /* Even Cycle Tables Lock/Unlock Trigger */ + uint16_t OLKT:1; /* Odd Cycle Tables Lock/Unlock Trigger */ + uint16_t CYCNUM:6; /* Cycle Number */ + uint16_t ELKS:1; /* Even Cycle Tables Lock Status */ + uint16_t OLKS:1; /* Odd Cycle Tables Lock Status */ + uint16_t EVAL:1; /* Even Cycle Tables Valid */ + uint16_t OVAL:1; /* Odd Cycle Tables Valid */ + uint16_t:1; + uint16_t OPT:1; /* One Pair Trigger */ + uint16_t SDVEN:1; /* Sync Frame Deviation Table Enable */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t SIVEN:1; /* Sync Frame ID Table Enable */ +#else + uint16_t SIDEN:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_SFTCCSR_16B_tag; + + typedef union { /* Sync Frame ID Rejection Filter */ + uint16_t R; + struct { + uint16_t:6; + uint16_t SYNFRID:10; /* Sync Frame Rejection ID */ + } B; + } FR_SFIDRFR_16B_tag; + + typedef union { /* Sync Frame ID Acceptance Filter Value Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t FVAL:10; /* Filter Value */ + } B; + } FR_SFIDAFVR_16B_tag; + + typedef union { /* Sync Frame ID Acceptance Filter Mask Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t FMSK:10; /* Filter Mask */ + } B; + } FR_SFIDAFMR_16B_tag; + + typedef union { /* Network Management Vector Register0 */ + uint16_t R; + struct { + uint16_t NMVP_15_8:8; /* Network Management Vector Part */ + uint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR0_16B_tag; + + typedef union { /* Network Management Vector Register1 */ + uint16_t R; + struct { + uint16_t NMVP_15_8:8; /* Network Management Vector Part */ + uint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR1_16B_tag; + + typedef union { /* Network Management Vector Register2 */ + uint16_t R; + struct { + uint16_t NMVP_15_8:8; /* Network Management Vector Part */ + uint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR2_16B_tag; + + typedef union { /* Network Management Vector Register3 */ + uint16_t R; + struct { + uint16_t NMVP_15_8:8; /* Network Management Vector Part */ + uint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR3_16B_tag; + + typedef union { /* Network Management Vector Register4 */ + uint16_t R; + struct { + uint16_t NMVP_15_8:8; /* Network Management Vector Part */ + uint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR4_16B_tag; + + typedef union { /* Network Management Vector Register5 */ + uint16_t R; + struct { + uint16_t NMVP_15_8:8; /* Network Management Vector Part */ + uint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR5_16B_tag; + + typedef union { /* Network Management Vector Length Register */ + uint16_t R; + struct { + uint16_t:12; + uint16_t NMVL:4; /* Network Management Vector Length */ + } B; + } FR_NMVLR_16B_tag; + + typedef union { /* Timer Configuration and Control Register */ + uint16_t R; + struct { + uint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + uint16_t T2_CFG:1; /* Timer T2 Configuration */ +#else + uint16_t T2CFG:1; /* Timer T2 Configuration */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t T2_REP:1; /* Timer T2 Repetitive Mode */ +#else + uint16_t T2REP:1; /* Timer T2 Configuration */ +#endif + uint16_t:1; + uint16_t T2SP:1; /* Timer T2 Stop */ + uint16_t T2TR:1; /* Timer T2 Trigger */ + uint16_t T2ST:1; /* Timer T2 State */ + uint16_t:3; +#ifndef USE_FIELD_ALIASES_FR + uint16_t T1_REP:1; /* Timer T1 Repetitive Mode */ +#else + uint16_t T1REP:1; +#endif + uint16_t:1; + uint16_t T1SP:1; /* Timer T1 Stop */ + uint16_t T1TR:1; /* Timer T1 Trigger */ + uint16_t T1ST:1; /* Timer T1 State */ + } B; + } FR_TICCR_16B_tag; + + typedef union { /* Timer 1 Cycle Set Register */ + uint16_t R; + struct { + uint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + uint16_t T1_CYC_VAL:6; /* Timer T1 Cycle Filter Value */ +#else + uint16_t TI1CYCVAL:1; /* Timer T1 Cycle Filter Value */ +#endif + uint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + uint16_t T1_CYC_MSK:6; /* Timer T1 Cycle Filter Mask */ +#else + uint16_t TI1CYCMSK:1; /* Timer T1 Cycle Filter Mask */ +#endif + } B; + } FR_TI1CYSR_16B_tag; + + typedef union { /* Timer 1 Macrotick Offset Register */ + uint16_t R; + struct { + uint16_t:2; + uint16_t T1_MTOFFSET:14; /* Timer 1 Macrotick Offset */ + } B; + } FR_TI1MTOR_16B_tag; + + typedef union { /* Timer 2 Configuration Register 0 */ + uint16_t R; + struct { + uint16_t:2; + uint16_t T2_CYC_VAL:6; /* Timer T2 Cycle Filter Value */ + uint16_t:2; + uint16_t T2_CYC_MSK:6; /* Timer T2 Cycle Filter Mask */ + } B; + } FR_TI2CR0_16B_tag; + + typedef union { /* Timer 2 Configuration Register 1 */ + uint16_t R; + struct { + uint16_t T2_MTCNT:16; /* Timer T2 Macrotick Offset */ + } B; + } FR_TI2CR1_16B_tag; + + typedef union { /* Slot Status Selection Register */ + uint16_t R; + struct { + uint16_t WMD:1; /* Write Mode */ + uint16_t:1; + uint16_t SEL:2; /* Selector */ + uint16_t:1; + uint16_t SLOTNUMBER:11; /* Slot Number */ + } B; + } FR_SSSR_16B_tag; + + typedef union { /* Slot Status Counter Condition Register */ + uint16_t R; + struct { + uint16_t WMD:1; /* Write Mode */ + uint16_t:1; + uint16_t SEL:2; /* Selector */ + uint16_t:1; + uint16_t CNTCFG:2; /* Counter Configuration */ + uint16_t MCY:1; /* Multi Cycle Selection */ + uint16_t VFR:1; /* Valid Frame Restriction */ + uint16_t SYF:1; /* Sync Frame Restriction */ + uint16_t NUF:1; /* Null Frame Restriction */ + uint16_t SUF:1; /* Startup Frame Restriction */ + uint16_t STATUSMASK:4; /* Slot Status Mask */ + } B; + } FR_SSCCR_16B_tag; + + typedef union { /* Slot Status Register0 */ + uint16_t R; + struct { + uint16_t VFB:1; /* Valid Frame on Channel B */ + uint16_t SYB:1; /* Sync Frame Indicator Channel B */ + uint16_t NFB:1; /* Null Frame Indicator Channel B */ + uint16_t SUB:1; /* Startup Frame Indicator Channel B */ + uint16_t SEB:1; /* Syntax Error on Channel B */ + uint16_t CEB:1; /* Content Error on Channel B */ + uint16_t BVB:1; /* Boundary Violation on Channel B */ + uint16_t TCB:1; /* Transmission Conflict on Channel B */ + uint16_t VFA:1; /* Valid Frame on Channel A */ + uint16_t SYA:1; /* Sync Frame Indicator Channel A */ + uint16_t NFA:1; /* Null Frame Indicator Channel A */ + uint16_t SUA:1; /* Startup Frame Indicator Channel A */ + uint16_t SEA:1; /* Syntax Error on Channel A */ + uint16_t CEA:1; /* Content Error on Channel A */ + uint16_t BVA:1; /* Boundary Violation on Channel A */ + uint16_t TCA:1; /* Transmission Conflict on Channel A */ + } B; + } FR_SSR_16B_tag; + + + + typedef union { /* Slot Status Counter Register0 */ + uint16_t R; + struct { + uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ + } B; + } FR_SSCR0_16B_tag; + + typedef union { /* Slot Status Counter Register1 */ + uint16_t R; + struct { + uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ + } B; + } FR_SSCR1_16B_tag; + + typedef union { /* Slot Status Counter Register2 */ + uint16_t R; + struct { + uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ + } B; + } FR_SSCR2_16B_tag; + + typedef union { /* Slot Status Counter Register3 */ + uint16_t R; + struct { + uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ + } B; + } FR_SSCR3_16B_tag; + + typedef union { /* MTS A Configuration Register */ + uint16_t R; + struct { + uint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */ + uint16_t:1; + uint16_t CYCCNTMSK:6; /* Cycle Counter Mask */ + uint16_t:2; + uint16_t CYCCNTVAL:6; /* Cycle Counter Value */ + } B; + } FR_MTSACFR_16B_tag; + + typedef union { /* MTS B Configuration Register */ + uint16_t R; + struct { + uint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */ + uint16_t:1; + uint16_t CYCCNTMSK:6; /* Cycle Counter Mask */ + uint16_t:2; + uint16_t CYCCNTVAL:6; /* Cycle Counter Value */ + } B; + } FR_MTSBCFR_16B_tag; + + typedef union { /* Receive Shadow Buffer Index Register */ + uint16_t R; + struct { + uint16_t WMD:1; /* Write Mode */ + uint16_t:1; + uint16_t SEL:2; /* Selector */ + uint16_t:5; + uint16_t RSBIDX:7; /* Receive Shadow Buffer Index */ + } B; + } FR_RSBIR_16B_tag; + + typedef union { /* Receive FIFO Watermark and Selection Register */ + uint16_t R; + struct { + uint16_t WM:8; /* Watermark Value */ + uint16_t:7; + uint16_t SEL:1; /* Select */ + } B; + } FR_RFWMSR_16B_tag; + + typedef union { /* Receive FIFO Start Index Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t SIDX:10; /* Start Index */ + } B; + } FR_RF_RFSIR_16B_tag; + + typedef union { /* Receive FIFO Depth and Size Register */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t FIFO_DEPTH:8; /* FIFO Depth */ +#else + uint16_t FIFODEPTH:8; /* deprecated name - please avoid */ +#endif + uint16_t:1; +#ifndef USE_FIELD_ALIASES_FR + uint16_t ENTRY_SIZE:7; /* Entry Size */ +#else + uint16_t ENTRYSIZE:7; /* deprecated name - please avoid */ +#endif + } B; + } FR_RFDSR_16B_tag; + + typedef union { /* Receive FIFO A Read Index Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t RDIDX:10; /* Read Index */ + } B; + } FR_RFARIR_16B_tag; + + typedef union { /* Receive FIFO B Read Index Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t RDIDX:10; /* Read Index */ + } B; + } FR_RFBRIR_16B_tag; + + typedef union { /* Receive FIFO Message ID Acceptance Filter Value Register */ + uint16_t R; + struct { + uint16_t MIDAFVAL:16; /* Message ID Acceptance Filter Value */ + } B; + } FR_RFMIDAFVR_16B_tag; + + typedef union { /* Receive FIFO Message ID Acceptance Filter Mask Register */ + uint16_t R; + struct { + uint16_t MIDAFMSK:16; /* Message ID Acceptance Filter Mask */ + } B; + } FR_RFMIDAFMR_16B_tag; + + typedef union { /* Receive FIFO Frame ID Rejection Filter Value Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t FIDRFVAL:11; /* Frame ID Rejection Filter Value */ + } B; + } FR_RFFIDRFVR_16B_tag; + + typedef union { /* Receive FIFO Frame ID Rejection Filter Mask Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t FIDRFMSK:11; /* Frame ID Rejection Filter Mask */ + } B; + } FR_RFFIDRFMR_16B_tag; + + typedef union { /* Receive FIFO Range Filter Configuration Register */ + uint16_t R; + struct { + uint16_t WMD:1; /* Write Mode */ + uint16_t IBD:1; /* Interval Boundary */ + uint16_t SEL:2; /* Filter Selector */ + uint16_t:1; + uint16_t SID:11; /* Slot ID */ + } B; + } FR_RFRFCFR_16B_tag; + + typedef union { /* Receive FIFO Range Filter Control Register */ + uint16_t R; + struct { + uint16_t:4; + uint16_t F3MD:1; /* Range Filter 3 Mode */ + uint16_t F2MD:1; /* Range Filter 2 Mode */ + uint16_t F1MD:1; /* Range Filter 1 Mode */ + uint16_t F0MD:1; /* Range Filter 0 Mode */ + uint16_t:4; + uint16_t F3EN:1; /* Range Filter 3 Enable */ + uint16_t F2EN:1; /* Range Filter 2 Enable */ + uint16_t F1EN:1; /* Range Filter 1 Enable */ + uint16_t F0EN:1; /* Range Filter 0 Enable */ + } B; + } FR_RFRFCTR_16B_tag; + + typedef union { /* Last Dynamic Transmit Slot Channel A Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t LASTDYNTXSLOTA:11; /* Last Dynamic Transmission Slot Channel A */ + } B; + } FR_LDTXSLAR_16B_tag; + + typedef union { /* Last Dynamic Transmit Slot Channel B Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t LASTDYNTXSLOTB:11; /* Last Dynamic Transmission Slot Channel B */ + } B; + } FR_LDTXSLBR_16B_tag; + + typedef union { /* Protocol Configuration Register 0 */ + uint16_t R; + struct { + uint16_t ACTION_POINT_OFFSET:6; /* gdActionPointOffset - 1 */ + uint16_t STATIC_SLOT_LENGTH:10; /* gdStaticSlot */ + } B; + } FR_PCR0_16B_tag; + + typedef union { /* Protocol Configuration Register 1 */ + uint16_t R; + struct { + uint16_t:2; + uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; /* gMacroPerCycle - gdStaticSlot */ + } B; + } FR_PCR1_16B_tag; + + typedef union { /* Protocol Configuration Register 2 */ + uint16_t R; + struct { + uint16_t MINISLOT_AFTER_ACTION_POINT:6; /* gdMinislot - gdMinislotActionPointOffset - 1 */ + uint16_t NUMBER_OF_STATIC_SLOTS:10; /* gNumberOfStaticSlots */ + } B; + } FR_PCR2_16B_tag; + + typedef union { /* Protocol Configuration Register 3 */ + uint16_t R; + struct { + uint16_t WAKEUP_SYMBOL_RX_LOW:6; /* gdWakeupSymbolRxLow */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t MINISLOT_ACTION_POINT_OFFSET_4_0:5; /* gdMinislotActionPointOffset - 1 */ +#else + uint16_t MINISLOT_ACTION_POINT_OFFSET:5; /* deprecated name - please avoid */ +#endif + uint16_t COLDSTART_ATTEMPTS:5; /* gColdstartAttempts */ + } B; + } FR_PCR3_16B_tag; + + typedef union { /* Protocol Configuration Register 4 */ + uint16_t R; + struct { + uint16_t CAS_RX_LOW_MAX:7; /* gdCASRxLowMax - 1 */ + uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; /* gdWakeupSymbolRxWindow */ + } B; + } FR_PCR4_16B_tag; + + typedef union { /* Protocol Configuration Register 5 */ + uint16_t R; + struct { + uint16_t TSS_TRANSMITTER:4; /* gdTSSTransmitter */ + uint16_t WAKEUP_SYMBOL_TX_LOW:6; /* gdWakeupSymbolTxLow */ + uint16_t WAKEUP_SYMBOL_RX_IDLE:6; /* gdWakeupSymbolRxIdle */ + } B; + } FR_PCR5_16B_tag; + + typedef union { /* Protocol Configuration Register 6 */ + uint16_t R; + struct { + uint16_t:1; + uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; /* gdSymbolWindow - gdActionPointOffset - 1 */ + uint16_t MACRO_INITIAL_OFFSET_A:7; /* pMacroInitialOffset[A] */ + } B; + } FR_PCR6_16B_tag; + + typedef union { /* Protocol Configuration Register 7 */ + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_B:9; /* pDecodingCorrection + pDelayCompensation[B] + 2 */ + uint16_t MICRO_PER_MACRO_NOM_HALF:7; /* round(pMicroPerMacroNom / 2) */ + } B; + } FR_PCR7_16B_tag; + + typedef union { /* Protocol Configuration Register 8 */ + uint16_t R; + struct { + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; /* gMaxWithoutClockCorrectionFatal */ + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; /* gMaxWithoutClockCorrectionPassive */ + uint16_t WAKEUP_SYMBOL_TX_IDLE:8; /* gdWakeupSymbolTxIdle */ + } B; + } FR_PCR8_16B_tag; + + typedef union { /* Protocol Configuration Register 9 */ + uint16_t R; + struct { + uint16_t MINISLOT_EXISTS:1; /* gNumberOfMinislots!=0 */ + uint16_t SYMBOL_WINDOW_EXISTS:1; /* gdSymbolWindow!=0 */ + uint16_t OFFSET_CORRECTION_OUT:14; /* pOffsetCorrectionOut */ + } B; + } FR_PCR9_16B_tag; + + typedef union { /* Protocol Configuration Register 10 */ + uint16_t R; + struct { + uint16_t SINGLE_SLOT_ENABLED:1; /* pSingleSlotEnabled */ + uint16_t WAKEUP_CHANNEL:1; /* pWakeupChannel */ + uint16_t MACRO_PER_CYCLE:14; /* pMicroPerCycle */ + } B; + } FR_PCR10_16B_tag; + + typedef union { /* Protocol Configuration Register 11 */ + uint16_t R; + struct { + uint16_t KEY_SLOT_USED_FOR_STARTUP:1; /* pKeySlotUsedForStartup */ + uint16_t KEY_SLOT_USED_FOR_SYNC:1; /* pKeySlotUsedForSync */ + uint16_t OFFSET_CORRECTION_START:14; /* gOffsetCorrectionStart */ + } B; + } FR_PCR11_16B_tag; + + typedef union { /* Protocol Configuration Register 12 */ + uint16_t R; + struct { + uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; /* pAllowPassiveToActive */ + uint16_t KEY_SLOT_HEADER_CRC:11; /* header CRC for key slot */ + } B; + } FR_PCR12_16B_tag; + + typedef union { /* Protocol Configuration Register 13 */ + uint16_t R; + struct { + uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; /* max(gdActionPointOffset,gdMinislotActionPointOffset) - 1 */ + uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; /* gdStaticSlot - gdActionPointOffset - 1 */ + } B; + } FR_PCR13_16B_tag; + + typedef union { /* Protocol Configuration Register 14 */ + uint16_t R; + struct { + uint16_t RATE_CORRECTION_OUT:11; /* pRateCorrectionOut */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t LISTEN_TIMEOUT_20_16:5; /* pdListenTimeout - 1 */ +#else + uint16_t LISTEN_TIMEOUT_H:5; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR14_16B_tag; + + typedef union { /* Protocol Configuration Register 15 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t LISTEN_TIMEOUT_15_0:16; /* pdListenTimeout - 1 */ +#else + uint16_t LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR15_16B_tag; + + typedef union { /* Protocol Configuration Register 16 */ + uint16_t R; + struct { + uint16_t MACRO_INITIAL_OFFSET_B:7; /* pMacroInitialOffset[B] */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t NOISE_LISTEN_TIMEOUT_24_16:9; /* (gListenNoise * pdListenTimeout) - 1 */ +#else + uint16_t NOISE_LISTEN_TIMEOUT_H:9; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR16_16B_tag; + + typedef union { /* Protocol Configuration Register 17 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t NOISE_LISTEN_TIMEOUT_15_0:16; /* (gListenNoise * pdListenTimeout) - 1 */ +#else + uint16_t NOISE_LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR17_16B_tag; + + typedef union { /* Protocol Configuration Register 18 */ + uint16_t R; + struct { + uint16_t WAKEUP_PATTERN:6; /* pWakeupPattern */ + uint16_t KEY_SLOT_ID:10; /* pKeySlotId */ + } B; + } FR_PCR18_16B_tag; + + typedef union { /* Protocol Configuration Register 19 */ + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_A:9; /* pDecodingCorrection + pDelayCompensation[A] + 2 */ + uint16_t PAYLOAD_LENGTH_STATIC:7; /* gPayloadLengthStatic */ + } B; + } FR_PCR19_16B_tag; + + typedef union { /* Protocol Configuration Register 20 */ + uint16_t R; + struct { + uint16_t MICRO_INITIAL_OFFSET_B:8; /* pMicroInitialOffset[B] */ + uint16_t MICRO_INITIAL_OFFSET_A:8; /* pMicroInitialOffset[A] */ + } B; + } FR_PCR20_16B_tag; + + typedef union { /* Protocol Configuration Register 21 */ + uint16_t R; + struct { + uint16_t EXTERN_RATE_CORRECTION:3; /* pExternRateCorrection */ + uint16_t LATEST_TX:13; /* gNumberOfMinislots - pLatestTx */ + } B; + } FR_PCR21_16B_tag; + + typedef union { /* Protocol Configuration Register 22 */ + uint16_t R; + struct { + uint16_t R:1; /* Reserved bit */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t COMP_ACCEPTED_STARRUP_RANGE_A:11; /* pdAcceptedStartupRange - pDelayCompensationChA */ +#else + uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MICRO_PER_CYCLE_19_16:4; /* gMicroPerCycle */ +#else + uint16_t MICRO_PER_CYCLE_H:4; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR22_16B_tag; + + typedef union { /* Protocol Configuration Register 23 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t MICRO_PER_CYCLE_15_0:16; /* pMicroPerCycle */ +#else + uint16_t micro_per_cycle_l:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR23_16B_tag; + + typedef union { /* Protocol Configuration Register 24 */ + uint16_t R; + struct { + uint16_t CLUSTER_DRIFT_DAMPING:5; /* pClusterDriftDamping */ + uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; /* pPayloadLengthDynMax */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t MICRO_PER_CYCLE_MIN_19_16:4; /* pMicroPerCycle - pdMaxDrift */ +#else + uint16_t MICRO_PER_CYCLE_MIN_H:4; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR24_16B_tag; + + typedef union { /* Protocol Configuration Register 25 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t MICRO_PER_CYCLE_MIN_15_0:16; /* pMicroPerCycle - pdMaxDrift */ +#else + uint16_t MICRO_PER_CYCLE_MIN_L:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR25_16B_tag; + + typedef union { /* Protocol Configuration Register 26 */ + uint16_t R; + struct { + uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; /* pAllowHaltDueToClock */ + uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; /* pdAcceptedStartupRange - pDelayCompensationChB */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t MICRO_PER_CYCLE_MAX_19_16:4; /* pMicroPerCycle + pdMaxDrift */ +#else + uint16_t MICRO_PER_CYCLE_MAX_H:4; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR26_16B_tag; + + typedef union { /* Protocol Configuration Register 27 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t MICRO_PER_CYCLE_MAX_15_0:16; /* pMicroPerCycle + pdMaxDrift */ +#else + uint16_t MICRO_PER_CYCLE_MAX_L:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR27_16B_tag; + + typedef union { /* Protocol Configuration Register 28 */ + uint16_t R; + struct { + uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; /* gdDynamicSlotIdlePhase */ + uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; /* gMacroPerCycle - gOffsetCorrectionStart */ + } B; + } FR_PCR28_16B_tag; + + typedef union { /* Protocol Configuration Register 29 */ + uint16_t R; + struct { + uint16_t EXTERN_OFFSET_CORRECTION:3; /* pExternOffsetCorrection */ + uint16_t MINISLOTS_MAX:13; /* gNumberOfMinislots - 1 */ + } B; + } FR_PCR29_16B_tag; + + typedef union { /* Protocol Configuration Register 30 */ + uint16_t R; + struct { + uint16_t:12; + uint16_t SYNC_NODE_MAX:4; /* gSyncNodeMax */ + } B; + } FR_PCR30_16B_tag; + + typedef union { /* Receive FIFO System Memory Base Address High Register */ + uint16_t R; + struct { + uint16_t SMBA_31_16:16; /* System Memory Base Address */ + } B; + } FR_RFSYMBHADR_16B_tag; + + typedef union { /* Receive FIFO System Memory Base Address Low Register */ + uint16_t R; + struct { + uint16_t:4; + uint16_t SMBA_15_4:12; /* System Memory Base Address */ + } B; + } FR_RFSYMBLADR_16B_tag; + + typedef union { /* Receive FIFO Periodic Timer Register */ + uint16_t R; + struct { + uint16_t:2; + uint16_t PTD:14; /* Periodic Timer Duration */ + } B; + } FR_RFPTR_16B_tag; + + typedef union { /* Receive FIFO Fill Level and Pop Count Register */ + uint16_t R; + struct { + uint16_t FLPCB:8; /* Fill Level and Pop Count Channel B */ + uint16_t FLPCA:8; /* Fill Level and Pop Count Channel A */ + } B; + } FR_RFFLPCR_16B_tag; + + typedef union { /* ECC Error Interrupt Flag and Enable Register */ + uint16_t R; + struct { + uint16_t LRNE_OF:1; /* LRAM Non-Corrected Error Overflow Flag */ + uint16_t LRCE_OF:1; /* LRAM Corrected Error Overflow Flag */ + uint16_t DRNE_OF:1; /* DRAM Non-Corrected Error Overflow Flag */ + uint16_t DRCE_OF:1; /* DRAM Corrected Error Overflow Flag */ + uint16_t LRNE_IF:1; /* LRAM Non-Corrected Error Interrupt Flag */ + uint16_t LRCE_IF:1; /* LRAM Corrected Error Interrupt Flag */ + uint16_t DRNE_IF:1; /* DRAM Non-Corrected Error Interrupt Flag */ + uint16_t DRCE_IF:1; /* DRAM Corrected Error Interrupt Flag */ + uint16_t:4; + uint16_t LRNE_IE:1; /* LRAM Non-Corrected Error Interrupt Enable */ + uint16_t LRCE_IE:1; /* LRAM Corrected Error Interrupt Enable */ + uint16_t DRNE_IE:1; /* DRAM Non-Corrected Error Interrupt Enable */ + uint16_t DRCE_IE:1; /* DRAM Corrected Error Interrupt Enable */ + } B; + } FR_EEIFER_16B_tag; + + typedef union { /* ECC Error Report and Injection Control Register */ + uint16_t R; + struct { + uint16_t BSY:1; /* Register Update Busy */ + uint16_t:5; + uint16_t ERS:2; /* Error Report Select */ + uint16_t:3; + uint16_t ERM:1; /* Error Report Mode */ + uint16_t:2; + uint16_t EIM:1; /* Error Injection Mode */ + uint16_t EIE:1; /* Error Injection Enable */ + } B; + } FR_EERICR_16B_tag; + + typedef union { /* ECC Error Report Adress Register */ + uint16_t R; + struct { + uint16_t MID:1; /* Memory Identifier */ + uint16_t BANK:3; /* Memory Bank */ + uint16_t ADDR:12; /* Memory Address */ + } B; + } FR_EERAR_16B_tag; + + typedef union { /* ECC Error Report Data Register */ + uint16_t R; + struct { + uint16_t DATA:16; /* Data */ + } B; + } FR_EERDR_16B_tag; + + typedef union { /* ECC Error Report Code Register */ + uint16_t R; + struct { + uint16_t:11; + uint16_t CODE:5; /* Code */ + } B; + } FR_EERCR_16B_tag; + + typedef union { /* ECC Error Injection Address Register */ + uint16_t R; + struct { + uint16_t MID:1; /* Memory Identifier */ + uint16_t BANK:3; /* Memory Bank */ + uint16_t ADDR:12; /* Memory Address */ + } B; + } FR_EEIAR_16B_tag; + + typedef union { /* ECC Error Injection Data Register */ + uint16_t R; + struct { + uint16_t DATA:16; /* Data */ + } B; + } FR_EEIDR_16B_tag; + + typedef union { /* ECC Error Injection Code Register */ + uint16_t R; + struct { + uint16_t:11; + uint16_t CODE:5; /* Code */ + } B; + } FR_EEICR_16B_tag; + + + /* Register layout for all registers MBCCSR... */ + + typedef union { /* Message Buffer Configuration Control Status Register */ + uint16_t R; + struct { + uint16_t:1; + uint16_t MCM:1; /* Message Buffer Commit Mode */ + uint16_t MBT:1; /* Message Buffer Type */ + uint16_t MTD:1; /* Message Buffer Transfer Direction */ + uint16_t CMT:1; /* Commit for Transmission */ + uint16_t EDT:1; /* Enable/Disable Trigger */ + uint16_t LCKT:1; /* Lock/Unlock Trigger */ + uint16_t MBIE:1; /* Message Buffer Interrupt Enable */ + uint16_t:3; + uint16_t DUP:1; /* Data Updated */ + uint16_t DVAL:1; /* DataValid */ + uint16_t EDS:1; /* Enable/Disable Status */ + uint16_t LCKS:1; /* LockStatus */ + uint16_t MBIF:1; /* Message Buffer Interrupt Flag */ + } B; + } FR_MBCCSR_16B_tag; + + + /* Register layout for all registers MBCCFR... */ + + typedef union { /* Message Buffer Cycle Counter Filter Register */ + uint16_t R; + struct { + uint16_t MTM:1; /* Message Buffer Transmission Mode */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t CHA:1; /* Channel Assignment */ +#else + uint16_t CHNLA:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CHB:1; /* Channel Assignment */ +#else + uint16_t CHNLB:1; /* deprecated name - please avoid */ +#endif + uint16_t CCFE:1; /* Cycle Counter Filtering Enable */ + uint16_t CCFMSK:6; /* Cycle Counter Filtering Mask */ + uint16_t CCFVAL:6; /* Cycle Counter Filtering Value */ + } B; + } FR_MBCCFR_16B_tag; + + + /* Register layout for all registers MBFIDR... */ + + typedef union { /* Message Buffer Frame ID Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t FID:11; /* Frame ID */ + } B; + } FR_MBFIDR_16B_tag; + + + /* Register layout for all registers MBIDXR... */ + + typedef union { /* Message Buffer Index Register */ + uint16_t R; + struct { + uint16_t:9; + uint16_t MBIDX:7; /* Message Buffer Index */ + } B; + } FR_MBIDXR_16B_tag; + + + /* Register layout for generated register(s) NMVR... */ + + typedef union { /* */ + uint16_t R; + } FR_NMVR_16B_tag; + + + + + /* Register layout for generated register(s) SSCR... */ + + typedef union { /* */ + uint16_t R; + } FR_SSCR_16B_tag; + + + typedef struct FR_MB_struct_tag { + + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR; /* relative offset: 0x0000 */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR; /* relative offset: 0x0002 */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR; /* relative offset: 0x0004 */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR; /* relative offset: 0x0006 */ + + } FR_MB_tag; + + + typedef struct FR_struct_tag { /* start of FR_tag */ + /* Module Version Number */ + FR_MVR_16B_tag MVR; /* offset: 0x0000 size: 16 bit */ + /* Module Configuration Register */ + FR_MCR_16B_tag MCR; /* offset: 0x0002 size: 16 bit */ + union { + FR_SYMBADHR_16B_tag SYSBADHR; /* deprecated - please avoid */ + + /* SYSTEM MEMORY BASE ADD HIGH REG */ + FR_SYMBADHR_16B_tag SYMBADHR; /* offset: 0x0004 size: 16 bit */ + + }; + union { + FR_SYMBADLR_16B_tag SYSBADLR; /* deprecated - please avoid */ + + /* SYSTEM MEMORY BASE ADD LOW REG */ + FR_SYMBADLR_16B_tag SYMBADLR; /* offset: 0x0006 size: 16 bit */ + + }; + /* STROBE SIGNAL CONTROL REGISTER */ + FR_STBSCR_16B_tag STBSCR; /* offset: 0x0008 size: 16 bit */ + int8_t FR_reserved_000A[2]; + /* MESSAGE BUFFER DATA SIZE REGISTER */ + FR_MBDSR_16B_tag MBDSR; /* offset: 0x000C size: 16 bit */ + /* MESS. BUFFER SEG. SIZE & UTILISATION REG */ + FR_MBSSUTR_16B_tag MBSSUTR; /* offset: 0x000E size: 16 bit */ + union { + /* PE DRAM ACCESS REGISTER */ + FR_PEDRAR_16B_tag PEDRAR; /* offset: 0x0010 size: 16 bit */ + + FR_PEDRAR_16B_tag PADR; /* deprecated - please avoid */ + + }; + union { + /* PE DRAM DATA REGISTER */ + FR_PEDRDR_16B_tag PEDRDR; /* offset: 0x0012 size: 16 bit */ + + FR_PEDRDR_16B_tag PDAR; /* deprecated - please avoid */ + + }; + /* PROTOCOL OPERATION CONTROL REG */ + FR_POCR_16B_tag POCR; /* offset: 0x0014 size: 16 bit */ + /* GLOBAL INTERRUPT FLAG & ENABLE REG */ + FR_GIFER_16B_tag GIFER; /* offset: 0x0016 size: 16 bit */ + /* PROTOCOL INTERRUPT FLAG REGISTER 0 */ + FR_PIFR0_16B_tag PIFR0; /* offset: 0x0018 size: 16 bit */ + /* PROTOCOL INTERRUPT FLAG REGISTER 1 */ + FR_PIFR1_16B_tag PIFR1; /* offset: 0x001A size: 16 bit */ + /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */ + FR_PIER0_16B_tag PIER0; /* offset: 0x001C size: 16 bit */ + /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */ + FR_PIER1_16B_tag PIER1; /* offset: 0x001E size: 16 bit */ + /* CHI ERROR FLAG REGISTER */ + FR_CHIERFR_16B_tag CHIERFR; /* offset: 0x0020 size: 16 bit */ + /* Message Buffer Interrupt Vector Register */ + FR_MBIVEC_16B_tag MBIVEC; /* offset: 0x0022 size: 16 bit */ + /* Channel A Status Error Counter Register */ + FR_CASERCR_16B_tag CASERCR; /* offset: 0x0024 size: 16 bit */ + /* Channel B Status Error Counter Register */ + FR_CBSERCR_16B_tag CBSERCR; /* offset: 0x0026 size: 16 bit */ + /* Protocol Status Register 0 */ + FR_PSR0_16B_tag PSR0; /* offset: 0x0028 size: 16 bit */ + /* Protocol Status Register 1 */ + FR_PSR1_16B_tag PSR1; /* offset: 0x002A size: 16 bit */ + /* Protocol Status Register 2 */ + FR_PSR2_16B_tag PSR2; /* offset: 0x002C size: 16 bit */ + /* Protocol Status Register 3 */ + FR_PSR3_16B_tag PSR3; /* offset: 0x002E size: 16 bit */ + /* Macrotick Counter Register */ + FR_MTCTR_16B_tag MTCTR; /* offset: 0x0030 size: 16 bit */ + /* Cycle Counter Register */ + FR_CYCTR_16B_tag CYCTR; /* offset: 0x0032 size: 16 bit */ + /* Slot Counter Channel A Register */ + FR_SLTCTAR_16B_tag SLTCTAR; /* offset: 0x0034 size: 16 bit */ + /* Slot Counter Channel B Register */ + FR_SLTCTBR_16B_tag SLTCTBR; /* offset: 0x0036 size: 16 bit */ + /* Rate Correction Value Register */ + FR_RTCORVR_16B_tag RTCORVR; /* offset: 0x0038 size: 16 bit */ + /* Offset Correction Value Register */ + FR_OFCORVR_16B_tag OFCORVR; /* offset: 0x003A size: 16 bit */ + union { + FR_CIFR_16B_tag CIFRR; /* deprecated - please avoid */ + + /* Combined Interrupt Flag Register */ + FR_CIFR_16B_tag CIFR; /* offset: 0x003C size: 16 bit */ + + }; + /* System Memory Access Time-Out Register */ + FR_SYMATOR_16B_tag SYMATOR; /* offset: 0x003E size: 16 bit */ + /* Sync Frame Counter Register */ + FR_SFCNTR_16B_tag SFCNTR; /* offset: 0x0040 size: 16 bit */ + /* Sync Frame Table Offset Register */ + FR_SFTOR_16B_tag SFTOR; /* offset: 0x0042 size: 16 bit */ + /* Sync Frame Table Configuration, Control, Status Register */ + FR_SFTCCSR_16B_tag SFTCCSR; /* offset: 0x0044 size: 16 bit */ + /* Sync Frame ID Rejection Filter */ + FR_SFIDRFR_16B_tag SFIDRFR; /* offset: 0x0046 size: 16 bit */ + /* Sync Frame ID Acceptance Filter Value Register */ + FR_SFIDAFVR_16B_tag SFIDAFVR; /* offset: 0x0048 size: 16 bit */ + /* Sync Frame ID Acceptance Filter Mask Register */ + FR_SFIDAFMR_16B_tag SFIDAFMR; /* offset: 0x004A size: 16 bit */ + union { + FR_NMVR_16B_tag NMVR[6]; /* offset: 0x004C (0x0002 x 6) */ + + struct { + /* Network Management Vector Register0 */ + FR_NMVR0_16B_tag NMVR0; /* offset: 0x004C size: 16 bit */ + /* Network Management Vector Register1 */ + FR_NMVR1_16B_tag NMVR1; /* offset: 0x004E size: 16 bit */ + /* Network Management Vector Register2 */ + FR_NMVR2_16B_tag NMVR2; /* offset: 0x0050 size: 16 bit */ + /* Network Management Vector Register3 */ + FR_NMVR3_16B_tag NMVR3; /* offset: 0x0052 size: 16 bit */ + /* Network Management Vector Register4 */ + FR_NMVR4_16B_tag NMVR4; /* offset: 0x0054 size: 16 bit */ + /* Network Management Vector Register5 */ + FR_NMVR5_16B_tag NMVR5; /* offset: 0x0056 size: 16 bit */ + }; + + }; + /* Network Management Vector Length Register */ + FR_NMVLR_16B_tag NMVLR; /* offset: 0x0058 size: 16 bit */ + /* Timer Configuration and Control Register */ + FR_TICCR_16B_tag TICCR; /* offset: 0x005A size: 16 bit */ + /* Timer 1 Cycle Set Register */ + FR_TI1CYSR_16B_tag TI1CYSR; /* offset: 0x005C size: 16 bit */ + union { + /* Timer 1 Macrotick Offset Register */ + FR_TI1MTOR_16B_tag TI1MTOR; /* offset: 0x005E size: 16 bit */ + + FR_TI1MTOR_16B_tag T1MTOR; /* deprecated - please avoid */ + + }; + /* Timer 2 Configuration Register 0 */ + FR_TI2CR0_16B_tag TI2CR0; /* offset: 0x0060 size: 16 bit */ + /* Timer 2 Configuration Register 1 */ + FR_TI2CR1_16B_tag TI2CR1; /* offset: 0x0062 size: 16 bit */ + /* Slot Status Selection Register */ + FR_SSSR_16B_tag SSSR; /* offset: 0x0064 size: 16 bit */ + /* Slot Status Counter Condition Register */ + FR_SSCCR_16B_tag SSCCR; /* offset: 0x0066 size: 16 bit */ + union { + FR_SSR_16B_tag SSR[8]; /* offset: 0x0068 (0x0002 x 8) */ + + struct { + /* Slot Status Register0 */ + FR_SSR_16B_tag SSR0; /* offset: 0x0068 size: 16 bit */ + /* Slot Status Register1 */ + FR_SSR_16B_tag SSR1; /* offset: 0x006A size: 16 bit */ + /* Slot Status Register2 */ + FR_SSR_16B_tag SSR2; /* offset: 0x006C size: 16 bit */ + /* Slot Status Register3 */ + FR_SSR_16B_tag SSR3; /* offset: 0x006E size: 16 bit */ + /* Slot Status Register4 */ + FR_SSR_16B_tag SSR4; /* offset: 0x0070 size: 16 bit */ + /* Slot Status Register5 */ + FR_SSR_16B_tag SSR5; /* offset: 0x0072 size: 16 bit */ + /* Slot Status Register6 */ + FR_SSR_16B_tag SSR6; /* offset: 0x0074 size: 16 bit */ + /* Slot Status Register7 */ + FR_SSR_16B_tag SSR7; /* offset: 0x0076 size: 16 bit */ + }; + + }; + union { + FR_SSCR_16B_tag SSCR[4]; /* offset: 0x0078 (0x0002 x 4) */ + + struct { + /* Slot Status Counter Register0 */ + FR_SSCR0_16B_tag SSCR0; /* offset: 0x0078 size: 16 bit */ + /* Slot Status Counter Register1 */ + FR_SSCR1_16B_tag SSCR1; /* offset: 0x007A size: 16 bit */ + /* Slot Status Counter Register2 */ + FR_SSCR2_16B_tag SSCR2; /* offset: 0x007C size: 16 bit */ + /* Slot Status Counter Register3 */ + FR_SSCR3_16B_tag SSCR3; /* offset: 0x007E size: 16 bit */ + }; + + }; + /* MTS A Configuration Register */ + FR_MTSACFR_16B_tag MTSACFR; /* offset: 0x0080 size: 16 bit */ + /* MTS B Configuration Register */ + FR_MTSBCFR_16B_tag MTSBCFR; /* offset: 0x0082 size: 16 bit */ + /* Receive Shadow Buffer Index Register */ + FR_RSBIR_16B_tag RSBIR; /* offset: 0x0084 size: 16 bit */ + union { + /* Receive FIFO Watermark and Selection Register */ + FR_RFWMSR_16B_tag RFWMSR; /* offset: 0x0086 size: 16 bit */ + + FR_RFWMSR_16B_tag RFSR; /* deprecated - please avoid */ + + }; + union { + FR_RF_RFSIR_16B_tag RFSIR; /* deprecated - please avoid */ + + /* Receive FIFO Start Index Register */ + FR_RF_RFSIR_16B_tag RF_RFSIR; /* offset: 0x0088 size: 16 bit */ + + }; + /* Receive FIFO Depth and Size Register */ + FR_RFDSR_16B_tag RFDSR; /* offset: 0x008A size: 16 bit */ + /* Receive FIFO A Read Index Register */ + FR_RFARIR_16B_tag RFARIR; /* offset: 0x008C size: 16 bit */ + /* Receive FIFO B Read Index Register */ + FR_RFBRIR_16B_tag RFBRIR; /* offset: 0x008E size: 16 bit */ + /* Receive FIFO Message ID Acceptance Filter Value Register */ + FR_RFMIDAFVR_16B_tag RFMIDAFVR; /* offset: 0x0090 size: 16 bit */ + union { + /* Receive FIFO Message ID Acceptance Filter Mask Register */ + FR_RFMIDAFMR_16B_tag RFMIDAFMR; /* offset: 0x0092 size: 16 bit */ + + FR_RFMIDAFMR_16B_tag RFMIAFMR; /* deprecated - please avoid */ + + }; + /* Receive FIFO Frame ID Rejection Filter Value Register */ + FR_RFFIDRFVR_16B_tag RFFIDRFVR; /* offset: 0x0094 size: 16 bit */ + /* Receive FIFO Frame ID Rejection Filter Mask Register */ + FR_RFFIDRFMR_16B_tag RFFIDRFMR; /* offset: 0x0096 size: 16 bit */ + /* Receive FIFO Range Filter Configuration Register */ + FR_RFRFCFR_16B_tag RFRFCFR; /* offset: 0x0098 size: 16 bit */ + /* Receive FIFO Range Filter Control Register */ + FR_RFRFCTR_16B_tag RFRFCTR; /* offset: 0x009A size: 16 bit */ + /* Last Dynamic Transmit Slot Channel A Register */ + FR_LDTXSLAR_16B_tag LDTXSLAR; /* offset: 0x009C size: 16 bit */ + /* Last Dynamic Transmit Slot Channel B Register */ + FR_LDTXSLBR_16B_tag LDTXSLBR; /* offset: 0x009E size: 16 bit */ + /* Protocol Configuration Register 0 */ + FR_PCR0_16B_tag PCR0; /* offset: 0x00A0 size: 16 bit */ + /* Protocol Configuration Register 1 */ + FR_PCR1_16B_tag PCR1; /* offset: 0x00A2 size: 16 bit */ + /* Protocol Configuration Register 2 */ + FR_PCR2_16B_tag PCR2; /* offset: 0x00A4 size: 16 bit */ + /* Protocol Configuration Register 3 */ + FR_PCR3_16B_tag PCR3; /* offset: 0x00A6 size: 16 bit */ + /* Protocol Configuration Register 4 */ + FR_PCR4_16B_tag PCR4; /* offset: 0x00A8 size: 16 bit */ + /* Protocol Configuration Register 5 */ + FR_PCR5_16B_tag PCR5; /* offset: 0x00AA size: 16 bit */ + /* Protocol Configuration Register 6 */ + FR_PCR6_16B_tag PCR6; /* offset: 0x00AC size: 16 bit */ + /* Protocol Configuration Register 7 */ + FR_PCR7_16B_tag PCR7; /* offset: 0x00AE size: 16 bit */ + /* Protocol Configuration Register 8 */ + FR_PCR8_16B_tag PCR8; /* offset: 0x00B0 size: 16 bit */ + /* Protocol Configuration Register 9 */ + FR_PCR9_16B_tag PCR9; /* offset: 0x00B2 size: 16 bit */ + /* Protocol Configuration Register 10 */ + FR_PCR10_16B_tag PCR10; /* offset: 0x00B4 size: 16 bit */ + /* Protocol Configuration Register 11 */ + FR_PCR11_16B_tag PCR11; /* offset: 0x00B6 size: 16 bit */ + /* Protocol Configuration Register 12 */ + FR_PCR12_16B_tag PCR12; /* offset: 0x00B8 size: 16 bit */ + /* Protocol Configuration Register 13 */ + FR_PCR13_16B_tag PCR13; /* offset: 0x00BA size: 16 bit */ + /* Protocol Configuration Register 14 */ + FR_PCR14_16B_tag PCR14; /* offset: 0x00BC size: 16 bit */ + /* Protocol Configuration Register 15 */ + FR_PCR15_16B_tag PCR15; /* offset: 0x00BE size: 16 bit */ + /* Protocol Configuration Register 16 */ + FR_PCR16_16B_tag PCR16; /* offset: 0x00C0 size: 16 bit */ + /* Protocol Configuration Register 17 */ + FR_PCR17_16B_tag PCR17; /* offset: 0x00C2 size: 16 bit */ + /* Protocol Configuration Register 18 */ + FR_PCR18_16B_tag PCR18; /* offset: 0x00C4 size: 16 bit */ + /* Protocol Configuration Register 19 */ + FR_PCR19_16B_tag PCR19; /* offset: 0x00C6 size: 16 bit */ + /* Protocol Configuration Register 20 */ + FR_PCR20_16B_tag PCR20; /* offset: 0x00C8 size: 16 bit */ + /* Protocol Configuration Register 21 */ + FR_PCR21_16B_tag PCR21; /* offset: 0x00CA size: 16 bit */ + /* Protocol Configuration Register 22 */ + FR_PCR22_16B_tag PCR22; /* offset: 0x00CC size: 16 bit */ + /* Protocol Configuration Register 23 */ + FR_PCR23_16B_tag PCR23; /* offset: 0x00CE size: 16 bit */ + /* Protocol Configuration Register 24 */ + FR_PCR24_16B_tag PCR24; /* offset: 0x00D0 size: 16 bit */ + /* Protocol Configuration Register 25 */ + FR_PCR25_16B_tag PCR25; /* offset: 0x00D2 size: 16 bit */ + /* Protocol Configuration Register 26 */ + FR_PCR26_16B_tag PCR26; /* offset: 0x00D4 size: 16 bit */ + /* Protocol Configuration Register 27 */ + FR_PCR27_16B_tag PCR27; /* offset: 0x00D6 size: 16 bit */ + /* Protocol Configuration Register 28 */ + FR_PCR28_16B_tag PCR28; /* offset: 0x00D8 size: 16 bit */ + /* Protocol Configuration Register 29 */ + FR_PCR29_16B_tag PCR29; /* offset: 0x00DA size: 16 bit */ + /* Protocol Configuration Register 30 */ + FR_PCR30_16B_tag PCR30; /* offset: 0x00DC size: 16 bit */ + int8_t FR_reserved_00DE[10]; + /* Receive FIFO System Memory Base Address High Register */ + FR_RFSYMBHADR_16B_tag RFSYMBHADR; /* offset: 0x00E8 size: 16 bit */ + /* Receive FIFO System Memory Base Address Low Register */ + FR_RFSYMBLADR_16B_tag RFSYMBLADR; /* offset: 0x00EA size: 16 bit */ + /* Receive FIFO Periodic Timer Register */ + FR_RFPTR_16B_tag RFPTR; /* offset: 0x00EC size: 16 bit */ + /* Receive FIFO Fill Level and Pop Count Register */ + FR_RFFLPCR_16B_tag RFFLPCR; /* offset: 0x00EE size: 16 bit */ + /* ECC Error Interrupt Flag and Enable Register */ + FR_EEIFER_16B_tag EEIFER; /* offset: 0x00F0 size: 16 bit */ + /* ECC Error Report and Injection Control Register */ + FR_EERICR_16B_tag EERICR; /* offset: 0x00F2 size: 16 bit */ + /* ECC Error Report Adress Register */ + FR_EERAR_16B_tag EERAR; /* offset: 0x00F4 size: 16 bit */ + /* ECC Error Report Data Register */ + FR_EERDR_16B_tag EERDR; /* offset: 0x00F6 size: 16 bit */ + /* ECC Error Report Code Register */ + FR_EERCR_16B_tag EERCR; /* offset: 0x00F8 size: 16 bit */ + /* ECC Error Injection Address Register */ + FR_EEIAR_16B_tag EEIAR; /* offset: 0x00FA size: 16 bit */ + /* ECC Error Injection Data Register */ + FR_EEIDR_16B_tag EEIDR; /* offset: 0x00FC size: 16 bit */ + /* ECC Error Injection Code Register */ + FR_EEICR_16B_tag EEICR; /* offset: 0x00FE size: 16 bit */ + union { + /* Register set MB */ + FR_MB_tag MB[64]; /* offset: 0x0100 (0x0008 x 64) */ + + FR_MB_tag MBCCS[64]; /* offset: 0x0100 (0x0008 x 64) */ + + struct { + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR0; /* offset: 0x0100 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR0; /* offset: 0x0102 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR0; /* offset: 0x0104 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR0; /* offset: 0x0106 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR1; /* offset: 0x0108 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR1; /* offset: 0x010A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR1; /* offset: 0x010C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR1; /* offset: 0x010E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR2; /* offset: 0x0110 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR2; /* offset: 0x0112 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR2; /* offset: 0x0114 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR2; /* offset: 0x0116 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR3; /* offset: 0x0118 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR3; /* offset: 0x011A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR3; /* offset: 0x011C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR3; /* offset: 0x011E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR4; /* offset: 0x0120 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR4; /* offset: 0x0122 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR4; /* offset: 0x0124 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR4; /* offset: 0x0126 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR5; /* offset: 0x0128 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR5; /* offset: 0x012A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR5; /* offset: 0x012C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR5; /* offset: 0x012E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR6; /* offset: 0x0130 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR6; /* offset: 0x0132 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR6; /* offset: 0x0134 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR6; /* offset: 0x0136 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR7; /* offset: 0x0138 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR7; /* offset: 0x013A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR7; /* offset: 0x013C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR7; /* offset: 0x013E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR8; /* offset: 0x0140 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR8; /* offset: 0x0142 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR8; /* offset: 0x0144 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR8; /* offset: 0x0146 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR9; /* offset: 0x0148 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR9; /* offset: 0x014A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR9; /* offset: 0x014C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR9; /* offset: 0x014E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR10; /* offset: 0x0150 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR10; /* offset: 0x0152 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR10; /* offset: 0x0154 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR10; /* offset: 0x0156 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR11; /* offset: 0x0158 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR11; /* offset: 0x015A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR11; /* offset: 0x015C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR11; /* offset: 0x015E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR12; /* offset: 0x0160 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR12; /* offset: 0x0162 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR12; /* offset: 0x0164 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR12; /* offset: 0x0166 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR13; /* offset: 0x0168 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR13; /* offset: 0x016A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR13; /* offset: 0x016C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR13; /* offset: 0x016E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR14; /* offset: 0x0170 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR14; /* offset: 0x0172 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR14; /* offset: 0x0174 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR14; /* offset: 0x0176 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR15; /* offset: 0x0178 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR15; /* offset: 0x017A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR15; /* offset: 0x017C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR15; /* offset: 0x017E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR16; /* offset: 0x0180 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR16; /* offset: 0x0182 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR16; /* offset: 0x0184 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR16; /* offset: 0x0186 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR17; /* offset: 0x0188 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR17; /* offset: 0x018A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR17; /* offset: 0x018C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR17; /* offset: 0x018E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR18; /* offset: 0x0190 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR18; /* offset: 0x0192 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR18; /* offset: 0x0194 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR18; /* offset: 0x0196 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR19; /* offset: 0x0198 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR19; /* offset: 0x019A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR19; /* offset: 0x019C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR19; /* offset: 0x019E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR20; /* offset: 0x01A0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR20; /* offset: 0x01A2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR20; /* offset: 0x01A4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR20; /* offset: 0x01A6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR21; /* offset: 0x01A8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR21; /* offset: 0x01AA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR21; /* offset: 0x01AC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR21; /* offset: 0x01AE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR22; /* offset: 0x01B0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR22; /* offset: 0x01B2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR22; /* offset: 0x01B4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR22; /* offset: 0x01B6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR23; /* offset: 0x01B8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR23; /* offset: 0x01BA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR23; /* offset: 0x01BC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR23; /* offset: 0x01BE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR24; /* offset: 0x01C0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR24; /* offset: 0x01C2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR24; /* offset: 0x01C4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR24; /* offset: 0x01C6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR25; /* offset: 0x01C8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR25; /* offset: 0x01CA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR25; /* offset: 0x01CC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR25; /* offset: 0x01CE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR26; /* offset: 0x01D0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR26; /* offset: 0x01D2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR26; /* offset: 0x01D4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR26; /* offset: 0x01D6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR27; /* offset: 0x01D8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR27; /* offset: 0x01DA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR27; /* offset: 0x01DC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR27; /* offset: 0x01DE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR28; /* offset: 0x01E0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR28; /* offset: 0x01E2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR28; /* offset: 0x01E4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR28; /* offset: 0x01E6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR29; /* offset: 0x01E8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR29; /* offset: 0x01EA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR29; /* offset: 0x01EC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR29; /* offset: 0x01EE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR30; /* offset: 0x01F0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR30; /* offset: 0x01F2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR30; /* offset: 0x01F4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR30; /* offset: 0x01F6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR31; /* offset: 0x01F8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR31; /* offset: 0x01FA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR31; /* offset: 0x01FC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR31; /* offset: 0x01FE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR32; /* offset: 0x0200 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR32; /* offset: 0x0202 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR32; /* offset: 0x0204 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR32; /* offset: 0x0206 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR33; /* offset: 0x0208 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR33; /* offset: 0x020A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR33; /* offset: 0x020C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR33; /* offset: 0x020E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR34; /* offset: 0x0210 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR34; /* offset: 0x0212 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR34; /* offset: 0x0214 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR34; /* offset: 0x0216 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR35; /* offset: 0x0218 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR35; /* offset: 0x021A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR35; /* offset: 0x021C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR35; /* offset: 0x021E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR36; /* offset: 0x0220 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR36; /* offset: 0x0222 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR36; /* offset: 0x0224 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR36; /* offset: 0x0226 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR37; /* offset: 0x0228 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR37; /* offset: 0x022A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR37; /* offset: 0x022C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR37; /* offset: 0x022E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR38; /* offset: 0x0230 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR38; /* offset: 0x0232 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR38; /* offset: 0x0234 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR38; /* offset: 0x0236 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR39; /* offset: 0x0238 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR39; /* offset: 0x023A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR39; /* offset: 0x023C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR39; /* offset: 0x023E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR40; /* offset: 0x0240 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR40; /* offset: 0x0242 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR40; /* offset: 0x0244 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR40; /* offset: 0x0246 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR41; /* offset: 0x0248 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR41; /* offset: 0x024A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR41; /* offset: 0x024C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR41; /* offset: 0x024E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR42; /* offset: 0x0250 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR42; /* offset: 0x0252 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR42; /* offset: 0x0254 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR42; /* offset: 0x0256 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR43; /* offset: 0x0258 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR43; /* offset: 0x025A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR43; /* offset: 0x025C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR43; /* offset: 0x025E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR44; /* offset: 0x0260 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR44; /* offset: 0x0262 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR44; /* offset: 0x0264 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR44; /* offset: 0x0266 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR45; /* offset: 0x0268 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR45; /* offset: 0x026A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR45; /* offset: 0x026C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR45; /* offset: 0x026E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR46; /* offset: 0x0270 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR46; /* offset: 0x0272 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR46; /* offset: 0x0274 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR46; /* offset: 0x0276 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR47; /* offset: 0x0278 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR47; /* offset: 0x027A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR47; /* offset: 0x027C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR47; /* offset: 0x027E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR48; /* offset: 0x0280 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR48; /* offset: 0x0282 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR48; /* offset: 0x0284 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR48; /* offset: 0x0286 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR49; /* offset: 0x0288 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR49; /* offset: 0x028A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR49; /* offset: 0x028C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR49; /* offset: 0x028E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR50; /* offset: 0x0290 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR50; /* offset: 0x0292 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR50; /* offset: 0x0294 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR50; /* offset: 0x0296 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR51; /* offset: 0x0298 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR51; /* offset: 0x029A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR51; /* offset: 0x029C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR51; /* offset: 0x029E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR52; /* offset: 0x02A0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR52; /* offset: 0x02A2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR52; /* offset: 0x02A4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR52; /* offset: 0x02A6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR53; /* offset: 0x02A8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR53; /* offset: 0x02AA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR53; /* offset: 0x02AC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR53; /* offset: 0x02AE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR54; /* offset: 0x02B0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR54; /* offset: 0x02B2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR54; /* offset: 0x02B4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR54; /* offset: 0x02B6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR55; /* offset: 0x02B8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR55; /* offset: 0x02BA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR55; /* offset: 0x02BC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR55; /* offset: 0x02BE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR56; /* offset: 0x02C0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR56; /* offset: 0x02C2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR56; /* offset: 0x02C4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR56; /* offset: 0x02C6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR57; /* offset: 0x02C8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR57; /* offset: 0x02CA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR57; /* offset: 0x02CC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR57; /* offset: 0x02CE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR58; /* offset: 0x02D0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR58; /* offset: 0x02D2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR58; /* offset: 0x02D4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR58; /* offset: 0x02D6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR59; /* offset: 0x02D8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR59; /* offset: 0x02DA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR59; /* offset: 0x02DC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR59; /* offset: 0x02DE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR60; /* offset: 0x02E0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR60; /* offset: 0x02E2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR60; /* offset: 0x02E4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR60; /* offset: 0x02E6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR61; /* offset: 0x02E8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR61; /* offset: 0x02EA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR61; /* offset: 0x02EC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR61; /* offset: 0x02EE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR62; /* offset: 0x02F0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR62; /* offset: 0x02F2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR62; /* offset: 0x02F4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR62; /* offset: 0x02F6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR63; /* offset: 0x02F8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR63; /* offset: 0x02FA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR63; /* offset: 0x02FC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR63; /* offset: 0x02FE size: 16 bit */ + }; + + }; + } FR_tag; + + +#define FR (*(volatile FR_tag *) 0xFFFE0000UL) + + + + + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ +#endif /* _leopard_H_*/ + +/* End of file */ + diff --git a/bsps/powerpc/include/mpc55xx/fsl-mpc5668.h b/bsps/powerpc/include/mpc55xx/fsl-mpc5668.h new file mode 100644 index 0000000000..b7a1793dca --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/fsl-mpc5668.h @@ -0,0 +1,6721 @@ +/* + * Modifications of the original file provided by Freescale are: + * + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/************************************************************************** + * FILE NAME: mpc5668.h COPYRIGHT (c) Freescale 2009 * + * REVISION: 1.1 All Rights Reserved * + * * + * DESCRIPTION: * + * This file contain all of the register and bit field definitions for * + * MPC5668. * + **************************************************************************/ +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +/************************************************************************** + * Example register & bit field write: * + * * + * ..B. = 1; * + * ..R = 0x10000000; * + * * + **************************************************************************/ + +#ifndef _MPC5668_H_ +#define _MPC5668_H_ + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/*************************************************************************/ +/* MODULE : ADC */ +/*************************************************************************/ + struct ADC_tag { + + union { + uint32_t R; + struct { + uint32_t OWREN:1; + uint32_t WLSIDE:1; + uint32_t MODE:1; + uint32_t EDGLEV:1; + uint32_t TRGEN:1; + uint32_t EDGE:1; + uint32_t XSTRTEN:1; + uint32_t NSTART:1; + uint32_t:1; + uint32_t JTRGEN:1; + uint32_t JEDGE:1; + uint32_t JSTART:1; + uint32_t:2; + uint32_t CTUEN:1; + uint32_t:8; + uint32_t ADCLKSEL:1; + uint32_t ABORTCHAIN:1; + uint32_t ABORT:1; + uint32_t ACKO:1; + uint32_t OFFREFRESH:1; + uint32_t OFFCANC:1; + uint32_t:2; + uint32_t PWDN:1; + } B; + } MCR; /* MAIN CONFIGURATION REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:7; + uint32_t NSTART:1; + uint32_t JABORT:1; + uint32_t:2; + uint32_t JSTART:1; + uint32_t:3; + uint32_t CTUSTART:1; + uint32_t CHADDR:7; + uint32_t:3; + uint32_t ACKO:1; + uint32_t OFFREFRESH:1; + uint32_t OFFCANC:1; + uint32_t ADCSTATUS:3; + } B; + } MSR; /* MAIN STATUS REGISTER */ + + uint32_t adc_reserved1[2]; + + union { + uint32_t R; + struct { + uint32_t:25; + uint32_t OFFCANCOVR:1; + uint32_t EOFFSET:1; + uint32_t EOCTU:1; + uint32_t JEOC:1; + uint32_t JECH:1; + uint32_t EOC:1; + uint32_t ECH:1; + } B; + } ISR; /* INTERRUPT STATUS REGISTER */ + + union { + uint32_t R; + struct { + uint32_t EOCCH31:1; + uint32_t EOCCH30:1; + uint32_t EOCCH29:1; + uint32_t EOCCH28:1; + uint32_t EOCCH27:1; + uint32_t EOCCH26:1; + uint32_t EOCCH25:1; + uint32_t EOCCH24:1; + uint32_t EOCCH23:1; + uint32_t EOCCH22:1; + uint32_t EOCCH21:1; + uint32_t EOCCH20:1; + uint32_t EOCCH19:1; + uint32_t EOCCH18:1; + uint32_t EOCCH17:1; + uint32_t EOCCH16:1; + uint32_t EOCCH15:1; + uint32_t EOCCH14:1; + uint32_t EOCCH13:1; + uint32_t EOCCH12:1; + uint32_t EOCCH11:1; + uint32_t EOCCH10:1; + uint32_t EOCCH9:1; + uint32_t EOCCH8:1; + uint32_t EOCCH7:1; + uint32_t EOCCH6:1; + uint32_t EOCCH5:1; + uint32_t EOCCH4:1; + uint32_t EOCCH3:1; + uint32_t EOCCH2:1; + uint32_t EOCCH1:1; + uint32_t EOCCH0:1; + } B; + } CEOCFR0; /* CHANNEL PENDING REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t EOCCH63:1; + uint32_t EOCCH62:1; + uint32_t EOCCH61:1; + uint32_t EOCCH60:1; + uint32_t EOCCH59:1; + uint32_t EOCCH58:1; + uint32_t EOCCH57:1; + uint32_t EOCCH56:1; + uint32_t EOCCH55:1; + uint32_t EOCCH54:1; + uint32_t EOCCH53:1; + uint32_t EOCCH52:1; + uint32_t EOCCH51:1; + uint32_t EOCCH50:1; + uint32_t EOCCH49:1; + uint32_t EOCCH48:1; + uint32_t EOCCH47:1; + uint32_t EOCCH46:1; + uint32_t EOCCH45:1; + uint32_t EOCCH44:1; + uint32_t EOCCH43:1; + uint32_t EOCCH42:1; + uint32_t EOCCH41:1; + uint32_t EOCCH40:1; + uint32_t EOCCH39:1; + uint32_t EOCCH38:1; + uint32_t EOCCH37:1; + uint32_t EOCCH36:1; + uint32_t EOCCH35:1; + uint32_t EOCCH34:1; + uint32_t EOCCH33:1; + uint32_t EOCCH32:1; + } B; + } CEOCFR1; /* CHANNEL PENDING REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t EOCCH95:1; + uint32_t EOCCH94:1; + uint32_t EOCCH93:1; + uint32_t EOCCH92:1; + uint32_t EOCCH91:1; + uint32_t EOCCH90:1; + uint32_t EOCCH89:1; + uint32_t EOCCH88:1; + uint32_t EOCCH87:1; + uint32_t EOCCH86:1; + uint32_t EOCCH85:1; + uint32_t EOCCH84:1; + uint32_t EOCCH83:1; + uint32_t EOCCH82:1; + uint32_t EOCCH81:1; + uint32_t EOCCH80:1; + uint32_t EOCCH79:1; + uint32_t EOCCH78:1; + uint32_t EOCCH77:1; + uint32_t EOCCH76:1; + uint32_t EOCCH75:1; + uint32_t EOCCH74:1; + uint32_t EOCCH73:1; + uint32_t EOCCH72:1; + uint32_t EOCCH71:1; + uint32_t EOCCH70:1; + uint32_t EOCCH69:1; + uint32_t EOCCH68:1; + uint32_t EOCCH67:1; + uint32_t EOCCH66:1; + uint32_t EOCCH65:1; + uint32_t EOCCH64:1; + } B; + } CEOCFR2; /* CHANNEL PENDING REGISTER 2 */ + + union { + uint32_t R; + struct { + uint32_t:25; + uint32_t MSKOFFCANCOVR:1; + uint32_t MSKEOFFSET:1; + uint32_t MSKEOCTU:1; + uint32_t MSKJEOC:1; + uint32_t MSKJECH:1; + uint32_t MSKEOC:1; + uint32_t MSKECH:1; + } B; + } IMR; /* INTERRUPT MASK REGISTER */ + + union { + uint32_t R; + struct { + uint32_t CIM31:1; + uint32_t CIM30:1; + uint32_t CIM29:1; + uint32_t CIM28:1; + uint32_t CIM27:1; + uint32_t CIM26:1; + uint32_t CIM25:1; + uint32_t CIM24:1; + uint32_t CIM23:1; + uint32_t CIM22:1; + uint32_t CIM21:1; + uint32_t CIM20:1; + uint32_t CIM19:1; + uint32_t CIM18:1; + uint32_t CIM17:1; + uint32_t CIM16:1; + uint32_t CIM15:1; + uint32_t CIM14:1; + uint32_t CIM13:1; + uint32_t CIM12:1; + uint32_t CIM11:1; + uint32_t CIM10:1; + uint32_t CIM9:1; + uint32_t CIM8:1; + uint32_t CIM7:1; + uint32_t CIM6:1; + uint32_t CIM5:1; + uint32_t CIM4:1; + uint32_t CIM3:1; + uint32_t CIM2:1; + uint32_t CIM1:1; + uint32_t CIM0:1; + } B; + } CIMR0; /* CHANNEL INTERRUPT MASK REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t CIM63:1; + uint32_t CIM62:1; + uint32_t CIM61:1; + uint32_t CIM60:1; + uint32_t CIM59:1; + uint32_t CIM58:1; + uint32_t CIM57:1; + uint32_t CIM56:1; + uint32_t CIM55:1; + uint32_t CIM54:1; + uint32_t CIM53:1; + uint32_t CIM52:1; + uint32_t CIM51:1; + uint32_t CIM50:1; + uint32_t CIM49:1; + uint32_t CIM48:1; + uint32_t CIM47:1; + uint32_t CIM46:1; + uint32_t CIM45:1; + uint32_t CIM44:1; + uint32_t CIM43:1; + uint32_t CIM42:1; + uint32_t CIM41:1; + uint32_t CIM40:1; + uint32_t CIM39:1; + uint32_t CIM38:1; + uint32_t CIM37:1; + uint32_t CIM36:1; + uint32_t CIM35:1; + uint32_t CIM34:1; + uint32_t CIM33:1; + uint32_t CIM32:1; + } B; + } CIMR1; /* CHANNEL INTERRUPT MASK REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t CIM63:1; + uint32_t CIM62:1; + uint32_t CIM61:1; + uint32_t CIM60:1; + uint32_t CIM59:1; + uint32_t CIM58:1; + uint32_t CIM57:1; + uint32_t CIM56:1; + uint32_t CIM55:1; + uint32_t CIM54:1; + uint32_t CIM53:1; + uint32_t CIM52:1; + uint32_t CIM51:1; + uint32_t CIM50:1; + uint32_t CIM49:1; + uint32_t CIM48:1; + uint32_t CIM47:1; + uint32_t CIM46:1; + uint32_t CIM45:1; + uint32_t CIM44:1; + uint32_t CIM43:1; + uint32_t CIM42:1; + uint32_t CIM41:1; + uint32_t CIM40:1; + uint32_t CIM39:1; + uint32_t CIM38:1; + uint32_t CIM37:1; + uint32_t CIM36:1; + uint32_t CIM35:1; + uint32_t CIM34:1; + uint32_t CIM33:1; + uint32_t CIM32:1; + } B; + } CIMR2; /* CHANNEL INTERRUPT MASK REGISTER 2 */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t WDG3H:1; + uint32_t WDG2H:1; + uint32_t WDG1H:1; + uint32_t WDG0H:1; + uint32_t WDG3L:1; + uint32_t WDG2L:1; + uint32_t WDG1L:1; + uint32_t WDG0L:1; + } B; + } WTISR; /* WATCHDOG INTERRUPT THRESHOLD REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t MSKWDG3H:1; + uint32_t MSKWDG2H:1; + uint32_t MSKWDG1H:1; + uint32_t MSKWDG0H:1; + uint32_t MSKWDG3L:1; + uint32_t MSKWDG2L:1; + uint32_t MSKWDG1L:1; + uint32_t MSKWDG0L:1; + } B; + } WTIMR; /* WATCHDOG INTERRUPT THRESHOLD MASK REGISTER */ + + uint32_t adc_reserved2[2]; + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t DCLR:1; + uint32_t DMAEN:1; + } B; + } DMAE; /* DMA ENABLE REGISTER */ + + union { + uint32_t R; + struct { + uint32_t DMA31:1; + uint32_t DMA30:1; + uint32_t DMA29:1; + uint32_t DMA28:1; + uint32_t DMA27:1; + uint32_t DMA26:1; + uint32_t DMA25:1; + uint32_t DMA24:1; + uint32_t DMA23:1; + uint32_t DMA22:1; + uint32_t DMA21:1; + uint32_t DMA20:1; + uint32_t DMA19:1; + uint32_t DMA18:1; + uint32_t DMA17:1; + uint32_t DMA16:1; + uint32_t DMA15:1; + uint32_t DMA14:1; + uint32_t DMA13:1; + uint32_t DMA12:1; + uint32_t DMA11:1; + uint32_t DMA10:1; + uint32_t DMA9:1; + uint32_t DMA8:1; + uint32_t DMA7:1; + uint32_t DMA6:1; + uint32_t DMA5:1; + uint32_t DMA4:1; + uint32_t DMA3:1; + uint32_t DMA2:1; + uint32_t DMA1:1; + uint32_t DMA0:1; + } B; + } DMAR0; /* DMA CHANNEL SELECT REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t DMA63:1; + uint32_t DMA62:1; + uint32_t DMA61:1; + uint32_t DMA60:1; + uint32_t DMA59:1; + uint32_t DMA58:1; + uint32_t DMA57:1; + uint32_t DMA56:1; + uint32_t DMA55:1; + uint32_t DMA54:1; + uint32_t DMA53:1; + uint32_t DMA52:1; + uint32_t DMA51:1; + uint32_t DMA50:1; + uint32_t DMA49:1; + uint32_t DMA48:1; + uint32_t DMA47:1; + uint32_t DMA46:1; + uint32_t DMA45:1; + uint32_t DMA44:1; + uint32_t DMA43:1; + uint32_t DMA42:1; + uint32_t DMA41:1; + uint32_t DMA40:1; + uint32_t DMA39:1; + uint32_t DMA38:1; + uint32_t DMA37:1; + uint32_t DMA36:1; + uint32_t DMA35:1; + uint32_t DMA34:1; + uint32_t DMA33:1; + uint32_t DMA32:1; + } B; + } DMAR1; /* DMA CHANNEL SELECT REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t DMA95:1; + uint32_t DMA94:1; + uint32_t DMA93:1; + uint32_t DMA92:1; + uint32_t DMA91:1; + uint32_t DMA90:1; + uint32_t DMA89:1; + uint32_t DMA88:1; + uint32_t DMA87:1; + uint32_t DMA86:1; + uint32_t DMA85:1; + uint32_t DMA84:1; + uint32_t DMA83:1; + uint32_t DMA82:1; + uint32_t DMA81:1; + uint32_t DMA80:1; + uint32_t DMA79:1; + uint32_t DMA78:1; + uint32_t DMA77:1; + uint32_t DMA76:1; + uint32_t DMA75:1; + uint32_t DMA74:1; + uint32_t DMA73:1; + uint32_t DMA72:1; + uint32_t DMA71:1; + uint32_t DMA70:1; + uint32_t DMA69:1; + uint32_t DMA68:1; + uint32_t DMA67:1; + uint32_t DMA66:1; + uint32_t DMA65:1; + uint32_t DMA64:1; + } B; + } DMAR2; /* DMA CHANNEL SELECT REGISTER 2 */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t THREN:1; + uint32_t THRINV:1; + uint32_t THROP:1; + uint32_t:6; + uint32_t THRCH:7; + } B; + } TRC[4]; /* THRESHOLD CONTROL REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t THRH:10; + uint32_t:6; + uint32_t THRL:10; + } B; + } THRHLR[4]; /* THRESHOLD REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t THRH:10; + uint32_t:6; + uint32_t THRL:10; + } B; + } THRALT[4]; /* ALTERNATE THRESHOLD REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:25; + uint32_t PREVAL2:2; + uint32_t PREVAL1:2; + uint32_t PREVAL0:2; + uint32_t PRECONV:1; + } B; + } PSCR; /* PRESAMPLING CONTROL REGISTER */ + + union { + uint32_t R; + struct { + uint32_t PSR31:1; + uint32_t PSR30:1; + uint32_t PSR29:1; + uint32_t PSR28:1; + uint32_t PSR27:1; + uint32_t PSR26:1; + uint32_t PSR25:1; + uint32_t PSR24:1; + uint32_t PSR23:1; + uint32_t PSR22:1; + uint32_t PSR21:1; + uint32_t PSR20:1; + uint32_t PSR19:1; + uint32_t PSR18:1; + uint32_t PSR17:1; + uint32_t PSR16:1; + uint32_t PSR15:1; + uint32_t PSR14:1; + uint32_t PSR13:1; + uint32_t PSR12:1; + uint32_t PSR11:1; + uint32_t PSR10:1; + uint32_t PSR9:1; + uint32_t PSR8:1; + uint32_t PSR7:1; + uint32_t PSR6:1; + uint32_t PSR5:1; + uint32_t PSR4:1; + uint32_t PSR3:1; + uint32_t PSR2:1; + uint32_t PSR1:1; + uint32_t PSR0:1; + } B; + } PSR0; /* PRESAMPLING REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t PSR63:1; + uint32_t PSR62:1; + uint32_t PSR61:1; + uint32_t PSR60:1; + uint32_t PSR59:1; + uint32_t PSR58:1; + uint32_t PSR57:1; + uint32_t PSR56:1; + uint32_t PSR55:1; + uint32_t PSR54:1; + uint32_t PSR53:1; + uint32_t PSR52:1; + uint32_t PSR51:1; + uint32_t PSR50:1; + uint32_t PSR49:1; + uint32_t PSR48:1; + uint32_t PSR47:1; + uint32_t PSR46:1; + uint32_t PSR45:1; + uint32_t PSR44:1; + uint32_t PSR43:1; + uint32_t PSR42:1; + uint32_t PSR41:1; + uint32_t PSR40:1; + uint32_t PSR39:1; + uint32_t PSR38:1; + uint32_t PSR37:1; + uint32_t PSR36:1; + uint32_t PSR35:1; + uint32_t PSR34:1; + uint32_t PSR33:1; + uint32_t PSR32:1; + } B; + } PSR1; /* PRESAMPLING REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t PSR95:1; + uint32_t PSR94:1; + uint32_t PSR93:1; + uint32_t PSR92:1; + uint32_t PSR91:1; + uint32_t PSR90:1; + uint32_t PSR89:1; + uint32_t PSR88:1; + uint32_t PSR87:1; + uint32_t PSR86:1; + uint32_t PSR85:1; + uint32_t PSR84:1; + uint32_t PSR83:1; + uint32_t PSR82:1; + uint32_t PSR81:1; + uint32_t PSR80:1; + uint32_t PSR79:1; + uint32_t PSR78:1; + uint32_t PSR77:1; + uint32_t PSR76:1; + uint32_t PSR75:1; + uint32_t PSR74:1; + uint32_t PSR73:1; + uint32_t PSR72:1; + uint32_t PSR71:1; + uint32_t PSR70:1; + uint32_t PSR69:1; + uint32_t PSR68:1; + uint32_t PSR67:1; + uint32_t PSR66:1; + uint32_t PSR65:1; + uint32_t PSR64:1; + } B; + } PSR2; /* PRESAMPLING REGISTER 2 */ + + uint32_t adc_reserved3; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t INPLATCH:1; + uint32_t:1; + uint32_t OFFSHIFT:2; + uint32_t:1; + uint32_t INPCMP:2; + uint32_t:1; + uint32_t INPSAMP:8; + } B; + } CTR0; /* CONVERSION TIMING REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t INPLATCH:1; + uint32_t:4; + uint32_t INPCMP:2; + uint32_t:1; + uint32_t INPSAMP:8; + } B; + } CTR1; /* CONVERSION TIMING REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t INPLATCH:1; + uint32_t:4; + uint32_t INPCMP:2; + uint32_t:1; + uint32_t INPSAMP:8; + } B; + } CTR2; /* CONVERSION TIMING REGISTER 2 */ + + uint32_t adc_reserved4; + + union { + uint32_t R; + struct { + uint32_t CH31:1; + uint32_t CH30:1; + uint32_t CH29:1; + uint32_t CH28:1; + uint32_t CH27:1; + uint32_t CH26:1; + uint32_t CH25:1; + uint32_t CH24:1; + uint32_t CH23:1; + uint32_t CH22:1; + uint32_t CH21:1; + uint32_t CH20:1; + uint32_t CH19:1; + uint32_t CH18:1; + uint32_t CH17:1; + uint32_t CH16:1; + uint32_t CH15:1; + uint32_t CH14:1; + uint32_t CH13:1; + uint32_t CH12:1; + uint32_t CH11:1; + uint32_t CH10:1; + uint32_t CH9:1; + uint32_t CH8:1; + uint32_t CH7:1; + uint32_t CH6:1; + uint32_t CH5:1; + uint32_t CH4:1; + uint32_t CH3:1; + uint32_t CH2:1; + uint32_t CH1:1; + uint32_t CH0:1; + } B; + } NCMR0; /* NORMAL CONVERSION MASK REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t CH63:1; + uint32_t CH62:1; + uint32_t CH61:1; + uint32_t CH60:1; + uint32_t CH59:1; + uint32_t CH58:1; + uint32_t CH57:1; + uint32_t CH56:1; + uint32_t CH55:1; + uint32_t CH54:1; + uint32_t CH53:1; + uint32_t CH52:1; + uint32_t CH51:1; + uint32_t CH50:1; + uint32_t CH49:1; + uint32_t CH48:1; + uint32_t CH47:1; + uint32_t CH46:1; + uint32_t CH45:1; + uint32_t CH44:1; + uint32_t CH43:1; + uint32_t CH42:1; + uint32_t CH41:1; + uint32_t CH40:1; + uint32_t CH39:1; + uint32_t CH38:1; + uint32_t CH37:1; + uint32_t CH36:1; + uint32_t CH35:1; + uint32_t CH34:1; + uint32_t CH33:1; + uint32_t CH32:1; + } B; + } NCMR1; /* NORMAL CONVERSION MASK REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t PSR95:1; + uint32_t PSR94:1; + uint32_t PSR93:1; + uint32_t PSR92:1; + uint32_t PSR91:1; + uint32_t PSR90:1; + uint32_t PSR89:1; + uint32_t PSR88:1; + uint32_t PSR87:1; + uint32_t PSR86:1; + uint32_t PSR85:1; + uint32_t PSR84:1; + uint32_t PSR83:1; + uint32_t PSR82:1; + uint32_t PSR81:1; + uint32_t PSR80:1; + uint32_t PSR79:1; + uint32_t PSR78:1; + uint32_t PSR77:1; + uint32_t PSR76:1; + uint32_t PSR75:1; + uint32_t PSR74:1; + uint32_t PSR73:1; + uint32_t PSR72:1; + uint32_t PSR71:1; + uint32_t PSR70:1; + uint32_t PSR69:1; + uint32_t PSR68:1; + uint32_t PSR67:1; + uint32_t PSR66:1; + uint32_t PSR65:1; + uint32_t PSR64:1; + } B; + } NCMR2; /* NORMAL CONVERSION MASK REGISTER 2 */ + + uint32_t adc_reserved5; + + union { + uint32_t R; + struct { + uint32_t CH31:1; + uint32_t CH30:1; + uint32_t CH29:1; + uint32_t CH28:1; + uint32_t CH27:1; + uint32_t CH26:1; + uint32_t CH25:1; + uint32_t CH24:1; + uint32_t CH23:1; + uint32_t CH22:1; + uint32_t CH21:1; + uint32_t CH20:1; + uint32_t CH19:1; + uint32_t CH18:1; + uint32_t CH17:1; + uint32_t CH16:1; + uint32_t CH15:1; + uint32_t CH14:1; + uint32_t CH13:1; + uint32_t CH12:1; + uint32_t CH11:1; + uint32_t CH10:1; + uint32_t CH9:1; + uint32_t CH8:1; + uint32_t CH7:1; + uint32_t CH6:1; + uint32_t CH5:1; + uint32_t CH4:1; + uint32_t CH3:1; + uint32_t CH2:1; + uint32_t CH1:1; + uint32_t CH0:1; + } B; + } JCMR0; /* INJECTED CONVERSION MASK REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t CH63:1; + uint32_t CH62:1; + uint32_t CH61:1; + uint32_t CH60:1; + uint32_t CH59:1; + uint32_t CH58:1; + uint32_t CH57:1; + uint32_t CH56:1; + uint32_t CH55:1; + uint32_t CH54:1; + uint32_t CH53:1; + uint32_t CH52:1; + uint32_t CH51:1; + uint32_t CH50:1; + uint32_t CH49:1; + uint32_t CH48:1; + uint32_t CH47:1; + uint32_t CH46:1; + uint32_t CH45:1; + uint32_t CH44:1; + uint32_t CH43:1; + uint32_t CH42:1; + uint32_t CH41:1; + uint32_t CH40:1; + uint32_t CH39:1; + uint32_t CH38:1; + uint32_t CH37:1; + uint32_t CH36:1; + uint32_t CH35:1; + uint32_t CH34:1; + uint32_t CH33:1; + uint32_t CH32:1; + } B; + } JCMR1; /* INJECTED CONVERSION MASK REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t PSR95:1; + uint32_t PSR94:1; + uint32_t PSR93:1; + uint32_t PSR92:1; + uint32_t PSR91:1; + uint32_t PSR90:1; + uint32_t PSR89:1; + uint32_t PSR88:1; + uint32_t PSR87:1; + uint32_t PSR86:1; + uint32_t PSR85:1; + uint32_t PSR84:1; + uint32_t PSR83:1; + uint32_t PSR82:1; + uint32_t PSR81:1; + uint32_t PSR80:1; + uint32_t PSR79:1; + uint32_t PSR78:1; + uint32_t PSR77:1; + uint32_t PSR76:1; + uint32_t PSR75:1; + uint32_t PSR74:1; + uint32_t PSR73:1; + uint32_t PSR72:1; + uint32_t PSR71:1; + uint32_t PSR70:1; + uint32_t PSR69:1; + uint32_t PSR68:1; + uint32_t PSR67:1; + uint32_t PSR66:1; + uint32_t PSR65:1; + uint32_t PSR64:1; + } B; + } JCMR2; /* INJECTED CONVERSION MASK REGISTER 2 */ + + union { + uint32_t R; + struct { + uint32_t:15; + uint32_t OFFSETLOAD:1; + uint32_t:8; + uint32_t OFFSET_WORD:8; + } B; + } OFFWR; /* OFFSET WORD REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t DSD:8; + } B; + } DSDR; /* DECODE SIGNALS DELAY REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t PDED:8; + } B; + } PDEDR; /* DECODE SIGNALS DELAY REGISTER */ + + uint32_t adc_reserved6[9]; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t TEST_CTL:16; + } B; + } TCTLR; /* TEST CONTROL REGISTER */ + + uint32_t adc_reserved7[3]; + + union { + uint32_t R; + struct { + uint32_t:12; + uint32_t VALID:1; + uint32_t OVERW:1; + uint32_t RESULT:2; + uint32_t:6; + uint32_t CDATA:10; + } B; + } PRECDATAREG[32]; /* PRESISION DATA REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:12; + uint32_t VALID:1; + uint32_t OVERW:1; + uint32_t RESULT:2; + uint32_t:6; + uint32_t CDATA:10; + } B; + } INTDATAREG[32]; /* PRESISION DATA REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:12; + uint32_t VALID:1; + uint32_t OVERW:1; + uint32_t RESULT:2; + uint32_t:6; + uint32_t CDATA:10; + } B; + } EXTDATAREG[32]; /* PRESISION DATA REGISTER */ + + }; /* end of ADC_tag */ +/**************************************************************************/ +/* MODULE : AXBS Crossbar Switch (XBAR) */ +/**************************************************************************/ + struct XBAR_tag { + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; + uint32_t:1; + uint32_t MSTR6:3; + uint32_t:9; + uint32_t MSTR5:3; + uint32_t:1; + uint32_t MSTR3:3; + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:1; + } B; + } MPR0; /* Master Priority Register 0 */ + + uint32_t xbar_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR0; /* Master Priority Register 0 */ + + uint32_t xbar_reserved2[58]; + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; + uint32_t:1; + uint32_t MSTR6:3; + uint32_t:9; + uint32_t MSTR5:3; + uint32_t:1; + uint32_t MSTR3:3; + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:1; + } B; + } MPR1; /* Master Priority Register 1 */ + + uint32_t xbar_reserved3[3]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR1; /* Master Priority Register 1 */ + + uint32_t xbar_reserved4[58]; + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; + uint32_t:1; + uint32_t MSTR6:3; + uint32_t:9; + uint32_t MSTR5:3; + uint32_t:1; + uint32_t MSTR3:3; + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:1; + } B; + } MPR2; /* Master Priority Register 2 */ + + uint32_t xbar_reserved5[3]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR2; /* Master Priority Register 2 */ + + uint32_t xbar_reserved6[58]; + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; + uint32_t:1; + uint32_t MSTR6:3; + uint32_t:9; + uint32_t MSTR5:3; + uint32_t:1; + uint32_t MSTR3:3; + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:1; + } B; + } MPR3; /* Master Priority Register 3 */ + + uint32_t xbar_reserved7[3]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR3; /* Master Priority Register 3 */ + + uint32_t xbar_reserved8[186]; + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; + uint32_t:1; + uint32_t MSTR6:3; + uint32_t:9; + uint32_t MSTR5:3; + uint32_t:1; + uint32_t MSTR3:3; + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:1; + } B; + } MPR6; /* Master Priority Register 6 */ + + uint32_t xbar_reserved9[3]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR6; /* Master Priority Register 6 */ + + uint32_t xbar_reserved10[58]; + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; + uint32_t:1; + uint32_t MSTR6:3; + uint32_t:9; + uint32_t MSTR5:3; + uint32_t:1; + uint32_t MSTR3:3; + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:1; + } B; + } MPR7; /* Master Priority Register 7 */ + + uint32_t xbar_reserved11[3]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR7; /* Master Priority Register 7 */ + + uint32_t xbar_reserved12[506]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } MGPCR7; /* Master General Purpose Register 7 */ + + }; +/*************************************************************************/ +/* MODULE : CRP */ +/*************************************************************************/ + struct CRP_tag { + + union { + uint32_t R; + struct { + uint32_t IRCTRIMEN:1; + uint32_t:4; + uint32_t PREDIV:3; + uint32_t:4; + uint32_t EN128KIRC:1; + uint32_t EN32KOSC:1; + uint32_t ENLPOSC:1; + uint32_t EN40MOSC:1; + uint32_t:3; + uint32_t TRIM128IRC:5; + uint32_t:2; + uint32_t TRIM16IRC:6; + } B; + } CLKSRC; /* CLOCK SOURCE REGISTER */ + + uint32_t crp_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t CNTEN:1; + uint32_t RTCIE:1; + uint32_t FRZEN:1; + uint32_t ROVREN:1; + uint32_t RTCVAL:12; + uint32_t APIEN:1; + uint32_t APIIE:1; + uint32_t CLKSEL:2; + uint32_t DIV512EN:1; + uint32_t DIV32EN:1; + uint32_t APIVAL:10; + } B; + } RTCC; /* RTC CONTROL REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:2; + uint32_t RTCF:1; + uint32_t:15; + uint32_t APIF:1; + uint32_t:2; + uint32_t ROVRF:1; + uint32_t:10; + } B; + } RTSC; /* RTC STATUS REGISTER */ + + union { + uint32_t R; + struct { + uint32_t RTCCNT:32; + } B; + } RTCCNT; /* RTC Counter Register */ + + uint32_t crp_reserved2[9]; + + union { + uint32_t R; + struct { + uint32_t PWK31:2; + uint32_t PWK30:2; + uint32_t PWK29:2; + uint32_t PWK28:2; + uint32_t PWK27:2; + uint32_t PWK26:2; + uint32_t PWK25:2; + uint32_t PWK24:2; + uint32_t PWK23:2; + uint32_t PWK22:2; + uint32_t PWK21:2; + uint32_t PWK20:2; + uint32_t PWK19:2; + uint32_t PWK18:2; + uint32_t PWK17:2; + uint32_t PWK16:2; + } B; + } PWKENH; /* PIN WAKEUP ENABLE HIGH REGISTER */ + + union { + uint32_t R; + struct { + uint32_t PWK15:2; + uint32_t PWK14:2; + uint32_t PWK13:2; + uint32_t PWK12:2; + uint32_t PWK11:2; + uint32_t PWK10:2; + uint32_t PWK9:2; + uint32_t PWK8:2; + uint32_t PWK7:2; + uint32_t PWK6:2; + uint32_t PWK5:2; + uint32_t PWK4:2; + uint32_t PWK3:2; + uint32_t PWK2:2; + uint32_t PWK1:2; + uint32_t PWK0:2; + } B; + } PWKENL; /* PIN WAKEUP ENABLE LOW REGISTER */ + + union { + uint32_t R; + struct { + uint32_t PWKSRCIE31:1; + uint32_t PWKSRCIE30:1; + uint32_t PWKSRCIE29:1; + uint32_t PWKSRCIE28:1; + uint32_t PWKSRCIE27:1; + uint32_t PWKSRCIE26:1; + uint32_t PWKSRCIE25:1; + uint32_t PWKSRCIE24:1; + uint32_t PWKSRCIE23:1; + uint32_t PWKSRCIE22:1; + uint32_t PWKSRCIE21:1; + uint32_t PWKSRCIE20:1; + uint32_t PWKSRCIE19:1; + uint32_t PWKSRCIE18:1; + uint32_t PWKSRCIE17:1; + uint32_t PWKSRCIE16:1; + uint32_t PWKSRCIE15:1; + uint32_t PWKSRCIE14:1; + uint32_t PWKSRCIE13:1; + uint32_t PWKSRCIE12:1; + uint32_t PWKSRCIE11:1; + uint32_t PWKSRCIE10:1; + uint32_t PWKSRCIE9:1; + uint32_t PWKSRCIE8:1; + uint32_t PWKSRCIE7:1; + uint32_t PWKSRCIE6:1; + uint32_t PWKSRCIE5:1; + uint32_t PWKSRCIE4:1; + uint32_t PWKSRCIE3:1; + uint32_t PWKSRCIE2:1; + uint32_t PWKSRCIE1:1; + uint32_t PWKSRCIE0:1; + } B; + } PWKSRCIE; /* PIN WAKEUP SOURCE INTERRUPT ENABLE REGISTER */ + + union { + uint32_t R; + struct { + uint32_t PWKSRCIE31:1; + uint32_t PWKSRCIE30:1; + uint32_t PWKSRCIE29:1; + uint32_t PWKSRCIE28:1; + uint32_t PWKSRCIE27:1; + uint32_t PWKSRCIE26:1; + uint32_t PWKSRCIE25:1; + uint32_t PWKSRCIE24:1; + uint32_t PWKSRCIE23:1; + uint32_t PWKSRCIE22:1; + uint32_t PWKSRCIE21:1; + uint32_t PWKSRCIE20:1; + uint32_t PWKSRCIE19:1; + uint32_t PWKSRCIE18:1; + uint32_t PWKSRCIE17:1; + uint32_t PWKSRCIE16:1; + uint32_t PWKSRCIE15:1; + uint32_t PWKSRCIE14:1; + uint32_t PWKSRCIE13:1; + uint32_t PWKSRCIE12:1; + uint32_t PWKSRCIE11:1; + uint32_t PWKSRCIE10:1; + uint32_t PWKSRCIE9:1; + uint32_t PWKSRCIE8:1; + uint32_t PWKSRCIE7:1; + uint32_t PWKSRCIE6:1; + uint32_t PWKSRCIE5:1; + uint32_t PWKSRCIE4:1; + uint32_t PWKSRCIE3:1; + uint32_t PWKSRCIE2:1; + uint32_t PWKSRCIE1:1; + uint32_t PWKSRCIE0:1; + } B; + } PWKSRCF; /* PIN WAKEUP SOURCE FLAG REGISTER */ + + union { + uint32_t R; + struct { + uint32_t Z6VECB:20; + uint32_t:10; + uint32_t Z6RST:1; + uint32_t VLE:1; + } B; + } Z6VEC; /* Z6 RESET VECTOR REGISTER */ + + union { + uint32_t R; + struct { + uint32_t Z0VECB:30; + uint32_t Z0RST:1; + uint32_t:1; + } B; + } Z0VEC; /* Z0 RESET VECTOR REGISTER */ + + union { + uint32_t R; + struct { + uint32_t RECPTR:30; + uint32_t FASTREC:1; + uint32_t:1; + } B; + } RECPTR; /* RESET RECOVERY POINTER REGISTER */ + + uint32_t crp_reserved3; + + union { + uint32_t R; + struct { + uint32_t SLEEPF:1; + uint32_t:12; + uint32_t RTCOVRWKF:1; + uint32_t RTCWKF:1; + uint32_t APIWKF:1; + uint32_t SLEEP:1; + uint32_t:4; + uint32_t RAMSEL:3; + uint32_t:4; + uint32_t WKCLKSEL:1; + uint32_t RTCOVRWKEN:1; + uint32_t RTCWKEN:1; + uint32_t APIWKEN:1; + } B; + } PSCR; /* POWER STATUS AND CONTROL REGISTER */ + + uint32_t crp_reserved4[3]; + + union { + uint32_t R; + struct { + uint32_t LVI5LOCK:1; + uint32_t LVI5RE:1; + uint32_t:7; + uint32_t LVI5HIE:1; + uint32_t LVI5NIE:1; + uint32_t LVI5IE:1; + uint32_t:2; + uint32_t FRIE:1; + uint32_t FDIS:1; + uint32_t:9; + uint32_t LVI5HIF:1; + uint32_t LVI5NF:1; + uint32_t LVI5F:1; + uint32_t:2; + uint32_t FRF:1; + uint32_t FRDY:1; + } B; + } SOCSC; /* LVI Status and Control Register */ + + }; /* end of CRP_tag */ +/*************************************************************************/ +/* MODULE : CTU */ +/*************************************************************************/ + struct CTU_tag { + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t TRGIEN:1; + uint32_t TRGI:1; + uint32_t:2; + uint32_t PRESC_CONF:4; + } B; + } CSR; /* Control Status Register */ + + union { + uint32_t R; + struct { + uint32_t:23; + uint32_t SV:9; + } B; + } SVR[7]; /* Start Value Register */ + + union { + uint32_t R; + struct { + uint32_t:23; + uint32_t CV:9; + } B; + } CVR[4]; /* Current Value Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t TM:1; + uint32_t:1; + uint32_t COUNT_GROUP:2; + uint32_t:1; + uint32_t DELAY_INDEX:3; + uint32_t CLR_FG:1; + uint32_t:1; + uint32_t CHANNEL_VALUE:6; + } B; + } EVTCFGR[33]; /* Event Configuration Register */ + + }; /* end of CTU_tag */ +/*************************************************************************/ +/* MODULE : DMAMUX */ +/*************************************************************************/ + struct DMAMUX_tag { + union { + uint8_t R; + struct { + uint8_t ENBL:1; + uint8_t TRIG:1; + uint8_t SOURCE:6; + } B; + } CHCONFIG[32]; /* DMA Channel Configuration Register */ + + }; /* end of DMAMUX_tag */ +/*************************************************************************/ +/* MODULE : DSPI */ +/*************************************************************************/ + struct DSPI_tag { + union DSPI_MCR_tag { + uint32_t R; + struct { + uint32_t MSTR:1; + uint32_t CONT_SCKE:1; + uint32_t DCONF:2; + uint32_t FRZ:1; + uint32_t MTFE:1; + uint32_t PCSSE:1; + uint32_t ROOE:1; + uint32_t:2; + uint32_t PCSIS5:1; + uint32_t PCSIS4:1; + uint32_t PCSIS3:1; + uint32_t PCSIS2:1; + uint32_t PCSIS1:1; + uint32_t PCSIS0:1; + uint32_t:1; + uint32_t MDIS:1; + uint32_t DIS_TXF:1; + uint32_t DIS_RXF:1; + uint32_t CLR_TXF:1; + uint32_t CLR_RXF:1; + uint32_t SMPL_PT:2; + uint32_t:7; + uint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t dspi_reserved1; + + union { + uint32_t R; + struct { + uint32_t SPI_TCNT:16; + uint32_t:16; + } B; + } TCR; + + union DSPI_CTAR_tag { + uint32_t R; + struct { + uint32_t DBR:1; + uint32_t FMSZ:4; + uint32_t CPOL:1; + uint32_t CPHA:1; + uint32_t LSBFE:1; + uint32_t PCSSCK:2; + uint32_t PASC:2; + uint32_t PDT:2; + uint32_t PBR:2; + uint32_t CSSCK:4; + uint32_t ASC:4; + uint32_t DT:4; + uint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers */ + + union DSPI_SR_tag { + uint32_t R; + struct { + uint32_t TCF:1; + uint32_t TXRXS:1; + uint32_t:1; + uint32_t EOQF:1; + uint32_t TFUF:1; + uint32_t:1; + uint32_t TFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t TXCTR:4; + uint32_t TXNXTPTR:4; + uint32_t RXCTR:4; + uint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register */ + + union DSPI_RSER_tag { + uint32_t R; + struct { + uint32_t TCFRE:1; + uint32_t:2; + uint32_t EOQFRE:1; + uint32_t TFUFRE:1; + uint32_t:1; + uint32_t TFFFRE:1; + uint32_t TFFFDIRS:1; + uint32_t:4; + uint32_t RFOFRE:1; + uint32_t:1; + uint32_t RFDFRE:1; + uint32_t RFDFDIRS:1; + uint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register */ + + union DSPI_PUSHR_tag { + uint32_t R; + struct { + uint32_t CONT:1; + uint32_t CTAS:3; + uint32_t EOQ:1; + uint32_t CTCNT:1; + uint32_t:4; + uint32_t PCS5:1; + uint32_t PCS4:1; + uint32_t PCS3:1; + uint32_t PCS2:1; + uint32_t PCS1:1; + uint32_t PCS0:1; + uint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register */ + + union DSPI_POPR_tag { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register */ + + union { + uint32_t R; + struct { + uint32_t TXCMD:16; + uint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_txf[12]; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_rxf[12]; + + union { + uint32_t R; + struct { + uint32_t:11; + uint32_t TSBC:1; + uint32_t TXSS:1; + uint32_t:2; + uint32_t CID:1; + uint32_t DCONT:1; + uint32_t DSICTAS:3; + uint32_t:6; + uint32_t DPCS5:1; + uint32_t DPCS4:1; + uint32_t DPCS3:1; + uint32_t DPCS2:1; + uint32_t DPCS1:1; + uint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t SER_DATA:32; + } B; + } SDR; /* DSI Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t ASER_DATA:32; + } B; + } ASDR; /* DSI Alternate Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t COMP_DATA:32; + } B; + } COMPR; /* DSI Transmit Comparison Register */ + + union { + uint32_t R; + struct { + uint32_t DESER_DATA:32; + } B; + } DDR; /* DSI deserialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t TSBCNT:5; + uint32_t:16; + uint32_t DPCS1_7:1; + uint32_t DPCS1_6:1; + uint32_t DPCS1_5:1; + uint32_t DPCS1_4:1; + uint32_t DPCS1_3:1; + uint32_t DPCS1_2:1; + uint32_t DPCS1_1:1; + uint32_t DPCS1_0:1; + } B; + } DSICR1; /* DSI Configuration Register 1 */ + + }; /* end of DSPI_tag */ +/*************************************************************************/ +/* MODULE : ECSM */ +/*************************************************************************/ + struct ECSM_tag { + + uint32_t ecsm_reserved1[9]; + + union { + uint32_t R; + struct { + uint32_t FXSBE0:1; + uint32_t FXSBE1:1; + uint32_t FXSBE2:1; + uint32_t FXSBE3:1; + uint32_t:2; + uint32_t FXSBE6:1; + uint32_t FXSBE7:1; + uint32_t RBEN:1; + uint32_t WBEN:1; + uint32_t ACCERR:1; + uint32_t:21; + } B; + } FBOMCR; /* FEC Burst Optimisation Master Control Register */ + + uint8_t ecsm_reserved2[27]; + + union { + uint8_t R; + struct { + uint8_t:2; + uint8_t EPR1BR:1; + uint8_t EPF1BR:1; + uint8_t:2; + uint8_t EPRNCR:1; + uint8_t EPFNCR:1; + } B; + } ECR; /* ECC Configuration Register */ + + uint8_t ecsm_reserved3[3]; + + union { + uint8_t R; + struct { + uint8_t:2; + uint8_t PR1BC:1; + uint8_t PF1BC:1; + uint8_t:2; + uint8_t PRNCE:1; + uint8_t PFNCE:1; + } B; + } ESR; /* ECC Status Register */ + + uint16_t ecsm_reserved4; + + union { + uint16_t R; + struct { + uint16_t:2; + uint16_t FRC1BI:1; + uint16_t FR11BI:1; + uint16_t:2; + uint16_t FRCNCI:1; + uint16_t FR1NCI:1; + uint16_t PREI_SEL:1; + uint16_t ERRBIT:7; + } B; + } EEGR; /* ECC Error Generation Register */ + + uint32_t ecsm_reserved5; + + union { + uint32_t R; + struct { + uint32_t PFEAR:32; + } B; + } PFEAR; /* Platform Flash ECC Address Register */ + + uint16_t ecsm_reserved6; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t PFEMR:4; + } B; + } PFEMR; /* Platform Flash ECC Address Register */ + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROTECTION:4; + } B; + } PFEAT; /* Flash ECC Attributes Register */ + + union { + uint32_t R; + struct { + uint32_t PFEDRH:32; + } B; + } PFEDRH; /* Flash ECC Data High Register */ + + union { + uint32_t R; + struct { + uint32_t PFEDRL:32; + } B; + } PFEDRL; /* Flash ECC Data Low Register */ + + union { + uint32_t R; + struct { + uint32_t PREAR:32; + } B; + } PREAR; /* Platform RAM ECC Address Register */ + + uint16_t ecsm_reserved8; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t PREMR:4; + } B; + } PREMR; /* RAM ECC Attributes Register */ + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROTECTION:4; + } B; + } PREAT; /* Platform RAM ECC Attributes Register */ + + union { + uint32_t R; + struct { + uint32_t PREDR:32; + } B; + } PREDRH; /* Platform RAM ECC Data Low Register High */ + + union { + uint32_t R; + struct { + uint32_t PREDR:32; + } B; + } PREDRL; /* Platform RAM ECC Data Low Register Low */ + + }; /* end of ECSM_tag */ +/*************************************************************************/ +/* MODULE : EMIOS */ +/*************************************************************************/ + struct EMIOS_tag { + union EMIOS_MCR_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t GTBE:1; + uint32_t:1; + uint32_t GPREN:1; + uint32_t:10; + uint32_t GPRE:8; + uint32_t:8; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t F31:1; + uint32_t F30:1; + uint32_t F29:1; + uint32_t F28:1; + uint32_t F27:1; + uint32_t F26:1; + uint32_t F25:1; + uint32_t F24:1; + uint32_t F23:1; + uint32_t F22:1; + uint32_t F21:1; + uint32_t F20:1; + uint32_t F19:1; + uint32_t F18:1; + uint32_t F17:1; + uint32_t F16:1; + uint32_t F15:1; + uint32_t F14:1; + uint32_t F13:1; + uint32_t F12:1; + uint32_t F11:1; + uint32_t F10:1; + uint32_t F9:1; + uint32_t F8:1; + uint32_t F7:1; + uint32_t F6:1; + uint32_t F5:1; + uint32_t F4:1; + uint32_t F3:1; + uint32_t F2:1; + uint32_t F1:1; + uint32_t F0:1; + } B; + } GFR; /* Global FLAG Register */ + + union { + uint32_t R; + struct { + uint32_t OU31:1; + uint32_t OU30:1; + uint32_t OU29:1; + uint32_t OU28:1; + uint32_t OU27:1; + uint32_t OU26:1; + uint32_t OU25:1; + uint32_t OU24:1; + uint32_t OU23:1; + uint32_t OU22:1; + uint32_t OU21:1; + uint32_t OU20:1; + uint32_t OU19:1; + uint32_t OU18:1; + uint32_t OU17:1; + uint32_t OU16:1; + uint32_t OU15:1; + uint32_t OU14:1; + uint32_t OU13:1; + uint32_t OU12:1; + uint32_t OU11:1; + uint32_t OU10:1; + uint32_t OU9:1; + uint32_t OU8:1; + uint32_t OU7:1; + uint32_t OU6:1; + uint32_t OU5:1; + uint32_t OU4:1; + uint32_t OU3:1; + uint32_t OU2:1; + uint32_t OU1:1; + uint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register */ + + union { + uint32_t R; + struct { + uint32_t UC31:1; + uint32_t UC30:1; + uint32_t UC29:1; + uint32_t UC28:1; + uint32_t UC27:1; + uint32_t UC26:1; + uint32_t UC25:1; + uint32_t UC24:1; + uint32_t UC23:1; + uint32_t UC22:1; + uint32_t UC21:1; + uint32_t UC20:1; + uint32_t UC19:1; + uint32_t UC18:1; + uint32_t UC17:1; + uint32_t UC16:1; + uint32_t UC15:1; + uint32_t UC14:1; + uint32_t UC13:1; + uint32_t UC12:1; + uint32_t UC11:1; + uint32_t UC10:1; + uint32_t UC9:1; + uint32_t UC8:1; + uint32_t UC7:1; + uint32_t UC6:1; + uint32_t UC5:1; + uint32_t UC4:1; + uint32_t UC3:1; + uint32_t UC2:1; + uint32_t UC1:1; + uint32_t UC0:1; + } B; + } UCDIS; /* Disable Channel Register */ + + uint32_t emios_reserved1[4]; + + struct EMIOS_CH_tag { + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t A:16; /* Channel A Data Register */ + } B; + } CADR; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t B:16; /* Channel B Data Register */ + } B; + } CBDR; + + union { + uint32_t R; /* Channel Counter Register */ + struct { + uint32_t:16; + uint32_t C:16; /* Channel C Data Register */ + } B; + } CCNTR; + + union EMIOS_CCR_tag { + uint32_t R; + struct { + uint32_t FREN:1; + uint32_t ODIS:1; + uint32_t ODISSL:2; + uint32_t UCPRE:2; + uint32_t UCPREN:1; + uint32_t DMA:1; + uint32_t:1; + uint32_t IF:4; + uint32_t FCK:1; + uint32_t FEN:1; + uint32_t:3; + uint32_t FORCMA:1; + uint32_t FORCMB:1; + uint32_t:1; + uint32_t BSL:2; + uint32_t EDSEL:1; + uint32_t EDPOL:1; + uint32_t MODE:7; + } B; + } CCR; /* Channel Control Register */ + + union EMIOS_CSR_tag { + uint32_t R; + struct { + uint32_t OVR:1; + uint32_t:15; + uint32_t OVFL:1; + uint32_t:12; + uint32_t UCIN:1; + uint32_t UCOUT:1; + uint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register */ + + union { + uint32_t R; /* Alternate Channel A Data Register */ + } ALTA; + + uint32_t emios_channel_reserved[2]; + + } CH[32]; + + }; /* end of EMIOS_tag */ +/*************************************************************************/ +/* MODULE : eSCI */ +/*************************************************************************/ + struct ESCI_tag { + union ESCI_CR1_tag { + uint32_t R; + struct { + uint32_t:3; + uint32_t SBR:13; + uint32_t LOOPS:1; + uint32_t:1; + uint32_t RSRC:1; + uint32_t M:1; + uint32_t WAKE:1; + uint32_t ILT:1; + uint32_t PE:1; + uint32_t PT:1; + uint32_t TIE:1; + uint32_t TCIE:1; + uint32_t RIE:1; + uint32_t ILIE:1; + uint32_t TE:1; + uint32_t RE:1; + uint32_t RWU:1; + uint32_t SBK:1; + } B; + } CR1; /* Control Register 1 */ + + union ESCI_CR2_tag { + uint16_t R; + struct { + uint16_t MDIS:1; + uint16_t FBR:1; + uint16_t BSTP:1; + uint16_t IEBERR:1; + uint16_t RXDMA:1; + uint16_t TXDMA:1; + uint16_t BRK13:1; + uint16_t TXDIR:1; + uint16_t BESM13:1; + uint16_t SBSTP:1; + uint16_t RXPOL:1; + uint16_t PMSK:1; + uint16_t ORIE:1; + uint16_t NFIE:1; + uint16_t FEIE:1; + uint16_t PFIE:1; + } B; + } CR2; /* Control Register 2 */ + + union ESCI_DR_tag { + uint16_t R; + struct { + uint16_t RN:1; + uint16_t TN:1; + uint16_t ERR:1; + uint16_t:1; + uint16_t RD_11:4; + uint16_t D:8; + } B; + } DR; /* Data Register */ + + union ESCI_SR_tag { + uint32_t R; + struct { + uint32_t TDRE:1; + uint32_t TC:1; + uint32_t RDRF:1; + uint32_t IDLE:1; + uint32_t OR:1; + uint32_t NF:1; + uint32_t FE:1; + uint32_t PF:1; + uint32_t:3; + uint32_t BERR:1; + uint32_t:2; + uint32_t TACT:1; + uint32_t RACT:1; + uint32_t RXRDY:1; + uint32_t TXRDY:1; + uint32_t LWAKE:1; + uint32_t STO:1; + uint32_t PBERR:1; + uint32_t CERR:1; + uint32_t CKERR:1; + uint32_t FRC:1; + uint32_t:6; + uint32_t UREQ:1; + uint32_t OVFL:1; + } B; + } SR; /* Status Register */ + + union { + uint32_t R; + struct { + uint32_t LRES:1; + uint32_t WU:1; + uint32_t WUD0:1; + uint32_t WUD1:1; + uint32_t:2; + uint32_t PRTY:1; + uint32_t LIN:1; + uint32_t RXIE:1; + uint32_t TXIE:1; + uint32_t WUIE:1; + uint32_t STIE:1; + uint32_t PBIE:1; + uint32_t CIE:1; + uint32_t CKIE:1; + uint32_t FCIE:1; + uint32_t:6; + uint32_t UQIE:1; + uint32_t OFIE:1; + uint32_t:8; + } B; + } LCR; /* LIN Control Register */ + + union { + uint8_t R; + } LTR; /* LIN Transmit Register */ + + uint8_t eSCI_reserved1[3]; + + union { + uint8_t R; + } LRR; /* LIN Recieve Register */ + + uint8_t eSCI_reserved2[3]; + + union { + uint16_t R; + } LPR; /* LIN CRC Polynom Register */ + + union { + uint8_t R; + struct { + uint8_t:3; + uint8_t SYNM:1; + uint8_t EROE:1; + uint8_t ERFE:1; + uint8_t ERPE:1; + uint8_t M2:1; + } B; + } CR3; /* Control Register 3 */ + + uint8_t eSCI_reserved3[5]; + }; /* end of ESCI_tag */ +/*************************************************************************/ +/* MODULE : FEC */ +/*************************************************************************/ + struct FEC_tag { + + uint32_t fec_reserved_start; + + union { + uint32_t R; + struct { + uint32_t HBERR:1; + uint32_t BABR:1; + uint32_t BABT:1; + uint32_t GRA:1; + uint32_t TXF:1; + uint32_t TXB:1; + uint32_t RXF:1; + uint32_t RXB:1; + uint32_t MII:1; + uint32_t EBERR:1; + uint32_t LC:1; + uint32_t RL:1; + uint32_t UN:1; + uint32_t:19; + } B; + } EIR; /* Interrupt Event Register */ + + union { + uint32_t R; + struct { + uint32_t HBERR:1; + uint32_t BABR:1; + uint32_t BABT:1; + uint32_t GRA:1; + uint32_t TXF:1; + uint32_t TXB:1; + uint32_t RXF:1; + uint32_t RXB:1; + uint32_t MII:1; + uint32_t EBERR:1; + uint32_t LC:1; + uint32_t RL:1; + uint32_t UN:1; + uint32_t:19; + } B; + } EIMR; /* Interrupt Mask Register */ + + uint32_t fec_reserved_eimr; + + union { + uint32_t R; + struct { + uint32_t:7; + uint32_t R_DES_ACTIVE:1; + uint32_t:24; + } B; + } RDAR; /* Receive Descriptor Active Register */ + + union { + uint32_t R; + struct { + uint32_t:7; + uint32_t X_DES_ACTIVE:1; + uint32_t:24; + } B; + } TDAR; /* Transmit Descriptor Active Register */ + + uint32_t fec_reserved_tdar[3]; + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t ETHER_EN:1; + uint32_t RESET:1; + } B; + } ECR; /* Ethernet Control Register */ + + uint32_t fec_reserved_ecr[6]; + + union { + uint32_t R; + struct { + uint32_t ST:2; + uint32_t OP:2; + uint32_t PA:5; + uint32_t RA:5; + uint32_t TA:2; + uint32_t DATA:16; + } B; + } MMFR; /* MII Data Register */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t DIS_PREAMBLE:1; + uint32_t MII_SPEED:6; + uint32_t:1; + } B; + } MSCR; /* MII Speed Control Register */ + + uint32_t fec_reserved_mscr[7]; + + union { + uint32_t R; + struct { + uint32_t MIB_DISABLE:1; + uint32_t MIB_IDLE:1; + uint32_t:30; + } B; + } MIBC; /* MIB Control Register */ + + uint32_t fec_reserved_mibc[7]; + + union { + uint32_t R; + struct { + uint32_t:5; + uint32_t MAX_FL:11; + uint32_t:10; + uint32_t FCE:1; + uint32_t BC_REJ:1; + uint32_t PROM:1; + uint32_t MII_MODE:1; + uint32_t DRT:1; + uint32_t LOOP:1; + } B; + } RCR; /* Receive Control Register */ + + uint32_t fec_reserved_rcr[15]; + + union { + uint32_t R; + struct { + uint32_t:27; + uint32_t RFC_PAUSE:1; + uint32_t TFC_PAUSE:1; + uint32_t FDEN:1; + uint32_t HBC:1; + uint32_t GTS:1; + } B; + } TCR; /* Transmit Control Register */ + + uint32_t fec_reserved_tcr[7]; + + union { + uint32_t R; + struct { + uint32_t PADDR1:32; + } B; + } PALR; /* Physical Address Low Register */ + + union { + uint32_t R; + struct { + uint32_t PADDR2:16; + uint32_t TYPE:16; + } B; + } PAUR; /* Physical Address High + Type Register */ + + union { + uint32_t R; + struct { + uint32_t OPCODE:16; + uint32_t PAUSE_DUR:16; + } B; + } OPD; /* Opcode/Pause Duration Register */ + + uint32_t fec_reserved_opd[10]; + + union { + uint32_t R; + struct { + uint32_t IADDR1:32; + } B; + } IAUR; /* Descriptor Individual Upper Address Register */ + + union { + uint32_t R; + struct { + uint32_t IADDR2:32; + } B; + } IALR; /* Descriptor Individual Lower Address Register */ + + union { + uint32_t R; + struct { + uint32_t GADDR1:32; + } B; + } GAUR; /* Descriptor Group Upper Address Register */ + + union { + uint32_t R; + struct { + uint32_t GADDR2:32; + } B; + } GALR; /* Descriptor Group Lower Address Register */ + + uint32_t fec_reserved_galr[7]; + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t X_WMRK:2; + } B; + } TFWR; /* FIFO Transmit FIFO Watermark Register */ + + uint32_t fec_reserved_tfwr; + + union { + uint32_t R; + struct { + uint32_t:22; + uint32_t R_BOUND:8; + uint32_t:2; + } B; + } FRBR; /* FIFO Receive Bound Register */ + + union { + uint32_t R; + struct { + uint32_t:22; + uint32_t R_FSTART:8; + uint32_t:2; + } B; + } FRSR; /* FIFO Receive Start Register */ + + uint32_t fec_reserved_frsr[11]; + + union { + uint32_t R; + struct { + uint32_t R_DES_START:30; + uint32_t:2; + } B; + } ERDSR; /* Receive Descriptor Ring Start Register */ + + union { + uint32_t R; + struct { + uint32_t X_DES_START:30; + uint32_t:2; + } B; + } ETDSR; /* Transmit Descriptor Ring Start Register */ + + union { + uint32_t R; + struct { + uint32_t:21; + uint32_t R_BUF_SIZE:7; + uint32_t:4; + } B; + } EMRBR; /* Receive Buffer Size Register */ + + uint32_t fec_reserved_emrbr[29]; + + union { + uint32_t R; + } RMON_T_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } RMON_T_PACKETS; /* RMON Tx packet count */ + + union { + uint32_t R; + } RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */ + + union { + uint32_t R; + } RMON_T_MC_PKT; /* RMON Tx Multicast Packets */ + + union { + uint32_t R; + } RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */ + + union { + uint32_t R; + } RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */ + + union { + uint32_t R; + } RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */ + + union { + uint32_t R; + } RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */ + + union { + uint32_t R; + } RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */ + + union { + uint32_t R; + } RMON_T_COL; /* RMON Tx collision count */ + + union { + uint32_t R; + } RMON_T_P64; /* RMON Tx 64 byte packets */ + + union { + uint32_t R; + } RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */ + + union { + uint32_t R; + } RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */ + + union { + uint32_t R; + } RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */ + + union { + uint32_t R; + } RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */ + + union { + uint32_t R; + } RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */ + + union { + uint32_t R; + } RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */ + + union { + uint32_t R; + } RMON_T_OCTETS; /* RMON Tx Octets */ + + union { + uint32_t R; + } IEEE_T_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } IEEE_T_FRAME_OK; /* Frames Transmitted OK */ + + union { + uint32_t R; + } IEEE_T_1COL; /* Frames Transmitted with Single Collision */ + + union { + uint32_t R; + } IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */ + + union { + uint32_t R; + } IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */ + + union { + uint32_t R; + } IEEE_T_LCOL; /* Frames Transmitted with Late Collision */ + + union { + uint32_t R; + } IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */ + + union { + uint32_t R; + } IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */ + + union { + uint32_t R; + } IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */ + + union { + uint32_t R; + } IEEE_T_SQE; /* Frames Transmitted with SQE Error */ + + union { + uint32_t R; + } IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */ + + union { + uint32_t R; + } IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */ + + uint32_t fec_reserved_rmon_t_octets_ok[2]; + + union { + uint32_t R; + } RMON_R_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } RMON_R_PACKETS; /* RMON Rx packet count */ + + union { + uint32_t R; + } RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */ + + union { + uint32_t R; + } RMON_R_MC_PKT; /* RMON Rx Multicast Packets */ + + union { + uint32_t R; + } RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */ + + union { + uint32_t R; + } RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */ + + union { + uint32_t R; + } RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */ + + union { + uint32_t R; + } RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */ + + union { + uint32_t R; + } RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */ + + uint32_t fec_reserved_rmon_r_jab; + + union { + uint32_t R; + } RMON_R_P64; /* RMON Rx 64 byte packets */ + + union { + uint32_t R; + } RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */ + + union { + uint32_t R; + } RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */ + + union { + uint32_t R; + } RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */ + + union { + uint32_t R; + } RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */ + + union { + uint32_t R; + } RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */ + + union { + uint32_t R; + } RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */ + + union { + uint32_t R; + } RMON_R_OCTETS; /* RMON Rx Octets */ + + union { + uint32_t R; + } IEEE_R_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } IEEE_R_FRAME_OK; /* Frames Received OK */ + + union { + uint32_t R; + } IEEE_R_CRC; /* Frames Received with CRC Error */ + + union { + uint32_t R; + } IEEE_R_ALIGN; /* Frames Received with Alignment Error */ + + union { + uint32_t R; + } IEEE_R_MACERR; /* Receive Fifo Overflow count */ + + union { + uint32_t R; + } IEEE_R_FDXFC; /* Flow Control Pause frames received */ + + union { + uint32_t R; + } IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */ + + }; /* end of FEC_tag */ +/*************************************************************************/ +/* MODULE : FLASH */ +/*************************************************************************/ + struct FLASH_tag { + union { + uint32_t R; + struct { + uint32_t:5; + uint32_t SIZE:3; + uint32_t:1; + uint32_t LAS:3; + uint32_t:3; + uint32_t MAS:1; + uint32_t EER:1; + uint32_t RWE:1; + uint32_t SBC:1; + uint32_t:1; + uint32_t PEAS:1; + uint32_t DONE:1; + uint32_t PEG:1; + uint32_t:4; + uint32_t PGM:1; + uint32_t PSUS:1; + uint32_t ERS:1; + uint32_t ESUS:1; + uint32_t EHV:1; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t LME:1; + uint32_t:10; + uint32_t SLOCK:1; + uint32_t:2; + uint32_t MLOCK:2; + uint32_t:6; + uint32_t LLOCK:10; + } B; + } LML; /* Low/Mid-address space block locking Register */ + + union { + uint32_t R; + struct { + uint32_t HBE:1; + uint32_t:25; + uint32_t HBLOCK:6; + } B; + } HBL; /* High-address space block locking Register */ + + union { + uint32_t R; + struct { + uint32_t SLE:1; + uint32_t:10; + uint32_t SSLOCK:1; + uint32_t:2; + uint32_t SMLOCK:2; + uint32_t:6; + uint32_t SLLOCK:10; + } B; + } SLL; /* Secondary low/mid-address space block locking Register */ + + union { + uint32_t R; + struct { + uint32_t:14; + uint32_t MSEL:2; + uint32_t:6; + uint32_t LSEL:10; + } B; + } LMS; /* Low/Mid-address space block locking Register */ + + union { + uint32_t R; + struct { + uint32_t:26; + uint32_t HBSEL:6; + } B; + } HBS; /* High-address space block locking Register */ + + union { + uint32_t R; + struct { + uint32_t SAD:1; + uint32_t:10; + uint32_t ADDR:18; + uint32_t:3; + } B; + } ADR; /* Address Register */ + + union { + uint32_t R; + struct { + uint32_t LBCFG:4; + uint32_t ARB:1; + uint32_t PRI:1; + uint32_t:1; + uint32_t M8PFE:1; + uint32_t:1; + uint32_t M6PFE:1; + uint32_t M5PFE:1; + uint32_t M4PFE:1; + uint32_t:1; + uint32_t M2PFE:1; + uint32_t M1PFE:1; + uint32_t M0PFE:1; + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + uint32_t:1; + uint32_t DPFEN:1; + uint32_t:1; + uint32_t IPFEN:1; + uint32_t:1; + uint32_t PFLIM:2; + uint32_t BFEN:1; + } B; + } PFCRP0; /* Platform Flash Configuration Register for Port 0 */ + + union { + uint32_t R; + struct { + uint32_t LBCFG:4; + uint32_t:3; + uint32_t M8PFE:1; + uint32_t:1; + uint32_t M6PFE:1; + uint32_t M5PFE:1; + uint32_t M4PFE:1; + uint32_t:1; + uint32_t M2PFE:1; + uint32_t M1PFE:1; + uint32_t M0PFE:1; + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + uint32_t:1; + uint32_t DPFEN:1; + uint32_t:1; + uint32_t IPFEN:1; + uint32_t:1; + uint32_t PFLIM:2; + uint32_t BFEN:1; + } B; + } PFCRP1; /* Platform Flash Configuration Register for Port 1 */ + + union { + uint32_t R; + struct { + uint32_t M7AP:2; + uint32_t M6AP:2; + uint32_t M5AP:2; + uint32_t M4AP:2; + uint32_t M3AP:2; + uint32_t M2AP:2; + uint32_t M1AP:2; + uint32_t M0AP:2; + uint32_t SHSACC:4; + uint32_t:4; + uint32_t SHDACC:4; + uint32_t:4; + } B; + } PFAPR; /* Platform Flash access protection Register */ + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t SACC:31; + } B; + } PFSACC; /* PFlash Supervisor Access Control Register */ + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t DACC:31; + } B; + } PFDACC; /* PFlash Data Access Control Register */ + + uint32_t FLASH_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t UTE:1; + uint32_t SCBE:1; + uint32_t:6; + uint32_t DSI:8; + uint32_t:10; + uint32_t MRE:1; + uint32_t MRV:1; + uint32_t EIE:1; + uint32_t AIS:1; + uint32_t AIE:1; + uint32_t AID:1; + } B; + } UT0; /* User Test Register 0 */ + + union { + uint32_t R; + struct { + uint32_t DAI:32; + } B; + } UT1; /* User Test Register 1 */ + + union { + uint32_t R; + struct { + uint32_t DAI:32; + } B; + } UT2; /* User Test Register 2 */ + + union { + uint32_t R; + struct { + uint32_t MISR:32; + } B; + } MISR[5]; /* Multiple Input Signature Register */ + + }; /* end of FLASH_tag */ +/*************************************************************************/ +/* MODULE : FlexCAN */ +/*************************************************************************/ + struct FLEXCAN_tag { + union { + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t FEN:1; + uint32_t HALT:1; + uint32_t NOTRDY:1; + uint32_t WAKMSK:1; + uint32_t SOFTRST:1; + uint32_t FRZACK:1; + uint32_t SUPV:1; + uint32_t SLFWAK:1; + uint32_t WRNEN:1; + uint32_t LPMACK:1; + uint32_t WAKSRC:1; + uint32_t DOZE:1; + uint32_t SRXDIS:1; + uint32_t BCC:1; + uint32_t:2; + uint32_t LPRIO_EN:1; + uint32_t AEN:1; + uint32_t:2; + uint32_t IDAM:2; + uint32_t:2; + uint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t PRESDIV:8; + uint32_t RJW:2; + uint32_t PSEG1:3; + uint32_t PSEG2:3; + uint32_t BOFFMSK:1; + uint32_t ERRMSK:1; + uint32_t CLKSRC:1; + uint32_t LPB:1; + uint32_t TWRNMSK:1; + uint32_t RWRNMSK:1; + uint32_t:2; + uint32_t SMP:1; + uint32_t BOFFREC:1; + uint32_t TSYN:1; + uint32_t LBUF:1; + uint32_t LOM:1; + uint32_t PROPSEG:3; + } B; + } CTRL; /* Control Register */ + + union { + uint32_t R; + } TIMER; /* Free Running Timer */ + + uint32_t FLEXCAN_reserved1; + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXECNT:8; + uint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + uint32_t R; + struct { + uint32_t:14; + uint32_t TWRNINT:1; + uint32_t RWRNINT:1; + uint32_t BIT1ERR:1; + uint32_t BIT0ERR:1; + uint32_t ACKERR:1; + uint32_t CRCERR:1; + uint32_t FRMERR:1; + uint32_t STFERR:1; + uint32_t TXWRN:1; + uint32_t RXWRN:1; + uint32_t IDLE:1; + uint32_t TXRX:1; + uint32_t FLTCONF:2; + uint32_t:1; + uint32_t BOFFINT:1; + uint32_t ERRINT:1; + uint32_t WAKINT:1; + } B; + } ESR; /* Error and Status Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63M:1; + uint32_t BUF62M:1; + uint32_t BUF61M:1; + uint32_t BUF60M:1; + uint32_t BUF59M:1; + uint32_t BUF58M:1; + uint32_t BUF57M:1; + uint32_t BUF56M:1; + uint32_t BUF55M:1; + uint32_t BUF54M:1; + uint32_t BUF53M:1; + uint32_t BUF52M:1; + uint32_t BUF51M:1; + uint32_t BUF50M:1; + uint32_t BUF49M:1; + uint32_t BUF48M:1; + uint32_t BUF47M:1; + uint32_t BUF46M:1; + uint32_t BUF45M:1; + uint32_t BUF44M:1; + uint32_t BUF43M:1; + uint32_t BUF42M:1; + uint32_t BUF41M:1; + uint32_t BUF40M:1; + uint32_t BUF39M:1; + uint32_t BUF38M:1; + uint32_t BUF37M:1; + uint32_t BUF36M:1; + uint32_t BUF35M:1; + uint32_t BUF34M:1; + uint32_t BUF33M:1; + uint32_t BUF32M:1; + } B; + } IMASK2; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31M:1; + uint32_t BUF30M:1; + uint32_t BUF29M:1; + uint32_t BUF28M:1; + uint32_t BUF27M:1; + uint32_t BUF26M:1; + uint32_t BUF25M:1; + uint32_t BUF24M:1; + uint32_t BUF23M:1; + uint32_t BUF22M:1; + uint32_t BUF21M:1; + uint32_t BUF20M:1; + uint32_t BUF19M:1; + uint32_t BUF18M:1; + uint32_t BUF17M:1; + uint32_t BUF16M:1; + uint32_t BUF15M:1; + uint32_t BUF14M:1; + uint32_t BUF13M:1; + uint32_t BUF12M:1; + uint32_t BUF11M:1; + uint32_t BUF10M:1; + uint32_t BUF09M:1; + uint32_t BUF08M:1; + uint32_t BUF07M:1; + uint32_t BUF06M:1; + uint32_t BUF05M:1; + uint32_t BUF04M:1; + uint32_t BUF03M:1; + uint32_t BUF02M:1; + uint32_t BUF01M:1; + uint32_t BUF00M:1; + } B; + } IMASK1; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63I:1; + uint32_t BUF62I:1; + uint32_t BUF61I:1; + uint32_t BUF60I:1; + uint32_t BUF59I:1; + uint32_t BUF58I:1; + uint32_t BUF57I:1; + uint32_t BUF56I:1; + uint32_t BUF55I:1; + uint32_t BUF54I:1; + uint32_t BUF53I:1; + uint32_t BUF52I:1; + uint32_t BUF51I:1; + uint32_t BUF50I:1; + uint32_t BUF49I:1; + uint32_t BUF48I:1; + uint32_t BUF47I:1; + uint32_t BUF46I:1; + uint32_t BUF45I:1; + uint32_t BUF44I:1; + uint32_t BUF43I:1; + uint32_t BUF42I:1; + uint32_t BUF41I:1; + uint32_t BUF40I:1; + uint32_t BUF39I:1; + uint32_t BUF38I:1; + uint32_t BUF37I:1; + uint32_t BUF36I:1; + uint32_t BUF35I:1; + uint32_t BUF34I:1; + uint32_t BUF33I:1; + uint32_t BUF32I:1; + } B; + } IFLAG2; /* Interruput Flag Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31I:1; + uint32_t BUF30I:1; + uint32_t BUF29I:1; + uint32_t BUF28I:1; + uint32_t BUF27I:1; + uint32_t BUF26I:1; + uint32_t BUF25I:1; + uint32_t BUF24I:1; + uint32_t BUF23I:1; + uint32_t BUF22I:1; + uint32_t BUF21I:1; + uint32_t BUF20I:1; + uint32_t BUF19I:1; + uint32_t BUF18I:1; + uint32_t BUF17I:1; + uint32_t BUF16I:1; + uint32_t BUF15I:1; + uint32_t BUF14I:1; + uint32_t BUF13I:1; + uint32_t BUF12I:1; + uint32_t BUF11I:1; + uint32_t BUF10I:1; + uint32_t BUF09I:1; + uint32_t BUF08I:1; + uint32_t BUF07I:1; + uint32_t BUF06I:1; + uint32_t BUF05I:1; + uint32_t BUF04I:1; + uint32_t BUF03I:1; + uint32_t BUF02I:1; + uint32_t BUF01I:1; + uint32_t BUF00I:1; + } B; + } IFLAG1; /* Interruput Flag Register */ + + uint32_t FLEXCAN_reserved2[19]; + + struct canbuf_t { + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t CODE:4; + uint32_t:1; + uint32_t SRR:1; + uint32_t IDE:1; + uint32_t RTR:1; + uint32_t LENGTH:4; + uint32_t TIMESTAMP:16; + } B; + } CS; + + union { + uint32_t R; + struct { + uint32_t PRIO:3; + uint32_t STD_ID:11; + uint32_t EXT_ID:18; + } B; + } ID; + + union { + /* uint8_t B[8]; Data buffer in Bytes (8 bits) */ + /* uint16_t H[4]; Data buffer in Half-words (16 bits) */ + uint32_t W[2]; /* Data buffer in words (32 bits) */ + /* uint32_t R[2]; Data buffer in words (32 bits) */ + } DATA; + + } BUF[64]; + + uint32_t FLEXCAN_reserved3[256]; + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RXIMR[64]; /* RX Individual Mask Registers */ + + }; /* end of CTU_tag */ +/**************************************************************************/ +/* MODULE : FlexRay */ +/**************************************************************************/ + + typedef union uMVR { + uint16_t R; + struct { + uint16_t CHIVER:8; /* CHI Version Number */ + uint16_t PEVER:8; /* PE Version Number */ + } B; + } MVR_t; + + typedef union uMCR { + uint16_t R; + struct { + uint16_t MEN:1; /* module enable */ + uint16_t:1; + uint16_t SCMD:1; /* single channel mode */ + uint16_t CHB:1; /* channel B enable */ + uint16_t CHA:1; /* channel A enable */ + uint16_t SFFE:1; /* synchronization frame filter enable */ + uint16_t:5; + uint16_t CLKSEL:1; /* protocol engine clock source select */ + uint16_t PRESCALE:3; /* protocol engine clock prescaler */ + uint16_t:1; + } B; + } MCR_t; + typedef union uSTBSCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t STBSSEL:7; /* strobe signal select */ + uint16_t:3; + uint16_t ENB:1; /* strobe signal enable */ + uint16_t:2; + uint16_t STBPSEL:2; /* strobe port select */ + } B; + } STBSCR_t; + typedef union uMBDSR { + uint16_t R; + struct { + uint16_t:1; + uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ + uint16_t:1; + uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ + } B; + } MBDSR_t; + + typedef union uMBSSUTR { + uint16_t R; + struct { + + uint16_t:2; + uint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */ + uint16_t:2; + uint16_t LAST_MB_UTIL:6; /* last message buffer utilized */ + } B; + } MBSSUTR_t; + + typedef union uPOCR { + uint16_t R; + uint8_t byte[2]; + struct { + uint16_t WME:1; /* write mode external correction command */ + uint16_t:3; + uint16_t EOC_AP:2; /* external offset correction application */ + uint16_t ERC_AP:2; /* external rate correction application */ + uint16_t BSY:1; /* command write busy / write mode command */ + uint16_t:3; + uint16_t POCCMD:4; /* protocol command */ + } B; + } POCR_t; +/* protocol commands */ + typedef union uGIFER { + uint16_t R; + struct { + uint16_t MIF:1; /* module interrupt flag */ + uint16_t PRIF:1; /* protocol interrupt flag */ + uint16_t CHIF:1; /* CHI interrupt flag */ + uint16_t WKUPIF:1; /* wakeup interrupt flag */ + uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ + uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ + uint16_t RBIF:1; /* receive message buffer interrupt flag */ + uint16_t TBIF:1; /* transmit buffer interrupt flag */ + uint16_t MIE:1; /* module interrupt enable */ + uint16_t PRIE:1; /* protocol interrupt enable */ + uint16_t CHIE:1; /* CHI interrupt enable */ + uint16_t WKUPIE:1; /* wakeup interrupt enable */ + uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ + uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ + uint16_t RBIE:1; /* receive message buffer interrupt enable */ + uint16_t TBIE:1; /* transmit buffer interrupt enable */ + } B; + } GIFER_t; + typedef union uPIFR0 { + uint16_t R; + struct { + uint16_t FATLIF:1; /* fatal protocol error interrupt flag */ + uint16_t INTLIF:1; /* internal protocol error interrupt flag */ + uint16_t ILCFIF:1; /* illegal protocol configuration flag */ + uint16_t CSAIF:1; /* cold start abort interrupt flag */ + uint16_t MRCIF:1; /* missing rate correctio interrupt flag */ + uint16_t MOCIF:1; /* missing offset correctio interrupt flag */ + uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ + uint16_t MXSIF:1; /* max sync frames detected interrupt flag */ + uint16_t MTXIF:1; /* media access test symbol received flag */ + uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ + uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ + uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ + uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ + uint16_t TI2IF:1; /* timer 2 expired interrupt flag */ + uint16_t TI1IF:1; /* timer 1 expired interrupt flag */ + uint16_t CYSIF:1; /* cycle start interrupt flag */ + } B; + } PIFR0_t; + typedef union uPIFR1 { + uint16_t R; + struct { + uint16_t EMCIF:1; /* error mode changed interrupt flag */ + uint16_t IPCIF:1; /* illegal protocol command interrupt flag */ + uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ + uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ + uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ + uint16_t:2; + uint16_t EVTIF:1; /* even cycle table written interrupt flag */ + uint16_t ODTIF:1; /* odd cycle table written interrupt flag */ + uint16_t:4; + } B; + } PIFR1_t; + typedef union uPIER0 { + uint16_t R; + struct { + uint16_t FATLIE:1; /* fatal protocol error interrupt enable */ + uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ + uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ + uint16_t CSAIE:1; /* cold start abort interrupt enable */ + uint16_t MRCIE:1; /* missing rate correctio interrupt enable */ + uint16_t MOCIE:1; /* missing offset correctio interrupt enable */ + uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ + uint16_t MXSIE:1; /* max sync frames detected interrupt enable */ + uint16_t MTXIE:1; /* media access test symbol received interrupt enable */ + uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ + uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ + uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ + uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ + uint16_t TI2IE:1; /* timer 2 expired interrupt enable */ + uint16_t TI1IE:1; /* timer 1 expired interrupt enable */ + uint16_t CYSIE:1; /* cycle start interrupt enable */ + } B; + } PIER0_t; + typedef union uPIER1 { + uint16_t R; + struct { + uint16_t EMCIE:1; /* error mode changed interrupt enable */ + uint16_t IPCIE:1; /* illegal protocol command interrupt enable */ + uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ + uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ + uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ + uint16_t:2; + uint16_t EVTIE:1; /* even cycle table written interrupt enable */ + uint16_t ODTIE:1; /* odd cycle table written interrupt enable */ + uint16_t:4; + } B; + } PIER1_t; + typedef union uCHIERFR { + uint16_t R; + struct { + uint16_t FRLBEF:1; /* flame lost channel B error flag */ + uint16_t FRLAEF:1; /* frame lost channel A error flag */ + uint16_t PCMIEF:1; /* command ignored error flag */ + uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ + uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ + uint16_t MSBEF:1; /* message buffer search error flag */ + uint16_t MBUEF:1; /* message buffer utilization error flag */ + uint16_t LCKEF:1; /* lock error flag */ + uint16_t DBLEF:1; /* double transmit message buffer lock error flag */ + uint16_t SBCFEF:1; /* system bus communication failure error flag */ + uint16_t FIDEF:1; /* frame ID error flag */ + uint16_t DPLEF:1; /* dynamic payload length error flag */ + uint16_t SPLEF:1; /* static payload length error flag */ + uint16_t NMLEF:1; /* network management length error flag */ + uint16_t NMFEF:1; /* network management frame error flag */ + uint16_t ILSAEF:1; /* illegal access error flag */ + } B; + } CHIERFR_t; + typedef union uMBIVEC { + uint16_t R; + struct { + + uint16_t:2; + uint16_t TBIVEC:6; /* transmit buffer interrupt vector */ + uint16_t:2; + uint16_t RBIVEC:6; /* receive buffer interrupt vector */ + } B; + } MBIVEC_t; + + typedef union uPSR0 { + uint16_t R; + struct { + uint16_t ERRMODE:2; /* error mode */ + uint16_t SLOTMODE:2; /* slot mode */ + uint16_t:1; + uint16_t PROTSTATE:3; /* protocol state */ + uint16_t SUBSTATE:4; /* protocol sub state */ + uint16_t:1; + uint16_t WAKEUPSTATUS:3; /* wakeup status */ + } B; + } PSR0_t; + +/* protocol states */ +/* protocol sub-states */ +/* wakeup status */ + typedef union uPSR1 { + uint16_t R; + struct { + uint16_t CSAA:1; /* cold start attempt abort flag */ + uint16_t SCP:1; /* cold start path */ + uint16_t:1; + uint16_t REMCSAT:5; /* remanining coldstart attempts */ + uint16_t CPN:1; /* cold start noise path */ + uint16_t HHR:1; /* host halt request pending */ + uint16_t FRZ:1; /* freeze occured */ + uint16_t APTAC:5; /* allow passive to active counter */ + } B; + } PSR1_t; + typedef union uPSR2 { + uint16_t R; + struct { + uint16_t NBVB:1; /* NIT boundary violation on channel B */ + uint16_t NSEB:1; /* NIT syntax error on channel B */ + uint16_t STCB:1; /* symbol window transmit conflict on channel B */ + uint16_t SBVB:1; /* symbol window boundary violation on channel B */ + uint16_t SSEB:1; /* symbol window syntax error on channel B */ + uint16_t MTB:1; /* media access test symbol MTS received on channel B */ + uint16_t NBVA:1; /* NIT boundary violation on channel A */ + uint16_t NSEA:1; /* NIT syntax error on channel A */ + uint16_t STCA:1; /* symbol window transmit conflict on channel A */ + uint16_t SBVA:1; /* symbol window boundary violation on channel A */ + uint16_t SSEA:1; /* symbol window syntax error on channel A */ + uint16_t MTA:1; /* media access test symbol MTS received on channel A */ + uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ + } B; + } PSR2_t; + typedef union uPSR3 { + uint16_t R; + struct { + uint16_t:2; + uint16_t WUB:1; /* wakeup symbol received on channel B */ + uint16_t ABVB:1; /* aggregated boundary violation on channel B */ + uint16_t AACB:1; /* aggregated additional communication on channel B */ + uint16_t ACEB:1; /* aggregated content error on channel B */ + uint16_t ASEB:1; /* aggregated syntax error on channel B */ + uint16_t AVFB:1; /* aggregated valid frame on channel B */ + uint16_t:2; + uint16_t WUA:1; /* wakeup symbol received on channel A */ + uint16_t ABVA:1; /* aggregated boundary violation on channel A */ + uint16_t AACA:1; /* aggregated additional communication on channel A */ + uint16_t ACEA:1; /* aggregated content error on channel A */ + uint16_t ASEA:1; /* aggregated syntax error on channel A */ + uint16_t AVFA:1; /* aggregated valid frame on channel A */ + } B; + } PSR3_t; + typedef union uCIFRR { + uint16_t R; + struct { + uint16_t:8; + uint16_t MIFR:1; /* module interrupt flag */ + uint16_t PRIFR:1; /* protocol interrupt flag */ + uint16_t CHIFR:1; /* CHI interrupt flag */ + uint16_t WUPIFR:1; /* wakeup interrupt flag */ + uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ + uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ + uint16_t RBIFR:1; /* receive message buffer interrupt flag */ + uint16_t TBIFR:1; /* transmit buffer interrupt flag */ + } B; + } CIFRR_t; + typedef union uSYMATOR { + uint16_t R; + struct { + uint16_t:11; + uint16_t TIMEOUT:5; /* system memory time out value */ + } B; + } SYMATOR_t; + + typedef union uSFCNTR { + uint16_t R; + struct { + uint16_t SFEVB:4; /* sync frames channel B, even cycle */ + uint16_t SFEVA:4; /* sync frames channel A, even cycle */ + uint16_t SFODB:4; /* sync frames channel B, odd cycle */ + uint16_t SFODA:4; /* sync frames channel A, odd cycle */ + } B; + } SFCNTR_t; + + typedef union uSFTCCSR { + uint16_t R; + struct { + uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ + uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ + uint16_t CYCNUM:6; /* cycle number */ + uint16_t ELKS:1; /* even cycle tables lock status */ + uint16_t OLKS:1; /* odd cycle tables lock status */ + uint16_t EVAL:1; /* even cycle tables valid */ + uint16_t OVAL:1; /* odd cycle tables valid */ + uint16_t:1; + uint16_t OPT:1; /*one pair trigger */ + uint16_t SDVEN:1; /* sync frame deviation table enable */ + uint16_t SIDEN:1; /* sync frame ID table enable */ + } B; + } SFTCCSR_t; + typedef union uSFIDRFR { + uint16_t R; + struct { + uint16_t:6; + uint16_t SYNFRID:10; /* sync frame rejection ID */ + } B; + } SFIDRFR_t; + + typedef union uTICCR { + uint16_t R; + struct { + uint16_t:2; + uint16_t T2CFG:1; /* timer 2 configuration */ + uint16_t T2REP:1; /* timer 2 repetitive mode */ + uint16_t:1; + uint16_t T2SP:1; /* timer 2 stop */ + uint16_t T2TR:1; /* timer 2 trigger */ + uint16_t T2ST:1; /* timer 2 state */ + uint16_t:3; + uint16_t T1REP:1; /* timer 1 repetitive mode */ + uint16_t:1; + uint16_t T1SP:1; /* timer 1 stop */ + uint16_t T1TR:1; /* timer 1 trigger */ + uint16_t T1ST:1; /* timer 1 state */ + + } B; + } TICCR_t; + typedef union uTI1CYSR { + uint16_t R; + struct { + uint16_t:2; + uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ + uint16_t:2; + uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ + + } B; + } TI1CYSR_t; + + typedef union uSSSR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* static slot number */ + uint16_t:1; + uint16_t SLOTNUMBER:11; /* selector */ + } B; + } SSSR_t; + + typedef union uSSCCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:1; + uint16_t CNTCFG:2; /* counter configuration */ + uint16_t MCY:1; /* multi cycle selection */ + uint16_t VFR:1; /* valid frame selection */ + uint16_t SYF:1; /* sync frame selection */ + uint16_t NUF:1; /* null frame selection */ + uint16_t SUF:1; /* startup frame selection */ + uint16_t STATUSMASK:4; /* slot status mask */ + } B; + } SSCCR_t; + typedef union uSSR { + uint16_t R; + struct { + uint16_t VFB:1; /* valid frame on channel B */ + uint16_t SYB:1; /* valid sync frame on channel B */ + uint16_t NFB:1; /* valid null frame on channel B */ + uint16_t SUB:1; /* valid startup frame on channel B */ + uint16_t SEB:1; /* syntax error on channel B */ + uint16_t CEB:1; /* content error on channel B */ + uint16_t BVB:1; /* boundary violation on channel B */ + uint16_t TCB:1; /* tx conflict on channel B */ + uint16_t VFA:1; /* valid frame on channel A */ + uint16_t SYA:1; /* valid sync frame on channel A */ + uint16_t NFA:1; /* valid null frame on channel A */ + uint16_t SUA:1; /* valid startup frame on channel A */ + uint16_t SEA:1; /* syntax error on channel A */ + uint16_t CEA:1; /* content error on channel A */ + uint16_t BVA:1; /* boundary violation on channel A */ + uint16_t TCA:1; /* tx conflict on channel A */ + } B; + } SSR_t; + typedef union uMTSCFR { + uint16_t R; + struct { + uint16_t MTE:1; /* media access test symbol transmission enable */ + uint16_t:1; + uint16_t CYCCNTMSK:6; /* cycle counter mask */ + uint16_t:2; + uint16_t CYCCNTVAL:6; /* cycle counter value */ + } B; + } MTSCFR_t; + + typedef union uRSBIR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:5; + uint16_t RSBIDX:7; /* receive shadow buffer index */ + } B; + } RSBIR_t; + + typedef union uRFDSR { + uint16_t R; + struct { + uint16_t FIFODEPTH:8; /* fifo depth */ + uint16_t:1; + uint16_t ENTRYSIZE:7; /* entry size */ + } B; + } RFDSR_t; + + typedef union uRFRFCFR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t IBD:1; /* interval boundary */ + uint16_t SEL:2; /* filter number */ + uint16_t:1; + uint16_t SID:11; /* slot ID */ + } B; + } RFRFCFR_t; + + typedef union uRFRFCTR { + uint16_t R; + struct { + uint16_t:4; + uint16_t F3MD:1; /* filter mode */ + uint16_t F2MD:1; /* filter mode */ + uint16_t F1MD:1; /* filter mode */ + uint16_t F0MD:1; /* filter mode */ + uint16_t:4; + uint16_t F3EN:1; /* filter enable */ + uint16_t F2EN:1; /* filter enable */ + uint16_t F1EN:1; /* filter enable */ + uint16_t F0EN:1; /* filter enable */ + } B; + } RFRFCTR_t; + typedef union uPCR0 { + uint16_t R; + struct { + uint16_t ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_LENGTH:10; + } B; + } PCR0_t; + + typedef union uPCR1 { + uint16_t R; + struct { + uint16_t:2; + uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; + } B; + } PCR1_t; + + typedef union uPCR2 { + uint16_t R; + struct { + uint16_t MINISLOT_AFTER_ACTION_POINT:6; + uint16_t NUMBER_OF_STATIC_SLOTS:10; + } B; + } PCR2_t; + + typedef union uPCR3 { + uint16_t R; + struct { + uint16_t WAKEUP_SYMBOL_RX_LOW:6; + uint16_t MINISLOT_ACTION_POINT_OFFSET:5; + uint16_t COLDSTART_ATTEMPTS:5; + } B; + } PCR3_t; + + typedef union uPCR4 { + uint16_t R; + struct { + uint16_t CAS_RX_LOW_MAX:7; + uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; + } B; + } PCR4_t; + + typedef union uPCR5 { + uint16_t R; + struct { + uint16_t TSS_TRANSMITTER:4; + uint16_t WAKEUP_SYMBOL_TX_LOW:6; + uint16_t WAKEUP_SYMBOL_RX_IDLE:6; + } B; + } PCR5_t; + + typedef union uPCR6 { + uint16_t R; + struct { + uint16_t:1; + uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; + uint16_t MACRO_INITIAL_OFFSET_A:7; + } B; + } PCR6_t; + + typedef union uPCR7 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_B:9; + uint16_t MICRO_PER_MACRO_NOM_HALF:7; + } B; + } PCR7_t; + + typedef union uPCR8 { + uint16_t R; + struct { + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; + uint16_t WAKEUP_SYMBOL_TX_IDLE:8; + } B; + } PCR8_t; + + typedef union uPCR9 { + uint16_t R; + struct { + uint16_t MINISLOT_EXISTS:1; + uint16_t SYMBOL_WINDOW_EXISTS:1; + uint16_t OFFSET_CORRECTION_OUT:14; + } B; + } PCR9_t; + + typedef union uPCR10 { + uint16_t R; + struct { + uint16_t SINGLE_SLOT_ENABLED:1; + uint16_t WAKEUP_CHANNEL:1; + uint16_t MACRO_PER_CYCLE:14; + } B; + } PCR10_t; + + typedef union uPCR11 { + uint16_t R; + struct { + uint16_t KEY_SLOT_USED_FOR_STARTUP:1; + uint16_t KEY_SLOT_USED_FOR_SYNC:1; + uint16_t OFFSET_CORRECTION_START:14; + } B; + } PCR11_t; + + typedef union uPCR12 { + uint16_t R; + struct { + uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; + uint16_t KEY_SLOT_HEADER_CRC:11; + } B; + } PCR12_t; + + typedef union uPCR13 { + uint16_t R; + struct { + uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; + } B; + } PCR13_t; + + typedef union uPCR14 { + uint16_t R; + struct { + uint16_t RATE_CORRECTION_OUT:11; + uint16_t LISTEN_TIMEOUT_H:5; + } B; + } PCR14_t; + + typedef union uPCR15 { + uint16_t R; + struct { + uint16_t LISTEN_TIMEOUT_L:16; + } B; + } PCR15_t; + + typedef union uPCR16 { + uint16_t R; + struct { + uint16_t MACRO_INITIAL_OFFSET_B:7; + uint16_t NOISE_LISTEN_TIMEOUT_H:9; + } B; + } PCR16_t; + + typedef union uPCR17 { + uint16_t R; + struct { + uint16_t NOISE_LISTEN_TIMEOUT_L:16; + } B; + } PCR17_t; + + typedef union uPCR18 { + uint16_t R; + struct { + uint16_t WAKEUP_PATTERN:6; + uint16_t KEY_SLOT_ID:10; + } B; + } PCR18_t; + + typedef union uPCR19 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_A:9; + uint16_t PAYLOAD_LENGTH_STATIC:7; + } B; + } PCR19_t; + + typedef union uPCR20 { + uint16_t R; + struct { + uint16_t MICRO_INITIAL_OFFSET_B:8; + uint16_t MICRO_INITIAL_OFFSET_A:8; + } B; + } PCR20_t; + + typedef union uPCR21 { + uint16_t R; + struct { + uint16_t EXTERN_RATE_CORRECTION:3; + uint16_t LATEST_TX:13; + } B; + } PCR21_t; + + typedef union uPCR22 { + uint16_t R; + struct { + uint16_t:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; + uint16_t MICRO_PER_CYCLE_H:4; + } B; + } PCR22_t; + + typedef union uPCR23 { + uint16_t R; + struct { + uint16_t micro_per_cycle_l:16; + } B; + } PCR23_t; + + typedef union uPCR24 { + uint16_t R; + struct { + uint16_t CLUSTER_DRIFT_DAMPING:5; + uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; + uint16_t MICRO_PER_CYCLE_MIN_H:4; + } B; + } PCR24_t; + + typedef union uPCR25 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MIN_L:16; + } B; + } PCR25_t; + + typedef union uPCR26 { + uint16_t R; + struct { + uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; + uint16_t MICRO_PER_CYCLE_MAX_H:4; + } B; + } PCR26_t; + + typedef union uPCR27 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MAX_L:16; + } B; + } PCR27_t; + + typedef union uPCR28 { + uint16_t R; + struct { + uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; + uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; + } B; + } PCR28_t; + + typedef union uPCR29 { + uint16_t R; + struct { + uint16_t EXTERN_OFFSET_CORRECTION:3; + uint16_t MINISLOTS_MAX:13; + } B; + } PCR29_t; + + typedef union uPCR30 { + uint16_t R; + struct { + uint16_t:12; + uint16_t SYNC_NODE_MAX:4; + } B; + } PCR30_t; + + typedef struct uMSG_BUFF_CCS { + union { + uint16_t R; + struct { + uint16_t:1; + uint16_t MCM:1; /* message buffer commit mode */ + uint16_t MBT:1; /* message buffer type */ + uint16_t MTD:1; /* message buffer direction */ + uint16_t CMT:1; /* commit for transmission */ + uint16_t EDT:1; /* enable / disable trigger */ + uint16_t LCKT:1; /* lock request trigger */ + uint16_t MBIE:1; /* message buffer interrupt enable */ + uint16_t:3; + uint16_t DUP:1; /* data updated */ + uint16_t DVAL:1; /* data valid */ + uint16_t EDS:1; /* lock status */ + uint16_t LCKS:1; /* enable / disable status */ + uint16_t MBIF:1; /* message buffer interrupt flag */ + } B; + } MBCCSR; + union { + uint16_t R; + struct { + uint16_t MTM:1; /* message buffer transmission mode */ + uint16_t CHNLA:1; /* channel assignement */ + uint16_t CHNLB:1; /* channel assignement */ + uint16_t CCFE:1; /* cycle counter filter enable */ + uint16_t CCFMSK:6; /* cycle counter filter mask */ + uint16_t CCFVAL:6; /* cycle counter filter value */ + } B; + } MBCCFR; + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t FID:11; /* frame ID */ + } B; + } MBFIDR; + + union { + uint16_t R; + struct { + uint16_t:9; + uint16_t MBIDX:7; /* message buffer index */ + } B; + } MBIDXR; + } MSG_BUFF_CCS_t; + typedef union uSYSBADHR { + uint16_t R; + } SYSBADHR_t; + typedef union uSYSBADLR { + uint16_t R; + } SYSBADLR_t; + typedef union uPADR { + uint16_t R; + } PADR_t; + typedef union uPDAR { + uint16_t R; + } PDAR_t; + typedef union uCASERCR { + uint16_t R; + } CASERCR_t; + typedef union uCBSERCR { + uint16_t R; + } CBSERCR_t; + typedef union uCYCTR { + uint16_t R; + } CYCTR_t; + typedef union uMTCTR { + uint16_t R; + } MTCTR_t; + typedef union uSLTCTAR { + uint16_t R; + } SLTCTAR_t; + typedef union uSLTCTBR { + uint16_t R; + } SLTCTBR_t; + typedef union uRTCORVR { + uint16_t R; + } RTCORVR_t; + typedef union uOFCORVR { + uint16_t R; + } OFCORVR_t; + typedef union uSFTOR { + uint16_t R; + } SFTOR_t; + typedef union uSFIDAFVR { + uint16_t R; + } SFIDAFVR_t; + typedef union uSFIDAFMR { + uint16_t R; + } SFIDAFMR_t; + typedef union uNMVR { + uint16_t R; + } NMVR_t; + typedef union uNMVLR { + uint16_t R; + } NMVLR_t; + typedef union uT1MTOR { + uint16_t R; + } T1MTOR_t; + typedef union uTI2CR0 { + uint16_t R; + } TI2CR0_t; + typedef union uTI2CR1 { + uint16_t R; + } TI2CR1_t; + typedef union uSSCR { + uint16_t R; + } SSCR_t; + typedef union uRFSR { + uint16_t R; + } RFSR_t; + typedef union uRFSIR { + uint16_t R; + } RFSIR_t; + typedef union uRFARIR { + uint16_t R; + } RFARIR_t; + typedef union uRFBRIR { + uint16_t R; + } RFBRIR_t; + typedef union uRFMIDAFVR { + uint16_t R; + } RFMIDAFVR_t; + typedef union uRFMIAFMR { + uint16_t R; + } RFMIAFMR_t; + typedef union uRFFIDRFVR { + uint16_t R; + } RFFIDRFVR_t; + typedef union uRFFIDRFMR { + uint16_t R; + } RFFIDRFMR_t; + typedef union uLDTXSLAR { + uint16_t R; + } LDTXSLAR_t; + typedef union uLDTXSLBR { + uint16_t R; + } LDTXSLBR_t; + + typedef struct FR_tag { + volatile MVR_t MVR; /*module version register *//*0 */ + volatile MCR_t MCR; /*module configuration register *//*2 */ + volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ + volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ + volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ + uint16_t reserved0[1]; /*A */ + volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ + volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ + uint16_t reserved1[1]; /*10 */ + uint16_t reserved2[1]; /*12 */ + volatile POCR_t POCR; /*Protocol operation control register *//*14 */ + volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ + volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ + volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ + volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ + volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ + volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ + volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ + volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ + volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ + volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ + volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ + volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ + volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ + volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ + volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ + volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ + volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ + volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ + volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ + volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ + volatile SYMATOR_t SYMATOR; /*system memory acess time-out register *//*3E */ + volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ + volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ + volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ + volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ + volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ + volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ + volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ + volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ + volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ + volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ + volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ + volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ + volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ + volatile SSSR_t SSSR; /*slot status selection register *//*64 */ + volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ + volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ + volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ + volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ + volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ + volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ + volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ + volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ + volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ + volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ + volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ + volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ + volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ + volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ + volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ + volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ + volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ + volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ + volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ + volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ + volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ + volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ + volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ + volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ + volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ + volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ + volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ + volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ + volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ + volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ + volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ + volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ + volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ + volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ + volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ + volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ + volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ + volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ + volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ + volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ + volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ + volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ + volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ + volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ + volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ + volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ + volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ + volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ + volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ + volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ + uint16_t reserved3[17]; + volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ + } FR_tag_t; + + typedef union uF_HEADER /* frame header */ + { + struct { + uint16_t:5; + uint16_t HDCRC:11; /* Header CRC */ + uint16_t:2; + uint16_t CYCCNT:6; /* Cycle Count */ + uint16_t:1; + uint16_t PLDLEN:7; /* Payload Length */ + uint16_t:1; + uint16_t PPI:1; /* Payload Preamble Indicator */ + uint16_t NUF:1; /* Null Frame Indicator */ + uint16_t SYF:1; /* Sync Frame Indicator */ + uint16_t SUF:1; /* Startup Frame Indicator */ + uint16_t FID:11; /* Frame ID */ + } B; + uint16_t WORDS[3]; + } F_HEADER_t; + typedef union uS_STSTUS /* slot status */ + { + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t CH:1; /* Channel */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t:1; + } RX; + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t TCB:1; /* Tx Conflict on channel B */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t TCA:1; /* Tx Conflict on channel A */ + } TX; + uint16_t R; + } S_STATUS_t; + + typedef struct uMB_HEADER /* message buffer header */ + { + F_HEADER_t FRAME_HEADER; + uint16_t DATA_OFFSET; + S_STATUS_t SLOT_STATUS; + } MB_HEADER_t; +/**************************************************************************/ +/* MODULE : FMPLL */ +/**************************************************************************/ + struct FMPLL_tag { + + uint32_t FMPLL_reserved0; + + union FMPLL_SYNSR_tag { /* Synthesiser Status Register */ + uint32_t R; + struct { + uint32_t:22; + uint32_t LOLF:1; + uint32_t LOC:1; + uint32_t MODE:1; + uint32_t PLLSEL:1; + uint32_t PLLREF:1; + uint32_t LOCKS:1; + uint32_t LOCK:1; + uint32_t LOCF:1; + uint32_t CALDONE:1; + uint32_t CALPASS:1; + } B; + } SYNSR; + + union FMPLL_ESYNCR1_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t CLKCFG:3; + uint32_t:8; + uint32_t EPREDIV:4; + uint32_t:8; + uint32_t EMFD:8; + } B; + } ESYNCR1; + + union FMPLL_ESYNCR2_tag { + uint32_t R; + struct { + uint32_t:8; + uint32_t LOCEN:1; + uint32_t LOLRE:1; + uint32_t LOCRE:1; + uint32_t LOLIRQ:1; + uint32_t LOCIRQ:1; + uint32_t:1; + uint32_t ERATE:2; + uint32_t:5; + uint32_t EDEPTH:3; + uint32_t:2; + uint32_t ERFD:6; + } B; + } ESYNCR2; + + }; +/*************************************************************************/ +/* MODULE : i2c */ +/*************************************************************************/ + struct I2C_tag { + union { + uint8_t R; + struct { + uint8_t AD:7; + uint8_t:1; + } B; + } IBAD; /* Module Bus Address Register */ + + union { + uint8_t R; + struct { + uint8_t MULT:2; + uint8_t ICR:6; + } B; + } IBFD; /* Module Bus Frequency Register */ + + union { + uint8_t R; + struct { + uint8_t MDIS:1; + uint8_t IBIE:1; + uint8_t MS:1; + uint8_t TX:1; + uint8_t NOACK:1; + uint8_t RSTA:1; + uint8_t DMAEN:1; + uint8_t:1; + } B; + } IBCR; /* Module Bus Control Register */ + + union { + uint8_t R; + struct { + uint8_t TCF:1; + uint8_t IAAS:1; + uint8_t IBB:1; + uint8_t IBAL:1; + uint8_t:1; + uint8_t SRW:1; + uint8_t IBIF:1; + uint8_t RXAK:1; + } B; + } IBSR; /* Module Status Register */ + + union { + uint8_t R; + struct { + uint8_t DATA:8; + } B; + } IBDR; /* Module Data Register */ + + union { + uint8_t R; + struct { + uint8_t BIIE:1; + uint8_t:7; + } B; + } IBIC; /* Module Interrupt Configuration Register */ + + }; /* end of i2c_tag */ +/*************************************************************************/ +/* MODULE : INTC */ +/*************************************************************************/ + struct INTC_tag { + union { + uint32_t R; + struct { + uint32_t:18; + uint32_t VTES_PRC1:1; + uint32_t:4; + uint32_t HVEN_PRC1:1; + uint32_t:2; + uint32_t VTES:1; + uint32_t:4; + uint32_t HVEN:1; + } B; + } MCR; /* Module Configuration Register */ + + int32_t INTC_reserved1; + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR; /* Processor 0 (Z6) Current Priority Register */ + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR_PRC1; /* Processor 1 (Z0) Current Priority Register */ + + union { + uint32_t R; + struct { + uint32_t VTBA:21; + uint32_t INTVEC:9; + uint32_t:2; + } B; + } IACKR; /* Processor 0 (Z6) Interrupt Acknowledge Register */ + + union { + uint32_t R; + struct { + uint32_t VTBA_PRC1:21; + uint32_t INTVEC_PRC1:9; + uint32_t:2; + } B; + } IACKR_PRC1; /* Processor 1 (Z0) Interrupt Acknowledge Register */ + + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } EOIR; /* Processor 0 End of Interrupt Register */ + + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } EOIR_PRC1; /* Processor 1 End of Interrupt Register */ + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t SET:1; + uint8_t CLR:1; + } B; + } SSCIR[8]; /* Software Set/Clear Interruput Register */ + + uint32_t intc_reserved2[6]; + + union { + uint8_t R; + struct { + uint8_t PRC_SEL:2; + uint8_t:2; + uint8_t PRI:4; + } B; + } PSR[316]; /* Software Set/Clear Interrupt Register */ + + }; /* end of INTC_tag */ +/*************************************************************************/ +/* MODULE : MLB */ +/*************************************************************************/ + struct MLB_tag { + + union { + uint32_t R; + struct { + uint32_t MDE:1; + uint32_t LBM:1; + uint32_t MCS:2; + uint32_t:1; + uint32_t MLK:1; + uint32_t MLE:1; + uint32_t MHRE:1; + uint32_t MRS:1; + uint32_t:15; + uint32_t MDA:8; + } B; + } DCCR; /* Device Control Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t SSRE:1; + uint32_t SDMU:1; + uint32_t SDML:1; + uint32_t SDSC:1; + uint32_t SDCS:1; + uint32_t SDNU:1; + uint32_t SDNL:1; + uint32_t SDR:1; + } B; + } SSCR; /* MLB Blank Register */ + + union { + uint32_t R; + struct { + uint32_t MSD:32; + } B; + } SDCR; /* MLB Status Register */ + + union { + uint32_t R; + struct { + uint32_t:25; + uint32_t SMMU:1; + uint32_t SMML:1; + uint32_t SMSC:1; + uint32_t SMCS:1; + uint32_t SMNU:1; + uint32_t SMNL:1; + uint32_t SMR:1; + } B; + } SMCR; /* RX Control Channel Address Register */ + + uint32_t MLB_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t UMA:8; + uint32_t UMI:8; + uint32_t MMA:8; + uint32_t MMI:8; + } B; + } VCCR; /* Version Control Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t SRBA:16; + uint32_t STBA:16; + } B; + } SBCR; /* Sync Base Address Config Register */ + + union { + uint32_t R; + struct { + uint32_t ARBA:16; + uint32_t ATBA:16; + } B; + } ABCR; /* Async Base Address Channel Config Register */ + + union { + uint32_t R; + struct { + uint32_t CRBA:16; + uint32_t CTBA:16; + } B; + } CBCR; /* Control Base Address Config Register */ + + union { + uint32_t R; + struct { + uint32_t IRBA:16; + uint32_t ITBA:16; + } B; + } IBCR; /* Isochronous Base Address Config Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t CSU:16; + } B; + } CICR; /* Channel Interrupt Config Register */ + + uint32_t MLB_reserved2[3]; + + struct mlbch_t { + + union { + uint32_t R; + struct { + uint32_t CE:1; + uint32_t TR:1; + uint32_t CT:2; + uint32_t FSE_FCE:1; + uint32_t MDS:2; + uint32_t:2; + uint32_t MLFS:1; + uint32_t:1; + uint32_t MBE:1; + uint32_t MBS:1; + uint32_t MBD:1; + uint32_t MDB:1; + uint32_t MPE:1; + uint32_t FSCD_IPL:1; + uint32_t IPL:2; + uint32_t FSPC_IPL:5; + uint32_t CA:8; + } B; + } CECR; /* Channel Entry Config Register */ + + union { + uint32_t R; + struct { + uint32_t BM:1; + uint32_t BF:1; + uint32_t:10; + uint32_t IVB:2; + uint32_t GIRB_GB:1; + uint32_t RDY:1; + uint32_t:4; + uint32_t PBS:1; + uint32_t PBD:1; + uint32_t PBDB:1; + uint32_t PBPE:1; + uint32_t:1; + uint32_t LFS:1; + uint32_t HBE:1; + uint32_t BE:1; + uint32_t CBS:1; + uint32_t CBD:1; + uint32_t CBDB:1; + uint32_t CBPE:1; + } B; + } CSCR; /* Channel Status Config Register */ + + union { + uint32_t R; + struct { + uint32_t BCA:16; + uint32_t BFA:16; + } B; + } CCBCR; /* Channel Current Buffer Config Register */ + + union { + uint32_t R; + struct { + uint32_t BSA:16; + uint32_t BEA:16; + } B; + } CNBCR; /* Channel Next Buffer Config Register */ + + } CH[16]; + + uint32_t MLB_reserved3[80]; + + union { + uint32_t R; + struct { + uint32_t BSA:16; + uint32_t BEA:16; + } B; + } LCBCR[16]; /* Local Channel Buffer Config Register */ + + }; /* end of MLB_tag */ +/*************************************************************************/ +/* MODULE : MPU */ +/*************************************************************************/ + struct MPU_tag { + union { + uint32_t R; + struct { + uint32_t MPERR:8; + uint32_t:4; + uint32_t HRL:4; + uint32_t NSP:4; + uint32_t NGRD:4; + uint32_t:7; + uint32_t VLD:1; + } B; + } CESR; /* Module Control/Error Status Register */ + + uint32_t mpu_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR0; /* Error Address Register */ + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR0; /* Error Detail Register */ + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR1; + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR1; + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR2; + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR3; + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR3; + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR2; + + uint32_t mpu_reserved2[244]; + + struct { + union { + uint32_t R; + struct { + uint32_t SRTADDR:27; + uint32_t:5; + } B; + } WORD0; /* Region Descriptor n Word 0 */ + + union { + uint32_t R; + struct { + uint32_t ENDADDR:27; + uint32_t:5; + } B; + } WORD1; /* Region Descriptor n Word 1 */ + + union { + uint32_t R; + struct { + uint32_t:2; + uint32_t M6RE:1; + uint32_t M6WE:1; + uint32_t M5RE:1; + uint32_t M5WE:1; + uint32_t M4RE:1; + uint32_t M4WE:1; + uint32_t:6; + uint32_t M2PE:1; + uint32_t M2SM:2; + uint32_t M2UM:3; + uint32_t M1PE:1; + uint32_t M1SM:2; + uint32_t M1UM:3; + uint32_t M0PE:1; + uint32_t M0SM:2; + uint32_t M0UM:3; + } B; + } WORD2; /* Region Descriptor n Word 2 */ + + union { + uint32_t R; + struct { + uint32_t PID:8; + uint32_t PIDMASK:8; + uint32_t:15; + uint32_t VLD:1; + } B; + } WORD3; /* Region Descriptor n Word 3 */ + + } RGD[16]; + + uint32_t mpu_reserved3[192]; + + union { + uint32_t R; + struct { + uint32_t:2; + uint32_t M6RE:1; + uint32_t M6WE:1; + uint32_t M5RE:1; + uint32_t M5WE:1; + uint32_t M4RE:1; + uint32_t M4WE:1; + uint32_t:6; + uint32_t M2PE:1; + uint32_t M2SM:2; + uint32_t M2UM:3; + uint32_t M1PE:1; + uint32_t M1SM:2; + uint32_t M1UM:3; + uint32_t M0PE:1; + uint32_t M0SM:2; + uint32_t M0UM:3; + } B; + } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */ + }; +/**************************************************************************/ +/* MODULE : pit */ +/**************************************************************************/ + struct PIT_tag { + + union PIT_MCR_tag { + uint32_t R; + struct { + uint32_t:30; + uint32_t MDIS:1; + uint32_t FRZ:1; + } B; + } PITMCR; + + uint32_t pit_reserved1[59]; + + struct PIT_CHANNEL_tag { + union { + uint32_t R; + struct { + uint32_t TSV:32; + } B; + } LDVAL; + + union { + uint32_t R; + struct { + uint32_t TVL:32; + } B; + } CVAL; + + union PIT_TCTRL_tag { + uint32_t R; + struct { + uint32_t:30; + uint32_t TIE:1; + uint32_t TEN:1; + } B; + } TCTRL; + + union PIT_TFLG_tag { + uint32_t R; + struct { + uint32_t:31; + uint32_t TIF:1; + } B; + } TFLG; + } CHANNEL[9]; + }; + + /* Compatibility with MPC5643L */ + typedef struct PIT_CHANNEL_tag PIT_RTI_CHANNEL_tag; + typedef union PIT_MCR_tag PIT_RTI_PITMCR_32B_tag; + typedef union PIT_TCTRL_tag PIT_RTI_TCTRL_32B_tag; + typedef union PIT_TFLG_tag PIT_RTI_TFLG_32B_tag; +/**************************************************************************/ +/* MODULE : sem4 */ +/**************************************************************************/ + struct SEMA4_tag { + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t GTFSM:2; + } B; + } GATE[16]; /* Gate n Register */ + + uint32_t sema4_reserved1[12]; /* {0x40-0x10}/4 = 0x0C */ + + union { + uint16_t R; + struct { + uint16_t INE0:1; + uint16_t INE1:1; + uint16_t INE2:1; + uint16_t INE3:1; + uint16_t INE4:1; + uint16_t INE5:1; + uint16_t INE6:1; + uint16_t INE7:1; + uint16_t INE8:1; + uint16_t INE9:1; + uint16_t INE10:1; + uint16_t INE11:1; + uint16_t INE12:1; + uint16_t INE13:1; + uint16_t INE14:1; + uint16_t INE15:1; + } B; + } CP0INE; + + uint16_t sema4_reserved2[3]; /* {0x48-0x42}/2 = 0x03 */ + + union { + uint16_t R; + struct { + uint16_t INE0:1; + uint16_t INE1:1; + uint16_t INE2:1; + uint16_t INE3:1; + uint16_t INE4:1; + uint16_t INE5:1; + uint16_t INE6:1; + uint16_t INE7:1; + uint16_t INE8:1; + uint16_t INE9:1; + uint16_t INE10:1; + uint16_t INE11:1; + uint16_t INE12:1; + uint16_t INE13:1; + uint16_t INE14:1; + uint16_t INE15:1; + } B; + } CP1INE; + + uint16_t sema4_reserved3[27]; /* {0x80-0x4A}/2 = 0x1B */ + + union { + uint16_t R; + struct { + uint16_t GN0:1; + uint16_t GN1:1; + uint16_t GN2:1; + uint16_t GN3:1; + uint16_t GN4:1; + uint16_t GN5:1; + uint16_t GN6:1; + uint16_t GN7:1; + uint16_t GN8:1; + uint16_t GN9:1; + uint16_t GN10:1; + uint16_t GN11:1; + uint16_t GN12:1; + uint16_t GN13:1; + uint16_t GN14:1; + uint16_t GN15:1; + } B; + } CP0NTF; + + uint16_t sema4_reserved4[3]; /* {0x88-0x82}/2 = 0x03 */ + + union { + uint16_t R; + struct { + uint16_t GN0:1; + uint16_t GN1:1; + uint16_t GN2:1; + uint16_t GN3:1; + uint16_t GN4:1; + uint16_t GN5:1; + uint16_t GN6:1; + uint16_t GN7:1; + uint16_t GN8:1; + uint16_t GN9:1; + uint16_t GN10:1; + uint16_t GN11:1; + uint16_t GN12:1; + uint16_t GN13:1; + uint16_t GN14:1; + uint16_t GN15:1; + } B; + } CP1NTF; + + uint16_t sema4_reserved5[59]; /* {0x100-0x8A}/2 = 0x3B */ + + union { + uint16_t R; + struct { + uint16_t:2; + uint16_t RSTGSM:2; + uint16_t:1; + uint16_t RSTGMS:3; + uint16_t RSTGTN:8; + } B; + } RSTGT; + + uint16_t sema4_reserved6; + + union { + uint16_t R; + struct { + uint16_t:2; + uint16_t RSTNSM:2; + uint16_t:1; + uint16_t RSTNMS:3; + uint16_t RSTNTN:8; + } B; + } RSTNTF; + }; +/*************************************************************************/ +/* MODULE : SIU */ +/*************************************************************************/ + struct SIU_tag { + + int32_t SIU_reserved0; + + union { + uint32_t R; + struct { + uint32_t PARTNUM:16; + uint32_t CSP:1; + uint32_t PKG:5; + uint32_t:2; + uint32_t MASKNUM_MAJOR:4; + uint32_t MASKNUM_MINOR:4; + } B; + } MIDR; /* MCU ID Register */ + + int32_t SIU_reserved1; + + union { + uint32_t R; + struct { + uint32_t PORS:1; + uint32_t ERS:1; + uint32_t LLRS:1; + uint32_t LCRS:1; + uint32_t WDRS:1; + uint32_t CRS:1; + uint32_t:8; + uint32_t SSRS:1; + uint32_t:15; + uint32_t BOOTCFG:1; + uint32_t:1; + } B; + } RSR; /* Reset Status Register */ + + union { + uint32_t R; + struct { + uint32_t SSR:1; + uint32_t:15; + uint32_t CRE0:1; + uint32_t CRE1:1; + uint32_t:6; + uint32_t SSRL:1; + uint32_t:7; + } B; + } SRCR; /* System Reset Control Register */ + + union { + uint32_t R; + struct { + uint32_t NMI0:1; + uint32_t NMI1:1; + uint32_t:14; + uint32_t EIF15:1; + uint32_t EIF14:1; + uint32_t EIF13:1; + uint32_t EIF12:1; + uint32_t EIF11:1; + uint32_t EIF10:1; + uint32_t EIF9:1; + uint32_t EIF8:1; + uint32_t EIF7:1; + uint32_t EIF6:1; + uint32_t EIF5:1; + uint32_t EIF4:1; + uint32_t EIF3:1; + uint32_t EIF2:1; + uint32_t EIF1:1; + uint32_t EIF0:1; + } B; + } EISR; /* External Interrupt Status Register */ + + union SIU_DIRER_tag { + uint32_t R; + struct { + uint32_t:16; + uint32_t EIRE15:1; + uint32_t EIRE14:1; + uint32_t EIRE13:1; + uint32_t EIRE12:1; + uint32_t EIRE11:1; + uint32_t EIRE10:1; + uint32_t EIRE9:1; + uint32_t EIRE8:1; + uint32_t EIRE7:1; + uint32_t EIRE6:1; + uint32_t EIRE5:1; + uint32_t EIRE4:1; + uint32_t EIRE3:1; + uint32_t EIRE2:1; + uint32_t EIRE1:1; + uint32_t EIRE0:1; + } B; + } DIRER; /* DMA/Interrupt Request Enable Register */ + + union SIU_DIRSR_tag { + uint32_t R; + struct { + uint32_t:30; + uint32_t DIRS1:1; + uint32_t DIRS0:1; + } B; + } DIRSR; /* DMA/Interrupt Select Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t OVF15:1; + uint32_t OVF14:1; + uint32_t OVF13:1; + uint32_t OVF12:1; + uint32_t OVF11:1; + uint32_t OVF10:1; + uint32_t OVF9:1; + uint32_t OVF8:1; + uint32_t OVF7:1; + uint32_t OVF6:1; + uint32_t OVF5:1; + uint32_t OVF4:1; + uint32_t OVF3:1; + uint32_t OVF2:1; + uint32_t OVF1:1; + uint32_t OVF0:1; + } B; + } OSR; /* Overrun Status Register */ + + union SIU_ORER_tag { + uint32_t R; + struct { + uint32_t:16; + uint32_t ORE15:1; + uint32_t ORE14:1; + uint32_t ORE13:1; + uint32_t ORE12:1; + uint32_t ORE11:1; + uint32_t ORE10:1; + uint32_t ORE9:1; + uint32_t ORE8:1; + uint32_t ORE7:1; + uint32_t ORE6:1; + uint32_t ORE5:1; + uint32_t ORE4:1; + uint32_t ORE3:1; + uint32_t ORE2:1; + uint32_t ORE1:1; + uint32_t ORE0:1; + } B; + } ORER; /* Overrun Request Enable Register */ + + union SIU_IREER_tag { + uint32_t R; + struct { + uint32_t NREE0:1; + uint32_t NREE1:1; + uint32_t:14; + uint32_t IREE15:1; + uint32_t IREE14:1; + uint32_t IREE13:1; + uint32_t IREE12:1; + uint32_t IREE11:1; + uint32_t IREE10:1; + uint32_t IREE9:1; + uint32_t IREE8:1; + uint32_t IREE7:1; + uint32_t IREE6:1; + uint32_t IREE5:1; + uint32_t IREE4:1; + uint32_t IREE3:1; + uint32_t IREE2:1; + uint32_t IREE1:1; + uint32_t IREE0:1; + } B; + } IREER; /* External IRQ Rising-Edge Event Enable Register */ + + union SIU_IFEER_tag { + uint32_t R; + struct { + uint32_t NFEE0:1; + uint32_t NFEE1:1; + uint32_t:14; + uint32_t IFEE15:1; + uint32_t IFEE14:1; + uint32_t IFEE13:1; + uint32_t IFEE12:1; + uint32_t IFEE11:1; + uint32_t IFEE10:1; + uint32_t IFEE9:1; + uint32_t IFEE8:1; + uint32_t IFEE7:1; + uint32_t IFEE6:1; + uint32_t IFEE5:1; + uint32_t IFEE4:1; + uint32_t IFEE3:1; + uint32_t IFEE2:1; + uint32_t IFEE1:1; + uint32_t IFEE0:1; + } B; + } IFEER; /* External IRQ Falling-Edge Event Enable Register */ + + union SIU_IDFR_tag { + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } IDFR; /* External IRQ Digital Filter Register */ + + union { + uint32_t R; + struct { + uint32_t FNMI0:1; + uint32_t FNMI1:1; + uint32_t:14; + uint32_t FI15:1; + uint32_t FI14:1; + uint32_t FI13:1; + uint32_t FI12:1; + uint32_t FI11:1; + uint32_t FI10:1; + uint32_t FI9:1; + uint32_t FI8:1; + uint32_t FI7:1; + uint32_t FI6:1; + uint32_t FI5:1; + uint32_t FI4:1; + uint32_t FI3:1; + uint32_t FI2:1; + uint32_t FI1:1; + uint32_t FI0:1; + } B; + } IFIR; /* External IRQ Filtered Input Register */ + + int32_t SIU_reserved2[2]; + + union SIU_PCR_tag { + uint16_t R; + struct { + uint16_t:4; + uint16_t PA:2; + uint16_t OBE:1; + uint16_t IBE:1; + uint16_t DSC:2; + uint16_t ODE:1; + uint16_t HYS:1; + uint16_t SRC:2; + uint16_t WPE:1; + uint16_t WPS:1; + } B; + } PCR[155]; /* Pad Configuration Registers */ + + int32_t SIU_reserved3[290]; + + union { + uint8_t R; + struct { + uint8_t:7; + uint8_t PDO:1; + } B; + } GPDO[155]; /* GPIO Pin Data Output Registers */ + + int8_t SIU_reserved4[357]; + + union { + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; + } B; + } GPDI[155]; /* GPIO Pin Data Input Registers */ + + int32_t SIU_reserved5[26]; + + union { + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } ISEL1; /* IMUX Register */ + + union { + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } ISEL2; /* IMUX Register */ + + int32_t SIU_reserved6; + + union { + uint32_t R; + struct { + uint32_t:17; + uint32_t TSEL1:7; + uint32_t:1; + uint32_t TSEL0:7; + } B; + } ISEL4; /* IMUX Register */ + + int32_t SIU_reserved7[27]; + + union { + uint32_t R; + struct { + uint32_t:14; + uint32_t MATCH:1; + uint32_t DISNEX:1; + uint32_t:8; + uint32_t TESTLOCK:1; + uint32_t:7; + } B; + } CCR; /* Chip Configuration Register Register */ + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t ECEN:1; + uint32_t:1; + uint32_t ECDF:2; + } B; + } ECCR; /* External Clock Configuration Register Register */ + + union { + uint32_t R; + } GPR0; /* General Purpose Register 0 */ + + union { + uint32_t R; + } GPR1; /* General Purpose Register 1 */ + + union { + uint32_t R; + } GPR2; /* General Purpose Register 2 */ + + union { + uint32_t R; + } GPR3; /* General Purpose Register 3 */ + + int32_t SIU_reserved8[2]; + + union { + uint32_t R; + struct { + uint32_t SYSCLKSEL:2; + uint32_t SYSCLKDIV:3; + uint32_t:19; + uint32_t LPCLKDIV3:2; + uint32_t LPCLKDIV2:2; + uint32_t LPCLKDIV1:2; + uint32_t LPCLKDIV0:2; + } B; + } SYSCLK; /* System CLock Register */ + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t HLT6:1; + uint32_t HLT7:1; + uint32_t:1; + uint32_t HLT9:1; + uint32_t HLT10:1; + uint32_t HLT11:1; + uint32_t HLT12:1; + uint32_t HLT13:1; + uint32_t HLT14:1; + uint32_t HLT15:1; + uint32_t HLT16:1; + uint32_t HLT17:1; + uint32_t HLT18:1; + uint32_t HLT19:1; + uint32_t HLT20:1; + uint32_t HLT21:1; + uint32_t HLT22:1; + uint32_t HLT23:1; + uint32_t:2; + uint32_t HLT26:1; + uint32_t HLT27:1; + uint32_t HLT28:1; + uint32_t HLT29:1; + uint32_t:1; + uint32_t HLT31:1; + } B; + } HLT0; /* Halt Register 0 */ + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t HLT3:1; + uint32_t HLT4:1; + uint32_t:15; + uint32_t HLT20:1; + uint32_t HLT21:1; + uint32_t HLT22:1; + uint32_t HLT23:1; + uint32_t:2; + uint32_t HLT26:1; + uint32_t HLT27:1; + uint32_t HLT28:1; + uint32_t HLT29:1; + uint32_t:2; + } B; + } HLT1; /* Halt Register 1 */ + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t HLTACK6:1; + uint32_t HLTACK7:1; + uint32_t:1; + uint32_t HLTACK9:1; + uint32_t HLTACK10:1; + uint32_t HLTACK11:1; + uint32_t HLTACK12:1; + uint32_t HLTACK13:1; + uint32_t HLTACK14:1; + uint32_t HLTACK15:1; + uint32_t HLTACK16:1; + uint32_t HLTACK17:1; + uint32_t HLTACK18:1; + uint32_t HLTACK19:1; + uint32_t HLTACK20:1; + uint32_t HLTACK21:1; + uint32_t HLTACK22:1; + uint32_t HLTACK23:1; + uint32_t:2; + uint32_t HLTACK26:1; + uint32_t HLTACK27:1; + uint32_t HLTACK28:1; + uint32_t HLTACK29:1; + uint32_t:1; + uint32_t HLTACK31:1; + } B; + } HLTACK0; /* Halt Acknowledge Register 0 */ + + union { + uint32_t R; + struct { + uint32_t HLTACK0:1; + uint32_t HLTACK1:1; + uint32_t:1; + uint32_t HLTACK3:1; + uint32_t HLTACK4:1; + uint32_t:11; + uint32_t HLTACK20:1; + uint32_t HLTACK21:1; + uint32_t HLTACK22:1; + uint32_t HLTACK23:1; + uint32_t:2; + uint32_t HLTACK26:1; + uint32_t HLTACK27:1; + uint32_t HLTACK28:1; + uint32_t HLTACK29:1; + uint32_t:2; + } B; + } HLTACK1; /* Halt Acknowledge Register 0 */ + + union { + uint32_t R; + struct { + uint32_t EMIOSSEL31:4; + uint32_t EMIOSSEL30:4; + uint32_t EMIOSSEL29:4; + uint32_t EMIOSSEL28:4; + uint32_t EMIOSSEL27:4; + uint32_t EMIOSSEL26:4; + uint32_t EMIOSSEL25:4; + uint32_t EMIOSSEL24:4; + } B; + } EMIOS_SEL0; /* eMIOS Select Register 0 */ + + union { + uint32_t R; + struct { + uint32_t EMIOSSEL23:4; + uint32_t EMIOSSEL22:4; + uint32_t EMIOSSEL21:4; + uint32_t EMIOSSEL20:4; + uint32_t EMIOSSEL19:4; + uint32_t EMIOSSEL18:4; + uint32_t EMIOSSEL17:4; + uint32_t EMIOSSEL16:4; + } B; + } EMIOS_SEL1; /* eMIOS Select Register 1 */ + + union { + uint32_t R; + struct { + uint32_t EMIOSSEL15:4; + uint32_t EMIOSSEL14:4; + uint32_t EMIOSSEL13:4; + uint32_t EMIOSSEL12:4; + uint32_t EMIOSSEL11:4; + uint32_t EMIOSSEL10:4; + uint32_t EMIOSSEL9:4; + uint32_t EMIOSSEL8:4; + } B; + } EMIOS_SEL2; /* eMIOS Select Register 2 */ + + union { + uint32_t R; + struct { + uint32_t EMIOSSEL7:4; + uint32_t EMIOSSEL6:4; + uint32_t EMIOSSEL5:4; + uint32_t EMIOSSEL4:4; + uint32_t EMIOSSEL3:4; + uint32_t EMIOSSEL2:4; + uint32_t EMIOSSEL1:4; + uint32_t EMIOSSEL0:4; + } B; + } EMIOS_SEL3; /* eMIOS Select Register 3 */ + + union { + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } ISEL2A; /* External Interrupt Select Register 2A */ + + int32_t SIU_reserved9[142]; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t PB:16; + } B; + } PGPDO0; /* Parallel GPIO Pin Data Output Register */ + + union { + uint32_t R; + struct { + uint32_t PC:16; + uint32_t PD:16; + } B; + } PGPDO1; /* Parallel GPIO Pin Data Output Register */ + + union { + uint32_t R; + struct { + uint32_t PE:16; + uint32_t PF:16; + } B; + } PGPDO2; /* Parallel GPIO Pin Data Output Register */ + + union { + uint32_t R; + struct { + uint32_t PG:16; + uint32_t PH:16; + } B; + } PGPDO3; /* Parallel GPIO Pin Data Output Register */ + + union { + uint32_t R; + struct { + uint32_t PJ:16; + uint32_t PK:11; + uint32_t:5; + } B; + } PGPDO4; /* Parallel GPIO Pin Data Output Register */ + + int32_t SIU_reserved10[11]; + + union { + uint32_t R; + struct { + uint32_t PA:16; + uint32_t PB:16; + } B; + } PGPDI0; /* Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PC:16; + uint32_t PD:16; + } B; + } PGPDI1; /* Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PE:16; + uint32_t PF:16; + } B; + } PGPDI2; /* Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PG:16; + uint32_t PH:16; + } B; + } PGPDI3; /* Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PJ:16; + uint32_t PK:11; + uint32_t:5; + } B; + } PGPDI4; /* Parallel GPIO Pin Data Input Register */ + + int32_t SIU_reserved11[12]; + + union { + uint32_t R; + struct { + uint32_t PB_MASK:16; + uint32_t PB:16; + } B; + } MPGPDO1; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PC_MASK:16; + uint32_t PC:16; + } B; + } MPGPDO2; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PD_MASK:16; + uint32_t PD:16; + } B; + } MPGPDO3; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PE_MASK:16; + uint32_t PE:16; + } B; + } MPGPDO4; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PF_MASK:16; + uint32_t PF:16; + } B; + } MPGPDO5; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PG_MASK:16; + uint32_t PG:16; + } B; + } MPGPDO6; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PH_MASK:16; + uint32_t PH:16; + } B; + } MPGPDO7; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PJ_MASK:16; + uint32_t PJ:16; + } B; + } MPGPDO8; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PK_MASK:11; + uint32_t:5; + uint32_t PK:11; + uint32_t:5; + } B; + } MPGPDO9; /* Masked Parallel GPIO Pin Data Input Register */ + + int32_t SIU_reserved12[22]; + + union { + uint32_t R; + struct { + uint32_t MASK31:1; + uint32_t MASK30:1; + uint32_t MASK29:1; + uint32_t MASK28:1; + uint32_t MASK27:1; + uint32_t MASK26:1; + uint32_t MASK25:1; + uint32_t MASK24:1; + uint32_t MASK23:1; + uint32_t MASK22:1; + uint32_t MASK21:1; + uint32_t MASK20:1; + uint32_t MASK19:1; + uint32_t MASK18:1; + uint32_t MASK17:1; + uint32_t MASK16:1; + uint32_t DATA31:1; + uint32_t DATA30:1; + uint32_t DATA29:1; + uint32_t DATA28:1; + uint32_t DATA27:1; + uint32_t DATA26:1; + uint32_t DATA25:1; + uint32_t DATA24:1; + uint32_t DATA23:1; + uint32_t DATA22:1; + uint32_t DATA21:1; + uint32_t DATA20:1; + uint32_t DATA19:1; + uint32_t DATA18:1; + uint32_t DATA17:1; + uint32_t DATA16:1; + } B; + } DSPIAH; /* Masked Serial GPO for DSPI_A High Register */ + + union { + uint32_t R; + struct { + uint32_t MASK15:1; + uint32_t MASK14:1; + uint32_t MASK13:1; + uint32_t MASK12:1; + uint32_t MASK11:1; + uint32_t MASK10:1; + uint32_t MASK9:1; + uint32_t MASK8:1; + uint32_t MASK7:1; + uint32_t MASK6:1; + uint32_t MASK5:1; + uint32_t MASK4:1; + uint32_t MASK3:1; + uint32_t MASK2:1; + uint32_t MASK1:1; + uint32_t MASK0:1; + uint32_t DATA15:1; + uint32_t DATA14:1; + uint32_t DATA13:1; + uint32_t DATA12:1; + uint32_t DATA11:1; + uint32_t DATA10:1; + uint32_t DATA9:1; + uint32_t DATA8:1; + uint32_t DATA7:1; + uint32_t DATA6:1; + uint32_t DATA5:1; + uint32_t DATA4:1; + uint32_t DATA3:1; + uint32_t DATA2:1; + uint32_t DATA1:1; + uint32_t DATA0:1; + } B; + } DSPIAL; /* Masked Serial GPO for DSPI_A Low Register */ + + union { + uint32_t R; + struct { + uint32_t MASK31:1; + uint32_t MASK30:1; + uint32_t MASK29:1; + uint32_t MASK28:1; + uint32_t MASK27:1; + uint32_t MASK26:1; + uint32_t MASK25:1; + uint32_t MASK24:1; + uint32_t MASK23:1; + uint32_t MASK22:1; + uint32_t MASK21:1; + uint32_t MASK20:1; + uint32_t MASK19:1; + uint32_t MASK18:1; + uint32_t MASK17:1; + uint32_t MASK16:1; + uint32_t DATA31:1; + uint32_t DATA30:1; + uint32_t DATA29:1; + uint32_t DATA28:1; + uint32_t DATA27:1; + uint32_t DATA26:1; + uint32_t DATA25:1; + uint32_t DATA24:1; + uint32_t DATA23:1; + uint32_t DATA22:1; + uint32_t DATA21:1; + uint32_t DATA20:1; + uint32_t DATA19:1; + uint32_t DATA18:1; + uint32_t DATA17:1; + uint32_t DATA16:1; + } B; + } DSPIBH; /* Masked Serial GPO for DSPI_B High Register */ + + union { + uint32_t R; + struct { + uint32_t MASK15:1; + uint32_t MASK14:1; + uint32_t MASK13:1; + uint32_t MASK12:1; + uint32_t MASK11:1; + uint32_t MASK10:1; + uint32_t MASK9:1; + uint32_t MASK8:1; + uint32_t MASK7:1; + uint32_t MASK6:1; + uint32_t MASK5:1; + uint32_t MASK4:1; + uint32_t MASK3:1; + uint32_t MASK2:1; + uint32_t MASK1:1; + uint32_t MASK0:1; + uint32_t DATA15:1; + uint32_t DATA14:1; + uint32_t DATA13:1; + uint32_t DATA12:1; + uint32_t DATA11:1; + uint32_t DATA10:1; + uint32_t DATA9:1; + uint32_t DATA8:1; + uint32_t DATA7:1; + uint32_t DATA6:1; + uint32_t DATA5:1; + uint32_t DATA4:1; + uint32_t DATA3:1; + uint32_t DATA2:1; + uint32_t DATA1:1; + uint32_t DATA0:1; + } B; + } DSPIBL; /* Masked Serial GPO for DSPI_B Low Register */ + + union { + uint32_t R; + struct { + uint32_t MASK31:1; + uint32_t MASK30:1; + uint32_t MASK29:1; + uint32_t MASK28:1; + uint32_t MASK27:1; + uint32_t MASK26:1; + uint32_t MASK25:1; + uint32_t MASK24:1; + uint32_t MASK23:1; + uint32_t MASK22:1; + uint32_t MASK21:1; + uint32_t MASK20:1; + uint32_t MASK19:1; + uint32_t MASK18:1; + uint32_t MASK17:1; + uint32_t MASK16:1; + uint32_t DATA31:1; + uint32_t DATA30:1; + uint32_t DATA29:1; + uint32_t DATA28:1; + uint32_t DATA27:1; + uint32_t DATA26:1; + uint32_t DATA25:1; + uint32_t DATA24:1; + uint32_t DATA23:1; + uint32_t DATA22:1; + uint32_t DATA21:1; + uint32_t DATA20:1; + uint32_t DATA19:1; + uint32_t DATA18:1; + uint32_t DATA17:1; + uint32_t DATA16:1; + } B; + } DSPICH; /* Masked Serial GPO for DSPI_C High Register */ + + union { + uint32_t R; + struct { + uint32_t MASK15:1; + uint32_t MASK14:1; + uint32_t MASK13:1; + uint32_t MASK12:1; + uint32_t MASK11:1; + uint32_t MASK10:1; + uint32_t MASK9:1; + uint32_t MASK8:1; + uint32_t MASK7:1; + uint32_t MASK6:1; + uint32_t MASK5:1; + uint32_t MASK4:1; + uint32_t MASK3:1; + uint32_t MASK2:1; + uint32_t MASK1:1; + uint32_t MASK0:1; + uint32_t DATA15:1; + uint32_t DATA14:1; + uint32_t DATA13:1; + uint32_t DATA12:1; + uint32_t DATA11:1; + uint32_t DATA10:1; + uint32_t DATA9:1; + uint32_t DATA8:1; + uint32_t DATA7:1; + uint32_t DATA6:1; + uint32_t DATA5:1; + uint32_t DATA4:1; + uint32_t DATA3:1; + uint32_t DATA2:1; + uint32_t DATA1:1; + uint32_t DATA0:1; + } B; + } DSPICL; /* Masked Serial GPO for DSPI_C Low Register */ + + union { + uint32_t R; + struct { + uint32_t MASK31:1; + uint32_t MASK30:1; + uint32_t MASK29:1; + uint32_t MASK28:1; + uint32_t MASK27:1; + uint32_t MASK26:1; + uint32_t MASK25:1; + uint32_t MASK24:1; + uint32_t MASK23:1; + uint32_t MASK22:1; + uint32_t MASK21:1; + uint32_t MASK20:1; + uint32_t MASK19:1; + uint32_t MASK18:1; + uint32_t MASK17:1; + uint32_t MASK16:1; + uint32_t DATA31:1; + uint32_t DATA30:1; + uint32_t DATA29:1; + uint32_t DATA28:1; + uint32_t DATA27:1; + uint32_t DATA26:1; + uint32_t DATA25:1; + uint32_t DATA24:1; + uint32_t DATA23:1; + uint32_t DATA22:1; + uint32_t DATA21:1; + uint32_t DATA20:1; + uint32_t DATA19:1; + uint32_t DATA18:1; + uint32_t DATA17:1; + uint32_t DATA16:1; + } B; + } DSPIDH; /* Masked Serial GPO for DSPI_D High Register */ + + union { + uint32_t R; + struct { + uint32_t MASK15:1; + uint32_t MASK14:1; + uint32_t MASK13:1; + uint32_t MASK12:1; + uint32_t MASK11:1; + uint32_t MASK10:1; + uint32_t MASK9:1; + uint32_t MASK8:1; + uint32_t MASK7:1; + uint32_t MASK6:1; + uint32_t MASK5:1; + uint32_t MASK4:1; + uint32_t MASK3:1; + uint32_t MASK2:1; + uint32_t MASK1:1; + uint32_t MASK0:1; + uint32_t DATA15:1; + uint32_t DATA14:1; + uint32_t DATA13:1; + uint32_t DATA12:1; + uint32_t DATA11:1; + uint32_t DATA10:1; + uint32_t DATA9:1; + uint32_t DATA8:1; + uint32_t DATA7:1; + uint32_t DATA6:1; + uint32_t DATA5:1; + uint32_t DATA4:1; + uint32_t DATA3:1; + uint32_t DATA2:1; + uint32_t DATA1:1; + uint32_t DATA0:1; + } B; + } DSPIDL; /* Masked Serial GPO for DSPI_D Low Register */ + + int32_t SIU_reserved13[9]; + + union { + uint32_t R; + struct { + uint32_t EMIOS31:1; + uint32_t EMIOS30:1; + uint32_t EMIOS29:1; + uint32_t EMIOS28:1; + uint32_t EMIOS27:1; + uint32_t EMIOS26:1; + uint32_t EMIOS25:1; + uint32_t EMIOS24:1; + uint32_t EMIOS23:1; + uint32_t EMIOS22:1; + uint32_t EMIOS21:1; + uint32_t EMIOS20:1; + uint32_t EMIOS19:1; + uint32_t EMIOS18:1; + uint32_t EMIOS17:1; + uint32_t EMIOS16:1; + uint32_t EMIOS15:1; + uint32_t EMIOS14:1; + uint32_t EMIOS13:1; + uint32_t EMIOS12:1; + uint32_t EMIOS11:1; + uint32_t EMIOS10:1; + uint32_t EMIOS9:1; + uint32_t EMIOS8:1; + uint32_t EMIOS7:1; + uint32_t EMIOS6:1; + uint32_t EMIOS5:1; + uint32_t EMIOS4:1; + uint32_t EMIOS3:1; + uint32_t EMIOS2:1; + uint32_t EMIOS1:1; + uint32_t EMIOS0:1; + } B; + } EMIOSA; /* EMIOS A Select Register */ + + union { + uint32_t R; + struct { + uint32_t DSPIAH31:1; + uint32_t DSPIAH30:1; + uint32_t DSPIAH29:1; + uint32_t DSPIAH28:1; + uint32_t DSPIAH27:1; + uint32_t DSPIAH26:1; + uint32_t DSPIAH25:1; + uint32_t DSPIAH24:1; + uint32_t DSPIAH23:1; + uint32_t DSPIAH22:1; + uint32_t DSPIAH21:1; + uint32_t DSPIAH20:1; + uint32_t DSPIAH19:1; + uint32_t DSPIAH18:1; + uint32_t DSPIAH17:1; + uint32_t DSPIAH16:1; + uint32_t DSPIAL15:1; + uint32_t DSPIAL14:1; + uint32_t DSPIAL13:1; + uint32_t DSPIAL12:1; + uint32_t DSPIAL11:1; + uint32_t DSPIAL10:1; + uint32_t DSPIAL9:1; + uint32_t DSPIAL8:1; + uint32_t DSPIAL7:1; + uint32_t DSPIAL6:1; + uint32_t DSPIAL5:1; + uint32_t DSPIAL4:1; + uint32_t DSPIAL3:1; + uint32_t DSPIAL2:1; + uint32_t DSPIAL1:1; + uint32_t DSPIAL0:1; + } B; + } DSPIAHLA; /* DSPIAH/L Select Register for DSPI A */ + + int32_t SIU_reserved14[2]; + + union { + uint32_t R; + struct { + uint32_t EMIOS31:1; + uint32_t EMIOS30:1; + uint32_t EMIOS29:1; + uint32_t EMIOS28:1; + uint32_t EMIOS27:1; + uint32_t EMIOS26:1; + uint32_t EMIOS25:1; + uint32_t EMIOS24:1; + uint32_t EMIOS23:1; + uint32_t EMIOS22:1; + uint32_t EMIOS21:1; + uint32_t EMIOS20:1; + uint32_t EMIOS19:1; + uint32_t EMIOS18:1; + uint32_t EMIOS17:1; + uint32_t EMIOS16:1; + uint32_t EMIOS15:1; + uint32_t EMIOS14:1; + uint32_t EMIOS13:1; + uint32_t EMIOS12:1; + uint32_t EMIOS11:1; + uint32_t EMIOS10:1; + uint32_t EMIOS9:1; + uint32_t EMIOS8:1; + uint32_t EMIOS7:1; + uint32_t EMIOS6:1; + uint32_t EMIOS5:1; + uint32_t EMIOS4:1; + uint32_t EMIOS3:1; + uint32_t EMIOS2:1; + uint32_t EMIOS1:1; + uint32_t EMIOS0:1; + } B; + } EMIOSB; /* EMIOS B Select Register */ + + union { + uint32_t R; + struct { + uint32_t DSPIBH31:1; + uint32_t DSPIBH30:1; + uint32_t DSPIBH29:1; + uint32_t DSPIBH28:1; + uint32_t DSPIBH27:1; + uint32_t DSPIBH26:1; + uint32_t DSPIBH25:1; + uint32_t DSPIBH24:1; + uint32_t DSPIBH23:1; + uint32_t DSPIBH22:1; + uint32_t DSPIBH21:1; + uint32_t DSPIBH20:1; + uint32_t DSPIBH19:1; + uint32_t DSPIBH18:1; + uint32_t DSPIBH17:1; + uint32_t DSPIBH16:1; + uint32_t DSPIBL15:1; + uint32_t DSPIBL14:1; + uint32_t DSPIBL13:1; + uint32_t DSPIBL12:1; + uint32_t DSPIBL11:1; + uint32_t DSPIBL10:1; + uint32_t DSPIBL9:1; + uint32_t DSPIBL8:1; + uint32_t DSPIBL7:1; + uint32_t DSPIBL6:1; + uint32_t DSPIBL5:1; + uint32_t DSPIBL4:1; + uint32_t DSPIBL3:1; + uint32_t DSPIBL2:1; + uint32_t DSPIBL1:1; + uint32_t DSPIBL0:1; + } B; + } DSPIBHLB; /* DSPIBH/L Select Register for DSPI B */ + + int32_t SIU_reserved115[2]; + + union { + uint32_t R; + struct { + uint32_t EMIOS31:1; + uint32_t EMIOS30:1; + uint32_t EMIOS29:1; + uint32_t EMIOS28:1; + uint32_t EMIOS27:1; + uint32_t EMIOS26:1; + uint32_t EMIOS25:1; + uint32_t EMIOS24:1; + uint32_t EMIOS23:1; + uint32_t EMIOS22:1; + uint32_t EMIOS21:1; + uint32_t EMIOS20:1; + uint32_t EMIOS19:1; + uint32_t EMIOS18:1; + uint32_t EMIOS17:1; + uint32_t EMIOS16:1; + uint32_t EMIOS15:1; + uint32_t EMIOS14:1; + uint32_t EMIOS13:1; + uint32_t EMIOS12:1; + uint32_t EMIOS11:1; + uint32_t EMIOS10:1; + uint32_t EMIOS9:1; + uint32_t EMIOS8:1; + uint32_t EMIOS7:1; + uint32_t EMIOS6:1; + uint32_t EMIOS5:1; + uint32_t EMIOS4:1; + uint32_t EMIOS3:1; + uint32_t EMIOS2:1; + uint32_t EMIOS1:1; + uint32_t EMIOS0:1; + } B; + } EMIOSC; /* EMIOS C Select Register */ + + union { + uint32_t R; + struct { + uint32_t DSPICH31:1; + uint32_t DSPICH30:1; + uint32_t DSPICH29:1; + uint32_t DSPICH28:1; + uint32_t DSPICH27:1; + uint32_t DSPICH26:1; + uint32_t DSPICH25:1; + uint32_t DSPICH24:1; + uint32_t DSPICH23:1; + uint32_t DSPICH22:1; + uint32_t DSPICH21:1; + uint32_t DSPICH20:1; + uint32_t DSPICH19:1; + uint32_t DSPICH18:1; + uint32_t DSPICH17:1; + uint32_t DSPICH16:1; + uint32_t DSPICL15:1; + uint32_t DSPICL14:1; + uint32_t DSPICL13:1; + uint32_t DSPICL12:1; + uint32_t DSPICL11:1; + uint32_t DSPICL10:1; + uint32_t DSPICL9:1; + uint32_t DSPICL8:1; + uint32_t DSPICL7:1; + uint32_t DSPICL6:1; + uint32_t DSPICL5:1; + uint32_t DSPICL4:1; + uint32_t DSPICL3:1; + uint32_t DSPICL2:1; + uint32_t DSPICL1:1; + uint32_t DSPICL0:1; + } B; + } DSPICHLC; /* DSPIAH/L Select Register for DSPI C */ + + int32_t SIU_reserved16[2]; + + union { + uint32_t R; + struct { + uint32_t EMIOS31:1; + uint32_t EMIOS30:1; + uint32_t EMIOS29:1; + uint32_t EMIOS28:1; + uint32_t EMIOS27:1; + uint32_t EMIOS26:1; + uint32_t EMIOS25:1; + uint32_t EMIOS24:1; + uint32_t EMIOS23:1; + uint32_t EMIOS22:1; + uint32_t EMIOS21:1; + uint32_t EMIOS20:1; + uint32_t EMIOS19:1; + uint32_t EMIOS18:1; + uint32_t EMIOS17:1; + uint32_t EMIOS16:1; + uint32_t EMIOS15:1; + uint32_t EMIOS14:1; + uint32_t EMIOS13:1; + uint32_t EMIOS12:1; + uint32_t EMIOS11:1; + uint32_t EMIOS10:1; + uint32_t EMIOS9:1; + uint32_t EMIOS8:1; + uint32_t EMIOS7:1; + uint32_t EMIOS6:1; + uint32_t EMIOS5:1; + uint32_t EMIOS4:1; + uint32_t EMIOS3:1; + uint32_t EMIOS2:1; + uint32_t EMIOS1:1; + uint32_t EMIOS0:1; + } B; + } EMIOSD; /* EMIOS D Select Register */ + + union { + uint32_t R; + struct { + uint32_t DSPIDH31:1; + uint32_t DSPIDH30:1; + uint32_t DSPIDH29:1; + uint32_t DSPIDH28:1; + uint32_t DSPIDH27:1; + uint32_t DSPIDH26:1; + uint32_t DSPIDH25:1; + uint32_t DSPIDH24:1; + uint32_t DSPIDH23:1; + uint32_t DSPIDH22:1; + uint32_t DSPIDH21:1; + uint32_t DSPIDH20:1; + uint32_t DSPIDH19:1; + uint32_t DSPIDH18:1; + uint32_t DSPIDH17:1; + uint32_t DSPIDH16:1; + uint32_t DSPIDL15:1; + uint32_t DSPIDL14:1; + uint32_t DSPIDL13:1; + uint32_t DSPIDL12:1; + uint32_t DSPIDL11:1; + uint32_t DSPIDL10:1; + uint32_t DSPIDL9:1; + uint32_t DSPIDL8:1; + uint32_t DSPIDL7:1; + uint32_t DSPIDL6:1; + uint32_t DSPIDL5:1; + uint32_t DSPIDL4:1; + uint32_t DSPIDL3:1; + uint32_t DSPIDL2:1; + uint32_t DSPIDL1:1; + uint32_t DSPIDL0:1; + } B; + } DSPIDHLD; /* DSPIAH/L Select Register for DSPI D */ + + }; /* end of SIU_tag */ +/**************************************************************************/ +/* MODULE : STM */ +/**************************************************************************/ + struct STM_tag { + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t CPS:8; + uint32_t:6; + uint32_t FRZ:1; + uint32_t TEN:1; + } B; + } CR; /* STM Control Register */ + + union { + uint32_t R; + } CNT; /* STM Count Register */ + + int32_t STM_reserved[2]; + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CEN:1; + } B; + } CCR0; /* STM Channel Control Register 0 */ + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CIF:1; + } B; + } CIR0; /* STM Channel Interrupt Register 0 */ + + union { + uint32_t R; + } CMP0; /* STM Channel Compare Register 0 */ + + int32_t STM_reserved1; + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CEN:1; + } B; + } CCR1; /* STM Channel Control Register 1 */ + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CIF:1; + } B; + } CIR1; /* STM Channel Interrupt Register 1 */ + + union { + uint32_t R; + } CMP1; /* STM Channel Compare Register 1 */ + + int32_t STM_reserved2; + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CEN:1; + } B; + } CCR2; /* STM Channel Control Register 2 */ + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CIF:1; + } B; + } CIR2; /* STM Channel Interrupt Register 2 */ + + union { + uint32_t R; + } CMP2; /* STM Channel Compare Register 2 */ + + int32_t STM_reserved3; + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CEN:1; + } B; + } CCR3; /* STM Channel Control Register 3 */ + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CIF:1; + } B; + } CIR3; /* STM Channel Interrupt Register 3 */ + + union { + uint32_t R; + } CMP3; /* STM Channel Compare Register 3 */ + + }; /* end of STM_tag */ +/**************************************************************************/ +/* MODULE : SWT */ +/**************************************************************************/ + struct SWT_tag { + union { + uint32_t R; + struct { + uint32_t MAP0:1; + uint32_t MAP1:1; + uint32_t MAP2:1; + uint32_t MAP3:1; + uint32_t MAP4:1; + uint32_t MAP5:1; + uint32_t MAP6:1; + uint32_t MAP7:1; + uint32_t:14; + uint32_t KEY:1; + uint32_t RIA:1; + uint32_t WND:1; + uint32_t ITR:1; + uint32_t HLK:1; + uint32_t SLK:1; + uint32_t:2; + uint32_t FRZ:1; + uint32_t WEN:1; + } B; + } CR; /* SWT Control Register */ + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t TIF:1; + } B; + } IR; /* SWT Interrupt Register */ + + union { + uint32_t R; + struct { + uint32_t WTO:32; + } B; + } TO; /* SWT Time-Out Register */ + + union { + uint32_t R; + struct { + uint32_t WST:32; + } B; + } WN; /* SWT Window Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t WSC:16; + } B; + } SR; /* SWT Service Register */ + + union { + uint32_t R; + struct { + uint32_t CNT:32; + } B; + } CO; /* SWT Counter Output Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t SK:16; + } B; + } SK; /* SWT Service Key Register */ + + }; /* end of SWT_tag */ + +/* Define memories */ + +#define SRAM0_START 0x40000000UL +#define SRAM0_SIZE 0x80000UL +#define SRAM0_END 0x4007FFFFUL + +#define SRAM1_START 0x40080000UL +#define SRAM1_SIZE 0x14000UL +#define SRAM1_END 0x40093FFFUL + +#define FLASH_START 0x0UL +#define FLASH_SIZE 0x200000UL +#define FLASH_END 0x1FFFFFUL + +/* Define instances of modules AIPS_A */ +#define MLB (*(volatile struct MLB_tag *) 0xC3F84000UL) +#define I2C_C (*(volatile struct I2C_tag *) 0xC3F88000UL) +#define I2C_D (*(volatile struct I2C_tag *) 0xC3F8C000UL) +#define DSPI_C (*(volatile struct DSPI_tag *) 0xC3F90000UL) +#define DSPI_D (*(volatile struct DSPI_tag *) 0xC3F94000UL) +#define ESCI_J (*(volatile struct ESCI_tag *) 0xC3FA0000UL) +#define ESCI_K (*(volatile struct ESCI_tag *) 0xC3FA4000UL) +#define ESCI_L (*(volatile struct ESCI_tag *) 0xC3FA8000UL) +#define ESCI_M (*(volatile struct ESCI_tag *) 0xC3FAC000UL) +#define FR (*(volatile struct FR_tag *) 0xC3FDC000UL) + +/* Define instances of modules AIPS_B */ +#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000UL) +#define SEMA4 (*(volatile struct SEMA4_tag *) 0xFFF10000UL) +#define MPU (*(volatile struct MPU_tag *) 0xFFF14000UL) +#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL) +#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL) +#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL) +#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) +#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL) +#define FEC (*(volatile struct FEC_tag *) 0xFFF4C000UL) +#define ADC (*(volatile struct ADC_tag *) 0xFFF80000UL) +#define I2C_A (*(volatile struct I2C_tag *) 0xFFF88000UL) +#define I2C_B (*(volatile struct I2C_tag *) 0xFFF8C000UL) +#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000UL) +#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000UL) +#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFA0000UL) +#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFA4000UL) +#define ESCI_C (*(volatile struct ESCI_tag *) 0xFFFA8000UL) +#define ESCI_D (*(volatile struct ESCI_tag *) 0xFFFAC000UL) +#define ESCI_E (*(volatile struct ESCI_tag *) 0xFFFB0000UL) +#define ESCI_F (*(volatile struct ESCI_tag *) 0xFFFB4000UL) +#define ESCI_G (*(volatile struct ESCI_tag *) 0xFFFB8000UL) +#define ESCI_H (*(volatile struct ESCI_tag *) 0xFFFBC000UL) +#define CAN_A (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL) +#define CAN_B (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL) +#define CAN_C (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL) +#define CAN_D (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL) +#define CAN_E (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL) +#define CAN_F (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL) +#define CTU (*(volatile struct CTU_tag *) 0xFFFD8000UL) +#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL) +#define PIT (*(volatile struct PIT_tag *) 0xFFFE0000UL) +#define PIT_RTI (*(volatile struct PIT_tag *) 0xFFFE0000UL) +#define EMIOS (*(volatile struct EMIOS_tag *) 0xFFFE4000UL) +#define SIU (*(volatile struct SIU_tag *) 0xFFFE8000UL) +#define CRP (*(volatile struct CRP_tag *) 0xFFFEC000UL) +#define FMPLL (*(volatile struct FMPLL_tag *) 0xFFFF0000UL) +#define FLASH (*(volatile struct FLASH_tag *) 0xFFFF8000UL) + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ +#endif /* ifdef _MPC5668_H */ diff --git a/bsps/powerpc/include/mpc55xx/fsl-mpc567x.h b/bsps/powerpc/include/mpc55xx/fsl-mpc567x.h new file mode 100644 index 0000000000..31a132a096 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/fsl-mpc567x.h @@ -0,0 +1,6630 @@ +/* + * Modifications of the original file provided by Freescale are: + * + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/**************************************************************************/ +/* FILE NAME: mpc5674f.h COPYRIGHT (c) Freescale 2009 */ +/* VERSION: 1.04 All Rights Reserved */ +/* */ +/* DESCRIPTION: */ +/* This file contains all of the register and bit field definitions for */ +/* MPC5674F. */ +/*========================================================================*/ +/* UPDATE HISTORY */ +/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ +/* --- ----------- --------- --------------------- */ +/* NOTE: Branch pulled at version 0.87 for mpc5674_c.h version 1.00 */ +/* 1.00 B. Terry Corrected DECFILT addresses and added */ +/* 4 additional filters for Rev. 2 */ +/* 1.01 B. Terry 16/Nov/09 Corrected bit definitions in SIUDIV */ +/* register. */ +/* 1.02 B. Terry 19/Nov/09 Added ISEL8, ISEL9, ISEL10, and ISEL11 */ +/* regs to SIU tag. (Mamba 2 features) */ +/* 1.03 B. Terry 19/Nov/09 Renamed ISEL10 and ISEL11 to DECFIL1 */ +/* and DECFIL2 to match RM. */ +/* 1.04 B. Terry 22/Jan/10 Updated bitfields of MPU RGDx Word2 */ +/* register to reflect Mamba 2. Added */ +/* MXCR and MXSR registers to DecFilt. */ +/* Removed pre-release rev history. */ +/**************************************************************************/ + +#ifndef _MPC5674F_H_ +#define _MPC5674F_H_ + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/****************************************************************************/ +/* MODULE : PBRIDGE_A Peripheral Bridge */ +/****************************************************************************/ + + struct PBRIDGE_A_tag { + + union { /* Master Privilege Control Register 0*/ + uint32_t R; + struct { + uint32_t MBW0:1; /* z7 Core */ + uint32_t MTR0:1; + uint32_t MTW0:1; + uint32_t MPL0:1; + uint32_t MBW1:1; /* Nexus */ + uint32_t MTR1:1; + uint32_t MTW1:1; + uint32_t MPL1:1; + uint32_t MBW2:1; /* Reserved */ + uint32_t MTR2:1; + uint32_t MTW2:1; + uint32_t MPL2:1; + uint32_t MBW3:1; /* Reserved */ + uint32_t MTR3:1; + uint32_t MTW3:1; + uint32_t MPL3:1; + uint32_t MBW4:1; /* eDMA A */ + uint32_t MTR4:1; + uint32_t MTW4:1; + uint32_t MPL4:1; + uint32_t MBW5:1; /* eDMA B */ + uint32_t MTR5:1; + uint32_t MTW5:1; + uint32_t MPL5:1; + uint32_t MBW6:1; /* FLEXRAY */ + uint32_t MTR6:1; + uint32_t MTW6:1; + uint32_t MPL6:1; + uint32_t MBW7:1; /* EBI */ + uint32_t MTR7:1; + uint32_t MTW7:1; + uint32_t MPL7:1; + } B; + } MPCR; + + union { /* Master Privilege Control Register 1 */ + uint32_t R; + struct { + uint32_t:32; /* reserved */ + } B; + } MPCR1; + + uint32_t PBRIDGE_A_reserved0008[6]; /* 0x0008-0x001F */ + + union { /* Peripheral Access Control Register 0 */ + uint32_t R; + struct { + uint32_t BW0:1; /* PBRIDGE_A */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } PACR0; + + uint32_t PBRIDGE_A_reserved0024[7]; /* 0x0024-0x003F */ + + union { /* Off-Platform Peripheral Access Control Register 0 */ + uint32_t R; + struct { + uint32_t BW0:1; /* FMPLL */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; /* EBI control */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; /* Flash A control */ + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t BW3:1; /* Flash B control */ + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + uint32_t BW4:1; /* SIU */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } OPACR0; + + union { /* Off-Platform Peripheral Access Control Register 1 */ + uint32_t R; + struct { + uint32_t BW0:1; /* EMIOS */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW7:1; /* PMC */ + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR1; + + union { /* Off-Platform Peripheral Access Control Register 2 */ + uint32_t R; + struct { + uint32_t BW0:1; /* eTPU */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:4; /* Reserved */ + uint32_t BW2:1; /* eTPU PRAM */ + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t BW3:1; /* eTPU PRAM mirror */ + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + uint32_t BW4:1; /* eTPU SCM */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t BW5:1; /* eTPU SCM */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } OPACR2; + + union { /* Off-Platform Peripheral Access Control Register 3 */ + uint32_t R; + struct { + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW4:1; /* PIT/RTI */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } OPACR3; + + uint32_t PBRIDGE_A_reserved0050[4076]; /* 0x0050-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : PBRIDGE_B Peripheral Bridge */ +/****************************************************************************/ + + struct PBRIDGE_B_tag { + + union { /* Master Privilege Control Register 0 */ + uint32_t R; + struct { + uint32_t MBW0:1; /* z7 Core */ + uint32_t MTR0:1; + uint32_t MTW0:1; + uint32_t MPL0:1; + uint32_t MBW1:1; /* Nexus */ + uint32_t MTR1:1; + uint32_t MTW1:1; + uint32_t MPL1:1; + uint32_t MBW2:1; /* Reserved */ + uint32_t MTR2:1; + uint32_t MTW2:1; + uint32_t MPL2:1; + uint32_t MBW3:1; /* Reserved */ + uint32_t MTR3:1; + uint32_t MTW3:1; + uint32_t MPL3:1; + uint32_t MBW4:1; /* eDMA A */ + uint32_t MTR4:1; + uint32_t MTW4:1; + uint32_t MPL4:1; + uint32_t MBW5:1; /* eDMA B */ + uint32_t MTR5:1; + uint32_t MTW5:1; + uint32_t MPL5:1; + uint32_t MBW6:1; /* FLEXRAY */ + uint32_t MTR6:1; + uint32_t MTW6:1; + uint32_t MPL6:1; + uint32_t MBW7:1; /* EBI */ + uint32_t MTR7:1; + uint32_t MTW7:1; + uint32_t MPL7:1; + } B; + } MPCR; + + union { /* Master Privilege Control Register 1 */ + uint32_t R; + struct { + uint32_t:32; /* Reserved */ + + } B; + } MPCR1; + + uint32_t PBRIDGE_B_reserved0008[6]; /* 0x0008-0x001F */ + + union { /* Peripheral Access Control Register 0 */ + uint32_t R; + struct { + uint32_t BW0:1; /* PBRIDGE B */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; /* XBAR */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW4:1; /* MPU */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } PACR0; + + union { /* Peripheral Access Control Register 1 */ + uint32_t R; + struct { + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW6:1; /* SWT */ + uint32_t SP6:1; + uint32_t WP6:1; + uint32_t TP6:1; + uint32_t BW7:1; /* STM */ + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } PACR1; + + union { /* Peripheral Access Control Register 2 */ + uint32_t R; + struct { + uint32_t BW0:1; /* ECSM */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; /* eDMA A */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; /* INTC */ + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW5:1; /* eDMA B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } PACR2; + + uint32_t PBRIDGE_B_reserved002C[5]; /* 0x002C-0x003F */ + + union { /* Off-Platform Peripheral Access Control Register 0 */ + uint32_t R; + struct { + uint32_t BW0:1; /* eQADC A */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; /* eQADC B */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; /* Decimation Filters A, B, C, D */ + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t:4; /* Reserved */ + uint32_t BW4:1; /* DSPI_A */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t BW5:1; /* DSPI_B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + uint32_t BW6:1; /* DSPI_C */ + uint32_t SP6:1; + uint32_t WP6:1; + uint32_t TP6:1; + uint32_t BW7:1; /* DSPI_D */ + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR0; + + union { /* Off-Platform Peripheral Access Control Register 1 */ + uint32_t R; + struct { + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW4:1; /* ESCI_A */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t BW5:1; /* ESCI_B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + uint32_t BW6:1; /* ESCI_C */ + uint32_t SP6:1; + uint32_t WP6:1; + uint32_t TP6:1; + uint32_t:4; /* Reserved */ + } B; + } OPACR1; + + union { /* Off-Platform Peripheral Access Control Register 2 */ + uint32_t R; + struct { + uint32_t BW0:1; /* FlexCAN_A */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; /* FlexCAN_B */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; /* FlexCAN_C */ + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t BW3:1; /* FlexCAN_D */ + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } OPACR2; + + union { /* Off-Platform Peripheral Access Control Register 3 */ + uint32_t R; + struct { + uint32_t BW0:1; /* FlexRAY */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW3:1; /* Temp Sensor */ + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW7:1; /* BAM */ + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR3; + + uint32_t PBRIDGE_B_reserved0050[4076]; /* 0x0050-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : FMPLL */ +/****************************************************************************/ + + struct FMPLL_tag { + + uint32_t FMPLL_reserved0000; /* 0x0000-0x0003 */ + + union FMPLL_SYNSR_tag { /* FMPLL Synthesizer Status Register */ + uint32_t R; + struct { + uint32_t:22; + uint32_t LOLF:1; + uint32_t LOC:1; + uint32_t MODE:1; + uint32_t PLLSEL:1; + uint32_t PLLREF:1; + uint32_t LOCKS:1; + uint32_t LOCK:1; + uint32_t LOCF:1; + uint32_t CALDONE:1; + uint32_t CALPASS:1; + } B; + } SYNSR; + + union FMPLL_ESYNCR1_tag {/* FMPLL Enhanced Synthesizer Control Register 1 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t CLKCFG:3; + uint32_t:8; + uint32_t EPREDIV:4; + uint32_t :8; + uint32_t EMFD:8; + } B; + } ESYNCR1; + + union FMPLL_ESYNCR2_tag {/* FMPLL Enhanced Synthesizer Control Register 2 */ + uint32_t R; + struct { + uint32_t:8; + uint32_t LOCEN:1; + uint32_t LOLRE:1; + uint32_t LOCRE:1; + uint32_t LOLIRQ:1; + uint32_t LOCIRQ:1; + uint32_t:1; + uint32_t ERATE:2; + uint32_t CLKCFG_DIS:1; + uint32_t:4; + uint32_t EDEPTH:3; + uint32_t:2; + uint32_t ERFD:6; + } B; + } ESYNCR2; + + uint32_t FMPLL_reserved0010[4092]; /* 0x0010-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : External Bus Interface (EBI) */ +/****************************************************************************/ + + struct EBI_CS_tag { + uint32_t ebi_cs_reserved [2]; + }; + + struct EBI_CAL_CS_tag { + union { /* Calibration Base Register Bank */ + uint32_t R; + struct { + uint32_t BA:17; + uint32_t:3; + uint32_t PS:1; + uint32_t:3; + uint32_t AD_MUX:1; + uint32_t BL:1; + uint32_t WEBS:1; + uint32_t TBDIP:1; + uint32_t:1; + uint32_t SETA:1; + uint32_t BI:1; + uint32_t V:1; + } B; + } BR; + + union { /* Calibration Option Register Bank */ + uint32_t R; + struct { + uint32_t AM:17; + uint32_t:7; + uint32_t SCY:4; + uint32_t:1; + uint32_t BSCY:2; + uint32_t:1; + } B; + } OR; + }; + + struct EBI_tag { + + union EBI_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ACGE:1; + uint32_t:8; + uint32_t MDIS:1; + uint32_t:3; + uint32_t D16_31:1; + uint32_t AD_MUX:1; + uint32_t DBM:1; + } B; + } MCR; + + uint32_t EBI_reserved0004; /* 0x0004-0x0007 */ + + union { /* Transfer Error Status Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t TEAF:1; + uint32_t BMTF:1; + } B; + } TESR; + + union { /* Bus Monitor Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t BMT:8; + uint32_t BME:1; + uint32_t:7; + } B; + } BMCR; + + /* Base/Option registers */ + struct EBI_CS_tag CS[4]; + + uint32_t EBI_reserved0030[4]; /* 0x0030-0x003F */ + + /* Calibration registers */ + struct EBI_CAL_CS_tag CAL_CS[4]; + + uint32_t EBI_reserved0060[4000]; /* 0x0060-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : FLASH */ +/****************************************************************************/ + + struct FLASH_tag { + + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:5; + uint32_t SIZE:3; + uint32_t:1; + uint32_t LAS:3; + uint32_t:3; + uint32_t MAS:1; + uint32_t EER:1; + uint32_t RWE:1; + uint32_t SBC:1; + uint32_t:1; + uint32_t PEAS:1; + uint32_t DONE:1; + uint32_t PEG:1; + uint32_t:4; + uint32_t PGM:1; + uint32_t PSUS:1; + uint32_t ERS:1; + uint32_t ESUS:1; + uint32_t EHV:1; + } B; + } MCR; + + union LMLR_tag { /* Low/Mid Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t LME:1; + uint32_t:10; + uint32_t SLOCK:1; + uint32_t:2; + uint32_t MLOCK:2; + uint32_t:6; + uint32_t LLOCK:10; + } B; + } LMLR; /* Legacy naming - refer to LML in Reference Manual */ + + union HLR_tag { /* High Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t HBE:1; + uint32_t:25; + uint32_t HBLOCK:6; /* Legacy naming - refer to HLOCK in Reference Manual */ + } B; + } HLR; /* Legacy naming - refer to HBL in Reference Manual */ + + union SLMLR_tag { /* Secondary Low/Mid Block Locking Register */ + uint32_t R; + struct { + uint32_t SLE:1; + uint32_t:10; + uint32_t SSLOCK:1; + uint32_t:2; + uint32_t SMLOCK:2; + uint32_t:6; + uint32_t SLLOCK:10; + } B; + } SLMLR; /* Legacy naming - refer to SLL in Reference Manual */ + + union { /* Low/Mid Address Space Block Select Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MSEL:2; + uint32_t:6; + uint32_t LSEL:10; + } B; + } LMSR; /* Legacy naming - refer to LMS in Reference Manual */ + + union { /* High Address Space Block Select Register */ + uint32_t R; + struct { + uint32_t:26; + uint32_t HBSEL:6; /* Legacy naming - refer to HSEL in Reference Manual */ + } B; + } HSR; /* Legacy naming - refer to HBS in Reference Manual */ + + union { /* Address Register */ + uint32_t R; + struct { + uint32_t SAD:1; + uint32_t:13; + uint32_t ADDR:15; + uint32_t:3; + } B; + } AR; /* Legacy naming - refer to ADR in Reference Manual */ + + union { /* Platform Flash Configuration Register 1 */ + uint32_t R; + struct { + uint32_t:7; + uint32_t M8PFE:1; /* z7 Nexus */ + uint32_t:1; /* EBI Testing - Reserved */ + uint32_t M6PFE:1; /* FlexRay */ + uint32_t M5PFE:1; /* eDMA_B */ + uint32_t M4PFE:1; /* eDMA_A */ + uint32_t:1; /* Reserved */ + uint32_t:1; /* Reserved */ + uint32_t:1; /* Reserved */ + uint32_t M0PFE:1; /* z7 Core */ + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + uint32_t:1; + uint32_t DPFEN:1; + uint32_t:1; + uint32_t IPFEN:1; + uint32_t:1; + uint32_t PFLIM:2; + uint32_t BFEN:1; + } B; + } BIUCR; /* Legacy naming - PFCR1 */ + + union { /*Platform Flash Access Protection Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t M8AP:2; /* z7 Nexus */ + uint32_t:2; /* EBI Testing - Reserved */ + uint32_t M6AP:2; /* FlexRay */ + uint32_t M5AP:2; /* eDMA_B */ + uint32_t M4AP:2; /* eDMA_A */ + uint32_t:2; /* Reserved */ + uint32_t:2; /* Reserved */ + uint32_t:2; /* Reserved */ + uint32_t M0AP:2; /* z7 Core */ + } B; + } BIUAPR; /* Legacy naming - refer to PFAPR in Reference Manual */ + + union { /* Platform Flash Configuration Register 2 */ + uint32_t R; + struct { + uint32_t LBCFG:2; + uint32_t:30; + } B; + } BIUCR2; + + uint32_t FLASH_reserved0028[4086]; /* 0x0028-0x3FFF */ + }; + +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + int32_t SIU_reserved0000 /* 0x0000-0x0003 */; + + union { /* MCU ID Register */ + uint32_t R; + struct { + uint32_t PARTNUM:16; + uint32_t PKG:4; + uint32_t:4; + uint32_t MAJOR_REV:4; + uint32_t MINOR_REV:4; + } B; + } MIDR; + + int32_t SIU_reserved0008; /* 0x0008-0x000B */ + + union { /* Reset Status Register */ + uint32_t R; + struct { + uint32_t PORS:1; + uint32_t ERS:1; + uint32_t LLRS:1; + uint32_t LCRS:1; + uint32_t WDRS:1; + uint32_t CRS:1; + uint32_t SWTRS:1; + uint32_t:7; + uint32_t SSRS:1; + uint32_t SERF:1; + uint32_t WKPCFG:1; + uint32_t:11; + uint32_t ABR:1; + uint32_t BOOTCFG:2; + uint32_t RGF:1; + } B; + } RSR; + + union { /* System Reset Control Register */ + uint32_t R; + struct { + uint32_t SSR:1; + uint32_t SER:1; + uint32_t:30; // Removed CRE bit + } B; + } SRCR; + + union SIU_EISR_tag { /* External Interrupt Status Register */ + uint32_t R; + struct { + uint32_t NMI:1; + uint32_t:15; + uint32_t EIF15:1; + uint32_t EIF14:1; + uint32_t EIF13:1; + uint32_t EIF12:1; + uint32_t EIF11:1; + uint32_t EIF10:1; + uint32_t EIF9:1; + uint32_t EIF8:1; + uint32_t EIF7:1; + uint32_t EIF6:1; + uint32_t EIF5:1; + uint32_t EIF4:1; + uint32_t EIF3:1; + uint32_t EIF2:1; + uint32_t EIF1:1; + uint32_t EIF0:1; + } B; + } EISR; + + union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t NMISEL8:1; + uint32_t:7; + uint32_t NMISEL0:1; + uint32_t:7; + uint32_t EIRE15:1; + uint32_t EIRE14:1; + uint32_t EIRE13:1; + uint32_t EIRE12:1; + uint32_t EIRE11:1; + uint32_t EIRE10:1; + uint32_t EIRE9:1; + uint32_t EIRE8:1; + uint32_t EIRE7:1; + uint32_t EIRE6:1; + uint32_t EIRE5:1; + uint32_t EIRE4:1; + uint32_t EIRE3:1; + uint32_t EIRE2:1; + uint32_t EIRE1:1; + uint32_t EIRE0:1; + } B; + } DIRER; + + union SIU_DIRSR_tag { /* DMA/Interrupt Request Select Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DIRS3:1; + uint32_t DIRS2:1; + uint32_t DIRS1:1; + uint32_t DIRS0:1; + } B; + } DIRSR; + + union { /* Overrun Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t OVF15:1; + uint32_t OVF14:1; + uint32_t OVF13:1; + uint32_t OVF12:1; + uint32_t OVF11:1; + uint32_t OVF10:1; + uint32_t OVF9:1; + uint32_t OVF8:1; + uint32_t OVF7:1; + uint32_t OVF6:1; + uint32_t OVF5:1; + uint32_t OVF4:1; + uint32_t OVF3:1; + uint32_t OVF2:1; + uint32_t OVF1:1; + uint32_t OVF0:1; + } B; + } OSR; + + union SIU_ORER_tag { /* Overrun Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ORE15:1; + uint32_t ORE14:1; + uint32_t ORE13:1; + uint32_t ORE12:1; + uint32_t ORE11:1; + uint32_t ORE10:1; + uint32_t ORE9:1; + uint32_t ORE8:1; + uint32_t ORE7:1; + uint32_t ORE6:1; + uint32_t ORE5:1; + uint32_t ORE4:1; + uint32_t ORE3:1; + uint32_t ORE2:1; + uint32_t ORE1:1; + uint32_t ORE0:1; + } B; + } ORER; + + union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t IREE_NMI8:1; + uint32_t:7; + uint32_t IREE_NMI0:1; + uint32_t:7; + uint32_t IREE15:1; + uint32_t IREE14:1; + uint32_t IREE13:1; + uint32_t IREE12:1; + uint32_t IREE11:1; + uint32_t IREE10:1; + uint32_t IREE9:1; + uint32_t IREE8:1; + uint32_t IREE7:1; + uint32_t IREE6:1; + uint32_t IREE5:1; + uint32_t IREE4:1; + uint32_t IREE3:1; + uint32_t IREE2:1; + uint32_t IREE1:1; + uint32_t IREE0:1; + } B; + } IREER; + + union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t IFEE_NMI8:1; + uint32_t:7; + uint32_t IFEE_NMI0:1; + uint32_t:7; + uint32_t IFEE15:1; + uint32_t IFEE14:1; + uint32_t IFEE13:1; + uint32_t IFEE12:1; + uint32_t IFEE11:1; + uint32_t IFEE10:1; + uint32_t IFEE9:1; + uint32_t IFEE8:1; + uint32_t IFEE7:1; + uint32_t IFEE6:1; + uint32_t IFEE5:1; + uint32_t IFEE4:1; + uint32_t IFEE3:1; + uint32_t IFEE2:1; + uint32_t IFEE1:1; + uint32_t IFEE0:1; + } B; + } IFEER; + + union SIU_IDFR_tag { /* External IRQ Digital Filter Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } IDFR; + + union { /* External IRQ Filtered Input Register */ + uint32_t R; + struct { + uint32_t FI31:1; + uint32_t FI30:1; + uint32_t FI29:1; + uint32_t FI28:1; + uint32_t FI27:1; + uint32_t FI26:1; + uint32_t FI25:1; + uint32_t FI24:1; + uint32_t FI23:1; + uint32_t FI22:1; + uint32_t FI21:1; + uint32_t FI20:1; + uint32_t FI19:1; + uint32_t FI18:1; + uint32_t FI17:1; + uint32_t FI16:1; + uint32_t FI15:1; + uint32_t FI14:1; + uint32_t FI13:1; + uint32_t FI12:1; + uint32_t FI11:1; + uint32_t FI10:1; + uint32_t FI9:1; + uint32_t FI8:1; + uint32_t FI7:1; + uint32_t FI6:1; + uint32_t FI5:1; + uint32_t FI4:1; + uint32_t FI3:1; + uint32_t FI2:1; + uint32_t FI1:1; + uint32_t FI0:1; + } B; + } IFIR; + + int32_t SIU_reserved0038[2]; /* 0x0038-0x003F */ + + union SIU_PCR_tag { /* Pad Configuration Registers */ + uint16_t R; + struct { + uint16_t:3; + uint16_t PA:3; + uint16_t OBE:1; + uint16_t IBE:1; + uint16_t DSC:2; + uint16_t ODE:1; + uint16_t HYS:1; + uint16_t SRC:2; + uint16_t WPE:1; + uint16_t WPS:1; + } B; + } PCR[512]; + + int16_t SIU_reserved0440[224]; /* 0x0440-0x05FF */ + + union { /* GPIO Pin Data Output Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDO:1; + } B; + } GPDO[512]; + + union { /* GPIO Pin Data Input Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; + } B; + } GPDI[256]; + + uint32_t SIU_reserved0900; /* 0x0900-0x0903 */ + + union { /* External IRQ Input Select Register */ + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } EIISR; + + union { /* DSPI Input Select Register */ + uint32_t R; + struct { + uint32_t SINSELA:2; + uint32_t SSSELA:2; + uint32_t SCKSELA:2; + uint32_t TRIGSELA:2; + uint32_t SINSELB:2; + uint32_t SSSELB:2; + uint32_t SCKSELB:2; + uint32_t TRIGSELB:2; + uint32_t SINSELC:2; + uint32_t SSSELC:2; + uint32_t SCKSELC:2; + uint32_t TRIGSELC:2; + uint32_t SINSELD:2; + uint32_t SSSELD:2; + uint32_t SCKSELD:2; + uint32_t TRIGSELD:2; + } B; + } DISR; + + int32_t SIU_reserved090C; /* 0x090C-0x090F */ + + union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */ + uint32_t R; + struct { + uint32_t:1; + uint32_t CTSEL5_0:7; + uint32_t:1; + uint32_t CTSEL4_0:7; + uint32_t:1; + uint32_t CTSEL3_0:7; + uint32_t:1; + uint32_t CTSEL2_0:7; + } B; + } ISEL4; + + union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */ + uint32_t R; + struct { + uint32_t:1; + uint32_t CTSEL1_0:7; + uint32_t:1; + uint32_t CTSEL0_0:7; + uint32_t:16; + } B; + } ISEL5; + + union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */ + uint32_t R; + struct { + uint32_t:1; + uint32_t CTSEL5_1:7; + uint32_t:1; + uint32_t CTSEL4_1:7; + uint32_t:1; + uint32_t CTSEL3_1:7; + uint32_t:1; + uint32_t CTSEL2_1:7; + } B; + } ISEL6; + + union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */ + uint32_t R; + struct { + uint32_t:1; + uint32_t CTSEL1_1:7; + uint32_t:1; + uint32_t CTSEL0_1:7; + uint32_t:16; + } B; + } ISEL7; + + union { /* eTPU Input Select Register */ + uint32_t R; + struct { + uint32_t:11; + uint32_t ETPU29:1; + uint32_t:3; + uint32_t ETPU28:1; + uint32_t:3; + uint32_t ETPU27:1; + uint32_t:3; + uint32_t ETPU26:1; + uint32_t:3; + uint32_t ETPU25:1; + uint32_t:3; + uint32_t ETPU24:1; + } B; + } ISEL8; + + union { /* eQADC Advanced Trigger Select */ + uint32_t R; + struct { + uint32_t:27; + uint32_t ETSEL0A:5; + } B; + } ISEL9; + + union { /* DecFilter Integrator Control */ + uint32_t R; + struct { + uint32_t ZSELA:4; + uint32_t HSELA:4; + uint32_t ZSELB:4; + uint32_t HSELB:4; + uint32_t ZSELC:4; + uint32_t HSELC:4; + uint32_t ZSELD:4; + uint32_t HSELD:4; + } B; + } DECFIL1; + + union { /* DecFilter Integrator Control */ + uint32_t R; + struct { + uint32_t ZSELE:4; + uint32_t HSELE:4; + uint32_t ZSELF:4; + uint32_t HSELF:4; + uint32_t ZSELG:4; + uint32_t HSELG:4; + uint32_t ZSELH:4; + uint32_t HSELH:4; + } B; + } DECFIL2; + + + int32_t SIU_reserved0920[20]; /* 0x0930-0x097F */ + + union { /* Chip Configuration Register Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MATCH:1; + uint32_t DISNEX:1; + uint32_t:16; + } B; + } CCR; + + union { /* External Clock Configuration Register Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ENGDIV:8; + uint32_t ECSS:1; + uint32_t:3; + uint32_t EBTS:1; + uint32_t:1; + uint32_t EBDF:2; + } B; + } ECCR; + + union { /* Compare A Register High */ + uint32_t R; + struct { + uint32_t CMPAH:32; + } B; + } CARH; + + union { /* Compare A Register Low */ + uint32_t R; + struct { + uint32_t CMPAL:32; + } B; + } CARL; + + union { /* Compare B Register High */ + uint32_t R; + struct { + uint32_t CMPBH:32; + } B; + } CBRH; + + union { /* Compare B Register Low */ + uint32_t R; + struct { + uint32_t CMPBL:32; + } B; + } CBRL; + + int32_t SIU_reserved0998[2]; /* 0x0998-0x099F */ + + union { /* System Clock Register */ + uint32_t R; + struct { + uint32_t:22; + uint32_t IPCLKDIV:2; + uint32_t:3; + uint32_t BYPASS:1; + uint32_t SYSCLKDIV:2; + uint32_t:2; + } B; + } SYSDIV; + + union { /* Halt Register */ + uint32_t R; + struct { + uint32_t CPUSTP:1; /* CPU and Platform stop request */ + uint32_t:4; /* Reserved */ + uint32_t TPUSTP:1; /* eTPU_A stop request */ + uint32_t NPCSTP:1; /* Nexus stop request */ + uint32_t EBISTP:1; /* EBI stop request*/ + uint32_t ADCSTP:1; /* eQADC stop request */ + uint32_t:1; /* Reserved */ + uint32_t MIOSSTP:1; /* eMIOS stop request */ + uint32_t DFILSTP:1; /* Decimation filter stop request */ + uint32_t:1; /* Reserved */ + uint32_t PITSTP:1; /* PIT stop request */ + uint32_t:2; /* Reserved */ + uint32_t CNDSTP:1; /* FlexCAN D stop request */ + uint32_t CNCSTP:1; /* FlexCAN C stop request */ + uint32_t CNBSTP:1; /* FlexCAN B stop request */ + uint32_t CNASTP:1; /* FlexCAN A stop request */ + uint32_t SPIDSTP:1; /* DSPI D stop request */ + uint32_t SPICSTP:1; /* DSPI C stop request */ + uint32_t SPIBSTP:1; /* DSPI B stop request */ + uint32_t SPIASTP:1; /* DSPI C stop request */ + uint32_t:5; /* Reserved */ + uint32_t SCICSTP:1; /* eSCI C stop request */ + uint32_t SCIBSTP:1; /* eSCI B stop request */ + uint32_t SCIASTP:1; /* eSCI A stop request */ + } B; + } HLT; + + union { /* Halt Acknowledge Register */ + uint32_t R; + struct { + uint32_t CPUACK:1; /* CPU and Platform stop acknowledge */ + uint32_t:4; /* Reserved */ + uint32_t TPUACK:1; /* eTPU_A stop acknowledge */ + uint32_t NPCACK:1; /* Nexus stop acknowledge */ + uint32_t EBIACK:1; /* EBI stop acknowledge*/ + uint32_t ADCACK:1; /* eQADC stop acknowledge */ + uint32_t:1; /* Reserved */ + uint32_t MIOSACK:1; /* eMIOS stop acknowledge */ + uint32_t DFILACK:1; /* Decimation filter stop acknowledge */ + uint32_t:1; /* Reserved */ + uint32_t PITACK:1; /* PIT stop acknowledge */ + uint32_t:2; /* Reserved */ + uint32_t CNDACK:1; /* FlexCAN D stop acknowledge */ + uint32_t CNCACK:1; /* FlexCAN C stop acknowledge */ + uint32_t CNBACK:1; /* FlexCAN B stop acknowledge */ + uint32_t CNAACK:1; /* FlexCAN A stop acknowledge */ + uint32_t SPIDACK:1; /* DSPI D stop acknowledge */ + uint32_t SPICACK:1; /* DSPI C stop acknowledge */ + uint32_t SPIBACK:1; /* DSPI B stop acknowledge */ + uint32_t SPIAACK:1; /* DSPI C stop acknowledge */ + uint32_t:5; /* Reserved */ + uint32_t SCICACK:1; /* eSCI C stop acknowledge */ + uint32_t SCIBACK:1; /* eSCI B stop acknowledge */ + uint32_t SCIAACK:1; /* eSCI A stop acknowledge */ + } B; + } HLTACK; + + int32_t SIU_reserved09AC[21]; /* 0x09AC-0x09FF */ + + int32_t SIU_reserved0A00[128]; /* 0x0A00-0x0BFF */ + + union { /* Parallel GPIO Pin Data Output Register */ + uint32_t R; + struct { + uint32_t PGPDO0:1; + uint32_t PGPDO1:1; + uint32_t PGPDO2:1; + uint32_t PGPDO3:1; + uint32_t PGPDO4:1; + uint32_t PGPDO5:1; + uint32_t PGPDO6:1; + uint32_t PGPDO7:1; + uint32_t PGPDO8:1; + uint32_t PGPDO9:1; + uint32_t PGPDO10:1; + uint32_t PGPDO11:1; + uint32_t PGPDO12:1; + uint32_t PGPDO13:1; + uint32_t PGPDO14:1; + uint32_t PGPDO15:1; + uint32_t PGPDO16:1; + uint32_t PGPDO17:1; + uint32_t PGPDO18:1; + uint32_t PGPDO19:1; + uint32_t PGPDO20:1; + uint32_t PGPDO21:1; + uint32_t PGPDO22:1; + uint32_t PGPDO23:1; + uint32_t PGPDO24:1; + uint32_t PGPDO25:1; + uint32_t PGPDO26:1; + uint32_t PGPDO27:1; + uint32_t PGPDO28:1; + uint32_t PGPDO29:1; + uint32_t PGPDO30:1; + uint32_t PGPDO31:1; + } B; + } PGPDO[16]; + + union { /* Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PGPDI0:1; + uint32_t PGPDI1:1; + uint32_t PGPDI2:1; + uint32_t PGPDI3:1; + uint32_t PGPDI4:1; + uint32_t PGPDI5:1; + uint32_t PGPDI6:1; + uint32_t PGPDI7:1; + uint32_t PGPDI8:1; + uint32_t PGPDI9:1; + uint32_t PGPDI10:1; + uint32_t PGPDI11:1; + uint32_t PGPDI12:1; + uint32_t PGPDI13:1; + uint32_t PGPDI14:1; + uint32_t PGPDI15:1; + uint32_t PGPDI16:1; + uint32_t PGPDI17:1; + uint32_t PGPDI18:1; + uint32_t PGPDI19:1; + uint32_t PGPDI20:1; + uint32_t PGPDI21:1; + uint32_t PGPDI22:1; + uint32_t PGPDI23:1; + uint32_t PGPDI24:1; + uint32_t PGPDI25:1; + uint32_t PGPDI26:1; + uint32_t PGPDI27:1; + uint32_t PGPDI28:1; + uint32_t PGPDI29:1; + uint32_t PGPDI30:1; + uint32_t PGPDI31:1; + } B; + } PGPDI[16]; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t MASK0:1; + uint32_t MASK1:1; + uint32_t MASK2:1; + uint32_t MASK3:1; + uint32_t MASK4:1; + uint32_t MASK5:1; + uint32_t MASK6:1; + uint32_t MASK7:1; + uint32_t MASK8:1; + uint32_t MASK9:1; + uint32_t MASK10:1; + uint32_t MASK11:1; + uint32_t MASK12:1; + uint32_t MASK13:1; + uint32_t MASK14:1; + uint32_t MASK15:1; + uint32_t DATA0:1; + uint32_t DATA1:1; + uint32_t DATA2:1; + uint32_t DATA3:1; + uint32_t DATA4:1; + uint32_t DATA5:1; + uint32_t DATA6:1; + uint32_t DATA7:1; + uint32_t DATA8:1; + uint32_t DATA9:1; + uint32_t DATA10:1; + uint32_t DATA11:1; + uint32_t DATA12:1; + uint32_t DATA13:1; + uint32_t DATA14:1; + uint32_t DATA15:1; + } B; + } MPGPDO[32]; + + union { /* DSPI_A Mask Output High Register */ + uint32_t R; + struct { + uint32_t MASK0:1; + uint32_t MASK1:1; + uint32_t MASK2:1; + uint32_t MASK3:1; + uint32_t MASK4:1; + uint32_t MASK5:1; + uint32_t MASK6:1; + uint32_t MASK7:1; + uint32_t MASK8:1; + uint32_t MASK9:1; + uint32_t MASK10:1; + uint32_t MASK11:1; + uint32_t MASK12:1; + uint32_t MASK13:1; + uint32_t MASK14:1; + uint32_t MASK15:1; + uint32_t DATA0:1; + uint32_t DATA1:1; + uint32_t DATA2:1; + uint32_t DATA3:1; + uint32_t DATA4:1; + uint32_t DATA5:1; + uint32_t DATA6:1; + uint32_t DATA7:1; + uint32_t DATA8:1; + uint32_t DATA9:1; + uint32_t DATA10:1; + uint32_t DATA11:1; + uint32_t DATA12:1; + uint32_t DATA13:1; + uint32_t DATA14:1; + uint32_t DATA15:1; + } B; + } DSPIAH; + + union { /* DSPI_A Mask Output Low Register */ + uint32_t R; + struct { + uint32_t MASK16:1; + uint32_t MASK17:1; + uint32_t MASK18:1; + uint32_t MASK19:1; + uint32_t MASK20:1; + uint32_t MASK21:1; + uint32_t MASK22:1; + uint32_t MASK23:1; + uint32_t MASK24:1; + uint32_t MASK25:1; + uint32_t MASK26:1; + uint32_t MASK27:1; + uint32_t MASK28:1; + uint32_t MASK29:1; + uint32_t MASK30:1; + uint32_t MASK31:1; + uint32_t DATA16:1; + uint32_t DATA17:1; + uint32_t DATA18:1; + uint32_t DATA19:1; + uint32_t DATA20:1; + uint32_t DATA21:1; + uint32_t DATA22:1; + uint32_t DATA23:1; + uint32_t DATA24:1; + uint32_t DATA25:1; + uint32_t DATA26:1; + uint32_t DATA27:1; + uint32_t DATA28:1; + uint32_t DATA29:1; + uint32_t DATA30:1; + uint32_t DATA31:1; + } B; + } DSPIAL; + + union { /* DSPI_B Mask Output High Register */ + uint32_t R; + struct { + uint32_t MASK0:1; + uint32_t MASK1:1; + uint32_t MASK2:1; + uint32_t MASK3:1; + uint32_t MASK4:1; + uint32_t MASK5:1; + uint32_t MASK6:1; + uint32_t MASK7:1; + uint32_t MASK8:1; + uint32_t MASK9:1; + uint32_t MASK10:1; + uint32_t MASK11:1; + uint32_t MASK12:1; + uint32_t MASK13:1; + uint32_t MASK14:1; + uint32_t MASK15:1; + uint32_t DATA0:1; + uint32_t DATA1:1; + uint32_t DATA2:1; + uint32_t DATA3:1; + uint32_t DATA4:1; + uint32_t DATA5:1; + uint32_t DATA6:1; + uint32_t DATA7:1; + uint32_t DATA8:1; + uint32_t DATA9:1; + uint32_t DATA10:1; + uint32_t DATA11:1; + uint32_t DATA12:1; + uint32_t DATA13:1; + uint32_t DATA14:1; + uint32_t DATA15:1; + } B; + } DSPIBH; + + union { /* DSPI_B Mask Output Low Register */ + uint32_t R; + struct { + uint32_t MASK16:1; + uint32_t MASK17:1; + uint32_t MASK18:1; + uint32_t MASK19:1; + uint32_t MASK20:1; + uint32_t MASK21:1; + uint32_t MASK22:1; + uint32_t MASK23:1; + uint32_t MASK24:1; + uint32_t MASK25:1; + uint32_t MASK26:1; + uint32_t MASK27:1; + uint32_t MASK28:1; + uint32_t MASK29:1; + uint32_t MASK30:1; + uint32_t MASK31:1; + uint32_t DATA16:1; + uint32_t DATA17:1; + uint32_t DATA18:1; + uint32_t DATA19:1; + uint32_t DATA20:1; + uint32_t DATA21:1; + uint32_t DATA22:1; + uint32_t DATA23:1; + uint32_t DATA24:1; + uint32_t DATA25:1; + uint32_t DATA26:1; + uint32_t DATA27:1; + uint32_t DATA28:1; + uint32_t DATA29:1; + uint32_t DATA30:1; + uint32_t DATA31:1; + } B; + } DSPIBL; + + union { /* DSPI_C Mask Output High Register */ + uint32_t R; + struct { + uint32_t MASK0:1; + uint32_t MASK1:1; + uint32_t MASK2:1; + uint32_t MASK3:1; + uint32_t MASK4:1; + uint32_t MASK5:1; + uint32_t MASK6:1; + uint32_t MASK7:1; + uint32_t MASK8:1; + uint32_t MASK9:1; + uint32_t MASK10:1; + uint32_t MASK11:1; + uint32_t MASK12:1; + uint32_t MASK13:1; + uint32_t MASK14:1; + uint32_t MASK15:1; + uint32_t DATA0:1; + uint32_t DATA1:1; + uint32_t DATA2:1; + uint32_t DATA3:1; + uint32_t DATA4:1; + uint32_t DATA5:1; + uint32_t DATA6:1; + uint32_t DATA7:1; + uint32_t DATA8:1; + uint32_t DATA9:1; + uint32_t DATA10:1; + uint32_t DATA11:1; + uint32_t DATA12:1; + uint32_t DATA13:1; + uint32_t DATA14:1; + uint32_t DATA15:1; + } B; + } DSPICH; + + union { /* DSPI_C Mask Output Low Register */ + uint32_t R; + struct { + uint32_t MASK16:1; + uint32_t MASK17:1; + uint32_t MASK18:1; + uint32_t MASK19:1; + uint32_t MASK20:1; + uint32_t MASK21:1; + uint32_t MASK22:1; + uint32_t MASK23:1; + uint32_t MASK24:1; + uint32_t MASK25:1; + uint32_t MASK26:1; + uint32_t MASK27:1; + uint32_t MASK28:1; + uint32_t MASK29:1; + uint32_t MASK30:1; + uint32_t MASK31:1; + uint32_t DATA16:1; + uint32_t DATA17:1; + uint32_t DATA18:1; + uint32_t DATA19:1; + uint32_t DATA20:1; + uint32_t DATA21:1; + uint32_t DATA22:1; + uint32_t DATA23:1; + uint32_t DATA24:1; + uint32_t DATA25:1; + uint32_t DATA26:1; + uint32_t DATA27:1; + uint32_t DATA28:1; + uint32_t DATA29:1; + uint32_t DATA30:1; + uint32_t DATA31:1; + } B; + } DSPICL; + + union { /* DSPI_D Mask Output High Register */ + uint32_t R; + struct { + uint32_t MASK0:1; + uint32_t MASK1:1; + uint32_t MASK2:1; + uint32_t MASK3:1; + uint32_t MASK4:1; + uint32_t MASK5:1; + uint32_t MASK6:1; + uint32_t MASK7:1; + uint32_t MASK8:1; + uint32_t MASK9:1; + uint32_t MASK10:1; + uint32_t MASK11:1; + uint32_t MASK12:1; + uint32_t MASK13:1; + uint32_t MASK14:1; + uint32_t MASK15:1; + uint32_t DATA0:1; + uint32_t DATA1:1; + uint32_t DATA2:1; + uint32_t DATA3:1; + uint32_t DATA4:1; + uint32_t DATA5:1; + uint32_t DATA6:1; + uint32_t DATA7:1; + uint32_t DATA8:1; + uint32_t DATA9:1; + uint32_t DATA10:1; + uint32_t DATA11:1; + uint32_t DATA12:1; + uint32_t DATA13:1; + uint32_t DATA14:1; + uint32_t DATA15:1; + } B; + } DSPIDH; + + union { /* DSPI_D Mask Output Low Register */ + uint32_t R; + struct { + uint32_t MASK16:1; + uint32_t MASK17:1; + uint32_t MASK18:1; + uint32_t MASK19:1; + uint32_t MASK20:1; + uint32_t MASK21:1; + uint32_t MASK22:1; + uint32_t MASK23:1; + uint32_t MASK24:1; + uint32_t MASK25:1; + uint32_t MASK26:1; + uint32_t MASK27:1; + uint32_t MASK28:1; + uint32_t MASK29:1; + uint32_t MASK30:1; + uint32_t MASK31:1; + uint32_t DATA16:1; + uint32_t DATA17:1; + uint32_t DATA18:1; + uint32_t DATA19:1; + uint32_t DATA20:1; + uint32_t DATA21:1; + uint32_t DATA22:1; + uint32_t DATA23:1; + uint32_t DATA24:1; + uint32_t DATA25:1; + uint32_t DATA26:1; + uint32_t DATA27:1; + uint32_t DATA28:1; + uint32_t DATA29:1; + uint32_t DATA30:1; + uint32_t DATA31:1; + } B; + } DSPIDL; + + int32_t SIU_reserved0D20[8]; /* 0x0D20-0x0D3F */ + + union { /* ETPU B Select Register */ + uint32_t R; + struct { + uint32_t ETPUB15:1; + uint32_t ETPUB14:1; + uint32_t ETPUB13:1; + uint32_t ETPUB12:1; + uint32_t ETPUB11:1; + uint32_t ETPUB10:1; + uint32_t ETPUB9:1; + uint32_t ETPUB8:1; + uint32_t ETPUB7:1; + uint32_t ETPUB6:1; + uint32_t ETPUB5:1; + uint32_t ETPUB4:1; + uint32_t ETPUB3:1; + uint32_t ETPUB2:1; + uint32_t ETPUB1:1; + uint32_t ETPUB0:1; + uint32_t ETPUB31:1; + uint32_t ETPUB30:1; + uint32_t ETPUB29:1; + uint32_t ETPUB28:1; + uint32_t ETPUB27:1; + uint32_t ETPUB26:1; + uint32_t ETPUB25:1; + uint32_t ETPUB24:1; + uint32_t ETPUB23:1; + uint32_t ETPUB22:1; + uint32_t ETPUB21:1; + uint32_t ETPUB20:1; + uint32_t ETPUB19:1; + uint32_t ETPUB18:1; + uint32_t ETPUB17:1; + uint32_t ETPUB16:1; + } B ; + } ETPUBA; + + union { /* EMIOS A Select Register */ + uint32_t R; + struct { + uint32_t EMIOS7:1; + uint32_t EMIOS6:1; + uint32_t EMIOS5:1; + uint32_t EMIOS4:1; + uint32_t EMIOS3:1; + uint32_t EMIOS2:1; + uint32_t EMIOS1:1; + uint32_t EMIOS0:1; + uint32_t EMIOS8:1; + uint32_t EMIOS9:1; + uint32_t EMIOS10:1; + uint32_t EMIOS11:1; + uint32_t EMIOS12:1; + uint32_t EMIOS13:1; + uint32_t EMIOS14:1; + uint32_t EMIOS15:1; + uint32_t EMIOS16:1; + uint32_t EMIOS17:1; + uint32_t EMIOS18:1; + uint32_t EMIOS19:1; + uint32_t EMIOS20:1; + uint32_t EMIOS21:1; + uint32_t EMIOS22:1; + uint32_t EMIOS23:1; + uint32_t EMIOS0_0:1; + uint32_t EMIOS1_1:1; + uint32_t EMIOS2_2:1; + uint32_t EMIOS3_3:1; + uint32_t EMIOS4_4:1; + uint32_t EMIOS5_5:1; + uint32_t EMIOS6_6:1; + uint32_t EMIOS7_7:1; + } B; + } EMIOSA; + + union { /* DSPIAH/L Select Register for DSPI A */ + uint32_t R; + struct { + uint32_t DSPIAH0:1; + uint32_t DSPIAH1:1; + uint32_t DSPIAH2:1; + uint32_t DSPIAH3:1; + uint32_t DSPIAH4:1; + uint32_t DSPIAH5:1; + uint32_t DSPIAH6:1; + uint32_t DSPIAH7:1; + uint32_t DSPIAH8:1; + uint32_t DSPIAH9:1; + uint32_t DSPIAH10:1; + uint32_t DSPIAH11:1; + uint32_t DSPIAH12:1; + uint32_t DSPIAH13:1; + uint32_t DSPIAH14:1; + uint32_t DSPIAH15:1; + uint32_t DSPIAL16:1; + uint32_t DSPIAL17:1; + uint32_t DSPIAL18:1; + uint32_t DSPIAL19:1; + uint32_t DSPIAL20:1; + uint32_t DSPIAL21:1; + uint32_t DSPIAL22:1; + uint32_t DSPIAL23:1; + uint32_t DSPIAL24:1; + uint32_t DSPIAL25:1; + uint32_t DSPIAL26:1; + uint32_t DSPIAL27:1; + uint32_t DSPIAL28:1; + uint32_t DSPIAL29:1; + uint32_t DSPIAL30:1; + uint32_t DSPIAL31:1; + } B; + } DSPIAHLA; + + int32_t SIU_reserved0D4C; /* 0x0D4C-0x0D4F */ + + union { /* ETPU A Select Register */ + uint32_t R; + struct { + uint32_t ETPUA23:1; + uint32_t ETPUA22:1; + uint32_t ETPUA21:1; + uint32_t ETPUA20:1; + uint32_t ETPUA19:1; + uint32_t ETPUA18:1; + uint32_t ETPUA17:1; + uint32_t ETPUA16:1; + uint32_t ETPUA29:1; + uint32_t ETPUA28:1; + uint32_t ETPUA27:1; + uint32_t ETPUA26:1; + uint32_t ETPUA25:1; + uint32_t ETPUA24:1; + uint32_t ETPUA31:1; + uint32_t ETPUA30:1; + uint32_t ETPUA12:1; + uint32_t ETPUA13:1; + uint32_t ETPUA14:1; + uint32_t ETPUA15:1; + uint32_t ETPUA0:1; + uint32_t ETPUA1:1; + uint32_t ETPUA2:1; + uint32_t ETPUA3:1; + uint32_t ETPUA4:1; + uint32_t ETPUA5:1; + uint32_t ETPUA6:1; + uint32_t ETPUA7:1; + uint32_t ETPUA8:1; + uint32_t ETPUA9:1; + uint32_t ETPUA10:1; + uint32_t ETPUA11:1; + } B ; + } ETPUAB; + + union { /* EMIOS B Select Register */ + uint32_t R; + struct { + uint32_t EMIOS11:1; + uint32_t EMIOS10:1; + uint32_t EMIOS9:1; + uint32_t EMIOS8:1; + uint32_t EMIOS6:1; + uint32_t EMIOS5:1; + uint32_t EMIOS4:1; + uint32_t EMIOS3:1; + uint32_t EMIOS2:1; + uint32_t EMIOS1:1; + uint32_t EMIOS0:1; + uint32_t EMIOS23:1; + uint32_t EMIOS15:1; + uint32_t EMIOS14:1; + uint32_t EMIOS13:1; + uint32_t EMIOS12:1; + uint32_t EMIOS23_23:1; + uint32_t EMIOS15_15:1; + uint32_t EMIOS14_14:1; + uint32_t EMIOS13_13:1; + uint32_t EMIOS12_12:1; + uint32_t EMIOS11_11:1; + uint32_t EMIOS10_10:1; + uint32_t EMIOS9_9:1; + uint32_t EMIOS8_8:1; + uint32_t EMIOS6_6:1; + uint32_t EMIOS5_5:1; + uint32_t EMIOS4_4:1; + uint32_t EMIOS3_3:1; + uint32_t EMIOS2_2:1; + uint32_t EMIOS1_1:1; + uint32_t EMIOS0_0:1; + } B; + } EMIOSB; + + union { /* DSPIBH/L Select Register for DSPI B */ + uint32_t R; + struct { + uint32_t DSPIBH0:1; + uint32_t DSPIBH1:1; + uint32_t DSPIBH2:1; + uint32_t DSPIBH3:1; + uint32_t DSPIBH4:1; + uint32_t DSPIBH5:1; + uint32_t DSPIBH6:1; + uint32_t DSPIBH7:1; + uint32_t DSPIBH8:1; + uint32_t DSPIBH9:1; + uint32_t DSPIBH10:1; + uint32_t DSPIBH11:1; + uint32_t DSPIBH12:1; + uint32_t DSPIBH13:1; + uint32_t DSPIBH14:1; + uint32_t DSPIBH15:1; + uint32_t DSPIBL16:1; + uint32_t DSPIBL17:1; + uint32_t DSPIBL18:1; + uint32_t DSPIBL19:1; + uint32_t DSPIBL20:1; + uint32_t DSPIBL21:1; + uint32_t DSPIBL22:1; + uint32_t DSPIBL23:1; + uint32_t DSPIBL24:1; + uint32_t DSPIBL25:1; + uint32_t DSPIBL26:1; + uint32_t DSPIBL27:1; + uint32_t DSPIBL28:1; + uint32_t DSPIBL29:1; + uint32_t DSPIBL30:1; + uint32_t DSPIBL31:1; + } B; + } DSPIBHLB; + + int32_t SIU_reserved0D5C; /* 0x0D5C-0x0D5F */ + + union { /* ETPU A Select Register */ + uint32_t R; + struct { + uint32_t ETPUA12:1; + uint32_t ETPUA13:1; + uint32_t ETPUA14:1; + uint32_t ETPUA15:1; + uint32_t ETPUA0:1; + uint32_t ETPUA1:1; + uint32_t ETPUA2:1; + uint32_t ETPUA3:1; + uint32_t ETPUA4:1; + uint32_t ETPUA5:1; + uint32_t ETPUA6:1; + uint32_t ETPUA7:1; + uint32_t ETPUA8:1; + uint32_t ETPUA9:1; + uint32_t ETPUA10:1; + uint32_t ETPUA11:1; + uint32_t ETPUA23:1; + uint32_t ETPUA22:1; + uint32_t ETPUA21:1; + uint32_t ETPUA20:1; + uint32_t ETPUA19:1; + uint32_t ETPUA18:1; + uint32_t ETPUA17:1; + uint32_t ETPUA16:1; + uint32_t ETPUA29:1; + uint32_t ETPUA28:1; + uint32_t ETPUA27:1; + uint32_t ETPUA26:1; + uint32_t ETPUA25:1; + uint32_t ETPUA24:1; + uint32_t ETPUA31:1; + uint32_t ETPUA30:1; + } B ; + } ETPUAC; + + union { /* EMIOS C Select Register */ + uint32_t R; + struct { + uint32_t EMIOS12:1; + uint32_t EMIOS13:1; + uint32_t EMIOS14:1; + uint32_t EMIOS15:1; + uint32_t EMIOS23:1; + uint32_t EMIOS0:1; + uint32_t EMIOS1:1; + uint32_t EMIOS2:1; + uint32_t EMIOS3:1; + uint32_t EMIOS4:1; + uint32_t EMIOS5:1; + uint32_t EMIOS6:1; + uint32_t EMIOS8:1; + uint32_t EMIOS9:1; + uint32_t EMIOS10:1; + uint32_t EMIOS11:1; + uint32_t EMIOS23_23:1; + uint32_t EMIOS22:1; + uint32_t EMIOS21:1; + uint32_t EMIOS20:1; + uint32_t EMIOS19:1; + uint32_t EMIOS18:1; + uint32_t EMIOS17:1; + uint32_t EMIOS16:1; + uint32_t EMIOS29:1; + uint32_t EMIOS28:1; + uint32_t EMIOS27:1; + uint32_t EMIOS26:1; + uint32_t EMIOS25:1; + uint32_t EMIOS24:1; + uint32_t EMIOS31:1; + uint32_t EMIOS30:1; + } B; + } EMIOSC; + + union { /* DSPICH/L Select Register for DSPI C */ + uint32_t R; + struct { + uint32_t DSPICH0:1; + uint32_t DSPICH1:1; + uint32_t DSPICH2:1; + uint32_t DSPICH3:1; + uint32_t DSPICH4:1; + uint32_t DSPICH5:1; + uint32_t DSPICH6:1; + uint32_t DSPICH7:1; + uint32_t DSPICH8:1; + uint32_t DSPICH9:1; + uint32_t DSPICH10:1; + uint32_t DSPICH11:1; + uint32_t DSPICH12:1; + uint32_t DSPICH13:1; + uint32_t DSPICH14:1; + uint32_t DSPICH15:1; + uint32_t DSPICL16:1; + uint32_t DSPICL17:1; + uint32_t DSPICL18:1; + uint32_t DSPICL19:1; + uint32_t DSPICL20:1; + uint32_t DSPICL21:1; + uint32_t DSPICL22:1; + uint32_t DSPICL23:1; + uint32_t DSPICL24:1; + uint32_t DSPICL25:1; + uint32_t DSPICL26:1; + uint32_t DSPICL27:1; + uint32_t DSPICL28:1; + uint32_t DSPICL29:1; + uint32_t DSPICL30:1; + uint32_t DSPICL31:1; + } B; + } DSPICHLC; + + int32_t SIU_reserved0D6C; /* 0x0D6C-0x0D6F */ + + union { /* ETPU B Select Register */ + uint32_t R; + struct { + uint32_t ETPUB21:1; + uint32_t ETPUB20:1; + uint32_t ETPUB19:1; + uint32_t ETPUB18:1; + uint32_t ETPUB17:1; + uint32_t ETPUB16:1; + uint32_t:4; + uint32_t ETPUB29:1; + uint32_t ETPUB28:1; + uint32_t ETPUB27:1; + uint32_t ETPUB26:1; + uint32_t ETPUB25:1; + uint32_t ETPUB24:1; + uint32_t:16; + } B ; + } ETPUBD; + + union { /* EMIOS D Select Register */ + uint32_t R; + struct { + uint32_t:6; + uint32_t EMIOS11:1; + uint32_t EMIOS10:1; + uint32_t EMIOS13:1; + uint32_t EMIOS12:1; + uint32_t:22; + } B; + } EMIOSD; + + union { /* DSPIDH/L Select Register for DSPI D */ + uint32_t R; + struct { + uint32_t:32; + } B; + } DSPIDHLD; + + int32_t SIU_reserved0D7C; /* 0x0D7C-0x0D7F */ + + int32_t SIU_reserved0D80[32]; /* 0x0D80-0x0DFF */ + + union { /* GPIO Pin Data Input Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; + } B; + } GPDI0_511[512]; + + uint32_t SIU_reserved1000[3072]; /* 0x1000-0x3FFF */ + }; + +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + + struct EMIOS_tag { + + union EMIOS_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t GTBE:1; + uint32_t ETB:1; + uint32_t GPREN:1; + uint32_t:6; + uint32_t SRV:4; + uint32_t GPRE:8; + uint32_t:8; + } B; + } MCR; + + union { /* Global FLAG Register */ + uint32_t R; + struct { + uint32_t F31:1; + uint32_t F30:1; + uint32_t F29:1; + uint32_t F28:1; + uint32_t F27:1; + uint32_t F26:1; + uint32_t F25:1; + uint32_t F24:1; + uint32_t F23:1; + uint32_t F22:1; + uint32_t F21:1; + uint32_t F20:1; + uint32_t F19:1; + uint32_t F18:1; + uint32_t F17:1; + uint32_t F16:1; + uint32_t F15:1; + uint32_t F14:1; + uint32_t F13:1; + uint32_t F12:1; + uint32_t F11:1; + uint32_t F10:1; + uint32_t F9:1; + uint32_t F8:1; + uint32_t F7:1; + uint32_t F6:1; + uint32_t F5:1; + uint32_t F4:1; + uint32_t F3:1; + uint32_t F2:1; + uint32_t F1:1; + uint32_t F0:1; + } B; + } GFR; + + union { /* Output Update Disable Register */ + uint32_t R; + struct { + uint32_t OU31:1; + uint32_t OU30:1; + uint32_t OU29:1; + uint32_t OU28:1; + uint32_t OU27:1; + uint32_t OU26:1; + uint32_t OU25:1; + uint32_t OU24:1; + uint32_t OU23:1; + uint32_t OU22:1; + uint32_t OU21:1; + uint32_t OU20:1; + uint32_t OU19:1; + uint32_t OU18:1; + uint32_t OU17:1; + uint32_t OU16:1; + uint32_t OU15:1; + uint32_t OU14:1; + uint32_t OU13:1; + uint32_t OU12:1; + uint32_t OU11:1; + uint32_t OU10:1; + uint32_t OU9:1; + uint32_t OU8:1; + uint32_t OU7:1; + uint32_t OU6:1; + uint32_t OU5:1; + uint32_t OU4:1; + uint32_t OU3:1; + uint32_t OU2:1; + uint32_t OU1:1; + uint32_t OU0:1; + } B; + } OUDR; + + uint32_t eMIOS_reserved000C[5]; /* 0x000C-0x001F */ + + struct EMIOS_CH_tag { + union { /* Channel A Data Register */ + uint32_t R; + } CADR; + + union { /* Channel B Data Register */ + uint32_t R; + } CBDR; + + union { /* Channel Counter Register */ + uint32_t R; + } CCNTR; + + union EMIOS_CCR_tag {/* Channel Control Register */ + uint32_t R; + struct { + uint32_t FREN:1; + uint32_t ODIS:1; + uint32_t ODISSL:2; + uint32_t UCPRE:2; + uint32_t UCPREN:1; + uint32_t DMA:1; + uint32_t:1; + uint32_t IF:4; + uint32_t FCK:1; + uint32_t FEN:1; + uint32_t:3; + uint32_t FORCMA:1; + uint32_t FORCMB:1; + uint32_t:1; + uint32_t BSL:2; + uint32_t EDSEL:1; + uint32_t EDPOL:1; + uint32_t MODE:7; + } B; + } CCR; + + union EMIOS_CSR_tag {/* Channel Status Register */ + uint32_t R; + struct { + uint32_t OVR:1; + uint32_t:15; + uint32_t OVFL:1; + uint32_t:12; + uint32_t UCIN:1; + uint32_t UCOUT:1; + uint32_t FLAG:1; + } B; + } CSR; + + union { /* Alternate Channel A Data Register */ + uint32_t R; + } ALTA; + + uint32_t eMIOS_channel_reserved0018[2]; /* 0x0018-0x001F */ + + } CH[32]; + + uint32_t eMIOS_reserved0420[3832]; /* 0x0420-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : PMC */ +/****************************************************************************/ + + struct PMC_tag { + + union { + uint32_t R; + struct { + uint32_t LVRER:1; + uint32_t LVREH:1; + uint32_t LVRE50:1; + uint32_t LVRE33:1; + uint32_t LVREC:1; + uint32_t LVREA:1; + uint32_t:1; + uint32_t:1; + uint32_t LVIER:1; + uint32_t LVIEH:1; + uint32_t LVIE50:1; + uint32_t LVIE33:1; + uint32_t LVIEC:1; + uint32_t LVIEA:1; + uint32_t:1; + uint32_t TLK:1; + uint32_t:16; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t :8; + uint32_t LVDATRIM:4; + uint32_t LVDREGTRIM:4; + uint32_t VDD33TRIM:4; + uint32_t LVD33TRIM:4; + uint32_t VDDCTRIM:4; + uint32_t LVDCTRIM:4; + } B; + } TRIMR; /* Trimming register */ + + union { + uint32_t R; + struct { + uint32_t :5; + uint32_t LVFSTBY:1; + uint32_t BGRDY:1; + uint32_t BGTS:1; + uint32_t :5; + uint32_t LVFCSTBY:1; + uint32_t :2; + uint32_t LVFCR:1; + uint32_t LVFCH:1; + uint32_t LVFC50:1; + uint32_t LVFC33:1; + uint32_t LVFCC:1; + uint32_t LVFCA:1; + uint32_t :2; + uint32_t LVFR:1; + uint32_t LVFH:1; + uint32_t LVF50:1; + uint32_t LVF33:1; + uint32_t LVFC:1; + uint32_t LVFA:1; + uint32_t :2; + } B; + } SR; /* status register */ + + uint32_t PMC_reserved000C[4093]; /* 0x000C-0x3FFF */ + }; + +/****************************************************************************/ +/* MODULE :ETPU */ +/****************************************************************************/ + +/***************************Configuration Registers**************************/ + + struct ETPU_tag { + union { /* MODULE CONFIGURATION REGISTER */ + uint32_t R; + struct { + uint32_t GEC:1; /* Global Exception Clear */ + uint32_t SDMERR:1; /* SDM Read Error */ + uint32_t WDTOA:1; /* Watchdog Timeout-eTPU_A */ + uint32_t WDTOB:1; /* Watchdog Timeout-eTPU_B */ + uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */ + uint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */ + uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */ + uint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */ + uint32_t:3; + uint32_t SCMSIZE:5; /* Shared Code Memory size */ + uint32_t:4; + uint32_t SCMMISC:1; /* SCM MISC Complete/Clear */ + uint32_t SCMMISF:1; /* SCM MISC Flag */ + uint32_t SCMMISEN:1; /* SCM MISC Enable */ + uint32_t:2; + uint32_t VIS:1; /* SCM Visability */ + uint32_t:5; + uint32_t GTBE:1; /* Global Time Base Enable */ + } B; + } MCR; + + union { /* COHERENT DUAL-PARAMETER CONTROL */ + uint32_t R; + struct { + uint32_t STS:1; /* Start Status bit */ + uint32_t CTBASE:5; /* Channel Transfer Base */ + uint32_t PBASE:10; /* Parameter Buffer Base Address */ + uint32_t PWIDTH:1; /* Parameter Width */ + uint32_t PARAM0:7; /* Channel Parameter 0 */ + uint32_t WR:1; /* Read/Write selection */ + uint32_t PARAM1:7; /* Channel Parameter 1 */ + } B; + } CDCR; + + uint32_t eTPU_reserved0008; /* 0x0008-0x000B */ + + union { /* MISC Compare Register */ + uint32_t R; + struct { + uint32_t ETPUMISCCMP:32; + } B; + } MISCCMPR; + + union { /* SCM off-range Date Register */ + uint32_t R; + struct { + uint32_t ETPUSCMOFFDATA:32; + } B; + } SCMOFFDATAR; + + union { /* ETPU_A Configuration Register */ + uint32_t R; + struct { + uint32_t FEND:1; /* Force END */ + uint32_t MDIS:1; /* Low power Stop */ + uint32_t:1; + uint32_t STF:1; /* Stop Flag */ + uint32_t:4; + uint32_t HLTF:1; /* Halt Mode Flag */ + uint32_t:3; + uint32_t FCSS:1; /* Filter Clock Source Select */ + uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + uint32_t CDFC:2; + uint32_t:1; + uint32_t ERBA:5; /* Engine Relative Base Address */ + uint32_t SPPDIS:1; /* Schedule Priority Passing Disable */ + uint32_t:2; + uint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_A; + + union { /* ETPU_B Configuration Register */ + uint32_t R; + struct { + uint32_t FEND:1; /* Force END */ + uint32_t MDIS:1; /* Low power Stop */ + uint32_t:1; + uint32_t STF:1; /* Stop Flag */ + uint32_t:4; + uint32_t HLTF:1; /* Halt Mode Flag */ + uint32_t:3; + uint32_t FCSS:1; /* Filter Clock Source Select */ + uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + uint32_t CDFC:2; + uint32_t:1; + uint32_t ERBA:5; /* Engine Relative Base Address */ + uint32_t SPPDIS:1; /* Schedule Priority Passing Disable */ + uint32_t:2; + uint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_B; + + uint32_t eTPU_reserved001C; /* 0x001C-0x001F */ + + union { /* ETPU_A Timebase Configuration Register */ + uint32_t R; + struct { + uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + uint32_t AM:2; /* Angle Mode */ + uint32_t:3; + uint32_t TCR2P:6; /* TCR2 Prescaler Control */ + uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + uint32_t TCR1CS:1; /* TCR1 Clock Source */ + uint32_t:5; + uint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_A; + + union { /* ETPU_A TCR1 Visibility Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t TCR1:24; + } B; + } TB1R_A; + + union { /* ETPU_A TCR2 Visibility Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t TCR2:24; + } B; + } TB2R_A; + + union { /* ETPU_A STAC Configuration Register */ + uint32_t R; + struct { + uint32_t REN1:1; /* Resource Enable TCR1 */ + uint32_t RSC1:1; /* Resource Control TCR1 */ + uint32_t:2; + uint32_t SERVER_ID1:4; /* TCR1 Server ID */ + uint32_t:4; + uint32_t SRV1:4; /* Resource Server Slot */ + uint32_t REN2:1; /* Resource Enable TCR2 */ + uint32_t RSC2:1; /* Resource Control TCR2 */ + uint32_t:2; + uint32_t SERVER_ID2:4; /* TCR2 Server ID */ + uint32_t:4; + uint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_A; + + uint32_t eTPU_reserved0030[4]; /* 0x0030-0x003F */ + + union { /* ETPU_B Timebase Configuration Register */ + uint32_t R; + struct { + uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + uint32_t AM:2; /* Angle Mode */ + uint32_t:3; + uint32_t TCR2P:6; /* TCR2 Prescaler Control */ + uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + uint32_t TCR1CS:1; /* TCR1 Clock Source */ + uint32_t:5; + uint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_B; + + union { /* ETPU_B TCR1 Visibility Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t TCR1:24; + } B; + } TB1R_B; + + union { /* ETPU_B TCR2 Visibility Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t TCR2:24; + } B; + } TB2R_B; + + union { /* ETPU_B STAC Configuration Register */ + uint32_t R; + struct { + uint32_t REN1:1; /* Resource Enable TCR1 */ + uint32_t RSC1:1; /* Resource Control TCR1 */ + uint32_t:2; + uint32_t SERVER_ID1:4; /* TCR1 Server ID */ + uint32_t:4; + uint32_t SRV1:4; /* Resource Server Slot */ + uint32_t REN2:1; /* Resource Enable TCR2 */ + uint32_t RSC2:1; /* Resource Control TCR2 */ + uint32_t:2; + uint32_t SERVER_ID2:4; /* TCR2 Server ID */ + uint32_t:4; + uint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_B; + + uint32_t eTPU_reserved0050[4]; /* 0x0050-0x005F */ + + union { /* Watchdog Timer Register A */ + uint32_t R; + struct { + uint32_t WDM:2; /* Watchdog Mode */ + uint32_t:14; + uint32_t WDCNT:16; /* Watchdog Count */ + } B; + } WDTR_A; + + uint32_t eTPU_reserved0064; /* 0x0064-0x0067 */ + + union { /* Idle Counter Register A*/ + uint32_t R; + struct { + uint32_t IDLE_CNT:31; + uint32_t ICLR:1; /* Idle Clear */ + } B; + + } IDLE_A; + + uint32_t eTPU_reserved006C; /* 0x006C-0x006F */ + + union { /* Watchdog Timer Register B */ + uint32_t R; + struct { + uint32_t WDM:2; /* Watchdog Mode */ + uint32_t:14; + uint32_t WDCNT:16; /* Watchdog Count */ + } B; + } WDTR_B; + + uint32_t eTPU_reserved0074; /* 0x0074-0x0077 */ + + union { /* Idle Counter Register B*/ + uint32_t R; + struct { + uint32_t IDLE_CNT:31; + uint32_t ICLR:1; /* Idle Clear */ + } B; + } IDLE_B; + + uint32_t eTPU_reserved007C; /* 0x007C-0x007F */ + + uint32_t eTPU_reserved0080[96]; /* 0x0080-0x01FF */ + +/*****************************Status and Control Registers**************************/ + + union { /* ETPU_A Channel Interrut Status */ + uint32_t R; + struct { + uint32_t CIS31:1; /* Channel 31 Interrut Status */ + uint32_t CIS30:1; /* Channel 30 Interrut Status */ + uint32_t CIS29:1; /* Channel 29 Interrut Status */ + uint32_t CIS28:1; /* Channel 28 Interrut Status */ + uint32_t CIS27:1; /* Channel 27 Interrut Status */ + uint32_t CIS26:1; /* Channel 26 Interrut Status */ + uint32_t CIS25:1; /* Channel 25 Interrut Status */ + uint32_t CIS24:1; /* Channel 24 Interrut Status */ + uint32_t CIS23:1; /* Channel 23 Interrut Status */ + uint32_t CIS22:1; /* Channel 22 Interrut Status */ + uint32_t CIS21:1; /* Channel 21 Interrut Status */ + uint32_t CIS20:1; /* Channel 20 Interrut Status */ + uint32_t CIS19:1; /* Channel 19 Interrut Status */ + uint32_t CIS18:1; /* Channel 18 Interrut Status */ + uint32_t CIS17:1; /* Channel 17 Interrut Status */ + uint32_t CIS16:1; /* Channel 16 Interrut Status */ + uint32_t CIS15:1; /* Channel 15 Interrut Status */ + uint32_t CIS14:1; /* Channel 14 Interrut Status */ + uint32_t CIS13:1; /* Channel 13 Interrut Status */ + uint32_t CIS12:1; /* Channel 12 Interrut Status */ + uint32_t CIS11:1; /* Channel 11 Interrut Status */ + uint32_t CIS10:1; /* Channel 10 Interrut Status */ + uint32_t CIS9:1; /* Channel 9 Interrut Status */ + uint32_t CIS8:1; /* Channel 8 Interrut Status */ + uint32_t CIS7:1; /* Channel 7 Interrut Status */ + uint32_t CIS6:1; /* Channel 6 Interrut Status */ + uint32_t CIS5:1; /* Channel 5 Interrut Status */ + uint32_t CIS4:1; /* Channel 4 Interrut Status */ + uint32_t CIS3:1; /* Channel 3 Interrut Status */ + uint32_t CIS2:1; /* Channel 2 Interrut Status */ + uint32_t CIS1:1; /* Channel 1 Interrut Status */ + uint32_t CIS0:1; /* Channel 0 Interrut Status */ + } B; + } CISR_A; + + union { /* ETPU_B Channel Interruput Status */ + uint32_t R; + struct { + uint32_t CIS31:1; /* Channel 31 Interrut Status */ + uint32_t CIS30:1; /* Channel 30 Interrut Status */ + uint32_t CIS29:1; /* Channel 29 Interrut Status */ + uint32_t CIS28:1; /* Channel 28 Interrut Status */ + uint32_t CIS27:1; /* Channel 27 Interrut Status */ + uint32_t CIS26:1; /* Channel 26 Interrut Status */ + uint32_t CIS25:1; /* Channel 25 Interrut Status */ + uint32_t CIS24:1; /* Channel 24 Interrut Status */ + uint32_t CIS23:1; /* Channel 23 Interrut Status */ + uint32_t CIS22:1; /* Channel 22 Interrut Status */ + uint32_t CIS21:1; /* Channel 21 Interrut Status */ + uint32_t CIS20:1; /* Channel 20 Interrut Status */ + uint32_t CIS19:1; /* Channel 19 Interrut Status */ + uint32_t CIS18:1; /* Channel 18 Interrut Status */ + uint32_t CIS17:1; /* Channel 17 Interrut Status */ + uint32_t CIS16:1; /* Channel 16 Interrut Status */ + uint32_t CIS15:1; /* Channel 15 Interrut Status */ + uint32_t CIS14:1; /* Channel 14 Interrut Status */ + uint32_t CIS13:1; /* Channel 13 Interrut Status */ + uint32_t CIS12:1; /* Channel 12 Interrut Status */ + uint32_t CIS11:1; /* Channel 11 Interrut Status */ + uint32_t CIS10:1; /* Channel 10 Interrut Status */ + uint32_t CIS9:1; /* Channel 9 Interrut Status */ + uint32_t CIS8:1; /* Channel 8 Interrut Status */ + uint32_t CIS7:1; /* Channel 7 Interrut Status */ + uint32_t CIS6:1; /* Channel 6 Interrut Status */ + uint32_t CIS5:1; /* Channel 5 Interrut Status */ + uint32_t CIS4:1; /* Channel 4 Interrut Status */ + uint32_t CIS3:1; /* Channel 3 Interrut Status */ + uint32_t CIS2:1; /* Channel 2 Interrut Status */ + uint32_t CIS1:1; /* Channel 1 Interrupt Status */ + uint32_t CIS0:1; /* Channel 0 Interrupt Status */ + } B; + } CISR_B; + + uint32_t eTPU_reserved0208[2]; /* 0x0208-0x020F */ + + union { /* ETPU_A Data Transfer Request Status */ + uint32_t R; + struct { + uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_A; + + union { /* ETPU_B Data Transfer Request Status */ + uint32_t R; + struct { + uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_B; + + uint32_t eTPU_reserved0218[2]; /* 0x0218-0x021F */ + + union { /* ETPU_A Interruput Overflow Status */ + uint32_t R; + struct { + uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_A; + + union { /* ETPU_B Interruput Overflow Status */ + uint32_t R; + struct { + uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_B; + + uint32_t eTPU_reserved0228[2]; /* 0x0228-0x022F */ + + union { /* ETPU_A Data Transfer Overflow Status */ + uint32_t R; + struct { + uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_A; + + union { /* ETPU_B Data Transfer Overflow Status */ + uint32_t R; + struct { + uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_B; + + uint32_t eTPU_reserved0238[2]; /* 0x0238-0x023F */ + + union { /* ETPU_A Channel Interruput Enable */ + uint32_t R; + struct { + uint32_t CIE31:1; /* Channel 31 Interruput Enable */ + uint32_t CIE30:1; /* Channel 30 Interruput Enable */ + uint32_t CIE29:1; /* Channel 29 Interruput Enable */ + uint32_t CIE28:1; /* Channel 28 Interruput Enable */ + uint32_t CIE27:1; /* Channel 27 Interruput Enable */ + uint32_t CIE26:1; /* Channel 26 Interruput Enable */ + uint32_t CIE25:1; /* Channel 25 Interruput Enable */ + uint32_t CIE24:1; /* Channel 24 Interruput Enable */ + uint32_t CIE23:1; /* Channel 23 Interruput Enable */ + uint32_t CIE22:1; /* Channel 22 Interruput Enable */ + uint32_t CIE21:1; /* Channel 21 Interruput Enable */ + uint32_t CIE20:1; /* Channel 20 Interruput Enable */ + uint32_t CIE19:1; /* Channel 19 Interruput Enable */ + uint32_t CIE18:1; /* Channel 18 Interruput Enable */ + uint32_t CIE17:1; /* Channel 17 Interruput Enable */ + uint32_t CIE16:1; /* Channel 16 Interruput Enable */ + uint32_t CIE15:1; /* Channel 15 Interruput Enable */ + uint32_t CIE14:1; /* Channel 14 Interruput Enable */ + uint32_t CIE13:1; /* Channel 13 Interruput Enable */ + uint32_t CIE12:1; /* Channel 12 Interruput Enable */ + uint32_t CIE11:1; /* Channel 11 Interruput Enable */ + uint32_t CIE10:1; /* Channel 10 Interruput Enable */ + uint32_t CIE9:1; /* Channel 9 Interruput Enable */ + uint32_t CIE8:1; /* Channel 8 Interruput Enable */ + uint32_t CIE7:1; /* Channel 7 Interruput Enable */ + uint32_t CIE6:1; /* Channel 6 Interruput Enable */ + uint32_t CIE5:1; /* Channel 5 Interruput Enable */ + uint32_t CIE4:1; /* Channel 4 Interruput Enable */ + uint32_t CIE3:1; /* Channel 3 Interruput Enable */ + uint32_t CIE2:1; /* Channel 2 Interruput Enable */ + uint32_t CIE1:1; /* Channel 1 Interruput Enable */ + uint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_A; + + union { /* ETPU_B Channel Interruput Enable */ + uint32_t R; + struct { + uint32_t CIE31:1; /* Channel 31 Interruput Enable */ + uint32_t CIE30:1; /* Channel 30 Interruput Enable */ + uint32_t CIE29:1; /* Channel 29 Interruput Enable */ + uint32_t CIE28:1; /* Channel 28 Interruput Enable */ + uint32_t CIE27:1; /* Channel 27 Interruput Enable */ + uint32_t CIE26:1; /* Channel 26 Interruput Enable */ + uint32_t CIE25:1; /* Channel 25 Interruput Enable */ + uint32_t CIE24:1; /* Channel 24 Interruput Enable */ + uint32_t CIE23:1; /* Channel 23 Interruput Enable */ + uint32_t CIE22:1; /* Channel 22 Interruput Enable */ + uint32_t CIE21:1; /* Channel 21 Interruput Enable */ + uint32_t CIE20:1; /* Channel 20 Interruput Enable */ + uint32_t CIE19:1; /* Channel 19 Interruput Enable */ + uint32_t CIE18:1; /* Channel 18 Interruput Enable */ + uint32_t CIE17:1; /* Channel 17 Interruput Enable */ + uint32_t CIE16:1; /* Channel 16 Interruput Enable */ + uint32_t CIE15:1; /* Channel 15 Interruput Enable */ + uint32_t CIE14:1; /* Channel 14 Interruput Enable */ + uint32_t CIE13:1; /* Channel 13 Interruput Enable */ + uint32_t CIE12:1; /* Channel 12 Interruput Enable */ + uint32_t CIE11:1; /* Channel 11 Interruput Enable */ + uint32_t CIE10:1; /* Channel 10 Interruput Enable */ + uint32_t CIE9:1; /* Channel 9 Interruput Enable */ + uint32_t CIE8:1; /* Channel 8 Interruput Enable */ + uint32_t CIE7:1; /* Channel 7 Interruput Enable */ + uint32_t CIE6:1; /* Channel 6 Interruput Enable */ + uint32_t CIE5:1; /* Channel 5 Interruput Enable */ + uint32_t CIE4:1; /* Channel 4 Interruput Enable */ + uint32_t CIE3:1; /* Channel 3 Interruput Enable */ + uint32_t CIE2:1; /* Channel 2 Interruput Enable */ + uint32_t CIE1:1; /* Channel 1 Interruput Enable */ + uint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_B; + + uint32_t eTPU_reserved0248[2]; /* 0x0248-0x024F */ + + union { /* ETPU_A Channel Data Transfer Request Enable */ + uint32_t R; + struct { + uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_A; + + union { /* ETPU_B Channel Data Transfer Request Enable */ + uint32_t R; + struct { + uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_B; + + uint32_t eTPU_reserved0258[2]; /* 0x0258-0x025F */ + + union { /* Watchdog Status Register A */ + uint32_t R; + struct { + uint32_t WDS31:1; + uint32_t WDS30:1; + uint32_t WDS29:1; + uint32_t WDS28:1; + uint32_t WDS27:1; + uint32_t WDS26:1; + uint32_t WDS25:1; + uint32_t WDS24:1; + uint32_t WDS23:1; + uint32_t WDS22:1; + uint32_t WDS21:1; + uint32_t WDS20:1; + uint32_t WDS19:1; + uint32_t WDS18:1; + uint32_t WDS17:1; + uint32_t WDS16:1; + uint32_t WDS15:1; + uint32_t WDS14:1; + uint32_t WDS13:1; + uint32_t WDS12:1; + uint32_t WDS11:1; + uint32_t WDS10:1; + uint32_t WDS9:1; + uint32_t WDS8:1; + uint32_t WDS7:1; + uint32_t WDS6:1; + uint32_t WDS5:1; + uint32_t WDS4:1; + uint32_t WDS3:1; + uint32_t WDS2:1; + uint32_t WDS1:1; + uint32_t WDS0:1; + } B; + } WDSR_A; + + union { /* Watchdog Status Register B */ + uint32_t R; + struct { + uint32_t WDS31:1; + uint32_t WDS30:1; + uint32_t WDS29:1; + uint32_t WDS28:1; + uint32_t WDS27:1; + uint32_t WDS26:1; + uint32_t WDS25:1; + uint32_t WDS24:1; + uint32_t WDS23:1; + uint32_t WDS22:1; + uint32_t WDS21:1; + uint32_t WDS20:1; + uint32_t WDS19:1; + uint32_t WDS18:1; + uint32_t WDS17:1; + uint32_t WDS16:1; + uint32_t WDS15:1; + uint32_t WDS14:1; + uint32_t WDS13:1; + uint32_t WDS12:1; + uint32_t WDS11:1; + uint32_t WDS10:1; + uint32_t WDS9:1; + uint32_t WDS8:1; + uint32_t WDS7:1; + uint32_t WDS6:1; + uint32_t WDS5:1; + uint32_t WDS4:1; + uint32_t WDS3:1; + uint32_t WDS2:1; + uint32_t WDS1:1; + uint32_t WDS0:1; + } B; + } WDSR_B; + + uint32_t eTPU_reserved0268[6]; /* 0x0268-0x027F */ + + union { /* ETPU_A Channel Pending Service Status */ + uint32_t R; + struct { + uint32_t SR31:1; /* Channel 31 Pending Service Status */ + uint32_t SR30:1; /* Channel 30 Pending Service Status */ + uint32_t SR29:1; /* Channel 29 Pending Service Status */ + uint32_t SR28:1; /* Channel 28 Pending Service Status */ + uint32_t SR27:1; /* Channel 27 Pending Service Status */ + uint32_t SR26:1; /* Channel 26 Pending Service Status */ + uint32_t SR25:1; /* Channel 25 Pending Service Status */ + uint32_t SR24:1; /* Channel 24 Pending Service Status */ + uint32_t SR23:1; /* Channel 23 Pending Service Status */ + uint32_t SR22:1; /* Channel 22 Pending Service Status */ + uint32_t SR21:1; /* Channel 21 Pending Service Status */ + uint32_t SR20:1; /* Channel 20 Pending Service Status */ + uint32_t SR19:1; /* Channel 19 Pending Service Status */ + uint32_t SR18:1; /* Channel 18 Pending Service Status */ + uint32_t SR17:1; /* Channel 17 Pending Service Status */ + uint32_t SR16:1; /* Channel 16 Pending Service Status */ + uint32_t SR15:1; /* Channel 15 Pending Service Status */ + uint32_t SR14:1; /* Channel 14 Pending Service Status */ + uint32_t SR13:1; /* Channel 13 Pending Service Status */ + uint32_t SR12:1; /* Channel 12 Pending Service Status */ + uint32_t SR11:1; /* Channel 11 Pending Service Status */ + uint32_t SR10:1; /* Channel 10 Pending Service Status */ + uint32_t SR9:1; /* Channel 9 Pending Service Status */ + uint32_t SR8:1; /* Channel 8 Pending Service Status */ + uint32_t SR7:1; /* Channel 7 Pending Service Status */ + uint32_t SR6:1; /* Channel 6 Pending Service Status */ + uint32_t SR5:1; /* Channel 5 Pending Service Status */ + uint32_t SR4:1; /* Channel 4 Pending Service Status */ + uint32_t SR3:1; /* Channel 3 Pending Service Status */ + uint32_t SR2:1; /* Channel 2 Pending Service Status */ + uint32_t SR1:1; /* Channel 1 Pending Service Status */ + uint32_t SR0:1; /* Channel 0 Pending Service Status */ + } B; + } CPSSR_A; + + union { /* ETPU_B Channel Pending Service Status */ + uint32_t R; + struct { + uint32_t SR31:1; /* Channel 31 Pending Service Status */ + uint32_t SR30:1; /* Channel 30 Pending Service Status */ + uint32_t SR29:1; /* Channel 29 Pending Service Status */ + uint32_t SR28:1; /* Channel 28 Pending Service Status */ + uint32_t SR27:1; /* Channel 27 Pending Service Status */ + uint32_t SR26:1; /* Channel 26 Pending Service Status */ + uint32_t SR25:1; /* Channel 25 Pending Service Status */ + uint32_t SR24:1; /* Channel 24 Pending Service Status */ + uint32_t SR23:1; /* Channel 23 Pending Service Status */ + uint32_t SR22:1; /* Channel 22 Pending Service Status */ + uint32_t SR21:1; /* Channel 21 Pending Service Status */ + uint32_t SR20:1; /* Channel 20 Pending Service Status */ + uint32_t SR19:1; /* Channel 19 Pending Service Status */ + uint32_t SR18:1; /* Channel 18 Pending Service Status */ + uint32_t SR17:1; /* Channel 17 Pending Service Status */ + uint32_t SR16:1; /* Channel 16 Pending Service Status */ + uint32_t SR15:1; /* Channel 15 Pending Service Status */ + uint32_t SR14:1; /* Channel 14 Pending Service Status */ + uint32_t SR13:1; /* Channel 13 Pending Service Status */ + uint32_t SR12:1; /* Channel 12 Pending Service Status */ + uint32_t SR11:1; /* Channel 11 Pending Service Status */ + uint32_t SR10:1; /* Channel 10 Pending Service Status */ + uint32_t SR9:1; /* Channel 9 Pending Service Status */ + uint32_t SR8:1; /* Channel 8 Pending Service Status */ + uint32_t SR7:1; /* Channel 7 Pending Service Status */ + uint32_t SR6:1; /* Channel 6 Pending Service Status */ + uint32_t SR5:1; /* Channel 5 Pending Service Status */ + uint32_t SR4:1; /* Channel 4 Pending Service Status */ + uint32_t SR3:1; /* Channel 3 Pending Service Status */ + uint32_t SR2:1; /* Channel 2 Pending Service Status */ + uint32_t SR1:1; /* Channel 1 Pending Service Status */ + uint32_t SR0:1; /* Channel 0 Pending Service Status */ + } B; + } CPSSR_B; + + uint32_t eTPU_reserved0288[2]; /* 0x0288-0x028F */ + + union { /* ETPU_A Channel Service Status */ + uint32_t R; + struct { + uint32_t SS31:1; /* Channel 31 Service Status */ + uint32_t SS30:1; /* Channel 30 Service Status */ + uint32_t SS29:1; /* Channel 29 Service Status */ + uint32_t SS28:1; /* Channel 28 Service Status */ + uint32_t SS27:1; /* Channel 27 Service Status */ + uint32_t SS26:1; /* Channel 26 Service Status */ + uint32_t SS25:1; /* Channel 25 Service Status */ + uint32_t SS24:1; /* Channel 24 Service Status */ + uint32_t SS23:1; /* Channel 23 Service Status */ + uint32_t SS22:1; /* Channel 22 Service Status */ + uint32_t SS21:1; /* Channel 21 Service Status */ + uint32_t SS20:1; /* Channel 20 Service Status */ + uint32_t SS19:1; /* Channel 19 Service Status */ + uint32_t SS18:1; /* Channel 18 Service Status */ + uint32_t SS17:1; /* Channel 17 Service Status */ + uint32_t SS16:1; /* Channel 16 Service Status */ + uint32_t SS15:1; /* Channel 15 Service Status */ + uint32_t SS14:1; /* Channel 14 Service Status */ + uint32_t SS13:1; /* Channel 13 Service Status */ + uint32_t SS12:1; /* Channel 12 Service Status */ + uint32_t SS11:1; /* Channel 11 Service Status */ + uint32_t SS10:1; /* Channel 10 Service Status */ + uint32_t SS9:1; /* Channel 9 Service Status */ + uint32_t SS8:1; /* Channel 8 Service Status */ + uint32_t SS7:1; /* Channel 7 Service Status */ + uint32_t SS6:1; /* Channel 6 Service Status */ + uint32_t SS5:1; /* Channel 5 Service Status */ + uint32_t SS4:1; /* Channel 4 Service Status */ + uint32_t SS3:1; /* Channel 3 Service Status */ + uint32_t SS2:1; /* Channel 2 Service Status */ + uint32_t SS1:1; /* Channel 1 Service Status */ + uint32_t SS0:1; /* Channel 0 Service Status */ + } B; + } CSSR_A; + + union { /* ETPU_B Channel Service Status */ + uint32_t R; + struct { + uint32_t SS31:1; /* Channel 31 Service Status */ + uint32_t SS30:1; /* Channel 30 Service Status */ + uint32_t SS29:1; /* Channel 29 Service Status */ + uint32_t SS28:1; /* Channel 28 Service Status */ + uint32_t SS27:1; /* Channel 27 Service Status */ + uint32_t SS26:1; /* Channel 26 Service Status */ + uint32_t SS25:1; /* Channel 25 Service Status */ + uint32_t SS24:1; /* Channel 24 Service Status */ + uint32_t SS23:1; /* Channel 23 Service Status */ + uint32_t SS22:1; /* Channel 22 Service Status */ + uint32_t SS21:1; /* Channel 21 Service Status */ + uint32_t SS20:1; /* Channel 20 Service Status */ + uint32_t SS19:1; /* Channel 19 Service Status */ + uint32_t SS18:1; /* Channel 18 Service Status */ + uint32_t SS17:1; /* Channel 17 Service Status */ + uint32_t SS16:1; /* Channel 16 Service Status */ + uint32_t SS15:1; /* Channel 15 Service Status */ + uint32_t SS14:1; /* Channel 14 Service Status */ + uint32_t SS13:1; /* Channel 13 Service Status */ + uint32_t SS12:1; /* Channel 12 Service Status */ + uint32_t SS11:1; /* Channel 11 Service Status */ + uint32_t SS10:1; /* Channel 10 Service Status */ + uint32_t SS9:1; /* Channel 9 Service Status */ + uint32_t SS8:1; /* Channel 8 Service Status */ + uint32_t SS7:1; /* Channel 7 Service Status */ + uint32_t SS6:1; /* Channel 6 Service Status */ + uint32_t SS5:1; /* Channel 5 Service Status */ + uint32_t SS4:1; /* Channel 4 Service Status */ + uint32_t SS3:1; /* Channel 3 Service Status */ + uint32_t SS2:1; /* Channel 2 Service Status */ + uint32_t SS1:1; /* Channel 1 Service Status */ + uint32_t SS0:1; /* Channel 0 Service Status */ + } B; + } CSSR_B; + + uint32_t eTPU_reserved0298[2]; /* 0x0298-0x029F */ + + uint32_t eTPU_reserved02A0[88]; /* 0x02A0-0x03FF */ + +/*****************************Channels********************************/ + + struct { + union { /* Channel Configuration Register */ + uint32_t R; + struct { + uint32_t CIE:1; /* Channel Interruput Enable */ + uint32_t DTRE:1; /* Data Transfer Request Enable */ + uint32_t CPR:2; /* Channel Priority */ + uint32_t:2; + uint32_t ETPD:1; + uint32_t ETCS:1; /* Entry Table Condition Select */ + uint32_t:3; + uint32_t CFS:5; /* Channel Function Select */ + uint32_t ODIS:1; /* Output disable */ + uint32_t OPOL:1; /* output polarity */ + uint32_t:3; + uint32_t CPBA:11; /* Channel Parameter Base Address */ + } B; + } CR; + + union { /* Channel Status Control Register */ + uint32_t R; + struct { + uint32_t CIS:1; /* Channel Interruput Status */ + uint32_t CIOS:1; /* Channel Interruput Overflow Status */ + uint32_t:6; + uint32_t DTRS:1; /* Data Transfer Status */ + uint32_t DTROS:1; /* Data Transfer Overflow Status */ + uint32_t:6; + uint32_t IPS:1; /* Input Pin State */ + uint32_t OPS:1; /* Output Pin State */ + uint32_t OBE:1; /* Output Buffer Enable */ + uint32_t:11; + uint32_t FM1:1; /* Function mode */ + uint32_t FM0:1; /* Function mode */ + } B; + } SCR; + + union { /* Channel Host Service Request Register */ + uint32_t R; + struct { + uint32_t:29; /* Host Service Request */ + uint32_t HSR:3; + } B; + } HSRR; + + uint32_t eTPU_ch_reserved00C; /* channel offset 0x00C-0x00F */ + + } CHAN[127]; + + uint32_t eTPU_reserved1000[7168]; /* 0x1000-0x7FFF */ + + }; + +/****************************************************************************/ +/* MODULE : PIT / RTI */ +/****************************************************************************/ + + struct PIT_tag { + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:29; + uint32_t MDIS_RTI:1; + uint32_t MDIS:1; + uint32_t FRZ:1; + } B; + } MCR; + + uint32_t PIT_reserved0004[59]; /* 0x0004-0x00EF */ + + struct { + union { + uint32_t R; /* TSVn */ + } LDVAL; /* Timer Load Value Register */ + + union { + uint32_t R; /* TVLn */ + } CVAL; /* Current Timer Value Register */ + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t TIE:1; + uint32_t TEN:1; + } B; + } TCTRL; /* Timer Control Register */ + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t TIF:1; + } B; + } TFLG; /* Timer Flag Register */ + } RTI; /* RTI Channel */ + + struct { + union { + uint32_t R; + struct { + uint32_t TSV:32; + } B; + } LDVAL; + + union { + uint32_t R; + struct { + uint32_t TVL:32; + } B; + } CVAL; + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t TIE:1; + uint32_t TEN:1; + } B; + } TCTRL; + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t TIF:1; + } B; + } TFLG; + } CH[4]; + + uint32_t PIT_reserved00140[4016]; /* 0x0140-0x3FFF */ + }; + +/****************************************************************************/ +/* MODULE : XBAR CrossBar */ +/****************************************************************************/ + + struct XBAR_tag { + + union { /* Master Priority Register for Slave Port 0 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; /* EBI (development bus) */ + uint32_t:1; + uint32_t MSTR6:3; /* FlexRay */ + uint32_t:1; + uint32_t MSTR5:3; /* eDMA_B */ + uint32_t:1; + uint32_t MSTR4:3; /* eDMA_A */ + uint32_t:1; + uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ + uint32_t:1; + uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ + uint32_t:1; + uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ + uint32_t:1; + uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ + } B; + } MPR0; + + uint32_t XBAR_reserved0004[3]; /* 0x0004-0x000F */ + + union { /* General Purpose Control Register for Slave Port 0 */ + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR0; + + uint32_t XBAR_reserved0014[59]; /* 0x0014-0x00FF */ + + union { /* Master Priority Register for Slave Port 1 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; /* EBI (development bus) */ + uint32_t:1; + uint32_t MSTR6:3; /* FlexRay */ + uint32_t:1; + uint32_t MSTR5:3; /* eDMA_B */ + uint32_t:1; + uint32_t MSTR4:3; /* eDMA_A */ + uint32_t:1; + uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ + uint32_t:1; + uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ + uint32_t:1; + uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ + uint32_t:1; + uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ + } B; + } MPR1; + + uint32_t XBAR_reserved0104[3]; /* 0x0104-0x010F */ + + union { /* General Purpose Control Register for Slave Port 1 */ + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR1; + + uint32_t XBAR_reserved0114[59]; /* 0x0114-0x01FF */ + + union { /* Master Priority Register for Slave Port 2 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; /* EBI (development bus) */ + uint32_t:1; + uint32_t MSTR6:3; /* FlexRay */ + uint32_t:1; + uint32_t MSTR5:3; /* eDMA_B */ + uint32_t:1; + uint32_t MSTR4:3; /* eDMA_A */ + uint32_t:1; + uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ + uint32_t:1; + uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ + uint32_t:1; + uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ + uint32_t:1; + uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ + } B; + } MPR2; + + uint32_t XBAR_reserved0204[3]; /* 0x0204-0x020F */ + + union { /* General Purpose Control Register for Slave Port 2 */ + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR2; + + uint32_t XBAR_reserved0214[59]; /* 0x0214-0x02FF */ + + uint32_t XBAR_reserved0300[64]; /* 0x0300-0x03FF */ + + uint32_t XBAR_reserved0400[64]; /* 0x0400-0x04FF */ + + uint32_t XBAR_reserved0500[64]; /* 0x0500-0x05FF */ + + union { /* Master Priority Register for Slave Port 6 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; /* EBI (development bus) */ + uint32_t:1; + uint32_t MSTR6:3; /* FlexRay */ + uint32_t:1; + uint32_t MSTR5:3; /* eDMA_B */ + uint32_t:1; + uint32_t MSTR4:3; /* eDMA_A */ + uint32_t:1; + uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ + uint32_t:1; + uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ + uint32_t:1; + uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ + uint32_t:1; + uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ + } B; + } MPR6; + + uint32_t XBAR_reserved604[3]; /* 0x0604-0x060F */ + + union { /* General Purpose Control Register for Slave Port 6 */ + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR6; + + uint32_t XBAR_reserved0614[59]; /* 0x0614-0x06FF */ + + union { /* Master Priority Register for Slave Port 7 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; /* EBI (development bus) */ + uint32_t:1; + uint32_t MSTR6:3; /* FlexRay */ + uint32_t:1; + uint32_t MSTR5:3; /* eDMA_B */ + uint32_t:1; + uint32_t MSTR4:3; /* eDMA_A */ + uint32_t:1; + uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ + uint32_t:1; + uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ + uint32_t:1; + uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ + uint32_t:1; + uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ + } B; + } MPR7; + + uint32_t XBAR_reserved704[3]; /* 0x0704-0x070F */ + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR7; /* General Purpose Control Register for Slave Port 7 */ + + uint32_t XBAR_reserved0714[59]; /* 0x0714-0x07FF */ + + uint32_t XBAR_reserved0800[3584]; /* 0x0800-0x3FFF */ + }; + +/****************************************************************************/ +/* MODULE : MPU */ +/****************************************************************************/ + + struct MPU_tag { + + union { /* Module Control/Error Status Register */ + uint32_t R; + struct { + uint32_t SPERR:8; + uint32_t:4; + uint32_t HRL:4; + uint32_t NSP:4; + uint32_t NRGD:4; + uint32_t:7; + uint32_t VLD:1; + } B; + } CESR; + + uint32_t MPU_reserved0004[3]; /* 0x0004-0x000F */ + + struct { + union { /* MPU Error Address Registers */ + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR; + + union { /* MPU Error Detail Registers */ + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR; + } PORT[3]; + + uint32_t MPU_reserved0028[246]; /* 0x0028-0x03FF */ + + struct { + union { /* Region Descriptor n Word 0 */ + uint32_t R; + struct { + uint32_t SRTADDR:27; + uint32_t:5; + } B; + } WORD0; + + union { /* Region Descriptor n Word 1 */ + uint32_t R; + struct { + uint32_t ENDADDR:27; + uint32_t:5; + } B; + } WORD1; + + union { /* Region Descriptor n Word 2 */ + uint32_t R; + struct { + uint32_t M7RE:1; + uint32_t M7WE:1; + uint32_t M6RE:1; + uint32_t M6WE:1; + uint32_t M5RE:1; + uint32_t M5WE:1; + uint32_t M4RE:1; + uint32_t M4WE:1; + uint32_t: 18; + uint32_t M0PE:1; + uint32_t M0SM:2; + uint32_t M0UM:3; + } B; + } WORD2; + + union { /* Region Descriptor n Word 3 */ + uint32_t R; + struct { + uint32_t PID:8; + uint32_t PIDMASK:8; + uint32_t:15; + uint32_t VLD:1; + } B; + } WORD3; + } RGD[16]; + + uint32_t MPU_reserved0500[192]; /* 0x0500-0x07FF */ + + union { /* Region Descriptor Alternate Access Control n */ + uint32_t R; + struct { + uint32_t:6; + uint32_t M4RE:1; + uint32_t M4WE:1; + uint32_t M3PE:1; + uint32_t M3SM:2; + uint32_t M3UM:3; + uint32_t M2PE:1; + uint32_t M2SM:2; + uint32_t M2UM:3; + uint32_t M1PE:1; + uint32_t M1SM:2; + uint32_t M1UM:3; + uint32_t M0PE:1; + uint32_t M0SM:2; + uint32_t M0UM:3; + } B; + } RGDAAC[16]; + + uint32_t MPU_reserved0840[3568]; /* 0x0840-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : SWT */ +/****************************************************************************/ + + struct SWT_tag { + + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t MAP0:1; + uint32_t MAP1:1; + uint32_t:1; + uint32_t:1; + uint32_t MAP4:1; + uint32_t MAP5:1; + uint32_t MAP6:1; + uint32_t MAP7:1; + uint32_t:14; + uint32_t KEY:1; + uint32_t RIA:1; + uint32_t WND:1; + uint32_t ITR:1; + uint32_t HLK:1; + uint32_t SLK:1; + uint32_t CSL:1; + uint32_t STP:1; + uint32_t FRZ:1; + uint32_t WEN:1; + } B; + } MCR; + + union { /* Interrupt register */ + uint32_t R; + struct { + uint32_t :31; + uint32_t TIF:1; + } B; + } IR; + + union { /* Timeout register */ + uint32_t R; + struct { + uint32_t WTO:32; + } B; + } TO; + + union { /* Window register */ + uint32_t R; + struct { + uint32_t WST:32; + } B; + } WN; + + union { /* Service register */ + uint32_t R; + struct { + uint32_t :16; + uint32_t WSC:16; + } B; + } SR; + + union { /* Counter output register */ + uint32_t R; + struct { + uint32_t CNT:32; + } B; + } CO; + + union { /* Service key register */ + uint32_t R; + struct { + uint32_t :16; + uint32_t SK:16; + } B; + } SK; + + uint32_t SWT_reserved001C[4089]; /* 0x001C-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : STM */ +/****************************************************************************/ + + struct STM_tag { + + union { /* Control Register */ + uint32_t R; + struct { + uint32_t :16; + uint32_t CPS:8; + uint32_t :6; + uint32_t FRZ:1; + uint32_t TEN:1; + } B; + } CR; + + union { /* STM Counter */ + uint32_t R; + } CNT; + + uint32_t STM_reserved0008[2]; /* 0x0008-0x000F */ + + /* channel 0 registers */ + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CEN:1; + } B; + } CCR0; /* Chan 0 Control Register */ + + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CIF:1; + } B; + } CIR0; /* Chan 0 Interrupt Register */ + + union { + uint32_t R; + } CMP0; /* Chan 0 Compare Register */ + + uint32_t STM_reserved2[1]; + +/* channel 1 registers */ + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CEN:1; + } B; + } CCR1; /* Chan 1 Control Register */ + + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CIF:1; + } B; + } CIR1; /* Chan 1 Interrupt Register */ + + union { + uint32_t R; + } CMP1; /* Chan 1 Compare Register */ + + uint32_t STM_reserved3[1]; + +/* channel 2 registers */ + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CEN:1; + } B; + } CCR2; /* Chan 2 Control Register */ + + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CIF:1; + } B; + } CIR2; /* Chan 2 Interrupt Register */ + + union { + uint32_t R; + } CMP2; /* Chan 2 Compare Register */ + + uint32_t STM_reserved4[1]; + +/* channel 3 registers */ + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CEN:1; + } B; + } CCR3; /* Chan 3 Control Register */ + + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CIF:1; + } B; + } CIR3; /* Chan 3 Interrupt Register */ + + union { + uint32_t R; + } CMP3; /* Chan 3 Compare Register */ + + uint32_t STM_reserved0050[4076]; /* 0x0050-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : ECSM */ +/****************************************************************************/ + + struct ECSM_tag { + + union { /* Processor core type */ + uint16_t R; + } PCT; + + union { /* Platform revision */ + uint16_t R; + } REV; + + uint32_t ECSM_reserved0004; /* 0x0004-0x0007 */ + + union { /* IPS Module Configuration */ + uint32_t R; + } IMC; + + uint8_t ECSM_reserved000C[3]; /* 0x000C-0x000E */ + + union { /* Miscellaneous Reset Status Register */ + uint8_t R; + struct { + uint8_t POR:1; + uint8_t DIR:1; + uint8_t SWTR:1; + uint8_t:5; + } B; + } MRSR; + + uint8_t ECSM_reserved0010[51]; /* 0x0010-0x0042 */ + + union { /* ECC Configuration Register */ + uint8_t R; + struct { + uint8_t:2; + uint8_t ER1BR:1; + uint8_t EF1BR:1; + uint8_t:2; + uint8_t ERNCR:1; + uint8_t EFNCR:1; + } B; + } ECR; + + uint8_t ECSM_reserved0044[3]; /* 0x0044-0x0046 */ + + union { /* ECC Status Register */ + uint8_t R; + struct { + uint8_t:2; + uint8_t R1BC:1; + uint8_t F1BC:1; + uint8_t:2; + uint8_t RNCE:1; + uint8_t FNCE:1; + } B; + } ESR; + + uint16_t ECSM_reserved0048; /* 0x0048-0x0049 */ + + union { /* ECC Error Generation Register */ + uint16_t R; + struct { + uint16_t:2; + uint16_t FRC1BI:1; + uint16_t FR11BI:1; + uint16_t:2; + uint16_t FRCNCI:1; + uint16_t FR1NCI:1; + uint16_t:1; + uint16_t ERRBIT:7; + } B; + } EEGR; + + uint32_t ECSM_reserved004C; /* 0x004C-0x004F */ + + union { /* Flash ECC Address Register */ + uint32_t R; + struct { + uint32_t FEAR:32; + } B; + } FEAR; + + uint16_t ECSM_reserved0054; /* 0x0054-0x0055 */ + + union { /* Flash ECC Master Number Register */ + uint8_t R; + struct { + uint8_t:4; + uint8_t FEMR:4; + } B; + } FEMR; + + union { /* Flash ECC Attributes Register */ + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROT0:1; + uint8_t PROT1:1; + uint8_t PROT2:1; + uint8_t PROT3:1; + } B; + } FEAT; + + union { /* Flash ECC Data Register High */ + uint32_t R; + struct { + uint32_t FEDH:32; + } B; + } FEDRH; + + union { /* Flash ECC Data Register Low */ + uint32_t R; + struct { + uint32_t FEDL:32; + } B; + } FEDRL; + + union { /* RAM ECC Address Register */ + uint32_t R; + struct { + uint32_t REAR:32; + } B; + } REAR; + + uint16_t ECSM_reserved0064; /* 0x0064-0x0065 */ + + union { /* RAM ECC Master Number Register */ + uint8_t R; + struct { + uint8_t:4; + uint8_t REMR:4; + } B; + } REMR; + + union { /* RAM ECC Attributes Register */ + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROT0:1; + uint8_t PROT1:1; + uint8_t PROT2:1; + uint8_t PROT3:1; + } B; + } REAT; + + union { /* RAM ECC Data Register */ + uint32_t R; + struct { + uint32_t REDH:32; + } B; + } REDRH; + + union { /* RAM ECC Data Register */ + uint32_t R; + struct { + uint32_t REDL:32; + } B; + } REDRL; + + uint32_t ECSM_reserved0070[4068]; /* 0x0070-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + + struct INTC_tag { + + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:26; + uint32_t VTES:1; + uint32_t:4; + uint32_t HVEN:1; + } B; + } MCR; + + uint32_t INTC_reserved0004; /* 0x0004-0x0007 */ + + union { /* Current Priority Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR; + + uint32_t INTC_reserved000C; /* 0x000C-0x000F */ + + union { /* Interrupt Acknowledge Register */ + uint32_t R; + struct { + uint32_t VTBA:21; + uint32_t INTVEC:9; + uint32_t:2; + } B; + } IACKR; + + uint32_t INTC_reserved0014; /* 0x0014-0x0017 */ + + union { /* End of Interrupt Register */ + uint32_t R; + struct { + uint32_t EOIR:32; + } B; + } EOIR; + + uint32_t INTC_reserved001C; /* 0x001C-0x001F */ + + union { /* Software Set/Clear Interruput Register */ + uint8_t R; + struct { + uint8_t:6; + uint8_t SET:1; + uint8_t CLR:1; + } B; + } SSCIR[8]; + + uint32_t INTC_reserved0028[6]; /* 0x0028-0x003F */ + + union { /* Software Set/Clear Interrupt Register */ + uint8_t R; + struct { + uint8_t:4; + uint8_t PRI:4; + } B; + } PSR[480]; + + uint16_t INTC_reserved0220[7920]; /* 0x0220-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : EQADC */ +/****************************************************************************/ + + struct EQADC_tag { + + union EQADC_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t ICEA0:1; + uint32_t ICEA1:1; + uint32_t:1; + uint32_t ESSIE:2; + uint32_t:1; + uint32_t DBG:2; + } B; + } MCR; + + uint32_t eQADC_reserved0004; /* 0x0004-0x0007 */ + + union EQADC_NMSFR_tag { /* Null Message Send Format Register */ + uint32_t R; + struct { + uint32_t:6; + uint32_t NMF:26; + } B; + } NMSFR; + + union EQADC_ETDFR_tag { /* External Trigger Digital Filter Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } ETDFR; + + union EQADC_CFPR_tag { /* CFIFO Push Registers */ + uint32_t R; + struct { + uint32_t CFPUSH:32; + } B; + } CFPR[6]; + + uint32_t eQADC_reserved0028[2]; /* 0x0028-0x002F */ + + union EQADC_RFPR_tag { /* Result FIFO Pop Registers */ + uint32_t R; + struct { + uint32_t:16; + uint32_t RFPOP:16; + } B; + } RFPR[6]; + + uint32_t eQADC_reserved0048[2]; /* 0x0048-0x004F */ + + union EQADC_CFCR_tag { /* CFIFO Control Registers */ + uint16_t R; + struct { + uint16_t:3; + uint16_t CFEEE0:1; + uint16_t STRME0:1; + uint16_t SSE:1; + uint16_t CFINV:1; + uint16_t:1; + uint16_t MODE:4; + uint16_t AMODE0:4; + } B; + } CFCR[6]; + + uint32_t eQADC_reserved005C; /* 0x005C-0x005F */ + + union EQADC_IDCR_tag { /* Interrupt and DMA Control Registers */ + uint16_t R; + struct { + uint16_t NCIE:1; + uint16_t TORIE:1; + uint16_t PIE:1; + uint16_t EOQIE:1; + uint16_t CFUIE:1; + uint16_t:1; + uint16_t CFFE:1; + uint16_t CFFS:1; + uint16_t:4; + uint16_t RFOIE:1; + uint16_t:1; + uint16_t RFDE:1; + uint16_t RFDS:1; + } B; + } IDCR[6]; + + uint32_t eQADC_reserved006C; /* 0x006C-0x006F */ + + union { /* FIFO and Interrupt Status Registers */ + uint32_t R; + struct { + uint32_t NCF:1; + uint32_t TORF:1; + uint32_t PF:1; + uint32_t EOQF:1; + uint32_t CFUF:1; + uint32_t SSS:1; + uint32_t CFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t CFCTR:4; + uint32_t TNXTPTR:4; + uint32_t RFCTR:4; + uint32_t POPNXTPTR:4; + } B; + } FISR[6]; + + uint32_t eQADC_reserved0088[2]; /* 0x0088-0x008F */ + + union { /* CFIFO Transfer Counter Registers */ + uint16_t R; + struct { + uint16_t:5; + uint16_t TCCF:11; /* Legacy naming - refer to TC_CF in Reference Manual */ + } B; + } CFTCR[6]; + + uint32_t eQADC_reserved009C[1]; /* 0x009F */ + + union { /* CFIFO Status Register 0 */ + uint32_t R; + struct { + uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB0 in Reference Manual */ + uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB0 in Reference Manual */ + uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB0 in Reference Manual */ + uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB0 in Reference Manual */ + uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB0 in Reference Manual */ + uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB0 in Reference Manual */ + uint32_t:5; + uint32_t LCFTCB0:4; + uint32_t TC_LCFTCB0:11; + } B; + } CFSSR0; + + union { /* CFIFO Status Register 1 */ + uint32_t R; + struct { + uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB1 in Reference Manual */ + uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB1 in Reference Manual */ + uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB1 in Reference Manual */ + uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB1 in Reference Manual */ + uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB1 in Reference Manual */ + uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB1 in Reference Manual */ + uint32_t:5; + uint32_t LCFTCB1:4; + uint32_t TC_LCFTCB1:11; + } B; + } CFSSR1; + + union { /* CFIFO Status Register 2 */ + uint32_t R; + struct { + uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TSSI in Reference Manual */ + uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TSSI in Reference Manual */ + uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TSSI in Reference Manual */ + uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TSSI in Reference Manual */ + uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TSSI in Reference Manual */ + uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TSSI in Reference Manual */ + uint32_t:4; + uint32_t ECBNI:1; + uint32_t LCFTSSI:4; + uint32_t TC_LCFTSSI:11; + } B; + } CFSSR2; + + union { /* CFIFO Status Register */ + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:20; + } B; + } CFSR; + + uint32_t eQADC_reserved00B0; /* 0x00B0-0x00B3 */ + + union EQADC_SSICR_tag { /* SSI Control Register */ + uint32_t R; + struct { + uint32_t:21; + uint32_t MDT:3; + uint32_t:4; + uint32_t BR:4; + } B; + } SSICR; + + union { /* SSI Recieve Data Register */ + uint32_t R; + struct { + uint32_t RDV:1; + uint32_t:5; + uint32_t RDATA:26; + } B; + } SSIRDR; + + uint32_t eQADC_reserved00BC[17]; /* 0x00BC-0x00FF */ + + struct { + union { + uint32_t R; + struct { + uint32_t CFIFO_DATA:32; + } B; + } R[4]; + + uint32_t eQADC_cf_reserved010[12]; /* CFIFO offset 0x010-0x03F */ + + } CF[6]; + + uint32_t eQADC_reserved0280[32]; /* 0x0280-0x02FF */ + + struct { + union { + uint32_t R; + struct { + uint32_t RFIFO_DATA:32; + } B; + } R[4]; + + uint32_t eQADC_rf_reserved010[12]; /* RFIFO offset 0x010-0x03F */ + + } RF[6]; + + uint32_t eQADC_reserved0480[3808]; /* 0x0480-0x3FFF */ + }; + +/****************************************************************************/ +/* MODULE : Decimation Filter */ +/****************************************************************************/ + + struct DECFIL_tag { + + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t FREN:1; + uint32_t :1; + uint32_t FRZ:1; + uint32_t SRES:1; + uint32_t CASCD:2; + uint32_t IDEN:1; + uint32_t ODEN:1; + uint32_t ERREN:1; + uint32_t :1; + uint32_t FTYPE:2; + uint32_t :1; + uint32_t SCAL:2; + uint32_t :1; + uint32_t SAT:1; + uint32_t ISEL:1; + uint32_t :1; + uint32_t DEC_RATE:4; + uint32_t :1; + uint32_t DSEL:1; + uint32_t IBIE:1; + uint32_t OBIE:1; + uint32_t EDME:1; + uint32_t TORE:1; + uint32_t TRFE:1; + uint32_t :1; + } B; + } MCR; + + union { /* Module Status Register */ + uint32_t R; + struct { + uint32_t BSY:1; + uint32_t:1; + uint32_t DEC_COUNTER:4; + uint32_t IDFC:1; + uint32_t ODFC:1; + uint32_t:1; + uint32_t IBIC:1; + uint32_t OBIC:1; + uint32_t:1; + uint32_t DIVRC:1; + uint32_t OVFC:1; + uint32_t OVRC:1; + uint32_t IVRC:1; + uint32_t:6; + uint32_t IDF:1; + uint32_t ODF:1; + uint32_t:1; + uint32_t IBIF:1; + uint32_t OBIF:1; + uint32_t:1; + uint32_t DIVR:1; + uint32_t OVF:1; + uint32_t OVR:1; + uint32_t IVR:1; + } B; + } SR; + + union { /* Module Extended Config Register */ + uint32_t R; + struct { + uint32_t SDMAE:1; + uint32_t SSIG:1; + uint32_t SSAT:1; + uint32_t SCSAT:1; + uint32_t:10; + uint32_t SRQ:1; + uint32_t SZR0:1; + uint32_t:1; + uint32_t SISEL:1; + uint32_t SZROSEL:2; + uint32_t:2; + uint32_t SHLTSEL:2; + uint32_t:1; + uint32_t SRQSEL:3; + uint32_t:2; + uint32_t SENSEL:2; + } B; + } MXCR; + + union { /* Module Extended Status Register */ + uint32_t R; + struct { + uint32_t:7; + uint32_t SDFC:1; + uint32_t:2; + uint32_t SSEC:1; + uint32_t SCEC:1; + uint32_t:1; + uint32_t SSOVFC:1; + uint32_t SCOVFC:1; + uint32_t SVRC:1; + uint32_t:7; + uint32_t SDF:1; + uint32_t:2; + uint32_t SSE:1; + uint32_t SCE:1; + uint32_t:1; + uint32_t SSOVF:1; + uint32_t SCOVF:1; + uint32_t SVR:1; + } B; + } MXSR; + + union { /* Interface Input Buffer Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t PREFILL:1; + uint32_t FLUSH:1; + uint32_t INPBUF:16; + } B; + } IB; + + union { /* Interface Output Buffer Register */ + uint32_t R; + struct { + uint32_t:9; + uint32_t TSI:1; + uint32_t:2; + uint32_t OUTTAG:4; + uint32_t OUTBUF:16; + } B; + } OB; + + uint32_t DFILT_reserved0018[2]; /* 0x0018-0x001F */ + + union { /* Coefficient n Register */ + int32_t R; + struct { + int32_t:8; + int32_t COEF:24; + } B; + } COEF[9]; + + uint32_t DFILT_reserved0044[13]; /* 0x0044-0x0077 */ + + union { /* TAP n Register */ + int32_t R; + struct { + int32_t:8; + int32_t TAP:24; + } B; + } TAP[8]; + + uint32_t DFILT_reserved0098[14]; /* 0x0098-0x00CF */ + + union { /* EDID Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t SAMP_DATA:16; + } B; + } EDID; + + uint32_t DFILT_reserved00D4[459]; /* 0x00D4-0x07FF */ + + }; + +/****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + + struct DSPI_tag { + + union DSPI_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t MSTR:1; + uint32_t CONT_SCKE:1; + uint32_t DCONF:2; + uint32_t FRZ:1; + uint32_t MTFE:1; + uint32_t PCSSE:1; + uint32_t ROOE:1; + uint32_t PCSIS7:1; + uint32_t PCSIS6:1; + uint32_t PCSIS5:1; + uint32_t PCSIS4:1; + uint32_t PCSIS3:1; + uint32_t PCSIS2:1; + uint32_t PCSIS1:1; + uint32_t PCSIS0:1; + uint32_t DOZE:1; + uint32_t MDIS:1; + uint32_t DIS_TXF:1; + uint32_t DIS_RXF:1; + uint32_t CLR_TXF:1; + uint32_t CLR_RXF:1; + uint32_t SMPL_PT:2; + uint32_t:7; + uint32_t HALT:1; + } B; + } MCR; + + uint32_t DSPI_reserved0004; /* 0x0004-0x0007 */ + + union { /* Transfer Count Register */ + uint32_t R; + struct { + uint32_t TCNT:16; + uint32_t:16; + } B; + } TCR; + + union DSPI_CTAR_tag {/* Clock and Transfer Attributes Registers */ + uint32_t R; + struct { + uint32_t DBR:1; + uint32_t FMSZ:4; + uint32_t CPOL:1; + uint32_t CPHA:1; + uint32_t LSBFE:1; + uint32_t PCSSCK:2; + uint32_t PASC:2; + uint32_t PDT:2; + uint32_t PBR:2; + uint32_t CSSCK:4; + uint32_t ASC:4; + uint32_t DT:4; + uint32_t BR:4; + } B; + } CTAR[8]; + + union DSPI_SR_tag { /* Status Register */ + uint32_t R; + struct { + uint32_t TCF:1; + uint32_t TXRXS:1; + uint32_t:1; + uint32_t EOQF:1; + uint32_t TFUF:1; + uint32_t:1; + uint32_t TFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t TXCTR:4; + uint32_t TXNXTPTR:4; + uint32_t RXCTR:4; + uint32_t POPNXTPTR:4; + } B; + } SR; + + union DSPI_RSER_tag { /* DMA/Interrupt Request Select and Enable Register */ + uint32_t R; + struct { + uint32_t TCFRE:1; + uint32_t:2; + uint32_t EOQFRE:1; + uint32_t TFUFRE:1; + uint32_t:1; + uint32_t TFFFRE:1; + uint32_t TFFFDIRS:1; + uint32_t:4; + uint32_t RFOFRE:1; + uint32_t:1; + uint32_t RFDFRE:1; + uint32_t RFDFDIRS:1; + uint32_t:16; + } B; + } RSER; + + union DSPI_PUSHR_tag { /* PUSH TX FIFO Register */ + uint32_t R; + struct { + uint32_t CONT:1; + uint32_t CTAS:3; + uint32_t EOQ:1; + uint32_t CTCNT:1; + uint32_t:2; + uint32_t PCS7:1; + uint32_t PCS6:1; + uint32_t PCS5:1; + uint32_t PCS4:1; + uint32_t PCS3:1; + uint32_t PCS2:1; + uint32_t PCS1:1; + uint32_t PCS0:1; + uint32_t TXDATA:16; + } B; + } PUSHR; + + union DSPI_POPR_tag { /* POP RX FIFO Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } POPR; + + union { /* Transmit FIFO Registers */ + uint32_t R; + struct { + uint32_t TXCMD:16; + uint32_t TXDATA:16; + } B; + } TXFR[4]; + + uint32_t DSPI_reserved004C[12]; /* 0x004C-0x007B */ + + union { /* Transmit FIFO Registers */ + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } RXFR[4]; + + uint32_t DSPI_reserved008C[12]; /* 0x008C-0x00BB */ + + union { /* DSI Configuration Register */ + uint32_t R; + struct { + uint32_t MTOE:1; + uint32_t:1; + uint32_t MTOCNT:6; + uint32_t:3; + uint32_t TSBC:1; + uint32_t TXSS:1; + uint32_t TPOL:1; + uint32_t TRRE:1; + uint32_t CID:1; + uint32_t DCONT:1; + uint32_t DSICTAS:3; + uint32_t:4; + uint32_t DPCS7:1; + uint32_t DPCS6:1; + uint32_t DPCS5:1; + uint32_t DPCS4:1; + uint32_t DPCS3:1; + uint32_t DPCS2:1; + uint32_t DPCS1:1; + uint32_t DPCS0:1; + } B; + } DSICR; + + union { /* DSI Serialization Data Register */ + uint32_t R; + struct { + uint32_t SER_DATA:32; + } B; + } SDR; + + union { /* DSI Alternate Serialization Data Register */ + uint32_t R; + struct { + uint32_t ASER_DATA:32; + } B; + } ASDR; + + union { /* DSI Transmit Comparison Register */ + uint32_t R; + struct { + uint32_t COMP_DATA:32; + } B; + } COMPR; + + union { /* DSI deserialization Data Register */ + uint32_t R; + struct { + uint32_t DESER_DATA:32; + } B; + } DDR; + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t TSBCNT:5; + uint32_t:16; + uint32_t DPCS1_7:1; + uint32_t DPCS1_6:1; + uint32_t DPCS1_5:1; + uint32_t DPCS1_4:1; + uint32_t DPCS1_3:1; + uint32_t DPCS1_2:1; + uint32_t DPCS1_1:1; + uint32_t DPCS1_0:1; + } B; + } DSICR1; + uint32_t DSPI_reserved00D4[4043]; /* 0x00D4-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + + struct ESCI_tag { + union ESCI_CR1_tag { /* Control Register 1 */ + uint32_t R; + struct { + uint32_t:3; + uint32_t SBR:13; + uint32_t LOOPS:1; + uint32_t:1; + uint32_t RSRC:1; + uint32_t M:1; + uint32_t WAKE:1; + uint32_t ILT:1; + uint32_t PE:1; + uint32_t PT:1; + uint32_t TIE:1; + uint32_t TCIE:1; + uint32_t RIE:1; + uint32_t ILIE:1; + uint32_t TE:1; + uint32_t RE:1; + uint32_t RWU:1; + uint32_t SBK:1; + } B; + } CR1; + + union ESCI_CR2_tag { /* Control Register 2 */ + uint16_t R; + struct { + uint16_t MDIS:1; + uint16_t FBR:1; + uint16_t BSTP:1; + uint16_t IEBERR:1; + uint16_t RXDMA:1; + uint16_t TXDMA:1; + uint16_t BRK13:1; + uint16_t TXDIR:1; + uint16_t BESM13:1; + uint16_t SBSTP:1; + uint16_t RXPOL:1; + uint16_t PMSK:1; + uint16_t ORIE:1; + uint16_t NFIE:1; + uint16_t FEIE:1; + uint16_t PFIE:1; + } B; + } CR2; + + union ESCI_DR_tag { /* Data Register */ + uint16_t R; + + struct { + uint16_t RN:1; + uint16_t TN:1; + uint16_t ERR:1; + uint16_t:1; + uint16_t RD_11:4; + uint16_t D:8; + } B; + } DR; /* Legacy naming - refer to SDR in Reference Manual */ + + union ESCI_SR_tag { /* Status Register */ + uint32_t R; + struct { + uint32_t TDRE:1; + uint32_t TC:1; + uint32_t RDRF:1; + uint32_t IDLE:1; + uint32_t OR:1; + uint32_t NF:1; + uint32_t FE:1; + uint32_t PF:1; + uint32_t:3; + uint32_t BERR:1; + uint32_t:2; + uint32_t TACT:1; + uint32_t RAF:1; + uint32_t RXRDY:1; + uint32_t TXRDY:1; + uint32_t LWAKE:1; + uint32_t STO:1; + uint32_t PBERR:1; + uint32_t CERR:1; + uint32_t CKERR:1; + uint32_t FRC:1; + uint32_t:6; + uint32_t UREQ:1; + uint32_t OVFL:1; + } B; + } SR; + + union { /* LIN Control Register */ + uint32_t R; + struct { + uint32_t LRES:1; + uint32_t WU:1; + uint32_t WUD0:1; + uint32_t WUD1:1; + uint32_t :2; + uint32_t PRTY:1; + uint32_t LIN:1; + uint32_t RXIE:1; + uint32_t TXIE:1; + uint32_t WUIE:1; + uint32_t STIE:1; + uint32_t PBIE:1; + uint32_t CIE:1; + uint32_t CKIE:1; + uint32_t FCIE:1; + uint32_t:6; + uint32_t UQIE:1; + uint32_t OFIE:1; + uint32_t:8; + } B; + } LCR; + + union { /* LIN Transmit Register */ + uint8_t R; + } LTR; + + uint8_t eSCI_reserved0011[3]; /* 0x0011-0x0013 */ + + union { /* LIN Recieve Register */ + uint8_t R; + struct { + uint8_t D:8; + } B; + } LRR; + + uint8_t eSCI_reserved0015[3]; /* 0x0015-0x0017 */ + + union { /* LIN CRC Polynom Register */ + uint16_t R; + struct { + uint16_t P:16; + } B; + } LPR; + + union { /* Control Register 3 */ + uint16_t R; + struct { + uint16_t:3; + uint16_t SYNM:1; + uint16_t EROE:1; + uint16_t ERFE:1; + uint16_t ERPE:1; + uint16_t M2:1; + uint16_t:8; + } B; + } CR3; + + uint32_t eSCI_reserved001C; /* 0x001C-0x001F */ + + uint32_t eSCI_reserved0020[4088]; /* 0x0020-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + + struct FLEXCAN2_tag { + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t FEN:1; + uint32_t HALT:1; + uint32_t NOTRDY:1; + uint32_t WAK_MSK:1; + uint32_t SOFTRST:1; + uint32_t FRZACK:1; + uint32_t SUPV:1; + uint32_t SLF_WAK:1; + uint32_t WRNEN:1; + uint32_t MDISACK:1; + uint32_t WAK_SRC:1; + uint32_t DOZE:1; + uint32_t SRXDIS:1; + uint32_t BCC:1; + uint32_t:2; + uint32_t LPRIO_EN:1; + uint32_t AEN:1; + uint32_t:2; + uint32_t IDAM:2; + uint32_t:2; + uint32_t MAXMB:6; + } B; + } MCR; + + union { /* Control Register */ + uint32_t R; + struct { + uint32_t PRESDIV:8; + uint32_t RJW:2; + uint32_t PSEG1:3; + uint32_t PSEG2:3; + uint32_t BOFFMSK:1; + uint32_t ERRMSK:1; + uint32_t CLKSRC:1; + uint32_t LPB:1; + uint32_t TWRNMSK:1; + uint32_t RWRNMSK:1; + uint32_t:2; + uint32_t SMP:1; + uint32_t BOFFREC:1; + uint32_t TSYN:1; + uint32_t LBUF:1; + uint32_t LOM:1; + uint32_t PROPSEG:3; + } B; + } CR; /* Legacy naming - refer to CTRL in Reference Manual */ + + union { /* Free Running Timer */ + uint32_t R; + } TIMER; + + int32_t FLEXCAN_reserved000C; /* 0x000C-0x000F */ + + union { /* RX Global Mask */ + uint32_t R; + struct { + uint32_t MI31:1; + uint32_t MI30:1; + uint32_t MI29:1; + uint32_t MI28:1; + uint32_t MI27:1; + uint32_t MI26:1; + uint32_t MI25:1; + uint32_t MI24:1; + uint32_t MI23:1; + uint32_t MI22:1; + uint32_t MI21:1; + uint32_t MI20:1; + uint32_t MI19:1; + uint32_t MI18:1; + uint32_t MI17:1; + uint32_t MI16:1; + uint32_t MI15:1; + uint32_t MI14:1; + uint32_t MI13:1; + uint32_t MI12:1; + uint32_t MI11:1; + uint32_t MI10:1; + uint32_t MI9:1; + uint32_t MI8:1; + uint32_t MI7:1; + uint32_t MI6:1; + uint32_t MI5:1; + uint32_t MI4:1; + uint32_t MI3:1; + uint32_t MI2:1; + uint32_t MI1:1; + uint32_t MI0:1; + } B; + } RXGMASK; + + union { /* RX 14 Mask */ + uint32_t R; + struct { + uint32_t MI31:1; + uint32_t MI30:1; + uint32_t MI29:1; + uint32_t MI28:1; + uint32_t MI27:1; + uint32_t MI26:1; + uint32_t MI25:1; + uint32_t MI24:1; + uint32_t MI23:1; + uint32_t MI22:1; + uint32_t MI21:1; + uint32_t MI20:1; + uint32_t MI19:1; + uint32_t MI18:1; + uint32_t MI17:1; + uint32_t MI16:1; + uint32_t MI15:1; + uint32_t MI14:1; + uint32_t MI13:1; + uint32_t MI12:1; + uint32_t MI11:1; + uint32_t MI10:1; + uint32_t MI9:1; + uint32_t MI8:1; + uint32_t MI7:1; + uint32_t MI6:1; + uint32_t MI5:1; + uint32_t MI4:1; + uint32_t MI3:1; + uint32_t MI2:1; + uint32_t MI1:1; + uint32_t MI0:1; + } B; + } RX14MASK; + + union { /* RX 15 Mask */ + uint32_t R; + struct { + uint32_t MI31:1; + uint32_t MI30:1; + uint32_t MI29:1; + uint32_t MI28:1; + uint32_t MI27:1; + uint32_t MI26:1; + uint32_t MI25:1; + uint32_t MI24:1; + uint32_t MI23:1; + uint32_t MI22:1; + uint32_t MI21:1; + uint32_t MI20:1; + uint32_t MI19:1; + uint32_t MI18:1; + uint32_t MI17:1; + uint32_t MI16:1; + uint32_t MI15:1; + uint32_t MI14:1; + uint32_t MI13:1; + uint32_t MI12:1; + uint32_t MI11:1; + uint32_t MI10:1; + uint32_t MI9:1; + uint32_t MI8:1; + uint32_t MI7:1; + uint32_t MI6:1; + uint32_t MI5:1; + uint32_t MI4:1; + uint32_t MI3:1; + uint32_t MI2:1; + uint32_t MI1:1; + uint32_t MI0:1; + } B; + } RX15MASK; + + union { /* Error Counter Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t RXECNT:8; + uint32_t TXECNT:8; + } B; + } ECR; + + union { /* Error and Status Register */ + uint32_t R; + struct { + uint32_t:14; + + uint32_t TWRNINT:1; + uint32_t RWRNINT:1; + uint32_t BIT1ERR:1; + uint32_t BIT0ERR:1; + uint32_t ACKERR:1; + uint32_t CRCERR:1; + uint32_t FRMERR:1; + uint32_t STFERR:1; + uint32_t TXWRN:1; + uint32_t RXWRN:1; + uint32_t IDLE:1; + uint32_t TXRX:1; + uint32_t FLTCONF:2; + uint32_t:1; + uint32_t BOFFINT:1; + uint32_t ERRINT:1; + uint32_t WAKINT:1; + } B; + } ESR; + + union { /* Interruput Masks Register */ + uint32_t R; + struct { + uint32_t BUF63M:1; + uint32_t BUF62M:1; + uint32_t BUF61M:1; + uint32_t BUF60M:1; + uint32_t BUF59M:1; + uint32_t BUF58M:1; + uint32_t BUF57M:1; + uint32_t BUF56M:1; + uint32_t BUF55M:1; + uint32_t BUF54M:1; + uint32_t BUF53M:1; + uint32_t BUF52M:1; + uint32_t BUF51M:1; + uint32_t BUF50M:1; + uint32_t BUF49M:1; + uint32_t BUF48M:1; + uint32_t BUF47M:1; + uint32_t BUF46M:1; + uint32_t BUF45M:1; + uint32_t BUF44M:1; + uint32_t BUF43M:1; + uint32_t BUF42M:1; + uint32_t BUF41M:1; + uint32_t BUF40M:1; + uint32_t BUF39M:1; + uint32_t BUF38M:1; + uint32_t BUF37M:1; + uint32_t BUF36M:1; + uint32_t BUF35M:1; + uint32_t BUF34M:1; + uint32_t BUF33M:1; + uint32_t BUF32M:1; + } B; + } IMRH; /* Legacy naming - refer to IMASK2 in Reference Manual */ + + union { /* Interruput Masks Register */ + uint32_t R; + struct { + uint32_t BUF31M:1; + uint32_t BUF30M:1; + uint32_t BUF29M:1; + uint32_t BUF28M:1; + uint32_t BUF27M:1; + uint32_t BUF26M:1; + uint32_t BUF25M:1; + uint32_t BUF24M:1; + uint32_t BUF23M:1; + uint32_t BUF22M:1; + uint32_t BUF21M:1; + uint32_t BUF20M:1; + uint32_t BUF19M:1; + uint32_t BUF18M:1; + uint32_t BUF17M:1; + uint32_t BUF16M:1; + uint32_t BUF15M:1; + uint32_t BUF14M:1; + uint32_t BUF13M:1; + uint32_t BUF12M:1; + uint32_t BUF11M:1; + uint32_t BUF10M:1; + uint32_t BUF09M:1; + uint32_t BUF08M:1; + uint32_t BUF07M:1; + uint32_t BUF06M:1; + uint32_t BUF05M:1; + uint32_t BUF04M:1; + uint32_t BUF03M:1; + uint32_t BUF02M:1; + uint32_t BUF01M:1; + uint32_t BUF00M:1; + } B; + } IMRL; /* Legacy naming - refer to IMASK1 in Reference Manual */ + + union { /* Interruput Flag Register */ + uint32_t R; + struct { + uint32_t BUF63I:1; + uint32_t BUF62I:1; + uint32_t BUF61I:1; + uint32_t BUF60I:1; + uint32_t BUF59I:1; + uint32_t BUF58I:1; + uint32_t BUF57I:1; + uint32_t BUF56I:1; + uint32_t BUF55I:1; + uint32_t BUF54I:1; + uint32_t BUF53I:1; + uint32_t BUF52I:1; + uint32_t BUF51I:1; + uint32_t BUF50I:1; + uint32_t BUF49I:1; + uint32_t BUF48I:1; + uint32_t BUF47I:1; + uint32_t BUF46I:1; + uint32_t BUF45I:1; + uint32_t BUF44I:1; + uint32_t BUF43I:1; + uint32_t BUF42I:1; + uint32_t BUF41I:1; + uint32_t BUF40I:1; + uint32_t BUF39I:1; + uint32_t BUF38I:1; + uint32_t BUF37I:1; + uint32_t BUF36I:1; + uint32_t BUF35I:1; + uint32_t BUF34I:1; + uint32_t BUF33I:1; + uint32_t BUF32I:1; + } B; + } IFRH; /* Legacy naming - refer to IFLAG2 in Reference Manual */ + + union { /* Interruput Flag Register */ + uint32_t R; + struct { + uint32_t BUF31I:1; + uint32_t BUF30I:1; + uint32_t BUF29I:1; + uint32_t BUF28I:1; + uint32_t BUF27I:1; + uint32_t BUF26I:1; + uint32_t BUF25I:1; + uint32_t BUF24I:1; + uint32_t BUF23I:1; + uint32_t BUF22I:1; + uint32_t BUF21I:1; + uint32_t BUF20I:1; + uint32_t BUF19I:1; + uint32_t BUF18I:1; + uint32_t BUF17I:1; + uint32_t BUF16I:1; + uint32_t BUF15I:1; + uint32_t BUF14I:1; + uint32_t BUF13I:1; + uint32_t BUF12I:1; + uint32_t BUF11I:1; + uint32_t BUF10I:1; + uint32_t BUF09I:1; + uint32_t BUF08I:1; + uint32_t BUF07I:1; + uint32_t BUF06I:1; + uint32_t BUF05I:1; + uint32_t BUF04I:1; + uint32_t BUF03I:1; + uint32_t BUF02I:1; + uint32_t BUF01I:1; + uint32_t BUF00I:1; + } B; + } IFRL; /* Legacy naming - refer to IFLAG1 in Reference Manual */ + + uint32_t FLEXCAN_reserved0034[19]; /* 0x0034-0x007F */ + + struct canbuf_t { + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t CODE:4; + uint32_t:1; + uint32_t SRR:1; + uint32_t IDE:1; + uint32_t RTR:1; + uint32_t LENGTH:4; + uint32_t TIMESTAMP:16; + } B; + } CS; + + union { + uint32_t R; + struct { + uint32_t PRIO:3; + uint32_t STD_ID:11; + uint32_t EXT_ID:18; + } B; + } ID; + + union { + uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + uint32_t W[2]; /* Data buffer in words (32 bits) */ + uint32_t R[2]; /* Data buffer in words (32 bits) */ + } DATA; + + } BUF[64]; + + int32_t FLEXCAN_reserved0480[256]; /* 0x0480-0x087F */ + + union { /* RX Individual Mask Registers */ + uint32_t R; + struct { + uint32_t MI31:1; + uint32_t MI30:1; + uint32_t MI29:1; + uint32_t MI28:1; + uint32_t MI27:1; + uint32_t MI26:1; + uint32_t MI25:1; + uint32_t MI24:1; + uint32_t MI23:1; + uint32_t MI22:1; + uint32_t MI21:1; + uint32_t MI20:1; + uint32_t MI19:1; + uint32_t MI18:1; + uint32_t MI17:1; + uint32_t MI16:1; + uint32_t MI15:1; + uint32_t MI14:1; + uint32_t MI13:1; + uint32_t MI12:1; + uint32_t MI11:1; + uint32_t MI10:1; + uint32_t MI9:1; + uint32_t MI8:1; + uint32_t MI7:1; + uint32_t MI6:1; + uint32_t MI5:1; + uint32_t MI4:1; + uint32_t MI3:1; + uint32_t MI2:1; + uint32_t MI1:1; + uint32_t MI0:1; + } B; + } RXIMR[64]; + + int32_t FLEXCAN_reserved0980[3488]; /* 0x0980-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : FlexRay */ +/****************************************************************************/ + + typedef union uMVR { + uint16_t R; + struct { + uint16_t CHIVER:8; /* CHI Version Number */ + uint16_t PEVER:8; /* PE Version Number */ + } B; + } MVR_t; + + typedef union uMCR { + uint16_t R; + struct { + uint16_t MEN:1; /* module enable */ + uint16_t:1; + uint16_t SCMD:1; /* single channel mode */ + uint16_t CHB:1; /* channel B enable */ + uint16_t CHA:1; /* channel A enable */ + uint16_t SFFE:1; /* synchronization frame filter enable */ + uint16_t:5; + uint16_t CLKSEL:1; /* protocol engine clock source select */ + uint16_t PRESCALE:3; /* protocol engine clock prescaler */ + uint16_t:1; + } B; + } MCR_t; + + typedef union uSTBSCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t STBSSEL:7; /* strobe signal select */ + uint16_t:3; + uint16_t ENB:1; /* strobe signal enable */ + uint16_t:2; + uint16_t STBPSEL:2; /* strobe port select */ + } B; + } STBSCR_t; + typedef union uSTBPCR { + uint16_t R; + struct { + uint16_t:12; + uint16_t STB3EN:1; /* strobe port enable */ + uint16_t STB2EN:1; /* strobe port enable */ + uint16_t STB1EN:1; /* strobe port enable */ + uint16_t STB0EN:1; /* strobe port enable */ + } B; + } STBPCR_t; + + typedef union uMBDSR { + uint16_t R; + struct { + uint16_t:1; + uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ + uint16_t:1; + uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ + } B; + } MBDSR_t; + typedef union uMBSSUTR { + uint16_t R; + struct { + + uint16_t:1; + uint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */ + uint16_t:1; + uint16_t LAST_MB_UTIL:7; /* last message buffer utilized */ + } B; + } MBSSUTR_t; + + typedef union uPOCR { + uint16_t R; + uint8_t byte[2]; + struct { + uint16_t WME:1; /* write mode external correction command */ + uint16_t:3; + uint16_t EOC_AP:2; /* external offset correction application */ + uint16_t ERC_AP:2; /* external rate correction application */ + uint16_t BSY:1; /* command write busy / write mode command */ + uint16_t:3; + uint16_t POCCMD:4; /* protocol command */ + } B; + } POCR_t; +/* protocol commands */ + typedef union uGIFER { + uint16_t R; + struct { + uint16_t MIF:1; /* module interrupt flag */ + uint16_t PRIF:1; /* protocol interrupt flag */ + uint16_t CHIF:1; /* CHI interrupt flag */ + uint16_t WKUPIF:1; /* wakeup interrupt flag */ + uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ + uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ + uint16_t RBIF:1; /* receive message buffer interrupt flag */ + uint16_t TBIF:1; /* transmit buffer interrupt flag */ + uint16_t MIE:1; /* module interrupt enable */ + uint16_t PRIE:1; /* protocol interrupt enable */ + uint16_t CHIE:1; /* CHI interrupt enable */ + uint16_t WKUPIE:1; /* wakeup interrupt enable */ + uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ + uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ + uint16_t RBIE:1; /* receive message buffer interrupt enable */ + uint16_t TBIE:1; /* transmit buffer interrupt enable */ + } B; + } GIFER_t; + typedef union uPIFR0 { + uint16_t R; + struct { + uint16_t FATLIF:1; /* fatal protocol error interrupt flag */ + uint16_t INTLIF:1; /* internal protocol error interrupt flag */ + uint16_t ILCFIF:1; /* illegal protocol configuration flag */ + uint16_t CSAIF:1; /* cold start abort interrupt flag */ + uint16_t MRCIF:1; /* missing rate correctio interrupt flag */ + uint16_t MOCIF:1; /* missing offset correctio interrupt flag */ + uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ + uint16_t MXSIF:1; /* max sync frames detected interrupt flag */ + uint16_t MTXIF:1; /* media access test symbol received flag */ + uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ + uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ + uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ + uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ + uint16_t TI2IF:1; /* timer 2 expired interrupt flag */ + uint16_t TI1IF:1; /* timer 1 expired interrupt flag */ + uint16_t CYSIF:1; /* cycle start interrupt flag */ + } B; + } PIFR0_t; + typedef union uPIFR1 { + uint16_t R; + struct { + uint16_t EMCIF:1; /* error mode changed interrupt flag */ + uint16_t IPCIF:1; /* illegal protocol command interrupt flag */ + uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ + uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ + uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ + uint16_t:2; + uint16_t EVTIF:1; /* even cycle table written interrupt flag */ + uint16_t ODTIF:1; /* odd cycle table written interrupt flag */ + uint16_t:4; + } B; + } PIFR1_t; + typedef union uPIER0 { + uint16_t R; + struct { + uint16_t FATLIE:1; /* fatal protocol error interrupt enable */ + uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ + uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ + uint16_t CSAIE:1; /* cold start abort interrupt enable */ + uint16_t MRCIE:1; /* missing rate correctio interrupt enable */ + uint16_t MOCIE:1; /* missing offset correctio interrupt enable */ + uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ + uint16_t MXSIE:1; /* max sync frames detected interrupt enable */ + uint16_t MTXIE:1; /* media access test symbol received interrupt enable */ + uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ + uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ + uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ + uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ + uint16_t TI2IE:1; /* timer 2 expired interrupt enable */ + uint16_t TI1IE:1; /* timer 1 expired interrupt enable */ + uint16_t CYSIE:1; /* cycle start interrupt enable */ + } B; + } PIER0_t; + typedef union uPIER1 { + uint16_t R; + struct { + uint16_t EMCIE:1; /* error mode changed interrupt enable */ + uint16_t IPCIE:1; /* illegal protocol command interrupt enable */ + uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ + uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ + uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ + uint16_t:2; + uint16_t EVTIE:1; /* even cycle table written interrupt enable */ + uint16_t ODTIE:1; /* odd cycle table written interrupt enable */ + uint16_t:4; + } B; + } PIER1_t; + typedef union uCHIERFR { + uint16_t R; + struct { + uint16_t FRLBEF:1; /* flame lost channel B error flag */ + uint16_t FRLAEF:1; /* frame lost channel A error flag */ + uint16_t PCMIEF:1; /* command ignored error flag */ + uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ + uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ + uint16_t MSBEF:1; /* message buffer search error flag */ + uint16_t MBUEF:1; /* message buffer utilization error flag */ + uint16_t LCKEF:1; /* lock error flag */ + uint16_t DBLEF:1; /* double transmit message buffer lock error flag */ + uint16_t SBCFEF:1; /* system bus communication failure error flag */ + uint16_t FIDEF:1; /* frame ID error flag */ + uint16_t DPLEF:1; /* dynamic payload length error flag */ + uint16_t SPLEF:1; /* static payload length error flag */ + uint16_t NMLEF:1; /* network management length error flag */ + uint16_t NMFEF:1; /* network management frame error flag */ + uint16_t ILSAEF:1; /* illegal access error flag */ + } B; + } CHIERFR_t; + typedef union uMBIVEC { + uint16_t R; + struct { + + uint16_t:1; + uint16_t TBIVEC:7; /* transmit buffer interrupt vector */ + uint16_t:1; + uint16_t RBIVEC:7; /* receive buffer interrupt vector */ + } B; + } MBIVEC_t; + + typedef union uPSR0 { + uint16_t R; + struct { + uint16_t ERRMODE:2; /* error mode */ + uint16_t SLOTMODE:2; /* slot mode */ + uint16_t:1; + uint16_t PROTSTATE:3; /* protocol state */ + uint16_t SUBSTATE:4; /* protocol sub state */ + uint16_t:1; + uint16_t WAKEUPSTATUS:3; /* wakeup status */ + } B; + } PSR0_t; + +/* protocol states */ +/* protocol sub-states */ +/* wakeup status */ + typedef union uPSR1 { + uint16_t R; + struct { + uint16_t CSAA:1; /* cold start attempt abort flag */ + uint16_t SCP:1; /* cold start path */ + uint16_t:1; + uint16_t REMCSAT:5; /* remanining coldstart attempts */ + uint16_t CPN:1; /* cold start noise path */ + uint16_t HHR:1; /* host halt request pending */ + uint16_t FRZ:1; /* freeze occured */ + uint16_t APTAC:5; /* allow passive to active counter */ + } B; + } PSR1_t; + typedef union uPSR2 { + uint16_t R; + struct { + uint16_t NBVB:1; /* NIT boundary violation on channel B */ + uint16_t NSEB:1; /* NIT syntax error on channel B */ + uint16_t STCB:1; /* symbol window transmit conflict on channel B */ + uint16_t SBVB:1; /* symbol window boundary violation on channel B */ + uint16_t SSEB:1; /* symbol window syntax error on channel B */ + uint16_t MTB:1; /* media access test symbol MTS received on channel B */ + uint16_t NBVA:1; /* NIT boundary violation on channel A */ + uint16_t NSEA:1; /* NIT syntax error on channel A */ + uint16_t STCA:1; /* symbol window transmit conflict on channel A */ + uint16_t SBVA:1; /* symbol window boundary violation on channel A */ + uint16_t SSEA:1; /* symbol window syntax error on channel A */ + uint16_t MTA:1; /* media access test symbol MTS received on channel A */ + uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ + } B; + } PSR2_t; + typedef union uPSR3 { + uint16_t R; + struct { + uint16_t:2; + uint16_t WUB:1; /* wakeup symbol received on channel B */ + uint16_t ABVB:1; /* aggregated boundary violation on channel B */ + uint16_t AACB:1; /* aggregated additional communication on channel B */ + uint16_t ACEB:1; /* aggregated content error on channel B */ + uint16_t ASEB:1; /* aggregated syntax error on channel B */ + uint16_t AVFB:1; /* aggregated valid frame on channel B */ + uint16_t:2; + uint16_t WUA:1; /* wakeup symbol received on channel A */ + uint16_t ABVA:1; /* aggregated boundary violation on channel A */ + uint16_t AACA:1; /* aggregated additional communication on channel A */ + uint16_t ACEA:1; /* aggregated content error on channel A */ + uint16_t ASEA:1; /* aggregated syntax error on channel A */ + uint16_t AVFA:1; /* aggregated valid frame on channel A */ + } B; + } PSR3_t; + typedef union uCIFRR { + uint16_t R; + struct { + uint16_t:8; + uint16_t MIFR:1; /* module interrupt flag */ + uint16_t PRIFR:1; /* protocol interrupt flag */ + uint16_t CHIFR:1; /* CHI interrupt flag */ + uint16_t WUPIFR:1; /* wakeup interrupt flag */ + uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ + uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ + uint16_t RBIFR:1; /* receive message buffer interrupt flag */ + uint16_t TBIFR:1; /* transmit buffer interrupt flag */ + } B; + } CIFRR_t; + typedef union uSFCNTR { + uint16_t R; + struct { + uint16_t SFEVB:4; /* sync frames channel B, even cycle */ + uint16_t SFEVA:4; /* sync frames channel A, even cycle */ + uint16_t SFODB:4; /* sync frames channel B, odd cycle */ + uint16_t SFODA:4; /* sync frames channel A, odd cycle */ + } B; + } SFCNTR_t; + + typedef union uSFTCCSR { + uint16_t R; + struct { + uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ + uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ + uint16_t CYCNUM:6; /* cycle number */ + uint16_t ELKS:1; /* even cycle tables lock status */ + uint16_t OLKS:1; /* odd cycle tables lock status */ + uint16_t EVAL:1; /* even cycle tables valid */ + uint16_t OVAL:1; /* odd cycle tables valid */ + uint16_t:1; + uint16_t OPT:1; /*one pair trigger */ + uint16_t SDVEN:1; /* sync frame deviation table enable */ + uint16_t SIDEN:1; /* sync frame ID table enable */ + } B; + } SFTCCSR_t; + typedef union uSFIDRFR { + uint16_t R; + struct { + uint16_t:6; + uint16_t SYNFRID:10; /* sync frame rejection ID */ + } B; + } SFIDRFR_t; + + typedef union uTICCR { + uint16_t R; + struct { + uint16_t:2; + uint16_t T2CFG:1; /* timer 2 configuration */ + uint16_t T2REP:1; /* timer 2 repetitive mode */ + uint16_t:1; + uint16_t T2SP:1; /* timer 2 stop */ + uint16_t T2TR:1; /* timer 2 trigger */ + uint16_t T2ST:1; /* timer 2 state */ + uint16_t:3; + uint16_t T1REP:1; /* timer 1 repetitive mode */ + uint16_t:1; + uint16_t T1SP:1; /* timer 1 stop */ + uint16_t T1TR:1; /* timer 1 trigger */ + uint16_t T1ST:1; /* timer 1 state */ + + } B; + } TICCR_t; + typedef union uTI1CYSR { + uint16_t R; + struct { + uint16_t:2; + uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ + uint16_t:2; + uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ + + } B; + } TI1CYSR_t; + + typedef union uSSSR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* static slot number */ + uint16_t:1; + uint16_t SLOTNUMBER:11; /* selector */ + } B; + } SSSR_t; + + typedef union uSSCCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:1; + uint16_t CNTCFG:2; /* counter configuration */ + uint16_t MCY:1; /* multi cycle selection */ + uint16_t VFR:1; /* valid frame selection */ + uint16_t SYF:1; /* sync frame selection */ + uint16_t NUF:1; /* null frame selection */ + uint16_t SUF:1; /* startup frame selection */ + uint16_t STATUSMASK:4; /* slot status mask */ + } B; + } SSCCR_t; + typedef union uSSR { + uint16_t R; + struct { + uint16_t VFB:1; /* valid frame on channel B */ + uint16_t SYB:1; /* valid sync frame on channel B */ + uint16_t NFB:1; /* valid null frame on channel B */ + uint16_t SUB:1; /* valid startup frame on channel B */ + uint16_t SEB:1; /* syntax error on channel B */ + uint16_t CEB:1; /* content error on channel B */ + uint16_t BVB:1; /* boundary violation on channel B */ + uint16_t TCB:1; /* tx conflict on channel B */ + uint16_t VFA:1; /* valid frame on channel A */ + uint16_t SYA:1; /* valid sync frame on channel A */ + uint16_t NFA:1; /* valid null frame on channel A */ + uint16_t SUA:1; /* valid startup frame on channel A */ + uint16_t SEA:1; /* syntax error on channel A */ + uint16_t CEA:1; /* content error on channel A */ + uint16_t BVA:1; /* boundary violation on channel A */ + uint16_t TCA:1; /* tx conflict on channel A */ + } B; + } SSR_t; + typedef union uMTSCFR { + uint16_t R; + struct { + uint16_t MTE:1; /* media access test symbol transmission enable */ + uint16_t:1; + uint16_t CYCCNTMSK:6; /* cycle counter mask */ + uint16_t:2; + uint16_t CYCCNTVAL:6; /* cycle counter value */ + } B; + } MTSCFR_t; + typedef union uRSBIR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:4; + uint16_t RSBIDX:8; /* receive shadow buffer index */ + } B; + } RSBIR_t; + typedef union uRFDSR { + uint16_t R; + struct { + uint16_t FIFODEPTH:8; /* fifo depth */ + uint16_t:1; + uint16_t ENTRYSIZE:7; /* entry size */ + } B; + } RFDSR_t; + + typedef union uRFRFCFR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t IBD:1; /* interval boundary */ + uint16_t SEL:2; /* filter number */ + uint16_t:1; + uint16_t SID:11; /* slot ID */ + } B; + } RFRFCFR_t; + + typedef union uRFRFCTR { + uint16_t R; + struct { + uint16_t:4; + uint16_t F3MD:1; /* filter mode */ + uint16_t F2MD:1; /* filter mode */ + uint16_t F1MD:1; /* filter mode */ + uint16_t F0MD:1; /* filter mode */ + uint16_t:4; + uint16_t F3EN:1; /* filter enable */ + uint16_t F2EN:1; /* filter enable */ + uint16_t F1EN:1; /* filter enable */ + uint16_t F0EN:1; /* filter enable */ + } B; + } RFRFCTR_t; + typedef union uPCR0 { + uint16_t R; + struct { + uint16_t ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_LENGTH:10; + } B; + } PCR0_t; + + typedef union uPCR1 { + uint16_t R; + struct { + uint16_t:2; + uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; + } B; + } PCR1_t; + + typedef union uPCR2 { + uint16_t R; + struct { + uint16_t MINISLOT_AFTER_ACTION_POINT:6; + uint16_t NUMBER_OF_STATIC_SLOTS:10; + } B; + } PCR2_t; + + typedef union uPCR3 { + uint16_t R; + struct { + uint16_t WAKEUP_SYMBOL_RX_LOW:6; + uint16_t MINISLOT_ACTION_POINT_OFFSET:5; + uint16_t COLDSTART_ATTEMPTS:5; + } B; + } PCR3_t; + + typedef union uPCR4 { + uint16_t R; + struct { + uint16_t CAS_RX_LOW_MAX:7; + uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; + } B; + } PCR4_t; + + typedef union uPCR5 { + uint16_t R; + struct { + uint16_t TSS_TRANSMITTER:4; + uint16_t WAKEUP_SYMBOL_TX_LOW:6; + uint16_t WAKEUP_SYMBOL_RX_IDLE:6; + } B; + } PCR5_t; + + typedef union uPCR6 { + uint16_t R; + struct { + uint16_t:1; + uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; + uint16_t MACRO_INITIAL_OFFSET_A:7; + } B; + } PCR6_t; + + typedef union uPCR7 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_B:9; + uint16_t MICRO_PER_MACRO_NOM_HALF:7; + } B; + } PCR7_t; + + typedef union uPCR8 { + uint16_t R; + struct { + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; + uint16_t WAKEUP_SYMBOL_TX_IDLE:8; + } B; + } PCR8_t; + + typedef union uPCR9 { + uint16_t R; + struct { + uint16_t MINISLOT_EXISTS:1; + uint16_t SYMBOL_WINDOW_EXISTS:1; + uint16_t OFFSET_CORRECTION_OUT:14; + } B; + } PCR9_t; + + typedef union uPCR10 { + uint16_t R; + struct { + uint16_t SINGLE_SLOT_ENABLED:1; + uint16_t WAKEUP_CHANNEL:1; + uint16_t MACRO_PER_CYCLE:14; + } B; + } PCR10_t; + + typedef union uPCR11 { + uint16_t R; + struct { + uint16_t KEY_SLOT_USED_FOR_STARTUP:1; + uint16_t KEY_SLOT_USED_FOR_SYNC:1; + uint16_t OFFSET_CORRECTION_START:14; + } B; + } PCR11_t; + + typedef union uPCR12 { + uint16_t R; + struct { + uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; + uint16_t KEY_SLOT_HEADER_CRC:11; + } B; + } PCR12_t; + + typedef union uPCR13 { + uint16_t R; + struct { + uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; + } B; + } PCR13_t; + + typedef union uPCR14 { + uint16_t R; + struct { + uint16_t RATE_CORRECTION_OUT:11; + uint16_t LISTEN_TIMEOUT_H:5; + } B; + } PCR14_t; + + typedef union uPCR15 { + uint16_t R; + struct { + uint16_t LISTEN_TIMEOUT_L:16; + } B; + } PCR15_t; + + typedef union uPCR16 { + uint16_t R; + struct { + uint16_t MACRO_INITIAL_OFFSET_B:7; + uint16_t NOISE_LISTEN_TIMEOUT_H:9; + } B; + } PCR16_t; + + typedef union uPCR17 { + uint16_t R; + struct { + uint16_t NOISE_LISTEN_TIMEOUT_L:16; + } B; + } PCR17_t; + + typedef union uPCR18 { + uint16_t R; + struct { + uint16_t WAKEUP_PATTERN:6; + uint16_t KEY_SLOT_ID:10; + } B; + } PCR18_t; + + typedef union uPCR19 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_A:9; + uint16_t PAYLOAD_LENGTH_STATIC:7; + } B; + } PCR19_t; + + typedef union uPCR20 { + uint16_t R; + struct { + uint16_t MICRO_INITIAL_OFFSET_B:8; + uint16_t MICRO_INITIAL_OFFSET_A:8; + } B; + } PCR20_t; + + typedef union uPCR21 { + uint16_t R; + struct { + uint16_t EXTERN_RATE_CORRECTION:3; + uint16_t LATEST_TX:13; + } B; + } PCR21_t; + + typedef union uPCR22 { + uint16_t R; + struct { + uint16_t:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; + uint16_t MICRO_PER_CYCLE_H:4; + } B; + } PCR22_t; + + typedef union uPCR23 { + uint16_t R; + struct { + uint16_t micro_per_cycle_l:16; + } B; + } PCR23_t; + + typedef union uPCR24 { + uint16_t R; + struct { + uint16_t CLUSTER_DRIFT_DAMPING:5; + uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; + uint16_t MICRO_PER_CYCLE_MIN_H:4; + } B; + } PCR24_t; + + typedef union uPCR25 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MIN_L:16; + } B; + } PCR25_t; + + typedef union uPCR26 { + uint16_t R; + struct { + uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; + uint16_t MICRO_PER_CYCLE_MAX_H:4; + } B; + } PCR26_t; + + typedef union uPCR27 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MAX_L:16; + } B; + } PCR27_t; + + typedef union uPCR28 { + uint16_t R; + struct { + uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; + uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; + } B; + } PCR28_t; + + typedef union uPCR29 { + uint16_t R; + struct { + uint16_t EXTERN_OFFSET_CORRECTION:3; + uint16_t MINISLOTS_MAX:13; + } B; + } PCR29_t; + + typedef union uPCR30 { + uint16_t R; + struct { + uint16_t:12; + uint16_t SYNC_NODE_MAX:4; + } B; + } PCR30_t; + + typedef struct uMSG_BUFF_CCS { + union { + uint16_t R; + struct { + uint16_t:1; + uint16_t MCM:1; /* message buffer commit mode */ + uint16_t MBT:1; /* message buffer type */ + uint16_t MTD:1; /* message buffer direction */ + uint16_t CMT:1; /* commit for transmission */ + uint16_t EDT:1; /* enable / disable trigger */ + uint16_t LCKT:1; /* lock request trigger */ + uint16_t MBIE:1; /* message buffer interrupt enable */ + uint16_t:3; + uint16_t DUP:1; /* data updated */ + uint16_t DVAL:1; /* data valid */ + uint16_t EDS:1; /* lock status */ + uint16_t LCKS:1; /* enable / disable status */ + uint16_t MBIF:1; /* message buffer interrupt flag */ + } B; + } MBCCSR; + union { + uint16_t R; + struct { + uint16_t MTM:1; /* message buffer transmission mode */ + uint16_t CHNLA:1; /* channel assignement */ + uint16_t CHNLB:1; /* channel assignement */ + uint16_t CCFE:1; /* cycle counter filter enable */ + uint16_t CCFMSK:6; /* cycle counter filter mask */ + uint16_t CCFVAL:6; /* cycle counter filter value */ + } B; + } MBCCFR; + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t FID:11; /* frame ID */ + } B; + } MBFIDR; + union { + uint16_t R; + struct { + uint16_t:8; + uint16_t MBIDX:8; /* message buffer index */ + } B; + } MBIDXR; + } MSG_BUFF_CCS_t; + typedef union uSYSBADHR { + uint16_t R; + } SYSBADHR_t; + typedef union uSYSBADLR { + uint16_t R; + } SYSBADLR_t; + typedef union uPDAR { + uint16_t R; + } PDAR_t; + typedef union uCASERCR { + uint16_t R; + } CASERCR_t; + typedef union uCBSERCR { + uint16_t R; + } CBSERCR_t; + typedef union uCYCTR { + uint16_t R; + } CYCTR_t; + typedef union uMTCTR { + uint16_t R; + } MTCTR_t; + typedef union uSLTCTAR { + uint16_t R; + } SLTCTAR_t; + typedef union uSLTCTBR { + uint16_t R; + } SLTCTBR_t; + typedef union uRTCORVR { + uint16_t R; + } RTCORVR_t; + typedef union uOFCORVR { + uint16_t R; + } OFCORVR_t; + typedef union uSFTOR { + uint16_t R; + } SFTOR_t; + typedef union uSFIDAFVR { + uint16_t R; + } SFIDAFVR_t; + typedef union uSFIDAFMR { + uint16_t R; + } SFIDAFMR_t; + typedef union uNMVR { + uint16_t R; + } NMVR_t; + typedef union uNMVLR { + uint16_t R; + } NMVLR_t; + typedef union uT1MTOR { + uint16_t R; + } T1MTOR_t; + typedef union uTI2CR0 { + uint16_t R; + } TI2CR0_t; + typedef union uTI2CR1 { + uint16_t R; + } TI2CR1_t; + typedef union uSSCR { + uint16_t R; + } SSCR_t; + typedef union uRFSR { + uint16_t R; + } RFSR_t; + typedef union uRFSIR { + uint16_t R; + } RFSIR_t; + typedef union uRFARIR { + uint16_t R; + } RFARIR_t; + typedef union uRFBRIR { + uint16_t R; + } RFBRIR_t; + typedef union uRFMIDAFVR { + uint16_t R; + } RFMIDAFVR_t; + typedef union uRFMIAFMR { + uint16_t R; + } RFMIAFMR_t; + typedef union uRFFIDRFVR { + uint16_t R; + } RFFIDRFVR_t; + typedef union uRFFIDRFMR { + uint16_t R; + } RFFIDRFMR_t; + typedef union uLDTXSLAR { + uint16_t R; + } LDTXSLAR_t; + typedef union uLDTXSLBR { + uint16_t R; + } LDTXSLBR_t; + + typedef struct FR_tag { + volatile MVR_t MVR; /*module version register *//*0 */ + volatile MCR_t MCR; /*module configuration register *//*2 */ + volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ + volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ + volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ + volatile STBPCR_t STBPCR; /*strobe port control register *//*A */ + volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ + volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ + uint16_t reserved3a[1]; /*10 */ + volatile PDAR_t PDAR; /*PE data register *//*12 */ + volatile POCR_t POCR; /*Protocol operation control register *//*14 */ + volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ + volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ + volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ + volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ + volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ + volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ + volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ + volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ + volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ + volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ + volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ + volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ + volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ + volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ + volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ + volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ + volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ + volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ + volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ + volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ + uint16_t reserved3[1]; /*3E */ + volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ + volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ + volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ + volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ + volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ + volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ + volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ + volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ + volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ + volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ + volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ + volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ + volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ + volatile SSSR_t SSSR; /*slot status selection register *//*64 */ + volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ + volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ + volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ + volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ + volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ + volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ + volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ + volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ + volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ + volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ + volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ + volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ + volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ + volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ + volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ + volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ + volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ + volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ + volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ + volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ + volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ + volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ + volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ + volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ + volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ + volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ + volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ + volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ + volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ + volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ + volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ + volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ + volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ + volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ + volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ + volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ + volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ + volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ + volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ + volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ + volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ + volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ + volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ + volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ + volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ + volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ + volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ + volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ + volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ + volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ + uint16_t reserved2[17]; + volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ + } FR_tag_t; + + typedef union uF_HEADER /* frame header */ + { + struct { + uint16_t:5; + uint16_t HDCRC:11; /* Header CRC */ + uint16_t:2; + uint16_t CYCCNT:6; /* Cycle Count */ + uint16_t:1; + uint16_t PLDLEN:7; /* Payload Length */ + uint16_t:1; + uint16_t PPI:1; /* Payload Preamble Indicator */ + uint16_t NUF:1; /* Null Frame Indicator */ + uint16_t SYF:1; /* Sync Frame Indicator */ + uint16_t SUF:1; /* Startup Frame Indicator */ + uint16_t FID:11; /* Frame ID */ + } B; + uint16_t WORDS[3]; + } F_HEADER_t; + typedef union uS_STSTUS /* slot status */ + { + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t CH:1; /* Channel */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t:1; + } RX; + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t TCB:1; /* Tx Conflict on channel B */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t TCA:1; /* Tx Conflict on channel A */ + } TX; + uint16_t R; + } S_STATUS_t; + + typedef struct uMB_HEADER /* message buffer header */ + { + F_HEADER_t FRAME_HEADER; + uint16_t DATA_OFFSET; + S_STATUS_t SLOT_STATUS; + } MB_HEADER_t; + +/* Define memories */ + +#define SRAM_START 0x40000000 +#define SRAM_SIZE 0x40000 +#define SRAM_END 0x4003FFFF + +#define FLASH_START 0x00000000 +#define FLASH_SIZE 0x400000 +#define FLASH_END 0x003FFFFF + +/* Define instances of modules */ +#define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *) 0xC3F00000) +#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000) +#define EBI (*( volatile struct EBI_tag *) 0xC3F84000) +#define FLASH_A (*( volatile struct FLASH_tag *) 0xC3F88000) +#define FLASH FLASH_A +#define FLASH_B (*( volatile struct FLASH_tag *) 0xC3F8C000) +#define SIU (*( volatile struct SIU_tag *) 0xC3F90000) + +#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000) +#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000) + +#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000) +#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) +#define ETPU_DATA_RAM_END 0xC3FC8FFC +#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) +#define CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) + +#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000) + +#define PBRIDGE_B (*( volatile struct PBRIDGE_B_tag *) 0xFFF00000) +#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000) +#define MPU (*( volatile struct MPU_tag *) 0xFFF10000) +#define SWT (*( volatile struct SWT_tag *) 0xFFF38000) +#define STM (*( volatile struct STM_tag *) 0xFFF3C000) +#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000) +#define EDMA_A (*( volatile struct EDMA_tag *) 0xFFF44000) +#define EDMA EDMA_A +#define INTC (*( volatile struct INTC_tag *) 0xFFF48000) +#define EDMA_B (*( volatile struct EDMA_tag *) 0xFFF54000) + +#define EQADC_A (*( volatile struct EQADC_tag *) 0xFFF80000) +#define EQADC EQADC_A +#define EQADC_B (*( volatile struct EQADC_tag *) 0xFFF84000) + +#define DECFIL_A (*( volatile struct DECFIL_tag *) 0xFFF88000) +#define DECFIL_B (*( volatile struct DECFIL_tag *) 0xFFF88800) +#define DECFIL_C (*( volatile struct DECFIL_tag *) 0xFFF89000) +#define DECFIL_D (*( volatile struct DECFIL_tag *) 0xFFF89800) +#define DECFIL_E (*( volatile struct DECFIL_tag *) 0xFFF8A000) +#define DECFIL_F (*( volatile struct DECFIL_tag *) 0xFFF8A800) +#define DECFIL_G (*( volatile struct DECFIL_tag *) 0xFFF8B000) +#define DECFIL_H (*( volatile struct DECFIL_tag *) 0xFFF8B800) + +#define DSPI_A (*( volatile struct DSPI_tag *) 0xFFF90000) +#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000) +#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000) +#define DSPI_D (*( volatile struct DSPI_tag *) 0xFFF9C000) + +#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000) +#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000) +#define ESCI_C (*( volatile struct ESCI_tag *) 0xFFFB8000) +#define ESCI_D (*( volatile struct ESCI_tag *) 0xFFFBC000) + +#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000) +#define CAN_B (*( volatile struct FLEXCAN2_tag *) 0xFFFC4000) +#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000) +#define CAN_D (*( volatile struct FLEXCAN2_tag *) 0xFFFCC000) + +#define FR (*( volatile struct FR_tag *) 0xFFFE0000) +#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000) + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ +#endif /* ifdef _MPC5674_H */ +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ diff --git a/bsps/powerpc/include/mpc55xx/mpc55xx.h b/bsps/powerpc/include/mpc55xx/mpc55xx.h new file mode 100644 index 0000000000..634be30e18 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/mpc55xx.h @@ -0,0 +1,155 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Documentation for this file + */ + +/* + * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup mpc55xx BSP for MPC55xx boards + */ + +/** + * @defgroup mpc55xx_config Configuration files + * + * @ingroup mpc55xx + * + * Makefiles, configure scripts etc. + */ + +/** + * @page mpc55xx_ext_doc External Documentation + * + * @section mpc55xx_ext_doc_mpc5567rm_1 MPC5567 Microcontroller Reference Manual (Rev. 1, January 2007, Volume 1 of 2) + * @section mpc55xx_ext_doc_mpc5567rm_2 MPC5567 Microcontroller Reference Manual (Rev. 1, January 2007, Volume 2 of 2) + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_H +#define LIBCPU_POWERPC_MPC55XX_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +int mpc55xx_flash_copy(void *dest, const void *src, size_t nbytes); +int mpc55xx_flash_copy_op(void *rdest, const void *src, size_t nbytes, + uint32_t opmask, uint32_t *p_fail_addr); +int mpc55xx_flash_size(uint32_t *p_size); +int mpc55xx_flash_writable(void); +uint32_t mpc55xx_flash_address(void); +void mpc55xx_flash_set_read_only(void); +void mpc55xx_flash_set_read_write(void); + +int mpc55xx_physical_address(const void *addr, uint32_t *p_result); +int mpc55xx_mapped_address(const void *addr, uint32_t *p_result); + +/* Bits for opmask. */ +#define MPC55XX_FLASH_BLANK_CHECK 0x01 +#define MPC55XX_FLASH_UNLOCK 0x02 +#define MPC55XX_FLASH_ERASE 0x04 +#define MPC55XX_FLASH_PROGRAM 0x08 +#define MPC55XX_FLASH_VERIFY 0x10 + +/* Error returns. CONFIG or SIZE might mean you just + * need to check for new configuration bits. + * SIZE and RANGE mean you are outside of a known flash region. + * ERASE means the erase failed, + * PROGRAM means the program failed, + * BLANK means it wasn't blank and BLANK_CHECK was specified, + * VERIFY means VERIFY was set and it didn't match the source, + * and LOCK means either the locking failed or you needed to + * specify MPC55XX_FLASH_UNLOCK and didn't. + */ +#define MPC55XX_FLASH_CONFIG_ERR (-1) +#define MPC55XX_FLASH_SIZE_ERR (-2) +#define MPC55XX_FLASH_RANGE_ERR (-3) +#define MPC55XX_FLASH_ERASE_ERR (-4) +#define MPC55XX_FLASH_PROGRAM_ERR (-5) +#define MPC55XX_FLASH_NOT_BLANK_ERR (-6) +#define MPC55XX_FLASH_VERIFY_ERR (-7) +#define MPC55XX_FLASH_LOCK_ERR (-8) + +#define MPC55XX_CACHE_ALIGNED_MASK ((uintptr_t) 0x1f) + +#define MPC55XX_CACHE_LINE_SIZE 32 + +/** + * @brief Returns true if the buffer starting at @a s of size @a n is cache aligned. + */ +static inline int mpc55xx_is_cache_aligned( const void *s, size_t n) +{ + return !(((uintptr_t) s & MPC55XX_CACHE_ALIGNED_MASK) || (n & MPC55XX_CACHE_ALIGNED_MASK)); +} + +static inline uintptr_t mpc55xx_cache_aligned_start( const void *s) +{ + return ((uintptr_t) s & MPC55XX_CACHE_ALIGNED_MASK) ? (((uintptr_t) s & ~MPC55XX_CACHE_ALIGNED_MASK) + MPC55XX_CACHE_LINE_SIZE) : (uintptr_t)s; +} + +static inline size_t mpc55xx_non_cache_aligned_size( const void *s) +{ + return (uintptr_t) mpc55xx_cache_aligned_start( s) - (uintptr_t) s; +} + +static inline size_t mpc55xx_cache_aligned_size( const void *s, size_t n) +{ + return (n - mpc55xx_non_cache_aligned_size( s)) & ~MPC55XX_CACHE_ALIGNED_MASK; +} + +/** + * @brief Returns the number of leading zeros. + */ +static inline uint32_t mpc55xx_count_leading_zeros( uint32_t value) +{ + uint32_t count; + __asm__ ( + "cntlzw %0, %1;" + : "=r" (count) + : "r" (value) + ); + return count; +} + +static inline void mpc55xx_wait_for_interrupt(void) +{ + #ifdef MPC55XX_HAS_WAIT_INSTRUCTION + __asm__ volatile ("wait"); + #else + __asm__ volatile (""); + #endif +} + +static inline void mpc55xx_mmu_apply_config(const struct MMU_tag *config) +{ + PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS0, config->MAS0.R); + PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1, config->MAS1.R); + PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS2, config->MAS2.R); + PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS3, config->MAS3.R); + __asm__ volatile ("tlbwe"); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_H */ diff --git a/bsps/powerpc/include/mpc55xx/reg-defs.h b/bsps/powerpc/include/mpc55xx/reg-defs.h new file mode 100644 index 0000000000..2d66f6a8d0 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/reg-defs.h @@ -0,0 +1,100 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Register definitions. + */ + +/* + * Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_REG_DEFS_H +#define LIBCPU_POWERPC_MPC55XX_REG_DEFS_H + +#include + +#if MPC55XX_CHIP_FAMILY == 551 + #define FLASH_BIUCR 0xFFFF801C +#else + #define FLASH_BIUCR 0xC3F8801C +#endif + +/* + * Definitions for FLASH_BIUCR (Flash BIU Control Register) + */ + +/* Fields for Flash Bus Interface Control */ +/* Fields for Prefetch Control (MnPFE Master n Prefetch Enable) */ + +/* Fields for M3PFE (Master 3 (EBI) prefetch enable bit [12]) */ +#define FLASH_BUICR_EBI_PREFTCH 0x00080000 + +/* Fields for M2PFE (Master 2 (eDMA) prefetch enable bit [13]) */ +#define FLASH_BUICR_EDMA_PREFTCH 0x00040000 + +/* Fields for M1PFE (Master 1 (Nexus) prefetch enable bit [14]) */ +#define FLASH_BUICR_NEX_PREFTCH 0x00020000 + +/* Fields for M0PFE (Master 0 (e200z core) prefetch enable bit [15]) */ +#define FLASH_BUICR_CPU_PREFTCH 0x00010000 + +/* Fields for APC (access pipelining control bits [16:18]) */ +#define FLASH_BUICR_APC_0 0x00000000 +#define FLASH_BUICR_APC_1 0x00002000 +#define FLASH_BUICR_APC_2 0x00004000 +#define FLASH_BUICR_APC_3 0x00006000 +#define FLASH_BUICR_APC_4 0x00008000 +#define FLASH_BUICR_APC_5 0x0000A000 +#define FLASH_BUICR_APC_6 0x0000C000 +#define FLASH_BUICR_APC_NO 0x0000E000 + +/* Fields for WWSC (write wait state control bits [19:20]) */ +#define FLASH_BUICR_WWSC_1 0x00000800 +#define FLASH_BUICR_WWSC_2 0x00001000 +#define FLASH_BUICR_WWSC_3 0x00001800 + +/* Fields for RWSC (read wait state control bits [21:23]) */ +#define FLASH_BUICR_RWSC_0 0x00000000 +#define FLASH_BUICR_RWSC_1 0x00000100 +#define FLASH_BUICR_RWSC_2 0x00000200 +#define FLASH_BUICR_RWSC_3 0x00000300 +#define FLASH_BUICR_RWSC_4 0x00000400 +#define FLASH_BUICR_RWSC_5 0x00000500 +#define FLASH_BUICR_RWSC_6 0x00000600 +#define FLASH_BUICR_RWSC_7 0x00000700 + +/* Fields for DPFEN (data prefetch enable bits [24:25]) */ +#define FLASH_BUICR_DPFEN_0 0x00000000 +#define FLASH_BUICR_DPFEN_1 0x00000040 +#define FLASH_BUICR_DPFEN_3 0x000000C0 + +/* Fields for IPFEN (instruction prefetch enable bits [26:27]) */ +#define FLASH_BUICR_IPFEN_0 0x00000000 +#define FLASH_BUICR_IPFEN_1 0x00000010 +#define FLASH_BUICR_IPFEN_3 0x00000030 + +/* Fields for PFLIM (additional line prefetch (limit) bits [28:30]) */ +#define FLASH_BUICR_PFLIM_0 0x00000000 +#define FLASH_BUICR_PFLIM_1 0x00000002 +#define FLASH_BUICR_PFLIM_2 0x00000004 +#define FLASH_BUICR_PFLIM_3 0x00000006 +#define FLASH_BUICR_PFLIM_4 0x00000008 +#define FLASH_BUICR_PFLIM_5 0x0000000A +#define FLASH_BUICR_PFLIM_6 0x0000000C + +/* Fields for BFEN (enable line read buffer hits bit [31]) */ +#define FLASH_BUICR_BFEN 0x00000001 + +#endif /* LIBCPU_POWERPC_MPC55XX_REG_DEFS_H */ diff --git a/bsps/powerpc/include/mpc55xx/regs-edma.h b/bsps/powerpc/include/mpc55xx/regs-edma.h new file mode 100644 index 0000000000..804730ccd8 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/regs-edma.h @@ -0,0 +1,710 @@ +/** + * @file + * + * @ingroup mpc55xx + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ + +#ifndef LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H +#define LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/* MODULE : eDMA */ +/****************************************************************************/ + struct EDMA_tag { + union EDMA_CR_tag { + uint32_t R; + struct { +#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 + uint32_t:14; + uint32_t CX:1; + uint32_t ECX:1; +#else + uint32_t:16; +#endif + uint32_t GRP3PRI:2; + uint32_t GRP2PRI:2; + uint32_t GRP1PRI:2; + uint32_t GRP0PRI:2; +#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 + uint32_t EMLM:1; + uint32_t CLM:1; + uint32_t HALT:1; + uint32_t HOE:1; +#else + uint32_t:4; +#endif + uint32_t ERGA:1; + uint32_t ERCA:1; + uint32_t EDBG:1; + uint32_t EBW:1; + } B; + } CR; /* Control Register */ + + union { + uint32_t R; + struct { + uint32_t VLD:1; +#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 + uint32_t:14; + uint32_t ECX:1; +#else + uint32_t:15; +#endif + uint32_t GPE:1; + uint32_t CPE:1; + uint32_t ERRCHN:6; + uint32_t SAE:1; + uint32_t SOE:1; + uint32_t DAE:1; + uint32_t DOE:1; + uint32_t NCE:1; + uint32_t SGE:1; + uint32_t SBE:1; + uint32_t DBE:1; + } B; + } ESR; /* Error Status Register */ + + union { + uint32_t R; + struct { + uint32_t ERQ63:1; + uint32_t ERQ62:1; + uint32_t ERQ61:1; + uint32_t ERQ60:1; + uint32_t ERQ59:1; + uint32_t ERQ58:1; + uint32_t ERQ57:1; + uint32_t ERQ56:1; + uint32_t ERQ55:1; + uint32_t ERQ54:1; + uint32_t ERQ53:1; + uint32_t ERQ52:1; + uint32_t ERQ51:1; + uint32_t ERQ50:1; + uint32_t ERQ49:1; + uint32_t ERQ48:1; + uint32_t ERQ47:1; + uint32_t ERQ46:1; + uint32_t ERQ45:1; + uint32_t ERQ44:1; + uint32_t ERQ43:1; + uint32_t ERQ42:1; + uint32_t ERQ41:1; + uint32_t ERQ40:1; + uint32_t ERQ39:1; + uint32_t ERQ38:1; + uint32_t ERQ37:1; + uint32_t ERQ36:1; + uint32_t ERQ35:1; + uint32_t ERQ34:1; + uint32_t ERQ33:1; + uint32_t ERQ32:1; + } B; + } ERQRH; /* DMA Enable Request Register High */ + + union { + uint32_t R; + struct { + uint32_t ERQ31:1; + uint32_t ERQ30:1; + uint32_t ERQ29:1; + uint32_t ERQ28:1; + uint32_t ERQ27:1; + uint32_t ERQ26:1; + uint32_t ERQ25:1; + uint32_t ERQ24:1; + uint32_t ERQ23:1; + uint32_t ERQ22:1; + uint32_t ERQ21:1; + uint32_t ERQ20:1; + uint32_t ERQ19:1; + uint32_t ERQ18:1; + uint32_t ERQ17:1; + uint32_t ERQ16:1; + uint32_t ERQ15:1; + uint32_t ERQ14:1; + uint32_t ERQ13:1; + uint32_t ERQ12:1; + uint32_t ERQ11:1; + uint32_t ERQ10:1; + uint32_t ERQ09:1; + uint32_t ERQ08:1; + uint32_t ERQ07:1; + uint32_t ERQ06:1; + uint32_t ERQ05:1; + uint32_t ERQ04:1; + uint32_t ERQ03:1; + uint32_t ERQ02:1; + uint32_t ERQ01:1; + uint32_t ERQ00:1; + } B; + } ERQRL; /* DMA Enable Request Register Low */ + + union { + uint32_t R; + struct { + uint32_t EEI63:1; + uint32_t EEI62:1; + uint32_t EEI61:1; + uint32_t EEI60:1; + uint32_t EEI59:1; + uint32_t EEI58:1; + uint32_t EEI57:1; + uint32_t EEI56:1; + uint32_t EEI55:1; + uint32_t EEI54:1; + uint32_t EEI53:1; + uint32_t EEI52:1; + uint32_t EEI51:1; + uint32_t EEI50:1; + uint32_t EEI49:1; + uint32_t EEI48:1; + uint32_t EEI47:1; + uint32_t EEI46:1; + uint32_t EEI45:1; + uint32_t EEI44:1; + uint32_t EEI43:1; + uint32_t EEI42:1; + uint32_t EEI41:1; + uint32_t EEI40:1; + uint32_t EEI39:1; + uint32_t EEI38:1; + uint32_t EEI37:1; + uint32_t EEI36:1; + uint32_t EEI35:1; + uint32_t EEI34:1; + uint32_t EEI33:1; + uint32_t EEI32:1; + } B; + } EEIRH; /* DMA Enable Error Interrupt Register High */ + + union { + uint32_t R; + struct { + uint32_t EEI31:1; + uint32_t EEI30:1; + uint32_t EEI29:1; + uint32_t EEI28:1; + uint32_t EEI27:1; + uint32_t EEI26:1; + uint32_t EEI25:1; + uint32_t EEI24:1; + uint32_t EEI23:1; + uint32_t EEI22:1; + uint32_t EEI21:1; + uint32_t EEI20:1; + uint32_t EEI19:1; + uint32_t EEI18:1; + uint32_t EEI17:1; + uint32_t EEI16:1; + uint32_t EEI15:1; + uint32_t EEI14:1; + uint32_t EEI13:1; + uint32_t EEI12:1; + uint32_t EEI11:1; + uint32_t EEI10:1; + uint32_t EEI09:1; + uint32_t EEI08:1; + uint32_t EEI07:1; + uint32_t EEI06:1; + uint32_t EEI05:1; + uint32_t EEI04:1; + uint32_t EEI03:1; + uint32_t EEI02:1; + uint32_t EEI01:1; + uint32_t EEI00:1; + } B; + } EEIRL; /* DMA Enable Error Interrupt Register Low */ + + union { /* DMA Set Enable Request Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t SERQ:7; + } B; + } SERQR; + + union { /* DMA Clear Enable Request Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t CERQ:7; + } B; + } CERQR; + + union { /* DMA Set Enable Error Interrupt Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t SEEI:7; + } B; + } SEEIR; + + union { /* DMA Clear Enable Error Interrupt Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t CEEI:7; + } B; + } CEEIR; + + union { /* DMA Clear Interrupt Request Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t CINT:7; + } B; + } CIRQR; + + union { /* DMA Clear error Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t CERR:7; + } B; + } CER; + + union { /* Set Start Bit Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t SSB:7; + } B; + } SSBR; + + union { /* Clear Done Status Bit Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t CDSB:7; + } B; + } CDSBR; + + union { + uint32_t R; + struct { + uint32_t INT63:1; + uint32_t INT62:1; + uint32_t INT61:1; + uint32_t INT60:1; + uint32_t INT59:1; + uint32_t INT58:1; + uint32_t INT57:1; + uint32_t INT56:1; + uint32_t INT55:1; + uint32_t INT54:1; + uint32_t INT53:1; + uint32_t INT52:1; + uint32_t INT51:1; + uint32_t INT50:1; + uint32_t INT49:1; + uint32_t INT48:1; + uint32_t INT47:1; + uint32_t INT46:1; + uint32_t INT45:1; + uint32_t INT44:1; + uint32_t INT43:1; + uint32_t INT42:1; + uint32_t INT41:1; + uint32_t INT40:1; + uint32_t INT39:1; + uint32_t INT38:1; + uint32_t INT37:1; + uint32_t INT36:1; + uint32_t INT35:1; + uint32_t INT34:1; + uint32_t INT33:1; + uint32_t INT32:1; + } B; + } IRQRH; /* DMA Interrupt Request High */ + + union { + uint32_t R; + struct { + uint32_t INT31:1; + uint32_t INT30:1; + uint32_t INT29:1; + uint32_t INT28:1; + uint32_t INT27:1; + uint32_t INT26:1; + uint32_t INT25:1; + uint32_t INT24:1; + uint32_t INT23:1; + uint32_t INT22:1; + uint32_t INT21:1; + uint32_t INT20:1; + uint32_t INT19:1; + uint32_t INT18:1; + uint32_t INT17:1; + uint32_t INT16:1; + uint32_t INT15:1; + uint32_t INT14:1; + uint32_t INT13:1; + uint32_t INT12:1; + uint32_t INT11:1; + uint32_t INT10:1; + uint32_t INT09:1; + uint32_t INT08:1; + uint32_t INT07:1; + uint32_t INT06:1; + uint32_t INT05:1; + uint32_t INT04:1; + uint32_t INT03:1; + uint32_t INT02:1; + uint32_t INT01:1; + uint32_t INT00:1; + } B; + } IRQRL; /* DMA Interrupt Request Low */ + + union { + uint32_t R; + struct { + uint32_t ERR63:1; + uint32_t ERR62:1; + uint32_t ERR61:1; + uint32_t ERR60:1; + uint32_t ERR59:1; + uint32_t ERR58:1; + uint32_t ERR57:1; + uint32_t ERR56:1; + uint32_t ERR55:1; + uint32_t ERR54:1; + uint32_t ERR53:1; + uint32_t ERR52:1; + uint32_t ERR51:1; + uint32_t ERR50:1; + uint32_t ERR49:1; + uint32_t ERR48:1; + uint32_t ERR47:1; + uint32_t ERR46:1; + uint32_t ERR45:1; + uint32_t ERR44:1; + uint32_t ERR43:1; + uint32_t ERR42:1; + uint32_t ERR41:1; + uint32_t ERR40:1; + uint32_t ERR39:1; + uint32_t ERR38:1; + uint32_t ERR37:1; + uint32_t ERR36:1; + uint32_t ERR35:1; + uint32_t ERR34:1; + uint32_t ERR33:1; + uint32_t ERR32:1; + } B; + } ERH; /* DMA Error High */ + + union { + uint32_t R; + struct { + uint32_t ERR31:1; + uint32_t ERR30:1; + uint32_t ERR29:1; + uint32_t ERR28:1; + uint32_t ERR27:1; + uint32_t ERR26:1; + uint32_t ERR25:1; + uint32_t ERR24:1; + uint32_t ERR23:1; + uint32_t ERR22:1; + uint32_t ERR21:1; + uint32_t ERR20:1; + uint32_t ERR19:1; + uint32_t ERR18:1; + uint32_t ERR17:1; + uint32_t ERR16:1; + uint32_t ERR15:1; + uint32_t ERR14:1; + uint32_t ERR13:1; + uint32_t ERR12:1; + uint32_t ERR11:1; + uint32_t ERR10:1; + uint32_t ERR09:1; + uint32_t ERR08:1; + uint32_t ERR07:1; + uint32_t ERR06:1; + uint32_t ERR05:1; + uint32_t ERR04:1; + uint32_t ERR03:1; + uint32_t ERR02:1; + uint32_t ERR01:1; + uint32_t ERR00:1; + } B; + } ERL; /* DMA Error Low */ + +#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 + union { /* hardware request status high */ + uint32_t R; + struct { + uint32_t HRS63:1; + uint32_t HRS62:1; + uint32_t HRS61:1; + uint32_t HRS60:1; + uint32_t HRS59:1; + uint32_t HRS58:1; + uint32_t HRS57:1; + uint32_t HRS56:1; + uint32_t HRS55:1; + uint32_t HRS54:1; + uint32_t HRS53:1; + uint32_t HRS52:1; + uint32_t HRS51:1; + uint32_t HRS50:1; + uint32_t HRS49:1; + uint32_t HRS48:1; + uint32_t HRS47:1; + uint32_t HRS46:1; + uint32_t HRS45:1; + uint32_t HRS44:1; + uint32_t HRS43:1; + uint32_t HRS42:1; + uint32_t HRS41:1; + uint32_t HRS40:1; + uint32_t HRS39:1; + uint32_t HRS38:1; + uint32_t HRS37:1; + uint32_t HRS36:1; + uint32_t HRS35:1; + uint32_t HRS34:1; + uint32_t HRS33:1; + uint32_t HRS32:1; + } B; + } HRSH; + + union { /* hardware request status low */ + uint32_t R; + struct { + uint32_t HRS31:1; + uint32_t HRS30:1; + uint32_t HRS29:1; + uint32_t HRS28:1; + uint32_t HRS27:1; + uint32_t HRS26:1; + uint32_t HRS25:1; + uint32_t HRS24:1; + uint32_t HRS23:1; + uint32_t HRS22:1; + uint32_t HRS21:1; + uint32_t HRS20:1; + uint32_t HRS19:1; + uint32_t HRS18:1; + uint32_t HRS17:1; + uint32_t HRS16:1; + uint32_t HRS15:1; + uint32_t HRS14:1; + uint32_t HRS13:1; + uint32_t HRS12:1; + uint32_t HRS11:1; + uint32_t HRS10:1; + uint32_t HRS09:1; + uint32_t HRS08:1; + uint32_t HRS07:1; + uint32_t HRS06:1; + uint32_t HRS05:1; + uint32_t HRS04:1; + uint32_t HRS03:1; + uint32_t HRS02:1; + uint32_t HRS01:1; + uint32_t HRS00:1; + } B; + } HRSL; + + uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */ +#else + uint32_t edma_reserved1[52]; +#endif + + union { + uint8_t R; + struct { + uint8_t ECP:1; +#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 + uint8_t DPA:1; +#else + uint8_t:1; +#endif + uint8_t GRPPRI:2; + uint8_t CHPRI:4; + } B; + } CPR[64]; + + uint32_t edma_reserved2[944]; + +/****************************************************************************/ +/* DMA2 Transfer Control Descriptor */ +/****************************************************************************/ + struct tcd_t { + uint32_t SADDR; /* source address */ + + /* Source and destination fields */ + union tcd_SDF_tag { + uint32_t R; + struct { + uint16_t SMOD:5; /* source address modulo */ + uint16_t SSIZE:3; /* source transfer size */ + uint16_t DMOD:5; /* destination address modulo */ + uint16_t DSIZE:3; /* destination transfer size */ + int16_t SOFF; /* signed source address offset */ + } B; + } SDF; + + uint32_t NBYTES; /* inner (“minor”) byte count */ + + int32_t SLAST; /* last destination address adjustment, or + scatter/gather address (if e_sg = 1) */ + + uint32_t DADDR; /* destination address */ + + /* CITER and destination fields */ + union tcd_CDF_tag { + uint32_t R; + struct { + uint16_t CITERE_LINK:1; + uint16_t CITER:15; + int16_t DOFF; /* signed destination address offset */ + } B; + struct { + uint16_t CITERE_LINK:1; + uint16_t CITERLINKCH:6; + uint16_t CITER:9; + int16_t DOFF; + } B_ALT; + struct { + uint16_t CITER; + int16_t DOFF; + } B_NOLINK; + } CDF; + + int32_t DLAST_SGA; + + /* BITER and misc fields */ + union tcd_BMF_tag { + uint32_t R; + struct { + uint32_t BITERE_LINK:1; /* beginning ("major") iteration count */ + uint32_t BITER:15; + uint32_t BWC:2; /* bandwidth control */ + uint32_t MAJORLINKCH:6; /* enable channel-to-channel link */ + uint32_t DONE:1; /* channel done */ + uint32_t ACTIVE:1; /* channel active */ + uint32_t MAJORE_LINK:1; /* enable channel-to-channel link */ + uint32_t E_SG:1; /* enable scatter/gather descriptor */ + uint32_t D_REQ:1; /* disable ipd_req when done */ + uint32_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ + uint32_t INT_MAJ:1; /* interrupt on major loop completion */ + uint32_t START:1; /* explicit channel start */ + } B; + struct { + uint32_t BITERE_LINK:1; + uint32_t BITERLINKCH:6; + uint32_t BITER:9; + uint32_t BWC:2; + uint32_t MAJORLINKCH:6; + uint32_t DONE:1; + uint32_t ACTIVE:1; + uint32_t MAJORE_LINK:1; + uint32_t E_SG:1; + uint32_t D_REQ:1; + uint32_t INT_HALF:1; + uint32_t INT_MAJ:1; + uint32_t START:1; + } B_ALT; + struct { + uint16_t BITER; + uint16_t BWC:2; + uint16_t MAJORLINKCH:6; + uint16_t DONE:1; + uint16_t ACTIVE:1; + uint16_t MAJORE_LINK:1; + uint16_t E_SG:1; + uint16_t D_REQ:1; + uint16_t INT_HALF:1; + uint16_t INT_MAJ:1; + uint16_t START:1; + } B_NOLINK; + } BMF; + } TCD[64]; /* transfer_control_descriptor */ + }; + +#ifndef __cplusplus + static const struct tcd_t EDMA_TCD_DEFAULT = { + .SADDR = 0, + .SDF = { .R = 0 }, + .NBYTES = 0, + .SLAST = 0, + .DADDR = 0, + .CDF = { .R = 0 }, + .DLAST_SGA = 0, + .BMF = { .R = 0 } + }; +#endif /* __cplusplus */ + +#define EDMA_TCD_BITER_MASK 0x7fff + +#define EDMA_TCD_BITER_SIZE (EDMA_TCD_BITER_MASK + 1) + +#define EDMA_TCD_BITER_LINKED_MASK 0x1ff + +#define EDMA_TCD_BITER_LINKED_SIZE (EDMA_TCD_BITER_LINKED_MASK + 1) + +#define EDMA_TCD_LINK_AND_BITER(link, biter) \ + (((link) << 9) + ((biter) & EDMA_TCD_BITER_LINKED_MASK)) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H */ diff --git a/bsps/powerpc/include/mpc55xx/regs-mmu.h b/bsps/powerpc/include/mpc55xx/regs-mmu.h new file mode 100644 index 0000000000..e03047c4ad --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/regs-mmu.h @@ -0,0 +1,200 @@ +/** + * @file + * + * @ingroup mpc55xx + */ + +/* + * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ + +#ifndef LIBCPU_POWERPC_MPC55XX_REGS_MMU_H +#define LIBCPU_POWERPC_MPC55XX_REGS_MMU_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/* MMU */ +/****************************************************************************/ + struct MMU_tag { + union { + uint32_t R; + struct { + uint32_t : 2; + uint32_t TLBSEL : 2; + uint32_t : 7; + uint32_t ESEL : 5; + uint32_t : 11; + uint32_t NV : 5; + } B; + } MAS0; + + union { + uint32_t R; + struct { + uint32_t VALID : 1; + uint32_t IPROT : 1; + uint32_t : 6; + uint32_t TID : 8; + uint32_t : 3; + uint32_t TS : 1; + uint32_t TSIZE : 5; + uint32_t : 7; + } B; + } MAS1; + + union { + uint32_t R; + struct { + uint32_t EPN : 22; + uint32_t : 4; + uint32_t VLE : 1; + uint32_t W : 1; + uint32_t I : 1; + uint32_t M : 1; + uint32_t G : 1; + uint32_t E : 1; + } B; + } MAS2; + + union { + uint32_t R; + struct { + uint32_t RPN : 22; + uint32_t U0 : 1; + uint32_t U1 : 1; + uint32_t U2 : 1; + uint32_t U3 : 1; + uint32_t UX : 1; + uint32_t SX : 1; + uint32_t UW : 1; + uint32_t SW : 1; + uint32_t UR : 1; + uint32_t SR : 1; + } B; + } MAS3; + }; + + union MMU_MAS4_tag { + uint32_t R; + struct { + uint32_t : 2; + uint32_t TLBSELD : 2; + uint32_t : 10; + uint32_t TIDSELD : 2; + uint32_t : 4; + uint32_t TSIZED : 4; + uint32_t : 3; + uint32_t WD : 1; + uint32_t ID : 1; + uint32_t MD : 1; + uint32_t GD : 1; + uint32_t ED : 1; + } B; + }; + + union MMU_MAS6_tag { + uint32_t R; + struct { + uint32_t : 8; + uint32_t SPID : 8; + uint32_t : 15; + uint32_t SAS : 1; + } B; + }; + +#define MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addreff, addrreal, size, x, w, r, io) \ + { \ + .MAS0 = { .B = { .TLBSEL = 1, .ESEL = (idx) } }, \ + .MAS1 = { .B = { \ + .VALID = 1, .IPROT = 1, .TID = 0, .TS = 0, .TSIZE = (size) } \ + }, \ + .MAS2 = { .B = { \ + .EPN = (addreff) >> 10, .VLE = 0, \ + .W = (io) == 2, .I = (io) == 1, .M = 0, .G = (io) == 1, .E = 0 } \ + }, \ + .MAS3 = { .B = { \ + .RPN = (addrreal) >> 10, .U0 = 0, .U1 = 0, .U2 = 0, .U3 = 0, .UX = 0, \ + .SX = (x), .UW = 0, .SW = (w), .UR = 0, .SR = (r) } \ + } \ + } + +#define MPC55XX_MMU_TAG_INITIALIZER(idx, addr, size, x, w, r, io) \ + MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addr, addr, size, x, w, r, io) + +#define MPC55XX_MMU_1K 0 +#define MPC55XX_MMU_2K 1 +#define MPC55XX_MMU_4K 2 +#define MPC55XX_MMU_8K 3 +#define MPC55XX_MMU_16K 4 +#define MPC55XX_MMU_32K 5 +#define MPC55XX_MMU_64K 6 +#define MPC55XX_MMU_128K 7 +#define MPC55XX_MMU_256K 8 +#define MPC55XX_MMU_512K 9 +#define MPC55XX_MMU_1M 10 +#define MPC55XX_MMU_2M 11 +#define MPC55XX_MMU_4M 12 +#define MPC55XX_MMU_8M 13 +#define MPC55XX_MMU_16M 14 +#define MPC55XX_MMU_32M 15 +#define MPC55XX_MMU_64M 16 +#define MPC55XX_MMU_128M 17 +#define MPC55XX_MMU_256M 18 +#define MPC55XX_MMU_512M 19 +#define MPC55XX_MMU_1G 20 +#define MPC55XX_MMU_2G 21 +#define MPC55XX_MMU_4G 22 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_REGS_MMU_H */ diff --git a/bsps/powerpc/include/mpc55xx/regs.h b/bsps/powerpc/include/mpc55xx/regs.h new file mode 100644 index 0000000000..3a4e737f1a --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/regs.h @@ -0,0 +1,88 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Register definitions for the MPC55xx and MPC56xx microcontroller + * family. + */ + +/* + * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_REGS_H +#define LIBCPU_POWERPC_MPC55XX_REGS_H + +#include + +#if MPC55XX_CHIP_FAMILY == 551 + #include + #define MPC55XX_HAS_EBI + #define MPC55XX_HAS_ESCI + #define MPC55XX_HAS_EMIOS + #define MPC55XX_HAS_FMPLL_ENHANCED + #define MPC55XX_HAS_SIU +#elif MPC55XX_CHIP_FAMILY == 555 + #include + #define MPC55XX_HAS_EBI + #define MPC55XX_HAS_ESCI + #define MPC55XX_HAS_EMIOS + #define MPC55XX_HAS_FMPLL + #define MPC55XX_HAS_UNIFIED_CACHE + #define MPC55XX_HAS_SIU +#elif MPC55XX_CHIP_FAMILY == 556 + #include + #define MPC55XX_HAS_EBI + #define MPC55XX_HAS_ESCI + #define MPC55XX_HAS_EMIOS + #define MPC55XX_HAS_FMPLL + #define MPC55XX_HAS_UNIFIED_CACHE + #define MPC55XX_HAS_SIU +#elif MPC55XX_CHIP_FAMILY == 564 + #include + #define MPC55XX_HAS_STM + #define MPC55XX_HAS_SWT + #define MPC55XX_HAS_MODE_CONTROL + #define MPC55XX_HAS_INSTRUCTION_CACHE + #define MPC55XX_HAS_LINFLEX + #define MPC55XX_HAS_SECOND_INTERNAL_RAM_AREA + #define MPC55XX_HAS_SIU_LITE +#elif MPC55XX_CHIP_FAMILY == 566 + #include + #define MPC55XX_HAS_ESCI + #define MPC55XX_HAS_EMIOS + #define MPC55XX_HAS_FMPLL_ENHANCED + #define MPC55XX_HAS_UNIFIED_CACHE + #define MPC55XX_HAS_SIU + /* + * TODO: This e200z650n3e core has a wait instruction, but it did not wake-up + * from PIT interrupts. + */ +#elif MPC55XX_CHIP_FAMILY == 567 + #include + #define MPC55XX_HAS_EBI + #define MPC55XX_HAS_ESCI + #define MPC55XX_HAS_EMIOS + #define MPC55XX_HAS_FMPLL_ENHANCED + #define MPC55XX_HAS_INSTRUCTION_CACHE + #define MPC55XX_HAS_DATA_CACHE + #define MPC55XX_HAS_SIU + #define MPC55XX_HAS_WAIT_INSTRUCTION +#else + #error "unsupported chip type" +#endif + +#define MPC55XX_ZERO_FLAGS { .R = 0 } + +#endif /* LIBCPU_POWERPC_MPC55XX_REGS_H */ diff --git a/bsps/powerpc/include/mpc55xx/siu.h b/bsps/powerpc/include/mpc55xx/siu.h new file mode 100644 index 0000000000..3495750145 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/siu.h @@ -0,0 +1,313 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief System Integration Unit Access (SIU). + */ + +/* + * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_SIU_H +#define LIBCPU_POWERPC_MPC55XX_SIU_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef enum { + #if MPC55XX_CHIP_FAMILY == 567 + PCR_MDO4_GPIO75 = 75, + PCR_MDO5_GPIO76 = 76, + PCR_MDO6_GPIO77 = 77, + PCR_MDO7_GPIO78 = 78, + PCR_MDO8_GPIO79 = 79, + PCR_MDO9_GPIO80 = 80, + PCR_MDO10_GPIO81 = 81, + PCR_MDO11_GPIO82 = 82, + PCR_CNTXA_TXDA_GPIO83 = 83, + PCR_CNRXA_RXDA_GPIO84 = 84, + PCR_CNTXB_PCSC3_GPIO85 = 85, + PCR_CNRXB_PCSC4_GPIO86 = 86, + PCR_CNTXC_PCSD3_GPIO87 = 87, + PCR_CNRXC_PCSD4_GPIO88 = 88, + PCR_TXDA_GPIO89 = 89, + PCR_RXDA_GPIO90 = 90, + PCR_TXDB_PCSD1_GPIO91 = 91, + PCR_RXDB_PCSD5_GPIO92 = 92, + PCR_SCKA_PCSC1_GPIO93 = 93, + PCR_SINA_PCSC2_GPIO94 = 94, + PCR_SOUTA_PCSC5_GPIO95 = 95, + PCR_PCSA0_PCSD2_GPIO96 = 96, + PCR_PCSA1_GPIO97 = 97, + PCR_PCSA2_GPIO98 = 98, + PCR_PCSA3_GPIO99 = 99, + PCR_PCSA4_GPIO100 = 100, + PCR_PCSA5_ETRIG1_GPIO101 = 101, + PCR_SCKB_GPIO102 = 102, + PCR_SINB_GPIO103 = 103, + PCR_SOUTB_GPIO104 = 104, + PCR_PCSB0_PCSD2_GPIO105 = 105, + PCR_PCSB1_PCSD0_GPIO106 = 106, + PCR_PCSB2_SOUTC_GPIO107 = 107, + PCR_PCSB3_SINC_GPIO108 = 108, + PCR_PCSB4_SCKC_GPIO109 = 109, + PCR_PCSB5_PCSC0_GPIO110 = 110, + PCR_TCRCLKA_IRQ7_GPIO113 = 113, + PCR_ETPUA0_ETPUA12_GPIO114 = 114, + PCR_ETPUA1_ETPUA13_GPIO115 = 115, + PCR_ETPUA2_ETPUA14_GPIO116 = 116, + PCR_ETPUA3_ETPUA15_GPIO117 = 117, + PCR_ETPUA4_ETPUA16_GPIO118 = 118, + PCR_ETPUA5_ETPUA17_GPIO119 = 119, + PCR_ETPUA6_ETPUA18_GPIO120 = 120, + PCR_ETPUA7_ETPUA19_GPIO121 = 121, + PCR_ETPUA8_ETPUA20_GPIO122 = 122, + PCR_ETPUA9_ETPUA21_GPIO123 = 123, + PCR_ETPUA10_ETPUA22_GPIO124 = 124, + PCR_ETPUA11_ETPUA23_GPIO125 = 125, + PCR_ETPUA12_PCSB1_GPIO126 = 126, + PCR_ETPUA13_PCSB3_GPIO127 = 127, + PCR_ETPUA14_PCSB4_GPIO128 = 128, + PCR_ETPUA15_PCSB5_GPIO129 = 129, + PCR_ETPUA16_PCSD1_GPIO130 = 130, + PCR_ETPUA17_PCSD2_GPIO131 = 131, + PCR_ETPUA18_PCSD3_GPIO132 = 132, + PCR_ETPUA19_PCSD4_GPIO133 = 133, + PCR_ETPUA20_IRQ8_GPIO134 = 134, + PCR_ETPUA21_IRQ9_GPIO135 = 135, + PCR_ETPUA22_IRQ10_GPIO136 = 136, + PCR_ETPUA23_IRQ11_GPIO137 = 137, + PCR_ETPUA24_IRQ12_GPIO138 = 138, + PCR_ETPUA25_IRQ13_GPIO139 = 139, + PCR_ETPUA26_IRQ14_GPIO140 = 140, + PCR_ETPUA27_IRQ15_GPIO141 = 141, + PCR_ETPUA28_PCSC1_GPIO142 = 142, + PCR_ETPUA29_PCSC2_GPIO143 = 143, + PCR_ETPUA30_PCSC3_GPIO144 = 144, + PCR_ETPUA31_PCSC4_GPIO145 = 145, + PCR_TCRCLKB_IRQ6_GPIO146 = 146, + PCR_ETPUB0_ETPUB16_GPIO147 = 147, + PCR_ETPUB1_ETPUB17_GPIO148 = 148, + PCR_ETPUB2_ETPUB18_GPIO149 = 149, + PCR_ETPUB3_ETPUB19_GPIO150 = 150, + PCR_ETPUB4_ETPUB20_GPIO151 = 151, + PCR_ETPUB5_ETPUB21_GPIO152 = 152, + PCR_ETPUB6_ETPUB22_GPIO153 = 153, + PCR_ETPUB7_ETPUB23_GPIO154 = 154, + PCR_ETPUB8_ETPUB24_GPIO155 = 155, + PCR_ETPUB9_ETPUB25_GPIO156 = 156, + PCR_ETPUB10_ETPUB26_GPIO157 = 157, + PCR_ETPUB11_ETPUB27_GPIO158 = 158, + PCR_ETPUB12_ETPUB28_GPIO159 = 159, + PCR_ETPUB13_ETPUB29_GPIO160 = 160, + PCR_ETPUB14_ETPUB30_GPIO161 = 161, + PCR_ETPUB15_ETPUB31_GPIO162 = 162, + PCR_ETPUB16_PCSA1_GPIO163 = 163, + PCR_ETPUB17_PCSA2_GPIO164 = 164, + PCR_ETPUB18_PCSA3_GPIO165 = 165, + PCR_ETPUB19_PCSA4_GPIO166 = 166, + PCR_ETPUB20_GPIO167 = 167, + PCR_ETPUB21_GPIO168 = 168, + PCR_ETPUB22_GPIO169 = 169, + PCR_ETPUB23_GPIO170 = 170, + PCR_ETPUB24_GPIO171 = 171, + PCR_ETPUB25_GPIO172 = 172, + PCR_ETPUB26_GPIO173 = 173, + PCR_ETPUB27_GPIO174 = 174, + PCR_ETPUB28_GPIO175 = 175, + PCR_ETPUB29_GPIO176 = 176, + PCR_ETPUB30_GPIO177 = 177, + PCR_ETPUB31_GPIO178 = 178, + PCR_EMIOS0_ETPUA0_GPIO179 = 179, + PCR_EMIOS1_ETPUA1_GPIO180 = 180, + PCR_EMIOS2_ETPUA2_GPIO181 = 181, + PCR_EMIOS3_ETPUA3_GPIO182 = 182, + PCR_EMIOS4_ETPUA4_GPIO183 = 183, + PCR_EMIOS5_ETPUA5_GPIO184 = 184, + PCR_EMIOS6_ETPUA6_GPIO185 = 185, + PCR_EMIOS7_ETPUA7_GPIO186 = 186, + PCR_EMIOS8_ETPUA8_GPIO187 = 187, + PCR_EMIOS9_ETPUA9_GPIO188 = 188, + PCR_EMIOS10_SCKD_GPIO189 = 189, + PCR_EMIOS11_SIND_GPIO190 = 190, + PCR_EMIOS12_SOUTC_GPIO191 = 191, + PCR_EMIOS13_SOUTD_GPIO192 = 192, + PCR_EMIOS14_IRQ0_GPIO193 = 193, + PCR_EMIOS15_IRQ1_GPIO194 = 194, + PCR_EMIOS16_ETPUB0_GPIO195 = 195, + PCR_EMIOS17_ETPUB1_GPIO196 = 196, + PCR_EMIOS18_ETPUB2_GPIO197 = 197, + PCR_EMIOS19_ETPUB3_GPIO198 = 198, + PCR_EMIOS20_ETPUB4_GPIO199 = 199, + PCR_EMIOS21_ETPUB5_GPIO200 = 200, + PCR_EMIOS22_ETPUB6_GPIO201 = 201, + PCR_EMIOS23_ETPUB7_GPIO202 = 202, + PCR_EMIOS24_PCSB0_GPIO203 = 203, + PCR_EMIOS25_PCSB1_GPIO204 = 204, + PCR_PLLCFG0_IRQ4_GPIO208 = 208, + PCR_PLLCFG1_IRQ5_GPIO209 = 209, + PCR_BOOTCFG0_IRQ2_GPIO211 = 211, + PCR_BOOTCFG1_IRQ3_GPIO212 = 212, + PCR_WKPCFG_NMI_GPIO213 = 213, + PCR_ENGCLK = 214, + PCR_MCKO = 219, + PCR_MDO0_GPIO220 = 220, + PCR_MDO1_GPIO221 = 221, + PCR_MDO2_GPIO222 = 222, + PCR_MDO3_GPIO223 = 223, + PCR_MSEO0 = 224, + PCR_MSEO1 = 225, + PCR_RDY = 226, + PCR_TDO = 228, + PCR_D_CLKOUT = 229, + PCR_RSTOUT = 230, + PCR_MDO12_GPIO231 = 231, + PCR_MDO13_GPIO232 = 232, + PCR_MDO14_GPIO233 = 233, + PCR_MDO15_GPIO234 = 234, + PCR_SCKC_SCK_C_LVDSP_GPIO235 = 235, + PCR_SINC_SCK_C_LVDSM_GPIO236 = 236, + PCR_SOUTC_SOUT_C_LVDSP_GPIO237 = 237, + PCR_PCSC0_SOUT_C_LVDSM_GPIO238 = 238, + PCR_PCSC1_GPIO239 = 239, + PCR_PCSC2_GPIO240 = 240, + PCR_PCSC3_GPIO241 = 241, + PCR_PCSC4_GPIO242 = 242, + PCR_PCSC5_GPIO243 = 243, + PCR_TXDC_ETRIG0_GPIO244 = 244, + PCR_RXDC_GPIO245 = 245, + PCR_CNTXD_GPIO246 = 246, + PCR_CNRXD_GPIO247 = 247, + PCR_FR_A_TX_GPIO248 = 248, + PCR_FR_A_RX_GPIO249 = 249, + PCR_FR_A_TX_EN_GPIO250 = 250, + PCR_FR_B_TX_GPIO251 = 251, + PCR_FR_B_RX_GPIO252 = 252, + PCR_FR_B_TX_EN_GPIO253 = 253, + PCR_D_CS0_GPIO256 = 256, + PCR_D_CS2_D_ADD_DAT31_GPIO257 = 257, + PCR_D_CS3_D_TEA_GPIO258 = 258, + PCR_D_ADD12_GPIO259 = 259, + PCR_D_ADD13_GPIO260 = 260, + PCR_D_ADD14_GPIO261 = 261, + PCR_D_ADD15_GPIO262 = 262, + PCR_D_ADD16_D_ADD_DAT16_GPIO263 = 263, + PCR_D_ADD17_D_ADD_DAT17_GPIO264 = 264, + PCR_D_ADD18_D_ADD_DAT18_GPIO265 = 265, + PCR_D_ADD19_D_ADD_DAT19_GPIO266 = 266, + PCR_D_ADD20_D_ADD_DAT20_GPIO267 = 267, + PCR_D_ADD21_D_ADD_DAT21_GPIO268 = 268, + PCR_D_ADD22_D_ADD_DAT22_GPIO269 = 269, + PCR_D_ADD23_D_ADD_DAT23_GPIO270 = 270, + PCR_D_ADD24_D_ADD_DAT24_GPIO271 = 271, + PCR_D_ADD25_D_ADD_DAT25_GPIO272 = 272, + PCR_D_ADD26_D_ADD_DAT26_GPIO273 = 273, + PCR_D_ADD27_D_ADD_DAT27_GPIO274 = 274, + PCR_D_ADD28_D_ADD_DAT28_GPIO275 = 275, + PCR_D_ADD29_D_ADD_DAT29_GPIO276 = 276, + PCR_D_ADD30_D_ADD_DAT30_GPIO277 = 277, + PCR_D_ADD_DAT0_GPIO278 = 278, + PCR_D_ADD_DAT1_GPIO279 = 279, + PCR_D_ADD_DAT2_GPIO280 = 280, + PCR_D_ADD_DAT3_GPIO281 = 281, + PCR_D_ADD_DAT4_GPIO282 = 282, + PCR_D_ADD_DAT5_GPIO283 = 283, + PCR_D_ADD_DAT6_GPIO284 = 284, + PCR_D_ADD_DAT7_GPIO285 = 285, + PCR_D_ADD_DAT8_GPIO286 = 286, + PCR_D_ADD_DAT9_GPIO287 = 287, + PCR_D_ADD_DAT10_GPIO288 = 288, + PCR_D_ADD_DAT11_GPIO289 = 289, + PCR_D_ADD_DAT12_GPIO290 = 290, + PCR_D_ADD_DAT13_GPIO291 = 291, + PCR_D_ADD_DAT14_GPIO292 = 292, + PCR_D_ADD_DAT15_GPIO293 = 293, + PCR_D_RD_WR_GPIO294 = 294, + PCR_D_WE0_GPIO295 = 295, + PCR_D_WE1_GPIO296 = 296, + PCR_D_OE_GPIO297 = 297, + PCR_D_TS_GPIO298 = 298, + PCR_D_ALE_GPIO299 = 299, + PCR_D_TA_GPIO300 = 300, + PCR_D_CS1_GPIO301 = 301, + PCR_D_BDIP_GPIO302 = 302, + PCR_D_WE2_GPIO303 = 303, + PCR_D_WE3_GPIO304 = 304, + PCR_D_ADD9_GPIO305 = 305, + PCR_D_ADD10_GPIO306 = 306, + PCR_D_ADD11_GPIO307 = 307, + PCR_EMIOS26_PCSB2_GPIO432 = 432, + PCR_EMIOS27_PCSB3_GPIO433 = 433, + PCR_EMIOS28_PCSC0_GPIO434 = 434, + PCR_EMIOS29_PCSC1_GPIO435 = 435, + PCR_EMIOS30_PCSC2_GPIO436 = 436, + PCR_EMIOS31_PCSC5_GPIO437 = 437, + PCR_TCRCLKC_GPIO440 = 440, + PCR_ETPUC0_GPIO441 = 441, + PCR_ETPUC1_GPIO442 = 442, + PCR_ETPUC2_GPIO443 = 443, + PCR_ETPUC3_GPIO444 = 444, + PCR_ETPUC4_GPIO445 = 445, + PCR_ETPUC5_GPIO446 = 446, + PCR_ETPUC6_GPIO447 = 447, + PCR_ETPUC7_GPIO448 = 448, + PCR_ETPUC8_GPIO449 = 449, + PCR_ETPUC9_IRQ0_GPIO450 = 450, + PCR_ETPUC10__IRQ1_GPIO451 = 451, + PCR_ETPUC11_IRQ2_GPIO452 = 452, + PCR_ETPUC12_IRQ3_GPIO453 = 453, + PCR_ETPUC13_3_IRQ4_GPIO454 = 454, + PCR_ETPUC14_4_IRQ5_GPIO455 = 455, + PCR_ETPUC15__GPIO456 = 456, + PCR_ETPUC16_FR_A_TX_GPIO457 = 457, + PCR_ETPUC17_FR_A_RX_GPIO458 = 458, + PCR_ETPUC18_FR_A_TX_EN_GPIO459 = 459, + PCR_ETPUC19_TXDA_GPIO460 = 460, + PCR_ETPUC20_RXDA_GPIO461 = 461, + PCR_ETPUC21_TXDB_GPIO462 = 462, + PCR_ETPUC22_RXDB_GPIO463 = 463, + PCR_ETPUC23_PCSD5_GPIO464 = 464, + PCR_ETPUC24_PCSD4_GPIO465 = 465, + PCR_ETPUC25_PCSD3_GPIO466 = 466, + PCR_ETPUC26_PCSD2_GPIO467 = 467, + PCR_ETPUC27_PCSD1_GPIO468 = 468, + PCR_ETPUC28_PCSD0_GPIO469 = 469, + PCR_ETPUC29_SCKD_GPIO470 = 470, + PCR_ETPUC30_SOUTD_GPIO471 = 471, + PCR_ETPUC31_SIND_GPIO472 = 472 + #else + PCR_TODO + #endif +} pcr_index; + +typedef struct mpc55xx_siu_pcr_entry { + uint16_t pcr_idx; /* first PCR index for this entry */ + uint16_t pcr_cnt; /* PCR count using this entry */ + union SIU_PCR_tag pcr_val; /* value to write to the PCR[idx++val] */ +} mpc55xx_siu_pcr_entry_t; + +rtems_status_code mpc55xx_siu_pcr_init(volatile struct SIU_tag *siu, + const mpc55xx_siu_pcr_entry_t *pcr_entry); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_SIU_H */ diff --git a/bsps/powerpc/include/mpc55xx/watchdog.h b/bsps/powerpc/include/mpc55xx/watchdog.h new file mode 100644 index 0000000000..d5a8af794e --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/watchdog.h @@ -0,0 +1,68 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Header file for the watchdog timer. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_WATCHDOG_H +#define LIBCPU_POWERPC_MPC55XX_WATCHDOG_H + +#include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +static inline void mpc55xx_watchdog_clear() +{ + PPC_SET_SPECIAL_PURPOSE_REGISTER( BOOKE_TSR, BOOKE_TSR_WIS); +} + +static inline void mpc55xx_watchdog_enable_interrupt( bool enable) +{ + if (enable) { + PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( BOOKE_TCR, BOOKE_TCR_WIE); + } else { + PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( BOOKE_TCR, BOOKE_TCR_WIE); + } +} + +static inline rtems_status_code mpc55xx_watchdog_set_time_base_bit( uint32_t bit) +{ + if (bit > 63) { + return RTEMS_INVALID_NUMBER; + } + + PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED( + BOOKE_TCR, + BOOKE_TCR_WP( bit) | BOOKE_TCR_WPEXT( bit >> 2), + BOOKE_TCR_WP_MASK | BOOKE_TCR_WPEXT_MASK + ); + + return RTEMS_SUCCESSFUL; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_WATCHDOG_H */ diff --git a/bsps/powerpc/include/mpc5xx.h b/bsps/powerpc/include/mpc5xx.h new file mode 100644 index 0000000000..fc9b756cbf --- /dev/null +++ b/bsps/powerpc/include/mpc5xx.h @@ -0,0 +1,626 @@ +/* + * + * MPC5xx Internal I/O Definitions + */ + +/* + * MPC5xx port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h: + * + * Submitted By: * + * * + * W. Eric Norum * + * Saskatchewan Accelerator Laboratory * + * University of Saskatchewan * + * 107 North Road * + * Saskatoon, Saskatchewan, CANADA * + * S7N 5C6 * + * * + * eric@skatter.usask.ca * + * * + * Modified for use with the MPC860 (original code was for MC68360) * + * by * + * Jay Monkman * + * Frasca International, Inc. * + * 906 E. Airport Rd. * + * Urbana, IL, 61801 * + * * + * jmonkman@frasca.com * + * * + * Modified further for use with the MPC821 by: * + * Andrew Bray * + * * + * With some corrections/additions by: * + * Darlene A. Stewart and * + * Charles-Antoine Gauthier * + * Institute for Information Technology * + * National Research Council of Canada * + * Ottawa, ON K1A 0R6 * + * * + * Darlene.Stewart@iit.nrc.ca * + * charles.gauthier@iit.nrc.ca * + * * + * Corrections/additions: * + * Copyright (c) 1999, National Research Council of Canada * + * + * MPC5xx port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MPC5XX_H +#define _MPC5XX_H + +#include + + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Macros for accessing Special Purpose Registers (SPRs) + */ + +#define _eieio __asm__ volatile ("eieio\n"::) +#define _sync __asm__ volatile ("sync\n"::) +#define _isync __asm__ volatile ("isync\n"::) + +/* + * Core Registers (SPRs) + */ +#define DER 149 /* Debug Enable Register */ +#define IMMR 638 /* Internal Memory Map Register */ +#define IMMR_FLEN (1<<11) /* Internal flash ROM enabled */ + +/* + * Interrupt Control Registers (SPRs) + */ +#define EIE 80 /* External Interrupt Enable Register */ +#define EID 81 /* External Interrupt Disable Register */ +#define NRI 82 /* Non-Recoverable Interrupt Register */ + +#define ECR 148 /* Exception Cause Register */ + +/* + * Bus Control Registers (SPRs) + */ +#define LCTRL1 156 /* L-Bus Support Control Register 1 */ +#define LCTRL2 157 /* L-Bus Support Control Register 2 */ +#define ICTRL 158 /* I-Bus Support Control Register */ + +/* + * Burst Buffer Control Registers (SPRs) + */ +#define BBCMCR 560 /* Burst Buffer Configuration Register */ +#define BBCMCR_BE (1<<13) /* Burst enable */ +#define BBCMCR_ETRE (1<<12) /* Exception table relocation enable */ + +#define MI_RBA0 784 /* Region 0 Address Register */ +#define MI_RBA1 785 /* Region 1 Address Register */ +#define MI_RBA2 786 /* Region 2 Address Register */ +#define MI_RBA3 787 /* Region 3 Address Register */ + +#define MI_RA0 816 /* Region 0 Attribute Register */ +#define MI_RA1 817 /* Region 1 Attribute Register */ +#define MI_RA2 818 /* Region 2 Attribute Register */ +#define MI_RA3 819 /* Region 3 Attribute Register */ +#define MI_GRA 528 /* Region Global Attribute Register */ +#define MI_RA_PP (3 << 10) /* Protection bits: */ +#define MI_RA_PP_SUPV (1 << 10) /* Supervisor */ +#define MI_RA_PP_USER (2 << 10) /* User */ +#define MI_RA_G (1 << 6) /* Guarded region */ + + +/* + * L-Bus to U-Bus Interface (L2U) Registers (SPRs) + */ +#define L2U_MCR 568 /* L2U Module Configuration Register */ + +#define L2U_RBA0 792 /* L2U Region 0 Address Register */ +#define L2U_RBA1 793 /* L2U Region 1 Address Register */ +#define L2U_RBA2 794 /* L2U Region 2 Address Register */ +#define L2U_RBA3 795 /* L2U Region 3 Address Register */ + +#define L2U_RA0 824 /* L2U Region 0 Attribute Register */ +#define L2U_RA1 825 /* L2U Region 1 Attribute Register */ +#define L2U_RA2 826 /* L2U Region 2 Attribute Register */ +#define L2U_RA3 827 /* L2U Region 3 Attribute Register */ +#define L2U_GRA 536 /* L2U Global Region Attribute Register */ +#define L2U_RA_PP (3 << 10) /* Protection bits: */ +#define L2U_RA_PP_SUPV (1 << 10) /* Supervisor */ +#define L2U_RA_PP_USER (2 << 10) /* User */ +#define L2U_RA_G (1 << 6) /* Guarded region */ + + +/* + ************************************************************************* + * REGISTER SUBBLOCKS * + ************************************************************************* + */ + +/* + ************************************************************************* + * System Protection Control Register (SYPCR) * + ************************************************************************* + */ +#define USIU_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ +#define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ +#define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */ +#define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */ +#define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */ +#define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ +#define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */ + +#define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ +#define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */ +#define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */ +#define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */ +#define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ +#define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */ + +/* + ************************************************************************* + * Software Service Register (SWSR) * + ************************************************************************* + */ +#define TICKLE_WATCHDOG() \ +do { \ + usiu.swsr = 0x556C; \ + usiu.swsr = 0xAA39; \ +} while (0) \ + +/* + ************************************************************************* + * Memory Control Registers * + ************************************************************************* + */ +#define USIU_MEMC_BR_BA(x) (((uint32_t)x)&0xffff8000) + /* Base address */ +#define USIU_MEMC_BR_AT(x) ((x)<<12) /* Address type */ +#define USIU_MEMC_BR_PS8 (1<<10) /* 8 bit port */ +#define USIU_MEMC_BR_PS16 (2<<10) /* 16 bit port */ +#define USIU_MEMC_BR_PS32 (0<<10) /* 32 bit port */ +#define USIU_MEMC_BR_WP (1<<8) /* Write protect */ +#define USIU_MEMC_BR_WEBS (1<<5) /* Write enable/byte select */ +#define USIU_MEMC_BR_TBDIP (1<<4) /* Toggle-Burst data in progress*/ +#define USIU_MEMC_BR_LBDIP (1<<3) /* Late-burst data in progress */ +#define USIU_MEMC_BR_SETA (1<<2) /* External transfer acknowledge */ +#define USIU_MEMC_BR_BI (1<<1) /* Burst inhibit */ +#define USIU_MEMC_BR_V (1<<0) /* Base/Option register are valid */ + +#define USIU_MEMC_OR_32K 0xffff8000 /* Address range */ +#define USIU_MEMC_OR_64K 0xffff0000 +#define USIU_MEMC_OR_128K 0xfffe0000 +#define USIU_MEMC_OR_256K 0xfffc0000 +#define USIU_MEMC_OR_512K 0xfff80000 +#define USIU_MEMC_OR_1M 0xfff00000 +#define USIU_MEMC_OR_2M 0xffe00000 +#define USIU_MEMC_OR_4M 0xffc00000 +#define USIU_MEMC_OR_8M 0xff800000 +#define USIU_MEMC_OR_16M 0xff000000 +#define USIU_MEMC_OR_32M 0xfe000000 +#define USIU_MEMC_OR_64M 0xfc000000 +#define USIU_MEMC_OR_128 0xf8000000 +#define USIU_MEMC_OR_256M 0xf0000000 +#define USIU_MEMC_OR_512M 0xe0000000 +#define USIU_MEMC_OR_1G 0xc0000000 +#define USIU_MEMC_OR_2G 0x80000000 +#define USIU_MEMC_OR_4G 0x00000000 +#define USIU_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ +#define USIU_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ +#define USIU_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ +#define USIU_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ +#define USIU_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ +#define USIU_MEMC_OR_ETHR (1<<8) /* Extended hold time on reads */ +#define USIU_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ +#define USIU_MEMC_OR_BSCY(x) ((x)<<1) /* Burst beat length in clocks */ +#define USIU_MEMC_OR_TRLX (1<<0) /* Relaxed timing in GPCM */ + +/* + ************************************************************************* + * Clocks and Reset Controlmer * + ************************************************************************* + */ + +#define USIU_SCCR_DBCT (1<<31) /* Disable backup clock for timers */ +#define USIU_SCCR_COM(x) ((x)<<29) /* Clock output mode */ +#define USIU_SCCR_RTDIV (1<<24) /* RTC, PIT divide by 256, not 4 */ +#define USIU_PRQEN (1<<21) /* MSR[POW] controls frequency */ +#define USIU_SCCR_EBDF(x) ((x)<<17) /* External bus division factor */ +#define USIU_LME (1<<16) /* Enable limp mode */ +#define USIU_ENGDIV(x) ((x)<<9) /* Set engineering clock divisor */ + +#define USIU_PLPRCR_MF(x) (((x)-1)<<20) /* PLL mult. factor (true) */ +#define USIU_PLPRCR_SPLS (1<<16) /* System PLL locked */ +#define USIU_PLPRCR_TEXPS (1<<14) /* Assert TEXP always */ + +/* + ************************************************************************* + * Programmable Interval Timer * + ************************************************************************* + */ +#define USIU_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ +#define USIU_PISCR_PS (1<<7) /* PIT Interrupt state */ +#define USIU_PISCR_PIE (1<<2) /* PIT interrupt enable */ +#define USIU_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ +#define USIU_PISCR_PTE (1<<0) /* PIT enable */ + +/* + ************************************************************************* + * Time Base * + ************************************************************************* + */ +#define USIU_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ +#define USIU_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ +#define USIU_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ +#define USIU_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ +#define USIU_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ +#define USIU_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ +#define USIU_TBSCR_TBE (1<<0) /* enable TB and decrementer */ + +/* + ************************************************************************* + * SIU Interrupt Mask * + ************************************************************************* + */ +#define USIU_SIMASK_IRM0 (1<<31) +#define USIU_SIMASK_LVM0 (1<<30) +#define USIU_SIMASK_IRM1 (1<<29) +#define USIU_SIMASK_LVM1 (1<<28) +#define USIU_SIMASK_IRM2 (1<<27) +#define USIU_SIMASK_LVM2 (1<<26) +#define USIU_SIMASK_IRM3 (1<<25) +#define USIU_SIMASK_LVM3 (1<<24) +#define USIU_SIMASK_IRM4 (1<<23) +#define USIU_SIMASK_LVM4 (1<<22) +#define USIU_SIMASK_IRM5 (1<<21) +#define USIU_SIMASK_LVM5 (1<<20) +#define USIU_SIMASK_IRM6 (1<<19) +#define USIU_SIMASK_LVM6 (1<<18) +#define USIU_SIMASK_IRM7 (1<<17) +#define USIU_SIMASK_LVM7 (1<<16) + +/* + ************************************************************************* + * SIU Module Control * + ************************************************************************* + */ +#define USIU_SIUMCR_EARB (1<<31) +#define USIU_SIUMCR_EARP0 (0<<28) +#define USIU_SIUMCR_EARP1 (1<<28) +#define USIU_SIUMCR_EARP2 (2<<28) +#define USIU_SIUMCR_EARP3 (3<<28) +#define USIU_SIUMCR_EARP4 (4<<28) +#define USIU_SIUMCR_EARP5 (5<<28) +#define USIU_SIUMCR_EARP6 (6<<28) +#define USIU_SIUMCR_EARP7 (7<<28) +#define USIU_SIUMCR_DSHW (1<<23) +#define USIU_SIUMCR_DBGC0 (0<<21) +#define USIU_SIUMCR_DBGC1 (1<<21) +#define USIU_SIUMCR_DBGC2 (2<<21) +#define USIU_SIUMCR_DBGC3 (3<<21) +#define USIU_SIUMCR_DBPC (1<<20) +#define USIU_SIUMCR_ATWC (1<<19) +#define USIU_SIUMCR_GPC0 (0<<17) +#define USIU_SIUMCR_GPC1 (1<<17) +#define USIU_SIUMCR_GPC2 (2<<17) +#define USIU_SIUMCR_GPC3 (3<<17) +#define USIU_SIUMCR_DLK (1<<16) +#define USIU_SIUMCR_SC0 (0<<13) +#define USIU_SIUMCR_SC1 (1<<13) +#define USIU_SIUMCR_SC2 (2<<13) +#define USIU_SIUMCR_SC3 (3<<13) +#define USIU_SIUMCR_RCTX (1<<12) +#define USIU_SIUMCR_MLRC0 (0<<10) +#define USIU_SIUMCR_MLRC1 (1<<10) +#define USIU_SIUMCR_MLRC2 (2<<10) +#define USIU_SIUMCR_MLRC3 (3<<10) +#define USIU_SIUMCR_MTSC (1<<7) + +/* + * Value to write to a key register to unlock the corresponding SIU register + */ +#define USIU_UNLOCK_KEY 0x55CCAA33 + +/* + ************************************************************************* + * UIMB Module Control * + ************************************************************************* + */ +#define UIMB_UMCR_STOP (1<<31) +#define UIMB_UMCR_IRQMUX(x) ((x)<<29) +#define UIMB_UMCR_HSPEED (1<<28) + +/* + ************************************************************************* + * QSMCM Serial Communications Interface (SCI) * + ************************************************************************* + */ + + +#define QSMCM_ILDSCI(x) ((x)<<8) /* SCI interrupt level */ + +#define QSMCM_SCI_BAUD(x) ((x)&0x1FFF) /* Baud rate field */ + +#define QSMCM_SCI_LOOPS (1<<14) /* Loopback test mode */ +#define QSMCM_SCI_WOMS (1<<13) /* Wire-or mode select */ +#define QSMCM_SCI_ILT (1<<12) /* Idle-line detect type */ +#define QSMCM_SCI_PT (1<<11) /* Parity type */ +#define QSMCM_SCI_PE (1<<10) /* Parity enable */ +#define QSMCM_SCI_M (1<<9) /* 11-bit mode */ +#define QSMCM_SCI_WAKE (1<<8) /* Wakeup mode */ + +#define QSMCM_SCI_TIE (1<<7) /* Transmitter interrupt enable */ +#define QSMCM_SCI_TCIE (1<<6) /* Transmit complete intr. enable */ +#define QSMCM_SCI_RIE (1<<5) /* Receiver interrupt enable */ +#define QSMCM_SCI_ILIE (1<<4) /* Idle line interrupt enable */ +#define QSMCM_SCI_TE (1<<3) /* Transmitter enable */ +#define QSMCM_SCI_RE (1<<2) /* Receiver enable */ +#define QSMCM_SCI_RWU (1<<1) /* Receiver wake-up enable */ +#define QSMCM_SCI_SBK (1<<0) /* Send break */ + +#define QSMCM_SCI_TDRE (1<<8) /* Transmit data register empty */ +#define QSMCM_SCI_TC (1<<7) /* Transmit complete */ +#define QSMCM_SCI_RDRF (1<<6) /* Receive data register full */ +#define QSMCM_SCI_RAF (1<<5) /* Receiver active flag */ +#define QSMCM_SCI_IDLE (1<<4) /* Idle line detected */ +#define QSMCM_SCI_OR (1<<3) /* Receiver overrun error */ +#define QSMCM_SCI_NF (1<<2) /* Receiver noise error flag */ +#define QSMCM_SCI_FE (1<<1) /* Receiver framing error */ +#define QSMCM_SCI_PF (1<<0) /* Receiver parity error */ + +/* + ************************************************************************* + * Unified System Interface Unit * + ************************************************************************* + */ + +/* + * Memory controller registers + */ +typedef struct m5xxMEMCRegisters_ { + uint32_t _br; + uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */ +} m5xxMEMCRegisters_t; + +/* + * USIU itself + */ +typedef struct usiu_ { + /* + * SIU Block + */ + uint32_t siumcr; + uint32_t sypcr; + uint32_t _pad70; + uint16_t _pad0; + uint16_t swsr; + uint32_t sipend; + uint32_t simask; + uint32_t siel; + uint32_t sivec; + uint32_t tesr; + uint32_t sgpiodt1; + uint32_t sgpiodt2; + uint32_t sgpiocr; + uint32_t emcr; + uint8_t _pad71[0x03C-0x034]; + uint32_t pdmcr; + uint8_t _pad2[0x100-0x40]; + + /* + * MEMC Block + */ + m5xxMEMCRegisters_t memc[4]; + uint8_t _pad7[0x140-0x120]; + uint32_t dmbr; + uint32_t dmor; + uint8_t _pad8[0x178-0x148]; + uint16_t mstat; + uint8_t _pad9[0x200-0x17A]; + + /* + * System integration timers + */ + uint16_t tbscr; + uint16_t _pad10; + uint32_t tbreff0; + uint32_t tbreff1; + uint8_t _pad11[0x220-0x20c]; + uint16_t rtcsc; + uint16_t _pad12; + uint32_t rtc; + uint32_t rtsec; + uint32_t rtcal; + uint32_t _pad13[4]; + uint16_t piscr; + uint16_t _pad14; + uint16_t pitc; + uint16_t _pad_14_1; + uint16_t pitr; + uint16_t _pad_14_2; + uint8_t _pad15[0x280-0x24c]; + + /* + * Clocks and Reset + */ + uint32_t sccr; + uint32_t plprcr; + uint16_t rsr; + uint16_t _pad72; + uint16_t colir; + uint16_t _pad73; + uint16_t vsrmcr; + uint8_t _pad16[0x300-0x292]; + + /* + * System integration timers keys + */ + uint32_t tbscrk; + uint32_t tbreff0k; + uint32_t tbreff1k; + uint32_t tbk; + uint32_t _pad17[4]; + uint32_t rtcsk; + uint32_t rtck; + uint32_t rtseck; + uint32_t rtcalk; + uint32_t _pad18[4]; + uint32_t piscrk; + uint32_t pitck; + uint8_t _pad19[0x380-0x348]; + + /* + * Clocks and Reset Keys + */ + uint32_t sccrk; + uint32_t plprck; + uint32_t rsrk; + uint8_t _pad20[0x400-0x38c]; +} usiu_t; + +extern volatile usiu_t usiu; /* defined in linkcmds */ + +/* + ************************************************************************* + * Inter-Module Bus and Devices * + ************************************************************************* + */ + +/* + * Dual-Port TPU RAM (DPTRAM) + */ +typedef struct m5xxDPTRAMRegisters_ { + uint8_t pad[0x4000]; /* define later */ +} m5xxDPTRAMRegisters_t; + +/* + * Time Processor Unit (TPU) + */ +typedef struct m5xxTPU3Registers_ { + uint8_t pad[0x400]; /* define later */ +} m5xxTPU3Registers_t; + +/* + * Queued A/D Converter (QADC) + */ +typedef struct m5xxQADC64Registers_ { + uint8_t pad[0x400]; /* define later */ +} m5xxQADC64Registers_t; + +/* + * Serial Communications Interface (SCI) + */ +typedef struct m5xxSCIRegisters_ { + uint16_t sccr0; + uint16_t sccr1; + uint16_t scsr; + uint16_t scdr; +} m5xxSCIRegisters_t; + +/* + * Serial Peripheral Interface (SPI) + */ +typedef struct m5xxSPIRegisters_ { + uint16_t spcr0; + uint16_t spcr1; + uint16_t spcr2; + uint8_t spcr3; + uint8_t spsr; +} m5xxSPIRegisters_t; + +/* + * Queued Serial Multi-Channel Module (QSMCM) + */ +typedef struct m5xxQSMCMRegisters_ { + uint16_t qsmcmmcr; + uint16_t qtest; + uint16_t qdsci_il; + uint16_t qspi_il; + + m5xxSCIRegisters_t sci1; + + uint8_t _pad10[0x14-0x10]; + + uint16_t portqs; + uint16_t pqspar; + m5xxSPIRegisters_t spi; + + m5xxSCIRegisters_t sci2; + + uint16_t qsci1cr; + uint16_t qsci1sr; + uint16_t sctq[0x10]; + uint16_t scrq[0x10]; + + uint8_t _pad6C[0x140-0x06C]; + + uint16_t recram[0x20]; + uint16_t tranram[0x20]; + uint16_t comdram[0x20]; +} m5xxQSMCMRegisters_t; + +/* + * Modular Input/Output System (MIOS) + */ +typedef struct m5xxMIOS1Registers_ { + uint8_t pad[0x1000]; /* define later */ +} m5xxMIOS1Registers_t; + +/* + * Can 2.0B Controller (TouCAN) + */ +typedef struct m5xxTouCANRegisters_ { + uint8_t pad[0x400]; /* define later */ +} m5xxTouCANRegisters_t; + +/* + * U-Bus to IMB3 Bus Interface Module (UIMB) + */ +typedef struct m5xxUIMBRegisters_ { + uint32_t umcr; + uint32_t utstcreg; + uint32_t uipend; +} m5xxUIMBRegisters_t; + +/* + * IMB itself + */ +typedef struct imb_ { + m5xxDPTRAMRegisters_t dptram; + m5xxTPU3Registers_t tpu[2]; + m5xxQADC64Registers_t qadc[2]; + m5xxQSMCMRegisters_t qsmcm; + uint8_t _pad5200[0x6000-0x5200]; + m5xxMIOS1Registers_t mios; + m5xxTouCANRegisters_t toucan[2]; + uint8_t _pad7800[0x7F80-0x7800]; + m5xxUIMBRegisters_t uimb; +} imb_t; + +extern volatile imb_t imb; /* defined in linkcmds */ + + +/* + * Methods shared across libcpu and the BSP. + */ +void clockOn(void* unused); +void clockOff(void* unused); +int clockIsOn(void* unused); +rtems_isr Clock_isr(rtems_vector_number vector); + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _MPC5XX_H */ diff --git a/bsps/powerpc/include/mpc5xx/console.h b/bsps/powerpc/include/mpc5xx/console.h new file mode 100644 index 0000000000..c0633af938 --- /dev/null +++ b/bsps/powerpc/include/mpc5xx/console.h @@ -0,0 +1,34 @@ +/* + * Console declarations + * + * + * MPC5xx port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MPC5XX_CONSOLE_H +#define _MPC5XX_CONSOLE_H + +#include +#include + +void m5xx_uart_initialize(int minor); + +/* Termios callbacks */ +int m5xx_uart_firstOpen(int maj, int min, void *arg); +int m5xx_uart_lastClose(int maj, int min, void *arg); +int m5xx_uart_pollRead(int minor); +ssize_t m5xx_uart_pollWrite(int minor, const char* buf, size_t len); +ssize_t m5xx_uart_write (int minor, const char *buf, size_t len); +int m5xx_uart_setAttributes(int, const struct termios* t); + +#define NUM_PORTS 2 /* number of serial ports */ + +#define SCI1_MINOR 0 +#define SCI2_MINOR 1 + +#endif /* _MPC5XX_CONSOLE_H */ diff --git a/bsps/powerpc/include/mpc8260.h b/bsps/powerpc/include/mpc8260.h new file mode 100644 index 0000000000..ea088ebae8 --- /dev/null +++ b/bsps/powerpc/include/mpc8260.h @@ -0,0 +1,1510 @@ +/* buggy version of CPU */ +#define REV_0_2 + +/* +************************************************************************** +************************************************************************** +** ** +** MOTOROLA MPC8260 POWER QUAD INTEGRATED COMMUNICATIONS CONTROLLER ** +** POWERQUICC II ** +** ** +** HARDWARE DECLARATIONS ** +** ** +** ** +** Submitted by: ** +** Andy Dachs ** ** +** Surrey Satellite Technology Limited ** ** +** http://www.sstl.co.uk ** ** +** a.dachs@sstl.co.uk ** ** +** ** +** Based on previous submissions for other PPC variants by: ** +** ** +** Submitted By: ** +** ** +** W. Eric Norum ** +** Saskatchewan Accelerator Laboratory ** +** University of Saskatchewan ** +** 107 North Road ** +** Saskatoon, Saskatchewan, CANADA ** +** S7N 5C6 ** +** ** +** eric@skatter.usask.ca ** +** ** +** Modified for use with the MPC860 (original code was for MC68360) ** +** by ** +** Jay Monkman ** +** Frasca International, Inc. ** +** 906 E. Airport Rd. ** +** Urbana, IL, 61801 ** +** ** +** jmonkman@frasca.com ** +** ** +** ** +************************************************************************** +************************************************************************** +*/ + +#ifndef _MPC8260_H +#define _MPC8260_H + +#ifndef ASM +/* + Macros for SPRs +*/ + + + + +/* +************************************************************************* +* REGISTER SUBBLOCKS * +************************************************************************* +*/ + + +/* + * Memory controller registers + */ +typedef struct m8260MEMCRegisters_ { + uint32_t br; + uint32_t _or; /* or is a C++ keyword :( */ +} m8260MEMCRegisters_t; + + +/* + * Fast Communication Controller Registers +*/ +typedef struct m8260FCCRegisters_ { + uint32_t gfmr; + uint32_t fpsmr; + uint16_t ftodr; + uint8_t fcc_pad0[2]; + uint16_t fdsr; + uint8_t fcc_pad1[2]; + uint32_t fcce; + uint32_t fccm; + uint8_t fccs; + uint8_t fcc_pad2[3]; + uint8_t ftirr_phy0; /* n/a on FCC3 */ + uint8_t ftirr_phy1; /* n/a on FCC3 */ + uint8_t ftirr_phy2; /* n/a on FCC3 */ + uint8_t ftirr_phy3; /* n/a on FCC3 */ +} m8260FCCRegisters_t; + + +/* + * Serial Communications Controller registers + */ +typedef struct m8260SCCRegisters_ { + uint32_t gsmr_l; + uint32_t gsmr_h; + uint16_t psmr; + uint8_t scc_pad0[2]; + uint16_t todr; + uint16_t dsr; + uint16_t scce; + uint8_t scc_pad2[2]; + uint16_t sccm; + uint8_t scc_pad3[1]; + uint8_t sccs; + uint8_t scc_pad1[8]; +} m8260SCCRegisters_t; + +/* + * Serial Management Controller registers + */ +typedef struct m8260SMCRegisters_ { + uint8_t smc_pad0[2]; + uint16_t smcmr; + uint8_t smc_pad2[2]; + uint8_t smce; + uint8_t smc_pad3[3]; + uint8_t smcm; + uint8_t smc_pad1[5]; +} m8260SMCRegisters_t; + + +/* + * Serial Interface With Time Slot Assigner Registers + */ +typedef struct m8260SIRegisters_ { + uint16_t siamr; + uint16_t sibmr; + uint16_t sicmr; + uint16_t sidmr; + uint8_t sigmr; + uint8_t si_pad0[1]; + uint8_t sicmdr; + uint8_t si_pad1[1]; + uint8_t sistr; + uint8_t si_pad2[1]; + uint16_t sirsr; +} m8260SIRegisters_t; + + +/* + * Multi Channel Controller registers + */ +typedef struct m8260MCCRegisters_ { + uint16_t mcce; + uint8_t mcc_pad2[2]; + uint16_t mccm; + uint16_t mcc_pad0; + uint8_t mccf; + uint8_t mcc_pad1[7]; +} m8260MCCRegisters_t; + + +/* +************************************************************************* +* RISC Timers * +************************************************************************* +*/ +/* +typedef struct m8260TimerParms_ { + uint16_t tm_base; + uint16_t _tm_ptr; + uint16_t _r_tmr; + uint16_t _r_tmv; + uint32_t tm_cmd; + uint32_t tm_cnt; +} m8260TimerParms_t; +*/ + +/* + * RISC Controller Configuration Register (RCCR) + * All other bits in this register are reserved. + */ +#define M8260_RCCR_TIME (1<<31) /* Enable timer */ +#define M8260_RCCR_TIMEP(x) ((x)<<24) /* Timer period */ +#define M8260_RCCR_DR1M (1<<23) /* IDMA Rqst 1 Mode */ +#define M8260_RCCR_DR2M (1<<22) /* IDMA Rqst 2 Mode */ +#define M8260_RCCR_DR1QP(x) ((x)<<20) /* IDMA1 Rqst Priority */ +#define M8260_RCCR_EIE (1<<19) /* External Interrupt Enable */ +#define M8260_RCCR_SCD (1<<18) /* Scheduler Configuration */ +#define M8260_RCCR_DR2QP(x) ((x)<<16) /* IDMA2 Rqst Priority */ +#define M8260_RCCR_ERAM(x) ((x)<<13) /* Enable RAM Microcode */ +#define M8260_RCCR_EDM1 (1<<11) /* DRQ1 Edge detect mode */ +#define M8260_RCCR_EDM2 (1<<10) /* DRQ2 Edge detect mode */ +#define M8260_RCCR_EDM3 (1<<9) /* DRQ3 Edge detect mode */ +#define M8260_RCCR_EDM4 (1<<8) /* DRQ4 Edge detect mode */ +#define M8260_RCCR_DR3M (1<<7) /* IDMA Rqst 1 Mode */ +#define M8260_RCCR_DR4M (1<<6) /* IDMA Rqst 2 Mode */ +#define M8260_RCCR_DR3QP(x) ((x)<<4) /* IDMA3 Rqst Priority */ +#define M8260_RCCR_DEM12 (1<<3) /* DONE1,2 Edge detect mode */ +#define M8260_RCCR_DEM34 (1<<2) /* DONE3,4 Edge detect mode */ +#define M8260_RCCR_DR4QP(x) (x) /* IDMA4 Rqst Priority */ + + + +/* + * Command register + * Set up this register before issuing a M8260_CR_OP_SET_TIMER command. + */ +#if 0 +#define M8260_TM_CMD_V (1<<31) /* Set to enable timer */ +#define M8260_TM_CMD_R (1<<30) /* Set for automatic restart */ +#define M8260_TM_CMD_PWM (1<<29) /* Set for PWM operation */ +#define M8260_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ +#define M8260_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ +#endif + +/* +************************************************************************* +* DMA Controllers * +************************************************************************* +*/ +typedef struct m8260IDMAparms_ { + uint16_t ibase; + uint16_t dcm; + uint16_t ibdptr; + uint16_t dpr_buf; + uint16_t _buf_inv; + uint16_t ssmax; + uint16_t _dpr_in_ptr; + uint16_t sts; + uint16_t _dpr_out_ptr; + uint16_t seob; + uint16_t deob; + uint16_t dts; + uint16_t _ret_add; + uint16_t reserved; + uint32_t _bd_cnt; + uint32_t _s_ptr; + uint32_t _d_ptr; + uint32_t istate; +} m8260IDMAparms_t; + + +/* +************************************************************************* +* Serial Communication Controllers * +************************************************************************* +*/ + + +typedef struct m8260SCCparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; + uint32_t _rcrc; + uint32_t _tcrc; + union { + struct { + uint32_t _res0; + uint32_t _res1; + uint16_t max_idl; + uint16_t idlc; + uint16_t brkcr; + uint16_t parec; + uint16_t frmec; + uint16_t nosec; + uint16_t brkec; + uint16_t brklen; + uint16_t uaddr[2]; + uint16_t rtemp; + uint16_t toseq; + uint16_t character[8]; + uint16_t rccm; + uint16_t rccr; + uint16_t rlbc; + } uart; + struct { + uint32_t _pad0; + uint32_t c_mask; + uint32_t c_pres; + uint16_t disfc; + uint16_t crcec; + uint16_t abtsc; + uint16_t nmarc; + uint16_t retrc; + uint16_t mflr; + uint16_t _max_cnt; + uint16_t rfthr; + uint16_t _rfcnt; + uint16_t hmask; + uint16_t haddr1; + uint16_t haddr2; + uint16_t haddr3; + uint16_t haddr4; + uint16_t _tmp; + uint16_t _tmp_mb; + } hdlc; + struct { + uint32_t _pad0; + uint32_t crcc; + uint16_t prcrc; + uint16_t ptcrc; + uint16_t parec; + uint16_t bsync; + uint16_t bdle; + uint16_t character[8]; + uint16_t rccm; + } bisync; + struct { + uint32_t _crc_p; + uint32_t _crc_c; + } transparent; + struct { + uint32_t c_pres; + uint32_t c_mask; + uint32_t crcec; + uint32_t alec; + uint32_t disfc; + uint16_t pads; + uint16_t ret_lim; + uint16_t _ret_cnt; + uint16_t mflr; + uint16_t minflr; + uint16_t maxd1; + uint16_t maxd2; + uint16_t _maxd; + uint16_t _dma_cnt; + uint16_t _max_b; + uint16_t gaddr1; + uint16_t gaddr2; + uint16_t gaddr3; + uint16_t gaddr4; + uint32_t _tbuf0data0; + uint32_t _tbuf0data1; + uint32_t _tbuf0rba0; + uint32_t _tbuf0crc; + uint16_t _tbuf0bcnt; + uint16_t paddr_h; + uint16_t paddr_m; + uint16_t paddr_l; + uint16_t p_per; + uint16_t _rfbd_ptr; + uint16_t _tfbd_ptr; + uint16_t _tlbd_ptr; + uint32_t _tbuf1data0; + uint32_t _tbuf1data1; + uint32_t _tbuf1rba0; + uint32_t _tbuf1crc; + uint16_t _tbuf1bcnt; + uint16_t _tx_len; + uint16_t iaddr1; + uint16_t iaddr2; + uint16_t iaddr3; + uint16_t iaddr4; + uint16_t _boff_cnt; + uint16_t taddr_l; + uint16_t taddr_m; + uint16_t taddr_h; + } ethernet; + } un; +} m8260SCCparms_t; + + +/* + * Event and mask registers (SCCE, SCCM) + */ +#define M8260_SCCE_BRKE (1<<6) +#define M8260_SCCE_BRK (1<<5) +#define M8260_SCCE_TXE (1<<4) +#define M8260_SCCE_RXF (1<<3) +#define M8260_SCCE_BSY (1<<2) +#define M8260_SCCE_TX (1<<1) +#define M8260_SCCE_RX (1<<0) + + +/* +************************************************************************* +* Fast Serial Communication Controllers * +************************************************************************* +*/ + + +typedef struct m8260FCCparms_ { + uint16_t riptr; + uint16_t tiptr; + uint16_t _pad0; + uint16_t mrblr; + uint32_t rstate; + uint32_t rbase; + uint16_t _rbdstat; + uint16_t _rbdlen; + uint32_t _rdptr; + uint32_t tstate; + uint32_t tbase; + uint16_t _tbdstat; + uint16_t _tbdlen; + uint32_t _tdptr; + uint32_t _rbptr; + uint32_t _tbptr; + uint32_t _rcrc; + uint32_t _pad1; + uint32_t _tcrc; + + union { + struct { + uint32_t _pad0; + uint32_t _pad1; + uint32_t c_mask; + uint32_t c_pres; + uint16_t disfc; + uint16_t crcec; + uint16_t abtsc; + uint16_t nmarc; + uint32_t _max_cnt; + uint16_t mflr; + uint16_t rfthr; + uint16_t rfcnt; + uint16_t hmask; + uint16_t haddr1; + uint16_t haddr2; + uint16_t haddr3; + uint16_t haddr4; + uint16_t _ts_tmp; + uint16_t _tmp_mb; + } hdlc; + struct { + uint32_t _pad0; + uint32_t _pad1; + uint32_t c_mask; + uint32_t c_pres; + uint16_t disfc; + uint16_t crcec; + uint16_t abtsc; + uint16_t nmarc; + uint32_t _max_cnt; + uint16_t mflr; + uint16_t rfthr; + uint16_t rfcnt; + uint16_t hmask; + uint16_t haddr1; + uint16_t haddr2; + uint16_t haddr3; + uint16_t haddr4; + uint16_t _ts_tmp; + uint16_t _tmp_mb; + } transparent; + struct { + uint32_t _stat_buf; + uint32_t cam_ptr; + uint32_t c_mask; + uint32_t c_pres; + uint32_t crcec; + uint32_t alec; + uint32_t disfc; + uint16_t ret_lim; + uint16_t _ret_cnt; + uint16_t p_per; + uint16_t _boff_cnt; + uint32_t gaddr_h; + uint32_t gaddr_l; + uint16_t tfcstat; + uint16_t tfclen; + uint32_t tfcptr; + uint16_t mflr; + uint16_t paddr1_h; + uint16_t paddr1_m; + uint16_t paddr1_l; + uint16_t _ibd_cnt; + uint16_t _ibd_start; + uint16_t _ibd_end; + uint16_t _tx_len; + uint16_t _ibd_base; + uint32_t iaddr_h; + uint32_t iaddr_l; + uint16_t minflr; + uint16_t taddr_h; + uint16_t taddr_m; + uint16_t taddr_l; + uint16_t pad_ptr; + uint16_t _pad0; + uint16_t _cf_range; + uint16_t _max_b; + uint16_t maxd1; + uint16_t maxd2; + uint16_t _maxd; + uint16_t _dma_cnt; + uint32_t octc; + uint32_t colc; + uint32_t broc; + uint32_t mulc; + uint32_t uspc; + uint32_t frgc; + uint32_t ospc; + uint32_t jbrc; + uint32_t p64c; + uint32_t p65c; + uint32_t p128c; + uint32_t p256c; + uint32_t p512c; + uint32_t p1024c; + uint32_t _cam_buf; + uint32_t _pad1; + } ethernet; + } un; +} m8260FCCparms_t; + + +/* + * Receive and transmit function code register bits + * These apply to the function code registers of all devices, not just SCC. + */ +#define M8260_RFCR_BO(x) ((x)<<3) +#define M8260_RFCR_MOT (2<<3) +#define M8260_RFCR_LOCAL_BUS (2) +#define M8260_RFCR_60X_BUS (0) +#define M8260_TFCR_BO(x) ((x)<<3) +#define M8260_TFCR_MOT (2<<3) +#define M8260_TFCR_LOCAL_BUS (2) +#define M8260_TFCR_60X_BUS (0) + +/* +************************************************************************* +* Serial Management Controllers * +************************************************************************* +*/ +typedef struct m8260SMCparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; + union { + struct { + uint16_t max_idl; + uint16_t _idlc; + uint16_t _brkln; + uint16_t brkec; + uint16_t brkcr; + uint16_t _r_mask; + } uart; + struct { + uint16_t _pad0[6]; + } transparent; + } un; + uint32_t _pad6; +} m8260SMCparms_t; + +/* + * Mode register + */ +#define M8260_SMCMR_CLEN(x) ((x)<<11) /* Character length */ +#define M8260_SMCMR_2STOP (1<<10) /* 2 stop bits */ +#define M8260_SMCMR_PARITY (1<<9) /* Enable parity */ +#define M8260_SMCMR_EVEN (1<<8) /* Even parity */ +#define M8260_SMCMR_SM_GCI (0<<4) /* GCI Mode */ +#define M8260_SMCMR_SM_UART (2<<4) /* UART Mode */ +#define M8260_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ +#define M8260_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ +#define M8260_SMCMR_DM_ECHO (2<<2) /* Echo mode */ +#define M8260_SMCMR_TEN (1<<1) /* Enable transmitter */ +#define M8260_SMCMR_REN (1<<0) /* Enable receiver */ + +/* + * Event and mask registers (SMCE, SMCM) + */ +#define M8260_SMCE_TXE (1<<4) +#define M8260_SMCE_BSY (1<<2) +#define M8260_SMCE_TX (1<<1) +#define M8260_SMCE_RX (1<<0) + +/* +************************************************************************* +* Serial Peripheral Interface * +************************************************************************* +*/ +typedef struct m8260SPIparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; +} m8260SPIparms_t; + +/* + * Mode register (SPMODE) + */ +#define M8260_SPMODE_LOOP (1<<14) /* Local loopback mode */ +#define M8260_SPMODE_CI (1<<13) /* Clock invert */ +#define M8260_SPMODE_CP (1<<12) /* Clock phase */ +#define M8260_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ +#define M8260_SPMODE_REV (1<<10) /* Reverse data */ +#define M8260_SPMODE_MASTER (1<<9) /* SPI is master */ +#define M8260_SPMODE_EN (1<<8) /* Enable SPI */ +#define M8260_SPMODE_CLEN(x) ((x)<<4) /* Character length */ +#define M8260_SPMODE_PM(x) (x) /* Prescaler modulus */ + +/* + * Mode register (SPCOM) + */ +#define M8260_SPCOM_STR (1<<7) /* Start transmit */ + +/* + * Event and mask registers (SPIE, SPIM) + */ +#define M8260_SPIE_MME (1<<5) /* Multi-master error */ +#define M8260_SPIE_TXE (1<<4) /* Tx error */ +#define M8260_SPIE_BSY (1<<2) /* Busy condition*/ +#define M8260_SPIE_TXB (1<<1) /* Tx buffer */ +#define M8260_SPIE_RXB (1<<0) /* Rx buffer */ + +/* +************************************************************************* +* SDMA (SCC, SMC, SPI) Buffer Descriptors * +************************************************************************* +*/ +typedef struct m8260BufferDescriptor_ { + uint16_t status; + uint16_t length; + volatile void *buffer; +} m8260BufferDescriptor_t; + +/* + * Bits in receive buffer descriptor status word + */ +#define M8260_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_LAST (1<<11) /* Ethernet, SPI */ +#define M8260_BD_CONTROL_CHAR (1<<11) /* SCC UART */ +#define M8260_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ +#define M8260_BD_ADDRESS (1<<10) /* SCC UART */ +#define M8260_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ +#define M8260_BD_MISS (1<<8) /* Ethernet */ +#define M8260_BD_IDLE (1<<8) /* SCC UART, SMC UART */ +#define M8260_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ +#define M8260_BD_LONG (1<<5) /* Ethernet, SCC HDLC */ +#define M8260_BD_BREAK (1<<5) /* SCC UART, SMC UART */ +#define M8260_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */ +#define M8260_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ +#define M8260_BD_SHORT (1<<3) /* Ethernet */ +#define M8260_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ +#define M8260_BD_ABORT (1<<3) /* SCC HDLC */ +#define M8260_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */ +#define M8260_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_COLLISION (1<<0) /* Ethernet */ +#define M8260_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ +#define M8260_BD_MASTER_ERROR (1<<0) /* SPI */ + +#define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */ +#define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */ +#define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ +#define M8xx_BD_ADDRESS (1<<10) /* SCC UART */ +#define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ +#define M8xx_BD_MISS (1<<8) /* Ethernet */ +#define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */ +#define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ +#define M8xx_BD_LONG (1<<5) /* Ethernet, SCC HDLC */ +#define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */ +#define M8xx_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */ +#define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ +#define M8xx_BD_SHORT (1<<3) /* Ethernet */ +#define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ +#define M8xx_BD_ABORT (1<<3) /* SCC HDLC */ +#define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */ +#define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_COLLISION (1<<0) /* Ethernet */ +#define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ +#define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */ + +/* + * Bits in transmit buffer descriptor status word + * Many bits have the same meaning as those in receiver buffer descriptors. + */ +#define M8260_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_PAD (1<<14) /* Ethernet */ +#define M8260_BD_CTS_REPORT (1<<11) /* SCC UART */ +#define M8260_BD_TX_CRC (1<<10) /* Ethernet */ +#define M8260_BD_DEFER (1<<9) /* Ethernet */ +#define M8260_BD_HEARTBEAT (1<<8) /* Ethernet */ +#define M8260_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ +#define M8260_BD_LATE_COLLISION (1<<7) /* Ethernet */ +#define M8260_BD_NO_STOP_BIT (1<<7) /* SCC UART */ +#define M8260_BD_RETRY_LIMIT (1<<6) /* Ethernet */ +#define M8260_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ +#define M8260_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */ +#define M8260_BD_CARRIER_LOST (1<<0) /* Ethernet */ +#define M8260_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */ + +#define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_PAD (1<<14) /* Ethernet */ +#define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */ +#define M8xx_BD_TX_CRC (1<<10) /* Ethernet */ +#define M8xx_BD_DEFER (1<<9) /* Ethernet */ +#define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */ +#define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ +#define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */ +#define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */ +#define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */ +#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ +#define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */ +#define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */ +#define M8xx_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */ + +/* +************************************************************************* +* IDMA Buffer Descriptors * +************************************************************************* +*/ +typedef struct m8260IDMABufferDescriptor_ { + uint16_t status; + uint8_t dfcr; + uint8_t sfcr; + uint32_t length; + void *source; + void *destination; +} m8260IDMABufferDescriptor_t; + +/* +************************************************************************* +* RISC Communication Processor Module Command Register (CR) * +************************************************************************* +*/ +#define M8260_CR_RST (1<<31) /* Reset communication processor */ + +#define M8260_CR_FCC1 ((4<<26)|(16<<21)) /* FCC1 page and code */ +#define M8260_CR_FCC1_ATM ((4<<26)|(14<<21)) /* FCC1 ATM mode page and code */ +#define M8260_CR_FCC2 ((5<<26)|(17<<21)) /* FCC2 page and code */ +#define M8260_CR_FCC2_ATM ((5<<26)|(14<<21)) /* FCC2 ATM mode page and code */ +#define M8260_CR_FCC3 ((6<<26)|(18<<21)) /* FCC3 page and code */ +#define M8260_CR_SCC1 ((0<<26)|(4<<21)) /* SCC1 page and code */ +#define M8260_CR_SCC2 ((1<<26)|(5<<21)) /* SCC2 page and code */ +#define M8260_CR_SCC3 ((2<<26)|(6<<21)) /* SCC3 page and code */ +#define M8260_CR_SCC4 ((3<<26)|(7<<21)) /* SCC4 page and code */ +#define M8260_CR_SMC1 ((7<<26)|(8<<21)) /* SMC1 page and code */ +#define M8260_CR_SMC2 ((8<<26)|(9<<21)) /* SMC2 page and code */ +#define M8260_CR_RAND ((10<<26)|(14<<21)) /* SMC2 page and code */ +#define M8260_CR_SPI ((9<<26)|(10<<21)) /* SPI page and code */ +#define M8260_CR_I2C ((10<<26)|(11<<21)) /* I2C page and code */ +#define M8260_CR_TMR ((10<<26)|(15<<21)) /* Timer page and code */ +#define M8260_CR_MCC1 ((7<<26)|(28<<21)) /* MCC1 page and code */ +#define M8260_CR_MCC2 ((8<<26)|(29<<21)) /* MCC2 page and code */ +#define M8260_CR_IDMA1 ((7<<26)|(20<<21)) /* IDMA1 page and code */ +#define M8260_CR_IDMA2 ((8<<26)|(21<<21)) /* IDMA2 page and code */ +#define M8260_CR_IDMA3 ((9<<26)|(22<<21)) /* IDMA3 page and code */ +#define M8260_CR_IDMA4 ((10<<26)|(23<<21)) /* IDMA4 page and code */ + +#define M8260_CR_FLG (1<<16) /* Command sempahore flag */ + +#define M8260_CR_MCC_CHAN(x) ((x)<<6) /* MCC channel number */ +#define M8260_CR_FCC_HDLC (0<<6) /* FCC HDLC/Transparent protocol code */ +#define M8260_CR_FCC_ATM (10<<6) /* FCC ATM protocol code */ +#define M8260_CR_FCC_ETH (12<<6) /* FCC Ethernet protocol code */ + +#define M8260_CR_OP_INIT_RX_TX (0) /* FCC, SCC, SMC UART, SMC GCI, SPI, I2C, MCC */ +#define M8260_CR_OP_INIT_RX (1) /* FCC, SCC, SMC UART, SPI, I2C, MCC */ +#define M8260_CR_OP_INIT_TX (2) /* FCC, SCC, SMC UART, SPI, I2C, MCC */ +#define M8260_CR_OP_INIT_HUNT (3) /* FCC, SCC, SMC UART */ +#define M8260_CR_OP_STOP_TX (4) /* FCC, SCC, SMC UART, MCC */ +#define M8260_CR_OP_GR_STOP_TX (5) /* FCC, SCC */ +#define M8260_CR_OP_RESTART_TX (6) /* FCC, SCC, SMC UART */ +#define M8260_CR_OP_CLOSE_RX_BD (7) /* FCC, SCC, SMC UART, SPI, I2C */ +#define M8260_CR_OP_SET_GRP_ADDR (8) /* FCC, SCC */ +#define M8260_CR_OP_SET_TIMER (8) /* Timer */ +#define M8260_CR_OP_GCI_TIMEOUT (9) /* SMC GCI */ +#define M8260_CR_OP_START_IDMA (9) /* IDMA */ +#define M8260_CR_OP_STOP_RX (9) /* MCC */ +#define M8260_CR_OP_ATM_TX (10) /* FCC */ +#define M8260_CR_OP_RESET_BCS (10) /* SCC */ +#define M8260_CR_OP_GCI_ABORT (10) /* SMC GCI */ +#define M8260_CR_OP_STOP_IDMA (11) /* IDMA */ +#define M8260_CR_OP_RANDOM (12) /* RAND */ + +/* +************************************************************************* +* System Protection Control Register (SYPCR) * +************************************************************************* +*/ +#define M8260_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ +#define M8260_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ +#define M8260_SYPCR_BME (1<<7) /* Bus monitor enable */ +#define M8260_SYPCR_SWF (1<<3) /* Software watchdog freeze */ +#define M8260_SYPCR_SWE (1<<2) /* Software watchdog enable */ +#define M8260_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ +#define M8260_SYPCR_SWP (1<<0) /* Software watchdog prescale */ + +/* +************************************************************************* +* Memory Control Registers * +************************************************************************* +*/ +#define M8260_UPM_AMX_8col (0<<20) /* 8 column DRAM */ +#define M8260_UPM_AMX_9col (1<<20) /* 9 column DRAM */ +#define M8260_UPM_AMX_10col (2<<20) /* 10 column DRAM */ +#define M8260_UPM_AMX_11col (3<<20) /* 11 column DRAM */ +#define M8260_UPM_AMX_12col (4<<20) /* 12 column DRAM */ +#define M8260_UPM_AMX_13col (5<<20) /* 13 column DRAM */ +#define M8260_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */ +#define M8260_MSR_WPER (1<<7) /* Write protection error */ +#define M8260_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */ +#define M8260_BR_BA(x) ((x)&0xffff8000) /* Base address */ +#define M8260_BR_AT(x) ((x)<<12) /* Address type */ +#define M8260_BR_PS8 (1<<10) /* 8 bit port */ +#define M8260_BR_PS16 (2<<10) /* 16 bit port */ +#define M8260_BR_PS32 (0<<10) /* 32 bit port */ +#define M8260_BR_PARE (1<<9) /* Parity checking enable */ +#define M8260_BR_WP (1<<8) /* Write protect */ +#define M8260_BR_MS_GPCM (0<<6) /* GPCM */ +#define M8260_BR_MS_UPMA (2<<6) /* UPM A */ +#define M8260_BR_MS_UPMB (3<<6) /* UPM B */ +#define M8260_MEMC_BR_V (1<<0) /* Base/Option register are valid */ + +#define M8260_MEMC_OR_32K 0xffff8000 /* Address range */ +#define M8260_MEMC_OR_64K 0xffff0000 +#define M8260_MEMC_OR_128K 0xfffe0000 +#define M8260_MEMC_OR_256K 0xfffc0000 +#define M8260_MEMC_OR_512K 0xfff80000 +#define M8260_MEMC_OR_1M 0xfff00000 +#define M8260_MEMC_OR_2M 0xffe00000 +#define M8260_MEMC_OR_4M 0xffc00000 +#define M8260_MEMC_OR_8M 0xff800000 +#define M8260_MEMC_OR_16M 0xff000000 +#define M8260_MEMC_OR_32M 0xfe000000 +#define M8260_MEMC_OR_64M 0xfc000000 +#define M8260_MEMC_OR_128 0xf8000000 +#define M8260_MEMC_OR_256M 0xf0000000 +#define M8260_MEMC_OR_512M 0xe0000000 +#define M8260_MEMC_OR_1G 0xc0000000 +#define M8260_MEMC_OR_2G 0x80000000 +#define M8260_MEMC_OR_4G 0x00000000 +#define M8260_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ +#define M8260_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ +#define M8260_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */ +#define M8260_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ +#define M8260_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ +#define M8260_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ +#define M8260_MEMC_OR_BI (1<8) /* Burst inhibit */ +#define M8260_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ +#define M8260_MEMC_OR_SETA (1<<3) /* *TA generated externally */ +#define M8260_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */ +#define M8260_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */ + +/* +************************************************************************* +* UPM Registers (MxMR) * +************************************************************************* +*/ +#define M8260_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */ +#define M8260_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */ +#define M8260_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */ +#define M8260_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */ +#define M8260_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */ +#define M8260_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */ +#define M8260_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */ +#define M8260_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */ +/* +************************************************************************* +* Memory Command Register (MCR) * +************************************************************************* +*/ +#define M8260_MEMC_MCR_WRITE (0<<30) /* WRITE command */ +#define M8260_MEMC_MCR_READ (1<<30) /* READ command */ +#define M8260_MEMC_MCR_RUN (2<<30) /* RUN command */ +#define M8260_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */ +#define M8260_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */ +#define M8260_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */ +#define M8260_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */ +#define M8260_MEMC_MCR_MAD(x) (x) /* Machine address */ + + + +/* +************************************************************************* +* SI Mode Register (SIMODE) * +************************************************************************* +*/ +#define M8260_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ +#define M8260_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ +#define M8260_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ +#define M8260_SI_SMC2_BRG2 (1<<28) +#define M8260_SI_SMC2_BRG3 (2<<28) +#define M8260_SI_SMC2_BRG4 (3<<28) +#define M8260_SI_SMC2_CLK5 (0<<28) +#define M8260_SI_SMC2_CLK6 (1<<28) +#define M8260_SI_SMC2_CLK7 (2<<28) +#define M8260_SI_SMC2_CLK8 (3<<28) +#define M8260_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ +#define M8260_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ +#define M8260_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ +#define M8260_SI_SMC1_BRG2 (1<<12) +#define M8260_SI_SMC1_BRG3 (2<<12) +#define M8260_SI_SMC1_BRG4 (3<<12) +#define M8260_SI_SMC1_CLK1 (0<<12) +#define M8260_SI_SMC1_CLK2 (1<<12) +#define M8260_SI_SMC1_CLK3 (2<<12) +#define M8260_SI_SMC1_CLK4 (3<<12) + +/* +************************************************************************* +* SDMA Configuration Register (SDCR) * +************************************************************************* +*/ +#define M8260_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */ +#define M8260_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */ + +/* +************************************************************************* +* SDMA Status Register (SDSR) * +************************************************************************* +*/ +#define M8260_SDSR_SBER (1<<7) /* SDMA Channel bus error */ +#define M8260_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */ +#define M8260_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */ + +/* +************************************************************************* +* Baud (sic) Rate Generators * +************************************************************************* +*/ +#define M8260_BRG_RST (1<<17) /* Reset generator */ +#define M8260_BRG_EN (1<<16) /* Enable generator */ +#define M8260_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ +#define M8260_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ +#define M8260_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ +#define M8260_BRG_ATB (1<<13) /* Autobaud */ +#define M8260_BRG_115200 (21<<1) /* Assume 40 MHz clock */ +#define M8260_BRG_57600 (32<<1) +#define M8260_BRG_38400 (64<<1) +#define M8260_BRG_19200 (129<<1) +#define M8260_BRG_9600 (259<<1) +#define M8260_BRG_4800 (520<<1) +#define M8260_BRG_2400 (1040<<1) +#define M8260_BRG_1200 (2082<<1) +#define M8260_BRG_600 ((259<<1) | 1) +#define M8260_BRG_300 ((520<<1) | 1) +#define M8260_BRG_150 ((1040<<1) | 1) +#define M8260_BRG_75 ((2080<<1) | 1) + +#define M8xx_BRG_RST (1<<17) /* Reset generator */ +#define M8xx_BRG_EN (1<<16) /* Enable generator */ +#define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ + +#define M8260_BRG1 (1<<7) +#define M8260_BRG2 (1<<6) +#define M8260_BRG3 (1<<5) +#define M8260_BRG4 (1<<4) +#define M8260_BRG5 (1<<3) +#define M8260_BRG6 (1<<2) +#define M8260_BRG7 (1<<1) +#define M8260_BRG8 (1<<0) + + + +#define M8260_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */ +#define M8260_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */ +#define M8260_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */ +#define M8260_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */ +#define M8260_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */ +#define M8260_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */ +#define M8260_TGCR_STP1 (1<<1) /* Stop timer */ +#define M8260_TGCR_STP2 (1<<5) /* Stop timer */ +#define M8260_TGCR_STP3 (1<<9) /* Stop timer */ +#define M8260_TGCR_STP4 (1<<13) /* Stop timer */ +#define M8260_TGCR_RST1 (1<<0) /* Enable timer */ +#define M8260_TGCR_RST2 (1<<4) /* Enable timer */ +#define M8260_TGCR_RST3 (1<<8) /* Enable timer */ +#define M8260_TGCR_RST4 (1<<12) /* Enable timer */ +#define M8260_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */ +#define M8260_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */ + +#define M8260_TMR_PS(x) ((x)<<8) /* Timer prescaler */ +#define M8260_TMR_CE_RISE (1<<6) /* Capture on rising edge */ +#define M8260_TMR_CE_FALL (2<<6) /* Capture on falling edge */ +#define M8260_TMR_CE_ANY (3<<6) /* Capture on any edge */ +#define M8260_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */ +#define M8260_TMR_ORI (1<<4) /* Interrupt on reaching reference */ +#define M8260_TMR_RESTART (1<<3) /* Restart timer after reference */ +#define M8260_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */ +#define M8260_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */ +#define M8260_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */ +#define M8260_TMR_TGATE (1<<0) /* TGATE controls timer */ + +#ifdef REV_0_2 +#define M8260_PISCR_PS (1<<6) /* PIT Interrupt state */ +#else +#define M8260_PISCR_PS (1<<7) /* PIT Interrupt state */ +#endif +#define M8260_PISCR_PIE (1<<2) /* PIT interrupt enable */ +#define M8260_PISCR_PTF (1<<1) /* Stop timer when freeze asserted */ +#define M8260_PISCR_PTE (1<<0) /* PIT enable */ + +#if 0 +#define M8260_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ +#define M8260_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ +#define M8260_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ +#define M8260_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ +#define M8260_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ +#define M8260_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ +#define M8260_TBSCR_TBE (1<<0) /* enable TB and decrementer */ +#endif + +#define M8260_TMCNTSC_SEC (1<<7) /* per second flag */ +#define M8260_TMCNTSC_ALR (1<<6) /* Alarm interrupt flag */ +#define M8260_TMCNTSC_SIE (1<<3) /* per second interrupt enable */ +#define M8260_TMCNTSC_ALE (1<<2) /* Alarm interrupt enable */ +#define M8260_TMCNTSC_TCF (1<<1) /* Time count frequency */ +#define M8260_TMCNTSC_TCE (1<<0) /* Time count enable */ + +#define M8260_SIMASK_PC0 (1<<31) +#define M8260_SIMASK_PC1 (1<<30) +#define M8260_SIMASK_PC2 (1<<29) +#define M8260_SIMASK_PC3 (1<<28) +#define M8260_SIMASK_PC4 (1<<27) +#define M8260_SIMASK_PC5 (1<<26) +#define M8260_SIMASK_PC6 (1<<25) +#define M8260_SIMASK_PC7 (1<<24) +#define M8260_SIMASK_PC8 (1<<23) +#define M8260_SIMASK_PC9 (1<<22) +#define M8260_SIMASK_PC10 (1<<21) +#define M8260_SIMASK_PC11 (1<<20) +#define M8260_SIMASK_PC12 (1<<19) +#define M8260_SIMASK_PC13 (1<<18) +#define M8260_SIMASK_PC14 (1<<17) +#define M8260_SIMASK_PC15 (1<<16) +#define M8260_SIMASK_IRQ1 (1<<14) +#define M8260_SIMASK_IRQ2 (1<<13) +#define M8260_SIMASK_IRQ3 (1<<12) +#define M8260_SIMASK_IRQ4 (1<<11) +#define M8260_SIMASK_IRQ5 (1<<10) +#define M8260_SIMASK_IRQ6 (1<<9) +#define M8260_SIMASK_IRQ7 (1<<8) +#define M8260_SIMASK_TMCNT (1<<2) +#define M8260_SIMASK_PIT (1<<1) + +#define M8260_SIMASK_FCC1 (1<<31) +#define M8260_SIMASK_FCC2 (1<<30) +#define M8260_SIMASK_FCC3 (1<<29) +#define M8260_SIMASK_MCC1 (1<<27) +#define M8260_SIMASK_MCC2 (1<<26) +#define M8260_SIMASK_SCC1 (1<<23) +#define M8260_SIMASK_SCC2 (1<<22) +#define M8260_SIMASK_SCC3 (1<<21) +#define M8260_SIMASK_SCC4 (1<<20) +#define M8260_SIMASK_I2C (1<<15) +#define M8260_SIMASK_SPI (1<<14) +#define M8260_SIMASK_RTT (1<<13) +#define M8260_SIMASK_SMC1 (1<<12) +#define M8260_SIMASK_SMC2 (1<<11) +#define M8260_SIMASK_IDMA1 (1<<10) +#define M8260_SIMASK_IDMA2 (1<<9) +#define M8260_SIMASK_IDMA3 (1<<8) +#define M8260_SIMASK_IDMA4 (1<<7) +#define M8260_SIMASK_SDMA (1<<6) +#define M8260_SIMASK_TIMER1 (1<<4) +#define M8260_SIMASK_TIMER2 (1<<3) +#define M8260_SIMASK_TIMER3 (1<<2) +#define M8260_SIMASK_TIMER4 (1<<1) + +#define M8260_SIUMCR_EARB (1<<31) +#define M8260_SIUMCR_EARP0 (0<<28) +#define M8260_SIUMCR_EARP1 (1<<28) +#define M8260_SIUMCR_EARP2 (2<<28) +#define M8260_SIUMCR_EARP3 (3<<28) +#define M8260_SIUMCR_EARP4 (4<<28) +#define M8260_SIUMCR_EARP5 (5<<28) +#define M8260_SIUMCR_EARP6 (6<<28) +#define M8260_SIUMCR_EARP7 (7<<28) +#define M8260_SIUMCR_DSHW (1<<23) +#define M8260_SIUMCR_DBGC0 (0<<21) +#define M8260_SIUMCR_DBGC1 (1<<21) +#define M8260_SIUMCR_DBGC2 (2<<21) +#define M8260_SIUMCR_DBGC3 (3<<21) +#define M8260_SIUMCR_DBPC0 (0<<19) +#define M8260_SIUMCR_DBPC1 (1<<19) +#define M8260_SIUMCR_DBPC2 (2<<19) +#define M8260_SIUMCR_DBPC3 (3<<19) +#define M8260_SIUMCR_FRC (1<<17) +#define M8260_SIUMCR_DLK (1<<16) +#define M8260_SIUMCR_PNCS (1<<15) +#define M8260_SIUMCR_OPAR (1<<14) +#define M8260_SIUMCR_DPC (1<<13) +#define M8260_SIUMCR_MPRE (1<<12) +#define M8260_SIUMCR_MLRC0 (0<<10) +#define M8260_SIUMCR_MLRC1 (1<<10) +#define M8260_SIUMCR_MLRC2 (2<<10) +#define M8260_SIUMCR_MLRC3 (3<<10) +#define M8260_SIUMCR_AEME (1<<9) +#define M8260_SIUMCR_SEME (1<<8) +#define M8260_SIUMCR_BSC (1<<7) +#define M8260_SIUMCR_GB5E (1<<6) +#define M8260_SIUMCR_B2DD (1<<5) +#define M8260_SIUMCR_B3DD (1<<4) + +/* +************************************************************************* +* MPC8260 DUAL-PORT RAM AND REGISTERS * +************************************************************************* +*/ +typedef struct m8260_ { + + /* + * CPM Dual-Port RAM + */ + uint8_t dpram1[16384]; /* 0x0000 - 0x3FFF BD/data/ucode */ + uint8_t cpm_pad0[16384]; /* 0x4000 - 0x7FFF Reserved */ + + m8260SCCparms_t scc1p; + uint8_t pad_scc1[256-sizeof(m8260SCCparms_t)]; + m8260SCCparms_t scc2p; + uint8_t pad_scc2[256-sizeof(m8260SCCparms_t)]; + m8260SCCparms_t scc3p; + uint8_t pad_scc3[256-sizeof(m8260SCCparms_t)]; + m8260SCCparms_t scc4p; + uint8_t pad_scc4[256-sizeof(m8260SCCparms_t)]; + + m8260FCCparms_t fcc1p; + uint8_t pad_fcc1[256-sizeof(m8260FCCparms_t)]; + m8260FCCparms_t fcc2p; + uint8_t pad_fcc2[256-sizeof(m8260FCCparms_t)]; + m8260FCCparms_t fcc3p; + uint8_t pad_fcc3[256-sizeof(m8260FCCparms_t)]; + + uint8_t mcc1p[128]; + uint8_t pad_mcc1[124]; + uint16_t smc1_base; + uint16_t idma1_base; + uint8_t mcc2p[128]; + uint8_t pad_mcc2[124]; + uint16_t smc2_base; + uint16_t idma2_base; + uint8_t pad_spi[252]; + uint16_t spi_base; + uint16_t idma3_base; + uint8_t pad_risc[224]; + uint8_t risc_timers[16]; + uint16_t rev_num; + uint16_t cpm_pad7; + uint32_t cpm_pad8; + uint16_t rand; + uint16_t i2c_base; + uint16_t idma4_base; + uint8_t cpm_pad9[1282]; + + uint8_t cpm_pad1[8192]; /* 0x9000 - 0xAFFF Reserved */ + + m8260SMCparms_t smc1p; + m8260SMCparms_t smc2p; + uint8_t dpram3[4096-2*sizeof(m8260SMCparms_t)]; + + uint8_t cpm_pad2[16384]; /* 0xC000 - 0xFFFF Reserved */ + + + /* + * General SIU Block + */ + uint32_t siumcr; + uint32_t sypcr; + uint8_t siu_pad0[6]; + uint16_t swsr; + uint8_t siu_pad1[20]; + uint32_t bcr; + uint8_t ppc_acr; + uint8_t siu_pad4[3]; + uint32_t ppc_alrh; + uint32_t ppc_alr1; + uint8_t lcl_acr; + uint8_t siu_pad5[3]; + uint32_t lcl_alrh; + uint32_t lcl_alr1; + uint32_t tescr1; + uint32_t tescr2; + uint32_t l_tescr1; + uint32_t l_tescr2; + uint32_t pdtea; + uint8_t pdtem; + uint8_t siu_pad2[3]; + uint32_t ldtea; + uint8_t ldtem; + uint8_t siu_pad3[163]; + + + /* + * Memory Controller Block + */ + m8260MEMCRegisters_t memc[12]; + uint8_t mem_pad0[8]; + uint32_t mar; + uint8_t mem_pad1[4]; + uint32_t mamr; + uint32_t mbmr; + uint32_t mcmr; + uint32_t mdmr; + uint8_t mem_pad2[4]; + uint16_t mptpr; + uint8_t mem_pad5[2]; + uint32_t mdr; + uint8_t mem_pad3[4]; + uint32_t psdmr; + uint32_t lsdmr; + uint8_t purt; + uint8_t mem_pad6[3]; + uint8_t psrt; + uint8_t mem_pad7[3]; + uint8_t lurt; + uint8_t mem_pad8[3]; + uint8_t lsrt; + uint8_t mem_pad9[3]; + uint32_t immr; + uint8_t mem_pad4[84]; + + + /* + * System integration timers + */ + uint8_t sit_pad0[32]; + uint16_t tmcntsc; + uint8_t sit_pad6[2]; + uint32_t tmcnt; + uint32_t tmcntsec; + uint32_t tmcntal; + uint8_t sit_pad2[16]; + uint16_t piscr; + uint8_t sit_pad5[2]; + uint32_t pitc; + uint32_t pitr; + uint8_t sit_pad3[94]; + uint8_t sit_pad4[2390]; + + + /* + * Interrupt Controller + */ + uint16_t sicr; + uint8_t ict_pad1[2]; + uint32_t sivec; + uint32_t sipnr_h; + uint32_t sipnr_l; + uint32_t siprr; + uint32_t scprr_h; + uint32_t scprr_l; + uint32_t simr_h; + uint32_t simr_l; + uint32_t siexr; + uint8_t ict_pad0[88]; + + + /* + * Clocks and Reset + */ + uint32_t sccr; + uint8_t clr_pad1[4]; + uint32_t scmr; + uint8_t clr_pad2[4]; + uint32_t rsr; + uint32_t rmr; + uint8_t clr_pad0[104]; + + + /* + * Input/ Output Port + */ + uint32_t pdira; + uint32_t ppara; + uint32_t psora; + uint32_t podra; + uint32_t pdata; + uint8_t iop_pad0[12]; + uint32_t pdirb; + uint32_t pparb; + uint32_t psorb; + uint32_t podrb; + uint32_t pdatb; + uint8_t iop_pad1[12]; + uint32_t pdirc; + uint32_t pparc; + uint32_t psorc; + uint32_t podrc; + uint32_t pdatc; + uint8_t iop_pad2[12]; + uint32_t pdird; + uint32_t ppard; + uint32_t psord; + uint32_t podrd; + uint32_t pdatd; + uint8_t iop_pad3[12]; + + + /* + * CPM Timers + */ + uint8_t tgcr1; + uint8_t cpt_pad0[3]; + uint8_t tgcr2; + uint8_t cpt_pad1[11]; + uint16_t tmr1; + uint16_t tmr2; + uint16_t trr1; + uint16_t trr2; + uint16_t tcr1; + uint16_t tcr2; + uint16_t tcn1; + uint16_t tcn2; + uint16_t tmr3; + uint16_t tmr4; + uint16_t trr3; + uint16_t trr4; + uint16_t tcr3; + uint16_t tcr4; + uint16_t tcn3; + uint16_t tcn4; + uint16_t ter1; + uint16_t ter2; + uint16_t ter3; + uint16_t ter4; + uint8_t cpt_pad2[608]; + + + /* + * DMA Block + */ + uint8_t sdsr; + uint8_t dma_pad0[3]; + uint8_t sdmr; + uint8_t dma_pad1[3]; + + uint8_t idsr1; + uint8_t dma_pad2[3]; + uint8_t idmr1; + uint8_t dma_pad3[3]; + uint8_t idsr2; + uint8_t dma_pad4[3]; + uint8_t idmr2; + uint8_t dma_pad5[3]; + uint8_t idsr3; + uint8_t dma_pad6[3]; + uint8_t idmr3; + uint8_t dma_pad7[3]; + uint8_t idsr4; + uint8_t dma_pad8[3]; + uint8_t idmr4; + uint8_t dma_pad9[707]; + + + /* + * FCC Block + */ + m8260FCCRegisters_t fcc1; + m8260FCCRegisters_t fcc2; + m8260FCCRegisters_t fcc3; + + uint8_t fcc_pad0[656]; + + /* + * BRG 5-8 Block + */ + uint32_t brgc5; + uint32_t brgc6; + uint32_t brgc7; + uint32_t brgc8; + uint8_t brg_pad0[608]; + + + /* + * I2C + */ + uint8_t i2mod; + uint8_t i2m_pad0[3]; + uint8_t i2add; + uint8_t i2m_pad1[3]; + uint8_t i2brg; + uint8_t i2m_pad2[3]; + uint8_t i2com; + uint8_t i2m_pad3[3]; + uint8_t i2cer; + uint8_t i2m_pad4[3]; + uint8_t i2cmr; + uint8_t i2m_pad5[331]; + + + /* + * CPM Block + */ + uint32_t cpcr; + uint32_t rccr; + uint8_t cpm_pad3[14]; + uint16_t rter; + uint8_t cpm_pad[2]; + uint16_t rtmr; + uint16_t rtscr; + uint8_t cpm_pad4[2]; + uint32_t rtsr; + uint8_t cpm_pad5[12]; + + + /* + * BRG 1-4 Block + */ + uint32_t brgc1; + uint32_t brgc2; + uint32_t brgc3; + uint32_t brgc4; + + + /* + * SCC Block + */ + m8260SCCRegisters_t scc1; + m8260SCCRegisters_t scc2; + m8260SCCRegisters_t scc3; + m8260SCCRegisters_t scc4; + + + /* + * SMC Block + */ + m8260SMCRegisters_t smc1; + m8260SMCRegisters_t smc2; + + + /* + * SPI Block + */ + uint16_t spmode; + uint8_t spi_pad0[4]; + uint8_t spie; + uint8_t spi_pad1[3]; + uint8_t spim; + uint8_t spi_pad2[2]; + uint8_t spcom; + uint8_t spi_pad3[82]; + + + /* + * CPM Mux Block + */ + uint8_t cmxsi1cr; + uint8_t cmx_pad0[1]; + uint8_t cmxsi2cr; + uint8_t cmx_pad1[1]; + uint32_t cmxfcr; + uint32_t cmxscr; + uint8_t cmxsmr; + uint8_t cmx_pad2[1]; + uint16_t cmxuar; + uint8_t cmx_pad3[16]; + + + /* + * SI & MCC Blocks + */ + m8260SIRegisters_t si1; + m8260MCCRegisters_t mcc1; + m8260SIRegisters_t si2; + m8260MCCRegisters_t mcc2; + + uint8_t mcc_pad0[1152]; + + /* + * SI1 RAM + */ + uint8_t si1txram[512]; + uint8_t ram_pad0[512]; + uint8_t si1rxram[512]; + uint8_t ram_pad1[512]; + + + /* + * SI2 RAM + */ + uint8_t si2txram[512]; + uint8_t ram_pad2[512]; + uint8_t si2rxram[512]; + uint8_t ram_pad3[512]; + + +} m8260_t; + +extern volatile m8260_t m8260; +#endif /* ASM */ + +#endif /* _MPC8260_H */ diff --git a/bsps/powerpc/include/mpc8260/console.h b/bsps/powerpc/include/mpc8260/console.h new file mode 100644 index 0000000000..049cef6d89 --- /dev/null +++ b/bsps/powerpc/include/mpc8260/console.h @@ -0,0 +1,60 @@ +#ifndef _MPC8260_CONSOLE_H +#define _MPC8260_CONSOLE_H + +#include + +void m8xx_uart_initialize(void); +void m8xx_uart_interrupts_initialize(void); +void m8xx_uart_scc_initialize (int minor); +void m8xx_uart_smc_initialize (int minor); + +/* Termios callbacks */ +int m8xx_uart_pollRead(int minor); +ssize_t m8xx_uart_pollWrite(int minor, const char* buf, size_t len); +ssize_t m8xx_uart_write(int minor, const char *buf, size_t len); +int m8xx_uart_setAttributes(int, const struct termios* t); + + +#if 0 +int m8260_smc_set_attributes(int, const struct termios*); +int m8260_scc_set_attributes(int, const struct termios*); +void m8260_scc_initialize(int); +void m8260_smc_initialize(int); +int m8260_char_poll_read(int); +int m8260_char_poll_write(int, const char*, int); +rtems_isr m8260_scc1_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_scc2_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_scc3_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_scc4_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_smc1_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_smc2_console_interrupt_handler(rtems_vector_number); +int m8260_buf_poll_read(int, char**); +int m8260_buf_poll_write(int, char*, int); +void m8260_console_initialize(void); +rtems_device_driver m8260_console_read(rtems_device_major_number, + rtems_device_minor_number, + void*); +rtems_device_driver m8260_console_write(rtems_device_major_number, + rtems_device_minor_number, + void*); + + +typedef struct Buf_t_ { + struct Buf_t_ *next; + volatile char *buf; + volatile int len; + int pos; +} Buf_t; +#endif + +#define NUM_PORTS 6 + +#define SMC1_MINOR 0 +#define SMC2_MINOR 1 +#define SCC1_MINOR 2 +#define SCC2_MINOR 3 +#define SCC3_MINOR 4 +#define SCC4_MINOR 5 + + +#endif diff --git a/bsps/powerpc/include/mpc8260/cpm.h b/bsps/powerpc/include/mpc8260/cpm.h new file mode 100644 index 0000000000..31708a4199 --- /dev/null +++ b/bsps/powerpc/include/mpc8260/cpm.h @@ -0,0 +1,123 @@ +/* + * cpm.h + * + * This include file contains definitions pertaining + * to the Communications Processor Module (CPM) on the MPC8xx. + * + * Copyright (c) 1999, National Research Council of Canada + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MPC8260_CPM_H +#define _MPC8260_CPM_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#define M8xx_BRG_1 (1U << 0) +#define M8xx_BRG_2 (1U << 1) +#define M8xx_BRG_3 (1U << 2) +#define M8xx_BRG_4 (1U << 3) +#define M8xx_BRG_5 (1U << 4) +#define M8xx_BRG_6 (1U << 5) +#define M8xx_BRG_7 (1U << 6) +#define M8xx_BRG_8 (1U << 7) + + +#define M8260_SCC_BRGS (M8xx_BRG_1 | M8xx_BRG_2 | M8xx_BRG_3 | M8xx_BRG_4) +#define M8260_FCC_BRGS (M8xx_BRG_5 | M8xx_BRG_6 | M8xx_BRG_7 | M8xx_BRG_8) +#define M8260_SMC1_BRGS (M8xx_BRG_1|M8xx_BRG_7) +#define M8260_SMC2_BRGS (M8xx_BRG_2|M8xx_BRG_8) + + +#define M8xx_CLK_1 (1U << 0) +#define M8xx_CLK_2 (1U << 1) +#define M8xx_CLK_3 (1U << 2) +#define M8xx_CLK_4 (1U << 3) +#define M8xx_CLK_5 (1U << 4) +#define M8xx_CLK_6 (1U << 5) +#define M8xx_CLK_7 (1U << 6) +#define M8xx_CLK_8 (1U << 7) +#define M8xx_CLK_9 (1U << 8) +#define M8xx_CLK_10 (1U << 9) +#define M8xx_CLK_11 (1U << 10) +#define M8xx_CLK_12 (1U << 11) +#define M8xx_CLK_13 (1U << 12) +#define M8xx_CLK_14 (1U << 13) +#define M8xx_CLK_15 (1U << 14) +#define M8xx_CLK_16 (1U << 15) +#define M8xx_CLK_17 (1U << 16) +#define M8xx_CLK_18 (1U << 17) +#define M8xx_CLK_19 (1U << 18) +#define M8xx_CLK_20 (1U << 19) + +#define M8260_BRG1_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) +#define M8260_BRG2_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) +#define M8260_BRG3_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) +#define M8260_BRG4_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) +#define M8260_BRG5_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) +#define M8260_BRG6_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) +#define M8260_BRG7_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) +#define M8260_BRG8_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) + +#define M8260_SCC1_CLKS (M8xx_CLK_3 | M8xx_CLK_4 | M8xx_CLK_11 | M8xx_CLK_12) +#define M8260_SCC2_CLKS (M8xx_CLK_3 | M8xx_CLK_4 | M8xx_CLK_11 | M8xx_CLK_12) +#define M8260_SCC3_CLKS (M8xx_CLK_5 | M8xx_CLK_6 | M8xx_CLK_7 | M8xx_CLK_8 ) +#define M8260_SCC4_CLKS (M8xx_CLK_5 | M8xx_CLK_6 | M8xx_CLK_7 | M8xx_CLK_8 ) + +#define M8260_FCC1_CLKS (M8xx_CLK_9 | M8xx_CLK_10 | M8xx_CLK_11 | M8xx_CLK_12) +#define M8260_FCC2_CLKS (M8xx_CLK_13 | M8xx_CLK_14 | M8xx_CLK_15 | M8xx_CLK_16) +#define M8260_FCC3_CLKS (M8xx_CLK_13 | M8xx_CLK_14 | M8xx_CLK_15 | M8xx_CLK_16) + +#define M8260_TDM_RXA1 (M8xx_CLK_1 | M8xx_CLK_19 ) +#define M8260_TDM_RXB1 (M8xx_CLK_3 | M8xx_CLK_9 ) +#define M8260_TDM_RXC1 (M8xx_CLK_5 | M8xx_CLK_13 ) +#define M8260_TDM_RXD1 (M8xx_CLK_7 | M8xx_CLK_15 ) +#define M8260_TDM_TXA1 (M8xx_CLK_2 | M8xx_CLK_20 ) +#define M8260_TDM_TXB1 (M8xx_CLK_4 | M8xx_CLK_10 ) +#define M8260_TDM_TXC1 (M8xx_CLK_6 | M8xx_CLK_14 ) +#define M8260_TDM_TXD1 (M8xx_CLK_8 | M8xx_CLK_16 ) + +#define M8260_TDM_RXA2 (M8xx_CLK_13 | M8xx_CLK_5 ) +#define M8260_TDM_RXB2 (M8xx_CLK_15 | M8xx_CLK_17 ) +#define M8260_TDM_RXC2 (M8xx_CLK_3 | M8xx_CLK_17 ) +#define M8260_TDM_RXD2 (M8xx_CLK_1 | M8xx_CLK_19 ) +#define M8260_TDM_TXA2 (M8xx_CLK_14 | M8xx_CLK_6 ) +#define M8260_TDM_TXB2 (M8xx_CLK_16 | M8xx_CLK_18 ) +#define M8260_TDM_TXC2 (M8xx_CLK_4 | M8xx_CLK_18 ) +#define M8260_TDM_TXD2 (M8xx_CLK_2 | M8xx_CLK_20 ) + + + +/* Functions */ + +void m8xx_cp_execute_cmd( uint32_t command ); +void *m8xx_dpram_allocate( unsigned int byte_count ); + +#define m8xx_bd_allocate(count) \ + m8xx_dpram_allocate( (count) * sizeof(m8260BufferDescriptor_t) ) +#define m8xx_RISC_timer_table_allocate(count) \ + m8xx_dpram_allocate( (count) * 4 ) + + + +int m8xx_get_brg_cd (int baud); +int m8xx_get_brg(unsigned brgmask, int baud); +void m8xx_free_brg(int brg_num); + + +int m8xx_get_clk( unsigned clkmask ); +void m8xx_free_clk( int clk_num ); + + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/powerpc/include/mpc8260/mmu.h b/bsps/powerpc/include/mpc8260/mmu.h new file mode 100644 index 0000000000..9445dde3bc --- /dev/null +++ b/bsps/powerpc/include/mpc8260/mmu.h @@ -0,0 +1,47 @@ +/* + * mmu.h + * + * This include file contains definitions pertaining + * to the MMU on the MPC8xx. + * + * Copyright (c) 1999, National Research Council of Canada + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MPC8260_MMU_H +#define _MPC8260_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The MMU_TLB_table is used to statically initialize the Table Lookaside + * Buffers in the MMU of an MPC8260. + */ +typedef struct { + uint32_t mmu_epn; /* Effective Page Number */ + uint32_t mmu_twc; /* Tablewalk Control Register */ + uint32_t mmu_rpn; /* Real Page Number */ +} MMU_TLB_table_t; + +/* + * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be + * supplied by the BSP. + */ +extern MMU_TLB_table_t MMU_TLB_table[]; /* MMU TLB table supplied by BSP */ +extern int MMU_N_TLB_Table_Entries; /* Number of entries in MMU TLB table */ + +/* Functions */ + +void mmu_init( void ); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/powerpc/include/mpc83xx/gtm.h b/bsps/powerpc/include/mpc83xx/gtm.h new file mode 100644 index 0000000000..a17510ed10 --- /dev/null +++ b/bsps/powerpc/include/mpc83xx/gtm.h @@ -0,0 +1,67 @@ +/** + * @file + * + * @brief Header file for timer functions. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_MPC83XX_TIMER_H +#define LIBBSP_POWERPC_MPC83XX_TIMER_H + +#include +#include + +#include + +#define MPC83XX_GTM_NUMBER 8 + +#define MPC83XX_GTM_CLOCK_CASCADED 0x0000 +#define MPC83XX_GTM_CLOCK_SYSTEM 0x0002 +#define MPC83XX_GTM_CLOCK_SYSTEM_SLOW 0x0004 +#define MPC83XX_GTM_CLOCK_EXTERN 0x0006 + +rtems_status_code mpc83xx_gtm_initialize( int timer, int clock); + +rtems_status_code mpc83xx_gtm_enable_restart( int timer, bool enable); + +rtems_status_code mpc83xx_gtm_set_clock( int timer, int clock); + +rtems_status_code mpc83xx_gtm_get_clock( int timer, int *clock); + +rtems_status_code mpc83xx_gtm_start( int timer); + +rtems_status_code mpc83xx_gtm_stop( int timer); + +rtems_status_code mpc83xx_gtm_set_value( int timer, uint16_t value); + +rtems_status_code mpc83xx_gtm_get_value( int timer, uint16_t *value); + +rtems_status_code mpc83xx_gtm_set_reference( int timer, uint16_t reference); + +rtems_status_code mpc83xx_gtm_get_reference( int timer, uint16_t *reference); + +rtems_status_code mpc83xx_gtm_set_prescale( int timer, uint8_t prescale); + +rtems_status_code mpc83xx_gtm_get_prescale( int timer, uint8_t *prescale); + +rtems_status_code mpc83xx_gtm_interrupt_get_vector( int timer, rtems_vector_number *vector); + +rtems_status_code mpc83xx_gtm_interrupt_enable( int timer); + +rtems_status_code mpc83xx_gtm_interrupt_disable( int timer); + +rtems_status_code mpc83xx_gtm_interrupt_clear( int timer); + +#endif /* LIBBSP_POWERPC_MPC83XX_TIMER_H */ diff --git a/bsps/powerpc/include/mpc83xx/mpc83xx.h b/bsps/powerpc/include/mpc83xx/mpc83xx.h new file mode 100644 index 0000000000..6f7417af1c --- /dev/null +++ b/bsps/powerpc/include/mpc83xx/mpc83xx.h @@ -0,0 +1,1014 @@ +#ifndef _MPC83XX_MPC83XX_H +#define _MPC83XX_MPC83XX_H + +#include + +#if MPC83XX_CHIP_TYPE == 8343 +#define M83xx_HAS_PCI TRUE +#define M83xx_HAS_USB1 TRUE +#elif MPC83XX_CHIP_TYPE == 8347 +#define M83xx_HAS_PCI TRUE +#define M83xx_HAS_USB1 TRUE +#define M83xx_HAS_USB2 TRUE +#elif MPC83XX_CHIP_TYPE == 8349 +#define M83xx_HAS_PCI TRUE +#define M83xx_HAS_WIDE_PCI TRUE +#define M83xx_HAS_USB1 TRUE +#define M83xx_HAS_USB2 TRUE +#elif MPC83XX_CHIP_TYPE == 8360 +#define M83xx_HAS_PCI TRUE +#define M83xx_HAS_QE TRUE +#endif + +#if !defined(ASM) + +#include +#include + +/* Offset Register Access Reset Section/Page */ +/* System Configuration Registers */ +typedef struct m83xxSysConRegisters_ { + volatile uint32_t immrbar; /* 0x0_00000 Internal memory map base address register R/W 0xFF40_0000 5.2.4.1/5-5 */ + uint8_t reserved0_0004[0x00008-0x00004];/* 0x0_0004 Reserved, should be cleared */ + volatile uint32_t altcbar; /* 0x0_0008 Alternate configuration base address register R/W 0x0000_0000 5.2.4.2/5-7 */ + uint8_t reserved0_000C[0x00020-0x0000C];/* 0x0_000C--0x0_001C Reserved, should be cleared */ + volatile uint32_t lblawbar0; /* 0x0_0020 LBC local access window 0 base address register R/W 0x0000_00001 5.2.4.3/5-7 */ + volatile uint32_t lblawar0; /* 0x0_0024 LBC local access window 0 attribute register R/W 0x0000_00002 5.2.4.4/5-8 */ + volatile uint32_t lblawbar1; /* 0x0_0028 LBC local access window 1 base address register R/W 0x0000_0000 5.2.4.3/5-7 */ + volatile uint32_t lblawar1; /* 0x0_002C LBC local access window 1 attribute register R/W 0x0000_0000 5.2.4.4/5-8 */ + volatile uint32_t lblawbar2; /* 0x0_0030 LBC local access window 2 base address register R/W 0x0000_0000 5.2.4.3/5-7 */ + volatile uint32_t lblawar2; /* 0x0_0034 LBC local access window 2 attribute register R/W 0x0000_0000 5.2.4.4/5-8 */ + volatile uint32_t lblawbar3; /* 0x0_0038 LBC local access window 3 base address register R/W 0x0000_0000 5.2.4.3/5-7 */ + volatile uint32_t lblawar3; /* 0x0_003C LBC local access window 3 attribute register R/W 0x0000_0000 5.2.4.4/5-8 */ + uint8_t reserved0_0040[0x00060-0x00040];/* 0x0_0040--0x0_005C Reserved, should be cleared */ + volatile uint32_t pcilawbar0; /* 0x0_0060 PCI local access window0 base address register R/W 0x0000_00003 5.2.4.5/5-9 */ + volatile uint32_t pcilawar0; /* 0x0_0064 PCI local access window0 attribute register R/W 0x0000_00004 5.2.4.6/5-10 */ + volatile uint32_t pcilawbar1; /* 0x0_0068 PCI local access window1 base address register R/W 0x0000_0000 5.2.4.5/5-9 */ + volatile uint32_t pcilawar1; /* 0x0_006C PCI local access window1 attribute register R/W 0x0000_0000 5.2.4.6/5-10 */ + uint8_t reserved0_0070[0x000A0-0x00070];/* 0x0_0070--0x0_009C Reserved, should be cleared */ + volatile uint32_t ddrlawbar0; /* 0x0_00A0 DDR local access window0 base address register R/W 0x0000_00005 5.2.4.7/5-12 */ + volatile uint32_t ddrlawar0; /* 0x0_00A4 DDR local access window0 attribute register R/W 0x0000_00006 5.2.4.8/5-13 */ + volatile uint32_t ddrlawbar1; /* 0x0_00A8 DDR local access window1 base address register R/W 0x0000_0000 5.2.4.7/5-12 */ + volatile uint32_t ddrlawar1; /* 0x0_00AC DDR local access window1 attribute register R/W 0x0000_0000 5.2.4.8/5-13 */ + uint8_t reserved0_00B0[0x00100-0x000B0];/* 0x0_00B0--0x0_0100 Reserved, should be cleared */ + volatile uint32_t sgprl; /* 0x0_0100 general purpose register low (SGPRL) R/W 0x0000_0000 5.3.2.1/5-17 */ + volatile uint32_t sgprh; /* 0x0_0104 general purpose register high (SGPRH) R/W 0x0000_0000 5.3.2.2/5-17 */ + volatile uint32_t spridr; /* 0x0_0108 part and revision ID register (SPRIDR) R 0x0000_0000 5.3.2.3/5-18 */ + uint8_t reserved0_010C[0x00110-0x0010C];/* 0x0_010C--0x0_0110 Reserved, should be cleared */ + volatile uint32_t spcr; /* 0x0_0110 priority configuration register (SPCR) R/W 0x0000_0000 5.3.2.4/5-19 */ + volatile uint32_t sicrl; /* 0x0_0114 I/O configuration register low (SICRL) R/W 0x0000_0000 5.3.2.5/5-21 */ + volatile uint32_t sicrh; /* 0x0_0118 I/O configuration register high (SICRH) R/W 0x0000_00007 5.3.2.6/5-24 */ + uint8_t reserved0_011C[0x00128-0x0011C];/* 0x0_011C--0x0_0128 Reserved */ + volatile uint32_t ddrcdr; /* 0x0_0128 control driver register (DDRCDR) R/W 0x7304_0001 5.3.2.8/5-28 */ + volatile uint32_t ddrdsr; /* 0x0_012C debug status register (DDRDSR) R 0x3300_0000 5.3.2.9/5-30 */ + uint8_t reserved0_0130[0x00150-0x00130];/* 0x0_0130--0x0_015C Reserved */ + volatile uint32_t gpr_1; /* 0x0_0150 General Purpose Register 1 (GPR_1) */ + uint8_t reserved0_0154[0x00200-0x00154];/* 0x0_0154--0x0_01FC Reserved */ +} m83xxSysConRegisters_t; +#define M83xx_SYSCON_SPCR_TBEN (1 << (31-9)) + +/* Watchdog Timer (WDT) Registers */ +typedef struct m83xxWDTRegisters_ { + uint8_t reserved0_0200[0x00204-0x00200];/* 0x0_0200 Reserved, should be cleared */ + volatile uint32_t swcrr; /* 0x0_0204 System watchdog control register R/W 0x0000_0007 5.4.4.1/5-33 */ + volatile uint32_t swcnr; /* 0x0_0208 System watchdog count register R 0x0000_FFFF 5.4.4.2/5-34 */ + uint8_t reserved0_020C[(0x0020E)-0x0020C];/* 0x0_020C Reserved, should be cleared */ + volatile uint16_t swsrr; /* 0x0_020E System watchdog service register R/W 0x0000_0000 5.4.4.3/5-34 */ +} m83xxWDTRegisters_t; + +/* Real Time Clock Module Registers (RTC) */ +typedef struct m83xxRTCRegisters_ { + volatile uint32_t rtcnr; /* 0x0_0300 Real time counter control register R/W 0x0000_0000 5.5.5.1/5-40 */ + volatile uint32_t rtldr; /* 0x0_0304 Real time counter load register R/W 0x0000_0000 5.5.5.2/5-41 */ + volatile uint32_t rtpsr; /* 0x0_0308 Real time counter prescale register R/W 0x0000_0000 5.5.5.3/5-41 */ + volatile uint32_t rtctr; /* 0x0_030C Real time counter register R 0x0000_0000 5.5.5.4/5-42 */ + volatile uint32_t rtevr; /* 0x0_0310 Real time counter event register R/W 0x0000_0000 5.5.5.5/5-42 */ + volatile uint32_t rtalr; /* 0x0_0314 Real time counter alarm register R/W 0xFFFF_FFFF 5.5.5.6/5-43 */ + uint8_t reserved0_0314[0x00320-0x00318];/* 0x0_0318--0x0_031F Reserved; should be cleared */ +} m83xxRTCRegisters_t; + + /* Periodic Interval Timer (PIT) Registers */ +typedef struct m83xxPITRegisters_ { + volatile uint32_t ptcnr; /* 0x0_0400 Periodic interval timer control register R/W 0x0000_0000 5.6.5.1/5-47 */ + volatile uint32_t ptldr; /* 0x0_0404 Periodic interval timer load register R/W 0x0000_0000 5.6.5.2/5-48 */ + volatile uint32_t ptpsr; /* 0x0_0408 Periodic interval timer prescale register R/W 0x0000_0000 5.6.5.3/5-49 */ + volatile uint32_t ptctr; /* 0x0_040C Periodic interval timer counter register R 0x0000_0000 5.6.5.4/5-49 */ + volatile uint32_t ptevr; /* 0x0_0410 Periodic interval timer event register R/W 0x0000_0000 5.6.5.5/5-50 */ + uint8_t reserved0_0414[0x00500-0x00414]; /* 0x0_0414--0x0_041F Reserved, should be cleared */ +} m83xxPITRegisters_t; + + /* Global Timers Module 1/2 */ +#define M83xxGTIdx(n) (n&3) +#define M83xxGTLowIdx(n) (n&1) +#define M83xxGTHighIdx(n) (((n)>>1)&1) +#define M83xxGTModIdx(n) (((n)>>2)&1) + +#define M83xxGTIdxCnt (4) +#define M83xxGTLowCnt (2) +#define M83xxGTHighCnt (2) +#define M83xxGTModCnt (2) + +typedef struct m83xxGTMRegisters_ { + struct { + volatile uint8_t reg; /* 0x0_0500 Timer 1+2/3+4 global timers configuration register R/W 0x00 5.7.5.1/5-57 */ + uint8_t reserved0_0501[0x00504-0x00501]; /* 0x0_0501--0x0_0503 Reserved, should be cleared */ + } gtcfr[M83xxGTHighCnt]; + uint8_t reserved0_0508[0x00510-0x00508]; /* 0x0_0508--0x0_050f Reserved, should be cleared */ + struct { + volatile uint16_t gtmdr[M83xxGTLowCnt]; /* 0x0_0510 Timer 1/2 global timers mode register R/W 0x0000 5.7.5.2/5-60 */ + volatile uint16_t gtrfr[M83xxGTLowCnt]; /* 0x0_0514 Timer 1/2 global timers reference register R/W 0x0000 5.7.5.3/5-62 */ + volatile uint16_t gtcpr[M83xxGTLowCnt]; /* 0x0_0518 Timer 1/2 global timers capture register R/W 0x0000 5.7.5.4/5-62 */ + volatile uint16_t gtcnr[M83xxGTLowCnt]; /* 0x0_051C Timer 1/2 global timers counter register R/W 0x0000 5.7.5.5/5-63 */ + } gt_tim_regs[M83xxGTHighCnt]; + volatile uint16_t gtevr[M83xxGTIdxCnt]; /* 0x0_0530 Timer 1-4 global timers event register Special 0x0000 5.7.5.6/5-63 */ + volatile uint16_t gtpsr[M83xxGTIdxCnt]; /* 0x0_0538 Timer 1-4 global timers prescale register R/W 0x0003 5.7.5.7/5-64 */ + uint8_t reserved0_0540[0x00600-0x00540]; /* 0x0_0540--0x0_05fc Reserved */ +} m83xxGTMRegisters_t; + + /* Integrated Programmable Interrupt Controller (IPIC) */ +typedef struct m83xxIPICRegisters_ { + volatile uint32_t sicfr; /* 0x0_0700 System global interrupt configuration register R/W 0x0000_0000 8.5.1/8-8 */ + volatile uint32_t sivcr; /* 0x0_0704 System global interrupt vector register R 0x0000_0000 8.5.2/8-9 */ + volatile uint32_t sipnr[2]; /* 0x0_0708 System internal interrupt pending register H/L R 0x0000_0000 8.5.3/8-11 */ + volatile uint32_t siprr[4]; /* 0x0_0710 System internal interrupt group A-D priority register R/W 0x0530_9770 8.5.4/8-14 */ + volatile uint32_t simsr[2]; /* 0x0_0720 System internal interrupt mask register H/L R/W 0x0000_0000 8.5.6/8-15 */ + uint8_t reserved0_0728[0x0072C-0x00728]; /* 0x0_072C--0x0_0728 Reserved, should be cleared */ + volatile uint32_t sepnr; /* 0x0_072C System external interrupt pending register R/W Special 8.5.8/8-18 */ + volatile uint32_t smprr[2]; /* 0x0_0730 System mixed interrupt group A/B priority register R/W 0x0530_9770 8.5.9/8-18 */ + volatile uint32_t semsr; /* 0x0_0738 System external interrupt mask register R/W 0x0000_0000 8.5.11/8-20 */ + volatile uint32_t secnr; /* 0x0_073C System external interrupt control register R/W 0x0000_0000 8.5.12/8-21 */ + volatile uint32_t sersr; /* 0x0_0740 System error status register R/W 0x0000_0000 8.5.13/8-22 */ + volatile uint32_t sermr; /* 0x0_0744 System error mask register R/W $ 8.5.14/8-23 */ + volatile uint32_t sercr; /* 0x0_0748 System error control register R/W 0x0000_0000 8.5.15/8-24 */ + uint8_t reserved0_074C[0x00750-0x0074C]; /* 0x0_074C--0x0_074F Reserved, should be cleared */ + volatile uint32_t sifcr[2]; /* 0x0_0750 System internal interrupt force register H/L R/W 0x0000_0000 8.5.16/8-25 */ + volatile uint32_t sefcr; /* 0x0_0758 System external interrupt force register R/W 0x0000_0000 8.5.17/8-26 */ + volatile uint32_t serfr; /* 0x0_075C System error force register R/W 0x0000_0000 8.5.18/8-26 */ + volatile uint32_t scvcr; /* 0x0_0760 System critical interrupt vector register R 0x0000_0000 8.5.19/8-27 */ + volatile uint32_t smvcr; /* 0x0_0764 System management interrupt vector register R 0x0000_0000 8.5.20/8-27 */ + uint8_t reserved0_0760[0x00800-0x00768]; /* 0x0_0768--0x0_07FF Reserved, should be cleared */ +} m83xxIPICRegisters_t; + +/* get vector number from vector register content */ +#define MPC83xx_VCR_TO_VEC(regval) ((regval) & 0x7f) + + + /* System Arbiter Registers */ +typedef struct m83xxARBRegisters_ { + volatile uint32_t acr; /* 0x0_0800 Arbiter configuration register R/W 0x0000_0000 6.2.1/6-2 */ + volatile uint32_t atr; /* 0x0_0804 Arbiter timers register R/W 0x00FF_00FF 6.2.2/6-4 */ + uint8_t reserved0_0808[0x0080C-0x00808]; /* 0x0_0808 Reserved, should be cleared R 0x0000_0000 */ + volatile uint32_t aer; /* 0x0_080C Arbiter event register R/W 0x0000_0000 6.2.3/6-5 */ + volatile uint32_t aidr; /* 0x0_0810 Arbiter interrupt definition register R/W 0x0000_0000 6.2.4/6-6 */ + volatile uint32_t amr; /* 0x0_0814 Arbiter mask register R/W 0x0000_0000 6.2.5/6-7 */ + volatile uint32_t aeatr; /* 0x0_0818 Arbiter event attributes register R 0x0000_0000 6.2.6/6-7 */ + volatile uint32_t aeadr; /* 0x0_081C Arbiter event address register R 0x0000_0000 6.2.7/6-9 */ + volatile uint32_t aerr; /* 0x0_0820 Arbiter event response register R/W 0x0000_0000 6.2.8/6-10 */ + uint8_t reserved0_0824[0x00900-0x00824]; /* 0x0_0824--0x0_08FF Reserved, should be cleared */ +} m83xxARBRegisters_t; + + /* Reset Module */ +typedef struct m83xxRESRegisters_ { + volatile uint32_t rcwlr; /* 0x0_0900 Reset configuration word low register R 0x0000_0000 4.5.1.1/4-32 */ + volatile uint32_t rcwhr; /* 0x0_0904 Reset configuration word high register R 0x0000_0000 4.5.1.2/4-32 */ + uint8_t reserved0_0908[0x00910-0x00908]; /* 0x0_0908--0x0_090C Reserved, should be cleared */ + volatile uint32_t rsr; /* 0x0_0910 Reset status register R/W 0x0000_0000 4.5.1.3/4-33 */ + volatile uint32_t rmr; /* 0x0_0914 Reset mode register R/W 0x0000_0000 4.5.1.4/4-34 */ + volatile uint32_t rpr; /* 0x0_0918 Reset protection register R/W 0x0000_0000 4.5.1.5/4-35 */ + volatile uint32_t rcr; /* 0x0_091C Reset control register R/W 0x0000_0000 4.5.1.6/4-36 */ + volatile uint32_t rcer; /* 0x0_0920 Reset control enable register R/W 0x0000_0000 4.5.1.7/4-36 */ + uint8_t reserved0_0924[0x00A00-0x00924]; /* 0x0_0924--0x0_09FC Reserved, should be cleared */ +} m83xxRESRegisters_t; + + /* Clock Module */ +typedef struct m83xxCLKRegisters_ { + volatile uint32_t spmr; /* 0x0_0A00 System PLL mode register R 0x0000_0000 4.5.2.1/4-37 */ + volatile uint32_t occr; /* 0x0_0A04 Output clock control register R/W 0x0000_0000 4.5.2.2/4-38 */ + volatile uint32_t sccr; /* 0x0_0A08 System clock control register R/W 0xFFFF_FFFF 4.5.2.3/4-40 */ + uint8_t reserved0_0A08[0x00B00-0x00A0C]; /* 0x0_0A0C--0x0_0AFC Reserved, should be cleared */ +} m83xxCLKRegisters_t; + /* Power Management Control Module */ +typedef struct m83xxPMCRegisters_ { + volatile uint32_t pmccr; /* 0x0_0B00 Power management controller configuration register R/W 0x0000_0000 5.8.3.1/5-69 */ + volatile uint32_t pmcer; /* 0x0_0B04 Power management controller event register R/W 0x0000_0000 5.8.3.2/5-70 */ + volatile uint32_t pmcmr; /* 0x0_0B08 Power management controller mask register R/W 0x0000_0000 5.8.3.3/5-71 */ + uint8_t reserved0_0B10[0x00C00-0x00B0C]; /* 0x0_0B0C--0x0_0BFC Reserved, should be cleared */ +} m83xxPMCRegisters_t; + /* GPIO1 Registers */ +typedef struct m83xxGPIORegisters_ { + volatile uint32_t gpdir; /* 0x0_0C00 GPIO1/2 direction register R/W 0x0000_0000 21.3.1/21-3 */ + volatile uint32_t gpdr; /* 0x0_0C04 GPIO1/2 open drain register R/W 0x0000_0000 21.3.2/21-4 */ + volatile uint32_t gpdat; /* 0x0_0C08 GPIO1/2 data register R/W 0x0000_0000 21.3.3/21-4 */ + volatile uint32_t gpier; /* 0x0_0C0C GPIO1/2 interrupt event register R/W Undefined 21.3.4/21-5 */ + volatile uint32_t gpimr; /* 0x0_0C10 GPIO1/2 interrupt mask register R/W 0x0000_0000 21.3.5/21-5 */ + volatile uint32_t gpicr; /* 0x0_0C14 GPIO1/2 external interrupt control register R/W 0x0000_0000 21.3.6/21-6 */ + uint8_t reserved0_0C1C[0x00D00-0x00C18]; /* 0x0_0C18--0x0_0CFF Reserved, should be cleared */ +} m83xxGPIORegisters_t; + + /* DLL */ +typedef struct m83xxDLLRegisters_ { + uint8_t reserved0_1000[0x01010-0x01000]; /* 0x0_1000--0x0_100F Reserved, should be cleared */ + volatile uint32_t mckenr; /* 0x0_1010 MCK enable register (MCKENR) R/W 0xFC00_0000 4.5.3/4-41 */ + uint8_t reserved0_1014[0x01100-0x01014]; /* 0x0_1014--0x0_10FF Reserved, should be cleared */ + volatile uint32_t reserved0_1100; /* 0x0_1100 Reserved. Reset value should be preserved. R/W 0x0500_0280 */ + volatile uint32_t reserved0_1104; /* 0x0_1104 Reserved. Reset value should be preserved. R/W 0x8004_0810 */ + volatile uint32_t dllovr; /* 0x0_1108 DLL override register (DLLOVR) R/W 0x0000_0000 22.4.1/22-4 */ + volatile uint32_t dllsr; /* 0x0_110C DLL status register (DLLSR) R 0x0000_0000 22.4.2/22-4 */ + volatile uint32_t dllck; /* 0x0_1110 DLL clock register (DLLCK) R/W 0xFC00_0000 22.4.3/22-5 */ + uint8_t reserved0_1110[0x01200-0x01114]; /* 0x0_1114--0x0_11FF Reserved, should be cleared */ +} m83xxDLLRegisters_t; + + /* DDR Memory Controller Memory Map */ +typedef struct m83xxDDRRegisters_ { + volatile uint32_t cs0_bnds; /* 0x0_2000 Chip select 0 memory bounds R/W 0x0000_0000 9.4.1.1/9-10 */ + uint8_t reserved0_2004[0x02008-0x02004]; /* 0x0_2004--0x0_2008 Reserved, should be cleared */ + volatile uint32_t cs1_bnds; /* 0x0_2008 Chip select 1 memory bounds R/W 0x0000_0000 */ + uint8_t reserved0_200C[0x02010-0x0200C]; /* 0x0_200C--0x0_2010 Reserved, should be cleared */ + volatile uint32_t cs2_bnds; /* 0x0_2010 Chip select 2 memory bounds R/W 0x0000_0000 */ + uint8_t reserved0_2014[0x02018-0x02014]; /* 0x0_2014--0x0_2018 Reserved, should be cleared */ + volatile uint32_t cs3_bnds; /* 0x0_2018 Chip select 3 memory bounds R/W 0x0000_0000 */ + uint8_t reserved0_201C[0x02080-0x0201C]; /* 0x0_201C--0x0_207F Reserved, should be cleared */ + volatile uint32_t cs0_config; /* 0x0_2080 Chip select 0 configuration R/W 0x0000_0000 9.4.1.2/9-11 */ + volatile uint32_t cs1_config; /* 0x0_2084 Chip select 1 configuration R/W 0x0000_0000 */ + volatile uint32_t cs2_config; /* 0x0_2088 Chip select 2 configuration R/W 0x0000_0000 */ + volatile uint32_t cs3_config; /* 0x0_208C Chip select 3 configuration R/W 0x0000_0000 */ + uint8_t reserved0_2090[0x02100-0x02090]; /* 0x0_2090--0x0_2100 Reserved, should be cleared */ + volatile uint32_t timing_cfg_3; /* 0x0_2100 DDR SDRAM timing configuration 3 R/W 0x0000_0000 9.4.1.3/9-13 */ + volatile uint32_t timing_cfg_0; /* 0x0_2104 DDR SDRAM timing configuration 0 R/W 0x0011_0105 9.4.1.4/9-14 */ + volatile uint32_t timing_cfg_1; /* 0x0_2108 DDR SDRAM timing configuration 1 R/W 0x0000_0000 9.4.1.5/9-16 */ + volatile uint32_t timing_cfg_2; /* 0x0_210C DDR SDRAM timing configuration 2 R/W 0x0000_0000 9.4.1.6/9-18 */ + volatile uint32_t ddr_sdram_cfg; /* 0x0_2110 DDR SDRAM control configuration R/W 0x0200_0000 9.4.1.7/9-20 */ + volatile uint32_t ddr_sdram_cfg_2; /* 0x0_2114 DDR SDRAM control configuration 2 R/W 0x0000_0000 9.4.1.8/9-22 */ + volatile uint32_t ddr_sdram_mode; /* 0x0;_2118 DDR SDRAM mode configuration R/W 0x0000_0000 9.4.1.9/9-24 */ + volatile uint32_t ddr_sdram_mode_2; /* 0x0_211C DDR SDRAM mode configuration 2 R/W 0x0000_0000 9.4.1.10/9-24 */ + volatile uint32_t ddr_sdram_md_cntl; /* 0x0_2120 DDR SDRAM mode control R/W 0x0000_0000 9.4.1.11/9-25 */ + volatile uint32_t ddr_sdram_interval; /* 0x0_2124 DDR SDRAM interval configuration R/W 0x0000_0000 9.4.1.12/9-27 */ + volatile uint32_t ddr_data_init; /* 0x0_2128 DDR SDRAM data initialization R/W 0x0000_0000 9.4.1.13/9-28 */ + uint8_t reserved0_212C[0x02130-0x0212C]; /* 0x0_212C Reserved $ $ */ + volatile uint32_t ddr_sdram_clk_cntl; /* 0x0_2130 DDR SDRAM clock control R/W 0x0200_0000 9.4.1.14/9-28 */ + uint8_t reserved0_2134[0x02148-0x02134]; /* 0x0_2140 Reserved $ $ */ + volatile uint32_t ddr_init_address; /* 0x0_2148 DDR training initialization address R/W 0x0000_0000 9.4.1.15/9-29 */ + uint8_t reserved0_214C[0x02BF8-0x0214C]; /* 0x0_214C Reserved $ $ */ + volatile uint32_t ddr_ip_rev1; /* 0x0_2BF8 DDR IP block revision 1 R 0x0002_0200 9.4.1.16/9-30 */ + volatile uint32_t ddr_ip_rev2; /* 0x0_2BFC DDR IP block revision 2 R 0x0000_0000 9.4.1.17/9-30 */ + uint8_t reserved0_2C00[0x02E00-0x02C00]; /* 0x0_2C00 Reserved $ $ */ + volatile uint32_t data_err_inject_hi; /* 0x0_2E00 Memory data path error injection mask high R/W 0x0000_0000 9.4.1.18/9-31 */ + volatile uint32_t data_err_inject_lo; /* 0x0_2E04 Memory data path error injection mask low R/W 0x0000_0000 9.4.1.19/9-31 */ + volatile uint32_t ecc_err_inject; /* 0x0_2E08 Memory data path error injection mask ECC R/W 0x0000_0000 9.4.1.20/9-32 */ + uint8_t reserved0_2E0C[0x02E20-0x02E0C]; /* 0x0_2E0C Reserved $ $ */ + volatile uint32_t capture_data_hi; /* 0x0_2E20 Memory data path read capture high R/W 0x0000_0000 9.4.1.21/9-32 */ + volatile uint32_t capture_data_lo; /* 0x0_2E24 Memory data path read capture low R/W 0x0000_0000 9.4.1.22/9-33 */ + volatile uint32_t capture_ecc; /* 0x0_2E28 Memory data path read capture ECC R/W 0x0000_0000 9.4.1.23/9-33 */ + uint8_t reserved0_2E2C[0x02E40-0x02E2C]; /* 0x0_2E2C Reserved $ $ */ + volatile uint32_t err_detect; /* 0x0_2E40 Memory error detect w1c 0x0000_0000 9.4.1.24/9-33 */ + volatile uint32_t err_disable; /* 0x0_2E44 Memory error disable R/W 0x0000_0000 9.4.1.25/9-34 */ + volatile uint32_t err_int_en; /* 0x0_2E48 Memory error interrupt enable R/W 0x0000_0000 9.4.1.26/9-35 */ + volatile uint32_t capture_attributes; /* 0x0_2E4C Memory error attributes capture R/W 0x0000_0000 9.4.1.27/9-36 */ + volatile uint32_t capture_address; /* 0x0_2E50 Memory error address capture R/W 0x0000_0000 9.4.1.28/9-37 */ + uint8_t reserved0_2E54[0x02E58-0x02E54]; /* 0x0_2E54 Reserved $ $ */ + volatile uint32_t err_sbe; /* 0x0_2E58 Single-Bit ECC memory error management R/W 0x0000_0000 9.4.1.29/9-37 */ + uint8_t reserved0_2E5C[0x2F00-0x2E5C]; +} m83xxDDRRegisters_t; + + /* I2C Controller */ +typedef struct m83xxI2CRegisters_ { + volatile uint8_t i2cadr; /* 0x0_3000 I2C1 address register R/W 0x00 17.3.1.1/17-5 */ + uint8_t reserved0_3001[0x03004-0x03001]; + volatile uint8_t i2cfdr; /* 0x0_3004 I2C1 frequency divider register R/W 0x00 17.3.1.2/17-5 */ + uint8_t reserved0_3005[0x03008-0x03005]; + volatile uint8_t i2ccr; /* 0x0_3008 I2C1 control register R/W 0x00 17.3.1.3/17-6 */ + uint8_t reserved0_3009[0x0300C-0x03009]; + volatile uint8_t i2csr; /* 0x0_300C I2C1 status register R/W 0x81 17.3.1.4/17-8 */ + uint8_t reserved0_300D[0x03010-0x0300D]; + volatile uint8_t i2cdr; /* 0x0_3010 I2C1 data register R/W 0x00 17.3.1.5/17-9 */ + uint8_t reserved0_3011[0x03014-0x03011]; + volatile uint8_t i2cdfsrr; /* 0x0_3014 I2C1 digital filter sampling rate register R/W 0x0001_0000 17.3.1.6/17-10 */ + uint8_t reserved0_3015[0x03018-0x03015]; + uint8_t reserved0_3018[0x03100-0x03018]; /* 0x0_3018-30FF Reserved, should be cleared */ +} m83xxI2CRegisters_t; + + /* DUART */ +typedef struct m83xxDUARTRegisters_ { + union { + volatile uint8_t urbr; /* 0x0_4500 ULCR[DLAB] = 0 UART1 receiver buffer register R 0x00 18.3.1.1/18-6 */ + volatile uint8_t uthr; /* 0x0_4500 ULCR[DLAB] = 0 UART1 transmitter holding register W 0x00 18.3.1.2/18-6 */ + volatile uint8_t udlb; /* 0x0_4500 ULCR[DLAB] = 1 UART1 divisor least significant byte register R/W 0x00 18.3.1.3/18-7 */ + } urbr_uthr_udlb; + union { + volatile uint8_t uier; /* 0x0_4501 ULCR[DLAB] = 0 UART1 interrupt enable register R/W 0x00 18.3.1.4/18-8 */ + volatile uint8_t udmb; /* 0x0_4501 ULCR[DLAB] = 1 UART1 divisor most significant byte register R/W 0x00 18.3.1.3/18-7 */ + } uier_udmb; + union { + volatile uint8_t uiir; /* 0x0_4502 ULCR[DLAB] = 0 UART1 interrupt ID register R 0x01 18.3.1.5/18-9 */ + volatile uint8_t ufcr; /* 0x0_4502 ULCR[DLAB] = 0 UART1 FIFO control register W 0x00 18.3.1.6/18-10 */ + volatile uint8_t uafr; /* 0x0_4502 ULCR[DLAB] = 1 UART1 alternate function register R/W 0x00 18.3.1.12/18-16 */ + } uiir_ufcr_uafr; + volatile uint8_t ulcr; /* 0x0_4503 ULCR[DLAB] = x UART1 line control register R/W 0x00 18.3.1.7/18-11 */ + volatile uint8_t umcr; /* 0x0_4504 ULCR[DLAB] = x UART1 MODEM control register R/W 0x00 18.3.1.8/18-13 */ + volatile uint8_t ulsr; /* 0x0_4505 ULCR[DLAB] = x UART1 line status register R 0x60 18.3.1.9/18-14 */ + volatile uint8_t umsr; /* 0x0_4506 ULCR[DLAB] = x UART1 MODEM status register R 0x00 18.3.1.10/18-15 */ + volatile uint8_t uscr; /* 0x0_4507 ULCR[DLAB] = x UART1 scratch register R/W 0x00 18.3.1.11/18-16 */ + uint8_t reserved0_4508[0x04510-0x04508];/* 0x0_4508-450F Reserved */ + volatile uint8_t udsr; /* 0x0_4510 ULCR[DLAB] = x UART1 DMA status register R 0x01 18.3.1.13/18-17 */ + uint8_t reserved0_4511[0x04600-0x04511];/* 0x0_4511-45FF Reserved */ +} m83xxDUARTRegisters_t; + + /* Local Bus Controller (LBC) Registers */ +typedef struct m83xxLBCRegisters_ { + struct { + volatile uint32_t br; /* 0x0_5000 Base register 0 ,R/W 0x0000_RR01 10.3.1.1/10-11 */ + volatile uint32_t optionsr; /* 0x0_5004 Options register 0 R/W 0x0000_0FF7 10.3.1.2/10-12 */ + } bor[8]; + uint8_t reserved0_5040[0x05068-0x05040];/* 0x0_5040-5067 Reserved */ + volatile uint32_t mar; /* 0x0_5068 UPM address register R/W 0x0000_0000 10.3.1.3/10-18 */ + uint8_t reserved0_506C[0x05070-0x0506C];/* 0x0_506C-506F Reserved */ + volatile uint32_t mamr; /* 0x0_5070 UPMA mode register R/W 0x0000_0000 10.3.1.4/10-19 */ + volatile uint32_t mbmr; /* 0x0_5074 UPMB mode register R/W 0x0000_0000 10.3.1.4/10-19 */ + volatile uint32_t mcmr; /* 0x0_5078 UPMC mode register R/W 0x0000_0000 10.3.1.4/10-19 */ + uint8_t reserved0_507C[0x05084-0x0507C];/* 0x0_507C-5083 Reserved */ + volatile uint32_t mrtpr; /* 0x0_5084 Memory refresh timer prescaler register R/W 0x0000_0000 10.3.1.5/10-21 */ + volatile uint32_t mdr; /* 0x0_5088 UPM data register R/W 0x0000_0000 10.3.1.6/10-22 */ + uint8_t reserved0_508C[0x05094-0x0508C];/* 0x0_508C-5093 Reserved */ + volatile uint32_t lsdmr; /* 0x0_5094 SDRAM mode register R/W 0x0000_0000 10.3.1.7/10-22 */ + uint8_t reserved0_5098[0x050A0-0x05098];/* 0x0_5098-509F Reserved */ + volatile uint32_t lurt; /* 0x0_50A0 UPM refresh timer R/W 0x0000_0000 10.3.1.8/10-24 */ + volatile uint32_t lsrt; /* 0x0_50A4 SDRAM refresh timer R/W 0x0000_0000 10.3.1.9/10-25 */ + uint8_t reserved0_50A8[0x050B0-0x050A8];/* 0x0_50A8-50AF Reserved */ + volatile uint32_t ltesr; /* 0x0_50B0 Transfer error status register Read/ bit-reset 0x0000_0000 10.3.1.10/10-26 */ + volatile uint32_t ltedr; /* 0x0_50B4 Transfer error check disable register R/W 0x0000_0000 10.3.1.11/10-27 */ + volatile uint32_t lteir; /* 0x0_50B8 Transfer error interrupt enable register R/W 0x0000_0000 10.3.1.12/10-27 */ + volatile uint32_t lteatr; /* 0x0_50BC Transfer error attributes register R/W 0x0000_0000 10.3.1.13/10-28 */ + volatile uint32_t ltear; /* 0x0_50C0 Transfer error address register R/W 0x0000_0000 10.3.1.14/10-29 */ + uint8_t reserved0_50C4[0x050D0-0x050C4];/* 0x0_50C4-50CF Reserved */ + volatile uint32_t lbcr; /* 0x0_50D0 Local bus configuration register R/W 0x0000_0000 10.3.1.15/10-29 */ + volatile uint32_t lcrr; /* 0x0_50D4 Clock ratio register R/W 0x8000_0008 10.3.1.16/10-30 */ + uint8_t reserved0_50D8[0x05100-0x050D8];/* 0x0_50D8-50FF Reserved */ +} m83xxLBCRegisters_t; + + /* Serial Peripheral Interface (SPI) */ +typedef struct m83xxSPIRegisters_ { + uint8_t reserved0_7000[0x07020-0x07000];/* 0x0_7000-7020 Reserved, should be cleared */ + volatile uint32_t spmode; /* 0x0_7020 SPI mode register R/W 0x0000_0000 19.4.1.1/19-9 */ + volatile uint32_t spie; /* 0x0_7024 SPI event register R/W 0x0000_0000 19.4.1.2/19-11 */ + volatile uint32_t spim; /* 0x0_7028 SPI mask register R/W 0x0000_0000 19.4.1.3/19-13 */ + volatile uint32_t spcom; /* 0x0_702C SPI command register R/W 0x0000_0000 19.4.1.4/19-14 */ + volatile uint32_t spitd; /* 0x0_7030 SPI transmit register R/W 0x0000_0000 19.4.1.5/19-14 */ + volatile uint32_t spird; /* 0x0_7034 SPI receive register R 0xFFFF_FFFF 19.4.1.6/19-15 */ + uint8_t reserved0_7038[0x07100-0x07038];/* 0x0_7038-70FF Reserved */ +} m83xxSPIRegisters_t; + /* SPIMODE register fields */ +#define MPC83XX_SPIMODE_LOOP (1 << (31- 1)) /* loopback */ +#define MPC83XX_SPIMODE_CI (1 << (31- 2)) /* clock invert */ +#define MPC83XX_SPIMODE_CP (1 << (31- 3)) /* clock phase */ +#define MPC83XX_SPIMODE_DIV16 (1 << (31- 4)) /* divide by 16 */ +#define MPC83XX_SPIMODE_REV (1 << (31- 5)) /* LSB first */ +#define MPC83XX_SPIMODE_M_S (1 << (31- 6)) /* master/slave */ +#define MPC83XX_SPIMODE_EN (1 << (31- 7)) /* enable */ +#define MPC83XX_SPIMODE_LEN(n) ((n) << (31-11)) /* length code */ +#define MPC83XX_SPIMODE_PM(n) ((n) << (31-15)) /* prescaler */ +#define MPC83XX_SPIMODE_OD (1 << (31-19)) /* open drain */ + + /* SPCOM register fields */ +#define MPC83XX_SPCOM_LST (1 << (31- 9)) /* last transfer */ + + /* SPIE/M register fields */ +#define MPC83XX_SPIE_LT (1 << (31-17)) /* last character transmitted */ +#define MPC83XX_SPIE_DNR (1 << (31-18)) /* data not ready */ +#define MPC83XX_SPIE_OV (1 << (31-19)) /* overrun */ +#define MPC83XX_SPIE_UN (1 << (31-20)) /* unterrun */ +#define MPC83XX_SPIE_MME (1 << (31-21)) /* multi-master error */ +#define MPC83XX_SPIE_NE (1 << (31-22)) /* not empty */ +#define MPC83XX_SPIE_NF (1 << (31-23)) /* not full */ + +typedef struct m83xxDMARegisters_ { + /* DMA Registers */ + uint8_t reserved0_8000[0x08030-0x08000];/* 0x0_8000-0x0_802f Reserved */ + volatile uint32_t omisr; /* 0x0_8030 Outbound message interrupt status register Special 0x0000_0000 12.4.1/12-4 */ + volatile uint32_t omimr; /* 0x0_8034 Outbound message interrupt mask register R/W 0x0000_0000 12.4.2/12-6 */ + uint8_t reserved0_8038[0x08050-0x08038];/* 0x0_8038-0x0_804f Reserved */ + volatile uint32_t imr0; /* 0x0_8050 Inbound message register 0 R/W 0x0000_0000 12.4.3/12-7 */ + volatile uint32_t imr1; /* 0x0_8054 Inbound message register 1 R/W 0x0000_0000 12.4.3/12-7 */ + volatile uint32_t omr0; /* 0x0_8058 Outbound message register 0 R/W 0x0000_0000 12.4.4/12-7 */ + volatile uint32_t omr1; /* 0x0_805C Outbound message register 1 R/W 0x0000_0000 12.4.4/12-7 */ + volatile uint32_t odr; /* 0x0_8060 Outbound doorbell register R/W 0x0000_0000 12.4.5/12-8 */ + uint8_t reserved0_8064[0x08068-0x08064];/* 0x0_8064-0x0_8067 Reserved */ + volatile uint32_t idr; /* 0x0_8068 Inbound doorbell register R/W 0x0000_0000 12.4.5/12-8 */ + uint8_t reserved0_806C[0x08080-0x0806C];/* 0x0_806C-0x0_807F Reserved */ + volatile uint32_t imisr; /* 0x0_8080 Inbound message interrupt status register R/W 0x0000_0000 12.4.6/12-9 */ + volatile uint32_t imimr; /* 0x0_8084 Inbound message interrupt mask register R/W 0x0000_0000 12.4.7/12-11 */ + uint8_t reserved0_8088[0x080A8-0x08088];/* 0x0_8088-0x0_80A7 Reserved */ + struct m83xxDMAChannelRegisters_ { + uint8_t reserved0_80A8[0x08100-0x080A8];/* 0x0_80A8-0x0_80FF Reserved */ + volatile uint32_t dmamr0; /* 0x0_8100 DMA 0 mode register R/W 0x0000_0000 12.4.8.1/12-12 */ + volatile uint32_t dmasr0; /* 0x0_8104 DMA 0 status register R/W 0x0000_0000 12.4.8.2/12-14 */ + volatile uint32_t dmacdar0; /* 0x0_8108 DMA 0 current descriptor address register R/W 0x0000_0000 12.4.8.3/12-15 */ + uint8_t reserved0_810C[0x08110-0x0810C];/* 0x0_810C-0x0_810F Reserved */ + volatile uint32_t dmasar0; /* 0x0_8110 DMA 0 source address register R/W 0x0000_0000 12.4.8.4/12-16 */ + uint8_t reserved0_8114[0x08118-0x08114];/* 0x0_8114-0x0_8117 Reserved */ + volatile uint32_t dmadar0; /* 0x0_8118 DMA 0 destination address register R/W 0x0000_0000 12.4.8.5/12-16 */ + uint8_t reserved0_811C[0x08120-0x0811C];/* 0x0_8120-0x0_811C Reserved */ + volatile uint32_t dmabcr0; /* 0x0_8120 DMA 0 byte count register R/W 0x0000_0000 12.4.8.6/12-17 */ + volatile uint32_t dmandar0; /* 0x0_8124 DMA 0 next descriptor address register R/W 0x0000_0000 12.4.8.7/12-17 */ + }chan[4]; + volatile uint32_t dmagsr; /* 0x0_82A8 DMA general status register R 0x0000_0000 12.4.8.8/12-18 */ + uint8_t reserved0_82AC[0x082FF-0x082AC]; /* 0x0_82AC-0x0_82FF Reserved, should be cleared */ +} m83xxDMARegisters_t; + +/* Registers in DMA section use little-endian byte order */ + +/* DMA mode register */ +#define MPC83XX_DMAMR_DRCNT_1 (5 << 24) +#define MPC83XX_DMAMR_DRCNT_2 (6 << 24) +#define MPC83XX_DMAMR_DRCNT_4 (7 << 24) +#define MPC83XX_DMAMR_DRCNT_8 (8 << 24) +#define MPC83XX_DMAMR_DRCNT_16 (9 << 24) +#define MPC83XX_DMAMR_DRCNT_32 (0xA << 24) + +#define MPC83XX_DMAMR_BWC_1 (0 << 21) +#define MPC83XX_DMAMR_BWC_2 (1 << 21) +#define MPC83XX_DMAMR_BWC_4 (2 << 21) +#define MPC83XX_DMAMR_BWC_8 (3 << 21) +#define MPC83XX_DMAMR_BWC_16 (4 << 21) + +#define MPC83XX_DMAMR_DMSEN (1 << 20) +#define MPC83XX_DMAMR_IRQS (1 << 19) +#define MPC83XX_DMAMR_EMSEN (1 << 18) + +#define MPC83XX_DMAMR_DAHTS_1 (0 << 16) +#define MPC83XX_DMAMR_DAHTS_2 (1 << 16) +#define MPC83XX_DMAMR_DAHTS_4 (2 << 16) +#define MPC83XX_DMAMR_DAHTS_8 (3 << 16) + +#define MPC83XX_DMAMR_SAHTS_1 (0 << 14) +#define MPC83XX_DMAMR_SAHTS_2 (1 << 14) +#define MPC83XX_DMAMR_SAHTS_4 (2 << 14) +#define MPC83XX_DMAMR_SAHTS_8 (3 << 14) + +#define MPC83XX_DMAMR_DAHE (1 << 13) +#define MPC83XX_DMAMR_SAHE (1 << 12) + +#define MPC83XX_DMAMR_PRC_PCI_READ (0 << 10) +#define MPC83XX_DMAMR_PRC_PCI_READ_LINE (1 << 10) +#define MPC83XX_DMAMR_PRC_PCI_READ_MULTIPLE (2 << 10) + +#define MPC83XX_DMAMR_EOIIE (1 << 7) +#define MPC83XX_DMAMR_TEM (1 << 3) +#define MPC83XX_DMAMR_CTM (1 << 2) +#define MPC83XX_DMAMR_CC (1 << 1) +#define MPC83XX_DMAMR_CS (1 << 0) + +/* DMA status register */ +#define MPC83XX_DMASR_TE (1 << 7) +#define MPC83XX_DMASR_CB (1 << 2) +#define MPC83XX_DMASR_EOSI (1 << 1) +#define MPC83XX_DMASR_EOCDI (1 << 0) + +/* DMA current descriptor address register */ +#define MPC83XX_DMACDAR_SNEN (1 << 4) +#define MPC83XX_DMACDAR_EOSIE (1 << 3) + +/* DMA next descriptor address register */ +#define MPC83XX_DMANDAR_NSNEN (1 << 4) +#define MPC83XX_DMANDAR_NEOSIE (1 << 3) +#define MPC83XX_DMANDAR_EOTD (1 << 0) + + +typedef struct m83xxPCICfgRegisters_ { + /* PCI1 Software Configuration Registers */ + volatile uint32_t config_address; /* 0x0_8300 PCI1 CONFIG_ADDRESS W 13.3.1.1/13-16 */ + volatile uint32_t config_data; /* 0x0_8304 PCI1 CONFIG_DATA R/W 13.3.1.2/13-18 */ + volatile uint32_t int_ack; /* 0x0_8308 PCI1 INT_ACK R 13.3.1.3/13-18 */ + uint8_t reserved0_830C[0x08380-0x0830C]; /* 0x0_830C-0x0_837F Reserved */ +} m83xxPCICfgRegisters_t; + +typedef struct m83xxPCIIosRegisters_ { + /* Sequencer (IOS) */ + volatile uint32_t potar0; /* 0x0_8400 PCI outbound translation address register 0 R/W 0x0000_0000 11.4.1/11-3 */ + uint8_t reserved0_8404[0x08408-0x08404];/* 0x0_8404 Reserved */ + volatile uint32_t pobar0; /* 0x0_8408 PCI outbound base address register 0 R/W 0x0000_0000 11.4.2/11-3 */ + uint8_t reserved0_840C[0x08410-0x0840C];/* 0x0_840C Reserved */ + volatile uint32_t pocmr0; /* 0x0_8410 PCI outbound comparison mask register 0 R/W 0x0000_0000 11.4.3/11-4 */ + uint8_t reserved0_8414[0x08418-0x08414];/* 0x0_8414 Reserved */ + volatile uint32_t potar1; /* 0x0_8418 PCI outbound translation address register 1 R/W 0x0000_0000 11.4.1/11-3 */ + uint8_t reserved0_841C[0x08420-0x0841C];/* 0x0_841C Reserved */ + volatile uint32_t pobar1; /* 0x0_8420 PCI outbound base address register 1 R/W 0x0000_0000 11.4.2/11-3 */ + uint8_t reserved0_8424[0x08428-0x08424];/* 0x0_8424 Reserved */ + volatile uint32_t pocmr1; /* 0x0_8428 PCI outbound comparison mask register 1 R/W 0x0000_0000 11.4.3/11-4 */ + uint8_t reserved0_842C[0x08430-0x0842C];/* 0x0_842C Reserved */ + volatile uint32_t potar2; /* 0x0_8430 PCI outbound translation address register 2 R/W 0x0000_0000 11.4.1/11-3 */ + uint8_t reserved0_8434[0x08438-0x08434];/* 0x0_8434 Reserved */ + volatile uint32_t pobar2; /* 0x0_8438 PCI outbound base address register 2 R/W 0x0000_0000 11.4.2/11-3 */ + uint8_t reserved0_843C[0x08440-0x0843C];/* 0x0_843C Reserved */ + volatile uint32_t pocmr2; /* 0x0_8440 PCI outbound comparison mask register 2 R/W 0x0000_0000 11.4.3/11-4 */ + uint8_t reserved0_8444[0x08448-0x08444];/* 0x0_8444 Reserved */ + volatile uint32_t potar3; /* 0x0_8448 PCI outbound translation address register 3 R/W 0x0000_0000 11.4.1/11-3 */ + uint8_t reserved0_844C[0x08450-0x0844C];/* 0x0_844C Reserved */ + volatile uint32_t pobar3; /* 0x0_8450 PCI outbound base address register 3 R/W 0x0000_0000 11.4.2/11-3 */ + uint8_t reserved0_8454[0x08458-0x08454];/* 0x0_8454 Reserved */ + volatile uint32_t pocmr3; /* 0x0_8458 PCI outbound comparison mask register 3 R/W 0x0000_0000 11.4.3/11-4 */ + uint8_t reserved0_845C[0x08460-0x0845C];/* 0x0_845C Reserved */ + volatile uint32_t potar4; /* 0x0_8460 PCI outbound translation address register 4 R/W 0x0000_0000 11.4.1/11-3 */ + uint8_t reserved0_8464[0x08468-0x08464];/* 0x0_8464 Reserved */ + volatile uint32_t pobar4; /* 0x0_8468 PCI outbound base address register 4 R/W 0x0000_0000 11.4.2/11-3 */ + uint8_t reserved0_846C[0x08470-0x0846C];/* 0x0_846C Reserved */ + volatile uint32_t pocmr4; /* 0x0_8470 PCI outbound comparison mask register 4 R/W 0x0000_0000 11.4.3/11-4 */ + uint8_t reserved0_8474[0x08478-0x08474];/* 0x0_8474 Reserved */ + volatile uint32_t potar5; /* 0x0_8478 PCI outbound translation address register 5 R/W 0x0000_0000 11.4.1/11-3 */ + uint8_t reserved0_847C[0x08480-0x0847C];/* 0x0_847C Reserved */ + volatile uint32_t pobar5; /* 0x0_8480 PCI outbound base address register 5 R/W 0x0000_0000 11.4.2/11-3 */ + uint8_t reserved0_8484[0x08488-0x08484];/* 0x0_8484 Reserved */ + volatile uint32_t pocmr5; /* 0x0_8488 PCI outbound comparison mask register 5 R/W 0x0000_0000 11.4.3/11-4 */ + uint8_t reserved0_848C[0x084F0-0x0848C];/* 0x0_848C Reserved */ + volatile uint32_t pmcr; /* 0x0_84F0 Power management control register R/W 0x0000_0000 11.4.4/11-5 */ + uint8_t reserved0_84F4[0x084F8-0x084F4];/* 0x0_84F4 Reserved */ + volatile uint32_t dtcr; /* 0x0_84F8 Discard timer control register R/W 0x0000_0000 11.4.5/11-6 */ + uint8_t reserved0_84FC[0x08500-0x084FC];/* 0x0_84FC Reserved */ +} m83xxPCIIosRegisters_t; + +typedef struct m83xxPCICtrlRegisters_ { + /* PCI1 Error Management Registers */ + volatile uint32_t pci_esr; /* 0x0_8500 PCI error status register R / w1c 0x0000_0000 13.3.2.1/13-18 */ + volatile uint32_t pci_ecdr; /* 0x0_8504 PCI error capture disable register R/W 0x0000_0000 13.3.2.2/13-19 */ + volatile uint32_t pci_eer; /* 0x0_8508 PCI error enable register R/W 0x0000_0000 13.3.2.3/13-20 */ + volatile uint32_t pci_eatcr; /* 0x0_850C PCI error attributes capture register R/W 0x0000_0000 13.3.2.4/13-21 */ + volatile uint32_t pci_eacr; /* 0x0_8510 PCI error address capture register R 0x0000_0000 13.3.2.5/13-23 */ + volatile uint32_t pci_eeacr; /* 0x0_8514 PCI error extended address capture register R 0x0000_0000 13.3.2.6/13-23 */ + volatile uint32_t pci_edlcr; /* 0x0_8518 PCI error data low capture register R 0x0000_0000 13.3.2.7/13-24 */ + volatile uint32_t pci_edhcr; /* 0x0_851C PCI error data high capture register R 0x0000_0000 13.3.2.8/13-24 */ + /* PCI1 Control and Status Registers */ + volatile uint32_t pci_gcr; /* 0x0_8520 PCI general control register R/W 0x0000_0000 13.3.2.9/13-24 */ + volatile uint32_t pci_ecr; /* 0x0_8524 PCI error control register R/W 0x0000_0000 13.3.2.10/13-25 */ + volatile uint32_t pci_gsr; /* 0x0_8528 PCI general status register R 0x0000_0000 13.3.2.11/13-26 */ + uint8_t reserved0_852C[0x08538-0x0852C];/* 0x0_852C Reserved */ + /* PCI1 Inbound ATU Registers */ + volatile uint32_t pitar2; /* 0x0_8538 PCI inbound translation address register 2 R/W 0x0000_0000 13.3.2.12/13-26 */ + uint8_t reserved0_853C[0x08540-0x0853C];/* 0x0_853C Reserved, should be cleared $ $ */ + volatile uint32_t pibar2; /* 0x0_8540 PCI inbound base address register 2 R/W 0x0000_0000 13.3.2.13/13-27 */ + volatile uint32_t piebar2; /* 0x0_8544 PCI inbound extended base address register 2 R/W 0x0000_0000 13.3.2.14/13-27 */ + volatile uint32_t piwar2; /* 0x0_8548 PCI inbound window attributes register 2 R/W 0x0000_0000 13.3.2.15/13-28 */ + uint8_t reserved0_854C[0x08550-0x0854C];/* 0x0_854C Reserved */ + volatile uint32_t pitar1; /* 0x0_8550 PCI inbound translation address register 1 R/W 0x0000_0000 13.3.2.12/13-26 */ + uint8_t reserved0_8550[0x08558-0x08554];/* 0x0_8554 Reserved, should be cleared $ $ */ + volatile uint32_t pibar1; /* 0x0_8558 PCI inbound base address register 1 R/W 0x0000_0000 13.3.2.13/13-27 */ + volatile uint32_t piebar1; /* 0x0_855C PCI inbound extended base address register 1 R/W 0x0000_0000 13.3.2.14/13-27 */ + volatile uint32_t piwar1; /* 0x0_8560 PCI inbound window attributes register 1 R/W 0x0000_0000 13.3.2.15/13-28 */ + uint8_t reserved0_8564[0x08568-0x08564];/* 0x0_8564 Reserved */ + volatile uint32_t pitar0; /* 0x0_8568 PCI inbound translation address register 0 R/W 0x0000_0000 13.3.2.12/13-26 */ + uint8_t reserved0_856c[0x08570-0x0856c];/* 0x0_856C Reserved, should be cleared $ $ */ + volatile uint32_t pibar0; /* 0x0_8570 PCI inbound base address register 0 R/W 0x0000_0000 13.3.2.13/13-27 */ + uint8_t reserved0_8574[0x08578-0x08574];/* 0x0_8574 Reserved */ + volatile uint32_t piwar0; /* 0x0_8578 PCI inbound window attributes register 0 R/W 0x0000_0000 13.3.2.14/13-27 */ + uint8_t reserved0_857c[0x08580-0x0857c];/* 0x0_857C Reserved, should be cleared $ $ */ + uint8_t reserved0_8580[0x08600-0x08580];/* 0x0_8580 Reserved */ +} m83xxPCICtrlRegisters_t; + +typedef struct m83xxUSB_MPHRegisters_ { + /* USB MPH Controller Registers */ + uint8_t reserved0x2_2000[0x22100-0x22000]; /* 0x2_2000--0x2_20FF Reserved, should be cleared */ + volatile uint16_t caplength; /* 0x2_2100 Capability register length R 0x40 16.3.1.1/16-19 */ + volatile uint16_t hciversion; /* 0x2_2102 Host interface version number R 0x0100 16.3.1.2/16-19 */ + volatile uint32_t hcsparams; /* 0x2_2104 Host crtl. structural parameters R 0x0121_0012 16.3.1.3/16-20 */ + volatile uint32_t hccparams; /* 0x2_2108 Host crtl. capability parameters R 0x0000_0006 16.3.1.4/16-21 */ + uint8_t reserved0x2_210C[0x22140-0x2210C]; /* Reserved */ + volatile uint32_t usbcmd; /* 0x2_2140 USB command R/W 0x0008_nBn0 16.3.2.1/16-23 */ + volatile uint32_t usbsts; /* 0x2_2144 USB status R/W 0x0000_0000 16.3.2.2/16-26 */ + volatile uint32_t usbintr; /* 0x2_2148 USB interrupt enable R/W 0x0000_0000 16.3.2.3/16-28 */ + volatile uint32_t frindex; /* 0x2_214C USB frame index R/W 0x0000_nnnn 16.3.2.4/16-30 */ + uint8_t reserved0x2_2150[0x22154-0x22150]; /* Reserved */ + volatile uint32_t periodiclistbase; /* 0x2_2154 Frame list base address R/W 0xnnnn_0000 16.3.2.6/16-31 */ + volatile uint32_t asynclistaddr; /* 0x2_2158 Next asynchronous list addr R/W 0x0000_0000 16.3.2.8/16-32 */ + volatile uint32_t asyncttsts; /* 0x2_215C Asynchronous buffer status for embedded TT TBD 0x0000_0000 16.3.2.10/16-34 */ + volatile uint32_t burstsize; /* 0x2_2160 Programmable burst size R/W 0x000_1010 16.3.2.11/16-34 */ + volatile uint32_t txfilltuning; /* 0x2_2164 Host TT transmit pre-buffer packet tuning R/W 0x0002_0000 16.3.2.12/16-35 */ + volatile uint32_t txttfilltuning; /* 0x2_2168 Host TT transmit pre-buffer packet tuning R/W 0x0000_0000 16.3.2.13/16-37 */ + uint8_t reserved0x2_216c[0x22170-0x2216c]; /* Reserved */ + volatile uint32_t viewport; /* 0x2_2170 ULPI ULPI Register Access R/W 0x0000_0000 16.3.2.14/16-37 */ + uint8_t reserved0x2_2174[0x22180-0x22174]; /* Reserved */ + volatile uint32_t configflag; /* 0x2_2180 Configured flag register R 0x0000_0001 16.3.2.15/16-39 */ + volatile uint32_t portsc1; /* 0x2_2184 Port status/control 1 R/W 0x8C00_0001 16.3.2.16/16-39 */ + volatile uint32_t portsc2; /* 0x2_2188 Port status/control 2 R/W 0x8C00_0001 16.3.2.16/16-39 */ + uint8_t reserved0x2_218c[0x221A8-0x2218c]; /* Reserved */ + volatile uint32_t usbmode; /* 0x2_21A8 USB device mode R/W 0x0000_0003 16.3.2.18/16-47 */ + uint8_t reserved0x2_21AC[0x22400-0x221AC]; /* Reserved */ + volatile uint32_t snoop1; /* 0x2_2400 Snoop 1 R/W 0x0000_0000 16.3.2.26/16-53 */ + volatile uint32_t snoop2; /* 0x2_2404 Snoop 2 R/W 0x0000_0000 16.3.2.26/16-53 */ + volatile uint32_t age_cnt_thresh; /* 0x2_2408 Age count threshold R/W 0x0000_0000 16.3.2.27/16-54 */ + volatile uint32_t si_ctrl; /* 0x2_240C System interface control R/W 0x0000_0000 16.3.2.28/16-56 */ + volatile uint32_t pri_ctrl; /* 0x2_2410 Priority control R/W 0x0000_0000 16.3.2.29/16-56 */ + uint8_t reserved0x2_2414[0x22500-0x22414]; /* Reserved */ + volatile uint32_t control; /* 0x2_2500 Control R/W 0x0000_0000 16.3.2.30/16-57 */ + uint8_t reserved0x2_2504[0x23000-0x22504]; /* 0x2_2504--0x2_2FFF Reserved, should be cleared */ +} m83xxUSB_MPHRegisters_t; + +typedef struct m83xxUSB_DRRegisters_ { + /* USB DR Controller Registers */ + uint8_t reserved0x2_3000[0x23100-0x23000]; /* 0x2_3000--0x2_30FF Reserved, should be cleared */ + volatile uint16_t caplength; /* 0x2_3100 Capability register length R 0x40 16.3.1.1/16-19 */ + volatile uint16_t hciversion; /* 0x2_3102 Host interface version number R 0x0100 16.3.1.2/16-19 */ + volatile uint32_t hcsparams; /* 0x2_3104 Host crtl. structural parameters R 0x0111_0011 16.3.1.3/16-20 */ + volatile uint32_t hccparams; /* 0x2_3108 Host crtl. capability parameters R 0x0000_0006 16.3.1.4/16-21 */ + uint8_t reserved0x2_310c[0x23120-0x2310C]; /* 0x2_310c--0x2_311f Reserved */ + volatile uint32_t dciversion; /* 0x2_3120 Device interface version number R 0x0001 16.3.1.5/16-22 */ + volatile uint32_t dccparams; /* 0x2_3124 Device controller parameters R 0x0000_0186 16.3.1.6/16-22 */ + uint8_t reserved0x2_3128[0x23140-0x23128]; /* 0x2_3128--0x2_313f Reserved */ + volatile uint32_t usbcmd; /* 0x2_3140 USB command R/W 0x0008_nBn0 16.3.2.1/16-23 */ + volatile uint32_t usbsts; /* 0x2_3144 USB status R/W 0x0000_0000 16.3.2.2/16-26 */ + volatile uint32_t usbintr; /* 0x2_3148 USB interrupt enable R/W 0x0000_0000 16.3.2.3/16-28 */ + volatile uint32_t frindex; /* 0x2_314C USB frame index R/W 0x0000_nnnn 16.3.2.4/16-30 */ + uint8_t reserved0x2_3150[0x23154-0x23150]; /* 0x2_3150--0x2_3153 Reserved */ + union { + volatile uint32_t periodiclistbase; /* 0x2_3154 Frame list base address R/W 0xnnnn_0000 16.3.2.6/16-31 */ + volatile uint32_t deviceaddr; /* 0x2_3154 USB device address R/W 0x0000_0000 16.3.2.7/16-32 */ + } perbase_devaddr; + union { + volatile uint32_t asynclistaddr; /* 0x2_3158 Next asynchronous list addr (host mode) R/W 0x0000_0000 16.3.2.8/16-32 */ + volatile uint32_t addr; /* 0x2_3158 ENDPOINT Address at endpoint list (device mode) R/W 0x0000_0000 16.3.2.9/16-33 */ + } async_addr; + uint8_t reserved0x2_315c[0x23160-0x2315c]; /* 0x2_315c--0x2_315f Reserved */ + volatile uint32_t burstsize; /* 0x2_3160 Programmable burst size R/W 0x0000_1010 16.3.2.11/16-34 */ + volatile uint32_t txfilltuning; /* 0x2_3164 Host TT transmit pre-buffer packet tuning R/W 0x0002_0000 16.3.2.12/16-35 */ + uint8_t reserved0x2_3168[0x23170-0x23168]; /* 0x2_3168--0x2_316f Reserved */ + volatile uint32_t viewport; /* 0x2_3170 ULPI ULPI Register Access R/W 0x0000_0000 16.3.2.14/16-37 */ + uint8_t reserved0x2_3174[0x23180-0x23174]; /* 0x2_3174--0x2_317F Reserved */ + volatile uint32_t configflag; /* 0x2_3180 Configured flag register R 0x0000_0001 16.3.2.15/16-39 */ + volatile uint32_t portsc1; /* 0x2_3184 Port status/control R/W 0x9C00_0000 16.3.2.16/16-39 */ + uint8_t reserved0x2_3188[0x231A4-0x23188]; /* 0x2_3188--0x2_31A3 Reserved */ + volatile uint32_t otgsc; /* 0x2_31A4 On-the-Go status and control R/W 0x0000_0001 16.3.2.17/16-44 */ + volatile uint32_t usbmode; /* 0x2_31A8 USB device mode R/W 0x0000_0000 16.3.2.18/16-47 */ + volatile uint32_t endptsetupstat; /* 0x2_31AC Endpoint setup status R/W 0x0000_0000 16.3.2.19/16-48 */ + volatile uint32_t endpointprime; /* 0x2_31B0 Endpoint initialization R/W 0x0000_0000 16.3.2.20/16-48 */ + volatile uint32_t endptflush; /* 0x2_31B4 Endpoint de-initialize R/W 0x0000_0000 16.3.2.21/16-49 */ + volatile uint32_t endptstatus; /* 0x2_31B8 Endpoint status R 0x0000_0000 16.3.2.22/16-50 */ + volatile uint32_t endptcomplete; /* 0x2_31BC Endpoint complete R/W 0x0000_0000 16.3.2.23/16-50 */ + volatile uint32_t endptctrl[6]; /* 0x2_31C0 Endpoint control 0 R/W 0x0080_0080 16.3.2.24/16-51 */ + uint8_t reserved0x2_31D8[0x23400-0x231D8]; /* 0x2_31D8--0x2_33ff Reserved */ + volatile uint32_t snoop1; /* 0x2_3400 Snoop 1 R/W 0x0000_0000 16.3.2.26/16-53 */ + volatile uint32_t snoop2; /* 0x2_3404 Snoop 2 R/W 0x0000_0000 16.3.2.26/16-53 */ + volatile uint32_t age_cnt_thresh; /* 0x2_3408 Age count threshold R/W 0x0000_0000 16.3.2.27/16-54 */ + volatile uint32_t pri_ctrl; /* 0x2_340C Priority control R/W 0x0000_0000 16.3.2.29/16-56 */ + volatile uint32_t si_ctrl; /* 0x2_3410 System interface control R/W 0x0000_0000 16.3.2.28/16-56 */ + uint8_t reserved0x2_3414[0x23500-0x23414]; /* 0x2_3414--0x2_34ff Reserved */ + volatile uint32_t control; /* 0x2_3500 Control R/W 0x0000_0000 16.3.2.30/16-57 */ + uint8_t reserved0x2_3504[0x24000-0x23504]; /* 0x2_3504--0x2_3FFF Reserved, should be cleared */ +} m83xxUSB_DRRegisters_t; + +#if 0 /* FIXME: to be formatted soon */ + /* Security Engine Address Map Registers */ + /* Controller Registers */ + volatile uint32_t reserved;## /* 0x3_0000--0x3_0FFF Reserved, should be cleared */ + volatile uint32_t imr; /* 0x3_1008 Interrupt mask register R/W 0x0000_0000_0000_0000 14.7.2.1/14-94 */ + volatile uint32_t isr; /* 0x3_1010 Interrupt status register R 0x0000_0000_0000_0000 14.7.2.2/14-96 */ + volatile uint32_t icr; /* 0x3_1018 Interrupt clear register W 0x0000_0000_0000_0000 14.7.2.3/14-96 */ + volatile uint32_t id; /* 0x3_1020 Identification register R 0x0000_0000_0000_00400x 14.7.2.4/14-98 */ + volatile uint32_t euasr; /* 0x3_1028 EU assignment status register R 0xF0F0_F0F0_00FF_F0F0 14.7.2/14-93 */ + volatile uint32_t mcr; /* 0x3_1030 Master control register R/W 0000_0000_0000_0000 14.7.2.5/14-98 */ + /* Channel 1 */ + volatile uint32_t cccr1; /* 0x3_1108 Crypto-channel 1 configuration register R/W 0x0000_0000_0000_0000 14.6.1.1/14-82 */ + volatile uint32_t ccpsr1; /* 0x3_1110 Crypto-channel 1 pointer status register R 0x0000_0000_0000_0007 14.6.1.2/14-85 */ + volatile uint32_t cdpr1; /* 0x3_1140 Crypto-channel 1 current descriptor pointer register R 0x0000_0000_0000_0000 14.6.1.3/14-90 */ + volatile uint32_t */ +0x3_1180--0x3_11BF + DBn /* volatile; uint32_t ff1, /* 0x3_1148 Crypto-channel 1 fetch FIFO address register W 0x0000_0000_0000_0000 14.6.1.4/14-90 Crypto-channel 1 descriptor buffers [0–7] R 0x0000_0000_0000_0000 14.6.1.5/14-91 */ + /* Channel 2-4: FIXME: same layout as channel 1*/ + /* Data Encryption Standard Execution Unit (DEU) */ + volatile uint32_t deumr; /* 0x3_2000 DEU mode register R/W 0x0000_0000_0000_0000 14.5.2.1/14-35 */ + volatile uint32_t deuksr; /* 0x3_2008 DEU key size register R/W 0x0000_0000_0000_0000 14.5.2.2/14-36 */ + volatile uint32_t deudsr; /* 0x3_2010 DEU data size register R/W 0x0000_0000_0000_0000 14.5.2.3/14-36 */ + volatile uint32_t deurcr; /* 0x3_2018 DEU reset control register R/W 0x0000_0000_0000_0000 14.5.2.4/14-37 */ + volatile uint32_t deusr; /* 0x3_2028 DEU status register R 0x0000_0000_0000_0000 14.5.2.5/14-37 */ + volatile uint32_t deuisr; /* 0x3_2030 DEU interrupt status register R 0x0000_0000_0000_0000 14.5.2.6/14-38 */ + volatile uint32_t deuicr; /* 0x3_2038 DEU interrupt control register R/W 0x0000_0000_0000_3000 14.5.2.7/14-40 */ + volatile uint32_t deueug; /* 0x3_2050 DEU EU-Go register W 0x0000_0000_0000_0000 14.5.2.8/14-41 */ + volatile uint32_t deuiv; /* 0x3_2100 DEU initialization vector register R/W 0x0000_0000_0000_0000 14.5.2.9/14-42 */ + volatile uint32_t deuk1; /* 0x3_2400 DEU key 1 register W $ 14.5.2.10/14-42 */ + volatile uint32_t deuk2; /* 0x3_2408 DEU key 2 register W $ 14.5.2.10/14-42 */ + volatile uint32_t deuk3; /* 0x3_2410 DEU key 3 register W $ 14.5.2.10/14-42 */ +0x3_2800--0x3_2FFF +DEU FIFO R/W 0x0000_0000_0000_0000 14.5.2.11/14-42 + /* Advanced Encryption Standard Execution Unit (AESU) */ + volatile uint32_t aesumr; /* 0x3_4000 AESU mode register R/W 0x0000_0000_0000_0000 14.5.6.1/14-68 */ + volatile uint32_t aesuksr; /* 0x3_4008 AESU key size register R/W 0x0000_0000_0000_0000 14.5.6.2/14-71 */ + volatile uint32_t aesudsr; /* 0x3_4010 AESU data size register R/W 0x0000_0000_0000_0000 14.5.6.3/14-71 */ + volatile uint32_t aesurcr; /* 0x3_4018 AESU reset control register R/W 0x0000_0000_0000_0000 14.5.6.4/14-72 */ + volatile uint32_t aesusr; /* 0x3_4028 AESU status register R 0x0000_0000_0000_0000 14.5.6.5/14-73 */ + volatile uint32_t aesuisr; /* 0x3_4030 AESU interrupt status register R 0x0000_0000_0000_0000 14.5.6.6/14-74 */ + volatile uint32_t aesuicr; /* 0x3_4038 AESU interrupt control register R/W 0x0000_0000_0000_1000 14.5.6.7/14-75 */ + volatile uint32_t aesuemr; /* 0x3_4050 AESU end-of-message register W 0x0000_0000_0000_0000 14.5.6.8/14-76 */ +0x3_4100 AESU context memory registers R/W 0x0000_0000_0000_0000 14.5.6.9/14-77 +0x3_4400--0x3_4408 +AESU key memory R/W 0x0000_0000_0000_0000 14.5.6.9.5/14-81 +0x3_4800--0x3_4FFF +AESU FIFO R/W 0x0000_0000_0000_0000 14.5.6.9.6/14-81 + /* Message Digest Execution Unit (MDEU) */ + volatile uint32_t mdeumr; /* 0x3_6000 MDEU mode register R/W 0x0000_0000_0000_0000 14.5.4.1/14-51 */ + volatile uint32_t mdeuksr; /* 0x3_6008 MDEU key size register R/W 0x0000_0000_0000_0000 14.5.4.3/14-55 */ + volatile uint32_t mdeudsr; /* 0x3_6010 MDEU data size register R/W 0x0000_0000_0000_0000 14.5.4.4/14-56 */ + volatile uint32_t mdeurcr; /* 0x3_6018 MDEU reset control register R/W 0x0000_0000_0000_0000 14.5.4.5/14-56 */ + volatile uint32_t mdeusr; /* 0x3_6028 MDEU status register R 0x0000_0000_0000_0000 14.5.4.6/14-57 */ + volatile uint32_t mdeuisr; /* 0x3_6030 MDEU interrupt status register R 0x0000_0000_0000_0000 14.5.4.7/14-58 */ + volatile uint32_t mdeuicr; /* 0x3_6038 MDEU interrupt control register R/W 0x0000_0000_0000_1000 14.5.4.8/14-59 */ + volatile uint32_t mdeueug; /* 0x3_6050 MDEU EU-Go register W 0x0000_0000_0000_0000 14.5.4.10/14-61 */ +0x3_6100--0x3_6120 +MDEU context memory registers R/W 0x0000_0000_0000_0000 14.5.4.11/14-61 +0x3_6400--0x3_647F +MDEU key memory W 0x0000_0000_0000_0000 14.5.4.12/14-62 +0x3_6800--0x3_6FFF +MDEU FIFO W 0x0000_0000_0000_0000 14.5.4.13/14-63 + /* ARC Four Execution Unit (AFEU) */ + volatile uint32_t afeumr; /* 0x3_8000 AFEU mode register R/W 0x0000_0000_0000_0000 14.5.3.1/14-43 */ + volatile uint32_t afeuksr; /* 0x3_8008 AFEU key size register R/W 0x0000_0000_0000_0000 14.5.3.3/14-44 */ + volatile uint32_t afeudsr; /* 0x3_8010 AFEU data size register R/W 0x0000_0000_0000_0000 14.5.3.4/14-45 */ + volatile uint32_t afeurcr; /* 0x3_8018 AFEU reset control register R/W 0x0000_0000_0000_0000 14.5.3.5/14-46 */ + volatile uint32_t afeusr; /* 0x3_8028 AFEU status register R 0x0000_0000_0000_0000 14.5.3.6/14-46 */ + volatile uint32_t afeuisr; /* 0x3_8030 AFEU interrupt status register R 0x0000_0000_0000_0000 14.5.3.7/14-47 */ + volatile uint32_t afeuicr; /* 0x3_8038 AFEU interrupt control register R/W 0x0000_0000_0000_1000 14.5.3.8/14-49 */ + volatile uint32_t afeuemr; /* 0x3_8050 AFEU end of message register W 0x0000_0000_0000_0000 14.5.3.9/14-50 */ +0x3_8100--0x3_81FF +AFEU context memory registers R/W 0x0000_0000_0000_0000 14.5.3.10.1/14-50 +0x3_8200 AFEU context memory pointers R/W 0x0000_0000_0000_0000 14.5.3.10.2/14-51 + volatile uint32_t afeuk0; /* 0x3_8400 AFEU key register 0 W $ 14.5.3.11/14-51 */ + volatile uint32_t afeuk1; /* 0x3_848 AFEU key register 1 W $ 14.5.3.11/14-51 */ +0x3_8800--0x3_8FFF +AFEU FIFO R/W 0x0000_0000_0000_0000 14.5.3.11.1/14-51 + /* Random Number Generator (RNG) */ + volatile uint32_t rngmr; /* 0x3_A000 RNG mode register R/W 0x0000_0000_0000_0000 14.5.5.1/14-63 */ + volatile uint32_t rngdsr; /* 0x3_A010 RNG data size register R/W 0x0000_0000_0000_0000 14.5.5.2/14-64 */ + volatile uint32_t rngrcr; /* 0x3_A018 RNG reset control register R/W 0x0000_0000_0000_0000 14.5.5.3/14-65 */ + volatile uint32_t rngsr; /* 0x3_A028 RNG status register R 0x0000_0000_0000_0000 14.5.5.4/14-65 */ + volatile uint32_t rngisr; /* 0x3_A030 RNG interrupt status register R 0x0000_0000 */ +_0000_0000 +14.5.5.5/14-66 + volatile uint32_t rngicr; /* 0x3_A038 RNG interrupt control register R/W 0x0000_0000 */ +_0000_1000 +14.5.5.6/14-67 + volatile uint32_t rngeug; /* 0x3_A050 RNG EU-Go register W 0x0000_0000 */ +_0000_0000 +14.5.5.7/14-68 +0x3_A800--0x3_AFFF +RNG FIFO R 0x0000_0000 +_0000_0000 +14.5.5.8/14-68 + /* Public Key Execution Unit (PKEU) */ + volatile uint32_t pkeumr; /* 0x3_C000 PKEU mode register R/W 0x0000_0000_0000_0000 14.5.1.1/14-26 */ + volatile uint32_t pkeuksr; /* 0x3_C008 PKEU key size register R/W 0x0000_0000_0000_0000 14.5.1.2/14-28 */ + volatile uint32_t pkeudsr; /* 0x3_C010 PKEU data size register R/W 0x0000_0000_0000_0000 14.5.1.3/14-28 */ + volatile uint32_t pkeurcr; /* 0x3_C018 PKEU reset control register R/W 0x0000_0000_0000_0000 14.5.1.5/14-29 */ + volatile uint32_t pkeusr; /* 0x3_C028 PKEU status register R 0x0000_0000_0000_0000 14.5.1.6/14-30 */ + volatile uint32_t pkeuisr; /* 0x3_C030 PKEU interrupt status register R 0x0000_0000_0000_0000 14.5.1.7/14-31 */ + volatile uint32_t pkeuicr; /* 0x3_C038 PKEU interrupt control register R/W 0x0000_0000_0000_1000 14.5.1.8/14-32 */ + volatile uint32_t pkeuabs; /* 0x3_C040 PKEU AB size register R/W 0x0000_0000_0000_0000 14.5.1.3/14-28 */ + volatile uint32_t pkeueug; /* 0x3_C050 PKEU EU-Go W 0x0000_0000_0000_0000 14.5.1.9/14-33 */ +0x3_C200--0x3_C23F +PKEU parameter memory A0 R/W 0x0000_0000_0000_0000 14.5.1.10/14-34 +0x3_C240--0x3_C27F +PKEU parameter memory A1 R/W 0x0000_0000_0000_0000 +0x3_C280--0x3_C2BF +PKEU parameter memory A2 R/W 0x0000_0000_0000_0000 +0x3_C2C0--0x3_C2FF +PKEU parameter memory A3 R/W 0x0000_0000_0000_0000 +0x3_C300--0x3_C33F +PKEU parameter memory B0 R/W 0x0000_0000_0000_0000 +0x3_C340--0x3_C37F +PKEU parameter memory B1 R/W 0x0000_0000_0000_0000 +0x3_C380--0x3_C3BF +PKEU parameter memory B2 R/W 0x0000_0000_0000_0000 +0x3_C3C0--0x3_C3FF +PKEU parameter memory B3 R/W 0x0000_0000_0000_0000 +0x3_C400--0x3_C4FF +PKEU parameter memory E W 0x0000_0000_0000_0000 +0x3_C800--0x3_C8FF +PKEU parameter memory N R/W 0x0000_0000_0000_0000 +#endif + +typedef struct m83xxRegisters_ { + m83xxSysConRegisters_t syscon; + m83xxWDTRegisters_t wdt; + uint8_t reserved0_0210[0x0300-0x0210]; + m83xxRTCRegisters_t rtc; + uint8_t reserved0_0320[0x0400-0x0320]; + m83xxPITRegisters_t pit; + m83xxGTMRegisters_t gtm[M83xxGTModCnt]; + m83xxIPICRegisters_t ipic; + m83xxARBRegisters_t arb; + m83xxRESRegisters_t res; + m83xxCLKRegisters_t clk; + m83xxPMCRegisters_t pmc; + m83xxGPIORegisters_t gpio[2]; + uint8_t reserved0_0E00[0x1000-0x0E00]; + m83xxDLLRegisters_t dll; + uint8_t reserved0_1200[0x2000-0x1200]; + m83xxDDRRegisters_t ddr; + uint8_t reserved0_2F00[0x3000-0x2F00]; + m83xxI2CRegisters_t i2c[2]; + uint8_t reserved0_3200[0x4000-0x3200]; + uint8_t reserved0_4000[0x4500-0x4000]; + m83xxDUARTRegisters_t duart[2]; + uint8_t reserved0_4700[0x5000-0x4700]; + m83xxLBCRegisters_t lbc; + uint8_t reserved0_5100[0x7000-0x5100]; + m83xxSPIRegisters_t spi; + uint8_t reserved0_7100[0x8000-0x7100]; + m83xxDMARegisters_t dma; + m83xxPCICfgRegisters_t pcicfg[2]; + m83xxPCIIosRegisters_t pciios; + m83xxPCICtrlRegisters_t pcictrl[2]; + uint8_t reserved0_8700[0x22000-0x8700]; + m83xxUSB_MPHRegisters_t usb_mph; + m83xxUSB_DRRegisters_t usb_dr; + volatile tsec_registers tsec[TSEC_COUNT]; +} m83xxRegisters_t; + +extern m83xxRegisters_t mpc83xx; + +static inline void mpc83xx_reset(void) +{ + _ISR_Set_level( 0 ); + + /* Set Reset Protection Register (RPR) to "RSTE" */ + mpc83xx.res.rpr = 0x52535445; + + /* + * Wait for Control Register Enabled in the + * Reset Control Enable Register (RCER). + */ + while (mpc83xx.res.rcer != 0x00000001) { + /* Wait */ + } + + /* Set Software Hard Reset in the Reset Control Register (RCR) */ + mpc83xx.res.rcr = 0x00000002; +} + +#endif /* !defined ASM */ +/* + * some definitions used in assembler startup + */ +/* + * default address of IMMRBAR + */ +#define IMMRBAR_DEFAULT 0xFF400000 +/* + * offsets of some registers + */ +#define LBLAWBAR0_OFF 0x00020 +#define LBLAWAR0_OFF 0x00024 +#define LBLAWBAR1_OFF 0x00028 +#define LBLAWAR1_OFF 0x0002C +#define LBLAWBAR2_OFF 0x00030 +#define LBLAWAR2_OFF 0x00034 +#define LBLAWBAR3_OFF 0x00038 +#define LBLAWAR3_OFF 0x0003C +#define PCILAWBAR0_OFF 0x00060 +#define PCILAWAR0_OFF 0x00064 +#define PCILAWBAR1_OFF 0x00068 +#define PCILAWAR1_OFF 0x0006C +#define DDRLAWBAR0_OFF 0x000A0 +#define DDRLAWAR0_OFF 0x000A4 +#define DDRLAWBAR1_OFF 0x000A8 +#define DDRLAWAR1_OFF 0x000AC + +#define BR0_OFF 0x05000 +#define OR0_OFF 0x05004 +#define BR1_OFF 0x05008 +#define OR1_OFF 0x0500C +#define BR2_OFF 0x05010 +#define OR2_OFF 0x05014 +#define BR3_OFF 0x05018 +#define OR3_OFF 0x0501C +#define BR4_OFF 0x05020 +#define OR4_OFF 0x05024 +#define BR5_OFF 0x05028 +#define OR5_OFF 0x0502C +#define BR6_OFF 0x05030 +#define OR6_OFF 0x05034 +#define BR7_OFF 0x05038 +#define OR7_OFF 0x0503C + +#define MRPTR_OFF 0x05084 +#define LSDMR_OFF 0x05094 +#define LSRT_OFF 0x050A4 +#define LCRR_OFF 0x050d4 + + +#define CS0_BNDS_OFF 0x02000 +#define CS1_BNDS_OFF 0x02008 +#define CS2_BNDS_OFF 0x02010 +#define CS3_BNDS_OFF 0x02018 +#define CS0_CONFIG_OFF 0x02080 +#define CS1_CONFIG_OFF 0x02084 +#define CS2_CONFIG_OFF 0x02088 +#define CS3_CONFIG_OFF 0x0208C +#define TIMING_CFG_3_OFF 0x02100 +#define TIMING_CFG_0_OFF 0x02104 +#define TIMING_CFG_1_OFF 0x02108 +#define TIMING_CFG_2_OFF 0x0210C +#define DDR_SDRAM_CFG_OFF 0x02110 +#define DDR_SDRAM_CFG_2_OFF 0x02114 +#define DDR_SDRAM_MODE_OFF 0x02118 +#define DDR_SDRAM_MODE_2_OFF 0x0211C +#define DDR_SDRAM_MD_CNTL_OFF 0x02120 +#define DDR_SDRAM_INTERVAL_OFF 0x02124 +#define DDR_SDRAM_DATA_INIT_OFF 0x02128 +#define DDRCDR_OFF 0x0012C +#define DDR_SDRAM_CLK_CNTL_OFF 0x02130 +#define DDR_SDRAM_INIT_ADDR_OFF 0x02148 +#define DDR_ERR_DISABLE_OFF 0x02E44 + +/* + * some bits in DDR_SDRAM_CFG register + */ +#define DDR_SDRAM_CFG_MEM_EN (1 << (31- 0)) /* enable memory */ +/* + * bits in DDR_SDRAM_CFG_2 register + */ +#define DDR_SDRAM_CFG_2_D_FRC_SR (1 << (31- 0)) /* force self refresh */ +#define DDR_SDRAM_CFG_2_D_SR_IE (1 << (31- 1)) /* self refresh interrupt en */ +#define DDR_SDRAM_CFG_2_D_DLL_RST_DIS (1 << (31- 2)) /* DLL reset disable */ +#define DDR_SDRAM_CFG_2_D_DQS_CFG_DIF (1 << (31- 5)) /* use diff. DQS */ +#define DDR_SDRAM_CFG_2_D_INIT (1 << (31-27)) /* Init DRAM with pattern */ + +/* + * bits in reset configuration words/registers + */ + /* Local bus clocking mode */ +#define RCWLR_LBIUCM_1_1 (0 << (31- 0)) /* 1:1 */ +#define RCWLR_LBIUCM_2_1 (1 << (31- 0)) /* 2:1 */ + /* DDR clocking mode */ +#define RCWLR_DDRCM_1_1 (0 << (31- 1)) /* 1:1 */ +#define RCWLR_DDRCM_2_1 (1 << (31- 1)) /* 2:1 */ + /* System PLL mult. factor */ +#define RCWLR_SPMF(n) (((n)&0xf)<<(31- 7)) + /* Core PLL mult. factor */ +#define RCWLR_COREPLL(n) (((n)&0xff)<<(31-15)) + +/* for MPC8309: */ +#define RCWLR_CEVCOD_1_8 (2<<(31-25)) /* QUICC internal PLL divider 1:8 */ +#define RCWLR_CEVCOD_1_4 (1<<(31-25)) /* QUICC internal PLL divider 1:4 */ +#define RCWLR_CEVCOD_1_2 (0<<(31-25)) /* QUICC internal PLL divider 1:2 */ + /* QUICC Engine PLL mult. factor */ +#define RCWLR_CEPDF_2 (1<<(31-26)) /* QUICC Engine divide PLL out by 2*/ + /* QUICC Engine PLL mult. factor */ +#define RCWLR_CEPMF(n) (((n)&0x1f)<<(31-31)) + + /* PCI host mode */ +#define RCWHR_PCI_AGENT (0 << (31- 0)) /* agent mode */ +#define RCWHR_PCI_HOST (1 << (31- 0)) /* host mode */ + +#define RCWHR_PCI_32 (0 << (31- 1)) /* PCI bus width 32 bit */ +#define RCWHR_PCI_64 (1 << (31- 1)) /* PCI bus width 64 bit */ + +#define RCWHR_PCI1ARB_DIS (0 << (31- 2)) /* PCI1 arbiter disabled */ +#define RCWHR_PCI1ARB_EN (1 << (31- 2)) /* PCI1 arbiter enabled */ +#define RCWHR_PCI2ARB_DIS (0 << (31- 3)) /* PCI2 arbiter disabled */ +#define RCWHR_PCI2ARB_EN (1 << (31- 3)) /* PCI2 arbiter enabled */ + +#define RCWHR_CORE_DIS (1 << (31- 4)) /* CPU core disabled */ +#define RCWHR_CORE_EN (0 << (31- 4)) /* CPU core enabled */ + +#define RCWHR_BMS_LOW (0 << (31- 5)) /* Boot from low addr 0x00000100 */ +#define RCWHR_BMS_HIGH (1 << (31- 5)) /* Boot from high addr 0xFFF00100 */ + +#define RCWHR_BOOTSEQ_NONE (0 <<(31- 7)) /* Bootsequencer off */ +#define RCWHR_BOOTSEQ_NORM (1 <<(31- 7)) /* Bootsequencer normal I2C */ +#define RCWHR_BOOTSEQ_EXTD (2 <<(31- 7)) /* Bootsequencer extended I2C */ +#define RCWHR_BOOTSEQ_RSRV (3 <<(31- 7)) /* Bootsequencer reserved */ + +#define RCWHR_SW_DIS (0 << (31- 8)) /* Watchdog disabled */ +#define RCWHR_SW_EN (1 << (31- 8)) /* Watchdog enabled */ + +#define RCWHR_ROMLOC_DDR (0 << (31-11)) /* Initial ROM location:DDR Ram */ +#define RCWHR_ROMLOC_PCI1 (1 << (31-11)) /* Initial ROM location:PCI 1 */ +#define RCWHR_ROMLOC_PCI2 (2 << (31-11)) /* Initial ROM location:PCI 2 */ +#define RCWHR_ROMLOC_RSV1 (3 << (31-11)) /* Initial ROM location:Reserved */ +#define RCWHR_ROMLOC_RSV2 (4 << (31-11)) /* Initial ROM location:Reserved */ +#define RCWHR_ROMLOC_LB08 (5 << (31-11)) /* Initial ROM location:LBus 8bit*/ +#define RCWHR_ROMLOC_LB16 (6 << (31-11)) /* Initial ROM location:LBus 16bit*/ +#define RCWHR_ROMLOC_LB32 (7 << (31-11)) /* Initial ROM location:LBus 32bit*/ + +#define RCWHR_TSEC1M_RGMII (0 << (31-17)) /* TSEC1 Mode: RGMII */ +#define RCWHR_TSEC1M_RTBI (1 << (31-17)) /* TSEC1 Mode: RTBI */ +#define RCWHR_TSEC1M_GMII (2 << (31-17)) /* TSEC1 Mode: GMII */ +#define RCWHR_TSEC1M_TBI (3 << (31-17)) /* TSEC1 Mode: TBI */ + +#define RCWHR_TSEC2M_RGMII (0 << (31-19)) /* TSEC2 Mode: RGMII */ +#define RCWHR_TSEC2M_RTBI (1 << (31-19)) /* TSEC2 Mode: RTBI */ +#define RCWHR_TSEC2M_GMII (2 << (31-19)) /* TSEC2 Mode: GMII */ +#define RCWHR_TSEC2M_TBI (3 << (31-19)) /* TSEC2 Mode: TBI */ + +#define RCWHR_ENDIAN_BIG (0 << (31-28)) /* Big Endian Mode */ +#define RCWHR_ENDIAN_LIT (1 << (31-28)) /* True Little Endian Mode */ + +#define RCWHR_LALE_NORM (0 << (31-29)) /* normal LALE timing */ +#define RCWHR_LALE_EARLY (1 << (31-29)) /* early LALE negation */ + +#define RCWHR_LDP_PAR (0 << (31-30)) /* LDP0-3 are parity pins */ +#define RCWHR_LDP_SPC (1 << (31-30)) /* LDP0-3 are special pins */ + +/* + * For MPC8309: + */ +#define RCWHR_RLEXT_LGCY (0 << (31-13)) /* Boot ROM loc. extension: Legacy */ +#define RCWHR_RLEXT_NAND (1 << (31-13)) /* Boot ROM loc. extension: NAND Fl.*/ +#define RCWHR_RLEXT_RSV2 (2 << (31-13)) /* Boot ROM loc. extension: resrvd */ +#define RCWHR_RLEXT_RSV3 (3 << (31-13)) /* Boot ROM loc. extension: resrvd */ +#endif /* _MPC83XX_MPC83XX_H */ diff --git a/bsps/powerpc/include/mpc83xx/mpc83xx_i2cdrv.h b/bsps/powerpc/include/mpc83xx/mpc83xx_i2cdrv.h new file mode 100644 index 0000000000..206cb87cb4 --- /dev/null +++ b/bsps/powerpc/include/mpc83xx/mpc83xx_i2cdrv.h @@ -0,0 +1,68 @@ +/*===============================================================*\ +| Project: RTEMS support for MPC83xx | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains the MPC83xx I2C driver declarations | +\*===============================================================*/ +#ifndef _MPC83XX_I2CDRV_H +#define _MPC83XX_I2CDRV_H + +#include +#include + +#include + +#ifdef LIBBSP_POWERPC_GEN83XX_BSP_H + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef LIBBSP_POWERPC_MPC55XXEVB_BSP_H + typedef struct { + volatile uint8_t i2cadr; + volatile uint8_t i2cfdr; + volatile uint8_t i2ccr; + volatile uint8_t i2csr; + volatile uint8_t i2cdr; + volatile uint8_t i2cdfsrr; + } m83xxI2CRegisters_t; +#endif + +typedef struct mpc83xx_i2c_softc { + m83xxI2CRegisters_t *reg_ptr; /* ptr to HW registers */ + int initialized; /* TRUE: module is initialized */ + rtems_irq_number irq_number; /* IRQ number used for this module */ + uint32_t base_frq; /* input frq for baud rate divider */ + rtems_id irq_sema_id; /* SEMA used for IRQ signalling */ + void (*probe)(struct mpc83xx_i2c_softc *self); +} mpc83xx_i2c_softc_t ; + +typedef struct { + rtems_libi2c_bus_t bus_desc; + struct mpc83xx_i2c_softc softc; +} mpc83xx_i2c_desc_t; + + +extern rtems_libi2c_bus_ops_t mpc83xx_i2c_ops; + +#ifdef __cplusplus +} +#endif + + +#endif /* _MPC83XX_I2CDRV_H */ diff --git a/bsps/powerpc/include/mpc83xx/mpc83xx_spidrv.h b/bsps/powerpc/include/mpc83xx/mpc83xx_spidrv.h new file mode 100644 index 0000000000..92fe66831a --- /dev/null +++ b/bsps/powerpc/include/mpc83xx/mpc83xx_spidrv.h @@ -0,0 +1,172 @@ +/*===============================================================*\ +| Project: RTEMS support for MPC83xx | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains the MPC83xx SPI driver declarations | +| NOTE: this driver has the same API as a I2C driver | +\*===============================================================*/ +#ifndef _MPC83XX_SPIDRV_H +#define _MPC83XX_SPIDRV_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct mpc83xx_spi_softc { + m83xxSPIRegisters_t *reg_ptr; + int initialized; + rtems_irq_number irq_number; + uint32_t base_frq; /* input frq for baud rate divider */ + rtems_id irq_sema_id; + uint32_t curr_addr; /* current spi address */ + uint32_t idle_char; + uint8_t bytes_per_char; + uint8_t bit_shift; +} mpc83xx_spi_softc_t ; + +typedef struct { + rtems_libi2c_bus_t bus_desc; + mpc83xx_spi_softc_t softc; +} mpc83xx_spi_desc_t; + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code mpc83xx_spi_init +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| initialize the driver | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh /* bus specifier structure */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int mpc83xx_spi_read_write_bytes +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| transmit/receive some bytes from SPI device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + unsigned char *rbuf, /* buffer to store bytes */ + const unsigned char *tbuf, /* buffer to send bytes */ + int len /* number of bytes to transceive */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| number of bytes received or (negative) error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int mpc83xx_spi_read_bytes +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| receive some bytes from SPI device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + unsigned char *buf, /* buffer to store bytes */ + int len /* number of bytes to receive */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| number of bytes received or (negative) error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int mpc83xx_spi_write_bytes +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| send some bytes to SPI device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + unsigned char *buf, /* buffer to send */ + int len /* number of bytes to send */ + + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| number of bytes sent or (negative) error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code mpc83xx_spi_set_tfr_mode +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| set SPI to desired baudrate/clock mode/character mode | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + const rtems_libi2c_tfr_mode_t *tfr_mode /* transfer mode info */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int mpc83xx_spi_ioctl +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| perform selected ioctl function for SPI | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + int cmd, /* ioctl command code */ + void *arg /* additional argument array */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +#ifdef __cplusplus +} +#endif + + +#endif /* _MPC83XX_I2CDRV_H */ diff --git a/bsps/powerpc/include/mpc8xx.h b/bsps/powerpc/include/mpc8xx.h new file mode 100644 index 0000000000..3222e7fd03 --- /dev/null +++ b/bsps/powerpc/include/mpc8xx.h @@ -0,0 +1,1499 @@ +/* +************************************************************************** +************************************************************************** +** ** +** MOTOROLA MPC860/MPC821 PORTABLE SYSTEMS MICROPROCESSOR ** +** ** +** HARDWARE DECLARATIONS ** +** ** +** ** +** Submitted By: ** +** ** +** W. Eric Norum ** +** Saskatchewan Accelerator Laboratory ** +** University of Saskatchewan ** +** 107 North Road ** +** Saskatoon, Saskatchewan, CANADA ** +** S7N 5C6 ** +** ** +** eric@skatter.usask.ca ** +** ** +** Modified for use with the MPC860 (original code was for MC68360) ** +** by ** +** Jay Monkman ** +** Frasca International, Inc. ** +** 906 E. Airport Rd. ** +** Urbana, IL, 61801 ** +** ** +** jmonkman@frasca.com ** +** ** +** Modified further for use with the MPC821 by: ** +** Andrew Bray ** +** ** +** With some corrections/additions by: ** +** Darlene A. Stewart and ** +** Charles-Antoine Gauthier ** +** Institute for Information Technology ** +** National Research Council of Canada ** +** Ottawa, ON K1A 0R6 ** +** ** +** Darlene.Stewart@iit.nrc.ca ** +** charles.gauthier@iit.nrc.ca ** +** ** +** Corrections/additions: ** +** Copyright (c) 1999, National Research Council of Canada ** +************************************************************************** +************************************************************************** +*/ +#ifndef _MPC8XX_H +#define _MPC8XX_H + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Macros for accessing Special Purpose Registers (SPRs) + */ +#define _mtspr(_spr,_reg) __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) ) +#define _mfspr(_reg,_spr) __asm__ volatile ( "mfspr %0, %1\n" : "=r" ((_reg)) : "i" ((_spr)) ) + +#define _isync __asm__ volatile ("isync\n"::) + +/* + * Core Registers (SPRs) + */ +#define M8xx_DEC 22 /* Decrementer Register */ +#define M8xx_DER 149 /* Debug Enable Register */ +#define M8xx_ICTRL 158 /* Instruction Support Control Register */ +#define M8xx_TBL_WR 284 /* Timebase Lower Write Register */ +#define M8xx_TBU_WR 285 /* Timebase Upper Write Register */ +#define M8xx_IMMR 638 /* Internal Memory Map Register */ + +/* + * Cache Control Registers (SPRs) + */ +#define M8xx_IC_CST 560 /* Instruction Cache Control and Status Register */ +#define M8xx_DC_CST 568 /* Data Cache Control and Status Register */ +#define M8xx_IC_ADR 561 /* Instruction Cache Address Register */ +#define M8xx_DC_ADR 569 /* Data Cache Address Register */ +#define M8xx_IC_DAT 562 /* Instruction Cache Data Port Register */ +#define M8xx_DC_DAT 570 /* Data Cache Data Port Register */ + +/* + * MMU Registers (SPRs) + */ +/* Control Registers */ +#define M8xx_MI_CTR 784 /* IMMU Control Register */ +#define M8xx_MD_CTR 792 /* DMMU Control Register */ +/* TLB Source Registers */ +#define M8xx_MI_EPN 787 /* IMMU Effective Page Number Register (EPN) */ +#define M8xx_MD_EPN 795 /* DMMU Effective Page Number Register (EPN) */ +#define M8xx_MI_TWC 789 /* IMMU Tablewalk Control Register (TWC) */ +#define M8xx_MD_TWC 797 /* DMMU Tablewalk Control Register (TWC) */ +#define M8xx_MI_RPN 790 /* IMMU Real (physical) Page Number Register (RPN) */ +#define M8xx_MD_RPN 798 /* DMMU Real (physical) Page Number Register (RPN) */ +/* Tablewalk Assist Registers */ +#define M8xx_M_TWB 796 /* MMU Tablewalk Base Register (TWB) */ +/* Protection Registers */ +#define M8xx_M_CASID 793 /* MMU Current Address Space ID Register */ +#define M8xx_MI_AP 786 /* IMMU Access Protection Register */ +#define M8xx_MD_AP 794 /* DMMU Access Protection Register */ +/* Scratch Register */ +#define M8xx_M_TW 799 /* MMU Tablewalk Special Register */ +/* Debug Registers */ +#define M8xx_MI_CAM 816 /* IMMU CAM Entry Read Register */ +#define M8xx_MI_RAM0 817 /* IMMU RAM Entry Read Register 0 */ +#define M8xx_MI_RAM1 818 /* IMMU RAM Entry Read Register 1 */ +#define M8xx_MD_CAM 824 /* DMMU CAM Entry Read Register */ +#define M8xx_MD_RAM0 825 /* DMMU RAM Entry Read Register 0 */ +#define M8xx_MD_RAM1 826 /* DMMU RAM Entry Read Register 1 */ + +#define M8xx_MI_CTR_GPM (1<<31) +#define M8xx_MI_CTR_PPM (1<<30) +#define M8xx_MI_CTR_CIDEF (1<<29) +#define M8xx_MI_CTR_RSV4I (1<<27) +#define M8xx_MI_CTR_PPCS (1<<25) +#define M8xx_MI_CTR_ITLB_INDX(x) ((x)<<8) /* ITLB index */ + +#define M8xx_MD_CTR_GPM (1<<31) +#define M8xx_MD_CTR_PPM (1<<30) +#define M8xx_MD_CTR_CIDEF (1<<29) +#define M8xx_MD_CTR_WTDEF (1<<28) +#define M8xx_MD_CTR_RSV4D (1<<27) +#define M8xx_MD_CTR_TWAM (1<<26) +#define M8xx_MD_CTR_PPCS (1<<25) +#define M8xx_MD_CTR_DTLB_INDX(x) ((x)<<8) /* DTLB index */ + +#define M8xx_MI_EPN_VALID (1<<9) + +#define M8xx_MD_EPN_VALID (1<<9) + +#define M8xx_MI_TWC_G (1<<4) +#define M8xx_MI_TWC_PSS (0<<2) +#define M8xx_MI_TWC_PS512 (1<<2) +#define M8xx_MI_TWC_PS8 (3<<2) +#define M8xx_MI_TWC_VALID (1) + +#define M8xx_MD_TWC_G (1<<4) +#define M8xx_MD_TWC_PSS (0<<2) +#define M8xx_MD_TWC_PS512 (1<<2) +#define M8xx_MD_TWC_PS8 (3<<2) +#define M8xx_MD_TWC_WT (1<<1) +#define M8xx_MD_TWC_VALID (1) + +#define M8xx_MI_RPN_F (0xf<<4) +#define M8xx_MI_RPN_16K (1<<3) +#define M8xx_MI_RPN_SHARED (1<<2) +#define M8xx_MI_RPN_CI (1<<1) +#define M8xx_MI_RPN_VALID (1) + +#define M8xx_MD_RPN_CHANGE (1<<8) +#define M8xx_MD_RPN_F (0xf<<4) +#define M8xx_MD_RPN_16K (1<<3) +#define M8xx_MD_RPN_SHARED (1<<2) +#define M8xx_MD_RPN_CI (1<<1) +#define M8xx_MD_RPN_VALID (1) + +#define M8xx_MI_AP_Kp (1) + +#define M8xx_MD_AP_Kp (1) + +#define M8xx_CACHE_CMD_SFWT (0x1<<24) +#define M8xx_CACHE_CMD_ENABLE (0x2<<24) +#define M8xx_CACHE_CMD_CFWT (0x3<<24) +#define M8xx_CACHE_CMD_DISABLE (0x4<<24) +#define M8xx_CACHE_CMD_STLES (0x5<<24) +#define M8xx_CACHE_CMD_LLCB (0x6<<24) +#define M8xx_CACHE_CMD_CLES (0x7<<24) +#define M8xx_CACHE_CMD_UNLOCK (0x8<<24) +#define M8xx_CACHE_CMD_UNLOCKALL (0xa<<24) +#define M8xx_CACHE_CMD_INVALIDATE (0xc<<24) +#define M8xx_CACHE_CMD_FLUSH (0xe<<24) + +/* +************************************************************************* +* REGISTER SUBBLOCKS * +************************************************************************* +*/ + +/* + * Memory controller registers + */ +typedef struct m8xxMEMCRegisters_ { + uint32_t _br; + uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */ +} m8xxMEMCRegisters_t; + +/* + * Serial Communications Controller registers + */ +typedef struct m8xxSCCRegisters_ { + uint32_t gsmr_l; + uint32_t gsmr_h; + uint16_t psmr; + uint16_t _pad0; + uint16_t todr; + uint16_t dsr; + uint16_t scce; + uint16_t _pad1; + uint16_t sccm; + uint8_t _pad2; + uint8_t sccs; + uint32_t _pad3[2]; +} m8xxSCCRegisters_t; + +/* + * Serial Management Controller registers + */ +typedef struct m8xxSMCRegisters_ { + uint16_t _pad0; + uint16_t smcmr; + uint16_t _pad1; + uint8_t smce; + uint8_t _pad2; + uint16_t _pad3; + uint8_t smcm; + uint8_t _pad4; + uint32_t _pad5; +} m8xxSMCRegisters_t; + +/* + * Fast Ethernet Controller registers (Only on MPC8xxT) + */ +typedef struct m8xxFECRegisters_ { + uint32_t addr_low; + uint32_t addr_high; + uint32_t hash_table_high; + uint32_t hash_table_low; + uint32_t r_des_start; + uint32_t x_des_start; + uint32_t r_buf_size; + uint32_t _pad0[9]; + uint32_t ecntrl; + uint32_t ievent; + uint32_t imask; + uint32_t ivec; + uint32_t r_des_active; + uint32_t x_des_active; + uint32_t _pad1[10]; + uint32_t mii_data; + uint32_t mii_speed; + uint32_t _pad2[17]; + uint32_t r_bound; + uint32_t r_fstart; + uint32_t _pad3[6]; + uint32_t x_fstart; + uint32_t _pad4[17]; + uint32_t fun_code; + uint32_t _pad5[3]; + uint32_t r_cntrl; + uint32_t r_hash; + uint32_t _pad6[14]; + uint32_t x_cntrl; + uint32_t _pad7[30]; + +} m8xxFECRegisters_t; + +#define M8xx_FEC_IEVENT_HBERR (1 << 31) +#define M8xx_FEC_IEVENT_BABR (1 << 30) +#define M8xx_FEC_IEVENT_BABT (1 << 29) +#define M8xx_FEC_IEVENT_GRA (1 << 28) +#define M8xx_FEC_IEVENT_TFINT (1 << 27) +#define M8xx_FEC_IEVENT_TXB (1 << 26) +#define M8xx_FEC_IEVENT_RFINT (1 << 25) +#define M8xx_FEC_IEVENT_RXB (1 << 24) +#define M8xx_FEC_IEVENT_MII (1 << 23) +#define M8xx_FEC_IEVENT_EBERR (1 << 22) +#define M8xx_FEC_IMASK_HBEEN (1 << 31) +#define M8xx_FEC_IMASK_BREEN (1 << 30) +#define M8xx_FEC_IMASK_BTEN (1 << 29) +#define M8xx_FEC_IMASK_GRAEN (1 << 28) +#define M8xx_FEC_IMASK_TFIEN (1 << 27) +#define M8xx_FEC_IMASK_TBIEN (1 << 26) +#define M8xx_FEC_IMASK_RFIEN (1 << 25) +#define M8xx_FEC_IMASK_RBIEN (1 << 24) +#define M8xx_FEC_IMASK_MIIEN (1 << 23) +#define M8xx_FEC_IMASK_EBERREN (1 << 22) + + /* + * access macros to write to mii_data register + */ +#define M8xx_FEC_MII_DATA_ST ( 1 << (31- 1)) +#define M8xx_FEC_MII_DATA_OP_RD ( 2 << (31- 3)) +#define M8xx_FEC_MII_DATA_OP_WR ( 1 << (31- 3)) +#define M8xx_FEC_MII_DATA_PHYAD(n) (((n) & 0x3f) << (31- 8)) +#define M8xx_FEC_MII_DATA_PHYRA(n) (((n) & 0x3f) << (31-13)) +#define M8xx_FEC_MII_DATA_TA ( 2 << (31-15)) +#define M8xx_FEC_MII_DATA_WDATA(n) ((n) & 0xffff ) +#define M8xx_FEC_MII_DATA_RDATA(reg) ((reg) & 0xffff ) + /* + * bits for FEC X_CNTRL register + */ +#define M8xx_FEC_X_CNTRL_FDEN ( 1 << (31-29)) +#define M8xx_FEC_X_CNTRL_HBC ( 1 << (31-30)) +#define M8xx_FEC_X_CNTRL_GTS ( 1 << (31-31)) +/* +************************************************************************* +* Miscellaneous Parameters * +************************************************************************* +*/ +typedef struct m8xxMiscParms_ { + uint16_t rev_num; + uint16_t _res1; + uint32_t _res2; + uint32_t _res3; +} m8xxMiscParms_t; + +/* +************************************************************************* +* RISC Timers * +************************************************************************* +*/ +typedef struct m8xxTimerParms_ { + uint16_t tm_base; + uint16_t _tm_ptr; + uint16_t _r_tmr; + uint16_t _r_tmv; + uint32_t tm_cmd; + uint32_t tm_cnt; +} m8xxTimerParms_t; + +/* + * RISC Controller Configuration Register (RCCR) + * All other bits in this register are reserved. + */ +#define M8xx_RCCR_TIME (1<<15) /* Enable timer */ +#define M8xx_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ +#define M8xx_RCCR_DR1M (1<<7) /* IDMA Rqst 1 Mode */ +#define M8xx_RCCR_DR0M (1<<6) /* IDMA Rqst 0 Mode */ +#define M8xx_RCCR_DRQP(x) ((x)<<4) /* IDMA Rqst Priority */ +#define M8xx_RCCR_EIE (1<<3) /* External Interrupt Enable */ +#define M8xx_RCCR_SCD (1<<2) /* Scheduler Configuration */ +#define M8xx_RCCR_ERAM(x) (x) /* Enable RAM Microcode */ + +/* + * Command register + * Set up this register before issuing a M8xx_CR_OP_SET_TIMER command. + */ +#define M8xx_TM_CMD_V (1<<31) /* Set to enable timer */ +#define M8xx_TM_CMD_R (1<<30) /* Set for automatic restart */ +#define M8xx_TM_CMD_PWM (1<<29) /* Set for PWM operation */ +#define M8xx_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ +#define M8xx_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ + +/* +************************************************************************* +* DMA Controllers * +************************************************************************* +*/ +typedef struct m8xxIDMAparms_ { + uint16_t ibase; + uint16_t dcmr; + uint32_t _sapr; + uint32_t _dapr; + uint16_t ibptr; + uint16_t _write_sp; + uint32_t _s_byte_c; + uint32_t _d_byte_c; + uint32_t _s_state; + uint32_t _itemp[4]; + uint32_t _sr_mem; + uint16_t _read_sp; + uint16_t _res0; + uint16_t _res1; + uint16_t _res2; + uint32_t _d_state; +} m8xxIDMAparms_t; + + +/* +************************************************************************* +* DSP * +************************************************************************* +*/ +typedef struct m8xxDSPparms_ { + uint32_t fdbase; + uint32_t _fd_ptr; + uint32_t _dstate; + uint32_t _pad0; + uint16_t _dstatus; + uint16_t _i; + uint16_t _tap; + uint16_t _cbase; + uint16_t _pad1; + uint16_t _xptr; + uint16_t _pad2; + uint16_t _yptr; + uint16_t _m; + uint16_t _pad3; + uint16_t _n; + uint16_t _pad4; + uint16_t _k; + uint16_t _pad5; +} m8xxDSPparms_t; + +/* +************************************************************************* +* Serial Communication Controllers * +************************************************************************* +*/ +typedef struct m8xxSCCparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; + uint32_t _rcrc; + uint32_t _tcrc; + union { + struct { + uint32_t _res0; + uint32_t _res1; + uint16_t max_idl; + uint16_t _idlc; + uint16_t brkcr; + uint16_t parec; + uint16_t frmec; + uint16_t nosec; + uint16_t brkec; + uint16_t brkln; + uint16_t uaddr[2]; + uint16_t _rtemp; + uint16_t toseq; + uint16_t character[8]; + uint16_t rccm; + uint16_t rccr; + uint16_t rlbc; + } uart; + } un; +} m8xxSCCparms_t; + +typedef struct m8xxSCCENparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; + uint32_t _rcrc; + uint32_t _tcrc; + union { + struct { + uint32_t _res0; + uint32_t _res1; + uint16_t max_idl; + uint16_t _idlc; + uint16_t brkcr; + uint16_t parec; + uint16_t frmec; + uint16_t nosec; + uint16_t brkec; + uint16_t brkln; + uint16_t uaddr[2]; + uint16_t _rtemp; + uint16_t toseq; + uint16_t character[8]; + uint16_t rccm; + uint16_t rccr; + uint16_t rlbc; + } uart; + struct { + uint32_t c_pres; + uint32_t c_mask; + uint32_t crcec; + uint32_t alec; + uint32_t disfc; + uint16_t pads; + uint16_t ret_lim; + uint16_t _ret_cnt; + uint16_t mflr; + uint16_t minflr; + uint16_t maxd1; + uint16_t maxd2; + uint16_t _maxd; + uint16_t dma_cnt; + uint16_t _max_b; + uint16_t gaddr1; + uint16_t gaddr2; + uint16_t gaddr3; + uint16_t gaddr4; + uint32_t _tbuf0data0; + uint32_t _tbuf0data1; + uint32_t _tbuf0rba0; + uint32_t _tbuf0crc; + uint16_t _tbuf0bcnt; + uint16_t paddr_h; + uint16_t paddr_m; + uint16_t paddr_l; + uint16_t p_per; + uint16_t _rfbd_ptr; + uint16_t _tfbd_ptr; + uint16_t _tlbd_ptr; + uint32_t _tbuf1data0; + uint32_t _tbuf1data1; + uint32_t _tbuf1rba0; + uint32_t _tbuf1crc; + uint16_t _tbuf1bcnt; + uint16_t _tx_len; + uint16_t iaddr1; + uint16_t iaddr2; + uint16_t iaddr3; + uint16_t iaddr4; + uint16_t _boff_cnt; + uint16_t taddr_m; + uint16_t taddr_l; + uint16_t taddr_h; + } ethernet; + } un; +} m8xxSCCENparms_t; + +/* + * Receive and transmit function code register bits + * These apply to the function code registers of all devices, not just SCC. + */ +#define M8xx_RFCR_BO(x) ((x)<<3) +#define M8xx_RFCR_MOT (2<<3) +#define M8xx_RFCR_DMA_SPACE(x) (x) +#define M8xx_TFCR_BO(x) ((x)<<3) +#define M8xx_TFCR_MOT (2<<3) +#define M8xx_TFCR_DMA_SPACE(x) (x) + +/* + * Event and mask registers (SCCE, SCCM) + */ +#define M8xx_SCCE_BRKE (1<<6) +#define M8xx_SCCE_BRK (1<<4) +#define M8xx_SCCE_BSY (1<<2) +#define M8xx_SCCE_TX (1<<1) +#define M8xx_SCCE_RX (1<<0) + +/* +************************************************************************* +* Serial Management Controllers * +************************************************************************* +*/ +typedef struct m8xxSMCparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; + union { + struct { + uint16_t max_idl; + uint16_t _idlc; + uint16_t brkln; + uint16_t brkec; + uint16_t brkcr; + uint16_t _r_mask; + } uart; + struct { + uint16_t _pad0[5]; + } transparent; + } un; +} m8xxSMCparms_t; + +/* + * Mode register + */ +#define M8xx_SMCMR_CLEN(x) ((x)<<11) /* Character length */ +#define M8xx_SMCMR_2STOP (1<<10) /* 2 stop bits */ +#define M8xx_SMCMR_PARITY (1<<9) /* Enable parity */ +#define M8xx_SMCMR_EVEN (1<<8) /* Even parity */ +#define M8xx_SMCMR_SM_GCI (0<<4) /* GCI Mode */ +#define M8xx_SMCMR_SM_UART (2<<4) /* UART Mode */ +#define M8xx_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ +#define M8xx_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ +#define M8xx_SMCMR_DM_ECHO (2<<2) /* Echo mode */ +#define M8xx_SMCMR_TEN (1<<1) /* Enable transmitter */ +#define M8xx_SMCMR_REN (1<<0) /* Enable receiver */ + +/* + * Event and mask registers (SMCE, SMCM) + */ +#define M8xx_SMCE_BRKE (1<<6) +#define M8xx_SMCE_BRK (1<<4) +#define M8xx_SMCE_BSY (1<<2) +#define M8xx_SMCE_TX (1<<1) +#define M8xx_SMCE_RX (1<<0) + +/* +************************************************************************* +* Serial Peripheral Interface * +************************************************************************* +*/ +typedef struct m8xxSPIparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; +} m8xxSPIparms_t; + +/* + * Mode register (SPMODE) + */ +#define M8xx_SPMODE_LOOP (1<<14) /* Local loopback mode */ +#define M8xx_SPMODE_CI (1<<13) /* Clock invert */ +#define M8xx_SPMODE_CP (1<<12) /* Clock phase */ +#define M8xx_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ +#define M8xx_SPMODE_REV (1<<10) /* Reverse data */ +#define M8xx_SPMODE_MASTER (1<<9) /* SPI is master */ +#define M8xx_SPMODE_EN (1<<8) /* Enable SPI */ +#define M8xx_SPMODE_CLEN(x) ((x)<<4) /* Character length */ +#define M8xx_SPMODE_PM(x) (x) /* Prescaler modulus */ + +/* + * Mode register (SPCOM) + */ +#define M8xx_SPCOM_STR (1<<7) /* Start transmit */ + +/* + * Event and mask registers (SPIE, SPIM) + */ +#define M8xx_SPIE_MME (1<<5) /* Multi-master error */ +#define M8xx_SPIE_TXE (1<<4) /* Tx error */ +#define M8xx_SPIE_BSY (1<<2) /* Busy condition*/ +#define M8xx_SPIE_TXB (1<<1) /* Tx buffer */ +#define M8xx_SPIE_RXB (1<<0) /* Rx buffer */ + +/* +************************************************************************* +* SDMA (SCC, SMC, SPI) Buffer Descriptors * +************************************************************************* +*/ +typedef struct m8xxBufferDescriptor_ { + volatile uint16_t status; + uint16_t length; + volatile void *buffer; +} m8xxBufferDescriptor_t; + +/* + * Bits in receive buffer descriptor status word + */ +#define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */ +#define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */ +#define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ +#define M8xx_BD_ADDRESS (1<<10) /* SCC UART */ +#define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ +#define M8xx_BD_MISS (1<<8) /* Ethernet */ +#define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */ +#define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ +#define M8xx_BD_LONG (1<<5) /* Ethernet */ +#define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */ +#define M8xx_BD_NONALIGNED (1<<4) /* Ethernet */ +#define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ +#define M8xx_BD_SHORT (1<<3) /* Ethernet */ +#define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ +#define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet */ +#define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_COLLISION (1<<0) /* Ethernet */ +#define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ +#define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */ + +/* + * Bits in transmit buffer descriptor status word + * Many bits have the same meaning as those in receiver buffer descriptors. + */ +#define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_PAD (1<<14) /* Ethernet */ +#define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */ +#define M8xx_BD_TX_CRC (1<<10) /* Ethernet */ +#define M8xx_BD_DEFER (1<<9) /* Ethernet */ +#define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */ +#define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ +#define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */ +#define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */ +#define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */ +#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ +#define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ +#define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */ +#define M8xx_BD_CTS_LOST (1<<0) /* SCC UART */ + +/* +************************************************************************* +* IDMA Buffer Descriptors * +************************************************************************* +*/ +typedef struct m8xxIDMABufferDescriptor_ { + uint16_t status; + uint8_t dfcr; + uint8_t sfcr; + uint32_t length; + void *source; + void *destination; +} m8xxIDMABufferDescriptor_t; + +/* +************************************************************************* +* RISC Communication Processor Module Command Register (CR) * +************************************************************************* +*/ +#define M8xx_CR_RST (1<<15) /* Reset communication processor */ +#define M8xx_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ +#define M8xx_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ +#define M8xx_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ +#define M8xx_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ +#define M8xx_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ +#define M8xx_CR_OP_GR_STOP_TX (5<<8) /* SCC */ +#define M8xx_CR_OP_INIT_IDMA (5<<8) /* IDMA */ +#define M8xx_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ +#define M8xx_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ +#define M8xx_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ +#define M8xx_CR_OP_SET_TIMER (8<<8) /* Timer */ +#define M8xx_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ +#define M8xx_CR_OP_RESERT_BCS (10<<8) /* SCC */ +#define M8xx_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ +#define M8xx_CR_OP_STOP_IDMA (11<<8) /* IDMA */ +#define M8xx_CR_OP_START_DSP (12<<8) /* DSP */ +#define M8xx_CR_OP_INIT_DSP (13<<8) /* DSP */ + +#define M8xx_CR_CHAN_SCC1 (0<<4) /* Channel selection */ +#define M8xx_CR_CHAN_I2C (1<<4) +#define M8xx_CR_CHAN_IDMA1 (1<<4) +#define M8xx_CR_CHAN_SCC2 (4<<4) +#define M8xx_CR_CHAN_SPI (5<<4) +#define M8xx_CR_CHAN_IDMA2 (5<<4) +#define M8xx_CR_CHAN_TIMER (5<<4) +#define M8xx_CR_CHAN_SCC3 (8<<4) +#define M8xx_CR_CHAN_SMC1 (9<<4) +#define M8xx_CR_CHAN_DSP1 (9<<4) +#define M8xx_CR_CHAN_SCC4 (12<<4) +#define M8xx_CR_CHAN_SMC2 (13<<4) +#define M8xx_CR_CHAN_DSP2 (13<<4) +#define M8xx_CR_FLG (1<<0) /* Command flag */ + +/* +************************************************************************* +* System Protection Control Register (SYPCR) * +************************************************************************* +*/ +#define M8xx_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ +#define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ +#define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */ +#define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */ +#define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */ +#define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ +#define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */ + +/* +************************************************************************* +* PCMCIA Control Registers +************************************************************************* +*/ +#define M8xx_PCMCIA_POR_BSIZE_1B (0x00 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_2B (0x01 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_4B (0x03 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_8B (0x02 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_16B (0x06 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_32B (0x07 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_64B (0x05 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_128B (0x04 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_256B (0x0C << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_512B (0x0D << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_1KB (0x0F << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_2KB (0x0E << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_4KB (0x0A << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_8KB (0x0B << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_16KB (0x09 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_32KB (0x08 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_64KB (0x18 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_128KB (0x19 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_256KB (0x1B << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_512KB (0x1A << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_1MB (0x1E << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_2MB (0x1F << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_4MB (0x1D << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_8MB (0x1C << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_16MB (0x14 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_32MB (0x15 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_64MB (0x17 << (31-4)) + +#define M8xx_PCMCIA_POR_PSHT(x) (((x) & 0x0f) << (31-15)) +#define M8xx_PCMCIA_POR_PSST(x) (((x) & 0x0f) << (31-19)) +#define M8xx_PCMCIA_POR_PSL(x) (((x) & 0x1f) << (31-24)) +#define M8xx_PCMCIA_POR_PPS_8 ((0) << (31-19)) +#define M8xx_PCMCIA_POR_PPS_16 ((1) << (31-19)) + +#define M8xx_PCMCIA_POR_PRS_MEM ((0) << (31-28)) +#define M8xx_PCMCIA_POR_PRS_ATT ((2) << (31-28)) +#define M8xx_PCMCIA_POR_PRS_IO ((3) << (31-28)) +#define M8xx_PCMCIA_POR_PRS_DMA ((4) << (31-28)) +#define M8xx_PCMCIA_POR_PRS_DML ((5) << (31-28)) + +#define M8xx_PCMCIA_POR_PSLOT_A ((0) << (31-29)) +#define M8xx_PCMCIA_POR_PSLOT_B ((1) << (31-29)) + +#define M8xx_PCMCIA_POR_WP ((1) << (31-30)) +#define M8xx_PCMCIA_POR_VALID ((1) << (31-31)) + +#define M8xx_PCMCIA_PGCR_CIRQLVL(x) (((x) & 0xff) << (31- 7)) +#define M8xx_PCMCIA_PGCR_CSCHLVL(x) (((x) & 0xff) << (31-15)) +#define M8xx_PCMCIA_PGCR_CDRQ_OFF ((0) << (31-17)) +#define M8xx_PCMCIA_PGCR_CDRQ_IOIS16 ((2) << (31-17)) +#define M8xx_PCMCIA_PGCR_CDRQ_SPKR ((3) << (31-17)) +#define M8xx_PCMCIA_PGCR_COE ((1) << (31-24)) +#define M8xx_PCMCIA_PGCR_CRESET ((1) << (31-25)) + +#define M8xx_PCMCIA_PIPR_CAVS1 ((1) << (31- 0)) +#define M8xx_PCMCIA_PIPR_CAVS2 ((1) << (31- 1)) +#define M8xx_PCMCIA_PIPR_CAWP ((1) << (31- 2)) +#define M8xx_PCMCIA_PIPR_CACD2 ((1) << (31- 3)) +#define M8xx_PCMCIA_PIPR_CACD1 ((1) << (31- 4)) +#define M8xx_PCMCIA_PIPR_CABVD2 ((1) << (31- 5)) +#define M8xx_PCMCIA_PIPR_CABVD1 ((1) << (31- 6)) +#define M8xx_PCMCIA_PIPR_CARDY ((1) << (31- 7)) +#define M8xx_PCMCIA_PIPR_CBVS1 ((1) << (31-16)) +#define M8xx_PCMCIA_PIPR_CBVS2 ((1) << (31-17)) +#define M8xx_PCMCIA_PIPR_CBWP ((1) << (31-18)) +#define M8xx_PCMCIA_PIPR_CBCD2 ((1) << (31-19)) +#define M8xx_PCMCIA_PIPR_CBCD1 ((1) << (31-20)) +#define M8xx_PCMCIA_PIPR_CBBVD2 ((1) << (31-21)) +#define M8xx_PCMCIA_PIPR_CBBVD1 ((1) << (31-22)) +#define M8xx_PCMCIA_PIPR_CBRDY ((1) << (31-23)) + + +#define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ +#define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */ +#define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */ +#define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */ +#define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ +#define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */ + +/* +************************************************************************* +* Memory Control Registers * +************************************************************************* +*/ +#define M8xx_UPM_AMX_8col (0<<20) /* 8 column DRAM */ +#define M8xx_UPM_AMX_9col (1<<20) /* 9 column DRAM */ +#define M8xx_UPM_AMX_10col (2<<20) /* 10 column DRAM */ +#define M8xx_UPM_AMX_11col (3<<20) /* 11 column DRAM */ +#define M8xx_UPM_AMX_12col (4<<20) /* 12 column DRAM */ +#define M8xx_UPM_AMX_13col (5<<20) /* 13 column DRAM */ +#define M8xx_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */ +#define M8xx_MSR_WPER (1<<7) /* Write protection error */ +#define M8xx_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */ +#define M8xx_BR_BA(x) ((x)&0xffff8000) /* Base address */ +#define M8xx_BR_AT(x) ((x)<<12) /* Address type */ +#define M8xx_BR_PS8 (1<<10) /* 8 bit port */ +#define M8xx_BR_PS16 (2<<10) /* 16 bit port */ +#define M8xx_BR_PS32 (0<<10) /* 32 bit port */ +#define M8xx_BR_PARE (1<<9) /* Parity checking enable */ +#define M8xx_BR_WP (1<<8) /* Write protect */ +#define M8xx_BR_MS_GPCM (0<<6) /* GPCM */ +#define M8xx_BR_MS_UPMA (2<<6) /* UPM A */ +#define M8xx_BR_MS_UPMB (3<<6) /* UPM B */ +#define M8xx_MEMC_BR_V (1<<0) /* Base/Option register are valid */ + +#define M8xx_MEMC_OR_32K 0xffff8000 /* Address range */ +#define M8xx_MEMC_OR_64K 0xffff0000 +#define M8xx_MEMC_OR_128K 0xfffe0000 +#define M8xx_MEMC_OR_256K 0xfffc0000 +#define M8xx_MEMC_OR_512K 0xfff80000 +#define M8xx_MEMC_OR_1M 0xfff00000 +#define M8xx_MEMC_OR_2M 0xffe00000 +#define M8xx_MEMC_OR_4M 0xffc00000 +#define M8xx_MEMC_OR_8M 0xff800000 +#define M8xx_MEMC_OR_16M 0xff000000 +#define M8xx_MEMC_OR_32M 0xfe000000 +#define M8xx_MEMC_OR_64M 0xfc000000 +#define M8xx_MEMC_OR_128 0xf8000000 +#define M8xx_MEMC_OR_256M 0xf0000000 +#define M8xx_MEMC_OR_512M 0xe0000000 +#define M8xx_MEMC_OR_1G 0xc0000000 +#define M8xx_MEMC_OR_2G 0x80000000 +#define M8xx_MEMC_OR_4G 0x00000000 +#define M8xx_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ +#define M8xx_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ +#define M8xx_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */ +#define M8xx_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ +#define M8xx_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ +#define M8xx_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ +#define M8xx_MEMC_OR_BI (1<<8) /* Burst inhibit */ +#define M8xx_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ +#define M8xx_MEMC_OR_SETA (1<<3) /* *TA generated externally */ +#define M8xx_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */ +#define M8xx_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */ + +/* +************************************************************************* +* UPM Registers (MxMR) * +************************************************************************* +*/ +#define M8xx_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */ +#define M8xx_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */ +#define M8xx_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */ +#define M8xx_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */ +#define M8xx_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */ +#define M8xx_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */ +#define M8xx_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */ +#define M8xx_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */ +/* +************************************************************************* +* Memory Command Register (MCR) * +************************************************************************* +*/ +#define M8xx_MEMC_MCR_WRITE (0<<30) /* WRITE command */ +#define M8xx_MEMC_MCR_READ (1<<30) /* READ command */ +#define M8xx_MEMC_MCR_RUN (2<<30) /* RUN command */ +#define M8xx_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */ +#define M8xx_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */ +#define M8xx_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */ +#define M8xx_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */ +#define M8xx_MEMC_MCR_MAD(x) (x) /* Machine address */ + + + +/* +************************************************************************* +* SI Mode Register (SIMODE) * +************************************************************************* +*/ +#define M8xx_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ +#define M8xx_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ +#define M8xx_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ +#define M8xx_SI_SMC2_BRG2 (1<<28) +#define M8xx_SI_SMC2_BRG3 (2<<28) +#define M8xx_SI_SMC2_BRG4 (3<<28) +#define M8xx_SI_SMC2_CLK5 (0<<28) +#define M8xx_SI_SMC2_CLK6 (1<<28) +#define M8xx_SI_SMC2_CLK7 (2<<28) +#define M8xx_SI_SMC2_CLK8 (3<<28) +#define M8xx_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ +#define M8xx_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ +#define M8xx_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ +#define M8xx_SI_SMC1_BRG2 (1<<12) +#define M8xx_SI_SMC1_BRG3 (2<<12) +#define M8xx_SI_SMC1_BRG4 (3<<12) +#define M8xx_SI_SMC1_CLK1 (0<<12) +#define M8xx_SI_SMC1_CLK2 (1<<12) +#define M8xx_SI_SMC1_CLK3 (2<<12) +#define M8xx_SI_SMC1_CLK4 (3<<12) + +/* +************************************************************************* +* SDMA Configuration Register (SDCR) * +************************************************************************* +*/ +#define M8xx_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */ +#define M8xx_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */ + +/* +************************************************************************* +* SDMA Status Register (SDSR) * +************************************************************************* +*/ +#define M8xx_SDSR_SBER (1<<7) /* SDMA Channel bus error */ +#define M8xx_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */ +#define M8xx_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */ + +/* +************************************************************************* +* Baud (sic) Rate Generators * +************************************************************************* +*/ +#define M8xx_BRG_RST (1<<17) /* Reset generator */ +#define M8xx_BRG_EN (1<<16) /* Enable generator */ +#define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ +#define M8xx_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ +#define M8xx_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ +#define M8xx_BRG_ATB (1<<13) /* Autobaud */ +#define M8xx_BRG_115200 (21<<1) /* Assume 40 MHz clock */ +#define M8xx_BRG_57600 (32<<1) +#define M8xx_BRG_38400 (64<<1) +#define M8xx_BRG_19200 (129<<1) +#define M8xx_BRG_9600 (259<<1) +#define M8xx_BRG_4800 (520<<1) +#define M8xx_BRG_2400 (1040<<1) +#define M8xx_BRG_1200 (2082<<1) +#define M8xx_BRG_600 ((259<<1) | 1) +#define M8xx_BRG_300 ((520<<1) | 1) +#define M8xx_BRG_150 ((1040<<1) | 1) +#define M8xx_BRG_75 ((2080<<1) | 1) + +#define M8xx_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */ +#define M8xx_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */ +#define M8xx_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */ +#define M8xx_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */ +#define M8xx_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */ +#define M8xx_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */ +#define M8xx_TGCR_STP1 (1<<1) /* Stop timer */ +#define M8xx_TGCR_STP2 (1<<5) /* Stop timer */ +#define M8xx_TGCR_STP3 (1<<9) /* Stop timer */ +#define M8xx_TGCR_STP4 (1<<13) /* Stop timer */ +#define M8xx_TGCR_RST1 (1<<0) /* Enable timer */ +#define M8xx_TGCR_RST2 (1<<4) /* Enable timer */ +#define M8xx_TGCR_RST3 (1<<8) /* Enable timer */ +#define M8xx_TGCR_RST4 (1<<12) /* Enable timer */ +#define M8xx_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */ +#define M8xx_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */ + +#define M8xx_TMR_PS(x) ((x)<<8) /* Timer prescaler */ +#define M8xx_TMR_CE_RISE (1<<6) /* Capture on rising edge */ +#define M8xx_TMR_CE_FALL (2<<6) /* Capture on falling edge */ +#define M8xx_TMR_CE_ANY (3<<6) /* Capture on any edge */ +#define M8xx_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */ +#define M8xx_TMR_ORI (1<<4) /* Interrupt on reaching reference */ +#define M8xx_TMR_RESTART (1<<3) /* Restart timer after reference */ +#define M8xx_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */ +#define M8xx_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */ +#define M8xx_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */ +#define M8xx_TMR_TGATE (1<<0) /* TGATE controls timer */ + +#define M8xx_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ +#define M8xx_PISCR_PS (1<<7) /* PIT Interrupt state */ +#define M8xx_PISCR_PIE (1<<2) /* PIT interrupt enable */ +#define M8xx_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ +#define M8xx_PISCR_PTE (1<<0) /* PIT enable */ + +#define M8xx_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ +#define M8xx_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ +#define M8xx_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ +#define M8xx_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ +#define M8xx_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ +#define M8xx_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ +#define M8xx_TBSCR_TBE (1<<0) /* enable TB and decrementer */ + +#define M8xx_SIMASK_IRM0 (1<<31) +#define M8xx_SIMASK_LVM0 (1<<30) +#define M8xx_SIMASK_IRM1 (1<<29) +#define M8xx_SIMASK_LVM1 (1<<28) +#define M8xx_SIMASK_IRM2 (1<<27) +#define M8xx_SIMASK_LVM2 (1<<26) +#define M8xx_SIMASK_IRM3 (1<<25) +#define M8xx_SIMASK_LVM3 (1<<24) +#define M8xx_SIMASK_IRM4 (1<<23) +#define M8xx_SIMASK_LVM4 (1<<22) +#define M8xx_SIMASK_IRM5 (1<<21) +#define M8xx_SIMASK_LVM5 (1<<20) +#define M8xx_SIMASK_IRM6 (1<<19) +#define M8xx_SIMASK_LVM6 (1<<18) +#define M8xx_SIMASK_IRM7 (1<<17) +#define M8xx_SIMASK_LVM7 (1<<16) + +#define M8xx_SIUMCR_EARB (1<<31) +#define M8xx_SIUMCR_EARP0 (0<<28) +#define M8xx_SIUMCR_EARP1 (1<<28) +#define M8xx_SIUMCR_EARP2 (2<<28) +#define M8xx_SIUMCR_EARP3 (3<<28) +#define M8xx_SIUMCR_EARP4 (4<<28) +#define M8xx_SIUMCR_EARP5 (5<<28) +#define M8xx_SIUMCR_EARP6 (6<<28) +#define M8xx_SIUMCR_EARP7 (7<<28) +#define M8xx_SIUMCR_DSHW (1<<23) +#define M8xx_SIUMCR_DBGC0 (0<<21) +#define M8xx_SIUMCR_DBGC1 (1<<21) +#define M8xx_SIUMCR_DBGC2 (2<<21) +#define M8xx_SIUMCR_DBGC3 (3<<21) +#define M8xx_SIUMCR_DBPC0 (0<<19) +#define M8xx_SIUMCR_DBPC1 (1<<19) +#define M8xx_SIUMCR_DBPC2 (2<<19) +#define M8xx_SIUMCR_DBPC3 (3<<19) +#define M8xx_SIUMCR_FRC (1<<17) +#define M8xx_SIUMCR_DLK (1<<16) +#define M8xx_SIUMCR_PNCS (1<<15) +#define M8xx_SIUMCR_OPAR (1<<14) +#define M8xx_SIUMCR_DPC (1<<13) +#define M8xx_SIUMCR_MPRE (1<<12) +#define M8xx_SIUMCR_MLRC0 (0<<10) +#define M8xx_SIUMCR_MLRC1 (1<<10) +#define M8xx_SIUMCR_MLRC2 (2<<10) +#define M8xx_SIUMCR_MLRC3 (3<<10) +#define M8xx_SIUMCR_AEME (1<<9) +#define M8xx_SIUMCR_SEME (1<<8) +#define M8xx_SIUMCR_BSC (1<<7) +#define M8xx_SIUMCR_GB5E (1<<6) +#define M8xx_SIUMCR_B2DD (1<<5) +#define M8xx_SIUMCR_B3DD (1<<4) + +/* + * Value to write to a key register to unlock the corresponding SIU register + */ +#define M8xx_UNLOCK_KEY 0x55CCAA33 + +/* +************************************************************************* +* MPC8xx INTERNAL MEMORY MAP REGISTERS (IMMR provides base address) * +************************************************************************* +*/ +typedef struct m8xx_ { + + /* + * SIU Block + */ + uint32_t siumcr; + uint32_t sypcr; +#if defined(mpc860) + uint32_t swt; +#elif defined(mpc821) + uint32_t _pad70; +#endif + uint16_t _pad0; + uint16_t swsr; + uint32_t sipend; + uint32_t simask; + uint32_t siel; + uint32_t sivec; + uint32_t tesr; + uint32_t _pad1[3]; + uint32_t sdcr; + uint8_t _pad2[0x80-0x34]; + + /* + * PCMCIA Block + */ + uint32_t pbr0; + uint32_t por0; + uint32_t pbr1; + uint32_t por1; + uint32_t pbr2; + uint32_t por2; + uint32_t pbr3; + uint32_t por3; + uint32_t pbr4; + uint32_t por4; + uint32_t pbr5; + uint32_t por5; + uint32_t pbr6; + uint32_t por6; + uint32_t pbr7; + uint32_t por7; + uint8_t _pad3[0xe0-0xc0]; + uint32_t pgcra; + uint32_t pgcrb; + uint32_t pscr; + uint32_t _pad4; + uint32_t pipr; + uint32_t _pad5; + uint32_t per; + uint32_t _pad6; + + /* + * MEMC Block + */ + m8xxMEMCRegisters_t memc[8]; + uint8_t _pad7[0x164-0x140]; + uint32_t mar; + uint32_t mcr; + uint32_t _pad8; + uint32_t mamr; + uint32_t mbmr; + uint16_t mstat; + uint16_t mptpr; + uint32_t mdr; + uint8_t _pad9[0x200-0x180]; + + /* + * System integration timers + */ + uint16_t tbscr; + uint16_t _pad10; + uint32_t tbreff0; + uint32_t tbreff1; + uint8_t _pad11[0x220-0x20c]; + uint16_t rtcsc; + uint16_t _pad12; + uint32_t rtc; + uint32_t rtsec; + uint32_t rtcal; + uint32_t _pad13[4]; + uint16_t piscr; + uint16_t _pad14; + uint16_t pitc; + uint16_t _pad_14_1; + uint16_t pitr; + uint16_t _pad_14_2; + uint8_t _pad15[0x280-0x24c]; + + + /* + * Clocks and Reset + */ + uint32_t sccr; + uint32_t plprcr; + uint32_t rsr; + uint8_t _pad16[0x300-0x28c]; + + + /* + * System integration timers keys + */ + uint32_t tbscrk; + uint32_t tbreff0k; + uint32_t tbreff1k; + uint32_t tbk; + uint32_t _pad17[4]; + uint32_t rtcsk; + uint32_t rtck; + uint32_t rtseck; + uint32_t rtcalk; + uint32_t _pad18[4]; + uint32_t piscrk; + uint32_t pitck; + uint8_t _pad19[0x380-0x348]; + + /* + * Clocks and Reset Keys + */ + uint32_t sccrk; + uint32_t plprck; + uint32_t rsrk; + uint8_t _pad20[0x400-0x38c]; + uint8_t _pad21[0x800-0x400]; + uint8_t _pad22[0x860-0x800]; + + + /* + * I2C + */ + uint8_t i2mod; + uint8_t _pad23[3]; + uint8_t i2add; + uint8_t _pad24[3]; + uint8_t i2brg; + uint8_t _pad25[3]; + uint8_t i2com; + uint8_t _pad26[3]; + uint8_t i2cer; + uint8_t _pad27[3]; + uint8_t i2cmr; + uint8_t _pad28[0x900-0x875]; + + /* + * DMA Block + */ + uint32_t _pad29; + uint32_t sdar; + uint8_t sdsr; + uint8_t _pad30[3]; + uint8_t sdmr; + uint8_t _pad31[3]; + uint8_t idsr1; + uint8_t _pad32[3]; + uint8_t idmr1; + uint8_t _pad33[3]; + uint8_t idsr2; + uint8_t _pad34[3]; + uint8_t idmr2; + uint8_t _pad35[0x930-0x91d]; + + /* + * CPM Interrupt Control Block + */ + uint16_t civr; + uint8_t _pad36[14]; + uint32_t cicr; + uint32_t cipr; + uint32_t cimr; + uint32_t cisr; + + /* + * I/O Port Block + */ + uint16_t padir; + uint16_t papar; + uint16_t paodr; + uint16_t padat; + uint8_t _pad37[8]; + uint16_t pcdir; + uint16_t pcpar; + uint16_t pcso; + uint16_t pcdat; + uint16_t pcint; + uint8_t _pad39[6]; + uint16_t pddir; + uint16_t pdpar; + uint16_t _pad40; + uint16_t pddat; + uint8_t _pad41[8]; + + /* + * CPM Timers Block + */ + uint16_t tgcr; + uint8_t _pad42[14]; + uint16_t tmr1; + uint16_t tmr2; + uint16_t trr1; + uint16_t trr2; + uint16_t tcr1; + uint16_t tcr2; + uint16_t tcn1; + uint16_t tcn2; + uint16_t tmr3; + uint16_t tmr4; + uint16_t trr3; + uint16_t trr4; + uint16_t tcr3; + uint16_t tcr4; + uint16_t tcn3; + uint16_t tcn4; + uint16_t ter1; + uint16_t ter2; + uint16_t ter3; + uint16_t ter4; + uint8_t _pad43[8]; + + /* + * CPM Block + */ + uint16_t cpcr; + uint16_t _pad44; + uint16_t rccr; + uint8_t _pad45; + uint8_t rmds; + uint32_t rmdr; + uint16_t rctr1; + uint16_t rctr2; + uint16_t rctr3; + uint16_t rctr4; + uint16_t _pad46; + uint16_t rter; + uint16_t _pad47; + uint16_t rtmr; + uint8_t _pad48[0x9f0-0x9dc]; + + /* + * BRG Block + */ + uint32_t brgc1; + uint32_t brgc2; + uint32_t brgc3; + uint32_t brgc4; + + /* + * SCC Block + */ + m8xxSCCRegisters_t scc1; + m8xxSCCRegisters_t scc2; +#if defined(mpc860) + m8xxSCCRegisters_t scc3; + m8xxSCCRegisters_t scc4; +#elif defined(mpc821) + uint8_t _pad72[0xa80-0xa40]; +#endif + + /* + * SMC Block + */ + m8xxSMCRegisters_t smc1; + m8xxSMCRegisters_t smc2; + + /* + * SPI Block + */ + uint16_t spmode; + uint16_t _pad49[2]; + uint8_t spie; + uint8_t _pad50; + uint16_t _pad51; + uint8_t spim; + uint8_t _pad52[2]; + uint8_t spcom; + uint16_t _pad53[2]; + + /* + * PIP Block + */ + uint16_t pipc; + uint16_t _pad54; + uint16_t ptpr; + uint32_t pbdir; + uint32_t pbpar; + uint16_t _pad55; + uint16_t pbodr; + uint32_t pbdat; + uint32_t _pad56[6]; + + /* + * SI Block + */ + uint32_t simode; + uint8_t sigmr; + uint8_t _pad57; + uint8_t sistr; + uint8_t sicmr; + uint32_t _pad58; + uint32_t sicr; + uint16_t sirp[2]; + uint32_t _pad59[3]; + uint8_t _pad60[0xc00-0xb00]; + uint8_t siram[512]; +#if defined(mpc860) + /* + * This is only used on the MPC8xxT - for the Fast Ethernet Controller (FEC) + */ + m8xxFECRegisters_t fec; +#elif defined(mpc821) + uint8_t lcdram[512]; +#endif + uint8_t _pad62[0x2000-0x1000]; + + /* + * Dual-port RAM + */ + uint8_t dpram0[0x200]; /* BD/DATA/UCODE */ + uint8_t dpram1[0x200]; /* BD/DATA/UCODE */ + uint8_t dpram2[0x400]; /* BD/DATA/UCODE */ + uint8_t dpram3[0x600]; /* BD/DATA*/ + uint8_t dpram4[0x200]; /* BD/DATA/UCODE */ + uint8_t _pad63[0x3c00-0x3000]; + + /* When using SCC1 for ethernet, we lose the use of I2C since + * their parameters would overlap. Motorola has a microcode + * patch to move parameters around so that both can be used + * together. It is available on their web site somewhere + * under http://www.mot.com/mpc8xx. If ethernet is used on + * one (or more) of the other SCCs, then other CPM features + * will be unavailable: + * SCC2 -> lose SPI + * SCC3 -> lose SMC1 + * SCC4 -> lose SMC2 + * However, Ethernet only works on SCC1 on the 8xx. + */ + m8xxSCCENparms_t scc1p; + uint8_t _rsv1[0xCB0-0xC00-sizeof(m8xxSCCENparms_t)]; + m8xxMiscParms_t miscp; + uint8_t _rsv2[0xcc0-0xCB0-sizeof(m8xxMiscParms_t)]; + m8xxIDMAparms_t idma1p; + uint8_t _rsv3[0xd00-0xcc0-sizeof(m8xxIDMAparms_t)]; + + m8xxSCCparms_t scc2p; + uint8_t _rsv4[0xD80-0xD00-sizeof(m8xxSCCparms_t)]; + m8xxSPIparms_t spip; + uint8_t _rsv5[0xDB0-0xD80-sizeof(m8xxSPIparms_t)]; + m8xxTimerParms_t tmp; + uint8_t _rsv6[0xDC0-0xDB0-sizeof(m8xxTimerParms_t)]; + m8xxIDMAparms_t idma2p; + uint8_t _rsv7[0xE00-0xDC0-sizeof(m8xxIDMAparms_t)]; + + m8xxSCCparms_t scc3p; /* Not available on MPC821 */ + uint8_t _rsv8[0xE80-0xE00-sizeof(m8xxSCCparms_t)]; + m8xxSMCparms_t smc1p; + uint8_t _rsv9[0xEC0-0xE80-sizeof(m8xxSMCparms_t)]; + m8xxDSPparms_t dsp1p; + uint8_t _rsv10[0xF00-0xEC0-sizeof(m8xxDSPparms_t)]; + + m8xxSCCparms_t scc4p; /* Not available on MPC821 */ + uint8_t _rsv11[0xF80-0xF00-sizeof(m8xxSCCparms_t)]; + m8xxSMCparms_t smc2p; + uint8_t _rsv12[0xFC0-0xF80-sizeof(m8xxSMCparms_t)]; + m8xxDSPparms_t dsp2p; + uint8_t _rsv13[0x1000-0xFC0-sizeof(m8xxDSPparms_t)]; +} m8xx_t; + +extern volatile m8xx_t m8xx; + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _MPC8XX_H */ diff --git a/bsps/powerpc/include/mpc8xx/console.h b/bsps/powerpc/include/mpc8xx/console.h new file mode 100644 index 0000000000..eea561e7eb --- /dev/null +++ b/bsps/powerpc/include/mpc8xx/console.h @@ -0,0 +1,32 @@ +#ifndef _MPC8XX_CONSOLE_H +#define _MPC8XX_CONSOLE_H + +#include + +void m8xx_uart_initialize(void); +void m8xx_uart_interrupts_initialize(void); +void m8xx_uart_scc_initialize (int minor); +void m8xx_uart_smc_initialize (int minor); + +/* Termios callbacks */ +int m8xx_uart_pollRead(int minor); +ssize_t m8xx_uart_pollWrite(int minor, const char* buf, size_t len); +ssize_t m8xx_uart_write(int minor, const char *buf, size_t len); +int m8xx_uart_setAttributes(int, const struct termios* t); + + +#ifdef mpc860 +#define NUM_PORTS 6 /* number of serial ports for mpc860 */ +#else +#define NUM_PORTS 4 /* number of serial ports for mpc821 */ +#endif + +#define SMC1_MINOR 0 +#define SMC2_MINOR 1 +#define SCC1_MINOR 2 +#define SCC2_MINOR 3 +#define SCC3_MINOR 4 +#define SCC4_MINOR 5 + + +#endif diff --git a/bsps/powerpc/include/mpc8xx/cpm.h b/bsps/powerpc/include/mpc8xx/cpm.h new file mode 100644 index 0000000000..49889bdc32 --- /dev/null +++ b/bsps/powerpc/include/mpc8xx/cpm.h @@ -0,0 +1,36 @@ +/* + * cpm.h + * + * This include file contains definitions pertaining + * to the Communications Processor Module (CPM) on the MPC8xx. + * + * Copyright (c) 1999, National Research Council of Canada + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MPC8XX_CPM_H +#define _MPC8XX_CPM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Functions */ + +void m8xx_cp_execute_cmd( uint16_t command ); +void *m8xx_dpram_allocate( unsigned int byte_count ); + +#define m8xx_bd_allocate(count) \ + m8xx_dpram_allocate( (count) * sizeof(m8xxBufferDescriptor_t) ) +#define m8xx_RISC_timer_table_allocate(count) \ + m8xx_dpram_allocate( (count) * 4 ) + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/powerpc/include/mpc8xx/mmu.h b/bsps/powerpc/include/mpc8xx/mmu.h new file mode 100644 index 0000000000..f818b14be1 --- /dev/null +++ b/bsps/powerpc/include/mpc8xx/mmu.h @@ -0,0 +1,47 @@ +/* + * mmu.h + * + * This include file contains definitions pertaining + * to the MMU on the MPC8xx. + * + * Copyright (c) 1999, National Research Council of Canada + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MPC8XX_MMU_H +#define _MPC8XX_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The MMU_TLB_table is used to statically initialize the Table Lookaside + * Buffers in the MMU of an MPC8xx. + */ +typedef struct { + uint32_t mmu_epn; /* Effective Page Number */ + uint32_t mmu_twc; /* Tablewalk Control Register */ + uint32_t mmu_rpn; /* Real Page Number */ +} MMU_TLB_table_t; + +/* + * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be + * supplied by the BSP. + */ +extern MMU_TLB_table_t MMU_TLB_table[]; /* MMU TLB table supplied by BSP */ +extern int MMU_N_TLB_Table_Entries; /* Number of entries in MMU TLB table */ + +/* Functions */ + +void mmu_init( void ); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/powerpc/include/nvram.h b/bsps/powerpc/include/nvram.h new file mode 100644 index 0000000000..f579544336 --- /dev/null +++ b/bsps/powerpc/include/nvram.h @@ -0,0 +1,167 @@ +/* + * PreP compliant NVRAM access + * + * This file can be found in motorla or IBP PPC site. + */ + +#ifndef _PPC_NVRAM_H +#define _PPC_NVRAM_H + +#define NVRAM_AS0 0x74 +#define NVRAM_AS1 0x75 +#define NVRAM_DATA 0x77 + +/* RTC Offsets */ + +#define MOTO_RTC_SECONDS 0x1FF9 +#define MOTO_RTC_MINUTES 0x1FFA +#define MOTO_RTC_HOURS 0x1FFB +#define MOTO_RTC_DAY_OF_WEEK 0x1FFC +#define MOTO_RTC_DAY_OF_MONTH 0x1FFD +#define MOTO_RTC_MONTH 0x1FFE +#define MOTO_RTC_YEAR 0x1FFF +#define MOTO_RTC_CONTROLA 0x1FF8 +#define MOTO_RTC_CONTROLB 0x1FF9 + +#ifndef BCD_TO_BIN +#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) +#endif + +#ifndef BIN_TO_BCD +#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) +#endif + +/* Structure map for NVRAM on PowerPC Reference Platform */ +/* All fields are either character/byte strings which are valid either + endian or they are big-endian numbers. + + There are a number of Date and Time fields which are in RTC format, + big-endian. These are stored in UT (GMT). + + For enum's: if given in hex then they are bit significant, i.e. only + one bit is on for each enum. +*/ + +#define NVSIZE 4096 /* size of NVRAM */ +#define OSAREASIZE 512 /* size of OSArea space */ +#define CONFSIZE 1024 /* guess at size of Configuration space */ + +#ifndef ASM + +typedef struct _SECURITY { + unsigned long BootErrCnt; /* Count of boot password errors */ + unsigned long ConfigErrCnt; /* Count of config password errors */ + unsigned long BootErrorDT[2]; /* Date&Time from RTC of last error in pw */ + unsigned long ConfigErrorDT[2]; /* Date&Time from RTC of last error in pw */ + unsigned long BootCorrectDT[2]; /* Date&Time from RTC of last correct pw */ + unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */ + unsigned long BootSetDT[2]; /* Date&Time from RTC of last set of pw */ + unsigned long ConfigSetDT[2]; /* Date&Time from RTC of last set of pw */ + unsigned char Serial[16]; /* Box serial number */ +} SECURITY; + +typedef enum _OS_ID { + Unknown = 0, + Firmware = 1, + AIX = 2, + NT = 3, + MKOS2 = 4, + MKAIX = 5, + Taligent = 6, + Solaris = 7, + MK = 12 +} OS_ID; + +typedef struct _ERROR_LOG { + unsigned char ErrorLogEntry[40]; /* To be architected */ +} ERROR_LOG; + +typedef enum _BOOT_STATUS { + BootStarted = 0x01, + BootFinished = 0x02, + RestartStarted = 0x04, + RestartFinished = 0x08, + PowerFailStarted = 0x10, + PowerFailFinished = 0x20, + ProcessorReady = 0x40, + ProcessorRunning = 0x80, + ProcessorStart = 0x0100 +} BOOT_STATUS; + +typedef struct _RESTART_BLOCK { + unsigned short Version; + unsigned short Revision; + unsigned long ResumeReserve1[2]; + volatile unsigned long BootStatus; + unsigned long CheckSum; /* Checksum of RESTART_BLOCK */ + void* RestartAddress; + void* SaveAreaAddr; + unsigned long SaveAreaLength; +} RESTART_BLOCK; + +typedef enum _OSAREA_USAGE { + Empty = 0, + Used = 1 +} OSAREA_USAGE; + +typedef enum _PM_MODE { + Suspend = 0x80, /* Part of state is in memory */ + Normal = 0x00 /* No power management in effect */ +} PMMode; + +typedef struct _HEADER { + unsigned short Size; /* NVRAM size in K(1024) */ + unsigned char Version; /* Structure map different */ + unsigned char Revision; /* Structure map the same -may + be new values in old fields + in other words old code still works */ + unsigned short Crc1; /* check sum from beginning of nvram to OSArea */ + unsigned short Crc2; /* check sum of config */ + unsigned char LastOS; /* OS_ID */ + unsigned char Endian; /* B if big endian, L if little endian */ + unsigned char OSAreaUsage;/* OSAREA_USAGE */ + unsigned char PMMode; /* Shutdown mode */ + RESTART_BLOCK RestartBlock; + SECURITY Security; + ERROR_LOG ErrorLog[2]; + + /* Global Environment information */ + void* GEAddress; + unsigned long GELength; + + /* Date&Time from RTC of last change to Global Environment */ + unsigned long GELastWriteDT[2]; + + /* Configuration information */ + void* ConfigAddress; + unsigned long ConfigLength; + + /* Date&Time from RTC of last change to Configuration */ + unsigned long ConfigLastWriteDT[2]; + unsigned long ConfigCount; /* Count of entries in Configuration */ + + /* OS dependent temp area */ + void* OSAreaAddress; + unsigned long OSAreaLength; + + /* Date&Time from RTC of last change to OSArea */ + unsigned long OSAreaLastWriteDT[2]; +} HEADER; + +/* Here is the whole map of the NVRAM */ +typedef struct _NVRAM_MAP { + HEADER Header; + unsigned char GEArea[NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)]; + unsigned char OSArea[OSAREASIZE]; + unsigned char ConfigArea[CONFSIZE]; +} NVRAM_MAP; + +/* Routines to manipulate the NVRAM */ +void init_prep_nvram(void); +char *prep_nvram_get_var(const char *name); +char *prep_nvram_first_var(void); +char *prep_nvram_next_var(char *name); + +#endif /* ASM */ + +#endif /* _PPC_NVRAM_H */ diff --git a/bsps/powerpc/include/ppc4xx/ppc405ex.h b/bsps/powerpc/include/ppc4xx/ppc405ex.h new file mode 100644 index 0000000000..98ebbe28a2 --- /dev/null +++ b/bsps/powerpc/include/ppc4xx/ppc405ex.h @@ -0,0 +1,191 @@ +/* + +Constants for manipulating system registers of PPC 405EX in C + +Michael Hamel ADInstruments May 2008 + +*/ + +#include +/* Indirect access to Clocking/Power-On registers */ +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) + +#define mtcpr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ + PPC_SET_DEVICE_CONTROL_REGISTER(cprcfgd,d); \ + } while (0) + +#define mfcpr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ + d = PPC_DEVICE_CONTROL_REGISTER(cprcfgd); \ + } while (0) + + +/* Indirect access to System registers */ +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) + +#define mtsdr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ + PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfgd,d); \ + } while (0) + +#define mfsdr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ + d = PPC_DEVICE_CONTROL_REGISTER(sdrcfgd); \ + } while (0) + +/* Indirect access to EBC registers */ +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) +#define ebccfgd (EBC_DCR_BASE+0x1) + +#define mtebc(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ + PPC_SET_DEVICE_CONTROL_REGISTER(ebccfgd,d); \ + } while (0) + +#define mfebc(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ + d = PPC_DEVICE_CONTROL_REGISTER(ebccfgd); \ + } while (0) + +/* EBC DCRs */ +enum { + /* + EBC0_B0CR = 0, + EBC0_B1CR = 1, + EBC0_B2CR = 2, + EBC0_B3CR = 3, + EBC0_B0AP = 0x10, + EBC0_B1AP = 0x11, + EBC0_B2AP = 0x12, + EBC0_B3AP = 0x13, + EBC0_BEAR = 0x20, + EBC0_BESR = 0x21, + EBC0_CFG = 0x23, + */ + EBC0_CID = 0x24 +}; + +enum { + SDR0_PINSTP = 0x40, + SDR0_UART0 = 0x120, + SDR0_UART1 = 0x121, + SDR0_C405 = 0x180, + SDR0_SRST0 = 0x200, + SDR0_MALTBL = 0x280, + SDR0_MALRBL = 0x2A0, + SDR0_MALTBS = 0x2C0, + SDR0_MALRBS = 0x2E0, + SDR0_PFC2 = 0x4102, + SDR0_MFR = 0x4300, + SDR0_EMAC0RXST = 0x4301, + SDR0_HSF = 0x4400 +}; + +enum { + CPR0_CLKUPD = 0x20, + CPR0_PLLC = 0x40, + CPR0_PLLD = 0x60, + CPR0_CPUD = 0x80, + CPR0_PLBD = 0xA0, + CPR0_OPBD = 0xC0, + CPR0_PERD = 0xE0, + CPR0_AHBD = 0x100, + CPR0_ICFG = 0x140 +}; + +/* Memory-mapped registers */ + + +/*======================= Ethernet =================== */ + +enum { + EMAC0EXAddress = 0xEF600900, + EMAC1EXAddress = 0xEF600A00, + + /* 405EX-specific bits in EMAC_MR1 */ + keEMAC1000Mbps = 0x00800000, + keEMAC16KRxFIFO = 0x00280000, + keEMAC8KRxFIFO = 0x00200000, + keEMAC4KRxFIFO = 0x00180000, + keEMAC2KRxFIFO = 0x00100000, + keEMAC1KRxFIFO = 0x00080000, + keEMAC16KTxFIFO = 0x00050000, + keEMAC8KTxFIFO = 0x00040000, + keEMAC4KTxFIFO = 0x00030000, + keEMAC2KTxFIFO = 0x00020000, + keEMAC1KTxFIFO = 0x00010000, + keEMACJumbo = 0x00000800, + keEMACIPHYAddr4 = 0x180, + keEMACOPB50MHz = 0x00, + keEMACOPB66MHz = 0x08, + keEMACOPB83MHz = 0x10, + keEMACOPB100MHz = 0x18, + keEMACOPBGt100 = 0x20, + + /* 405EX-specific bits in MAL0_CFG */ + keMALRdMaxBurst4 = 0, + keMALRdMaxBurst8 = 0x00100000, + keMALRdMaxBurst16 = 0x00200000, + keMALRdMaxBurst32 = 0x00300000, + + keMALWrLowPriority = 0, + keMALWrMedLowPriority = 0x00040000, + keMALWrMedHiPriority = 0x00080000, + keMALWrHighPriority = 0x000C0000, + + keMALWrMaxBurst4 = 0, + keMALWrMaxBurst8 = 0x00010000, + keMALWrMaxBurst16 = 0x00020000, + keMALWrMaxBurst32 = 0x00030000, + + /* 405EX-specific STA bits */ + keSTARun = 0x8000, + keSTADirectRd = 0x1000, + keSTADirectWr = 0x0800, + keSTAIndirAddr = 0x2000, + keSTAIndirRd = 0x3000, + keSTAIndirWr = 0x2800 +}; + +typedef struct GPIORegisters { + uint32_t OR; + uint32_t GPIO_TCR; /* Note that TCR is defined as a DCR name */ + uint32_t OSRL; + uint32_t OSRH; + uint32_t TSRL; + uint32_t TSRH; + uint32_t ODR; + uint32_t IR; + uint32_t RR1; + uint32_t RR2; + uint32_t RR3; + uint32_t unknown; + uint32_t ISR1L; + uint32_t ISR1H; + uint32_t ISR2L; + uint32_t ISR2H; + uint32_t ISR3L; + uint32_t ISR3H; +} GPIORegisters; + +enum { GPIOAddress = 0xEF600800 }; + +typedef struct RGMIIRegisters { + uint32_t FER; + uint32_t SSR; +} RGMIIRegisters; + +enum { RGMIIAddress = 0xEF600B00 }; + diff --git a/bsps/powerpc/include/ppc4xx/ppc405gp.h b/bsps/powerpc/include/ppc4xx/ppc405gp.h new file mode 100644 index 0000000000..9cf46a780a --- /dev/null +++ b/bsps/powerpc/include/ppc4xx/ppc405gp.h @@ -0,0 +1,214 @@ + +/* SDRAM DCRs */ +enum { + SDRAM0_BESR0 = 0, + SDRAM0_BESR1 = 8, + SDRAM0_BEAR = 0x10, + SDRAM0_CFG = 0x20, + SDRAM0_STATUS = 0x24, + SDRAM0_RTR = 0x30, + SDRAM0_PMIT = 0x34, + SDRAM0_TR = 0x80 +}; + + +/* EBC DCRs */ +enum { + EBC0_B0CR = 0, + EBC0_B1CR = 1, + EBC0_B2CR = 2, + EBC0_B3CR = 3, + EBC0_B4CR = 4, + EBC0_B5CR = 5, + EBC0_B6CR = 6, + EBC0_B7CR = 7, + EBC0_B0AP = 0x10, + EBC0_B1AP = 0x11, + EBC0_B2AP = 0x12, + EBC0_B3AP = 0x13, + EBC0_B4AP = 0x14, + EBC0_B5AP = 0x15, + EBC0_B6AP = 0x16, + EBC0_B7AP = 0x17, + EBC0_BEAR = 0x20, + EBC0_BESR0 = 0x21, + EBC0_BESR1 = 0x22, + EBC0_CFG = 0x23 +}; + +/* MAL DCRs, have to be #defines */ +#define MAL0_CFG 0x180 +#define MAL0_ESR 0x181 +#define MAL0_IER 0x182 +#define MAL0_TXCASR 0x184 +#define MAL0_TXCARR 0x185 +#define MAL0_TXEOBISR 0x186 +#define MAL0_TXDEIR 0x187 +#define MAL0_RXCASR 0x190 +#define MAL0_RXCARR 0x191 +#define MAL0_RXEOBISR 0x192 +#define MAL0_RXDEIR 0x193 +#define MAL0_TXCTP0R 0x1A0 +#define MAL0_TXCTP1R 0x1A1 +#define MAL0_RXCTP0R 0x1C0 +#define MAL0_RXCTP1R 0x1C1 +#define MAL0_RCBS0 0x1E0 +#define MAL0_RCBS1 0x1E1 + +/* Memory-mapped registers */ + +typedef struct EthernetRegisters_GP { + uint32_t mode0; + uint32_t mode1; + uint32_t xmtMode0; + uint32_t xmtMode1; + uint32_t rcvMode; + uint32_t intStatus; + uint32_t intEnable; + uint32_t addrHi; + uint32_t addrLo; + uint32_t VLANTPID; + uint32_t VLANTCI; + uint32_t pauseTimer; + uint32_t g_indivHash[4]; /* EX non-IP multicast addr/mask */ + uint32_t g_groupHash[4]; + uint32_t lastSrcLo; + uint32_t lastSrcHi; + uint32_t IPGap; + uint32_t STAcontrol; + uint32_t xmtReqThreshold; + uint32_t rcvWatermarks; + uint32_t bytesXmtd; + uint32_t bytesRcvd; + uint32_t e_unused2; + uint32_t e_revID; + uint32_t e_unused3[2]; + uint32_t e_indivHash[8]; + uint32_t e_groupHash[8]; + uint32_t e_xmtPause; +} EthernetRegisters_GP; + +typedef struct EthernetRegisters_GP EthernetRegisters_EX; + +enum { EMACAddress = 0xEF600800 }; +enum { EMAC0GPAddress = 0xEF600800 }; + +enum { + // Mode 0 bits + kEMACRxIdle = 0x80000000, + kEMACTxIdle = 0x40000000, + kEMACSoftRst = 0x20000000, + kEMACTxEnable = 0x10000000, + kEMACRxEnable = 0x08000000, + + // Mode 1 bits + kEMACFullDuplex = 0x80000000, + kEMACDoFlowControl = 0x10000000, + kEMACIgnoreSQE = 0x01000000, + kEMAC100MBbps = 0x00400000, + kEMAC4KRxFIFO = 0x00300000, + kEMAC2KTxFIFO = 0x00080000, + kEMACTx0Multi = 0x00008000, + kEMACTxDependent= 0x00014000, + kEMAC100Mbps = 0x00400000, + kgEMAC4KRxFIFO = 0x00300000, + kgEMAC2KTxFIFO = 0x00080000, + kgEMACTx0Multi = 0x00008000, + kgEMACTxDependent= 0x00014000, + + + // Tx mode bits + kEMACNewPacket0 = 0x80000000, + kEMACNewPacket1 = 0x40000000, + + // Receive mode bits + kEMACStripPadding = 0x80000000, + kEMACStripFCS = 0x40000000, + kEMACRcvRunts = 0x20000000, + kEMACRcvFCSErrs = 0x10000000, + kEMACRcvOversize = 0x08000000, + kEMACPromiscRcv = 0x01000000, + kEMACPromMultRcv = 0x00800000, + kEMACIndivRcv = 0x00400000, + kEMACHashRcv = 0x00200000, + kEMACBrcastRcv = 0x00100000, + kEMACMultcastRcv = 0x00080000, + keEMACNonIPMultcast = 0x00040000, + keEMACRxFIFOAFMax = 7, + + // EMAC_STACR bits + kgSTAComplete = 0x8000, + kSTAErr = 0x4000, + + // Interrupt status bits + kEMACIOverrun = 0x02000000, + kEMACIPause = 0x01000000, + kEMACIBadPkt = 0x00800000, + kEMACIRuntPkt = 0x00400000, + kEMACIShortEvt= 0x00200000, + kEMACIAlignErr= 0x00100000, + kEMACIBadFCS = 0x00080000, + kEMACIOverSize= 0x00040000, + kEMACILLCRange= 0x00020000, + kEMACISQEErr = 0x00000080, + kEMACITxErr = 0x00000040, + + // Buffer descriptor control bits + kMALTxReady = 0x8000, + kMALRxEmpty = 0x8000, + kMALWrap = 0x4000, + kMALContinuous = 0x2000, + kMALLast = 0x1000, + kMALRxFirst = 0x0800, + kMALInterrupt = 0x0400, + + kMALReset = 0x80000000, + kMALLowPriority = 0, + kMALMedLowPriority = 0x00400000, + kMALMedHiPriority = 0x00800000, + kMALHighPriority = 0x00C00000, + kMALLatency8 = 0x00040000, + kMALLockErr = 0x8000, + kMALCanBurst = 0x4000, + kMALLocksOPB = 0x80, + kMALLocksErrs = 0x2, + + // MAL channel masks + kMALChannel0 = 0x80000000, + kMALChannel1 = 0x40000000, + + // EMAC Tx descriptor bits sent + kEMACGenFCS = 0x200, + kEMACGenPad = 0x100, + kEMACInsSrcAddr = 0x080, + kEMACRepSrcAddr = 0x040, + kEMACInsVLAN = 0x020, + kEMACRepVLAN = 0x010, + + // EMAC TX descriptor bits returned + kEMACErrMask = 0x3FF, + kEMACFCSWrong = 0x200, + kEMACBadPrev = 0x100, + kEMACLostCarrier = 0x080, + kEMACDeferred = 0x040, + kEMACCollFail = 0x020, + kEMACLateColl = 0x010, + kEMACMultColl = 0x008, + kEMACOneColl = 0x004, + kEMACUnderrun = 0x002, + kEMACSQEFail = 0x001, + + // EMAC Rx descriptor bits returned + kEMACOverrun = 0x200, + kEMACPausePkt = 0x100, + kEMACBadPkt = 0x080, + kEMACRuntPkt = 0x040, + kEMACShortEvt = 0x020, + kEMACAlignErr = 0x010, + kEMACBadFCS = 0x008, + kEMACPktLong = 0x004, + kEMACPktOOR = 0x002, + kEMACPktIRL = 0x001 +}; + + diff --git a/bsps/powerpc/include/rtems/powerpc/cache.h b/bsps/powerpc/include/rtems/powerpc/cache.h new file mode 100644 index 0000000000..1fdc75ae8b --- /dev/null +++ b/bsps/powerpc/include/rtems/powerpc/cache.h @@ -0,0 +1,38 @@ +#ifndef _RTEMS_POWERPC_CACHE_H +#define _RTEMS_POWERPC_CACHE_H + +#include /* for PPC_D_CACHE */ + +#ifdef _OLD_EXCEPTIONS + +#if (PPC_D_CACHE != 0) +#define _CPU_Data_Cache_Block_Flush( _address ) \ + do { register void *__address = (_address); \ + register uint32_t _zero = 0; \ + __asm__ volatile ( "dcbf %0,%1" : \ + "=r" (_zero), "=r" (__address) : \ + "0" (_zero), "1" (__address) \ + ); \ + } while (0) +#else +#define _CPU_Data_Cache_Block_Flush( _address ) /* nop */ +#endif + +/* + * FIXME: This is not used anywhere. + */ +#if (PPC_D_CACHE != 0) +#define _CPU_Data_Cache_Block_Invalidate( _address ) \ + do { register void *__address = (_address); \ + register uint32_t _zero = 0; \ + __asm__ volatile ( "dcbi %0,%1" : \ + "=r" (_zero), "=r" (__address) : \ + "0" (_zero), "1" (__address) \ + ); \ + } while (0) +#else +#define _CPU_Data_Cache_Block_Invalidate( _address ) /* nop */ +#endif +#endif + +#endif diff --git a/bsps/powerpc/include/rtems/powerpc/debugmod.h b/bsps/powerpc/include/rtems/powerpc/debugmod.h new file mode 100644 index 0000000000..61b650695c --- /dev/null +++ b/bsps/powerpc/include/rtems/powerpc/debugmod.h @@ -0,0 +1,124 @@ +/* debugmod.h + * + * This file contains definitions for the IBM/Motorola PowerPC + * family members. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * MPC860 support code was added by Jay Monkman + * MPC8260 support added by Andy Dachs + * Surrey Satellite Technology Limited + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * + * Note: + * This file is included by both C and assembler code ( -DASM ) + */ + +/* + * FIXME: This file is not used anywhere inside of RTEMS source-tree. + * Notify OAR if you actually use it, otherwise it might be removed in + * future versions of RTEMS + */ + +#ifndef _RTEMS_POWERPC_DEBUGMOD_H +#define _RTEMS_POWERPC_DEBUGMOD_H + +#warning "please read the FIXME inside of this file" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the PowerPC family. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + * + * The following architectural feature definitions are defaulted + * unless specifically set by the model definition: + * + * + PPC_DEBUG_MODEL - PPC_DEBUG_MODEL_STANDARD + */ + +/* + * Define the debugging assistance models found in the PPC family. + * + * Standard: single step and branch trace + * Single Step Only: single step only + * IBM 4xx: debug exception + */ + +#define PPC_DEBUG_MODEL_STANDARD 1 +#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2 +#define PPC_DEBUG_MODEL_IBM4xx 3 + +#elif defined(ppc403) || defined(ppc405) || defined(ppc440) + +#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_IBM4xx + +#elif defined(ppc601) + +#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY + +#endif + +/* + * Use the default debug scheme defined in the architectural specification + * if another model has not been specified. + */ + +#ifndef PPC_DEBUG_MODEL +#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD +#endif + +/* + * Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming + * Environments" and the manuals for various PPC models. + */ + +#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD) +#define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */ +#define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */ +#define PPC_MSR_SE 0x000000400 /* bit 21 - single step trace enable */ +#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY) +#define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */ +#define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */ +#define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */ +#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx) +#define PPC_MSR_DE 0x000000200 /* bit 22 - debug exception enable */ +#define PPC_MSR_BE 0x000000000 /* bit 22 - branch trace enable */ +#define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */ +#else +#error "MSR constants -- unknown PPC_DEBUG_MODEL!!" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_POWERPC_DEBUGMOD_H */ +/* end of include file */ diff --git a/bsps/powerpc/include/rtems/powerpc/powerpc.h b/bsps/powerpc/include/rtems/powerpc/powerpc.h new file mode 100644 index 0000000000..8b2cf1e371 --- /dev/null +++ b/bsps/powerpc/include/rtems/powerpc/powerpc.h @@ -0,0 +1,644 @@ +/** + * @file rtems/powerpc/powerpc.h + */ + +/* + * This file contains definitions for the IBM/Motorola PowerPC + * family members. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * MPC860 support code was added by Jay Monkman + * MPC8260 support added by Andy Dachs + * Surrey Satellite Technology Limited + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * + * Note: + * This file is included by both C and assembler code ( -DASM ) + */ + + +#ifndef _RTEMS_POWERPC_POWERPC_H +#define _RTEMS_POWERPC_POWERPC_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Till S. 2008/07/10: + * + * Using the macros/definitions which depend on a preprocessor + * symbol defining the CPU flavor is discouraged. + * I recommend to not use definitions from this file and + * in particular - not to add more bits and pieces. + * + * Instead, try to use run-time detection (see e.g. cpuIdent.c/cpuIdent.h) + * of features etc. + */ + +#include + +/* + * Unfortunately it is very inefficient to use run-time detection for the cache + * line size, so give the BSP the opportunity to define it here. + */ +#include + +/* + * This file contains the information required to build + * RTEMS for a particular member of the PowerPC family. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + * + * The following architectural feature definitions are defaulted + * unless specifically set by the model definition: + * + * + PPC_INTERRUPT_MAX - 16 + * + PPC_CACHE_ALIGNMENT + * + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE + * + PPC_HAS_EXCEPTION_PREFIX - 1 + * + PPC_USE_MULTIPLE - 0 + */ + +/* + * Define the low power mode models + * + * Standard: as defined for 603e + * Nap Mode: nap mode only (604) + * XXX 403GB, 603, 603e, 604, 821 + */ + +#define PPC_LOW_POWER_MODE_NONE 0 +#define PPC_LOW_POWER_MODE_STANDARD 1 + +/** + * @brief For boards with no cache set PPC_CACHE_ALIGNMENT to this value. + */ +#define PPC_NO_CACHE_ALIGNMENT 4 + +/** + * @brief Used to define PPC_CACHE_ALIGN_POWER for boards with no cache (and + * PPC_NO_CACHE_ALIGNMENT defined). + */ +#define PPC_NO_CACHE_ALIGNMENT_POWER 2 + +/* + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. + */ + +#if defined(ppc403) +/* + * IBM 403 + * + * Developed for 403GA. Book checked for 403GB. + * + * Does not have user mode. + */ + +#define PPC_CACHE_ALIGNMENT 16 +#define PPC_HAS_RI 0 +#define PPC_HAS_RFCI 1 +#define PPC_USE_MULTIPLE 1 +#define PPC_I_CACHE 2048 +#define PPC_D_CACHE 1024 + +#define PPC_HAS_EXCEPTION_PREFIX 0 +#define PPC_HAS_EVPR 1 + +#elif defined (ppc405) + +#define PPC_CACHE_ALIGNMENT 32 +#define PPC_HAS_RI 0 +#define PPC_HAS_RFCI 1 +#define PPC_USE_MULTIPLE 1 +#define PPC_I_CACHE 16384 +#define PPC_D_CACHE 16384 /* except GP/CR */ +#define PPC_HAS_EXCEPTION_PREFIX 0 +#define PPC_HAS_EVPR 1 + +#elif defined (ppc440) + +#define PPC_CACHE_ALIGNMENT 32 +#define PPC_HAS_RI 0 +#define PPC_HAS_RFCI 1 +#define PPC_USE_MULTIPLE 1 +#define PPC_I_CACHE 32768 +#define PPC_D_CACHE 32768 +#define PPC_HAS_EXCEPTION_PREFIX 0 +#define PPC_HAS_EVPR 1 + +#elif defined(mpc555) + +/* Copied from mpc505 */ +#define PPC_CACHE_ALIGNMENT PPC_NO_CACHE_ALIGNMENT + +/* Added by querbach@realtime.bc.ca */ +#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD + +/* Based on comments by Sergei Organov */ +#define PPC_I_CACHE 0 +#define PPC_D_CACHE 0 + +#elif defined(mpc505) || defined(mpc509) +/* + * Submitted by Sergei Organov as a patch against + * 3.6.0 long after 4.0 was released. This is just an attempt + * to get the setting correct. + */ + +#define CPU_MODEL_NAME "PowerPC 505/509" + +#define PPC_CACHE_ALIGNMENT PPC_NO_CACHE_ALIGNMENT +#define PPC_I_CACHE 4096 +#define PPC_D_CACHE 0 + + +#elif defined(ppc601) + +/* + * Submitted with original port -- book checked only. + */ + +#define PPC_USE_MULTIPLE 1 +#define PPC_I_CACHE 0 +#define PPC_D_CACHE 32768 + +#elif defined(ppc603) +/* + * Submitted with original port -- book checked only. + */ + +#define PPC_I_CACHE 8192 +#define PPC_D_CACHE 8192 + +#elif defined(ppc603e) + +/* + * Submitted with original port. + * + * Known to work on real hardware. + */ + +#define PPC_I_CACHE 16384 +#define PPC_D_CACHE 16384 + +#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD + +#elif defined(mpc604) +/* + * Submitted with original port -- book checked only. + */ + +#define PPC_I_CACHE 16384 +#define PPC_D_CACHE 16384 + +#elif defined(mpc860) +/* + * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 + * with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca) + */ +#define PPC_I_CACHE 4096 +#define PPC_D_CACHE 4096 +#define PPC_CACHE_ALIGNMENT 16 +#define PPC_INTERRUPT_MAX 71 +#define PPC_USE_MULTIPLE 1 + +#define PPC_MSR_0 0x00009000 +#define PPC_MSR_1 0x00001000 +#define PPC_MSR_2 0x00001000 +#define PPC_MSR_3 0x00000000 + +#elif defined(mpc821) +/* + * Added by Andrew Bray 6/April/1999 + */ +#define PPC_I_CACHE 4096 +#define PPC_D_CACHE 4096 +#define PPC_CACHE_ALIGNMENT 16 +#define PPC_INTERRUPT_MAX 71 + +#define PPC_MSR_0 0x00009000 +#define PPC_MSR_1 0x00001000 +#define PPC_MSR_2 0x00001000 +#define PPC_MSR_3 0x00000000 + +#elif defined(mpc750) + +#define PPC_I_CACHE 16384 +#define PPC_D_CACHE 16384 + +#elif defined(mpc7400) + +#define PPC_I_CACHE 32768 +#define PPC_D_CACHE 32768 + +#elif defined(mpc7455) +/* + * Added by S.K. Feng 10/03 + */ + +#define PPC_CACHE_ALIGNMENT 32 +#define PPC_I_CACHE 32768 +#define PPC_D_CACHE 32768 + +#elif defined(mpc8260) +/* + * Added by Andy Dachs 23/11/2000 + */ +#define PPC_I_CACHE 16384 +#define PPC_D_CACHE 16384 +#define PPC_CACHE_ALIGNMENT 32 +#define PPC_INTERRUPT_MAX 125 +#define PPC_USE_MULTIPLE 1 + +#elif defined(__ppc_generic) + +#else + +#error "Unsupported CPU Model" + +#endif + +/* + * If the maximum number of exception sources has not been defined, + * then default it to 16. + */ + +#ifndef PPC_INTERRUPT_MAX +#define PPC_INTERRUPT_MAX 16 +#endif + +#ifndef PPC_CACHE_ALIGNMENT +#define PPC_CACHE_ALIGNMENT PPC_DEFAULT_CACHE_LINE_SIZE +#endif + +#if (PPC_CACHE_ALIGNMENT == 16) +#define PPC_CACHE_ALIGN_POWER 4 +#elif (PPC_CACHE_ALIGNMENT == 32) +#define PPC_CACHE_ALIGN_POWER 5 +#elif (PPC_CACHE_ALIGNMENT == 64) +#define PPC_CACHE_ALIGN_POWER 6 +#elif (PPC_CACHE_ALIGNMENT == PPC_NO_CACHE_ALIGNMENT) +#define PPC_CACHE_ALIGN_POWER PPC_NO_CACHE_ALIGNMENT_POWER +#else +#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT" +#endif + +/* + * Unless otherwise specified, assume the model has an IP/EP bit to + * set the exception address prefix. + */ + +#ifndef PPC_HAS_EXCEPTION_PREFIX +#define PPC_HAS_EXCEPTION_PREFIX 1 +#endif +/* + * Unless otherwise specified, assume the model has an RI bit to + * identify non-recoverable interrupts + */ + +#ifndef PPC_HAS_RI +#define PPC_HAS_RI 1 +#endif + +/* + * Unless otherwise specified, assume the model does NOT have + * 403 style EVPR register to set the exception address prefix. + */ + +#ifndef PPC_HAS_EVPR +#define PPC_HAS_EVPR 0 +#endif + +/* + * If no low power mode model was specified, then assume there is none. + */ + +#ifndef PPC_LOW_POWER_MODE +#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE +#endif + +/* + * Unless specified above, then assume the model does NOT have critical + * interrupt support. + */ + +#ifndef PPC_HAS_RFCI +#define PPC_HAS_RFCI 0 +#endif + +/* + * Unless specified above, do not use the load/store multiple instructions + * in a context switch. + */ + +#ifndef PPC_USE_MULTIPLE +#define PPC_USE_MULTIPLE 0 +#endif + +/* + * The following exceptions are not maskable, and are not + * necessarily predictable, so cannot be offered to RTEMS: + * Alignment exception - handled by the CPU module + * Data exceptions. + * Instruction exceptions. + */ + +/* + * Base Interrupt vectors supported on all models. + */ +#define PPC_IRQ_SYSTEM_RESET 0 /* 0x00100 - System reset. */ +#define PPC_IRQ_MCHECK 1 /* 0x00200 - Machine check */ +#define PPC_IRQ_PROTECT 2 /* 0x00300 - Protection violation */ +#define PPC_IRQ_ISI 3 /* 0x00400 - Instruction Fetch error */ +#define PPC_IRQ_EXTERNAL 4 /* 0x00500 - External interrupt */ +#define PPC_IRQ_ALIGNMENT 5 /* 0X00600 - Alignment exception */ +#define PPC_IRQ_PROGRAM 6 /* 0x00700 - Program exception */ +#define PPC_IRQ_NOFP 7 /* 0x00800 - Floating point unavailable */ +#define PPC_IRQ_DECREMENTER 8 /* 0x00900 - Decrementer interrupt */ +#define PPC_IRQ_RESERVED_A 9 /* 0x00a00 - Implementation Reserved */ +#define PPC_IRQ_RESERVED_B 10 /* 0x00b00 - Implementation Reserved */ +#define PPC_IRQ_SCALL 11 /* 0x00c00 - System call */ +#define PPC_IRQ_TRACE 12 /* 0x00d00 - Trace Exception */ +#define PPC_IRQ_FP_ASST 13 /* ox00e00 - Floating point assist */ +#define PPC_STD_IRQ_LAST PPC_IRQ_FP_ASST + +#define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET + +#if defined(ppc403) || defined(ppc405) || defined(ppc440) + +#define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ +#define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ +#define PPC_IRQ_FIT (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer */ +#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer */ +#define PPC_IRQ_DEBUG (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions */ +#define PPC_IRQ_LAST PPC_IRQ_DEBUG + +#elif defined(mpc505) || defined(mpc509) +#define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ +#define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+ 2) +#define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+ 3) +#define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+ 4) +#define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+ 5) + +#elif defined(mpc555) +#define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ +#define PPC_IRQ_INST_PE (PPC_STD_IRQ_LAST+2) /* Insn protection error */ +#define PPC_IRQ_DATA_PE (PPC_STD_IRQ_LAST+3) /* Data protection error */ +#define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+4) /* Data breakpoint */ +#define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+5) /* Insn breakpoint */ +#define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+6) /* Maskable ext bkpt */ +#define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+7) /* Non-maskable ext bkpt */ +#define PPC_IRQ_LAST PPC_IRQ_NMEXT_BP + +#elif defined(ppc601) +#undef PPC_IRQ_TRACE +#define PPC_IRQ_TRACE (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/ +#define PPC_IRQ_LAST PPC_IRQ_TRACE + +#elif defined(ppc602) +#define PPC_IRQ_LAST (PPC_STD_IRQ_LAST) + +#elif defined(ppc603) || defined(ppc603e) +#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/ +#define PPC_IRQ_DATA_LOAD (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/ +#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss */ +#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */ +#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ +#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT + +#elif defined(mpc604) +#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break */ +#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */ +#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT + +#elif defined(mpc860) || defined(mpc821) +#define PPC_IRQ_EMULATE (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation */ +#define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/ +#define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */ +#define PPC_IRQ_INST_ERR (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */ +#define PPC_IRQ_DATA_ERR (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */ +#define PPC_IRQ_DATA_BPNT (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */ +#define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */ +#define PPC_IRQ_IO_BPNT (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */ +#define PPC_IRQ_DEV_PORT (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */ +#define PPC_IRQ_IRQ0 (PPC_STD_IRQ_LAST + 10) +#define PPC_IRQ_LVL0 (PPC_STD_IRQ_LAST + 11) +#define PPC_IRQ_IRQ1 (PPC_STD_IRQ_LAST + 12) +#define PPC_IRQ_LVL1 (PPC_STD_IRQ_LAST + 13) +#define PPC_IRQ_IRQ2 (PPC_STD_IRQ_LAST + 14) +#define PPC_IRQ_LVL2 (PPC_STD_IRQ_LAST + 15) +#define PPC_IRQ_IRQ3 (PPC_STD_IRQ_LAST + 16) +#define PPC_IRQ_LVL3 (PPC_STD_IRQ_LAST + 17) +#define PPC_IRQ_IRQ4 (PPC_STD_IRQ_LAST + 18) +#define PPC_IRQ_LVL4 (PPC_STD_IRQ_LAST + 19) +#define PPC_IRQ_IRQ5 (PPC_STD_IRQ_LAST + 20) +#define PPC_IRQ_LVL5 (PPC_STD_IRQ_LAST + 21) +#define PPC_IRQ_IRQ6 (PPC_STD_IRQ_LAST + 22) +#define PPC_IRQ_LVL6 (PPC_STD_IRQ_LAST + 23) +#define PPC_IRQ_IRQ7 (PPC_STD_IRQ_LAST + 24) +#define PPC_IRQ_LVL7 (PPC_STD_IRQ_LAST + 25) +#define PPC_IRQ_CPM_ERROR (PPC_STD_IRQ_LAST + 26) +#define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 27) +#define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 28) +#define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 29) +#define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 30) +#define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 31) +#define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 32) +#define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 33) +#define PPC_IRQ_CPM_RESERVED_8 (PPC_STD_IRQ_LAST + 34) +#define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 35) +#define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 36) +#define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 37) +#define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 38) +#define PPC_IRQ_CPM_RESERVED_D (PPC_STD_IRQ_LAST + 39) +#define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 40) +#define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 41) +#define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 42) +#define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 43) +#define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 44) +#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45) +#define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 46) +#define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 47) +#define PPC_IRQ_CPM_SDMA_ERROR (PPC_STD_IRQ_LAST + 48) +#define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 49) +#define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 50) +#define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 51) +#define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 52) +#define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 53) +#define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 54) +#define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 55) +#define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 56) +#define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 57) + +#define PPC_IRQ_LAST PPC_IRQ_CPM_PC15 + +#elif defined(mpc8260) + +#define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/ +#define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */ +#define PPC_IRQ_DATA_L_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */ +#define PPC_IRQ_DATA_S_MISS (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */ +#define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */ +#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */ +/* 0x1600 - 0x2F00 reserved */ +#define PPC_IRQ_CPM_NONE (PPC_STD_IRQ_LAST + 50) +#define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 51) +#define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 52) +#define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 53) +#define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 54) +#define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 55) +#define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 56) +#define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 57) +#define PPC_IRQ_CPM_IDMA3 (PPC_STD_IRQ_LAST + 58) +#define PPC_IRQ_CPM_IDMA4 (PPC_STD_IRQ_LAST + 59) +#define PPC_IRQ_CPM_SDMA (PPC_STD_IRQ_LAST + 60) +#define PPC_IRQ_CPM_RES_A (PPC_STD_IRQ_LAST + 61) +#define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 62) +#define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 63) +#define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 64) +#define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 65) +#define PPC_IRQ_CPM_TMCNT (PPC_STD_IRQ_LAST + 66) +#define PPC_IRQ_CPM_PIT (PPC_STD_IRQ_LAST + 67) +#define PPC_IRQ_CPM_RES_B (PPC_STD_IRQ_LAST + 68) +#define PPC_IRQ_CPM_IRQ1 (PPC_STD_IRQ_LAST + 69) +#define PPC_IRQ_CPM_IRQ2 (PPC_STD_IRQ_LAST + 70) +#define PPC_IRQ_CPM_IRQ3 (PPC_STD_IRQ_LAST + 71) +#define PPC_IRQ_CPM_IRQ4 (PPC_STD_IRQ_LAST + 72) +#define PPC_IRQ_CPM_IRQ5 (PPC_STD_IRQ_LAST + 73) +#define PPC_IRQ_CPM_IRQ6 (PPC_STD_IRQ_LAST + 74) +#define PPC_IRQ_CPM_IRQ7 (PPC_STD_IRQ_LAST + 75) +#define PPC_IRQ_CPM_RES_C (PPC_STD_IRQ_LAST + 76) +#define PPC_IRQ_CPM_RES_D (PPC_STD_IRQ_LAST + 77) +#define PPC_IRQ_CPM_RES_E (PPC_STD_IRQ_LAST + 78) +#define PPC_IRQ_CPM_RES_F (PPC_STD_IRQ_LAST + 79) +#define PPC_IRQ_CPM_RES_G (PPC_STD_IRQ_LAST + 80) +#define PPC_IRQ_CPM_RES_H (PPC_STD_IRQ_LAST + 81) +#define PPC_IRQ_CPM_FCC1 (PPC_STD_IRQ_LAST + 82) +#define PPC_IRQ_CPM_FCC2 (PPC_STD_IRQ_LAST + 83) +#define PPC_IRQ_CPM_FCC3 (PPC_STD_IRQ_LAST + 84) +#define PPC_IRQ_CPM_RES_I (PPC_STD_IRQ_LAST + 85) +#define PPC_IRQ_CPM_MCC1 (PPC_STD_IRQ_LAST + 86) +#define PPC_IRQ_CPM_MCC2 (PPC_STD_IRQ_LAST + 87) +#define PPC_IRQ_CPM_RES_J (PPC_STD_IRQ_LAST + 88) +#define PPC_IRQ_CPM_RES_K (PPC_STD_IRQ_LAST + 89) +#define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 90) +#define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 91) +#define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 92) +#define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 93) +#define PPC_IRQ_CPM_RES_L (PPC_STD_IRQ_LAST + 94) +#define PPC_IRQ_CPM_RES_M (PPC_STD_IRQ_LAST + 95) +#define PPC_IRQ_CPM_RES_N (PPC_STD_IRQ_LAST + 96) +#define PPC_IRQ_CPM_RES_O (PPC_STD_IRQ_LAST + 97) +#define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 98) +#define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 99) +#define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 100) +#define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 101) +#define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 102) +#define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 103) +#define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 104) +#define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 105) +#define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 106) +#define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 107) +#define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 108) +#define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 109) +#define PPC_IRQ_CPM_PC3 (PPC_STD_IRQ_LAST + 110) +#define PPC_IRQ_CPM_PC2 (PPC_STD_IRQ_LAST + 111) +#define PPC_IRQ_CPM_PC1 (PPC_STD_IRQ_LAST + 112) +#define PPC_IRQ_CPM_PC0 (PPC_STD_IRQ_LAST + 113) + +#define PPC_IRQ_LAST PPC_IRQ_CPM_PC0 + +#endif + + +/* + * If the maximum number of exception sources is too low, + * then fix it + */ + +#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST +#undef PPC_INTERRUPT_MAX +#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1) +#endif + +/* + * Machine Status Register (MSR) Constants Used by RTEMS + */ + +#if PPC_HAS_RI +#define PPC_MSR_RI 0x000000002 /* bit 30 - recoverable exception */ +#endif + +#define PPC_MSR_DR 0x000000010 /* bit 27 - data address translation */ +#define PPC_MSR_IR 0x000000020 /* bit 26 - instruction addr translation*/ + +/* + * Some PPC model manuals refer to the Exception Prefix (EP) bit as + * IP for no apparent reason. + */ +#if (PPC_HAS_EXCEPTION_PREFIX) +#define PPC_MSR_EP 0x000000040 /* bit 25 - exception prefix */ +#else +#define PPC_MSR_EP 0x000000000 /* bit 25 - exception prefix */ +#endif + +#if (PPC_HAS_FPU) +#define PPC_MSR_FP 0x000002000 /* bit 18 - floating point enable */ +#else +#define PPC_MSR_FP 0x000000000 /* bit 18 - floating point enable */ +#endif + +#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE) +#define PPC_MSR_POW 0x000000000 /* bit 13 - power management enable */ +#else +#define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */ +#endif + +#define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */ +#define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */ + +#if (PPC_HAS_RFCI) +#define PPC_MSR_CE 0x000020000 /* bit 14 - critical interrupt enable */ +#else +#define PPC_MSR_CE 0x000000000 /* bit 14 - critical interrupt enable */ +#endif + +#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE) + +#if defined(__powerpc64__) +#define PPC_MINIMUM_STACK_FRAME_SIZE 32 +#else +#define PPC_MINIMUM_STACK_FRAME_SIZE PPC_STACK_ALIGNMENT +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_POWERPC_POWERPC_H */ diff --git a/bsps/powerpc/include/tty_drv.h b/bsps/powerpc/include/tty_drv.h new file mode 100644 index 0000000000..d2024c89d7 --- /dev/null +++ b/bsps/powerpc/include/tty_drv.h @@ -0,0 +1,63 @@ +#ifdef ppc405 +#ifndef __tty_drv__ +#define __tty_drv__ + +/* functions */ +#ifdef __cplusplus +extern "C" { +#endif + + +/* ttyS1 entry points */ +rtems_device_driver tty0_initialize( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver tty0_open( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver tty0_control( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + + +/* tty1 & tty2 shared entry points */ +rtems_device_driver tty0_close( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + + +rtems_device_driver tty0_read( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver tty0_write( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + + +#define TTY0_DRIVER_TABLE_ENTRY \ + { tty0_initialize, tty0_open, tty0_close, \ + tty0_read, tty0_write, tty0_control } + + +#ifdef __cplusplus +} +#endif +/* end of include file */ + +#endif /* __tty_drv__ */ +#endif /* ppc405 */ diff --git a/bsps/powerpc/motorola_powerpc/headers.am b/bsps/powerpc/motorola_powerpc/headers.am new file mode 100644 index 0000000000..b577b15c5b --- /dev/null +++ b/bsps/powerpc/motorola_powerpc/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/motorola_powerpc/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/motorola_powerpc/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/motorola_powerpc/include/bsp/irq.h diff --git a/bsps/powerpc/motorola_powerpc/include/bsp.h b/bsps/powerpc/motorola_powerpc/include/bsp.h new file mode 100644 index 0000000000..675796becf --- /dev/null +++ b/bsps/powerpc/motorola_powerpc/include/bsp.h @@ -0,0 +1,248 @@ +/* + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H +#define LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H + +#include +#include + +#include +#include +#include + +#ifdef qemu +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * diagram illustrating the role of the configuration + * constants + * PCI_MEM_WIN0: CPU starting addr where PCI memory space is visible + * PCI_MEM_BASE: CPU address of PCI mem addr. zero. (regardless of this + * address being 'visible' or not!). + * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME + * _VME_A32_WIN0_ON_VME: VME address of that same window + * + * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between + * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI + * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to + * the base address read from PCI config.space in order to translate that + * into a CPU address. + * + * NOTE: VME addresses should NEVER be translated using these constants! + * they are strictly for BSP internal use. Drivers etc. should use + * the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs). + * + * CPU ADDR PCI_ADDR VME ADDR + * + * 00000000 XXXXXXXX XXXXXXXX + * ^ ^ ........ + * | | + * | | e.g., RAM XXXXXXXX + * | | 00000000 + * | | ......... ^ + * | | (possible offset | + * | | between pci and XXXXXXXX | ...... + * | | cpu addresses) | + * | v | + * | PCI_MEM_BASE -------------> 00000000 --------------- | + * | ........ ........ ^ | + * | invisible | | + * | ........ from CPU | | + * v | | + * PCI_MEM_WIN0 ============= first visible PCI addr | | + * | | + * pci devices pci window | | + * visible here v v + * mapped by ========== _VME_A32_WIN0_ON_PCI ======= _VME_A32_WIN0_ON_VME + * vme window + * VME devices hostbridge mapped by + * visible here universe + * ===================================================== + * + */ + +/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */ +#if defined(mvme2100) +#define _IO_BASE CHRP_ISA_IO_BASE +#define _ISA_MEM_BASE CHRP_ISA_MEM_BASE +/* address of our ram on the PCI bus */ +#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET +/* offset of pci memory as seen from the CPU */ +#define PCI_MEM_BASE 0 +/* where (in CPU addr. space) does the PCI window start */ +#define PCI_MEM_WIN0 0x80000000 + +#else +#define _IO_BASE PREP_ISA_IO_BASE +#define _ISA_MEM_BASE PREP_ISA_MEM_BASE +#ifndef qemu +/* address of our ram on the PCI bus */ +#define PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET +/* offset of pci memory as seen from the CPU */ +#define PCI_MEM_BASE PREP_ISA_MEM_BASE +#define PCI_MEM_WIN0 0 +#else +#define PCI_DRAM_OFFSET 0 +#define PCI_MEM_BASE 0 +#define PCI_MEM_WIN0 PREP_ISA_MEM_BASE +#endif +#endif + + +/* + * Base address definitions for several devices + * + * MVME2100 is very similar but has fewer devices and uses on-CPU EPIC + * implementation of OpenPIC controller. It also cannot be probed to + * find out what it is which is VERY different from other Motorola boards. + */ + +#if defined(mvme2100) +#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e10000) +/* #define BSP_UART_IOBASE_COM1 (0xffe10000) */ +#define BSP_OPEN_PIC_BASE_OFFSET 0x40000 + +#define MVME_HAS_DEC21140 +#else +#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8) +#define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8) + +#if ! defined(qemu) +#define BSP_KBD_IOBASE ((_IO_BASE)+0x60) +#define BSP_VGA_IOBASE ((_IO_BASE)+0x3c0) +#endif + +#if defined(mvme2300) +#define MVME_HAS_DEC21140 +#endif +#endif + +#define BSP_CONSOLE_PORT BSP_UART_COM1 +#define BSP_UART_BAUD_BASE 115200 + +#if defined(MVME_HAS_DEC21140) +struct rtems_bsdnet_ifconfig; +#define RTEMS_BSP_NETWORK_DRIVER_NAME "dc1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_dec21140_driver_attach +extern int rtems_dec21140_driver_attach(); +#endif + +#ifdef qemu +#define RTEMS_BSP_NETWORK_DRIVER_NAME "ne1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_ne_driver_attach +extern int rtems_ne_driver_attach(); +#endif + +#ifdef qemu +#define BSP_IDLE_TASK_BODY bsp_ppc_idle_task_body +extern void *bsp_ppc_idle_task_body(uintptr_t arg); +#endif + +#include +/* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver + * to implement VME IRQ priorities in software. + * Note that this requires support by the interrupt controller + * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c) + * and the BSP-specific universe initialization/configuration + * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c) + * + * ********* IMPORTANT NOTE ******** + * When deriving from this file (new BSPs) + * DO NOT define "BSP_PIC_DO_EOI" if you don't know what + * you are doing i.e., w/o implementing the required pieces + * mentioned above. + * ********* IMPORTANT NOTE ******** + */ +#define BSP_PIC_DO_EOI openpic_eoi(0) + +#ifndef ASM +#define outport_byte(port,value) outb(value,port) +#define outport_word(port,value) outw(value,port) +#define outport_long(port,value) outl(value,port) + +#define inport_byte(port,value) (value = inb(port)) +#define inport_word(port,value) (value = inw(port)) +#define inport_long(port,value) (value = inl(port)) + +/* + * Vital Board data Start using DATA RESIDUAL + */ + +/* + * Total memory using RESIDUAL DATA + */ +extern unsigned int BSP_mem_size; +/* + * Start of the heap + */ +extern unsigned int BSP_heap_start; +/* + * PCI Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * processor clock frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; + +/* + * String passed by the bootloader. + */ +extern char *BSP_commandline_string; + +#define BSP_Convert_decrementer( _value ) \ + ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) + +/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ +extern int BSP_disconnect_clock_handler (void); +extern int BSP_connect_clock_handler (void); + +/* clear hostbridge errors + * + * NOTE: The routine returns always (-1) if 'enableMCP==1' + * [semantics needed by libbspExt] if the MCP input is not wired. + * It returns and clears the error bits of the PCI status register. + * MCP support is disabled because: + * a) the 2100 has no raven chip + * b) the raven (2300) would raise machine check interrupts + * on PCI config space access to empty slots. + */ +extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); + +/* + * Prototypes for methods called only from .S for dependency tracking + */ +char *save_boot_params( + void *r3, + void *r4, + void *r5, + char *cmdline_start, + char *cmdline_end +); +void zero_bss(void); + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void VIA_isa_bridge_interrupts_setup(void); + +#endif + +#ifdef __cplusplus +}; +#endif + +#endif diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h b/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h new file mode 100644 index 0000000000..9b355819f1 --- /dev/null +++ b/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h @@ -0,0 +1,233 @@ +#ifndef RTEMS_BSP_VME_CONFIG_H +#define RTEMS_BSP_VME_CONFIG_H + +/* BSP specific address space configuration parameters */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2002, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +/* + * The BSP maps VME address ranges into + * one BAT. + * NOTE: the BSP (startup/bspstart.c) uses + * hardcoded window lengths that match this + * layout: + * + * BSP_VME_BAT_IDX defines + * which BAT to use for mapping the VME bus. + * If this is undefined, no extra BAT will be + * configured and VME has to share the available + * PCI address space with PCI devices. + * + * If you do define BSP_VME_BAT_IDX you must + * make sure the corresponding BAT is really + * available and unused! + */ + +#if defined(mvme2100) +#define _VME_A32_WIN0_ON_PCI 0x90000000 +#define _VME_A24_ON_PCI 0x9f000000 +#define _VME_A16_ON_PCI 0x9fff0000 +#define BSP_VME_BAT_IDX 1 +#else +#define _VME_A32_WIN0_ON_PCI 0x10000000 +#define _VME_A24_ON_PCI 0x1f000000 +#define _VME_A16_ON_PCI 0x1fff0000 +#define BSP_VME_BAT_IDX 0 +#endif + +/* start of the A32 window on the VME bus + * TODO: this should perhaps be a run-time configuration option + */ +#define _VME_A32_WIN0_ON_VME 0x20000000 + +/* if _VME_DRAM_OFFSET is defined, the BSP + * will map the board RAM onto the VME bus, starting + * at _VME_DRAM_OFFSET + */ +#define _VME_DRAM_OFFSET 0xc0000000 + +/* Define BSP_PCI_VME_DRIVER_DOES_EOI to let the vmeUniverse + * driver (Tsi148 driver doesn't implement this) implement + * VME IRQ priorities in software. + * + * Here's how this works: + * + * 1) VME IRQ happens + * 2) universe propagates IRQ to PCI/PPC/main interrupt + * controller ('PIC' - programmable interrupt controller). + * 3) PIC driver dispatches universe driver's ISR + * 4) universe driver ISR acknowledges IRQ on VME, + * determines VME vector. + * ++++++++++++ stuff between ++ signs is related to SW priorities +++++++++ + * 5) universe driver *masks* all VME IRQ levels <= interrupting + * level. + * 6) universe driver calls PIC driver's 'EOI' routine. + * This effectively re-enables PCI and hence higher + * level VME interrupts. + * 7) universe driver dispatches user VME ISR. + * + * ++>> HIGHER PRIORITY VME IRQ COULD HAPPEN HERE and would be handled <<++ + * + * 8) user ISR returns, universe driver re-enables lower + * level VME interrupts, returns. + * 9) universe driver ISR returns control to PIC driver + * 10) PIC driver *omits* regular EOI sequence since this + * was already done by universe driver (step 6). + * ++++++++++++ end of special handling (SW priorities) ++++++++++++++++++++ + * 11) PIC driver ISR dispatcher returns. + * + * Note that the BSP *MUST* provide the following hooks + * in order for this to work: + * a) bsp.h must define the symbol BSP_PIC_DO_EOI to + * a sequence of instructions that terminates an + * interrupt at the interrupt controller. + * b) The interrupt controller driver must check the + * interrupt source and *must omit* running the EOI + * sequence if the interrupt source is the vmeUniverse + * (because the universe driver already ran BSP_PIC_DO_EOI) + * The interrupt controller must define the variable + * + * int _BSP_vme_bridge_irq = -1; + * + * which is assigned the universe's interrupt line information + * by vme_universe.c:BSP_VMEIrqMgrInstall(). The interrupt + * controller driver may use this variable to determine + * if an IRQ was caused by the universe. + * + * c) define BSP_PCI_VME_DRIVER_DOES_EOI + * + * NOTE: If a) and b) are not implemented by the BSP + * BSP_PCI_VME_DRIVER_DOES_EOI must be *undefined*. + */ +#define BSP_PCI_VME_DRIVER_DOES_EOI + +#ifdef BSP_PCI_VME_DRIVER_DOES_EOI +/* don't reference vmeUniverse0PciIrqLine directly from the irq + * controller driver - leave it up to BSP_VMEIrqMgrInstall() to + * set _BSP_vme_bridge_irq. That way, we can avoid linking + * the universe driver if VME is unused... + */ +extern int _BSP_vme_bridge_irq; +#endif + +/* If your BSP requires a non-standard way to configure + * the VME interrupt manager then define the symbol + * + * BSP_VME_UNIVERSE_INSTALL_IRQ_MGR + * + * to a proper instruction sequence that installs the + * universe interrupt manager. This requires knowledge + * of the wiring between the universe and the PIC (main + * interrupt controller), i.e., which IRQ 'pins' of the + * universe are wired to which 'lines'/inputs at the PIC. + * (consult vmeUniverse.h for more information). + * + * When installing the universe IRQ manager it is also + * possible to specify whether it should try to share + * PIC interrupts with other sources. This might not + * be supported by all BSPs (but the unverse driver + * recognizes that). + * + * If BSP_VME_UNIVERSE_INSTALL_IRQ_MGR is undefined then + * the default algorithm is used (vme_universe.c): + * + * This default setup uses only a single wire. It reads + * the PIC 'line' from PCI configuration space and assumes + * this to be wired to the first (LIRQ0) IRQ input at the + * universe. The default setup tries to use interrupt + * sharing. + */ + +#include +#include + +#define BSP_VME_UNIVERSE_INSTALL_IRQ_MGR(err) \ +do { \ +int bus, dev, i = 0, j; \ +const struct _int_map *bspmap; \ + /* install the VME interrupt manager; \ + * if there's a bsp route map, use it to \ + * configure additional lines... \ + */ \ + err = -1; \ + if (0 == pci_find_device(0x10e3, 0x0000, 0, &bus, &dev, &i)){ \ + if ( (bspmap = motorolaIntMap(currentBoard)) ) { \ + for ( i=0; bspmap[i].bus >= 0; i++ ) { \ + if ( bspmap[i].bus == bus && bspmap[i].slot == dev ) { \ + int pins[5], names[4]; \ + /* found it; use info here... */ \ + /* copy up to 4 entries; terminated with -1 pin */ \ + for ( j=0; \ + j<5 && (pins[j]=bspmap[i].pin_route[j].pin-1)>=0; \ + j++) { \ + names[j] = bspmap[i].pin_route[j].int_name[0]; \ + } \ + pins[4] = -1; \ + if ( 0 == vmeUniverseInstallIrqMgrAlt( \ + VMEUNIVERSE_IRQ_MGR_FLAG_SHARED, /* shared IRQs */\ + pins[0], names[0], \ + pins[1], names[1], \ + pins[2], names[2], \ + pins[3], names[3], \ + -1) ) { \ + i = -1; \ + break; \ + } \ + } \ + } \ + } \ + if ( i >= 0 ) \ + err = vmeUniverseInstallIrqMgrAlt( \ + VMEUNIVERSE_IRQ_MGR_FLAG_SHARED, \ + 0,-1, \ + -1); \ + } \ +} while (0) + +extern int BSP_VMEInit(void); +extern int BSP_VMEIrqMgrInstall(void); + +#endif diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h new file mode 100644 index 0000000000..2d575d8122 --- /dev/null +++ b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h @@ -0,0 +1,204 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by RTEMS to write interrupt handlers. + * + * Copyright (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef BSP_POWERPC_IRQ_H +#define BSP_POWERPC_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 +#include + +/* + * 8259 edge/level control definitions at VIA + */ +#define ISA8259_M_ELCR 0x4d0 +#define ISA8259_S_ELCR 0x4d1 + +#define ELCRS_INT15_LVL 0x80 +#define ELCRS_INT14_LVL 0x40 +#define ELCRS_INT13_LVL 0x20 +#define ELCRS_INT12_LVL 0x10 +#define ELCRS_INT11_LVL 0x08 +#define ELCRS_INT10_LVL 0x04 +#define ELCRS_INT9_LVL 0x02 +#define ELCRS_INT8_LVL 0x01 +#define ELCRM_INT7_LVL 0x80 +#define ELCRM_INT6_LVL 0x40 +#define ELCRM_INT5_LVL 0x20 +#define ELCRM_INT4_LVL 0x10 +#define ELCRM_INT3_LVL 0x8 +#define ELCRM_INT2_LVL 0x4 +#define ELCRM_INT1_LVL 0x2 +#define ELCRM_INT0_LVL 0x1 + + /* PIC's command and mask registers */ +#define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */ +#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 /* Slave PIC command register */ +#define PIC_MASTER_IMR_IO_PORT 0x21 /* Master PIC Interrupt Mask Register */ +#define PIC_SLAVE_IMR_IO_PORT 0xa1 /* Slave PIC Interrupt Mask Register */ + + /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */ +#define PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */ +#define SLAVE_PIC_EOSI 0x62 /* End of Specific Interrupt (EOSI) for cascade */ +#define PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */ + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * rtems_irq_number Definitions + */ + +/* + * ISA IRQ handler related definitions + */ +#define BSP_ISA_IRQ_NUMBER (16) +#define BSP_ISA_IRQ_LOWEST_OFFSET (0) +#define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1) +/* + * PCI IRQ handlers related definitions + * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE + */ +#ifndef qemu +#define BSP_PCI_IRQ_NUMBER (16) +#else +#define BSP_PCI_IRQ_NUMBER (0) +#endif +#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER) +#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) +/* + * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt + * handler might be connected + */ +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) +/* Misc vectors for OPENPIC irqs (IPI, timers) + */ +#ifndef qemu +#define BSP_MISC_IRQ_NUMBER (8) +#else +#define BSP_MISC_IRQ_NUMBER (0) +#endif + +#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) +#define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) +/* + * Some ISA IRQ symbolic name definition + */ +#define BSP_ISA_PERIODIC_TIMER (0) +#define BSP_ISA_KEYBOARD (1) +#define BSP_ISA_UART_COM2_IRQ (3) +#define BSP_ISA_UART_COM1_IRQ (4) +#define BSP_ISA_RT_TIMER1 (8) +#define BSP_ISA_RT_TIMER3 (10) +/* + * Some PCI IRQ symbolic name definition + */ +#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET) +#if BSP_PCI_IRQ_NUMBER > 0 +#define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0) +#endif + +#if defined(mvme2100) +#define BSP_DEC21143_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1) +#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2) +#define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3) +#define BSP_PCMIP_TYPE2_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 4) +#define BSP_PCMIP_TYPE2_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 5) +#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7) +#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8) +#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9) +#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10) +#define BSP_UART_COM1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 13) +#define BSP_FRONT_PANEL_ABORT_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 14) +#define BSP_RTC_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 15) +#else +#define BSP_UART_COM1_IRQ BSP_ISA_UART_COM1_IRQ +#define BSP_UART_COM2_IRQ BSP_ISA_UART_COM2_IRQ +#endif + +/* + * Some Processor execption handled as RTEMS IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) + + +/* + * Type definition for RTEMS managed interrupts + */ +typedef unsigned short rtems_i8259_masks; + +extern volatile rtems_i8259_masks i8259s_cache; + +/*-------------------------------------------------------------------------+ +| Function Prototypes. ++--------------------------------------------------------------------------*/ +/* + * ------------------------ Intel 8259 (or emulation) Mngt Routines ------- + */ +void BSP_i8259s_init(void); + +/* + * function to disable a particular irq at 8259 level. After calling + * this function, even if the device asserts the interrupt line it will + * not be propagated further to the processor + * + * RETURNS: 1/0 if the interrupt was enabled/disabled originally or + * a value < 0 on error. + */ +int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine); +/* + * function to enable a particular irq at 8259 level. After calling + * this function, if the device asserts the interrupt line it will + * be propagated further to the processor + */ +int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine); +/* + * function to acknowledge a particular irq at 8259 level. After calling + * this function, if a device asserts an enabled interrupt line it will + * be propagated further to the processor. Mainly usefull for people + * writing raw handlers as this is automagically done for RTEMS managed + * handlers. + */ +int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine); +/* + * function to check if a particular irq is enabled at 8259 level. After calling + */ +int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine); + +extern void BSP_rtems_irq_mng_init(unsigned cpuId); +extern void BSP_i8259s_init(void); + +/* Stuff in irq_supp.h should eventually go into */ +#include + +#ifdef __cplusplus +}; +#endif + +#endif +#endif diff --git a/bsps/powerpc/motorola_powerpc/include/tm27.h b/bsps/powerpc/motorola_powerpc/include/tm27.h new file mode 100644 index 0000000000..81eb55a54a --- /dev/null +++ b/bsps/powerpc/motorola_powerpc/include/tm27.h @@ -0,0 +1,64 @@ +/* + * @file + * @ingroup powerpc_motorola_powerpc + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + */ + +#include + +#define MUST_WAIT_FOR_INTERRUPT 1 + +void nullFunc() {} +static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, + 0, + (rtems_irq_enable)nullFunc, + (rtems_irq_disable)nullFunc, + (rtems_irq_is_enabled) nullFunc}; +void Install_tm27_vector(void (*_handler)()) +{ + clockIrqData.hdl = _handler; + if (!BSP_install_rtems_irq_handler (&clockIrqData)) { + printk("Error installing clock interrupt handler!\n"); + rtems_fatal_error_occurred(1); + } +} + +#define Cause_tm27_intr() \ + do { \ + uint32_t _clicks = 8; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Clear_tm27_intr() \ + do { \ + uint32_t _clicks = 0xffffffff; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Lower_tm27_intr() \ + do { \ + uint32_t _msr = 0; \ + _ISR_Set_level( 0 ); \ + __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + _msr |= 0x8002; \ + __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + } while (0) + +#endif diff --git a/bsps/powerpc/mpc55xxevb/headers.am b/bsps/powerpc/mpc55xxevb/headers.am new file mode 100644 index 0000000000..6dffbe060c --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/headers.am @@ -0,0 +1,15 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h diff --git a/bsps/powerpc/mpc55xxevb/include/bsp.h b/bsps/powerpc/mpc55xxevb/include/bsp.h new file mode 100644 index 0000000000..eee5d208c1 --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp.h @@ -0,0 +1,104 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Global BSP variables and functions + */ + +/* + * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_MPC55XXEVB_BSP_H +#define LIBBSP_POWERPC_MPC55XXEVB_BSP_H + +#include + +#define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN + +#define BSP_FEATURE_IRQ_EXTENSION + +#define MPC55XX_PERIPHERAL_CLOCK \ + (MPC55XX_SYSTEM_CLOCK / MPC55XX_SYSTEM_CLOCK_DIVIDER) + +#ifndef ASM + +#include + +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @brief System clock frequency */ +extern unsigned int bsp_clock_speed; + +/** @brief Time base clicks per micro second */ +extern uint32_t bsp_clicks_per_usec; + +/** @brief Convert Decrementer ticks to microseconds */ +#define BSP_Convert_decrementer( _value ) \ + (((unsigned long long) (_value)) / ((unsigned long long)bsp_clicks_per_usec)) + +rtems_status_code mpc55xx_sd_card_init( bool mount); + +/* Network driver configuration */ + +struct rtems_bsdnet_ifconfig; + +int smsc9218i_attach_detach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH smsc9218i_attach_detach + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" + +rtems_status_code bsp_register_i2c(void); + +void bsp_restart(void *addr); + +void *bsp_idle_thread(uintptr_t arg); + +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +LINKER_SYMBOL(bsp_section_dsram_begin) +LINKER_SYMBOL(bsp_section_dsram_end) +LINKER_SYMBOL(bsp_section_dsram_size) +LINKER_SYMBOL(bsp_section_dsram_load_begin) +LINKER_SYMBOL(bsp_section_dsram_load_end) + +#define BSP_DSRAM_SECTION __attribute__((section(".bsp_dsram"))) + +LINKER_SYMBOL(bsp_section_sysram_begin) +LINKER_SYMBOL(bsp_section_sysram_end) +LINKER_SYMBOL(bsp_section_sysram_size) +LINKER_SYMBOL(bsp_section_sysram_load_begin) +LINKER_SYMBOL(bsp_section_sysram_load_end) + +#define BSP_SYSRAM_SECTION __attribute__((section(".bsp_sysram"))) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_POWERPC_MPC55XXEVB_BSP_H */ diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h b/bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h new file mode 100644 index 0000000000..4be6788141 --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h @@ -0,0 +1,57 @@ +/** + * @file + * + * @brief Console ESCI API. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_ESCI_H +#define LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_ESCI_H + +#include "console-generic.h" + +#undef CR0 +#undef CR1 +#undef CR2 +#undef CR3 + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef MPC55XX_HAS_ESCI + +extern const console_generic_callbacks mpc55xx_esci_callbacks; + +typedef struct { + volatile struct ESCI_tag *regs; + struct rtems_termios_tty *tty; + int transmit_nest_level; + bool transmit_in_progress; + rtems_vector_number irq; +} mpc55xx_esci_context; + +extern mpc55xx_esci_context mpc55xx_esci_devices []; + +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_ESCI_H */ diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h b/bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h new file mode 100644 index 0000000000..c3f7a4628f --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h @@ -0,0 +1,81 @@ +/** + * @file + * + * @brief Generic console driver API. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_CONSOLE_GENERIC_H +#define LIBBSP_SHARED_CONSOLE_GENERIC_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + rtems_termios_callbacks termios_callbacks; + int (*poll_read)(int minor); + void (*poll_write)(int minor, char c); +} console_generic_callbacks; + +typedef struct { + void *context; + const console_generic_callbacks *callbacks; + const char *device_path; +} console_generic_info; + +extern const console_generic_info console_generic_info_table []; + +extern const size_t console_generic_info_count; + +extern const rtems_device_minor_number console_generic_minor; + +#define CONSOLE_GENERIC_INFO_TABLE \ + const console_generic_info console_generic_info_table [] + +#define CONSOLE_GENERIC_INFO(context, callbacks, device_path) \ + { context, callbacks, device_path } + +#define CONSOLE_GENERIC_INFO_COUNT \ + const size_t console_generic_info_count = \ + sizeof(console_generic_info_table) / sizeof(console_generic_info_table [0]) + +#define CONSOLE_GENERIC_MINOR(minor) \ + const rtems_device_minor_number console_generic_minor = (minor) + +static inline void *console_generic_get_context(int minor) +{ + return console_generic_info_table [minor].context; +} + +static inline struct rtems_termios_tty *console_generic_get_tty_at_open( + void *arg +) +{ + const rtems_libio_open_close_args_t *oc = + (const rtems_libio_open_close_args_t *) arg; + + return (struct rtems_termios_tty *) oc->iop->data1; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_CONSOLE_GENERIC_H */ diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h b/bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h new file mode 100644 index 0000000000..c70f36d13b --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h @@ -0,0 +1,64 @@ +/** + * @file + * + * @brief Console LINFlexD API. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_LINFLEX_H +#define LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_LINFLEX_H + +#include "console-generic.h" + +#undef CR0 +#undef CR1 +#undef CR2 +#undef CR3 + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef MPC55XX_HAS_LINFLEX + +extern const console_generic_callbacks mpc55xx_linflex_callbacks; + +typedef struct { + volatile LINFLEX_tag *regs; + struct rtems_termios_tty *tty; + rtems_vector_number irq_rxi; + rtems_vector_number irq_txi; + rtems_vector_number irq_err; + volatile SIU_PCR_tag *tx_pcr_register; + uint8_t tx_pa_value:2; + volatile SIU_PCR_tag *rx_pcr_register; + volatile SIUL_PSMI_8B_tag *rx_psmi_register; + uint8_t rx_padsel_value:4; + int transmit_nest_level; + bool transmit_in_progress; +} mpc55xx_linflex_context; + +extern mpc55xx_linflex_context mpc55xx_linflex_devices []; + +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_LINFLEX_H */ diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/irq.h b/bsps/powerpc/mpc55xxevb/include/bsp/irq.h new file mode 100644 index 0000000000..4efa92219e --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp/irq.h @@ -0,0 +1,499 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief IRQ + */ + +/* + * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_IRQ_H +#define LIBBSP_POWERPC_IRQ_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * Interrupt numbers + */ + +#define MPC55XX_IRQ_INVALID 0x10000U +#define MPC55XX_IRQ_MIN 0U + +/* Software interrupts */ +#define MPC55XX_IRQ_SOFTWARE_MIN 0U +#define MPC55XX_IRQ_SOFTWARE_MAX 7U +#define MPC55XX_IRQ_SOFTWARE_GET_INDEX(v) (v) +#define MPC55XX_IRQ_SOFTWARE_GET_REQUEST(i) (i) +#define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U) + +#if MPC55XX_CHIP_FAMILY == 551 + #define MPC55XX_IRQ_MAX 293U + + /* eDMA */ + #define MPC55XX_IRQ_EDMA_ERROR(group) \ + ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID) + #define MPC55XX_IRQ_EDMA(ch) \ + ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID) + + /* I2C */ + #define MPC55XX_IRQ_I2C(mod) \ + ((mod) == 0 ? 48U : MPC55XX_IRQ_INVALID) + + /* SIU external interrupts */ + #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U + #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U + #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U + #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U + #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U + + /* PIT */ + #define MPC55XX_IRQ_RTI 148U + #define MPC55XX_IRQ_PIT(timer) (148U + (timer)) + + /* eTPU */ + #define MPC55XX_IRQ_ETPU_BASE(mod) MPC55XX_IRQ_INVALID + + /* DSPI */ + #define MPC55XX_IRQ_DSPI_BASE(mod) \ + ((mod) == 0 ? 117U : \ + ((mod) == 1 ? 122U : \ + ((mod) == 2 ? 274U : \ + ((mod) == 3 ? 279U : MPC55XX_IRQ_INVALID)))) + + /* eMIOS */ + #define MPC55XX_IRQ_EMIOS(ch) \ + ((unsigned) (ch) < 24U ? 58U + (ch) : MPC55XX_IRQ_INVALID) + + /* eQADC */ + #define MPC55XX_IRQ_EQADC_BASE(mod) \ + ((mod) == 0 ? 82U : MPC55XX_IRQ_INVALID) + + /* eSCI */ + #define MPC55XX_IRQ_ESCI(mod) \ + ((mod) == 0 ? 113U : \ + ((mod) == 1 ? 114U : \ + ((mod) == 2 ? 115U : \ + ((mod) == 3 ? 116U : \ + ((mod) == 4 ? 270U : \ + ((mod) == 5 ? 271U : \ + ((mod) == 6 ? 272U : \ + ((mod) == 7 ? 273U : MPC55XX_IRQ_INVALID)))))))) + + /* FlexCAN */ + #define MPC55XX_IRQ_CAN_BASE(mod) \ + ((mod) == 0 ? 127U : \ + ((mod) == 1 ? 157U : \ + ((mod) == 2 ? 178U : \ + ((mod) == 3 ? 199U : \ + ((mod) == 4 ? 220U : \ + ((mod) == 5 ? 241U : MPC55XX_IRQ_INVALID)))))) + + /* FlexRay */ + #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \ + ((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID) +#elif MPC55XX_CHIP_FAMILY == 564 + #define MPC55XX_IRQ_MAX 255U + + /* eDMA */ + #define MPC55XX_IRQ_EDMA_ERROR(group) \ + ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID) + #define MPC55XX_IRQ_EDMA(ch) \ + ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID) + + /* SWT */ + #define MPC55XX_IRQ_SWT_0 28U + #define MPC55XX_IRQ_SWT_1 29U + + /* STM */ + #define MPC55XX_IRQ_STM_CHANNEL(ch) ((ch) + 30U) + + /* ECSM */ + #define MPC55XX_IRQ_ECSM_FAS 9U + #define MPC55XX_IRQ_ECSM_NCE 35U + #define MPC55XX_IRQ_ECSM_COR 36U + + /* MC */ + #define MPC55XX_IRQ_MC_ME_SAFE_MODE 51U + #define MPC55XX_IRQ_MC_ME_MODE_TRANSITION 52U + #define MPC55XX_IRQ_MC_ME_INVALID_MODE 53U + #define MPC55XX_IRQ_MC_ME_INVALID_CONFIG 54U + #define MPC55XX_IRQ_MC_RGM_FRAE 56U + + /* XOSC */ + #define MPC55XX_IRQ_XOSC 57U + + /* PIT */ + #define MPC55XX_IRQ_PIT_CHANNEL(ch) \ + ((ch) == 3 ? 127U : ((ch) + 59U)) + + /* SIU external interrupts */ + #define MPC55XX_IRQ_SIU_EXTERNAL_0 41U + #define MPC55XX_IRQ_SIU_EXTERNAL_1 42U + #define MPC55XX_IRQ_SIU_EXTERNAL_2 43U + #define MPC55XX_IRQ_SIU_EXTERNAL_3 44U + + /* ADC */ + #define MPC55XX_IRQ_ADC_BASE(mod) \ + ((mod) == 0 ? 62U : \ + ((mod) == 1 ? 82U : MPC55XX_IRQ_INVALID)) + + /* DSPI */ + #define MPC55XX_IRQ_DSPI_BASE(mod) \ + ((mod) == 0 ? 74U : \ + ((mod) == 1 ? 94U : \ + ((mod) == 2 ? 114U : MPC55XX_IRQ_INVALID))) + + /* FlexCAN */ + #define MPC55XX_IRQ_CAN_BASE(mod) \ + ((mod) == 0 ? 65U : \ + ((mod) == 1 ? 85U : MPC55XX_IRQ_INVALID)) + + /* FlexPWM */ + #define MPC55XX_IRQ_FLEXPWM_BASE(mod) \ + ((mod) == 0 ? 179U : \ + ((mod) == 1 ? 233U : MPC55XX_IRQ_INVALID)) + + /* FlexRay */ + #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \ + ((mod) == 0 ? 131U : MPC55XX_IRQ_INVALID) + + /* LINFlexD */ + #define MPC55XX_IRQ_LINFLEX_BASE(mod) \ + ((mod) == 0 ? 79U : \ + ((mod) == 1 ? 99U : MPC55XX_IRQ_INVALID)) + + /* eTimer */ + #define MPC55XX_IRQ_ETIMER_BASE(mod) \ + ((mod) == 0 ? 157U : \ + ((mod) == 1 ? 168U : \ + ((mod) == 2 ? 222U : MPC55XX_IRQ_INVALID))) + + /* CTU */ + #define MPC55XX_IRQ_CTU_MRS 193U + #define MPC55XX_IRQ_CTU_T(idx) ((idx) + 194U) + #define MPC55XX_IRQ_CTU_FIFO(idx) ((idx) + 202U) + #define MPC55XX_IRQ_CTU_ADC 206U + #define MPC55XX_IRQ_CTU_ERR 207U + + /* SEMA */ + #define MPC55XX_IRQ_SEMA_0 247U + #define MPC55XX_IRQ_SEMA_1 248U + + /* FCCU */ + #define MPC55XX_IRQ_FCCU_ALRM 250U + #define MPC55XX_IRQ_FCCU_CFG_TO 251U + #define MPC55XX_IRQ_FCCU_SC_RCC0_F 252U + #define MPC55XX_IRQ_FCCU_SC_RCC1_F 253U + + /* PMU */ + #define MPC55XX_IRQ_PMU 254U + + /* SWG */ + #define MPC55XX_IRQ_SWG 255U +#elif MPC55XX_CHIP_FAMILY == 566 + #define MPC55XX_IRQ_MAX 315U + + /* eDMA */ + #define MPC55XX_IRQ_EDMA_ERROR(group) \ + ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID) + #define MPC55XX_IRQ_EDMA(ch) \ + ((unsigned) (ch) < 32U ? 11U + (ch) : MPC55XX_IRQ_INVALID) + + /* PIT */ + #define MPC55XX_IRQ_PIT_CHANNEL(ch) \ + ((unsigned) (ch) < 9U ? 148U + (ch) : MPC55XX_IRQ_INVALID) + + /* SIU external interrupts */ + #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U + #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U + #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U + #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U + + /* eMIOS */ + #define MPC55XX_IRQ_EMIOS(ch) \ + ((unsigned) (ch) < 24U ? 58U + (ch) : \ + ((unsigned) (ch) < 32U ? 262U + (ch) : MPC55XX_IRQ_INVALID)) + + /* eSCI */ + #define MPC55XX_IRQ_ESCI(mod) \ + ((unsigned) (mod) < 4U ? 113U + (mod) : \ + ((unsigned) (mod) < 8U ? 270U + (mod) : \ + ((unsigned) (mod) < 12U ? 306U + (mod) : MPC55XX_IRQ_INVALID))) +#else + #if MPC55XX_CHIP_FAMILY == 555 + #define MPC55XX_IRQ_MAX 307U + #elif MPC55XX_CHIP_FAMILY == 556 + #define MPC55XX_IRQ_MAX 360U + #elif MPC55XX_CHIP_FAMILY == 567 + #define MPC55XX_IRQ_MAX 479U + #else + #error "unsupported chip type" + #endif + + /* eDMA */ + #define MPC55XX_IRQ_EDMA_ERROR(group) \ + ((group) == 0 ? 10U : \ + ((group) == 1 ? 210U : \ + ((group) == 2 ? 425U : MPC55XX_IRQ_INVALID))) + #define MPC55XX_IRQ_EDMA(ch) \ + ((unsigned) (ch) < 32U ? 11U + (ch) : \ + ((unsigned) (ch) < 64U ? 179U + (ch) : \ + ((unsigned) (ch) < 96U ? 362U + (ch) : MPC55XX_IRQ_INVALID))) + + /* I2C */ + #define MPC55XX_IRQ_I2C(mod) MPC55XX_IRQ_INVALID + + /* SIU external interrupts */ + #define MPC55XX_IRQ_SIU_EXTERNAL_0 46U + #define MPC55XX_IRQ_SIU_EXTERNAL_1 47U + #define MPC55XX_IRQ_SIU_EXTERNAL_2 48U + #define MPC55XX_IRQ_SIU_EXTERNAL_3 49U + #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U + + /* PIT */ + #define MPC55XX_IRQ_RTI 305U + #define MPC55XX_IRQ_PIT(ch) (301U + (ch)) + + /* eTPU */ + #define MPC55XX_IRQ_ETPU_BASE(mod) \ + ((mod) == 0 ? 67U : \ + ((mod) == 1 ? 243U : MPC55XX_IRQ_INVALID)) + + /* DSPI */ + #define MPC55XX_IRQ_DSPI_BASE(mod) \ + ((mod) == 0 ? 275U : \ + ((mod) == 1 ? 131U : \ + ((mod) == 2 ? 136U : \ + ((mod) == 3 ? 141U : MPC55XX_IRQ_INVALID)))) + + /* eMIOS */ + #define MPC55XX_IRQ_EMIOS(ch) \ + ((unsigned) (ch) < 16U ? 51U + (ch) : \ + ((unsigned) (ch) < 24U ? 186U + (ch) : \ + ((unsigned) (ch) < 32U ? 435U + (ch) : MPC55XX_IRQ_INVALID))) + + /* eQADC */ + #define MPC55XX_IRQ_EQADC_BASE(mod) \ + ((mod) == 0 ? 100U : \ + ((mod) == 1 ? 394U : MPC55XX_IRQ_INVALID)) + + /* eSCI */ + #define MPC55XX_IRQ_ESCI(mod) \ + ((mod) == 0 ? 146U : \ + ((mod) == 1 ? 149U : \ + ((mod) == 2 ? 473U : MPC55XX_IRQ_INVALID))) + + /* FlexCAN */ + #define MPC55XX_IRQ_CAN_BASE(mod) \ + ((mod) == 0 ? 152U : \ + ((mod) == 1 ? 280U : \ + ((mod) == 2 ? 173U : \ + ((mod) == 3 ? 308U : \ + ((mod) == 4 ? 329U : MPC55XX_IRQ_INVALID))))) + + /* FlexRay */ + #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \ + ((mod) == 0 ? 350U : MPC55XX_IRQ_INVALID) +#endif + +#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U) + +/* ADC */ +#define MPC55XX_IRQ_ADC_EOC(mod) \ + (MPC55XX_IRQ_ADC_BASE(mod) + 0U) +#define MPC55XX_IRQ_ADC_ER(mod) \ + (MPC55XX_IRQ_ADC_BASE(mod) + 1U) +#define MPC55XX_IRQ_ADC_WD(mod) \ + (MPC55XX_IRQ_ADC_BASE(mod) + 2U) + +/* eTimer */ +#define MPC55XX_IRQ_ETIMER_TC(mod, ch) \ + (MPC55XX_IRQ_ETIMER_BASE(mod) + (ch)) +#define MPC55XX_IRQ_ETIMER_WTIF(mod) \ + (MPC55XX_IRQ_ETIMER_BASE(mod) + 8U) +#define MPC55XX_IRQ_ETIMER_RCF(mod) \ + (MPC55XX_IRQ_ETIMER_BASE(mod) + 10U) + +/* eTPU */ +#define MPC55XX_IRQ_ETPU(mod) \ + (MPC55XX_IRQ_ETPU_BASE(mod) + 0U) +#define MPC55XX_IRQ_ETPU_CHANNEL(mod, ch) \ + (MPC55XX_IRQ_ETPU_BASE(mod) + 1U + (ch)) + +/* DSPI */ +#define MPC55XX_IRQ_DSPI_TFUF_RFOF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 0U) +#define MPC55XX_IRQ_DSPI_EOQF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 1U) +#define MPC55XX_IRQ_DSPI_TFFF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 2U) +#define MPC55XX_IRQ_DSPI_TCF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 3U) +#define MPC55XX_IRQ_DSPI_RFDF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 4U) + +/* eQADC */ +#define MPC55XX_IRQ_EQADC_TORF_RFOF_CFUF(mod) \ + (MPC55XX_IRQ_EQADC_BASE(mod) + 0U) +#define MPC55XX_IRQ_EQADC_NCF(mod, fifo) \ + (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 0U) +#define MPC55XX_IRQ_EQADC_PF(mod, fifo) \ + (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 1U) +#define MPC55XX_IRQ_EQADC_EOQF(mod, fifo) \ + (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 2U) +#define MPC55XX_IRQ_EQADC_CFFF(mod, fifo) \ + (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 3U) +#define MPC55XX_IRQ_EQADC_RFDF(mod, fifo) \ + (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 4U) + +/* FlexCAN */ +#if MPC55XX_CHIP_FAMILY == 564 + #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U) + #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U) + #define MPC55XX_IRQ_CAN_BUF_0_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U) + #define MPC55XX_IRQ_CAN_BUF_4_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U) + #define MPC55XX_IRQ_CAN_BUF_8_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U) + #define MPC55XX_IRQ_CAN_BUF_12_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U) + #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U) +#else + #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U) + #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U) + #define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U) + #define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U) + #define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U) + #define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U) + #define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U) + #define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U) + #define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U) + #define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U) + #define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U) + #define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U) + #define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U) + #define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U) + #define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U) + #define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U) + #define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U) + #define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U) + #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U) + #define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U) +#endif + +/* FlexPWM */ +#define MPC55XX_IRQ_FLEXPWM_RF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 0U) +#define MPC55XX_IRQ_FLEXPWM_COF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 1U) +#define MPC55XX_IRQ_FLEXPWM_CAF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 2U) +#define MPC55XX_IRQ_FLEXPWM_FFLAG(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 12U) +#define MPC55XX_IRQ_FLEXPWM_REF(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 13U) + +/* FlexRay */ +#if MPC55XX_CHIP_FAMILY == 564 + #define MPC55XX_IRQ_FLEXRAY_LRNEIF_DRNEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U) + #define MPC55XX_IRQ_FLEXRAY_LRCEIF_DRCEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U) + #define MPC55XX_IRQ_FLEXRAY_FAFAIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U) + #define MPC55XX_IRQ_FLEXRAY_FAFVIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U) + #define MPC55XX_IRQ_FLEXRAY_WUPIEF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U) + #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U) + #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U) + #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U) + #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 8U) + #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 9U) +#else + #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U) + #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U) + #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U) + #define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U) + #define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U) + #define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U) + #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U) + #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U) +#endif + +/* LINFlexD */ +#define MPC55XX_IRQ_LINFLEX_RXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 0U) +#define MPC55XX_IRQ_LINFLEX_TXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 1U) +#define MPC55XX_IRQ_LINFLEX_ERR(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 2U) + +/* Checks */ +#define MPC55XX_IRQ_IS_VALID(v) \ + ((v) >= MPC55XX_IRQ_MIN && \ + (v) <= MPC55XX_IRQ_MAX) +#define MPC55XX_IRQ_IS_SOFTWARE(v) \ + ((v) >= MPC55XX_IRQ_SOFTWARE_MIN && \ + (v) <= MPC55XX_IRQ_SOFTWARE_MAX) + +/* + * Interrupt controller + */ + +#define MPC55XX_INTC_MIN_PRIORITY 1U +#define MPC55XX_INTC_MAX_PRIORITY 15U +#define MPC55XX_INTC_DISABLED_PRIORITY 0U +#define MPC55XX_INTC_INVALID_PRIORITY (MPC55XX_INTC_MAX_PRIORITY + 1) +#define MPC55XX_INTC_DEFAULT_PRIORITY (MPC55XX_INTC_MIN_PRIORITY + 1) +#define MPC55XX_INTC_IS_VALID_PRIORITY(p) \ + ((p) >= MPC55XX_INTC_DISABLED_PRIORITY && (p) <= MPC55XX_INTC_MAX_PRIORITY) + +rtems_status_code mpc55xx_interrupt_handler_install( + rtems_vector_number vector, + const char *info, + rtems_option options, + unsigned priority, + rtems_interrupt_handler handler, + void *arg +); + +rtems_status_code mpc55xx_intc_get_priority( + rtems_vector_number vector, + unsigned *priority +); + +rtems_status_code mpc55xx_intc_set_priority( + rtems_vector_number vector, + unsigned priority +); + +rtems_status_code mpc55xx_intc_raise_software_irq(rtems_vector_number vector); + +rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector); + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define BSP_INTERRUPT_VECTOR_MIN MPC55XX_IRQ_MIN + +#define BSP_INTERRUPT_VECTOR_MAX MPC55XX_IRQ_MAX + +#ifdef BSP_INTERRUPT_HANDLER_TABLE_SIZE + #define BSP_INTERRUPT_USE_INDEX_TABLE + #define BSP_INTERRUPT_NO_HEAP_USAGE +#endif + +/** @} */ + +/* Legacy API */ +#define MPC55XX_IRQ_EDMA_GET_REQUEST(ch) MPC55XX_IRQ_EDMA(ch) +#define MPC55XX_IRQ_EMIOS_GET_REQUEST(ch) MPC55XX_IRQ_EMIOS(ch) + +#ifdef __cplusplus +}; +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_IRQ_H */ diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h b/bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h new file mode 100644 index 0000000000..b432b9cecd --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h @@ -0,0 +1,170 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Low-level configuration. + */ + +/* + * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_MPC55XXEVB_MPC55XX_CONFIG_H +#define LIBBSP_POWERPC_MPC55XXEVB_MPC55XX_CONFIG_H + +#include + +#include + +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + uint32_t index : 10; + uint32_t count : 10; + uint32_t output : 1; + union SIU_PCR_tag pcr; +} mpc55xx_siu_pcr_config; + +extern BSP_START_DATA_SECTION const mpc55xx_siu_pcr_config + mpc55xx_start_config_siu_pcr []; + +extern BSP_START_DATA_SECTION const size_t + mpc55xx_start_config_siu_pcr_count []; + +extern BSP_START_DATA_SECTION const struct + MMU_tag mpc55xx_start_config_mmu_early []; + +extern BSP_START_DATA_SECTION const size_t + mpc55xx_start_config_mmu_early_count []; + +extern BSP_START_DATA_SECTION const struct + MMU_tag mpc55xx_start_config_mmu []; + +extern BSP_START_DATA_SECTION const size_t + mpc55xx_start_config_mmu_count []; + +#ifdef MPC55XX_HAS_FMPLL + typedef struct { + union FMPLL_SYNCR_tag syncr_tmp; + union FMPLL_SYNCR_tag syncr_final; + } mpc55xx_clock_config; +#endif + +#ifdef MPC55XX_HAS_FMPLL_ENHANCED + typedef struct { + union FMPLL_ESYNCR2_tag esyncr2_tmp; + union FMPLL_ESYNCR2_tag esyncr2_final; + union FMPLL_ESYNCR1_tag esyncr1_final; + } mpc55xx_clock_config; +#endif + +#ifdef MPC55XX_HAS_MODE_CONTROL + typedef struct { + struct { + PLLD_CR_32B_tag cr; + PLLD_MR_32B_tag mr; + } fmpll [2]; + CGM_OC_EN_32B_tag oc_en; + CGM_OCDS_SC_32B_tag ocds_sc; + CGM_SC_DC0_3_32B_tag sc_dc0_3; + CGM_AUXCLK_tag auxclk [5]; + } mpc55xx_clock_config; +#endif + +extern BSP_START_DATA_SECTION const mpc55xx_clock_config + mpc55xx_start_config_clock []; + +#ifdef MPC55XX_HAS_EBI + typedef struct { + union EBI_MCR_tag ebi_mcr; + uint32_t siu_eccr_ebdf; + } mpc55xx_ebi_config; + + extern BSP_START_DATA_SECTION const mpc55xx_ebi_config + mpc55xx_start_config_ebi []; + + extern BSP_START_DATA_SECTION const size_t + mpc55xx_start_config_ebi_count []; + + extern BSP_START_DATA_SECTION const struct EBI_CS_tag + mpc55xx_start_config_ebi_cs []; + + extern BSP_START_DATA_SECTION const size_t + mpc55xx_start_config_ebi_cs_count []; + + extern BSP_START_DATA_SECTION const struct EBI_CAL_CS_tag + mpc55xx_start_config_ebi_cal_cs []; + + extern BSP_START_DATA_SECTION const size_t + mpc55xx_start_config_ebi_cal_cs_count []; +#endif + +/** + * @brief Start prologue. + * + * In case the BSP enabled the MPC55XX_ENABLE_START_PROLOGUE option, then this + * function will be called directly after the Boot Assist Module (BAM) jumped + * to the start entry defined by the reset configuration. + * + * This function executes in the context initialized by the BAM. There exists + * no valid stack pointer and the internal RAM has an invalid ECC state. + * + * The default implementation does nothing. The application may provide its + * own implementation. + */ +void mpc55xx_start_prologue(void); + +void mpc55xx_start_early(void); + +void mpc55xx_start_flash(void); + +void mpc55xx_start_cache(void); + +void mpc55xx_start_clock(void); + +void mpc55xx_start_watchdog(void); + +void mpc55xx_start_mmu_apply_config(const struct MMU_tag *config, size_t count); + +uint32_t mpc55xx_get_system_clock(void); + +LINKER_SYMBOL(bsp_ram_start) +LINKER_SYMBOL(bsp_ram_end) +LINKER_SYMBOL(bsp_ram_size) + +LINKER_SYMBOL(bsp_ram_1_start) +LINKER_SYMBOL(bsp_ram_1_end) +LINKER_SYMBOL(bsp_ram_1_size) + +LINKER_SYMBOL(bsp_rom_start) +LINKER_SYMBOL(bsp_rom_end) +LINKER_SYMBOL(bsp_rom_size) + +#ifdef MPC55XX_BOOTFLAGS + extern uint32_t mpc55xx_bootflag_0 []; +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_MPC55XXEVB_MPC55XX_CONFIG_H */ diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h b/bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h new file mode 100644 index 0000000000..e4366b039c --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h @@ -0,0 +1,704 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief SMSC - LAN9218i + */ + +/* + * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +/** + * @name Memory Map + * @{ + */ + +typedef struct { + uint32_t rx_fifo_data; + uint32_t rx_fifo_data_aliases [7]; + uint32_t tx_fifo_data; + uint32_t tx_fifo_data_aliases [7]; + uint32_t rx_fifo_status; + uint32_t rx_fifo_status_peek; + uint32_t tx_fifo_status; + uint32_t tx_fifo_status_peek; + uint32_t id_rev; + uint32_t irq_cfg; + uint32_t int_sts; + uint32_t int_en; + uint32_t reserved_0; + uint32_t byte_test; + uint32_t fifo_int; + uint32_t rx_cfg; + uint32_t tx_cfg; + uint32_t hw_cfg; + uint32_t rx_dp_ctl; + uint32_t rx_fifo_inf; + uint32_t tx_fifo_inf; + uint32_t pmt_ctrl; + uint32_t gpio_cfg; + uint32_t gpt_cfg; + uint32_t gpt_cnt; + uint32_t reserved_1; + uint32_t word_swap; + uint32_t free_run; + uint32_t rx_drop; + uint32_t mac_csr_cmd; + uint32_t mac_csr_data; + uint32_t afc_cfg; + uint32_t e2p_cmd; + uint32_t e2p_data; +} smsc9218i_registers; + +/* + * SMSC9218 registers are accessed little-endian (address 0x3fff8000, A22 used + * as END_SEL). + */ +#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT + volatile smsc9218i_registers *const smsc9218i = + (volatile smsc9218i_registers *) 0x3fff8000; + volatile smsc9218i_registers *const smsc9218i_dma = + (volatile smsc9218i_registers *) 0x3fff8200; +#else + volatile smsc9218i_registers *const smsc9218i = + (volatile smsc9218i_registers *) 0x3fff8000; + volatile smsc9218i_registers *const smsc9218i_dma = + (volatile smsc9218i_registers *) 0x3fff8000; +#endif + +/** @} */ + +#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT + #define SMSC9218I_BIT_POS(pos) (pos) +#else + #define SMSC9218I_BIT_POS(pos) \ + ((pos) > 15 ? \ + ((pos) > 23 ? (pos) - 24 : (pos) - 8) \ + : ((pos) > 7 ? (pos) + 8 : (pos) + 24)) +#endif + +#define SMSC9218I_FLAG(pos) \ + (1U << SMSC9218I_BIT_POS(pos)) + +#define SMSC9218I_FIELD_8(val, pos) \ + (((val) & 0xff) << SMSC9218I_BIT_POS(pos)) + +#define SMSC9218I_GET_FIELD_8(reg, pos) \ + (((reg) >> SMSC9218I_BIT_POS(pos)) & 0xff) + +#define SMSC9218I_FIELD_16(val, pos) \ + (SMSC9218I_FIELD_8((val) >> 8, (pos) + 8) \ + | SMSC9218I_FIELD_8((val), pos)) + +#define SMSC9218I_GET_FIELD_16(reg, pos) \ + ((SMSC9218I_GET_FIELD_8(reg, (pos) + 8) << 8) \ + | SMSC9218I_GET_FIELD_8(reg, pos)) + +#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT + #define SMSC9218I_SWAP(val) (val) +#else + #define SMSC9218I_SWAP(val) \ + ((((val) >> 24) & 0xff) \ + | ((((val) >> 16) & 0xff) << 8) \ + | ((((val) >> 8) & 0xff) << 16) \ + | (((val) & 0xff) << 24)) +#endif + +/** + * @name Receive Status + * @{ + */ + +#define SMSC9218I_RX_STS_FILTER_FAIL SMSC9218I_FLAG(30) +#define SMSC9218I_RX_STS_GET_LENGTH(reg) (SMSC9218I_GET_FIELD_16(reg, 16) & 0x3fff) +#define SMSC9218I_RX_STS_ERROR SMSC9218I_FLAG(15) +#define SMSC9218I_RX_STS_BROADCAST SMSC9218I_FLAG(13) +#define SMSC9218I_RX_STS_ERROR_LENGTH SMSC9218I_FLAG(12) +#define SMSC9218I_RX_STS_ERROR_RUNT_FRAME SMSC9218I_FLAG(11) +#define SMSC9218I_RX_STS_MULTICAST SMSC9218I_FLAG(10) +#define SMSC9218I_RX_STS_ERROR_TOO_LONG SMSC9218I_FLAG(7) +#define SMSC9218I_RX_STS_ERROR_COLLISION SMSC9218I_FLAG(6) +#define SMSC9218I_RX_STS_TYPE SMSC9218I_FLAG(5) +#define SMSC9218I_RX_STS_WATCHDOG SMSC9218I_FLAG(4) +#define SMSC9218I_RX_STS_ERROR_MII SMSC9218I_FLAG(3) +#define SMSC9218I_RX_STS_DRIBBLING_BIT SMSC9218I_FLAG(2) +#define SMSC9218I_RX_STS_ERROR_CRC SMSC9218I_FLAG(1) + +/** @} */ + +/** + * @name Transmit Status + * @{ + */ + +#define SMSC9218I_TX_STS_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16) +#define SMSC9218I_TX_STS_ERROR SMSC9218I_FLAG(15) +#define SMSC9218I_TX_STS_ERROR_LOSS_OF_CARRIER SMSC9218I_FLAG(11) +#define SMSC9218I_TX_STS_ERROR_NO_CARRIER SMSC9218I_FLAG(10) +#define SMSC9218I_TX_STS_ERROR_LATE_COLLISION SMSC9218I_FLAG(9) +#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_COLLISIONS SMSC9218I_FLAG(8) +#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_DEFERRAL SMSC9218I_FLAG(2) +#define SMSC9218I_TX_STS_ERROR_DEFERRED SMSC9218I_FLAG(0) + +/** @} */ + +/** + * @name Transmit Command A + * @{ + */ + +#define SMSC9218I_TX_A_IOC SMSC9218I_FLAG(31) +#define SMSC9218I_TX_A_END_ALIGN_4 0 +#define SMSC9218I_TX_A_END_ALIGN_16 SMSC9218I_FLAG(24) +#define SMSC9218I_TX_A_END_ALIGN_32 SMSC9218I_FLAG(25) +#define SMSC9218I_TX_A_DOFF(val) SMSC9218I_FIELD_8(val, 16) +#define SMSC9218I_TX_A_FIRST SMSC9218I_FLAG(13) +#define SMSC9218I_TX_A_LAST SMSC9218I_FLAG(12) +#define SMSC9218I_TX_A_FRAGMENT_LENGTH(val) SMSC9218I_FIELD_16(val, 0) + +/** @} */ + +/** + * @name Transmit Command B + * @{ + */ + +#define SMSC9218I_TX_B_TAG(val) SMSC9218I_FIELD_16(val, 16) +#define SMSC9218I_TX_B_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16) +#define SMSC9218I_TX_B_DISABLE_CRC SMSC9218I_FLAG(13) +#define SMSC9218I_TX_B_DISABLE_PAD SMSC9218I_FLAG(12) +#define SMSC9218I_TX_B_FRAME_LENGTH(val) SMSC9218I_FIELD_16(val, 0) + +/** @} */ + +/** + * @name Chip ID and Revision + * @{ + */ + +#define SMSC9218I_ID_REV_GET_ID(reg) SMSC9218I_GET_FIELD_16(reg, 16) +#define SMSC9218I_ID_REV_GET_REV(reg) SMSC9218I_GET_FIELD_16(reg, 0) +#define SMSC9218I_ID_REV_ID_CHIP_118 0x0118U +#define SMSC9218I_ID_REV_ID_CHIP_218 0x118aU + +/** @} */ + +/** + * @name Interrupt Configuration + * @{ + */ + +#define SMSC9218I_IRQ_CFG_INT_DEAS(val) SMSC9218I_FIELD_8(val, 24) +#define SMSC9218I_IRQ_CFG_GET_INT_DEAS(reg) SMSC9218I_GET_FIELD_8(reg, 24) +#define SMSC9218I_IRQ_CFG_INT_DEAS_CLR SMSC9218I_FLAG(14) +#define SMSC9218I_IRQ_CFG_INT_DEAS_STS SMSC9218I_FLAG(13) +#define SMSC9218I_IRQ_CFG_IRQ_INT SMSC9218I_FLAG(12) +#define SMSC9218I_IRQ_CFG_IRQ_EN SMSC9218I_FLAG(8) +#define SMSC9218I_IRQ_CFG_IRQ_POL SMSC9218I_FLAG(4) +#define SMSC9218I_IRQ_CFG_IRQ_TYPE SMSC9218I_FLAG(0) + +/** @} */ + +/** + * @name Interrupt Enable and Status + * @{ + */ + +#define SMSC9218I_INT_SW SMSC9218I_FLAG(31) +#define SMSC9218I_INT_TXSTOP SMSC9218I_FLAG(25) +#define SMSC9218I_INT_RXSTOP SMSC9218I_FLAG(24) +#define SMSC9218I_INT_RXDFH SMSC9218I_FLAG(23) +#define SMSC9218I_INT_TIOC SMSC9218I_FLAG(21) +#define SMSC9218I_INT_RXD SMSC9218I_FLAG(20) +#define SMSC9218I_INT_GPT SMSC9218I_FLAG(19) +#define SMSC9218I_INT_PHY SMSC9218I_FLAG(18) +#define SMSC9218I_INT_PME SMSC9218I_FLAG(17) +#define SMSC9218I_INT_TXSO SMSC9218I_FLAG(16) +#define SMSC9218I_INT_RWT SMSC9218I_FLAG(15) +#define SMSC9218I_INT_RXE SMSC9218I_FLAG(14) +#define SMSC9218I_INT_TXE SMSC9218I_FLAG(13) +#define SMSC9218I_INT_TDFO SMSC9218I_FLAG(10) +#define SMSC9218I_INT_TDFA SMSC9218I_FLAG(9) +#define SMSC9218I_INT_TSFF SMSC9218I_FLAG(8) +#define SMSC9218I_INT_TSFL SMSC9218I_FLAG(7) +#define SMSC9218I_INT_RSFF SMSC9218I_FLAG(4) +#define SMSC9218I_INT_RSFL SMSC9218I_FLAG(3) +#define SMSC9218I_INT_GPIO2 SMSC9218I_FLAG(2) +#define SMSC9218I_INT_GPIO1 SMSC9218I_FLAG(1) +#define SMSC9218I_INT_GPIO0 SMSC9218I_FLAG(0) + +/** @} */ + +/** + * @name Byte Order Testing + * @{ + */ + +#define SMSC9218I_BYTE_TEST SMSC9218I_SWAP(0x87654321U) + +/** @} */ + +/** + * @name FIFO Level Interrupts + * @{ + */ + +#define SMSC9218I_FIFO_INT_TDAL(val) SMSC9218I_FIELD_8(val, 24) +#define SMSC9218I_FIFO_INT_GET_TDAL(reg) SMSC9218I_GET_FIELD_8(reg, 24) +#define SMSC9218I_FIFO_INT_TSL(val) SMSC9218I_FIELD_8(val, 16) +#define SMSC9218I_FIFO_INT_GET_TSL(reg) SMSC9218I_GET_FIELD_8(reg, 16) +#define SMSC9218I_FIFO_INT_RSL(val) SMSC9218I_FIELD_8(val, 0) +#define SMSC9218I_FIFO_INT_GET_RSL(reg) SMSC9218I_GET_FIELD_8(reg, 0) + +/** @} */ + +/** + * @name Receive Configuration + * @{ + */ + +#define SMSC9218I_RX_CFG_END_ALIGN_4 0 +#define SMSC9218I_RX_CFG_END_ALIGN_16 SMSC9218I_FLAG(30) +#define SMSC9218I_RX_CFG_END_ALIGN_32 SMSC9218I_FLAG(31) +#define SMSC9218I_RX_CFG_DMA_CNT(val) SMSC9218I_FIELD_8(val, 24) +#define SMSC9218I_RX_CFG_GET_DMA_CNT(reg) SMSC9218I_GET_FIELD_8(reg, 24) +#define SMSC9218I_RX_CFG_DUMP SMSC9218I_FLAG(15) +#define SMSC9218I_RX_CFG_DOFF(val) SMSC9218I_FIELD_8(val, 8) +#define SMSC9218I_RX_CFG_GET_DOFF(reg) SMSC9218I_GET_FIELD_8(reg, 8) + +/** @} */ + +/** + * @name Transmit Configuration + * @{ + */ + +#define SMSC9218I_TX_CFG_SDUMP SMSC9218I_FLAG(15) +#define SMSC9218I_TX_CFG_DDUMP SMSC9218I_FLAG(14) +#define SMSC9218I_TX_CFG_SAO SMSC9218I_FLAG(2) +#define SMSC9218I_TX_CFG_ON SMSC9218I_FLAG(1) +#define SMSC9218I_TX_CFG_STOP SMSC9218I_FLAG(0) + +/** @} */ + +/** + * @name Hardware Configuration + * @{ + */ + +#define SMSC9218I_HW_CFG_LED_3 SMSC9218I_FLAG(30) +#define SMSC9218I_HW_CFG_LED_2 SMSC9218I_FLAG(29) +#define SMSC9218I_HW_CFG_LED_1 SMSC9218I_FLAG(28) +#define SMSC9218I_HW_CFG_AMDIX SMSC9218I_FLAG(24) +#define SMSC9218I_HW_CFG_MBO SMSC9218I_FLAG(20) +#define SMSC9218I_HW_CFG_TX_FIF_SZ(val) SMSC9218I_FIELD_8(val, 16) +#define SMSC9218I_HW_CFG_GET_TX_FIF_SZ(reg) SMSC9218I_GET_FIELD_8(reg, 16) +#define SMSC9218I_HW_CFG_BITMD_32 SMSC9218I_FLAG(2) +#define SMSC9218I_HW_CFG_SRST_TO SMSC9218I_FLAG(1) +#define SMSC9218I_HW_CFG_SRST SMSC9218I_FLAG(0) + +/** @} */ + +/** + * @name Receive Datapath Control + * @{ + */ + +#define SMSC9218I_RX_DP_CTRL_FFWD SMSC9218I_FLAG(31) + +/** @} */ + +/** + * @name Receive FIFO Information + * @{ + */ + +#define SMSC9218I_RX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16) +#define SMSC9218I_RX_FIFO_INF_GET_DUSED(reg) SMSC9218I_GET_FIELD_16(reg, 0) + +/** @} */ + +/** + * @name Transmit FIFO Information + * @{ + */ + +#define SMSC9218I_TX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16) +#define SMSC9218I_TX_FIFO_INF_GET_FREE(reg) SMSC9218I_GET_FIELD_16(reg, 0) + +/** @} */ + +/** + * @name Power Management Control + * @{ + */ + +#define SMSC9218I_PMT_CTRL_PM_MODE_D0 0 +#define SMSC9218I_PMT_CTRL_PM_MODE_D1 SMSC9218I_FLAG(12) +#define SMSC9218I_PMT_CTRL_PM_MODE_D2 SMSC9218I_FLAG(13) +#define SMSC9218I_PMT_CTRL_PHY_RST SMSC9218I_FLAG(10) +#define SMSC9218I_PMT_CTRL_WOL_EN SMSC9218I_FLAG(9) +#define SMSC9218I_PMT_CTRL_ED_EN SMSC9218I_FLAG(8) +#define SMSC9218I_PMT_CTRL_PME_TYPE_PUPU SMSC9218I_FLAG(6) +#define SMSC9218I_PMT_CTRL_WUPS_NO 0 +#define SMSC9218I_PMT_CTRL_WUPS_ENERGY SMSC9218I_FLAG(4) +#define SMSC9218I_PMT_CTRL_WUPS_MAGIC SMSC9218I_FLAG(5) +#define SMSC9218I_PMT_CTRL_PME_IND SMSC9218I_FLAG(3) +#define SMSC9218I_PMT_CTRL_PME_POL SMSC9218I_FLAG(2) +#define SMSC9218I_PMT_CTRL_PME_EN SMSC9218I_FLAG(1) +#define SMSC9218I_PMT_CTRL_READY SMSC9218I_FLAG(0) + +/** @} */ + +/** + * @name General Purpose IO Configuration + * @{ + */ + +#define SMSC9218I_GPIO_CFG_LED3 SMSC9218I_FLAG(30) +#define SMSC9218I_GPIO_CFG_LED2 SMSC9218I_FLAG(29) +#define SMSC9218I_GPIO_CFG_LED1 SMSC9218I_FLAG(28) +#define SMSC9218I_GPIO_CFG_GPIO2_INT_POL SMSC9218I_FLAG(26) +#define SMSC9218I_GPIO_CFG_GPIO1_INT_POL SMSC9218I_FLAG(25) +#define SMSC9218I_GPIO_CFG_GPIO0_INT_POL SMSC9218I_FLAG(24) +#define SMSC9218I_GPIO_CFG_GPIOBUF2 SMSC9218I_FLAG(18) +#define SMSC9218I_GPIO_CFG_GPIOBUF1 SMSC9218I_FLAG(17) +#define SMSC9218I_GPIO_CFG_GPIOBUF0 SMSC9218I_FLAG(16) +#define SMSC9218I_GPIO_CFG_GPIODIR2 SMSC9218I_FLAG(10) +#define SMSC9218I_GPIO_CFG_GPIODIR1 SMSC9218I_FLAG(9) +#define SMSC9218I_GPIO_CFG_GPIODIR0 SMSC9218I_FLAG(8) +#define SMSC9218I_GPIO_CFG_GPO4 SMSC9218I_FLAG(4) +#define SMSC9218I_GPIO_CFG_GPO3 SMSC9218I_FLAG(3) +#define SMSC9218I_GPIO_CFG_GPIO0 SMSC9218I_FLAG(0) +#define SMSC9218I_GPIO_CFG_GPIO2 SMSC9218I_FLAG(2) +#define SMSC9218I_GPIO_CFG_GPIO1 SMSC9218I_FLAG(1) + +/** @} */ + +/** + * @name General Purpose Timer Configuration + * @{ + */ + +#define SMSC9218I_GPT_CFG_TIMER_EN SMSC9218I_FLAG(29) +#define SMSC9218I_GPT_CFG_LOAD(val) SMSC9218I_FIELD_16(val, 0) +#define SMSC9218I_GPT_CFG_GET_LOAD(reg) SMSC9218I_GET_FIELD_16(reg, 0) + +/** @} */ + +/** + * @name General Purpose Timer Count + * @{ + */ + +#define SMSC9218I_GPT_CNT_GET_CNT SMSC9218I_GET_FIELD_16(reg, 0) + +/** @} */ + +/** + * @name Word Swap + * @{ + */ + +#define SMSC9218I_ENDIAN_BIG 0xffffffffU + +/** @} */ + +/** + * @name Free Run Counter + * @{ + */ + +#define SMSC9218I_FREE_RUN_GET(reg) SMSC9218I_SWAP(reg) + +/** @} */ + +/** + * @name Receiver Dropped Frames Counter + * @{ + */ + +#define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg) + +/** @} */ + +/** + * @name EEPROM Command Register + * @{ + */ + +#define SMSC9218I_E2P_CMD_EPC_BUSY SMSC9218I_FLAG(31) + +/** @} */ + +/** + * @name MAC Control and Status Synchronizer Command + * @{ + */ + +#define SMSC9218I_MAC_CSR_CMD_BUSY SMSC9218I_FLAG(31) +#define SMSC9218I_MAC_CSR_CMD_READ SMSC9218I_FLAG(30) +#define SMSC9218I_MAC_CSR_CMD_ADDR(val) SMSC9218I_FIELD_8(val, 0) +#define SMSC9218I_MAC_CSR_CMD_GET_ADDR(reg) SMSC9218I_GET_FIELD_8(reg, 0) + +/** @} */ + +/** + * @name MAC Control Register + * @{ + */ + +#define SMSC9218I_MAC_CR 0x00000001U +#define SMSC9218I_MAC_CR_RXALL 0x80000000U +#define SMSC9218I_MAC_CR_HBDIS 0x10000000U +#define SMSC9218I_MAC_CR_RCVOWN 0x00800000U +#define SMSC9218I_MAC_CR_LOOPBK 0x00200000U +#define SMSC9218I_MAC_CR_FDPX 0x00100000U +#define SMSC9218I_MAC_CR_MCPAS 0x00080000U +#define SMSC9218I_MAC_CR_PRMS 0x00040000U +#define SMSC9218I_MAC_CR_INVFILT 0x00020000U +#define SMSC9218I_MAC_CR_PASSBAD 0x00010000U +#define SMSC9218I_MAC_CR_HFILT 0x00008000U +#define SMSC9218I_MAC_CR_HPFILT 0x00002000U +#define SMSC9218I_MAC_CR_LCOLL 0x00001000U +#define SMSC9218I_MAC_CR_BCAST 0x00000800U +#define SMSC9218I_MAC_CR_DISRTY 0x00000400U +#define SMSC9218I_MAC_CR_PADSTR 0x00000100U +#define SMSC9218I_MAC_CR_BOLMT_MASK 0x000000c0U +#define SMSC9218I_MAC_CR_BOLMT_10 0x00000000U +#define SMSC9218I_MAC_CR_BOLMT_8 0x00000040U +#define SMSC9218I_MAC_CR_BOLMT_4 0x00000080U +#define SMSC9218I_MAC_CR_BOLMT_1 0x000000c0U +#define SMSC9218I_MAC_CR_DFCHK 0x00000020U +#define SMSC9218I_MAC_CR_TXEN 0x00000008U +#define SMSC9218I_MAC_CR_RXEN 0x00000004U + +/** @} */ + +/** + * @name MAC Address High + * @{ + */ + +#define SMSC9218I_MAC_ADDRH 0x00000002U +#define SMSC9218I_MAC_ADDRH_MASK 0x0000ffffU + +/** @} */ + +/** + * @name MAC Address Low + * @{ + */ + +#define SMSC9218I_MAC_ADDRL 0x00000003U +#define SMSC9218I_MAC_ADDRL_MASK 0xffffffffU + +/** @} */ + +/** + * @name Multicast Hash Table High + * @{ + */ + +#define SMSC9218I_MAC_HASHH 0x00000004U +#define SMSC9218I_MAC_HASHH_MASK 0xffffffffU + +/** @} */ + +/** + * @name Multicast Hash Table Low + * @{ + */ + +#define SMSC9218I_MAC_HASHL 0x00000005U +#define SMSC9218I_MAC_HASHL_MASK 0xffffffffU + +/** @} */ + +/** + * @name MII Access + * @{ + */ + +#define SMSC9218I_MAC_MII_ACC 0x00000006U +#define SMSC9218I_MAC_MII_ACC_PHY_DEFAULT (1U << 11) +#define SMSC9218I_MAC_MII_ACC_WRITE (1U << 1) +#define SMSC9218I_MAC_MII_ACC_BUSY (1U << 0) +#define SMSC9218I_MAC_MII_ACC_ADDR(addr) ((addr) << 6) + +/** @} */ + +/** + * @name MII Data + * @{ + */ + +#define SMSC9218I_MAC_MII_DATA 0x00000007U + +/** @} */ + +/** + * @name Flow Control + * @{ + */ + +#define SMSC9218I_MAC_FLOW 0x00000008U +#define SMSC9218I_MAC_FLOW_FCPT_MASK 0xffff0000U +#define SMSC9218I_MAC_FLOW_FCPASS 0x00000004U +#define SMSC9218I_MAC_FLOW_FCEN 0x00000002U +#define SMSC9218I_MAC_FLOW_FCBSY 0x00000001U + +/** @} */ + +/** + * @name VLAN1 Tag + * @{ + */ + +#define SMSC9218I_MAC_VLAN1 0x00000009U + +/** @} */ + +/** + * @name VLAN2 Tag + * @{ + */ + +#define SMSC9218I_MAC_VLAN2 0x0000000aU + +/** @} */ + +/** + * @name Wake-up Frame Filter + * @{ + */ + +#define SMSC9218I_MAC_WUFF 0x0000000bU + +/** @} */ + +/** + * @name Wake-up Control and Status + * @{ + */ + +#define SMSC9218I_MAC_WUCSR 0x0000000cU +#define SMSC9218I_MAC_WUCSR_GUE 0x00000200U +#define SMSC9218I_MAC_WUCSR_WUFR 0x00000040U +#define SMSC9218I_MAC_WUCSR_MPR 0x00000020U +#define SMSC9218I_MAC_WUCSR_WUEN 0x00000004U +#define SMSC9218I_MAC_WUCSR_MPEN 0x00000002U + +/** @} */ + +/** + * @name PHY Identifier 1 + * @{ + */ + +#define SMSC9218I_PHY_ID1_LAN9118 0x7 + +/** @} */ + +/** + * @name PHY Identifier 2 + * @{ + */ + +#define SMSC9218I_PHY_ID2_LAN9218 0xc0c3 + +/** @} */ + +/** + * @name Mode Control and Status + * @{ + */ + +#define SMSC9218I_PHY_MCSR 0x00000011U +#define SMSC9218I_PHY_MCSR_EDPWRDOWN 0x00002000U +#define SMSC9218I_PHY_MCSR_ENERGYON 0x00000002U + +/** @} */ + +/** + * @name Special Modes + * @{ + */ + +#define SMSC9218I_PHY_SPMODES 0x00000012U + +/** @} */ + +/** + * @name Special Control and Status Indications + * @{ + */ + +#define SMSC9218I_PHY_CSIR 0x0000001bU +#define SMSC9218I_PHY_CSIR_SQEOFF 0x00000800U +#define SMSC9218I_PHY_CSIR_FEFIEN 0x00000020U +#define SMSC9218I_PHY_CSIR_XPOL 0x00000010U + +/** @} */ + +/** + * @name Interrupt Source Flag + * @{ + */ + +#define SMSC9218I_PHY_ISR 0x0000001dU +#define SMSC9218I_PHY_ISR_INT7 0x00000080U +#define SMSC9218I_PHY_ISR_INT6 0x00000040U +#define SMSC9218I_PHY_ISR_INT5 0x00000020U +#define SMSC9218I_PHY_ISR_INT4 0x00000010U +#define SMSC9218I_PHY_ISR_INT3 0x00000008U +#define SMSC9218I_PHY_ISR_INT2 0x00000004U +#define SMSC9218I_PHY_ISR_INT1 0x00000002U + +/** @} */ + +/** + * @name Interrupt Mask + * @{ + */ + +#define SMSC9218I_PHY_IMR 0x0000001eU +#define SMSC9218I_PHY_IMR_INT7 0x00000080U +#define SMSC9218I_PHY_IMR_INT6 0x00000040U +#define SMSC9218I_PHY_IMR_INT5 0x00000020U +#define SMSC9218I_PHY_IMR_INT4 0x00000010U +#define SMSC9218I_PHY_IMR_INT3 0x00000008U +#define SMSC9218I_PHY_IMR_INT2 0x00000004U +#define SMSC9218I_PHY_IMR_INT1 0x00000002U + +/** @} */ + +/** + * @name PHY Special Control and Status + * @{ + */ + +#define SMSC9218I_PHY_PHYSCSR 0x0000001fU +#define SMSC9218I_PHY_PHYSCSR_ANDONE 0x00001000U +#define SMSC9218I_PHY_PHYSCSR_4B5B_EN 0x00000040U +#define SMSC9218I_PHY_PHYSCSR_SPEED_MASK 0x0000001cU +#define SMSC9218I_PHY_PHYSCSR_SPEED_10HD 0x00000004U +#define SMSC9218I_PHY_PHYSCSR_SPEED_10FD 0x00000014U +#define SMSC9218I_PHY_PHYSCSR_SPEED_100HD 0x00000008U +#define SMSC9218I_PHY_PHYSCSR_SPEED_100FD 0x00000018U + +/** @} */ diff --git a/bsps/powerpc/mpc55xxevb/include/tm27.h b/bsps/powerpc/mpc55xxevb/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/powerpc/mpc8260ads/headers.am b/bsps/powerpc/mpc8260ads/headers.am new file mode 100644 index 0000000000..10c6e42313 --- /dev/null +++ b/bsps/powerpc/mpc8260ads/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/mpc8260ads/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/mpc8260ads/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc8260ads/include/bsp/irq.h diff --git a/bsps/powerpc/mpc8260ads/include/bsp.h b/bsps/powerpc/mpc8260ads/include/bsp.h new file mode 100644 index 0000000000..c207a2ec99 --- /dev/null +++ b/bsps/powerpc/mpc8260ads/include/bsp.h @@ -0,0 +1,86 @@ +/* + * This include file contains all board IO definitions. + */ + +/* + * COPYRIGHT (c) 1989-2014. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_MPC8260ADS_BSP_H +#define LIBBSP_POWERPC_MPC8260ADS_BSP_H + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Board configuration registers + */ + +typedef struct bcsr + +{ + uint32_t bcsr0; /* Board Control and Status Register */ + uint32_t bcsr1; + uint32_t bcsr2; + uint32_t bcsr3; + +} BCSR; + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_enet_driver_attach + +/* miscellaneous stuff assumed to exist */ + +/* + * We need to decide how much memory will be non-cacheable. This + * will mainly be memory that will be used in DMA (network and serial + * buffers). + */ +/* +#define NOCACHE_MEM_SIZE 512*1024 +*/ + +/* functions */ + +#if 0 +void M8260ExecuteRISC( uint32_t command ); +void *M8260AllocateBufferDescriptors( int count ); +void *M8260AllocateRiscTimers( int count ); +extern char M8260DefaultWatchdogFeeder; +#endif + +/* + * Prototypes for items shared across file boundaries in the BSP + */ +extern uint32_t bsp_serial_per_sec; +void *bsp_idle_thread( uintptr_t ignored ); +void cpu_init(void); +int mbx8xx_console_get_configuration(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/mpc8260ads/include/bsp/irq.h b/bsps/powerpc/mpc8260ads/include/bsp/irq.h new file mode 100644 index 0000000000..1dd18611fc --- /dev/null +++ b/bsps/powerpc/mpc8260ads/include/bsp/irq.h @@ -0,0 +1,193 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * by following + * the STREAM API Specification Document link. + * + * Modified for mpc8260 by Andy Dachs + * Surrey Satellite Technology Limited + * The interrupt handling on the mpc8260 seems quite different from + * the 860 (I don't know the 860 well). Although some interrupts + * are routed via the CPM irq and some are direct to the SIU they all + * appear logically the same. Therefore I removed the distinction + * between SIU and CPM interrupts. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_IRQ_H +#define LIBBSP_POWERPC_IRQ_H +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* +extern volatile unsigned int ppc_cached_irq_mask; +*/ + +/* + * Symblolic IRQ names and related definitions. + */ + + /* + * CPM IRQ handlers related definitions + * CAUTION : BSP_CPM_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE + */ +#define BSP_CPM_IRQ_NUMBER (64) +#define BSP_CPM_IRQ_LOWEST_OFFSET (0) +#define BSP_CPM_IRQ_MAX_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER - 1) + /* + * PowerPc exceptions handled as interrupt where a rtems managed interrupt + * handler might be connected + */ +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET + 1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) + /* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_LOWEST_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET) + + /* + * Some SIU IRQ symbolic name definition. Please note that + * INT IRQ are defined but a single one will be used to + * redirect all CPM interrupt. + * + * On the mpc8260 all this seems to be transparent. Although the + * CPM, PIT and TMCNT interrupt may well be the only interrupts routed + * to the SIU at the hardware level all of them appear as CPM interupts + * to software apart from the registers for setting priority. + * + * The MPC8260 User Manual seems shot through with inconsistencies + * about this whole area. + */ + + /* + * Some CPM IRQ symbolic name definition + */ +#define BSP_CPM_IRQ_ERROR (BSP_CPM_IRQ_LOWEST_OFFSET + 0) +#define BSP_CPM_IRQ_I2C (BSP_CPM_IRQ_LOWEST_OFFSET + 1) +#define BSP_CPM_IRQ_SPI (BSP_CPM_IRQ_LOWEST_OFFSET + 2) +#define BSP_CPM_IRQ_RISC_TIMERS (BSP_CPM_IRQ_LOWEST_OFFSET + 3) +#define BSP_CPM_IRQ_SMC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 4) +#define BSP_CPM_IRQ_SMC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 5) +#define BSP_CPM_IRQ_IDMA1 (BSP_CPM_IRQ_LOWEST_OFFSET + 6) +#define BSP_CPM_IRQ_IDMA2 (BSP_CPM_IRQ_LOWEST_OFFSET + 7) +#define BSP_CPM_IRQ_IDMA3 (BSP_CPM_IRQ_LOWEST_OFFSET + 8) +#define BSP_CPM_IRQ_IDMA4 (BSP_CPM_IRQ_LOWEST_OFFSET + 9) +#define BSP_CPM_IRQ_SDMA (BSP_CPM_IRQ_LOWEST_OFFSET + 10) + +#define BSP_CPM_IRQ_TIMER_1 (BSP_CPM_IRQ_LOWEST_OFFSET + 12) +#define BSP_CPM_IRQ_TIMER_2 (BSP_CPM_IRQ_LOWEST_OFFSET + 13) +#define BSP_CPM_IRQ_TIMER_3 (BSP_CPM_IRQ_LOWEST_OFFSET + 14) +#define BSP_CPM_IRQ_TIMER_4 (BSP_CPM_IRQ_LOWEST_OFFSET + 15) +#define BSP_CPM_IRQ_TMCNT (BSP_CPM_IRQ_LOWEST_OFFSET + 16) +#define BSP_CPM_IRQ_PIT (BSP_CPM_IRQ_LOWEST_OFFSET + 17) + +#define BSP_CPM_IRQ_IRQ1 (BSP_CPM_IRQ_LOWEST_OFFSET + 19) +#define BSP_CPM_IRQ_IRQ2 (BSP_CPM_IRQ_LOWEST_OFFSET + 20) +#define BSP_CPM_IRQ_IRQ3 (BSP_CPM_IRQ_LOWEST_OFFSET + 21) +#define BSP_CPM_IRQ_IRQ4 (BSP_CPM_IRQ_LOWEST_OFFSET + 22) +#define BSP_CPM_IRQ_IRQ5 (BSP_CPM_IRQ_LOWEST_OFFSET + 23) +#define BSP_CPM_IRQ_IRQ6 (BSP_CPM_IRQ_LOWEST_OFFSET + 24) +#define BSP_CPM_IRQ_IRQ7 (BSP_CPM_IRQ_LOWEST_OFFSET + 25) + +#define BSP_CPM_IRQ_FCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 32) +#define BSP_CPM_IRQ_FCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 33) +#define BSP_CPM_IRQ_FCC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 34) +#define BSP_CPM_IRQ_MCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 36) +#define BSP_CPM_IRQ_MCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 37) + +#define BSP_CPM_IRQ_SCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 40) +#define BSP_CPM_IRQ_SCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 41) +#define BSP_CPM_IRQ_SCC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 42) +#define BSP_CPM_IRQ_SCC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 43) + +#define BSP_CPM_IRQ_PC15 (BSP_CPM_IRQ_LOWEST_OFFSET + 48) +#define BSP_CPM_IRQ_PC14 (BSP_CPM_IRQ_LOWEST_OFFSET + 49) +#define BSP_CPM_IRQ_PC13 (BSP_CPM_IRQ_LOWEST_OFFSET + 50) +#define BSP_CPM_IRQ_PC12 (BSP_CPM_IRQ_LOWEST_OFFSET + 51) +#define BSP_CPM_IRQ_PC11 (BSP_CPM_IRQ_LOWEST_OFFSET + 52) +#define BSP_CPM_IRQ_PC10 (BSP_CPM_IRQ_LOWEST_OFFSET + 53) +#define BSP_CPM_IRQ_PC9 (BSP_CPM_IRQ_LOWEST_OFFSET + 54) +#define BSP_CPM_IRQ_PC8 (BSP_CPM_IRQ_LOWEST_OFFSET + 55) +#define BSP_CPM_IRQ_PC7 (BSP_CPM_IRQ_LOWEST_OFFSET + 56) +#define BSP_CPM_IRQ_PC6 (BSP_CPM_IRQ_LOWEST_OFFSET + 57) +#define BSP_CPM_IRQ_PC5 (BSP_CPM_IRQ_LOWEST_OFFSET + 58) +#define BSP_CPM_IRQ_PC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 59) +#define BSP_CPM_IRQ_PC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 60) +#define BSP_CPM_IRQ_PC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 61) +#define BSP_CPM_IRQ_PC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 62) +#define BSP_CPM_IRQ_PC0 (BSP_CPM_IRQ_LOWEST_OFFSET + 63) + + /* + * Some Processor exception handled as rtems IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) +#define BSP_PERIODIC_TIMER (BSP_DECREMENTER) + +#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET + +#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET + +#define CPM_INTERRUPT + +/*-------------------------------------------------------------------------+ +| Function Prototypes. ++--------------------------------------------------------------------------*/ +/* + * ------------------------ PPC CPM Mngt Routines ------- + */ + +/* + * function to disable a particular irq. After calling + * this function, even if the device asserts the interrupt line it will + * not be propagated further to the processor + */ +int BSP_irq_disable_at_cpm (const rtems_irq_number irqLine); +/* + * function to enable a particular irq. After calling + * this function, if the device asserts the interrupt line it will + * be propagated further to the processor + */ +int BSP_irq_enable_at_cpm (const rtems_irq_number irqLine); +/* + * function to acknoledge a particular irq. After calling + * this function, if a device asserts an enabled interrupt line it will + * be propagated further to the processor. Mainly usefull for people + * writting raw handlers as this is automagically done for rtems managed + * handlers. + */ +int BSP_irq_ack_at_cpm (const rtems_irq_number irqLine); +/* + * function to check if a particular irq is enabled. After calling + */ +int BSP_irq_enabled_at_cpm (const rtems_irq_number irqLine); + +extern void BSP_rtems_irq_mng_init(unsigned cpuId); + +#ifdef __cplusplus +} +#endif + +/* Now that we have defined some basics, include the generic support */ +#include + +#endif + +#endif diff --git a/bsps/powerpc/mpc8260ads/include/tm27.h b/bsps/powerpc/mpc8260ads/include/tm27.h new file mode 100644 index 0000000000..b1eafc47aa --- /dev/null +++ b/bsps/powerpc/mpc8260ads/include/tm27.h @@ -0,0 +1,46 @@ +/* + * @file + * @ingroup powerpc_mpc8260ads + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) \ + do { \ + static rtems_irq_connect_data scIrqData = { \ + PPC_IRQ_SCALL, \ + (rtems_irq_hdl) handler, \ + NULL, \ + NULL, \ + NULL \ + }; \ + BSP_install_rtems_irq_handler (&scIrqData); \ + } while(0) + +#define Cause_tm27_intr() __asm__ volatile ("sc") + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/powerpc/mvme3100/headers.am b/bsps/powerpc/mvme3100/headers.am new file mode 100644 index 0000000000..3a242350e6 --- /dev/null +++ b/bsps/powerpc/mvme3100/headers.am @@ -0,0 +1,13 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/mvme3100/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/mvme3100/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme3100/include/bsp/VMEConfig.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme3100/include/bsp/if_tsec_pub.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme3100/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme3100/include/bsp/mpc8540_i2c_busdrv.h diff --git a/bsps/powerpc/mvme3100/include/bsp.h b/bsps/powerpc/mvme3100/include/bsp.h new file mode 100644 index 0000000000..3fbfcb3120 --- /dev/null +++ b/bsps/powerpc/mvme3100/include/bsp.h @@ -0,0 +1,343 @@ +/** + * @file + * + * @ingroup mvme3100_bsp + * + * @brief This file contains BSP API definition. + */ + +/* + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Adapted for the mvme3100 BSP by T. Straumann, 2007. + */ +#ifndef LIBBSP_POWERPC_MVME3100_BSP_H +#define LIBBSP_POWERPC_MVME3100_BSP_H + +#ifndef ASM + +#include +#include + +#include +#include +#include + +/** + * @defgroup mvme3100_bsp confdefs.h overrides + * + * @ingroup powerpc_mvme3100 + * + * @brief confdefs.h overrides for this BSP: + */ + +#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) + +/* + * diagram illustrating the role of the configuration + * constants + * PCI_MEM_WIN0: CPU starting addr where PCI memory space is visible + * PCI_MEM_BASE: CPU address of PCI mem addr. zero. (regardless of this + * address being 'visible' or not!). + * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME + * _VME_A32_WIN0_ON_VME: VME address of that same window + * + * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between + * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI + * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to + * the base address read from PCI config.space in order to translate that + * into a CPU address. + * + * NOTE: VME addresses should NEVER be translated using these constants! + * they are strictly for BSP internal use. Drivers etc. should use + * the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs). + * + * CPU ADDR PCI_ADDR VME ADDR + * + * 00000000 XXXXXXXX XXXXXXXX + * ^ ^ ........ + * | | + * | | e.g., RAM XXXXXXXX + * | | 00000000 + * | | ......... ^ + * | | (possible offset | + * | | between pci and XXXXXXXX | ...... + * | | cpu addresses) | + * | v | + * | PCI_MEM_BASE -------------> 00000000 --------------- | + * | ........ ........ ^ | + * | invisible | | + * | ........ from CPU | | + * v | | + * PCI_MEM_WIN0 ============= first visible PCI addr | | + * | | + * pci devices pci window | | + * visible here v v + * mapped by ========== _VME_A32_WIN0_ON_PCI ======= _VME_A32_WIN0_ON_VME + * vme window + * VME devices hostbridge mapped by + * visible here universe + * ===================================================== + * + */ + +/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */ +#define _IO_BASE 0xe0000000 /* Motload's PCI IO base */ +#define _ISA_MEM_BASE CHRP_ISA_MEM_BASE +/* address of our ram on the PCI bus */ +#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET +/* offset of pci memory as seen from the CPU */ +#define PCI_MEM_BASE 0 +/* where (in CPU addr. space) does the PCI window start */ +#define PCI_MEM_WIN0 0x80000000 + +/* + * Base address definitions for several devices + */ + +#define BSP_OPEN_PIC_BASE_OFFSET 0x40000 +#define BSP_OPEN_PIC_BIG_ENDIAN + +#define BSP_8540_CCSR_BASE (0xe1000000) + +#define BSP_UART_IOBASE_COM1 (BSP_8540_CCSR_BASE+0x4500) +#define BSP_UART_IOBASE_COM2 (BSP_8540_CCSR_BASE+0x4600) +#define PCI_CONFIG_ADDR (BSP_8540_CCSR_BASE+0x8000) +#define PCI_CONFIG_DATA (BSP_8540_CCSR_BASE+0x8004) +#define PCI_CONFIG_WR_ADDR( addr, val ) out_be32((uint32_t*)(addr), (val)) + +#define BSP_CONSOLE_PORT BSP_UART_COM1 +#define BSP_UART_BAUD_BASE (-9600) /* use existing divisor to determine clock rate */ +#define BSP_UART_USE_SHARED_IRQS + +#define BSP_MVME3100_IRQ_DETECT_REG ((volatile uint8_t *)0xe2000007) + +/* I2C Devices */ +/* Note that the i2c addresses stated in the manual are + * left-shifted by one bit. + */ +#define BSP_VPD_I2C_ADDR (0xA8>>1) /* the VPD EEPROM */ +#define BSP_USR0_I2C_ADDR (0xA4>>1) /* the 1st user EEPROM */ +#define BSP_USR1_I2C_ADDR (0xA6>>1) /* the 2nd user EEPROM */ +#define BSP_THM_I2C_ADDR (0x90>>1) /* the DS1621 temperature sensor & thermostat */ +#define BSP_RTC_I2C_ADDR (0xD0>>1) /* the DS1375 wall-clock */ + +#define BSP_I2C_BUS_DESCRIPTOR mpc8540_i2c_bus_descriptor + +#define BSP_I2C_BUS0_NAME "/dev/i2c0" + +#define BSP_I2C_VPD_EEPROM_NAME "vpd-eeprom" +#define BSP_I2C_USR_EEPROM_NAME "usr-eeprom" +#define BSP_I2C_USR1_EEPROM_NAME "usr1-eeprom" +#define BSP_I2C_DS1621_NAME "ds1621" +#define BSP_I2C_THM_NAME BSP_I2C_DS1621_NAME +#define BSP_I2C_DS1621_RAW_NAME "ds1621-raw" +#define BSP_I2C_DS1375_RAW_NAME "ds1375-raw" +#define BSP_I2C_RTC_RAW_NAME BSP_I2C_DS1375_RAW_NAME + +#define BSP_I2C_VPD_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_VPD_EEPROM_NAME) +#define BSP_I2C_USR_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR_EEPROM_NAME) +#define BSP_I2C_USR1_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR1_EEPROM_NAME) +#define BSP_I2C_DS1621_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_NAME) +#define BSP_I2C_THM_DEV_NAME BSP_I2C_DS1621_DEV_NAME +#define BSP_I2C_DS1621_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_RAW_NAME) +#define BSP_I2C_DS1375_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1375_RAW_NAME) + +/* Definitions useful for bootloader (netboot); where to find + * boot/'environment' parameters. + */ +#define BSP_EEPROM_BOOTPARMS_NAME BSP_I2C_USR1_EEPROM_DEV_NAME +#define BSP_EEPROM_BOOTPARMS_SIZE 1024 +#define BSP_EEPROM_BOOTPARMS_OFFSET 0 +#define BSP_BOOTPARMS_WRITE_ENABLE() do { BSP_eeprom_write_enable(); } while (0) +#define BSP_BOOTPARMS_WRITE_DISABLE() do { BSP_eeprom_write_protect();} while (0) + + +#ifdef __cplusplus +extern "C" { +#endif +/* Initialize the I2C driver and register all devices + * RETURNS 0 on success, -1 on error. + * + * Access to the VPD and user EEPROMS as well + * as the ds1621 temperature sensor is possible + * by means of file nodes + * + * /dev/i2c0.vpd-eeprom (read-only) + * /dev/i2c0.usr-eeprom (read-write) + * /dev/i2c0.usr1-eeprom (read-write) + * /dev/i2c0.ds1621 (read-only; one byte: board-temp in degC) + * /dev/i2c0.ds1621-raw (read-write; transfer bytes to/from the ds1621) + * /dev/i2c0.ds1375-raw (read-write; transfer bytes to/from the ds1375) + * + */ +int BSP_i2c_initialize(void); +#define BSP_PREDRIVER_I2C_INIT + +/* System Control Register */ +#define BSP_MVME3100_SYS_CR ((volatile uint8_t *)0xe2000001) +#define BSP_MVME3100_SYS_CR_RESET_MSK (7<<5) +#define BSP_MVME3100_SYS_CR_RESET (5<<5) +#define BSP_MVME3100_SYS_CR_EEPROM_WP (1<<1) +#define BSP_MVME3100_SYS_CR_TSTAT_MSK (1<<0) + +/* LED support */ +#define BSP_MVME3100_SYS_IND_REG ((volatile uint8_t *)0xe2000002) +#define BSP_LED_BRD_FAIL (1<<0) +#define BSP_LED_USR1 (1<<1) +#define BSP_LED_USR2 (1<<2) +#define BSP_LED_USR3 (1<<3) + +/* Flash CSR */ +#define BSP_MVME3100_FLASH_CSR ((volatile uint8_t *)0xe2000003) +#define BSP_MVME3100_FLASH_CSR_FLASH_RDY (1<<0) +#define BSP_MVME3100_FLASH_CSR_FBT_BLK_SEL (1<<1) +#define BSP_MVME3100_FLASH_CSR_F_WP_HW (1<<2) +#define BSP_MVME3100_FLASH_CSR_F_WP_SW (1<<3) +#define BSP_MVME3100_FLASH_CSR_MAP_SEL (1<<4) + +/* Phy interrupt detect */ +#define BSP_MVME3100_IRQ_DETECT_REG ((volatile uint8_t *)0xe2000007) + +/* Atomically set bits in a sys-register; The bits set in 'mask' + * are set in the register others; are left unmodified. + * + * RETURNS: old state. + * + * NOTE : since BSP_setSysReg( reg, 0 ) does not make + * any changes this call may be used + * to read the current status w/o modifying it. + */ +uint8_t BSP_setSysReg(volatile uint8_t *r, uint8_t mask); + +/* Atomically clear bits in a sys-register; The bits set in 'mask' + * are cleared in the register; others are left unmodified. + * + * RETURNS: old state. + * + * NOTE : since BSP_clrSysReg( reg, 0 ) does not make + * any changes this call may be used + * to read the current status w/o modifying it. + */ + +uint8_t BSP_clrSysReg(volatile uint8_t *r, uint8_t mask); + +/* Convenience wrappers around BSP_setSysReg()/BSP_clrSysReg() */ + +/* Set write-protection for all EEPROM devices + * RETURNS: old status + */ +uint8_t BSP_eeprom_write_protect(void); + +/* Disengage write-protection for all EEPROM devices + * RETURNS: old status + */ +uint8_t BSP_eeprom_write_enable(void); + +/* Set LEDs that have their bit set in the mask + * + * RETURNS: old status. + * + * NOTE : since BSP_setLEDs( 0 ) does not make + * any changes this call may be used + * to read the current status w/o modifying it. + */ +uint8_t BSP_setLEDs(uint8_t mask); + +/* Clear LEDs that have their bit set in the mask + * + * RETURNS: old status + * + * NOTE: : see above (BSP_setLEDs) + */ +uint8_t BSP_clrLEDs(uint8_t mask); + +#if 0 +#define outport_byte(port,value) outb(value,port) +#define outport_word(port,value) outw(value,port) +#define outport_long(port,value) outl(value,port) + +#define inport_byte(port,value) (value = inb(port)) +#define inport_word(port,value) (value = inw(port)) +#define inport_long(port,value) (value = inl(port)) +#endif + +/* + * Total memory using RESIDUAL DATA + */ +extern unsigned int BSP_mem_size; +/* + * PCI Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * processor clock frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; +/* + * The commandline as passed from the bootloader. + */ +extern char *BSP_commandline_string; + +#define BSP_Convert_decrementer( _value ) \ + ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) + +extern rtems_configuration_table BSP_Configuration; +/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ +extern int BSP_disconnect_clock_handler (void); +extern int BSP_connect_clock_handler (void); + +/* clear hostbridge errors + * + * NOTE: The routine returns always (-1) if 'enableMCP==1' + * [semantics needed by libbspExt] if the MCP input is not wired. + * It returns and clears the error bits of the PCI status register. + * MCP support is disabled because: + * a) the 2100 has no raven chip + * b) the raven (2300) would raise machine check interrupts + * on PCI config space access to empty slots. + */ +extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); +extern void BSP_motload_pci_fixup(void); + +struct rtems_bsdnet_ifconfig; + +int +rtems_tsec_attach(struct rtems_bsdnet_ifconfig *ifcfg, int attaching); + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "tse1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_tsec_attach + +/* + * Prototypes for methods called only from .S for dependency tracking + */ +char *save_boot_params( + void *r3, + void *r4, + void *r5, + char *cmdline_start, + char *cmdline_end +); +void zero_bss(void); + +/* + * Prototypes for methods in the BSP that cross file boundaries + */ +extern void BSP_vme_config(void); +extern void BSP_pciConfigDump_early( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/powerpc/mvme3100/include/bsp/VMEConfig.h b/bsps/powerpc/mvme3100/include/bsp/VMEConfig.h new file mode 100644 index 0000000000..10b424c2a8 --- /dev/null +++ b/bsps/powerpc/mvme3100/include/bsp/VMEConfig.h @@ -0,0 +1,132 @@ +/** + * @file + * + * @ingroup powerpc_vmeconfig + * + * @brief mvme3100 BSP specific address space configuration parameters + */ + +#ifndef RTEMS_BSP_VME_CONFIG_H +#define RTEMS_BSP_VME_CONFIG_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2002..2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +/* + * NOTE: the BSP (startup/bspstart.c) uses + * hardcoded window lengths that match this + * layout: + */ + +#define _VME_A32_WIN0_ON_PCI 0xc0000000 +#define _VME_CSR_ON_PCI 0xce000000 +#define _VME_A24_ON_PCI 0xcf000000 +#define _VME_A16_ON_PCI 0xcfff0000 + +/* start of the A32 window on the VME bus + * TODO: this should perhaps be a run-time configuration option + */ +#define _VME_A32_WIN0_ON_VME 0x20000000 + +/* if _VME_DRAM_OFFSET is defined, the BSP + * will map the board RAM onto the VME bus, starting + * at _VME_DRAM_OFFSET + */ +#define _VME_DRAM_OFFSET 0xc0000000 + +/* If your BSP requires a non-standard way to configure + * the VME interrupt manager then define the symbol + * + * BSP_VME_INSTALL_IRQ_MGR + * + * to a proper instruction sequence that installs the + * universe interrupt manager. This requires knowledge + * of the wiring between the universe and the PIC (main + * interrupt controller), i.e., which IRQ 'pins' of the + * universe are wired to which 'lines'/inputs at the PIC. + * (consult vmeUniverse.h for more information). + * + * When installing the universe IRQ manager it is also + * possible to specify whether it should try to share + * PIC interrupts with other sources. This might not + * be supported by all BSPs (but the unverse driver + * recognizes that). + * + * If BSP_VME_INSTALL_IRQ_MGR is undefined then + * the default algorithm is used (vme_universe.c): + * + * This default setup uses only a single wire. It reads + * the PIC 'line' from PCI configuration space and assumes + * this to be wired to the first (LIRQ0) IRQ input at the + * universe. The default setup tries to use interrupt + * sharing. + */ + +extern int BSP_VMEInit(void); +extern int BSP_VMEIrqMgrInstall(void); + +/** + * @defgroup powerpc_vme BSP_VME_INSTALL_IRQ_MGR Support + * + * @ingroup powerpc_mvme3100 + * + * @brief BSP_VME_INSTALL_IRQ_MGR Support Package + */ +#define BSP_VME_INSTALL_IRQ_MGR(err) \ + do { \ + err = vmeTsi148InstallIrqMgrAlt(\ + VMETSI148_IRQ_MGR_FLAG_SHARED, /* use shared IRQs */ \ + 0, BSP_VME0_IRQ, \ + 1, BSP_VME1_IRQ, \ + 2, BSP_VME2_IRQ, \ + 3, BSP_VME3_IRQ, \ + -1 /* terminate list */ \ + ); \ + } while (0) + +/* This BSP uses the Tsi148 Driver */ +#define _VME_DRIVER_TSI148 + +#endif diff --git a/bsps/powerpc/mvme3100/include/bsp/if_tsec_pub.h b/bsps/powerpc/mvme3100/include/bsp/if_tsec_pub.h new file mode 100644 index 0000000000..7eb0358eae --- /dev/null +++ b/bsps/powerpc/mvme3100/include/bsp/if_tsec_pub.h @@ -0,0 +1,475 @@ +/** + * @file + * + * @ingroup powerpc_iftsecpub + * + * @brief IF_TSEC_PUB Support + */ + +#ifndef IF_TSEC_PUBLIC_INTERFACE_H +#define IF_TSEC_PUBLIC_INTERFACE_H + +/* + * Authorship + * ---------- + * This software ('mvme3100' RTEMS BSP) was created by + * + * Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'mvme3100' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Opaque driver handle */ +struct tsec_private; + +/********** Low-level Driver API ****************/ + +/** + * @defgroup powerpc_iftsecpub Low-level Driver API + * + * @ingroup powerpc_mvme3100 + * + * @brief This API provides driver access to applications that + * want to use e.g., the second ethernet interface + * independently from the BSD TCP/IP stack. E.g., for + * raw ethernet packet communication... + */ + +#define TSEC_TXIRQ ( (1<<(31-9)) | (1<<(31-11)) ) +#define TSEC_RXIRQ ( (1<<(31-0)) | (1<<(31- 3)) | (1<<(31-24)) ) +#define TSEC_LKIRQ ( 1<<(31- 4) ) +/* + * Setup an interface. + * Allocates resources for descriptor rings and sets up the driver software structure. + * + * Arguments: + * unit: + * interface # (1..2). The interface must not be attached to BSD already. + * + * driver_tid: + * ISR posts RTEMS event # ('unit' - 1) to task with ID 'driver_tid' and disables interrupts + * from this interface. + * + * void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred): + * Pointer to user-supplied callback to release a buffer that had been sent + * by BSP_tsec_send_buf() earlier. The callback is passed 'cleanup_txbuf_arg' + * and a flag indicating whether the send had been successful. + * The driver no longer accesses 'user_buf' after invoking this callback. + * CONTEXT: This callback is executed either by BSP_tsec_swipe_tx() or + * BSP_tsec_send_buf(), BSP_tsec_init_hw(), BSP_tsec_stop_hw() (the latter + * ones calling BSP_tsec_swipe_tx()). + * void *cleanup_txbuf_arg: + * Closure argument that is passed on to 'cleanup_txbuf()' callback; + * + * void *(*alloc_rxbuf)(int *p_size, uintptr_t *p_data_addr), + * Pointer to user-supplied callback to allocate a buffer for subsequent + * insertion into the RX ring by the driver. + * RETURNS: opaque handle to the buffer (which may be a more complex object + * such as an 'mbuf'). The handle is not used by the driver directly + * but passed back to the 'consume_rxbuf()' callback. + * Size of the available data area and pointer to buffer's data area + * in '*psize' and '*p_data_area', respectively. + * If no buffer is available, this routine should return NULL in which + * case the driver drops the last packet and re-uses the last buffer + * instead of handing it out to 'consume_rxbuf()'. + * CONTEXT: Called when initializing the RX ring (BSP_tsec_init_hw()) or when + * swiping it (BSP_tsec_swipe_rx()). + * + * + * void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len); + * Pointer to user-supplied callback to pass a received buffer back to + * the user. The driver no longer accesses the buffer after invoking this + * callback (with 'len'>0, see below). 'user_buf' is the buffer handle + * previously generated by 'alloc_rxbuf()'. + * The callback is passed 'cleanup_rxbuf_arg' and a 'len' + * argument giving the number of bytes that were received. + * 'len' may be <=0 in which case the 'user_buf' argument is NULL. + * 'len' == 0 means that the last 'alloc_rxbuf()' had failed, + * 'len' < 0 indicates a receiver error. In both cases, the last packet + * was dropped/missed and the last buffer will be re-used by the driver. + * NOTE: the data are 'prefixed' with two bytes, i.e., the ethernet packet header + * is stored at offset 2 in the buffer's data area. Also, the FCS (4 bytes) + * is appended. 'len' accounts for both. + * CONTEXT: Called from BSP_tsec_swipe_rx(). + * void *cleanup_rxbuf_arg: + * Closure argument that is passed on to 'consume_rxbuf()' callback; + * + * rx_ring_size, tx_ring_size: + * How many big to make the RX and TX descriptor rings. Note that the sizes + * may be 0 in which case a reasonable default will be used. + * If either ring size is < 0 then the RX or TX will be disabled. + * Note that it is illegal in this case to use BSP_tsec_swipe_rx() or + * BSP_tsec_swipe_tx(), respectively. + * + * irq_mask: + * Interrupts to enable. OR of flags from above. + * + */ +struct tsec_private * +BSP_tsec_setup( + int unit, + rtems_id driver_tid, + void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred), + void * cleanup_txbuf_arg, + void * (*alloc_rxbuf)(int *p_size, uintptr_t *p_data_addr), + void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len), + void * consume_rxbuf_arg, + int rx_ring_size, + int tx_ring_size, + int irq_mask +); + +/* + * Alternate 'setup' routine allowing the user to install an ISR rather + * than a task ID. + * All parameters (other than 'isr' / 'isr_arg') and the return value + * are identical to the BSP_tsec_setup() entry point. + */ +struct tsec_private * +BSP_tsec_setup_1( + int unit, + void (*isr)(void *isr_arg), + void * isr_arg, + void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred), + void * cleanup_txbuf_arg, + void * (*alloc_rxbuf)(int *p_size, uintptr_t *p_data_addr), + void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len), + void * consume_rxbuf_arg, + int rx_ring_size, + int tx_ring_size, + int irq_mask +); + + +/* + * Descriptor scavenger; cleanup the TX ring, passing all buffers + * that have been sent to the cleanup_tx() callback. + * This routine is called from BSP_tsec_send_buf(), BSP_tsec_init_hw(), + * BSP_tsec_stop_hw(). + * + * RETURNS: number of buffers processed. + */ + +int +BSP_tsec_swipe_tx(struct tsec_private *mp); + + +/* + * Reset statistics counters. + */ +void +BSP_tsec_reset_stats(struct tsec_private *mp); + +/* + * Initialize interface hardware + * + * 'mp' handle obtained by from BSP_tsec_setup(). + * 'promisc' whether to set promiscuous flag. + * 'enaddr' pointer to six bytes with MAC address. Read + * from the device if NULL. + * NOTE: multicast filter is cleared by this routine. + */ +void +BSP_tsec_init_hw(struct tsec_private *mp, int promisc, unsigned char *enaddr); + +/* + * Clear multicast hash filter. No multicast frames are accepted + * after executing this routine (unless the hardware was initialized + * in 'promiscuous' mode). + * + * Reset reference count for all hash-table entries + * to zero (see BSP_tsec_mcast_filter_accept_del()). + */ +void +BSP_tsec_mcast_filter_clear(struct tsec_private *mp); + +/* + * Program multicast filter to accept all multicast frames. + * + * Increment reference count for all hash-table entries + * by one (see BSP_tsec_mcast_filter_accept_del()). + */ +void +BSP_tsec_mcast_filter_accept_all(struct tsec_private *mp); + +/* + * Add a MAC address to the multicast filter and increment + * the reference count for the matching hash-table entry + * (see BSP_tsec_mcast_filter_accept_del()). + * + * Existing entries are not changed but note that + * the filter is imperfect, i.e., multiple MAC addresses + * may alias to a single filter entry. Hence software + * filtering must still be performed. + * + */ +void +BSP_tsec_mcast_filter_accept_add(struct tsec_private *mp, unsigned char *enaddr); + +/* + * Remove a MAC address from the (imperfec) multicast + * filter. + * Note that the driver maintains an internal reference + * counter for each multicast hash. The hash-table + * entry is only cleared when the reference count + * reaches zero ('del' has been called the same + * amount of times as 'add' for an address (or + * any alias) that matches a given table entry. + * BSP_tsec_mcast_filter_clear() resets all reference + * counters to zero. + */ +void +BSP_tsec_mcast_filter_accept_del(struct tsec_private *mp, unsigned char *enaddr); + +/* + * Dump statistics to FILE 'f'. If NULL, stdout is used. + */ +void +BSP_tsec_dump_stats(struct tsec_private *mp, FILE *f); + +/* + * Shutdown hardware and clean out the rings + */ +void +BSP_tsec_stop_hw(struct tsec_private *mp); + +/* + * calls BSP_tsec_stop_hw(), releases all resources and marks the interface + * as unused. + * RETURNS 0 on success, nonzero on failure. + * NOTE: the handle MUST NOT be used after successful execution of this + * routine. + */ +int +BSP_tsec_detach(struct tsec_private *mp); + +/* + * Enqueue a mbuf chain or a raw data buffer for transmission; + * RETURN: #bytes sent or -1 if there are not enough free descriptors + * + * If 'len' is <=0 then 'm_head' is assumed to point to a mbuf chain. + * OTOH, a raw data packet (or a different type of buffer) + * may be sent (non-BSD driver) by pointing data_p to the start of + * the data and passing 'len' > 0. + * 'm_head' is passed back to the 'cleanup_txbuf()' callback. + * + * Comments: software cache-flushing incurs a penalty if the + * packet cannot be queued since it is flushed anyways. + * The algorithm is slightly more efficient in the normal + * case, though. + * + * RETURNS: # bytes enqueued to device for transmission or -1 if no + * space in the TX ring was available. + */ + +int +BSP_tsec_send_buf(struct tsec_private *mp, void *m_head, void *data_p, int len); + +/* + * Retrieve all received buffers from the RX ring, replacing them + * by fresh ones (obtained from the alloc_rxbuf() callback). The + * received buffers are passed to consume_rxbuf(). + * + * RETURNS: number of buffers processed. + */ +int +BSP_tsec_swipe_rx(struct tsec_private *mp); + +/* read ethernet address from hw to buffer */ +void +BSP_tsec_read_eaddr(struct tsec_private *mp, unsigned char *eaddr); + +/* Read MII register */ +uint32_t +BSP_tsec_mdio_rd(struct tsec_private *mp, unsigned reg); + +/* Write MII register */ +int +BSP_tsec_mdio_wr(struct tsec_private *mp, unsigned reg, uint32_t val); + +/* + * read/write media word. + * 'cmd': can be SIOCGIFMEDIA, SIOCSIFMEDIA, 0 or 1. The latter + * are aliased to the former for convenience. + * 'parg': pointer to media word. + * + * RETURNS: 0 on success, nonzero on error + */ +int +BSP_tsec_media_ioctl(struct tsec_private *mp, int cmd, int *parg); + +/* Interrupt related routines */ + +/* + * When it comes to interrupts the chip has two rather + * annoying features: + * 1 once an IRQ is pending, clearing the IMASK does not + * de-assert the interrupt line. + * 2 the chip has three physical interrupt lines even though + * all events are reported in a single register. Rather + * useless; we must hook 3 ISRs w/o any real benefit. + * In fact, it makes our life a bit more difficult: + * + * Hence, for (1) we would have to mask interrupts at the PIC + * but to re-enable them we would have to do that three times + * because of (2). + * + * Therefore, we take the following approach: + * + * ISR masks all interrupts on the TSEC, acks/clears them + * and stores the acked irqs in the device struct where + * it is picked up by BSP_tsec_ack_irqs(). + * Since all interrupts are disabled until the daemon + * re-enables them after calling BSP_tsec_ack_irqs() + * no interrupts are lost. + * + * BUT: NO isr (including PHY isrs) MUST INTERRUPT ANY + * OTHER ONE, i.e., they all must have the same + * priority. Otherwise, integrity of the cached + * irq_pending variable may be compromised. + */ + +/* Note: the BSP_tsec_enable/disable/ack_irqs() entry points + * are deprecated. + * The newer API where the user passes a mask allows + * for more selective control. + */ + +/* Enable interrupts at device */ +void +BSP_tsec_enable_irqs(struct tsec_private *mp); + +/* Disable interrupts at device */ +void +BSP_tsec_disable_irqs(struct tsec_private *mp); + +/* + * Acknowledge (and clear) interrupts. + * RETURNS: interrupts that were raised. + */ +uint32_t +BSP_tsec_ack_irqs(struct tsec_private *mp); + +/* Enable interrupts included in 'mask' (leaving + * already enabled interrupts on). If the mask includes + * bits that were not passed to the 'setup' routine then + * the behavior is undefined. + */ +void +BSP_tsec_enable_irq_mask(struct tsec_private *mp, uint32_t irq_mask); + +/* Disable interrupts included in 'mask' (leaving + * other ones that are currently enabled on). If the mask + * includes bits that were not passed to the 'setup' routine + * then the behavior is undefined. + + * RETURNS: Bitmask of interrupts that were enabled upon entry + * into this routine. This can be used to restore the previous + * state. + */ +uint32_t +BSP_tsec_disable_irq_mask(struct tsec_private *mp, uint32_t irq_mask); + +/* Acknowledge and clear selected interrupts. + * + * RETURNS: All pending interrupts. + * + * NOTE: Only pending interrupts contained in 'mask' + * are cleared. Others are left pending. + * + * This routine can be used to check for pending + * interrupts (pass mask == 0) or to clear all + * interrupts (pass mask == -1). + */ +uint32_t +BSP_tsec_ack_irq_mask(struct tsec_private *mp, uint32_t mask); + + +/* Retrieve the driver daemon TID that was passed to + * BSP_tsec_setup(). + */ + +rtems_id +BSP_tsec_get_tid(struct tsec_private *mp); + +struct tsec_private * +BSP_tsec_getp(unsigned index); + +/* + * + * Example driver task loop (note: no synchronization of + * buffer access shown!). + * RTEMS_EVENTx = 0,1 or 2 depending on IF unit. + * + * / * setup (obtain handle) and initialize hw here * / + * + * do { + * / * ISR disables IRQs and posts event * / + * rtems_event_receive( RTEMS_EVENTx, RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &evs ); + * irqs = BSP_tsec_ack_irqs(handle); + * if ( irqs & BSP_TSEC_IRQ_TX ) { + * BSP_tsec_swipe_tx(handle); / * cleanup_txbuf() callback executed * / + * } + * if ( irqs & BSP_TSEC_IRQ_RX ) { + * BSP_tsec_swipe_rx(handle); / * alloc_rxbuf() and consume_rxbuf() executed * / + * } + * BSP_tsec_enable_irqs(handle); + * } while (1); + * + */ + +/* PUBLIC RTEMS BSDNET ATTACH FUNCTION */ +struct rtems_bsdnet_ifconfig; + +int +rtems_tsec_attach(struct rtems_bsdnet_ifconfig *ifcfg, int attaching); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/mvme3100/include/bsp/irq.h b/bsps/powerpc/mvme3100/include/bsp/irq.h new file mode 100644 index 0000000000..0158e05149 --- /dev/null +++ b/bsps/powerpc/mvme3100/include/bsp/irq.h @@ -0,0 +1,137 @@ +/** + * @file + * + * @ingroup powerpc_irq + * + * @brief This include file describe the data structure and the functions + * implemented by RTEMS to write interrupt handlers. + */ + +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by RTEMS to write interrupt handlers. + * + * Copyright (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Adapted for the mvme3100 BSP by T. Straumann, 2007. + */ + +#ifndef BSP_POWERPC_IRQ_H +#define BSP_POWERPC_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup powerpc_irq Definitions + * + * @ingroup powerpc_mvme3100 + * + * @brief rtems_irq_number Definitions + */ + +/* Must pad number of external sources to 16 because + * of the layout of vector/priority registers in the + * 8540's openpic where there is a gap between + * registers corresponding to external and core sources. + */ +#define BSP_EXT_IRQ_NUMBER (16) +#define BSP_CORE_IRQ_NUMBER (32) + +/* openpic glue code from shared/irq assigns priorities and configures + * initial ISRs for BSP_PCI_IRQ_NUMBER entries (plus ISA stuff on legacy + * boards). Hence PCI_IRQ_NUMBER must also cover the internal sources + * even though they have nothing to do with PCI. + */ +#define BSP_PCI_IRQ_NUMBER (BSP_EXT_IRQ_NUMBER + BSP_CORE_IRQ_NUMBER) +#define BSP_PCI_IRQ_LOWEST_OFFSET (0) +#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) + +#define BSP_CORE_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_EXT_IRQ_NUMBER) +#define BSP_CORE_IRQ_MAX_OFFSET (BSP_CORE_IRQ_LOWEST_OFFSET + BSP_CORE_IRQ_NUMBER - 1) + +/* + * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt + * handler might be connected + */ +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CORE_IRQ_MAX_OFFSET + 1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) +/* Misc vectors for OPENPIC irqs (IPI, timers) + */ +#define BSP_MISC_IRQ_NUMBER (8) +#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) +#define BSP_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) + +/* + * Some PCI IRQ symbolic name definition + */ +#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET) + +#define BSP_VME0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 0) +#define BSP_VME1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1) +#define BSP_VME2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2) +#define BSP_VME3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3) + +#define BSP_ABORT_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8) +#define BSP_TEMP_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9) +#define BSP_PHY_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10) +#define BSP_RTC_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 11) + +/* Weird - they provide 3 different IRQ lines per ethernet controller + * but only one shared line for 2 UARTs ??? + */ +#define BSP_UART_COM1_IRQ (BSP_CORE_IRQ_LOWEST_OFFSET + 26) +#define BSP_UART_COM2_IRQ (BSP_CORE_IRQ_LOWEST_OFFSET + 26) +#define BSP_I2C_IRQ (BSP_CORE_IRQ_LOWEST_OFFSET + 27) + +/* + * Some internal (CORE) name definitions + */ +/* Ethernet (FEC) */ +#define BSP_CORE_IRQ_FEC (BSP_CORE_IRQ_LOWEST_OFFSET + 25) +/* i2c controller */ +#define BSP_CORE_IRQ_I2C (BSP_CORE_IRQ_LOWEST_OFFSET + 27) + +/* + * Some Processor execption handled as RTEMS IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) + +/*-------------------------------------------------------------------------+ +| Function Prototypes. ++--------------------------------------------------------------------------*/ + +extern void BSP_rtems_irq_mng_init(unsigned cpuId); + +#include + +#ifdef __cplusplus +}; +#endif + +#endif +#endif diff --git a/bsps/powerpc/mvme3100/include/bsp/mpc8540_i2c_busdrv.h b/bsps/powerpc/mvme3100/include/bsp/mpc8540_i2c_busdrv.h new file mode 100644 index 0000000000..181b45f468 --- /dev/null +++ b/bsps/powerpc/mvme3100/include/bsp/mpc8540_i2c_busdrv.h @@ -0,0 +1,72 @@ +/** + * @file + * + * @ingroup powerpc_mpc8540i2cbusdrv + * + * @brief I2C bus driver for mpc8540-based boards + */ + +#ifndef MPC8540_I2C_BUS_DRIVER_H +#define MPC8540_I2C_BUS_DRIVER_H + +/* + * Authorship + * ---------- + * This software ('mvme3100' RTEMS BSP) was created by + * + * Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'mvme3100' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#include +#include + +/* for registration with libi2c */ +extern rtems_libi2c_bus_t *mpc8540_i2c_bus_descriptor; + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/bsps/powerpc/mvme3100/include/tm27.h b/bsps/powerpc/mvme3100/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/mvme3100/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/powerpc/mvme5500/headers.am b/bsps/powerpc/mvme5500/headers.am new file mode 100644 index 0000000000..94c03a6982 --- /dev/null +++ b/bsps/powerpc/mvme5500/headers.am @@ -0,0 +1,21 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/GT64260TWSI.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/GT64260eth.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/GT64260ethreg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/VMEConfig.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/VPD.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/bspException.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/bspMvme5500.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/gtpcireg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/gtreg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/if_wmreg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/pcireg.h diff --git a/bsps/powerpc/mvme5500/include/bsp.h b/bsps/powerpc/mvme5500/include/bsp.h new file mode 100644 index 0000000000..c1b17cee10 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp.h @@ -0,0 +1,206 @@ +/* + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * (C) S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP. + */ + +#ifndef LIBBSP_POWERPC_MVME5500_BSP_H +#define LIBBSP_POWERPC_MVME5500_BSP_H + +#ifndef ASM + +#include +#include + +#include +#include +#include + +/* Board type */ +typedef enum { + undefined = 0, + MVME5500, + MVME6100 +} BSP_BoardTypes; + +BSP_BoardTypes BSP_getBoardType(void); + +/* Board type */ +typedef enum { + Undefined, + UNIVERSE2, + TSI148, +} BSP_VMEchipTypes; + +BSP_VMEchipTypes BSP_getVMEchipType(void); + +/* The version of Discovery system controller */ + +typedef enum { + notdefined, + GT64260A, + GT64260B, + MV64360, +} DiscoveryChipVersion; + +DiscoveryChipVersion BSP_getDiscoveryChipVersion(void); + +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define GT64x60_REG_BASE 0xf1000000 /* Base of GT64260 Reg Space */ +#define GT64x60_REG_SPACE_SIZE 0x10000 /* 64Kb Internal Reg Space */ + +#define GT64x60_DEV1_BASE 0xf1100000 /* Device bank1(chip select 1) base + */ +#define GT64260_DEV1_SIZE 0x00100000 /* Device bank size */ + +/* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */ +#define _IO_BASE GT64x60_REG_BASE + +#define BSP_NVRAM_BASE_ADDR 0xf1110000 + +#define BSP_RTC_INTA_REG 0x7ff0 +#define BSP_RTC_SECOND 0x7ff2 +#define BSP_RTC_MINUTE 0x7ff3 +#define BSP_RTC_HOUR 0x7ff4 +#define BSP_RTC_DATE 0x7ff5 +#define BSP_RTC_INTERRUPTS 0x7ff6 +#define BSP_RTC_WATCHDOG 0x7ff7 + +/* PCI0 Domain I/O space */ +#define PCI0_IO_BASE 0xf0000000 +#define PCI1_IO_BASE 0xf0800000 + +/* PCI 0 memory space as seen from the CPU */ +#define PCI0_MEM_BASE 0x80000000 +#define PCI_MEM_BASE 0 /* glue for vmeUniverse */ +#define PCI_MEM_BASE_ADJUSTMENT 0 + +/* address of our ram on the PCI bus */ +#define PCI_DRAM_OFFSET 0 + +/* PCI 1 memory space as seen from the CPU */ +#define PCI1_MEM_BASE 0xe0000000 +#define PCI1_MEM_SIZE 0x10000000 + +/* Needed for hot adding via PMCspan on the PCI0 local bus. + * This is board dependent, only because mvme5500 + * supports hot adding and has more than one local PCI + * bus. + */ +#define BSP_MAX_PCI_BUS_ON_PCI0 8 +#define BSP_MAX_PCI_BUS_ON_PCI1 2 +#define BSP_MAX_PCI_BUS (BSP_MAX_PCI_BUS_ON_PCI0+BSP_MAX_PCI_BUS_ON_PCI1) + + +/* The glues to Till's vmeUniverse, although the name does not + * actually reflect the relevant architect of the MVME5500. + */ +#define BSP_PCI_IRQ0 BSP_GPP_IRQ_LOWEST_OFFSET + +/* + * confdefs.h overrides for this BSP: + * - Interrupt stack space is not minimum if defined. + */ +#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) /* 2/09 wants it to be adjustable by BSP */ + +/* uart.c uses out_8 instead of outb */ +#define BSP_UART_IOBASE_COM1 GT64x60_DEV1_BASE + 0x20000 +#define BSP_UART_IOBASE_COM2 GT64x60_DEV1_BASE + 0x21000 + +#define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ +#define BSP_UART_BAUD_BASE 115200 + +/* + * Total memory using RESIDUAL DATA + */ +extern unsigned int BSP_mem_size; +/* + * PCI Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * processor clock frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; + +#define BSP_Convert_decrementer( _value ) \ + ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) + +extern void bsp_reset(void); +/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ +extern int BSP_disconnect_clock_handler(void); +extern int BSP_connect_clock_handler(void); + +unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); + +/* + * Prototypes for methods called only from .S for dependency tracking + */ +char *save_boot_params( + void *r3, + void *r4, + void *r5, + char *cmdline_start, + char *cmdline_end +); +void zero_bss(void); + +/* + * Prototypes for methods in the BSP that cross file boundaries + */ +uint32_t probeMemoryEnd(void); +void pci_interface(void); +void BSP_printPicIsrTbl(void); +int I2Cread_eeprom( + unsigned char I2cBusAddr, + uint32_t devA2A1A0, + uint32_t AddrBytes, + unsigned char *pBuff, + uint32_t numBytes +); + +#if 0 +#define RTEMS_BSP_NETWORK_DRIVER_NAME "gt1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_GT64260eth_driver_attach +#else +#define RTEMS_BSP_NETWORK_DRIVER_NAME "wmG1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_i82544EI_driver_attach +#endif + +extern int RTEMS_BSP_NETWORK_DRIVER_ATTACH(); + +#define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER() + +static inline void lwmemBar(void) +{ + __asm__ volatile("lwsync":::"memory"); +} + +static inline void io_flush(void) +{ + __asm__ volatile("isync":::"memory"); +} + +static inline void memBar(void) +{ + __asm__ volatile("sync":::"memory"); +} + +static inline void ioBar(void) +{ + __asm__ volatile("eieio":::"memory"); +} + +#endif + +#endif /* !ASM */ diff --git a/bsps/powerpc/mvme5500/include/bsp/GT64260TWSI.h b/bsps/powerpc/mvme5500/include/bsp/GT64260TWSI.h new file mode 100644 index 0000000000..1377e6f607 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/GT64260TWSI.h @@ -0,0 +1,20 @@ +#ifndef __GT64260TWSI_h +#define __GT64260TWSI_h + +/* GT64260TWSI.h - header for the GT64260 Two-Wire Serial Interface */ + +/* TWSI Control Register Bits */ +#define TWSI_ACK 4 +#define TWSI_INTFLG 8 +#define TWSI_STOP 0x10 +#define TWSI_START 0x20 +#define TWSI_TWSIEN 0x40 +#define TWSI_INTEN 0x80 + +void GT64260TWSIinit(void); +int GT64260TWSIstart(void); +int GT64260TWSIwrite(unsigned char Data); +int GT64260TWSIread(unsigned char *, int lastByte); +int GT64260TWSIstop(void); + +#endif diff --git a/bsps/powerpc/mvme5500/include/bsp/GT64260eth.h b/bsps/powerpc/mvme5500/include/bsp/GT64260eth.h new file mode 100644 index 0000000000..2703bb423e --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/GT64260eth.h @@ -0,0 +1,140 @@ +/* GT64260eth.h + * + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. + * + * RTEMS/Mvme5500 port 2004 by S. Kate Feng, , + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* Keep the ring sizes a power of two for efficiency. + Making the Tx ring too long decreases the effectiveness of channel + bonding and packet priority. + There are no ill effects from too-large receive rings. */ +#define TX_RING_SIZE 32 +#define GT_NEXTTX(x) ((x + 1) % TX_RING_SIZE ) +#define TX_QUARTER_FULL TX_RING_SIZE/2 +#define TX_HALF_FULL TX_RING_SIZE/2 +#define RX_RING_SIZE 16 +#define HASH_TABLE_SIZE 16 +#define HASH_DRAM_SIZE HASH_TABLE_SIZE*1024 /* size of DRAM for hash table */ +#define INTR_ERR_SIZE 16 + +enum GTeth_txprio { + GE_TXPRIO_HI=1, + GE_TXPRIO_LO=0, + GE_TXPRIO_NONE=2 +}; +enum GTeth_rxprio { + GE_RXPRIO_HI=3, + GE_RXPRIO_MEDHI=2, + GE_RXPRIO_MEDLO=1, + GE_RXPRIO_LO=0 +}; + +struct GTeth_softc { + struct GTeth_desc txq_desc[TX_RING_SIZE]; /* transmit descriptor memory */ + struct GTeth_desc rxq_desc[RX_RING_SIZE]; /* receive descriptor memory */ + struct mbuf* txq_mbuf[TX_RING_SIZE]; /* transmit buffer memory */ + struct mbuf* rxq_mbuf[RX_RING_SIZE]; /* receive buffer memory */ + struct GTeth_softc *next_module; + volatile unsigned int intr_errsts[INTR_ERR_SIZE]; /* capture the right intr_status */ + unsigned int intr_err_ptr1; /* ptr used in GTeth_error() */ + unsigned int intr_err_ptr2; /* ptr used in ISR */ + struct ifqueue txq_pendq; /* these are ready to go to the GT */ + unsigned int txq_pending; + unsigned int txq_lo; /* next to be given to GT DMA */ + unsigned int txq_fi; /* next to be free */ + unsigned int txq_to_cpu; /* next to be returned to CPU */ + unsigned int txq_ei_gapcount; /* counter until next EI */ + unsigned int txq_nactive; /* number of active descriptors */ + unsigned int txq_nintr; /* number of txq desc. send TX_EVENT */ + unsigned int txq_outptr; /* where to put next transmit packet */ + unsigned int txq_inptr; /* start of 1st queued tx packet */ + unsigned int txq_free; /* free Tx queue slots. */ + unsigned txq_intrbits; /* bits to write to EIMR */ + unsigned txq_esdcmrbits; /* bits to write to ESDCMR */ + unsigned txq_epsrbits; /* bits to test with EPSR */ + + caddr_t txq_ectdp; /* offset to cur. tx desc ptr reg */ + unsigned long txq_desc_busaddr; /* bus addr of tx descriptors */ + caddr_t txq_buf_busaddr; /* bus addr of tx buffers */ + + struct mbuf *rxq_curpkt; /* mbuf for current packet */ + struct GTeth_desc *rxq_head_desc; /* rxq head descriptor */ + unsigned int rxq_fi; /* next to be returned to CPU */ + unsigned int rxq_active; /* # of descriptors given to GT */ + unsigned rxq_intrbits; /* bits to write to EIMR */ + unsigned long rxq_desc_busaddr; /* bus addr of rx descriptors */ + + struct arpcom arpcom; /* rtems if structure, contains ifnet */ + int sc_macno; /* which mac? 0, 1, or 2 */ + + unsigned int sc_tickflags; + #define GE_TICK_TX_IFSTART 0x0001 + #define GE_TICK_RX_RESTART 0x0002 + unsigned int sc_flags; + #define GE_ALLMULTI 0x0001 + #define GE_PHYSTSCHG 0x0002 + #define GE_RXACTIVE 0x0004 + unsigned sc_pcr; /* current EPCR value */ + unsigned sc_pcxr; /* current EPCXR value */ + unsigned sc_intrmask; /* current EIMR value */ + unsigned sc_idlemask; /* suspended EIMR bits */ + unsigned sc_max_frame_length; /* maximum frame length */ + unsigned rx_buf_sz; + + /* Hash table related members */ + unsigned long long *sc_hashtable; + unsigned int sc_hashmask; /* 0x1ff or 0x1fff */ + + rtems_id daemonTid; + rtems_id daemonSync; /* synchronization with the daemon */ + /* statistics */ + struct { + volatile unsigned long rxInterrupts; + + volatile unsigned long txInterrupts; + unsigned long txMultiBuffPacket; + unsigned long txMultiMaxLen; + unsigned long txSinglMaxLen; + unsigned long txMultiMaxLoop; + unsigned long txBuffMaxLen; + unsigned long length_errors; + unsigned long frame_errors; + unsigned long crc_errors; + unsigned long or_errors; /* overrun error */ + } stats; +}; diff --git a/bsps/powerpc/mvme5500/include/bsp/GT64260ethreg.h b/bsps/powerpc/mvme5500/include/bsp/GT64260ethreg.h new file mode 100644 index 0000000000..d9081ccb53 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/GT64260ethreg.h @@ -0,0 +1,879 @@ +/* $NetBSD: GT64260ethreg.h,v 1.2 2003/03/17 16:41:16 matt Exp $ */ + +/* + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_GTETHREG_H_ +#define _DEV_GTETHREG_H_ + +#define ETH__BIT(bit) (1U << (bit)) +#define ETH__LLBIT(bit) (1ULL << (bit)) +#define ETH__MASK(bit) (ETH__BIT(bit) - 1) +#define ETH__LLMASK(bit) (ETH__LLBIT(bit) - 1) +#define ETH__GEN(n, off) (0x2400+((n) << 10)+(ETH__ ## off)) +#define ETH__EXT(data, bit, len) (((data) >> (bit)) & ETH__MASK(len)) +#define ETH__LLEXT(data, bit, len) (((data) >> (bit)) & ETH__LLMASK(len)) +#define ETH__CLR(data, bit, len) ((data) &= ~(ETH__MASK(len) << (bit))) +#define ETH__INS(new, bit) ((new) << (bit)) +#define ETH__LLINS(new, bit) ((unsigned long long)(new) << (bit)) + +/* + * Descriptors used for both receive & transmit data. Note that the descriptor + * must start on a 4LW boundary. Since the GT accesses the descriptor as + * two 64-bit quantities, we must present them 32bit quantities in the right + * order based on endianess. + */ + +struct GTeth_desc { +#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN /* for mvme5500 */ + unsigned ed_lencnt; /* Buffer size is hi 16 bits; Byte count (rx) is lo 16 */ + unsigned ed_cmdsts; /* command (hi16)/status (lo16) bits */ + unsigned ed_nxtptr; /* next descriptor (must be 4LW aligned) */ + unsigned ed_bufptr; /* pointer to packet buffer */ +#endif +#if defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN + unsigned ed_cmdsts; /* command (hi16)/status (lo16) bits */ + unsigned ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */ + unsigned ed_bufptr; /* pointer to packet buffer */ + unsigned ed_nxtptr; /* next descriptor (must be 4LW aligned) */ +#endif +}; + +/* Ethernet 0 address control (Low), Offset: 0xf200 */ +#define RxBSnoopEn ETH__BIT(6) /* Rx buffer snoop enable,1=enable*/ +#define TxBSnoopEn ETH__BIT(14) /* Tx buffer snoop enable */ +#define RxDSnoopEn ETH__BIT(22) /* Rx descriptor snoop enable */ +#define TxDSnoopEn ETH__BIT(30) /* Tx descriptor snoop enable */ + +/* Ethernet 0 address control (High), Offset: 0xf204 */ +#define HashSnoopEn ETH__BIT(6) /* Hash Table snoop enable */ + +/* */ +#define GT_CUU_Eth0_AddrCtrlLow 0xf200 +#define GT_CUU_Eth0_AddrCtrlHigh 0xf204 + +/* Table 578: Ethernet TX Descriptor - Command/Status word + * All bits except F, EI, AM, O are only valid if TX_CMD_L is also set, + * otherwise should be 0 (tx). + */ + +#define TX_STS_LC ETH__BIT(5) /* Late Collision */ +#define TX_STS_UR ETH__BIT(6) /* Underrun error */ +#define TX_STS_RL ETH__BIT(8) /* Retransmit Limit (excession coll) */ +#define TX_STS_COL ETH__BIT(9) /* Collision Occurred */ +#define TX_STS_RC(v) ETH__GETBITS(v, 10, 4) /* Retransmit Count */ +#define TX_STS_ES ETH__BIT(15) /* Error Summary (LC|UR|RL) */ +#define TX_CMD_L ETH__BIT(16) /* Last - End Of Packet */ +#define TX_CMD_F ETH__BIT(17) /* First - Start Of Packet */ +#define TX_CMD_P ETH__BIT(18) /* Pad Packet */ +#define TX_CMD_GC ETH__BIT(22) /* Generate CRC */ +#define TX_CMD_EI ETH__BIT(23) /* Enable Interrupt */ +#define TX_CMD_AM ETH__BIT(30) /* Auto Mode */ +#define TX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */ + +#define TX_CMD_FIRST (TX_CMD_F|TX_CMD_O) +#define TX_CMD_LAST (TX_CMD_L|TX_CMD_GC|TX_CMD_P|TX_CMD_O) + +/* Table 608: Ethernet RX Descriptor - Command/Status Word + * All bits except F, EI, AM, O are only valid if RX_CMD_L is also set, + * otherwise should be ignored (rx). + */ +#define RX_STS_CE ETH__BIT(0) /* CRC Error */ +#define RX_STS_COL ETH__BIT(1) /* Collision sensed during reception */ +#define RX_STS_LC ETH__BIT(5) /* Late Collision (Reserved) */ +#define RX_STS_OR ETH__BIT(6) /* Overrun Error */ +#define RX_STS_MFL ETH__BIT(7) /* Max Frame Len Error */ +#define RX_STS_SF ETH__BIT(8) /* Short Frame Error (< 64 bytes) */ +#define RX_STS_FT ETH__BIT(11) /* Frame Type (1 = 802.3) */ +#define RX_STS_M ETH__BIT(12) /* Missed Frame */ +#define RX_STS_HE ETH__BIT(13) /* Hash Expired (manual match) */ +#define RX_STS_IGMP ETH__BIT(14) /* IGMP Packet */ +#define RX_STS_ES ETH__BIT(15) /* Error Summary (CE|COL|LC|OR|MFL|SF) */ +#define RX_CMD_L ETH__BIT(16) /* Last - End Of Packet */ +#define RX_CMD_F ETH__BIT(17) /* First - Start Of Packet */ +#define RX_CMD_EI ETH__BIT(23) /* Enable Interrupt */ +#define RX_CMD_AM ETH__BIT(30) /* Auto Mode */ +#define RX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */ + +/* Table 586: Hash Table Entry Fields + */ +#define HSH_V ETH__LLBIT(0) /* Entry is valid */ +#define HSH_S ETH__LLBIT(1) /* Skip this entry */ +#define HSH_RD ETH__LLBIT(2) /* Receive(1) / Discard (0) */ +#define HSH_R ETH__LLBIT(2) /* Receive(1) */ +#define HSH_PRIO_GET(v) ETH__LLEXT(v, 51, 2) +#define HSH_PRIO_INS(v) ETH__LLINS(v, 51) +#define HSH_ADDR_MASK 0x7fffff8LLU +#define HSH_LIMIT 12 + + +#define ETH_EPAR 0x2000 /* PHY Address Register */ +#define ETH_ESMIR 0x2010 /* SMI Register */ + +#define ETH_BASE_ETH0 0x2400 /* Ethernet0 Register Base */ +#define ETH_BASE_ETH1 0x2800 /* Ethernet1 Register Base */ +#define ETH_BASE_ETH2 0x2c00 /* Ethernet2 Register Base */ +#define ETH_SIZE 0x0400 /* Register Space */ + +#define ETH__EBASE 0x0000 /* Base of Registers */ +#define ETH__EPCR 0x0000 /* Port Config. Register */ +#define ETH__EPCXR 0x0008 /* Port Config. Extend Reg */ +#define ETH__EPCMR 0x0010 /* Port Command Register */ +#define ETH__EPSR 0x0018 /* Port Status Register */ +#define ETH__ESPR 0x0020 /* Port Serial Parameters Reg */ +#define ETH__EHTPR 0x0028 /* Port Hash Table Pointer Reg*/ +#define ETH__EFCSAL 0x0030 /* Flow Control Src Addr Low */ +#define ETH__EFCSAH 0x0038 /* Flow Control Src Addr High */ +#define ETH__ESDCR 0x0040 /* SDMA Configuration Reg */ +#define ETH__ESDCMR 0x0048 /* SDMA Command Register */ +#define ETH__EICR 0x0050 /* Interrupt Cause Register */ +#define ETH__EIMR 0x0058 /* Interrupt Mask Register */ +#define ETH__EFRDP0 0x0080 /* First Rx Desc Pointer 0 */ +#define ETH__EFRDP1 0x0084 /* First Rx Desc Pointer 1 */ +#define ETH__EFRDP2 0x0088 /* First Rx Desc Pointer 2 */ +#define ETH__EFRDP3 0x008c /* First Rx Desc Pointer 3 */ +#define ETH__ECRDP0 0x00a0 /* Current Rx Desc Pointer 0 */ +#define ETH__ECRDP1 0x00a4 /* Current Rx Desc Pointer 1 */ +#define ETH__ECRDP2 0x00a8 /* Current Rx Desc Pointer 2 */ +#define ETH__ECRDP3 0x00ac /* Current Rx Desc Pointer 3 */ +#define ETH__ECTDP0 0x00e0 /* Current Tx Desc Pointer 0 */ +#define ETH__ECTDP1 0x00e4 /* Current Tx Desc Pointer 1 */ +#define ETH__EDSCP2P0L 0x0060 /* IP Differentiated Services + CodePoint to Priority0 low */ +#define ETH__EDSCP2P0H 0x0064 /* IP Differentiated Services + CodePoint to Priority0 high*/ +#define ETH__EDSCP2P1L 0x0068 /* IP Differentiated Services + CodePoint to Priority1 low */ +#define ETH__EDSCP2P1H 0x006c /* IP Differentiated Services + CodePoint to Priority1 high*/ +#define ETH__EVPT2P 0x0068 /* VLAN Prio. Tag to Priority */ +#define ETH__EMIBCTRS 0x0100 /* MIB Counters */ + +/* SKF : we are only concerned with the Ethernet0 for the mvme5500 board */ +#define ETH0_EBASE 0x2400 /* Base of Registers */ +#define ETH0_EPCR 0x2400 /* Port Config. Register */ +#define ETH0_EPCXR 0x2408 /* Port Config. Extend Reg */ +#define ETH0_EPCMR 0x2410 /* Port Command Register */ +#define ETH0_EPSR 0x2418 /* Port Status Register */ +#define ETH0_ESPR 0x2420 /* Port Serial Parameters Reg */ +#define ETH0_EHTPR 0x2428 /* Port Hash Table Pointer Reg*/ +#define ETH0_EFCSAL 0x2430 /* Flow Control Src Addr Low */ +#define ETH0_EFCSAH 0x2438 /* Flow Control Src Addr High */ +#define ETH0_ESDCR 0x2440 /* SDMA Configuration Reg */ +#define ETH0_ESDCMR 0x2448 /* SDMA Command Register */ +#define ETH0_EICR 0x2450 /* Interrupt Cause Register */ +#define ETH0_EIMR 0x2458 /* Interrupt Mask Register */ +#define ETH0_EFRDP0 0x2480 /* First Rx Desc Pointer 0 */ +#define ETH0_EFRDP1 0x2484 /* First Rx Desc Pointer 1 */ +#define ETH0_EFRDP2 0x2488 /* First Rx Desc Pointer 2 */ +#define ETH0_EFRDP3 0x248c /* First Rx Desc Pointer 3 */ +#define ETH0_ECRDP0 0x24a0 /* Current Rx Desc Pointer 0 */ +#define ETH0_ECRDP1 0x24a4 /* Current Rx Desc Pointer 1 */ +#define ETH0_ECRDP2 0x24a8 /* Current Rx Desc Pointer 2 */ +#define ETH0_ECRDP3 0x24ac /* Current Rx Desc Pointer 3 */ +#define ETH0_ECTDP0 0x24e0 /* Current Tx Desc Pointer 0 */ +#define ETH0_ECTDP1 0x24e4 /* Current Tx Desc Pointer 1 */ +#define ETH0_EDSCP2P0L 0x2460 /* IP Differentiated Services + CodePoint to Priority0 low */ +#define ETH0_EDSCP2P0H 0x2464 /* IP Differentiated Services + CodePoint to Priority0 high*/ +#define ETH0_EDSCP2P1L 0x2468 /* IP Differentiated Services + CodePoint to Priority1 low */ +#define ETH0_EDSCP2P1H 0x246c /* IP Differentiated Services + CodePoint to Priority1 high*/ +#define ETH0_EVPT2P 0x2468 /* VLAN Prio. Tag to Priority */ +#define ETH0_EMIBCTRS 0x2500 /* MIB Counters */ + +#define ETH_BASE(n) ETH__GEN(n, EBASE) +#define ETH_EPCR(n) ETH__GEN(n, EPCR) /* Port Config. Register */ +#define ETH_EPCXR(n) ETH__GEN(n, EPCXR) /* Port Config. Extend Reg */ +#define ETH_EPCMR(n) ETH__GEN(n, EPCMR) /* Port Command Register */ +#define ETH_EPSR(n) ETH__GEN(n, EPSR) /* Port Status Register */ +#define ETH_ESPR(n) ETH__GEN(n, ESPR) /* Port Serial Parameters Reg */ +#define ETH_EHTPR(n) ETH__GEN(n, EHPTR) /* Port Hash Table Pointer Reg*/ +#define ETH_EFCSAL(n) ETH__GEN(n, EFCSAL) /* Flow Control Src Addr Low */ +#define ETH_EFCSAH(n) ETH__GEN(n, EFCSAH) /* Flow Control Src Addr High */ +#define ETH_ESDCR(n) ETH__GEN(n, ESDCR) /* SDMA Configuration Reg */ +#define ETH_ESDCMR(n) ETH__GEN(n, ESDCMR) /* SDMA Command Register */ +#define ETH_EICR(n) ETH__GEN(n, EICR) /* Interrupt Cause Register */ +#define ETH_EIMR(n) ETH__GEN(n, EIMR) /* Interrupt Mask Register */ +#define ETH_EFRDP0(n) ETH__GEN(n, EFRDP0) /* First Rx Desc Pointer 0 */ +#define ETH_EFRDP1(n) ETH__GEN(n, EFRDP1) /* First Rx Desc Pointer 1 */ +#define ETH_EFRDP2(n) ETH__GEN(n, EFRDP2) /* First Rx Desc Pointer 2 */ +#define ETH_EFRDP3(n) ETH__GEN(n, EFRDP3) /* First Rx Desc Pointer 3 */ +#define ETH_ECRDP0(n) ETH__GEN(n, ECRDP0) /* Current Rx Desc Pointer 0 */ +#define ETH_ECRDP1(n) ETH__GEN(n, ECRDP1) /* Current Rx Desc Pointer 1 */ +#define ETH_ECRDP2(n) ETH__GEN(n, ECRDP2) /* Current Rx Desc Pointer 2 */ +#define ETH_ECRDP3(n) ETH__GEN(n, ECRDP3) /* Current Rx Desc Pointer 3 */ +#define ETH_ECTDP0(n) ETH__GEN(n, ECTDP0) /* Current Tx Desc Pointer 0 */ +#define ETH_ECTDP1(n) ETH__GEN(n, ECTDP1) /* Current Tx Desc Pointer 1 */ +#define ETH_EDSCP2P0L(n) ETH__GEN(n, EDSCP2P0L) /* IP Differentiated Services + CodePoint to Priority0 low */ +#define ETH_EDSCP2P0H(n) ETH__GEN(n, EDSCP2P0H) /* IP Differentiated Services + CodePoint to Priority0 high*/ +#define ETH_EDSCP2P1L(n) ETH__GEN(n, EDSCP2P1L) /* IP Differentiated Services + CodePoint to Priority1 low */ +#define ETH_EDSCP2P1H(n) ETH__GEN(n, EDSCP1P1H) /* IP Differentiated Services + CodePoint to Priority1 high*/ +#define ETH_EVPT2P(n) ETH__GEN(n, EVPT2P) /* VLAN Prio. Tag to Priority */ +#define ETH_EMIBCTRS(n) ETH__GEN(n, EMIBCTRS) /* MIB Counters */ + +#define ETH_EPAR_PhyAD_GET(v, n) (((v) >> ((n) * 5)) & 0x1f) + +#define ETH_ESMIR_READ(phy, reg) (ETH__INS(phy, 16)|\ + ETH__INS(reg, 21)|\ + ETH_ESMIR_ReadOpcode) +#define ETH_ESMIR_WRITE(phy, reg, val) (ETH__INS(phy, 16)|\ + ETH__INS(reg, 21)|\ + ETH__INS(val, 0)|\ + ETH_ESMIR_WriteOpcode) +#define ETH_ESMIR_Value_GET(v) ETH__EXT(v, 0, 16) +#define ETH_ESMIR_WriteOpcode 0 +#define ETH_ESMIR_ReadOpcode ETH__BIT(26) +#define ETH_ESMIR_ReadValid ETH__BIT(27) +#define ETH_ESMIR_Busy ETH__BIT(28) + +/* + * Table 597: Port Configuration Register (PCR) + * 00:00 PM Promiscuous mode + * 0: Normal mode (Frames are only received if the + * destination address is found in the hash + * table) + * 1: Promiscuous mode (Frames are received + * regardless of their destination address. + * Errored frames are discarded unless the Port + * Configuration register's PBF bit is set) + * 01:01 RBM Reject Broadcast Mode + * 0: Receive broadcast address + * 1: Reject frames with broadcast address + * Overridden by the promiscuous mode. + * 02:02 PBF Pass Bad Frames + * (0: Normal mode, 1: Pass bad Frames) + * The Ethernet receiver passes to the CPU errored + * frames (like fragments and collided packets) + * that are normally rejected. + * NOTE: Frames are only passed if they + * successfully pass address filtering. + * 06:03 Reserved + * 07:07 EN Enable (0: Disabled, 1: Enable) + * When enabled, the ethernet port is ready to + * transmit/receive. + * 09:08 LPBK Loop Back Mode + * 00: Normal mode + * 01: Internal loop back mode (TX data is looped + * back to the RX lines. No transition is seen + * on the interface pins) + * 10: External loop back mode (TX data is looped + * back to the RX lines and also transmitted + * out to the MII interface pins) + * 11: Reserved + * 10:10 FC Force Collision + * 0: Normal mode. + * 1: Force Collision on any TX frame. + * For RXM test (in Loopback mode). + * 11:11 Reserved. + * 12:12 HS Hash Size + * 0: 8K address filtering + * (256KB of memory space required). + * 1: 512 address filtering + * ( 16KB of memory space required). + * 13:13 HM Hash Mode (0: Hash Func. 0; 1: Hash Func. 1) + * 14:14 HDM Hash Default Mode + * 0: Discard addresses not found in address table + * 1: Pass addresses not found in address table + * 15:15 HD Duplex Mode (0: Half Duplex, 1: Full Duplex) + * NOTE: Valid only when auto-negotiation for + * duplex mode is disabled. + * 30:16 Reserved + * 31:31 ACCS Accelerate Slot Time + * (0: Normal mode, 1: Reserved) + */ +#define ETH_EPCR_PM ETH__BIT(0) +#define ETH_EPCR_RBM ETH__BIT(1) +#define ETH_EPCR_PBF ETH__BIT(2) +#define ETH_EPCR_EN ETH__BIT(7) +#define ETH_EPCR_LPBK_GET(v) ETH__BIT(v, 8, 2) +#define ETH_EPCR_LPBK_Normal 0 +#define ETH_EPCR_LPBK_Internal 1 +#define ETH_EPCR_LPBK_External 2 +#define ETH_EPCR_FC ETH__BIT(10) + +#define ETH_EPCR_HS ETH__BIT(12) +#define ETH_EPCR_HS_8K 0 +#define ETH_EPCR_HS_512 ETH_EPCR_HS + +#define ETH_EPCR_HM ETH__BIT(13) +#define ETH_EPCR_HM_0 0 +#define ETH_EPCR_HM_1 ETH_EPCR_HM + +#define ETH_EPCR_HDM ETH__BIT(14) +#define ETH_EPCR_HDM_Discard 0 +#define ETH_EPCR_HDM_Pass ETH_EPCR_HDM + +#define ETH_EPCR_HD_Half 0 +#define ETH_EPCR_HD_Full ETH_EPCR_HD_Full + +#define ETH_EPCR_ACCS ETH__BIT(31) + + + +/* + * Table 598: Port Configuration Extend Register (PCXR) + * 00:00 IGMP IGMP Packets Capture Enable + * 0: IGMP packets are treated as normal Multicast + * packets. + * 1: IGMP packets on IPv4/Ipv6 over Ethernet/802.3 + * are trapped and sent to high priority RX + * queue. + * 01:01 SPAN Spanning Tree Packets Capture Enable + * 0: BPDU (Bridge Protocol Data Unit) packets are + * treated as normal Multicast packets. + * 1: BPDU packets are trapped and sent to high + * priority RX queue. + * 02:02 PAR Partition Enable (0: Normal, 1: Partition) + * When more than 61 collisions occur while + * transmitting, the port enters Partition mode. + * It waits for the first good packet from the + * wire and then goes back to Normal mode. Under + * Partition mode it continues transmitting, but + * it does not receive. + * 05:03 PRIOtx Priority weight in the round-robin between high + * and low priority TX queues. + * 000: 1 pkt from HIGH, 1 pkt from LOW. + * 001: 2 pkt from HIGH, 1 pkt from LOW. + * 010: 4 pkt from HIGH, 1 pkt from LOW. + * 011: 6 pkt from HIGH, 1 pkt from LOW. + * 100: 8 pkt from HIGH, 1 pkt from LOW. + * 101: 10 pkt from HIGH, 1 pkt from LOW. + * 110: 12 pkt from HIGH, 1 pkt from LOW. + * 111: All pkt from HIGH, 0 pkt from LOW. LOW is + * served only if HIGH is empty. + * NOTE: If the HIGH queue is emptied before + * finishing the count, the count is reset + * until the next first HIGH comes in. + * 07:06 PRIOrx Default Priority for Packets Received on this + * Port (00: Lowest priority, 11: Highest priority) + * 08:08 PRIOrx_Override Override Priority for Packets Received on this + * Port (0: Do not override, 1: Override with + * field) + * 09:09 DPLXen Enable Auto-negotiation for Duplex Mode + * (0: Enable, 1: Disable) + * 11:10 FCTLen Enable Auto-negotiation for 802.3x Flow-control + * 0: Enable; When enabled, 1 is written (through + * SMI access) to the PHY's register 4 bit 10 + * to advertise flow-control capability. + * 1: Disable; Only enables flow control after the + * PHY address is set by the CPU. When changing + * the PHY address the flow control + * auto-negotiation must be disabled. + * 11:11 FLP Force Link Pass + * (0: Force Link Pass, 1: Do NOT Force Link pass) + * 12:12 FCTL 802.3x Flow-Control Mode (0: Enable, 1: Disable) + * NOTE: Only valid when auto negotiation for flow + * control is disabled. + * 13:13 Reserved + * 15:14 MFL Max Frame Length + * Maximum packet allowed for reception (including + * CRC): 00: 1518 bytes, 01: 1536 bytes, + * 10: 2048 bytes, 11: 64K bytes + * 16:16 MIBclrMode MIB Counters Clear Mode (0: Clear, 1: No effect) + * 17:17 MIBctrMode Reserved. (MBZ) + * 18:18 Speed Port Speed (0: 10Mbit/Sec, 1: 100Mbit/Sec) + * NOTE: Only valid if SpeedEn bit is set. + * 19:19 SpeedEn Enable Auto-negotiation for Speed + * (0: Enable, 1: Disable) + * 20:20 RMIIen RMII enable + * 0: Port functions as MII port + * 1: Port functions as RMII port + * 21:21 DSCPen DSCP enable + * 0: IP DSCP field decoding is disabled. + * 1: IP DSCP field decoding is enabled. + * 31:22 Reserved + */ +#define ETH_EPCXR_IGMP ETH__BIT(0) +#define ETH_EPCXR_SPAN ETH__BIT(1) +#define ETH_EPCXR_PAR ETH__BIT(2) +#define ETH_EPCXR_PRIOtx_GET(v) ETH__EXT(v, 3, 3) +#define ETH_EPCXR_PRIOrx_GET(v) ETH__EXT(v, 3, 3) +#define ETH_EPCXR_PRIOrx_Override ETH__BIT(8) +#define ETH_EPCXR_DLPXen ETH__BIT(9) +#define ETH_EPCXR_FCTLen ETH__BIT(10) +#define ETH_EPCXR_FLP ETH__BIT(11) +#define ETH_EPCXR_FCTL ETH__BIT(12) +#define ETH_EPCXR_MFL_GET(v) ETH__EXT(v, 14, 2) +#define ETH_EPCXR_MFL_1518 0 +#define ETH_EPCXR_MFL_1536 1 +#define ETH_EPCXR_MFL_2048 2 +#define ETH_EPCXR_MFL_64K 3 +#define ETH_EPCXR_MIBclrMode ETH__BIT(16) +#define ETH_EPCXR_MIBctrMode ETH__BIT(17) +#define ETH_EPCXR_Speed ETH__BIT(18) +#define ETH_EPCXR_SpeedEn ETH__BIT(19) +#define ETH_EPCXR_RMIIEn ETH__BIT(20) +#define ETH_EPCXR_DSCPEn ETH__BIT(21) + + + +/* + * Table 599: Port Command Register (PCMR) + * 14:00 Reserved + * 15:15 FJ Force Jam / Flow Control + * When in half-duplex mode, the CPU uses this bit + * to force collisions on the Ethernet segment. + * When the CPU recognizes that it is going to run + * out of receive buffers, it can force the + * transmitter to send jam frames, forcing + * collisions on the wire. To allow transmission + * on the Ethernet segment, the CPU must clear the + * FJ bit when more resources are available. When + * in full-duplex and flow-control is enabled, this + * bit causes the port's transmitter to send + * flow-control PAUSE packets. The CPU must reset + * this bit when more resources are available. + * 31:16 Reserved + */ + +#define ETH_EPCMR_FJ ETH__BIT(15) + + +/* + * Table 600: Port Status Register (PSR) -- Read Only + * 00:00 Speed Indicates Port Speed (0: 10Mbs, 1: 100Mbs) + * 01:01 Duplex Indicates Port Duplex Mode (0: Half, 1: Full) + * 02:02 Fctl Indicates Flow-control Mode + * (0: enabled, 1: disabled) + * 03:03 Link Indicates Link Status (0: down, 1: up) + * 04:04 Pause Indicates that the port is in flow-control + * disabled state. This bit is set when an IEEE + * 802.3x flow-control PAUSE (XOFF) packet is + * received (assuming that flow-control is + * enabled and the port is in full-duplex mode). + * Reset when XON is received, or when the XOFF + * timer has expired. + * 05:05 TxLow Tx Low Priority Status + * Indicates the status of the low priority + * transmit queue: (0: Stopped, 1: Running) + * 06:06 TxHigh Tx High Priority Status + * Indicates the status of the high priority + * transmit queue: (0: Stopped, 1: Running) + * 07:07 TXinProg TX in Progress + * Indicates that the port's transmitter is in an + * active transmission state. + * 31:08 Reserved + */ +#define ETH_EPSR_Speed ETH__BIT(0) +#define ETH_EPSR_Duplex ETH__BIT(1) +#define ETH_EPSR_Fctl ETH__BIT(2) +#define ETH_EPSR_Link ETH__BIT(3) +#define ETH_EPSR_Pause ETH__BIT(4) +#define ETH_EPSR_TxLow ETH__BIT(5) +#define ETH_EPSR_TxHigh ETH__BIT(6) +#define ETH_EPSR_TXinProg ETH__BIT(7) + + +/* + * Table 601: Serial Parameters Register (SPR) + * 01:00 JAM_LENGTH Two bits to determine the JAM Length + * (in Backpressure) as follows: + * 00 = 12K bit-times + * 01 = 24K bit-times + * 10 = 32K bit-times + * 11 = 48K bit-times + * 06:02 JAM_IPG Five bits to determine the JAM IPG. + * The step is four bit-times. The value may vary + * between 4 bit time to 124. + * 11:07 IPG_JAM_TO_DATA Five bits to determine the IPG JAM to DATA. + * The step is four bit-times. The value may vary + * between 4 bit time to 124. + * 16:12 IPG_DATA Inter-Packet Gap (IPG) + * The step is four bit-times. The value may vary + * between 12 bit time to 124. + * NOTE: These bits may be changed only when the + * Ethernet ports is disabled. + * 21:17 Data_Blind Data Blinder + * The number of nibbles from the beginning of the + * IPG, in which the IPG counter is restarted when + * detecting a carrier activity. Following this + * value, the port enters the Data Blinder zone and + * does not reset the IPG counter. This ensures + * fair access to the medium. + * The default is 10 hex (64 bit times - 2/3 of the + * default IPG). The step is 4 bit-times. Valid + * range is 3 to 1F hex nibbles. + * NOTE: These bits may be only changed when the + * Ethernet port is disabled. + * 22:22 Limit4 The number of consecutive packet collisions that + * occur before the collision counter is reset. + * 0: The port resets its collision counter after + * 16 consecutive retransmit trials and + * restarts the Backoff algorithm. + * 1: The port resets its collision counter and + * restarts the Backoff algorithm after 4 + * consecutive transmit trials. + * 31:23 Reserved + */ +#define ETH_ESPR_JAM_LENGTH_GET(v) ETH__EXT(v, 0, 2) +#define ETH_ESPR_JAM_IPG_GET(v) ETH__EXT(v, 2, 5) +#define ETH_ESPR_IPG_JAM_TO_DATA_GET(v) ETH__EXT(v, 7, 5) +#define ETH_ESPR_IPG_DATA_GET(v) ETH__EXT(v, 12, 5) +#define ETH_ESPR_Data_Bilnd_GET(v) ETH__EXT(v, 17, 5) +#define ETH_ESPR_Limit4(v) ETH__BIT(22) + +/* + * Table 602: Hash Table Pointer Register (HTPR) + * 31:00 HTP 32-bit pointer to the address table. + * Bits [2:0] must be set to zero. + */ + +/* + * Table 603: Flow Control Source Address Low (FCSAL) + * 15:0 SA[15:0] Source Address + * The least significant bits of the source + * address for the port. This address is used for + * Flow Control. + * 31:16 Reserved + */ + +/* + * Table 604: Flow Control Source Address High (FCSAH) + * 31:0 SA[47:16] Source Address + * The most significant bits of the source address + * for the port. This address is used for Flow + * Control. + */ + + +/* + * Table 605: SDMA Configuration Register (SDCR) + * 01:00 Reserved + * 05:02 RC Retransmit Count + * Sets the maximum number of retransmits per + * packet. After executing retransmit for RC + * times, the TX SDMA closes the descriptor with a + * Retransmit Limit error indication and processes + * the next packet. When RC is set to 0, the + * number of retransmits is unlimited. In this + * case, the retransmit process is only terminated + * if CPU issues an Abort command. + * 06:06 BLMR Big/Little Endian Receive Mode + * The DMA supports Big or Little Endian + * configurations on a per channel basis. The BLMR + * bit only affects data transfer to memory. + * 0: Big Endian + * 1: Little Endian + * 07:07 BLMT Big/Little Endian Transmit Mode + * The DMA supports Big or Little Endian + * configurations on a per channel basis. The BLMT + * bit only affects data transfer from memory. + * 0: Big Endian + * 1: Little Endian + * 08:08 POVR PCI Override + * When set, causes the SDMA to direct all its + * accesses in PCI_0 direction and overrides + * normal address decoding process. + * 09:09 RIFB Receive Interrupt on Frame Boundaries + * When set, the SDMA Rx generates interrupts only + * on frame boundaries (i.e. after writing the + * frame status to the descriptor). + * 11:10 Reserved + * 13:12 BSZ Burst Size + * Sets the maximum burst size for SDMA + * transactions: + * 00: Burst is limited to 1 64bit words. + * 01: Burst is limited to 2 64bit words. + * 10: Burst is limited to 4 64bit words. + * 11: Burst is limited to 8 64bit words. + * 31:14 Reserved + */ +#define ETH_ESDCR_RC_GET(v) ETH__EXT(v, 2, 4) +#define ETH_ESDCR_BLMR ETH__BIT(6) +#define ETH_ESDCR_BLMT ETH__BIT(7) +#define ETH_ESDCR_POVR ETH__BIT(8) +#define ETH_ESDCR_RIFB ETH__BIT(9) +#define ETH_ESDCR_BSZ_GET(v) ETH__EXT(v, 12, 2) +#define ETH_ESDCR_BSZ_SET(v, n) (ETH__CLR(v, 12, 2),\ + (v) |= ETH__INS(n, 12)) +#define ETH_ESDCR_BSZ_1 0 +#define ETH_ESDCR_BSZ_2 1 +#define ETH_ESDCR_BSZ_4 2 +#define ETH_ESDCR_BSZ_8 3 + +#define ETH_ESDCR_BSZ_Strings { "1 64-bit word", "2 64-bit words", \ + "4 64-bit words", "8 64-bit words" } + +/* + * Table 606: SDMA Command Register (SDCMR) + * 06:00 Reserved + * 07:07 ERD Enable RX DMA. + * Set to 1 by the CPU to cause the SDMA to start + * a receive process. Cleared when the CPU issues + * an Abort Receive command. + * 14:08 Reserved + * 15:15 AR Abort Receive + * Set to 1 by the CPU to abort a receive SDMA + * operation. When the AR bit is set, the SDMA + * aborts its current operation and moves to IDLE. + * No descriptor is closed. The AR bit is cleared + * upon entering IDLE. After setting the AR bit, + * the CPU must poll the bit to verify that the + * abort sequence is completed. + * 16:16 STDH Stop TX High + * Set to 1 by the CPU to stop the transmission + * process from the high priority queue at the end + * of the current frame. An interrupt is generated + * when the stop command has been executed. + * Writing 1 to STDH resets TXDH bit. + * Writing 0 to this bit has no effect. + * 17:17 STDL Stop TX Low + * Set to 1 by the CPU to stop the transmission + * process from the low priority queue at the end + * of the current frame. An interrupt is generated + * when the stop command has been executed. + * Writing 1 to STDL resets TXDL bit. + * Writing 0 to this bit has no effect. + * 22:18 Reserved + * 23:23 TXDH Start Tx High + * Set to 1 by the CPU to cause the SDMA to fetch + * the first descriptor and start a transmit + * process from the high priority Tx queue. + * Writing 1 to TXDH resets STDH bit. + * Writing 0 to this bit has no effect. + * 24:24 TXDL Start Tx Low + * Set to 1 by the CPU to cause the SDMA to fetch + * the first descriptor and start a transmit + * process from the low priority Tx queue. + * Writing 1 to TXDL resets STDL bit. + * Writing 0 to this bit has no effect. + * 30:25 Reserved + * 31:31 AT Abort Transmit + * Set to 1 by the CPU to abort a transmit DMA + * operation. When the AT bit is set, the SDMA + * aborts its current operation and moves to IDLE. + * No descriptor is closed. Cleared upon entering + * IDLE. After setting AT bit, the CPU must poll + * it in order to verify that the abort sequence + * is completed. + */ +#define ETH_ESDCMR_ERD ETH__BIT(7) +#define ETH_ESDCMR_AR ETH__BIT(15) +#define ETH_ESDCMR_STDH ETH__BIT(16) +#define ETH_ESDCMR_STDL ETH__BIT(17) +#define ETH_ESDCMR_TXDH ETH__BIT(23) +#define ETH_ESDCMR_TXDL ETH__BIT(24) +#define ETH_ESDCMR_AT ETH__BIT(31) + +/* + * Table 607: Interrupt Cause Register (ICR) + * 00:00 RxBuffer Rx Buffer Return + * Indicates an Rx buffer returned to CPU ownership + * or that the port finished reception of a Rx + * frame in either priority queues. + * NOTE: In order to get a Rx Buffer return per + * priority queue, use bit 19:16. This bit is + * set upon closing any Rx descriptor which + * has its EI bit set. To limit the + * interrupts to frame (rather than buffer) + * boundaries, the user must set SDMA + * Configuration register's RIFB bit. When + * the RIFB bit is set, an interrupt + * generates only upon closing the first + * descriptor of a received packet, if this + * descriptor has it EI bit set. + * 01:01 Reserved + * 02:02 TxBufferHigh Tx Buffer for High priority Queue + * Indicates a Tx buffer returned to CPU ownership + * or that the port finished transmission of a Tx + * frame. + * NOTE: This bit is set upon closing any Tx + * descriptor which has its EI bit set. To + * limit the interrupts to frame (rather than + * buffer) boundaries, the user must set EI + * only in the last descriptor. + * 03:03 TxBufferLow Tx Buffer for Low Priority Queue + * Indicates a Tx buffer returned to CPU ownership + * or that the port finished transmission of a Tx + * frame. + * NOTE: This bit is set upon closing any Tx + * descriptor which has its EI bit set. To + * limit the interrupts to frame (rather than + * buffer) boundaries, the user must set EI + * only in the last descriptor. + * 05:04 Reserved + * 06:06 TxEndHigh Tx End for High Priority Queue + * Indicates that the Tx DMA stopped processing the + * high priority queue after stop command, or that + * it reached the end of the high priority + * descriptor chain. + * 07:07 TxEndLow Tx End for Low Priority Queue + * Indicates that the Tx DMA stopped processing the + * low priority queue after stop command, or that + * it reached the end of the low priority + * descriptor chain. + * 08:08 RxError Rx Resource Error + * Indicates a Rx resource error event in one of + * the priority queues. + * NOTE: To get a Rx Resource Error Indication per + * priority queue, use bit 23:20. + * 09:09 Reserved + * 10:10 TxErrorHigh Tx Resource Error for High Priority Queue + * Indicates a Tx resource error event during + * packet transmission from the high priority queue + * 11:11 TxErrorLow Tx Resource Error for Low Priority Queue + * Indicates a Tx resource error event during + * packet transmission from the low priority queue + * 12:12 RxOVR Rx Overrun + * Indicates an overrun event that occurred during + * reception of a packet. + * 13:13 TxUdr Tx Underrun + * Indicates an underrun event that occurred during + * transmission of packet from either queue. + * 15:14 Reserved + * 16:16 RxBuffer-Queue[0] Rx Buffer Return in Priority Queue[0] + * Indicates a Rx buffer returned to CPU ownership + * or that the port completed reception of a Rx + * frame in a receive priority queue[0] + * 17:17 RxBuffer-Queue[1] Rx Buffer Return in Priority Queue[1] + * Indicates a Rx buffer returned to CPU ownership + * or that the port completed reception of a Rx + * frame in a receive priority queue[1]. + * 18:18 RxBuffer-Queue[2] Rx Buffer Return in Priority Queue[2] + * Indicates a Rx buffer returned to CPU ownership + * or that the port completed reception of a Rx + * frame in a receive priority queue[2]. + * 19:19 RxBuffer-Queue[3] Rx Buffer Return in Priority Queue[3] + * Indicates a Rx buffer returned to CPU ownership + * or that the port completed reception of a Rx + * frame in a receive priority queue[3]. + * 20:20 RxError-Queue[0] Rx Resource Error in Priority Queue[0] + * Indicates a Rx resource error event in receive + * priority queue[0]. + * 21:21 RxError-Queue[1] Rx Resource Error in Priority Queue[1] + * Indicates a Rx resource error event in receive + * priority queue[1]. + * 22:22 RxError-Queue[2] Rx Resource Error in Priority Queue[2] + * Indicates a Rx resource error event in receive + * priority queue[2]. + * 23:23 RxError-Queue[3] Rx Resource Error in Priority Queue[3] + * Indicates a Rx resource error event in receive + * priority queue[3]. + * 27:24 Reserved + * 28:29 MIIPhySTC MII PHY Status Change + * Indicates a status change reported by the PHY + * connected to this port. Set when the MII + * management interface block identifies a change + * in PHY's register 1. + * 29:29 SMIdone SMI Command Done + * Indicates that the SMI completed a MII + * management command (either read or write) that + * was initiated by the CPU writing to the SMI + * register. + * 30:30 Reserved + * 31:31 EtherIntSum Ethernet Interrupt Summary + * This bit is a logical OR of the (unmasked) bits + * [30:04] in the Interrupt Cause register. + */ + +#define ETH_IR_RxBuffer ETH__BIT(0) +#define ETH_IR_TxBufferHigh ETH__BIT(2) +#define ETH_IR_TxBufferLow ETH__BIT(3) +#define ETH_IR_TxEndHigh ETH__BIT(6) +#define ETH_IR_TxEndLow ETH__BIT(7) +#define ETH_IR_RxError ETH__BIT(8) +#define ETH_IR_TxErrorHigh ETH__BIT(10) +#define ETH_IR_TxErrorLow ETH__BIT(11) +#define ETH_IR_RxOVR ETH__BIT(12) +#define ETH_IR_TxUdr ETH__BIT(13) +#define ETH_IR_RxBuffer_0 ETH__BIT(16) +#define ETH_IR_RxBuffer_1 ETH__BIT(17) +#define ETH_IR_RxBuffer_2 ETH__BIT(18) +#define ETH_IR_RxBuffer_3 ETH__BIT(19) +#define ETH_IR_RxBuffer_GET(v) ETH__EXT(v, 16, 4) +#define ETH_IR_RxError_0 ETH__BIT(20) +#define ETH_IR_RxError_1 ETH__BIT(21) +#define ETH_IR_RxError_2 ETH__BIT(22) +#define ETH_IR_RxError_3 ETH__BIT(23) +#define ETH_IR_RxError_GET(v) ETH__EXT(v, 20, 4) +#define ETH_IR_RxBits (ETH_IR_RxBuffer_0|\ + ETH_IR_RxBuffer_1|\ + ETH_IR_RxBuffer_2|\ + ETH_IR_RxBuffer_3|\ + ETH_IR_RxError_0|\ + ETH_IR_RxError_1|\ + ETH_IR_RxError_2|\ + ETH_IR_RxError_3) +#define ETH_IR_MIIPhySTC ETH__BIT(28) +#define ETH_IR_SMIdone ETH__BIT(29) +#define ETH_IR_EtherIntSum (1<<31) +#define ETH_IR_Summary (1<<31) +#define ETH_IR_ErrorSum 0x803d00 +#define INTR_RX_ERROR 0x801100 +#define INTR_TX_ERROR 0x002c00 + +/* + * Table 608: Interrupt Mask Register (IMR) + * 31:00 Various Mask bits for the Interrupt Cause register. + */ + +/* + * Table 609: IP Differentiated Services CodePoint to Priority0 low (DSCP2P0L), + * 31:00 Priority0_low The LSB priority bits for DSCP[31:0] entries. + */ + +/* + * Table 610: IP Differentiated Services CodePoint to Priority0 high (DSCP2P0H) + * 31:00 Priority0_high The LSB priority bits for DSCP[63:32] entries. + */ + +/* + * Table 611: IP Differentiated Services CodePoint to Priority1 low (DSCP2P1L) + * 31:00 Priority1_low The MSB priority bits for DSCP[31:0] entries. + */ + +/* + * Table 612: IP Differentiated Services CodePoint to Priority1 high (DSCP2P1H) + * 31:00 Priority1_high The MSB priority bit for DSCP[63:32] entries. + */ + +/* + * Table 613: VLAN Priority Tag to Priority (VPT2P) + * 07:00 Priority0 The LSB priority bits for VLAN Priority[7:0] + * entries. + * 15:08 Priority1 The MSB priority bits for VLAN Priority[7:0] + * entries. + * 31:16 Reserved + */ +#endif /* _DEV_GTETHREG_H_ */ diff --git a/bsps/powerpc/mvme5500/include/bsp/VMEConfig.h b/bsps/powerpc/mvme5500/include/bsp/VMEConfig.h new file mode 100644 index 0000000000..ecc5789899 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/VMEConfig.h @@ -0,0 +1,67 @@ +#ifndef RTEMS_BSP_VME_CONFIG_H +#define RTEMS_BSP_VME_CONFIG_H +/* VMEConfig.h, S. Kate Feng modified it for MVME5500 3/04 + * + * May 2011 : Use the VME shared IRQ handlers. + * + * It seems that the implementation of VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND + * is not fully developed. The UNIV_REGOFF_VCSR_BS is defined for VME64 + * specification, which does not apply to a VME32 crate. In order to avoid + * spurious VME interrupts, a better and more universal solution is + * to flush the vmeUniverse FIFO by reading a register back within the + * users' Interrupt Service Routine (ISR) before returning. + * + * Some devices might require the ISR to issue an interrupt status READ + * after its IRQ is cleared, but before its corresponding interrupt + * is enabled again. + * + */ + +/* + * Prototypes + */ +int BSP_VMEInit(void); +int BSP_VMEIrqMgrInstall(void); + +/* BSP specific address space configuration parameters */ + +/* + * The BSP maps VME address ranges into + * one BAT. + * NOTE: the BSP (startup/bspstart.c) uses + * hardcoded window lengths that match this + * layout: + */ +#define _VME_A32_WIN0_ON_PCI 0x90000000 +/* If _VME_CSR_ON_PCI is defined then the A32 window is reduced to accommodate + * CSR for space. + */ +#define _VME_CSR_ON_PCI 0x9e000000 +#define _VME_A24_ON_PCI 0x9f000000 +#define _VME_A16_ON_PCI 0x9fff0000 + +/* Reuse BAT 0 for VME */ +#define BSP_VME_BAT_IDX 0 + +/* start of the A32 window on the VME bus + * TODO: this should perhaps be a configuration option + */ +#define _VME_A32_WIN0_ON_VME 0x20000000 + +/* if _VME_DRAM_OFFSET is defined, the BSP + * will map our RAM onto the VME bus, starting + * at _VME_DRAM_OFFSET + */ +#define _VME_DRAM_OFFSET 0x90000000 + +#define BSP_VME_UNIVERSE_INSTALL_IRQ_MGR(err) \ + do { \ + err = vmeUniverseInstallIrqMgrAlt(VMEUNIVERSE_IRQ_MGR_FLAG_SHARED,\ + 0, BSP_GPP_VME_VLINT0, \ + 1, BSP_GPP_VME_VLINT1, \ + 2, BSP_GPP_VME_VLINT2, \ + 3, BSP_GPP_VME_VLINT3, \ + -1 /* terminate list */); \ + } while (0) + +#endif diff --git a/bsps/powerpc/mvme5500/include/bsp/VPD.h b/bsps/powerpc/mvme5500/include/bsp/VPD.h new file mode 100644 index 0000000000..33aec8b74c --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/VPD.h @@ -0,0 +1,9 @@ +/* The mapping of the Configuration VPD + * + * (C) 2004, NSLS, Brookhaven National Laboratory, + * S. Kate Feng, + * + */ + +#define VPD_ENET0_OFFSET 0x3c +#define VPD_ENET1_OFFSET 0x45 diff --git a/bsps/powerpc/mvme5500/include/bsp/bspException.h b/bsps/powerpc/mvme5500/include/bsp/bspException.h new file mode 100644 index 0000000000..7cd816e818 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/bspException.h @@ -0,0 +1,99 @@ +#ifndef BSP_EXCEPTION_HANDLER_H +#define BSP_EXCEPTION_HANDLER_H + +/* A slightly improved exception 'default' exception handler for RTEMS / SVGM */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 5/2002, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include + +/* Two types of exception intercepting / catching is supported: + * + * - lowlevel handling (runs at IRQ level, before restoring any + * task context). + * - highlevel handling. + * + * A lowlevel user hook is invoked twice, before and after processing + * (printing) the exception. + * If the user hook returns a nonzero value, normal processing + * is skipped (including the second call to the hook) + * + * If the hook returns nonzero to the second call, no default + * 'panic' occurs. + * + * Default 'panic': + * - if a task context is available: + * - if a highlevel handler is installed, pass control + * to the highlevel handler when returning from the + * exception (the highlevel handler should probably + * do a longjmp()). Otherwise: + * - try to suspend interrupted task. + * - hang if no task context is available. + * + */ + +typedef struct BSP_ExceptionExtensionRec_ *BSP_ExceptionExtension; + +typedef int (*BSP_ExceptionHookProc)(BSP_Exception_frame *frame, BSP_ExceptionExtension ext, int after); + +typedef struct BSP_ExceptionExtensionRec_ { + BSP_ExceptionHookProc lowlevelHook; + int quiet; /* silence the exception handler */ + void (*highlevelHook)(BSP_ExceptionExtension); + /* user fields may be added after this */ +} BSP_ExceptionExtensionRec; + +#define SRR1_TEA_EXC (1<<(31-13)) +#define SRR1_MCP_EXC (1<<(31-12)) + +void +BSP_exceptionHandler(BSP_Exception_frame* excPtr); + +/* install an exception handler to the current task context */ +BSP_ExceptionExtension +BSP_exceptionHandlerInstall(BSP_ExceptionExtension e); + +#endif diff --git a/bsps/powerpc/mvme5500/include/bsp/bspMvme5500.h b/bsps/powerpc/mvme5500/include/bsp/bspMvme5500.h new file mode 100644 index 0000000000..9fb53869ff --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/bspMvme5500.h @@ -0,0 +1,15 @@ +/* GT64260 register base mapping on the MVME5500 + * + * (C) Shuchen K. Feng ,NSLS, + * Brookhaven National Laboratory, 2003 + * + */ +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define GT64260_REG_BASE 0xf1000000 /* Base of GT64260 Reg Space */ +#define GT64260_REG_SPACE_SIZE 0x10000 /* 64Kb Internal Reg Space */ + +#define GT64260_DEV1_BASE 0xf1100000 /* Device bank1(chip select 1) base + */ +#define GT64260_DEV1_SIZE 0x00100000 /* Device bank size */ diff --git a/bsps/powerpc/mvme5500/include/bsp/gtpcireg.h b/bsps/powerpc/mvme5500/include/bsp/gtpcireg.h new file mode 100644 index 0000000000..74751f6088 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/gtpcireg.h @@ -0,0 +1,99 @@ +/* $NetBSD: gtpcireg.h,v 1.2 2003/03/24 17:03:18 matt Exp $ */ + +/* + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#define PCI_ARBCTL_EN (1<<31) + +#define PCI_COMMAND_SB_DIS 0x2000 /* PCI configuration read will stop + * acting as sync barrier transactin + */ + +#define PCI_MEM_BASE_ADDR PCI_BASE_ADDRESS_4 + +#define PCI_IO_BASE_ADDR PCI_BASE_ADDRESS_5 + +#define PCI_STATUS_CLRERR_MASK 0xf9000000 /* */ + +#define PCI_BARE_IntMemEn 0x200 + +#define PCI_ACCCTLBASEL_PrefetchEn 0x0001000 +#define PCI_ACCCTLBASEL_RdPrefetch 0x0010000 +#define PCI_ACCCTLBASEL_RdLinePrefetch 0x0020000 +#define PCI_ACCCTLBASEL_RdMulPrefetch 0x0040000 +#define PCI_ACCCTLBASEL_WBurst_8_QW 0x0100000 +#define PCI_ACCCTLBASEL_PCISwap_NoSwap 0x1000000 + +#define PCI0_P2P_CONFIG 0x1d14 +#define PCI_SNOOP_BASE0_LOW 0x1f00 +#define PCI_SNOOP_BASE0_HIGH 0x1f04 +#define PCI_SNOOP_TOP0 0x1f08 + +#define PCI0_SCS0_BAR_SIZE 0x0c08 +#define PCI0_SCS1_BAR_SIZE 0x0d08 +#define PCI0_SCS2_BAR_SIZE 0x0c0c +#define PCI0_SCS3_BAR_SIZE 0x0d0c + +#define PCI0_BASE_ADDR_REG_ENABLE 0x0c3c +#define PCI0_ARBITER_CNTL 0x1d00 +#define PCI0_ACCESS_CNTL_BASE0_LOW 0x1e00 +#define PCI0_ACCESS_CNTL_BASE0_HIGH 0x1e04 +#define PCI0_ACCESS_CNTL_BASE0_TOP 0x1e08 + +#define PCI0_ACCESS_CNTL_BASE1_LOW 0x1e10 +#define PCI0_ACCESS_CNTL_BASE1_HIGH 0x1e14 +#define PCI0_ACCESS_CNTL_BASE1_TOP 0x1e18 + +#define PCI1_BASE_ADDR_REG_ENABLE 0x0cbc +#define PCI1_ARBITER_CNTL 0x1d80 +#define PCI1_ACCESS_CNTL_BASE0_LOW 0x1e80 +#define PCI1_ACCESS_CNTL_BASE0_HIGH 0x1e84 +#define PCI1_ACCESS_CNTL_BASE0_TOP 0x1e88 + +#define PCI1_ACCESS_CNTL_BASE1_LOW 0x1e90 +#define PCI1_ACCESS_CNTL_BASE1_HIGH 0x1e94 +#define PCI1_ACCESS_CNTL_BASE1_TOP 0x1e98 + +#define PCI_SNOOP_BASE1_LOW 0x1f10 +#define PCI_SNOOP_BASE1_HIGH 0x1f14 +#define PCI_SNOOP_TOP1 0x1f18 + +#define PCI0_CMD_CNTL 0xc00 + +#define PCI1_P2P_CONFIG 0x1d94 +#define PCI1_CMD_CNTL 0xc80 +#define PCI1_CONFIG_ADDR 0xc78 +#define PCI1_CONFIG_DATA 0xc7c diff --git a/bsps/powerpc/mvme5500/include/bsp/gtreg.h b/bsps/powerpc/mvme5500/include/bsp/gtreg.h new file mode 100644 index 0000000000..e9aaeff844 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/gtreg.h @@ -0,0 +1,810 @@ +/* $NetBSD: gtreg.h,v 1.1 2003/03/05 22:08:22 matt Exp $ */ + +/* + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DISCOVERY_DEV_GTREG_H_ +#define _DISCOVERY_DEV_GTREG_H_ + +#define GT__BIT(bit) (1U << (bit)) +#define GT__MASK(bit) (GT__BIT(bit) - 1) +#define GT__EXT(data, bit, len) (((data) >> (bit)) & GT__MASK(len)) +#define GT__CLR(data, bit, len) ((data) &= ~(GT__MASK(len) << (bit))) +#define GT__INS(new, bit) ((new) << (bit)) + + +/* + * Table 30: CPU Address Decode Register Map + */ +#define GT_SCS0_Low_Decode 0x0008 +#define GT_SCS0_High_Decode 0x0010 +#define GT_SCS1_Low_Decode 0x0208 +#define GT_SCS1_High_Decode 0x0210 +#define GT_SCS2_Low_Decode 0x0018 +#define GT_SCS2_High_Decode 0x0020 +#define GT_SCS3_Low_Decode 0x0218 +#define GT_SCS3_High_Decode 0x0220 +#define GT_CS0_Low_Decode 0x0028 +#define GT_CS0_High_Decode 0x0030 +#define GT_CS1_Low_Decode 0x0228 +#define GT_CS1_High_Decode 0x0230 +#define GT_CS2_Low_Decode 0x0248 +#define GT_CS2_High_Decode 0x0250 +#define GT_CS3_Low_Decode 0x0038 +#define GT_CS3_High_Decode 0x0040 +#define GT_BootCS_Low_Decode 0x0238 +#define GT_BootCS_High_Decode 0x0240 +#define GT_PCI0_IO_Low_Decode 0x0048 +#define GT_PCI0_IO_High_Decode 0x0050 +#define GT_PCI0_Mem0_Low_Decode 0x0058 +#define GT_PCI0_Mem0_High_Decode 0x0060 +#define GT_PCI0_Mem1_Low_Decode 0x0080 +#define GT_PCI0_Mem1_High_Decode 0x0088 +#define GT_PCI0_Mem2_Low_Decode 0x0258 +#define GT_PCI0_Mem2_High_Decode 0x0260 +#define GT_PCI0_Mem3_Low_Decode 0x0280 +#define GT_PCI0_Mem3_High_Decode 0x0288 +#define GT_PCI1_IO_Low_Decode 0x0090 +#define GT_PCI1_IO_High_Decode 0x0098 +#define GT_PCI1_Mem0_Low_Decode 0x00a0 +#define GT_PCI1_Mem0_High_Decode 0x00a8 +#define GT_PCI1_Mem1_Low_Decode 0x00b0 +#define GT_PCI1_Mem1_High_Decode 0x00b8 +#define GT_PCI1_Mem2_Low_Decode 0x02a0 +#define GT_PCI1_Mem2_High_Decode 0x02a8 +#define GT_PCI1_Mem3_Low_Decode 0x02b0 +#define GT_PCI1_Mem3_High_Decode 0x02b8 +#define GT_Internal_Decode 0x0068 +#define GT_CPU0_Low_Decode 0x0290 +#define GT_CPU0_High_Decode 0x0298 +#define GT_CPU1_Low_Decode 0x02c0 +#define GT_CPU1_High_Decode 0x02c8 +#define GT_PCI0_IO_Remap 0x00f0 +#define GT_PCI0_Mem0_Remap_Low 0x00f8 +#define GT_PCI0_Mem0_Remap_High 0x0320 +#define GT_PCI0_Mem1_Remap_Low 0x0100 +#define GT_PCI0_Mem1_Remap_High 0x0328 +#define GT_PCI0_Mem2_Remap_Low 0x02f8 +#define GT_PCI0_Mem2_Remap_High 0x0330 +#define GT_PCI0_Mem3_Remap_Low 0x0300 +#define GT_PCI0_Mem3_Remap_High 0x0338 +#define GT_PCI1_IO_Remap 0x0108 +#define GT_PCI1_Mem0_Remap_Low 0x0110 +#define GT_PCI1_Mem0_Remap_High 0x0340 +#define GT_PCI1_Mem1_Remap_Low 0x0118 +#define GT_PCI1_Mem1_Remap_High 0x0348 +#define GT_PCI1_Mem2_Remap_Low 0x0310 +#define GT_PCI1_Mem2_Remap_High 0x0350 +#define GT_PCI1_Mem3_Remap_Low 0x0318 +#define GT_PCI1_Mem3_Remap_High 0x0358 + + +/* + * Table 31: CPU Control Register Map + */ +#define GT_CPU_Cfg 0x0000 +#define GT_CPU_Mode 0x0120 +#define GT_CPU_Master_Ctl 0x0160 +#define GT_CPU_If_Xbar_Ctl_Low 0x0150 +#define GT_CPU_If_Xbar_Ctl_High 0x0158 +#define GT_CPU_If_Xbar_Timeout 0x0168 +#define GT_CPU_Rd_Rsp_Xbar_Ctl_Low 0x0170 +#define GT_CPU_Rd_Rsp_Xbar_Ctl_High 0x0178 + +/* + * Table 32: CPU Sync Barrier Register Map + */ +#define GT_PCI_Sync_Barrier(bus) (0x00c0 | ((bus) << 3)) +#define GT_PCI0_Sync_Barrier 0x00c0 +#define GT_PCI1_Sync_Barrier 0x00c8 + +/* + * Table 33: CPU Access Protection Register Map + */ +#define GT_Protect_Low_0 0x0180 +#define GT_Protect_High_0 0x0188 +#define GT_Protect_Low_1 0x0190 +#define GT_Protect_High_1 0x0198 +#define GT_Protect_Low_2 0x01a0 +#define GT_Protect_High_2 0x01a8 +#define GT_Protect_Low_3 0x01b0 +#define GT_Protect_High_3 0x01b8 +#define GT_Protect_Low_4 0x01c0 +#define GT_Protect_High_4 0x01c8 +#define GT_Protect_Low_5 0x01d0 +#define GT_Protect_High_5 0x01d8 +#define GT_Protect_Low_6 0x01e0 +#define GT_Protect_High_6 0x01e8 +#define GT_Protect_Low_7 0x01f0 +#define GT_Protect_High_7 0x01f8 + +/* + * Table 34: Snoop Control Register Map + */ +#define GT_Snoop_Base_0 0x0380 +#define GT_Snoop_Top_0 0x0388 +#define GT_Snoop_Base_1 0x0390 +#define GT_Snoop_Top_1 0x0398 +#define GT_Snoop_Base_2 0x03a0 +#define GT_Snoop_Top_2 0x03a8 +#define GT_Snoop_Base_3 0x03b0 +#define GT_Snoop_Top_3 0x03b8 + +/* + * Table 35: CPU Error Report Register Map + */ +#define GT_CPU_Error_Address_Low 0x0070 +#define GT_CPU_Error_Address_High 0x0078 +#define GT_CPU_Error_Data_Low 0x0128 +#define GT_CPU_Error_Data_High 0x0130 +#define GT_CPU_Error_Parity 0x0138 +#define GT_CPU_Error_Cause 0x0140 +#define GT_CPU_Error_Mask 0x0148 + +#define GT_DecodeAddr_SET(g, r, v) \ + do { \ + gt_read((g), GT_Internal_Decode); \ + gt_write((g), (r), ((v) & 0xfff00000) >> 20); \ + while ((gt_read((g), (r)) & 0xfff) != ((v) >> 20)); \ + } while (0) + +#define GT_LowAddr_GET(v) (GT__EXT((v), 0, 12) << 20) +#define GT_HighAddr_GET(v) ((GT__EXT((v), 0, 12) << 20) | 0xfffff) + +#define GT_MPP_Control0 0xf000 +#define GT_MPP_Control1 0xf004 +#define GT_MPP_Control2 0xf008 +#define GT_MPP_Control3 0xf00c + +/* added for GT64260 */ +#define GT_MPP_SerialPortMultiplex 0xf010 + +#define GT_GPP_IO_Control 0xf100 +#define GT_GPP_Level_Control 0xf110 +#define GT_GPP_Value 0xf104 +#define GT_GPP_Interrupt_Cause 0xf108 +#define GT_GPP_Interrupt_Mask 0xf10c +/* + * Table 36: SCS[0]* Low Decode Address, Offset: 0x008 + * Table 38: SCS[1]* Low Decode Address, Offset: 0x208 + * Table 40: SCS[2]* Low Decode Address, Offset: 0x018 + * Table 42: SCS[3]* Low Decode Address, Offset: 0x218 + * Table 44: CS[0]* Low Decode Address, Offset: 0x028 + * Table 46: CS[1]* Low Decode Address, Offset: 0x228 + * Table 48: CS[2]* Low Decode Address, Offset: 0x248 + * Table 50: CS[3]* Low Decode Address, Offset: 0x038 + * Table 52: BootCS* Low Decode Address, Offset: 0x238 + * Table 75: CPU 0 Low Decode Address, Offset: 0x290 + * Table 77: CPU 1 Low Decode Address, Offset: 0x2c0 + * + * 11:00 LowAddr SCS[0] Base Address + * 31:12 Reserved Must be 0. + */ + +/* + * Table 37: SCS[0]* High Decode Address, Offset: 0x010 + * Table 39: SCS[1]* High Decode Address, Offset: 0x210 + * Table 41: SCS[2]* High Decode Address, Offset: 0x020 + * Table 43: SCS[3]* High Decode Address, Offset: 0x220 + * Table 45: CS[0]* High Decode Address, Offset: 0x030 + * Table 47: CS[1]* High Decode Address, Offset: 0x230 + * Table 49: CS[2]* High Decode Address, Offset: 0x250 + * Table 51: CS[3]* High Decode Address, Offset: 0x040 + * Table 53: BootCS* High Decode Address, Offset: 0x240 + * Table 76: CPU 0 High Decode Address, Offset: 0x298 + * Table 78: CPU 1 High Decode Address, Offset: 0x2c8 + * + * 11:00 HighAddr SCS[0] Top Address + * 31:12 Reserved + */ + +/* + * Table 54: PCI_0 I/O Low Decode Address, Offset: 0x048 + * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058 + * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080 + * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258 + * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280 + * Table 64: PCI_1 I/O Low Decode Address, Offset: 0x090 + * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0 + * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0 + * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0 + * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0 + * + * 11:00 LowAddr PCI IO/Memory Space Base Address + * 23:12 Reserved + * 26:24 PCISwap PCI Master Data Swap Control (0: Byte Swap; + * 1: No swapping; 2: Both byte and word swap; + * 3: Word swap; 4..7: Reserved) + * 27:27 PCIReq64 PCI master REQ64* policy (Relevant only when + * configured to 64-bit PCI bus and not I/O) + * 0: Assert s REQ64* only when transaction + * is longer than 64-bits. + * 1: Always assert REQ64*. + * 31:28 Reserved + */ +#define GT_PCISwap_GET(v) GT__EXT((v), 24, 3) +#define GT_PCISwap_ByteSwap 0 +#define GT_PCISwap_NoSwap 1 +#define GT_PCISwap_ByteWordSwap 2 +#define GT_PCISwap_WordSwap 3 +#define GT_PCI_LowDecode_PCIReq64 GT__BIT(27) + +/* + * Table 55: PCI_0 I/O High Decode Address, Offset: 0x050 + * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060 + * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088 + * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260 + * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288 + * Table 65: PCI_1 I/O High Decode Address, Offset: 0x098 + * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8 + * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8 + * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8 + * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8 + * + * 11:00 HighAddr PCI_0 I/O Space Top Address + * 31:12 Reserved + */ + +/* + * Table 74: Internal Space Decode, Offset: 0x068 + * 15:00 IntDecode GT64260 Internal Space Base Address + * 23:16 Reserved + * 26:24 PCISwap Same as PCI_0 Memory 0 Low Decode Address. + * NOTE: Reserved for Galileo Technology usage. + * Relevant only for PCI master configuration + * transactions on the PCI bus. + * 31:27 Reserved + */ + +/* + * Table 79: PCI_0 I/O Address Remap, Offset: 0x0f0 + * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8 + * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100 + * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8 + * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300 + * Table 88: PCI_1 I/O Address Remap, Offset: 0x108 + * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110 + * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118 + * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310 + * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318 + * + * 11:00 Remap PCI IO/Memory Space Address Remap (31:20) + * 31:12 Reserved + */ + +/* + * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320 + * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328 + * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330 + * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338 + * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340 + * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348 + * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350 + * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358 + * + * 31:00 Remap PCI Memory Address Remap (high 32 bits) + */ + +/* + * Table 97: CPU Configuration, Offset: 0x000 + * 07:00 NoMatchCnt CPU Address Miss Counter + * 08:08 NoMatchCntEn CPU Address Miss Counter Enable + * NOTE: Relevant only if multi-GT is enabled. + * (0: Disabled; 1: Enabled) + * 09:09 NoMatchCntExt CPU address miss counter MSB + * 10:10 Reserved + * 11:11 AACKDelay Address Acknowledge Delay + * 0: AACK* is asserted one cycle after TS*. + * 1: AACK* is asserted two cycles after TS*. + * 12:12 Endianess Must be 0 + * NOTE: The GT64260 does not support the PowerPC + * Little Endian convention + * 13:13 Pipeline Pipeline Enable + * 0: Disabled. The GT64260 will not respond with + * AACK* to a new CPU transaction, before the + * previous transaction data phase completes. + * 1: Enabled. + * 14:14 Reserved + * 15:15 TADelay Transfer Acknowledge Delay + * 0: TA* is asserted one cycle after AACK* + * 1: TA* is asserted two cycles after AACK* + * 16:16 RdOOO Read Out of Order Completion + * 0: Not Supported, Data is always returned in + * order (DTI[0-2] is always driven + * 1: Supported + * 17:17 StopRetry Relevant only if PCI Retry is enabled + * 0: Keep Retry all PCI transactions targeted + * to the GT64260. + * 1: Stop Retry of PCI transactions. + * 18:18 MultiGTDec Multi-GT Address Decode + * 0: Normal address decoding + * 1: Multi-GT address decoding + * 19:19 DPValid CPU DP[0-7] Connection. CPU write parity ... + * 0: is not checked. (Not connected) + * 1: is checked (Connected) + * 21:20 Reserved + * 22:22 PErrProp Parity Error Propagation + * 0: GT64260 always drives good parity on + * DP[0-7] during CPU reads. + * 1: GT64260 drives bad parity on DP[0-7] in case + * the read response from the target interface + * comes with erroneous data indication + * (e.g. ECC error from SDRAM interface). + * 25:23 Reserved + * 26:26 APValid CPU AP[0-3] Connection. CPU address parity ... + * 0: is not checked. (Not connected) + * 1: is checked (Connected) + * 27:27 RemapWrDis Address Remap Registers Write Control + * 0: Write to Low Address decode register. + * Results in writing of the corresponding + * Remap register. + * 1: Write to Low Address decode register. No + * affect on the corresponding Remap register. + * 28:28 ConfSBDis Configuration Read Sync Barrier Disable + * 0: enabled; 1: disabled + * 29:29 IOSBDis I/O Read Sync Barrier Disable + * 0: enabled; 1: disabled + * 30:30 ClkSync Clocks Synchronization + * 0: The CPU interface is running with SysClk, + * which is asynchronous to TClk. + * 1: The CPU interface is running with TClk. + * 31:31 Reserved + */ +#define GT_CPUCfg_NoMatchCnt_GET(v) GT__EXT((v), 0, 8) +#define GT_CPUCfg_NoMatchCntEn GT__BIT( 9) +#define GT_CPUCfg_NoMatchCntExt GT__BIT(10) +#define GT_CPUCfg_AACKDelay GT__BIT(11) +#define GT_CPUCfg_Endianess GT__BIT(12) +#define GT_CPUCfg_Pipeline GT__BIT(13) +#define GT_CPUCfg_TADelay GT__BIT(15) +#define GT_CPUCfg_RdOOO GT__BIT(16) +#define GT_CPUCfg_StopRetry GT__BIT(17) +#define GT_CPUCfg_MultiGTDec GT__BIT(18) +#define GT_CPUCfg_DPValid GT__BIT(19) +#define GT_CPUCfg_PErrProp GT__BIT(22) +#define GT_CPUCfg_APValid GT__BIT(26) +#define GT_CPUCfg_RemapWrDis GT__BIT(27) +#define GT_CPUCfg_ConfSBDis GT__BIT(28) +#define GT_CPUCfg_IOSBDis GT__BIT(29) +#define GT_CPUCfg_ClkSync GT__BIT(30) + +/* + * Table 98: CPU Mode, Offset: 0x120, Read only + * 01:00 MultiGTID Multi-GT ID + * Represents the ID to which the GT64260 responds + * to during a multi-GT address decoding period. + * 02:02 MultiGT (0: Single; 1: Multiple) GT configuration + * 03:03 RetryEn (0: Don't; 1: Do) Retry PCI transactions + * 07:04 CPUType + * 0x0-0x3: Reserved + * 0x4: 64-bit PowerPC CPU, 60x bus + * 0x5: 64-bit PowerPC CPU, MPX bus + * 0x6-0xf: Reserved + * 31:08 Reserved + */ +#define GT_CPUMode_MultiGTID_GET(v) GT__EXT(v, 0, 2) +#define GT_CPUMode_MultiGT GT__BIT(2) +#define GT_CPUMode_RetryEn GT__BIT(3) +#define GT_CPUMode_CPUType_GET(v) GT__EXT(v, 4, 4) + +/* + * Table 99: CPU Master Control, Offset: 0x160 + * 07:00 Reserved + * 08:08 IntArb CPU Bus Internal Arbiter Enable + * NOTE: Only relevant to 60x bus mode. When + * running MPX bus, the GT64260 internal + * arbiter must be used. + * 0: Disabled. External arbiter is required. + * 1: Enabled. Use the GT64260 CPU bus arbiter. + * 09:09 IntBusCtl CPU Interface Unit Internal Bus Control + * NOTE: This bit must be set to 1. It is reserved + * for Galileo Technology usage. + * 0: Enable internal bus sharing between master + * and slave interfaces. + * 1: Disable internal bus sharing between master + * and slave interfaces. + * 10:10 MWrTrig Master Write Transaction Trigger + * 0: With first valid write data + * 1: With last valid write data + * 11:11 MRdTrig Master Read Response Trigger + * 0: With first valid read data + * 1: With last valid read data + * 12:12 CleanBlock Clean Block Snoop Transaction Support + * 0: CPU does not support clean block (603e,750) + * 1: CPU supports clean block (604e,G4) + * 13:13 FlushBlock Flush Block Snoop Transaction Support + * 0: CPU does not support flush block (603e,750) + * 1: CPU supports flush block (604e,G4) + * 31:14 Reserved + */ +#define GT_CPUMstrCtl_IntArb GT__BIT(8) +#define GT_CPUMstrCtl_IntBusCtl GT__BIT(9) +#define GT_CPUMstrCtl_MWrTrig GT__BIT(10) +#define GT_CPUMstrCtl_MRdTrig GT__BIT(11) +#define GT_CPUMstrCtl_CleanBlock GT__BIT(12) +#define GT_CPUMstrCtl_FlushBlock GT__BIT(13) + +#define GT_ArbSlice_SDRAM 0x0 /* SDRAM interface snoop request */ +#define GT_ArbSlice_DEVICE 0x1 /* Device request */ +#define GT_ArbSlice_NULL 0x2 /* NULL request */ +#define GT_ArbSlice_PCI0 0x3 /* PCI_0 access */ +#define GT_ArbSlice_PCI1 0x4 /* PCI_1 access */ +#define GT_ArbSlice_COMM 0x5 /* Comm unit access */ +#define GT_ArbSlice_IDMA0123 0x6 /* IDMA channels 0/1/2/3 access */ +#define GT_ArbSlice_IDMA4567 0x7 /* IDMA channels 4/5/6/7 access */ + /* 0x8-0xf: Reserved */ + +/* Pass in the slice number (from 0..16) as 'n' + */ +#define GT_XbarCtl_GET_ArbSlice(v, n) GT__EXT((v), (((n) & 7)*4, 4) + +/* + * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150 + * 03:00 Arb0 Slice 0 of CPU Master pizza Arbiter + * 07:04 Arb1 Slice 1 of CPU Master pizza Arbiter + * 11:08 Arb2 Slice 2 of CPU Master pizza Arbiter + * 15:12 Arb3 Slice 3 of CPU Master pizza Arbiter + * 19:16 Arb4 Slice 4 of CPU Master pizza Arbiter + * 23:20 Arb5 Slice 5 of CPU Master pizza Arbiter + * 27:24 Arb6 Slice 6 of CPU Master pizza Arbiter + * 31:28 Arb7 Slice 7 of CPU Master pizza Arbiter + */ + +/* + * Table 101: CPU Interface Crossbar Control High, Offset: 0x158 + * 03:00 Arb8 Slice 8 of CPU Master pizza Arbiter + * 07:04 Arb9 Slice 9 of CPU Master pizza Arbiter + * 11:08 Arb10 Slice 10 of CPU Master pizza Arbiter + * 15:12 Arb11 Slice 11 of CPU Master pizza Arbiter + * 19:16 Arb12 Slice 12 of CPU Master pizza Arbiter + * 23:20 Arb13 Slice 13 of CPU Master pizza Arbiter + * 27:24 Arb14 Slice 14 of CPU Master pizza Arbiter + * 31:28 Arb15 Slice 15 of CPU Master pizza Arbiter + */ + +/* + * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168 + * NOTE: Reserved for Galileo Technology usage. + * 07:00 Timeout Crossbar Arbiter Timeout Preset Value + * 15:08 Reserved + * 16:16 TimeoutEn Crossbar Arbiter Timer Enable + * (0: Enable; 1: Disable) + * 31:17 Reserved + */ + +/* + * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170 + * 03:00 Arb0 Slice 0 of CPU Slave pizza Arbiter + * 07:04 Arb1 Slice 1 of CPU Slave pizza Arbiter + * 11:08 Arb2 Slice 2 of CPU Slave pizza Arbiter + * 15:12 Arb3 Slice 3 of CPU Slave pizza Arbiter + * 19:16 Arb4 Slice 4 of CPU Slave pizza Arbiter + * 23:20 Arb5 Slice 5 of CPU Slave pizza Arbiter + * 27:24 Arb6 Slice 6 of CPU Slave pizza Arbiter + * 31:28 Arb7 Slice 7 of CPU Slave pizza Arbiter + */ +/* + * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178 + * 03:00 Arb8 Slice 8 of CPU Slave pizza Arbiter + * 07:04 Arb9 Slice 9 of CPU Slave pizza Arbiter + * 11:08 Arb10 Slice 10 of CPU Slave pizza Arbiter + * 15:12 Arb11 Slice 11 of CPU Slave pizza Arbiter + * 19:16 Arb12 Slice 12 of CPU Slave pizza Arbiter + * 23:20 Arb13 Slice 13 of CPU Slave pizza Arbiter + * 27:24 Arb14 Slice 14 of CPU Slave pizza Arbiter + * 31:28 Arb15 Slice 15 of CPU Slave pizza Arbiter + */ + +/* + * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0 + * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8 + * NOTE: The read data is random and should be ignored. + * 31:00 SyncBarrier A CPU read from this register creates a + * synchronization barrier cycle. + */ + +/* + * Table 107: CPU Protect Address 0 Low, Offset: 0x180 + * Table 109: CPU Protect Address 1 Low, Offset: 0x190 + * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0 + * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0 + * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0 + * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0 + * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0 + * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0 + * + * 11:00 LowAddr CPU Protect Region Base Address + * Corresponds to address bits[31:20]. + * 15:12 Reserved. Must be 0 + * 16:16 AccProtect CPU Access Protect + * Access is (0: allowed; 1: forbidden) + * 17:17 WrProtect CPU Write Protect + * Writes are (0: allowed; 1: forbidden) + * 18:18 CacheProtect CPU caching protect. Caching (block read) + * is (0: allowed; 1: forbidden) + * 31:19 Reserved + */ +#define GT_CPU_AccProtect GT__BIT(16) +#define GT_CPU_WrProtect GT__BIT(17) +#define GT_CPU_CacheProtect GT__BIT(18) + +/* + * Table 108: CPU Protect Address 0 High, Offset: 0x188 + * Table 110: CPU Protect Address 1 High, Offset: 0x198 + * Table 112: CPU Protect Address 2 High, Offset: 0x1a8 + * Table 114: CPU Protect Address 3 High, Offset: 0x1b8 + * Table 116: CPU Protect Address 4 High, Offset: 0x1c8 + * Table 118: CPU Protect Address 5 High, Offset: 0x1d8 + * Table 120: CPU Protect Address 6 High, Offset: 0x1e8 + * Table 122: CPU Protect Address 7 High, Offset: 0x1f8 + * + * 11:00 HighAddr CPU Protect Region Top Address + * Corresponds to address bits[31:20] + * 31:12 Reserved + */ + +/* + * Table 123: Snoop Base Address 0, Offset: 0x380 + * Table 125: Snoop Base Address 1, Offset: 0x390 + * Table 127: Snoop Base Address 2, Offset: 0x3a0 + * Table 129: Snoop Base Address 3, Offset: 0x3b0 + * + * 11:00 LowAddr Snoop Region Base Address [31:20] + * 15:12 Reserved Must be 0. + * 17:16 Snoop Snoop Type + * 0x0: No Snoop + * 0x1: Snoop to WT region + * 0x2: Snoop to WB region + * 0x3: Reserved + * 31:18 Reserved + */ +#define GT_Snoop_GET(v) GT__EXT((v), 16, 2) +#define GT_Snoop_INS(v) GT__INS((v), 16) +#define GT_Snoop_None 0 +#define GT_Snoop_WT 1 +#define GT_Snoop_WB 2 + + +/* + * Table 124: Snoop Top Address 0, Offset: 0x388 + * Table 126: Snoop Top Address 1, Offset: 0x398 + * Table 128: Snoop Top Address 2, Offset: 0x3a8 + * Table 130: Snoop Top Address 3, Offset: 0x3b8 + * 11:00 HighAddr Snoop Region Top Address [31:20] + * 31:12 Reserved + */ + + +/* + * Table 131: CPU Error Address Low, Offset: 0x070, Read Only. + * In case of multiple errors, only the first one is latched. New error + * report latching is enabled only after the CPU Error Address Low register + * is being read. + * 31:00 ErrAddr Latched address bits [31:0] of a CPU + * transaction in case of: + * o illegal address (failed address decoding) + * o access protection violation + * o bad data parity + * o bad address parity + * Upon address latch, no new address are + * registered (due to additional error condition), + * until the register is being read. + */ + +/* + * Table 132: CPU Error Address High, Offset: 0x078, Read Only. + * Once data is latched, no new data can be registered (due to additional + * error condition), until CPU Error Low Address is being read (which + * implies, it should be the last being read by the interrupt handler). + * 03:00 Reserved + * 07:04 ErrPar Latched address parity bits in case + * of bad CPU address parity detection. + * 31:08 Reserved + */ +#define GT_CPUErrorAddrHigh_ErrPar_GET(v) GT__EXT((v), 4, 4) + +/* + * Table 133: CPU Error Data Low, Offset: 0x128, Read only. + * 31:00 PErrData Latched data bits [31:0] in case of bad data + * parity sampled on write transactions or on + * master read transactions. + */ + +/* + * Table 134: CPU Error Data High, Offset: 0x130, Read only. + * 31:00 PErrData Latched data bits [63:32] in case of bad data + * parity sampled on write transactions or on + * master read transactions. + */ + +/* + * Table 135: CPU Error Parity, Offset: 0x138, Read only. + * 07:00 PErrPar Latched data parity bus in case of bad data + * parity sampled on write transactions or on + * master read transactions. + * 31:10 Reserved + */ +#define GT_CPUErrorParity_PErrPar_GET(v) GT__EXT((v), 0, 8) + +/* + * Table 136: CPU Error Cause, Offset: 0x140 + * Bits[7:0] are clear only. A cause bit is set upon an error condition + * occurrence. Write a 0 value to clear the bit. Writing a 1 value has + * no affect. + * 00:00 AddrOut CPU Address Out of Range + * 01:01 AddrPErr Bad Address Parity Detected + * 02:02 TTErr Transfer Type Violation. + * The CPU attempts to burst (read or write) to an + * internal register. + * 03:03 AccErr Access to a Protected Region + * 04:04 WrErr Write to a Write Protected Region + * 05:05 CacheErr Read from a Caching protected region + * 06:06 WrDataPErr Bad Write Data Parity Detected + * 07:07 RdDataPErr Bad Read Data Parity Detected + * 26:08 Reserved + * 31:27 Sel Specifies the error event currently being + * reported in Error Address, Error Data, and + * Error Parity registers. + * 0x0: AddrOut + * 0x1: AddrPErr + * 0x2: TTErr + * 0x3: AccErr + * 0x4: WrErr + * 0x5: CacheErr + * 0x6: WrDataPErr + * 0x7: RdDataPErr + * 0x8-0x1f: Reserved + */ +#define GT_CPUError_AddrOut GT__BIT(GT_CPUError_Sel_AddrOut) +#define GT_CPUError_AddrPErr GT__BIT(GT_CPUError_Sel_AddrPErr) +#define GT_CPUError_TTErr GT__BIT(GT_CPUError_Sel_TTErr) +#define GT_CPUError_AccErr GT__BIT(GT_CPUError_Sel_AccErr) +#define GT_CPUError_WrErr GT__BIT(GT_CPUError_Sel_WrPErr) +#define GT_CPUError_CacheErr GT__BIT(GT_CPUError_Sel_CachePErr) +#define GT_CPUError_WrDataPErr GT__BIT(GT_CPUError_Sel_WrDataPErr) +#define GT_CPUError_RdDataPErr GT__BIT(GT_CPUError_Sel_RdDataPErr) + +#define GT_CPUError_Sel_AddrOut 0 +#define GT_CPUError_Sel_AddrPErr 1 +#define GT_CPUError_Sel_TTErr 2 +#define GT_CPUError_Sel_AccErr 3 +#define GT_CPUError_Sel_WrErr 4 +#define GT_CPUError_Sel_CacheErr 5 +#define GT_CPUError_Sel_WrDataPErr 6 +#define GT_CPUError_Sel_RdDataPErr 7 + +#define GT_CPUError_Sel_GET(v) GT__EXT((v), 27, 5) + +/* + * Table 137: CPU Error Mask, Offset: 0x148 + * 00:00 AddrOut If set to 1, enables AddrOut interrupt. + * 01:01 AddrPErr If set to 1, enables AddrPErr interrupt. + * 02:02 TTErr If set to 1, enables TTErr interrupt. + * 03:03 AccErr If set to 1, enables AccErr interrupt. + * 04:04 WrErr If set to 1, enables WrErr interrupt. + * 05:05 CacheErr If set to 1, enables CacheErr interrupt. + * 06:06 WrDataPErr If set to 1, enables WrDataPErr interrupt. + * 07:07 RdDataPErr If set to 1, enables RdDataPErr interrupt. + * 31:08 Reserved + */ + +/* Comm Unit Arbiter Control */ +#define GT_CommUnitArb_Ctrl 0xf300 /**/ +/* + * Comm Unit Interrupt registers + */ +#define GT_CommUnitIntr_Cause 0xf310 +#define GT_CommUnitIntr_Mask 0xf314 +#define GT_CommUnitIntr_ErrAddr 0xf318 + +#define GT_CommUnitIntr_E0 0x00000007 +#define GT_CommUnitIntr_E1 0x00000070 +#define GT_CommUnitIntr_E2 0x00000700 +#define GT_CommUnitIntr_S0 0x00070000 +#define GT_CommUnitIntr_S1 0x00700000 +#define GT_CommUnitIntr_Sel 0x70000000 + +/* + * SDRAM Error Report (ECC) Registers + */ +#define GT_ECC_Data_Lo 0x484 /* latched Error Data (low) */ +#define GT_ECC_Data_Hi 0x480 /* latched Error Data (high) */ +#define GT_ECC_Addr 0x490 /* latched Error Address */ +#define GT_ECC_Rec 0x488 /* latched ECC code from SDRAM */ +#define GT_ECC_Calc 0x48c /* latched ECC code from SDRAM */ +#define GT_ECC_Ctl 0x494 /* ECC Control */ +#define GT_ECC_Count 0x498 /* ECC 1-bit error count */ + +/* + * Watchdog Registers + */ +#define GT_WDOG_Config 0xb410 +#define GT_WDOG_Value 0xb414 +#define GT_WDOG_Value_NMI GT__MASK(24) +#define GT_WDOG_Config_Preset GT__MASK(24) +#define GT_WDOG_Config_Ctl1a GT__BIT(24) +#define GT_WDOG_Config_Ctl1b GT__BIT(25) +#define GT_WDOG_Config_Ctl2a GT__BIT(26) +#define GT_WDOG_Config_Ctl2b GT__BIT(27) +#define GT_WDOG_Config_Enb GT__BIT(31) + +#define GT_WDOG_NMI_DFLT (GT__MASK(24) & GT_WDOG_Value_NMI) +#define GT_WDOG_Preset_DFLT (GT__MASK(22) & GT_WDOG_Config_Preset) + +/* + * Device Bus Interrupts + */ +#define GT_DEVBUS_ICAUSE 0x4d0 /* Device Interrupt Cause */ +#define GT_DEVBUS_IMASK 0x4d4 /* Device Interrupt Mask */ +#define GT_DEVBUS_ERR_ADDR 0x4d8 /* Device Error Address */ + +/* + * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK + */ +#define GT_DEVBUS_DBurstErr GT__BIT(0) +#define GT_DEVBUS_DRdyErr GT__BIT(1) +#define GT_DEVBUS_Sel GT__BIT(27) +#define GT_DEVBUS_RES ~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel) + +/* TWSI Interface - TWSI Interface Registers */ +#define TWSI_SLV_ADDR 0xc000 +#define TWSI_EXT_SLV_ADDR 0xc010 +#define TWSI_DATA 0xc004 +#define TWSI_CTRL 0xc008 +#define TWSI_STATUS 0xc00c +#define TWSI_BAUDE_RATE 0xc00c +#define TWSI_SFT_RST 0xc01c + +/* Section 25.2 : Table 734 */ + +#define GT64260_MAIN_INT_CAUSE_LO 0xc18 /* read Only */ +#define GT64260_MAIN_INT_CAUSE_HI 0xc68 /* read Only */ +#define GT64260_CPU_INT_MASK_LO 0xc1c +#define GT64260_CPU_INT_MASK_HI 0xc6c +#define GT64260_CPU_SEL_CAUSE 0xc70 /* read Only */ +#define GT_PCI0_INT_MASK_LO 0xc24 +#define GT_PCI0_INT_MASK_HI 0xc64 +#define GT_PCI0_SEL_CAUSE 0xc74 /* read Only */ +#define GT_PCI1_INT_MASK_LO 0xca4 +#define GT_PCI1_INT_MASK_HI 0xce4 +#define GT_PCI1_SEL_CAUSE 0xcf4 /* read Only */ +#define GT_CPU_INT0_MASK 0xe60 +#define GT_CPU_INT1_MASK 0xe64 +#define GT_CPU_INT2_MASK 0xe68 +#define GT_CPU_INT3_MASK 0xe6c + +#endif /* !_DISCOVERY_DEV_GTREG_H */ diff --git a/bsps/powerpc/mvme5500/include/bsp/if_wmreg.h b/bsps/powerpc/mvme5500/include/bsp/if_wmreg.h new file mode 100644 index 0000000000..3e21c62581 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/if_wmreg.h @@ -0,0 +1,740 @@ +/* $NetBSD: if_wmreg.h,v 1.22 2007/04/29 20:35:21 bouyer Exp $ */ + +/* + * Copyright (c) 2001 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * Some are added by Shuchen Kate Feng , + * NSLS, Brookhaven National Laboratory. All rights reserved. + * under the Deaprtment of Energy contract DE-AC02-98CH10886 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Register description for the Intel i82542 (``Wiseman''), + * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit + * Ethernet chips. + */ + +/* + * The wiseman supports 64-bit PCI addressing. This structure + * describes the address in descriptors. + */ +typedef struct wiseman_addr { + uint32_t wa_low; /* low-order 32 bits */ + uint32_t wa_high; /* high-order 32 bits */ +} __attribute__((__packed__)) wiseman_addr_t; + +/* + * The Wiseman receive descriptor. + * + * The receive descriptor ring must be aligned to a 4K boundary, + * and there must be an even multiple of 8 descriptors in the ring. + */ +typedef volatile struct wiseman_rxdesc { + wiseman_addr_t wrx_addr; /* buffer address */ + + uint16_t wrx_len; /* buffer length */ + uint16_t wrx_cksum; /* checksum (starting at PCSS) */ + + uint8_t wrx_status; /* Rx status */ + uint8_t wrx_errors; /* Rx errors */ + uint16_t wrx_special; /* special field (VLAN, etc.) */ +} __attribute__((__packed__)) wiseman_rxdesc_t; + +/* wrx_status bits */ +#define WRX_ST_DD (1U << 0) /* descriptor done */ +#define WRX_ST_EOP (1U << 1) /* end of packet */ +#define WRX_ST_IXSM (1U << 2) /* ignore checksum indication */ +#define WRX_ST_VP (1U << 3) /* VLAN packet */ +#define WRX_ST_BPDU (1U << 4) /* ??? */ +#define WRX_ST_TCPCS (1U << 5) /* TCP checksum performed */ +#define WRX_ST_IPCS (1U << 6) /* IP checksum performed */ +#define WRX_ST_PIF (1U << 7) /* passed in-exact filter */ + +/* wrx_error bits */ +#define WRX_ER_CE (1U << 0) /* CRC error */ +#define WRX_ER_SE (1U << 1) /* symbol error */ +#define WRX_ER_SEQ (1U << 2) /* sequence error */ +#define WRX_ER_ICE (1U << 3) /* ??? */ +#define WRX_ER_CXE (1U << 4) /* carrier extension error */ +#define WRX_ER_TCPE (1U << 5) /* TCP checksum error */ +#define WRX_ER_IPE (1U << 6) /* IP checksum error */ +#define WRX_ER_RXE (1U << 7) /* Rx data error */ + +/* wrx_special field for VLAN packets */ +#define WRX_VLAN_ID(x) ((x) & 0x0fff) /* VLAN identifier */ +#define WRX_VLAN_CFI (1U << 12) /* Canonical Form Indicator */ +#define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */ + +/* + * The Wiseman transmit descriptor. + * + * The transmit descriptor ring must be aligned to a 4K boundary, + * and there must be an even multiple of 8 descriptors in the ring. + */ +typedef struct wiseman_tx_fields { + uint8_t wtxu_status; /* Tx status */ + uint8_t wtxu_options; /* options */ + uint16_t wtxu_vlan; /* VLAN info */ +} __attribute__((__packed__)) wiseman_txfields_t; +typedef volatile struct wiseman_txdesc { + wiseman_addr_t wtx_addr; /* buffer address */ + uint32_t wtx_cmdlen; /* command and length */ + wiseman_txfields_t wtx_fields; /* fields; see below */ +} __attribute__((__packed__)) wiseman_txdesc_t; + +/* Commands for wtx_cmdlen */ +#define WTX_CMD_EOP (1U << 24) /* end of packet */ +#define WTX_CMD_IFCS (1U << 25) /* insert FCS */ +#define WTX_CMD_RS (1U << 27) /* report status */ +#define WTX_CMD_RPS (1U << 28) /* report packet sent */ +#define WTX_CMD_DEXT (1U << 29) /* descriptor extension */ +#define WTX_CMD_VLE (1U << 30) /* VLAN enable */ +#define WTX_CMD_IDE (1U << 31) /* interrupt delay enable */ + +/* Descriptor types (if DEXT is set) */ +#define WTX_DTYP_C (0U << 20) /* context */ +#define WTX_DTYP_D (1U << 20) /* data */ + +/* wtx_fields status bits */ +#define WTX_ST_DD (1U << 0) /* descriptor done */ +#define WTX_ST_EC (1U << 1) /* excessive collisions */ +#define WTX_ST_LC (1U << 2) /* late collision */ +#define WTX_ST_TU (1U << 3) /* transmit underrun */ + +/* wtx_fields option bits for IP/TCP/UDP checksum offload */ +#define WTX_IXSM (1U << 0) /* IP checksum offload */ +#define WTX_TXSM (1U << 1) /* TCP/UDP checksum offload */ + +/* Maximum payload per Tx descriptor */ +#define WTX_MAX_LEN 4096 + +/* + * The Livengood TCP/IP context descriptor. + */ +struct livengood_tcpip_ctxdesc { + uint32_t tcpip_ipcs; /* IP checksum context */ + uint32_t tcpip_tucs; /* TCP/UDP checksum context */ + uint32_t tcpip_cmdlen; + uint32_t tcpip_seg; /* TCP segmentation context */ +}; + +/* commands for context descriptors */ +#define WTX_TCPIP_CMD_TCP (1U << 24) /* 1 = TCP, 0 = UDP */ +#define WTX_TCPIP_CMD_IP (1U << 25) /* 1 = IPv4, 0 = IPv6 */ +#define WTX_TCPIP_CMD_TSE (1U << 26) /* segmentation context valid */ + +#define WTX_TCPIP_IPCSS(x) ((x) << 0) /* checksum start */ +#define WTX_TCPIP_IPCSO(x) ((x) << 8) /* checksum value offset */ +#define WTX_TCPIP_IPCSE(x) ((x) << 16) /* checksum end */ + +#define WTX_TCPIP_TUCSS(x) ((x) << 0) /* checksum start */ +#define WTX_TCPIP_TUCSO(x) ((x) << 8) /* checksum value offset */ +#define WTX_TCPIP_TUCSE(x) ((x) << 16) /* checksum end */ + +#define WTX_TCPIP_SEG_STATUS(x) ((x) << 0) +#define WTX_TCPIP_SEG_HDRLEN(x) ((x) << 8) +#define WTX_TCPIP_SEG_MSS(x) ((x) << 16) + +/* + * PCI config registers used by the Wiseman. + */ +#define WM_PCI_MMBA PCI_MAPREG_START +/* registers for FLASH access on ICH8 */ +#define WM_ICH8_FLASH 0x0014 + +/* + * Wiseman Control/Status Registers. + */ +#define WMREG_CTRL 0x0000 /* Device Control Register */ +#define CTRL_FD (1U << 0) /* full duplex */ +#define CTRL_BEM (1U << 1) /* big-endian mode */ +#define CTRL_PRIOR (1U << 2) /* 0 = receive, 1 = fair */ +#define CTRL_LRST (1U << 3) /* link reset */ +#define CTRL_ASDE (1U << 5) /* auto speed detect enable */ +#define CTRL_SLU (1U << 6) /* set link up */ +#define CTRL_ILOS (1U << 7) /* invert loss of signal */ +#define CTRL_SPEED(x) ((x) << 8) /* speed (Livengood) */ +#define CTRL_SPEED_10 CTRL_SPEED(0) +#define CTRL_SPEED_100 CTRL_SPEED(1) +#define CTRL_SPEED_1000 CTRL_SPEED(2) +#define CTRL_SPEED_MASK CTRL_SPEED(3) +#define CTRL_FRCSPD (1U << 11) /* force speed (Livengood) */ +#define CTRL_FRCFDX (1U << 12) /* force full-duplex (Livengood) */ +#define CTRL_D_UD_EN (1U << 13) /* Dock/Undock enable */ +#define CTRL_D_UD_POL (1U << 14) /* Defined polarity of Dock/Undock indication in SDP[0] */ +#define CTRL_F_PHY_R (1U << 15) /* Reset both PHY ports, through PHYRST_N pin */ +#define CTRL_EXT_LINK_EN (1U << 16) /* enable link status from external LINK_0 and LINK_1 pins */ +#define CTRL_SWDPINS_SHIFT 18 +#define CTRL_SWDPINS_MASK 0x0f +#define CTRL_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x))) +#define CTRL_SWDPIO_SHIFT 22 +#define CTRL_SWDPIO_MASK 0x0f +#define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x))) +#define CTRL_RST (1U << 26) /* device reset */ +#define CTRL_RFCE (1U << 27) /* Rx flow control enable */ +#define CTRL_TFCE (1U << 28) /* Tx flow control enable */ +#define CTRL_VME (1U << 30) /* VLAN Mode Enable */ +#define CTRL_PHY_RESET (1U << 31) /* PHY reset (Cordova) */ + +#define WMREG_CTRL_SHADOW 0x0004 /* Device Control Register (shadow) */ + +#define WMREG_STATUS 0x0008 /* Device Status Register */ +#define STATUS_FD (1U << 0) /* full duplex */ +#define STATUS_LU (1U << 1) /* link up */ +#define STATUS_TCKOK (1U << 2) /* Tx clock running */ +#define STATUS_RBCOK (1U << 3) /* Rx clock running */ +#define STATUS_FUNCID_SHIFT 2 /* 82546 function ID */ +#define STATUS_FUNCID_MASK 3 /* ... */ +#define STATUS_TXOFF (1U << 4) /* Tx paused */ +#define STATUS_TBIMODE (1U << 5) /* fiber mode (Livengood) */ +#define STATUS_SPEED(x) ((x) << 6) /* speed indication */ +#define STATUS_SPEED_10 STATUS_SPEED(0) +#define STATUS_SPEED_100 STATUS_SPEED(1) +#define STATUS_SPEED_1000 STATUS_SPEED(2) +#define STATUS_ASDV(x) ((x) << 8) /* auto speed det. val. (Livengood) */ +#define STATUS_MTXCKOK (1U << 10) /* MTXD clock running */ +#define STATUS_PCI66 (1U << 11) /* 66MHz bus (Livengood) */ +#define STATUS_BUS64 (1U << 12) /* 64-bit bus (Livengood) */ +#define STATUS_PCIX_MODE (1U << 13) /* PCIX mode (Cordova) */ +#define STATUS_PCIXSPD(x) ((x) << 14) /* PCIX speed indication (Cordova) */ +#define STATUS_PCIXSPD_50_66 STATUS_PCIXSPD(0) +#define STATUS_PCIXSPD_66_100 STATUS_PCIXSPD(1) +#define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2) +#define STATUS_PCIXSPD_MASK STATUS_PCIXSPD(3) + +#define WMREG_EECD 0x0010 /* EEPROM Control Register */ +#define EECD_SK (1U << 0) /* clock */ +#define EECD_CS (1U << 1) /* chip select */ +#define EECD_DI (1U << 2) /* data in */ +#define EECD_DO (1U << 3) /* data out */ +#define EECD_FWE(x) ((x) << 4) /* flash write enable control */ +#define EECD_FWE_DISABLED EECD_FWE(1) +#define EECD_FWE_ENABLED EECD_FWE(2) +#define EECD_EE_REQ (1U << 6) /* (shared) EEPROM request */ +#define EECD_EE_GNT (1U << 7) /* (shared) EEPROM grant */ +#define EECD_EE_PRES (1U << 8) /* EEPROM present */ +#define EECD_EE_SIZE (1U << 9) /* EEPROM size + (0 = 64 word, 1 = 256 word) */ +#define EECD_EE_AUTORD (1U << 9) /* auto read done */ +#define EECD_EE_ABITS (1U << 10) /* EEPROM address bits + (based on type) */ +#define EECD_EE_TYPE (1U << 13) /* EEPROM type + (0 = Microwire, 1 = SPI) */ +#define EECD_SEC1VAL (1U << 22) /* Sector One Valid */ + +#define UWIRE_OPC_ERASE 0x04 /* MicroWire "erase" opcode */ +#define UWIRE_OPC_WRITE 0x05 /* MicroWire "write" opcode */ +#define UWIRE_OPC_READ 0x06 /* MicroWire "read" opcode */ + +#define SPI_OPC_WRITE 0x02 /* SPI "write" opcode */ +#define SPI_OPC_READ 0x03 /* SPI "read" opcode */ +#define SPI_OPC_A8 0x08 /* opcode bit 3 == address bit 8 */ +#define SPI_OPC_WREN 0x06 /* SPI "set write enable" opcode */ +#define SPI_OPC_WRDI 0x04 /* SPI "clear write enable" opcode */ +#define SPI_OPC_RDSR 0x05 /* SPI "read status" opcode */ +#define SPI_OPC_WRSR 0x01 /* SPI "write status" opcode */ +#define SPI_MAX_RETRIES 5000 /* max wait of 5ms for RDY signal */ + +#define SPI_SR_RDY 0x01 +#define SPI_SR_WEN 0x02 +#define SPI_SR_BP0 0x04 +#define SPI_SR_BP1 0x08 +#define SPI_SR_WPEN 0x80 + +#define EEPROM_OFF_MACADDR 0x00 /* MAC address offset */ +#define EEPROM_OFF_CFG1 0x0a /* config word 1 */ +#define EEPROM_OFF_CFG2 0x0f /* config word 2 */ +#define EEPROM_OFF_SWDPIN 0x20 /* SWD Pins (Cordova) */ + +#define EEPROM_CFG1_LVDID (1U << 0) +#define EEPROM_CFG1_LSSID (1U << 1) +#define EEPROM_CFG1_PME_CLOCK (1U << 2) +#define EEPROM_CFG1_PM (1U << 3) +#define EEPROM_CFG1_ILOS (1U << 4) +#define EEPROM_CFG1_SWDPIO_SHIFT 5 +#define EEPROM_CFG1_SWDPIO_MASK (0xf << EEPROM_CFG1_SWDPIO_SHIFT) +#define EEPROM_CFG1_IPS1 (1U << 8) +#define EEPROM_CFG1_LRST (1U << 9) +#define EEPROM_CFG1_FD (1U << 10) +#define EEPROM_CFG1_FRCSPD (1U << 11) +#define EEPROM_CFG1_IPS0 (1U << 12) +#define EEPROM_CFG1_64_32_BAR (1U << 13) + +#define EEPROM_CFG2_CSR_RD_SPLIT (1U << 1) +#define EEPROM_CFG2_APM_EN (1U << 2) +#define EEPROM_CFG2_64_BIT (1U << 3) +#define EEPROM_CFG2_MAX_READ (1U << 4) +#define EEPROM_CFG2_DMCR_MAP (1U << 5) +#define EEPROM_CFG2_133_CAP (1U << 6) +#define EEPROM_CFG2_MSI_DIS (1U << 7) +#define EEPROM_CFG2_FLASH_DIS (1U << 8) +#define EEPROM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9) +#define EEPROM_CFG2_ANE (1U << 11) +#define EEPROM_CFG2_PAUSE(x) (((x) & 3) >> 12) +#define EEPROM_CFG2_ASDE (1U << 14) +#define EEPROM_CFG2_APM_PME (1U << 15) +#define EEPROM_CFG2_SWDPIO_SHIFT 4 +#define EEPROM_CFG2_SWDPIO_MASK (0xf << EEPROM_CFG2_SWDPIO_SHIFT) + +#define EEPROM_SWDPIN_MASK 0xdf +#define EEPROM_SWDPIN_SWDPIN_SHIFT 0 +#define EEPROM_SWDPIN_SWDPIO_SHIFT 8 + +#define WMREG_EERD 0x0014 /* EEPROM read */ +#define EERD_DONE 0x02 /* done bit */ +#define EERD_START 0x01 /* First bit for telling part to start operation */ +#define EERD_ADDR_SHIFT 2 /* Shift to the address bits */ +#define EERD_DATA_SHIFT 16 /* Offset to data in EEPROM read/write registers */ + +#define WMREG_CTRL_EXT 0x0018 /* Extended Device Control Register */ +#define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */ +#define CTRL_EXT_SWDPINS_SHIFT 4 +#define CTRL_EXT_SWDPINS_MASK 0x0d +#define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT + (x) - 4)) +#define CTRL_EXT_SWDPIO_SHIFT 8 +#define CTRL_EXT_SWDPIO_MASK 0x0d +#define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT + (x) - 4)) +#define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */ +#define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */ +#define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */ +#define CTRL_EXT_SPD_BYPS (1U << 15) /* speed select bypass */ +#define CTRL_EXT_IPS1 (1U << 16) /* invert power state bit 1 */ +#define CTRL_EXT_RO_DIS (1U << 17) /* relaxed ordering disabled */ +#define CTRL_EXT_LINK_MODE_MASK 0x00C00000 +#define CTRL_EXT_LINK_MODE_GMII 0x00000000 +#define CTRL_EXT_LINK_MODE_TBI 0x00C00000 +#define CTRL_EXT_LINK_MODE_KMRN 0x00000000 +#define CTRL_EXT_LINK_MODE_SERDES 0x00C00000 + + +#define WMREG_MDIC 0x0020 /* MDI Control Register */ +#define MDIC_DATA(x) ((x) & 0xffff) +#define MDIC_REGADD(x) ((x) << 16) +#define MDIC_PHYADD(x) ((x) << 21) +#define MDIC_OP_WRITE (1U << 26) +#define MDIC_OP_READ (2U << 26) +#define MDIC_READY (1U << 28) +#define MDIC_I (1U << 29) /* interrupt on MDI complete */ +#define MDIC_E (1U << 30) /* MDI error */ + +#define WMREG_FCAL 0x0028 /* Flow Control Address Low */ +#define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */ + +#define WMREG_FCAH 0x002c /* Flow Control Address High */ +#define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */ + +#define WMREG_FCT 0x0030 /* Flow Control Type */ + +#define WMREG_VET 0x0038 /* VLAN Ethertype */ + +#define WMREG_RAL_BASE 0x0040 /* Receive Address List */ +#define WMREG_CORDOVA_RAL_BASE 0x5400 +#define WMREG_RAL_LO(b, x) ((b) + ((x) << 3)) +#define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4) + /* + * Receive Address List: The LO part is the low-order 32-bits + * of the MAC address. The HI part is the high-order 16-bits + * along with a few control bits. + */ +#define RAL_AS(x) ((x) << 16) /* address select */ +#define RAL_AS_DEST RAL_AS(0) /* (cordova?) */ +#define RAL_AS_SOURCE RAL_AS(1) /* (cordova?) */ +#define RAL_RDR1 (1U << 30) /* put packet in alt. rx ring */ +#define RAL_AV (1U << 31) /* entry is valid */ + +#define WM_RAL_TABSIZE 16 +#define WM_ICH8_RAL_TABSIZE 7 + +#define WMREG_ICR 0x00c0 /* Interrupt Cause Register */ +#define ICR_TXDW (1U << 0) /* Tx desc written back */ +#define ICR_TXQE (1U << 1) /* Tx queue empty */ +#define ICR_LSC (1U << 2) /* link status change */ +#define ICR_RXSEQ (1U << 3) /* receive sequence error */ +#define ICR_RXDMT0 (1U << 4) /* Rx ring 0 nearly empty */ +#define ICR_RXO (1U << 6) /* Rx overrun */ +#define ICR_RXT0 (1U << 7) /* Rx ring 0 timer */ +#define ICR_MDAC (1U << 9) /* MDIO access complete */ +#define ICR_RXCFG (1U << 10) /* Receiving /C/ */ +#define ICR_GPI(x) (1U << (x)) /* general purpose interrupts */ +#define ICR_INT (1U << 31) /* device generated an interrupt */ + +#define WMREG_ITR 0x00c4 /* Interrupt Throttling Register */ +#define ITR_IVAL_MASK 0xffff /* Interval mask */ +#define ITR_IVAL_SHIFT 0 /* Interval shift */ + +#define WMREG_ICS 0x00c8 /* Interrupt Cause Set Register */ + /* See ICR bits. */ + +#define WMREG_IMS 0x00d0 /* Interrupt Mask Set Register */ + /* See ICR bits. */ + +#define WMREG_IMC 0x00d8 /* Interrupt Mask Clear Register */ + /* See ICR bits. */ + +#define WMREG_RCTL 0x0100 /* Receive Control */ +#define RCTL_EN (1U << 1) /* receiver enable */ +#define RCTL_SBP (1U << 2) /* store bad packets */ +#define RCTL_UPE (1U << 3) /* unicast promisc. enable */ +#define RCTL_MPE (1U << 4) /* multicast promisc. enable */ +#define RCTL_LPE (1U << 5) /* large packet enable */ +#define RCTL_LBM(x) ((x) << 6) /* loopback mode */ +#define RCTL_LBM_NONE RCTL_LBM(0) +#define RCTL_LBM_PHY RCTL_LBM(3) +#define RCTL_RDMTS(x) ((x) << 8) /* receive desc. min thresh size */ +#define RCTL_RDMTS_1_2 RCTL_RDMTS(0) +#define RCTL_RDMTS_1_4 RCTL_RDMTS(1) +#define RCTL_RDMTS_1_8 RCTL_RDMTS(2) +#define RCTL_RDMTS_MASK RCTL_RDMTS(3) +#define RCTL_MO(x) ((x) << 12) /* multicast offset */ +#define RCTL_BAM (1U << 15) /* broadcast accept mode */ +#define RCTL_2k (0 << 16) /* 2k Rx buffers */ +#define RCTL_1k (1 << 16) /* 1k Rx buffers */ +#define RCTL_512 (2 << 16) /* 512 byte Rx buffers */ +#define RCTL_256 (3 << 16) /* 256 byte Rx buffers */ +#define RCTL_BSEX_16k (1 << 16) /* 16k Rx buffers (BSEX) */ +#define RCTL_BSEX_8k (2 << 16) /* 8k Rx buffers (BSEX) */ +#define RCTL_BSEX_4k (3 << 16) /* 4k Rx buffers (BSEX) */ +#define RCTL_DPF (1U << 22) /* discard pause frames */ +#define RCTL_PMCF (1U << 23) /* pass MAC control frames */ +#define RCTL_BSEX (1U << 25) /* buffer size extension (Livengood) */ +#define RCTL_SECRC (1U << 26) /* strip Ethernet CRC */ + +#define WMREG_OLD_RDTR0 0x0108 /* Receive Delay Timer (ring 0) */ +#define WMREG_RDTR 0x2820 +#define RDTR_FPD (1U << 31) /* flush partial descriptor */ + +#define WMREG_RADV 0x282c /* Receive Interrupt Absolute Delay Timer */ + +#define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */ +#define WMREG_RDBAL 0x2800 + +#define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */ +#define WMREG_RDBAH 0x2804 + +#define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */ +#define WMREG_RDLEN 0x2808 + +#define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */ +#define WMREG_RDH 0x2810 + +#define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */ +#define WMREG_RDT 0x2818 + +#define WMREG_RXDCTL 0x2828 /* Receive Descriptor Control */ +#define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ +#define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ +#define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ +#define RXDCTL_GRAN (1U << 24) /* 0 = cacheline, 1 = descriptor */ + +#define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */ + +#define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */ + +#define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */ + +#define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */ + +#define WMREG_OLD_RDH1 0x0148 + +#define WMREG_OLD_RDT1 0x0150 + +#define WMREG_OLD_FCRTH 0x0160 /* Flow Control Rx Threshold Hi (OLD) */ +#define WMREG_FCRTL 0x2160 /* Flow Control Rx Threshold Lo */ +#define FCRTH_DFLT 0x00008000 + +#define WMREG_OLD_FCRTL 0x0168 /* Flow Control Rx Threshold Lo (OLD) */ +#define WMREG_FCRTH 0x2168 /* Flow Control Rx Threhsold Hi */ +#define FCRTL_DFLT 0x00004000 +#define FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ + +#define WMREG_FCTTV 0x0170 /* Flow Control Transmit Timer Value */ +#define FCTTV_DFLT 0x00000600 + +#define WMREG_TXCW 0x0178 /* Transmit Configuration Word (TBI mode) */ + /* See MII ANAR_X bits. */ +#define TXCW_TxConfig (1U << 30) /* Tx Config */ +#define TXCW_ANE (1U << 31) /* Autonegotiate */ + +#define WMREG_RXCW 0x0180 /* Receive Configuration Word (TBI mode) */ + /* See MII ANLPAR_X bits. */ +#define RXCW_NC (1U << 26) /* no carrier */ +#define RXCW_IV (1U << 27) /* config invalid */ +#define RXCW_CC (1U << 28) /* config change */ +#define RXCW_C (1U << 29) /* /C/ reception */ +#define RXCW_SYNCH (1U << 30) /* synchronized */ +#define RXCW_ANC (1U << 31) /* autonegotiation complete */ + +#define WMREG_MTA 0x0200 /* Multicast Table Array */ +#define WMREG_CORDOVA_MTA 0x5200 + +#define WMREG_TCTL 0x0400 /* Transmit Control Register */ +#define TCTL_EN (1U << 1) /* transmitter enable */ +#define TCTL_PSP (1U << 3) /* pad short packets */ +#define TCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - collision threshold */ +#define TCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - collision distance */ +#define TCTL_SWXOFF (1U << 22) /* software XOFF */ +#define TCTL_RTLC (1U << 24) /* retransmit on late collision */ +#define TCTL_NRTU (1U << 25) /* no retransmit on underrun */ +#define TCTL_MULR (1U << 28) /* multiple request */ + +#define TX_COLLISION_THRESHOLD 15 +#define TX_COLLISION_DISTANCE_HDX 512 +#define TX_COLLISION_DISTANCE_FDX 64 + +#define WMREG_TCTL_EXT 0x0404 /* Transmit Control Register */ +#define TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ +#define TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ + +#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 + +#define WMREG_TQSA_LO 0x0408 + +#define WMREG_TQSA_HI 0x040c + +#define WMREG_TIPG 0x0410 /* Transmit IPG Register */ +#define TIPG_IPGT(x) (x) /* IPG transmit time */ +#define TIPG_IPGR1(x) ((x) << 10) /* IPG receive time 1 */ +#define TIPG_IPGR2(x) ((x) << 20) /* IPG receive time 2 */ + +#define TIPG_WM_DFLT (TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a)) +#define TIPG_LG_DFLT (TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) +#define TIPG_1000T_DFLT (TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) +#define TIPG_1000T_80003_DFLT \ + (TIPG_IPGT(0x08) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) +#define TIPG_10_100_80003_DFLT \ + (TIPG_IPGT(0x09) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) + +#define WMREG_TQC 0x0418 + +#define WMREG_EEWR 0x102c /* EEPROM write */ + +#define WMREG_RDFH 0x2410 /* Receive Data FIFO Head */ + +#define WMREG_RDFT 0x2418 /* Receive Data FIFO Tail */ + +#define WMREG_RDFHS 0x2420 /* Receive Data FIFO Head Saved */ + +#define WMREG_RDFTS 0x2428 /* Receive Data FIFO Tail Saved */ + +#define WMREG_TDFH 0x3410 /* Transmit Data FIFO Head */ + +#define WMREG_TDFT 0x3418 /* Transmit Data FIFO Tail */ + +#define WMREG_TDFHS 0x3420 /* Transmit Data FIFO Head Saved */ + +#define WMREG_TDFTS 0x3428 /* Transmit Data FIFO Tail Saved */ + +#define WMREG_TDFPC 0x3430 /* Transmit Data FIFO Packet Count */ + +#define WMREG_OLD_TBDAL 0x0420 /* Transmit Descriptor Base Lo */ +#define WMREG_TBDAL 0x3800 + +#define WMREG_OLD_TBDAH 0x0424 /* Transmit Descriptor Base Hi */ +#define WMREG_TBDAH 0x3804 + +#define WMREG_OLD_TDLEN 0x0428 /* Transmit Descriptor Length */ +#define WMREG_TDLEN 0x3808 + +#define WMREG_OLD_TDH 0x0430 /* Transmit Descriptor Head */ +#define WMREG_TDH 0x3810 + +#define WMREG_OLD_TDT 0x0438 /* Transmit Descriptor Tail */ +#define WMREG_TDT 0x3818 + +#define WMREG_OLD_TIDV 0x0440 /* Transmit Delay Interrupt Value */ +#define WMREG_TIDV 0x3820 + +#define WMREG_TXDCTL 0x3828 /* Trandmit Descriptor Control */ +#define TXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ +#define TXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ +#define TXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ + +#define WMREG_TADV 0x382c /* Transmit Absolute Interrupt Delay Timer */ + +#define WMREG_AIT 0x0458 /* Adaptive IFS Throttle */ + +#define WMREG_VFTA 0x0600 + +#define WM_MC_TABSIZE 128 +#define WM_ICH8_MC_TABSIZE 32 +#define WM_VLAN_TABSIZE 128 + +#define WMREG_PBA 0x1000 /* Packet Buffer Allocation */ +#define PBA_BYTE_SHIFT 10 /* KB -> bytes */ +#define PBA_ADDR_SHIFT 7 /* KB -> quadwords */ +#define PBA_8K 0x0008 +#define PBA_12K 0x000c +#define PBA_16K 0x0010 /* 16K, default Tx allocation */ +#define PBA_22K 0x0016 +#define PBA_24K 0x0018 +#define PBA_30K 0x001e +#define PBA_32K 0x0020 +#define PBA_40K 0x0028 +#define PBA_48K 0x0030 /* 48K, default Rx allocation */ + +#define WMREG_PBS 0x1000 /* Packet Buffer Size (ICH8 only ?) */ + +#define WMREG_TXDMAC 0x3000 /* Transfer DMA Control */ +#define TXDMAC_DPP (1U << 0) /* disable packet prefetch */ + +#define WMREG_TSPMT 0x3830 /* TCP Segmentation Pad and Minimum + Threshold (Cordova) */ +#define TSPMT_TSMT(x) (x) /* TCP seg min transfer */ +#define TSPMT_TSPBP(x) ((x) << 16) /* TCP seg pkt buf padding */ + +#define WMREG_RXCSUM 0x5000 /* Receive Checksum register */ +#define RXCSUM_PCSS 0x000000ff /* Packet Checksum Start */ +#define RXCSUM_IPOFL (1U << 8) /* IP checksum offload */ +#define RXCSUM_TUOFL (1U << 9) /* TCP/UDP checksum offload */ +#define RXCSUM_IPV6OFL (1U << 10) /* IPv6 checksum offload */ + +#define WMREG_RXERRC 0x400C /* receive error Count - R/clr */ +#define WMREG_COLC 0x4028 /* collision Count - R/clr */ +#define WMREG_XONRXC 0x4048 /* XON Rx Count - R/clr */ +#define WMREG_XONTXC 0x404c /* XON Tx Count - R/clr */ +#define WMREG_XOFFRXC 0x4050 /* XOFF Rx Count - R/clr */ +#define WMREG_XOFFTXC 0x4054 /* XOFF Tx Count - R/clr */ +#define WMREG_FCRUC 0x4058 /* Flow Control Rx Unsupported Count - R/clr */ + +#define WMREG_KUMCTRLSTA 0x0034 /* MAC-PHY interface - RW */ +#define KUMCTRLSTA_MASK 0x0000FFFF +#define KUMCTRLSTA_OFFSET 0x001F0000 +#define KUMCTRLSTA_OFFSET_SHIFT 16 +#define KUMCTRLSTA_REN 0x00200000 + +#define KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 +#define KUMCTRLSTA_OFFSET_CTRL 0x00000001 +#define KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 +#define KUMCTRLSTA_OFFSET_DIAG 0x00000003 +#define KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 +#define KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 +#define KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 +#define KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E +#define KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F + +/* FIFO Control */ +#define KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 +#define KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 + +/* In-Band Control */ +#define KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x00000500 +#define KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 + +/* Half-Duplex Control */ +#define KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 +#define KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 + +#define WMREG_MDPHYA 0x003C /* PHY address - RW */ + +#define WMREG_MANC2H 0x5860 /* Managment Control To Host - RW */ + +#define WMREG_SWSM 0x5b50 /* SW Semaphore */ +#define SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ +#define SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ +#define SWSM_WMNG 0x00000004 /* Wake MNG Clock */ +#define SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ + +#define WMREG_SW_FW_SYNC 0x5b5c /* software-firmware semaphore */ +#define SWFW_EEP_SM 0x0001 /* eeprom access */ +#define SWFW_PHY0_SM 0x0002 /* first ctrl phy access */ +#define SWFW_PHY1_SM 0x0004 /* second ctrl phy access */ +#define SWFW_MAC_CSR_SM 0x0008 +#define SWFW_SOFT_SHIFT 0 /* software semaphores */ +#define SWFW_FIRM_SHIFT 16 /* firmware semaphores */ + +#define WMREG_EXTCNFCTR 0x0f00 /* Extended Configuration Control */ +#define EXTCNFCTR_PCIE_WRITE_ENABLE 0x00000001 +#define EXTCNFCTR_PHY_WRITE_ENABLE 0x00000002 +#define EXTCNFCTR_D_UD_ENABLE 0x00000004 +#define EXTCNFCTR_D_UD_LATENCY 0x00000008 +#define EXTCNFCTR_D_UD_OWNER 0x00000010 +#define EXTCNFCTR_MDIO_SW_OWNERSHIP 0x00000020 +#define EXTCNFCTR_MDIO_HW_OWNERSHIP 0x00000040 +#define EXTCNFCTR_EXT_CNF_POINTER 0x0FFF0000 +#define E1000_EXTCNF_CTRL_SWFLAG EXTCNFCTR_MDIO_SW_OWNERSHIP + +/* ich8 flash control */ +#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ +#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ +#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ +#define ICH_FLASH_SEG_SIZE_256 256 +#define ICH_FLASH_SEG_SIZE_4K 4096 +#define ICH_FLASH_SEG_SIZE_64K 65536 + +#define ICH_CYCLE_READ 0x0 +#define ICH_CYCLE_RESERVED 0x1 +#define ICH_CYCLE_WRITE 0x2 +#define ICH_CYCLE_ERASE 0x3 + +#define ICH_FLASH_GFPREG 0x0000 +#define ICH_FLASH_HSFSTS 0x0004 /* Flash Status Register */ +#define HSFSTS_DONE 0x0001 /* Flash Cycle Done */ +#define HSFSTS_ERR 0x0002 /* Flash Cycle Error */ +#define HSFSTS_DAEL 0x0004 /* Direct Access error Log */ +#define HSFSTS_ERSZ_MASK 0x0018 /* Block/Sector Erase Size */ +#define HSFSTS_ERSZ_SHIFT 3 +#define HSFSTS_FLINPRO 0x0020 /* flash SPI cycle in Progress */ +#define HSFSTS_FLDVAL 0x4000 /* Flash Descriptor Valid */ +#define HSFSTS_FLLK 0x8000 /* Flash Configuration Lock-Down */ +#define ICH_FLASH_HSFCTL 0x0006 /* Flash control Register */ +#define HSFCTL_GO 0x0001 /* Flash Cycle Go */ +#define HSFCTL_CYCLE_MASK 0x0006 /* Flash Cycle */ +#define HSFCTL_CYCLE_SHIFT 1 +#define HSFCTL_BCOUNT_MASK 0x0300 /* Data Byte Count */ +#define HSFCTL_BCOUNT_SHIFT 8 +#define ICH_FLASH_FADDR 0x0008 +#define ICH_FLASH_FDATA0 0x0010 +#define ICH_FLASH_FRACC 0x0050 +#define ICH_FLASH_FREG0 0x0054 +#define ICH_FLASH_FREG1 0x0058 +#define ICH_FLASH_FREG2 0x005C +#define ICH_FLASH_FREG3 0x0060 +#define ICH_FLASH_FPR0 0x0074 +#define ICH_FLASH_FPR1 0x0078 +#define ICH_FLASH_SSFSTS 0x0090 +#define ICH_FLASH_SSFCTL 0x0092 +#define ICH_FLASH_PREOP 0x0094 +#define ICH_FLASH_OPTYPE 0x0096 +#define ICH_FLASH_OPMENU 0x0098 + +#define ICH_FLASH_REG_MAPSIZE 0x00A0 +#define ICH_FLASH_SECTOR_SIZE 4096 +#define ICH_GFPREG_BASE_MASK 0x1FFF +#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF + +/* start of Kate Feng added */ +#define WMREG_GPTC 0x4080 /* Good packets transmitted count */ +#define WMREG_GPRC 0x4074 /* Good packets received count */ +#define WMREG_CRCERRS 0x4000 /* CRC Error Count */ +#define WMREG_RLEC 0x4040 /* Receive Length Error Count */ +/* end of Kate Feng added */ diff --git a/bsps/powerpc/mvme5500/include/bsp/irq.h b/bsps/powerpc/mvme5500/include/bsp/irq.h new file mode 100644 index 0000000000..6704c2f626 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/irq.h @@ -0,0 +1,137 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Copyright 2004, 2005 Brookhaven National Laboratory and + * Shuchen Kate Feng + * + * - modified shared/irq/irq.h for Mvme5500 (no ISA devices/PIC) + * - Discovery GT64260 interrupt controller instead of 8259. + * - Added support for software IRQ priority levels. + * - modified to optimize the IRQ latency and handling + */ + +#ifndef LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H +#define LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 +#include + +#ifndef ASM + +#define OneTierIrqPrioTbl 1 + +/* + * Symbolic IRQ names and related definitions. + */ + +/* leave the ISA symbols in there, so we can reuse shared/irq.c + * Also, we start numbering PCI irqs at 16 because the OPENPIC + * driver relies on this when mapping irq number <-> vectors + * (OPENPIC_VEC_SOURCE in openpic.h) + */ + + /* See section 25.2 , Table 734 of GT64260 controller + * Main Interrupt Cause Low register + */ +#define BSP_MICL_IRQ_NUMBER (32) +#define BSP_MICL_IRQ_LOWEST_OFFSET (0) +#define BSP_MICL_IRQ_MAX_OFFSET (BSP_MICL_IRQ_LOWEST_OFFSET + BSP_MICL_IRQ_NUMBER -1) + /* + * Main Interrupt Cause High register + */ +#define BSP_MICH_IRQ_NUMBER (32) +#define BSP_MICH_IRQ_LOWEST_OFFSET (BSP_MICL_IRQ_MAX_OFFSET+1) +#define BSP_MICH_IRQ_MAX_OFFSET (BSP_MICH_IRQ_LOWEST_OFFSET + BSP_MICH_IRQ_NUMBER -1) + /* External GPP Interrupt assignements + */ +#define BSP_GPP_IRQ_NUMBER (32) +#define BSP_GPP_IRQ_LOWEST_OFFSET (BSP_MICH_IRQ_MAX_OFFSET+1) +#define BSP_GPP_IRQ_MAX_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET + BSP_GPP_IRQ_NUMBER - 1) + + /* + * PowerPc exceptions handled as interrupt where a rtems managed interrupt + * handler might be connected + */ +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_GPP_IRQ_MAX_OFFSET + 1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) + + /* allow a couple of vectors for VME and counter/timer irq sources etc. + * This is probably not needed any more. + */ +#define BSP_MISC_IRQ_NUMBER (30) +#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) + + /* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) +#define BSP_MAIN_IRQ_NUMBER (64) +#define BSP_PIC_IRQ_NUMBER (96) +#define BSP_LOWEST_OFFSET (BSP_MICL_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) + + /* Main CPU interrupt cause (Low) */ +#define BSP_MAIN_TIMER0_1_IRQ (BSP_MICL_IRQ_LOWEST_OFFSET+8) +#define BSP_MAIN_PCI0_7_0 (BSP_MICL_IRQ_LOWEST_OFFSET+12) +#define BSP_MAIN_PCI0_15_8 (BSP_MICL_IRQ_LOWEST_OFFSET+13) +#define BSP_MAIN_PCI0_23_16 (BSP_MICL_IRQ_LOWEST_OFFSET+14) +#define BSP_MAIN_PCI0_31_24 (BSP_MICL_IRQ_LOWEST_OFFSET+15) +#define BSP_MAIN_PCI1_7_0 (BSP_MICL_IRQ_LOWEST_OFFSET+16) +#define BSP_MAIN_PCI1_15_8 (BSP_MICL_IRQ_LOWEST_OFFSET+18) +#define BSP_MAIN_PCI1_23_16 (BSP_MICL_IRQ_LOWEST_OFFSET+19) +#define BSP_MAIN_PCI1_31_24 (BSP_MICL_IRQ_LOWEST_OFFSET+20) + + + /* Main CPU interrupt cause (High) */ +#define BSP_MAIN_ETH0_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET) +#define BSP_MAIN_ETH1_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+1) +#define BSP_MAIN_ETH2_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+2) +#define BSP_MAIN_GPP7_0_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+24) +#define BSP_MAIN_GPP15_8_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+25) +#define BSP_MAIN_GPP23_16_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+26) +#define BSP_MAIN_GPP31_24_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+27) + + /* on the MVME5500, these are the GT64260B external GPP0 interrupt */ +#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET) +#define BSP_UART_COM2_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET) +#define BSP_UART_COM1_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET) +#define BSP_GPP8_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+8) +#define BSP_GPP_PMC1_INTA (BSP_GPP8_IRQ_OFFSET) +#define BSP_GPP16_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+16) +#define BSP_GPP24_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+24) +#define BSP_GPP_VME_VLINT0 (BSP_GPP_IRQ_LOWEST_OFFSET+12) +#define BSP_GPP_VME_VLINT1 (BSP_GPP_IRQ_LOWEST_OFFSET+13) +#define BSP_GPP_VME_VLINT2 (BSP_GPP_IRQ_LOWEST_OFFSET+14) +#define BSP_GPP_VME_VLINT3 (BSP_GPP_IRQ_LOWEST_OFFSET+15) +#define BSP_GPP_PMC2_INTA (BSP_GPP_IRQ_LOWEST_OFFSET+16) +#define BSP_GPP_82544_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+20) +#define BSP_GPP_WDT_NMI_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+24) +#define BSP_GPP_WDT_EXP_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+25) + + /* + * Some Processor execption handled as rtems IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) + +extern void BSP_rtems_irq_mng_init(unsigned cpuId); + +#include + +#endif +#endif diff --git a/bsps/powerpc/mvme5500/include/bsp/pcireg.h b/bsps/powerpc/mvme5500/include/bsp/pcireg.h new file mode 100644 index 0000000000..2b8b10d853 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/pcireg.h @@ -0,0 +1,386 @@ +/* $NetBSD: pcireg.h,v 1.44 2003/12/02 16:31:06 briggs Exp $ */ + +/* + * Copyright (c) 1995, 1996, 1999, 2000 + * Christopher G. Demetriou. All rights reserved. + * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. + * Copyright (C) 2007 Brookhaven National Laboratory, Shuchen Kate Feng + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Charles M. Hannum. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include + +/* + * PCI Class and Revision Register; defines type and revision of device. + */ +#define PCI_CLASS_REG 0x08 + +#define PCI_CLASS_SHIFT 24 +#define PCI_CLASS_MASK 0xff +#define PCI_CLASS(cr) \ + (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) + +#define PCI_SUBCLASS_SHIFT 16 +#define PCI_SUBCLASS_MASK 0xff +#define PCI_SUBCLASS(cr) \ + (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) + +#define PCI_INTERFACE_SHIFT 8 +#define PCI_INTERFACE_MASK 0xff +#define PCI_INTERFACE(cr) \ + (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) + +#define PCI_REVISION_SHIFT 0 +#define PCI_REVISION_MASK 0xff +#define PCI_REVISION(cr) \ + (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) + +#define PCI_CLASS_CODE(mainclass, subclass, interface) \ + ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ + (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ + (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) + +/* base classes */ +#define PCI_CLASS_PREHISTORIC 0x00 +#define PCI_CLASS_MASS_STORAGE 0x01 +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_DISPLAY 0x03 +#define PCI_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MEMORY 0x05 +#define PCI_CLASS_BRIDGE 0x06 +#define PCI_CLASS_COMMUNICATIONS 0x07 +#define PCI_CLASS_SYSTEM 0x08 +#define PCI_CLASS_INPUT 0x09 +#define PCI_CLASS_DOCK 0x0a +#define PCI_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_SERIALBUS 0x0c +#define PCI_CLASS_WIRELESS 0x0d +#define PCI_CLASS_I2O 0x0e +#define PCI_CLASS_SATCOM 0x0f +#define PCI_CLASS_CRYPTO 0x10 +#define PCI_CLASS_DASP 0x11 +#define PCI_CLASS_UNDEFINED 0xff + +/* 0x00 prehistoric subclasses */ +#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 +#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 + +/* 0x01 mass storage subclasses */ +#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 +#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 +#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 +#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 +#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 +#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 +#define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 +#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 + +/* 0x02 network subclasses */ +#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 +#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 +#define PCI_SUBCLASS_NETWORK_FDDI 0x02 +#define PCI_SUBCLASS_NETWORK_ATM 0x03 +#define PCI_SUBCLASS_NETWORK_ISDN 0x04 +#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 +#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 +#define PCI_SUBCLASS_NETWORK_MISC 0x80 + +/* 0x03 display subclasses */ +#define PCI_SUBCLASS_DISPLAY_VGA 0x00 +#define PCI_SUBCLASS_DISPLAY_XGA 0x01 +#define PCI_SUBCLASS_DISPLAY_3D 0x02 +#define PCI_SUBCLASS_DISPLAY_MISC 0x80 + +/* 0x04 multimedia subclasses */ +#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 +#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 +#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 +#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 + +/* 0x05 memory subclasses */ +#define PCI_SUBCLASS_MEMORY_RAM 0x00 +#define PCI_SUBCLASS_MEMORY_FLASH 0x01 +#define PCI_SUBCLASS_MEMORY_MISC 0x80 + +/* 0x06 bridge subclasses */ +#define PCI_SUBCLASS_BRIDGE_HOST 0x00 +#define PCI_SUBCLASS_BRIDGE_ISA 0x01 +#define PCI_SUBCLASS_BRIDGE_EISA 0x02 +#define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */ +#define PCI_SUBCLASS_BRIDGE_PCI 0x04 +#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 +#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 +#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 +#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 +#define PCI_SUBCLASS_BRIDGE_STPCI 0x09 +#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a +#define PCI_SUBCLASS_BRIDGE_MISC 0x80 + +/* 0x07 communications subclasses */ +#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 +#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 +#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 +#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 +#define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 +#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 +#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 + +/* 0x08 system subclasses */ +#define PCI_SUBCLASS_SYSTEM_PIC 0x00 +#define PCI_SUBCLASS_SYSTEM_DMA 0x01 +#define PCI_SUBCLASS_SYSTEM_TIMER 0x02 +#define PCI_SUBCLASS_SYSTEM_RTC 0x03 +#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 +#define PCI_SUBCLASS_SYSTEM_MISC 0x80 + +/* 0x09 input subclasses */ +#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 +#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 +#define PCI_SUBCLASS_INPUT_MOUSE 0x02 +#define PCI_SUBCLASS_INPUT_SCANNER 0x03 +#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 +#define PCI_SUBCLASS_INPUT_MISC 0x80 + +/* 0x0a dock subclasses */ +#define PCI_SUBCLASS_DOCK_GENERIC 0x00 +#define PCI_SUBCLASS_DOCK_MISC 0x80 + +/* 0x0b processor subclasses */ +#define PCI_SUBCLASS_PROCESSOR_386 0x00 +#define PCI_SUBCLASS_PROCESSOR_486 0x01 +#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 +#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 +#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 +#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 +#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 + +/* 0x0c serial bus subclasses */ +#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 +#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 +#define PCI_SUBCLASS_SERIALBUS_SSA 0x02 +#define PCI_SUBCLASS_SERIALBUS_USB 0x03 +#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ +#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 +#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 +#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 +#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 +#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 + +/* 0x0d wireless subclasses */ +#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 +#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 +#define PCI_SUBCLASS_WIRELESS_RF 0x10 +#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 +#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 +#define PCI_SUBCLASS_WIRELESS_802_11A 0x20 +#define PCI_SUBCLASS_WIRELESS_802_11B 0x21 +#define PCI_SUBCLASS_WIRELESS_MISC 0x80 + +/* 0x0e I2O (Intelligent I/O) subclasses */ +#define PCI_SUBCLASS_I2O_STANDARD 0x00 + +/* 0x0f satellite communication subclasses */ +/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ +#define PCI_SUBCLASS_SATCOM_TV 0x01 +#define PCI_SUBCLASS_SATCOM_AUDIO 0x02 +#define PCI_SUBCLASS_SATCOM_VOICE 0x03 +#define PCI_SUBCLASS_SATCOM_DATA 0x04 + +/* 0x10 encryption/decryption subclasses */ +#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 +#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 +#define PCI_SUBCLASS_CRYPTO_MISC 0x80 + +/* 0x11 data acquisition and signal processing subclasses */ +#define PCI_SUBCLASS_DASP_DPIO 0x00 +#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 +#define PCI_SUBCLASS_DASP_SYNC 0x10 +#define PCI_SUBCLASS_DASP_MGMT 0x20 +#define PCI_SUBCLASS_DASP_MISC 0x80 + +/* + * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. + */ +#define PCI_BHLC_REG 0x0c + +#define PCI_BIST_SHIFT 24 +#define PCI_BIST_MASK 0xff +#define PCI_BIST(bhlcr) \ + (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) + +#define PCI_HDRTYPE_SHIFT 16 +#define PCI_HDRTYPE_MASK 0xff +#define PCI_HDRTYPE(bhlcr) \ + (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) + +#define PCI_HDRTYPE_TYPE(bhlcr) \ + (PCI_HDRTYPE(bhlcr) & 0x7f) +#define PCI_HDRTYPE_MULTIFN(bhlcr) \ + ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) + +#define PCI_LATTIMER_SHIFT 8 +#define PCI_LATTIMER_MASK 0xff +#define PCI_LATTIMER(bhlcr) \ + (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) + +#define PCI_CACHELINE_SHIFT 0 +#define PCI_CACHELINE_MASK 0xff +#define PCI_CACHELINE(bhlcr) \ + (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) + +#define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ + ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ + (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ + (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ + (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ + (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) + +/* + * PCI header type + */ +#define PCI_HDRTYPE_DEVICE 0 +#define PCI_HDRTYPE_PPB 1 +#define PCI_HDRTYPE_PCB 2 + +/* + * Mapping registers + */ +#define PCI_MAPREG_START 0x10 +#define PCI_MAPREG_END 0x28 +#define PCI_MAPREG_ROM 0x30 +#define PCI_MAPREG_PPB_END 0x18 +#define PCI_MAPREG_PCB_END 0x14 + +#define PCI_MAPREG_TYPE(mr) \ + ((mr) & PCI_MAPREG_TYPE_MASK) +#define PCI_MAPREG_TYPE_MASK 0x00000001 + +#define PCI_MAPREG_TYPE_MEM 0x00000000 +#define PCI_MAPREG_TYPE_IO 0x00000001 +#define PCI_MAPREG_ROM_ENABLE 0x00000001 + +#define PCI_MAPREG_MEM_TYPE(mr) \ + ((mr) & PCI_MAPREG_MEM_TYPE_MASK) +#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 + +#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 +#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 +#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 + +#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ + (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) +#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 + +#define PCI_MAPREG_MEM_ADDR(mr) \ + ((mr) & PCI_MAPREG_MEM_ADDR_MASK) +#define PCI_MAPREG_MEM_SIZE(mr) \ + (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) +#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 + +#define PCI_MAPREG_MEM64_ADDR(mr) \ + ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) +#define PCI_MAPREG_MEM64_SIZE(mr) \ + (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) +#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL + +#define PCI_MAPREG_IO_ADDR(mr) \ + ((mr+PCI0_IO_BASE) & PCI_MAPREG_IO_ADDR_MASK) +#define PCI_MAPREG_IO_SIZE(mr) \ + (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) +#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc + +#define PCI_MAPREG_SIZE_TO_MASK(size) \ + (-(size)) + +#define PCI_MAPREG_NUM(offset) \ + (((unsigned)(offset)-PCI_MAPREG_START)/4) + + +/* + * Cardbus CIS pointer (PCI rev. 2.1) + */ +#define PCI_CARDBUS_CIS_REG 0x28 + +/* + * Subsystem identification register; contains a vendor ID and a device ID. + * Types/macros for PCI_ID_REG apply. + * (PCI rev. 2.1) + */ +#define PCI_SUBSYS_ID_REG 0x2c + +/* + * capabilities link list (PCI rev. 2.2) + */ +#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ +#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ +#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) +#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) +#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) + +#define PCI_CAP_RESERVED0 0x00 +#define PCI_CAP_PWRMGMT 0x01 +#define PCI_CAP_AGP 0x02 +#define PCI_CAP_VPD 0x03 +#define PCI_CAP_SLOTID 0x04 +#define PCI_CAP_MSI 0x05 +#define PCI_CAP_CPCI_HOTSWAP 0x06 +#define PCI_CAP_PCIX 0x07 +#define PCI_CAP_LDT 0x08 +#define PCI_CAP_VENDSPEC 0x09 +#define PCI_CAP_DEBUGPORT 0x0a +#define PCI_CAP_CPCI_RSRCCTL 0x0b +#define PCI_CAP_HOTPLUG 0x0c +#define PCI_CAP_AGP8 0x0e +#define PCI_CAP_SECURE 0x0f +#define PCI_CAP_PCIEXPRESS 0x10 +#define PCI_CAP_MSIX 0x11 + +/* + * Vital Product Data; access via capability pointer (PCI rev 2.2). + */ +#define PCI_VPD_ADDRESS_MASK 0x7fff +#define PCI_VPD_ADDRESS_SHIFT 16 +#define PCI_VPD_ADDRESS(ofs) \ + (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) +#define PCI_VPD_DATAREG(ofs) ((ofs) + 4) +#define PCI_VPD_OPFLAG 0x80000000 + +/* + * Power Management Capability; access via capability pointer. + */ + +/* Power Management Capability Register */ +#define PCI_PMCR 0x02 +#define PCI_PMCR_D1SUPP 0x0200 +#define PCI_PMCR_D2SUPP 0x0400 +/* Power Management Control Status Register */ +#define PCI_PMCSR 0x04 +#define PCI_PMCSR_STATE_MASK 0x03 +#define PCI_PMCSR_STATE_D0 0x00 +#define PCI_PMCSR_STATE_D1 0x01 +#define PCI_PMCSR_STATE_D2 0x02 +#define PCI_PMCSR_STATE_D3 0x03 + diff --git a/bsps/powerpc/mvme5500/include/tm27.h b/bsps/powerpc/mvme5500/include/tm27.h new file mode 100644 index 0000000000..2a80618cfb --- /dev/null +++ b/bsps/powerpc/mvme5500/include/tm27.h @@ -0,0 +1,66 @@ +/* + * @file + * @ingroup powerpc_mvme5500 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 1 + +void nullFunc() {} +static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, + 0, + (rtems_irq_enable)nullFunc, + (rtems_irq_disable)nullFunc, + (rtems_irq_is_enabled) nullFunc}; + +void Install_tm27_vector(void (*_handler)()) +{ + clockIrqData.hdl = _handler; + if (!BSP_install_rtems_irq_handler (&clockIrqData)) { + printk("Error installing clock interrupt handler!\n"); + rtems_fatal_error_occurred(1); + } +} + +#define Cause_tm27_intr() \ + do { \ + uint32_t _clicks = 1; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + + +#define Clear_tm27_intr() \ + do { \ + uint32_t _clicks = 0xffffffff; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Lower_tm27_intr() \ + do { \ + uint32_t _msr = 0; \ + _ISR_Set_level( 0 ); \ + __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + _msr |= 0x8002; \ + __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + } while (0) + +#endif diff --git a/bsps/powerpc/psim/headers.am b/bsps/powerpc/psim/headers.am new file mode 100644 index 0000000000..a1f49d3727 --- /dev/null +++ b/bsps/powerpc/psim/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/psim/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/psim/include/psim.h +include_HEADERS += ../../../../../../bsps/powerpc/psim/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/psim/include/bsp/irq.h diff --git a/bsps/powerpc/psim/include/bsp.h b/bsps/powerpc/psim/include/bsp.h new file mode 100644 index 0000000000..cffc9632e7 --- /dev/null +++ b/bsps/powerpc/psim/include/bsp.h @@ -0,0 +1,90 @@ +/* bsp.h + * + * This include file contains all Papyrus board IO definitions. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_PSIM_BSP_H +#define LIBBSP_POWERPC_PSIM_BSP_H + +#include + +#ifdef ASM +/* Definition of where to store registers in alignment handler */ +#define ALIGN_REGS 0x0140 + +#else +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Constants */ + +/* + * Information placed in the linkcmds file. + */ + +extern int end; /* last address in the program */ +extern int RAM_END; + +extern uint32_t BSP_mem_size; + +#define BSP_Convert_decrementer( _value ) ( (unsigned long long) _value ) + +/* macros */ +#define Processor_Synchronize() \ + __asm__ (" eieio ") + +/* + * Network configuration + */ +struct rtems_bsdnet_ifconfig; + +int rtems_ifsim_attach(struct rtems_bsdnet_ifconfig *ifcfg, int attaching); + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "ifsim1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_ifsim_attach + +/* + * Interfaces to required Clock Driver support methods + */ +int BSP_disconnect_clock_handler(void); +int BSP_connect_clock_handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#define BSP_HAS_NO_VME + +#endif diff --git a/bsps/powerpc/psim/include/bsp/irq.h b/bsps/powerpc/psim/include/bsp/irq.h new file mode 100644 index 0000000000..376c95a627 --- /dev/null +++ b/bsps/powerpc/psim/include/bsp/irq.h @@ -0,0 +1,74 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_IRQ_H +#define LIBBSP_POWERPC_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 + +#ifndef ASM + +#include + + +/* + * Symblolic IRQ names and related definitions. + */ + +/* + * PCI IRQ handlers related definitions + * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE + */ +#define BSP_PCI_IRQ_NUMBER (16) +#define BSP_PCI_IRQ_LOWEST_OFFSET (0) +#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) + +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1) + + + /* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) + + /* + * Some Processor execption handled as rtems IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) + +#include + +#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET +#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET + +#ifdef __cplusplus +extern "C" { +#endif + +void BSP_rtems_irq_mng_init(unsigned cpuId); + +#ifdef __cplusplus +} +#endif + +#endif +#endif diff --git a/bsps/powerpc/psim/include/psim.h b/bsps/powerpc/psim/include/psim.h new file mode 100644 index 0000000000..e7b6fa7578 --- /dev/null +++ b/bsps/powerpc/psim/include/psim.h @@ -0,0 +1,90 @@ +/* + * PSIM addresses and constants based upon the configuration + * of devices used in the script provided by RTEMS. + */ + +#ifndef __PSIM_h +#define __PSIM_h + +/* + * RAM Information + */ + +extern char RamBase[]; +extern char RamSize[]; + +/* + * RamBase/RamSize is defined by the linker script; + * CPP symbols are AFAIK unused and deprecated. + */ +#define PSIM_RAM_SIZE ((unsigned long)RamSize) +#define PSIM_RAM_BASE ((void*)RamBase) + +/* + * NVRAM/RTC Structure and Information + */ + +#define PSIM_RTC_FREEZE 0xc0 +#define PSIM_RTC_UPDATE 0x00 + +typedef struct { + volatile uint8_t Control; /* 0x04 */ + volatile uint8_t Second; /* 0x05 */ + volatile uint8_t Minute; /* 0x06 */ + volatile uint8_t Hour; /* 0x07 */ + volatile uint8_t Day; /* 0x08 */ + volatile uint8_t Date; /* 0x09 */ + volatile uint8_t Month; /* 0x0a */ + volatile uint8_t Year; /* 0x0b */ +} psim_rtc_t; + +/* + * System V IPC Semaphore -- Read Only + */ + +typedef struct { + volatile uint32_t obtain_value; /* 0x00 */ + volatile uint32_t lock; /* 0x04 */ + volatile uint32_t unlock; /* 0x08 */ +} psim_sysv_sem_t; + +typedef struct { + /* 0x0c000000 - 0x0c007FFF - AMD 29F040 */ + volatile uint8_t Flash[ 512 * 1024 ]; + + /* 0x0c080000 - 0x0c0FFFFF - NVRAM/NVRAM */ + volatile uint8_t nvram[ 512 * 1024 ]; + + /* 0x0c100000 - 0x0c100007 - NVRAM/RTC */ + psim_rtc_t RTC; + + /* 0x0c100008 - 0x0c10000F - NVRAM/RTC */ + uint8_t gap1[8]; + + /* 0x0c100010 - 0x0c10001b - System V IPC Semaphore */ + psim_sysv_sem_t Semaphore; + + /* 0x0c10001c - 0x0c10001f - NVRAM/RTC */ + uint8_t gap2[4]; + + /* 0x0c100020 - 0x0c10005F - Ethernet */ + volatile uint8_t Ethtap[ 64 ]; + + /* 0x0c100060 - 0x0c10FFFF - NVRAM/RTC */ + uint8_t gap3[65440]; + + /* 0x0c110000 - 0x0c12FFFF - System V IPC Shared Memory */ + uint8_t SharedMemory[ 128 * 1024 ]; + + /* 0x0c130000 - 0x0c170000 - OpenPIC IRQ Controller */ + volatile uint8_t OpenPIC[ 256 * 1024 ]; + +} psim_registers_t; + +/* + * Data Structure Overlay for Registers. See linkcmds for placement. + */ +extern psim_registers_t PSIM; + +#endif +/* end of include file */ diff --git a/bsps/powerpc/psim/include/tm27.h b/bsps/powerpc/psim/include/tm27.h new file mode 100644 index 0000000000..3a41283a13 --- /dev/null +++ b/bsps/powerpc/psim/include/tm27.h @@ -0,0 +1,66 @@ +/* + * @file + * @ingroup powerpc_psim + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 1 + +void nullFunc() {} +static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, + 0, + (rtems_irq_enable)nullFunc, + (rtems_irq_disable)nullFunc, + (rtems_irq_is_enabled) nullFunc}; + +void Install_tm27_vector(void (*_handler)()) +{ + clockIrqData.hdl = _handler; + if (!BSP_install_rtems_irq_handler (&clockIrqData)) { + printk("Error installing clock interrupt handler!\n"); + rtems_fatal_error_occurred(1); + } +} + +#define Cause_tm27_intr() \ + do { \ + uint32_t _clicks = 1; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + + +#define Clear_tm27_intr() \ + do { \ + uint32_t _clicks = 0xffffffff; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Lower_tm27_intr() \ + do { \ + uint32_t _msr = 0; \ + _ISR_Set_level( 0 ); \ + __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + _msr |= 0x8002; \ + __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + } while (0) + +#endif diff --git a/bsps/powerpc/qemuppc/headers.am b/bsps/powerpc/qemuppc/headers.am new file mode 100644 index 0000000000..21ab8382a5 --- /dev/null +++ b/bsps/powerpc/qemuppc/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/qemuppc/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/qemuppc/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qemuppc/include/bsp/irq.h diff --git a/bsps/powerpc/qemuppc/include/bsp.h b/bsps/powerpc/qemuppc/include/bsp.h new file mode 100644 index 0000000000..240cfd3bea --- /dev/null +++ b/bsps/powerpc/qemuppc/include/bsp.h @@ -0,0 +1,47 @@ +/* + * This include file contains some definitions specific to the + * qemu powerpc Prep simulator + */ + +/* + * COPYRIGHT (c) 1989-2014. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QEMUPPC_BSP_H +#define LIBBSP_POWERPC_QEMUPPC_BSP_H + +#ifndef ASM + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Convert decrementer value to tenths of microseconds (used by shared timer + * driver). + */ +#define BSP_Convert_decrementer( _value ) \ + ((int) (((_value) * 10) / bsp_clicks_per_usec)) + +/* + * Prototypes for methods that are referenced from .S + */ +void cmain(void); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/powerpc/qemuppc/include/bsp/irq.h b/bsps/powerpc/qemuppc/include/bsp/irq.h new file mode 100644 index 0000000000..7124dbcaf8 --- /dev/null +++ b/bsps/powerpc/qemuppc/include/bsp/irq.h @@ -0,0 +1,76 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_IRQ_H +#define LIBBSP_POWERPC_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 + +#ifndef ASM + +#include + + +/* + * Symblolic IRQ names and related definitions. + */ + +/* + * PCI IRQ handlers related definitions + * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE + */ +/* FIXME: do we need PCI interrrupts here ? */ +#define BSP_PCI_IRQ_NUMBER (16) +#define BSP_PCI_IRQ_LOWEST_OFFSET (0) +#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) + +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1) + + + /* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) + + /* + * Some Processor execption handled as rtems IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) + +#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET + +#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET + +/* #include */ + +#ifdef __cplusplus +extern "C" { +#endif + +void BSP_rtems_irq_mng_init(unsigned cpuId); + +#ifdef __cplusplus +} +#endif + +#endif +#endif diff --git a/bsps/powerpc/qemuppc/include/tm27.h b/bsps/powerpc/qemuppc/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/qemuppc/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/powerpc/qoriq/headers.am b/bsps/powerpc/qoriq/headers.am new file mode 100644 index 0000000000..9d23263d43 --- /dev/null +++ b/bsps/powerpc/qoriq/headers.am @@ -0,0 +1,24 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/tm27.h + +include_asmdir = $(includedir)/asm +include_asm_HEADERS = +include_asm_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/asm/epapr_hcalls.h +include_asm_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/asm/fsl_hcalls.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp/intercom.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp/mmu.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp/qoriq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp/tsec-config.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp/uart-bridge.h + +include_uapi_asmdir = $(includedir)/uapi/asm +include_uapi_asm_HEADERS = +include_uapi_asm_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/uapi/asm/epapr_hcalls.h diff --git a/bsps/powerpc/qoriq/include/asm/epapr_hcalls.h b/bsps/powerpc/qoriq/include/asm/epapr_hcalls.h new file mode 100644 index 0000000000..3d87cca611 --- /dev/null +++ b/bsps/powerpc/qoriq/include/asm/epapr_hcalls.h @@ -0,0 +1,573 @@ +/* + * ePAPR hcall interface + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * Author: Timur Tabi + * + * This file is provided under a dual BSD/GPL license. When using or + * redistributing this file, you may do so under either license. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* A "hypercall" is an "sc 1" instruction. This header file file provides C + * wrapper functions for the ePAPR hypervisor interface. It is inteded + * for use by Linux device drivers and other operating systems. + * + * The hypercalls are implemented as inline assembly, rather than assembly + * language functions in a .S file, for optimization. It allows + * the caller to issue the hypercall instruction directly, improving both + * performance and memory footprint. + */ + +#ifndef _EPAPR_HCALLS_H +#define _EPAPR_HCALLS_H + +#include + +#ifndef __ASSEMBLY__ +#include + +/* + * Hypercall register clobber list + * + * These macros are used to define the list of clobbered registers during a + * hypercall. Technically, registers r0 and r3-r12 are always clobbered, + * but the gcc inline assembly syntax does not allow us to specify registers + * on the clobber list that are also on the input/output list. Therefore, + * the lists of clobbered registers depends on the number of register + * parmeters ("+r" and "=r") passed to the hypercall. + * + * Each assembly block should use one of the HCALL_CLOBBERSx macros. As a + * general rule, 'x' is the number of parameters passed to the assembly + * block *except* for r11. + * + * If you're not sure, just use the smallest value of 'x' that does not + * generate a compilation error. Because these are static inline functions, + * the compiler will only check the clobber list for a function if you + * compile code that calls that function. + * + * r3 and r11 are not included in any clobbers list because they are always + * listed as output registers. + * + * XER, CTR, and LR are currently listed as clobbers because it's uncertain + * whether they will be clobbered. + * + * Note that r11 can be used as an output parameter. + * + * The "memory" clobber is only necessary for hcalls where the Hypervisor + * will read or write guest memory. However, we add it to all hcalls because + * the impact is minimal, and we want to ensure that it's present for the + * hcalls that need it. +*/ + +/* List of common clobbered registers. Do not use this macro. */ +#define EV_HCALL_CLOBBERS "r0", "r12", "xer", "ctr", "lr", "cc", "memory" + +#define EV_HCALL_CLOBBERS8 EV_HCALL_CLOBBERS +#define EV_HCALL_CLOBBERS7 EV_HCALL_CLOBBERS8, "r10" +#define EV_HCALL_CLOBBERS6 EV_HCALL_CLOBBERS7, "r9" +#define EV_HCALL_CLOBBERS5 EV_HCALL_CLOBBERS6, "r8" +#define EV_HCALL_CLOBBERS4 EV_HCALL_CLOBBERS5, "r7" +#define EV_HCALL_CLOBBERS3 EV_HCALL_CLOBBERS4, "r6" +#define EV_HCALL_CLOBBERS2 EV_HCALL_CLOBBERS3, "r5" +#define EV_HCALL_CLOBBERS1 EV_HCALL_CLOBBERS2, "r4" + +extern bool epapr_paravirt_enabled; +extern uint32_t epapr_hypercall_start[]; + +#ifdef CONFIG_EPAPR_PARAVIRT +int __init epapr_paravirt_early_init(void); +#else +static inline int epapr_paravirt_early_init(void) { return 0; } +#endif + +/* + * We use "uintptr_t" to define a register because it's guaranteed to be a + * 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit + * platform. + * + * All registers are either input/output or output only. Registers that are + * initialized before making the hypercall are input/output. All + * input/output registers are represented with "+r". Output-only registers + * are represented with "=r". Do not specify any unused registers. The + * clobber list will tell the compiler that the hypercall modifies those + * registers, which is good enough. + */ + +/** + * ev_int_set_config - configure the specified interrupt + * @interrupt: the interrupt number + * @config: configuration for this interrupt + * @priority: interrupt priority + * @destination: destination CPU number + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_int_set_config(unsigned int interrupt, + uint32_t config, unsigned int priority, uint32_t destination) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + + r11 = EV_HCALL_TOKEN(EV_INT_SET_CONFIG); + r3 = interrupt; + r4 = config; + r5 = priority; + r6 = destination; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6) + : : EV_HCALL_CLOBBERS4 + ); + + return r3; +} + +/** + * ev_int_get_config - return the config of the specified interrupt + * @interrupt: the interrupt number + * @config: returned configuration for this interrupt + * @priority: returned interrupt priority + * @destination: returned destination CPU number + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_int_get_config(unsigned int interrupt, + uint32_t *config, unsigned int *priority, uint32_t *destination) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + + r11 = EV_HCALL_TOKEN(EV_INT_GET_CONFIG); + r3 = interrupt; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5), "=r" (r6) + : : EV_HCALL_CLOBBERS4 + ); + + *config = r4; + *priority = r5; + *destination = r6; + + return r3; +} + +/** + * ev_int_set_mask - sets the mask for the specified interrupt source + * @interrupt: the interrupt number + * @mask: 0=enable interrupts, 1=disable interrupts + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_int_set_mask(unsigned int interrupt, + unsigned int mask) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = EV_HCALL_TOKEN(EV_INT_SET_MASK); + r3 = interrupt; + r4 = mask; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + return r3; +} + +/** + * ev_int_get_mask - returns the mask for the specified interrupt source + * @interrupt: the interrupt number + * @mask: returned mask for this interrupt (0=enabled, 1=disabled) + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_int_get_mask(unsigned int interrupt, + unsigned int *mask) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = EV_HCALL_TOKEN(EV_INT_GET_MASK); + r3 = interrupt; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "=r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + *mask = r4; + + return r3; +} + +/** + * ev_int_eoi - signal the end of interrupt processing + * @interrupt: the interrupt number + * + * This function signals the end of processing for the the specified + * interrupt, which must be the interrupt currently in service. By + * definition, this is also the highest-priority interrupt. + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_int_eoi(unsigned int interrupt) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = EV_HCALL_TOKEN(EV_INT_EOI); + r3 = interrupt; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +/** + * ev_byte_channel_send - send characters to a byte stream + * @handle: byte stream handle + * @count: (input) num of chars to send, (output) num chars sent + * @buffer: pointer to a 16-byte buffer + * + * @buffer must be at least 16 bytes long, because all 16 bytes will be + * read from memory into registers, even if count < 16. + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_byte_channel_send(unsigned int handle, + unsigned int *count, const char buffer[EV_BYTE_CHANNEL_MAX_BYTES]) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + register uintptr_t r7 __asm__("r7"); + register uintptr_t r8 __asm__("r8"); + const uint32_t *p = (const uint32_t *) buffer; + + r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_SEND); + r3 = handle; + r4 = *count; + r5 = be32toh(p[0]); + r6 = be32toh(p[1]); + r7 = be32toh(p[2]); + r8 = be32toh(p[3]); + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), + "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), "+r" (r8) + : : EV_HCALL_CLOBBERS6 + ); + + *count = r4; + + return r3; +} + +/** + * ev_byte_channel_receive - fetch characters from a byte channel + * @handle: byte channel handle + * @count: (input) max num of chars to receive, (output) num chars received + * @buffer: pointer to a 16-byte buffer + * + * The size of @buffer must be at least 16 bytes, even if you request fewer + * than 16 characters, because we always write 16 bytes to @buffer. This is + * for performance reasons. + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_byte_channel_receive(unsigned int handle, + unsigned int *count, char buffer[EV_BYTE_CHANNEL_MAX_BYTES]) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + register uintptr_t r7 __asm__("r7"); + register uintptr_t r8 __asm__("r8"); + uint32_t *p = (uint32_t *) buffer; + + r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_RECEIVE); + r3 = handle; + r4 = *count; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4), + "=r" (r5), "=r" (r6), "=r" (r7), "=r" (r8) + : : EV_HCALL_CLOBBERS6 + ); + + *count = r4; + p[0] = htobe32(r5); + p[1] = htobe32(r6); + p[2] = htobe32(r7); + p[3] = htobe32(r8); + + return r3; +} + +/** + * ev_byte_channel_poll - returns the status of the byte channel buffers + * @handle: byte channel handle + * @rx_count: returned count of bytes in receive queue + * @tx_count: returned count of free space in transmit queue + * + * This function reports the amount of data in the receive queue (i.e. the + * number of bytes you can read), and the amount of free space in the transmit + * queue (i.e. the number of bytes you can write). + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_byte_channel_poll(unsigned int handle, + unsigned int *rx_count, unsigned int *tx_count) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + + r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_POLL); + r3 = handle; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5) + : : EV_HCALL_CLOBBERS3 + ); + + *rx_count = r4; + *tx_count = r5; + + return r3; +} + +/** + * ev_int_iack - acknowledge an interrupt + * @handle: handle to the target interrupt controller + * @vector: returned interrupt vector + * + * If handle is zero, the function returns the next interrupt source + * number to be handled irrespective of the hierarchy or cascading + * of interrupt controllers. If non-zero, specifies a handle to the + * interrupt controller that is the target of the acknowledge. + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_int_iack(unsigned int handle, + unsigned int *vector) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = EV_HCALL_TOKEN(EV_INT_IACK); + r3 = handle; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "=r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + *vector = r4; + + return r3; +} + +/** + * ev_doorbell_send - send a doorbell to another partition + * @handle: doorbell send handle + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_doorbell_send(unsigned int handle) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = EV_HCALL_TOKEN(EV_DOORBELL_SEND); + r3 = handle; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +/** + * ev_idle -- wait for next interrupt on this core + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_idle(void) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = EV_HCALL_TOKEN(EV_IDLE); + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "=r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +#ifdef CONFIG_EPAPR_PARAVIRT +static inline unsigned long epapr_hypercall(unsigned long *in, + unsigned long *out, + unsigned long nr) +{ + unsigned long register r0 asm("r0"); + unsigned long register r3 asm("r3") = in[0]; + unsigned long register r4 asm("r4") = in[1]; + unsigned long register r5 asm("r5") = in[2]; + unsigned long register r6 asm("r6") = in[3]; + unsigned long register r7 asm("r7") = in[4]; + unsigned long register r8 asm("r8") = in[5]; + unsigned long register r9 asm("r9") = in[6]; + unsigned long register r10 asm("r10") = in[7]; + unsigned long register r11 asm("r11") = nr; + unsigned long register r12 asm("r12"); + + asm volatile("bl epapr_hypercall_start" + : "=r"(r0), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6), + "=r"(r7), "=r"(r8), "=r"(r9), "=r"(r10), "=r"(r11), + "=r"(r12) + : "r"(r3), "r"(r4), "r"(r5), "r"(r6), "r"(r7), "r"(r8), + "r"(r9), "r"(r10), "r"(r11) + : "memory", "cc", "xer", "ctr", "lr"); + + out[0] = r4; + out[1] = r5; + out[2] = r6; + out[3] = r7; + out[4] = r8; + out[5] = r9; + out[6] = r10; + out[7] = r11; + + return r3; +} +#else +static unsigned long epapr_hypercall(unsigned long *in, + unsigned long *out, + unsigned long nr) +{ + return EV_UNIMPLEMENTED; +} +#endif + +static inline long epapr_hypercall0_1(unsigned int nr, unsigned long *r2) +{ + unsigned long in[8]; + unsigned long out[8]; + unsigned long r; + + r = epapr_hypercall(in, out, nr); + *r2 = out[0]; + + return r; +} + +static inline long epapr_hypercall0(unsigned int nr) +{ + unsigned long in[8]; + unsigned long out[8]; + + return epapr_hypercall(in, out, nr); +} + +static inline long epapr_hypercall1(unsigned int nr, unsigned long p1) +{ + unsigned long in[8]; + unsigned long out[8]; + + in[0] = p1; + return epapr_hypercall(in, out, nr); +} + +static inline long epapr_hypercall2(unsigned int nr, unsigned long p1, + unsigned long p2) +{ + unsigned long in[8]; + unsigned long out[8]; + + in[0] = p1; + in[1] = p2; + return epapr_hypercall(in, out, nr); +} + +static inline long epapr_hypercall3(unsigned int nr, unsigned long p1, + unsigned long p2, unsigned long p3) +{ + unsigned long in[8]; + unsigned long out[8]; + + in[0] = p1; + in[1] = p2; + in[2] = p3; + return epapr_hypercall(in, out, nr); +} + +static inline long epapr_hypercall4(unsigned int nr, unsigned long p1, + unsigned long p2, unsigned long p3, + unsigned long p4) +{ + unsigned long in[8]; + unsigned long out[8]; + + in[0] = p1; + in[1] = p2; + in[2] = p3; + in[3] = p4; + return epapr_hypercall(in, out, nr); +} +#endif /* !__ASSEMBLY__ */ +#endif /* _EPAPR_HCALLS_H */ diff --git a/bsps/powerpc/qoriq/include/asm/fsl_hcalls.h b/bsps/powerpc/qoriq/include/asm/fsl_hcalls.h new file mode 100644 index 0000000000..ba76c132aa --- /dev/null +++ b/bsps/powerpc/qoriq/include/asm/fsl_hcalls.h @@ -0,0 +1,653 @@ +/* + * Freescale hypervisor call interface + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Author: Timur Tabi + * + * This file is provided under a dual BSD/GPL license. When using or + * redistributing this file, you may do so under either license. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_HCALLS_H +#define _FSL_HCALLS_H + +#include +#include + +#define FH_API_VERSION 1 + +#define FH_ERR_GET_INFO 1 +#define FH_PARTITION_GET_DTPROP 2 +#define FH_PARTITION_SET_DTPROP 3 +#define FH_PARTITION_RESTART 4 +#define FH_PARTITION_GET_STATUS 5 +#define FH_PARTITION_START 6 +#define FH_PARTITION_STOP 7 +#define FH_PARTITION_MEMCPY 8 +#define FH_DMA_ENABLE 9 +#define FH_DMA_DISABLE 10 +#define FH_SEND_NMI 11 +#define FH_VMPIC_GET_MSIR 12 +#define FH_SYSTEM_RESET 13 +#define FH_GET_CORE_STATE 14 +#define FH_ENTER_NAP 15 +#define FH_EXIT_NAP 16 +#define FH_CLAIM_DEVICE 17 +#define FH_PARTITION_STOP_DMA 18 + +/* vendor ID: Freescale Semiconductor */ +#define FH_HCALL_TOKEN(num) _EV_HCALL_TOKEN(EV_FSL_VENDOR_ID, num) + +/* + * We use "uintptr_t" to define a register because it's guaranteed to be a + * 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit + * platform. + * + * All registers are either input/output or output only. Registers that are + * initialized before making the hypercall are input/output. All + * input/output registers are represented with "+r". Output-only registers + * are represented with "=r". Do not specify any unused registers. The + * clobber list will tell the compiler that the hypercall modifies those + * registers, which is good enough. + */ + +/** + * fh_send_nmi - send NMI to virtual cpu(s). + * @vcpu_mask: send NMI to virtual cpu(s) specified by this mask. + * + * Returns 0 for success, or EINVAL for invalid vcpu_mask. + */ +static inline unsigned int fh_send_nmi(unsigned int vcpu_mask) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_SEND_NMI); + r3 = vcpu_mask; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +/* Arbitrary limits to avoid excessive memory allocation in hypervisor */ +#define FH_DTPROP_MAX_PATHLEN 4096 +#define FH_DTPROP_MAX_PROPLEN 32768 + +/** + * fh_partition_get_dtprop - get a property from a guest device tree. + * @handle: handle of partition whose device tree is to be accessed + * @dtpath_addr: physical address of device tree path to access + * @propname_addr: physical address of name of property + * @propvalue_addr: physical address of property value buffer + * @propvalue_len: length of buffer on entry, length of property on return + * + * Returns zero on success, non-zero on error. + */ +static inline unsigned int fh_partition_get_dtprop(int handle, + uint64_t dtpath_addr, + uint64_t propname_addr, + uint64_t propvalue_addr, + uint32_t *propvalue_len) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + register uintptr_t r7 __asm__("r7"); + register uintptr_t r8 __asm__("r8"); + register uintptr_t r9 __asm__("r9"); + register uintptr_t r10 __asm__("r10"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_GET_DTPROP); + r3 = handle; + +#ifdef CONFIG_PHYS_64BIT + r4 = dtpath_addr >> 32; + r6 = propname_addr >> 32; + r8 = propvalue_addr >> 32; +#else + r4 = 0; + r6 = 0; + r8 = 0; +#endif + r5 = (uint32_t)dtpath_addr; + r7 = (uint32_t)propname_addr; + r9 = (uint32_t)propvalue_addr; + r10 = *propvalue_len; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), + "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), + "+r" (r8), "+r" (r9), "+r" (r10) + : : EV_HCALL_CLOBBERS8 + ); + + *propvalue_len = r4; + return r3; +} + +/** + * Set a property in a guest device tree. + * @handle: handle of partition whose device tree is to be accessed + * @dtpath_addr: physical address of device tree path to access + * @propname_addr: physical address of name of property + * @propvalue_addr: physical address of property value + * @propvalue_len: length of property + * + * Returns zero on success, non-zero on error. + */ +static inline unsigned int fh_partition_set_dtprop(int handle, + uint64_t dtpath_addr, + uint64_t propname_addr, + uint64_t propvalue_addr, + uint32_t propvalue_len) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r6 __asm__("r6"); + register uintptr_t r8 __asm__("r8"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r7 __asm__("r7"); + register uintptr_t r9 __asm__("r9"); + register uintptr_t r10 __asm__("r10"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_SET_DTPROP); + r3 = handle; + +#ifdef CONFIG_PHYS_64BIT + r4 = dtpath_addr >> 32; + r6 = propname_addr >> 32; + r8 = propvalue_addr >> 32; +#else + r4 = 0; + r6 = 0; + r8 = 0; +#endif + r5 = (uint32_t)dtpath_addr; + r7 = (uint32_t)propname_addr; + r9 = (uint32_t)propvalue_addr; + r10 = propvalue_len; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), + "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), + "+r" (r8), "+r" (r9), "+r" (r10) + : : EV_HCALL_CLOBBERS8 + ); + + return r3; +} + +/** + * fh_partition_restart - reboot the current partition + * @partition: partition ID + * + * Returns an error code if reboot failed. Does not return if it succeeds. + */ +static inline unsigned int fh_partition_restart(unsigned int partition) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_RESTART); + r3 = partition; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +#define FH_PARTITION_STOPPED 0 +#define FH_PARTITION_RUNNING 1 +#define FH_PARTITION_STARTING 2 +#define FH_PARTITION_STOPPING 3 +#define FH_PARTITION_PAUSING 4 +#define FH_PARTITION_PAUSED 5 +#define FH_PARTITION_RESUMING 6 + +/** + * fh_partition_get_status - gets the status of a partition + * @partition: partition ID + * @status: returned status code + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_partition_get_status(unsigned int partition, + unsigned int *status) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_GET_STATUS); + r3 = partition; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "=r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + *status = r4; + + return r3; +} + +/** + * fh_partition_start - boots and starts execution of the specified partition + * @partition: partition ID + * @entry_point: guest physical address to start execution + * + * The hypervisor creates a 1-to-1 virtual/physical IMA mapping, so at boot + * time, guest physical address are the same as guest virtual addresses. + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_partition_start(unsigned int partition, + uint32_t entry_point, int load) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_START); + r3 = partition; + r4 = entry_point; + r5 = load; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5) + : : EV_HCALL_CLOBBERS3 + ); + + return r3; +} + +/** + * fh_partition_stop - stops another partition + * @partition: partition ID + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_partition_stop(unsigned int partition) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_STOP); + r3 = partition; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +/** + * struct fh_sg_list: definition of the fh_partition_memcpy S/G list + * @source: guest physical address to copy from + * @target: guest physical address to copy to + * @size: number of bytes to copy + * @reserved: reserved, must be zero + * + * The scatter/gather list for fh_partition_memcpy() is an array of these + * structures. The array must be guest physically contiguous. + * + * This structure must be aligned on 32-byte boundary, so that no single + * strucuture can span two pages. + */ +struct fh_sg_list { + uint64_t source; /**< guest physical address to copy from */ + uint64_t target; /**< guest physical address to copy to */ + uint64_t size; /**< number of bytes to copy */ + uint64_t reserved; /**< reserved, must be zero */ +} __attribute__ ((aligned(32))); + +/** + * fh_partition_memcpy - copies data from one guest to another + * @source: the ID of the partition to copy from + * @target: the ID of the partition to copy to + * @sg_list: guest physical address of an array of &fh_sg_list structures + * @count: the number of entries in @sg_list + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_partition_memcpy(unsigned int source, + unsigned int target, uint64_t sg_list, unsigned int count) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + register uintptr_t r7 __asm__("r7"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_MEMCPY); + r3 = source; + r4 = target; + r5 = (uint32_t) sg_list; + +#ifdef CONFIG_PHYS_64BIT + r6 = sg_list >> 32; +#else + r6 = 0; +#endif + r7 = count; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), + "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7) + : : EV_HCALL_CLOBBERS5 + ); + + return r3; +} + +/** + * fh_dma_enable - enable DMA for the specified device + * @liodn: the LIODN of the I/O device for which to enable DMA + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_dma_enable(unsigned int liodn) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_DMA_ENABLE); + r3 = liodn; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +/** + * fh_dma_disable - disable DMA for the specified device + * @liodn: the LIODN of the I/O device for which to disable DMA + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_dma_disable(unsigned int liodn) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_DMA_DISABLE); + r3 = liodn; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + + +/** + * fh_vmpic_get_msir - returns the MPIC-MSI register value + * @interrupt: the interrupt number + * @msir_val: returned MPIC-MSI register value + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_vmpic_get_msir(unsigned int interrupt, + unsigned int *msir_val) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = FH_HCALL_TOKEN(FH_VMPIC_GET_MSIR); + r3 = interrupt; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "=r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + *msir_val = r4; + + return r3; +} + +/** + * fh_system_reset - reset the system + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_system_reset(void) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_SYSTEM_RESET); + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "=r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + + +/** + * fh_err_get_info - get platform error information + * @queue id: + * 0 for guest error event queue + * 1 for global error event queue + * + * @pointer to store the platform error data: + * platform error data is returned in registers r4 - r11 + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_err_get_info(int queue, uint32_t *bufsize, + uint32_t addr_hi, uint32_t addr_lo, int peek) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + register uintptr_t r7 __asm__("r7"); + + r11 = FH_HCALL_TOKEN(FH_ERR_GET_INFO); + r3 = queue; + r4 = *bufsize; + r5 = addr_hi; + r6 = addr_lo; + r7 = peek; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), + "+r" (r7) + : : EV_HCALL_CLOBBERS5 + ); + + *bufsize = r4; + + return r3; +} + + +#define FH_VCPU_RUN 0 +#define FH_VCPU_IDLE 1 +#define FH_VCPU_NAP 2 + +/** + * fh_get_core_state - get the state of a vcpu + * + * @handle: handle of partition containing the vcpu + * @vcpu: vcpu number within the partition + * @state:the current state of the vcpu, see FH_VCPU_* + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_get_core_state(unsigned int handle, + unsigned int vcpu, unsigned int *state) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = FH_HCALL_TOKEN(FH_GET_CORE_STATE); + r3 = handle; + r4 = vcpu; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + *state = r4; + return r3; +} + +/** + * fh_enter_nap - enter nap on a vcpu + * + * Note that though the API supports entering nap on a vcpu other + * than the caller, this may not be implmented and may return EINVAL. + * + * @handle: handle of partition containing the vcpu + * @vcpu: vcpu number within the partition + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_enter_nap(unsigned int handle, unsigned int vcpu) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = FH_HCALL_TOKEN(FH_ENTER_NAP); + r3 = handle; + r4 = vcpu; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + return r3; +} + +/** + * fh_exit_nap - exit nap on a vcpu + * @handle: handle of partition containing the vcpu + * @vcpu: vcpu number within the partition + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_exit_nap(unsigned int handle, unsigned int vcpu) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = FH_HCALL_TOKEN(FH_EXIT_NAP); + r3 = handle; + r4 = vcpu; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + return r3; +} +/** + * fh_claim_device - claim a "claimable" shared device + * @handle: fsl,hv-device-handle of node to claim + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_claim_device(unsigned int handle) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_CLAIM_DEVICE); + r3 = handle; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +/** + * Run deferred DMA disabling on a partition's private devices + * + * This applies to devices which a partition owns either privately, + * or which are claimable and still actively owned by that partition, + * and which do not have the no-dma-disable property. + * + * @handle: partition (must be stopped) whose DMA is to be disabled + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_partition_stop_dma(unsigned int handle) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_STOP_DMA); + r3 = handle; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} +#endif diff --git a/bsps/powerpc/qoriq/include/bsp.h b/bsps/powerpc/qoriq/include/bsp.h new file mode 100644 index 0000000000..d7e9e95b3f --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp.h @@ -0,0 +1,128 @@ +/** + * @file + * + * @ingroup QorIQ + * + * @brief BSP API. + */ + +/* + * Copyright (c) 2010, 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_BSP_H +#define LIBBSP_POWERPC_QORIQ_BSP_H + +#include + +#ifdef QORIQ_IS_HYPERVISOR_GUEST +#define QORIQ_THREAD_COUNT 1 +#else +#define QORIQ_THREAD_COUNT QORIQ_PHYSICAL_THREAD_COUNT +#endif + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_FDT_IS_SUPPORTED + +#define QORIQ_CHIP(alpha, num) ((alpha) * 10000 + (num)) + +#define QORIQ_CHIP_P1020 QORIQ_CHIP('P', 1020) + +#define QORIQ_CHIP_T2080 QORIQ_CHIP('T', 2080) + +#define QORIQ_CHIP_T4240 QORIQ_CHIP('T', 4240) + +#define QORIQ_CHIP_VARIANT QORIQ_CHIP(QORIQ_CHIP_SERIES, QORIQ_CHIP_NUMBER) + +#define QORIQ_CHIP_IS_T_VARIANT(variant) ((variant) / 10000 == 'T') + +extern unsigned BSP_bus_frequency; + +struct rtems_bsdnet_ifconfig; + +int BSP_tsec_attach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +int qoriq_if_intercom_attach_detach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +#if defined(HAS_UBOOT) + /* Routine to obtain U-Boot environment variables */ + const char *bsp_uboot_getenv( + const char *name + ); +#endif + +void bsp_restart(void *addr) RTEMS_NO_RETURN; + +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_tsec_attach +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH4 qoriq_if_intercom_attach_detach + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec1" +#define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2" +#define RTEMS_BSP_NETWORK_DRIVER_NAME3 "tsec3" +#define RTEMS_BSP_NETWORK_DRIVER_NAME4 "intercom1" + +/* Internal data and functions */ + +typedef struct { + uint64_t addr; + uint64_t r3; + uint32_t reserved_0; + uint32_t pir; + uint64_t r6; + uint32_t reserved_1[8]; +} qoriq_start_spin_table; + +extern qoriq_start_spin_table * +qoriq_start_spin_table_addr[QORIQ_CPU_COUNT / QORIQ_THREAD_COUNT]; + +void qoriq_start_thread(void); + +void qoriq_restart_secondary_processor( + const qoriq_start_spin_table *spin_table +) RTEMS_NO_RETURN; + +void qoriq_initialize_exceptions(void *interrupt_stack_begin); + +void qoriq_decrementer_dispatch(void); + +extern uint32_t bsp_time_base_frequency; + +extern uint32_t qoriq_clock_frequency; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_POWERPC_QORIQ_BSP_H */ diff --git a/bsps/powerpc/qoriq/include/bsp/intercom.h b/bsps/powerpc/qoriq/include/bsp/intercom.h new file mode 100644 index 0000000000..39b2ba938e --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp/intercom.h @@ -0,0 +1,125 @@ +/** + * @file + * + * @ingroup QorIQInterCom + * + * @brief Inter-Processor Communication API. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_INTERCOM_H +#define LIBBSP_POWERPC_QORIQ_INTERCOM_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup QorIQInterCom QorIQ - Inter-Processor Communication Support + * + * @ingroup QorIQ + * + * @brief Inter-processor communication support. + * + * @{ + */ + +uint32_t qoriq_spin_lock(uint32_t *lock); + +void qoriq_spin_unlock(uint32_t *lock, uint32_t msr); + +#define INTERCOM_CORE_COUNT 2 + +#define INTERCOM_SERVICE_COUNT 8 + +typedef enum { + INTERCOM_TYPE_MPCI, + INTERCOM_TYPE_UART_0, + INTERCOM_TYPE_UART_1, + INTERCOM_TYPE_NETWORK, + INTERCOM_TYPE_CUSTOM_0, + INTERCOM_TYPE_CUSTOM_1, + INTERCOM_TYPE_CUSTOM_2, + INTERCOM_TYPE_CUSTOM_3, + INTERCOM_TYPE_CUSTOM_4 +} intercom_type; + +typedef enum { + INTERCOM_SIZE_64 = 0, + INTERCOM_SIZE_512, + INTERCOM_SIZE_2K, + INTERCOM_SIZE_4K +} intercom_size; + +typedef struct intercom_packet { + union { + struct intercom_packet *next; + rtems_chain_node node; + } glue; + intercom_type type_index; + intercom_size size_index; + uint32_t flags; + size_t size; + uint32_t cache_line_alignment [2]; + char data []; +} intercom_packet; + +typedef void (*intercom_service)(intercom_packet *packet, void *arg); + +void qoriq_intercom_init(void); + +void qoriq_intercom_start(void); + +void qoriq_intercom_service_install(intercom_type type, intercom_service service, void *arg); + +void qoriq_intercom_service_remove(intercom_type type); + +intercom_packet *qoriq_intercom_allocate_packet(intercom_type type, intercom_size size); + +void qoriq_intercom_send_packets(int destination_core, intercom_packet *first, intercom_packet *last); + +static inline void qoriq_intercom_send_packet(int destination_core, intercom_packet *packet) +{ + qoriq_intercom_send_packets(destination_core, packet, packet); +} + +void qoriq_intercom_broadcast_packets(intercom_packet *first, intercom_packet *last); + +static inline void qoriq_intercom_broadcast_packet(intercom_packet *packet) +{ + qoriq_intercom_broadcast_packets(packet, packet); +} + +void qoriq_intercom_send(int destination_core, intercom_type type, intercom_size size, const void *buf, size_t n); + +void qoriq_intercom_free_packet(intercom_packet *packet); + +intercom_packet *qoriq_intercom_clone_packet(const intercom_packet *packet); + +#ifdef RTEMS_MULTIPROCESSING + extern rtems_mpci_table qoriq_intercom_mpci; +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_QORIQ_INTERCOM_H */ diff --git a/bsps/powerpc/qoriq/include/bsp/irq.h b/bsps/powerpc/qoriq/include/bsp/irq.h new file mode 100644 index 0000000000..e178057950 --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp/irq.h @@ -0,0 +1,401 @@ +/** + * @file + * + * @ingroup QorIQInterrupt + * + * @brief Interrupt API. + */ + +/* + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_IRQ_H +#define LIBBSP_POWERPC_QORIQ_IRQ_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef QORIQ_IS_HYPERVISOR_GUEST + +#define BSP_INTERRUPT_VECTOR_MAX 1023 + +#else /* !QORIQ_IS_HYPERVISOR_GUEST */ + +#define QORIQ_IRQ_ERROR 0 + +#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) + +#define QORIQ_IRQ_PCI_EXPRESS_1 4 +#define QORIQ_IRQ_PCI_EXPRESS_2 5 +#define QORIQ_IRQ_PCI_EXPRESS_3 6 +#define QORIQ_IRQ_PCI_EXPRESS_4 7 +#define QORIQ_IRQ_PAMU 8 +#define QORIQ_IRQ_IFC 9 +#define QORIQ_IRQ_DMA_CHANNEL_1_1 12 +#define QORIQ_IRQ_DMA_CHANNEL_1_2 13 +#define QORIQ_IRQ_DMA_CHANNEL_1_3 14 +#define QORIQ_IRQ_DMA_CHANNEL_1_4 15 +#define QORIQ_IRQ_DMA_CHANNEL_2_1 16 +#define QORIQ_IRQ_DMA_CHANNEL_2_2 17 +#define QORIQ_IRQ_DMA_CHANNEL_2_3 18 +#define QORIQ_IRQ_DMA_CHANNEL_2_4 19 +#define QORIQ_IRQ_DUART_1 20 +#define QORIQ_IRQ_DUART_2 21 +#define QORIQ_IRQ_DUARL_I2C_1 22 +#define QORIQ_IRQ_DUARL_I2C_2 23 +#define QORIQ_IRQ_PCI_EXPRESS_1_INTA 24 +#define QORIQ_IRQ_PCI_EXPRESS_2_INTA 25 +#define QORIQ_IRQ_PCI_EXPRESS_3_INTA 26 +#define QORIQ_IRQ_PCI_EXPRESS_4_INTA 27 +#define QORIQ_IRQ_USB_1 28 +#define QORIQ_IRQ_USB_2 29 +#define QORIQ_IRQ_ESDHC 32 +#define QORIQ_IRQ_PERF_MON 36 +#define QORIQ_IRQ_ESPI 37 +#define QORIQ_IRQ_GPIO_2 38 +#define QORIQ_IRQ_GPIO_1 39 +#define QORIQ_IRQ_SATA_1 52 +#define QORIQ_IRQ_SATA_2 53 +#define QORIQ_IRQ_DMA_CHANNEL_1_5 60 +#define QORIQ_IRQ_DMA_CHANNEL_1_6 61 +#define QORIQ_IRQ_DMA_CHANNEL_1_7 62 +#define QORIQ_IRQ_DMA_CHANNEL_1_8 63 +#define QORIQ_IRQ_DMA_CHANNEL_2_5 64 +#define QORIQ_IRQ_DMA_CHANNEL_2_6 65 +#define QORIQ_IRQ_DMA_CHANNEL_2_7 66 +#define QORIQ_IRQ_DMA_CHANNEL_2_8 67 +#define QORIQ_IRQ_EVENT_PROC_UNIT_1 68 +#define QORIQ_IRQ_EVENT_PROC_UNIT_2 69 +#define QORIQ_IRQ_GPIO_3 70 +#define QORIQ_IRQ_GPIO_4 71 +#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_1 72 +#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_2 73 +#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_3 74 +#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_4 75 +#define QORIQ_IRQ_SEC_5_2_GLOBAL_ERROR 76 +#define QORIQ_IRQ_SEC_MON 77 +#define QORIQ_IRQ_EVENT_PROC_UNIT_3 78 +#define QORIQ_IRQ_EVENT_PROC_UNIT_4 79 +#define QORIQ_IRQ_FRAME_MGR 80 +#define QORIQ_IRQ_MDIO_1 84 +#define QORIQ_IRQ_MDIO_2 85 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_0 88 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_0 89 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_1 90 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_1 91 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_2 92 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_2 93 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_3 94 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_3 95 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_4 96 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_4 97 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_5 98 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_5 99 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_6 100 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_6 101 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_7 102 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_7 103 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_8 104 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_8 105 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_9 106 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_9 107 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_10 109 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_10 109 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_11 110 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_11 111 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_12 112 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_12 113 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_13 114 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_13 115 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_14 116 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_14 117 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_15 118 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_15 119 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_16 120 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_16 121 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_17 122 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_17 123 +#define QORIQ_IRQ_DMA_CHANNEL_3_1 240 +#define QORIQ_IRQ_DMA_CHANNEL_3_2 241 +#define QORIQ_IRQ_DMA_CHANNEL_3_3 242 +#define QORIQ_IRQ_DMA_CHANNEL_3_4 243 +#define QORIQ_IRQ_DMA_CHANNEL_3_5 244 +#define QORIQ_IRQ_DMA_CHANNEL_3_6 245 +#define QORIQ_IRQ_DMA_CHANNEL_3_7 246 +#define QORIQ_IRQ_DMA_CHANNEL_3_8 247 + +#define QORIQ_IRQ_EXT_BASE 256 + +#else /* QORIQ_CHIP_VARIANT */ + +/** + * @defgroup QoriqInterruptP1020 QorIQ - P1020 Internal Interrupt Sources + * + * @ingroup QorIQInterrupt + * + * @brief P1020 internal interrupt sources. + * + * @{ + */ + +#define QORIQ_IRQ_ETSEC_TX_1_GROUP_1 1 +#define QORIQ_IRQ_ETSEC_RX_1_GROUP_1 2 +#define QORIQ_IRQ_ETSEC_ER_1_GROUP_1 8 +#define QORIQ_IRQ_ETSEC_TX_3_GROUP_1 9 +#define QORIQ_IRQ_ETSEC_RX_3_GROUP_1 10 +#define QORIQ_IRQ_ETSEC_ER_3_GROUP_1 11 +#define QORIQ_IRQ_ETSEC_TX_2_GROUP_1 35 +#define QORIQ_IRQ_ETSEC_RX_2_GROUP_1 36 +#define QORIQ_IRQ_TDM 46 +#define QORIQ_IRQ_TDM_ERROR 47 +#define QORIQ_IRQ_ETSEC_ER_2_GROUP_1 51 + +/** @} */ + +/** + * @defgroup QoriqInterruptP2020 QorIQ - P2020 Internal Interrupt Sources + * + * @ingroup QorIQInterrupt + * + * @brief P2020 internal interrupt sources. + * + * @{ + */ + +#define QORIQ_IRQ_L2_CACHE 0 +#define QORIQ_IRQ_ECM 1 +#define QORIQ_IRQ_DDR_CONTROLLER 2 +#define QORIQ_IRQ_PCI_EXPRESS_3 8 +#define QORIQ_IRQ_PCI_EXPRESS_2 9 +#define QORIQ_IRQ_PCI_EXPRESS_1 10 +#define QORIQ_IRQ_SRIO_ERR_WRT_1_2 32 +#define QORIQ_IRQ_SRIO_OUT_DOORBELL_1 33 +#define QORIQ_IRQ_SRIO_IN_DOORBELL_1 34 +#define QORIQ_IRQ_SRIO_OUT_MSG_1 37 +#define QORIQ_IRQ_SRIO_IN_MSG_1 38 +#define QORIQ_IRQ_SRIO_OUT_MSG_2 39 +#define QORIQ_IRQ_SRIO_IN_MSG_2 40 + +/** @} */ + +/** + * @defgroup QoriqInterruptAll QorIQ - Internal Interrupt Sources + * + * @ingroup QorIQInterrupt + * + * @brief Internal interrupt sources. + * + * @{ + */ + +#define QORIQ_IRQ_ELBC 3 +#define QORIQ_IRQ_DMA_CHANNEL_1_1 4 +#define QORIQ_IRQ_DMA_CHANNEL_2_1 5 +#define QORIQ_IRQ_DMA_CHANNEL_3_1 6 +#define QORIQ_IRQ_DMA_CHANNEL_4_1 7 +#define QORIQ_IRQ_USB_1 12 +#define QORIQ_IRQ_ETSEC_TX_1 13 +#define QORIQ_IRQ_ETSEC_RX_1 14 +#define QORIQ_IRQ_ETSEC_TX_3 15 +#define QORIQ_IRQ_ETSEC_RX_3 16 +#define QORIQ_IRQ_ETSEC_ER_3 17 +#define QORIQ_IRQ_ETSEC_ER_1 18 +#define QORIQ_IRQ_ETSEC_TX_2 19 +#define QORIQ_IRQ_ETSEC_RX_2 20 +#define QORIQ_IRQ_ETSEC_ER_2 24 +#define QORIQ_IRQ_DUART_1 26 +#define QORIQ_IRQ_I2C 27 +#define QORIQ_IRQ_PERFORMANCE_MONITOR 28 +#define QORIQ_IRQ_SECURITY_1 29 +#define QORIQ_IRQ_USB_2 30 +#define QORIQ_IRQ_GPIO 31 +#define QORIQ_IRQ_SECURITY_2 42 +#define QORIQ_IRQ_ESPI 43 +#define QORIQ_IRQ_ETSEC_IEEE_1588_1 52 +#define QORIQ_IRQ_ETSEC_IEEE_1588_2 53 +#define QORIQ_IRQ_ETSEC_IEEE_1588_3 54 +#define QORIQ_IRQ_ESDHC 56 +#define QORIQ_IRQ_DMA_CHANNEL_1_2 60 +#define QORIQ_IRQ_DMA_CHANNEL_2_2 61 +#define QORIQ_IRQ_DMA_CHANNEL_3_2 62 +#define QORIQ_IRQ_DMA_CHANNEL_4_2 63 + +/** @} */ + +#define QORIQ_IRQ_EXT_BASE 64 + +#endif /* QORIQ_CHIP_VARIANT */ + +/** + * @defgroup QoriqInterruptExternal QorIQ - External Interrupt Sources + * + * @ingroup QorIQInterrupt + * + * @brief External interrupt sources. + * + * @{ + */ + +#define QORIQ_IRQ_EXT_0 (QORIQ_IRQ_EXT_BASE + 0) +#define QORIQ_IRQ_EXT_1 (QORIQ_IRQ_EXT_BASE + 1) +#define QORIQ_IRQ_EXT_2 (QORIQ_IRQ_EXT_BASE + 2) +#define QORIQ_IRQ_EXT_3 (QORIQ_IRQ_EXT_BASE + 3) +#define QORIQ_IRQ_EXT_4 (QORIQ_IRQ_EXT_BASE + 4) +#define QORIQ_IRQ_EXT_5 (QORIQ_IRQ_EXT_BASE + 5) +#define QORIQ_IRQ_EXT_6 (QORIQ_IRQ_EXT_BASE + 6) +#define QORIQ_IRQ_EXT_7 (QORIQ_IRQ_EXT_BASE + 7) +#define QORIQ_IRQ_EXT_8 (QORIQ_IRQ_EXT_BASE + 8) +#define QORIQ_IRQ_EXT_9 (QORIQ_IRQ_EXT_BASE + 9) +#define QORIQ_IRQ_EXT_10 (QORIQ_IRQ_EXT_BASE + 10) +#define QORIQ_IRQ_EXT_11 (QORIQ_IRQ_EXT_BASE + 11) + +/** @} */ + +/** + * @defgroup QoriqInterruptIPI QorIQ - Interprocessor Interrupts + * + * @ingroup QorIQInterrupt + * + * @brief Interprocessor interrupts. + * + * @{ + */ + +#define QORIQ_IRQ_IPI_BASE (QORIQ_IRQ_EXT_11 + 1) +#define QORIQ_IRQ_IPI_0 (QORIQ_IRQ_IPI_BASE + 0) +#define QORIQ_IRQ_IPI_1 (QORIQ_IRQ_IPI_BASE + 1) +#define QORIQ_IRQ_IPI_2 (QORIQ_IRQ_IPI_BASE + 2) +#define QORIQ_IRQ_IPI_3 (QORIQ_IRQ_IPI_BASE + 3) + +/** @} */ + +/** + * @defgroup QoriqInterruptIPI QorIQ - Message Interrupts + * + * @ingroup QorIQInterrupt + * + * @brief Message interrupts. + * + * @{ + */ + +#define QORIQ_IRQ_MI_BASE (QORIQ_IRQ_IPI_3 + 1) +#define QORIQ_IRQ_MI_0 (QORIQ_IRQ_MI_BASE + 0) +#define QORIQ_IRQ_MI_1 (QORIQ_IRQ_MI_BASE + 1) +#define QORIQ_IRQ_MI_2 (QORIQ_IRQ_MI_BASE + 2) +#define QORIQ_IRQ_MI_3 (QORIQ_IRQ_MI_BASE + 3) +#define QORIQ_IRQ_MI_4 (QORIQ_IRQ_MI_BASE + 4) +#define QORIQ_IRQ_MI_5 (QORIQ_IRQ_MI_BASE + 5) +#define QORIQ_IRQ_MI_6 (QORIQ_IRQ_MI_BASE + 6) +#define QORIQ_IRQ_MI_7 (QORIQ_IRQ_MI_BASE + 7) + +/** @} */ + +/** + * @defgroup QoriqInterruptIPI QorIQ - Shared Message Signaled Interrupts + * + * @ingroup QorIQInterrupt + * + * @brief Shared message signaled interrupts. + * + * @{ + */ + +#define QORIQ_IRQ_MSI_BASE (QORIQ_IRQ_MI_7 + 1) +#define QORIQ_IRQ_MSI_0 (QORIQ_IRQ_MSI_BASE + 0) +#define QORIQ_IRQ_MSI_1 (QORIQ_IRQ_MSI_BASE + 1) +#define QORIQ_IRQ_MSI_2 (QORIQ_IRQ_MSI_BASE + 2) +#define QORIQ_IRQ_MSI_3 (QORIQ_IRQ_MSI_BASE + 3) +#define QORIQ_IRQ_MSI_4 (QORIQ_IRQ_MSI_BASE + 4) +#define QORIQ_IRQ_MSI_5 (QORIQ_IRQ_MSI_BASE + 5) +#define QORIQ_IRQ_MSI_6 (QORIQ_IRQ_MSI_BASE + 6) +#define QORIQ_IRQ_MSI_7 (QORIQ_IRQ_MSI_BASE + 7) + +/** @} */ + +/** + * @defgroup QoriqInterruptIPI QorIQ - Global Timer Interrupts + * + * @ingroup QorIQInterrupt + * + * @brief Global Timer interrupts. + * + * @{ + */ + +#define QORIQ_IRQ_GT_BASE (QORIQ_IRQ_MSI_7 + 1) +#define QORIQ_IRQ_GT_A_0 (QORIQ_IRQ_GT_BASE + 0) +#define QORIQ_IRQ_GT_A_1 (QORIQ_IRQ_GT_BASE + 1) +#define QORIQ_IRQ_GT_A_2 (QORIQ_IRQ_GT_BASE + 2) +#define QORIQ_IRQ_GT_A_3 (QORIQ_IRQ_GT_BASE + 3) +#define QORIQ_IRQ_GT_B_0 (QORIQ_IRQ_GT_BASE + 4) +#define QORIQ_IRQ_GT_B_1 (QORIQ_IRQ_GT_BASE + 5) +#define QORIQ_IRQ_GT_B_2 (QORIQ_IRQ_GT_BASE + 6) +#define QORIQ_IRQ_GT_B_3 (QORIQ_IRQ_GT_BASE + 7) + +#define BSP_INTERRUPT_VECTOR_MAX QORIQ_IRQ_GT_B_3 + +/** @} */ + +#endif /* QORIQ_IS_HYPERVISOR_GUEST */ + +/** + * @defgroup QorIQInterrupt QorIQ - Interrupt Support + * + * @ingroup QorIQ + * + * @brief Interrupt support. + * + * @{ + */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define QORIQ_PIC_PRIORITY_LOWEST 1 +#define QORIQ_PIC_PRIORITY_HIGHEST 15 +#define QORIQ_PIC_PRIORITY_DISABLED 0 +#define QORIQ_PIC_PRIORITY_INVALID (QORIQ_PIC_PRIORITY_HIGHEST + 1) +#define QORIQ_PIC_PRIORITY_DEFAULT (QORIQ_PIC_PRIORITY_LOWEST + 1) +#define QORIQ_PIC_PRIORITY_IS_VALID(p) \ + ((p) >= QORIQ_PIC_PRIORITY_DISABLED && (p) <= QORIQ_PIC_PRIORITY_HIGHEST) + +rtems_status_code qoriq_pic_set_priority( + rtems_vector_number vector, + int new_priority, + int *old_priority +); + +void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +); + +void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_QORIQ_IRQ_H */ diff --git a/bsps/powerpc/qoriq/include/bsp/mmu.h b/bsps/powerpc/qoriq/include/bsp/mmu.h new file mode 100644 index 0000000000..4cacb1b375 --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp/mmu.h @@ -0,0 +1,101 @@ +/** + * @file + * + * @ingroup QorIQMMU + * + * @brief MMU API. + */ + +/* + * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_MMU_H +#define LIBBSP_POWERPC_QORIQ_MMU_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup QorIQMMU QorIQ - MMU Support + * + * @ingroup QorIQ + * + * @brief MMU support. + * + * @{ + */ + +#define QORIQ_MMU_MIN_POWER 12 +#define QORIQ_MMU_MAX_POWER 30 +#define QORIQ_MMU_POWER_STEP 2 + +typedef struct { + uintptr_t begin; + uintptr_t last; + uint32_t mas1; + uint32_t mas2; + uint32_t mas3; + uint32_t mas7; +} qoriq_mmu_entry; + +typedef struct { + int count; + qoriq_mmu_entry entries [QORIQ_TLB1_ENTRY_COUNT]; +} qoriq_mmu_context; + +void qoriq_mmu_context_init(qoriq_mmu_context *self); + +bool qoriq_mmu_add( + qoriq_mmu_context *self, + uintptr_t begin, + uintptr_t last, + uint32_t mas1, + uint32_t mas2, + uint32_t mas3, + uint32_t mas7 +); + +void qoriq_mmu_partition(qoriq_mmu_context *self, int max_count); + +void qoriq_mmu_write_to_tlb1(qoriq_mmu_context *self, int first_tlb); + +void qoriq_mmu_change_perm(uint32_t test, uint32_t set, uint32_t clear); + +void qoriq_mmu_config(bool boot_processor, int first_tlb, int scratch_tlb); + +void qoriq_tlb1_write( + int esel, + uint32_t mas1, + uint32_t mas2, + uint32_t mas3, + uint32_t mas7, + uintptr_t ea, + int tsize +); + +void qoriq_tlb1_invalidate(int esel); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_QORIQ_MMU_H */ diff --git a/bsps/powerpc/qoriq/include/bsp/qoriq.h b/bsps/powerpc/qoriq/include/bsp/qoriq.h new file mode 100644 index 0000000000..2d28d0aec7 --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp/qoriq.h @@ -0,0 +1,559 @@ +/** + * @file + * + * @ingroup QorIQ + * + * @brief QorIQ Configuration, Control and Status Registers. + */ + +/* + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_QORIQ_H +#define LIBBSP_POWERPC_QORIQ_QORIQ_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define QORIQ_FILL(a, b, s) uint8_t reserved_ ## b [b - a - sizeof(s)] +#define QORIQ_RESERVE(a, b) uint8_t reserved_ ## b [b - a] + +typedef struct { + uint32_t reg; + QORIQ_FILL(0x00000, 0x00010, uint32_t); +} qoriq_pic_reg; + +typedef struct { + uint32_t ccr; + QORIQ_FILL(0x00000, 0x00010, uint32_t); + uint32_t bcr; + QORIQ_FILL(0x00010, 0x00020, uint32_t); + uint32_t vpr; + QORIQ_FILL(0x00020, 0x00030, uint32_t); + uint32_t dr; + QORIQ_FILL(0x00030, 0x00040, uint32_t); +} qoriq_pic_global_timer; + +#define GTCCR_TOG BSP_BBIT32(0) +#define GTCCR_COUNT_GET(reg) BSP_BFLD32GET(reg, 1, 31) + +#define GTBCR_CI BSP_BBIT32(0) +#define GTBCR_COUNT(val) BSP_BFLD32(val, 1, 31) +#define GTBCR_COUNT_GET(reg) BSP_BFLD32GET(reg, 1, 31) +#define GTBCR_COUNT_SET(reg, val) BSP_BFLD32SET(reg, val, 1, 31) + +typedef struct { + uint32_t misc; + QORIQ_FILL(0x00000, 0x00010, uint32_t); + uint32_t internal [2]; + QORIQ_FILL(0x00010, 0x00020, uint32_t [2]); +} qoriq_pic_bit_field; + +typedef struct { + uint32_t vpr; + QORIQ_FILL(0x00000, 0x00010, uint32_t); + uint32_t dr; + QORIQ_FILL(0x00010, 0x00020, uint32_t); +} qoriq_pic_src_cfg; + +typedef struct { + QORIQ_RESERVE(0x00000, 0x00040); + qoriq_pic_reg ipidr [4]; + uint32_t ctpr; + QORIQ_FILL(0x00080, 0x00090, uint32_t); + uint32_t whoami; + QORIQ_FILL(0x00090, 0x000a0, uint32_t); + uint32_t iack; + QORIQ_FILL(0x000a0, 0x000b0, uint32_t); + uint32_t eoi; + QORIQ_FILL(0x000b0, 0x01000, uint32_t); +} qoriq_pic_per_cpu; + +typedef struct { + uint32_t brr1; + QORIQ_FILL(0x00000, 0x00010, uint32_t); + uint32_t brr2; + QORIQ_FILL(0x00010, 0x00040, uint32_t); + qoriq_pic_reg ipidr [4]; + uint32_t ctpr; + QORIQ_FILL(0x00080, 0x00090, uint32_t); + uint32_t whoami; + QORIQ_FILL(0x00090, 0x000a0, uint32_t); + uint32_t iack; + QORIQ_FILL(0x000a0, 0x000b0, uint32_t); + uint32_t eoi; + QORIQ_FILL(0x000b0, 0x01000, uint32_t); + uint32_t frr; + QORIQ_FILL(0x01000, 0x01020, uint32_t); + uint32_t gcr; + QORIQ_FILL(0x01020, 0x01080, uint32_t); + uint32_t vir; + QORIQ_FILL(0x01080, 0x01090, uint32_t); + uint32_t pir; + QORIQ_FILL(0x01090, 0x010a0, uint32_t); + qoriq_pic_reg ipivpr [4]; + uint32_t svr; + QORIQ_FILL(0x010e0, 0x010f0, uint32_t); + uint32_t tfrra; + QORIQ_FILL(0x010f0, 0x01100, uint32_t); + qoriq_pic_global_timer gta [4]; + QORIQ_RESERVE(0x01200, 0x01300); + uint32_t tcra; + QORIQ_FILL(0x01300, 0x01308, uint32_t); + uint32_t erqsr; + QORIQ_FILL(0x01308, 0x01310, uint32_t); + qoriq_pic_bit_field irqsr; + qoriq_pic_bit_field cisr; + qoriq_pic_bit_field pm [4]; + QORIQ_RESERVE(0x013d0, 0x01400); + qoriq_pic_reg msgr03 [4]; + QORIQ_RESERVE(0x01440, 0x01500); + uint32_t mer03; + QORIQ_FILL(0x01500, 0x01510, uint32_t); + uint32_t msr03; + QORIQ_FILL(0x01510, 0x01600, uint32_t); + qoriq_pic_reg msir [8]; + QORIQ_RESERVE(0x01680, 0x01720); + uint32_t msisr; + QORIQ_FILL(0x01720, 0x01740, uint32_t); + uint32_t msiir; + QORIQ_FILL(0x01740, 0x020f0, uint32_t); + uint32_t tfrrb; + QORIQ_FILL(0x020f0, 0x02100, uint32_t); + qoriq_pic_global_timer gtb [4]; + QORIQ_RESERVE(0x02200, 0x02300); + uint32_t tcrb; + QORIQ_FILL(0x02300, 0x02400, uint32_t); + qoriq_pic_reg msgr47 [4]; + QORIQ_RESERVE(0x02440, 0x02500); + uint32_t mer47; + QORIQ_FILL(0x02500, 0x02510, uint32_t); + uint32_t msr47; + QORIQ_FILL(0x02510, 0x10000, uint32_t); + qoriq_pic_src_cfg ei [12]; + QORIQ_RESERVE(0x10180, 0x10200); + qoriq_pic_src_cfg ii_0 [160]; + qoriq_pic_src_cfg mi [8]; + QORIQ_RESERVE(0x11700, 0x11c00); + qoriq_pic_src_cfg msi [8]; + QORIQ_RESERVE(0x11d00, 0x13000); + qoriq_pic_src_cfg ii_1 [96]; + QORIQ_RESERVE(0x13c00, 0x20000); + qoriq_pic_per_cpu per_cpu [2]; +} qoriq_pic; + +#define GTTCR_ROVR(val) BSP_BFLD32(val, 5, 7) +#define GTTCR_ROVR_GET(reg) BSP_BFLD32GET(reg, 5, 7) +#define GTTCR_ROVR_SET(reg, val) BSP_BFLD32SET(reg, val, 5, 7) +#define GTTCR_RTM BSP_BBIT32(15) +#define GTTCR_CLKR(val) BSP_BFLD32(val, 22, 23) +#define GTTCR_CLKR_GET(reg) BSP_BFLD32GET(reg, 22, 23) +#define GTTCR_CLKR_SET(reg, val) BSP_BFLD32SET(reg, val, 22, 23) +#define GTTCR_CASC(val) BSP_BFLD32(val, 29, 31) +#define GTTCR_CASC_GET(reg) BSP_BFLD32GET(reg, 29, 31) +#define GTTCR_CASC_SET(reg, val) BSP_BFLD32SET(reg, val, 29, 31) + +typedef struct { +} qoriq_uart; + +typedef struct { + uint32_t gpdir; + uint32_t gpodr; + uint32_t gpdat; + uint32_t gpier; + uint32_t gpimr; + uint32_t gpicr; + uint32_t gpibe; + QORIQ_RESERVE(0x001c, 0x1000); +} qoriq_gpio; + +typedef struct { + QORIQ_RESERVE(0x000, 0x100); + uint16_t caplength; + uint16_t hciversion; + uint32_t hcsparams; + uint32_t hccparams; + QORIQ_RESERVE(0x10c, 0x120); + uint32_t dciversion; + uint32_t dccparams; + QORIQ_RESERVE(0x128, 0x140); + uint32_t usbcmd; + uint32_t usbsts; + uint32_t usbintr; + uint32_t frindex; + QORIQ_RESERVE(0x150, 0x154); + union { + uint32_t periodiclistbase; + uint32_t deviceaddr; + } perbase_devaddr; + union { + uint32_t asynclistaddr; + uint32_t addr; + } async_addr; + QORIQ_RESERVE(0x15c, 0x160); + uint32_t burstsize; + uint32_t txfilltuning; + QORIQ_RESERVE(0x168, 0x170); + uint32_t viewport; + QORIQ_RESERVE(0x174, 0x180); + uint32_t configflag; + uint32_t portsc1; + QORIQ_RESERVE(0x188, 0x1a8); + uint32_t usbmode; + uint32_t endptsetupstat; + uint32_t endpointprime; + uint32_t endptflush; + uint32_t endptstatus; + uint32_t endptcomplete; + uint32_t endptctrl[6]; + QORIQ_RESERVE(0x1d8, 0x400); + uint32_t snoop1; + uint32_t snoop2; + uint32_t age_cnt_thresh; + uint32_t pri_ctrl; + uint32_t si_ctrl; + QORIQ_RESERVE(0x414, 0x500); + uint32_t control; +} qoriq_usb; + +typedef struct { + uint32_t dsaddr; + uint32_t blkattr; + uint32_t cmdarg; + uint32_t xfertyp; + uint32_t cmdrsp0; + uint32_t cmdrsp1; + uint32_t cmdrsp2; + uint32_t cmdrsp3; + uint32_t datport; + uint32_t prsstat; + uint32_t proctl; + uint32_t sysctl; + uint32_t irqstat; + uint32_t irqstaten; + uint32_t irqsigen; + uint32_t autoc12err; + uint32_t hostcapblt; + uint32_t wml; + QORIQ_FILL(0x00044, 0x00050, uint32_t); + uint32_t fevt; + QORIQ_FILL(0x00050, 0x000fc, uint32_t); + uint32_t hostver; + QORIQ_FILL(0x000fc, 0x0040c, uint32_t); + uint32_t dcr; +} qoriq_esdhc; + +#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) + +typedef struct { + uint32_t ccsrbarh; + uint32_t ccsrbarl; + uint32_t ccsrar; + uint32_t altcbarh; + uint32_t altcbarl; + uint32_t altcar; + uint32_t bstrh; + uint32_t bstrl; + uint32_t bstar; +} qoriq_lcc; + +#define LCC_BSTAR_EN BSP_BBIT32(0) + +typedef struct { + uint32_t lawbarh; + uint32_t lawbarl; + uint32_t lawar; + uint32_t reserved_0xc; +} qoriq_law; + +typedef struct { + uint32_t reserved_0x0[640]; + uint32_t qmbm_warmrst; +} qoriq_dcfg; + +typedef struct { + QORIQ_RESERVE(0x0000, 0x1000); +} qoriq_bman; + +typedef struct { + QORIQ_RESERVE(0x0000, 0x1000); +} qoriq_qman; + +typedef struct { + QORIQ_RESERVE(0x000000, 0x100000); +} qoriq_fman; + +typedef struct { + qoriq_lcc lcc; + QORIQ_FILL(0x000000, 0x000c00, qoriq_lcc); + qoriq_law law [32]; + QORIQ_FILL(0x000c00, 0x001000, qoriq_law [32]); + QORIQ_RESERVE(0x001000, 0x040000); + qoriq_pic pic; + QORIQ_FILL(0x040000, 0x070000, qoriq_pic); + QORIQ_RESERVE(0x070000, 0x0e0000); + qoriq_dcfg dcfg; + QORIQ_FILL(0x0e0000, 0x0e1000, qoriq_dcfg); + QORIQ_RESERVE(0x0e1000, 0x114000); + qoriq_esdhc esdhc; + QORIQ_FILL(0x114000, 0x115000, qoriq_esdhc); + QORIQ_RESERVE(0x115000, 0x11c500); + qoriq_uart uart_0; + QORIQ_FILL(0x11c500, 0x11c600, qoriq_uart); + qoriq_uart uart_1; + QORIQ_FILL(0x11c600, 0x11d500, qoriq_uart); + qoriq_uart uart_2; + QORIQ_FILL(0x11d500, 0x11d600, qoriq_uart); + qoriq_uart uart_3; + QORIQ_FILL(0x11d600, 0x11e000, qoriq_uart); + QORIQ_RESERVE(0x11e000, 0x130000); + qoriq_gpio gpio[4]; + QORIQ_RESERVE(0x134000, 0x210000); + qoriq_usb usb_1; + QORIQ_FILL(0x210000, 0x211000, qoriq_usb); + QORIQ_RESERVE(0x211000, 0x318000); + qoriq_qman qman; + QORIQ_RESERVE(0x319000, 0x31a000); + qoriq_bman bman; + QORIQ_RESERVE(0x31b000, 0x400000); + qoriq_fman fman[2]; + QORIQ_RESERVE(0x600000, 0x2000000); +} qoriq_ccsr; + +#else /* QORIQ_CHIP_VARIANT */ + +typedef struct { + uint32_t ccsrbar; + uint32_t reserved_0; + uint32_t altcbar; + uint32_t reserved_1; + uint32_t altcar; + uint32_t reserved_2 [3]; + uint32_t bptr; +} qoriq_lcc; + +#define CCSRBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 23) +#define CCSRBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 23) +#define CCSRBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 23) + +#define ALTCBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 23) +#define ALTCBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 23) +#define ALTCBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 23) + +#define ALTCAR_EN BSP_BBIT32(0) +#define ALTCAR_TRGT_ID(val) BSP_BFLD32(val, 8, 11) +#define ALTCAR_TRGT_ID_GET(reg) BSP_BFLD32GET(reg, 8, 11) +#define ALTCAR_TRGT_ID_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 11) + +#define BPTR_EN BSP_BBIT32(0) +#define BPTR_BOOT_PAGE(val) BSP_BFLD32(val, 8, 31) +#define BPTR_BOOT_PAGE_GET(reg) BSP_BFLD32GET(reg, 8, 31) +#define BPTR_BOOT_PAGE_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 31) + +typedef struct { + uint32_t bar; + uint32_t reserved_0; + uint32_t ar; + uint32_t reserved_1 [5]; +} qoriq_law; + +#define LAWBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 31) +#define LAWBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 31) +#define LAWBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 31) + +#define LAWAR_EN BSP_BBIT32(0) +#define LAWAR_TRGT(val) BSP_BFLD32(val, 8, 11) +#define LAWAR_TRGT_GET(reg) BSP_BFLD32GET(reg, 8, 11) +#define LAWAR_TRGT_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 11) +#define LAWAR_SIZE(val) BSP_BFLD32(val, 26, 31) +#define LAWAR_SIZE_GET(reg) BSP_BFLD32GET(reg, 26, 31) +#define LAWAR_SIZE_SET(reg, val) BSP_BFLD32SET(reg, val, 26, 31) + +typedef struct { +} qoriq_ecm; + +typedef struct { +} qoriq_ddr_controller; + +typedef struct { +} qoriq_i2c; + +typedef struct { +} qoriq_local_bus; + +typedef struct { +} qoriq_spi; + +typedef struct { +} qoriq_pci_express; + +typedef struct { +} qoriq_tdm; + +typedef struct { +} qoriq_l2_cache; + +typedef struct { +} qoriq_dma; + +typedef struct { +} qoriq_tdm_dma; + +typedef struct { +} qoriq_sec; + +typedef struct { +} qoriq_serial_rapid_io; + +typedef struct { +} qoriq_global_utilities; + +typedef struct { +} qoriq_performance_monitor; + +typedef struct { +} qoriq_debug_watchpoint; + +typedef struct { +} qoriq_serdes; + +typedef struct { +} qoriq_boot_rom; + +typedef struct { + qoriq_lcc lcc; + QORIQ_FILL(0x00000, 0x00c08, qoriq_lcc); + qoriq_law law [12]; + QORIQ_FILL(0x00c08, 0x01000, qoriq_law [12]); + qoriq_ecm ecm; + QORIQ_FILL(0x01000, 0x02000, qoriq_ecm); + qoriq_ddr_controller ddr_controller; + QORIQ_FILL(0x02000, 0x03000, qoriq_ddr_controller); + qoriq_i2c i2c; + QORIQ_FILL(0x03000, 0x04000, qoriq_i2c); + QORIQ_RESERVE(0x04000, 0x04500); + qoriq_uart uart_0; + QORIQ_FILL(0x04500, 0x04600, qoriq_uart); + qoriq_uart uart_1; + QORIQ_FILL(0x04600, 0x04700, qoriq_uart); + QORIQ_RESERVE(0x04700, 0x05000); + qoriq_local_bus local_bus; + QORIQ_FILL(0x05000, 0x06000, qoriq_local_bus); + qoriq_spi spi; + QORIQ_FILL(0x06000, 0x07000, qoriq_spi); + QORIQ_RESERVE(0x07000, 0x08000); + qoriq_pci_express pci_express_3; + QORIQ_FILL(0x08000, 0x09000, qoriq_pci_express); + qoriq_pci_express pci_express_2; + QORIQ_FILL(0x09000, 0x0a000, qoriq_pci_express); + qoriq_pci_express pci_express_1; + QORIQ_FILL(0x0a000, 0x0b000, qoriq_pci_express); + QORIQ_RESERVE(0x0b000, 0x0c000); + qoriq_dma dma_2; + QORIQ_FILL(0x0c000, 0x0d000, qoriq_dma); + QORIQ_RESERVE(0x0d000, 0x0f000); + qoriq_gpio gpio; + QORIQ_RESERVE(0x10000, 0x16000); + qoriq_tdm tdm; + QORIQ_FILL(0x16000, 0x17000, qoriq_tdm); + QORIQ_RESERVE(0x17000, 0x20000); + qoriq_l2_cache l2_cache; + QORIQ_FILL(0x20000, 0x21000, qoriq_l2_cache); + qoriq_dma dma_1; + QORIQ_FILL(0x21000, 0x22000, qoriq_dma); + qoriq_usb usb_1; + QORIQ_FILL(0x22000, 0x23000, qoriq_usb); + qoriq_usb usb_2; + QORIQ_FILL(0x23000, 0x24000, qoriq_usb); + tsec_registers tsec_1; + QORIQ_FILL(0x24000, 0x25000, tsec_registers); + tsec_registers tsec_2; + QORIQ_FILL(0x25000, 0x26000, tsec_registers); + tsec_registers tsec_3; + QORIQ_FILL(0x26000, 0x27000, tsec_registers); + QORIQ_RESERVE(0x27000, 0x2c000); + qoriq_tdm_dma tdm_dma; + QORIQ_FILL(0x2c000, 0x2d000, qoriq_tdm_dma); + QORIQ_RESERVE(0x2d000, 0x2e000); + qoriq_esdhc esdhc; + QORIQ_FILL(0x2e000, 0x2f000, qoriq_esdhc); + QORIQ_RESERVE(0x2f000, 0x30000); + qoriq_sec sec; + QORIQ_FILL(0x30000, 0x31000, qoriq_sec); + QORIQ_RESERVE(0x31000, 0x40000); + qoriq_pic pic; + QORIQ_FILL(0x40000, 0x80000, qoriq_pic); + QORIQ_RESERVE(0x80000, 0xb0000); + tsec_registers tsec_1_group_0; + QORIQ_FILL(0xb0000, 0xb1000, tsec_registers); + tsec_registers tsec_2_group_0; + QORIQ_FILL(0xb1000, 0xb2000, tsec_registers); + tsec_registers tsec_3_group_0; + QORIQ_FILL(0xb2000, 0xb3000, tsec_registers); + QORIQ_RESERVE(0xb3000, 0xb4000); + tsec_registers tsec_1_group_1; + QORIQ_FILL(0xb4000, 0xb5000, tsec_registers); + tsec_registers tsec_2_group_1; + QORIQ_FILL(0xb5000, 0xb6000, tsec_registers); + tsec_registers tsec_3_group_1; + QORIQ_FILL(0xb6000, 0xb7000, tsec_registers); + QORIQ_RESERVE(0xb7000, 0xc0000); + qoriq_serial_rapid_io serial_rapid_io; + QORIQ_FILL(0xc0000, 0xe0000, qoriq_serial_rapid_io); + qoriq_global_utilities global_utilities; + QORIQ_FILL(0xe0000, 0xe1000, qoriq_global_utilities); + qoriq_performance_monitor performance_monitor; + QORIQ_FILL(0xe1000, 0xe2000, qoriq_performance_monitor); + qoriq_debug_watchpoint debug_watchpoint; + QORIQ_FILL(0xe2000, 0xe3000, qoriq_debug_watchpoint); + qoriq_serdes serdes; + QORIQ_FILL(0xe3000, 0xe4000, qoriq_serdes); + QORIQ_RESERVE(0xe4000, 0xf0000); + qoriq_boot_rom boot_rom; + QORIQ_FILL(0xf0000, 0x100000, qoriq_boot_rom); +} qoriq_ccsr; + +#endif /* QORIQ_CHIP_VARIANT */ + +extern volatile qoriq_ccsr qoriq; + +#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) +extern uint8_t qoriq_bman_portal[2][16777216]; +extern uint8_t qoriq_qman_portal[2][16777216]; + +void qoriq_clear_ce_portal(void *base, size_t size); +void qoriq_clear_ci_portal(void *base, size_t size); +#endif + +static inline void qoriq_reset_qman_and_bman(void) +{ +#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) + qoriq.dcfg.qmbm_warmrst = 0x3; + + while ((qoriq.dcfg.qmbm_warmrst & 0x3) != 0) { + /* Wait for reset done */ + } +#endif +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_QORIQ_QORIQ_H */ diff --git a/bsps/powerpc/qoriq/include/bsp/tsec-config.h b/bsps/powerpc/qoriq/include/bsp/tsec-config.h new file mode 100644 index 0000000000..b1a70e7486 --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp/tsec-config.h @@ -0,0 +1,36 @@ +/** + * @file + * + * @ingroup QorIQ + * + * @brief TSEC configuration. + */ + +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_TSEC_CONFIG_H +#define LIBBSP_POWERPC_QORIQ_TSEC_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define TSEC_COUNT 3 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_QORIQ_TSEC_CONFIG_H */ diff --git a/bsps/powerpc/qoriq/include/bsp/uart-bridge.h b/bsps/powerpc/qoriq/include/bsp/uart-bridge.h new file mode 100644 index 0000000000..97e6553b7c --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp/uart-bridge.h @@ -0,0 +1,72 @@ +/** + * @file + * + * @ingroup QorIQUartBridge + * + * @brief UART to Intercom bridge API. + */ + +/* + * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_UART_BRIDGE_H +#define LIBBSP_POWERPC_QORIQ_UART_BRIDGE_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup QorIQUartBridge QorIQ - UART to Intercom Bridge Support + * + * @ingroup QorIQ + * + * @brief UART to Intercom bridge support. + * + * @{ + */ + +typedef struct { + rtems_termios_device_context base; + const char *device_path; + intercom_type type; + rtems_id transmit_task; + rtems_chain_control transmit_fifo; +} uart_bridge_master_context; + +typedef struct { + rtems_termios_device_context base; + struct rtems_termios_tty *tty; + intercom_type type; + rtems_id transmit_task; + rtems_chain_control transmit_fifo; +} uart_bridge_slave_context; + +bool qoriq_uart_bridge_master_probe(rtems_termios_device_context *base); + +extern const rtems_termios_device_handler qoriq_uart_bridge_master; + +extern const rtems_termios_device_handler qoriq_uart_bridge_slave; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_QORIQ_UART_BRIDGE_H */ diff --git a/bsps/powerpc/qoriq/include/tm27.h b/bsps/powerpc/qoriq/include/tm27.h new file mode 100644 index 0000000000..46264b7e67 --- /dev/null +++ b/bsps/powerpc/qoriq/include/tm27.h @@ -0,0 +1,96 @@ +/** + * @file + * + * @ingroup QorIQ + * + * @brief Support file for Timer Test 27. + */ + +/* + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 + #error "This is an RTEMS internal file you must not include directly." +#endif /* _RTEMS_TMTEST27 */ + +#ifndef TMTESTS_TM27_H +#define TMTESTS_TM27_H + +#include + +#include + +#include +#include + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define IPI_INDEX_LOW 1 + +#define IPI_INDEX_HIGH 2 + +static void Install_tm27_vector(void (*handler)(rtems_vector_number)) +{ + rtems_status_code sc; + rtems_vector_number low = QORIQ_IRQ_IPI_0 + IPI_INDEX_LOW; + rtems_vector_number high = QORIQ_IRQ_IPI_0 + IPI_INDEX_HIGH; + + sc = rtems_interrupt_handler_install( + low, + "tm17 low", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = qoriq_pic_set_priority(low, 1, NULL); + assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_interrupt_handler_install( + high, + "tm17 high", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = qoriq_pic_set_priority(high, 2, NULL); + assert(sc == RTEMS_SUCCESSFUL); +} + +static void qoriq_tm27_cause(uint32_t ipi_index) +{ + uint32_t self = ppc_processor_id(); + + qoriq.pic.per_cpu[self].ipidr[ipi_index].reg = UINT32_C(1) << self; +} + +static void Cause_tm27_intr() +{ + qoriq_tm27_cause(IPI_INDEX_LOW); +} + +static void Clear_tm27_intr() +{ + /* Nothing to do */ +} + +static void Lower_tm27_intr(void) +{ + qoriq_tm27_cause(IPI_INDEX_HIGH); +} + +#endif /* TMTESTS_TM27_H */ diff --git a/bsps/powerpc/qoriq/include/uapi/asm/epapr_hcalls.h b/bsps/powerpc/qoriq/include/uapi/asm/epapr_hcalls.h new file mode 100644 index 0000000000..b4504f3944 --- /dev/null +++ b/bsps/powerpc/qoriq/include/uapi/asm/epapr_hcalls.h @@ -0,0 +1,98 @@ +/* + * ePAPR hcall interface + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * Author: Timur Tabi + * + * This file is provided under a dual BSD/GPL license. When using or + * redistributing this file, you may do so under either license. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _UAPI_ASM_POWERPC_EPAPR_HCALLS_H +#define _UAPI_ASM_POWERPC_EPAPR_HCALLS_H + +#define EV_BYTE_CHANNEL_SEND 1 +#define EV_BYTE_CHANNEL_RECEIVE 2 +#define EV_BYTE_CHANNEL_POLL 3 +#define EV_INT_SET_CONFIG 4 +#define EV_INT_GET_CONFIG 5 +#define EV_INT_SET_MASK 6 +#define EV_INT_GET_MASK 7 +#define EV_INT_IACK 9 +#define EV_INT_EOI 10 +#define EV_INT_SEND_IPI 11 +#define EV_INT_SET_TASK_PRIORITY 12 +#define EV_INT_GET_TASK_PRIORITY 13 +#define EV_DOORBELL_SEND 14 +#define EV_MSGSND 15 +#define EV_IDLE 16 + +/* vendor ID: epapr */ +#define EV_LOCAL_VENDOR_ID 0 /* for private use */ +#define EV_EPAPR_VENDOR_ID 1 +#define EV_FSL_VENDOR_ID 2 /* Freescale Semiconductor */ +#define EV_IBM_VENDOR_ID 3 /* IBM */ +#define EV_GHS_VENDOR_ID 4 /* Green Hills Software */ +#define EV_ENEA_VENDOR_ID 5 /* Enea */ +#define EV_WR_VENDOR_ID 6 /* Wind River Systems */ +#define EV_AMCC_VENDOR_ID 7 /* Applied Micro Circuits */ +#define EV_KVM_VENDOR_ID 42 /* KVM */ + +/* The max number of bytes that a byte channel can send or receive per call */ +#define EV_BYTE_CHANNEL_MAX_BYTES 16 + + +#define _EV_HCALL_TOKEN(id, num) (((id) << 16) | (num)) +#define EV_HCALL_TOKEN(hcall_num) _EV_HCALL_TOKEN(EV_EPAPR_VENDOR_ID, hcall_num) + +/* epapr return codes */ +#define EV_SUCCESS 0 +#define EV_EPERM 1 /* Operation not permitted */ +#define EV_ENOENT 2 /* Entry Not Found */ +#define EV_EIO 3 /* I/O error occurred */ +#define EV_EAGAIN 4 /* The operation had insufficient + * resources to complete and should be + * retried + */ +#define EV_ENOMEM 5 /* There was insufficient memory to + * complete the operation */ +#define EV_EFAULT 6 /* Bad guest address */ +#define EV_ENODEV 7 /* No such device */ +#define EV_EINVAL 8 /* An argument supplied to the hcall + was out of range or invalid */ +#define EV_INTERNAL 9 /* An internal error occurred */ +#define EV_CONFIG 10 /* A configuration error was detected */ +#define EV_INVALID_STATE 11 /* The object is in an invalid state */ +#define EV_UNIMPLEMENTED 12 /* Unimplemented hypercall */ +#define EV_BUFFER_OVERFLOW 13 /* Caller-supplied buffer too small */ + +#endif /* _UAPI_ASM_POWERPC_EPAPR_HCALLS_H */ diff --git a/bsps/powerpc/ss555/headers.am b/bsps/powerpc/ss555/headers.am new file mode 100644 index 0000000000..f53a4bd6b2 --- /dev/null +++ b/bsps/powerpc/ss555/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/ss555/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/ss555/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/ss555/include/bsp/irq.h diff --git a/bsps/powerpc/ss555/include/bsp.h b/bsps/powerpc/ss555/include/bsp.h new file mode 100644 index 0000000000..a82d10a667 --- /dev/null +++ b/bsps/powerpc/ss555/include/bsp.h @@ -0,0 +1,91 @@ +/* + * This file includes definitions for the Intec SS555. + */ + +/* + * SS555 port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h: + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SS555_BSP_H +#define LIBBSP_POWERPC_SS555_BSP_H + +#ifndef ASM + +#include +#include + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Clock definitions + */ + +#define BSP_CRYSTAL_HZ 4000000 /* crystal frequency, Hz */ +#define BSP_CLOCK_HZ 40000000 /* CPU clock frequency, Hz + +/* + * I/O definitions + * + * The SS555 board includes a CPLD to control on-board features and + * off-board devices. + */ +typedef struct cpld_ { + uint8_t cs3a[32]; /* Chip select 3A */ + uint8_t pad0[0x200000 - 0x000020]; + + uint8_t cs3b[32]; /* Chip select 3B */ + uint8_t pad2[0x400000 - 0x200020]; + + uint8_t cs3c[32]; /* Chip select 3C */ + uint8_t pad4[0x600000 - 0x400020]; + + uint8_t cs3d[32]; /* Chip select 3D */ + uint8_t pad6[0x800000 - 0x600020]; + + uint8_t serial_ints; /* Enable/disable serial interrupts */ + uint8_t serial_resets; /* Enable/disable serial resets */ + uint8_t serial_ack; /* Acknowledge serial transfers */ + uint8_t pad8[0xA00000 - 0x800003]; + + uint8_t iflash_writess; /* Enable/disable internal-flash writes */ + uint8_t nflash_writess; /* Enable/disable NAND-flash writes */ + uint8_t padA[0xC00000 - 0xA00002]; +} cpld_t; + +extern volatile cpld_t cpld; /* defined in linkcmds */ + +/* clock/p_clock.c */ +extern int BSP_disconnect_clock_handler (void); + +extern int BSP_connect_clock_handler (rtems_irq_hdl hdl); + +/* + * Prototypes for methods called from .S to support dependency tracking. + */ +void _InitSS555(void); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/powerpc/ss555/include/bsp/irq.h b/bsps/powerpc/ss555/include/bsp/irq.h new file mode 100644 index 0000000000..44e39608b1 --- /dev/null +++ b/bsps/powerpc/ss555/include/bsp/irq.h @@ -0,0 +1,66 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * + * SS555 port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from libbsp/powerpc/mbx8xx/irq/irq.h: + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SS555_IRQ_IRQ_H +#define LIBBSP_POWERPC_SS555_IRQ_IRQ_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * These are no longer prototyped anywhere else. This appears to be + * remnants of the IRQ code upgrade. + * + * --joel 28 April 2010 + */ +int CPU_install_rtems_irq_handler(const rtems_irq_connect_data* irq); +int CPU_get_current_rtems_irq_handler(rtems_irq_connect_data* irq); +int CPU_remove_rtems_irq_handler(const rtems_irq_connect_data* irq); +int CPU_rtems_irq_mngt_set(rtems_irq_global_settings* config); +int CPU_rtems_irq_mngt_get(rtems_irq_global_settings** config); +void C_default_exception_handler(CPU_Exception_frame* excPtr); + +/* + * The SS555 has no external interrupt controller chip, so use the standard + * routines from the CPU-dependent code. + */ +#define BSP_install_rtems_irq_handler(ptr) CPU_install_rtems_irq_handler(ptr) +#define BSP_get_current_rtems_irq_handler(ptr) CPU_get_current_rtems_irq_handler(ptr) +#define BSP_remove_rtems_irq_handler(ptr) CPU_remove_rtems_irq_handler(ptr) +#define BSP_rtems_irq_mngt_set(config) CPU_rtems_irq_mngt_set(config) +#define BSP_rtems_irq_mngt_get(config) CPU_rtems_irq_mngt_get(config) +#define BSP_rtems_irq_mng_init(cpuId) CPU_rtems_irq_mng_init(cpuId) + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* LIBBSP_POWERPC_SS555_IRQ_IRQ_H */ diff --git a/bsps/powerpc/ss555/include/tm27.h b/bsps/powerpc/ss555/include/tm27.h new file mode 100644 index 0000000000..5106801744 --- /dev/null +++ b/bsps/powerpc/ss555/include/tm27.h @@ -0,0 +1,56 @@ +/* + * @file + * @ingroup powerpc_ss555 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * + * The following require that IRQ7 be jumpered to ground. On the SS555, + * this can be done by shorting together CN5 pin 48 and CN5 pin 50. + */ + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ +{ \ + extern rtems_irq_connect_data tm27IrqData; \ + usiu.siel |= (1 << 17); \ + usiu.sipend |= (1 << 17); \ + \ + tm27IrqData.hdl = (rtems_irq_hdl)handler; \ + BSP_install_rtems_irq_handler (&tm27IrqData); \ +} + +#define Cause_tm27_intr() \ +{ \ + usiu.siel &= ~(1 << 17); \ +} + +#define Clear_tm27_intr() \ +{ \ + usiu.siel |= (1 << 17); \ + usiu.sipend |= (1 << 17); \ +} + +#define Lower_tm27_intr() \ +{ \ + ppc_cached_irq_mask |= (1 << 17); \ + usiu.simask = ppc_cached_irq_mask; \ +} + +#endif diff --git a/bsps/powerpc/t32mppc/headers.am b/bsps/powerpc/t32mppc/headers.am new file mode 100644 index 0000000000..57d3bd9be1 --- /dev/null +++ b/bsps/powerpc/t32mppc/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/t32mppc/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/t32mppc/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/t32mppc/include/bsp/irq.h diff --git a/bsps/powerpc/t32mppc/include/bsp.h b/bsps/powerpc/t32mppc/include/bsp.h new file mode 100644 index 0000000000..c27f235ef6 --- /dev/null +++ b/bsps/powerpc/t32mppc/include/bsp.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2012, 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_T32MPPC_BSP_H +#define LIBBSP_POWERPC_T32MPPC_BSP_H + +#include + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +extern uint32_t bsp_time_base_frequency; + +void t32mppc_decrementer_dispatch(void); + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_T32MPPC_BSP_H */ diff --git a/bsps/powerpc/t32mppc/include/bsp/irq.h b/bsps/powerpc/t32mppc/include/bsp/irq.h new file mode 100644 index 0000000000..0053aa5ac1 --- /dev/null +++ b/bsps/powerpc/t32mppc/include/bsp/irq.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2012, 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_T32MPPC_IRQ_H +#define LIBBSP_POWERPC_T32MPPC_IRQ_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 0 + +RTEMS_INLINE_ROUTINE void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +) +{ + (void) vector; + (void) affinity; +} + +RTEMS_INLINE_ROUTINE void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +) +{ + (void) vector; + _Processor_mask_From_index( affinity, 0 ); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_T32MPPC_IRQ_H */ diff --git a/bsps/powerpc/t32mppc/include/tm27.h b/bsps/powerpc/t32mppc/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/t32mppc/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/powerpc/tqm8xx/headers.am b/bsps/powerpc/tqm8xx/headers.am new file mode 100644 index 0000000000..a3c97f53da --- /dev/null +++ b/bsps/powerpc/tqm8xx/headers.am @@ -0,0 +1,13 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/tqm8xx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/tqm8xx/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/tqm8xx/include/bsp/8xx_immap.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/tqm8xx/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/tqm8xx/include/bsp/spi.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/tqm8xx/include/bsp/tqm.h diff --git a/bsps/powerpc/tqm8xx/include/bsp.h b/bsps/powerpc/tqm8xx/include/bsp.h new file mode 100644 index 0000000000..5c8eae81b4 --- /dev/null +++ b/bsps/powerpc/tqm8xx/include/bsp.h @@ -0,0 +1,169 @@ +/* + * RTEMS TQM8xx BSP + * This include file contains all board IO definitions. + */ + +/* + * This file has been adapted to MPC8xx by: + * Thomas Doerfler + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * COPYRIGHT (c) 1989-2008. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_TQM8XX_BSP_H +#define LIBBSP_POWERPC_TQM8XX_BSP_H + +/* + * indicate, that BSP is booted via TQMMon + */ +#define BSP_HAS_TQMMON + +#include + +LINKER_SYMBOL(TopRamReserved); + +LINKER_SYMBOL( bsp_ram_start); +LINKER_SYMBOL( bsp_ram_end); +LINKER_SYMBOL( bsp_ram_size); + +LINKER_SYMBOL( bsp_rom_start); +LINKER_SYMBOL( bsp_rom_end); +LINKER_SYMBOL( bsp_rom_size); + +LINKER_SYMBOL( bsp_section_text_start); +LINKER_SYMBOL( bsp_section_text_end); +LINKER_SYMBOL( bsp_section_text_size); + +LINKER_SYMBOL( bsp_section_data_start); +LINKER_SYMBOL( bsp_section_data_end); +LINKER_SYMBOL( bsp_section_data_size); + +LINKER_SYMBOL( bsp_section_bss_start); +LINKER_SYMBOL( bsp_section_bss_end); +LINKER_SYMBOL( bsp_section_bss_size); + +LINKER_SYMBOL( bsp_interrupt_stack_start); +LINKER_SYMBOL( bsp_interrupt_stack_end); +LINKER_SYMBOL( bsp_interrupt_stack_size); + +LINKER_SYMBOL( bsp_work_area_start); + +#ifndef ASM + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; + +#if BSP_USE_NETWORK_FEC +extern int rtems_fec_enet_driver_attach (struct rtems_bsdnet_ifconfig *config, + int attaching); +#define RTEMS_BSP_FEC_NETWORK_DRIVER_NAME "fec1" +#define RTEMS_BSP_FEC_NETWORK_DRIVER_ATTACH rtems_fec_enet_driver_attach +#endif + +#if BSP_USE_NETWORK_SCC +extern int rtems_scc_enet_driver_attach (struct rtems_bsdnet_ifconfig *config, + int attaching); +#define RTEMS_BSP_SCC_NETWORK_DRIVER_NAME "scc1" +#define RTEMS_BSP_SCC_NETWORK_DRIVER_ATTACH rtems_scc_enet_driver_attach +#endif + +#if BSP_USE_NETWORK_FEC +#define RTEMS_BSP_NETWORK_DRIVER_NAME RTEMS_BSP_FEC_NETWORK_DRIVER_NAME +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH RTEMS_BSP_FEC_NETWORK_DRIVER_ATTACH +#elif BSP_USE_NETWORK_SCC +#define RTEMS_BSP_NETWORK_DRIVER_NAME RTEMS_BSP_SCC_NETWORK_DRIVER_NAME +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH RTEMS_BSP_SCC_NETWORK_DRIVER_ATTACH +#endif +/* + * We need to decide how much memory will be non-cacheable. This + * will mainly be memory that will be used in DMA (network and serial + * buffers). + */ +#define NOCACHE_MEM_SIZE 512*1024 + +/* + * indicate, that BSP has IDE driver + */ +#undef RTEMS_BSP_HAS_IDE_DRIVER + +/* + * SPI driver configuration + */ + + /* select values for SPI addressing */ +#define PGHPLUS_SPI_ADDR_EEPROM 0 +#define PGHPLUS_SPI_ADDR_DISP4 1 + /* NOTE: DISP4 occupies two consecutive addresses for data and control port */ +#define PGHPLUS_SPI_ADDR_DISP4_DATA (PGHPLUS_SPI_ADDR_DISP4) +#define PGHPLUS_SPI_ADDR_DISP4_CTRL (PGHPLUS_SPI_ADDR_DISP4_DATA+1) + + /* bit masks for Port B lines */ +#define PGHPLUS_PB_SPI_EEP_CE_MSK (1<< 0) +#define PGHPLUS_PB_SPI_DISP4_RS_MSK (1<<15) +#define PGHPLUS_PB_SPI_DISP4_CE_MSK (1<<14) + +/* + * our (internal) bus frequency + */ +extern uint32_t BSP_bus_frequency; + +/* + * Interfaces to required Clock Driver support methods + */ +int BSP_disconnect_clock_handler(void); +int BSP_connect_clock_handler (rtems_irq_hdl); + +extern uint32_t bsp_clock_speed; + +char serial_getc(void); + +int serial_tstc(void); + +void serial_init(void); + +int mbx8xx_console_get_configuration(void); + +void _InitTQM8xx (void); + +rtems_status_code bsp_register_spi(void); + +void *bsp_idle_thread( uintptr_t ignored ); + +void cpu_init(void); + +#ifdef __cplusplus +} +#endif + +#endif +#endif diff --git a/bsps/powerpc/tqm8xx/include/bsp/8xx_immap.h b/bsps/powerpc/tqm8xx/include/bsp/8xx_immap.h new file mode 100644 index 0000000000..c1c414e25f --- /dev/null +++ b/bsps/powerpc/tqm8xx/include/bsp/8xx_immap.h @@ -0,0 +1,477 @@ +/*===============================================================*\ +| Project: RTEMS BSP support for TQ modules | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains definitions to interact with TQC's | +| processor modules | +\*===============================================================*/ +/* derived from mbx8xx BSP */ +/* + * MPC8xx Internal Memory Map + * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) + * + * The I/O on the MPC860 is comprised of blocks of special registers + * and the dual port ram for the Communication Processor Module. + * Within this space are functional units such as the SIU, memory + * controller, system timers, and other control functions. It is + * a combination that I found difficult to separate into logical + * functional files.....but anyone else is welcome to try. -- Dan + */ +#ifndef __IMMAP_8XX__ +#define __IMMAP_8XX__ + +/* System configuration registers. +*/ +typedef struct sys_conf { + unsigned int sc_siumcr; + unsigned int sc_sypcr; + unsigned int sc_swt; + char res1[2]; + unsigned short sc_swsr; + unsigned int sc_sipend; + unsigned int sc_simask; + unsigned int sc_siel; + unsigned int sc_sivec; + unsigned int sc_tesr; + char res2[0xc]; + unsigned int sc_sdcr; + char res3[0x4c]; +} sysconf8xx_t; + +/* PCMCIA configuration registers. +*/ +typedef struct pcmcia_conf { + unsigned int pcmc_pbr0; + unsigned int pcmc_por0; + unsigned int pcmc_pbr1; + unsigned int pcmc_por1; + unsigned int pcmc_pbr2; + unsigned int pcmc_por2; + unsigned int pcmc_pbr3; + unsigned int pcmc_por3; + unsigned int pcmc_pbr4; + unsigned int pcmc_por4; + unsigned int pcmc_pbr5; + unsigned int pcmc_por5; + unsigned int pcmc_pbr6; + unsigned int pcmc_por6; + unsigned int pcmc_pbr7; + unsigned int pcmc_por7; + char res1[0x20]; + unsigned int pcmc_pgcra; + unsigned int pcmc_pgcrb; + unsigned int pcmc_pscr; + char res2[4]; + unsigned int pcmc_pipr; + char res3[4]; + unsigned int pcmc_per; + char res4[4]; +} pcmconf8xx_t; + +/* Memory controller registers. +*/ +typedef struct mem_ctlr { + unsigned int memc_br0; + unsigned int memc_or0; + unsigned int memc_br1; + unsigned int memc_or1; + unsigned int memc_br2; + unsigned int memc_or2; + unsigned int memc_br3; + unsigned int memc_or3; + unsigned int memc_br4; + unsigned int memc_or4; + unsigned int memc_br5; + unsigned int memc_or5; + unsigned int memc_br6; + unsigned int memc_or6; + unsigned int memc_br7; + unsigned int memc_or7; + char res1[0x24]; + unsigned int memc_mar; + unsigned int memc_mcr; + char res2[4]; + unsigned int memc_mamr; + unsigned int memc_mbmr; + unsigned short memc_mstat; + unsigned short memc_mptpr; + unsigned int memc_mdr; + char res3[0x80]; +} memctl8xx_t; + +/* System Integration Timers. +*/ +typedef struct sys_int_timers { + unsigned short sit_tbscr; + unsigned int sit_tbreff0; + unsigned int sit_tbreff1; + char res1[0x14]; + unsigned short sit_rtcsc; + unsigned int sit_rtc; + unsigned int sit_rtsec; + unsigned int sit_rtcal; + char res2[0x10]; + unsigned short sit_piscr; + char res3[2]; + unsigned int sit_pitc; + unsigned int sit_pitr; + char res4[0x34]; +} sit8xx_t; + +#define TBSCR_TBIRQ_MASK ((unsigned short)0xff00) +#define TBSCR_REFA ((unsigned short)0x0080) +#define TBSCR_REFB ((unsigned short)0x0040) +#define TBSCR_REFAE ((unsigned short)0x0008) +#define TBSCR_REFBE ((unsigned short)0x0004) +#define TBSCR_TBF ((unsigned short)0x0002) +#define TBSCR_TBE ((unsigned short)0x0001) + +#define RTCSC_RTCIRQ_MASK ((unsigned short)0xff00) +#define RTCSC_SEC ((unsigned short)0x0080) +#define RTCSC_ALR ((unsigned short)0x0040) +#define RTCSC_38K ((unsigned short)0x0010) +#define RTCSC_SIE ((unsigned short)0x0008) +#define RTCSC_ALE ((unsigned short)0x0004) +#define RTCSC_RTF ((unsigned short)0x0002) +#define RTCSC_RTE ((unsigned short)0x0001) + +#define PISCR_PIRQ_MASK ((unsigned short)0xff00) +#define PISCR_PS ((unsigned short)0x0080) +#define PISCR_PIE ((unsigned short)0x0004) +#define PISCR_PTF ((unsigned short)0x0002) +#define PISCR_PTE ((unsigned short)0x0001) + +/* Clocks and Reset. +*/ +typedef struct clk_and_reset { + unsigned int car_sccr; + unsigned int car_plprcr; + unsigned int car_rsr; + char res[0x74]; /* Reserved area */ +} car8xx_t; + +/* System Integration Timers keys. +*/ +typedef struct sitk { + unsigned int sitk_tbscrk; + unsigned int sitk_tbreff0k; + unsigned int sitk_tbreff1k; + unsigned int sitk_tbk; + char res1[0x10]; + unsigned int sitk_rtcsck; + unsigned int sitk_rtck; + unsigned int sitk_rtseck; + unsigned int sitk_rtcalk; + char res2[0x10]; + unsigned int sitk_piscrk; + unsigned int sitk_pitck; + char res3[0x38]; +} sitk8xx_t; + +/* Clocks and reset keys. +*/ +typedef struct cark { + unsigned int cark_sccrk; + unsigned int cark_plprcrk; + unsigned int cark_rsrk; + char res[0x474]; +} cark8xx_t; + +/* The key to unlock registers maintained by keep-alive power. +*/ +#define KAPWR_KEY ((unsigned int)0x55ccaa33) + +/* LCD interface. MPC821 Only. +*/ +typedef struct lcd { + unsigned short lcd_lcolr[16]; + char res[0x20]; + unsigned int lcd_lccr; + unsigned int lcd_lchcr; + unsigned int lcd_lcvcr; + char res2[4]; + unsigned int lcd_lcfaa; + unsigned int lcd_lcfba; + char lcd_lcsr; + char res3[0x7]; +} lcd8xx_t; + +/* I2C +*/ +typedef struct i2c { + unsigned char i2c_i2mod; + char res1[3]; + unsigned char i2c_i2add; + char res2[3]; + unsigned char i2c_i2brg; + char res3[3]; + unsigned char i2c_i2com; + char res4[3]; + unsigned char i2c_i2cer; + char res5[3]; + unsigned char i2c_i2cmr; + char res6[0x8b]; +} i2c8xx_t; + +/* DMA control/status registers. +*/ +typedef struct sdma_csr { + char res1[4]; + unsigned int sdma_sdar; + unsigned char sdma_sdsr; + char res3[3]; + unsigned char sdma_sdmr; + char res4[3]; + unsigned char sdma_idsr1; + char res5[3]; + unsigned char sdma_idmr1; + char res6[3]; + unsigned char sdma_idsr2; + char res7[3]; + unsigned char sdma_idmr2; + char res8[0x13]; +} sdma8xx_t; + +/* Communication Processor Module Interrupt Controller. +*/ +typedef struct cpm_ic { + unsigned short cpic_civr; + char res[0xe]; + unsigned int cpic_cicr; + unsigned int cpic_cipr; + unsigned int cpic_cimr; + unsigned int cpic_cisr; +} cpic8xx_t; + +/* Input/Output Port control/status registers. +*/ +typedef struct io_port { + unsigned short iop_padir; + unsigned short iop_papar; + unsigned short iop_paodr; + unsigned short iop_padat; + char res1[8]; + unsigned short iop_pcdir; + unsigned short iop_pcpar; + unsigned short iop_pcso; + unsigned short iop_pcdat; + unsigned short iop_pcint; + char res2[6]; + unsigned short iop_pddir; + unsigned short iop_pdpar; + char res3[2]; + unsigned short iop_pddat; + char res4[8]; +} iop8xx_t; + +/* Communication Processor Module Timers +*/ +typedef struct cpm_timers { + unsigned short cpmt_tgcr; + char res1[0xe]; + unsigned short cpmt_tmr1; + unsigned short cpmt_tmr2; + unsigned short cpmt_trr1; + unsigned short cpmt_trr2; + unsigned short cpmt_tcr1; + unsigned short cpmt_tcr2; + unsigned short cpmt_tcn1; + unsigned short cpmt_tcn2; + unsigned short cpmt_tmr3; + unsigned short cpmt_tmr4; + unsigned short cpmt_trr3; + unsigned short cpmt_trr4; + unsigned short cpmt_tcr3; + unsigned short cpmt_tcr4; + unsigned short cpmt_tcn3; + unsigned short cpmt_tcn4; + unsigned short cpmt_ter1; + unsigned short cpmt_ter2; + unsigned short cpmt_ter3; + unsigned short cpmt_ter4; + char res2[8]; +} cpmtimer8xx_t; + +/* Finally, the Communication Processor stuff..... +*/ +typedef struct scc { /* Serial communication channels */ + unsigned int scc_gsmrl; + unsigned int scc_gsmrh; + unsigned short scc_pmsr; + char res1[2]; + unsigned short scc_todr; + unsigned short scc_dsr; + unsigned short scc_scce; + char res2[2]; + unsigned short scc_sccm; + char res3; + unsigned char scc_sccs; + char res4[8]; +} scc_t; + +typedef struct smc { /* Serial management channels */ + char res1[2]; + unsigned short smc_smcmr; + char res2[2]; + unsigned char smc_smce; + char res3[3]; + unsigned char smc_smcm; + char res4[5]; +} smc_t; + +/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but + * it fits within the address space. + */ +typedef struct fec { + unsigned int fec_addr_low; /* LS 32 bits of station address */ + unsigned short fec_addr_high; /* MS 16 bits of address */ + unsigned short res1; + unsigned int fec_hash_table_high; + unsigned int fec_hash_table_low; + unsigned int fec_r_des_start; + unsigned int fec_x_des_start; + unsigned int fec_r_buff_size; + unsigned int res2[9]; + unsigned int fec_ecntrl; + unsigned int fec_ievent; + unsigned int fec_imask; + unsigned int fec_ivec; + unsigned int fec_r_des_active; + unsigned int fec_x_des_active; + unsigned int res3[10]; + unsigned int fec_mii_data; + unsigned int fec_mii_speed; + unsigned int res4[17]; + unsigned int fec_r_bound; + unsigned int fec_r_fstart; + unsigned int res5[6]; + unsigned int fec_x_fstart; + unsigned int res6[17]; + unsigned int fec_fun_code; + unsigned int res7[3]; + unsigned int fec_r_cntrl; + unsigned int fec_r_hash; + unsigned int res8[14]; + unsigned int fec_x_cntrl; + unsigned int res9[0x1e]; +} fec_t; + +typedef struct comm_proc { + /* General control and status registers. + */ + unsigned short cp_cpcr; + char res1[2]; + unsigned short cp_rccr; + char res2[6]; + unsigned short cp_cpmcr1; + unsigned short cp_cpmcr2; + unsigned short cp_cpmcr3; + unsigned short cp_cpmcr4; + char res3[2]; + unsigned short cp_rter; + char res4[2]; + unsigned short cp_rtmr; + char res5[0x14]; + + /* Baud rate generators. + */ + unsigned int cp_brgc1; + unsigned int cp_brgc2; + unsigned int cp_brgc3; + unsigned int cp_brgc4; + + /* Serial Communication Channels. + */ + scc_t cp_scc[4]; + + /* Serial Management Channels. + */ + smc_t cp_smc[2]; + + /* Serial Peripheral Interface. + */ + unsigned short cp_spmode; + char res6[4]; + unsigned char cp_spie; + char res7[3]; + unsigned char cp_spim; + char res8[2]; + unsigned char cp_spcom; + char res9[2]; + + /* Parallel Interface Port. + */ + char res10[2]; + unsigned short cp_pipc; + char res11[2]; + unsigned short cp_ptpr; + unsigned int cp_pbdir; + unsigned int cp_pbpar; + char res12[2]; + unsigned short cp_pbodr; + unsigned int cp_pbdat; + char res13[0x18]; + + /* Serial Interface and Time Slot Assignment. + */ + unsigned int cp_simode; + unsigned char cp_sigmr; + char res14; + unsigned char cp_sistr; + unsigned char cp_sicmr; + char res15[4]; + unsigned int cp_sicr; + unsigned int cp_sirp; + char res16[0x10c]; + unsigned char cp_siram[0x200]; + + /* The fast ethernet controller is not really part of the CPM, + * but it resides in the address space. + */ + fec_t cp_fec; + char res18[0x1000]; + + /* Dual Ported RAM follows. + * There are many different formats for this memory area + * depending upon the devices used and options chosen. + */ + unsigned char cp_dpmem[0x1000]; /* BD / Data / ucode */ + unsigned char res19[0xc00]; + unsigned char cp_dparam[0x400]; /* Parameter RAM */ +} cpm8xx_t; + +/* Internal memory map. +*/ +typedef struct immap { + sysconf8xx_t im_siu_conf; /* SIU Configuration */ + pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ + memctl8xx_t im_memctl; /* Memory Controller */ + sit8xx_t im_sit; /* System integration timers */ + car8xx_t im_clkrst; /* Clocks and reset */ + sitk8xx_t im_sitk; /* Sys int timer keys */ + cark8xx_t im_clkrstk; /* Clocks and reset keys */ + lcd8xx_t im_lcd; /* LCD (821 only) */ + i2c8xx_t im_i2c; /* I2C control/status */ + sdma8xx_t im_sdma; /* SDMA control/status */ + cpic8xx_t im_cpic; /* CPM Interrupt Controller */ + iop8xx_t im_ioport; /* IO Port control/status */ + cpmtimer8xx_t im_cpmtimer; /* CPM timers */ + cpm8xx_t im_cpm; /* Communication processor */ +} immap_t; + +#endif /* __IMMAP_8XX__ */ diff --git a/bsps/powerpc/tqm8xx/include/bsp/irq.h b/bsps/powerpc/tqm8xx/include/bsp/irq.h new file mode 100644 index 0000000000..2d66829037 --- /dev/null +++ b/bsps/powerpc/tqm8xx/include/bsp/irq.h @@ -0,0 +1,160 @@ +/*===============================================================*\ +| Project: RTEMS TQM8xx BSP | ++-----------------------------------------------------------------+ +| This file has been adapted to MPC8xx by | +| Thomas Doerfler | +| Copyright (c) 2008 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | +| | +| See the other copyright notice below for the original parts. | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains the console driver | +\*===============================================================*/ +/* derived from: generic MPC83xx BSP */ +#ifndef TQM8xx_IRQ_IRQ_H +#define TQM8xx_IRQ_IRQ_H + +#include + +#include +#include +#include + +/* + * the following definitions specify the indices used + * to interface the interrupt handler API + */ + +/* + * Peripheral IRQ handlers related definitions + */ +#define BSP_SIU_PER_IRQ_NUMBER 16 +#define BSP_SIU_IRQ_LOWEST_OFFSET 0 +#define BSP_SIU_IRQ_MAX_OFFSET (BSP_SIU_IRQ_LOWEST_OFFSET\ + +BSP_SIU_PER_IRQ_NUMBER-1) + +#define BSP_IS_SIU_IRQ(irqnum) \ + (((irqnum) >= BSP_SIU_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_SIU_IRQ_MAX_OFFSET)) + +#define BSP_CPM_PER_IRQ_NUMBER 32 +#define BSP_CPM_IRQ_LOWEST_OFFSET (BSP_SIU_IRQ_MAX_OFFSET+1) +#define BSP_CPM_IRQ_MAX_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET\ + +BSP_CPM_PER_IRQ_NUMBER-1) + +#define BSP_IS_CPM_IRQ(irqnum) \ + (((irqnum) >= BSP_CPM_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_CPM_IRQ_MAX_OFFSET)) +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 1 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET+1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ + +BSP_PROCESSOR_IRQ_NUMBER-1) + +#define BSP_IS_PROCESSOR_IRQ(irqnum) \ + (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) +#define BSP_LOWEST_OFFSET BSP_SIU_IRQ_LOWEST_OFFSET +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET + +#define BSP_IS_VALID_IRQ(irqnum) \ + (BSP_IS_PROCESSOR_IRQ(irqnum) \ + || BSP_IS_SIU_IRQ(irqnum) \ + || BSP_IS_CPM_IRQ(irqnum)) + +#ifndef ASM +#ifdef __cplusplus +extern "C" { +#endif + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ + typedef enum { + BSP_SIU_EXT_IRQ_0 = BSP_SIU_IRQ_LOWEST_OFFSET + 0, + BSP_SIU_INT_IRQ_0 = BSP_SIU_IRQ_LOWEST_OFFSET + 1, + BSP_SIU_EXT_IRQ_1 = BSP_SIU_IRQ_LOWEST_OFFSET + 2, + BSP_SIU_INT_IRQ_1 = BSP_SIU_IRQ_LOWEST_OFFSET + 3, + BSP_SIU_EXT_IRQ_2 = BSP_SIU_IRQ_LOWEST_OFFSET + 4, + BSP_SIU_INT_IRQ_2 = BSP_SIU_IRQ_LOWEST_OFFSET + 5, + BSP_SIU_EXT_IRQ_3 = BSP_SIU_IRQ_LOWEST_OFFSET + 6, + BSP_SIU_INT_IRQ_3 = BSP_SIU_IRQ_LOWEST_OFFSET + 7, + BSP_SIU_EXT_IRQ_4 = BSP_SIU_IRQ_LOWEST_OFFSET + 8, + BSP_SIU_INT_IRQ_4 = BSP_SIU_IRQ_LOWEST_OFFSET + 9, + BSP_SIU_EXT_IRQ_5 = BSP_SIU_IRQ_LOWEST_OFFSET + 10, + BSP_SIU_INT_IRQ_5 = BSP_SIU_IRQ_LOWEST_OFFSET + 11, + BSP_SIU_EXT_IRQ_6 = BSP_SIU_IRQ_LOWEST_OFFSET + 12, + BSP_SIU_INT_IRQ_6 = BSP_SIU_IRQ_LOWEST_OFFSET + 13, + BSP_SIU_EXT_IRQ_7 = BSP_SIU_IRQ_LOWEST_OFFSET + 14, + BSP_SIU_INT_IRQ_7 = BSP_SIU_IRQ_LOWEST_OFFSET + 15, + BSP_SIU_IRQ_LAST = BSP_SIU_IRQ_MAX_OFFSET, + /* + * Some CPM IRQ symbolic name definition + */ + BSP_CPM_IRQ_ERROR = (BSP_CPM_IRQ_LOWEST_OFFSET), + BSP_CPM_IRQ_PARALLEL_IO_PC4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 1), + BSP_CPM_IRQ_PARALLEL_IO_PC5 = (BSP_CPM_IRQ_LOWEST_OFFSET + 2), + BSP_CPM_IRQ_SMC2_OR_PIP = (BSP_CPM_IRQ_LOWEST_OFFSET + 3), + BSP_CPM_IRQ_SMC1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 4), + BSP_CPM_IRQ_SPI = (BSP_CPM_IRQ_LOWEST_OFFSET + 5), + BSP_CPM_IRQ_PARALLEL_IO_PC6 = (BSP_CPM_IRQ_LOWEST_OFFSET + 6), + BSP_CPM_IRQ_TIMER_4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 7), + BSP_CPM_IRQ_PARALLEL_IO_PC7 = (BSP_CPM_IRQ_LOWEST_OFFSET + 9), + BSP_CPM_IRQ_PARALLEL_IO_PC8 = (BSP_CPM_IRQ_LOWEST_OFFSET + 10), + BSP_CPM_IRQ_PARALLEL_IO_PC9 = (BSP_CPM_IRQ_LOWEST_OFFSET + 11), + BSP_CPM_IRQ_TIMER_3 = (BSP_CPM_IRQ_LOWEST_OFFSET + 12), + BSP_CPM_IRQ_PARALLEL_IO_PC10= (BSP_CPM_IRQ_LOWEST_OFFSET + 14), + BSP_CPM_IRQ_PARALLEL_IO_PC11= (BSP_CPM_IRQ_LOWEST_OFFSET + 15), + BSP_CPM_I2C = (BSP_CPM_IRQ_LOWEST_OFFSET + 16), + BSP_CPM_RISC_TIMER_TABLE = (BSP_CPM_IRQ_LOWEST_OFFSET + 17), + BSP_CPM_IRQ_TIMER_2 = (BSP_CPM_IRQ_LOWEST_OFFSET + 18), + BSP_CPM_IDMA2 = (BSP_CPM_IRQ_LOWEST_OFFSET + 20), + BSP_CPM_IDMA1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 21), + BSP_CPM_SDMA_CHANNEL_BUS_ERR= (BSP_CPM_IRQ_LOWEST_OFFSET + 22), + BSP_CPM_IRQ_PARALLEL_IO_PC12= (BSP_CPM_IRQ_LOWEST_OFFSET + 23), + BSP_CPM_IRQ_PARALLEL_IO_PC13= (BSP_CPM_IRQ_LOWEST_OFFSET + 24), + BSP_CPM_IRQ_TIMER_1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 25), + BSP_CPM_IRQ_PARALLEL_IO_PC14= (BSP_CPM_IRQ_LOWEST_OFFSET + 26), + BSP_CPM_IRQ_SCC4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 27), + BSP_CPM_IRQ_SCC3 = (BSP_CPM_IRQ_LOWEST_OFFSET + 28), + BSP_CPM_IRQ_SCC2 = (BSP_CPM_IRQ_LOWEST_OFFSET + 29), + BSP_CPM_IRQ_SCC1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 30), + BSP_CPM_IRQ_PARALLEL_IO_PC15= (BSP_CPM_IRQ_LOWEST_OFFSET + 31), + BSP_CPM_IRQ_LAST = BSP_CPM_IRQ_MAX_OFFSET, + } rtems_irq_symbolic_name; + + /* + * Symbolic name for CPM interrupt on SIU Internal level 2 + */ +#define BSP_CPM_INTERRUPT BSP_SIU_INT_IRQ_2 +#define BSP_PERIODIC_TIMER BSP_SIU_INT_IRQ_6 +#define BSP_FAST_ETHERNET_CTRL BSP_SIU_INT_IRQ_3 + +#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET + +#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET + +extern int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine); + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ + +#endif /* TQM8XX_IRQ_IRQ_H */ diff --git a/bsps/powerpc/tqm8xx/include/bsp/spi.h b/bsps/powerpc/tqm8xx/include/bsp/spi.h new file mode 100644 index 0000000000..e2af971c8d --- /dev/null +++ b/bsps/powerpc/tqm8xx/include/bsp/spi.h @@ -0,0 +1,146 @@ +/*===============================================================*\ +| Project: RTEMS support for MPC8xx | ++-----------------------------------------------------------------+ +| Copyright (c) 2009 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains the MPC8xx SPI driver declarations | +\*===============================================================*/ +#ifndef _M8XX_SPIDRV_H +#define _M8XX_SPIDRV_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct m8xx_spi_softc { + int initialized; + rtems_id irq_sema_id; + rtems_isr_entry old_handler; + m8xxBufferDescriptor_t *rx_bd; + m8xxBufferDescriptor_t *tx_bd; +} m8xx_spi_softc_t ; + +typedef struct { + rtems_libi2c_bus_t bus_desc; + m8xx_spi_softc_t softc; +} m8xx_spi_desc_t; + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code m8xx_spi_init +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| initialize the driver | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh /* bus specifier structure */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int m8xx_spi_read_bytes +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| receive some bytes from SPI device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + unsigned char *buf, /* buffer to store bytes */ + int len /* number of bytes to receive */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| number of bytes received or (negative) error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int m8xx_spi_write_bytes +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| send some bytes to SPI device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + unsigned char *buf, /* buffer to send */ + int len /* number of bytes to send */ + + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| number of bytes sent or (negative) error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code m8xx_spi_set_tfr_mode +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| set SPI to desired baudrate/clock mode/character mode | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + const rtems_libi2c_tfr_mode_t *tfr_mode /* transfer mode info */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int m8xx_spi_ioctl +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| perform selected ioctl function for SPI | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + int cmd, /* ioctl command code */ + void *arg /* additional argument array */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +#ifdef __cplusplus +} +#endif + + +#endif /* _M8XX_SPIDRV_H */ diff --git a/bsps/powerpc/tqm8xx/include/bsp/tqm.h b/bsps/powerpc/tqm8xx/include/bsp/tqm.h new file mode 100644 index 0000000000..11f6001304 --- /dev/null +++ b/bsps/powerpc/tqm8xx/include/bsp/tqm.h @@ -0,0 +1,51 @@ +/*===============================================================*\ +| Project: RTEMS BSP support for TQ modules | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains definitions to interact with TQC's | +| processor modules | +\*===============================================================*/ + +#ifndef __TQM_H__ +#define __TQM_H__ +#include + +typedef struct { + uint32_t sdram_size; /* existing SDRAM size */ + uint32_t flash_base; /* start address flash */ + uint32_t flash_size; /* existing Flash size */ + uint32_t flash_offset; + uint32_t sram_base; /* start address sram */ + uint32_t sram_size; /* existing sram size */ + uint32_t immr_base; /* start address internal memory map */ + uint32_t reboot; /* reboot flag */ + uint8_t ip_addr[4]; /* IP address */ + uint8_t eth_addr[6]; /* ethernet (MAC) address */ + uint8_t gap_42[2]; /* gap for alignment */ + void (*put_char)(int c); /* function to output characters */ +} tqm_bd_info_t; + +#define TQM_BD_INFO_ADDR 0x3400 +#define TQM_BD_INFO (*(tqm_bd_info_t *)TQM_BD_INFO_ADDR) + +#define TQM_CONF_INFO_BLOCK_ADDR 0x4001fe00 + +#define IMAP_ADDR ((unsigned int)0xfa200000) +#define IMAP_SIZE ((unsigned int)(64 * 1024)) + +#endif /* __TQM_H__ */ diff --git a/bsps/powerpc/tqm8xx/include/tm27.h b/bsps/powerpc/tqm8xx/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/tqm8xx/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/powerpc/virtex/headers.am b/bsps/powerpc/virtex/headers.am new file mode 100644 index 0000000000..9feceaf16d --- /dev/null +++ b/bsps/powerpc/virtex/headers.am @@ -0,0 +1,13 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/virtex/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/virtex/include/tm27.h +include_HEADERS += ../../../../../../bsps/powerpc/virtex/include/xiltemac.h +include_HEADERS += ../../../../../../bsps/powerpc/virtex/include/xparameters_dflt.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/virtex/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/virtex/include/bsp/opbintctrl.h diff --git a/bsps/powerpc/virtex/include/bsp.h b/bsps/powerpc/virtex/include/bsp.h new file mode 100644 index 0000000000..2f61ee2517 --- /dev/null +++ b/bsps/powerpc/virtex/include/bsp.h @@ -0,0 +1,84 @@ +/* bsp.h + * + * This include file contains all GEN405 board IO definitions. + * + * derived from helas403/include/bsp.h: + * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp + * Author: Thomas Doerfler + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef LIBBSP_POWERPC_VIRTEX_BSP_H +#define LIBBSP_POWERPC_VIRTEX_BSP_H + +#include + +#ifdef ASM +/* Definition of where to store registers in alignment handler */ +#define ALIGN_REGS 0x0140 + +#else +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN + +/* miscellaneous stuff assumed to exist */ +extern bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ + +/* Network Defines */ +#if 1 /* EB/doe changes */ +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#else +#include "xiltemac.h" +#define RTEMS_BSP_NETWORK_DRIVER_NAME XILTEMAC_DRIVER_PREFIX +#endif +struct rtems_bsdnet_ifconfig; +extern int xilTemac_driver_attach(struct rtems_bsdnet_ifconfig*, int ); +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH xilTemac_driver_attach + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif diff --git a/bsps/powerpc/virtex/include/bsp/irq.h b/bsps/powerpc/virtex/include/bsp/irq.h new file mode 100644 index 0000000000..1ce5b68b98 --- /dev/null +++ b/bsps/powerpc/virtex/include/bsp/irq.h @@ -0,0 +1,94 @@ +/*===============================================================*\ +| Project: RTEMS virtex BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares constants of the interrupt controller | +\*===============================================================*/ +#ifndef VIRTEX_IRQ_IRQ_H +#define VIRTEX_IRQ_IRQ_H + +#include +#include +#include + +/* + * the following definitions specify the indices used + * to interface the interrupt handler API + */ + +/* + * Peripheral IRQ handlers related definitions + */ +#define BSP_OPBINTC_PER_IRQ_NUMBER XPAR_INTC_MAX_NUM_INTR_INPUTS +#define BSP_OPBINTC_IRQ_LOWEST_OFFSET 0 +#define BSP_OPBINTC_IRQ_MAX_OFFSET (BSP_OPBINTC_IRQ_LOWEST_OFFSET\ + +BSP_OPBINTC_PER_IRQ_NUMBER-1) + +#define BSP_IS_OPBINTC_IRQ(irqnum) \ + (((irqnum) >= BSP_OPBINTC_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_OPBINTC_IRQ_MAX_OFFSET)) +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 3 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_OPBINTC_IRQ_MAX_OFFSET+1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ + +BSP_PROCESSOR_IRQ_NUMBER-1) + +#define BSP_IS_PROCESSOR_IRQ(irqnum) \ + (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) +#define BSP_LOWEST_OFFSET BSP_OPBINTC_IRQ_LOWEST_OFFSET +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET + +#define BSP_IS_VALID_IRQ(irqnum) \ + (BSP_IS_PROCESSOR_IRQ(irqnum) \ + || BSP_IS_OPBINTC_IRQ(irqnum)) + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX BSP_PROCESSOR_IRQ_MAX_OFFSET + +#ifndef ASM +#ifdef __cplusplus +extern "C" { +#endif + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ + typedef enum { + BSP_OPBINTC_IRQ_FIRST = BSP_OPBINTC_IRQ_LOWEST_OFFSET, + /* + * Note: for this BSP, the peripheral names are derived + * from the Xilinx parameter file + */ + BSP_OPBINTC_IRQ_LAST = BSP_OPBINTC_IRQ_MAX_OFFSET, + BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, + BSP_PIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, + BSP_CRIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 + } rtems_irq_symbolic_name; + +#define BSP_OPBINTC_XPAR(xname) (BSP_OPBINTC_IRQ_LOWEST_OFFSET+xname) + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ + +#endif /* VIRTEX_IRQ_IRQ_H */ diff --git a/bsps/powerpc/virtex/include/bsp/opbintctrl.h b/bsps/powerpc/virtex/include/bsp/opbintctrl.h new file mode 100644 index 0000000000..4ade0e48f8 --- /dev/null +++ b/bsps/powerpc/virtex/include/bsp/opbintctrl.h @@ -0,0 +1,75 @@ +/* opbintctrl.h + * + * This file contains definitions and declarations for the + * Xilinx Off Processor Bus (OPB) Interrupt Controller + * + * Author: Keith Robertson + * COPYRIGHT (c) 2005 by Linn Products Ltd, Scotland + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _INCLUDE_OPBINTCTRL_H +#define _INCLUDE_OPBINTCTRL_H + +#include +#include +#include +#include +#include +#include RTEMS_XPARAMETERS_H + +#define USE_GREG_INTERRUPTS + +#ifdef __cplusplus +extern "C" { +#endif + + +/* extern XIntc InterruptController; + */ + + +/* Maximum number of IRQs. Defined in vhdl model */ +#define OPB_INTC_IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS + +/* Width of INTC registers. Defined in vhdl model */ +#define OPB_INTC_REGISTER_WIDTH 32 + +/* Base Register address and register offsets. Defined in vhdl model */ +#define OPB_INTC_BASE XPAR_INTC_SINGLE_BASEADDR + + + + + +/* Interrupt Status Register */ +#define OPB_INTC_ISR 0x0 +/* Interrupt Pending Register (ISR && IER) */ +#define OPB_INTC_IPR 0x4 +/* Interrupt Enable Register */ +#define OPB_INTC_IER 0x8 +/* Interrupt Acknowledge Register */ +#define OPB_INTC_IAR 0xC +/* Set Interrupt Enable (same as read/mask/write to IER) */ +#define OPB_INTC_SIE 0x10 +/* Clear Interrupt Enable (same as read/mask/write to IER) */ +#define OPB_INTC_CIE 0x14 +/* Interrupt Vector Address (highest priority vector number from IPR) */ +#define OPB_INTC_IVR 0x18 +/* Master Enable Register */ +#define OPB_INTC_MER 0x1C + +/* Master Enable Register: Hardware Interrupt Enable */ +#define OPB_INTC_MER_HIE 0x2 + +/* Master Enable Register: Master IRQ Enable */ +#define OPB_INTC_MER_ME 0x1 + +#ifdef __cplusplus +} +#endif + +#endif /* _INCLUDE_OPBINTCTRL_H */ diff --git a/bsps/powerpc/virtex/include/tm27.h b/bsps/powerpc/virtex/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/virtex/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/powerpc/virtex/include/xiltemac.h b/bsps/powerpc/virtex/include/xiltemac.h new file mode 100644 index 0000000000..185b89bdc1 --- /dev/null +++ b/bsps/powerpc/virtex/include/xiltemac.h @@ -0,0 +1,375 @@ +/* + * Driver for plb inteface of the xilinx temac 3.00a + * + * Author: Keith Robertson + * Copyright (c) 2007 Linn Products Ltd, Scotland. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _XILINX_TEMAC_ +#define _XILINX_TEMAC_ +#include + + +#define XILTEMAC_DRIVER_PREFIX "xiltemac" + +#define DRIVER_PREFIX XILTEMAC_DRIVER_PREFIX + + +/** IPIF interrupt and reset registers + */ +#define XTE_DISR_OFFSET 0x00000000 /**< Device interrupt status */ +#define XTE_DIPR_OFFSET 0x00000004 /**< Device interrupt pending */ +#define XTE_DIER_OFFSET 0x00000008 /**< Device interrupt enable */ +#define XTE_DIIR_OFFSET 0x00000018 /**< Device interrupt ID */ +#define XTE_DGIE_OFFSET 0x0000001C /**< Device global interrupt enable */ +#define XTE_IPISR_OFFSET 0x00000020 /**< IP interrupt status */ +#define XTE_IPIER_OFFSET 0x00000028 /**< IP interrupt enable */ +#define XTE_DSR_OFFSET 0x00000040 /**< Device software reset (write) */ + +/** IPIF transmit fifo + */ +#define XTE_PFIFO_TX_BASE_OFFSET 0x00002000 /**< Packet FIFO Tx channel */ +#define XTE_PFIFO_TX_VACANCY_OFFSET 0x00002004 /**< Packet Fifo Tx Vacancy */ +#define XTE_PFIFO_TX_DATA_OFFSET 0x00002100 /**< IPIF Tx packet fifo port */ + +/** IPIF receive fifo + */ +#define XTE_PFIFO_RX_BASE_OFFSET 0x00002010 /**< Packet FIFO Rx channel */ +#define XTE_PFIFO_RX_VACANCY_OFFSET 0x00002014 /**< Packet Fifo Rx Vacancy */ +#define XTE_PFIFO_RX_DATA_OFFSET 0x00002200 /**< IPIF Rx packet fifo port */ + +/** IPIF fifo masks + */ +#define XTE_PFIFO_COUNT_MASK 0x00FFFFFF + +/** IPIF transmit and recieve DMA offsets + */ +#define XTE_DMA_SEND_OFFSET 0x00002300 /**< DMA Tx channel */ +#define XTE_DMA_RECV_OFFSET 0x00002340 /**< DMA Rx channel */ + +/** IPIF IPIC_TO_TEMAC Core Registers + */ +#define XTE_CR_OFFSET 0x00001000 /**< Control */ +#define XTE_TPLR_OFFSET 0x00001004 /**< Tx packet length (FIFO) */ +#define XTE_TSR_OFFSET 0x00001008 /**< Tx status (FIFO) */ +#define XTE_RPLR_OFFSET 0x0000100C /**< Rx packet length (FIFO) */ +#define XTE_RSR_OFFSET 0x00001010 /**< Receive status */ +#define XTE_IFGP_OFFSET 0x00001014 /**< Interframe gap */ +#define XTE_TPPR_OFFSET 0x00001018 /**< Tx pause packet */ + +/** TEMAC Core Registers + * These are registers defined within the device's hard core located in the + * processor block. They are accessed with the host interface. These registers + * are addressed offset by XTE_HOST_IPIF_OFFSET or by the DCR base address + * if so configured. + */ +#define XTE_HOST_IPIF_OFFSET 0x00003000 /**< Offset of host registers when + memory mapped into IPIF */ +#define XTE_ERXC0_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000200) /**< Rx configuration word 0 */ +#define XTE_ERXC1_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000240) /**< Rx configuration word 1 */ +#define XTE_ETXC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000280) /**< Tx configuration */ +#define XTE_EFCC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000002C0) /**< Flow control configuration */ +#define XTE_ECFG_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000300) /**< EMAC configuration */ +#define XTE_EGMIC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000320) /**< RGMII/SGMII configuration */ +#define XTE_EMC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000340) /**< Management configuration */ +#define XTE_EUAW0_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000380) /**< Unicast address word 0 */ +#define XTE_EUAW1_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000384) /**< Unicast address word 1 */ +#define XTE_EMAW0_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000388) /**< Multicast address word 0 */ +#define XTE_EMAW1_OFFSET (XTE_HOST_IPIF_OFFSET + 0x0000038C) /**< Multicast address word 1 */ +#define XTE_EAFM_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000390) /**< Promisciuous mode */ +#define XTE_EIRS_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003A0) /**< IRstatus */ +#define XTE_EIREN_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003A4) /**< IRenable */ +#define XTE_EMIID_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003B0) /**< MIIMwrData */ +#define XTE_EMIIC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003B4) /**< MiiMcnt */ + +/* Register masks. The following constants define bit locations of various + * control bits in the registers. Constants are not defined for those registers + * that have a single bit field representing all 32 bits. For further + * information on the meaning of the various bit masks, refer to the HW spec. + */ + +/** Interrupt status bits for top level interrupts + * These bits are associated with the XTE_DISR_OFFSET, XTE_DIPR_OFFSET, + * and XTE_DIER_OFFSET registers. + */ +#define XTE_DXR_SEND_FIFO_MASK 0x00000040 /**< Send FIFO channel */ +#define XTE_DXR_RECV_FIFO_MASK 0x00000020 /**< Receive FIFO channel */ +#define XTE_DXR_RECV_DMA_MASK 0x00000010 /**< Receive DMA channel */ +#define XTE_DXR_SEND_DMA_MASK 0x00000008 /**< Send DMA channel */ +#define XTE_DXR_CORE_MASK 0x00000004 /**< Core */ +#define XTE_DXR_DPTO_MASK 0x00000002 /**< Data phase timeout */ +#define XTE_DXR_TERR_MASK 0x00000001 /**< Transaction error */ + +/** Interrupt status bits for MAC interrupts + * These bits are associated with XTE_IPISR_OFFSET and XTE_IPIER_OFFSET + * registers. + */ +#define XTE_IPXR_XMIT_DONE_MASK 0x00000001 /**< Tx complete */ +#define XTE_IPXR_RECV_DONE_MASK 0x00000002 /**< Rx complete */ +#define XTE_IPXR_AUTO_NEG_MASK 0x00000004 /**< Auto negotiation complete */ +#define XTE_IPXR_RECV_REJECT_MASK 0x00000008 /**< Rx packet rejected */ +#define XTE_IPXR_XMIT_SFIFO_EMPTY_MASK 0x00000010 /**< Tx status fifo empty */ +#define XTE_IPXR_RECV_LFIFO_EMPTY_MASK 0x00000020 /**< Rx length fifo empty */ +#define XTE_IPXR_XMIT_LFIFO_FULL_MASK 0x00000040 /**< Tx length fifo full */ +#define XTE_IPXR_RECV_LFIFO_OVER_MASK 0x00000080 /**< Rx length fifo overrun + Note that this signal is + no longer asserted by HW + */ +#define XTE_IPXR_RECV_LFIFO_UNDER_MASK 0x00000100 /**< Rx length fifo underrun */ +#define XTE_IPXR_XMIT_SFIFO_OVER_MASK 0x00000200 /**< Tx status fifo overrun */ +#define XTE_IPXR_XMIT_SFIFO_UNDER_MASK 0x00000400 /**< Tx status fifo underrun */ +#define XTE_IPXR_XMIT_LFIFO_OVER_MASK 0x00000800 /**< Tx length fifo overrun */ +#define XTE_IPXR_XMIT_LFIFO_UNDER_MASK 0x00001000 /**< Tx length fifo underrun */ +#define XTE_IPXR_RECV_PFIFO_ABORT_MASK 0x00002000 /**< Rx packet rejected due to + full packet FIFO */ +#define XTE_IPXR_RECV_LFIFO_ABORT_MASK 0x00004000 /**< Rx packet rejected due to + full length FIFO */ + +#define XTE_IPXR_RECV_DROPPED_MASK \ + (XTE_IPXR_RECV_REJECT_MASK | \ + XTE_IPXR_RECV_PFIFO_ABORT_MASK | \ + XTE_IPXR_RECV_LFIFO_ABORT_MASK) /**< IPXR bits that indicate a dropped + receive frame */ +#define XTE_IPXR_XMIT_ERROR_MASK \ + (XTE_IPXR_XMIT_SFIFO_OVER_MASK | \ + XTE_IPXR_XMIT_SFIFO_UNDER_MASK | \ + XTE_IPXR_XMIT_LFIFO_OVER_MASK | \ + XTE_IPXR_XMIT_LFIFO_UNDER_MASK) /**< IPXR bits that indicate transmit + errors */ + +#define XTE_IPXR_RECV_ERROR_MASK \ + (XTE_IPXR_RECV_DROPPED_MASK | \ + XTE_IPXR_RECV_LFIFO_UNDER_MASK) /**< IPXR bits that indicate receive + errors */ + +#define XTE_IPXR_FIFO_FATAL_ERROR_MASK \ + (XTE_IPXR_XMIT_SFIFO_OVER_MASK | \ + XTE_IPXR_XMIT_SFIFO_UNDER_MASK | \ + XTE_IPXR_XMIT_LFIFO_OVER_MASK | \ + XTE_IPXR_XMIT_LFIFO_UNDER_MASK | \ + XTE_IPXR_RECV_LFIFO_UNDER_MASK) /**< IPXR bits that indicate errors with + one of the length or status FIFOs + that is fatal in nature. These bits + can only be cleared by a device + reset */ + +/** Software reset register (DSR) + */ +#define XTE_DSR_RESET_MASK 0x0000000A /**< Write this value to DSR to + reset entire core */ + + +/** Global interrupt enable register (DGIE) + */ +#define XTE_DGIE_ENABLE_MASK 0x80000000 /**< Write this value to DGIE to + enable interrupts from this + device */ + +/** Control Register (CR) + */ +#define XTE_CR_HTRST_MASK 0x00000008 /**< Reset hard temac */ +#define XTE_CR_BCREJ_MASK 0x00000004 /**< Disable broadcast address + filtering */ +#define XTE_CR_MCREJ_MASK 0x00000002 /**< Disable multicast address + filtering */ +#define XTE_CR_HDUPLEX_MASK 0x00000001 /**< Enable half duplex operation */ + + +/** Transmit Packet Length Register (TPLR) + */ +#define XTE_TPLR_TXPL_MASK 0x00003FFF /**< Tx packet length in bytes */ + + +/** Transmit Status Register (TSR) + */ +#define XTE_TSR_TXED_MASK 0x80000000 /**< Excess deferral error */ +#define XTE_TSR_PFIFOU_MASK 0x40000000 /**< Packet FIFO underrun */ +#define XTE_TSR_TXA_MASK 0x3E000000 /**< Transmission attempts */ +#define XTE_TSR_TXLC_MASK 0x01000000 /**< Late collision error */ +#define XTE_TSR_TPCF_MASK 0x00000001 /**< Transmit packet complete + flag */ + +#define XTE_TSR_ERROR_MASK \ + (XTE_TSR_TXED_MASK | \ + XTE_TSR_PFIFOU_MASK | \ + XTE_TSR_TXLC_MASK) /**< TSR bits that indicate an + error */ + + +/** Receive Packet Length Register (RPLR) + */ +#define XTE_RPLR_RXPL_MASK 0x00003FFF /**< Rx packet length in bytes */ + + +/** Receive Status Register (RSR) + */ +#define XTE_RSR_RPCF_MASK 0x00000001 /**< Receive packet complete + flag */ + +/** Interframe Gap Register (IFG) + */ +#define XTE_IFG_IFGD_MASK 0x000000FF /**< IFG delay */ + + +/** Transmit Pause Packet Register (TPPR) + */ +#define XTE_TPPR_TPPD_MASK 0x0000FFFF /**< Tx pause packet data */ + + +/** Receiver Configuration Word 1 (ERXC1) + */ +#define XTE_ERXC1_RXRST_MASK 0x80000000 /**< Receiver reset */ +#define XTE_ERXC1_RXJMBO_MASK 0x40000000 /**< Jumbo frame enable */ +#define XTE_ERXC1_RXFCS_MASK 0x20000000 /**< FCS not stripped */ +#define XTE_ERXC1_RXEN_MASK 0x10000000 /**< Receiver enable */ +#define XTE_ERXC1_RXVLAN_MASK 0x08000000 /**< VLAN enable */ +#define XTE_ERXC1_RXHD_MASK 0x04000000 /**< Half duplex */ +#define XTE_ERXC1_RXLT_MASK 0x02000000 /**< Length/type check disable */ +#define XTE_ERXC1_ERXC1_MASK 0x0000FFFF /**< Pause frame source address + bits [47:32]. Bits [31:0] + are stored in register + ERXC0 */ + + +/** Transmitter Configuration (ETXC) + */ +#define XTE_ETXC_TXRST_MASK 0x80000000 /**< Transmitter reset */ +#define XTE_ETXC_TXJMBO_MASK 0x40000000 /**< Jumbo frame enable */ +#define XTE_ETXC_TXFCS_MASK 0x20000000 /**< Generate FCS */ +#define XTE_ETXC_TXEN_MASK 0x10000000 /**< Transmitter enable */ +#define XTE_ETXC_TXVLAN_MASK 0x08000000 /**< VLAN enable */ +#define XTE_ETXC_TXHD_MASK 0x04000000 /**< Half duplex */ +#define XTE_ETXC_TXIFG_MASK 0x02000000 /**< IFG adjust enable */ + + +/** Flow Control Configuration (EFCC) + */ +#define XTE_EFCC_TXFLO_MASK 0x40000000 /**< Tx flow control enable */ +#define XTE_EFCC_RXFLO_MASK 0x20000000 /**< Rx flow control enable */ + + +/** EMAC Configuration (ECFG) + */ +#define XTE_ECFG_LINKSPD_MASK 0xC0000000 /**< Link speed */ +#define XTE_ECFG_RGMII_MASK 0x20000000 /**< RGMII mode enable */ +#define XTE_ECFG_SGMII_MASK 0x10000000 /**< SGMII mode enable */ +#define XTE_ECFG_1000BASEX_MASK 0x08000000 /**< 1000BaseX mode enable */ +#define XTE_ECFG_HOSTEN_MASK 0x04000000 /**< Host interface enable */ +#define XTE_ECFG_TX16BIT 0x02000000 /**< 16 bit Tx client enable */ +#define XTE_ECFG_RX16BIT 0x01000000 /**< 16 bit Rx client enable */ + +#define XTE_ECFG_LINKSPD_10 0x00000000 /**< XTE_ECFG_LINKSPD_MASK for + 10 Mbit */ +#define XTE_ECFG_LINKSPD_100 0x40000000 /**< XTE_ECFG_LINKSPD_MASK for + 100 Mbit */ +#define XTE_ECFG_LINKSPD_1000 0x80000000 /**< XTE_ECFG_LINKSPD_MASK for + 1000 Mbit */ + +/** EMAC RGMII/SGMII Configuration (EGMIC) + */ +#define XTE_EGMIC_RGLINKSPD_MASK 0xC0000000 /**< RGMII link speed */ +#define XTE_EGMIC_SGLINKSPD_MASK 0x0000000C /**< SGMII link speed */ +#define XTE_EGMIC_RGSTATUS_MASK 0x00000002 /**< RGMII link status */ +#define XTE_EGMIC_RGHALFDUPLEX_MASK 0x00000001 /**< RGMII half duplex */ + +#define XTE_EGMIC_RGLINKSPD_10 0x00000000 /**< XTE_EGMIC_RGLINKSPD_MASK + for 10 Mbit */ +#define XTE_EGMIC_RGLINKSPD_100 0x40000000 /**< XTE_EGMIC_RGLINKSPD_MASK + for 100 Mbit */ +#define XTE_EGMIC_RGLINKSPD_1000 0x80000000 /**< XTE_EGMIC_RGLINKSPD_MASK + for 1000 Mbit */ +#define XTE_EGMIC_SGLINKSPD_10 0x00000000 /**< XTE_SGMIC_RGLINKSPD_MASK + for 10 Mbit */ +#define XTE_EGMIC_SGLINKSPD_100 0x00000004 /**< XTE_SGMIC_RGLINKSPD_MASK + for 100 Mbit */ +#define XTE_EGMIC_SGLINKSPD_1000 0x00000008 /**< XTE_SGMIC_RGLINKSPD_MASK + for 1000 Mbit */ + +/** EMAC Management Configuration (EMC) + */ +#define XTE_EMC_MDIO_MASK 0x00000040 /**< MII management enable */ +#define XTE_EMC_CLK_DVD_MAX 0x3F /**< Maximum MDIO divisor */ + + +/** EMAC Unicast Address Register Word 1 (EUAW1) + */ +#define XTE_EUAW1_MASK 0x0000FFFF /**< Station address bits [47:32] + Station address bits [31:0] + are stored in register + EUAW0 */ + + +/** EMAC Multicast Address Register Word 1 (EMAW1) + */ +#define XTE_EMAW1_CAMRNW_MASK 0x00800000 /**< CAM read/write control */ +#define XTE_EMAW1_CAMADDR_MASK 0x00030000 /**< CAM address mask */ +#define XTE_EUAW1_MASK 0x0000FFFF /**< Multicast address bits [47:32] + Multicast address bits [31:0] + are stored in register + EMAW0 */ +#define XTE_EMAW1_CAMMADDR_SHIFT_MASK 16 /**< Number of bits to shift right + to align with + XTE_EMAW1_CAMADDR_MASK */ + + +/** EMAC Address Filter Mode (EAFM) + */ +#define XTE_EAFM_EPPRM_MASK 0x80000000 /**< Promiscuous mode enable */ + + +/** EMAC MII Management Write Data (EMIID) + */ +#define XTE_EMIID_MIIMWRDATA_MASK 0x0000FFFF /**< Data port */ + + +/** EMAC MII Management Control (EMIIC) + */ +#define XTE_EMIID_MIIMDECADDR_MASK 0x0000FFFF /**< Address port */ + + +struct XilTemacStats +{ + volatile uint32_t iInterrupts; + + volatile uint32_t iRxInterrupts; + volatile uint32_t iRxRejectedInterrupts; + volatile uint32_t iRxRejectedInvalidFrame; + volatile uint32_t iRxRejectedDataFifoFull; + volatile uint32_t iRxRejectedLengthFifoFull; + volatile uint32_t iRxMaxDrained; + volatile uint32_t iRxStrayEvents; + + volatile uint32_t iTxInterrupts; + volatile uint32_t iTxMaxDrained; +}; + +#define MAX_UNIT_BYTES 50 + +struct XilTemac +{ + struct arpcom iArpcom; + struct XilTemacStats iStats; + struct ifnet* iIfp; + + char iUnitName[MAX_UNIT_BYTES]; + + uint32_t iAddr; + rtems_event_set iIoEvent; + + int iIsrVector; + +#if PPC_HAS_CLASSIC_EXCEPTIONS + rtems_isr_entry iOldHandler; +#else + rtems_irq_connect_data iOldHandler; +#endif + int iIsPresent; +}; + + +#endif /* _XILINX_EMAC_*/ diff --git a/bsps/powerpc/virtex/include/xparameters_dflt.h b/bsps/powerpc/virtex/include/xparameters_dflt.h new file mode 100644 index 0000000000..b31cb26fe8 --- /dev/null +++ b/bsps/powerpc/virtex/include/xparameters_dflt.h @@ -0,0 +1,192 @@ +/******************************************************************* +* +* CAUTION: This file is automatically generated by libgen. +* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 +* DO NOT EDIT. +* +* Copyright (c) 2005 Xilinx, Inc. All rights reserved. +* +* Description: Driver parameters +* +*******************************************************************/ + +#define STDIN_BASEADDRESS 0x40600000 +#define STDOUT_BASEADDRESS 0x40600000 + +/******************************************************************/ + +/* Definitions for driver PLBARB */ +#define XPAR_XPLBARB_NUM_INSTANCES 1 + +/* Definitions for peripheral PLB */ +#define XPAR_PLB_BASEADDR 0x00000000 +#define XPAR_PLB_HIGHADDR 0x00000000 +#define XPAR_PLB_DEVICE_ID 0 +#define XPAR_PLB_PLB_NUM_MASTERS 3 + + +/******************************************************************/ + +/* Definitions for driver OPBARB */ +#define XPAR_XOPBARB_NUM_INSTANCES 1 + +/* Definitions for peripheral OPB */ +#define XPAR_OPB_BASEADDR 0xFFFFFFFF +#define XPAR_OPB_HIGHADDR 0x00000000 +#define XPAR_OPB_DEVICE_ID 0 +#define XPAR_OPB_NUM_MASTERS 1 + + +/******************************************************************/ + +/* Definitions for driver UARTLITE */ +#define XPAR_XUARTLITE_NUM_INSTANCES 1 + +/* Definitions for peripheral CONSOLE */ +#define XPAR_CONSOLE_BASEADDR 0x40600000 +#define XPAR_CONSOLE_HIGHADDR 0x4060FFFF +#define XPAR_CONSOLE_DEVICE_ID 0 +#define XPAR_CONSOLE_BAUDRATE 115200 +#define XPAR_CONSOLE_USE_PARITY 0 +#define XPAR_CONSOLE_ODD_PARITY 0 +#define XPAR_CONSOLE_DATA_BITS 8 + + +/******************************************************************/ + +/* Definitions for driver GPIO */ +#define XPAR_XGPIO_NUM_INSTANCES 3 + +/* Definitions for peripheral LEDS */ +#define XPAR_LEDS_BASEADDR 0x40000000 +#define XPAR_LEDS_HIGHADDR 0x4000FFFF +#define XPAR_LEDS_DEVICE_ID 0 +#define XPAR_LEDS_INTERRUPT_PRESENT 0 +#define XPAR_LEDS_IS_DUAL 0 + + +/* Definitions for peripheral PBLEDS */ +#define XPAR_PBLEDS_BASEADDR 0x40020000 +#define XPAR_PBLEDS_HIGHADDR 0x4002FFFF +#define XPAR_PBLEDS_DEVICE_ID 1 +#define XPAR_PBLEDS_INTERRUPT_PRESENT 0 +#define XPAR_PBLEDS_IS_DUAL 0 + + +/* Definitions for peripheral PUSHBUTTONS */ +#define XPAR_PUSHBUTTONS_BASEADDR 0x40040000 +#define XPAR_PUSHBUTTONS_HIGHADDR 0x4004FFFF +#define XPAR_PUSHBUTTONS_DEVICE_ID 2 +#define XPAR_PUSHBUTTONS_INTERRUPT_PRESENT 1 +#define XPAR_PUSHBUTTONS_IS_DUAL 0 + + +/******************************************************************/ + +/* Definitions for driver TMRCTR */ +#define XPAR_XTMRCTR_NUM_INSTANCES 1 + +/* Definitions for peripheral OPBTIMER */ +#define XPAR_OPBTIMER_BASEADDR 0x41C00000 +#define XPAR_OPBTIMER_HIGHADDR 0x41C0FFFF +#define XPAR_OPBTIMER_DEVICE_ID 0 + + +/******************************************************************/ + +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3 +#define XPAR_XINTC_HAS_IPR 1 +#define XPAR_XINTC_USE_DCR 0 +/* Definitions for driver INTC */ +#define XPAR_XINTC_NUM_INSTANCES 1 + +/* Definitions for peripheral INTC */ +#define XPAR_INTC_BASEADDR 0x41200000 +#define XPAR_INTC_HIGHADDR 0x4120FFFF +#define XPAR_INTC_DEVICE_ID 0 +#define XPAR_INTC_KIND_OF_INTR 0x00000000 + + +/******************************************************************/ + +#define XPAR_INTC_SINGLE_BASEADDR 0x41200000 +#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF +#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_INTC_DEVICE_ID +#define XPAR_OPBTIMER_INTERRUPT_MASK 0X000001 +#define XPAR_INTC_OPBTIMER_INTERRUPT_INTR 0 +#define XPAR_ETHERNET_IP2INTC_IRPT_MASK 0X000002 +#define XPAR_INTC_ETHERNET_IP2INTC_IRPT_INTR 1 +#define XPAR_PUSHBUTTONS_IP2INTC_IRPT_MASK 0X000004 +#define XPAR_INTC_PUSHBUTTONS_IP2INTC_IRPT_INTR 2 + +/******************************************************************/ + +/* Definitions for driver DDR */ +#define XPAR_XDDR_NUM_INSTANCES 1 + +/* Definitions for peripheral DDR_SDRAM_64MX32 */ +#define XPAR_DDR_SDRAM_64MX32_ECC_BASEADDR 0xFFFFFFFF +#define XPAR_DDR_SDRAM_64MX32_ECC_HIGHADDR 0x00000000 +#define XPAR_DDR_SDRAM_64MX32_DEVICE_ID 0 +#define XPAR_DDR_SDRAM_64MX32_INCLUDE_ECC_INTR 0 + + +/******************************************************************/ + +/* Definitions for peripheral DDR_SDRAM_64MX32 */ +#define XPAR_DDR_SDRAM_64MX32_MEM0_BASEADDR 0x00000000 +#define XPAR_DDR_SDRAM_64MX32_MEM0_HIGHADDR 0x03FFFFFF + +/******************************************************************/ + + +/* Definitions for peripheral HARD_TEMAC_0 */ +#define XPAR_HARD_TEMAC_0_PHY_TYPE 1 + + +/******************************************************************/ + +/* Definitions for driver TEMAC */ +#define XPAR_XTEMAC_NUM_INSTANCES 1 + +/* Definitions for peripheral ETHERNET */ +#define XPAR_ETHERNET_DEVICE_ID 0 +#define XPAR_ETHERNET_BASEADDR 0x81200000 +#define XPAR_ETHERNET_HIGHADDR 0x8120FFFF +#define XPAR_ETHERNET_RXFIFO_DEPTH 32768 +#define XPAR_ETHERNET_TXFIFO_DEPTH 32768 +#define XPAR_ETHERNET_MAC_FIFO_DEPTH 64 +#define XPAR_ETHERNET_DMA_TYPE 1 +#define XPAR_ETHERNET_TX_DRE_TYPE 0 +#define XPAR_ETHERNET_RX_DRE_TYPE 0 +#define XPAR_ETHERNET_INCLUDE_TX_CSUM 0 +#define XPAR_ETHERNET_INCLUDE_RX_CSUM 0 + + +/******************************************************************/ + + +/* Definitions for peripheral FLASH */ +#define XPAR_FLASH_NUM_BANKS_MEM 1 + + +/******************************************************************/ + +/* Definitions for peripheral FLASH */ +#define XPAR_FLASH_MEM0_BASEADDR 0x06000000 +#define XPAR_FLASH_MEM0_HIGHADDR 0x067FFFFF + +/******************************************************************/ + + +/* Definitions for peripheral PLB_BRAM_IF_CNTLR_1 */ +#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff8000 +#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff + + +/******************************************************************/ + +#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 + +/******************************************************************/ + diff --git a/bsps/powerpc/virtex4/headers.am b/bsps/powerpc/virtex4/headers.am new file mode 100644 index 0000000000..9ea2ab1635 --- /dev/null +++ b/bsps/powerpc/virtex4/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/virtex4/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/virtex4/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/virtex4/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/virtex4/include/bsp/mmu.h diff --git a/bsps/powerpc/virtex4/include/bsp.h b/bsps/powerpc/virtex4/include/bsp.h new file mode 100644 index 0000000000..91e7ddf4ab --- /dev/null +++ b/bsps/powerpc/virtex4/include/bsp.h @@ -0,0 +1,83 @@ +/* + * This include file contains all Virtex4 board IO definitions. + */ + +/* + * derived from helas403/include/bsp.h: + * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp + * Author: Thomas Doerfler + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef LIBBSP_POWERPC_VIRTEX4_BSP_H +#define LIBBSP_POWERPC_VIRTEX4_BSP_H + +#include + +/* + * confdefs.h overrides for this BSP: + * - Interrupt stack space is not minimum if defined. + */ +#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) + +#ifdef ASM +/* Definition of where to store registers in alignment handler */ +#define ALIGN_REGS 0x0140 + +#else +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* miscellaneous stuff assumed to exist */ +extern bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ + +extern rtems_configuration_table BSP_Configuration; /* owned by BSP */ +#endif /* ASM */ + +void BSP_ask_for_reset(void); + +/* + * Prototypes for BSP methods shared across file boundaries + */ +void zero_bss(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/virtex4/include/bsp/irq.h b/bsps/powerpc/virtex4/include/bsp/irq.h new file mode 100644 index 0000000000..45ef69adbf --- /dev/null +++ b/bsps/powerpc/virtex4/include/bsp/irq.h @@ -0,0 +1,79 @@ +/*===============================================================*\ +| Project: RTEMS virtex BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares constants of the interrupt controller | +\*===============================================================*/ +#ifndef VIRTEX4_IRQ_IRQ_H +#define VIRTEX4_IRQ_IRQ_H + +#include + +/* + * the following definitions specify the indices used + * to interface the interrupt handler API + */ + +/* + * Peripheral IRQ handlers related definitions + */ + /* Not supported at this level */ + +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 3 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET 0 +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ + +BSP_PROCESSOR_IRQ_NUMBER-1) + +#define BSP_IS_PROCESSOR_IRQ(irqnum) \ + (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) + +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) +#define BSP_LOWEST_OFFSET BSP_PROCESSOR_IRQ_LOWEST_OFFSET +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET + +#define BSP_IS_VALID_IRQ(irqnum) (BSP_IS_PROCESSOR_IRQ(irqnum)) + +#ifndef ASM +#ifdef __cplusplus +extern "C" { +#endif + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ + typedef enum { + BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, + BSP_PIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, + BSP_CRIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 + } rtems_irq_symbolic_name; + + extern rtems_irq_connect_data *BSP_rtems_irq_tbl; + void BSP_irqexc_on_fnc(const rtems_irq_connect_data *conn_data); + void BSP_irqexc_off_fnc(const rtems_irq_connect_data *unused); + void BSP_rtems_irq_mngt_init(unsigned cpuId); + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ + +#endif /* VIRTEX4_IRQ_IRQ_H */ diff --git a/bsps/powerpc/virtex4/include/bsp/mmu.h b/bsps/powerpc/virtex4/include/bsp/mmu.h new file mode 100644 index 0000000000..3e2710b95c --- /dev/null +++ b/bsps/powerpc/virtex4/include/bsp/mmu.h @@ -0,0 +1,269 @@ +#ifndef RTEMS_VIRTEX4_MMU_H +#define RTEMS_VIRTEX4_MMU_H +/** + * @file + * + * @ingroup Virtex4MMU + * + * @brief Routines to manipulate the PPC 405 MMU. + */ +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * and was transcribed for the PPC 405 by + * R. Claus , 2012, + * Stanford Linear Accelerator Center, Stanford University, + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup Virtex4MMU Virtex 4 - MMU Support + * + * @ingroup Virtex4 + * + * @brief MMU support. + * + * @{ + */ + +/* Some routines require or return a index 'key'. + */ +typedef int bsp_tlb_idx_t; + +/* Cache the relevant TLB entries so that we can make sure the user cannot + * create conflicting (overlapping) entries. Keep them public for informational + * purposes. + */ +typedef struct { + struct { + uint32_t pad:24; + uint32_t tid:8; /** Translation ID */ + } id; + struct { + uint32_t epn:22; /** Effective page number */ + uint32_t size:3; /** Page size */ + uint32_t v:1; /** Valid */ + uint32_t att:2; /** Little-endian, User-defined */ + uint32_t pad:4; + } hi; /** High word*/ + struct { + uint32_t rpn:22; /** Real page number */ + uint32_t perm:6; /** Execute enable, Write-enable, Zone select */ + uint32_t wimg:4; /** Write-through, Caching inhibited, Mem coherent, Guarded */ + } lo; /** Low word */ +} bsp_tlb_entry_t; + +#define NTLBS 64 + +extern bsp_tlb_entry_t* bsp_mmu_cache; + + +// These constants will have to be shifted right by 20 bits before +// being inserted the high word of the TLB. + +#define MMU_M_SIZE_1K (0x00000000U) +#define MMU_M_SIZE_4K (0x08000000U) +#define MMU_M_SIZE_16K (0x10000000U) +#define MMU_M_SIZE_64K (0x18000000U) +#define MMU_M_SIZE_256K (0x20000000U) +#define MMU_M_SIZE_1M (0x28000000U) +#define MMU_M_SIZE_4M (0x30000000U) +#define MMU_M_SIZE_16M (0x38000000U) +#define MMU_M_SIZE_MIN (MMU_M_SIZE_1K) +#define MMU_M_SIZE_MAX (MMU_M_SIZE_16M) +#define MMU_M_SIZE (0x38000000U) +#define MMU_V_SIZE (27) + +#define MMU_M_ATTR_LITTLE_ENDIAN (0x02000000U) +#define MMU_M_ATTR_USER0 (0x01000000U) +#define MMU_M_ATTR (0x03000000U) +#define MMU_V_ATTR (24) + +// These constants have the same bit positions they'll occupy +// in low word of the TLB. + +#define MMU_M_PERM_EXEC (0x00000200U) +#define MMU_M_PERM_DATA_WRITE (0x00000100U) +#define MMU_M_PERM_ZONE_SELECT (0x000000f0U) +#define MMU_M_PERM (0x000003f0U) +#define MMU_V_PERM (4) + +#define MMU_M_PROP_WRITE_THROUGH (0x00000008U) +#define MMU_M_PROP_UNCACHED (0x00000004U) +#define MMU_M_PROP_MEM_COHERENT (0x00000002U) +#define MMU_M_PROP_GUARDED (0x00000001U) +#define MMU_M_PROP (0x0000000fU) +#define MMU_V_PROP (0) + + +/* + * Dump (cleartext) content info from cached TLB entries + * to a file (stdout if f==NULL). + */ +void +bsp_mmu_dump_cache(FILE *f); + +/* Read a TLB entry from the hardware and store the settings in the + * bsp_mmu_cache[] structure. + * + * The routine can perform this operation quietly or + * print information to a file. + * + * 'key': TLB entry index. + * 'quiet': perform operation silently (no info printed) if nonzero. + * 'f': open FILE where to print information. May be NULL, in + * which case 'stdout' is used. + * + * RETURNS: + * 0: success; TLB entry is VALID + * +1: success but TLB entry is INVALID + * < 0: error (-1: invalid argument) + * (-2: driver not initialized) + */ +int +bsp_mmu_update(bsp_tlb_idx_t key, bool quiet, FILE *f); + +/* Initialize cache. Should be done only once although this is not enforced. + * + * RETURNS: zero on success, nonzero on error; in this case the driver will + * refuse to change TLB entries (other than disabling them). + */ +int +bsp_mmu_initialize(void); + +/* Find first free TLB entry by examining all entries' valid bit. The first + * entry without the valid bit set is returned. + * + * RETURNS: A free TLB entry number. -1 if no entry can be found. + */ +bsp_tlb_idx_t +bsp_mmu_find_first_free(void); + +/* Write a TLB entry (can also be used to disable an entry). + * + * The routine checks against the cached data in bsp_mmu_cache[] + * to prevent the user from generating overlapping entries. + * + * 'idx': TLB entry # to manipulate + * 'ea': Effective address (must be page aligned) + * 'pa': Physical address (must be page aligned) + * 'sz': Page size selector; page size is 1024 * 2^(2*sz) bytes. + * 'sz' may also be one of the following: + * - page size in bytes ( >= 1024 ); the selector + * value is then computed by this routine. + * However, 'sz' must be a valid page size + * or -1 will be returned. + * - a value < 0 to invalidate/disable the + * TLB entry. + * 'flgs': Page's little-endian & user-defined flags, permissions and attributes + * 'tid': Translation ID + * + * RETURNS: 0 on success, nonzero on error: + * + * >0: requested mapping would overlap with + * existing mapping in another entry. Return + * value gives conflicting entry + 1; i.e., + * if a value of 4 is returned then the request + * conflicts with existing mapping in entry 3. + * -1: invalid argument + * -3: driver not initialized (or initialization failed). + * <0: other error + */ +bsp_tlb_idx_t +bsp_mmu_write(bsp_tlb_idx_t idx, uint32_t ea, uint32_t pa, uint sz, + uint32_t flgs, uint32_t tid); + +/* Check if a ea/tid/sz mapping overlaps with an existing entry. + * + * 'ea': The Effective Address to match against + * 'sz': The 'logarithmic' size selector; the page size + * is 1024*2^(2*sz). + * 'tid': The TID to match against + * + * RETURNS: + * >= 0: index of TLB entry that already provides a mapping + * which overlaps within the ea range. + * -1: SUCCESS (no conflicting entry found) + * <=-2: ERROR (invalid input) + */ +bsp_tlb_idx_t +bsp_mmu_match(uint32_t ea, int sz, uint32_t tid); + +/* Find TLB index that maps 'ea/tid' combination + * + * 'ea': Effective address to match against + * 'tid': The TID to match against + * + * RETURNS: index 'key'; i.e., the index number. + * + * On error (no mapping) -1 is returned. + */ +bsp_tlb_idx_t +bsp_mmu_find(uint32_t ea, uint32_t tid); + +/* Mark TLB entry as invalid ('disabled'). + * + * 'key': TLB entry index. + * + * RETURNS: zero on success, nonzero on error (TLB unchanged). + * + * NOTE: If a TLB entry is disabled the associated + * entry in bsp_mmu_cache[] is also marked as disabled. + */ +int +bsp_mmu_invalidate(bsp_tlb_idx_t key); + +/** @} */ + +#ifdef __cplusplus +}; +#endif + +#endif diff --git a/bsps/powerpc/virtex4/include/tm27.h b/bsps/powerpc/virtex4/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/virtex4/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/powerpc/virtex5/headers.am b/bsps/powerpc/virtex5/headers.am new file mode 100644 index 0000000000..4a5dff7ff9 --- /dev/null +++ b/bsps/powerpc/virtex5/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/virtex5/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/virtex5/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/virtex5/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/virtex5/include/bsp/mmu.h diff --git a/bsps/powerpc/virtex5/include/bsp.h b/bsps/powerpc/virtex5/include/bsp.h new file mode 100644 index 0000000000..ee9f20058d --- /dev/null +++ b/bsps/powerpc/virtex5/include/bsp.h @@ -0,0 +1,107 @@ +/* @file + * + * This include file contains all GEN405 board IO definitions. + */ + +/* + * derived from helas403/include/bsp.h: + * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp + * Author: Thomas Doerfler + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef LIBBSP_POWERPC_VIRTEX5_BSP_H +#define LIBBSP_POWERPC_VIRTEX5_BSP_H + +#include + +/* + * confdefs.h overrides for this BSP: + * - Interrupt stack space is not minimum if defined. + */ +#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) + +#ifdef ASM +/* Definition of where to store registers in alignment handler */ +#define ALIGN_REGS 0x0140 + +#else +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* miscellaneous stuff assumed to exist */ +extern bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ + +/* + * Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * Processor Clock Frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; + +/* + * Macro used by shared MPC6xx timer driver + */ +#define BSP_Convert_decrementer( _value ) \ + ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) + +/* + * Interfaces to required Clock Driver support methods + */ +int BSP_disconnect_clock_handler(void); +int BSP_connect_clock_handler(void); + +/* + * Prototypes for BSP methods shared across file boundaries + */ +void zero_bss(void); + +#endif /* ASM */ + +void BSP_ask_for_reset(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/virtex5/include/bsp/irq.h b/bsps/powerpc/virtex5/include/bsp/irq.h new file mode 100644 index 0000000000..066090de7f --- /dev/null +++ b/bsps/powerpc/virtex5/include/bsp/irq.h @@ -0,0 +1,82 @@ +/*===============================================================*\ +| Project: RTEMS virtex BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares constants of the interrupt controller | +\*===============================================================*/ +#ifndef VIRTEX5_IRQ_IRQ_H +#define VIRTEX5_IRQ_IRQ_H + +#include + +/* + * the following definitions specify the indices used + * to interface the interrupt handler API + */ + +/* + * Peripheral IRQ handlers related definitions + */ + /* Not supported at this level */ + +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 3 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET 0 +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ + +BSP_PROCESSOR_IRQ_NUMBER-1) + +#define BSP_IS_PROCESSOR_IRQ(irqnum) \ + (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) + +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) +#define BSP_LOWEST_OFFSET BSP_PROCESSOR_IRQ_LOWEST_OFFSET +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET + +#define BSP_IS_VALID_IRQ(irqnum) (BSP_IS_PROCESSOR_IRQ(irqnum)) + +#ifndef ASM +#ifdef __cplusplus +extern "C" { +#endif + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ + typedef enum { + BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, + BSP_PIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, + BSP_CRIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 + } rtems_irq_symbolic_name; + + extern rtems_irq_connect_data *BSP_rtems_irq_tbl; + void BSP_irqexc_on_fnc(const rtems_irq_connect_data *conn_data); + void BSP_irqexc_off_fnc(const rtems_irq_connect_data *unused); + void BSP_rtems_irq_mngt_init(unsigned cpuId); + +#define BSP_DEC BSP_PIT +#define BSP_DECREMENTER BSP_PIT + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ + +#endif /* VIRTEX5_IRQ_IRQ_H */ diff --git a/bsps/powerpc/virtex5/include/bsp/mmu.h b/bsps/powerpc/virtex5/include/bsp/mmu.h new file mode 100644 index 0000000000..a3fb32b662 --- /dev/null +++ b/bsps/powerpc/virtex5/include/bsp/mmu.h @@ -0,0 +1,287 @@ +#ifndef RTEMS_VIRTEX5_MMU_H +#define RTEMS_VIRTEX5_MMU_H +/** + * @file + * + * @ingroup Virtex5MMU + * + * @brief Routines to manipulate the PPC 440 MMU. + */ +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann , 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * and was transcribed for the PPC 440 by + * R. Claus , 2012, + * Stanford Linear Accelerator Center, Stanford University, + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup Virtex5MMU Virtex 5 - MMU Support + * + * @ingroup Virtex5 + * + * @brief MMU support. + * + * @{ + */ + +/* Some routines require or return an index 'key'. + */ +typedef int bsp_tlb_idx_t; + +/* Cache the relevant TLB entries so that we can make sure the user cannot + * create conflicting (overlapping) entries. Keep them public for informational + * purposes. + */ +typedef struct { + struct { + uint32_t pad:24; + uint32_t tid:8; /** Translation ID */ + } id; + struct { + uint32_t epn:22; /** Effective page number */ + uint32_t v:1; /** Valid */ + uint32_t ts:1; /** Translation Address Space */ + uint32_t size:4; /** Page size */ + uint32_t tpar:4; /** Tag parity */ + } w0; + struct { + uint32_t rpn:22; /** The real (translated) page number. */ + uint32_t par1:2; /** For matching the TLB array parity */ + uint32_t pad:4; + uint32_t erpn:4; /** Extended Real Page Number */ + } w1; + struct { + uint32_t par2:2; /** Parity for TLB word 2 */ + uint32_t pad1:14; + uint32_t att:4; /** User-defined attributes */ + uint32_t wimge:5; /** Write-Through/Caching Inhibited/Memory Coherent/Guarded/Endian */ + uint32_t pad2:1; + uint32_t perm:6; /** User-State Executable/Writeable/Readable Supervisor-State Executable/Writeable/Readable */ + } w2; +} bsp_tlb_entry_t; + +#define NTLBS 64 + +extern bsp_tlb_entry_t* bsp_mmu_cache; + +// These constants will have to be shifted right by 20 bits before +// being inserted the high word of the TLB. + +#define MMU_M_SIZE_1K (0x00000000U) +#define MMU_M_SIZE_4K (0x08000000U) +#define MMU_M_SIZE_16K (0x10000000U) +#define MMU_M_SIZE_64K (0x18000000U) +#define MMU_M_SIZE_256K (0x20000000U) +#define MMU_M_SIZE_1M (0x28000000U) +#define MMU_M_SIZE_16M (0x38000000U) +#define MMU_M_SIZE_256M (0x48000000U) +#define MMU_M_SIZE_MIN (MMU_M_SIZE_1K) +#define MMU_M_SIZE_MAX (MMU_M_SIZE_256M) +#define MMU_M_SIZE (0x78000000U) +#define MMU_V_SIZE (27) + +// These constants have the same bit positions they'll occupy +// in low word of the TLB. + +#define MMU_M_ATTR_USER0 (0x00010000U) +#define MMU_M_ATTR_USER1 (0x00008000U) +#define MMU_M_ATTR_USER2 (0x00004000U) +#define MMU_M_ATTR_USER3 (0x00002000U) +#define MMU_M_ATTR (0x0001e000U) +#define MMU_V_ATTR (13) + +#define MMU_M_PROP_WRITE_THROUGH (0x00001000U) +#define MMU_M_PROP_UNCACHED (0x00000800U) +#define MMU_M_PROP_MEM_COHERENT (0x00000400U) +#define MMU_M_PROP_GUARDED (0x00000200U) +#define MMU_M_PROP_LITTLE_ENDIAN (0x00000100U) +#define MMU_M_PROP (0x00000f00U) +#define MMU_V_PROP (8) + +#define MMU_M_PERM_USER_EXEC (0x00000020U) +#define MMU_M_PERM_USER_WRITE (0x00000010U) +#define MMU_M_PERM_USER_READ (0x00000008U) +#define MMU_M_PERM_SUPER_EXEC (0x00000004U) +#define MMU_M_PERM_SUPER_WRITE (0x00000002U) +#define MMU_M_PERM_SUPER_READ (0x00000001U) +#define MMU_M_PERM (0x0000003fU) +#define MMU_V_PERM (0) + + +/* + * Dump (cleartext) content info from cached TLB entries + * to a file (stdout if f==NULL). + */ +void +bsp_mmu_dump_cache(FILE *f); + +/* Read a TLB entry from the hardware and store the settings in the + * bsp_mmu_cache[] structure. + * + * The routine can perform this operation quietly or + * print information to a file. + * + * 'key': TLB entry index. + * 'quiet': perform operation silently (no info printed) if nonzero. + * 'f': open FILE where to print information. May be NULL, in + * which case 'stdout' is used. + * + * RETURNS: + * 0: success; TLB entry is VALID + * +1: success but TLB entry is INVALID + * < 0: error (-1: invalid argument) + * (-2: driver not initialized) + */ +int +bsp_mmu_update(bsp_tlb_idx_t key, bool quiet, FILE *f); + +/* Initialize cache. Should be done only once although this is not enforced. + * + * RETURNS: zero on success, nonzero on error; in this case the driver will + * refuse to change TLB entries (other than disabling them). + */ +int +bsp_mmu_initialize(void); + +/* Find first free TLB entry by examining all entries' valid bit. The first + * entry without the valid bit set is returned. + * + * RETURNS: A free TLB entry number. -1 if no entry can be found. + */ +bsp_tlb_idx_t +bsp_mmu_find_first_free(void); + +/* Write a TLB entry (can also be used to disable an entry). + * + * The routine checks against the cached data in bsp_mmu_cache[] + * to prevent the user from generating overlapping entries. + * + * 'idx': TLB entry # to manipulate + * 'ea': Effective address (must be page aligned) + * 'pa': Physical address (must be page aligned) + * 'sz': Page size selector; page size is 1024 * 2^(2*sz) bytes. + * 'sz' may also be one of the following: + * - page size in bytes ( >= 1024 ); the selector + * value is then computed by this routine. + * However, 'sz' must be a valid page size + * or -1 will be returned. + * - a value < 0 to invalidate/disable the + * TLB entry. + * 'flgs': Page's User-defined flags, permissions and WIMGE page attributes + * 'tid': Translation ID + * 'ts': Translation Space + * 'erpn': Extended Real Page Number + * + * RETURNS: 0 on success, nonzero on error: + * + * >0: requested mapping would overlap with + * existing mapping in another entry. Return + * value gives conflicting entry + 1; i.e., + * if a value of 4 is returned then the request + * conflicts with existing mapping in entry 3. + * -1: invalid argument + * -3: driver not initialized (or initialization failed). + * <0: other error + */ +bsp_tlb_idx_t +bsp_mmu_write(bsp_tlb_idx_t idx, uint32_t ea, uint32_t pa, int sz, + uint32_t flgs, uint32_t tid, uint32_t ts, uint32_t erpn); + +/* Check if a ea/tid/ts/sz mapping overlaps with an existing entry. + * + * 'ea': The Effective Address to match against + * 'sz': The 'logarithmic' size selector; the page size + * is 1024*2^(2*sz). + * 'tid': Translation ID + * 'ts': Translation Space + * + * RETURNS: + * >= 0: index of TLB entry that already provides a mapping + * which overlaps within the ea range. + * -1: SUCCESS (no conflicting entry found) + * <=-2: ERROR (invalid input) + */ +bsp_tlb_idx_t +bsp_mmu_match(uint32_t ea, int sz, uint32_t tid, uint32_t ts); + +/* Find TLB index that maps 'ea/tid/ts' combination + * + * 'ea': Effective address to match against + * 'tid': Translation ID + * 'ts': Translation Space + * + * RETURNS: index 'key'; i.e., the index number. + * + * On error (no mapping) -1 is returned. + */ +bsp_tlb_idx_t +bsp_mmu_find(uint32_t ea, uint32_t tid, uint32_t ts); + +/* Mark TLB entry as invalid ('disabled'). + * + * 'key': TLB entry index. + * + * RETURNS: zero on success, nonzero on error (TLB unchanged). + * + * NOTE: If a TLB entry is disabled the associated + * entry in bsp_tlb_cache[] is also marked as disabled. + */ +int +bsp_mmu_invalidate(bsp_tlb_idx_t key); + +/** @} */ + +#ifdef __cplusplus +}; +#endif + +#endif diff --git a/bsps/powerpc/virtex5/include/tm27.h b/bsps/powerpc/virtex5/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/virtex5/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/riscv/headers.am b/bsps/riscv/headers.am new file mode 100644 index 0000000000..2fd6c8822e --- /dev/null +++ b/bsps/riscv/headers.am @@ -0,0 +1,5 @@ +## This file was generated by "./boostrap -H". + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/riscv/include/bsp/linker-symbols.h diff --git a/bsps/riscv/include/bsp/linker-symbols.h b/bsps/riscv/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..a4b03f527c --- /dev/null +++ b/bsps/riscv/include/bsp/linker-symbols.h @@ -0,0 +1,81 @@ +#ifndef LIBBSP_RISCV_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_RISCV_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup riscv_linker Linker Support + * + * @ingroup riscv_shared + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM +#define LINKER_SYMBOL(sym) extern char sym []; +#else +#define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_vector_begin) +LINKER_SYMBOL(bsp_section_vector_end) +LINKER_SYMBOL(bsp_section_vector_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_vector_table_begin) +LINKER_SYMBOL(bsp_vector_table_end) +LINKER_SYMBOL(bsp_vector_table_size) + +LINKER_SYMBOL(bsp_start_vector_table_begin) +LINKER_SYMBOL(bsp_start_vector_table_end) +LINKER_SYMBOL(bsp_start_vector_table_size) + +LINKER_SYMBOL(bsp_translation_table_base) +LINKER_SYMBOL(bsp_translation_table_end) + +LINKER_SYMBOL(_bsp_processor_count) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_RISCV_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/riscv/riscv_generic/headers.am b/bsps/riscv/riscv_generic/headers.am new file mode 100644 index 0000000000..6993fe8688 --- /dev/null +++ b/bsps/riscv/riscv_generic/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/riscv/riscv_generic/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/riscv/riscv_generic/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/riscv/riscv_generic/include/bsp/irq.h diff --git a/bsps/riscv/riscv_generic/include/bsp.h b/bsps/riscv/riscv_generic/include/bsp.h new file mode 100644 index 0000000000..79f359ac34 --- /dev/null +++ b/bsps/riscv/riscv_generic/include/bsp.h @@ -0,0 +1,73 @@ +/* + * + * Copyright (c) 2015 University of York. + * Hesham Almatary + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef LIBBSP_RISCV_GENERIC_H +#define LIBBSP_RISCV_GENERIC_H + +#include +#include +#include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup riscv_generic Register Definitions + * + * @ingroup riscv_generic + * + * @brief Shared register definitions for RISC-V systems. + * + * @{ + */ + +/** + * @name Register Macros + * + * @{ + */ + +#define REG(x) (*((volatile unsigned long *) (x))) +#define BIT(n) (1 << (n)) + +#define MTIME_MM 0x000000000200bff8 +#define MTIMECMP_MM 0x0000000002004000 + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_RISCV_GENERIC_H */ diff --git a/bsps/riscv/riscv_generic/include/bsp/irq.h b/bsps/riscv/riscv_generic/include/bsp/irq.h new file mode 100644 index 0000000000..d7ee45b378 --- /dev/null +++ b/bsps/riscv/riscv_generic/include/bsp/irq.h @@ -0,0 +1,49 @@ +/** + * @file + * + * @ingroup RISCV_IRQ + * + * @brief Interrupt definitions. + */ + +/* + * + * Copyright (c) 2015 University of York. + * Hesham Almatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef LIBBSP_GENERIC_RISCV_IRQ_H +#define LIBBSP_GENERIC_RISCV_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#define BSP_INTERRUPT_VECTOR_MIN 0x0 +#define BSP_INTERRUPT_VECTOR_MAX 0x24 + +#endif /* ASM */ +#endif /* LIBBSP_GENERIC_RISCV_IRQ_H */ diff --git a/bsps/riscv/riscv_generic/include/tm27.h b/bsps/riscv/riscv_generic/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/riscv/riscv_generic/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/sh/gensh1/headers.am b/bsps/sh/gensh1/headers.am new file mode 100644 index 0000000000..5118d283ce --- /dev/null +++ b/bsps/sh/gensh1/headers.am @@ -0,0 +1,17 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/sh/gensh1/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/sh/gensh1/include/tm27.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh1/include/rtems/score/iosh7032.h +include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh1/include/rtems/score/ispsh7032.h + +include_shdir = $(includedir)/sh +include_sh_HEADERS = +include_sh_HEADERS += ../../../../../../bsps/sh/gensh1/include/sh/sci.h +include_sh_HEADERS += ../../../../../../bsps/sh/gensh1/include/sh/sh7_pfc.h +include_sh_HEADERS += ../../../../../../bsps/sh/gensh1/include/sh/sh7_sci.h diff --git a/bsps/sh/gensh1/include/bsp.h b/bsps/sh/gensh1/include/bsp.h new file mode 100644 index 0000000000..2c0da4b074 --- /dev/null +++ b/bsps/sh/gensh1/include/bsp.h @@ -0,0 +1,86 @@ +/* + * generic sh1 + * + * This include file contains all board IO definitions. + */ + +/* + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SH_GENSH1_BSP_H +#define LIBBSP_SH_GENSH1_BSP_H + +#include +#include /* for tcflag_t */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* EDIT: To activate the sci driver, change the define below */ +#if 1 +#include +#define BSP_CONSOLE_DEVNAME "/dev/null" +#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVNULL_DRIVER_TABLE_ENTRY +#else +#include +#define BSP_CONSOLE_DEVNAME "/dev/sci0" +#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVSCI_DRIVER_TABLE_ENTRY +#endif + +/* Constants */ + +/* + * Defined in the linker script 'linkcmds' + */ + +extern void *CPU_Interrupt_stack_low; +extern void *CPU_Interrupt_stack_high; + +/* + * Device Driver Table Entries + */ + +/* + * We redefine CONSOLE_DRIVER_TABLE_ENTRY to redirect /dev/console + */ +#undef CONSOLE_DRIVER_TABLE_ENTRY +#define CONSOLE_DRIVER_TABLE_ENTRY \ + BSP_CONSOLE_DRIVER_TABLE_ENTRY, \ + { console_initialize, console_open, console_close, \ + console_read, console_write, console_control } + +/* + * BSP methods that cross file boundaries. + */ +void bsp_hw_init(void); + +extern int _sci_get_brparms( + tcflag_t cflag, + unsigned char *smr, + unsigned char *brr +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sh/gensh1/include/rtems/score/iosh7032.h b/bsps/sh/gensh1/include/rtems/score/iosh7032.h new file mode 100644 index 0000000000..3750024a64 --- /dev/null +++ b/bsps/sh/gensh1/include/rtems/score/iosh7032.h @@ -0,0 +1,220 @@ +/* + * This include file contains information pertaining to the Hitachi SH + * processor. + * + * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !! + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which + * contained no copyright notice. + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __IOSH7030_H +#define __IOSH7030_H + +/* + * After each line is explained whether the access is char short or long. + * The functions read/writeb, w, l, 8, 16, 32 can be found + * in exec/score/cpu/sh/sh_io.h + * + * 8 bit == char ( readb, writeb, read8, write8) + * 16 bit == short ( readw, writew, read16, write16 ) + * 32 bit == long ( readl, writel, read32, write32 ) + */ + +#define SCI0_SMR 0x05fffec0 /* char */ +#define SCI0_BRR 0x05fffec1 /* char */ +#define SCI0_SCR 0x05fffec2 /* char */ +#define SCI0_TDR 0x05fffec3 /* char */ +#define SCI0_SSR 0x05fffec4 /* char */ +#define SCI0_RDR 0x05fffec5 /* char */ + +#define SCI1_SMR 0x05fffec8 /* char */ +#define SCI1_BRR 0x05fffec9 /* char */ +#define SCI1_SCR 0x05fffeca /* char */ +#define SCI1_TDR 0x05fffecb /* char */ +#define SCI1_SSR 0x05fffecc /* char */ +#define SCI1_RDR 0x05fffecd /* char */ + + +#define ADDRAH 0x05fffee0 /* char */ +#define ADDRAL 0x05fffee1 /* char */ +#define ADDRBH 0x05fffee2 /* char */ +#define ADDRBL 0x05fffee3 /* char */ +#define ADDRCH 0x05fffee4 /* char */ +#define ADDRCL 0x05fffee5 /* char */ +#define ADDRDH 0x05fffee6 /* char */ +#define ADDRDL 0x05fffee7 /* char */ +#define AD_DRA 0x05fffee0 /* short */ +#define AD_DRB 0x05fffee2 /* short */ +#define AD_DRC 0x05fffee4 /* short */ +#define AD_DRD 0x05fffee6 /* short */ +#define ADCSR 0x05fffee8 /* char */ +#define ADCR 0x05fffee9 /* char */ + +/*ITU SHARED*/ +#define ITU_TSTR 0x05ffff00 /* char */ +#define ITU_TSNC 0x05ffff01 /* char */ +#define ITU_TMDR 0x05ffff02 /* char */ +#define ITU_TFCR 0x05ffff03 /* char */ + +/*ITU CHANNEL 0*/ +#define ITU_TCR0 0x05ffff04 /* char */ +#define ITU_TIOR0 0x05ffff05 /* char */ +#define ITU_TIER0 0x05ffff06 /* char */ +#define ITU_TSR0 0x05ffff07 /* char */ +#define ITU_TCNT0 0x05ffff08 /* short */ +#define ITU_GRA0 0x05ffff0a /* short */ +#define ITU_GRB0 0x05ffff0c /* short */ + + /*ITU CHANNEL 1*/ +#define ITU_TCR1 0x05ffff0E /* char */ +#define ITU_TIOR1 0x05ffff0F /* char */ +#define ITU_TIER1 0x05ffff10 /* char */ +#define ITU_TSR1 0x05ffff11 /* char */ +#define ITU_TCNT1 0x05ffff12 /* short */ +#define ITU_GRA1 0x05ffff14 /* short */ +#define ITU_GRB1 0x05ffff16 /* short */ + + + /*ITU CHANNEL 2*/ +#define ITU_TCR2 0x05ffff18 /* char */ +#define ITU_TIOR2 0x05ffff19 /* char */ +#define ITU_TIER2 0x05ffff1A /* char */ +#define ITU_TSR2 0x05ffff1B /* char */ +#define ITU_TCNT2 0x05ffff1C /* short */ +#define ITU_GRA2 0x05ffff1E /* short */ +#define ITU_GRB2 0x05ffff20 /* short */ + + /*ITU CHANNEL 3*/ +#define ITU_TCR3 0x05ffff22 /* char */ +#define ITU_TIOR3 0x05ffff23 /* char */ +#define ITU_TIER3 0x05ffff24 /* char */ +#define ITU_TSR3 0x05ffff25 /* char */ +#define ITU_TCNT3 0x05ffff26 /* short */ +#define ITU_GRA3 0x05ffff28 /* short */ +#define ITU_GRB3 0x05ffff2A /* short */ +#define ITU_BRA3 0x05ffff2C /* short */ +#define ITU_BRB3 0x05ffff2E /* short */ + + /*ITU CHANNELS 0-4 SHARED*/ +#define ITU_TOCR 0x05ffff31 /* char */ + + /*ITU CHANNEL 4*/ +#define ITU_TCR4 0x05ffff32 /* char */ +#define ITU_TIOR4 0x05ffff33 /* char */ +#define ITU_TIER4 0x05ffff34 /* char */ +#define ITU_TSR4 0x05ffff35 /* char */ +#define ITU_TCNT4 0x05ffff36 /* short */ +#define ITU_GRA4 0x05ffff38 /* short */ +#define ITU_GRB4 0x05ffff3A /* short */ +#define ITU_BRA4 0x05ffff3C /* short */ +#define ITU_BRB4 0x05ffff3E /* short */ + + /*DMAC CHANNELS 0-3 SHARED*/ +#define DMAOR 0x05ffff48 /* short */ + + /*DMAC CHANNEL 0*/ +#define DMA_SAR0 0x05ffff40 /* long */ +#define DMA_DAR0 0x05ffff44 /* long */ +#define DMA_TCR0 0x05ffff4a /* short */ +#define DMA_CHCR0 0x05ffff4e /* short */ + + /*DMAC CHANNEL 1*/ +#define DMA_SAR1 0x05ffff50 /* long */ +#define DMA_DAR1 0x05ffff54 /* long */ +#define DMA_TCR1 0x05fffF5a /* short */ +#define DMA_CHCR1 0x05ffff5e /* short */ + + /*DMAC CHANNEL 3*/ +#define DMA_SAR3 0x05ffff60 /* long */ +#define DMA_DAR3 0x05ffff64 /* long */ +#define DMA_TCR3 0x05fffF6a /* short */ +#define DMA_CHCR3 0x05ffff6e /* short */ + +/*DMAC CHANNEL 4*/ +#define DMA_SAR4 0x05ffff70 /* long */ +#define DMA_DAR4 0x05ffff74 /* long */ +#define DMA_TCR4 0x05fffF7a /* short */ +#define DMA_CHCR4 0x05ffff7e /* short */ + +/*INTC*/ +#define INTC_IPRA 0x05ffff84 /* short */ +#define INTC_IPRB 0x05ffff86 /* short */ +#define INTC_IPRC 0x05ffff88 /* short */ +#define INTC_IPRD 0x05ffff8A /* short */ +#define INTC_IPRE 0x05ffff8C /* short */ +#define INTC_ICR 0x05ffff8E /* short */ + +/*UBC*/ +#define UBC_BARH 0x05ffff90 /* short */ +#define UBC_BARL 0x05ffff92 /* short */ +#define UBC_BAMRH 0x05ffff94 /* short */ +#define UBC_BAMRL 0x05ffff96 /* short */ +#define UBC_BBR 0x05ffff98 /* short */ + +/*BSC*/ +#define BSC_BCR 0x05ffffA0 /* short */ +#define BSC_WCR1 0x05ffffA2 /* short */ +#define BSC_WCR2 0x05ffffA4 /* short */ +#define BSC_WCR3 0x05ffffA6 /* short */ +#define BSC_DCR 0x05ffffA8 /* short */ +#define BSC_PCR 0x05ffffAA /* short */ +#define BSC_RCR 0x05ffffAC /* short */ +#define BSC_RTCSR 0x05ffffAE /* short */ +#define BSC_RTCNT 0x05ffffB0 /* short */ +#define BSC_RTCOR 0x05ffffB2 /* short */ + +/*WDT*/ +#define WDT_TCSR 0x05ffffB8 /* char */ +#define WDT_TCNT 0x05ffffB9 /* char */ +#define WDT_RSTCSR 0x05ffffBB /* char */ + +/*POWER DOWN STATE*/ +#define PDT_SBYCR 0x05ffffBC /* char */ + +/*PORT A*/ +#define PADR 0x05ffffC0 /* short */ + +/*PORT B*/ +#define PBDR 0x05ffffC2 /* short */ + + /*PORT C*/ +#define PCDR 0x05ffffD0 /* short */ + +/*PFC*/ +#define PFC_PAIOR 0x05ffffC4 /* short */ +#define PFC_PBIOR 0x05ffffC6 /* short */ +#define PFC_PACR1 0x05ffffC8 /* short */ +#define PFC_PACR2 0x05ffffCA /* short */ +#define PFC_PBCR1 0x05ffffCC /* short */ +#define PFC_PBCR2 0x05ffffCE /* short */ +#define PFC_CASCR 0x05ffffEE /* short */ + +/*TPC*/ +#define TPC_TPMR 0x05ffffF0 /* short */ +#define TPC_TPCR 0x05ffffF1 /* short */ +#define TPC_NDERH 0x05ffffF2 /* short */ +#define TPC_NDERL 0x05ffffF3 /* short */ +#define TPC_NDRB 0x05ffffF4 /* char */ +#define TPC_NDRA 0x05ffffF5 /* char */ +#define TPC_NDRB1 0x05ffffF6 /* char */ +#define TPC_NDRA1 0x05ffffF7 /* char */ + +#endif diff --git a/bsps/sh/gensh1/include/rtems/score/ispsh7032.h b/bsps/sh/gensh1/include/rtems/score/ispsh7032.h new file mode 100644 index 0000000000..9c7cee8bd6 --- /dev/null +++ b/bsps/sh/gensh1/include/rtems/score/ispsh7032.h @@ -0,0 +1,162 @@ +/* + * This include file contains information pertaining to the Hitachi SH + * processor. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __CPU_ISPS_H +#define __CPU_ISPS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern void __ISR_Handler( uint32_t vector ); + + +/* + * interrupt vector table offsets + */ +#define NMI_ISP_V 11 +#define USB_ISP_V 12 +#define IRQ0_ISP_V 64 +#define IRQ1_ISP_V 65 +#define IRQ2_ISP_V 66 +#define IRQ3_ISP_V 67 +#define IRQ4_ISP_V 68 +#define IRQ5_ISP_V 69 +#define IRQ6_ISP_V 70 +#define IRQ7_ISP_V 71 +#define DMA0_ISP_V 72 +#define DMA1_ISP_V 74 +#define DMA2_ISP_V 76 +#define DMA3_ISP_V 78 + +#define IMIA0_ISP_V 80 +#define IMIB0_ISP_V 81 +#define OVI0_ISP_V 82 + +#define IMIA1_ISP_V 84 +#define IMIB1_ISP_V 85 +#define OVI1_ISP_V 86 + +#define IMIA2_ISP_V 88 +#define IMIB2_ISP_V 89 +#define OVI2_ISP_V 90 + +#define IMIA3_ISP_V 92 +#define IMIB3_ISP_V 93 +#define OVI3_ISP_V 94 + +#define IMIA4_ISP_V 96 +#define IMIB4_ISP_V 97 +#define OVI4_ISP_V 98 + +#define ERI0_ISP_V 100 +#define RXI0_ISP_V 101 +#define TXI0_ISP_V 102 +#define TEI0_ISP_V 103 + +#define ERI1_ISP_V 104 +#define RXI1_ISP_V 105 +#define TXI1_ISP_V 106 +#define TEI1_ISP_V 107 + +#define PRT_ISP_V 108 +#define ADU_ISP_V 109 +#define WDT_ISP_V 112 +#define DREF_ISP_V 113 + + +/* dummy ISP */ +extern void _dummy_isp( void ); + +/* Non Maskable Interrupt */ +extern void _nmi_isp( void ); + +/* User Break Controller */ +extern void _usb_isp( void ); + +/* External interrupts 0-7 */ +extern void _irq0_isp( void ); +extern void _irq1_isp( void ); +extern void _irq2_isp( void ); +extern void _irq3_isp( void ); +extern void _irq4_isp( void ); +extern void _irq5_isp( void ); +extern void _irq6_isp( void ); +extern void _irq7_isp( void ); + +/* DMA - Controller */ +extern void _dma0_isp( void ); +extern void _dma1_isp( void ); +extern void _dma2_isp( void ); +extern void _dma3_isp( void ); + +/* Interrupt Timer Unit */ +/* Timer 0 */ +extern void _imia0_isp( void ); +extern void _imib0_isp( void ); +extern void _ovi0_isp( void ); +/* Timer 1 */ +extern void _imia1_isp( void ); +extern void _imib1_isp( void ); +extern void _ovi1_isp( void ); +/* Timer 2 */ +extern void _imia2_isp( void ); +extern void _imib2_isp( void ); +extern void _ovi2_isp( void ); +/* Timer 3 */ +extern void _imia3_isp( void ); +extern void _imib3_isp( void ); +extern void _ovi3_isp( void ); +/* Timer 4 */ +extern void _imia4_isp( void ); +extern void _imib4_isp( void ); +extern void _ovi4_isp( void ); + +/* seriell interfaces */ +extern void _eri0_isp( void ); +extern void _rxi0_isp( void ); +extern void _txi0_isp( void ); +extern void _tei0_isp( void ); +extern void _eri1_isp( void ); +extern void _rxi1_isp( void ); +extern void _txi1_isp( void ); +extern void _tei1_isp( void ); + +/* Parity Control Unit of the Bus State Controllers */ +extern void _prt_isp( void ); + +/* ADC */ +extern void _adu_isp( void ); + +/* Watchdog Timer */ +extern void _wdt_isp( void ); + +/* DRAM refresh control unit of bus state controller */ +extern void _dref_isp( void ); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sh/gensh1/include/sh/sci.h b/bsps/sh/gensh1/include/sh/sci.h new file mode 100644 index 0000000000..5653afca3c --- /dev/null +++ b/bsps/sh/gensh1/include/sh/sci.h @@ -0,0 +1,82 @@ +/* + * Driver for the sh1 703x on-chip serial devices (sci) + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _sh_sci_h +#define _sh_sci_h + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Devices are set to 9600 bps, 8 databits, 1 stopbit, no + * parity and asynchronous mode by default. + * + * NOTE: + * The onboard serial devices of the SH do not support hardware + * handshake. + */ + +#define DEVSCI_DRIVER_TABLE_ENTRY \ + { sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \ + sh_sci_write, sh_sci_control } + +extern rtems_device_driver sh_sci_initialize( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_open( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_close( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_read( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_write( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_control( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sh/gensh1/include/sh/sh7_pfc.h b/bsps/sh/gensh1/include/sh/sh7_pfc.h new file mode 100644 index 0000000000..1045af6af8 --- /dev/null +++ b/bsps/sh/gensh1/include/sh/sh7_pfc.h @@ -0,0 +1,115 @@ +/* + * Bit values for the pin function controller of the Hitachi SH703X + * + * From Hitachi tutorials + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _sh7_pfc_h +#define _sh7_pfc_h + +#include + +/* + * Port B IO Register (PBIOR) + */ +#define PBIOR PFC_PBIOR +#define PB15IOR 0x8000 +#define PB14IOR 0x4000 +#define PB13IOR 0x2000 +#define PB12IOR 0x1000 +#define PB11IOR 0x0800 +#define PB10IOR 0x0400 +#define PB9IOR 0x0200 +#define PB8IOR 0x0100 +#define PB7IOR 0x0080 +#define PB6IOR 0x0040 +#define PB5IOR 0x0020 +#define PB4IOR 0x0010 +#define PB3IOR 0x0008 +#define PB2IOR 0x0004 +#define PB1IOR 0x0002 +#define PB0IOR 0x0001 + +/* + * Port B Control Register (PBCR1) + */ +#define PBCR1 PFC_PBCR1 +#define PB15MD1 0x8000 +#define PB15MD0 0x4000 +#define PB14MD1 0x2000 +#define PB14MD0 0x1000 +#define PB13MD1 0x0800 +#define PB13MD0 0x0400 +#define PB12MD1 0x0200 +#define PB12MD0 0x0100 +#define PB11MD1 0x0080 +#define PB11MD0 0x0040 +#define PB10MD1 0x0020 +#define PB10MD0 0x0010 +#define PB9MD1 0x0008 +#define PB9MD0 0x0004 +#define PB8MD1 0x0002 +#define PB8MD0 0x0001 + +#define PB15MD PB15MD1|PB14MD0 +#define PB14MD PB14MD1|PB14MD0 +#define PB13MD PB13MD1|PB13MD0 +#define PB12MD PB12MD1|PB12MD0 +#define PB11MD PB11MD1|PB11MD0 +#define PB10MD PB10MD1|PB10MD0 +#define PB9MD PB9MD1|PB9MD0 +#define PB8MD PB8MD1|PB8MD0 + +#define PB_TXD1 PB11MD1 +#define PB_RXD1 PB10MD1 +#define PB_TXD0 PB9MD1 +#define PB_RXD0 PB8MD1 + +/* + * Port B Control Register (PBCR2) + */ +#define PBCR2 PFC_PBCR2 +#define PB7MD1 0x8000 +#define PB7MD0 0x4000 +#define PB6MD1 0x2000 +#define PB6MD0 0x1000 +#define PB5MD1 0x0800 +#define PB5MD0 0x0400 +#define PB4MD1 0x0200 +#define PB4MD0 0x0100 +#define PB3MD1 0x0080 +#define PB3MD0 0x0040 +#define PB2MD1 0x0020 +#define PB2MD0 0x0010 +#define PB1MD1 0x0008 +#define PB1MD0 0x0004 +#define PB0MD1 0x0002 +#define PB0MD0 0x0001 + +#define PB7MD PB7MD1|PB7MD0 +#define PB6MD PB6MD1|PB6MD0 +#define PB5MD PB5MD1|PB5MD0 +#define PB4MD PB4MD1|PB4MD0 +#define PB3MD PB3MD1|PB3MD0 +#define PB2MD PB2MD1|PB2MD0 +#define PB1MD PB1MD1|PB1MD0 +#define PB0MD PB0MD1|PB0MD0 + +#endif /* _sh7_pfc_h */ diff --git a/bsps/sh/gensh1/include/sh/sh7_sci.h b/bsps/sh/gensh1/include/sh/sh7_sci.h new file mode 100644 index 0000000000..0b80a485d3 --- /dev/null +++ b/bsps/sh/gensh1/include/sh/sh7_sci.h @@ -0,0 +1,79 @@ +/* + * Bit values for the serial control registers of the Hitachi SH703X + * + * From Hitachi tutorials + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _sh7_sci_h +#define _sh7_sci_h + +#include + +/* + * Serial mode register bits + */ + +#define SCI_SYNC_MODE 0x80 +#define SCI_SEVEN_BIT_DATA 0x40 +#define SCI_PARITY_ON 0x20 +#define SCI_ODD_PARITY 0x10 +#define SCI_STOP_BITS_2 0x08 +#define SCI_ENABLE_MULTIP 0x04 +#define SCI_PHI_64 0x03 +#define SCI_PHI_16 0x02 +#define SCI_PHI_4 0x01 +#define SCI_PHI_0 0x00 + +/* + * Serial register offsets, relative to SCI0_SMR or SCI1_SMR + */ + +#define SCI_SMR 0x00 +#define SCI_BRR 0x01 +#define SCI_SCR 0x02 +#define SCI_TDR 0x03 +#define SCI_SSR 0x04 +#define SCI_RDR 0x05 + +/* + * Serial control register bits + */ +#define SCI_TIE 0x80 /* Transmit interrupt enable */ +#define SCI_RIE 0x40 /* Receive interrupt enable */ +#define SCI_TE 0x20 /* Transmit enable */ +#define SCI_RE 0x10 /* Receive enable */ +#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */ +#define SCI_TEIE 0x04 /* Transmit end interrupt enable */ +#define SCI_CKE1 0x02 /* Clock enable 1 */ +#define SCI_CKE0 0x01 /* Clock enable 0 */ + +/* + * Serial status register bits + */ +#define SCI_TDRE 0x80 /* Transmit data register empty */ +#define SCI_RDRF 0x40 /* Receive data register full */ +#define SCI_ORER 0x20 /* Overrun error */ +#define SCI_FER 0x10 /* Framing error */ +#define SCI_PER 0x08 /* Parity error */ +#define SCI_TEND 0x04 /* Transmit end */ +#define SCI_MPB 0x02 /* Multiprocessor bit */ +#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */ + +#endif /* _sh7_sci_h */ diff --git a/bsps/sh/gensh1/include/tm27.h b/bsps/sh/gensh1/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/sh/gensh1/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/sh/gensh2/headers.am b/bsps/sh/gensh2/headers.am new file mode 100644 index 0000000000..7062397ddf --- /dev/null +++ b/bsps/sh/gensh2/headers.am @@ -0,0 +1,19 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/sh/gensh2/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/sh/gensh2/include/tm27.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh2/include/rtems/score/iosh7045.h +include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh2/include/rtems/score/ispsh7045.h + +include_shdir = $(includedir)/sh +include_sh_HEADERS = +include_sh_HEADERS += ../../../../../../bsps/sh/gensh2/include/sh/io_types.h +include_sh_HEADERS += ../../../../../../bsps/sh/gensh2/include/sh/sci.h +include_sh_HEADERS += ../../../../../../bsps/sh/gensh2/include/sh/sci_termios.h +include_sh_HEADERS += ../../../../../../bsps/sh/gensh2/include/sh/sh7_pfc.h +include_sh_HEADERS += ../../../../../../bsps/sh/gensh2/include/sh/sh7_sci.h diff --git a/bsps/sh/gensh2/include/bsp.h b/bsps/sh/gensh2/include/bsp.h new file mode 100644 index 0000000000..221137ad81 --- /dev/null +++ b/bsps/sh/gensh2/include/bsp.h @@ -0,0 +1,85 @@ +/* + * generic sh2 + * + * This include file contains all board IO definitions. + */ + +/* + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Minor adaptations for sh2 by: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + */ + +#ifndef LIBBSP_SH_GENSH2_BSP_H +#define LIBBSP_SH_GENSH2_BSP_H + +#include + +#include +#include + +#include /* for tcflag_t */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if 1 +/* FIXME: + * These definitions will be no longer necessary if the old + * implementation of SCI driver will be droped + */ +#define BSP_CONSOLE_DEVNAME "/dev/sci0" +#define BSP_CONSOLE_MINOR_NUMBER ((rtems_device_minor_number) 0) +#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVSCI_DRIVER_TABLE_ENTRY +#define BSP_CONSOLE_DEVICE_TERMIOS_HANDLERS (sh_sci_get_termios_handlers(TRUE)) +#endif + +/* Constants */ + +/* + * Defined in the linker script 'linkcmds' + */ +extern void *CPU_Interrupt_stack_low; +extern void *CPU_Interrupt_stack_high; + +/* + * BSP methods that cross file boundaries. + */ +void bsp_hw_init(void); +extern int _sci_get_brparms( + tcflag_t cflag, + unsigned char *smr, + unsigned char *brr +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sh/gensh2/include/rtems/score/iosh7045.h b/bsps/sh/gensh2/include/rtems/score/iosh7045.h new file mode 100644 index 0000000000..db3252b72d --- /dev/null +++ b/bsps/sh/gensh2/include/rtems/score/iosh7045.h @@ -0,0 +1,322 @@ +/* + * This include file contains information pertaining to the Hitachi SH + * processor. + * + * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !! + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which + * contained no copyright notice. + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified to reflect on-chip registers for sh7045 processor, based on + * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which + * contained no copyright notice: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * August, 1999 + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + */ + +#ifndef __IOSH7045_H +#define __IOSH7045_H + +/* + * After each line is explained whether the access is char short or long. + * The functions read/writeb, w, l, 8, 16, 32 can be found + * in exec/score/cpu/sh/sh_io.h + * + * 8 bit == char ( readb, writeb, read8, write8) + * 16 bit == short ( readw, writew, read16, write16 ) + * 32 bit == long ( readl, writel, read32, write32 ) + * JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_ + * ENGINE_..Hardware_Manual; alignment access-restrictions may apply + */ + +#define REG_BASE 0xFFFF8000 + +/* SCI0 Registers */ +#define SCI_SMR0 (REG_BASE + 0x01a0) /*char: Serial mode ch 0 */ +#define SCI_BRR0 (REG_BASE + 0x01a1) /*char: Bit rate ch 0 */ +#define SCI_SCR0 (REG_BASE + 0x01a2) /*char: Serial control ch 0 */ +#define SCI_TDR0 (REG_BASE + 0x01a3) /*char: Transmit data ch 0 */ +#define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */ +#define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */ + +#define SCI0_SMR SCI_SMR0 + +/* SCI1 Registers */ +#define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */ +#define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */ +#define SCI_SCR1 (REG_BASE + 0x01b2) /* char: Serial control ch 1 */ +#define SCI_TDR1 (REG_BASE + 0x01b3) /* char: Transmit data ch 1 */ +#define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */ +#define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */ + +#define SCI1_SMR SCI_SMR1 + +/* ADI */ +/* High Speed A/D (Excluding A-Mask Part)*/ +#define ADDRA (REG_BASE + 0x03F0) /* short */ +#define ADDRB (REG_BASE + 0x03F2) /* short */ +#define ADDRC (REG_BASE + 0x03F4) /* short */ +#define ADDRD (REG_BASE + 0x03F6) /* short */ +#define ADDRE (REG_BASE + 0x03F8) /* short */ +#define ADDRF (REG_BASE + 0x03FA) /* short */ +#define ADDRG (REG_BASE + 0x03FC) /* short */ +#define ADDRH (REG_BASE + 0x03FE) /* short */ +#define ADCSR (REG_BASE + 0x03E0) /* char */ +#define ADCR (REG_BASE + 0x03E1) /* char */ + +/* Mid-Speed A/D (A-Mask part)*/ +#define ADDRA0 (REG_BASE + 0x0400) /* char, short */ +#define ADDRA0H (REG_BASE + 0x0400) /* char, short */ +#define ADDRA0L (REG_BASE + 0x0401) /* char */ +#define ADDRB0 (REG_BASE + 0x0402) /* char, short */ +#define ADDRB0H (REG_BASE + 0x0402) /* char, short */ +#define ADDRB0L (REG_BASE + 0x0403) /* char */ +#define ADDRC0 (REG_BASE + 0x0404) /* char, short */ +#define ADDRC0H (REG_BASE + 0x0404) /* char, short */ +#define ADDRC0L (REG_BASE + 0x0405) /* char */ +#define ADDRD0 (REG_BASE + 0x0406) /* char, short */ +#define ADDRD0H (REG_BASE + 0x0406) /* char, short */ +#define ADDRD0L (REG_BASE + 0x0407) /* char */ +#define ADCSR0 (REG_BASE + 0x0410) /* char */ +#define ADCR0 (REG_BASE + 0x0412) /* char */ +#define ADDRA1 (REG_BASE + 0x0408) /* char, short */ +#define ADDRA1H (REG_BASE + 0x0408) /* char, short */ +#define ADDRA1L (REG_BASE + 0x0409) /* char */ +#define ADDRB1 (REG_BASE + 0x040A) /* char, short */ +#define ADDRB1H (REG_BASE + 0x040A) /* char, short */ +#define ADDRB1L (REG_BASE + 0x040B) /* char */ +#define ADDRC1 (REG_BASE + 0x040C) /* char, short */ +#define ADDRC1H (REG_BASE + 0x040C) /* char, short */ +#define ADDRC1L (REG_BASE + 0x040D) /* char */ +#define ADDRD1 (REG_BASE + 0x040E) /* char, short */ +#define ADDRD1H (REG_BASE + 0x040E) /* char, short */ +#define ADDRD1L (REG_BASE + 0x040F) /* char */ +#define ADCSR1 (REG_BASE + 0x0411) /* char */ +#define ADCR1 (REG_BASE + 0x0413) /* char */ + +/*MTU SHARED*/ +#define MTU_TSTR (REG_BASE + 0x0240) /* char, short, word */ +#define MTU_TSYR (REG_BASE + 0x0241) /* char, short, word */ +#define MTU_ICSR (REG_BASE + 0x03C0) /* input lev. CSR */ +#define MTU_OCSR (REG_BASE + 0x03C0) /* output lev. CSR */ + +/*MTU CHANNEL 0*/ +#define MTU_TCR0 (REG_BASE + 0x0260) /* char, short, word */ +#define MTU_TMDR0 (REG_BASE + 0x0261) /* char, short, word */ +#define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word */ +#define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word */ +#define MTU_TIER0 (REG_BASE + 0x0264) /* char, short, word */ +#define MTU_TSR0 (REG_BASE + 0x0265) /* char, short, word */ +#define MTU_TCNT0 (REG_BASE + 0x0266) /* short, word */ +#define MTU_GR0A (REG_BASE + 0x0268) /* short, word */ +#define MTU_GR0B (REG_BASE + 0x026A) /* short, word */ +#define MTU_GR0C (REG_BASE + 0x026C) /* short, word */ +#define MTU_GR0D (REG_BASE + 0x026E) /* short, word */ + +/*MTU CHANNEL 1*/ +#define MTU_TCR1 (REG_BASE + 0x0280) /* char, short, word */ +#define MTU_TMDR1 (REG_BASE + 0x0281) /* char, short, word */ +#define MTU_TIOR1 (REG_BASE + 0x0282) /* char, short, word */ +#define MTU_TIER1 (REG_BASE + 0x0284) /* char, short, word */ +#define MTU_TSR1 (REG_BASE + 0x0285) /* char, short, word */ +#define MTU_TCNT1 (REG_BASE + 0x0286) /* short, word */ +#define MTU_GR1A (REG_BASE + 0x0288) /* short, word */ +#define MTU_GR1B (REG_BASE + 0x028A) /* short, word */ + +/*MTU CHANNEL 2*/ +#define MTU_TCR2 (REG_BASE + 0x02A0) /* char, short, word */ +#define MTU_TMDR2 (REG_BASE + 0x02A1) /* char, short, word */ +#define MTU_TIOR2 (REG_BASE + 0x02A2) /* char, short, word */ +#define MTU_TIER2 (REG_BASE + 0x02A4) /* char, short, word */ +#define MTU_TSR2 (REG_BASE + 0x02A5) /* char, short, word */ +#define MTU_TCNT2 (REG_BASE + 0x02A6) /* short, word */ +#define MTU_GR2A (REG_BASE + 0x02A8) /* short, word */ +#define MTU_GR2B (REG_BASE + 0x02AA) /* short, word */ + +/*MTU CHANNELS 3-4 SHARED*/ +#define MTU_TOER (REG_BASE + 0x020A) /* char, short, word */ +#define MTU_TOCR (REG_BASE + 0x020B) /* char, short, word */ +#define MTU_TGCR (REG_BASE + 0x020D) /* char, short, word */ +#define MTU_TCDR (REG_BASE + 0x0214) /* short, word */ +#define MTU_TDDR (REG_BASE + 0x0216) /* short, word */ +#define MTU_TCNTS (REG_BASE + 0x0220) /* short, word */ +#define MTU_TCBR (REG_BASE + 0x0222) /* short, word */ + +/*MTU CHANNEL 3*/ +#define MTU_TCR3 (REG_BASE + 0x0200) /* char, short, word */ +#define MTU_TMDR3 (REG_BASE + 0x0202) /* char, short, word */ +#define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word */ +#define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word */ +#define MTU_TIER3 (REG_BASE + 0x0208) /* char, short, word */ +#define MTU_TSR3 (REG_BASE + 0x022C) /* char, short, word */ +#define MTU_TCNT3 (REG_BASE + 0x0210) /* short, word */ +#define MTU_GR3A (REG_BASE + 0x0218) /* short, word */ +#define MTU_GR3B (REG_BASE + 0x021A) /* short, word */ +#define MTU_GR3C (REG_BASE + 0x0224) /* short, word */ +#define MTU_GR3D (REG_BASE + 0x0226) /* short, word */ + +/*MTU CHANNEL 4*/ +#define MTU_TCR4 (REG_BASE + 0x0201) /* char, short, word */ +#define MTU_TMDR4 (REG_BASE + 0x0203) /* char, short, word */ +#define MTU_TIOR4 (REG_BASE + 0x0206) /* char, short, word */ +#define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word */ +#define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word */ +#define MTU_TIER4 (REG_BASE + 0x0209) /* char, short, word */ +#define MTU_TSR4 (REG_BASE + 0x022D) /* char, short, word */ +#define MTU_TCNT4 (REG_BASE + 0x0212) /* short, word */ +#define MTU_GR4A (REG_BASE + 0x021C) /* short, word */ +#define MTU_GR4B (REG_BASE + 0x021E) /* short, word */ +#define MTU_GR4C (REG_BASE + 0x0228) /* short, word */ +#define MTU_GR4D (REG_BASE + 0x022A) /* short, word */ + +/*DMAC CHANNELS 0-3 SHARED*/ +#define DMAOR (REG_BASE + 0x06B0) /* short */ + +/*DMAC CHANNEL 0*/ +#define DMA_SAR0 (REG_BASE + 0x06C0) /* short, word */ +#define DMA_DAR0 (REG_BASE + 0x06C4) /* short, word */ +#define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */ +#define DMA_CHCR0 (REG_BASE + 0x06CC) /* short, word */ + +/*DMAC CHANNEL 1*/ +#define DMA_SAR1 (REG_BASE + 0x06D0) /* short, word */ +#define DMA_DAR1 (REG_BASE + 0x06D4) /* short, word */ +#define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */ +#define DMA_CHCR1 (REG_BASE + 0x06DC) /* short, word */ + +/*DMAC CHANNEL 3*/ +#define DMA_SAR3 (REG_BASE + 0x06E0) /* short, word */ +#define DMA_DAR3 (REG_BASE + 0x06E4) /* short, word */ +#define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */ +#define DMA_CHCR3 (REG_BASE + 0x06EC) /* short, word */ + +/*DMAC CHANNEL 4*/ +#define DMA_SAR4 (REG_BASE + 0x06F0) /* short, word */ +#define DMA_DAR4 (REG_BASE + 0x06F4) /* short, word */ +#define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */ +#define DMA_CHCR4 (REG_BASE + 0x06FC) /* short, word */ + +/*Data Transfer Controller*/ +#define DTC_DTEA (REG_BASE + 0x0700) /* char, short, word */ +#define DTC_DTEB (REG_BASE + 0x0701) /* char, short(?), word(?) */ +#define DTC_DTEC (REG_BASE + 0x0702) /* char, short(?), word(?) */ +#define DTC_DTED (REG_BASE + 0x0703) /* char, short(?), word(?) */ +#define DTC_DTEE (REG_BASE + 0x0704) /* char, short(?), word(?) */ +#define DTC_DTCSR (REG_BASE + 0x0706) /* char, short, word */ +#define DTC_DTBR (REG_BASE + 0x0708) /* short, word */ + +/*Cache Memory*/ +#define CAC_CCR (REG_BASE + 0x0740) /* char, short, word */ + +/*INTC*/ +#define INTC_IPRA (REG_BASE + 0x0348) /* char, short, word */ +#define INTC_IPRB (REG_BASE + 0x034A) /* char, short, word */ +#define INTC_IPRC (REG_BASE + 0x034C) /* char, short, word */ +#define INTC_IPRD (REG_BASE + 0x034E) /* char, short, word */ +#define INTC_IPRE (REG_BASE + 0x0350) /* char, short, word */ +#define INTC_IPRF (REG_BASE + 0x0352) /* char, short, word */ +#define INTC_IPRG (REG_BASE + 0x0354) /* char, short, word */ +#define INTC_IPRH (REG_BASE + 0x0356) /* char, short, word */ +#define INTC_ICR (REG_BASE + 0x0358) /* char, short, word */ +#define INTC_ISR (REG_BASE + 0x035A) /* char, short, word */ + +/*Flash (F-ZTAT)*/ +#define FL_FLMCR1 (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */ +#define FL_FLMCR2 (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */ +#define FL_EBR1 (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */ +#define FL_EBR2 (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */ +#define FL_RAMER (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */ + +/*UBC*/ +#define UBC_BARH (REG_BASE + 0x0600) /* char, short, word */ +#define UBC_BARL (REG_BASE + 0x0602) /* char, short, word */ +#define UBC_BAMRH (REG_BASE + 0x0604) /* char, short, word */ +#define UBC_BAMRL (REG_BASE + 0x0606) /* char, short, word */ +#define UBC_BBR (REG_BASE + 0x0608) /* char, short, word */ +/*BSC*/ +#define BSC_BCR1 (REG_BASE + 0x0620) /* short */ +#define BSC_BCR2 (REG_BASE + 0x0622) /* short */ +#define BSC_WCR1 (REG_BASE + 0x0624) /* short */ +#define BSC_WCR2 (REG_BASE + 0x0626) /* short */ +#define BSC_DCR (REG_BASE + 0x062A) /* short */ +#define BSC_RTCSR (REG_BASE + 0x062C) /* short */ +#define BSC_RTCNT (REG_BASE + 0x062E) /* short */ +#define BSC_RTCOR (REG_BASE + 0x0630) /* short */ + +/*WDT*/ +#define WDT_R_TCSR (REG_BASE + 0x0610) /* rd: char */ +#define WDT_R_TCNT (REG_BASE + 0x0611) /* rd: char */ +#define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */ +#define WDT_W_TCSR (REG_BASE + 0x0610) /* wrt: short */ +#define WDT_W_TCNT (REG_BASE + 0x0610) /* wrt: short */ +#define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */ + +/*POWER DOWN STATE*/ +#define PDT_SBYCR (REG_BASE + 0x0614) /* char */ + +/* Port I/O Control Registers */ +#define IO_PADRH (REG_BASE + 0x0380) /* Port A Data Register */ +#define IO_PADRL (REG_BASE + 0x0382) /* Port A Data Register */ +#define IO_PBDR (REG_BASE + 0x0390) /* Port B Data Register */ +#define IO_PCDR (REG_BASE + 0x0392) /* Port C Data Register */ +#define IO_PDDRH (REG_BASE + 0x03A0) /* Port D Data Register */ +#define IO_PDDRL (REG_BASE + 0x03A2) /* Port D Data Register */ +#define IO_PEDR (REG_BASE + 0x03B0) /* Port E Data Register */ +#define IO_PFDR (REG_BASE + 0x03B2) /* Port F Data Register */ + +/*Pin Function Control Register*/ +#define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */ +#define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */ +#define PFC_PACRH (REG_BASE + 0x0388) /* Port A Ctr. Reg. H */ +#define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */ +#define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */ +#define PFC_PBIOR (REG_BASE + 0x0394) /* Port B I/O Register */ +#define PFC_PBCR1 (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */ +#define PFC_PBCR2 (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */ +#define PFC_PCIOR (REG_BASE + 0x0396) /* Port C I/O Register */ +#define PFC_PCCR (REG_BASE + 0x039C) /* Port C Ctr. Reg. */ +#define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */ +#define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */ +#define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */ +#define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */ +#define PFC_PDCRL (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L */ +#define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */ +#define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */ +#define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */ +#define PFC_IFCR (REG_BASE + 0x03C8) /* short */ + +/*Compare/Match Timer*/ +#define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */ +#define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */ +#define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */ +#define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */ +#define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */ +#define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */ +#define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */ + +#endif diff --git a/bsps/sh/gensh2/include/rtems/score/ispsh7045.h b/bsps/sh/gensh2/include/rtems/score/ispsh7045.h new file mode 100644 index 0000000000..fb9f5297ae --- /dev/null +++ b/bsps/sh/gensh2/include/rtems/score/ispsh7045.h @@ -0,0 +1,208 @@ +/* + * This include file contains information pertaining to the Hitachi SH + * processor. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified to reflect isp entries for sh7045 processor: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + */ + +#ifndef __CPU_ISPS_H +#define __CPU_ISPS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern void __ISR_Handler( uint32_t vector ); + + +/* + * interrupt vector table offsets + */ +#define NMI_ISP_V 11 +#define USB_ISP_V 12 +#define IRQ0_ISP_V 64 +#define IRQ1_ISP_V 65 +#define IRQ2_ISP_V 66 +#define IRQ3_ISP_V 67 +#define IRQ4_ISP_V 68 +#define IRQ5_ISP_V 69 +#define IRQ6_ISP_V 70 +#define IRQ7_ISP_V 71 +#define DMA0_ISP_V 72 +#define DMA1_ISP_V 76 +#define DMA2_ISP_V 80 +#define DMA3_ISP_V 84 + +#define MTUA0_ISP_V 88 +#define MTUB0_ISP_V 89 +#define MTUC0_ISP_V 90 +#define MTUD0_ISP_V 91 +#define MTUV0_ISP_V 92 + +#define MTUA1_ISP_V 96 +#define MTUB1_ISP_V 97 +#define MTUV1_ISP_V 100 +#define MTUU1_ISP_V 101 + +#define MTUA2_ISP_V 104 +#define MTUB2_ISP_V 105 +#define MTUV2_ISP_V 108 +#define MTUU2_ISP_V 109 + +#define MTUA3_ISP_V 112 +#define MTUB3_ISP_V 113 +#define MTUC3_ISP_V 114 +#define MTUD3_ISP_V 115 +#define MTUV3_ISP_V 116 + +#define MTUA4_ISP_V 120 +#define MTUB4_ISP_V 121 +#define MTUC4_ISP_V 122 +#define MTUD4_ISP_V 123 +#define MTUV4_ISP_V 124 + +#define ERI0_ISP_V 128 +#define RXI0_ISP_V 129 +#define TXI0_ISP_V 130 +#define TEI0_ISP_V 131 + +#define ERI1_ISP_V 132 +#define RXI1_ISP_V 133 +#define TXI1_ISP_V 134 +#define TEI1_ISP_V 135 + +#define ADI0_ISP_V 136 +#define ADI1_ISP_V 137 +#define DTC_ISP_V 140 /* Data Transfer Controller */ +#define CMT0_ISP_V 144 /* Compare Match Timer */ +#define CMT1_ISP_V 148 +#define WDT_ISP_V 152 /* Wtachdog Timer */ +#define CMI_ISP_V 153 /* BSC RAS interrupt */ +#define OEI_ISP_V 156 /* I/O Port */ +#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */ +#if 0 +#define PRT_ISP_V /* parity error - no equivalent */ +#endif + +/* dummy ISP */ +extern void _dummy_isp( void ); + +/* Non Maskable Interrupt */ +extern void _nmi_isp( void ); + +/* User Break Controller */ +extern void _usb_isp( void ); + +/* External interrupts 0-7 */ +extern void _irq0_isp( void ); +extern void _irq1_isp( void ); +extern void _irq2_isp( void ); +extern void _irq3_isp( void ); +extern void _irq4_isp( void ); +extern void _irq5_isp( void ); +extern void _irq6_isp( void ); +extern void _irq7_isp( void ); + +/* DMA - Controller */ +extern void _dma0_isp( void ); +extern void _dma1_isp( void ); +extern void _dma2_isp( void ); +extern void _dma3_isp( void ); + +/* Interrupt Timer Unit */ +/* Timer 0 */ +extern void _mtua0_isp( void ); +extern void _mtub0_isp( void ); +extern void _mtuc0_isp( void ); +extern void _mtud0_isp( void ); +extern void _mtuv0_isp( void ); +/* Timer 1 */ +extern void _mtua1_isp( void ); +extern void _mtub1_isp( void ); +extern void _mtuv1_isp( void ); +extern void _mtuu1_isp( void ); +/* Timer 2 */ +extern void _mtua2_isp( void ); +extern void _mtub2_isp( void ); +extern void _mtuv2_isp( void ); +extern void _mtuu2_isp( void ); +/* Timer 3 */ +extern void _mtua3_isp( void ); +extern void _mtub3_isp( void ); +extern void _mtuc3_isp( void ); +extern void _mtud3_isp( void ); +extern void _mtuv3_isp( void ); +/* Timer 4 */ +extern void _mtua4_isp( void ); +extern void _mtub4_isp( void ); +extern void _mtuc4_isp( void ); +extern void _mtud4_isp( void ); +extern void _mtuv4_isp( void ); + +/* serial interfaces */ +extern void _eri0_isp( void ); +extern void _rxi0_isp( void ); +extern void _txi0_isp( void ); +extern void _tei0_isp( void ); +extern void _eri1_isp( void ); +extern void _rxi1_isp( void ); +extern void _txi1_isp( void ); +extern void _tei1_isp( void ); + +/* ADC */ +extern void _adi0_isp( void ); +extern void _adi1_isp( void ); + +/* Data Transfer Controller */ +extern void _dtci_isp( void ); + +/* Compare Match Timer */ +extern void _cmt0_isp( void ); +extern void _cmt1_isp( void ); + +/* Watchdog Timer */ +extern void _wdt_isp( void ); + +/* DRAM refresh control unit of bus state controller */ +extern void _bsc_isp( void ); + +/* I/O Port */ +extern void _oei_isp( void ); + +/* Parity Control Unit of the Bus State Controllers */ +/* extern void _prt_isp( void ); */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sh/gensh2/include/sh/io_types.h b/bsps/sh/gensh2/include/sh/io_types.h new file mode 100644 index 0000000000..1dab885672 --- /dev/null +++ b/bsps/sh/gensh2/include/sh/io_types.h @@ -0,0 +1,84 @@ +/************************************************************************ + * + * Data types and constants for Hitachi SH704X on-chip peripherals + * + * Author: John M.Mills (jmills@tga.com) + * + * COPYRIGHT (c) 1999, TGA Technologies, Norcross, GA, USA + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * This file may be distributed as part of the RTEMS software item. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * + ************************************************************************/ + +#ifndef _sh_io_types_h +#define _sh_io_types_h + +#include +#include + +typedef enum {SCI0, SCI1} portNo; +typedef enum {eight, seven} dataBits; +typedef enum {one, two} stopBits; +typedef enum {even, odd} parity; + +typedef struct { + portNo line; + int speed_ix; + dataBits dBits; + int parEn; + parity par; + int mulPro; + stopBits sBits; +} sci_setup_t; + +typedef union{ + unsigned char Reg; /* By Register */ + struct { /* By Field */ + unsigned char Sync :1; /* Async/Sync */ + unsigned char DBts :1; /* Char.Length */ + unsigned char ParEn :1; /* Parity En.*/ + unsigned char Odd :1; /* Even/Odd */ + unsigned char SBts :1; /* No.Stop Bits */ + unsigned char MulP :1; /* Multi-Proc. */ + unsigned char Dvsr :2; /* Clock Sel. */ + } Fld; +} sci_smr_t; + +typedef union { + unsigned char Reg; /* By Register */ + struct { /* By Field */ + unsigned char TIE :1; /* Tx.Int.En. */ + unsigned char RIE :1; /* Rx.Int.En. */ + unsigned char TE :1; /* Tx.En. */ + unsigned char RE :1; /* Rx.En. */ + unsigned char MPIE:1; /* Mult.Pro.Int.En. */ + unsigned char TEIE:1; /* Tx.End Int.En. */ + unsigned char CkSrc :2; /* Clock Src. */ + } Fld; +} sci_scr_t; + +typedef struct { + unsigned char n ; + unsigned char N ; +} sci_bitrate_t; + +#endif /* _sh_io_types_h */ diff --git a/bsps/sh/gensh2/include/sh/sci.h b/bsps/sh/gensh2/include/sh/sci.h new file mode 100644 index 0000000000..dc34371d48 --- /dev/null +++ b/bsps/sh/gensh2/include/sh/sci.h @@ -0,0 +1,89 @@ +/* + * Driver for the sh2 704x on-chip serial devices (sci) + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _sh_sci_h +#define _sh_sci_h + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Devices are set to 9600 bps, 8 databits, 1 stopbit, no + * parity and asynchronous mode by default. + * + * NOTE: + * The onboard serial devices of the SH do not support hardware + * handshake. + */ + +#define DEVSCI_DRIVER_TABLE_ENTRY \ + { sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \ + sh_sci_write, sh_sci_control } + +extern rtems_device_driver sh_sci_initialize( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_open( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_close( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_read( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_write( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_control( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern const rtems_termios_callbacks * sh_sci_get_termios_handlers( + bool poll +); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sh/gensh2/include/sh/sci_termios.h b/bsps/sh/gensh2/include/sh/sci_termios.h new file mode 100644 index 0000000000..63750c9461 --- /dev/null +++ b/bsps/sh/gensh2/include/sh/sci_termios.h @@ -0,0 +1,65 @@ +/* + * COPYRIGHT (c) 1989-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _SH_SCI_TERMIOS_H_ +#define _SH_SCI_TERMIOS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + + +int sh_sci_set_attributes( + int minor, + const struct termios *t +); + +void sh_sci_initialize_interrupts(int minor); + +void sh_sci_init(int minor); + +ssize_t sh_sci_write_support_int( + int minor, + const char *buf, + size_t len +); + +ssize_t sh_sci_write_support_polled( + int minor, + const char *buf, + size_t len +); + +void sh_sci_write_polled( + int minor, + char c +); + +int sh_sci_inbyte_nonblocking_polled(int minor); + + +int sh_sci_first_open( + int major, + int minor, + void *arg +); + +int sh_sci_last_close( + int major, + int minor, + void *arg +); + +#ifdef __cplusplus +} +#endif + + +#endif /* _SH_SCI_TERMIOS_H_ */ diff --git a/bsps/sh/gensh2/include/sh/sh7_pfc.h b/bsps/sh/gensh2/include/sh/sh7_pfc.h new file mode 100644 index 0000000000..b56433a9e2 --- /dev/null +++ b/bsps/sh/gensh2/include/sh/sh7_pfc.h @@ -0,0 +1,202 @@ +/* + * Bit values for the pin function controller of the Hitachi SH704x + * + * From Hitachi tutorials + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _sh7_pfc_h +#define _sh7_pfc_h + +#include + +/* + * Port A IO Registers (PAIORH, PAIORL) + * 1 => OUTPUT + * 0 => INPUT + */ +#define PAIORH PFC_PAIORH +#define PAIORL PFC_PAIORL + +/* PAIORH */ +#define PA23IOR 0x0080 +#define PA22IOR 0x0040 +#define PA21IOR 0x0020 +#define PA20IOR 0x0010 +#define PA19IOR 0x0008 +#define PA18IOR 0x0004 +#define PA17IOR 0x0002 +#define PA16IOR 0x0001 + +/* PAIORL */ +#define PA15IOR 0x8000 +#define PA14IOR 0x4000 +#define PA13IOR 0x2000 +#define PA12IOR 0x1000 +#define PA11IOR 0x0800 +#define PA10IOR 0x0400 +#define PA9IOR 0x0200 +#define PA8IOR 0x0100 +#define PA7IOR 0x0080 +#define PA6IOR 0x0040 +#define PA5IOR 0x0020 +#define PA4IOR 0x0010 +#define PA3IOR 0x0008 +#define PA2IOR 0x0004 +#define PA1IOR 0x0002 +#define PA0IOR 0x0001 + +/* + * Port A Control Registers (PACRH, PACRL1, PACRL2) + * and mode bits + */ +#define PACRH PFC_PACRH +#define PACRL1 PFC_PACRL1 +#define PACRL2 PFC_PACRL2 + +/* PACRH */ +#define PA23MD0 0x4000 +#define PA22MD0 0x1000 +#define PA21MD0 0x0400 +#define PA20MD0 0x0100 +#define PA19MD1 0x0080 +#define PA19MD0 0x0040 +#define PA18MD1 0x0020 +#define PA18MD0 0x0010 +#define PA17MD0 0x0004 +#define PA16MD0 0x0001 + +/* PACRL1 */ +#define PA15MD0 0x4000 +#define PA14MD0 0x1000 +#define PA13MD0 0x0400 +#define PA12MD0 0x0100 +#define PA11MD0 0x0040 +#define PA10MD0 0x0010 +#define PA9MD1 0x0008 +#define PA9MD0 0x0004 +#define PA8MD1 0x0002 +#define PA8MD0 0x0001 + +/* PACRL2 */ +#define PA7MD1 0x8000 +#define PA7MD0 0x4000 +#define PA6MD1 0x2000 +#define PA6MD0 0x1000 +#define PA5MD1 0x0800 +#define PA5MD0 0x0400 +#define PA4MD0 0x0100 +#define PA3MD0 0x0040 +#define PA2MD1 0x0020 +#define PA2MD0 0x0010 +#define PA1MD0 0x0004 +#define PA0MD0 0x0001 + +#define PA_TXD1 PA4MD0 +#define PA_RXD1 PA3MD0 +#define PA_TXD0 PA1MD0 +#define PA_RXD0 PA0MD0 + +/* + * Port B IO Register (PBIOR) + */ +#define PBIOR PFC_PBIOR +#define PB15IOR 0x8000 +#define PB14IOR 0x4000 +#define PB13IOR 0x2000 +#define PB12IOR 0x1000 +#define PB11IOR 0x0800 +#define PB10IOR 0x0400 +#define PB9IOR 0x0200 +#define PB8IOR 0x0100 +#define PB7IOR 0x0080 +#define PB6IOR 0x0040 +#define PB5IOR 0x0020 +#define PB4IOR 0x0010 +#define PB3IOR 0x0008 +#define PB2IOR 0x0004 +#define PB1IOR 0x0002 +#define PB0IOR 0x0001 + +/* + * Port B Control Register (PBCR1) + */ +#define PBCR1 PFC_PBCR1 +#define PB15MD1 0x8000 +#define PB15MD0 0x4000 +#define PB14MD1 0x2000 +#define PB14MD0 0x1000 +#define PB13MD1 0x0800 +#define PB13MD0 0x0400 +#define PB12MD1 0x0200 +#define PB12MD0 0x0100 +#define PB11MD1 0x0080 +#define PB11MD0 0x0040 +#define PB10MD1 0x0020 +#define PB10MD0 0x0010 +#define PB9MD1 0x0008 +#define PB9MD0 0x0004 +#define PB8MD1 0x0002 +#define PB8MD0 0x0001 + +#define PB15MD PB15MD1|PB14MD0 +#define PB14MD PB14MD1|PB14MD0 +#define PB13MD PB13MD1|PB13MD0 +#define PB12MD PB12MD1|PB12MD0 +#define PB11MD PB11MD1|PB11MD0 +#define PB10MD PB10MD1|PB10MD0 +#define PB9MD PB9MD1|PB9MD0 +#define PB8MD PB8MD1|PB8MD0 + +#define PB_TXD1 PB11MD1 +#define PB_RXD1 PB10MD1 +#define PB_TXD0 PB9MD1 +#define PB_RXD0 PB8MD1 + +/* + * Port B Control Register (PBCR2) + */ +#define PBCR2 PFC_PBCR2 +#define PB7MD1 0x8000 +#define PB7MD0 0x4000 +#define PB6MD1 0x2000 +#define PB6MD0 0x1000 +#define PB5MD1 0x0800 +#define PB5MD0 0x0400 +#define PB4MD1 0x0200 +#define PB4MD0 0x0100 +#define PB3MD1 0x0080 +#define PB3MD0 0x0040 +#define PB2MD1 0x0020 +#define PB2MD0 0x0010 +#define PB1MD1 0x0008 +#define PB1MD0 0x0004 +#define PB0MD1 0x0002 +#define PB0MD0 0x0001 + +#define PB7MD PB7MD1|PB7MD0 +#define PB6MD PB6MD1|PB6MD0 +#define PB5MD PB5MD1|PB5MD0 +#define PB4MD PB4MD1|PB4MD0 +#define PB3MD PB3MD1|PB3MD0 +#define PB2MD PB2MD1|PB2MD0 +#define PB1MD PB1MD1|PB1MD0 +#define PB0MD PB0MD1|PB0MD0 + +#endif /* _sh7_pfc_h */ diff --git a/bsps/sh/gensh2/include/sh/sh7_sci.h b/bsps/sh/gensh2/include/sh/sh7_sci.h new file mode 100644 index 0000000000..7218313704 --- /dev/null +++ b/bsps/sh/gensh2/include/sh/sh7_sci.h @@ -0,0 +1,88 @@ +/* + * Bit values for the serial control registers of the Hitachi SH704X + * + * From Hitachi tutorials + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _sh7_sci_h +#define _sh7_sci_h + +#include + +/* + * Serial mode register bits + */ + +#define SCI_SYNC_MODE 0x80 +#define SCI_SEVEN_BIT_DATA 0x40 +#define SCI_PARITY_ON 0x20 +#define SCI_ODD_PARITY 0x10 +#define SCI_STOP_BITS_2 0x08 +#define SCI_ENABLE_MULTIP 0x04 +#define SCI_PHI_64 0x03 +#define SCI_PHI_16 0x02 +#define SCI_PHI_4 0x01 +#define SCI_PHI_0 0x00 + +/* + * Serial register offsets, relative to SCI0_SMR or SCI1_SMR + */ + +#define SCI_SMR 0x00 +#define SCI_BRR 0x01 +#define SCI_SCR 0x02 +#define SCI_TDR 0x03 +#define SCI_SSR 0x04 +#define SCI_RDR 0x05 + +/* + * Serial control register bits + */ +#define SCI_TIE 0x80 /* Transmit interrupt enable */ +#define SCI_RIE 0x40 /* Receive interrupt enable */ +#define SCI_TE 0x20 /* Transmit enable */ +#define SCI_RE 0x10 /* Receive enable */ +#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */ +#define SCI_TEIE 0x04 /* Transmit end interrupt enable */ +#define SCI_CKE1 0x02 /* Clock enable 1 */ +#define SCI_CKE0 0x01 /* Clock enable 0 */ + +/* + * Serial status register bits + */ +#define SCI_TDRE 0x80 /* Transmit data register empty */ +#define SCI_RDRF 0x40 /* Receive data register full */ +#define SCI_ORER 0x20 /* Overrun error */ +#define SCI_FER 0x10 /* Framing error */ +#define SCI_PER 0x08 /* Parity error */ +#define SCI_TEND 0x04 /* Transmit end */ +#define SCI_MPB 0x02 /* Multiprocessor bit */ +#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */ + +/* + * INTC Priority Settings + */ + +#define SCI0_IPMSK 0x00F0 +#define SCI0_LOWIP 0x0010 +#define SCI1_IPMSK 0x000F +#define SCI1_LOWIP 0x0001 + +#endif /* _sh7_sci_h */ diff --git a/bsps/sh/gensh2/include/tm27.h b/bsps/sh/gensh2/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/sh/gensh2/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/sh/gensh4/headers.am b/bsps/sh/gensh4/headers.am new file mode 100644 index 0000000000..d3bb5ad26c --- /dev/null +++ b/bsps/sh/gensh4/headers.am @@ -0,0 +1,19 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/sh/gensh4/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/sh/gensh4/include/sdram.h +include_HEADERS += ../../../../../../bsps/sh/gensh4/include/tm27.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh4/include/rtems/score/iosh7750.h +include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh4/include/rtems/score/ipl.h +include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh4/include/rtems/score/ispsh7750.h +include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh4/include/rtems/score/sh4_regs.h +include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh4/include/rtems/score/sh7750_regs.h + +include_shdir = $(includedir)/sh +include_sh_HEADERS = +include_sh_HEADERS += ../../../../../../bsps/sh/gensh4/include/sh/sh4uart.h diff --git a/bsps/sh/gensh4/include/bsp.h b/bsps/sh/gensh4/include/bsp.h new file mode 100644 index 0000000000..b70c2ffdac --- /dev/null +++ b/bsps/sh/gensh4/include/bsp.h @@ -0,0 +1,92 @@ +/* + * generic sh4 BSP + * + * This include file contains all board IO definitions. + */ + +/* + * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * Based on work: + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Minor adaptations for sh2 by: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + */ + +#ifndef LIBBSP_SH_GENSH4_BSP_H +#define LIBBSP_SH_GENSH4_BSP_H + +#include +#include +#include + +#include "rtems/score/sh7750_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Constants */ + +/* + * Defined in the linker script 'linkcmds' + */ + +extern void *CPU_Interrupt_stack_low; +extern void *CPU_Interrupt_stack_high; + +/* + * Defined in start.S + */ +extern uint32_t boot_mode; +#define SH4_BOOT_MODE_FLASH 0 +#define SH4_BOOT_MODE_IPL 1 + +/* + * Device Driver Table Entries + */ + +/* + * We redefine CONSOLE_DRIVER_TABLE_ENTRY to redirect /dev/console + */ +#undef CONSOLE_DRIVER_TABLE_ENTRY +#define CONSOLE_DRIVER_TABLE_ENTRY \ + { console_initialize, console_open, console_close, \ + console_read, console_write, console_control } + +/* + * BSP methods that cross file boundaries. + */ +void bsp_hw_init(void); +void early_hw_init(void); +void bsp_cache_on(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sh/gensh4/include/rtems/score/iosh7750.h b/bsps/sh/gensh4/include/rtems/score/iosh7750.h new file mode 100644 index 0000000000..c5c532dbc2 --- /dev/null +++ b/bsps/sh/gensh4/include/rtems/score/iosh7750.h @@ -0,0 +1,47 @@ +/* + * This include file contains information pertaining to the Hitachi SH + * processor. + * + * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !! + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which + * contained no copyright notice. + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified to reflect on-chip registers for sh7045 processor, based on + * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which + * contained no copyright notice: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * August, 1999 + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + */ + +#ifndef __IOSH7750_H +#define __IOSH7750_H + +#include + +#endif diff --git a/bsps/sh/gensh4/include/rtems/score/ipl.h b/bsps/sh/gensh4/include/rtems/score/ipl.h new file mode 100644 index 0000000000..9ce2d87e0e --- /dev/null +++ b/bsps/sh/gensh4/include/rtems/score/ipl.h @@ -0,0 +1,73 @@ +/* ipl.h + * + * IPL console driver + * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * Based on work: + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __IPL_DRIVER_h +#define __IPL_DRIVER_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define IPL_DRIVER_TABLE_ENTRY \ + { ipl_console_initialize, ipl_console_open, ipl_console_close, \ + ipl_console_read, ipl_console_write, ipl_console_control } + + +#define NULL_SUCCESSFUL RTEMS_SUCCESSFUL + +rtems_device_driver ipl_console_initialize( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver ipl_console_open( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver ipl_console_close( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver ipl_console_read( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver ipl_console_write( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver ipl_console_control( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/sh/gensh4/include/rtems/score/ispsh7750.h b/bsps/sh/gensh4/include/rtems/score/ispsh7750.h new file mode 100644 index 0000000000..396644a241 --- /dev/null +++ b/bsps/sh/gensh4/include/rtems/score/ispsh7750.h @@ -0,0 +1,62 @@ +/* + * This include file contains information pertaining to the Hitachi + * SH7750 processor. + * + * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * Based on work of: + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified to reflect isp entries for sh7045 processor: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + */ + +#ifndef __CPU_ISPS_H +#define __CPU_ISPS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* dummy ISP */ +extern void _dummy_isp( void ); + +extern void __ISR_Handler( uint32_t vector ); + +/* This variable contains VBR value used to pass control when debug, error + * or virtual memory exceptions occured. + */ +extern void *_VBR_Saved; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sh/gensh4/include/rtems/score/sh4_regs.h b/bsps/sh/gensh4/include/rtems/score/sh4_regs.h new file mode 100644 index 0000000000..074dc6d7a1 --- /dev/null +++ b/bsps/sh/gensh4/include/rtems/score/sh4_regs.h @@ -0,0 +1,51 @@ +/* + * Bits on SH-4 registers. + * See SH-4 Programming manual for more details. + * + * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia + * Author: Alexandra Kossovsky + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SH4_REGS_H__ +#define __SH4_REGS_H__ + +/* SR -- Status Register */ +#define SH4_SR_MD 0x40000000 /* Priveleged mode */ +#define SH4_SR_RB 0x20000000 /* General register bank specifier */ +#define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */ +#define SH4_SR_FD 0x00008000 /* FPU disable bit */ +#define SH4_SR_M 0x00000200 /* For signed division: + divisor (module) is negative */ +#define SH4_SR_Q 0x00000100 /* For signed division: + dividend (and quotient) is negative */ +#define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */ +#define SH4_SR_IMASK_S 4 +#define SH4_SR_S 0x00000002 /* Saturation for MAC instruction: + if set, data in MACH/L register + is restricted to 48/32 bits + for MAC.W/L instructions */ +#define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */ +#define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */ + +/* FPSCR -- FPU Starus/Control Register */ +#define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */ +#define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */ +#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point + operations flag */ + /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */ +#define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */ +#define SH4_FPSCR_CAUSE 0x0003f000 /* FPU exeption cause field */ +#define SH4_FPSCR_CAUSE_S 12 +#define SH4_FPSCR_ENABLE 0x00000f80 /* FPU exeption enable field */ +#define SH4_FPSCR_ENABLE_s 7 +#define SH4_FPSCR_FLAG 0x0000007d /* FPU exeption flag field */ +#define SH4_FPSCR_FLAG_S 2 +#define SH4_FPSCR_RM 0x00000001 /* Rounding mode: + 1/0 -- round to zero/nearest */ +#define SH4_FPSCR_RESERV 0xffd00000 /* Reserved bits, read/write as 0 */ + +#endif diff --git a/bsps/sh/gensh4/include/rtems/score/sh7750_regs.h b/bsps/sh/gensh4/include/rtems/score/sh7750_regs.h new file mode 100644 index 0000000000..b65f9b6e51 --- /dev/null +++ b/bsps/sh/gensh4/include/rtems/score/sh7750_regs.h @@ -0,0 +1,1613 @@ +/* + * SH-7750 memory-mapped registers + * This file based on information provided in the following document: + * "Hitachi SuperH (tm) RISC engine. SH7750 Series (SH7750, SH7750S) + * Hardware Manual" + * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd. + * + * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia + * Author: Alexandra Kossovsky + * Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SH7750_REGS_H__ +#define __SH7750_REGS_H__ + +/* + * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and + * in 0x1f000000 - 0x1fffffff (area 7 address) + */ +#define SH7750_P4_BASE 0xff000000 /* Accessable only in + priveleged mode */ +#define SH7750_A7_BASE 0x1f000000 /* Accessable only using TLB */ + +#define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs)) +#define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs)) + +/* + * MMU Registers + */ + +/* Page Table Entry High register - PTEH */ +#define SH7750_PTEH_REGOFS 0x000000 /* offset */ +#define SH7750_PTEH SH7750_P4_REG32(SH7750_PTEH_REGOFS) +#define SH7750_PTEH_A7 SH7750_A7_REG32(SH7750_PTEH_REGOFS) +#define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */ +#define SH7750_PTEH_VPN_S 10 +#define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */ +#define SH7750_PTEH_ASID_S 0 + +/* Page Table Entry Low register - PTEL */ +#define SH7750_PTEL_REGOFS 0x000004 /* offset */ +#define SH7750_PTEL SH7750_P4_REG32(SH7750_PTEL_REGOFS) +#define SH7750_PTEL_A7 SH7750_A7_REG32(SH7750_PTEL_REGOFS) +#define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */ +#define SH7750_PTEL_PPN_S 10 +#define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */ +#define SH7750_PTEL_SZ1 0x00000080 /* Page size bit 1 */ +#define SH7750_PTEL_SZ0 0x00000010 /* Page size bit 0 */ +#define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */ +#define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */ +#define SH7750_PTEL_SZ_64KB 0x00000080 /* 64-kbyte page */ +#define SH7750_PTEL_SZ_1MB 0x00000090 /* 1-Mbyte page */ +#define SH7750_PTEL_PR 0x00000060 /* Protection Key Data */ +#define SH7750_PTEL_PR_ROPO 0x00000000 /* read-only in priv mode */ +#define SH7750_PTEL_PR_RWPO 0x00000020 /* read-write in priv mode */ +#define SH7750_PTEL_PR_ROPU 0x00000040 /* read-only in priv or user mode*/ +#define SH7750_PTEL_PR_RWPU 0x00000060 /* read-write in priv or user mode*/ +#define SH7750_PTEL_C 0x00000008 /* Cacheability + (0 - page not cacheable) */ +#define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been + performed to a page) */ +#define SH7750_PTEL_SH 0x00000002 /* Share Status bit (1 - page are + shared by processes) */ +#define SH7750_PTEL_WT 0x00000001 /* Write-through bit, specifies the + cache write mode: + 0 - Copy-back mode + 1 - Write-through mode */ + +/* Page Table Entry Assistance register - PTEA */ +#define SH7750_PTEA_REGOFS 0x000034 /* offset */ +#define SH7750_PTEA SH7750_P4_REG32(SH7750_PTEA_REGOFS) +#define SH7750_PTEA_A7 SH7750_A7_REG32(SH7750_PTEA_REGOFS) +#define SH7750_PTEA_TC 0x00000008 /* Timing Control bit + 0 - use area 5 wait states + 1 - use area 6 wait states */ +#define SH7750_PTEA_SA 0x00000007 /* Space Attribute bits: */ +#define SH7750_PTEA_SA_UNDEF 0x00000000 /* 0 - undefined */ +#define SH7750_PTEA_SA_IOVAR 0x00000001 /* 1 - variable-size I/O space */ +#define SH7750_PTEA_SA_IO8 0x00000002 /* 2 - 8-bit I/O space */ +#define SH7750_PTEA_SA_IO16 0x00000003 /* 3 - 16-bit I/O space */ +#define SH7750_PTEA_SA_CMEM8 0x00000004 /* 4 - 8-bit common memory space*/ +#define SH7750_PTEA_SA_CMEM16 0x00000005 /* 5 - 16-bit common memory space*/ +#define SH7750_PTEA_SA_AMEM8 0x00000006 /* 6 - 8-bit attr memory space */ +#define SH7750_PTEA_SA_AMEM16 0x00000007 /* 7 - 16-bit attr memory space */ + + +/* Translation table base register */ +#define SH7750_TTB_REGOFS 0x000008 /* offset */ +#define SH7750_TTB SH7750_P4_REG32(SH7750_TTB_REGOFS) +#define SH7750_TTB_A7 SH7750_A7_REG32(SH7750_TTB_REGOFS) + +/* TLB exeption address register - TEA */ +#define SH7750_TEA_REGOFS 0x00000c /* offset */ +#define SH7750_TEA SH7750_P4_REG32(SH7750_TEA_REGOFS) +#define SH7750_TEA_A7 SH7750_A7_REG32(SH7750_TEA_REGOFS) + +/* MMU control register - MMUCR */ +#define SH7750_MMUCR_REGOFS 0x000010 /* offset */ +#define SH7750_MMUCR SH7750_P4_REG32(SH7750_MMUCR_REGOFS) +#define SH7750_MMUCR_A7 SH7750_A7_REG32(SH7750_MMUCR_REGOFS) +#define SH7750_MMUCR_AT 0x00000001 /* Address translation bit */ +#define SH7750_MMUCR_TI 0x00000004 /* TLB invalidate */ +#define SH7750_MMUCR_SV 0x00000100 /* Single Virtual Mode bit */ +#define SH7750_MMUCR_SQMD 0x00000200 /* Store Queue Mode bit */ +#define SH7750_MMUCR_URC 0x0000FC00 /* UTLB Replace Counter */ +#define SH7750_MMUCR_URC_S 10 +#define SH7750_MMUCR_URB 0x00FC0000 /* UTLB Replace Boundary */ +#define SH7750_MMUCR_URB_S 18 +#define SH7750_MMUCR_LRUI 0xFC000000 /* Least Recently Used ITLB */ +#define SH7750_MMUCR_LRUI_S 26 + + + + +/* + * Cache registers + * IC -- instructions cache + * OC -- operand cache + */ + +/* Cache Control Register - CCR */ +#define SH7750_CCR_REGOFS 0x00001c /* offset */ +#define SH7750_CCR SH7750_P4_REG32(SH7750_CCR_REGOFS) +#define SH7750_CCR_A7 SH7750_A7_REG32(SH7750_CCR_REGOFS) + +#define SH7750_CCR_IIX 0x00008000 /* IC index enable bit */ +#define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit: + set it to clear IC */ +#define SH7750_CCR_ICE 0x00000100 /* IC enable bit */ +#define SH7750_CCR_OIX 0x00000080 /* OC index enable bit */ +#define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit + if you set OCE = 0, + you should set ORA = 0 */ +#define SH7750_CCR_OCI 0x00000008 /* OC invalidation bit */ +#define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */ +#define SH7750_CCR_WT 0x00000002 /* Write-through bit for P0,U0,P3 area */ +#define SH7750_CCR_OCE 0x00000001 /* OC enable bit */ + +/* Queue address control register 0 - QACR0 */ +#define SH7750_QACR0_REGOFS 0x000038 /* offset */ +#define SH7750_QACR0 SH7750_P4_REG32(SH7750_QACR0_REGOFS) +#define SH7750_QACR0_A7 SH7750_A7_REG32(SH7750_QACR0_REGOFS) + +/* Queue address control register 1 - QACR1 */ +#define SH7750_QACR1_REGOFS 0x00003c /* offset */ +#define SH7750_QACR1 SH7750_P4_REG32(SH7750_QACR1_REGOFS) +#define SH7750_QACR1_A7 SH7750_A7_REG32(SH7750_QACR1_REGOFS) + + +/* + * Exeption-related registers + */ + +/* Immediate data for TRAPA instuction - TRA */ +#define SH7750_TRA_REGOFS 0x000020 /* offset */ +#define SH7750_TRA SH7750_P4_REG32(SH7750_TRA_REGOFS) +#define SH7750_TRA_A7 SH7750_A7_REG32(SH7750_TRA_REGOFS) + +#define SH7750_TRA_IMM 0x000003fd /* Immediate data operand */ +#define SH7750_TRA_IMM_S 2 + +/* Exeption event register - EXPEVT */ +#define SH7750_EXPEVT_REGOFS 0x000024 +#define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS) +#define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS) + +#define SH7750_EXPEVT_EX 0x00000fff /* Exeption code */ +#define SH7750_EXPEVT_EX_S 0 + +/* Interrupt event register */ +#define SH7750_INTEVT_REGOFS 0x000028 +#define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS) +#define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS) +#define SH7750_INTEVT_EX 0x00000fff /* Exeption code */ +#define SH7750_INTEVT_EX_S 0 + +/* + * Exception/interrupt codes + */ +#define SH7750_EVT_TO_NUM(evt) ((evt) >> 5) + +/* Reset exception category */ +#define SH7750_EVT_POWER_ON_RST 0x000 /* Power-on reset */ +#define SH7750_EVT_MANUAL_RST 0x020 /* Manual reset */ +#define SH7750_EVT_TLB_MULT_HIT 0x140 /* TLB multiple-hit exception */ + +/* General exception category */ +#define SH7750_EVT_USER_BREAK 0x1E0 /* User break */ +#define SH7750_EVT_IADDR_ERR 0x0E0 /* Instruction address error */ +#define SH7750_EVT_TLB_READ_MISS 0x040 /* ITLB miss exception / + DTLB miss exception (read) */ +#define SH7750_EVT_TLB_READ_PROTV 0x0A0 /* ITLB protection violation / + DTLB protection violation (read)*/ +#define SH7750_EVT_ILLEGAL_INSTR 0x180 /* General Illegal Instruction + exception */ +#define SH7750_EVT_SLOT_ILLEGAL_INSTR 0x1A0 /* Slot Illegal Instruction + exception */ +#define SH7750_EVT_FPU_DISABLE 0x800 /* General FPU disable exception*/ +#define SH7750_EVT_SLOT_FPU_DISABLE 0x820 /* Slot FPU disable exception */ +#define SH7750_EVT_DATA_READ_ERR 0x0E0 /* Data address error (read) */ +#define SH7750_EVT_DATA_WRITE_ERR 0x100 /* Data address error (write) */ +#define SH7750_EVT_DTLB_WRITE_MISS 0x060 /* DTLB miss exception (write) */ +#define SH7750_EVT_DTLB_WRITE_PROTV 0x0C0 /* DTLB protection violation + exception (write) */ +#define SH7750_EVT_FPU_EXCEPTION 0x120 /* FPU exception */ +#define SH7750_EVT_INITIAL_PGWRITE 0x080 /* Initial Page Write exception */ +#define SH7750_EVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */ + +/* Interrupt exception category */ +#define SH7750_EVT_NMI 0x1C0 /* Non-maskable interrupt */ +#define SH7750_EVT_IRQ0 0x200 /* External Interrupt 0 */ +#define SH7750_EVT_IRQ1 0x220 /* External Interrupt 1 */ +#define SH7750_EVT_IRQ2 0x240 /* External Interrupt 2 */ +#define SH7750_EVT_IRQ3 0x260 /* External Interrupt 3 */ +#define SH7750_EVT_IRQ4 0x280 /* External Interrupt 4 */ +#define SH7750_EVT_IRQ5 0x2A0 /* External Interrupt 5 */ +#define SH7750_EVT_IRQ6 0x2C0 /* External Interrupt 6 */ +#define SH7750_EVT_IRQ7 0x2E0 /* External Interrupt 7 */ +#define SH7750_EVT_IRQ8 0x300 /* External Interrupt 8 */ +#define SH7750_EVT_IRQ9 0x320 /* External Interrupt 9 */ +#define SH7750_EVT_IRQA 0x340 /* External Interrupt A */ +#define SH7750_EVT_IRQB 0x360 /* External Interrupt B */ +#define SH7750_EVT_IRQC 0x380 /* External Interrupt C */ +#define SH7750_EVT_IRQD 0x3A0 /* External Interrupt D */ +#define SH7750_EVT_IRQE 0x3C0 /* External Interrupt E */ + +/* Peripheral Module Interrupts - Timer Unit (TMU) */ +#define SH7750_EVT_TUNI0 0x400 /* TMU Underflow Interrupt 0 */ +#define SH7750_EVT_TUNI1 0x420 /* TMU Underflow Interrupt 1 */ +#define SH7750_EVT_TUNI2 0x440 /* TMU Underflow Interrupt 2 */ +#define SH7750_EVT_TICPI2 0x460 /* TMU Input Capture Interrupt 2*/ + +/* Peripheral Module Interrupts - Real-Time Clock (RTC) */ +#define SH7750_EVT_RTC_ATI 0x480 /* Alarm Interrupt Request */ +#define SH7750_EVT_RTC_PRI 0x4A0 /* Periodic Interrupt Request */ +#define SH7750_EVT_RTC_CUI 0x4C0 /* Carry Interrupt Request */ + +/* Peripheral Module Interrupts - Serial Communication Interface (SCI) */ +#define SH7750_EVT_SCI_ERI 0x4E0 /* Receive Error */ +#define SH7750_EVT_SCI_RXI 0x500 /* Receive Data Register Full */ +#define SH7750_EVT_SCI_TXI 0x520 /* Transmit Data Register Empty */ +#define SH7750_EVT_SCI_TEI 0x540 /* Transmit End */ + +/* Peripheral Module Interrupts - Watchdog Timer (WDT) */ +#define SH7750_EVT_WDT_ITI 0x560 /* Interval Timer Interrupt + (used when WDT operates in + interval timer mode) */ + +/* Peripheral Module Interrupts - Memory Refresh Unit (REF) */ +#define SH7750_EVT_REF_RCMI 0x580 /* Compare-match Interrupt */ +#define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow + interrupt */ + +/* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */ +#define SH7750_EVT_HUDI 0x600 /* UDI interrupt */ + +/* Peripheral Module Interrupts - General-Purpose I/O (GPIO) */ +#define SH7750_EVT_GPIO 0x620 /* GPIO Interrupt */ + +/* Peripheral Module Interrupts - DMA Controller (DMAC) */ +#define SH7750_EVT_DMAC_DMTE0 0x640 /* DMAC 0 Transfer End Interrupt*/ +#define SH7750_EVT_DMAC_DMTE1 0x660 /* DMAC 1 Transfer End Interrupt*/ +#define SH7750_EVT_DMAC_DMTE2 0x680 /* DMAC 2 Transfer End Interrupt*/ +#define SH7750_EVT_DMAC_DMTE3 0x6A0 /* DMAC 3 Transfer End Interrupt*/ +#define SH7750_EVT_DMAC_DMAE 0x6C0 /* DMAC Address Error Interrupt */ + +/* Peripheral Module Interrupts - Serial Communication Interface with FIFO */ +/* (SCIF) */ +#define SH7750_EVT_SCIF_ERI 0x700 /* Receive Error */ +#define SH7750_EVT_SCIF_RXI 0x720 /* Receive FIFO Data Full or + Receive Data ready interrupt */ +#define SH7750_EVT_SCIF_BRI 0x740 /* Break or overrun error */ +#define SH7750_EVT_SCIF_TXI 0x760 /* Transmit FIFO Data Empty */ + +/* + * Power Management + */ +#define SH7750_STBCR_REGOFS 0xC00004 /* offset */ +#define SH7750_STBCR SH7750_P4_REG32(SH7750_STBCR_REGOFS) +#define SH7750_STBCR_A7 SH7750_A7_REG32(SH7750_STBCR_REGOFS) + +#define SH7750_STBCR_STBY 0x80 /* Specifies a transition to standby mode: + 0 - Transition to SLEEP mode on SLEEP + 1 - Transition to STANDBY mode on SLEEP*/ +#define SH7750_STBCR_PHZ 0x40 /* State of peripheral module pins in + standby mode: + 0 - normal state + 1 - high-impendance state */ + +#define SH7750_STBCR_PPU 0x20 /* Peripheral module pins pull-up controls*/ +#define SH7750_STBCR_MSTP4 0x10 /* Stopping the clock supply to DMAC */ +#define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4 +#define SH7750_STBCR_MSTP3 0x08 /* Stopping the clock supply to SCIF */ +#define SH7750_STBCR_SCIF_STP SH7750_STBCR_MSTP3 +#define SH7750_STBCR_MSTP2 0x04 /* Stopping the clock supply to TMU */ +#define SH7750_STBCR_TMU_STP SH7750_STBCR_MSTP2 +#define SH7750_STBCR_MSTP1 0x02 /* Stopping the clock supply to RTC */ +#define SH7750_STBCR_RTC_STP SH7750_STBCR_MSTP1 +#define SH7750_STBCR_MSPT0 0x01 /* Stopping the clock supply to SCI */ +#define SH7750_STBCR_SCI_STP SH7750_STBCR_MSTP0 + +#define SH7750_STBCR_STBY 0x80 + + +#define SH7750_STBCR2_REGOFS 0xC00010 /* offset */ +#define SH7750_STBCR2 SH7750_P4_REG32(SH7750_STBCR2_REGOFS) +#define SH7750_STBCR2_A7 SH7750_A7_REG32(SH7750_STBCR2_REGOFS) + +#define SH7750_STBCR2_DSLP 0x80 /* Specifies transition to deep sleep mode: + 0 - transition to sleep or standby mode + as it is specified in STBY bit + 1 - transition to deep sleep mode on + execution of SLEEP instruction */ +#define SH7750_STBCR2_MSTP6 0x02 /* Stopping the clock supply to Store Queue + in the cache controller */ +#define SH7750_STBCR2_SQ_STP SH7750_STBCR2_MSTP6 +#define SH7750_STBCR2_MSTP5 0x01 /* Stopping the clock supply to the User + Break Controller (UBC) */ +#define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5 + +/* + * Clock Pulse Generator (CPG) + */ +#define SH7750_FRQCR_REGOFS 0xC00000 /* offset */ +#define SH7750_FRQCR SH7750_P4_REG32(SH7750_FRQCR_REGOFS) +#define SH7750_FRQCR_A7 SH7750_A7_REG32(SH7750_FRQCR_REGOFS) + +#define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable + 0 - CKIO pin goes to HiZ/pullup + 1 - Clock is output from CKIO */ +#define SH7750_FRQCR_PLL1EN 0x0400 /* PLL circuit 1 enable */ +#define SH7750_FRQCR_PLL2EN 0x0200 /* PLL circuit 2 enable */ + +#define SH7750_FRQCR_IFC 0x01C0 /* CPU clock frequency division ratio: */ +#define SH7750_FRQCR_IFCDIV1 0x0000 /* 0 - * 1 */ +#define SH7750_FRQCR_IFCDIV2 0x0040 /* 1 - * 1/2 */ +#define SH7750_FRQCR_IFCDIV3 0x0080 /* 2 - * 1/3 */ +#define SH7750_FRQCR_IFCDIV4 0x00C0 /* 3 - * 1/4 */ +#define SH7750_FRQCR_IFCDIV6 0x0100 /* 4 - * 1/6 */ +#define SH7750_FRQCR_IFCDIV8 0x0140 /* 5 - * 1/8 */ + +#define SH7750_FRQCR_BFC 0x0038 /* Bus clock frequency division ratio: */ +#define SH7750_FRQCR_BFCDIV1 0x0000 /* 0 - * 1 */ +#define SH7750_FRQCR_BFCDIV2 0x0008 /* 1 - * 1/2 */ +#define SH7750_FRQCR_BFCDIV3 0x0010 /* 2 - * 1/3 */ +#define SH7750_FRQCR_BFCDIV4 0x0018 /* 3 - * 1/4 */ +#define SH7750_FRQCR_BFCDIV6 0x0020 /* 4 - * 1/6 */ +#define SH7750_FRQCR_BFCDIV8 0x0028 /* 5 - * 1/8 */ + +#define SH7750_FRQCR_PFC 0x0007 /* Peripheral module clock frequency + division ratio: */ +#define SH7750_FRQCR_PFCDIV2 0x0000 /* 0 - * 1/2 */ +#define SH7750_FRQCR_PFCDIV3 0x0001 /* 1 - * 1/3 */ +#define SH7750_FRQCR_PFCDIV4 0x0002 /* 2 - * 1/4 */ +#define SH7750_FRQCR_PFCDIV6 0x0003 /* 3 - * 1/6 */ +#define SH7750_FRQCR_PFCDIV8 0x0004 /* 4 - * 1/8 */ + +/* + * Watchdog Timer (WDT) + */ + +/* Watchdog Timer Counter register - WTCNT */ +#define SH7750_WTCNT_REGOFS 0xC00008 /* offset */ +#define SH7750_WTCNT SH7750_P4_REG32(SH7750_WTCNT_REGOFS) +#define SH7750_WTCNT_A7 SH7750_A7_REG32(SH7750_WTCNT_REGOFS) +#define SH7750_WTCNT_KEY 0x5A00 /* When WTCNT byte register written, + you have to set the upper byte to + 0x5A */ + +/* Watchdog Timer Control/Status register - WTCSR */ +#define SH7750_WTCSR_REGOFS 0xC0000C /* offset */ +#define SH7750_WTCSR SH7750_P4_REG32(SH7750_WTCSR_REGOFS) +#define SH7750_WTCSR_A7 SH7750_A7_REG32(SH7750_WTCSR_REGOFS) +#define SH7750_WTCSR_KEY 0xA500 /* When WTCSR byte register written, + you have to set the upper byte to + 0xA5 */ +#define SH7750_WTCSR_TME 0x80 /* Timer enable (1-upcount start) */ +#define SH7750_WTCSR_MODE 0x40 /* Timer Mode Select: */ +#define SH7750_WTCSR_MODE_WT 0x40 /* Watchdog Timer Mode */ +#define SH7750_WTCSR_MODE_IT 0x00 /* Interval Timer Mode */ +#define SH7750_WTCSR_RSTS 0x20 /* Reset Select: */ +#define SH7750_WTCSR_RST_MAN 0x20 /* Manual Reset */ +#define SH7750_WTCSR_RST_PWR 0x00 /* Power-on Reset */ +#define SH7750_WTCSR_WOVF 0x10 /* Watchdog Timer Overflow Flag */ +#define SH7750_WTCSR_IOVF 0x08 /* Interval Timer Overflow Flag */ +#define SH7750_WTCSR_CKS 0x07 /* Clock Select: */ +#define SH7750_WTCSR_CKS_DIV32 0x00 /* 1/32 of frequency divider 2 input */ +#define SH7750_WTCSR_CKS_DIV64 0x01 /* 1/64 */ +#define SH7750_WTCSR_CKS_DIV128 0x02 /* 1/128 */ +#define SH7750_WTCSR_CKS_DIV256 0x03 /* 1/256 */ +#define SH7750_WTCSR_CKS_DIV512 0x04 /* 1/512 */ +#define SH7750_WTCSR_CKS_DIV1024 0x05 /* 1/1024 */ +#define SH7750_WTCSR_CKS_DIV2048 0x06 /* 1/2048 */ +#define SH7750_WTCSR_CKS_DIV4096 0x07 /* 1/4096 */ + +/* + * Real-Time Clock (RTC) + */ +/* 64-Hz Counter Register (byte, read-only) - R64CNT */ +#define SH7750_R64CNT_REGOFS 0xC80000 /* offset */ +#define SH7750_R64CNT SH7750_P4_REG32(SH7750_R64CNT_REGOFS) +#define SH7750_R64CNT_A7 SH7750_A7_REG32(SH7750_R64CNT_REGOFS) + +/* Second Counter Register (byte, BCD-coded) - RSECCNT */ +#define SH7750_RSECCNT_REGOFS 0xC80004 /* offset */ +#define SH7750_RSECCNT SH7750_P4_REG32(SH7750_RSECCNT_REGOFS) +#define SH7750_RSECCNT_A7 SH7750_A7_REG32(SH7750_RSECCNT_REGOFS) + +/* Minute Counter Register (byte, BCD-coded) - RMINCNT */ +#define SH7750_RMINCNT_REGOFS 0xC80008 /* offset */ +#define SH7750_RMINCNT SH7750_P4_REG32(SH7750_RMINCNT_REGOFS) +#define SH7750_RMINCNT_A7 SH7750_A7_REG32(SH7750_RMINCNT_REGOFS) + +/* Hour Counter Register (byte, BCD-coded) - RHRCNT */ +#define SH7750_RHRCNT_REGOFS 0xC8000C /* offset */ +#define SH7750_RHRCNT SH7750_P4_REG32(SH7750_RHRCNT_REGOFS) +#define SH7750_RHRCNT_A7 SH7750_A7_REG32(SH7750_RHRCNT_REGOFS) + +/* Day-of-Week Counter Register (byte) - RWKCNT */ +#define SH7750_RWKCNT_REGOFS 0xC80010 /* offset */ +#define SH7750_RWKCNT SH7750_P4_REG32(SH7750_RWKCNT_REGOFS) +#define SH7750_RWKCNT_A7 SH7750_A7_REG32(SH7750_RWKCNT_REGOFS) + +#define SH7750_RWKCNT_SUN 0 /* Sunday */ +#define SH7750_RWKCNT_MON 1 /* Monday */ +#define SH7750_RWKCNT_TUE 2 /* Tuesday */ +#define SH7750_RWKCNT_WED 3 /* Wednesday */ +#define SH7750_RWKCNT_THU 4 /* Thursday */ +#define SH7750_RWKCNT_FRI 5 /* Friday */ +#define SH7750_RWKCNT_SAT 6 /* Saturday */ + +/* Day Counter Register (byte, BCD-coded) - RDAYCNT */ +#define SH7750_RDAYCNT_REGOFS 0xC80014 /* offset */ +#define SH7750_RDAYCNT SH7750_P4_REG32(SH7750_RDAYCNT_REGOFS) +#define SH7750_RDAYCNT_A7 SH7750_A7_REG32(SH7750_RDAYCNT_REGOFS) + +/* Month Counter Register (byte, BCD-coded) - RMONCNT */ +#define SH7750_RMONCNT_REGOFS 0xC80018 /* offset */ +#define SH7750_RMONCNT SH7750_P4_REG32(SH7750_RMONCNT_REGOFS) +#define SH7750_RMONCNT_A7 SH7750_A7_REG32(SH7750_RMONCNT_REGOFS) + +/* Year Counter Register (half, BCD-coded) - RYRCNT */ +#define SH7750_RYRCNT_REGOFS 0xC8001C /* offset */ +#define SH7750_RYRCNT SH7750_P4_REG32(SH7750_RYRCNT_REGOFS) +#define SH7750_RYRCNT_A7 SH7750_A7_REG32(SH7750_RYRCNT_REGOFS) + +/* Second Alarm Register (byte, BCD-coded) - RSECAR */ +#define SH7750_RSECAR_REGOFS 0xC80020 /* offset */ +#define SH7750_RSECAR SH7750_P4_REG32(SH7750_RSECAR_REGOFS) +#define SH7750_RSECAR_A7 SH7750_A7_REG32(SH7750_RSECAR_REGOFS) +#define SH7750_RSECAR_ENB 0x80 /* Second Alarm Enable */ + +/* Minute Alarm Register (byte, BCD-coded) - RMINAR */ +#define SH7750_RMINAR_REGOFS 0xC80024 /* offset */ +#define SH7750_RMINAR SH7750_P4_REG32(SH7750_RMINAR_REGOFS) +#define SH7750_RMINAR_A7 SH7750_A7_REG32(SH7750_RMINAR_REGOFS) +#define SH7750_RMINAR_ENB 0x80 /* Minute Alarm Enable */ + +/* Hour Alarm Register (byte, BCD-coded) - RHRAR */ +#define SH7750_RHRAR_REGOFS 0xC80028 /* offset */ +#define SH7750_RHRAR SH7750_P4_REG32(SH7750_RHRAR_REGOFS) +#define SH7750_RHRAR_A7 SH7750_A7_REG32(SH7750_RHRAR_REGOFS) +#define SH7750_RHRAR_ENB 0x80 /* Hour Alarm Enable */ + +/* Day-of-Week Alarm Register (byte) - RWKAR */ +#define SH7750_RWKAR_REGOFS 0xC8002C /* offset */ +#define SH7750_RWKAR SH7750_P4_REG32(SH7750_RWKAR_REGOFS) +#define SH7750_RWKAR_A7 SH7750_A7_REG32(SH7750_RWKAR_REGOFS) +#define SH7750_RWKAR_ENB 0x80 /* Day-of-week Alarm Enable */ + +#define SH7750_RWKAR_SUN 0 /* Sunday */ +#define SH7750_RWKAR_MON 1 /* Monday */ +#define SH7750_RWKAR_TUE 2 /* Tuesday */ +#define SH7750_RWKAR_WED 3 /* Wednesday */ +#define SH7750_RWKAR_THU 4 /* Thursday */ +#define SH7750_RWKAR_FRI 5 /* Friday */ +#define SH7750_RWKAR_SAT 6 /* Saturday */ + +/* Day Alarm Register (byte, BCD-coded) - RDAYAR */ +#define SH7750_RDAYAR_REGOFS 0xC80030 /* offset */ +#define SH7750_RDAYAR SH7750_P4_REG32(SH7750_RDAYAR_REGOFS) +#define SH7750_RDAYAR_A7 SH7750_A7_REG32(SH7750_RDAYAR_REGOFS) +#define SH7750_RDAYAR_ENB 0x80 /* Day Alarm Enable */ + +/* Month Counter Register (byte, BCD-coded) - RMONAR */ +#define SH7750_RMONAR_REGOFS 0xC80034 /* offset */ +#define SH7750_RMONAR SH7750_P4_REG32(SH7750_RMONAR_REGOFS) +#define SH7750_RMONAR_A7 SH7750_A7_REG32(SH7750_RMONAR_REGOFS) +#define SH7750_RMONAR_ENB 0x80 /* Month Alarm Enable */ + +/* RTC Control Register 1 (byte) - RCR1 */ +#define SH7750_RCR1_REGOFS 0xC80038 /* offset */ +#define SH7750_RCR1 SH7750_P4_REG32(SH7750_RCR1_REGOFS) +#define SH7750_RCR1_A7 SH7750_A7_REG32(SH7750_RCR1_REGOFS) +#define SH7750_RCR1_CF 0x80 /* Carry Flag */ +#define SH7750_RCR1_CIE 0x10 /* Carry Interrupt Enable */ +#define SH7750_RCR1_AIE 0x08 /* Alarm Interrupt Enable */ +#define SH7750_RCR1_AF 0x01 /* Alarm Flag */ + +/* RTC Control Register 2 (byte) - RCR2 */ +#define SH7750_RCR2_REGOFS 0xC8003C /* offset */ +#define SH7750_RCR2 SH7750_P4_REG32(SH7750_RCR2_REGOFS) +#define SH7750_RCR2_A7 SH7750_A7_REG32(SH7750_RCR2_REGOFS) +#define SH7750_RCR2_PEF 0x80 /* Periodic Interrupt Flag */ +#define SH7750_RCR2_PES 0x70 /* Periodic Interrupt Enable: */ +#define SH7750_RCR2_PES_DIS 0x00 /* Periodic Interrupt Disabled */ +#define SH7750_RCR2_PES_DIV256 0x10 /* Generated at 1/256 sec interval */ +#define SH7750_RCR2_PES_DIV64 0x20 /* Generated at 1/64 sec interval */ +#define SH7750_RCR2_PES_DIV16 0x30 /* Generated at 1/16 sec interval */ +#define SH7750_RCR2_PES_DIV4 0x40 /* Generated at 1/4 sec interval */ +#define SH7750_RCR2_PES_DIV2 0x50 /* Generated at 1/2 sec interval */ +#define SH7750_RCR2_PES_x1 0x60 /* Generated at 1 sec interval */ +#define SH7750_RCR2_PES_x2 0x70 /* Generated at 2 sec interval */ +#define SH7750_RCR2_RTCEN 0x08 /* RTC Crystal Oscillator is Operated */ +#define SH7750_RCR2_ADJ 0x04 /* 30-Second Adjastment */ +#define SH7750_RCR2_RESET 0x02 /* Frequency divider circuits are reset*/ +#define SH7750_RCR2_START 0x01 /* 0 - sec, min, hr, day-of-week, month, + year counters are stopped + 1 - sec, min, hr, day-of-week, month, + year counters operate normally */ + + +/* + * Timer Unit (TMU) + */ +/* Timer Output Control Register (byte) - TOCR */ +#define SH7750_TOCR_REGOFS 0xD80000 /* offset */ +#define SH7750_TOCR SH7750_P4_REG32(SH7750_TOCR_REGOFS) +#define SH7750_TOCR_A7 SH7750_A7_REG32(SH7750_TOCR_REGOFS) +#define SH7750_TOCR_TCOE 0x01 /* Timer Clock Pin Control: + 0 - TCLK is used as external clock + input or input capture control + 1 - TCLK is used as on-chip RTC + output clock pin */ + +/* Timer Start Register (byte) - TSTR */ +#define SH7750_TSTR_REGOFS 0xD80004 /* offset */ +#define SH7750_TSTR SH7750_P4_REG32(SH7750_TSTR_REGOFS) +#define SH7750_TSTR_A7 SH7750_A7_REG32(SH7750_TSTR_REGOFS) +#define SH7750_TSTR_STR2 0x04 /* TCNT2 performs count operations */ +#define SH7750_TSTR_STR1 0x02 /* TCNT1 performs count operations */ +#define SH7750_TSTR_STR0 0x01 /* TCNT0 performs count operations */ +#define SH7750_TSTR_STR(n) (1 << (n)) + +/* Timer Constant Register - TCOR0, TCOR1, TCOR2 */ +#define SH7750_TCOR_REGOFS(n) (0xD80008 + ((n)*12)) /* offset */ +#define SH7750_TCOR(n) SH7750_P4_REG32(SH7750_TCOR_REGOFS(n)) +#define SH7750_TCOR_A7(n) SH7750_A7_REG32(SH7750_TCOR_REGOFS(n)) +#define SH7750_TCOR0 SH7750_TCOR(0) +#define SH7750_TCOR1 SH7750_TCOR(1) +#define SH7750_TCOR2 SH7750_TCOR(2) +#define SH7750_TCOR0_A7 SH7750_TCOR_A7(0) +#define SH7750_TCOR1_A7 SH7750_TCOR_A7(1) +#define SH7750_TCOR2_A7 SH7750_TCOR_A7(2) + +/* Timer Counter Register - TCNT0, TCNT1, TCNT2 */ +#define SH7750_TCNT_REGOFS(n) (0xD8000C + ((n)*12)) /* offset */ +#define SH7750_TCNT(n) SH7750_P4_REG32(SH7750_TCNT_REGOFS(n)) +#define SH7750_TCNT_A7(n) SH7750_A7_REG32(SH7750_TCNT_REGOFS(n)) +#define SH7750_TCNT0 SH7750_TCNT(0) +#define SH7750_TCNT1 SH7750_TCNT(1) +#define SH7750_TCNT2 SH7750_TCNT(2) +#define SH7750_TCNT0_A7 SH7750_TCNT_A7(0) +#define SH7750_TCNT1_A7 SH7750_TCNT_A7(1) +#define SH7750_TCNT2_A7 SH7750_TCNT_A7(2) + +/* Timer Control Register (half) - TCR0, TCR1, TCR2 */ +#define SH7750_TCR_REGOFS(n) (0xD80010 + ((n)*12)) /* offset */ +#define SH7750_TCR(n) SH7750_P4_REG32(SH7750_TCR_REGOFS(n)) +#define SH7750_TCR_A7(n) SH7750_A7_REG32(SH7750_TCR_REGOFS(n)) +#define SH7750_TCR0 SH7750_TCR(0) +#define SH7750_TCR1 SH7750_TCR(1) +#define SH7750_TCR2 SH7750_TCR(2) +#define SH7750_TCR0_A7 SH7750_TCR_A7(0) +#define SH7750_TCR1_A7 SH7750_TCR_A7(1) +#define SH7750_TCR2_A7 SH7750_TCR_A7(2) + +#define SH7750_TCR2_ICPF 0x200 /* Input Capture Interrupt Flag + (1 - input capture has occured) */ +#define SH7750_TCR_UNF 0x100 /* Underflow flag */ +#define SH7750_TCR2_ICPE 0x0C0 /* Input Capture Control: */ +#define SH7750_TCR2_ICPE_DIS 0x000 /* Input Capture function is not used*/ +#define SH7750_TCR2_ICPE_NOINT 0x080 /* Input Capture function is used, but + input capture interrupt is not + enabled */ +#define SH7750_TCR2_ICPE_INT 0x0C0 /* Input Capture function is used, + input capture interrupt enabled */ +#define SH7750_TCR_UNIE 0x020 /* Underflow Interrupt Control + (1 - underflow interrupt enabled) */ +#define SH7750_TCR_CKEG 0x018 /* Clock Edge selection: */ +#define SH7750_TCR_CKEG_RAISE 0x000 /* Count/capture on rising edge */ +#define SH7750_TCR_CKEG_FALL 0x008 /* Count/capture on falling edge */ +#define SH7750_TCR_CKEG_BOTH 0x018 /* Count/capture on both rising and + falling edges */ +#define SH7750_TCR_TPSC 0x007 /* Timer prescaler */ +#define SH7750_TCR_TPSC_DIV4 0x000 /* Counts on peripheral clock/4 */ +#define SH7750_TCR_TPSC_DIV16 0x001 /* Counts on peripheral clock/16 */ +#define SH7750_TCR_TPSC_DIV64 0x002 /* Counts on peripheral clock/64 */ +#define SH7750_TCR_TPSC_DIV256 0x003 /* Counts on peripheral clock/256 */ +#define SH7750_TCR_TPSC_DIV1024 0x004 /* Counts on peripheral clock/1024 */ +#define SH7750_TCR_TPSC_RTC 0x006 /* Counts on on-chip RTC output clk*/ +#define SH7750_TCR_TPSC_EXT 0x007 /* Counts on external clock */ + +/* Input Capture Register (read-only) - TCPR2 */ +#define SH7750_TCPR2_REGOFS 0xD8002C /* offset */ +#define SH7750_TCPR2 SH7750_P4_REG32(SH7750_TCPR2_REGOFS) +#define SH7750_TCPR2_A7 SH7750_A7_REG32(SH7750_TCPR2_REGOFS) + +/* + * Bus State Controller - BSC + */ +/* Bus Control Register 1 - BCR1 */ +#define SH7750_BCR1_REGOFS 0x800000 /* offset */ +#define SH7750_BCR1 SH7750_P4_REG32(SH7750_BCR1_REGOFS) +#define SH7750_BCR1_A7 SH7750_A7_REG32(SH7750_BCR1_REGOFS) +#define SH7750_BCR1_ENDIAN 0x80000000 /* Endianness (1 - little endian) */ +#define SH7750_BCR1_MASTER 0x40000000 /* Master/Slave mode (1-master) */ +#define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX)*/ +#define SH7750_BCR1_IPUP 0x02000000 /* Input Pin Pull-up Control: + 0 - pull-up resistor is on for + control input pins + 1 - pull-up resistor is off */ +#define SH7750_BCR1_OPUP 0x01000000 /* Output Pin Pull-up Control: + 0 - pull-up resistor is on for + control output pins + 1 - pull-up resistor is off */ +#define SH7750_BCR1_A1MBC 0x00200000 /* Area 1 SRAM Byte Control Mode: + 0 - Area 1 SRAM is set to + normal mode + 1 - Area 1 SRAM is set to byte + control mode */ +#define SH7750_BCR1_A4MBC 0x00100000 /* Area 4 SRAM Byte Control Mode: + 0 - Area 4 SRAM is set to + normal mode + 1 - Area 4 SRAM is set to byte + control mode */ +#define SH7750_BCR1_BREQEN 0x00080000 /* BREQ Enable: + 0 - External requests are not + accepted + 1 - External requests are + accepted */ +#define SH7750_BCR1_PSHR 0x00040000 /* Partial Sharing Bit: + 0 - Master Mode + 1 - Partial-sharing Mode */ +#define SH7750_BCR1_MEMMPX 0x00020000 /* Area 1 to 6 MPX Interface: + 0 - SRAM/burst ROM interface + 1 - MPX interface */ +#define SH7750_BCR1_HIZMEM 0x00008000 /* High Impendance Control. Specifies + the state of A[25:0], BS\, CSn\, + RD/WR\, CE2A\, CE2B\ in standby + mode and when bus is released: + 0 - signals go to High-Z mode + 1 - signals driven */ +#define SH7750_BCR1_HIZCNT 0x00004000 /* High Impendance Control. Specifies + the state of the RAS\, RAS2\, WEn\, + CASn\, DQMn, RD\, CASS\, FRAME\, + RD2\ signals in standby mode and + when bus is released: + 0 - signals go to High-Z mode + 1 - signals driven */ +#define SH7750_BCR1_A0BST 0x00003800 /* Area 0 Burst ROM Control */ +#define SH7750_BCR1_A0BST_SRAM 0x0000 /* Area 0 accessed as SRAM i/f */ +#define SH7750_BCR1_A0BST_ROM4 0x0800 /* Area 0 accessed as burst ROM + interface, 4 cosequtive access*/ +#define SH7750_BCR1_A0BST_ROM8 0x1000 /* Area 0 accessed as burst ROM + interface, 8 cosequtive access*/ +#define SH7750_BCR1_A0BST_ROM16 0x1800 /* Area 0 accessed as burst ROM + interface, 16 cosequtive access*/ +#define SH7750_BCR1_A0BST_ROM32 0x2000 /* Area 0 accessed as burst ROM + interface, 32 cosequtive access*/ + +#define SH7750_BCR1_A5BST 0x00000700 /* Area 5 Burst ROM Control */ +#define SH7750_BCR1_A5BST_SRAM 0x0000 /* Area 5 accessed as SRAM i/f */ +#define SH7750_BCR1_A5BST_ROM4 0x0100 /* Area 5 accessed as burst ROM + interface, 4 cosequtive access*/ +#define SH7750_BCR1_A5BST_ROM8 0x0200 /* Area 5 accessed as burst ROM + interface, 8 cosequtive access*/ +#define SH7750_BCR1_A5BST_ROM16 0x0300 /* Area 5 accessed as burst ROM + interface, 16 cosequtive access*/ +#define SH7750_BCR1_A5BST_ROM32 0x0400 /* Area 5 accessed as burst ROM + interface, 32 cosequtive access*/ + +#define SH7750_BCR1_A6BST 0x000000E0 /* Area 6 Burst ROM Control */ +#define SH7750_BCR1_A6BST_SRAM 0x0000 /* Area 6 accessed as SRAM i/f */ +#define SH7750_BCR1_A6BST_ROM4 0x0020 /* Area 6 accessed as burst ROM + interface, 4 cosequtive access*/ +#define SH7750_BCR1_A6BST_ROM8 0x0040 /* Area 6 accessed as burst ROM + interface, 8 cosequtive access*/ +#define SH7750_BCR1_A6BST_ROM16 0x0060 /* Area 6 accessed as burst ROM + interface, 16 cosequtive access*/ +#define SH7750_BCR1_A6BST_ROM32 0x0080 /* Area 6 accessed as burst ROM + interface, 32 cosequtive access*/ + +#define SH7750_BCR1_DRAMTP 0x001C /* Area 2 and 3 Memory Type */ +#define SH7750_BCR1_DRAMTP_2SRAM_3SRAM 0x0000 /* Area 2 and 3 are SRAM or MPX + interface. */ +#define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM 0x0008 /* Area 2 - SRAM/MPX, Area 3 - + synchronous DRAM */ +#define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C /* Area 2 and 3 are synchronous + DRAM interface */ +#define SH7750_BCR1_DRAMTP_2SRAM_3DRAM 0x0010 /* Area 2 - SRAM/MPX, Area 3 - + DRAM interface */ +#define SH7750_BCR1_DRAMTP_2DRAM_3DRAM 0x0014 /* Area 2 and 3 are DRAM + interface */ + +#define SH7750_BCR1_A56PCM 0x00000001 /* Area 5 and 6 Bus Type: + 0 - SRAM interface + 1 - PCMCIA interface */ + +/* Bus Control Register 2 (half) - BCR2 */ +#define SH7750_BCR2_REGOFS 0x800004 /* offset */ +#define SH7750_BCR2 SH7750_P4_REG32(SH7750_BCR2_REGOFS) +#define SH7750_BCR2_A7 SH7750_A7_REG32(SH7750_BCR2_REGOFS) + +#define SH7750_BCR2_A0SZ 0xC000 /* Area 0 Bus Width */ +#define SH7750_BCR2_A0SZ_S 14 +#define SH7750_BCR2_A6SZ 0x3000 /* Area 6 Bus Width */ +#define SH7750_BCR2_A6SZ_S 12 +#define SH7750_BCR2_A5SZ 0x0C00 /* Area 5 Bus Width */ +#define SH7750_BCR2_A5SZ_S 10 +#define SH7750_BCR2_A4SZ 0x0300 /* Area 4 Bus Width */ +#define SH7750_BCR2_A4SZ_S 8 +#define SH7750_BCR2_A3SZ 0x00C0 /* Area 3 Bus Width */ +#define SH7750_BCR2_A3SZ_S 6 +#define SH7750_BCR2_A2SZ 0x0030 /* Area 2 Bus Width */ +#define SH7750_BCR2_A2SZ_S 4 +#define SH7750_BCR2_A1SZ 0x000C /* Area 1 Bus Width */ +#define SH7750_BCR2_A1SZ_S 2 +#define SH7750_BCR2_SZ_64 0 /* 64 bits */ +#define SH7750_BCR2_SZ_8 1 /* 8 bits */ +#define SH7750_BCR2_SZ_16 2 /* 16 bits */ +#define SH7750_BCR2_SZ_32 3 /* 32 bits */ +#define SH7750_BCR2_PORTEN 0x0001 /* Port Function Enable : + 0 - D51-D32 are not used as a port + 1 - D51-D32 are used as a port */ + +/* Wait Control Register 1 - WCR1 */ +#define SH7750_WCR1_REGOFS 0x800008 /* offset */ +#define SH7750_WCR1 SH7750_P4_REG32(SH7750_WCR1_REGOFS) +#define SH7750_WCR1_A7 SH7750_A7_REG32(SH7750_WCR1_REGOFS) +#define SH7750_WCR1_DMAIW 0x70000000 /* DACK Device Inter-Cycle Idle + specification */ +#define SH7750_WCR1_DMAIW_S 28 +#define SH7750_WCR1_A6IW 0x07000000 /* Area 6 Inter-Cycle Idle spec. */ +#define SH7750_WCR1_A6IW_S 24 +#define SH7750_WCR1_A5IW 0x00700000 /* Area 5 Inter-Cycle Idle spec. */ +#define SH7750_WCR1_A5IW_S 20 +#define SH7750_WCR1_A4IW 0x00070000 /* Area 4 Inter-Cycle Idle spec. */ +#define SH7750_WCR1_A4IW_S 16 +#define SH7750_WCR1_A3IW 0x00007000 /* Area 3 Inter-Cycle Idle spec. */ +#define SH7750_WCR1_A3IW_S 12 +#define SH7750_WCR1_A2IW 0x00000700 /* Area 2 Inter-Cycle Idle spec. */ +#define SH7750_WCR1_A2IW_S 8 +#define SH7750_WCR1_A1IW 0x00000070 /* Area 1 Inter-Cycle Idle spec. */ +#define SH7750_WCR1_A1IW_S 4 +#define SH7750_WCR1_A0IW 0x00000007 /* Area 0 Inter-Cycle Idle spec. */ +#define SH7750_WCR1_A0IW_S 0 + +/* Wait Control Register 2 - WCR2 */ +#define SH7750_WCR2_REGOFS 0x80000C /* offset */ +#define SH7750_WCR2 SH7750_P4_REG32(SH7750_WCR2_REGOFS) +#define SH7750_WCR2_A7 SH7750_A7_REG32(SH7750_WCR2_REGOFS) + +#define SH7750_WCR2_A6W 0xE0000000 /* Area 6 Wait Control */ +#define SH7750_WCR2_A6W_S 29 +#define SH7750_WCR2_A6B 0x1C000000 /* Area 6 Burst Pitch */ +#define SH7750_WCR2_A6B_S 26 +#define SH7750_WCR2_A5W 0x03800000 /* Area 5 Wait Control */ +#define SH7750_WCR2_A5W_S 23 +#define SH7750_WCR2_A5B 0x00700000 /* Area 5 Burst Pitch */ +#define SH7750_WCR2_A5B_S 20 +#define SH7750_WCR2_A4W 0x000E0000 /* Area 4 Wait Control */ +#define SH7750_WCR2_A4W_S 17 +#define SH7750_WCR2_A3W 0x0000E000 /* Area 3 Wait Control */ +#define SH7750_WCR2_A3W_S 13 +#define SH7750_WCR2_A2W 0x00000E00 /* Area 2 Wait Control */ +#define SH7750_WCR2_A2W_S 9 +#define SH7750_WCR2_A1W 0x000001C0 /* Area 1 Wait Control */ +#define SH7750_WCR2_A1W_S 6 +#define SH7750_WCR2_A0W 0x00000038 /* Area 0 Wait Control */ +#define SH7750_WCR2_A0W_S 3 +#define SH7750_WCR2_A0B 0x00000007 /* Area 0 Burst Pitch */ +#define SH7750_WCR2_A0B_S 0 + +#define SH7750_WCR2_WS0 0 /* 0 wait states inserted */ +#define SH7750_WCR2_WS1 1 /* 1 wait states inserted */ +#define SH7750_WCR2_WS2 2 /* 2 wait states inserted */ +#define SH7750_WCR2_WS3 3 /* 3 wait states inserted */ +#define SH7750_WCR2_WS6 4 /* 6 wait states inserted */ +#define SH7750_WCR2_WS9 5 /* 9 wait states inserted */ +#define SH7750_WCR2_WS12 6 /* 12 wait states inserted */ +#define SH7750_WCR2_WS15 7 /* 15 wait states inserted */ + +#define SH7750_WCR2_BPWS0 0 /* 0 wait states inserted from 2nd access */ +#define SH7750_WCR2_BPWS1 1 /* 1 wait states inserted from 2nd access */ +#define SH7750_WCR2_BPWS2 2 /* 2 wait states inserted from 2nd access */ +#define SH7750_WCR2_BPWS3 3 /* 3 wait states inserted from 2nd access */ +#define SH7750_WCR2_BPWS4 4 /* 4 wait states inserted from 2nd access */ +#define SH7750_WCR2_BPWS5 5 /* 5 wait states inserted from 2nd access */ +#define SH7750_WCR2_BPWS6 6 /* 6 wait states inserted from 2nd access */ +#define SH7750_WCR2_BPWS7 7 /* 7 wait states inserted from 2nd access */ + +/* DRAM CAS\ Assertion Delay (area 3,2) */ +#define SH7750_WCR2_DRAM_CAS_ASW1 0 /* 1 cycle */ +#define SH7750_WCR2_DRAM_CAS_ASW2 1 /* 2 cycles */ +#define SH7750_WCR2_DRAM_CAS_ASW3 2 /* 3 cycles */ +#define SH7750_WCR2_DRAM_CAS_ASW4 3 /* 4 cycles */ +#define SH7750_WCR2_DRAM_CAS_ASW7 4 /* 7 cycles */ +#define SH7750_WCR2_DRAM_CAS_ASW10 5 /* 10 cycles */ +#define SH7750_WCR2_DRAM_CAS_ASW13 6 /* 13 cycles */ +#define SH7750_WCR2_DRAM_CAS_ASW16 7 /* 16 cycles */ + +/* SDRAM CAS\ Latency Cycles */ +#define SH7750_WCR2_SDRAM_CAS_LAT1 1 /* 1 cycle */ +#define SH7750_WCR2_SDRAM_CAS_LAT2 2 /* 2 cycles */ +#define SH7750_WCR2_SDRAM_CAS_LAT3 3 /* 3 cycles */ +#define SH7750_WCR2_SDRAM_CAS_LAT4 4 /* 4 cycles */ +#define SH7750_WCR2_SDRAM_CAS_LAT5 5 /* 5 cycles */ + +/* Wait Control Register 3 - WCR3 */ +#define SH7750_WCR3_REGOFS 0x800010 /* offset */ +#define SH7750_WCR3 SH7750_P4_REG32(SH7750_WCR3_REGOFS) +#define SH7750_WCR3_A7 SH7750_A7_REG32(SH7750_WCR3_REGOFS) + +#define SH7750_WCR3_A6S 0x04000000 /* Area 6 Write Strobe Setup time */ +#define SH7750_WCR3_A6H 0x03000000 /* Area 6 Data Hold Time */ +#define SH7750_WCR3_A6H_S 24 +#define SH7750_WCR3_A5S 0x00400000 /* Area 5 Write Strobe Setup time */ +#define SH7750_WCR3_A5H 0x00300000 /* Area 5 Data Hold Time */ +#define SH7750_WCR3_A5H_S 20 +#define SH7750_WCR3_A4S 0x00040000 /* Area 4 Write Strobe Setup time */ +#define SH7750_WCR3_A4H 0x00030000 /* Area 4 Data Hold Time */ +#define SH7750_WCR3_A4H_S 16 +#define SH7750_WCR3_A3S 0x00004000 /* Area 3 Write Strobe Setup time */ +#define SH7750_WCR3_A3H 0x00003000 /* Area 3 Data Hold Time */ +#define SH7750_WCR3_A3H_S 12 +#define SH7750_WCR3_A2S 0x00000400 /* Area 2 Write Strobe Setup time */ +#define SH7750_WCR3_A2H 0x00000300 /* Area 2 Data Hold Time */ +#define SH7750_WCR3_A2H_S 8 +#define SH7750_WCR3_A1S 0x00000040 /* Area 1 Write Strobe Setup time */ +#define SH7750_WCR3_A1H 0x00000030 /* Area 1 Data Hold Time */ +#define SH7750_WCR3_A1H_S 4 +#define SH7750_WCR3_A0S 0x00000004 /* Area 0 Write Strobe Setup time */ +#define SH7750_WCR3_A0H 0x00000003 /* Area 0 Data Hold Time */ +#define SH7750_WCR3_A0H_S 0 + +#define SH7750_WCR3_DHWS_0 0 /* 0 wait states data hold time */ +#define SH7750_WCR3_DHWS_1 1 /* 1 wait states data hold time */ +#define SH7750_WCR3_DHWS_2 2 /* 2 wait states data hold time */ +#define SH7750_WCR3_DHWS_3 3 /* 3 wait states data hold time */ + +#define SH7750_MCR_REGOFS 0x800014 /* offset */ +#define SH7750_MCR SH7750_P4_REG32(SH7750_MCR_REGOFS) +#define SH7750_MCR_A7 SH7750_A7_REG32(SH7750_MCR_REGOFS) + +#define SH7750_MCR_RASD 0x80000000 /* RAS Down mode */ +#define SH7750_MCR_MRSET 0x40000000 /* SDRAM Mode Register Set */ +#define SH7750_MCR_PALL 0x00000000 /* SDRAM Precharge All cmd. Mode */ +#define SH7750_MCR_TRC 0x38000000 /* RAS Precharge Time at End of + Refresh: */ +#define SH7750_MCR_TRC_0 0x00000000 /* 0 */ +#define SH7750_MCR_TRC_3 0x08000000 /* 3 */ +#define SH7750_MCR_TRC_6 0x10000000 /* 6 */ +#define SH7750_MCR_TRC_9 0x18000000 /* 9 */ +#define SH7750_MCR_TRC_12 0x20000000 /* 12 */ +#define SH7750_MCR_TRC_15 0x28000000 /* 15 */ +#define SH7750_MCR_TRC_18 0x30000000 /* 18 */ +#define SH7750_MCR_TRC_21 0x38000000 /* 21 */ + +#define SH7750_MCR_TCAS 0x00800000 /* CAS Negation Period */ +#define SH7750_MCR_TCAS_1 0x00000000 /* 1 */ +#define SH7750_MCR_TCAS_2 0x00800000 /* 2 */ + +#define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period + SDRAM: minimum number of cycles + until the next bank active cmd + is output after precharging */ +#define SH7750_MCR_TPC_S 19 +#define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */ +#define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */ +#define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */ +#define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */ +#define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */ +#define SH7750_MCR_TPC_SDRAM_6 0x00280000 /* 6 cycles */ +#define SH7750_MCR_TPC_SDRAM_7 0x00300000 /* 7 cycles */ +#define SH7750_MCR_TPC_SDRAM_8 0x00380000 /* 8 cycles */ + +#define SH7750_MCR_RCD 0x00030000 /* DRAM: RAS-CAS Assertion Delay time + SDRAM: bank active-read/write cmd + delay time */ +#define SH7750_MCR_RCD_DRAM_2 0x00000000 /* DRAM delay 2 clocks */ +#define SH7750_MCR_RCD_DRAM_3 0x00010000 /* DRAM delay 3 clocks */ +#define SH7750_MCR_RCD_DRAM_4 0x00020000 /* DRAM delay 4 clocks */ +#define SH7750_MCR_RCD_DRAM_5 0x00030000 /* DRAM delay 5 clocks */ +#define SH7750_MCR_RCD_SDRAM_2 0x00010000 /* DRAM delay 2 clocks */ +#define SH7750_MCR_RCD_SDRAM_3 0x00020000 /* DRAM delay 3 clocks */ +#define SH7750_MCR_RCD_SDRAM_4 0x00030000 /* DRAM delay 4 clocks */ + +#define SH7750_MCR_TRWL 0x0000E000 /* SDRAM Write Precharge Delay */ +#define SH7750_MCR_TRWL_1 0x00000000 /* 1 */ +#define SH7750_MCR_TRWL_2 0x00002000 /* 2 */ +#define SH7750_MCR_TRWL_3 0x00004000 /* 3 */ +#define SH7750_MCR_TRWL_4 0x00006000 /* 4 */ +#define SH7750_MCR_TRWL_5 0x00008000 /* 5 */ + +#define SH7750_MCR_TRAS 0x00001C00 /* DRAM: CAS-Before-RAS Refresh RAS + asserting period + SDRAM: Command interval after + synchronous DRAM refresh */ +#define SH7750_MCR_TRAS_DRAM_2 0x00000000 /* 2 */ +#define SH7750_MCR_TRAS_DRAM_3 0x00000400 /* 3 */ +#define SH7750_MCR_TRAS_DRAM_4 0x00000800 /* 4 */ +#define SH7750_MCR_TRAS_DRAM_5 0x00000C00 /* 5 */ +#define SH7750_MCR_TRAS_DRAM_6 0x00001000 /* 6 */ +#define SH7750_MCR_TRAS_DRAM_7 0x00001400 /* 7 */ +#define SH7750_MCR_TRAS_DRAM_8 0x00001800 /* 8 */ +#define SH7750_MCR_TRAS_DRAM_9 0x00001C00 /* 9 */ + +#define SH7750_MCR_TRAS_SDRAM_TRC_4 0x00000000 /* 4 + TRC */ +#define SH7750_MCR_TRAS_SDRAM_TRC_5 0x00000400 /* 5 + TRC */ +#define SH7750_MCR_TRAS_SDRAM_TRC_6 0x00000800 /* 6 + TRC */ +#define SH7750_MCR_TRAS_SDRAM_TRC_7 0x00000C00 /* 7 + TRC */ +#define SH7750_MCR_TRAS_SDRAM_TRC_8 0x00001000 /* 8 + TRC */ +#define SH7750_MCR_TRAS_SDRAM_TRC_9 0x00001400 /* 9 + TRC */ +#define SH7750_MCR_TRAS_SDRAM_TRC_10 0x00001800 /* 10 + TRC */ +#define SH7750_MCR_TRAS_SDRAM_TRC_11 0x00001C00 /* 11 + TRC */ + +#define SH7750_MCR_BE 0x00000200 /* Burst Enable */ +#define SH7750_MCR_SZ 0x00000180 /* Memory Data Size */ +#define SH7750_MCR_SZ_64 0x00000000 /* 64 bits */ +#define SH7750_MCR_SZ_16 0x00000100 /* 16 bits */ +#define SH7750_MCR_SZ_32 0x00000180 /* 32 bits */ + +#define SH7750_MCR_AMX 0x00000078 /* Address Multiplexing */ +#define SH7750_MCR_AMX_S 3 +#define SH7750_MCR_AMX_DRAM_8BIT_COL 0x00000000 /* 8-bit column addr */ +#define SH7750_MCR_AMX_DRAM_9BIT_COL 0x00000008 /* 9-bit column addr */ +#define SH7750_MCR_AMX_DRAM_10BIT_COL 0x00000010 /* 10-bit column addr */ +#define SH7750_MCR_AMX_DRAM_11BIT_COL 0x00000018 /* 11-bit column addr */ +#define SH7750_MCR_AMX_DRAM_12BIT_COL 0x00000020 /* 12-bit column addr */ +/* See SH7750 Hardware Manual for SDRAM address multiplexor selection */ + +#define SH7750_MCR_RFSH 0x00000004 /* Refresh Control */ +#define SH7750_MCR_RMODE 0x00000002 /* Refresh Mode: */ +#define SH7750_MCR_RMODE_NORMAL 0x00000000 /* Normal Refresh Mode */ +#define SH7750_MCR_RMODE_SELF 0x00000002 /* Self-Refresh Mode */ +#define SH7750_MCR_RMODE_EDO 0x00000001 /* EDO Mode */ + +/* SDRAM Mode Set address */ +#define SH7750_SDRAM_MODE_A2_BASE 0xFF900000 +#define SH7750_SDRAM_MODE_A3_BASE 0xFF940000 +#define SH7750_SDRAM_MODE_A2_32BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 2)) +#define SH7750_SDRAM_MODE_A3_32BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 2)) +#define SH7750_SDRAM_MODE_A2_64BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 3)) +#define SH7750_SDRAM_MODE_A3_64BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 3)) + + +/* PCMCIA Control Register (half) - PCR */ +#define SH7750_PCR_REGOFS 0x800018 /* offset */ +#define SH7750_PCR SH7750_P4_REG32(SH7750_PCR_REGOFS) +#define SH7750_PCR_A7 SH7750_A7_REG32(SH7750_PCR_REGOFS) + +#define SH7750_PCR_A5PCW 0xC000 /* Area 5 PCMCIA Wait - Number of wait + states to be added to the number of + waits specified by WCR2 in a low-speed + PCMCIA wait cycle */ +#define SH7750_PCR_A5PCW_0 0x0000 /* 0 waits inserted */ +#define SH7750_PCR_A5PCW_15 0x4000 /* 15 waits inserted */ +#define SH7750_PCR_A5PCW_30 0x8000 /* 30 waits inserted */ +#define SH7750_PCR_A5PCW_50 0xC000 /* 50 waits inserted */ + +#define SH7750_PCR_A6PCW 0x3000 /* Area 6 PCMCIA Wait - Number of wait + states to be added to the number of + waits specified by WCR2 in a low-speed + PCMCIA wait cycle */ +#define SH7750_PCR_A6PCW_0 0x0000 /* 0 waits inserted */ +#define SH7750_PCR_A6PCW_15 0x1000 /* 15 waits inserted */ +#define SH7750_PCR_A6PCW_30 0x2000 /* 30 waits inserted */ +#define SH7750_PCR_A6PCW_50 0x3000 /* 50 waits inserted */ + +#define SH7750_PCR_A5TED 0x0E00 /* Area 5 Address-OE\/WE\ Assertion Delay, + delay time from address output to + OE\/WE\ assertion on the connected + PCMCIA interface */ +#define SH7750_PCR_A5TED_S 9 +#define SH7750_PCR_A6TED 0x01C0 /* Area 6 Address-OE\/WE\ Assertion Delay*/ +#define SH7750_PCR_A6TED_S 6 + +#define SH7750_PCR_TED_0WS 0 /* 0 Waits inserted */ +#define SH7750_PCR_TED_1WS 1 /* 1 Waits inserted */ +#define SH7750_PCR_TED_2WS 2 /* 2 Waits inserted */ +#define SH7750_PCR_TED_3WS 3 /* 3 Waits inserted */ +#define SH7750_PCR_TED_6WS 4 /* 6 Waits inserted */ +#define SH7750_PCR_TED_9WS 5 /* 9 Waits inserted */ +#define SH7750_PCR_TED_12WS 6 /* 12 Waits inserted */ +#define SH7750_PCR_TED_15WS 7 /* 15 Waits inserted */ + +#define SH7750_PCR_A5TEH 0x0038 /* Area 5 OE\/WE\ Negation Address delay, + address hold delay time from OE\/WE\ + negation in a write on the connected + PCMCIA interface */ +#define SH7750_PCR_A5TEH_S 3 + +#define SH7750_PCR_A6TEH 0x0007 /* Area 6 OE\/WE\ Negation Address delay*/ +#define SH7750_PCR_A6TEH_S 0 + +#define SH7750_PCR_TEH_0WS 0 /* 0 Waits inserted */ +#define SH7750_PCR_TEH_1WS 1 /* 1 Waits inserted */ +#define SH7750_PCR_TEH_2WS 2 /* 2 Waits inserted */ +#define SH7750_PCR_TEH_3WS 3 /* 3 Waits inserted */ +#define SH7750_PCR_TEH_6WS 4 /* 6 Waits inserted */ +#define SH7750_PCR_TEH_9WS 5 /* 9 Waits inserted */ +#define SH7750_PCR_TEH_12WS 6 /* 12 Waits inserted */ +#define SH7750_PCR_TEH_15WS 7 /* 15 Waits inserted */ + +/* Refresh Timer Control/Status Register (half) - RTSCR */ +#define SH7750_RTCSR_REGOFS 0x80001C /* offset */ +#define SH7750_RTCSR SH7750_P4_REG32(SH7750_RTCSR_REGOFS) +#define SH7750_RTCSR_A7 SH7750_A7_REG32(SH7750_RTCSR_REGOFS) + +#define SH7750_RTCSR_KEY 0xA500 /* RTCSR write key */ +#define SH7750_RTCSR_CMF 0x0080 /* Compare-Match Flag (indicates a + match between the refresh timer + counter and refresh time constant) */ +#define SH7750_RTCSR_CMIE 0x0040 /* Compare-Match Interrupt Enable */ +#define SH7750_RTCSR_CKS 0x0038 /* Refresh Counter Clock Selects */ +#define SH7750_RTCSR_CKS_DIS 0x0000 /* Clock Input Disabled */ +#define SH7750_RTCSR_CKS_CKIO_DIV4 0x0008 /* Bus Clock / 4 */ +#define SH7750_RTCSR_CKS_CKIO_DIV16 0x0010 /* Bus Clock / 16 */ +#define SH7750_RTCSR_CKS_CKIO_DIV64 0x0018 /* Bus Clock / 64 */ +#define SH7750_RTCSR_CKS_CKIO_DIV256 0x0020 /* Bus Clock / 256 */ +#define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028 /* Bus Clock / 1024 */ +#define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030 /* Bus Clock / 2048 */ +#define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038 /* Bus Clock / 4096 */ + +#define SH7750_RTCSR_OVF 0x0004 /* Refresh Count Overflow Flag */ +#define SH7750_RTCSR_OVIE 0x0002 /* Refresh Count Overflow Interrupt + Enable */ +#define SH7750_RTCSR_LMTS 0x0001 /* Refresh Count Overflow Limit Select */ +#define SH7750_RTCSR_LMTS_1024 0x0000 /* Count Limit is 1024 */ +#define SH7750_RTCSR_LMTS_512 0x0001 /* Count Limit is 512 */ + +/* Refresh Timer Counter (half) - RTCNT */ +#define SH7750_RTCNT_REGOFS 0x800020 /* offset */ +#define SH7750_RTCNT SH7750_P4_REG32(SH7750_RTCNT_REGOFS) +#define SH7750_RTCNT_A7 SH7750_A7_REG32(SH7750_RTCNT_REGOFS) + +#define SH7750_RTCNT_KEY 0xA500 /* RTCNT write key */ + +/* Refresh Time Constant Register (half) - RTCOR */ +#define SH7750_RTCOR_REGOFS 0x800024 /* offset */ +#define SH7750_RTCOR SH7750_P4_REG32(SH7750_RTCOR_REGOFS) +#define SH7750_RTCOR_A7 SH7750_A7_REG32(SH7750_RTCOR_REGOFS) + +#define SH7750_RTCOR_KEY 0xA500 /* RTCOR write key */ + +/* Refresh Count Register (half) - RFCR */ +#define SH7750_RFCR_REGOFS 0x800028 /* offset */ +#define SH7750_RFCR SH7750_P4_REG32(SH7750_RFCR_REGOFS) +#define SH7750_RFCR_A7 SH7750_A7_REG32(SH7750_RFCR_REGOFS) + +#define SH7750_RFCR_KEY 0xA400 /* RFCR write key */ + +/* + * Direct Memory Access Controller (DMAC) + */ + +/* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */ +#define SH7750_SAR_REGOFS(n) (0xA00000 + ((n)*16)) /* offset */ +#define SH7750_SAR(n) SH7750_P4_REG32(SH7750_SAR_REGOFS(n)) +#define SH7750_SAR_A7(n) SH7750_A7_REG32(SH7750_SAR_REGOFS(n)) +#define SH7750_SAR0 SH7750_SAR(0) +#define SH7750_SAR1 SH7750_SAR(1) +#define SH7750_SAR2 SH7750_SAR(2) +#define SH7750_SAR3 SH7750_SAR(3) +#define SH7750_SAR0_A7 SH7750_SAR_A7(0) +#define SH7750_SAR1_A7 SH7750_SAR_A7(1) +#define SH7750_SAR2_A7 SH7750_SAR_A7(2) +#define SH7750_SAR3_A7 SH7750_SAR_A7(3) + +/* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */ +#define SH7750_DAR_REGOFS(n) (0xA00004 + ((n)*16)) /* offset */ +#define SH7750_DAR(n) SH7750_P4_REG32(SH7750_DAR_REGOFS(n)) +#define SH7750_DAR_A7(n) SH7750_A7_REG32(SH7750_DAR_REGOFS(n)) +#define SH7750_DAR0 SH7750_DAR(0) +#define SH7750_DAR1 SH7750_DAR(1) +#define SH7750_DAR2 SH7750_DAR(2) +#define SH7750_DAR3 SH7750_DAR(3) +#define SH7750_DAR0_A7 SH7750_DAR_A7(0) +#define SH7750_DAR1_A7 SH7750_DAR_A7(1) +#define SH7750_DAR2_A7 SH7750_DAR_A7(2) +#define SH7750_DAR3_A7 SH7750_DAR_A7(3) + +/* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */ +#define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n)*16)) /* offset */ +#define SH7750_DMATCR(n) SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n)) +#define SH7750_DMATCR_A7(n) SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n)) +#define SH7750_DMATCR0_P4 SH7750_DMATCR(0) +#define SH7750_DMATCR1_P4 SH7750_DMATCR(1) +#define SH7750_DMATCR2_P4 SH7750_DMATCR(2) +#define SH7750_DMATCR3_P4 SH7750_DMATCR(3) +#define SH7750_DMATCR0_A7 SH7750_DMATCR_A7(0) +#define SH7750_DMATCR1_A7 SH7750_DMATCR_A7(1) +#define SH7750_DMATCR2_A7 SH7750_DMATCR_A7(2) +#define SH7750_DMATCR3_A7 SH7750_DMATCR_A7(3) + +/* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */ +#define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n)*16)) /* offset */ +#define SH7750_CHCR(n) SH7750_P4_REG32(SH7750_CHCR_REGOFS(n)) +#define SH7750_CHCR_A7(n) SH7750_A7_REG32(SH7750_CHCR_REGOFS(n)) +#define SH7750_CHCR0 SH7750_CHCR(0) +#define SH7750_CHCR1 SH7750_CHCR(1) +#define SH7750_CHCR2 SH7750_CHCR(2) +#define SH7750_CHCR3 SH7750_CHCR(3) +#define SH7750_CHCR0_A7 SH7750_CHCR_A7(0) +#define SH7750_CHCR1_A7 SH7750_CHCR_A7(1) +#define SH7750_CHCR2_A7 SH7750_CHCR_A7(2) +#define SH7750_CHCR3_A7 SH7750_CHCR_A7(3) + +#define SH7750_CHCR_SSA 0xE0000000 /* Source Address Space Attribute */ +#define SH7750_CHCR_SSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */ +#define SH7750_CHCR_SSA_DYNBSZ 0x20000000 /* Dynamic Bus Sizing I/O space */ +#define SH7750_CHCR_SSA_IO8 0x40000000 /* 8-bit I/O space */ +#define SH7750_CHCR_SSA_IO16 0x60000000 /* 16-bit I/O space */ +#define SH7750_CHCR_SSA_CMEM8 0x80000000 /* 8-bit common memory space */ +#define SH7750_CHCR_SSA_CMEM16 0xA0000000 /* 16-bit common memory space */ +#define SH7750_CHCR_SSA_AMEM8 0xC0000000 /* 8-bit attribute memory space */ +#define SH7750_CHCR_SSA_AMEM16 0xE0000000 /* 16-bit attribute memory space */ + +#define SH7750_CHCR_STC 0x10000000 /* Source Address Wait Control Select, + specifies CS5 or CS6 space wait + control for PCMCIA access */ + +#define SH7750_CHCR_DSA 0x0E000000 /* Source Address Space Attribute */ +#define SH7750_CHCR_DSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */ +#define SH7750_CHCR_DSA_DYNBSZ 0x02000000 /* Dynamic Bus Sizing I/O space */ +#define SH7750_CHCR_DSA_IO8 0x04000000 /* 8-bit I/O space */ +#define SH7750_CHCR_DSA_IO16 0x06000000 /* 16-bit I/O space */ +#define SH7750_CHCR_DSA_CMEM8 0x08000000 /* 8-bit common memory space */ +#define SH7750_CHCR_DSA_CMEM16 0x0A000000 /* 16-bit common memory space */ +#define SH7750_CHCR_DSA_AMEM8 0x0C000000 /* 8-bit attribute memory space */ +#define SH7750_CHCR_DSA_AMEM16 0x0E000000 /* 16-bit attribute memory space */ + +#define SH7750_CHCR_DTC 0x01000000 /* Destination Address Wait Control + Select, specifies CS5 or CS6 + space wait control for PCMCIA + access */ + +#define SH7750_CHCR_DS 0x00080000 /* DREQ\ Select : */ +#define SH7750_CHCR_DS_LOWLVL 0x00000000 /* Low Level Detection */ +#define SH7750_CHCR_DS_FALL 0x00080000 /* Falling Edge Detection */ + +#define SH7750_CHCR_RL 0x00040000 /* Request Check Level: */ +#define SH7750_CHCR_RL_ACTH 0x00000000 /* DRAK is an active high out */ +#define SH7750_CHCR_RL_ACTL 0x00040000 /* DRAK is an active low out */ + +#define SH7750_CHCR_AM 0x00020000 /* Acknowledge Mode: */ +#define SH7750_CHCR_AM_RD 0x00000000 /* DACK is output in read cycle */ +#define SH7750_CHCR_AM_WR 0x00020000 /* DACK is output in write cycle*/ + +#define SH7750_CHCR_AL 0x00010000 /* Acknowledge Level: */ +#define SH7750_CHCR_AL_ACTH 0x00000000 /* DACK is an active high out */ +#define SH7750_CHCR_AL_ACTL 0x00010000 /* DACK is an active low out */ + +#define SH7750_CHCR_DM 0x0000C000 /* Destination Address Mode: */ +#define SH7750_CHCR_DM_FIX 0x00000000 /* Destination Addr Fixed */ +#define SH7750_CHCR_DM_INC 0x00004000 /* Destination Addr Incremented */ +#define SH7750_CHCR_DM_DEC 0x00008000 /* Destination Addr Decremented */ + +#define SH7750_CHCR_SM 0x00003000 /* Source Address Mode: */ +#define SH7750_CHCR_SM_FIX 0x00000000 /* Source Addr Fixed */ +#define SH7750_CHCR_SM_INC 0x00001000 /* Source Addr Incremented */ +#define SH7750_CHCR_SM_DEC 0x00002000 /* Source Addr Decremented */ + +#define SH7750_CHCR_RS 0x00000F00 /* Request Source Select: */ +#define SH7750_CHCR_RS_ER_DA_EA_TO_EA 0x000 /* External Request, Dual Address + Mode (External Addr Space-> + External Addr Space) */ +#define SH7750_CHCR_RS_ER_SA_EA_TO_ED 0x200 /* External Request, Single + Address Mode (External Addr + Space -> External Device) */ +#define SH7750_CHCR_RS_ER_SA_ED_TO_EA 0x300 /* External Request, Single + Address Mode, (External + Device -> External Addr + Space)*/ +#define SH7750_CHCR_RS_AR_EA_TO_EA 0x400 /* Auto-Request (External Addr + Space -> External Addr Space)*/ + +#define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500 /* Auto-Request (External Addr + Space -> On-chip Peripheral + Module) */ +#define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip + Peripheral Module -> + External Addr Space */ +#define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800 /* SCI Transmit-Data-Empty intr + transfer request (external + address space -> SCTDR1) */ +#define SH7750_CHCR_RS_SCIRX_SC_TO_EA 0x900 /* SCI Receive-Data-Full intr + transfer request (SCRDR1 -> + External Addr Space) */ +#define SH7750_CHCR_RS_SCIFTX_EA_TO_SC 0xA00 /* SCIF Transmit-Data-Empty intr + transfer request (external + address space -> SCFTDR1) */ +#define SH7750_CHCR_RS_SCIFRX_SC_TO_EA 0xB00 /* SCIF Receive-Data-Full intr + transfer request (SCFRDR2 -> + External Addr Space) */ +#define SH7750_CHCR_RS_TMU2_EA_TO_EA 0xC00 /* TMU Channel 2 (input capture + interrupt), (external address + space -> external address + space) */ +#define SH7750_CHCR_RS_TMU2_EA_TO_OCP 0xD00 /* TMU Channel 2 (input capture + interrupt), (external address + space -> on-chip peripheral + module) */ +#define SH7750_CHCR_RS_TMU2_OCP_TO_EA 0xE00 /* TMU Channel 2 (input capture + interrupt), (on-chip + peripheral module -> external + address space) */ + +#define SH7750_CHCR_TM 0x00000080 /* Transmit mode: */ +#define SH7750_CHCR_TM_CSTEAL 0x00000000 /* Cycle Steal Mode */ +#define SH7750_CHCR_TM_BURST 0x00000080 /* Burst Mode */ + +#define SH7750_CHCR_TS 0x00000070 /* Transmit Size: */ +#define SH7750_CHCR_TS_QUAD 0x00000000 /* Quadword Size (64 bits) */ +#define SH7750_CHCR_TS_BYTE 0x00000010 /* Byte Size (8 bit) */ +#define SH7750_CHCR_TS_WORD 0x00000020 /* Word Size (16 bit) */ +#define SH7750_CHCR_TS_LONG 0x00000030 /* Longword Size (32 bit) */ +#define SH7750_CHCR_TS_BLOCK 0x00000040 /* 32-byte block transfer */ + +#define SH7750_CHCR_IE 0x00000004 /* Interrupt Enable */ +#define SH7750_CHCR_TE 0x00000002 /* Transfer End */ +#define SH7750_CHCR_DE 0x00000001 /* DMAC Enable */ + +/* DMA Operation Register - DMAOR */ +#define SH7750_DMAOR_REGOFS 0xA00040 /* offset */ +#define SH7750_DMAOR SH7750_P4_REG32(SH7750_DMAOR_REGOFS) +#define SH7750_DMAOR_A7 SH7750_A7_REG32(SH7750_DMAOR_REGOFS) + +#define SH7750_DMAOR_DDT 0x00008000 /* On-Demand Data Transfer Mode */ + +#define SH7750_DMAOR_PR 0x00000300 /* Priority Mode: */ +#define SH7750_DMAOR_PR_0123 0x00000000 /* CH0 > CH1 > CH2 > CH3 */ +#define SH7750_DMAOR_PR_0231 0x00000100 /* CH0 > CH2 > CH3 > CH1 */ +#define SH7750_DMAOR_PR_2013 0x00000200 /* CH2 > CH0 > CH1 > CH3 */ +#define SH7750_DMAOR_PR_RR 0x00000300 /* Round-robin mode */ + +#define SH7750_DMAOR_COD 0x00000010 /* Check Overrun for DREQ\ */ +#define SH7750_DMAOR_AE 0x00000004 /* Address Error flag */ +#define SH7750_DMAOR_NMIF 0x00000002 /* NMI Flag */ +#define SH7750_DMAOR_DME 0x00000001 /* DMAC Master Enable */ + +/* + * Serial Communication Interface - SCI + * Serial Communication Interface with FIFO - SCIF + */ +/* SCI Receive Data Register (byte, read-only) - SCRDR1, SCFRDR2 */ +#define SH7750_SCRDR_REGOFS(n) ((n) == 1 ? 0xE00014 : 0xE80014) /* offset */ +#define SH7750_SCRDR(n) SH7750_P4_REG32(SH7750_SCRDR_REGOFS(n)) +#define SH7750_SCRDR1 SH7750_SCRDR(1) +#define SH7750_SCRDR2 SH7750_SCRDR(2) +#define SH7750_SCRDR_A7(n) SH7750_A7_REG32(SH7750_SCRDR_REGOFS(n)) +#define SH7750_SCRDR1_A7 SH7750_SCRDR_A7(1) +#define SH7750_SCRDR2_A7 SH7750_SCRDR_A7(2) + +/* SCI Transmit Data Register (byte) - SCTDR1, SCFTDR2 */ +#define SH7750_SCTDR_REGOFS(n) ((n) == 1 ? 0xE0000C : 0xE8000C) /* offset */ +#define SH7750_SCTDR(n) SH7750_P4_REG32(SH7750_SCTDR_REGOFS(n)) +#define SH7750_SCTDR1 SH7750_SCTDR(1) +#define SH7750_SCTDR2 SH7750_SCTDR(2) +#define SH7750_SCTDR_A7(n) SH7750_A7_REG32(SH7750_SCTDR_REGOFS(n)) +#define SH7750_SCTDR1_A7 SH7750_SCTDR_A7(1) +#define SH7750_SCTDR2_A7 SH7750_SCTDR_A7(2) + +/* SCI Serial Mode Register - SCSMR1(byte), SCSMR2(half) */ +#define SH7750_SCSMR_REGOFS(n) ((n) == 1 ? 0xE00000 : 0xE80000) /* offset */ +#define SH7750_SCSMR(n) SH7750_P4_REG32(SH7750_SCSMR_REGOFS(n)) +#define SH7750_SCSMR1 SH7750_SCSMR(1) +#define SH7750_SCSMR2 SH7750_SCSMR(2) +#define SH7750_SCSMR_A7(n) SH7750_A7_REG32(SH7750_SCSMR_REGOFS(n)) +#define SH7750_SCSMR1_A7 SH7750_SCSMR_A7(1) +#define SH7750_SCSMR2_A7 SH7750_SCSMR_A7(2) + +#define SH7750_SCSMR1_CA 0x80 /* Communication Mode (C/A\): */ +#define SH7750_SCSMR1_CA_ASYNC 0x00 /* Asynchronous Mode */ +#define SH7750_SCSMR1_CA_SYNC 0x80 /* Synchronous Mode */ +#define SH7750_SCSMR_CHR 0x40 /* Character Length: */ +#define SH7750_SCSMR_CHR_8 0x00 /* 8-bit data */ +#define SH7750_SCSMR_CHR_7 0x40 /* 7-bit data */ +#define SH7750_SCSMR_PE 0x20 /* Parity Enable */ +#define SH7750_SCSMR_PM 0x10 /* Parity Mode: */ +#define SH7750_SCSMR_PM_EVEN 0x00 /* Even Parity */ +#define SH7750_SCSMR_PM_ODD 0x10 /* Odd Parity */ +#define SH7750_SCSMR_STOP 0x08 /* Stop Bit Length: */ +#define SH7750_SCSMR_STOP_1 0x00 /* 1 stop bit */ +#define SH7750_SCSMR_STOP_2 0x08 /* 2 stop bit */ +#define SH7750_SCSMR1_MP 0x04 /* Multiprocessor Mode */ +#define SH7750_SCSMR_CKS 0x03 /* Clock Select */ +#define SH7750_SCSMR_CKS_S 0 +#define SH7750_SCSMR_CKS_DIV1 0x00 /* Periph clock */ +#define SH7750_SCSMR_CKS_DIV4 0x01 /* Periph clock / 4 */ +#define SH7750_SCSMR_CKS_DIV16 0x02 /* Periph clock / 16 */ +#define SH7750_SCSMR_CKS_DIV64 0x03 /* Periph clock / 64 */ + +/* SCI Serial Control Register - SCSCR1(byte), SCSCR2(half) */ +#define SH7750_SCSCR_REGOFS(n) ((n) == 1 ? 0xE00008 : 0xE80008) /* offset */ +#define SH7750_SCSCR(n) SH7750_P4_REG32(SH7750_SCSCR_REGOFS(n)) +#define SH7750_SCSCR1 SH7750_SCSCR(1) +#define SH7750_SCSCR2 SH7750_SCSCR(2) +#define SH7750_SCSCR_A7(n) SH7750_A7_REG32(SH7750_SCSCR_REGOFS(n)) +#define SH7750_SCSCR1_A7 SH7750_SCSCR_A7(1) +#define SH7750_SCSCR2_A7 SH7750_SCSCR_A7(2) + +#define SH7750_SCSCR_TIE 0x80 /* Transmit Interrupt Enable */ +#define SH7750_SCSCR_RIE 0x40 /* Receive Interrupt Enable */ +#define SH7750_SCSCR_TE 0x20 /* Transmit Enable */ +#define SH7750_SCSCR_RE 0x10 /* Receive Enable */ +#define SH7750_SCSCR1_MPIE 0x08 /* Multiprocessor Interrupt Enable */ +#define SH7750_SCSCR2_REIE 0x08 /* Receive Error Interrupt Enable */ +#define SH7750_SCSCR1_TEIE 0x04 /* Transmit End Interrupt Enable */ +#define SH7750_SCSCR1_CKE 0x03 /* Clock Enable: */ +#define SH7750_SCSCR_CKE_INTCLK 0x00 /* Use Internal Clock */ +#define SH7750_SCSCR_CKE_EXTCLK 0x02 /* Use External Clock from SCK*/ +#define SH7750_SCSCR1_CKE_ASYNC_SCK_CLKOUT 0x01 /* Use SCK as a clock output + in asynchronous mode */ + +/* SCI Serial Status Register - SCSSR1(byte), SCSSR2(half) */ +#define SH7750_SCSSR_REGOFS(n) ((n) == 1 ? 0xE00010 : 0xE80010) /* offset */ +#define SH7750_SCSSR(n) SH7750_P4_REG32(SH7750_SCSSR_REGOFS(n)) +#define SH7750_SCSSR1 SH7750_SCSSR(1) +#define SH7750_SCSSR2 SH7750_SCSSR(2) +#define SH7750_SCSSR_A7(n) SH7750_A7_REG32(SH7750_SCSSR_REGOFS(n)) +#define SH7750_SCSSR1_A7 SH7750_SCSSR_A7(1) +#define SH7750_SCSSR2_A7 SH7750_SCSSR_A7(2) + +#define SH7750_SCSSR1_TDRE 0x80 /* Transmit Data Register Empty */ +#define SH7750_SCSSR1_RDRF 0x40 /* Receive Data Register Full */ +#define SH7750_SCSSR1_ORER 0x20 /* Overrun Error */ +#define SH7750_SCSSR1_FER 0x10 /* Framing Error */ +#define SH7750_SCSSR1_PER 0x08 /* Parity Error */ +#define SH7750_SCSSR1_TEND 0x04 /* Transmit End */ +#define SH7750_SCSSR1_MPB 0x02 /* Multiprocessor Bit */ +#define SH7750_SCSSR1_MPBT 0x01 /* Multiprocessor Bit Transfer */ + +#define SH7750_SCSSR2_PERN 0xF000 /* Number of Parity Errors */ +#define SH7750_SCSSR2_PERN_S 12 +#define SH7750_SCSSR2_FERN 0x0F00 /* Number of Framing Errors */ +#define SH7750_SCSSR2_FERN_S 8 +#define SH7750_SCSSR2_ER 0x0080 /* Receive Error */ +#define SH7750_SCSSR2_TEND 0x0040 /* Transmit End */ +#define SH7750_SCSSR2_TDFE 0x0020 /* Transmit FIFO Data Empty */ +#define SH7750_SCSSR2_BRK 0x0010 /* Break Detect */ +#define SH7750_SCSSR2_FER 0x0008 /* Framing Error */ +#define SH7750_SCSSR2_PER 0x0004 /* Parity Error */ +#define SH7750_SCSSR2_RDF 0x0002 /* Receive FIFO Data Full */ +#define SH7750_SCSSR2_DR 0x0001 /* Receive Data Ready */ + +/* SCI Serial Port Register - SCSPTR1(byte) */ +#define SH7750_SCSPTR1_REGOFS 0xE0001C /* offset */ +#define SH7750_SCSPTR1 SH7750_P4_REG32(SH7750_SCSPTR1_REGOFS) +#define SH7750_SCSPTR1_A7 SH7750_A7_REG32(SH7750_SCSPTR1_REGOFS) + +#define SH7750_SCSPTR1_EIO 0x80 /* Error Interrupt Only */ +#define SH7750_SCSPTR1_SPB1IO 0x08 /* 1: Output SPB1DT bit to SCK pin */ +#define SH7750_SCSPTR1_SPB1DT 0x04 /* Serial Port Clock Port Data */ +#define SH7750_SCSPTR1_SPB0IO 0x02 /* 1: Output SPB0DT bit to TxD pin */ +#define SH7750_SCSPTR1_SPB0DT 0x01 /* Serial Port Break Data */ + +/* SCIF Serial Port Register - SCSPTR2(half) */ +#define SH7750_SCSPTR2_REGOFS 0xE80020 /* offset */ +#define SH7750_SCSPTR2 SH7750_P4_REG32(SH7750_SCSPTR2_REGOFS) +#define SH7750_SCSPTR2_A7 SH7750_A7_REG32(SH7750_SCSPTR2_REGOFS) + +#define SH7750_SCSPTR2_RTSIO 0x80 /* 1: Output RTSDT bit to RTS2\ pin */ +#define SH7750_SCSPTR2_RTSDT 0x40 /* RTS Port Data */ +#define SH7750_SCSPTR2_CTSIO 0x20 /* 1: Output CTSDT bit to CTS2\ pin */ +#define SH7750_SCSPTR2_CTSDT 0x10 /* CTS Port Data */ +#define SH7750_SCSPTR2_SPB2IO 0x02 /* 1: Output SPBDT bit to TxD2 pin */ +#define SH7750_SCSPTR2_SPB2DT 0x01 /* Serial Port Break Data */ + +/* SCI Bit Rate Register - SCBRR1(byte), SCBRR2(byte) */ +#define SH7750_SCBRR_REGOFS(n) ((n) == 1 ? 0xE00004 : 0xE80004) /* offset */ +#define SH7750_SCBRR(n) SH7750_P4_REG32(SH7750_SCBRR_REGOFS(n)) +#define SH7750_SCBRR1 SH7750_SCBRR_P4(1) +#define SH7750_SCBRR2 SH7750_SCBRR_P4(2) +#define SH7750_SCBRR_A7(n) SH7750_A7_REG32(SH7750_SCBRR_REGOFS(n)) +#define SH7750_SCBRR1_A7 SH7750_SCBRR(1) +#define SH7750_SCBRR2_A7 SH7750_SCBRR(2) + +/* SCIF FIFO Control Register - SCFCR2(half) */ +#define SH7750_SCFCR2_REGOFS 0xE80018 /* offset */ +#define SH7750_SCFCR2 SH7750_P4_REG32(SH7750_SCFCR2_REGOFS) +#define SH7750_SCFCR2_A7 SH7750_A7_REG32(SH7750_SCFCR2_REGOFS) + +#define SH7750_SCFCR2_RSTRG 0x700 /* RTS2\ Output Active Trigger; RTS2\ + signal goes to high level when the + number of received data stored in + FIFO exceeds the trigger number */ +#define SH7750_SCFCR2_RSTRG_15 0x000 /* 15 bytes */ +#define SH7750_SCFCR2_RSTRG_1 0x000 /* 1 byte */ +#define SH7750_SCFCR2_RSTRG_4 0x000 /* 4 bytes */ +#define SH7750_SCFCR2_RSTRG_6 0x000 /* 6 bytes */ +#define SH7750_SCFCR2_RSTRG_8 0x000 /* 8 bytes */ +#define SH7750_SCFCR2_RSTRG_10 0x000 /* 10 bytes */ +#define SH7750_SCFCR2_RSTRG_14 0x000 /* 14 bytes */ + +#define SH7750_SCFCR2_RTRG 0x0C0 /* Receive FIFO Data Number Trigger, + Receive Data Full (RDF) Flag sets + when number of receive data bytes is + equal or greater than the trigger + number */ +#define SH7750_SCFCR2_RTRG_1 0x000 /* 1 byte */ +#define SH7750_SCFCR2_RTRG_4 0x040 /* 4 bytes */ +#define SH7750_SCFCR2_RTRG_8 0x080 /* 8 bytes */ +#define SH7750_SCFCR2_RTRG_14 0x0C0 /* 14 bytes */ + +#define SH7750_SCFCR2_TTRG 0x030 /* Transmit FIFO Data Number Trigger, + Transmit FIFO Data Register Empty (TDFE) + flag sets when the number of remaining + transmit data bytes is equal or less + than the trigger number */ +#define SH7750_SCFCR2_TTRG_8 0x000 /* 8 bytes */ +#define SH7750_SCFCR2_TTRG_4 0x010 /* 4 bytes */ +#define SH7750_SCFCR2_TTRG_2 0x020 /* 2 bytes */ +#define SH7750_SCFCR2_TTRG_1 0x030 /* 1 byte */ + +#define SH7750_SCFCR2_MCE 0x008 /* Modem Control Enable */ +#define SH7750_SCFCR2_TFRST 0x004 /* Transmit FIFO Data Register Reset, + invalidates the transmit data in the + transmit FIFO */ +#define SH7750_SCFCR2_RFRST 0x002 /* Receive FIFO Data Register Reset, + invalidates the receive data in the + receive FIFO data register and resets + it to the empty state */ +#define SH7750_SCFCR2_LOOP 0x001 /* Loopback Test */ + +/* SCIF FIFO Data Count Register - SCFDR2(half, read-only) */ +#define SH7750_SCFDR2_REGOFS 0xE8001C /* offset */ +#define SH7750_SCFDR2 SH7750_P4_REG32(SH7750_SCFDR2_REGOFS) +#define SH7750_SCFDR2_A7 SH7750_A7_REG32(SH7750_SCFDR2_REGOFS) + +#define SH7750_SCFDR2_T 0x1F00 /* Number of untransmitted data bytes + in transmit FIFO */ +#define SH7750_SCFDR2_T_S 8 +#define SH7750_SCFDR2_R 0x001F /* Number of received data bytes in + receive FIFO */ +#define SH7750_SCFDR2_R_S 0 + +/* SCIF Line Status Register - SCLSR2(half, read-only) */ +#define SH7750_SCLSR2_REGOFS 0xE80024 /* offset */ +#define SH7750_SCLSR2 SH7750_P4_REG32(SH7750_SCLSR2_REGOFS) +#define SH7750_SCLSR2_A7 SH7750_A7_REG32(SH7750_SCLSR2_REGOFS) + +#define SH7750_SCLSR2_ORER 0x0001 /* Overrun Error */ + +/* + * SCI-based Smart Card Interface + */ +/* Smart Card Mode Register - SCSCMR1(byte) */ +#define SH7750_SCSCMR1_REGOFS 0xE00018 /* offset */ +#define SH7750_SCSCMR1 SH7750_P4_REG32(SH7750_SCSCMR1_REGOFS) +#define SH7750_SCSCMR1_A7 SH7750_A7_REG32(SH7750_SCSCMR1_REGOFS) + +#define SH7750_SCSCMR1_SDIR 0x08 /* Smart Card Data Transfer Direction: */ +#define SH7750_SCSCMR1_SDIR_LSBF 0x00 /* LSB-first */ +#define SH7750_SCSCMR1_SDIR_MSBF 0x08 /* MSB-first */ + +#define SH7750_SCSCMR1_SINV 0x04 /* Smart Card Data Inversion */ +#define SH7750_SCSCMR1_SMIF 0x01 /* Smart Card Interface Mode Select */ + +/* Smart-card specific bits in other registers */ +/* SCSMR1: */ +#define SH7750_SCSMR1_GSM 0x80 /* GSM mode select */ + +/* SCSSR1: */ +#define SH7750_SCSSR1_ERS 0x10 /* Error Signal Status */ + +/* + * I/O Ports + */ +/* Port Control Register A - PCTRA */ +#define SH7750_PCTRA_REGOFS 0x80002C /* offset */ +#define SH7750_PCTRA SH7750_P4_REG32(SH7750_PCTRA_REGOFS) +#define SH7750_PCTRA_A7 SH7750_A7_REG32(SH7750_PCTRA_REGOFS) + +#define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */ +#define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1)) /* Bit n is not pulled up */ +#define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */ +#define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2)) /* Bit n is an output */ + +/* Port Data Register A - PDTRA(half) */ +#define SH7750_PDTRA_REGOFS 0x800030 /* offset */ +#define SH7750_PDTRA SH7750_P4_REG32(SH7750_PDTRA_REGOFS) +#define SH7750_PDTRA_A7 SH7750_A7_REG32(SH7750_PDTRA_REGOFS) + +#define SH7750_PDTRA_BIT(n) (1 << (n)) + +/* Port Control Register B - PCTRB */ +#define SH7750_PCTRB_REGOFS 0x800040 /* offset */ +#define SH7750_PCTRB SH7750_P4_REG32(SH7750_PCTRB_REGOFS) +#define SH7750_PCTRB_A7 SH7750_A7_REG32(SH7750_PCTRB_REGOFS) + +#define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */ +#define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1)) /* Bit n is not pulled up */ +#define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */ +#define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2)) /* Bit n is an output */ + +/* Port Data Register B - PDTRB(half) */ +#define SH7750_PDTRB_REGOFS 0x800044 /* offset */ +#define SH7750_PDTRB SH7750_P4_REG32(SH7750_PDTRB_REGOFS) +#define SH7750_PDTRB_A7 SH7750_A7_REG32(SH7750_PDTRB_REGOFS) + +#define SH7750_PDTRB_BIT(n) (1 << ((n)-16)) + +/* GPIO Interrupt Control Register - GPIOIC(half) */ +#define SH7750_GPIOIC_REGOFS 0x800048 /* offset */ +#define SH7750_GPIOIC SH7750_P4_REG32(SH7750_GPIOIC_REGOFS) +#define SH7750_GPIOIC_A7 SH7750_A7_REG32(SH7750_GPIOIC_REGOFS) + +#define SH7750_GPIOIC_PTIREN(n) (1 << (n)) /* Port n is used as a GPIO int */ + +/* + * Interrupt Controller - INTC + */ +/* Interrupt Control Register - ICR (half) */ +#define SH7750_ICR_REGOFS 0xD00000 /* offset */ +#define SH7750_ICR SH7750_P4_REG32(SH7750_ICR_REGOFS) +#define SH7750_ICR_A7 SH7750_A7_REG32(SH7750_ICR_REGOFS) + +#define SH7750_ICR_NMIL 0x8000 /* NMI Input Level */ +#define SH7750_ICR_MAI 0x4000 /* NMI Interrupt Mask */ + +#define SH7750_ICR_NMIB 0x0200 /* NMI Block Mode: */ +#define SH7750_ICR_NMIB_BLK 0x0000 /* NMI requests held pending while + SR.BL bit is set to 1 */ +#define SH7750_ICR_NMIB_NBLK 0x0200 /* NMI requests detected when SR.BL bit + set to 1 */ + +#define SH7750_ICR_NMIE 0x0100 /* NMI Edge Select: */ +#define SH7750_ICR_NMIE_FALL 0x0000 /* Interrupt request detected on falling + edge of NMI input */ +#define SH7750_ICR_NMIE_RISE 0x0100 /* Interrupt request detected on rising + edge of NMI input */ + +#define SH7750_ICR_IRLM 0x0080 /* IRL Pin Mode: */ +#define SH7750_ICR_IRLM_ENC 0x0000 /* IRL\ pins used as a level-encoded + interrupt requests */ +#define SH7750_ICR_IRLM_RAW 0x0080 /* IRL\ pins used as a four independent + interrupt requests */ + +/* Interrupt Priority Register A - IPRA (half) */ +#define SH7750_IPRA_REGOFS 0xD00004 /* offset */ +#define SH7750_IPRA SH7750_P4_REG32(SH7750_IPRA_REGOFS) +#define SH7750_IPRA_A7 SH7750_A7_REG32(SH7750_IPRA_REGOFS) + +#define SH7750_IPRA_TMU0 0xF000 /* TMU0 interrupt priority */ +#define SH7750_IPRA_TMU0_S 12 +#define SH7750_IPRA_TMU1 0x0F00 /* TMU1 interrupt priority */ +#define SH7750_IPRA_TMU1_S 8 +#define SH7750_IPRA_TMU2 0x00F0 /* TMU2 interrupt priority */ +#define SH7750_IPRA_TMU2_S 4 +#define SH7750_IPRA_RTC 0x000F /* RTC interrupt priority */ +#define SH7750_IPRA_RTC_S 0 + +/* Interrupt Priority Register B - IPRB (half) */ +#define SH7750_IPRB_REGOFS 0xD00008 /* offset */ +#define SH7750_IPRB SH7750_P4_REG32(SH7750_IPRB_REGOFS) +#define SH7750_IPRB_A7 SH7750_A7_REG32(SH7750_IPRB_REGOFS) + +#define SH7750_IPRB_WDT 0xF000 /* WDT interrupt priority */ +#define SH7750_IPRB_WDT_S 12 +#define SH7750_IPRB_REF 0x0F00 /* Memory Refresh unit interrupt + priority */ +#define SH7750_IPRB_REF_S 8 +#define SH7750_IPRB_SCI1 0x00F0 /* SCI1 interrupt priority */ +#define SH7750_IPRB_SCI1_S 4 + +/* Interrupt Priority Register C - IPRC (half) */ +#define SH7750_IPRC_REGOFS 0xD00004 /* offset */ +#define SH7750_IPRC SH7750_P4_REG32(SH7750_IPRC_REGOFS) +#define SH7750_IPRC_A7 SH7750_A7_REG32(SH7750_IPRC_REGOFS) + +#define SH7750_IPRC_GPIO 0xF000 /* GPIO interrupt priority */ +#define SH7750_IPRC_GPIO_S 12 +#define SH7750_IPRC_DMAC 0x0F00 /* DMAC interrupt priority */ +#define SH7750_IPRC_DMAC_S 8 +#define SH7750_IPRC_SCIF 0x00F0 /* SCIF interrupt priority */ +#define SH7750_IPRC_SCIF_S 4 +#define SH7750_IPRC_HUDI 0x000F /* H-UDI interrupt priority */ +#define SH7750_IPRC_HUDI_S 0 + + +/* + * User Break Controller registers + */ +#define SH7750_BARA 0x200000 /* Break address regiser A */ +#define SH7750_BAMRA 0x200004 /* Break address mask regiser A */ +#define SH7750_BBRA 0x200008 /* Break bus cycle regiser A */ +#define SH7750_BARB 0x20000c /* Break address regiser B */ +#define SH7750_BAMRB 0x200010 /* Break address mask regiser B */ +#define SH7750_BBRB 0x200014 /* Break bus cycle regiser B */ +#define SH7750_BASRB 0x000018 /* Break ASID regiser B */ +#define SH7750_BDRB 0x200018 /* Break data regiser B */ +#define SH7750_BDMRB 0x20001c /* Break data mask regiser B */ +#define SH7750_BRCR 0x200020 /* Break control register */ + +#define SH7750_BRCR_UDBE 0x0001 /* User break debug enable bit */ + +#endif diff --git a/bsps/sh/gensh4/include/sdram.h b/bsps/sh/gensh4/include/sdram.h new file mode 100644 index 0000000000..52acaa61db --- /dev/null +++ b/bsps/sh/gensh4/include/sdram.h @@ -0,0 +1,40 @@ +/* + * SDRAM Mode Register + * Based on Fujitsu MB81F643242B data sheet. + * + * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SDRAM_H__ +#define __SDRAM_H__ + +/* SDRAM Mode Register */ +#define SDRAM_MODE_BL 0x0007 /* Burst Length: */ +#define SDRAM_MODE_BL_1 0x0000 /* 0 */ +#define SDRAM_MODE_BL_2 0x0001 /* 2 */ +#define SDRAM_MODE_BL_4 0x0002 /* 4 */ +#define SDRAM_MODE_BL_8 0x0003 /* 8 */ +#define SDRAM_MODE_BL_16 0x0004 /* 16 */ +#define SDRAM_MODE_BL_32 0x0005 /* 32 */ +#define SDRAM_MODE_BL_64 0x0006 /* 64 */ +#define SDRAM_MODE_BL_FULL 0x0007 /* Full column */ + +#define SDRAM_MODE_BT 0x0008 /* Burst Type: */ +#define SDRAM_MODE_BT_SEQ 0x0000 /* Sequential */ +#define SDRAM_MODE_BT_ILV 0x0008 /* Interleave */ + +#define SDRAM_MODE_CL 0x0070 /* CAS Latency: */ +#define SDRAM_MODE_CL_1 0x0010 /* 1 */ +#define SDRAM_MODE_CL_2 0x0020 /* 2 */ +#define SDRAM_MODE_CL_3 0x0030 /* 3 */ + +#define SDRAM_MODE_OPC 0x0200 /* Opcode: */ +#define SDRAM_MODE_OPC_BRBW 0x0000 /* Burst read & Burst write */ +#define SDRAM_MODE_OPC_BRSW 0x0200 /* Burst read & Single write */ + +#endif diff --git a/bsps/sh/gensh4/include/sh/sh4uart.h b/bsps/sh/gensh4/include/sh/sh4uart.h new file mode 100644 index 0000000000..1e7a486eb8 --- /dev/null +++ b/bsps/sh/gensh4/include/sh/sh4uart.h @@ -0,0 +1,174 @@ +/* + * Generic UART Serial driver for SH-4 processors definitions + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed. + * Author: Alexandra Kossovsky + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SH4UART_H__ +#define __SH4UART_H__ + +#include + + +/* + * Define this to work from gdb stub + */ + +/* FIXME: This is BSP-specific */ +#define SH4_WITH_IPL + +#define SH4_SCI 1 /* Serial Communication Interface - SCI */ +#define SH4_SCIF 2 /* Serial Communication Interface with FIFO - SCIF */ +#define TRANSMIT_TRIGGER_VALUE(ttrg) ((ttrg) == SH7750_SCFCR2_RTRG_1 ? 1 : \ + (ttrg) == SH7750_SCFCR2_RTRG_4 ? 4 : \ + (ttrg) == SH7750_SCFCR2_RTRG_8 ? 8 : 14) + +/* + * Macros to call UART registers + */ +#define SCRDR(n) (*(volatile uint8_t*)SH7750_SCRDR(n)) +#define SCRDR1 SCRDR(1) +#define SCRDR2 SCRDR(2) +#define SCTDR(n) (*(volatile uint8_t*)SH7750_SCTDR(n)) +#define SCTDR1 SCTDR(1) +#define SCTDR2 SCTDR(2) +#define SCSMR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSMR1 : \ + *(volatile uint16_t*)SH7750_SCSMR2) +#define SCSMR1 SCSMR(1) +#define SCSMR2 SCSMR(2) +#define SCSCR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSCR1 : \ + *(volatile uint16_t*)SH7750_SCSCR2) +#define SCSCR1 SCSCR(1) +#define SCSCR2 SCSCR(2) +#define SCSSR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSSR1 : \ + *(volatile uint16_t*)SH7750_SCSSR2) +#define SCSSR1 SCSSR(1) +#define SCSSR2 SCSSR(2) +#define SCSPTR1 (*(volatile uint8_t*)SH7750_SCSPTR1) +#define SCSPTR2 (*(volatile uint16_t*)SH7750_SCSPTR2) +#define SCBRR(n) (*(volatile uint8_t*)SH7750_SCBRR(n)) +#define SCBRR1 SCBRR(1) +#define SCBRR2 SCBRR(2) +#define SCFCR2 (*(volatile uint16_t*)SH7750_SCFCR2) +#define SCFDR2 (*(volatile uint16_t*)SH7750_SCFDR2) +#define SCLSR2 (*(volatile uint16_t*)SH7750_SCLSR2) + +#define IPRB (*(volatile uint16_t*)SH7750_IPRB) +#define IPRC (*(volatile uint16_t*)SH7750_IPRC) + +/* + * The following structure is a descriptor of single UART channel. + * It contains the initialization information about channel and + * current operating values + */ +typedef struct sh4uart { + uint8_t chn; /* UART channel number */ + uint8_t int_driven; /* UART interrupt vector number, or + 0 if polled I/O */ + void *tty; /* termios channel descriptor */ + + volatile const char *tx_buf; /* Transmit buffer from termios */ + volatile uint32_t tx_buf_len; /* Transmit buffer length */ + volatile uint32_t tx_ptr; /* Index of next char to transmit*/ + + rtems_isr_entry old_handler_transmit; /* Saved interrupt handlers */ + rtems_isr_entry old_handler_receive; + + tcflag_t c_iflag; /* termios input mode flags */ + bool parerr_mark_flag; /* Parity error processing state */ +} sh4uart; + +/* + * Functions from sh4uart.c + */ + +/* sh4uart_init -- + * This function verifies the input parameters and perform initialization + * of the Motorola Coldfire on-chip UART descriptor structure. + * + */ +rtems_status_code +sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven); + +/* sh4uart_reset -- + * This function perform the hardware initialization of Motorola + * Coldfire processor on-chip UART controller using parameters + * filled by the sh4uart_init function. + */ +rtems_status_code +sh4uart_reset(sh4uart *uart); + +/* sh4uart_disable -- + * This function disable the operations on Motorola Coldfire UART + * controller + */ +rtems_status_code +sh4uart_disable(sh4uart *uart, int disable_port); + +/* sh4uart_set_attributes -- + * This function parse the termios attributes structure and perform + * the appropriate settings in hardware. + */ +rtems_status_code +sh4uart_set_attributes(sh4uart *mcf, const struct termios *t); + +/* sh4uart_poll_read -- + * This function tried to read character from MCF UART and perform + * error handling. + */ +int +sh4uart_poll_read(sh4uart *uart); + +#ifdef SH4_WITH_IPL +/* ipl_console_poll_read -- + * This function tried to read character from MCF UART over SH-IPL. + */ +int +ipl_console_poll_read(int minor); + +/* sh4uart_interrupt_write -- + * This function initiate transmitting of the buffer in interrupt mode. + */ +rtems_status_code +sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len); + +/* sh4uart_poll_write -- + * This function transmit buffer byte-by-byte in polling mode. + */ +int +sh4uart_poll_write(sh4uart *uart, const char *buf, int len); + +/* ipl_console_poll_write -- + * This function transmit buffer byte-by-byte in polling mode over SH-IPL. + */ +int +ipl_console_poll_write(int minor, const char *buf, int len); + +/* + * ipl_finish -- + * Says gdb that program finished to get out from it. + */ +extern void ipl_finish(void); +#endif + +/* sh4uart_stop_remote_tx -- + * This function stop data flow from remote device. + */ +rtems_status_code +sh4uart_stop_remote_tx(sh4uart *uart); + +/* sh4uart_start_remote_tx -- + * This function resume data flow from remote device. + */ +rtems_status_code +sh4uart_start_remote_tx(sh4uart *uart); + +/* Descriptor structures for two on-chip UART channels */ +extern sh4uart sh4_uarts[2]; + +#endif diff --git a/bsps/sh/gensh4/include/tm27.h b/bsps/sh/gensh4/include/tm27.h new file mode 100644 index 0000000000..c26ec49272 --- /dev/null +++ b/bsps/sh/gensh4/include/tm27.h @@ -0,0 +1,59 @@ +/* + * @file + * @ingroup sh_gensh4 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#ifndef SH7750_EVT_WDT_ITI +# error "..." +#endif + +#define Install_tm27_vector( handler ) \ +{ \ + rtems_isr_entry old_handler; \ + rtems_status_code status; \ + status = rtems_interrupt_catch( (handler), \ + SH7750_EVT_TO_NUM(SH7750_EVT_WDT_ITI), &old_handler); \ + if (status != RTEMS_SUCCESSFUL) \ + printf("Status of rtems_interrupt_catch = %d", status); \ +} + +#define Cause_tm27_intr() \ +{ \ + *(volatile uint16_t*)SH7750_IPRB |= 0xf000; \ + *(volatile uint16_t*)SH7750_WTCSR = SH7750_WTCSR_KEY; \ + *(volatile uint16_t*)SH7750_WTCNT = SH7750_WTCNT_KEY | 0xfe; \ + *(volatile uint16_t*)SH7750_WTCSR = \ + SH7750_WTCSR_KEY | SH7750_WTCSR_TME; \ +} + +#define Clear_tm27_intr() \ +{ \ + *(volatile uint16_t*)SH7750_WTCSR = SH7750_WTCSR_KEY; \ +} + +#define Lower_tm27_intr() \ +{ \ + sh_set_interrupt_level((SH7750_IPRB & 0xf000) << SH4_SR_IMASK_S); \ +} + +#endif diff --git a/bsps/sh/shsim/headers.am b/bsps/sh/shsim/headers.am new file mode 100644 index 0000000000..d221f41a07 --- /dev/null +++ b/bsps/sh/shsim/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/sh/shsim/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/sh/shsim/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/sh/shsim/include/bsp/syscall.h diff --git a/bsps/sh/shsim/include/bsp.h b/bsps/sh/shsim/include/bsp.h new file mode 100644 index 0000000000..7b8236b09a --- /dev/null +++ b/bsps/sh/shsim/include/bsp.h @@ -0,0 +1,65 @@ +/* + * SH-gdb simulator BSP + * + * This include file contains all board IO definitions. + */ + +/* + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * COPYRIGHT (c) 2001, Ralf Corsepius, Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * COPYRIGHT (c) 2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SH_SHSIM_BSP_H +#define LIBBSP_SH_SHSIM_BSP_H + +#ifndef ASM + +#include + +#include +#include + +/* + * FIXME: One of these would be enough. + */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Constants */ + +void *clock_driver_sim_idle_body(uintptr_t); +#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body + +/* + * Defined in the linker script 'linkcmds' + */ +extern void *CPU_Interrupt_stack_low; +extern void *CPU_Interrupt_stack_high; + +/* + * BSP methods that cross file boundaries. + */ +int _sys_exit (int n); +void bsp_hw_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ +#endif diff --git a/bsps/sh/shsim/include/bsp/syscall.h b/bsps/sh/shsim/include/bsp/syscall.h new file mode 100644 index 0000000000..e5cde7217b --- /dev/null +++ b/bsps/sh/shsim/include/bsp/syscall.h @@ -0,0 +1,32 @@ +#define SYS_exit 1 +#define SYS_fork 2 + +#define SYS_read 3 +#define SYS_write 4 +#define SYS_open 5 +#define SYS_close 6 +#define SYS_wait4 7 +#define SYS_creat 8 +#define SYS_link 9 +#define SYS_unlink 10 +#define SYS_execv 11 +#define SYS_chdir 12 +#define SYS_mknod 14 +#define SYS_chmod 15 +#define SYS_chown 16 +#define SYS_lseek 19 +#define SYS_getpid 20 +#define SYS_isatty 21 +#define SYS_fstat 22 +#define SYS_time 23 + +#define SYS_ARG 24 +#define SYS_stat 38 + +#define SYS_pipe 42 +#define SYS_execve 59 + +#define SYS_utime 201 /* not really a system call */ +#define SYS_wait 202 /* nor is this */ + +int __trap34(int, int, void*, int ); diff --git a/bsps/sh/shsim/include/tm27.h b/bsps/sh/shsim/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/sh/shsim/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/sparc/erc32/headers.am b/bsps/sparc/erc32/headers.am new file mode 100644 index 0000000000..00ad61f3e2 --- /dev/null +++ b/bsps/sparc/erc32/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/sparc/erc32/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/sparc/erc32/include/erc32.h +include_HEADERS += ../../../../../../bsps/sparc/erc32/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/sparc/erc32/include/bsp/irq.h diff --git a/bsps/sparc/erc32/include/bsp.h b/bsps/sparc/erc32/include/bsp.h new file mode 100644 index 0000000000..71719f9cf3 --- /dev/null +++ b/bsps/sparc/erc32/include/bsp.h @@ -0,0 +1,184 @@ +/** + * @file + * + * @ingroup sparc_erc32 + * + * @brief Global BSP Definitions. + */ + +/* + * COPYRIGHT (c) 1989-2007. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Ported to ERC32 implementation of the SPARC by On-Line Applications + * Research Corporation (OAR) under contract to the European Space + * Agency (ESA). + * + * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. + * European Space Agency. + */ + +#ifndef LIBBSP_SPARC_ERC32_BSP_H +#define LIBBSP_SPARC_ERC32_BSP_H + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup sparc_erc32 ERC32 Support + * + * @ingroup bsp_sparc + * + * @brief ERC32 Support Package + */ + +/* + * BSP provides its own Idle thread body + */ +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_erc32_sonic_driver_attach( + struct rtems_bsdnet_ifconfig *config +); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "sonic1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_erc32_sonic_driver_attach + +/* Constants */ + +/* + * Information placed in the linkcmds file. + */ + +extern int RAM_START; +extern int RAM_END; +extern int RAM_SIZE; + +extern int PROM_START; +extern int PROM_END; +extern int PROM_SIZE; + +extern int CLOCK_SPEED; + +extern int end; /* last address in the program */ + +/* functions */ + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +void BSP_fatal_exit(uint32_t error); + +void bsp_spurious_initialize( void ); + +/* Interrupt Service Routine (ISR) pointer */ +typedef void (*bsp_shared_isr)(void *arg); + +/* Initializes the Shared System Interrupt service */ +extern void BSP_shared_interrupt_init(void); + +/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */ +void bsp_isr_handler(rtems_vector_number vector); + +/* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple + * interrupt handlers may use the same IRQ number, all ISRs will be called + * when an interrupt on that line is fired. + * + * Arguments + * irq System IRQ number + * info Optional Name of IRQ source + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static __inline__ int BSP_shared_interrupt_register + ( + int irq, + const char *info, + bsp_shared_isr isr, + void *arg + ) +{ + return rtems_interrupt_handler_install(irq, info, + RTEMS_INTERRUPT_SHARED, isr, arg); +} + +/* Unregister previously registered shared IRQ handler. + * + * Arguments + * irq System IRQ number + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static __inline__ int BSP_shared_interrupt_unregister + ( + int irq, + bsp_shared_isr isr, + void *arg + ) +{ + return rtems_interrupt_handler_remove(irq, isr, arg); +} + +/* Clear interrupt pending on IRQ controller, this is typically done on a + * level triggered interrupt source such as PCI to avoid taking double IRQs. + * In such a case the interrupt source must be cleared first on LEON, before + * acknowledging the IRQ with this function. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_clear(int irq); + +/* Enable Interrupt. This function will unmask the IRQ at the interrupt + * controller. This is normally done by _register(). Note that this will + * affect all ISRs on this IRQ. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_unmask(int irq); + +/* Disable Interrupt. This function will mask one IRQ at the interrupt + * controller. This is normally done by _unregister(). Note that this will + * affect all ISRs on this IRQ. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_mask(int irq); + +/* + * Delay for the specified number of microseconds. + */ +void rtems_bsp_delay(int usecs); + +/* + * Prototypes for methods used across file boundaries + */ +void console_outbyte_polled(int port, unsigned char ch); +int console_inbyte_nonblocking(int port); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/erc32/include/bsp/irq.h b/bsps/sparc/erc32/include/bsp/irq.h new file mode 100644 index 0000000000..7789c9f57d --- /dev/null +++ b/bsps/sparc/erc32/include/bsp/irq.h @@ -0,0 +1,48 @@ +/** + * @file + * @ingroup sparc_erc32 + * @brief ERC32 generic shared IRQ setup + * + * Based on libbsp/shared/include/irq.h. + */ + +/* + * Copyright (c) 2012. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ERC32_IRQ_CONFIG_H +#define LIBBSP_ERC32_IRQ_CONFIG_H + +#include + +#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX BSP_INTERRUPT_VECTOR_MAX_STD + +/* No extra check is needed */ +#undef BSP_INTERRUPT_CUSTOM_VALID_VECTOR + +RTEMS_INLINE_ROUTINE void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +) +{ + (void) vector; + (void) affinity; +} + +RTEMS_INLINE_ROUTINE void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +) +{ + (void) vector; + _Processor_mask_From_index( affinity, 0 ); +} + +#endif /* LIBBSP_ERC32_IRQ_CONFIG_H */ diff --git a/bsps/sparc/erc32/include/erc32.h b/bsps/sparc/erc32/include/erc32.h new file mode 100644 index 0000000000..7db4a6c91b --- /dev/null +++ b/bsps/sparc/erc32/include/erc32.h @@ -0,0 +1,549 @@ +/** + * @file + * @ingroup sparc_erc32 + * @brief Contains information pertaining to the ERC32 + */ + +/* erc32.h + * + * This include file contains information pertaining to the ERC32. + * The ERC32 is a custom SPARC V7 implementation based on the Cypress + * 601/602 chipset. This CPU has a number of on-board peripherals and + * was developed by the European Space Agency to target space applications. + * + * NOTE: Other than where absolutely required, this version currently + * supports only the peripherals and bits used by the basic board + * support package. This includes at least significant pieces of + * the following items: + * + * + UART Channels A and B + * + General Purpose Timer + * + Real Time Clock + * + Watchdog Timer (so it can be disabled) + * + Control Register (so powerdown mode can be enabled) + * + Memory Control Register + * + Interrupt Control + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Ported to ERC32 implementation of the SPARC by On-Line Applications + * Research Corporation (OAR) under contract to the European Space + * Agency (ESA). + * + * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. + * European Space Agency. + */ + +#ifndef _INCLUDE_ERC32_h +#define _INCLUDE_ERC32_h + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Interrupt Sources + * + * The interrupt source numbers directly map to the trap type and to + * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, + * and the Interrupt Pending Registers. + */ + +#define ERC32_INTERRUPT_MASKED_ERRORS 1 +#define ERC32_INTERRUPT_EXTERNAL_1 2 +#define ERC32_INTERRUPT_EXTERNAL_2 3 +#define ERC32_INTERRUPT_UART_A_RX_TX 4 +#define ERC32_INTERRUPT_UART_B_RX_TX 5 +#define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6 +#define ERC32_INTERRUPT_UART_ERROR 7 +#define ERC32_INTERRUPT_DMA_ACCESS_ERROR 8 +#define ERC32_INTERRUPT_DMA_TIMEOUT 9 +#define ERC32_INTERRUPT_EXTERNAL_3 10 +#define ERC32_INTERRUPT_EXTERNAL_4 11 +#define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12 +#define ERC32_INTERRUPT_REAL_TIME_CLOCK 13 +#define ERC32_INTERRUPT_EXTERNAL_5 14 +#define ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15 + +#ifndef ASM + +/* + * Trap Types for on-chip peripherals + * + * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments + * + * NOTE: The priority level for each source corresponds to the least + * significant nibble of the trap type. + */ + +#define ERC32_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) + +#define ERC32_TRAP_SOURCE( _trap ) ((_trap) - 0x10) + +#define ERC32_Is_MEC_Trap( _trap ) \ + ( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \ + (_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) ) + +/* + * Structure for ERC32 memory mapped registers. + * + * Source: Section 3.25.2 - Register Address Map + * + * NOTE: There is only one of these structures per CPU, its base address + * is 0x01f80000, and the variable MEC is placed there by the + * linkcmds file. + */ + +typedef struct { + volatile uint32_t Control; /* offset 0x00 */ + volatile uint32_t Software_Reset; /* offset 0x04 */ + volatile uint32_t Power_Down; /* offset 0x08 */ + volatile uint32_t Unimplemented_0; /* offset 0x0c */ + volatile uint32_t Memory_Configuration; /* offset 0x10 */ + volatile uint32_t IO_Configuration; /* offset 0x14 */ + volatile uint32_t Wait_State_Configuration; /* offset 0x18 */ + volatile uint32_t Unimplemented_1; /* offset 0x1c */ + volatile uint32_t Memory_Access_0; /* offset 0x20 */ + volatile uint32_t Memory_Access_1; /* offset 0x24 */ + volatile uint32_t Unimplemented_2[ 7 ]; /* offset 0x28 */ + volatile uint32_t Interrupt_Shape; /* offset 0x44 */ + volatile uint32_t Interrupt_Pending; /* offset 0x48 */ + volatile uint32_t Interrupt_Mask; /* offset 0x4c */ + volatile uint32_t Interrupt_Clear; /* offset 0x50 */ + volatile uint32_t Interrupt_Force; /* offset 0x54 */ + volatile uint32_t Unimplemented_3[ 2 ]; /* offset 0x58 */ + /* offset 0x60 */ + volatile uint32_t Watchdog_Program_and_Timeout_Acknowledge; + volatile uint32_t Watchdog_Trap_Door_Set; /* offset 0x64 */ + volatile uint32_t Unimplemented_4[ 6 ]; /* offset 0x68 */ + volatile uint32_t Real_Time_Clock_Counter; /* offset 0x80 */ + volatile uint32_t Real_Time_Clock_Scalar; /* offset 0x84 */ + volatile uint32_t General_Purpose_Timer_Counter; /* offset 0x88 */ + volatile uint32_t General_Purpose_Timer_Scalar; /* offset 0x8c */ + volatile uint32_t Unimplemented_5[ 2 ]; /* offset 0x90 */ + volatile uint32_t Timer_Control; /* offset 0x98 */ + volatile uint32_t Unimplemented_6; /* offset 0x9c */ + volatile uint32_t System_Fault_Status; /* offset 0xa0 */ + volatile uint32_t First_Failing_Address; /* offset 0xa4 */ + volatile uint32_t First_Failing_Data; /* offset 0xa8 */ + volatile uint32_t First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */ + volatile uint32_t Error_and_Reset_Status; /* offset 0xb0 */ + volatile uint32_t Error_Mask; /* offset 0xb4 */ + volatile uint32_t Unimplemented_7[ 2 ]; /* offset 0xb8 */ + volatile uint32_t Debug_Control; /* offset 0xc0 */ + volatile uint32_t Breakpoint; /* offset 0xc4 */ + volatile uint32_t Watchpoint; /* offset 0xc8 */ + volatile uint32_t Unimplemented_8; /* offset 0xcc */ + volatile uint32_t Test_Control; /* offset 0xd0 */ + volatile uint32_t Test_Data; /* offset 0xd4 */ + volatile uint32_t Unimplemented_9[ 2 ]; /* offset 0xd8 */ + volatile uint32_t UART_Channel_A; /* offset 0xe0 */ + volatile uint32_t UART_Channel_B; /* offset 0xe4 */ + volatile uint32_t UART_Status; /* offset 0xe8 */ +} ERC32_Register_Map; + +#endif + +/* + * The following constants are intended to be used ONLY in assembly + * language files. + * + * NOTE: The intended style of usage is to load the address of MEC + * into a register and then use these as displacements from + * that register. + */ + +#ifdef ASM + +#define ERC32_MEC_CONTROL_OFFSET 0x00 +#define ERC32_MEC_SOFTWARE_RESET_OFFSET 0x04 +#define ERC32_MEC_POWER_DOWN_OFFSET 0x08 +#define ERC32_MEC_UNIMPLEMENTED_0_OFFSET 0x0C +#define ERC32_MEC_MEMORY_CONFIGURATION_OFFSET 0x10 +#define ERC32_MEC_IO_CONFIGURATION_OFFSET 0x14 +#define ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET 0x18 +#define ERC32_MEC_UNIMPLEMENTED_1_OFFSET 0x1C +#define ERC32_MEC_MEMORY_ACCESS_0_OFFSET 0x20 +#define ERC32_MEC_MEMORY_ACCESS_1_OFFSET 0x24 +#define ERC32_MEC_UNIMPLEMENTED_2_OFFSET 0x28 +#define ERC32_MEC_INTERRUPT_SHAPE_OFFSET 0x44 +#define ERC32_MEC_INTERRUPT_PENDING_OFFSET 0x48 +#define ERC32_MEC_INTERRUPT_MASK_OFFSET 0x4C +#define ERC32_MEC_INTERRUPT_CLEAR_OFFSET 0x50 +#define ERC32_MEC_INTERRUPT_FORCE_OFFSET 0x54 +#define ERC32_MEC_UNIMPLEMENTED_3_OFFSET 0x58 +#define ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60 +#define ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET 0x64 +#define ERC32_MEC_UNIMPLEMENTED_4_OFFSET 0x6C +#define ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET 0x80 +#define ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET 0x84 +#define ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET 0x88 +#define ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET 0x8C +#define ERC32_MEC_UNIMPLEMENTED_5_OFFSET 0x90 +#define ERC32_MEC_TIMER_CONTROL_OFFSET 0x98 +#define ERC32_MEC_UNIMPLEMENTED_6_OFFSET 0x9C +#define ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET 0xA0 +#define ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET 0xA4 +#define ERC32_MEC_FIRST_FAILING_DATA_OFFSET 0xA8 +#define ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET 0xAC +#define ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET 0xB0 +#define ERC32_MEC_ERROR_MASK_OFFSET 0xB4 +#define ERC32_MEC_UNIMPLEMENTED_7_OFFSET 0xB8 +#define ERC32_MEC_DEBUG_CONTROL_OFFSET 0xC0 +#define ERC32_MEC_BREAKPOINT_OFFSET 0xC4 +#define ERC32_MEC_WATCHPOINT_OFFSET 0xC8 +#define ERC32_MEC_UNIMPLEMENTED_8_OFFSET 0xCC +#define ERC32_MEC_TEST_CONTROL_OFFSET 0xD0 +#define ERC32_MEC_TEST_DATA_OFFSET 0xD4 +#define ERC32_MEC_UNIMPLEMENTED_9_OFFSET 0xD8 +#define ERC32_MEC_UART_CHANNEL_A_OFFSET 0xE0 +#define ERC32_MEC_UART_CHANNEL_B_OFFSET 0xE4 +#define ERC32_MEC_UART_STATUS_OFFSET 0xE8 + +#endif + +/* + * The following defines the bits in the Configuration Register. + */ + +#define ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001 +#define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001 +#define ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000 + +#define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002 +#define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002 +#define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000 + +#define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004 +#define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004 +#define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000 + +#define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008 +#define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008 +#define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000 + +/* + * The following defines the bits in the Memory Configuration Register. + */ + +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00 +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 ) + +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000 +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 0 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 1 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 2 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M ( 3 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M ( 4 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M ( 5 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M ( 6 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M ( 7 << 18 ) + +/* + * The following defines the bits in the Timer Control Register. + */ + +#define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */ + /* 0 = stop at 0 */ +#define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */ + /* 0 = no function */ +#define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */ + /* 0 = hold scalar and counter */ +#define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start*/ + /* 0 = no function */ + +#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */ + /* 0 = stop at 0 */ +#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */ + /* 0 = no function */ +#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */ + /* 0 = hold scalar and counter */ +#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start*/ + /* 0 = no function */ + +/* + * The following defines the bits in the UART Control Registers. + * + */ + +#define ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ + +/* + * The following defines the bits in the MEC UART Control Registers. + */ + +#define ERC32_MEC_UART_STATUS_DR 0x00000001 /* Data Ready */ +#define ERC32_MEC_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ +#define ERC32_MEC_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ +#define ERC32_MEC_UART_STATUS_FE 0x00000010 /* RX Framing Error */ +#define ERC32_MEC_UART_STATUS_PE 0x00000020 /* RX Parity Error */ +#define ERC32_MEC_UART_STATUS_OE 0x00000040 /* RX Overrun Error */ +#define ERC32_MEC_UART_STATUS_CU 0x00000080 /* Clear Errors */ +#define ERC32_MEC_UART_STATUS_TXE 0x00000006 /* TX Empty */ +#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */ +#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */ +#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */ +#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */ + +#define ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0) +#define ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0) +#define ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0) +#define ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0) +#define ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0) +#define ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0) +#define ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0) +#define ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0) + +#define ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16) +#define ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16) +#define ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16) +#define ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16) +#define ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16) +#define ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16) +#define ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16) +#define ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16) + +#ifndef ASM + +/* + * This is used to manipulate the on-chip registers. + * + * The following symbol must be defined in the linkcmds file and point + * to the correct location. + */ + +extern ERC32_Register_Map ERC32_MEC; + +static __inline__ int bsp_irq_fixup(int irq) +{ + return irq; +} + +/* + * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, + * and the Interrupt Pending Registers. + * + * NOTE: For operations which are not atomic, this code disables interrupts + * to guarantee there are no intervening accesses to the same register. + * The operations which read the register, modify the value and then + * store the result back are vulnerable. + */ + +#define ERC32_Clear_interrupt( _source ) \ + do { \ + ERC32_MEC.Interrupt_Clear = (1 << (_source)); \ + } while (0) + +#define ERC32_Force_interrupt( _source ) \ + do { \ + uint32_t _level; \ + \ + _level = sparc_disable_interrupts(); \ + ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \ + ERC32_MEC.Interrupt_Force = (1 << (_source)); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +#define ERC32_Is_interrupt_pending( _source ) \ + (ERC32_MEC.Interrupt_Pending & (1 << (_source))) + +#define ERC32_Is_interrupt_masked( _source ) \ + (ERC32_MEC.Interrupt_Mask & (1 << (_source))) + +#define ERC32_Mask_interrupt( _source ) \ + do { \ + uint32_t _level; \ + \ + _level = sparc_disable_interrupts(); \ + ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +#define ERC32_Unmask_interrupt( _source ) \ + do { \ + uint32_t _level; \ + \ + _level = sparc_disable_interrupts(); \ + ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +#define ERC32_Disable_interrupt( _source, _previous ) \ + do { \ + uint32_t _level; \ + uint32_t _mask = 1 << (_source); \ + \ + _level = sparc_disable_interrupts(); \ + (_previous) = ERC32_MEC.Interrupt_Mask; \ + ERC32_MEC.Interrupt_Mask = _previous | _mask; \ + sparc_enable_interrupts( _level ); \ + (_previous) &= _mask; \ + } while (0) + +#define ERC32_Restore_interrupt( _source, _previous ) \ + do { \ + uint32_t _level; \ + uint32_t _mask = 1 << (_source); \ + \ + _level = sparc_disable_interrupts(); \ + ERC32_MEC.Interrupt_Mask = \ + (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +/* Make all SPARC BSPs have common macros for interrupt handling on local CPU */ +#define BSP_Clear_interrupt(_source) ERC32_Clear_interrupt(_source) +#define BSP_Force_interrupt(_source) ERC32_Force_interrupt(_source) +#define BSP_Is_interrupt_pending(_source) ERC32_Is_interrupt_pending(_source) +#define BSP_Is_interrupt_masked(_source) ERC32_Is_interrupt_masked(_source) +#define BSP_Unmask_interrupt(_source) ERC32_Unmask_interrupt(_source) +#define BSP_Mask_interrupt(_source) ERC32_Mask_interrupt(_source) +#define BSP_Disable_interrupt(_source, _previous) \ + ERC32_Disable_interrupt(_source, _prev) +#define BSP_Restore_interrupt(_source, _previous) \ + ERC32_Restore_interrupt(_source, _previous) + +/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */ +#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \ + BSP_Is_interrupt_masked(_source) +#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \ + BSP_Unmask_interrupt(_source) +#define BSP_Cpu_Mask_interrupt(_source, _cpu) \ + BSP_Mask_interrupt(_source) +#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \ + BSP_Disable_interrupt(_source, _prev) +#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \ + BSP_Cpu_Restore_interrupt(_source, _previous) + +/* + * The following macros attempt to hide the fact that the General Purpose + * Timer and Real Time Clock Timer share the Timer Control Register. Because + * the Timer Control Register is write only, we must mirror it in software + * and insure that writes to one timer do not alter the current settings + * and status of the other timer. + * + * This code promotes the view that the two timers are completely independent. + * By exclusively using the routines below to access the Timer Control + * Register, the application can view the system as having a General Purpose + * Timer Control Register and a Real Time Clock Timer Control Register + * rather than the single shared value. + * + * Each logical timer control register is organized as follows: + * + * D0 - Counter Reload + * 1 = reload counter at zero and restart + * 0 = stop counter at zero + * + * D1 - Counter Load + * 1 = load counter with preset value and restart + * 0 = no function + * + * D2 - Enable + * 1 = enable counting + * 0 = hold scaler and counter + * + * D3 - Scaler Load + * 1 = load scalar with preset value and restart + * 0 = no function + * + * To insure the management of the mirror is atomic, we disable interrupts + * around updates. + */ + +#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001 +#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 + +#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002 + +#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004 +#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 + +#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008 + +#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001 +#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004 + +#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F +#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005 + +extern uint32_t _ERC32_MEC_Timer_Control_Mirror; + +/* + * This macros manipulate the General Purpose Timer portion of the + * Timer Control register and promote the view that there are actually + * two independent Timer Control Registers. + */ + +#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \ + do { \ + uint32_t _level; \ + uint32_t _control; \ + uint32_t __value; \ + \ + __value = ((_value) & 0x0f); \ + _level = sparc_disable_interrupts(); \ + _control = _ERC32_MEC_Timer_Control_Mirror; \ + _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \ + _ERC32_MEC_Timer_Control_Mirror = _control | _value; \ + _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \ + _control |= __value; \ + /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \ + ERC32_MEC.Timer_Control = _control; \ + sparc_enable_interrupts( _level ); \ + } while ( 0 ) + +#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \ + do { \ + (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \ + } while ( 0 ) + +/* + * This macros manipulate the Real Timer Clock Timer portion of the + * Timer Control register and promote the view that there are actually + * two independent Timer Control Registers. + */ + +#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \ + do { \ + uint32_t _level; \ + uint32_t _control; \ + uint32_t __value; \ + \ + __value = ((_value) & 0x0f) << 8; \ + _level = sparc_disable_interrupts(); \ + _control = _ERC32_MEC_Timer_Control_Mirror; \ + _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \ + _ERC32_MEC_Timer_Control_Mirror = _control | __value; \ + _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \ + _control |= __value; \ + /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \ + ERC32_MEC.Timer_Control = _control; \ + sparc_enable_interrupts( _level ); \ + } while ( 0 ) + +#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \ + do { \ + (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \ + } while ( 0 ) + +#endif /* !ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* !_INCLUDE_ERC32_h */ diff --git a/bsps/sparc/erc32/include/tm27.h b/bsps/sparc/erc32/include/tm27.h new file mode 100644 index 0000000000..958036fbf0 --- /dev/null +++ b/bsps/sparc/erc32/include/tm27.h @@ -0,0 +1,85 @@ +/** + * @file + * @ingroup sparc_erc32 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * COPYRIGHT (c) 2006. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: Since the interrupt code for the SPARC supports both synchronous + * and asynchronous trap handlers, support for testing with both + * is included. + */ + +#define ERC32_BSP_USE_SYNCHRONOUS_TRAP 0 + +/* + * The synchronous trap is an arbitrarily chosen software trap. + */ + +#if (ERC32_BSP_USE_SYNCHRONOUS_TRAP == 1) + +#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), TEST_VECTOR, 1 ); + +#define Cause_tm27_intr() \ + __asm__ volatile( "ta 0x10; nop " ); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +/* + * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. + */ + +#else /* use a regular asynchronous trap */ + +#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1 +#define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1) +#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) +#define TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), TEST_VECTOR, 1 ); \ + set_vector( (handler), TEST_VECTOR2, 1 ); + +#define Cause_tm27_intr() \ + do { \ + ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \ + nop(); \ + nop(); \ + nop(); \ + } while (0) + +#define Clear_tm27_intr() \ + ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE ) + +#define Lower_tm27_intr() /* empty */ + +#endif + +#endif diff --git a/bsps/sparc/headers.am b/bsps/sparc/headers.am new file mode 100644 index 0000000000..c561e0c06f --- /dev/null +++ b/bsps/sparc/headers.am @@ -0,0 +1,75 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../bsps/sparc/include/ambapp.h +include_HEADERS += ../../../../../bsps/sparc/include/ambapp_ids.h +include_HEADERS += ../../../../../bsps/sparc/include/grlib.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/ahbstat.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/apbuart.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/apbuart_cons.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/apbuart_termios.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/b1553brm.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/b1553rt.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/canmux.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/cons.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/debug_defs.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/genirq.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gnatcommon.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gpiolib.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gptimer.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr1553b.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr1553bc.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr1553bc_list.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr1553bm.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr1553rt.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr_701.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr_cpci_gr740.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr_leon4_n2x.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr_rasta_adcdac.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr_rasta_io.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr_rasta_spw_router.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr_rasta_tmtc.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gr_tmtc_1553.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/gradcdac.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grascs.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grcan.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grctm.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/greth.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grgpio.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/griommu.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grpci.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grpci2.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grpci2dma.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grpwm.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grslink.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grspw.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grspw_pkt.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grspw_router.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grtc.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/grtm.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/i2cmst.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/l2c.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/l4stat.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/mctrl.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/memscrub.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/network_interface_add.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/occan.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/pcif.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/satcan.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/spictrl.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/spwcuc.h +include_bsp_HEADERS += ../../../../../bsps/sparc/include/bsp/tlib.h + +include_drvmgrdir = $(includedir)/drvmgr +include_drvmgr_HEADERS = +include_drvmgr_HEADERS += ../../../../../bsps/sparc/include/drvmgr/ambapp_bus.h +include_drvmgr_HEADERS += ../../../../../bsps/sparc/include/drvmgr/ambapp_bus_grlib.h +include_drvmgr_HEADERS += ../../../../../bsps/sparc/include/drvmgr/bspcommon.h +include_drvmgr_HEADERS += ../../../../../bsps/sparc/include/drvmgr/leon2_amba_bus.h + +include_libcpudir = $(includedir)/libcpu +include_libcpu_HEADERS = +include_libcpu_HEADERS += ../../../../../bsps/sparc/include/libcpu/access.h diff --git a/bsps/sparc/include/ambapp.h b/bsps/sparc/include/ambapp.h new file mode 100644 index 0000000000..338602e83d --- /dev/null +++ b/bsps/sparc/include/ambapp.h @@ -0,0 +1,376 @@ +/** + * @file + * @ingroup sparc_bsp + * @defgroup amba AMBA + * @ingroup amba + * @brief AMBA Plug &Play routines + */ + +/* + * COPYRIGHT (c) 2009. + * Aeroflex Gaisler. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __AMBAPP_H__ +#define __AMBAPP_H__ + +/* Include VENDOR and DEVICE definitions */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Max supported AHB buses */ +#define AHB_BUS_MAX 6 + +struct ambapp_dev; +struct ambapp_core; +struct ambapp_apb_info; +struct ambapp_ahb_info; + +struct ambapp_dev { + struct ambapp_dev *next; /* Next */ + struct ambapp_dev *prev; /* Previous Device. If (this == + * rev->child) prev is bus bridge */ + struct ambapp_dev *children; /* Points to first device on sub-bus */ + void *owner; /* Owner of this AMBA device */ + unsigned char dev_type; /* AHB MST, AHB SLV or APB SLV*/ + unsigned char vendor; /* Vendor ID */ + unsigned short device; /* Device ID */ + int devinfo[0]; /* Device info (APB/AHB dep. on type) */ +}; + +#define AMBAPP_FLAG_FFACT_DIR 0x100 /* Frequency factor direction, 0=down, 1=up */ +#define AMBAPP_FLAG_FFACT 0x0f0 /* Frequency factor against top bus */ +#define AMBAPP_FLAG_MBUS 0x00c +#define AMBAPP_FLAG_SBUS 0x003 + +/* Get APB or AHB information from a AMBA device */ +#define DEV_TO_APB(adev) ((struct ambapp_apb_info *)((adev)->devinfo)) +#define DEV_TO_AHB(adev) ((struct ambapp_ahb_info *)((adev)->devinfo)) +#define DEV_TO_COMMON(adev) ((struct ambapp_common_info *)((adev)->devinfo)) +/* Convert address of ambapp_apb_info/ambapp_ahb_info into ambapp_dev */ +#define APB_TO_DEV(apb_info) ((struct ambapp_dev *)(unsigned int(apb_info) - \ + offsetof(struct ambapp_dev, devinfo))) +#define AHB_TO_DEV(ahb_info) ((struct ambapp_dev *)(unsigned int(ahb_info) - \ + offsetof(struct ambapp_dev, devinfo))) + +struct ambapp_common_info { + unsigned char irq; + unsigned char ver; + unsigned char ahbidx; /* AHB Bus Index */ +}; + +struct ambapp_apb_info { + /* COMMON */ + unsigned char irq; + unsigned char ver; + unsigned char ahbidx; /* AHB Bus Index */ + + /* APB SPECIFIC */ + unsigned int start; + unsigned int mask; +}; + +struct ambapp_ahb_info { + /* COMMON */ + unsigned char irq; + unsigned char ver; + unsigned char ahbidx; /* AHB Bus Index */ + + /* AHB SPECIFIC */ + unsigned int start[4]; + unsigned int mask[4]; + char type[4]; /* type[N] Determine type of start[N]-mask[N], + * 2=AHB Memory Space, 3=AHB I/O Space */ + unsigned int custom[3]; +}; + +/* Describes a complete AMBA Core. Each device may consist of 3 interfaces */ +struct ambapp_core { + char irq; /* irq=-1 indicate no IRQ */ + unsigned char vendor; + unsigned short device; + int index; /* Core index */ + struct ambapp_ahb_info *ahb_mst; + struct ambapp_ahb_info *ahb_slv; + struct ambapp_apb_info *apb_slv; +}; + +struct ambapp_ahb_bus { + unsigned int ioarea; /* AHB Bus IOAREA */ + unsigned int freq_hz; /* Frequency of AHB Bus */ + struct ambapp_dev *bridge;/* Bridge Device on Parent AHB Bus */ + struct ambapp_dev *dev; /* First Device on AHB Bus */ +}; + +struct ambapp_mmap { + unsigned int size; + unsigned int local_adr; + unsigned int remote_adr; +}; + +/* Complete AMBA PnP information */ +struct ambapp_bus { + struct ambapp_dev *root; /* AHB/APB Device Tree*/ + struct ambapp_mmap *mmaps; /* Memory MAP Array */ + struct ambapp_ahb_bus ahbs[AHB_BUS_MAX]; /* AHB Buses */ +}; + +/* + * Return values + * 0 - continue + * 1 - stop scanning + */ +typedef int (*ambapp_func_t)(struct ambapp_dev *dev, int index, void *arg); + +#define DEV_IS_FREE(dev) (dev->owner == NULL) +#define DEV_IS_ALLOCATED(dev) (dev->owner != NULL) + +/* Options to ambapp_for_each */ +#define OPTIONS_AHB_MSTS 0x00000001 +#define OPTIONS_AHB_SLVS 0x00000002 +#define OPTIONS_APB_SLVS 0x00000004 +#define OPTIONS_ALL_DEVS (OPTIONS_AHB_MSTS|OPTIONS_AHB_SLVS|OPTIONS_APB_SLVS) + +#define OPTIONS_FREE 0x00000010 +#define OPTIONS_ALLOCATED 0x00000020 +#define OPTIONS_ALL (OPTIONS_FREE|OPTIONS_ALLOCATED) + +/* Depth first search, Defualt is breath first search. */ +#define OPTIONS_DEPTH_FIRST 0x00000100 + +#define DEV_AHB_NONE 0 +#define DEV_AHB_MST 1 +#define DEV_AHB_SLV 2 +#define DEV_APB_SLV 3 + +/* Structures used to access Plug&Play information directly */ +struct ambapp_pnp_ahb { + const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */ + const unsigned int custom[3]; + const unsigned int mbar[4]; /* MASK, ADDRESS, TYPE, CACHABLE/PREFETCHABLE */ +}; + +struct ambapp_pnp_apb { + const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */ + const unsigned int iobar; /* MASK, ADDRESS, TYPE, CACHABLE/PREFETCHABLE */ +}; + +#define ambapp_pnp_vendor(id) (((id) >> 24) & 0xff) +#define ambapp_pnp_device(id) (((id) >> 12) & 0xfff) +#define ambapp_pnp_ver(id) (((id)>>5) & 0x1f) +#define ambapp_pnp_irq(id) ((id) & 0x1f) + +#define ambapp_pnp_start(mbar) (((mbar) & 0xfff00000) & (((mbar) & 0xfff0) << 16)) +#define ambapp_pnp_mbar_mask(mbar) (((mbar)>>4) & 0xfff) +#define ambapp_pnp_mbar_type(mbar) ((mbar) & 0xf) + +#define ambapp_pnp_apb_start(iobar, base) ((base) | ((((iobar) & 0xfff00000)>>12) & (((iobar) & 0xfff0)<<4)) ) +#define ambapp_pnp_apb_mask(iobar) ((~(ambapp_pnp_mbar_mask(iobar)<<8) & 0x000fffff) + 1) + +#define AMBA_TYPE_AHBIO_ADDR(addr,base_ioarea) ((unsigned int)(base_ioarea) | ((addr) >> 12)) + +#define AMBA_TYPE_APBIO 0x1 +#define AMBA_TYPE_MEM 0x2 +#define AMBA_TYPE_AHBIO 0x3 + +/* Copy Data from AMBA PnP I/O Area */ +typedef void *(*ambapp_memcpy_t)( + void *dest, /* Destination RAM copy */ + const void *src, /* Source AMBA PnP Address to copy from */ + int n, /* Number of bytes to be copied */ + struct ambapp_bus *abus /* Optional AMBA Bus pointer */ + ); + +/* Scan a AMBA Plug & Play bus and create all device structures describing the + * the devices. The devices will form a tree, where every node describes one + * interface. The resulting tree is placed in the location pointed to by root. + * + * Since it the tree is located in RAM it is easier to work with AMBA buses + * that is located over PCI and SpaceWire etc. + * + * \param ioarea The IO-AREA where Plug & Play information can be found. + * \param parent Used internally when recursing down a bridge. Set to NULL. + * \param mmaps Is used to perform address translation if needed. + * \param root Resulting device node tree root is stored here. + * + */ +extern int ambapp_scan( + struct ambapp_bus *abus, + unsigned int ioarea, + ambapp_memcpy_t memfunc, + struct ambapp_mmap *mmaps + ); + +/* Initialize the frequency [Hz] of all AHB Buses from knowing the frequency + * of one particular APB/AHB Device. + */ +extern void ambapp_freq_init( + struct ambapp_bus *abus, + struct ambapp_dev *dev, + unsigned int freq); + +/* Returns the frequency [Hz] of a AHB/APB device */ +extern unsigned int ambapp_freq_get( + struct ambapp_bus *abus, + struct ambapp_dev *dev); + +/* Iterates through all AMBA devices previously found, it calls func + * once for every device that match the search arguments. + * + * SEARCH OPTIONS + * All search options must be fulfilled, type of devices searched (options) + * and AMBA Plug&Play ID [VENDOR,DEVICE], before func() is called. The options + * can be use to search only for AMBA APB or AHB Slaves or AHB Masters for + * example. Note that when VENDOR=-1 or DEVICE=-1 it will match any vendor or + * device ID, this means setting both VENDOR and DEVICE to -1 will result in + * calling all devices matches the options argument. + * + * \param abus AMBAPP Bus to search + * \param options Search options, see OPTIONS_* above + * \param vendor AMBAPP VENDOR ID to search for + * \param device AMBAPP DEVICE ID to search for + * \param func Function called for every device matching search options + * \param arg Optional argument passed on to func + * + * func return value affects the search, returning a non-zero value will + * stop the search and ambapp_for_each will return immediately returning the + * same non-zero value. + * + * Return Values + * 0 - all devices was scanned + * non-zero - stopped by user function returning the non-zero value + */ +extern int ambapp_for_each( + struct ambapp_bus *abus, + unsigned int options, + int vendor, + int device, + ambapp_func_t func, + void *arg); + +/* Helper function for ambapp_for_each(), find a device by index. If pcount + * is NULL the first device is returned, else pcount is interpreted as index + * by decrementing the value until zero is reaced: *count=0 first device, + * *count=1 second device etc. + * + * The matching device is returned, which will stop the ambapp_for_each search. + * If zero is returned from ambapp_for_each no device matching the index was + * found + */ +extern int ambapp_find_by_idx(struct ambapp_dev *dev, int index, void *pcount); + +/* Get number of devices matching the options/vendor/device arguments, the + * arguments are passed onto ambapp_for_each(). + */ +extern int ambapp_dev_count(struct ambapp_bus *abus, unsigned int options, + int vendor, int device); + +/* Print short information about devices on the AMBA bus onto the console */ +extern void ambapp_print(struct ambapp_bus *abus, int show_depth); + +/* Mark a device taken (allocate), Owner field is set with owner Data. Returns + * -1 if device has already been allocated. + */ +extern int ambapp_alloc_dev(struct ambapp_dev *dev, void *owner); + +/* Owner field is cleared, which indicates that device is not allocated */ +extern void ambapp_free_dev(struct ambapp_dev *dev); + +/* Find AHB/APB Bridge or AHB/AHB Bridge Parent */ +extern struct ambapp_dev *ambapp_find_parent(struct ambapp_dev *dev); + +/* Returns bus depth (number of sub AHB buses) of device from root bus */ +extern int ambapp_depth(struct ambapp_dev *dev); + +/* Get Device Name from AMBA PnP name database */ +extern char *ambapp_device_id2str(int vendor, int id); + +/* Get Vendor Name from AMBA PnP name database */ +extern char *ambapp_vendor_id2str(int vendor); + +/* Set together VENDOR_DEVICE Name from AMBA PnP name database. Return length + * of C-string stored in buf not including string termination '\0'. + */ +extern int ambapp_vendev_id2str(int vendor, int id, char *buf); + +/* Help functions for backwards compability */ + +extern int ambapp_find_apbslv( + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_apb_info *dev); + +extern int ambapp_find_apbslv_next( + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_apb_info *dev, + int index); + +extern int ambapp_find_apbslvs_next( + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_apb_info *dev, + int index, + int maxno); + +extern int ambapp_find_apbslvs( + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_apb_info *dev, + int maxno); + +extern int ambapp_find_ahbslv( + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_ahb_info *dev); + +extern int ambapp_find_ahbslv_next( + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_ahb_info *dev, + int index); + +extern int ambapp_find_ahbslvs_next( + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_ahb_info *dev, + int index, + int maxno); + +extern int ambapp_find_ahbslvs( + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_ahb_info *dev, + int maxno); + + +extern int ambapp_get_number_ahbslv_devices( + struct ambapp_bus *abus, + int vendor, + int device); + +extern int ambapp_get_number_apbslv_devices( + struct ambapp_bus *abus, + int vendor, + int device); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/ambapp_ids.h b/bsps/sparc/include/ambapp_ids.h new file mode 100644 index 0000000000..c0c3547e94 --- /dev/null +++ b/bsps/sparc/include/ambapp_ids.h @@ -0,0 +1,317 @@ +/** + * @file + * @ingroup amba + * @brief AMBA Plug & Play Bus Vendor and Device IDs + */ + +/* + * COPYRIGHT (c) 2008. + * Gaisler Research + * + * This header file provide all known VENDOR and DEVICE IDs available + * in the AMBA Plug & Play information. Taken from GRLIB 3386. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef __AMBAPP_DEVS_H__ +#define __AMBAPP_DEVS_H__ + +/* Vendor codes */ +#define VENDOR_RESERVED 0x00 +#define VENDOR_GAISLER 0x01 +#define VENDOR_PENDER 0x02 +#define VENDOR_ESA 0x04 +#define VENDOR_ASTRIUM 0x06 +#define VENDOR_OPENCHIP 0x07 +#define VENDOR_OPENCORES 0x08 +#define VENDOR_CONTRIB 0x09 +#define VENDOR_DLR 0x0a +#define VENDOR_EONIC 0x0b +#define VENDOR_TELECOMPT 0x0c +#define VENDOR_DTU 0x0d +#define VENDOR_BSC 0x0e +#define VENDOR_RADIONOR 0x0f +#define VENDOR_GLEICHMANN 0x10 +#define VENDOR_MENTA 0x11 +#define VENDOR_SUN 0x13 +#define VENDOR_MOVIDIA 0x14 +#define VENDOR_ORBITA 0x17 +#define VENDOR_SIEMENS 0x1a +#define VENDOR_SYNOPSYS 0x21 +#define VENDOR_NASA 0x22 +#define VENDOR_NIIET 0x23 +#define VENDOR_S3 0x31 +#define VENDOR_ACTEL 0xac +#define VENDOR_APPLECORE 0xae +#define VENDOR_C3E 0xc3 +#define VENDOR_CBKPAN 0xc8 +#define VENDOR_CAL 0xca +#define VENDOR_CETON 0xcb +#define VENDOR_EMBEDDIT 0xea +#define VENDOR_NASA_GSFC 0xfc +#define VENDOR_AZST 0xfe + +/* Gaisler Research device id's */ +#define GAISLER_LEON2DSU 0x002 +#define GAISLER_LEON3 0x003 +#define GAISLER_LEON3DSU 0x004 +#define GAISLER_ETHAHB 0x005 +#define GAISLER_APBMST 0x006 +#define GAISLER_AHBUART 0x007 +#define GAISLER_SRCTRL 0x008 +#define GAISLER_SDCTRL 0x009 +#define GAISLER_SSRCTRL 0x00a +#define GAISLER_I2C2AHB 0x00b +#define GAISLER_APBUART 0x00c +#define GAISLER_IRQMP 0x00d +#define GAISLER_AHBRAM 0x00e +#define GAISLER_AHBDPRAM 0x00f +#define GAISLER_GRIOMMU2 0x010 +#define GAISLER_GPTIMER 0x011 +#define GAISLER_PCITRG 0x012 +#define GAISLER_PCISBRG 0x013 +#define GAISLER_PCIFBRG 0x014 +#define GAISLER_PCITRACE 0x015 +#define GAISLER_DMACTRL 0x016 +#define GAISLER_AHBTRACE 0x017 +#define GAISLER_DSUCTRL 0x018 +#define GAISLER_CANAHB 0x019 +#define GAISLER_GPIO 0x01a +#define GAISLER_AHBROM 0x01b +#define GAISLER_AHBJTAG 0x01c +#define GAISLER_ETHMAC 0x01d +#define GAISLER_SWNODE 0x01e +#define GAISLER_SPW 0x01f +#define GAISLER_AHB2AHB 0x020 +#define GAISLER_USBDC 0x021 +#define GAISLER_USB_DCL 0x022 +#define GAISLER_DDRMP 0x023 +#define GAISLER_ATACTRL 0x024 +#define GAISLER_DDRSP 0x025 +#define GAISLER_EHCI 0x026 +#define GAISLER_UHCI 0x027 +#define GAISLER_I2CMST 0x028 +#define GAISLER_SPW2 0x029 +#define GAISLER_AHBDMA 0x02a +#define GAISLER_NUHOSP3 0x02b +#define GAISLER_CLKGATE 0x02c +#define GAISLER_SPICTRL 0x02d +#define GAISLER_DDR2SP 0x02e +#define GAISLER_SLINK 0x02f +#define GAISLER_GRTM 0x030 +#define GAISLER_GRTC 0x031 +#define GAISLER_GRPW 0x032 +#define GAISLER_GRCTM 0x033 +#define GAISLER_GRHCAN 0x034 +#define GAISLER_GRFIFO 0x035 +#define GAISLER_GRADCDAC 0x036 +#define GAISLER_GRPULSE 0x037 +#define GAISLER_GRTIMER 0x038 +#define GAISLER_AHB2PP 0x039 +#define GAISLER_GRVERSION 0x03a +#define GAISLER_APB2PW 0x03b +#define GAISLER_PW2APB 0x03c +#define GAISLER_GRCAN 0x03d +#define GAISLER_I2CSLV 0x03e +#define GAISLER_U16550 0x03f +#define GAISLER_AHBMST_EM 0x040 +#define GAISLER_AHBSLV_EM 0x041 +#define GAISLER_GRTESTMOD 0x042 +#define GAISLER_ASCS 0x043 +#define GAISLER_IPMVBCTRL 0x044 +#define GAISLER_SPIMCTRL 0x045 +#define GAISLER_L4STAT 0x047 +#define GAISLER_LEON4 0x048 +#define GAISLER_LEON4DSU 0x049 +#define GAISLER_GRPWM 0x04a +#define GAISLER_PWM 0x04a +#define GAISLER_L2CACHE 0x04b +#define GAISLER_SDCTRL64 0x04c +#define GAISLER_GR1553B 0x04d +#define GAISLER_1553TST 0x04e +#define GAISLER_GRIOMMU 0x04f +#define GAISLER_FTAHBRAM 0x050 +#define GAISLER_FTSRCTRL 0x051 +#define GAISLER_AHBSTAT 0x052 +#define GAISLER_LEON3FT 0x053 +#define GAISLER_FTMCTRL 0x054 +#define GAISLER_FTSDCTRL 0x055 +#define GAISLER_FTSRCTRL8 0x056 +#define GAISLER_MEMSCRUB 0x057 +#define GAISLER_FTSDCTRL64 0x058 +#define GAISLER_NANDFCTRL 0x059 +#define GAISLER_N2DLLCTRL 0x05a +#define GAISLER_N2PLLCTRL 0x05b +#define GAISLER_SPI2AHB 0x05c +#define GAISLER_DDRSDMUX 0x05d +#define GAISLER_AHBFROM 0x05e +#define GAISLER_PCIEXP 0x05f +#define GAISLER_APBPS2 0x060 +#define GAISLER_VGACTRL 0x061 +#define GAISLER_LOGAN 0x062 +#define GAISLER_SVGACTRL 0x063 +#define GAISLER_T1AHB 0x064 +#define GAISLER_MP7WRAP 0x065 +#define GAISLER_GRSYSMON 0x066 +#define GAISLER_GRACECTRL 0x067 +#define GAISLER_ATAHBSLV 0x068 +#define GAISLER_ATAHBMST 0x069 +#define GAISLER_ATAPBSLV 0x06a +#define GAISLER_MIGDDR2 0x06b +#define GAISLER_LCDCTRL 0x06c +#define GAISLER_SWITCHOVER 0x06d +#define GAISLER_FIFOUART 0x06e +#define GAISLER_MUXCTRL 0x06f +#define GAISLER_B1553BC 0x070 +#define GAISLER_B1553RT 0x071 +#define GAISLER_B1553BRM 0x072 +#define GAISLER_GRAES 0x073 +#define GAISLER_AES 0x073 +#define GAISLER_ECC 0x074 +#define GAISLER_PCIF 0x075 +#define GAISLER_CLKMOD 0x076 +#define GAISLER_HAPSTRAK 0x077 +#define GAISLER_TEST_1X2 0x078 +#define GAISLER_WILD2AHB 0x079 +#define GAISLER_BIO1 0x07a +#define GAISLER_GRAESDMA 0x07b +#define GAISLER_AESDMA 0x07b +#define GAISLER_GRPCI2 0x07c +#define GAISLER_GRPCI2_DMA 0x07d +#define GAISLER_GRPCI2_TB 0x07e +#define GAISLER_MMA 0x07f +#define GAISLER_SATCAN 0x080 +#define GAISLER_CANMUX 0x081 +#define GAISLER_GRTMRX 0x082 +#define GAISLER_GRTCTX 0x083 +#define GAISLER_GRTMDESC 0x084 +#define GAISLER_GRTMVC 0x085 +#define GAISLER_GEFFE 0x086 +#define GAISLER_GPREG 0x087 +#define GAISLER_GRTMPAHB 0x088 +#define GAISLER_SPWCUC 0x089 +#define GAISLER_SPW2_DMA 0x08a +#define GAISLER_SPW_ROUTER 0x08b +#define GAISLER_SPWROUTER 0x08b +#define GAISLER_EDCLMST 0x08c +#define GAISLER_GRPWTX 0x08d +#define GAISLER_GRPWRX 0x08e +#define GAISLER_GPREGBANK 0x08f +#define GAISLER_MIG_7SERIES 0x090 +#define GAISLER_GRSPW2_SIST 0x091 +#define GAISLER_SGMII 0x092 +#define GAISLER_RGMII 0x093 +#define GAISLER_IRQGEN 0x094 +#define GAISLER_GRDMAC 0x095 +#define GAISLER_AHB2AVLA 0x096 +#define GAISLER_SPWTDP 0x097 +#define GAISLER_L3STAT 0x098 +#define GAISLER_GR740THS 0x099 +#define GAISLER_GRRM 0x09a +#define GAISLER_CMAP 0x09b +#define GAISLER_CPGEN 0x09c +#define GAISLER_AMBAPROT 0x09d +#define GAISLER_IGLOO2_BRIDGE 0x09e +#define GAISLER_AHB2AXI 0x09f +#define GAISLER_AXI2AHB 0x0a0 +#define GAISLER_FDIR_RSTCTRL 0x0a1 +#define GAISLER_APB3MST 0x0a2 +#define GAISLER_LRAM 0x0a3 +#define GAISLER_BOOTSEQ 0x0a4 +#define GAISLER_TCCOP 0x0a5 +#define GAISLER_SPIMASTER 0x0a6 +#define GAISLER_SPISLAVE 0x0a7 +#define GAISLER_GRSRIO 0x0a8 + +#define GAISLER_PIPEWRAPPER 0xffa +#define GAISLER_L2TIME 0xffd /* internal device: leon2 timer */ +#define GAISLER_L2C 0xffe /* internal device: leon2compat */ +#define GAISLER_PLUGPLAY 0xfff /* internal device: plug & play configarea */ + +/* European Space Agency device id's */ +#define ESA_LEON2 0x002 +#define ESA_LEON2APB 0x003 +#define ESA_IRQ 0x005 +#define ESA_TIMER 0x006 +#define ESA_UART 0x007 +#define ESA_CFG 0x008 +#define ESA_IO 0x009 +#define ESA_MCTRL 0x00f +#define ESA_PCIARB 0x010 +#define ESA_HURRICANE 0x011 +#define ESA_SPW_RMAP 0x012 +#define ESA_SPW2 0x012 +#define ESA_AHBUART 0x013 +#define ESA_SPWA 0x014 +#define ESA_BOSCHCAN 0x015 +#define ESA_IRQ2 0x016 +#define ESA_AHBSTAT 0x017 +#define ESA_WPROT 0x018 +#define ESA_WPROT2 0x019 +#define ESA_PDEC3AMBA 0x020 +#define ESA_PTME3AMBA 0x021 + +#define OPENCHIP_APBGPIO 0x001 +#define OPENCHIP_APBI2C 0x002 +#define OPENCHIP_APBSPI 0x003 +#define OPENCHIP_APBCHARLCD 0x004 +#define OPENCHIP_APBPWM 0x005 +#define OPENCHIP_APBPS2 0x006 +#define OPENCHIP_APBMMCSD 0x007 +#define OPENCHIP_APBNAND 0x008 +#define OPENCHIP_APBLPC 0x009 +#define OPENCHIP_APBCF 0x00a +#define OPENCHIP_APBSYSACE 0x00b +#define OPENCHIP_APB1WIRE 0x00c +#define OPENCHIP_APBJTAG 0x00d +#define OPENCHIP_APBSUI 0x00e + + +#define CONTRIB_CORE1 0x001 +#define CONTRIB_CORE2 0x002 + +#define GLEICHMANN_CUSTOM 0x001 +#define GLEICHMANN_GEOLCD01 0x002 +#define GLEICHMANN_DAC 0x003 +#define GLEICHMANN_HPI 0x004 +#define GLEICHMANN_SPI 0x005 +#define GLEICHMANN_HIFC 0x006 +#define GLEICHMANN_ADCDAC 0x007 +#define GLEICHMANN_SPIOC 0x008 +#define GLEICHMANN_AC97 0x009 + +#define SUN_T1 0x001 +#define SUN_S1 0x011 + +#define ORBITA_1553B 0x001 +#define ORBITA_429 0x002 +#define ORBITA_SPI 0x003 +#define ORBITA_I2C 0x004 +#define ORBITA_SMARTCARD 0x064 +#define ORBITA_SDCARD 0x065 +#define ORBITA_UART16550 0x066 +#define ORBITA_CRYPTO 0x067 +#define ORBITA_SYSIF 0x068 +#define ORBITA_PIO 0x069 +#define ORBITA_RTC 0x0c8 +#define ORBITA_COLORLCD 0x12c +#define ORBITA_PCI 0x190 +#define ORBITA_DSP 0x1f4 +#define ORBITA_USBHOST 0x258 +#define ORBITA_USBDEV 0x2bc + +#define NASA_EP32 0x001 + +#define CAL_DDRCTRL 0x188 + +#define ACTEL_COREMP7 0x001 + +/* Opencores device id's */ +#define OPENCORES_PCIBR 0x4 +#define OPENCORES_ETHMAC 0x5 + +#endif diff --git a/bsps/sparc/include/bsp/ahbstat.h b/bsps/sparc/include/bsp/ahbstat.h new file mode 100644 index 0000000000..71e2330f69 --- /dev/null +++ b/bsps/sparc/include/bsp/ahbstat.h @@ -0,0 +1,76 @@ +/* AHBSTAT driver interface + * + * COPYRIGHT (c) 2011. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __AHBSTAT_H__ +#define __AHBSTAT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* AHBSTAT Registers layout */ +struct ahbstat_regs { + volatile uint32_t status; + volatile uint32_t failing; +}; + +/* AHB fail interrupt callback to user. This function is declared weak so that + * the user can define a function pointer variable containing the address + * responsible for handling errors + * + * minor Index of AHBSTAT hardware + * regs Register address of AHBSTAT + * status AHBSTAT status register at IRQ + * failing_address AHBSTAT Failing address register at IRQ + * + * * User return + * 0: print error onto terminal with printk and reenable AHBSTAT + * 1: just re-enable AHBSTAT + * 2: just print error + * 3: do nothing, let user do custom handling + */ +extern int (*ahbstat_error)( + int minor, + struct ahbstat_regs *regs, + uint32_t status, + uint32_t failing_address); + +/* Get Last received AHB Error + * + * \param minor Index used to indentify a specific AHBSTAT core + * \param status Status register at time of error IRQ was recevied + * \param address Failing address register at time of error IRQ + * + * Return + * 0: No error received + * 1: Error Received, last status and address stored into argument pointers + * -1: No such AHBSTAT device + */ +extern int ahbstat_last_error(int minor, uint32_t *status, uint32_t *address); + +/* Get AHBSTAT registers address from minor. Can also be used to check if + * AHBSTAT hardware is present. + * + * Return + * NULL returned if no such device + * non-zero Address to AHBSTAT register + */ +extern struct ahbstat_regs *ahbstat_get_regs(int minor); + +/* Registers the AHBSTAT driver to the Driver Manager */ +void ahbstat_register_drv (void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/apbuart.h b/bsps/sparc/include/bsp/apbuart.h new file mode 100644 index 0000000000..a324805d7d --- /dev/null +++ b/bsps/sparc/include/bsp/apbuart.h @@ -0,0 +1,60 @@ +/** + * @file + * @ingroup sparc_bsp + * @defgroup uart UART + * @ingroup uart + * @brief Driver interface for APBUART + */ + +/* + * COPYRIGHT (c) 2007. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef __APBUART_H__ +#define __APBUART_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define APBUART_CTRL_RE 0x1 +#define APBUART_CTRL_TE 0x2 +#define APBUART_CTRL_RI 0x4 +#define APBUART_CTRL_TI 0x8 +#define APBUART_CTRL_PS 0x10 +#define APBUART_CTRL_PE 0x20 +#define APBUART_CTRL_FL 0x40 +#define APBUART_CTRL_LB 0x80 +#define APBUART_CTRL_EC 0x100 +#define APBUART_CTRL_TF 0x200 +#define APBUART_CTRL_RF 0x400 +#define APBUART_CTRL_BI 0x1000 +#define APBUART_CTRL_DI 0x2000 +#define APBUART_CTRL_FA 0x80000000 + +#define APBUART_STATUS_DR 0x1 +#define APBUART_STATUS_TS 0x2 +#define APBUART_STATUS_TE 0x4 +#define APBUART_STATUS_BR 0x8 +#define APBUART_STATUS_OV 0x10 +#define APBUART_STATUS_PE 0x20 +#define APBUART_STATUS_FE 0x40 +#define APBUART_STATUS_ERR 0x78 +#define APBUART_STATUS_TH 0x80 +#define APBUART_STATUS_RH 0x100 +#define APBUART_STATUS_TF 0x200 +#define APBUART_STATUS_RF 0x400 + +#ifdef __cplusplus +} +#endif + +#endif /* __APBUART_H__ */ diff --git a/bsps/sparc/include/bsp/apbuart_cons.h b/bsps/sparc/include/bsp/apbuart_cons.h new file mode 100644 index 0000000000..d0ac9244af --- /dev/null +++ b/bsps/sparc/include/bsp/apbuart_cons.h @@ -0,0 +1,16 @@ +/* APBUART Console driver interface + * + * COPYRIGHT (c) 2015. + * Cobham Gaisler. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __APBUART_CONS_H__ +#define __APBUART_CONS_H__ + +void apbuart_cons_register_drv (void); + +#endif diff --git a/bsps/sparc/include/bsp/apbuart_termios.h b/bsps/sparc/include/bsp/apbuart_termios.h new file mode 100644 index 0000000000..40377c1023 --- /dev/null +++ b/bsps/sparc/include/bsp/apbuart_termios.h @@ -0,0 +1,60 @@ +/* + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * Modified for LEON3 BSP. + * COPYRIGHT (c) 2004. + * Gaisler Research. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef APBUART_TERMIOS_H +#define APBUART_TERMIOS_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct apbuart_context { + rtems_termios_device_context base; + struct apbuart_regs *regs; + unsigned int freq_hz; + rtems_vector_number irq; + volatile int sending; + char *buf; +}; + +const rtems_termios_device_handler apbuart_handler_interrupt; + +const rtems_termios_device_handler apbuart_handler_polled; + +/* + * apbuart_outbyte_polled + * + * This routine transmits a character using polling. + */ +void apbuart_outbyte_polled( + struct apbuart_regs *regs, + unsigned char ch, + int do_cr_on_newline, + int wait_sent +); + +/* + * apbuart_inbyte_nonblocking + * + * This routine polls for a character. + */ +int apbuart_inbyte_nonblocking(struct apbuart_regs *regs); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* APBUART_TERMIOS_H */ diff --git a/bsps/sparc/include/bsp/b1553brm.h b/bsps/sparc/include/bsp/b1553brm.h new file mode 100644 index 0000000000..eba0716f75 --- /dev/null +++ b/bsps/sparc/include/bsp/b1553brm.h @@ -0,0 +1,178 @@ +/** + * @file + * @ingroup sparc_bsp + * @defgroup 1553 B1553BRM + * @ingroup 1553 + * @brief B1553BRM device driver + */ + +/* + * COPYRIGHT (c) 2006. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __B1553BRM_H__ +#define __B1553BRM_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct brm_reg { + volatile unsigned int ctrl; /* 0x00 */ + volatile unsigned int oper; /* 0x04 */ + volatile unsigned int cur_cmd; /* 0x08 */ + volatile unsigned int imask; /* 0x0C */ + volatile unsigned int ipend; /* 0x10 */ + volatile unsigned int ipoint; /* 0x14 */ + volatile unsigned int bit_reg; /* 0x18 */ + volatile unsigned int ttag; /* 0x1C */ + volatile unsigned int dpoint; /* 0x20 */ + volatile unsigned int sw; /* 0x24 */ + volatile unsigned int initcount; /* 0x28 */ + volatile unsigned int mcpoint; /* 0x2C */ + volatile unsigned int mdpoint; /* 0x30 */ + volatile unsigned int mbc; /* 0x34 */ + volatile unsigned int mfilta; /* 0x38 */ + volatile unsigned int mfiltb; /* 0x3C */ + volatile unsigned int rt_cmd_leg[16]; /* 0x40-0x80 */ + volatile unsigned int enhanced; /* 0x84 */ + + volatile unsigned int dummy[31]; + + volatile unsigned int w_ctrl; /* 0x100 */ + volatile unsigned int w_irqctrl; /* 0x104 */ + volatile unsigned int w_ahbaddr; /* 0x108 */ +}; + +struct bm_msg { + unsigned short miw; + unsigned short cw1; + unsigned short cw2; + unsigned short sw1; + unsigned short sw2; + unsigned short time; + unsigned short data[32]; +}; + +struct rt_msg { + unsigned short miw; + unsigned short time; + unsigned short data[32]; + unsigned short desc; +}; + +/* + * rtaddr[0] and subaddr[0] : RT address and subaddress (for rt-rt receive addresses) + * rtaddr[1] and subaddr[1] : Only for RT-RT. Transmit addresses. + * + * wc : word count, or mode code if subaddress 0 or 31. + * + * ctrl, bit 0 (TR) : 1 - transmit, 0 - receive. Ignored for rt-rt + * bit 1 (RTRT) : 1 - rt to rt, 0 - normal + * bit 2 (AB) : 1 - Bus B, 0 - Bus A + * bit 4:3 (Retry) : 1 - 1, 2 - 2, 3 - 3, 0 - 4 + * bit 5 (END) : End of list + * bit 15 (BAME) : Message error. Set by BRM if protocol error is detected + * + * tsw[0] : status word + * tsw[1] : Only for rt-rt, status word 2 + * + * data : data to be transmitted, or received data + * + */ +struct bc_msg { + unsigned char rtaddr[2]; + unsigned char subaddr[2]; + unsigned short wc; + unsigned short ctrl; + unsigned short tsw[2]; + unsigned short data[32]; +}; + +/* BC control bits */ +#define BC_TR 0x0001 +#define BC_RTRT 0x0002 +#define BC_BUSA 0x0004 +#define BC_EOL 0x0020 +#define BC_SKIP 0x0040 +#define BC_BAME 0x8000 + +#define BRM_MBC_IRQ 1 /* Monitor Block Counter irq */ +#define BRM_CBA_IRQ 2 /* Command Block Accessed irq */ +#define BRM_RTF_IRQ 4 /* Retry Fail irq */ +#define BRM_ILLOP_IRQ 8 /* Illogical Opcode irq */ +#define BRM_BC_ILLCMD_IRQ 16 /* BC Illocigal Command irq */ +#define BRM_EOL_IRQ 32 /* End Of List irq */ +#define BRM_RT_ILLCMD_IRQ 128 /* RT Illegal Command irq */ +#define BRM_IXEQ0_IRQ 256 /* Index Equal Zero irq */ +#define BRM_BDRCV_IRQ 512 /* Broadcast Command Received irq */ +#define BRM_SUBAD_IRQ 1024 /* Subaddress Accessed irq */ +#define BRM_MERR_IRQ 2048 /* Message Error irq */ +#define BRM_TAPF_IRQ 8192 /* Terminal Address Parity Fail irq */ +#define BRM_WRAPF_IRQ 16384 /* Wrap Fail irq */ +#define BRM_DMAF_IRQ 32768 /* DMA Fail irq */ + + +#define BRM_SET_MODE 0 +#define BRM_SET_BUS 1 +#define BRM_SET_MSGTO 2 +#define BRM_SET_RT_ADDR 3 +#define BRM_SET_STD 4 +#define BRM_SET_BCE 5 +#define BRM_TX_BLOCK 7 +#define BRM_RX_BLOCK 8 + +#define BRM_DO_LIST 10 +#define BRM_LIST_DONE 11 + +#define BRM_CLR_STATUS 12 +#define BRM_GET_STATUS 13 +#define BRM_SET_EVENTID 14 + +#define GET_ERROR_DESCRIPTOR(event_in) (event_in>>16) + + +#define BRM_MODE_BC 0x0 +#define BRM_MODE_RT 0x1 +#define BRM_MODE_BM 0x2 +#define BRM_MODE_BM_RT 0x3 /* both RT and BM */ + +#define BRM_FREQ_12MHZ 0 +#define BRM_FREQ_16MHZ 1 +#define BRM_FREQ_20MHZ 2 +#define BRM_FREQ_24MHZ 3 +#define BRM_FREQ_MASK 0x3 + +#define CLKDIV_MASK 0xf + +#define CLKSEL_MASK 0x7 + +void b1553brm_register_drv(void); + +/* Default initialization of the RT legalization registers. The values in this + * array are written to the registers on boot driver initialization and when + * the user set the mode to RT-mode by calling ioctl(BRM_SET_MODE). Thus, + * update the array first then call ioctl(BRM_SET_MODE) for the changes to have + * an affect. Note that this affects all B1553BRM RTs in the system. + */ +extern unsigned short b1553brm_rt_cmd_legalize[16]; + +/* Print information about all BRM devices handled by this driver */ +void b1553brm_print(int options); + +/* Print information about one BRM device */ +void b1553brm_print_dev(struct drvmgr_dev *dev, int options); + +#ifdef __cplusplus +} +#endif + +#endif /* __BRM_H__ */ + diff --git a/bsps/sparc/include/bsp/b1553rt.h b/bsps/sparc/include/bsp/b1553rt.h new file mode 100644 index 0000000000..fbe4b706de --- /dev/null +++ b/bsps/sparc/include/bsp/b1553rt.h @@ -0,0 +1,79 @@ +/* B1553RT driver interface + * + * COPYRIGHT (c) 2009. + * Aeroflex Gaisler AB + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __B1553RT_H__ +#define __B1553RT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct rt_reg { + volatile unsigned int stat; /* 0x00 */ + volatile unsigned int ctrl; /* 0x04 */ + volatile unsigned int vword; /* 0x08 */ + volatile unsigned int irq; /* 0x0C */ + volatile unsigned int addr; /* 0x10 */ + volatile unsigned int ipm; /* 0x14 */ +}; + + +struct rt_msg { + unsigned short miw; + unsigned short time; + unsigned short data[32]; + unsigned short desc; +}; + +#define RT_FREQ_12MHZ 0 +#define RT_FREQ_16MHZ 1 +#define RT_FREQ_20MHZ 2 +#define RT_FREQ_24MHZ 3 +#define RT_FREQ_MASK 0x3 + +/* IOCTLs */ +#define RT_SET_ADDR 3 +#define RT_SET_BCE 5 +#define RT_RX_BLOCK 8 +#define RT_CLR_STATUS 12 +#define RT_GET_STATUS 13 +#define RT_SET_EVENTID 14 + +#define RT_SET_VECTORW 32 +#define RT_SET_EXTMDATA 33 + +#define RT_ILLCMD_IRQ 128 +#define RT_MERR_IRQ 2048 +#define RT_DMAF_IRQ 32768 /* DMA Fail irq */ + +#define RT_TSW_OK (1<<14) +#define RT_TSW_BUS (1<<13) +#define RT_TSW_BC (1<<12) +#define RT_TSW_LPBKERRB (1<<11) +#define RT_TSW_LPBKERRA (1<<10) +#define RT_TSW_ILL (1<<9) +#define RT_TSW_MEM (1<<8) +#define RT_TSW_MAN (1<<7) +#define RT_TSW_PAR (1<<6) +#define RT_TSW_WC (1<<5) + +void b1553rt_print_dev(struct drvmgr_dev *dev, int options); +void b1553rt_print(int options); + +void b1553rt_register_drv(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __RT_H__ */ + diff --git a/bsps/sparc/include/bsp/canmux.h b/bsps/sparc/include/bsp/canmux.h new file mode 100644 index 0000000000..02727f44c7 --- /dev/null +++ b/bsps/sparc/include/bsp/canmux.h @@ -0,0 +1,32 @@ +/* + * Header file for RTEMS CAN_MUX driver + * + * COPYRIGHT (c) 2008. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __CANMUX_H__ +#define __CANMUX_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Driver interface */ +int canmux_register(void); + +/* ioctl calls */ +#define CANMUX_IOC_BUSA_SATCAN 1 +#define CANMUX_IOC_BUSA_OCCAN1 2 +#define CANMUX_IOC_BUSB_SATCAN 3 +#define CANMUX_IOC_BUSB_OCCAN2 4 + +#ifdef __cplusplus +} +#endif + +#endif /* __CANMUX_H__ */ diff --git a/bsps/sparc/include/bsp/cons.h b/bsps/sparc/include/bsp/cons.h new file mode 100644 index 0000000000..c30e41cf14 --- /dev/null +++ b/bsps/sparc/include/bsp/cons.h @@ -0,0 +1,42 @@ +/* Console driver interface to UART drivers + * + * - First console device that has System Console flag set will be + * system console. + * - If none of the registered console devices has system console set, + * the first is registered device is used, unless it has + * + * COPYRIGHT (c) 2010. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __CONS_H__ +#define __CONS_H__ + +#include + +struct console_dev; + +#define CONSOLE_FLAG_SYSCON 0x01 +#define CONSOLE_FLAG_SYSCON_GRANT 0x02 + +struct console_dev { + rtems_termios_device_context base; + /* Set CONSOLE_FLAG_SYSCON to request this device to be system console + * and/or debug console. CONSOLE_FLAG_SYSCON_GRANT will be set on the + * device which was selected as system console. + */ + int flags; + char *fsname; /* File system prefix */ + const rtems_termios_device_handler *handler; +}; + +extern void console_dev_register(struct console_dev *dev); +#if 0 +extern void console_dev_unregister(struct console_dev *dev); +#endif + +#endif diff --git a/bsps/sparc/include/bsp/debug_defs.h b/bsps/sparc/include/bsp/debug_defs.h new file mode 100644 index 0000000000..58f7460f52 --- /dev/null +++ b/bsps/sparc/include/bsp/debug_defs.h @@ -0,0 +1,45 @@ +/** + * @file + * @ingroup bsp_kit + * @defgroup sparc_bsp SPARC + * @ingroup sparc_bsp + * @brief Debug Definitions + */ + +#ifndef __DEBUG_DEFS_H__ +#define __DEBUG_DEFS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef DEBUG + + #ifndef DEBUG_FLAGS + #define DEBUG_FLAGS 0 + #endif + + #define DBG(fmt, args...) do { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); } while(0) + #define DBG2(fmt) do { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__); } while(0) + #define DBGC(c,fmt, args...) do { if (DEBUG_FLAGS & c) { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); }} while(0) + +#else + + #define DBG(fmt, args...) + #define DBG2(fmt, args...) + #define DBGC(c, fmt, args...) + +#endif + +#ifdef DEBUGFUNCS + #define FUNCDBG() do { printk("%s\n\r",__FUNCTION__); } while(0) +#else + #define FUNCDBG() +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DEBUG_DEFS_H__ */ diff --git a/bsps/sparc/include/bsp/genirq.h b/bsps/sparc/include/bsp/genirq.h new file mode 100644 index 0000000000..673be173b1 --- /dev/null +++ b/bsps/sparc/include/bsp/genirq.h @@ -0,0 +1,132 @@ +/* General Shared Interrupt handling function interface + * + * The functions does not manipulate the IRQ controller or the + * interrupt level of the CPU. It simply helps the caller with + * managing shared interrupts where multiple interrupt routines + * share on interrupt vector/number. + * + * COPYRIGHT (c) 2008. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GENIRQ_H__ +#define __GENIRQ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*genirq_handler)(void *arg); +typedef void* genirq_t; + +struct genirq_stats { + unsigned int irq_cnt; +}; + +/* Initialize the genirq interface. Must be the first function + * called. + * + * Returns zero on success, otherwise failure. + */ +extern genirq_t genirq_init(int number_of_irqs); + +/* Free the dynamically allocated memory that the genirq interface has + * allocated. Also the handlers will be freed. + * + * Returns zero on success, otherwise failure. + */ +extern void genirq_destroy(genirq_t d); + +/* Check IRQ number validity + * + * Returns zero for valid IRQ numbers, -1 of invalid IRQ numbers. + */ +extern int genirq_check(genirq_t d, int irq); + +/* Allocate one ISR handler and initialize it. Input to genirq_register(). + * + * \param isr The interrupt service routine called upon IRQ + * \param arg The argument given to isr() when called. + * + * Returns a pointer on success, on failure NULL is returned. + */ +extern void *genirq_alloc_handler(genirq_handler isr, void *arg); + +/* Free handler memory */ +#define genirq_free_handler(handler) free(handler) + +/* Register shared interrupt handler previously initialized with + * genirq_alloc_handler(). + * + * NOTE: internal list structures are accessed and needs to be protected by + * spin-locks/IRQ disable by the user to guarantee a correct behaviour. + * + * \param irq The interrupt number to register ISR on + * \param handler Install the pre- allocated and initialized handler. + * + * Return Values + * -1 = Failed + * 0 = Handler registered Successfully, first handler on this IRQ + * 1 = Handler registered Successfully, _not_ first handler on this IRQ + */ +extern int genirq_register(genirq_t d, int irq, void *handler); + +/* Unregister an previous registered interrupt handler. It is the user's + * responsibility to free the handler returned by genirq_unregister(). + * + * NOTE: internal list structures are accessed and needs to be protected by + * spin-locks/IRQ disable by the user to guarantee a correct behaviour. + * + * Return Values + * NULL = ISR not registered before or unable to unregister enabled ISR + * Pointer = ISR sucessfully unregistered. Returned is the handler pointer + * previously allocated with genirq_alloc_handler(). + */ +extern void *genirq_unregister(genirq_t d, int irq, + genirq_handler isr, void *arg); + +/* Enables IRQ only for this isr[arg] combination. Records if this + * is the first interrupt enable, only then must interrupts be enabled + * on the interrupt controller. + * + * NOTE: internal list structures are accessed and needs to be protected by + * spin-locks/IRQ disable by the user to guarantee a correct behaviour. + * + * Return values + * -1 = Failure, for example isr[arg] not registered on this irq + * 0 = IRQ must be enabled, it is the first IRQ handler to be enabled + * 1 = IRQ has already been enabled, either by isr[arg] or by another handler + */ +extern int genirq_enable(genirq_t d, int irq, genirq_handler isr, void *arg); + +/* Disables IRQ only for this isr[arg] combination. Records if this + * is the only interrupt handler that is enabled on this IRQ, only then + * must interrupts be disabled on the interrupt controller. + * + * NOTE: internal list structures are accessed and needs to be protected by + * spin-locks/IRQ disable by the user to guarantee a correct behaviour. + * + * Return values + * -1 = Failure, for example isr[arg] not registered on this irq + * 0 = IRQ must be disabled, no ISR are enabled for this IRQ + * 1 = ISR has already been disabled, or other ISRs are still enabled + */ +extern int genirq_disable(genirq_t d, int irq, genirq_handler isr, void *arg); + +/* Must be called by user when an IRQ has fired, the argument 'irq' + * is the IRQ number of the IRQ which was fired. + * + * NOTE: internal list structures are accessed and needs to be protected by + * spin-locks/IRQ disable by the user to guarantee a correct behaviour. + */ +extern void genirq_doirq(genirq_t d, int irq); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gnatcommon.h b/bsps/sparc/include/bsp/gnatcommon.h new file mode 100644 index 0000000000..1a04449293 --- /dev/null +++ b/bsps/sparc/include/bsp/gnatcommon.h @@ -0,0 +1,19 @@ +#ifndef __GNATCOMMON_H +#define __GNATCOMMON_H + +/* + * Support for gnat/rtems interrupts and exception handling. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +void __gnat_install_handler (void); +void __gnat_install_handler_common (int t1, int t2); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gpiolib.h b/bsps/sparc/include/bsp/gpiolib.h new file mode 100644 index 0000000000..f82d4fa2c2 --- /dev/null +++ b/bsps/sparc/include/bsp/gpiolib.h @@ -0,0 +1,94 @@ +/* GPIO Library interface + * + * COPYRIGHT (c) 2009. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GPIOLIB_H__ +#define __GPIOLIB_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* GPIO Config of one GPIO port */ +struct gpiolib_config { + char mask; /* 0=Masked/1=Unmasked IRQ */ + char irq_level; /* Edge or Level triggered IRQ */ + char irq_polarity; /* Polarity of IRQ */ +}; + +#define GPIOLIB_IRQ_EDGE 0 +#define GPIOLIB_IRQ_LEVEL 1 + +#define GPIOLIB_IRQ_POL_LOW 0 +#define GPIOLIB_IRQ_POL_HIGH 1 + +/* Libarary initialize function must be called befor any other */ +extern int gpiolib_initialize(void); + +/*** User Interface ***/ + +extern void *gpiolib_open(int port); +extern void *gpiolib_open_by_name(char *devName); +extern void gpiolib_close(void *handle); + +/* Show the current status one or all GPIO ports in the system. + * Int port is port nunber, if port = -1 selects all ports. + * + * If port != -1, handle is used to get port. + * If port != -1, handle == NULL, then port is used as port number + */ +extern void gpiolib_show(int port, void *handle); + +extern int gpiolib_set_config(void *handle, struct gpiolib_config *cfg); +extern int gpiolib_set(void *handle, int dir, int val); +extern int gpiolib_get(void *handle, int *inval); +extern int gpiolib_irq_clear(void *handle); +extern int gpiolib_irq_enable(void *handle); +extern int gpiolib_irq_disable(void *handle); +extern int gpiolib_irq_mask(void *handle); +extern int gpiolib_irq_unmask(void *handle); +extern int gpiolib_irq_force(void *handle); +extern int gpiolib_irq_register(void *handle, void *func, void *arg); + +/*** Driver Interface ***/ + +struct gpiolib_info { + char devName[64]; +}; + +struct gpiolib_drv_ops { + int (*config)(void *handle, struct gpiolib_config *cfg); + int (*get)(void *handle, int *val); + int (*irq_opts)(void *handle, unsigned int options); + int (*irq_register)(void *handle, void *func, void *arg); + int (*open)(void *handle); + int (*set)(void *handle, int dir, int outval); + int (*show)(void *handle); + int (*get_info)(void *handle, struct gpiolib_info *pinfo); +}; + +#define GPIOLIB_IRQ_ENABLE 0x01 +#define GPIOLIB_IRQ_DISABLE 0x02 +#define GPIOLIB_IRQ_CLEAR 0x04 +#define GPIOLIB_IRQ_FORCE 0x08 +#define GPIOLIB_IRQ_MASK 0x10 +#define GPIOLIB_IRQ_UNMASK 0x20 + +struct gpiolib_drv { + struct gpiolib_drv_ops *ops; +}; + +/* Register a GPIO port */ +extern int gpiolib_drv_register(struct gpiolib_drv *drv, void *handle); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gptimer.h b/bsps/sparc/include/bsp/gptimer.h new file mode 100644 index 0000000000..ee0120d2bd --- /dev/null +++ b/bsps/sparc/include/bsp/gptimer.h @@ -0,0 +1,30 @@ +/* GPTIMER and GRTIMER timer driver + * + * COPYRIGHT (c) 2015. + * Cobham Gaisler. + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef __GPTIMER_H__ +#define __GPTIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* The GPTIMER_INFO_AVAIL define set from the BSP bsp.h configures if the + * Driver manager info interface is built. + */ + +/* Register GPTIMER and GRTIMER driver to Driver Manager */ +void gptimer_register_drv (void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gr1553b.h b/bsps/sparc/include/bsp/gr1553b.h new file mode 100644 index 0000000000..006417b530 --- /dev/null +++ b/bsps/sparc/include/bsp/gr1553b.h @@ -0,0 +1,369 @@ +/* GR1553B driver, used by BC, RT and/or BM driver + * + * COPYRIGHT (c) 2010. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * OVERVIEW + * ======== + * This driver controls the GR1553B device regardless of interfaces supported + * (BC, RT and/or BM). The device can be located at an on-chip AMBA or an + * AMBA-over-PCI bus. This driver provides an interface for the BC, RT and BM + * drivers to use. Since the different interfaces are accessed over the same + * register interface on the same core, the other drivers must share a GR1553B + * device. Any combination of interface functionality is supported, but the RT + * and BC functionality can nnot be used simultaneously due to hardware + * limitation. + * + */ + +#ifndef __GR1553B_H__ +#define __GR1553B_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* The GR1553B registers */ +struct gr1553b_regs { + /* Common Registers */ + volatile uint32_t irq; /* 0x00 IRQ register */ + volatile uint32_t imask; /* 0x04 IRQ enable mask */ + int unused0[(0x10-0x08)/4]; + volatile uint32_t hwcfg; /* 0x10 HW config register */ + + int unused1[(0x40-0x14)/4]; /* Padding */ + + /* BC Registers */ + volatile uint32_t bc_stat; /* 0x40 BC status */ + volatile uint32_t bc_ctrl; /* 0x44 BC Action register */ + volatile uint32_t bc_bd; /* 0x48 BC transfer list pointer */ + volatile uint32_t bc_abd; /* 0x4c BC async list pointer */ + volatile uint32_t bc_timer; /* 0x50 BC timer register */ + volatile uint32_t bc_wake; /* 0x54 BC wakeup control register */ + volatile uint32_t bc_irqptr; /* 0x58 BC transfer IRQ pointer */ + volatile uint32_t bc_busmsk; /* 0x5C BC per-RT bus mask register */ + + int unused2[(0x68-0x60)/4]; /* Padding */ + + volatile uint32_t bc_slot; /* 0x68 BC Current BD pointer */ + volatile uint32_t bc_aslot; /* 0x6c BC Current async BD pointer */ + + int unused3[(0x80-0x70)/4]; /* Padding */ + + /* RT Registers */ + volatile uint32_t rt_stat; /* 0x80 RT status */ + volatile uint32_t rt_cfg; /* 0x84 RT config register */ + volatile uint32_t rt_stat2; /* 0x88 RT bus status bits */ + volatile uint32_t rt_statw; /* 0x8c RT status words */ + volatile uint32_t rt_sync; /* 0x90 RT bus synchronize */ + volatile uint32_t rt_tab; /* 0x94 RT subaddress table base */ + volatile uint32_t rt_mcctrl; /* 0x98 RT valid mode code mask */ + int unused4[(0xa4-0x9c)/4]; + volatile uint32_t rt_ttag; /* 0xa4 RT time tag register */ + int unused5; /* 0xa8 RESERVED */ + volatile uint32_t rt_evsz; /* 0xac RT event log end pointer */ + volatile uint32_t rt_evlog; /* 0xb0 RT event log position */ + volatile uint32_t rt_evirq; /* 0xb4 RT event log IRQ position */ + + int unused6[(0xc0-0xb8)/4]; /* Padding */ + + /* BM Registers */ + volatile uint32_t bm_stat; /* 0xc0 BM status */ + volatile uint32_t bm_ctrl; /* 0xc4 BM control register */ + volatile uint32_t bm_adr; /* 0xc8 BM address filter */ + volatile uint32_t bm_subadr; /* 0xcc BM subaddress filter */ + volatile uint32_t bm_mc; /* 0xd0 BM mode code filter */ + volatile uint32_t bm_start; /* 0xd4 BM log start address */ + volatile uint32_t bm_end; /* 0xd8 BM log size/alignment mask */ + volatile uint32_t bm_pos; /* 0xdc BM log position */ + volatile uint32_t bm_ttag; /* 0xe0 BM time tag register */ +}; + +#define GR1553BC_KEY 0x15520000 +#define GR1553RT_KEY 0x15530000 + +/* IRQ Definitions */ +#define GR1553BC_IRQLOG_SIZE 64 +#define GR1553BC_IRQLOG_CNT (GR1553BC_IRQLOG_SIZE/sizeof(uint32_t)) + +/*** IRQ Flag Register ***/ +#define GR1553B_IRQ_BCEV_BIT 0 +#define GR1553B_IRQ_BCD_BIT 1 +#define GR1553B_IRQ_BCWK_BIT 2 +#define GR1553B_IRQ_RTEV_BIT 8 +#define GR1553B_IRQ_RTD_BIT 9 +#define GR1553B_IRQ_RTTE_BIT 10 +#define GR1553B_IRQ_BMD_BIT 16 +#define GR1553B_IRQ_BMTOF_BIT 17 + +#define GR1553B_IRQ_BCEV (1< +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register GR1553B driver needed by BC driver */ +extern void gr1553bc_register(void); + +/* A BC descriptor accessed as is */ +struct gr1553bc_bd_raw { + volatile uint32_t words[4]; +}; + +/* A BC descriptor accessed as a transfer descriptor */ +struct gr1553bc_bd_tr { + volatile uint32_t settings[2]; + volatile uint32_t dptr; + volatile uint32_t status; +}; + +/* A BC descriptor accessed as a conditional descriptor */ +struct gr1553bc_bd_cond { + volatile uint32_t cond; + volatile uint32_t bdptr; + volatile uint32_t padding[2]; +}; + +/* A BC descriptor accessed any way */ +union gr1553bc_bd { + struct gr1553bc_bd_raw raw; + struct gr1553bc_bd_tr tr; + struct gr1553bc_bd_cond cond; +}; + +/* Current state of the BC hardware */ +struct gr1553bc_status { + unsigned int status; + unsigned int time; +}; + +#define KEEP_TIMESLOT 0x10 +/* Initialize a BC descriptor. The words written is controllable by + * the flags argument. + * + * flags: + * bit[N=0..3]: 1 = set BD wordN according to argument wordN, + * 0 = do not modify BD wordN + * + * If bit KEEP_TIMESLOT is set the time slot of word0 is preserved, + * this bit only have an affect when the descriptor is a transfer + * descriptor. + */ +extern void gr1553bc_bd_init( + union gr1553bc_bd *bd, + unsigned int flags, + uint32_t word0, + uint32_t word1, + uint32_t word2, + uint32_t word3 + ); + +/* Initialize a Transfer descriptor + * + * Arguments: + * struct gr1553bc_bd_tr *bd + * uint32_t setting0 + * uint32_t setting1 + * uint32_t data + * uint32_t status + */ +#define gr1553bc_bd_tr_init(bd, set0, set1, data, status) \ + gr1553bc_bd_init((union gr1553bc_bd *)bd,\ + 0xf, set0, set1, data, status) +/* Initializa a Condition descriptor + * + * Arguments: + * struct gr1553bc_bd_cond *bd + * uint32_t cond + * uint32_t jump_adr + */ +#define gr1553bc_bd_cond_init(bd, cond, jump_adr) \ + gr1553bc_bd_init((union gr1553bc_bd *)bd, \ + 0xf, cond, jump_adr, 0, 0) + +/* Size of a descriptor */ +#define GR1553BC_BD_SIZE sizeof(struct gr1553bc_bd_raw) + +/* Alignment of a descriptor */ +#define GR1553BC_BD_ALIGN 16 + +/* End of list marker */ +#define GR1553BC_TR_EOL 0x80ffffff + +#define GR1553BC_BD_TYPE 0x80000000 + +/* Condition descriptor bits */ +#define GR1553BC_UNCOND_JMP 0x820000ff +#define GR1553BC_UNCOND_IRQ 0x860000ff +#define GR1553BC_UNCOND_NOJMP 0x82000000 + +/* Transfer descriptor bits */ +#define GR1553BC_TR_DUMMY_0 0x00000000 +#define GR1553BC_TR_DUMMY_1 0x80000000 + +#define GR1553BC_TR_TIME 0x0000ffff + +#define GR1553BC_TR_EXTTRIG 0x40000000 + +/* Take a GR1553BC hardware device identified by instance index (minor). + * A pointer is returned that is used internally by the GR1553BC + * driver, it is used as an input paramter 'bc' to all other + * functions that manipulate the hardware. + */ +extern void *gr1553bc_open(int minor); + +extern void gr1553bc_close(void *bc); + +/* Stores Current Major/Minor frame number and the Slot number executing + * into the location indicated by 'mid'. There may be two lists executing + * in "parallel", the 'async' argument select for which list the MID is + * looked up, the Syncronous (async=0) list or the Asynchronous (async=1) + * list. + * + */ +extern int gr1553bc_indication(void *bc, int async, int *mid); + +/* Trigger external time sync by writing to the BC action register. + * This may be good for debugging or if the time management is + * implemented in software. + * + * if trig=0 the external trigger memory is cleared. + * if trig!=0 the external trigger memory is set. + */ +extern void gr1553bc_ext_trig(void *bc, int trig); + +/* Configure the GR1553BC driver */ +/*extern int gr1553bc_config(struct gr1553bc_config *cfg);*/ + +/* Start major frame processing. At least one list pointer must be + * non-zero to affect BC operation. The BC communication is enabled + * depending on list and Interrupts are enabled. This function can + * be called multiple times. + * + * If a list is already executing it will be replaced with the new + * list. + * + * list - Schedule Transfer List + * list_async - Asynchronous list + */ +extern int gr1553bc_start + ( + void *bc, + struct gr1553bc_list *list, + struct gr1553bc_list *list_async + ); + +/* Pause GR1553B BC scheduled transfers. + * + * Does not affect asynchronous operation. + */ +extern int gr1553bc_pause(void *bc); + +/* Restart GR1553B BC scheduled transfers, after being paused + * + * Does not affect asynchronous operation. + */ +extern int gr1553bc_restart(void *bc); + +/* Stop BC transmission. + * + * OPTIONS + * bit0 - 1=STOP schedule list + * bit1 - 1=STOP asynchronous list + */ +extern int gr1553bc_stop(void *bc, int options); + +/* Standard IRQ function setup. IRQ can be generated by condition descriptors + * or by transfer descriptors or by errors. + * + * Condition descriptors are inserted into the list by user, each condition + * may have a custom function and data assigned to it, see + * gr1553bc_slot_irq_prepare(). IRQs generated by condition descriptors are + * not handled by this function. + * + * Transfer descriptors can generate IRQ if enabled by user. + * + * IRQs generated by transfer descriptors or by BC errors (DMA error etc.) + * is handled by this standard ISR handler. + */ +extern int gr1553bc_irq_setup + ( + void *bc, + bcirq_func_t func, + void *data + ); + +/* Get Current BC hardware state/status. The Status is stored into the + * area pointed to by status. See "struct gr1553bc_status" for more + * info. + */ +extern void gr1553bc_status(void *bc, struct gr1553bc_status *status); + +#ifdef __cplusplus +} +#endif + +#endif /* __GR1553BC_H__ */ diff --git a/bsps/sparc/include/bsp/gr1553bc_list.h b/bsps/sparc/include/bsp/gr1553bc_list.h new file mode 100644 index 0000000000..a89ddf58cf --- /dev/null +++ b/bsps/sparc/include/bsp/gr1553bc_list.h @@ -0,0 +1,707 @@ +/* + * GR1553B BC driver, Descriptor LIST handling + * + * COPYRIGHT (c) 2010. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GR1553BC_LIST_H__ +#define __GR1553BC_LIST_H__ + +/*!\file doc/gr1553bc_list.h + * \brief GR1553B BC driver + * + * \section OVERVIEW + * + * The BC device driver can schedule synchronous and asynchronous lists + * of descriptors. The list contains a descriptor table and a software + * description to make some operations possible, for example translate + * descriptor-address into descriptor-number. + * + * This is the LIST API. It provides functionality to create and manage + * a BC descriptor list. + * + * A list is built up by the following build blocks: + * - Major Frame (Consists of N Minor Frames) + * - Minor Frame (Consists of up to 32 1553 Message Slots) + * - Message Slot (Transfer/Condition BC descriptor) + * + * The user can configure lists with different configuration of number of + * Major Frames, Minor Frame and messages slots within a Minor Frame. The + * List manages a strait descriptor table (may be changed) and a Frame/Slot + * tree in order to easily find it's way through all descriptor created. + * + * Each Minor frame consist of up to 32 message slot and 2 message slots + * for time management and descriptor find operations. The list can manage + * time slots per minor frame, for example a minor frame may be programmed + * to take 8ms and when the user allocate a message slot within that Minor + * frame the time spcified will be subtracted from the 8ms, and when the + * message slot is freed the time will be returned to the Minor frame again. + * + * A Major, Minor and Message Slots are identified using a MID (Message-ID). + * The MID is a way for the user to avoid using pointers are talk with the + * list API in an easier way. For example a condition Slot that should jump + * to a transfer slot can be created by knowing "MID and Jump-To-MID". When + * allocating a Slot (with or without time) the user may specify a certain + * Slot or a Minor frame, when a Minor frame is given then the API will find + * a free Slot as early in the Minor Frame as possible and return it to the + * user. + * + * A MID can be created using the macros: + * GR1553BC_ID(major,minor,slot) - ID of a SLOT + * GR1553BC_MINOR_ID(major,minor) - ID of a MINOR (Slot=0xff) + * GR1553BC_MAJOR_ID(major) - ID of a Major (Minor=0xff,Slot=0xff) + * + * The typical approach create lists is in the following order: + * -# gr1553bc_list_alloc(&list, MAJOR_CNT) + * -# gr1553bc_list_config(list, &listcfg) + * -# Create all Major Frames and Minor frame, for each major frame: + * a) gr1553bc_major_alloc_skel(&major, &major_minor_cfg) + * b) gr1553bc_list_set_major(list, &major, MAJOR_NUM) + * -# link end Major Frames together: + * a) gr1553bc_list_set_major(&major7, &major0) // Connect Major frames + * -# gr1553bc_list_table_alloc() (Allocate Descriptor Table) + * -# gr1553bc_list_table_build() (Build Descriptor Table from Majors/Minors) + * -# Allocate and initialize Descriptors pre defined before starting: + * -## gr1553bc_slot_alloc(list, &MID, TIME_REQUIRED, ..) + * -## gr1553bc_slot_transfer(MID, ...) + * -# START BC HARDWARE BY SHCDULING ABOVE LIST + * -# Operate on List + * + * + * \section bc_list_update Changing a scheduled BC list (during BC-runtime) + * + * One can use the INDICATION service to avoid modifying + * a descriptor currently in use by the BC core. One can also in most cases + * do descriptor initialization in three steps: Init Descriptor as Dummy + * with and allocated time (often done before starting/scheduling list), + * then modify transfer options and data-pointers, then clear the Dummy + * bit in one atomic data store. This approach will avoid potential races + * between software has hardware. + * + * + * \section bc_memory_setup Custom Memory Setup + * + * For designs where dynamically memory is not an option, or the driver + * is used on a AMBA-over-PCI bus (where malloc() does not work), the + * API allows the user to provide custom addresses for descriptor table + * and object descriptions (lists, major frames, minor frames). Custom + * descriptor table is probably the most interesting thing for most, it + * is setup with gr1553bc_list_table_alloc(list, CUSTOM_ADDRESS). + * + * Object descriptions are normally allocated during initialization + * procedure by providing the API with a object configuration, for + * example a Major Frame configuration enables the API to allocate + * the software description of a Major Frame with all it's Minor frames. + * + * + * \section major Major Frame + * + * Consists of multiple Minor frames. A Major frame may be connected/linked + * with another Major frame, this will result in a Jump Slot from last + * Minor frame in the first Major to the first Minor in the second Major. + * + * + * \section minor Minor Frame + * + * Consists of up to 32 Message Slots. The services are Time-Management and + * Slot allocation. + * + * Time-Management is optional. + * + * Time-Slot-Management can be enabled per Minor frame. A Minor frame can be + * assigned a time in microseconds. The BC will not continue to the next + * Minor frame until the time has passed. It is managed by adding an extra + * Dummy Message Slot with the total minor frame time. Each time a message + * Slot is allocated (with a certain time: Slot-Time) the Slot-Time will + * be decremented from the total time of the Minor frame. This way the + * sum of the Message Slot will always sum up to the total time of the + * Minor configuration. When a message slot is freed, the Dymmy Message + * Slot's Slot-Time is incremented with the freed Slot-Time. + * + * A Message Slot can be allocated by identifying a specific free Slot + * by the MID (Message-ID) or by letting the API allocate the first free + * Slot in the Minor Frame (Set MID Slot-ID to 0xff to identify Minor + * Frame). + * + * + * \section slot Message Slot + * + * The GR1553B BC core supports two Slot (Descriptor) Types: + * - Transfer descriptor + * - Condition descriptor (Jump, unconditional-IRQ) + * + * See the hardware manual for a detail description of a descriptor (Slot). + * + * The BC Core is unaware of lists, it steps through executing each + * descriptor as the encountered, Conditionals resulting in jumps may + * let us to create more complex arrangements of buffer descriptos (BDs) + * which we call list. + * + * Transfer BDs (TBDs) may have a time slot assigned, the BC core will wait + * until the time has expired before executing the next descriptor. Time + * slots are handled by a Minor frame in the list. + * + * A Message Slot is allocated using the gr1553bc_slot_alloc() function, + * and configured by calling one of the below functions: + * - gr1553bc_slot_irq_prepare [unconditional IRQ slot] + * - gr1553bc_slot_jump [unconditional jump] + * - gr1553bc_slot_exttrig [Dummy transfer, wait for EXTERNAL-TRIGGER] + * - gr1553bc_slot_transfer [Transfer descriptor] + * - gr1553bc_slot_empty [Create Dummy Transfer descriptor] + * - gr1553bc_slot_raw [Custom Descriptor handling] + * + * - gr1553bc_slot_dummy [Set existing Transfer descriptor to Dummy] + * - gr1553bc_slot_update [Update DataPointer|Status of a TBD] + * + * + * \section bc_IRQ Interrupt Handling + * + * There are different types of interrupts, Error IRQs or transfer IRQs. The + * Error IRQs are handled by the driver can a callback function is called. + * + * Transfer Descriptors can be programmed to generate interrupt, and + * condition descriptors can be programmed to generate interrupt + * unconditionaly (there exists more conditional types). When a Transfer + * descriptor causes IRQ the general ISR callback of the BC driver is + * called to let the user handle the interrupt. When a condition descriptor + * causes an IRQ a custom IRQ handler is called (if assigned). + * + * Transfers descriptor IRQ is enabled by configuring the descriptor. + * + * The API provides functions for placing unconditional IRQ points anywhere + * in the list. The order: + * -# gr1553bc_slot_alloc(&MID, TIME=0, ..) + * -# gr1553bc_slot_irq_prepare(MID, funcISR, data) + * -# gr1553bc_slot_irq_enable(MID) + * + * \verbatim + * void funcISR(*bd, *data) + * { + * // HANDLE ONE OR MULTIPLE DESCRIPTORS (MULTIPLE IN THIS EXAMPLE): + * int MID; + * gr1553bc_mid_from_bd(bd,&MID,NULL); + * printf("IRQ ON %06x\n", MID); + * } + * \endverbatim + * + * \ingroup GR1553BC + */ + +#include +#include + +/**** CONFIGURATION OPTIONS ****/ + +/* Define GR1553BC_TIMESLOT to make driver take care of time + * management of minor frames. + */ +#define GR1553BC_TIMESLOT + +#define GR1553BC_MINOR_MAX 256 +#define GR1553BC_SLOT_MAX 32 + +#ifdef __cplusplus +extern "C" { +#endif + +struct gr1553bc_list; +struct gr1553bc_major; +struct gr1553bc_minor; +struct gr1553bc_minor_cfg; +struct gr1553bc_major_cfg; + +struct gr1553bc_minor_cfg { + int slot_cnt; + int timeslot; /* Total time of minor frame in us */ +}; + +struct gr1553bc_major_cfg { + int minor_cnt; /* Number of Minor Frames */ + struct gr1553bc_minor_cfg minor_cfgs[1]; +}; + +struct gr1553bc_list_cfg { + unsigned char rt_timeout[31]; /* Number of us timeout tolerance per RT */ + unsigned char bc_timeout; /* Number of us timeout tolerance of + * broadcast transfers */ + int tropt_irq_on_err; /* Generate IRQ on transfer error */ + int tropt_pause_on_err; /* Pause list on transfer error */ + int async_list; /* Set to non-zero if asyncronous list*/ +}; + +/* Default Configuration */ +extern struct gr1553bc_list_cfg gr1553bc_def_cfg; + +/* Complete list of all major frames */ +struct gr1553bc_list { + void *_table_custom; /* Config option given by user */ + void *_table; /* address of allocated bd-table */ + unsigned int table_hw; /* Descriptor table base HW-ADR */ + unsigned int table_cpu; /* Descriptor table base CPU-ADR */ + int table_size; /* Descriptor Table Size */ + void *bc; /* BC HW, needed for adr translation */ + unsigned char rt_timeout[32]; /* Tolerance per RT, default 20us + * Note: 31 is for Broadcast */ + uint32_t tropts; /* Transfer descriptor options: + * On transfer error the following bits + * do affect: + * - bit28 1=Generate IRQ + * - bit26 1=Pause transfer list + * + */ + int async_list; /* async list or not */ + int major_cnt; /* Number of Major frames */ + struct gr1553bc_major *majors[1]; /* Var-Array of Major Pointers*/ +}; + +/* Alloc a List with a maximum number of Major frames supported */ +extern int gr1553bc_list_alloc(struct gr1553bc_list **list, int max_major); + +/* Free List if allocated with gr1553bc_list_alloc() */ +extern void gr1553bc_list_free(struct gr1553bc_list *list); + +/* Configure Global List parameters + * + * \param list List to be configured and initialized. + * \param cfg List Configuration + * \param bc The BC hardware device description + * (only needed for address translation) + */ +extern int gr1553bc_list_config + ( + struct gr1553bc_list *list, + struct gr1553bc_list_cfg *cfg, + void *bc + ); + +/* Link a 'major' Major frame with next major frame + * The links affected: + * - major->next + * - major->minor[LAST]->next + */ +extern void gr1553bc_list_link_major( + struct gr1553bc_major *major, + struct gr1553bc_major *next + ); + +/* Link in a Major frame into a BC list. + * Calls gr1553bc_list_link_major() to link major frame with major-1 and + * major+1. If ending or starting major frame the frame is wrapped around. + */ +extern int gr1553bc_list_set_major( + struct gr1553bc_list *list, + struct gr1553bc_major *major, + int no); + +/* Calculate the size required in the descriptor table by one minor frame. */ +extern int gr1553bc_minor_table_size(struct gr1553bc_minor *minor); + +/* Calculate the size required for the descriptor table. + */ +extern int gr1553bc_list_table_size(struct gr1553bc_list *list); + +/* Allocate an empty descriptor table from list description suitable for + * the BC given by 'bc'. + * + * \param bdtab_custom Custom Descriptor Allocation options: + * ZERO: Dynamically allocated by Driver (CPU near RAM) + * Non-Zero: Use provided address as BASE of BD-TABLE + * Non-Zero with LSB set: Same as Non-Zero but address + * is given as HW address (used with AMBA-over-PCI to + * to specify RAM location on PCI board). + */ +extern int gr1553bc_list_table_alloc + ( + struct gr1553bc_list *list, + void *bdtab_custom + ); + +/* Free descriptor table allocated with gr1553bc_list_table_alloc() */ +extern void gr1553bc_list_table_free(struct gr1553bc_list *list); + +/* Build an empty descriptor table from list description, + * the minor frames will be linked together. + */ +extern int gr1553bc_list_table_build(struct gr1553bc_list *list); + +/* Major Frame */ +struct gr1553bc_major { + struct gr1553bc_major *next; /* Next Major Frame */ + struct gr1553bc_major_cfg *cfg; /* User Config of Major frame */ + struct gr1553bc_minor *minors[1]; /* Minor frames */ +}; + +/* Minor Frame */ +struct gr1553bc_minor { + struct gr1553bc_minor *next; /* Next Minor Frame */ + struct gr1553bc_minor_cfg *cfg; /* User Config of Minor frame */ + uint32_t alloc; /* Descripts allocated */ + + /* Note: THIS POINTER MUST BE ALIGNED ON A 128-bit BOUNDARY */ + union gr1553bc_bd *bds; /* Descriptors for this minor frame (CPU ADRS)*/ +}; + +/* Alloc a Major/Minor frame skeleton according to the configuration structure. + * The descriptor table is not allocated. + */ +extern int gr1553bc_major_alloc_skel + ( + struct gr1553bc_major **major, + struct gr1553bc_major_cfg *cfg + ); + +/* Unique Message/Descriptor ID. Can be used to identify a Major or Minor + * Frame, or a Slot. + * + * - If minor_num is 0xff, the ID identifies a Major Frame + * - If slot_num is 0xff, the ID identifies a Minor Frame + * - If non of the above is true, the ID identifies a specific Slot + */ +#define GR1553BC_ID(major_num, minor_num, slot_num) \ + ((((major_num)<<16)&0xff0000) | (((minor_num)<<8)&0xff00) | \ + ((slot_num) & 0xff)) +#define GR1553BC_MINOR_ID(major_num, minor_num) \ + GR1553BC_ID(major_num, minor_num, 0xff) +#define GR1553BC_MAJOR_ID(major_num) \ + GR1553BC_ID(major_num, 0xff, 0xff) + +#define GR1553BC_MAJID_FROM_ID(mid) (((mid) >> 16) & 0xff) +#define GR1553BC_MINID_FROM_ID(mid) (((mid) >> 8) & 0xff) +#define GR1553BC_SLOTID_FROM_ID(mid) ((mid) & 0xff) +#define GR1553BC_ID_SET_SLOT(mid, slot_num) (((mid) & ~0xff) | ((slot_num) & 0xff)) + +extern struct gr1553bc_major *gr1553bc_major_from_id + ( + struct gr1553bc_list *list, + int mid + ); + +extern struct gr1553bc_minor *gr1553bc_minor_from_id + ( + struct gr1553bc_list *list, + int mid + ); + +/* Get free time left of minor frame identified by MID 'mid' */ +extern int gr1553bc_list_freetime(struct gr1553bc_list *list, int mid); + +/* Get free time left of minor frame */ +extern int gr1553bc_minor_freetime(struct gr1553bc_minor *minor); + +/* Allocate a time slot on a minor frame, major/minor frame is identified + * by MID. The 'mid' is a input/ouput parameter, the resulting slot taken + * will be placed in 'mid', a pointer to the allocated descriptor is stored + * into bd. + * + * Major/Minor must be specified by MID, if slot is specified that slot will + * be allocated, if slot is 0xff, then the first free slot is allocated. + * + * The function fails (return negative) if timeslot is longer than remaining + * time in minor frame, if no more slots are available in minor frame, if + * MID points to a bad major/minor or major/minor/slot. + */ +extern int gr1553bc_slot_alloc( + struct gr1553bc_list *list, + int *mid, + int timeslot, + union gr1553bc_bd **bd + ); +/* Same as gr1553bc_slot_alloc but identifies a minor instead of list. + * The major/minor part of MID is ignored. + */ +extern int gr1553bc_slot_alloc2( + struct gr1553bc_minor *minor, + int *mid, + int timeslot, + union gr1553bc_bd **bd + ); + +/* Free message slot and the time associated with it. The time taken by the + * message slot is added to the END TIME descriptor, if managed by the driver + * for this minor frame. The descriptor will be + */ +extern int gr1553bc_slot_free(struct gr1553bc_list *list, int mid); +extern int gr1553bc_slot_free2(struct gr1553bc_minor *minor, int mid); + +/* Find MID from Descriptor pointer + * + * In the end of each minor frame is a unconditional jump + * to next minor frame descriptor. The hardware does not + * use the last 8 bytes of conditional descriptors, in the + * padding area a MID is stored so that we can lookup the + * MID of a descriptor. This function finds the jump + * descriptor and subtracs the offset from it. + * + * A faster way of looking up can be implemented if the + * list is symertical, however in the current setup we + * allow different numbers of slots in minor frames, and + * different number of minor frames in a major frame. + * + * \param bd IN: Descriptor to lookup MID of (CPU address of BD) + * \param mid OUT: Pointer to where Message-ID (Slot-ID) will be stored + * \param async OUT: Function will store non-zero value if BD belogs to + * async list. + */ +extern int gr1553bc_mid_from_bd( + union gr1553bc_bd *bd, + int *mid, + int *async + ); + +/********** TRANSFER DESCRIPTOR MANIPULATION **********/ + +/* Get pointer to descriptor entry from MID. */ +extern union gr1553bc_bd *gr1553bc_slot_bd + ( + struct gr1553bc_list *list, + int mid + ); + +/* IRQ function */ +typedef void (*bcirq_func_t)(union gr1553bc_bd *bd, void *data); + +/* Create unconditional IRQ customly defined location. + * The IRQ is disabled, enable it with gr1553bc_slot_irq_enable(). + */ +extern int gr1553bc_slot_irq_prepare + ( + struct gr1553bc_list *list, + int mid, + bcirq_func_t func, + void *data + ); + +/* Enable previously prepared unconditional IRQ */ +extern int gr1553bc_slot_irq_enable(struct gr1553bc_list *list, int mid); + +/* Disable unconditional IRQ point, changed to unconditional JUMP + * to descriptor following. + * After disabling it it can be enabled again, or freed. + */ +extern int gr1553bc_slot_irq_disable(struct gr1553bc_list *list, int mid); + +/* Create custom jump to descriptor, conditional or unconditional, see + * hardware manual for conditions. + * + * set conditional to GR1553BC_UNCOND_JMP for unconditional jump. + */ +extern int gr1553bc_slot_jump + ( + struct gr1553bc_list *list, + int mid, + uint32_t condition, + int to_mid + ); + +/* Create a dummy transfer, paused until external trigger is set. The + * Slot is will have the dummy bit set, no transfer will take place. + */ +extern int gr1553bc_slot_exttrig(struct gr1553bc_list *list, int mid); + +/* Create a transfer on a previous allocated descriptor. It is assumed + * that the descriptor has been initialized empty before calling this + * function, this is to avoid races. + * + * The settings that are controlled on a global level (and not + * by this function): + * - IRQ after transfer error + * - IRQ after transfer (not supported, insert separate IRQ slot after this) + * - Pause schedule after transfer error + * - Pause schedule after transfer (not supported) + * - slot time optional (set when MID allocated), otherwise 0 + * - (OPTIONAL) Dummy Bit, set using slot_empty() or ..._TT_DUMMY + * - RT timeout tolerance (managed per RT) + * + * Input Parameters: + * - Retry Mode (options) + * - Number of retires (options) + * - Bus selection (A or B) (options) + * - dummy bit (options) + * - transfer type (tt) + * - rt src/dst address (tt) + * - RT subaddress (tt) + * - word count (tt) + * - mode code (tt) + * - data pointer (dptr) + * + * + * See macros defined in this header file for creating transfer types (tt) + * and word count etc. + * + * See macros defined in this header file for creating the mask of options. + * + * Note that if bit0 (LSB) of dptr is set, then the address is translated into + * hardware address, otherwise the dptr is assumed to be accessible from the + * 1553 core. This is an option only for AMBA-over-PCI. + */ +extern int gr1553bc_slot_transfer( + struct gr1553bc_list *list, + int mid, + int options, + int tt, + uint16_t *dptr); + +/* Remove or set dummy bit of a transfer descriptor + * Bit31 of *dummy is written to the dummy bit, the + * old descriptor value is stored into *dummy. + */ +extern int gr1553bc_slot_dummy( + struct gr1553bc_list *list, + int mid, + unsigned int *dummy); + +/* Make a slot empty (BC will not generate bus transfers), time slot + * allocated is untouched (if assigned). + */ +extern int gr1553bc_slot_empty(struct gr1553bc_list *list, int mid); + +/* Transfer descriptor status and/or update Transfer descriptor data pointer. + * + * Read and/or write Status of a slot. Writing the status word may be + * used by software to indicate that result has been handled, or bit 31 + * may be written 1 telling software that when it reaches 0, then BC + * has executed the request. + * + * Operation: + * bd->status = *stat & (bd->status 0xffffff) | (*stat & 0x80000000); + * *stat = Value of bd->status before rewrite. + * + * Note that the status word is not written when *stat is zero. + * + * Note that if bit0 (LSB) of dptr is set, then the address is translated into + * hardware address, otherwise the dptr is assumed to be accessible from the + * 1553 core. This is an option only for AMBA-over-PCI. + */ +extern int gr1553bc_slot_update( + struct gr1553bc_list *list, + int mid, + uint16_t *dptr, + unsigned int *stat); + +/* Modify a transfer descriptor in any way, + * + * flags: + * bit[N=0..3]: 1 = set BD wordN according to argument wordN, + * 0 = do not modify BD wordN + */ +extern int gr1553bc_slot_raw + ( + struct gr1553bc_list *list, + int mid, + unsigned int flags, + uint32_t word0, + uint32_t word1, + uint32_t word2, + uint32_t word3 + ); + + +/***** Macros to create BC Transfer Types (tt) for gr1553bc_slot_transfer() *****/ + +/* WRITE TO RT (BC-to-RT) */ +#define GR1553BC_BC2RT(rtadr, subadr, word_count) \ + ((rtadr<<11) | (subadr<<5) | (0x1f<<21) | (0<<10) | \ + ((word_count>=32) ? 0 : word_count)) + +/* READ FROM RT (RT-to-BC) */ +#define GR1553BC_RT2BC(rtadr, subadr, word_count) \ + ((rtadr<<11) | (subadr<<5) | (0x1f<<21) | (1<<10) | \ + ((word_count>=32) ? 0 : word_count)) + +/* RT(TX) WRITE TO RT(RX) (RT-to-RT) */ +#define GR1553BC_RT2RT(tx_rtadr, tx_subadr, rx_rtadr, rx_subadr, word_count) \ + ((rx_rtadr<<11) | (rx_subadr<<5) | \ + (tx_rtadr<<21) | (tx_subadr<<16) | \ + (0<<10) | \ + ((word_count>=32) ? 0 : word_count)) + +/* Mode command without data. (BC-to-RT) + * Mode code: 0,1,2,3,4,5,6,7 or 8. + */ +#define GR1553BC_MC_NODATA(rtadr, modecode) \ + ((rtadr<<11) | (0x1f<<5) | (0x1f<<21) | \ + (modecode<<0) | (1<<10)) + +/* Mode command with 4 byte data (RT-to-BC) + * Mode code: 16, 18 or 19. + */ +#define GR1553BC_MC_RT2BC(rtadr, modecode) \ + ((rtadr<<11) | (0x1f<<5) | (0x1f<<21) | \ + (modecode<<0) | (1<<10)) + +/* Mode command with 4 byte data (BC-to-RT) + * Mode code: 17, 20 or 21. + */ +#define GR1553BC_MC_BC2RT(rtadr, modecode) \ + ((rtadr<<11) | (0x1f<<5) | (0x1f<<21) | \ + (modecode<<0) | (0<<10)) + +/* Broadcast to all RTs, to a specific subaddress (BC-to-RTs) */ +#define GR1553BC_BC_BC2RT(subadr, word_count) \ + ((0x1f<<11) | (subadr<<5) | (0x1f<<21) | \ + (0<<10) | \ + ((word_count>=32) ? 0 : word_count)) + +/* Request RT to broadcast to all RTs, to a specific subaddress (RT-to-RTs) */ +#define GR1553BC_BC_RT2RT(tx_rtadr, tx_subadr, rx_subadr, word_count) \ + ((0x1f<<11) | (rx_subadr<<5) | \ + (tx_rtadr<<21) | (tx_subadr<<16) | \ + (0<<10) | \ + ((word_count>=32) ? 0 : word_count)) + +/* Broadcast mode command without data (BC-to-RTs) + * Mode code: 1,3,4,5,6,7 or 8 + */ +#define GR1553BC_BC_MC_NODATA(modecode) \ + ((0x1f<<11) | (0x1f<<5) | (0x1f<<21) | \ + ((modecode)<<0) | (1<<10)) + +/* Broadcast mode command with 4 byte data (BC-to-RTs) + * Mode code: 17, 20 or 21 + */ +#define GR1553BC_BC_MC_BC2RT(modecode) \ + ((0x1f<<11) | (0x1f<<5) | (0x1f<<21) | \ + ((modecode)<<0) | (0<<10)) + + +/***** Macros to create BC options (options) for gr1553bc_slot_transfer() *****/ + +/* Dummy (BC does no bus trasactions) */ +#define GR1553BC_OPT_DUMMY (1<<1) + +/* Retry modes */ +#define GR1553BC_RETRY_SAME 0x0 /* Retry on the same bus only */ +#define GR1553BC_RETRY_ALTER 0x1 /* Retry alternating on both busses */ +#define GR1553BC_RETRY_ATTEMPT 0x2 /* Many attepts first on original + * bus then on other bus */ +/* Number of retires supported */ +#define GR1553BC_RETRY_CNT_MAX 6 + +/* Dummy bit: No transfer + * Bus bit: 0=A, 1=B + * Exttrig bit: Wait for external trigger (used for timesync) + * Exclusive bit: 1=Don't allow other messages in this time slot. + */ +#define GR1553BC_OPTIONS(dummy, exttrig, exclusive, retrymode, nretry, bus) \ + ((((exttrig) & 0x1) << 30) | (((exclusive) & 0x1) << 29) | \ + ((retrymode) << 23) | ((nretry) << 20) | \ + ((bus) & 1) | (((dummy) & 0x1) << 1)) + +#define GR1553BC_OPTIONS_BUSA GR1553BC_OPTIONS(0,0,0,GR1553BC_RETRY_SAME,0,0) +#define GR1553BC_OPTIONS_BUSB GR1553BC_OPTIONS(0,0,0,GR1553BC_RETRY_SAME,0,1) +#define GR1553BC_OPTIONS_BUSA_DUM GR1553BC_OPTIONS(1,0,0,GR1553BC_RETRY_SAME,0,0) +#define GR1553BC_OPTIONS_BUSB_DUM GR1553BC_OPTIONS(1,0,0,GR1553BC_RETRY_SAME,0,1) + +/* Show parts of a list - this is for debugging only */ +extern void gr1553bc_show_list(struct gr1553bc_list *list, int options); + +#ifdef __cplusplus +} +#endif + +#endif /* __GR1553BC_LIST_H__ */ diff --git a/bsps/sparc/include/bsp/gr1553bm.h b/bsps/sparc/include/bsp/gr1553bm.h new file mode 100644 index 0000000000..058bc59a45 --- /dev/null +++ b/bsps/sparc/include/bsp/gr1553bm.h @@ -0,0 +1,204 @@ +/* GR1553B BM driver + * + * COPYRIGHT (c) 2010. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GR1553BM_H__ +#define __GR1553BM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register GR1553B driver needed by BM driver */ +extern void gr1553bm_register(void); + +struct gr1553bm_entry { + uint32_t time; /* bit31=1, bit 30=0 */ + uint32_t data; /* bit31=0, bit 30=0 */ +}; + +#define GR1553BM_ERROPTS_MANL 0x02 +#define GR1553BM_ERROPTS_UDWL 0x04 +#define GR1553BM_ERROPTS_IMCL 0x08 +#define GR1553BM_ERROPTS_ALL 0x0e + +/* Function used to implement a custom copy routine. + * Returns number of bytes the desctionation address + * should be incremented with. + * + * \param dst Optional Destination address + * \param src Source DMA address + * \param nentires Number of entries to be processed. + * \param data Custom Data (set by config) + */ +typedef int (*bmcopy_func_t)( + unsigned int dst, + struct gr1553bm_entry *src, + int nentries, + void *data + ); + +/* IRQ function callback, called on BM DMA error */ +typedef void (*bmisr_func_t)(void *bm, void *data); + +/* BM driver configuration */ +struct gr1553bm_config { + + /*** Time options ***/ + + /* 8-bit time resolution, the BM will update the time according + * to this setting. 0 will make the time tag be of highest + * resolution (no division), 1 will make the BM increment the + * time tag once for two time ticks (div with 2), etc. + */ + uint8_t time_resolution; + + /* Enable Time Overflow IRQ handling. Setting this to 1 + * makes the driver to update the 64-bit time by it self, + * it will use time overflow IRQ to detect when the 64-bit + * time counter must be incremented. + * + * If set to zero, the driver expect the user to call + * gr1553bm_time() regularly, it must be called more often + * than the time overflows to avoid an incorrect time. + */ + int time_ovf_irq; + + + + /*** Filtering options ***/ + + /* Bus error log options + * + * bit0,4-31 = reserved, set to zero + * Bit1 = Enables logging of Invalid mode code errors + * Bit2 = Enables logging of Unexpected Data errors + * Bit3 = Enables logging of Manchester/parity errors + */ + unsigned int filt_error_options; + + /* RT Address filtering bit mask. Each bit enables (if set) + * logging of a certain RT sub address. Bit 31 enables logging + * of broadcast messages. + */ + unsigned int filt_rtadr; + + /* RT Subaddress filtering bit mask, bit definition: + * 31: Enables logging of mode commands on subadr 31 + * 1..30: BitN enables/disables logging of RT subadr N + * 0: Enables logging of mode commands on subadr 0 + */ + unsigned int filt_subadr; + + /* Mode code Filter, is written into "BM RT Mode code filter" + * register, please see hardware manual for bit declarations. + */ + unsigned int filt_mc; + + + + /*** Buffer options ***/ + + /* Size of buffer in bytes, must be aligned to 8-byte + * The size is limited to max 4Mb. + */ + unsigned int buffer_size; + + /* Custom buffer, must be aligned to 8-byte and be of buffer_size + * length. If NULL dynamic memory allocation is used. + */ + void *buffer_custom; + + /* Custom Copy function, may be used to implement a more + * effective way of copying the DMA buffer. For example + * the DMA log may need to be compressed before copied + * onto a storage, this function can be used to avoid an + * extra copy. + */ + bmcopy_func_t copy_func; + + /* Optional Custom Data passed on to copy_func() */ + void *copy_func_arg; + + + + /*** Interrupt options ***/ + + /* Custom DMA error function, note that this function is called + * from Interrupt Context. Set to NULL to disable this callback. + */ + bmisr_func_t dma_error_isr; + + /* Optional Custom Data passed on to dma_error_isr() */ + void *dma_error_arg; +}; + +/* Open BM device by instance number (minor) + * + * The return value is used as input parameter in all other function calls + * in the A + */ +extern void *gr1553bm_open(int minor); + +/* Close previously opened Bm device */ +extern void gr1553bm_close(void *bm); + +/* Configure the BM driver before starting */ +extern int gr1553bm_config(void *bm, struct gr1553bm_config *cfg); + +/* Start logging */ +extern int gr1553bm_start(void *bm); + +/* Get 64-bit 1553 Time. Low 24-bit time is acquired from BM hardware, + * the MSB is taken from a software counter internal to the driver. The + * counter is incremented every time the Time overflows by: + * - using "Time overflow" IRQ if enabled in user configuration + * - by checking IRQ flag (IRQ disabled), it is required that user + * calls this function before the next time overflow. + * + * The BM timer is limited to 24-bits, in order to handle overflows + * correctly and maintain a valid time an Interrupt handler is used + * or this function must be called when IRQ is not used. + * + * Update software time counters and return the current time. + */ +extern void gr1553bm_time(void *bm, uint64_t *time); + +/* Return zero when logging has not been started, non-zero when logging + * has been started + */ +extern int gr1553bm_started(void *bm); + +/* Check how many entries are currently stored in the BM Log DMA-area */ +extern int gr1553bm_available(void *bm, int *nentries); + +/* Stop logging */ +extern void gr1553bm_stop(void *bm); + +/* Read a maximum number of entries from LOG buffer. This function + * must be + * + * Arguments + * bm - Private pointer returned by gr1553bm_open() + * dst - Address where log data is written + * max - (IN/OUT) Maximum number of entires, when successfull + * the number of entries actually written is stored + * into the address of max. + * + * Result + * 0 = success + * -1 = fail. (may be due to BM logging not started) + */ +extern int gr1553bm_read(void *bm, struct gr1553bm_entry *dst, int *max); + +#ifdef __cplusplus +} +#endif + +#endif /* __GR1553BM_H__ */ diff --git a/bsps/sparc/include/bsp/gr1553rt.h b/bsps/sparc/include/bsp/gr1553rt.h new file mode 100644 index 0000000000..55237b5dfd --- /dev/null +++ b/bsps/sparc/include/bsp/gr1553rt.h @@ -0,0 +1,434 @@ +/* GR1553B RT driver + * + * COPYRIGHT (c) 2010. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GR1553RT_H__ +#define __GR1553RT_H__ + +/* CONFIG OPTION: Maximum number of LIST IDs supported. + * There are two lists per RT subaddress, one for RX one + * for TX. + */ +#define RTLISTID_MAX 64 + +/* CONFIG OPTION: Maximum number of Interrupt handlers per device supported + * max is 256 supported, and minimum is 1. + */ +#define RTISR_MAX 64 + +/* CONFIG OPTION: Maximum number of transfer (RX/TX) descriptors supported. + * + * Set this option to zero to allow flexible number of descriptors, + * requires dynamically allocation of driver structures. + */ +/*#define RTBD_MAX 4096*/ +#define RTBD_MAX 0 + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register GR1553B driver needed by RT driver */ +extern void gr1553rt_register(void); + +struct gr1553rt_list; + +/* Descriptor read/written by hardware. + * + * Must be aligned to 16 byte boundary + */ +struct gr1553rt_bd { + volatile unsigned int ctrl; /* 0x00 Control/Status word */ + volatile unsigned int dptr; /* 0x04 Data Pointer */ + volatile unsigned int next; /* 0x08 Next Descriptor in list */ + volatile unsigned int unused; /* 0x0C UNUSED BY HARDWARE */ +}; + +/* Sub address table entry, the hardware access */ +struct gr1553rt_sa { + volatile unsigned int ctrl; /* 0x00 SUBADDRESS CONTROL WORD */ + volatile unsigned int txptr; /* 0x04 TRANSMIT BD POINTER */ + volatile unsigned int rxptr; /* 0x08 RECEIVE BD POINTER */ + volatile unsigned int unused; /* 0x0C UNUSED BY HARDWARE */ +}; + +/* Configuration of a RT-SubAddress-List */ +struct gr1553rt_list_cfg { + unsigned int bd_cnt; /* Number of hw-descriptors in list */ +}; + +/* A TX or RX subaddress descriptor list */ +struct gr1553rt_list { + short listid; /* ID/NUMBER of List. -1 unassigned */ + short subadr; /* SubAddress. -1 when not scheduled */ + void *rt; /* Scheduled on Device */ + struct gr1553rt_list_cfg *cfg; /* List configuration */ + int bd_cnt; /* Number of Descriptors */ + + /* !!Must be last in data structure!! + * !!Array must at least be of length bd_cnt!! + */ + unsigned short bds[1]; /* Array of BDIDs, -1 unused/end */ +}; + +/* GR1553B-RT Driver configuration options used when calling gr1553rt_config(). + * + * Note that if not custom addresses are given the driver will dynamically + * allocate memory for buffers. + * Note that if custom addresses with the LSB set, the address will be + * interpreted as a address accessible by hardware, and translated + * into an address used by CPU. + */ +struct gr1553rt_cfg { + unsigned char rtaddress; /* RT Address 0..30 */ + + /*** MODE CODE CONFIG ***/ + unsigned int modecode; /* Mode codes enable/disable/IRQ/EV-Log. + * Each modecode has a 2-bit cfg field. + * See Mode Code Control Register in + * hardware manual. + */ + + /*** TIME CONFIG ***/ + unsigned short time_res; /* Time tag resolution in us */ + + /*** SUBADDRESS TABLE CONFIG ***/ + void *satab_buffer; /* Optional Custom buffer. Must be + * At least 16*32 bytes, and be aligned + * to 10-bit (1KB) boundary. Set to NULL + * to make driver allocate buffer. + */ + + /*** EVENT LOG CONFIG ***/ + void *evlog_buffer; /* Optional Custom buffer */ + int evlog_size; /* Length, must be a multiple of 2. + * If set to ZERO event log is disabled + */ + + /*** TRANSFER DESCRIPTOR CONFIG ***/ + int bd_count; /* Number of transfer descriptors shared + * by all RX/TX sub-addresses */ + void *bd_buffer; /* Optional Custom descriptor area. + * Must hold bd_count*32 bytes. + * If NULL, descriptors will be + * allocated dynamically. */ +}; + +/* GR1553B-RT status indication, copied from the RT registers and stored + * here. Used when calling the gr1553rt_status() function. + */ +struct gr1553rt_status { + unsigned int status; /* RT Status word */ + unsigned int bus_status; /* BUS Status */ + unsigned short synctime; /* Time Tag of last sync with data */ + unsigned short syncword; /* Data of last mode code synchronize + * with data. */ + unsigned short time_res; /* Time resolution (set by config) */ + unsigned short time; /* Current Time Tag */ +}; + +/* ISR callback definition for ERRORs detected in the GR1553B-RT interrupt + * handler. + * + * \param err Inidicate Error type. The IRQ flag register bit mask: + * Bit 9 - RT DMA ERROR + * Bit 10 - RT Table access error + * \param data Custom data assigned by user + */ +typedef void (*gr1553rt_irqerr_t)(int err, void *data); + +/* ISR callback definition for modecodes that are configured to generate + * an IRQ. The callback is called from within the GR1553B-RT interrupt + * handler. + * + * \param mcode Mode code that caused this IRQ + * \param entry The raw Eventlog Entry + * \param data Custom data assigned by user + */ +typedef void (*gr1553rt_irqmc_t)(int mcode, unsigned int entry, void *data); + +/* Transfer ISR callback definition. Called from GR1553B-RT interrupt handler + * when an interrupt has been generated and a event logged due to a 1553 + * transfer to this RT. + * + * \param list List (Subaddress/TransferType) that caused IRQ + * \param entry The raw Eventlog Entry + * \param bd_next Next Descriptor-entry index in the list (Subaddress/tr-type) + * This can be used to process all descriptors upto entry_next. + * \param data Custom data assigned by user + */ +typedef void (*gr1553rt_irq_t)( + struct gr1553rt_list *list, + unsigned int entry, + int bd_next, + void *data + ); + +/* Configure a list according to configuration. Assign the list + * to a device, however not to a RT sub address yet. The rt + * is stored within list. + * + * \param rt RT Device driver identification, stored within list. + * \param list The list to configure + * \param cfg Configuration for list. Pointer to configuration is + * stored within list for later use. + */ +extern int gr1553rt_list_init + ( + void *rt, + struct gr1553rt_list **plist, + struct gr1553rt_list_cfg *cfg + ); + +/* Assign an Error Interrupt handler. Before the handler is called the + * RT hardware is stopped/disabled. The handler is optional, if not assigned + * the ISR will still stop the RT upon error. + * + * Errors detected by the interrupt handler: + * - DMA error + * - Subaddress table access error + * + * \param func ISR called when an error causes an interrupt. + * \param data Custom data given as an argument when calling ISR + */ +extern int gr1553rt_irq_err + ( + void *rt, + gr1553rt_irqerr_t func, + void *data + ); + +/* Assign a ModeCode Interrupt handler callback. Called when a 1553 modecode + * transfer is logged and cause an IRQ. The modecode IRQ generation is + * configured from "struct gr1553rt_cfg" when calling gr1553rt_config(). + * + * \param func ISR called when a modecode causes an interrupt. + * \param data Custom data given as an argument when calling ISR + */ +extern int gr1553rt_irq_mc + ( + void *rt, + gr1553rt_irqmc_t func, + void *data + ); + +/* Assign transfer interrupt handler callback. Called when a RX or TX + * transfer is logged and cause an interrupt, the function is called + * from the GR1553B-RT driver's ISR, in interrupt context. + * + * The callback can be installed per subaddress and transfer type. + * Subaddress 0 and 31 are not valid (gr1553rt_irq_mc() for modecodes). + * + * \param subadr Select subaddress (1-30) + * \param tx 1=TX subaddress, 0=RX subaddress + * \param func ISR called when subaddress of spcified transfer type + * causes an interrupt. + * \param data Custom data given as an argument when calling ISR + */ +extern int gr1553rt_irq_sa + ( + void *rt, + int subadr, + int tx, + gr1553rt_irq_t func, + void *data + ); + +#define GR1553RT_BD_FLAGS_IRQEN (1<<30) +/* Initialize a descriptor entry in a list. This is typically done + * prior to scheduling the list. + * + * \param entry_no Entry number in list (descriptor index in list) + * \param flags Enable IRQ when descriptor is accessed by setting + * argument GR1553RT_BD_FLAGS_IRQEN. Enabling IRQ on a + * descriptor basis will override SA-table IRQ config. + * \param dptr Data Pointer to RX or TX operation. The LSB indicate + * if the address must be translated into Hardware address + * - this is useful when a buffer close to CPU is used + * as a data pointer and the RT core is located over PCI. + * \param next Next Entry in list. Set to 0xffff for end of list. Set + * 0xfffe for next entry in list, wrap around to entry + * zero if entry_no is last descriptor in list (circular). + */ +extern int gr1553rt_bd_init( + struct gr1553rt_list *list, + unsigned short entry_no, + unsigned int flags, + uint16_t *dptr, + unsigned short next + ); + +/* Manipulate/Read Control/Status and Data Pointer words of a buffer descriptor. + * If status is zero, the control/status word is accessed. If dptr is non-zero + * the data pointer word is accessed. + * + * \param list The list that the descriptor is located at + * + * \param entry_no The descriptor number accessed + * + * \param status IN/OUT. If zero no effect. If pointer is non-zero the + * value pointed to: + * IN: Written to Control/Status + * OUT: the value of the Control/Status word before writing. + * + * \param dptr IN/OUT. If zero no effect. If pointer is non-zero, the + * value pointed to: + * IN: non-zero: Descriptor data pointer will be updated with + * this value. Note that the LSB indicate if the address + * must be translated into hardware-aware address. + * OUT: The old data pointer is stored here. + */ +extern int gr1553rt_bd_update( + struct gr1553rt_list *list, + int entry_no, + unsigned int *status, + uint16_t **dptr + ); + +/* Get the next/current descriptor processed of a RT sub-address. + * + * \param subadr RT Subaddress + * \param txeno Pointer to where TX descriptor number is stored. + * \param rxeno Pointer to where RX descriptor number is stored. + */ +extern int gr1553rt_indication(void *rt, int subadr, int *txeno, int *rxeno); + +/* Take a GR1553RT hardware device identified by minor. + * A pointer is returned that is used internally by the GR1553RT + * driver, it is used as an input parameter 'rt' to all other + * functions that manipulate the hardware. + * + * This function initializes the RT hardware to a stopped/disable level. + */ +extern void *gr1553rt_open(int minor); + +/* Close and stop/disable the RT hardware. */ +extern void gr1553rt_close(void *rt); + +/* Configure the RT. The RT device must be configured once before + * started. A started RT device can not be configured. + * + * \param rt The RT to configure + * \param cfg Configuration parameters + */ +extern int gr1553rt_config(void *rt, struct gr1553rt_cfg *cfg); + +/* Schedule a RX or TX list on a sub address. If a list has already been + * schduled on the subaddress and on the same transfer type (RX/TX), the + * old list is replaced with the list given here. + * + * \param subadr Subaddress to schedule list on + * \param tx Subaddress transfer type: 1=TX, 0=RX + * \param list Preconfigued RT list scheduled + */ +extern void gr1553rt_sa_schedule( + void *rt, + int subadr, + int tx, + struct gr1553rt_list *list + ); + +/* Set SubAdress options. One may for example Enable or Disable a sub + * address RX and/or TX. See hardware manual for SA-Table configuration + * options. + * + * \param subadr SubAddress to configure + * \param mask Bit mask of option-bits written to subaddress config + * \param options The new options written to subaddress config. + * + */ +extern void gr1553rt_sa_setopts( + void *rt, + int subadr, + unsigned int mask, + unsigned int options + ); + +/* Get The Subaddress and transfer type of a scheduled list. Normally the + * application knows which subaddress the list is for. + * + * \param list List to lookup information for + * \param subadr Pointer to where the subaddress is stored + * \param tx Transfer type is stored here. 1=TX, 0=RX. + */ +extern void gr1553rt_list_sa( + struct gr1553rt_list *list, + int *subadr, + int *tx + ); + +/* Start RT Communication + * + * Interrupts will be enabled. The RT enabled and the "RT-run-time" + * part of the API will be opened for the user and parts that need the + * RT to be stopped are no longer available. After the RT has been + * started the configuration function can not be called. + */ +extern int gr1553rt_start(void *rt); + +/* Get Status of the RT core. See data structure gr1553rt_status for more + * information about the result. It can be used to read out: + * - time information + * - sync information + * - bus & RT status + * + * \param status Pointer to where the status words will be stored. They + * are stored according to the gr1553rt_status data structure. + */ +extern void gr1553rt_status(void *rt, struct gr1553rt_status *status); + +/* Stop RT communication. Only possible to stop an already started RT device. + * Interrupts are disabled and the RT Enable bit cleared. + */ +extern void gr1553rt_stop(void *rt); + +/* Set RT vector and/or bit word. + * + * - Vector Word is used in response to "Transmit vector word" BC commands + * - Bit Word is used in response to "Transmit bit word" BC commands + * + * + * \param mask Bit-Mask, bits that are 1 will result in that bit in the + * words register being overwritten with the value of words + * \param words Bits 31..16: Bit Word. Bits 15..0: Vector Word. + * + * Operation: + * hw_words = (hw_words & ~mask) | (words & mask) + */ +extern void gr1553rt_set_vecword( + void *rt, + unsigned int mask, + unsigned int words + ); + +/* Set selectable bits of the "Bus Status Register". The bits written + * is determined by the "mask" bit-mask. Operation: + * + * bus_status = (bus_status & ~mask) | (sts & mask) + * + */ +extern void gr1553rt_set_bussts(void *rt, unsigned int mask, unsigned int sts); + +/* Read up to MAX number of entries in eventlog log. + * + * \param dst Destination address for event log entries + * \param max Maximal number of event log entries that an be stored into dst + * + * Return + * negative Failure + * zero No entries available at the moment + * positive Number of entries copied into dst + */ +extern int gr1553rt_evlog_read(void *rt, unsigned int *dst, int max); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gr_701.h b/bsps/sparc/include/bsp/gr_701.h new file mode 100644 index 0000000000..acfd9237a2 --- /dev/null +++ b/bsps/sparc/include/bsp/gr_701.h @@ -0,0 +1,51 @@ +/* GR-701 PCI Target driver. + * + * COPYRIGHT (c) 2008. + * Cobham Gaisler AB. + * + * Configures the GR-701 interface PCI board. + * This driver provides a AMBA PnP bus by using the general part + * of the AMBA PnP bus driver (ambapp_bus.c). + * + * Driver resources for the AMBA PnP bus provided can be set using + * gr701_set_resources(). + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GR_701_H__ +#define __GR_701_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* An array of pointers to GR-701 resources. The resources will be + * used by the drivers controlling the cores on the GR-701 target AMBA bus. + * + * The gr701_resources is declared weak so that the user can override the + * default configuration. The array must be terminated with a NULL resource. + */ +extern struct drvmgr_bus_res *gr701_resources[]; + +#define GR701_OPTIONS_AMBA 0x01 +#define GR701_OPTIONS_IRQ 0x02 + +/* Print information about all GR-701 PCI boards */ +void gr701_print(int options); + +/* Print information about one GR-701 PCI board */ +void gr701_print_dev(struct drvmgr_dev *dev, int options); + +/* Register GR-701 driver */ +void gr701_register_drv(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gr_cpci_gr740.h b/bsps/sparc/include/bsp/gr_cpci_gr740.h new file mode 100644 index 0000000000..55c28acb4c --- /dev/null +++ b/bsps/sparc/include/bsp/gr_cpci_gr740.h @@ -0,0 +1,61 @@ +/* GR-CPCI-GR740 PCI Peripheral driver + * + * COPYRIGHT (c) 2017. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Configures the GR-CPIC-GR740 interface PCI board in peripheral + * mode. This driver provides a AMBA PnP bus by using the general part + * of the AMBA PnP bus driver (ambapp_bus.c). + * + * + * Driver resource options: + * NAME DEFAULT VALUE + * ahbmst2pci _RAM_START AMBA->PCI translation PCI base address + * ambaFreq 250000000 (250MHz) AMBA system frequency of GR740 + * cgEnMask 0x1f (all) Clock gating enable mask + * + * TODO/UNTESTED + * Interrupt testing + * bar0 RESOURCE 0x00000000 L2-Cache SDRAM memory + * bar1 RESOURCE 0xf0000000 L2-Cache registers + */ + +#ifndef __GR_CPCI_GR740_H__ +#define __GR_CPCI_GR740_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* An array of pointers to GR-CPCI-GR740 resources. The resources will be + * used by the drivers controlling the cores on the GR-CPCI-GR740 target + * AMBA bus. + * + * The gr_cpci_gr740_resources is declared weak so that the user can override the + * default configuration. The array must be terminated with a NULL resource. + */ +extern struct drvmgr_bus_res *gr_cpci_gr740_resources[]; + +/* Options to gr_cpci_gr740_print function */ +#define GR_CPCI_GR740_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ + +/* Print information about all GR-CPCI-GR740 PCI boards */ +void gr_cpci_gr740_print(int options); + +/* Print information about one GR-CPCI-GR740 PCI board */ +void gr_cpci_gr740_print_dev(struct drvmgr_dev *dev, int options); + +/* Register GR-CPCI-GR740 driver */ +void gr_cpci_gr740_register_drv(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gr_leon4_n2x.h b/bsps/sparc/include/bsp/gr_leon4_n2x.h new file mode 100644 index 0000000000..9a8041202a --- /dev/null +++ b/bsps/sparc/include/bsp/gr_leon4_n2x.h @@ -0,0 +1,61 @@ +/* GR-CPCI-LEON4-N2X (NGFP) PCI Peripheral driver + * + * COPYRIGHT (c) 2013. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Configures the GR-CPIC-LEON4-N2X interface PCI board in peripheral + * mode. This driver provides a AMBA PnP bus by using the general part + * of the AMBA PnP bus driver (ambapp_bus.c). + * + * + * Driver resource options: + * NAME DEFAULT VALUE + * ahbmst2pci _RAM_START AMBA->PCI translation PCI base address + * ambaFreq 200000000 (200MHz) AMBA system frequency of LEON4-N2X + * cgEnMask 0x1f (all) Clock gating enable mask + * + * TODO/UNTESTED + * Interrupt testing + * bar0 RESOURCE 0x00000000 L2-Cache SDRAM memory + * bar1 RESOURCE 0xf0000000 L2-Cache registers + */ + +#ifndef __GR_CPCI_LEON4_N2X_H__ +#define __GR_CPCI_LEON4_N2X_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* An array of pointers to GR-CPCI-LEON4-N2X resources. The resources will be + * used by the drivers controlling the cores on the GR-CPCI-LEON4-N2X target + * AMBA bus. + * + * The gr_leon4_n2x_resources is declared weak so that the user can override the + * default configuration. The array must be terminated with a NULL resource. + */ +extern struct drvmgr_bus_res *gr_leon4_n2x_resources[]; + +/* Options to gr_cpci_leon4_n2x_print function */ +#define GR_LEON4_N2X_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ + +/* Print information about all GR-CPCI-LEON4-N2X PCI boards */ +void gr_leon4_n2x_print(int options); + +/* Print information about one GR-CPCI-LEON4-N2X PCI board */ +void gr_cpci_leon4_n2x_print_dev(struct drvmgr_dev *dev, int options); + +/* Register GR-CPCI-LEON4-N2X driver */ +void gr_cpci_leon4_n2x_register_drv(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gr_rasta_adcdac.h b/bsps/sparc/include/bsp/gr_rasta_adcdac.h new file mode 100644 index 0000000000..9e16cab96b --- /dev/null +++ b/bsps/sparc/include/bsp/gr_rasta_adcdac.h @@ -0,0 +1,52 @@ +/* GR-RASTA-ADCDAC PCI Target driver. + * + * COPYRIGHT (c) 2008. + * Cobham Gaisler AB. + * + * Configures the GR-RASTA-ADCDAC interface PCI board. + * This driver provides a AMBA PnP bus by using the general part + * of the AMBA PnP bus driver (ambapp_bus.c). + * + * Driver resources for the AMBA PnP bus provided can be set using + * gr_rasta_adcdac_set_resources(). + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GR_RASTA_ADCDAC_H__ +#define __GR_RASTA_ADCDAC_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* An array of pointers to GR-RASTA-ADCDAC resources. The resources will be + * used by the drivers controlling the cores on the GR-RASTA-ADCDAC target AMBA bus. + * + * The gr_rasta_adcdac_resources is declared weak so that the user can override + * the default configuration. The array must be terminated with a NULL resource. + */ +extern struct drvmgr_bus_res *gr_rasta_adcdac_resources[]; + +/* Options to gr_rasta_io_print function */ +#define RASTA_ADCDAC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ +#define RASTA_ADCDAC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ + +/* Print information about all GR-RASTA-IO PCI boards */ +void gr_rasta_adcdac_print(int options); + +/* Print information about one GR-RASTA-IO PCI board */ +void gr_rasta_adcdac_print_dev(struct drvmgr_dev *dev, int options); + +/* Register GR-RASTA-IO driver */ +void gr_rasta_adcdac_register_drv(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gr_rasta_io.h b/bsps/sparc/include/bsp/gr_rasta_io.h new file mode 100644 index 0000000000..72a44f5151 --- /dev/null +++ b/bsps/sparc/include/bsp/gr_rasta_io.h @@ -0,0 +1,52 @@ +/* GR-RASTA-IO PCI Target driver. + * + * COPYRIGHT (c) 2008. + * Cobham Gaisler AB. + * + * Configures the GR-RASTA-IO interface PCI board. + * This driver provides a AMBA PnP bus by using the general part + * of the AMBA PnP bus driver (ambapp_bus.c). + * + * Driver resources for the AMBA PnP bus provided can be set using + * gr_rasta_io_set_resources(). + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GR_RASTA_IO_H__ +#define __GR_RASTA_IO_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* An array of pointers to GR-RASTA-IO resources. The resources will be + * used by the drivers controlling the cores on the GR-RASTA-IO target AMBA bus. + * + * The gr_rasta_io_resources is declared weak so that the user can override the + * default configuration. The array must be terminated with a NULL resource. + */ +extern struct drvmgr_bus_res *gr_rasta_io_resources[]; + +/* Options to gr_rasta_io_print function */ +#define RASTA_IO_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ +#define RASTA_IO_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ + +/* Print information about GR-RASTA-IO PCI boards */ +void gr_rasta_io_print(int options); + +/* Print information about a GR-RASTA-IO PCI board */ +void gr_rasta_io_print_dev(struct drvmgr_dev *dev, int options); + +/* Register GR-RASTA-IO driver */ +void gr_rasta_io_register_drv(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gr_rasta_spw_router.h b/bsps/sparc/include/bsp/gr_rasta_spw_router.h new file mode 100644 index 0000000000..1cc9e41979 --- /dev/null +++ b/bsps/sparc/include/bsp/gr_rasta_spw_router.h @@ -0,0 +1,48 @@ +/* GR-RASTA-SPW-ROUTER PCI Peripheral driver + * + * COPYRIGHT (c) 2015. + * Cobham Gaisler. + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef __GR_RASTA_SPW_ROUTER_H__ +#define __GR_RASTA_SPW_ROUTER_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* An array of pointers to GR-RASTA-SPW-ROUTER resources. The resources will be + * used by the drivers controlling the cores on the GR-RASTA-SPW-ROUTER target + * AMBA bus. + * + * The gr_rasta_spw_router_resources is declared weak so that the user can + * override the default configuration. The array must be terminated with a + * NULL resource. + */ +extern struct drvmgr_bus_res *gr_rasta_spw_router_resources[]; + +/* Options to gr_rasta_spw_router_print function */ +#define RASTA_SPW_ROUTER_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ +#define RASTA_SPW_ROUTER_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ + +/* Print information about all GR-CPCI-LEON4-N2X PCI boards */ +void gr_rasta_spw_router_print(int options); + +/* Print information about one GR-CPCI-LEON4-N2X PCI board */ +void gr_rasta_spw_router_print_dev(struct drvmgr_dev *dev, int options); + +/* Register GR-RASTA-SPW-ROUTER driver to Driver Manager */ +void gr_rasta_spw_router_register_drv(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gr_rasta_tmtc.h b/bsps/sparc/include/bsp/gr_rasta_tmtc.h new file mode 100644 index 0000000000..2b10ce2df3 --- /dev/null +++ b/bsps/sparc/include/bsp/gr_rasta_tmtc.h @@ -0,0 +1,103 @@ +/* GR-RASTA-TMTC PCI Target driver. + * + * COPYRIGHT (c) 2008. + * Cobham Gaisler AB. + * + * Configures the GR-RASTA-TMTC interface PCI board. + * This driver provides a AMBA PnP bus by using the general part + * of the AMBA PnP bus driver (ambapp_bus.c). + * + * Driver resources for the AMBA PnP bus provided can be set using + * gr_rasta_tmtc_set_resources(). + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GR_RASTA_TMTC_H__ +#define __GR_RASTA_TMTC_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* GPIO TM/TC configuration pin definitions + * --31 PWRX (1=PW2APB, 0=TM VC3/4) + * --30 PWTC (1=APB2PW, 0=TC MAP1/2) + * --29 Redundant TM (1=enable, 0=disable) + * --28 Redundant TC (1=enable, 0=disable) + * --27 Select TM output (1=GRTM, 0=PTME) + * --26 Loop back PW (1=enable, 0=disable) + * --25 Transponder clock (1=PLL, 0=PLL bypass) + * --24 PWTX-SELECT (0=TX0-0, 1=TX0-1) + * --23 PDEC Map Switch (1=on, 0=off) + * --22 PDEC Ext CPDU (1=on, 0=off) + * --21 PDEC Super User (1=on, 0=off) + * --20 PDEC RM On (1=on, 0=off) + * --19 PDEC AU Enable (1=on, 0=off) + * --18 PDEC Dynamic Mode (1=on, 0=off) + * --17 PDEC Priority (1=on, 0=off) + * --16 TC PSS Support (1=on, 0=off) + * --15 TC Mark (1=on, 0=off) + * --14 TC Pseudo (1=on, 0=off) + * --13 TC Rising Clock (1=rise, 0=fall) + * --12 TC Active High (1=high, 0=low) + * --11 Bit Lock Positive (1=high, 0=low) + * --10 RF Avail Positive (1=high, 0=low) + * -- 9 : 0 SpaceCraft ID + */ + +#define GR_TMTC_GPIO_PWRX (1<<31) +#define GR_TMTC_GPIO_PWTC (1<<30) +#define GR_TMTC_GPIO_RED_TM (1<<29) +#define GR_TMTC_GPIO_RED_TC (1<<28) +#define GR_TMTC_GPIO_GRTM_SEL (1<<27) +#define GR_TMTC_GPIO_LB_PW (1<<26) +#define GR_TMTC_GPIO_TRANSP_CLK (1<<25) +#define GR_TMTC_GPIO_PWTX_SEL (1<<24) +#define GR_TMTC_GPIO_PDEC_MAP (1<<23) +#define GR_TMTC_GPIO_PDEC_CPDU (1<<22) +#define GR_TMTC_GPIO_PDEC_SU (1<<21) +#define GR_TMTC_GPIO_PDEC_RM (1<<20) +#define GR_TMTC_GPIO_PDEC_AU (1<<19) +#define GR_TMTC_GPIO_PDEC_DYN_MODE (1<<18) +#define GR_TMTC_GPIO_PDEC_PRIO (1<<17) +#define GR_TMTC_GPIO_TC_PSS (1<<16) +#define GR_TMTC_GPIO_TC_MARK (1<<15) +#define GR_TMTC_GPIO_TC_PSEUDO (1<<14) +#define GR_TMTC_GPIO_TC_RISING_CLK (1<<13) +#define GR_TMTC_GPIO_TC_ACTIVE_HIGH (1<<12) +#define GR_TMTC_GPIO_TC_BIT_LOCK (1<<11) +#define GR_TMTC_GPIO_TC_RF_AVAIL (1<<10) +#define GR_TMTC_GPIO_SCID (0x000003ff) + +/* An array of pointers to GR-RASTA-TMTC bus resources. The resources will be + * used by the device drivers controlling the cores on the GR-RASTA-IO target + * AMBA bus. + * + * The array is defined weak, and defaults to no resources. The array must be + * terminated with a NULL resource. + */ +extern struct drvmgr_bus_res *gr_rasta_tmtc_resources[]; + +/* Options to gr_rasta_io_print function */ +#define RASTA_TMTC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ +#define RASTA_TMTC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ + +/* Print information about GR-RASTA-TMTC PCI boards */ +void gr_rasta_tmtc_print(int options); + +/* Print information about a GR-RASTA-TMTC PCI boards */ +void gr_rasta_tmtc_print_dev(struct drvmgr_dev *dev, int options); + +/* Register GR-RASTA-TMTC driver */ +void gr_rasta_tmtc_register_drv(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gr_tmtc_1553.h b/bsps/sparc/include/bsp/gr_tmtc_1553.h new file mode 100644 index 0000000000..b6ac43da00 --- /dev/null +++ b/bsps/sparc/include/bsp/gr_tmtc_1553.h @@ -0,0 +1,55 @@ +/* GR-TMTC-1553 PCI Target driver. + * + * COPYRIGHT (c) 2010. + * Cobham Gaisler AB. + * + * Configures the GR-TMTC-1553 interface PCI board. + * This driver provides a AMBA PnP bus by using the general part + * of the AMBA PnP bus driver (ambapp_bus.c). + * + * Driver resources for the AMBA PnP bus provided can be set using + * gr_tmtc_1553_set_resources(). + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GR_TMTC_1553_H__ +#define __GR_TMTC_1553_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* An array of pointers to GR-TMTC-1553 resources. The resources will be + * used by the drivers controlling the cores on the GR-TMTC-1553 target AMBA bus. + * + * The gr_rasta_io_resources is declared weak so that the user can override the + * default configuration. The array must be terminated with a NULL resource. + */ +extern struct drvmgr_bus_res *gr_tmtc_1553_resources[]; + +/* Options to gr_rasta_io_print function */ +#define TMTC_1553_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ +#define TMTC_1553_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ + +/* Print information about GR-RASTA-IO PCI board */ +void gr_tmtc_1553_print(int options); + +/* Register GR-RASTA-IO driver */ +void gr_tmtc_1553_register_drv(void); + +/* Print information about all GR-TMTC-1553 devices registered to this driver */ +void gr_tmtc_1553_print(int options); + +/* Print information about one GR-TMTC-1553 device */ +void gr_tmtc_1553_print_dev(struct drvmgr_dev *dev, int options); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/gradcdac.h b/bsps/sparc/include/bsp/gradcdac.h new file mode 100644 index 0000000000..b52077845f --- /dev/null +++ b/bsps/sparc/include/bsp/gradcdac.h @@ -0,0 +1,227 @@ +/* ADC / DAC (GRADCDAC) interface +/* + * COPYRIGHT (c) 2009. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRADCDAC_H__ +#define __GRADCDAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +struct gradcdac_regs { + volatile unsigned int config; /* 0x00 Configuration Register */ + volatile unsigned int status; /* 0x04 Status Register */ + int unused0[2]; + volatile unsigned int adc_din; /* 0x10 ADC Data Input Register */ + volatile unsigned int dac_dout; /* 0x14 DAC Data Output Register */ + int unused1[2]; + volatile unsigned int adrin; /* 0x20 Address Input Register */ + volatile unsigned int adrout; /* 0x24 Address Output Register */ + volatile unsigned int adrdir; /* 0x28 Address Direction Register */ + int unused2[1]; + volatile unsigned int data_in; /* 0x30 Data Input Register */ + volatile unsigned int data_out; /* 0x34 Data Output Register */ + volatile unsigned int data_dir; /* 0x38 Data Direction Register */ +}; + +#define GRADCDAC_CFG_DACWS 0x00f80000 +#define GRADCDAC_CFG_WRPOL 0x00040000 +#define GRADCDAC_CFG_DACDW 0x00030000 +#define GRADCDAC_CFG_ADCWS 0x0000f800 +#define GRADCDAC_CFG_RCPOL 0x00000400 +#define GRADCDAC_CFG_CSMODE 0x00000300 +#define GRADCDAC_CFG_CSPOL 0x00000080 +#define GRADCDAC_CFG_RDYMODE 0x00000040 +#define GRADCDAC_CFG_RDYPOL 0x00000020 +#define GRADCDAC_CFG_TRIGPOL 0x00000010 +#define GRADCDAC_CFG_TRIGMODE 0x0000000c +#define GRADCDAC_CFG_ADCDW 0x00000003 + +#define GRADCDAC_CFG_DACWS_BIT 19 +#define GRADCDAC_CFG_WRPOL_BIT 18 +#define GRADCDAC_CFG_DACDW_BIT 16 +#define GRADCDAC_CFG_ADCWS_BIT 11 +#define GRADCDAC_CFG_RCPOL_BIT 10 +#define GRADCDAC_CFG_CSMODE_BIT 8 +#define GRADCDAC_CFG_CSPOL_BIT 7 +#define GRADCDAC_CFG_RDYMODE_BIT 6 +#define GRADCDAC_CFG_RDYPOL_BIT 5 +#define GRADCDAC_CFG_TRIGPOL_BIT 4 +#define GRADCDAC_CFG_TRIGMODE_BIT 2 +#define GRADCDAC_CFG_ADCDW_BIT 0 + +#define GRADCDAC_STATUS_DACNO 0x40 +#define GRADCDAC_STATUS_DACRDY 0x20 +#define GRADCDAC_STATUS_DACON 0x10 +#define GRADCDAC_STATUS_ADCTO 0x08 +#define GRADCDAC_STATUS_ADCNO 0x04 +#define GRADCDAC_STATUS_ADCRDY 0x02 +#define GRADCDAC_STATUS_ADCON 0x01 + +#define GRADCDAC_STATUS_DACNO_BIT 6 +#define GRADCDAC_STATUS_DACRDY_BIT 5 +#define GRADCDAC_STATUS_DACON_BIT 4 +#define GRADCDAC_STATUS_ADCTO_BIT 3 +#define GRADCDAC_STATUS_ADCNO_BIT 2 +#define GRADCDAC_STATUS_ADCRDY_BIT 1 +#define GRADCDAC_STATUS_ADCON_BIT 0 + +#define GRADCDAC_IRQ_DAC 1 +#define GRADCDAC_IRQ_ADC 0 + +struct gradcdac_config { + unsigned char dac_ws; + char wr_pol; + unsigned char dac_dw; + unsigned char adc_ws; + char rc_pol; + unsigned char cs_mode; + char cs_pol; + char ready_mode; + char ready_pol; + char trigg_pol; + unsigned char trigg_mode; + unsigned char adc_dw; +}; + +extern void *gradcdac_open(char *devname); + +extern void gradcdac_set_config(void *cookie, struct gradcdac_config *cfg); + +extern void gradcdac_get_config(void *cookie, struct gradcdac_config *cfg); + +extern void gradcdac_set_cfg(void *cookie, unsigned int config); + +extern unsigned int gradcdac_get_cfg(void *cookie); + +extern unsigned int gradcdac_get_status(void *cookie); + +static int __inline__ gradcdac_DAC_ReqRej(unsigned int status) +{ + return (status & GRADCDAC_STATUS_DACNO); +} + +static int __inline__ gradcdac_DAC_isCompleted(unsigned int status) +{ + return (status & GRADCDAC_STATUS_DACRDY); +} + +static int __inline__ gradcdac_DAC_isOngoing(unsigned int status) +{ + return (status & GRADCDAC_STATUS_DACON); +} + +static int __inline__ gradcdac_ADC_isTimeouted(unsigned int status) +{ + return (status & GRADCDAC_STATUS_ADCTO); +} + +static int __inline__ gradcdac_ADC_ReqRej(unsigned int status) +{ + return (status & GRADCDAC_STATUS_ADCNO); +} + +static int __inline__ gradcdac_ADC_isCompleted(unsigned int status) +{ + return (status & GRADCDAC_STATUS_ADCRDY); +} + +static int __inline__ gradcdac_ADC_isOngoing(unsigned int status) +{ + return (status & GRADCDAC_STATUS_ADCON); +} + +#define GRADCDAC_ISR_BOTH 3 +#define GRADCDAC_ISR_DAC 2 +#define GRADCDAC_ISR_ADC 1 + +/* Install IRQ handler for ADC and/or DAC interrupt. + * The installed IRQ handler(ISR) must read the status + * register to clear the pending interrupt avoiding multiple + * entries to the ISR caused by the same IRQ. + * + * \param adc 1=ADC interrupt, 2=ADC interrupt, 3=ADC and DAC interrupt + * \param isr Interrupt service routine called when IRQ is fired + * \param arg custom argument passed to ISR when called. + */ +extern int gradcdac_install_irq_handler + (void *cookie, int adc, void (*isr)(void *cookie, void *arg), void *arg); + +extern void gradcdac_uninstall_irq_handler(void *cookie, int adc); + +/* Make the ADC circuitry initialize a analogue to digital + * conversion. The result can be read out by gradcdac_adc_convert_try + * or gradcdac_adc_convert. + */ +extern void gradcdac_adc_convert_start(void *cookie); + +/* Tries to read the conversion result. If the circuitry is busy + * converting the function return a non-zero value, if the conversion + * has successfully finished the function return zero. + * + * \param digital_value the resulting converted value is placed here + * \return zero = ADC conversion complete, digital_value contain current conversion result + * positive = ADC busy, digital_value contain previous conversion result + * negative = Conversion request failed. + */ +extern int gradcdac_adc_convert_try(void *cookie, unsigned short *digital_value); + +/* Waits until the ADC circuity has finished a digital to analogue + * conversion. The Waiting is implemented as a busy loop utilizing + * 100% CPU load. + * + * \return zero = Conversion ok + * negative = Conversion request failed. + */ +extern int gradcdac_adc_convert(void *cookie, unsigned short *digital_value); + +/* Try to make the DAC circuitry initialize a digital to analogue + * conversion. If the circuitry is busy by a previous conversion + * the function return a non-zero value, if the conversion is + * successfully initialized the function return zero. + */ +extern int gradcdac_dac_convert_try(void *cookie, unsigned short digital_value); + +/* Initializes a digital to analogue conversion by waiting until + * previous conversions is finished before procceding with the + * conversion. The Waiting is implemented as a busy loop utilizing + * 100% CPU load. + */ +extern void gradcdac_dac_convert(void *cookie, unsigned short digital_value); + +extern unsigned int gradcdac_get_adrinput(void *cookie); +extern void gradcdac_set_adrinput(void *cookie, unsigned int input); + +extern unsigned int gradcdac_get_adroutput(void *cookie); +extern void gradcdac_set_adroutput(void *cookie, unsigned int output); + +extern unsigned int gradcdac_get_adrdir(void *cookie); +extern void gradcdac_set_adrdir(void *cookie, unsigned int dir); + +extern unsigned int gradcdac_get_datainput(void *cookie); +extern void gradcdac_set_datainput(void *cookie, unsigned int input); + +extern unsigned int gradcdac_get_dataoutput(void *cookie); +extern void gradcdac_set_dataoutput(void *cookie, unsigned int output); + +extern unsigned int gradcdac_get_datadir(void *cookie); +extern void gradcdac_set_datadir(void *cookie, unsigned int dir); + +/* Show one or all GRADCDAC cores. If cookie is NULL all GRADCDAC's are shown */ +extern void grAdcDacShow(void *cookie); + +/* Register Driver routine */ +extern void gradcdac_register_drv (void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/grascs.h b/bsps/sparc/include/bsp/grascs.h new file mode 100644 index 0000000000..b393e77888 --- /dev/null +++ b/bsps/sparc/include/bsp/grascs.h @@ -0,0 +1,92 @@ +/* + * Header file for GRASCS RTEMS driver + * + * COPYRIGHT (c) 2008. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRASCS_H__ +#define __GRASCS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Minimum and maximum system frequency */ +#define GRASCS_MIN_SFREQ 10000 +#define GRASCS_MAX_SFREQ 255000 + +/* Default, minimum and maximum ETR pulse frequency */ +#define GRASCS_DEFAULT_ETRFREQ 10 +#define GRASCS_MIN_ETRFREQ 1 +#define GRASCS_MAX_ETRFREQ 100 + +/* Maximum number of external time markers */ +#define GRASCS_MAX_TMS 6 + +/* Error codes */ +#define GRASCS_ERROR_STARTSTOP 1 /* Serial/synch interface is running/stopped */ +#define GRASCS_ERROR_TRANSACTIVE 2 /* Busy with transaction */ +#define GRASCS_ERROR_CAPFAULT 3 /* Core capabilities prohibit request */ + +/* Command register */ +#define GRASCS_CMD_RESET (1 << 0) +#define GRASCS_CMD_STARTSTOP (1 << 1) +#define GRASCS_CMD_ESTARTSTOP (1 << 2) +#define GRASCS_CMD_SENDTM (1 << 3) +#define GRASCS_CMD_ETRCTRL (7 << 4) +#define GRASCS_CMD_ETRCTRL_BITS 4 +#define GRASCS_CMD_SLAVESEL (15 << 8) +#define GRASCS_CMD_SLAVESEL_BITS 8 +#define GRASCS_CMD_TCDONE (1 << 12) +#define GRASCS_CMD_TMDONE (1 << 13) +#define GRASCS_CMD_US1 (255 << 16) +#define GRASCS_CMD_US1_BITS 16 +#define GRASCS_CMD_US1C (1 << 24) + +/* Clock scale register */ +#define GRASCS_CLK_ETRFREQ_BITS 12 + +/* Status register */ +#define GRASCS_STS_RUNNING (1 << 0) +#define GRASCS_STS_ERUNNING (1 << 1) +#define GRASCS_STS_TCDONE (1 << 4) +#define GRASCS_STS_TMDONE (1 << 5) +#define GRASCS_STS_DBITS_BITS 8 +#define GRASCS_STS_NSLAVES_BITS 13 +#define GRASCS_STS_USCONF_BITS 18 +#define GRASCS_STS_TMCONF_BITS 19 + +extern int ASCS_init(void); + +extern int ASCS_input_select(int slave); + +extern int ASCS_etr_select(int etr, int freq); + +extern void ASCS_start(void); + +extern void ASCS_stop(void); + +extern int ASCS_iface_status(void); + +extern int ASCS_TC_send(int *word); + +extern int ASCS_TC_send_block(int *block, int ntrans); + +extern void ASCS_TC_sync_start(void); + +extern void ASCS_TC_sync_stop(void); + +extern int ASCS_TM_recv(int *word); + +extern int ASCS_TM_recv_block(int *block, int ntrans); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/grcan.h b/bsps/sparc/include/bsp/grcan.h new file mode 100644 index 0000000000..5cdbad4b01 --- /dev/null +++ b/bsps/sparc/include/bsp/grcan.h @@ -0,0 +1,342 @@ +/** + * @file + * @ingroup sparc_bsp + * @defgroup can GRCAN + * @ingroup can + * @brief Macros used for grcan controller + */ + +/* + * COPYRIGHT (c) 2007. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRCAN_H__ +#define __GRCAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +struct grcan_regs { + volatile unsigned int conf; /* 0x00 */ + volatile unsigned int stat; /* 0x04 */ + volatile unsigned int ctrl; /* 0x08 */ + volatile unsigned int dummy0[3]; /* 0x0C-0x014 */ + volatile unsigned int smask; /* 0x18 */ + volatile unsigned int scode; /* 0x1C */ + + volatile unsigned int dummy1[56]; /* 0x20-0xFC */ + + volatile unsigned int pimsr; /* 0x100 */ + volatile unsigned int pimr; /* 0x104 */ + volatile unsigned int pisr; /* 0x108 */ + volatile unsigned int pir; /* 0x10C */ + volatile unsigned int imr; /* 0x110 */ + volatile unsigned int picr; /* 0x114 */ + + volatile unsigned int dummy2[58]; /* 0x118-0x1FC */ + + volatile unsigned int tx0ctrl; /* 0x200 */ + volatile unsigned int tx0addr; /* 0x204 */ + volatile unsigned int tx0size; /* 0x208 */ + volatile unsigned int tx0wr; /* 0x20C */ + volatile unsigned int tx0rd; /* 0x210 */ + volatile unsigned int tx0irq; /* 0x214 */ + + volatile unsigned int dummy3[58]; /* 0x218-0x2FC */ + + volatile unsigned int rx0ctrl; /* 0x300 */ + volatile unsigned int rx0addr; /* 0x304 */ + volatile unsigned int rx0size; /* 0x308 */ + volatile unsigned int rx0wr; /* 0x30C */ + volatile unsigned int rx0rd; /* 0x310 */ + volatile unsigned int rx0irq; /* 0x314 */ + volatile unsigned int rx0mask; /* 0x318 */ + volatile unsigned int rx0code; /* 0x31C */ +}; + +struct grcan_stats { + unsigned int passive_cnt; + unsigned int overrun_cnt; + unsigned int rxsync_cnt; + unsigned int txsync_cnt; + unsigned int txloss_cnt; + unsigned int ahberr_cnt; + unsigned int ints; + unsigned int busoff_cnt; +}; + +struct grcan_timing { + unsigned char scaler; + unsigned char ps1; + unsigned char ps2; + unsigned int rsj; + unsigned char bpr; +}; + +struct grcan_selection { + int selection; + int enable0; + int enable1; +}; + +struct grcan_filter { + unsigned long long mask; + unsigned long long code; +}; + +/* CAN MESSAGE */ +typedef struct { + char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */ + char rtr; /* RTR - Remote Transmission Request */ + char unused; /* unused */ + unsigned char len; + unsigned char data[8]; + unsigned int id; +} CANMsg; + +enum { + GRCAN_RET_OK = 0, + GRCAN_RET_INVARG = -1, + GRCAN_RET_NOTSTARTED = -2, + GRCAN_RET_TIMEOUT = -3, + /* Bus-off condition detected (request aborted by driver) */ + GRCAN_RET_BUSOFF = -4, + /* AHB error condition detected (request aborted by driver) */ + GRCAN_RET_AHBERR = -5, +}; + +/* + * User functions can cause these transitions: + * STATE_STOPPED -> STATE_STARTED + * STATE_STARTED -> STATE_STOPPED + * STATE_BUSOFF -> STATE_STOPPED + * STATE_AHBERR -> STATE_STOPPED + * + * ISR can cause these transition + * STATE_STARTED -> STATE_BUSOFF + * STATE_STARTED -> STATE_AHBERR + * + * STATE_BUSOFF is entered from ISR on bus-off condition. STATE_AHBERR is + * entered from ISR on AHB DMA errors on RX/TX operations. At transition the ISR + * disables DMA, masks all interrupts and releases semaphores. + */ +enum grcan_state { + STATE_STOPPED = 0, + STATE_STARTED = 1, + STATE_BUSOFF = 2, + STATE_AHBERR = 3, +}; + +#define GRCAN_CFG_ABORT 0x00000001 +#define GRCAN_CFG_ENABLE0 0x00000002 +#define GRCAN_CFG_ENABLE1 0x00000004 +#define GRCAN_CFG_SELECTION 0x00000008 +#define GRCAN_CFG_SILENT 0x00000010 +#define GRCAN_CFG_BPR 0x00000300 +#define GRCAN_CFG_RSJ 0x00007000 +#define GRCAN_CFG_PS1 0x00f00000 +#define GRCAN_CFG_PS2 0x000f0000 +#define GRCAN_CFG_SCALER 0xff000000 + +#define GRCAN_CFG_BPR_BIT 8 +#define GRCAN_CFG_RSJ_BIT 12 +#define GRCAN_CFG_PS1_BIT 20 +#define GRCAN_CFG_PS2_BIT 16 +#define GRCAN_CFG_SCALER_BIT 24 + +#define GRCAN_CTRL_RESET 0x2 +#define GRCAN_CTRL_ENABLE 0x1 + +#define GRCAN_TXCTRL_ENABLE 1 +#define GRCAN_TXCTRL_ONGOING 1 + +#define GRCAN_RXCTRL_ENABLE 1 +#define GRCAN_RXCTRL_ONGOING 1 + +/* Relative offset of IRQ sources to AMBA Plug&Play */ +#define GRCAN_IRQ_IRQ 0 +#define GRCAN_IRQ_TXSYNC 1 +#define GRCAN_IRQ_RXSYNC 2 + +#define GRCAN_ERR_IRQ 0x1 +#define GRCAN_OFF_IRQ 0x2 +#define GRCAN_OR_IRQ 0x4 +#define GRCAN_RXAHBERR_IRQ 0x8 +#define GRCAN_TXAHBERR_IRQ 0x10 +#define GRCAN_RXIRQ_IRQ 0x20 +#define GRCAN_TXIRQ_IRQ 0x40 +#define GRCAN_RXFULL_IRQ 0x80 +#define GRCAN_TXEMPTY_IRQ 0x100 +#define GRCAN_RX_IRQ 0x200 +#define GRCAN_TX_IRQ 0x400 +#define GRCAN_RXSYNC_IRQ 0x800 +#define GRCAN_TXSYNC_IRQ 0x1000 +#define GRCAN_RXERR_IRQ 0x2000 +#define GRCAN_TXERR_IRQ 0x4000 +#define GRCAN_RXMISS_IRQ 0x8000 +#define GRCAN_TXLOSS_IRQ 0x10000 + +#define GRCAN_STAT_PASS 0x1 +#define GRCAN_STAT_OFF 0x2 +#define GRCAN_STAT_OR 0x4 +#define GRCAN_STAT_AHBERR 0x8 +#define GRCAN_STAT_ACTIVE 0x10 +#define GRCAN_STAT_RXERRCNT 0xff00 +#define GRCAN_STAT_TXERRCNT 0xff0000 + +/* + * Return number of GRCAN devices available to driver + */ +extern int grcan_dev_count(void); + +/* + * Open a GRCAN device + * + * dev_no: Device number to open + * return: Device handle to use with all other grcan_ API functions. The + * function returns NULL if device can not be opened. + */ +extern void *grcan_open(int dev_no); + +/* + * Open a GRCAN device by name. Finds device index then calls + * grcan_open(index). + * + * name: Device name to open + * dev_no: Device number matching name. Will be set if device found. + * return: Device handle to use with all other grcan_ API functions. The + * function returns NULL if device can not be opened or not found. + */ +extern void *grcan_open_by_name(char *name, int *dev_no); + +/* + * Close a GRCAN device + * + * return: This function always returns 0 (success) + */ +extern int grcan_close(void *d); + +/* + * Receive CAN messages + * + * Multiple CAN messages can be received in one call. + * + * d: Device handle + * msg: Pointer to receive messages + * count: Number of CAN messages to receive + * + * return: + * >=0: Number of CAN messages received. This can be + * less than the count parameter. + * GRCAN_RET_INVARG: count parameter less than one or NULL msg. + * GRCAN_RET_NOTSTARTED: Device not in started mode + * GRCAN_RET_TIMEOUT: Timeout in non-blocking mode + * GRCAN_RET_BUSOFF: A read was interrupted by a bus-off error. + * Device has left started mode. + * GRCAN_RET_AHBERR: Similar to BUSOFF, but was caused by AHB Error. + */ +extern int grcan_read( + void *d, + CANMsg *msg, + size_t count +); + +/* + * Transmit CAN messages + * + * Multiple CAN messages can be transmit in one call. + * + * d: Device handle + * msg: Pointer to messages to transmit + * count: Number of CAN messages to transmit + * + * return: + * >=0: Number of CAN messages transmitted. This can be + * less than the count parameter. + * GRCAN_RET_INVARG: count parameter less than one. + * GRCAN_RET_NOTSTARTED: Device not in started mode + * GRCAN_RET_TIMEOUT: Timeout in non-blocking mode + * GRCAN_RET_BUSOFF: A write was interrupted by a Bus-off error. + * Device has left started mode + * GRCAN_RET_AHBERR: Similar to BUSOFF, but was caused by AHB Error. + */ +extern int grcan_write( + void *d, + CANMsg *msg, + size_t count +); + +/* + * Returns current GRCAN software state + * + * If STATE_BUSOFF or STATE_AHBERR is returned then the function grcan_stop() + * shall be called before continue using the driver. + * + * d: Device handle + * return: + * STATE_STOPPED Stopped + * STATE_STARTED Started + * STATE_BUSOFF Bus-off has been detected + * STATE_AHBERR AHB error has been detected + */ +extern int grcan_get_state(void *d); + +/* The remaining functions return 0 on success and non-zero on failure. */ + +/* Functions controlling operational + * mode + */ +/* Bring the link up after open or bus-off */ +extern int grcan_start(void *d); +/* stop to change baud rate/config or closing down */ +extern int grcan_stop(void *d); +/* Wait until all TX messages have been sent */ +extern int grcan_flush(void *d); + +/* Functions that require connection + * to be stopped + */ +/* enable silent mode read only state */ +extern int grcan_set_silent(void *d, int silent); +/* enable/disable stopping link on AHB Error */ +extern int grcan_set_abort(void *d, int abort); +/* Set Enable0,Enable1,Selection */ +extern int grcan_set_selection(void *d, const struct grcan_selection *selection); +/* Set baudrate by using driver's baud rate timing calculation routines */ +extern int grcan_set_speed(void *d, unsigned int hz); +/* Set baudrate by specifying the timing registers manually */ +extern int grcan_set_btrs(void *d, const struct grcan_timing *timing); + +/* Functions can be called whenever */ +/* Enable/disable Blocking on reception (until at least one message has been received) */ +int grcan_set_rxblock(void* d, int block); +/* Enable/disable Blocking on transmission (until at least one message has been transmitted) */ +int grcan_set_txblock(void* d, int block); +/* Enable/disable Blocking until all requested messages has been sent */ +int grcan_set_txcomplete(void* d, int complete); +/* Enable/disable Blocking until all requested has been received */ +int grcan_set_rxcomplete(void* d, int complete); +/* Get statistics */ +extern int grcan_get_stats(void *d, struct grcan_stats *stats); +/* Clear statistics */ +extern int grcan_clr_stats(void *d); +/* Set Acceptance filters, provide pointer to "struct grcan_filter" or NULL to disable filtering (let all messages pass) */ +extern int grcan_set_afilter(void *d, const struct grcan_filter *filter); +/* Set Sync Messages RX/TX filters, NULL disables the IRQ completely */ +extern int grcan_set_sfilter(void *d, const struct grcan_filter *filter); +/* Get status register of GRCAN core */ +extern int grcan_get_status(void *d, unsigned int *status); + +void grcan_register_drv(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/grctm.h b/bsps/sparc/include/bsp/grctm.h new file mode 100644 index 0000000000..5ff81559aa --- /dev/null +++ b/bsps/sparc/include/bsp/grctm.h @@ -0,0 +1,171 @@ +/* GRCTM - CCSDS Time Manager - register driver interface. + * + * COPYRIGHT (c) 2009. + * Cobham Gaisler AB + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRCTM_H__ +#define __GRCTM_H__ + +#define DAT0_IRQ 0x1 +#define DAT1_IRQ 0x2 +#define DAT2_IRQ 0x4 +#define PULSE0_IRQ 0x10 +#define PULSE1_IRQ 0x20 +#define PULSE2_IRQ 0x40 +#define PULSE3_IRQ 0x80 +#define PULSE4_IRQ 0x100 +#define PULSE5_IRQ 0x200 +#define PULSE6_IRQ 0x400 +#define PULSE7_IRQ 0x800 + +struct grctm_regs { + volatile unsigned int grr; + volatile unsigned int gcr; + volatile unsigned int gsr; + volatile unsigned int unused[2]; + volatile unsigned int pfr; + volatile unsigned int etcr; + volatile unsigned int etfr; + volatile unsigned int dcr0; + volatile unsigned int dfr0; + volatile unsigned int dcr1; + volatile unsigned int dfr1; + volatile unsigned int dcr2; + volatile unsigned int dfr2; + volatile unsigned int stcr; + volatile unsigned int stfr; + volatile unsigned int pdr[8]; + volatile unsigned int pimsr; + volatile unsigned int pimr; + volatile unsigned int pisr; + volatile unsigned int pir; + volatile unsigned int imr; + volatile unsigned int picr; + volatile unsigned int unused1[2]; + volatile unsigned int etir; + volatile unsigned int fsir; + volatile unsigned int serconf; + volatile unsigned int unused2; + volatile unsigned int twsc; + volatile unsigned int twadj; + volatile unsigned int twtx; + volatile unsigned int twrx; +}; + +struct grctm_stats { + + /* IRQ Stats */ + unsigned int nirqs; + unsigned int pulse; +}; + +/* Function ISR callback prototype */ +typedef void (*grctm_isr_t)(unsigned int pimr, void *data); + +/* Open a GRCTM device by minor number. */ +extern void *grctm_open(int minor); + +/* Close a previously opened GRCTM device */ +extern void grctm_close(void *spwcuc); + +/* Hardware Reset of GRCTM */ +extern int grctm_reset(void *grctm); + +/* Enable Interrupts at Interrupt controller */ +extern void grctm_int_enable(void *grctm); + +/* Disable Interrupts at Interrupt controller */ +extern void grctm_int_disable(void *grctm); + +/* Clear Statistics gathered by the driver */ +extern void grctm_clr_stats(void *grctm); + +/* Get Statistics gathered by the driver */ +extern void grctm_get_stats(void *grctm, struct grctm_stats *stats); + +/* Register an Interrupt handler and custom data, the function call is + * removed by setting func to NULL. + */ +extern void grctm_int_register(void *grctm, grctm_isr_t func, void *data); + +/* Enable external synchronisation (from spwcuc) */ +extern void grctm_enable_ext_sync(void *grctm); + +/* Disable external synchronisation (from spwcuc) */ +extern void grctm_disable_ext_sync(void *grctm); + +/* Enable TimeWire synchronisation */ +extern void grctm_enable_tw_sync(void *grctm); + +/* Disable TimeWire synchronisation */ +extern void grctm_disable_tw_sync(void *grctm); + +/* Disable frequency synthesizer from driving ET */ +extern void grctm_disable_fs(void *grctm); + +/* Enable frequency synthesizer to drive ET */ +extern void grctm_enable_fs(void *grctm); + +/* Return elapsed coarse time */ +extern unsigned int grctm_get_et_coarse(void *grctm); + +/* Return elapsed fine time */ +extern unsigned int grctm_get_et_fine(void *grctm); + +/* Return elapsed time (coarse and fine) */ +extern unsigned long long grctm_get_et(void *grctm); + +/* Return 1 if specified datation has been latched */ +extern int grctm_is_dat_latched(void *grctm, int dat); + +/* Set triggering edge of datation input */ +extern void grctm_set_dat_edge(void *grctm, int dat, int edge); + +/* Return latched datation coarse time */ +extern unsigned int grctm_get_dat_coarse(void *grctm, int dat); + +/* Return latched datation fine time */ +extern unsigned int grctm_get_dat_fine(void *grctm, int dat); + +/* Return latched datation ET */ +extern unsigned long long grctm_get_dat_et(void *grctm, int dat); + +/* Return current pulse configuration */ +extern unsigned int grctm_get_pulse_reg(void *grctm, int pulse); + +/* Set pulse register */ +extern void grctm_set_pulse_reg(void *grctm, int pulse, unsigned int val); + +/* Configure pulse: pp = period, pw = width, pl = level, en = enable */ +extern void grctm_cfg_pulse(void *grctm, int pulse, int pp, int pw, int pl, int en); + +/* Enable pulse output */ +extern void grctm_enable_pulse(void *grctm, int pulse); + +/* Disable pulse output */ +extern void grctm_disable_pulse(void *grctm, int pulse); + +/* Clear interrupts */ +extern void grctm_clear_irqs(void *grctm, int irqs); + +/* Enable interrupts */ +extern void grctm_enable_irqs(void *grctm, int irqs); + +/* Set Frequency synthesizer increment */ +void grctm_set_fs_incr(void *grctm, int incr); + +/* Set ET increment */ +void grctm_set_et_incr(void *grctm, int incr); + +/* Get register base address */ +struct grctm_regs *grctm_get_regs(void *grctm); + +/* Register the GRCTM driver to Driver Manager */ +extern void grctm_register(void); + +#endif diff --git a/bsps/sparc/include/bsp/greth.h b/bsps/sparc/include/bsp/greth.h new file mode 100644 index 0000000000..9209d823e3 --- /dev/null +++ b/bsps/sparc/include/bsp/greth.h @@ -0,0 +1,157 @@ +/* + * Cobham Gaisler ethernet MAC driver + * adapted from Opencores driver by Marko Isomaki + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRETH_H__ +#define __GRETH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Ethernet configuration registers */ + +typedef struct _greth_regs { + volatile uint32_t ctrl; /* Ctrl Register */ + volatile uint32_t status; /* Status Register */ + volatile uint32_t mac_addr_msb; /* Bit 47-32 of MAC address */ + volatile uint32_t mac_addr_lsb; /* Bit 31-0 of MAC address */ + volatile uint32_t mdio_ctrl; /* MDIO control and status */ + volatile uint32_t txdesc; /* Transmit descriptor pointer */ + volatile uint32_t rxdesc; /* Receive descriptor pointer */ +} greth_regs; + +#define GRETH_TOTAL_BD 128 +#define GRETH_MAXBUF_LEN 1520 + +/* Tx BD */ +#define GRETH_TXD_ENABLE 0x0800 /* Tx BD Enable */ +#define GRETH_TXD_WRAP 0x1000 /* Tx BD Wrap (last BD) */ +#define GRETH_TXD_IRQ 0x2000 /* Tx BD IRQ Enable */ +#define GRETH_TXD_MORE 0x20000 /* Tx BD More (more descs for packet) */ +#define GRETH_TXD_IPCS 0x40000 /* Tx BD insert ip chksum */ +#define GRETH_TXD_TCPCS 0x80000 /* Tx BD insert tcp chksum */ +#define GRETH_TXD_UDPCS 0x100000 /* Tx BD insert udp chksum */ + +#define GRETH_TXD_UNDERRUN 0x4000 /* Tx BD Underrun Status */ +#define GRETH_TXD_RETLIM 0x8000 /* Tx BD Retransmission Limit Status */ +#define GRETH_TXD_LATECOL 0x10000 /* Tx BD Late Collision */ + +#define GRETH_TXD_STATS (GRETH_TXD_UNDERRUN | \ + GRETH_TXD_RETLIM | \ + GRETH_TXD_LATECOL) + +#define GRETH_TXD_CS (GRETH_TXD_IPCS | \ + GRETH_TXD_TCPCS | \ + GRETH_TXD_UDPCS) + +/* Rx BD */ +#define GRETH_RXD_ENABLE 0x0800 /* Rx BD Enable */ +#define GRETH_RXD_WRAP 0x1000 /* Rx BD Wrap (last BD) */ +#define GRETH_RXD_IRQ 0x2000 /* Rx BD IRQ Enable */ + +#define GRETH_RXD_DRIBBLE 0x4000 /* Rx BD Dribble Nibble Status */ +#define GRETH_RXD_TOOLONG 0x8000 /* Rx BD Too Long Status */ +#define GRETH_RXD_CRCERR 0x10000 /* Rx BD CRC Error Status */ +#define GRETH_RXD_OVERRUN 0x20000 /* Rx BD Overrun Status */ +#define GRETH_RXD_LENERR 0x40000 /* Rx BD Length Error */ +#define GRETH_RXD_ID 0x40000 /* Rx BD IP Detected */ +#define GRETH_RXD_IR 0x40000 /* Rx BD IP Chksum Error */ +#define GRETH_RXD_UD 0x40000 /* Rx BD UDP Detected*/ +#define GRETH_RXD_UR 0x40000 /* Rx BD UDP Chksum Error */ +#define GRETH_RXD_TD 0x40000 /* Rx BD TCP Detected */ +#define GRETH_RXD_TR 0x40000 /* Rx BD TCP Chksum Error */ + + +#define GRETH_RXD_STATS (GRETH_RXD_OVERRUN | \ + GRETH_RXD_DRIBBLE | \ + GRETH_RXD_TOOLONG | \ + GRETH_RXD_CRCERR) + +/* CTRL Register */ +#define GRETH_CTRL_TXEN 0x00000001 /* Transmit Enable */ +#define GRETH_CTRL_RXEN 0x00000002 /* Receive Enable */ +#define GRETH_CTRL_TXIRQ 0x00000004 /* Transmit Enable */ +#define GRETH_CTRL_RXIRQ 0x00000008 /* Receive Enable */ +#define GRETH_CTRL_FULLD 0x00000010 /* Full Duplex */ +#define GRETH_CTRL_PRO 0x00000020 /* Promiscuous (receive all) */ +#define GRETH_CTRL_RST 0x00000040 /* Reset MAC */ +#define GRETH_CTRL_SP 0x00000080 /* 100MBit speed mode */ +#define GRETH_CTRL_GB 0x00000100 /* 1GBit speed mode */ +#define GRETH_CTRL_DD 0x00001000 /* Disable EDCL Duplex Detection */ +#define GRETH_CTRL_ED 0x00004000 /* EDCL Disable */ + +/* Status Register */ +#define GRETH_STATUS_RXERR 0x00000001 /* Receive Error */ +#define GRETH_STATUS_TXERR 0x00000002 /* Transmit Error IRQ */ +#define GRETH_STATUS_RXIRQ 0x00000004 /* Receive Frame IRQ */ +#define GRETH_STATUS_TXIRQ 0x00000008 /* Transmit Error IRQ */ +#define GRETH_STATUS_RXAHBERR 0x00000010 /* Receiver AHB Error */ +#define GRETH_STATUS_TXAHBERR 0x00000020 /* Transmitter AHB Error */ + +/* MDIO Control */ +#define GRETH_MDIO_WRITE 0x00000001 /* MDIO Write */ +#define GRETH_MDIO_READ 0x00000002 /* MDIO Read */ +#define GRETH_MDIO_LINKFAIL 0x00000004 /* MDIO Link failed */ +#define GRETH_MDIO_BUSY 0x00000008 /* MDIO Link Busy */ +#define GRETH_MDIO_REGADR 0x000007C0 /* Register Address */ +#define GRETH_MDIO_PHYADR 0x0000F800 /* PHY address */ +#define GRETH_MDIO_DATA 0xFFFF0000 /* MDIO DATA */ + + +/* MII registers */ +#define GRETH_MII_EXTADV_1000FD 0x00000200 +#define GRETH_MII_EXTADV_1000HD 0x00000100 +#define GRETH_MII_EXTPRT_1000FD 0x00000800 +#define GRETH_MII_EXTPRT_1000HD 0x00000400 + +#define GRETH_MII_100T4 0x00000200 +#define GRETH_MII_100TXFD 0x00000100 +#define GRETH_MII_100TXHD 0x00000080 +#define GRETH_MII_10FD 0x00000040 +#define GRETH_MII_10HD 0x00000020 + + +/* Attach routine */ + +void greth_register_drv(void); + +/* PHY data */ +struct phy_device_info +{ + int vendor; + int device; + int rev; + + int adv; + int part; + + int extadv; + int extpart; +}; + +/* Limit speed modes advertised during auto-negotiation */ +#define GRETH_ADV_10_HD 0x0001 +#define GRETH_ADV_10_FD 0x0002 +#define GRETH_ADV_100_HD 0x0004 +#define GRETH_ADV_100_FD 0x0008 +#define GRETH_ADV_1000_HD 0x0010 +#define GRETH_ADV_1000_FD 0x0020 +#define GRETH_ADV_ALL 0x003f +/* +#ifdef CPU_U32_FIX +void ipalign(struct mbuf *m); +#endif + +*/ +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsps/sparc/include/bsp/grgpio.h b/bsps/sparc/include/bsp/grgpio.h new file mode 100644 index 0000000000..c49054548c --- /dev/null +++ b/bsps/sparc/include/bsp/grgpio.h @@ -0,0 +1,25 @@ +/* + * GRGPIO GPIO Driver interface. + * + * COPYRIGHT (c) 2009. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRGPIO_H__ +#define __GRGPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void grgpio_register_drv (void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/griommu.h b/bsps/sparc/include/bsp/griommu.h new file mode 100644 index 0000000000..2bafe4c513 --- /dev/null +++ b/bsps/sparc/include/bsp/griommu.h @@ -0,0 +1,187 @@ +/* + * GRIOMMU Driver Interface + * + * COPYRIGHT (c) 2017 + * Cobham Gaisler AB + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * OVERVIEW + * ======== + * This driver controls the GRIOMMU device located + * at an on-chip AMBA. + */ + +#ifndef __GRIOMMU_H__ +#define __GRIOMMU_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void griommu_register_drv(void); + +#define GRIOMMU_ERR_OK 0 +#define GRIOMMU_ERR_NOINIT -1 +#define GRIOMMU_ERR_EINVAL -2 +#define GRIOMMU_ERR_IMPLEMENTED -3 +#define GRIOMMU_ERR_NOTFOUND -4 + +/* Size of APV (has to be divided by page size in bytes) */ +#define GRIOMMU_APV_SIZE 0x20000000 + +/* Alignment of APV */ +#define GRIOMMU_APV_ALIGN 0x10 + +/* IOMMU APV allocation helper functions */ +extern void * griommu_apv_new(void); +extern void griommu_apv_delete(void * apv); + +/* IOMMU Master Setup */ + +/* IOMMU Master find */ +/* + * GRIOMMU MASTER register fields + */ +#define MASTER_VENDOR (0xff << MASTER_VENDOR_BIT) +#define MASTER_DEVICE (0xfff << MASTER_DEVICE_BIT) +#define MASTER_BS (0x1 << MASTER_BS_BIT) +#define MASTER_GROUP (0xf << MASTER_GROUP_BIT) + +#define MASTER_VENDOR_BIT 24 +#define MASTER_DEVICE_BIT 12 +#define MASTER_BS_BIT 4 +#define MASTER_GROUP_BIT 0 + +#define GRIOMMU_OPTIONS_BUS0 0 +#define GRIOMMU_OPTIONS_BUS1 1 +extern int griommu_master_setup(int master, int group, int options); +extern int griommu_master_find(int vendor, int device, int instance); +extern int griommu_master_info(int master, uint32_t * info); +#define griommu_get_master_vendor(info) \ + ((info & MASTER_VENDOR) >> MASTER_VENDOR_BIT) +#define griommu_get_master_device(info) \ + ((info & MASTER_DEVICE) >> MASTER_DEVICE_BIT) +#define griommu_get_master_routing(info) \ + ((info & MASTER_BS) >> MASTER_BS_BIT) +#define griommu_get_master_group(info) \ + ((info & MASTER_GROUP) >> MASTER_GROUP_BIT) + +/* IOMMU Group Setup */ +#define GRIOMMU_OPTIONS_GROUP_PASSTHROUGH 2 +#define GRIOMMU_OPTIONS_GROUP_ENABLE 1 +#define GRIOMMU_OPTIONS_GROUP_DISABLE 0 +extern int griommu_group_setup(int group, void * apv, int options); +extern int griommu_group_info(int group, uint32_t * info); +#define GRIOMMU_OPTIONS_APV_ALLOW 0x1 +#define GRIOMMU_OPTIONS_APV_DONTALLOW 0x0 +extern int griommu_group_apv_init(int group, int options); +extern int griommu_group_apv_address_set(int group, uint32_t addr, int size, + int options); +extern int griommu_group_apv_page_set(int group, int index, int size, + int options); +extern int griommu_group_apv_flush(int group); + +/* IOMMU Setup */ +/* + * GRIOMMU CTRL register fields + */ +#define CTRL_PGSZ (0x7 << CTRL_PGSZ_BIT) +#define CTRL_LB (0x1 << CTRL_LB_BIT) +#define CTRL_SP (0x1 << CTRL_SP_BIT) +#define CTRL_ITR (0xf << CTRL_ITR_BIT) +#define CTRL_DP (0x1 << CTRL_DP_BIT) +#define CTRL_SIV (0x1 << CTRL_SIV_BIT) +#define CTRL_HPROT (0x3 << CTRL_HPROT_BIT) +#define CTRL_AU (0x1 << CTRL_AU_BIT) +#define CTRL_WP (0x1 << CTRL_WP_BIT) +#define CTRL_DM (0x1 << CTRL_DM_BIT) +#define CTRL_GS (0x1 << CTRL_GS_BIT) +#define CTRL_CE (0x1 << CTRL_CE_BIT) +#define CTRL_PM (0x3 << CTRL_PM_BIT) +#define CTRL_PM_APV (0x0 << CTRL_PM_BIT) +#define CTRL_PM_IOMMU (0x1 << CTRL_PM_BIT) +#define CTRL_EN (0x1 << CTRL_EN_BIT) + +#define CTRL_PGSZ_BIT 18 +#define CTRL_LB_BIT 17 +#define CTRL_SP_BIT 16 +#define CTRL_ITR_BIT 12 +#define CTRL_DP_BIT 11 +#define CTRL_SIV_BIT 10 +#define CTRL_HPROT_BIT 8 +#define CTRL_AU_BIT 7 +#define CTRL_WP_BIT 6 +#define CTRL_DM_BIT 5 +#define CTRL_GS_BIT 4 +#define CTRL_CE_BIT 3 +#define CTRL_PM_BIT 1 +#define CTRL_EN_BIT 0 + +#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS0 0 +#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS1 CTRL_LB +#define GRIOMMU_OPTIONS_CACHE_DISABLE 0 +#define GRIOMMU_OPTIONS_CACHE_ENABLE CTRL_CE +#define GRIOMMU_OPTIONS_GROUPADDRESSING_DISABLE 0 +#define GRIOMMU_OPTIONS_GROUPADDRESSING_ENABLE CTRL_GS +#define GRIOMMU_OPTIONS_WPROTONLY_DISABLE 0 +#define GRIOMMU_OPTIONS_WPROTONLY_ENABLE CTRL_WP +#define GRIOMMU_OPTIONS_AHBUPDATE_DISABLE 0 +#define GRIOMMU_OPTIONS_AHBUPDATE_ENABLE CTRL_AU +#define GRIOMMU_OPTIONS_PREFETCH_DISABLE CTRL_DP +#define GRIOMMU_OPTIONS_PREFETCH_ENABLE 0 +#define GRIOMMU_OPTIONS_PAGESIZE_4KIB 0 +#define GRIOMMU_OPTIONS_PAGESIZE_8KIB (0x1 << CTRL_PGSZ_BIT) +#define GRIOMMU_OPTIONS_PAGESIZE_16KIB (0x2 << CTRL_PGSZ_BIT) +#define GRIOMMU_OPTIONS_PAGESIZE_32KIB (0x3 << CTRL_PGSZ_BIT) +#define GRIOMMU_OPTIONS_PAGESIZE_64KIB (0x4 << CTRL_PGSZ_BIT) +#define GRIOMMU_OPTIONS_PAGESIZE_128KIB (0x5 << CTRL_PGSZ_BIT) +#define GRIOMMU_OPTIONS_PAGESIZE_256KIB (0x6 << CTRL_PGSZ_BIT) +#define GRIOMMU_OPTIONS_PAGESIZE_512KIB (0x7 << CTRL_PGSZ_BIT) +extern int griommu_setup(int options); +extern int griommu_status(void); + +#define GRIOMMU_MODE_IOMMU 1 +#define GRIOMMU_MODE_GROUPAPV 0 +extern int griommu_enable(int mode); +extern int griommu_disable(void); + +/* IOMMU APV setup */ +extern int griommu_apv_flush(void); +extern int griommu_apv_init(void * apv, int options); +extern int griommu_apv_address_set(void * apv, uint32_t addr, int size, + int options); +extern int griommu_apv_page_set(void * apv, int index, int size, int options); + +/* GRIOMMU Interrupts */ +/* Function Interrupt-Code ISR callback prototype. + * arg - Custom arg provided by user + * access - AHB Access that failed + * status - Error status register of the GRIOMMU core + */ +typedef void (*griommu_isr_t)(void *arg, uint32_t access, uint32_t status); +#define GRIOMMU_INTERRUPT_ALL (0x2f << 0) +#define GRIOMMU_INTERRUPT_PARITY_ERROR (0x1 << 5) +#define GRIOMMU_INTERRUPT_FLUSH_COMPLETED (0x1 << 3) +#define GRIOMMU_INTERRUPT_FLUSH_START (0x1 << 2) +#define GRIOMMU_INTERRUPT_ACCESS_DENIED (0x1 << 1) +#define GRIOMMU_INTERRUPT_TRANSLATION_ERROR (0x1 << 0) +extern int griommu_isr_register(griommu_isr_t isr, void * arg, int options); +extern int griommu_isr_unregister(void); +extern int griommu_interrupt_unmask(int options); +extern int griommu_interrupt_mask(int options); + +extern int griommu_error_status(uint32_t * access); + +extern int griommu_print(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __GRIOMMU_H__ */ diff --git a/bsps/sparc/include/bsp/grpci.h b/bsps/sparc/include/bsp/grpci.h new file mode 100644 index 0000000000..2321706200 --- /dev/null +++ b/bsps/sparc/include/bsp/grpci.h @@ -0,0 +1,31 @@ +#ifndef __GRPCI_H__ +#define __GRPCI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register the GRPCI driver to the Driver Manager */ +extern void grpci_register_drv(void); + +/* Transfer data using GRPCI DMA unit from AMBA to PCI space. Blocks until + * operation completes. + */ +int grpci_dma_to_pci( + unsigned int ahb_addr, + unsigned int pci_addr, + unsigned int len); + +/* Transfer data using GRPCI DMA unit from PCI to AMBA space. Blocks until + * operation completes. + */ +int grpci_dma_from_pci( + unsigned int ahb_addr, + unsigned int pci_addr, + unsigned int len); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/grpci2.h b/bsps/sparc/include/bsp/grpci2.h new file mode 100644 index 0000000000..c356b5641f --- /dev/null +++ b/bsps/sparc/include/bsp/grpci2.h @@ -0,0 +1,65 @@ +/* GRLIB GRPCI2 PCI HOST driver. + * + * COPYRIGHT (c) 2011 + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRPCI2_H__ +#define __GRPCI2_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void grpci2_register_drv(void); + +/* Driver Resources: + * + * PCI Interrupts + * ============== + * The interrupt settings are normally autodetected from Plyg&Play, however + * if IRQs are routed using custom GPIO pins in order to reduce the PIN count + * reserved for PCI, the options below can be used to tell GRPCI2 driver which + * System IRQ a PCI interrupt is connected to. + * Name="INTA#", Type=INT, System Interrupt number that PCI INTA is connected to + * Name="INTB#", Type=INT, System Interrupt number that PCI INTB is connected to + * Name="INTC#", Type=INT, System Interrupt number that PCI INTC is connected to + * Name="INTD#", Type=INT, System Interrupt number that PCI INTD is connected to + * + * Name="IRQmask", Type=INT, + * + * PCI Bytetwisting (endianess) + * ============================ + * Name="byteTwisting", Type=INT, Enable/Disable Bytetwisting by hardware + * + * PCI Latency timer + * ============================ + * Name="latencyTimer", Type=INT, Set the latency timer + * + * PCI Host's Target BARs setup + * ============================ + * The Host's BARs are not configured by the configuration routines, by default + * the BARs are configured disabled (BAR=0) except for BAR0 which is mapped to + * the Main Memory for the Host. + * Name="tgtBarCfg", Type=PTR (*grpci2_pcibar_cfg), Target PCI BARs of Host + */ + +/* When the Host acts as a target on the PCI bus, the PCI BARs of the host's + * configuration space determine at which PCI address the Host will be accessed + * at and when accessing a BAR which AMBA address it will be translated to. + */ +struct grpci2_pcibar_cfg { + unsigned int pciadr; /* PCI address of BAR (BAR content) */ + unsigned int ahbadr; /* 'pciadr' translated to this AHB Address */ + unsigned int barsize; /* PCI BAR Size, must be a power of 2 */ +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/grpci2dma.h b/bsps/sparc/include/bsp/grpci2dma.h new file mode 100644 index 0000000000..c1a2663a86 --- /dev/null +++ b/bsps/sparc/include/bsp/grpci2dma.h @@ -0,0 +1,263 @@ +/* + * GRPCI2 DMA Driver + * + * COPYRIGHT (c) 2017 + * Cobham Gaisler AB + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * OVERVIEW + * ======== + * This driver controls the DMA on the GRPCI2 device, located + * at an on-chip AMBA. + */ + +#ifndef __GRPCI2DMA_H__ +#define __GRPCI2DMA_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Error return codes */ +#define GRPCI2DMA_ERR_OK 0 +#define GRPCI2DMA_ERR_WRONGPTR -1 +#define GRPCI2DMA_ERR_NOINIT -2 +#define GRPCI2DMA_ERR_TOOMANY -3 +#define GRPCI2DMA_ERR_ERROR -4 +#define GRPCI2DMA_ERR_STOPDMA -5 +#define GRPCI2DMA_ERR_NOTFOUND -6 + +/* Size of a dma descriptors */ +#define GRPCI2DMA_BD_CHAN_SIZE 0x10 +#define GRPCI2DMA_BD_DATA_SIZE 0x10 + +/* Alignment of dma descriptors */ +#define GRPCI2DMA_BD_CHAN_ALIGN 0x10 +#define GRPCI2DMA_BD_DATA_ALIGN 0x10 + +/* User-helper functions to allocate/deallocate + * channel and data descriptors + */ +extern void * grpci2dma_channel_new(int number); +extern void grpci2dma_channel_delete(void * chanbd); +extern void * grpci2dma_data_new(int number); +extern void grpci2dma_data_delete(void * databd); + +/* Function: + * -grpci2dma_prepare + * Description: + * -Prepare a transfer, initializing the required data descriptors + * Parameters: + * -pci_start: Where in PCI/remote starts the transfer + * -ahb_start: Where in AHB/local starts the transfer + * -dir: Direction of the transfer (AHBTOPCI or PCITOAHB) + * -endianness: Endianness of the transfer (LITTLEENDIAN or BIGENDIAN) + * -size: Size in bytes of the transfer (the function will calculate if there + * are enough descriptors) + * -databd: Pointer to the data descriptor buffer + * -bdindex: Where in the buffer to start the transfer + * -bdmax: Maximum index for the data descriptor buffer + * -block_size: Size in bytes for each PCI transaction (or block). Guaranteed + * to be at least smaller that this value. Put 0 to use default. + * Default is maximum, which is 0x10000*4 bytes. + * Returns: + * -WRONGPTR: Wrong input parameters + * -TOOMANY: Not enough data descriptors in the buffer + * -value > 0: A positive return value means the number of data descriptors + * prepared/used in the buffer, starting from index. + */ +#define GRPCI2DMA_AHBTOPCI 1 +#define GRPCI2DMA_PCITOAHB 0 +#define GRPCI2DMA_LITTLEENDIAN 1 +#define GRPCI2DMA_BIGENDIAN 0 +extern int grpci2dma_prepare( + uint32_t pci_start, uint32_t ahb_start, int dir, int endianness, + int size, void * databd, int bdindex, int bdmax, int block_size); + +/* Function: + * -grpci2dma_status + * Description: + * -Status of an transfer: + * Parameters: + * -databd: Pointer to the data descriptor buffer + * -bdindex: Where in the buffer starts the transfer + * -bdsize: Number of descriptors used by the transfer + * Returns: + * -WRONGPTR: Wrong input parameters + * -GRPCI2DMA_BD_DATA_STATUS_ERR: If at least one of the descriptors has an + * error + * -GRPCI2DMA_BD_DATA_STATUS_ENABLED: If at least one of the descriptors is + * enabled, which means that the transfer is still not finished. + * -GRPCI2DMA_BD_DATA_STATUS_DISABLED: If all the descriptors are disabled, + * which means that either the transfer finished or it was never prepared. + */ +#define GRPCI2DMA_BD_STATUS_DISABLED 0 +#define GRPCI2DMA_BD_STATUS_ENABLED 1 +#define GRPCI2DMA_BD_STATUS_ERR 2 +extern int grpci2dma_status(void *databd, int bdindex, int bdsize); + +/* Function Interrupt-Code ISR callback prototype. + * arg - Custom arg provided by user + * cid - Channel ID that got the interrupt + * status - Error status of the DMA core + */ +typedef void (*grpci2dma_isr_t)(void *arg, int cid, unsigned int status); + +/* Function: + * -grpci2dma_isr_register + * Description: + * -Register an ISR for a channel (and enable interrupts if disabled) + * Parameters: + * -chan_no: ID of the channel + * -dmaisr: ISR + * -arg: Argument to pass to the ISR when called + * Returns: + * -NOINIT: GRPCI2 DMA not initialized + * -WRONGPTR: Wrong input parameters + * -OK (=0): Done + */ +extern int grpci2dma_isr_register( + int chan_no, grpci2dma_isr_t dmaisr, void *arg); + +/* Function: + * -grpci2dma_isr_unregister + * Description: + * -Unregister an ISR for a channel (and enable interrupts if disabled) + * Parameters: + * -chan_no: ID of the channel + * Returns: + * -NOINIT: GRPCI2 DMA not initialized + * -WRONGPTR: Wrong input parameters + * -OK (=0): Done + */ +extern int grpci2dma_isr_unregister(int chan_no); + +/* Function: + * -grpci2dma_open + * Description: + * -Open a channel (and allocate the descriptor if the user does not provide + * one). + * Parameters: + * -chan: Descriptor for the channel (must be aligned to 0x10) + * Returns: + * -NOINIT: GRPCI2 DMA not initialized + * -TOOMANY: Maximum number of channels already opened. + * -WRONGPTR: Wrong input parameters + * -ERROR: Inconsistent state found in driver + * -value > 0: A positive return value means the id for the channel. + */ +extern int grpci2dma_open(void * chan); + +/* Function: + * -grpci2dma_close + * Description: + * -Stop and close a channel (and deallocate it if the user did not provide a + * pointer when opening it) + * Parameters: + * -chan_no: Id of the channel + * Returns: + * -NOINIT: GRPCI2 DMA not initialized + * -NOTFOUND: Channel not opened. + * -STOPDMA: Cannot stop channel. + * -WRONGPTR: Wrong input parameters + * -OK (=0): Done. + */ +extern int grpci2dma_close(int chan_no); + +/* Function: + * -grpci2dma_start + * Description: + * -Start a channel + * Parameters: + * -chan_no: Id of the channel + * -options: Maximum number of data descriptors to be executed before moving + * to next channel (up to 0x10000) + * Returns: + * -NOINIT: GRPCI2 DMA not initialized + * -WRONGPTR: Wrong input parameters + * -ERROR: Inconsistent state found in driver + * -OK (=0): Done. + */ +extern int grpci2dma_start(int chan_no, int options); + +/* Function: + * -grpci2dma_stop + * Description: + * -Start a channel + * Parameters: + * -chan_no: Id of the channel + * Returns: + * -NOINIT: GRPCI2 DMA not initialized + * -WRONGPTR: Wrong input parameters + * -ERROR: Inconsistent state found in driver + * -OK (=0): Done. + */ +extern int grpci2dma_stop(int chan_no); + +/* Function: + * -grpci2dma_push + * Description: + * -Push a transfer into a channel (already started or not) + * Parameters: + * -chan_no: Id of the channel + * -databd: Pointer to the data descriptor buffer + * -bdindex: Where in the buffer starts the transfer + * -bdsize: Number of descriptors used by the transfer + * Returns: + * -NOINIT: GRPCI2 DMA not initialized + * -WRONGPTR: Wrong input parameters + * -NOTFOUND: Channel not opened. + * -OK (=0): Done. + */ +extern int grpci2dma_push(int chan_no, void *databd, int bdindex, int bdsize); + +/* Function: + * -grpci2dma_active + * Description: + * -Check if dma is active + * Parameters: + * Returns: + * -(!=0): Active. + * -(=0): Not active. + */ +extern int grpci2dma_active(void); + +/* Function: + * -grpci2dma_interrupt_enable + * Description: + * -Enable interrupt for a transfer + * Parameters: + * -databd: Pointer to the data descriptor buffer + * -bdindex: Where in the buffer starts the transfer + * -bdmax: Upper limit for index. index < bdmax + * -options: + * (=GRPCI2DMA_OPTIONS_ALL)=Enable interrupt on all transfer descriptors. + * (=GRPCI2DMA_OPTIONS_ONE)=Enable interrupt on transfer descriptor + * indicated by bdindex. + * Returns: + * -NOINIT: GRPCI2 DMA not initialized + * -WRONGPTR: Wrong input parameters + * -ERROR: Inconsistent state found in driver + * -OK (=0): Done. + */ +#define GRPCI2DMA_OPTIONS_ALL 1 +#define GRPCI2DMA_OPTIONS_ONE 0 +extern int grpci2dma_interrupt_enable( + void *databd, int bdindex, int bdmax, int options); + +/* Debug function: print dma channel and associated data descriptors. + * Only prints if driver internal DEBUG flag is defined. */ +extern int grpci2dma_print(int chan_no); +extern int grpci2dma_print_bd(void * data); + +#ifdef __cplusplus +} +#endif + +#endif /* __GRPCI2DMA_H__ */ diff --git a/bsps/sparc/include/bsp/grpwm.h b/bsps/sparc/include/bsp/grpwm.h new file mode 100644 index 0000000000..6898f8ac2e --- /dev/null +++ b/bsps/sparc/include/bsp/grpwm.h @@ -0,0 +1,127 @@ +/* + * GRPWM PWM Driver interface. + * + * COPYRIGHT (c) 2009. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRPWM_H__ +#define __GRPWM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void grpwm_register_drv (void); + +#define GRPWM_IOCTL_GET_CAP 1 /* Get Capabilities */ +#define GRPWM_IOCTL_SET_CONFIG 2 /* Configure one PWM Channel */ +#define GRPWM_IOCTL_SET_SCALER 3 /* Set one scaler */ +#define GRPWM_IOCTL_UPDATE 4 /* Set current period and compare value */ +#define GRPWM_IOCTL_IRQ 5 /* Set up IRQ handling */ + +/*** Argument for GRPWM_IOCTL_GET_CAP ***/ + +/* The Capability of the PWM core */ +struct grpwm_ioctl_cap { + int channel_cnt; /* Number of channels */ + unsigned int pwm; /* Capability1 register */ + unsigned int wave; /* Capability2 register, Wave form capabilities of last PWM channel, otherwise 0 */ +}; + +/*** Argument for GRPWM_IOCTL_GET_CONFIG and GRPWM_IOCTL_SET_CONFIG ***/ + +/* Config One PWM */ +struct grpwm_ioctl_config { + unsigned int channel; /* Select channel to configure */ + + /* Specific for one PWM channel */ + unsigned int options; /* PWM options */ + unsigned char dbscaler; /* value greater than 15 disable Dead band */ + unsigned char scaler_index; /* Select scaler used by PWM channel */ + + /* IRQ Setup */ + unsigned char irqscaler; /* IRQ scaler */ + void *isr_arg; /* Argument of IRQ handler */ + void (*isr)(int channel, void *arg); /* Interrupt service routine for this PWM Channel */ + + /* Waveform set up */ + int wave_activate; /* Enables Waveform functionality */ + unsigned int wave_synccfg; /* Bits [29,30,31] is written into Wave-Config register */ + unsigned int wave_sync; /* Sets sync compare register */ + unsigned int *wave_data; /* If not NULL, the Wave RAM is filled with data */ + unsigned int wave_data_length; /* Length of Wave RAM Data, Also used for wstopaddr */ +}; + +#define GRPWM_CONFIG_OPTION_FLIP 0x04000000 /* Set this to Flip PWM output pair */ +#define GRPWM_CONFIG_OPTION_DEAD_BAND 0x00200000 /* Dead Band enable */ +#define GRPWM_CONFIG_OPTION_SYMMETRIC 0x00000040 /* If not defined, asymmetric */ +#define GRPWM_CONFIG_OPTION_ASYMMERTIC 0 +#define GRPWM_CONFIG_OPTION_DUAL 0x00000020 /* Dual Compare Enable */ +#define GRPWM_CONFIG_OPTION_PAIR 0x00000004 /* PWM Pair Enable */ +#define GRPWM_CONFIG_OPTION_SINGLE 0x00000000 /* PWM Pair Disable */ +#define GRPWM_CONFIG_OPTION_POLARITY_HIGH 0x00000002 /* PWM Polarity HIGH */ +#define GRPWM_CONFIG_OPTION_POLARITY_LOW 0x00000000 /* PWM Polarity LOW */ + +#define GRPWM_CONFIG_OPTION_MASK ( \ + GRPWM_CONFIG_OPTION_DEAD_BAND | GRPWM_CONFIG_OPTION_SYMMETRIC | \ + GRPWM_CONFIG_OPTION_DUAL | GRPWM_CONFIG_OPTION_PAIR | \ + GRPWM_CONFIG_OPTION_POLARITY_HIGH \ + ) + +/*** Argument for GPPWM_IOCTL_SET_SCALER ***/ + +struct grpwm_ioctl_scaler { + unsigned int index_mask;/* Scaler update index mask, bit 0 = Scaler 0, bit 1 = Scaler 1 */ + unsigned int values[8]; /* Scaler update values, values[N] is stored into scaler N, if mask & 1<> 16) & 0xF) +/* Get IO card # from received SLINK word */ +#define SLINK_WRD_CARDNUM(x) ((x >> 21) & 0x3) +/* Get data part from SLINK word */ +#define SLINK_WRD_PAYLOAD(x) (x & 0xFFFF) + +/* Checks status value to see if transmit queue has free slot */ +#define SLINK_STS_TRANSFREE(x) (x & SLINK_S_TNF) +/* Get Sequence Index value */ +#define SLINK_STS_SI(x) ((x >> 16) & 0xFF) + +/**** Function declarations, driver interface ****/ +/* Initializes the SLINK core */ +int SLINK_init(unsigned int nullwrd, int parity, int qsize, + void (*interrupt_trans_handler)(int), + void (*sequence_callback)(int)); + +/* Enables the core */ +void SLINK_start(void); + +/* Disables the core */ +void SLINK_stop(void); + +/* Reads one word */ +int SLINK_read(int data, int channel, int *reply); + +/* Writes one word */ +int SLINK_write(int data, int channel); + +/* Peforms a SEQUENCE */ +int SLINK_seqstart(int *a, int *b, int n, int channel, int reconly); + +/* Aborts a SEQUENCE */ +void SLINK_seqabort(void); + +/* Status of current or last SEQUENCE */ +int SLINK_seqstatus(void); + +/* Number of words transferred in last SEQUENCE */ +int SLINK_seqwrds(void); + +/* Returns value of core's status register */ +int SLINK_hwstatus(void); + +/* Returns number of elements in queue associated with IO card */ +int SLINK_queuestatus(int iocard); + +/* Take first element from queue for IO card # 'iocard' */ +int SLINK_dequeue(int iocard, int *elem); + +/* Returns structure containing core driver statistics */ +SLINK_stats *SLINK_statistics(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __GRSLINK_H__ */ diff --git a/bsps/sparc/include/bsp/grspw.h b/bsps/sparc/include/bsp/grspw.h new file mode 100644 index 0000000000..3270e8a5a2 --- /dev/null +++ b/bsps/sparc/include/bsp/grspw.h @@ -0,0 +1,168 @@ +/** + * @file + * @ingroup sparc_bsp + * @defgroup spw SpaceWire + * @ingroup spw + * @brief GRSPW Device Driver + */ + +/* + * COPYRIGHT (c) 2007. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRSPW_H__ +#define __GRSPW_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPW_LINKERR_EVENT RTEMS_EVENT_0 + +typedef struct { + unsigned int rxsize; + unsigned int txdsize; + unsigned int txhsize; +} spw_ioctl_packetsize; + +#define GRSPW_PKTSEND_OPTION_HDR_CRC 0x1 +#define GRSPW_PKTSEND_OPTION_DATA_CRC 0x2 +#define GRSPW_PKTSEND_OPTION_NOCRCLEN(len) ((len & 0xf) << 8) +#define GRSPW_PKTSEND_OPTION_NOCRCLEN_MASK 0xf00 + +typedef struct { + unsigned int hlen; + char *hdr; + unsigned int dlen; + char *data; + unsigned int sent; + unsigned int options; +} spw_ioctl_pkt_send; + +typedef struct { + unsigned int tx_link_err; + unsigned int rx_rmap_header_crc_err; + unsigned int rx_rmap_data_crc_err; + unsigned int rx_eep_err; + unsigned int rx_truncated; + unsigned int parity_err; + unsigned int escape_err; + unsigned int credit_err; + unsigned int write_sync_err; + unsigned int disconnect_err; + unsigned int early_ep; + unsigned int invalid_address; + unsigned int packets_sent; + unsigned int packets_received; +} spw_stats; + +typedef struct { + unsigned int nodeaddr; + unsigned int destkey; + unsigned int clkdiv; /* Note: contain both CLKDIVSTART and CLKDIVRUN, but IOCTL_SET_CLKDIV* commands are split into two */ + unsigned int rxmaxlen; + unsigned int timer; + unsigned int disconnect; + unsigned int promiscuous; + unsigned int rmapen; + unsigned int rmapbufdis; + unsigned int linkdisabled; + unsigned int linkstart; + + unsigned int check_rmap_err; /* check incoming packets for rmap errors */ + unsigned int rm_prot_id; /* remove protocol id from incoming packets */ + unsigned int tx_blocking; /* use blocking tx */ + unsigned int tx_block_on_full; /* block when all tx_buffers are used */ + unsigned int rx_blocking; /* block when no data is available */ + unsigned int disable_err; /* disable link automatically when link error is detected */ + unsigned int link_err_irq; /* generate an interrupt when link error occurs */ + rtems_id event_id; /* task id that should receive link err irq event */ + + unsigned int is_rmap; + unsigned int is_rxunaligned; + unsigned int is_rmapcrc; + + unsigned int nodemask; + unsigned int keep_source; /* copy source address to user-buffer in read() operations + * Note that rm_prot_id has no effect when keep_source is + * set. + */ + unsigned int rtimeout; /* Read timeout if != 0 */ +} spw_config; + +#define SPACEWIRE_IOCTRL_SET_NODEADDR 1 +#define SPACEWIRE_IOCTRL_SET_RXBLOCK 2 +#define SPACEWIRE_IOCTRL_SET_DESTKEY 4 +#define SPACEWIRE_IOCTRL_SET_CLKDIV 5 +#define SPACEWIRE_IOCTRL_SET_TIMER 6 +#define SPACEWIRE_IOCTRL_SET_DISCONNECT 7 +#define SPACEWIRE_IOCTRL_SET_PROMISCUOUS 8 +#define SPACEWIRE_IOCTRL_SET_RMAPEN 9 +#define SPACEWIRE_IOCTRL_SET_RMAPBUFDIS 10 +#define SPACEWIRE_IOCTRL_SET_CHECK_RMAP 11 +#define SPACEWIRE_IOCTRL_SET_RM_PROT_ID 12 +#define SPACEWIRE_IOCTRL_SET_TXBLOCK 14 +#define SPACEWIRE_IOCTRL_SET_DISABLE_ERR 15 +#define SPACEWIRE_IOCTRL_SET_LINK_ERR_IRQ 16 +#define SPACEWIRE_IOCTRL_SET_EVENT_ID 17 +#define SPACEWIRE_IOCTRL_SET_PACKETSIZE 20 +#define SPACEWIRE_IOCTRL_GET_LINK_STATUS 23 +#define SPACEWIRE_IOCTRL_GET_CONFIG 25 +#define SPACEWIRE_IOCTRL_GET_STATISTICS 26 +#define SPACEWIRE_IOCTRL_CLR_STATISTICS 27 +#define SPACEWIRE_IOCTRL_SEND 28 +#define SPACEWIRE_IOCTRL_LINKDISABLE 29 +#define SPACEWIRE_IOCTRL_LINKSTART 30 +#define SPACEWIRE_IOCTRL_SET_TXBLOCK_ON_FULL 31 +#define SPACEWIRE_IOCTRL_SET_COREFREQ 32 +#define SPACEWIRE_IOCTRL_SET_CLKDIVSTART 33 +#define SPACEWIRE_IOCTRL_SET_NODEMASK 34 +#define SPACEWIRE_IOCTRL_SET_KEEP_SOURCE 35 +#define SPACEWIRE_IOCTRL_SET_TCODE_CTRL 36 +#define SPACEWIRE_IOCTRL_SET_TCODE 37 +#define SPACEWIRE_IOCTRL_GET_TCODE 38 +#define SPACEWIRE_IOCTRL_SET_READ_TIMEOUT 39 + +#define SPACEWIRE_IOCTRL_START 64 +#define SPACEWIRE_IOCTRL_STOP 65 + +/* Defines what register bits that will be touched + * for SPACEWIRE_IOCTRL_SET_TCODE_CTRL + */ +#define SPACEWIRE_TCODE_CTRL_IE_MSK 0x001 +#define SPACEWIRE_TCODE_CTRL_TT_MSK 0x004 +#define SPACEWIRE_TCODE_CTRL_TR_MSK 0x008 + +/* Defines what register bits that should be set + * for SPACEWIRE_IOCTRL_SET_TCODE_CTRL + */ +#define SPACEWIRE_TCODE_CTRL_IE 0x100 +#define SPACEWIRE_TCODE_CTRL_TT 0x400 +#define SPACEWIRE_TCODE_CTRL_TR 0x800 + +/* SPACEWIRE_IOCTRL_SET_TCODE argument mask */ +#define SPACEWIRE_TCODE_TCODE 0x0ff +#define SPACEWIRE_TCODE_SET 0x100 /* Set Timecode register */ +#define SPACEWIRE_TCODE_TX 0x400 + +void grspw_register_drv (void); + +void grspw_print(int options); + +/* Global GRSPW Function pointer called upon timecode receive interrupt */ +extern void (*grspw_timecode_callback) + (void *pDev, void *regs, int minor, unsigned int tc); + + +#ifdef __cplusplus +} +#endif + +#endif /* __GRSPW_H__ */ diff --git a/bsps/sparc/include/bsp/grspw_pkt.h b/bsps/sparc/include/bsp/grspw_pkt.h new file mode 100644 index 0000000000..a74a7c9f6a --- /dev/null +++ b/bsps/sparc/include/bsp/grspw_pkt.h @@ -0,0 +1,845 @@ +/* + * GRSPW/GRSPW2 SpaceWire Kernel Library Interface + * + * COPYRIGHT (c) 2011 + * Cobham Gaisler AB + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRSPW_PKT_H__ +#define __GRSPW_PKT_H__ + +struct grspw_pkt; + +/* Maximum number of GRSPW devices supported by driver */ +#define GRSPW_MAX 32 + +/* Weak overridable variable the user can use to define the worker-task + * priority (0..255) or to disable (-1) the creation of the worker-task + * and the message queue to save space */ +extern int grspw_work_task_priority; + +#ifndef GRSPW_PKT_FLAGS +#define GRSPW_PKT_FLAGS +/*** TX Packet flags ***/ + +/* Enable IRQ generation */ +#define TXPKT_FLAG_IE 0x0040 + +/* Enable Header CRC generation (if CRC is available in HW) + * Header CRC will be appended (one byte at end of header) + */ +#define TXPKT_FLAG_HCRC 0x0100 + +/* Enable Data CRC generation (if CRC is available in HW) + * Data CRC will be appended (one byte at end of packet) + */ +#define TXPKT_FLAG_DCRC 0x0200 + +/* Control how many bytes the beginning of the Header + * the CRC should not be calculated for */ +#define TXPKT_FLAG_NOCRC_MASK 0x0000000f +#define TXPKT_FLAG_NOCRC_LEN0 0x00000000 +#define TXPKT_FLAG_NOCRC_LEN1 0x00000001 +#define TXPKT_FLAG_NOCRC_LEN2 0x00000002 +#define TXPKT_FLAG_NOCRC_LEN3 0x00000003 +#define TXPKT_FLAG_NOCRC_LEN4 0x00000004 +#define TXPKT_FLAG_NOCRC_LEN5 0x00000005 +#define TXPKT_FLAG_NOCRC_LEN6 0x00000006 +#define TXPKT_FLAG_NOCRC_LEN7 0x00000007 +#define TXPKT_FLAG_NOCRC_LEN8 0x00000008 +#define TXPKT_FLAG_NOCRC_LEN9 0x00000009 +#define TXPKT_FLAG_NOCRC_LENa 0x0000000a +#define TXPKT_FLAG_NOCRC_LENb 0x0000000b +#define TXPKT_FLAG_NOCRC_LENc 0x0000000c +#define TXPKT_FLAG_NOCRC_LENd 0x0000000d +#define TXPKT_FLAG_NOCRC_LENe 0x0000000e +#define TXPKT_FLAG_NOCRC_LENf 0x0000000f + +#define TXPKT_FLAG_INPUT_MASK (TXPKT_FLAG_NOCRC_MASK | TXPKT_FLAG_IE | \ + TXPKT_FLAG_HCRC | TXPKT_FLAG_DCRC) + +/* Marks if packet was transmitted or not */ +#define TXPKT_FLAG_TX 0x4000 + +/* Link Error */ +#define TXPKT_FLAG_LINKERR 0x8000 + +#define TXPKT_FLAG_OUTPUT_MASK (TXPKT_FLAG_TX | TXPKT_FLAG_LINKERR) + +/*** RX Packet Flags ***/ + +/* Enable IRQ generation */ +#define RXPKT_FLAG_IE 0x0010 + +#define RXPKT_FLAG_INPUT_MASK (RXPKT_FLAG_IE) + +/* Packet was truncated */ +#define RXPKT_FLAG_TRUNK 0x0800 +/* Data CRC error (only valid if RMAP CRC is enabled) */ +#define RXPKT_FLAG_DCRC 0x0400 +/* Header CRC error (only valid if RMAP CRC is enabled) */ +#define RXPKT_FLAG_HCRC 0x0200 +/* Error in End-of-Packet */ +#define RXPKT_FLAG_EEOP 0x0100 +/* Marks if packet was recevied or not */ +#define RXPKT_FLAG_RX 0x8000 + +#define RXPKT_FLAG_OUTPUT_MASK (RXPKT_FLAG_TRUNK | RXPKT_FLAG_DCRC | \ + RXPKT_FLAG_HCRC | RXPKT_FLAG_EEOP) + +/*** General packet flag options ***/ + +/* Translate Hdr and/or Payload address */ +#define PKT_FLAG_TR_DATA 0x1000 +#define PKT_FLAG_TR_HDR 0x2000 +/* All General options */ +#define PKT_FLAG_MASK 0x3000 + +#endif +/* GRSPW RX/TX Packet structure. + * + * - For RX the 'hdr' and 'hlen' fields are not used, they are not written + * by driver. + * + * - The 'pkt_id' field is untouched by driver, it is intended for packet + * numbering or user-custom data. + * + * - The last packet in a list must have 'next' set to NULL. + * + * - data and hdr pointers are written without modification to hardware, + * this means that caller must do address translation to hardware + * address itself. + * + * - the 'flags' field are interpreted differently depending on transfer + * type (RX/TX). See XXPKT_FLAG_* options above. + */ +struct grspw_pkt { + struct grspw_pkt *next; /* Next packet in list. NULL if last packet */ + unsigned int pkt_id; /* User assigned ID (not touched by driver) */ + unsigned short flags; /* RX/TX Options and status */ + unsigned char reserved; /* Reserved, must be zero */ + unsigned char hlen; /* Length of Header Buffer (only TX) */ + unsigned int dlen; /* Length of Data Buffer */ + void *data; /* 4-byte or byte aligned depends on HW */ + void *hdr; /* 4-byte or byte aligned depends on HW (only TX) */ +}; + +/* GRSPW SpaceWire Packet List */ +struct grspw_list { + struct grspw_pkt *head; + struct grspw_pkt *tail; +}; + +/* SpaceWire Link State */ +typedef enum { + SPW_LS_ERRRST = 0, + SPW_LS_ERRWAIT = 1, + SPW_LS_READY = 2, + SPW_LS_CONNECTING = 3, + SPW_LS_STARTED = 4, + SPW_LS_RUN = 5 +} spw_link_state_t; + +/* Address Configuration */ +struct grspw_addr_config { + /* Ignore address field and put all received packets to first + * DMA channel. + */ + int promiscuous; + + /* Default Node Address and Mask */ + unsigned char def_addr; + unsigned char def_mask; + /* DMA Channel custom Node Address and Mask */ + struct { + char node_en; /* Enable Separate Addr */ + unsigned char node_addr; /* Node address */ + unsigned char node_mask; /* Node address mask */ + } dma_nacfg[4]; +}; + +/* Hardware Support in GRSPW Core */ +struct grspw_hw_sup { + char rmap; /* If RMAP in HW is available */ + char rmap_crc; /* If RMAP CRC is available */ + char rx_unalign; /* RX unaligned (byte boundary) access allowed*/ + char nports; /* Number of Ports (1 or 2) */ + char ndma_chans; /* Number of DMA Channels (1..4) */ + char strip_adr; /* Hardware can strip ADR from packet data */ + char strip_pid; /* Hardware can strip PID from packet data */ + int hw_version; /* GRSPW Hardware Version */ + char reserved[2]; + char irq; /* SpW Distributed Interrupt available if 1 */ + char irq_num; /* Number of interrupts that can be generated */ + char itmr_width; /* SpW Intr. ISR timers bit width. 0=no timer */ +}; + +struct grspw_core_stats { + int irq_cnt; + int err_credit; + int err_eeop; + int err_addr; + int err_parity; + int err_disconnect; + int err_escape; + int err_wsync; /* only in GRSPW1 */ +}; + +/* grspw_link_ctrl() options */ +#define LINKOPTS_ENABLE 0x0000 +#define LINKOPTS_DISABLE 0x0001 +#define LINKOPTS_START 0x0002 +#define LINKOPTS_AUTOSTART 0x0004 +#define LINKOPTS_DIS_ONERR 0x0008 /* Disable DMA transmitter on link error + * Controls LE bit in DMACTRL register. + */ +#define LINKOPTS_DIS_ON_CE 0x0020000/* Disable Link on Credit error */ +#define LINKOPTS_DIS_ON_ER 0x0040000/* Disable Link on Escape error */ +#define LINKOPTS_DIS_ON_DE 0x0080000/* Disable Link on Disconnect error */ +#define LINKOPTS_DIS_ON_PE 0x0100000/* Disable Link on Parity error */ +#define LINKOPTS_DIS_ON_WE 0x0400000/* Disable Link on write synchonization + * error (GRSPW1 only) + */ +#define LINKOPTS_DIS_ON_EE 0x1000000/* Disable Link on Early EOP/EEP error*/ + +/*#define LINKOPTS_TICK_OUT_IRQ 0x0100*//* Enable Tick-out IRQ */ +#define LINKOPTS_EIRQ 0x0200 /* Enable Error Link IRQ */ + +#define LINKOPTS_MASK 0x15e020f/* All above options */ +#define LINKOPTS_MASK_DIS_ON 0x15e0000/* All disable link on error options + * On a certain error the link disable + * bit will be written and the work + * task will call dma_stop() for all + * channels. + */ + +#define LINKSTS_CE 0x002 /* Credit error */ +#define LINKSTS_ER 0x004 /* Escape error */ +#define LINKSTS_DE 0x008 /* Disconnect error */ +#define LINKSTS_PE 0x010 /* Parity error */ +#define LINKSTS_WE 0x040 /* Write synchonization error (GRSPW1 only) */ +#define LINKSTS_IA 0x080 /* Invalid address */ +#define LINKSTS_EE 0x100 /* Early EOP/EEP */ +#define LINKSTS_MASK 0x1de + +/* grspw_tc_ctrl() options */ +#define TCOPTS_EN_RXIRQ 0x0001 /* Tick-Out IRQ */ +#define TCOPTS_EN_TX 0x0004 +#define TCOPTS_EN_RX 0x0008 + +/* grspw_ic_ctrl() options: + * Corresponds code duplicatingly to GRSPW_CTRL_XX_BIT defines + */ +#define ICOPTS_INTNUM (0x1f << 27) +#define ICOPTS_EN_SPWIRQ_ON_EE (1 << 24) +#define ICOPTS_EN_SPWIRQ_ON_IA (1 << 23) +#define ICOPTS_EN_PRIO (1 << 22) +#define ICOPTS_EN_TIMEOUTIRQ (1 << 20) +#define ICOPTS_EN_ACKIRQ (1 << 19) +#define ICOPTS_EN_TICKOUTIRQ (1 << 18) +#define ICOPTS_EN_RX (1 << 17) +#define ICOPTS_EN_TX (1 << 16) +#define ICOPTS_BASEIRQ (0x1f << 8) +#define ICOPTS_EN_FLAGFILTER (1 << 0) /* NOTE: Not in icctrl. CTRL.bit12 */ + +/* grspw_ic_rlisr() and grspw_ic_rlintack() */ +#define ICRELOAD_EN (1 << 31) +#define ICRELOAD_MASK 0x7fffffff + +/* grspw_rmap_ctrl() options */ +#define RMAPOPTS_EN_RMAP 0x0001 +#define RMAPOPTS_EN_BUF 0x0002 + +/* grspw_dma_config.flags options */ +#define DMAFLAG_NO_SPILL 0x0001 /* See HW doc DMA-CTRL NS bit */ +#define DMAFLAG_RESV1 0x0002 /* HAS NO EFFECT */ +#define DMAFLAG_STRIP_ADR 0x0004 /* See HW doc DMA-CTRL SA bit */ +#define DMAFLAG_STRIP_PID 0x0008 /* See HW doc DMA-CTRL SP bit */ +#define DMAFLAG_RESV2 0x0010 /* HAS NO EFFECT */ +#define DMAFLAG_MASK (DMAFLAG_NO_SPILL|DMAFLAG_STRIP_ADR|DMAFLAG_STRIP_PID) +/* grspw_dma_config.flags misc options (not shifted internally) */ +#define DMAFLAG2_TXIE 0x00100000 /* See HW doc DMA-CTRL TI bit. + * Used to enable TX DMA interrupt + * when tx_irq_en_cnt=0. + */ +#define DMAFLAG2_RXIE 0x00200000 /* See HW doc DMA-CTRL RI bit. + * Used to enable RX DMA interrupt + * when rx_irq_en_cnt=0. + */ +/* Defines how the ISR will disable RX/TX DMA interrupt source when a DMA RX/TX + * interrupt has happended. DMA Error Interrupt always disables both RX/TX DMA + * interrupt. By default both RX/TX IRQs are disabled when either a RX, TX or + * both RX/TX DMA interrupt has been requested. The work-task, custom + * application handler or custom ISR handler is responsible to re-enable + * DMA interrupts. + */ +#define DMAFLAG2_IRQD_SRC 0x01000000 /* Disable triggering RX/TX source */ +#define DMAFLAG2_IRQD_NONE 0x00c00000 /* Never disable RX/TX IRQ in ISR */ +#define DMAFLAG2_IRQD_BOTH 0x00000000 /* Always disable both RX/TX sources */ +#define DMAFLAG2_IRQD_MASK 0x01c00000 /* Mask of options */ +#define DMAFLAG2_IRQD_BIT 22 + +#define DMAFLAG2_MASK (DMAFLAG2_TXIE | DMAFLAG2_RXIE | DMAFLAG2_IRQD_MASK) + +struct grspw_dma_config { + int flags; /* DMA config flags, see DMAFLAG1&2_* options */ + int rxmaxlen; /* RX Max Packet Length */ + int rx_irq_en_cnt; /* Enable RX IRQ every cnt descriptors */ + int tx_irq_en_cnt; /* Enable TX IRQ every cnt descriptors */ +}; + +/* Statistics per DMA channel */ +struct grspw_dma_stats { + /* IRQ Statistics */ + int irq_cnt; /* Number of DMA IRQs generated by channel */ + + /* Descriptor Statistics */ + int tx_pkts; /* Number of Transmitted packets */ + int tx_err_link; /* Number of Transmitted packets with Link Error*/ + int rx_pkts; /* Number of Received packets */ + int rx_err_trunk; /* Number of Received Truncated packets */ + int rx_err_endpkt; /* Number of Received packets with bad ending */ + + /* Diagnostics to help developers sizing their number buffers to avoid + * out-of-buffers or other phenomenons. + */ + int send_cnt_min; /* Minimum number of packets in TX SEND Q */ + int send_cnt_max; /* Maximum number of packets in TX SEND Q */ + int tx_sched_cnt_min; /* Minimum number of packets in TX SCHED Q */ + int tx_sched_cnt_max; /* Maximum number of packets in TX SCHED Q */ + int sent_cnt_max; /* Maximum number of packets in TX SENT Q */ + int tx_work_cnt; /* Times the work thread processed TX BDs */ + int tx_work_enabled; /* No. RX BDs enabled by work thread */ + + int ready_cnt_min; /* Minimum number of packets in RX READY Q */ + int ready_cnt_max; /* Maximum number of packets in RX READY Q */ + int rx_sched_cnt_min; /* Minimum number of packets in RX SCHED Q */ + int rx_sched_cnt_max; /* Maximum number of packets in RX SCHED Q */ + int recv_cnt_max; /* Maximum number of packets in RX RECV Q */ + int rx_work_cnt; /* Times the work thread processed RX BDs */ + int rx_work_enabled; /* No. RX BDs enabled by work thread */ +}; + +/* ISR message sending call back. Compatible with rtems_message_queue_send(). + * The 'buf' parameter has a pointer to a WORK-TASK message defined by the + * WORK_* macros below. The message indicates what GRSPW device operations + * are pending, thus what caused the interrupt. + * + * \param data defined by grspw_work_config.msgisr_arg, default a rtems_id. + * \param buf Pointer to a 32-bit message word + * \param n Always 4 (byte size of buf). + */ +typedef int (*grspw_msgqisr_t)(void *data, unsigned int *buf, unsigned int n); + +/* Work message definitions, the int sent to *buf + * Bits 31..24: reserved. + * Bits 23..16: GRSPW device number message is associated with. + * Bit 15: reserved. + * Bit 14: work-task shall delete message queue on exit. + * Bit 13: work-task shall exit and delete itself. + * Bit 12: link error - shut down all DMA operations (stop DMA channels). + * Bit 11..8: Indicats DMA error on DMA channel 3..0. + * Bit 7..0: Indicats RX and/or TX packets completed on channel 3..0. + */ +#define WORK_NONE 0 +#define WORK_SHUTDOWN 0x1000 /* Signal shut down */ +#define WORK_QUIT_TASK 0x2000 /* Work task shall exit (delete itself) */ +#define WORK_FREE_MSGQ 0x4000 /* Delete MsgQ (valid when WORK_QUIT_TASK) */ +#define WORK_DMA(chan, rxtx) (((rxtx) & 0x3) << ((chan) * 2)) +#define WORK_DMA_TX(chan) WORK_DMA(chan, 1) +#define WORK_DMA_RX(chan) WORK_DMA(chan, 2) +#define WORK_DMA_ER(chan) (0x1 << ((chan) + 8)) +#define WORK_DMA_MASK 0xfff /* max 4 channels all work */ +#define WORK_DMA_TX_MASK 0x055 /* max 4 channels TX work */ +#define WORK_DMA_RX_MASK 0x0aa /* max 4 channels RX work */ +#define WORK_DMA_ER_MASK 0xf00 /* max 4 channels Error work */ +#define WORK_DMA_CHAN_MASK(chan) (WORK_DMA_ER(chan) | WORK_DMA(chan, 0x3)) +#define WORK_CORE_BIT 16 +#define WORK_CORE_MASK 0x00ff0000 +#define WORK_CORE(device) ((device) << WORK_CORE_BIT) + +/* Message Q used to send messages to work task */ +struct grspw_work_config { + grspw_msgqisr_t msgisr; + void *msgisr_arg; /* example: rtems_id to Msg Q */ +}; + +extern void grspw_initialize_user( + /* Callback every time a GRSPW device is found. Args: DeviceIndex */ + void *(*devfound)(int), + /* Callback every time a GRSPW device is removed. Args: + * int = DeviceIndex + * void* = Return Value from devfound() + */ + void (*devremove)(int,void*) + ); + +/* Creates a MsgQ (optional) and spawns a worker task associated with the + * message Q. The task can also be associated with a custom msgQ if *msgQ. + * is non-zero. + * + * \param prio Task priority, set to -1 for default. + * \param stack Task stack size, set to 0 for default. + * \param msgQ pMsgQ=NULL: illegal, + * pMsqQ==0: create new MsgQ with task and place in *pMsgQ, + * *pmsqQ!=0: pointer to MsgQ used for task. + * \param msgMax Maximum number of messages, set to 0 for default. + * \return 0 on failure, task id on success. + */ +extern rtems_id grspw_work_spawn(int prio, int stack, rtems_id *pMsgQ, int msgMax); + +/* Free task associated with message queue and optionally also the message + * queue itself. The message queue is deleted by the work task and is therefore + * delayed until it the work task resumes its execution. + */ +extern rtems_status_code grspw_work_free(rtems_id msgQ, int freeMsgQ); + +/* Configure a GRSPW device Work task and Message Q set up. + * This affects messages to: + * - DMA AHB error interrupt handling (mandatory) + * - Link status interrupt handling (optional) + * - RX DMA, defaults to common msgQ (configured per DMA channel) + */ +extern void grspw_work_cfg(void *d, struct grspw_work_config *wc); + +/* Work-task function, called only from the work task. The function is provided + * as a way for the user to create its own work tasks. + * The argument determines which message queue the task shall read its + * work jobs from. + * + * The messages are always 32-bit words and follows the format defined by the + * WORK_* macros above. + */ +extern void grspw_work_func(rtems_id msgQ); + +enum grspw_worktask_ev { + WORKTASK_EV_NONE = 0, + WORKTASK_EV_QUIT = 1, + WORKTASK_EV_SHUTDOWN = 2, + WORKTASK_EV_DMA_STOP = 3, +}; + +/* Weak function to let user override. Function called every time one of the + * events above is handled by the work-task. The message 'msg' is the current + * message being processed by the work-task. + * The user can for example add custom code to invoke on a DMA error, link + * error or monitor when the work-task exits after a call to grspw_work_free(). + */ +extern void grspw_work_event(enum grspw_worktask_ev ev, unsigned int msg); + +#ifdef RTEMS_SMP +/* Set ISR interrupt affinity. The LEON IRQCtrl requires that the cpumask shall + * always have one bit set. + */ +extern int grspw_isr_affinity(void *d, const cpu_set_t *cpus); +#endif + +extern int grspw_dev_count(void); +extern void *grspw_open(int dev_no); +extern int grspw_close(void *d); +extern void grspw_hw_support(void *d, struct grspw_hw_sup *hw); +extern void grspw_stats_read(void *d, struct grspw_core_stats *sts); +extern void grspw_stats_clr(void *d); + +/* Set and Read current node address configuration. The dma_nacfg[N] field + * represents the configuration for DMA Channel N. + * + * Set cfg->promiscous to -1 in order to only read current configuration. + */ +extern void grspw_addr_ctrl(void *d, struct grspw_addr_config *cfg); + +/*** Link Control interface ***/ +/* Read Link State */ +extern spw_link_state_t grspw_link_state(void *d); +/* options [in/out]: set to -1 to only read current config + * + * CLKDIV register contain: + * bits 7..0 : Clock Div RUN (only run-state) + * bits 15..8 : Clock Div During Startup (all link states except run-state) + */ +extern void grspw_link_ctrl(void *d, int *options, int *stscfg, int *clkdiv); +/* Read the current value of the status register */ +extern unsigned int grspw_link_status(void *d); +/* Clear bits in the status register */ +extern void grspw_link_status_clr(void *d, unsigned int clearmask); + +/*** Time Code Interface ***/ +/* Generate Tick-In (increment Time Counter, Send Time Code) */ +extern void grspw_tc_tx(void *d); +/* Control Timcode settings of core */ +extern void grspw_tc_ctrl(void *d, int *options); +/* Assign ISR Function to TimeCode RX IRQ */ +extern void grspw_tc_isr(void *d, void (*tcisr)(void *data, int tc), void *data); +/* Read/Write TCTRL and TIMECNT. Write if not -1, always read current value + * TCTRL = bits 7 and 6 + * TIMECNT = bits 5 to 0 + */ +extern void grspw_tc_time(void *d, int *time); + +/*** Interrupt-code Interface ***/ +struct spwpkt_ic_config { + unsigned int tomask; + unsigned int aamask; + unsigned int scaler; + unsigned int isr_reload; + unsigned int ack_reload; +}; +/* Function Interrupt-Code ISR callback prototype. Called when respective + * interrupt handling option has been enabled by grspw_ic_ctrl(), the + * arguments rxirq, rxack and intto are read from the registers of the + * GRSPW core read by the GRSPW ISR, they are individually valid only when + * repective handling been turned on. + * + * data - Custom data provided by user + * rxirq - Interrupt-Code Recevie register of the GRSPW core read by ISR + * (only defined if IQ bit enabled through grspw_ic_ctrl()) + * rxack - Interrupt-Ack-Code Recevie register of the GRSPW core read by ISR + * (only defined if AQ bit enabled through grspw_ic_ctrl()) + * intto - Interrupt Tick-out Recevie register of the GRSPW core read by ISR + * (only defined if TQ bit enabled through grspw_ic_ctrl()) + */ +typedef void (*spwpkt_ic_isr_t)(void *data, unsigned int rxirq, + unsigned int rxack, unsigned int intto); +/* Control Interrupt-code settings of core + * Write if 'options' not pointing to -1, always read current value + */ +extern void grspw_ic_ctrl(void *d, unsigned int *options); +/* Write (rw&1 == 1) configuration parameters to registers and/or, + * Read (rw&2 == 1) configuration parameters from registers, in that sequence. + */ +extern void grspw_ic_config(void *d, int rw, struct spwpkt_ic_config *cfg); +/* Read or Write Interrupt-code status registers. + * If pointer argument *ptr == 0 then only read, if *ptr != 0 then only write. + * If *ptr is NULL no operation. + */ +extern void grspw_ic_sts(void *d, unsigned int *rxirq, unsigned int *rxack, + unsigned int *intto); +/* Generate Tick-In for the given Interrupt-code + * Returns zero on success and non-zero on failure + * + * Interrupt code bits (ic): + * Bit 5 - ACK if 1 + * Bits 4-0 Interrupt-code number + */ +extern int grspw_ic_tickin(void *d, int ic); +/* Assign handler function to Interrupt-code timeout IRQ */ +extern void grspw_ic_isr(void *d, spwpkt_ic_isr_t handler, void *data); + +/*** RMAP Control Interface ***/ +/* Set (not -1) and/or read RMAP options. */ +extern int grspw_rmap_ctrl(void *d, int *options, int *dstkey); +extern void grspw_rmap_support(void *d, char *rmap, char *rmap_crc); + +/*** SpW Port Control Interface ***/ + +/* Select port, if + * -1=The current selected port is returned + * 0=Port 0 + * 1=Port 1 + * Other positive values=Both Port0 and Port1 + */ +extern int grspw_port_ctrl(void *d, int *port); +/* Returns Number ports available in hardware */ +extern int grspw_port_count(void *d); +/* Returns the current active port */ +extern int grspw_port_active(void *d); + +/*** DMA Interface ***/ +extern void *grspw_dma_open(void *d, int chan_no); +extern int grspw_dma_close(void *c); + +extern int grspw_dma_start(void *c); +extern void grspw_dma_stop(void *c); + +/* Enable interrupt manually */ +extern unsigned int grspw_dma_enable_int(void *c, int rxtx, int force); + +/* Return Current DMA Control & Status Register */ +extern unsigned int grspw_dma_ctrlsts(void *c); + +/* Schedule List of packets for transmission at some point in + * future. + * + * 1. Move transmitted packets to SENT List (SCHED->SENT) + * 2. Add the requested packets to the SEND List (USER->SEND) + * 3. Schedule as many packets as possible for transmission (SEND->SCHED) + * + * Call this function with pkts=NULL to just do step 1 and 3. This may be + * required in Polling-mode. + * + * The above steps 1 and 3 may be skipped by setting 'opts': + * bit0 = 1: Skip Step 1. + * bit1 = 1: Skip Step 3. + * Skipping both step 1 and 3 may be usefull when IRQ is enabled, then + * the work queue will be totaly responsible for handling descriptors. + * + * The fastest solution in retreiving sent TX packets and sending new frames + * is to call: + * A. grspw_dma_tx_reclaim(opts=0) + * B. grspw_dma_tx_send(opts=1) + * + * NOTE: the TXPKT_FLAG_TX flag must not be set. + * + * Return Code + * -1 Error + * 0 Successfully added pkts to send/sched list + * 1 DMA stopped. No operation. + */ +extern int grspw_dma_tx_send(void *c, int opts, struct grspw_list *pkts, int count); + +/* Reclaim TX packet buffers that has previously been scheduled for transmission + * with grspw_dma_tx_send(). + * + * 1. Move transmitted packets to SENT List (SCHED->SENT) + * 2. Move all SENT List to pkts list (SENT->USER) + * 3. Schedule as many packets as possible for transmission (SEND->SCHED) + * + * The above steps 1 may be skipped by setting 'opts': + * bit0 = 1: Skip Step 1. + * bit1 = 1: Skip Step 3. + * + * The fastest solution in retreiving sent TX packets and sending new frames + * is to call: + * A. grspw_dma_tx_reclaim(opts=2) (Skip step 3) + * B. grspw_dma_tx_send(opts=1) (Skip step 1) + * + * Return Code + * -1 Error + * 0 Successful. pkts list filled with all packets from sent list + * 1 Same as 0, but indicates that DMA stopped + */ +extern int grspw_dma_tx_reclaim(void *c, int opts, struct grspw_list *pkts, int *count); + +/* Get current number of Packets in respective TX Queue. */ +extern void grspw_dma_tx_count(void *c, int *send, int *sched, int *sent, int *hw); + +#define GRSPW_OP_AND 0 +#define GRSPW_OP_OR 1 +/* Block until send_cnt or fewer packets are Queued in "Send and Scheduled" Q, + * op (AND or OR), sent_cnt or more packet "have been sent" (Sent Q) condition + * is met. + * If a link error occurs and the Stop on Link error is defined, this function + * will also return to caller. + * The timeout argument is used to return after timeout ticks, regardless of + * the other conditions. If timeout is zero, the function will wait forever + * until the condition is satisfied. + * + * NOTE: if IRQ of TX descriptors are not enabled conditions are never + * checked, this may hang infinitely unless a timeout has been specified + * + * Return Code + * -1 Error + * 0 Returing to caller because specified conditions are now fullfilled + * 1 DMA stopped + * 2 Timeout, conditions are not met + * 3 Another task is already waiting. Service is Busy. + */ +extern int grspw_dma_tx_wait(void *c, int send_cnt, int op, int sent_cnt, int timeout); + +/* Get received RX packet buffers that has previously been scheduled for + * reception with grspw_dma_rx_prepare(). + * + * 1. Move Scheduled packets to RECV List (SCHED->RECV) + * 2. Move all RECV packet to the callers list (RECV->USER) + * 3. Schedule as many free packet buffers as possible (READY->SCHED) + * + * The above steps 1 may be skipped by setting 'opts': + * bit0 = 1: Skip Step 1. + * bit1 = 1: Skip Step 3. + * + * The fastest solution in retreiving received RX packets and preparing new + * packet buffers for future receive, is to call: + * A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3) + * B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1) + * + * Return Code + * -1 Error + * 0 Successfully filled pkts list with packets from recv list. + * 1 DMA stopped + */ +extern int grspw_dma_rx_recv(void *c, int opts, struct grspw_list *pkts, int *count); + +/* Add more RX packet buffers for future for reception. The received packets + * can later be read out with grspw_dma_rx_recv(). + * + * 1. Move Received packets to RECV List (SCHED->RECV) + * 2. Add the "free/ready" packet buffers to the READY List (USER->READY) + * 3. Schedule as many packets as possible (READY->SCHED) + * + * The above steps 1 may be skipped by setting 'opts': + * bit0 = 1: Skip Step 1. + * bit1 = 1: Skip Step 3. + * + * The fastest solution in retreiving received RX packets and preparing new + * packet buffers for future receive, is to call: + * A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3) + * B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1) + * + * Return Code + * -1 Error + * 0 Successfully added packet buffers from pkt list into the ready queue + * 1 DMA stopped + */ +extern int grspw_dma_rx_prepare(void *c, int opts, struct grspw_list *pkts, int count); + +/* Get current number of Packets in respective RX Queue. */ +extern void grspw_dma_rx_count(void *c, int *ready, int *sched, int *recv, int *hw); + +/* Block until recv_cnt or more packets are Queued in RECV Q, op (AND or OR), + * ready_cnt or fewer packet buffers are available in the "READY and Scheduled" Q, + * condition is met. + * If a link error occurs and the Stop on Link error is defined, this function + * will also return to caller, however with an error. + * The timeout argument is used to return after timeout ticks, regardless of + * the other conditions. If timeout is zero, the function will wait forever + * until the condition is satisfied. + * + * NOTE: if IRQ of RX descriptors are not enabled conditions are never + * checked, this may hang infinitely unless a timeout has been specified + * + * Return Code + * -1 Error + * 0 Returing to caller because specified conditions are now fullfilled + * 1 DMA stopped + * 2 Timeout, conditions are not met + * 3 Another task is already waiting. Service is Busy. + */ +extern int grspw_dma_rx_wait(void *c, int recv_cnt, int op, int ready_cnt, int timeout); + +extern int grspw_dma_config(void *c, struct grspw_dma_config *cfg); +extern void grspw_dma_config_read(void *c, struct grspw_dma_config *cfg); + +extern void grspw_dma_stats_read(void *c, struct grspw_dma_stats *sts); +extern void grspw_dma_stats_clr(void *c); + +/* Register GRSPW packet driver to Driver Manager */ +void grspw2_register_drv (void); + +/*** GRSPW SpaceWire Packet List Handling Routines ***/ + +static inline void grspw_list_clr(struct grspw_list *list) +{ + list->head = NULL; + list->tail = NULL; +} + +static inline int grspw_list_is_empty(struct grspw_list *list) +{ + return (list->head == NULL); +} + +/* Return Number of entries in list */ +static inline int grspw_list_cnt(struct grspw_list *list) +{ + struct grspw_pkt *lastpkt = NULL, *pkt = list->head; + int cnt = 0; + while ( pkt ) { + cnt++; + lastpkt = pkt; + pkt = pkt->next; + } + if ( lastpkt && (list->tail != lastpkt) ) + return -1; + return cnt; +} + +static inline void +grspw_list_append(struct grspw_list *list, struct grspw_pkt *pkt) +{ + pkt->next = NULL; + if ( list->tail == NULL ) { + list->head = pkt; + } else { + list->tail->next = pkt; + } + list->tail = pkt; +} + +static inline void +grspw_list_prepend(struct grspw_list *list, struct grspw_pkt *pkt) +{ + pkt->next = list->head; + if ( list->head == NULL ) { + list->tail = pkt; + } + list->head = pkt; +} + +static inline void +grspw_list_append_list(struct grspw_list *list, struct grspw_list *alist) +{ + if (grspw_list_is_empty(alist)) { + return; + } + alist->tail->next = NULL; + if ( list->tail == NULL ) { + list->head = alist->head; + } else { + list->tail->next = alist->head; + } + list->tail = alist->tail; +} + +static inline void +grspw_list_prepend_list(struct grspw_list *list, struct grspw_list *alist) +{ + if (grspw_list_is_empty(alist)) { + return; + } + if ( list->head == NULL ) { + list->tail = alist->tail; + alist->tail->next = NULL; + } else { + alist->tail->next = list->head; + } + list->head = alist->head; +} + +/* Remove dlist (delete-list) from head of list */ +static inline void +grspw_list_remove_head_list(struct grspw_list *list, struct grspw_list *dlist) +{ + if (grspw_list_is_empty(dlist)) { + return; + } + list->head = dlist->tail->next; + if ( list->head == NULL ) { + list->tail = NULL; + } + dlist->tail->next = NULL; +} + +/* Take A number of entries from head of list 'list' and put the entires + * to rlist (result list). + */ +static inline int +grspw_list_take_head_list(struct grspw_list *list, struct grspw_list *rlist, int max) +{ + int cnt; + struct grspw_pkt *pkt, *last; + + pkt = list->head; + + if ( (max < 1) || (pkt == NULL) ) { + grspw_list_clr(rlist); + return 0; + } + + cnt = 0; + rlist->head = pkt; + last = pkt; + while ((cnt < max) && pkt) { + last = pkt; + pkt = pkt->next; + cnt++; + } + rlist->tail = last; + grspw_list_remove_head_list(list, rlist); + return cnt; +} + +#endif diff --git a/bsps/sparc/include/bsp/grspw_router.h b/bsps/sparc/include/bsp/grspw_router.h new file mode 100644 index 0000000000..2fab8d5f6c --- /dev/null +++ b/bsps/sparc/include/bsp/grspw_router.h @@ -0,0 +1,505 @@ +/* + * GRSPW ROUTER APB-Register Driver. + * + * COPYRIGHT (c) 2010-2017. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRSPW_ROUTER_H__ +#define __GRSPW_ROUTER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Maximum number of ROUTER devices supported by driver */ +#define ROUTER_MAX 2 + +#define ROUTER_ERR_OK 0 +#define ROUTER_ERR_EINVAL -1 +#define ROUTER_ERR_ERROR -2 +#define ROUTER_ERR_TOOMANY -3 +#define ROUTER_ERR_IMPLEMENTED -4 + +/* Hardware Information */ +struct router_hw_info { + uint8_t nports_spw; + uint8_t nports_amba; + uint8_t nports_fifo; + int8_t srouting; + int8_t pnp_enable; + int8_t timers_avail; + int8_t pnp_avail; + uint8_t ver_major; + uint8_t ver_minor; + uint8_t ver_patch; + uint8_t iid; + + /* Router capabilities */ + uint8_t amba_port_fifo_size; + uint8_t spw_port_fifo_size; + uint8_t rmap_maxdlen; + int8_t aux_async; + int8_t aux_dist_int_support; + int8_t dual_port_support; + int8_t dist_int_support; + int8_t spwd_support; + uint8_t pktcnt_support; + uint8_t charcnt_support; +}; + +#define ROUTER_FLG_CFG 0x01 +#define ROUTER_FLG_IID 0x02 +#define ROUTER_FLG_IDIV 0x04 +#define ROUTER_FLG_TPRES 0x08 +#define ROUTER_FLG_TRLD 0x10 +#define ROUTER_FLG_ALL 0x1f /* All Above Flags */ + +struct router_config { + uint32_t flags; /* Determine what configuration should be updated */ + + /* Router Configuration Register */ + uint32_t config; + + /* Set Instance ID */ + uint8_t iid; + + /* SpaceWire Link Initialization Clock Divisor */ + uint8_t idiv; + + /* Timer Prescaler */ + uint32_t timer_prescaler; +}; + +/* Routing table address control */ +struct router_route_acontrol { + uint32_t control[31]; + uint32_t control_logical[224]; +}; + +/* Routing table port mapping */ +struct router_route_portmap { + uint32_t pmap[31]; /* Port Setup for ports 1-31 */ + uint32_t pmap_logical[224]; /* Port setup for locgical addresses 32-255 */ +}; + +/* Routing table */ +#define ROUTER_ROUTE_FLG_MAP 0x01 +#define ROUTER_ROUTE_FLG_CTRL 0x02 +#define ROUTER_ROUTE_FLG_ALL 0x3 /* All Above Flags */ +struct router_routing_table { + uint32_t flags; /* Determine what configuration should be updated */ + + struct router_route_acontrol acontrol; + struct router_route_portmap portmap; +}; + +/* Set/Get Port Control/Status */ +#define ROUTER_PORT_FLG_SET_CTRL 0x01 +#define ROUTER_PORT_FLG_GET_CTRL 0x02 +#define ROUTER_PORT_FLG_SET_STS 0x04 +#define ROUTER_PORT_FLG_GET_STS 0x08 +#define ROUTER_PORT_FLG_SET_CTRL2 0x10 +#define ROUTER_PORT_FLG_GET_CTRL2 0x20 +#define ROUTER_PORT_FLG_SET_TIMER 0x40 +#define ROUTER_PORT_FLG_GET_TIMER 0x80 +#define ROUTER_PORT_FLG_SET_PKTLEN 0x100 +#define ROUTER_PORT_FLG_GET_PKTLEN 0x200 +struct router_port { + uint32_t flag; + /* Port control */ + uint32_t ctrl; + /* Port status */ + uint32_t sts; + /* Port control 2 */ + uint32_t ctrl2; + /* Timer Reload */ + uint32_t timer_reload; + /* Maximum packet length */ + uint32_t packet_length; +}; + +/* Register GRSPW Router driver to Driver Manager */ +void router_register_drv(void); + +extern void *router_open(unsigned int dev_no); +extern int router_close(void *d); +extern int router_print(void *d); +extern int router_hwinfo_get(void *d, struct router_hw_info *hwinfo); + +/* Router general config */ +extern int router_config_set(void *d, struct router_config *cfg); +extern int router_config_get(void *d, struct router_config *cfg); + +/* Routing table config */ +extern int router_routing_table_set(void *d, + struct router_routing_table *cfg); +extern int router_routing_table_get(void *d, + struct router_routing_table *cfg); + +/* + * ROUTER PCTRL register fields + */ +#define PCTRL_RD (0xff << PCTRL_RD_BIT) +#define PCTRL_ST (0x1 << PCTRL_ST_BIT) +#define PCTRL_SR (0x1 << PCTRL_SR_BIT) +#define PCTRL_AD (0x1 << PCTRL_AD_BIT) +#define PCTRL_LR (0x1 << PCTRL_LR_BIT) +#define PCTRL_PL (0x1 << PCTRL_PL_BIT) +#define PCTRL_TS (0x1 << PCTRL_TS_BIT) +#define PCTRL_IC (0x1 << PCTRL_IC_BIT) +#define PCTRL_ET (0x1 << PCTRL_ET_BIT) +#define PCTRL_NP (0x1 << PCTRL_NP_BIT) +#define PCTRL_PS (0x1 << PCTRL_PS_BIT) +#define PCTRL_BE (0x1 << PCTRL_BE_BIT) +#define PCTRL_DI (0x1 << PCTRL_DI_BIT) +#define PCTRL_TR (0x1 << PCTRL_TR_BIT) +#define PCTRL_PR (0x1 << PCTRL_PR_BIT) +#define PCTRL_TF (0x1 << PCTRL_TF_BIT) +#define PCTRL_RS (0x1 << PCTRL_RS_BIT) +#define PCTRL_TE (0x1 << PCTRL_TE_BIT) +#define PCTRL_CE (0x1 << PCTRL_CE_BIT) +#define PCTRL_AS (0x1 << PCTRL_AS_BIT) +#define PCTRL_LS (0x1 << PCTRL_LS_BIT) +#define PCTRL_LD (0x1 << PCTRL_LD_BIT) + +#define PCTRL_RD_BIT 24 +#define PCTRL_ST_BIT 21 +#define PCTRL_SR_BIT 20 +#define PCTRL_AD_BIT 19 +#define PCTRL_LR_BIT 18 +#define PCTRL_PL_BIT 17 +#define PCTRL_TS_BIT 16 +#define PCTRL_IC_BIT 15 +#define PCTRL_ET_BIT 14 +#define PCTRL_NP_BIT 13 +#define PCTRL_PS_BIT 12 +#define PCTRL_BE_BIT 11 +#define PCTRL_DI_BIT 10 +#define PCTRL_TR_BIT 9 +#define PCTRL_PR_BIT 8 +#define PCTRL_TF_BIT 7 +#define PCTRL_RS_BIT 6 +#define PCTRL_TE_BIT 5 +#define PCTRL_CE_BIT 3 +#define PCTRL_AS_BIT 2 +#define PCTRL_LS_BIT 1 +#define PCTRL_LD_BIT 0 + +/* + * ROUTER PCTRL2 register fields + */ +#define PCTRL2_SM (0xff << PCTRL2_SM_BIT) +#define PCTRL2_SV (0xff << PCTRL2_SV_BIT) +#define PCTRL2_OR (0x1 << PCTRL2_OR_BIT) +#define PCTRL2_UR (0x1 << PCTRL2_UR_BIT) +#define PCTRL2_AT (0x1 << PCTRL2_AT_BIT) +#define PCTRL2_AR (0x1 << PCTRL2_AR_BIT) +#define PCTRL2_IT (0x1 << PCTRL2_IT_BIT) +#define PCTRL2_IR (0x1 << PCTRL2_IR_BIT) +#define PCTRL2_SD (0x1f << PCTRL2_SD_BIT) +#define PCTRL2_SC (0x1f << PCTRL2_SC_BIT) + +#define PCTRL2_SM_BIT 24 +#define PCTRL2_SV_BIT 16 +#define PCTRL2_OR_BIT 15 +#define PCTRL2_UR_BIT 14 +#define PCTRL2_AT_BIT 12 +#define PCTRL2_AR_BIT 11 +#define PCTRL2_IT_BIT 10 +#define PCTRL2_IR_BIT 9 +#define PCTRL2_SD_BIT 1 +#define PCTRL2_SC_BIT 0 + +/* Router Set/Get Port configuration */ +extern int router_port_ioc(void *d, int port, struct router_port *cfg); + +/* Read-modify-write Port Control register */ +extern int router_port_ctrl_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value); +/* Read-modify-write Port Control2 register */ +extern int router_port_ctrl2_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value); +/* Read Port Control register */ +extern int router_port_ctrl_get(void *d, int port, uint32_t *ctrl); +/* Read Port Control2 register */ +extern int router_port_ctrl2_get(void *d, int port, uint32_t *ctrl2); +/* Write Port Control Register */ +extern int router_port_ctrl_set(void *d, int port, uint32_t mask, uint32_t ctrl); +/* Write Port Control2 Register */ +extern int router_port_ctrl2_set(void *d, int port, uint32_t mask, uint32_t ctrl2); +/* Set Timer Reload Value for a specific port */ +extern int router_port_treload_set(void *d, int port, uint32_t reload); +/* Get Timer Reload Value for a specific port */ +extern int router_port_treload_get(void *d, int port, uint32_t *reload); +/* Get Maximum packet length for a specific port */ +extern int router_port_maxplen_get(void *d, int port, uint32_t *length); +/* Set Maximum packet length for a specific port */ +extern int router_port_maxplen_set(void *d, int port, uint32_t length); + +/* + * ROUTER PSTSCFG register fields + */ +#define PSTSCFG_EO (0x1 << PSTSCFG_EO_BIT) +#define PSTSCFG_EE (0x1 << PSTSCFG_EE_BIT) +#define PSTSCFG_PL (0x1 << PSTSCFG_PL_BIT) +#define PSTSCFG_TT (0x1 << PSTSCFG_TT_BIT) +#define PSTSCFG_PT (0x1 << PSTSCFG_PT_BIT) +#define PSTSCFG_HC (0x1 << PSTSCFG_HC_BIT) +#define PSTSCFG_PI (0x1 << PSTSCFG_PI_BIT) +#define PSTSCFG_CE (0x1 << PSTSCFG_CE_BIT) +#define PSTSCFG_EC (0xf << PSTSCFG_EC_BIT) +#define PSTSCFG_TS (0x1 << PSTSCFG_TS_BIT) +#define PSTSCFG_ME (0x1 << PSTSCFG_ME_BIT) +#define PSTSCFG_IP (0x1f << PSTSCFG_IP_BIT) +#define PSTSCFG_CP (0x1 << PSTSCFG_CP_BIT) +#define PSTSCFG_PC (0xf << PSTSCFG_PC_BIT) +#define PSTSCFG_WCLEAR (PSTSCFG_EO | PSTSCFG_EE | PSTSCFG_PL | \ + PSTSCFG_TT | PSTSCFG_PT | PSTSCFG_HC | \ + PSTSCFG_PI | PSTSCFG_CE | PSTSCFG_TS | \ + PSTSCFG_ME | PSTSCFG_CP) +#define PSTSCFG_WCLEAR2 (PSTSCFG_CE | PSTSCFG_CP) + +#define PSTSCFG_EO_BIT 31 +#define PSTSCFG_EE_BIT 30 +#define PSTSCFG_PL_BIT 29 +#define PSTSCFG_TT_BIT 28 +#define PSTSCFG_PT_BIT 27 +#define PSTSCFG_HC_BIT 26 +#define PSTSCFG_PI_BIT 25 +#define PSTSCFG_CE_BIT 24 +#define PSTSCFG_EC_BIT 20 +#define PSTSCFG_TS_BIT 18 +#define PSTSCFG_ME_BIT 17 +#define PSTSCFG_IP_BIT 7 +#define PSTSCFG_CP_BIT 4 +#define PSTSCFG_PC_BIT 0 + +/* + * ROUTER PSTS register fields + */ +#define PSTS_PT (0x3 << PSTS_PT_BIT) +#define PSTS_PL (0x1 << PSTS_PL_BIT) +#define PSTS_TT (0x1 << PSTS_TT_BIT) +#define PSTS_RS (0x1 << PSTS_RS_BIT) +#define PSTS_SR (0x1 << PSTS_SR_BIT) +#define PSTS_LR (0x1 << PSTS_LR_BIT) +#define PSTS_SP (0x1 << PSTS_SP_BIT) +#define PSTS_AC (0x1 << PSTS_AC_BIT) +#define PSTS_TS (0x1 << PSTS_TS_BIT) +#define PSTS_ME (0x1 << PSTS_ME_BIT) +#define PSTS_TF (0x1 << PSTS_TF_BIT) +#define PSTS_RE (0x1 << PSTS_RE_BIT) +#define PSTS_LS (0x7 << PSTS_LS_BIT) +#define PSTS_IP (0x1f << PSTS_IP_BIT) +#define PSTS_PR (0x1 << PSTS_PR_BIT) +#define PSTS_PB (0x1 << PSTS_PB_BIT) +#define PSTS_IA (0x1 << PSTS_IA_BIT) +#define PSTS_CE (0x1 << PSTS_CE_BIT) +#define PSTS_ER (0x1 << PSTS_ER_BIT) +#define PSTS_DE (0x1 << PSTS_DE_BIT) +#define PSTS_PE (0x1 << PSTS_PE_BIT) +#define PSTS_WCLEAR (PSTS_PL | PSTS_TT | PSTS_RS | PSTS_SR | \ + PSTS_TS | PSTS_ME | PSTS_IA | PSTS_CE | \ + PSTS_ER | PSTS_DE | PSTS_PE) + +#define PSTS_PT_BIT 30 +#define PSTS_PL_BIT 29 +#define PSTS_TT_BIT 28 +#define PSTS_RS_BIT 27 +#define PSTS_SR_BIT 26 +#define PSTS_LR_BIT 22 +#define PSTS_SP_BIT 21 +#define PSTS_AC_BIT 20 +#define PSTS_TS_BIT 18 +#define PSTS_ME_BIT 17 +#define PSTS_TF_BIT 16 +#define PSTS_RE_BIT 15 +#define PSTS_LS_BIT 12 +#define PSTS_IP_BIT 7 +#define PSTS_PR_BIT 6 +#define PSTS_PB_BIT 5 +#define PSTS_IA_BIT 4 +#define PSTS_CE_BIT 3 +#define PSTS_ER_BIT 2 +#define PSTS_DE_BIT 1 +#define PSTS_PE_BIT 0 + +/* Check Port Status register and clear errors if there are */ +extern int router_port_status(void *d, int port, uint32_t *sts, uint32_t clrmsk); + +#define ROUTER_LINK_STATUS_ERROR_RESET 0 +#define ROUTER_LINK_STATUS_ERROR_WAIT 1 +#define ROUTER_LINK_STATUS_READY 2 +#define ROUTER_LINK_STATUS_STARTED 3 +#define ROUTER_LINK_STATUS_CONNECTING 4 +#define ROUTER_LINK_STATUS_RUN_STATE 5 +/* Get Link status */ +extern int router_port_link_status(void *d, int port); +/* Operate a Link */ +extern int router_port_enable(void *d, int port); +extern int router_port_disable(void *d, int port); +extern int router_port_link_stop(void *d, int port); +extern int router_port_link_start(void *d, int port); +extern int router_port_link_receive_spill(void *d, int port); +extern int router_port_link_transmit_reset(void *d, int port); + +/* Get port credit counter register */ +extern int router_port_cred_get(void *d, int port, uint32_t *cred); + +/* + * ROUTER RTACTRL register fields + */ +#define RTACTRL_SR (0x1 << RTACTRL_SR_BIT) +#define RTACTRL_EN (0x1 << RTACTRL_EN_BIT) +#define RTACTRL_PR (0x1 << RTACTRL_PR_BIT) +#define RTACTRL_HD (0x1 << RTACTRL_HD_BIT) + +#define RTACTRL_SR_BIT 3 +#define RTACTRL_EN_BIT 2 +#define RTACTRL_PR_BIT 1 +#define RTACTRL_HD_BIT 0 + +/* Individual route modification */ +#define ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE (0x1 << 16) +#define ROUTER_ROUTE_PACKETDISTRIBUTION_DISABLE (0x0 << 16) +#define ROUTER_ROUTE_SPILLIFNOTREADY_ENABLE RTACTRL_SR +#define ROUTER_ROUTE_SPILLIFNOTREADY_DISABLE 0 +#define ROUTER_ROUTE_ENABLE RTACTRL_EN +#define ROUTER_ROUTE_DISABLE 0 +#define ROUTER_ROUTE_PRIORITY_HIGH RTACTRL_PR +#define ROUTER_ROUTE_PRIORITY_LOW 0 +#define ROUTER_ROUTE_HEADERDELETION_ENABLE RTACTRL_HD +#define ROUTER_ROUTE_HEADERDELETION_DISABLE 0 +struct router_route { + uint8_t from_address; + uint8_t to_port[32]; + int count; + int options; +}; +extern int router_route_set(void *d, struct router_route *route); +extern int router_route_get(void *d, struct router_route *route); + +/* Router configuration port write enable */ +extern int router_write_enable(void *d); +extern int router_write_disable(void *d); + +/* Router reset */ +extern int router_reset(void *d); + +/* Set Instance ID */ +extern int router_instance_set(void *d, uint8_t iid); +/* Get Instance ID */ +extern int router_instance_get(void *d, uint8_t *iid); + +/* Set SpaceWire Link Initialization Clock Divisor */ +extern int router_idiv_set(void *d, uint8_t idiv); +/* Get SpaceWire Link Initialization Clock Divisor */ +extern int router_idiv_get(void *d, uint8_t *idiv); + +/* Set Timer Prescaler */ +extern int router_tpresc_set(void *d, uint32_t prescaler); +/* Get Timer Prescaler */ +extern int router_tpresc_get(void *d, uint32_t *prescaler); + +/* Set/get Router configuration */ +extern int router_cfgsts_set(void *d, uint32_t cfgsts); +extern int router_cfgsts_get(void *d, uint32_t *cfgsts); + +/* Router timecode */ +extern int router_tc_enable(void *d); +extern int router_tc_disable(void *d); +extern int router_tc_reset(void *d); +extern int router_tc_get(void *d); + +/* Router Interrupts */ +/* + * ROUTER IMASK register fields + */ +#define IMASK_PE (0x1 << IMASK_PE_BIT) +#define IMASK_SR (0x1 << IMASK_SR_BIT) +#define IMASK_RS (0x1 << IMASK_RS_BIT) +#define IMASK_TT (0x1 << IMASK_TT_BIT) +#define IMASK_PL (0x1 << IMASK_PL_BIT) +#define IMASK_TS (0x1 << IMASK_TS_BIT) +#define IMASK_AC (0x1 << IMASK_AC_BIT) +#define IMASK_RE (0x1 << IMASK_RE_BIT) +#define IMASK_IA (0x1 << IMASK_IA_BIT) +#define IMASK_LE (0x1 << IMASK_LE_BIT) +#define IMASK_ME (0x1 << IMASK_ME_BIT) +#define IMASK_ALL ( IMASK_PE | IMASK_SR | IMASK_RS | IMASK_TT \ + IMASK_PL | IMASK_TS | IMASK_AC | IMASK_RE | IMASK_IA \ + IMASK_LE | IMASK_ME) + +#define IMASK_PE_BIT 10 +#define IMASK_SR_BIT 9 +#define IMASK_RS_BIT 8 +#define IMASK_TT_BIT 7 +#define IMASK_PL_BIT 6 +#define IMASK_TS_BIT 5 +#define IMASK_AC_BIT 4 +#define IMASK_RE_BIT 3 +#define IMASK_IA_BIT 2 +#define IMASK_LE_BIT 1 +#define IMASK_ME_BIT 0 + +#define ROUTER_INTERRUPT_ALL IMASK_ALL +#define ROUTER_INTERRUPT_SPWPNP_ERROR IMASK_PE +#define ROUTER_INTERRUPT_SPILLED IMASK_SR +#define ROUTER_INTERRUPT_RUNSTATE IMASK_RS +#define ROUTER_INTERRUPT_TC_TRUNCATION IMASK_TT +#define ROUTER_INTERRUPT_PACKET_TRUNCATION IMASK_PL +#define ROUTER_INTERRUPT_TIMEOUT IMASK_TS +#define ROUTER_INTERRUPT_CFGPORT IMASK_AC +#define ROUTER_INTERRUPT_RMAP_ERROR IMASK_RE +#define ROUTER_INTERRUPT_INVALID_ADDRESS IMASK_IA +#define ROUTER_INTERRUPT_LINK_ERROR IMASK_LE +#define ROUTER_INTERRUPT_MEMORY_ERROR IMASK_ME +extern int router_port_interrupt_unmask(void *d, int port); +extern int router_port_interrupt_mask(void *d, int port); +extern int router_interrupt_unmask(void *d, int options); +extern int router_interrupt_mask(void *d, int options); + +/* Router Interrupt code generation */ +/* + * ROUTER ICODEGEN register fields + */ +#define ICODEGEN_UA (0x1 << ICODEGEN_UA_BIT) +#define ICODEGEN_AH (0x1 << ICODEGEN_AH_BIT) +#define ICODEGEN_IT (0x1 << ICODEGEN_IT_BIT) +#define ICODEGEN_TE (0x1 << ICODEGEN_TE_BIT) +#define ICODEGEN_EN (0x1 << ICODEGEN_EN_BIT) +#define ICODEGEN_IN (0x1f << ICODEGEN_IN_BIT) + +#define ICODEGEN_UA_BIT 20 +#define ICODEGEN_AH_BIT 19 +#define ICODEGEN_IT_BIT 18 +#define ICODEGEN_TE_BIT 17 +#define ICODEGEN_EN_BIT 16 +#define ICODEGEN_IN_BIT 0 + +#define ROUTER_ICODEGEN_ITYPE_EDGE ICODEGEN_IT +#define ROUTER_ICODEGEN_ITYPE_LEVEL 0 +#define ROUTER_ICODEGEN_AUTOUNACK_ENABLE ICODEGEN_UA +#define ROUTER_ICODEGEN_AUTOUNACK_DISABLE 0 +#define ROUTER_ICODEGEN_AUTOACK_ENABLE ICODEGEN_AH +#define ROUTER_ICODEGEN_AUTOACK_DISABLE 0 +extern int router_icodegen_enable(void *d, uint8_t intn, uint32_t aitimer, + int options); +extern int router_icodegen_disable(void *d); + +/* Router interrupt change timers */ +extern int router_isrctimer_set(void *d, uint32_t reloadvalue); +extern int router_isrctimer_get(void *d, uint32_t *reloadvalue); + +/* Router interrupt timers */ +extern int router_isrtimer_set(void *d, uint32_t reloadvalue); +extern int router_isrtimer_get(void *d, uint32_t *reloadvalue); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/grtc.h b/bsps/sparc/include/bsp/grtc.h new file mode 100644 index 0000000000..3ee1fa547c --- /dev/null +++ b/bsps/sparc/include/bsp/grtc.h @@ -0,0 +1,155 @@ +/* GRTC Telecommand (TC) decoder driver interface + * + * COPYRIGHT (c) 2007. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRTC_H__ +#define __GRTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define GRTC_IOC_UNUSED 0 + +/* Driver operation controlling commands */ +#define GRTC_IOC_START 1 +#define GRTC_IOC_STOP 2 +#define GRTC_IOC_ISSTARTED 3 +#define GRTC_IOC_SET_BLOCKING_MODE 4 /* Raw mode only */ +#define GRTC_IOC_SET_TIMEOUT 5 /* Raw mode only */ + +#define GRTC_IOC_ADD_BUFF 16 /* Frame mode only */ +#define GRTC_IOC_RECV 17 /* Frame mode only */ + +/* Available only in STOPPED mode */ +#define GRTC_IOC_SET_MODE 32 /* Set frame mode (ioctl) or raw mode (read) */ +#define GRTC_IOC_SET_BUF_PARAM 33 +#define GRTC_IOC_SET_CONFIG 34 +#define GRTC_IOC_POOLS_SETUP 35 /* Frame mode only */ + +/* Available in both running and stopped mode */ +#define GRTC_IOC_GET_CONFIG 64 +#define GRTC_IOC_GET_BUF_PARAM 65 +#define GRTC_IOC_GET_HW_STATUS 66 +#define GRTC_IOC_ASSIGN_FRM_POOL 67 +#define GRTC_IOC_GET_CLCW_ADR 68 /* Get address of CLCWRx1 */ +#define GRTC_IOC_GET_STATS 69 /* Get statistics, note that most of the stats are only avilable in FRAME mode */ +#define GRTC_IOC_CLR_STATS 70 /* Clear statistics */ + +/* Available only in RUNNING mode */ + +/* Args to GRTC_IOC_GET_BUF_PARAMS */ +#define GRTC_BUF_MAXLEN (0x100*1024) +#define GRTC_BUF_MASK 0xfffffc00 +struct grtc_ioc_buf_params { + unsigned int length; /* Length of new buffer in multiples of 1kbyte blocks */ + void *custom_buffer; /* If set zero driver will allocate with malloc, set LSB to 1 to indicate remote address */ +}; + +/* Args to GRTC_IOC_SET_BLOCKING_MODE */ +enum { + GRTC_BLKMODE_POLL = 0, /* Never block (polling mode) */ + GRTC_BLKMODE_BLK = 1, /* Block until at least 1 byte can be read */ + GRTC_BLKMODE_COMPLETE = 2 /* Block until all data requested has be read */ +}; + +/* Argument of GRTC_IOC_SET_CONFIG and GRTC_IOC_GET_CONFIG + * Pointer to: + */ +struct grtc_ioc_config { + int psr_enable; + int nrzm_enable; + int pss_enable; + int crc_calc; /* Enable Software CRC calculation (only Frame mode) */ +}; + +/* Argument of GRTC_IOC_GET_HW_STATUS: + * Pointer to a grtc_ioc_hw_status structure that will be filled + * in by driver. + */ +struct grtc_ioc_hw_status { + unsigned int sir; + unsigned int far; + unsigned int clcw1; + unsigned int clcw2; + unsigned int phir; + unsigned int str; +}; + +struct grtc_hdr { + unsigned short flags_scid; + unsigned short vc_len; + unsigned char seqnum; +} __attribute__((packed)); + +/* Frame pool, all frames in pool have the same buffer length (frame mode only) */ +struct grtc_frame { + struct grtc_frame *next; /* Next frame in list */ + unsigned short len; /* Length of frame extracted */ + unsigned short reserved; /* Reserved */ + struct grtc_frame_pool *pool; /* The frame pool this frame belongs to */ + + /* The Frame content */ + struct grtc_hdr hdr; /* Primary Header */ + unsigned char data[3]; /* Frame payload */ +} __attribute__((packed)); + +/* GRTC_IOC_RECV argument, single linked list of received frames */ +struct grtc_list { + struct grtc_frame *head; /* First frame in list */ + struct grtc_frame *tail; /* Last frame in list */ + int cnt; /* Number of frames in list */ +}; + +struct grtc_ioc_pools_setup { + unsigned int pool_cnt; /* Number of pools */ + unsigned int pool_frame_len[1]; /* Array of 'pool_cnt' length: Frame length of frames in a pool + * Lengths must be sorted, starting with the smallest frame pool. + */ +}; + +struct grtc_ioc_assign_frm_pool { + unsigned int frame_len; /* The length of the pool to insert the frame into */ + struct grtc_frame *frames; /* Frames to assign to a pool */ +}; + +enum { + GRTC_MODE_RAW = 0, + GRTC_MODE_FRAME = 1 +}; + +/* TC driver stats collected during receiving. The statistics is only available + * in FRAME mode. In RAW mode the user interprets the incoming frames and is + * therefore responsible for generating the staticstics. + */ +struct grtc_ioc_stats { + unsigned long long frames_recv; /* Total number of non-erroneous frames received */ + /* Errors related to incoming data */ + unsigned int err; /* total number of errors */ + unsigned int err_hdr; /* number of errors in Header */ + unsigned int err_payload; /* Number of errors in payload */ + unsigned int err_ending; /* Number of errors in end (Filler, end marker) */ + unsigned int err_abandoned; /* Number of abandoned frames, NOT IMPLEMENTED */ + /* Errors related to the handling of incoming frames */ + unsigned int dropped; /* Number of dropped frames TC driver */ + unsigned int dropped_no_buf; /* Number of dropped frame caused by no buffers were available */ + unsigned int dropped_too_long; /* Number of dropped frames that was larger than any buffer available for driver */ +}; + +/* Register GRTC driver at driver manager */ +void grtc_register_drv(void); + +/* Register GRTC RMAP driver at driver manager */ +void grtc_rmap_register_drv (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __GRTC_H__ */ diff --git a/bsps/sparc/include/bsp/grtm.h b/bsps/sparc/include/bsp/grtm.h new file mode 100644 index 0000000000..625f8389b7 --- /dev/null +++ b/bsps/sparc/include/bsp/grtm.h @@ -0,0 +1,245 @@ +/* GRTM Telemetry (TM) driver interface + * + * COPYRIGHT (c) 2007. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRTM_H__ +#define __GRTM_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define GRTM_IOC_UNUSED 0 + +/* Driver operation controlling commands */ +#define GRTM_IOC_START 1 +#define GRTM_IOC_STOP 2 +#define GRTM_IOC_ISSTARTED 3 +#define GRTM_IOC_SET_BLOCKING_MODE 4 +#define GRTM_IOC_SET_TIMEOUT 5 + +/* Available only in STOPPED mode */ +#define GRTM_IOC_SET_CONFIG 32 + +/* Available in both running and stopped mode */ +#define GRTM_IOC_RECLAIM 64 +#define GRTM_IOC_GET_CONFIG 65 +#define GRTM_IOC_GET_HW_IMPL 66 +#define GRTM_IOC_GET_HW_STATUS 67 /* Not implemented */ +#define GRTM_IOC_GET_OCFREG 68 +#define GRTM_IOC_GET_STATS 69 +#define GRTM_IOC_CLR_STATS 70 + +/* Available only in RUNNING mode */ +#define GRTM_IOC_SEND 96 + +/* Args to GRTC_IOC_SET_BLOCKING_MODE */ +enum { + GRTM_BLKMODE_POLL = 0, /* Never block (polling mode) */ + GRTM_BLKMODE_BLK = 1, /* Block until at least 1 byte can be read */ +}; + +/* Reed Solomon Encoder implemented */ +enum { + GRTM_RS_IMPL_NONE = 0, + GRTM_RS_IMPL_E16 = 1, /* E16 */ + GRTM_RS_IMPL_E8 = 2, /* E8 */ + GRTM_RS_IMPL_BOTH = 3 /* Both E8 and E16 */ + +}; + +struct grtm_ioc_hw { + char cs; /* Sub Carrier */ + char sp; /* Split-Phase Level */ + char ce; + char nrz; + char psr; + char te; + unsigned char rsdep; + unsigned char rs; + char aasm; + char fecf; + char ocf; + char evc; + char idle; + char fsh; + char mcg; + char iz; + char fhec; + char aos; + char cif; + char ocfb; + + unsigned short blk_size; /* Block Size */ + unsigned short fifo_size; /* FIFO Size */ + +}; + +/* Driver Mode */ +enum { + GRTM_MODE_TM = 0, /* TM */ + GRTM_MODE_AOS = 1 /* AOS */ +}; + +/* Physical layer Options */ +#define GRTM_IOC_PHY_SCF (1<<15) /* Sub Carrier Fall */ +#define GRTM_IOC_PHY_SF (1<<31) /* Symbol Fall */ + +/* Coding Sub-layer Options */ +#define GRTM_IOC_CODE_SC (1<<0) /* Enable Sub Carrier modulation */ +#define GRTM_IOC_CODE_SP (1<<1) /* Enable Split-Phase (SP) level modulation */ +#define GRTM_IOC_CODE_CE (1<<5) /* Enable Convolutional Encoding */ +#define GRTM_IOC_CODE_NRZ (1<<6) /* Enable Non-Return-to-Zero mark encoding */ +#define GRTM_IOC_CODE_PSR (1<<7) /* Enable Pseudo-Randomizer */ +#define GRTM_IOC_CODE_RS8 (1<<11) /* Reed-solomon Encoder to use: 0=E16, 1=E8 */ +#define GRTM_IOC_CODE_RS (1<<15) /* Enable Reed-Solomon Encoder */ +#define GRTM_IOC_CODE_AASM (1<<16) /* Enable Alternative attached synchronization marker */ +#define GRTM_IOC_CODE_ALL (GRTM_IOC_CODE_SC|GRTM_IOC_CODE_SP|GRTM_IOC_CODE_CE| \ + GRTM_IOC_CODE_NRZ|GRTM_IOC_CODE_PSR|GRTM_IOC_CODE_RS8|\ + GRTM_IOC_CODE_RS|GRTM_IOC_CODE_AASM) + +enum { + GRTM_CERATE_00 = 0, /* Rate 1/2, no puncturing */ + GRTM_CERATE_02 = 2, /* Rate 1/2, punctured */ + GRTM_CERATE_04 = 4, /* Rate 2/3, punctured */ + GRTM_CERATE_05 = 5, /* Rate 3/4, punctured */ + GRTM_CERATE_06 = 6, /* Rate 5/6, punctured */ + GRTM_CERATE_07 = 7, /* Rate 7/8, punctured */ +}; + +/* Options for Generating all frames */ +#define GRTM_IOC_ALL_FHEC 0x01 /* Enable Frame Header Error Control (Only AOS) */ +#define GRTM_IOC_ALL_FECF 0x02 /* Enable Transfer Frame CRC */ +#define GRTM_IOC_ALL_IZ 0x04 /* Enable Insert Zone */ +#define GRTM_IOC_ALL_ALL (GRTM_IOC_ALL_FHEC|GRTM_IOC_ALL_FECF|GRTM_IOC_ALL_IZ) + +/* Master Frame Generation Options */ +#define GRTM_IOC_MF_OW 0x01 /* Over Write OCF bits 16 and 17 */ +#define GRTM_IOC_MF_OCF 0x02 /* Enable Operation Control Field (OCF) for master channel */ +#define GRTM_IOC_MF_FSH 0x04 /* Enable MC_FSH for master channel */ +#define GRTM_IOC_MF_MC 0x08 /* Enable Master channel counter generation */ +#define GRTM_IOC_MF_ALL (GRTM_IOC_MF_OW|GRTM_IOC_MF_OCF|GRTM_IOC_MF_FSH|GRTM_IOC_MF_MC) + +/* Idle Frames Generation Options */ +#define GRTM_IOC_IDLE_MC 0x01 /* Enable Master Channel (MC) counter generation (TM Only) */ +#define GRTM_IOC_IDLE_VCC 0x02 /* Enable Virtual Channel counter cycle generation (AOS Only)*/ +#define GRTM_IOC_IDLE_FSH 0x04 /* Enable Frame Secondary Header (FSH) for idle frames (TM Only) */ +#define GRTM_IOC_IDLE_EVC 0x08 /* Enable Extended Virtual Channel Counter Generation */ +#define GRTM_IOC_IDLE_OCF 0x10 /* Enable OCF/CLCW in idle frame */ +#define GRTM_IOC_IDLE_EN 0x20 /* Enable Idle frame generation */ +#define GRTM_IOC_IDLE_ALL (GRTM_IOC_IDLE_MC|GRTM_IOC_IDLE_VCC|GRTM_IOC_IDLE_FSH| \ + GRTM_IOC_IDLE_EVC|GRTM_IOC_IDLE_OCF|GRTM_IOC_IDLE_EN) + +/* Argument of GRTM_IOC_SET_CONFIG and GRTM_IOC_GET_CONFIG. + * Driver and Hardware configuration. + * + * Pointer to: + */ +struct grtm_ioc_config { + + /* Mode AOS or TM */ + unsigned char mode; /* 0=TM, 1=AOS */ + + unsigned short frame_length; /* Length of every frame transmitted */ + unsigned short limit; /* Number of data bytes fetched by DMA before transmission starts */ + unsigned int as_marker; /* Attached Synchronization Marker */ + + /* Physical layer options */ + unsigned short phy_subrate; /* Sub Carrier rate - sub carrier devision factor - 1 */ + unsigned short phy_symbolrate; /* Symbol Rate division factor - 1 */ + unsigned char phy_opts; /* Mask of GRTM_IOC_PHY_XXXX */ + + /* Coding sub-layer Options */ + unsigned char code_rsdep; /* Coding sub-layer Reed-Solomon interleave depth (3-bit) */ + unsigned char code_ce_rate; /* Convolutional encoding rate, select one of GRTM_CERATE_00 ... GRTM_CERATE_07 */ + unsigned char code_csel; /* */ + unsigned int code_opts; /* Mask of GRTM_IOC_CODE_XXXX */ + + /* All Frames Generation */ + unsigned char all_izlen; /* FSH/IZ Length (5-bit) */ + unsigned char all_opts; /* Mask of GRTM_IOC_ALL_XXXX */ + + /* Master Frame Generation */ + unsigned char mf_opts; /* Mask of GRTM_IOC_MF_XXXX */ + + /* Idle frame Generation */ + unsigned short idle_scid; + unsigned char idle_vcid; + unsigned char idle_opts; /* Mask of GRTM_IOC_IDLE_XXXX */ + + /* Interrupt options */ + unsigned int enable_cnt; /* Number of frames in between Interrupt is generated, Zero disables interrupt */ + int isr_desc_proc; /* Enable ISR to process descriptors */ + int blocking; /* Blocking mode select (POLL,BLK..) */ + rtems_interval timeout; /* Blocking mode timeout */ +}; + +struct grtm_frame; + +struct grtm_list { + struct grtm_frame *head; /* First Frame in list */ + struct grtm_frame *tail; /* Last Frame in list */ +}; + +#define GRTM_FLAGS_SENT 0x01 +#define GRRM_FLAGS_ERR 0x02 + +#define GRTM_FLAGS_TRANSLATE (1<<31) /* Translate frame payload address from CPU address to remote bus (the bus GRTM is resident on) */ +#define GRTM_FLAGS_TRANSLATE_AND_REMEMBER (1<<30) /* As GRTM_FLAGS_TRANSLATE, however if the translated payload address equals the payload address + * the GRTM_FLAGS_TRANSLATE_AND_REMEMBER bit is cleared and the GRTM_FLAGS_TRANSLATE bit is set */ +#define GRTM_FLAGS_COPY_DATA (1<<29) /* Where available: Transfer Frame payload to target, may be used for SpaceWire, where the GRTM driver transfer + * the payload to a buffer on the SpaceWire target. + */ + +#define GRTM_FLAGS_TS (1<<14) +#define GRTM_FLAGS_VCE (1<<9) +#define GRTM_FLAGS_MCB (1<<8) +#define GRTM_FLAGS_FSHB (1<<7) +#define GRTM_FLAGS_OCFB (1<<6) +#define GRTM_FLAGS_FHECB (1<<5) +#define GRTM_FLAGS_IZB (1<<4) +#define GRTM_FLAGS_FECFB (1<<3) + +#define GRTM_FLAGS_MASK (GRTM_FLAGS_TS|GRTM_FLAGS_VCE|GRTM_FLAGS_MCB|\ + GRTM_FLAGS_FSHB|GRTM_FLAGS_OCFB|GRTM_FLAGS_FHECB|\ + GRTM_FLAGS_IZB|GRTM_FLAGS_FECFB) + +/* The GRTM software representation of a Frame */ +struct grtm_frame { + /* Options and status */ + unsigned int flags; /* bypass options, and sent/error status */ + + struct grtm_frame *next; /* Next packet in chain */ + + unsigned int *payload; /* The Headers and Payload, Frame data and header must be word aligned */ +}; + +#define FRAME_SIZE(payloadlen) (sizeof(struct grtm_frame)+payloadlen) + +struct grtm_ioc_stats { + unsigned long long frames_sent; + unsigned int err_underrun; + unsigned int err_tx; + unsigned int err_ahb; + unsigned int err_transfer_frame; +}; + +/* Register GRTM driver at driver manager */ +void grtm_register_drv(void); + +/* Register GRTM RMAP driver at driver manager */ +void grtm_rmap_register_drv (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __GRTM_H__ */ diff --git a/bsps/sparc/include/bsp/i2cmst.h b/bsps/sparc/include/bsp/i2cmst.h new file mode 100644 index 0000000000..3eee717524 --- /dev/null +++ b/bsps/sparc/include/bsp/i2cmst.h @@ -0,0 +1,65 @@ +/** + * @file + * @ingroup sparc_bsp + * @defgroup i2c I2C-master + * @ingroup i2c + * @brief Driver for GRLIB port of OpenCores I2C-master + */ + +/* + * COPYRIGHT (c) 2007 Cobham Gaisler AB + * with parts from the RTEMS MPC83xx I2C driver (c) 2007 Embedded Brains GmbH. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _I2CMST_H +#define _I2CMST_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* I2C-master operational registers */ + +typedef struct gr_i2cmst_regs { + volatile unsigned int prescl; /* Prescale register */ + volatile unsigned int ctrl; /* Control register */ + volatile unsigned int tdrd; /* Transmit and Receive registers */ + volatile unsigned int cmdsts; /* Command and Status registers */ +} gr_i2cmst_regs_t; + +/* Control (CTRL) register */ +#define GRI2C_CTRL_EN 0x00000080 /* Enable core */ +#define GRI2C_CTRL_IEN 0x00000040 /* Interrupt enable */ + +/* Command (CMD) register */ +#define GRI2C_CMD_STA 0x00000080 /* Generate START condition */ +#define GRI2C_CMD_STO 0x00000040 /* Generate STOP condition */ +#define GRI2C_CMD_RD 0x00000020 /* Read from slave */ +#define GRI2C_CMD_WR 0x00000010 /* Write to slave */ +#define GRI2C_CMD_ACK 0x00000008 /* Acknowledge */ +#define GRI2C_CMD_IACK 0x00000001 /* Interrupt acknowledge */ + +/* Status (STS) register */ +#define GRI2C_STS_RXACK 0x00000080 /* Receive acknowledge */ +#define GRI2C_STS_BUSY 0x00000040 /* I2C-bus busy */ +#define GRI2C_STS_AL 0x00000020 /* Arbitration lost */ +#define GRI2C_STS_TIP 0x00000002 /* Transfer in progress */ +#define GRI2C_STS_IF 0x00000001 /* Interrupt flag */ + +#define GRI2C_STATUS_IDLE 0x00000000 + +/* Register I2CMST driver to Driver Manager */ +void i2cmst_register_drv (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _I2CMST_H */ diff --git a/bsps/sparc/include/bsp/l2c.h b/bsps/sparc/include/bsp/l2c.h new file mode 100644 index 0000000000..52473ddf2a --- /dev/null +++ b/bsps/sparc/include/bsp/l2c.h @@ -0,0 +1,201 @@ +/* + * GRLIB L2CACHE Driver + * + * COPYRIGHT (c) 2017 + * Cobham Gaisler AB + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * OVERVIEW + * ======== + * This driver controls the L2CACHE device located + * at an on-chip AMBA. + */ + +#ifndef __L2CACHE_H__ +#define __L2CACHE_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void l2cache_register_drv(void); + +#define L2CACHE_ERR_OK 0 +#define L2CACHE_ERR_NOINIT -1 +#define L2CACHE_ERR_EINVAL -2 +#define L2CACHE_ERR_TOOMANY -3 +#define L2CACHE_ERR_ERROR -4 + +/* L2C Flush options */ +#define L2CACHE_OPTIONS_FLUSH_WAIT (0x1 << 2) +#define L2CACHE_OPTIONS_FLUSH_INVALIDATE (0x3 << 0) +#define L2CACHE_OPTIONS_FLUSH_WRITEBACK (0x2 << 0) +#define L2CACHE_OPTIONS_FLUSH_INV_WBACK (0x1 << 0) +#define L2CACHE_OPTIONS_FLUSH_NONE (0 << 0) + +/* L2C Status */ +#define L2CACHE_STATUS_ENABLED 1 +#define L2CACHE_STATUS_SPLIT_ENABLED (0x1 << 1) +#define L2CACHE_STATUS_EDAC_ENABLED (0x1 << 2) +#define L2CACHE_STATUS_REPL (0x3 << L2CACHE_STATUS_REPL_BIT) +#define L2CACHE_STATUS_REPL_BIT 3 +#define L2CACHE_STATUS_WRITETHROUGH (0x1 << 5) +#define L2CACHE_STATUS_LOCK (0xf << L2CACHE_STATUS_LOCK_BIT) +#define L2CACHE_STATUS_LOCK_BIT 6 +#define L2CACHE_STATUS_SCRUB_ENABLED (0x1 << 10) +#define L2CACHE_STATUS_INT (0xf << L2CACHE_STATUS_INT_BIT) +#define L2CACHE_STATUS_INT_BIT 11 +#define L2CACHE_STATUS_INT_BCKEND (0x1 << 11) +#define L2CACHE_STATUS_INT_WPHIT (0x1 << 12) +#define L2CACHE_STATUS_INT_UEE (0x1 << 13) +#define L2CACHE_STATUS_INT_CEE (0x1 << 14) +#define L2CACHE_STATUS_SCRUB_DELAY (0xffff << L2CACHE_STATUS_SCRUB_DELAY_BIT) +#define L2CACHE_STATUS_SCRUB_DELAY_BIT 15 +#define L2CACHE_STATUS_SIGN_BIT 31 + +/* status helper macros */ +#define L2CACHE_ENABLED(status) (status & L2CACHE_STATUS_ENABLED) +#define L2CACHE_DISABLED(status) (!(status & L2CACHE_STATUS_ENABLED)) +#define L2CACHE_SPLIT_ENABLED(status) (status & L2CACHE_STATUS_SPLIT_ENABLED) +#define L2CACHE_SPLIT_DISABLED(status) \ + (!(status & L2CACHE_STATUS_SPLIT_ENABLED)) +#define L2CACHE_EDAC_ENABLED(status) (status & L2CACHE_STATUS_EDAC_ENABLED) +#define L2CACHE_EDAC_DISABLED(status) (!(status & L2CACHE_STATUS_EDAC_ENABLED)) +#define L2CACHE_REPL(status) \ + ((status & L2CACHE_STATUS_REPL) >> L2CACHE_STATUS_REPL_BIT) +#define L2CACHE_WRITETHROUGH(status) (status & L2CACHE_STATUS_WRITETHROUGH) +#define L2CACHE_WRITEBACK(status) (!(status & L2CACHE_STATUS_WRITETHROUGH)) +#define L2CACHE_LOCKED_WAYS(status) \ + ((status & L2CACHE_STATUS_LOCK) >> L2CACHE_STATUS_LOCK_BIT) +#define L2CACHE_SCRUB_ENABLED(status) (status & L2CACHE_STATUS_SCRUB_ENABLED) +#define L2CACHE_SCRUB_DISABLED(status) \ + (!(status & L2CACHE_STATUS_SCRUB_ENABLED)) +#define L2CACHE_SCRUB_DELAY(status) \ + ((status & L2CACHE_STATUS_SCRUB_DELAY) >> L2CACHE_STATUS_SCRUB_DELAY_BIT) +#define L2CACHE_INT_ENABLED(status) (status & L2CACHE_STATUS_INT) +#define L2CACHE_INT_DISABLED(status) (!(status & L2CACHE_STATUS_INT)) +extern int l2cache_status(void); + +/* L2C Setup */ +extern int l2cache_enable(int flush); +extern int l2cache_disable(int flush); + +extern int l2cache_split_enable(void); +extern int l2cache_split_disable(void); + +extern int l2cache_edac_enable(int flush); +extern int l2cache_edac_disable(int flush); + +extern int l2cache_scrub_enable(int delay); +extern int l2cache_scrub_disable(void); +extern int l2cache_scrub_line(int way, int index); + +extern int l2cache_writethrough(int flush); +extern int l2cache_writeback(int flush); + +#define L2CACHE_OPTIONS_REPL_INDEX_WAY_BIT (2) +#define L2CACHE_OPTIONS_REPL_MASTERIDX_MOD (3 << 0) +#define L2CACHE_OPTIONS_REPL_MASTERIDX_IDX (2 << 0) +#define L2CACHE_OPTIONS_REPL_RANDOM (1 << 0) +#define L2CACHE_OPTIONS_REPL_LRU (0 << 0) +extern int l2cache_replacement(int options, int flush); + +/* L2C Flush */ +extern int l2cache_flush(int flush); +extern int l2cache_flush_address(uint32_t addr, int size, int flush); +extern int l2cache_flush_line(int way, int index, int flush); +extern int l2cache_flush_way(int way, int flush); + +/* L2C Lock way */ +#define L2CACHE_OPTIONS_DIRTY (0x1 << 2) +#define L2CACHE_OPTIONS_VALID (0x1 << 1) +#define L2CACHE_OPTIONS_FETCH (0x1 << 0) +#define L2CACHE_OPTIONS_DISABLE 2 +#define L2CACHE_OPTIONS_ENABLE 1 +#define L2CACHE_OPTIONS_NONE 0 +extern int l2cache_lock_way(uint32_t tag, int options, int flush, int enable); +extern int l2cache_unlock(void); + +/* L2C Fill a way */ +extern int l2cache_fill_way(int way, uint32_t tag, int options, int flush); + +/* L2C MTRR */ +#define L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH (0x1 << 2) +#define L2CACHE_OPTIONS_MTRR_ACCESS_UNCACHED (0x0 << 2) +#define L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE (0x1 << 1) +#define L2CACHE_OPTIONS_MTRR_WRITEPROT_DISABLE (0x0 << 1) +extern int l2cache_mtrr_enable(int id, uint32_t addr, uint32_t mask, + int options, int flush); +extern int l2cache_mtrr_disable(int id); + +/* L2C Debug print */ +extern int l2cache_print(void); + +/* L2C Interrupts */ +/* Function Interrupt-Code ISR callback prototype. + * arg - Custom arg provided by user + * addr - Cacheline addr that generated the error + * status - Error status register of the L2CACHE core + */ +typedef void (*l2cache_isr_t)(void *arg, uint32_t addr, uint32_t status); +#define L2CACHE_INTERRUPT_ALL (0xf << 0) +#define L2CACHE_INTERRUPT_BACKENDERROR (0x1 << 3) +#define L2CACHE_INTERRUPT_WPROTHIT (0x1 << 2) +#define L2CACHE_INTERRUPT_UNCORRERROR (0x1 << 1) +#define L2CACHE_INTERRUPT_CORRERROR (0x1 << 0) +extern int l2cache_isr_register( l2cache_isr_t isr, void * arg, int options); +extern int l2cache_isr_unregister(void); +extern int l2cache_interrupt_mask(int options); +extern int l2cache_interrupt_unmask(int options); + +/* L2C error interface */ +#define L2CACHE_STATUS_MULTIPLEERRORS 2 +#define L2CACHE_STATUS_NEWERROR 1 +#define L2CACHE_STATUS_NOERROR 0 +extern int l2cache_error_status(uint32_t * addr, uint32_t * status); + +/*#define TEST_L2CACHE*/ +#ifdef TEST_L2CACHE +/* Used for internal testing */ +/* + * L2CACHE Tag private data struture + */ +struct l2cache_tag { + uint32_t tag; + int valid; + int dirty; + int lru; +}; + +/* + * L2CACHE Line private data struture + */ +struct l2cache_dataline { + uint32_t data[16]; + int words; +}; +extern int l2cache_get_index( uint32_t addr); +extern uint32_t l2cache_get_tag( uint32_t addr); + +extern int l2cache_diag_tag( int way, int index, struct l2cache_tag * tag); +extern int l2cache_diag_line( int way, int index, + struct l2cache_dataline * dataline); + +#define L2CACHE_HIT 1 +#define L2CACHE_MISS 0 +extern int l2cache_lookup(uint32_t addr, int * way); + +extern int l2cache_error_inject_address( uint32_t addr, uint32_t mask); +#endif /* TEST_L2CACHE */ + +#ifdef __cplusplus +} +#endif + +#endif /* __L2CACHE_H__ */ diff --git a/bsps/sparc/include/bsp/l4stat.h b/bsps/sparc/include/bsp/l4stat.h new file mode 100644 index 0000000000..94fbe4b095 --- /dev/null +++ b/bsps/sparc/include/bsp/l4stat.h @@ -0,0 +1,91 @@ +/* + * L4STAT APB-Register Driver. + * + * COPYRIGHT (c) 2017. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __L4STAT_H__ +#define __L4STAT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define L4STAT_ERR_OK 0 +#define L4STAT_ERR_EINVAL -1 +#define L4STAT_ERR_ERROR -2 +#define L4STAT_ERR_TOOMANY -3 +#define L4STAT_ERR_IMPLEMENTED -4 + +/* Register L4STAT driver to Driver Manager */ +void l4stat_register_drv (void); + +extern int l4stat_counter_print(unsigned int counter); + +/* + * L4STAT CCTRL register fields + */ +#define CCTRL_NCPU (0xf << CCTRL_NCPU_BIT) +#define CCTRL_NCNT_L3STAT (0x1ff << CCTRL_NCNT_BIT) +#define CCTRL_NCNT (0x1f << CCTRL_NCNT_BIT) +#define CCTRL_MC (0x1 << CCTRL_MC_BIT) +#define CCTRL_IA (0x1 << CCTRL_IA_BIT) +#define CCTRL_DS (0x1 << CCTRL_DS_BIT) +#define CCTRL_EE (0x1 << CCTRL_EE_BIT) +#define CCTRL_AE (0x1 << CCTRL_AE_BIT) +#define CCTRL_EL (0x1 << CCTRL_EL_BIT) +#define CCTRL_CD (0x1 << CCTRL_CD_BIT) +#define CCTRL_SU (0x3 << CCTRL_SU_BIT) +#define CCTRL_CL (0x1 << CCTRL_CL_BIT) +#define CCTRL_EN (0x1 << CCTRL_EN_BIT) +#define CCTRL_EVENTID (0xff << CCTRL_EVENTID_BIT) +#define CCTRL_CPUAHBM (0xf << CCTRL_CPUAHBM_BIT) + +#define CCTRL_NCPU_BIT 28 +#define CCTRL_NCNT_BIT 23 +#define CCTRL_MC_BIT 22 +#define CCTRL_IA_BIT 21 +#define CCTRL_DS_BIT 20 +#define CCTRL_EE_BIT 19 +#define CCTRL_AE_BIT 18 +#define CCTRL_EL_BIT 17 +#define CCTRL_CD_BIT 16 +#define CCTRL_SU_BIT 14 +#define CCTRL_CL_BIT 13 +#define CCTRL_EN_BIT 12 +#define CCTRL_EVENTID_BIT 4 +#define CCTRL_CPUAHBM_BIT 0 + +#define L4STAT_OPTIONS_EVENT_LEVEL_ENABLE CCTRL_EL +#define L4STAT_OPTIONS_EVENT_LEVEL_DISABLE 0 +#define L4STAT_OPTIONS_MAXIMUM_DURATION CCTRL_CD +#define L4STAT_OPTIONS_SUPERVISOR_MODE_FILTER (0x1 << CCTRL_SU_BIT) +#define L4STAT_OPTIONS_USER_MODE_FILTER (0x2 << CCTRL_SU_BIT) +#define L4STAT_OPTIONS_NO_FILTER 0 +#define L4STAT_OPTIONS_CLEAR_ON_READ CCTRL_CL + +extern int l4stat_counter_enable(unsigned int counter, int event, int cpu, int options); +extern int l4stat_counter_disable(unsigned int counter); +extern int l4stat_counter_set(unsigned int counter, uint32_t val); +extern int l4stat_counter_get(unsigned int counter, uint32_t *val); + +static inline int l4stat_counter_clear(unsigned int counter) +{ + return l4stat_counter_set(counter, 0); +} + +extern int l4stat_counter_max_set(unsigned int counter, uint32_t val); +extern int l4stat_counter_max_get(unsigned int counter, uint32_t *val); +extern int l4stat_tstamp_set(uint32_t val); +extern int l4stat_tstamp_get(uint32_t *val); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/mctrl.h b/bsps/sparc/include/bsp/mctrl.h new file mode 100644 index 0000000000..db449cb11a --- /dev/null +++ b/bsps/sparc/include/bsp/mctrl.h @@ -0,0 +1,26 @@ +/* + * Memory Controller driver interface + * + * COPYRIGHT (c) 2015. + * Cobham Gaisler. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __MCTRL_H__ +#define __MCTRL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register MEMCTRL driver to Driver manager */ +void mctrl_register_drv (void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/memscrub.h b/bsps/sparc/include/bsp/memscrub.h new file mode 100644 index 0000000000..1e55d8e127 --- /dev/null +++ b/bsps/sparc/include/bsp/memscrub.h @@ -0,0 +1,172 @@ +/* MEMSCRUB driver interface + * + * COPYRIGHT (c) 2017. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __MEMSCRUB_H__ +#define __MEMSCRUB_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define MEMSCRUB_ERR_OK 0 +#define MEMSCRUB_ERR_EINVAL -1 +#define MEMSCRUB_ERR_ERROR -2 + +extern void memscrub_register_drv(void); + +/* + * MEMORYSCRUBBER CONFIG register fields + */ +#define CONFIG_DELAY_BIT 8 +#define CONFIG_IRQD_BIT 7 +#define CONFIG_SERA_BIT 5 +#define CONFIG_LOOP_BIT 4 +#define CONFIG_MODE_BIT 2 +#define CONFIG_ES_BIT 1 +#define CONFIG_SCEN_BIT 0 + +#define CONFIG_DELAY (0xff << CONFIG_DELAY_BIT) +#define CONFIG_IRQD (0x1 << CONFIG_IRQD_BIT) +#define CONFIG_SERA (0x1 << CONFIG_SERA_BIT) +#define CONFIG_LOOP (0x1 << CONFIG_LOOP_BIT) +#define CONFIG_MODE (0x3 << CONFIG_MODE_BIT) +#define CONFIG_ES (0x1 << CONFIG_ES_BIT) +#define CONFIG_SCEN (0x1 << CONFIG_SCEN_BIT) +#define CONFIG_MODE_SCRUB (0x0 << CONFIG_MODE_BIT) +#define CONFIG_MODE_REGEN (0x1 << CONFIG_MODE_BIT) +#define CONFIG_MODE_INIT (0x2 << CONFIG_MODE_BIT) + +#define MEMSCRUB_OPTIONS_INTERRUPTDONE_ENABLE CONFIG_IRQD +#define MEMSCRUB_OPTIONS_INTERRUPTDONE_DISABLE 0 +#define MEMSCRUB_OPTIONS_EXTERNALSTART_ENABLE CONFIG_ES +#define MEMSCRUB_OPTIONS_EXTERNALSTART_DISABLE 0 +#define MEMSCRUB_OPTIONS_LOOPMODE_ENABLE CONFIG_LOOP +#define MEMSCRUB_OPTIONS_LOOPMODE_DISABLE 0 +#define MEMSCRUB_OPTIONS_SECONDARY_MEMRANGE_ENABLE CONFIG_SERA +#define MEMSCRUB_OPTIONS_SECONDARY_MEMRANGE_DISABLE 0 + +/* Scrubbing modes */ +extern int memscrub_init_start(uint32_t value, uint8_t delay, int options); +extern int memscrub_scrub_start(uint8_t delay, int options); +extern int memscrub_regen_start(uint8_t delay, int options); +extern int memscrub_stop(void); +extern int memscrub_active(void); + +/* Set/get memory ranges */ +extern int memscrub_range_set(uint32_t start, uint32_t end); +extern int memscrub_range_get(uint32_t * start, uint32_t * end); +extern int memscrub_secondary_range_set(uint32_t start, uint32_t end); +extern int memscrub_secondary_range_get(uint32_t * start, uint32_t * end); + +/* Interrupts */ +/* MEMSCRUB Interrupts */ +/* Function Interrupt-Code ISR callback prototype. + * arg - Custom arg provided by user + * access - AHB Access that failed + * ahbstatus - AHB status register of the MEMSCRUB core + * status - status register of the MEMSCRUB core + */ +typedef void (*memscrub_isr_t)(void *arg, uint32_t ahbaccess, + uint32_t ahbstatus, uint32_t scrubstatus); +extern int memscrub_isr_register(memscrub_isr_t isr, void * data); +extern int memscrub_isr_unregister(void); + +extern int memscrub_error_status(uint32_t *ahbaccess, uint32_t *ahbstatus, + uint32_t *scrubstatus); + +/* Set the different error thresholds. */ + +/* + * MEMORYSCRUBBER AHBS register fields + */ +#define AHBS_CECNT_BIT 22 +#define AHBS_UECNT_BIT 14 +#define AHBS_DONE_BIT 13 +#define AHBS_SEC_BIT 11 +#define AHBS_SBC_BIT 10 +#define AHBS_CE_BIT 9 +#define AHBS_NE_BIT 8 +#define AHBS_HW_BIT 7 +#define AHBS_HM_BIT 3 +#define AHBS_HS_BIT 0 + +#define AHBS_CECNT (0x3ff << AHBS_CECNT_BIT) +#define AHBS_UECNT (0xff << AHBS_UECNT_BIT) +#define AHBS_DONE (1 << AHBS_DONE_BIT) +#define AHBS_SEC (1 << AHBS_SEC_BIT) +#define AHBS_SBC (1 << AHBS_SBC_BIT) +#define AHBS_CE (1 << AHBS_CE_BIT) +#define AHBS_NE (1 << AHBS_NE_BIT) +#define AHBS_HW (1 << AHBS_HW_BIT) +#define AHBS_HM (0xf << AHBS_HM_BIT) +#define AHBS_HS (0x7 << AHBS_HS_BIT) + +/* + * MEMORYSCRUBBER STAT register fields + */ +#define STAT_RUNCOUNT_BIT 22 +#define STAT_BLKCOUNT_BIT 14 +#define STAT_DONE_BIT 13 +#define STAT_BURSTLEN_BIT 1 +#define STAT_ACTIVE_BIT 0 + +#define STAT_RUNCOUNT (0x3ff << STAT_RUNCOUNT_BIT) +#define STAT_BLKCOUNT (0xff << STAT_BLKCOUNT_BIT) +#define STAT_DONE (0x1 << STAT_DONE_BIT) +#define STAT_BURSTLEN (0xf << STAT_BURSTLEN_BIT) +#define STAT_ACTIVE (0x1 << STAT_ACTIVE_BIT) + +/* + * MEMORYSCRUBBER AHBERC register fields + */ +#define AHBERC_CECNTT_BIT 22 +#define AHBERC_UECNTT_BIT 14 +#define AHBERC_CECTE_BIT 1 +#define AHBERC_UECTE_BIT 0 + +#define AHBERC_CECNTT (0x3ff << AHBERC_CECNTT_BIT) +#define AHBERC_UECNTT (0xff << AHBERC_UECNTT_BIT) +#define AHBERC_CECTE (0x1 << AHBERC_CECTE_BIT) +#define AHBERC_UECTE (0x1 << AHBERC_UECTE_BIT) + +/* + * MEMORYSCRUBBER ETHRES register fields + */ +#define ETHRES_RECT_BIT 22 +#define ETHRES_BECT_BIT 14 +#define ETHRES_RECTE_BIT 1 +#define ETHRES_BECTE_BIT 0 + +#define ETHRES_RECT (0x3ff << ETHRES_RECT_BIT) +#define ETHRES_BECT (0xff << ETHRES_BECT_BIT) +#define ETHRES_RECTE (0x1 << ETHRES_RECTE_BIT) +#define ETHRES_BECTE (0x1 << ETHRES_BECTE_BIT) + +#define MEMSCRUB_OPTIONS_AHBERROR_CORTHRES_ENABLE AHBERC_CECTE +#define MEMSCRUB_OPTIONS_AHBERROR_CORTHRES_DISABLE 0 +#define MEMSCRUB_OPTIONS_AHBERROR_UNCORTHRES_ENABLE AHBERC_UECTE +#define MEMSCRUB_OPTIONS_AHBERROR_UNCORTHRES_DISABLE 0 +#define MEMSCRUB_OPTIONS_SCRUBERROR_RUNTHRES_ENABLE ETHRES_RECTE +#define MEMSCRUB_OPTIONS_SCRUBERROR_RUNTHRES_DISABLE 0 +#define MEMSCRUB_OPTIONS_SCRUBERROR_BLOCKTHRES_ENABLE ETHRES_BECTE +#define MEMSCRUB_OPTIONS_SCRUBERROR_BLOCKTHRES_DISABLE 0 +extern int memscrub_ahberror_setup(int uethres, int cethres, int options); +extern int memscrub_scruberror_setup(int blkthres, int runthres, + int options); + +extern int memscrub_scrub_position(uint32_t * position); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/network_interface_add.h b/bsps/sparc/include/bsp/network_interface_add.h new file mode 100644 index 0000000000..b04a96f003 --- /dev/null +++ b/bsps/sparc/include/bsp/network_interface_add.h @@ -0,0 +1,47 @@ +/* Network interface register help function + * + * COPYRIGHT (c) 2008. + * Cobham Gaisler AB. + * + * This function adds a network interface to the + * rtems_bsdnet_config.ifconfig linked list of interfaces. + * The interface configuration is taken from the user defined + * array interface_configs. This function is useful for PnP + * systems when an unknown number of interfaces are available. + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __NETWORK_INTERFACE_ADD_H__ +#define __NETWORK_INTERFACE_ADD_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Interface configuration description */ +struct ethernet_config { + char *ip_addr; /* IP address */ + char *ip_netmask; /* IP Netmask */ + char eth_adr[6]; /* Ethernet hardware MAC address */ +}; + +/* Array with configurations for all interfaces in the system + * Must be defined by the user. + */ +extern struct ethernet_config interface_configs[]; + +/* Routine adding interface to rtems_bsdnet_config.ifconfig linked + * list of interfaces. + */ +int network_interface_add(struct rtems_bsdnet_ifconfig *interface); + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_NETWORKCONFIG_H_ */ diff --git a/bsps/sparc/include/bsp/occan.h b/bsps/sparc/include/bsp/occan.h new file mode 100644 index 0000000000..0bf34dee48 --- /dev/null +++ b/bsps/sparc/include/bsp/occan.h @@ -0,0 +1,165 @@ +/** + * @file + * @ingroup can + * @brief Gaisler wrapper to OpenCores CAN - driver interface + */ + +/* + * COPYRIGHT (c) 2007. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __OCCAN_DRIVER_H__ +#define __OCCAN_DRIVER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* CAN MESSAGE */ +typedef struct { + char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */ + char rtr; /* RTR - Remote Transmission Request */ + char sshot; /* single shot */ + unsigned char len; + unsigned char data[8]; + unsigned int id; +} CANMsg; + +typedef struct { + /* tx/rx stats */ + unsigned int rx_msgs; + unsigned int tx_msgs; + + /* Error Interrupt counters */ + unsigned int err_warn; + unsigned int err_dovr; + unsigned int err_errp; + unsigned int err_arb; + unsigned int err_bus; + + /**** BUS ERRORS (err_arb) ****/ + + /* ALC 4-0 */ + unsigned int err_arb_bitnum[32]; /* At what bit arbitration is lost */ + + /******************************/ + + /**** BUS ERRORS (err_bus) ****/ + + /* ECC 7-6 */ + unsigned int err_bus_bit; /* Bit error */ + unsigned int err_bus_form; /* Form Error */ + unsigned int err_bus_stuff; /* Stuff Error */ + unsigned int err_bus_other; /* Other Error */ + + /* ECC 5 */ + unsigned int err_bus_rx; /* Errors during Reception */ + unsigned int err_bus_tx; /* Errors during Transmission */ + + /* ECC 4:0 */ + unsigned int err_bus_segs[32]; /* Segment (Where in frame error occured) + * See OCCAN_SEG_* defines for indexes + */ + + /******************************/ + + + /* total number of interrupts */ + unsigned int ints; + + /* software monitoring hw errors */ + unsigned int tx_buf_error; + + /* Software fifo overrun */ + unsigned int rx_sw_dovr; + +} occan_stats; + +/* indexes into occan_stats.err_bus_segs[index] */ +#define OCCAN_SEG_ID28 0x02 /* ID field bit 28:21 */ +#define OCCAN_SEG_ID20 0x06 /* ID field bit 20:18 */ +#define OCCAN_SEG_ID17 0x07 /* ID field bit 17:13 */ +#define OCCAN_SEG_ID12 0x0f /* ID field bit 12:5 */ +#define OCCAN_SEG_ID4 0x0e /* ID field bit 4:0 */ + +#define OCCAN_SEG_START 0x03 /* Start of Frame */ +#define OCCAN_SEG_SRTR 0x04 /* Bit SRTR */ +#define OCCAN_SEG_IDE 0x05 /* Bit IDE */ +#define OCCAN_SEG_RTR 0x0c /* Bit RTR */ +#define OCCAN_SEG_RSV0 0x09 /* Reserved bit 0 */ +#define OCCAN_SEG_RSV1 0x0d /* Reserved bit 1 */ + +#define OCCAN_SEG_DLEN 0x0b /* Data Length code */ +#define OCCAN_SEG_DFIELD 0x0a /* Data Field */ + +#define OCCAN_SEG_CRC_SEQ 0x08 /* CRC Sequence */ +#define OCCAN_SEG_CRC_DELIM 0x18 /* CRC Delimiter */ + +#define OCCAN_SEG_ACK_SLOT 0x19 /* Acknowledge slot */ +#define OCCAN_SEG_ACK_DELIM 0x1b /* Acknowledge delimiter */ +#define OCCAN_SEG_EOF 0x1a /* End Of Frame */ +#define OCCAN_SEG_INTERMISSION 0x12 /* Intermission */ +#define OCCAN_SEG_ACT_ERR 0x11 /* Active error flag */ +#define OCCAN_SEG_PASS_ERR 0x16 /* Passive error flag */ +#define OCCAN_SEG_DOMINANT 0x13 /* Tolerate dominant bits */ +#define OCCAN_SEG_EDELIM 0x17 /* Error delimiter */ +#define OCCAN_SEG_OVERLOAD 0x1c /* overload flag */ + + +#define CANMSG_OPT_RTR 0x40 /* RTR Frame */ +#define CANMSG_OPT_EXTENDED 0x80 /* Exteneded frame */ +#define CANMSG_OPT_SSHOT 0x01 /* Single Shot, no retry */ + +#define OCCAN_IOC_START 1 +#define OCCAN_IOC_STOP 2 + +#define OCCAN_IOC_GET_CONF 3 +#define OCCAN_IOC_GET_STATS 4 +#define OCCAN_IOC_GET_STATUS 5 + +#define OCCAN_IOC_SET_SPEED 6 +#define OCCAN_IOC_SPEED_AUTO 7 +#define OCCAN_IOC_SET_LINK 8 +#define OCCAN_IOC_SET_FILTER 9 +#define OCCAN_IOC_SET_BLK_MODE 10 +#define OCCAN_IOC_SET_BUFLEN 11 +#define OCCAN_IOC_SET_BTRS 12 + + +struct occan_afilter { + unsigned char code[4]; + unsigned char mask[4]; + int single_mode; +}; + +#define OCCAN_STATUS_RESET 0x01 +#define OCCAN_STATUS_OVERRUN 0x02 +#define OCCAN_STATUS_WARN 0x04 +#define OCCAN_STATUS_ERR_PASSIVE 0x08 +#define OCCAN_STATUS_ERR_BUSOFF 0x10 +#define OCCAN_STATUS_QUEUE_ERROR 0x80 + +#define OCCAN_BLK_MODE_RX 0x1 +#define OCCAN_BLK_MODE_TX 0x2 + +void occan_register_drv (void); + + +#define OCCAN_SPEED_500K 500000 +#define OCCAN_SPEED_250K 250000 +#define OCCAN_SPEED_125K 125000 +#define OCCAN_SPEED_75K 75000 +#define OCCAN_SPEED_50K 50000 +#define OCCAN_SPEED_25K 25000 +#define OCCAN_SPEED_10K 10000 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/pcif.h b/bsps/sparc/include/bsp/pcif.h new file mode 100644 index 0000000000..0221fcdd50 --- /dev/null +++ b/bsps/sparc/include/bsp/pcif.h @@ -0,0 +1,15 @@ +#ifndef __PCIF_H__ +#define __PCIF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register the PCIF PCI host driver to the Driver Manager */ +extern void pcif_register_drv(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/satcan.h b/bsps/sparc/include/bsp/satcan.h new file mode 100644 index 0000000000..ab9f5e0cd4 --- /dev/null +++ b/bsps/sparc/include/bsp/satcan.h @@ -0,0 +1,142 @@ +/* + * Header file for RTEMS SATCAN FPGA driver + * + * COPYRIGHT (c) 2009. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SATCAN_H__ +#define __SATCAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Config structure passed to SatCAN_init(..) */ +typedef struct { + /* Configuration */ + int nodeno; + int dps; + /* Callback functions */ + void (*ahb_irq_callback)(void); + void (*pps_irq_callback)(void); + void (*m5_irq_callback)(void); + void (*m4_irq_callback)(void); + void (*m3_irq_callback)(void); + void (*m2_irq_callback)(void); + void (*m1_irq_callback)(void); + void (*sync_irq_callback)(void); + void (*can_irq_callback)(unsigned int fifo); +} satcan_config; + +#define SATCAN_HEADER_SIZE 4 +#define SATCAN_HEADER_NMM_POS 3 +#define SATCAN_PAYLOAD_SIZE 8 + +/* SatCAN message */ +typedef struct { + unsigned char header[SATCAN_HEADER_SIZE]; /* Header of SatCAN message */ + unsigned char payload[SATCAN_PAYLOAD_SIZE]; /* Payload of SatCAN message */ +} satcan_msg; + +/* SatCAN modify register structure */ +typedef struct { + unsigned int reg; + unsigned int val; +} satcan_regmod; + +/* Driver interface */ +int satcan_register(satcan_config *conf); + +/* SatCAN interrupt IDs */ +#define SATCAN_IRQ_NONACT_TO_ACT 0 +#define SATCAN_IRQ_ACTIVE_TO_NONACT 1 +#define SATCAN_IRQ_STR1_TO_DPS 2 +#define SATCAN_IRQ_DPS_TO_STR1 3 +#define SATCAN_IRQ_STR2_TO_DPS 4 +#define SATCAN_IRQ_DPS_TO_STR2 5 +#define SATCAN_IRQ_STR3_TO_DPS 6 +#define SATCAN_IRQ_DPS_TO_STR3 7 +#define SATCAN_IRQ_PLD1_TO_DPS 8 +#define SATCAN_IRQ_DPS_TO_PLD1 9 +#define SATCAN_IRQ_PLD2_TO_DPS 10 +#define SATCAN_IRQ_DPS_TO_PLD2 11 +#define SATCAN_IRQ_SYNC 16 +#define SATCAN_IRQ_TIME_MARKER1 17 +#define SATCAN_IRQ_TIME_MARKER2 18 +#define SATCAN_IRQ_TIME_MARKER3 19 +#define SATCAN_IRQ_TIME_MARKER4 20 +#define SATCAN_IRQ_TIME_MARKER5 21 +#define SATCAN_IRQ_EOD1 22 +#define SATCAN_IRQ_EOD2 23 +#define SATCAN_IRQ_TOD 24 +#define SATCAN_IRQ_CRITICAL 25 + +/* IOC */ +#define SATCAN_IOC_DMA_2K 1 /* Use DMA area for 2K messages */ +#define SATCAN_IOC_DMA_8K 2 /* Use DMA area for 8K messages */ +#define SATCAN_IOC_GET_REG 3 /* Provides direct read access to all core registers */ +#define SATCAN_IOC_SET_REG 4 /* Provides direct write access to all core registers */ +#define SATCAN_IOC_OR_REG 5 /* Provides direct read access to all core registers */ +#define SATCAN_IOC_AND_REG 6 /* Provides direct write access to all core registers */ +#define SATCAN_IOC_EN_TX1_DIS_TX2 7 /* Enable DMA TX channel 1, Disable DMA TX channel 2 */ +#define SATCAN_IOC_EN_TX2_DIS_TX1 8 /* Enable DMA TX channel 2, Disable DMA TX channel 1 */ +#define SATCAN_IOC_GET_DMA_MODE 9 /* Returns the current DMA mode */ +#define SATCAN_IOC_SET_DMA_MODE 10 /* Sets the DMA mode */ +#define SATCAN_IOC_ACTIVATE_DMA 11 /* Directly activate DMA channel */ +#define SATCAN_IOC_DEACTIVATE_DMA 12 /* Directly deactivate DMA channel */ +#define SATCAN_IOC_DMA_STATUS 13 /* Returns status of directly activated DMA */ +#define SATCAN_IOC_GET_DOFFSET 14 /* Get TX DMA offset */ +#define SATCAN_IOC_SET_DOFFSET 15 /* Set TX DMA offset */ +#define SATCAN_IOC_GET_TIMEOUT 16 /* Set TX DMA timeout */ +#define SATCAN_IOC_SET_TIMEOUT 17 /* Get TX DMA timeout */ + + +/* Values used to select core register with IOC_SET_REG/IOC_GET_REG */ +#define SATCAN_SWRES 0 /* Software reset */ +#define SATCAN_INT_EN 1 /* Interrupt enable */ +#define SATCAN_FIFO 3 /* FIFO read */ +#define SATCAN_FIFO_RES 4 /* FIFO reset */ +#define SATCAN_TSTAMP 5 /* Current time stamp */ +#define SATCAN_CMD0 6 /* Command register 0 */ +#define SATCAN_CMD1 7 /* Command register 1 */ +#define SATCAN_START_CTC 8 /* Start cycle time counter */ +#define SATCAN_RAM_BASE 9 /* RAM offset address */ +#define SATCAN_STOP_CTC 10 /* Stop cycle time counter / DPS active status */ +#define SATCAN_DPS_ACT 10 /* Stop cycle time counter / DPS active status */ +#define SATCAN_PLL_RST 11 /* DPLL reset */ +#define SATCAN_PLL_CMD 12 /* DPLL command */ +#define SATCAN_PLL_STAT 13 /* DPLL status */ +#define SATCAN_PLL_OFF 14 /* DPLL offset */ +#define SATCAN_DMA 15 /* DMA channel enable */ +#define SATCAN_DMA_TX_1_CUR 16 /* DMA channel 1 TX current address */ +#define SATCAN_DMA_TX_1_END 17 /* DMA channel 1 TX end address */ +#define SATCAN_DMA_TX_2_CUR 18 /* DMA channel 2 TX current address */ +#define SATCAN_DMA_TX_2_END 19 /* DMA channel 2 TX end address */ +#define SATCAN_RX 20 /* CAN RX enable / Filter start ID */ +#define SATCAN_FILTER_START 20 /* CAN RX enable / Filter start ID */ +#define SATCAN_FILTER_SETUP 21 /* Filter setup / Filter stop ID */ +#define SATCAN_FILTER_STOP 21 /* Filter setup / Filter stop ID */ +#define SATCAN_WCTRL 32 /* Wrapper status/control register */ +#define SATCAN_WIPEND 33 /* Wrapper interrupt pending register */ +#define SATCAN_WIMASK 34 /* Wrapper interrupt mask register */ +#define SATCAN_WAHBADDR 35 /* Wrapper AHB address register */ + + +/* Values used to communicate DMA mode */ +#define SATCAN_DMA_MODE_USER 0 +#define SATCAN_DMA_MODE_SYSTEM 1 + +/* Values used to directly activate DMA channel */ +#define SATCAN_DMA_ENABLE_TX1 1 +#define SATCAN_DMA_ENABLE_TX2 2 + +#ifdef __cplusplus +} +#endif + +#endif /* __SATCAN_H__ */ diff --git a/bsps/sparc/include/bsp/spictrl.h b/bsps/sparc/include/bsp/spictrl.h new file mode 100644 index 0000000000..98922fbd30 --- /dev/null +++ b/bsps/sparc/include/bsp/spictrl.h @@ -0,0 +1,126 @@ +/* + * SPICTRL SPI Driver interface. + * + * COPYRIGHT (c) 2009. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SPICTRL_H__ +#define __SPICTRL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void spictrl_register_drv (void); + +/*** REGISTER LAYOUT ***/ +struct spictrl_regs { + volatile unsigned int capability; /* 0x00 */ + volatile unsigned int resv[7]; /* 0x04 */ + volatile unsigned int mode; /* 0x20 */ + volatile unsigned int event; /* 0x24 */ + volatile unsigned int mask; /* 0x28 */ + volatile unsigned int command; /* 0x2c */ + volatile unsigned int tx; /* 0x30 */ + volatile unsigned int rx; /* 0x34 */ + volatile unsigned int slvsel; /* 0x38 */ + volatile unsigned int am_slvsel; /* 0x3c */ + volatile unsigned int am_cfg; /* 0x40 */ + volatile unsigned int am_period; /* 0x44 */ + int reserved0[2]; + volatile unsigned int am_mask[4]; /* 0x50-0x5C */ + int reserved1[(0x200-0x60)/4]; + volatile unsigned int am_tx[128]; /* 0x200-0x3FC */ + volatile unsigned int am_rx[128]; /* 0x400-0x5FC */ +}; + +/* -- About automated periodic transfer mode -- + * + * Core must support this feature. + * + * The SPI core must be configured in periodic mode before + * writing the data into the transfer FIFO which will be used + * mutiple times in different transfers, it will also make + * the receive FIFO to be updated. + * + * In periodic mode the following sequence is performed, + * 1. start() + * 2. ioctl(CONFIG, &config) - Enable periodic mode + * 3. set_address() + * 4. write() - Fills TX FIFO, this has some constraints + * 5. ioctl(START) - Starts the periodic transmission of the TX FIFO + * 6. read() - Read one response of the tranistted data. It will + * hang until data is available. If hanging is not an + * options use ioctl(STATUS) + * 7. go back to 6. + * + * 8. ioctl(STOP) - Stop to set up a new periodic or normal transfer + * 9. stop() + * + * Note that the the read length must equal the total write length. + */ + +/* Custom SPICTRL driver ioctl commands */ +#define SPICTRL_IOCTL_PERIOD_START 5000 /* Start automated periodic transfer mode */ +#define SPICTRL_IOCTL_PERIOD_STOP 5001 /* Stop to SPI core from doing periodic transfers */ +#define SPICTRL_IOCTL_CONFIG 5002 /* Configure Periodic transfer mode (before calling write() and START) */ +#define SPICTRL_IOCTL_STATUS 5003 /* Get status */ + +#define SPICTRL_IOCTL_PERIOD_READ 5005 /* Write transmit registers and mask register + * (only in automatic periodic mode) + * Note that it is probably prefferred to read + * the received words using the read() using + * operations instead. + */ +#define SPICTRL_IOCTL_PERIOD_WRITE 5006 /* Read receive registers and mask register + * (only in automatic periodic mode) */ +#define SPICTRL_IOCTL_REGS 5007 /* Get SPICTRL Register */ + +/* SPICTRL_IOCTL_CONFIG argument */ +struct spictrl_ioctl_config { + int clock_gap; /* Clock GAP between */ + unsigned int flags; /* Normal mode flags */ + int periodic_mode; /* 1=Enables Automated periodic transfers if supported by hardware */ + unsigned int period; /* Number of clocks between automated transfers are started */ + unsigned int period_flags; /* Options */ + unsigned int period_slvsel; /* Slave Select when transfer is not active, default is 0xffffffff */ +}; +#define SPICTRL_FLAGS_TAC 0x10 + +#define SPICTRL_PERIOD_FLAGS_ERPT 0x80 /* Trigger start-period from external signal */ +#define SPICTRL_PERIOD_FLAGS_SEQ 0x40 +#define SPICTRL_PERIOD_FLAGS_STRICT 0x20 +#define SPICTRL_PERIOD_FLAGS_OVTB 0x10 +#define SPICTRL_PERIOD_FLAGS_OVDB 0x08 +#define SPICTRL_PERIOD_FLAGS_ASEL 0x04 +#define SPICTRL_PERIOD_FLAGS_EACT 0x01 + +/* SPICTRL_IOCTL_PERIOD_READ and SPICTRL_IOCTL_PERIOD_WRITE Argument data structure + * + * Note that the order of reading the mask registers are different for read/write + * operation. See options notes. + */ +struct spictrl_period_io { + int options; /* READ: bit0=Read Mask Registers into masks[]. + * bit1=Read Receive registers according to masks[] + * (after reading masks). + * + * WRITE: bit0=Update Mask accoring to masks[]. + * bit1=Update Transmit registers according to masks[]. + * (before reading masks) + */ + unsigned int masks[4]; + + void *data; /* Data read sequentially according to masks[] bit. */ +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/bsp/spwcuc.h b/bsps/sparc/include/bsp/spwcuc.h new file mode 100644 index 0000000000..e420367640 --- /dev/null +++ b/bsps/sparc/include/bsp/spwcuc.h @@ -0,0 +1,188 @@ +/* SPWCUC - SpaceWire - CCSDS unsegmented Code Transfer Protocol GRLIB core + * register driver interface. + * + * COPYRIGHT (c) 2009. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SPWCUC_H__ +#define __SPWCUC_H__ + +#define PKT_INIT_IRQ 0x1 +#define PKT_ERR_IRQ 0x2 +#define PKT_RX_IRQ 0x4 +#define WRAP_ERR_IRQ 0x8 +#define WRAP_IRQ 0x10 +#define SYNC_ERR_IRQ 0x20 +#define SYNC_IRQ 0x40 +#define TOL_ERR_IRQ 0x80 +#define TICK_RX_ERR_IRQ 0x100 +#define TICK_RX_WRAP_IRQ 0x200 +#define TICK_RX_IRQ 0x400 +#define TICK_TX_WRAP_IRQ 0x800 +#define TICK_TX_IRQ 0x1000 + +/* SPWCUC Register layout */ +struct spwcuc_regs { + volatile unsigned int config; /* 00 */ + volatile unsigned int status; /* 04 */ + volatile unsigned int control; /* 08 */ + volatile unsigned int unused0; /* 0c */ + volatile unsigned int dla; /* 10 */ + volatile unsigned int pid; /* 14 */ + volatile unsigned int offset; /* 18 */ + volatile unsigned int unused1; /* 1c */ + volatile unsigned int pkt_ct; /* 20 */ + volatile unsigned int pkt_ft; /* 24 */ + volatile unsigned int pkt_pf_crc; /* 28 */ + volatile unsigned int unused2; /* 2c */ + volatile unsigned int etct; /* 30 */ + volatile unsigned int etft; /* 34 */ + volatile unsigned int etct_next; /* 38 */ + volatile unsigned int etft_next; /* 3c */ + volatile unsigned int unused3[8]; /* 40-5c */ + volatile unsigned int pimsr; /* 60 */ + volatile unsigned int pimr; /* 64 */ + volatile unsigned int pisr; /* 68 */ + volatile unsigned int pir; /* 6c */ + volatile unsigned int imr; /* 70 */ + volatile unsigned int picr; /* 74 */ +}; + +struct spwcuc_cfg { + unsigned char sel_out; /* Bits 3-0 enable time code transmission on respective output */ + unsigned char sel_in; /* Select SpW to receive time codes on, 0-3 */ + unsigned char mapping; /* Define mapping of time code time info into T-field, 0-31 */ + unsigned char tolerance; /* Define SpaceWire time code reception tolerance, 0-31 */ + unsigned char tid; /* Define CUC P-Field time code identification, 1 = Level 1, 2 = Level 2 */ + unsigned char ctf; /* If 1 check time code flags to be all zero */ + unsigned char cp; /* If 1 check P-Field time code id against tid */ + + unsigned char txen; /* Enable SpaceWire time code transmission */ + unsigned char rxen; /* Enable SpaceWire time code reception */ + unsigned char pktsyncen; /* Enable SpaceWire time CUC packet sync */ + unsigned char pktiniten; /* Enable SpaceWire time CUC packet init */ + unsigned char pktrxen; /* Enable SpaceWire time CUC packet reception */ + + unsigned char dla; /* SpaceWire destination logical address */ + unsigned char dla_mask; /* SpaceWire destination logical address mask */ + unsigned char pid; /* SpaceWire protocol ID */ + + unsigned int offset; /* Packet reception offset */ +}; + +/* SPWCUC Statistics gathered by driver */ +struct spwcuc_stats { + + /* IRQ Stats */ + unsigned int nirqs; + unsigned int tick_tx; + unsigned int tick_tx_wrap; + unsigned int tick_rx; + unsigned int tick_rx_wrap; + unsigned int tick_rx_error; + unsigned int tolerr; + unsigned int sync; + unsigned int syncerr; + unsigned int wrap; + unsigned int wraperr; + unsigned int pkt_rx; + unsigned int pkt_err; + unsigned int pkt_init; +}; + +/* Function ISR callback prototype + * + * pimr - PIMR/PIR register of the SPWCUC core read by ISR + * data - Custom data provided by user + */ +typedef void (*spwcuc_isr_t)(unsigned int pimr, void *data); + +/* Open a SPWCUC device by minor number. A SPWCUC device can only by opened + * once. The handle returned must be used as the input parameter 'spwcuc' in + * the rest of the calls in the function interface. + */ +extern void *spwcuc_open(int minor); + +/* Close a previously opened SPWCUC device */ +extern void spwcuc_close(void *spwcuc); + +/* Reset SPWCUC Core */ +extern int spwcuc_reset(void *spwcuc); + +/* Enable Interrupts at Interrupt controller */ +extern void spwcuc_int_enable(void *spwcuc); + +/* Disable Interrupts at Interrupt controller */ +extern void spwcuc_int_disable(void *spwcuc); + +/* Clear Statistics gathered by the driver */ +extern void spwcuc_clr_stats(void *spwcuc); + +/* Get Statistics gathered by the driver. The statistics are stored into + * the location pointed to by 'stats'. + */ +extern void spwcuc_get_stats(void *spwcuc, struct spwcuc_stats *stats); + +/* Register an Interrupt handler and custom data, the function call is + * removed by setting func to NULL. + * + * The driver's interrupt handler is installed on open(), however the user + * callback called from the driver's ISR is installed using this function. + */ +extern void spwcuc_int_register(void *spwcuc, spwcuc_isr_t func, void *data); + +/* Configure the spwcuc core. The configuration is taken from the data + * structure pointed to by 'cfg'. See data structure spwcuc_cfg fields. + */ +extern void spwcuc_config(void *spwcuc, struct spwcuc_cfg *cfg); + +/* Return elapsed coarse time */ +extern unsigned int spwcuc_get_et_coarse(void *spwcuc); + +/* Return elapsed fine time */ +extern unsigned int spwcuc_get_et_fine(void *spwcuc); + +/* Return elapsed time (coarse and fine) 64-bit value */ +extern unsigned long long spwcuc_get_et(void *spwcuc); + +/* Return next elapsed coarse time (for use when sending SpW time packet) */ +extern unsigned int spwcuc_get_next_et_coarse(void *spwcuc); + +/* Return next elapsed fine time (for use when sending SpW time packet) */ +extern unsigned int spwcuc_get_next_et_fine(void *spwcuc); + +/* Return next elapsed time (for use when sending SpW time packet) */ +extern unsigned long long spwcuc_get_next_et(void *spwcuc); + +/* Force/Set the elapsed time (coarse 32-bit and fine 24-bit) by writing the + * T-Field Time Packet Registers then the FORCE bit. + */ +extern void spwcuc_force_et(void *spwcuc, unsigned long long time); + +/* Return received (from time packet) elapsed coarse time */ +extern unsigned int spwcuc_get_tp_et_coarse(void *spwcuc); + +/* Return received (from time packet) elapsed fine time */ +extern unsigned int spwcuc_get_tp_et_fine(void *spwcuc); + +/* Return received (from time packet) elapsed time (coarse and fine) */ +extern unsigned long long spwcuc_get_tp_et(void *spwcuc); + +/* Clear interrupts */ +extern void spwcuc_clear_irqs(void *spwcuc, int irqs); + +/* Enable interrupts */ +extern void spwcuc_enable_irqs(void *spwcuc, int irqs); + +/* Get Register */ +extern struct spwcuc_regs *spwcuc_get_regs(void *spwcuc); + +/* Register the SPWCUC Driver to the Driver Manager */ +extern void spwcuc_register(void); + +#endif diff --git a/bsps/sparc/include/bsp/tlib.h b/bsps/sparc/include/bsp/tlib.h new file mode 100644 index 0000000000..debb8c8215 --- /dev/null +++ b/bsps/sparc/include/bsp/tlib.h @@ -0,0 +1,202 @@ +/* + * Timer Library (TLIB) + * + * The Library rely on timer drivers, the timer presented by the + * timer driver must look like a down-counter timer, which generates + * interrupt (if configured) when underflown. + * + * If Timer hardware is an up-counter the Timer driver must recalculate + * into values that would match as if it was a down-counter. + * + * COPYRIGHT (c) 2011. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __TLIB_H__ +#define __TLIB_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +struct tlib_dev; + +typedef void (*tlib_isr_t)(void *data); + +enum { + TLIB_FLAGS_BROADCAST = 0x01 +}; + +struct tlib_drv { + /*** Functions ***/ + void (*reset)(struct tlib_dev *hand); + void (*get_freq)( + struct tlib_dev *hand, + unsigned int *basefreq, + unsigned int *tickrate); + int (*set_freq)(struct tlib_dev *hand, unsigned int tickrate); + void (*irq_reg)(struct tlib_dev *hand, tlib_isr_t func, void *data, int flags); + void (*irq_unreg)(struct tlib_dev *hand, tlib_isr_t func,void *data); + void (*start)(struct tlib_dev *hand, int once); + void (*stop)(struct tlib_dev *hand); + void (*restart)(struct tlib_dev *hand); + void (*get_counter)(struct tlib_dev *hand, unsigned int *counter); + int (*custom)(struct tlib_dev *hand, int cmd, void *arg); + int (*int_pend)(struct tlib_dev *hand, int ack); + void (*get_widthmask)(struct tlib_dev *hand, unsigned int *widthmask); +}; + +struct tlib_dev { + struct tlib_dev *next; + char status; /* 0=closed, 1=open, 2=timer started */ + char index; /* Timer Index */ + tlib_isr_t isr_func; + void *isr_data; + struct tlib_drv *drv; +}; + +#ifdef RTEMS_DRVMGR_STARTUP +/* Clock Driver Timer register function. Only used when the TLIB-Clock + * driver is used. A specific Timer is registered as the System Clock + * timer. + */ +extern void Clock_timer_register(int timer_number); +#endif + +/* Register Timer. Called by Timer Drivers in order to register + * a Timer to the Timer Library. The registration order determines + * the Timer Number used in tlib_open() to identify a specific + * Timer. + */ +extern int tlib_dev_reg(struct tlib_dev *newdev); + +/* Allocate a Timer. + * + * A Timer handle is returned identifying the timer in later calls. + */ +extern void *tlib_open(int timer_no); + +/* Close Timer */ +extern void tlib_close(void *hand); + +/* Returns Number of Timers currently registered to Timer Library */ +extern int tlib_ntimer(void); + +static inline void tlib_reset(void *hand) +{ + struct tlib_dev *dev = hand; + + dev->drv->reset(dev); +} +/* Get Frequencies: + * - Base Frequency (unchangable base freq rate of timer, prescaler, clkinput) + * - Current Tick Rate [in multiples of Base Frequency] + */ +static inline void tlib_get_freq( + void *hand, + unsigned int *basefreq, + unsigned int *tickrate) +{ + struct tlib_dev *dev = hand; + + dev->drv->get_freq(dev, basefreq, tickrate); +} + +/* Set current Tick Rate in number of "Base-Frequency ticks" */ +static inline int tlib_set_freq(void *hand, unsigned int tickrate) +{ + struct tlib_dev *dev = hand; + + return dev->drv->set_freq(dev, tickrate); +} + +/* Register ISR at Timer ISR */ +static inline void tlib_irq_unregister(void *hand) +{ + struct tlib_dev *dev = hand; + + if ( dev->isr_func ) { + dev->drv->irq_unreg(dev, dev->isr_func, dev->isr_data); + dev->isr_func = NULL; + } +} + +/* Register ISR at Timer ISR */ +static inline void tlib_irq_register(void *hand, tlib_isr_t func, void *data, int flags) +{ + struct tlib_dev *dev = hand; + + /* Unregister previous ISR if installed */ + tlib_irq_unregister(hand); + dev->isr_func = func; + dev->isr_data = data; + dev->drv->irq_reg(dev, func, data, flags); +} + +/* Start Timer, ISRs will be generated if enabled. + * + * once determines if timer should restart (=0) on underflow automatically, + * or stop when underflow is reached (=1). + */ +static inline void tlib_start(void *hand, int once) +{ + struct tlib_dev *dev = hand; + + dev->drv->start(dev, once); +} + +/* Stop Timer, no more ISRs will be generated */ +static inline void tlib_stop(void *hand) +{ + struct tlib_dev *dev = hand; + + dev->drv->stop(dev); +} + +/* Restart/Reload Timer, may be usefull if a Watchdog Timer */ +static inline void tlib_restart(void *hand) +{ + struct tlib_dev *dev = hand; + + dev->drv->restart(dev); +} + +/* Get current counter value (since last tick) */ +static inline void tlib_get_counter(void *hand, unsigned int *counter) +{ + struct tlib_dev *dev = hand; + + dev->drv->get_counter(dev, counter); +} + +/* Do a custom operation */ +static inline void tlib_custom(void *hand, int cmd, void *arg) +{ + struct tlib_dev *dev = hand; + + dev->drv->custom(dev, cmd, arg); +} + +static inline int tlib_interrupt_pending(void *hand, int ack) +{ + struct tlib_dev *dev = hand; + + return dev->drv->int_pend(dev, ack); +} + +static inline void tlib_get_widthmask(void *hand, unsigned int *widthmask) +{ + struct tlib_dev *dev = hand; + + dev->drv->get_widthmask(dev, widthmask); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/drvmgr/ambapp_bus.h b/bsps/sparc/include/drvmgr/ambapp_bus.h new file mode 100644 index 0000000000..d034aae3a3 --- /dev/null +++ b/bsps/sparc/include/drvmgr/ambapp_bus.h @@ -0,0 +1,142 @@ +/* General part of a AMBA Plug & Play bus driver. + * + * COPYRIGHT (c) 2008. + * Cobham Gaisler AB. + * + * This is the general part of the different AMBA Plug & Play + * drivers. The drivers are wrappers around this driver, making + * the code size smaller for systems with multiple AMBA Plug & + * Play buses. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __AMBAPP_BUS_H__ +#define __AMBAPP_BUS_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* GRLIB AMBA Plug&Play Driver ID generation */ +#define DRIVER_AMBAPP_ID(vendor, device) \ + DRIVER_ID(DRVMGR_BUS_TYPE_AMBAPP, ((((vendor) & 0xff) << 16) | ((device) & 0xfff))) + +/*** Gaisler Hardware Device Driver IDs ***/ +#define DRIVER_AMBAPP_GAISLER_AHBSTAT_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_AHBSTAT) +#define DRIVER_AMBAPP_GAISLER_APBUART_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_APBUART) +#define DRIVER_AMBAPP_GAISLER_B1553BRM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_B1553BRM) +#define DRIVER_AMBAPP_GAISLER_B1553RT_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_B1553RT) +#define DRIVER_AMBAPP_GAISLER_GPTIMER_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GPTIMER) +#define DRIVER_AMBAPP_GAISLER_GR1553B_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GR1553B) +#define DRIVER_AMBAPP_GAISLER_GRADCDAC_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRADCDAC) +#define DRIVER_AMBAPP_GAISLER_GRAES_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRAESDMA) +#define DRIVER_AMBAPP_GAISLER_GRCAN_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRCAN) +#define DRIVER_AMBAPP_GAISLER_GRCTM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRCTM) +#define DRIVER_AMBAPP_GAISLER_GRETH_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_ETHMAC) +#define DRIVER_AMBAPP_GAISLER_GRGPIO_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GPIO) +#define DRIVER_AMBAPP_GAISLER_GRPCI2_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRPCI2) +#define DRIVER_AMBAPP_GAISLER_GRIOMMU_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRIOMMU) +#define DRIVER_AMBAPP_GAISLER_GRPCI_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PCIFBRG) +#define DRIVER_AMBAPP_GAISLER_GRPWM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRPWM) +#define DRIVER_AMBAPP_GAISLER_GRPWRX_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PW2APB) +#define DRIVER_AMBAPP_GAISLER_GRSPW_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPW) +#define DRIVER_AMBAPP_GAISLER_GRSPW2_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPW2) +#define DRIVER_AMBAPP_GAISLER_GRTC_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRTC) +#define DRIVER_AMBAPP_GAISLER_GRTM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRTM) +#define DRIVER_AMBAPP_GAISLER_I2CMST_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_I2CMST) +#define DRIVER_AMBAPP_GAISLER_OCCAN_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_CANAHB) +#define DRIVER_AMBAPP_GAISLER_PCIF_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PCIF) +#define DRIVER_AMBAPP_GAISLER_PCITRACE_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PCITRACE) +#define DRIVER_AMBAPP_GAISLER_SPICTRL_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPICTRL) +#define DRIVER_AMBAPP_GAISLER_SPWCUC_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPWCUC) +#define DRIVER_AMBAPP_GAISLER_SPW_ROUTER_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPW_ROUTER) +#define DRIVER_AMBAPP_GAISLER_L2CACHE_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_L2CACHE) +#define DRIVER_AMBAPP_GAISLER_MEMSCRUB_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_MEMSCRUB) +#define DRIVER_AMBAPP_GAISLER_L4STAT_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_L4STAT) + +/*** ESA Hardware Device Driver IDs ***/ +#define DRIVER_AMBAPP_ESA_MCTRL_ID DRIVER_AMBAPP_ID(VENDOR_ESA, ESA_MCTRL) +#define DRIVER_AMBAPP_MCTRL_ID DRIVER_AMBAPP_ESA_MCTRL_ID + +struct amba_dev_id { + unsigned short vendor; + unsigned short device; + /* Version ? */ +}; + +struct amba_drv_info { + struct drvmgr_drv general; /* General bus info */ + /* AMBA specific bus information */ + struct amba_dev_id *ids; /* Supported hardware */ +}; + +struct amba_dev_info { + struct amba_dev_id id; + struct ambapp_core info; +}; + +struct ambapp_ops { + int (*int_register) + (struct drvmgr_dev *dev, int index, const char *info, drvmgr_isr isr, void *arg); + int (*int_unregister) + (struct drvmgr_dev *dev, int index, drvmgr_isr isr, void *arg); + int (*int_clear)(struct drvmgr_dev *dev, int index); + int (*int_mask)(struct drvmgr_dev *dev, int index); + int (*int_unmask)(struct drvmgr_dev *dev, int index); +#ifdef RTEMS_SMP + int (*int_set_affinity)(struct drvmgr_dev *dev, int index, + const Processor_mask *cpus); +#endif + int (*get_params) + (struct drvmgr_dev *, struct drvmgr_bus_params *); +}; + +struct ambapp_config { + struct ambapp_bus *abus; /* Prescanned AMBA PnP bus */ + struct ambapp_ops *ops; /* AMBA bus operations */ + struct drvmgr_map_entry *maps_up; /* Bus memory map up-stream towards CPU */ + struct drvmgr_map_entry *maps_down; /* Bus memory map down-stream towards HW */ + struct drvmgr_bus_res *resources; /* Driver Resources */ + int bus_type; /* Set DRVMGR_BUS_TYPE_AMBAPP_DIST if distributed AMBA Bus */ + struct drvmgr_func *funcs; /* Custom functions */ +}; + +/*** Bus operations with READ/WRITE access operations *** + * + * The functions are implemented using the standard drvmgr RW interface + */ +#define AMBAPP_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_REG) +#define AMBAPP_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_REG) +#define AMBAPP_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_REG) +#define AMBAPP_R64 DRVMGR_RWFUNC(RW_SIZE_8|RW_READ|RW_REG) +#define AMBAPP_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_REG) +#define AMBAPP_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_REG) +#define AMBAPP_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_REG) +#define AMBAPP_W64 DRVMGR_RWFUNC(RW_SIZE_8|RW_WRITE|RW_REG) +#define AMBAPP_RMEM DRVMGR_RWFUNC(RW_SIZE_ANY|RW_READ|RW_MEM) +#define AMBAPP_WMEM DRVMGR_RWFUNC(RW_SIZE_ANY|RW_WRITE|RW_MEM) +#define AMBAPP_MEMSET DRVMGR_RWFUNC(RW_SIZE_ANY|RW_SET|RW_MEM) +#define AMBAPP_RW_ARG DRVMGR_RWFUNC(RW_ARG) + +/* Register an ambapp bus on-top of a device */ +extern int ambapp_bus_register( + struct drvmgr_dev *dev, + struct ambapp_config *config + ); + +extern void ambapp_bus_freq_register( + struct drvmgr_dev *dev, + int amba_interface, + unsigned int freq_hz); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/drvmgr/ambapp_bus_grlib.h b/bsps/sparc/include/drvmgr/ambapp_bus_grlib.h new file mode 100644 index 0000000000..2def4bc2b4 --- /dev/null +++ b/bsps/sparc/include/drvmgr/ambapp_bus_grlib.h @@ -0,0 +1,36 @@ +/* LEON3 GRLIB AMBA Plug & Play bus driver interface. + * + * COPYRIGHT (c) 2008. + * Cobham Gaisler AB. + * + * This is driver is a wrapper for the general AMBA Plug & Play bus + * driver. This is the root bus driver for GRLIB systems. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __AMBAPP_BUS_GRLIB_H__ +#define __AMBAPP_BUS_GRLIB_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +struct grlib_config { + struct ambapp_bus *abus; + struct drvmgr_bus_res *resources; +}; + +/* Register GRLIB AMBA PnP Bus as root bus at driver manager */ +extern int ambapp_grlib_root_register(struct grlib_config *config); + +/* Register bus driver to Driver Manager */ +void ambapp_grlib_register(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/drvmgr/bspcommon.h b/bsps/sparc/include/drvmgr/bspcommon.h new file mode 100644 index 0000000000..d3470009f8 --- /dev/null +++ b/bsps/sparc/include/drvmgr/bspcommon.h @@ -0,0 +1,28 @@ +/* Common BSP/driver configuration routines. + * + * COPYRIGHT (c) 2015. + * Cobham Gaisler. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef __BSPCOMMON_H__ +#define __BSPCOMMON_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Count driver resource array length. Array must be terminated with a NULL */ +int get_resarray_count(struct drvmgr_bus_res **array); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/drvmgr/leon2_amba_bus.h b/bsps/sparc/include/drvmgr/leon2_amba_bus.h new file mode 100644 index 0000000000..ebb3a08486 --- /dev/null +++ b/bsps/sparc/include/drvmgr/leon2_amba_bus.h @@ -0,0 +1,95 @@ +/* LEON2 Hardcoded bus driver interface. + * + * COPYRIGHT (c) 2008. + * Cobham Gaisler AB. + * + * Bus driver for a hardcoded setup. LEON2 systems have some + * cores always present, here called "Standard Cores". In + * addtion to the standard cores there are often extra cores + * that can be defined using the "Custom Cores" mechanism. + * + * A Core is described by assigning a base register and + * IRQ0..IRQ15 using the leon2_core structure. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LEON2_AMBA_BUS_H__ +#define __LEON2_AMBA_BUS_H__ + +/*** Cores location and IRQs hardcoded ***/ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* LEON2 AMBA Driver ID generation */ +#define DRIVER_LEON2_AMBA(id) DRIVER_ID(DRVMGR_BUS_TYPE_LEON2_AMBA, id) + +/* LEON2 Cores (any unique 48-bit number will do) */ +#define LEON2_AMBA_NONE_ID 0 +#define LEON2_AMBA_TIMER_ID 1 +#define LEON2_AMBA_UART_ID 2 +#define LEON2_AMBA_GPIO_ID 3 +#define LEON2_AMBA_IRQCTRL_ID 4 + +#define LEON2_AMBA_AT697PCI_ID 100 +#define LEON2_AMBA_AMBAPP_ID 0xfff0 + +/* LEON2 driver IDs */ +#define DRIVER_LEON2_AMBA_TIMER DRIVER_LEON2_AMBA(LEON2_AMBA_TIMER_ID) +#define DRIVER_LEON2_AMBA_UART DRIVER_LEON2_AMBA(LEON2_AMBA_UART_ID) +#define DRIVER_LEON2_AMBA_AT697PCI DRIVER_LEON2_AMBA(LEON2_AMBA_AT697PCI_ID) +#define DRIVER_LEON2_AMBA_AMBAPP DRIVER_LEON2_AMBA(LEON2_AMBA_AMBAPP_ID) + +struct leon2_amba_dev_id { + unsigned short core_id; +}; + +#define EMPTY_LEON2_CORE {{LEON2_AMBA_NONE_ID}, NULL, NULL} +struct leon2_core { + struct leon2_amba_dev_id id; /* Core ID */ + char *name; /* Name of Core */ + struct drvmgr_key *keys; /* Core setup (location, IRQs) */ +}; + +struct leon2_bus { + struct leon2_core *std_cores; /* The LEON2 standard cores */ + struct leon2_core *custom_cores; /* Custom cores on the same bus */ + struct drvmgr_map_entry *maps_up; /* Memory map ip-stream */ + struct drvmgr_map_entry *maps_down; /* Memory map down-stream */ +}; + +extern struct leon2_core leon2_std_cores[]; + +/* Data structure drivers can access */ +struct leon2_amba_dev_info { + unsigned short core_id; /* Core ID */ + unsigned int reg_base; /* Register base */ + char irqs[16]; /* 16 irqs */ +}; + +struct leon2_amba_drv_info { + struct drvmgr_drv general; /* General bus info */ + /* AMBA specific bus information */ + struct leon2_amba_dev_id *ids; /* Supported hardware */ +}; + +/* Initialize LEON2 bus with a configuration + * bus_config - What cores, their location and irqs + * resources - Driver configuration for the cores specified bus_config + */ +int leon2_root_register( + struct leon2_bus *bus_config, + struct drvmgr_bus_res *resources); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/grlib.h b/bsps/sparc/include/grlib.h new file mode 100644 index 0000000000..a2d0877fb8 --- /dev/null +++ b/bsps/sparc/include/grlib.h @@ -0,0 +1,164 @@ +/** + * @file + * @ingroup amba + * @brief Common GRLIB AMBA Core Register definitions + */ + +/* + * COPYRIGHT (c) 2012 + * Aeroflex Gaisler + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __GRLIB_H__ +#define __GRLIB_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* ESA MEMORY CONTROLLER */ +struct mctrl_regs { + unsigned int mcfg1; + unsigned int mcfg2; + unsigned int mcfg3; +}; + +/* APB UART */ +struct apbuart_regs { + volatile unsigned int data; + volatile unsigned int status; + volatile unsigned int ctrl; + volatile unsigned int scaler; +}; + +/* IRQMP and IRQAMP interrupt controller timestamps */ +struct irqmp_timestamp_regs { + volatile unsigned int counter; /* 0x00 */ + volatile unsigned int control; /* 0x04 */ + volatile unsigned int assertion; /* 0x08 */ + volatile unsigned int ack; /* 0x0c */ +}; + +/* IRQMP and IRQAMP interrupt controllers */ +struct irqmp_regs { + volatile unsigned int ilevel; /* 0x00 */ + volatile unsigned int ipend; /* 0x04 */ + volatile unsigned int iforce; /* 0x08 */ + volatile unsigned int iclear; /* 0x0c */ + volatile unsigned int mpstat; /* 0x10 */ + volatile unsigned int bcast; /* 0x14 */ + volatile unsigned int notused02; /* 0x18 */ + volatile unsigned int wdgctrl; /* 0x1c */ + volatile unsigned int ampctrl; /* 0x20 */ + volatile unsigned int icsel[2]; /* 0x24,0x28 */ + volatile unsigned int notused13; /* 0x2c */ + volatile unsigned int notused20; /* 0x30 */ + volatile unsigned int notused21; /* 0x34 */ + volatile unsigned int notused22; /* 0x38 */ + volatile unsigned int notused23; /* 0x3c */ + volatile unsigned int mask[16]; /* 0x40 */ + volatile unsigned int force[16]; /* 0x80 */ + /* Extended IRQ registers */ + volatile unsigned int intid[16]; /* 0xc0 */ + volatile struct irqmp_timestamp_regs timestamp[16]; /* 0x100 */ + volatile unsigned int resetaddr[4]; /* 0x200 */ + volatile unsigned int resv0[12]; /* 0x210 - 0x23C */ + volatile unsigned int pboot; /* 0x240 */ + volatile unsigned int resv1[47]; /* 0x244 - 0x2FC */ + volatile unsigned int irqmap[8]; /* 0x300 - 0x31C */ + volatile unsigned int resv2[824]; /* 0x320 - 0x1000 */ +}; + +/* GPTIMER Timer instance */ +struct gptimer_timer_regs { + volatile unsigned int value; + volatile unsigned int reload; + volatile unsigned int ctrl; + volatile unsigned int notused; +}; + +#define GPTIMER_TIMER_CTRL_EN 0x00000001U +#define GPTIMER_TIMER_CTRL_RS 0x00000002U +#define GPTIMER_TIMER_CTRL_LD 0x00000004U +#define GPTIMER_TIMER_CTRL_IE 0x00000008U +#define GPTIMER_TIMER_CTRL_IP 0x00000010U +#define GPTIMER_TIMER_CTRL_CH 0x00000020U +#define GPTIMER_TIMER_CTRL_DH 0x00000040U + +/* GPTIMER common registers */ +struct gptimer_regs { + volatile unsigned int scaler_value; /* common timer registers */ + volatile unsigned int scaler_reload; + volatile unsigned int cfg; + volatile unsigned int notused; + struct gptimer_timer_regs timer[7]; +}; + +/* GRGPIO GPIO */ +struct grgpio_regs { + volatile unsigned int data; /* 0x00 I/O port data register */ + volatile unsigned int output; /* 0x04 I/O port output register */ + volatile unsigned int dir; /* 0x08 I/O port direction register */ + volatile unsigned int imask; /* 0x0C Interrupt mask register */ + volatile unsigned int ipol; /* 0x10 Interrupt polarity register */ + volatile unsigned int iedge; /* 0x14 Interrupt edge register */ + volatile unsigned int bypass; /* 0x18 Bypass register */ + volatile unsigned int cap; /* 0x1C Capability register */ + volatile unsigned int irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */ + volatile unsigned int res_30; /* 0x30 Reserved */ + volatile unsigned int res_34; /* 0x34 Reserved */ + volatile unsigned int res_38; /* 0x38 Reserved */ + volatile unsigned int res_3C; /* 0x3C Reserved */ + volatile unsigned int iavail; /* 0x40 Interrupt available register */ + volatile unsigned int iflag; /* 0x44 Interrupt flag register */ + volatile unsigned int res_48; /* 0x48 Reserved */ + volatile unsigned int pulse; /* 0x4C Pulse register */ + volatile unsigned int res_50; /* 0x50 Reserved */ + volatile unsigned int output_or; /* 0x54 I/O port output register, logical-OR */ + volatile unsigned int dir_or; /* 0x58 I/O port direction register, logical-OR */ + volatile unsigned int imask_or; /* 0x5C Interrupt mask register, logical-OR */ + volatile unsigned int res_60; /* 0x60 Reserved */ + volatile unsigned int output_and; /* 0x64 I/O port output register, logical-AND */ + volatile unsigned int dir_and; /* 0x68 I/O port direction register, logical-AND */ + volatile unsigned int imask_and; /* 0x6C Interrupt mask register, logical-AND */ + volatile unsigned int res_70; /* 0x70 Reserved */ + volatile unsigned int output_xor; /* 0x74 I/O port output register, logical-XOR */ + volatile unsigned int dir_xor; /* 0x78 I/O port direction register, logical-XOR */ + volatile unsigned int imask_xor; /* 0x7C Interrupt mask register, logical-XOR */ +}; + +/* L2C - Level 2 Cache Controller registers */ +struct l2c_regs { + volatile unsigned int control; /* 0x00 Control register */ + volatile unsigned int status; /* 0x04 Status register */ + volatile unsigned int flush_mem_addr; /* 0x08 Flush (Memory address) */ + volatile unsigned int flush_set_index; /* 0x0c Flush (set, index) */ + volatile unsigned int access_counter; /* 0x10 */ + volatile unsigned int hit_counter; /* 0x14 */ + volatile unsigned int bus_cycle_counter; /* 0x18 */ + volatile unsigned int bus_usage_counter; /* 0x1c */ + volatile unsigned int error_status_control; /* 0x20 Error status/control */ + volatile unsigned int error_addr; /* 0x24 Error address */ + volatile unsigned int tag_check_bit; /* 0x28 TAG-check-bit */ + volatile unsigned int data_check_bit; /* 0x2c Data-check-bit */ + volatile unsigned int scrub_control_status; /* 0x30 Scrub Control/Status */ + volatile unsigned int scrub_delay; /* 0x34 Scrub Delay */ + volatile unsigned int error_injection; /* 0x38 Error injection */ + volatile unsigned int access_control; /* 0x3c Access control */ + volatile unsigned int reserved_40[16]; /* 0x40 Reserved */ + volatile unsigned int mtrr[32]; /* 0x80 - 0xFC MTRR registers */ + volatile unsigned int reserved_100[131008]; /* 0x100 Reserved */ + volatile unsigned int diag_iface_tag[16384]; /* 0x80000 - 0x8FFFC Diagnostic interface (Tag) */ + volatile unsigned int reserved_90000[376832]; /* 0x90000 Reserved */ + volatile unsigned int diag_iface_data[524288];/* 0x200000 - 0x3FFFFC Diagnostic interface (Data) */ +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/include/libcpu/access.h b/bsps/sparc/include/libcpu/access.h new file mode 100644 index 0000000000..cdf6b77122 --- /dev/null +++ b/bsps/sparc/include/libcpu/access.h @@ -0,0 +1,50 @@ +/* + * access.h - access routines for SPARC. SPARC is big endian only. + * + * COPYRIGHT (c) 2011 + * Aeroflex Gaisler. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_ACCESS_H +#define _LIBCPU_ACCESS_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* "Raw" access */ +extern uint8_t _ld8(uint8_t *addr); +extern void _st8(uint8_t *addr, uint8_t val); +extern uint16_t _ld16(uint16_t *addr); +extern void _st16(uint16_t *addr, uint16_t val); +extern uint32_t _ld32(uint32_t *addr); +extern void _st32(uint32_t *addr, uint32_t val); +extern uint64_t _ld64(uint64_t *addr); +extern void _st64(uint64_t *addr, uint64_t val); + +/* Aliases for Big Endian */ +extern uint16_t _ld_be16(uint16_t *addr); +extern void _st_be16(uint16_t *addr, uint16_t val); +extern uint32_t _ld_be32(uint32_t *addr); +extern void _st_be32(uint32_t *addr, uint32_t val); +extern uint64_t _ld_be64(uint64_t *addr); +extern void _st_be64(uint64_t *addr, uint64_t val); + +/* Little endian */ +extern uint16_t _ld_le16(uint16_t *addr); +extern void _st_le16(uint16_t *addr, uint16_t val); +extern uint32_t _ld_le32(uint32_t *addr); +extern void _st_le32(uint32_t *addr, uint32_t val); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/leon2/headers.am b/bsps/sparc/leon2/headers.am new file mode 100644 index 0000000000..73ae163778 --- /dev/null +++ b/bsps/sparc/leon2/headers.am @@ -0,0 +1,12 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/sparc/leon2/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/sparc/leon2/include/leon.h +include_HEADERS += ../../../../../../bsps/sparc/leon2/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/sparc/leon2/include/bsp/at697_pci.h +include_bsp_HEADERS += ../../../../../../bsps/sparc/leon2/include/bsp/irq.h diff --git a/bsps/sparc/leon2/include/bsp.h b/bsps/sparc/leon2/include/bsp.h new file mode 100644 index 0000000000..2028ba0db3 --- /dev/null +++ b/bsps/sparc/leon2/include/bsp.h @@ -0,0 +1,220 @@ +/** + * @file + * + * @ingroup sparc_leon2 + * + * @brief Global BSP Definitions. + */ + +/* bsp.h + * + * This include file contains all SPARC simulator definitions. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Ported to ERC32 implementation of the SPARC by On-Line Applications + * Research Corporation (OAR) under contract to the European Space + * Agency (ESA). + * + * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. + * European Space Agency. + */ + +#ifndef LIBBSP_SPARC_LEON2_BSP_H +#define LIBBSP_SPARC_LEON2_BSP_H + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup sparc_leon2 LEON2 Support + * + * @ingroup bsp_sparc + * + * @brief LEON2 Support Package + * + */ + +/* SPARC CPU variant: LEON2 */ +#define LEON2 1 + +/* + * BSP provides its own Idle thread body + */ +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_leon_open_eth_driver_attach( + struct rtems_bsdnet_ifconfig *config +); +extern int rtems_smc91111_driver_attach_leon2( + struct rtems_bsdnet_ifconfig *config +); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "open_eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_OPENETH \ + rtems_leon_open_eth_driver_attach +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_SMC91111 \ + rtems_smc91111_driver_attach_leon2 + +#define HAS_SMC91111 + +/* Configure GRETH driver */ +#define GRETH_SUPPORTED +#define GRETH_MEM_LOAD(addr) leon_r32_no_cache((uintptr_t) addr) + +/* + * The synchronous trap is an arbitrarily chosen software trap. + */ + +extern int CPU_SPARC_HAS_SNOOPING; + +/* Constants */ + +/* + * Information placed in the linkcmds file. + */ + +extern int RAM_START; +extern int RAM_END; +extern int RAM_SIZE; + +extern int PROM_START; +extern int PROM_END; +extern int PROM_SIZE; + +extern int CLOCK_SPEED; + +extern int end; /* last address in the program */ + +/* miscellaneous stuff assumed to exist */ + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +void BSP_fatal_exit(uint32_t error); + +void bsp_spurious_initialize( void ); + +/* Interrupt Service Routine (ISR) pointer */ +typedef void (*bsp_shared_isr)(void *arg); + +/* Initializes the Shared System Interrupt service */ +extern void BSP_shared_interrupt_init(void); + +/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */ +void bsp_isr_handler(rtems_vector_number vector); + +/* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple + * interrupt handlers may use the same IRQ number, all ISRs will be called + * when an interrupt on that line is fired. + * + * Arguments + * irq System IRQ number + * info Optional Name of IRQ source + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static __inline__ int BSP_shared_interrupt_register + ( + int irq, + const char *info, + bsp_shared_isr isr, + void *arg + ) +{ + return rtems_interrupt_handler_install(irq, info, + RTEMS_INTERRUPT_SHARED, isr, arg); +} + +/* Unregister previously registered shared IRQ handler. + * + * Arguments + * irq System IRQ number + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static __inline__ int BSP_shared_interrupt_unregister + ( + int irq, + bsp_shared_isr isr, + void *arg + ) +{ + return rtems_interrupt_handler_remove(irq, isr, arg); +} + +/* Clear interrupt pending on IRQ controller, this is typically done on a + * level triggered interrupt source such as PCI to avoid taking double IRQs. + * In such a case the interrupt source must be cleared first on LEON, before + * acknowledging the IRQ with this function. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_clear(int irq); + +/* Enable Interrupt. This function will unmask the IRQ at the interrupt + * controller. This is normally done by _register(). Note that this will + * affect all ISRs on this IRQ. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_unmask(int irq); + +/* Disable Interrupt. This function will mask one IRQ at the interrupt + * controller. This is normally done by _unregister(). Note that this will + * affect all ISRs on this IRQ. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_mask(int irq); + +/* + * Delay method + */ +void rtems_bsp_delay(int usecs); + +/* + * Prototypes for BSP methods that are used across file boundaries + */ +int cchip1_register(void); + +/* AT697 has PCI defined as big endian */ +#define BSP_PCI_BIG_ENDIAN + +/* Common driver build-time configurations. On small systems undefine + * [DRIVER]_INFO_AVAIL to avoid info routines get dragged in. It is good + * for debugging and printing information about the system, but makes the + * image bigger. + */ +#define AMBAPPBUS_INFO_AVAIL /* AMBAPP Bus driver */ +#define GPTIMER_INFO_AVAIL /* GPTIMER Timer driver */ +#define GRETH_INFO_AVAIL /* GRETH Ethernet driver */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/leon2/include/bsp/at697_pci.h b/bsps/sparc/leon2/include/bsp/at697_pci.h new file mode 100644 index 0000000000..9a511ec6f9 --- /dev/null +++ b/bsps/sparc/leon2/include/bsp/at697_pci.h @@ -0,0 +1,26 @@ +/* AT697 PCI host bridge driver + * + * COPYRIGHT (c) 2015. + * Cobham Gaisler. + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef __AT697PCI_H__ +#define __AT697PCI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register AT697 PCI host bridge driver to Driver Manager */ +void at697pci_register_drv(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/leon2/include/bsp/irq.h b/bsps/sparc/leon2/include/bsp/irq.h new file mode 100644 index 0000000000..086bf253c4 --- /dev/null +++ b/bsps/sparc/leon2/include/bsp/irq.h @@ -0,0 +1,28 @@ +/** + * @file + * @ingroup sparc_leon2 + * @brief Interrupts definitions + * + * Based on libbsp/shared/include/irq.h. + */ + +/* + * Copyright (c) 2012. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_LEON2_IRQ_CONFIG_H +#define LIBBSP_LEON2_IRQ_CONFIG_H + +#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX BSP_INTERRUPT_VECTOR_MAX_STD + +/* No extra check is needed */ +#undef BSP_INTERRUPT_CUSTOM_VALID_VECTOR + +#endif /* LIBBSP_LEON2_IRQ_CONFIG_H */ diff --git a/bsps/sparc/leon2/include/leon.h b/bsps/sparc/leon2/include/leon.h new file mode 100644 index 0000000000..7ec6b1dcf9 --- /dev/null +++ b/bsps/sparc/leon2/include/leon.h @@ -0,0 +1,423 @@ +/** + * @defgroup leon1 Leon-1 Handler + * @ingroup sparc_leon2 + * + * @file + * @ingroup leon1 + * @brief Handlers Leon-1 + * + * This include file contains information pertaining to the LEON-1. + * The LEON-1 is a custom SPARC V7 implementation. + * This CPU has a number of on-board peripherals and + * was developed by the European Space Agency to target space applications. + * + * NOTE: Other than where absolutely required, this version currently + * supports only the peripherals and bits used by the basic board + * support package. This includes at least significant pieces of + * the following items: + * + * + UART Channels A and B + * + Real Time Clock + * + Memory Control Register + * + Interrupt Control + * + */ + +/* + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Ported to LEON implementation of the SPARC by On-Line Applications + * Research Corporation (OAR) under contract to the European Space + * Agency (ESA). + * + * LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995. + * European Space Agency. + */ + +#ifndef _INCLUDE_LEON_h +#define _INCLUDE_LEON_h + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Interrupt Sources + * + * The interrupt source numbers directly map to the trap type and to + * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, + * and the Interrupt Pending Registers. + */ + +#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR 1 +#define LEON_INTERRUPT_UART_2_RX_TX 2 +#define LEON_INTERRUPT_UART_1_RX_TX 3 +#define LEON_INTERRUPT_EXTERNAL_0 4 +#define LEON_INTERRUPT_EXTERNAL_1 5 +#define LEON_INTERRUPT_EXTERNAL_2 6 +#define LEON_INTERRUPT_EXTERNAL_3 7 +#define LEON_INTERRUPT_TIMER1 8 +#define LEON_INTERRUPT_TIMER2 9 +#define LEON_INTERRUPT_EMPTY1 10 +#define LEON_INTERRUPT_EMPTY2 11 +#define LEON_INTERRUPT_EMPTY3 12 +#define LEON_INTERRUPT_EMPTY4 13 +#define LEON_INTERRUPT_EMPTY5 14 +#define LEON_INTERRUPT_EMPTY6 15 + +#ifndef ASM + +/* + * Trap Types for on-chip peripherals + * + * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments + * + * NOTE: The priority level for each source corresponds to the least + * significant nibble of the trap type. + */ + +#define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) + +#define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) + +#define LEON_INT_TRAP( _trap ) \ + ( (_trap) >= LEON_TRAP_TYPE( LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR ) && \ + (_trap) <= LEON_TRAP_TYPE( LEON_INTERRUPT_EMPTY6 ) ) + +/* + * Structure for LEON memory mapped registers. + * + * Source: Section 6.1 - On-chip registers + * + * NOTE: There is only one of these structures per CPU, its base address + * is 0x80000000, and the variable LEON_REG is placed there by the + * linkcmds file. + */ + +typedef struct { + volatile unsigned int Memory_Config_1; + volatile unsigned int Memory_Config_2; + volatile unsigned int Edac_Control; + volatile unsigned int Failed_Address; + volatile unsigned int Memory_Status; + volatile unsigned int Cache_Control; + volatile unsigned int Power_Down; + volatile unsigned int Write_Protection_1; + volatile unsigned int Write_Protection_2; + volatile unsigned int Leon_Configuration; + volatile unsigned int dummy2; + volatile unsigned int dummy3; + volatile unsigned int dummy4; + volatile unsigned int dummy5; + volatile unsigned int dummy6; + volatile unsigned int dummy7; + volatile unsigned int Timer_Counter_1; + volatile unsigned int Timer_Reload_1; + volatile unsigned int Timer_Control_1; + volatile unsigned int Watchdog; + volatile unsigned int Timer_Counter_2; + volatile unsigned int Timer_Reload_2; + volatile unsigned int Timer_Control_2; + volatile unsigned int dummy8; + volatile unsigned int Scaler_Counter; + volatile unsigned int Scaler_Reload; + volatile unsigned int dummy9; + volatile unsigned int dummy10; + volatile unsigned int UART_Channel_1; + volatile unsigned int UART_Status_1; + volatile unsigned int UART_Control_1; + volatile unsigned int UART_Scaler_1; + volatile unsigned int UART_Channel_2; + volatile unsigned int UART_Status_2; + volatile unsigned int UART_Control_2; + volatile unsigned int UART_Scaler_2; + volatile unsigned int Interrupt_Mask; + volatile unsigned int Interrupt_Pending; + volatile unsigned int Interrupt_Force; + volatile unsigned int Interrupt_Clear; + volatile unsigned int PIO_Data; + volatile unsigned int PIO_Direction; + volatile unsigned int PIO_Interrupt; +} LEON_Register_Map; + +#endif + +/* + * The following constants are intended to be used ONLY in assembly + * language files. + * + * NOTE: The intended style of usage is to load the address of LEON REGS + * into a register and then use these as displacements from + * that register. + */ + +#ifdef ASM + +#define LEON_REG_MEMCFG1_OFFSET 0x00 +#define LEON_REG_MEMCFG2_OFFSET 0x04 +#define LEON_REG_EDACCTRL_OFFSET 0x08 +#define LEON_REG_FAILADDR_OFFSET 0x0C +#define LEON_REG_MEMSTATUS_OFFSET 0x10 +#define LEON_REG_CACHECTRL_OFFSET 0x14 +#define LEON_REG_POWERDOWN_OFFSET 0x18 +#define LEON_REG_WRITEPROT1_OFFSET 0x1C +#define LEON_REG_WRITEPROT2_OFFSET 0x20 +#define LEON_REG_LEONCONF_OFFSET 0x24 +#define LEON_REG_UNIMPLEMENTED_2_OFFSET 0x28 +#define LEON_REG_UNIMPLEMENTED_3_OFFSET 0x2C +#define LEON_REG_UNIMPLEMENTED_4_OFFSET 0x30 +#define LEON_REG_UNIMPLEMENTED_5_OFFSET 0x34 +#define LEON_REG_UNIMPLEMENTED_6_OFFSET 0x38 +#define LEON_REG_UNIMPLEMENTED_7_OFFSET 0x3C +#define LEON_REG_TIMERCNT1_OFFSET 0x40 +#define LEON_REG_TIMERLOAD1_OFFSET 0x44 +#define LEON_REG_TIMERCTRL1_OFFSET 0x48 +#define LEON_REG_WDOG_OFFSET 0x4C +#define LEON_REG_TIMERCNT2_OFFSET 0x50 +#define LEON_REG_TIMERLOAD2_OFFSET 0x54 +#define LEON_REG_TIMERCTRL2_OFFSET 0x58 +#define LEON_REG_UNIMPLEMENTED_8_OFFSET 0x5C +#define LEON_REG_SCALERCNT_OFFSET 0x60 +#define LEON_REG_SCALER_LOAD_OFFSET 0x64 +#define LEON_REG_UNIMPLEMENTED_9_OFFSET 0x68 +#define LEON_REG_UNIMPLEMENTED_10_OFFSET 0x6C +#define LEON_REG_UARTDATA1_OFFSET 0x70 +#define LEON_REG_UARTSTATUS1_OFFSET 0x74 +#define LEON_REG_UARTCTRL1_OFFSET 0x78 +#define LEON_REG_UARTSCALER1_OFFSET 0x7C +#define LEON_REG_UARTDATA2_OFFSET 0x80 +#define LEON_REG_UARTSTATUS2_OFFSET 0x84 +#define LEON_REG_UARTCTRL2_OFFSET 0x88 +#define LEON_REG_UARTSCALER2_OFFSET 0x8C +#define LEON_REG_IRQMASK_OFFSET 0x90 +#define LEON_REG_IRQPEND_OFFSET 0x94 +#define LEON_REG_IRQFORCE_OFFSET 0x98 +#define LEON_REG_IRQCLEAR_OFFSET 0x9C +#define LEON_REG_PIODATA_OFFSET 0xA0 +#define LEON_REG_PIODIR_OFFSET 0xA4 +#define LEON_REG_PIOIRQ_OFFSET 0xA8 +#define LEON_REG_SIM_RAM_SIZE_OFFSET 0xF4 +#define LEON_REG_SIM_ROM_SIZE_OFFSET 0xF8 + +#endif + +/* + * The following defines the bits in Memory Configuration Register 1. + */ + +#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 + +/* + * The following defines the bits in Memory Configuration Register 1. + */ + +#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 + + +/* + * The following defines the bits in the Timer Control Register. + */ + +#define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ + /* 0 = hold scalar and counter */ +#define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ + /* 0 = stop at 0 */ +#define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ + /* 0 = no function */ + +/* + * The following defines the bits in the UART Control Registers. + * + */ + +#define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ + +/* + * The following defines the bits in the LEON UART Status Registers. + */ + +#define LEON_REG_UART_STATUS_CLR 0x00000000 /* Clear all status bits */ +#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ +#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ +#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ +#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ +#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ +#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ +#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ +#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ + + +/* + * The following defines the bits in the LEON UART Status Registers. + */ + +#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ +#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ +#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ +#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ +#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ +#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ +#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ +#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ + +#ifndef ASM + +/* + * This is used to manipulate the on-chip registers. + * + * The following symbol must be defined in the linkcmds file and point + * to the correct location. + */ + +extern LEON_Register_Map LEON_REG; + +static __inline__ int bsp_irq_fixup(int irq) +{ + return irq; +} + +/* + * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, + * and the Interrupt Pending Registers. + * + * NOTE: For operations which are not atomic, this code disables interrupts + * to guarantee there are no intervening accesses to the same register. + * The operations which read the register, modify the value and then + * store the result back are vulnerable. + */ + +#define LEON_Clear_interrupt( _source ) \ + do { \ + LEON_REG.Interrupt_Clear = (1 << (_source)); \ + } while (0) + +#define LEON_Force_interrupt( _source ) \ + do { \ + LEON_REG.Interrupt_Force = (1 << (_source)); \ + } while (0) + +#define LEON_Is_interrupt_pending( _source ) \ + (LEON_REG.Interrupt_Pending & (1 << (_source))) + +#define LEON_Is_interrupt_masked( _source ) \ + (!(LEON_REG.Interrupt_Mask & (1 << (_source)))) + +#define LEON_Mask_interrupt( _source ) \ + do { \ + uint32_t _level; \ + \ + _level = sparc_disable_interrupts(); \ + LEON_REG.Interrupt_Mask &= ~(1 << (_source)); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +#define LEON_Unmask_interrupt( _source ) \ + do { \ + uint32_t _level; \ + \ + _level = sparc_disable_interrupts(); \ + LEON_REG.Interrupt_Mask |= (1 << (_source)); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +#define LEON_Disable_interrupt( _source, _previous ) \ + do { \ + uint32_t _level; \ + uint32_t _mask = 1 << (_source); \ + \ + _level = sparc_disable_interrupts(); \ + (_previous) = LEON_REG.Interrupt_Mask; \ + LEON_REG.Interrupt_Mask = _previous & ~_mask; \ + sparc_enable_interrupts( _level ); \ + (_previous) &= _mask; \ + } while (0) + +#define LEON_Restore_interrupt( _source, _previous ) \ + do { \ + uint32_t _level; \ + uint32_t _mask = 1 << (_source); \ + \ + _level = sparc_disable_interrupts(); \ + LEON_REG.Interrupt_Mask = \ + (LEON_REG.Interrupt_Mask & ~_mask) | (_previous); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +/* Make all SPARC BSPs have common macros for interrupt handling */ +#define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source) +#define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source) +#define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source) +#define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source) +#define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source) +#define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source) +#define BSP_Disable_interrupt(_source, _previous) \ + LEON_Disable_interrupt(_source, _prev) +#define BSP_Restore_interrupt(_source, _previous) \ + LEON_Restore_interrupt(_source, _previous) + +/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */ +#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \ + BSP_Is_interrupt_masked(_source) +#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \ + BSP_Unmask_interrupt(_source) +#define BSP_Cpu_Mask_interrupt(_source, _cpu) \ + BSP_Mask_interrupt(_source) +#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \ + BSP_Disable_interrupt(_source, _prev) +#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \ + BSP_Cpu_Restore_interrupt(_source, _previous) + +/* + * Each timer control register is organized as follows: + * + * D0 - Enable + * 1 = enable counting + * 0 = hold scaler and counter + * + * D1 - Counter Reload + * 1 = reload counter at zero and restart + * 0 = stop counter at zero + * + * D2 - Counter Load + * 1 = load counter with preset value + * 0 = no function + * + */ + +#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 +#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 + +#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 + +#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 +#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 + +#define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 +#define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 + +#define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 +#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 + +/* Load 32-bit word by forcing a cache-miss */ +static inline unsigned int leon_r32_no_cache(uintptr_t addr) +{ + unsigned int tmp; + __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr)); + return tmp; +} + +#endif /* !ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* !_INCLUDE_LEON_h */ + diff --git a/bsps/sparc/leon2/include/tm27.h b/bsps/sparc/leon2/include/tm27.h new file mode 100644 index 0000000000..0d28641b9b --- /dev/null +++ b/bsps/sparc/leon2/include/tm27.h @@ -0,0 +1,84 @@ +/** + * @file + * @ingroup sparc_leon2 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * COPYRIGHT (c) 2006. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: Since the interrupt code for the SPARC supports both synchronous + * and asynchronous trap handlers, support for testing with both + * is included. + */ + +#define SIS_USE_SYNCHRONOUS_TRAP 0 + +/* + * The synchronous trap is an arbitrarily chosen software trap. + */ + +#if (SIS_USE_SYNCHRONOUS_TRAP == 1) + +#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), TEST_VECTOR, 1 ); + +#define Cause_tm27_intr() \ + __asm__ volatile( "ta 0x10; nop " ); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +/* + * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. + */ + +#else /* use a regular asynchronous trap */ + +#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1 +#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) +#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1 +#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), TEST_VECTOR, 1 ); \ + set_vector( (handler), TEST_VECTOR2, 1 ); + +#define Cause_tm27_intr() \ + do { \ + LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \ + nop(); \ + nop(); \ + nop(); \ + } while (0) + +#define Clear_tm27_intr() \ + LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE ) + +#define Lower_tm27_intr() /* empty */ + +#endif + +#endif diff --git a/bsps/sparc/leon3/headers.am b/bsps/sparc/leon3/headers.am new file mode 100644 index 0000000000..755a89632d --- /dev/null +++ b/bsps/sparc/leon3/headers.am @@ -0,0 +1,13 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/sparc/leon3/include/amba.h +include_HEADERS += ../../../../../../bsps/sparc/leon3/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/sparc/leon3/include/leon.h +include_HEADERS += ../../../../../../bsps/sparc/leon3/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/sparc/leon3/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/sparc/leon3/include/bsp/watchdog.h diff --git a/bsps/sparc/leon3/include/amba.h b/bsps/sparc/leon3/include/amba.h new file mode 100644 index 0000000000..059b28ca07 --- /dev/null +++ b/bsps/sparc/leon3/include/amba.h @@ -0,0 +1,48 @@ +/** + * @file + * @defgroup amba AMBA Driver Handler + * @ingroup sparc_leon3 + * @brief AMBA Plag & Play Bus Driver Macros + */ + +/* + * AMBA Plag & Play Bus Driver Macros + * + * Macros used for AMBA Plug & Play bus scanning + * + * COPYRIGHT (c) 2004. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __AMBA_H__ +#define __AMBA_H__ + +#define LEON3_IO_AREA 0xfff00000 +#define LEON3_CONF_AREA 0xff000 +#define LEON3_AHB_SLAVE_CONF_AREA (1 << 11) + +#define LEON3_AHB_CONF_WORDS 8 +#define LEON3_APB_CONF_WORDS 2 +#define LEON3_AHB_MASTERS 64 +#define LEON3_AHB_SLAVES 64 +#define LEON3_APB_SLAVES 16 + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* The AMBA Plug&Play info of the bus that the LEON3 sits on */ +extern struct ambapp_bus ambapp_plb; + +#ifdef __cplusplus +} +#endif + +#endif /* __AMBA_H__ */ diff --git a/bsps/sparc/leon3/include/bsp.h b/bsps/sparc/leon3/include/bsp.h new file mode 100644 index 0000000000..3fda4edc66 --- /dev/null +++ b/bsps/sparc/leon3/include/bsp.h @@ -0,0 +1,250 @@ +/** + * @file + * + * @ingroup sparc_leon3 + * + * @brief Global BSP Definitions. + */ + +/* bsp.h + * + * This include file contains all SPARC simulator definitions. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Ported to ERC32 implementation of the SPARC by On-Line Applications + * Research Corporation (OAR) under contract to the European Space + * Agency (ESA). + * + * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. + * European Space Agency. + */ + +#ifndef LIBBSP_SPARC_LEON3_BSP_H +#define LIBBSP_SPARC_LEON3_BSP_H + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup sparc_leon3 LEON3 Support + * + * @ingroup bsp_sparc + * + * @brief LEON3 support package + * + */ + +/* SPARC CPU variant: LEON3 */ +#define LEON3 1 + +/* + * BSP provides its own Idle thread body + */ +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +/* Maximum supported APBUARTs by BSP */ +#define BSP_NUMBER_OF_TERMIOS_PORTS 8 + +/* Make sure maximum number of consoles fit in filesystem */ +#define BSP_MAXIMUM_DEVICES 8 + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_leon_open_eth_driver_attach( + struct rtems_bsdnet_ifconfig *config, + int attach +); +extern int rtems_smc91111_driver_attach_leon3( + struct rtems_bsdnet_ifconfig *config, + int attach +); +extern int rtems_leon_greth_driver_attach( + struct rtems_bsdnet_ifconfig *config, + int attach +); + +#define RTEMS_BSP_NETWORK_DRIVER_NAME_OPENETH "open_eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_OPENETH \ + rtems_leon_open_eth_driver_attach +#define RTEMS_BSP_NETWORK_DRIVER_NAME_SMC91111 "smc_eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_SMC91111 \ + rtems_smc91111_driver_attach_leon3 +#define RTEMS_BSP_NETWORK_DRIVER_NAME_GRETH "gr_eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_GRETH \ + rtems_leon_greth_driver_attach + +#ifndef RTEMS_BSP_NETWORK_DRIVER_NAME +#define RTEMS_BSP_NETWORK_DRIVER_NAME RTEMS_BSP_NETWORK_DRIVER_NAME_GRETH +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH RTEMS_BSP_NETWORK_DRIVER_ATTACH_GRETH +#endif + +#define HAS_SMC91111 + +/* Configure GRETH driver */ +#define GRETH_SUPPORTED +#define GRETH_MEM_LOAD(addr) leon_r32_no_cache((uintptr_t)addr) + +extern int CPU_SPARC_HAS_SNOOPING; + +/* Constants */ + +/* + * Information placed in the linkcmds file. + */ + +extern int RAM_START; +extern int RAM_END; +extern int RAM_SIZE; + +extern int PROM_START; +extern int PROM_END; +extern int PROM_SIZE; + +extern int CLOCK_SPEED; + +extern int end; /* last address in the program */ + +/* miscellaneous stuff assumed to exist */ + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +void BSP_fatal_exit(uint32_t error); + +void bsp_spurious_initialize( void ); + +/* + * Delay for the specified number of microseconds. + */ +void rtems_bsp_delay(int usecs); + +/* Interrupt Service Routine (ISR) pointer */ +typedef void (*bsp_shared_isr)(void *arg); + +/* Initializes the Shared System Interrupt service */ +extern void BSP_shared_interrupt_init(void); + +/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */ +void bsp_isr_handler(rtems_vector_number vector); + +/* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple + * interrupt handlers may use the same IRQ number, all ISRs will be called + * when an interrupt on that line is fired. + * + * Arguments + * irq System IRQ number + * info Optional Name of IRQ source + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static __inline__ int BSP_shared_interrupt_register + ( + int irq, + const char *info, + bsp_shared_isr isr, + void *arg + ) +{ + return rtems_interrupt_handler_install(irq, info, + RTEMS_INTERRUPT_SHARED, isr, arg); +} + +/* Unregister previously registered shared IRQ handler. + * + * Arguments + * irq System IRQ number + * isr Function pointer to the ISR + * arg Second argument to function isr + */ +static __inline__ int BSP_shared_interrupt_unregister + ( + int irq, + bsp_shared_isr isr, + void *arg + ) +{ + return rtems_interrupt_handler_remove(irq, isr, arg); +} + +/* Clear interrupt pending on IRQ controller, this is typically done on a + * level triggered interrupt source such as PCI to avoid taking double IRQs. + * In such a case the interrupt source must be cleared first on LEON, before + * acknowledging the IRQ with this function. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_clear(int irq); + +/* Enable Interrupt. This function will unmask the IRQ at the interrupt + * controller. This is normally done by _register(). Note that this will + * affect all ISRs on this IRQ. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_unmask(int irq); + +/* Disable Interrupt. This function will mask one IRQ at the interrupt + * controller. This is normally done by _unregister(). Note that this will + * affect all ISRs on this IRQ. + * + * Arguments + * irq System IRQ number + */ +extern void BSP_shared_interrupt_mask(int irq); + +#if defined(RTEMS_SMP) || defined(RTEMS_MULTIPROCESSING) +/* Irq used by the shared memory driver and for inter-processor interrupts. + * The variable is weakly linked. Redefine the variable in your application + * to override the BSP default. + */ +extern const unsigned char LEON3_mp_irq; +#endif + +#ifdef RTEMS_SMP +/* Weak table used to implement static interrupt CPU affinity in a SMP + * configuration. The array index is the interrupt to be looked up, and + * the array[INTERRUPT] content is the CPU number relative to boot CPU + * index that will be servicing the interrupts from the IRQ source. The + * default is to let the first CPU (the boot cpu) to handle all + * interrupts (all zeros). + */ +extern const unsigned char LEON3_irq_to_cpu[32]; +#endif + +/* Common driver build-time configurations. On small systems undefine + * [DRIVER]_INFO_AVAIL to avoid info routines get dragged in. It is good + * for debugging and printing information about the system, but makes the + * image bigger. + */ +#define AMBAPPBUS_INFO_AVAIL /* AMBAPP Bus driver */ +#define APBUART_INFO_AVAIL /* APBUART Console driver */ +#define GPTIMER_INFO_AVAIL /* GPTIMER Timer driver */ +#define GRETH_INFO_AVAIL /* GRETH Ethernet driver */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/leon3/include/bsp/irq.h b/bsps/sparc/leon3/include/bsp/irq.h new file mode 100644 index 0000000000..c3e7959139 --- /dev/null +++ b/bsps/sparc/leon3/include/bsp/irq.h @@ -0,0 +1,55 @@ +/** + * @file + * @ingroup sparc_leon3 + * @brief LEON3 generic shared IRQ setup + * + * Based on libbsp/shared/include/irq.h. + */ + +/* + * Copyright (c) 2012. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_LEON3_IRQ_CONFIG_H +#define LIBBSP_LEON3_IRQ_CONFIG_H + +#include +#include + +#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ +#define BSP_INTERRUPT_VECTOR_MAX_EXT 31 /* Extended IRQ controller */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX BSP_INTERRUPT_VECTOR_MAX_EXT + +/* The check is different depending on IRQ controller, runtime detected */ +#define BSP_INTERRUPT_CUSTOM_VALID_VECTOR + +/** + * @brief Returns true if the interrupt vector with number @a vector is valid. + */ +static inline bool bsp_interrupt_is_valid_vector(rtems_vector_number vector) +{ + return (rtems_vector_number) BSP_INTERRUPT_VECTOR_MIN <= vector + && ((vector <= (rtems_vector_number) BSP_INTERRUPT_VECTOR_MAX_STD && + LEON3_IrqCtrl_EIrq == 0) || + (vector <= (rtems_vector_number) BSP_INTERRUPT_VECTOR_MAX_EXT && + LEON3_IrqCtrl_EIrq != 0)); +} + +void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +); + +void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +); + +#endif /* LIBBSP_LEON3_IRQ_CONFIG_H */ diff --git a/bsps/sparc/leon3/include/bsp/watchdog.h b/bsps/sparc/leon3/include/bsp/watchdog.h new file mode 100644 index 0000000000..3c63be2a8f --- /dev/null +++ b/bsps/sparc/leon3/include/bsp/watchdog.h @@ -0,0 +1,49 @@ +/* watchdog.h + * + * The LEON3 BSP timer watch-dog interface + * + * COPYRIGHT (c) 2012. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Initialize BSP watchdog routines. Returns number of watchdog timers found. + * Currently only one is supported. + */ +int bsp_watchdog_init(void); + +/* Reload watchdog (last timer on the first GPTIMER core), all systems does not + * feature a watchdog, it is expected that if this function is called the + * user knows that there is a watchdog available. + * + * The prescaler is normally set to number of MHz of system, this is to + * make the system clock tick be stable. + * + * Arguments + * watchdog - Always 0 for now + * reload_value - Number of timer clocks (after prescaler) to count before + * watchdog is woken. + */ +void bsp_watchdog_reload(int watchdog, unsigned int reload_value); + +/* Stop watchdog timer */ +void bsp_watchdog_stop(int watchdog); + +/* Use watchdog0 timer to reset the system */ +void bsp_watchdog_system_reset(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc/leon3/include/leon.h b/bsps/sparc/leon3/include/leon.h new file mode 100644 index 0000000000..758b760b0b --- /dev/null +++ b/bsps/sparc/leon3/include/leon.h @@ -0,0 +1,511 @@ +/** + * @file + * @ingroup sparc_leon3 + * @brief LEON3 BSP data types and macros + */ + +/* leon.h + * + * LEON3 BSP data types and macros. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * Modified for LEON3 BSP. + * COPYRIGHT (c) 2004. + * Gaisler Research. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _INCLUDE_LEON_h +#define _INCLUDE_LEON_h + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define LEON_INTERRUPT_EXTERNAL_1 5 + +#ifndef ASM +/* + * Trap Types for on-chip peripherals + * + * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments + * + * NOTE: The priority level for each source corresponds to the least + * significant nibble of the trap type. + */ + +#define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) + +#define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) + +#define LEON_INT_TRAP( _trap ) \ + ( (_trap) >= 0x11 && \ + (_trap) <= 0x1F ) + +/* /\* */ +/* * This is used to manipulate the on-chip registers. */ +/* * */ +/* * The following symbol must be defined in the linkcmds file and point */ +/* * to the correct location. */ +/* *\/ */ +/* Leon uses dynamic register mapping using amba configuration records */ +/* LEON_Register_Map is obsolete */ +/* extern LEON_Register_Map LEON_REG; */ + +#endif + +/* + * The following defines the bits in Memory Configuration Register 1. + */ + +#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 + +/* + * The following defines the bits in Memory Configuration Register 1. + */ + +#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 + + +/* + * The following defines the bits in the Timer Control Register. + */ + +#define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ + /* 0 = hold scalar and counter */ +#define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ + /* 0 = stop at 0 */ +#define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ + /* 0 = no function */ + +/* + * The following defines the bits in the UART Control Registers. + */ + +#define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ + +/* + * The following defines the bits in the LEON UART Status Register. + */ + +#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ +#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ +#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ +#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ +#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ +#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ +#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ +#define LEON_REG_UART_STATUS_TF 0x00000200 /* FIFO Full */ +#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ + +/* + * The following defines the bits in the LEON UART Control Register. + */ + +#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ +#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ +#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ +#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ +#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ +#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ +#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ +#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ +#define LEON_REG_UART_CTRL_DB 0x00000800 /* Debug FIFO enable */ +#define LEON_REG_UART_CTRL_SI 0x00004000 /* TX shift register empty IRQ enable */ +#define LEON_REG_UART_CTRL_FA 0x80000000 /* FIFO Available */ +#define LEON_REG_UART_CTRL_FA_BIT 31 + +/* + * The following defines the bits in the LEON Cache Control Register. + */ +#define LEON3_REG_CACHE_CTRL_FI 0x00200000 /* Flush instruction cache */ +#define LEON3_REG_CACHE_CTRL_DS 0x00800000 /* Data cache snooping */ + +/* LEON3 Interrupt Controller */ +extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; +extern struct ambapp_dev *LEON3_IrqCtrl_Adev; + +/* LEON3 GP Timer */ +extern volatile struct gptimer_regs *LEON3_Timer_Regs; +extern struct ambapp_dev *LEON3_Timer_Adev; + +/* LEON3 CPU Index of boot CPU */ +extern uint32_t LEON3_Cpu_Index; + +/* The external IRQ number, -1 if not external interrupts */ +extern int LEON3_IrqCtrl_EIrq; + +static __inline__ int bsp_irq_fixup(int irq) +{ + int eirq, cpu; + + if (LEON3_IrqCtrl_EIrq != 0 && irq == LEON3_IrqCtrl_EIrq) { + /* Get interrupt number from IRQ controller */ + cpu = _LEON3_Get_current_processor(); + eirq = LEON3_IrqCtrl_Regs->intid[cpu] & 0x1f; + if (eirq & 0x10) + irq = eirq; + } + + return irq; +} + +/* Macros used for manipulating bits in LEON3 GP Timer Control Register */ + +#define LEON3_IRQMPSTATUS_CPUNR 28 +#define LEON3_IRQMPSTATUS_BROADCAST 27 + + +#ifndef ASM + +/* + * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, + * and the Interrupt Pending Registers. + * + * NOTE: For operations which are not atomic, this code disables interrupts + * to guarantee there are no intervening accesses to the same register. + * The operations which read the register, modify the value and then + * store the result back are vulnerable. + */ + +extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; + +#define LEON3_IRQCTRL_ACQUIRE( _lock_context ) \ + rtems_interrupt_lock_acquire( &LEON3_IrqCtrl_Lock, _lock_context ) + +#define LEON3_IRQCTRL_RELEASE( _lock_context ) \ + rtems_interrupt_lock_release( &LEON3_IrqCtrl_Lock, _lock_context ) + +#define LEON_Clear_interrupt( _source ) \ + do { \ + LEON3_IrqCtrl_Regs->iclear = (1U << (_source)); \ + } while (0) + +#define LEON_Force_interrupt( _source ) \ + do { \ + LEON3_IrqCtrl_Regs->iforce = (1U << (_source)); \ + } while (0) + +#define LEON_Enable_interrupt_broadcast( _source ) \ + do { \ + rtems_interrupt_lock_context _lock_context; \ + uint32_t _mask = 1U << ( _source ); \ + LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ + LEON3_IrqCtrl_Regs->bcast |= _mask; \ + LEON3_IRQCTRL_RELEASE( &_lock_context ); \ + } while (0) + +#define LEON_Disable_interrupt_broadcast( _source ) \ + do { \ + rtems_interrupt_lock_context _lock_context; \ + uint32_t _mask = 1U << ( _source ); \ + LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ + LEON3_IrqCtrl_Regs->bcast &= ~_mask; \ + LEON3_IRQCTRL_RELEASE( &_lock_context ); \ + } while (0) + +#define LEON_Is_interrupt_pending( _source ) \ + (LEON3_IrqCtrl_Regs->ipend & (1U << (_source))) + +#define LEON_Cpu_Is_interrupt_masked( _source, _cpu ) \ + (!(LEON3_IrqCtrl_Regs->mask[_cpu] & (1U << (_source)))) + +#define LEON_Cpu_Mask_interrupt( _source, _cpu ) \ + do { \ + rtems_interrupt_lock_context _lock_context; \ + LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ + LEON3_IrqCtrl_Regs->mask[_cpu] &= ~(1U << (_source)); \ + LEON3_IRQCTRL_RELEASE( &_lock_context ); \ + } while (0) + +#define LEON_Cpu_Unmask_interrupt( _source, _cpu ) \ + do { \ + rtems_interrupt_lock_context _lock_context; \ + LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ + LEON3_IrqCtrl_Regs->mask[_cpu] |= (1U << (_source)); \ + LEON3_IRQCTRL_RELEASE( &_lock_context ); \ + } while (0) + +#define LEON_Cpu_Disable_interrupt( _source, _previous, _cpu ) \ + do { \ + rtems_interrupt_lock_context _lock_context; \ + uint32_t _mask = 1U << (_source); \ + LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ + (_previous) = LEON3_IrqCtrl_Regs->mask[_cpu]; \ + LEON3_IrqCtrl_Regs->mask[_cpu] = _previous & ~_mask; \ + LEON3_IRQCTRL_RELEASE( &_lock_context ); \ + (_previous) &= _mask; \ + } while (0) + +#define LEON_Cpu_Restore_interrupt( _source, _previous, _cpu ) \ + do { \ + rtems_interrupt_lock_context _lock_context; \ + uint32_t _mask = 1U << (_source); \ + LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ + LEON3_IrqCtrl_Regs->mask[_cpu] = \ + (LEON3_IrqCtrl_Regs->mask[_cpu] & ~_mask) | (_previous); \ + LEON3_IRQCTRL_RELEASE( &_lock_context ); \ + } while (0) + +/* Map single-cpu operations to local CPU */ +#define LEON_Is_interrupt_masked( _source ) \ + LEON_Cpu_Is_interrupt_masked(_source, _LEON3_Get_current_processor()) + +#define LEON_Mask_interrupt(_source) \ + LEON_Cpu_Mask_interrupt(_source, _LEON3_Get_current_processor()) + +#define LEON_Unmask_interrupt(_source) \ + LEON_Cpu_Unmask_interrupt(_source, _LEON3_Get_current_processor()) + +#define LEON_Disable_interrupt(_source, _previous) \ + LEON_Cpu_Disable_interrupt(_source, _previous, _LEON3_Get_current_processor()) + +#define LEON_Restore_interrupt(_source, _previous) \ + LEON_Cpu_Restore_interrupt(_source, _previous, _LEON3_Get_current_processor()) + +/* Make all SPARC BSPs have common macros for interrupt handling */ +#define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source) +#define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source) +#define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source) +#define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source) +#define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source) +#define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source) +#define BSP_Disable_interrupt(_source, _previous) \ + LEON_Disable_interrupt(_source, _prev) +#define BSP_Restore_interrupt(_source, _previous) \ + LEON_Restore_interrupt(_source, _previous) + +/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */ +#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \ + LEON_Cpu_Is_interrupt_masked(_source, _cpu) +#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \ + LEON_Cpu_Unmask_interrupt(_source, _cpu) +#define BSP_Cpu_Mask_interrupt(_source, _cpu) \ + LEON_Cpu_Mask_interrupt(_source, _cpu) +#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \ + LEON_Cpu_Disable_interrupt(_source, _prev, _cpu) +#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \ + LEON_Cpu_Restore_interrupt(_source, _previous, _cpu) + +/* + * Each timer control register is organized as follows: + * + * D0 - Enable + * 1 = enable counting + * 0 = hold scaler and counter + * + * D1 - Counter Reload + * 1 = reload counter at zero and restart + * 0 = stop counter at zero + * + * D2 - Counter Load + * 1 = load counter with preset value + * 0 = no function + * + */ + +#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 +#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 + +#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 + +#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 +#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 + +#define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 +#define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 + +#define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 +#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 + +#if defined(RTEMS_MULTIPROCESSING) + #define LEON3_CLOCK_INDEX \ + (rtems_configuration_get_user_multiprocessing_table() ? LEON3_Cpu_Index : 0) +#else + #define LEON3_CLOCK_INDEX 0 +#endif + +/* + * We assume that a boot loader (usually GRMON) initialized the GPTIMER 0 to + * run with 1MHz. This is used to determine all clock frequencies of the PnP + * devices. See also ambapp_freq_init() and ambapp_freq_get(). + */ +#define LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER 1000000 + +/* Load 32-bit word by forcing a cache-miss */ +static inline unsigned int leon_r32_no_cache(uintptr_t addr) +{ + unsigned int tmp; + __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr)); + return tmp; +} + +/* Let user override which on-chip APBUART will be debug UART + * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... + * 1 = APBUART[0] + * 2 = APBUART[1] + * 3 = APBUART[2] + * ... + */ +extern int syscon_uart_index; + +/* Let user override which on-chip APBUART will be debug UART + * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... + * 1 = APBUART[0] + * 2 = APBUART[1] + * 3 = APBUART[2] + * ... + */ +extern int leon3_debug_uart_index; + +/* Let user override which on-chip TIMER core will be used for system clock + * timer. This controls which timer core will be accociated with + * LEON3_Timer_Regs registers base address. This value will by destroyed during + * initialization. + * 0 = Default configuration. GPTIMER[0] + * 1 = GPTIMER[1] + * 2 = GPTIMER[2] + * ... + */ +extern int leon3_timer_core_index; + +/* Let user override system clock timer prescaler. This affects all timer + * instances on the system clock timer core determined by + * leon3_timer_core_index. + * 0 = Default configuration. Use bootloader configured value. + * N = Prescaler is set to N. N must not be less that number of timers. + * 8 = Prescaler is set to 8 (the fastest prescaler possible on all HW) + * ... + */ +extern unsigned int leon3_timer_prescaler; + +/* GRLIB extended IRQ controller register */ +void leon3_ext_irq_init(void); + +void leon3_power_down_loop(void) RTEMS_NO_RETURN; + +static inline uint32_t leon3_get_cpu_count( + volatile struct irqmp_regs *irqmp +) +{ + uint32_t mpstat = irqmp->mpstat; + + return ((mpstat >> LEON3_IRQMPSTATUS_CPUNR) & 0xf) + 1; +} + +static inline void leon3_set_system_register(uint32_t addr, uint32_t val) +{ + __asm__ volatile( + "sta %1, [%0] 2" + : + : "r" (addr), "r" (val) + ); +} + +static inline uint32_t leon3_get_system_register(uint32_t addr) +{ + uint32_t val; + + __asm__ volatile( + "lda [%1] 2, %0" + : "=r" (val) + : "r" (addr) + ); + + return val; +} + +static inline void leon3_set_cache_control_register(uint32_t val) +{ + leon3_set_system_register(0x0, val); +} + +static inline uint32_t leon3_get_cache_control_register(void) +{ + return leon3_get_system_register(0x0); +} + +static inline bool leon3_data_cache_snooping_enabled(void) +{ + return leon3_get_cache_control_register() & LEON3_REG_CACHE_CTRL_DS; +} + +static inline uint32_t leon3_get_inst_cache_config_register(void) +{ + return leon3_get_system_register(0x8); +} + +static inline uint32_t leon3_get_data_cache_config_register(void) +{ + return leon3_get_system_register(0xc); +} + +static inline bool leon3_irqmp_has_timestamp( + volatile struct irqmp_timestamp_regs *irqmp_ts +) +{ + return (irqmp_ts->control >> 27) > 0; +} + +static inline uint32_t leon3_up_counter_low(void) +{ + uint32_t asr23; + + __asm__ volatile ( + "mov %%asr23, %0" + : "=&r" (asr23) + ); + + return asr23; +} + +static inline uint32_t leon3_up_counter_high(void) +{ + uint32_t asr22; + + __asm__ volatile ( + "mov %%asr22, %0" + : "=&r" (asr22) + ); + + return asr22; +} + +static inline void leon3_up_counter_enable(void) +{ + __asm__ volatile ( + "mov %g0, %asr22" + ); +} + +static inline bool leon3_up_counter_is_available(void) +{ + return leon3_up_counter_low() != leon3_up_counter_low(); +} + +static inline uint32_t leon3_up_counter_frequency(void) +{ + /* + * For simplicity, assume that the interrupt controller uses the processor + * clock. This is at least true on the GR740. + */ + return ambapp_freq_get(&ambapp_plb, LEON3_IrqCtrl_Adev); +} + +#endif /* !ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* !_INCLUDE_LEON_h */ +/* end of include file */ + diff --git a/bsps/sparc/leon3/include/tm27.h b/bsps/sparc/leon3/include/tm27.h new file mode 100644 index 0000000000..00921d4880 --- /dev/null +++ b/bsps/sparc/leon3/include/tm27.h @@ -0,0 +1,84 @@ +/** + * @file + * @ingroup sparc_leon3 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * COPYRIGHT (c) 2006. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: Since the interrupt code for the SPARC supports both synchronous + * and asynchronous trap handlers, support for testing with both + * is included. + */ + +#define SIS_USE_SYNCHRONOUS_TRAP 0 + +/* + * The synchronous trap is an arbitrarily chosen software trap. + */ + +#if (SIS_USE_SYNCHRONOUS_TRAP == 1) + +#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), TEST_VECTOR, 1 ); + +#define Cause_tm27_intr() \ + __asm__ volatile( "ta 0x10; nop " ); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +/* + * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. + */ + +#else /* use a regular asynchronous trap */ + +#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1 +#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) +#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1 +#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), TEST_VECTOR, 1 ); \ + set_vector( (handler), TEST_VECTOR2, 1 ); + +#define Cause_tm27_intr() \ + do { \ + LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \ + nop(); \ + nop(); \ + nop(); \ + } while (0) + +#define Clear_tm27_intr() \ + LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE ) + +#define Lower_tm27_intr() /* empty */ + +#endif + +#endif diff --git a/bsps/sparc64/headers.am b/bsps/sparc64/headers.am new file mode 100644 index 0000000000..1a04025280 --- /dev/null +++ b/bsps/sparc64/headers.am @@ -0,0 +1,54 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../bsps/sparc64/include/asm.h +include_HEADERS += ../../../../../bsps/sparc64/include/traptable.h + +include_archdir = $(includedir)/arch +include_arch_HEADERS = +include_arch_HEADERS += ../../../../../bsps/sparc64/include/arch/arch.h +include_arch_HEADERS += ../../../../../bsps/sparc64/include/arch/boot.h +include_arch_HEADERS += ../../../../../bsps/sparc64/include/arch/regdef.h +include_arch_HEADERS += ../../../../../bsps/sparc64/include/arch/stack.h + +include_arch_mmdir = $(includedir)/arch/mm +include_arch_mm_HEADERS = +include_arch_mm_HEADERS += ../../../../../bsps/sparc64/include/arch/mm/cache_spec.h +include_arch_mm_HEADERS += ../../../../../bsps/sparc64/include/arch/mm/frame.h +include_arch_mm_HEADERS += ../../../../../bsps/sparc64/include/arch/mm/mmu.h +include_arch_mm_HEADERS += ../../../../../bsps/sparc64/include/arch/mm/page.h +include_arch_mm_HEADERS += ../../../../../bsps/sparc64/include/arch/mm/tlb.h +include_arch_mm_HEADERS += ../../../../../bsps/sparc64/include/arch/mm/tte.h + +include_arch_mm_sun4udir = $(includedir)/arch/mm/sun4u +include_arch_mm_sun4u_HEADERS = +include_arch_mm_sun4u_HEADERS += ../../../../../bsps/sparc64/include/arch/mm/sun4u/frame.h +include_arch_mm_sun4u_HEADERS += ../../../../../bsps/sparc64/include/arch/mm/sun4u/mmu.h +include_arch_mm_sun4u_HEADERS += ../../../../../bsps/sparc64/include/arch/mm/sun4u/page.h +include_arch_mm_sun4u_HEADERS += ../../../../../bsps/sparc64/include/arch/mm/sun4u/tlb.h +include_arch_mm_sun4u_HEADERS += ../../../../../bsps/sparc64/include/arch/mm/sun4u/tte.h + +include_arch_sun4udir = $(includedir)/arch/sun4u +include_arch_sun4u_HEADERS = +include_arch_sun4u_HEADERS += ../../../../../bsps/sparc64/include/arch/sun4u/arch.h + +include_bootdir = $(includedir)/boot +include_boot_HEADERS = +include_boot_HEADERS += ../../../../../bsps/sparc64/include/boot/align.h +include_boot_HEADERS += ../../../../../bsps/sparc64/include/boot/balloc.h +include_boot_HEADERS += ../../../../../bsps/sparc64/include/boot/gentypes.h +include_boot_HEADERS += ../../../../../bsps/sparc64/include/boot/main.h +include_boot_HEADERS += ../../../../../bsps/sparc64/include/boot/ofw.h +include_boot_HEADERS += ../../../../../bsps/sparc64/include/boot/ofw_tree.h +include_boot_HEADERS += ../../../../../bsps/sparc64/include/boot/ofwarch.h +include_boot_HEADERS += ../../../../../bsps/sparc64/include/boot/register.h +include_boot_HEADERS += ../../../../../bsps/sparc64/include/boot/stack.h +include_boot_HEADERS += ../../../../../bsps/sparc64/include/boot/types.h + +include_genarch_ofwdir = $(includedir)/genarch/ofw +include_genarch_ofw_HEADERS = +include_genarch_ofw_HEADERS += ../../../../../bsps/sparc64/include/genarch/ofw/ofw_tree.h + +include_kerneldir = $(includedir)/kernel +include_kernel_HEADERS = +include_kernel_HEADERS += ../../../../../bsps/sparc64/include/kernel/align.h diff --git a/bsps/sparc64/include/arch/arch.h b/bsps/sparc64/include/arch/arch.h new file mode 100644 index 0000000000..5fdd4a2cb2 --- /dev/null +++ b/bsps/sparc64/include/arch/arch.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** + * @file + * @brief Various sparc64-specific macros. + */ + +#ifndef KERN_sparc64_ARCH_H_ +#define KERN_sparc64_ARCH_H_ + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + +#define ASI_AIUP 0x10 /** Access to primary context with user privileges. */ +#define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ + +#define NWINDOWS 8 /** Number of register window sets. */ + +#ifndef __ASM__ + +extern void arch_pre_main(void); + +#endif /* __ASM__ */ + + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/boot.h b/bsps/sparc64/include/arch/boot.h new file mode 100644 index 0000000000..b0a997a957 --- /dev/null +++ b/bsps/sparc64/include/arch/boot.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_BOOT_H_ +#define KERN_sparc64_BOOT_H_ + +#if 0 +#define VMA 0x400000 +#endif +#define VMA 0x4000 +#define LMA VMA + +#ifndef __ASM__ +#ifndef __LINKER__ + +#include +#include +#include + +#define TASKMAP_MAX_RECORDS 32 +#define MEMMAP_MAX_RECORDS 32 + +#define BOOTINFO_TASK_NAME_BUFLEN 32 + +typedef struct { + void * addr; + uint32_t size; + char name[BOOTINFO_TASK_NAME_BUFLEN]; +} utask_t; + +typedef struct { + uint32_t count; + utask_t tasks[TASKMAP_MAX_RECORDS]; +} taskmap_t; + +typedef struct { + uintptr_t start; + uint32_t size; +} memzone_t; + +typedef struct { + uint32_t total; + uint32_t count; + memzone_t zones[MEMMAP_MAX_RECORDS]; +} memmap_t; + +/** Bootinfo structure. + * + * Must be in sync with bootinfo structure used by the boot loader. + */ +typedef struct { + uintptr_t physmem_start; + taskmap_t taskmap; + memmap_t memmap; + ballocs_t ballocs; + ofw_tree_node_t *ofw_root; +} bootinfo_t; + +extern bootinfo_t bootinfo; + +#endif +#endif + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/cache_spec.h b/bsps/sparc64/include/arch/mm/cache_spec.h new file mode 100644 index 0000000000..1d9199db33 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/cache_spec.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2008 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_CACHE_SPEC_H_ +#define KERN_sparc64_CACHE_SPEC_H_ + +/* + * The following macros are valid for the following processors: + * + * UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III, + * UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+ + * + * Should we support other UltraSPARC processors, we need to make sure that + * the macros are defined correctly for them. + */ + +#if defined (US) +#define DCACHE_SIZE (16 * 1024) +#elif defined (US3) +#define DCACHE_SIZE (64 * 1024) +#endif +#define DCACHE_LINE_SIZE 32 + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/frame.h b/bsps/sparc64/include/arch/mm/frame.h new file mode 100644 index 0000000000..fb66e54bf1 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/frame.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_FRAME_H_ +#define KERN_sparc64_FRAME_H_ + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/mmu.h b/bsps/sparc64/include/arch/mm/mmu.h new file mode 100644 index 0000000000..1d445f2e24 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/mmu.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_MMU_H_ +#define KERN_sparc64_MMU_H_ + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/page.h b/bsps/sparc64/include/arch/mm/page.h new file mode 100644 index 0000000000..f1451a2866 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/page.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_PAGE_H_ +#define KERN_sparc64_PAGE_H_ + +#include + +/* + * On the TLB and TSB level, we still use 8K pages, which are supported by the + * MMU. + */ +#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH +#define MMU_PAGE_SIZE MMU_FRAME_SIZE + +/* + * On the page table level, we use 16K pages. 16K pages are not supported by + * the MMU but we emulate them with pairs of 8K pages. + */ +#define PAGE_WIDTH FRAME_WIDTH +#define PAGE_SIZE FRAME_SIZE + +#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) + +#ifdef KERNEL + +#ifndef __ASM__ + +#include + +extern uintptr_t physmem_base; + +#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) +#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) + +typedef union { + uintptr_t address; + struct { + uint64_t vpn : 51; /**< Virtual Page Number. */ + unsigned offset : 13; /**< Offset. */ + } __attribute__ ((packed)); +} page_address_t; + +extern void page_arch_init(void); + +#endif /* !def __ASM__ */ + +#endif /* KERNEL */ + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/frame.h b/bsps/sparc64/include/arch/mm/sun4u/frame.h new file mode 100644 index 0000000000..e30f504d08 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/sun4u/frame.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_SUN4U_FRAME_H_ +#define KERN_sparc64_SUN4U_FRAME_H_ + +/* + * Page size supported by the MMU. + * For 8K there is the nasty illegal virtual aliasing problem. + * Therefore, the kernel uses 8K only internally on the TLB and TSB levels. + */ +#define MMU_FRAME_WIDTH 13 /* 8K */ +#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) + +/* + * Page size exported to the generic memory management subsystems. + * This page size is not directly supported by the MMU, but we can emulate + * each 16K page with a pair of adjacent 8K pages. + */ +#define FRAME_WIDTH 14 /* 16K */ +#define FRAME_SIZE (1 << FRAME_WIDTH) + +#ifdef KERNEL +#ifndef __ASM__ + +#include + +union frame_address { + uintptr_t address; + struct { +#if defined (US) + unsigned : 23; + uint64_t pfn : 28; /**< Physical Frame Number. */ +#elif defined (US3) + unsigned : 21; + uint64_t pfn : 30; /**< Physical Frame Number. */ +#endif + unsigned offset : 13; /**< Offset. */ + } __attribute__ ((packed)); +}; + +typedef union frame_address frame_address_t; + +extern uintptr_t last_frame; +extern uintptr_t end_of_identity; + +extern void frame_arch_init(void); +#define physmem_print() + +#endif +#endif + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/mmu.h b/bsps/sparc64/include/arch/mm/sun4u/mmu.h new file mode 100644 index 0000000000..f887ebe7f4 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/sun4u/mmu.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_MMU_H_ +#define KERN_sparc64_sun4u_MMU_H_ + +#if defined(US) +/* LSU Control Register ASI. */ +#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ +#endif + +/* I-MMU ASIs. */ +#define ASI_IMMU 0x50 +#define ASI_IMMU_TSB_8KB_PTR_REG 0x51 +#define ASI_IMMU_TSB_64KB_PTR_REG 0x52 +#define ASI_ITLB_DATA_IN_REG 0x54 +#define ASI_ITLB_DATA_ACCESS_REG 0x55 +#define ASI_ITLB_TAG_READ_REG 0x56 +#define ASI_IMMU_DEMAP 0x57 + +/* Virtual Addresses within ASI_IMMU. */ +#define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ +#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ +#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ +#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ +#if defined (US3) +#define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */ +#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ +#endif + + +/* D-MMU ASIs. */ +#define ASI_DMMU 0x58 +#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 +#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a +#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b +#define ASI_DTLB_DATA_IN_REG 0x5c +#define ASI_DTLB_DATA_ACCESS_REG 0x5d +#define ASI_DTLB_TAG_READ_REG 0x5e +#define ASI_DMMU_DEMAP 0x5f + +/* Virtual Addresses within ASI_DMMU. */ +#define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ +#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ +#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ +#define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ +#define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ +#define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ +#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ +#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ +#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ +#if defined (US3) +#define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */ +#define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */ +#define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */ +#endif + +#ifndef __ASM__ + +#include +#include +#include + +#if defined(US) +/** LSU Control Register. */ +typedef union { + uint64_t value; + struct { + unsigned : 23; + unsigned pm : 8; + unsigned vm : 8; + unsigned pr : 1; + unsigned pw : 1; + unsigned vr : 1; + unsigned vw : 1; + unsigned : 1; + unsigned fm : 16; + unsigned dm : 1; /**< D-MMU enable. */ + unsigned im : 1; /**< I-MMU enable. */ + unsigned dc : 1; /**< D-Cache enable. */ + unsigned ic : 1; /**< I-Cache enable. */ + + } __attribute__ ((packed)); +} lsu_cr_reg_t; +#endif /* US */ + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/page.h b/bsps/sparc64/include/arch/mm/sun4u/page.h new file mode 100644 index 0000000000..f1451a2866 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/sun4u/page.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_PAGE_H_ +#define KERN_sparc64_PAGE_H_ + +#include + +/* + * On the TLB and TSB level, we still use 8K pages, which are supported by the + * MMU. + */ +#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH +#define MMU_PAGE_SIZE MMU_FRAME_SIZE + +/* + * On the page table level, we use 16K pages. 16K pages are not supported by + * the MMU but we emulate them with pairs of 8K pages. + */ +#define PAGE_WIDTH FRAME_WIDTH +#define PAGE_SIZE FRAME_SIZE + +#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) + +#ifdef KERNEL + +#ifndef __ASM__ + +#include + +extern uintptr_t physmem_base; + +#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) +#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) + +typedef union { + uintptr_t address; + struct { + uint64_t vpn : 51; /**< Virtual Page Number. */ + unsigned offset : 13; /**< Offset. */ + } __attribute__ ((packed)); +} page_address_t; + +extern void page_arch_init(void); + +#endif /* !def __ASM__ */ + +#endif /* KERNEL */ + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/tlb.h b/bsps/sparc64/include/arch/mm/sun4u/tlb.h new file mode 100644 index 0000000000..6f6e6542e6 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/sun4u/tlb.h @@ -0,0 +1,693 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TLB_sun4u_H_ +#define KERN_sparc64_TLB_sun4u_H_ + +#if defined (US) +#define ITLB_ENTRY_COUNT 64 +#define DTLB_ENTRY_COUNT 64 +#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT +#endif + +/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ +#if defined (US3) +#define DTLB_MAX_LOCKED_ENTRIES 16 +#endif + +#define MEM_CONTEXT_KERNEL 0 +#define MEM_CONTEXT_TEMP 1 + +/** Page sizes. */ +#define PAGESIZE_8K 0 +#define PAGESIZE_64K 1 +#define PAGESIZE_512K 2 +#define PAGESIZE_4M 3 + +/** Bit width of the TLB-locked portion of kernel address space. */ +#define KERNEL_PAGE_WIDTH 22 /* 4M */ + +/* TLB Demap Operation types. */ +#define TLB_DEMAP_PAGE 0 +#define TLB_DEMAP_CONTEXT 1 +#if defined (US3) +#define TLB_DEMAP_ALL 2 +#endif + +#define TLB_DEMAP_TYPE_SHIFT 6 + +/* TLB Demap Operation Context register encodings. */ +#define TLB_DEMAP_PRIMARY 0 +#define TLB_DEMAP_SECONDARY 1 +#define TLB_DEMAP_NUCLEUS 2 + +/* There are more TLBs in one MMU in US3, their codes are defined here. */ +#if defined (US3) +/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */ +#define TLB_DSMALL 0 +#define TLB_DBIG_0 2 +#define TLB_DBIG_1 3 + +/* I-MMU: one small (16-entry) TLB and one big TLB */ +#define TLB_ISMALL 0 +#define TLB_IBIG 2 +#endif + +#define TLB_DEMAP_CONTEXT_SHIFT 4 + +/* TLB Tag Access shifts */ +#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 +#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) +#define TLB_TAG_ACCESS_VPN_SHIFT 13 + +#ifndef __ASM__ + +#include +#include +#include +#include +#include +#include +#include +#include + +union tlb_context_reg { + uint64_t v; + struct { + unsigned long : 51; + unsigned context : 13; /**< Context/ASID. */ + } __attribute__ ((packed)); +}; +typedef union tlb_context_reg tlb_context_reg_t; + +/** I-/D-TLB Data In/Access Register type. */ +typedef tte_data_t tlb_data_t; + +/** I-/D-TLB Data Access Address in Alternate Space. */ + +#if defined (US) + +union tlb_data_access_addr { + uint64_t value; + struct { + uint64_t : 55; + unsigned tlb_entry : 6; + unsigned : 3; + } __attribute__ ((packed)); +}; +typedef union tlb_data_access_addr dtlb_data_access_addr_t; +typedef union tlb_data_access_addr dtlb_tag_read_addr_t; +typedef union tlb_data_access_addr itlb_data_access_addr_t; +typedef union tlb_data_access_addr itlb_tag_read_addr_t; + +#elif defined (US3) + +/* + * In US3, I-MMU and D-MMU have different formats of the data + * access register virtual address. In the corresponding + * structures the member variable for the entry number is + * called "local_tlb_entry" - it contrasts with the "tlb_entry" + * for the US data access register VA structure. The rationale + * behind this is to prevent careless mistakes in the code + * caused by setting only the entry number and not the TLB + * number in the US3 code (when taking the code from US). + */ + +union dtlb_data_access_addr { + uint64_t value; + struct { + uint64_t : 45; + unsigned : 1; + unsigned tlb_number : 2; + unsigned : 4; + unsigned local_tlb_entry : 9; + unsigned : 3; + } __attribute__ ((packed)); +}; +typedef union dtlb_data_access_addr dtlb_data_access_addr_t; +typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; + +union itlb_data_access_addr { + uint64_t value; + struct { + uint64_t : 45; + unsigned : 1; + unsigned tlb_number : 2; + unsigned : 6; + unsigned local_tlb_entry : 7; + unsigned : 3; + } __attribute__ ((packed)); +}; +typedef union itlb_data_access_addr itlb_data_access_addr_t; +typedef union itlb_data_access_addr itlb_tag_read_addr_t; + +#endif + +/** I-/D-TLB Tag Read Register. */ +union tlb_tag_read_reg { + uint64_t value; + struct { + uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ + unsigned context : 13; /**< Context identifier. */ + } __attribute__ ((packed)); +}; +typedef union tlb_tag_read_reg tlb_tag_read_reg_t; +typedef union tlb_tag_read_reg tlb_tag_access_reg_t; + + +/** TLB Demap Operation Address. */ +union tlb_demap_addr { + uint64_t value; + struct { + uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ +#if defined (US) + unsigned : 6; /**< Ignored. */ + unsigned type : 1; /**< The type of demap operation. */ +#elif defined (US3) + unsigned : 5; /**< Ignored. */ + unsigned type: 2; /**< The type of demap operation. */ +#endif + unsigned context : 2; /**< Context register selection. */ + unsigned : 4; /**< Zero. */ + } __attribute__ ((packed)); +}; +typedef union tlb_demap_addr tlb_demap_addr_t; + +/** TLB Synchronous Fault Status Register. */ +union tlb_sfsr_reg { + uint64_t value; + struct { +#if defined (US) + unsigned long : 40; /**< Implementation dependent. */ + unsigned asi : 8; /**< ASI. */ + unsigned : 2; + unsigned ft : 7; /**< Fault type. */ +#elif defined (US3) + unsigned long : 39; /**< Implementation dependent. */ + unsigned nf : 1; /**< Non-faulting load. */ + unsigned asi : 8; /**< ASI. */ + unsigned tm : 1; /**< I-TLB miss. */ + unsigned : 3; /**< Reserved. */ + unsigned ft : 5; /**< Fault type. */ +#endif + unsigned e : 1; /**< Side-effect bit. */ + unsigned ct : 2; /**< Context Register selection. */ + unsigned pr : 1; /**< Privilege bit. */ + unsigned w : 1; /**< Write bit. */ + unsigned ow : 1; /**< Overwrite bit. */ + unsigned fv : 1; /**< Fault Valid bit. */ + } __attribute__ ((packed)); +}; +typedef union tlb_sfsr_reg tlb_sfsr_reg_t; + +#if defined (US3) + +/* + * Functions for determining the number of entries in TLBs. They either return + * a constant value or a value based on the CPU autodetection. + */ + +/** + * Determine the number of entries in the DMMU's small TLB. + */ +static inline uint16_t tlb_dsmall_size(void) +{ + return 16; +} + +/** + * Determine the number of entries in each DMMU's big TLB. + */ +static inline uint16_t tlb_dbig_size(void) +{ + return 512; +} + +/** + * Determine the number of entries in the IMMU's small TLB. + */ +static inline uint16_t tlb_ismall_size(void) +{ + return 16; +} + +/** + * Determine the number of entries in the IMMU's big TLB. + */ +static inline uint16_t tlb_ibig_size(void) +{ + if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) + return 512; + else + return 128; +} + +#endif + +/** Read MMU Primary Context Register. + * + * @return Current value of Primary Context Register. + */ +static inline uint64_t mmu_primary_context_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); +} + +/** Write MMU Primary Context Register. + * + * @param v New value of Primary Context Register. + */ +static inline void mmu_primary_context_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); + flush_pipeline(); +} + +/** Read MMU Secondary Context Register. + * + * @return Current value of Secondary Context Register. + */ +static inline uint64_t mmu_secondary_context_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); +} + +/** Write MMU Primary Context Register. + * + * @param v New value of Primary Context Register. + */ +static inline void mmu_secondary_context_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); + flush_pipeline(); +} + +#if defined (US) + +/** Read IMMU TLB Data Access Register. + * + * @param entry TLB Entry index. + * + * @return Current value of specified IMMU TLB Data Access + * Register. + */ +static inline uint64_t itlb_data_access_read(size_t entry) +{ + itlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_entry = entry; + return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); +} + +/** Write IMMU TLB Data Access Register. + * + * @param entry TLB Entry index. + * @param value Value to be written. + */ +static inline void itlb_data_access_write(size_t entry, uint64_t value) +{ + itlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_entry = entry; + asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); + flush_pipeline(); +} + +/** Read DMMU TLB Data Access Register. + * + * @param entry TLB Entry index. + * + * @return Current value of specified DMMU TLB Data Access + * Register. + */ +static inline uint64_t dtlb_data_access_read(size_t entry) +{ + dtlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_entry = entry; + return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); +} + +/** Write DMMU TLB Data Access Register. + * + * @param entry TLB Entry index. + * @param value Value to be written. + */ +static inline void dtlb_data_access_write(size_t entry, uint64_t value) +{ + dtlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_entry = entry; + asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); + membar(); +} + +/** Read IMMU TLB Tag Read Register. + * + * @param entry TLB Entry index. + * + * @return Current value of specified IMMU TLB Tag Read Register. + */ +static inline uint64_t itlb_tag_read_read(size_t entry) +{ + itlb_tag_read_addr_t tag; + + tag.value = 0; + tag.tlb_entry = entry; + return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); +} + +/** Read DMMU TLB Tag Read Register. + * + * @param entry TLB Entry index. + * + * @return Current value of specified DMMU TLB Tag Read Register. + */ +static inline uint64_t dtlb_tag_read_read(size_t entry) +{ + dtlb_tag_read_addr_t tag; + + tag.value = 0; + tag.tlb_entry = entry; + return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); +} + +#elif defined (US3) + + +/** Read IMMU TLB Data Access Register. + * + * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) + * @param entry TLB Entry index. + * + * @return Current value of specified IMMU TLB Data Access + * Register. + */ +static inline uint64_t itlb_data_access_read(int tlb, size_t entry) +{ + itlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_number = tlb; + reg.local_tlb_entry = entry; + return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); +} + +/** Write IMMU TLB Data Access Register. + * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) + * @param entry TLB Entry index. + * @param value Value to be written. + */ +static inline void itlb_data_access_write(int tlb, size_t entry, + uint64_t value) +{ + itlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_number = tlb; + reg.local_tlb_entry = entry; + asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); + flush_pipeline(); +} + +/** Read DMMU TLB Data Access Register. + * + * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) + * @param entry TLB Entry index. + * + * @return Current value of specified DMMU TLB Data Access + * Register. + */ +static inline uint64_t dtlb_data_access_read(int tlb, size_t entry) +{ + dtlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_number = tlb; + reg.local_tlb_entry = entry; + return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); +} + +/** Write DMMU TLB Data Access Register. + * + * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) + * @param entry TLB Entry index. + * @param value Value to be written. + */ +static inline void dtlb_data_access_write(int tlb, size_t entry, + uint64_t value) +{ + dtlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_number = tlb; + reg.local_tlb_entry = entry; + asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); + membar(); +} + +/** Read IMMU TLB Tag Read Register. + * + * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) + * @param entry TLB Entry index. + * + * @return Current value of specified IMMU TLB Tag Read Register. + */ +static inline uint64_t itlb_tag_read_read(int tlb, size_t entry) +{ + itlb_tag_read_addr_t tag; + + tag.value = 0; + tag.tlb_number = tlb; + tag.local_tlb_entry = entry; + return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); +} + +/** Read DMMU TLB Tag Read Register. + * + * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) + * @param entry TLB Entry index. + * + * @return Current value of specified DMMU TLB Tag Read Register. + */ +static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry) +{ + dtlb_tag_read_addr_t tag; + + tag.value = 0; + tag.tlb_number = tlb; + tag.local_tlb_entry = entry; + return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); +} + +#endif + + +/** Write IMMU TLB Tag Access Register. + * + * @param v Value to be written. + */ +static inline void itlb_tag_access_write(uint64_t v) +{ + asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); + flush_pipeline(); +} + +/** Read IMMU TLB Tag Access Register. + * + * @return Current value of IMMU TLB Tag Access Register. + */ +static inline uint64_t itlb_tag_access_read(void) +{ + return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); +} + +/** Write DMMU TLB Tag Access Register. + * + * @param v Value to be written. + */ +static inline void dtlb_tag_access_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); + membar(); +} + +/** Read DMMU TLB Tag Access Register. + * + * @return Current value of DMMU TLB Tag Access Register. + */ +static inline uint64_t dtlb_tag_access_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); +} + + +/** Write IMMU TLB Data in Register. + * + * @param v Value to be written. + */ +static inline void itlb_data_in_write(uint64_t v) +{ + asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); + flush_pipeline(); +} + +/** Write DMMU TLB Data in Register. + * + * @param v Value to be written. + */ +static inline void dtlb_data_in_write(uint64_t v) +{ + asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); + membar(); +} + +/** Read ITLB Synchronous Fault Status Register. + * + * @return Current content of I-SFSR register. + */ +static inline uint64_t itlb_sfsr_read(void) +{ + return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); +} + +/** Write ITLB Synchronous Fault Status Register. + * + * @param v New value of I-SFSR register. + */ +static inline void itlb_sfsr_write(uint64_t v) +{ + asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); + flush_pipeline(); +} + +/** Read DTLB Synchronous Fault Status Register. + * + * @return Current content of D-SFSR register. + */ +static inline uint64_t dtlb_sfsr_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); +} + +/** Write DTLB Synchronous Fault Status Register. + * + * @param v New value of D-SFSR register. + */ +static inline void dtlb_sfsr_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); + membar(); +} + +/** Read DTLB Synchronous Fault Address Register. + * + * @return Current content of D-SFAR register. + */ +static inline uint64_t dtlb_sfar_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); +} + +/** Perform IMMU TLB Demap Operation. + * + * @param type Selects between context and page demap (and entire MMU + * demap on US3). + * @param context_encoding Specifies which Context register has Context ID for + * demap. + * @param page Address which is on the page to be demapped. + */ +static inline void itlb_demap(int type, int context_encoding, uintptr_t page) +{ + tlb_demap_addr_t da; + page_address_t pg; + + da.value = 0; + pg.address = page; + + da.type = type; + da.context = context_encoding; + da.vpn = pg.vpn; + + /* da.value is the address within the ASI */ + asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); + + flush_pipeline(); +} + +/** Perform DMMU TLB Demap Operation. + * + * @param type Selects between context and page demap (and entire MMU + * demap on US3). + * @param context_encoding Specifies which Context register has Context ID for + * demap. + * @param page Address which is on the page to be demapped. + */ +static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) +{ + tlb_demap_addr_t da; + page_address_t pg; + + da.value = 0; + pg.address = page; + + da.type = type; + da.context = context_encoding; + da.vpn = pg.vpn; + + /* da.value is the address within the ASI */ + asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); + + membar(); +} + +extern void fast_instruction_access_mmu_miss(unative_t, istate_t *); +extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *); +extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *); + +extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); + +extern void dump_sfsr_and_sfar(void); +extern void describe_dmmu_fault(void); + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/tte.h b/bsps/sparc64/include/arch/mm/sun4u/tte.h new file mode 100644 index 0000000000..46acaed47c --- /dev/null +++ b/bsps/sparc64/include/arch/mm/sun4u/tte.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_TTE_H_ +#define KERN_sparc64_sun4u_TTE_H_ + +#define TTE_G (1 << 0) +#define TTE_W (1 << 1) +#define TTE_P (1 << 2) +#define TTE_E (1 << 3) +#define TTE_CV (1 << 4) +#define TTE_CP (1 << 5) +#define TTE_L (1 << 6) + +#define TTE_V_SHIFT 63 +#define TTE_SIZE_SHIFT 61 + +#ifndef __ASM__ + +#include + +/* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */ +#define VA_TAG_PAGE_SHIFT 22 + +/** Translation Table Entry - Tag. */ +union tte_tag { + uint64_t value; + struct { + unsigned g : 1; /**< Global. */ + unsigned : 2; /**< Reserved. */ + unsigned context : 13; /**< Context identifier. */ + unsigned : 6; /**< Reserved. */ + uint64_t va_tag : 42; /**< Virtual Address Tag, bits 63:22. */ + } __attribute__ ((packed)); +}; + +typedef union tte_tag tte_tag_t; + +/** Translation Table Entry - Data. */ +union tte_data { + uint64_t value; + struct { + unsigned v : 1; /**< Valid. */ + unsigned size : 2; /**< Page size of this entry. */ + unsigned nfo : 1; /**< No-Fault-Only. */ + unsigned ie : 1; /**< Invert Endianness. */ + unsigned soft2 : 9; /**< Software defined field. */ +#if defined (US) + unsigned diag : 9; /**< Diagnostic data. */ + unsigned pfn : 28; /**< Physical Address bits, bits 40:13. */ +#elif defined (US3) + unsigned : 7; /**< Reserved. */ + unsigned pfn : 30; /**< Physical Address bits, bits 42:13 */ +#endif + unsigned soft : 6; /**< Software defined field. */ + unsigned l : 1; /**< Lock. */ + unsigned cp : 1; /**< Cacheable in physically indexed cache. */ + unsigned cv : 1; /**< Cacheable in virtually indexed cache. */ + unsigned e : 1; /**< Side-effect. */ + unsigned p : 1; /**< Privileged. */ + unsigned w : 1; /**< Writable. */ + unsigned g : 1; /**< Global. */ + } __attribute__ ((packed)); +}; + +typedef union tte_data tte_data_t; + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/tlb.h b/bsps/sparc64/include/arch/mm/tlb.h new file mode 100644 index 0000000000..4adf26ca64 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/tlb.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TLB_H_ +#define KERN_sparc64_TLB_H_ + + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/tte.h b/bsps/sparc64/include/arch/mm/tte.h new file mode 100644 index 0000000000..f0b746e8c6 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/tte.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TTE_H_ +#define KERN_sparc64_TTE_H_ + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/regdef.h b/bsps/sparc64/include/arch/regdef.h new file mode 100644 index 0000000000..aae46fa99f --- /dev/null +++ b/bsps/sparc64/include/arch/regdef.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_REGDEF_H_ +#define KERN_sparc64_REGDEF_H_ + +#define PSTATE_IE_BIT (1 << 1) +#define PSTATE_AM_BIT (1 << 3) + +#define PSTATE_AG_BIT (1 << 0) +#define PSTATE_IG_BIT (1 << 11) +#define PSTATE_MG_BIT (1 << 10) + +#define PSTATE_PRIV_BIT (1 << 2) +#define PSTATE_PEF_BIT (1 << 4) + +#define TSTATE_PSTATE_SHIFT 8 +#define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT << TSTATE_PSTATE_SHIFT) +#define TSTATE_IE_BIT (PSTATE_IE_BIT << TSTATE_PSTATE_SHIFT) +#define TSTATE_PEF_BIT (PSTATE_PEF_BIT << TSTATE_PSTATE_SHIFT) + +#define TSTATE_CWP_MASK 0x1f + +#define WSTATE_NORMAL(n) (n) +#define WSTATE_OTHER(n) ((n) << 3) + +/* + * The following definitions concern the UPA_CONFIG register on US and the + * FIREPLANE_CONFIG register on US3. + */ +#define ICBUS_CONFIG_MID_SHIFT 17 + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/stack.h b/bsps/sparc64/include/arch/stack.h new file mode 100644 index 0000000000..6364916912 --- /dev/null +++ b/bsps/sparc64/include/arch/stack.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_STACK_H_ +#define KERN_sparc64_STACK_H_ + +#define STACK_ITEM_SIZE 8 + +/** According to SPARC Compliance Definition, every stack frame is 16-byte aligned. */ +#define STACK_ALIGNMENT 16 + +/** + * 16-extended-word save area for %i[0-7] and %l[0-7] registers. + */ +#define STACK_WINDOW_SAVE_AREA_SIZE (16 * STACK_ITEM_SIZE) + +/** + * Six extended words for first six arguments. + */ +#define STACK_ARG_SAVE_AREA_SIZE (6 * STACK_ITEM_SIZE) + +/** + * By convention, the actual top of the stack is %sp + STACK_BIAS. + */ +#define STACK_BIAS 2047 + +/* + * Offsets of arguments on stack. + */ +#define STACK_ARG0 0 +#define STACK_ARG1 8 +#define STACK_ARG2 16 +#define STACK_ARG3 24 +#define STACK_ARG4 32 +#define STACK_ARG5 40 +#define STACK_ARG6 48 + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/sun4u/arch.h b/bsps/sparc64/include/arch/sun4u/arch.h new file mode 100644 index 0000000000..9e883a37ff --- /dev/null +++ b/bsps/sparc64/include/arch/sun4u/arch.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** + * @file + * @brief Various sun4u-specific macros. + */ + +#ifndef KERN_sparc64_sun4u_ARCH_H_ +#define KERN_sparc64_sun4u_ARCH_H_ + +#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ +#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ +#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/asm.h b/bsps/sparc64/include/asm.h new file mode 100644 index 0000000000..bd3cc1298a --- /dev/null +++ b/bsps/sparc64/include/asm.h @@ -0,0 +1,13 @@ +/* + * asm.h + * + * Copyright 2010 Gedare Bloom + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + + +extern void halt( void ); + diff --git a/bsps/sparc64/include/boot/align.h b/bsps/sparc64/include/boot/align.h new file mode 100644 index 0000000000..96229101ed --- /dev/null +++ b/bsps/sparc64/include/boot/align.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup generic + * @{ + */ +/** @file + */ + +#ifndef BOOT_ALIGN_H_ +#define BOOT_ALIGN_H_ + +/** Align to the nearest higher address. + * + * @param addr Address or size to be aligned. + * @param align Size of alignment, must be power of 2. + */ +#define ALIGN_UP(addr, align) (((addr) + ((align) - 1)) & ~((align) - 1)) + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/boot/balloc.h b/bsps/sparc64/include/boot/balloc.h new file mode 100644 index 0000000000..8e502c0c58 --- /dev/null +++ b/bsps/sparc64/include/boot/balloc.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Modifications are made to compile for RTEMS. Move BALLOC_MAX_SIZE from + * asm.h to here. + * + */ + + +#ifndef BOOT_BALLOC_H_ +#define BOOT_BALLOC_H_ + +#include + +#define BALLOC_MAX_SIZE (128 * 1024) + +typedef struct { + uintptr_t base; + size_t size; +} ballocs_t; + +extern void balloc_init(ballocs_t *ball, uintptr_t base, uintptr_t kernel_base); +extern void *balloc(size_t size, size_t alignment); +extern void *balloc_rebase(void *ptr); + +#endif diff --git a/bsps/sparc64/include/boot/gentypes.h b/bsps/sparc64/include/boot/gentypes.h new file mode 100644 index 0000000000..a3e82d6eef --- /dev/null +++ b/bsps/sparc64/include/boot/gentypes.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup generic + * @{ + */ +/** @file + */ + +#ifndef BOOT_GENTYPES_H_ +#define BOOT_GENTYPES_H_ + +#define NULL 0 +#define false 0 +#define true 1 + +typedef unsigned long size_t; + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/boot/main.h b/bsps/sparc64/include/boot/main.h new file mode 100644 index 0000000000..5ddc814ac8 --- /dev/null +++ b/bsps/sparc64/include/boot/main.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BOOT_sparc64_MAIN_H_ +#define BOOT_sparc64_MAIN_H_ + +#include +#include +#include +#include + +#define KERNEL_VIRTUAL_ADDRESS 0x400000 + +#define TASKMAP_MAX_RECORDS 32 + +/** Size of buffer for storing task name in task_t. */ +#define BOOTINFO_TASK_NAME_BUFLEN 32 + +#define BSP_PROCESSOR 1 +#define AP_PROCESSOR 0 + +#define SUBARCH_US 1 +#define SUBARCH_US3 3 + +typedef struct { + void *addr; + uint32_t size; + char name[BOOTINFO_TASK_NAME_BUFLEN]; +} task_t; + +typedef struct { + uint32_t count; + task_t tasks[TASKMAP_MAX_RECORDS]; +} taskmap_t; + +typedef struct { + uintptr_t physmem_start; + taskmap_t taskmap; + memmap_t memmap; + ballocs_t ballocs; + ofw_tree_node_t *ofw_root; +} bootinfo_t; + +extern uint32_t silo_ramdisk_image; +extern uint32_t silo_ramdisk_size; + +extern void start(void); +extern void bootstrap(void); + +#endif diff --git a/bsps/sparc64/include/boot/ofw.h b/bsps/sparc64/include/boot/ofw.h new file mode 100644 index 0000000000..c562b675a2 --- /dev/null +++ b/bsps/sparc64/include/boot/ofw.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BOOT_OFW_H_ +#define BOOT_OFW_H_ + +#include +#include + +#define MEMMAP_MAX_RECORDS 32 +#define MAX_OFW_ARGS 12 + +#define OFW_TREE_PATH_MAX_LEN 256 +#define OFW_TREE_PROPERTY_MAX_NAMELEN 32 +#define OFW_TREE_PROPERTY_MAX_VALUELEN 64 + +typedef unative_t ofw_arg_t; +typedef unsigned int ihandle; +typedef unsigned int phandle; + +/** OpenFirmware command structure + * + */ +typedef struct { + ofw_arg_t service; /**< Command name. */ + ofw_arg_t nargs; /**< Number of in arguments. */ + ofw_arg_t nret; /**< Number of out arguments. */ + ofw_arg_t args[MAX_OFW_ARGS]; /**< List of arguments. */ +} ofw_args_t; + +typedef struct { + void *start; + uint32_t size; +} memzone_t; + +typedef struct { + uint32_t total; + uint32_t count; + memzone_t zones[MEMMAP_MAX_RECORDS]; +} memmap_t; + +typedef struct { + uint32_t info; + uint32_t addr_hi; + uint32_t addr_lo; +} pci_addr_t; + +typedef struct { + pci_addr_t addr; + uint32_t size_hi; + uint32_t size_lo; +} pci_reg_t; + +extern uintptr_t ofw_cif; + +extern phandle ofw_chosen; +extern ihandle ofw_stdout; +extern phandle ofw_root; +extern ihandle ofw_mmu; +extern phandle ofw_memory; + +extern void ofw_init(void); + +extern void ofw_write(const char *str, const int len); + +extern int ofw_get_property(const phandle device, const char *name, void *buf, const int buflen); +extern int ofw_get_proplen(const phandle device, const char *name); +extern int ofw_next_property(const phandle device, char *previous, char *buf); + +extern phandle ofw_get_child_node(const phandle node); +extern phandle ofw_get_peer_node(const phandle node); +extern phandle ofw_find_device(const char *name); + +extern int ofw_package_to_path(const phandle device, char *buf, const int buflen); + +extern int ofw(ofw_args_t *arg); +extern unsigned long ofw_call(const char *service, const int nargs, const int nret, ofw_arg_t *rets, ...); +extern void ofw_write(const char *str, const int len); +extern void ofw_read(void *str, const int len); +extern unsigned int ofw_get_address_cells(const phandle device); +extern unsigned int ofw_get_size_cells(const phandle device); +extern void *ofw_translate(const void *virt); +extern int ofw_translate_failed(ofw_arg_t flag); +extern void *ofw_claim_virt(const void *virt, const unsigned int len); +extern void *ofw_claim_phys(const void *virt, const unsigned int len); +extern void *ofw_claim_phys_any(const unsigned int len, const unsigned int alignment); +extern int ofw_map(const void *phys, const void *virt, const unsigned int size, const int mode); +extern int ofw_memmap(memmap_t *map); +extern void ofw_setup_screens(void); +extern void ofw_quiesce(void); + +#endif diff --git a/bsps/sparc64/include/boot/ofw_tree.h b/bsps/sparc64/include/boot/ofw_tree.h new file mode 100644 index 0000000000..5872ade261 --- /dev/null +++ b/bsps/sparc64/include/boot/ofw_tree.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BOOT_OFW_TREE_H_ +#define BOOT_OFW_TREE_H_ + +#include +#include + + +/** Memory representation of OpenFirmware device tree node property. */ +typedef struct { + char name[OFW_TREE_PROPERTY_MAX_NAMELEN]; + size_t size; + void *value; +} ofw_tree_property_t; + +/** Memory representation of OpenFirmware device tree node. */ +typedef struct ofw_tree_node { + struct ofw_tree_node *parent; + struct ofw_tree_node *peer; + struct ofw_tree_node *child; + + uint32_t node_handle; /**< Old OpenFirmware node handle. */ + + char *da_name; /**< Disambigued name. */ + + unsigned int properties; /**< Number of properties. */ + ofw_tree_property_t *property; + + void *device; /**< Member used solely by the kernel. */ +} ofw_tree_node_t; + +extern ofw_tree_node_t *ofw_tree_build(void); + +#endif diff --git a/bsps/sparc64/include/boot/ofwarch.h b/bsps/sparc64/include/boot/ofwarch.h new file mode 100644 index 0000000000..2d4f7643c0 --- /dev/null +++ b/bsps/sparc64/include/boot/ofwarch.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BOOT_sparc64_OFWARCH_H_ +#define BOOT_sparc64_OFWARCH_H_ + +#include "main.h" +#include "types.h" + +#define OFW_ADDRESS_CELLS 2 +#define OFW_SIZE_CELLS 2 + +extern int ofw_cpu(uint16_t mid_mask, uintptr_t physmem_start); +extern int ofw_get_physmem_start(uintptr_t *start); + +#endif diff --git a/bsps/sparc64/include/boot/register.h b/bsps/sparc64/include/boot/register.h new file mode 100644 index 0000000000..61bf34ac66 --- /dev/null +++ b/bsps/sparc64/include/boot/register.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BOOT_sparc64_REGISTER_H_ +#define BOOT_sparc64_REGISTER_H_ + +#define PSTATE_IE_BIT 2 +#define PSTATE_PRIV_BIT 4 +#define PSTATE_AM_BIT 8 + +#define ASI_ICBUS_CONFIG 0x4a +#define ICBUS_CONFIG_MID_SHIFT 17 + +#endif diff --git a/bsps/sparc64/include/boot/stack.h b/bsps/sparc64/include/boot/stack.h new file mode 100644 index 0000000000..1486dd21b4 --- /dev/null +++ b/bsps/sparc64/include/boot/stack.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BOOT_sparc64_STACK_H_ +#define BOOT_sparc64_STACK_H_ + +#define STACK_ALIGNMENT 16 +#define STACK_BIAS 2047 +#define STACK_WINDOW_SAVE_AREA_SIZE (16 * 8) + +#endif diff --git a/bsps/sparc64/include/boot/types.h b/bsps/sparc64/include/boot/types.h new file mode 100644 index 0000000000..095e25233d --- /dev/null +++ b/bsps/sparc64/include/boot/types.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BOOT_sparc64_TYPES_H_ +#define BOOT_sparc64_TYPES_H_ + +#include + +typedef signed char int8_t; + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef unsigned long uint64_t; + +typedef uint64_t uintptr_t; +typedef uint64_t unative_t; + +#endif diff --git a/bsps/sparc64/include/genarch/ofw/ofw_tree.h b/bsps/sparc64/include/genarch/ofw/ofw_tree.h new file mode 100644 index 0000000000..f62d545527 --- /dev/null +++ b/bsps/sparc64/include/genarch/ofw/ofw_tree.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef KERN_OFW_TREE_H_ +#define KERN_OFW_TREE_H_ + +#include +#include + +#define OFW_TREE_PROPERTY_MAX_NAMELEN 32 + +/** Memory representation of OpenFirmware device tree node property. */ +typedef struct { + char name[OFW_TREE_PROPERTY_MAX_NAMELEN]; + size_t size; + void *value; +} ofw_tree_property_t; + +/** Memory representation of OpenFirmware device tree node. */ +typedef struct ofw_tree_node { + struct ofw_tree_node *parent; + struct ofw_tree_node *peer; + struct ofw_tree_node *child; + + uint32_t node_handle; /**< Old OpenFirmware node handle. */ + + char *da_name; /**< Disambigued name. */ + + unsigned int properties; /**< Number of properties. */ + ofw_tree_property_t *property; + + /** + * Pointer to a structure representing respective device. + * Its semantics is device dependent. + */ + void *device; +} ofw_tree_node_t; + +/* Walker for visiting OpenFirmware device tree nodes. */ +typedef bool (* ofw_tree_walker_t)(ofw_tree_node_t *, void *); + +extern void ofw_tree_init(ofw_tree_node_t *); +extern void ofw_tree_print(void); + +extern const char *ofw_tree_node_name(const ofw_tree_node_t *); +extern ofw_tree_node_t *ofw_tree_lookup(const char *); +extern ofw_tree_property_t *ofw_tree_getprop(const ofw_tree_node_t *, + const char *); +extern void ofw_tree_walk_by_device_type(const char *, ofw_tree_walker_t, + void *); + +extern ofw_tree_node_t *ofw_tree_find_child(ofw_tree_node_t *, const char *); +extern ofw_tree_node_t *ofw_tree_find_child_by_device_type(ofw_tree_node_t *, + const char *); + +extern ofw_tree_node_t *ofw_tree_find_peer_by_device_type(ofw_tree_node_t *, + const char *); +extern ofw_tree_node_t *ofw_tree_find_peer_by_name(ofw_tree_node_t *, + const char *); +extern ofw_tree_node_t *ofw_tree_find_node_by_handle(ofw_tree_node_t *, + uint32_t); + +#endif diff --git a/bsps/sparc64/include/kernel/align.h b/bsps/sparc64/include/kernel/align.h new file mode 100644 index 0000000000..6003ea9c4e --- /dev/null +++ b/bsps/sparc64/include/kernel/align.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup generic + * @ingroup others + * @{ + */ +/** + * @file + * @brief Macros for making values and addresses aligned. + */ + +#ifndef KERN_ALIGN_H_ +#define KERN_ALIGN_H_ + +/** Align to the nearest lower address. + * + * @param s Address or size to be aligned. + * @param a Size of alignment, must be power of 2. + */ +#define ALIGN_DOWN(s, a) ((s) & ~((a) - 1)) + + +/** Align to the nearest higher address. + * + * @param s Address or size to be aligned. + * @param a Size of alignment, must be power of 2. + */ +#define ALIGN_UP(s, a) (((s) + ((a) - 1)) & ~((a) - 1)) + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/traptable.h b/bsps/sparc64/include/traptable.h new file mode 100644 index 0000000000..353c60d79c --- /dev/null +++ b/bsps/sparc64/include/traptable.h @@ -0,0 +1,21 @@ +/* + * traptable.h + * + * Copyright 2010 Gedare Bloom + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* This file can be included by assembly code */ + +#define ENTRY_SIZE (32) + +#define TABLE_SIZE (1024*ENTRY_SIZE) + +#ifndef ASM +extern void* real_trap_table; +extern void* trap_table[TABLE_SIZE]; +#endif + diff --git a/bsps/sparc64/niagara/headers.am b/bsps/sparc64/niagara/headers.am new file mode 100644 index 0000000000..24d001f919 --- /dev/null +++ b/bsps/sparc64/niagara/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/sparc64/niagara/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/sparc64/niagara/include/tm27.h diff --git a/bsps/sparc64/niagara/include/bsp.h b/bsps/sparc64/niagara/include/bsp.h new file mode 100644 index 0000000000..81058270a9 --- /dev/null +++ b/bsps/sparc64/niagara/include/bsp.h @@ -0,0 +1,41 @@ +/* bsp.h + * + * This include file contains all SPARC64 simulator definitions. + * + * COPYRIGHT (c) 1989-1998. On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SPARC64_NIAGARA_BSP_H +#define LIBBSP_SPARC64_NIAGARA_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* support for simulated clock tick */ +/* +void *clock_driver_sim_idle_body(uintptr_t); +#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body +*/ + +/* this should be defined somewhere */ +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc64/niagara/include/tm27.h b/bsps/sparc64/niagara/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/sparc64/niagara/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/sparc64/usiii/headers.am b/bsps/sparc64/usiii/headers.am new file mode 100644 index 0000000000..06129f2596 --- /dev/null +++ b/bsps/sparc64/usiii/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/sparc64/usiii/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/sparc64/usiii/include/tm27.h diff --git a/bsps/sparc64/usiii/include/bsp.h b/bsps/sparc64/usiii/include/bsp.h new file mode 100644 index 0000000000..8051db3987 --- /dev/null +++ b/bsps/sparc64/usiii/include/bsp.h @@ -0,0 +1,42 @@ +/* bsp.h + * + * This include file contains all SPARC64 simulator definitions. + * + * COPYRIGHT (c) 1989-1998. On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef LIBBSP_SPARC64_USIII_BSP_H +#define LIBBSP_SPARC64_USIII_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* support for simulated clock tick */ +/* +void *clock_driver_sim_idle_body(uintptr_t); +#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body +*/ + +/* this should be defined somewhere */ +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sparc64/usiii/include/tm27.h b/bsps/sparc64/usiii/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/sparc64/usiii/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/v850/gdbv850sim/headers.am b/bsps/v850/gdbv850sim/headers.am new file mode 100644 index 0000000000..d8acdece23 --- /dev/null +++ b/bsps/v850/gdbv850sim/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/v850/gdbv850sim/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/v850/gdbv850sim/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/v850/gdbv850sim/include/bsp/syscall.h diff --git a/bsps/v850/gdbv850sim/include/bsp.h b/bsps/v850/gdbv850sim/include/bsp.h new file mode 100644 index 0000000000..ac8b43024f --- /dev/null +++ b/bsps/v850/gdbv850sim/include/bsp.h @@ -0,0 +1,35 @@ +/* + * This include file contains some definitions specific to the + * GDB simulator in gdb. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_V850_GDBV850SIM_BSP_H +#define LIBBSP_V850_GDBV850SIM_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* support for simulated clock tick */ +void *clock_driver_sim_idle_body(uintptr_t); +#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/v850/gdbv850sim/include/bsp/syscall.h b/bsps/v850/gdbv850sim/include/bsp/syscall.h new file mode 100644 index 0000000000..d8eebdd3f9 --- /dev/null +++ b/bsps/v850/gdbv850sim/include/bsp/syscall.h @@ -0,0 +1,47 @@ +/* from libgloss/v850 */ +#ifndef _SYS_SYSCALL_H_ +#define _SYS_SYSCALL_H_ + +#ifndef ASM +extern int __trap0 (int function, int p1, int p2, int p3); + +#define TRAP0(f, p1, p2, p3) __trap0(f, (int)(p1), (int)(p2), (int)(p3)) +#endif + +#define SYS_exit 1 +#define SYS_fork 2 + +#define SYS_read 3 +#define SYS_write 4 +#define SYS_open 5 +#define SYS_close 6 +#define SYS_wait4 7 +#define SYS_creat 8 +#define SYS_link 9 +#define SYS_unlink 10 +#define SYS_execv 11 +#define SYS_chdir 12 +#define SYS_mknod 14 +#define SYS_chmod 15 +#define SYS_chown 16 +#define SYS_lseek 19 +#define SYS_getpid 20 +#define SYS_isatty 21 +#define SYS_fstat 22 +#define SYS_time 23 + + +#define SYS_ARG 24 +#define SYS_stat 38 + + +#define SYS_pipe 42 +#define SYS_execve 59 +#define SYS_times 43 +#define SYS_gettimeofday 116 +#define SYS_rename 134 + +#define SYS_utime 201 /* not really a system call */ +#define SYS_wait 202 /* nor is this */ + +#endif diff --git a/bsps/v850/gdbv850sim/include/tm27.h b/bsps/v850/gdbv850sim/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/v850/gdbv850sim/include/tm27.h @@ -0,0 +1 @@ +#include -- cgit v1.2.3